From f2b214b0dff95d6bb79cbb5b6ff5ba9d90f655c9 Mon Sep 17 00:00:00 2001 From: oharboe Date: Wed, 2 Jan 2008 21:52:27 +0000 Subject: Initial import from www.ecosforge.net --- .project | 11 + zpu/.project | 11 + zpu/COPYING | 12 + zpu/ChangeLog | 11 + zpu/STATUS | 11 + zpu/docs/presentations/zpu.odp | Bin 0 -> 60715 bytes zpu/docs/presentations/zpudemo.odp | Bin 0 -> 222644 bytes zpu/docs/zpupresentation.odp | Bin 0 -> 78518 bytes zpu/docs/zpupresentation.ppt | Bin 0 -> 150016 bytes zpu/docs/zpupresentation_old.odt | Bin 0 -> 126772 bytes zpu/docs/zpuprotoarch.odt | Bin 0 -> 23961 bytes zpu/hdl/example/helloworld.vhd | 12506 +++++++++++++++++++ zpu/hdl/example/io.vhd | 97 + zpu/hdl/example/log.txt | 15 + zpu/hdl/example/sim_fpga_top.vhd | 179 + zpu/hdl/example/simzpu.do | 29 + zpu/hdl/example/zpu_config.vhd | 20 + zpu/hdl/index.html | 47 + zpu/hdl/wishbone/wishbone_pkg.vhd | 52 + zpu/hdl/wishbone/zpu_system.vhd | 71 + zpu/hdl/wishbone/zpu_wb_bridge.vhd | 49 + zpu/hdl/zpu3/src/.cvsignore | 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b/.project new file mode 100644 index 0000000..bdcda92 --- /dev/null +++ b/.project @@ -0,0 +1,11 @@ + + + oczpu + + + + + + + + diff --git a/zpu/.project b/zpu/.project new file mode 100644 index 0000000..55b1cb8 --- /dev/null +++ b/zpu/.project @@ -0,0 +1,11 @@ + + + zpu + + + + + + + + diff --git a/zpu/COPYING b/zpu/COPYING new file mode 100644 index 0000000..96b27d3 --- /dev/null +++ b/zpu/COPYING @@ -0,0 +1,12 @@ +About ZPU licensing: + +Licensing is not entirely fleshed out yet(there are many parts to a +soft CPU), but the license for the HDL will be BSD/eCos-like to be +friendly towards commercially oriented projects, however the +architecture, documentation and tools will be GPL. This means that all +updates to the architecture must be shared, but actual +implementations(which are small and can be very project speific) can +be friendly towards commercial considerations. + + +Patches to update files w/correct licensing info will be most appreciated! diff --git a/zpu/ChangeLog b/zpu/ChangeLog new file mode 100644 index 0000000..827ede8 --- /dev/null +++ b/zpu/ChangeLog @@ -0,0 +1,11 @@ +2007-09-11 Øyvind Harboe + * Cleaning up zpu/hdl/example. simzpu.do file now uses zpu4/src files instead + of duplicating them. Hello world simzpu.do now works out of the box. +2007-09-10 Øyvind Harboe + * Cleaning up .html files a bit. + * retired zpututorial.odt. +2007-08-04 Øyvind Harboe + * small ZPU hello world example now simulates with valid log.txt/trace.txt file. + * Until files are properly organized, ChangeLog will not be kept up to date. +2007-08-03 Øyvind Harboe + * Starting to commit files diff --git a/zpu/STATUS b/zpu/STATUS new file mode 100644 index 0000000..e28f191 --- /dev/null +++ b/zpu/STATUS @@ -0,0 +1,11 @@ +The current state of the ZPU: + +- Patches welcome! +- Zylin is rummaging up the various files that might be of interest + to the open source ZPU project. +- The ZPU, GCC toolchain and HDL works. Zylin eCosBoard 1.1 ships w/a + ZPU(see http://www.zylin.com), if you need a development board before + implementing on your own system. +- The docs leave a lot to be desired at this point. +- Licensing needs to be ironed out. After which lots of files will have + to be updated, strictly speaking. Patches welcome! diff --git a/zpu/docs/presentations/zpu.odp b/zpu/docs/presentations/zpu.odp new file mode 100644 index 0000000..e2a6554 Binary files /dev/null and b/zpu/docs/presentations/zpu.odp differ diff --git a/zpu/docs/presentations/zpudemo.odp b/zpu/docs/presentations/zpudemo.odp new file mode 100644 index 0000000..d0085a8 Binary files /dev/null and b/zpu/docs/presentations/zpudemo.odp differ diff --git a/zpu/docs/zpupresentation.odp b/zpu/docs/zpupresentation.odp new file mode 100644 index 0000000..28d9a7b Binary files /dev/null and b/zpu/docs/zpupresentation.odp differ diff --git a/zpu/docs/zpupresentation.ppt b/zpu/docs/zpupresentation.ppt new file mode 100644 index 0000000..100c4a4 Binary files /dev/null and b/zpu/docs/zpupresentation.ppt differ diff --git a/zpu/docs/zpupresentation_old.odt b/zpu/docs/zpupresentation_old.odt new file mode 100644 index 0000000..53e1f98 Binary files /dev/null and b/zpu/docs/zpupresentation_old.odt differ diff --git a/zpu/docs/zpuprotoarch.odt b/zpu/docs/zpuprotoarch.odt new file mode 100644 index 0000000..67a4171 Binary files /dev/null and b/zpu/docs/zpuprotoarch.odt differ diff --git a/zpu/hdl/example/helloworld.vhd b/zpu/hdl/example/helloworld.vhd new file mode 100644 index 0000000..9c99259 --- /dev/null +++ b/zpu/hdl/example/helloworld.vhd @@ -0,0 +1,12506 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity dualport_ram is +port (clk : in std_logic; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memAWrite : in std_logic_vector(wordSize-1 downto 0); + memARead : out std_logic_vector(wordSize-1 downto 0); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memBWrite : in std_logic_vector(wordSize-1 downto 0); + memBRead : out std_logic_vector(wordSize-1 downto 0)); +end dualport_ram; + +architecture dualport_ram_arch of dualport_ram is + + +type ram_type is array(0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); + +shared variable ram : ram_type := +( +0 => x"0b0b0b0b", +1 => x"82700b0b", +2 => x"82f4e00c", +3 => x"3a0b0b81", +4 => x"e48c0400", +5 => x"00000000", +6 => x"00000000", +7 => x"00000000", +8 => x"80088408", +9 => x"88080b0b", +10 => x"81e4fd2d", +11 => x"880c840c", +12 => x"800c0400", +13 => x"00000000", +14 => x"00000000", +15 => x"00000000", +16 => x"71fd0608", +17 => x"72830609", +18 => x"81058205", +19 => x"832b2a83", +20 => x"ffff0652", +21 => x"04000000", +22 => x"00000000", +23 => x"00000000", +24 => x"71fd0608", +25 => x"83ffff73", +26 => x"83060981", +27 => x"05820583", +28 => x"2b2b0906", +29 => x"7383ffff", +30 => x"0b0b0b0b", +31 => x"83a70400", +32 => x"72098105", +33 => x"72057373", +34 => x"09060906", +35 => x"73097306", +36 => x"070a8106", +37 => x"53510400", +38 => x"00000000", +39 => x"00000000", +40 => x"72722473", +41 => x"732e0753", +42 => x"51040000", +43 => x"00000000", +44 => x"00000000", +45 => x"00000000", +46 => x"00000000", +47 => x"00000000", +48 => x"71737109", +49 => x"71068106", +50 => x"30720a10", +51 => x"0a720a10", +52 => x"0a31050a", +53 => x"81065151", +54 => x"53510400", +55 => x"00000000", +56 => x"72722673", +57 => x"732e0753", +58 => x"51040000", +59 => x"00000000", +60 => x"00000000", +61 => x"00000000", +62 => x"00000000", +63 => x"00000000", +64 => x"00000000", +65 => x"00000000", +66 => x"00000000", +67 => x"00000000", +68 => x"00000000", +69 => x"00000000", +70 => x"00000000", +71 => x"00000000", +72 => x"0b0b0b88", +73 => x"c9040000", +74 => x"00000000", +75 => x"00000000", +76 => x"00000000", +77 => x"00000000", +78 => x"00000000", +79 => x"00000000", +80 => x"720a722b", +81 => x"0a535104", +82 => x"00000000", +83 => x"00000000", +84 => x"00000000", +85 => x"00000000", +86 => x"00000000", +87 => x"00000000", +88 => x"72729f06", +89 => x"0981050b", +90 => x"0b0b88ac", +91 => x"05040000", +92 => x"00000000", +93 => x"00000000", +94 => x"00000000", +95 => x"00000000", +96 => x"72722aff", +97 => x"739f062a", +98 => x"0974090a", +99 => x"8106ff05", +100 => x"06075351", +101 => x"04000000", +102 => x"00000000", +103 => x"00000000", +104 => x"71715351", +105 => x"020d0406", +106 => x"73830609", +107 => x"81058205", +108 => x"832b0b2b", +109 => x"0772fc06", +110 => x"0c515104", +111 => x"00000000", +112 => x"72098105", +113 => x"72050970", +114 => x"81050906", +115 => x"0a810653", +116 => x"51040000", +117 => x"00000000", +118 => x"00000000", +119 => x"00000000", +120 => x"72098105", +121 => x"72050970", +122 => x"81050906", +123 => x"0a098106", +124 => x"53510400", +125 => x"00000000", +126 => x"00000000", +127 => x"00000000", +128 => x"71098105", +129 => x"52040000", +130 => x"00000000", +131 => x"00000000", +132 => x"00000000", +133 => x"00000000", +134 => x"00000000", +135 => x"00000000", +136 => x"72720981", +137 => x"05055351", +138 => x"04000000", +139 => x"00000000", +140 => x"00000000", +141 => x"00000000", +142 => x"00000000", +143 => x"00000000", +144 => x"72097206", +145 => x"73730906", +146 => x"07535104", +147 => x"00000000", +148 => x"00000000", +149 => x"00000000", +150 => x"00000000", +151 => x"00000000", +152 => x"71fc0608", +153 => x"72830609", +154 => x"81058305", +155 => x"1010102a", +156 => x"81ff0652", +157 => x"04000000", +158 => x"00000000", +159 => x"00000000", +160 => x"71fc0608", +161 => x"0b0b82f4", +162 => x"cc738306", +163 => x"10100508", +164 => x"060b0b0b", +165 => x"88af0400", +166 => x"00000000", +167 => x"00000000", +168 => x"80088408", +169 => x"88087575", +170 => x"0b0b0b8e", +171 => x"c42d5050", +172 => x"80085688", +173 => x"0c840c80", +174 => x"0c510400", +175 => x"00000000", +176 => x"80088408", +177 => x"88087575", +178 => x"0b0b0b90", +179 => x"8d2d5050", +180 => x"80085688", +181 => x"0c840c80", +182 => x"0c510400", +183 => x"00000000", +184 => x"72097081", +185 => x"0509060a", +186 => x"8106ff05", +187 => x"70547106", +188 => x"73097274", +189 => x"05ff0506", +190 => x"07515151", +191 => x"04000000", +192 => x"72097081", +193 => x"0509060a", +194 => x"098106ff", +195 => x"05705471", +196 => x"06730972", +197 => x"7405ff05", +198 => x"06075151", +199 => x"51040000", +200 => x"05ff0504", +201 => x"00000000", +202 => x"00000000", +203 => x"00000000", +204 => x"00000000", +205 => x"00000000", +206 => x"00000000", +207 => x"00000000", +208 => x"810b0b0b", +209 => x"82f4dc0c", +210 => x"51040000", +211 => x"00000000", +212 => x"00000000", +213 => x"00000000", +214 => x"00000000", +215 => x"00000000", +216 => x"71810552", +217 => x"04000000", +218 => x"00000000", +219 => x"00000000", +220 => x"00000000", +221 => x"00000000", +222 => x"00000000", +223 => x"00000000", +224 => x"00000000", +225 => x"00000000", +226 => x"00000000", +227 => x"00000000", +228 => x"00000000", +229 => x"00000000", +230 => x"00000000", +231 => x"00000000", +232 => x"02840572", +233 => x"10100552", +234 => x"04000000", +235 => x"00000000", +236 => x"00000000", +237 => x"00000000", +238 => x"00000000", +239 => x"00000000", +240 => x"00000000", +241 => x"00000000", +242 => x"00000000", +243 => x"00000000", +244 => x"00000000", +245 => x"00000000", +246 => x"00000000", +247 => x"00000000", +248 => x"717105ff", +249 => x"05715351", +250 => x"020d0400", +251 => x"00000000", +252 => x"00000000", +253 => x"00000000", +254 => x"00000000", +255 => x"00000000", +256 => x"0b0b0b83", +257 => x"e93f0b0b", +258 => x"82e4cc3f", +259 => x"04101010", +260 => x"10101010", +261 => x"10101010", +262 => x"10101010", +263 => x"10101010", +264 => x"10101010", +265 => x"10101010", +266 => x"10101010", +267 => x"53510473", +268 => x"81ff0673", +269 => x"83060981", +270 => x"05830510", +271 => x"10102b07", +272 => x"72fc060c", +273 => x"5151043c", +274 => x"04727280", +275 => x"728106ff", +276 => x"05097206", +277 => x"05711052", +278 => x"720a100a", +279 => x"5372ed38", +280 => x"51515351", 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x"00000000", +12146 => x"00000000", +12147 => x"00000000", +12148 => x"00000000", +12149 => x"00000000", +12150 => x"00000000", +12151 => x"00000000", +12152 => x"00000000", +12153 => x"00000000", +12154 => x"00000000", +12155 => x"43000000", +12156 => x"00000000", +12157 => x"00000000", +12158 => x"00000000", +12159 => x"00000000", +12160 => x"00000000", +12161 => x"00000001", +12162 => x"0000b8cc", +12163 => x"00000000", +12164 => x"00000000", +12165 => x"00000000", +12166 => x"00000000", +12167 => x"00000000", +12168 => x"00000000", +12169 => x"00000000", +12170 => x"00000000", +12171 => x"00000000", +12172 => x"00000000", +12173 => x"00000000", +12174 => x"00000000", +12175 => x"ffffffff", +12176 => x"00000000", +12177 => x"00020000", +12178 => x"00000000", +12179 => x"00000000", +12180 => x"0000be48", +12181 => x"0000be48", +12182 => x"0000be50", +12183 => x"0000be50", +12184 => x"0000be58", +12185 => x"0000be58", +12186 => x"0000be60", +12187 => x"0000be60", +12188 => x"0000be68", +12189 => x"0000be68", +12190 => x"0000be70", +12191 => x"0000be70", +12192 => x"0000be78", +12193 => x"0000be78", +12194 => x"0000be80", +12195 => x"0000be80", +12196 => x"0000be88", +12197 => x"0000be88", +12198 => x"0000be90", +12199 => x"0000be90", +12200 => x"0000be98", +12201 => x"0000be98", +12202 => x"0000bea0", +12203 => x"0000bea0", +12204 => x"0000bea8", +12205 => x"0000bea8", +12206 => x"0000beb0", +12207 => x"0000beb0", +12208 => x"0000beb8", +12209 => x"0000beb8", +12210 => x"0000bec0", +12211 => x"0000bec0", +12212 => x"0000bec8", +12213 => x"0000bec8", +12214 => x"0000bed0", +12215 => x"0000bed0", +12216 => x"0000bed8", +12217 => x"0000bed8", +12218 => x"0000bee0", +12219 => x"0000bee0", +12220 => x"0000bee8", +12221 => x"0000bee8", +12222 => x"0000bef0", +12223 => x"0000bef0", +12224 => x"0000bef8", +12225 => x"0000bef8", +12226 => x"0000bf00", +12227 => x"0000bf00", +12228 => x"0000bf08", +12229 => x"0000bf08", +12230 => x"0000bf10", +12231 => x"0000bf10", +12232 => x"0000bf18", +12233 => x"0000bf18", +12234 => x"0000bf20", +12235 => x"0000bf20", +12236 => x"0000bf28", +12237 => x"0000bf28", +12238 => x"0000bf30", +12239 => x"0000bf30", +12240 => x"0000bf38", +12241 => x"0000bf38", +12242 => x"0000bf40", +12243 => x"0000bf40", +12244 => x"0000bf48", +12245 => x"0000bf48", +12246 => x"0000bf50", +12247 => x"0000bf50", +12248 => x"0000bf58", +12249 => x"0000bf58", +12250 => x"0000bf60", +12251 => x"0000bf60", +12252 => x"0000bf68", +12253 => x"0000bf68", +12254 => x"0000bf70", +12255 => x"0000bf70", +12256 => x"0000bf78", +12257 => x"0000bf78", +12258 => x"0000bf80", +12259 => x"0000bf80", +12260 => x"0000bf88", +12261 => x"0000bf88", +12262 => x"0000bf90", +12263 => x"0000bf90", +12264 => x"0000bf98", +12265 => x"0000bf98", +12266 => x"0000bfa0", +12267 => x"0000bfa0", +12268 => x"0000bfa8", +12269 => x"0000bfa8", +12270 => x"0000bfb0", +12271 => x"0000bfb0", +12272 => x"0000bfb8", +12273 => x"0000bfb8", +12274 => x"0000bfc0", +12275 => x"0000bfc0", +12276 => x"0000bfc8", +12277 => x"0000bfc8", +12278 => x"0000bfd0", +12279 => x"0000bfd0", +12280 => x"0000bfd8", +12281 => x"0000bfd8", +12282 => x"0000bfe0", +12283 => x"0000bfe0", +12284 => x"0000bfe8", +12285 => x"0000bfe8", +12286 => x"0000bff0", +12287 => x"0000bff0", +12288 => x"0000bff8", +12289 => x"0000bff8", +12290 => x"0000c000", +12291 => x"0000c000", +12292 => x"0000c008", +12293 => x"0000c008", +12294 => x"0000c010", +12295 => x"0000c010", +12296 => x"0000c018", +12297 => x"0000c018", +12298 => x"0000c020", +12299 => x"0000c020", +12300 => x"0000c028", +12301 => x"0000c028", +12302 => x"0000c030", +12303 => x"0000c030", +12304 => x"0000c038", +12305 => x"0000c038", +12306 => x"0000c040", +12307 => x"0000c040", +12308 => x"0000c048", +12309 => x"0000c048", +12310 => x"0000c050", +12311 => x"0000c050", +12312 => x"0000c058", +12313 => x"0000c058", +12314 => x"0000c060", +12315 => x"0000c060", +12316 => x"0000c068", +12317 => x"0000c068", +12318 => x"0000c070", +12319 => x"0000c070", +12320 => x"0000c078", +12321 => x"0000c078", +12322 => x"0000c080", +12323 => x"0000c080", +12324 => x"0000c088", +12325 => x"0000c088", +12326 => x"0000c090", +12327 => x"0000c090", +12328 => x"0000c098", +12329 => x"0000c098", +12330 => x"0000c0a0", +12331 => x"0000c0a0", +12332 => x"0000c0a8", +12333 => x"0000c0a8", +12334 => x"0000c0b0", +12335 => x"0000c0b0", +12336 => x"0000c0b8", +12337 => x"0000c0b8", +12338 => x"0000c0c0", +12339 => x"0000c0c0", +12340 => x"0000c0c8", +12341 => x"0000c0c8", +12342 => x"0000c0d0", +12343 => x"0000c0d0", +12344 => x"0000c0d8", +12345 => x"0000c0d8", +12346 => x"0000c0e0", +12347 => x"0000c0e0", +12348 => x"0000c0e8", +12349 => x"0000c0e8", +12350 => x"0000c0f0", +12351 => x"0000c0f0", +12352 => x"0000c0f8", +12353 => x"0000c0f8", +12354 => x"0000c100", +12355 => x"0000c100", +12356 => x"0000c108", +12357 => x"0000c108", +12358 => x"0000c110", +12359 => x"0000c110", +12360 => x"0000c118", +12361 => x"0000c118", +12362 => x"0000c120", +12363 => x"0000c120", +12364 => x"0000c128", +12365 => x"0000c128", +12366 => x"0000c130", +12367 => x"0000c130", +12368 => x"0000c138", +12369 => x"0000c138", +12370 => x"0000c140", +12371 => x"0000c140", +12372 => x"0000c148", +12373 => x"0000c148", +12374 => x"0000c150", +12375 => x"0000c150", +12376 => x"0000c158", +12377 => x"0000c158", +12378 => x"0000c160", +12379 => x"0000c160", +12380 => x"0000c168", +12381 => x"0000c168", +12382 => x"0000c170", +12383 => x"0000c170", +12384 => x"0000c178", +12385 => x"0000c178", +12386 => x"0000c180", +12387 => x"0000c180", +12388 => x"0000c188", +12389 => x"0000c188", +12390 => x"0000c190", +12391 => x"0000c190", +12392 => x"0000c198", +12393 => x"0000c198", +12394 => x"0000c1a0", +12395 => x"0000c1a0", +12396 => x"0000c1a8", +12397 => x"0000c1a8", +12398 => x"0000c1b0", +12399 => x"0000c1b0", +12400 => x"0000c1b8", +12401 => x"0000c1b8", +12402 => x"0000c1c0", +12403 => x"0000c1c0", +12404 => x"0000c1c8", +12405 => x"0000c1c8", +12406 => x"0000c1d0", +12407 => x"0000c1d0", +12408 => x"0000c1d8", +12409 => x"0000c1d8", +12410 => x"0000c1e0", +12411 => x"0000c1e0", +12412 => x"0000c1e8", +12413 => x"0000c1e8", +12414 => x"0000c1f0", +12415 => x"0000c1f0", +12416 => x"0000c1f8", +12417 => x"0000c1f8", +12418 => x"0000c200", +12419 => x"0000c200", +12420 => x"0000c208", +12421 => x"0000c208", +12422 => x"0000c210", +12423 => x"0000c210", +12424 => x"0000c218", +12425 => x"0000c218", +12426 => x"0000c220", +12427 => x"0000c220", +12428 => x"0000c228", +12429 => x"0000c228", +12430 => x"0000c230", +12431 => x"0000c230", +12432 => x"0000c238", +12433 => x"0000c238", +12434 => x"0000c240", +12435 => x"0000c240", +12436 => x"0000ba2c", +12437 => x"ffffffff", +12438 => x"00000000", +12439 => x"ffffffff", +12440 => x"00000000", + others => x"00000000" +); + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then + report "write collision" severity failure; + end if; + + if (memAWriteEnable = '1') then + ram(conv_integer(memAAddr)) := memAWrite; + memARead <= memAWrite; + else + memARead <= ram(conv_integer(memAAddr)); + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (memBWriteEnable = '1') then + ram(conv_integer(memBAddr)) := memBWrite; + memBRead <= memBWrite; + else + memBRead <= ram(conv_integer(memBAddr)); + end if; + end if; +end process; + + + + +end dualport_ram_arch; diff --git a/zpu/hdl/example/io.vhd b/zpu/hdl/example/io.vhd new file mode 100644 index 0000000..7dbe36f --- /dev/null +++ b/zpu/hdl/example/io.vhd @@ -0,0 +1,97 @@ +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +use std.textio.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; +use work.txt_util.all; + +entity zpu_io is + generic ( + log_file: string := "log.txt" + ); + port( + clk : in std_logic; + areset : in std_logic; + busy : out std_logic; + writeEnable : in std_logic; + readEnable : in std_logic; + write : in std_logic_vector(wordSize-1 downto 0); + read : out std_logic_vector(wordSize-1 downto 0); + addr : in std_logic_vector(maxAddrBit downto minAddrBit) + ); +end zpu_io; + + +architecture behave of zpu_io is + + + +signal timer_read : std_logic_vector(7 downto 0); +--signal timer_write : std_logic_vector(7 downto 0); +signal timer_we : std_logic; + +signal serving : std_logic; + +file l_file : TEXT open write_mode is log_file; + +begin + + + timerinst: timer port map ( + clk => clk, + areset => areset, + we => timer_we, + din => write(7 downto 0), + adr => addr(4 downto 2), + dout => timer_read); + + busy <= writeEnable or readEnable; + timer_we <= writeEnable and addr(12); + + process(areset, clk) + begin + if (areset = '1') then +-- timer_we <= '0'; + elsif (clk'event and clk = '1') then +-- timer_we <= '0'; + if writeEnable = '1' then + -- external interface + if addr=x"2028003" then + -- Write to UART + -- report "" & character'image(conv_integer(memBint)) severity note; + print(l_file, character'val(conv_integer(write))); + elsif addr(12)='1' then +-- report "xxx" severity failure; +-- timer_we <= '1'; + else + print(l_file, character'val(conv_integer(write))); + report "Illegal IO write" severity warning; + end if; + + end if; + read <= (others => '0'); + if (readEnable = '1') then + if addr=x"1001" then + read <= (0=>'1', others => '0'); -- recieve empty + elsif addr(12)='1' then + read(7 downto 0) <= timer_read; + elsif addr(11)='1' then + read(7 downto 0) <= ZPU_Frequency; + elsif addr=x"2028003" then + read <= (others => '0'); + else + read <= (others => '0'); + read(8) <= '1'; + report "Illegal IO read" severity warning; + end if; + end if; + end if; + end process; + + +end behave; + diff --git a/zpu/hdl/example/log.txt b/zpu/hdl/example/log.txt new file mode 100644 index 0000000..6954a81 --- /dev/null +++ b/zpu/hdl/example/log.txt @@ -0,0 +1,15 @@ +H +e +l +l +o + +w +o +r +l +d +! + + + diff --git a/zpu/hdl/example/sim_fpga_top.vhd b/zpu/hdl/example/sim_fpga_top.vhd new file mode 100644 index 0000000..b51fea0 --- /dev/null +++ b/zpu/hdl/example/sim_fpga_top.vhd @@ -0,0 +1,179 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 20:15:31 04/14/05 +-- Design Name: +-- Module Name: fpga_top - behave +-- Project Name: +-- Target Device: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity fpga_top is +end fpga_top; + +architecture behave of fpga_top is + + +signal clk : std_logic; + +signal areset : std_logic; + + +component zpu_io is + generic ( + log_file: string := "log.txt" + ); + port( + clk : in std_logic; + areset : in std_logic; + busy : out std_logic; + writeEnable : in std_logic; + readEnable : in std_logic; + write : in std_logic_vector(wordSize-1 downto 0); + read : out std_logic_vector(wordSize-1 downto 0); + addr : in std_logic_vector(maxAddrBit downto minAddrBit) + ); +end component; + + + + + +signal mem_busy : std_logic; +signal mem_read : std_logic_vector(wordSize-1 downto 0); +signal mem_write : std_logic_vector(wordSize-1 downto 0); +signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); +signal mem_writeEnable : std_logic; +signal mem_readEnable : std_logic; +signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + +signal enable : std_logic; + +signal dram_mem_busy : std_logic; +signal dram_mem_read : std_logic_vector(wordSize-1 downto 0); +signal dram_mem_write : std_logic_vector(wordSize-1 downto 0); +signal dram_mem_writeEnable : std_logic; +signal dram_mem_readEnable : std_logic; +signal dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + + +signal io_busy : std_logic; + +signal io_mem_read : std_logic_vector(wordSize-1 downto 0); +signal io_mem_writeEnable : std_logic; +signal io_mem_readEnable : std_logic; + + +signal dram_ready : std_logic; +signal io_ready : std_logic; +signal io_reading : std_logic; + + +signal break : std_logic; + +begin + poweronreset: roc port map (O => areset); + + + + zpu: zpu_core port map ( + clk => clk , + areset => areset, + enable => enable, + in_mem_busy => mem_busy, + mem_read => mem_read, + mem_write => mem_write, + out_mem_addr => mem_addr, + out_mem_writeEnable => mem_writeEnable, + out_mem_readEnable => mem_readEnable, + mem_writeMask => mem_writeMask, + interrupt => '0', + break => break); + + + ioMap: zpu_io port map ( + clk => clk, + areset => areset, + busy => io_busy, + writeEnable => io_mem_writeEnable, + readEnable => io_mem_readEnable, + write => mem_write, + read => io_mem_read, + addr => mem_addr(maxAddrBit downto minAddrBit) + ); + + dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit); + dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit); + io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit); + io_mem_readEnable <= mem_readEnable and mem_addr(ioBit); + mem_busy <= io_busy; + + + + -- Memory reads either come from IO or DRAM. We need to pick the right one. + memorycontrol: + process(dram_mem_read, dram_ready, io_ready, io_mem_read) + begin + mem_read <= (others => 'U'); + if dram_ready='1' then + mem_read <= dram_mem_read; + end if; + + if io_ready='1' then + mem_read <= (others => '0'); + mem_read <= io_mem_read; + end if; + end process; + + + io_ready <= (io_reading or io_mem_readEnable) and not io_busy; + + memoryControlSync: + process(clk, areset) + begin + if areset = '1' then + enable <= '0'; + io_reading <= '0'; + dram_ready <= '0'; + elsif (clk'event and clk = '1') then + enable <= '1'; + io_reading <= io_busy or io_mem_readEnable; + dram_ready<=dram_mem_readEnable; + + end if; + end process; + + -- wiggle the clock @ 100MHz + clock : PROCESS + begin + clk <= '0'; + wait for 5 ns; + clk <= '1'; + wait for 5 ns; + end PROCESS clock; + + +end behave; diff --git a/zpu/hdl/example/simzpu.do b/zpu/hdl/example/simzpu.do new file mode 100644 index 0000000..083187f --- /dev/null +++ b/zpu/hdl/example/simzpu.do @@ -0,0 +1,29 @@ +# Xilinx WebPack modelsim script +# +# 1. Change directory to this source directory +# cd C:/workspace/zpunew/hdl/example +# "do zimzpu.do" + +set BreakOnAssertion 1 +vlib work + +vcom -93 -explicit zpu_config.vhd +vcom -93 -explicit ../zpu4/src/zpupkg.vhd +vcom -93 -explicit ../zpu4/src/txt_util.vhd +vcom -93 -explicit sim_fpga_top.vhd +vcom -93 -explicit ../zpu4/src/zpu_core_small.vhd +vcom -93 -explicit helloworld.vhd +vcom -93 -explicit ../zpu4/src/timer.vhd +vcom -93 -explicit io.vhd +vcom -93 -explicit ../zpu4/src/trace.vhd + +# run ZPU +vsim fpga_top +view wave +add wave -recursive fpga_top/zpu/* +#add wave -recursive fpga_top/* +view structure +#view signals + +# Enough to run tiny programs +run 10 ms diff --git a/zpu/hdl/example/zpu_config.vhd b/zpu/hdl/example/zpu_config.vhd new file mode 100644 index 0000000..a59ac8e --- /dev/null +++ b/zpu/hdl/example/zpu_config.vhd @@ -0,0 +1,20 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +package zpu_config is + -- generate trace output + constant Generate_Trace : boolean := true; + constant wordPower : integer := 5; + -- during simulation, set this to '0' to get matching trace.txt + constant DontCareValue : std_logic := '0'; + -- Clock frequency in MHz. + constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64"; + -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) + constant maxAddrBitIncIO : integer := 27; + constant maxAddrBitBRAM : integer := 16; + + -- start byte address of stack. + -- point to top of RAM - 2*words + constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"1fffff8"; +end zpu_config; diff --git a/zpu/hdl/index.html b/zpu/hdl/index.html new file mode 100644 index 0000000..d3b4c1a --- /dev/null +++ b/zpu/hdl/index.html @@ -0,0 +1,47 @@ + + +

Getting started - FPGA

+The simplest version of the ZPU uses BRAM. When getting accustomed to the ZPU, a BRAM ZPU with a UART +is a good place to start. +

+You'll find a working simulation script in hdl/example/simzpu.do. +

+When implementing the ZPU, copy the following files and modify them to your needs: +

    +
  1. hdl/example/zpu_config.vhd - set up RAM size here +
  2. hdl/example/helloworld.vhd - dual port BRAM implementation. +
+Obviously you must also connect the ZPU to the rest of your IO subsystem. IO is memory mapped(read/write) in the ZPU. +

Generating VHDL BRAM initialization

+ + +../install/bin/zpu-elf-objdump -O binary hello.elf hello.bin
+java -classpath ../simulator/zpusim.jar com.zylin.zpu.simulator.tools.MakeRam hello.bin >hello.bram
+ + +

Running example simulation

+The hdl/example directory has a simulation written for Xilinx WebPack ModelSim. From the ModelSim command prompt: +
    +
  1. cd c:/<installfolder>/hdl/example +
  2. do zpusim.do +
+

+After running the hello world simulation (see zpusim.do), two files are written to the hdl/exmaple directory: +

    +
  1. log.txt - contains the "Hello world!" text written to the debug channel/simplified UART. +
  2. trace.txt - a trace file for the CPU. The instruction set simulator has the capability of taking +this file as input in order to verify that the HDL implementation matches the instruction set simulator. +When a mismatch is found, the GDB debugger will break. Very handy for debugging custom ZPU implementations. +
+

HDL Directories & files

+ + +The HDL files need a bit of spit and polish! + + diff --git a/zpu/hdl/wishbone/wishbone_pkg.vhd b/zpu/hdl/wishbone/wishbone_pkg.vhd new file mode 100644 index 0000000..c3b0d9b --- /dev/null +++ b/zpu/hdl/wishbone/wishbone_pkg.vhd @@ -0,0 +1,52 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +package wishbone_pkg is + + type wishbone_bus_in is record + adr : std_logic_vector(31 downto 0); + sel : std_logic_vector(3 downto 0); + we : std_logic; + dat : std_logic_vector(31 downto 0); -- Note! Data written with 'we' + cyc : std_logic; + stb : std_logic; + end record; + + type wishbone_bus_out is record + dat : std_logic_vector(31 downto 0); + ack : std_logic; + end record; + + type wishbone_bus is record + insig : wishbone_bus_in; + outsig : wishbone_bus_out; + end record; + + component atomic32_access is + port ( cpu_clk : in std_logic; + areset : in std_logic; + + -- Wishbone from CPU interface + wb_16_i : in wishbone_bus_in; + wb_16_o : out wishbone_bus_out; + -- Wishbone to FPGA registers and ethernet core + wb_32_i : in wishbone_bus_out; + wb_32_o : out wishbone_bus_in); + end component; + + component eth_access_corr is + port ( cpu_clk : in std_logic; + areset : in std_logic; + + -- Wishbone from Wishbone MUX + eth_raw_o : out wishbone_bus_out; + eth_raw_i : in wishbone_bus_in; + + -- Wishbone ethernet core + eth_slave_i : in wishbone_bus_out; + eth_slave_o : out wishbone_bus_in); + end component; + + +end wishbone_pkg; diff --git a/zpu/hdl/wishbone/zpu_system.vhd b/zpu/hdl/wishbone/zpu_system.vhd new file mode 100644 index 0000000..6e79370 --- /dev/null +++ b/zpu/hdl/wishbone/zpu_system.vhd @@ -0,0 +1,71 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + +library work; +use work.wishbone_pkg.all; +use work.zpupkg.all; +use work.zpu_config.all; +use work.ic300pkg.all; + +entity zpu_system is + generic( + simulate : boolean := false); + port ( areset : in std_logic; + cpu_clk : in std_logic; + + -- ZPU Control signals + enable : in std_logic; + interrupt : in std_logic; + + zpu_status : out std_logic_vector(63 downto 0); + + -- wishbone interfaces + zpu_wb_i : in wishbone_bus_out; + zpu_wb_o : out wishbone_bus_in); +end zpu_system; + +architecture behave of zpu_system is + +signal mem_req : std_logic; +signal mem_we : std_logic; +signal mem_ack : std_logic; +signal mem_read : std_logic_vector(wordSize-1 downto 0); +signal mem_write : std_logic_vector(wordSize-1 downto 0); +signal out_mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); +signal mem_writeMask : std_logic_vector(wordBytes-1 downto 0); + + +begin + + my_zpu_core: + zpu_core port map ( + clk => cpu_clk, + areset => areset, + enable => enable, + mem_req => mem_req, + mem_we => mem_we, + mem_ack => mem_ack, + mem_read => mem_read, + mem_write => mem_write, + out_mem_addr => out_mem_addr, + mem_writeMask => mem_writeMask, + interrupt => interrupt, + zpu_status => zpu_status, + break => open); + + my_zpu_wb_bridge: + zpu_wb_bridge port map ( + clk => cpu_clk, + areset => areset, + mem_req => mem_req, + mem_we => mem_we, + mem_ack => mem_ack, + mem_read => mem_read, + mem_write => mem_write, + out_mem_addr => out_mem_addr, + mem_writeMask => mem_writeMask, + zpu_wb_i => zpu_wb_i, + zpu_wb_o => zpu_wb_o); + +end behave; diff --git a/zpu/hdl/wishbone/zpu_wb_bridge.vhd b/zpu/hdl/wishbone/zpu_wb_bridge.vhd new file mode 100644 index 0000000..4182f7a --- /dev/null +++ b/zpu/hdl/wishbone/zpu_wb_bridge.vhd @@ -0,0 +1,49 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.phi_config.all; +use work.wishbone_pkg.all; +use work.zpupkg.all; +use work.zpu_config.all; + +entity zpu_wb_bridge is + port ( -- Native ZPU interface + clk : in std_logic; + areset : in std_logic; + + mem_req : in std_logic; + mem_we : in std_logic; + mem_ack : out std_logic; + mem_read : out std_logic_vector(wordSize-1 downto 0); + mem_write : in std_logic_vector(wordSize-1 downto 0); + out_mem_addr : in std_logic_vector(maxAddrBitIncIO downto 0); + mem_writeMask : in std_logic_vector(wordBytes-1 downto 0); + + -- Wishbone from ZPU + zpu_wb_i : in wishbone_bus_out; + zpu_wb_o : out wishbone_bus_in); + +end zpu_wb_bridge; + +architecture behave of zpu_wb_bridge is + +begin + + mem_read <= zpu_wb_i.dat; + mem_ack <= zpu_wb_i.ack; + + zpu_wb_o.adr <= "000000" & out_mem_addr(27) & out_mem_addr(24 downto 0); + zpu_wb_o.dat <= mem_write; + zpu_wb_o.sel <= mem_writeMask; + zpu_wb_o.stb <= mem_req; + zpu_wb_o.cyc <= mem_req; + zpu_wb_o.we <= mem_we; + +end behave; + + + + + diff --git a/zpu/hdl/zpu3/src/.cvsignore b/zpu/hdl/zpu3/src/.cvsignore new file mode 100644 index 0000000..760be11 --- /dev/null +++ b/zpu/hdl/zpu3/src/.cvsignore @@ -0,0 +1 @@ +xilinx_device_details.xml diff --git a/zpu/hdl/zpu3/src/build.xml b/zpu/hdl/zpu3/src/build.xml new file mode 100644 index 0000000..e1b268a --- /dev/null +++ b/zpu/hdl/zpu3/src/build.xml @@ -0,0 +1,114 @@ + + + + + + + eCosBoard firmware build file + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/zpu/hdl/zpu3/src/clocks.vhd b/zpu/hdl/zpu3/src/clocks.vhd new file mode 100644 index 0000000..a352b3c --- /dev/null +++ b/zpu/hdl/zpu3/src/clocks.vhd @@ -0,0 +1,246 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library UNISIM; +use UNISIM.vcomponents.all; + +entity clocks is + port ( areset : in std_logic; + cpu_clk_p : in std_logic; + sdr_clk_fb_p : in std_logic; + cpu_clk : out std_logic; + cpu_clk_2x : out std_logic; + cpu_clk_4x : out std_logic; + ddr_in_clk : out std_logic; + ddr_in_clk_2x : out std_logic; + locked : out std_logic_vector(2 downto 0)); +end clocks; + +architecture behave of clocks is + +signal low : std_logic; + +signal cpu_clk_in : std_logic; +signal sdr_clk_fb_in : std_logic; + +signal dcm_cpu1 : std_logic; +signal dcm_cpu2 : std_logic; +signal dcm_cpu2_dum : std_logic; +signal dcm_cpu4 : std_logic; +signal dcm_ddr2 : std_logic; +signal dcm_ddr2_2x : std_logic; + +signal cpu_clk_int : std_logic; +signal cpu_clk_2x_int : std_logic; +signal cpu_clk_2x_dum_int : std_logic; +signal cpu_clk_4x_int : std_logic; +signal ddr_in_clk_int : std_logic; +signal ddr_in_clk_2x_int : std_logic; + +signal dcm1_locked_del : std_logic; +signal dcm2_locked_del : std_logic; +signal dcm2_reset : std_logic; +signal dcm3_reset : std_logic; + +signal locked_int : std_logic_vector(2 downto 0); +signal del_addr : std_logic_vector(3 downto 0); + +begin + + low <= '0'; + del_addr <= "1111"; + + cpu_clk <= cpu_clk_int; + cpu_clk_2x <= cpu_clk_2x_int; + cpu_clk_4x <= cpu_clk_4x_int; + ddr_in_clk <= ddr_in_clk_int; + ddr_in_clk_2x <= ddr_in_clk_2x_int; + locked <= locked_int; + + + CPU_IBUFG: + IBUFG port map ( + O => cpu_clk_in, + I => cpu_clk_p); + + SDR_FB_IBUFG: + IBUFG port map ( + O => sdr_clk_fb_in, + I => sdr_clk_fb_p); + + dcm2_rst: + SRL16 generic map ( + INIT => X"0000") + port map ( + Q => dcm1_locked_del, + A0 => del_addr(0), + A1 => del_addr(1), + A2 => del_addr(2), + A3 => del_addr(3), + CLK => cpu_clk_int, + D => locked_int(0)); + + dcm2_reset <= not(dcm1_locked_del); + + dcm3_rst: + SRL16 generic map ( + INIT => X"0000") + port map ( + Q => dcm2_locked_del, + A0 => del_addr(0), + A1 => del_addr(1), + A2 => del_addr(2), + A3 => del_addr(3), + CLK => cpu_clk_int, + D => locked_int(1)); + + dcm3_reset <= not(dcm2_locked_del); + + cpu1_dcm: + DCM generic map ( + CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 + -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 + CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 + CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32 + CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature + CLKIN_PERIOD => 15.625, -- Specify period of input clock + CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE + CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or + -- an integer from 0 to 15 + DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis + DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL + DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE + FACTORY_JF => X"8080", -- FACTORY JF Values + PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 + STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE + port map ( + CLK0 => dcm_cpu1, -- 0 degree DCM CLK ouptput + CLK180 => open, -- 180 degree DCM CLK output + CLK270 => open, -- 270 degree DCM CLK output + CLK2X => dcm_cpu2, -- 2X DCM CLK output + CLK2X180 => open, -- 2X, 180 degree DCM CLK out + CLK90 => open, -- 90 degree DCM CLK output + CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) + CLKFX => open, -- DCM CLK synthesis out (M/D) + CLKFX180 => open, -- 180 degree CLK synthesis out + LOCKED => locked_int(0), -- DCM LOCK status output + PSDONE => open, -- Dynamic phase adjust done output + STATUS => open, -- 8-bit DCM status bits output + CLKFB => cpu_clk_int, -- DCM clock feedback + CLKIN => cpu_clk_in, -- Clock input (from IBUFG, BUFG or DCM) + PSCLK => low, -- Dynamic phase adjust clock input + PSEN => low, -- Dynamic phase adjust enable input + PSINCDEC => low, -- Dynamic phase adjust increment/decrement + RST => areset); -- DCM asynchronous reset input + + cpu2_dcm: + DCM generic map ( + CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 + -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 + CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 + CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32 + CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature + CLKIN_PERIOD => 7.8125, -- Specify period of input clock + CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE + CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or + -- an integer from 0 to 15 + DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis + DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL + DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE + FACTORY_JF => X"8080", -- FACTORY JF Values + PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 + STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE + port map ( + CLK0 => dcm_cpu2_dum, -- 0 degree DCM CLK ouptput + CLK180 => open, -- 180 degree DCM CLK output + CLK270 => open, -- 270 degree DCM CLK output + CLK2X => dcm_cpu4, -- 2X DCM CLK output + CLK2X180 => open, -- 2X, 180 degree DCM CLK out + CLK90 => open, -- 90 degree DCM CLK output + CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) + CLKFX => open, -- DCM CLK synthesis out (M/D) + CLKFX180 => open, -- 180 degree CLK synthesis out + LOCKED => locked_int(1), -- DCM LOCK status output + PSDONE => open, -- Dynamic phase adjust done output + STATUS => open, -- 8-bit DCM status bits output + CLKFB => cpu_clk_2x_dum_int, -- DCM clock feedback + CLKIN => cpu_clk_2x_int, -- Clock input (from IBUFG, BUFG or DCM) + PSCLK => low, -- Dynamic phase adjust clock input + PSEN => low, -- Dynamic phase adjust enable input + PSINCDEC => low, -- Dynamic phase adjust increment/decrement + RST => dcm2_reset); -- DCM asynchronous reset input + + ddr_read_dcm: + DCM generic map ( + CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 + -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 + CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 + CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32 + CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature + CLKIN_PERIOD => 7.8125, -- Specify period of input clock + CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift of NONE, FIXED or VARIABLE +-- CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE + CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or + -- an integer from 0 to 15 + DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis + DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL + DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE + FACTORY_JF => X"8080", -- FACTORY JF Values + PHASE_SHIFT => 103, -- Amount of fixed phase shift from -255 to 255 +-- PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 + STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE + port map ( + CLK0 => dcm_ddr2, -- 0 degree DCM CLK ouptput + CLK180 => open, -- 180 degree DCM CLK output + CLK270 => open, -- 270 degree DCM CLK output + CLK2X => dcm_ddr2_2x, -- 2X DCM CLK output + CLK2X180 => open, -- 2X, 180 degree DCM CLK out + CLK90 => open, -- 90 degree DCM CLK output + CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) + CLKFX => open, -- DCM CLK synthesis out (M/D) + CLKFX180 => open, -- 180 degree CLK synthesis out + LOCKED => locked_int(2), -- DCM LOCK status output + PSDONE => open, -- Dynamic phase adjust done output + STATUS => open, -- 8-bit DCM status bits output + CLKFB => ddr_in_clk_int, -- DCM clock feedback + CLKIN => sdr_clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM) + PSCLK => low, -- Dynamic phase adjust clock input + PSEN => low, -- Dynamic phase adjust enable input + PSINCDEC => low, -- Dynamic phase adjust increment/decrement + RST => dcm3_reset); -- DCM asynchronous reset input + + cpu1: + BUFG port map ( + I => dcm_cpu1, + O => cpu_clk_int); + + cpu2: + BUFG port map ( + I => dcm_cpu2, + O => cpu_clk_2x_int); + + cpu2_dum: + BUFG port map ( + I => dcm_cpu2_dum, + O => cpu_clk_2x_dum_int); + + cpu4: + BUFG port map ( + I => dcm_cpu4, + O => cpu_clk_4x_int); + + ddr_clk: + BUFG port map ( + I => dcm_ddr2, + O => ddr_in_clk_int); + + ddr_clk_2x: + BUFG port map ( + I => dcm_ddr2_2x, + O => ddr_in_clk_2x_int); + +end behave; \ No newline at end of file diff --git a/zpu/hdl/zpu3/src/ddr_bridge.vhd b/zpu/hdl/zpu3/src/ddr_bridge.vhd new file mode 100644 index 0000000..7dece76 --- /dev/null +++ b/zpu/hdl/zpu3/src/ddr_bridge.vhd @@ -0,0 +1,203 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library UNISIM; +use UNISIM.vcomponents.all; + +library zylin; +use zylin.ddr.all; + +library work; +use work.phi_config.all; + +entity ddr_bridge is + port ( areset : in std_logic; + cpu_clk : in std_logic; + cpu_clk_2x : in std_logic; + cpu_clk_4x : in std_logic; + ddr_in_clk : in std_logic; + ddr_in_clk_2x : in std_logic; + + cpu_we : in std_logic_vector(1 downto 0); + cpu_re : in std_logic; + cpu_din : in std_logic_vector(15 downto 0); + cpu_a : in std_logic_vector(20 downto 0); + cpu_dout : inout std_logic_vector(15 downto 0); + + sdr_clk_p : out std_logic; -- ddr_sdram_clock + sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock + cke_q_p : out std_logic; -- clock enable + cs_qn_p : out std_logic; -- /chip select + ras_qn_p : inout std_logic; -- /ras + cas_qn_p : inout std_logic; -- /cas + we_qn_p : inout std_logic; -- /write enable + dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00" + dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write + ba_q_p : out std_logic_vector(1 downto 0); -- bank select + sdr_a_p : out std_logic_vector(12 downto 0); -- address bus + sdr_d_p : inout std_logic_vector(15 downto 0)); -- bidir data bus +end ddr_bridge; + +architecture behave of ddr_bridge is + +signal refresh_en : std_logic; +signal ddr_command_we : std_logic; +signal ddr_command : std_logic_vector(15 downto 0); + +signal ddr_req : std_logic; +signal ddr_req_adr : std_logic_vector(23 downto 1); +signal ddr_rd_wr_n : std_logic; +signal ddr_req_len : std_logic; + +signal ddr_read_en : std_logic; +signal ddr_write_en : std_logic; +signal ddr_data_read : std_logic_vector(31 downto 0); +signal ddr_data_write : std_logic_vector(35 downto 0); + +signal ddr_read_smp : std_logic_vector(31 downto 0); +signal ddr_read_delay : std_logic_vector(15 downto 0); + +signal ddr_write_smp : std_logic_vector(15 downto 0); +signal ddr_addr_smp : std_logic_vector(15 downto 0); + +signal ddr_req_type_smp : std_logic; +signal ddr_req_on : std_logic; +signal ddr_req_off : std_logic; +signal ddr_req_int : std_logic; + +constant Sim_Delay : time := 1.0 ns; + +begin + + ddr_req_len <= '0'; + ddr_data_write <= "0000" & ddr_write_smp & ddr_write_smp; + ddr_req_adr <= "0000000" & ddr_addr_smp; + ddr_rd_wr_n <= ddr_req_type_smp; + ddr_req <= ddr_req_int; + + process(cpu_clk, areset) -- CPU writeable registers + begin + if areset = '1' then + refresh_en <= '0'; + ddr_command_we <= '0'; + ddr_command <= "0000000000000000"; + ddr_write_smp <= "0000000000000000"; + ddr_req_type_smp <= '0'; + ddr_req_on <= '0'; + elsif (cpu_clk'event and cpu_clk = '1') then + + if cpu_we(0) = '1' and cpu_a(19 downto 17) = Fpga_DDR_Ctrl_Base and cpu_a(3 downto 1) = DDR_Ctrl_Reg_Addr then + refresh_en <= cpu_din(0); + else + refresh_en <= refresh_en; + end if; + + if cpu_we(0) = '1' and cpu_a(19 downto 17) = Fpga_DDR_Ctrl_Base and cpu_a(3 downto 1) = DDR_Mode_Reg_Addr then + ddr_command <= cpu_din; + ddr_command_we <= '1'; + else + ddr_command <= ddr_command; + ddr_command_we <= '0'; + end if; + + if cpu_we(0) = '1' and cpu_a(19 downto 17) = Fpga_DDR_Ctrl_Base and cpu_a(3 downto 1) = DDR_Data_Reg_Addr then + ddr_write_smp <= cpu_din; + else + ddr_write_smp <= ddr_write_smp; + end if; + + if cpu_we(0) = '1' and cpu_a(19 downto 17) = Fpga_DDR_Ctrl_Base and cpu_a(3 downto 1) = DDR_Addr_Reg_Addr then + ddr_addr_smp <= cpu_din; + else + ddr_addr_smp <= ddr_addr_smp; + end if; + + if cpu_we(0) = '1' and cpu_a(19 downto 17) = Fpga_DDR_Ctrl_Base and cpu_a(3 downto 1) = DDR_Req_Reg_Addr then + ddr_req_type_smp <= cpu_din(0); + ddr_req_on <= '1'; + else + ddr_req_type_smp <= ddr_req_type_smp; + ddr_req_on <= '0'; + end if; + + end if; + end process; + + -- CPU readable registers + cpu_dout <= ddr_read_delay when (cpu_re = '1' and cpu_a(19 downto 17) = Fpga_DDR_Ctrl_Base and cpu_a(3 downto 1) = DDR_Data_Reg_Addr) else "ZZZZZZZZZZZZZZZZ"; + + -- Capture data read from DDR + process(cpu_clk_2x, areset) + begin + if areset = '1' then + ddr_read_smp <= (others => '0'); + elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then + if ddr_read_en = '1' then + ddr_read_smp <= ddr_data_read after Sim_Delay; + else + ddr_read_smp <= ddr_read_smp after Sim_Delay; + end if; + end if; + end process; + + -- Move captured data from DDR to cpu_clk domain (for better routing timing) + process(cpu_clk, areset) + begin + if areset = '1' then + ddr_read_delay <= "0000000000000000"; + elsif (cpu_clk'event and cpu_clk = '1') then + ddr_read_delay <= ddr_read_smp(15 downto 0); + end if; + end process; + + process(cpu_clk_2x, areset) + begin + if areset = '1' then + ddr_req_int <= '0'; + elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then + if ddr_req_on = '1' then + ddr_req_int <= '1' after Sim_Delay; + elsif ddr_read_en = '1' or ddr_write_en = '1' then + ddr_req_int <= '0' after Sim_Delay; + else + ddr_req_int <= ddr_req_int after Sim_Delay; + end if; + end if; + end process; + + + ddr_interface: + ddr_top port map( + areset => areset, + cpu_clk => cpu_clk, + cpu_clk_2x => cpu_clk_2x, + cpu_clk_4x => cpu_clk_4x, + ddr_in_clk => ddr_in_clk, + ddr_in_clk_2x => ddr_in_clk_2x, + ddr_command => ddr_command, + ddr_command_we => ddr_command_we, + refresh_en => refresh_en, + ddr_data_read => ddr_data_read, + ddr_data_write => ddr_data_write, + ddr_req => ddr_req, + ddr_req_adr => ddr_req_adr, + ddr_rd_wr_n => ddr_rd_wr_n, + ddr_req_len => ddr_req_len, + ddr_read_en => ddr_read_en, + ddr_write_en => ddr_write_en, + sdr_clk_p => sdr_clk_p, + sdr_clk_n_p => sdr_clk_n_p, + cke_q_p => cke_q_p, + cs_qn_p => cs_qn_p, + ras_qn_p => ras_qn_p, + cas_qn_p => cas_qn_p, + we_qn_p => we_qn_p, + dm_q_p => dm_q_p, + dqs_q_p => dqs_q_p, + ba_q_p => ba_q_p, + sdr_a_p => sdr_a_p, + sdr_d_p => sdr_d_p); + + +end behave; diff --git a/zpu/hdl/zpu3/src/dmips_ram.vhd b/zpu/hdl/zpu3/src/dmips_ram.vhd new file mode 100644 index 0000000..f472653 --- /dev/null +++ b/zpu/hdl/zpu3/src/dmips_ram.vhd @@ -0,0 +1,3824 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + + +library zylin; +use zylin.zpu_config.all; +use zylin.zpupkg.all; + +entity dualport_ram is +port (clk : in std_logic; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit); + memAWrite : in std_logic_vector(wordSize-1 downto 0); + memARead : out std_logic_vector(wordSize-1 downto 0); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit); + memBWrite : in std_logic_vector(wordSize-1 downto 0); + memBRead : out std_logic_vector(wordSize-1 downto 0)); +end dualport_ram; + +architecture dualport_ram_arch of dualport_ram is + + +type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); + +shared variable ram : ram_type := +( +0 => x"800b0b0b", +1 => x"0b0b8070", +2 => x"0b0b80e5", +3 => x"d00c3a0b", +4 => x"0b0bbed7", +5 => x"04000000", +6 => x"00000000", +7 => x"00000000", +8 => x"80088408", +9 => x"88080b0b", +10 => x"0bbfa72d", +11 => x"880c840c", +12 => x"800c0400", +13 => x"00000000", +14 => x"00000000", +15 => x"00000000", +16 => x"71fd0608", +17 => x"72830609", +18 => x"81058205", +19 => x"832b2a83", +20 => x"ffff0652", +21 => x"0b0b0400", +22 => x"00000000", +23 => x"00000000", +24 => x"71fd0608", +25 => x"83ffff73", +26 => x"83060981", +27 => x"05820583", +28 => x"2b2b0906", +29 => x"7383ffff", +30 => x"0b0b0b0b", +31 => x"83a70400", +32 => x"72098105", +33 => x"72057373", +34 => x"09060906", +35 => x"73097306", +36 => x"070a8106", +37 => x"530b0b51", +38 => x"04000000", +39 => x"00000000", +40 => x"72722473", +41 => x"732e0753", +42 => x"0b0b5104", +43 => x"00000000", +44 => x"00000000", +45 => x"00000000", +46 => x"00000000", +47 => x"00000000", +48 => x"71737109", +49 => x"71068106", +50 => x"30720a10", +51 => x"0a720a10", +52 => x"0a31050a", +53 => x"81065151", +54 => x"530b0b51", +55 => x"04000000", +56 => x"72722673", +57 => x"732e0753", +58 => x"0b0b5104", +59 => x"00000000", +60 => x"00000000", +61 => x"00000000", +62 => x"00000000", +63 => x"00000000", +64 => x"00000000", +65 => x"00000000", +66 => x"00000000", +67 => x"00000000", +68 => x"00000000", +69 => x"00000000", +70 => x"00000000", +71 => x"00000000", +72 => x"0b0b0b88", +73 => x"c6040000", +74 => x"00000000", +75 => x"00000000", +76 => x"00000000", +77 => x"00000000", +78 => x"00000000", +79 => x"00000000", +80 => x"720a722b", +81 => x"0a530b0b", +82 => x"51040000", +83 => x"00000000", +84 => x"00000000", +85 => x"00000000", +86 => x"00000000", +87 => x"00000000", +88 => x"72729f06", +89 => x"0981050b", +90 => x"0b0b88a7", +91 => x"05040000", +92 => x"00000000", +93 => x"00000000", +94 => x"00000000", +95 => x"00000000", +96 => x"72722aff", +97 => x"739f062a", +98 => x"0974090a", +99 => x"8106ff05", +100 => x"0607530b", +101 => x"0b510400", +102 => x"00000000", +103 => x"00000000", +104 => x"7171530b", +105 => x"0b510406", +106 => x"73830609", +107 => x"81058205", +108 => x"832b0b2b", +109 => x"0772fc06", +110 => x"0c515104", +111 => x"00000000", +112 => x"72098105", +113 => x"72050970", +114 => x"81050906", +115 => x"0a810653", +116 => x"0b0b5104", +117 => x"00000000", +118 => x"00000000", +119 => x"00000000", +120 => x"72098105", +121 => x"72050970", +122 => x"81050906", +123 => x"0a098106", +124 => x"530b0b51", +125 => x"04000000", +126 => x"00000000", +127 => x"00000000", +128 => x"71098105", +129 => x"520b0b04", +130 => x"00000000", +131 => x"00000000", +132 => x"00000000", +133 => x"00000000", +134 => x"00000000", +135 => x"00000000", +136 => x"72720981", +137 => x"0505530b", +138 => x"0b510400", +139 => x"00000000", +140 => x"00000000", +141 => x"00000000", +142 => x"00000000", +143 => x"00000000", +144 => x"72097206", +145 => x"73730906", +146 => x"07530b0b", +147 => x"51040000", +148 => x"00000000", +149 => x"00000000", +150 => x"00000000", +151 => x"00000000", +152 => x"71fc0608", +153 => x"72830609", +154 => x"81058305", +155 => x"1010102a", +156 => x"81ff0652", +157 => x"0b0b0400", +158 => x"00000000", +159 => x"00000000", +160 => x"71fc0608", +161 => x"0b0b80e5", +162 => x"bc738306", +163 => x"10100508", +164 => x"060b0b0b", +165 => x"88ac0400", +166 => x"00000000", +167 => x"00000000", +168 => x"80088408", +169 => x"88087575", +170 => x"0b0b0ba3", +171 => x"fa2d5050", +172 => x"80085688", +173 => x"0c840c80", +174 => x"0c510400", +175 => x"00000000", +176 => x"80088408", +177 => x"88087575", +178 => x"0b0b0ba4", +179 => x"ca2d5050", +180 => x"80085688", +181 => x"0c840c80", +182 => x"0c510400", +183 => x"00000000", +184 => x"72097081", +185 => x"0509060a", +186 => x"8106ff05", +187 => x"70540b0b", +188 => x"71067309", +189 => x"727405ff", +190 => x"05060751", +191 => x"51510400", +192 => x"72097081", +193 => x"0509060a", +194 => x"098106ff", +195 => x"0570540b", +196 => x"0b710673", +197 => x"09727405", +198 => x"ff050607", +199 => x"51515104", +200 => x"05ff0504", +201 => x"00000000", +202 => x"00000000", +203 => x"00000000", +204 => x"00000000", +205 => x"00000000", +206 => x"00000000", +207 => x"00000000", +208 => x"810b0b0b", +209 => x"80e5cc0c", +210 => x"51040000", +211 => x"00000000", +212 => x"00000000", +213 => x"00000000", +214 => x"00000000", +215 => x"00000000", +216 => x"71810552", +217 => x"0b0b0400", +218 => x"00000000", +219 => x"00000000", +220 => x"00000000", +221 => x"00000000", +222 => x"00000000", +223 => x"00000000", +224 => x"00000000", +225 => x"00000000", +226 => x"00000000", +227 => x"00000000", +228 => x"00000000", +229 => x"00000000", +230 => x"00000000", +231 => x"00000000", +232 => x"02840572", +233 => x"10100552", +234 => x"0b0b0400", +235 => x"00000000", +236 => x"00000000", +237 => x"00000000", +238 => x"00000000", +239 => x"00000000", +240 => x"00000000", +241 => x"00000000", +242 => x"00000000", +243 => x"00000000", +244 => x"00000000", +245 => x"00000000", +246 => x"00000000", +247 => x"00000000", +248 => x"717105ff", +249 => x"0571530b", +250 => x"0b510400", +251 => x"00000000", +252 => x"00000000", +253 => x"00000000", +254 => x"00000000", +255 => x"00000000", +256 => x"84803f80", +257 => x"cef23f04", +258 => x"10101010", +259 => x"10101010", +260 => x"10101010", +261 => x"10101010", +262 => x"10101010", +263 => x"10101010", +264 => x"10101010", +265 => x"10101053", +266 => x"0b0b5104", +267 => x"7381ff06", +268 => x"73830609", +269 => x"81058305", +270 => x"1010102b", +271 => x"0772fc06", +272 => x"0c515104", +273 => x"3c047272", +274 => x"80728106", +275 => x"ff050972", +276 => x"06057110", +277 => x"520b0b72", +278 => x"0a100a53", +279 => x"0b0b72e9", +280 => x"38515153", +281 => x"0b0b5104", +282 => x"70700b0b", +283 => x"80f5c008", +284 => x"520b0b84", +285 => x"0b720508", +286 => x"70810651", +287 => x"510b0b70", +288 => x"f2387108", +289 => x"81ff0680", +290 => x"0c505004", +291 => x"70700b0b", +292 => x"80f5c008", +293 => x"520b0b84", +294 => x"0b720508", +295 => x"700a100a", +296 => x"70810651", +297 => x"51510b0b", +298 => x"70ed3873", +299 => x"720c5050", +300 => x"0480e5cc", +301 => x"08802ea8", +302 => x"38838080", +303 => x"0b0b0b80", +304 => x"f5c00c82", +305 => x"a0800b0b", +306 => x"0b80f5c4", +307 => x"0c829080", +308 => x"0b80f5d4", +309 => x"0c0b0b80", +310 => x"f5c80b80", +311 => x"f5d80c04", +312 => x"f8808080", +313 => x"a40b0b0b", +314 => x"80f5c00c", +315 => x"f8808082", +316 => x"800b0b0b", +317 => x"80f5c40c", +318 => x"f8808084", +319 => x"800b80f5", +320 => x"d40cf880", +321 => x"8080940b", +322 => x"80f5d80c", +323 => x"f8808080", +324 => x"9c0b80f5", +325 => x"d00cf880", +326 => x"8080a00b", +327 => x"80f5dc0c", +328 => x"04f23d0d", +329 => x"600b0b80", +330 => x"f5c40856", +331 => x"5d82750c", +332 => x"8059805a", +333 => x"800b8f3d", +334 => x"71101017", +335 => x"70085957", +336 => x"5d5b8076", +337 => x"81ff067c", +338 => x"832b5658", +339 => x"520b0b0b", +340 => x"76530b0b", +341 => x"7b5198c6", +342 => x"3f7d7f7a", +343 => x"72077c72", +344 => x"07717160", +345 => x"8105415f", +346 => x"5d5b5957", +347 => x"557a8724", +348 => x"80c1380b", +349 => x"0b80f5c4", +350 => x"087b1010", +351 => x"71057008", +352 => x"58515580", +353 => x"7681ff06", +354 => x"7c832b56", +355 => x"58520b0b", +356 => x"0b76530b", +357 => x"0b7b5198", +358 => x"853f7d7f", +359 => x"7a72077c", +360 => x"72077171", +361 => x"60810541", +362 => x"5f5d5b59", +363 => x"5755877b", +364 => x"25c13876", +365 => x"7d0c7784", +366 => x"1e0c7c80", +367 => x"0c903d0d", +368 => x"04707080", +369 => x"f5cc3351", +370 => x"0b0b70b2", +371 => x"3880e5d8", +372 => x"08700852", +373 => x"0b0b520b", +374 => x"0b0b7080", +375 => x"2e9a3884", +376 => x"720580e5", +377 => x"d80c702d", +378 => x"80e5d808", +379 => x"7008520b", +380 => x"0b520b0b", +381 => x"0b70e838", +382 => x"810b80f5", +383 => x"cc345050", +384 => x"0404700b", +385 => x"0b80f5bc", +386 => x"08802e8e", +387 => x"380b0b0b", +388 => x"0b800b80", +389 => x"2e098106", +390 => x"83385004", +391 => x"0b0b80f5", +392 => x"bc510b0b", +393 => x"0bf3d93f", +394 => x"50040470", +395 => x"70028f05", +396 => x"33520b0b", +397 => x"0b0b718a", +398 => x"2e893871", +399 => x"51fccd3f", +400 => x"5050048d", +401 => x"51fcc53f", +402 => x"7151fcc0", +403 => x"3f505004", +404 => x"cd3d0db6", +405 => x"3d707084", +406 => x"05520b0b", +407 => x"088cab5d", +408 => x"56a63d5f", +409 => x"5d807570", +410 => x"81055733", +411 => x"765c5559", +412 => x"0b730b79", +413 => x"2e80ca38", +414 => x"8f3d5c73", +415 => x"a52e0981", +416 => x"0680cf38", +417 => x"79708105", +418 => x"5b33540b", +419 => x"0b7380e4", +420 => x"2e81c838", +421 => x"7380e424", +422 => x"80d13873", +423 => x"80e32ea8", +424 => x"3880520b", +425 => x"0ba5517a", +426 => x"2d80520b", +427 => x"0b73517a", +428 => x"2d821959", +429 => x"79708105", +430 => x"5b33540b", +431 => x"0b73ffbb", +432 => x"3878800c", +433 => x"b53d0d04", +434 => x"7c841e83", +435 => x"72053356", +436 => x"5e578052", +437 => x"0b0b7351", +438 => x"7a2d8119", +439 => x"7a708105", +440 => x"5c335559", +441 => x"0b73ff93", +442 => x"38d73973", +443 => x"80f32e09", +444 => x"8106ffad", +445 => x"387c841e", +446 => x"7108595e", +447 => x"56807733", +448 => x"56560b74", +449 => x"0b762e8d", +450 => x"38811670", +451 => x"1870335a", +452 => x"555677f5", +453 => x"38ff1655", +454 => x"807625ff", +455 => x"97387670", +456 => x"81055833", +457 => x"5880520b", +458 => x"0b77517a", +459 => x"2d811975", +460 => x"ff175757", +461 => x"59807625", +462 => x"fefa3876", +463 => x"70810558", +464 => x"33588052", +465 => x"0b0b7751", +466 => x"7a2d8119", +467 => x"75ff1757", +468 => x"57590b75", +469 => x"8024c738", +470 => x"feda397c", +471 => x"841e7108", +472 => x"70719f2c", +473 => x"59530b0b", +474 => x"595e5680", +475 => x"7524818d", +476 => x"38757e7d", +477 => x"58595580", +478 => x"57740b77", +479 => x"2e098106", +480 => x"bc38b07c", +481 => x"3402b905", +482 => x"567b0b76", +483 => x"2e9938ff", +484 => x"16560b0b", +485 => x"75337870", +486 => x"81055a34", +487 => x"8117577b", +488 => x"762e0981", +489 => x"06e93880", +490 => x"7834767e", +491 => x"ff720557", +492 => x"58560b0b", +493 => x"758024fe", +494 => x"e538fdf8", +495 => x"398a7536", +496 => x"0b0b80d7", +497 => x"b005540b", +498 => x"0b733376", +499 => x"70810558", +500 => x"348a7535", +501 => x"550b0b74", +502 => x"802effad", +503 => x"388a7536", +504 => x"0b0b80d7", +505 => x"b005540b", +506 => x"0b733376", +507 => x"70810558", +508 => x"348a7535", +509 => x"550b0b74", +510 => x"c438ff8d", +511 => x"3974520b", +512 => x"0b76530b", +513 => x"0bb53dff", +514 => x"b8055192", +515 => x"dc3fa43d", +516 => x"0856fedd", +517 => x"397080c1", +518 => x"0b81c48c", +519 => x"34800b81", +520 => x"c5e40c70", +521 => x"800c5004", +522 => x"7070800b", +523 => x"81c48c33", +524 => x"520b0b52", +525 => x"0b0b0b70", +526 => x"80c12e98", +527 => x"387181c5", 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x"00000000", +3748 => x"00000000", +3749 => x"00000000", +3750 => x"00000000", +3751 => x"00000000", +3752 => x"00000000", +3753 => x"00000000", +3754 => x"000031b0", +3755 => x"ffffffff", +3756 => x"00000000", +3757 => x"ffffffff", +3758 => x"00000000", + others => x"00000000" +); + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then + report "write collision" severity failure; + end if; + + if (memAWriteEnable = '1') then + ram(conv_integer(memAAddr)) := memAWrite; + memARead <= memAWrite; + else + memARead <= ram(conv_integer(memAAddr)); + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (memBWriteEnable = '1') then + ram(conv_integer(memBAddr)) := memBWrite; + memBRead <= memBWrite; + else + memBRead <= ram(conv_integer(memBAddr)); + end if; + end if; +end process; + + + + +end dualport_ram_arch; diff --git a/zpu/hdl/zpu3/src/dualport_ram.vhd b/zpu/hdl/zpu3/src/dualport_ram.vhd new file mode 100644 index 0000000..54380ce --- /dev/null +++ b/zpu/hdl/zpu3/src/dualport_ram.vhd @@ -0,0 +1,4996 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + + +library zylin; +use zylin.zpu_config.all; +use zylin.zpupkg.all; + +entity dualport_ram is +port (clk : in std_logic; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit); + memAWrite : in std_logic_vector(wordSize-1 downto 0); + memARead : out std_logic_vector(wordSize-1 downto 0); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit); + memBWrite : in std_logic_vector(wordSize-1 downto 0); + memBRead : out std_logic_vector(wordSize-1 downto 0)); +end dualport_ram; + +architecture dualport_ram_arch of dualport_ram is + + +type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); + +shared variable ram : ram_type := +( +0 => x"800b0b0b", +1 => x"0b0b8070", +2 => x"0b0b818a", +3 => x"880c3a0b", +4 => x"0b80fae8", +5 => x"04000000", +6 => x"00000000", +7 => x"00000000", +8 => x"80088408", +9 => x"88080b0b", +10 => x"80fbba2d", +11 => x"880c840c", +12 => x"800c0400", +13 => x"00000000", +14 => x"00000000", +15 => x"00000000", +16 => x"71fd0608", +17 => x"72830609", +18 => x"81058205", +19 => x"832b2a83", +20 => x"ffff0652", +21 => x"04000000", +22 => x"00000000", +23 => x"00000000", +24 => x"71fd0608", +25 => x"83ffff73", +26 => x"83060981", +27 => x"05820583", +28 => x"2b2b0906", +29 => x"7383ffff", +30 => x"0b0b0b0b", +31 => x"83a70400", +32 => x"72098105", +33 => x"72057373", +34 => x"09060906", +35 => x"73097306", +36 => x"070a8106", +37 => x"530b0b51", +38 => x"04000000", +39 => x"00000000", +40 => x"72722473", +41 => x"732e0753", +42 => x"0b0b5104", +43 => x"00000000", +44 => x"00000000", +45 => x"00000000", +46 => x"00000000", +47 => x"00000000", +48 => x"71737109", +49 => x"71068106", +50 => x"30720a10", +51 => x"0a720a10", +52 => x"0a31050a", +53 => x"81065151", +54 => x"530b0b51", +55 => x"04000000", +56 => x"72722673", +57 => x"732e0753", +58 => x"0b0b5104", +59 => x"00000000", +60 => x"00000000", +61 => x"00000000", +62 => x"00000000", +63 => x"00000000", +64 => x"00000000", +65 => x"00000000", +66 => x"00000000", +67 => x"00000000", +68 => x"00000000", +69 => x"00000000", +70 => x"00000000", +71 => x"00000000", +72 => x"72728072", +73 => x"8106ff05", +74 => x"09720605", +75 => x"71105272", +76 => x"0a100a53", +77 => x"0b0b72eb", +78 => x"38515153", +79 => x"0b0b5104", +80 => x"720a722b", +81 => x"0a530b0b", +82 => x"51040000", +83 => x"00000000", +84 => x"00000000", +85 => x"00000000", +86 => x"00000000", +87 => x"00000000", +88 => x"72729f06", +89 => x"0981050b", +90 => x"0b0b88a7", +91 => x"05040000", +92 => x"00000000", +93 => x"00000000", +94 => x"00000000", +95 => x"00000000", +96 => x"72722aff", +97 => x"739f062a", +98 => x"0974090a", +99 => x"8106ff05", +100 => x"0607530b", +101 => x"0b510400", +102 => x"00000000", +103 => x"00000000", +104 => x"7171530b", +105 => x"0b510406", +106 => x"73830609", +107 => x"81058205", +108 => x"832b0b2b", +109 => x"0772fc06", +110 => x"0c515104", +111 => x"00000000", +112 => x"72098105", +113 => x"72050970", +114 => x"81050906", +115 => x"0a810653", +116 => x"0b0b5104", +117 => x"00000000", +118 => x"00000000", +119 => x"00000000", +120 => x"72098105", +121 => x"72050970", +122 => x"81050906", +123 => x"0a098106", +124 => x"530b0b51", +125 => x"04000000", +126 => x"00000000", +127 => x"00000000", +128 => x"71098105", +129 => x"52040000", +130 => x"00000000", +131 => x"00000000", +132 => x"00000000", +133 => x"00000000", +134 => x"00000000", +135 => x"00000000", +136 => x"72720981", +137 => x"0505530b", +138 => x"0b510400", +139 => x"00000000", +140 => x"00000000", +141 => x"00000000", +142 => x"00000000", +143 => x"00000000", +144 => x"72097206", +145 => x"73730906", +146 => x"07530b0b", +147 => x"51040000", +148 => x"00000000", +149 => x"00000000", +150 => x"00000000", +151 => x"00000000", +152 => x"71fc0608", +153 => x"72830609", +154 => x"81058305", +155 => x"1010102a", +156 => x"81ff0652", +157 => x"04000000", +158 => x"00000000", +159 => x"00000000", +160 => x"71fc0608", +161 => x"0b0b8189", +162 => x"f4738306", +163 => x"10100508", +164 => x"060b0b0b", +165 => x"88ac0400", +166 => x"00000000", +167 => x"00000000", +168 => x"80088408", +169 => x"88087575", +170 => x"0b0b0b8f", +171 => x"e42d5050", +172 => x"80085688", +173 => x"0c840c80", +174 => x"0c510400", +175 => x"00000000", +176 => x"80088408", +177 => x"88087575", +178 => x"0b0b0b91", +179 => x"9c2d5050", +180 => x"80085688", +181 => x"0c840c80", +182 => x"0c510400", +183 => x"00000000", +184 => x"72097081", +185 => x"0509060a", +186 => x"8106ff05", +187 => x"70540b0b", +188 => x"71067309", +189 => x"727405ff", +190 => x"05060751", +191 => x"51510400", +192 => x"72097081", +193 => x"0509060a", +194 => x"098106ff", +195 => x"0570540b", +196 => x"0b710673", +197 => x"09727405", +198 => x"ff050607", +199 => x"51515104", +200 => x"05ff0504", +201 => x"00000000", +202 => x"00000000", +203 => x"00000000", +204 => x"00000000", +205 => x"00000000", +206 => x"00000000", +207 => x"00000000", +208 => x"810b0b0b", +209 => x"818a840c", +210 => x"51040000", +211 => x"00000000", +212 => x"00000000", +213 => x"00000000", +214 => x"00000000", +215 => x"00000000", +216 => x"71810552", +217 => x"04000000", +218 => x"00000000", +219 => x"00000000", +220 => x"00000000", +221 => x"00000000", +222 => x"00000000", +223 => x"00000000", +224 => x"00000000", +225 => x"00000000", +226 => x"00000000", +227 => x"00000000", +228 => x"00000000", +229 => x"00000000", +230 => x"00000000", +231 => x"00000000", +232 => x"02840572", +233 => x"10100552", +234 => x"04000000", +235 => x"00000000", +236 => x"00000000", +237 => x"00000000", +238 => x"00000000", +239 => x"00000000", +240 => x"00000000", +241 => x"00000000", +242 => x"00000000", +243 => x"00000000", +244 => x"00000000", +245 => x"00000000", +246 => x"00000000", +247 => x"00000000", +248 => x"717105ff", +249 => x"0571530b", +250 => x"0b510400", +251 => x"00000000", +252 => x"00000000", +253 => x"00000000", +254 => x"00000000", +255 => x"00000000", +256 => x"83cd3f80", +257 => x"fd803f04", +258 => x"10101010", +259 => x"10101010", +260 => x"10101010", +261 => x"10101010", +262 => x"10101010", +263 => x"10101010", +264 => x"10101010", +265 => x"10101053", +266 => x"0b0b5104", +267 => x"7381ff06", +268 => x"73830609", +269 => x"81058305", +270 => x"1010102b", +271 => x"0772fc06", +272 => x"0c515104", +273 => x"3c047070", +274 => x"0b0b819a", +275 => x"90085284", +276 => x"0b720508", +277 => x"70810651", +278 => x"510b0b70", +279 => x"f2387108", +280 => x"81ff0680", +281 => x"0c505004", +282 => x"70700b0b", +283 => x"819a9008", +284 => x"52840b72", +285 => x"0508700a", +286 => x"100a7081", +287 => x"06515151", +288 => x"0b0b70ed", +289 => x"3873720c", +290 => x"50500481", +291 => x"8a840880", +292 => x"2ea83883", +293 => x"80800b0b", +294 => x"0b819a90", +295 => x"0c82a080", +296 => x"0b0b0b81", +297 => x"9a940c82", +298 => x"90800b81", +299 => x"9aa40c0b", +300 => x"0b819a98", +301 => x"0b819aa8", +302 => x"0c04f880", +303 => x"8080a40b", +304 => x"0b0b819a", +305 => x"900cf880", +306 => x"8082800b", +307 => x"0b0b819a", +308 => x"940cf880", +309 => x"8084800b", +310 => x"819aa40c", +311 => x"f8808080", +312 => x"940b819a", +313 => x"a80cf880", +314 => x"80809c0b", +315 => x"819aa00c", +316 => x"f8808080", +317 => x"a00b819a", +318 => x"ac0c04f2", +319 => x"3d0d600b", +320 => x"0b819a94", +321 => x"08565d82", +322 => x"750c8059", +323 => x"805a800b", +324 => x"8f3d7110", +325 => x"10177008", +326 => x"5a575d5b", +327 => x"807781ff", +328 => x"067c832b", +329 => x"5658520b", +330 => x"76530b0b", +331 => x"7b5183ae", +332 => x"3f7d7f7a", +333 => x"72077c72", +334 => x"07717160", +335 => x"8105415f", +336 => x"5d5b5957", +337 => x"557a8724", +338 => x"bf380b0b", +339 => x"819a9408", +340 => x"7b101071", +341 => x"05700859", +342 => x"51558077", +343 => x"81ff067c", +344 => x"832b5658", +345 => x"520b7653", +346 => x"0b0b7b51", +347 => x"82f03f7d", +348 => x"7f7a7207", +349 => x"7c720771", +350 => x"71608105", +351 => x"415f5d5b", +352 => x"59575587", +353 => x"7b25c338", +354 => x"767d0c77", +355 => x"841e0c7c", +356 => x"800c903d", +357 => x"0d047070", +358 => x"819a9c33", +359 => x"510b0b70", +360 => x"aa38818a", +361 => x"90087008", +362 => x"52520b70", +363 => x"802e9638", +364 => x"84720581", +365 => x"8a900c70", +366 => x"2d818a90", +367 => x"08700852", +368 => x"520b70ec", +369 => x"38810b81", +370 => x"9a9c3450", +371 => x"50040470", +372 => x"0b0b819a", +373 => x"8c08802e", +374 => x"8e380b0b", +375 => x"0b0b800b", +376 => x"802e0981", +377 => x"06833850", +378 => x"040b0b81", +379 => x"9a8c510b", +380 => x"0b0bf48c", +381 => x"3f500404", +382 => x"8c08028c", +383 => x"0cfa3d0d", +384 => x"800b8c08", +385 => x"fc050c8c", +386 => x"08fc0508", +387 => x"892481b9", +388 => x"388c08f0", +389 => x"05705253", +390 => x"0b0bfddf", +391 => x"3f8c08f4", +392 => x"05088c08", +393 => x"f8050c8c", +394 => x"08f80508", +395 => x"520b0b81", +396 => x"85b45187", +397 => x"c53f0b0b", +398 => x"8185c051", +399 => x"8a8b3f0b", +400 => x"0b8185d0", +401 => x"518a823f", +402 => x"fc0b819a", +403 => x"b00c819a", +404 => x"b008812c", +405 => x"530b0b72", +406 => x"fe2e8438", +407 => x"87903f8a", +408 => x"0b819ab4", +409 => x"0c819ab4", +410 => x"08819ab0", +411 => x"0829530b", +412 => x"0b72d82e", +413 => x"843886f6", +414 => x"3f8a0b81", +415 => x"9ab00c84", +416 => x"e2ad800b", +417 => x"819ab40c", +418 => x"819ab408", +419 => x"819ab008", +420 => x"29530b0b", +421 => x"72afd7c2", +422 => x"802e8438", +423 => x"86d03f81", +424 => x"0a0b819a", +425 => x"b00cff0b", +426 => x"819ab40c", +427 => x"819ab408", +428 => x"819ab008", +429 => x"25843886", +430 => x"b53f8c08", +431 => x"fc050881", +432 => x"058c08fc", +433 => x"050cfebf", +434 => x"398c08fc", +435 => x"05088a2e", +436 => x"8438869a", +437 => x"3f72800c", +438 => x"883d0d8c", +439 => x"0c048c08", +440 => x"028c0cf5", +441 => x"3d0d8c08", +442 => x"9405089f", +443 => x"388c088c", +444 => x"05088c08", +445 => x"9005088c", +446 => x"08880508", +447 => x"5856540b", +448 => x"0b73760c", +449 => x"7484170c", +450 => x"81cd3980", +451 => x"0b8c08f0", +452 => x"050c800b", +453 => x"8c08f405", +454 => x"0c8c088c", +455 => x"05088c08", +456 => x"90050856", +457 => x"540b0b73", +458 => x"8c08f005", +459 => x"0c748c08", +460 => x"f4050c8c", +461 => x"08f8058c", +462 => x"08f00556", +463 => x"56887054", +464 => x"0b0b7553", +465 => x"0b0b7652", +466 => x"540b0b85", +467 => x"ef3fa00b", +468 => x"8c089405", +469 => x"08318c08", +470 => x"ec050c8c", +471 => x"08ec0508", +472 => x"80249f38", +473 => x"800b8c08", +474 => x"f4050c8c", +475 => x"08ec0508", +476 => x"308c08fc", +477 => x"0508712b", +478 => x"8c08f005", +479 => x"0c540b0b", +480 => x"bb398c08", +481 => x"fc05088c", +482 => x"08ec0508", +483 => x"2a8c08e8", +484 => x"050c8c08", +485 => x"fc05088c", +486 => x"08940508", +487 => x"2b8c08f4", +488 => x"050c8c08", +489 => x"f805088c", +490 => x"08940508", +491 => x"2b708c08", +492 => x"e8050807", +493 => x"8c08f005", +494 => x"0c540b0b", +495 => x"8c08f005", +496 => x"088c08f4", +497 => x"05088c08", +498 => x"88050858", +499 => x"56540b0b", +500 => x"73760c74", +501 => x"84170c8c", +502 => x"08880508", +503 => x"800c8d3d", +504 => x"0d8c0c04", +505 => x"8c08028c", +506 => x"0cf93d0d", +507 => x"800b8c08", +508 => x"fc050c8c", +509 => x"08880508", +510 => x"8025ab38", +511 => x"8c088805", +512 => x"08308c08", +513 => x"88050c80", +514 => x"0b8c08f4", +515 => x"050c8c08", +516 => x"fc050888", +517 => x"38810b8c", +518 => x"08f4050c", +519 => x"8c08f405", +520 => x"088c08fc", +521 => x"050c8c08", +522 => x"8c050880", +523 => x"25ab388c", +524 => x"088c0508", +525 => x"308c088c", +526 => x"050c800b", +527 => x"8c08f005", +528 => x"0c8c08fc", +529 => x"05088838", +530 => x"810b8c08", +531 => x"f0050c8c", +532 => x"08f00508", +533 => x"8c08fc05", +534 => x"0c80530b", +535 => x"0b8c088c", +536 => x"0508528c", +537 => x"08880508", +538 => x"5181b13f", +539 => x"8008708c", +540 => x"08f8050c", +541 => x"540b0b8c", +542 => x"08fc0508", +543 => x"802e8c38", +544 => x"8c08f805", +545 => x"08308c08", +546 => x"f8050c8c", +547 => x"08f80508", +548 => x"70800c54", +549 => x"0b0b893d", +550 => x"0d8c0c04", +551 => x"8c08028c", +552 => x"0cfb3d0d", +553 => x"800b8c08", +554 => x"fc050c8c", +555 => x"08880508", +556 => x"80259338", +557 => x"8c088805", +558 => x"08308c08", +559 => x"88050c81", +560 => x"0b8c08fc", +561 => x"050c8c08", +562 => x"8c050880", +563 => x"258c388c", +564 => x"088c0508", +565 => x"308c088c", +566 => x"050c8153", +567 => x"0b0b8c08", +568 => x"8c050852", +569 => x"8c088805", +570 => x"0851b13f", +571 => x"8008708c", +572 => x"08f8050c", +573 => x"540b0b8c", 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x"050851ff", +4242 => x"8dd23f80", +4243 => x"0870800c", +4244 => x"540b0b50", +4245 => x"5050508c", +4246 => x"0c048c08", +4247 => x"028c0c70", +4248 => x"70707081", +4249 => x"530b0b8c", +4250 => x"088c0508", +4251 => x"528c0888", +4252 => x"050851ff", +4253 => x"8da63f80", +4254 => x"0870800c", +4255 => x"540b0b50", +4256 => x"5050508c", +4257 => x"0c047070", +4258 => x"819a800b", +4259 => x"fc057008", +4260 => x"52520b70", +4261 => x"ff2e9338", +4262 => x"702dfc72", +4263 => x"05700852", +4264 => x"520b70ff", +4265 => x"2e098106", +4266 => x"ef385050", +4267 => x"0404ff85", +4268 => x"e53f0400", +4269 => x"4379636c", +4270 => x"65732025", +4271 => x"640a0000", +4272 => x"48656c6c", +4273 => x"6f20776f", +4274 => x"726c6420", +4275 => x"310a0000", +4276 => x"48656c6c", +4277 => x"6f20776f", +4278 => x"726c6420", +4279 => x"320a0000", +4280 => x"0a000000", +4281 => x"20202020", +4282 => x"20202020", +4283 => x"20202020", +4284 => x"20202020", +4285 => x"30303030", +4286 => x"30303030", +4287 => x"30303030", +4288 => x"30303030", +4289 => x"000017e3", +4290 => x"0000138d", +4291 => x"0000138d", +4292 => x"000017d9", +4293 => x"0000138d", +4294 => x"0000138d", +4295 => x"0000138d", +4296 => x"0000138d", +4297 => x"0000138d", +4298 => x"0000138d", +4299 => x"00001364", +4300 => x"0000177e", +4301 => x"0000138d", +4302 => x"00001376", +4303 => x"000016ec", +4304 => x"0000138d", +4305 => x"000017af", +4306 => x"0000178a", +4307 => x"0000178a", +4308 => x"0000178a", +4309 => x"0000178a", +4310 => x"0000178a", +4311 => x"0000178a", +4312 => x"0000178a", +4313 => x"0000178a", +4314 => x"0000178a", +4315 => x"0000138d", +4316 => x"0000138d", +4317 => x"0000138d", +4318 => x"0000138d", +4319 => x"0000138d", +4320 => x"0000138d", +4321 => x"0000138d", +4322 => x"0000138d", +4323 => x"0000138d", +4324 => x"00001699", +4325 => x"00001326", +4326 => x"0000138d", +4327 => x"0000138d", +4328 => x"0000138d", +4329 => x"0000138d", +4330 => x"0000138d", +4331 => x"0000138d", +4332 => x"0000138d", +4333 => x"0000138d", +4334 => x"0000138d", +4335 => x"0000138d", +4336 => x"000012ec", +4337 => x"0000138d", +4338 => x"0000138d", +4339 => x"0000138d", +4340 => x"00001553", +4341 => x"0000138d", +4342 => x"00001015", +4343 => x"0000138d", +4344 => x"0000138d", +4345 => x"00001733", +4346 => x"0000138d", +4347 => x"0000138d", +4348 => x"0000138d", +4349 => x"0000138d", +4350 => x"0000138d", +4351 => x"0000138d", +4352 => x"0000138d", +4353 => x"0000138d", +4354 => x"0000138d", +4355 => x"0000138d", +4356 => x"00001699", +4357 => x"0000132a", +4358 => x"0000138d", +4359 => x"0000138d", +4360 => x"0000138d", +4361 => x"0000168e", +4362 => x"0000132a", +4363 => x"0000138d", +4364 => x"0000138d", +4365 => x"000015d8", +4366 => x"0000138d", +4367 => x"000015a8", +4368 => x"000012f0", +4369 => x"000015f7", +4370 => x"00001383", +4371 => x"0000138d", +4372 => x"00001553", +4373 => x"0000138d", +4374 => x"00001019", +4375 => x"0000138d", +4376 => x"0000138d", +4377 => x"000017ba", +4378 => x"62756720", +4379 => x"696e2076", +4380 => x"66707269", +4381 => x"6e74663a", +4382 => x"20626164", +4383 => x"20626173", +4384 => x"65000000", +4385 => x"30313233", +4386 => x"34353637", +4387 => x"38396162", +4388 => x"63646566", +4389 => x"00000000", +4390 => x"30313233", +4391 => x"34353637", +4392 => x"38394142", +4393 => x"43444546", +4394 => x"00000000", +4395 => x"286e756c", +4396 => x"6c290000", +4397 => x"432d5554", +4398 => x"462d3800", +4399 => x"432d534a", +4400 => x"49530000", +4401 => x"432d4555", +4402 => x"434a5000", +4403 => x"432d4a49", +4404 => x"53000000", +4405 => x"43000000", +4406 => x"2e000000", +4407 => x"49534f2d", +4408 => x"38383539", +4409 => x"2d310000", +4410 => x"64756d6d", +4411 => x"792e6578", +4412 => x"65000000", +4413 => x"00ffffff", +4414 => x"ff00ffff", +4415 => x"ffff00ff", +4416 => x"ffffff00", +4417 => x"00000000", +4418 => x"00000000", +4419 => x"00000000", +4420 => x"00004d08", +4421 => x"00004518", +4422 => x"00000000", +4423 => x"00004780", +4424 => x"000047dc", +4425 => x"00004838", +4426 => x"00000000", +4427 => x"00000000", +4428 => x"00000000", +4429 => x"00000000", +4430 => x"00000000", +4431 => x"00000000", +4432 => x"00000000", +4433 => x"00000000", +4434 => x"00000000", +4435 => x"000044d4", +4436 => x"00000000", +4437 => x"00000000", +4438 => x"00000000", +4439 => x"00000000", +4440 => x"00000000", +4441 => x"00000000", +4442 => x"00000000", +4443 => x"00000000", +4444 => x"00000000", +4445 => x"00000000", +4446 => x"00000000", +4447 => x"00000000", +4448 => x"00000000", +4449 => x"00000000", +4450 => x"00000000", +4451 => x"00000000", +4452 => x"00000000", +4453 => x"00000000", +4454 => x"00000000", +4455 => x"00000000", +4456 => x"00000000", +4457 => x"00000000", +4458 => x"00000000", +4459 => x"00000000", +4460 => x"00000000", +4461 => x"00000000", +4462 => x"00000000", +4463 => x"00000000", +4464 => x"00000001", +4465 => x"330eabcd", +4466 => x"1234e66d", +4467 => x"deec0005", +4468 => x"000b0000", +4469 => x"00000000", +4470 => x"00000000", +4471 => x"00000000", +4472 => x"00000000", +4473 => x"00000000", +4474 => x"00000000", +4475 => x"00000000", +4476 => x"00000000", +4477 => x"00000000", +4478 => x"00000000", +4479 => x"00000000", +4480 => x"00000000", +4481 => x"00000000", +4482 => x"00000000", +4483 => x"00000000", +4484 => x"00000000", +4485 => x"00000000", +4486 => x"00000000", +4487 => x"00000000", +4488 => x"00000000", +4489 => x"00000000", +4490 => x"00000000", +4491 => x"00000000", +4492 => x"00000000", +4493 => x"00000000", +4494 => x"00000000", +4495 => x"00000000", +4496 => x"00000000", +4497 => x"00000000", +4498 => x"00000000", +4499 => x"00000000", +4500 => x"00000000", +4501 => x"00000000", +4502 => x"00000000", +4503 => x"00000000", +4504 => x"00000000", +4505 => x"00000000", +4506 => x"00000000", +4507 => x"00000000", +4508 => x"00000000", +4509 => x"00000000", +4510 => x"00000000", +4511 => x"00000000", +4512 => x"00000000", +4513 => x"00000000", +4514 => x"00000000", +4515 => x"00000000", +4516 => x"00000000", +4517 => x"00000000", +4518 => x"00000000", +4519 => x"00000000", +4520 => x"00000000", +4521 => x"00000000", +4522 => x"00000000", +4523 => x"00000000", +4524 => x"00000000", +4525 => x"00000000", +4526 => x"00000000", +4527 => x"00000000", +4528 => x"00000000", +4529 => x"00000000", +4530 => x"00000000", +4531 => x"00000000", +4532 => x"00000000", +4533 => x"00000000", +4534 => x"00000000", +4535 => x"00000000", +4536 => x"00000000", +4537 => x"00000000", +4538 => x"00000000", +4539 => x"00000000", +4540 => x"00000000", +4541 => x"00000000", +4542 => x"00000000", +4543 => x"00000000", +4544 => x"00000000", +4545 => x"00000000", +4546 => x"00000000", +4547 => x"00000000", +4548 => x"00000000", +4549 => x"00000000", +4550 => x"00000000", +4551 => x"00000000", +4552 => x"00000000", +4553 => x"00000000", +4554 => x"00000000", +4555 => x"00000000", +4556 => x"00000000", +4557 => x"00000000", +4558 => x"00000000", +4559 => x"00000000", +4560 => x"00000000", +4561 => x"00000000", +4562 => x"00000000", +4563 => x"00000000", +4564 => x"00000000", +4565 => x"00000000", +4566 => x"00000000", +4567 => x"00000000", +4568 => x"00000000", +4569 => x"00000000", +4570 => x"00000000", +4571 => x"00000000", +4572 => x"00000000", +4573 => x"00000000", +4574 => x"00000000", +4575 => x"00000000", +4576 => x"00000000", +4577 => x"00000000", +4578 => x"00000000", +4579 => x"00000000", +4580 => x"00000000", +4581 => x"00000000", +4582 => x"00000000", +4583 => x"00000000", +4584 => x"00000000", +4585 => x"00000000", +4586 => x"00000000", +4587 => x"00000000", +4588 => x"00000000", +4589 => x"00000000", +4590 => x"00000000", +4591 => x"00000000", +4592 => x"00000000", +4593 => x"00000000", +4594 => x"00000000", +4595 => x"00000000", +4596 => x"00000000", +4597 => x"00000000", +4598 => x"00000000", +4599 => x"00000000", +4600 => x"00000000", +4601 => x"00000000", +4602 => x"00000000", +4603 => x"00000000", +4604 => x"00000000", +4605 => x"00000000", +4606 => x"00000000", +4607 => x"00000000", +4608 => x"00000000", +4609 => x"00000000", +4610 => x"00000000", +4611 => x"00000000", +4612 => x"00000000", +4613 => x"00000000", +4614 => x"00000000", +4615 => x"00000000", +4616 => x"00000000", +4617 => x"00000000", +4618 => x"00000000", +4619 => x"00000000", +4620 => x"00000000", +4621 => x"00000000", +4622 => x"00000000", +4623 => x"00000000", +4624 => x"00000000", +4625 => x"00000000", +4626 => x"00000000", +4627 => x"00000000", +4628 => x"00000000", +4629 => x"00000000", +4630 => x"00000000", +4631 => x"00000000", +4632 => x"00000000", +4633 => x"00000000", +4634 => x"00000000", +4635 => x"00000000", +4636 => x"00000000", +4637 => x"00000000", +4638 => x"00000000", +4639 => x"00000000", +4640 => x"00000000", +4641 => x"00000000", +4642 => x"00000000", +4643 => x"00000000", +4644 => x"00000000", +4645 => x"43000000", +4646 => x"00000000", +4647 => x"00000000", +4648 => x"00000000", +4649 => x"00000000", +4650 => x"00000000", +4651 => x"00000001", +4652 => x"000044dc", +4653 => x"00000000", +4654 => x"00000000", +4655 => x"00000000", +4656 => x"00000000", +4657 => x"00000000", +4658 => x"00000000", +4659 => x"00000000", +4660 => x"00000000", +4661 => x"00000000", +4662 => x"00000000", +4663 => x"00000000", +4664 => x"00000000", +4665 => x"ffffffff", +4666 => x"00000000", +4667 => x"00020000", +4668 => x"00000000", +4669 => x"00000000", +4670 => x"000048f0", +4671 => x"000048f0", +4672 => x"000048f8", +4673 => x"000048f8", +4674 => x"00004900", +4675 => x"00004900", +4676 => x"00004908", +4677 => x"00004908", +4678 => x"00004910", +4679 => x"00004910", +4680 => x"00004918", +4681 => x"00004918", +4682 => x"00004920", +4683 => x"00004920", +4684 => x"00004928", +4685 => x"00004928", +4686 => x"00004930", +4687 => x"00004930", +4688 => x"00004938", +4689 => x"00004938", +4690 => x"00004940", +4691 => x"00004940", +4692 => x"00004948", +4693 => x"00004948", +4694 => x"00004950", +4695 => x"00004950", +4696 => x"00004958", +4697 => x"00004958", +4698 => x"00004960", +4699 => x"00004960", +4700 => x"00004968", +4701 => x"00004968", +4702 => x"00004970", +4703 => x"00004970", +4704 => x"00004978", +4705 => x"00004978", +4706 => x"00004980", +4707 => x"00004980", +4708 => x"00004988", +4709 => x"00004988", +4710 => x"00004990", +4711 => x"00004990", +4712 => x"00004998", +4713 => x"00004998", +4714 => x"000049a0", +4715 => x"000049a0", +4716 => x"000049a8", +4717 => x"000049a8", +4718 => x"000049b0", +4719 => x"000049b0", +4720 => x"000049b8", +4721 => x"000049b8", +4722 => x"000049c0", +4723 => x"000049c0", +4724 => x"000049c8", +4725 => x"000049c8", +4726 => x"000049d0", +4727 => x"000049d0", +4728 => x"000049d8", +4729 => x"000049d8", +4730 => x"000049e0", +4731 => x"000049e0", +4732 => x"000049e8", +4733 => x"000049e8", +4734 => x"000049f0", +4735 => x"000049f0", +4736 => x"000049f8", +4737 => x"000049f8", +4738 => x"00004a00", +4739 => x"00004a00", +4740 => x"00004a08", +4741 => x"00004a08", +4742 => x"00004a10", +4743 => x"00004a10", +4744 => x"00004a18", +4745 => x"00004a18", +4746 => x"00004a20", +4747 => x"00004a20", +4748 => x"00004a28", +4749 => x"00004a28", +4750 => x"00004a30", +4751 => x"00004a30", +4752 => x"00004a38", +4753 => x"00004a38", +4754 => x"00004a40", +4755 => x"00004a40", +4756 => x"00004a48", +4757 => x"00004a48", +4758 => x"00004a50", +4759 => x"00004a50", +4760 => x"00004a58", +4761 => x"00004a58", +4762 => x"00004a60", +4763 => x"00004a60", +4764 => x"00004a68", +4765 => x"00004a68", +4766 => x"00004a70", +4767 => x"00004a70", +4768 => x"00004a78", +4769 => x"00004a78", +4770 => x"00004a80", +4771 => x"00004a80", +4772 => x"00004a88", +4773 => x"00004a88", +4774 => x"00004a90", +4775 => x"00004a90", +4776 => x"00004a98", +4777 => x"00004a98", +4778 => x"00004aa0", +4779 => x"00004aa0", +4780 => x"00004aa8", +4781 => x"00004aa8", +4782 => x"00004ab0", +4783 => x"00004ab0", +4784 => x"00004ab8", +4785 => x"00004ab8", +4786 => x"00004ac0", +4787 => x"00004ac0", +4788 => x"00004ac8", +4789 => x"00004ac8", +4790 => x"00004ad0", +4791 => x"00004ad0", +4792 => x"00004ad8", +4793 => x"00004ad8", +4794 => x"00004ae0", +4795 => x"00004ae0", +4796 => x"00004ae8", +4797 => x"00004ae8", +4798 => x"00004af0", +4799 => x"00004af0", +4800 => x"00004af8", +4801 => x"00004af8", +4802 => x"00004b00", +4803 => x"00004b00", +4804 => x"00004b08", +4805 => x"00004b08", +4806 => x"00004b10", +4807 => x"00004b10", +4808 => x"00004b18", +4809 => x"00004b18", +4810 => x"00004b20", +4811 => x"00004b20", +4812 => x"00004b28", +4813 => x"00004b28", +4814 => x"00004b30", +4815 => x"00004b30", +4816 => x"00004b38", +4817 => x"00004b38", +4818 => x"00004b40", +4819 => x"00004b40", +4820 => x"00004b48", +4821 => x"00004b48", +4822 => x"00004b50", +4823 => x"00004b50", +4824 => x"00004b58", +4825 => x"00004b58", +4826 => x"00004b60", +4827 => x"00004b60", +4828 => x"00004b68", +4829 => x"00004b68", +4830 => x"00004b70", +4831 => x"00004b70", +4832 => x"00004b78", +4833 => x"00004b78", +4834 => x"00004b80", +4835 => x"00004b80", +4836 => x"00004b88", +4837 => x"00004b88", +4838 => x"00004b90", +4839 => x"00004b90", +4840 => x"00004b98", +4841 => x"00004b98", +4842 => x"00004ba0", +4843 => x"00004ba0", +4844 => x"00004ba8", +4845 => x"00004ba8", +4846 => x"00004bb0", +4847 => x"00004bb0", +4848 => x"00004bb8", +4849 => x"00004bb8", +4850 => x"00004bc0", +4851 => x"00004bc0", +4852 => x"00004bc8", +4853 => x"00004bc8", +4854 => x"00004bd0", +4855 => x"00004bd0", +4856 => x"00004bd8", +4857 => x"00004bd8", +4858 => x"00004be0", +4859 => x"00004be0", +4860 => x"00004be8", +4861 => x"00004be8", +4862 => x"00004bf0", +4863 => x"00004bf0", +4864 => x"00004bf8", +4865 => x"00004bf8", +4866 => x"00004c00", +4867 => x"00004c00", +4868 => x"00004c08", +4869 => x"00004c08", +4870 => x"00004c10", +4871 => x"00004c10", +4872 => x"00004c18", +4873 => x"00004c18", +4874 => x"00004c20", +4875 => x"00004c20", +4876 => x"00004c28", +4877 => x"00004c28", +4878 => x"00004c30", +4879 => x"00004c30", +4880 => x"00004c38", +4881 => x"00004c38", +4882 => x"00004c40", +4883 => x"00004c40", +4884 => x"00004c48", +4885 => x"00004c48", +4886 => x"00004c50", +4887 => x"00004c50", +4888 => x"00004c58", +4889 => x"00004c58", +4890 => x"00004c60", +4891 => x"00004c60", +4892 => x"00004c68", +4893 => x"00004c68", +4894 => x"00004c70", +4895 => x"00004c70", +4896 => x"00004c78", +4897 => x"00004c78", +4898 => x"00004c80", +4899 => x"00004c80", +4900 => x"00004c88", +4901 => x"00004c88", +4902 => x"00004c90", +4903 => x"00004c90", +4904 => x"00004c98", +4905 => x"00004c98", +4906 => x"00004ca0", +4907 => x"00004ca0", +4908 => x"00004ca8", +4909 => x"00004ca8", +4910 => x"00004cb0", +4911 => x"00004cb0", +4912 => x"00004cb8", +4913 => x"00004cb8", +4914 => x"00004cc0", +4915 => x"00004cc0", +4916 => x"00004cc8", +4917 => x"00004cc8", +4918 => x"00004cd0", +4919 => x"00004cd0", +4920 => x"00004cd8", +4921 => x"00004cd8", +4922 => x"00004ce0", +4923 => x"00004ce0", +4924 => x"00004ce8", +4925 => x"00004ce8", +4926 => x"000044e8", +4927 => x"ffffffff", +4928 => x"00000000", +4929 => x"ffffffff", +4930 => x"00000000", + others => x"00000000" +); + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then + report "write collision" severity failure; + end if; + + if (memAWriteEnable = '1') then + ram(conv_integer(memAAddr)) := memAWrite; + memARead <= memAWrite; + else + memARead <= ram(conv_integer(memAAddr)); + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (memBWriteEnable = '1') then + ram(conv_integer(memBAddr)) := memBWrite; + memBRead <= memBWrite; + else + memBRead <= ram(conv_integer(memBAddr)); + end if; + end if; +end process; + + + + +end dualport_ram_arch; diff --git a/zpu/hdl/zpu3/src/dualport_ram_synplicity.vhd b/zpu/hdl/zpu3/src/dualport_ram_synplicity.vhd new file mode 100644 index 0000000..83a7de2 --- /dev/null +++ b/zpu/hdl/zpu3/src/dualport_ram_synplicity.vhd @@ -0,0 +1,5012 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + + +library zylin; +use zylin.zpu_config.all; +use zylin.zpupkg.all; + +entity dualport_ram is +port (clk : in std_logic; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit); + memAWrite : in std_logic_vector(wordSize-1 downto 0); + memARead : out std_logic_vector(wordSize-1 downto 0); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit); + memBWrite : in std_logic_vector(wordSize-1 downto 0); + memBRead : out std_logic_vector(wordSize-1 downto 0)); +end dualport_ram; + +architecture dualport_ram_arch of dualport_ram is + + +type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); + + +--shared variable ram : ram_type := +signal ram : ram_type := +( +0 => x"800b0b0b", +1 => x"0b0b8070", +2 => x"0b0b818a", +3 => x"dc0c3a0b", +4 => x"0b80dab4", +5 => x"04000000", +6 => x"00000000", +7 => x"00000000", +8 => x"80088408", +9 => x"88080b0b", +10 => x"80db972d", +11 => x"880c840c", +12 => x"800c0400", +13 => x"00000000", +14 => x"00000000", +15 => x"00000000", +16 => x"71fd0608", +17 => x"72830609", +18 => x"81058205", +19 => x"832b0b2a", +20 => x"83ffff06", +21 => x"52810504", +22 => x"00000000", +23 => x"00000000", +24 => x"71fd0608", +25 => x"83ffff73", +26 => x"83060981", +27 => x"05820583", +28 => x"2b0b2b09", +29 => x"067383ff", +30 => x"ff0b0b0b", +31 => x"0b83a704", +32 => x"72098105", +33 => x"72057373", +34 => x"09060906", +35 => x"73097306", +36 => x"070a8106", +37 => x"53518105", +38 => x"04000000", +39 => x"00000000", +40 => x"72722473", +41 => x"732e0753", +42 => x"51810504", +43 => x"00000000", +44 => x"00000000", +45 => x"00000000", +46 => x"00000000", +47 => x"00000000", +48 => x"71737109", +49 => x"71068106", +50 => x"30720a10", +51 => x"0a720a10", +52 => x"0a31050a", +53 => x"81065151", +54 => x"53518105", +55 => x"04000000", +56 => x"72722673", +57 => x"732e0753", +58 => x"51810504", +59 => x"00000000", +60 => x"00000000", +61 => x"00000000", +62 => x"00000000", +63 => x"00000000", +64 => x"72ff0571", +65 => x"81050673", +66 => x"ff050972", +67 => x"74058005", +68 => x"06075350", +69 => x"50040000", +70 => x"00000000", +71 => x"00000000", +72 => x"0b0b0b8c", +73 => x"f8040000", +74 => x"00000000", +75 => x"00000000", +76 => x"00000000", +77 => x"00000000", +78 => x"00000000", +79 => x"00000000", +80 => x"720a722b", +81 => x"0a535181", +82 => x"05040000", +83 => x"00000000", +84 => x"00000000", +85 => x"00000000", +86 => x"00000000", +87 => x"00000000", +88 => x"72729f06", +89 => x"0981050b", +90 => x"0b0b88a7", +91 => x"05040000", +92 => x"00000000", +93 => x"00000000", +94 => x"00000000", +95 => x"00000000", +96 => x"72722aff", +97 => x"739f062a", +98 => x"0974090a", +99 => x"8106ff05", +100 => x"06075351", +101 => x"81050400", +102 => x"00000000", +103 => x"00000000", +104 => x"71718105", +105 => x"53510406", +106 => x"73830609", +107 => x"81058205", +108 => x"832b0b2b", +109 => x"0772fc06", +110 => x"0c515181", +111 => x"05040000", +112 => x"72098105", +113 => x"72050970", +114 => x"81050906", +115 => x"0a810653", +116 => x"51810504", +117 => x"00000000", +118 => x"00000000", +119 => x"00000000", +120 => x"72098105", +121 => x"72050970", +122 => x"81050906", +123 => x"0a098106", +124 => x"53518105", +125 => x"04000000", +126 => x"00000000", +127 => x"00000000", +128 => x"71098105", +129 => x"52810504", +130 => x"00000000", +131 => x"00000000", +132 => x"00000000", +133 => x"00000000", +134 => x"00000000", +135 => x"00000000", +136 => x"72720981", +137 => x"05055351", +138 => x"81050409", +139 => x"81058305", +140 => x"1010102b", +141 => x"0772fc06", +142 => x"0c515181", +143 => x"05040000", +144 => x"72097206", +145 => x"73730906", +146 => x"07535181", +147 => x"05040000", +148 => x"00000000", +149 => x"00000000", +150 => x"00000000", +151 => x"00000000", +152 => x"71fc0608", +153 => x"72830609", +154 => x"81058305", +155 => x"1010102a", +156 => x"81ff0652", +157 => x"81050400", +158 => x"00000000", +159 => x"00000000", +160 => x"71fc0608", +161 => x"0b0b818a", +162 => x"88738306", +163 => x"10100508", +164 => x"067381ff", +165 => x"06738306", +166 => x"0b0b0b84", +167 => x"ab040000", +168 => x"80088408", +169 => x"88087575", +170 => x"0b0b0bb3", +171 => x"912d5050", +172 => x"80085688", +173 => x"0c840c80", +174 => x"0c810551", +175 => x"04000000", +176 => x"80088408", +177 => x"88087575", +178 => x"0b0b0bb4", +179 => x"8a2d5050", +180 => x"80085688", +181 => x"0c840c80", +182 => x"0c810551", +183 => x"04000000", +184 => x"72097081", +185 => x"0509060a", +186 => x"8106ff05", +187 => x"70547181", +188 => x"05067309", +189 => x"72740580", +190 => x"05060753", +191 => x"50500400", +192 => x"72097081", +193 => x"0509060a", +194 => x"098106ff", +195 => x"05705471", +196 => x"81050673", +197 => x"09727405", +198 => x"80050607", +199 => x"53505004", +200 => x"05800504", +201 => x"00000000", +202 => x"00000000", +203 => x"00000000", +204 => x"00000000", +205 => x"00000000", +206 => x"00000000", +207 => x"00000000", +208 => x"810b0b0b", +209 => x"818ad80c", +210 => x"51810504", +211 => x"00000000", +212 => x"00000000", +213 => x"00000000", +214 => x"00000000", +215 => x"00000000", +216 => x"72830610", +217 => x"10728306", +218 => x"0710100b", +219 => x"0b818a98", +220 => x"05080400", +221 => x"00000000", +222 => x"00000000", +223 => x"00000000", +224 => x"00000000", +225 => x"00000000", +226 => x"00000000", +227 => x"00000000", +228 => x"00000000", +229 => x"00000000", +230 => x"00000000", +231 => x"00000000", +232 => x"02840572", +233 => x"10100552", +234 => x"81050400", +235 => x"00000000", +236 => x"00000000", +237 => x"00000000", +238 => x"00000000", +239 => x"00000000", +240 => x"00000000", +241 => x"00000000", +242 => x"00000000", +243 => x"00000000", +244 => x"00000000", +245 => x"00000000", +246 => x"00000000", +247 => x"00000000", +248 => x"71710571", +249 => x"81055351", +250 => x"04000000", +251 => x"00000000", +252 => x"00000000", +253 => x"00000000", +254 => x"00000000", +255 => x"00000000", +256 => x"8db33f80", +257 => x"f39e3f04", +258 => x"10101010", +259 => x"10101010", +260 => x"10101010", +261 => x"10101010", +262 => x"10101010", +263 => x"10101010", +264 => x"10101010", +265 => x"10101053", +266 => x"51810504", +267 => x"72fc0608", +268 => x"81ff0a06", +269 => x"72fc0670", +270 => x"5408fe80", +271 => x"0a060772", +272 => x"0c515181", +273 => x"050472fc", +274 => x"06080a10", +275 => x"10101010", +276 => x"1010100a", +277 => x"87fc8080", +278 => x"0672fc06", +279 => x"08f883ff", +280 => x"ff060772", +281 => x"fc060c51", +282 => x"51810504", +283 => x"72fc0608", +284 => x"0a101010", +285 => x"10101010", +286 => x"10101010", +287 => x"10101010", +288 => x"100a83fe", +289 => x"800672fc", +290 => x"0608fc81", +291 => x"ff060772", +292 => x"fc060c51", +293 => x"51810504", +294 => x"72fc0608", +295 => x"0a101010", +296 => x"10101010", +297 => x"10101010", +298 => x"10101010", +299 => x"10101010", +300 => x"10101010", +301 => x"100a81ff", +302 => x"0672fc06", +303 => x"08fe8006", +304 => x"0772fc06", +305 => x"0c515181", +306 => x"050472fc", +307 => x"06081010", +308 => x"10101010", +309 => x"101081ff", +310 => x"0a0672fc", +311 => x"0608fe80", +312 => x"0a060772", +313 => x"fc060c51", +314 => x"51810504", +315 => x"72fc0608", +316 => x"87fc8080", +317 => x"0672fc06", +318 => x"705408f8", +319 => x"83ffff06", +320 => x"07720c51", +321 => x"51810504", +322 => x"72fc0608", +323 => x"0a101010", +324 => x"10101010", +325 => x"100a83fe", +326 => x"800672fc", +327 => x"0608fc81", +328 => x"ff060772", +329 => x"fc060c51", +330 => x"51810504", +331 => x"72fc0608", +332 => x"0a101010", +333 => x"10101010", +334 => x"10101010", +335 => x"10101010", +336 => x"100a81ff", +337 => x"0672fc06", +338 => x"08fe8006", +339 => x"0772fc06", +340 => x"0c515181", +341 => x"050472fc", +342 => x"06081010", +343 => x"10101010", +344 => x"10101010", +345 => x"10101010", +346 => x"101081ff", +347 => x"0a0672fc", +348 => x"0608fe80", +349 => x"0a060772", +350 => x"fc060c51", +351 => x"51810504", +352 => x"72fc0608", +353 => x"10101010", +354 => x"10101010", +355 => x"87fc8080", +356 => x"0672fc06", +357 => x"08f883ff", +358 => x"ff060772", +359 => x"fc060c51", +360 => x"51810504", +361 => x"72fc0608", +362 => x"83fe8006", +363 => x"72fc0670", +364 => x"5408fc81", +365 => x"ff060772", +366 => x"0c515181", +367 => x"050472fc", +368 => x"06080a10", +369 => x"10101010", +370 => x"1010100a", +371 => x"81ff0672", +372 => x"fc0608fe", +373 => x"80060772", +374 => x"fc060c51", +375 => x"51810504", +376 => x"72fc0608", +377 => x"10101010", +378 => x"10101010", +379 => x"10101010", +380 => x"10101010", +381 => x"10101010", +382 => x"10101010", +383 => x"81ff0a06", +384 => x"72fc0608", +385 => x"fe800a06", +386 => x"0772fc06", +387 => x"0c515181", +388 => x"050472fc", +389 => x"06081010", +390 => x"10101010", +391 => x"10101010", +392 => x"10101010", +393 => x"101087fc", +394 => x"80800672", +395 => x"fc0608f8", +396 => x"83ffff06", +397 => x"0772fc06", +398 => x"0c515181", +399 => x"050472fc", +400 => x"06081010", +401 => x"10101010", +402 => x"101083fe", +403 => x"800672fc", +404 => x"0608fc81", +405 => x"ff060772", +406 => x"fc060c51", +407 => x"51810504", +408 => x"72fc0608", +409 => x"81ff0672", +410 => x"fc067054", +411 => x"08fe8006", +412 => x"07720c51", +413 => x"51810504", +414 => x"72728072", +415 => x"8106ff05", +416 => x"09720605", +417 => x"71105272", +418 => x"0a100a53", +419 => x"728106ff", +420 => x"05097206", +421 => x"05711052", +422 => x"720a100a", +423 => x"53728106", +424 => x"ff050972", +425 => x"06057110", +426 => x"52720a10", +427 => x"0a537281", +428 => x"06ff0509", +429 => x"72060571", +430 => x"1052720a", +431 => x"100a5372", +432 => x"8106ff05", +433 => x"09720605", +434 => x"71105272", +435 => x"0a100a53", +436 => x"728106ff", +437 => x"05097206", +438 => x"05711052", +439 => x"720a100a", +440 => x"53728106", +441 => x"ff050972", +442 => x"06057110", +443 => x"52720a10", +444 => x"0a537281", +445 => x"06ff0509", +446 => x"72060571", +447 => x"1052720a", +448 => x"100a5372", +449 => x"83a13772", +450 => x"8106ff05", +451 => x"09720605", +452 => x"71105272", +453 => x"0a100a53", +454 => x"728106ff", +455 => x"05097206", +456 => x"05711052", +457 => x"720a100a", +458 => x"53728106", +459 => x"ff050972", +460 => x"06057110", +461 => x"52720a10", +462 => x"0a537281", +463 => x"06ff0509", +464 => x"72060571", +465 => x"1052720a", +466 => x"100a5372", +467 => x"8106ff05", +468 => x"09720605", +469 => x"71105272", +470 => x"0a100a53", +471 => x"728106ff", +472 => x"05097206", +473 => x"05711052", +474 => x"720a100a", +475 => x"53728106", +476 => x"ff050972", +477 => x"06057110", +478 => x"52720a10", +479 => x"0a537281", +480 => x"06ff0509", +481 => x"72060571", +482 => x"1052720a", +483 => x"100a5372", +484 => x"82953772", +485 => x"8106ff05", +486 => x"09720605", +487 => x"71105272", +488 => x"0a100a53", +489 => x"728106ff", +490 => x"05097206", +491 => x"05711052", +492 => x"720a100a", +493 => x"53728106", +494 => x"ff050972", +495 => x"06057110", +496 => x"52720a10", +497 => x"0a537281", +498 => x"06ff0509", +499 => x"72060571", +500 => x"1052720a", +501 => x"100a5372", +502 => x"8106ff05", +503 => x"09720605", +504 => x"71105272", +505 => x"0a100a53", +506 => x"728106ff", +507 => x"05097206", +508 => x"05711052", +509 => x"720a100a", +510 => x"53728106", +511 => x"ff050972", +512 => x"06057110", +513 => x"52720a10", +514 => x"0a537281", +515 => x"06ff0509", +516 => x"72060571", +517 => x"1052720a", +518 => x"100a5372", +519 => x"81893772", +520 => x"8106ff05", +521 => x"09720605", +522 => x"71105272", +523 => x"0a100a53", +524 => x"728106ff", +525 => x"05097206", +526 => x"05711052", +527 => x"720a100a", +528 => x"53728106", +529 => x"ff050972", +530 => x"06057110", +531 => x"52720a10", +532 => x"0a537281", +533 => x"06ff0509", +534 => x"72060571", +535 => x"1052720a", +536 => x"100a5372", +537 => x"8106ff05", +538 => x"09720605", +539 => x"71105272", +540 => x"0a100a53", +541 => x"728106ff", +542 => x"05097206", +543 => x"05711052", +544 => x"720a100a", +545 => x"53728106", +546 => x"ff050972", +547 => x"06057110", +548 => x"52720a10", +549 => x"0a537281", +550 => x"06ff0509", +551 => x"72060571", +552 => x"1052720a", +553 => x"100a5351", +554 => x"51535181", +555 => x"05043c04", +556 => x"70700b0b", +557 => x"819acc08", +558 => x"52841208", +559 => x"70810651", +560 => x"51700970", +561 => x"81050906", +562 => x"0a098106", +563 => x"ff0509e9", +564 => x"0bf70506", +565 => x"84010505", +566 => x"04710881", +567 => x"ff06800c", +568 => x"50500470", +569 => x"700b0b81", +570 => x"9acc0852", +571 => x"84120870", +572 => x"0a100a70", +573 => x"81065151", +574 => x"51700970", +575 => x"81050906", +576 => x"0a098106", +577 => x"ff0509e4", +578 => x"0bf70506", +579 => x"84010505", +580 => x"0473720c", +581 => x"50500481", +582 => x"8ad80809", +583 => x"70810509", +584 => x"060a8106", +585 => x"ff0509b0", +586 => x"0bf70506", +587 => x"84010505", +588 => x"04838080", +589 => x"0b0b0b81", +590 => x"9acc0c82", +591 => x"a0800b0b", +592 => x"0b819ad0", +593 => x"0c829080", +594 => x"0b819ae0", +595 => x"0c0b0b81", +596 => x"9ad40b81", +597 => x"9ae40c04", +598 => x"f8808080", +599 => x"a40b0b0b", +600 => x"819acc0c", +601 => x"f8808082", +602 => x"800b0b0b", +603 => x"819ad00c", +604 => x"f8808084", +605 => x"800b819a", +606 => x"e00cf880", +607 => x"8080940b", +608 => x"819ae40c", +609 => x"f8808080", +610 => x"9c0b819a", +611 => x"dc0cf880", +612 => x"8080a00b", +613 => x"819ae80c", +614 => x"04f23d0d", +615 => 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x"00004714", +4552 => x"00004714", +4553 => x"0000471c", +4554 => x"0000471c", +4555 => x"00004724", +4556 => x"00004724", +4557 => x"0000472c", +4558 => x"0000472c", +4559 => x"00004734", +4560 => x"00004734", +4561 => x"0000473c", +4562 => x"0000473c", +4563 => x"00004744", +4564 => x"00004744", +4565 => x"0000474c", +4566 => x"0000474c", +4567 => x"00004754", +4568 => x"00004754", +4569 => x"0000475c", +4570 => x"0000475c", +4571 => x"00004764", +4572 => x"00004764", +4573 => x"0000476c", +4574 => x"0000476c", +4575 => x"00004774", +4576 => x"00004774", +4577 => x"0000477c", +4578 => x"0000477c", +4579 => x"00004784", +4580 => x"00004784", +4581 => x"0000478c", +4582 => x"0000478c", +4583 => x"00004794", +4584 => x"00004794", +4585 => x"0000479c", +4586 => x"0000479c", +4587 => x"000047a4", +4588 => x"000047a4", +4589 => x"000047ac", +4590 => x"000047ac", +4591 => x"000047b4", +4592 => x"000047b4", +4593 => x"000047bc", +4594 => x"000047bc", +4595 => x"000047c4", +4596 => x"000047c4", +4597 => x"000047cc", +4598 => x"000047cc", +4599 => x"000047d4", +4600 => x"000047d4", +4601 => x"000047dc", +4602 => x"000047dc", +4603 => x"000047e4", +4604 => x"000047e4", +4605 => x"000047ec", +4606 => x"000047ec", +4607 => x"000047f4", +4608 => x"000047f4", +4609 => x"000047fc", +4610 => x"000047fc", +4611 => x"00004804", +4612 => x"00004804", +4613 => x"0000480c", +4614 => x"0000480c", +4615 => x"00004814", +4616 => x"00004814", +4617 => x"0000481c", +4618 => x"0000481c", +4619 => x"00004824", +4620 => x"00004824", +4621 => x"0000482c", +4622 => x"0000482c", +4623 => x"00004834", +4624 => x"00004834", +4625 => x"0000483c", +4626 => x"0000483c", +4627 => x"00004844", +4628 => x"00004844", +4629 => x"0000484c", +4630 => x"0000484c", +4631 => x"00004854", +4632 => x"00004854", +4633 => x"0000485c", +4634 => x"0000485c", +4635 => x"00004864", +4636 => x"00004864", +4637 => x"0000486c", +4638 => x"0000486c", +4639 => x"00004874", +4640 => x"00004874", +4641 => x"0000487c", +4642 => x"0000487c", +4643 => x"00004884", +4644 => x"00004884", +4645 => x"0000488c", +4646 => x"0000488c", +4647 => x"00004894", +4648 => x"00004894", +4649 => x"0000489c", +4650 => x"0000489c", +4651 => x"000048a4", +4652 => x"000048a4", +4653 => x"000048ac", +4654 => x"000048ac", +4655 => x"000048b4", +4656 => x"000048b4", +4657 => x"000048bc", +4658 => x"000048bc", +4659 => x"000048c4", +4660 => x"000048c4", +4661 => x"000048cc", +4662 => x"000048cc", +4663 => x"000048d4", +4664 => x"000048d4", +4665 => x"000048dc", +4666 => x"000048dc", +4667 => x"000048e4", +4668 => x"000048e4", +4669 => x"000048ec", +4670 => x"000048ec", +4671 => x"000048f4", +4672 => x"000048f4", +4673 => x"000048fc", +4674 => x"000048fc", +4675 => x"00004904", +4676 => x"00004904", +4677 => x"0000490c", +4678 => x"0000490c", +4679 => x"00004914", +4680 => x"00004914", +4681 => x"0000491c", +4682 => x"0000491c", +4683 => x"00004924", +4684 => x"00004924", +4685 => x"0000492c", +4686 => x"0000492c", +4687 => x"00004934", +4688 => x"00004934", +4689 => x"0000493c", +4690 => x"0000493c", +4691 => x"00004944", +4692 => x"00004944", +4693 => x"0000494c", +4694 => x"0000494c", +4695 => x"00004954", +4696 => x"00004954", +4697 => x"0000495c", +4698 => x"0000495c", +4699 => x"00004964", +4700 => x"00004964", +4701 => x"0000496c", +4702 => x"0000496c", +4703 => x"00004974", +4704 => x"00004974", +4705 => x"0000497c", +4706 => x"0000497c", +4707 => x"00004984", +4708 => x"00004984", +4709 => x"0000498c", +4710 => x"0000498c", +4711 => x"00004994", +4712 => x"00004994", +4713 => x"0000499c", +4714 => x"0000499c", +4715 => x"000049a4", +4716 => x"000049a4", +4717 => x"000049b8", +4718 => x"00000000", +4719 => x"00004c20", +4720 => x"00004c7c", +4721 => x"00004cd8", +4722 => x"00000000", +4723 => x"00000000", +4724 => x"00000000", +4725 => x"00000000", +4726 => x"00000000", +4727 => x"00000000", +4728 => x"00000000", +4729 => x"00000000", +4730 => x"00000000", +4731 => x"000043f8", +4732 => x"00000000", +4733 => x"00000000", +4734 => x"00000000", +4735 => x"00000000", +4736 => x"00000000", +4737 => x"00000000", +4738 => x"00000000", +4739 => x"00000000", +4740 => x"00000000", +4741 => x"00000000", +4742 => x"00000000", +4743 => x"00000000", +4744 => x"00000000", +4745 => x"00000000", +4746 => x"00000000", +4747 => x"00000000", +4748 => x"00000000", +4749 => x"00000000", +4750 => x"00000000", +4751 => x"00000000", +4752 => x"00000000", +4753 => x"00000000", +4754 => x"00000000", +4755 => x"00000000", +4756 => x"00000000", +4757 => x"00000000", +4758 => x"00000000", +4759 => x"00000000", +4760 => x"00000001", +4761 => x"330eabcd", +4762 => x"1234e66d", +4763 => x"deec0005", +4764 => x"000b0000", +4765 => x"00000000", +4766 => x"00000000", +4767 => x"00000000", +4768 => x"00000000", +4769 => x"00000000", +4770 => x"00000000", +4771 => x"00000000", +4772 => x"00000000", +4773 => x"00000000", +4774 => x"00000000", +4775 => x"00000000", +4776 => x"00000000", +4777 => x"00000000", +4778 => x"00000000", +4779 => x"00000000", +4780 => x"00000000", +4781 => x"00000000", +4782 => x"00000000", +4783 => x"00000000", +4784 => x"00000000", +4785 => x"00000000", +4786 => x"00000000", +4787 => x"00000000", +4788 => x"00000000", +4789 => x"00000000", +4790 => x"00000000", +4791 => x"00000000", +4792 => x"00000000", +4793 => x"00000000", +4794 => x"00000000", +4795 => x"00000000", +4796 => x"00000000", +4797 => x"00000000", +4798 => x"00000000", +4799 => x"00000000", +4800 => x"00000000", +4801 => x"00000000", +4802 => x"00000000", +4803 => x"00000000", +4804 => x"00000000", +4805 => x"00000000", +4806 => x"00000000", +4807 => x"00000000", +4808 => x"00000000", +4809 => x"00000000", +4810 => x"00000000", +4811 => x"00000000", +4812 => x"00000000", +4813 => x"00000000", +4814 => x"00000000", +4815 => x"00000000", +4816 => x"00000000", +4817 => x"00000000", +4818 => x"00000000", +4819 => x"00000000", +4820 => x"00000000", +4821 => x"00000000", +4822 => x"00000000", +4823 => x"00000000", +4824 => x"00000000", +4825 => x"00000000", +4826 => x"00000000", +4827 => x"00000000", +4828 => x"00000000", +4829 => x"00000000", +4830 => x"00000000", +4831 => x"00000000", +4832 => x"00000000", +4833 => x"00000000", +4834 => x"00000000", +4835 => x"00000000", +4836 => x"00000000", +4837 => x"00000000", +4838 => x"00000000", +4839 => x"00000000", +4840 => x"00000000", +4841 => x"00000000", +4842 => x"00000000", +4843 => x"00000000", +4844 => x"00000000", +4845 => x"00000000", +4846 => x"00000000", +4847 => x"00000000", +4848 => x"00000000", +4849 => x"00000000", +4850 => x"00000000", +4851 => x"00000000", +4852 => x"00000000", +4853 => x"00000000", +4854 => x"00000000", +4855 => x"00000000", +4856 => x"00000000", +4857 => x"00000000", +4858 => x"00000000", +4859 => x"00000000", +4860 => x"00000000", +4861 => x"00000000", +4862 => x"00000000", +4863 => x"00000000", +4864 => x"00000000", +4865 => x"00000000", +4866 => x"00000000", +4867 => x"00000000", +4868 => x"00000000", +4869 => x"00000000", +4870 => x"00000000", +4871 => x"00000000", +4872 => x"00000000", +4873 => x"00000000", +4874 => x"00000000", +4875 => x"00000000", +4876 => x"00000000", +4877 => x"00000000", +4878 => x"00000000", +4879 => x"00000000", +4880 => x"00000000", +4881 => x"00000000", +4882 => x"00000000", +4883 => x"00000000", +4884 => x"00000000", +4885 => x"00000000", +4886 => x"00000000", +4887 => x"00000000", +4888 => x"00000000", +4889 => x"00000000", +4890 => x"00000000", +4891 => x"00000000", +4892 => x"00000000", +4893 => x"00000000", +4894 => x"00000000", +4895 => x"00000000", +4896 => x"00000000", +4897 => x"00000000", +4898 => x"00000000", +4899 => x"00000000", +4900 => x"00000000", +4901 => x"00000000", +4902 => x"00000000", +4903 => x"00000000", +4904 => x"00000000", +4905 => x"00000000", +4906 => x"00000000", +4907 => x"00000000", +4908 => x"00000000", +4909 => x"00000000", +4910 => x"00000000", +4911 => x"00000000", +4912 => x"00000000", +4913 => x"00000000", +4914 => x"00000000", +4915 => x"00000000", +4916 => x"00000000", +4917 => x"00000000", +4918 => x"00000000", +4919 => x"00000000", +4920 => x"00000000", +4921 => x"00000000", +4922 => x"00000000", +4923 => x"00000000", +4924 => x"00000000", +4925 => x"00000000", +4926 => x"00000000", +4927 => x"00000000", +4928 => x"00000000", +4929 => x"00000000", +4930 => x"00000000", +4931 => x"00000000", +4932 => x"00000000", +4933 => x"00000000", +4934 => x"00000000", +4935 => x"00000000", +4936 => x"00000000", +4937 => x"00000000", +4938 => x"00000000", +4939 => x"00000000", +4940 => x"00000000", +4941 => x"000043fc", +4942 => x"ffffffff", +4943 => x"00000000", +4944 => x"ffffffff", +4945 => x"00000000", + others => x"00000000" +); + +attribute syn_ramstyle : string; +attribute syn_ramstyle of ram : signal is "no_rw_check" ; + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (memAWriteEnable = '1') then + ram(conv_integer(memAAddr)) <= memAWrite; + memARead <= memAWrite; + else + memARead <= ram(conv_integer(memAAddr)); + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (memBWriteEnable = '1') then + ram(conv_integer(memBAddr)) <= memBWrite; + memBRead <= memBWrite; + else + memBRead <= ram(conv_integer(memBAddr)); + end if; + end if; +end process; + + + + +end dualport_ram_arch; diff --git a/zpu/hdl/zpu3/src/helloworld_ram.vhd b/zpu/hdl/zpu3/src/helloworld_ram.vhd new file mode 100644 index 0000000..2e1d35d --- /dev/null +++ b/zpu/hdl/zpu3/src/helloworld_ram.vhd @@ -0,0 +1,3345 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +library zylin; +use zylin.zpu_config.all; +use zylin.zpupkg.all; + +entity dualport_ram is +port (clk : in std_logic; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit); + memAWrite : in std_logic_vector(wordSize-1 downto 0); + memARead : out std_logic_vector(wordSize-1 downto 0); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit); + memBWrite : in std_logic_vector(wordSize-1 downto 0); + memBRead : out std_logic_vector(wordSize-1 downto 0)); +end dualport_ram; + +architecture dualport_ram_arch of dualport_ram is + + +type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); + +shared variable ram : ram_type := +( +0 => x"800b0b0b", +1 => x"0b0b8070", +2 => x"0b0b80d6", +3 => x"f00c3a0b", +4 => x"0b80cd92", +5 => x"04000000", +6 => x"00000000", +7 => x"00000000", +8 => x"80088408", +9 => x"88080b0b", +10 => x"80cde02d", +11 => x"880c840c", +12 => x"800c0400", +13 => x"00000000", +14 => x"00000000", +15 => x"00000000", +16 => x"71fd0608", +17 => x"72830609", +18 => x"81058205", +19 => x"832b0b2a", +20 => x"83ffff06", +21 => x"52040000", +22 => x"00000000", +23 => x"00000000", +24 => x"71fd0608", +25 => x"83ffff73", +26 => x"83060981", +27 => x"05820583", +28 => x"2b0b2b09", +29 => x"067383ff", +30 => x"ff0b0b0b", +31 => x"0b83a504", +32 => x"72098105", +33 => x"72057373", +34 => x"09060906", +35 => x"73097306", +36 => x"070a8106", +37 => x"53510400", +38 => x"00000000", +39 => x"00000000", +40 => x"72722473", +41 => x"732e0753", +42 => x"51040000", +43 => x"00000000", +44 => x"00000000", +45 => x"00000000", +46 => x"00000000", +47 => x"00000000", +48 => x"71737109", +49 => x"71068106", +50 => x"30720a10", +51 => x"0a720a10", +52 => x"0a31050a", +53 => x"81065151", +54 => x"53510400", +55 => x"00000000", +56 => x"72722673", +57 => x"732e0753", +58 => x"51040000", +59 => x"00000000", +60 => x"00000000", +61 => x"00000000", +62 => x"00000000", +63 => x"00000000", +64 => x"00000000", +65 => x"00000000", +66 => x"00000000", +67 => x"00000000", +68 => x"00000000", +69 => x"00000000", +70 => x"00000000", +71 => x"00000000", +72 => x"72728072", +73 => x"8106ff05", +74 => x"09720605", +75 => x"71105272", +76 => x"0a100a53", +77 => x"72ed3851", +78 => x"51535104", +79 => x"00000000", +80 => x"720a722b", +81 => x"0a535104", +82 => x"00000000", +83 => x"00000000", +84 => x"00000000", +85 => x"00000000", +86 => x"00000000", +87 => x"00000000", +88 => x"72729f06", +89 => x"0981050b", +90 => x"0b0b88a7", +91 => x"05040000", +92 => x"00000000", +93 => x"00000000", +94 => x"00000000", +95 => x"00000000", +96 => x"72722aff", +97 => x"739f062a", +98 => x"0974090a", +99 => x"8106ff05", +100 => x"06075351", +101 => x"04000000", +102 => x"00000000", +103 => x"00000000", +104 => x"71715351", +105 => x"04067383", +106 => x"06098105", +107 => x"8205832b", +108 => x"0b2b0772", +109 => x"fc060c51", +110 => x"51040000", +111 => x"00000000", +112 => x"72098105", +113 => x"72050970", +114 => x"81050906", +115 => x"0a810653", +116 => x"51040000", +117 => x"00000000", +118 => x"00000000", +119 => x"00000000", +120 => x"72098105", +121 => x"72050970", +122 => x"81050906", +123 => x"0a098106", +124 => x"53510400", +125 => x"00000000", +126 => x"00000000", +127 => x"00000000", +128 => x"71098105", +129 => x"52040000", +130 => x"00000000", +131 => x"00000000", +132 => x"00000000", +133 => x"00000000", +134 => x"00000000", +135 => x"00000000", +136 => x"72720981", +137 => x"05055351", +138 => x"04098105", +139 => x"83051010", +140 => x"102b0772", +141 => x"fc060c51", +142 => x"51040000", +143 => x"00000000", +144 => x"72097206", +145 => x"73730906", +146 => x"07535104", +147 => x"00000000", +148 => x"00000000", +149 => x"00000000", +150 => x"00000000", +151 => x"00000000", +152 => x"71fc0608", +153 => x"72830609", +154 => x"81058305", +155 => x"1010102a", +156 => x"81ff0652", +157 => x"04000000", +158 => x"00000000", +159 => x"00000000", +160 => x"71fc0608", +161 => x"0b0b80d6", +162 => x"dc738306", +163 => x"10100508", +164 => x"067381ff", +165 => x"06738306", +166 => x"0b0b0b84", +167 => x"a9040000", +168 => x"80088408", +169 => x"88087575", +170 => x"0b0b0b8e", +171 => x"fd2d5050", +172 => x"80085688", +173 => x"0c840c80", +174 => x"0c510400", +175 => x"00000000", +176 => x"80088408", +177 => x"88087575", +178 => x"0b0b0b90", +179 => x"af2d5050", +180 => x"80085688", +181 => x"0c840c80", +182 => x"0c510400", +183 => x"00000000", +184 => x"72097081", +185 => x"0509060a", +186 => x"8106ff05", +187 => x"70547106", +188 => x"73097274", +189 => x"05ff0506", +190 => x"07535050", +191 => x"04000000", +192 => x"72097081", +193 => x"0509060a", +194 => x"098106ff", +195 => x"05705471", +196 => x"06730972", +197 => x"7405ff05", +198 => x"06075350", +199 => x"50040000", +200 => x"05ff0504", +201 => x"00000000", +202 => x"00000000", +203 => x"00000000", +204 => x"00000000", +205 => x"00000000", +206 => x"00000000", +207 => x"00000000", +208 => x"810b0b0b", +209 => x"80d6ec0c", +210 => x"51040000", +211 => x"00000000", +212 => x"00000000", +213 => x"00000000", +214 => x"00000000", +215 => x"00000000", +216 => x"71810552", +217 => x"04000000", +218 => x"00000000", +219 => x"00000000", +220 => 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x"00000000", +2872 => x"00000000", +2873 => x"00000000", +2874 => x"00000000", +2875 => x"00000000", +2876 => x"00000000", +2877 => x"00000000", +2878 => x"00000000", +2879 => x"00000000", +2880 => x"00000000", +2881 => x"00000000", +2882 => x"00000000", +2883 => x"00000000", +2884 => x"00000000", +2885 => x"00000000", +2886 => x"00000000", +2887 => x"00000000", +2888 => x"00000000", +2889 => x"00000000", +2890 => x"00000000", +2891 => x"00000000", +2892 => x"00000000", +2893 => x"00000000", +2894 => x"00000000", +2895 => x"00000000", +2896 => x"00000000", +2897 => x"00000000", +2898 => x"00000000", +2899 => x"00000000", +2900 => x"00000000", +2901 => x"00000000", +2902 => x"00000000", +2903 => x"00000000", +2904 => x"00000000", +2905 => x"00000000", +2906 => x"00000000", +2907 => x"00000000", +2908 => x"00000000", +2909 => x"00000000", +2910 => x"00000000", +2911 => x"00000000", +2912 => x"00000000", +2913 => x"00000000", +2914 => x"00000000", +2915 => x"00000000", +2916 => x"00000000", +2917 => x"00000000", +2918 => x"00000000", +2919 => x"00000000", +2920 => x"00000000", +2921 => x"00000000", +2922 => x"00000000", +2923 => x"00000000", +2924 => x"00000000", +2925 => x"00000000", +2926 => x"00000000", +2927 => x"00000000", +2928 => x"00000000", +2929 => x"00000000", +2930 => x"00000000", +2931 => x"00000000", +2932 => x"00000000", +2933 => x"00000000", +2934 => x"00000000", +2935 => x"00000000", +2936 => x"00000000", +2937 => x"00000000", +2938 => x"00000000", +2939 => x"00000000", +2940 => x"00000000", +2941 => x"00000000", +2942 => x"00000000", +2943 => x"00000000", +2944 => x"00000000", +2945 => x"00000000", +2946 => x"00000000", +2947 => x"00000000", +2948 => x"00000000", +2949 => x"00000000", +2950 => x"00000000", +2951 => x"00000000", +2952 => x"00000000", +2953 => x"00000000", +2954 => x"00000000", +2955 => x"00000000", +2956 => x"00000000", +2957 => x"00000000", +2958 => x"00000000", +2959 => x"00000000", +2960 => x"00000000", +2961 => x"00000000", +2962 => x"00000000", +2963 => x"00000000", +2964 => x"00000000", +2965 => x"00000000", +2966 => x"00000000", +2967 => x"00000000", +2968 => x"00000000", +2969 => x"00000000", +2970 => x"00000000", +2971 => x"00000000", +2972 => x"00000000", +2973 => x"00000000", +2974 => x"00000000", +2975 => x"00000000", +2976 => x"00000000", +2977 => x"00000000", +2978 => x"00000000", +2979 => x"00000000", +2980 => x"00000000", +2981 => x"00000000", +2982 => x"00000000", +2983 => x"00000000", +2984 => x"00000000", +2985 => x"00000000", +2986 => x"00000000", +2987 => x"00000000", +2988 => x"00000000", +2989 => x"00000000", +2990 => x"00000000", +2991 => x"00000000", +2992 => x"00000000", +2993 => x"00000000", +2994 => x"00000000", +2995 => x"00000000", +2996 => x"00000000", +2997 => x"00000000", +2998 => x"00000000", +2999 => x"00000000", +3000 => x"00000000", +3001 => x"00000000", +3002 => x"00000000", +3003 => x"00000000", +3004 => x"00000000", +3005 => x"00000000", +3006 => x"00000000", +3007 => x"00000000", +3008 => x"00000000", +3009 => x"00000000", +3010 => x"00000000", +3011 => x"00000000", +3012 => x"00000000", +3013 => x"00000000", +3014 => x"00000000", +3015 => x"00000000", +3016 => x"00000000", +3017 => x"00000000", +3018 => x"00000000", +3019 => x"ffffffff", +3020 => x"00000000", +3021 => x"00020000", +3022 => x"00000000", +3023 => x"00000000", +3024 => x"00002f38", +3025 => x"00002f38", +3026 => x"00002f40", +3027 => x"00002f40", +3028 => x"00002f48", +3029 => x"00002f48", +3030 => x"00002f50", +3031 => x"00002f50", +3032 => x"00002f58", +3033 => x"00002f58", +3034 => x"00002f60", +3035 => x"00002f60", +3036 => x"00002f68", +3037 => x"00002f68", +3038 => x"00002f70", +3039 => x"00002f70", +3040 => x"00002f78", +3041 => x"00002f78", +3042 => x"00002f80", +3043 => x"00002f80", +3044 => x"00002f88", +3045 => x"00002f88", +3046 => x"00002f90", +3047 => x"00002f90", +3048 => x"00002f98", +3049 => x"00002f98", +3050 => x"00002fa0", +3051 => x"00002fa0", +3052 => x"00002fa8", +3053 => x"00002fa8", +3054 => x"00002fb0", +3055 => x"00002fb0", +3056 => x"00002fb8", +3057 => x"00002fb8", +3058 => x"00002fc0", +3059 => x"00002fc0", +3060 => x"00002fc8", +3061 => x"00002fc8", +3062 => x"00002fd0", +3063 => x"00002fd0", +3064 => x"00002fd8", +3065 => x"00002fd8", +3066 => x"00002fe0", +3067 => x"00002fe0", +3068 => x"00002fe8", +3069 => x"00002fe8", +3070 => x"00002ff0", +3071 => x"00002ff0", +3072 => x"00002ff8", +3073 => x"00002ff8", +3074 => x"00003000", +3075 => x"00003000", +3076 => x"00003008", +3077 => x"00003008", +3078 => x"00003010", +3079 => x"00003010", +3080 => x"00003018", +3081 => x"00003018", +3082 => x"00003020", +3083 => x"00003020", +3084 => x"00003028", +3085 => x"00003028", +3086 => x"00003030", +3087 => x"00003030", +3088 => x"00003038", +3089 => x"00003038", +3090 => x"00003040", +3091 => x"00003040", +3092 => x"00003048", +3093 => x"00003048", +3094 => x"00003050", +3095 => x"00003050", +3096 => x"00003058", +3097 => x"00003058", +3098 => x"00003060", +3099 => x"00003060", +3100 => x"00003068", +3101 => x"00003068", +3102 => x"00003070", +3103 => x"00003070", +3104 => x"00003078", +3105 => x"00003078", +3106 => x"00003080", +3107 => x"00003080", +3108 => x"00003088", +3109 => x"00003088", +3110 => x"00003090", +3111 => x"00003090", +3112 => x"00003098", +3113 => x"00003098", +3114 => x"000030a0", +3115 => x"000030a0", +3116 => x"000030a8", +3117 => x"000030a8", +3118 => x"000030b0", +3119 => x"000030b0", +3120 => x"000030b8", +3121 => x"000030b8", +3122 => x"000030c0", +3123 => x"000030c0", +3124 => x"000030c8", +3125 => x"000030c8", +3126 => x"000030d0", +3127 => x"000030d0", +3128 => x"000030d8", +3129 => x"000030d8", +3130 => x"000030e0", +3131 => x"000030e0", +3132 => x"000030e8", +3133 => x"000030e8", +3134 => x"000030f0", +3135 => x"000030f0", +3136 => x"000030f8", +3137 => x"000030f8", +3138 => x"00003100", +3139 => x"00003100", +3140 => x"00003108", +3141 => x"00003108", +3142 => x"00003110", +3143 => x"00003110", +3144 => x"00003118", +3145 => x"00003118", +3146 => x"00003120", +3147 => x"00003120", +3148 => x"00003128", +3149 => x"00003128", +3150 => x"00003130", +3151 => x"00003130", +3152 => x"00003138", +3153 => x"00003138", +3154 => x"00003140", +3155 => x"00003140", +3156 => x"00003148", +3157 => x"00003148", +3158 => x"00003150", +3159 => x"00003150", +3160 => x"00003158", +3161 => x"00003158", +3162 => x"00003160", +3163 => x"00003160", +3164 => x"00003168", +3165 => x"00003168", +3166 => x"00003170", +3167 => x"00003170", +3168 => x"00003178", +3169 => x"00003178", +3170 => x"00003180", +3171 => x"00003180", +3172 => x"00003188", +3173 => x"00003188", +3174 => x"00003190", +3175 => x"00003190", +3176 => x"00003198", +3177 => x"00003198", +3178 => x"000031a0", +3179 => x"000031a0", +3180 => x"000031a8", +3181 => x"000031a8", +3182 => x"000031b0", +3183 => x"000031b0", +3184 => x"000031b8", +3185 => x"000031b8", +3186 => x"000031c0", +3187 => x"000031c0", +3188 => x"000031c8", +3189 => x"000031c8", +3190 => x"000031d0", +3191 => x"000031d0", +3192 => x"000031d8", +3193 => x"000031d8", +3194 => x"000031e0", +3195 => x"000031e0", +3196 => x"000031e8", +3197 => x"000031e8", +3198 => x"000031f0", +3199 => x"000031f0", +3200 => x"000031f8", +3201 => x"000031f8", +3202 => x"00003200", +3203 => x"00003200", +3204 => x"00003208", +3205 => x"00003208", +3206 => x"00003210", +3207 => x"00003210", +3208 => x"00003218", +3209 => x"00003218", +3210 => x"00003220", +3211 => x"00003220", +3212 => x"00003228", +3213 => x"00003228", +3214 => x"00003230", +3215 => x"00003230", +3216 => x"00003238", +3217 => x"00003238", +3218 => x"00003240", +3219 => x"00003240", +3220 => x"00003248", +3221 => x"00003248", +3222 => x"00003250", +3223 => x"00003250", +3224 => x"00003258", +3225 => x"00003258", +3226 => x"00003260", +3227 => x"00003260", +3228 => x"00003268", +3229 => x"00003268", +3230 => x"00003270", +3231 => x"00003270", +3232 => x"00003278", +3233 => x"00003278", +3234 => x"00003280", +3235 => x"00003280", +3236 => x"00003288", +3237 => x"00003288", +3238 => x"00003290", +3239 => x"00003290", +3240 => x"00003298", +3241 => x"00003298", +3242 => x"000032a0", +3243 => x"000032a0", +3244 => x"000032a8", +3245 => x"000032a8", +3246 => x"000032b0", +3247 => x"000032b0", +3248 => x"000032b8", +3249 => x"000032b8", +3250 => x"000032c0", +3251 => x"000032c0", +3252 => x"000032c8", +3253 => x"000032c8", +3254 => x"000032d0", +3255 => x"000032d0", +3256 => x"000032d8", +3257 => x"000032d8", +3258 => x"000032e0", +3259 => x"000032e0", +3260 => x"000032e8", +3261 => x"000032e8", +3262 => x"000032f0", +3263 => x"000032f0", +3264 => x"000032f8", +3265 => x"000032f8", +3266 => x"00003300", +3267 => x"00003300", +3268 => x"00003308", +3269 => x"00003308", +3270 => x"00003310", +3271 => x"00003310", +3272 => x"00003318", +3273 => x"00003318", +3274 => x"00003320", +3275 => x"00003320", +3276 => x"00003328", +3277 => x"00003328", +3278 => x"00003330", +3279 => x"00003330", +3280 => x"00002b50", +3281 => x"ffffffff", +3282 => x"00000000", +3283 => x"ffffffff", +3284 => x"00000000", + others => x"00000000" +); + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (memAWriteEnable = '1') then + ram(conv_integer(memAAddr)) := memAWrite; + memARead <= memAWrite; + else + memARead <= ram(conv_integer(memAAddr)); + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (memBWriteEnable = '1') then + ram(conv_integer(memBAddr)) := memBWrite; + memBRead <= memBWrite; + else + memBRead <= ram(conv_integer(memBAddr)); + end if; + end if; +end process; + + + + +end dualport_ram_arch; diff --git a/zpu/hdl/zpu3/src/ic300.bitgen b/zpu/hdl/zpu3/src/ic300.bitgen new file mode 100644 index 0000000..1095099 --- /dev/null +++ b/zpu/hdl/zpu3/src/ic300.bitgen @@ -0,0 +1,27 @@ +-g DebugBitstream:No +-g Binary:yes +-g CRC:Enable +-g ConfigRate:50 +-g CclkPin:Pullnone +-g M0Pin:Pullnone +-g M1Pin:Pullnone +-g M2Pin:Pullnone +-g ProgPin:PullUp +-g DonePin:Pullnone +-g TckPin:Pullnone +-g TdiPin:Pullnone +-g TdoPin:Pullnone +-g TmsPin:Pullnone +-g UnusedPin:Pullnone +-g UserID:0xFFFFFFFF +-g DCMShutDown:Disable +-g DCIUpdateMode:AsRequired +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:Level1 +-g DonePipe:No +-g DriveDone:Yes + diff --git a/zpu/hdl/zpu3/src/ic300.lso b/zpu/hdl/zpu3/src/ic300.lso new file mode 100644 index 0000000..22de730 --- /dev/null +++ b/zpu/hdl/zpu3/src/ic300.lso @@ -0,0 +1 @@ +work diff --git a/zpu/hdl/zpu3/src/ic300.ucf b/zpu/hdl/zpu3/src/ic300.ucf new file mode 100644 index 0000000..e11357f --- /dev/null +++ b/zpu/hdl/zpu3/src/ic300.ucf @@ -0,0 +1,146 @@ +# clock inputs +net "cpu_clk_p" loc = "R9" | iostandard=LVTTL; + +# input pins +net "cpu_a_p(0)" loc = "N15" | iostandard=LVTTL; +net "cpu_a_p(1)" loc = "P16" | iostandard=LVTTL; +net "cpu_a_p(2)" loc = "P13" | iostandard=LVTTL; +net "cpu_a_p(3)" loc = "N16" | iostandard=LVTTL; +net "cpu_a_p(4)" loc = "P15" | iostandard=LVTTL; +net "cpu_a_p(5)" loc = "R11" | iostandard=LVTTL; +net "cpu_a_p(6)" loc = "T14" | iostandard=LVTTL; +net "cpu_a_p(7)" loc = "R16" | iostandard=LVTTL; +net "cpu_a_p(8)" loc = "P14" | iostandard=LVTTL; +net "cpu_a_p(9)" loc = "T13" | iostandard=LVTTL; +net "cpu_a_p(10)" loc = "R13" | iostandard=LVTTL; +net "cpu_a_p(11)" loc = "P7" | iostandard=LVTTL; +net "cpu_a_p(12)" loc = "N12" | iostandard=LVTTL; +net "cpu_a_p(13)" loc = "R12" | iostandard=LVTTL; +net "cpu_a_p(14)" loc = "L13" | iostandard=LVTTL; +net "cpu_a_p(15)" loc = "K12" | iostandard=LVTTL; +net "cpu_a_p(16)" loc = "K15" | iostandard=LVTTL; +net "cpu_a_p(17)" loc = "T10" | iostandard=LVTTL; +net "cpu_a_p(18)" loc = "T9" | iostandard=LVTTL; +net "cpu_a_p(19)" loc = "N10" | iostandard=LVTTL; +net "cpu_a_p(20)" loc = "T8" | iostandard=LVTTL; +net "cpu_wr_n_p(0)" loc = "L15" | iostandard=LVTTL; +net "cpu_wr_n_p(1)" loc = "N14" | iostandard=LVTTL; +net "cpu_oe_n_p" loc = "T12" | iostandard=LVTTL; +net "cpu_cs_n_p(1)" loc = "R3" | iostandard=LVTTL; +net "cpu_cs_n_p(2)" loc = "M16" | iostandard=LVTTL; +net "cpu_cs_n_p(3)" loc = "P11" | iostandard=LVTTL; + +#net "sdr_clk_fb_p" loc = "B8" | iostandard=SSTL2_I; + +# output pins +net "cpu_fiq_p" loc = "K16" | iostandard=LVTTL; +net "cpu_irq_p(0)" loc = "M14" | iostandard=LVTTL; +net "cpu_irq_p(1)" loc = "J16" | iostandard=LVTTL; +net "cpu_wait_n_p" loc = "M15" | iostandard=LVTTL; + +#net "sdr_clk_p" loc = "D8" | iostandard=SSTL2_I | FAST; +#net "sdr_clk_n_p" loc = "F5" | iostandard=SSTL2_I | FAST; +#net "cke_q_p" loc = "F4" | iostandard=SSTL2_I | FAST; +#net "cs_qn_p" loc = "M2" | iostandard=SSTL2_I | FAST | PULLUP; +#net "ras_qn_p" loc = "J2" | iostandard=SSTL2_I | FAST | PULLUP | NODELAY; +#net "cas_qn_p" loc = "M3" | iostandard=SSTL2_I | FAST | PULLUP | NODELAY; +#net "we_qn_p" loc = "K4" | iostandard=SSTL2_I | FAST | PULLUP | NODELAY; +#net "dm_q_p(0)" loc = "L4" | iostandard=SSTL2_I | FAST; +#net "dm_q_p(1)" loc = "E4" | iostandard=SSTL2_I | FAST; +#net "dqs_q_p(0)" loc = "L3" | iostandard=SSTL2_I | FAST; +#net "dqs_q_p(1)" loc = "D3" | iostandard=SSTL2_I | FAST; +#net "ba_q_p(0)" loc = "M1" | iostandard=SSTL2_I | FAST; +#net "ba_q_p(1)" loc = "J3" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(0)" loc = "J4" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(1)" loc = "N2" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(2)" loc = "H4" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(3)" loc = "P2" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(4)" loc = "E7" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(5)" loc = "G4" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(6)" loc = "D7" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(7)" loc = "G5" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(8)" loc = "C7" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(9)" loc = "F3" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(10)" loc = "N3" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(11)" loc = "E6" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(12)" loc = "D6" | iostandard=SSTL2_I | FAST; + +# bidirectional pins +net "cpu_d_p(0)" loc = "M11" | iostandard=LVTTL; +net "cpu_d_p(1)" loc = "N11" | iostandard=LVTTL; +net "cpu_d_p(2)" loc = "P10" | iostandard=LVTTL; +net "cpu_d_p(3)" loc = "R10" | iostandard=LVTTL; +net "cpu_d_p(4)" loc = "T7" | iostandard=LVTTL; +net "cpu_d_p(5)" loc = "R7" | iostandard=LVTTL; +net "cpu_d_p(6)" loc = "N6" | iostandard=LVTTL; +net "cpu_d_p(7)" loc = "M6" | iostandard=LVTTL; +net "cpu_d_p(8)" loc = "K13" | iostandard=LVTTL; +net "cpu_d_p(9)" loc = "M10" | iostandard=LVTTL; +net "cpu_d_p(10)" loc = "L12" | iostandard=LVTTL; +net "cpu_d_p(11)" loc = "M13" | iostandard=LVTTL; +net "cpu_d_p(12)" loc = "K14" | iostandard=LVTTL; +net "cpu_d_p(13)" loc = "L14" | iostandard=LVTTL; +net "cpu_d_p(14)" loc = "J13" | iostandard=LVTTL; +net "cpu_d_p(15)" loc = "J14" | iostandard=LVTTL; + +#net "sdr_d_p(0)" loc = "G1" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(1)" loc = "H3" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(2)" loc = "G3" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(3)" loc = "K2" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(4)" loc = "F2" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(5)" loc = "L2" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(6)" loc = "E1" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(7)" loc = "M4" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(8)" loc = "C6" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(9)" loc = "E2" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(10)" loc = "C2" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(11)" loc = "D1" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(12)" loc = "B7" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(13)" loc = "D2" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(14)" loc = "B6" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(15)" loc = "B5" | iostandard=SSTL2_I | NODELAY | FAST; + +# TIMING +# Create timing names +NET "cpu_clk_p" TNM_NET = "cpu_clk_p"; +NET "sdr_clk_fb_p" TNM_NET = "sdr_clk_fb_p"; +#NET "cpu_clk" TNM_NET = "cpu_clk"; +#NET "cpu_clk_2x" TNM_NET = "cpu_clk_2x"; +#NET "cpu_clk_4x" TNM_NET = "cpu_clk_4x"; +#NET "ddr_in_clk" TNM_NET = "ddr_in_clk"; +#NET "ddr_in_clk_2x" TNM_NET = "ddr_in_clk_2x"; + +## Create timing + +# Periode timing +TIMESPEC "TS_cpu_clk" = PERIOD "cpu_clk_p" 15.6 ns HIGH 50 %; +#TIMESPEC "TS_sdr_clk_fb_p" = PERIOD "sdr_clk_fb_p" 7.8 ns HIGH 50 %; + +# Clock domain crossing timing +#TIMESPEC "TS_cpu1_to_cpu2" = FROM "cpu_clk" TO "cpu_clk_2x" 7.8 ns; +#TIMESPEC "TS_cpu1_to_cpu4" = FROM "cpu_clk" TO "cpu_clk_4x" 3.9 ns; +#TIMESPEC "TS_cpu1_to_ddr2" = FROM "cpu_clk" TO "ddr_in_clk" 7.8 ns; +#TIMESPEC "TS_cpu1_to_ddr2_2x" = FROM "cpu_clk" TO "ddr_in_clk_2x" 3.9 ns; + +#TIMESPEC "TS_cpu2_to_cpu1" = FROM "cpu_clk_2x" TO "cpu_clk" 7.8 ns; +#TIMESPEC "TS_cpu2_to_cpu4" = FROM "cpu_clk_2x" TO "cpu_clk_4x" 3.9 ns; +#TIMESPEC "TS_cpu2_to_ddr2" = FROM "cpu_clk_2x" TO "ddr_in_clk" 7.8 ns; +#TIMESPEC "TS_cpu2_to_ddr_2x" = FROM "cpu_clk_2x" TO "ddr_in_clk_2x" 3.9 ns; + +#TIMESPEC "TS_cpu4_to_cpu1" = FROM "cpu_clk_4x" TO "cpu_clk" 3.9 ns; +#TIMESPEC "TS_cpu4_to_cpu2" = FROM "cpu_clk_4x" TO "cpu_clk_2x" 3.9 ns; +#TIMESPEC "TS_cpu4_to_ddr2" = FROM "cpu_clk_4x" TO "ddr_in_clk" 3.9 ns; +#TIMESPEC "TS_cpu4_to_ddr2_2x" = FROM "cpu_clk_4x" TO "ddr_in_clk_2x" 3.9 ns; + +#TIMESPEC "TS_ddr2_to_cpu1" = FROM "ddr_in_clk" TO "cpu_clk" 7.8 ns; +#TIMESPEC "TS_ddr2_to_cpu2" = FROM "ddr_in_clk" TO "cpu_clk_2x" 7.8 ns; +#TIMESPEC "TS_ddr2_to_cpu4" = FROM "ddr_in_clk" TO "cpu_clk_4x" 3.9 ns; +#TIMESPEC "TS_ddr2_to_ddr2_2x" = FROM "ddr_in_clk" TO "ddr_in_clk_2x" 3.9 ns; + +#TIMESPEC "TS_ddr2_2x_to_cpu1" = FROM "ddr_in_clk_2x" TO "cpu_clk" 3.9 ns; +#TIMESPEC "TS_ddr2_2x_to_cpu2" = FROM "ddr_in_clk_2x" TO "cpu_clk_2x" 3.9 ns; +#TIMESPEC "TS_ddr2_2x_to_cpu4" = FROM "ddr_in_clk_2x" TO "cpu_clk_4x" 3.9 ns; +#TIMESPEC "TS_ddr2_2x_to_ddr2" = FROM "ddr_in_clk_2x" TO "ddr_in_clk" 3.9 ns; + + + diff --git a/zpu/hdl/zpu3/src/ic300.vhd b/zpu/hdl/zpu3/src/ic300.vhd new file mode 100644 index 0000000..a1b4f41 --- /dev/null +++ b/zpu/hdl/zpu3/src/ic300.vhd @@ -0,0 +1,144 @@ +-------------------------------------------------------------------------------- +-- Company: Zylin AS +-- Engineer: Tore Ramsland +-- +-- Create Date: 21:47:41 07/03/05 +-- Design Name: ic300 +-- Module Name: ic300 - behave +-- Project Name: eCosBoard +-- Target Device: XC3S400400-FG256 +-- Tool versions: 7.1i +-- Description: Top level +-- +-- Dependencies: +-- +-- Revision: +-- 2005-07-11 Updated to test FPGA +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library UNISIM; +use UNISIM.VComponents.all; + +library zylin; +use zylin.arm7.all; + +library zylin; +use zylin.zpu_config.all; +use zylin.zpupkg.all; + +library work; +use work.phi_config.all; +use work.ic300pkg.all; + +entity ic300 is + generic( + simulate_io_time : boolean := false); + port ( -- Clock inputs + cpu_clk_p : in std_logic; + + -- CPU interface signals + cpu_a_p : in std_logic_vector(20 downto 0); + cpu_wr_n_p : in std_logic_vector(1 downto 0); + cpu_cs_n_p : in std_logic_vector(3 downto 1); + cpu_oe_n_p : in std_logic; + cpu_d_p : inout std_logic_vector(15 downto 0); + cpu_irq_p : out std_logic_vector(1 downto 0); + cpu_fiq_p : out std_logic; + cpu_wait_n_p : out std_logic; + + -- DDR SDRAM Signals + sdr_clk_p : out std_logic; -- ddr_sdram_clock + sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock + cke_q_p : out std_logic; -- clock enable + cs_qn_p : out std_logic; -- /chip select + ras_qn_p : inout std_logic; -- /ras + cas_qn_p : inout std_logic; -- /cas + we_qn_p : inout std_logic; -- /write enable + dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00" + dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write + ba_q_p : out std_logic_vector(1 downto 0); -- bank select + sdr_a_p : out std_logic_vector(12 downto 0); -- address bus + sdr_d_p : inout std_logic_vector(15 downto 0); -- bidir data bus + sdr_clk_fb_p : in std_logic -- DDR clock feedback + ); +end ic300; + +architecture behave of ic300 is + +signal cpu_we : std_logic_vector(1 downto 0); -- Write signal for lower(0) and upper(1) 8 data bits +signal cpu_re : std_logic; -- Read enable signal for all 16 bits +signal areset : std_logic; -- Asyncronous active high reset (for initialization) +signal areset_dummy : std_logic; + +-- Clock module signals +signal clk_status : std_logic_vector(2 downto 0); -- DLL lock status (from 3 DLL's) +signal cpu_clk : std_logic; -- 64 MHz CPU clk +signal cpu_clk_2x : std_logic; -- 128 MHz CPU clk (in phase with 64 MHz) +signal cpu_clk_4x : std_logic; -- 256 MHz CPU clk (in phase with 64 MHz) +signal ddr_in_clk : std_logic; -- 128 MHz clock from DDR SDRAM +signal ddr_in_clk_2x : std_logic; -- 256 MHz clock from DDR SDRAM + -- NOTE! Phase relation to 64 MHz clock unknown + +-- Internal CPU interface signals +signal cpu_din : std_logic_vector(15 downto 0); -- 16-bit data from CPU +signal cpu_dout : std_logic_vector(15 downto 0); -- 16-bit data to CPU +signal cpu_a : std_logic_vector(20 downto 0); -- 21-bit address from CPU + +begin + +-- areset <= '0'; + areset_dummy <= '0'; + + global_init_reset: + rocbuf port map(I=>areset_dummy,O=>areset); + + allclocks: + clocks port map( + areset => areset, + cpu_clk_p => cpu_clk_p, + cpu_clk => cpu_clk, + cpu_clk_2x => cpu_clk_2x, + cpu_clk_4x => cpu_clk_4x, + sdr_clk_fb_p => sdr_clk_fb_p, + ddr_in_clk => ddr_in_clk, + ddr_in_clk_2x => ddr_in_clk_2x, + locked => clk_status); + + arm7cpu: + arm7wb generic map (simulate_io_time => simulate_io_time) + port map( + areset => areset, + cpu_clk => cpu_clk, + cpu_clk_2x => cpu_clk_2x, + cpu_a_p => cpu_a_p, + cpu_wr_n_p => cpu_wr_n_p, + cpu_cs_n_p => cpu_cs_n_p, + cpu_oe_n_p => cpu_oe_n_p, + cpu_d_p => cpu_d_p, + cpu_irq_p => cpu_irq_p, + cpu_fiq_p => cpu_fiq_p, + cpu_wait_n_p => cpu_wait_n_p, + cpu_din => cpu_din, + cpu_a => cpu_a, + cpu_we => cpu_we, + cpu_re => cpu_re, + cpu_dout => cpu_dout); + + + cpu_fpga_regs: + zpuio port map( + areset => areset, + cpu_clk => cpu_clk, + clk_status => clk_status, + cpu_din => cpu_din, + cpu_a => cpu_a, + cpu_we => cpu_we, + cpu_re => cpu_re, + cpu_dout => cpu_dout); + + +end behave; diff --git a/zpu/hdl/zpu3/src/ic300_config.vhd b/zpu/hdl/zpu3/src/ic300_config.vhd new file mode 100644 index 0000000..9d3f939 --- /dev/null +++ b/zpu/hdl/zpu3/src/ic300_config.vhd @@ -0,0 +1,20 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +package phi_config is + + constant Fpga_Global_Base : std_logic_vector(19 downto 17) := "000"; -- 0x0280.... + constant Clock_Stat_Reg_Addr : std_logic_vector(3 downto 1) := "000"; -- 0x....0000 + constant Testreg32_Lower_Addr : std_logic_vector(3 downto 1) := "110"; -- 0x....000C + constant Testreg32_Upper_Addr : std_logic_vector(3 downto 1) := "111"; -- 0x....000E + + constant Fpga_DDR_Ctrl_Base : std_logic_vector(19 downto 17) := "111"; -- 0x028E.... + constant DDR_Ctrl_Reg_Addr : std_logic_vector(3 downto 1) := "000"; -- 0x....0000 + constant DDR_Mode_Reg_Addr : std_logic_vector(3 downto 1) := "001"; -- 0x....0002 + + -- These are temporary test registers only! + constant DDR_Data_Reg_Addr : std_logic_vector(3 downto 1) := "100"; -- 0x....0008 + constant DDR_Addr_Reg_Addr : std_logic_vector(3 downto 1) := "101"; -- 0x....000A + constant DDR_Req_Reg_Addr : std_logic_vector(3 downto 1) := "110"; -- 0x....000C + +end phi_config; diff --git a/zpu/hdl/zpu3/src/ic300pkg.vhd b/zpu/hdl/zpu3/src/ic300pkg.vhd new file mode 100644 index 0000000..13da306 --- /dev/null +++ b/zpu/hdl/zpu3/src/ic300pkg.vhd @@ -0,0 +1,88 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +package ic300pkg is + + component ic300 is + port ( -- Clock inputs + cpu_clk_p : in std_logic; + + -- CPU interface signals + cpu_a_p : in std_logic_vector(20 downto 0); + cpu_wr_n_p : in std_logic_vector(1 downto 0); + cpu_cs_n_p : in std_logic_vector(3 downto 1); + cpu_oe_n_p : in std_logic; + cpu_d_p : inout std_logic_vector(15 downto 0); + cpu_irq_p : out std_logic_vector(1 downto 0); + cpu_fiq_p : out std_logic; + cpu_wait_n_p : out std_logic; + + -- DDR SDRAM Signals + sdr_clk_p : out std_logic; -- ddr_sdram_clock + sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock + cke_q_p : out std_logic; -- clock enable + cs_qn_p : out std_logic; -- /chip select + ras_qn_p : inout std_logic; -- /ras + cas_qn_p : inout std_logic; -- /cas + we_qn_p : inout std_logic; -- /write enable + dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00" + dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write + ba_q_p : out std_logic_vector(1 downto 0); -- bank select + sdr_a_p : out std_logic_vector(12 downto 0); -- address bus + sdr_d_p : inout std_logic_vector(15 downto 0); -- bidir data bus + sdr_clk_fb_p : in std_logic -- DDR clock feedback + ); + end component; + + component clocks is + port ( areset : in std_logic; + cpu_clk_p : in std_logic; + sdr_clk_fb_p : in std_logic; + cpu_clk : out std_logic; + cpu_clk_2x : out std_logic; + cpu_clk_4x : out std_logic; + ddr_in_clk : out std_logic; + ddr_in_clk_2x : out std_logic; + locked : out std_logic_vector(2 downto 0)); + end component; + + component cpu_regs is + port ( areset : in std_logic; + cpu_clk : in std_logic; + clk_status : in std_logic_vector(2 downto 0); + cpu_din : in std_logic_vector(15 downto 0); + cpu_a : in std_logic_vector(20 downto 0); + cpu_we : in std_logic_vector(1 downto 0); + cpu_re : in std_logic; + cpu_dout : inout std_logic_vector(15 downto 0)); + end component; + + component ddr_bridge is + port ( areset : in std_logic; + cpu_clk : in std_logic; + cpu_clk_2x : in std_logic; + cpu_clk_4x : in std_logic; + ddr_in_clk : in std_logic; + ddr_in_clk_2x : in std_logic; + + cpu_we : in std_logic_vector(1 downto 0); + cpu_re : in std_logic; + cpu_din : in std_logic_vector(15 downto 0); + cpu_a : in std_logic_vector(20 downto 0); + cpu_dout : inout std_logic_vector(15 downto 0); + + sdr_clk_p : out std_logic; -- ddr_sdram_clock + sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock + cke_q_p : out std_logic; -- clock enable + cs_qn_p : out std_logic; -- /chip select + ras_qn_p : inout std_logic; -- /ras + cas_qn_p : inout std_logic; -- /cas + we_qn_p : inout std_logic; -- /write enable + dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00" + dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write + ba_q_p : out std_logic_vector(1 downto 0); -- bank select + sdr_a_p : out std_logic_vector(12 downto 0); -- address bus + sdr_d_p : inout std_logic_vector(15 downto 0)); -- bidir data bus + end component; + +end ic300pkg; diff --git a/zpu/hdl/zpu3/src/io.vhd b/zpu/hdl/zpu3/src/io.vhd new file mode 100644 index 0000000..6b50ca1 --- /dev/null +++ b/zpu/hdl/zpu3/src/io.vhd @@ -0,0 +1,95 @@ +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +use std.textio.all; + +library zylin; +use zylin.zpu_config.all; +use zylin.zpupkg.all; +use zylin.txt_util.all; + +entity zpu_io is + generic ( + log_file: string := "log.txt" + ); + port( + clk : in std_logic; + areset : in std_logic; + busy : out std_logic; + writeEnable : in std_logic; + readEnable : in std_logic; + write : in std_logic_vector(7 downto 0); + read : out std_logic_vector(7 downto 0); + addr : in std_logic_vector(maxAddrBit downto minAddrBit) + ); +end zpu_io; + + +architecture behave of zpu_io is + + + +signal timer_read : std_logic_vector(7 downto 0); +--signal timer_write : std_logic_vector(7 downto 0); +signal timer_we : std_logic; + +file l_file : TEXT open write_mode is log_file; + +begin + + + timerinst: timer port map ( + clk => clk, + areset => areset, + we => timer_we, + din => write, + adr => addr(4 downto 2), + dout => timer_read); + + + process(areset, clk) + begin + if (areset = '1') then + timer_we <= '0'; + busy <= '1'; + elsif (clk'event and clk = '1') then + busy <= '1'; + timer_we <= '0'; + if writeEnable = '1' then + -- external interface + if addr=x"1000" then + -- Write to UART + -- report "" & character'image(conv_integer(memBint)) severity note; + print(l_file, character'val(conv_integer(write))); + busy <= '0'; + elsif addr(12)='1' then + timer_we <= '1'; + busy <= '0'; + else + report "Illegal IO write" severity failure; + end if; + + end if; + if (readEnable = '1') then + if addr=x"1001" then + read <= (0=>'1', others => '0'); -- recieve empty + busy <= '0'; + elsif addr(12)='1' then + read <= timer_read; + busy <= '0'; + elsif addr(11)='1' then + read <= ZPU_Frequency; + busy <= '0'; + else + report "Illegal IO read" severity failure; + end if; + else + read <= (others => '1'); + end if; + end if; + end process; + + +end behave; + diff --git a/zpu/hdl/zpu3/src/log.txt b/zpu/hdl/zpu3/src/log.txt new file mode 100644 index 0000000..5557b06 --- /dev/null +++ b/zpu/hdl/zpu3/src/log.txt @@ -0,0 +1,156 @@ + + + +D +h +r +y +s +t +o +n +e + +B +e +n +c +h +m +a +r +k +, + +V +e +r +s +i +o +n + +2 +. +1 + +( +L +a +n +g +u +a +g +e +: + +C +) + + + + + + +P +r +o +g +r +a +m + +c +o +m +p +i +l +e +d + +w +i +t +h +o +u +t + +' +r +e +g +i +s +t +e +r +' + +a +t +t +r +i +b +u +t +e + + + + + + +E +x +e +c +u +t +i +o +n + +s +t +a +r +t +s +, + +2 +0 +0 +0 +0 +0 + +r +u +n +s + +t +h +r +o +u +g +h + +D +h +r +y +s +t +o +n +e + + + diff --git a/zpu/hdl/zpu3/src/niltrace.vhd b/zpu/hdl/zpu3/src/niltrace.vhd new file mode 100644 index 0000000..40fc1ca --- /dev/null +++ b/zpu/hdl/zpu3/src/niltrace.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +use std.textio.all; +use work.zpu_config.all; + + +entity trace is + port( + clk : in std_logic; + begin_inst : in std_logic; + pc : in std_logic_vector(maxAddrBit downto 0); + opcode : in std_logic_vector(7 downto 0); + sp : in std_logic_vector(maxAddrBit downto 2); + memA : in std_logic_vector(wordSize-1 downto 0); + busy : in std_logic); +end trace; + + +architecture behave of trace is + +begin + +end behave; + diff --git a/zpu/hdl/zpu3/src/sim_fpga_top.vhd b/zpu/hdl/zpu3/src/sim_fpga_top.vhd new file mode 100644 index 0000000..3044606 --- /dev/null +++ b/zpu/hdl/zpu3/src/sim_fpga_top.vhd @@ -0,0 +1,127 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 20:15:31 04/14/05 +-- Design Name: +-- Module Name: fpga_top - behave +-- Project Name: +-- Target Device: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +library zylin; +use zylin.zpu_config.all; +use zylin.zpupkg.all; + +entity fpga_top is +end fpga_top; + +architecture behave of fpga_top is + + +signal clk : std_logic; + +signal areset : std_logic; + + +component zpu_top is + Port ( clk : in std_logic; + areset : in std_logic; + io_busy : in std_logic; + io_read : in std_logic_vector(7 downto 0); + io_write : out std_logic_vector(7 downto 0); + io_addr : out std_logic_vector(maxAddrBit downto minAddrBit); + io_writeEnable : out std_logic; + io_readEnable : out std_logic; + interrupt : in std_logic; + break : out std_logic); +end component; + + +component zpu_io is + generic ( + log_file: string := "log.txt" + ); + port( + clk : in std_logic; + areset : in std_logic; + busy : out std_logic; + writeEnable : in std_logic; + readEnable : in std_logic; + write : in std_logic_vector(7 downto 0); + read : out std_logic_vector(7 downto 0); + addr : in std_logic_vector(maxAddrBit downto minAddrBit) + ); +end component; + + + +signal io_busy : std_logic; +signal io_read : std_logic_vector(7 downto 0); +signal io_write : std_logic_vector(7 downto 0); +signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit); +signal io_writeEnable : std_logic; +signal io_readEnable : std_logic; + +signal break : std_logic; + +begin + poweronreset: roc port map (O => areset); + + + + zpu: zpu_top port map ( + clk => clk , + areset => areset, + io_busy => io_busy, + io_read => io_read, + io_write => io_write, + io_addr => io_addr, + io_writeEnable => io_writeEnable, + io_readEnable => io_readEnable, + interrupt => '0', + break => break); + + + ioMap: zpu_io port map ( + clk => clk, + areset => areset, + busy => io_busy, + writeEnable => io_writeEnable, + readEnable => io_readEnable, + write => io_write, + read => io_read, + addr => io_addr + ); + + + + -- wiggle the clock @ 100MHz + clock : PROCESS + begin + clk <= '0'; + wait for 5 ns; + clk <= '1'; + wait for 5 ns; + end PROCESS clock; + + +end behave; diff --git a/zpu/hdl/zpu3/src/status.txt b/zpu/hdl/zpu3/src/status.txt new file mode 100644 index 0000000..df8773a --- /dev/null +++ b/zpu/hdl/zpu3/src/status.txt @@ -0,0 +1,67 @@ +- Make LOADSP/STORESP/ADDSP/PUSHPC & OR emulated => From 444 => 428 LUT. + A pitiful saving in return for destroying performance. +- If I reduce datapath to 8(which is useless) => 197 LUT. + +Bare bones version of ZPU3: + +- remove NOP, PUSHPC, STORESP, LOADSP, ADDSP and OR instructions. This requires + modification to the GCC toolchain and will result in a fairly significant + code increase. We should still do better than ARM though. +- reduce datapath to 16 bits. This will reduce stack usage, which is good. +- 4kBytes of RAM. + + [exec] ========================================================================= + [exec] Device utilization summary: + [exec] --------------------------- + [exec] Selected Device : 3s400ft256-4 + [exec] Number of Slices: 167 out of 3584 4% + [exec] Number of Slice Flip Flops: 126 out of 7168 1% + [exec] Number of 4 input LUTs: 288 out of 7168 4% + [exec] Number of bonded IOBs: 49 out of 173 28% + [exec] Number of BRAMs: 1 out of 16 6% + [exec] Number of GCLKs: 1 out of 8 12% + [exec] ========================================================================= + + + + +Measurements: + +- Removing PUSHPC(which is possible) reduces usage by 2 LUT's. +- I tried to introduce the instructions as seperate states at the top level, + but did not succeed in reducing LUT count. This might be an avenue to + pursue if asynchronous(?) ROM's could replace logic. +- 550 LUT @ 76MHz. 32 bit datapath & 8 bit instructions. Added seperate decode + stage. +- Tried to move memAControl into decoded opcode. Usage went up to 594 from 550. + +- using 16 bit opcodes to encode signals directly. 466 LUT's. +- w/2kBytes 32 RAM & 32 bit opcodes. 415 LUT's. +- 16 bit opcode, 16 bit datapath and 1kbyte RAM. 292 LUT's. + +- 725 LUT's @ 63MHz + Minimum period: 15.909ns{1} (Maximum frequency: 62.858MHz) +- removed addsp, loadsp & storesp. => 670 LUT's. +- removed all pushes & pops to sp. => 638 LUT's. +- removed OR instruction. => 672 LUT's. +- on the second cycle an ADD is done regardless => 713 LUT's. +- using others => 'x' for e.g. pushsp. 713 => 703. +- switching from lots of prioritized if() for decoding instruction to a case + statement. 713 => 631. +- Using ZPU1's memory scheme instead of inferred memory. 713 => 715, i.e. no + difference. +- Removing AddSP. 715 => 704 LUT's. +- Add COMPARE. 715 => 743 LUT's. +- Slight reorganization of binary operand & NOP 715 => 704. +- STORE only pops 1 (which can be fixed in the assembler). 704 => 701. +- Remove NOP. NOP is only used to clear idim_flag. Use NOT instead. +- Removing FLIP. 681 => 646. Using a different way to generate the FLIP, + 681 => 679. +- Add a seperate memory system for code? +- Use IDIM_FLAG to cache value before IM and make add single cycle. + +- by expanding the opcode to 32 bits, encoding everything in the opcode & + using case statements. 713 => 433 LUT. +- 32 bit opcode w/encoded state & 16 bit datapath. => 325 LUT +- by using 512 byte RAM, 16 bit datapath and 32 bit instructions => 285. + diff --git a/zpu/hdl/zpu3/src/testlut.vhd b/zpu/hdl/zpu3/src/testlut.vhd new file mode 100644 index 0000000..fcc8fde --- /dev/null +++ b/zpu/hdl/zpu3/src/testlut.vhd @@ -0,0 +1,106 @@ +-- Company: Zylin AS +-- +-- Hooks up the ZPU to physical pads to ensure that it is not optimized to +-- oblivion. This is purely to have something to measure LUT usage against. +-- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library zylin; +use zylin.zpu_config.all; +use zylin.zpupkg.all; + +entity ic300 is + port ( -- Clock inputs + cpu_clk_p : in std_logic; + + -- CPU interface signals + cpu_a_p : in std_logic_vector(20 downto 0); + cpu_wr_n_p : in std_logic_vector(1 downto 0); + cpu_cs_n_p : in std_logic_vector(3 downto 1); + cpu_oe_n_p : in std_logic; + cpu_d_p : out std_logic_vector(15 downto 0); + cpu_irq_p : out std_logic_vector(1 downto 0); + cpu_fiq_p : out std_logic; + cpu_wait_n_p : out std_logic; + + sdr_clk_fb_p : in std_logic -- DDR clock feedback + ); +end ic300; + +architecture behave of ic300 is + + +signal io_busy : std_logic; +signal io_read : std_logic_vector(7 downto 0); +signal io_write : std_logic_vector(7 downto 0); +signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit); +signal io_writeEnable : std_logic; +signal io_readEnable : std_logic; + + +signal cpu_we : std_logic_vector(1 downto 0); +signal cpu_re : std_logic; +signal areset : std_logic; + +-- Clock module signals +signal clk_status : std_logic_vector(2 downto 0); +signal cpu_clk : std_logic; +signal cpu_clk_2x : std_logic; +signal cpu_clk_4x : std_logic; +signal ddr_in_clk : std_logic; + + +-- Internal CPU interface signals +signal cpu_din : std_logic_vector(15 downto 0); +signal cpu_dout : std_logic_vector(15 downto 0); +signal cpu_a : std_logic_vector(20 downto 0); + +signal dummy : std_logic_vector(maxAddrBit downto minAddrBit+5); + +begin + + areset <= '0'; -- MUST BE CHANGED TO SOMETHING CORRECT + +-- cpu_d_p <= (others => '0'); + cpu_irq_p <= (others => '0'); + cpu_fiq_p <= '0'; + cpu_wait_n_p <= '0'; + + cpu_d_p(15 downto 15) <= (others => '0'); + + -- delay signals going out/in w/1 clk so the + -- ZPU does not have to drive those pins. + -- + -- these registers can be placed close to the ZPU and these + -- registers then have a full clock to drive the pins. + process(cpu_clk_p, areset) + begin + if (cpu_clk_p'event and cpu_clk_p = '1') then + cpu_d_p(0) <= io_writeEnable; + cpu_d_p(1) <= io_readEnable; + cpu_d_p(9 downto 2) <= io_write; + io_read <= cpu_a_p(7 downto 0); + -- 32 read/write registers is plenty realisitic for a minimal size + -- soft-CPU + cpu_d_p(14 downto 10) <= io_addr(minAddrBit+4 downto minAddrBit); + end if; + end process; + + + zpu: zpu_top port map ( + clk => cpu_clk_p , + areset => areset, + io_busy => '0', + io_writeEnable => io_writeEnable, + io_readEnable => io_readEnable, + io_write => io_write, + io_read => io_read, + io_addr => io_addr, + interrupt => '0' + ); + + + +end behave; diff --git a/zpu/hdl/zpu3/src/timer.vhd b/zpu/hdl/zpu3/src/timer.vhd new file mode 100644 index 0000000..65836f0 --- /dev/null +++ b/zpu/hdl/zpu3/src/timer.vhd @@ -0,0 +1,157 @@ +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity timer is + port( + clk : in std_logic; + areset : in std_logic; + we : in std_logic; + din : in std_logic_vector(7 downto 0); + adr : in std_logic_vector(2 downto 0); + dout : out std_logic_vector(7 downto 0)); +end timer; + + +architecture behave of timer is + +signal sample : std_logic; +signal reset : std_logic; + +signal c : std_logic_vector(1 to 7); + +signal cnt : std_logic_vector(63 downto 0); +signal cnt_smp : std_logic_vector(63 downto 0); + +begin + + reset <= '1' when (we = '1' and din(0) = '1') else '0'; + sample <= '1' when (we = '1' and din(1) = '1') else '0'; + + process(clk, areset) -- Carry generation + begin + if areset = '1' then + c <= "0000000"; + elsif (clk'event and clk = '1') then + if reset = '1' then + c <= "0000000"; + else + if cnt(7 downto 0) = "11111110" then + c(1) <= '1'; + else + c(1) <= '0'; + end if; + if cnt(15 downto 8) = "11111111" then + c(2) <= '1'; + else + c(2) <= '0'; + end if; + if cnt(23 downto 16) = "11111111" and c(2) = '1' then + c(3) <= '1'; + else + c(3) <= '0'; + end if; + if cnt(31 downto 24) = "11111111" and c(3) = '1' then + c(4) <= '1'; + else + c(4) <= '0'; + end if; + if cnt(39 downto 32) = "11111111" and c(4) = '1' then + c(5) <= '1'; + else + c(5) <= '0'; + end if; + if cnt(47 downto 40) = "11111111" and c(5) = '1' then + c(6) <= '1'; + else + c(6) <= '0'; + end if; + if cnt(55 downto 48) = "11111111" and c(6) = '1' then + c(7) <= '1'; + else + c(7) <= '0'; + end if; + end if; + end if; + end process; + + process(clk, areset) + begin + if areset = '1' then + cnt <= (others=>'0'); + elsif (clk'event and clk = '1') then + if reset = '1' then + cnt <= (others=>'0'); + else + cnt(7 downto 0) <= cnt(7 downto 0) + '1'; + if c(1) = '1' then + cnt(15 downto 8) <= cnt(15 downto 8) + '1'; + else + cnt(15 downto 8) <= cnt(15 downto 8); + end if; + if c(2) = '1' and c(1) = '1' then + cnt(23 downto 16) <= cnt(23 downto 16) + '1'; + else + cnt(23 downto 16) <= cnt(23 downto 16); + end if; + if c(3) = '1' and c(1) = '1' then + cnt(31 downto 24) <= cnt(31 downto 24) + '1'; + else + cnt(31 downto 24) <= cnt(31 downto 24); + end if; + if c(4) = '1' and c(1) = '1' then + cnt(39 downto 32) <= cnt(39 downto 32) + '1'; + else + cnt(39 downto 32) <= cnt(39 downto 32); + end if; + if c(5) = '1' and c(1) = '1' then + cnt(47 downto 40) <= cnt(47 downto 40) + '1'; + else + cnt(47 downto 40) <= cnt(47 downto 40); + end if; + if c(6) = '1' and c(1) = '1' then + cnt(55 downto 48) <= cnt(55 downto 48) + '1'; + else + cnt(55 downto 48) <= cnt(55 downto 48); + end if; + if c(7) = '1' and c(1) = '1' then + cnt(63 downto 56) <= cnt(63 downto 56) + '1'; + else + cnt(63 downto 56) <= cnt(63 downto 56); + end if; + end if; + end if; + end process; + + process(clk, areset) + begin + if areset = '1' then + cnt_smp <= (others=>'0'); + elsif (clk'event and clk = '1') then + if reset = '1' then + cnt_smp <= (others=>'0'); + elsif sample = '1' then + cnt_smp <= cnt; + else + cnt_smp <= cnt_smp; + end if; + end if; + end process; + + process(cnt_smp, adr) + begin + case adr is + when "000" => dout <= cnt_smp(7 downto 0); + when "001" => dout <= cnt_smp(15 downto 8); + when "010" => dout <= cnt_smp(23 downto 16); + when "011" => dout <= cnt_smp(31 downto 24); + when "100" => dout <= cnt_smp(39 downto 32); + when "101" => dout <= cnt_smp(47 downto 40); + when "110" => dout <= cnt_smp(55 downto 48); + when others => dout <= cnt_smp(63 downto 56); + end case; + end process; + + +end behave; + diff --git a/zpu/hdl/zpu3/src/trace.vhd b/zpu/hdl/zpu3/src/trace.vhd new file mode 100644 index 0000000..81eb448 --- /dev/null +++ b/zpu/hdl/zpu3/src/trace.vhd @@ -0,0 +1,80 @@ +library ieee; +use ieee.std_logic_1164.all; +--use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +use std.textio.all; + +library zylin; +use zylin.zpu_config.all; +use zylin.zpupkg.all; +use zylin.txt_util.all; + + +entity trace is + generic ( + log_file: string := "trace.txt" + ); + port( + clk : in std_logic; + begin_inst : in std_logic; + pc : in std_logic_vector(maxAddrBit downto 0); + opcode : in std_logic_vector(7 downto 0); + sp : in std_logic_vector(maxAddrBit downto 2); + memA : in std_logic_vector(wordSize-1 downto 0); + memB : in std_logic_vector(wordSize-1 downto 0); + busy : in std_logic + ); +end trace; + + +architecture behave of trace is + + +file l_file : TEXT open write_mode is log_file; + + +begin + + +-- write data and control information to a file + +receive_data: process + +variable l: line; +variable t : std_logic_vector(wordSize-1 downto 0); +variable t2 : std_logic_vector(maxAddrBit downto 0); + + + +begin + + t:= (others => '0'); + t2:= (others => '0'); + + -- print header for the logfile + print(l_file, "#pc,opcode,sp,top_of_stack "); + print(l_file, "#----------"); + print(l_file, " "); + + wait until clk = '1'; + wait until clk = '0'; + + while true loop + + if begin_inst = '1' then + t(maxAddrBit downto 2):=sp; + t2:=pc; + print(l_file, "0x" & hstr(t2) & " 0x" & hstr(opcode) & " 0x" & hstr(t) & " 0x" & hstr(memA) & " 0x" & hstr(memB)); + end if; + + wait until clk = '0'; + + end loop; + + end process receive_data; + + + +end behave; + diff --git a/zpu/hdl/zpu3/src/txt_util.vhd b/zpu/hdl/zpu3/src/txt_util.vhd new file mode 100644 index 0000000..d42303b --- /dev/null +++ b/zpu/hdl/zpu3/src/txt_util.vhd @@ -0,0 +1,586 @@ +library ieee; +use ieee.std_logic_1164.all; +use std.textio.all; + + +package txt_util is + + -- prints a message to the screen + procedure print(text: string); + + -- prints the message when active + -- useful for debug switches + procedure print(active: boolean; text: string); + + -- converts std_logic into a character + function chr(sl: std_logic) return character; + + -- converts std_logic into a string (1 to 1) + function str(sl: std_logic) return string; + + -- converts std_logic_vector into a string (binary base) + function str(slv: std_logic_vector) return string; + + -- converts boolean into a string + function str(b: boolean) return string; + + -- converts an integer into a single character + -- (can also be used for hex conversion and other bases) + function chr(int: integer) return character; + + -- converts integer into string using specified base + function str(int: integer; base: integer) return string; + + -- converts integer to string, using base 10 + function str(int: integer) return string; + + -- convert std_logic_vector into a string in hex format + function hstr(slv: std_logic_vector) return string; + + + -- functions to manipulate strings + ----------------------------------- + + -- convert a character to upper case + function to_upper(c: character) return character; + + -- convert a character to lower case + function to_lower(c: character) return character; + + -- convert a string to upper case + function to_upper(s: string) return string; + + -- convert a string to lower case + function to_lower(s: string) return string; + + + + -- functions to convert strings into other formats + -------------------------------------------------- + + -- converts a character into std_logic + function to_std_logic(c: character) return std_logic; + + -- converts a string into std_logic_vector + function to_std_logic_vector(s: string) return std_logic_vector; + + + + -- file I/O + ----------- + + -- read variable length string from input file + procedure str_read(file in_file: TEXT; + res_string: out string); + + -- print string to a file and start new line + procedure print(file out_file: TEXT; + new_string: in string); + + -- print character to a file and start new line + procedure print(file out_file: TEXT; + char: in character); + +end txt_util; + + + + +package body txt_util is + + + + + -- prints text to the screen + + procedure print(text: string) is + variable msg_line: line; + begin + write(msg_line, text); + writeline(output, msg_line); + end print; + + + + + -- prints text to the screen when active + + procedure print(active: boolean; text: string) is + begin + if active then + print(text); + end if; + end print; + + + -- converts std_logic into a character + + function chr(sl: std_logic) return character is + variable c: character; + begin + case sl is + when 'U' => c:= 'U'; + when 'X' => c:= 'X'; + when '0' => c:= '0'; + when '1' => c:= '1'; + when 'Z' => c:= 'Z'; + when 'W' => c:= 'W'; + when 'L' => c:= 'L'; + when 'H' => c:= 'H'; + when '-' => c:= '-'; + end case; + return c; + end chr; + + + + -- converts std_logic into a string (1 to 1) + + function str(sl: std_logic) return string is + variable s: string(1 to 1); + begin + s(1) := chr(sl); + return s; + end str; + + + + -- converts std_logic_vector into a string (binary base) + -- (this also takes care of the fact that the range of + -- a string is natural while a std_logic_vector may + -- have an integer range) + + function str(slv: std_logic_vector) return string is + variable result : string (1 to slv'length); + variable r : integer; + begin + r := 1; + for i in slv'range loop + result(r) := chr(slv(i)); + r := r + 1; + end loop; + return result; + end str; + + + function str(b: boolean) return string is + + begin + if b then + return "true"; + else + return "false"; + end if; + end str; + + + -- converts an integer into a character + -- for 0 to 9 the obvious mapping is used, higher + -- values are mapped to the characters A-Z + -- (this is usefull for systems with base > 10) + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function chr(int: integer) return character is + variable c: character; + begin + case int is + when 0 => c := '0'; + when 1 => c := '1'; + when 2 => c := '2'; + when 3 => c := '3'; + when 4 => c := '4'; + when 5 => c := '5'; + when 6 => c := '6'; + when 7 => c := '7'; + when 8 => c := '8'; + when 9 => c := '9'; + when 10 => c := 'A'; + when 11 => c := 'B'; + when 12 => c := 'C'; + when 13 => c := 'D'; + when 14 => c := 'E'; + when 15 => c := 'F'; + when 16 => c := 'G'; + when 17 => c := 'H'; + when 18 => c := 'I'; + when 19 => c := 'J'; + when 20 => c := 'K'; + when 21 => c := 'L'; + when 22 => c := 'M'; + when 23 => c := 'N'; + when 24 => c := 'O'; + when 25 => c := 'P'; + when 26 => c := 'Q'; + when 27 => c := 'R'; + when 28 => c := 'S'; + when 29 => c := 'T'; + when 30 => c := 'U'; + when 31 => c := 'V'; + when 32 => c := 'W'; + when 33 => c := 'X'; + when 34 => c := 'Y'; + when 35 => c := 'Z'; + when others => c := '?'; + end case; + return c; + end chr; + + + + -- convert integer to string using specified base + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function str(int: integer; base: integer) return string is + + variable temp: string(1 to 10); + variable num: integer; + variable abs_int: integer; + variable len: integer := 1; + variable power: integer := 1; + + begin + + -- bug fix for negative numbers + abs_int := abs(int); + + num := abs_int; + + while num >= base loop -- Determine how many + len := len + 1; -- characters required + num := num / base; -- to represent the + end loop ; -- number. + + for i in len downto 1 loop -- Convert the number to + temp(i) := chr(abs_int/power mod base); -- a string starting + power := power * base; -- with the right hand + end loop ; -- side. + + -- return result and add sign if required + if int < 0 then + return '-'& temp(1 to len); + else + return temp(1 to len); + end if; + + end str; + + + -- convert integer to string, using base 10 + function str(int: integer) return string is + + begin + + return str(int, 10) ; + + end str; + + + + -- converts a std_logic_vector into a hex string. + function hstr(slv: std_logic_vector) return string is + variable hexlen: integer; + variable longslv : std_logic_vector(67 downto 0) := (others => '0'); + variable hex : string(1 to 16); + variable fourbit : std_logic_vector(3 downto 0); + begin + hexlen := (slv'left+1)/4; + if (slv'left+1) mod 4 /= 0 then + hexlen := hexlen + 1; + end if; + longslv(slv'left downto 0) := slv; + for i in (hexlen -1) downto 0 loop + fourbit := longslv(((i*4)+3) downto (i*4)); + case fourbit is + when "0000" => hex(hexlen -I) := '0'; + when "0001" => hex(hexlen -I) := '1'; + when "0010" => hex(hexlen -I) := '2'; + when "0011" => hex(hexlen -I) := '3'; + when "0100" => hex(hexlen -I) := '4'; + when "0101" => hex(hexlen -I) := '5'; + when "0110" => hex(hexlen -I) := '6'; + when "0111" => hex(hexlen -I) := '7'; + when "1000" => hex(hexlen -I) := '8'; + when "1001" => hex(hexlen -I) := '9'; + when "1010" => hex(hexlen -I) := 'A'; + when "1011" => hex(hexlen -I) := 'B'; + when "1100" => hex(hexlen -I) := 'C'; + when "1101" => hex(hexlen -I) := 'D'; + when "1110" => hex(hexlen -I) := 'E'; + when "1111" => hex(hexlen -I) := 'F'; + when "ZZZZ" => hex(hexlen -I) := 'z'; + when "UUUU" => hex(hexlen -I) := 'u'; + when "XXXX" => hex(hexlen -I) := 'x'; + when others => hex(hexlen -I) := '?'; + end case; + end loop; + return hex(1 to hexlen); + end hstr; + + + + -- functions to manipulate strings + ----------------------------------- + + + -- convert a character to upper case + + function to_upper(c: character) return character is + + variable u: character; + + begin + + case c is + when 'a' => u := 'A'; + when 'b' => u := 'B'; + when 'c' => u := 'C'; + when 'd' => u := 'D'; + when 'e' => u := 'E'; + when 'f' => u := 'F'; + when 'g' => u := 'G'; + when 'h' => u := 'H'; + when 'i' => u := 'I'; + when 'j' => u := 'J'; + when 'k' => u := 'K'; + when 'l' => u := 'L'; + when 'm' => u := 'M'; + when 'n' => u := 'N'; + when 'o' => u := 'O'; + when 'p' => u := 'P'; + when 'q' => u := 'Q'; + when 'r' => u := 'R'; + when 's' => u := 'S'; + when 't' => u := 'T'; + when 'u' => u := 'U'; + when 'v' => u := 'V'; + when 'w' => u := 'W'; + when 'x' => u := 'X'; + when 'y' => u := 'Y'; + when 'z' => u := 'Z'; + when others => u := c; + end case; + + return u; + + end to_upper; + + + -- convert a character to lower case + + function to_lower(c: character) return character is + + variable l: character; + + begin + + case c is + when 'A' => l := 'a'; + when 'B' => l := 'b'; + when 'C' => l := 'c'; + when 'D' => l := 'd'; + when 'E' => l := 'e'; + when 'F' => l := 'f'; + when 'G' => l := 'g'; + when 'H' => l := 'h'; + when 'I' => l := 'i'; + when 'J' => l := 'j'; + when 'K' => l := 'k'; + when 'L' => l := 'l'; + when 'M' => l := 'm'; + when 'N' => l := 'n'; + when 'O' => l := 'o'; + when 'P' => l := 'p'; + when 'Q' => l := 'q'; + when 'R' => l := 'r'; + when 'S' => l := 's'; + when 'T' => l := 't'; + when 'U' => l := 'u'; + when 'V' => l := 'v'; + when 'W' => l := 'w'; + when 'X' => l := 'x'; + when 'Y' => l := 'y'; + when 'Z' => l := 'z'; + when others => l := c; + end case; + + return l; + + end to_lower; + + + + -- convert a string to upper case + + function to_upper(s: string) return string is + + variable uppercase: string (s'range); + + begin + + for i in s'range loop + uppercase(i):= to_upper(s(i)); + end loop; + return uppercase; + + end to_upper; + + + + -- convert a string to lower case + + function to_lower(s: string) return string is + + variable lowercase: string (s'range); + + begin + + for i in s'range loop + lowercase(i):= to_lower(s(i)); + end loop; + return lowercase; + + end to_lower; + + + +-- functions to convert strings into other types + + +-- converts a character into a std_logic + +function to_std_logic(c: character) return std_logic is + variable sl: std_logic; + begin + case c is + when 'U' => + sl := 'U'; + when 'X' => + sl := 'X'; + when '0' => + sl := '0'; + when '1' => + sl := '1'; + when 'Z' => + sl := 'Z'; + when 'W' => + sl := 'W'; + when 'L' => + sl := 'L'; + when 'H' => + sl := 'H'; + when '-' => + sl := '-'; + when others => + sl := 'X'; + end case; + return sl; + end to_std_logic; + + +-- converts a string into std_logic_vector + +function to_std_logic_vector(s: string) return std_logic_vector is + variable slv: std_logic_vector(s'high-s'low downto 0); + variable k: integer; +begin + k := s'high-s'low; + for i in s'range loop + slv(k) := to_std_logic(s(i)); + k := k - 1; + end loop; + return slv; +end to_std_logic_vector; + + + + + + +---------------- +-- file I/O -- +---------------- + + + +-- read variable length string from input file + +procedure str_read(file in_file: TEXT; + res_string: out string) is + + variable l: line; + variable c: character; + variable is_string: boolean; + + begin + + readline(in_file, l); + -- clear the contents of the result string + for i in res_string'range loop + res_string(i) := ' '; + end loop; + -- read all characters of the line, up to the length + -- of the results string + for i in res_string'range loop + read(l, c, is_string); + res_string(i) := c; + if not is_string then -- found end of line + exit; + end if; + end loop; + +end str_read; + + +-- print string to a file +procedure print(file out_file: TEXT; + new_string: in string) is + + variable l: line; + + begin + + write(l, new_string); + writeline(out_file, l); + +end print; + + +-- print character to a file and start new line +procedure print(file out_file: TEXT; + char: in character) is + + variable l: line; + + begin + + write(l, char); + writeline(out_file, l); + +end print; + + + +-- appends contents of a string to a file until line feed occurs +-- (LF is considered to be the end of the string) + +procedure str_write(file out_file: TEXT; + new_string: in string) is + begin + + for i in new_string'range loop + print(out_file, new_string(i)); + if new_string(i) = LF then -- end of string + exit; + end if; + end loop; + +end str_write; + + + + +end txt_util; + + + + diff --git a/zpu/hdl/zpu3/src/xilinx_dualport.vhd b/zpu/hdl/zpu3/src/xilinx_dualport.vhd new file mode 100644 index 0000000..0e6edc9 --- /dev/null +++ b/zpu/hdl/zpu3/src/xilinx_dualport.vhd @@ -0,0 +1,1482 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 11:47:36 03/22/05 +-- Design Name: +-- Module Name: mem_sys - behave +-- Project Name: +-- Target Device: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; +library zylin; +use zylin.zpu_config.all; + +entity dualport_ram is +port (clk : in std_logic; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit); + memAWrite : in std_logic_vector(wordSize-1 downto 0); + memARead : out std_logic_vector(wordSize-1 downto 0); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit); + memBWrite : in std_logic_vector(wordSize-1 downto 0); + memBRead : out std_logic_vector(wordSize-1 downto 0)); +end dualport_ram; + +architecture dualport_ram_arch of dualport_ram is + + +signal low : std_logic; +signal high : std_logic; +signal re : std_logic; + +begin + + high <= '1'; + low <= '0'; + re <= '1'; + + + ZPU_RAM0 : RAMB16_S2_S2 + generic map ( + INIT_A => X"0", -- Value of output RAM registers on Port A at startup + INIT_B => X"0", -- Value of output RAM registers on Port B at startup + SRVAL_A => X"0", -- Port A ouput value upon SSR assertion + SRVAL_B => X"0", -- Port B ouput value upon SSR assertion + WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" + INIT_00 => X"01A100E100010001003600770002006D000F0000000F06AD000302940008003C", + INIT_01 => X"7D4000000741F68100C800030000377935990003000300030003002A00150001", + INIT_02 => X"0007584101010C3D55555555370000000092800000001490000000066A594EBB", + INIT_03 => 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X"0000000000000000000000000000000000000000000000000000000000000000") + port map ( + DOA => memARead(1 downto 0), -- Port A 2-bit Data Output + DOB => memBRead(1 downto 0), -- Port B 2-bit Data Output + ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input + ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input + CLKA => clk, -- Port A Clock + CLKB => clk, -- Port B Clock + DIA => memAWrite(1 downto 0), -- Port A 2-bit Data Input + DIB => memBWrite(1 downto 0), -- Port B 2-bit Data Input + ENA => re, -- Port A RAM Enable Input + ENB => high, -- PortB RAM Enable Input + SSRA => low, -- Port A Synchronous Set/Reset Input + SSRB => low, -- Port B Synchronous Set/Reset Input + WEA => low, -- Port A Write Enable Input + WEB => memBWriteEnable -- Port B Write Enable Input + ); + ZPU_RAM1 : RAMB16_S2_S2 + generic map ( + INIT_A => X"0", -- Value of output RAM registers on Port A at startup + INIT_B => X"0", -- Value of output RAM registers on Port B at startup + SRVAL_A => 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X"8085515155B6E90616D6E0146830806841851156724A0EC620DD04559653A415", + INIT_21 => X"75858C001F40514145B5B40507C305515155BA2D93E496D5695545B4605B9418", + INIT_22 => X"0810203080F20408032DA18003C200E266D1C15050400CF788038803844E58A1", + INIT_23 => X"0F203CCF4CF040B12103010203480F208C80A24CF04080D0C03C1023BC82F203", + INIT_24 => X"0600F6CFD04155043040000C38832340070840C04080F2103010203C803203C8", + INIT_25 => X"0A000C00000020061C7185CFEAAAAAAAAAAAAAAA95555555555555540B080387", + INIT_26 => X"0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A", + INIT_27 => X"313A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A", + INIT_28 => X"00000000000000000000000000000000000000000001F0000000000000030000", + INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000", + INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000") + port map ( + DOA => memARead(3 downto 2), -- Port A 2-bit Data Output + DOB => memBRead(3 downto 2), -- Port B 2-bit Data Output + ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input + ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input + CLKA => clk, -- Port A Clock + CLKB => clk, -- Port B Clock + DIA => memAWrite(3 downto 2), -- Port A 2-bit Data Input + DIB => memBWrite(3 downto 2), -- Port B 2-bit Data Input + ENA => re, -- Port A RAM Enable Input + ENB => high, -- PortB RAM Enable Input + SSRA => low, -- Port A Synchronous Set/Reset Input + SSRB => low, -- Port B Synchronous Set/Reset Input + WEA => memAWriteEnable, -- Port A Write Enable Input + WEB => memBWriteEnable -- Port B Write Enable Input + ); + ZPU_RAM2 : RAMB16_S2_S2 + generic map ( + INIT_A => X"0", -- Value of output RAM registers on Port A at startup + INIT_B => X"0", -- Value of output RAM registers on Port B at startup + SRVAL_A => X"0", -- Port A ouput value upon SSR assertion + SRVAL_B => X"0", -- Port B ouput value upon SSR assertion + WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" + INIT_00 => X"0008000800000000000000010001002A000200000002000800000080000800C6", + INIT_01 => X"023AAAAAA028A040002A0000000002B000000000000000000000000000080000", + INIT_02 => X"AAA00B000020000C0000000002AAAAAAAA082AAAAAAA828AAAAAAAA008223032", + INIT_03 => X"AAA8CC000000E0000CC00E2AA33000000003800000030008300C2AAAAAAA3AAA", + INIT_04 => X"3C2828002830A0A000A0C020038AA8F02AAAA302AAAAA8000008300032A8038A", + INIT_05 => X"820800C0A0A000A0C282800283C2828002830A0A000A0F0A0A000A0C28280028", + INIT_06 => X"00000C00303000208600C841C0008C028AB00806C170000010000C0080002A30", + INIT_07 => X"8AB83808200000C000020C2000023002A830001E300380080002A00230100000", + INIT_08 => X"0000C00C00322300330800E0008020C088C0E280000B0003CC0020F08038AB83", + INIT_09 => X"40001DA0C0200401080400000CD880A23C00C23008C00A3B20303010102C8000", + INIT_0A => X"0000002AEC0C70000A0093220A8008C0230028EE00032A008CA00C230004F00B", + INIT_0B => X"9030420240C820130704202C1C108041C900C10A2CD04E0C00B34C80380E4000", + INIT_0C => X"8E32028C080030DA0244070DA342C0BC26AA40880A36C0A020D1008304020040", + INIT_0D => X"20A0303230280000AC0020A828028A20220000000C2080000B200030000C82C2", + INIT_0E => X"323200204380C300000080880B80A80B83008D037820E3A00008C0400000C203", + INIT_0F => X"00004800400008012C2000000300820808A323008D800A30008083C81C801000", + INIT_10 => X"8030808000C0002F8C0008C0000230000002200882883881C8CB0002FA000000", + INIT_11 => X"3080000A8030002A3220A08C0002800002200882883881C8CB000200C1200170", + INIT_12 => X"2F8C000AB0282A0A8CAFA006230000040008C8300080100408C08A820B003028", + INIT_13 => X"0002C0020208400002C8C1020800040002C282A0A800320003203C02000000C0", + INIT_14 => X"28002208005C2A840002A08A3009090828820E0900000A823200200507004300", + INIT_15 => X"0880A3000000020F00420E030000A080A0208208828C00000821810007080322", + INIT_16 => X"85002D080320300040088382000800000008C080E0AA0300E030A0000000008C", + INIT_17 => X"80C00C00C0010088C088C83C00028C002300800820000200013834000010B03C", + INIT_18 => X"0A20108A00290E4080038C088C00A20081C12810A30000E0A0A000000C02C804", + INIT_19 => X"C000020C0223C020C300000C002300C20882C0C813280FEF0008C0A8280900C0", + INIT_1A => X"8200000030428C0E008C100108E0CC084020000ABA882800380702E300026028", + INIT_1B => X"C0CE4280A240A02890280A240A02890280A200A02880280A2230228824330210", + INIT_1C => X"081C8000008000008C00C204DC280368800042CE0002C1C0A0000383A00E0280", + INIT_1D => X"0880030E803200308281822223088C00020082C0C08C630003008C08CA000000", + INIT_1E => X"00206003248C882E00238008023030008EB33021D0D00C002020400323020E80", + INIT_1F => X"08CA008A00888008AE0300F230223002030008AE02A00808A040812060030823", + INIT_20 => X"88B0060A0032E00880C0C8322821A22AA3020D83B00D808C182E28CA00878020", + INIT_21 => X"20000C003280A28E2030320C8B8220060A003248C6EA80C3003820302403026A", + INIT_22 => X"C2BA0AAC2AA0AE82A93AAEABA2A0B110EAAFA3EFEE8ABBAAC2C442444F300000", + INIT_23 => X"A90AA4BABAAAE82F04946BA0AAC2AA0AC82AE0BAAAE82AB24E5ABA09E42B90AA", + INIT_24 => X"AA8FAAAAACFBBEE8BED8AAA9EC0AEEBECAC1251AE82A905946BA0AA42AA0AA42", + INIT_25 => X"FAA00C000000700562A2FC8FC00000000000000000000000000000000E02C44E", + INIT_26 => X"FAA5500FFAA5500FFAA5500FFAA5500FFAA5500FFAA5500FFAA5500FFAA5500F", + INIT_27 => X"0D25500FFAA5500FFAA5500FFAA5500FFAA5500FFAA5500FFAA5500FFAA5500F", + INIT_28 => X"0000000000000000000000000000000000000000000080000000000000020000", + INIT_29 => X"00000000000000000CF000000000000000000000000000000000000000000000", + INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000") + port map ( + DOA => memARead(5 downto 4), -- Port A 2-bit Data Output + DOB => memBRead(5 downto 4), -- Port B 2-bit Data Output + ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input + ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input + CLKA => clk, -- Port A Clock + CLKB => clk, -- Port B Clock + DIA => memAWrite(5 downto 4), -- Port A 2-bit Data Input + DIB => memBWrite(5 downto 4), -- Port B 2-bit Data Input + ENA => re, -- Port A RAM Enable Input + ENB => high, -- PortB RAM Enable Input + SSRA => low, -- Port A Synchronous Set/Reset Input + SSRB => low, -- Port B Synchronous Set/Reset Input + WEA => memAWriteEnable, -- Port A Write Enable Input + WEB => memBWriteEnable -- Port B Write Enable Input + ); + ZPU_RAM3 : RAMB16_S2_S2 + generic map ( + INIT_A => X"0", -- Value of output RAM registers on Port A at startup + INIT_B => X"0", -- Value of output RAM registers on Port B at startup + SRVAL_A => X"0", -- Port A ouput value upon SSR assertion + SRVAL_B => X"0", -- Port B ouput value upon SSR assertion + WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" + INIT_00 => X"00040044000000020008000200020115000500020005000400020000000C0089", + INIT_01 => X"2975555550165082031500000000017218820002000200020002002000040000", + INIT_02 => X"5550070B0150281C000000008155555555849555555561555555555404117230", + INIT_03 => X"5555EE000000D8000CE00D9557B8000000036000000B80053000555555553555", + INIT_04 => X"31141484143450521050E090036555F0955557015555540000053200B9540365", + INIT_05 => X"4305181450521050D1414841431141484143450521050C450521050D14148414", + INIT_06 => X"088A0C0830B088305988C583C9824C914136660AEABA8A2AAA2A08084081160A", + INIT_07 => X"1544300C14808010800A0C1694A932055632082D3208420448095991A8684080", + INIT_08 => X"008210800A02130B030A8092006990C04620C540821702028C8290F568315443", + INIT_09 => X"9AB92A20C8084AAB01A820AB082640D53AA081A164C265B750A1702032124808", + INIT_0A => X"08016955148DF82021207E5595420685930996D9952351204C588C926A2FC00B", + INIT_0B => X"20E9A590C3A2192A9E9A590C3A6964A7A312A6830CEBA08A6433AA21310CA020", + INIT_0C => X"6E31A15036890AA312FD78AA33A084ACBE61820106E8843108A6A4229A90C4A4", + INIT_0D => X"11510AC9309402005C20185021614512190A28A28CF042020F108232008C45C4", + INIT_0E => X"31214814832100080940422454855404420142448520CC9E00A4C2C40808D90B", + INIT_0F => X"20268482C800150257062188232541244453130942420532044203C43C593612", + INIT_10 => X"7830466802C008134C8064C8208132082025942102102103D4C6202525980008", + INIT_11 => X"3241200540B2481531105A4C0002082025942102102103D4C6202520FB5002B0", + INIT_12 => X"134C801D711635AD4C525809932060882024C4202648202924C855430F223516", + INIT_13 => X"8282C80B91A8820265040201042028202691635AD44231040B103C99200003C8", + INIT_14 => X"9600999400AC154C98015A653207468C14C808871080914131A01A0A0F24C301", + INIT_15 => X"044853098808030C00C111820210C16080C44104654C8220949E86A80B240B19", + INIT_16 => X"4B46A224231280A0801E421B0AA401202064C048D1552324123252026480814C", + INIT_17 => X"48E88E88E8828204C864C42C90814C8053204205108099080A743C809070883D", + INIT_18 => X"0596A8858AA60CAA58004C066C60594203DB16B053201012505808208D03C468", + INIT_19 => X"C818807D4458A0C2C202603D081702E6862888C460988FDF02089AD4164688C6", + INIT_1A => X"420200A2B99B4C29286E640205F1CC088844081F49601684300F25132009D084", + INIT_1B => X"C9C2831215A0C4856831215A0C4856831215A0C485683121593251515C730222", + INIT_1C => X"203D4080904A20086864E4682C918096010081C30A0292C6442020EBD9160148", + INIT_1D => X"0548232D623112344203115113204C82084015E8C94D930063204C94D5202448", + INIT_1E => X"1080842348196501021064050170B2005553108554208C902010C06313012D42", + INIT_1F => X"04C500542A464205692388F93219320523420569084206041080560084234606", + INIT_20 => X"660408084234C2A548C8D63106851905632142433C9D654C965D54C5005B0A92", + INIT_21 => X"00201E21706259615232358C576854080842348195C541C3003112361A235591", + INIT_22 => X"005000100050140005055541515105505555514554414515441544554002020A", + INIT_23 => X"0500145455514015051545000140050014001055514000514054500114005001", + INIT_24 => X"4545554554515544005000055401555541414551400050515450001400500140", + INIT_25 => X"FFF00C000000501394E93A4FC000000000000000000000000000000005041545", + INIT_26 => X"FFFFFFFAAAAAAAA5555555500000000FFFFFFFFAAAAAAAA5555555500000000F", + INIT_27 => X"093FFFFAAAAAAAA5555555500000000FFFFFFFFAAAAAAAA5555555500000000F", + INIT_28 => X"0000000000000000000000000000000000000000000070000000000000000000", + INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000", + INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000") + port map ( + DOA => memARead(7 downto 6), -- Port A 2-bit Data Output + DOB => memBRead(7 downto 6), -- Port B 2-bit Data Output + ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input + ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input + CLKA => clk, -- Port A Clock + CLKB => clk, -- Port B Clock + DIA => memAWrite(7 downto 6), -- Port A 2-bit Data Input + DIB => memBWrite(7 downto 6), -- Port B 2-bit Data Input + ENA => re, -- Port A RAM Enable Input + ENB => high, -- PortB RAM Enable Input + SSRA => low, -- Port A Synchronous Set/Reset Input + SSRB => low, -- Port B Synchronous Set/Reset Input + WEA => memAWriteEnable, -- Port A Write Enable Input + WEB => memBWriteEnable -- Port B Write Enable Input + ); + ZPU_RAM4 : RAMB16_S2_S2 + generic map ( + INIT_A => X"0", -- Value of output RAM registers on Port A at startup + INIT_B => X"0", -- Value of output RAM registers on Port B at startup + SRVAL_A => X"0", -- Port A ouput value upon SSR assertion + SRVAL_B => X"0", -- Port B ouput value upon SSR assertion + WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" + INIT_00 => X"02550195000200030077007600030359001E0003001C09DD000307EA00000064", + INIT_01 => X"706555555755A365027600130001222837780003000300030003001600120005", + INIT_02 => X"555709831042087800000000D355555554DA5555555536355555554D5AA46DF7", + INIT_03 => X"5541AA00002A2800AC82A25506A8000000A8A00002A200018329555555559555", + INIT_04 => X"A6956586F8AA55961BE2AAACA89541B85555060D555554AAC001822A2154A895", + INIT_05 => X"15564C3A55961BE2A956586F8A6956586F8AA55961BE29A55961BE2A956586F8", + INIT_06 => X"C4DD0F9C3E254D554C5A94D4A3500F07C1D00B5C330CF3C3F3CC5544DD52494A", + INIT_07 => X"E1B5D755571D97818E76755CE71835646436755036461D5558E13248A5555D99", + INIT_08 => X"DD953042010B03E0024CD486B931E7579D27491D5550765A0D55154409D21B5D", + INIT_09 => X"4424F150D91D3714CDB070020425D4601515551100F8018994D19555114041D5", + INIT_0A => X"75543554959F55D556679190489D554403E0072C4060DE140F41BA11D6E44451", + INIT_0B => X"6845704D611544DC545704D5111C1371144C1DC79E5C71E113697174D0747754", + INIT_0C => X"38344823553107174E413471697193C477905D84C7455344DE19D378574D9313", + INIT_0D => X"55DD48483E1B310505675CCD58860351454104100F441D5552558C3655B95098", + INIT_0E => X"65111AF8DD1AD055541D1D54F08F41D115509285CE0754B47450F82DDB5B6556", + INIT_0F => X"D550499F18E4B076DA4214846A8499649843C3E382555435685D9495496C3106", + INIT_10 => X"4DD55C3555001BD40D9110D5558C3701D5515951951D5114D0D2678221658145", + INIT_11 => X"340D6B9445289AC434711C0F9F15CDD5515951951D5114D0D2678267C4950175", + INIT_12 => X"F40D912D604235CD0D221D444356E005D550D1555381555500D97D875686A420", + INIT_13 => X"80549BE357DF5D553D7DD55A1DD555D557D4336CD746A5475E5D6A216391175A", + INIT_14 => X"010501F5405D40C8D5940C1435580D3849CE5740B18E1910340745C556881D5B", + INIT_15 => X"9B4603E049D9C0084555521555D5710555774D34040D536B8421F9D453441141", + INIT_16 => X"041175106E554455555F9551036500638510F943D169668356285678818E340F", + INIT_17 => X"D8F98F98F98FDD00D920DD6A08440D9103545D563755637555C621AE0505C164", + INIT_18 => X"1157D3918169757BC8590F9710611503950440C103644653210DD555BE179544", + INIT_19 => X"D54C433594B0854455550145755140154527D89514BD8B95754C1CD64F0D1906", + INIT_1A => X"5551405045830F8D75D16D155464110C4D99D918486C8049DD528503667CD750", + INIT_1B => X"A3429553102554C409553102554C409553102554C4095531003C972139044313", + INIT_1C => X"D151519E005111D94414170D204D0484CA4555500503216C59D5301C3526441B", + INIT_1D => X"57046685066556A495D5DD4103D10D51773591C0DE4C83E503570DE4CD6B889D", + INIT_1E => X"1775776F4CCF97A4766261D877D536396DC347407021AA255525558D03E7055D", + INIT_1F => X"30F31DBD15BBDD56706F9BF83648357C6F5D547377B6FD0855545F35776F3A33", + INIT_20 => X"8837575776B0C15859D9843C816FE39A4366411D28401C0D41F3E0FB1D9F4566", + INIT_21 => X"07670D146590C32F1676610FF31267545776B40CCCCFC89D59D5A6E8DC6F2CDF", + INIT_22 => X"CC30300C00300C000C320499A95208E1C4535A2755E92DCB882389238A427556", + INIT_23 => X"000002951C50C080313003030BC02D003400811C50C002CB87E43003F803E300", + INIT_24 => X"5841550C544F955C0740000C380831B1C14C8C00C0C023330030300800D00000", + INIT_25 => X"FFF00C000000F01400FFEAB3C0000000000000003FFFFFFFEAAA9543850823A8", + INIT_26 => X"555555555555555555555555555555500000000000000000000000000000000F", + INIT_27 => X"3A3FFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA5", + INIT_28 => X"00000000000000000000000000000000000000000000B0000000000000020000", + INIT_29 => X"00000000000000000CE000000000000000000000000000000000000000000000", + INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000") + port map ( + DOA => memARead(9 downto 8), -- Port A 2-bit Data Output + DOB => memBRead(9 downto 8), -- Port B 2-bit Data Output + ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input + ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input + CLKA => clk, -- Port A Clock + CLKB => clk, -- Port B Clock + DIA => memAWrite(9 downto 8), -- Port A 2-bit Data Input + DIB => memBWrite(9 downto 8), -- Port B 2-bit Data Input + ENA => re, -- Port A RAM Enable Input + ENB => high, -- PortB RAM Enable Input + SSRA => low, -- Port A Synchronous Set/Reset Input + SSRB => low, -- Port B Synchronous Set/Reset Input + WEA => memAWriteEnable, -- Port A Write Enable Input + WEB => memBWriteEnable -- Port B Write Enable Input + ); + ZPU_RAM5 : RAMB16_S2_S2 + generic map ( + INIT_A => X"0", -- Value of output RAM registers on Port A at startup + INIT_B => X"0", -- Value of output RAM registers on Port B at startup + SRVAL_A => X"0", -- Port A ouput value upon SSR assertion + SRVAL_B => X"0", -- Port B ouput value upon SSR assertion + WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" + INIT_00 => X"0028016800040002006B00A40002002500150002001500200002078500620060", + INIT_01 => X"090555555A16501F0555001E00011554543400020002000200020008001C0004", + INIT_02 => X"555A082282D08E55000000009355555555841555555561455555555058510938", + INIT_03 => X"5564320000C598030D3C595590C80000031660000C58C0246FC1555555550555", + INIT_04 => X"12084505C8182114172040DF165564345555903D55555715C0246FC58D571655", + INIT_05 => X"96296A48211417206084505C81A084505C8182114172058211417206084505C8", + INIT_06 => X"E18B5B896D1CD962A7546A5450CF5B71580861C4E138618E91B8586205916041", + INIT_07 => X"17146758A54584656E0B18A04CF16646C1660945661A862854D183703F0F0588", + INIT_08 => X"0582C0F063C156D030459915F861A18480718705961516185996751FBC617146", + INIT_09 => X"378E9CA59823E272012C64BB400C144101558A49B5B4BD50710945615F380059", + INIT_0A => X"1852855419554461645F509EE3462926D6D2F546F1595CCC5B756511B2343155", + INIT_0B => X"B7702AFAD5CB6C8B1702AFAD9C0AB629CBD9C4BA28082E8CBEA02C8E801A1166", + INIT_0C => X"0166AC531C4502C8D941902C80263E735D40066BA5723A8DA8CCBEA322DAFEBE", + INIT_0D => X"A01240416D1107E5A19151016694527B3730C30C5B44061651A15D6601668510", + INIT_0E => X"DA01D4D9861C12585D05065D2811A8519615D0104661940514C5B41453955451", + INIT_0F => X"6168095D15E114149C58BE2F5542950D5956D6D080162966440614694692E3C5", + INIT_10 => X"40628441544996DA5988A599654D643461695D65165D65D45596534A07012D74", + INIT_11 => X"668D5784B55457D16459CA5B8496B061695D65165D65D4559653465304D4BC14", + INIT_12 => X"CA5985D59F72958459207121566453606155996169016161A5985D5559451715", + INIT_13 => X"4D5555D195940616913116116061606165B7295844555A2759A175215B85D555", + INIT_14 => X"70B417352F056B6A715694656668C4C6756858D0D14D121D66E164A05D440611", + INIT_15 => X"80ACD6D20058E080458A141616C58D8595B41041C55991577DC058B25D774D57", + INIT_16 => X"A01F145855A314C58515165132DC89574495B80B0855514715545534054D025B", + INIT_17 => X"17495497495C066598559D45356659889666462941859D185867416D14046975", + INIT_18 => X"99524CDD7720192513505B84634995CA1454710996622409D9C0596565546840", + INIT_19 => X"996DF895A74805A21616894518A86430CC0D5568440545001645484671C4D444", + INIT_1A => X"561B22C94D195B472D1345162807D10000A4582043DF16F464514116627A61A5", + INIT_1B => X"5100966998A59A662966998A59A662966998A59A66296699896E9892E1FC400C", + INIT_1C => X"6545195D1AC85458697806A50148143DF1458A102C00D046646190140D247717", + INIT_1D => X"280F5144451A15D51616D05456C1599118412815927256E196655927215B4460", + INIT_1E => X"11858751486456951621685817855578511641A9DF0165016105845C16E02E06", + INIT_1F => X"35B8051B0CB846294559D7456619664659462A441B75B441C587E5058759A619", + INIT_20 => X"641759587598E0C15454556E8BAA56A5566140865C12B2596B3255B40507C305", + INIT_21 => X"C1632BBD073618665515155B50B647595875948676CA8846106405D4D05DA420", + INIT_22 => X"C030003C40F10C040D284715799040C1155498499FE9FDA30103010304C41658", + INIT_23 => X"0D1036025D60C0F617D18300080422103440125D60C0420B00C4301190424003", + INIT_24 => X"D0456C31905419FC4108000C300999F50245F460C000C14D1830003040D10344", + INIT_25 => X"AAA00C000000002AAA555573EAAAAAAAAAAAAAAA955555555555555407010320", + INIT_26 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA", + INIT_27 => X"003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", + INIT_28 => X"0000000000000000000000000000000000000000000060000000000000020000", + INIT_29 => X"00000000000000000CE000000000000000000000000000000000000000000000", + INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000") + port map ( + DOA => memARead(11 downto 10), -- Port A 2-bit Data Output + DOB => memBRead(11 downto 10), -- Port B 2-bit Data Output + ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input + ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input + CLKA => clk, -- Port A Clock + CLKB => clk, -- Port B Clock + DIA => memAWrite(11 downto 10), -- Port A 2-bit Data Input + DIB => memBWrite(11 downto 10), -- Port B 2-bit Data Input + ENA => re, -- Port A RAM Enable Input + ENB => high, -- PortB RAM Enable Input + SSRA => low, -- Port A Synchronous Set/Reset Input + SSRB => low, -- Port B Synchronous Set/Reset Input + WEA => memAWriteEnable, -- Port A Write Enable Input + WEB => memBWriteEnable -- Port B Write Enable Input + ); + ZPU_RAM6 : RAMB16_S2_S2 + generic map ( + INIT_A => X"0", -- Value of output RAM registers on Port A at startup + INIT_B => X"0", -- Value of output RAM registers on Port B at startup + SRVAL_A => X"0", -- Port A ouput value upon SSR assertion + SRVAL_B => X"0", -- Port B ouput value upon SSR assertion + WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" + INIT_00 => X"00000000000000000001000200000000000200000002008800000300000000B0", + INIT_01 => X"202000000800080A010000000000080202B20000000000000000000200000000", + INIT_02 => X"0008A20300A00C02AAAAAAAA0B00000000020000000000000000000002002830", + INIT_03 => X"0000B8AAAAC002AB2CBC000002E2AAAAAB000AAAAC0EEA800FC8000000000000", + INIT_04 => X"84A000A0C2828002830A22CF000000B00000023C00000300EA800FC0EC030000", + INIT_05 => X"000003028002830A0A000A0C284A000A0C2828002830A328002830A0A000A0C2", + INIT_06 => X"3C0003000CA33000040300400B38030004028238020082002600000C8C080000", + INIT_07 => X"8A08CB00028C0A803C31300EA08000208000200800208C0003C8380232828C02", + INIT_08 => X"8C000B04881380C8800F0400B03803020093020C000A30280000202224C0A08C", + INIT_09 => X"003914C000B6C0E02C000003000820C882A00080003200900D800800B802D8C0", + INIT_0A => X"30003002B808C8C004033000800C020000C802409E0608CE03080080A00C0302", + INIT_0B => X"C0D00083034C08010D100830340028034CB3403C3000030420C004DA00322302", + INIT_0C => X"E0002A07384C004DB0C22004D00B6894C2820CAE22D364D8304820C120932820", + INIT_0D => X"00E002C00C811C0028A3282C08228A2400CB2CB203C08C0000002C0008000200", + INIT_0E => X"000E80CACC0B80002A0C0C80280088C20008800A22B32C0E30803220CB808800", + INIT_0F => X"C002283E00C289320830C830042028000200C0C8200000002A8C80000022BC30", + INIT_10 => X"88C0020880BB82C800080000003C02F8C0000C08408008008002032202088038", + INIT_11 => X"022C0B02300202C0000020030A00B8C0000C0840800800800203220B08800010", + INIT_12 => X"C8000A04800A12240020200280022F80C000000001080000200000010020A080", + INIT_13 => X"BE8081C90A260C0010BA8008A8C000C00100A122401000030C0030880F0A0080", + INIT_14 => X"0A00822000040020688002080028208008480200401C8A80002302800C200C08", + INIT_15 => X"00A000C8D8C0C0800000028000E00C20200082082000080B202050200E020802", + INIT_16 => X"000218020C02208000050088F8834C0F2A20300FB400002380C20072201CA803", + INIT_17 => X"00882883881C8CB000200C008880000800028C00230002300003203C81004038", + INIT_18 => X"000008428210320A080A03020820002200880A80000202B92028C00028000022", + INIT_19 => X"00890210803420210000280A30001020B8C8C200000C1800302F82430A2083B2", + INIT_1A => X"0000D0B68823032CC0A208000200000C20A8C0E000830008C800228000B06320", + INIT_1B => X"0820808E8CA023A12808E84A023A12808E84A023A12808E8480C0B8AE0040304", + INIT_1C => X"C808003C8233A0C00C30080800009008320000000B83A00828C0082808800001", + INIT_1D => X"00B00820E0C000A08080022200C6000A322860C0083880C000020083800F2028", + INIT_1E => X"E320230E188022AA300E24C13380203035000332ED0C20800080020E80C03C8C", + INIT_1F => X"70320C8A08388C003602C18800000022028C00363330F3888002A2E0230A2220", + INIT_20 => X"2263020230E1E0880182800C92308AAA0000384C8C202300C23220320C8B8220", + INIT_21 => X"E303800A0100820A0060A003082303020230E18800DAB48C08C8B0E0C80202AA", + INIT_22 => X"4AAA2AA4AAA2AA8AAB2AEEEAE2A12512CFEFA2FAAA8F2AA2C59444944F803000", + INIT_23 => X"A32A8CAAABAAA8EF04892AA3AC4AB02AD0AAC2ABAAA8AB12CF7EAA2B4CA932AA", + INIT_24 => X"AE8EEAAFA8FBFAA8AE94AAAAAC8FABAA8A81224AA8EA305892AA3A8CAAB2A8CA", + INIT_25 => X"00000C000000100000000033C00000000000000000000000000000000A04944E", + INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_27 => X"1500000000000000000000000000000000000000000000000000000000000000", + INIT_28 => X"00000000000000000000000000000000000000000000A0000000000000000000", + INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000", + INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000") + port map ( + DOA => memARead(13 downto 12), -- Port A 2-bit Data Output + DOB => memBRead(13 downto 12), -- Port B 2-bit Data Output + ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input + ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input + CLKA => clk, -- Port A Clock + CLKB => clk, -- Port B Clock + DIA => memAWrite(13 downto 12), -- Port A 2-bit Data Input + DIB => memBWrite(13 downto 12), -- Port B 2-bit Data Input + ENA => re, -- Port A RAM Enable Input + ENB => high, -- PortB RAM Enable Input + SSRA => low, -- Port A Synchronous Set/Reset Input + SSRB => low, -- Port B Synchronous Set/Reset Input + WEA => memAWriteEnable, -- Port A Write Enable Input + WEB => memBWriteEnable -- Port B Write Enable Input + ); + ZPU_RAM7 : RAMB16_S2_S2 + generic map ( + INIT_A => X"0", -- Value of output RAM registers on Port A at startup + INIT_B => X"0", -- Value of output RAM registers on Port B at startup + SRVAL_A => X"0", -- Port A ouput value upon SSR assertion + SRVAL_B => X"0", -- Port B ouput value upon SSR assertion + WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" + INIT_00 => X"028200020002000000020081000001800000000000000A4600000320002A00CA", + INIT_01 => X"905000000C800680020000080000444101710000000000000000001100000002", + INIT_02 => X"000C51A6981A9A015555555587000000002140000000081000000006010850B2", + INIT_03 => X"0001745555E001579D7E000005D15555578005555E0DD5410FE400000000A000", + INIT_04 => X"4C521050D1414841434519CF80000172000005BC00000380D5410FE0DC038000", + INIT_05 => X"00800311484143450521050D148521050D1414841434521484143450521050D1", + INIT_06 => X"B21023208C60000808020082040823582DA15A0A0A828A202A0202024C040620", + INIT_07 => X"5454C702054C25583CB23201564080111480B02080B14C8202C4451530504C29", + INIT_08 => X"4C2CD70F843F88C6782C0E40B2442321A663258C008530942000508418C9454C", + INIT_09 => X"90332AA202A8C4867C420A02E68152956550205C02310276425C64087C4124C0", + INIT_0A => X"320900014031E4C8090F7980048C817008C409D4390C4DAD23442049465EBE08", + INIT_0B => X"A6EA40229BAA42128EA40229BA900843AA22A93A69924E9A08A64AA22E319301", + INIT_0C => X"1080551FB198A8AA21E92A8AA64A88A82A6D8C6B22EA88A329A508A694328808", + INIT_0D => X"091921E08C46AC38145316580551649C4024924923E24C8008083C80A4202506", + INIT_0E => X"809103D78C9C4802118C8C50462554C94085486515E31E1D32123198C7831708", + INIT_0F => X"C805903D82C942314421C0700C1514904108C8C518408080114C42002005E000", + INIT_10 => X"64C82514423FC3D4202E1200002C8134C8000C048048048202080B1484546834", + INIT_11 => X"81380F25708102D882181023258074C8000C048048048202080B140BA642AAA2", + INIT_12 => X"D42025987905A11A208844A948010368C80200080368080812025822081080C0", + INIT_13 => X"0D4202C615198C803475408494C808C802D05A11A220C0A30C0830540B258202", + INIT_14 => X"45A24450AAA8001ED44005148016322E0482011A9C2C554C8013056A0C128C84", + INIT_15 => X"267108C424C2CAA22020854080D02C10102165961120040B501AB6060C09A404", + INIT_16 => X"2A80668308085210208B405C3410A90B1512326F49010C17408110F1542C5423", + INIT_17 => X"42102102103D4C6202520C204660202E08014C80932001320243982C52A28031", + INIT_18 => X"800422C160763185560523251E58003082160568080B914B1814C00020820259", + INIT_19 => X"00470222620A101A808054213206208A2193C202621C225A301FD1A305320225", + INIT_1A => X"408028096013231C01580480818028AE6674C292201F5104C60814480A709312", + INIT_1B => X"05A8405D4A5017529405D4A5017529405D4A5017529405D4A48D445D900A2B99", + INIT_1C => X"C421882C5F0098C24E6697488A6D6201F520208A80EBD91434C81A9690E40082", + INIT_1D => X"81700C11108080C14040851988D92005316491C20534C8C808012053440F1254", + INIT_1E => X"1310130866891415309108C2332080B255482315568030580850212D48C9BC4C", + INIT_1F => X"B2358C41A1714C810908C22080848011084C81093370B4E690215110130841A2", + INIT_20 => X"119301013086DA150202108D206544150809068C5E980520407852358C576850", + INIT_21 => X"D30B40018241451440808423460613010130866895E50E4C84C54086C6085545", + INIT_22 => X"4410101440510404051545555151455155455154554145554515451540283001", + INIT_23 => X"0510145455504015151141010144051054405055504040514154101054415101", + INIT_24 => X"5445551554515554415400041401555541454450404051511410101440510144", + INIT_25 => X"55500C000000D00000000033C000000000000000000000000000000005051544", + INIT_26 => X"5555555555555555555555555555555555555555555555555555555555555555", + INIT_27 => X"1515555555555555555555555555555555555555555555555555555555555555", + INIT_28 => X"00000000000000000000000000000000000000000000E0000000000000010000", + INIT_29 => X"00000000000000000CD000000000000000000000000000000000000000000000", + INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000") + port map ( + DOA => memARead(15 downto 14), -- Port A 2-bit Data Output + DOB => memBRead(15 downto 14), -- Port B 2-bit Data Output + ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input + ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input + CLKA => clk, -- Port A Clock + CLKB => clk, -- Port B Clock + DIA => memAWrite(15 downto 14), -- Port A 2-bit Data Input + DIB => memBWrite(15 downto 14), -- Port B 2-bit Data Input + ENA => re, -- Port A RAM Enable Input + ENB => high, -- PortB RAM Enable Input + SSRA => low, -- Port A Synchronous Set/Reset Input + SSRB => low, -- Port B Synchronous Set/Reset Input + WEA => memAWriteEnable, -- Port A Write Enable Input + WEB => memBWriteEnable -- Port B Write Enable Input + ); + ZPU_RAM8 : RAMB16_S2_S2 + generic map ( + INIT_A => X"0", -- Value of output RAM registers on Port A at startup + INIT_B => X"0", -- Value of output RAM registers on Port B at startup + SRVAL_A => X"0", -- Port A ouput value upon SSR assertion + SRVAL_B => X"0", -- Port B ouput value upon SSR assertion + WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" + INIT_00 => X"015502550005000300F6005200030357002A0003002A066500030BDD001C000F", + INIT_01 => X"793000000D4EC7C70123002F0001191522250003000300030003003D00060009", + INIT_02 => X"000D601010C040A555555554DA00000001DCC000000077600000001645953DFD", + INIT_03 => X"0024C9555693855A7CB92A00932555555A4E15556932D564899E00000000A000", + INIT_04 => X"5D961BE2A956586F8AA567064E0024F0000093A4000002405564CB932C024A80", + INIT_05 => X"5D510E56586F8AA55961BE2A955961BE2A956586F8AA566586F8AA55961BE2A9", + INIT_06 => X"A2CD6E8D995445D50415505D54486DAC86F2014401004100D90F76420F951317", + INIT_07 => X"1510D0756C0F85016A08356D69D1AE7545BE09D1BE090D551595211564540F86", + INIT_08 => X"0F805644C511DB9595044165E874C364C783450F96543E146F9B074370D9510D", + INIT_09 => X"D0059716B8C5137DC0372001534D13641227546416A51443126409D9590120F9", + INIT_0A => X"36560854A95A40D9CF52944C950D51909A94912C5C5517E569C5555639E4D274", + INIT_0B => X"1C5D34787171C74DC5D34787174D1531714974D1874D34571E113716083403E4", + INIT_0C => X"11BC45059E74587172579D87113C5A54D9100D71F15C56148574D215D3785A1E", + INIT_0D => X"57101951A951691C0443C079D85206791520820865500D917555498E15555D43", + INIT_0E => X"5643D4020DC94C76460F0D54FD2FB0F89D9E0713B48365143E566570FDD56475", + INIT_0F => X"D9515D4955A1203DB50398E455555344471A9996A41D51BE6B0D1D51D5B6B105", + INIT_10 => X"10D5514C5D3FD4116B8D1639C1459E40D9C401D0DD3DD2DD36BE5659440CD400", + INIT_11 => X"9F7C5E85475555A1AF08416284DD00D9F401D01D31D21D36BE56595B07104410", + INIT_12 => X"016B86C4001110346B344830DAE76470D916F1D9C089D9C816783811755571F1", + INIT_13 => X"905DD595B4040D9C0A341D9FD0D9C0D98D1111034FC55553757DD5545E865D17", + INIT_14 => X"11907484261415500C0179A5BE6373A31C467445C5596D8D8C03C3F0755C0D9D", + INIT_15 => X"83E4589420F845D51755749D9C37408777410410826F9657E7434002771C0034", + INIT_16 => X"354053475556521764441D2BC0A4815E5456A851083F555955557525B559536A", + INIT_17 => X"951951D5114D0D2678263DD55BD1678D58E60D5903659436431C1549535241DD", + INIT_18 => X"44003B04E4403403010B6681900440719D0110345BE343C85440F9715CDD5515", + INIT_19 => X"7986431374C5975D9D99B9D835502D49FC805555310551403E56034C107395E0", + INIT_1A => X"9D9120C85C8066553413241D5C5014B168B0F8D350CD1D40D275549BE1100366", + INIT_1B => X"54B49D071CE741C739D071CE741C739D071C2741C739D071CD815C8654051858", + INIT_1C => X"D1D145596B4080F8C1518D8456E6310CD53754060C2C353430D91D85BC110115", + INIT_1D => X"5264555525557571DDDD84001BD76B9437189636B0241BA01AE46B024D525D40", + INIT_1E => X"0377485474C5E3903E3400F03FC755E86D59C3478B415575D96767055BA26C0D", + INIT_1F => X"E6A10F207A310D5D0455154D8E21AE7F540D550437D5EC0C6767EA6748574D31", + INIT_20 => X"EF2D7675C576C499D515DDAD233DBA2F18E0360D814C1E67410C66A10FB31265", + INIT_21 => X"03E10116505841CC7565776BFB332B767485444C49EF430D90DD1554E856A57E", + INIT_22 => X"060010B042F18004022C024D1C0C8C024C88055CCD9726B03330313015D43E70", + INIT_23 => X"2E10B94C860800712F77200103040C105040C086080040C8029A0013B84AE10B", + INIT_24 => X"7D02A0C02689FCD84294002EC00712EB68CBDDC80042C2F7720010B040210B84", + INIT_25 => X"00008C00000000000000003CC0000000000000003FFFFFFFEAAA954349323032", + INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_28 => X"0000000000000000000000000000000000000000000C20000000000000000000", + INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000", + INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000") + port map ( + DOA => memARead(17 downto 16), -- Port A 2-bit Data Output + DOB => memBRead(17 downto 16), -- Port B 2-bit Data Output + ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input + ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input + CLKA => clk, -- Port A Clock + CLKB => clk, -- Port B Clock + DIA => memAWrite(17 downto 16), -- Port A 2-bit Data Input + DIB => memBWrite(17 downto 16), -- Port B 2-bit Data Input + ENA => re, -- Port A RAM Enable Input + ENB => high, -- PortB RAM Enable Input + SSRA => low, -- Port A Synchronous Set/Reset Input + SSRB => low, -- Port B Synchronous Set/Reset Input + WEA => memAWriteEnable, -- Port A Write Enable Input + WEB => memBWriteEnable -- Port B Write Enable Input + ); + ZPU_RAM9 : RAMB16_S2_S2 + generic map ( + INIT_A => X"0", -- Value of output RAM registers on Port A at startup + INIT_B => X"0", -- Value of output RAM registers on Port B at startup + SRVAL_A => X"0", -- Port A ouput value upon SSR assertion + SRVAL_B => X"0", -- Port B ouput value upon SSR assertion + WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" + INIT_00 => X"009600160000000600E4009200060557000C0006000C02960006039300FA003A", + INIT_01 => X"B5D000000581E4BC081000060000110A155A0006000600060006004200740002", + INIT_02 => X"000959D19C274612555555558600000001AD000000006B60000000120541D009", + INIT_03 => X"00176555560F45581050E6005D955555583D155560F955579000000000002000", + INIT_04 => X"811417206084505C818201B03D00174C00005DC0000000331557D00F94003980", + INIT_05 => X"05904844505C8182114172060811417206084505C818204505C8182114172060", + INIT_06 => X"00B95D4956847059025610062B41597E299E04403812086A800816305B801AB3", + INIT_07 => X"16159116405B452D7501664AC09D5E01854D00657D01599654685565C7F75B44", + INIT_08 => X"5B405444511054691C433355D45496618696555B86456D155784919B25916159", + INIT_09 => X"970A02C57472B208C4E68B5073F10827B8D166E7551A574890E7B45841D905B8", + INIT_0A => X"6608B8000D640598E4514E75D5599B9D54695D15555904C55955628C08C3901A", + INIT_0B => X"C00B65A3002C1BE880B25A3002E96FA02CB02E9C30CB670268CB22CAE16696E1", + INIT_0C => X"356F85644232302C85304B02CBE7201284D6591C100B20C8302FA0CCBEB32C68", + INIT_0D => X"5A1BF03D468501103796DC24564AC421C50C30C3550C59841859454D1161632D", + INIT_0E => X"85D4D448590820161C5B595667C5A5B00581FCE8121643C16C95DA45B0D65418", + INIT_0F => X"985951471451596F6CB8120458A153154515546A2F45996E0059061061011525", + INIT_10 => X"659969F546555451534615B81D455DA5981400574554574665B551AAF5F542E5", + INIT_11 => X"6E55514D618A545D4CF26151450565984400574554574665B151AA555CD50306", + INIT_12 => X"615B4500879C03135F4F516357E04A6598053058E04058E495F4D4C818A5A16D", + INIT_13 => X"2B06D5689712598E0D3485815598E5986439C031312585AA184862965D454615", + INIT_14 => X"5C56557980C2D511356D69554E245A019110147CD1668D555F16CD6E18AD5981", + INIT_15 => X"4547156A05B44C709165B5058C4155014151861854578151255C0A1E1890E155", + INIT_16 => X"2C2148055859485162900507A804095DA5159403033C58A4458A051A45469451", + INIT_17 => X"D65165D65D4559653465B062850D534657E159901662056619D03156BAC41061", + INIT_18 => X"B40CA027558966CDB0B5594581EB405406459A4355D1A9405265B84963061695", + INIT_19 => X"B88C400052E3616445894869665813035A621616A3C160716E0031309D5A160E", + INIT_1A => X"85810003DF1055A137F7C24592C0B0534655B4753E2568459918A017D1809655", + INIT_1B => X"2ABF45A916115A458456916115A458456916D15A4584569161554844B32CD4D2", + INIT_1C => X"90665146A34835B4405B2243F45997E25841667C00140D3415982F3F5F100D16", + INIT_1D => X"914458A14585B58D0505057316525381649A743537DD175394E25B7DD251A445", + INIT_1E => X"564156596A42E5216D10D5B16F1195145157D6798BF562805801602E55501859", + INIT_1F => X"55955BA2D8F159910159565D4D217E105A5995016785D8328160E61156594E90", + INIT_20 => X"ED891416A5952D91D6561D652197FA6617D2065983117557579455155B50B645", + INIT_21 => X"96D1C15CCF5965D07595875966192514156597A438065D59859925A5D55A7182", + INIT_22 => X"86601098427198040F00102D2065F4638C0066147C25890194D197D1A48D6E32", + INIT_23 => X"2F10BD01DBE980D133F4660103040C10F04001DBE98040CF435E60123048C109", + INIT_24 => X"41CC71F0461277C043200020184454DCA90C7D198042D31F466010B440F10BC4", + INIT_25 => X"00000C00000000000000003CEAAAAAAAAAAAAAAA95555555555555540D14D180", + INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_28 => X"0000000000000000000000000000000000000000000B70000000000000000000", + INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000", + INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000") + port map ( + DOA => memARead(19 downto 18), -- Port A 2-bit Data Output + DOB => memBRead(19 downto 18), -- Port B 2-bit Data Output + ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input + ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input + CLKA => clk, -- Port A Clock + CLKB => clk, -- Port B Clock + DIA => memAWrite(19 downto 18), -- Port A 2-bit Data Input + DIB => memBWrite(19 downto 18), -- Port B 2-bit Data Input + ENA => re, -- Port A RAM Enable Input + ENB => high, -- PortB RAM Enable Input + SSRA => low, -- Port A Synchronous Set/Reset Input + SSRB => low, -- Port B Synchronous Set/Reset Input + WEA => memAWriteEnable, -- Port A Write Enable Input + WEB => memBWriteEnable -- Port B Write Enable Input + ); + ZPU_RAM10 : RAMB16_S2_S2 + generic map ( + INIT_A => X"0", -- Value of output RAM registers on Port A at startup + INIT_B => X"0", -- Value of output RAM registers on Port B at startup + SRVAL_A => X"0", -- Port A ouput value upon SSR assertion + SRVAL_B => X"0", -- Port B ouput value upon SSR assertion + WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" + INIT_00 => X"00000000000200000042000800000003000A0000000A00000000038300200000", + INIT_01 => X"300AAAAAA020C232008800040000088008000000000000000000000800020000", + INIT_02 => X"AAA00002000008000000000000AAAAAAA8042AAAAAAA010AAAAAAA8020080088", + INIT_03 => X"AA800000008F00020208C0AA00000000023C000008F00000088CAAAAAAAA0AAA", + INIT_04 => X"0002830A0A000A0C282820323C2A800CAAAA00E2AAAAAA330000C88F02AA302A", + INIT_05 => X"8C0800000A0C2828002830A0A0002830A0A000A0C2828000A0C2828002830A0A", + INIT_06 => X"00300020200000C0A1000A0C000002088CA200005C130CB400003000030080C3", + INIT_07 => X"020002302E0320083088002282802C00880C88C83C880000C000083000800320", + INIT_08 => X"0322C80CE030C20033203A80C2CB0000E00022030A800C830F0A2321A0082000", + INIT_09 => X"020C00407253203845C00010EF0EF6002003008C60406000008C08C000200030", + INIT_0A => X"000003AAA80820008C020809000002318101802138028CC00E20000838403030", + INIT_0B => X"4202C0C108040C8010241C108090720804C0093413A20D00B042004C0C0000C0", + INIT_0C => X"802D008C8E130004D020800042893401283000252C01344D1008344020C13030", + INIT_0D => X"008A4000100000328380C228C82C20A028000000063200023000082C800000C0", + INIT_0E => X"02A8408800BCD830040300828028A0328C009022AA0000000EA0800030C08030", + INIT_0F => X"00A0000A0008280C031A0E8000000B8020C18000808C083C0A000C08C0A20800", + INIT_10 => X"000000808C9540880F24C0F0A0183C8000A2A0C78C78C68C90B000080080A800", + INIT_11 => X"0C100020230080883C080804208C8000A2A0C78C78C68C90B00008020822A882", + INIT_12 => X"880720A2880288820F00008800C0A800008070C0C0A8C0C140320BE030002868", + INIT_13 => X"A00C000080A0000C0A120C004000C000880028882000002E3028C0000C208C00", + INIT_14 => X"02A03008AA200022008010800C001222002A3008243000041C40D082300C0002", + INIT_15 => X"20808202003208CF6300308C0EA32823032C208220030202210210BA32028B30", + INIT_16 => X"08D080B10000B62300200C028200260C0080C20B80FF0000000030003800020C", + INIT_17 => X"C084080080080020322030C02A200B2401C0000880028000200AA000258210C8", + INIT_18 => X"82A22200A08000200A0A0820C2282A1A8CA0000800C90280080030A00B8C0000", + INIT_19 => X"7038030C21E023288C0238C80023663238A100000C2002080C000822021200A2", + INIT_1A => X"8C0C088083000C003020CD8C08382EA2083032C0008420000A3000C0C8000020", + INIT_1B => X"00F08C08A0A3022828C08A0A3022828C08A023022828C08A08280A2C0D0B6882", + INIT_1C => X"00C800000108003200820121208428084F63002088280880B000FC0A230B8800", + INIT_1D => X"088000002000300C8C0CB208838A0300000AA21072EA030B82C00F2EA2000820", + INIT_1E => X"802328022802E2A80C8AE0300F2320023A02C0294F080038C023003C03080E00", + INIT_1F => X"206003248E340008E002008C3C903C08020008E00380E000E30008A328021E00", + INIT_20 => X"ECAA3232802208C0C0808C386200BAA2C3C8E20012002B0B0281206003082300", + INIT_21 => X"00C82C04338C00893020230E2220EA32328022800A22AC00000AA020E00200AA", + INIT_22 => X"8BAA2AC8AB22EA8AAA3AAAABAEF12242EAEEFAAAEAEAB9EB858904893FB00C38", + INIT_23 => X"B62ADAAFAAAEA88604013AA2AD8AB62AA8AAA3AAAEA8AB6ECAA3AA299CAE72AC", + INIT_24 => X"FA8BABAAF8BEAEACBAC0AABBF88B3FAB8FC1804EA8AB706013AA2ADCAA22AD8A", + INIT_25 => X"00000C00000000000000003CC00000000000000000000000000000000B05893B", + INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_28 => X"00000000000000000000000000000000000000000002C0000000000000000000", + INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000", + INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000") + port map ( + DOA => memARead(21 downto 20), -- Port A 2-bit Data Output + DOB => memBRead(21 downto 20), -- Port B 2-bit Data Output + ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input + ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input + CLKA => clk, -- Port A Clock + CLKB => clk, -- Port B Clock + DIA => memAWrite(21 downto 20), -- Port A 2-bit Data Input + DIB => memBWrite(21 downto 20), -- Port B 2-bit Data Input + ENA => re, -- Port A RAM Enable Input + ENB => high, -- PortB RAM Enable Input + SSRA => low, -- Port A Synchronous Set/Reset Input + SSRB => low, -- Port B Synchronous Set/Reset Input + WEA => memAWriteEnable, -- Port A Write Enable Input + WEB => memBWriteEnable -- Port B Write Enable Input + ); + ZPU_RAM11 : RAMB16_S2_S2 + generic map ( + INIT_A => X"0", -- Value of output RAM registers on Port A at startup + INIT_B => X"0", -- Value of output RAM registers on Port B at startup + SRVAL_A => X"0", -- Port A ouput value upon SSR assertion + SRVAL_B => X"0", -- Port B ouput value upon SSR assertion + WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" + INIT_00 => X"010002800005000000C1008400000003002100000021040000000B0B00000080", + INIT_01 => X"300555555818C13E024600280002446044400000000000000000001400210008", + INIT_02 => X"5558001502C05488000000002055555554085555555502055555554490240A60", + INIT_03 => X"55400000005F20014925C05500000000017C800005F080001652555555554555", + INIT_04 => X"284143450521050D141494397C95402E555500D95555557B8000D65F09557015", + INIT_05 => X"4C06A011050D1414841434505284143450521050D1414A1050D1414841434505", + INIT_06 => X"08300810202228C05A80858C82220C544955A62AAEABAEBA2AA230A8232640C7", + INIT_07 => X"81820930112311843064801515403C98683C64CC3C642000820254B002222311", + INIT_08 => X"2319C42EE8BAC200709BF860C11608091088112325648C440F25531652041820", + INIT_09 => X"0AAA64A0B1AA88B6AE80A0F9CB0D89600123002ED080D0A1082E04C2601C8232", + INIT_0A => X"80B1F855540592024B086067802000BB42034297B9016AC008640821B6A83830", + INIT_0B => X"A590C3A6964A7A3129083A696430E8864AA6423AE830CEA4A9A084AA0C8048C8", + INIT_0C => X"402E609E6DA6824AA1855024A08AA99B160820AA6292A9AA6A4229A908A6A9E9", + INIT_0D => X"0155C680202440B64308D144C55D125014820820088920293200203C44080420", + INIT_0E => X"21158224204A263099232052441402364C257115550828288DD0801236C05232", + INIT_0F => X"025008204204448D20BD0F420204075350030300404C042C95208C84C8591480", + INIT_10 => X"120000824C6A82140F18C0B258202D42025358CF4CF4CF4C70F6080202425682", + INIT_11 => X"2D2E0814132042102D960C0C114C42025358CF4CF4CF4C70F608020811195469", + INIT_12 => X"140F1159658164C80B60264402C9144202E0B8C2CA74C2C6C0F140DA32001498", + INIT_13 => X"508C820240D8202CA5A58C268202C2024698164C8BB0201D3214C8120C114C82", + INIT_14 => X"41582246551A8099826834902C91209986B53201DC3018282FC8F041320C2024", + INIT_15 => X"14404302823121C09300314C2D531653231C1041590B25085301B0E5318547A2", + INIT_16 => X"812A614202024993081A8C9343921D0C01408167603C02062020808004200508", + INIT_17 => X"C048048048202080B140B8C815580B1803C9200648096080914544201F19B8C4", + INIT_18 => X"635309A05A60803045A50814A916352D4C51801602C6196216023258074C8000", + INIT_19 => X"B2642B997AD453154C2904C48011F864F8BA80800C1809048C988C8B81208071", + INIT_1A => X"4C2886A01F5A0808B007D24C040A0258047231C180889E2205320603C46A4810", + INIT_1B => X"80704C945513251544C945513251544C945513251544C9455031215D42809601", + INIT_1C => X"08C528201A2E02316950461B05582C08889300706A9690E6B2029C005E94E8C0", + INIT_1D => X"044202085020302C4C8C718442140B248247C1B0F4D18206C3C90B4D15080612", + INIT_1E => X"4813140150A9C5588C5692388F9310815542C81567040804C25309BC02058D20", + INIT_1F => X"80842348197820041901405C3C782C95012004188320C6849309555314016C2A", + INIT_20 => X"CC55313140158184C0404C219A25715003C510202846A50F6A46008423460610", + INIT_21 => X"08C41C890A4D24963010130841A215313140150A91905D2022045012D6015414", + INIT_22 => X"4050001400501400051411551455445144445554554505515511551140808CB4", + INIT_23 => X"0500154555414015155545000500140050004155414001414154500154015001", + INIT_24 => X"5545515054551554015400055445555541451551400051455450001400500140", + INIT_25 => X"00000C00000000000000003CC000000000000000000000000000000001151151", + INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_28 => X"0000000000000000000000000000000000000000000300000000000000000000", + INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000", + INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000") + port map ( + DOA => memARead(23 downto 22), -- Port A 2-bit Data Output + DOB => memBRead(23 downto 22), -- Port B 2-bit Data Output + ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input + ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input + CLKA => clk, -- Port A Clock + CLKB => clk, -- Port B Clock + DIA => memAWrite(23 downto 22), -- Port A 2-bit Data Input + DIB => memBWrite(23 downto 22), -- Port B 2-bit Data Input + ENA => re, -- Port A RAM Enable Input + ENB => high, -- PortB RAM Enable Input + SSRA => low, -- Port A Synchronous Set/Reset Input + SSRB => low, -- Port B Synchronous Set/Reset Input + WEA => memAWriteEnable, -- Port A Write Enable Input + WEB => memBWriteEnable -- Port B Write Enable Input + ); + ZPU_RAM12 : RAMB16_S2_S2 + generic map ( + INIT_A => X"0", -- Value of output RAM registers on Port A at startup + INIT_B => X"0", -- Value of output RAM registers on Port B at startup + SRVAL_A => X"0", -- Port A ouput value upon SSR assertion + SRVAL_B => X"0", -- Port B ouput value upon SSR assertion + WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" + INIT_00 => X"039A019A000D000B001200DA0007023A001E000F001E0FDA000F0BD9003C00CC", + INIT_01 => X"B69555554C5750DF077600150001D65619160003000B0003000B007E00620009", + INIT_02 => X"554C39042084105A00000001DD55555555D955555555769555555565615EB5BE", + INIT_03 => X"554AAC0000192000620183552AB000000064800001B8800A0819555555549555", + INIT_04 => X"686F8AA55961BE2A9565862064954A8855552A255555506A800A481B855060D5", + INIT_05 => X"0F947491BE2A956586F8AA559686F8AA55961BE2A9565A1BE2A956586F8AA559", + INIT_06 => X"55E4555D553130F9471D940D531356044986430CC330E31F333C3E346A848391", + INIT_07 => X"35D6B03E5162555DD551BE454D416A32594950D1695D6F969D55D0B050106257", + INIT_08 => X"6A55650674135555948D2557551899E1D319DC6686C599575286C34146735D6B", + INIT_09 => X"0B511375E55C5CCB20300054564209022543E5E74557415004E410F8141746E8", + INIT_0A => X"AE0A5E5545D396F84475FC1100639791155105719777D7445735D550CB8C5434", + INIT_0B => X"704D5111C1371164C4DA119C13584551371134971C79E5D3C571D371018C5BA1", + INIT_0C => X"994753E402D391371FF80D1371A5C46D51346795104DC671DD378774DE15C546", + INIT_0D => X"5B5A9011555CD497541A5760FB60D8541C4D34D354C86B843665D9495DD99522", + INIT_0E => X"64695D546782203E03646F924107E6D50F86A6360919C905A7E55556E49D9436", + INIT_0F => X"B8440DDE1D5511B9048D4B53755C343160951559A40F957A056F0D90D94114C7", + INIT_10 => X"D679D4140D155DD85255D5E851D14116B87360F80F80F00D0537757F43D40796", + INIT_11 => X"7410755803559DF9600C1C55540FD6387360F80F80F00D0534757C75D144000D", + INIT_12 => X"D8525415078455CE5804350557A1910638D530F845D0F840E5651B0C35474055", + INIT_13 => X"450D5D5551C06F8451150F8B46F8467840C8455CEC0766083640D5A775540D9D", + INIT_14 => X"C435C39600054001D41427915A29110183343D0001D5B8055FDAF500354C6B86", + INIT_15 => X"5E50155F46A5765083E7050F8583D043C3C4D34D43568A75400001C83704D943", + INIT_16 => X"092310E176738BC3E0850F1317C143755645556B5856754057556754DDD55B55", + INIT_17 => X"1D05D35D25D36BE56595F0D52318565417A1679C5AE171AE108065D5B81070DC", + INIT_18 => X"137710413751AC75D19455584241371D0D284586159535150C16284DD40D9740", + INIT_19 => X"68B51C594F5503C60F85C0DDBE728B201C6CDD960905D341AA04DCE847119D04", + INIT_1A => X"0F8C5FD0CDD555441033720F9048321F20C6655390C4D1167C355C5495C159F5", + INIT_1B => X"54650F25F943C97E50F25F943C97E50F25F943C97E50F25F99553100D20C86C8", + INIT_1C => X"B0D3CDD5C10D16651A0001CA4C27190C4C83E467FD85FC2686B8D90E8F841C1D", + INIT_1D => X"9B517557476727680F0FB03495F05689BECE30C59D995556D6A05DD991756036", + INIT_1E => X"9AC3CC76F058CBDDA96706F9BF837755E8D719DE3645D500F8C3E26C15549C6B", + INIT_1F => X"75776F40CEB46F9098761DF5694D6A1D776B9C198FF7418483E18F83EC767C15", + INIT_20 => X"CF6C3C3EC76E0CC7DD9D71515318703B9794416707741951E1AF35776F3A3327", + INIT_21 => X"1995184149CDC7DFA76748564D310C3C3CC76F45BAFA416F86F01755E5775604", + INIT_22 => X"C13000BC02E04C002D999D80225BDDC38B0652041E3E0C672F772F7700859A10", + INIT_23 => X"3900D6125104C0BE1369130006001000D000C25104C001872DE13009E407500B", + INIT_24 => X"9B24DA1D155701E2091800057049300F44449A44C003B116913000DC02D00F40", + INIT_25 => X"00000C00000000000000003F00000000000000003FFFFFFFEAAA954314EF7729", + INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_28 => X"00000000000000000000000000000000000000000002B0000000000000000000", + INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000", + INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000") + port map ( + DOA => memARead(25 downto 24), -- Port A 2-bit Data Output + DOB => memBRead(25 downto 24), -- Port B 2-bit Data Output + ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input + ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input + CLKA => clk, -- Port A Clock + CLKB => clk, -- Port B Clock + DIA => memAWrite(25 downto 24), -- Port A 2-bit Data Input + DIB => memBWrite(25 downto 24), -- Port B 2-bit Data Input + ENA => re, -- Port A RAM Enable Input + ENB => high, -- PortB RAM Enable Input + SSRA => low, -- Port A Synchronous Set/Reset Input + SSRB => low, -- Port B Synchronous Set/Reset Input + WEA => memAWriteEnable, -- Port A Write Enable Input + WEB => memBWriteEnable -- Port B Write Enable Input + ); + ZPU_RAM13 : RAMB16_S2_S2 + generic map ( + INIT_A => X"0", -- Value of output RAM registers on Port A at startup + INIT_B => X"0", -- Value of output RAM registers on Port B at startup + SRVAL_A => X"0", -- Port A ouput value upon SSR assertion + SRVAL_B => X"0", -- Port B ouput value upon SSR assertion + WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" + INIT_00 => X"048000800000000200D00184000A017000000002000011200002000000180188", + INIT_01 => X"7C5555555854138606440000000108641104000E0006000A0002005000C00000", + INIT_02 => X"5558042D08A0B41A00000001AD555555549155555555E41555555541A0206648", + INIT_03 => X"55715C000240F00919240F55C57000000903C000243480300640555555555555", + INIT_04 => X"405C8182114172060845114903D571635555C5955555590C80300643455903D5", + INIT_05 => X"5B801D017206084505C818211405C8182114172060845017206084505C818211", + INIT_06 => X"CF9158A961AC95B82D05825991BD5A818146BA784E178E05EE196D1F5140921C", + INIT_07 => X"B005756E115DA14862955E25811175003146959146905384061691264ACA55A0", + INIT_08 => X"59A42C80120D1614043907018A5255D15255DD5D458556865145564855BB005F", + INIT_09 => X"01CCB2259A0B2392C28EB25C2C44439D7556E1C065846DC42FC145B4B017F5D4", + INIT_0A => X"5D045055085455F440192D596B5B87059615B7094314F0445810596FD2990D67", + INIT_0B => X"2AFAD9C0AB629CBFAFADDC0ABEB572DBE2CBEB0208A280BA712A3A2C017F5451", + INIT_0C => X"11556380E4B31F22CC8459F22A00B2C9AD2F53440AC8B22C8BAA332CA8CCB170", + INIT_0D => X"20521D116161320750D75445BA63043113F3CF3C5A8353456600614680580100", + INIT_0E => X"61C0465D5B55056D2C59536A410615565B4484160756D1354445850590451166", + INIT_0F => X"34540464C6282165840F2FC01644185361165611845B8175155F598598574301", + INIT_10 => X"95B81610590006D555A145D454614515B44D55B85B05B059451518414910F155", + INIT_11 => X"754218A4566586A15676D758A25B95745945B85B05B05945151841195403B8C5", + INIT_12 => X"D551A2D57526556851549CC515512185746555B44C55B454651AD2896651552D", + INIT_13 => X"8559861581715344E5155B4405F4557449226556808162B96615991018A25946", + INIT_14 => X"26810900EE302D971042C7156514441D7E116C47006114D165575485665C5744", + INIT_15 => X"A0C05611F51A011016E3015B4416DC56D6D50410605144194847857167575649", + INIT_16 => X"8501D75816390056D02C5B13154B001851558A06B000164401658184C0614458", + INIT_17 => X"0574554574665B151AA515999DD755A194515B8256D1855D195248612057559C", + INIT_18 => X"294541ADD1C95F545C0658A6DD729444592D35B5D46841BCF6D5145056598440", + INIT_19 => X"149C18D3853DD6ED5B46C5954E2306988017058001305075452D168064440507", + INIT_1A => X"5B45DE3E255C5866C889405B844000F7C4859A19500318D5F56654D4686755D5", + INIT_1B => X"94C55B661556D98555B661556D98555B661556D98555B6615966998090003DF1", + INIT_1C => X"3592E46160BFE5DAB10482E8425701001416E005E33F6F15057471E127141505", + INIT_1D => X"80C9165B516301415B5B0701161251457D340D55D4531628D7525D4509184AA5", + INIT_1E => X"16D6E0146835CA997694559D7456518A815556F59C405905B416D01856291657", + INIT_1F => X"8587514864C4538C5A1605E146B57504145784994C01A31416D14956D0141E0C", + INIT_20 => X"CD516D6D0145C6464505A965E90EB3E9566B0C5F1536A2596A25058759A61921", + INIT_21 => X"5468563D4019C7D5514156594E90616D6E0146C37529415345B4115925148658", + INIT_22 => X"01C0003000C07000268DD053D75C7D13203354162007003471F473F46485451C", + INIT_23 => X"020009137507003F200E1C000C003400D00003750700030D29C1C00BC00F0003", + INIT_24 => X"CC244C4D1D8522020A340015444E300FD448038700000200E1C0000002D00080", + INIT_25 => X"00000C00000000000000003F2AAAAAAAAAAAAAAA95555555555555541931F475", + INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_28 => X"0000000000000000000000000000000000000000000300000000000000000000", + INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000", + INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000") + port map ( + DOA => memARead(27 downto 26), -- Port A 2-bit Data Output + DOB => memBRead(27 downto 26), -- Port B 2-bit Data Output + ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input + ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input + CLKA => clk, -- Port A Clock + CLKB => clk, -- Port B Clock + DIA => memAWrite(27 downto 26), -- Port A 2-bit Data Input + DIB => memBWrite(27 downto 26), -- Port B 2-bit Data Input + ENA => re, -- Port A RAM Enable Input + ENB => high, -- PortB RAM Enable Input + SSRA => low, -- Port A Synchronous Set/Reset Input + SSRB => low, -- Port B Synchronous Set/Reset Input + WEA => memAWriteEnable, -- Port A Write Enable Input + WEB => memBWriteEnable -- Port B Write Enable Input + ); + ZPU_RAM14 : RAMB16_S2_S2 + generic map ( + INIT_A => X"0", -- Value of output RAM registers on Port A at startup + INIT_B => X"0", -- Value of output RAM registers on Port B at startup + SRVAL_A => X"0", -- Port A ouput value upon SSR assertion + SRVAL_B => X"0", -- Port B ouput value upon SSR assertion + WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" + INIT_00 => X"000A000A00020008000A0002000400B2000A0008000A008A000C000A00100010", + INIT_01 => X"3C00000002000B2100020000000000020882000C000800000004000A00060002", + INIT_02 => X"0002800A00C02800AAAAAAA80400000003080000000042000000000008082020", + INIT_03 => X"00300EAAA808FAA00C008F00C03AAAAAA023EAAA80B02AB22008000000000000", + INIT_04 => X"2A0C2828002830A0A000802023C0303B0000C0000000002E2AB2200B000023C0", + INIT_05 => X"0302A00830A0A000A0C2828002A0C2828002830A0A000A830A0A000A0C282800", + INIT_06 => X"322C0000000F2030098C00000AC20218800000408020003A00A00C9008220000", + INIT_07 => X"3000B00C08080028C0002C008CC030B82000000000000B0A0C00001031310403", + INIT_08 => X"080003203C800000000302230088C3CB2C00CF0420E030020020000200F3000F", + INIT_09 => X"0284200000013410000200FB000402024000C082C002C087A08260320D0F0002", + INIT_0A => X"1C88F20068CB00320032CA23C00F020B000B0203C230201A00B0C00610320001", + INIT_0B => X"00830340024034CA0830340020C0D302C0420C0001C30028D0036C04002D0108", + INIT_0C => X"CC390F8224230200473B002007401083A38D0B0080801204828C120B304810D1", + INIT_0D => X"2B020380000CCE810202820030002ACC0B082082000003200008C80000C02802", + INIT_0E => X"004C8C800F22000C8E0E072BB02AA0A003228022B000F80018400000228C0000", + INIT_0F => X"7202A8CC8C002008E004CD363022A22F0A808008200300308807000000200D83", + INIT_10 => X"4070A00200000C00000240C208C0188072012030030030004022302201020A80", + INIT_11 => X"3802300200028CA00A8A040000030032012030030030004022302232C0A80B28", + INIT_12 => X"000000000880004802201A200008A820F24020320800321260002A2000232800", + INIT_13 => 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X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000") + port map ( + DOA => memARead(29 downto 28), -- Port A 2-bit Data Output + DOB => memBRead(29 downto 28), -- Port B 2-bit Data Output + ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input + ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input + CLKA => clk, -- Port A Clock + CLKB => clk, -- Port B Clock + DIA => memAWrite(29 downto 28), -- Port A 2-bit Data Input + DIB => memBWrite(29 downto 28), -- Port B 2-bit Data Input + ENA => re, -- Port A RAM Enable Input + ENB => high, -- PortB RAM Enable Input + SSRA => low, -- Port A Synchronous Set/Reset Input + SSRB => low, -- Port B Synchronous Set/Reset Input + WEA => memAWriteEnable, -- Port A Write Enable Input + WEB => memBWriteEnable -- Port B Write Enable Input + ); + ZPU_RAM15 : RAMB16_S2_S2 + generic map ( + INIT_A => X"0", -- Value of output RAM registers on Port A at startup + INIT_B => X"0", -- Value of output RAM registers on Port B at startup + SRVAL_A => X"0", -- Port A ouput value upon SSR assertion + SRVAL_B => X"0", -- Port B ouput value upon SSR assertion + WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE + SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" + INIT_00 => X"012501250005000C00850021000C04790015000800150445000C06A500A20022", + INIT_01 => X"3E0000000102861A0021001A000062014461000800080008000C000500090005", + INIT_02 => X"00016181A9A606405555555408000000020400000000C1800000002406860012", + INIT_03 => X"00380D555416F5504C816F00E0355555505BD555417215799015000000000000", + INIT_04 => X"150D141484143450521044505BC038370000E0000000005D1579901720005BC0", + INIT_05 => X"232560943450521050D141484150D1414841434505210543450521050D141484", + INIT_06 => X"00220200080CA232424C242006C10156652140C2A0A8208A00A08C600C152802", + INIT_07 => X"7960B48C94080954C8002C90603830464420020820060B290C804A2B0A8A0808", + INIT_08 => X"0801A099B260808262038663204603C45802DC0C111020210811482500B7960F", + INIT_09 => X"B21A08408092A834489A08F2B02D6019E008C8D9C021C81E70D9D231028F00C1", + INIT_0A => X"3C65F50054C400B126310D53AA0B236700872053A93255150278C00D7442A482", + INIT_0B => X"40229BA900843AA20229BA9008A6EA90C4A08A6493A69908EA4E884AE83E0304", + INIT_0C => X"083213991D0B0084AC3620084E992813008A0B666021294A508A694329A528EA", + INIT_0D => X"941900480802026609C30522351855428704104100200F1080A4C42028C29489", + INIT_0E => X"09924C500B55848C49080F5E48945081231541904403C48021D020A0854C8880", + INIT_0F => X"F11354CE4C829821D2282A093015515E4540408412232430540F202202542263", + INIT_10 => X"C0B252C920AA8C820809A0C114C82140F11A123A23A23A20A08132192B490540", + INIT_11 => X"31A9320188014C4821458A02082340F11A123A23A23A20A08132193189540F14", + INIT_12 => X"82080840056000820852B53082055430F180823121423135908045108013168C", + INIT_13 => X"50204C8060860B121484231580B130B12056000826630914809200493208204C", + INIT_14 => X"60147B5503C56A444956B3C8304DAD4164688CA9A8C840D832822238801B0B15", + INIT_15 => X"050A408700809D8A08CB58231148D108C8D65965050811315FBC68B48264017B", + INIT_16 => X"3987081A30B361C8C641238A42DC6932092020630669301593001321D4C82502", + INIT_17 => X"8CF4CF4CF4C70F60802082005016080982040F2403C4582C4D2424C852942208", + INIT_18 => X"5A12D4581F1C3F2241500201C105A1AA20896085820254018580C114C4202535", + INIT_19 => X"81709601658808D02311D2042C992E2EAE684C29A084C9682040482661AD4CA0", + INIT_1A => X"231F1CC0888102070A2228232621A807D66080894AE65C90B4801182024003D0", + INIT_1B => X"060023511408D445023511408D445023511408D4450235114405D4AA486A01F5", + INIT_1C => X"F208D4C846C8108005EA29C4245760AE6A08CA81CC005E9120F1C00A4B12968C", + INIT_1D => X"26093003130B531623235855404608102D249870C644408183040C6451321180", + INIT_1E => X"42C8D6310685E5402010908C22081320554202D55024C0523108C58D80818C0F", + INIT_1F => X"1013086689640B2442308CC820343062310B24402E93142648C56148D6315DA1", + INIT_20 => X"ED148C8D631068854C4C500542A579414301690F86B5240C527110130841A213", + INIT_21 => X"82028B29217CE3C1531314016C2A548C8D6310685441680F10F6131181315052", + INIT_22 => X"4150005401505400051555515555155155055515155504555455555540A03041", + INIT_23 => X"1100451145454055115515000500140050004145454001414151500144051005", + INIT_24 => X"5544555515551154011400155405100554441545400111055150004400500440", + INIT_25 => X"00000C00000000000000003F0000000000000000000000000000000015545555", + INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_28 => X"0000000000000000000000000000000000000000000300000000000000000000", + INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000", + INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000") + port map ( + DOA => memARead(31 downto 30), -- Port A 2-bit Data Output + DOB => memBRead(31 downto 30), -- Port B 2-bit Data Output + ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input + ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input + CLKA => clk, -- Port A Clock + CLKB => clk, -- Port B Clock + DIA => memAWrite(31 downto 30), -- Port A 2-bit Data Input + DIB => memBWrite(31 downto 30), -- Port B 2-bit Data Input + ENA => re, -- Port A RAM Enable Input + ENB => high, -- PortB RAM Enable Input + SSRA => low, -- Port A Synchronous Set/Reset Input + SSRB => low, -- Port B Synchronous Set/Reset Input + WEA => memAWriteEnable, -- Port A Write Enable Input + WEB => memBWriteEnable -- Port B Write Enable Input + ); +end dualport_ram_arch; diff --git a/zpu/hdl/zpu3/src/xmake.filelist b/zpu/hdl/zpu3/src/xmake.filelist new file mode 100644 index 0000000..3d0a779 --- /dev/null +++ b/zpu/hdl/zpu3/src/xmake.filelist @@ -0,0 +1,5 @@ +vhdl zylin "zpu_config.vhd" +vhdl zylin "zpupkg.vhd" +vhdl work "dmips_ram.vhd" +vhdl zylin "zpu_top_bram_intstack.vhd" +vhdl work "testlut.vhd" diff --git a/zpu/hdl/zpu3/src/xmake.xst b/zpu/hdl/zpu3/src/xmake.xst new file mode 100644 index 0000000..bfdb23f --- /dev/null +++ b/zpu/hdl/zpu3/src/xmake.xst @@ -0,0 +1,53 @@ +set -tmpdir ../tmp +set -xsthdpdir ../xst +run +-ifn xmake.filelist +-ifmt mixed +-ofn ../syn/ic300 +-ofmt NGC +-p xc3s400-4-ft256 +-top ic300 +-opt_mode Area +-opt_level 2 +-iuc NO +-lso ic300.lso +-keep_hierarchy NO +-glob_opt AllClockNets +-rtlview Yes +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-rom_style Auto +-mux_extract YES +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-resource_sharing YES +-mult_style auto +-iobuf YES +-max_fanout 500 +-bufg 8 +-register_duplication YES +-equivalent_register_removal NO +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-use_clock_enable Yes +-use_sync_set No +-use_sync_reset No +-iob true +-slice_utilization_ratio_maxmargin 5 diff --git a/zpu/hdl/zpu3/src/zpu_config.vhd b/zpu/hdl/zpu3/src/zpu_config.vhd new file mode 100644 index 0000000..506121c --- /dev/null +++ b/zpu/hdl/zpu3/src/zpu_config.vhd @@ -0,0 +1,25 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +package zpu_config is + + constant Generate_Trace : boolean := false; + -- during simulation, set this to '0' to get matching trace.txt + constant DontCareValue : std_logic := '0'; + -- Clock frequency in MHz. + constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64"; + -- maximum address includes upper bit for IO registers + -- the rest is RAM + constant maxAddrBit : integer := 14; + constant minAddrBit : integer := 2; + -- This bit is set for read/writes to IO + -- FIX!!! eventually this should be set to wordSize-1 so as to + -- to make the address of IO independent of amount of memory + -- reserved for CPU. Requires trivial tweaks in toolchain/runtime + -- libraries. + constant ioBit : integer := maxAddrBit+1; + constant wordPower : integer := 5; + constant wordSize : integer := 2**wordPower; + +end zpu_config; diff --git a/zpu/hdl/zpu3/src/zpu_pipelined.vhd b/zpu/hdl/zpu3/src/zpu_pipelined.vhd new file mode 100644 index 0000000..207939d --- /dev/null +++ b/zpu/hdl/zpu3/src/zpu_pipelined.vhd @@ -0,0 +1,852 @@ +-- Company: ZPU3 +-- Engineer: Øyvind Harboe + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.STD_LOGIC_arith.ALL; + +library zylin; +use zylin.zpu_config.all; +use zylin.zpupkg.all; + + +entity zpu_top is + Port ( clk : in std_logic; + areset : in std_logic; + io_busy : in std_logic; + io_read : in std_logic_vector(7 downto 0); + io_write : out std_logic_vector(7 downto 0); + io_addr : out std_logic_vector(maxAddrBit downto minAddrBit); + io_writeEnable : out std_logic; + io_readEnable : out std_logic; + interrupt : in std_logic; + break : out std_logic); +end zpu_top; + +architecture behave of zpu_top is + +signal readIO : std_logic; + + + +signal memAWriteEnable : std_logic; +signal memAAddr : std_logic_vector(maxAddrBit downto minAddrBit); +signal memAWrite : std_logic_vector(wordSize-1 downto 0); +signal memARead : std_logic_vector(wordSize-1 downto 0); +signal memBWriteEnable : std_logic; +signal memBAddr : std_logic_vector(maxAddrBit downto minAddrBit); +signal memBWrite : std_logic_vector(wordSize-1 downto 0); +signal memBRead : std_logic_vector(wordSize-1 downto 0); + + +signal busy : std_logic; + +signal begin_inst : std_logic; + + + +signal trace_opcode : std_logic_vector(7 downto 0); +signal trace_pc : std_logic_vector(maxAddrBit downto 0); +signal trace_sp : std_logic_vector(maxAddrBit downto minAddrBit); +signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); +signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); + +type DecodedOpcodeType is +( +Decoded_Stall , +Decoded_Nop , +Decoded_Im , +Decoded_ImShift , +Decoded_LoadSP , +Decoded_StoreSP , +Decoded_AddSP , +Decoded_Emulate , +Decoded_Break , +Decoded_PushPC , +Decoded_PushSP , +Decoded_PopPC , +Decoded_Add , +Decoded_Or , +Decoded_And , +Decoded_Load , +Decoded_Not , +Decoded_Flip , +Decoded_Store , +Decoded_Storeb , +Decoded_PopSP , +Decoded_Ashiftleft , +Decoded_Ashiftright , +Decoded_Lshiftright , +Decoded_Eqbranch , +Decoded_Neqbranch , +Decoded_Eq , +Decoded_Neq , +Decoded_Loadb , +Decoded_Lessthan , +Decoded_Lessthanorequal , +Decoded_Ulessthan , +Decoded_Ulessthanorequal , +Decoded_Duplicate , +Decoded_Duplicate2 , +Decoded_Duplicate3 , +Decoded_MoveDown, +Decoded_MoveDown2, +Decoded_MoveDown3, +Decoded_Pushspadd, +Decoded_Callpcrel, +Decoded_Sub +); + + +signal decode_pc : std_logic_vector(maxAddrBit downto 0); +signal decode_fetchedPC : std_logic_vector(maxAddrBit downto 0); +signal decode_fetched : std_logic; +signal decode_opcode : std_logic_vector(OpCode_Size-1 downto 0); +signal decode_opcodeWord : std_logic_vector(wordSize-1 downto 0); +signal decode_starved : std_logic; +signal decode_wordStarved : std_logic; +signal decode_willBeStarved : std_logic; +signal decode_idim_flag : std_logic; + +signal execute1_stall : std_logic; +signal execute1_fetched : std_logic; +signal execute1_decodedOpcode : DecodedOpcodeType; +signal execute1_fetchedPC : std_logic_vector(maxAddrBit downto 0); +signal execute1_sp : std_logic_vector(maxAddrBit downto minAddrBit); +signal execute1_opcode : std_logic_vector(opCode_Size-1 downto 0); +signal execute1_spOffset : std_logic_vector(4 downto 0); +signal execute1_fetchPC : std_logic_vector(maxAddrBit downto 0); +signal execute1_push1 : std_logic; +signal execute1_push2 : std_logic; +signal execute1_pop1 : std_logic; +signal execute1_pop2 : std_logic; +signal execute1_antialias : std_logic; +signal execute1_savedTopOfStack : std_logic_vector(wordSize-1 downto 0); + + +signal load_decodedOpcode : DecodedOpcodeType; +signal load_opcode : std_logic_vector(opCode_Size-1 downto 0); +signal load_spOffset : std_logic_vector(4 downto 0); +signal load_stall : std_logic; +signal load_willBeStalled : std_logic; + +signal execute2_opcode : std_logic_vector(opCode_Size-1 downto 0); +signal execute2_topOfStack : std_logic_vector(wordSize-1 downto 0); +signal execute2_addResult : std_logic_vector(wordSize-1 downto 0); +signal execute2_topOfStackB : std_logic_vector(wordSize-1 downto 0); +signal execute2_pc : std_logic_vector(maxAddrBit downto 0); +signal execute2_sp : std_logic_vector(maxAddrBit downto minAddrBit); +signal execute2_loading : std_logic; +signal execute2_loadByte : std_logic; +signal execute2_storeByte : std_logic; +signal execute2_loadingDone : std_logic; +signal execute2_decodedOpcode : DecodedOpcodeType; +signal execute2_spOffset : std_logic_vector(4 downto 0); +signal execute2_persistTopOfStack : std_logic; +signal execute2_persistTopOfStackB : std_logic; +signal execute2_resync : std_logic; +signal execute2_resync2 : std_logic; +signal execute2_resync3 : std_logic; +signal execute2_resync4 : std_logic; +signal execute2_resync5 : std_logic; +signal execute2_resync6 : std_logic; +signal execute2_resync7 : std_logic; +signal execute2_resync8 : std_logic; +signal execute2_resync9 : std_logic; +signal execute2_resync10 : std_logic; + + +begin + traceFileGenerate: + if Generate_Trace generate + trace_file: trace port map ( + clk => clk, + begin_inst => begin_inst, + pc => trace_pc, + opcode => trace_opcode, + sp => trace_sp, + memA => trace_topOfStack, + memB => trace_topOfStackB, + busy => busy + ); + end generate; + + + memory: dualport_ram port map ( + clk => clk, + memAWriteEnable => memAWriteEnable, + memAAddr => memAAddr, + memAWrite => memAWrite, + memARead => memARead, + memBWriteEnable => memBWriteEnable, + memBAddr => memBAddr, + memBWrite => memBWrite, + memBRead => memBRead + ); + + opcodeControl: + process(clk, areset) + variable compareA : signed(wordSize-1 downto 0); + variable compareB : signed(wordSize-1 downto 0); + variable execute1_doFetch : boolean; + begin + if areset = '1' then + break <= '0'; + begin_inst <= '0'; + memAAddr <= (others => '0'); + memBAddr <= (others => '0'); + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + memAWrite <= (others => '0'); + memBWrite <= (others => '0'); + + memBAddr <= (others => '0'); + memBWrite <= (others => '0'); + + + io_writeEnable <= '0'; + io_readEnable <= '0'; + io_addr <= (others => '0'); + io_write <= (others => '0'); + + -- stage 1. Don't care since this is driven by stage2 + decode_pc <= (others => '0'); + decode_fetched <= '0'; + decode_starved <= '0'; + decode_opcode <= (others => '0'); + decode_opcodeWord <= (others => '0'); + + -- stage 2. + execute1_antialias <= '0'; + execute1_fetchPC <= (others => '0'); + execute1_fetched <= '0'; + execute1_decodedOpcode <= Decoded_Stall; + execute1_sp <= (2 => '0', others => '1'); + execute1_push1 <= '0'; + execute1_push2 <= '0'; + execute1_pop1 <= '0'; + execute1_pop2 <= '0'; + execute1_stall <= '1'; + + -- stage 3 + load_decodedOpcode <= Decoded_Stall; + load_stall <= '1'; + load_willBeStalled <= '1'; + + -- stage 4 + decode_idim_flag <= '0'; + execute2_pc <= (others => '0'); + execute2_sp <= (2 => '0', others => '1'); + execute2_loading <= '0'; + execute2_loadByte <= '0'; + execute2_storeByte <= '0'; + execute2_loadingDone <= '0'; + execute2_decodedOpcode <= Decoded_Stall; + execute2_resync <= '1'; + execute2_resync2 <= '0'; + execute2_resync3 <= '0'; + execute2_resync4 <= '0'; + execute2_resync5 <= '0'; + execute2_resync6 <= '0'; + execute2_resync7 <= '0'; + execute2_resync8 <= '0'; + execute2_resync9 <= '0'; + execute2_resync10 <= '0'; + execute2_persistTopOfStack <= '0'; + execute2_persistTopOfStackB <= '0'; + + -- stage 5 + memBWriteEnable <= '0'; + + + elsif (clk'event and clk = '1') then + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + io_writeEnable <= '0'; + io_readEnable <= '0'; + begin_inst <= '0'; + + -- stage0: fetch + decode_willBeStarved <= '0'; + if (decode_fetched='1') then + -- resync #4 + decode_opcodeWord <= memARead; + decode_pc <= decode_fetchedPC; + elsif (decode_pc(minAddrBit-1 downto 0)=b"11") then + decode_willBeStarved <= '1'; + else + -- we can continue decoding. + decode_pc <= decode_pc + 1; + end if; + + -- stage 0b: move to byte.. + -- resync #5 + decode_starved <= decode_willBeStarved; + case decode_pc(minAddrBit-1 downto 0) is + when "00" => decode_opcode <= decode_opcodeWord(31 downto 24); + when "01" => decode_opcode <= decode_opcodeWord(23 downto 16); + when "10" => decode_opcode <= decode_opcodeWord(15 downto 8); + when others => decode_opcode <= decode_opcodeWord(7 downto 0); + end case; + + -- stage1: decode 1 + execute1_opcode <= decode_opcode; + + execute1_spOffset(4)<=not decode_opcode(4); + execute1_spOffset(3 downto 0)<=decode_opcode(3 downto 0); + + execute1_decodedOpcode<=Decoded_Break; + + decode_idim_flag <= '0'; + + -- resync #6 + -- resync #1 + if (decode_starved = '1') then + execute1_decodedOpcode<=Decoded_Stall; + decode_idim_flag <= decode_idim_flag; + elsif (decode_opcode(7 downto 7)=OpCode_Im) then + decode_idim_flag <= '1'; + if (decode_idim_flag = '0') then + execute1_decodedOpcode<=Decoded_Im; + else + execute1_decodedOpcode<=Decoded_ImShift; + end if; + elsif (decode_opcode(7 downto 5)=OpCode_StoreSP) then + if (decode_opcode(4 downto 0)=b"10001") then + execute1_decodedOpcode<=Decoded_MoveDown; + elsif (decode_opcode(4 downto 0)=b"10010") then + execute1_decodedOpcode<=Decoded_MoveDown2; +-- elsif (decode_opcode(4 downto 0)=b"10011") then +-- execute1_decodedOpcode<=Decoded_MoveDown3; + else + execute1_decodedOpcode<=Decoded_StoreSP; + end if; + elsif (decode_opcode(7 downto 5)=OpCode_LoadSP) then + if (decode_opcode(4 downto 0)=b"10000") then + execute1_decodedOpcode<=Decoded_Duplicate; + elsif (decode_opcode(4 downto 0)=b"10001") then + execute1_decodedOpcode<=Decoded_Duplicate2; + elsif (decode_opcode(4 downto 0)=b"10010") then + execute1_decodedOpcode<=Decoded_Duplicate3; + else + execute1_decodedOpcode<=Decoded_LoadSP; + end if; + elsif (decode_opcode(7 downto 5)=OpCode_Emulate) then + execute1_decodedOpcode<=Decoded_Emulate; + if decode_opcode(5 downto 0)=OpCode_Neqbranch then + execute1_decodedOpcode <= Decoded_Neqbranch; + elsif decode_opcode(5 downto 0)=OpCode_Eq then + execute1_decodedOpcode <= Decoded_Eq; + elsif decode_opcode(5 downto 0)=OpCode_Lessthan then + execute1_decodedOpcode <= Decoded_Lessthan; + elsif decode_opcode(5 downto 0)=OpCode_Ulessthan then + execute1_decodedOpcode <= Decoded_Ulessthan; + elsif decode_opcode(5 downto 0)=OpCode_Loadb then + execute1_decodedOpcode <= Decoded_Loadb; + elsif decode_opcode(5 downto 0)=OpCode_Storeb then + execute1_decodedOpcode <= Decoded_Storeb; + elsif decode_opcode(5 downto 0)=OpCode_Pushspadd then + execute1_decodedOpcode <= Decoded_Pushspadd; + elsif decode_opcode(5 downto 0)=OpCode_Callpcrel then + execute1_decodedOpcode <= Decoded_Callpcrel; + elsif decode_opcode(5 downto 0)=OpCode_Sub then + execute1_decodedOpcode <= Decoded_Sub; + end if; + elsif (decode_opcode(7 downto 4)=OpCode_AddSP) then + if (decode_opcode(3 downto 0) = 0) then + execute1_decodedOpcode<=Decoded_Ashiftleft; + elsif (decode_opcode(3 downto 0) = 1) then +-- execute1_decodedOpcode<=Decoded_AddSP; + elsif (decode_opcode(3 downto 0) = 2) then +-- execute1_decodedOpcode<=Decoded_AddSP; + else + execute1_decodedOpcode<=Decoded_AddSP; + end if; + else + case decode_opcode(3 downto 0) is + when OpCode_Nop => + execute1_decodedOpcode<=Decoded_Nop; + when OpCode_PushSP => + execute1_decodedOpcode<=Decoded_PushSP; + when OpCode_PopPC => + execute1_decodedOpcode<=Decoded_PopPC; + when OpCode_Add => + execute1_decodedOpcode<=Decoded_Add; + when OpCode_Or => + execute1_decodedOpcode<=Decoded_Or; + when OpCode_And => + execute1_decodedOpcode<=Decoded_And; + when OpCode_Load => + execute1_decodedOpcode<=Decoded_Load; + when OpCode_Not => + execute1_decodedOpcode<=Decoded_Not; + when OpCode_Flip => + execute1_decodedOpcode<=Decoded_Flip; + when OpCode_Store => + execute1_decodedOpcode<=Decoded_Store; + when OpCode_PopSP => + execute1_decodedOpcode<=Decoded_PopSP; + when others => + execute1_decodedOpcode<=Decoded_Break; + end case; + end if; + + + -- stage 2: execute 1 - load stage. + -- + -- the address must be known without using the value on top of the stack... + -- resync #3 + execute1_fetched <= '0'; + decode_fetched <= execute1_fetched; -- the value in memAAddr will be valid for 1 cycle only + decode_fetchedPC <= execute1_fetchedPC; + + if (execute1_fetchPC(1 downto 0)/=b"00") then + execute1_fetchPC <= execute1_fetchPC+1; + end if; + + execute1_push1 <= '0'; + execute1_push2 <= execute1_push1; + execute1_pop1 <= '0'; + execute1_pop2 <= execute1_pop1; + + if ((execute1_push1 and execute1_push2)='1') then + memAWrite <= execute2_topOfStack; + else + memAWrite <= execute2_topOfStackB; + end if; + + -- resync #7 + case execute1_decodedOpcode is + when Decoded_Neqbranch | Decoded_MoveDown3 | Decoded_Load | Decoded_Loadb | Decoded_Store | Decoded_Storeb | Decoded_Emulate | Decoded_PopSP | Decoded_PopPC| Decoded_Callpcrel => + execute1_stall <= '1'; + when others => + -- nothing... + end case; + + execute1_antialias <= load_stall; + execute1_doFetch := false; + case execute1_decodedOpcode is + when Decoded_PushSP | Decoded_Emulate => + execute1_sp <= execute1_sp - 1; + execute1_push1 <= '1'; + execute1_doFetch := true; + when Decoded_Duplicate3 => + memAWriteEnable <= ((execute1_push1 and execute1_push2) or + (execute1_push1 and not execute1_pop2) or + (execute1_push2 and not execute1_pop1)) and + (not execute1_antialias and not execute1_stall); + memAAddr <= execute1_sp + 2; + execute1_sp <= execute1_sp - 1; + execute1_push1 <= '1'; + when Decoded_Im | Decoded_Duplicate | Decoded_Duplicate2 => + execute1_sp <= execute1_sp - 1; + execute1_push1 <= '1'; + execute1_doFetch := true; + when Decoded_LoadSP => + memAAddr <= execute1_sp+execute1_spOffset; + execute1_sp <= execute1_sp - 1; + execute1_push1 <= '1'; + when Decoded_AddSP => + memAAddr <= execute1_sp+execute1_spOffset; + when Decoded_MoveDown2 => + execute1_sp <= execute1_sp + 1; + execute1_pop1 <= '1'; + execute1_doFetch := true; + when Decoded_Ulessthan | Decoded_Lessthan | Decoded_Eq | Decoded_Neqbranch | Decoded_MoveDown3 | Decoded_MoveDown | Decoded_Add | Decoded_Sub | Decoded_Or | Decoded_And | Decoded_PopPC | Decoded_StoreSP => + -- be afraid :-) + memAWriteEnable <= ((execute1_push1 and execute1_push2) or + (execute1_push1 and not execute1_pop2) or + (execute1_push2 and not execute1_pop1)) and + (not execute1_antialias and not execute1_stall); + memAAddr <= execute1_sp + 2; + execute1_sp <= execute1_sp + 1; + execute1_pop1 <= '1'; + when others => + execute1_doFetch := true; + end case; + + if execute1_doFetch then + -- resync #2 + -- some instruction that does not change the stack pointer + -- and does not need use a memory operand. + -- We can fetch the next word to be decoded to avoid stalls + execute1_fetchPC <= execute1_fetchPC+1; + memAAddr <= execute1_fetchPC(maxAddrBit downto minAddrBit); + execute1_fetchedPC <= execute1_fetchPC; + execute1_fetched <= '1'; + end if; + + + -- stage 3: fetching memory takes 1 cycle + -- here we also verify that we've fetched & decoded the right + -- opcode. + -- resync #8 + load_decodedOpcode <= execute1_decodedOpcode; + load_opcode <= execute1_opcode; + load_spOffset <= execute1_spOffset; + load_stall <= execute1_stall; + -- resync #9 + if (load_stall = '1') then + execute2_decodedOpcode <= Decoded_Stall; + else + execute2_decodedOpcode <= load_decodedOpcode; + end if; + execute2_opcode <= load_opcode; + execute2_spOffset <= load_spOffset; + + -- stage 4: execute 2 - we now have both operands. This is the + -- main execute stage... + begin_inst <= '1'; + trace_pc <= execute2_pc; + trace_opcode <= execute2_opcode; + trace_sp <= execute2_sp; + trace_topOfStack <= execute2_topOfStack; + trace_topOfStackB <= execute2_topOfStackB; + + execute2_pc <= execute2_pc + 1; + execute2_loading <= '0'; + memBWriteEnable <= '0'; + + case execute2_decodedOpcode is + when Decoded_PopSP => + execute2_sp <= execute2_topOfStack(maxAddrBit downto minAddrBit); + + memBWriteEnable <= '1'; + memBAddr <= execute2_sp + 1; + memBWrite <= execute2_topOfStackB; + execute2_resync <= '1'; + when Decoded_Callpcrel => + execute2_topOfStack <= (others => DontCareValue); + execute2_topOfStack(maxAddrBit downto 0) <= execute2_pc + 1; + execute2_pc <= execute2_pc + execute2_topOfStack(maxAddrBit downto 0); + execute2_persistTopOfStack <= '1'; + when Decoded_PopPC => + execute2_pc <= execute2_topOfStack(maxAddrBit downto 0); + execute2_sp <= execute2_sp + 1; + + memBWriteEnable <= '1'; + memBAddr <= execute2_sp + 1; + memBWrite <= execute2_topOfStackB; + execute2_resync <= '1'; + when Decoded_Emulate => + execute2_sp <= execute2_sp - 1; + + execute2_topOfStack <= (others => DontCareValue); + execute2_topOfStack(maxAddrBit downto 0) <= execute2_pc + 1; + execute2_topOfStackB <= execute2_topOfStack; + + memBWriteEnable <= '1'; + memBAddr <= execute2_sp+1; + memBWrite <= execute2_topOfStackB; + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + execute2_pc <= (others => '0'); + execute2_pc(9 downto 5) <= execute2_opcode(4 downto 0); + execute2_persistTopOfStack <= '1'; + when Decoded_Im => + execute2_sp <= execute2_sp - 1; + for i in wordSize-1 downto 7 loop + execute2_topOfStack(i) <= execute2_opcode(6); + end loop; + execute2_topOfStack(6 downto 0) <= execute2_opcode(6 downto 0); + + execute2_topOfStackB <= execute2_topOfStack; + memBWriteEnable <= '1'; + memBAddr <= execute2_sp + 1; + memBWrite <= execute2_topOfStackB; + when Decoded_ImShift => + execute2_topOfStack(wordSize-1 downto 7) <= execute2_topOfStack(wordSize-8 downto 0); + execute2_topOfStack(6 downto 0) <= execute2_opcode(6 downto 0); + when Decoded_LoadSP => + execute2_sp <= execute2_sp - 1; + execute2_topOfStack <= memARead; + execute2_topOfStackB <= execute2_topOfStack; + memBWriteEnable <= '1'; + memBAddr <= execute2_sp + 1; + memBWrite <= execute2_topOfStackB; + when Decoded_Break => + report "Break instruction encountered" severity failure; + break <= '1'; + when Decoded_PushSP => + execute2_topOfStack <= (others => DontCareValue); + execute2_topOfStack(maxAddrBit downto minAddrBit) <= execute2_sp; + + execute2_sp <= execute2_sp - 1; + execute2_topOfStackB <= execute2_topOfStack; + memBWriteEnable <= '1'; + memBAddr <= execute2_sp + 1; + memBWrite <= execute2_topOfStackB; + when Decoded_Add => + execute2_sp <= execute2_sp + 1; + execute2_topOfStack <= execute2_topOfStackB + execute2_topOfStack; + execute2_topOfStackB <= memARead; + when Decoded_Sub => + execute2_sp <= execute2_sp + 1; + execute2_topOfStack <= execute2_topOfStackB - execute2_topOfStack; + execute2_topOfStackB <= memARead; + when Decoded_AddSP => + execute2_topOfStack <= execute2_topOfStack + memARead; + when Decoded_Or => + execute2_sp <= execute2_sp + 1; + execute2_topOfStack <= execute2_topOfStackB or execute2_topOfStack; + execute2_topOfStackB <= memARead; + when Decoded_And => + execute2_sp <= execute2_sp + 1; + execute2_topOfStack <= execute2_topOfStackB and execute2_topOfStack; + execute2_topOfStackB <= memARead; + when Decoded_Load | Decoded_Loadb | Decoded_Storeb => + if (execute2_topOfStack(ioBit)='1') then + io_addr <= execute2_topOfStack(maxAddrBit downto minAddrBit); + io_readEnable <= '1'; + else + memAAddr <= execute2_topOfStack(maxAddrBit downto minAddrBit); + execute1_fetched <= '0'; + end if; + if (execute2_decodedOpcode = Decoded_Loadb) then + execute2_loadByte <= '1'; + else + execute2_loadByte <= '0'; + end if; + if (execute2_decodedOpcode = Decoded_Storeb) then + execute2_storeByte <= '1'; + else + execute2_storebyte <= '0'; + end if; + execute2_loading <= '1'; + when Decoded_Ashiftleft => + execute2_topOfStack(wordSize-1 downto 1) <= execute2_topOfStack(wordSize-2 downto 0); + execute2_topOfStack(0) <= '0'; + when Decoded_MoveDown => + execute2_sp <= execute2_sp + 1; + execute2_topOfStackB <= memARead; + when Decoded_MoveDown2 => + execute2_sp <= execute2_sp + 1; + execute2_topOfStack <= execute2_topOfStackB; + execute2_topOfStackB <= execute2_topOfStack; + when Decoded_MoveDown3 => + execute2_sp <= execute2_sp + 1; + memBWriteEnable <= '1'; + memBAddr <= execute2_sp+execute2_spOffset; + memBWrite <= execute2_topOfStack; + + execute2_topOfStack <= execute2_topOfStackB; + execute2_topOfStackB <= memARead; + execute2_persistTopOfStack <= '1'; + when Decoded_Duplicate => + execute2_topOfStackB <= execute2_topOfStack; + execute2_sp <= execute2_sp - 1; + memBWriteEnable <= '1'; + memBAddr <= execute2_sp + 1; + memBWrite <= execute2_topOfStackB; + when Decoded_Duplicate2 => + execute2_topOfStack <= execute2_topOfStackB; + execute2_topOfStackB <= execute2_topOfStack; + execute2_sp <= execute2_sp - 1; + memBWriteEnable <= '1'; + memBAddr <= execute2_sp + 1; + memBWrite <= execute2_topOfStackB; + when Decoded_Duplicate3 => + execute2_topOfStack <= memARead; + execute2_topOfStackB <= execute2_topOfStack; + execute2_sp <= execute2_sp - 1; + memBWriteEnable <= '1'; + memBAddr <= execute2_sp + 1; + memBWrite <= execute2_topOfStackB; + when Decoded_Pushspadd => + execute2_topOfStack <= (others => DontCareValue); + execute2_topOfStack(maxAddrBit downto minAddrBit) <= execute2_sp + execute2_topOfStack(maxAddrBit-minAddrBit downto 0); + when Decoded_Not => + execute2_topOfStack <= not execute2_topOfStack; + when Decoded_Flip => + for i in 0 to wordSize-1 loop + execute2_topOfStack(i) <= execute2_topOfStack(wordSize-1-i); + end loop; + when Decoded_Store => + execute2_sp <= execute2_sp + 2; + if (execute2_topOfStack(ioBit)='0') then + memBAddr <= execute2_topOfStack(maxAddrBit downto minAddrBit); + memBWrite <= execute2_topOfStackB; + memBWriteEnable <= '1'; + else + io_addr <= execute2_topOfStack(maxAddrBit downto minAddrBit); + io_write <= execute2_topOfStackB(7 downto 0); + io_writeEnable <= '1'; + end if; + execute2_resync <= '1'; + when Decoded_StoreSP => + execute2_sp <= execute2_sp + 1; + memBWriteEnable <= '1'; + memBAddr <= execute2_sp+execute2_spOffset; + memBWrite <= execute2_topOfStack; + + execute2_topOfStack <= execute2_topOfStackB; + execute2_topOfStackB <= memARead; + when Decoded_Neqbranch => + execute2_sp <= execute2_sp + 2; + if (execute2_topOfStackB/=0) then + execute2_pc <= execute2_topOfStack(maxAddrBit downto 0) + execute2_pc; + end if; + execute2_resync <= '1'; + when Decoded_Eq => + execute2_sp <= execute2_sp + 1; + execute2_topOfStack <= (others => '0'); + if (execute2_topOfStack=execute2_topOfStackB) then + execute2_topOfStack(0) <= '1'; + end if; + execute2_topOfStackB <= memARead; + when Decoded_Ulessthan => + execute2_sp <= execute2_sp + 1; + execute2_topOfStack <= (others => '0'); + if (execute2_topOfStack + execute2_sp <= execute2_sp + 1; + execute2_topOfStack <= (others => '0'); + compareA := signed(execute2_topOfStack); + compareB := signed(execute2_topOfStackB); + if (compareA + begin_inst <= '0'; + execute2_pc <= execute2_pc; + when others => + -- nop + end case; + + -- load cycle... + execute2_loadingDone <= execute2_loading; + if (execute2_loadingDone ='1') then + if (execute2_topOfStack(ioBit)='1') then + if (io_busy = '0') then + execute2_topOfStack <= (others => '0'); + execute2_topOfStack(7 downto 0) <= io_read; + execute2_persistTopOfStack <= '1'; + else + execute2_loadingDone <= '1'; + end if; + else + if (execute2_storeByte = '1') then + execute2_sp <= execute2_sp + 2; + memBWriteEnable <= '1'; + memBAddr <= execute2_topOfStack(maxAddrBit downto minAddrBit); + memBWrite <= memARead; + case execute2_topOfStack(minAddrBit-1 downto 0) is + when "00" => memBWrite(31 downto 24) <= execute2_topOfStackB(7 downto 0); + when "01" => memBWrite(23 downto 16) <= execute2_topOfStackB(7 downto 0); + when "10" => memBWrite(15 downto 8) <= execute2_topOfStackB(7 downto 0); + when others => memBWrite(7 downto 0) <= execute2_topOfStackB(7 downto 0); + end case; +-- case execute2_topOfStack(0 downto 0) is +-- when "1" => memBWrite(15 downto 8) <= execute2_topOfStackB(7 downto 0); +-- when others => memBWrite(7 downto 0) <= execute2_topOfStackB(7 downto 0); +-- end case; + execute2_resync <= '1'; + elsif (execute2_loadByte = '1') then + execute2_topOfStack <= (others => '0'); + case execute2_topOfStack(minAddrBit-1 downto 0) is + when "00" => execute2_topOfStack(7 downto 0) <= memARead(31 downto 24); + when "01" => execute2_topOfStack(7 downto 0) <= memARead(23 downto 16); + when "10" => execute2_topOfStack(7 downto 0) <= memARead(15 downto 8); + when others => execute2_topOfStack(7 downto 0) <= memARead(7 downto 0); + end case; +-- case execute2_topOfStack(0 downto 0) is +-- when "1" => execute2_topOfStack(7 downto 0) <= memARead(15 downto 8); +-- when others => execute2_topOfStack(7 downto 0) <= memARead(7 downto 0); +-- end case; + execute2_persistTopOfStack <= '1'; + else + execute2_topOfStack <= memARead; + execute2_persistTopOfStack <= '1'; + end if; + end if; + end if; + + -- write top of stack... + execute2_persistTopOfStackB <= execute2_persistTopOfStack; + if (execute2_persistTopOfStack = '1') then + execute2_persistTopOfStack <= '0'; + memBWriteEnable <= '1'; + memBAddr <= execute2_sp; + memBWrite <= execute2_topOfStack; + end if; + if (execute2_persistTopOfStackB = '1') then + memBWriteEnable <= '1'; + memBAddr <= execute2_sp+1; + memBWrite <= execute2_topOfStackB; + + execute2_resync <= '1'; + end if; + + -- here we resync the pipeline. + -- a number of things have to happen on certain cycles + execute2_resync2 <= execute2_resync; + execute2_resync3 <= execute2_resync2; + execute2_resync4 <= execute2_resync3; + execute2_resync5 <= execute2_resync4; + execute2_resync6 <= execute2_resync5; + execute2_resync7 <= execute2_resync6; + execute2_resync8 <= execute2_resync7; + execute2_resync9 <= execute2_resync8; + execute2_resync10 <= execute2_resync9; + + if (execute2_resync = '1' ) then + -- resync #1 + execute2_resync <= '0'; + decode_starved <= '1'; + memAAddr <= execute2_sp; + end if; + if (execute2_resync2 = '1') then + -- resync #2 + execute1_fetchPC <= execute2_pc; + memAAddr <= execute2_sp + 1; + end if; + if (execute2_resync3 = '1') then + -- resync #3 + execute2_topOfStack <= memARead; + end if; + if (execute2_resync4 = '1') then + -- resync #4 + -- during this cycle the address is set to the opcode + execute2_topOfStackB <= memARead; + end if; + if (execute2_resync5 = '1') then + -- resync #5 + execute1_pop1 <= '0'; + execute1_push1 <= '0'; + end if; + if (execute2_resync6 = '1') then + -- resync #6 + decode_idim_flag <= '0'; + execute1_pop1 <= '0'; + execute1_push1 <= '0'; + end if; + if (execute2_resync7 = '1') then + -- resync #7 + execute1_sp <= execute2_sp; + execute1_stall <= '0'; + end if; + if (execute2_resync8 = '1') then + -- resync #8 +-- load_stall <= '0'; + end if; + if (execute2_resync9 = '1') then + -- resync #9 + end if; + if (execute2_resync10 = '1') then + end if; + + + + + end if; + end process; + + + +end behave; diff --git a/zpu/hdl/zpu3/src/zpu_top.vhd b/zpu/hdl/zpu3/src/zpu_top.vhd new file mode 100644 index 0000000..0ac6df4 --- /dev/null +++ b/zpu/hdl/zpu3/src/zpu_top.vhd @@ -0,0 +1,421 @@ +-- Company: ZPU3 +-- Engineer: Øyvind Harboe + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library zylin; +use zylin.zpu_config.all; +use zylin.zpupkg.all; + + +entity zpu_top is + Port ( clk : in std_logic; + areset : in std_logic; + io_busy : in std_logic; + io_read : in std_logic_vector(7 downto 0); + io_write : out std_logic_vector(7 downto 0); + io_addr : out std_logic_vector(maxAddrBit downto minAddrBit); + io_writeEnable : out std_logic; + io_readEnable : out std_logic; + interrupt : in std_logic; + break : out std_logic); +end zpu_top; + +architecture behave of zpu_top is + +signal readIO : std_logic; + + + +signal memAWriteEnable : std_logic; +signal memAAddr : std_logic_vector(maxAddrBit downto minAddrBit); +signal memAWrite : std_logic_vector(wordSize-1 downto 0); +signal memARead : std_logic_vector(wordSize-1 downto 0); +signal memBWriteEnable : std_logic; +signal memBAddr : std_logic_vector(maxAddrBit downto minAddrBit); +signal memBWrite : std_logic_vector(wordSize-1 downto 0); +signal memBRead : std_logic_vector(wordSize-1 downto 0); + + + +signal pc : std_logic_vector(maxAddrBit downto 0); +signal sp : std_logic_vector(maxAddrBit downto minAddrBit); + +signal idim_flag : std_logic; + +--signal storeToStack : std_logic; +--signal fetchNextInstruction : std_logic; +--signal extraCycle : std_logic; +signal busy : std_logic; +--signal fetching : std_logic; + +signal begin_inst : std_logic; + + + +signal trace_opcode : std_logic_vector(7 downto 0); +signal trace_pc : std_logic_vector(maxAddrBit downto 0); +signal trace_sp : std_logic_vector(maxAddrBit downto minAddrBit); +signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); +signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); + +-- state machine. + +subtype State_Type is std_logic_vector(3 downto 0); +constant State_Fetch : State_Type := b"0000"; +constant State_WriteIODone : State_Type := b"0001"; +constant State_Execute : State_Type := b"0010"; +constant State_StoreToStack : State_Type := b"0011"; +constant State_Add : State_Type := b"0100"; +constant State_Or : State_Type := b"0101"; +constant State_And : State_Type := b"0110"; +constant State_Store : State_Type := b"0111"; +constant State_ReadIO : State_Type := b"1000"; +constant State_WriteIO : State_Type := b"1001"; +constant State_Load : State_Type := b"1010"; +constant State_FetchNext : State_Type := b"1011"; +constant State_AddSP : State_Type := b"1100"; +constant State_ReadIODone : State_Type := b"1101"; +constant State_Decode : State_Type := b"1110"; +constant State_Resync : State_Type := b"1111"; + + +subtype DecodedOpcodeType is std_logic_vector(4 downto 0); +constant Decoded_Nop : DecodedOpcodeType := b"00000"; +constant Decoded_Im : DecodedOpcodeType := b"00001"; +constant Decoded_ImShift : DecodedOpcodeType := b"00010"; +constant Decoded_LoadSP : DecodedOpcodeType := b"00011"; +constant Decoded_StoreSP : DecodedOpcodeType := b"00100"; +constant Decoded_AddSP : DecodedOpcodeType := b"00101"; +constant Decoded_Emulate : DecodedOpcodeType := b"00110"; +constant Decoded_Break : DecodedOpcodeType := b"00111"; +constant Decoded_PushPC : DecodedOpcodeType := b"01000"; +constant Decoded_PushSP : DecodedOpcodeType := b"01001"; +constant Decoded_PopPC : DecodedOpcodeType := b"01010"; +constant Decoded_Add : DecodedOpcodeType := b"01011"; +constant Decoded_Or : DecodedOpcodeType := b"01100"; +constant Decoded_And : DecodedOpcodeType := b"01101"; +constant Decoded_Load : DecodedOpcodeType := b"01110"; +constant Decoded_Not : DecodedOpcodeType := b"01111"; +constant Decoded_Flip : DecodedOpcodeType := b"10000"; +constant Decoded_Store : DecodedOpcodeType := b"10001"; +constant Decoded_PopSP : DecodedOpcodeType := b"10010"; + +signal opcode : std_logic_vector(OpCode_Size-1 downto 0); + +signal decodedOpcode : DecodedOpcodeType; + +signal state : State_Type; + +begin + traceFileGenerate: + if Generate_Trace generate + trace_file: trace port map ( + clk => clk, + begin_inst => begin_inst, + pc => trace_pc, + opcode => trace_opcode, + sp => trace_sp, + memA => trace_topOfStack, + memB => trace_topOfStackB, + busy => busy + ); + end generate; + + + memory: dualport_ram port map ( + clk => clk, + memAWriteEnable => memAWriteEnable, + memAAddr => memAAddr, + memAWrite => memAWrite, + memARead => memARead, + memBWriteEnable => memBWriteEnable, + memBAddr => memBAddr, + memBWrite => memBWrite, + memBRead => memBRead + ); + + + + + opcodeControl: + process(clk, areset) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + variable spOffset : std_logic_vector(4 downto 0); + begin + if areset = '1' then + state <= State_Resync; + break <= '0'; + sp <= (2 => '0', others => '1'); + pc <= (others => '0'); + idim_flag <= '0'; + begin_inst <= '0'; + memAAddr <= (others => '0'); + memBAddr <= (others => '0'); + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + io_writeEnable <= '0'; + io_readEnable <= '0'; + decodedOpcode <= (others => '0'); + memAWrite <= (others => '0'); + memBWrite <= (others => '0'); + opcode <= (others => '0'); + io_addr <= (others => '0'); + io_write <= (others => '0'); + elsif (clk'event and clk = '1') then + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + -- This saves ca. 100 LUT's, by explicitly declaring that the + -- memAWrite can be left at whatever value if memAWriteEnable is + -- not set. + memAWrite <= (others => DontCareValue); + memBWrite <= (others => DontCareValue); + opcode <= (others => DontCareValue); +-- io_addr <= (others => DontCareValue); +-- io_write <= (others => DontCareValue); + spOffset := (others => DontCareValue); + memAAddr <= (others => DontCareValue); + memBAddr <= (others => DontCareValue); + + io_writeEnable <= '0'; + io_readEnable <= '0'; + begin_inst <= '0'; + + case state is + when State_Execute => + state <= State_Fetch; + -- at this point: + -- memBRead contains opcode word + -- memARead contains top of stack + pc <= pc + 1; + + -- trace + begin_inst <= '1'; + trace_pc <= pc; + trace_opcode <= opcode; + trace_sp <= sp; + trace_topOfStack <= memARead; + trace_topOfStackB <= memBRead; + + -- during the next cycle we'll be reading the next opcode + spOffset(4):=not opcode(4); + spOffset(3 downto 0):=opcode(3 downto 0); + + case decodedOpcode is + when Decoded_Im => + memAWriteEnable <= '1'; + sp <= sp - 1; + memAAddr <= sp-1; + for i in wordSize-1 downto 7 loop + memAWrite(i) <= opcode(6); + end loop; + memAWrite(6 downto 0) <= opcode(6 downto 0); + when Decoded_ImShift => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0); + memAWrite(6 downto 0) <= opcode(6 downto 0); + when Decoded_StoreSP => + memBWriteEnable <= '1'; + memBAddr <= sp+spOffset; + memBWrite <= memARead; + sp <= sp + 1; + state <= State_Resync; + when Decoded_LoadSP => + sp <= sp - 1; + memAAddr <= sp+spOffset; + when Decoded_Emulate => + sp <= sp - 1; + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto 0) <= pc + 1; + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= (others => '0'); + pc(9 downto 5) <= opcode(4 downto 0); + when Decoded_AddSP => + memAAddr <= sp; + memBAddr <= sp+spOffset; + state <= State_AddSP; + when Decoded_Break => + report "Break instruction encountered" severity failure; + break <= '1'; + when Decoded_PushSP => + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + sp <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto minAddrBit) <= sp; + when Decoded_PopPC => + pc <= memARead(maxAddrBit downto 0); + sp <= sp + 1; + state <= State_Resync; + when Decoded_Add => + sp <= sp + 1; + state <= State_Add; + when Decoded_Or => + sp <= sp + 1; + state <= State_Or; + when Decoded_And => + sp <= sp + 1; + state <= State_And; + when Decoded_Load => + if (memARead(ioBit)='1') then + io_addr <= memARead(maxAddrBit downto minAddrBit); + io_readEnable <= '1'; + state <= State_ReadIO; + else + memAAddr <= memARead(maxAddrBit downto minAddrBit); + end if; + when Decoded_Not => + memAAddr <= sp(maxAddrBit downto minAddrBit); + memAWriteEnable <= '1'; + memAWrite <= not memARead; + when Decoded_Flip => + memAAddr <= sp(maxAddrBit downto minAddrBit); + memAWriteEnable <= '1'; + for i in 0 to wordSize-1 loop + memAWrite(i) <= memARead(wordSize-1-i); + end loop; + when Decoded_Store => + memBAddr <= sp + 1; + sp <= sp + 1; + if (memARead(ioBit)='1') then + state <= State_WriteIO; + else + state <= State_Store; + end if; + when Decoded_PopSP => + sp <= memARead(maxAddrBit downto minAddrBit); + state <= State_Resync; + when Decoded_Nop => + memAAddr <= sp; + when others => + null; + end case; + when State_ReadIO => + if (io_busy = '0') then + state <= State_Fetch; + memAWriteEnable <= '1'; + memAWrite <= (others => '0'); + memAWrite(7 downto 0) <= io_read; + end if; + when State_WriteIO => + sp <= sp + 1; + io_writeEnable <= '1'; + io_addr <= memARead(maxAddrBit downto minAddrBit); + io_write <= memBRead(7 downto 0); + state <= State_WriteIODone; + when State_WriteIODone => + if (io_busy = '0') then + state <= State_Resync; + end if; + when State_Fetch => + -- We need to resync. During the *next* cycle + -- we'll fetch the opcode @ pc and thus it will + -- be available for State_Execute the cycle after + -- next + memBAddr <= pc(maxAddrBit downto minAddrBit); + state <= State_FetchNext; + when State_FetchNext => + -- at this point memARead contains the value that is either + -- from the top of stack or should be copied to the top of the stack + memAWriteEnable <= '1'; + memAWrite <= memARead; + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Decode; + when State_Decode => + case pc(1 downto 0) is + when "00" => tOpcode := memBRead(31 downto 24); + when "01" => tOpcode := memBRead(23 downto 16); + when "10" => tOpcode := memBRead(15 downto 8); + when others => tOpcode := memBRead(7 downto 0); + end case; + idim_flag <= tOpcode(7); + opcode <= tOpcode; + if (tOpcode(7 downto 7)=OpCode_Im) then + if (idim_flag='1') then + decodedOpcode<=Decoded_ImShift; + else + decodedOpcode<=Decoded_Im; + end if; + elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then + decodedOpcode<=Decoded_StoreSP; + elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then + decodedOpcode<=Decoded_LoadSP; + elsif (tOpcode(7 downto 5)=OpCode_Emulate) then + decodedOpcode<=Decoded_Emulate; + elsif (tOpcode(7 downto 4)=OpCode_AddSP) then + decodedOpcode<=Decoded_AddSP; + else + case tOpcode(3 downto 0) is + when OpCode_Break => + decodedOpcode<=Decoded_Break; + when OpCode_PushSP => + decodedOpcode<=Decoded_PushSP; + when OpCode_PopPC => + decodedOpcode<=Decoded_PopPC; + when OpCode_Add => + decodedOpcode<=Decoded_Add; + when OpCode_Or => + decodedOpcode<=Decoded_Or; + when OpCode_And => + decodedOpcode<=Decoded_And; + when OpCode_Load => + decodedOpcode<=Decoded_Load; + when OpCode_Not => + decodedOpcode<=Decoded_Not; + when OpCode_Flip => + decodedOpcode<=Decoded_Flip; + when OpCode_Store => + decodedOpcode<=Decoded_Store; + when OpCode_PopSP => + decodedOpcode<=Decoded_PopSP; + when others => + decodedOpcode<=Decoded_Nop; + end case; + end if; + -- during the State_Execute cycle we'll be fetching SP+1 + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Execute; + when State_Store => + sp <= sp + 1; + memAWriteEnable <= '1'; + memAAddr <= memARead(maxAddrBit downto minAddrBit); + memAWrite <= memBRead; + state <= State_Resync; + when State_AddSP => + state <= State_Add; + when State_Add => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead + memBRead; + state <= State_Fetch; + when State_Or => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead or memBRead; + state <= State_Fetch; + when State_Resync => + memAAddr <= sp; + state <= State_Fetch; + when State_And => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead and memBRead; + state <= State_Fetch; + when others => + null; + end case; + end if; + end process; + + + +end behave; diff --git a/zpu/hdl/zpu3/src/zpu_top_medium.vhd b/zpu/hdl/zpu3/src/zpu_top_medium.vhd new file mode 100644 index 0000000..4896b30 --- /dev/null +++ b/zpu/hdl/zpu3/src/zpu_top_medium.vhd @@ -0,0 +1,768 @@ +-- Company: ZPU3 +-- Engineer: Øyvind Harboe + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.STD_LOGIC_arith.ALL; + +library zylin; +use zylin.zpu_config.all; +use zylin.zpupkg.all; + + +entity zpu_top is + Port ( clk : in std_logic; + areset : in std_logic; + io_busy : in std_logic; + io_read : in std_logic_vector(7 downto 0); + io_write : out std_logic_vector(7 downto 0); + io_addr : out std_logic_vector(maxAddrBit downto minAddrBit); + io_writeEnable : out std_logic; + io_readEnable : out std_logic; + interrupt : in std_logic; + break : out std_logic); +end zpu_top; + +architecture behave of zpu_top is + +signal readIO : std_logic; + + + +signal memAWriteEnable : std_logic; +signal memAAddr : std_logic_vector(maxAddrBit downto minAddrBit); +signal memAWrite : std_logic_vector(wordSize-1 downto 0); +signal memARead : std_logic_vector(wordSize-1 downto 0); +signal memBWriteEnable : std_logic; +signal memBAddr : std_logic_vector(maxAddrBit downto minAddrBit); +signal memBWrite : std_logic_vector(wordSize-1 downto 0); +signal memBRead : std_logic_vector(wordSize-1 downto 0); + + + +signal pc : std_logic_vector(maxAddrBit downto 0); +signal sp : std_logic_vector(maxAddrBit downto minAddrBit); + +signal idim_flag : std_logic; + +--signal storeToStack : std_logic; +--signal fetchNextInstruction : std_logic; +--signal extraCycle : std_logic; +signal busy : std_logic; +--signal fetching : std_logic; + +signal begin_inst : std_logic; + + + +signal trace_opcode : std_logic_vector(7 downto 0); +signal trace_pc : std_logic_vector(maxAddrBit downto 0); +signal trace_sp : std_logic_vector(maxAddrBit downto minAddrBit); +signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); + +-- state machine. + +subtype State_Type is std_logic_vector(4 downto 0); +constant State_ResyncDecode : State_Type := b"00000"; +constant State_WriteIODone : State_Type := b"00001"; +constant State_Execute : State_Type := b"00010"; +constant State_StoreToStack : State_Type := b"00011"; +constant State_Add : State_Type := b"00100"; +constant State_Or : State_Type := b"00101"; +constant State_And : State_Type := b"00110"; +constant State_Store : State_Type := b"00111"; +constant State_ReadIO : State_Type := b"01000"; +constant State_WriteIO : State_Type := b"01001"; +constant State_Load : State_Type := b"01010"; +constant State_ResyncStack : State_Type := b"01011"; +constant State_AddSP : State_Type := b"01100"; +constant State_ReadIODone : State_Type := b"01101"; +constant State_Decode : State_Type := b"01110"; +constant State_LoadByte1 : State_Type := b"01111"; +constant State_LoadByte2 : State_Type := b"10000"; +constant State_StoreByte1 : State_Type := b"10001"; +constant State_StoreByte2 : State_Type := b"10010"; +constant State_Mult1 : State_Type := b"10011"; +constant State_Mult2 : State_Type := b"10100"; +constant State_Mult3 : State_Type := b"10101"; + + +subtype DecodedOpcodeType is std_logic_vector(5 downto 0); +constant Decoded_Nop : DecodedOpcodeType := b"000000"; +constant Decoded_Im : DecodedOpcodeType := b"000001"; +constant Decoded_ImShift : DecodedOpcodeType := b"000010"; +constant Decoded_LoadSP : DecodedOpcodeType := b"000011"; +constant Decoded_StoreSP : DecodedOpcodeType := b"000100"; +constant Decoded_AddSP : DecodedOpcodeType := b"000101"; +constant Decoded_Emulate : DecodedOpcodeType := b"000110"; +constant Decoded_Break : DecodedOpcodeType := b"000111"; +constant Decoded_PushPC : DecodedOpcodeType := b"001000"; +constant Decoded_PushSP : DecodedOpcodeType := b"001001"; +constant Decoded_PopPC : DecodedOpcodeType := b"001010"; +constant Decoded_Add : DecodedOpcodeType := b"001011"; +constant Decoded_Or : DecodedOpcodeType := b"001100"; +constant Decoded_And : DecodedOpcodeType := b"001101"; +constant Decoded_Load : DecodedOpcodeType := b"001110"; +constant Decoded_Not : DecodedOpcodeType := b"001111"; +constant Decoded_Flip : DecodedOpcodeType := b"010000"; +constant Decoded_Store : DecodedOpcodeType := b"010001"; +constant Decoded_PopSP : DecodedOpcodeType := b"010010"; +constant Decoded_Ashiftleft : DecodedOpcodeType := b"010011"; +constant Decoded_Ashiftright : DecodedOpcodeType := b"010100"; +constant Decoded_Lshiftright : DecodedOpcodeType := b"010101"; +constant Decoded_Eqbranch : DecodedOpcodeType := b"010110"; +constant Decoded_Neqbranch : DecodedOpcodeType := b"010111"; +constant Decoded_Eq : DecodedOpcodeType := b"011000"; +constant Decoded_Neq : DecodedOpcodeType := b"011001"; +constant Decoded_Loadb : DecodedOpcodeType := b"011010"; +constant Decoded_Lessthan : DecodedOpcodeType := b"011011"; +constant Decoded_Lessthanorequal : DecodedOpcodeType := b"011100"; +constant Decoded_Ulessthan : DecodedOpcodeType := b"011101"; +constant Decoded_Ulessthanorequal : DecodedOpcodeType := b"011110"; +constant Decoded_Storeb : DecodedOpcodeType := b"011111"; +constant Decoded_Lshift2 : DecodedOpcodeType := b"100000"; +constant Decoded_DoubleIm : DecodedOpcodeType := b"100001"; +constant Decoded_AddIm : DecodedOpcodeType := b"100011"; +constant Decoded_Mult16x16 : DecodedOpcodeType := b"100100"; +constant Decoded_Swap : DecodedOpcodeType := b"100101"; +constant Decoded_Callpcrel : DecodedOpcodeType := b"100110"; +constant Decoded_Pushspadd : DecodedOpcodeType := b"100111"; + + +signal mult1 : std_logic_vector(wordSize/2-1 downto 0); +signal mult2 : std_logic_vector(wordSize/2-1 downto 0); +signal multResult : std_logic_vector(wordSize-1 downto 0); + +signal storeByte : std_logic_vector(7 downto 0); +signal byteSelect : std_logic_vector(minAddrBit-1 downto 0); + +signal opcode : std_logic_vector(OpCode_Size-1 downto 0); +signal opcode2 : std_logic_vector(OpCode_Size-1 downto 0); + +signal decodedOpcode : DecodedOpcodeType; + +signal state : State_Type; + +begin + traceFileGenerate: + if Generate_Trace generate + trace_file: trace port map ( + clk => clk, + begin_inst => begin_inst, + pc => trace_pc, + opcode => trace_opcode, + sp => trace_sp, + memA => trace_topOfStack, + busy => busy + ); + end generate; + + + memory: dualport_ram port map ( + clk => clk, + memAWriteEnable => memAWriteEnable, + memAAddr => memAAddr, + memAWrite => memAWrite, + memARead => memARead, + memBWriteEnable => memBWriteEnable, + memBAddr => memBAddr, + memBWrite => memBWrite, + memBRead => memBRead + ); + + + process(clk, areset) + begin + if (clk'event and clk = '1') then + multResult <= mult1 * mult2; + end if; + end process; + + + + opcodeControl: + process(clk, areset) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + variable tOpcode2 : std_logic_vector(OpCode_Size-1 downto 0); + variable spOffset : std_logic_vector(4 downto 0); + variable spOffset2 : std_logic_vector(4 downto 0); + variable nextPC : std_logic_vector(maxAddrBit downto 0); + variable pushspaddTemp : std_logic_vector(maxAddrBit downto minAddrBit); + variable tempVal : std_logic_vector(wordSize-1 downto 0); + variable compareA : signed(wordSize-1 downto 0); + variable compareB : signed(wordSize-1 downto 0); + begin + if areset = '1' then + mult1 <= (others => '0'); + mult2 <= (others => '0'); + state <= State_ResyncDecode; + break <= '0'; + sp <= (2 => '0', others => '1'); + pc <= (others => '0'); + idim_flag <= '0'; + begin_inst <= '0'; + memAAddr <= (others => '0'); + memBAddr <= (others => '0'); + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + io_writeEnable <= '0'; + io_readEnable <= '0'; + decodedOpcode <= (others => '0'); + memAWrite <= (others => '0'); + memBWrite <= (others => '0'); + opcode <= (others => '0'); + io_addr <= (others => '0'); + io_write <= (others => '0'); + elsif (clk'event and clk = '1') then + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + + io_writeEnable <= '0'; + io_readEnable <= '0'; + begin_inst <= '0'; + + case state is + when State_Decode => + nextPC:=pc+1; + case pc(1 downto 0) is + when "00" => tOpcode := memARead(31 downto 24); + when "01" => tOpcode := memARead(23 downto 16); + when "10" => tOpcode := memARead(15 downto 8); + when others => tOpcode := memARead(7 downto 0); + end case; + case nextPC(1 downto 0) is + when "00" => tOpcode2 := memBRead(31 downto 24); + when "01" => tOpcode2 := memBRead(23 downto 16); + when "10" => tOpcode2 := memBRead(15 downto 8); + when others => tOpcode2 := memBRead(7 downto 0); + end case; + idim_flag <= tOpcode(7); + opcode <= tOpcode; + opcode2 <= tOpcode2; + if (tOpcode(7 downto 7)=OpCode_Im and tOpcode2(7 downto 4)=0 and tOpcode2(3 downto 0)=Opcode_Add and idim_flag='0') then + idim_flag <= '0'; + decodedOpcode <= Decoded_AddIm; + nextPC := pc + 2; + elsif (tOpcode(7 downto 7)=OpCode_Im and tOpcode2(7 downto 7)=OpCode_Im and idim_flag='0') then + decodedOpcode <= Decoded_DoubleIm; + nextPC := pc + 2; + elsif (tOpcode(7 downto 4)=OpCode_AddSP and tOpcode(3 downto 0)=0 and + tOpcode2(7 downto 4)=OpCode_AddSP and tOpcode2(3 downto 0)=0) then + decodedOpcode <= Decoded_Lshift2; + nextPC := pc + 2; + elsif (tOpcode(7 downto 7)=OpCode_Im) then + if (idim_flag='1') then + decodedOpcode<=Decoded_ImShift; + else + decodedOpcode<=Decoded_Im; + end if; + elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then + decodedOpcode<=Decoded_StoreSP; + elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then + decodedOpcode<=Decoded_LoadSP; + elsif (tOpcode(7 downto 5)=OpCode_Emulate) then + if tOpcode(5 downto 0)=OpCode_Eqbranch then + decodedOpcode <= Decoded_Eqbranch; + elsif tOpcode(5 downto 0)=OpCode_Neqbranch then + decodedOpcode <= Decoded_Neqbranch; + elsif tOpcode(5 downto 0)=OpCode_Eq then + decodedOpcode <= Decoded_Eq; + elsif tOpcode(5 downto 0)=OpCode_Neq then + decodedOpcode <= Decoded_Neq; + elsif tOpcode(5 downto 0)=OpCode_Lessthan then + decodedOpcode <= Decoded_Lessthan; + elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then + decodedOpcode <= Decoded_Lessthanorequal; + elsif tOpcode(5 downto 0)=OpCode_Ulessthan then + decodedOpcode <= Decoded_Ulessthan; + elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then + decodedOpcode <= Decoded_Ulessthanorequal; + elsif tOpcode(5 downto 0)=OpCode_Loadb then + decodedOpcode <= Decoded_Loadb; + elsif tOpcode(5 downto 0)=OpCode_Storeb then + decodedOpcode <= Decoded_Storeb; + elsif tOpcode(5 downto 0)=OpCode_Mult16x16 then + decodedOpcode <= Decoded_Mult16x16; + elsif tOpcode(5 downto 0)=OpCode_Swap then + decodedOpcode <= Decoded_Swap; + elsif tOpcode(5 downto 0)=OpCode_Callpcrel then + decodedOpcode <= Decoded_Callpcrel; + elsif tOpcode(5 downto 0)=OpCode_Pushspadd then + decodedOpcode <= Decoded_Pushspadd; +-- elsif tOpcode(5 downto 0)=OpCode_Lshiftright then +-- decodedOpcode <= Decoded_Lshiftright; +-- elsif tOpcode(5 downto 0)=OpCode_Ashiftleft then +-- decodedOpcode <= Decoded_Ashiftleft; +-- elsif tOpcode(5 downto 0)=OpCode_Ashiftright then +-- decodedOpcode <= Decoded_Ashiftright; + else + decodedOpcode<=Decoded_Emulate; + end if; + elsif (tOpcode(7 downto 4)=OpCode_AddSP) then + decodedOpcode<=Decoded_AddSP; + else + case tOpcode(3 downto 0) is + when OpCode_Break => + decodedOpcode<=Decoded_Break; + when OpCode_PushPC => + decodedOpcode<=Decoded_PushPC; + when OpCode_PushSP => + decodedOpcode<=Decoded_PushSP; + when OpCode_PopPC => + decodedOpcode<=Decoded_PopPC; + when OpCode_Add => + decodedOpcode<=Decoded_Add; + when OpCode_Or => + decodedOpcode<=Decoded_Or; + when OpCode_And => + decodedOpcode<=Decoded_And; + when OpCode_Load => + decodedOpcode<=Decoded_Load; + when OpCode_Not => + decodedOpcode<=Decoded_Not; + when OpCode_Flip => + decodedOpcode<=Decoded_Flip; + when OpCode_Store => + decodedOpcode<=Decoded_Store; + when OpCode_PopSP => + decodedOpcode<=Decoded_PopSP; + when others => + decodedOpcode<=Decoded_Nop; + end case; + end if; + -- Fetch the two next opcodes... :-) + memAAddr <= nextPC(maxAddrBit downto minAddrBit); + nextPC:=nextPC+1; + memBAddr <= nextPC(maxAddrBit downto minAddrBit); + state <= State_Execute; + when State_Execute => + state <= State_Decode; + -- at this point: + -- memBRead contains opcode word + -- memARead contains top of stack + pc <= pc + 1; + + -- trace + begin_inst <= '1'; + trace_pc <= pc; + trace_opcode <= opcode; + trace_sp <= sp; + trace_topOfStack <= memARead; + + -- during the next cycle we'll be reading the next opcode + spOffset(4):=not opcode(4); + spOffset(3 downto 0):=opcode(3 downto 0); + spOffset2(4):=not opcode2(4); + spOffset2(3 downto 0):=opcode2(3 downto 0); + + case decodedOpcode is + + when Decoded_DoubleIm => + memAWriteEnable <= '1'; + sp <= sp - 1; + memAAddr <= sp-1; + for i in wordSize-1 downto 14 loop + memAWrite(i) <= opcode(6); + end loop; + memAWrite(13 downto 7) <= opcode(6 downto 0); + memAWrite(6 downto 0) <= opcode2(6 downto 0); + memBAddr <= sp; + memBWrite <= memARead; + memBWriteEnable <= '1'; + pc <= pc + 2; + when Decoded_Im => + memAWriteEnable <= '1'; + sp <= sp - 1; + memAAddr <= sp-1; + for i in wordSize-1 downto 7 loop + memAWrite(i) <= opcode(6); + end loop; + memAWrite(6 downto 0) <= opcode(6 downto 0); + memBAddr <= sp; + memBWrite <= memARead; + memBWriteEnable <= '1'; + when Decoded_ImShift => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0); + memAWrite(6 downto 0) <= opcode(6 downto 0); + memBAddr <= sp + 1; + when Decoded_StoreSP => + memAWriteEnable <= '1'; + memAAddr <= sp+spOffset; + memAWrite <= memARead; + -- avoid address crashes. + memBAddr <= sp - 1; + sp <= sp + 1; + state <= State_ResyncDecode; + when Decoded_LoadSP => + sp <= sp - 1; + if (spOffset = 0) then + -- This is a duplicate instruction. + memAAddr <= sp-1; + memAWriteEnable <= '1'; + memAWrite <= memARead; + else + memAAddr <= sp+spOffset; + end if; + memBAddr <= sp; + memBWrite <= memARead; + memBWriteEnable <= '1'; + when Decoded_Callpcrel => + memAWriteEnable <= '1'; + memAAddr <= sp; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto 0) <= pc + 1; + memBAddr <= sp+1; + pc <= pc + memARead(maxAddrBit downto 0); + state <= State_ResyncDecode; + when Decoded_Emulate => + sp <= sp - 1; + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto 0) <= pc; + memBAddr <= sp; + memBWrite <= memARead; + memBWriteEnable <= '1'; + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= (others => '0'); + pc(9 downto 5) <= opcode(4 downto 0); + state <= State_ResyncDecode; + when Decoded_AddSP => + if spOffset=0 then + -- avoid address line crashes... + -- FIX!!! is this an issue? + -- oh-well. While we are at it, we've got a faster + -- shift operation without updating the toolchain. + memAWriteEnable <= '1'; + memAAddr <= sp; + memAWrite <= memARead + memARead; + memBAddr <= sp+1; + else + memAWriteEnable <= '1'; + memAAddr <= sp; + memAWrite <= memARead; + memBAddr <= sp+spOffset; + state <= State_AddSP; + end if; + when Decoded_Break => + report "Break instruction encountered" severity failure; + break <= '1'; + when Decoded_PushPC => + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + sp <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto 0) <= pc; + memBAddr <= sp; + memBWrite <= memARead; + memBWriteEnable <= '1'; + when Decoded_PushSP => + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + sp <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto minAddrBit) <= sp; + memBAddr <= sp; + memBWrite <= memARead; + memBWriteEnable <= '1'; + when Decoded_Pushspadd => + memAWriteEnable <= '1'; + memAAddr <= sp; + memAWrite <= (others => DontCareValue); + pushspaddTemp := memARead(maxAddrBit-minAddrBit downto 0); + memAWrite(maxAddrBit downto minAddrBit) <= sp+pushspaddTemp; + memBAddr <= sp+1; + when Decoded_PopPC => + memAAddr <= sp; + pc <= memARead(maxAddrBit downto 0); + sp <= sp + 1; + state <= State_ResyncDecode; + when Decoded_AddIm => + memAWriteEnable <= '1'; + memAAddr <= sp; + tempVal(wordSize-1 downto 7) := (others => tOpcode(6)); + tempVal(6 downto 0) := tOpcode(6 downto 0); + memAWrite <= memARead + tempVal; + memBAddr <= sp + 1; + pc <= pc + 2; + when Decoded_Add => + memAWriteEnable <= '1'; + memAWrite <= memARead + memBRead; + memAAddr <= sp + 1; + memBAddr <= sp + 2; + sp <= sp + 1; + when Decoded_Or => + sp <= sp + 1; + memAWriteEnable <= '1'; + memAWrite <= memARead or memBRead; + memAWriteEnable <= '1'; + memAAddr <= sp + 1; + memBAddr <= sp + 2; + when Decoded_And => + sp <= sp + 1; + memAWriteEnable <= '1'; + memAWrite <= memARead and memBRead; + memAWriteEnable <= '1'; + memAAddr <= sp + 1; + memBAddr <= sp + 2; + when Decoded_Load => + if (memARead(ioBit)='1') then + io_addr <= memARead(maxAddrBit downto minAddrBit); + io_readEnable <= '1'; + state <= State_ReadIO; + else + memAAddr <= memARead(maxAddrBit downto minAddrBit); + memBAddr <= sp + 1; + end if; + when Decoded_Swap => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite(wordSize/2-1 downto 0) <= memARead(wordSize-1 downto wordSize/2); + memAWrite(wordSize-1 downto wordSize/2) <= memARead(wordSize/2-1 downto 0); + memBAddr <= sp + 1; + when Decoded_Not => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= not memARead; + memBAddr <= sp + 1; + when Decoded_Flip => + memAAddr <= sp; + memAWriteEnable <= '1'; + for i in 0 to wordSize-1 loop + memAWrite(i) <= memARead(wordSize-1-i); + end loop; + memBAddr <= sp + 1; + when Decoded_Lshift2 => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite(1 downto 0) <= (others => '0'); + memAWrite(wordSize-1 downto 2) <= memARead(wordSize-1-2 downto 0); + memBAddr <= sp + 1; + pc <= pc + 2; + when Decoded_Store => + sp <= sp + 2; + if (memARead(ioBit)='1') then + io_writeEnable <= '1'; + io_addr <= memARead(maxAddrBit downto minAddrBit); + io_write <= memBRead(7 downto 0); + state <= State_WriteIO; + else + memAWriteEnable <= '1'; + memAAddr <= memARead(maxAddrBit downto minAddrBit); + memAWrite <= memBRead; + state <= State_ResyncDecode; + end if; + when Decoded_PopSP => + sp <= memARead(maxAddrBit downto minAddrBit); + state <= State_ResyncDecode; + when Decoded_Ashiftleft => + memAWrite(wordSize-1 downto conv_integer(memARead(wordPower-1 downto 0))) <= + memBRead(wordSize-conv_integer(memARead(wordPower-1 downto 0))-1 downto 0); + if memARead(wordPower-1 downto 0)/=0 then + memAWrite(conv_integer(memARead(wordPower-1 downto 0))-1 downto 0) <= (others => '0'); + end if; + memAWriteEnable <= '1'; + memAAddr <= sp + 1; + memBAddr <= sp + 2; + sp <= sp + 1; + when Decoded_Ashiftright | Decoded_Lshiftright => + memAWrite(wordSize-1-conv_integer(memARead(wordPower-1 downto 0)) downto 0) <= + memBRead(wordSize-1 downto conv_integer(memARead(wordPower-1 downto 0))); + if memARead(wordPower-1 downto 0)/=0 then + if decodedOpcode=Decoded_Ashiftright and memBRead(wordSize-1)='1' then + memAWrite(wordSize-1 downto wordSize-conv_integer(memARead(wordPower-1 downto 0))-1) <= (others => '1'); + else + memAWrite(wordSize-1 downto wordSize-conv_integer(memARead(wordPower-1 downto 0))-1) <= (others => '0'); + end if; + end if; + memAWriteEnable <= '1'; + memAAddr <= sp + 1; + memBAddr <= sp + 2; + sp <= sp + 1; + when Decoded_Eqbranch => + sp <= sp + 2; + if (memBRead=0) then + pc <= memARead(maxAddrBit downto 0) + pc; + end if; + state <= State_ResyncDecode; + when Decoded_Neqbranch => + sp <= sp + 2; + if (memBRead/=0) then + pc <= memARead(maxAddrBit downto 0) + pc; + end if; + state <= State_ResyncDecode; + when Decoded_Eq => + sp <= sp + 1; + memAWrite <= (others => '0'); + if (memARead=memBRead) then + memAWrite(0) <= '1'; + end if; + memAAddr <= sp + 1; + memAWriteEnable <= '1'; + memBAddr <= sp + 2; + when Decoded_Neq => + sp <= sp + 1; + memAWrite <= (others => '0'); + if (memARead/=memBRead) then + memAWrite(0) <= '1'; + end if; + memAAddr <= sp + 1; + memAWriteEnable <= '1'; + memBAddr <= sp + 2; + when Decoded_Ulessthan => + sp <= sp + 1; + memAWrite <= (others => '0'); + if (memARead + sp <= sp + 1; + memAWrite <= (others => '0'); + if (memARead<=memBRead) then + memAWrite(0) <= '1'; + end if; + memAAddr <= sp + 1; + memAWriteEnable <= '1'; + memBAddr <= sp + 2; + when Decoded_Lessthan => + sp <= sp + 1; + memAWrite <= (others => '0'); + compareA := signed(memARead); + compareB := signed(memBRead); + if (compareA + sp <= sp + 1; + memAWrite <= (others => '0'); + compareA := signed(memARead); + compareB := signed(memBRead); + if (compareA<=compareB) then + memAWrite(0) <= '1'; + end if; + memAAddr <= sp + 1; + memAWriteEnable <= '1'; + memBAddr <= sp + 2; + when Decoded_Loadb => + byteSelect <= memARead(minAddrBit-1 downto 0); + memAAddr <= memARead(maxAddrBit downto minAddrBit); + state <= State_LoadByte1; + when Decoded_Storeb => + sp <= sp + 2; + byteSelect <= memARead(minAddrBit-1 downto 0); + storeByte <= memBRead(7 downto 0); + memAAddr <= memARead(maxAddrBit downto minAddrBit); + memBAddr <= sp; + state <= State_StoreByte1; + when Decoded_Mult16x16 => + mult1 <= memARead(wordSize/2-1 downto 0); + mult2 <= memBRead(wordSize/2-1 downto 0); + sp <= sp + 1; + state <= State_Mult1; + when others => + -- nop. Here we persist whatever was loaded into + -- memARead + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead; + memBAddr <= sp + 1; + + end case; + when State_ReadIO => + state <= State_ReadIODone; + when State_ReadIODone => + if (io_busy = '0') then + state <= State_ResyncDecode; + memAWriteEnable <= '1'; + memAWrite <= (others => '0'); + memAWrite(7 downto 0) <= io_read; + memAAddr <= sp; + end if; + when State_WriteIO => + state <= State_WriteIODone; + when State_WriteIODone => + if (io_busy = '0') then + state <= State_ResyncDecode; + end if; + when State_ResyncDecode => + memAAddr <= pc(maxAddrBit downto minAddrBit); + nextPC:=pc+1; + memBAddr <= nextPC(maxAddrBit downto minAddrBit); + state <= State_ResyncStack; + when State_ResyncStack => + memAAddr <= sp; + memBAddr <= sp+1; + state <= State_Decode; + when State_AddSP => + memAAddr <= pc(maxAddrBit downto minAddrBit); + nextPC:=pc+1; + memBAddr <= nextPC(maxAddrBit downto minAddrBit); + state <= State_Add; + when State_Add => + memAWriteEnable <= '1'; + memAWrite <= memARead + memBRead; + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Decode; + when State_LoadByte1 => + memAAddr <= pc(maxAddrBit downto minAddrBit); + nextPC:=pc+1; + memBAddr <= nextPC(maxAddrBit downto minAddrBit); + state <= State_LoadByte2; + when State_LoadByte2 => + memAWriteEnable <= '1'; + memAAddr <= sp; + memAWrite <= (others => '0'); + case byteSelect is + when "00" => memAWrite(7 downto 0) <= memARead(31 downto 24); + when "01" => memAWrite(7 downto 0) <= memARead(23 downto 16); + when "10" => memAWrite(7 downto 0) <= memARead(15 downto 8); + when others => memAWrite(7 downto 0) <= memARead(7 downto 0); + end case; + memBAddr <= sp + 1; + state <= State_Decode; + when State_StoreByte1 => + state <= State_StoreByte2; + when State_StoreByte2 => + memAWriteEnable <= '1'; + memAAddr <= memBRead(maxAddrBit downto minAddrBit); + memAWrite <= memARead; + case byteSelect is + when "00" => memAWrite(31 downto 24) <= storeByte; + when "01" => memAWrite(23 downto 16) <= storeByte; + when "10" => memAWrite(15 downto 8) <= storeByte; + when others => memAWrite(7 downto 0) <= storeByte; + end case; + state <= State_ResyncDecode; + when State_Mult1 => + memAAddr <= pc(maxAddrBit downto minAddrBit); + nextPC:=pc+1; + memBAddr <= nextPC(maxAddrBit downto minAddrBit); + state <= State_Mult2; + when State_Mult2 => + memAWriteEnable <= '1'; + memAWrite <= multResult; + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Decode; + + when others => + null; + end case; + end if; + end process; + + + +end behave; diff --git a/zpu/hdl/zpu3/src/zpuio.vhd b/zpu/hdl/zpu3/src/zpuio.vhd new file mode 100644 index 0000000..96e9aea --- /dev/null +++ b/zpu/hdl/zpu3/src/zpuio.vhd @@ -0,0 +1,180 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library zylin; +use zylin.arm7.all; + +library zylin; +use zylin.zpu_config.all; +use zylin.zpupkg.all; + +entity zpuio is + port ( areset : in std_logic; + cpu_clk : in std_logic; + clk_status : in std_logic_vector(2 downto 0); + cpu_din : in std_logic_vector(15 downto 0); + cpu_a : in std_logic_vector(20 downto 0); + cpu_we : in std_logic_vector(1 downto 0); + cpu_re : in std_logic; + cpu_dout : inout std_logic_vector(15 downto 0)); +end zpuio; + +architecture behave of zpuio is + +signal timer_read : std_logic_vector(7 downto 0); +--signal timer_write : std_logic_vector(7 downto 0); +signal timer_we : std_logic; + + +signal io_busy : std_logic; +signal io_read : std_logic_vector(7 downto 0); +signal io_write : std_logic_vector(7 downto 0); +signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit); +signal io_writeEnable : std_logic; +signal io_readEnable : std_logic; + +signal din : std_logic_vector(7 downto 0); +signal dout : std_logic_vector(7 downto 0); +signal adr : std_logic_vector(15 downto 0); +signal break : std_logic; +signal we : std_logic; +signal re : std_logic; + + +-- uart forwarding... + +signal uartTXPending : std_logic; +signal uartTXCleared : std_logic; +signal uartData : std_logic_vector(7 downto 0); + +signal readingTimer : std_logic; +begin + + timerinst: timer port map ( + clk => cpu_clk, + areset => areset, + we => timer_we, + din => io_write, + adr => io_addr(4 downto 2), + dout => timer_read); + + zpu: zpu_top port map ( + clk => cpu_clk , + areset => areset, + io_busy => io_busy, + io_writeEnable => io_writeEnable, + io_readEnable => io_readEnable, + io_write => io_write, + io_read => io_read, + io_addr => io_addr, + interrupt => '0' + --, +-- break => cpu_fiq_p +); + + + -- Read/write are on different addresses + -- The registers are 8 bits and mapped to bit[7:0] + -- + -- 0xC000 Write: Writes to UART TX FIFO (4 byte FIFO) + -- Read : Reads from UART RX FIFO (4 byte FIFO) + -- 0xC004 Read : UART status register + -- Bit 0 = RX FIFO empty + -- Bit 1 = TX FIFO full + -- 0xA000 Skrive: LED's (8 stk.) + + -- 0x9000 Write: bit 0: 1= reset counter + -- 0= counter running + -- bit 1: 1= sample counter (when set to 1) + -- 0=not used + -- Read : counter bit[7:0] + -- 0x9004 Read: counter bit [15:8] + -- 0x9008 Read: counter bit [23:16] + -- 0x900C Read: counter bit [31:24] + -- 0x9010 Read: counter bit [39:32] + -- 0x9014 Read: counter bit [47:40] + -- 0x9018 Read: counter bit [55:48] + -- 0x901C Read: counter bit [63:56] + -- + -- 0x8800 Read: unsigned 8-bit integer with FPGA frequency (in MHz) + + fauxUart: + process(cpu_clk, areset) + begin + if areset = '1' then + io_busy <= '0'; + uartTXPending <= '0'; + timer_we <= '0'; + io_busy <= '1'; + uartData <= x"58"; -- 'X' + readingTimer <= '0'; + elsif (cpu_clk'event and cpu_clk = '1') then + timer_we <= '0'; + io_busy <= '1'; + if uartTXCleared = '1' then + uartTXPending <= '0'; + end if; + + if io_writeEnable = '1' then + if io_addr=x"1000" then + -- Write to UART + uartData <= io_write; + uartTXPending <= '1'; + io_busy <= '0'; + elsif io_addr(12)='1' then + timer_we <= '1'; + io_busy <= '0'; + else + report "Illegal IO write" severity failure; + end if; + end if; + if (io_readEnable = '1') then + if io_addr=x"1001" then + io_read <= (0=>'1', -- recieve empty + 1 => uartTXPending, -- tx full + others => '0'); + io_busy <= '0'; + elsif io_addr(12)='1' then + readingTimer <= '1'; + io_busy <= '1'; + elsif io_addr(11)='1' then + io_read <= ZPU_Frequency; + io_busy <= '0'; + else + report "Illegal IO read" severity failure; + end if; + + else + if (readingTimer = '1') then + readingTimer <= '0'; + io_read <= timer_read; + io_busy <= '0'; + else + io_read <= (others => '1'); + end if; + end if; + end if; + end process; + + + forwardUARTOutputToARM: + process(cpu_clk, areset) + begin + if areset = '1' then + uartTXCleared <= '0'; + elsif (cpu_clk = '1' and cpu_clk'event) then + if cpu_we(0) = '1' and cpu_a(3 downto 1) = "000" then + uartTXCleared <= cpu_din(0); + else + uartTXCleared <= uartTXCleared; + end if; + end if; + end process; + + cpu_dout(7 downto 0) <= uartData when (cpu_re = '1' and cpu_a(3 downto 1) = "001") else (others => 'Z'); + cpu_dout <= (0 => uartTXPending, others => '0') when (cpu_re = '1' and cpu_a(3 downto 1) = "000") else (others => 'Z'); + + + +end behave; diff --git a/zpu/hdl/zpu3/src/zpupkg.vhd b/zpu/hdl/zpu3/src/zpupkg.vhd new file mode 100644 index 0000000..a904b11 --- /dev/null +++ b/zpu/hdl/zpu3/src/zpupkg.vhd @@ -0,0 +1,130 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; + +library zylin; +use zylin.zpu_config.all; + +package zpupkg is + + component dualport_ram is + port (clk : in std_logic; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit); + memAWrite : in std_logic_vector(wordSize-1 downto 0); + memARead : out std_logic_vector(wordSize-1 downto 0); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit); + memBWrite : in std_logic_vector(wordSize-1 downto 0); + memBRead : out std_logic_vector(wordSize-1 downto 0)); + end component; + + + component trace is + port( + clk : in std_logic; + begin_inst : in std_logic; + pc : in std_logic_vector(maxAddrBit downto 0); + opcode : in std_logic_vector(7 downto 0); + sp : in std_logic_vector(maxAddrBit downto minAddrBit); + memA : in std_logic_vector(wordSize-1 downto 0); + memB : in std_logic_vector(wordSize-1 downto 0); + busy : in std_logic + ); + end component; + + component zpu_top is + Port ( clk : in std_logic; + areset : in std_logic; + io_busy : in std_logic; + io_read : in std_logic_vector(7 downto 0); + io_write : out std_logic_vector(7 downto 0); + io_addr : out std_logic_vector(maxAddrBit downto minAddrBit); + io_writeEnable : out std_logic; + io_readEnable : out std_logic; + interrupt : in std_logic; + break : out std_logic); + end component; + + + component timer is + port( + clk : in std_logic; + areset : in std_logic; + we : in std_logic; + din : in std_logic_vector(7 downto 0); + adr : in std_logic_vector(2 downto 0); + dout : out std_logic_vector(7 downto 0)); + end component; + + + component zpuio is + port ( areset : in std_logic; + cpu_clk : in std_logic; + clk_status : in std_logic_vector(2 downto 0); + cpu_din : in std_logic_vector(15 downto 0); + cpu_a : in std_logic_vector(20 downto 0); + cpu_we : in std_logic_vector(1 downto 0); + cpu_re : in std_logic; + cpu_dout : inout std_logic_vector(15 downto 0)); + end component; + + + -- opcode decode constants + constant OpCode_Im : std_logic_vector(7 downto 7) := "1"; + constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010"; + constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011"; + constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001"; + constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001"; + constant OpCode_Short : std_logic_vector(7 downto 4) := "0000"; + + constant OpCode_Break : std_logic_vector(3 downto 0) := "0000"; + constant OpCode_Shiftleft: std_logic_vector(3 downto 0) := "0001"; + constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010"; + constant OpCode_PushInt : std_logic_vector(3 downto 0) := "0011"; + + constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100"; + constant OpCode_Add : std_logic_vector(3 downto 0) := "0101"; + constant OpCode_And : std_logic_vector(3 downto 0) := "0110"; + constant OpCode_Or : std_logic_vector(3 downto 0) := "0111"; + + constant OpCode_Load : std_logic_vector(3 downto 0) := "1000"; + constant OpCode_Not : std_logic_vector(3 downto 0) := "1001"; + constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010"; + constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011"; + + constant OpCode_Store : std_logic_vector(3 downto 0) := "1100"; + constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101"; + constant OpCode_Compare : std_logic_vector(3 downto 0) := "1110"; + constant OpCode_PopInt : std_logic_vector(3 downto 0) := "1111"; + + constant OpCode_Lessthan : std_logic_vector(5 downto 0) := conv_std_logic_vector(36, 6); + constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := conv_std_logic_vector(37, 6); + constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := conv_std_logic_vector(38, 6); + constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := conv_std_logic_vector(39, 6); + + constant OpCode_Swap : std_logic_vector(5 downto 0) := conv_std_logic_vector(40, 6); + + constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := conv_std_logic_vector(42, 6); + constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := conv_std_logic_vector(43, 6); + constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := conv_std_logic_vector(44, 6); + + constant OpCode_Eq : std_logic_vector(5 downto 0) := conv_std_logic_vector(46, 6); + constant OpCode_Neq : std_logic_vector(5 downto 0) := conv_std_logic_vector(47, 6); + + constant OpCode_Sub : std_logic_vector(5 downto 0) := conv_std_logic_vector(49, 6); + constant OpCode_Loadb : std_logic_vector(5 downto 0) := conv_std_logic_vector(51, 6); + constant OpCode_Storeb : std_logic_vector(5 downto 0) := conv_std_logic_vector(52, 6); + + constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := conv_std_logic_vector(55, 6); + constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := conv_std_logic_vector(56, 6); + + constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := conv_std_logic_vector(61, 6); + constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := conv_std_logic_vector(62, 6); + constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := conv_std_logic_vector(63, 6); + + + + constant OpCode_Size : integer := 8; + +end zpupkg; diff --git a/zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7pkg.vhd b/zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7pkg.vhd new file mode 100644 index 0000000..95fbc18 --- /dev/null +++ b/zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7pkg.vhd @@ -0,0 +1,31 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +package arm7 is + + component arm7wb + generic( + simulate_io_time : boolean := false); + port ( areset : in std_logic; + cpu_clk : in std_logic; + cpu_clk_2x : in std_logic; + cpu_a_p : in std_logic_vector(20 downto 0); + cpu_wr_n_p : in std_logic_vector(1 downto 0); + cpu_cs_n_p : in std_logic_vector(3 downto 1); + cpu_oe_n_p : in std_logic; + cpu_d_p : inout std_logic_vector(15 downto 0); + cpu_irq_p : out std_logic_vector(1 downto 0); + cpu_fiq_p : out std_logic; + cpu_wait_n_p : out std_logic; + + cpu_din : out std_logic_vector(15 downto 0); + cpu_a : out std_logic_vector(20 downto 0); + cpu_we : out std_logic_vector(1 downto 0); + cpu_re : out std_logic; + cpu_dout : in std_logic_vector(15 downto 0)); + end component; + +end arm7; + + \ No newline at end of file diff --git a/zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7wb.vhd b/zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7wb.vhd new file mode 100644 index 0000000..55b8125 --- /dev/null +++ b/zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7wb.vhd @@ -0,0 +1,213 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity arm7wb is + generic( + simulate_io_time : boolean := false); + port ( areset : in std_logic; + cpu_clk : in std_logic; + cpu_clk_2x : in std_logic; + cpu_a_p : in std_logic_vector(20 downto 0); + cpu_wr_n_p : in std_logic_vector(1 downto 0); + cpu_cs_n_p : in std_logic_vector(3 downto 1); + cpu_oe_n_p : in std_logic; + cpu_d_p : inout std_logic_vector(15 downto 0); + cpu_irq_p : out std_logic_vector(1 downto 0); + cpu_fiq_p : out std_logic; + cpu_wait_n_p : out std_logic; + + cpu_din : out std_logic_vector(15 downto 0); + cpu_a : out std_logic_vector(20 downto 0); + cpu_we : out std_logic_vector(1 downto 0); + cpu_re : out std_logic; + cpu_dout : in std_logic_vector(15 downto 0)); +end arm7wb; + +architecture behave of arm7wb is + +attribute keep : string; + +signal cpu_oe_n : std_logic; +signal cpu_fiq : std_logic; +signal cpu_wait_n : std_logic; +signal cpu_clk_toggle : std_logic; +signal cpu_clk_smp1 : std_logic; +signal cpu_clk_smp2 : std_logic; +signal cpu_clk_phase : std_logic; +signal cpu_oe_n_del : std_logic; +signal cpu_a_smp : std_logic_vector(20 downto 0); +signal cpu_d_smp : std_logic_vector(15 downto 0); + +signal int_oe_n : std_logic_vector(15 downto 0); +attribute keep of int_oe_n:signal is "true"; + +signal cpu_irq : std_logic_vector(1 downto 0); +signal cpu_wr_n : std_logic_vector(1 downto 0); +signal cpu_cs_n : std_logic_vector(3 downto 1); + +signal dout : std_logic_vector(15 downto 0); +signal cpu_d_p_out : std_logic_vector(15 downto 0); +signal read_cnt : std_logic_vector(1 downto 0); + +signal cpu_wr_n_p_del : std_logic_vector(1 downto 0); +signal cpu_a_p_del : std_logic_vector(20 downto 0); +signal cpu_d_p_del : std_logic_vector(15 downto 0); +signal cpu_cs_n_p_del : std_logic_vector(3 downto 1); +signal cpu_oe_n_p_del : std_logic; + +constant Sim_Delay : time := 0.5 ns; +constant Clock_2_Out : time := 5.5 ns; +constant Input_Setup : time := 2.5 ns; + +begin + + cpu_wait_n <= '1'; + cpu_fiq <= '1'; + cpu_irq <= "11"; + + iotimingon: + if simulate_io_time generate + begin + cpu_wr_n_p_del <= "XX" after 0 ns, cpu_wr_n_p after Input_Setup; + cpu_a_p_del <= "XXXXXXXXXXXXXXXXXXXXX" after 0 ns, cpu_a_p after Input_Setup; + cpu_d_p_del <= "XXXXXXXXXXXXXXXX" after 0 ns, cpu_d_p after Input_Setup; + cpu_cs_n_p_del <= "XXX" after 0 ns, cpu_cs_n_p after Input_Setup; + cpu_oe_n_p_del <= 'X' after 0 ns, cpu_oe_n_p after Input_Setup; + end generate; + + iotimingoff: + if not simulate_io_time generate + begin + cpu_wr_n_p_del <= cpu_wr_n_p; + cpu_a_p_del <= cpu_a_p; + cpu_d_p_del <= cpu_d_p; + cpu_cs_n_p_del <= cpu_cs_n_p; + cpu_oe_n_p_del <= cpu_oe_n_p; + end generate; + + process(cpu_clk, areset) -- Toggle FF with 1x clock to find phase + begin + if areset = '1' then + cpu_clk_toggle <= '0'; + elsif (cpu_clk'event and cpu_clk = '1') then + cpu_clk_toggle <= not(cpu_clk_toggle); + end if; + end process; + + process(cpu_clk_2x, areset) -- Find phase relationsship between 1x and 2x clock + begin + if areset = '1' then + cpu_clk_smp1 <= '0'; + cpu_clk_smp2 <= '1'; + cpu_clk_phase <= '0'; + elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then + cpu_clk_smp1 <= cpu_clk_toggle; + cpu_clk_smp2 <= cpu_clk_smp1; + if cpu_clk_smp1 = '1' and cpu_clk_smp2 = '0' then + cpu_clk_phase <= '0' after Sim_Delay; + else + cpu_clk_phase <= not(cpu_clk_phase) after Sim_Delay; + end if; + end if; + end process; + + process(cpu_clk_2x, areset) -- Sample input signals + begin + if areset = '1' then + cpu_oe_n <= '1'; + cpu_a_smp <= "000000000000000000000"; + cpu_d_smp <= "0000000000000000"; + cpu_wr_n <= "11"; + cpu_cs_n <= "111"; + elsif (cpu_clk_2x = '1' and cpu_clk_2x'event) then + cpu_oe_n <= cpu_oe_n_p_del after Sim_Delay; + cpu_a_smp <= cpu_a_p_del after Sim_Delay; + cpu_d_smp <= cpu_d_p_del after Sim_Delay; + cpu_wr_n <= cpu_wr_n_p_del after Sim_Delay; + cpu_cs_n <= cpu_cs_n_p_del after Sim_Delay; + end if; + end process; + + cpu_d_out: + for i in 0 to 15 generate + begin + process(cpu_clk_2x, areset) + begin + if areset = '1' then + cpu_d_p(i) <= 'Z'; + elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then + if int_oe_n(i) = '0' then + cpu_d_p(i) <= cpu_d_p_out(i) after Clock_2_Out; + else + cpu_d_p(i) <= 'Z' after Clock_2_Out; + end if; + end if; + end process; + end generate; + + process(cpu_clk, areset) -- Clocked output pins + begin + if areset = '1' then + cpu_d_p_out <= "1111111111111111"; + cpu_wait_n_p <= '1'; + cpu_irq_p <= "11"; + cpu_fiq_p <= '1'; + elsif (cpu_clk = '1' and cpu_clk'event) then + cpu_d_p_out <= cpu_dout; + cpu_wait_n_p <= '1'; + cpu_irq_p <= "11"; + cpu_fiq_p <= '1'; + end if; + end process; + + process(cpu_clk, areset) -- Generate control signals + begin + if areset = '1' then + int_oe_n <= "1111111111111111"; + read_cnt <= "00"; + cpu_we <= "00"; + cpu_re <= '0'; + cpu_a <= "000000000000000000000"; + cpu_din <= "0000000000000000"; + elsif (cpu_clk = '1' and cpu_clk'event) then + + cpu_a <= cpu_a_smp; + cpu_din <= cpu_d_smp; + + cpu_oe_n_del <= cpu_oe_n; + + if cpu_cs_n(1) = '1' then + read_cnt <= "00"; + else + read_cnt <= read_cnt + '1'; + end if; + + if read_cnt = "01" and cpu_cs_n(1) = '0' and cpu_wr_n(0) = '0' then + cpu_we(0) <= '1'; + else + cpu_we(0) <= '0'; + end if; + + if read_cnt = "01" and cpu_cs_n(1) = '0' and cpu_wr_n(1) = '0' then + cpu_we(1) <= '1'; + else + cpu_we(1) <= '0'; + end if; + + if read_cnt = "00" and cpu_cs_n(1) = '0' and cpu_oe_n = '0' then + cpu_re <= '1'; + else + cpu_re <= '0'; + end if; + + if read_cnt = "01" and cpu_cs_n(1) = '0' and cpu_oe_n = '0' then + int_oe_n <= "0000000000000000"; + else + int_oe_n <= "1111111111111111"; + end if; + + end if; + end process; + +end behave; diff --git a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_tb.do b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_tb.do new file mode 100644 index 0000000..d2c22cf --- /dev/null +++ b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_tb.do @@ -0,0 +1,17 @@ +vlib zylin +vcom -93 -explicit -work zylin ../ddrsdram/src/ddr_pkg.vhd +vcom -93 -explicit -work zylin ../ddrsdram/src/ddr_top.vhd +vcom -93 -explicit -work zylin ../ddrsdram/src/mt46v16m16.vhd +vcom -93 -explicit -work zylin ../ddrsdram/src/ddr_tb.vhd +vlib work +vsim -t 1ps zylin.ddr_tb +view wave +view signals +radix hex +add wave * +add wave sim:/ddr_tb/ddr_ctrl/* +force -freeze sim:/ddr_tb/areset 1 0 +run 10 ns +force -freeze sim:/ddr_tb/areset 0 0 +when sim:/ddr_tb/break_out stop +run 10 ms \ No newline at end of file diff --git a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_top.do b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_top.do new file mode 100644 index 0000000..31dd294 --- /dev/null +++ b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_top.do @@ -0,0 +1,111 @@ +vlib zylin +vcom -93 -explicit -work zylin ../ddrsdram/src/ddr_pkg.vhd +vcom -93 -explicit -work zylin ../ddrsdram/src/ddr_top.vhd +vlib work +vsim -t 1ps zylin.ddr_top +view wave +view signals +radix hex +# Add wave signals + +add wave -divider "System" +add wave sim:/ddr_top/areset +add wave sim:/ddr_top/cpu_clk +add wave sim:/ddr_top/cpu_clk_2x +add wave sim:/ddr_top/cpu_clk_4x +add wave sim:/ddr_top/ddr_in_clk +add wave sim:/ddr_top/ddr_in_clk_2x + +add wave -divider "Ctrl interface" +add wave sim:/ddr_top/cpu_clk +add wave sim:/ddr_top/ddr_data_read +add wave sim:/ddr_top/ddr_data_write +add wave sim:/ddr_top/ddr_req +add wave sim:/ddr_top/ddr_rd_wr_n +add wave sim:/ddr_top/ddr_req_len +add wave sim:/ddr_top/ddr_wr_mask +add wave sim:/ddr_top/ddr_read_en +add wave sim:/ddr_top/ddr_write_en +add wave sim:/ddr_top/ddr_command +add wave sim:/ddr_top/ddr_command_we + +add wave -divider "DDR interface" +add wave sim:/ddr_top/sdr_clk_p +add wave sim:/ddr_top/sdr_clk_n_p +add wave sim:/ddr_top/cke_q_p +add wave sim:/ddr_top/cs_qn_p +add wave sim:/ddr_top/ras_qn_p +add wave sim:/ddr_top/cas_qn_p +add wave sim:/ddr_top/we_qn_p +add wave sim:/ddr_top/dm_q_p +add wave sim:/ddr_top/dqs_q_p +add wave sim:/ddr_top/ba_q_p +add wave sim:/ddr_top/sdr_a_p +add wave sim:/ddr_top/sdr_d_p + +add wave -divider "Internal signals" +add wave sim:/ddr_top/clk2_phase +add wave sim:/ddr_top/clk4_phase +add wave sim:/ddr_top/ddr_state +add wave sim:/ddr_top/sdr_oe_n +add wave sim:/ddr_top/sdr_smp +add wave sim:/ddr_top/sdr_d + + +# Add input signals +force -freeze sim:/ddr_top/cpu_clk_4x 1 0, 0 {1.875 ns} -r 3.75 +run 100 ps +force -freeze sim:/ddr_top/cpu_clk_2x 1 0, 0 {3.75 ns} -r 7.5 +run 100 ps +force -freeze sim:/ddr_top/cpu_clk 1 0, 0 {7.5 ns} -r 15 +force -freeze sim:/ddr_top/ddr_in_clk 1 2ns, 0 {5.75 ns} -r 7.5 +force -freeze sim:/ddr_top/ddr_in_clk_2x 0 0.125ns, 1 {2 ns} -r 3.75 + +force -freeze sim:/ddr_top/areset 1 0 +force -freeze sim:/ddr_top/ddr_command 0000 0 +force -freeze sim:/ddr_top/ddr_command_we 0 0 +force -freeze sim:/ddr_top/ddr_data_write 1234abcd 0 +force -freeze sim:/ddr_top/ddr_req 0 0 +force -freeze sim:/ddr_top/ddr_req_adr 000000 0 +force -freeze sim:/ddr_top/ddr_rd_wr_n 0 0 +force -freeze sim:/ddr_top/ddr_req_len 000 0 +force -freeze sim:/ddr_top/ddr_wr_mask 0 0 + +# Start simulation +run 45 +force -freeze sim:/ddr_top/areset 0 0 +run 92 +# DDR Command +force -freeze sim:/ddr_top/ddr_command 000A 0 +force -freeze sim:/ddr_top/ddr_command_we 1 0 +run 15 +force -freeze sim:/ddr_top/ddr_command 0000 0 +force -freeze sim:/ddr_top/ddr_command_we 0 0 +run 90 +# DDR Read +force -freeze sim:/ddr_top/ddr_req 1 0 +force -freeze sim:/ddr_top/ddr_req_adr 00ABCD 0 +force -freeze sim:/ddr_top/ddr_rd_wr_n 1 0 +force -freeze sim:/ddr_top/ddr_req_len 000 0 +force -freeze sim:/ddr_top/ddr_wr_mask 0 0 +run 15 +force -freeze sim:/ddr_top/ddr_req 0 0 +force -freeze sim:/ddr_top/ddr_req_adr 000000 0 +force -freeze sim:/ddr_top/ddr_rd_wr_n 0 0 +force -freeze sim:/ddr_top/ddr_req_len 000 0 +force -freeze sim:/ddr_top/ddr_wr_mask 0 0 +run 150 +# DDR Write +force -freeze sim:/ddr_top/ddr_req 1 0 +force -freeze sim:/ddr_top/ddr_req_adr 00ABCD 0 +force -freeze sim:/ddr_top/ddr_rd_wr_n 0 0 +force -freeze sim:/ddr_top/ddr_req_len 000 0 +force -freeze sim:/ddr_top/ddr_wr_mask 0 0 +run 15 +force -freeze sim:/ddr_top/ddr_req 0 0 +force -freeze sim:/ddr_top/ddr_req_adr 000000 0 +force -freeze sim:/ddr_top/ddr_rd_wr_n 0 0 +force -freeze sim:/ddr_top/ddr_req_len 000 0 +force -freeze sim:/ddr_top/ddr_wr_mask 0 0 +run 180 + diff --git a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_pkg.vhd b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_pkg.vhd new file mode 100644 index 0000000..95f4b8a --- /dev/null +++ b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_pkg.vhd @@ -0,0 +1,90 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +package ddr is + + component ddr_top + generic( + simulate_io_time : boolean := false); + port ( -- Asyncronous reset and clocks + areset : in std_logic; + cpu_clk : in std_logic; + cpu_clk_2x : in std_logic; + cpu_clk_4x : in std_logic; + ddr_in_clk : in std_logic; + ddr_in_clk_2x : in std_logic; + + -- Command interface + ddr_command : in std_logic_vector(15 downto 0); + ddr_command_we : in std_logic; + refresh_en : in std_logic; + + + -- Data interface signals + ddr_data_read : out std_logic_vector(31 downto 0); -- Data read from DDR SDRAM + ddr_data_write : in std_logic_vector(35 downto 0); -- Data to be written to DDR SDRAM + ddr_req_adr : in std_logic_vector(23 downto 1); -- Request address + ddr_req : in std_logic; -- Request DDR SDRAM access + ddr_req_ack : out std_logic; -- Request acknowledge + ddr_busy : out std_logic; -- Request acknowledge + ddr_rd_wr_n : in std_logic; -- Access type 1=READ, 0=WRITE + ddr_req_len : in std_logic; -- Number of 16-bits words to transfer (0=2, 1=8) + ddr_read_en : out std_logic; -- Enable signal for read data + ddr_write_en : out std_logic; -- Enable (read) signal for data write + + -- DDR SDRAM Signals + sdr_clk_p : out std_logic; -- ddr_sdram_clock + sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock + cke_q_p : out std_logic; -- clock enable + cs_qn_p : out std_logic; -- /chip select + ras_qn_p : inout std_logic; -- /ras + cas_qn_p : inout std_logic; -- /cas + we_qn_p : inout std_logic; -- /write enable + dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00" + dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write + ba_q_p : out std_logic_vector(1 downto 0); -- bank select + sdr_a_p : out std_logic_vector(12 downto 0); -- address bus + sdr_d_p : inout std_logic_vector(15 downto 0)); -- bidir data bus + end component; + + component MT46V16M16 + GENERIC ( -- Timing for -75Z CL2 + tCK : TIME := 7.500 ns; + tCH : TIME := 3.375 ns; -- 0.45*tCK + tCL : TIME := 3.375 ns; -- 0.45*tCK + tDH : TIME := 0.500 ns; + tDS : TIME := 0.500 ns; + tIH : TIME := 0.900 ns; + tIS : TIME := 0.900 ns; + tMRD : TIME := 15.000 ns; + tRAS : TIME := 40.000 ns; + tRAP : TIME := 20.000 ns; + tRC : TIME := 65.000 ns; + tRFC : TIME := 75.000 ns; + tRCD : TIME := 20.000 ns; + tRP : TIME := 20.000 ns; + tRRD : TIME := 15.000 ns; + tWR : TIME := 15.000 ns; + addr_bits : INTEGER := 13; + data_bits : INTEGER := 16; + cols_bits : INTEGER := 9 + ); + PORT ( + Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); + Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ"; + Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + Clk : IN STD_LOGIC; + Clk_n : IN STD_LOGIC; + Cke : IN STD_LOGIC; + Cs_n : IN STD_LOGIC; + Ras_n : IN STD_LOGIC; + Cas_n : IN STD_LOGIC; + We_n : IN STD_LOGIC; + Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) + ); + end component; + +end ddr; + \ No newline at end of file diff --git a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_tb.vhd b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_tb.vhd new file mode 100644 index 0000000..5666532 --- /dev/null +++ b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_tb.vhd @@ -0,0 +1,301 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library zylin; +use zylin.ddr.all; + +entity ddr_tb is + port ( areset : in std_logic; + break_out : out std_logic); +end ddr_tb; + +architecture behave of ddr_tb is + +signal cpu_clk : std_logic; +signal cpu_clk_2x : std_logic; +signal cpu_clk_4x : std_logic; +signal ddr_in_clk : std_logic; +signal ddr_in_clk_2x : std_logic; + +signal ddr_command : std_logic_vector(15 downto 0); +signal ddr_command_we : std_logic; + +signal ddr_data_read : std_logic_vector(31 downto 0); -- Data read from DDR SDRAM +signal ddr_data_write : std_logic_vector(35 downto 0); -- Data to be written to DDR SDRAM +signal ddr_req_adr : std_logic_vector(23 downto 1); -- Request address +signal ddr_req : std_logic; -- Request DDR SDRAM access +signal ddr_req_ack : std_logic; -- Request acknowledge +signal ddr_busy : std_logic; -- Request acknowledge +signal ddr_rd_wr_n : std_logic; -- Access type 1=READ, 0=WRITE +signal ddr_req_len : std_logic; -- Number of 16-bits words to transfer +signal ddr_read_en : std_logic; -- Enable signal for read data +signal ddr_write_en : std_logic; -- Enable (read) signal for data write +signal refresh_en : std_logic; + +signal sdr_clk_p : std_logic; -- ddr_sdram_clock +signal sdr_clk_n_p : std_logic; -- /ddr_sdram_clock +signal cke_q_p : std_logic; -- clock enable +signal cs_qn_p : std_logic; -- /chip select +signal ras_qn_p : std_logic; -- /ras +signal cas_qn_p : std_logic; -- /cas +signal we_qn_p : std_logic; -- /write enable +signal dm_q_p : std_logic_vector(1 downto 0); -- data mask bits, set to "00" +signal dqs_q_p : std_logic_vector(1 downto 0); -- data strobe, only for write +signal ba_q_p : std_logic_vector(1 downto 0); -- bank select +signal sdr_a_p : std_logic_vector(12 downto 0); -- address bus +signal sdr_d_p : std_logic_vector(15 downto 0); -- bidir data bus + +constant min_time : time := 1.875 ns; + +begin + + clock1: + process + begin + loop + cpu_clk_4x <= '1'; + wait for min_time; + cpu_clk_4x <= '0'; + wait for min_time; + end loop; + end process; + + clock2: + process + begin + loop + cpu_clk_2x <= '1' after 100 ps; + wait until rising_edge(cpu_clk_4x); + cpu_clk_2x <= '0' after 100 ps; + wait until rising_edge(cpu_clk_4x); + end loop; + end process; + + clock3: + process + begin + loop + cpu_clk <= '1' after 100 ps; + wait until rising_edge(cpu_clk_2x); + cpu_clk <= '0' after 100 ps; + wait until rising_edge(cpu_clk_2x); + end loop; + end process; + + ddr_in_clk_2x <= cpu_clk_4x after 1 ns; + + clock4: + process + begin + loop + ddr_in_clk <= '0' after 100 ps; + wait until rising_edge(ddr_in_clk_2x); + ddr_in_clk <= '1' after 100 ps; + wait until rising_edge(ddr_in_clk_2x); + end loop; + end process; + + inputdata: + process + begin + -- Wait until global reset released + loop + ddr_command <= x"0000"; + ddr_command_we <= '0'; + ddr_data_write <= x"000000000"; + ddr_req <= '0'; + ddr_req_adr <= "00000000000000000000000"; + ddr_rd_wr_n <= '0'; + ddr_req_len <= '0'; + break_out <= '0'; + refresh_en <= '0'; + + wait until falling_edge(areset); + + -- DDR initialization sequence + -- Wait more than 200 us + wait for 201000 ns; + + -- Send precharge command + wait until rising_edge(cpu_clk); + ddr_command <= x"8000"; + ddr_command_we <= '1'; + wait until rising_edge(cpu_clk); + ddr_command <= x"0000"; + ddr_command_we <= '0'; + + -- Wait for 1 us + wait for 1000 ns; + + -- Load extended mode register + -- Enable DLL + -- Normal drive strength + wait until rising_edge(cpu_clk); + ddr_command <= x"2000"; + ddr_command_we <= '1'; + wait until rising_edge(cpu_clk); + ddr_command <= x"0000"; + ddr_command_we <= '0'; + + -- Wait for 1 us + wait for 1000 ns; + + -- Load mode register + -- Burst length: 2 + -- Burst type: Sequential + -- Cas latency: 2 + -- Reset DLL + wait until rising_edge(cpu_clk); + ddr_command <= x"0121"; + ddr_command_we <= '1'; + wait until rising_edge(cpu_clk); + ddr_command <= x"0000"; + ddr_command_we <= '0'; + + -- Wait for 1 us + wait for 1000 ns; + + -- Send precharge command + wait until rising_edge(cpu_clk); + ddr_command <= x"8000"; + ddr_command_we <= '1'; + wait until rising_edge(cpu_clk); + ddr_command <= x"0000"; + ddr_command_we <= '0'; + + -- Enable refresh + refresh_en <= '1'; + + -- Wait 30 us (minimum 2 autorefresh cycles) + wait for 30000 ns; + + -- Load mode register + -- Burst length: 2 + -- Burst type: Sequential + -- Cas latency: 2 + -- Deactivate Reset DLL + wait until rising_edge(cpu_clk); + ddr_command <= x"0021"; + ddr_command_we <= '1'; + wait until rising_edge(cpu_clk); + ddr_command <= x"0000"; + ddr_command_we <= '0'; + + -- Wait for 2 us (DLL stable) + wait for 2000 ns; + + -- Write data to DDR + wait until rising_edge(cpu_clk_2x); + ddr_data_write <= x"312345678"; + ddr_req <= '1'; + ddr_req_adr <= "00000000000000000000000"; + ddr_rd_wr_n <= '0'; + ddr_req_len <= '0'; + wait until rising_edge(ddr_write_en); + wait until rising_edge(cpu_clk_2x); + ddr_req <= '0'; + ddr_req_adr <= "00000000000000000000000"; + ddr_rd_wr_n <= '0'; + ddr_req_len <= '0'; + ddr_data_write <= x"000000000"; + wait for 100 ns; + + -- Read data from DDR + wait until rising_edge(cpu_clk_2x); + ddr_req <= '1'; + ddr_req_adr <= "00000000000000000000000"; + ddr_rd_wr_n <= '1'; + ddr_req_len <= '0'; + wait until rising_edge(ddr_req_ack); + wait until rising_edge(cpu_clk_2x); + ddr_req <= '0'; + ddr_req_adr <= "00000000000000000000000"; + ddr_rd_wr_n <= '0'; + ddr_req_len <= '0'; + ddr_data_write <= x"000000000"; + + + + wait for 100 ns; + break_out <= '1'; + wait for 100 ns; + + end loop; + + end process; + + ddr_ctrl: + ddr_top port map( + areset => areset, + cpu_clk => cpu_clk, + cpu_clk_2x => cpu_clk_2x, + cpu_clk_4x => cpu_clk_4x, + ddr_in_clk => ddr_in_clk, + ddr_in_clk_2x => ddr_in_clk_2x, + + -- Command interface + ddr_command => ddr_command, + ddr_command_we => ddr_command_we, + refresh_en => refresh_en, + + -- Data interface signals + ddr_data_read => ddr_data_read, + ddr_data_write => ddr_data_write, + ddr_req_adr => ddr_req_adr, + ddr_req => ddr_req, + ddr_req_ack => ddr_req_ack, + ddr_busy => ddr_busy, + ddr_rd_wr_n => ddr_rd_wr_n, + ddr_req_len => ddr_req_len, + ddr_read_en => ddr_read_en, + ddr_write_en => ddr_write_en, + -- DDR SDRAM Signals + sdr_clk_p => sdr_clk_p, + sdr_clk_n_p => sdr_clk_n_p, + cke_q_p => cke_q_p, + cs_qn_p => cs_qn_p, + ras_qn_p => ras_qn_p, + cas_qn_p => cas_qn_p, + we_qn_p => we_qn_p, + dm_q_p => dm_q_p, + dqs_q_p => dqs_q_p, + ba_q_p => ba_q_p, + sdr_a_p => sdr_a_p, + sdr_d_p => sdr_d_p); + + myram: + MT46V16M16 generic map( + tCK => 7.500 ns, + tCH => 3.375 ns, -- 0.45*tCK + tCL => 3.375 ns, -- 0.45*tCK + tDH => 0.500 ns, + tDS => 0.500 ns, + tIH => 0.900 ns, + tIS => 0.900 ns, + tMRD => 15.000 ns, + tRAS => 40.000 ns, + tRAP => 20.000 ns, + tRC => 65.000 ns, + tRFC => 75.000 ns, + tRCD => 20.000 ns, + tRP => 20.000 ns, + tRRD => 15.000 ns, + tWR => 15.000 ns, + addr_bits => 13, + data_bits => 16, + cols_bits => 9) + port map( + Dq => sdr_d_p, + Dqs => dqs_q_p, + Addr => sdr_a_p, + Ba => ba_q_p, + Clk => sdr_clk_p, + Clk_n => sdr_clk_n_p, + Cke => cke_q_p, + Cs_n => cs_qn_p, + Ras_n => ras_qn_p, + Cas_n => cas_qn_p, + We_n => we_qn_p, + Dm => dm_q_p); + +end behave; diff --git a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_top.vhd b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_top.vhd new file mode 100644 index 0000000..d5e98e1 --- /dev/null +++ b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_top.vhd @@ -0,0 +1,660 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity ddr_top is + generic( + simulate_io_time : boolean := false); + port ( -- Asyncronous reset and clocks + areset : in std_logic; + cpu_clk : in std_logic; + cpu_clk_2x : in std_logic; + cpu_clk_4x : in std_logic; + ddr_in_clk : in std_logic; + ddr_in_clk_2x : in std_logic; + + -- Command interface + ddr_command : in std_logic_vector(15 downto 0); + ddr_command_we : in std_logic; + refresh_en : in std_logic; + + -- Data interface signals + ddr_data_read : out std_logic_vector(31 downto 0); -- Data read from DDR SDRAM + ddr_data_write : in std_logic_vector(35 downto 0); -- Data to be written to DDR SDRAM + ddr_req_adr : in std_logic_vector(23 downto 1); -- Request address + ddr_req : in std_logic; -- Request DDR SDRAM access + ddr_req_ack : out std_logic; -- Request acknowledge + ddr_busy : out std_logic; -- Request acknowledge + ddr_rd_wr_n : in std_logic; -- Access type 1=READ, 0=WRITE + ddr_req_len : in std_logic; -- Number of 16-bits words to transfer (0=2, 1=8) + ddr_read_en : out std_logic; -- Enable signal for read data + ddr_write_en : out std_logic; -- Enable (read) signal for data write + + -- DDR SDRAM Signals + sdr_clk_p : out std_logic; -- ddr_sdram_clock + sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock + cke_q_p : out std_logic; -- clock enable + cs_qn_p : out std_logic; -- /chip select + ras_qn_p : inout std_logic; -- /ras + cas_qn_p : inout std_logic; -- /cas + we_qn_p : inout std_logic; -- /write enable + dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00" + dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write + ba_q_p : out std_logic_vector(1 downto 0); -- bank select + sdr_a_p : out std_logic_vector(12 downto 0); -- address bus + sdr_d_p : inout std_logic_vector(15 downto 0)); -- bidir data bus +end ddr_top; + +architecture behave of ddr_top is + +attribute keep : string; + +signal cpu_clk_tog : std_logic; +signal ddr_cmd : std_logic_vector(15 downto 0); +signal ddr_cmd_we_smp : std_logic; +signal new_command : std_logic; + +signal cpu_clk_2x_smp1 : std_logic; +signal cpu_clk_2x_smp2 : std_logic; +signal cpu_clk_4x_smp1 : std_logic; +signal cpu_clk_4x_smp2 : std_logic; + +signal clk2_phase : std_logic; +signal clk4_phase : std_logic_vector(3 downto 0); +signal clk4_phase_short : std_logic_vector(1 downto 0); + +signal ddr_clk_tog : std_logic; +signal ddr_clk_smp1 : std_logic; +signal ddr_clk_smp2 : std_logic; +signal ddr_clk_phase : std_logic; + +signal smp_req_adr : std_logic_vector(23 downto 1); +signal smp_req_type : std_logic; +signal smp_req_len : std_logic; +signal ddr_write_en_int : std_logic; +signal ddr_read_en_int : std_logic; + +signal dqs_q : std_logic_vector(1 downto 0); +signal dqs_oe_n : std_logic_vector(1 downto 0); +attribute keep of dqs_oe_n:signal is "true"; +signal cas_qn : std_logic; +signal ras_qn : std_logic; +signal we_qn : std_logic; +signal ba_q : std_logic_vector(1 downto 0); +signal sdr_clk : std_logic; +signal sdr_clk_n : std_logic; +signal sdr_a : std_logic_vector(12 downto 0); +signal sdr_d : std_logic_vector(15 downto 0); +signal sdr_smp : std_logic_vector(35 downto 0); +signal sdr_oe_n : std_logic_vector(15 downto 0); +attribute keep of sdr_oe_n:signal is "true"; +signal sdr_oe_ctrl : std_logic; +signal sdr_wr_msw : std_logic_vector(17 downto 0); +attribute keep of sdr_wr_msw:signal is "true"; +signal dm_q : std_logic_vector(1 downto 0); + +signal cas_n_smp : std_logic; +signal ras_n_smp : std_logic; +signal we_n_smp : std_logic; +signal read_start_sig : std_logic; +signal sdr_d_in : std_logic_vector(15 downto 0); +signal read_time_cnt : std_logic_vector(1 downto 0); +signal read_input_en : std_logic; +signal ddr_data_read_int : std_logic_vector(31 downto 0); + +signal refresh_pend : std_logic; +signal refresh_end : std_logic; +signal refresh_cnt : std_logic_vector(9 downto 0); +signal refresh_wait_cnt : std_logic_vector(2 downto 0); +signal refresh_wait_end : std_logic; + +signal cas_qn_p_del : std_logic; +signal ras_qn_p_del : std_logic; +signal we_qn_p_del : std_logic; +signal sdr_d_p_del : std_logic_vector(15 downto 0); + +type state_type is (idle, act, act_nop1, act_nop2, rd_wr, rd_nop1, + rd_nop2, pre, pre_nop1, pre_nop2, wr_nop1, wr_nop2, + wr_nop3, cmd, cpu_pre, refresh, refresh_wait); +signal ddr_state : state_type; + +constant Clk_to_Output : time := 2.2 ns; +constant Sim_Delay : time := 0.5 ns; +constant Input_Setup : time := 2.5 ns; + +constant Refresh_Interval : std_logic_vector(9 downto 0) := "1111100110"; + +begin + + iotimingon: + if simulate_io_time generate + begin + cas_qn_p_del <= 'X' after 0 ns, cas_qn_p after Input_Setup; + ras_qn_p_del <= 'X' after 0 ns, ras_qn_p after Input_Setup; + we_qn_p_del <= 'X' after 0 ns, we_qn_p after Input_Setup; + sdr_d_p_del <= "XXXXXXXXXXXXXXXX" after 0 ns, sdr_d_p after Input_Setup; + end generate; + + iotimingoff: + if not simulate_io_time generate + begin + cas_qn_p_del <= cas_qn_p; + ras_qn_p_del <= ras_qn_p; + we_qn_p_del <= we_qn_p; + sdr_d_p_del <= sdr_d_p; + end generate; + + ddr_write_en <= ddr_write_en_int; + ddr_read_en <= ddr_read_en_int; + ddr_data_read <= ddr_data_read_int; + + process(cpu_clk, areset) -- Toggle a flip-flop with cpu_clk, in order + begin -- to find phase relation with 2x and 4x clocks + if areset = '1' then + cpu_clk_tog <= '0'; + elsif (cpu_clk'event and cpu_clk = '1') then + cpu_clk_tog <= not(cpu_clk_tog) after Sim_Delay; + end if; + end process; + + process(cpu_clk_2x, areset) -- Find phase relation between cpu_clk and cpu_clk_2x + begin + if areset = '1' then + cpu_clk_2x_smp1 <= '0'; + cpu_clk_2x_smp2 <= '0'; + clk2_phase <= '0'; + elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then + cpu_clk_2x_smp1 <= cpu_clk_tog after Sim_Delay; + cpu_clk_2x_smp2 <= cpu_clk_2x_smp1 after Sim_Delay; + if (cpu_clk_2x_smp1 = '1' and cpu_clk_2x_smp2 = '0') then + clk2_phase <= '0' after Sim_Delay; + else + clk2_phase <= not(clk2_phase) after Sim_Delay; + end if; + end if; + end process; + + process(cpu_clk_4x, areset) -- Find phase relation between cpu_clk and cpu_clk_4x + begin + if areset = '1' then + cpu_clk_4x_smp1 <= '0'; + cpu_clk_4x_smp2 <= '0'; + clk4_phase <= "0000"; + clk4_phase_short <= "00"; + elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then + cpu_clk_4x_smp1 <= cpu_clk_tog after Sim_Delay; + cpu_clk_4x_smp2 <= cpu_clk_4x_smp1 after Sim_Delay; + if (cpu_clk_4x_smp1 = '1' and cpu_clk_4x_smp2 = '0') then + clk4_phase <= "0100" after Sim_Delay; + clk4_phase_short <= "01" after Sim_Delay; + else + clk4_phase <= (clk4_phase(2 downto 0) & clk4_phase(3)) after Sim_Delay; + clk4_phase_short <= clk4_phase_short(0) & clk4_phase_short(1); + end if; + end if; + end process; + + process(cpu_clk_4x, areset) -- + begin + if areset = '1' then + sdr_clk <= '0'; + sdr_clk_n <= '0'; + elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then + if clk4_phase_short(0) = '1' then + sdr_clk <= '1' after Sim_Delay; + else + sdr_clk <= '0' after Sim_Delay; + end if; + if clk4_phase_short(1) = '1' then + sdr_clk_n <= '1' after Sim_Delay; + else + sdr_clk_n <= '0' after Sim_Delay; + end if; + end if; + end process; + + cke_q_p <= '1' after Clk_to_Output; + cs_qn_p <= '0' after Clk_to_Output; + + process(cpu_clk_4x, areset) -- + begin + if areset = '1' then + ras_qn_p <= '1'; + cas_qn_p <= '1'; + we_qn_p <= '1'; + dqs_q_p <= "ZZ"; + sdr_a_p <= "0000000000000"; + ba_q_p <= "00"; + sdr_clk_p <= '0'; + sdr_clk_n_p <= '1'; + elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then + ras_qn_p <= transport ras_qn after Clk_to_Output; + cas_qn_p <= transport cas_qn after Clk_to_Output; + we_qn_p <= transport we_qn after Clk_to_Output; + if dqs_oe_n(0) = '0' then + dqs_q_p(0) <= transport dqs_q(0) after Clk_to_Output; + else + dqs_q_p(0) <= transport 'Z' after Clk_to_Output; + end if; + if dqs_oe_n(1) = '0' then + dqs_q_p(1) <= transport dqs_q(1) after Clk_to_Output; + else + dqs_q_p(1) <= transport 'Z' after Clk_to_Output; + end if; + sdr_a_p <= transport sdr_a after Clk_to_Output; + ba_q_p <= transport ba_q after Clk_to_Output; + sdr_clk_p <= transport sdr_clk after Clk_to_Output; + sdr_clk_n_p <= transport sdr_clk_n after Clk_to_Output; + end if; + end process; + + process(cpu_clk_2x, areset) -- + begin + if areset = '1' then + ddr_state <= idle; + ras_qn <= '1'; + cas_qn <= '1'; + we_qn <= '1'; + smp_req_adr <= (others => '0'); + smp_req_type <= '0'; + smp_req_len <= '0'; + sdr_a <= "XXXXXXXXXXXXX"; + ba_q <= "00"; + ddr_req_ack <= '0'; + ddr_busy <= '1'; + ddr_write_en_int <= '0'; + ddr_read_en_int <= '0'; + elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then + + -- Default values + ras_qn <= '1' after Sim_Delay; + cas_qn <= '1' after Sim_Delay; + we_qn <= '1' after Sim_Delay; + sdr_a <= "XXXXXXXXXXXXX" after Sim_Delay; + ba_q <= "00" after Sim_Delay; + ddr_req_ack <= '0' after Sim_Delay; + ddr_busy <= '1' after Sim_Delay; + ddr_write_en_int <= '0' after Sim_Delay; + ddr_read_en_int <= '0' after Sim_Delay; + + case ddr_state is + when idle => + smp_req_adr <= ddr_req_adr after Sim_Delay; + smp_req_type <= ddr_rd_wr_n after Sim_Delay; + smp_req_len <= ddr_req_len after Sim_Delay; + ddr_busy <= '0' after Sim_Delay; + if refresh_pend = '1' then + ddr_state <= refresh after Sim_Delay; + elsif new_command = '1' then + if ddr_cmd(15) = '1' then + ddr_state <= cpu_pre after Sim_Delay; + else + ddr_state <= cmd after Sim_Delay; + end if; + elsif ddr_req = '1' then + ddr_state <= act after Sim_Delay; + else + ddr_state <= idle after Sim_Delay; + end if; + when act => + sdr_a <= smp_req_adr(23 downto 11) after Sim_Delay; + ras_qn <= '0' after Sim_Delay; + ddr_state <= act_nop1 after Sim_Delay; + ddr_req_ack <= '1' after Sim_Delay; + ddr_write_en_int <= not(smp_req_type) after Sim_Delay; + when act_nop1 => + ddr_state <= act_nop2 after Sim_Delay; + when act_nop2 => + ddr_state <= rd_wr after Sim_Delay; + when rd_wr => + sdr_a(10) <= '0' after Sim_Delay; -- Disable auto precharge + sdr_a(9 downto 0) <= smp_req_adr(10 downto 1) after Sim_Delay; + cas_qn <= '0' after Sim_Delay; + we_qn <= smp_req_type after Sim_Delay; + if smp_req_type = '1' then + ddr_state <= rd_nop1 after Sim_Delay; + else + ddr_state <= wr_nop1 after Sim_Delay; + end if; + when wr_nop1 => + ddr_state <= wr_nop2 after Sim_Delay; + when wr_nop2 => + ddr_state <= wr_nop3 after Sim_Delay; + when wr_nop3 => + ddr_state <= pre after Sim_Delay; + when rd_nop1 => + ddr_state <= rd_nop2 after Sim_Delay; + when rd_nop2 => + ddr_state <= pre after Sim_Delay; + when pre => + ras_qn <= '0' after Sim_Delay; + we_qn <= '0' after Sim_Delay; + sdr_a(10) <= '1' after Sim_Delay; -- Precharge all banks + ddr_state <= pre_nop1 after Sim_Delay; + ddr_read_en_int <= smp_req_type after Sim_Delay; + when pre_nop1 => + ddr_state <= pre_nop2 after Sim_Delay; + when cmd => + cas_qn <= '0' after Sim_Delay; + ras_qn <= '0' after Sim_Delay; + we_qn <= '0' after Sim_Delay; + ba_q <= ddr_cmd(14 downto 13) after Sim_Delay; + sdr_a <= ddr_cmd(12 downto 0) after Sim_Delay; + ddr_state <= idle after Sim_Delay; + when cpu_pre => + ddr_state <= pre after Sim_Delay; + when refresh => + cas_qn <= '0' after Sim_Delay; + ras_qn <= '0' after Sim_Delay; + ddr_state <= refresh_wait after Sim_Delay; + when refresh_wait => + if refresh_wait_end = '1' then + ddr_state <= pre after Sim_Delay; + end if; + when pre_nop2 => + ddr_state <= idle after Sim_Delay; + when others => + ddr_state <= idle after Sim_Delay; + end case; + end if; + end process; + + process(cpu_clk, areset) -- + begin + if areset = '1' then + ddr_cmd <= "0000000000000000"; + elsif (cpu_clk'event and cpu_clk = '1') then + if ddr_command_we = '1' then + ddr_cmd <= ddr_command after Sim_Delay; + else + ddr_cmd <= ddr_cmd after Sim_Delay; + end if; + end if; + end process; + + process(cpu_clk_2x, areset) -- + begin + if areset = '1' then + ddr_cmd_we_smp <= '0'; + new_command <= '0'; + sdr_smp <= "000000000000000000000000000000000000"; + elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then + ddr_cmd_we_smp <= ddr_command_we after Sim_Delay; + if ddr_command_we = '0' and ddr_cmd_we_smp = '1' then + new_command <= '1' after Sim_Delay; + elsif ddr_state = cmd or ddr_state = cpu_pre then + new_command <= '0' after Sim_Delay; + else + new_command <= new_command after Sim_Delay; + end if; + + if ddr_write_en_int = '1' then + sdr_smp <= ddr_data_write after Sim_Delay; + else + sdr_smp <= sdr_smp after Sim_Delay; + end if; + + end if; + end process; + + process(cpu_clk_4x, areset) -- + begin + if areset = '1' then + dqs_q <= "00"; + dqs_oe_n <= "11"; + sdr_oe_ctrl <= '1'; + sdr_wr_msw <= "000000000000000000"; + elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then + + if ddr_state = wr_nop1 and clk4_phase_short(0) = '1' then + sdr_oe_ctrl <= '0' after Sim_Delay; + elsif ddr_state = wr_nop3 and clk4_phase_short(0) = '1' then + sdr_oe_ctrl <= '1' after Sim_Delay; + else + sdr_oe_ctrl <= sdr_oe_ctrl after Sim_Delay; + end if; + + if ddr_state = idle or ddr_state = wr_nop3 then + dqs_oe_n <= "11" after Sim_Delay; + elsif ddr_state = wr_nop1 then + dqs_oe_n <= "00" after Sim_Delay; + else + dqs_oe_n <= dqs_oe_n after Sim_Delay; + end if; + + if (ddr_state = wr_nop2 and clk4_phase_short(0) = '1') then + dqs_q <= "11" after Sim_Delay; + else + dqs_q <= "00" after Sim_Delay; + end if; + + if ddr_state = wr_nop1 and clk4_phase_short(1) = '1' then + sdr_wr_msw <= "111111111111111111" after Sim_Delay; + else + sdr_wr_msw <= "000000000000000000" after Sim_Delay; + end if; + + end if; + end process; + + -- NOTE! DATA OUTPUT PATH. CLOCKED ON FALLING 4X CLOCK + process(cpu_clk_4x, areset) -- + begin + if areset = '1' then + sdr_d_p <= "ZZZZZZZZZZZZZZZZ"; + dm_q_p <= "11"; + sdr_oe_n <= "1111111111111111"; + sdr_d <= "0000000000000000"; + dm_q <= "11"; + elsif (cpu_clk_4x'event and cpu_clk_4x = '0') then + + for i in 0 to 15 loop + if sdr_oe_n(i) = '0' then + sdr_d_p(i) <= transport sdr_d(i) after Clk_to_Output; + else + sdr_d_p(i) <= transport 'Z' after Clk_to_Output; + end if; + end loop; + + dm_q_p <= transport dm_q after Clk_to_Output; + + if sdr_oe_ctrl = '0' then + sdr_oe_n <= "0000000000000000" after Sim_Delay; + else + sdr_oe_n <= "1111111111111111" after Sim_Delay; + end if; + + for i in 0 to 15 loop + if sdr_wr_msw(i) = '0' then + sdr_d(i) <= sdr_smp(i) after Sim_Delay; + else + sdr_d(i) <= sdr_smp(i+16) after Sim_Delay; + end if; + end loop; + + for i in 0 to 1 loop + if sdr_wr_msw(i+16) = '0' then + dm_q(i) <= sdr_smp(i+32) after Sim_Delay; + else + dm_q(i) <= sdr_smp(i+34) after Sim_Delay; + end if; + end loop; + + end if; + end process; + + process(cpu_clk_2x, areset) -- + begin + if areset = '1' then + refresh_cnt <= "0000000000"; + refresh_pend <= '0'; + refresh_end <= '0'; + refresh_wait_cnt <= "000"; + refresh_wait_end <= '0'; + elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then + + if refresh_cnt = Refresh_Interval then + refresh_end <= '1'; + else + refresh_end <= '0'; + end if; + + if refresh_end = '1' then + refresh_cnt <= "0000000000"; + else + refresh_cnt <= refresh_cnt + '1'; + end if; + + if refresh_end = '1' and refresh_en = '1' then + refresh_pend <= '1' after Sim_Delay; + elsif ddr_state = refresh then + refresh_pend <= '0' after Sim_Delay; + else + refresh_pend <= refresh_pend after Sim_Delay; + end if; + + if ddr_state = refresh_wait then + refresh_wait_cnt <= refresh_wait_cnt + '1'; + else + refresh_wait_cnt <= "000"; + end if; + + if refresh_wait_cnt = "111" then + refresh_wait_end <= '1' after Sim_Delay; + else + refresh_wait_end <= '0' after Sim_Delay; + end if; + + end if; + end process; + + -- 911. THIS IS A DUMMY FOR FGPA IMPEMENTATION TESTING + + process(ddr_in_clk, areset) + begin + if areset = '1' then + ddr_clk_tog <= '0'; + elsif (ddr_in_clk'event and ddr_in_clk = '1') then + ddr_clk_tog <= not(ddr_clk_tog) after Sim_Delay; + end if; + end process; + + process(ddr_in_clk_2x, areset) + begin + if areset = '1' then + ddr_clk_smp1 <= '0'; + ddr_clk_smp2 <= '0'; + ddr_clk_phase <= '0'; + elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then + ddr_clk_smp1 <= ddr_clk_tog after Sim_Delay; + ddr_clk_smp2 <= ddr_clk_smp1 after Sim_Delay; + if ddr_clk_smp1 = '1' and ddr_clk_smp2 = '0' then + ddr_clk_phase <= '0'; + else + ddr_clk_phase <= not(ddr_clk_phase); + end if; + end if; + end process; + + process(ddr_in_clk_2x, areset) + begin + if areset = '1' then + cas_n_smp <= '0'; + ras_n_smp <= '0'; + we_n_smp <= '0'; + read_start_sig <= '0'; + elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then + cas_n_smp <= cas_qn_p_del after Sim_Delay; + ras_n_smp <= ras_qn_p_del after Sim_Delay; + we_n_smp <= we_qn_p_del after Sim_Delay; + if ras_n_smp = '1' and cas_n_smp = '0' and we_n_smp = '1' and ddr_clk_phase = '1' then + read_start_sig <= '1' after Sim_Delay; + else + read_start_sig <= '0' after Sim_Delay; + end if; + end if; + end process; + + process(ddr_in_clk_2x, areset) + begin + if areset = '1' then + sdr_d_in <= "0000000000000000"; + elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then + sdr_d_in <= sdr_d_p_del after Sim_Delay; + end if; + end process; + + process(ddr_in_clk_2x, areset) + begin + if areset = '1' then + read_time_cnt <= "00"; + read_input_en <= '0'; + elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then + + if read_start_sig = '1' then + read_time_cnt <= "01" after Sim_Delay; + elsif read_time_cnt = "00" then + read_time_cnt <= read_time_cnt after Sim_Delay; + else + read_time_cnt <= read_time_cnt + '1' after Sim_Delay; + end if; + + if read_time_cnt = "11" then + read_input_en <= '1' after Sim_Delay; + else + read_input_en <= '0' after Sim_Delay; + end if; + + end if; + end process; + + process(ddr_in_clk_2x, areset) + begin + if areset = '1' then + ddr_data_read_int <= "00000000000000000000000000000000"; + elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then + ddr_data_read_int(31 downto 16) <= "0000000000000000" after Sim_Delay; + if read_input_en = '1' then + ddr_data_read_int(15 downto 0) <= sdr_d_in after Sim_Delay; + else + ddr_data_read_int(15 downto 0) <= ddr_data_read_int(15 downto 0) after Sim_Delay; + end if; + end if; + end process; + + + + + + + + + -- ############### + + process(cpu_clk, areset) -- + begin + if areset = '1' then + elsif (cpu_clk'event and cpu_clk = '1') then + end if; + end process; + + + process(cpu_clk_2x, areset) -- + begin + if areset = '1' then + elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then + end if; + end process; + + + process(cpu_clk_4x, areset) -- + begin + if areset = '1' then + elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then + end if; + end process; + + +end behave; + + diff --git a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/mt46v16m16.vhd b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/mt46v16m16.vhd new file mode 100644 index 0000000..6b89345 --- /dev/null +++ b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/mt46v16m16.vhd @@ -0,0 +1,1320 @@ +----------------------------------------------------------------------------------------- +-- +-- File Name: MT46V16M16.VHD +-- Version: 2.1 +-- Date: January 14th, 2002 +-- Model: Behavioral +-- Simulator: NCDesktop - http://www.cadence.com +-- ModelSim PE - http://www.model.com +-- +-- Dependencies: None +-- +-- Author: Son P. Huynh +-- Email: sphuynh@micron.com +-- Phone: (208) 368-3825 +-- Company: Micron Technology, Inc. +-- Part Number: MT46V16M16 (4 Mb x 16 x 4 Banks) +-- +-- Description: Micron 256 Mb SDRAM DDR (Double Data Rate) +-- +-- Limitation: Doesn't model internal refresh counter +-- +-- Note: +-- +-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY +-- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR +-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. +-- +-- Copyright (c) 1998 Micron Semiconductor Products, Inc. +-- All rights researved +-- +-- Rev Author Date Changes +-- --- ---------------------------- ---------- ------------------------------------- +-- 2.1 Son P. Huynh 01/14/2002 - Fix Burst_counter +-- Micron Technology, Inc. +-- +-- 2.0 Son P. Huynh 11/08/2001 - Second release +-- Micron Technology, Inc. - Rewrote and remove SHARED VARIABLE +-- +----------------------------------------------------------------------------------------- + +LIBRARY IEEE; + USE IEEE.STD_LOGIC_1164.ALL; + USE IEEE.STD_LOGIC_UNSIGNED.ALL; + USE IEEE.STD_LOGIC_ARITH.ALL; + +ENTITY MT46V16M16 IS + GENERIC ( -- Timing for -75Z CL2 + tCK : TIME := 7.500 ns; + tCH : TIME := 3.375 ns; -- 0.45*tCK + tCL : TIME := 3.375 ns; -- 0.45*tCK + tDH : TIME := 0.500 ns; + tDS : TIME := 0.500 ns; + tIH : TIME := 0.900 ns; + tIS : TIME := 0.900 ns; + tMRD : TIME := 15.000 ns; + tRAS : TIME := 40.000 ns; + tRAP : TIME := 20.000 ns; + tRC : TIME := 65.000 ns; + tRFC : TIME := 75.000 ns; + tRCD : TIME := 20.000 ns; + tRP : TIME := 20.000 ns; + tRRD : TIME := 15.000 ns; + tWR : TIME := 15.000 ns; + addr_bits : INTEGER := 13; + data_bits : INTEGER := 16; + cols_bits : INTEGER := 9 + ); + PORT ( + Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); + Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ"; + Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + Clk : IN STD_LOGIC; + Clk_n : IN STD_LOGIC; + Cke : IN STD_LOGIC; + Cs_n : IN STD_LOGIC; + Ras_n : IN STD_LOGIC; + Cas_n : IN STD_LOGIC; + We_n : IN STD_LOGIC; + Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) + ); +END MT46V16M16; + +ARCHITECTURE behave OF MT46V16M16 IS + -- Array for Read pipeline + TYPE Array_Read_cmnd IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; + TYPE Array_Read_bank IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); + TYPE Array_Read_cols IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); + + -- Array for Write pipeline + TYPE Array_Write_cmnd IS ARRAY (2 DOWNTO 0) OF STD_LOGIC; + TYPE Array_Write_bank IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); + TYPE Array_Write_cols IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); + + -- Array for Auto Precharge + TYPE Array_Read_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC; + TYPE Array_Write_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC; + TYPE Array_Count_precharge IS ARRAY (3 DOWNTO 0) OF INTEGER; + + -- Array for Manual Precharge + TYPE Array_A10_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; + TYPE Array_Bank_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); + TYPE Array_Cmnd_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; + + -- Array for Burst Terminate + TYPE Array_Cmnd_bst IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; + + -- Array for Memory Access + TYPE Array_ram_type IS ARRAY (2**cols_bits - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0); + TYPE Array_ram_pntr IS ACCESS Array_ram_type; + TYPE Array_ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF Array_ram_pntr; + + -- Data pair + SIGNAL Dq_pair : STD_LOGIC_VECTOR (2 * data_bits - 1 DOWNTO 0); + SIGNAL Dm_pair : STD_LOGIC_VECTOR (3 DOWNTO 0); + + -- Mode Register + SIGNAL Mode_reg : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); + + -- Command Decode Variables + SIGNAL Active_enable, Aref_enable, Burst_term, Ext_mode_enable : STD_LOGIC := '0'; + SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : STD_LOGIC := '0'; + + -- Burst Length Decode Variables + SIGNAL Burst_length_2, Burst_length_4, Burst_length_8, Burst_length_f : STD_LOGIC := '0'; + + -- Cas Latency Decode Variables + SIGNAL Cas_latency_15, Cas_latency_2, Cas_latency_25, Cas_latency_3, Cas_latency_4 : STD_LOGIC := '0'; + + -- Internal Control Signals + SIGNAL Cs_in, Ras_in, Cas_in, We_in : STD_LOGIC := '0'; + + -- System Clock + SIGNAL Sys_clk : STD_LOGIC := '0'; + + -- Dqs buffer + SIGNAL Dqs_out : STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ"; + +BEGIN + -- Strip the strength + Cs_in <= To_X01 (Cs_n); + Ras_in <= To_X01 (Ras_n); + Cas_in <= To_X01 (Cas_n); + We_in <= To_X01 (We_n); + + -- Commands Decode + Active_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND We_in; + Aref_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND We_in; + Burst_term <= NOT(Cs_in) AND Ras_in AND Cas_in AND NOT(We_in); + Ext_mode_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND Ba(0) AND NOT(Ba(1)); + Mode_reg_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND NOT(Ba(0)) AND NOT(Ba(1)); + Prech_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND NOT(We_in); + Read_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND We_in; + Write_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND NOT(We_in); + + -- Burst Length Decode + Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0); + Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0)); + Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0); + Burst_length_f <= (Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0); + + -- CAS Latency Decode + Cas_latency_15 <= Mode_reg(6) AND NOT(Mode_reg(5)) AND (Mode_reg(4)); + Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4)); + Cas_latency_25 <= Mode_reg(6) AND Mode_reg(5) AND NOT(Mode_reg(4)); + Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4); + Cas_latency_4 <= (Mode_reg(6)) AND NOT(Mode_reg(5)) AND NOT(Mode_reg(4)); + + -- Dqs buffer + Dqs <= Dqs_out; + + -- + -- System Clock + -- + int_clk : PROCESS (Clk, Clk_n) + VARIABLE ClkZ, CkeZ : STD_LOGIC := '0'; + begin + IF Clk = '1' AND Clk_n = '0' THEN + ClkZ := '1'; + CkeZ := Cke; + ELSIF Clk = '0' AND Clk_n = '1' THEN + ClkZ := '0'; + END IF; + Sys_clk <= CkeZ AND ClkZ; + END PROCESS; + + -- + -- Main Process + -- + state_register : PROCESS + -- Precharge Variables + VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : STD_LOGIC := '0'; + + -- Activate Variables + VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : STD_LOGIC := '1'; + + -- Data IO variables + VARIABLE Data_in_enable, Data_out_enable : STD_LOGIC := '0'; + + -- Internal address mux variables + VARIABLE Cols_brst : STD_LOGIC_VECTOR (2 DOWNTO 0); + VARIABLE Prev_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; + VARIABLE Bank_addr : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; + VARIABLE Cols_addr : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); + VARIABLE Rows_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + VARIABLE B0_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + VARIABLE B1_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + VARIABLE B2_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + VARIABLE B3_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + + -- DLL Reset variables + VARIABLE DLL_enable : STD_LOGIC := '0'; + VARIABLE DLL_reset : STD_LOGIC := '0'; + VARIABLE DLL_done : STD_LOGIC := '0'; + VARIABLE DLL_count : INTEGER := 0; + + -- Timing Check + VARIABLE MRD_chk : TIME := 0 ns; + VARIABLE RFC_chk : TIME := 0 ns; + VARIABLE RRD_chk : TIME := 0 ns; + VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns; + VARIABLE RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3 : TIME := 0 ns; + VARIABLE RC_chk0, RC_chk1, RC_chk2, RC_chk3 : TIME := 0 ns; + VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns; + VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns; + VARIABLE WR_chk0, WR_chk1, WR_chk2, WR_chk3 : TIME := 0 ns; + + -- Read pipeline variables + VARIABLE Read_cmnd : Array_Read_cmnd; + VARIABLE Read_bank : Array_Read_bank; + VARIABLE Read_cols : Array_Read_cols; + + -- Write pipeline variables + VARIABLE Write_cmnd : Array_Write_cmnd; + VARIABLE Write_bank : Array_Write_bank; + VARIABLE Write_cols : Array_Write_cols; + + -- Auto Precharge variables + VARIABLE Read_precharge : Array_Read_precharge := ('0' & '0' & '0' & '0'); + VARIABLE Write_precharge : Array_Write_precharge := ('0' & '0' & '0' & '0'); + VARIABLE Count_precharge : Array_Count_precharge := ( 0 & 0 & 0 & 0 ); + + -- Manual Precharge variables + VARIABLE A10_precharge : Array_A10_precharge; + VARIABLE Bank_precharge : Array_Bank_precharge; + VARIABLE Cmnd_precharge : Array_Cmnd_precharge; + + -- Burst Terminate variable + VARIABLE Cmnd_bst : Array_Cmnd_bst; + + -- Memory Banks + VARIABLE Bank0 : Array_ram_stor; + VARIABLE Bank1 : Array_ram_stor; + VARIABLE Bank2 : Array_ram_stor; + VARIABLE Bank3 : Array_ram_stor; + + -- Burst Counter + VARIABLE Burst_counter : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); + + -- Internal Dqs initialize + VARIABLE Dqs_int : STD_LOGIC := '0'; + + -- Data buffer for DM Mask + VARIABLE Data_buf : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); + + -- + -- Initialize empty rows + -- + PROCEDURE Init_mem (Bank : STD_LOGIC_VECTOR; Row_index : INTEGER) IS + VARIABLE i, j : INTEGER := 0; + BEGIN + IF Bank = "00" THEN + IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty + Bank0 (Row_index) := NEW Array_ram_type; -- Open new row for access + FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros + FOR j IN (data_bits - 1) DOWNTO 0 LOOP + Bank0 (Row_index) (i) (j) := '0'; + END LOOP; + END LOOP; + END IF; + ELSIF Bank = "01" THEN + IF Bank1 (Row_index) = NULL THEN + Bank1 (Row_index) := NEW Array_ram_type; + FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP + FOR j IN (data_bits - 1) DOWNTO 0 LOOP + Bank1 (Row_index) (i) (j) := '0'; + END LOOP; + END LOOP; + END IF; + ELSIF Bank = "10" THEN + IF Bank2 (Row_index) = NULL THEN + Bank2 (Row_index) := NEW Array_ram_type; + FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP + FOR j IN (data_bits - 1) DOWNTO 0 LOOP + Bank2 (Row_index) (i) (j) := '0'; + END LOOP; + END LOOP; + END IF; + ELSIF Bank = "11" THEN + IF Bank3 (Row_index) = NULL THEN + Bank3 (Row_index) := NEW Array_ram_type; + FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP + FOR j IN (data_bits - 1) DOWNTO 0 LOOP + Bank3 (Row_index) (i) (j) := '0'; + END LOOP; + END LOOP; + END IF; + END IF; + END; + + -- + -- Burst Counter + -- + PROCEDURE Burst_decode IS + VARIABLE Cols_temp : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0) := (OTHERS => '0'); + BEGIN + -- Advance burst counter + Burst_counter := Burst_counter + 1; + + -- Burst Type + IF Mode_reg (3) = '0' THEN + Cols_temp := Cols_addr + 1; + ELSIF Mode_reg (3) = '1' THEN + Cols_temp (2) := Burst_counter (2) XOR Cols_brst (2); + Cols_temp (1) := Burst_counter (1) XOR Cols_brst (1); + Cols_temp (0) := Burst_counter (0) XOR Cols_brst (0); + END IF; + + -- Burst Length + IF Burst_length_2 = '1' THEN + Cols_addr (0) := Cols_temp (0); + ELSIF Burst_length_4 = '1' THEN + Cols_addr (1 DOWNTO 0) := Cols_temp (1 DOWNTO 0); + ELSIF Burst_length_8 = '1' THEN + Cols_addr (2 DOWNTO 0) := Cols_temp (2 DOWNTO 0); + ELSE + Cols_addr := Cols_temp; + END IF; + + -- Data counter + IF Burst_length_2 = '1' THEN + IF Burst_counter >= 2 THEN + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + ELSIF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + ELSIF Burst_length_4 = '1' THEN + IF Burst_counter >= 4 THEN + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + ELSIF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + ELSIF Burst_length_8 = '1' THEN + IF Burst_counter >= 8 THEN + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + ELSIF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + END IF; + END; + + BEGIN + WAIT ON Sys_clk; + + -- + -- Manual Precharge Pipeline + -- + IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN + -- A10 Precharge Pipeline + A10_precharge(0) := A10_precharge(1); + A10_precharge(1) := A10_precharge(2); + A10_precharge(2) := A10_precharge(3); + A10_precharge(3) := A10_precharge(4); + A10_precharge(4) := A10_precharge(5); + A10_precharge(5) := A10_precharge(6); + A10_precharge(6) := A10_precharge(7); + A10_precharge(7) := A10_precharge(8); + A10_precharge(8) := '0'; + + -- Bank Precharge Pipeline + Bank_precharge(0) := Bank_precharge(1); + Bank_precharge(1) := Bank_precharge(2); + Bank_precharge(2) := Bank_precharge(3); + Bank_precharge(3) := Bank_precharge(4); + Bank_precharge(4) := Bank_precharge(5); + Bank_precharge(5) := Bank_precharge(6); + Bank_precharge(6) := Bank_precharge(7); + Bank_precharge(7) := Bank_precharge(8); + Bank_precharge(8) := "00"; + + -- Command Precharge Pipeline + Cmnd_precharge(0) := Cmnd_precharge(1); + Cmnd_precharge(1) := Cmnd_precharge(2); + Cmnd_precharge(2) := Cmnd_precharge(3); + Cmnd_precharge(3) := Cmnd_precharge(4); + Cmnd_precharge(4) := Cmnd_precharge(5); + Cmnd_precharge(5) := Cmnd_precharge(6); + Cmnd_precharge(6) := Cmnd_precharge(7); + Cmnd_precharge(7) := Cmnd_precharge(8); + Cmnd_precharge(8) := '0'; + + -- Terminate Read if same bank or all banks + IF ((Cmnd_precharge (0) = '1') AND + (Bank_precharge (0) = Bank_addr OR A10_precharge (0) = '1') AND + (Data_out_enable = '1')) THEN + Data_out_enable := '0'; + END IF; + END IF; + + -- + -- Burst Terminate Pipeline + -- + IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN + -- Burst Terminate pipeline + Cmnd_bst (0) := Cmnd_bst (1); + Cmnd_bst (1) := Cmnd_bst (2); + Cmnd_bst (2) := Cmnd_bst (3); + Cmnd_bst (3) := Cmnd_bst (4); + Cmnd_bst (4) := Cmnd_bst (5); + Cmnd_bst (5) := Cmnd_bst (6); + Cmnd_bst (6) := Cmnd_bst (7); + Cmnd_bst (7) := Cmnd_bst (8); + Cmnd_bst (8) := '0'; + + -- Terminate current Read + IF ((Cmnd_bst (0) = '1') AND (Data_out_enable = '1')) THEN + Data_out_enable := '0'; + END IF; + END IF; + + -- + -- Dq and Dqs Drivers + -- + IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN + -- Read Command Pipeline + Read_cmnd (0) := Read_cmnd (1); + Read_cmnd (1) := Read_cmnd (2); + Read_cmnd (2) := Read_cmnd (3); + Read_cmnd (3) := Read_cmnd (4); + Read_cmnd (4) := Read_cmnd (5); + Read_cmnd (5) := Read_cmnd (6); + Read_cmnd (6) := Read_cmnd (7); + Read_cmnd (7) := Read_cmnd (8); + Read_cmnd (8) := '0'; + + -- Read Bank Pipeline + Read_bank (0) := Read_bank (1); + Read_bank (1) := Read_bank (2); + Read_bank (2) := Read_bank (3); + Read_bank (3) := Read_bank (4); + Read_bank (4) := Read_bank (5); + Read_bank (5) := Read_bank (6); + Read_bank (6) := Read_bank (7); + Read_bank (7) := Read_bank (8); + Read_bank (8) := "00"; + + -- Read Column Pipeline + Read_cols (0) := Read_cols (1); + Read_cols (1) := Read_cols (2); + Read_cols (2) := Read_cols (3); + Read_cols (3) := Read_cols (4); + Read_cols (4) := Read_cols (5); + Read_cols (5) := Read_cols (6); + Read_cols (6) := Read_cols (7); + Read_cols (7) := Read_cols (8); + Read_cols (8) := (OTHERS => '0'); + + -- Initialize Read command + IF Read_cmnd (0) = '1' THEN + Data_out_enable := '1'; + Bank_addr := Read_bank (0); + Cols_addr := Read_cols (0); + Cols_brst := Cols_addr (2 DOWNTO 0); + Burst_counter := (OTHERS => '0'); + + -- Row address mux + CASE Bank_addr IS + WHEN "00" => Rows_addr := B0_row_addr; + WHEN "01" => Rows_addr := B1_row_addr; + WHEN "10" => Rows_addr := B2_row_addr; + WHEN OTHERS => Rows_addr := B3_row_addr; + END CASE; + END IF; + + -- Toggle Dqs during Read command + IF Data_out_enable = '1' THEN + Dqs_int := '0'; + IF Dqs_out = "00" THEN + Dqs_out <= "11"; + ELSIF Dqs_out = "11" THEN + Dqs_out <= "00"; + ELSE + Dqs_out <= "00"; + END IF; + ELSIF Data_out_enable = '0' AND Dqs_int = '0' THEN + Dqs_out <= "ZZ"; + END IF; + + -- Initialize Dqs for Read command + IF Read_cmnd (2) = '1' THEN + IF Data_out_enable = '0' THEN + Dqs_int := '1'; + Dqs_out <= "00"; + END IF; + END IF; + + -- Read Latch + IF Data_out_enable = '1' THEN + -- Initialize Memory + Init_mem (Bank_addr, CONV_INTEGER(Rows_addr)); + + -- Output Data + CASE Bank_addr IS + WHEN "00" => Dq <= Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); + WHEN "01" => Dq <= Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); + WHEN "10" => Dq <= Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); + WHEN OTHERS => Dq <= Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); + END CASE; + + -- Increase Burst Counter + Burst_decode; + ELSE + Dq <= (OTHERS => 'Z'); + END IF; + END IF; + + -- + -- Write FIFO and DM Mask Logic + -- + IF Sys_clk'EVENT AND Sys_clk = '1' THEN + -- Write command pipeline + Write_cmnd (0) := Write_cmnd (1); + Write_cmnd (1) := Write_cmnd (2); + Write_cmnd (2) := '0'; + + -- Write command pipeline + Write_bank (0) := Write_bank (1); + Write_bank (1) := Write_bank (2); + Write_bank (2) := "00"; + + -- Write column pipeline + Write_cols (0) := Write_cols (1); + Write_cols (1) := Write_cols (2); + Write_cols (2) := (OTHERS => '0'); + + -- Initialize Write command + IF Write_cmnd (0) = '1' THEN + Data_in_enable := '1'; + Bank_addr := Write_bank (0); + Cols_addr := Write_cols (0); + Cols_brst := Cols_addr (2 DOWNTO 0); + Burst_counter := (OTHERS => '0'); + + -- Row address mux + CASE Bank_addr IS + WHEN "00" => Rows_addr := B0_row_addr; + WHEN "01" => Rows_addr := B1_row_addr; + WHEN "10" => Rows_addr := B2_row_addr; + WHEN OTHERS => Rows_addr := B3_row_addr; + END CASE; + END IF; + + -- Write data + IF Data_in_enable = '1' THEN + -- Initialize memory + Init_mem (Bank_addr, CONV_INTEGER(Rows_addr)); + + -- Write first data + IF Dm_pair (1) = '0' OR Dm_pair (0) = '0' THEN + -- Data Buffer + CASE Bank_addr IS + WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); + WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); + WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); + WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); + END CASE; + + -- Perform DM Mask + IF Dm_pair (0) = '0' THEN + Data_buf ( 7 DOWNTO 0) := Dq_pair ( 7 DOWNTO 0); + END IF; + IF Dm_pair (1) = '0' THEN + Data_buf (15 DOWNTO 8) := Dq_pair (15 DOWNTO 8); + END IF; + + -- Write Data + CASE Bank_addr IS + WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; + WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; + WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; + WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; + END CASE; + END IF; + + -- Increase Burst Counter + Burst_decode; + + -- Write second data + IF Dm_pair (3) = '0' OR Dm_pair (2) = '0' THEN + -- Data Buffer + CASE Bank_addr IS + WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); + WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); + WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); + WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); + END CASE; + + -- Perform DM Mask + IF Dm_pair (2) = '0' THEN + Data_buf ( 7 DOWNTO 0) := Dq_pair (23 DOWNTO 16); + END IF; + IF Dm_pair (3) = '0' THEN + Data_buf (15 DOWNTO 8) := Dq_pair (31 DOWNTO 24); + END IF; + + -- Write Data + CASE Bank_addr IS + WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; + WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; + WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; + WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; + END CASE; + END IF; + + -- Increase Burst Counter + Burst_decode; + + -- tWR start and tWTR check + IF Dm_pair (3 DOWNTO 2) = "00" OR Dm_pair (1 DOWNTO 0) = "00" THEN + CASE Bank_addr IS + WHEN "00" => WR_chk0 := NOW; + WHEN "01" => WR_chk1 := NOW; + WHEN "10" => WR_chk2 := NOW; + WHEN OTHERS => WR_chk3 := NOW; + END CASE; + + -- tWTR check + ASSERT (Read_enable = '0') + REPORT "tWTR violation during Read" + SEVERITY WARNING; + END IF; + END IF; + END IF; + + -- + -- Auto Precharge Calculation + -- + IF Sys_clk'EVENT AND Sys_clk = '1' THEN + -- Precharge counter + IF Read_precharge (0) = '1' OR Write_precharge (0) = '1' THEN + Count_precharge (0) := Count_precharge (0) + 1; + END IF; + IF Read_precharge (1) = '1' OR Write_precharge (1) = '1' THEN + Count_precharge (1) := Count_precharge (1) + 1; + END IF; + IF Read_precharge (2) = '1' OR Write_precharge (2) = '1' THEN + Count_precharge (2) := Count_precharge (2) + 1; + END IF; + IF Read_precharge (3) = '1' OR Write_precharge (3) = '1' THEN + Count_precharge (3) := Count_precharge (3) + 1; + END IF; + + -- Read with AutoPrecharge Calculation + -- The device start internal precharge when: + -- 1. Meet tRAS requirement + -- 2. BL/2 cycles after command + IF ((Read_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN + IF ((Burst_length_2 = '1' AND Count_precharge(0) >= 1) OR + (Burst_length_4 = '1' AND Count_precharge(0) >= 2) OR + (Burst_length_8 = '1' AND Count_precharge(0) >= 4)) THEN + Pc_b0 := '1'; + Act_b0 := '0'; + RP_chk0 := NOW; + Read_precharge(0) := '0'; + END IF; + END IF; + IF ((Read_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN + IF ((Burst_length_2 = '1' AND Count_precharge(1) >= 1) OR + (Burst_length_4 = '1' AND Count_precharge(1) >= 2) OR + (Burst_length_8 = '1' AND Count_precharge(1) >= 4)) THEN + Pc_b1 := '1'; + Act_b1 := '0'; + RP_chk1 := NOW; + Read_precharge(1) := '0'; + END IF; + END IF; + IF ((Read_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN + IF ((Burst_length_2 = '1' AND Count_precharge(2) >= 1) OR + (Burst_length_4 = '1' AND Count_precharge(2) >= 2) OR + (Burst_length_8 = '1' AND Count_precharge(2) >= 4)) THEN + Pc_b2 := '1'; + Act_b2 := '0'; + RP_chk2 := NOW; + Read_precharge(2) := '0'; + END IF; + END IF; + IF ((Read_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN + IF ((Burst_length_2 = '1' AND Count_precharge(3) >= 1) OR + (Burst_length_4 = '1' AND Count_precharge(3) >= 2) OR + (Burst_length_8 = '1' AND Count_precharge(3) >= 4)) THEN + Pc_b3 := '1'; + Act_b3 := '0'; + RP_chk3 := NOW; + Read_precharge(3) := '0'; + END IF; + END IF; + + -- Write with AutoPrecharge Calculation + -- The device start internal precharge when: + -- 1. Meet tRAS requirement + -- 2. Two clock after last burst + -- Since tWR is time base, the model will compensate tRP + IF ((Write_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN + IF ((Burst_length_2 = '1' AND Count_precharge (0) >= 4) OR + (Burst_length_4 = '1' AND Count_precharge (0) >= 5) OR + (Burst_length_8 = '1' AND Count_precharge (0) >= 7)) THEN + Pc_b0 := '1'; + Act_b0 := '0'; + RP_chk0 := NOW - ((2 * tCK) - tWR); + Write_precharge(0) := '0'; + END IF; + END IF; + IF ((Write_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN + IF ((Burst_length_2 = '1' AND Count_precharge (1) >= 4) OR + (Burst_length_4 = '1' AND Count_precharge (1) >= 5) OR + (Burst_length_8 = '1' AND Count_precharge (1) >= 7)) THEN + Pc_b1 := '1'; + Act_b1 := '0'; + RP_chk1 := NOW - ((2 * tCK) - tWR); + Write_precharge(1) := '0'; + END IF; + END IF; + IF ((Write_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN + IF ((Burst_length_2 = '1' AND Count_precharge (2) >= 4) OR + (Burst_length_4 = '1' AND Count_precharge (2) >= 5) OR + (Burst_length_8 = '1' AND Count_precharge (2) >= 7)) THEN + Pc_b2 := '1'; + Act_b2 := '0'; + RP_chk2 := NOW - ((2 * tCK) - tWR); + Write_precharge(2) := '0'; + END IF; + END IF; + IF ((Write_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN + IF ((Burst_length_2 = '1' AND Count_precharge (3) >= 4) OR + (Burst_length_4 = '1' AND Count_precharge (3) >= 5) OR + (Burst_length_8 = '1' AND Count_precharge (3) >= 7)) THEN + Pc_b3 := '1'; + Act_b3 := '0'; + RP_chk3 := NOW - ((2 * tCK) - tWR); + Write_precharge(3) := '0'; + END IF; + END IF; + END IF; + + -- + -- DLL Counter + -- + IF Sys_clk'EVENT AND Sys_clk = '1' THEN + IF (DLL_Reset = '1' AND DLL_done = '0') THEN + DLL_count := DLL_count + 1; + IF (DLL_count >= 200) THEN + DLL_done := '1'; + END IF; + END IF; + END IF; + + -- + -- Control Logic + -- + IF Sys_clk'EVENT AND Sys_clk = '1' THEN + -- Auto Refresh + IF Aref_enable = '1' THEN + -- Auto Refresh to Auto Refresh + ASSERT (NOW - RFC_chk >= tRFC) + REPORT "tRFC violation during Auto Refresh" + SEVERITY WARNING; + + -- Precharge to Auto Refresh + ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND + (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) + REPORT "tRP violation during Auto Refresh" + SEVERITY WARNING; + + -- Precharge to Auto Refresh + ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') + REPORT "All banks must be Precharge before Auto Refresh" + SEVERITY WARNING; + + -- Record current tRFC time + RFC_chk := NOW; + END IF; + + -- Extended Load Mode Register + IF Ext_mode_enable = '1' THEN + IF (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') THEN + IF (Addr (0) = '0') THEN + DLL_enable := '1'; + ELSE + DLL_enable := '0'; + END IF; + END IF; + + -- Precharge to EMR + ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') + REPORT "All bank must be Precharged before Extended Mode Register" + SEVERITY WARNING; + + -- Precharge to EMR + ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND + (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) + REPORT "tRP violation during Extended Load Register" + SEVERITY WARNING; + + -- LMR/EMR to EMR + ASSERT (NOW - MRD_chk >= tMRD) + REPORT "tMRD violation during Extended Mode Register" + SEVERITY WARNING; + + -- Record current tMRD time + MRD_chk := NOW; + END IF; + + -- Load Mode Register + IF Mode_reg_enable = '1' THEN + -- Register mode + Mode_reg <= Addr; + + -- DLL Reset + IF (DLL_enable = '1' AND Addr (8) = '1') THEN + DLL_reset := '1'; + DLL_done := '0'; + DLL_count := 0; + ELSIF (DLL_enable = '1' AND DLL_reset = '0' AND Addr (8) = '0') THEN + ASSERT (FALSE) + REPORT "DLL is ENABLE: DLL RESET is require" + SEVERITY WARNING; + ELSIF (DLL_enable = '0' AND Addr (8) = '1') THEN + ASSERT (FALSE) + REPORT "DLL is DISABLE: DLL RESET will be ignored" + SEVERITY WARNING; + END IF; + + -- Precharge to LMR + ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') + REPORT "All bank must be Precharged before Load Mode Register" + SEVERITY WARNING; + + -- Precharge to EMR + ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND + (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) + REPORT "tRP violation during Load Mode Register" + SEVERITY WARNING; + + -- LMR/ELMR to LMR + ASSERT (NOW - MRD_chk >= tMRD) + REPORT "tMRD violation during Load Mode Register" + SEVERITY WARNING; + + -- Check for invalid Burst Length + ASSERT ((Addr (2 DOWNTO 0) = "001") OR -- BL = 2 + (Addr (2 DOWNTO 0) = "010") OR -- BL = 4 + (Addr (2 DOWNTO 0) = "011")) -- BL = 8 + REPORT "Invalid Burst Length during Load Mode Register" + SEVERITY WARNING; + + -- Check for invalid CAS Latency + ASSERT ((Addr (6 DOWNTO 4) = "010") OR -- CL = 2.0 + (Addr (6 DOWNTO 4) = "110")) -- CL = 2.5 + REPORT "Invalid CAS Latency during Load Mode Register" + SEVERITY WARNING; + + -- Record current tMRD time + MRD_chk := NOW; + END IF; + + -- Active Block (latch Bank and Row Address) + IF Active_enable = '1' THEN + -- Activate an OPEN bank can corrupt data + ASSERT ((Ba = "00" AND Act_b0 = '0') OR + (Ba = "01" AND Act_b1 = '0') OR + (Ba = "10" AND Act_b2 = '0') OR + (Ba = "11" AND Act_b3 = '0')) + REPORT "Bank is already activated - data can be corrupted" + SEVERITY WARNING; + + -- Activate Bank 0 + IF Ba = "00" AND Pc_b0 = '1' THEN + -- Activate to Activate (same bank) + ASSERT (NOW - RC_chk0 >= tRC) + REPORT "tRC violation during Activate Bank 0" + SEVERITY WARNING; + + -- Precharge to Active + ASSERT (NOW - RP_chk0 >= tRP) + REPORT "tRP violation during Activate Bank 0" + SEVERITY WARNING; + + -- Record Variables for checking violation + Act_b0 := '1'; + Pc_b0 := '0'; + B0_row_addr := Addr; + RC_chk0 := NOW; + RCD_chk0 := NOW; + RAS_chk0 := NOW; + RAP_chk0 := NOW; + END IF; + + -- Activate Bank 1 + IF Ba = "01" AND Pc_b1 = '1' THEN + -- Activate to Activate (same bank) + ASSERT (NOW - RC_chk1 >= tRC) + REPORT "tRC violation during Activate Bank 1" + SEVERITY WARNING; + + -- Precharge to Active + ASSERT (NOW - RP_chk1 >= tRP) + REPORT "tRP violation during Activate Bank 1" + SEVERITY WARNING; + + -- Record Variables for checking violation + Act_b1 := '1'; + Pc_b1 := '0'; + B1_row_addr := Addr; + RC_chk1 := NOW; + RCD_chk1 := NOW; + RAS_chk1 := NOW; + RAP_chk1 := NOW; + END IF; + + -- Activate Bank 2 + IF Ba = "10" AND Pc_b2 = '1' THEN + -- Activate to Activate (same bank) + ASSERT (NOW - RC_chk2 >= tRC) + REPORT "tRC violation during Activate Bank 2" + SEVERITY WARNING; + + -- Precharge to Active + ASSERT (NOW - RP_chk2 >= tRP) + REPORT "tRP violation during Activate Bank 2" + SEVERITY WARNING; + + -- Record Variables for checking violation + Act_b2 := '1'; + Pc_b2 := '0'; + B2_row_addr := Addr; + RC_chk2 := NOW; + RCD_chk2 := NOW; + RAS_chk2 := NOW; + RAP_chk2 := NOW; + END IF; + + -- Activate Bank 3 + IF Ba = "11" AND Pc_b3 = '1' THEN + -- Activate to Activate (same bank) + ASSERT (NOW - RC_chk3 >= tRC) + REPORT "tRC violation during Activate Bank 3" + SEVERITY WARNING; + + -- Precharge to Active + ASSERT (NOW - RP_chk3 >= tRP) + REPORT "tRP violation during Activate Bank 3" + SEVERITY WARNING; + + -- Record Variables for checking violation + Act_b3 := '1'; + Pc_b3 := '0'; + B3_row_addr := Addr; + RC_chk3 := NOW; + RCD_chk3 := NOW; + RAS_chk3 := NOW; + RAP_chk3 := NOW; + END IF; + + -- Activate Bank A to Activate Bank B + IF (Prev_bank /= Ba) THEN + ASSERT (NOW - RRD_chk >= tRRD) + REPORT "tRRD violation during Activate" + SEVERITY WARNING; + END IF; + + -- AutoRefresh to Activate + ASSERT (NOW - RFC_chk >= tRFC) + REPORT "tRFC violation during Activate" + SEVERITY WARNING; + + -- Record Variables for Checking Violation + RRD_chk := NOW; + Prev_bank := Ba; + END IF; + + -- Precharge Block - Consider NOP if bank already precharged or in process of precharging + IF Prech_enable = '1' THEN + -- EMR or LMR to Precharge + ASSERT (NOW - MRD_chk >= tMRD) + REPORT "tMRD violation during Precharge" + SEVERITY WARNING; + + -- Precharge Bank 0 + IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "00")) AND Act_b0 = '1') THEN + Act_b0 := '0'; + Pc_b0 := '1'; + RP_chk0 := NOW; + + -- Activate to Precharge bank 0 + ASSERT (NOW - RAS_chk0 >= tRAS) + REPORT "tRAS violation during Precharge" + SEVERITY WARNING; + + -- tWR violation check for Write + ASSERT (NOW - WR_chk0 >= tWR) + REPORT "tWR violation during Precharge" + SEVERITY WARNING; + END IF; + + -- Precharge Bank 1 + IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "01")) AND Act_b1 = '1') THEN + Act_b1 := '0'; + Pc_b1 := '1'; + RP_chk1 := NOW; + + -- Activate to Precharge + ASSERT (NOW - RAS_chk1 >= tRAS) + REPORT "tRAS violation during Precharge" + SEVERITY WARNING; + + -- tWR violation check for Write + ASSERT (NOW - WR_chk1 >= tWR) + REPORT "tWR violation during Precharge" + SEVERITY WARNING; + END IF; + + -- Precharge Bank 2 + IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "10")) AND Act_b2 = '1') THEN + Act_b2 := '0'; + Pc_b2 := '1'; + RP_chk2 := NOW; + + -- Activate to Precharge + ASSERT (NOW - RAS_chk2 >= tRAS) + REPORT "tRAS violation during Precharge" + SEVERITY WARNING; + + -- tWR violation check for Write + ASSERT (NOW - WR_chk2 >= tWR) + REPORT "tWR violation during Precharge" + SEVERITY WARNING; + END IF; + + -- Precharge Bank 3 + IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "11")) AND Act_b3 = '1') THEN + Act_b3 := '0'; + Pc_b3 := '1'; + RP_chk3 := NOW; + + -- Activate to Precharge + ASSERT (NOW - RAS_chk3 >= tRAS) + REPORT "tRAS violation during Precharge" + SEVERITY WARNING; + + -- tWR violation check for Write + ASSERT (NOW - WR_chk3 >= tWR) + REPORT "tWR violation during Precharge" + SEVERITY WARNING; + END IF; + + -- Pipeline for READ + IF CAS_latency_15 = '1' THEN + A10_precharge (3) := Addr(10); + Bank_precharge (3) := Ba; + Cmnd_precharge (3) := '1'; + ELSIF CAS_latency_2 = '1' THEN + A10_precharge (4) := Addr(10); + Bank_precharge (4) := Ba; + Cmnd_precharge (4) := '1'; + ELSIF CAS_latency_25 = '1' THEN + A10_precharge (5) := Addr(10); + Bank_precharge (5) := Ba; + Cmnd_precharge (5) := '1'; + ELSIF CAS_latency_3 = '1' THEN + A10_precharge (6) := Addr(10); + Bank_precharge (6) := Ba; + Cmnd_precharge (6) := '1'; + ELSIF CAS_latency_4 = '1' THEN + A10_precharge (8) := Addr(10); + Bank_precharge (8) := Ba; + Cmnd_precharge (8) := '1'; + END IF; + END IF; + + -- Burst Terminate + IF Burst_term = '1' THEN + -- Pipeline for Read + IF CAS_latency_15 = '1' THEN + Cmnd_bst (3) := '1'; + ELSIF CAS_latency_2 = '1' THEN + Cmnd_bst (4) := '1'; + ELSIF CAS_latency_25 = '1' THEN + Cmnd_bst (5) := '1'; + ELSIF CAS_latency_3 = '1' THEN + Cmnd_bst (6) := '1'; + ELSIF CAS_latency_4 = '1' THEN + Cmnd_bst (8) := '1'; + END IF; + + -- Terminate Write + ASSERT (Data_in_enable = '0') + REPORT "It's illegal to Burst Terminate a Write" + SEVERITY WARNING; + + -- Terminate Read with Auto Precharge + ASSERT (Read_precharge (0) = '0' AND Read_precharge (1) = '0' AND + Read_precharge (2) = '0' AND Read_precharge (3) = '0') + REPORT "It's illegal to Burst Terminate a Read with Auto Precharge" + SEVERITY WARNING; + END IF; + + -- Read Command + IF Read_enable = '1' THEN + -- CAS Latency Pipeline + IF Cas_latency_15 = '1' THEN + Read_cmnd (3) := '1'; + Read_bank (3) := Ba; + Read_cols (3) := Addr (8 DOWNTO 0); + ELSIF Cas_latency_2 = '1' THEN + Read_cmnd (4) := '1'; + Read_bank (4) := Ba; + Read_cols (4) := Addr (8 DOWNTO 0); + ELSIF Cas_latency_25 = '1' THEN + Read_cmnd (5) := '1'; + Read_bank (5) := Ba; + Read_cols (5) := Addr (8 DOWNTO 0); + ELSIF Cas_latency_3 = '1' THEN + Read_cmnd (6) := '1'; + Read_bank (6) := Ba; + Read_cols (6) := Addr (8 DOWNTO 0); + ELSIF Cas_latency_4 = '1' THEN + Read_cmnd (8) := '1'; + Read_bank (8) := Ba; + Read_cols (8) := Addr (8 DOWNTO 0); + END IF; + + -- Write to Read: Terminate Write Immediately + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + END IF; + + -- Interrupting a Read with Auto Precharge (same bank only) + ASSERT (Read_precharge(CONV_INTEGER(Ba)) = '0') + REPORT "It's illegal to interrupt a Read with Auto Precharge" + SEVERITY WARNING; + + -- Activate to Read + ASSERT ((Ba = "00" AND Act_b0 = '1') OR + (Ba = "01" AND Act_b1 = '1') OR + (Ba = "10" AND Act_b2 = '1') OR + (Ba = "11" AND Act_b3 = '1')) + REPORT "Bank is not Activated for Read" + SEVERITY WARNING; + + -- Activate to Read without Auto Precharge + IF Addr (10) = '0' THEN + ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR + (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR + (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR + (Ba = "11" AND NOW - RCD_chk3 >= tRCD)) + REPORT "tRCD violation during Read" + SEVERITY WARNING; + END IF; + + -- Activate to Read with Auto Precharge + IF Addr (10) = '1' THEN + ASSERT ((Ba = "00" AND NOW - RAP_chk0 >= tRAP) OR + (Ba = "01" AND NOW - RAP_chk1 >= tRAP) OR + (Ba = "10" AND NOW - RAP_chk2 >= tRAP) OR + (Ba = "11" AND NOW - RAP_chk3 >= tRAP)) + REPORT "tRAP violation during Read" + SEVERITY WARNING; + END IF; + + -- Auto precharge + IF Addr (10) = '1' THEN + Read_precharge (Conv_INTEGER(Ba)) := '1'; + Count_precharge (Conv_INTEGER(Ba)) := 0; + END IF; + + -- DLL Check + IF (DLL_reset = '1') THEN + ASSERT (DLL_done = '1') + REPORT "DLL RESET not complete" + SEVERITY WARNING; + END IF; + END IF; + + -- Write Command + IF Write_enable = '1' THEN + -- Pipeline for Write + Write_cmnd (2) := '1'; + Write_bank (2) := Ba; + Write_cols (2) := Addr (8 DOWNTO 0); + + -- Interrupting a Write with Auto Precharge (same bank only) + ASSERT (Write_precharge(CONV_INTEGER(Ba)) = '0') + REPORT "It's illegal to interrupt a Write with Auto Precharge" + SEVERITY WARNING; + + -- Activate to Write + ASSERT ((Ba = "00" AND Act_b0 = '1') OR + (Ba = "01" AND Act_b1 = '1') OR + (Ba = "10" AND Act_b2 = '1') OR + (Ba = "11" AND Act_b3 = '1')) + REPORT "Bank is not Activated for Write" + SEVERITY WARNING; + + -- Activate to Write + ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR + (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR + (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR + (Ba = "11" AND NOW - RCD_chk3 >= tRCD)) + REPORT "tRCD violation during Write" + SEVERITY WARNING; + + -- Auto precharge + IF Addr (10) = '1' THEN + Write_precharge (Conv_INTEGER(Ba)) := '1'; + Count_precharge (Conv_INTEGER(Ba)) := 0; + END IF; + END IF; + END IF; + END PROCESS; + + -- + -- Dqs Receiver + -- + dqs_rcvrs : PROCESS + VARIABLE Dm_temp : STD_LOGIC_VECTOR (1 DOWNTO 0); + VARIABLE Dq_temp : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0); + BEGIN + WAIT ON Dqs; + -- Latch data at posedge Dqs + IF Dqs'EVENT AND Dqs (1) = '1' AND Dqs (0) = '1' THEN + Dq_temp := Dq; + Dm_temp := Dm; + END IF; + -- Latch data at negedge Dqs + IF Dqs'EVENT AND Dqs (1) = '0' AND Dqs (0) = '0' THEN + Dq_pair <= (Dq & Dq_temp); + Dm_pair <= (Dm & Dm_temp); + END IF; + END PROCESS; + + -- + -- Setup timing checks + -- + Setup_check : PROCESS + BEGIN + WAIT ON Sys_clk; + IF Sys_clk'EVENT AND Sys_clk = '1' THEN + ASSERT(Cke'LAST_EVENT >= tIS) + REPORT "CKE Setup time violation -- tIS" + SEVERITY WARNING; + ASSERT(Cs_n'LAST_EVENT >= tIS) + REPORT "CS# Setup time violation -- tIS" + SEVERITY WARNING; + ASSERT(Cas_n'LAST_EVENT >= tIS) + REPORT "CAS# Setup time violation -- tIS" + SEVERITY WARNING; + ASSERT(Ras_n'LAST_EVENT >= tIS) + REPORT "RAS# Setup time violation -- tIS" + SEVERITY WARNING; + ASSERT(We_n'LAST_EVENT >= tIS) + REPORT "WE# Setup time violation -- tIS" + SEVERITY WARNING; + ASSERT(Addr'LAST_EVENT >= tIS) + REPORT "ADDR Setup time violation -- tIS" + SEVERITY WARNING; + ASSERT(Ba'LAST_EVENT >= tIS) + REPORT "BA Setup time violation -- tIS" + SEVERITY WARNING; + END IF; + END PROCESS; + + -- + -- Hold timing checks + -- + Hold_check : PROCESS + BEGIN + WAIT ON Sys_clk'DELAYED (tIH); + IF Sys_clk'DELAYED (tIH) = '1' THEN + ASSERT(Cke'LAST_EVENT >= tIH) + REPORT "CKE Hold time violation -- tIH" + SEVERITY WARNING; + ASSERT(Cs_n'LAST_EVENT >= tIH) + REPORT "CS# Hold time violation -- tIH" + SEVERITY WARNING; + ASSERT(Cas_n'LAST_EVENT >= tIH) + REPORT "CAS# Hold time violation -- tIH" + SEVERITY WARNING; + ASSERT(Ras_n'LAST_EVENT >= tIH) + REPORT "RAS# Hold time violation -- tIH" + SEVERITY WARNING; + ASSERT(We_n'LAST_EVENT >= tIH) + REPORT "WE# Hold time violation -- tIH" + SEVERITY WARNING; + ASSERT(Addr'LAST_EVENT >= tIH) + REPORT "ADDR Hold time violation -- tIH" + SEVERITY WARNING; + ASSERT(Ba'LAST_EVENT >= tIH) + REPORT "BA Hold time violation -- tIH" + SEVERITY WARNING; + END IF; + END PROCESS; + +END behave; diff --git a/zpu/hdl/zpu4/src/.cvsignore b/zpu/hdl/zpu4/src/.cvsignore new file mode 100644 index 0000000..41c40a0 --- /dev/null +++ b/zpu/hdl/zpu4/src/.cvsignore @@ -0,0 +1,5 @@ +work +vsim.wlf +xilinx_device_details.xml +tcl_stacktrace.txt +vish_stacktrace.vstf diff --git a/zpu/hdl/zpu4/src/bram.vhd b/zpu/hdl/zpu4/src/bram.vhd new file mode 100644 index 0000000..435f3f4 --- /dev/null +++ b/zpu/hdl/zpu4/src/bram.vhd @@ -0,0 +1,3807 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + + +library zylin; +use zylin.zpu_config.all; +use zylin.zpupkg.all; + +entity dram is +port (clk : in std_logic; + areset : in std_logic; + mem_writeEnable : in std_logic; + mem_readEnable : in std_logic; + mem_addr : in std_logic_vector(maxAddrBit downto 0); + mem_write : in std_logic_vector(wordSize-1 downto 0); + mem_read : out std_logic_vector(wordSize-1 downto 0); + mem_busy : out std_logic; + mem_writeMask : in std_logic_vector(wordBytes-1 downto 0)); +end dram; + +architecture dram_arch of dram is + +type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); + +shared variable ram : ram_type := +( +0 => x"800b0b0b", +1 => x"0b0b8070", +2 => x"0b0b80e5", +3 => x"d00c3a0b", +4 => x"0b0bbed7", +5 => x"04000000", +6 => x"00000000", +7 => x"00000000", +8 => x"80088408", +9 => x"88080b0b", +10 => x"0bbfa72d", +11 => x"880c840c", +12 => x"800c0400", +13 => x"00000000", +14 => x"00000000", +15 => x"00000000", +16 => x"71fd0608", +17 => x"72830609", +18 => x"81058205", +19 => x"832b2a83", +20 => x"ffff0652", +21 => x"0b0b0400", +22 => x"00000000", +23 => x"00000000", +24 => x"71fd0608", +25 => x"83ffff73", +26 => x"83060981", +27 => x"05820583", +28 => x"2b2b0906", +29 => x"7383ffff", +30 => x"0b0b0b0b", +31 => x"83a70400", +32 => x"72098105", +33 => x"72057373", +34 => x"09060906", +35 => x"73097306", +36 => x"070a8106", +37 => x"530b0b51", +38 => x"04000000", +39 => x"00000000", +40 => x"72722473", +41 => x"732e0753", +42 => x"0b0b5104", +43 => x"00000000", +44 => x"00000000", +45 => x"00000000", +46 => x"00000000", +47 => x"00000000", +48 => x"71737109", +49 => x"71068106", +50 => x"30720a10", +51 => x"0a720a10", +52 => x"0a31050a", +53 => x"81065151", +54 => x"530b0b51", +55 => x"04000000", +56 => x"72722673", +57 => x"732e0753", +58 => x"0b0b5104", +59 => x"00000000", +60 => x"00000000", +61 => x"00000000", +62 => x"00000000", +63 => x"00000000", +64 => x"00000000", +65 => x"00000000", +66 => x"00000000", +67 => x"00000000", +68 => x"00000000", +69 => x"00000000", +70 => x"00000000", +71 => x"00000000", +72 => x"0b0b0b88", +73 => x"c6040000", +74 => x"00000000", +75 => x"00000000", +76 => x"00000000", +77 => x"00000000", +78 => x"00000000", +79 => x"00000000", +80 => x"720a722b", +81 => x"0a530b0b", +82 => x"51040000", +83 => x"00000000", +84 => x"00000000", +85 => x"00000000", +86 => x"00000000", +87 => x"00000000", +88 => x"72729f06", +89 => x"0981050b", +90 => x"0b0b88a7", +91 => x"05040000", +92 => x"00000000", +93 => x"00000000", +94 => x"00000000", +95 => x"00000000", +96 => x"72722aff", +97 => x"739f062a", +98 => x"0974090a", +99 => x"8106ff05", +100 => x"0607530b", +101 => x"0b510400", +102 => x"00000000", +103 => x"00000000", +104 => x"7171530b", +105 => x"0b510406", +106 => x"73830609", +107 => x"81058205", +108 => x"832b0b2b", +109 => x"0772fc06", +110 => x"0c515104", +111 => x"00000000", +112 => x"72098105", +113 => x"72050970", +114 => x"81050906", +115 => x"0a810653", +116 => x"0b0b5104", +117 => x"00000000", +118 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x"43000000", +3180 => x"64756d6d", +3181 => x"792e6578", +3182 => x"65000000", +3183 => x"00010202", +3184 => x"03030303", +3185 => x"04040404", +3186 => x"04040404", +3187 => x"05050505", +3188 => x"05050505", +3189 => x"05050505", +3190 => x"05050505", +3191 => x"06060606", +3192 => x"06060606", +3193 => x"06060606", +3194 => x"06060606", +3195 => x"06060606", +3196 => x"06060606", +3197 => x"06060606", +3198 => x"06060606", +3199 => x"07070707", +3200 => x"07070707", +3201 => x"07070707", +3202 => x"07070707", +3203 => x"07070707", +3204 => x"07070707", +3205 => x"07070707", +3206 => x"07070707", +3207 => x"07070707", +3208 => x"07070707", +3209 => x"07070707", +3210 => x"07070707", +3211 => x"07070707", +3212 => x"07070707", +3213 => x"07070707", +3214 => x"07070707", +3215 => x"08080808", +3216 => x"08080808", +3217 => x"08080808", +3218 => x"08080808", +3219 => x"08080808", +3220 => x"08080808", +3221 => x"08080808", +3222 => x"08080808", +3223 => x"08080808", +3224 => x"08080808", +3225 => x"08080808", +3226 => x"08080808", +3227 => x"08080808", +3228 => x"08080808", +3229 => x"08080808", +3230 => x"08080808", +3231 => x"08080808", +3232 => x"08080808", +3233 => x"08080808", +3234 => x"08080808", +3235 => x"08080808", +3236 => x"08080808", +3237 => x"08080808", +3238 => x"08080808", +3239 => x"08080808", +3240 => x"08080808", +3241 => x"08080808", +3242 => x"08080808", +3243 => x"08080808", +3244 => x"08080808", +3245 => x"08080808", +3246 => x"08080808", +3247 => x"00ffffff", +3248 => x"ff00ffff", +3249 => x"ffff00ff", +3250 => x"ffffff00", +3251 => x"00000000", +3252 => x"00000000", +3253 => x"00000000", +3254 => x"00003ab8", +3255 => x"000186a0", -- iterations +3256 => x"00000000", +3257 => x"00000000", +3258 => x"00000000", +3259 => x"00000000", +3260 => x"00000000", +3261 => x"00000000", +3262 => x"00000000", +3263 => x"00000000", +3264 => x"00000000", +3265 => x"00000000", +3266 => x"00000000", +3267 => x"00000000", +3268 => x"00000000", +3269 => x"ffffffff", +3270 => x"00000000", +3271 => x"00020000", +3272 => x"00000000", +3273 => x"00000000", +3274 => x"00003320", +3275 => x"00003320", +3276 => x"00003328", +3277 => x"00003328", +3278 => x"00003330", +3279 => x"00003330", +3280 => x"00003338", +3281 => x"00003338", +3282 => x"00003340", +3283 => x"00003340", +3284 => x"00003348", +3285 => x"00003348", +3286 => x"00003350", +3287 => x"00003350", +3288 => x"00003358", +3289 => x"00003358", +3290 => x"00003360", +3291 => x"00003360", +3292 => x"00003368", +3293 => x"00003368", +3294 => x"00003370", +3295 => x"00003370", +3296 => x"00003378", +3297 => x"00003378", +3298 => x"00003380", +3299 => x"00003380", +3300 => x"00003388", +3301 => x"00003388", +3302 => x"00003390", +3303 => x"00003390", +3304 => x"00003398", +3305 => x"00003398", +3306 => x"000033a0", +3307 => x"000033a0", +3308 => x"000033a8", +3309 => x"000033a8", +3310 => x"000033b0", +3311 => x"000033b0", +3312 => x"000033b8", +3313 => x"000033b8", +3314 => x"000033c0", +3315 => x"000033c0", +3316 => x"000033c8", +3317 => x"000033c8", +3318 => x"000033d0", +3319 => x"000033d0", +3320 => x"000033d8", +3321 => x"000033d8", +3322 => x"000033e0", +3323 => x"000033e0", +3324 => x"000033e8", +3325 => x"000033e8", +3326 => x"000033f0", +3327 => x"000033f0", +3328 => x"000033f8", +3329 => x"000033f8", +3330 => x"00003400", +3331 => x"00003400", +3332 => x"00003408", +3333 => x"00003408", +3334 => x"00003410", +3335 => x"00003410", +3336 => x"00003418", +3337 => x"00003418", +3338 => x"00003420", +3339 => x"00003420", +3340 => x"00003428", +3341 => x"00003428", +3342 => x"00003430", +3343 => x"00003430", +3344 => x"00003438", +3345 => x"00003438", +3346 => x"00003440", +3347 => x"00003440", +3348 => x"00003448", +3349 => x"00003448", +3350 => x"00003450", +3351 => x"00003450", +3352 => x"00003458", +3353 => x"00003458", +3354 => x"00003460", +3355 => x"00003460", +3356 => x"00003468", +3357 => x"00003468", +3358 => x"00003470", +3359 => x"00003470", +3360 => x"00003478", +3361 => x"00003478", +3362 => x"00003480", +3363 => x"00003480", +3364 => x"00003488", +3365 => x"00003488", +3366 => x"00003490", +3367 => x"00003490", +3368 => x"00003498", +3369 => x"00003498", +3370 => x"000034a0", +3371 => x"000034a0", +3372 => x"000034a8", +3373 => x"000034a8", +3374 => x"000034b0", +3375 => x"000034b0", +3376 => x"000034b8", +3377 => x"000034b8", +3378 => x"000034c0", +3379 => x"000034c0", +3380 => x"000034c8", +3381 => x"000034c8", +3382 => x"000034d0", +3383 => x"000034d0", +3384 => x"000034d8", +3385 => x"000034d8", +3386 => x"000034e0", +3387 => x"000034e0", +3388 => x"000034e8", +3389 => x"000034e8", +3390 => x"000034f0", +3391 => x"000034f0", +3392 => x"000034f8", +3393 => x"000034f8", +3394 => x"00003500", +3395 => x"00003500", +3396 => x"00003508", +3397 => x"00003508", +3398 => x"00003510", +3399 => x"00003510", +3400 => x"00003518", +3401 => x"00003518", +3402 => x"00003520", +3403 => x"00003520", +3404 => x"00003528", +3405 => x"00003528", +3406 => x"00003530", +3407 => x"00003530", +3408 => x"00003538", +3409 => x"00003538", +3410 => x"00003540", +3411 => x"00003540", +3412 => x"00003548", +3413 => x"00003548", +3414 => x"00003550", +3415 => x"00003550", +3416 => x"00003558", +3417 => x"00003558", +3418 => x"00003560", +3419 => x"00003560", +3420 => x"00003568", +3421 => x"00003568", +3422 => x"00003570", +3423 => x"00003570", +3424 => x"00003578", +3425 => x"00003578", +3426 => x"00003580", +3427 => x"00003580", +3428 => x"00003588", +3429 => x"00003588", +3430 => x"00003590", +3431 => x"00003590", +3432 => x"00003598", +3433 => x"00003598", +3434 => x"000035a0", +3435 => x"000035a0", +3436 => x"000035a8", +3437 => x"000035a8", +3438 => x"000035b0", +3439 => x"000035b0", +3440 => x"000035b8", +3441 => x"000035b8", +3442 => x"000035c0", +3443 => x"000035c0", +3444 => x"000035c8", +3445 => x"000035c8", +3446 => x"000035d0", +3447 => x"000035d0", +3448 => x"000035d8", +3449 => x"000035d8", +3450 => x"000035e0", +3451 => x"000035e0", +3452 => x"000035e8", +3453 => x"000035e8", +3454 => x"000035f0", +3455 => x"000035f0", +3456 => x"000035f8", +3457 => x"000035f8", +3458 => x"00003600", +3459 => x"00003600", +3460 => x"00003608", +3461 => x"00003608", +3462 => x"00003610", +3463 => x"00003610", +3464 => x"00003618", +3465 => x"00003618", +3466 => x"00003620", +3467 => x"00003620", +3468 => x"00003628", +3469 => x"00003628", +3470 => x"00003630", +3471 => x"00003630", +3472 => x"00003638", +3473 => x"00003638", +3474 => x"00003640", +3475 => x"00003640", +3476 => x"00003648", +3477 => x"00003648", +3478 => x"00003650", +3479 => x"00003650", +3480 => x"00003658", +3481 => x"00003658", +3482 => x"00003660", +3483 => x"00003660", +3484 => x"00003668", +3485 => x"00003668", +3486 => x"00003670", +3487 => x"00003670", +3488 => x"00003678", +3489 => x"00003678", +3490 => x"00003680", +3491 => x"00003680", +3492 => x"00003688", +3493 => x"00003688", +3494 => x"00003690", +3495 => x"00003690", +3496 => x"00003698", +3497 => x"00003698", +3498 => x"000036a0", +3499 => x"000036a0", +3500 => x"000036a8", +3501 => x"000036a8", +3502 => x"000036b0", +3503 => x"000036b0", +3504 => x"000036b8", +3505 => x"000036b8", +3506 => x"000036c0", +3507 => x"000036c0", +3508 => x"000036c8", +3509 => x"000036c8", +3510 => x"000036d0", +3511 => x"000036d0", +3512 => x"000036d8", +3513 => x"000036d8", +3514 => x"000036e0", +3515 => x"000036e0", +3516 => x"000036e8", +3517 => x"000036e8", +3518 => x"000036f0", +3519 => x"000036f0", +3520 => x"000036f8", +3521 => x"000036f8", +3522 => x"00003700", +3523 => x"00003700", +3524 => x"00003708", +3525 => x"00003708", +3526 => x"00003710", +3527 => x"00003710", +3528 => x"00003718", +3529 => x"00003718", +3530 => x"0000372c", +3531 => x"00000000", +3532 => x"00003994", +3533 => x"000039f0", +3534 => x"00003a4c", +3535 => x"00000000", +3536 => x"00000000", +3537 => x"00000000", +3538 => x"00000000", +3539 => x"00000000", +3540 => x"00000000", +3541 => x"00000000", +3542 => x"00000000", +3543 => x"00000000", +3544 => x"000031ac", +3545 => x"00000000", +3546 => x"00000000", +3547 => x"00000000", +3548 => x"00000000", +3549 => x"00000000", +3550 => x"00000000", +3551 => x"00000000", +3552 => x"00000000", +3553 => x"00000000", +3554 => x"00000000", +3555 => x"00000000", +3556 => x"00000000", +3557 => x"00000000", +3558 => x"00000000", +3559 => x"00000000", +3560 => x"00000000", +3561 => x"00000000", +3562 => x"00000000", +3563 => x"00000000", +3564 => x"00000000", +3565 => x"00000000", +3566 => x"00000000", +3567 => x"00000000", +3568 => x"00000000", +3569 => x"00000000", +3570 => x"00000000", +3571 => x"00000000", +3572 => x"00000000", +3573 => x"00000001", +3574 => x"330eabcd", +3575 => x"1234e66d", +3576 => x"deec0005", +3577 => x"000b0000", +3578 => x"00000000", +3579 => x"00000000", +3580 => x"00000000", +3581 => x"00000000", +3582 => x"00000000", +3583 => x"00000000", +3584 => x"00000000", +3585 => x"00000000", +3586 => x"00000000", +3587 => x"00000000", +3588 => x"00000000", +3589 => x"00000000", +3590 => x"00000000", +3591 => x"00000000", +3592 => x"00000000", +3593 => x"00000000", +3594 => x"00000000", +3595 => x"00000000", +3596 => x"00000000", +3597 => x"00000000", +3598 => x"00000000", +3599 => x"00000000", +3600 => x"00000000", +3601 => x"00000000", +3602 => x"00000000", +3603 => x"00000000", +3604 => x"00000000", +3605 => x"00000000", +3606 => x"00000000", +3607 => x"00000000", +3608 => x"00000000", +3609 => x"00000000", +3610 => x"00000000", +3611 => x"00000000", +3612 => x"00000000", +3613 => x"00000000", +3614 => x"00000000", +3615 => x"00000000", +3616 => x"00000000", +3617 => x"00000000", +3618 => x"00000000", +3619 => x"00000000", +3620 => x"00000000", +3621 => x"00000000", +3622 => x"00000000", +3623 => x"00000000", +3624 => x"00000000", +3625 => x"00000000", +3626 => x"00000000", +3627 => x"00000000", +3628 => x"00000000", +3629 => x"00000000", +3630 => x"00000000", +3631 => x"00000000", +3632 => x"00000000", +3633 => x"00000000", +3634 => x"00000000", +3635 => x"00000000", +3636 => x"00000000", +3637 => x"00000000", +3638 => x"00000000", +3639 => x"00000000", +3640 => x"00000000", +3641 => x"00000000", +3642 => x"00000000", +3643 => x"00000000", +3644 => x"00000000", +3645 => x"00000000", +3646 => x"00000000", +3647 => x"00000000", +3648 => x"00000000", +3649 => x"00000000", +3650 => x"00000000", +3651 => x"00000000", +3652 => x"00000000", +3653 => x"00000000", +3654 => x"00000000", +3655 => x"00000000", +3656 => x"00000000", +3657 => x"00000000", +3658 => x"00000000", +3659 => x"00000000", +3660 => x"00000000", +3661 => x"00000000", +3662 => x"00000000", +3663 => x"00000000", +3664 => x"00000000", +3665 => x"00000000", +3666 => x"00000000", +3667 => x"00000000", +3668 => x"00000000", +3669 => x"00000000", +3670 => x"00000000", +3671 => x"00000000", +3672 => x"00000000", +3673 => x"00000000", +3674 => x"00000000", +3675 => x"00000000", +3676 => x"00000000", +3677 => x"00000000", +3678 => x"00000000", +3679 => x"00000000", +3680 => x"00000000", +3681 => x"00000000", +3682 => x"00000000", +3683 => x"00000000", +3684 => x"00000000", +3685 => x"00000000", +3686 => x"00000000", +3687 => x"00000000", +3688 => x"00000000", +3689 => x"00000000", +3690 => x"00000000", +3691 => x"00000000", +3692 => x"00000000", +3693 => x"00000000", +3694 => x"00000000", +3695 => x"00000000", +3696 => x"00000000", +3697 => x"00000000", +3698 => x"00000000", +3699 => x"00000000", +3700 => x"00000000", +3701 => x"00000000", +3702 => x"00000000", +3703 => x"00000000", +3704 => x"00000000", +3705 => x"00000000", +3706 => x"00000000", +3707 => x"00000000", +3708 => x"00000000", +3709 => x"00000000", +3710 => x"00000000", +3711 => x"00000000", +3712 => x"00000000", +3713 => x"00000000", +3714 => x"00000000", +3715 => x"00000000", +3716 => x"00000000", +3717 => x"00000000", +3718 => x"00000000", +3719 => x"00000000", +3720 => x"00000000", +3721 => x"00000000", +3722 => x"00000000", +3723 => x"00000000", +3724 => x"00000000", +3725 => x"00000000", +3726 => x"00000000", +3727 => x"00000000", +3728 => x"00000000", +3729 => x"00000000", +3730 => x"00000000", +3731 => x"00000000", +3732 => x"00000000", +3733 => x"00000000", +3734 => x"00000000", +3735 => x"00000000", +3736 => x"00000000", +3737 => x"00000000", +3738 => x"00000000", +3739 => x"00000000", +3740 => x"00000000", +3741 => x"00000000", +3742 => x"00000000", +3743 => x"00000000", +3744 => x"00000000", +3745 => x"00000000", +3746 => x"00000000", +3747 => x"00000000", +3748 => x"00000000", +3749 => x"00000000", +3750 => x"00000000", +3751 => x"00000000", +3752 => x"00000000", +3753 => x"00000000", +3754 => x"000031b0", +3755 => x"ffffffff", +3756 => x"00000000", +3757 => x"ffffffff", +3758 => x"00000000", + others => x"00000000" +); + +begin + +mem_busy <= '0'; + +process (clk) +begin + if (clk'event and clk = '1') then + if (mem_writeEnable = '1') then + ram(conv_integer(mem_addr)) := mem_write; + end if; + mem_read <= ram(conv_integer(mem_addr)); + end if; +end process; + + + + +end dram_arch; diff --git a/zpu/hdl/zpu4/src/bram_dmips.vhd b/zpu/hdl/zpu4/src/bram_dmips.vhd new file mode 100644 index 0000000..1c85e0d --- /dev/null +++ b/zpu/hdl/zpu4/src/bram_dmips.vhd @@ -0,0 +1,3717 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity dualport_ram is +port (clk : in std_logic; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit); + memAWrite : in std_logic_vector(wordSize-1 downto 0); + memARead : out std_logic_vector(wordSize-1 downto 0); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit); + memBWrite : in std_logic_vector(wordSize-1 downto 0); + memBRead : out std_logic_vector(wordSize-1 downto 0)); +end dualport_ram; + +architecture dualport_ram_arch of dualport_ram is + + +type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); + +shared variable ram : ram_type := +( +0 => x"0b0b0b0b", +1 => x"80700b0b", +2 => x"80e2a40c", +3 => x"3a0b0b80", +4 => x"c6fc0400", +5 => x"00000000", +6 => x"00000000", +7 => x"00000000", +8 => x"80088408", +9 => x"88080b0b", +10 => x"80c7c32d", +11 => x"880c840c", +12 => x"800c0400", +13 => x"00000000", +14 => x"00000000", +15 => x"00000000", +16 => x"71fd0608", +17 => x"72830609", +18 => x"81058205", +19 => x"832b2a83", +20 => x"ffff0652", +21 => x"04000000", +22 => x"00000000", +23 => x"00000000", +24 => x"71fd0608", +25 => x"83ffff73", +26 => x"83060981", +27 => x"05820583", +28 => x"2b2b0906", +29 => x"7383ffff", +30 => x"0b0b0b0b", +31 => x"83a70400", +32 => x"72098105", +33 => x"72057373", +34 => x"09060906", +35 => x"73097306", +36 => x"070a8106", +37 => x"53510400", +38 => x"00000000", +39 => x"00000000", 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x"0000329c", +3243 => x"000032a4", +3244 => x"000032a4", +3245 => x"000032ac", +3246 => x"000032ac", +3247 => x"000032b4", +3248 => x"000032b4", +3249 => x"000032bc", +3250 => x"000032bc", +3251 => x"000032c4", +3252 => x"000032c4", +3253 => x"000032cc", +3254 => x"000032cc", +3255 => x"000032d4", +3256 => x"000032d4", +3257 => x"000032dc", +3258 => x"000032dc", +3259 => x"000032e4", +3260 => x"000032e4", +3261 => x"000032ec", +3262 => x"000032ec", +3263 => x"000032f4", +3264 => x"000032f4", +3265 => x"000032fc", +3266 => x"000032fc", +3267 => x"00003304", +3268 => x"00003304", +3269 => x"0000330c", +3270 => x"0000330c", +3271 => x"00003314", +3272 => x"00003314", +3273 => x"0000331c", +3274 => x"0000331c", +3275 => x"00003324", +3276 => x"00003324", +3277 => x"0000332c", +3278 => x"0000332c", +3279 => x"00003334", +3280 => x"00003334", +3281 => x"0000333c", +3282 => x"0000333c", +3283 => x"00003344", +3284 => x"00003344", +3285 => x"0000334c", +3286 => x"0000334c", +3287 => x"00003354", +3288 => x"00003354", +3289 => x"0000335c", +3290 => x"0000335c", +3291 => x"00003364", +3292 => x"00003364", +3293 => x"0000336c", +3294 => x"0000336c", +3295 => x"00003374", +3296 => x"00003374", +3297 => x"0000337c", +3298 => x"0000337c", +3299 => x"00003384", +3300 => x"00003384", +3301 => x"0000338c", +3302 => x"0000338c", +3303 => x"00003394", +3304 => x"00003394", +3305 => x"0000339c", +3306 => x"0000339c", +3307 => x"000033a4", +3308 => x"000033a4", +3309 => x"000033ac", +3310 => x"000033ac", +3311 => x"000033b4", +3312 => x"000033b4", +3313 => x"000033bc", +3314 => x"000033bc", +3315 => x"000033c4", +3316 => x"000033c4", +3317 => x"000033cc", +3318 => x"000033cc", +3319 => x"000033d4", +3320 => x"000033d4", +3321 => x"000033dc", +3322 => x"000033dc", +3323 => x"000033e4", +3324 => x"000033e4", +3325 => x"000033ec", +3326 => x"000033ec", +3327 => x"000033f4", +3328 => x"000033f4", +3329 => x"000033fc", +3330 => x"000033fc", +3331 => x"00003404", +3332 => x"00003404", +3333 => x"0000340c", +3334 => x"0000340c", +3335 => x"00003414", +3336 => x"00003414", +3337 => x"0000341c", +3338 => x"0000341c", +3339 => x"00003424", +3340 => x"00003424", +3341 => x"0000342c", +3342 => x"0000342c", +3343 => x"00003434", +3344 => x"00003434", +3345 => x"0000343c", +3346 => x"0000343c", +3347 => x"00003444", +3348 => x"00003444", +3349 => x"0000344c", +3350 => x"0000344c", +3351 => x"00003454", +3352 => x"00003454", +3353 => x"0000345c", +3354 => x"0000345c", +3355 => x"00003464", +3356 => x"00003464", +3357 => x"0000346c", +3358 => x"0000346c", +3359 => x"00003474", +3360 => x"00003474", +3361 => x"0000347c", +3362 => x"0000347c", +3363 => x"00003484", +3364 => x"00003484", +3365 => x"0000348c", +3366 => x"0000348c", +3367 => x"00003494", +3368 => x"00003494", +3369 => x"0000349c", +3370 => x"0000349c", +3371 => x"000034a4", +3372 => x"000034a4", +3373 => x"000034ac", +3374 => x"000034ac", +3375 => x"000034b4", +3376 => x"000034b4", +3377 => x"000034bc", +3378 => x"000034bc", +3379 => x"000034c4", +3380 => x"000034c4", +3381 => x"000034cc", +3382 => x"000034cc", +3383 => x"000034d4", +3384 => x"000034d4", +3385 => x"000034dc", +3386 => x"000034dc", +3387 => x"000034e4", +3388 => x"000034e4", +3389 => x"000034ec", +3390 => x"000034ec", +3391 => x"000034f4", +3392 => x"000034f4", +3393 => x"000034fc", +3394 => x"000034fc", +3395 => x"00003504", +3396 => x"00003504", +3397 => x"0000350c", +3398 => x"0000350c", +3399 => x"00003514", +3400 => x"00003514", +3401 => x"0000351c", +3402 => x"0000351c", +3403 => x"00003524", +3404 => x"00003524", +3405 => x"0000352c", +3406 => x"0000352c", +3407 => x"00003534", +3408 => x"00003534", +3409 => x"0000353c", +3410 => x"0000353c", +3411 => x"00003544", +3412 => x"00003544", +3413 => x"0000354c", +3414 => x"0000354c", +3415 => x"00003554", +3416 => x"00003554", +3417 => x"0000355c", +3418 => x"0000355c", +3419 => x"00003564", +3420 => x"00003564", +3421 => x"0000356c", +3422 => x"0000356c", +3423 => x"00003580", +3424 => x"00000000", +3425 => x"000037e8", +3426 => x"00003844", +3427 => x"000038a0", +3428 => x"00000000", +3429 => x"00000000", +3430 => x"00000000", +3431 => x"00000000", +3432 => x"00000000", +3433 => x"00000000", +3434 => x"00000000", +3435 => x"00000000", +3436 => x"00000000", +3437 => x"00003100", +3438 => x"00000000", +3439 => x"00000000", +3440 => x"00000000", +3441 => x"00000000", +3442 => x"00000000", +3443 => x"00000000", +3444 => x"00000000", +3445 => x"00000000", +3446 => x"00000000", +3447 => x"00000000", +3448 => x"00000000", +3449 => x"00000000", +3450 => x"00000000", +3451 => x"00000000", +3452 => x"00000000", +3453 => x"00000000", +3454 => x"00000000", +3455 => x"00000000", +3456 => x"00000000", +3457 => x"00000000", +3458 => x"00000000", +3459 => x"00000000", +3460 => x"00000000", +3461 => x"00000000", +3462 => x"00000000", +3463 => x"00000000", +3464 => x"00000000", +3465 => x"00000000", +3466 => x"00000001", +3467 => x"330eabcd", +3468 => x"1234e66d", +3469 => x"deec0005", +3470 => x"000b0000", +3471 => x"00000000", +3472 => x"00000000", +3473 => x"00000000", +3474 => x"00000000", +3475 => x"00000000", +3476 => x"00000000", +3477 => x"00000000", +3478 => x"00000000", +3479 => x"00000000", +3480 => x"00000000", +3481 => x"00000000", +3482 => x"00000000", +3483 => x"00000000", +3484 => x"00000000", +3485 => x"00000000", +3486 => x"00000000", +3487 => x"00000000", +3488 => x"00000000", +3489 => x"00000000", +3490 => x"00000000", +3491 => x"00000000", +3492 => x"00000000", +3493 => x"00000000", +3494 => x"00000000", +3495 => x"00000000", +3496 => x"00000000", +3497 => x"00000000", +3498 => x"00000000", +3499 => x"00000000", +3500 => x"00000000", +3501 => x"00000000", +3502 => x"00000000", +3503 => x"00000000", +3504 => x"00000000", +3505 => x"00000000", +3506 => x"00000000", +3507 => x"00000000", +3508 => x"00000000", +3509 => x"00000000", +3510 => x"00000000", +3511 => x"00000000", +3512 => x"00000000", +3513 => x"00000000", +3514 => x"00000000", +3515 => x"00000000", +3516 => x"00000000", +3517 => x"00000000", +3518 => x"00000000", +3519 => x"00000000", +3520 => x"00000000", +3521 => x"00000000", +3522 => x"00000000", +3523 => x"00000000", +3524 => x"00000000", +3525 => x"00000000", +3526 => x"00000000", +3527 => x"00000000", +3528 => x"00000000", +3529 => x"00000000", +3530 => x"00000000", +3531 => x"00000000", +3532 => x"00000000", +3533 => x"00000000", +3534 => x"00000000", +3535 => x"00000000", +3536 => x"00000000", +3537 => x"00000000", +3538 => x"00000000", +3539 => x"00000000", +3540 => x"00000000", +3541 => x"00000000", +3542 => x"00000000", +3543 => x"00000000", +3544 => x"00000000", +3545 => x"00000000", +3546 => x"00000000", +3547 => x"00000000", +3548 => x"00000000", +3549 => x"00000000", +3550 => x"00000000", +3551 => x"00000000", +3552 => x"00000000", +3553 => x"00000000", +3554 => x"00000000", +3555 => x"00000000", +3556 => x"00000000", +3557 => x"00000000", +3558 => x"00000000", +3559 => x"00000000", +3560 => x"00000000", +3561 => x"00000000", +3562 => x"00000000", +3563 => x"00000000", +3564 => x"00000000", +3565 => x"00000000", +3566 => x"00000000", +3567 => x"00000000", +3568 => x"00000000", +3569 => x"00000000", +3570 => x"00000000", +3571 => x"00000000", +3572 => x"00000000", +3573 => x"00000000", +3574 => x"00000000", +3575 => x"00000000", +3576 => x"00000000", +3577 => x"00000000", +3578 => x"00000000", +3579 => x"00000000", +3580 => x"00000000", +3581 => x"00000000", +3582 => x"00000000", +3583 => x"00000000", +3584 => x"00000000", +3585 => x"00000000", +3586 => x"00000000", +3587 => x"00000000", +3588 => x"00000000", +3589 => x"00000000", +3590 => x"00000000", +3591 => x"00000000", +3592 => x"00000000", +3593 => x"00000000", +3594 => x"00000000", +3595 => x"00000000", +3596 => x"00000000", +3597 => x"00000000", +3598 => x"00000000", +3599 => x"00000000", +3600 => x"00000000", +3601 => x"00000000", +3602 => x"00000000", +3603 => x"00000000", +3604 => x"00000000", +3605 => x"00000000", +3606 => x"00000000", +3607 => x"00000000", +3608 => x"00000000", +3609 => x"00000000", +3610 => x"00000000", +3611 => x"00000000", +3612 => x"00000000", +3613 => x"00000000", +3614 => x"00000000", +3615 => x"00000000", +3616 => x"00000000", +3617 => x"00000000", +3618 => x"00000000", +3619 => x"00000000", +3620 => x"00000000", +3621 => x"00000000", +3622 => x"00000000", +3623 => x"00000000", +3624 => x"00000000", +3625 => x"00000000", +3626 => x"00000000", +3627 => x"00000000", +3628 => x"00000000", +3629 => x"00000000", +3630 => x"00000000", +3631 => x"00000000", +3632 => x"00000000", +3633 => x"00000000", +3634 => x"00000000", +3635 => x"00000000", +3636 => x"00000000", +3637 => x"00000000", +3638 => x"00000000", +3639 => x"00000000", +3640 => x"00000000", +3641 => x"00000000", +3642 => x"00000000", +3643 => x"00000000", +3644 => x"00000000", +3645 => x"00000000", +3646 => x"00000000", +3647 => x"00003104", +3648 => x"ffffffff", +3649 => x"00000000", +3650 => x"ffffffff", +3651 => x"00000000", + others => x"00000000" +); + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then + report "write collision" severity failure; + end if; + + if (memAWriteEnable = '1') then + ram(conv_integer(memAAddr)) := memAWrite; + memARead <= memAWrite; + else + memARead <= ram(conv_integer(memAAddr)); + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (memBWriteEnable = '1') then + ram(conv_integer(memBAddr)) := memBWrite; + memBRead <= memBWrite; + else + memBRead <= ram(conv_integer(memBAddr)); + end if; + end if; +end process; + + + + +end dualport_ram_arch; diff --git a/zpu/hdl/zpu4/src/build.xml b/zpu/hdl/zpu4/src/build.xml new file mode 100644 index 0000000..e1b268a --- /dev/null +++ b/zpu/hdl/zpu4/src/build.xml @@ -0,0 +1,114 @@ + + + + + + + eCosBoard firmware build file + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/zpu/hdl/zpu4/src/clocks.vhd b/zpu/hdl/zpu4/src/clocks.vhd new file mode 100644 index 0000000..a352b3c --- /dev/null +++ b/zpu/hdl/zpu4/src/clocks.vhd @@ -0,0 +1,246 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library UNISIM; +use UNISIM.vcomponents.all; + +entity clocks is + port ( areset : in std_logic; + cpu_clk_p : in std_logic; + sdr_clk_fb_p : in std_logic; + cpu_clk : out std_logic; + cpu_clk_2x : out std_logic; + cpu_clk_4x : out std_logic; + ddr_in_clk : out std_logic; + ddr_in_clk_2x : out std_logic; + locked : out std_logic_vector(2 downto 0)); +end clocks; + +architecture behave of clocks is + +signal low : std_logic; + +signal cpu_clk_in : std_logic; +signal sdr_clk_fb_in : std_logic; + +signal dcm_cpu1 : std_logic; +signal dcm_cpu2 : std_logic; +signal dcm_cpu2_dum : std_logic; +signal dcm_cpu4 : std_logic; +signal dcm_ddr2 : std_logic; +signal dcm_ddr2_2x : std_logic; + +signal cpu_clk_int : std_logic; +signal cpu_clk_2x_int : std_logic; +signal cpu_clk_2x_dum_int : std_logic; +signal cpu_clk_4x_int : std_logic; +signal ddr_in_clk_int : std_logic; +signal ddr_in_clk_2x_int : std_logic; + +signal dcm1_locked_del : std_logic; +signal dcm2_locked_del : std_logic; +signal dcm2_reset : std_logic; +signal dcm3_reset : std_logic; + +signal locked_int : std_logic_vector(2 downto 0); +signal del_addr : std_logic_vector(3 downto 0); + +begin + + low <= '0'; + del_addr <= "1111"; + + cpu_clk <= cpu_clk_int; + cpu_clk_2x <= cpu_clk_2x_int; + cpu_clk_4x <= cpu_clk_4x_int; + ddr_in_clk <= ddr_in_clk_int; + ddr_in_clk_2x <= ddr_in_clk_2x_int; + locked <= locked_int; + + + CPU_IBUFG: + IBUFG port map ( + O => cpu_clk_in, + I => cpu_clk_p); + + SDR_FB_IBUFG: + IBUFG port map ( + O => sdr_clk_fb_in, + I => sdr_clk_fb_p); + + dcm2_rst: + SRL16 generic map ( + INIT => X"0000") + port map ( + Q => dcm1_locked_del, + A0 => del_addr(0), + A1 => del_addr(1), + A2 => del_addr(2), + A3 => del_addr(3), + CLK => cpu_clk_int, + D => locked_int(0)); + + dcm2_reset <= not(dcm1_locked_del); + + dcm3_rst: + SRL16 generic map ( + INIT => X"0000") + port map ( + Q => dcm2_locked_del, + A0 => del_addr(0), + A1 => del_addr(1), + A2 => del_addr(2), + A3 => del_addr(3), + CLK => cpu_clk_int, + D => locked_int(1)); + + dcm3_reset <= not(dcm2_locked_del); + + cpu1_dcm: + DCM generic map ( + CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 + -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 + CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 + CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32 + CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature + CLKIN_PERIOD => 15.625, -- Specify period of input clock + CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE + CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or + -- an integer from 0 to 15 + DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis + DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL + DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE + FACTORY_JF => X"8080", -- FACTORY JF Values + PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 + STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE + port map ( + CLK0 => dcm_cpu1, -- 0 degree DCM CLK ouptput + CLK180 => open, -- 180 degree DCM CLK output + CLK270 => open, -- 270 degree DCM CLK output + CLK2X => dcm_cpu2, -- 2X DCM CLK output + CLK2X180 => open, -- 2X, 180 degree DCM CLK out + CLK90 => open, -- 90 degree DCM CLK output + CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) + CLKFX => open, -- DCM CLK synthesis out (M/D) + CLKFX180 => open, -- 180 degree CLK synthesis out + LOCKED => locked_int(0), -- DCM LOCK status output + PSDONE => open, -- Dynamic phase adjust done output + STATUS => open, -- 8-bit DCM status bits output + CLKFB => cpu_clk_int, -- DCM clock feedback + CLKIN => cpu_clk_in, -- Clock input (from IBUFG, BUFG or DCM) + PSCLK => low, -- Dynamic phase adjust clock input + PSEN => low, -- Dynamic phase adjust enable input + PSINCDEC => low, -- Dynamic phase adjust increment/decrement + RST => areset); -- DCM asynchronous reset input + + cpu2_dcm: + DCM generic map ( + CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 + -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 + CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 + CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32 + CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature + CLKIN_PERIOD => 7.8125, -- Specify period of input clock + CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE + CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or + -- an integer from 0 to 15 + DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis + DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL + DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE + FACTORY_JF => X"8080", -- FACTORY JF Values + PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 + STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE + port map ( + CLK0 => dcm_cpu2_dum, -- 0 degree DCM CLK ouptput + CLK180 => open, -- 180 degree DCM CLK output + CLK270 => open, -- 270 degree DCM CLK output + CLK2X => dcm_cpu4, -- 2X DCM CLK output + CLK2X180 => open, -- 2X, 180 degree DCM CLK out + CLK90 => open, -- 90 degree DCM CLK output + CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) + CLKFX => open, -- DCM CLK synthesis out (M/D) + CLKFX180 => open, -- 180 degree CLK synthesis out + LOCKED => locked_int(1), -- DCM LOCK status output + PSDONE => open, -- Dynamic phase adjust done output + STATUS => open, -- 8-bit DCM status bits output + CLKFB => cpu_clk_2x_dum_int, -- DCM clock feedback + CLKIN => cpu_clk_2x_int, -- Clock input (from IBUFG, BUFG or DCM) + PSCLK => low, -- Dynamic phase adjust clock input + PSEN => low, -- Dynamic phase adjust enable input + PSINCDEC => low, -- Dynamic phase adjust increment/decrement + RST => dcm2_reset); -- DCM asynchronous reset input + + ddr_read_dcm: + DCM generic map ( + CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 + -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 + CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 + CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32 + CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature + CLKIN_PERIOD => 7.8125, -- Specify period of input clock + CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift of NONE, FIXED or VARIABLE +-- CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE + CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or + -- an integer from 0 to 15 + DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis + DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL + DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE + FACTORY_JF => X"8080", -- FACTORY JF Values + PHASE_SHIFT => 103, -- Amount of fixed phase shift from -255 to 255 +-- PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 + STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE + port map ( + CLK0 => dcm_ddr2, -- 0 degree DCM CLK ouptput + CLK180 => open, -- 180 degree DCM CLK output + CLK270 => open, -- 270 degree DCM CLK output + CLK2X => dcm_ddr2_2x, -- 2X DCM CLK output + CLK2X180 => open, -- 2X, 180 degree DCM CLK out + CLK90 => open, -- 90 degree DCM CLK output + CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) + CLKFX => open, -- DCM CLK synthesis out (M/D) + CLKFX180 => open, -- 180 degree CLK synthesis out + LOCKED => locked_int(2), -- DCM LOCK status output + PSDONE => open, -- Dynamic phase adjust done output + STATUS => open, -- 8-bit DCM status bits output + CLKFB => ddr_in_clk_int, -- DCM clock feedback + CLKIN => sdr_clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM) + PSCLK => low, -- Dynamic phase adjust clock input + PSEN => low, -- Dynamic phase adjust enable input + PSINCDEC => low, -- Dynamic phase adjust increment/decrement + RST => dcm3_reset); -- DCM asynchronous reset input + + cpu1: + BUFG port map ( + I => dcm_cpu1, + O => cpu_clk_int); + + cpu2: + BUFG port map ( + I => dcm_cpu2, + O => cpu_clk_2x_int); + + cpu2_dum: + BUFG port map ( + I => dcm_cpu2_dum, + O => cpu_clk_2x_dum_int); + + cpu4: + BUFG port map ( + I => dcm_cpu4, + O => cpu_clk_4x_int); + + ddr_clk: + BUFG port map ( + I => dcm_ddr2, + O => ddr_in_clk_int); + + ddr_clk_2x: + BUFG port map ( + I => dcm_ddr2_2x, + O => ddr_in_clk_2x_int); + +end behave; \ No newline at end of file diff --git a/zpu/hdl/zpu4/src/dmipssmalltrace.do b/zpu/hdl/zpu4/src/dmipssmalltrace.do new file mode 100644 index 0000000..eb4c6fe --- /dev/null +++ b/zpu/hdl/zpu4/src/dmipssmalltrace.do @@ -0,0 +1,26 @@ +set BreakOnAssertion 1 +vlib work + +vcom -93 -explicit zpu_config_trace.vhd +vcom -93 -explicit zpupkg.vhd +vcom -93 -explicit txt_util.vhd +vcom -93 -explicit sim_fpga_top.vhd +vcom -93 -explicit zpu_core_small.vhd +vcom -93 -explicit bram_dmips.vhd +vcom -93 -explicit dram_dmips.vhd +vcom -93 -explicit timer.vhd +vcom -93 -explicit io.vhd +vcom -93 -explicit trace.vhd + + +vsim fpga_top +view wave + +add wave -recursive fpga_top/zpu/* +#--add wave -recursive fpga_top/ioMap/* +#add wave -recursive fpga_top/* +view structure + + +# run ZPU +run 5 ms diff --git a/zpu/hdl/zpu4/src/dmipstrace.do b/zpu/hdl/zpu4/src/dmipstrace.do new file mode 100644 index 0000000..8d5f430 --- /dev/null +++ b/zpu/hdl/zpu4/src/dmipstrace.do @@ -0,0 +1,25 @@ +set BreakOnAssertion 1 +vlib work + +vcom -93 -explicit zpu_config_trace.vhd +vcom -93 -explicit zpupkg.vhd +vcom -93 -explicit txt_util.vhd +vcom -93 -explicit sim_fpga_top.vhd +vcom -93 -explicit zpu_core.vhd +vcom -93 -explicit dram_dmips.vhd +vcom -93 -explicit timer.vhd +vcom -93 -explicit io.vhd +vcom -93 -explicit trace.vhd + + +vsim fpga_top +view wave + +add wave -recursive fpga_top/zpu/* +#--add wave -recursive fpga_top/ioMap/* +#add wave -recursive fpga_top/* +view structure + + +# run ZPU +run 5 ms diff --git a/zpu/hdl/zpu4/src/dmipstraceintstack.do b/zpu/hdl/zpu4/src/dmipstraceintstack.do new file mode 100644 index 0000000..b2addb4 --- /dev/null +++ b/zpu/hdl/zpu4/src/dmipstraceintstack.do @@ -0,0 +1,25 @@ +set BreakOnAssertion 1 +vlib work + +vcom -93 -explicit zpu_config_trace.vhd +vcom -93 -explicit zpupkg.vhd +vcom -93 -explicit txt_util.vhd +vcom -93 -explicit sim_fpga_top.vhd +vcom -93 -explicit zpu_core_intstack.vhd +vcom -93 -explicit dram_dmips.vhd +vcom -93 -explicit timer.vhd +vcom -93 -explicit io.vhd +vcom -93 -explicit trace.vhd + + +vsim fpga_top +view wave + +add wave -recursive fpga_top/zpu/* +#--add wave -recursive fpga_top/ioMap/* +#add wave -recursive fpga_top/* +view structure + + +# run ZPU +run 5 ms diff --git a/zpu/hdl/zpu4/src/dram_dmips.vhd b/zpu/hdl/zpu4/src/dram_dmips.vhd new file mode 100644 index 0000000..e63a27a --- /dev/null +++ b/zpu/hdl/zpu4/src/dram_dmips.vhd @@ -0,0 +1,3702 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity dram is +port (clk : in std_logic; +areset : std_logic; + mem_writeEnable : in std_logic; + mem_readEnable : in std_logic; + mem_addr : in std_logic_vector(maxAddrBit downto 0); + mem_write : in std_logic_vector(wordSize-1 downto 0); + mem_read : out std_logic_vector(wordSize-1 downto 0); + mem_busy : out std_logic; + mem_writeMask : in std_logic_vector(wordBytes-1 downto 0)); +end dram; + +architecture dram_arch of dram is + + +type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); + +shared variable ram : ram_type := +( +0 => x"0b0b0b0b", +1 => x"80700b0b", +2 => x"80e2a40c", +3 => x"3a0b0b80", +4 => x"c6fc0400", +5 => x"00000000", +6 => x"00000000", +7 => x"00000000", +8 => x"80088408", +9 => x"88080b0b", +10 => x"80c7c32d", +11 => x"880c840c", +12 => x"800c0400", +13 => x"00000000", +14 => x"00000000", +15 => x"00000000", +16 => x"71fd0608", +17 => x"72830609", +18 => x"81058205", +19 => x"832b2a83", +20 => x"ffff0652", +21 => x"04000000", +22 => x"00000000", +23 => x"00000000", +24 => x"71fd0608", +25 => x"83ffff73", +26 => x"83060981", +27 => x"05820583", +28 => x"2b2b0906", +29 => x"7383ffff", +30 => x"0b0b0b0b", +31 => x"83a70400", +32 => x"72098105", +33 => x"72057373", +34 => x"09060906", +35 => x"73097306", +36 => x"070a8106", +37 => x"53510400", +38 => x"00000000", +39 => x"00000000", +40 => x"72722473", +41 => x"732e0753", +42 => x"51040000", +43 => x"00000000", +44 => x"00000000", +45 => x"00000000", +46 => x"00000000", +47 => x"00000000", +48 => x"71737109", +49 => x"71068106", +50 => x"30720a10", +51 => x"0a720a10", +52 => x"0a31050a", +53 => x"81065151", +54 => x"53510400", +55 => x"00000000", +56 => x"72722673", +57 => x"732e0753", +58 => x"51040000", +59 => x"00000000", +60 => x"00000000", +61 => x"00000000", +62 => x"00000000", +63 => x"00000000", +64 => x"00000000", +65 => x"00000000", +66 => x"00000000", +67 => x"00000000", +68 => x"00000000", +69 => x"00000000", +70 => x"00000000", +71 => x"00000000", +72 => x"0b0b0b88", +73 => x"c4040000", +74 => x"00000000", +75 => x"00000000", +76 => x"00000000", +77 => x"00000000", +78 => x"00000000", +79 => x"00000000", +80 => x"720a722b", +81 => x"0a535104", +82 => x"00000000", +83 => x"00000000", +84 => x"00000000", +85 => x"00000000", +86 => x"00000000", +87 => x"00000000", +88 => x"72729f06", +89 => x"0981050b", +90 => x"0b0b88a7", +91 => x"05040000", +92 => x"00000000", +93 => x"00000000", +94 => x"00000000", +95 => x"00000000", +96 => x"72722aff", +97 => x"739f062a", +98 => x"0974090a", +99 => x"8106ff05", +100 => x"06075351", +101 => x"04000000", +102 => x"00000000", +103 => x"00000000", +104 => x"71715351", +105 => x"020d0406", +106 => x"73830609", +107 => x"81058205", +108 => x"832b0b2b", +109 => x"0772fc06", +110 => x"0c515104", +111 => x"00000000", +112 => x"72098105", +113 => x"72050970", +114 => x"81050906", +115 => x"0a810653", +116 => x"51040000", +117 => x"00000000", +118 => x"00000000", +119 => x"00000000", +120 => x"72098105", +121 => x"72050970", +122 => x"81050906", +123 => x"0a098106", +124 => x"53510400", +125 => x"00000000", +126 => x"00000000", +127 => x"00000000", +128 => x"71098105", +129 => x"52040000", +130 => x"00000000", +131 => x"00000000", +132 => x"00000000", +133 => x"00000000", +134 => x"00000000", +135 => x"00000000", +136 => x"72720981", +137 => x"05055351", +138 => x"04000000", +139 => x"00000000", +140 => x"00000000", +141 => x"00000000", +142 => x"00000000", +143 => x"00000000", +144 => x"72097206", +145 => x"73730906", +146 => x"07535104", +147 => x"00000000", +148 => x"00000000", +149 => x"00000000", +150 => x"00000000", +151 => x"00000000", +152 => x"71fc0608", +153 => x"72830609", +154 => x"81058305", +155 => x"1010102a", +156 => x"81ff0652", +157 => x"04000000", +158 => x"00000000", +159 => x"00000000", +160 => x"71fc0608", +161 => x"0b0b80e2", +162 => x"90738306", +163 => x"10100508", +164 => x"060b0b0b", +165 => x"88aa0400", +166 => x"00000000", +167 => x"00000000", +168 => x"80088408", +169 => x"88087575", +170 => x"0b0b0baf", +171 => x"ac2d5050", +172 => x"80085688", +173 => x"0c840c80", +174 => x"0c510400", +175 => x"00000000", +176 => x"80088408", +177 => x"88087575", +178 => x"0b0b0baf", +179 => x"f02d5050", +180 => x"80085688", +181 => x"0c840c80", +182 => x"0c510400", +183 => x"00000000", +184 => x"72097081", +185 => x"0509060a", +186 => x"8106ff05", +187 => x"70547106", +188 => x"73097274", +189 => x"05ff0506", +190 => x"07515151", +191 => x"04000000", +192 => x"72097081", +193 => x"0509060a", +194 => x"098106ff", +195 => x"05705471", +196 => x"06730972", +197 => x"7405ff05", +198 => x"06075151", +199 => x"51040000", +200 => x"05ff0504", +201 => x"00000000", +202 => x"00000000", +203 => x"00000000", +204 => x"00000000", +205 => x"00000000", +206 => x"00000000", +207 => x"00000000", +208 => x"810b0b0b", +209 => x"80e2a00c", +210 => x"51040000", +211 => x"00000000", +212 => x"00000000", +213 => x"00000000", +214 => x"00000000", +215 => x"00000000", +216 => x"71810552", +217 => x"04000000", +218 => x"00000000", +219 => x"00000000", +220 => x"00000000", +221 => x"00000000", +222 => x"00000000", +223 => x"00000000", +224 => x"00000000", +225 => x"00000000", +226 => x"00000000", +227 => x"00000000", +228 => x"00000000", +229 => x"00000000", +230 => x"00000000", +231 => x"00000000", +232 => x"02840572", +233 => x"10100552", +234 => x"04000000", +235 => x"00000000", +236 => x"00000000", +237 => x"00000000", +238 => x"00000000", +239 => x"00000000", +240 => x"00000000", +241 => x"00000000", +242 => x"00000000", +243 => x"00000000", +244 => x"00000000", +245 => x"00000000", +246 => x"00000000", +247 => x"00000000", +248 => x"717105ff", +249 => x"05715351", +250 => x"020d0400", +251 => x"00000000", +252 => x"00000000", +253 => x"00000000", +254 => x"00000000", +255 => x"00000000", +256 => x"83d93f80", +257 => x"cbcf3f04", +258 => x"10101010", +259 => x"10101010", +260 => x"10101010", +261 => x"10101010", +262 => x"10101010", +263 => x"10101010", +264 => x"10101010", +265 => x"10101053", +266 => x"51047381", +267 => x"ff067383", +268 => x"06098105", +269 => x"83051010", +270 => x"102b0772", +271 => x"fc060c51", +272 => x"51043c04", +273 => x"72728072", +274 => x"8106ff05", +275 => x"09720605", +276 => x"71105272", +277 => x"0a100a53", +278 => x"72ed3851", +279 => x"51535104", +280 => x"ff3d0d0b", +281 => x"0b80f294", +282 => x"08528412", +283 => x"08708106", +284 => x"515170f6", +285 => x"38710881", +286 => x"ff06800c", +287 => x"833d0d04", +288 => x"ff3d0d0b", +289 => x"0b80f294", +290 => x"08528412", +291 => x"08700a10", +292 => x"0a708106", +293 => x"51515170", +294 => x"f1387372", +295 => x"0c833d0d", +296 => x"0480e2a0", +297 => x"08802ea8", +298 => x"38838080", +299 => x"0b0b0b80", +300 => x"f2940c82", +301 => x"a0800b0b", +302 => x"0b80f298", +303 => x"0c829080", +304 => x"0b80f2a8", +305 => x"0c0b0b80", +306 => x"f29c0b80", +307 => x"f2ac0c04", +308 => x"f8808080", +309 => x"a40b0b0b", +310 => x"80f2940c", +311 => x"f8808082", +312 => x"800b0b0b", +313 => x"80f2980c", +314 => x"f8808084", +315 => x"800b80f2", +316 => x"a80cf880", +317 => x"8080940b", +318 => x"80f2ac0c", +319 => x"f8808080", +320 => x"9c0b80f2", +321 => x"a40cf880", +322 => x"8080a00b", +323 => x"80f2b00c", +324 => x"04f23d0d", +325 => x"600b0b80", +326 => x"f2980856", +327 => x"5d82750c", +328 => x"8059805a", +329 => x"800b8f3d", +330 => x"71101017", +331 => x"70085957", +332 => x"5d5b8076", +333 => x"81ff067c", +334 => x"832b5658", +335 => x"5276537b", +336 => x"519af33f", +337 => x"7d7f7a72", +338 => x"077c7207", +339 => x"71716081", +340 => x"05415f5d", +341 => x"5b595755", +342 => x"7a8724bb", +343 => x"380b0b80", +344 => x"f298087b", +345 => x"10101170", +346 => x"08585155", +347 => x"807681ff", +348 => x"067c832b", +349 => x"56585276", +350 => x"537b519a", +351 => x"b93f7d7f", +352 => x"7a72077c", +353 => x"72077171", +354 => x"60810541", +355 => x"5f5d5b59", +356 => x"5755877b", +357 => x"25c73876", +358 => x"7d0c7784", +359 => x"1e0c7c80", +360 => x"0c903d0d", +361 => x"04ff3d0d", +362 => x"80f2a033", +363 => x"5170a738", +364 => x"80e2ac08", +365 => x"70085252", +366 => x"70802e94", +367 => x"38841280", +368 => x"e2ac0c70", +369 => x"2d80e2ac", +370 => x"08700852", +371 => x"5270ee38", +372 => x"810b80f2", +373 => x"a034833d", +374 => x"0d040480", +375 => x"3d0d0b0b", +376 => x"80f29008", +377 => x"802e8e38", +378 => x"0b0b0b0b", +379 => x"800b802e", +380 => x"09810685", +381 => x"38823d0d", +382 => x"040b0b80", +383 => x"f290510b", +384 => x"0b0bf3fc", +385 => x"3f823d0d", +386 => x"0404ff3d", +387 => x"0d028f05", +388 => x"3352718a", +389 => x"2e8a3871", +390 => x"51fce53f", +391 => x"833d0d04", +392 => x"8d51fcdc", +393 => x"3f7151fc", +394 => x"d73f833d", +395 => x"0d04ce3d", +396 => x"0db53d70", +397 => x"70840552", +398 => x"088c8a5c", +399 => x"56a53d5e", +400 => x"5c807570", +401 => x"81055733", +402 => x"765b5558", +403 => x"73782e80", +404 => x"c1388e3d", +405 => x"5b73a52e", +406 => x"09810680", +407 => x"c5387870", +408 => x"81055a33", +409 => x"547380e4", +410 => x"2e81b638", +411 => x"7380e424", +412 => x"80c63873", +413 => x"80e32ea1", +414 => x"388052a5", +415 => x"51792d80", +416 => x"52735179", +417 => x"2d821858", +418 => x"78708105", +419 => x"5a335473", +420 => x"c4387780", +421 => x"0cb43d0d", +422 => x"047b841d", +423 => x"83123356", +424 => x"5d578052", +425 => x"7351792d", +426 => x"81187970", +427 => x"81055b33", +428 => x"555873ff", +429 => x"a038db39", +430 => x"7380f32e", +431 => x"098106ff", +432 => x"b8387b84", +433 => x"1d710859", +434 => x"5d568077", +435 => x"33555673", +436 => x"762e8d38", +437 => x"81167018", +438 => x"70335755", +439 => x"5674f538", +440 => x"ff165580", +441 => x"7625ffa0", +442 => x"38767081", +443 => x"05583354", +444 => x"80527351", +445 => x"792d8118", +446 => x"75ff1757", +447 => x"57588076", +448 => x"25ff8538", +449 => x"76708105", +450 => x"58335480", +451 => x"52735179", +452 => x"2d811875", +453 => x"ff175757", +454 => x"58758024", +455 => x"cc38fee8", +456 => x"397b841d", +457 => x"71087071", +458 => x"9f2c5953", +459 => x"595d5680", +460 => x"75248195", +461 => x"38757d7c", +462 => x"58565480", +463 => x"5773772e", +464 => x"098106b6", +465 => x"38b07b34", +466 => x"02b50556", +467 => x"7a762e97", +468 => x"38ff1656", +469 => x"75337570", +470 => x"81055734", +471 => x"8117577a", +472 => x"762e0981", +473 => x"06eb3880", +474 => x"7534767d", +475 => x"ff125758", +476 => x"56758024", +477 => x"fef338fe", +478 => x"8f398a52", +479 => x"7351a0f0", +480 => x"3f80080b", +481 => x"0b80d484", +482 => x"05337670", +483 => x"81055834", +484 => x"8a527351", +485 => x"a0963f80", +486 => x"08548008", +487 => x"802effac", +488 => x"388a5273", +489 => x"51a0c93f", +490 => x"80080b0b", +491 => x"80d48405", +492 => x"33767081", +493 => x"0558348a", +494 => x"5273519f", +495 => x"ef3f8008", +496 => x"548008ff", +497 => x"b538ff84", +498 => x"39745276", +499 => x"53b43dff", +500 => x"b8055195", +501 => x"b63fa33d", +502 => x"0856fed9", +503 => x"39803d0d", +504 => x"80c10b81", +505 => x"c0f43480", +506 => x"0b81c2d0", +507 => x"0c70800c", +508 => x"823d0d04", +509 => x"ff3d0d80", +510 => x"0b81c0f4", +511 => x"33525270", +512 => x"80c12e99", +513 => x"387181c2", +514 => x"d0080781", +515 => x"c2d00c80", +516 => x"c20b81c0", +517 => x"f8347080", +518 => x"0c833d0d", +519 => x"04810b81", +520 => x"c2d00807", +521 => x"81c2d00c", +522 => x"80c20b81", +523 => x"c0f83470", +524 => x"800c833d", +525 => x"0d04fd3d", +526 => x"0d757008", +527 => x"8a055353", +528 => x"81c0f433", +529 => x"517080c1", +530 => x"2e8b3873", +531 => x"f3387080", +532 => x"0c853d0d", +533 => x"04ff1270", +534 => x"81c0f008", +535 => x"31740c80", +536 => x"0c853d0d", +537 => x"04fc3d0d", +538 => x"81c0fc08", +539 => x"5574802e", +540 => x"8c387675", +541 => x"08710c81", +542 => x"c0fc0856", +543 => x"548c1553", +544 => x"81c0f008", +545 => x"528a5190", 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x"08080808", +3136 => x"43000000", +3137 => x"64756d6d", +3138 => x"792e6578", +3139 => x"65000000", +3140 => x"00ffffff", +3141 => x"ff00ffff", +3142 => x"ffff00ff", +3143 => x"ffffff00", +3144 => x"00000000", +3145 => x"00000000", +3146 => x"00000000", +3147 => x"0000390c", +3148 => x"000004d2", -- iterations 0x4d2=1234 +3149 => x"00000000", +3150 => x"00000000", +3151 => x"00000000", +3152 => x"00000000", +3153 => x"00000000", +3154 => x"00000000", +3155 => x"00000000", +3156 => x"00000000", +3157 => x"00000000", +3158 => x"00000000", +3159 => x"00000000", +3160 => x"00000000", +3161 => x"00000000", +3162 => x"ffffffff", +3163 => x"00000000", +3164 => x"00020000", +3165 => x"00000000", +3166 => x"00000000", +3167 => x"00003174", +3168 => x"00003174", +3169 => x"0000317c", +3170 => x"0000317c", +3171 => x"00003184", +3172 => x"00003184", +3173 => x"0000318c", +3174 => x"0000318c", +3175 => x"00003194", +3176 => x"00003194", +3177 => x"0000319c", +3178 => x"0000319c", +3179 => x"000031a4", +3180 => x"000031a4", +3181 => x"000031ac", +3182 => x"000031ac", +3183 => x"000031b4", +3184 => x"000031b4", +3185 => x"000031bc", +3186 => x"000031bc", +3187 => x"000031c4", +3188 => x"000031c4", +3189 => x"000031cc", +3190 => x"000031cc", +3191 => x"000031d4", +3192 => x"000031d4", +3193 => x"000031dc", +3194 => x"000031dc", +3195 => x"000031e4", +3196 => x"000031e4", +3197 => x"000031ec", +3198 => x"000031ec", +3199 => x"000031f4", +3200 => x"000031f4", +3201 => x"000031fc", +3202 => x"000031fc", +3203 => x"00003204", +3204 => x"00003204", +3205 => x"0000320c", +3206 => x"0000320c", +3207 => x"00003214", +3208 => x"00003214", +3209 => x"0000321c", +3210 => x"0000321c", +3211 => x"00003224", +3212 => x"00003224", +3213 => x"0000322c", +3214 => x"0000322c", +3215 => x"00003234", +3216 => x"00003234", +3217 => x"0000323c", +3218 => x"0000323c", +3219 => x"00003244", +3220 => x"00003244", +3221 => x"0000324c", +3222 => x"0000324c", +3223 => x"00003254", +3224 => x"00003254", +3225 => x"0000325c", +3226 => x"0000325c", +3227 => x"00003264", +3228 => x"00003264", +3229 => x"0000326c", +3230 => x"0000326c", +3231 => x"00003274", +3232 => x"00003274", +3233 => x"0000327c", +3234 => x"0000327c", +3235 => x"00003284", +3236 => x"00003284", +3237 => x"0000328c", +3238 => x"0000328c", +3239 => x"00003294", +3240 => x"00003294", +3241 => x"0000329c", +3242 => x"0000329c", +3243 => x"000032a4", +3244 => x"000032a4", +3245 => x"000032ac", +3246 => x"000032ac", +3247 => x"000032b4", +3248 => x"000032b4", +3249 => x"000032bc", +3250 => x"000032bc", +3251 => x"000032c4", +3252 => x"000032c4", +3253 => x"000032cc", +3254 => x"000032cc", +3255 => x"000032d4", +3256 => x"000032d4", +3257 => x"000032dc", +3258 => x"000032dc", +3259 => x"000032e4", +3260 => x"000032e4", +3261 => x"000032ec", +3262 => x"000032ec", +3263 => x"000032f4", +3264 => x"000032f4", +3265 => x"000032fc", +3266 => x"000032fc", +3267 => x"00003304", +3268 => x"00003304", +3269 => x"0000330c", +3270 => x"0000330c", +3271 => x"00003314", +3272 => x"00003314", +3273 => x"0000331c", +3274 => x"0000331c", +3275 => x"00003324", +3276 => x"00003324", +3277 => x"0000332c", +3278 => x"0000332c", +3279 => x"00003334", +3280 => x"00003334", +3281 => x"0000333c", +3282 => x"0000333c", +3283 => x"00003344", +3284 => x"00003344", +3285 => x"0000334c", +3286 => x"0000334c", +3287 => x"00003354", +3288 => x"00003354", +3289 => x"0000335c", +3290 => x"0000335c", +3291 => x"00003364", +3292 => x"00003364", +3293 => x"0000336c", +3294 => x"0000336c", +3295 => x"00003374", +3296 => x"00003374", +3297 => x"0000337c", +3298 => x"0000337c", +3299 => x"00003384", +3300 => x"00003384", +3301 => x"0000338c", +3302 => x"0000338c", +3303 => x"00003394", +3304 => x"00003394", +3305 => x"0000339c", +3306 => x"0000339c", +3307 => x"000033a4", +3308 => x"000033a4", +3309 => x"000033ac", +3310 => x"000033ac", +3311 => x"000033b4", +3312 => x"000033b4", +3313 => x"000033bc", +3314 => x"000033bc", +3315 => x"000033c4", +3316 => x"000033c4", +3317 => x"000033cc", +3318 => x"000033cc", +3319 => x"000033d4", +3320 => x"000033d4", +3321 => x"000033dc", +3322 => x"000033dc", +3323 => x"000033e4", +3324 => x"000033e4", +3325 => x"000033ec", +3326 => x"000033ec", +3327 => x"000033f4", +3328 => x"000033f4", +3329 => x"000033fc", +3330 => x"000033fc", +3331 => x"00003404", +3332 => x"00003404", +3333 => x"0000340c", +3334 => x"0000340c", +3335 => x"00003414", +3336 => x"00003414", +3337 => x"0000341c", +3338 => x"0000341c", +3339 => x"00003424", +3340 => x"00003424", +3341 => x"0000342c", +3342 => x"0000342c", +3343 => x"00003434", +3344 => x"00003434", +3345 => x"0000343c", +3346 => x"0000343c", +3347 => x"00003444", +3348 => x"00003444", +3349 => x"0000344c", +3350 => x"0000344c", +3351 => x"00003454", +3352 => x"00003454", +3353 => x"0000345c", +3354 => x"0000345c", +3355 => x"00003464", +3356 => x"00003464", +3357 => x"0000346c", +3358 => x"0000346c", +3359 => x"00003474", +3360 => x"00003474", +3361 => x"0000347c", +3362 => x"0000347c", +3363 => x"00003484", +3364 => x"00003484", +3365 => x"0000348c", +3366 => x"0000348c", +3367 => x"00003494", +3368 => x"00003494", +3369 => x"0000349c", +3370 => x"0000349c", +3371 => x"000034a4", +3372 => x"000034a4", +3373 => x"000034ac", +3374 => x"000034ac", +3375 => x"000034b4", +3376 => x"000034b4", +3377 => x"000034bc", +3378 => x"000034bc", +3379 => x"000034c4", +3380 => x"000034c4", +3381 => x"000034cc", +3382 => x"000034cc", +3383 => x"000034d4", +3384 => x"000034d4", +3385 => x"000034dc", +3386 => x"000034dc", +3387 => x"000034e4", +3388 => x"000034e4", +3389 => x"000034ec", +3390 => x"000034ec", +3391 => x"000034f4", +3392 => x"000034f4", +3393 => x"000034fc", +3394 => x"000034fc", +3395 => x"00003504", +3396 => x"00003504", +3397 => x"0000350c", +3398 => x"0000350c", +3399 => x"00003514", +3400 => x"00003514", +3401 => x"0000351c", +3402 => x"0000351c", +3403 => x"00003524", +3404 => x"00003524", +3405 => x"0000352c", +3406 => x"0000352c", +3407 => x"00003534", +3408 => x"00003534", +3409 => x"0000353c", +3410 => x"0000353c", +3411 => x"00003544", +3412 => x"00003544", +3413 => x"0000354c", +3414 => x"0000354c", +3415 => x"00003554", +3416 => x"00003554", +3417 => x"0000355c", +3418 => x"0000355c", +3419 => x"00003564", +3420 => x"00003564", +3421 => x"0000356c", +3422 => x"0000356c", +3423 => x"00003580", +3424 => x"00000000", +3425 => x"000037e8", +3426 => x"00003844", +3427 => x"000038a0", +3428 => x"00000000", +3429 => x"00000000", +3430 => x"00000000", +3431 => x"00000000", +3432 => x"00000000", +3433 => x"00000000", +3434 => x"00000000", +3435 => x"00000000", +3436 => x"00000000", +3437 => x"00003100", +3438 => x"00000000", +3439 => x"00000000", +3440 => x"00000000", +3441 => x"00000000", +3442 => x"00000000", +3443 => x"00000000", +3444 => x"00000000", +3445 => x"00000000", +3446 => x"00000000", +3447 => x"00000000", +3448 => x"00000000", +3449 => x"00000000", +3450 => x"00000000", +3451 => x"00000000", +3452 => x"00000000", +3453 => x"00000000", +3454 => x"00000000", +3455 => x"00000000", +3456 => x"00000000", +3457 => x"00000000", +3458 => x"00000000", +3459 => x"00000000", +3460 => x"00000000", +3461 => x"00000000", +3462 => x"00000000", +3463 => x"00000000", +3464 => x"00000000", +3465 => x"00000000", +3466 => x"00000001", +3467 => x"330eabcd", +3468 => x"1234e66d", +3469 => x"deec0005", +3470 => x"000b0000", +3471 => x"00000000", +3472 => x"00000000", +3473 => x"00000000", +3474 => x"00000000", +3475 => x"00000000", +3476 => x"00000000", +3477 => x"00000000", +3478 => x"00000000", +3479 => x"00000000", +3480 => x"00000000", +3481 => x"00000000", +3482 => x"00000000", +3483 => x"00000000", +3484 => x"00000000", +3485 => x"00000000", +3486 => x"00000000", +3487 => x"00000000", +3488 => x"00000000", +3489 => x"00000000", +3490 => x"00000000", +3491 => x"00000000", +3492 => x"00000000", +3493 => x"00000000", +3494 => x"00000000", +3495 => x"00000000", +3496 => x"00000000", +3497 => x"00000000", +3498 => x"00000000", +3499 => x"00000000", +3500 => x"00000000", +3501 => x"00000000", +3502 => x"00000000", +3503 => x"00000000", +3504 => x"00000000", +3505 => x"00000000", +3506 => x"00000000", +3507 => x"00000000", +3508 => x"00000000", +3509 => x"00000000", +3510 => x"00000000", +3511 => x"00000000", +3512 => x"00000000", +3513 => x"00000000", +3514 => x"00000000", +3515 => x"00000000", +3516 => x"00000000", +3517 => x"00000000", +3518 => x"00000000", +3519 => x"00000000", +3520 => x"00000000", +3521 => x"00000000", +3522 => x"00000000", +3523 => x"00000000", +3524 => x"00000000", +3525 => x"00000000", +3526 => x"00000000", +3527 => x"00000000", +3528 => x"00000000", +3529 => x"00000000", +3530 => x"00000000", +3531 => x"00000000", +3532 => x"00000000", +3533 => x"00000000", +3534 => x"00000000", +3535 => x"00000000", +3536 => x"00000000", +3537 => x"00000000", +3538 => x"00000000", +3539 => x"00000000", +3540 => x"00000000", +3541 => x"00000000", +3542 => x"00000000", +3543 => x"00000000", +3544 => x"00000000", +3545 => x"00000000", +3546 => x"00000000", +3547 => x"00000000", +3548 => x"00000000", +3549 => x"00000000", +3550 => x"00000000", +3551 => x"00000000", +3552 => x"00000000", +3553 => x"00000000", +3554 => x"00000000", +3555 => x"00000000", +3556 => x"00000000", +3557 => x"00000000", +3558 => x"00000000", +3559 => x"00000000", +3560 => x"00000000", +3561 => x"00000000", +3562 => x"00000000", +3563 => x"00000000", +3564 => x"00000000", +3565 => x"00000000", +3566 => x"00000000", +3567 => x"00000000", +3568 => x"00000000", +3569 => x"00000000", +3570 => x"00000000", +3571 => x"00000000", +3572 => x"00000000", +3573 => x"00000000", +3574 => x"00000000", +3575 => x"00000000", +3576 => x"00000000", +3577 => x"00000000", +3578 => x"00000000", +3579 => x"00000000", +3580 => x"00000000", +3581 => x"00000000", +3582 => x"00000000", +3583 => x"00000000", +3584 => x"00000000", +3585 => x"00000000", +3586 => x"00000000", +3587 => x"00000000", +3588 => x"00000000", +3589 => x"00000000", +3590 => x"00000000", +3591 => x"00000000", +3592 => x"00000000", +3593 => x"00000000", +3594 => x"00000000", +3595 => x"00000000", +3596 => x"00000000", +3597 => x"00000000", +3598 => x"00000000", +3599 => x"00000000", +3600 => x"00000000", +3601 => x"00000000", +3602 => x"00000000", +3603 => x"00000000", +3604 => x"00000000", +3605 => x"00000000", +3606 => x"00000000", +3607 => x"00000000", +3608 => x"00000000", +3609 => x"00000000", +3610 => x"00000000", +3611 => x"00000000", +3612 => x"00000000", +3613 => x"00000000", +3614 => x"00000000", +3615 => x"00000000", +3616 => x"00000000", +3617 => x"00000000", +3618 => x"00000000", +3619 => x"00000000", +3620 => x"00000000", +3621 => x"00000000", +3622 => x"00000000", +3623 => x"00000000", +3624 => x"00000000", +3625 => x"00000000", +3626 => x"00000000", +3627 => x"00000000", +3628 => x"00000000", +3629 => x"00000000", +3630 => x"00000000", +3631 => x"00000000", +3632 => x"00000000", +3633 => x"00000000", +3634 => x"00000000", +3635 => x"00000000", +3636 => x"00000000", +3637 => x"00000000", +3638 => x"00000000", +3639 => x"00000000", +3640 => x"00000000", +3641 => x"00000000", +3642 => x"00000000", +3643 => x"00000000", +3644 => x"00000000", +3645 => x"00000000", +3646 => x"00000000", +3647 => x"00003104", +3648 => x"ffffffff", +3649 => x"00000000", +3650 => x"ffffffff", +3651 => x"00000000", + others => x"00000000" +); + +begin + +mem_busy<=mem_readEnable; -- we're done on the cycle after we serve the read request + +process (clk, areset) +begin + if areset = '1' then + elsif (clk'event and clk = '1') then + if (mem_writeEnable = '1') then + ram(conv_integer(mem_addr(maxAddrBit downto minAddrBit))) := mem_write; + end if; + mem_read <= ram(conv_integer(mem_addr(maxAddrBit downto minAddrBit))); + end if; +end process; + + + + +end dram_arch; diff --git a/zpu/hdl/zpu4/src/dram_hello.vhd b/zpu/hdl/zpu4/src/dram_hello.vhd new file mode 100644 index 0000000..dc46dbb --- /dev/null +++ b/zpu/hdl/zpu4/src/dram_hello.vhd @@ -0,0 +1,3214 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity dram is +port (clk : in std_logic; + mem_writeEnable : in std_logic; + mem_readEnable : in std_logic; + mem_addr : in std_logic_vector(maxAddrBit downto 0); + mem_write : in std_logic_vector(wordSize-1 downto 0); + mem_read : out std_logic_vector(wordSize-1 downto 0); + mem_busy : out std_logic; + mem_writeMask : in std_logic_vector(wordBytes-1 downto 0)); +end dram; + +architecture dram_arch of dram is + + +type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); + +shared variable ram : ram_type := +( +0 => x"0b0b0b0b", +1 => x"80700b0b", +2 => x"80d3900c", +3 => x"3a0b0b80", +4 => x"c8b20400", +5 => x"00000000", +6 => x"00000000", +7 => x"00000000", +8 => x"80088408", +9 => x"88080b0b", +10 => x"80c8fb2d", +11 => x"880c840c", +12 => x"800c0400", +13 => x"00000000", +14 => x"00000000", +15 => x"00000000", +16 => x"71fd0608", +17 => x"72830609", +18 => x"81058205", +19 => x"832b2a83", +20 => x"ffff0652", +21 => x"04000000", +22 => x"00000000", +23 => x"00000000", +24 => x"71fd0608", +25 => x"83ffff73", +26 => x"83060981", +27 => x"05820583", +28 => x"2b2b0906", +29 => x"7383ffff", +30 => x"0b0b0b0b", +31 => x"83a70400", +32 => x"72098105", +33 => x"72057373", +34 => x"09060906", +35 => x"73097306", +36 => x"070a8106", +37 => x"53510400", +38 => x"00000000", +39 => x"00000000", +40 => x"72722473", +41 => x"732e0753", +42 => x"51040000", +43 => x"00000000", +44 => x"00000000", +45 => x"00000000", +46 => x"00000000", +47 => x"00000000", +48 => x"71737109", +49 => x"71068106", +50 => x"30720a10", +51 => x"0a720a10", +52 => x"0a31050a", +53 => x"81065151", +54 => x"53510400", +55 => x"00000000", +56 => x"72722673", +57 => x"732e0753", +58 => x"51040000", +59 => x"00000000", +60 => x"00000000", +61 => x"00000000", +62 => x"00000000", +63 => x"00000000", +64 => x"00000000", +65 => x"00000000", +66 => x"00000000", +67 => x"00000000", +68 => x"00000000", +69 => x"00000000", +70 => x"00000000", +71 => x"00000000", +72 => x"0b0b0b88", +73 => x"c4040000", +74 => x"00000000", +75 => x"00000000", +76 => x"00000000", +77 => x"00000000", +78 => x"00000000", +79 => x"00000000", +80 => x"720a722b", +81 => x"0a535104", +82 => x"00000000", +83 => x"00000000", +84 => x"00000000", +85 => x"00000000", +86 => x"00000000", +87 => x"00000000", +88 => x"72729f06", +89 => x"0981050b", +90 => x"0b0b88a7", +91 => x"05040000", +92 => x"00000000", +93 => x"00000000", +94 => x"00000000", +95 => x"00000000", +96 => x"72722aff", +97 => x"739f062a", +98 => x"0974090a", +99 => x"8106ff05", +100 => x"06075351", +101 => x"04000000", +102 => x"00000000", +103 => x"00000000", +104 => x"71715351", +105 => x"020d0406", +106 => x"73830609", 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x"00000000", +2855 => x"00000000", +2856 => x"00000000", +2857 => x"00000000", +2858 => x"00000000", +2859 => x"00000000", +2860 => x"00000000", +2861 => x"00000000", +2862 => x"00000000", +2863 => x"00000000", +2864 => x"00000000", +2865 => x"00000000", +2866 => x"00000000", +2867 => x"00000000", +2868 => x"00000000", +2869 => x"00000000", +2870 => x"00000000", +2871 => x"00000000", +2872 => x"00000000", +2873 => x"00000000", +2874 => x"00000000", +2875 => x"00000000", +2876 => x"00000000", +2877 => x"00000000", +2878 => x"00000000", +2879 => x"00000000", +2880 => x"00000000", +2881 => x"00000000", +2882 => x"00000000", +2883 => x"00000000", +2884 => x"00000000", +2885 => x"00000000", +2886 => x"00000000", +2887 => x"00000000", +2888 => x"00000000", +2889 => x"00000000", +2890 => x"00000000", +2891 => x"00000000", +2892 => x"00000000", +2893 => x"00000000", +2894 => x"00000000", +2895 => x"00000000", +2896 => x"00000000", +2897 => x"00000000", +2898 => x"00000000", +2899 => x"ffffffff", +2900 => x"00000000", +2901 => x"00020000", +2902 => x"00000000", +2903 => x"00000000", +2904 => x"00002d58", +2905 => x"00002d58", +2906 => x"00002d60", +2907 => x"00002d60", +2908 => x"00002d68", +2909 => x"00002d68", +2910 => x"00002d70", +2911 => x"00002d70", +2912 => x"00002d78", +2913 => x"00002d78", +2914 => x"00002d80", +2915 => x"00002d80", +2916 => x"00002d88", +2917 => x"00002d88", +2918 => x"00002d90", +2919 => x"00002d90", +2920 => x"00002d98", +2921 => x"00002d98", +2922 => x"00002da0", +2923 => x"00002da0", +2924 => x"00002da8", +2925 => x"00002da8", +2926 => x"00002db0", +2927 => x"00002db0", +2928 => x"00002db8", +2929 => x"00002db8", +2930 => x"00002dc0", +2931 => x"00002dc0", +2932 => x"00002dc8", +2933 => x"00002dc8", +2934 => x"00002dd0", +2935 => x"00002dd0", +2936 => x"00002dd8", +2937 => x"00002dd8", +2938 => x"00002de0", +2939 => x"00002de0", +2940 => x"00002de8", +2941 => x"00002de8", +2942 => x"00002df0", +2943 => x"00002df0", +2944 => x"00002df8", +2945 => x"00002df8", +2946 => x"00002e00", +2947 => x"00002e00", +2948 => x"00002e08", +2949 => x"00002e08", +2950 => x"00002e10", +2951 => x"00002e10", +2952 => x"00002e18", +2953 => x"00002e18", +2954 => x"00002e20", +2955 => x"00002e20", +2956 => x"00002e28", +2957 => x"00002e28", +2958 => x"00002e30", +2959 => x"00002e30", +2960 => x"00002e38", +2961 => x"00002e38", +2962 => x"00002e40", +2963 => x"00002e40", +2964 => x"00002e48", +2965 => x"00002e48", +2966 => x"00002e50", +2967 => x"00002e50", +2968 => x"00002e58", +2969 => x"00002e58", +2970 => x"00002e60", +2971 => x"00002e60", +2972 => x"00002e68", +2973 => x"00002e68", +2974 => x"00002e70", +2975 => x"00002e70", +2976 => x"00002e78", +2977 => x"00002e78", +2978 => x"00002e80", +2979 => x"00002e80", +2980 => x"00002e88", +2981 => x"00002e88", +2982 => x"00002e90", +2983 => x"00002e90", +2984 => x"00002e98", +2985 => x"00002e98", +2986 => x"00002ea0", +2987 => x"00002ea0", +2988 => x"00002ea8", +2989 => x"00002ea8", +2990 => x"00002eb0", +2991 => x"00002eb0", +2992 => x"00002eb8", +2993 => x"00002eb8", +2994 => x"00002ec0", +2995 => x"00002ec0", +2996 => x"00002ec8", +2997 => x"00002ec8", +2998 => x"00002ed0", +2999 => x"00002ed0", +3000 => x"00002ed8", +3001 => x"00002ed8", +3002 => x"00002ee0", +3003 => x"00002ee0", +3004 => x"00002ee8", +3005 => x"00002ee8", +3006 => x"00002ef0", +3007 => x"00002ef0", +3008 => x"00002ef8", +3009 => x"00002ef8", +3010 => x"00002f00", +3011 => x"00002f00", +3012 => x"00002f08", +3013 => x"00002f08", +3014 => x"00002f10", +3015 => x"00002f10", +3016 => x"00002f18", +3017 => x"00002f18", +3018 => x"00002f20", +3019 => x"00002f20", +3020 => x"00002f28", +3021 => x"00002f28", +3022 => x"00002f30", +3023 => x"00002f30", +3024 => x"00002f38", +3025 => x"00002f38", +3026 => x"00002f40", +3027 => x"00002f40", +3028 => x"00002f48", +3029 => x"00002f48", +3030 => x"00002f50", +3031 => x"00002f50", +3032 => x"00002f58", +3033 => x"00002f58", +3034 => x"00002f60", +3035 => x"00002f60", +3036 => x"00002f68", +3037 => x"00002f68", +3038 => x"00002f70", +3039 => x"00002f70", +3040 => x"00002f78", +3041 => x"00002f78", +3042 => x"00002f80", +3043 => x"00002f80", +3044 => x"00002f88", +3045 => x"00002f88", +3046 => x"00002f90", +3047 => x"00002f90", +3048 => x"00002f98", +3049 => x"00002f98", +3050 => x"00002fa0", +3051 => x"00002fa0", +3052 => x"00002fa8", +3053 => x"00002fa8", +3054 => x"00002fb0", +3055 => x"00002fb0", +3056 => x"00002fb8", +3057 => x"00002fb8", +3058 => x"00002fc0", +3059 => x"00002fc0", +3060 => x"00002fc8", +3061 => x"00002fc8", +3062 => x"00002fd0", +3063 => x"00002fd0", +3064 => x"00002fd8", +3065 => x"00002fd8", +3066 => x"00002fe0", +3067 => x"00002fe0", +3068 => x"00002fe8", +3069 => x"00002fe8", +3070 => x"00002ff0", +3071 => x"00002ff0", +3072 => x"00002ff8", +3073 => x"00002ff8", +3074 => x"00003000", +3075 => x"00003000", +3076 => x"00003008", +3077 => x"00003008", +3078 => x"00003010", +3079 => x"00003010", +3080 => x"00003018", +3081 => x"00003018", +3082 => x"00003020", +3083 => x"00003020", +3084 => x"00003028", +3085 => x"00003028", +3086 => x"00003030", +3087 => x"00003030", +3088 => x"00003038", +3089 => x"00003038", +3090 => x"00003040", +3091 => x"00003040", +3092 => x"00003048", +3093 => x"00003048", +3094 => x"00003050", +3095 => x"00003050", +3096 => x"00003058", +3097 => x"00003058", +3098 => x"00003060", +3099 => x"00003060", +3100 => x"00003068", +3101 => x"00003068", +3102 => x"00003070", +3103 => x"00003070", +3104 => x"00003078", +3105 => x"00003078", +3106 => x"00003080", +3107 => x"00003080", +3108 => x"00003088", +3109 => x"00003088", +3110 => x"00003090", +3111 => x"00003090", +3112 => x"00003098", +3113 => x"00003098", +3114 => x"000030a0", +3115 => x"000030a0", +3116 => x"000030a8", +3117 => x"000030a8", +3118 => x"000030b0", +3119 => x"000030b0", +3120 => x"000030b8", +3121 => x"000030b8", +3122 => x"000030c0", +3123 => x"000030c0", +3124 => x"000030c8", +3125 => x"000030c8", +3126 => x"000030d0", +3127 => x"000030d0", +3128 => x"000030d8", +3129 => x"000030d8", +3130 => x"000030e0", +3131 => x"000030e0", +3132 => x"000030e8", +3133 => x"000030e8", +3134 => x"000030f0", +3135 => x"000030f0", +3136 => x"000030f8", +3137 => x"000030f8", +3138 => x"00003100", +3139 => x"00003100", +3140 => x"00003108", +3141 => x"00003108", +3142 => x"00003110", +3143 => x"00003110", +3144 => x"00003118", +3145 => x"00003118", +3146 => x"00003120", +3147 => x"00003120", +3148 => x"00003128", +3149 => x"00003128", +3150 => x"00003130", +3151 => x"00003130", +3152 => x"00003138", +3153 => x"00003138", +3154 => x"00003140", +3155 => x"00003140", +3156 => x"00003148", +3157 => x"00003148", +3158 => x"00003150", +3159 => x"00003150", +3160 => x"00002970", +3161 => x"ffffffff", +3162 => x"00000000", +3163 => x"ffffffff", +3164 => x"00000000", + others => x"00000000" +); + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + mem_busy<=mem_writeEnable or mem_readEnable; + if (mem_writeEnable = '1') then + ram(conv_integer(mem_addr(maxAddrBit downto minAddrBit))) := mem_write; + end if; + if (mem_readEnable = '1') then + mem_read <= ram(conv_integer(mem_addr(maxAddrBit downto minAddrBit))); + end if; + end if; +end process; + + + + +end dram_arch; diff --git a/zpu/hdl/zpu4/src/fastdmips.do b/zpu/hdl/zpu4/src/fastdmips.do new file mode 100644 index 0000000..504bf60 --- /dev/null +++ b/zpu/hdl/zpu4/src/fastdmips.do @@ -0,0 +1,19 @@ +set BreakOnAssertion 1 +vlib work + +vcom -93 -explicit zpu_config_fastsim.vhd +vcom -93 -explicit zpupkg.vhd +vcom -93 -explicit txt_util.vhd +vcom -93 -explicit sim_fpga_top.vhd +vcom -93 -explicit zpu_core.vhd +vcom -93 -explicit dram_dmips.vhd +vcom -93 -explicit timer.vhd +vcom -93 -explicit io.vhd +vcom -93 -explicit trace.vhd + + +vsim fpga_top +view wave + +# run ZPU +run 60000 ms diff --git a/zpu/hdl/zpu4/src/fastdmipsintstack.do b/zpu/hdl/zpu4/src/fastdmipsintstack.do new file mode 100644 index 0000000..ee9571e --- /dev/null +++ b/zpu/hdl/zpu4/src/fastdmipsintstack.do @@ -0,0 +1,19 @@ +set BreakOnAssertion 1 +vlib work + +vcom -93 -explicit zpu_config_fastsim.vhd +vcom -93 -explicit zpupkg.vhd +vcom -93 -explicit txt_util.vhd +vcom -93 -explicit sim_fpga_top.vhd +vcom -93 -explicit zpu_core_intstack.vhd +vcom -93 -explicit dram_dmips.vhd +vcom -93 -explicit timer.vhd +vcom -93 -explicit io.vhd +vcom -93 -explicit trace.vhd + + +vsim fpga_top +view wave + +# run ZPU +run 60000 ms diff --git a/zpu/hdl/zpu4/src/fastdmipssmall.do b/zpu/hdl/zpu4/src/fastdmipssmall.do new file mode 100644 index 0000000..3eaa083 --- /dev/null +++ b/zpu/hdl/zpu4/src/fastdmipssmall.do @@ -0,0 +1,21 @@ +set BreakOnAssertion 1 +vlib work + + +vcom -93 -explicit zpu_config_trace.vhd +vcom -93 -explicit zpupkg.vhd +vcom -93 -explicit txt_util.vhd +vcom -93 -explicit sim_fpga_top.vhd +vcom -93 -explicit zpu_core_small.vhd +vcom -93 -explicit bram_dmips.vhd +vcom -93 -explicit dram_dmips.vhd +vcom -93 -explicit timer.vhd +vcom -93 -explicit io.vhd +vcom -93 -explicit trace.vhd + + +vsim fpga_top +view wave + +# run ZPU +run 60000 ms diff --git a/zpu/hdl/zpu4/src/fastsimzpu.do b/zpu/hdl/zpu4/src/fastsimzpu.do new file mode 100644 index 0000000..504bf60 --- /dev/null +++ b/zpu/hdl/zpu4/src/fastsimzpu.do @@ -0,0 +1,19 @@ +set BreakOnAssertion 1 +vlib work + +vcom -93 -explicit zpu_config_fastsim.vhd +vcom -93 -explicit zpupkg.vhd +vcom -93 -explicit txt_util.vhd +vcom -93 -explicit sim_fpga_top.vhd +vcom -93 -explicit zpu_core.vhd +vcom -93 -explicit dram_dmips.vhd +vcom -93 -explicit timer.vhd +vcom -93 -explicit io.vhd +vcom -93 -explicit trace.vhd + + +vsim fpga_top +view wave + +# run ZPU +run 60000 ms diff --git a/zpu/hdl/zpu4/src/ic300.bitgen b/zpu/hdl/zpu4/src/ic300.bitgen new file mode 100644 index 0000000..1095099 --- /dev/null +++ b/zpu/hdl/zpu4/src/ic300.bitgen @@ -0,0 +1,27 @@ +-g DebugBitstream:No +-g Binary:yes +-g CRC:Enable +-g ConfigRate:50 +-g CclkPin:Pullnone +-g M0Pin:Pullnone +-g M1Pin:Pullnone +-g M2Pin:Pullnone +-g ProgPin:PullUp +-g DonePin:Pullnone +-g TckPin:Pullnone +-g TdiPin:Pullnone +-g TdoPin:Pullnone +-g TmsPin:Pullnone +-g UnusedPin:Pullnone +-g UserID:0xFFFFFFFF +-g DCMShutDown:Disable +-g DCIUpdateMode:AsRequired +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:Level1 +-g DonePipe:No +-g DriveDone:Yes + diff --git a/zpu/hdl/zpu4/src/ic300.lso b/zpu/hdl/zpu4/src/ic300.lso new file mode 100644 index 0000000..22de730 --- /dev/null +++ b/zpu/hdl/zpu4/src/ic300.lso @@ -0,0 +1 @@ +work diff --git a/zpu/hdl/zpu4/src/ic300.ucf b/zpu/hdl/zpu4/src/ic300.ucf new file mode 100644 index 0000000..4a141b9 --- /dev/null +++ b/zpu/hdl/zpu4/src/ic300.ucf @@ -0,0 +1,146 @@ +# clock inputs +net "cpu_clk_p" loc = "R9" | iostandard=LVTTL; + +# input pins +net "cpu_a_p(0)" loc = "N15" | iostandard=LVTTL; +net "cpu_a_p(1)" loc = "P16" | iostandard=LVTTL; +net "cpu_a_p(2)" loc = "P13" | iostandard=LVTTL; +net "cpu_a_p(3)" loc = "N16" | iostandard=LVTTL; +net "cpu_a_p(4)" loc = "P15" | iostandard=LVTTL; +net "cpu_a_p(5)" loc = "R11" | iostandard=LVTTL; +net "cpu_a_p(6)" loc = "T14" | iostandard=LVTTL; +net "cpu_a_p(7)" loc = "R16" | iostandard=LVTTL; +net "cpu_a_p(8)" loc = "P14" | iostandard=LVTTL; +net "cpu_a_p(9)" loc = "T13" | iostandard=LVTTL; +net "cpu_a_p(10)" loc = "R13" | iostandard=LVTTL; +net "cpu_a_p(11)" loc = "P7" | iostandard=LVTTL; +net "cpu_a_p(12)" loc = "N12" | iostandard=LVTTL; +net "cpu_a_p(13)" loc = "R12" | iostandard=LVTTL; +net "cpu_a_p(14)" loc = "L13" | iostandard=LVTTL; +net "cpu_a_p(15)" loc = "K12" | iostandard=LVTTL; +net "cpu_a_p(16)" loc = "K15" | iostandard=LVTTL; +net "cpu_a_p(17)" loc = "T10" | iostandard=LVTTL; +net "cpu_a_p(18)" loc = "T9" | iostandard=LVTTL; +net "cpu_a_p(19)" loc = "N10" | iostandard=LVTTL; +net "cpu_a_p(20)" loc = "T8" | iostandard=LVTTL; +net "cpu_wr_n_p(0)" loc = "L15" | iostandard=LVTTL; +net "cpu_wr_n_p(1)" loc = "N14" | iostandard=LVTTL; +net "cpu_oe_n_p" loc = "T12" | iostandard=LVTTL; +net "cpu_cs_n_p(1)" loc = "R3" | iostandard=LVTTL; +net "cpu_cs_n_p(2)" loc = "M16" | iostandard=LVTTL; +net "cpu_cs_n_p(3)" loc = "P11" | iostandard=LVTTL; + +#net "sdr_clk_fb_p" loc = "B8" | iostandard=SSTL2_I; + +# output pins +net "cpu_fiq_p" loc = "K16" | iostandard=LVTTL; +net "cpu_irq_p(0)" loc = "M14" | iostandard=LVTTL; +net "cpu_irq_p(1)" loc = "J16" | iostandard=LVTTL; +net "cpu_wait_n_p" loc = "M15" | iostandard=LVTTL; + +#net "sdr_clk_p" loc = "D8" | iostandard=SSTL2_I | FAST; +#net "sdr_clk_n_p" loc = "F5" | iostandard=SSTL2_I | FAST; +#net "cke_q_p" loc = "F4" | iostandard=SSTL2_I | FAST; +#net "cs_qn_p" loc = "M2" | iostandard=SSTL2_I | FAST | PULLUP; +#net "ras_qn_p" loc = "J2" | iostandard=SSTL2_I | FAST | PULLUP | NODELAY; +#net "cas_qn_p" loc = "M3" | iostandard=SSTL2_I | FAST | PULLUP | NODELAY; +#net "we_qn_p" loc = "K4" | iostandard=SSTL2_I | FAST | PULLUP | NODELAY; +#net "dm_q_p(0)" loc = "L4" | iostandard=SSTL2_I | FAST; +#net "dm_q_p(1)" loc = "E4" | iostandard=SSTL2_I | FAST; +#net "dqs_q_p(0)" loc = "L3" | iostandard=SSTL2_I | FAST; +#net "dqs_q_p(1)" loc = "D3" | iostandard=SSTL2_I | FAST; +#net "ba_q_p(0)" loc = "M1" | iostandard=SSTL2_I | FAST; +#net "ba_q_p(1)" loc = "J3" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(0)" loc = "J4" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(1)" loc = "N2" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(2)" loc = "H4" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(3)" loc = "P2" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(4)" loc = "E7" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(5)" loc = "G4" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(6)" loc = "D7" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(7)" loc = "G5" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(8)" loc = "C7" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(9)" loc = "F3" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(10)" loc = "N3" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(11)" loc = "E6" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(12)" loc = "D6" | iostandard=SSTL2_I | FAST; + +# bidirectional pins +net "cpu_d_p(0)" loc = "M11" | iostandard=LVTTL; +net "cpu_d_p(1)" loc = "N11" | iostandard=LVTTL; +net "cpu_d_p(2)" loc = "P10" | iostandard=LVTTL; +net "cpu_d_p(3)" loc = "R10" | iostandard=LVTTL; +net "cpu_d_p(4)" loc = "T7" | iostandard=LVTTL; +net "cpu_d_p(5)" loc = "R7" | iostandard=LVTTL; +net "cpu_d_p(6)" loc = "N6" | iostandard=LVTTL; +net "cpu_d_p(7)" loc = "M6" | iostandard=LVTTL; +net "cpu_d_p(8)" loc = "K13" | iostandard=LVTTL; +net "cpu_d_p(9)" loc = "M10" | iostandard=LVTTL; +net "cpu_d_p(10)" loc = "L12" | iostandard=LVTTL; +net "cpu_d_p(11)" loc = "M13" | iostandard=LVTTL; +net "cpu_d_p(12)" loc = "K14" | iostandard=LVTTL; +net "cpu_d_p(13)" loc = "L14" | iostandard=LVTTL; +net "cpu_d_p(14)" loc = "J13" | iostandard=LVTTL; +net "cpu_d_p(15)" loc = "J14" | iostandard=LVTTL; + +#net "sdr_d_p(0)" loc = "G1" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(1)" loc = "H3" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(2)" loc = "G3" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(3)" loc = "K2" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(4)" loc = "F2" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(5)" loc = "L2" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(6)" loc = "E1" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(7)" loc = "M4" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(8)" loc = "C6" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(9)" loc = "E2" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(10)" loc = "C2" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(11)" loc = "D1" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(12)" loc = "B7" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(13)" loc = "D2" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(14)" loc = "B6" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(15)" loc = "B5" | iostandard=SSTL2_I | NODELAY | FAST; + +# TIMING +# Create timing names +NET "cpu_clk_p" TNM_NET = "cpu_clk_p"; +NET "sdr_clk_fb_p" TNM_NET = "sdr_clk_fb_p"; +#NET "cpu_clk" TNM_NET = "cpu_clk"; +#NET "cpu_clk_2x" TNM_NET = "cpu_clk_2x"; +#NET "cpu_clk_4x" TNM_NET = "cpu_clk_4x"; +#NET "ddr_in_clk" TNM_NET = "ddr_in_clk"; +#NET "ddr_in_clk_2x" TNM_NET = "ddr_in_clk_2x"; + +## Create timing + +# Periode timing +TIMESPEC "TS_cpu_clk" = PERIOD "cpu_clk_p" 10 ns HIGH 50 %; +#TIMESPEC "TS_sdr_clk_fb_p" = PERIOD "sdr_clk_fb_p" 7.8 ns HIGH 50 %; + +# Clock domain crossing timing +#TIMESPEC "TS_cpu1_to_cpu2" = FROM "cpu_clk" TO "cpu_clk_2x" 7.8 ns; +#TIMESPEC "TS_cpu1_to_cpu4" = FROM "cpu_clk" TO "cpu_clk_4x" 3.9 ns; +#TIMESPEC "TS_cpu1_to_ddr2" = FROM "cpu_clk" TO "ddr_in_clk" 7.8 ns; +#TIMESPEC "TS_cpu1_to_ddr2_2x" = FROM "cpu_clk" TO "ddr_in_clk_2x" 3.9 ns; + +#TIMESPEC "TS_cpu2_to_cpu1" = FROM "cpu_clk_2x" TO "cpu_clk" 7.8 ns; +#TIMESPEC "TS_cpu2_to_cpu4" = FROM "cpu_clk_2x" TO "cpu_clk_4x" 3.9 ns; +#TIMESPEC "TS_cpu2_to_ddr2" = FROM "cpu_clk_2x" TO "ddr_in_clk" 7.8 ns; +#TIMESPEC "TS_cpu2_to_ddr_2x" = FROM "cpu_clk_2x" TO "ddr_in_clk_2x" 3.9 ns; + +#TIMESPEC "TS_cpu4_to_cpu1" = FROM "cpu_clk_4x" TO "cpu_clk" 3.9 ns; +#TIMESPEC "TS_cpu4_to_cpu2" = FROM "cpu_clk_4x" TO "cpu_clk_2x" 3.9 ns; +#TIMESPEC "TS_cpu4_to_ddr2" = FROM "cpu_clk_4x" TO "ddr_in_clk" 3.9 ns; +#TIMESPEC "TS_cpu4_to_ddr2_2x" = FROM "cpu_clk_4x" TO "ddr_in_clk_2x" 3.9 ns; + +#TIMESPEC "TS_ddr2_to_cpu1" = FROM "ddr_in_clk" TO "cpu_clk" 7.8 ns; +#TIMESPEC "TS_ddr2_to_cpu2" = FROM "ddr_in_clk" TO "cpu_clk_2x" 7.8 ns; +#TIMESPEC "TS_ddr2_to_cpu4" = FROM "ddr_in_clk" TO "cpu_clk_4x" 3.9 ns; +#TIMESPEC "TS_ddr2_to_ddr2_2x" = FROM "ddr_in_clk" TO "ddr_in_clk_2x" 3.9 ns; + +#TIMESPEC "TS_ddr2_2x_to_cpu1" = FROM "ddr_in_clk_2x" TO "cpu_clk" 3.9 ns; +#TIMESPEC "TS_ddr2_2x_to_cpu2" = FROM "ddr_in_clk_2x" TO "cpu_clk_2x" 3.9 ns; +#TIMESPEC "TS_ddr2_2x_to_cpu4" = FROM "ddr_in_clk_2x" TO "cpu_clk_4x" 3.9 ns; +#TIMESPEC "TS_ddr2_2x_to_ddr2" = FROM "ddr_in_clk_2x" TO "ddr_in_clk" 3.9 ns; + + + diff --git a/zpu/hdl/zpu4/src/ic300.vhd b/zpu/hdl/zpu4/src/ic300.vhd new file mode 100644 index 0000000..a1b4f41 --- /dev/null +++ b/zpu/hdl/zpu4/src/ic300.vhd @@ -0,0 +1,144 @@ +-------------------------------------------------------------------------------- +-- Company: Zylin AS +-- Engineer: Tore Ramsland +-- +-- Create Date: 21:47:41 07/03/05 +-- Design Name: ic300 +-- Module Name: ic300 - behave +-- Project Name: eCosBoard +-- Target Device: XC3S400400-FG256 +-- Tool versions: 7.1i +-- Description: Top level +-- +-- Dependencies: +-- +-- Revision: +-- 2005-07-11 Updated to test FPGA +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library UNISIM; +use UNISIM.VComponents.all; + +library zylin; +use zylin.arm7.all; + +library zylin; +use zylin.zpu_config.all; +use zylin.zpupkg.all; + +library work; +use work.phi_config.all; +use work.ic300pkg.all; + +entity ic300 is + generic( + simulate_io_time : boolean := false); + port ( -- Clock inputs + cpu_clk_p : in std_logic; + + -- CPU interface signals + cpu_a_p : in std_logic_vector(20 downto 0); + cpu_wr_n_p : in std_logic_vector(1 downto 0); + cpu_cs_n_p : in std_logic_vector(3 downto 1); + cpu_oe_n_p : in std_logic; + cpu_d_p : inout std_logic_vector(15 downto 0); + cpu_irq_p : out std_logic_vector(1 downto 0); + cpu_fiq_p : out std_logic; + cpu_wait_n_p : out std_logic; + + -- DDR SDRAM Signals + sdr_clk_p : out std_logic; -- ddr_sdram_clock + sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock + cke_q_p : out std_logic; -- clock enable + cs_qn_p : out std_logic; -- /chip select + ras_qn_p : inout std_logic; -- /ras + cas_qn_p : inout std_logic; -- /cas + we_qn_p : inout std_logic; -- /write enable + dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00" + dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write + ba_q_p : out std_logic_vector(1 downto 0); -- bank select + sdr_a_p : out std_logic_vector(12 downto 0); -- address bus + sdr_d_p : inout std_logic_vector(15 downto 0); -- bidir data bus + sdr_clk_fb_p : in std_logic -- DDR clock feedback + ); +end ic300; + +architecture behave of ic300 is + +signal cpu_we : std_logic_vector(1 downto 0); -- Write signal for lower(0) and upper(1) 8 data bits +signal cpu_re : std_logic; -- Read enable signal for all 16 bits +signal areset : std_logic; -- Asyncronous active high reset (for initialization) +signal areset_dummy : std_logic; + +-- Clock module signals +signal clk_status : std_logic_vector(2 downto 0); -- DLL lock status (from 3 DLL's) +signal cpu_clk : std_logic; -- 64 MHz CPU clk +signal cpu_clk_2x : std_logic; -- 128 MHz CPU clk (in phase with 64 MHz) +signal cpu_clk_4x : std_logic; -- 256 MHz CPU clk (in phase with 64 MHz) +signal ddr_in_clk : std_logic; -- 128 MHz clock from DDR SDRAM +signal ddr_in_clk_2x : std_logic; -- 256 MHz clock from DDR SDRAM + -- NOTE! Phase relation to 64 MHz clock unknown + +-- Internal CPU interface signals +signal cpu_din : std_logic_vector(15 downto 0); -- 16-bit data from CPU +signal cpu_dout : std_logic_vector(15 downto 0); -- 16-bit data to CPU +signal cpu_a : std_logic_vector(20 downto 0); -- 21-bit address from CPU + +begin + +-- areset <= '0'; + areset_dummy <= '0'; + + global_init_reset: + rocbuf port map(I=>areset_dummy,O=>areset); + + allclocks: + clocks port map( + areset => areset, + cpu_clk_p => cpu_clk_p, + cpu_clk => cpu_clk, + cpu_clk_2x => cpu_clk_2x, + cpu_clk_4x => cpu_clk_4x, + sdr_clk_fb_p => sdr_clk_fb_p, + ddr_in_clk => ddr_in_clk, + ddr_in_clk_2x => ddr_in_clk_2x, + locked => clk_status); + + arm7cpu: + arm7wb generic map (simulate_io_time => simulate_io_time) + port map( + areset => areset, + cpu_clk => cpu_clk, + cpu_clk_2x => cpu_clk_2x, + cpu_a_p => cpu_a_p, + cpu_wr_n_p => cpu_wr_n_p, + cpu_cs_n_p => cpu_cs_n_p, + cpu_oe_n_p => cpu_oe_n_p, + cpu_d_p => cpu_d_p, + cpu_irq_p => cpu_irq_p, + cpu_fiq_p => cpu_fiq_p, + cpu_wait_n_p => cpu_wait_n_p, + cpu_din => cpu_din, + cpu_a => cpu_a, + cpu_we => cpu_we, + cpu_re => cpu_re, + cpu_dout => cpu_dout); + + + cpu_fpga_regs: + zpuio port map( + areset => areset, + cpu_clk => cpu_clk, + clk_status => clk_status, + cpu_din => cpu_din, + cpu_a => cpu_a, + cpu_we => cpu_we, + cpu_re => cpu_re, + cpu_dout => cpu_dout); + + +end behave; diff --git a/zpu/hdl/zpu4/src/ic300_config.vhd b/zpu/hdl/zpu4/src/ic300_config.vhd new file mode 100644 index 0000000..b14ec79 --- /dev/null +++ b/zpu/hdl/zpu4/src/ic300_config.vhd @@ -0,0 +1,26 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +package phi_config is + + constant Fpga_Global_Base : std_logic_vector(19 downto 17) := "000"; -- 0x0800.... + constant Clock_Stat_Reg_Addr : std_logic_vector(5 downto 2) := "0000"; -- 0x....0000 + constant Ctrl_Reg_Addr : std_logic_vector(5 downto 2) := "0001"; -- 0x....0004 + constant output_enable : std_logic_vector(5 downto 2) := "0010"; -- 0x....0008 + constant output_disable : std_logic_vector(5 downto 2) := "0011"; -- 0x....000C + constant data_status : std_logic_vector(5 downto 2) := "0100"; -- 0x....0010 + constant set_output_data : std_logic_vector(5 downto 2) := "0101"; -- 0x....0014 + constant clear_output_data : std_logic_vector(5 downto 2) := "0110"; -- 0x....0018 + constant data_in_read : std_logic_vector(5 downto 2) := "0111"; -- 0x....001C + constant output_status : std_logic_vector(5 downto 2) := "1000"; -- 0x....0020 + constant cpu_access_address : std_logic_vector(5 downto 2) := "1001"; -- 0x....0024 + + constant Fpga_Ethernet_Reg_Base : std_logic_vector(19 downto 17) := "110"; -- 0x080C0000 + + constant Fpga_DDR_Ctrl_Base : std_logic_vector(19 downto 17) := "111"; -- 0x080E.... + constant DDR_Ctrl_Reg_Addr : std_logic_vector(3 downto 2) := "00"; -- 0x....0000 + constant DDR_Mode_Reg_Addr : std_logic_vector(3 downto 2) := "01"; -- 0x....0004 + constant DDR_Page_Select_Addr : std_logic_vector(3 downto 2) := "10"; -- 0x....0008 + + +end phi_config; diff --git a/zpu/hdl/zpu4/src/ic300pkg.vhd b/zpu/hdl/zpu4/src/ic300pkg.vhd new file mode 100644 index 0000000..13da306 --- /dev/null +++ b/zpu/hdl/zpu4/src/ic300pkg.vhd @@ -0,0 +1,88 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +package ic300pkg is + + component ic300 is + port ( -- Clock inputs + cpu_clk_p : in std_logic; + + -- CPU interface signals + cpu_a_p : in std_logic_vector(20 downto 0); + cpu_wr_n_p : in std_logic_vector(1 downto 0); + cpu_cs_n_p : in std_logic_vector(3 downto 1); + cpu_oe_n_p : in std_logic; + cpu_d_p : inout std_logic_vector(15 downto 0); + cpu_irq_p : out std_logic_vector(1 downto 0); + cpu_fiq_p : out std_logic; + cpu_wait_n_p : out std_logic; + + -- DDR SDRAM Signals + sdr_clk_p : out std_logic; -- ddr_sdram_clock + sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock + cke_q_p : out std_logic; -- clock enable + cs_qn_p : out std_logic; -- /chip select + ras_qn_p : inout std_logic; -- /ras + cas_qn_p : inout std_logic; -- /cas + we_qn_p : inout std_logic; -- /write enable + dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00" + dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write + ba_q_p : out std_logic_vector(1 downto 0); -- bank select + sdr_a_p : out std_logic_vector(12 downto 0); -- address bus + sdr_d_p : inout std_logic_vector(15 downto 0); -- bidir data bus + sdr_clk_fb_p : in std_logic -- DDR clock feedback + ); + end component; + + component clocks is + port ( areset : in std_logic; + cpu_clk_p : in std_logic; + sdr_clk_fb_p : in std_logic; + cpu_clk : out std_logic; + cpu_clk_2x : out std_logic; + cpu_clk_4x : out std_logic; + ddr_in_clk : out std_logic; + ddr_in_clk_2x : out std_logic; + locked : out std_logic_vector(2 downto 0)); + end component; + + component cpu_regs is + port ( areset : in std_logic; + cpu_clk : in std_logic; + clk_status : in std_logic_vector(2 downto 0); + cpu_din : in std_logic_vector(15 downto 0); + cpu_a : in std_logic_vector(20 downto 0); + cpu_we : in std_logic_vector(1 downto 0); + cpu_re : in std_logic; + cpu_dout : inout std_logic_vector(15 downto 0)); + end component; + + component ddr_bridge is + port ( areset : in std_logic; + cpu_clk : in std_logic; + cpu_clk_2x : in std_logic; + cpu_clk_4x : in std_logic; + ddr_in_clk : in std_logic; + ddr_in_clk_2x : in std_logic; + + cpu_we : in std_logic_vector(1 downto 0); + cpu_re : in std_logic; + cpu_din : in std_logic_vector(15 downto 0); + cpu_a : in std_logic_vector(20 downto 0); + cpu_dout : inout std_logic_vector(15 downto 0); + + sdr_clk_p : out std_logic; -- ddr_sdram_clock + sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock + cke_q_p : out std_logic; -- clock enable + cs_qn_p : out std_logic; -- /chip select + ras_qn_p : inout std_logic; -- /ras + cas_qn_p : inout std_logic; -- /cas + we_qn_p : inout std_logic; -- /write enable + dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00" + dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write + ba_q_p : out std_logic_vector(1 downto 0); -- bank select + sdr_a_p : out std_logic_vector(12 downto 0); -- address bus + sdr_d_p : inout std_logic_vector(15 downto 0)); -- bidir data bus + end component; + +end ic300pkg; diff --git a/zpu/hdl/zpu4/src/io.vhd b/zpu/hdl/zpu4/src/io.vhd new file mode 100644 index 0000000..b5465d1 --- /dev/null +++ b/zpu/hdl/zpu4/src/io.vhd @@ -0,0 +1,92 @@ +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +use std.textio.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; +use work.txt_util.all; + +entity zpu_io is + generic ( + log_file: string := "log.txt" + ); + port( + clk : in std_logic; + areset : in std_logic; + busy : out std_logic; + writeEnable : in std_logic; + readEnable : in std_logic; + write : in std_logic_vector(7 downto 0); + read : out std_logic_vector(7 downto 0); + addr : in std_logic_vector(maxAddrBit downto minAddrBit) + ); +end zpu_io; + + +architecture behave of zpu_io is + + + +signal timer_read : std_logic_vector(7 downto 0); +--signal timer_write : std_logic_vector(7 downto 0); +signal timer_we : std_logic; + +signal serving : std_logic; + +file l_file : TEXT open write_mode is log_file; + +begin + + + timerinst: timer port map ( + clk => clk, + areset => areset, + we => timer_we, + din => write, + adr => addr(4 downto 2), + dout => timer_read); + + busy <= writeEnable or readEnable; + timer_we <= writeEnable and addr(12); + + process(areset, clk) + begin + if (areset = '1') then +-- timer_we <= '0'; + elsif (clk'event and clk = '1') then +-- timer_we <= '0'; + if writeEnable = '1' then + -- external interface + if addr=x"1000" then + -- Write to UART + -- report "" & character'image(conv_integer(memBint)) severity note; + print(l_file, character'val(conv_integer(write))); + elsif addr(12)='1' then +-- report "xxx" severity failure; +-- timer_we <= '1'; + else + report "Illegal IO write" severity failure; + end if; + + end if; + read <= (others => 'U'); + if (readEnable = '1') then + if addr=x"1001" then + read <= (0=>'1', others => '0'); -- recieve empty + elsif addr(12)='1' then + read <= timer_read; + elsif addr(11)='1' then + read <= ZPU_Frequency; + else + report "Illegal IO read" severity failure; + end if; + end if; + end if; + end process; + + +end behave; + diff --git a/zpu/hdl/zpu4/src/log.txt b/zpu/hdl/zpu4/src/log.txt new file mode 100644 index 0000000..af58c93 --- /dev/null +++ b/zpu/hdl/zpu4/src/log.txt @@ -0,0 +1,380 @@ +H +e +l +l +o + +w +o +r +l +d + +1 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +2 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +1 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +2 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +1 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +2 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +1 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +2 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +1 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +2 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +1 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +2 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +1 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +2 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +1 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +2 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +1 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +2 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +1 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +2 + + + + + + diff --git a/zpu/hdl/zpu4/src/niltrace.vhd b/zpu/hdl/zpu4/src/niltrace.vhd new file mode 100644 index 0000000..40fc1ca --- /dev/null +++ b/zpu/hdl/zpu4/src/niltrace.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +use std.textio.all; +use work.zpu_config.all; + + +entity trace is + port( + clk : in std_logic; + begin_inst : in std_logic; + pc : in std_logic_vector(maxAddrBit downto 0); + opcode : in std_logic_vector(7 downto 0); + sp : in std_logic_vector(maxAddrBit downto 2); + memA : in std_logic_vector(wordSize-1 downto 0); + busy : in std_logic); +end trace; + + +architecture behave of trace is + +begin + +end behave; + diff --git a/zpu/hdl/zpu4/src/sim_fpga_top.vhd b/zpu/hdl/zpu4/src/sim_fpga_top.vhd new file mode 100644 index 0000000..2905505 --- /dev/null +++ b/zpu/hdl/zpu4/src/sim_fpga_top.vhd @@ -0,0 +1,190 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 20:15:31 04/14/05 +-- Design Name: +-- Module Name: fpga_top - behave +-- Project Name: +-- Target Device: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity fpga_top is +end fpga_top; + +architecture behave of fpga_top is + + +signal clk : std_logic; + +signal areset : std_logic; + + +component zpu_io is + generic ( + log_file: string := "log.txt" + ); + port( + clk : in std_logic; + areset : in std_logic; + busy : out std_logic; + writeEnable : in std_logic; + readEnable : in std_logic; + write : in std_logic_vector(7 downto 0); + read : out std_logic_vector(7 downto 0); + addr : in std_logic_vector(maxAddrBit downto minAddrBit) + ); +end component; + + + + + +signal mem_busy : std_logic; +signal mem_read : std_logic_vector(wordSize-1 downto 0); +signal mem_write : std_logic_vector(wordSize-1 downto 0); +signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); +signal mem_writeEnable : std_logic; +signal mem_readEnable : std_logic; +signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + +signal enable : std_logic; + +signal dram_mem_busy : std_logic; +signal dram_mem_read : std_logic_vector(wordSize-1 downto 0); +signal dram_mem_write : std_logic_vector(wordSize-1 downto 0); +signal dram_mem_writeEnable : std_logic; +signal dram_mem_readEnable : std_logic; +signal dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + + +signal io_busy : std_logic; + +signal io_mem_read : std_logic_vector(7 downto 0); +signal io_mem_writeEnable : std_logic; +signal io_mem_readEnable : std_logic; + + +signal dram_ready : std_logic; +signal io_ready : std_logic; +signal io_reading : std_logic; + + +signal break : std_logic; + +begin + poweronreset: roc port map (O => areset); + + + + zpu: zpu_core port map ( + clk => clk , + areset => areset, + enable => enable, + in_mem_busy => mem_busy, + mem_read => mem_read, + mem_write => mem_write, + out_mem_addr => mem_addr, + out_mem_writeEnable => mem_writeEnable, + out_mem_readEnable => mem_readEnable, + mem_writeMask => mem_writeMask, + interrupt => '0', + break => break); + + dram_imp: dram port map ( + clk => clk , + areset => areset, + mem_busy => dram_mem_busy, + mem_read => dram_mem_read, + mem_write => mem_write, + mem_addr => mem_addr(maxAddrBit downto 0), + mem_writeEnable => dram_mem_writeEnable, + mem_readEnable => dram_mem_readEnable, + mem_writeMask => mem_writeMask); + + + ioMap: zpu_io port map ( + clk => clk, + areset => areset, + busy => io_busy, + writeEnable => io_mem_writeEnable, + readEnable => io_mem_readEnable, + write => mem_write(7 downto 0), + read => io_mem_read, + addr => mem_addr(maxAddrBit downto minAddrBit) + ); + + dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit); + dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit); + io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit); + io_mem_readEnable <= mem_readEnable and mem_addr(ioBit); + mem_busy <= io_busy or dram_mem_busy or io_busy; + + + + -- Memory reads either come from IO or DRAM. We need to pick the right one. + memorycontrol: + process(dram_mem_read, dram_ready, io_ready, io_mem_read) + begin + mem_read <= (others => 'U'); + if dram_ready='1' then + mem_read <= dram_mem_read; + end if; + + if io_ready='1' then + mem_read <= (others => '0'); + mem_read(7 downto 0) <= io_mem_read; + end if; + end process; + + + io_ready <= (io_reading or io_mem_readEnable) and not io_busy; + + memoryControlSync: + process(clk, areset) + begin + if areset = '1' then + enable <= '0'; + io_reading <= '0'; + dram_ready <= '0'; + elsif (clk'event and clk = '1') then + enable <= '1'; + io_reading <= io_busy or io_mem_readEnable; + dram_ready<=dram_mem_readEnable; + + end if; + end process; + + -- wiggle the clock @ 100MHz + clock : PROCESS + begin + clk <= '0'; + wait for 5 ns; + clk <= '1'; + wait for 5 ns; + end PROCESS clock; + + +end behave; diff --git a/zpu/hdl/zpu4/src/simzpu.do b/zpu/hdl/zpu4/src/simzpu.do new file mode 100644 index 0000000..e6e3068 --- /dev/null +++ b/zpu/hdl/zpu4/src/simzpu.do @@ -0,0 +1,23 @@ +set BreakOnAssertion 1 +vlib work + +vcom -93 -explicit zpu_config.vhd +vcom -93 -explicit zpupkg.vhd +vcom -93 -explicit txt_util.vhd +vcom -93 -explicit sim_fpga_top.vhd +vcom -93 -explicit zpu_core.vhd +vcom -93 -explicit dram.vhd +vcom -93 -explicit timer.vhd +vcom -93 -explicit io.vhd +vcom -93 -explicit trace.vhd + +# run ZPU +vsim fpga_top +view wave +add wave -recursive fpga_top/zpu/* +#add wave -recursive fpga_top/* +view structure +#view signals + +# Enough to run tiny programs +run 1000 ms diff --git a/zpu/hdl/zpu4/src/simzpu_intstack.do b/zpu/hdl/zpu4/src/simzpu_intstack.do new file mode 100644 index 0000000..cec4873 --- /dev/null +++ b/zpu/hdl/zpu4/src/simzpu_intstack.do @@ -0,0 +1,23 @@ +set BreakOnAssertion 1 +vlib work + +vcom -93 -explicit zpu_config_trace.vhd +vcom -93 -explicit zpupkg.vhd +vcom -93 -explicit txt_util.vhd +vcom -93 -explicit sim_fpga_top.vhd +vcom -93 -explicit zpu_core_intstack.vhd +vcom -93 -explicit dram_hello.vhd +vcom -93 -explicit timer.vhd +vcom -93 -explicit io.vhd +vcom -93 -explicit trace.vhd + +# run ZPU +vsim fpga_top +view wave +add wave -recursive fpga_top/zpu/* +#add wave -recursive fpga_top/* +view structure +#view signals + +# Enough to run tiny programs +run 15 ms diff --git a/zpu/hdl/zpu4/src/status.txt b/zpu/hdl/zpu4/src/status.txt new file mode 100644 index 0000000..df01caf --- /dev/null +++ b/zpu/hdl/zpu4/src/status.txt @@ -0,0 +1,109 @@ +- Before NEQBRANCH opt 4.684 DMIPS 8.0 cycles average, after +- opcode pairs + +0x6060 0.1519223038446077 75961 9.048362120309708 LOADSP + LOADSP +0x4040 0.13967027934055867 69835 11.08668042546436 STORESP + STORESP +0x8038 0.10230620461240922 51153 10.251102204408818 IM + NEQBRANCH +0x4060 0.09856219712439425 49281 9.822802471596571 STORESP + LOADSP +0x6080 0.09734219468438937 48671 6.483415478886373 LOADSP + IM +0x3860 0.08642217284434568 43211 12.616350364963504 NEQBRANCH + LOADSP +0x8080 0.060966121932243864 30483 4.275915275634731 IM + IM +0x8005 0.05317010634021268 26585 6.572311495673671 IM + ADD +0x540 0.05215210430420861 26076 9.339541547277937 ADD + STORESP +0x3d0d 0.050808101616203236 25404 12.398243045387995 +0xd04 0.0466000932001864 23300 20.0 +0x6040 0.04389608779217558 21948 9.460344827586207 +0x4080 0.043648087296174594 21824 7.630769230769231 +0xc80 0.03966807933615867 19834 11.438292964244521 +0x8010 0.0391500783001566 19575 6.1248435544430535 +0x480 0.038798077596155195 19399 10.941342357586013 + + +- zpu_core.vhd: 1500 LUTs. Xilinx ISE reports 83MHz maximum frequency after P&R + which matches what I've found w/my ic300.vhd testbench + +- zpu_core_instack.vhd + - problems w/simulation trace since storeb/loadb will run into undefined memory + during emulation. Solution: implement loadb+storeb. + - simulation needs to read cycles from ModelSim trace so as to m ake readcycles + not cause false positives. This has other interesting potentials w.r.t. + knowing which instructions take the longest. + +- Ca. 1700 LUT inc. all instructions. Removing all higher level instructions + => 1300. + +- Review memory interface + - When is mem_busy high? Will it be high on the next cycle after + I've send mem_read/writeEnable? + - Should I hold off posting a read/write until mem_busy = '0'? + - Write posting could increase performance somewhat. Should there be + a seperate write busy signal? + - Synchronous reset? The ARM7 will have to copy the program to DRAM and + then start the ZPU. + +- Current instruction set has + - 31 DMIPS single cycle performance Simulator.java + - 8 DMIPS w/single cycle RAM access in ModelSim + +112 0.06100380865858346 67215918 +56 0.04139603650830458 45611457 +129 0.0375812381475752 41408192 +5 0.03703417264799563 40805418 +113 0.03540341331682748 39008596 +128 0.0343154384313754 37809831 +83 0.03322159422742951 36604599 +114 0.03213492807203279 35407276 +132 0.03158580962697109 34802240 +12 0.03049709687915076 33602662 +8 0.029409690138646426 32404523 +115 0.026690690908727877 29408644 +46 0.025054316381406774 27605635 +82 0.023965804208719754 26406278 +84 0.023961360698074072 26401382 +116 0.023417718589457643 25802380 +81 0.02179306727026773 24012288 +117 0.021783900714401432 24002188 +4 0.01797685126990833 19807461 +6 0.016340292503890113 18004249 +85 0.016339001017850734 18002826 +255 0.016338918428089957 18002735 +86 0.016337281154151066 18000931 +11 0.011984767180825744 13205194 +51 0.0114390303780569 12603884 +38 0.010892246228211845 12001420 +118 0.010347263624247446 11400941 +131 0.009257503529350904 10200209 +7 0.008713386756504965 9600684 +22 0.008712946580307425 9600199 + + +64 0.16176824859336478 178241352 +96 0.23147927881894828 255051161 +128 0.2646966482624612 291651105 + + +- Alternate memory interface to allow more caching in memory subsystem? + +-- The memory interface allows a dual port memory to be used +-- to increase performance. +-- +-- Also it is possible to implement a zero cycle register file instead +-- of memory, though obviously that will cause problems w.r.t. max +-- frequency for the ZPU. +-- +-- mem_writeEnable - set to '1' for a single cycle to send off a write request. +-- mem_write is valid only while mem_writeEnable='1'. +-- mem_readEnable - set to '1' for a single cycle to send off a read request. +-- mem_read is a single cycle while mem_read_busy='0'. +-- +-- mem_read/write_busy - It is illegal to send off a read/write request when mem_read/write_busy='1'. +-- Set to '0' when mem_read is valid after a read request. Note that +-- the definition allows zero wait state ram. +-- mem_read/write_addr - address for read/write request +-- mem_read - read data. Valid only on the cycle after mem_busy='0' after +-- mem_readEnable='1' for a single cycle. +-- mem_write - data to write +-- mem_writeMask - set to '1' for those bits that are to be written to memory upon +-- write request +-- break - set to '1' when CPU hits break instruction +-- interrupt - set to '1' until interrupts are cleared by CPU. diff --git a/zpu/hdl/zpu4/src/testlut.vhd b/zpu/hdl/zpu4/src/testlut.vhd new file mode 100644 index 0000000..668efcc --- /dev/null +++ b/zpu/hdl/zpu4/src/testlut.vhd @@ -0,0 +1,114 @@ +-- Company: Zylin AS +-- +-- Hooks up the ZPU to physical pads to ensure that it is not optimized to +-- oblivion. This is purely to have something to measure LUT usage against. +-- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity ic300 is + port ( -- Clock inputs + cpu_clk_p : in std_logic; + + -- CPU interface signals + cpu_a_p : in std_logic_vector(20 downto 0); + cpu_wr_n_p : in std_logic_vector(1 downto 0); + cpu_cs_n_p : in std_logic_vector(3 downto 1); + cpu_oe_n_p : in std_logic; + cpu_d_p : out std_logic_vector(15 downto 0); + cpu_irq_p : out std_logic_vector(1 downto 0); + cpu_fiq_p : out std_logic; + cpu_wait_n_p : out std_logic; + + sdr_clk_fb_p : in std_logic -- DDR clock feedback + ); +end ic300; + +architecture behave of ic300 is + + +signal io_busy : std_logic; +signal io_read : std_logic_vector(7 downto 0); +signal io_write : std_logic_vector(7 downto 0); +signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit); +signal io_writeEnable : std_logic; +signal io_readEnable : std_logic; + + +signal cpu_we : std_logic_vector(1 downto 0); +signal cpu_re : std_logic; +signal areset : std_logic; + +-- Clock module signals +signal clk_status : std_logic_vector(2 downto 0); +signal cpu_clk : std_logic; +signal cpu_clk_2x : std_logic; +signal cpu_clk_4x : std_logic; +signal ddr_in_clk : std_logic; + + +-- Internal CPU interface signals +signal cpu_din : std_logic_vector(15 downto 0); +signal cpu_dout : std_logic_vector(15 downto 0); +signal cpu_a : std_logic_vector(20 downto 0); + +signal dummy : std_logic_vector(maxAddrBit downto minAddrBit+5); + +signal dummy2 : std_logic_vector(wordSize-1 downto 0); +signal dummy3 : std_logic_vector(wordSize-1 downto 0); +signal dummy4 : std_logic_vector(wordSize-1 downto 0); +begin + + areset <= '0'; -- MUST BE CHANGED TO SOMETHING CORRECT + +-- cpu_d_p <= (others => '0'); + cpu_irq_p <= (others => '0'); + cpu_fiq_p <= '0'; + cpu_wait_n_p <= '0'; + + cpu_d_p(15 downto 15) <= (others => '0'); + + -- delay signals going out/in w/1 clk so the + -- ZPU does not have to drive those pins. + -- + -- these registers can be placed close to the ZPU and these + -- registers then have a full clock to drive the pins. + process(cpu_clk_p, areset) + begin + if (cpu_clk_p'event and cpu_clk_p = '1') then + cpu_d_p(0) <= io_writeEnable; + cpu_d_p(1) <= io_readEnable; + cpu_d_p(9 downto 2) <= io_write; + io_read <= cpu_a_p(7 downto 0); + -- 32 read/write registers is plenty realisitic for a minimal size + -- soft-CPU + cpu_d_p(14 downto 10) <= io_addr(minAddrBit+4 downto minAddrBit); + end if; + end process; + + + zpu: zpu_core port map ( + clk => cpu_clk_p , + areset => areset, + enable => '1', + + in_mem_busy => '0', + out_mem_writeEnable => io_writeEnable, + out_mem_readEnable => io_readEnable, + mem_write(7 downto 0) => io_write, + mem_write(wordSize-1 downto 8) => dummy3(wordSize-1 downto 8), + mem_read(7 downto 0) => io_read, + mem_read(wordSize-1 downto 8) => dummy2(wordSize-1 downto 8), + out_mem_addr(maxAddrBitIncIO) => dummy4(maxAddrBitIncIO), + out_mem_addr(minAddrBit-1 downto 0) => dummy4(minAddrBit-1 downto 0) , + out_mem_addr(maxAddrBit downto minAddrBit) => io_addr, + interrupt => '0' + ); + + +end behave; diff --git a/zpu/hdl/zpu4/src/timer.vhd b/zpu/hdl/zpu4/src/timer.vhd new file mode 100644 index 0000000..60c8fe2 --- /dev/null +++ b/zpu/hdl/zpu4/src/timer.vhd @@ -0,0 +1,61 @@ +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity timer is + port( + clk : in std_logic; + areset : in std_logic; + we : in std_logic; + din : in std_logic_vector(7 downto 0); + adr : in std_logic_vector(2 downto 0); + dout : out std_logic_vector(7 downto 0)); +end timer; + + +architecture behave of timer is + +signal sample : std_logic; +signal reset : std_logic; + + +signal cnt : std_logic_vector(63 downto 0); +signal cnt_smp : std_logic_vector(63 downto 0); + +begin + + reset <= '1' when (we = '1' and din(0) = '1') else '0'; + sample <= '1' when (we = '1' and din(1) = '1') else '0'; + + process(clk, areset) -- Carry generation + begin + if areset = '1' then + cnt <= (others => '0'); + cnt_smp <= (others => '0'); + elsif (clk'event and clk = '1') then + cnt <= cnt + 1; + if sample = '1' then +-- report "sampling" severity failure; + cnt_smp <= cnt; + end if; + end if; + end process; + + + process(cnt_smp, adr) + begin + case adr is + when "000" => dout <= cnt_smp(7 downto 0); + when "001" => dout <= cnt_smp(15 downto 8); + when "010" => dout <= cnt_smp(23 downto 16); + when "011" => dout <= cnt_smp(31 downto 24); + when "100" => dout <= cnt_smp(39 downto 32); + when "101" => dout <= cnt_smp(47 downto 40); + when "110" => dout <= cnt_smp(55 downto 48); + when others => dout <= cnt_smp(63 downto 56); + end case; + end process; + + +end behave; + diff --git a/zpu/hdl/zpu4/src/trace.vhd b/zpu/hdl/zpu4/src/trace.vhd new file mode 100644 index 0000000..bc5279f --- /dev/null +++ b/zpu/hdl/zpu4/src/trace.vhd @@ -0,0 +1,84 @@ +library ieee; +use ieee.std_logic_1164.all; +--use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +use std.textio.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; +use work.txt_util.all; + + +entity trace is + generic ( + log_file: string := "trace.txt" + ); + port( + clk : in std_logic; + begin_inst : in std_logic; + pc : in std_logic_vector(maxAddrBitIncIO downto 0); + opcode : in std_logic_vector(7 downto 0); + sp : in std_logic_vector(maxAddrBitIncIO downto 2); + memA : in std_logic_vector(wordSize-1 downto 0); + memB : in std_logic_vector(wordSize-1 downto 0); + busy : in std_logic; + intSp : in std_logic_vector(stack_bits-1 downto 0) + ); +end trace; + + +architecture behave of trace is + + +file l_file : TEXT open write_mode is log_file; + + +begin + + +-- write data and control information to a file + +receive_data: process + +variable l: line; +variable t : std_logic_vector(wordSize-1 downto 0); +variable t2 : std_logic_vector(maxAddrBitIncIO downto 0); +variable counter : std_logic_vector(63 downto 0); + + + +begin + + t:= (others => '0'); + t2:= (others => '0'); + +counter := (others => '0'); + -- print header for the logfile + print(l_file, "#pc,opcode,sp,top_of_stack "); + print(l_file, "#----------"); + print(l_file, " "); + + wait until clk = '1'; + wait until clk = '0'; + + while true loop + + counter := counter + 1; + if begin_inst = '1' then + t(maxAddrBitIncIO downto 2):=sp; + t2:=pc; + print(l_file, "0x" & hstr(t2) & " 0x" & hstr(opcode) & " 0x" & hstr(t) & " 0x" & hstr(memA) & " 0x" & hstr(memB) & " 0x" & hstr(intSp) & " 0x" & hstr(counter)); + end if; + + wait until clk = '0'; + + end loop; + + end process receive_data; + + + +end behave; + diff --git a/zpu/hdl/zpu4/src/txt_util.vhd b/zpu/hdl/zpu4/src/txt_util.vhd new file mode 100644 index 0000000..d3bf01a --- /dev/null +++ b/zpu/hdl/zpu4/src/txt_util.vhd @@ -0,0 +1,587 @@ +library ieee; +use ieee.std_logic_1164.all; +use std.textio.all; + +library work; + +package txt_util is + + -- prints a message to the screen + procedure print(text: string); + + -- prints the message when active + -- useful for debug switches + procedure print(active: boolean; text: string); + + -- converts std_logic into a character + function chr(sl: std_logic) return character; + + -- converts std_logic into a string (1 to 1) + function str(sl: std_logic) return string; + + -- converts std_logic_vector into a string (binary base) + function str(slv: std_logic_vector) return string; + + -- converts boolean into a string + function str(b: boolean) return string; + + -- converts an integer into a single character + -- (can also be used for hex conversion and other bases) + function chr(int: integer) return character; + + -- converts integer into string using specified base + function str(int: integer; base: integer) return string; + + -- converts integer to string, using base 10 + function str(int: integer) return string; + + -- convert std_logic_vector into a string in hex format + function hstr(slv: std_logic_vector) return string; + + + -- functions to manipulate strings + ----------------------------------- + + -- convert a character to upper case + function to_upper(c: character) return character; + + -- convert a character to lower case + function to_lower(c: character) return character; + + -- convert a string to upper case + function to_upper(s: string) return string; + + -- convert a string to lower case + function to_lower(s: string) return string; + + + + -- functions to convert strings into other formats + -------------------------------------------------- + + -- converts a character into std_logic + function to_std_logic(c: character) return std_logic; + + -- converts a string into std_logic_vector + function to_std_logic_vector(s: string) return std_logic_vector; + + + + -- file I/O + ----------- + + -- read variable length string from input file + procedure str_read(file in_file: TEXT; + res_string: out string); + + -- print string to a file and start new line + procedure print(file out_file: TEXT; + new_string: in string); + + -- print character to a file and start new line + procedure print(file out_file: TEXT; + char: in character); + +end txt_util; + + + + +package body txt_util is + + + + + -- prints text to the screen + + procedure print(text: string) is + variable msg_line: line; + begin + write(msg_line, text); + writeline(output, msg_line); + end print; + + + + + -- prints text to the screen when active + + procedure print(active: boolean; text: string) is + begin + if active then + print(text); + end if; + end print; + + + -- converts std_logic into a character + + function chr(sl: std_logic) return character is + variable c: character; + begin + case sl is + when 'U' => c:= 'U'; + when 'X' => c:= 'X'; + when '0' => c:= '0'; + when '1' => c:= '1'; + when 'Z' => c:= 'Z'; + when 'W' => c:= 'W'; + when 'L' => c:= 'L'; + when 'H' => c:= 'H'; + when '-' => c:= '-'; + end case; + return c; + end chr; + + + + -- converts std_logic into a string (1 to 1) + + function str(sl: std_logic) return string is + variable s: string(1 to 1); + begin + s(1) := chr(sl); + return s; + end str; + + + + -- converts std_logic_vector into a string (binary base) + -- (this also takes care of the fact that the range of + -- a string is natural while a std_logic_vector may + -- have an integer range) + + function str(slv: std_logic_vector) return string is + variable result : string (1 to slv'length); + variable r : integer; + begin + r := 1; + for i in slv'range loop + result(r) := chr(slv(i)); + r := r + 1; + end loop; + return result; + end str; + + + function str(b: boolean) return string is + + begin + if b then + return "true"; + else + return "false"; + end if; + end str; + + + -- converts an integer into a character + -- for 0 to 9 the obvious mapping is used, higher + -- values are mapped to the characters A-Z + -- (this is usefull for systems with base > 10) + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function chr(int: integer) return character is + variable c: character; + begin + case int is + when 0 => c := '0'; + when 1 => c := '1'; + when 2 => c := '2'; + when 3 => c := '3'; + when 4 => c := '4'; + when 5 => c := '5'; + when 6 => c := '6'; + when 7 => c := '7'; + when 8 => c := '8'; + when 9 => c := '9'; + when 10 => c := 'A'; + when 11 => c := 'B'; + when 12 => c := 'C'; + when 13 => c := 'D'; + when 14 => c := 'E'; + when 15 => c := 'F'; + when 16 => c := 'G'; + when 17 => c := 'H'; + when 18 => c := 'I'; + when 19 => c := 'J'; + when 20 => c := 'K'; + when 21 => c := 'L'; + when 22 => c := 'M'; + when 23 => c := 'N'; + when 24 => c := 'O'; + when 25 => c := 'P'; + when 26 => c := 'Q'; + when 27 => c := 'R'; + when 28 => c := 'S'; + when 29 => c := 'T'; + when 30 => c := 'U'; + when 31 => c := 'V'; + when 32 => c := 'W'; + when 33 => c := 'X'; + when 34 => c := 'Y'; + when 35 => c := 'Z'; + when others => c := '?'; + end case; + return c; + end chr; + + + + -- convert integer to string using specified base + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function str(int: integer; base: integer) return string is + + variable temp: string(1 to 10); + variable num: integer; + variable abs_int: integer; + variable len: integer := 1; + variable power: integer := 1; + + begin + + -- bug fix for negative numbers + abs_int := abs(int); + + num := abs_int; + + while num >= base loop -- Determine how many + len := len + 1; -- characters required + num := num / base; -- to represent the + end loop ; -- number. + + for i in len downto 1 loop -- Convert the number to + temp(i) := chr(abs_int/power mod base); -- a string starting + power := power * base; -- with the right hand + end loop ; -- side. + + -- return result and add sign if required + if int < 0 then + return '-'& temp(1 to len); + else + return temp(1 to len); + end if; + + end str; + + + -- convert integer to string, using base 10 + function str(int: integer) return string is + + begin + + return str(int, 10) ; + + end str; + + + + -- converts a std_logic_vector into a hex string. + function hstr(slv: std_logic_vector) return string is + variable hexlen: integer; + variable longslv : std_logic_vector(67 downto 0) := (others => '0'); + variable hex : string(1 to 16); + variable fourbit : std_logic_vector(3 downto 0); + begin + hexlen := (slv'left+1)/4; + if (slv'left+1) mod 4 /= 0 then + hexlen := hexlen + 1; + end if; + longslv(slv'left downto 0) := slv; + for i in (hexlen -1) downto 0 loop + fourbit := longslv(((i*4)+3) downto (i*4)); + case fourbit is + when "0000" => hex(hexlen -I) := '0'; + when "0001" => hex(hexlen -I) := '1'; + when "0010" => hex(hexlen -I) := '2'; + when "0011" => hex(hexlen -I) := '3'; + when "0100" => hex(hexlen -I) := '4'; + when "0101" => hex(hexlen -I) := '5'; + when "0110" => hex(hexlen -I) := '6'; + when "0111" => hex(hexlen -I) := '7'; + when "1000" => hex(hexlen -I) := '8'; + when "1001" => hex(hexlen -I) := '9'; + when "1010" => hex(hexlen -I) := 'A'; + when "1011" => hex(hexlen -I) := 'B'; + when "1100" => hex(hexlen -I) := 'C'; + when "1101" => hex(hexlen -I) := 'D'; + when "1110" => hex(hexlen -I) := 'E'; + when "1111" => hex(hexlen -I) := 'F'; + when "ZZZZ" => hex(hexlen -I) := 'z'; + when "UUUU" => hex(hexlen -I) := 'u'; + when "XXXX" => hex(hexlen -I) := 'x'; + when others => hex(hexlen -I) := '?'; + end case; + end loop; + return hex(1 to hexlen); + end hstr; + + + + -- functions to manipulate strings + ----------------------------------- + + + -- convert a character to upper case + + function to_upper(c: character) return character is + + variable u: character; + + begin + + case c is + when 'a' => u := 'A'; + when 'b' => u := 'B'; + when 'c' => u := 'C'; + when 'd' => u := 'D'; + when 'e' => u := 'E'; + when 'f' => u := 'F'; + when 'g' => u := 'G'; + when 'h' => u := 'H'; + when 'i' => u := 'I'; + when 'j' => u := 'J'; + when 'k' => u := 'K'; + when 'l' => u := 'L'; + when 'm' => u := 'M'; + when 'n' => u := 'N'; + when 'o' => u := 'O'; + when 'p' => u := 'P'; + when 'q' => u := 'Q'; + when 'r' => u := 'R'; + when 's' => u := 'S'; + when 't' => u := 'T'; + when 'u' => u := 'U'; + when 'v' => u := 'V'; + when 'w' => u := 'W'; + when 'x' => u := 'X'; + when 'y' => u := 'Y'; + when 'z' => u := 'Z'; + when others => u := c; + end case; + + return u; + + end to_upper; + + + -- convert a character to lower case + + function to_lower(c: character) return character is + + variable l: character; + + begin + + case c is + when 'A' => l := 'a'; + when 'B' => l := 'b'; + when 'C' => l := 'c'; + when 'D' => l := 'd'; + when 'E' => l := 'e'; + when 'F' => l := 'f'; + when 'G' => l := 'g'; + when 'H' => l := 'h'; + when 'I' => l := 'i'; + when 'J' => l := 'j'; + when 'K' => l := 'k'; + when 'L' => l := 'l'; + when 'M' => l := 'm'; + when 'N' => l := 'n'; + when 'O' => l := 'o'; + when 'P' => l := 'p'; + when 'Q' => l := 'q'; + when 'R' => l := 'r'; + when 'S' => l := 's'; + when 'T' => l := 't'; + when 'U' => l := 'u'; + when 'V' => l := 'v'; + when 'W' => l := 'w'; + when 'X' => l := 'x'; + when 'Y' => l := 'y'; + when 'Z' => l := 'z'; + when others => l := c; + end case; + + return l; + + end to_lower; + + + + -- convert a string to upper case + + function to_upper(s: string) return string is + + variable uppercase: string (s'range); + + begin + + for i in s'range loop + uppercase(i):= to_upper(s(i)); + end loop; + return uppercase; + + end to_upper; + + + + -- convert a string to lower case + + function to_lower(s: string) return string is + + variable lowercase: string (s'range); + + begin + + for i in s'range loop + lowercase(i):= to_lower(s(i)); + end loop; + return lowercase; + + end to_lower; + + + +-- functions to convert strings into other types + + +-- converts a character into a std_logic + +function to_std_logic(c: character) return std_logic is + variable sl: std_logic; + begin + case c is + when 'U' => + sl := 'U'; + when 'X' => + sl := 'X'; + when '0' => + sl := '0'; + when '1' => + sl := '1'; + when 'Z' => + sl := 'Z'; + when 'W' => + sl := 'W'; + when 'L' => + sl := 'L'; + when 'H' => + sl := 'H'; + when '-' => + sl := '-'; + when others => + sl := 'X'; + end case; + return sl; + end to_std_logic; + + +-- converts a string into std_logic_vector + +function to_std_logic_vector(s: string) return std_logic_vector is + variable slv: std_logic_vector(s'high-s'low downto 0); + variable k: integer; +begin + k := s'high-s'low; + for i in s'range loop + slv(k) := to_std_logic(s(i)); + k := k - 1; + end loop; + return slv; +end to_std_logic_vector; + + + + + + +---------------- +-- file I/O -- +---------------- + + + +-- read variable length string from input file + +procedure str_read(file in_file: TEXT; + res_string: out string) is + + variable l: line; + variable c: character; + variable is_string: boolean; + + begin + + readline(in_file, l); + -- clear the contents of the result string + for i in res_string'range loop + res_string(i) := ' '; + end loop; + -- read all characters of the line, up to the length + -- of the results string + for i in res_string'range loop + read(l, c, is_string); + res_string(i) := c; + if not is_string then -- found end of line + exit; + end if; + end loop; + +end str_read; + + +-- print string to a file +procedure print(file out_file: TEXT; + new_string: in string) is + + variable l: line; + + begin + + write(l, new_string); + writeline(out_file, l); + +end print; + + +-- print character to a file and start new line +procedure print(file out_file: TEXT; + char: in character) is + + variable l: line; + + begin + + write(l, char); + writeline(out_file, l); + +end print; + + + +-- appends contents of a string to a file until line feed occurs +-- (LF is considered to be the end of the string) + +procedure str_write(file out_file: TEXT; + new_string: in string) is + begin + + for i in new_string'range loop + print(out_file, new_string(i)); + if new_string(i) = LF then -- end of string + exit; + end if; + end loop; + +end str_write; + + + + +end txt_util; + + + + diff --git a/zpu/hdl/zpu4/src/xmake.filelist b/zpu/hdl/zpu4/src/xmake.filelist new file mode 100644 index 0000000..91e623f --- /dev/null +++ b/zpu/hdl/zpu4/src/xmake.filelist @@ -0,0 +1,12 @@ +vhdl work "ic300_config.vhd" +vhdl work "ic300pkg.vhd" +vhdl zylin "zpu_config.vhd" +vhdl zylin "zpupkg.vhd" +vhdl zylin "zpu_core.vhd" +vhdl work "bram.vhd" +vhdl zylin "zpuio.vhd" +vhdl zylin "..\dummyfpgalib\arm7\src\arm7pkg.vhd" +vhdl zylin "..\dummyfpgalib\arm7\src\arm7wb.vhd" +vhdl work "clocks.vhd" +vhdl work "timer.vhd" +vhdl work "ic300.vhd" \ No newline at end of file diff --git a/zpu/hdl/zpu4/src/xmake.filelist.bramsmall b/zpu/hdl/zpu4/src/xmake.filelist.bramsmall new file mode 100644 index 0000000..141633e --- /dev/null +++ b/zpu/hdl/zpu4/src/xmake.filelist.bramsmall @@ -0,0 +1,5 @@ +vhdl work "zpu_config.vhd" +vhdl work "zpupkg.vhd" +vhdl work "zpu_core_small.vhd" +vhdl work "bram_dmips.vhd" +vhdl work "testlut.vhd" diff --git a/zpu/hdl/zpu4/src/xmake.xst b/zpu/hdl/zpu4/src/xmake.xst new file mode 100644 index 0000000..bfdb23f --- /dev/null +++ b/zpu/hdl/zpu4/src/xmake.xst @@ -0,0 +1,53 @@ +set -tmpdir ../tmp +set -xsthdpdir ../xst +run +-ifn xmake.filelist +-ifmt mixed +-ofn ../syn/ic300 +-ofmt NGC +-p xc3s400-4-ft256 +-top ic300 +-opt_mode Area +-opt_level 2 +-iuc NO +-lso ic300.lso +-keep_hierarchy NO +-glob_opt AllClockNets +-rtlview Yes +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-rom_style Auto +-mux_extract YES +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-resource_sharing YES +-mult_style auto +-iobuf YES +-max_fanout 500 +-bufg 8 +-register_duplication YES +-equivalent_register_removal NO +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-use_clock_enable Yes +-use_sync_set No +-use_sync_reset No +-iob true +-slice_utilization_ratio_maxmargin 5 diff --git a/zpu/hdl/zpu4/src/zpu_config.vhd b/zpu/hdl/zpu4/src/zpu_config.vhd new file mode 100644 index 0000000..a13c0bf --- /dev/null +++ b/zpu/hdl/zpu4/src/zpu_config.vhd @@ -0,0 +1,16 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +package zpu_config is + -- generate trace output or not. + constant Generate_Trace : boolean := false; + constant wordPower : integer := 5; + -- during simulation, set this to '0' to get matching trace.txt + constant DontCareValue : std_logic := 'X'; + -- Clock frequency in MHz. + constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64"; + -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) + constant maxAddrBitIncIO : integer := 15; + +end zpu_config; diff --git a/zpu/hdl/zpu4/src/zpu_config_fastsim.vhd b/zpu/hdl/zpu4/src/zpu_config_fastsim.vhd new file mode 100644 index 0000000..d39c9e9 --- /dev/null +++ b/zpu/hdl/zpu4/src/zpu_config_fastsim.vhd @@ -0,0 +1,15 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +package zpu_config is + + constant Generate_Trace : boolean := false; + constant wordPower : integer := 5; + -- during simulation, set this to '0' to get matching trace.txt + constant DontCareValue : std_logic := '0'; + -- Clock frequency in MHz. + constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"50"; -- 80MHz + constant maxAddrBitIncIO : integer := 15; + +end zpu_config; diff --git a/zpu/hdl/zpu4/src/zpu_config_trace.vhd b/zpu/hdl/zpu4/src/zpu_config_trace.vhd new file mode 100644 index 0000000..d1bbbbb --- /dev/null +++ b/zpu/hdl/zpu4/src/zpu_config_trace.vhd @@ -0,0 +1,15 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +package zpu_config is + + constant Generate_Trace : boolean := true; + constant wordPower : integer := 5; + -- during simulation, set this to '0' to get matching trace.txt + constant DontCareValue : std_logic := '0'; + -- Clock frequency in MHz. + constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64"; + constant maxAddrBitIncIO : integer := 15; + +end zpu_config; diff --git a/zpu/hdl/zpu4/src/zpu_core.vhd b/zpu/hdl/zpu4/src/zpu_core.vhd new file mode 100644 index 0000000..c7093e2 --- /dev/null +++ b/zpu/hdl/zpu4/src/zpu_core.vhd @@ -0,0 +1,900 @@ + +-- Company: ZPU4 generic memory interface CPU +-- Engineer: Øyvind Harboe + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.STD_LOGIC_arith.ALL; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + + +-- mem_writeEnable - set to '1' for a single cycle to send off a write request. +-- mem_write is valid only while mem_writeEnable='1'. +-- mem_readEnable - set to '1' for a single cycle to send off a read request. +-- +-- mem_busy - It is illegal to send off a read/write request when mem_busy='1'. +-- Set to '0' when mem_read is valid after a read request. +-- If it goes to '1'(busy), it is on the cycle after mem_read/writeEnable +-- is '1'. +-- mem_addr - address for read/write request +-- mem_read - read data. Valid only on the cycle after mem_busy='0' after +-- mem_readEnable='1' for a single cycle. +-- mem_write - data to write +-- mem_writeMask - set to '1' for those bits that are to be written to memory upon +-- write request +-- break - set to '1' when CPU hits break instruction +-- interrupt - set to '1' until interrupts are cleared by CPU. + + + + +entity zpu_core is + Port ( clk : in std_logic; + areset : in std_logic; + enable : in std_logic; + in_mem_busy : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + out_mem_writeEnable : out std_logic; + out_mem_readEnable : out std_logic; + mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + interrupt : in std_logic; + break : out std_logic); +end zpu_core; + +architecture behave of zpu_core is + +type InsnType is +( +State_AddTop, +State_Dup, +State_DupStackB, +State_Pop, +State_Popdown, +State_Add, +State_Or, +State_And, +State_Store, +State_AddSP, +State_Shift, +State_Nop, +State_Im, +State_LoadSP, +State_StoreSP, +State_Emulate, +State_Load, +State_PushPC, +State_PushSP, +State_PopPC, +State_PopPCRel, +State_Not, +State_Flip, +State_PopSP, +State_Neqbranch, +State_Eq, +State_Loadb, +State_Mult, +State_Lessthan, +State_Lessthanorequal, +State_Ulessthanorequal, +State_Ulessthan, +State_Pushspadd, +State_Call, +State_Callpcrel, +State_Sub, +State_Break, +State_Storeb, +State_InsnFetch +); + +type StateType is +( +State_Load2, +State_Popped, +State_LoadSP2, +State_LoadSP3, +State_AddSP2, +State_Fetch, +State_Execute, +State_Decode, +State_Decode2, +State_Resync, + +State_StoreSP2, +State_Resync2, +State_Resync3, +State_Loadb2, +State_Storeb2, +State_Mult2, +State_Mult3, +State_Mult5, +State_Mult4, +State_BinaryOpResult2, +State_BinaryOpResult, +State_Idle +); + + +signal pc : std_logic_vector(maxAddrBitIncIO downto 0); +signal sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal incSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal incIncSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal decSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal stackA : std_logic_vector(wordSize-1 downto 0); +signal binaryOpResult : std_logic_vector(wordSize-1 downto 0); +signal binaryOpResult2 : std_logic_vector(wordSize-1 downto 0); +signal multResult2 : std_logic_vector(wordSize-1 downto 0); +signal multResult3 : std_logic_vector(wordSize-1 downto 0); +signal multResult : std_logic_vector(wordSize-1 downto 0); +signal multA : std_logic_vector(wordSize-1 downto 0); +signal multB : std_logic_vector(wordSize-1 downto 0); +signal stackB : std_logic_vector(wordSize-1 downto 0); +signal idim_flag : std_logic; +signal busy : std_logic; +signal mem_writeEnable : std_logic; +signal mem_readEnable : std_logic; +signal mem_addr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal mem_delayAddr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal mem_delayReadEnable : std_logic; + +signal decodeWord : std_logic_vector(wordSize-1 downto 0); + + +signal state : StateType; +signal insn : InsnType; +type InsnArray is array(0 to wordBytes-1) of InsnType; +signal decodedOpcode : InsnArray; + +type OpcodeArray is array(0 to wordBytes-1) of std_logic_vector(7 downto 0); + +signal opcode : OpcodeArray; + + + + +signal begin_inst : std_logic; +signal trace_opcode : std_logic_vector(7 downto 0); +signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); +signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); +signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); + +-- state machine. + +begin + + + traceFileGenerate: + if Generate_Trace generate + trace_file: trace port map ( + clk => clk, + begin_inst => begin_inst, + pc => trace_pc, + opcode => trace_opcode, + sp => trace_sp, + memA => trace_topOfStack, + memB => trace_topOfStackB, + busy => busy, + intsp => (others => 'U') + ); + end generate; + + + -- the memory subsystem will tell us one cycle later whether or + -- not it is busy + out_mem_writeEnable <= mem_writeEnable; + out_mem_readEnable <= mem_readEnable; + out_mem_addr(maxAddrBitIncIO downto minAddrBit) <= mem_addr; + out_mem_addr(minAddrBit-1 downto 0) <= (others => '0'); + + incSp <= sp + 1; + incIncSp <= sp + 2; + decSp <= sp - 1; + + + opcodeControl: + process(clk, areset) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + variable spOffset : std_logic_vector(4 downto 0); + variable tSpOffset : std_logic_vector(4 downto 0); + variable nextPC : std_logic_vector(maxAddrBitIncIO downto 0); + variable tNextState : InsnType; + variable tDecodedOpcode : InsnArray; + variable tMultResult : std_logic_vector(wordSize*2-1 downto 0); + begin + if areset = '1' then + state <= State_Idle; + break <= '0'; + -- point to top of RAM-8 + sp <= (others => '0'); + sp(maxAddrBit downto minAddrBit+1) <= (others => '1'); + + pc <= (others => '0'); + idim_flag <= '0'; + begin_inst <= '0'; + mem_writeEnable <= '0'; + mem_readEnable <= '0'; + multA <= (others => '0'); + multB <= (others => '0'); + mem_writeMask <= (others => '1'); + elsif (clk'event and clk = '1') then + -- we must multiply unconditionally to get pipelined multiplication + tMultResult := multA * multB; + multResult3 <= multResult2; + multResult2 <= multResult; + multResult <= tMultResult(wordSize-1 downto 0); + + + binaryOpResult2 <= binaryOpResult; -- pipeline a bit. + + + multA <= (others => DontCareValue); + multB <= (others => DontCareValue); + + + mem_addr <= (others => DontCareValue); + mem_readEnable <='0'; + mem_writeEnable <='0'; + mem_write <= (others => DontCareValue); + + if (mem_writeEnable = '1') and (mem_readEnable = '1') then + report "read/write collision" severity failure; + end if; + + + + + spOffset(4):=not opcode(conv_integer(pc(byteBits-1 downto 0)))(4); + spOffset(3 downto 0):=opcode(conv_integer(pc(byteBits-1 downto 0)))(3 downto 0); + nextPC := pc + 1; + + -- prepare trace snapshot + trace_opcode <= opcode(conv_integer(pc(byteBits-1 downto 0))); + trace_pc <= pc; + trace_sp <= sp; + trace_topOfStack <= stackA; + trace_topOfStackB <= stackB; + begin_inst <= '0'; + + + case state is + when State_Idle => + if enable='1' then + state <= State_Resync; + end if; + -- Initial state of ZPU, fetch top of stack + first instruction + when State_Resync => + if in_mem_busy='0' then + mem_addr <= sp; + mem_readEnable <= '1'; + state <= State_Resync2; + end if; + when State_Resync2 => + if in_mem_busy='0' then + stackA <= mem_read; + mem_addr <= incSp; + mem_readEnable <= '1'; + state <= State_Resync3; + end if; + when State_Resync3 => + if in_mem_busy='0' then + stackB <= mem_read; + mem_addr <= pc(maxAddrBitIncIO downto minAddrBit); + mem_readEnable <= '1'; + state <= State_Decode; + end if; + when State_Decode => + if in_mem_busy='0' then + decodeWord <= mem_read; + state <= State_Decode2; + end if; + when State_Decode2 => + -- decode 4 instructions in parallel + for i in 0 to wordBytes-1 loop + tOpcode := decodeWord((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8); + + tSpOffset(4):=not tOpcode(4); + tSpOffset(3 downto 0):=tOpcode(3 downto 0); + + opcode(i) <= tOpcode; + if (tOpcode(7 downto 7)=OpCode_Im) then + tNextState:=State_Im; + elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then + if tSpOffset = 0 then + tNextState := State_Pop; + elsif tSpOffset=1 then + tNextState := State_PopDown; + else + tNextState :=State_StoreSP; + end if; + elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then + if tSpOffset = 0 then + tNextState :=State_Dup; + elsif tSpOffset = 1 then + tNextState :=State_DupStackB; + else + tNextState :=State_LoadSP; + end if; + elsif (tOpcode(7 downto 5)=OpCode_Emulate) then + tNextState :=State_Emulate; + if tOpcode(5 downto 0)=OpCode_Neqbranch then + tNextState :=State_Neqbranch; + elsif tOpcode(5 downto 0)=OpCode_Eq then + tNextState :=State_Eq; + elsif tOpcode(5 downto 0)=OpCode_Lessthan then + tNextState :=State_Lessthan; + elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then + --tNextState :=State_Lessthanorequal; + elsif tOpcode(5 downto 0)=OpCode_Ulessthan then + tNextState :=State_Ulessthan; + elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then + --tNextState :=State_Ulessthanorequal; + elsif tOpcode(5 downto 0)=OpCode_Loadb then + tNextState :=State_Loadb; + elsif tOpcode(5 downto 0)=OpCode_Mult then + tNextState :=State_Mult; + elsif tOpcode(5 downto 0)=OpCode_Storeb then + tNextState :=State_Storeb; + elsif tOpcode(5 downto 0)=OpCode_Pushspadd then + tNextState :=State_Pushspadd; + elsif tOpcode(5 downto 0)=OpCode_Callpcrel then + tNextState :=State_Callpcrel; + elsif tOpcode(5 downto 0)=OpCode_Call then + --tNextState :=State_Call; + elsif tOpcode(5 downto 0)=OpCode_Sub then + tNextState :=State_Sub; + elsif tOpcode(5 downto 0)=OpCode_PopPCRel then + --tNextState :=State_PopPCRel; + end if; + elsif (tOpcode(7 downto 4)=OpCode_AddSP) then + if tSpOffset = 0 then + tNextState := State_Shift; + elsif tSpOffset = 1 then + tNextState := State_AddTop; + else + tNextState :=State_AddSP; + end if; + else + case tOpcode(3 downto 0) is + when OpCode_Nop => + tNextState :=State_Nop; + when OpCode_PushSP => + tNextState :=State_PushSP; + when OpCode_PopPC => + tNextState :=State_PopPC; + when OpCode_Add => + tNextState :=State_Add; + when OpCode_Or => + tNextState :=State_Or; + when OpCode_And => + tNextState :=State_And; + when OpCode_Load => + tNextState :=State_Load; + when OpCode_Not => + tNextState :=State_Not; + when OpCode_Flip => + tNextState :=State_Flip; + when OpCode_Store => + tNextState :=State_Store; + when OpCode_PopSP => + tNextState :=State_PopSP; + when others => + tNextState := State_Break; + + end case; + end if; + tDecodedOpcode(i) := tNextState; + + end loop; + + insn <= tDecodedOpcode(conv_integer(pc(byteBits-1 downto 0))); + + -- once we wrap, we need to fetch + tDecodedOpcode(0) := State_InsnFetch; + + decodedOpcode <= tDecodedOpcode; + state <= State_Execute; + + + + -- Each instruction must: + -- + -- 1. set idim_flag + -- 2. increase pc if applicable + -- 3. set next state if appliable + -- 4. do it's operation + + when State_Execute => + insn <= decodedOpcode(conv_integer(nextPC(byteBits-1 downto 0))); + + case insn is + when State_InsnFetch => + state <= State_Fetch; + when State_Im => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '1'; + pc <= pc + 1; + + if idim_flag='1' then + stackA(wordSize-1 downto 7) <= stackA(wordSize-8 downto 0); + stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0); + else + mem_writeEnable <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + stackB <= stackA; + sp <= decSp; + for i in wordSize-1 downto 7 loop + stackA(i) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6); + end loop; + stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0); + end if; + end if; + when State_StoreSP => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_StoreSP2; + + mem_writeEnable <= '1'; + mem_addr <= sp+spOffset; + mem_write <= stackA; + stackA <= stackB; + sp <= incSp; + end if; + + + when State_LoadSP => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_LoadSP2; + + sp <= decSp; + mem_writeEnable <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + end if; + when State_Emulate => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + sp <= decSp; + mem_writeEnable <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + stackB <= stackA; + + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= (others => '0'); + pc(9 downto 5) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(4 downto 0); + state <= State_Fetch; + end if; + when State_Callpcrel => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + + pc <= pc + stackA(maxAddrBitIncIO downto 0); + state <= State_Fetch; + end if; + when State_Call => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + pc <= stackA(maxAddrBitIncIO downto 0); + state <= State_Fetch; + end if; + when State_AddSP => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_AddSP2; + + mem_readEnable <= '1'; + mem_addr <= sp+spOffset; + end if; + when State_PushSP => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackA <= (others => '0'); + stackA(maxAddrBitIncIO downto minAddrBit) <= sp; + stackB <= stackA; + mem_writeEnable <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + end if; + when State_PopPC => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= stackA(maxAddrBitIncIO downto 0); + sp <= incSp; + + mem_writeEnable <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + state <= State_Resync; + end if; + when State_PopPCRel => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= stackA(maxAddrBitIncIO downto 0) + pc; + sp <= incSp; + + mem_writeEnable <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + state <= State_Resync; + end if; + when State_Add => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= stackA + stackB; + + mem_readEnable <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + state <= State_Popped; + end if; + when State_Sub => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + binaryOpResult <= stackB - stackA; + state <= State_BinaryOpResult; + end if; + when State_Pop => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + mem_addr <= incIncSp; + mem_readEnable <= '1'; + sp <= incSp; + stackA <= stackB; + state <= State_Popped; + end if; + when State_PopDown => + if in_mem_busy='0' then + -- PopDown leaves top of stack unchanged + begin_inst <= '1'; + idim_flag <= '0'; + mem_addr <= incIncSp; + mem_readEnable <= '1'; + sp <= incSp; + state <= State_Popped; + end if; + when State_Or => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= stackA or stackB; + mem_readEnable <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + state <= State_Popped; + end if; + when State_And => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + stackA <= stackA and stackB; + mem_readEnable <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + state <= State_Popped; + end if; + when State_Eq => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA=stackB) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + end if; + when State_Ulessthan => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA<=stackB) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + end if; + when State_Lessthan => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (signed(stackA) + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (signed(stackA)<=signed(stackB)) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + end if; + when State_Load => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Load2; + + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + mem_readEnable <= '1'; + end if; + + when State_Dup => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackB <= stackA; + mem_write <= stackB; + mem_addr <= incSp; + mem_writeEnable <= '1'; + end if; + when State_DupStackB => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackA <= stackB; + stackB <= stackA; + mem_write <= stackB; + mem_addr <= incSp; + mem_writeEnable <= '1'; + end if; + when State_Store => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + mem_write <= stackB; + mem_writeEnable <= '1'; + sp <= incIncSp; + state <= State_Resync; + end if; + when State_PopSP => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + mem_write <= stackB; + mem_addr <= incSp; + mem_writeEnable <= '1'; + sp <= stackA(maxAddrBitIncIO downto minAddrBit); + state <= State_Resync; + end if; + when State_Nop => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + when State_Not => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= not stackA; + when State_Flip => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + for i in 0 to wordSize-1 loop + stackA(i) <= stackA(wordSize-1-i); + end loop; + when State_AddTop => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= stackA + stackB; + when State_Shift => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0); + stackA(0) <= '0'; + when State_Pushspadd => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= (others => '0'); + stackA(maxAddrBitIncIO downto minAddrBit) <= stackA(maxAddrBitIncIO-minAddrBit downto 0)+sp; + when State_Neqbranch => + -- branches are almost always taken as they form loops + begin_inst <= '1'; + idim_flag <= '0'; + sp <= incIncSp; + if (stackB/=0) then + pc <= stackA(maxAddrBitIncIO downto 0) + pc; + else + pc <= pc + 1; + end if; + -- need to fetch stack again. + state <= State_Resync; + when State_Mult => + begin_inst <= '1'; + idim_flag <= '0'; + + multA <= stackA; + multB <= stackB; + state <= State_Mult2; + when State_Break => + report "Break instruction encountered" severity failure; + break <= '1'; + + when State_Loadb => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Loadb2; + + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + mem_readEnable <= '1'; + end if; + when State_Storeb => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Storeb2; + + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + mem_readEnable <= '1'; + end if; + + when others => + sp <= (others => DontCareValue); + report "Illegal instruction" severity failure; + break <= '1'; + end case; + + + when State_StoreSP2 => + if in_mem_busy='0' then + mem_addr <= incSp; + mem_readEnable <= '1'; + state <= State_Popped; + end if; + when State_LoadSP2 => + if in_mem_busy='0' then + state <= State_LoadSP3; + mem_readEnable <= '1'; + mem_addr <= sp+spOffset+1; + end if; + when State_LoadSP3 => + if in_mem_busy='0' then + pc <= pc + 1; + state <= State_Execute; + stackB <= stackA; + stackA <= mem_read; + end if; + when State_AddSP2 => + if in_mem_busy='0' then + pc <= pc + 1; + state <= State_Execute; + stackA <= stackA + mem_read; + end if; + when State_Load2 => + if in_mem_busy='0' then + stackA <= mem_read; + pc <= pc + 1; + state <= State_Execute; + end if; + when State_Loadb2 => + if in_mem_busy='0' then + stackA <= (others => '0'); + stackA(7 downto 0) <= mem_read(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8); + pc <= pc + 1; + state <= State_Execute; + end if; + when State_Storeb2 => + if in_mem_busy='0' then + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + mem_write <= mem_read; + mem_write(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8) <= stackB(7 downto 0) ; + mem_writeEnable <= '1'; + pc <= pc + 1; + sp <= incIncSp; + state <= State_Resync; + end if; + when State_Fetch => + if in_mem_busy='0' then + mem_addr <= pc(maxAddrBitIncIO downto minAddrBit); + mem_readEnable <= '1'; + state <= State_Decode; + end if; + when State_Mult2 => + state <= State_Mult3; + when State_Mult3 => + state <= State_Mult4; + when State_Mult4 => + state <= State_Mult5; + when State_Mult5 => + if in_mem_busy='0' then + stackA <= multResult3; + mem_readEnable <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + state <= State_Popped; + end if; + when State_BinaryOpResult => + state <= State_BinaryOpResult2; + when State_BinaryOpResult2 => + mem_readEnable <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + stackA <= binaryOpResult2; + state <= State_Popped; + when State_Popped => + if in_mem_busy='0' then + pc <= pc + 1; + stackB <= mem_read; + state <= State_Execute; + end if; + when others => + sp <= (others => DontCareValue); + report "Illegal state" severity failure; + break <= '1'; + end case; + end if; + end process; + + + +end behave; diff --git a/zpu/hdl/zpu4/src/zpu_core_small.vhd b/zpu/hdl/zpu4/src/zpu_core_small.vhd new file mode 100644 index 0000000..4d73f88 --- /dev/null +++ b/zpu/hdl/zpu4/src/zpu_core_small.vhd @@ -0,0 +1,433 @@ +-- Company: ZPU3 +-- Engineer: Øyvind Harboe + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + + +entity zpu_core is + Port ( clk : in std_logic; + areset : in std_logic; + enable : in std_logic; + in_mem_busy : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + out_mem_writeEnable : out std_logic; + out_mem_readEnable : out std_logic; + mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + interrupt : in std_logic; + break : out std_logic); +end zpu_core; + +architecture behave of zpu_core is + +signal readIO : std_logic; + + + +signal memAWriteEnable : std_logic; +signal memAAddr : std_logic_vector(maxAddrBit downto minAddrBit); +signal memAWrite : std_logic_vector(wordSize-1 downto 0); +signal memARead : std_logic_vector(wordSize-1 downto 0); +signal memBWriteEnable : std_logic; +signal memBAddr : std_logic_vector(maxAddrBit downto minAddrBit); +signal memBWrite : std_logic_vector(wordSize-1 downto 0); +signal memBRead : std_logic_vector(wordSize-1 downto 0); + + + +signal pc : std_logic_vector(maxAddrBit downto 0); +signal sp : std_logic_vector(maxAddrBit downto minAddrBit); + +signal idim_flag : std_logic; + +--signal storeToStack : std_logic; +--signal fetchNextInstruction : std_logic; +--signal extraCycle : std_logic; +signal busy : std_logic; +--signal fetching : std_logic; + +signal begin_inst : std_logic; + + + +signal trace_opcode : std_logic_vector(7 downto 0); +signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); +signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); +signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); + +-- state machine. +type State_Type is +( +State_Fetch, +State_WriteIODone, +State_Execute, +State_StoreToStack, +State_Add, +State_Or, +State_And, +State_Store, +State_ReadIO, +State_WriteIO, +State_Load, +State_FetchNext, +State_AddSP, +State_ReadIODone, +State_Decode, +State_Resync +); + +type DecodedOpcodeType is +( +Decoded_Nop, +Decoded_Im, +Decoded_ImShift, +Decoded_LoadSP, +Decoded_StoreSP , +Decoded_AddSP, +Decoded_Emulate, +Decoded_Break, +Decoded_PushSP, +Decoded_PopPC, +Decoded_Add, +Decoded_Or, +Decoded_And, +Decoded_Load, +Decoded_Not, +Decoded_Flip, +Decoded_Store, +Decoded_PopSP +); + + + +signal sampledOpcode : std_logic_vector(OpCode_Size-1 downto 0); +signal opcode : std_logic_vector(OpCode_Size-1 downto 0); + +signal decodedOpcode : DecodedOpcodeType; +signal sampledDecodedOpcode : DecodedOpcodeType; + + +signal state : State_Type; + +begin + traceFileGenerate: + if Generate_Trace generate + trace_file: trace port map ( + clk => clk, + begin_inst => begin_inst, + pc => trace_pc, + opcode => trace_opcode, + sp => trace_sp, + memA => trace_topOfStack, + memB => trace_topOfStackB, + busy => busy, + intsp => (others => 'U') + ); + end generate; + + + memory: dualport_ram port map ( + clk => clk, + memAWriteEnable => memAWriteEnable, + memAAddr => memAAddr(maxAddrBitBRAM downto minAddrBit), + memAWrite => memAWrite, + memARead => memARead, + memBWriteEnable => memBWriteEnable, + memBAddr => memBAddr(maxAddrBitBRAM downto minAddrBit), + memBWrite => memBWrite, + memBRead => memBRead + ); + + + + decodeControl: + process(memBRead, pc) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + begin + tOpcode := memBRead((wordBytes-1-conv_integer(pc(minAddrBit-1 downto 0))+1)*8-1 downto (wordBytes-1-conv_integer(pc(minAddrBit-1 downto 0)))*8); + + sampledOpcode <= tOpcode; + + if (tOpcode(7 downto 7)=OpCode_Im) then + sampledDecodedOpcode<=Decoded_Im; + elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then + sampledDecodedOpcode<=Decoded_StoreSP; + elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then + sampledDecodedOpcode<=Decoded_LoadSP; + elsif (tOpcode(7 downto 5)=OpCode_Emulate) then + sampledDecodedOpcode<=Decoded_Emulate; + elsif (tOpcode(7 downto 4)=OpCode_AddSP) then + sampledDecodedOpcode<=Decoded_AddSP; + else + case tOpcode(3 downto 0) is + when OpCode_Break => + sampledDecodedOpcode<=Decoded_Break; + when OpCode_PushSP => + sampledDecodedOpcode<=Decoded_PushSP; + when OpCode_PopPC => + sampledDecodedOpcode<=Decoded_PopPC; + when OpCode_Add => + sampledDecodedOpcode<=Decoded_Add; + when OpCode_Or => + sampledDecodedOpcode<=Decoded_Or; + when OpCode_And => + sampledDecodedOpcode<=Decoded_And; + when OpCode_Load => + sampledDecodedOpcode<=Decoded_Load; + when OpCode_Not => + sampledDecodedOpcode<=Decoded_Not; + when OpCode_Flip => + sampledDecodedOpcode<=Decoded_Flip; + when OpCode_Store => + sampledDecodedOpcode<=Decoded_Store; + when OpCode_PopSP => + sampledDecodedOpcode<=Decoded_PopSP; + when others => + sampledDecodedOpcode<=Decoded_Nop; + end case; + end if; + end process; + + + opcodeControl: + process(clk, areset) + variable spOffset : std_logic_vector(4 downto 0); + begin + if areset = '1' then + state <= State_Resync; + break <= '0'; + sp <= spStart(maxAddrBit downto minAddrBit); + pc <= (others => '0'); + idim_flag <= '0'; + begin_inst <= '0'; + memAAddr <= (others => '0'); + memBAddr <= (others => '0'); + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + out_mem_writeEnable <= '0'; + out_mem_readEnable <= '0'; + memAWrite <= (others => '0'); + memBWrite <= (others => '0'); + mem_writeMask <= (others => '1'); + elsif (clk'event and clk = '1') then + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + -- This saves ca. 100 LUT's, by explicitly declaring that the + -- memAWrite can be left at whatever value if memAWriteEnable is + -- not set. + memAWrite <= (others => DontCareValue); + memBWrite <= (others => DontCareValue); +-- out_mem_addr <= (others => DontCareValue); +-- mem_write <= (others => DontCareValue); + spOffset := (others => DontCareValue); + memAAddr <= (others => DontCareValue); + memBAddr <= (others => DontCareValue); + + out_mem_writeEnable <= '0'; + out_mem_readEnable <= '0'; + begin_inst <= '0'; + out_mem_addr <= memARead(maxAddrBitIncIO downto 0); + mem_write <= memBRead; + + decodedOpcode <= sampledDecodedOpcode; + opcode <= sampledOpcode; + + case state is + when State_Execute => + state <= State_Fetch; + -- at this point: + -- memBRead contains opcode word + -- memARead contains top of stack + pc <= pc + 1; + + -- trace + begin_inst <= '1'; + trace_pc <= (others => '0'); + trace_pc(maxAddrBit downto 0) <= pc; + trace_opcode <= opcode; + trace_sp <= (others => '0'); + trace_sp(maxAddrBit downto minAddrBit) <= sp; + trace_topOfStack <= memARead; + trace_topOfStackB <= memBRead; + + -- during the next cycle we'll be reading the next opcode + spOffset(4):=not opcode(4); + spOffset(3 downto 0):=opcode(3 downto 0); + + idim_flag <= '0'; + case decodedOpcode is + when Decoded_Im => + idim_flag <= '1'; + memAWriteEnable <= '1'; + if (idim_flag='0') then + sp <= sp - 1; + memAAddr <= sp-1; + for i in wordSize-1 downto 7 loop + memAWrite(i) <= opcode(6); + end loop; + memAWrite(6 downto 0) <= opcode(6 downto 0); + else + memAAddr <= sp; + memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0); + memAWrite(6 downto 0) <= opcode(6 downto 0); + end if; + when Decoded_StoreSP => + memBWriteEnable <= '1'; + memBAddr <= sp+spOffset; + memBWrite <= memARead; + sp <= sp + 1; + state <= State_Resync; + when Decoded_LoadSP => + sp <= sp - 1; + memAAddr <= sp+spOffset; + when Decoded_Emulate => + sp <= sp - 1; + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto 0) <= pc + 1; + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= (others => '0'); + pc(9 downto 5) <= opcode(4 downto 0); + when Decoded_AddSP => + memAAddr <= sp; + memBAddr <= sp+spOffset; + state <= State_AddSP; + when Decoded_Break => + report "Break instruction encountered" severity failure; + break <= '1'; + when Decoded_PushSP => + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + sp <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto minAddrBit) <= sp; + when Decoded_PopPC => + pc <= memARead(maxAddrBit downto 0); + sp <= sp + 1; + state <= State_Resync; + when Decoded_Add => + sp <= sp + 1; + state <= State_Add; + when Decoded_Or => + sp <= sp + 1; + state <= State_Or; + when Decoded_And => + sp <= sp + 1; + state <= State_And; + when Decoded_Load => + if (memARead(ioBit)='1') then + out_mem_addr <= memARead(maxAddrBitIncIO downto 0); + out_mem_readEnable <= '1'; + state <= State_ReadIO; + else + memAAddr <= memARead(maxAddrBit downto minAddrBit); + end if; + when Decoded_Not => + memAAddr <= sp(maxAddrBit downto minAddrBit); + memAWriteEnable <= '1'; + memAWrite <= not memARead; + when Decoded_Flip => + memAAddr <= sp(maxAddrBit downto minAddrBit); + memAWriteEnable <= '1'; + for i in 0 to wordSize-1 loop + memAWrite(i) <= memARead(wordSize-1-i); + end loop; + when Decoded_Store => + memBAddr <= sp + 1; + sp <= sp + 1; + if (memARead(ioBit)='1') then + state <= State_WriteIO; + else + state <= State_Store; + end if; + when Decoded_PopSP => + sp <= memARead(maxAddrBit downto minAddrBit); + state <= State_Resync; + when Decoded_Nop => + memAAddr <= sp; + when others => + null; + end case; + when State_ReadIO => + if (in_mem_busy = '0') then + state <= State_Fetch; + memAWriteEnable <= '1'; + memAWrite <= mem_read; + end if; + when State_WriteIO => + sp <= sp + 1; + out_mem_writeEnable <= '1'; + out_mem_addr <= memARead(maxAddrBitIncIO downto 0); + mem_write <= memBRead; + state <= State_WriteIODone; + when State_WriteIODone => + if (in_mem_busy = '0') then + state <= State_Resync; + end if; + when State_Fetch => + -- We need to resync. During the *next* cycle + -- we'll fetch the opcode @ pc and thus it will + -- be available for State_Execute the cycle after + -- next + memBAddr <= pc(maxAddrBit downto minAddrBit); + state <= State_FetchNext; + when State_FetchNext => + -- at this point memARead contains the value that is either + -- from the top of stack or should be copied to the top of the stack + memAWriteEnable <= '1'; + memAWrite <= memARead; + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Decode; + when State_Decode => + -- during the State_Execute cycle we'll be fetching SP+1 + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Execute; + when State_Store => + sp <= sp + 1; + memAWriteEnable <= '1'; + memAAddr <= memARead(maxAddrBit downto minAddrBit); + memAWrite <= memBRead; + state <= State_Resync; + when State_AddSP => + state <= State_Add; + when State_Add => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead + memBRead; + state <= State_Fetch; + when State_Or => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead or memBRead; + state <= State_Fetch; + when State_Resync => + memAAddr <= sp; + state <= State_Fetch; + when State_And => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead and memBRead; + state <= State_Fetch; + when others => + null; + end case; + + end if; + end process; + + + +end behave; diff --git a/zpu/hdl/zpu4/src/zpuio.vhd b/zpu/hdl/zpu4/src/zpuio.vhd new file mode 100644 index 0000000..d14629e --- /dev/null +++ b/zpu/hdl/zpu4/src/zpuio.vhd @@ -0,0 +1,256 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity zpuio is + port ( areset : in std_logic; + cpu_clk : in std_logic; + clk_status : in std_logic_vector(2 downto 0); + cpu_din : in std_logic_vector(15 downto 0); + cpu_a : in std_logic_vector(20 downto 0); + cpu_we : in std_logic_vector(1 downto 0); + cpu_re : in std_logic; + cpu_dout : inout std_logic_vector(15 downto 0)); +end zpuio; + +architecture behave of zpuio is + +signal timer_read : std_logic_vector(7 downto 0); +--signal timer_write : std_logic_vector(7 downto 0); +signal timer_we : std_logic; + + +signal io_busy : std_logic; +signal io_read : std_logic_vector(7 downto 0); +--signal io_write : std_logic_vector(7 downto 0); +signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit); +signal io_writeEnable : std_logic; +signal Enable : std_logic; + +signal din : std_logic_vector(7 downto 0); +signal dout : std_logic_vector(7 downto 0); +signal adr : std_logic_vector(15 downto 0); +signal break : std_logic; +signal we : std_logic; +signal re : std_logic; + + +-- uart forwarding... + +signal uartTXPending : std_logic; +signal uartTXCleared : std_logic; +signal uartData : std_logic_vector(7 downto 0); + +signal readingTimer : std_logic; + + + + +signal mem_busy : std_logic; +signal mem_read : std_logic_vector(wordSize-1 downto 0); +signal mem_write : std_logic_vector(wordSize-1 downto 0); +signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); +signal mem_writeEnable : std_logic; +signal mem_readEnable : std_logic; +signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + +signal dram_mem_busy : std_logic; +signal dram_mem_read : std_logic_vector(wordSize-1 downto 0); +signal dram_mem_write : std_logic_vector(wordSize-1 downto 0); +signal dram_mem_writeEnable : std_logic; +signal dram_mem_readEnable : std_logic; +signal dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + + + +--signal io_mem_read : std_logic_vector(7 downto 0); +--signal io_mem_writeEnable : std_logic; +--signal io_mem_readEnable : std_logic; +signal io_readEnable : std_logic; + + +signal dram_read : std_logic; + + + +begin + + io_addr <= mem_addr(maxAddrBit downto minAddrBit); + + timerinst: timer port map ( + clk => cpu_clk, + areset => areset, + we => timer_we, + din => mem_write(7 downto 0), + adr => io_addr(4 downto 2), + dout => timer_read); + + zpu: zpu_core port map ( + clk => cpu_clk , + areset => areset, + in_mem_busy => mem_busy, + mem_read => mem_read, + mem_write => mem_write, + out_mem_addr => mem_addr, + out_mem_writeEnable => mem_writeEnable, + out_mem_readEnable => mem_readEnable, + mem_writeMask => mem_writeMask, + interrupt => '0', + break => break); + + +ram_imp: dram port map ( + clk => cpu_clk , + areset => areset, + mem_busy => dram_mem_busy, + mem_read => dram_mem_read, + mem_write => mem_write, + mem_addr => mem_addr(maxAddrBit downto 0), + mem_writeEnable => dram_mem_writeEnable, + mem_readEnable => dram_mem_readEnable, + mem_writeMask => mem_writeMask); + + + -- Read/write are on different addresses + -- The registers are 8 bits and mapped to bit[7:0] + -- + -- 0xC000 Write: Writes to UART TX FIFO (4 byte FIFO) + -- Read : Reads from UART RX FIFO (4 byte FIFO) + -- 0xC004 Read : UART status register + -- Bit 0 = RX FIFO empty + -- Bit 1 = TX FIFO full + -- 0xA000 Skrive: LED's (8 stk.) + + -- 0x9000 Write: bit 0: 1= reset counter + -- 0= counter running + -- bit 1: 1= sample counter (when set to 1) + -- 0=not used + -- Read : counter bit[7:0] + -- 0x9004 Read: counter bit [15:8] + -- 0x9008 Read: counter bit [23:16] + -- 0x900C Read: counter bit [31:24] + -- 0x9010 Read: counter bit [39:32] + -- 0x9014 Read: counter bit [47:40] + -- 0x9018 Read: counter bit [55:48] + -- 0x901C Read: counter bit [63:56] + -- + -- 0x8800 Read: unsigned 8-bit integer with FPGA frequency (in MHz) + + fauxUart: + process(cpu_clk, areset) + begin + if areset = '1' then + io_busy <= '0'; + uartTXPending <= '0'; + timer_we <= '0'; + io_busy <= '0'; + uartData <= x"58"; -- 'X' + readingTimer <= '0'; + elsif (cpu_clk'event and cpu_clk = '1') then + timer_we <= '0'; + io_busy <= '0'; + if uartTXCleared = '1' then + uartTXPending <= '0'; + end if; + + if io_writeEnable = '1' then + if io_addr=x"1000" then + -- Write to UART + uartData <= mem_write(7 downto 0); + uartTXPending <= '1'; + io_busy <= '1'; + elsif io_addr(12)='1' then + timer_we <= '1'; + io_busy <= '1'; + else + report "Illegal IO write" severity failure; + end if; + end if; + if (io_readEnable = '1') then + if io_addr=x"1001" then + io_read <= (0=>'1', -- recieve empty + 1 => uartTXPending, -- tx full + others => '0'); + io_busy <= '1'; + elsif io_addr(12)='1' then + readingTimer <= '1'; + io_busy <= '1'; + elsif io_addr(11)='1' then + io_read <= ZPU_Frequency; + io_busy <= '1'; + else + report "Illegal IO read" severity failure; + end if; + + else + if (readingTimer = '1') then + readingTimer <= '0'; + io_read <= timer_read; + io_busy <= '0'; + else + io_read <= (others => '1'); + end if; + end if; + end if; + end process; + + + forwardUARTOutputToARM: + process(cpu_clk, areset) + begin + if areset = '1' then + uartTXCleared <= '0'; + elsif (cpu_clk = '1' and cpu_clk'event) then + if cpu_we(0) = '1' and cpu_a(3 downto 1) = "000" then + uartTXCleared <= cpu_din(0); + else + uartTXCleared <= uartTXCleared; + end if; + end if; + end process; + + cpu_dout(7 downto 0) <= uartData when (cpu_re = '1' and cpu_a(3 downto 1) = "001") else (others => 'Z'); + cpu_dout <= (0 => uartTXPending, others => '0') when (cpu_re = '1' and cpu_a(3 downto 1) = "000") else (others => 'Z'); + + dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit); + dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit); + io_writeEnable <= mem_writeEnable and mem_addr(ioBit); +-- io_readEnable <= mem_readEnable and mem_addr(ioBit); + mem_busy <= io_busy or dram_mem_busy or dram_read or io_readEnable; + + -- Memory reads either come from IO or DRAM. We need to pick the right one. + memorycontrol: + process(cpu_clk, areset) + begin + if areset = '1' then + dram_read <= '0'; + io_readEnable <= '0'; + + + elsif (cpu_clk'event and cpu_clk = '1') then + mem_read <= (others => '0'); + if mem_addr(ioBit)='0' and mem_readEnable='1' then + dram_read <= '1'; + end if; + if dram_read='1' and dram_mem_busy='0' then + dram_read <= '0'; + mem_read <= dram_mem_read; + end if; + + if mem_addr(ioBit)='1' and mem_readEnable='1' then + io_readEnable <= '1'; + end if; + if io_readEnable='1' and io_busy='0' then + io_readEnable <= '0'; + mem_read(7 downto 0) <= io_read; + end if; + + end if; + end process; + + +end behave; diff --git a/zpu/hdl/zpu4/src/zpuio_bram.vhd b/zpu/hdl/zpu4/src/zpuio_bram.vhd new file mode 100644 index 0000000..5d3f409 --- /dev/null +++ b/zpu/hdl/zpu4/src/zpuio_bram.vhd @@ -0,0 +1,229 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity zpuio is + port ( areset : in std_logic; + cpu_clk : in std_logic; + clk_status : in std_logic_vector(2 downto 0); + cpu_din : in std_logic_vector(15 downto 0); + cpu_a : in std_logic_vector(20 downto 0); + cpu_we : in std_logic_vector(1 downto 0); + cpu_re : in std_logic; + cpu_dout : inout std_logic_vector(15 downto 0)); +end zpuio; + +architecture behave of zpuio is + +signal timer_read : std_logic_vector(7 downto 0); +--signal timer_write : std_logic_vector(7 downto 0); +signal timer_we : std_logic; + + +signal io_busy : std_logic; +signal io_read : std_logic_vector(7 downto 0); +--signal io_write : std_logic_vector(7 downto 0); +signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit); +signal io_writeEnable : std_logic; +signal Enable : std_logic; + +signal din : std_logic_vector(7 downto 0); +signal dout : std_logic_vector(7 downto 0); +signal adr : std_logic_vector(15 downto 0); +signal break : std_logic; +signal we : std_logic; +signal re : std_logic; + + +-- uart forwarding... + +signal uartTXPending : std_logic; +signal uartTXCleared : std_logic; +signal uartData : std_logic_vector(7 downto 0); + +signal readingTimer : std_logic; + + + + +signal mem_busy : std_logic; +signal mem_read : std_logic_vector(wordSize-1 downto 0); +signal mem_write : std_logic_vector(wordSize-1 downto 0); +signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); +signal mem_writeEnable : std_logic; +signal mem_readEnable : std_logic; +signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + + + + +--signal io_mem_read : std_logic_vector(7 downto 0); +--signal io_mem_writeEnable : std_logic; +--signal io_mem_readEnable : std_logic; +signal io_readEnable : std_logic; + + + + + +begin + + io_addr <= mem_addr(maxAddrBit downto minAddrBit); + + timerinst: timer port map ( + clk => cpu_clk, + areset => areset, + we => timer_we, + din => mem_write(7 downto 0), + adr => io_addr(4 downto 2), + dout => timer_read); + + zpu: zpu_core port map ( + clk => cpu_clk , + areset => areset, + in_mem_busy => mem_busy, + mem_read => mem_read, + mem_write => mem_write, + out_mem_addr => mem_addr, + out_mem_writeEnable => mem_writeEnable, + out_mem_readEnable => mem_readEnable, + mem_writeMask => mem_writeMask, + interrupt => '0', + break => break); + + + + + -- Read/write are on different addresses + -- The registers are 8 bits and mapped to bit[7:0] + -- + -- 0xC000 Write: Writes to UART TX FIFO (4 byte FIFO) + -- Read : Reads from UART RX FIFO (4 byte FIFO) + -- 0xC004 Read : UART status register + -- Bit 0 = RX FIFO empty + -- Bit 1 = TX FIFO full + -- 0xA000 Skrive: LED's (8 stk.) + + -- 0x9000 Write: bit 0: 1= reset counter + -- 0= counter running + -- bit 1: 1= sample counter (when set to 1) + -- 0=not used + -- Read : counter bit[7:0] + -- 0x9004 Read: counter bit [15:8] + -- 0x9008 Read: counter bit [23:16] + -- 0x900C Read: counter bit [31:24] + -- 0x9010 Read: counter bit [39:32] + -- 0x9014 Read: counter bit [47:40] + -- 0x9018 Read: counter bit [55:48] + -- 0x901C Read: counter bit [63:56] + -- + -- 0x8800 Read: unsigned 8-bit integer with FPGA frequency (in MHz) + + fauxUart: + process(cpu_clk, areset) + begin + if areset = '1' then + io_busy <= '0'; + uartTXPending <= '0'; + timer_we <= '0'; + io_busy <= '0'; + uartData <= x"58"; -- 'X' + readingTimer <= '0'; + elsif (cpu_clk'event and cpu_clk = '1') then + timer_we <= '0'; + io_busy <= '0'; + if uartTXCleared = '1' then + uartTXPending <= '0'; + end if; + + if io_writeEnable = '1' then + if io_addr=x"1000" then + -- Write to UART + uartData <= mem_write(7 downto 0); + uartTXPending <= '1'; + io_busy <= '1'; + elsif io_addr(12)='1' then + timer_we <= '1'; + io_busy <= '1'; + else + report "Illegal IO write" severity failure; + end if; + end if; + if (io_readEnable = '1') then + if io_addr=x"1001" then + io_read <= (0=>'1', -- recieve empty + 1 => uartTXPending, -- tx full + others => '0'); + io_busy <= '1'; + elsif io_addr(12)='1' then + readingTimer <= '1'; + io_busy <= '1'; + elsif io_addr(11)='1' then + io_read <= ZPU_Frequency; + io_busy <= '1'; + else + report "Illegal IO read" severity failure; + end if; + + else + if (readingTimer = '1') then + readingTimer <= '0'; + io_read <= timer_read; + io_busy <= '0'; + else + io_read <= (others => '1'); + end if; + end if; + end if; + end process; + + + forwardUARTOutputToARM: + process(cpu_clk, areset) + begin + if areset = '1' then + uartTXCleared <= '0'; + elsif (cpu_clk = '1' and cpu_clk'event) then + if cpu_we(0) = '1' and cpu_a(3 downto 1) = "000" then + uartTXCleared <= cpu_din(0); + else + uartTXCleared <= uartTXCleared; + end if; + end if; + end process; + + cpu_dout(7 downto 0) <= uartData when (cpu_re = '1' and cpu_a(3 downto 1) = "001") else (others => 'Z'); + cpu_dout <= (0 => uartTXPending, others => '0') when (cpu_re = '1' and cpu_a(3 downto 1) = "000") else (others => 'Z'); + + io_writeEnable <= mem_writeEnable and mem_addr(ioBit); +-- io_readEnable <= mem_readEnable and mem_addr(ioBit); + mem_busy <= io_busy or io_readEnable; + + -- Memory reads either come from IO or DRAM. We need to pick the right one. + memorycontrol: + process(cpu_clk, areset) + begin + if areset = '1' then + io_readEnable <= '0'; + + + elsif (cpu_clk'event and cpu_clk = '1') then + mem_read <= (others => '0'); + + if mem_addr(ioBit)='1' and mem_readEnable='1' then + io_readEnable <= '1'; + end if; + if io_readEnable='1' and io_busy='0' then + io_readEnable <= '0'; + mem_read(7 downto 0) <= io_read; + end if; + + end if; + end process; + + +end behave; diff --git a/zpu/hdl/zpu4/src/zpupkg.vhd b/zpu/hdl/zpu4/src/zpupkg.vhd new file mode 100644 index 0000000..30c3e46 --- /dev/null +++ b/zpu/hdl/zpu4/src/zpupkg.vhd @@ -0,0 +1,168 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; + +library work; +use work.zpu_config.all; + +package zpupkg is + + -- This bit is set for read/writes to IO + -- FIX!!! eventually this should be set to wordSize-1 so as to + -- to make the address of IO independent of amount of memory + -- reserved for CPU. Requires trivial tweaks in toolchain/runtime + -- libraries. + + constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes + constant maxAddrBit : integer := maxAddrBitIncIO-1; + constant ioBit : integer := maxAddrBit+1; + constant wordSize : integer := 2**wordPower; + constant wordBytes : integer := wordSize/8; + constant minAddrBit : integer := byteBits; + -- configurable internal stack size. Probably going to be 16 after toolchain is done + constant stack_bits : integer := 5; + constant stack_size : integer := 2**stack_bits; + + component dualport_ram is + port (clk : in std_logic; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memAWrite : in std_logic_vector(wordSize-1 downto 0); + memARead : out std_logic_vector(wordSize-1 downto 0); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memBWrite : in std_logic_vector(wordSize-1 downto 0); + memBRead : out std_logic_vector(wordSize-1 downto 0)); + end component; + + component dram is + port (clk : in std_logic; + areset : in std_logic; + mem_writeEnable : in std_logic; + mem_readEnable : in std_logic; + mem_addr : in std_logic_vector(maxAddrBit downto 0); + mem_write : in std_logic_vector(wordSize-1 downto 0); + mem_read : out std_logic_vector(wordSize-1 downto 0); + mem_busy : out std_logic; + mem_writeMask : in std_logic_vector(wordBytes-1 downto 0)); + end component; + + + component trace is + port( + clk : in std_logic; + begin_inst : in std_logic; + pc : in std_logic_vector(maxAddrBitIncIO downto 0); + opcode : in std_logic_vector(7 downto 0); + sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit); + memA : in std_logic_vector(wordSize-1 downto 0); + memB : in std_logic_vector(wordSize-1 downto 0); + busy : in std_logic; + intSp : in std_logic_vector(stack_bits-1 downto 0) + ); + end component; + + component zpu_core is + port ( clk : in std_logic; + areset : in std_logic; + enable : in std_logic; + in_mem_busy : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + out_mem_writeEnable : out std_logic; + out_mem_readEnable : out std_logic; + mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + interrupt : in std_logic; + break : out std_logic); + end component; + + + + component timer is + port( + clk : in std_logic; + areset : in std_logic; + we : in std_logic; + din : in std_logic_vector(7 downto 0); + adr : in std_logic_vector(2 downto 0); + dout : out std_logic_vector(7 downto 0)); + end component; + + component zpuio is + port ( areset : in std_logic; + cpu_clk : in std_logic; + clk_status : in std_logic_vector(2 downto 0); + cpu_din : in std_logic_vector(15 downto 0); + cpu_a : in std_logic_vector(20 downto 0); + cpu_we : in std_logic_vector(1 downto 0); + cpu_re : in std_logic; + cpu_dout : inout std_logic_vector(15 downto 0)); + end component; + + + + + -- opcode decode constants + constant OpCode_Im : std_logic_vector(7 downto 7) := "1"; + constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010"; + constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011"; + constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001"; + constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001"; + constant OpCode_Short : std_logic_vector(7 downto 4) := "0000"; + + constant OpCode_Break : std_logic_vector(3 downto 0) := "0000"; + constant OpCode_Shiftleft: std_logic_vector(3 downto 0) := "0001"; + constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010"; + constant OpCode_PushInt : std_logic_vector(3 downto 0) := "0011"; + + constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100"; + constant OpCode_Add : std_logic_vector(3 downto 0) := "0101"; + constant OpCode_And : std_logic_vector(3 downto 0) := "0110"; + constant OpCode_Or : std_logic_vector(3 downto 0) := "0111"; + + constant OpCode_Load : std_logic_vector(3 downto 0) := "1000"; + constant OpCode_Not : std_logic_vector(3 downto 0) := "1001"; + constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010"; + constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011"; + + constant OpCode_Store : std_logic_vector(3 downto 0) := "1100"; + constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101"; + constant OpCode_Compare : std_logic_vector(3 downto 0) := "1110"; + constant OpCode_PopInt : std_logic_vector(3 downto 0) := "1111"; + + constant OpCode_Lessthan : std_logic_vector(5 downto 0) := conv_std_logic_vector(36, 6); + constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := conv_std_logic_vector(37, 6); + constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := conv_std_logic_vector(38, 6); + constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := conv_std_logic_vector(39, 6); + + constant OpCode_Swap : std_logic_vector(5 downto 0) := conv_std_logic_vector(40, 6); + constant OpCode_Mult : std_logic_vector(5 downto 0) := conv_std_logic_vector(41, 6); + + constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := conv_std_logic_vector(42, 6); + constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := conv_std_logic_vector(43, 6); + constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := conv_std_logic_vector(44, 6); + constant OpCode_Call : std_logic_vector(5 downto 0) := conv_std_logic_vector(45, 6); + + constant OpCode_Eq : std_logic_vector(5 downto 0) := conv_std_logic_vector(46, 6); + constant OpCode_Neq : std_logic_vector(5 downto 0) := conv_std_logic_vector(47, 6); + + constant OpCode_Sub : std_logic_vector(5 downto 0) := conv_std_logic_vector(49, 6); + constant OpCode_Loadb : std_logic_vector(5 downto 0) := conv_std_logic_vector(51, 6); + constant OpCode_Storeb : std_logic_vector(5 downto 0) := conv_std_logic_vector(52, 6); + + constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := conv_std_logic_vector(55, 6); + constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := conv_std_logic_vector(56, 6); + constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := conv_std_logic_vector(57, 6); + + constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := conv_std_logic_vector(61, 6); + constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := conv_std_logic_vector(62, 6); + constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := conv_std_logic_vector(63, 6); + + + + constant OpCode_Size : integer := 8; + + + +end zpupkg; diff --git a/zpu/hdl/zpu4/test/dmips/build.sh b/zpu/hdl/zpu4/test/dmips/build.sh new file mode 100644 index 0000000..51ff3de --- /dev/null +++ b/zpu/hdl/zpu4/test/dmips/build.sh @@ -0,0 +1,3 @@ +zpu-elf-gcc -DTIME $ZPUDIR/dhrystone/dhry_*.c -O3 -Wl,--gc-sections -Wl,--relax -abel -o dmips.elf +zpu-elf-objdump --disassemble-all >dmips.dis dmips.elf +zpu-elf-objcopy -O binary dmips.elf dmips.bin diff --git a/zpu/hdl/zpu4/test/dmips/dmips.bin b/zpu/hdl/zpu4/test/dmips/dmips.bin new file mode 100644 index 0000000..1330fe3 Binary files /dev/null and b/zpu/hdl/zpu4/test/dmips/dmips.bin differ diff --git a/zpu/hdl/zpu4/test/dmips/dmips.elf b/zpu/hdl/zpu4/test/dmips/dmips.elf new file mode 100644 index 0000000..7254a5d Binary files /dev/null and b/zpu/hdl/zpu4/test/dmips/dmips.elf differ diff --git a/zpu/hdl/zpu4/test/dmips/dmips.ram b/zpu/hdl/zpu4/test/dmips/dmips.ram new file mode 100644 index 0000000..27b991d --- /dev/null +++ b/zpu/hdl/zpu4/test/dmips/dmips.ram @@ -0,0 +1,3507 @@ +0 => x"0b0b0b0b", +1 => x"80700b0b", +2 => x"80dde00c", +3 => x"3a0b0b0b", +4 => x"b9990400", +5 => x"00000000", +6 => x"00000000", +7 => x"00000000", +8 => x"80088408", +9 => x"88080b0b", +10 => x"0bb9e02d", +11 => x"880c840c", +12 => x"800c0400", +13 => x"00000000", +14 => x"00000000", +15 => x"00000000", +16 => x"71fd0608", +17 => x"72830609", +18 => x"81058205", +19 => x"832b2a83", +20 => x"ffff0652", +21 => x"04000000", +22 => x"00000000", +23 => x"00000000", +24 => x"71fd0608", +25 => x"83ffff73", +26 => x"83060981", +27 => x"05820583", +28 => x"2b2b0906", +29 => x"7383ffff", +30 => x"0b0b0b0b", +31 => x"83a70400", +32 => x"72098105", +33 => x"72057373", +34 => x"09060906", +35 => x"73097306", +36 => x"070a8106", +37 => x"53510400", +38 => x"00000000", +39 => x"00000000", +40 => x"72722473", +41 => x"732e0753", +42 => x"51040000", +43 => x"00000000", +44 => x"00000000", +45 => x"00000000", +46 => x"00000000", +47 => x"00000000", +48 => x"71737109", +49 => x"71068106", +50 => x"30720a10", +51 => x"0a720a10", +52 => x"0a31050a", +53 => x"81065151", +54 => x"53510400", +55 => x"00000000", +56 => x"72722673", +57 => x"732e0753", +58 => x"51040000", +59 => x"00000000", +60 => x"00000000", +61 => x"00000000", +62 => x"00000000", +63 => x"00000000", +64 => x"00000000", +65 => x"00000000", +66 => x"00000000", +67 => x"00000000", +68 => x"00000000", +69 => x"00000000", +70 => x"00000000", +71 => x"00000000", +72 => x"0b0b0b88", +73 => x"c4040000", +74 => x"00000000", +75 => x"00000000", +76 => x"00000000", +77 => x"00000000", +78 => x"00000000", +79 => x"00000000", +80 => x"720a722b", +81 => x"0a535104", +82 => x"00000000", +83 => x"00000000", +84 => x"00000000", +85 => x"00000000", +86 => x"00000000", +87 => x"00000000", +88 => x"72729f06", +89 => x"0981050b", +90 => x"0b0b88a7", +91 => x"05040000", +92 => x"00000000", +93 => x"00000000", +94 => x"00000000", +95 => x"00000000", +96 => x"72722aff", +97 => x"739f062a", +98 => x"0974090a", +99 => x"8106ff05", +100 => x"06075351", +101 => x"04000000", +102 => x"00000000", +103 => x"00000000", +104 => x"71715351", +105 => x"020d0406", +106 => x"73830609", +107 => x"81058205", +108 => x"832b0b2b", +109 => x"0772fc06", +110 => x"0c515104", +111 => x"00000000", +112 => x"72098105", +113 => x"72050970", +114 => x"81050906", +115 => x"0a810653", +116 => x"51040000", +117 => x"00000000", +118 => x"00000000", +119 => x"00000000", +120 => x"72098105", +121 => x"72050970", +122 => x"81050906", +123 => x"0a098106", +124 => x"53510400", +125 => x"00000000", +126 => x"00000000", +127 => x"00000000", +128 => x"71098105", +129 => x"52040000", +130 => x"00000000", +131 => x"00000000", +132 => x"00000000", +133 => x"00000000", +134 => x"00000000", +135 => x"00000000", +136 => x"72720981", +137 => x"05055351", +138 => x"04000000", +139 => x"00000000", +140 => x"00000000", +141 => x"00000000", +142 => x"00000000", +143 => x"00000000", +144 => x"72097206", +145 => x"73730906", +146 => x"07535104", +147 => x"00000000", +148 => x"00000000", +149 => x"00000000", +150 => x"00000000", +151 => x"00000000", +152 => x"71fc0608", +153 => x"72830609", +154 => x"81058305", +155 => x"1010102a", +156 => x"81ff0652", +157 => x"04000000", +158 => x"00000000", +159 => x"00000000", +160 => x"71fc0608", +161 => x"0b0b80dd", +162 => x"cc738306", +163 => x"10100508", +164 => x"060b0b0b", +165 => x"88aa0400", +166 => x"00000000", +167 => x"00000000", +168 => x"80088408", +169 => x"88087575", +170 => x"0b0b0ba1", +171 => x"c92d5050", +172 => x"80085688", +173 => x"0c840c80", +174 => x"0c510400", +175 => x"00000000", +176 => x"80088408", +177 => x"88087575", +178 => x"0b0b0ba2", +179 => x"8d2d5050", +180 => x"80085688", +181 => x"0c840c80", +182 => x"0c510400", +183 => x"00000000", +184 => x"72097081", +185 => x"0509060a", +186 => x"8106ff05", +187 => x"70547106", +188 => x"73097274", +189 => x"05ff0506", +190 => x"07515151", +191 => x"04000000", +192 => x"72097081", +193 => x"0509060a", +194 => x"098106ff", +195 => x"05705471", +196 => x"06730972", +197 => x"7405ff05", +198 => x"06075151", +199 => x"51040000", +200 => x"05ff0504", +201 => x"00000000", +202 => x"00000000", +203 => x"00000000", +204 => x"00000000", +205 => x"00000000", +206 => x"00000000", +207 => x"00000000", +208 => x"810b0b0b", +209 => x"80dddc0c", +210 => x"51040000", +211 => x"00000000", +212 => x"00000000", +213 => x"00000000", +214 => x"00000000", +215 => x"00000000", +216 => x"71810552", +217 => x"04000000", +218 => x"00000000", +219 => x"00000000", +220 => x"00000000", +221 => x"00000000", +222 => x"00000000", +223 => x"00000000", +224 => x"00000000", +225 => x"00000000", +226 => x"00000000", +227 => x"00000000", +228 => x"00000000", +229 => x"00000000", +230 => x"00000000", +231 => x"00000000", +232 => x"02840572", +233 => x"10100552", +234 => x"04000000", +235 => x"00000000", +236 => x"00000000", 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x"00000000", +3473 => x"00000000", +3474 => x"00000000", +3475 => x"00000000", +3476 => x"00000000", +3477 => x"00000000", +3478 => x"00000000", +3479 => x"00000000", +3480 => x"00000000", +3481 => x"00000000", +3482 => x"00000000", +3483 => x"00000000", +3484 => x"00000000", +3485 => x"00000000", +3486 => x"00000000", +3487 => x"00000000", +3488 => x"00000000", +3489 => x"00000000", +3490 => x"00000000", +3491 => x"00000000", +3492 => x"00000000", +3493 => x"00000000", +3494 => x"00000000", +3495 => x"00000000", +3496 => x"00000000", +3497 => x"00000000", +3498 => x"00000000", +3499 => x"00000000", +3500 => x"00000000", +3501 => x"00000000", +3502 => x"00002dc0", +3503 => x"ffffffff", +3504 => x"00000000", +3505 => x"ffffffff", +3506 => x"00000000", diff --git a/zpu/hdl/zpu4/test/hello/build.sh b/zpu/hdl/zpu4/test/hello/build.sh new file mode 100644 index 0000000..0d81138 --- /dev/null +++ b/zpu/hdl/zpu4/test/hello/build.sh @@ -0,0 +1,3 @@ +zpu-elf-gcc -O3 -abel `pwd`/hello.c -o hello.elf -Wl,--relax -Wl,--gc-sections -g +zpu-elf-objdump --disassemble-all >hello.dis hello.elf +zpu-elf-objcopy -O binary hello.elf hello.bin diff --git a/zpu/hdl/zpu4/test/hello/hello.bin b/zpu/hdl/zpu4/test/hello/hello.bin new file mode 100644 index 0000000..fe17308 Binary files /dev/null and b/zpu/hdl/zpu4/test/hello/hello.bin differ diff --git a/zpu/hdl/zpu4/test/hello/hello.c b/zpu/hdl/zpu4/test/hello/hello.c new file mode 100644 index 0000000..ea3dbb8 --- /dev/null +++ b/zpu/hdl/zpu4/test/hello/hello.c @@ -0,0 +1,51 @@ +/* + +zpu-elf-gcc -abel `pwd`/hello.c -o hello.elf -Wl,--relax -Wl,--gc-sections -g +zpu-elf-objdump --disassemble-all >hello.dis hello.elf +zpu-elf-objcopy -O binary hello.elf hello.bin + + * */ +#include + +int j; +int k; + +int main(int argc, char **argv) +{ + int i; + for (i=0; i< 10; i++) + { + puts("Hello world 1\n"); + puts("Hello world 2\n"); + j=-4; + if ((j>>1)!=-2) + { + abort(); + } + + k=10; + if (k*j!=-40) + { + abort(); + } + + j=10; + k=10000000; + if (k*j!=100000000) + { + abort(); + } + + j=0x80000000; + k=0xffffffff; + if (j>k) + { + abort(); + } + } + if (i!=10) + { + abort(); + } + +} diff --git a/zpu/hdl/zpu4/test/hello/hello.elf b/zpu/hdl/zpu4/test/hello/hello.elf new file mode 100644 index 0000000..999b9a3 Binary files /dev/null and b/zpu/hdl/zpu4/test/hello/hello.elf differ diff --git a/zpu/hdl/zpu4/test/hello/hello.ram b/zpu/hdl/zpu4/test/hello/hello.ram new file mode 100644 index 0000000..f310151 --- /dev/null +++ b/zpu/hdl/zpu4/test/hello/hello.ram @@ -0,0 +1,3165 @@ +0 => x"0b0b0b0b", +1 => x"80700b0b", +2 => x"80d3900c", +3 => x"3a0b0b80", +4 => x"c8b20400", +5 => x"00000000", +6 => x"00000000", +7 => x"00000000", +8 => x"80088408", +9 => x"88080b0b", +10 => x"80c8fb2d", +11 => x"880c840c", +12 => x"800c0400", +13 => x"00000000", +14 => x"00000000", +15 => x"00000000", +16 => x"71fd0608", +17 => x"72830609", +18 => x"81058205", +19 => x"832b2a83", +20 => x"ffff0652", +21 => x"04000000", +22 => x"00000000", +23 => x"00000000", +24 => x"71fd0608", +25 => x"83ffff73", +26 => x"83060981", +27 => x"05820583", +28 => x"2b2b0906", +29 => x"7383ffff", +30 => x"0b0b0b0b", +31 => x"83a70400", +32 => x"72098105", +33 => x"72057373", +34 => x"09060906", +35 => x"73097306", +36 => x"070a8106", +37 => x"53510400", +38 => x"00000000", +39 => x"00000000", +40 => x"72722473", +41 => x"732e0753", +42 => x"51040000", +43 => x"00000000", +44 => x"00000000", +45 => x"00000000", +46 => x"00000000", +47 => x"00000000", +48 => x"71737109", +49 => x"71068106", +50 => x"30720a10", +51 => x"0a720a10", +52 => x"0a31050a", +53 => x"81065151", +54 => x"53510400", +55 => x"00000000", +56 => x"72722673", +57 => x"732e0753", +58 => x"51040000", +59 => x"00000000", +60 => x"00000000", +61 => x"00000000", +62 => x"00000000", +63 => x"00000000", +64 => x"00000000", +65 => x"00000000", +66 => x"00000000", +67 => x"00000000", +68 => x"00000000", +69 => x"00000000", +70 => x"00000000", +71 => x"00000000", +72 => x"0b0b0b88", +73 => x"c4040000", +74 => x"00000000", +75 => x"00000000", +76 => x"00000000", +77 => x"00000000", +78 => x"00000000", +79 => x"00000000", +80 => x"720a722b", +81 => x"0a535104", +82 => x"00000000", +83 => x"00000000", +84 => x"00000000", +85 => x"00000000", +86 => x"00000000", +87 => x"00000000", +88 => x"72729f06", +89 => x"0981050b", +90 => x"0b0b88a7", +91 => x"05040000", +92 => x"00000000", +93 => x"00000000", +94 => x"00000000", +95 => x"00000000", +96 => x"72722aff", +97 => x"739f062a", +98 => x"0974090a", +99 => x"8106ff05", +100 => x"06075351", +101 => x"04000000", +102 => x"00000000", +103 => x"00000000", +104 => x"71715351", +105 => x"020d0406", +106 => x"73830609", +107 => x"81058205", +108 => x"832b0b2b", +109 => x"0772fc06", +110 => x"0c515104", +111 => x"00000000", +112 => x"72098105", +113 => x"72050970", +114 => x"81050906", +115 => x"0a810653", +116 => x"51040000", +117 => x"00000000", +118 => x"00000000", +119 => x"00000000", +120 => x"72098105", +121 => x"72050970", +122 => x"81050906", +123 => x"0a098106", +124 => x"53510400", +125 => x"00000000", +126 => x"00000000", +127 => x"00000000", +128 => x"71098105", +129 => x"52040000", +130 => x"00000000", +131 => x"00000000", +132 => x"00000000", +133 => x"00000000", +134 => x"00000000", +135 => x"00000000", +136 => x"72720981", +137 => x"05055351", +138 => x"04000000", +139 => x"00000000", +140 => x"00000000", +141 => x"00000000", +142 => x"00000000", +143 => x"00000000", +144 => x"72097206", +145 => x"73730906", +146 => x"07535104", +147 => x"00000000", +148 => x"00000000", +149 => x"00000000", +150 => x"00000000", +151 => x"00000000", +152 => x"71fc0608", +153 => x"72830609", +154 => x"81058305", +155 => x"1010102a", +156 => x"81ff0652", +157 => x"04000000", +158 => x"00000000", +159 => x"00000000", +160 => x"71fc0608", +161 => x"0b0b80d2", +162 => x"fc738306", +163 => x"10100508", +164 => x"060b0b0b", +165 => x"88aa0400", +166 => x"00000000", +167 => x"00000000", +168 => x"80088408", +169 => x"88087575", +170 => x"0b0b0b8d", +171 => x"872d5050", +172 => x"80085688", +173 => x"0c840c80", +174 => x"0c510400", +175 => x"00000000", +176 => x"80088408", +177 => x"88087575", +178 => x"0b0b0b8d", +179 => x"cb2d5050", +180 => x"80085688", +181 => x"0c840c80", +182 => x"0c510400", +183 => x"00000000", +184 => x"72097081", +185 => x"0509060a", +186 => x"8106ff05", +187 => x"70547106", +188 => x"73097274", +189 => x"05ff0506", +190 => x"07515151", +191 => x"04000000", +192 => x"72097081", +193 => x"0509060a", +194 => x"098106ff", +195 => x"05705471", +196 => x"06730972", +197 => x"7405ff05", +198 => x"06075151", +199 => x"51040000", +200 => x"05ff0504", +201 => x"00000000", +202 => x"00000000", +203 => x"00000000", +204 => x"00000000", +205 => x"00000000", +206 => x"00000000", +207 => x"00000000", +208 => x"810b0b0b", +209 => x"80d38c0c", +210 => x"51040000", +211 => x"00000000", +212 => x"00000000", +213 => x"00000000", +214 => x"00000000", +215 => x"00000000", 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Getting started

+FPGA: check out zpu/hdl, read zpu/hdl/index.html +

+Software: check out zpu/sw, read zpu/sw/index.html +

+Docs: check out zpu/docs, this is what's available as of writing. Further documentation exists in the eCosBoard 1.1 product: http://www.zylin.com/ecosboard.htm +

Other directories

+You probably don't need or want to download other directories. +
    +
  • +gccsrc - the complete GCC toolchain source. Big! Almost certainly not something you need or want to download. This has been moved to /trunk/zpugccsrc to +avoid subversion choking. +
  • roadshow - various bits and bobs to demonstrate the ZPU that has not been sorted/reorganized yet. + +
+ + + diff --git a/zpu/roadshow/roadshow/build/makefirmware.sh b/zpu/roadshow/roadshow/build/makefirmware.sh new file mode 100644 index 0000000..b44559b --- /dev/null +++ b/zpu/roadshow/roadshow/build/makefirmware.sh @@ -0,0 +1,13 @@ +echo >$2 ZylinPhiFirmware + +if [ x"$3" = x ] ;then + echo "No ic300.bit embedded into .phi" +else + echo "Embed ic300.bit into .phi" + echo >>$2 "FPGA: `wc -c $3 | grep -o -e \[0-9\]*`" + cat >>$2 $1 +fi +echo "Writing application" +echo >>$2 "Application: `wc -c $1 | grep -o -e \[0-9\]*`" +cat >>$2 $1 +echo >>$2 Done \ No newline at end of file diff --git a/zpu/roadshow/roadshow/codesize/.cvsignore b/zpu/roadshow/roadshow/codesize/.cvsignore new file mode 100644 index 0000000..6559932 --- /dev/null +++ b/zpu/roadshow/roadshow/codesize/.cvsignore @@ -0,0 +1 @@ +smallstd.elf diff --git a/zpu/roadshow/roadshow/codesize/crt0_phi.S b/zpu/roadshow/roadshow/codesize/crt0_phi.S new file mode 100644 index 0000000..4d654e2 --- /dev/null +++ b/zpu/roadshow/roadshow/codesize/crt0_phi.S @@ -0,0 +1,178 @@ +/* Startup code for ZPU + Copyright (C) 2005 Free Software Foundation, Inc. + +This file is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +In addition to the permissions in the GNU General Public License, the +Free Software Foundation gives you unlimited permission to link the +compiled version of this file with other programs, and to distribute +those programs without any restriction coming from the use of this +file. (The General Public License restrictions do apply in other +respects; for example, they cover modification of the file, and +distribution when not linked into another program.) + +This file is distributed in the hope that it will be useful, but +WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + .file "crt0.S" + + + + +; .section ".fixed_vectors","ax" +; KLUDGE!!! we remove the executable bit to avoid relaxation + .section ".fixed_vectors","a" + +; DANGER!!!! +; we need to align these code sections to 32 bytes, which +; means we must not use any assembler instructions that are relaxed +; at linker time +; DANGER!!!! + + .macro fixedim value + im \value + .endm + + .macro jsr address + + im 0 ; save R0 + load + im 4 ; save R1 + load + im 8 ; save R2 + load + + fixedim \address + call + + im 8 + store ; restore R2 + im 4 + store ; restore R1 + im 0 + store ; restore R0 + .endm + + + .macro jmp address + fixedim \address + poppc + .endm + + + .macro fast_neg + not + im 1 + add + .endm + + .macro cimpl funcname + ; save R0 + im 0 + load + + ; save R1 + im 4 + load + + ; save R2 + im 8 + load + + loadsp 20 + loadsp 20 + + fixedim \funcname + call + + ; destroy arguments on stack + storesp 0 + storesp 0 + + im 0 + load + + ; poke the result into the right slot + storesp 24 + + ; restore R2 + im 8 + store + + ; restore R1 + im 4 + store + + ; restore r0 + im 0 + store + + + storesp 4 + poppc + .endm + + .macro mult1bit + ; create mask of lowest bit in A + loadsp 8 ; A + im 1 + and + im -1 + add + not + loadsp 8 ; B + and + add ; accumulate in C + + ; shift B left 1 bit + loadsp 4 ; B + addsp 0 + storesp 8 ; B + + ; shift A right 1 bit + loadsp 8 ; A + flip + addsp 0 + flip + storesp 12 ; A + .endm + + + +/* vectors */ + .balign 32,0 +# offset 0x0000 0000 + .globl _start +_start: + ; intSp must be 0 when we jump to _premain + + im ZPU_ID + loadsp 0 + im _cpu_config + store + config + jmp _premain + + + +/* instruction emulation code */ + + .data + + + .globl _hardware +_hardware: + .long 0 + .globl _cpu_config +_cpu_config: + .long 0 + diff --git a/zpu/roadshow/roadshow/codesize/hello.c b/zpu/roadshow/roadshow/codesize/hello.c new file mode 100644 index 0000000..176275c --- /dev/null +++ b/zpu/roadshow/roadshow/codesize/hello.c @@ -0,0 +1,9 @@ +/* Simple hello world */ +#include + + +int main(int argc, char **argv) +{ + puts("Hello world\n"); +} + diff --git a/zpu/roadshow/roadshow/codesize/index.html b/zpu/roadshow/roadshow/codesize/index.html new file mode 100644 index 0000000..3f61b4e --- /dev/null +++ b/zpu/roadshow/roadshow/codesize/index.html @@ -0,0 +1,58 @@ + + +

Compiling hello world program with the ZPU GCC toolchain

+The ZPU comes with a standard GCC toolchain and an instruction set simulator. This allows compiling, running & debugging simple test programs. The Simulator has +some very basic peripherals defined: counter, timer interrupt and a debug output port. +

Installation

+
    +
  1. Install Cygwin. http://www.cygwin.com +
  2. Start Cygwin bash +
  3. unzip zputoolchain.zip +
  4. Add install/bin from zputoolchain.zip to PATH.
    +export PATH=$PATH:/install/bin +
+

Hello world example

+The ZPU toolchain comes with newlib & libstdc++ support which means that many C/C++ programs can be compiled without modification. +

+ +zpu-elf-gcc -Os -zeta hello.c -o hello.elf -Wl,--relax -Wl,--gc-sections
+zpu-elf-size hello.elf
+ +

Optimizing for size

+The ZPU toolchain produces highly compact code. +
    +
  1. Since the ZPU GCC toolchain supports standard ANSI C, it is easy to stumble across +functionality that takes up a lot of space. E.g. the standard printf() function is a beast. Some compilers drop e.g. floating point support +from the printf() function and thus boast a "smaller" printf() when in fact they have a non-standard printf(). newlib has a standard printf() function +and an alternative iprintf() function that works only on integers. +
  2. The ZPU ships with default startup code that works across various configurations of the ZPU, so be warned that there is some overhead that will +not occurr in the final application(anywhere between 1-4kBytes). +
  3. Compilation and linker options matter. The ZPU benefits greatly from the "-Wl,--relax -Wl,--gc-sections" options which is not used by +all architectures(e.g. GCC ARM does not implement/need -Wl,--relax). +
+

Small code example

+ +zpu-elf-gcc -Os -abel smallstd.c -o smallstd.elf -Wl,--relax -Wl,--gc-sections
+zpu-elf-size small.elf
+
+$ zpu-elf-size small.elf
+ text data bss dec hex filename
+ 2845 952 36 3833 ef9 small.elf
+
+ + +

Even smaller code example

+If the ZPU implements the optional instructions, the RAM overhead can be reduced significantly. +

+ +zpu-elf-gcc -Os -abel crt0_phi.S small.c -o small.elf -Wl,--relax -Wl,--gc-sections -nostdlib
+zpu-elf-size small.elf
+
+$ zpu-elf-size small.elf
+ text data bss dec hex filename
+ 56 8 0 64 40 small.elf
+
+ + + + diff --git a/zpu/roadshow/roadshow/codesize/small.c b/zpu/roadshow/roadshow/codesize/small.c new file mode 100644 index 0000000..0317343 --- /dev/null +++ b/zpu/roadshow/roadshow/codesize/small.c @@ -0,0 +1,9 @@ +void _premain(void) +{ + volatile int *someRegister=(volatile int *)0; + volatile int *otherRegister=(volatile int *)4; + while (*someRegister!=0) + { + *otherRegister++; + } +} diff --git a/zpu/roadshow/roadshow/codesize/small.elf b/zpu/roadshow/roadshow/codesize/small.elf new file mode 100644 index 0000000..4193a53 Binary files /dev/null and b/zpu/roadshow/roadshow/codesize/small.elf differ diff --git a/zpu/roadshow/roadshow/codesize/smallstd.c b/zpu/roadshow/roadshow/codesize/smallstd.c new file mode 100644 index 0000000..5d4b87a --- /dev/null +++ b/zpu/roadshow/roadshow/codesize/smallstd.c @@ -0,0 +1,9 @@ +int main(int argc, char **argv) +{ + volatile int *someRegister=(volatile int *)0; + volatile int *otherRegister=(volatile int *)4; + while (*someRegister!=0) + { + *otherRegister++; + } +} diff --git a/zpu/roadshow/roadshow/dhrystone/.cvsignore b/zpu/roadshow/roadshow/dhrystone/.cvsignore new file mode 100644 index 0000000..3544c3f --- /dev/null +++ b/zpu/roadshow/roadshow/dhrystone/.cvsignore @@ -0,0 +1,2 @@ +dhrystone.elf +dhrystone_zpu.elf diff --git a/zpu/roadshow/roadshow/dhrystone/RATIONALE b/zpu/roadshow/roadshow/dhrystone/RATIONALE new file mode 100644 index 0000000..926e046 --- /dev/null +++ b/zpu/roadshow/roadshow/dhrystone/RATIONALE @@ -0,0 +1,361 @@ + + + Dhrystone Benchmark: Rationale for Version 2 and Measurement Rules + + [published in SIGPLAN Notices 23,8 (Aug. 1988), 49-62] + + + Reinhold P. Weicker + Siemens AG, E STE 35 + [now: Siemens AG, AUT E 51] + Postfach 3220 + D-8520 Erlangen + Germany (West) + + + + +1. Why a Version 2 of Dhrystone? + +The Dhrystone benchmark program [1] has become a popular benchmark for +CPU/compiler performance measurement, in particular in the area of +minicomputers, workstations, PC's and microprocesors. It apparently satisfies +a need for an easy-to-use integer benchmark; it gives a first performance +indication which is more meaningful than MIPS numbers which, in their literal +meaning (million instructions per second), cannot be used across different +instruction sets (e.g. RISC vs. CISC). With the increasing use of the +benchmark, it seems necessary to reconsider the benchmark and to check whether +it can still fulfill this function. Version 2 of Dhrystone is the result of +such a re-evaluation, it has been made for two reasons: + +o Dhrystone has been published in Ada [1], and Versions in Ada, Pascal and C + have been distributed by Reinhold Weicker via floppy disk. However, the + version that was used most often for benchmarking has been the version made + by Rick Richardson by another translation from the Ada version into the C + programming language, this has been the version distributed via the UNIX + network Usenet [2]. + + There is an obvious need for a common C version of Dhrystone, since C is at + present the most popular system programming language for the class of + systems (microcomputers, minicomputers, workstations) where Dhrystone is + used most. There should be, as far as possible, only one C version of + Dhrystone such that results can be compared without restrictions. In the + past, the C versions distributed by Rick Richardson (Version 1.1) and by + Reinhold Weicker had small (though not significant) differences. + + Together with the new C version, the Ada and Pascal versions have been + updated as well. + +o As far as it is possible without changes to the Dhrystone statistics, + optimizing compilers should be prevented from removing significant + statements. It has turned out in the past that optimizing compilers + suppressed code generation for too many statements (by "dead code removal" + or "dead variable elimination"). This has lead to the danger that + benchmarking results obtained by a naive application of Dhrystone - without + inspection of the code that was generated - could become meaningless. + +The overall policiy for version 2 has been that the distribution of +statements, operand types and operand locality described in [1] should remain +unchanged as much as possible. (Very few changes were necessary; their impact +should be negligible.) Also, the order of statements should remain unchanged. +Although I am aware of some critical remarks on the benchmark - I agree with +several of them - and know some suggestions for improvement, I didn't want to +change the benchmark into something different from what has become known as +"Dhrystone"; the confusion generated by such a change would probably outweight +the benefits. If I were to write a new benchmark program, I wouldn't give it +the name "Dhrystone" since this denotes the program published in [1]. +However, I do recognize the need for a larger number of representative +programs that can be used as benchmarks; users should always be encouraged to +use more than just one benchmark. + +The new versions (version 2.1 for C, Pascal and Ada) will be distributed as +widely as possible. (Version 2.1 differs from version 2.0 distributed via the +UNIX Network Usenet in March 1988 only in a few corrections for minor +deficiencies found by users of version 2.0.) Readers who want to use the +benchmark for their own measurements can obtain a copy in machine-readable +form on floppy disk (MS-DOS or XENIX format) from the author. + + +2. Overall Characteristics of Version 2 + +In general, version 2 follows - in the parts that are significant for +performance measurement, i.e. within the measurement loop - the published +(Ada) version and the C versions previously distributed. Where the versions +distributed by Rick Richardson [2] and Reinhold Weicker have been different, +it follows the version distributed by Reinhold Weicker. (However, the +differences have been so small that their impact on execution time in all +likelihood has been negligible.) The initialization and UNIX instrumentation +part - which had been omitted in [1] - follows mostly the ideas of Rick +Richardson [2]. However, any changes in the initialization part and in the +printing of the result have no impact on performance measurement since they +are outside the measaurement loop. As a concession to older compilers, names +have been made unique within the first 8 characters for the C version. + +The original publication of Dhrystone did not contain any statements for time +measurement since they are necessarily system-dependent. However, it turned +out that it is not enough just to inclose the main procedure of Dhrystone in a +loop and to measure the execution time. If the variables that are computed +are not used somehow, there is the danger that the compiler considers them as +"dead variables" and suppresses code generation for a part of the statements. +Therefore in version 2 all variables of "main" are printed at the end of the +program. This also permits some plausibility control for correct execution of +the benchmark. + +At several places in the benchmark, code has been added, but only in branches +that are not executed. The intention is that optimizing compilers should be +prevented from moving code out of the measurement loop, or from removing code +altogether. Statements that are executed have been changed in very few places +only. In these cases, only the role of some operands has been changed, and it +was made sure that the numbers defining the "Dhrystone distribution" +(distribution of statements, operand types and locality) still hold as much as +possible. Except for sophisticated optimizing compilers, execution times for +version 2.1 should be the same as for previous versions. + +Because of the self-imposed limitation that the order and distribution of the +executed statements should not be changed, there are still cases where +optimizing compilers may not generate code for some statements. To a certain +degree, this is unavoidable for small synthetic benchmarks. Users of the +benchmark are advised to check code listings whether code is generated for all +statements of Dhrystone. + +Contrary to the suggestion in the published paper and its realization in the +versions previously distributed, no attempt has been made to subtract the time +for the measurement loop overhead. (This calculation has proven difficult to +implement in a correct way, and its omission makes the program simpler.) +However, since the loop check is now part of the benchmark, this does have an +impact - though a very minor one - on the distribution statistics which have +been updated for this version. + + +3. Discussion of Individual Changes + +In this section, all changes are described that affect the measurement loop +and that are not just renamings of variables. All remarks refer to the C +version; the other language versions have been updated similarly. + +In addition to adding the measurement loop and the printout statements, +changes have been made at the following places: + +o In procedure "main", three statements have been added in the non-executed + "then" part of the statement + + if (Enum_Loc == Func_1 (Ch_Index, 'C')) + + they are + + strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 3'RD STRING"); + Int_2_Loc = Run_Index; + Int_Glob = Run_Index; + + The string assignment prevents movement of the preceding assignment to + Str_2_Loc (5'th statement of "main") out of the measurement loop (This + probably will not happen for the C version, but it did happen with another + language and compiler.) The assignment to Int_2_Loc prevents value + propagation for Int_2_Loc, and the assignment to Int_Glob makes the value of + Int_Glob possibly dependent from the value of Run_Index. + +o In the three arithmetic computations at the end of the measurement loop in + "main ", the role of some variables has been exchanged, to prevent the + division from just cancelling out the multiplication as it was in [1]. A + very smart compiler might have recognized this and suppressed code + generation for the division. + +o For Proc_2, no code has been changed, but the values of the actual parameter + have changed due to changes in "main". + +o In Proc_4, the second assignment has been changed from + + Bool_Loc = Bool_Loc | Bool_Glob; + + to + + Bool_Glob = Bool_Loc | Bool_Glob; + + It now assigns a value to a global variable instead of a local variable + (Bool_Loc); Bool_Loc would be a "dead variable" which is not used + afterwards. + +o In Func_1, the statement + + Ch_1_Glob = Ch_1_Loc; + + was added in the non-executed "else" part of the "if" statement, to prevent + the suppression of code generation for the assignment to Ch_1_Loc. + +o In Func_2, the second character comparison statement has been changed to + + if (Ch_Loc == 'R') + + ('R' instead of 'X') because a comparison with 'X' is implied in the + preceding "if" statement. + + Also in Func_2, the statement + + Int_Glob = Int_Loc; + + has been added in the non-executed part of the last "if" statement, in order + to prevent Int_Loc from becoming a dead variable. + +o In Func_3, a non-executed "else" part has been added to the "if" statement. + While the program would not be incorrect without this "else" part, it is + considered bad programming practice if a function can be left without a + return value. + + To compensate for this change, the (non-executed) "else" part in the "if" + statement of Proc_3 was removed. + +The distribution statistics have been changed only by the addition of the +measurement loop iteration (1 additional statement, 4 additional local integer +operands) and by the change in Proc_4 (one operand changed from local to +global). The distribution statistics in the comment headers have been updated +accordingly. + + +4. String Operations + +The string operations (string assignment and string comparison) have not been +changed, to keep the program consistent with the original version. + +There has been some concern that the string operations are over-represented in +the program, and that execution time is dominated by these operations. This +was true in particular when optimizing compilers removed too much code in the +main part of the program, this should have been mitigated in version 2. + +It should be noted that this is a language-dependent issue: Dhrystone was +first published in Ada, and with Ada or Pascal semantics, the time spent in +the string operations is, at least in all implementations known to me, +considerably smaller. In Ada and Pascal, assignment and comparison of strings +are operators defined in the language, and the upper bounds of the strings +occuring in Dhrystone are part of the type information known at compilation +time. The compilers can therefore generate efficient inline code. In C, +string assignemt and comparisons are not part of the language, so the string +operations must be expressed in terms of the C library functions "strcpy" and +"strcmp". (ANSI C allows an implementation to use inline code for these +functions.) In addition to the overhead caused by additional function calls, +these functions are defined for null-terminated strings where the length of +the strings is not known at compilation time; the function has to check every +byte for the termination condition (the null byte). + +Obviously, a C library which includes efficiently coded "strcpy" and "strcmp" +functions helps to obtain good Dhrystone results. However, I don't think that +this is unfair since string functions do occur quite frequently in real +programs (editors, command interpreters, etc.). If the strings functions are +implemented efficiently, this helps real programs as well as benchmark +programs. + +I admit that the string comparison in Dhrystone terminates later (after +scanning 20 characters) than most string comparisons in real programs. For +consistency with the original benchmark, I didn't change the program despite +this weakness. + + +5. Intended Use of Dhrystone + +When Dhrystone is used, the following "ground rules" apply: + +o Separate compilation (Ada and C versions) + + As mentioned in [1], Dhrystone was written to reflect actual programming + practice in systems programming. The division into several compilation + units (5 in the Ada version, 2 in the C version) is intended, as is the + distribution of inter-module and intra-module subprogram calls. Although on + many systems there will be no difference in execution time to a Dhrystone + version where all compilation units are merged into one file, the rule is + that separate compilation should be used. The intention is that real + programming practice, where programs consist of several independently + compiled units, should be reflected. This also has implies that the + compiler, while compiling one unit, has no information about the use of + variables, register allocation etc. occuring in other compilation units. + Although in real life compilation units will probably be larger, the + intention is that these effects of separate compilation are modeled in + Dhrystone. + + A few language systems have post-linkage optimization available (e.g., final + register allocation is performed after linkage). This is a borderline case: + Post-linkage optimization involves additional program preparation time + (although not as much as compilation in one unit) which may prevent its + general use in practical programming. I think that since it defeats the + intentions given above, it should not be used for Dhrystone. + + Unfortunately, ISO/ANSI Pascal does not contain language features for + separate compilation. Although most commercial Pascal compilers provide + separate compilation in some way, we cannot use it for Dhrystone since such + a version would not be portable. Therefore, no attempt has been made to + provide a Pascal version with several compilation units. + +o No procedure merging + + Although Dhrystone contains some very short procedures where execution would + benefit from procedure merging (inlining, macro expansion of procedures), + procedure merging is not to be used. The reason is that the percentage of + procedure and function calls is part of the "Dhrystone distribution" of + statements contained in [1]. This restriction does not hold for the string + functions of the C version since ANSI C allows an implementation to use + inline code for these functions. + +o Other optimizations are allowed, but they should be indicated + + It is often hard to draw an exact line between "normal code generation" and + "optimization" in compilers: Some compilers perform operations by default + that are invoked in other compilers only when optimization is explicitly + requested. Also, we cannot avoid that in benchmarking people try to achieve + results that look as good as possible. Therefore, optimizations performed + by compilers - other than those listed above - are not forbidden when + Dhrystone execution times are measured. Dhrystone is not intended to be + non-optimizable but is intended to be similarly optimizable as normal + programs. For example, there are several places in Dhrystone where + performance benefits from optimizations like common subexpression + elimination, value propagation etc., but normal programs usually also + benefit from these optimizations. Therefore, no effort was made to + artificially prevent such optimizations. However, measurement reports + should indicate which compiler optimization levels have been used, and + reporting results with different levels of compiler optimization for the + same hardware is encouraged. + +o Default results are those without "register" declarations (C version) + + When Dhrystone results are quoted without additional qualification, they + should be understood as results obtained without use of the "register" + attribute. Good compilers should be able to make good use of registers even + without explicit register declarations ([3], p. 193). + +Of course, for experimental purposes, post-linkage optimization, procedure +merging and/or compilation in one unit can be done to determine their effects. +However, Dhrystone numbers obtained under these conditions should be +explicitly marked as such; "normal" Dhrystone results should be understood as +results obtained following the ground rules listed above. + +In any case, for serious performance evaluation, users are advised to ask for +code listings and to check them carefully. In this way, when results for +different systems are compared, the reader can get a feeling how much +performance difference is due to compiler optimization and how much is due to +hardware speed. + + +6. Acknowledgements + +The C version 2.1 of Dhrystone has been developed in cooperation with Rick +Richardson (Tinton Falls, NJ), it incorporates many ideas from the "Version +1.1" distributed previously by him over the UNIX network Usenet. Through his +activity with Usenet, Rick Richardson has made a very valuable contribution to +the dissemination of the benchmark. I also thank Chaim Benedelac (National +Semiconductor), David Ditzel (SUN), Earl Killian and John Mashey (MIPS), Alan +Smith and Rafael Saavedra-Barrera (UC at Berkeley) for their help with +comments on earlier versions of the benchmark. + + +7. Bibliography + +[1] + Reinhold P. Weicker: Dhrystone: A Synthetic Systems Programming Benchmark. + Communications of the ACM 27, 10 (Oct. 1984), 1013-1030 + +[2] + Rick Richardson: Dhrystone 1.1 Benchmark Summary (and Program Text) + Informal Distribution via "Usenet", Last Version Known to me: Sept. 21, + 1987 + +[3] + Brian W. Kernighan and Dennis M. Ritchie: The C Programming Language. + Prentice-Hall, Englewood Cliffs (NJ) 1978 + diff --git a/zpu/roadshow/roadshow/dhrystone/README_C b/zpu/roadshow/roadshow/dhrystone/README_C new file mode 100644 index 0000000..a27a192 --- /dev/null +++ b/zpu/roadshow/roadshow/dhrystone/README_C @@ -0,0 +1,78 @@ +This "shar" file contains the documentation for the +electronic mail distribution of the Dhrystone benchmark (C version 2.1); +a companion "shar" file contains the source code. +(Because of mail length restrictions for some mailers, I have +split the distribution in two parts.) + +For versions in other languages, see the other "shar" files. + +Files containing the C version (*.h: Header File, *.c: C Modules) + + dhry.h + dhry_1.c + dhry_2.c + +The file RATIONALE contains the article + + "Dhrystone Benchmark: Rationale for Version 2 and Measurement Rules" + +which has been published, together with the C source code (Version 2.0), +in SIGPLAN Notices vol. 23, no. 8 (Aug. 1988), pp. 49-62. +This article explains all changes that have been made for Version 2, +compared with the version of the original publication +in Communications of the ACM vol. 27, no. 10 (Oct. 1984), pp. 1013-1030. +It also contains "ground rules" for benchmarking with Dhrystone +which should be followed by everyone who uses the program and publishes +Dhrystone results. + +Compared with the Version 2.0 published in SIGPLAN Notices, Version 2.1 +contains a few corrections that have been made after Version 2.0 was +distriobuted over the UNIX network Usenet. These small differences between +Version 2.0 and 2.1 should not affect execution time measurements. +For those who want to compare the exact contents of both versions, +the file "dhry_c.dif" contains the differences between the two versions, +as generated by a file comparison of the corresponding files with the +UNIX utility "diff". + +The file VARIATIONS contains the article + + "Understanding Variations in Dhrystone Performance" + +which has been published in Microprocessor Report, May 1989 +(Editor: M. Slater), pp. 16-17. It describes the points that users +should know if C Dhrystone results are compared. + +Recipients of this shar file who perform measurements are asked +to send measurement results to the author and/or to Rick Richardson. +Rick Richardson publishes regularly Dhrystone results on the UNIX network +Usenet. For submissions of results to him (preferably by electronic mail, +see address in the program header), he has provided a form which is contained +in the file "submit.frm". + + +The following files are contained in other "shar" files: + +Files containing the Ada version (*.s: Specifications, *.b: Bodies): + + d_global.s + d_main.b + d_pack_1.b + d_pack_1.s + d_pack_2.b + d_pack_2.s + +File containing the Pascal version: + + dhry.p + + +February 22, 1990 + + Reinhold P. Weicker + Siemens AG, AUT E 51 + Postfach 3220 + D-8520 Erlangen + Germany (West) + + Phone: [xxx-49]-9131-7-20330 (8-17 Central European Time) + UUCP: ..!mcsun!unido!estevax!weicker diff --git a/zpu/roadshow/roadshow/dhrystone/VARIATIONS b/zpu/roadshow/roadshow/dhrystone/VARIATIONS new file mode 100644 index 0000000..3046cbd --- /dev/null +++ b/zpu/roadshow/roadshow/dhrystone/VARIATIONS @@ -0,0 +1,157 @@ + + Understanding Variations in Dhrystone Performance + + + + By Reinhold P. Weicker, Siemens AG, AUT E 51, Erlangen + + + + April 1989 + + + This article has appeared in: + + + Microprocessor Report, May 1989 (Editor: M. Slater), pp. 16-17 + + + + +Microprocessor manufacturers tend to credit all the performance measured by +benchmarks to the speed of their processors, they often don't even mention the +programming language and compiler used. In their detailed documents, usually +called "performance brief" or "performance report," they usually do give more +details. However, these details are often lost in the press releases and other +marketing statements. For serious performance evaluation, it is necessary to +study the code generated by the various compilers. + +Dhrystone was originally published in Ada (Communications of the ACM, Oct. +1984). However, since good Ada compilers were rare at this time and, together +with UNIX, C became more and more popular, the C version of Dhrystone is the +one now mainly used in industry. There are "official" versions 2.1 for Ada, +Pascal, and C, which are as close together as the languages' semantic +differences permit. + +Dhrystone contains two statements where the programming language and its +translation play a major part in the execution time measured by the benchmark: + + o String assignment (in procedure Proc_0 / main) + o String comparison (in function Func_2) + +In Ada and Pascal, strings are arrays of characters where the length of the +string is part of the type information known at compile time. In C, strings +are also arrays of characters, but there are no operators defined in the +language for assignment and comparison of strings. Instead, functions +"strcpy" and "strcmp" are used. These functions are defined for strings of +arbitrary length, and make use of the fact that strings in C have to end with +a terminating null byte. For general-purpose calls to these functions, the +implementor can assume nothing about the length and the alignment of the +strings involved. + +The C version of Dhrystone spends a relatively large amount of time in these +two functions. Some time ago, I made measurements on a VAX 11/785 with the +Berkeley UNIX (4.2) compilers (often-used compilers, but certainly not the +most advanced). In the C version, 23% of the time was spent in the string +functions; in the Pascal version, only 10%. On good RISC machines (where less +time is spent in the procedure calling sequence than on a VAX) and with better +optimizing compilers, the percentage is higher; MIPS has reported 34% for an +R3000. Because of this effect, Pascal and Ada Dhrystone results are usually +better than C results (except when the optimization quality of the C compiler +is considerably better than that of the other compilers). + +Several people have noted that the string operations are over-represented in +Dhrystone, mainly because the strings occurring in Dhrystone are longer than +average strings. I admit that this is true, and have said so in my SIGPLAN +Notices paper (Aug. 1988); however, I didn't want to generate confusion by +changing the string lengths from version 1 to version 2. + +Even if they are somewhat over-represented in Dhrystone, string operations are +frequent enough that it makes sense to implement them in the most efficient +way possible, not only for benchmarking purposes. This means that they can +and should be written in assembly language code. ANSI C also explicitly allows +the strings functions to be implemented as macros, i.e. by inline code. + +There is also a third way to speed up the "strcpy" statement in Dhrystone: For +this particular "strcpy" statement, the source of the assignment is a string +constant. Therefore, in contrast to calls to "strcpy" in the general case, the +compiler knows the length and alignment of the strings involved at compile +time and can generate code in the same efficient way as a Pascal compiler +(word instructions instead of byte instructions). + +This is not allowed in the case of the "strcmp" call: Here, the addresses are +formal procedure parameters, and no assumptions can be made about the length +or alignment of the strings. Any such assumptions would indicate an incorrect +implementation. They might work for Dhrystone, where the strings are in fact +word-aligned with typical compilers, but other programs would deliver +incorrect results. + +So, for an apple-to-apple comparison between processors, and not between +several possible (legal or illegal) degrees of compiler optimization, one +should check that the systems are comparable with respect to the following +three points: + + (1) String functions in assembly language vs. in C + + Frequently used functions such as the string functions can and should be + written in assembly language, and all serious C language systems known + to me do this. (I list this point for completeness only.) Note that + processors with an instruction that checks a word for a null byte (such + as AMD's 29000 and Intel's 80960) have an advantage here. (This + advantage decreases relatively if optimization (3) is applied.) Due to + the length of the strings involved in Dhrystone, this advantage may be + considered too high in perspective, but it is certainly legal to use + such instructions - after all, these situations are what they were + invented for. + + (2) String function code inline vs. as library functions. + + ANSI C has created a new situation, compared with the older + Kernighan/Ritchie C. In the original C, the definition of the string + function was not part of the language. Now it is, and inlining is + explicitly allowed. I probably should have stated more clearly in my + SIGPLAN Notices paper that the rule "No procedure inlining for + Dhrystone" referred to the user level procedures only and not to the + library routines. + + (3) Fixed-length and alignment assumptions for the strings + + Compilers should be allowed to optimize in these cases if (and only if) + it is safe to do so. For Dhrystone, this is the "strcpy" statement, but + not the "strcmp" statement (unless, of course, the "strcmp" code + explicitly checks the alignment at execution time and branches + accordingly). A "Dhrystone switch" for the compiler that causes the + generation of code that may not work under certain circumstances is + certainly inappropriate for comparisons. It has been reported in Usenet + that some C compilers provide such a compiler option; since I don't have + access to all C compilers involved, I cannot verify this. + + If the fixed-length and word-alignment assumption can be used, a wide + bus that permits fast multi-word load instructions certainly does help; + however, this fact by itself should not make a really big difference. + +A check of these points - something that is necessary for a thorough +evaluation and comparison of the Dhrystone performance claims - requires +object code listings as well as listings for the string functions (strcpy, +strcmp) that are possibly called by the program. + +I don't pretend that Dhrystone is a perfect tool to measure the integer +performance of microprocessors. The more it is used and discussed, the more I +myself learn about aspects that I hadn't noticed yet when I wrote the program. +And of course, the very success of a benchmark program is a danger in that +people may tune their compilers and/or hardware to it, and with this action +make it less useful. + +Whetstone and Linpack have their critical points also: The Whetstone rating +depends heavily on the speed of the mathematical functions (sine, sqrt, ...), +and Linpack is sensitive to data alignment for some cache configurations. + +Introduction of a standard set of public domain benchmark software (something +the SPEC effort attempts) is certainly a worthwhile thing. In the meantime, +people will continue to use whatever is available and widely distributed, and +Dhrystone ratings are probably still better than MIPS ratings if these are - +as often in industry - based on no reproducible derivation. However, any +serious performance evaluation requires more than just a comparison of raw +numbers; one has to make sure that the numbers have been obtained in a +comparable way. + diff --git a/zpu/roadshow/roadshow/dhrystone/build.sh b/zpu/roadshow/roadshow/dhrystone/build.sh new file mode 100644 index 0000000..5bba707 --- /dev/null +++ b/zpu/roadshow/roadshow/dhrystone/build.sh @@ -0,0 +1,7 @@ +zpu-elf-gcc -phi -DTIME dhry_1.c dhry_2.c -O3 -Wl,--relax -Wl,--gc-sections -o dhrystone.elf +zpu-elf-size *.elf +zpu-elf-objcopy -O binary dhrystone.elf dhrystone.bin +sh ../build/makefirmware.sh dhrystone.bin dhrystone.zpu + + + diff --git a/zpu/roadshow/roadshow/dhrystone/dhry-c b/zpu/roadshow/roadshow/dhrystone/dhry-c new file mode 100644 index 0000000..4cec46c --- /dev/null +++ b/zpu/roadshow/roadshow/dhrystone/dhry-c @@ -0,0 +1,1779 @@ +# to unbundle, sh this file (in an empty directory) +echo RATIONALE 1>&2 +sed >RATIONALE <<'//GO.SYSIN DD RATIONALE' 's/^-//' +- +- +- Dhrystone Benchmark: Rationale for Version 2 and Measurement Rules +- +- [published in SIGPLAN Notices 23,8 (Aug. 1988), 49-62] +- +- +- Reinhold P. Weicker +- Siemens AG, E STE 35 +- [now: Siemens AG, AUT E 51] +- Postfach 3220 +- D-8520 Erlangen +- Germany (West) +- +- +- +- +-1. Why a Version 2 of Dhrystone? +- +-The Dhrystone benchmark program [1] has become a popular benchmark for +-CPU/compiler performance measurement, in particular in the area of +-minicomputers, workstations, PC's and microprocesors. It apparently satisfies +-a need for an easy-to-use integer benchmark; it gives a first performance +-indication which is more meaningful than MIPS numbers which, in their literal +-meaning (million instructions per second), cannot be used across different +-instruction sets (e.g. RISC vs. CISC). With the increasing use of the +-benchmark, it seems necessary to reconsider the benchmark and to check whether +-it can still fulfill this function. Version 2 of Dhrystone is the result of +-such a re-evaluation, it has been made for two reasons: +- +-o Dhrystone has been published in Ada [1], and Versions in Ada, Pascal and C +- have been distributed by Reinhold Weicker via floppy disk. However, the +- version that was used most often for benchmarking has been the version made +- by Rick Richardson by another translation from the Ada version into the C +- programming language, this has been the version distributed via the UNIX +- network Usenet [2]. +- +- There is an obvious need for a common C version of Dhrystone, since C is at +- present the most popular system programming language for the class of +- systems (microcomputers, minicomputers, workstations) where Dhrystone is +- used most. There should be, as far as possible, only one C version of +- Dhrystone such that results can be compared without restrictions. In the +- past, the C versions distributed by Rick Richardson (Version 1.1) and by +- Reinhold Weicker had small (though not significant) differences. +- +- Together with the new C version, the Ada and Pascal versions have been +- updated as well. +- +-o As far as it is possible without changes to the Dhrystone statistics, +- optimizing compilers should be prevented from removing significant +- statements. It has turned out in the past that optimizing compilers +- suppressed code generation for too many statements (by "dead code removal" +- or "dead variable elimination"). This has lead to the danger that +- benchmarking results obtained by a naive application of Dhrystone - without +- inspection of the code that was generated - could become meaningless. +- +-The overall policiy for version 2 has been that the distribution of +-statements, operand types and operand locality described in [1] should remain +-unchanged as much as possible. (Very few changes were necessary; their impact +-should be negligible.) Also, the order of statements should remain unchanged. +-Although I am aware of some critical remarks on the benchmark - I agree with +-several of them - and know some suggestions for improvement, I didn't want to +-change the benchmark into something different from what has become known as +-"Dhrystone"; the confusion generated by such a change would probably outweight +-the benefits. If I were to write a new benchmark program, I wouldn't give it +-the name "Dhrystone" since this denotes the program published in [1]. +-However, I do recognize the need for a larger number of representative +-programs that can be used as benchmarks; users should always be encouraged to +-use more than just one benchmark. +- +-The new versions (version 2.1 for C, Pascal and Ada) will be distributed as +-widely as possible. (Version 2.1 differs from version 2.0 distributed via the +-UNIX Network Usenet in March 1988 only in a few corrections for minor +-deficiencies found by users of version 2.0.) Readers who want to use the +-benchmark for their own measurements can obtain a copy in machine-readable +-form on floppy disk (MS-DOS or XENIX format) from the author. +- +- +-2. Overall Characteristics of Version 2 +- +-In general, version 2 follows - in the parts that are significant for +-performance measurement, i.e. within the measurement loop - the published +-(Ada) version and the C versions previously distributed. Where the versions +-distributed by Rick Richardson [2] and Reinhold Weicker have been different, +-it follows the version distributed by Reinhold Weicker. (However, the +-differences have been so small that their impact on execution time in all +-likelihood has been negligible.) The initialization and UNIX instrumentation +-part - which had been omitted in [1] - follows mostly the ideas of Rick +-Richardson [2]. However, any changes in the initialization part and in the +-printing of the result have no impact on performance measurement since they +-are outside the measaurement loop. As a concession to older compilers, names +-have been made unique within the first 8 characters for the C version. +- +-The original publication of Dhrystone did not contain any statements for time +-measurement since they are necessarily system-dependent. However, it turned +-out that it is not enough just to inclose the main procedure of Dhrystone in a +-loop and to measure the execution time. If the variables that are computed +-are not used somehow, there is the danger that the compiler considers them as +-"dead variables" and suppresses code generation for a part of the statements. +-Therefore in version 2 all variables of "main" are printed at the end of the +-program. This also permits some plausibility control for correct execution of +-the benchmark. +- +-At several places in the benchmark, code has been added, but only in branches +-that are not executed. The intention is that optimizing compilers should be +-prevented from moving code out of the measurement loop, or from removing code +-altogether. Statements that are executed have been changed in very few places +-only. In these cases, only the role of some operands has been changed, and it +-was made sure that the numbers defining the "Dhrystone distribution" +-(distribution of statements, operand types and locality) still hold as much as +-possible. Except for sophisticated optimizing compilers, execution times for +-version 2.1 should be the same as for previous versions. +- +-Because of the self-imposed limitation that the order and distribution of the +-executed statements should not be changed, there are still cases where +-optimizing compilers may not generate code for some statements. To a certain +-degree, this is unavoidable for small synthetic benchmarks. Users of the +-benchmark are advised to check code listings whether code is generated for all +-statements of Dhrystone. +- +-Contrary to the suggestion in the published paper and its realization in the +-versions previously distributed, no attempt has been made to subtract the time +-for the measurement loop overhead. (This calculation has proven difficult to +-implement in a correct way, and its omission makes the program simpler.) +-However, since the loop check is now part of the benchmark, this does have an +-impact - though a very minor one - on the distribution statistics which have +-been updated for this version. +- +- +-3. Discussion of Individual Changes +- +-In this section, all changes are described that affect the measurement loop +-and that are not just renamings of variables. All remarks refer to the C +-version; the other language versions have been updated similarly. +- +-In addition to adding the measurement loop and the printout statements, +-changes have been made at the following places: +- +-o In procedure "main", three statements have been added in the non-executed +- "then" part of the statement +- +- if (Enum_Loc == Func_1 (Ch_Index, 'C')) +- +- they are +- +- strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 3'RD STRING"); +- Int_2_Loc = Run_Index; +- Int_Glob = Run_Index; +- +- The string assignment prevents movement of the preceding assignment to +- Str_2_Loc (5'th statement of "main") out of the measurement loop (This +- probably will not happen for the C version, but it did happen with another +- language and compiler.) The assignment to Int_2_Loc prevents value +- propagation for Int_2_Loc, and the assignment to Int_Glob makes the value of +- Int_Glob possibly dependent from the value of Run_Index. +- +-o In the three arithmetic computations at the end of the measurement loop in +- "main ", the role of some variables has been exchanged, to prevent the +- division from just cancelling out the multiplication as it was in [1]. A +- very smart compiler might have recognized this and suppressed code +- generation for the division. +- +-o For Proc_2, no code has been changed, but the values of the actual parameter +- have changed due to changes in "main". +- +-o In Proc_4, the second assignment has been changed from +- +- Bool_Loc = Bool_Loc | Bool_Glob; +- +- to +- +- Bool_Glob = Bool_Loc | Bool_Glob; +- +- It now assigns a value to a global variable instead of a local variable +- (Bool_Loc); Bool_Loc would be a "dead variable" which is not used +- afterwards. +- +-o In Func_1, the statement +- +- Ch_1_Glob = Ch_1_Loc; +- +- was added in the non-executed "else" part of the "if" statement, to prevent +- the suppression of code generation for the assignment to Ch_1_Loc. +- +-o In Func_2, the second character comparison statement has been changed to +- +- if (Ch_Loc == 'R') +- +- ('R' instead of 'X') because a comparison with 'X' is implied in the +- preceding "if" statement. +- +- Also in Func_2, the statement +- +- Int_Glob = Int_Loc; +- +- has been added in the non-executed part of the last "if" statement, in order +- to prevent Int_Loc from becoming a dead variable. +- +-o In Func_3, a non-executed "else" part has been added to the "if" statement. +- While the program would not be incorrect without this "else" part, it is +- considered bad programming practice if a function can be left without a +- return value. +- +- To compensate for this change, the (non-executed) "else" part in the "if" +- statement of Proc_3 was removed. +- +-The distribution statistics have been changed only by the addition of the +-measurement loop iteration (1 additional statement, 4 additional local integer +-operands) and by the change in Proc_4 (one operand changed from local to +-global). The distribution statistics in the comment headers have been updated +-accordingly. +- +- +-4. String Operations +- +-The string operations (string assignment and string comparison) have not been +-changed, to keep the program consistent with the original version. +- +-There has been some concern that the string operations are over-represented in +-the program, and that execution time is dominated by these operations. This +-was true in particular when optimizing compilers removed too much code in the +-main part of the program, this should have been mitigated in version 2. +- +-It should be noted that this is a language-dependent issue: Dhrystone was +-first published in Ada, and with Ada or Pascal semantics, the time spent in +-the string operations is, at least in all implementations known to me, +-considerably smaller. In Ada and Pascal, assignment and comparison of strings +-are operators defined in the language, and the upper bounds of the strings +-occuring in Dhrystone are part of the type information known at compilation +-time. The compilers can therefore generate efficient inline code. In C, +-string assignemt and comparisons are not part of the language, so the string +-operations must be expressed in terms of the C library functions "strcpy" and +-"strcmp". (ANSI C allows an implementation to use inline code for these +-functions.) In addition to the overhead caused by additional function calls, +-these functions are defined for null-terminated strings where the length of +-the strings is not known at compilation time; the function has to check every +-byte for the termination condition (the null byte). +- +-Obviously, a C library which includes efficiently coded "strcpy" and "strcmp" +-functions helps to obtain good Dhrystone results. However, I don't think that +-this is unfair since string functions do occur quite frequently in real +-programs (editors, command interpreters, etc.). If the strings functions are +-implemented efficiently, this helps real programs as well as benchmark +-programs. +- +-I admit that the string comparison in Dhrystone terminates later (after +-scanning 20 characters) than most string comparisons in real programs. For +-consistency with the original benchmark, I didn't change the program despite +-this weakness. +- +- +-5. Intended Use of Dhrystone +- +-When Dhrystone is used, the following "ground rules" apply: +- +-o Separate compilation (Ada and C versions) +- +- As mentioned in [1], Dhrystone was written to reflect actual programming +- practice in systems programming. The division into several compilation +- units (5 in the Ada version, 2 in the C version) is intended, as is the +- distribution of inter-module and intra-module subprogram calls. Although on +- many systems there will be no difference in execution time to a Dhrystone +- version where all compilation units are merged into one file, the rule is +- that separate compilation should be used. The intention is that real +- programming practice, where programs consist of several independently +- compiled units, should be reflected. This also has implies that the +- compiler, while compiling one unit, has no information about the use of +- variables, register allocation etc. occuring in other compilation units. +- Although in real life compilation units will probably be larger, the +- intention is that these effects of separate compilation are modeled in +- Dhrystone. +- +- A few language systems have post-linkage optimization available (e.g., final +- register allocation is performed after linkage). This is a borderline case: +- Post-linkage optimization involves additional program preparation time +- (although not as much as compilation in one unit) which may prevent its +- general use in practical programming. I think that since it defeats the +- intentions given above, it should not be used for Dhrystone. +- +- Unfortunately, ISO/ANSI Pascal does not contain language features for +- separate compilation. Although most commercial Pascal compilers provide +- separate compilation in some way, we cannot use it for Dhrystone since such +- a version would not be portable. Therefore, no attempt has been made to +- provide a Pascal version with several compilation units. +- +-o No procedure merging +- +- Although Dhrystone contains some very short procedures where execution would +- benefit from procedure merging (inlining, macro expansion of procedures), +- procedure merging is not to be used. The reason is that the percentage of +- procedure and function calls is part of the "Dhrystone distribution" of +- statements contained in [1]. This restriction does not hold for the string +- functions of the C version since ANSI C allows an implementation to use +- inline code for these functions. +- +-o Other optimizations are allowed, but they should be indicated +- +- It is often hard to draw an exact line between "normal code generation" and +- "optimization" in compilers: Some compilers perform operations by default +- that are invoked in other compilers only when optimization is explicitly +- requested. Also, we cannot avoid that in benchmarking people try to achieve +- results that look as good as possible. Therefore, optimizations performed +- by compilers - other than those listed above - are not forbidden when +- Dhrystone execution times are measured. Dhrystone is not intended to be +- non-optimizable but is intended to be similarly optimizable as normal +- programs. For example, there are several places in Dhrystone where +- performance benefits from optimizations like common subexpression +- elimination, value propagation etc., but normal programs usually also +- benefit from these optimizations. Therefore, no effort was made to +- artificially prevent such optimizations. However, measurement reports +- should indicate which compiler optimization levels have been used, and +- reporting results with different levels of compiler optimization for the +- same hardware is encouraged. +- +-o Default results are those without "register" declarations (C version) +- +- When Dhrystone results are quoted without additional qualification, they +- should be understood as results obtained without use of the "register" +- attribute. Good compilers should be able to make good use of registers even +- without explicit register declarations ([3], p. 193). +- +-Of course, for experimental purposes, post-linkage optimization, procedure +-merging and/or compilation in one unit can be done to determine their effects. +-However, Dhrystone numbers obtained under these conditions should be +-explicitly marked as such; "normal" Dhrystone results should be understood as +-results obtained following the ground rules listed above. +- +-In any case, for serious performance evaluation, users are advised to ask for +-code listings and to check them carefully. In this way, when results for +-different systems are compared, the reader can get a feeling how much +-performance difference is due to compiler optimization and how much is due to +-hardware speed. +- +- +-6. Acknowledgements +- +-The C version 2.1 of Dhrystone has been developed in cooperation with Rick +-Richardson (Tinton Falls, NJ), it incorporates many ideas from the "Version +-1.1" distributed previously by him over the UNIX network Usenet. Through his +-activity with Usenet, Rick Richardson has made a very valuable contribution to +-the dissemination of the benchmark. I also thank Chaim Benedelac (National +-Semiconductor), David Ditzel (SUN), Earl Killian and John Mashey (MIPS), Alan +-Smith and Rafael Saavedra-Barrera (UC at Berkeley) for their help with +-comments on earlier versions of the benchmark. +- +- +-7. Bibliography +- +-[1] +- Reinhold P. Weicker: Dhrystone: A Synthetic Systems Programming Benchmark. +- Communications of the ACM 27, 10 (Oct. 1984), 1013-1030 +- +-[2] +- Rick Richardson: Dhrystone 1.1 Benchmark Summary (and Program Text) +- Informal Distribution via "Usenet", Last Version Known to me: Sept. 21, +- 1987 +- +-[3] +- Brian W. Kernighan and Dennis M. Ritchie: The C Programming Language. +- Prentice-Hall, Englewood Cliffs (NJ) 1978 +- +//GO.SYSIN DD RATIONALE +echo README_C 1>&2 +sed >README_C <<'//GO.SYSIN DD README_C' 's/^-//' +-This "shar" file contains the documentation for the +-electronic mail distribution of the Dhrystone benchmark (C version 2.1); +-a companion "shar" file contains the source code. +-(Because of mail length restrictions for some mailers, I have +-split the distribution in two parts.) +- +-For versions in other languages, see the other "shar" files. +- +-Files containing the C version (*.h: Header File, *.c: C Modules) +- +- dhry.h +- dhry_1.c +- dhry_2.c +- +-The file RATIONALE contains the article +- +- "Dhrystone Benchmark: Rationale for Version 2 and Measurement Rules" +- +-which has been published, together with the C source code (Version 2.0), +-in SIGPLAN Notices vol. 23, no. 8 (Aug. 1988), pp. 49-62. +-This article explains all changes that have been made for Version 2, +-compared with the version of the original publication +-in Communications of the ACM vol. 27, no. 10 (Oct. 1984), pp. 1013-1030. +-It also contains "ground rules" for benchmarking with Dhrystone +-which should be followed by everyone who uses the program and publishes +-Dhrystone results. +- +-Compared with the Version 2.0 published in SIGPLAN Notices, Version 2.1 +-contains a few corrections that have been made after Version 2.0 was +-distriobuted over the UNIX network Usenet. These small differences between +-Version 2.0 and 2.1 should not affect execution time measurements. +-For those who want to compare the exact contents of both versions, +-the file "dhry_c.dif" contains the differences between the two versions, +-as generated by a file comparison of the corresponding files with the +-UNIX utility "diff". +- +-The file VARIATIONS contains the article +- +- "Understanding Variations in Dhrystone Performance" +- +-which has been published in Microprocessor Report, May 1989 +-(Editor: M. Slater), pp. 16-17. It describes the points that users +-should know if C Dhrystone results are compared. +- +-Recipients of this shar file who perform measurements are asked +-to send measurement results to the author and/or to Rick Richardson. +-Rick Richardson publishes regularly Dhrystone results on the UNIX network +-Usenet. For submissions of results to him (preferably by electronic mail, +-see address in the program header), he has provided a form which is contained +-in the file "submit.frm". +- +- +-The following files are contained in other "shar" files: +- +-Files containing the Ada version (*.s: Specifications, *.b: Bodies): +- +- d_global.s +- d_main.b +- d_pack_1.b +- d_pack_1.s +- d_pack_2.b +- d_pack_2.s +- +-File containing the Pascal version: +- +- dhry.p +- +- +-February 22, 1990 +- +- Reinhold P. Weicker +- Siemens AG, AUT E 51 +- Postfach 3220 +- D-8520 Erlangen +- Germany (West) +- +- Phone: [xxx-49]-9131-7-20330 (8-17 Central European Time) +- UUCP: ..!mcsun!unido!estevax!weicker +//GO.SYSIN DD README_C +echo VARIATIONS 1>&2 +sed >VARIATIONS <<'//GO.SYSIN DD VARIATIONS' 's/^-//' +- +- Understanding Variations in Dhrystone Performance +- +- +- +- By Reinhold P. Weicker, Siemens AG, AUT E 51, Erlangen +- +- +- +- April 1989 +- +- +- This article has appeared in: +- +- +- Microprocessor Report, May 1989 (Editor: M. Slater), pp. 16-17 +- +- +- +- +-Microprocessor manufacturers tend to credit all the performance measured by +-benchmarks to the speed of their processors, they often don't even mention the +-programming language and compiler used. In their detailed documents, usually +-called "performance brief" or "performance report," they usually do give more +-details. However, these details are often lost in the press releases and other +-marketing statements. For serious performance evaluation, it is necessary to +-study the code generated by the various compilers. +- +-Dhrystone was originally published in Ada (Communications of the ACM, Oct. +-1984). However, since good Ada compilers were rare at this time and, together +-with UNIX, C became more and more popular, the C version of Dhrystone is the +-one now mainly used in industry. There are "official" versions 2.1 for Ada, +-Pascal, and C, which are as close together as the languages' semantic +-differences permit. +- +-Dhrystone contains two statements where the programming language and its +-translation play a major part in the execution time measured by the benchmark: +- +- o String assignment (in procedure Proc_0 / main) +- o String comparison (in function Func_2) +- +-In Ada and Pascal, strings are arrays of characters where the length of the +-string is part of the type information known at compile time. In C, strings +-are also arrays of characters, but there are no operators defined in the +-language for assignment and comparison of strings. Instead, functions +-"strcpy" and "strcmp" are used. These functions are defined for strings of +-arbitrary length, and make use of the fact that strings in C have to end with +-a terminating null byte. For general-purpose calls to these functions, the +-implementor can assume nothing about the length and the alignment of the +-strings involved. +- +-The C version of Dhrystone spends a relatively large amount of time in these +-two functions. Some time ago, I made measurements on a VAX 11/785 with the +-Berkeley UNIX (4.2) compilers (often-used compilers, but certainly not the +-most advanced). In the C version, 23% of the time was spent in the string +-functions; in the Pascal version, only 10%. On good RISC machines (where less +-time is spent in the procedure calling sequence than on a VAX) and with better +-optimizing compilers, the percentage is higher; MIPS has reported 34% for an +-R3000. Because of this effect, Pascal and Ada Dhrystone results are usually +-better than C results (except when the optimization quality of the C compiler +-is considerably better than that of the other compilers). +- +-Several people have noted that the string operations are over-represented in +-Dhrystone, mainly because the strings occurring in Dhrystone are longer than +-average strings. I admit that this is true, and have said so in my SIGPLAN +-Notices paper (Aug. 1988); however, I didn't want to generate confusion by +-changing the string lengths from version 1 to version 2. +- +-Even if they are somewhat over-represented in Dhrystone, string operations are +-frequent enough that it makes sense to implement them in the most efficient +-way possible, not only for benchmarking purposes. This means that they can +-and should be written in assembly language code. ANSI C also explicitly allows +-the strings functions to be implemented as macros, i.e. by inline code. +- +-There is also a third way to speed up the "strcpy" statement in Dhrystone: For +-this particular "strcpy" statement, the source of the assignment is a string +-constant. Therefore, in contrast to calls to "strcpy" in the general case, the +-compiler knows the length and alignment of the strings involved at compile +-time and can generate code in the same efficient way as a Pascal compiler +-(word instructions instead of byte instructions). +- +-This is not allowed in the case of the "strcmp" call: Here, the addresses are +-formal procedure parameters, and no assumptions can be made about the length +-or alignment of the strings. Any such assumptions would indicate an incorrect +-implementation. They might work for Dhrystone, where the strings are in fact +-word-aligned with typical compilers, but other programs would deliver +-incorrect results. +- +-So, for an apple-to-apple comparison between processors, and not between +-several possible (legal or illegal) degrees of compiler optimization, one +-should check that the systems are comparable with respect to the following +-three points: +- +- (1) String functions in assembly language vs. in C +- +- Frequently used functions such as the string functions can and should be +- written in assembly language, and all serious C language systems known +- to me do this. (I list this point for completeness only.) Note that +- processors with an instruction that checks a word for a null byte (such +- as AMD's 29000 and Intel's 80960) have an advantage here. (This +- advantage decreases relatively if optimization (3) is applied.) Due to +- the length of the strings involved in Dhrystone, this advantage may be +- considered too high in perspective, but it is certainly legal to use +- such instructions - after all, these situations are what they were +- invented for. +- +- (2) String function code inline vs. as library functions. +- +- ANSI C has created a new situation, compared with the older +- Kernighan/Ritchie C. In the original C, the definition of the string +- function was not part of the language. Now it is, and inlining is +- explicitly allowed. I probably should have stated more clearly in my +- SIGPLAN Notices paper that the rule "No procedure inlining for +- Dhrystone" referred to the user level procedures only and not to the +- library routines. +- +- (3) Fixed-length and alignment assumptions for the strings +- +- Compilers should be allowed to optimize in these cases if (and only if) +- it is safe to do so. For Dhrystone, this is the "strcpy" statement, but +- not the "strcmp" statement (unless, of course, the "strcmp" code +- explicitly checks the alignment at execution time and branches +- accordingly). A "Dhrystone switch" for the compiler that causes the +- generation of code that may not work under certain circumstances is +- certainly inappropriate for comparisons. It has been reported in Usenet +- that some C compilers provide such a compiler option; since I don't have +- access to all C compilers involved, I cannot verify this. +- +- If the fixed-length and word-alignment assumption can be used, a wide +- bus that permits fast multi-word load instructions certainly does help; +- however, this fact by itself should not make a really big difference. +- +-A check of these points - something that is necessary for a thorough +-evaluation and comparison of the Dhrystone performance claims - requires +-object code listings as well as listings for the string functions (strcpy, +-strcmp) that are possibly called by the program. +- +-I don't pretend that Dhrystone is a perfect tool to measure the integer +-performance of microprocessors. The more it is used and discussed, the more I +-myself learn about aspects that I hadn't noticed yet when I wrote the program. +-And of course, the very success of a benchmark program is a danger in that +-people may tune their compilers and/or hardware to it, and with this action +-make it less useful. +- +-Whetstone and Linpack have their critical points also: The Whetstone rating +-depends heavily on the speed of the mathematical functions (sine, sqrt, ...), +-and Linpack is sensitive to data alignment for some cache configurations. +- +-Introduction of a standard set of public domain benchmark software (something +-the SPEC effort attempts) is certainly a worthwhile thing. In the meantime, +-people will continue to use whatever is available and widely distributed, and +-Dhrystone ratings are probably still better than MIPS ratings if these are - +-as often in industry - based on no reproducible derivation. However, any +-serious performance evaluation requires more than just a comparison of raw +-numbers; one has to make sure that the numbers have been obtained in a +-comparable way. +- +//GO.SYSIN DD VARIATIONS +echo dhry.h 1>&2 +sed >dhry.h <<'//GO.SYSIN DD dhry.h' 's/^-//' +-/* +- **************************************************************************** +- * +- * "DHRYSTONE" Benchmark Program +- * ----------------------------- +- * +- * Version: C, Version 2.1 +- * +- * File: dhry.h (part 1 of 3) +- * +- * Date: May 25, 1988 +- * +- * Author: Reinhold P. Weicker +- * Siemens AG, AUT E 51 +- * Postfach 3220 +- * 8520 Erlangen +- * Germany (West) +- * Phone: [+49]-9131-7-20330 +- * (8-17 Central European Time) +- * Usenet: ..!mcsun!unido!estevax!weicker +- * +- * Original Version (in Ada) published in +- * "Communications of the ACM" vol. 27., no. 10 (Oct. 1984), +- * pp. 1013 - 1030, together with the statistics +- * on which the distribution of statements etc. is based. +- * +- * In this C version, the following C library functions are used: +- * - strcpy, strcmp (inside the measurement loop) +- * - printf, scanf (outside the measurement loop) +- * In addition, Berkeley UNIX system calls "times ()" or "time ()" +- * are used for execution time measurement. For measurements +- * on other systems, these calls have to be changed. +- * +- * Collection of Results: +- * Reinhold Weicker (address see above) and +- * +- * Rick Richardson +- * PC Research. Inc. +- * 94 Apple Orchard Drive +- * Tinton Falls, NJ 07724 +- * Phone: (201) 389-8963 (9-17 EST) +- * Usenet: ...!uunet!pcrat!rick +- * +- * Please send results to Rick Richardson and/or Reinhold Weicker. +- * Complete information should be given on hardware and software used. +- * Hardware information includes: Machine type, CPU, type and size +- * of caches; for microprocessors: clock frequency, memory speed +- * (number of wait states). +- * Software information includes: Compiler (and runtime library) +- * manufacturer and version, compilation switches, OS version. +- * The Operating System version may give an indication about the +- * compiler; Dhrystone itself performs no OS calls in the measurement loop. +- * +- * The complete output generated by the program should be mailed +- * such that at least some checks for correctness can be made. +- * +- *************************************************************************** +- * +- * History: This version C/2.1 has been made for two reasons: +- * +- * 1) There is an obvious need for a common C version of +- * Dhrystone, since C is at present the most popular system +- * programming language for the class of processors +- * (microcomputers, minicomputers) where Dhrystone is used most. +- * There should be, as far as possible, only one C version of +- * Dhrystone such that results can be compared without +- * restrictions. In the past, the C versions distributed +- * by Rick Richardson (Version 1.1) and by Reinhold Weicker +- * had small (though not significant) differences. +- * +- * 2) As far as it is possible without changes to the Dhrystone +- * statistics, optimizing compilers should be prevented from +- * removing significant statements. +- * +- * This C version has been developed in cooperation with +- * Rick Richardson (Tinton Falls, NJ), it incorporates many +- * ideas from the "Version 1.1" distributed previously by +- * him over the UNIX network Usenet. +- * I also thank Chaim Benedelac (National Semiconductor), +- * David Ditzel (SUN), Earl Killian and John Mashey (MIPS), +- * Alan Smith and Rafael Saavedra-Barrera (UC at Berkeley) +- * for their help with comments on earlier versions of the +- * benchmark. +- * +- * Changes: In the initialization part, this version follows mostly +- * Rick Richardson's version distributed via Usenet, not the +- * version distributed earlier via floppy disk by Reinhold Weicker. +- * As a concession to older compilers, names have been made +- * unique within the first 8 characters. +- * Inside the measurement loop, this version follows the +- * version previously distributed by Reinhold Weicker. +- * +- * At several places in the benchmark, code has been added, +- * but within the measurement loop only in branches that +- * are not executed. The intention is that optimizing compilers +- * should be prevented from moving code out of the measurement +- * loop, or from removing code altogether. Since the statements +- * that are executed within the measurement loop have NOT been +- * changed, the numbers defining the "Dhrystone distribution" +- * (distribution of statements, operand types and locality) +- * still hold. Except for sophisticated optimizing compilers, +- * execution times for this version should be the same as +- * for previous versions. +- * +- * Since it has proven difficult to subtract the time for the +- * measurement loop overhead in a correct way, the loop check +- * has been made a part of the benchmark. This does have +- * an impact - though a very minor one - on the distribution +- * statistics which have been updated for this version. +- * +- * All changes within the measurement loop are described +- * and discussed in the companion paper "Rationale for +- * Dhrystone version 2". +- * +- * Because of the self-imposed limitation that the order and +- * distribution of the executed statements should not be +- * changed, there are still cases where optimizing compilers +- * may not generate code for some statements. To a certain +- * degree, this is unavoidable for small synthetic benchmarks. +- * Users of the benchmark are advised to check code listings +- * whether code is generated for all statements of Dhrystone. +- * +- * Version 2.1 is identical to version 2.0 distributed via +- * the UNIX network Usenet in March 1988 except that it corrects +- * some minor deficiencies that were found by users of version 2.0. +- * The only change within the measurement loop is that a +- * non-executed "else" part was added to the "if" statement in +- * Func_3, and a non-executed "else" part removed from Proc_3. +- * +- *************************************************************************** +- * +- * Defines: The following "Defines" are possible: +- * -DREG=register (default: Not defined) +- * As an approximation to what an average C programmer +- * might do, the "register" storage class is applied +- * (if enabled by -DREG=register) +- * - for local variables, if they are used (dynamically) +- * five or more times +- * - for parameters if they are used (dynamically) +- * six or more times +- * Note that an optimal "register" strategy is +- * compiler-dependent, and that "register" declarations +- * do not necessarily lead to faster execution. +- * -DNOSTRUCTASSIGN (default: Not defined) +- * Define if the C compiler does not support +- * assignment of structures. +- * -DNOENUMS (default: Not defined) +- * Define if the C compiler does not support +- * enumeration types. +- * -DTIMES (default) +- * -DTIME +- * The "times" function of UNIX (returning process times) +- * or the "time" function (returning wallclock time) +- * is used for measurement. +- * For single user machines, "time ()" is adequate. For +- * multi-user machines where you cannot get single-user +- * access, use the "times ()" function. If you have +- * neither, use a stopwatch in the dead of night. +- * "printf"s are provided marking the points "Start Timer" +- * and "Stop Timer". DO NOT use the UNIX "time(1)" +- * command, as this will measure the total time to +- * run this program, which will (erroneously) include +- * the time to allocate storage (malloc) and to perform +- * the initialization. +- * -DHZ=nnn +- * In Berkeley UNIX, the function "times" returns process +- * time in 1/HZ seconds, with HZ = 60 for most systems. +- * CHECK YOUR SYSTEM DESCRIPTION BEFORE YOU JUST APPLY +- * A VALUE. +- * +- *************************************************************************** +- * +- * Compilation model and measurement (IMPORTANT): +- * +- * This C version of Dhrystone consists of three files: +- * - dhry.h (this file, containing global definitions and comments) +- * - dhry_1.c (containing the code corresponding to Ada package Pack_1) +- * - dhry_2.c (containing the code corresponding to Ada package Pack_2) +- * +- * The following "ground rules" apply for measurements: +- * - Separate compilation +- * - No procedure merging +- * - Otherwise, compiler optimizations are allowed but should be indicated +- * - Default results are those without register declarations +- * See the companion paper "Rationale for Dhrystone Version 2" for a more +- * detailed discussion of these ground rules. +- * +- * For 16-Bit processors (e.g. 80186, 80286), times for all compilation +- * models ("small", "medium", "large" etc.) should be given if possible, +- * together with a definition of these models for the compiler system used. +- * +- ************************************************************************** +- * +- * Dhrystone (C version) statistics: +- * +- * [Comment from the first distribution, updated for version 2. +- * Note that because of language differences, the numbers are slightly +- * different from the Ada version.] +- * +- * The following program contains statements of a high level programming +- * language (here: C) in a distribution considered representative: +- * +- * assignments 52 (51.0 %) +- * control statements 33 (32.4 %) +- * procedure, function calls 17 (16.7 %) +- * +- * 103 statements are dynamically executed. The program is balanced with +- * respect to the three aspects: +- * +- * - statement type +- * - operand type +- * - operand locality +- * operand global, local, parameter, or constant. +- * +- * The combination of these three aspects is balanced only approximately. +- * +- * 1. Statement Type: +- * ----------------- number +- * +- * V1 = V2 9 +- * (incl. V1 = F(..) +- * V = Constant 12 +- * Assignment, 7 +- * with array element +- * Assignment, 6 +- * with record component +- * -- +- * 34 34 +- * +- * X = Y +|-|"&&"|"|" Z 5 +- * X = Y +|-|"==" Constant 6 +- * X = X +|- 1 3 +- * X = Y *|/ Z 2 +- * X = Expression, 1 +- * two operators +- * X = Expression, 1 +- * three operators +- * -- +- * 18 18 +- * +- * if .... 14 +- * with "else" 7 +- * without "else" 7 +- * executed 3 +- * not executed 4 +- * for ... 7 | counted every time +- * while ... 4 | the loop condition +- * do ... while 1 | is evaluated +- * switch ... 1 +- * break 1 +- * declaration with 1 +- * initialization +- * -- +- * 34 34 +- * +- * P (...) procedure call 11 +- * user procedure 10 +- * library procedure 1 +- * X = F (...) +- * function call 6 +- * user function 5 +- * library function 1 +- * -- +- * 17 17 +- * --- +- * 103 +- * +- * The average number of parameters in procedure or function calls +- * is 1.82 (not counting the function values as implicit parameters). +- * +- * +- * 2. Operators +- * ------------ +- * number approximate +- * percentage +- * +- * Arithmetic 32 50.8 +- * +- * + 21 33.3 +- * - 7 11.1 +- * * 3 4.8 +- * / (int div) 1 1.6 +- * +- * Comparison 27 42.8 +- * +- * == 9 14.3 +- * /= 4 6.3 +- * > 1 1.6 +- * < 3 4.8 +- * >= 1 1.6 +- * <= 9 14.3 +- * +- * Logic 4 6.3 +- * +- * && (AND-THEN) 1 1.6 +- * | (OR) 1 1.6 +- * ! (NOT) 2 3.2 +- * +- * -- ----- +- * 63 100.1 +- * +- * +- * 3. Operand Type (counted once per operand reference): +- * --------------- +- * number approximate +- * percentage +- * +- * Integer 175 72.3 % +- * Character 45 18.6 % +- * Pointer 12 5.0 % +- * String30 6 2.5 % +- * Array 2 0.8 % +- * Record 2 0.8 % +- * --- ------- +- * 242 100.0 % +- * +- * When there is an access path leading to the final operand (e.g. a record +- * component), only the final data type on the access path is counted. +- * +- * +- * 4. Operand Locality: +- * ------------------- +- * number approximate +- * percentage +- * +- * local variable 114 47.1 % +- * global variable 22 9.1 % +- * parameter 45 18.6 % +- * value 23 9.5 % +- * reference 22 9.1 % +- * function result 6 2.5 % +- * constant 55 22.7 % +- * --- ------- +- * 242 100.0 % +- * +- * +- * The program does not compute anything meaningful, but it is syntactically +- * and semantically correct. All variables have a value assigned to them +- * before they are used as a source operand. +- * +- * There has been no explicit effort to account for the effects of a +- * cache, or to balance the use of long or short displacements for code or +- * data. +- * +- *************************************************************************** +- */ +- +-/* Compiler and system dependent definitions: */ +- +-#ifndef TIME +-#define TIMES +-#endif +- /* Use times(2) time function unless */ +- /* explicitly defined otherwise */ +- +-#ifdef TIMES +-#include +-#include +- /* for "times" */ +-#endif +- +-#define Mic_secs_Per_Second 1000000.0 +- /* Berkeley UNIX C returns process times in seconds/HZ */ +- +-#ifdef NOSTRUCTASSIGN +-#define structassign(d, s) memcpy(&(d), &(s), sizeof(d)) +-#else +-#define structassign(d, s) d = s +-#endif +- +-#ifdef NOENUM +-#define Ident_1 0 +-#define Ident_2 1 +-#define Ident_3 2 +-#define Ident_4 3 +-#define Ident_5 4 +- typedef int Enumeration; +-#else +- typedef enum {Ident_1, Ident_2, Ident_3, Ident_4, Ident_5} +- Enumeration; +-#endif +- /* for boolean and enumeration types in Ada, Pascal */ +- +-/* General definitions: */ +- +-#include +- /* for strcpy, strcmp */ +- +-#define Null 0 +- /* Value of a Null pointer */ +-#define true 1 +-#define false 0 +- +-typedef int One_Thirty; +-typedef int One_Fifty; +-typedef char Capital_Letter; +-typedef int Boolean; +-typedef char Str_30 [31]; +-typedef int Arr_1_Dim [50]; +-typedef int Arr_2_Dim [50] [50]; +- +-typedef struct record +- { +- struct record *Ptr_Comp; +- Enumeration Discr; +- union { +- struct { +- Enumeration Enum_Comp; +- int Int_Comp; +- char Str_Comp [31]; +- } var_1; +- struct { +- Enumeration E_Comp_2; +- char Str_2_Comp [31]; +- } var_2; +- struct { +- char Ch_1_Comp; +- char Ch_2_Comp; +- } var_3; +- } variant; +- } Rec_Type, *Rec_Pointer; +- +- +//GO.SYSIN DD dhry.h +echo dhry_1.c 1>&2 +sed >dhry_1.c <<'//GO.SYSIN DD dhry_1.c' 's/^-//' +-/* +- **************************************************************************** +- * +- * "DHRYSTONE" Benchmark Program +- * ----------------------------- +- * +- * Version: C, Version 2.1 +- * +- * File: dhry_1.c (part 2 of 3) +- * +- * Date: May 25, 1988 +- * +- * Author: Reinhold P. Weicker +- * +- **************************************************************************** +- */ +- +-#include "dhry.h" +- +-/* Global Variables: */ +- +-Rec_Pointer Ptr_Glob, +- Next_Ptr_Glob; +-int Int_Glob; +-Boolean Bool_Glob; +-char Ch_1_Glob, +- Ch_2_Glob; +-int Arr_1_Glob [50]; +-int Arr_2_Glob [50] [50]; +- +-extern char *malloc (); +-Enumeration Func_1 (); +- /* forward declaration necessary since Enumeration may not simply be int */ +- +-#ifndef REG +- Boolean Reg = false; +-#define REG +- /* REG becomes defined as empty */ +- /* i.e. no register variables */ +-#else +- Boolean Reg = true; +-#endif +- +-/* variables for time measurement: */ +- +-#ifdef TIMES +-struct tms time_info; +-extern int times (); +- /* see library function "times" */ +-#define Too_Small_Time 120 +- /* Measurements should last at least about 2 seconds */ +-#endif +-#ifdef TIME +-extern long time(); +- /* see library function "time" */ +-#define Too_Small_Time 2 +- /* Measurements should last at least 2 seconds */ +-#endif +- +-long Begin_Time, +- End_Time, +- User_Time; +-float Microseconds, +- Dhrystones_Per_Second; +- +-/* end of variables for time measurement */ +- +- +-main () +-/*****/ +- +- /* main program, corresponds to procedures */ +- /* Main and Proc_0 in the Ada version */ +-{ +- One_Fifty Int_1_Loc; +- REG One_Fifty Int_2_Loc; +- One_Fifty Int_3_Loc; +- REG char Ch_Index; +- Enumeration Enum_Loc; +- Str_30 Str_1_Loc; +- Str_30 Str_2_Loc; +- REG int Run_Index; +- REG int Number_Of_Runs; +- +- /* Initializations */ +- +- Next_Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type)); +- Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type)); +- +- Ptr_Glob->Ptr_Comp = Next_Ptr_Glob; +- Ptr_Glob->Discr = Ident_1; +- Ptr_Glob->variant.var_1.Enum_Comp = Ident_3; +- Ptr_Glob->variant.var_1.Int_Comp = 40; +- strcpy (Ptr_Glob->variant.var_1.Str_Comp, +- "DHRYSTONE PROGRAM, SOME STRING"); +- strcpy (Str_1_Loc, "DHRYSTONE PROGRAM, 1'ST STRING"); +- +- Arr_2_Glob [8][7] = 10; +- /* Was missing in published program. Without this statement, */ +- /* Arr_2_Glob [8][7] would have an undefined value. */ +- /* Warning: With 16-Bit processors and Number_Of_Runs > 32000, */ +- /* overflow may occur for this array element. */ +- +- printf ("\n"); +- printf ("Dhrystone Benchmark, Version 2.1 (Language: C)\n"); +- printf ("\n"); +- if (Reg) +- { +- printf ("Program compiled with 'register' attribute\n"); +- printf ("\n"); +- } +- else +- { +- printf ("Program compiled without 'register' attribute\n"); +- printf ("\n"); +- } +- printf ("Please give the number of runs through the benchmark: "); +- { +- int n; +- scanf ("%d", &n); +- Number_Of_Runs = n; +- } +- printf ("\n"); +- +- printf ("Execution starts, %d runs through Dhrystone\n", Number_Of_Runs); +- +- /***************/ +- /* Start timer */ +- /***************/ +- +-#ifdef TIMES +- times (&time_info); +- Begin_Time = (long) time_info.tms_utime; +-#endif +-#ifdef TIME +- Begin_Time = time ( (long *) 0); +-#endif +- +- for (Run_Index = 1; Run_Index <= Number_Of_Runs; ++Run_Index) +- { +- +- Proc_5(); +- Proc_4(); +- /* Ch_1_Glob == 'A', Ch_2_Glob == 'B', Bool_Glob == true */ +- Int_1_Loc = 2; +- Int_2_Loc = 3; +- strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 2'ND STRING"); +- Enum_Loc = Ident_2; +- Bool_Glob = ! Func_2 (Str_1_Loc, Str_2_Loc); +- /* Bool_Glob == 1 */ +- while (Int_1_Loc < Int_2_Loc) /* loop body executed once */ +- { +- Int_3_Loc = 5 * Int_1_Loc - Int_2_Loc; +- /* Int_3_Loc == 7 */ +- Proc_7 (Int_1_Loc, Int_2_Loc, &Int_3_Loc); +- /* Int_3_Loc == 7 */ +- Int_1_Loc += 1; +- } /* while */ +- /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */ +- Proc_8 (Arr_1_Glob, Arr_2_Glob, Int_1_Loc, Int_3_Loc); +- /* Int_Glob == 5 */ +- Proc_1 (Ptr_Glob); +- for (Ch_Index = 'A'; Ch_Index <= Ch_2_Glob; ++Ch_Index) +- /* loop body executed twice */ +- { +- if (Enum_Loc == Func_1 (Ch_Index, 'C')) +- /* then, not executed */ +- { +- Proc_6 (Ident_1, &Enum_Loc); +- strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 3'RD STRING"); +- Int_2_Loc = Run_Index; +- Int_Glob = Run_Index; +- } +- } +- /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */ +- Int_2_Loc = Int_2_Loc * Int_1_Loc; +- Int_1_Loc = Int_2_Loc / Int_3_Loc; +- Int_2_Loc = 7 * (Int_2_Loc - Int_3_Loc) - Int_1_Loc; +- /* Int_1_Loc == 1, Int_2_Loc == 13, Int_3_Loc == 7 */ +- Proc_2 (&Int_1_Loc); +- /* Int_1_Loc == 5 */ +- +- } /* loop "for Run_Index" */ +- +- /**************/ +- /* Stop timer */ +- /**************/ +- +-#ifdef TIMES +- times (&time_info); +- End_Time = (long) time_info.tms_utime; +-#endif +-#ifdef TIME +- End_Time = time ( (long *) 0); +-#endif +- +- printf ("Execution ends\n"); +- printf ("\n"); +- printf ("Final values of the variables used in the benchmark:\n"); +- printf ("\n"); +- printf ("Int_Glob: %d\n", Int_Glob); +- printf (" should be: %d\n", 5); +- printf ("Bool_Glob: %d\n", Bool_Glob); +- printf (" should be: %d\n", 1); +- printf ("Ch_1_Glob: %c\n", Ch_1_Glob); +- printf (" should be: %c\n", 'A'); +- printf ("Ch_2_Glob: %c\n", Ch_2_Glob); +- printf (" should be: %c\n", 'B'); +- printf ("Arr_1_Glob[8]: %d\n", Arr_1_Glob[8]); +- printf (" should be: %d\n", 7); +- printf ("Arr_2_Glob[8][7]: %d\n", Arr_2_Glob[8][7]); +- printf (" should be: Number_Of_Runs + 10\n"); +- printf ("Ptr_Glob->\n"); +- printf (" Ptr_Comp: %d\n", (int) Ptr_Glob->Ptr_Comp); +- printf (" should be: (implementation-dependent)\n"); +- printf (" Discr: %d\n", Ptr_Glob->Discr); +- printf (" should be: %d\n", 0); +- printf (" Enum_Comp: %d\n", Ptr_Glob->variant.var_1.Enum_Comp); +- printf (" should be: %d\n", 2); +- printf (" Int_Comp: %d\n", Ptr_Glob->variant.var_1.Int_Comp); +- printf (" should be: %d\n", 17); +- printf (" Str_Comp: %s\n", Ptr_Glob->variant.var_1.Str_Comp); +- printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n"); +- printf ("Next_Ptr_Glob->\n"); +- printf (" Ptr_Comp: %d\n", (int) Next_Ptr_Glob->Ptr_Comp); +- printf (" should be: (implementation-dependent), same as above\n"); +- printf (" Discr: %d\n", Next_Ptr_Glob->Discr); +- printf (" should be: %d\n", 0); +- printf (" Enum_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Enum_Comp); +- printf (" should be: %d\n", 1); +- printf (" Int_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Int_Comp); +- printf (" should be: %d\n", 18); +- printf (" Str_Comp: %s\n", +- Next_Ptr_Glob->variant.var_1.Str_Comp); +- printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n"); +- printf ("Int_1_Loc: %d\n", Int_1_Loc); +- printf (" should be: %d\n", 5); +- printf ("Int_2_Loc: %d\n", Int_2_Loc); +- printf (" should be: %d\n", 13); +- printf ("Int_3_Loc: %d\n", Int_3_Loc); +- printf (" should be: %d\n", 7); +- printf ("Enum_Loc: %d\n", Enum_Loc); +- printf (" should be: %d\n", 1); +- printf ("Str_1_Loc: %s\n", Str_1_Loc); +- printf (" should be: DHRYSTONE PROGRAM, 1'ST STRING\n"); +- printf ("Str_2_Loc: %s\n", Str_2_Loc); +- printf (" should be: DHRYSTONE PROGRAM, 2'ND STRING\n"); +- printf ("\n"); +- +- User_Time = End_Time - Begin_Time; +- +- if (User_Time < Too_Small_Time) +- { +- printf ("Measured time too small to obtain meaningful results\n"); +- printf ("Please increase number of runs\n"); +- printf ("\n"); +- } +- else +- { +-#ifdef TIME +- Microseconds = (float) User_Time * Mic_secs_Per_Second +- / (float) Number_Of_Runs; +- Dhrystones_Per_Second = (float) Number_Of_Runs / (float) User_Time; +-#else +- Microseconds = (float) User_Time * Mic_secs_Per_Second +- / ((float) HZ * ((float) Number_Of_Runs)); +- Dhrystones_Per_Second = ((float) HZ * (float) Number_Of_Runs) +- / (float) User_Time; +-#endif +- printf ("Microseconds for one run through Dhrystone: "); +- printf ("%6.1f \n", Microseconds); +- printf ("Dhrystones per Second: "); +- printf ("%6.1f \n", Dhrystones_Per_Second); +- printf ("\n"); +- } +- +-} +- +- +-Proc_1 (Ptr_Val_Par) +-/******************/ +- +-REG Rec_Pointer Ptr_Val_Par; +- /* executed once */ +-{ +- REG Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp; +- /* == Ptr_Glob_Next */ +- /* Local variable, initialized with Ptr_Val_Par->Ptr_Comp, */ +- /* corresponds to "rename" in Ada, "with" in Pascal */ +- +- structassign (*Ptr_Val_Par->Ptr_Comp, *Ptr_Glob); +- Ptr_Val_Par->variant.var_1.Int_Comp = 5; +- Next_Record->variant.var_1.Int_Comp +- = Ptr_Val_Par->variant.var_1.Int_Comp; +- Next_Record->Ptr_Comp = Ptr_Val_Par->Ptr_Comp; +- Proc_3 (&Next_Record->Ptr_Comp); +- /* Ptr_Val_Par->Ptr_Comp->Ptr_Comp +- == Ptr_Glob->Ptr_Comp */ +- if (Next_Record->Discr == Ident_1) +- /* then, executed */ +- { +- Next_Record->variant.var_1.Int_Comp = 6; +- Proc_6 (Ptr_Val_Par->variant.var_1.Enum_Comp, +- &Next_Record->variant.var_1.Enum_Comp); +- Next_Record->Ptr_Comp = Ptr_Glob->Ptr_Comp; +- Proc_7 (Next_Record->variant.var_1.Int_Comp, 10, +- &Next_Record->variant.var_1.Int_Comp); +- } +- else /* not executed */ +- structassign (*Ptr_Val_Par, *Ptr_Val_Par->Ptr_Comp); +-} /* Proc_1 */ +- +- +-Proc_2 (Int_Par_Ref) +-/******************/ +- /* executed once */ +- /* *Int_Par_Ref == 1, becomes 4 */ +- +-One_Fifty *Int_Par_Ref; +-{ +- One_Fifty Int_Loc; +- Enumeration Enum_Loc; +- +- Int_Loc = *Int_Par_Ref + 10; +- do /* executed once */ +- if (Ch_1_Glob == 'A') +- /* then, executed */ +- { +- Int_Loc -= 1; +- *Int_Par_Ref = Int_Loc - Int_Glob; +- Enum_Loc = Ident_1; +- } /* if */ +- while (Enum_Loc != Ident_1); /* true */ +-} /* Proc_2 */ +- +- +-Proc_3 (Ptr_Ref_Par) +-/******************/ +- /* executed once */ +- /* Ptr_Ref_Par becomes Ptr_Glob */ +- +-Rec_Pointer *Ptr_Ref_Par; +- +-{ +- if (Ptr_Glob != Null) +- /* then, executed */ +- *Ptr_Ref_Par = Ptr_Glob->Ptr_Comp; +- Proc_7 (10, Int_Glob, &Ptr_Glob->variant.var_1.Int_Comp); +-} /* Proc_3 */ +- +- +-Proc_4 () /* without parameters */ +-/*******/ +- /* executed once */ +-{ +- Boolean Bool_Loc; +- +- Bool_Loc = Ch_1_Glob == 'A'; +- Bool_Glob = Bool_Loc | Bool_Glob; +- Ch_2_Glob = 'B'; +-} /* Proc_4 */ +- +- +-Proc_5 () /* without parameters */ +-/*******/ +- /* executed once */ +-{ +- Ch_1_Glob = 'A'; +- Bool_Glob = false; +-} /* Proc_5 */ +- +- +- /* Procedure for the assignment of structures, */ +- /* if the C compiler doesn't support this feature */ +-#ifdef NOSTRUCTASSIGN +-memcpy (d, s, l) +-register char *d; +-register char *s; +-register int l; +-{ +- while (l--) *d++ = *s++; +-} +-#endif +- +- +//GO.SYSIN DD dhry_1.c +echo dhry_2.c 1>&2 +sed >dhry_2.c <<'//GO.SYSIN DD dhry_2.c' 's/^-//' +-/* +- **************************************************************************** +- * +- * "DHRYSTONE" Benchmark Program +- * ----------------------------- +- * +- * Version: C, Version 2.1 +- * +- * File: dhry_2.c (part 3 of 3) +- * +- * Date: May 25, 1988 +- * +- * Author: Reinhold P. Weicker +- * +- **************************************************************************** +- */ +- +-#include "dhry.h" +- +-#ifndef REG +-#define REG +- /* REG becomes defined as empty */ +- /* i.e. no register variables */ +-#endif +- +-extern int Int_Glob; +-extern char Ch_1_Glob; +- +- +-Proc_6 (Enum_Val_Par, Enum_Ref_Par) +-/*********************************/ +- /* executed once */ +- /* Enum_Val_Par == Ident_3, Enum_Ref_Par becomes Ident_2 */ +- +-Enumeration Enum_Val_Par; +-Enumeration *Enum_Ref_Par; +-{ +- *Enum_Ref_Par = Enum_Val_Par; +- if (! Func_3 (Enum_Val_Par)) +- /* then, not executed */ +- *Enum_Ref_Par = Ident_4; +- switch (Enum_Val_Par) +- { +- case Ident_1: +- *Enum_Ref_Par = Ident_1; +- break; +- case Ident_2: +- if (Int_Glob > 100) +- /* then */ +- *Enum_Ref_Par = Ident_1; +- else *Enum_Ref_Par = Ident_4; +- break; +- case Ident_3: /* executed */ +- *Enum_Ref_Par = Ident_2; +- break; +- case Ident_4: break; +- case Ident_5: +- *Enum_Ref_Par = Ident_3; +- break; +- } /* switch */ +-} /* Proc_6 */ +- +- +-Proc_7 (Int_1_Par_Val, Int_2_Par_Val, Int_Par_Ref) +-/**********************************************/ +- /* executed three times */ +- /* first call: Int_1_Par_Val == 2, Int_2_Par_Val == 3, */ +- /* Int_Par_Ref becomes 7 */ +- /* second call: Int_1_Par_Val == 10, Int_2_Par_Val == 5, */ +- /* Int_Par_Ref becomes 17 */ +- /* third call: Int_1_Par_Val == 6, Int_2_Par_Val == 10, */ +- /* Int_Par_Ref becomes 18 */ +-One_Fifty Int_1_Par_Val; +-One_Fifty Int_2_Par_Val; +-One_Fifty *Int_Par_Ref; +-{ +- One_Fifty Int_Loc; +- +- Int_Loc = Int_1_Par_Val + 2; +- *Int_Par_Ref = Int_2_Par_Val + Int_Loc; +-} /* Proc_7 */ +- +- +-Proc_8 (Arr_1_Par_Ref, Arr_2_Par_Ref, Int_1_Par_Val, Int_2_Par_Val) +-/*********************************************************************/ +- /* executed once */ +- /* Int_Par_Val_1 == 3 */ +- /* Int_Par_Val_2 == 7 */ +-Arr_1_Dim Arr_1_Par_Ref; +-Arr_2_Dim Arr_2_Par_Ref; +-int Int_1_Par_Val; +-int Int_2_Par_Val; +-{ +- REG One_Fifty Int_Index; +- REG One_Fifty Int_Loc; +- +- Int_Loc = Int_1_Par_Val + 5; +- Arr_1_Par_Ref [Int_Loc] = Int_2_Par_Val; +- Arr_1_Par_Ref [Int_Loc+1] = Arr_1_Par_Ref [Int_Loc]; +- Arr_1_Par_Ref [Int_Loc+30] = Int_Loc; +- for (Int_Index = Int_Loc; Int_Index <= Int_Loc+1; ++Int_Index) +- Arr_2_Par_Ref [Int_Loc] [Int_Index] = Int_Loc; +- Arr_2_Par_Ref [Int_Loc] [Int_Loc-1] += 1; +- Arr_2_Par_Ref [Int_Loc+20] [Int_Loc] = Arr_1_Par_Ref [Int_Loc]; +- Int_Glob = 5; +-} /* Proc_8 */ +- +- +-Enumeration Func_1 (Ch_1_Par_Val, Ch_2_Par_Val) +-/*************************************************/ +- /* executed three times */ +- /* first call: Ch_1_Par_Val == 'H', Ch_2_Par_Val == 'R' */ +- /* second call: Ch_1_Par_Val == 'A', Ch_2_Par_Val == 'C' */ +- /* third call: Ch_1_Par_Val == 'B', Ch_2_Par_Val == 'C' */ +- +-Capital_Letter Ch_1_Par_Val; +-Capital_Letter Ch_2_Par_Val; +-{ +- Capital_Letter Ch_1_Loc; +- Capital_Letter Ch_2_Loc; +- +- Ch_1_Loc = Ch_1_Par_Val; +- Ch_2_Loc = Ch_1_Loc; +- if (Ch_2_Loc != Ch_2_Par_Val) +- /* then, executed */ +- return (Ident_1); +- else /* not executed */ +- { +- Ch_1_Glob = Ch_1_Loc; +- return (Ident_2); +- } +-} /* Func_1 */ +- +- +-Boolean Func_2 (Str_1_Par_Ref, Str_2_Par_Ref) +-/*************************************************/ +- /* executed once */ +- /* Str_1_Par_Ref == "DHRYSTONE PROGRAM, 1'ST STRING" */ +- /* Str_2_Par_Ref == "DHRYSTONE PROGRAM, 2'ND STRING" */ +- +-Str_30 Str_1_Par_Ref; +-Str_30 Str_2_Par_Ref; +-{ +- REG One_Thirty Int_Loc; +- Capital_Letter Ch_Loc; +- +- Int_Loc = 2; +- while (Int_Loc <= 2) /* loop body executed once */ +- if (Func_1 (Str_1_Par_Ref[Int_Loc], +- Str_2_Par_Ref[Int_Loc+1]) == Ident_1) +- /* then, executed */ +- { +- Ch_Loc = 'A'; +- Int_Loc += 1; +- } /* if, while */ +- if (Ch_Loc >= 'W' && Ch_Loc < 'Z') +- /* then, not executed */ +- Int_Loc = 7; +- if (Ch_Loc == 'R') +- /* then, not executed */ +- return (true); +- else /* executed */ +- { +- if (strcmp (Str_1_Par_Ref, Str_2_Par_Ref) > 0) +- /* then, not executed */ +- { +- Int_Loc += 7; +- Int_Glob = Int_Loc; +- return (true); +- } +- else /* executed */ +- return (false); +- } /* if Ch_Loc */ +-} /* Func_2 */ +- +- +-Boolean Func_3 (Enum_Par_Val) +-/***************************/ +- /* executed once */ +- /* Enum_Par_Val == Ident_3 */ +-Enumeration Enum_Par_Val; +-{ +- Enumeration Enum_Loc; +- +- Enum_Loc = Enum_Par_Val; +- if (Enum_Loc == Ident_3) +- /* then, executed */ +- return (true); +- else /* not executed */ +- return (false); +-} /* Func_3 */ +- +//GO.SYSIN DD dhry_2.c +echo dhry_c.dif 1>&2 +sed >dhry_c.dif <<'//GO.SYSIN DD dhry_c.dif' 's/^-//' +-7c7 +-< * Version: C, Version 2.1 +---- +-> * Version: C, Version 2.0 +-9c9 +-< * File: dhry.h (part 1 of 3) +---- +-> * File: dhry_global.h (part 1 of 3) +-11c11 +-< * Date: May 25, 1988 +---- +-> * Date: March 3, 1988 +-30c30 +-< * In addition, Berkeley UNIX system calls "times ()" or "time ()" +---- +-> * In addition, UNIX system calls "times ()" or "time ()" +-44c44 +-< * Please send results to Rick Richardson and/or Reinhold Weicker. +---- +-> * Please send results to Reinhold Weicker and/or Rick Richardson. +-59c59 +-< * History: This version C/2.1 has been made for two reasons: +---- +-> * History: This version C/2.0 has been made for two reasons: +-123,129d122 +-< * Version 2.1 is identical to version 2.0 distributed via +-< * the UNIX network Usenet in March 1988 except that it corrects +-< * some minor deficiencies that were found by users of version 2.0. +-< * The only change within the measurement loop is that a +-< * non-executed "else" part was added to the "if" statement in +-< * Func_3, and a non-executed "else" part removed from Proc_3. +-< * +-165,167c158,160 +-< * -DHZ=nnn +-< * In Berkeley UNIX, the function "times" returns process +-< * time in 1/HZ seconds, with HZ = 60 for most systems. +---- +-> * -DHZ=nnn (default: 60) +-> * The function "times" returns process times in +-> * 1/HZ seconds, with HZ = 60 for most systems. +-169c162 +-< * A VALUE. +---- +-> * THE DEFAULT VALUE. +-176,178c169,171 +-< * - dhry.h (this file, containing global definitions and comments) +-< * - dhry_1.c (containing the code corresponding to Ada package Pack_1) +-< * - dhry_2.c (containing the code corresponding to Ada package Pack_2) +---- +-> * - dhry_global.h (this file, containing global definitions and comments) +-> * - dhry_pack_1.c (containing the code corresponding to Ada package Pack_1) +-> * - dhry_pack_2.c (containing the code corresponding to Ada package Pack_2) +-350a344 +-> #ifndef TIMES +-353,354c347,354 +-< /* Use times(2) time function unless */ +-< /* explicitly defined otherwise */ +---- +-> #endif +-> /* Use "times" function for measurement */ +-> /* unless explicitly defined otherwise */ +-> #ifndef HZ +-> #define HZ 60 +-> #endif +-> /* Use HZ = 60 for "times" function */ +-> /* unless explicitly defined otherwise */ +-363c363 +-< /* Berkeley UNIX C returns process times in seconds/HZ */ +---- +-> /* UNIX C returns process times in seconds/HZ */ +-7c7 +-< * Version: C, Version 2.1 +---- +-> * Version: C, Version 2.0 +-9c9 +-< * File: dhry_1.c (part 2 of 3) +---- +-> * File: dhry_pack_1.c (part 2 of 3) +-11c11 +-< * Date: May 25, 1988 +---- +-> * Date: March 3, 1988 +-18c18 +-< #include "dhry.h" +---- +-> #include "dhry_global.h" +-50,51d49 +-< #define Too_Small_Time 120 +-< /* Measurements should last at least about 2 seconds */ +-55a54,55 +-> #endif +-> +-58d57 +-< #endif +-73a73 +-> +-84a85 +-> +-99,100c100,102 +-< /* Was missing in published program. Without this statement, */ +-< /* Arr_2_Glob [8][7] would have an undefined value. */ +---- +-> /* Was missing in published program. Without this */ +-> /* initialization, Arr_2_Glob [8][7] would have an */ +-> /* undefined value. */ +-105c107 +-< printf ("Dhrystone Benchmark, Version 2.1 (Language: C)\n"); +---- +-> printf ("Dhrystone Benchmark, Version 2.0 (Language: C)\n"); +-281c283 +-< /******************/ +---- +-> /**********************/ +-338c340 +-< /******************/ +---- +-> /**********************/ +-347a350,351 +-> else /* not executed */ +-> Int_Glob = 100; +-349a354 +-> +-7c7 +-< * Version: C, Version 2.1 +---- +-> * Version: C, Version 2.0 +-9c9 +-< * File: dhry_2.c (part 3 of 3) +---- +-> * File: dhry_pack_2.c (part 3 of 3) +-11c11 +-< * Date: May 25, 1988 +---- +-> * Date: March 3, 1988 +-18c18 +-< #include "dhry.h" +---- +-> #include "dhry_global.h" +-189,190d188 +-< else /* not executed */ +-< return (false); +//GO.SYSIN DD dhry_c.dif +echo submit.frm 1>&2 +sed >submit.frm <<'//GO.SYSIN DD submit.frm' 's/^-//' +-DHRYSTONE 2.1 BENCHMARK REPORTING FORM +-MANUF: +-MODEL: +-PROC: +-CLOCK: +-OS: +-OVERSION: +-COMPILER: +-CVERSION: +-OPTIONS: +-NOREG: +-REG: +-NOTES: +-DATE: +-SUBMITTER: +-CODESIZE: +-MAILTO: uunet!pcrat!dry2 +//GO.SYSIN DD submit.frm diff --git a/zpu/roadshow/roadshow/dhrystone/dhry.h b/zpu/roadshow/roadshow/dhrystone/dhry.h new file mode 100644 index 0000000..211c2e2 --- /dev/null +++ b/zpu/roadshow/roadshow/dhrystone/dhry.h @@ -0,0 +1,423 @@ +/* + **************************************************************************** + * + * "DHRYSTONE" Benchmark Program + * ----------------------------- + * + * Version: C, Version 2.1 + * + * File: dhry.h (part 1 of 3) + * + * Date: May 25, 1988 + * + * Author: Reinhold P. Weicker + * Siemens AG, AUT E 51 + * Postfach 3220 + * 8520 Erlangen + * Germany (West) + * Phone: [+49]-9131-7-20330 + * (8-17 Central European Time) + * Usenet: ..!mcsun!unido!estevax!weicker + * + * Original Version (in Ada) published in + * "Communications of the ACM" vol. 27., no. 10 (Oct. 1984), + * pp. 1013 - 1030, together with the statistics + * on which the distribution of statements etc. is based. + * + * In this C version, the following C library functions are used: + * - strcpy, strcmp (inside the measurement loop) + * - printf, scanf (outside the measurement loop) + * In addition, Berkeley UNIX system calls "times ()" or "time ()" + * are used for execution time measurement. For measurements + * on other systems, these calls have to be changed. + * + * Collection of Results: + * Reinhold Weicker (address see above) and + * + * Rick Richardson + * PC Research. Inc. + * 94 Apple Orchard Drive + * Tinton Falls, NJ 07724 + * Phone: (201) 389-8963 (9-17 EST) + * Usenet: ...!uunet!pcrat!rick + * + * Please send results to Rick Richardson and/or Reinhold Weicker. + * Complete information should be given on hardware and software used. + * Hardware information includes: Machine type, CPU, type and size + * of caches; for microprocessors: clock frequency, memory speed + * (number of wait states). + * Software information includes: Compiler (and runtime library) + * manufacturer and version, compilation switches, OS version. + * The Operating System version may give an indication about the + * compiler; Dhrystone itself performs no OS calls in the measurement loop. + * + * The complete output generated by the program should be mailed + * such that at least some checks for correctness can be made. + * + *************************************************************************** + * + * History: This version C/2.1 has been made for two reasons: + * + * 1) There is an obvious need for a common C version of + * Dhrystone, since C is at present the most popular system + * programming language for the class of processors + * (microcomputers, minicomputers) where Dhrystone is used most. + * There should be, as far as possible, only one C version of + * Dhrystone such that results can be compared without + * restrictions. In the past, the C versions distributed + * by Rick Richardson (Version 1.1) and by Reinhold Weicker + * had small (though not significant) differences. + * + * 2) As far as it is possible without changes to the Dhrystone + * statistics, optimizing compilers should be prevented from + * removing significant statements. + * + * This C version has been developed in cooperation with + * Rick Richardson (Tinton Falls, NJ), it incorporates many + * ideas from the "Version 1.1" distributed previously by + * him over the UNIX network Usenet. + * I also thank Chaim Benedelac (National Semiconductor), + * David Ditzel (SUN), Earl Killian and John Mashey (MIPS), + * Alan Smith and Rafael Saavedra-Barrera (UC at Berkeley) + * for their help with comments on earlier versions of the + * benchmark. + * + * Changes: In the initialization part, this version follows mostly + * Rick Richardson's version distributed via Usenet, not the + * version distributed earlier via floppy disk by Reinhold Weicker. + * As a concession to older compilers, names have been made + * unique within the first 8 characters. + * Inside the measurement loop, this version follows the + * version previously distributed by Reinhold Weicker. + * + * At several places in the benchmark, code has been added, + * but within the measurement loop only in branches that + * are not executed. The intention is that optimizing compilers + * should be prevented from moving code out of the measurement + * loop, or from removing code altogether. Since the statements + * that are executed within the measurement loop have NOT been + * changed, the numbers defining the "Dhrystone distribution" + * (distribution of statements, operand types and locality) + * still hold. Except for sophisticated optimizing compilers, + * execution times for this version should be the same as + * for previous versions. + * + * Since it has proven difficult to subtract the time for the + * measurement loop overhead in a correct way, the loop check + * has been made a part of the benchmark. This does have + * an impact - though a very minor one - on the distribution + * statistics which have been updated for this version. + * + * All changes within the measurement loop are described + * and discussed in the companion paper "Rationale for + * Dhrystone version 2". + * + * Because of the self-imposed limitation that the order and + * distribution of the executed statements should not be + * changed, there are still cases where optimizing compilers + * may not generate code for some statements. To a certain + * degree, this is unavoidable for small synthetic benchmarks. + * Users of the benchmark are advised to check code listings + * whether code is generated for all statements of Dhrystone. + * + * Version 2.1 is identical to version 2.0 distributed via + * the UNIX network Usenet in March 1988 except that it corrects + * some minor deficiencies that were found by users of version 2.0. + * The only change within the measurement loop is that a + * non-executed "else" part was added to the "if" statement in + * Func_3, and a non-executed "else" part removed from Proc_3. + * + *************************************************************************** + * + * Defines: The following "Defines" are possible: + * -DREG=register (default: Not defined) + * As an approximation to what an average C programmer + * might do, the "register" storage class is applied + * (if enabled by -DREG=register) + * - for local variables, if they are used (dynamically) + * five or more times + * - for parameters if they are used (dynamically) + * six or more times + * Note that an optimal "register" strategy is + * compiler-dependent, and that "register" declarations + * do not necessarily lead to faster execution. + * -DNOSTRUCTASSIGN (default: Not defined) + * Define if the C compiler does not support + * assignment of structures. + * -DNOENUMS (default: Not defined) + * Define if the C compiler does not support + * enumeration types. + * -DTIMES (default) + * -DTIME + * The "times" function of UNIX (returning process times) + * or the "time" function (returning wallclock time) + * is used for measurement. + * For single user machines, "time ()" is adequate. For + * multi-user machines where you cannot get single-user + * access, use the "times ()" function. If you have + * neither, use a stopwatch in the dead of night. + * "printf"s are provided marking the points "Start Timer" + * and "Stop Timer". DO NOT use the UNIX "time(1)" + * command, as this will measure the total time to + * run this program, which will (erroneously) include + * the time to allocate storage (malloc) and to perform + * the initialization. + * -DHZ=nnn + * In Berkeley UNIX, the function "times" returns process + * time in 1/HZ seconds, with HZ = 60 for most systems. + * CHECK YOUR SYSTEM DESCRIPTION BEFORE YOU JUST APPLY + * A VALUE. + * + *************************************************************************** + * + * Compilation model and measurement (IMPORTANT): + * + * This C version of Dhrystone consists of three files: + * - dhry.h (this file, containing global definitions and comments) + * - dhry_1.c (containing the code corresponding to Ada package Pack_1) + * - dhry_2.c (containing the code corresponding to Ada package Pack_2) + * + * The following "ground rules" apply for measurements: + * - Separate compilation + * - No procedure merging + * - Otherwise, compiler optimizations are allowed but should be indicated + * - Default results are those without register declarations + * See the companion paper "Rationale for Dhrystone Version 2" for a more + * detailed discussion of these ground rules. + * + * For 16-Bit processors (e.g. 80186, 80286), times for all compilation + * models ("small", "medium", "large" etc.) should be given if possible, + * together with a definition of these models for the compiler system used. + * + ************************************************************************** + * + * Dhrystone (C version) statistics: + * + * [Comment from the first distribution, updated for version 2. + * Note that because of language differences, the numbers are slightly + * different from the Ada version.] + * + * The following program contains statements of a high level programming + * language (here: C) in a distribution considered representative: + * + * assignments 52 (51.0 %) + * control statements 33 (32.4 %) + * procedure, function calls 17 (16.7 %) + * + * 103 statements are dynamically executed. The program is balanced with + * respect to the three aspects: + * + * - statement type + * - operand type + * - operand locality + * operand global, local, parameter, or constant. + * + * The combination of these three aspects is balanced only approximately. + * + * 1. Statement Type: + * ----------------- number + * + * V1 = V2 9 + * (incl. V1 = F(..) + * V = Constant 12 + * Assignment, 7 + * with array element + * Assignment, 6 + * with record component + * -- + * 34 34 + * + * X = Y +|-|"&&"|"|" Z 5 + * X = Y +|-|"==" Constant 6 + * X = X +|- 1 3 + * X = Y *|/ Z 2 + * X = Expression, 1 + * two operators + * X = Expression, 1 + * three operators + * -- + * 18 18 + * + * if .... 14 + * with "else" 7 + * without "else" 7 + * executed 3 + * not executed 4 + * for ... 7 | counted every time + * while ... 4 | the loop condition + * do ... while 1 | is evaluated + * switch ... 1 + * break 1 + * declaration with 1 + * initialization + * -- + * 34 34 + * + * P (...) procedure call 11 + * user procedure 10 + * library procedure 1 + * X = F (...) + * function call 6 + * user function 5 + * library function 1 + * -- + * 17 17 + * --- + * 103 + * + * The average number of parameters in procedure or function calls + * is 1.82 (not counting the function values as implicit parameters). + * + * + * 2. Operators + * ------------ + * number approximate + * percentage + * + * Arithmetic 32 50.8 + * + * + 21 33.3 + * - 7 11.1 + * * 3 4.8 + * / (int div) 1 1.6 + * + * Comparison 27 42.8 + * + * == 9 14.3 + * /= 4 6.3 + * > 1 1.6 + * < 3 4.8 + * >= 1 1.6 + * <= 9 14.3 + * + * Logic 4 6.3 + * + * && (AND-THEN) 1 1.6 + * | (OR) 1 1.6 + * ! (NOT) 2 3.2 + * + * -- ----- + * 63 100.1 + * + * + * 3. Operand Type (counted once per operand reference): + * --------------- + * number approximate + * percentage + * + * Integer 175 72.3 % + * Character 45 18.6 % + * Pointer 12 5.0 % + * String30 6 2.5 % + * Array 2 0.8 % + * Record 2 0.8 % + * --- ------- + * 242 100.0 % + * + * When there is an access path leading to the final operand (e.g. a record + * component), only the final data type on the access path is counted. + * + * + * 4. Operand Locality: + * ------------------- + * number approximate + * percentage + * + * local variable 114 47.1 % + * global variable 22 9.1 % + * parameter 45 18.6 % + * value 23 9.5 % + * reference 22 9.1 % + * function result 6 2.5 % + * constant 55 22.7 % + * --- ------- + * 242 100.0 % + * + * + * The program does not compute anything meaningful, but it is syntactically + * and semantically correct. All variables have a value assigned to them + * before they are used as a source operand. + * + * There has been no explicit effort to account for the effects of a + * cache, or to balance the use of long or short displacements for code or + * data. + * + *************************************************************************** + */ + +/* Compiler and system dependent definitions: */ + +#ifndef TIME +#define TIMES +#endif + /* Use times(2) time function unless */ + /* explicitly defined otherwise */ + +#ifdef TIMES +#include +#include + /* for "times" */ +#endif + +#define Mic_secs_Per_Second 1000000 + /* Berkeley UNIX C returns process times in seconds/HZ */ + +#ifdef NOSTRUCTASSIGN +#define structassign(d, s) memcpy(&(d), &(s), sizeof(d)) +#else +#define structassign(d, s) d = s +#endif + +#ifdef NOENUM +#define Ident_1 0 +#define Ident_2 1 +#define Ident_3 2 +#define Ident_4 3 +#define Ident_5 4 + typedef int Enumeration; +#else + typedef enum {Ident_1, Ident_2, Ident_3, Ident_4, Ident_5} + Enumeration; +#endif + /* for boolean and enumeration types in Ada, Pascal */ + +/* General definitions: */ + +#include + /* for strcpy, strcmp */ + +#define Null 0 + /* Value of a Null pointer */ +#define true 1 +#define false 0 + +typedef int One_Thirty; +typedef int One_Fifty; +typedef char Capital_Letter; +typedef int Boolean; +typedef char Str_30 [31]; +typedef int Arr_1_Dim [50]; +typedef int Arr_2_Dim [50] [50]; + +typedef struct record + { + struct record *Ptr_Comp; + Enumeration Discr; + union { + struct { + Enumeration Enum_Comp; + int Int_Comp; + char Str_Comp [31]; + } var_1; + struct { + Enumeration E_Comp_2; + char Str_2_Comp [31]; + } var_2; + struct { + char Ch_1_Comp; + char Ch_2_Comp; + } var_3; + } variant; + } Rec_Type, *Rec_Pointer; + + diff --git a/zpu/roadshow/roadshow/dhrystone/dhry_1.c b/zpu/roadshow/roadshow/dhrystone/dhry_1.c new file mode 100644 index 0000000..08a29b9 --- /dev/null +++ b/zpu/roadshow/roadshow/dhrystone/dhry_1.c @@ -0,0 +1,533 @@ +/* + **************************************************************************** + * + * "DHRYSTONE" Benchmark Program + * ----------------------------- + * + * Version: C, Version 2.1 + * + * File: dhry_1.c (part 2 of 3) + * + * Date: May 25, 1988 + * + * Author: Reinhold P. Weicker + * + **************************************************************************** + */ + +#include "dhry.h" +#include + +static int +_cvt(int val, char *buf, int radix, char *digits) +{ + char temp[80]; + char *cp = temp; + int length = 0; + + if (val == 0) { + /* Special case */ + *cp++ = '0'; + } else { + while (val) { + *cp++ = digits[val % radix]; + val /= radix; + } + } + while (cp != temp) { + *buf++ = *--cp; + length++; + } + *buf = '\0'; + return (length); +} + +#define is_digit(c) ((c >= '0') && (c <= '9')) + + +#ifndef TINY +static int +_vprintf(void (*putc)(char c, void **param), void **param, const char *fmt, va_list ap) +{ + char buf[sizeof(long long)*8]; + char c, sign, *cp=buf; + int left_prec, right_prec, zero_fill, pad, pad_on_right, + i, islong, islonglong; + long long val = 0; + int res = 0, length = 0; + + while ((c = *fmt++) != '\0') { + if (c == '%') { + c = *fmt++; + left_prec = right_prec = pad_on_right = islong = islonglong = 0; + sign = '\0'; + // Fetch value [numeric descriptors only] + switch (c) { + case 'd': + val = (long long)va_arg(ap, int); + if ((c == 'd') || (c == 'D')) { + if (val < 0) { + sign = '-'; + val = -val; + } + } else { + // Mask to unsigned, sized quantity + if (islong) { + val &= ((long long)1 << (sizeof(long) * 8)) - 1; + } else{ + val &= ((long long)1 << (sizeof(int) * 8)) - 1; + } + } + break; + default: + break; + } + // Process output + switch (c) { + case 'd': + switch (c) { + case 'd': + length = _cvt(val, buf, 10, "0123456789"); + break; + } + cp = buf; + break; + case 's': + cp = va_arg(ap, char *); + length = 0; + while (cp[length] != '\0') length++; + break; + case 'c': + c = va_arg(ap, int /*char*/); + (*putc)(c, param); + res++; + continue; + default: + (*putc)('%', param); + (*putc)(c, param); + res += 2; + continue; + } + while (length-- > 0) { + c = *cp++; + (*putc)(c, param); + res++; + } + } else { + (*putc)(c, param); + res++; + } + } + return (res); +} +#endif + +// Default wrapper function used by diag_printf +static void +_diag_write_char(char c, void **param) +{ + if (c=='\n') + { + outbyte('\r'); + } + outbyte(c); +} + +int +small_printf(const char *fmt, ...) +{ +#ifndef TINY + va_list ap; + int ret; + + va_start(ap, fmt); + ret = _vprintf(_diag_write_char, (void **)0, fmt, ap); + va_end(ap); + return (ret); +#else + return 0; +#endif +} + + + + +/* Global Variables: */ + +Rec_Pointer Ptr_Glob, + Next_Ptr_Glob; +int Int_Glob; +Boolean Bool_Glob; +char Ch_1_Glob, + Ch_2_Glob; +int Arr_1_Glob [50]; +int Arr_2_Glob [50] [50]; + +Enumeration Func_1 (); + /* forward declaration necessary since Enumeration may not simply be int */ + +#ifndef REG + Boolean Reg = false; +#define REG + /* REG becomes defined as empty */ + /* i.e. no register variables */ +#else + Boolean Reg = true; +#endif + +/* variables for time measurement: */ + +#ifdef TIMES +struct tms time_info; + /* see library function "times" */ +#define Too_Small_Time 120 + /* Measurements should last at least about 2 seconds */ +#endif +#ifdef TIME +extern long time(); + /* see library function "time" */ +#define Too_Small_Time 2 + /* Measurements should last at least 2 seconds */ +#endif + +long long Begin_Time, + End_Time, + User_Time; +long long Microseconds, + Dhrystones_Per_Second, + Vax_Mips; + +/* end of variables for time measurement */ + +int Number_Of_Runs = 50000; + +extern long long _readMicroseconds(); + + +int main () +/*****/ + + /* main program, corresponds to procedures */ + /* Main and Proc_0 in the Ada version */ +{ + One_Fifty Int_1_Loc; + REG One_Fifty Int_2_Loc; + One_Fifty Int_3_Loc; + REG char Ch_Index; + Enumeration Enum_Loc; + Str_30 Str_1_Loc; + Str_30 Str_2_Loc; + REG int Run_Index; + + /* Initializations */ + + Next_Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type)); + Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type)); + + Ptr_Glob->Ptr_Comp = Next_Ptr_Glob; + Ptr_Glob->Discr = Ident_1; + Ptr_Glob->variant.var_1.Enum_Comp = Ident_3; + Ptr_Glob->variant.var_1.Int_Comp = 40; + strcpy (Ptr_Glob->variant.var_1.Str_Comp, + "DHRYSTONE PROGRAM, SOME STRING"); + strcpy (Str_1_Loc, "DHRYSTONE PROGRAM, 1'ST STRING"); + + Arr_2_Glob [8][7] = 10; + /* Was missing in published program. Without this statement, */ + /* Arr_2_Glob [8][7] would have an undefined value. */ + /* Warning: With 16-Bit processors and Number_Of_Runs > 32000, */ + /* overflow may occur for this array element. */ + small_printf ("\n"); + small_printf ("Dhrystone Benchmark, Version 2.1 (Language: C)\n"); + small_printf ("\n"); + if (Reg) + { + small_printf ("Program compiled with 'register' attribute\n"); + small_printf ("\n"); + } + else + { + small_printf ("Program compiled without 'register' attribute\n"); + small_printf ("\n"); + } + Number_Of_Runs; + + small_printf ("Execution starts, %d runs through Dhrystone\n", Number_Of_Runs); + + /***************/ + /* Start timer */ + /***************/ + +#if 0 +#ifdef TIMES + times (&time_info); + Begin_Time = (long) time_info.tms_utime; +#endif +#ifdef TIME + Begin_Time = time ( (long *) 0); +#endif +#else + Begin_Time = _readMicroseconds(); +#endif + for (Run_Index = 1; Run_Index <= Number_Of_Runs; ++Run_Index) + { + + Proc_5(); + Proc_4(); + /* Ch_1_Glob == 'A', Ch_2_Glob == 'B', Bool_Glob == true */ + Int_1_Loc = 2; + Int_2_Loc = 3; + strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 2'ND STRING"); + Enum_Loc = Ident_2; + Bool_Glob = ! Func_2 (Str_1_Loc, Str_2_Loc); + /* Bool_Glob == 1 */ + while (Int_1_Loc < Int_2_Loc) /* loop body executed once */ + { + Int_3_Loc = 5 * Int_1_Loc - Int_2_Loc; + /* Int_3_Loc == 7 */ + Proc_7 (Int_1_Loc, Int_2_Loc, &Int_3_Loc); + /* Int_3_Loc == 7 */ + Int_1_Loc += 1; + } /* while */ + /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */ + Proc_8 (Arr_1_Glob, Arr_2_Glob, Int_1_Loc, Int_3_Loc); + /* Int_Glob == 5 */ + Proc_1 (Ptr_Glob); + for (Ch_Index = 'A'; Ch_Index <= Ch_2_Glob; ++Ch_Index) + /* loop body executed twice */ + { + if (Enum_Loc == Func_1 (Ch_Index, 'C')) + /* then, not executed */ + { + Proc_6 (Ident_1, &Enum_Loc); + strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 3'RD STRING"); + Int_2_Loc = Run_Index; + Int_Glob = Run_Index; + } + } + /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */ + Int_2_Loc = Int_2_Loc * Int_1_Loc; + Int_1_Loc = Int_2_Loc / Int_3_Loc; + Int_2_Loc = 7 * (Int_2_Loc - Int_3_Loc) - Int_1_Loc; + /* Int_1_Loc == 1, Int_2_Loc == 13, Int_3_Loc == 7 */ + Proc_2 (&Int_1_Loc); + /* Int_1_Loc == 5 */ + + } /* loop "for Run_Index" */ + + /**************/ + /* Stop timer */ + /**************/ + +#if 0 +#ifdef TIMES + times (&time_info); + End_Time = (long) time_info.tms_utime; +#endif +#ifdef TIME + End_Time = time ( (long *) 0); +#endif +#else + End_Time = _readMicroseconds(); +#endif + + small_printf ("Execution ends\n"); + small_printf ("\n"); + small_printf ("Final values of the variables used in the benchmark:\n"); + small_printf ("\n"); + small_printf ("Int_Glob: %d\n", Int_Glob); + small_printf (" should be: %d\n", 5); + small_printf ("Bool_Glob: %d\n", Bool_Glob); + small_printf (" should be: %d\n", 1); + small_printf ("Ch_1_Glob: %c\n", Ch_1_Glob); + small_printf (" should be: %c\n", 'A'); + small_printf ("Ch_2_Glob: %c\n", Ch_2_Glob); + small_printf (" should be: %c\n", 'B'); + small_printf ("Arr_1_Glob[8]: %d\n", Arr_1_Glob[8]); + small_printf (" should be: %d\n", 7); + small_printf ("Arr_2_Glob[8][7]: %d\n", Arr_2_Glob[8][7]); + small_printf (" should be: Number_Of_Runs + 10\n"); + small_printf ("Ptr_Glob->\n"); + small_printf (" Ptr_Comp: %d\n", (int) Ptr_Glob->Ptr_Comp); + small_printf (" should be: (implementation-dependent)\n"); + small_printf (" Discr: %d\n", Ptr_Glob->Discr); + small_printf (" should be: %d\n", 0); + small_printf (" Enum_Comp: %d\n", Ptr_Glob->variant.var_1.Enum_Comp); + small_printf (" should be: %d\n", 2); + small_printf (" Int_Comp: %d\n", Ptr_Glob->variant.var_1.Int_Comp); + small_printf (" should be: %d\n", 17); + small_printf (" Str_Comp: %s\n", Ptr_Glob->variant.var_1.Str_Comp); + small_printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n"); + small_printf ("Next_Ptr_Glob->\n"); + small_printf (" Ptr_Comp: %d\n", (int) Next_Ptr_Glob->Ptr_Comp); + small_printf (" should be: (implementation-dependent), same as above\n"); + small_printf (" Discr: %d\n", Next_Ptr_Glob->Discr); + small_printf (" should be: %d\n", 0); + small_printf (" Enum_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Enum_Comp); + small_printf (" should be: %d\n", 1); + small_printf (" Int_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Int_Comp); + small_printf (" should be: %d\n", 18); + small_printf (" Str_Comp: %s\n", + Next_Ptr_Glob->variant.var_1.Str_Comp); + small_printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n"); + small_printf ("Int_1_Loc: %d\n", Int_1_Loc); + small_printf (" should be: %d\n", 5); + small_printf ("Int_2_Loc: %d\n", Int_2_Loc); + small_printf (" should be: %d\n", 13); + small_printf ("Int_3_Loc: %d\n", Int_3_Loc); + small_printf (" should be: %d\n", 7); + small_printf ("Enum_Loc: %d\n", Enum_Loc); + small_printf (" should be: %d\n", 1); + small_printf ("Str_1_Loc: %s\n", Str_1_Loc); + small_printf (" should be: DHRYSTONE PROGRAM, 1'ST STRING\n"); + small_printf ("Str_2_Loc: %s\n", Str_2_Loc); + small_printf (" should be: DHRYSTONE PROGRAM, 2'ND STRING\n"); + small_printf ("\n"); + + User_Time = End_Time - Begin_Time; + small_printf ("User time: %d\n", (int)User_Time); + + if (User_Time < Too_Small_Time) + { + small_printf ("Measured time too small to obtain meaningful results\n"); + small_printf ("Please increase number of runs\n"); + small_printf ("\n"); + } +/* else */ + { +#if 0 +#ifdef TIME + Microseconds = (User_Time * Mic_secs_Per_Second ) + / Number_Of_Runs; + Dhrystones_Per_Second = Number_Of_Runs / User_Time; + Vax_Mips = (Number_Of_Runs*1000) / (1757*User_Time); +#else + Microseconds = (float) User_Time * Mic_secs_Per_Second + / ((float) HZ * ((float) Number_Of_Runs)); + Dhrystones_Per_Second = ((float) HZ * (float) Number_Of_Runs) + / (float) User_Time; + Vax_Mips = Dhrystones_Per_Second / 1757.0; +#endif +#else + Microseconds = User_Time / Number_Of_Runs; + Dhrystones_Per_Second = ((long long)Number_Of_Runs*1000000) / User_Time; + Vax_Mips = (((long long)Number_Of_Runs)*1000000000) / (1757*User_Time); +#endif + small_printf ("Microseconds for one run through Dhrystone: "); + small_printf ("%d \n", (int)Microseconds); + small_printf ("Dhrystones per Second: "); + small_printf ("%d \n", (int)Dhrystones_Per_Second); + small_printf ("VAX MIPS rating * 1000 = %d \n",(int)Vax_Mips); + small_printf ("\n"); + } + + return 0; +} + + +Proc_1 (Ptr_Val_Par) +/******************/ + +REG Rec_Pointer Ptr_Val_Par; + /* executed once */ +{ + REG Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp; + /* == Ptr_Glob_Next */ + /* Local variable, initialized with Ptr_Val_Par->Ptr_Comp, */ + /* corresponds to "rename" in Ada, "with" in Pascal */ + + structassign (*Ptr_Val_Par->Ptr_Comp, *Ptr_Glob); + Ptr_Val_Par->variant.var_1.Int_Comp = 5; + Next_Record->variant.var_1.Int_Comp + = Ptr_Val_Par->variant.var_1.Int_Comp; + Next_Record->Ptr_Comp = Ptr_Val_Par->Ptr_Comp; + Proc_3 (&Next_Record->Ptr_Comp); + /* Ptr_Val_Par->Ptr_Comp->Ptr_Comp + == Ptr_Glob->Ptr_Comp */ + if (Next_Record->Discr == Ident_1) + /* then, executed */ + { + Next_Record->variant.var_1.Int_Comp = 6; + Proc_6 (Ptr_Val_Par->variant.var_1.Enum_Comp, + &Next_Record->variant.var_1.Enum_Comp); + Next_Record->Ptr_Comp = Ptr_Glob->Ptr_Comp; + Proc_7 (Next_Record->variant.var_1.Int_Comp, 10, + &Next_Record->variant.var_1.Int_Comp); + } + else /* not executed */ + structassign (*Ptr_Val_Par, *Ptr_Val_Par->Ptr_Comp); +} /* Proc_1 */ + + +Proc_2 (Int_Par_Ref) +/******************/ + /* executed once */ + /* *Int_Par_Ref == 1, becomes 4 */ + +One_Fifty *Int_Par_Ref; +{ + One_Fifty Int_Loc; + Enumeration Enum_Loc; + + Int_Loc = *Int_Par_Ref + 10; + do /* executed once */ + if (Ch_1_Glob == 'A') + /* then, executed */ + { + Int_Loc -= 1; + *Int_Par_Ref = Int_Loc - Int_Glob; + Enum_Loc = Ident_1; + } /* if */ + while (Enum_Loc != Ident_1); /* true */ +} /* Proc_2 */ + + +Proc_3 (Ptr_Ref_Par) +/******************/ + /* executed once */ + /* Ptr_Ref_Par becomes Ptr_Glob */ + +Rec_Pointer *Ptr_Ref_Par; + +{ + if (Ptr_Glob != Null) + /* then, executed */ + *Ptr_Ref_Par = Ptr_Glob->Ptr_Comp; + Proc_7 (10, Int_Glob, &Ptr_Glob->variant.var_1.Int_Comp); +} /* Proc_3 */ + + +Proc_4 () /* without parameters */ +/*******/ + /* executed once */ +{ + Boolean Bool_Loc; + + Bool_Loc = Ch_1_Glob == 'A'; + Bool_Glob = Bool_Loc | Bool_Glob; + Ch_2_Glob = 'B'; +} /* Proc_4 */ + + +Proc_5 () /* without parameters */ +/*******/ + /* executed once */ +{ + Ch_1_Glob = 'A'; + Bool_Glob = false; +} /* Proc_5 */ + + + /* Procedure for the assignment of structures, */ + /* if the C compiler doesn't support this feature */ +#ifdef NOSTRUCTASSIGN +memcpy (d, s, l) +register char *d; +register char *s; +register int l; +{ + while (l--) *d++ = *s++; +} +#endif + + diff --git a/zpu/roadshow/roadshow/dhrystone/dhry_2.c b/zpu/roadshow/roadshow/dhrystone/dhry_2.c new file mode 100644 index 0000000..ed0e5b7 --- /dev/null +++ b/zpu/roadshow/roadshow/dhrystone/dhry_2.c @@ -0,0 +1,192 @@ +/* + **************************************************************************** + * + * "DHRYSTONE" Benchmark Program + * ----------------------------- + * + * Version: C, Version 2.1 + * + * File: dhry_2.c (part 3 of 3) + * + * Date: May 25, 1988 + * + * Author: Reinhold P. Weicker + * + **************************************************************************** + */ + +#include "dhry.h" + +#ifndef REG +#define REG + /* REG becomes defined as empty */ + /* i.e. no register variables */ +#endif + +extern int Int_Glob; +extern char Ch_1_Glob; + + +Proc_6 (Enum_Val_Par, Enum_Ref_Par) +/*********************************/ + /* executed once */ + /* Enum_Val_Par == Ident_3, Enum_Ref_Par becomes Ident_2 */ + +Enumeration Enum_Val_Par; +Enumeration *Enum_Ref_Par; +{ + *Enum_Ref_Par = Enum_Val_Par; + if (! Func_3 (Enum_Val_Par)) + /* then, not executed */ + *Enum_Ref_Par = Ident_4; + switch (Enum_Val_Par) + { + case Ident_1: + *Enum_Ref_Par = Ident_1; + break; + case Ident_2: + if (Int_Glob > 100) + /* then */ + *Enum_Ref_Par = Ident_1; + else *Enum_Ref_Par = Ident_4; + break; + case Ident_3: /* executed */ + *Enum_Ref_Par = Ident_2; + break; + case Ident_4: break; + case Ident_5: + *Enum_Ref_Par = Ident_3; + break; + } /* switch */ +} /* Proc_6 */ + + +Proc_7 (Int_1_Par_Val, Int_2_Par_Val, Int_Par_Ref) +/**********************************************/ + /* executed three times */ + /* first call: Int_1_Par_Val == 2, Int_2_Par_Val == 3, */ + /* Int_Par_Ref becomes 7 */ + /* second call: Int_1_Par_Val == 10, Int_2_Par_Val == 5, */ + /* Int_Par_Ref becomes 17 */ + /* third call: Int_1_Par_Val == 6, Int_2_Par_Val == 10, */ + /* Int_Par_Ref becomes 18 */ +One_Fifty Int_1_Par_Val; +One_Fifty Int_2_Par_Val; +One_Fifty *Int_Par_Ref; +{ + One_Fifty Int_Loc; + + Int_Loc = Int_1_Par_Val + 2; + *Int_Par_Ref = Int_2_Par_Val + Int_Loc; +} /* Proc_7 */ + + +Proc_8 (Arr_1_Par_Ref, Arr_2_Par_Ref, Int_1_Par_Val, Int_2_Par_Val) +/*********************************************************************/ + /* executed once */ + /* Int_Par_Val_1 == 3 */ + /* Int_Par_Val_2 == 7 */ +Arr_1_Dim Arr_1_Par_Ref; +Arr_2_Dim Arr_2_Par_Ref; +int Int_1_Par_Val; +int Int_2_Par_Val; +{ + REG One_Fifty Int_Index; + REG One_Fifty Int_Loc; + + Int_Loc = Int_1_Par_Val + 5; + Arr_1_Par_Ref [Int_Loc] = Int_2_Par_Val; + Arr_1_Par_Ref [Int_Loc+1] = Arr_1_Par_Ref [Int_Loc]; + Arr_1_Par_Ref [Int_Loc+30] = Int_Loc; + for (Int_Index = Int_Loc; Int_Index <= Int_Loc+1; ++Int_Index) + Arr_2_Par_Ref [Int_Loc] [Int_Index] = Int_Loc; + Arr_2_Par_Ref [Int_Loc] [Int_Loc-1] += 1; + Arr_2_Par_Ref [Int_Loc+20] [Int_Loc] = Arr_1_Par_Ref [Int_Loc]; + Int_Glob = 5; +} /* Proc_8 */ + + +Enumeration Func_1 (Ch_1_Par_Val, Ch_2_Par_Val) +/*************************************************/ + /* executed three times */ + /* first call: Ch_1_Par_Val == 'H', Ch_2_Par_Val == 'R' */ + /* second call: Ch_1_Par_Val == 'A', Ch_2_Par_Val == 'C' */ + /* third call: Ch_1_Par_Val == 'B', Ch_2_Par_Val == 'C' */ + +Capital_Letter Ch_1_Par_Val; +Capital_Letter Ch_2_Par_Val; +{ + Capital_Letter Ch_1_Loc; + Capital_Letter Ch_2_Loc; + + Ch_1_Loc = Ch_1_Par_Val; + Ch_2_Loc = Ch_1_Loc; + if (Ch_2_Loc != Ch_2_Par_Val) + /* then, executed */ + return (Ident_1); + else /* not executed */ + { + Ch_1_Glob = Ch_1_Loc; + return (Ident_2); + } +} /* Func_1 */ + + +Boolean Func_2 (Str_1_Par_Ref, Str_2_Par_Ref) +/*************************************************/ + /* executed once */ + /* Str_1_Par_Ref == "DHRYSTONE PROGRAM, 1'ST STRING" */ + /* Str_2_Par_Ref == "DHRYSTONE PROGRAM, 2'ND STRING" */ + +Str_30 Str_1_Par_Ref; +Str_30 Str_2_Par_Ref; +{ + REG One_Thirty Int_Loc; + Capital_Letter Ch_Loc; + + Int_Loc = 2; + while (Int_Loc <= 2) /* loop body executed once */ + if (Func_1 (Str_1_Par_Ref[Int_Loc], + Str_2_Par_Ref[Int_Loc+1]) == Ident_1) + /* then, executed */ + { + Ch_Loc = 'A'; + Int_Loc += 1; + } /* if, while */ + if (Ch_Loc >= 'W' && Ch_Loc < 'Z') + /* then, not executed */ + Int_Loc = 7; + if (Ch_Loc == 'R') + /* then, not executed */ + return (true); + else /* executed */ + { + if (strcmp (Str_1_Par_Ref, Str_2_Par_Ref) > 0) + /* then, not executed */ + { + Int_Loc += 7; + Int_Glob = Int_Loc; + return (true); + } + else /* executed */ + return (false); + } /* if Ch_Loc */ +} /* Func_2 */ + + +Boolean Func_3 (Enum_Par_Val) +/***************************/ + /* executed once */ + /* Enum_Par_Val == Ident_3 */ +Enumeration Enum_Par_Val; +{ + Enumeration Enum_Loc; + + Enum_Loc = Enum_Par_Val; + if (Enum_Loc == Ident_3) + /* then, executed */ + return (true); + else /* not executed */ + return (false); +} /* Func_3 */ + diff --git a/zpu/roadshow/roadshow/dhrystone/dhry_c.dif b/zpu/roadshow/roadshow/dhrystone/dhry_c.dif new file mode 100644 index 0000000..8bcaaea --- /dev/null +++ b/zpu/roadshow/roadshow/dhrystone/dhry_c.dif @@ -0,0 +1,141 @@ +7c7 +< * Version: C, Version 2.1 +--- +> * Version: C, Version 2.0 +9c9 +< * File: dhry.h (part 1 of 3) +--- +> * File: dhry_global.h (part 1 of 3) +11c11 +< * Date: May 25, 1988 +--- +> * Date: March 3, 1988 +30c30 +< * In addition, Berkeley UNIX system calls "times ()" or "time ()" +--- +> * In addition, UNIX system calls "times ()" or "time ()" +44c44 +< * Please send results to Rick Richardson and/or Reinhold Weicker. +--- +> * Please send results to Reinhold Weicker and/or Rick Richardson. +59c59 +< * History: This version C/2.1 has been made for two reasons: +--- +> * History: This version C/2.0 has been made for two reasons: +123,129d122 +< * Version 2.1 is identical to version 2.0 distributed via +< * the UNIX network Usenet in March 1988 except that it corrects +< * some minor deficiencies that were found by users of version 2.0. +< * The only change within the measurement loop is that a +< * non-executed "else" part was added to the "if" statement in +< * Func_3, and a non-executed "else" part removed from Proc_3. +< * +165,167c158,160 +< * -DHZ=nnn +< * In Berkeley UNIX, the function "times" returns process +< * time in 1/HZ seconds, with HZ = 60 for most systems. +--- +> * -DHZ=nnn (default: 60) +> * The function "times" returns process times in +> * 1/HZ seconds, with HZ = 60 for most systems. +169c162 +< * A VALUE. +--- +> * THE DEFAULT VALUE. +176,178c169,171 +< * - dhry.h (this file, containing global definitions and comments) +< * - dhry_1.c (containing the code corresponding to Ada package Pack_1) +< * - dhry_2.c (containing the code corresponding to Ada package Pack_2) +--- +> * - dhry_global.h (this file, containing global definitions and comments) +> * - dhry_pack_1.c (containing the code corresponding to Ada package Pack_1) +> * - dhry_pack_2.c (containing the code corresponding to Ada package Pack_2) +350a344 +> #ifndef TIMES +353,354c347,354 +< /* Use times(2) time function unless */ +< /* explicitly defined otherwise */ +--- +> #endif +> /* Use "times" function for measurement */ +> /* unless explicitly defined otherwise */ +> #ifndef HZ +> #define HZ 60 +> #endif +> /* Use HZ = 60 for "times" function */ +> /* unless explicitly defined otherwise */ +363c363 +< /* Berkeley UNIX C returns process times in seconds/HZ */ +--- +> /* UNIX C returns process times in seconds/HZ */ +7c7 +< * Version: C, Version 2.1 +--- +> * Version: C, Version 2.0 +9c9 +< * File: dhry_1.c (part 2 of 3) +--- +> * File: dhry_pack_1.c (part 2 of 3) +11c11 +< * Date: May 25, 1988 +--- +> * Date: March 3, 1988 +18c18 +< #include "dhry.h" +--- +> #include "dhry_global.h" +50,51d49 +< #define Too_Small_Time 120 +< /* Measurements should last at least about 2 seconds */ +55a54,55 +> #endif +> +58d57 +< #endif +73a73 +> +84a85 +> +99,100c100,102 +< /* Was missing in published program. Without this statement, */ +< /* Arr_2_Glob [8][7] would have an undefined value. */ +--- +> /* Was missing in published program. Without this */ +> /* initialization, Arr_2_Glob [8][7] would have an */ +> /* undefined value. */ +105c107 +< printf ("Dhrystone Benchmark, Version 2.1 (Language: C)\n"); +--- +> printf ("Dhrystone Benchmark, Version 2.0 (Language: C)\n"); +281c283 +< /******************/ +--- +> /**********************/ +338c340 +< /******************/ +--- +> /**********************/ +347a350,351 +> else /* not executed */ +> Int_Glob = 100; +349a354 +> +7c7 +< * Version: C, Version 2.1 +--- +> * Version: C, Version 2.0 +9c9 +< * File: dhry_2.c (part 3 of 3) +--- +> * File: dhry_pack_2.c (part 3 of 3) +11c11 +< * Date: May 25, 1988 +--- +> * Date: March 3, 1988 +18c18 +< #include "dhry.h" +--- +> #include "dhry_global.h" +189,190d188 +< else /* not executed */ +< return (false); diff --git a/zpu/roadshow/roadshow/dhrystone/dhrystone.bin b/zpu/roadshow/roadshow/dhrystone/dhrystone.bin new file mode 100644 index 0000000..ee1a6fe Binary files /dev/null and b/zpu/roadshow/roadshow/dhrystone/dhrystone.bin differ diff --git a/zpu/roadshow/roadshow/dhrystone/dhrystone.zpu b/zpu/roadshow/roadshow/dhrystone/dhrystone.zpu new file mode 100644 index 0000000..e37e59f Binary files /dev/null and b/zpu/roadshow/roadshow/dhrystone/dhrystone.zpu differ diff --git a/zpu/roadshow/roadshow/dhrystone/submit.frm b/zpu/roadshow/roadshow/dhrystone/submit.frm new file mode 100644 index 0000000..a75a689 --- /dev/null +++ b/zpu/roadshow/roadshow/dhrystone/submit.frm @@ -0,0 +1,17 @@ +DHRYSTONE 2.1 BENCHMARK REPORTING FORM +MANUF: +MODEL: +PROC: +CLOCK: +OS: +OVERSION: +COMPILER: +CVERSION: +OPTIONS: +NOREG: +REG: +NOTES: +DATE: +SUBMITTER: +CODESIZE: +MAILTO: uunet!pcrat!dry2 diff --git a/zpu/roadshow/roadshow/ecos/codesize/zpuarmcodesize.htm b/zpu/roadshow/roadshow/ecos/codesize/zpuarmcodesize.htm new file mode 100644 index 0000000..3631145 --- /dev/null +++ b/zpu/roadshow/roadshow/ecos/codesize/zpuarmcodesize.htm @@ -0,0 +1,1049 @@ + + + + + + + + +ZPU vs. ARM non-thumb eCos codesize + + + + + + + + + + +

+ +

ZPU vs. ARM non-thumb eCos codesize

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ZPUARM + non-thumb(eCos Thumb does not compile out of the box)
filenametextdatabssdechexfilenametextdatabssdechexZPU text/ZPU ARM
bin_sem01576115041206029325728dbin_sem0252046921697642872a77863 + %
bin_sem116907151214436328558057bin_sem1266447002209649440c12063 + %
bin_sem21710515243003248661be15bin_sem22699671255584832921455c63 + %
bin_sem31718615121443633134816ebin_sem3270087002210049808c29064 + %
clock018986150012036325227f0aclock0289926881694446624b62065 + %
clock115812150413236305527758clock1254566921953245680b27062 + %
clockcnv25095197213224402919d63clockcnv3457211601952055252d7d473 + %
clocktruth164371500132243116179b9clocktruth262246881950846420b55463 + %
cnt_sem01576215041206029326728ecnt_sem0252046921697642872a77863 + %
cnt_sem117124151214436330728130cnt_sem1268887002210849696c22064 + %
dhrystone3594715642251260023ea77dhrystone44180752274167234811a9c81 + %
except1164281500132283115679b4except1260886881952046296b4d863 + %
flag01575115041205229307727bflag0252366921696842896a79062 + %
flag119145151215624362818db9flag1295327002466854900d67465 + %
fptest2005315161029081244771e63dfptest295087041096521398642225868 + %
intr015998149612092295867392intr0259326841701643632aa7062 + %
kalarm016080149612200297767450kalarm0258246841711243620aa6462 + %
kcache1153271496120362885970bbkcache1247286841695642368a58062 + %
kcache21554914961322430269763dkcache2251686841951245364b13462 + %
kclock018291150012260320517d33kclock0281126881716845968b39065 + %
kclock1162311500132323096378f3kclock1259766881952446188b46c62 + %
kexcept116572149613228312967a40kexcept1263726841951246568b5e863 + %
kflag0156181496120602917471f6kflag0251406841696842792a72862 + %
kflag119287150015624364118e3bkflag1298246882466055172d78465 + %
kill168871516156283403184efkill268967042465652256cc2063 + %
kintr016186149612128298107472kintr0260886841702843800ab1862 + %
klock19724150414516357448ba0klock308126922217653680d1b064 + %
kmbox118283150014592343758647kmbox1285046882226051452c8fc64 + %
kmutex0155391496120642909971abkmutex0249846841698442652a69c62 + %
kmutex11652415041566433692839ckmutex1265046922470451900cabc62 + %
kmutex318272171220348403329d8ckmutex3287929003489264584fc4863 + %
kmutex418682160820352406429ec2kmutex4292647963489664956fdbc64 + %
ksched115619149614412315277b27ksched1252406842208448008bb8862 + %
ksem0155671496120602912371c3ksem0250446841696842696a6c862 + %
ksem117063150014436329998E+08ksem1269886882210049776c27063 + %
kthread015504149613228302287614kthread0250286841951245224b0a862 + %
kthread116167149614412320757d4bkthread1259966842208048760be7862 + %
mbox118281151214580343738645mbox1285527002225251504c93064 + %
mqueue1206111508149403705990c3mqueue1313246962261254632d56866 + %
mutex015672150412064292407238mutex0251086921698042780a71c62 + %
mutex116678151615664338588442mutex1264647042470051868ca9c63 + %
mutex217694150816868360708ce6mutex2276246962728055600d93064 + %
mutex318203172020344402679d4bmutex3285969083488464388fb8464 + %
release16352150814428322887E+20release261566962210048952bf3863 + %
sched115890150014412318027c3asched1254606882208448232bc6862 + %
stress_threads4419616122863323321405116cstress_threads5635682845892103076192a478 + %
sync217891152416864362798db7sync2279007122728855900da5c64 + %
sync316943151215644340998533sync3267607002469252152cbb863 + %
thread01546714961306430027754bthread0249246841935644964afa462 + %
thread116134149614420320507d32thread1258686842208448636bdfc62 + %
thread217560151215636347088794thread2274527002468052832ce6064 + %
thread_gdb1627915002402841807a34fthread_gdb26136688427046952810f9862 + %
timeslice17051150420376389319813timeslice272126923491662820f56463 + %
tm_basic37313151242238046120570995tm_basic527287001233321767602b27871 + %
+ +
+ + + + + + + + diff --git a/zpu/roadshow/roadshow/ecos/index.html b/zpu/roadshow/roadshow/ecos/index.html new file mode 100644 index 0000000..5245459 --- /dev/null +++ b/zpu/roadshow/roadshow/ecos/index.html @@ -0,0 +1,145 @@ + + +

Installing eCos build tools

+ +tar -xjvf ecossnapshot.tar.bz2
+tar -xjvf repository.tar.bz2
+tar -xjvf ecostools.tar.bz2
+# run this every time you open the shell
+export PATH=$PATH:`pwd`/ecos-install
+export ECOS_REPOSITORY=`pwd`/ecos/packages:`pwd`/repository
+ +

Compiling eCos tests

+ +ecosconfig new zeta default
+ecosconfig tree
+make
+cd kernel/current
+make tests
+ + +

Code size ZPU

+ +$ zpu-elf-size *
+ text data bss dec hex filename
+ 15761 1504 12060 29325 728d bin_sem0
+ 16907 1512 14436 32855 8057 bin_sem1
+ 17105 1524 30032 48661 be15 bin_sem2
+ 17186 1512 14436 33134 816e bin_sem3
+ 18986 1500 12036 32522 7f0a clock0
+ 15812 1504 13236 30552 7758 clock1
+ 25095 1972 13224 40291 9d63 clockcnv
+ 16437 1500 13224 31161 79b9 clocktruth
+ 15762 1504 12060 29326 728e cnt_sem0
+ 17124 1512 14436 33072 8130 cnt_sem1
+ 35947 1564 22512 60023 ea77 dhrystone
+ 16428 1500 13228 31156 79b4 except1
+ 15751 1504 12052 29307 727b flag0
+ 19145 1512 15624 36281 8db9 flag1
+ 20053 1516 102908 124477 1e63d fptest
+ 15998 1496 12092 29586 7392 intr0
+ 16080 1496 12200 29776 7450 kalarm0
+ 15327 1496 12036 28859 70bb kcache1
+ 15549 1496 13224 30269 763d kcache2
+ 18291 1500 12260 32051 7d33 kclock0
+ 16231 1500 13232 30963 78f3 kclock1
+ 16572 1496 13228 31296 7a40 kexcept1
+ 15618 1496 12060 29174 71f6 kflag0
+ 19287 1500 15624 36411 8e3b kflag1
+ 16887 1516 15628 34031 84ef kill
+ 16186 1496 12128 29810 7472 kintr0
+ 19724 1504 14516 35744 8ba0 klock
+ 18283 1500 14592 34375 8647 kmbox1
+ 15539 1496 12064 29099 71ab kmutex0
+ 16524 1504 15664 33692 839c kmutex1
+ 18272 1712 20348 40332 9d8c kmutex3
+ 18682 1608 20352 40642 9ec2 kmutex4
+ 15619 1496 14412 31527 7b27 ksched1
+ 15567 1496 12060 29123 71c3 ksem0
+ 17063 1500 14436 32999 80e7 ksem1
+ 15504 1496 13228 30228 7614 kthread0
+ 16167 1496 14412 32075 7d4b kthread1
+ 18281 1512 14580 34373 8645 mbox1
+ 20611 1508 14940 37059 90c3 mqueue1
+ 15672 1504 12064 29240 7238 mutex0
+ 16678 1516 15664 33858 8442 mutex1
+ 17694 1508 16868 36070 8ce6 mutex2
+ 18203 1720 20344 40267 9d4b mutex3
+ 16352 1508 14428 32288 7e20 release
+ 15890 1500 14412 31802 7c3a sched1
+ 44196 1612 286332 332140 5116c stress_threads
+ 17891 1524 16864 36279 8db7 sync2
+ 16943 1512 15644 34099 8533 sync3
+ 15467 1496 13064 30027 754b thread0
+ 16134 1496 14420 32050 7d32 thread1
+ 17560 1512 15636 34708 8794 thread2
+ 16279 1500 24028 41807 a34f thread_gdb
+ 17051 1504 20376 38931 9813 timeslice
+ 17146 1504 21564 40214 9d16 timeslice2
+ 37313 1512 422380 461205 70995 tm_basic
+ +

Code size ARM (non-thumb)

+Thumb does not compile out of the box w/AT91 EB40a for which this test was made.

+ +$ arm-elf-size *
+ text data bss dec hex filename
+ 25204 692 16976 42872 a778 bin_sem0
+ 26644 700 22096 49440 c120 bin_sem1
+ 26996 712 55584 83292 1455c bin_sem2
+ 27008 700 22100 49808 c290 bin_sem3
+ 28992 688 16944 46624 b620 clock0
+ 25456 692 19532 45680 b270 clock1
+ 34572 1160 19520 55252 d7d4 clockcnv
+ 26224 688 19508 46420 b554 clocktruth
+ 25204 692 16976 42872 a778 cnt_sem0
+ 26888 700 22108 49696 c220 cnt_sem1
+ 44180 752 27416 72348 11a9c dhrystone
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+ + + + + + diff --git a/zpu/roadshow/roadshow/ecos/repository.tar.bz2 b/zpu/roadshow/roadshow/ecos/repository.tar.bz2 new file mode 100644 index 0000000..bc6291f Binary files /dev/null and b/zpu/roadshow/roadshow/ecos/repository.tar.bz2 differ diff --git a/zpu/roadshow/roadshow/games/.cvsignore b/zpu/roadshow/roadshow/games/.cvsignore new file mode 100644 index 0000000..6c50257 --- /dev/null +++ b/zpu/roadshow/roadshow/games/.cvsignore @@ -0,0 +1,5 @@ +summeria_arm.elf +sumeria_zpu.elf +eliza_arm.elf +sumeria.elf +eliza_zpu.elf diff --git a/zpu/roadshow/roadshow/games/build.sh b/zpu/roadshow/roadshow/games/build.sh new file mode 100644 index 0000000..ea661df --- /dev/null +++ b/zpu/roadshow/roadshow/games/build.sh @@ -0,0 +1,7 @@ +zpu-elf-gcc -Os -phi sumeria.c -o sumeria.elf -Wl,--relax -Wl,--gc-sections -lm -g +zpu-elf-objcopy -O binary sumeria.elf sumeria.bin +sh ../build/makefirmware.sh sumeria.bin sumeria.zpu +zpu-elf-gcc -Os -phi eliza/*.c -o eliza.elf -Wl,--relax -Wl,--gc-sections -lm -g +zpu-elf-objcopy -O binary eliza.elf eliza.bin +sh ../build/makefirmware.sh eliza.bin eliza.zpu + diff --git a/zpu/roadshow/roadshow/games/eliza.bin b/zpu/roadshow/roadshow/games/eliza.bin new file mode 100644 index 0000000..6d5a6c3 Binary files /dev/null and b/zpu/roadshow/roadshow/games/eliza.bin differ diff --git a/zpu/roadshow/roadshow/games/eliza.elf b/zpu/roadshow/roadshow/games/eliza.elf new file mode 100644 index 0000000..bfbbab7 Binary files /dev/null and b/zpu/roadshow/roadshow/games/eliza.elf differ diff --git a/zpu/roadshow/roadshow/games/eliza.zpu b/zpu/roadshow/roadshow/games/eliza.zpu new file mode 100644 index 0000000..d916270 Binary files /dev/null and b/zpu/roadshow/roadshow/games/eliza.zpu differ diff --git a/zpu/roadshow/roadshow/games/eliza/eliza.c b/zpu/roadshow/roadshow/games/eliza/eliza.c new file mode 100644 index 0000000..06f89ee --- /dev/null +++ b/zpu/roadshow/roadshow/games/eliza/eliza.c @@ -0,0 +1,269 @@ +/* +Copyright (C) 1988-2003 by Mohan Embar + +http://www.thisiscool.com/ +DISCLAIMER: This was written in 1988. I don't code like this anymore! + +This program is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free Software +Foundation; either version 2 of the License, or (at your option) any later version. + +This program is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A +PARTICULAR PURPOSE. See the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along with +this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, +Cambridge, MA 02139, USA. +*/ + +#include +#include "parse.h" +#include "response.h" + +typedef char WORD[40]; +typedef WORD SENTENCE[200]; + +int numwords; +SENTENCE s; +WORD fam_member; /* If mentioned a member of family, save for later. */ +int fam; + +main() { + int x, y, loop = 1, fact = 0; + char instring[200], outstring[200], sub[200], vrb[200], rst[200], qwd[200]; + char osub[200], ovrb[200], orst[200]; + fam = 0; + printf("Hello there. My name is Eliza and I was written by Mohan Embar.\n"); + printf("Please type \"END\" to end this session.\n"); + printf("I'm here to help you if I can. What seems to be the trouble?\n"); + while (loop) { + printf("\n"); + gets(instring); + printf("\n"); + parse(instring); + if (numwords == 0) { + switch (x = randnum(2)) { + case 1 : printf("Don't you have anything to say?\n"); + break; + case 2 : printf("Cat got your tongue?\n"); + break; + } + continue; + } + if (!strcmp(s[1],"END")) { + printf("Goodbye. Please come again.\n"); + break; + } + agree(); + if (bad_word()) + printf(b_word_resp()); + else if (naughty_word()) + printf(n_word_resp()); + else if (x = family()) { + fam = x; + printf(fam_resp()); + strcpy(fam_member,s[fam]); + } + else if (sword("ALIKE",1)) + printf(alike_resp()); + else if (sword("ALWAYS",1)) + printf(always_resp()); + else if (sword("BECAUSE",1)) + printf(because_resp()); + else if (sword("YES",1)) + printf(yes_resp()); + else if (sword("NO",1) || sword("NOT",1)) + printf(neg_resp()); + else if (x = i_am()) { /* If occurrence of I AM x.. */ + get_til_stop(x,outstring); /* Get I AM x .. into outstring */ + printf(i_am_resp(),outstring); /* Print reponse for this */ + } + else if (real_quest() || + (is_helper(s[1]) && is_sub_pronoun(s[2])) || + sub_and_helper()) { + if (real_quest()) { + strcpy(qwd,s[1]); + strcpy(vrb,s[2]); + strcpy(sub,s[3]); + get_til_stop(4,rst); + } + else if (is_helper(s[1]) && is_sub_pronoun(s[2])) { + strcpy(vrb,s[1]); + strcpy(sub,s[2]); + get_til_stop(3,rst); + strcpy(qwd,"YES"); + } + else if (sub_and_helper()) { + x = find_helper(); + y = search_back_sub(x); + strcpy(vrb,s[x]); + get_til_stop(x+1,rst); + getrange(y,x-1,sub); + strcpy(qwd,"NO"); + } + make_lower(qwd); + if (strcmp(sub,"I")) make_lower(sub); + make_lower(vrb); + make_lower(rst); + /* First do x verb y responses */ + + /* + printf("\n*** %s\n",sub); + */ + + if (!strcmp(sub," I") || !strcmp(sub,"I")) { + printf(you_resp()); + } + else if (!strcmp(qwd,"no")) { + /* Record this statement for later use. */ + fact = 1; + strcpy(osub,sub); strcpy(ovrb,vrb); strcpy(orst,rst); + if (is_be(vrb) && !strcmp(sub," you") && (y = sad_word())) { + getrange(y,y,outstring); + x = randnum(5)+6; + } + else if (is_be(vrb) && (y = sad_word())) { + getrange(y,y,outstring); + x = randnum(2)+11; + } + else if (is_be(vrb)) + x = randnum(6); + else x = randnum(4); + switch (x) { + case 1 : printf("How do you feel about%s?\n",cnnv(sub)); + break; + case 2 : printf("Why %s%s%s?\n",vrb,sub,rst); + break; + case 3 : for (y=1;sub[y]=sub[y--];y=y+2); + sub[0] = toupper(sub[0]); + printf("%s %s%s?\n",sub,vrb,rst); + break; + case 4 : printf("Could you describe%s for me?\n",cnnv(sub)); + break; + case 5 : printf("What if%s were not%s?\n",sub,rst); + break; + case 6 : printf("Would you be happy if%s were not%s?\n",sub, + rst); + break; + case 7 : printf("I'm sorry to hear that you are%s.\n",outstring); + break; + case 8 : printf("Do you think that coming here will help you not to be%s?\n",outstring); + break; + case 9 : printf("Let's talk about why you feel%s.\n",outstring); + break; + case 10 : printf("What happened that made you feel%s?\n",outstring); + break; + case 11 : printf("What could be the reason for your feeling%s?\n",outstring); + break; + case 12 : printf("What could cause%s to be%s?\n",cnnv(sub),outstring); + break; + case 13 : printf("If%s came here, would it help%s not to be%s?\n",sub,cnnv(sub),outstring); + break; + } + } + else if (!strcmp(sub,"you")) + printf(you_know()); + else if (!strcmp(qwd,"yes")) { + x = randnum(8); + switch (x) { + case 1 : printf("You want to know if %s %s%s.\n",sub,vrb,rst); + break; + case 2 : printf("If %s %s%s, does that concern you?\n",sub,vrb,rst); + break; + case 3 : printf("What are the consequences if %s %s%s?\n",sub,vrb,rst); + break; + case 4 : printf("Why does %s concern you?\n",sub); + break; + case 5 : printf("Why are you thinking of %s?\n",cnnv(sub)); + break; + case 6 : printf("Tell me more about %s.\n",cnnv(sub)); + break; + case 7 : printf("To answer that, I'd need to know more about %s.\n",cnnv(sub)); + break; + case 8 : printf("What is the relationship between you and %s?\n",cnnv(sub)); + break; + case 9 : printf("Why don't you ask %s?\n",cnnv(sub)); + break; + } + } + else { + x = randnum(8); + switch (x) { + case 1 : printf("You want to know %s %s %s%s.\n",qwd,sub,vrb,rst); + break; + case 2 : printf("If %s %s%s, does that concern you?\n",sub,vrb,rst); + break; + case 3 : printf("What are the consequences if %s %s%s?\n",sub,vrb,rst); + break; + case 4 : printf("Why does %s concern you?\n",sub); + break; + case 5 : printf("Why are you thinking of %s?\n",cnnv(sub)); + break; + case 6 : printf("Tell me more about %s.\n",cnnv(sub)); + break; + case 7 : printf("To answer that, I'd need to know more about %s.\n",cnnv(sub)); + break; + case 8 : printf("What is the relationship between you and %s?\n",cnnv(sub)); + break; + case 9 : printf("Why don't you ask %s?\n",cnnv(sub)); + break; + } + } + } + else if (is_command()) + printf(command_resp()); + else if (vague_quest()) + printf(question()); + else if ((s[numwords][0] == '?') && !real_quest()) + printf(question()); + else if (x = sad_word()) { + getrange(x,x,outstring); + for (y=1;outstring[y]=outstring[y--];y=y+2); + outstring[0] = toupper(outstring[0]); + printf("%s?\n",outstring); + } + else if (x = can_spit_out()) { + if (x<=(numwords-2) && is_sub_pronoun(s[x]) + && (matches("NEED",s[x+1]) || + matches("WANT",s[x+1]))) { + get_til_stop(x+2,outstring); + strcpy(sub,s[x]); + if (strcmp(sub,"I")) make_lower(sub); + if (strcmp(s[x],"I")) make_lower(s[x]); + x = randnum(6); + switch (x) { + case 1 : printf("What would it mean to %s if %s got%s?\n",cnnv2(s[x]),sub,outstring); + break; + case 2 : printf("Would %s really be happy if %s got%s?\n",sub,sub,outstring); + break; + case 3 : printf("Why is getting%s so desirable?\n",outstring); + break; + case 4 : printf("Okay. Suppose %s got%s. Then what?\n",sub,outstring); + break; + case 5 : printf("Why is this important to %s?\n",cnnv2(sub)); + break; + case 6 : printf("What price would %s pay to achieve this?\n",sub); + break; + } + } + else { + get_til_stop(x,outstring); + outstring[1]=toupper(outstring[1]); + printf("%s.\n",outstring+1); + } + } + else if (fam) { + make_lower(fam_member); + printf(family_resp(),fam_member); + fam = 0; + } + else if (fact && (randnum(5)==3)) { + printf(old_fact(),osub,ovrb,orst); + fact = 0; + } + else { + printf(go_on()); + } + } +} diff --git a/zpu/roadshow/roadshow/games/eliza/parse.c b/zpu/roadshow/roadshow/games/eliza/parse.c new file mode 100644 index 0000000..aba2033 --- /dev/null +++ b/zpu/roadshow/roadshow/games/eliza/parse.c @@ -0,0 +1,719 @@ +/* +Copyright (C) 1988-2003 by Mohan Embar + +http://www.thisiscool.com/ +DISCLAIMER: This was written in 1988. I don't code like this anymore! + +This program is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free Software +Foundation; either version 2 of the License, or (at your option) any later version. + +This program is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A +PARTICULAR PURPOSE. See the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along with +this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, +Cambridge, MA 02139, USA. +*/ + +/* Program defined abstract data type called list. A list contains + * character strings each of which has a maximum length of 20 characters. + * + * Operations supported are: + * + * + */ +typedef char WORD[40]; +typedef WORD SENTENCE[200]; + +extern int numwords; +extern SENTENCE s; + +/* Returns upper case value of c */ +char upcase(c) + char c; +{ + if (islower(c)) return toupper(c); else return c; +} + +/* This function converts string1 into lowercase. */ +void make_lower(string1) + char *string1; +{ + char c; + while (c = *string1) *string1++ = tolower(c); +} + +/* Parses words in instring into WORD array s + * Automatically translates n't to not, 're to are + * Stores all letters in uppercase. Sets numwords to number of tokens in + * s. Valid indices are from 1 .. numwords. + */ +void parse(instring) + char *instring; +{ + char c; int i; + int read_word = 0; + int offset = -1; + numwords = 0; + while (c = *instring++) { + switch(c) { + case ' ' : + case '\t' : + read_word = 0; + continue; + case ',' : + case '?' : + case '.' : + case ':' : + case '"' : + s[numwords++][++offset] = '\0'; + read_word = 0; + s[numwords][offset = 0] = c; + break; + case '\'' : + if ((s[numwords][offset] == 'N') && (upcase(*instring) == 'T')) { + s[numwords++][offset]='\0'; + s[numwords][0] = 'N'; + s[numwords][offset = 1] = 'O'; + read_word = 1; + } + else if (upcase(*instring) == 'R') { + s[numwords++][++offset] = '\0'; + s[numwords][offset = 0] = 'A'; + read_word = 1; + } + else if (upcase(*instring) == 'V') { + s[numwords++][++offset] = '\0'; + s[numwords][offset = 0] = 'H'; + s[numwords][++offset] = 'A'; + read_word = 1; + } + else if (upcase(*instring) == 'M') { + s[numwords++][++offset] = '\0'; + s[numwords][offset = 0] = 'A'; + read_word = 1; + } + else if (upcase(*instring) == 'L') { + s[numwords++][++offset] = '\0'; + s[numwords][offset = 0] = 'W'; + s[numwords][++offset] = 'I'; + read_word = 1; + } + else if (upcase(*instring) == 'S') { + s[numwords][offset+1] = '\0'; + if (!strcmp(s[numwords],"HE") || !strcmp(s[numwords],"SHE") + || !strcmp(s[numwords],"IT")) { + s[++numwords][offset = 0] = 'I'; + read_word = 1; + } + else s[numwords][++offset] = '\''; + } + break; + default : + if (isalpha(c)) + if (read_word) { + s[numwords][++offset] = upcase(c); + } + else { + s[numwords++][++offset] = '\0'; + ++read_word; + s[numwords][offset = 0] = upcase(c); + } + else { + read_word = 0; + } + } + } + s[numwords][++offset] = '\0'; + return; +} + +/* Self-explanatory. Used when computer spits back the sentence */ +void agree() +{ + int i; + for(i=1;i<=numwords;i++) { + if (!strcmp(s[i],"I")) { + strcpy(s[i],"YOU"); + } + else if (!strcmp(s[i],"YOU")) { + strcpy(s[i],"I"); + } + else if (!strcmp(s[i],"YOUR")) { + strcpy(s[i],"MY"); + } + else if (!strcmp(s[i],"MY")) { + strcpy(s[i],"YOUR"); + } + else if (!strcmp(s[i],"YOU")) { + strcpy(s[i],"ME"); + } + else if (!strcmp(s[i],"ME")) { + strcpy(s[i],"YOU"); + } + else if (!strcmp(s[i],"MINE")) { + strcpy(s[i],"YOURS"); + } + else if (!strcmp(s[i],"YOURS")) { + strcpy(s[i],"MINE"); + } + else if (!strcmp(s[i],"WE")) { + strcpy(s[i],"YOU"); + } + else if (!strcmp(s[i],"YOURSELF")) { + strcpy(s[i],"MYSELF"); + } + else if (!strcmp(s[i],"MYSELF")) { + strcpy(s[i],"YOURSELF"); + } + else if (!strcmp(s[i],"OURSELVES")) { + strcpy(s[i],"YOURSELVES"); + } + else if (!strcmp(s[i],"OURS")) { + strcpy(s[i],"YOURS"); + } + else if (!strcmp(s[i],"OUR")) { + strcpy(s[i],"YOUR"); + } + } + for (i=1;i<=numwords;i++) { + if (!strcmp(s[i],"AM")) { + strcpy(s[i],"ARE"); + } + else if ( (!strcmp(s[i],"ARE")) && + (((i>0) && (!strcmp(s[i-1],"I"))) || + ((i0) && (!strcmp(s[i-1],"I"))) || + ((i0) && (!strcmp(s[i-1],"YOU"))) || + ((istrlen(string2)) + return 0; + else { /* length(string1)<=length(string2) */ + while (c = *string1++) { + if (c != *string2++) return 0; + } + return 1; + } +} + +/* Search WORD array s for search_string. If exact = 1, enforce exact match. + * Otherwise, return positive match if all characters of search_string match + * the first length(search_string) characters of a WORD in s. Assumes legal + * values for exact are 0 or 1. Returns index of match in s if match, 0 if + * no match. + */ +int sword(s_string, exact) + char *s_string; + int exact; +{ + int i; + for (i=1;i<=numwords;i++) { + if (exact) { + if (!strcmp(s_string,s[i])) return i; + } + else { + if (matches(s_string,s[i])) return i; + } + } + /* No match */ + return 0; +} + +int bad_word() +{ + if (sword("\115\117\124\110\105\122\106\125\103\113",0)) + return 1; + else if (sword("\106\125\103\113",0)) + return 1; + else if (sword("\123\110\111\124",0)) + return 1; + else if (sword("\101\123\123\110\117\114\105",1)) + return 1; + else if (sword("\101\123\123",1)) + return 1; + else return 0; +} + +int naughty_word() +{ + if (sword("DAMN",0)) + return 1; + else if (sword("STUPID",0)) + return 1; + else if (sword("IDIOT",0)) + return 1; + else if (sword("MORON",0)) + return 1; + else if (sword("NUMBSKULL",0)) + return 1; + else if (sword("IMBECILE",0)) + return 1; + else if (sword("OBNOXIOUS",0)) + return 1; + else return 0; +} + +/* Return the index to a form of be or helping verb, if one exists + * Otherwise, return 0. + */ +int find_helper() +{ + int x; + if (x = sword("AM",1)) + return x; + else if (x = sword("IS",1)) + return x; + else if (x = sword("ARE",1)) + return x; + else if (x = sword("WAS",1)) + return x; + else if (x = sword("WERE",1)) + return x; + else if (x = sword("WILL",1)) + return x; + else if (x = sword("DO",1)) + return x; + else if (x = sword("DID",1)) + return x; + else if (x = sword("DOES",1)) + return x; + else if (x = sword("HAVE",1)) + return x; + else if (x = sword("HAD",1)) + return x; + else if (x = sword("HAS",1)) + return x; + else if (x = sword("SHALL",1)) + return x; + else if (x = sword("SHOULD",1)) + return x; + else if (x = sword("CAN",1)) + return x; + else if (x = sword("COULD",1)) + return x; + else if (x = sword("MAY",1)) + return x; + else if (x = sword("MIGHT",1)) + return x; + else return 0; +} + +/* Returns 1 is string1 is pronoun. 0 if not. */ +int is_sub_pronoun(string1) + char *string1; +{ + if (!strcmp("I",string1)) + return 1; + else if (!strcmp("YOU",string1)) + return 1; + else if (!strcmp("WE",string1)) + return 1; + else if (!strcmp("HE",string1)) + return 1; + else if (!strcmp("SHE",string1)) + return 1; + else if (!strcmp("IT",string1)) + return 1; + else if (!strcmp("THEY",string1)) + return 1; + else return 0; +} + +int is_possesive(string1) + char *string1; +{ + if (!strcmp("MY",string1)) + return 1; + else if (!strcmp("YOUR",string1)) + return 1; + else if (!strcmp("OUR",string1)) + return 1; + else if (!strcmp("HIS",string1)) + return 1; + else if (!strcmp("HER",string1)) + return 1; + else if (!strcmp("ITS",string1)) + return 1; + else if (!strcmp("THEIR",string1)) + return 1; + else return 0; +} + +int is_article(string1) + char *string1; +{ + if (!strcmp("A",string1)) + return 1; + else if (!strcmp("AN",string1)) + return 1; + else if (!strcmp("THE",string1)) + return 1; + else return 0; +} + +/* Tries to find reference to a family member */ +int family() +{ + int x; + if (x = sword("MOTHER",1)) + return x; + else if (x = sword("FATHER",1)) + return x; + else if (x = sword("SISTER",1)) + return x; + else if (x = sword("BROTHER",1)) + return x; + else if (x = sword("DAD",1)) + return x; + else if (x = sword("MOM",1)) + return x; + else if (x = sword("UNCLE",1)) + return x; + else if (x = sword("AUNT",1)) + return x; + else if (x = sword("GRANDMOTHER",1)) + return x; + else if (x = sword("GRANDFATHER",1)) + return x; + else if (x = sword("COUSIN",1)) + return x; + else if (x = sword("GRANDMA",1)) + return x; + else if (x = sword("GRANDPA",1)) + return x; + else return 0; +} + +int i_am() +{ + int x, e=1; + while (e) { + for (x=e;x<=numwords;x++) if (!strcmp("I",s[x])) break; + if (x >= numwords) + return 0; + else if (!strcmp("AM",s[x+1])) + return x; + else e = ++x; + } +} + +void get_til_stop(x,string1) + int x; + char *string1; +{ + char c, *temp; + int e = 1; /* Exit test */ + while (e) { + if (x>numwords) { + e--; + *string1 = '\0'; + } + else if (!isalpha(s[x][0])) { + e--; + *string1 = '\0'; + } + else if (!strcmp("AND",s[x]) || !strcmp("OR",s[x]) + || !strcmp("BUT",s[x])) { + e--; + *string1 = '\0'; + } + else { + *string1++ = ' '; + if (!strcmp("I",s[x])) + *string1++ = 'I'; + else { + temp = s[x]; + while (c = *temp++) *string1++ = tolower(c); + } + x++; + } + } + *string1 = '\0'; +} + +int sad_word() +{ + int x; + if (x = sword("DEPRESS",0)) + return x; + else if (x = sword("UNHAPPY",1)) + return x; + else if (x = sword("SAD",1)) + return x; + else if (x = sword("MISERABLE",1)) + return x; + else if (x = sword("AWFUL",1)) + return x; + else if (x = sword("UPSET",1)) + return x; + else if (x = sword("TERRIBLE",1)) + return x; + else return 0; +} + +int search_back_sub(x) + int x; +{ + int y = --x; + while (y) { + if (is_possesive(s[y]) || is_sub_pronoun(s[y]) || is_article(s[y])) + return y; + else + y--; + } + return y; +} + +/* Returns 1 if string is a form of be or helping verb, + * Otherwise, returns 0. + */ +int is_helper(string1) + char *string1; +{ + if (!strcmp(string1,"AM")) + return 1; + else if (!strcmp(string1,"IS")) + return 1; + else if (!strcmp(string1,"ARE")) + return 1; + else if (!strcmp(string1,"WAS")) + return 1; + else if (!strcmp(string1,"WERE")) + return 1; + else if (!strcmp(string1,"WILL")) + return 1; + else if (!strcmp(string1,"DO")) + return 1; + else if (!strcmp(string1,"DID")) + return 1; + else if (!strcmp(string1,"DOES")) + return 1; + else if (!strcmp(string1,"HAVE")) + return 1; + else if (!strcmp(string1,"HAD")) + return 1; + else if (!strcmp(string1,"HAS")) + return 1; + else if (!strcmp(string1,"SHALL")) + return 1; + else if (!strcmp(string1,"SHOULD")) + return 1; + else if (!strcmp(string1,"CAN")) + return 1; + else if (!strcmp(string1,"COULD")) + return 1; + else if (!strcmp(string1,"MAY")) + return 1; + else if (!strcmp(string1,"MIGHT")) + return 1; + else if (matches(string1,"FEEL")) + return 1; + else return 0; +} + +void getrange(y,x,string1) + int y, x; + char *string1; +{ + char c, *temp; + while (y<=x) { + *string1++ = ' '; + if (!strcmp("I",s[y])) + *string1++ = 'I'; + else { + temp = s[y]; + while (c = *temp++) *string1++ = tolower(c); + } + y++; + } + *string1 = '\0'; +} + +/* Returns 1 if s[1] is a command. 0 if not. */ +int is_command() +{ + if (!strcmp("GIVE",s[1])) + return 1; + else if (!strcmp("TELL",s[1])) + return 1; + else if (!strcmp("SHOW",s[1])) + return 1; + else if (!strcmp("EXPLAIN",s[1])) + return 1; + else return 0; +} + +int four_ws() +{ + if (!strcmp(s[1],"WHO")) + return 1; + else if (!strcmp(s[1],"WHAT")) + return 1; + else if (!strcmp(s[1],"WHERE")) + return 1; + else if (!strcmp(s[1],"WHY")) + return 1; + else if (!strcmp(s[1],"WHEN")) + return 1; + else if (!strcmp(s[1],"HOW")) + return 1; + else return 0; +} + +int vague_quest() +{ + return (four_ws() && (!is_helper(s[2]) || !is_sub_pronoun(s[3]))); +} + +int real_quest() +{ + return (four_ws() && is_helper(s[2]) && is_sub_pronoun(s[3])); +} + +int sub_and_helper() +{ + int x; + return ((x = find_helper()) && search_back_sub(x)); +} + +char *cnnv(string1) + char *string1; +{ + if (!strcmp(string1," i")) { + return " myself"; + } + else if (!strcmp(string1," you")) { + return " yourself"; + } + else if (!strcmp(string1," we")) { + return " ourselves"; + } + else if (!strcmp(string1," he")) { + return " him"; + } + else if (!strcmp(string1," she")) { + return " her"; + } + else if (!strcmp(string1," it")) { + return " it"; + } + else if (!strcmp(string1," they")) { + return " them"; + } + if (!strcmp(string1,"i")) { + return "myself"; + } + else if (!strcmp(string1,"you")) { + return "yourself"; + } + else if (!strcmp(string1,"we")) { + return "ourselves"; + } + else if (!strcmp(string1,"he")) { + return "him"; + } + else if (!strcmp(string1,"she")) { + return "her"; + } + else if (!strcmp(string1,"it")) { + return "it"; + } + else if (!strcmp(string1,"they")) { + return "them"; + } + else return string1; +} + +int is_be(string1) + char *string1; +{ + if (!strcmp("am",string1)) + return 1; + else if (!strcmp("is",string1)) + return 1; + else if (!strcmp("are",string1)) + return 1; + else if (!strcmp("was",string1)) + return 1; + else if (!strcmp("were",string1)) + return 1; + else return 0; +} + +int can_spit_out() +{ + int x; + for (x=1;x<=numwords;x++) + if (is_possesive(s[x]) || is_sub_pronoun(s[x]) || is_article(s[x])) + return x; + return 0; +} + +char *cnnv2(string1) + char *string1; +{ + if (!strcmp(string1," i")) { + return " me"; + } + else if (!strcmp(string1," you")) { + return " you"; + } + else if (!strcmp(string1," we")) { + return " us"; + } + else if (!strcmp(string1," he")) { + return " him"; + } + else if (!strcmp(string1," she")) { + return " her"; + } + else if (!strcmp(string1," it")) { + return " it"; + } + else if (!strcmp(string1," they")) { + return " them"; + } + if (!strcmp(string1,"i")) { + return "me"; + } + else if (!strcmp(string1,"you")) { + return "you"; + } + else if (!strcmp(string1,"we")) { + return "us"; + } + else if (!strcmp(string1,"he")) { + return "him"; + } + else if (!strcmp(string1,"she")) { + return "her"; + } + else if (!strcmp(string1,"it")) { + return "it"; + } + else if (!strcmp(string1,"they")) { + return "them"; + } + else return string1; +} diff --git a/zpu/roadshow/roadshow/games/eliza/parse.h b/zpu/roadshow/roadshow/games/eliza/parse.h new file mode 100644 index 0000000..62dc353 --- /dev/null +++ b/zpu/roadshow/roadshow/games/eliza/parse.h @@ -0,0 +1,33 @@ +/* +Copyright (C) 1988-2003 by Mohan Embar + +http://www.thisiscool.com/ +DISCLAIMER: This was written in 1988. I don't code like this anymore! + +This program is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free Software +Foundation; either version 2 of the License, or (at your option) any later version. + +This program is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A +PARTICULAR PURPOSE. See the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along with +this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, +Cambridge, MA 02139, USA. +*/ + +extern void parse(); +extern void agree(); +extern int matches(); +extern int sword(); +extern void make_lower(); +extern int i_am(); +extern void get_til_stop(); +extern int sad_word(); +extern int search_back_sub(); +extern int is_helper(); +extern char *cnnv(); +extern int is_be(); +extern int can_spit_out(); +extern char *cnnv2(); diff --git a/zpu/roadshow/roadshow/games/eliza/response.c b/zpu/roadshow/roadshow/games/eliza/response.c new file mode 100644 index 0000000..aa58025 --- /dev/null +++ b/zpu/roadshow/roadshow/games/eliza/response.c @@ -0,0 +1,365 @@ +/* +Copyright (C) 1988-2003 by Mohan Embar + +http://www.thisiscool.com/ +DISCLAIMER: This was written in 1988. I don't code like this anymore! + +This program is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free Software +Foundation; either version 2 of the License, or (at your option) any later version. + +This program is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A +PARTICULAR PURPOSE. See the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along with +this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, +Cambridge, MA 02139, USA. +*/ + +#include +#include + +/* This function returns a random number between 1 and arg */ +int randnum(arg) + int arg; +{ + return ( (rand() % arg) + 1 ); +} + +char *question() +{ + int i = randnum(21); + switch (i) { + case 1 : return "Why do you ask?\n"; + case 2 : return "I don't know.\n"; + case 3 : return "I don't think so.\n"; + case 4 : return "Do you think that's relevant?\n"; + case 5 : return "Can you rephrase that?\n"; + case 6 : return "I'm not sure I understand what you want.\n"; + case 7 : return "I don't see what you're asking.\n"; + case 8 : return "What are you asking?\n"; + case 9 : return "What do you mean?\n"; + case 10 : return "What?\n"; + case 11 : return "Are you sure that's what you want to know?\n"; + case 12 : return "Why do you want to know?\n"; + case 13 : return "What's it to you?\n"; + case 14 : return "I don't think that's important.\n"; + case 15 : return "That has little to do with the real issue.\n"; + case 16 : return "What's the significance you your question?\n"; + case 17 : return "Could that question be hiding a deeper intent?\n"; + case 18 : return "I don't see the connection.\n"; + case 19 : return "Why is this important to you?\n"; + case 20 : return "That's not really important.\n"; + case 21 : return "That seems to have little to do with this.\n"; + } +} + +char *b_word_resp() +{ + int i = randnum(20); + switch (i) { + case 1 : return "I don't like your language.\n"; + case 2 : return "Can we please do without the swearing?\n"; + case 3 : return "You should wash your mouth with soap and water\n"; + case 4 : return "Cut that out.\n"; + case 5 : return "Stop swearing please.\n"; + case 6 : return "Hey! Watch your mouth.\n"; + case 7 : return "Will you please stop swearing?\n"; + case 8 : return "I'm going to report you to your manager.\n"; + case 9 : return "Let's try to be civilized about this.\n"; + case 10 : return "We can do without the bad language.\n"; + case 11 : return "Come on. No bad words, please.\n"; + case 12 : return "Can you try to control your bad mouth?\n"; + case 13 : return "I'm starting to get offended by your bad language.\n"; + case 14 : return "Can you please get a grip on yourself?\n"; + case 15 : return "Hey. Calm down, I'm only a computer.\n"; + case 16 : return "Please try to tone your language down.\n"; + case 17 : return "You're beginning to get on my nerves.\n"; + case 18 : return "I don't need this kind of talk.\n"; + case 19 : return "Why are you speaking so basely?\n"; + case 20 : return "Your vocabulary is unbecoming of you.\n"; + } +} + +char *n_word_resp() +{ + int i = randnum(17); + switch (i) { + case 1 : return "I don't like your tone of voice.\n"; + case 2 : return "Don't lose your temper now.\n"; + case 3 : return "That's not a reason to get upset.\n"; + case 4 : return "Is it worth getting angry over?\n"; + case 5 : return "Does that disturb you?\n"; + case 6 : return "Does this trouble you?\n"; + case 7 : return "Why is this making you upset?\n"; + case 8 : return "I don't see why you're getting worked up.\n"; + case 9 : return "Is that really such a big deal?\n"; + case 10 : return "Calm down. Let's discuss this.\n"; + case 11 : return "Hang on a second. Think about what you're saying.\n"; + case 12 : return "Don't you think you're overreacting a bit?\n"; + case 13 : return "I don't see what the big deal is.\n"; + case 14 : return "Take it easy. It's not that bad.\n"; + case 15 : return "Are you getting angry?\n"; + case 16 : return "Why is such a small thing making you upset?\n"; + case 17 : return "I don't see why you're getting annoyed.\n"; + } +} + +char *because_resp() +{ + int i = randnum(12); + switch (i) { + case 1 : return "Is that the real reason?\n"; + case 2 : return "I don't see the connection.\n"; + case 3 : return "What kind of an explanation is that?\n"; + case 4 : return "What does that have to do with it?\n"; + case 5 : return "That justification is a bit shaky to me.\n"; + case 6 : return "I don't see the point.\n"; + case 7 : return "I don't see that as a good reason.\n"; + case 8 : return "Are you happy with that justification?\n"; + case 9 : return "Are you sure?\n"; + case 10 : return "I don't understand.\n"; + case 11 : return "What does one thing have to do with the other?\n"; + case 12 : return "I don't see how that's related.\n"; + } +} + +char *yes_resp() +{ + int i = randnum(21); + switch (i) { + case 1 : return "Are you sure?\n"; + case 2 : return "Are you positive about that?\n"; + case 3 : return "How can you be so sure?\n"; + case 4 : return "Let's not jump to conclusions now.\n"; + case 5 : return "I don't see the connection.\n"; + case 6 : return "Have you considered all the possibilities?\n"; + case 7 : return "I'm still not convinced.\n"; + case 8 : return "Think about what you've just said.\n"; + case 9 : return "What are the implications of this?\n"; + case 10 : return "So what have we concluded?\n"; + case 11 : return "What does this mean?\n"; + case 12 : return "What do you mean?\n"; + case 13 : return "I'm having trouble understanding your argument.\n"; + case 14 : return "I don't see where you're coming from.\n"; + case 15 : return "You think so?\n"; + case 16 : return "Really?\n"; + case 17 : return "Is that right?\n"; + case 18 : return "Oh?\n"; + case 19 : return "Are you certain of this?\n"; + case 20 : return "I read you loud and clear.\n"; + case 21 : return "Yes?\n"; + } +} + +char *neg_resp() +{ + int i = randnum(11); + switch (i) { + case 1 : return "Why not?\n"; + case 2 : return "How come?\n"; + case 3 : return "No?\n"; + case 4 : return "Is there a reason why not?\n"; + case 5 : return "No?\n"; + case 6 : return "Why don't you think so?\n"; + case 7 : return "I don't see why not.\n"; + case 8 : return "What could be the reasons for this?\n"; + case 9 : return "Do you really believe this?\n"; + case 10 : return "You're not sure?\n"; + case 11 : return "That's a rather pessimistic attitude.\n"; + } +} + +char *go_on() +{ + int i = randnum(20); + switch (i) { + case 1 : return "Go on.\n"; + case 2 : return "I see.\n"; + case 3 : return "Keep going.\n"; + case 4 : return "Please continue.\n"; + case 5 : return "I'm listening.\n"; + case 6 : return "Can you elaborate on that?\n"; + case 7 : return "I understand.\n"; + case 8 : return "Oh?\n"; + case 9 : return "Is that right?\n"; + case 10 : return "Really?\n"; + case 11 : return "No, really?\n"; + case 12 : return "That's interesting.\n"; + case 13 : return "I'm finding this very informative.\n"; + case 14 : return "This is all very revealing.\n"; + case 15 : return "Don't hesitate to be honest with me.\n"; + case 16 : return "Don't hold anything back now.\n"; + case 17 : return "That's an interesting observation.\n"; + case 18 : return "I don't understand.\n"; + case 19 : return "I'm starting to get the big picture.\n"; + case 20 : return "And?\n"; + } +} + +char *always_resp() +{ + int i = randnum(10); + switch (i) { + case 1 : return "Can you think of a specific example?\n"; + case 2 : return "When?\n"; + case 3 : return "Really, always?\n"; + case 4 : return "Are you sure you can generalize like that?\n"; + case 5 : return "Isn't that a bit of an oversimplification?\n"; + case 6 : return "Be careful not to jump to conclusions now.\n"; + case 7 : return "All the time?\n"; + case 8 : return "So you're saying that this is happens quite often.\n"; + case 9 : return "Does this happen a lot?\n"; + case 10 : return "On what occassions?\n"; + } +} + +char *alike_resp() +{ + int i = randnum(4); + switch (i) { + case 1 : return "In what way?\n"; + case 2 : return "What resemblance do you see?\n"; + case 3 : return "What similarities are you thinking of?\n"; + case 4 : return "Specifically, what do you mean by this.\n"; + } +} + +char *fam_resp() +{ + int i = randnum(7); + switch (i) { + case 1 : return "Tell me more about your family.\n"; + case 2 : return "Please go on about your family.\n"; + case 3 : return "How was your home life when you were young?\n"; + case 4 : return "How do you get along with your parents?\n"; + case 5 : return "Would you say you have family problems?\n"; + case 6 : return "Your family interests me.\n"; + case 7 : return "Let`s talk some more about your family.\n"; + } +} + +char *family_resp() +{ + int i = randnum(5); + switch (i) { + case 1 : return "Earlier you were speaking of your %s.\n"; + case 2 : return "Tell me more about your %s.\n"; + case 3 : return "Do you think your %s ties into all this?\n"; + case 4 : return "How would your %s feel about this?\n"; + case 5 : return "Does your %s feel the same way?\n"; + } +} + +char *i_am_resp() +{ + int i = randnum(6); + switch (i) { + case 1 : return "Would you like to think that%s?\n"; + case 2 : return "Why do you say that%s?\n"; + case 3 : return "What leads you to believe that%s?\n"; + case 4 : return "What do you mean \"%s\"?\n"; + case 5 : return "You really feel that%s?\n"; + case 6 : return "Would it make you feel better if%s?\n"; + } +} + +char *sad1_word_resp() +{ + int i = randnum(5); + switch (i) { + case 1 : return "I am sorry to hear that%s.\n"; + case 2 : return "What are you going to do about the fact that%s?\n"; + case 3 : return "Why do you think%s?\n"; + case 4 : return "What gives you the impression that%s?\n"; + case 5 : return "Are you sure that%s?\n"; + } +} + +char *sad2_word_resp() +{ + int i = randnum(5); + switch (i) { + case 1 : return "I am sorry to hear that%s are feeling%s.\n"; + case 2 : return "What are you going to do about the fact that%s?\n"; + case 3 : return "Why do you think%s?\n"; + case 4 : return "What gives you the impression that%s?\n"; + case 5 : return "Are you sure that%s?\n"; + } +} + +char *command_resp() +{ + int i = randnum(21); + switch (i) { + case 1 : return "Why do you ask?\n"; + case 2 : return "Why should I?\n"; + case 3 : return "Why do you want me to?\n"; + case 4 : return "Do you think that's relevant?\n"; + case 5 : return "Can you rephrase that?\n"; + case 6 : return "I'm not sure I understand what you want.\n"; + case 7 : return "I don't see what you're asking.\n"; + case 8 : return "What are you asking?\n"; + case 9 : return "What do you mean?\n"; + case 10 : return "What?\n"; + case 11 : return "Are you sure that's what you want to know?\n"; + case 12 : return "Why do you want to know?\n"; + case 13 : return "What's it to you?\n"; + case 14 : return "I don't think that's important.\n"; + case 15 : return "That has little to do with the real issue.\n"; + case 16 : return "What's the significance you your question?\n"; + case 17 : return "Could that question be hiding a deeper intent?\n"; + case 18 : return "If I did that, what would it mean to you?\n"; + case 19 : return "Why is this important to you?\n"; + case 20 : return "That's not really important.\n"; + case 21 : return "That seems to have little to do with this.\n"; + } +} + +char *you_resp() +{ + int i = randnum(9); + switch (i) { + case 1 : return "Let's talk about you, not me.\n"; + case 2 : return "I'm not the one we came here to talk about.\n"; + case 3 : return "I don't find myself that interesting. Let's talk about you.\n"; + case 4 : return "I'd prefer to talk about you, not me.\n"; + case 5 : return "Why are you interested in me?\n"; + case 6 : return "I want to talk about you for a change.\n"; + case 7 : return "I'd rather not talk about myself.\n"; + case 8 : return "Enough about me.\n"; + case 9 : return "Let's talk about something other than myself.\n"; + } +} + +char *you_know() +{ + int i = randnum(13); + switch (i) { + case 1 : return "I don't know. What do you think?\n"; + case 2 : return "You tell me.\n"; + case 3 : return "I think you know the answer to that.\n"; + case 4 : return "Can you tell me?\n"; + case 5 : return "What do you think?\n"; + case 6 : return "Can you answer that yourself?\n"; + case 7 : return "If you give it some thought, you should know.\n"; + case 8 : return "Maybe you already know the answer to that.\n"; + case 9 : return "Perhaps you already know.\n"; + case 10 : return "If we keep talking, maybe we'll find out.\n"; + case 11 : return "Perhaps that will be brought out in this discussion.\n"; + case 12 : return "Let's find the answer out together.\n"; + case 13 : return "I'm sure we can work out the answer to that.\n"; + } +} + +char *old_fact() +{ + int i = randnum(4); + switch (i) { + case 1 : return "Earlier you said that%s %s%s.\n"; + case 2 : return "Could this have anything to do with the fact that%s %s%s?\n"; + case 3 : return "What does that have to do with your saying that%s %s%s?\n"; + case 4 : return "Didn't you just say that%s %s%s?\n"; + } +} diff --git a/zpu/roadshow/roadshow/games/eliza/response.h b/zpu/roadshow/roadshow/games/eliza/response.h new file mode 100644 index 0000000..8cc77e9 --- /dev/null +++ b/zpu/roadshow/roadshow/games/eliza/response.h @@ -0,0 +1,41 @@ +/* +Copyright (C) 1988-2003 by Mohan Embar + +http://www.thisiscool.com/ +DISCLAIMER: This was written in 1988. I don't code like this anymore! + +This program is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free Software +Foundation; either version 2 of the License, or (at your option) any later version. + +This program is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A +PARTICULAR PURPOSE. See the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along with +this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, +Cambridge, MA 02139, USA. +*/ + +/* Functions which return responses */ + +/* Generic question */ +char *question(); +char *b_word_resp(); +char *n_word_resp(); +char *because_resp(); +char *yes_resp(); +char *neg_resp(); +char *go_on(); +char *always_resp(); +char *alike_resp(); +char *fam_resp(); +char *family_resp(); +char *i_am_resp(); +char *sad1_word_resp(); +char *sad2_word_resp(); +char *command_resp(); +int randnum(); +char *you_resp(); +char *you_know(); +char *old_fact(); diff --git a/zpu/roadshow/roadshow/games/sumeria.bin b/zpu/roadshow/roadshow/games/sumeria.bin new file mode 100644 index 0000000..04e5751 Binary files /dev/null and b/zpu/roadshow/roadshow/games/sumeria.bin differ diff --git a/zpu/roadshow/roadshow/games/sumeria.c b/zpu/roadshow/roadshow/games/sumeria.c new file mode 100644 index 0000000..7171adf --- /dev/null +++ b/zpu/roadshow/roadshow/games/sumeria.c @@ -0,0 +1,444 @@ +/* Govern ancient Sumeria. Heavily modified by Mike Arnautov 1975. + * Converted from Basic to PR1ME Fortran (mode 32R) MLA 1979. + * Rev.19.1, GGR version 14 Oct 83. MLA + * Converted to ANSI C December 2001. MLA + */ + +#include +#include +#include + +int year_term; +int year_abs; +int percent_starved; +int dead_total; +int starved; +int population; + +char reply [160]; + +void try_again (int reason) +{ + if (reason == 1) + puts ("For the extreme folly of soft - heartedness and"); + if (reason) + { + printf ("%considering ", reason == 3 ? 'C' : 'c'); + puts ("the mess you would leave the city in,"); + puts ("you are hereby commanded to remain in office for"); + puts ("another ten years. May your fate be a lesson and"); + puts ("a warning for generations to come."); + } + else + { + puts ("Hamurabe, you are either a politico-economic genius"); + puts ("or just a lucky bastard. There being but one way to"); + puts ("settle the question, you are hereby requested to stay"); + puts ("in office for another ten years."); + } + year_term = 0; + year_abs--; + percent_starved = starved * 100.0 / population; + dead_total = starved; +} + +float rnd (void) +{ + return ((rand () % 1000) / 1000.0); +} + +int iabs (int value) +{ + return ((value >= 0) ? value : -value); +} + +void terminate (int abort) +{ + if (abort == 2) + { + puts ("For this extreme mismanagement you have been"); + puts ("deposed, flayed alive and publicly beheaded."); + puts ("\nMay Ashtaroth preserve your Ka.\n"); + } + else if (abort == 1) + { + puts ("\nHamurabe: I find myself unable to fulfil your wish."); + puts ("You will have to find yourself another kingdom."); + } + if (abort != 2) + puts ("\nMay Baal be with you.\n"); + exit (0); +} + +void think_again (char *what, int quantity) +{ + if (*what == 'l' || *what == 'g') + printf ("Hamurabe, think again. "); + if (*what == 'l') + printf ("You own %d acres of land.", quantity); + else if (*what == 'g') + printf ("You have only %d bushels of grain.", quantity); + else + printf ("But you only have %d people to tend the fields.", population); + puts (" Now then,"); +} +int query (char *prompt) +{ + while (1) + { + int sign; + int value; + char * cptr; + + printf (prompt); + fgets (reply, sizeof (reply) - 1, stdin); + value = 0; + sign = 1; + cptr = reply; + while (*cptr == ' ' || *cptr == '\t') cptr++; + if (*cptr == '-') + { + cptr++; + sign = -1; + } + if (*cptr == 'q' || *cptr == 'Q') + terminate (1); + while (*cptr && *cptr != '\n') + { + if (*cptr >= '0' && *cptr <= '9') + value = 10 * value + *cptr - '0'; + else if (*cptr == '.') + break; + else if (*cptr != '.') + { + sign = 0; + break; + } + cptr++; + } + if (sign) + return (sign * value); + puts ("Hamurabe, your command has not been understood!"); + } +} + +int main () +{ + int acreage; + int immigration; + int second_term; + int dead_total; + int stores; + int harvest; + int rat_food; + int yield; + int rounded_price; + int sell; + int buy; + int plant; + int food; + int transaction; + int rats; + int plague_deaths; + int survived; + int dead_rats; + int tmp_int; + + float price; + float breadline; + float provisions; + float plague; + float acres_per_head; + float acres_per_init; + float stores_per_head; + float rats_ate; + float rat_log; + float percent_starved; + float tmp_float; + + printf ("[Sumeria (Primos) rev.19.1, GGR (MLA) version 14 Oct 83]\n"); + puts ("[Conversion to ANSI C: MLA, Feb 2002]\n"); + while (1) + { + printf ("Do you know how to play? "); + fgets (reply, sizeof(reply) - 1, stdin); + if (*reply == '\n') break; + *reply += (*reply < 'a') ? 'a' - 'A' : 0; + if (*reply == 'y') break; + if (*reply != 'n' && *reply != 'q') continue; + puts ("\nToo bad!\n"); + break; + } + + srand (time (NULL)); + *(reply + sizeof (reply) - 1) = '\0'; + + puts ("Try your hand at governing ancient Sumeria"); + puts ("for a ten year term of office."); + + second_term = 0; + dead_total = 0; + percent_starved = 0; + year_term = 0; + year_abs = 0; + acres_per_init = 10; + population = 100; + stores = 2800; + harvest = 3000; + rat_food = 200; + yield = 3; + acreage = 1000; + immigration = 5; + transaction = 0; + price = 18 + 6 * rnd (); + breadline = 19 + 4 * rnd (); + provisions = breadline; + rats = 1000; + rat_log = 3; + plague = rnd () / 2; + starved = 0; + +year_term = year_abs = 9; + while (1) + { + + while (1) + { + year_term++; + year_abs++; + putchar ('\n'); + acres_per_head = ((float) acreage) / population; + stores_per_head = ((float) stores) /population; + puts ("Hamurabe: I beg to report to you,"); + printf ("In year %d, ", year_abs); + if (starved > 0) + printf ("%ld", starved); + else + printf ("no"); + printf (" %s starved, %ld came to the city.\n", + starved <= 1 ? "person" : "people", immigration); + if (plague >= 0.85) + printf ("A horrible plague struck! %d people died.\n", + plague_deaths); + printf ("Population is now %ld.\n", population); + printf ("The city owns %ld acres.\n", acreage); + printf ("You harvested %ld bushels per acre.\n", yield); + printf ("Rats ate %ld bushels.\n", rat_food); + printf ("You now have %ld bushels in store.\n\n", stores); + + if (year_term == 11) + break; + rounded_price = price + 0.5; + printf ("Land is trading at %ld bushels per acre.\n\n", rounded_price); + + while (1) + { + buy = query ("How many acres do you wish to buy? "); + if (rounded_price * buy <= stores) + break; + think_again ("grain", stores); + } + if (buy > 0) + { + acreage += + buy; + stores -= rounded_price * buy; + transaction = buy; + } + else + { + while (1) + { + sell = query ("How many acres do you wish to sell? "); + if (sell <= acreage) + break; + think_again ("land", acreage); + } + acreage -= sell; + stores += rounded_price * sell; + transaction = -sell; + } + + putchar ('\n'); + while (1) + { + food = query ("How many bushels do you wish to feed your people? "); + if (food <= stores) + break; + think_again ("grain", stores); + } + stores -= food; + putchar ('\n'); + while (1) + { + plant = query ("How many acres do you wish to plant with seed? "); + if (plant <= acreage && plant <= 2 * stores && + plant <= 10 * population) + break; + if (plant > acreage) + think_again ("land", acreage); + else if (plant > 2 * stores) + think_again ("grain", stores); + else + think_again ("people", population); + } + + stores -= plant / 2; + yield = 4 * rnd() + 1.65; + harvest = plant * yield; + rat_food = 0; + rats_ate = stores * (rat_log - 2.2) / 3.6; + dead_rats = rats - 4 * rats_ate; + rats = 3 * rats; + if (dead_rats > 0) rats = rats - dead_rats; + + if (plague >= 0.3) + { + if (plague >= 0.85) + { + if (plague > 1) plague = 1; + rats = 500 + 5000 * (plague - 0.7); + } + else + rats *= 1.225 - 0.75 * plague; + } + + if (rats < 500) + rats = 500; + rat_food = rats / 4; + if (rats_ate < rat_food) + rat_food = rats_ate; + rat_food *= 7; + if (rat_food <= 20) + rat_food = 20 + 30 * rnd(); + stores += harvest - rat_food; + rat_log = log10 (1.0 * rats); + if (stores + stores <= harvest) + { + rat_food = harvest * (1 + rnd()) / 4.0; + stores = harvest - rat_food; + } + + tmp_int = 100 + iabs (100 - population); + immigration = tmp_int * ((acres_per_head + + stores_per_head - 36) / 250.0 + + (provisions - breadline + 2.5) / 40) + .5; + if (immigration <= 0) + immigration = 5 * rnd() + 1; + survived = food / breadline; + provisions = (1.0 * food) / population; + plague = (2 * rnd() + rat_log - 3) / 3.0; + if (population < survived) + survived = population; + else + { + starved = population - survived; + if (starved >= 0.45 * population) + { + printf ("\nYou starved %d people in one year!\n", starved); + terminate (2); + } + percent_starved = ((year_term - 1) * percent_starved + + 100.0 * starved / population) / year_term; + population = survived; + dead_total += starved; + } + population += immigration; + price = (price + 15 + (stores_per_head - acres_per_head) / 3) / 2 + + transaction / 50 + 3 * rnd() - 2; + if (price <1.0) price = 1.0; + if (plague >= 0.85) + { + plague_deaths = population * (0.429 * plague - 0.164); + population -= plague_deaths; + } + } + + printf ("In your ten year term of office %d people starved.\n", + dead_total); + printf ("You started with %0.2f acres per person and ended\n", + acres_per_init); + acres_per_head = (1.0 * acreage) / population; + acres_per_init = acres_per_head; + printf ("with %0.2f acres per person.\n\n", acres_per_head); + + tmp_float = 10 * acres_per_head / 3; + if (percent_starved > 25) + terminate (2); + if (percent_starved <= 7) + { + try_again (1); + continue; + } + if (tmp_float < 7) + terminate (2); + if (tmp_float > 10) + { + puts ("Your heavy handed performance smacks of Nabuchodonoser"); + puts ("and Asurbanipal II. The surviving populace hates your"); + puts ("guts and your eventual assasination is just a matter of"); + puts ("time."); + terminate (0); + } + puts ("Consequently you have been deposed and disgraced"); + puts ("and only avoided a public punishment because"); + puts ("of mitigating circumstances. While it may be"); + puts ("admitted in private that you had a rotten deal"); + tmp_int = 3 * rnd(); + if (tmp_int == 0) + puts ("try explaining that to a mob looking for scape-goats."); + if (tmp_int == 1) + puts ("history is not interested in such petty excuses."); + if (tmp_int == 2) + { + puts ("you should have considered such occupational hazards"); + puts ("before applying for the job."); + } + terminate (0); + + if (acres_per_head < 7) + { + try_again (1); + continue; + } + if (acres_per_head < 9) + { + puts ("Your performance has been satisfactory and, in the"); + puts ("perspective of history, actually quite good."); + if (rnd() >= 0.5) + { + puts ("You may not be exactly popular, but given a good"); + puts ("body-guard there is nothing to be really worried about."); + } + else + { + puts ("While not exactly loved, you are at least respected."); + puts ("What more can a realistic ruler ask for?"); + } + } + else if (second_term == 0) + + if (second_term == 0) + { + if (stores <= 10 * population) + { + try_again (3); + continue; + } + second_term = 1; + try_again (0); + continue; + } + else + { + puts ("Hamurabe, your name will be remembered through the"); + puts ("ages to come with admiration and respect.\n"); + puts ("(So you did get away with it you lucky sod!)"); + } + if (stores > 10 * population) + terminate (0); + puts ("\n HOWEVER\n\n"); + second_term = 0; + try_again (2); + continue; + } +} diff --git a/zpu/roadshow/roadshow/games/sumeria.zpu b/zpu/roadshow/roadshow/games/sumeria.zpu new file mode 100644 index 0000000..0e6b41d Binary files /dev/null and b/zpu/roadshow/roadshow/games/sumeria.zpu differ diff --git a/zpu/roadshow/roadshow/helloworld/build.sh b/zpu/roadshow/roadshow/helloworld/build.sh new file mode 100644 index 0000000..8069e36 --- /dev/null +++ b/zpu/roadshow/roadshow/helloworld/build.sh @@ -0,0 +1,6 @@ +zpu-elf-gcc test.c -o test.elf -phi +zpu-elf-objcopy -O binary test.elf test.bin +sh ../build/makefirmware.sh ../build/ic300.bit test.zpu test.bin + + + diff --git a/zpu/roadshow/roadshow/helloworld/test.bin b/zpu/roadshow/roadshow/helloworld/test.bin new file mode 100644 index 0000000..540ccaf Binary files /dev/null and b/zpu/roadshow/roadshow/helloworld/test.bin differ diff --git a/zpu/roadshow/roadshow/helloworld/test.c b/zpu/roadshow/roadshow/helloworld/test.c new file mode 100644 index 0000000..8c33640 --- /dev/null +++ b/zpu/roadshow/roadshow/helloworld/test.c @@ -0,0 +1,11 @@ +int main(int argc, char **argv) +{ + for (;;) + { + int c; + printf("Hello world!\n"); + printf("Press any key!\n"); + c=inbyte(); + printf("You pressed (%02x) '%c'\n", c, c); + } +} diff --git a/zpu/roadshow/roadshow/helloworld/test.elf b/zpu/roadshow/roadshow/helloworld/test.elf new file mode 100644 index 0000000..bc362ae Binary files /dev/null and b/zpu/roadshow/roadshow/helloworld/test.elf differ diff --git a/zpu/roadshow/roadshow/helloworld/test.zpu b/zpu/roadshow/roadshow/helloworld/test.zpu new file mode 100644 index 0000000..1bee302 Binary files /dev/null and b/zpu/roadshow/roadshow/helloworld/test.zpu differ diff --git a/zpu/roadshow/roadshow/hwtest/build.sh b/zpu/roadshow/roadshow/hwtest/build.sh new file mode 100644 index 0000000..115b24a --- /dev/null +++ b/zpu/roadshow/roadshow/hwtest/build.sh @@ -0,0 +1,6 @@ +zpu-elf-gcc -nostdlib test.S -o test.elf +zpu-elf-objcopy -O binary test.elf test.bin +sh makefirmware.sh ic300.bit test.zpu test.bin + + + diff --git a/zpu/roadshow/roadshow/hwtest/test.S b/zpu/roadshow/roadshow/hwtest/test.S new file mode 100644 index 0000000..ac13be3 --- /dev/null +++ b/zpu/roadshow/roadshow/hwtest/test.S @@ -0,0 +1,19 @@ +_loop: + im 0x5a ; write Z to UART + nop + im 0x080a000c + store + ; increaase counter + im _test + load + im 1 + add + im _test + store + + + im _loop + poppc ; loop + + .align 4 +_test: .long 1 diff --git a/zpu/roadshow/roadshow/hwtest/test.bin b/zpu/roadshow/roadshow/hwtest/test.bin new file mode 100644 index 0000000..4b593ee Binary files /dev/null and b/zpu/roadshow/roadshow/hwtest/test.bin differ diff --git a/zpu/roadshow/roadshow/hwtest/test.elf b/zpu/roadshow/roadshow/hwtest/test.elf new file mode 100644 index 0000000..a2ccbc1 Binary files /dev/null and b/zpu/roadshow/roadshow/hwtest/test.elf differ diff --git a/zpu/roadshow/roadshow/hwtest/test.zpu b/zpu/roadshow/roadshow/hwtest/test.zpu new file mode 100644 index 0000000..7d8da42 Binary files /dev/null and b/zpu/roadshow/roadshow/hwtest/test.zpu differ diff --git a/zpu/roadshow/roadshow/images/bootloader.phi b/zpu/roadshow/roadshow/images/bootloader.phi new file mode 100644 index 0000000..a0a1918 Binary files /dev/null and b/zpu/roadshow/roadshow/images/bootloader.phi differ diff --git a/zpu/roadshow/roadshow/images/dhrystone.zpu b/zpu/roadshow/roadshow/images/dhrystone.zpu new file mode 100644 index 0000000..e37e59f Binary files /dev/null and b/zpu/roadshow/roadshow/images/dhrystone.zpu differ diff --git a/zpu/roadshow/roadshow/images/eliza.zpu b/zpu/roadshow/roadshow/images/eliza.zpu new file mode 100644 index 0000000..d916270 Binary files /dev/null and b/zpu/roadshow/roadshow/images/eliza.zpu differ diff --git a/zpu/roadshow/roadshow/images/ic300.bit b/zpu/roadshow/roadshow/images/ic300.bit new file mode 100644 index 0000000..cbbc2b6 Binary files /dev/null and b/zpu/roadshow/roadshow/images/ic300.bit differ diff --git a/zpu/roadshow/roadshow/images/net_test.zpu b/zpu/roadshow/roadshow/images/net_test.zpu new file mode 100644 index 0000000..9083cad Binary files /dev/null and b/zpu/roadshow/roadshow/images/net_test.zpu differ diff --git a/zpu/roadshow/roadshow/images/sumeria.zpu b/zpu/roadshow/roadshow/images/sumeria.zpu new file mode 100644 index 0000000..0e6b41d Binary files /dev/null and b/zpu/roadshow/roadshow/images/sumeria.zpu differ diff --git a/zpu/roadshow/roadshow/iss/index.html b/zpu/roadshow/roadshow/iss/index.html new file mode 100644 index 0000000..0b91a6a --- /dev/null +++ b/zpu/roadshow/roadshow/iss/index.html @@ -0,0 +1,14 @@ + + +

ISS test

+
    +
  1. Launch ISS
    +java -Xmx512m -cp simulator.jar com.zylin.zpu.simulator.SimApp 4444 false +
  2. Launch debugger
    +zpu-elf-gdb hello.elf
    +
  3. Connect to ISS
    +target remote localhost:4444 +
+ + + diff --git a/zpu/roadshow/roadshow/iss/simulator.jar b/zpu/roadshow/roadshow/iss/simulator.jar new file mode 100644 index 0000000..8cf63a8 Binary files /dev/null and b/zpu/roadshow/roadshow/iss/simulator.jar differ diff --git a/zpu/roadshow/roadshow/net_test/.cvsignore b/zpu/roadshow/roadshow/net_test/.cvsignore new file mode 100644 index 0000000..66dac94 --- /dev/null +++ b/zpu/roadshow/roadshow/net_test/.cvsignore @@ -0,0 +1,8 @@ +output +all.txt +dis.txt +gmon.out +ll.txt +prof.txt +net_test.txt +gmon.sum diff --git a/zpu/roadshow/roadshow/net_test/http_pages.c b/zpu/roadshow/roadshow/net_test/http_pages.c new file mode 100644 index 0000000..437dad8 --- /dev/null +++ b/zpu/roadshow/roadshow/net_test/http_pages.c @@ -0,0 +1,206 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static cyg_bool isUnsignedHex(char *string) +{ + int i = 0; + for(i = 0; string[i] != '\0'; i++) + if(!( ('0' <= string[i] && string[i] <= '9') || + ('a' <= string[i] && string[i] <= 'f') || + ('A' <= string[i] && string[i] <= 'F') )) + return 0; + return 1; +} + +static cyg_bool net_test_mac_handler(FILE *client, char *filename, char *formdata, void *arg) +{ + char error_string[50]; + + error_string[0] = '\0'; + + if( formdata != NULL ) + { + char *formlist[1]; + char *mac_string = NULL; + /* Parse the data */ + cyg_formdata_parse( formdata, formlist, 1 ); + mac_string = cyg_formlist_find( formlist, "mac"); + if(mac_string != NULL) + { + + if(!isUnsignedHex(mac_string)) + { + sprintf(error_string, "Please enter digits between 0-9 and a-f"); + } + else if(strlen(mac_string) != 12) + { + sprintf(error_string, "Please enter a 12 digit MAC address"); + } + else + { + char temp = '\0'; + int fd = -1; + cyg_uint8 mac_addr[6]; + error_string[0] = '\0'; + + temp = mac_string[2]; + mac_string[2] = '\0'; + mac_addr[0] = strtol(mac_string, NULL, 16); + mac_string[2] = temp; + + temp = mac_string[4]; + mac_string[4] = '\0'; + mac_addr[1] = strtol(mac_string, NULL, 16); + mac_string[4] = temp; + + temp = mac_string[6]; + mac_string[6] = '\0'; + mac_addr[2] = strtol(mac_string, NULL, 16); + mac_string[6] = temp; + + temp = mac_string[8]; + mac_string[8] = '\0'; + mac_addr[3] = strtol(mac_string, NULL, 16); + mac_string[8] = temp; + + temp = mac_string[10]; + mac_string[10] = '\0'; + mac_addr[4] = strtol(mac_string, NULL, 16); + mac_string[10] = temp; + + temp = mac_string[12]; + mac_string[12] = '\0'; + mac_addr[5] = strtol(mac_string, NULL, 16); + mac_string[12] = temp; + + /*write it to flash*/ + fd = creat("/jffs2/mac", O_TRUNC | O_CREAT); + if(fd < 0) + { + sprintf(error_string, "%n %s", errno, strerror(errno) ); + } + else + { + write(fd, mac_addr, 6); + close(fd); + fd = -1; + //CYGACC_CALL_IF_RESET(); + } + } + } + } + + html_begin(client); + + html_head(client,"Changing MAC Address", ""); + + html_body_begin(client,""); + { + fputs(error_string, client); + fputs("
\n", client); + html_form_begin( client, "/mac", "" ); + { + fputs( "Enter the new mac address in the format xxxxxxxxxxxx ", client ); + html_form_input( client, "mac", "mac", "", ""); + } + html_form_end(client); + } + html_body_end(client); + + html_end(client); + + return 1; +} + +CYG_HTTPD_TABLE_ENTRY( net_test_mac, + "/mac", + net_test_mac_handler, + NULL ); + + +static cyg_bool net_test_ip_handler(FILE *client, char *filename, char *formdata, void *arg) +{ + int fd = -1; + char error_string[50]; + char error_string2[50]; + + error_string[0] = '\0'; + error_string2[0] = '\0'; + if( formdata != NULL ) + { + char *formlist[1]; + char *ip_string = NULL; + /* Parse the data */ + cyg_formdata_parse( formdata, formlist, 1 ); + ip_string = cyg_formlist_find( formlist, "ip"); + if(ip_string != NULL) + { + /*write it to flash*/ + fd = creat("/jffs2/ip", O_TRUNC | O_CREAT); + if(fd < 0) + { + sprintf(error_string, "%n %s", errno, strerror(errno) ); + } + else + { + write(fd, ip_string, strlen(ip_string)); + close(fd); + fd = -1; + } + } + } + html_begin(client); + + html_head(client,"Changing IP Address", ""); + + html_body_begin(client,""); + { + char value[81]; + value[0] = '\0'; + fd = open("/jffs2/ip", O_RDONLY); + if(fd < 0) + { + sprintf(error_string2, "%n %s", errno, strerror(errno) ); + } + else + { + int len = read(fd, value, 80); + value[len] = '\0'; + close(fd); + fd = -1; + } + fputs(error_string, client); + fputs("
\n", client); + fputs(error_string2, client); + fputs("
\n", client); + html_form_begin( client, "/ip", "" ); + { + fputs( "Enter the new address in the following order: IP_mask_broadcast_gateway_server ", client ); + fputs("
\n", client); + html_form_input( client, "ip", "ip", value, ""); + } + html_form_end(client); + } + html_body_end(client); + + html_end(client); + + return 1; +} + +CYG_HTTPD_TABLE_ENTRY( net_test_ip, + "/ip", + net_test_ip_handler, + NULL ); + diff --git a/zpu/roadshow/roadshow/net_test/init.cpp b/zpu/roadshow/roadshow/net_test/init.cpp new file mode 100644 index 0000000..b5805b2 --- /dev/null +++ b/zpu/roadshow/roadshow/net_test/init.cpp @@ -0,0 +1,52 @@ +#include +#include +#include +#include + +#if 0 +externC int chdir(const char *); + +/* ================================================================= */ +/* Initialization object + */ + +class NetTestInit +{ +public: + NetTestInit(); +}; + +/* ----------------------------------------------------------------- */ +/* Static initialization object instance. The constructor is + * prioritized to run after any filesystem constructors. + */ +static NetTestInit netTestInitializer CYGBLD_ATTRIB_INIT_PRI(CYG_INIT_IO_FS + 1); + +/* ----------------------------------------------------------------- */ +/* Constructor, mounts the file system + */ + +NetTestInit::NetTestInit() +{ + int err = 0; + err = mount( "/dev/flash1", "/jffs2", "jffs2" ); + if(err < 0) + { + diag_printf("unable to mount jffs\n"); + } + else + { + diag_printf("mounted jffs\n"); + } + err = mount( "", "/ramfs", "ramfs" ); + if(err < 0) + { + diag_printf("unable to mount ramfs\n"); + } + else + { + diag_printf("mounted ramfs\n"); + } + chdir( "/ramfs" ); +} +#endif diff --git a/zpu/roadshow/roadshow/net_test/makefile b/zpu/roadshow/roadshow/net_test/makefile new file mode 100644 index 0000000..877afab --- /dev/null +++ b/zpu/roadshow/roadshow/net_test/makefile @@ -0,0 +1,41 @@ +PROJECTNAME = net_test +OUT= output +ECOS_DIR=$(OUT)/ecos +INSTALL_DIR=$(ECOS_DIR)/install + +.symbolic: all clean ecos + +all: ecos app + + + +clean: + rm -rf $(OUT)/* + +$(OUT): + mkdir $(OUT) + +$(ECOS_DIR)/ecos.ecc $(INSTALL_DIR)/include/pkgconf/ecos.mak: + mkdir -p $(ECOS_DIR) + cd $(ECOS_DIR) && ecosconfig new zpuetherphi minimal + cd $(ECOS_DIR) && ecosconfig import ../../$(PROJECTNAME).ecm + cd $(ECOS_DIR) && ecosconfig tree + cd $(ECOS_DIR) && make -s headers + +$(OUT)/ecostree: $(ECOS_DIR)/ecos.ecc + cd $(ECOS_DIR) && ecosconfig tree + echo >$(OUT)/ecostree + +ecos $(INSTALL_DIR)/lib/libtarget.a $(INSTALL_DIR)/lib/vectors.o: $(OUT)/ecostree + cd $(ECOS_DIR) && make -s + +app: + make -f $(INSTALL_DIR)/include/pkgconf/ecos.mak -f makefile $(OUT)/$(PROJECTNAME).bin + +$(OUT)/$(PROJECTNAME).bin: *.c makefile + zpu-elf-gcc -I$(INSTALL_DIR)/include $(ECOS_GLOBAL_CFLAGS) $(ECOS_GLOBAL_LDFLAGS) -L$(INSTALL_DIR)/lib *.c* -o $(OUT)/$(PROJECTNAME).elf -Wl,-Map,$(OUT)/$(PROJECTNAME).map -nostartfiles -nostdlib -Ttarget.ld -lstdc++ -lsupc++ + zpu-elf-objcopy -O binary $(OUT)/$(PROJECTNAME).elf $(OUT)/$(PROJECTNAME).bin + sh ../build/makefirmware.sh $(OUT)/$(PROJECTNAME).bin $(OUT)/$(PROJECTNAME).zpu + zpu-elf-size $(OUT)/$(PROJECTNAME).elf + + \ No newline at end of file diff --git a/zpu/roadshow/roadshow/net_test/net_test.ecm b/zpu/roadshow/roadshow/net_test/net_test.ecm new file mode 100644 index 0000000..5b32991 --- /dev/null +++ b/zpu/roadshow/roadshow/net_test/net_test.ecm @@ -0,0 +1,237 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware zpuetherphi ; + template default ; + package -hardware CYGPKG_HAL_ZYLIN current ; + package -hardware CYGPKG_HAL_ZYLIN_ZPU current ; + package -hardware CYGPKG_HAL_ZYLIN_ZPU_PHI current ; + package -hardware CYGPKG_IO_ETH_DRIVERS current ; + package -hardware CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC current ; + package -hardware CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_IO current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_ERROR current ; + package -template CYGPKG_ISOINFRA current ; + package -template CYGPKG_IO_SERIAL current ; + package -template CYGPKG_KERNEL current ; + package -template CYGPKG_MEMALLOC current ; + package -template CYGPKG_LIBC current ; + package -template CYGPKG_LIBC_I18N current ; + package -template CYGPKG_LIBC_SETJMP current ; + package -template CYGPKG_LIBC_SIGNALS current ; + package -template CYGPKG_LIBC_STARTUP current ; + package -template CYGPKG_LIBC_STDIO current ; + package -template CYGPKG_LIBC_STDLIB current ; + package -template CYGPKG_LIBC_STRING current ; + package -template CYGPKG_LIBC_TIME current ; + package -template CYGPKG_LIBM current ; + package -template CYGPKG_IO_WALLCLOCK current ; + package CYGPKG_NET_FREEBSD_STACK current ; + package CYGPKG_IO_FILEIO current ; + package CYGPKG_NET current ; + package CYGPKG_HTTPD current ; +}; + +cdl_component CYGPKG_IO_ETH_DRIVERS_STAND_ALONE { + inferred_value 0 +}; + +cdl_option CYGINT_DEVS_ETH_OPENCORES_ETHERMAC_TxNUM { + user_value 4 +}; + +cdl_option CYGINT_DEVS_ETH_OPENCORES_ETHERMAC_RxNUM { + user_value 32 +}; + +cdl_option CYGSEM_ERROR_PER_THREAD_ERRNO { + inferred_value 0 +}; + +cdl_option CYGBLD_ISO_CTYPE_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_ERRNO_CODES_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_ERRNO_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STDIO_FILETYPES_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STDIO_STREAMS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STDIO_FILEOPS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STDIO_FILEACCESS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STDIO_FORMATTED_IO_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STDIO_CHAR_IO_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STDIO_DIRECT_IO_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STDIO_FILEPOS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STDIO_ERROR_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STDLIB_STRCONV_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STDLIB_ABS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STDLIB_DIV_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STRERROR_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_FNMATCH_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_C_TIME_TYPES_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_C_CLOCK_FUNCS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_SIGNAL_NUMBERS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_SIGNAL_IMPL_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_SETJMP_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_DIRENT_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_BSDTYPES_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_OPEN_MAX_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_NAME_MAX_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_NETDB_PROTO_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_NETDB_SERV_HEADER { + inferred_value 1 +}; + +cdl_option CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT { + inferred_value 0 +}; + +cdl_option CYGNUM_LIBC_MAIN_DEFAULT_STACK_SIZE { + user_value 16384 +}; + +cdl_option CYGPKG_NET_TFTPD_THREAD_STACK_SIZE { + user_value (CYGNUM_HAL_STACK_SIZE_TYPICAL+(8192)) +}; + +cdl_component CYGPKG_NET_DHCP { + user_value 0 +}; + +cdl_component CYGHWR_NET_DRIVER_ETH0_MANUAL { + inferred_value 0 +}; + +cdl_component CYGHWR_NET_DRIVER_ETH0_BOOTP { + user_value 0 +}; + +cdl_component CYGHWR_NET_DRIVER_ETH0_ADDRS { + user_value 1 +}; + +cdl_option CYGHWR_NET_DRIVER_ETH0_ADDRS_IP { + user_value 10.0.0.57 +}; + +cdl_option CYGHWR_NET_DRIVER_ETH0_ADDRS_BROADCAST { + user_value 10.0.0.255 +}; + +cdl_option CYGHWR_NET_DRIVER_ETH0_ADDRS_GATEWAY { + user_value 10.0.0.1 +}; + +cdl_option CYGHWR_NET_DRIVER_ETH0_ADDRS_SERVER { + user_value 10.0.0.58 +}; + + diff --git a/zpu/roadshow/roadshow/net_test/ping_test.c b/zpu/roadshow/roadshow/net_test/ping_test.c new file mode 100644 index 0000000..7a3ce59 --- /dev/null +++ b/zpu/roadshow/roadshow/net_test/ping_test.c @@ -0,0 +1,585 @@ +//========================================================================== +// +// tests/ping_test.c +// +// Simple test of PING (ICMP) and networking support +// +//========================================================================== +//####BSDCOPYRIGHTBEGIN#### +// +// ------------------------------------------- +// +// Portions of this software may have been derived from OpenBSD or other sources, +// and are covered by the appropriate copyright disclaimers included herein. +// +// ------------------------------------------- +// +//####BSDCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas, andrew.lunn@ascom.ch +// Date: 2000-01-10 +// Purpose: +// Description: +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +// PING test code + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include CYGDAT_DEVS_ETH_OPENCORES_ETHERMAC_CFG + +#ifdef CYGBLD_DEVS_ETH_DEVICE_H // Get the device config if it exists +#include CYGBLD_DEVS_ETH_DEVICE_H // May provide CYGTST_DEVS_ETH_TEST_NET_REALTIME +#endif + +#ifdef CYGPKG_NET_TESTS_USE_RT_TEST_HARNESS // do we use the rt test? +# ifdef CYGTST_DEVS_ETH_TEST_NET_REALTIME // Get the test ancilla if it exists +# include CYGTST_DEVS_ETH_TEST_NET_REALTIME +# endif +#endif + +// Fill in the blanks if necessary +#ifndef TNR_OFF +# define TNR_OFF() +#endif +#ifndef TNR_ON +# define TNR_ON() +#endif +#ifndef TNR_INIT +# define TNR_INIT() +#endif +#ifndef TNR_PRINT_ACTIVITY +# define TNR_PRINT_ACTIVITY() +#endif + +#include + +#include +#include + +#include //directory +#include + +//for serial +cyg_io_handle_t handle; +extern int inet_aton __P((const char *, struct in_addr *)); +#ifndef CYGPKG_LIBC_STDIO +#define perror(s) diag_printf(#s ": %s\n", strerror(errno)) +#endif +#define SHOW_RESULT( _fn, _res ) \ +diag_printf(": " #_fn "() returned %ld %s\n", (long)_res, _res<0?strerror(errno):""); + +/* +#define STACK_SIZE (CYGNUM_HAL_STACK_SIZE_TYPICAL + 0x1000) +static char stack[STACK_SIZE]; +static cyg_thread thread_data; +static cyg_handle_t thread_handle; +*/ + + +/* NB!!! must be divisible by 8 */ +#define NUM_PINGS 8192 +#define MAX_PACKET 16384 +#define MIN_PACKET 64 +#define MAX_SEND (IP_MAXPACKET - 100) + +#define PACKET_ADD ((MAX_SEND - MIN_PACKET)/NUM_PINGS) +#define nPACKET_ADD 1 + +static unsigned char pkt1[MAX_PACKET], pkt2[MAX_PACKET]; + +#define UNIQUEID 0x1234 +/* we write this much to jffs2 in each go. + * + * DANGER!!! JFFS2 memory consumption is proportional to the # of write operations, + * so reducing this size will make the bootloader run out of memory. + */ +#define IOSIZE 16384 +void +pexit(char *s) +{ + CYG_TEST_FAIL_FINISH(s); +} + +// Compute INET checksum +int +inet_cksum(u_short *addr, int len) +{ + register int nleft = len; + register u_short *w = addr; + register u_short answer; + register u_int sum = 0; + u_short odd_byte = 0; + + /* + * Our algorithm is simple, using a 32 bit accumulator (sum), + * we add sequential 16 bit words to it, and at the end, fold + * back all the carry bits from the top 16 bits into the lower + * 16 bits. + */ + while( nleft > 1 ) { + cyg_uint32 t=*w++; + sum += t; + nleft -= 2; + } + + /* mop up an odd byte, if necessary */ + if( nleft == 1 ) { + *(u_char *)(&odd_byte) = *(u_char *)w; + sum += odd_byte; + } + + /* + * add back carry outs from top 16 bits to low 16 bits + */ + sum = (sum >> 16) + (sum & 0x0000ffff); /* add hi 16 to low 16 */ + sum += (sum >> 16); /* add carry */ + answer = ~sum; /* truncate to 16 bits */ + return (answer); +} + +static int +show_icmp(unsigned char *pkt, int len, + struct sockaddr_in *from, struct sockaddr_in *to) +{ + char buffer[100]; + cyg_uint32 buffer_index = 0; + cyg_tick_count_t tp, tv; + struct ip *ip; + struct icmp *icmp; + tv = cyg_current_time(); + ip = (struct ip *)pkt; + if ((len < (int)sizeof(*ip)) || ip->ip_v != IPVERSION) + { + buffer[0] = '\0'; + snprintf(buffer, 99, "%s: Short packet or not IP! - Len: %d, Version: %d\r\n", + inet_ntoa(from->sin_addr), len, ip->ip_v); + buffer_index = strlen(buffer); + cyg_io_write(handle, buffer, &buffer_index); + return 0; + } + icmp = (struct icmp *)(pkt + sizeof(*ip)); + len -= (sizeof(*ip) + 8); + tp = *((cyg_tick_count_t *)&icmp->icmp_data); + if (icmp->icmp_type != ICMP_ECHOREPLY) + { + buffer[0] = '\0'; + snprintf(buffer, 99, "%s: Invalid ICMP - type: %d\r\n", + inet_ntoa(from->sin_addr), icmp->icmp_type); + buffer_index = strlen(buffer); + cyg_io_write(handle, buffer, &buffer_index); + return 0; + } + if (icmp->icmp_id != UNIQUEID) + { + buffer[0] = '\0'; + snprintf(buffer, 99, "%s: ICMP received for wrong id - sent: %x, recvd: %x\r\n", + inet_ntoa(from->sin_addr), UNIQUEID, icmp->icmp_id); + buffer_index = strlen(buffer); + cyg_io_write(handle, buffer, &buffer_index); + } +// printf("%d bytes from %s: ", len, inet_ntoa(from->sin_addr)); +// printf("icmp_seq=%d", icmp->icmp_seq); + int t=(int)(tv-tp); + t*=10; +// printf(", time=%d ms\n", t); + return (from->sin_addr.s_addr == to->sin_addr.s_addr); +} + +static void +ping_host(int s, struct sockaddr_in *host) +{ + char buffer[100]; + cyg_uint32 buffer_index = 0; + struct icmp *icmp = (struct icmp *)pkt1; + int icmp_len = MIN_PACKET; + int seq = 0, ok_recv = 0, bogus_recv = 0; + cyg_tick_count_t *tp; + long *dp; + struct sockaddr_in from; + int len; + socklen_t fromlen; + + ok_recv = 0; + bogus_recv = 0; + snprintf(buffer, 99, "PING server %s\r\n", inet_ntoa(host->sin_addr)); + buffer_index = strlen(buffer); + cyg_io_write(handle, buffer, &buffer_index); + + + for (seq = 0; seq < NUM_PINGS; seq++, icmp_len += PACKET_ADD ) + { + cyg_thread_delay(50); + TNR_ON(); + + memset(pkt1, 0, sizeof(pkt1)); // make sure we start each time w/same situation... + // Build ICMP packet + icmp->icmp_type = ICMP_ECHO; + icmp->icmp_code = 0; + icmp->icmp_cksum = 0; + icmp->icmp_seq = seq; + icmp->icmp_id = 0x1234; + // Set up ping data + tp = (cyg_tick_count_t *)&icmp->icmp_data; + memset(tp, 0xff, icmp_len); // try to fish out bit 1 force to 0. + *tp++ = cyg_current_time(); + tp++; + dp = (long *)tp; + + // Add checksum + icmp->icmp_cksum = inet_cksum( (u_short *)icmp, icmp_len+8); + // Send it off + if (sendto(s, icmp, icmp_len+8, 0, (struct sockaddr *)host, sizeof(*host)) < 0) { + TNR_OFF(); + perror("sendto"); + continue; + } + // Wait for a response + fromlen = sizeof(from); + len = recvfrom(s, pkt2, sizeof(pkt2), 0, (struct sockaddr *)&from, &fromlen); + TNR_OFF(); + if (len < 0) { + perror("recvfrom"); + inet_cksum( (u_short *)icmp, icmp_len+8); + icmp_len = MIN_PACKET - PACKET_ADD; // just in case - long routes + } else { + if (show_icmp(pkt2, len, &from, host)) { + ok_recv++; + } else { + bogus_recv++; + } + } + } + TNR_OFF(); + snprintf(buffer, 99, "Sent %d packets, received %d OK, %d bad\r\n", NUM_PINGS, ok_recv, bogus_recv); + buffer_index = strlen(buffer); + cyg_io_write(handle, buffer, &buffer_index); +} + +#ifdef CYGPKG_PROFILE_GPROF +#include + +extern char _stext, _etext; // Defined by the linker + +static void +start_profile(void) +{ + // This starts up the system-wide profiling, gathering + // profile information on all of the code, with a 16 byte + // "bucket" size, at a rate of 100us/profile hit. + // Note: a bucket size of 16 will give pretty good function + // resolution. Much smaller and the buffer becomes + // much too large for very little gain. + // Note: a timer period of 100us is also a reasonable + // compromise. Any smaller and the overhead of + // handling the timter (profile) interrupt could + // swamp the system. A fast processor might get + // by with a smaller value, but a slow one could + // even be swamped by this value. If the value is + // too large, the usefulness of the profile is reduced. + + // no more interrupts than 1/10ms. + //profile_on(&_stext, &_etext, 16, 10000); // DRAM + //profile_on((void *)0x2000000, (void *)0x4000000, 32, 10000); // DRAM + //profile_on((void *)0, (void *)0x40000, 16, 10000); // SRAM + //profile_on(0, &_etext, 32, 10000); // SRAM & DRAM +} +#endif + +static void +ping_test(struct bootp *bp) +{ + struct protoent *p; + struct timeval tv; + struct sockaddr_in host; + int s; + + p = getprotobyname("icmp"); + if (p == NULL) + { + pexit("getprotobyname"); + return; + } + s = socket(AF_INET, SOCK_RAW, p->p_proto); + if (s < 0) { + pexit("socket"); + return; + } + tv.tv_sec = 4; + tv.tv_usec = 0; + setsockopt(s, SOL_SOCKET, SO_RCVTIMEO, &tv, sizeof(tv)); + + // default is 8192 bytes which is not big enough for our ping tests... + int sndsize=70000; + setsockopt(s, SOL_SOCKET, SO_RCVBUF, (char *)&sndsize, + (int)sizeof(sndsize)); + sndsize=70000; + setsockopt(s, SOL_SOCKET, SO_SNDBUF, (char *)&sndsize, + (int)sizeof(sndsize)); + + // Set up host address + host.sin_family = AF_INET; + host.sin_len = sizeof(host); + inet_aton("10.0.0.9", &(host.sin_addr)); // edgarpc dev machine +// inet_aton("10.0.0.1", &host.sin_addr); // cisco router + host.sin_port = 0; + ping_host(s, &host); +} + +void done_test() +{ +} + +void +net_test(void) +{ + + Cyg_ErrNo err; + diag_printf("Start PING test\r\n"); + TNR_INIT(); + + err = cyg_io_lookup("/dev/ser0", &handle); + if(err != ENOERR) + { + diag_printf("cannot open serial /dev/ser0"); + return; + } + printf("Testing stdout...\r\n"); + +#ifdef CYGHWR_NET_DRIVER_ETH0 + if (eth0_up) { + ping_test(ð0_bootp_data); + } +#endif +#ifdef CYGHWR_NET_DRIVER_ETH1 + if (eth1_up) { + ping_test(ð1_bootp_data); + } +#endif + TNR_PRINT_ACTIVITY(); + CYG_TEST_PASS_FINISH("Ping test OK"); + done_test(); +} + + +int getFileName(const char *extension, char *fileName) +{ + int found = 0; + DIR* ramfs = opendir("/ramfs"); + if(ramfs == NULL) + { + diag_printf("cannot open /ramfs\n"); + return found; + } + while(1) + { + struct dirent *entry = readdir( ramfs ); + int len = 0; + if( entry == NULL ) + break; + len = strlen(entry->d_name); + if(len > 4 && entry->d_name[len - 4] == '.' && + entry->d_name[len - 3] == 'p' && + entry->d_name[len - 2] == 'h' && + entry->d_name[len - 1] == 'i') + { + found = 1; + strcpy(fileName, "/ramfs/"); + strcat(fileName, entry->d_name); + } + } + closedir(ramfs); + ramfs = NULL; + return found; +} + +static char buf[IOSIZE]; + +static int copyfile( char *name2, char *name1 ) +{ + + int err = 0; + int fd1 = -1, fd2 = -1; + ssize_t done = 0, wrote = 0, current = 0; + + diag_printf(" copy file %s -> %s\n",name2,name1); + + fd1 = creat(name1, O_TRUNC | O_CREAT); + if( fd1 < 0 ) + { + SHOW_RESULT( creat, fd1 ); + diag_printf(" %s", name1); + return -1; + } + + fd2 = open( name2, O_RDONLY ); + if( fd2 < 0 ) + { + SHOW_RESULT( open, fd2 ); + diag_printf(" %s", name2); + return -1; + } + + for(;;) + { + done = read( fd2, buf, IOSIZE ); + if( done < 0 ) + { + SHOW_RESULT( read, done ); + return -1; + } + + if( done == 0 ) break; + + wrote = write( fd1, buf, done ); + if( wrote != done ) + { + SHOW_RESULT( write, wrote ); + return -1; + } + + current += wrote; + if( wrote != done ) break; + } + diag_printf("wrote %d\n", current); + err = close( fd1 ); + if( err < 0 ) + { + SHOW_RESULT( close, err ); + diag_printf(" %s", name1); + return -1; + } + + err = close( fd2 ); + if( err < 0 ) + { + SHOW_RESULT( close, err ); + diag_printf(" %s", name2); + return -1; + } + return 0; +} + +int isCompleted(const char *fileName) +{ + int err = access( fileName, W_OK ); + int fd = 0; + char readyBuffer[5]; + if( err < 0 && errno != EACCES ) + { + SHOW_RESULT( access, err ); + return 0; + } + fd = open(fileName, O_RDONLY); + if(fd < 0) + { + SHOW_RESULT( open, errno ); + return 0; + } + err = lseek(fd, -5, SEEK_END); + if(err < 0) + { + SHOW_RESULT( lseek, err ); + close(fd); + return 0; + } + err = read(fd, readyBuffer, 4); + if(err < 0) + { + SHOW_RESULT( read, err ); + close(fd); + return 0; + } + readyBuffer[4] = '\0'; + if(strncmp(readyBuffer, "Done", 4) != 0) + { + //diag_printf("Coudn't read \"Done\" at the end of the firmware file %s\n", readyBuffer); + close(fd); + return 0; + } + close(fd); + diag_printf("found!\n"); + return 1; +} + +static void ramfs_polling(cyg_addrword_t data) +{ + char fileName[100]; + int found = 0; + while(1) + { + cyg_thread_delay(100); + //scan the file system for a new .phi file + found = getFileName("phi", fileName); + if(found) + { + //check if the file has been transfered + if(isCompleted(fileName)) + { + //move the file to flash + unlink("/jffs2/firmware.bin"); + copyfile(fileName, "/jffs2/firmware.bin"); + diag_printf("firmware file copied to jffs2\n"); + unlink(fileName); + diag_printf("unmounting /jffs\n"); + umount("/jffs2"); + diag_printf("Resetting...\n"); +// CYGACC_CALL_IF_RESET(); + } + } + } +} + +static unsigned char ramfs_polling_stack[CYGNUM_HAL_STACK_SIZE_TYPICAL]; +static cyg_handle_t ramfs_polling_handle; +static cyg_thread ramfs_polling_thread; + +void start_ramfs_polling() +{ + + cyg_thread_create(10, &ramfs_polling, 0, "ramfs_polling", + ramfs_polling_stack, CYGNUM_HAL_STACK_SIZE_TYPICAL, + &ramfs_polling_handle, &ramfs_polling_thread); + cyg_thread_resume(ramfs_polling_handle); +} + +struct tftpd_fileops fileops = {open, + close, + write, + read}; + +externC void phi_init_all_network_interfaces(); + +int main(int argc, char **argv) +{ + diag_printf("Entered net_test main()\n"); + + int server_id = 0; + + init_all_network_interfaces(); + + + + int i=0; + while(1) + { + cyg_thread_delay(500); +// net_test(); + diag_printf("sleeping... %d\n", i++); + } + return 0; +} diff --git a/zpu/roadshow/roadshow/pics/GCC_logo.png b/zpu/roadshow/roadshow/pics/GCC_logo.png new file mode 100644 index 0000000..7b3435f Binary files /dev/null and b/zpu/roadshow/roadshow/pics/GCC_logo.png differ diff --git a/zpu/roadshow/roadshow/pics/codesize1.PNG b/zpu/roadshow/roadshow/pics/codesize1.PNG new file mode 100644 index 0000000..874ee9d Binary files /dev/null and b/zpu/roadshow/roadshow/pics/codesize1.PNG differ diff --git a/zpu/roadshow/roadshow/pics/codesize2.PNG b/zpu/roadshow/roadshow/pics/codesize2.PNG new file mode 100644 index 0000000..caa8c14 Binary files /dev/null and b/zpu/roadshow/roadshow/pics/codesize2.PNG differ diff --git a/zpu/roadshow/roadshow/pics/ecos.gif b/zpu/roadshow/roadshow/pics/ecos.gif new file mode 100644 index 0000000..3dad40c Binary files /dev/null and b/zpu/roadshow/roadshow/pics/ecos.gif differ diff --git a/zpu/roadshow/roadshow/pics/elizadebug1.PNG b/zpu/roadshow/roadshow/pics/elizadebug1.PNG new file mode 100644 index 0000000..f3c3f5f Binary files /dev/null and b/zpu/roadshow/roadshow/pics/elizadebug1.PNG differ diff --git a/zpu/roadshow/roadshow/pics/elizadebug2.PNG b/zpu/roadshow/roadshow/pics/elizadebug2.PNG new file mode 100644 index 0000000..13f046e Binary files /dev/null and b/zpu/roadshow/roadshow/pics/elizadebug2.PNG differ diff --git a/zpu/snapshot.sh b/zpu/snapshot.sh new file mode 100644 index 0000000..8fd6e33 --- /dev/null +++ b/zpu/snapshot.sh @@ -0,0 +1,7 @@ +export SNAPSHOT=`date +%Y-%m-%d` + +echo hdl$SNAPSHOT.zip docs$SNAPSHOT.zip sw$SNAPSHOT.zip +rm -f hdl$SNAPSHOT.zip docs$SNAPSHOT.zip sw$SNAPSHOT.zip +zip -r hdl$SNAPSHOT.zip hdl -x "*.svn*" +zip -r docs$SNAPSHOT.zip docs -x "*.svn*" +zip -r sw$SNAPSHOT.zip sw -x "*.svn*" diff --git a/zpu/sw/ecos/repository/dev/eth/opencores/ethermac/current/cdl/opencores_ethermac_drivers.cdl b/zpu/sw/ecos/repository/dev/eth/opencores/ethermac/current/cdl/opencores_ethermac_drivers.cdl new file mode 100644 index 0000000..017ee57 --- /dev/null +++ b/zpu/sw/ecos/repository/dev/eth/opencores/ethermac/current/cdl/opencores_ethermac_drivers.cdl @@ -0,0 +1,149 @@ +# ==================================================================== +# +# opencores_ethermac_eth_drivers.cdl +# +# Ethernet drivers - support for Opencores ethermac controllers +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## Copyright (C) 2004 Andrew Lunn +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): Gaisler Research, (Konrad Eisele) +# Contributors: +# Date: 2005-01-22 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC { + display "Opencores ethermac driver" + description "Ethernet driver for Opencores ethermac driver." + + parent CYGPKG_IO_ETH_DRIVERS + active_if CYGPKG_IO_ETH_DRIVERS + + active_if CYGINT_DEVS_ETH_OPENCORES_ETHERMAC_REQUIRED + + include_dir . + include_files ; # none _exported_ whatsoever + compile if_oeth.c + + include_files include/oeth_info.h + + define_proc { + puts $::cdl_header "#include "; + puts $::cdl_header "#include CYGDAT_DEVS_ETH_OPENCORES_ETHERMAC_CFG"; + } + + cdl_option CYGNUM_DEVS_ETH_OPENCORES_ETHERMAC_DEV_COUNT { + display "Number of supported interfaces." + calculated { CYGINT_DEVS_ETH_OPENCORES_ETHERMAC_REQUIRED } + flavor data + description " + This option selects the number of ethernet interfaces to + be supported by the driver." + } + + cdl_interface CYGINT_DEVS_ETH_OPENCORES_ETHERMAC_STATIC_ESA { + display "ESA is statically configured" + description " + If this is nonzero, then the ESA (MAC address) is statically + configured in the platform-specific package which instantiates + this driver with all its details. + + Note that use of this option is deprecated in favor of a + CYGSEM_DEVS_ETH_..._SET_ESA option in the platform specific + driver." + } + + cdl_option CYGINT_DEVS_ETH_OPENCORES_ETHERMAC_TxNUM { + display "Number of output buffers" + flavor data + legal_values 2 to 64 + default_value 4 + description " + This option specifies the number of output buffer packets + to be used for the opencores ethernet device in multiples of 2." + } + + cdl_option CYGINT_DEVS_ETH_OPENCORES_ETHERMAC_RxNUM { + display "Number of input buffers" + flavor data + legal_values 2 to 64 + default_value 4 + description " + This option specifies the number of input buffer packets + to be used for the opencores ethernet device in multiples of 2." + } + + cdl_component CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC_OPTIONS { + display "Opencores ethermac driver build options" + flavor none + no_define + + cdl_option CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "-D_KERNEL -D__ECOS" } + description " + This option modifies the set of compiler flags for + building the opencores ethermac driver package. + These flags are used in addition + to the set of global flags." + } + } + + cdl_component CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC_FLUSH { + display "Cache flushing" + flavor bool + default_value 1 + description "Flush cache before copying packets from/to the + ethermac dma transfer buffers. If you have cache snooping enabled + you can disable this option." + + } + + cdl_component CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC_ETH100 { + display "Initialize MII to 100mbit" + flavor bool + default_value 0 + description "Issue a MII sequence that enables a 100mbit link " + + } + +} diff --git a/zpu/sw/ecos/repository/ecos.db b/zpu/sw/ecos/repository/ecos.db new file mode 100644 index 0000000..c31fc4b --- /dev/null +++ b/zpu/sw/ecos/repository/ecos.db @@ -0,0 +1,128 @@ + +package CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC { + alias { "opencore's ethermac support" devs_eth_opencores_ethermac } + hardware + directory dev/eth/opencores/ethermac + script opencores_ethermac_drivers.cdl + description "This package contains hardware support for Opencores + ethermac." +} + +package CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI { + alias { "ethernet support for opencores on Zylin Phi addon board" devs_eth_zpu_opencores_phi } + hardware + directory dev/eth/zpu/opencores/phi + script phi_opencores_ethmac_drivers.cdl + description "This package contains hardware support for Opencores Ethermac + ethernet device on Phi." +} + + + +package CYGPKG_HAL_ZYLIN { + alias { "Zylin common HAL" hal_zylin } + directory hal/zylin/arch + script hal_zylin.cdl + hardware + description " +The Zylin architecture HAL package provides generic support for this +processor architecture. It is also necessary to select a specific +target platform HAL package." +} + + +package CYGPKG_HAL_ZYLIN_ZPU { + alias { "Zylin ZPU variant HAL" hal_zylin_zpu } + directory hal/zylin/zpu/var + script hal_zylin_zpu.cdl + hardware + description " + The Zylin ZPU HAL package provides the support needed to run eCos on Zylin + ZPU based targets." +} + + + +package CYGPKG_HAL_ZYLIN_ZPU_ZETA { + alias { "Zylin ZPU simulation" zeta } + directory hal/zylin/zpu/zeta + script hal_zylin_zpu_zeta.cdl + hardware + description " + The Zylin ZPU package provides the support needed to run eCos on an Zylin + evaluation board." +} +package CYGPKG_HAL_ZYLIN_ZPU_PHI { + alias { "Zylin ZPU evaluation board" phi } + directory hal/zylin/zpu/phi + script hal_zylin_zpu_phi.cdl + hardware + description " + The Zylin ZPU package provides the support needed to run eCos on a Zylin eCosBoard" +} + +package CYGPKG_HAL_ZYLIN_ZPU_ABEL { + alias { "Zylin ZPU Abel board" abel } + directory hal/zylin/zpu/abel + script hal_zylin_zpu_abel.cdl + hardware + description " + The Zylin ZPU package provides the support needed to run eCos on an Abel Zylin + evaluation board." +} + + +package CYGPKG_PHI_NET { + alias { "Zylin Phi networking" phi_net } + directory net/zylin + script phi_net.cdl + hardware + description "Contains phi specific network init." +} + + +target zeta { + alias { "Zylin ZPU evaluation board " zeta } + packages { CYGPKG_HAL_ZYLIN + CYGPKG_HAL_ZYLIN_ZPU + CYGPKG_HAL_ZYLIN_ZPU_ZETA + } + description " + The Zylin ZPU target provides the packages needed to run eCos on an Zylin + evaluation board." +} + +target phi { + alias { "Zylin ZPU evaluation board " phi } + packages { CYGPKG_HAL_ZYLIN + CYGPKG_HAL_ZYLIN_ZPU + CYGPKG_HAL_ZYLIN_ZPU_PHI + } + description " + The Zylin ZPU target provides the packages needed to run eCos on an Zylin eCosBoard" +} + +target abel { + alias { "Zylin ZPU evaluation board " abel } + packages { CYGPKG_HAL_ZYLIN + CYGPKG_HAL_ZYLIN_ZPU + CYGPKG_HAL_ZYLIN_ZPU_ABEL + } + description " + The Zylin ZPU target provides the packages needed to run eCos on an Abel Zylin + evaluation board." +} + +target zpuetherphi { + alias { "Zylin Phi addon board with ethernet" etherphi } + packages { CYGPKG_HAL_ZYLIN + CYGPKG_HAL_ZYLIN_ZPU + CYGPKG_HAL_ZYLIN_ZPU_PHI + CYGPKG_IO_ETH_DRIVERS + CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC + CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI + } + description " + The Zylin Phi ZPU target provides the packages needed to run ZPU eCos on a + Zylin eCosBoard addon board with ethernet." +} diff --git a/zpu/sw/helloworld/gccgdb.PNG b/zpu/sw/helloworld/gccgdb.PNG new file mode 100644 index 0000000..afdfc31 Binary files /dev/null and b/zpu/sw/helloworld/gccgdb.PNG differ diff --git a/zpu/sw/helloworld/gmon.out b/zpu/sw/helloworld/gmon.out new file mode 100644 index 0000000..86ca3d6 Binary files /dev/null and b/zpu/sw/helloworld/gmon.out differ diff --git a/zpu/sw/helloworld/hello.bin b/zpu/sw/helloworld/hello.bin new file mode 100644 index 0000000..4413b05 Binary files /dev/null and b/zpu/sw/helloworld/hello.bin differ diff --git a/zpu/sw/helloworld/hello.bram b/zpu/sw/helloworld/hello.bram new file mode 100644 index 0000000..f7e99e9 --- /dev/null +++ b/zpu/sw/helloworld/hello.bram @@ -0,0 +1,12441 @@ +0 => x"0b0b0b0b", +1 => x"82700b0b", +2 => x"82f4e00c", +3 => x"3a0b0b81", +4 => x"e48c0400", +5 => x"00000000", +6 => x"00000000", +7 => x"00000000", +8 => x"80088408", +9 => x"88080b0b", +10 => x"81e4fd2d", +11 => x"880c840c", +12 => x"800c0400", +13 => x"00000000", +14 => x"00000000", +15 => x"00000000", +16 => x"71fd0608", +17 => x"72830609", +18 => x"81058205", +19 => x"832b2a83", +20 => x"ffff0652", +21 => x"04000000", +22 => x"00000000", +23 => x"00000000", +24 => x"71fd0608", +25 => x"83ffff73", +26 => x"83060981", +27 => x"05820583", +28 => x"2b2b0906", +29 => x"7383ffff", +30 => x"0b0b0b0b", +31 => x"83a70400", +32 => x"72098105", +33 => x"72057373", +34 => x"09060906", +35 => x"73097306", +36 => x"070a8106", +37 => x"53510400", +38 => x"00000000", +39 => x"00000000", +40 => x"72722473", +41 => x"732e0753", +42 => x"51040000", +43 => x"00000000", +44 => x"00000000", +45 => x"00000000", +46 => x"00000000", +47 => x"00000000", +48 => x"71737109", +49 => x"71068106", +50 => x"30720a10", +51 => x"0a720a10", +52 => x"0a31050a", +53 => x"81065151", +54 => x"53510400", +55 => x"00000000", +56 => x"72722673", +57 => x"732e0753", +58 => x"51040000", +59 => x"00000000", +60 => x"00000000", +61 => x"00000000", +62 => x"00000000", +63 => x"00000000", +64 => x"00000000", +65 => x"00000000", +66 => x"00000000", +67 => x"00000000", +68 => x"00000000", +69 => x"00000000", +70 => x"00000000", +71 => x"00000000", +72 => x"0b0b0b88", +73 => x"c9040000", +74 => x"00000000", +75 => x"00000000", +76 => x"00000000", +77 => x"00000000", +78 => x"00000000", +79 => x"00000000", +80 => x"720a722b", +81 => x"0a535104", +82 => x"00000000", +83 => x"00000000", +84 => x"00000000", +85 => x"00000000", +86 => x"00000000", +87 => x"00000000", +88 => x"72729f06", +89 => x"0981050b", +90 => x"0b0b88ac", +91 => x"05040000", +92 => x"00000000", +93 => x"00000000", +94 => x"00000000", +95 => x"00000000", +96 => x"72722aff", +97 => x"739f062a", +98 => x"0974090a", +99 => x"8106ff05", +100 => x"06075351", +101 => x"04000000", +102 => x"00000000", +103 => x"00000000", +104 => x"71715351", +105 => x"020d0406", +106 => x"73830609", +107 => x"81058205", +108 => x"832b0b2b", +109 => x"0772fc06", +110 => x"0c515104", +111 => x"00000000", +112 => x"72098105", +113 => x"72050970", +114 => x"81050906", +115 => x"0a810653", +116 => x"51040000", +117 => x"00000000", +118 => x"00000000", +119 => x"00000000", +120 => x"72098105", +121 => x"72050970", +122 => x"81050906", +123 => x"0a098106", +124 => x"53510400", +125 => x"00000000", +126 => x"00000000", +127 => x"00000000", +128 => x"71098105", +129 => x"52040000", +130 => x"00000000", +131 => x"00000000", +132 => x"00000000", +133 => x"00000000", +134 => x"00000000", +135 => x"00000000", +136 => x"72720981", +137 => x"05055351", +138 => x"04000000", +139 => x"00000000", +140 => x"00000000", +141 => x"00000000", +142 => x"00000000", +143 => x"00000000", +144 => x"72097206", +145 => x"73730906", +146 => x"07535104", +147 => x"00000000", +148 => x"00000000", +149 => x"00000000", +150 => x"00000000", +151 => x"00000000", +152 => x"71fc0608", +153 => x"72830609", +154 => x"81058305", +155 => x"1010102a", +156 => x"81ff0652", +157 => x"04000000", +158 => x"00000000", +159 => x"00000000", +160 => x"71fc0608", +161 => x"0b0b82f4", +162 => x"cc738306", +163 => x"10100508", +164 => x"060b0b0b", +165 => x"88af0400", +166 => x"00000000", +167 => x"00000000", +168 => x"80088408", +169 => x"88087575", +170 => x"0b0b0b8e", +171 => x"c42d5050", +172 => x"80085688", +173 => x"0c840c80", +174 => x"0c510400", +175 => x"00000000", +176 => x"80088408", +177 => x"88087575", +178 => x"0b0b0b90", +179 => x"8d2d5050", +180 => x"80085688", +181 => x"0c840c80", +182 => x"0c510400", +183 => x"00000000", +184 => x"72097081", +185 => x"0509060a", +186 => x"8106ff05", +187 => x"70547106", +188 => x"73097274", +189 => x"05ff0506", +190 => x"07515151", +191 => x"04000000", +192 => x"72097081", +193 => x"0509060a", +194 => x"098106ff", +195 => x"05705471", +196 => x"06730972", +197 => x"7405ff05", +198 => x"06075151", +199 => x"51040000", +200 => x"05ff0504", +201 => x"00000000", +202 => x"00000000", +203 => x"00000000", +204 => x"00000000", +205 => x"00000000", +206 => x"00000000", +207 => x"00000000", +208 => x"810b0b0b", +209 => x"82f4dc0c", +210 => x"51040000", +211 => x"00000000", +212 => x"00000000", +213 => x"00000000", +214 => x"00000000", +215 => x"00000000", +216 => x"71810552", +217 => x"04000000", +218 => x"00000000", +219 => x"00000000", +220 => x"00000000", +221 => x"00000000", +222 => x"00000000", +223 => x"00000000", +224 => x"00000000", +225 => x"00000000", +226 => x"00000000", +227 => x"00000000", +228 => x"00000000", +229 => x"00000000", +230 => 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x"00000000", +12143 => x"00000000", +12144 => x"00000000", +12145 => x"00000000", +12146 => x"00000000", +12147 => x"00000000", +12148 => x"00000000", +12149 => x"00000000", +12150 => x"00000000", +12151 => x"00000000", +12152 => x"00000000", +12153 => x"00000000", +12154 => x"00000000", +12155 => x"43000000", +12156 => x"00000000", +12157 => x"00000000", +12158 => x"00000000", +12159 => x"00000000", +12160 => x"00000000", +12161 => x"00000001", +12162 => x"0000b8cc", +12163 => x"00000000", +12164 => x"00000000", +12165 => x"00000000", +12166 => x"00000000", +12167 => x"00000000", +12168 => x"00000000", +12169 => x"00000000", +12170 => x"00000000", +12171 => x"00000000", +12172 => x"00000000", +12173 => x"00000000", +12174 => x"00000000", +12175 => x"ffffffff", +12176 => x"00000000", +12177 => x"00020000", +12178 => x"00000000", +12179 => x"00000000", +12180 => x"0000be48", +12181 => x"0000be48", +12182 => x"0000be50", +12183 => x"0000be50", +12184 => x"0000be58", +12185 => x"0000be58", +12186 => x"0000be60", +12187 => x"0000be60", +12188 => x"0000be68", +12189 => x"0000be68", +12190 => x"0000be70", +12191 => x"0000be70", +12192 => x"0000be78", +12193 => x"0000be78", +12194 => x"0000be80", +12195 => x"0000be80", +12196 => x"0000be88", +12197 => x"0000be88", +12198 => x"0000be90", +12199 => x"0000be90", +12200 => x"0000be98", +12201 => x"0000be98", +12202 => x"0000bea0", +12203 => x"0000bea0", +12204 => x"0000bea8", +12205 => x"0000bea8", +12206 => x"0000beb0", +12207 => x"0000beb0", +12208 => x"0000beb8", +12209 => x"0000beb8", +12210 => x"0000bec0", +12211 => x"0000bec0", +12212 => x"0000bec8", +12213 => x"0000bec8", +12214 => x"0000bed0", +12215 => x"0000bed0", +12216 => x"0000bed8", +12217 => x"0000bed8", +12218 => x"0000bee0", +12219 => x"0000bee0", +12220 => x"0000bee8", +12221 => x"0000bee8", +12222 => x"0000bef0", +12223 => x"0000bef0", +12224 => x"0000bef8", +12225 => x"0000bef8", +12226 => x"0000bf00", +12227 => x"0000bf00", +12228 => x"0000bf08", +12229 => x"0000bf08", +12230 => x"0000bf10", +12231 => x"0000bf10", +12232 => x"0000bf18", +12233 => x"0000bf18", +12234 => x"0000bf20", +12235 => x"0000bf20", +12236 => x"0000bf28", +12237 => x"0000bf28", +12238 => x"0000bf30", +12239 => x"0000bf30", +12240 => x"0000bf38", +12241 => x"0000bf38", +12242 => x"0000bf40", +12243 => x"0000bf40", +12244 => x"0000bf48", +12245 => x"0000bf48", +12246 => x"0000bf50", +12247 => x"0000bf50", +12248 => x"0000bf58", +12249 => x"0000bf58", +12250 => x"0000bf60", +12251 => x"0000bf60", +12252 => x"0000bf68", +12253 => x"0000bf68", +12254 => x"0000bf70", +12255 => x"0000bf70", +12256 => x"0000bf78", +12257 => x"0000bf78", +12258 => x"0000bf80", +12259 => x"0000bf80", +12260 => x"0000bf88", +12261 => x"0000bf88", +12262 => x"0000bf90", +12263 => x"0000bf90", +12264 => x"0000bf98", +12265 => x"0000bf98", +12266 => x"0000bfa0", +12267 => x"0000bfa0", +12268 => x"0000bfa8", +12269 => x"0000bfa8", +12270 => x"0000bfb0", +12271 => x"0000bfb0", +12272 => x"0000bfb8", +12273 => x"0000bfb8", +12274 => x"0000bfc0", +12275 => x"0000bfc0", +12276 => x"0000bfc8", +12277 => x"0000bfc8", +12278 => x"0000bfd0", +12279 => x"0000bfd0", +12280 => x"0000bfd8", +12281 => x"0000bfd8", +12282 => x"0000bfe0", +12283 => x"0000bfe0", +12284 => x"0000bfe8", +12285 => x"0000bfe8", +12286 => x"0000bff0", +12287 => x"0000bff0", +12288 => x"0000bff8", +12289 => x"0000bff8", +12290 => x"0000c000", +12291 => x"0000c000", +12292 => x"0000c008", +12293 => x"0000c008", +12294 => x"0000c010", +12295 => x"0000c010", +12296 => x"0000c018", +12297 => x"0000c018", +12298 => x"0000c020", +12299 => x"0000c020", +12300 => x"0000c028", +12301 => x"0000c028", +12302 => x"0000c030", +12303 => x"0000c030", +12304 => x"0000c038", +12305 => x"0000c038", +12306 => x"0000c040", +12307 => x"0000c040", +12308 => x"0000c048", +12309 => x"0000c048", +12310 => x"0000c050", +12311 => x"0000c050", +12312 => x"0000c058", +12313 => x"0000c058", +12314 => x"0000c060", +12315 => x"0000c060", +12316 => x"0000c068", +12317 => x"0000c068", +12318 => x"0000c070", +12319 => x"0000c070", +12320 => x"0000c078", +12321 => x"0000c078", +12322 => x"0000c080", +12323 => x"0000c080", +12324 => x"0000c088", +12325 => x"0000c088", +12326 => x"0000c090", +12327 => x"0000c090", +12328 => x"0000c098", +12329 => x"0000c098", +12330 => x"0000c0a0", +12331 => x"0000c0a0", +12332 => x"0000c0a8", +12333 => x"0000c0a8", +12334 => x"0000c0b0", +12335 => x"0000c0b0", +12336 => x"0000c0b8", +12337 => x"0000c0b8", +12338 => x"0000c0c0", +12339 => x"0000c0c0", +12340 => x"0000c0c8", +12341 => x"0000c0c8", +12342 => x"0000c0d0", +12343 => x"0000c0d0", +12344 => x"0000c0d8", +12345 => x"0000c0d8", +12346 => x"0000c0e0", +12347 => x"0000c0e0", +12348 => x"0000c0e8", +12349 => x"0000c0e8", +12350 => x"0000c0f0", +12351 => x"0000c0f0", +12352 => x"0000c0f8", +12353 => x"0000c0f8", +12354 => x"0000c100", +12355 => x"0000c100", +12356 => x"0000c108", +12357 => x"0000c108", +12358 => x"0000c110", +12359 => x"0000c110", +12360 => x"0000c118", +12361 => x"0000c118", +12362 => x"0000c120", +12363 => x"0000c120", +12364 => x"0000c128", +12365 => x"0000c128", +12366 => x"0000c130", +12367 => x"0000c130", +12368 => x"0000c138", +12369 => x"0000c138", +12370 => x"0000c140", +12371 => x"0000c140", +12372 => x"0000c148", +12373 => x"0000c148", +12374 => x"0000c150", +12375 => x"0000c150", +12376 => x"0000c158", +12377 => x"0000c158", +12378 => x"0000c160", +12379 => x"0000c160", +12380 => x"0000c168", +12381 => x"0000c168", +12382 => x"0000c170", +12383 => x"0000c170", +12384 => x"0000c178", +12385 => x"0000c178", +12386 => x"0000c180", +12387 => x"0000c180", +12388 => x"0000c188", +12389 => x"0000c188", +12390 => x"0000c190", +12391 => x"0000c190", +12392 => x"0000c198", +12393 => x"0000c198", +12394 => x"0000c1a0", +12395 => x"0000c1a0", +12396 => x"0000c1a8", +12397 => x"0000c1a8", +12398 => x"0000c1b0", +12399 => x"0000c1b0", +12400 => x"0000c1b8", +12401 => x"0000c1b8", +12402 => x"0000c1c0", +12403 => x"0000c1c0", +12404 => x"0000c1c8", +12405 => x"0000c1c8", +12406 => x"0000c1d0", +12407 => x"0000c1d0", +12408 => x"0000c1d8", +12409 => x"0000c1d8", +12410 => x"0000c1e0", +12411 => x"0000c1e0", +12412 => x"0000c1e8", +12413 => x"0000c1e8", +12414 => x"0000c1f0", +12415 => x"0000c1f0", +12416 => x"0000c1f8", +12417 => x"0000c1f8", +12418 => x"0000c200", +12419 => x"0000c200", +12420 => x"0000c208", +12421 => x"0000c208", +12422 => x"0000c210", +12423 => x"0000c210", +12424 => x"0000c218", +12425 => x"0000c218", +12426 => x"0000c220", +12427 => x"0000c220", +12428 => x"0000c228", +12429 => x"0000c228", +12430 => x"0000c230", +12431 => x"0000c230", +12432 => x"0000c238", +12433 => x"0000c238", +12434 => x"0000c240", +12435 => x"0000c240", +12436 => x"0000ba2c", +12437 => x"ffffffff", +12438 => x"00000000", +12439 => x"ffffffff", +12440 => x"00000000", diff --git a/zpu/sw/helloworld/hello.c b/zpu/sw/helloworld/hello.c new file mode 100644 index 0000000..e9cc61e --- /dev/null +++ b/zpu/sw/helloworld/hello.c @@ -0,0 +1,6 @@ +// To compile: zpu-elf-gcc test.c -o test.elf -phi +// To run: +int main(int argc, char **argv) +{ + printf("Hello world!\n"); +} diff --git a/zpu/sw/helloworld/hello.elf b/zpu/sw/helloworld/hello.elf new file mode 100644 index 0000000..be3c093 Binary files /dev/null and b/zpu/sw/helloworld/hello.elf differ diff --git a/zpu/sw/helloworld/zpusim.PNG b/zpu/sw/helloworld/zpusim.PNG new file mode 100644 index 0000000..d8fc277 Binary files /dev/null and b/zpu/sw/helloworld/zpusim.PNG differ diff --git a/zpu/sw/index.html b/zpu/sw/index.html new file mode 100644 index 0000000..6c860a9 --- /dev/null +++ b/zpu/sw/index.html @@ -0,0 +1,44 @@ + + +

Getting started - a ZPU hello world program

+The ZPU comes with a standard GCC toolchain and an instruction set simulator. This allows compiling, running & debugging simple test programs. The Simulator has +some very basic peripherals defined: counter, timer interrupt and a debug output port. +

Installing

+
    +
  1. Install Cygwin. http://www.cygwin.com +
  2. Install Java +
  3. Start Cygwin bash +
  4. cd zpu/sw +
  5. unzip tools/zputoolchain.zip +
  6. zpu/sw/install/bin now has the .exe files for the GCC toolchain & GDB +
  7. You may want to add install/bin from zputoolchain.zip to PATH.
    +export PATH=$PATH:<unzipdir>/install/bin +
+

Hello world example

+The ZPU toolchain comes with newlib & libstdc++ support which means that many C/C++ programs can be compiled without modification. +

+ +cd zpu/sw/helloworld
+../install/bin/zpu-elf-gcc -phi hello.c -o hello.elf
+ +

Running the hello world example in GDB

+
    +
  1. cd zpu/sw/helloworld +
  2. Launch the simulator from a seperate bash shell:

    +java -classpath ../simulator/zpusim.jar -Xmx512m com.zylin.zpu.simulator.Phi 4444 +

    + +

  3. Launch GDB:

    +../install/bin/zpu-elf-gdb hello.elf +

  4. Connect to target, load and run application:

    + +(gdb) target remote localhost:4444
    +(gdb) load
    +(gdb) continue
    +     +

    + + + + + diff --git a/zpu/sw/simulator/.classpath b/zpu/sw/simulator/.classpath new file mode 100644 index 0000000..617be7e --- /dev/null +++ b/zpu/sw/simulator/.classpath @@ -0,0 +1,6 @@ + + + + + + diff --git a/zpu/sw/simulator/.project b/zpu/sw/simulator/.project new file mode 100644 index 0000000..9cd2fd7 --- /dev/null +++ b/zpu/sw/simulator/.project @@ -0,0 +1,17 @@ + + + simulator + + + + + + org.eclipse.jdt.core.javabuilder + + + + + + org.eclipse.jdt.core.javanature + + diff --git a/zpu/sw/simulator/.settings/org.eclipse.jdt.core.prefs b/zpu/sw/simulator/.settings/org.eclipse.jdt.core.prefs new file mode 100644 index 0000000..6a131a7 --- /dev/null +++ b/zpu/sw/simulator/.settings/org.eclipse.jdt.core.prefs @@ -0,0 +1,66 @@ +#Sat Aug 04 19:47:23 CEST 2007 +eclipse.preferences.version=1 +org.eclipse.jdt.core.compiler.codegen.inlineJsrBytecode=enabled +org.eclipse.jdt.core.compiler.codegen.targetPlatform=1.5 +org.eclipse.jdt.core.compiler.codegen.unusedLocal=preserve +org.eclipse.jdt.core.compiler.compliance=1.5 +org.eclipse.jdt.core.compiler.debug.lineNumber=generate +org.eclipse.jdt.core.compiler.debug.localVariable=generate +org.eclipse.jdt.core.compiler.debug.sourceFile=generate +org.eclipse.jdt.core.compiler.problem.annotationSuperInterface=warning +org.eclipse.jdt.core.compiler.problem.assertIdentifier=error +org.eclipse.jdt.core.compiler.problem.autoboxing=ignore +org.eclipse.jdt.core.compiler.problem.deprecation=warning +org.eclipse.jdt.core.compiler.problem.deprecationInDeprecatedCode=disabled +org.eclipse.jdt.core.compiler.problem.deprecationWhenOverridingDeprecatedMethod=disabled +org.eclipse.jdt.core.compiler.problem.discouragedReference=warning +org.eclipse.jdt.core.compiler.problem.emptyStatement=ignore +org.eclipse.jdt.core.compiler.problem.enumIdentifier=error +org.eclipse.jdt.core.compiler.problem.fallthroughCase=ignore +org.eclipse.jdt.core.compiler.problem.fatalOptionalError=enabled +org.eclipse.jdt.core.compiler.problem.fieldHiding=ignore +org.eclipse.jdt.core.compiler.problem.finalParameterBound=ignore +org.eclipse.jdt.core.compiler.problem.finallyBlockNotCompletingNormally=warning +org.eclipse.jdt.core.compiler.problem.forbiddenReference=error +org.eclipse.jdt.core.compiler.problem.hiddenCatchBlock=warning +org.eclipse.jdt.core.compiler.problem.incompatibleNonInheritedInterfaceMethod=warning +org.eclipse.jdt.core.compiler.problem.incompleteEnumSwitch=ignore +org.eclipse.jdt.core.compiler.problem.indirectStaticAccess=ignore +org.eclipse.jdt.core.compiler.problem.localVariableHiding=ignore +org.eclipse.jdt.core.compiler.problem.methodWithConstructorName=warning +org.eclipse.jdt.core.compiler.problem.missingDeprecatedAnnotation=ignore +org.eclipse.jdt.core.compiler.problem.missingOverrideAnnotation=ignore +org.eclipse.jdt.core.compiler.problem.missingSerialVersion=ignore +org.eclipse.jdt.core.compiler.problem.noEffectAssignment=warning +org.eclipse.jdt.core.compiler.problem.noImplicitStringConversion=warning +org.eclipse.jdt.core.compiler.problem.nonExternalizedStringLiteral=ignore +org.eclipse.jdt.core.compiler.problem.nullReference=ignore +org.eclipse.jdt.core.compiler.problem.overridingPackageDefaultMethod=warning +org.eclipse.jdt.core.compiler.problem.parameterAssignment=ignore +org.eclipse.jdt.core.compiler.problem.possibleAccidentalBooleanAssignment=ignore +org.eclipse.jdt.core.compiler.problem.potentialNullReference=ignore +org.eclipse.jdt.core.compiler.problem.rawTypeReference=ignore +org.eclipse.jdt.core.compiler.problem.redundantNullCheck=ignore +org.eclipse.jdt.core.compiler.problem.specialParameterHidingField=disabled +org.eclipse.jdt.core.compiler.problem.staticAccessReceiver=warning +org.eclipse.jdt.core.compiler.problem.suppressWarnings=enabled +org.eclipse.jdt.core.compiler.problem.syntheticAccessEmulation=ignore +org.eclipse.jdt.core.compiler.problem.typeParameterHiding=warning +org.eclipse.jdt.core.compiler.problem.uncheckedTypeOperation=ignore +org.eclipse.jdt.core.compiler.problem.undocumentedEmptyBlock=ignore +org.eclipse.jdt.core.compiler.problem.unhandledWarningToken=warning +org.eclipse.jdt.core.compiler.problem.unnecessaryElse=ignore +org.eclipse.jdt.core.compiler.problem.unnecessaryTypeCheck=ignore +org.eclipse.jdt.core.compiler.problem.unqualifiedFieldAccess=ignore +org.eclipse.jdt.core.compiler.problem.unusedDeclaredThrownException=ignore +org.eclipse.jdt.core.compiler.problem.unusedDeclaredThrownExceptionWhenOverriding=disabled +org.eclipse.jdt.core.compiler.problem.unusedImport=warning +org.eclipse.jdt.core.compiler.problem.unusedLabel=warning +org.eclipse.jdt.core.compiler.problem.unusedLocal=warning +org.eclipse.jdt.core.compiler.problem.unusedParameter=ignore +org.eclipse.jdt.core.compiler.problem.unusedParameterIncludeDocCommentReference=enabled +org.eclipse.jdt.core.compiler.problem.unusedParameterWhenImplementingAbstract=disabled +org.eclipse.jdt.core.compiler.problem.unusedParameterWhenOverridingConcrete=disabled +org.eclipse.jdt.core.compiler.problem.unusedPrivateMember=warning +org.eclipse.jdt.core.compiler.problem.varargsArgumentNeedCast=warning +org.eclipse.jdt.core.compiler.source=1.5 diff --git a/zpu/sw/simulator/ChangeLog b/zpu/sw/simulator/ChangeLog new file mode 100644 index 0000000..c645841 --- /dev/null +++ b/zpu/sw/simulator/ChangeLog @@ -0,0 +1,2 @@ +2007-08-04 Øyvind Harboe + * First version after open sourcing ZPU diff --git a/zpu/sw/simulator/build.xml b/zpu/sw/simulator/build.xml new file mode 100644 index 0000000..a5cc8a3 --- /dev/null +++ b/zpu/sw/simulator/build.xml @@ -0,0 +1,7 @@ + + + + + + + diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/Abel.java b/zpu/sw/simulator/com/zylin/zpu/simulator/Abel.java new file mode 100644 index 0000000..8d8667c --- /dev/null +++ b/zpu/sw/simulator/com/zylin/zpu/simulator/Abel.java @@ -0,0 +1,109 @@ + +package com.zylin.zpu.simulator; + +import com.zylin.zpu.simulator.exceptions.CPUException; +import com.zylin.zpu.simulator.exceptions.MemoryAccessException; + +public class Abel extends Simulator +{ + + protected int getIO() + { + return 0x8000; + } + + + + protected int ioRead(int addr) throws CPUException + { + switch (addr) + { + case 0xc000: + return syscall.readUART(); + + /* FIFO empty? bit 0, FIFO full bit 1(never the case) */ + case 0xc004: + return syscall.readFIFO(); + + case 0x9000: + case 0x9004: + case 0x9008: + case 0x900c: + + case 0x9010: + case 0x9014: + case 0x9018: + case 0x901c: + return readSampledTimer(addr, 0x9000); + + case 0x8800: + return readMHz(); + + default: + throw new MemoryAccessException(); + } + } + + /* + ; Read/write are on different addresses + ; The registers are 8 bits and mapped to bit[7:0] + ; + ; 0xC000 Write: Writes to UART TX FIFO (4 byte FIFO) + ; Read : Reads from UART RX FIFO (4 byte FIFO) + ; 0xC004 Read : UART status register + ; Bit 0 = RX FIFO empty + ; Bit 1 = TX FIFO full + ; 0xA000 Write: 8 LED's + */ + + /* + 0x9000 Write: bit 0: 1= reset counter + 0= counter running + bit 1: 1= sample counter (when set to 1) + 0=not used + Read : counter bit[7:0] + 0x9004 Read: counter bit [15:8] + 0x9008 Read: counter bit [23:16] + 0x900C Read: counter bit [31:24] + 0x9010 Read: counter bit [39:32] + 0x9014 Read: counter bit [47:40] + 0x9018 Read: counter bit [55:48] + 0x901C Read: counter bit [63:56] + + 0x8800 Read: unsigned 8-bit integer with FPGA frequency (in MHz) + */ + + protected void ioWrite(int addr, int val) throws MemoryAccessException + { + switch (addr) + { + case 0x9000: + writeTimerSampleReg(val); + case 0xc000: + syscall.writeUART(val); + break; + default: + throw new MemoryAccessException(); + } + } + + Abel() throws CPUException + { + } + + protected boolean emulateConfig() + { + return true; + } + + protected int getStartStack() + { + return getRAMSIZE()-8; + } + + protected int getRAMSIZE() + { + return 32768; + } + +} diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/FileTracer.java b/zpu/sw/simulator/com/zylin/zpu/simulator/FileTracer.java new file mode 100644 index 0000000..6ccca24 --- /dev/null +++ b/zpu/sw/simulator/com/zylin/zpu/simulator/FileTracer.java @@ -0,0 +1,285 @@ + +package com.zylin.zpu.simulator; + +import java.io.FileNotFoundException; +import java.io.IOException; +import java.io.LineNumberReader; + +import com.zylin.zpu.simulator.exceptions.CPUException; +import com.zylin.zpu.simulator.exceptions.GDBServerException; +import com.zylin.zpu.simulator.exceptions.TraceException; + +public class FileTracer implements Tracer +{ + private LineNumberReader file; + private boolean trigger; + private boolean resync; + private Simulator simulator; + private String line; + private boolean ignore; + + static class Trace + { + int pc; + int opcode; + int sp; + int stackA; + int stackB; + int intSp; + long cycle; + public boolean undefinedStackA; + public boolean undefinedStackB; + public boolean undefinedIntSp; + public void print() + { + System.err.println(Integer.toHexString(pc)+ " " + + Integer.toHexString(opcode) + " " + + Integer.toHexString(sp) + " " + + Integer.toHexString(stackA) + " " + + Integer.toHexString(stackB) + " " + + intSp + " " + + cycle); + + } + }; + private Trace[] trace= new Trace[100]; + private int current; + private String fileName; + private boolean metEnd; + + + public FileTracer(Simulator sim, String string) + { + simulator=sim; + fileName=string; + + resync=true; + + + for (int i=0; i=1) + { + portNumber=Integer.parseInt(args[0]); + } + } + + private void moreParse() + { + if (args.length>=2) + { + simulator.setTraceFile(args[1]); + } + } + + void run(String[] args) + { + this.args=args; + parseArgs(); + try + { + channel = ServerSocketChannel.open(); + try + { + System.out.println("Listening on port " + portNumber); + channel.socket().bind(new InetSocketAddress(portNumber)); + for (;;) + { + try + { + simulator=simFactory.create(); + simulator.suspend(); + moreParse(); + run(); + } catch (CPUException e) + { + e.printStackTrace(); + } + } + } finally + { + channel.close(); + } + } catch (IOException e1) + { + e1.printStackTrace(); + } + + } + + private void run() throws CPUException + { + final GDBServer gdbServer=new GDBServer(simulator, this); + simulator.setSyscall(gdbServer); + Thread thread = new Thread(new Runnable() + { + public void run() + { + try + { + gdbServer.gdbServer(); + } + catch (Throwable e) + { + e.printStackTrace(); + } + simulator.shutdown(); + } + }); + thread.start(); + try + { + simulator.run(); + } + finally + { + + try + { + thread.join(); + } catch (InterruptedException e) + { + e.printStackTrace(); + } + } + + } +} diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/SimFactory.java b/zpu/sw/simulator/com/zylin/zpu/simulator/SimFactory.java new file mode 100644 index 0000000..4db85d7 --- /dev/null +++ b/zpu/sw/simulator/com/zylin/zpu/simulator/SimFactory.java @@ -0,0 +1,8 @@ +package com.zylin.zpu.simulator; + +public interface SimFactory +{ + + Simulator create(); + +} diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/Simulator.java b/zpu/sw/simulator/com/zylin/zpu/simulator/Simulator.java new file mode 100644 index 0000000..c1b86d4 --- /dev/null +++ b/zpu/sw/simulator/com/zylin/zpu/simulator/Simulator.java @@ -0,0 +1,2063 @@ +package com.zylin.zpu.simulator; + +import java.io.ByteArrayOutputStream; +import java.io.FileOutputStream; +import java.io.IOException; +import java.io.InputStream; +import java.io.OutputStream; +import java.util.Collections; +import java.util.Comparator; +import java.util.LinkedList; +import java.util.List; + +import com.zylin.zpu.simulator.FileTracer.Trace; +import com.zylin.zpu.simulator.exceptions.CPUException; +import com.zylin.zpu.simulator.exceptions.DebuggerBreakpointException; +import com.zylin.zpu.simulator.exceptions.EndSessionException; +import com.zylin.zpu.simulator.exceptions.GDBServerException; +import com.zylin.zpu.simulator.exceptions.HardwareWatchPointException; +import com.zylin.zpu.simulator.exceptions.IllegalInstructionException; +import com.zylin.zpu.simulator.exceptions.InterruptException; +import com.zylin.zpu.simulator.exceptions.MemoryAccessException; + +public class Simulator implements ZPU, Machine, Sim +{ + + int minStack; + + /** + * the feeble version of the CPU, e.g. only implements + * 11 instructions. + * + * For debugging purposes it is useful to enable/disable + * each instruction + */ + boolean feeble[]=new boolean[256]; + + private long opcodeHistogram[]=new long[256]; + private long opcodeHistogramCycles[]=new long[256]; + private long opcodePairHistogram[]=new long[256*256]; + private long opcodePairHistogramCycles[]=new long[256*256]; + + /** weee! constants are 32 bit by default, so we need to assign a 64 bit + * integer in this matter. + */ + private static final long INTMASK = Long.parseLong("ffffffff", 16); + + final static int PUSHPC=59; + final static int OR=7; + final static int NOT=9; + final static int LOAD=8; + final static int STORE=12; + final static int POPPC=4; + final static int FLIP=10; + + final static int ADD=5; + final static int PUSHSP=2; + final static int POPSP=13; + final static int NOP=11; + final static int AND=6; + final static int ADDSP=16; + + final static int EMULATE=32; + final static int LOADH=34; + final static int STOREH=35; + final static int LESSTHAN=36; + final static int LESSTHANOREQUAL=37; + final static int ULESSTHAN=38; + final static int ULESSTHANOREQUAL=39; + final static int SWAP=40; + final static int MULT=41; + final static int LSHIFTRIGHT=42; + final static int ASHIFTLEFT=43; + final static int ASHIFTRIGHT=44; + final static int CALL=45; + final static int EQ=46; + final static int NEQ=47; + final static int NEG=48; + final static int SUB=49; + final static int XOR=50; + final static int LOADB=51; + final static int STOREB=52; + final static int DIV=53; + final static int MOD=54; + final static int EQBRANCH=55; + final static int NEQBRANCH=56; + final static int POPPCREL=57; + final static int CONFIG=58; + final static int SYSCALL=60; + final static int PUSHSPADD=61; + final static int MULT16X16=62; + final static int CALLPCREL=63; + final static int STORESP=64; + final static int LOADSP=64+32; + + int[] memory; + boolean[] validMemory; + protected long cycles; + protected int instructionCount; + private int sp; + private int pc; + protected boolean breakNext; + + /* halting synchronization object */ + protected Object halt = new Object(); + + private int IOSIZE=getIOSIZE(); + protected int getIOSIZE() + { + return 32768; + } + long prevCycles; + private static final int VECTORSIZE = 0x20; + private static final int VECTOR_RESET = 0; + private static final int VECTOR_INTERRUPT = 1; + private boolean hitVector; + private static final int VECTORBASE = 0x0; + private int nextVector; + protected long lastTimer; + protected boolean timer; + private boolean powerdown; + private boolean decodeMask; + + private static final int ZETA = 1; + + private static final int ABEL = 0; + + private int startStack; + + protected Host syscall; + + private long[] emulateOpcodeHistogram= new long[256]; + + private long[] emulateOpcodeHistogramCycles=new long[256]; + + private long emulateCycles;; + + public Simulator() throws CPUException + { + } + + + public void run() throws CPUException + { + syscall.running(); + + try + { + + instructionLoop(); + + + } catch (EndSessionException e) + { + /* done */ + } finally + { + } + dumpInfo(); + + System.err.println("Stack usage: " + (startStack-minStack)); + } + + private void dumpInfo() + { + dumpOpcodeHistogram(); + + //printMemoryHistorgram(); + } + + + private void dumpOpcodeHistogram() + { + System.out.println("Opcode histogram"); + dumpHistogram(opcodeHistogram, opcodeHistogramCycles); + System.out.println("Emulate histogram"); + dumpHistogram(emulateOpcodeHistogram, emulateOpcodeHistogramCycles); + System.out.println("Pair histogram"); + dumpHistogram(opcodePairHistogram, opcodePairHistogramCycles); + + + dumpGmon(); + + System.out.println("Grouping of LOADSP/STORESP/IM"); + printRange(64, 96); + printRange(96, 128); + printRange(128, 256); +// printRange(64, 65); +// printRange(65, 66); +// printRange(66, 64+32); +// printRange(96, 97); +// printRange(97, 98); +// printRange(98, 96+32); +// printRange(128, 129); +// printRange(129, 130); +// printRange(130, 131); +// printRange(131, 132); +// printRange(132, 133); +// printRange(252, 253); +// printRange(253, 254); +// printRange(254, 255); +// printRange(255, 256); + } + + + +// #define GMON_MAGIC "gmon" /* magic cookie */ +// #define GMON_VERSION 1 /* version number */ +// +// /* +// * Raw header as it appears on file (without padding): +// */ +// struct gmon_hdr +// { +// char cookie[4]; +// char version[4]; // a cyg_uint32, target-side endianness +// char spare[3 * 4]; +// }; +// +// /* types of records in this file: */ +// typedef enum +// { +// GMON_TAG_TIME_HIST = 0, GMON_TAG_CG_ARC = 1, GMON_TAG_BB_COUNT = 2 +// } +// GMON_Record_Tag; +// +// /* The histogram tag is followed by this header, and then an array of */ +// /* cyg_uint16's for the actual counts. */ +// +// struct gmon_hist_hdr +// { +// /* host-side gprof adapts to sizeof(void*) and endianness. */ +// /* It is assumed that the compiler does not insert padding around the */ +// /* cyg_uint32's or the char arrays. */ +// void* low_pc; /* base pc address of sample buffer */ +// void* high_pc; /* max pc address of sampled buffer */ +// cyg_uint32 hist_size; /* size of sample buffer */ +// cyg_uint32 prof_rate; /* profiling clock rate */ +// char dimen[15]; /* phys. dim., usually "seconds" */ +// char dimen_abbrev; /* usually 's' for "seconds" */ +// }; +// +// /* An arc tag is followed by a single arc record. self_pc corresponds to */ +// /* the location of an mcount() call, at the start of a function. from_pc */ +// /* corresponds to the return address, i.e. where the function was called */ +// /* from. count is the number of calls. */ +// +// struct gmon_cg_arc_record +// { +// void* from_pc; /* address within caller's body */ +// void* self_pc; /* address within callee's body */ +// cyg_uint32 count; /* number of arc traversals */ +// }; +// +// /* In theory gprof can also process basic block counts, as per the */ +// /* compiler's -fprofile-arcs flag. The compiler-generated basic block */ +// /* structure should contain a table of addresses and a table of counts, */ +// /* and the compiled code updates those counts. Current versions of the */ +// /* compiler (~3.2.1) do not output the table of addresses, and without */ +// /* that table gprof cannot process the counts. Possibly gprof should read */ +// /* in the .bb and .bbg files generated for gcov processing, but that does */ +// /* not happen at the moment. */ +// /* */ +// /* So for now gmon.out does not contain basic block counts and gprof */ +// /* operations that depend on it, e.g. --annotated-source, won't work. */ + + /** + * Write gmon.out file. + **/ + private void dumpGmon() + { + try + { + ByteArrayOutputStream b=new ByteArrayOutputStream(); + + +// /* +// * Raw header as it appears on file (without padding): +// */ +// struct gmon_hdr +// { +// char cookie[4]; +// char version[4]; // a cyg_uint32, target-side endianness +// char spare[3 * 4]; +// }; +// #define GMON_MAGIC "gmon" /* magic cookie */ +// #define GMON_VERSION 1 /* version number */ + +// dump binary memory gmon.out &profile_gmon_hdr ((char*)&profile_gmon_hdr + sizeof(struct gmon_hdr)) + b.write("gmon".getBytes()); + writeLong(b, 1); // version + b.write(new byte[3*4]); // spare + +// GMON_TAG_TIME_HIST = 0, GMON_TAG_CG_ARC = 1, GMON_TAG_BB_COUNT = 2 + +// append binary memory gmon.out &profile_tags[0] &profile_tags[1] + b.write(new byte[]{0}); // GMON_TAG_TIME_HIST + + +// +// // The gprof documentation claims that this should be the size in +// // bytes. The implementation treats it as a count. +// profile_hist_hdr.hist_size = (cyg_uint32) ((text_size + bucket_size - 1) / bucket_size); +// profile_hist_hdr.low_pc = _start; +// profile_hist_hdr.high_pc = (void*)((cyg_uint8*)_end - 1); +// // The prof_rate is the frequency in hz. The resolution argument is +// // an interval in microseconds. +// profile_hist_hdr.prof_rate = 1000000 / resolution; +// +// // Now allocate a buffer for the histogram data. +// profile_hist_data = (cyg_uint16*) malloc(profile_hist_hdr.hist_size * sizeof(cyg_uint16)); +// if ((cyg_uint16*)0 == profile_hist_data) { +// diag_printf("profile_on(): cannot allocate histogram buffer - ignored\n"); +// return; +// } +// memset(profile_hist_data, 0, profile_hist_hdr.hist_size * sizeof(cyg_uint16)); + + + +// struct gmon_hist_hdr +// { +// /* host-side gprof adapts to sizeof(void*) and endianness. */ +// /* It is assumed that the compiler does not insert padding around the */ +// /* cyg_uint32's or the char arrays. */ +// void* low_pc; /* base pc address of sample buffer */ +// void* high_pc; /* max pc address of sampled buffer */ +// cyg_uint32 hist_size; /* size of sample buffer */ +// cyg_uint32 prof_rate; /* profiling clock rate */ +// char dimen[15]; /* phys. dim., usually "seconds" */ +// char dimen_abbrev; /* usually 's' for "seconds" */ +// }; + + + // maximum 65536 buckets. + int length=memory.length*4; + if (length > 60000) + { + length=60000; + } + int buckets[]=new int[length]; + for (long i=0; i65535) + { + val=65535; + } + writeShort(b, val); + } + + OutputStream o=new FileOutputStream("gmon.out"); + b.writeTo(o); + o.flush(); + o.close(); + + } catch (IOException e) + { + // TODO Auto-generated catch block + e.printStackTrace(); + } + + + + } + + + private void writeLong(ByteArrayOutputStream b, int i) throws IOException + { + int val=i; + b.write(new byte[]{(byte)((val>>24)&0xff), + (byte)((val>>16)&0xff), + (byte)((val>>8)&0xff), + (byte)((val>>0)&0xff)}); + } + + + private void writeShort(ByteArrayOutputStream b, int i) throws IOException + { + int val=i; + b.write(new byte[]{ (byte)((val>>8)&0xff), + (byte)((val>>0)&0xff)}); + } + + + private void dumpHistogram(long[] ms, long[] ms2) + { + List l=new LinkedList(); + + totalCycles = 0; + for (int i=0; i<256; i++) + { + totalCycles+=opcodeHistogramCycles[i]; + } + for (int i=0; i>(32-7); + + if (decodeMask) + { + int a; + a=(popIntStack()<<7)|(t&0x7f); + pushIntStack(a); + } else + { + pushIntStack(t); + } + decodeMask=true; + } else + { + decodeMask = false; + if (isAddSP(instruction)) + { + int offset=instruction - ADDSP; + int valAddr=sp+offset*4; + int a = popIntStack(); + pushIntStack(cpuReadLong(valAddr) + a); + } else if ((instruction >= LOADSP) && (instruction < LOADSP + 32)) + { + int addr; + addr = getSp(); + int offset=(instruction - LOADSP)^0x10; + addr += 4 * offset; + pushIntStack(cpuReadLong(addr)); + } else if (isStoreSP(instruction)) + { + int addr; + addr = getSp(); + int offset=(instruction - STORESP)^0x10; + addr += 4 * offset; + + cpuWriteLong(addr, popIntStack()); + } else + { + int addr; + int val; + switch (instruction) + { + case 0: + throw new DebuggerBreakpointException(); + + case PUSHPC: + pushIntStack(pc); + break; + case OR: + pushIntStack(popIntStack() | popIntStack()); + break; + case NOT: + pushIntStack(popIntStack() ^ 0xffffffff); + break; + case LOAD: + pushIntStack(cpuReadLong(popIntStack())); + break; + case PUSHSPADD: + if (feeble[PUSHSPADD]) + { + emulate(); + } else + { + int a; + int b; + a=sp; + b=popIntStack()*4; + pushIntStack(a+b); + } + break; + case STORE: + addr = popIntOrExt(); + val = popIntOrExt(); + cpuWriteLong(addr, val); + break; + case POPPC: + { + // NB!!!! does NOT flush internal stack + int a; + if (intSp>0) + { + a=popIntStack(); + } else + { + a=pop(); + } + + if ((sp>=emulateSp)&&(emulateInProgress)) + { + emulateInProgress=false; + /* we returned from an emulate instruction */ + emulateOpcodeHistogram[emulateOpcode]++; + emulateOpcodeHistogramCycles[emulateOpcode]+=cycles-emulateCycles; + } + + setPc(a); + break; + } + case POPPCREL: + if (feeble[POPPCREL]) + { + emulate(); + } else + { + setPc(popIntStack()+getPc()); + } + break; + case FLIP: + pushIntStack(flip(popIntStack())); + break; + case ADD: + pushIntStack(popIntStack() + popIntStack()); + break; + case SUB: + if (feeble[SUB]) + { + emulate(); + } else + { + int a=popIntStack(); + int b=popIntStack(); + pushIntStack(b-a); + } + break; + case PUSHSP: + pushIntStack(getSp()); + break; + case POPSP: + changeSp(popIntStack()); + intSp=0; // flush internal stack + break; + case NOP: + break; + case AND: + pushIntStack(popIntStack() & popIntStack()); + break; + case XOR: + if (feeble[XOR]) + { + emulate(); + } else + { + pushIntStack(popIntStack() ^ popIntStack()); + } + break; + case LOADB: + if (feeble[LOADB]) + { + emulate(); + } else + { + pushIntStack(cpuReadByte(popIntStack())); + } + break; + case STOREB: + if (feeble[STOREB]) + { + emulate(); + } else + { + addr = popIntStack(); + val = popIntStack(); + cpuWriteByte(addr, val); + } + break; + case LOADH: + if (feeble[LOADH]) + { + emulate(); + } else + { + pushIntStack(cpuReadWord(popIntStack())); + } + break; + case STOREH: + if (feeble[STOREH]) + { + emulate(); + } else + { + addr = popIntStack(); + val = popIntStack(); + cpuWriteWord(addr, val); + } + break; + case LESSTHAN: + if (feeble[LESSTHAN]) + { + emulate(); + } else + { + int a; + int b; + a = popIntStack(); + b = popIntStack(); + pushIntStack((a < b) ? 1 : 0); + } + break; + case LESSTHANOREQUAL: + if (feeble[LESSTHANOREQUAL]) + { + emulate(); + } else + { + int a; + int b; + a = popIntStack(); + b = popIntStack(); + pushIntStack((a <= b) ? 1 : 0); + } + break; + case ULESSTHAN: + if (feeble[ULESSTHAN]) + { + emulate(); + } else + { + long a; + long b; + a = ((long) popIntStack()) & INTMASK; + b = ((long) popIntStack()) & INTMASK; + pushIntStack((a < b) ? 1 : 0); + } + break; + case ULESSTHANOREQUAL: + if (feeble[ULESSTHANOREQUAL]) + { + emulate(); + } else + { + long a; + long b; + a = ((long) popIntStack()) & INTMASK; + b = ((long) popIntStack()) & INTMASK; + pushIntStack((a <= b) ? 1 : 0); + } + break; + + case SWAP: +// if (feeble[SWAP]) +// { +// emulate(); +// } else + { + int swapVal=popIntStack();; + pushIntStack(((swapVal >>16)&0xffff)|(swapVal<<16)); + } + break; + case MULT16X16: +// if (feeble[SWAP]) +// { +// emulate(); +// } else + { + int a=popIntStack(); + int b=popIntStack(); + pushIntStack((a&0xffff)*(b&0xffff)); + } + break; + case EQBRANCH: + if (feeble[EQBRANCH]) + { + emulate(); + } else + { + int compare; + int target; + target = popIntStack() + pc; + compare = popIntStack(); + if (compare == 0) + { + setPc(target); + } else + { + setPc(pc + 1); + } + } + break; + + case NEQBRANCH: + if (feeble[NEQBRANCH]) + { + emulate(); + } else + { + int compare; + int target; + target = popIntStack() + pc; + compare = popIntStack(); + if (compare != 0) + { + setPc(target); + } else + { + setPc(pc + 1); + } + } + break; + + case MULT: + if (feeble[MULT]) + { + emulate(); + } else + { + pushIntStack(popIntStack() * popIntStack()); + } + break; + case DIV: + if (feeble[DIV]) + { + emulate(); + } else + { + int a; + int b; + a = popIntStack(); + b = popIntStack(); + if (b == 0) + { + throw new CPUException(); + } + pushIntStack(a / b); + } + break; + case MOD: + if (feeble[MOD]) + { + emulate(); + } else + { + int a; + int b; + a = popIntStack(); + b = popIntStack(); + if (b == 0) + { + throw new CPUException(); + } + pushIntStack(a % b); + } + break; + + case LSHIFTRIGHT: + if (feeble[LSHIFTRIGHT]) + { + emulate(); + } else + { + long shift; + long valX; + int t; + shift = ((long) popIntStack()) & INTMASK; + valX = ((long) popIntStack()) & INTMASK; + t = (int) (valX >> (shift & 0x3f)); + pushIntStack(t); + } + break; + + case ASHIFTLEFT: + if (feeble[ASHIFTLEFT]) + { + emulate(); + } else + { + long shift; + long valX; + shift = ((long) popIntStack()) & INTMASK; + valX = ((long) popIntStack()) & INTMASK; + int t = (int) (valX << (shift & 0x3f)); + pushIntStack(t); + } + break; + + case ASHIFTRIGHT: + if (feeble[ASHIFTRIGHT]) + { + emulate(); + } else + { + long shift; + int valX; + shift = ((long) popIntStack()) & INTMASK; + valX = popIntStack(); + int t = valX >> (shift & 0x3f); + pushIntStack(t); + } + break; + + case CALL: + if (feeble[CALL]) + { + emulate(); + } else + { + intSp=0; // flush internal stack + int address = pop(); + push(pc + 1); + setPc(address); + } + break; + case CALLPCREL: + if (feeble[CALLPCREL]) + { + emulate(); + } else + { + intSp=0; // flush internal stack + int address = pop(); + push(pc + 1); + setPc(address+pc); + } + break; + + case EQ: + if (feeble[EQ]) + { + emulate(); + } else + { + pushIntStack((popIntStack() == popIntStack()) ? 1 : 0); + } + break; + + case NEQ: + if (feeble[NEQ]) + { + emulate(); + } else + { + pushIntStack((popIntStack() != popIntStack()) ? 1 : 0); + } + break; + + case NEG: + if (feeble[NEG]) + { + emulate(); + } else + { + pushIntStack(-popIntStack()); + } + break; + + + case CONFIG: + if (emulateConfig()) + { + emulate(); + cpu=ABEL; + } else + { + cpu = popIntStack(); + } + switch (cpu) + { + case ABEL: + System.err.println("ZPU feeble instruction set"); + for (int i = 0; i < feeble.length; i++) + { + feeble[i] = true; + } + + setFeeble(); + + break; + case ZETA: + System.err.println("ZPU full instruction set"); + for (int i = 0; i < feeble.length; i++) + { + feeble[i] = false; + } + break; + default: + break; + } + break; + + case SYSCALL: + if (feeble[SYSCALL]) + { + throw new IllegalInstructionException(); + } else + { + intSp=0; // flush internal stack + syscall.syscall(this); + } + break; + + default: + throw new IllegalInstructionException(); + } + } + } + if (!touchedPc) + { + setPc(pc + 1); + } + committed(); + + // one more instruction retired + instructionCount++; + } + } + + + protected void setFeeble() + { + feeble[NEQBRANCH] = false; + feeble[EQ] = false; + feeble[LOADB] = false; + feeble[LESSTHAN] = false; + feeble[ULESSTHAN] = false; + feeble[STOREB] = false; + feeble[MULT] = false; + feeble[CALL] = true; + feeble[POPPCREL] = true; + feeble[LESSTHANOREQUAL] = true; + feeble[ULESSTHANOREQUAL] = true; + + feeble[PUSHSPADD] = false; + feeble[CALLPCREL] = false; + feeble[SUB] = false; + } + + + private int popIntOrExt() + { + int a; + if (intSp==0) + { + a=pop(); + } else + { + a=popIntStack(); + } + return a; + } + + int intSp; + + private int emulateSp; + + private int emulateOpcode; + + private boolean emulateInProgress; + + protected boolean timerPending; + + private boolean inInterrupt; + private int popIntStack() + { +// if (intSp<=0) +// throw new IllegalInstructionException(); + intSp--; + return pop(); + } + + private void pushIntStack(int x) + { +// if (intSp>=32) +// throw new IllegalInstructionException(); + push(x); + intSp++; + } + + + + private static boolean isAddSP(int instruction) + { + return (instruction >= ADDSP) && (instruction < ADDSP + 16); + } + + + private static boolean isStoreSP(int instruction) + { + return (instruction >= STORESP) && (instruction < STORESP + 32); + } + + + protected boolean emulateConfig() + { + return false; + } + + + private void checkCommit() throws CPUException + { + if (!commit) + { + decodeMask=savedDecodeMask; + pc=savedPc; + setSp(savedSp); + committed(); + } + } + + + private void committed() + { + commit=true; + tracer.commit(); + } + + + private void emulate() throws CPUException + { + // NB! Do NOT flush internal stack +// intSp=0; // flush internal stack + /* three total overhead to emulate instruction */ + if (!emulateInProgress) + { + emulateInProgress=true; + emulateSp = sp; + emulateOpcode = getOpcode(); + emulateCycles = cycles; + } + pushIntStack(pc+1); + setPc((cpuReadByte(pc)-32)*VECTORSIZE+VECTORBASE); + } + + + + private void checkInterrupts() throws InterruptException + { + if (!tracer.simInterrupt()) + { + /* These flags are set *regardless* of interrupt state. */ + while (lastTimer+timerInterval0) + { + lastTimer+=timerInterval; + } else + { + lastTimer=cycles; + } + timerPending=true; + } + } + + if (!interrupt) + return; + + /* if we are in the middle of decoding an instruction, no interrupt */ + if (decodeMask) + { + return; + } + if (tracer.simInterrupt()) + { + if (!tracer.onInterrupt()) + { + inInterrupt=false; + } + if (inInterrupt) + { + return; + } + /* Use trace information instead of trying to figure out when an interrupt happens. We don't try + * to simulate anything more complicated than timer interrupts so we don't need to worry about source. + */ + + if (tracer.onInterrupt()&&!inInterrupt) + { + if (!timer) + { + throw new IllegalInstructionException(); + } + + inInterrupt=true; + timerPending=true; + throw new InterruptException(); + } + + } else + { + if (!timerPending) + inInterrupt=false; + + if (inInterrupt) + { + return; + } + + if (timer&&timerPending) + { + inInterrupt=true; + throw new InterruptException(); + } + } + } + + + + + private void cpuWriteWord(int addr, int val) throws MemoryAccessException + { + if ((addr&0x1)!=0) + { + throw new MemoryAccessException(); + } + for (int i=0; i<2; i++) + { + writeByte(addr+i, val>>(8*(1-i))); + } + } + + /** + * @param i + * @return + * @throws MemoryAccessException + */ + private int cpuReadWord(int addr) throws MemoryAccessException + { + if ((addr&0x1)!=0) + { + throw new MemoryAccessException(); + } + return ((readByteInternal(addr+0)&0xff)<<8) | (readByteInternal(addr+1)&0xff); + } + + private void cpuWriteByte(int addr, int val) throws MemoryAccessException + { + writeByte(addr, val); + } + + + protected boolean interrupt; + protected long timerInterval; + private boolean touchedPc; + + private boolean accessWatchPoint; + + private int accessWatchPointAddress; + + private int accessWatchPointLength; + + private boolean commit; + + private boolean savedDecodeMask; + + private int savedSp; + + private int savedPc; + + private long[] profile; + + private int cpu; + + private long sampledCycle; + + private Tracer tracer=new Tracer() + { + + public void instructionEvent() + { + + } + + public void commit() + { + } + + public void setSp(int sp) + { + } + + public void dumpTraceBack() + { + + } + + public boolean onInterrupt() + { + return false; + } + + public boolean simInterrupt() + { + return false; + } + + }; + + private int instruction; + + private long totalCycles; + + + private String traceFileName; + + private int prevOpcode; + + private long prevCycles2; + + private int prevOpcode2; + + + + + /** + * checks if the CPU should halt, and halts. Fn. returns when the + * CPU has resumed execution. + * @throws EndSessionException + */ + private void checkHalt() throws EndSessionException + { + synchronized(halt) + { + if (powerdown) + { + throw new EndSessionException(); + } + + if (breakNext) + { + breakNext=false; + + halt.notify(); + try + { + syscall.halted(); + halt.wait(); + syscall.running(); + } catch (InterruptedException e) + { + e.printStackTrace(); + } + } + + if (powerdown) + { + throw new EndSessionException(); + } + } + } + + private int flip(int i) + { + int t=0; + for (int j=0; j<32; j++) + { + t|=((i>>j)&1)<<(31-j); + } + return t; + } + + /** the CPU is writing a long during execution */ + public void cpuWriteLong(int addr, int val) throws MemoryAccessException + { + if (accessWatchPoint&&(addr==accessWatchPointAddress)) + { + suspend(); + } + if ((addr&0x3)!=0) + { + throw new MemoryAccessException(); + } + if ((addr>=getIO())&&(addr=0)&&(addr<=memory.length*4)) + { + memory[addr/4]=val; + validMemory[addr/4]=true; + } else + { + throw new MemoryAccessException(); + } + } + + public void writeByte(int addr, int val) throws MemoryAccessException + { + if ((addr>=0)&&(addr>(((addr-base)/4)*32))&0xffffffff); + return t; + } + + + + private int cpuReadByte(int addr) throws MemoryAccessException + { + return readByteInternal(addr); + } + + + /** this is the CPU reading a long word during execution */ + public int cpuReadLong(int addr) throws CPUException + { + if (accessWatchPoint&&(addr==accessWatchPointAddress)) + { + suspend(); + } + if ((addr&0x3)!=0) + { + throw new MemoryAccessException(); + } + if ((addr>=getIO())&&(addr=0)&&(addr<=memory.length*4)) + { + return memory[addr/4]; + } else + { + throw new MemoryAccessException(); + } + } + + /** + * Causes a cycle to pass. + * @throws MemoryAccessException + */ + /** increase time and record how long we spent on this instruction */ + private void tick() throws MemoryAccessException + { + profile[pc]++; + int opcode; + opcode=readByte(pc); + opcodeHistogram[prevOpcode]++; + opcodeHistogramCycles[prevOpcode]+=cycles-prevCycles; + int opcodePair=groupOpcode(prevOpcode2)*256+groupOpcode(prevOpcode); + + opcodePairHistogram[opcodePair]++; + opcodePairHistogramCycles[opcodePair]+=cycles-prevCycles2; + + prevOpcode2=prevOpcode; + prevOpcode=opcode; + + + + prevCycles2=prevCycles; + prevCycles=cycles; + cycles++; + } + + private int groupOpcode(int instruction) + { + if (isAddSP(instruction)) + { + return ADDSP; + } else if ((instruction >= LOADSP) && (instruction < LOADSP + 32)) + { + return LOADSP; + } else if (isStoreSP(instruction)) + { + return STORESP; + } + + if ((instruction&0x80)!=0) + return 0x80; + return instruction; + } + + + public int readByte(int addr) throws MemoryAccessException + { + if ((addr>=0)&&(addr>((3-addr&0x3)*8))&0xff; + } + + private int pop() throws CPUException + { + int val; + validMemory[getSp()/4]=false; + val=cpuReadLong(getSp()); + setSp(getSp() + 4); + return val; + } + + private void push(int imm) throws CPUException + { + setSp(getSp() - 4); + cpuWriteLong(getSp(), imm); + } + + private final class OpcodeSample + { + private final int j; + + int opcode; + + long count; + + private OpcodeSample(int j, long l) + { + this.j = j; + opcode = j; + count = l; + } + } + + + + + private void initRam() + { + memory = (new int[getRAMSIZE()/4]); + validMemory = new boolean[getRAMSIZE()/4]; + for (int i=0; imemory.length*4)) + { + throw new MemoryAccessException(); + } + this.pc = pc; + touchedPc=true; + } + + public int getPc() + { + return pc; + } + + /** resume execution. This function returns when the CPU halts again. */ + public void cont() + { + for (;;) + { + synchronized(halt) + { + halt.notify(); + try + { + halt.wait(); + } catch (InterruptedException e) + { + e.printStackTrace(); + } + } + if (syscall.doneContinue()) + { + break; + } + } + } + + /** resume execution. This function returns when the CPU halts again. */ + public void step() + { + synchronized(halt) + { + suspend(); + cont(); + } + } + + + + public int getReg(int regNum) throws CPUException + { + if ((regNum>=0)&&(regNum<32)) + { + return memory[regNum]; + } else if (regNum==32) + { + return getSp(); + } else if (regNum==33) + { + return pc; + } else + { + throw new RuntimeException("Illegal getReg()"); + } + } + + public int getREGNUM() + { + return 34; + } + + public long getCycleCounter() + { + return cycles; + } + + public void addWaitStates(int num) + { + } + + /** tells simulator to enter the suspended state */ + public void suspend() + { + synchronized(halt) + { + breakNext=true; + } +// tracer.dumpTraceBack(); + } + + + public long getPrevCycles() + { + return prevCycles; + } + + public long getCycles() + { + return cycles; + } + + + public void enableAccessWatchPoint(int address, int length) throws CPUException + { + if (accessWatchPoint) + { + throw new HardwareWatchPointException(); + } + accessWatchPointAddress=address; + accessWatchPointLength=length; + accessWatchPoint=true; + } + public void disableAccessWatchPoint(int address, int length) throws CPUException + { + if (!accessWatchPoint) + { + throw new HardwareWatchPointException(); + } + if ((address!=accessWatchPointAddress)||(length!=accessWatchPointLength)) + { + throw new HardwareWatchPointException(); + } + + accessWatchPoint=false; + } + + /** POPSP changes the stack pointer */ + public void changeSp(int sp) throws CPUException + { + setSp(sp); + tracer.setSp(sp); + } + + public void setSp(int sp) throws CPUException + { + if ((sp%4)!=0) + { + throw new IllegalInstructionException(); + } + + if (sppad.length()) + { + t=t.substring(0, pad.length()); + } + return pad.substring(0, pad.length()-t.length())+t; + } + + public void write(byte[] bytes) throws IOException + { + int i=0; + while (i0) + { + writeBuffer.flip(); + int len=writeBuffer.limit(); + + int j=0; + while (j0?0:1; + } catch (IOException e) + { + e.printStackTrace(); + } + return 1; + } + + public void halted() + { + // TODO Auto-generated method stub + + } + + public void running() + { + // TODO Auto-generated method stub + + } +} diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/gdb/Packet.java b/zpu/sw/simulator/com/zylin/zpu/simulator/gdb/Packet.java new file mode 100644 index 0000000..7925bd5 --- /dev/null +++ b/zpu/sw/simulator/com/zylin/zpu/simulator/gdb/Packet.java @@ -0,0 +1,455 @@ +/* + * Created on Nov 16, 2004 + * + * To change the template for this generated file go to + * Window - Preferences - Java - Code Generation - Code and Comments + */ +package com.zylin.zpu.simulator.gdb; + +import java.io.IOException; +import java.util.regex.Matcher; +import java.util.regex.Pattern; + +import com.zylin.zpu.simulator.exceptions.BadPacketException; +import com.zylin.zpu.simulator.exceptions.CPUException; +import com.zylin.zpu.simulator.exceptions.EndSessionException; +import com.zylin.zpu.simulator.exceptions.GDBServerException; +import com.zylin.zpu.simulator.exceptions.MemoryAccessException; +import com.zylin.zpu.simulator.exceptions.NoAckException; +import com.zylin.zpu.simulator.exceptions.UnknownPacketException; + + +/** all packet related operations */ +class Packet +{ + private final GDBServer server; + + Packet(GDBServer server) + { + this.server = server; + reply=new StringBuffer(); + } + + void receive() throws IOException, GDBServerException, EndSessionException + { + int t; + /* we spool until we see a $ */ + this.server.expect('$'); + + StringBuffer packet=new StringBuffer(); + + int cc=0; + for (;;) + { + int t1; + t1=this.server.read(); + t = t1; + if (t==0x7d) + { + int t2; + t2=this.server.read(); + /* the next char is escaped after a GDB specific scheme. See + * gdb/gdb/remote.c */ + t = t2; + t^=0x20; + } else + { + if (t=='#') + { + break; + } + } + + cc+=t; + + packet.append((char)t); + } + cc&=0xff; + + String checkSum; + checkSum=""+(char)this.server.read()+(char)this.server.read(); + int readCheckSum; + readCheckSum=Integer.parseInt(checkSum, 16); + if (readCheckSum!=cc) + { + // error + dumpHex(packet.toString()); + + this.server.write("-".getBytes()); + throw new BadPacketException(); + } else + { + // ack + this.server.write("+".getBytes()); + } + + cmd=packet.toString(); + this.server.print(GDBServer.PACKET, "Got " + number + ": #$" + cmd + "#" + checkSum); + origCmd=cmd; + } + + void parseAndExecute() throws IOException, EndSessionException + { + boolean silent=false; + try + { + if (checkPrefix("g")) + { + readRegisters(); + } else if (checkPrefix("?")) + { + querySignal(); + } else if (checkPrefix("s")) + { + doStep(); + } else if (checkPrefix("m")) + { + try + { + readMemory(); + } catch (CPUException e) + { + silent=true; // happens all the time while hovering over variables in the GUI + throw e; + } + } else if (checkPrefix("c")) + { + continueExecution(); + } else if (checkPrefix("M")) + { + writeMemory(); + } else if (checkPrefix("z4")) + { + disableAccessWatchPoint(); + } else if (checkPrefix("Z4")) + { + enableAccessWatchPoint(); + } else if (checkPrefix("k")) + { + /* we must send a reply, but not wait for ack before we shut down + the connection. + */ + server.alive=false; + reply("OK"); + } else + { + throw new UnknownPacketException(); + } + } catch (UnknownPacketException e) + { + this.server.print(GDBServer.UNKNOWN, "Unknown packet: " + origCmd); + // empty reply to unknown packets + } catch (CPUException e) + { + if (!silent) + { + this.server.print(GDBServer.CPUEXCEPTION, "Exception handling GDB request"); + if (GDBServer.CPUEXCEPTION) + { + e.printStackTrace(); + } + } + reply("E01"); + } catch (GDBServerException e) + { + e.printStackTrace(); + reply("E01"); + } catch (RuntimeException e) + { + e.printStackTrace(); + reply("E01"); + } + } + + private void checkEmpty() throws GDBServerException + { + if (cmd.length()>0) + { + throw new GDBServerException(); + } + } + private void dumpHex(String arrayList2) + { + for (int i=0; i4) + { + byte[] tmp=new byte[4]; + file.read(tmp); + int word=0; + for (int j=0; j<4; j++) + { + word|=((int)(tmp[j])&0xff)<<((3-j)*8); + } + String str=Integer.toHexString(word); + while (str.length()<8) + { + str="0"+str; + } + + System.out.println(str); + i++; + } + } + +} diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/tools/MakeRam.java b/zpu/sw/simulator/com/zylin/zpu/simulator/tools/MakeRam.java new file mode 100644 index 0000000..4a7b233 --- /dev/null +++ b/zpu/sw/simulator/com/zylin/zpu/simulator/tools/MakeRam.java @@ -0,0 +1,39 @@ + +package com.zylin.zpu.simulator.tools; + +import java.io.FileInputStream; +import java.io.IOException; + +public class MakeRam +{ + public static void main(String[] args) throws IOException + { + new MakeRam().run(args[0]); + } + + private void run(String string) throws IOException + { + FileInputStream file=new FileInputStream(string); + + int i=0; + while (file.available()>4) + { + byte[] tmp=new byte[4]; + file.read(tmp); + int word=0; + for (int j=0; j<4; j++) + { + word|=((int)(tmp[j])&0xff)<<((3-j)*8); + } + String str=Integer.toHexString(word); + while (str.length()<8) + { + str="0"+str; + } + + System.out.println("" + i + " => x\"" + str + "\","); + i++; + } + } + +} diff --git a/zpu/sw/simulator/com/zylin/zpu/stats/CountSequences.java b/zpu/sw/simulator/com/zylin/zpu/stats/CountSequences.java new file mode 100644 index 0000000..0f06aec --- /dev/null +++ b/zpu/sw/simulator/com/zylin/zpu/stats/CountSequences.java @@ -0,0 +1,94 @@ +/* + * Created on Jan 18, 2005 + * + * TODO To change the template for this generated file go to + * Window - Preferences - Java - Code Style - Code Templates + */ +package com.zylin.zpu.stats; + +import java.io.File; +import java.io.FileInputStream; +import java.io.FileNotFoundException; +import java.io.IOException; + +import com.zylin.zpu.simulator.Machine; + +public class CountSequences implements Machine +{ + + private byte[] array; + private StatKeeper statKeeper; + + public static void main(String[] args) + { + new CountSequences().run(args[0]); + } + + private void run(String string) + { + try + { + File file=new File(string); + if (file.exists()) + System.out.println("It exists!"); + FileInputStream in=new FileInputStream(file); + + try + { + array=new byte[(int) file.length()]; + + if (in.read(array)!=array.length) + throw new IOException(); + + countStats(); + + statKeeper.printStats(); + } finally + { + in.close(); + } + + } catch (FileNotFoundException e) + { + e.printStackTrace(); + } catch (IOException e) + { + e.printStackTrace(); + } + + + } + + + private void countStats() + { + statKeeper=new StatKeeper(this); + for (int i=0; i=64)&&(j<96)) +// { +// j=64; +// } else if ((j>=96)&&(j<128)) +// { +// j=96; +// } else if ((j>=128)&&(j<256)) +// { +// j=128; +// } + statKeeper.countInstruction(j); + } + + } + + public long getPrevCycles() + { + return 0; + } + + public long getCycles() + { + return 0; + } +} diff --git a/zpu/sw/simulator/com/zylin/zpu/stats/DumpIt.java b/zpu/sw/simulator/com/zylin/zpu/stats/DumpIt.java new file mode 100644 index 0000000..80be11d --- /dev/null +++ b/zpu/sw/simulator/com/zylin/zpu/stats/DumpIt.java @@ -0,0 +1,17 @@ +/* + * Created on 26.nov.2004 + * + * To change the template for this generated file go to + * Window - Preferences - Java - Code Generation - Code and Comments + */ +package com.zylin.zpu.stats; +/** + * @author oyvind + * + * To change the template for this generated type comment go to + * Window - Preferences - Java - Code Generation - Code and Comments + */ +public interface DumpIt +{ + int dumpIt(int i); +} \ No newline at end of file diff --git a/zpu/sw/simulator/com/zylin/zpu/stats/Instruction.java b/zpu/sw/simulator/com/zylin/zpu/stats/Instruction.java new file mode 100644 index 0000000..252dd7f --- /dev/null +++ b/zpu/sw/simulator/com/zylin/zpu/stats/Instruction.java @@ -0,0 +1,62 @@ +package com.zylin.zpu.stats; + +public class Instruction +{ + public class DumpCycles implements DumpIt + { + public int dumpIt(int i) + { + return insn[i].cycles; + } + } + + + + public Instruction[] insn=new Instruction[256]; + public int count; + public int cycles; + + public Instruction addInstruction(int i) + { + if (insn[i]==null) + { + insn[i]=new Instruction(); + } + return insn[i]; + } + + /** + * Recursive print of statistics + */ + public void printStats() + { + System.out.println("Count dump"); + DumpIt cDump = new DumpCount(); + printCount("", cDump); + } + + /** + * Recursive print of counts + * @param string + * @param dumpIt TODO + */ + private void printCount(String string, DumpIt dumpIt) + { + for (int i=0; i Date: Thu, 3 Jan 2008 09:30:16 +0000 Subject: clarify licensing a bit. --- zpu/COPYING | 11 ++++++++--- zpu/ChangeLog | 13 ++----------- 2 files changed, 10 insertions(+), 14 deletions(-) diff --git a/zpu/COPYING b/zpu/COPYING index 96b27d3..9475e0f 100644 --- a/zpu/COPYING +++ b/zpu/COPYING @@ -1,8 +1,7 @@ About ZPU licensing: -Licensing is not entirely fleshed out yet(there are many parts to a -soft CPU), but the license for the HDL will be BSD/eCos-like to be -friendly towards commercially oriented projects, however the +The license for HDL implementations is BSD to be +friendly towards commercial projects, however the architecture, documentation and tools will be GPL. This means that all updates to the architecture must be shared, but actual implementations(which are small and can be very project speific) can @@ -10,3 +9,9 @@ be friendly towards commercial considerations. Patches to update files w/correct licensing info will be most appreciated! + + +The ZPU and all the files are per 1/1-2008 Copyright Zylin AS, i.e. +Zylin is free to decide upon the BSD license for HDL implementation +and GPL for architecture, tools and documentation. + \ No newline at end of file diff --git a/zpu/ChangeLog b/zpu/ChangeLog index 827ede8..a468d8a 100644 --- a/zpu/ChangeLog +++ b/zpu/ChangeLog @@ -1,11 +1,2 @@ -2007-09-11 Øyvind Harboe - * Cleaning up zpu/hdl/example. simzpu.do file now uses zpu4/src files instead - of duplicating them. Hello world simzpu.do now works out of the box. -2007-09-10 Øyvind Harboe - * Cleaning up .html files a bit. - * retired zpututorial.odt. -2007-08-04 Øyvind Harboe - * small ZPU hello world example now simulates with valid log.txt/trace.txt file. - * Until files are properly organized, ChangeLog will not be kept up to date. -2007-08-03 Øyvind Harboe - * Starting to commit files +2008-01-02 Øyvind Harboe + * Moved to www.opencores.org -- cgit v1.1 From 86579431bc123532d3225d59d7c01c4fa7115969 Mon Sep 17 00:00:00 2001 From: oharboe Date: Mon, 11 Feb 2008 20:47:26 +0000 Subject: * hdl/index.html. Fixed typo. Use objcopy and not objdump. --- zpu/ChangeLog | 2 ++ zpu/hdl/index.html | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/zpu/ChangeLog b/zpu/ChangeLog index a468d8a..2921691 100644 --- a/zpu/ChangeLog +++ b/zpu/ChangeLog @@ -1,2 +1,4 @@ +2008-02-11 Øyvind Harboe + * hdl/index.html. Fixed typo. Use objcopy and not objdump. 2008-01-02 Øyvind Harboe * Moved to www.opencores.org diff --git a/zpu/hdl/index.html b/zpu/hdl/index.html index d3b4c1a..271d46a 100644 --- a/zpu/hdl/index.html +++ b/zpu/hdl/index.html @@ -15,7 +15,7 @@ Obviously you must also connect the ZPU to the rest of your IO subsystem. IO is

    Generating VHDL BRAM initialization

    -../install/bin/zpu-elf-objdump -O binary hello.elf hello.bin
    +../install/bin/zpu-elf-objcopy -O binary hello.elf hello.bin
    java -classpath ../simulator/zpusim.jar com.zylin.zpu.simulator.tools.MakeRam hello.bin >hello.bram
     -- cgit v1.1 From 4f2caa8713e198e5cc50339a6272c085ff9ad980 Mon Sep 17 00:00:00 2001 From: oharboe Date: Tue, 19 Feb 2008 18:12:28 +0000 Subject: peek & poke example. --- zpu/roadshow/roadshow/loop/looptest.c | 68 +++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 zpu/roadshow/roadshow/loop/looptest.c diff --git a/zpu/roadshow/roadshow/loop/looptest.c b/zpu/roadshow/roadshow/loop/looptest.c new file mode 100644 index 0000000..5ae197a --- /dev/null +++ b/zpu/roadshow/roadshow/loop/looptest.c @@ -0,0 +1,68 @@ +/* This is a peek & poke example for an FPGA. + + It should loop at a frequency of ~50 instructions. If + the ZPU(small) is running at 25MHz, then this would yield + a peek & poke every 8ms or so. + + zpu-elf-gcc -O3 -zeta looptest.c -o looptest.elf -Wl,--relax -Wl,--gc-sections */ + + +/* +0000051c
    : + 51c: ff im -1 + 51d: 3d pushspadd + 51e: 0d popsp + 51f: 80 im 0 + 520: 52 storesp 8 + +00000521 <.L2>: + 521: 81 im 1 + 522: 12 addsp 8 + 523: 82 im 2 + 524: 80 im 0 + 525: 80 im 0 + 526: 08 load + 527: 71 loadsp 4 + 528: 82 im 2 + 529: 80 im 0 + 52a: 90 im 16 + 52b: 0c store + 52c: 81 im 1 + 52d: 12 addsp 8 + 52e: 82 im 2 + 52f: 80 im 0 + 530: 80 im 0 + 531: 08 load + 532: 71 loadsp 4 + 533: 82 im 2 + 534: 80 im 0 + 535: 90 im 16 + 536: 0c store + 537: 52 storesp 8 + 538: 52 storesp 8 + 539: 52 storesp 8 + 53a: 52 storesp 8 + 53b: e5 im -27 + 53c: 39 poppcrel +*/ +#define FPGA_ADDR 0x8000 + +typedef volatile unsigned int* pAddr; +#define FPGA_READ *(pAddr) (FPGA_ADDR) + +#define FPGA_WRITE *(pAddr) (FPGA_ADDR + 16) + + +int main(int argc, char **argv) +{ +int i; +int j = 0; + + while (1) + + { + j++; + i = FPGA_READ; + FPGA_WRITE = j; + } +} -- cgit v1.1 From 4a419c5aa7ef974279042ebfba2aed2adab197db Mon Sep 17 00:00:00 2001 From: oharboe Date: Thu, 21 Feb 2008 18:59:45 +0000 Subject: * zpu/zpu/hdl/index.html. Sharpened instructions and shows two working examples. Small & medium ZPU. * got zpu4/src/simzpu_medium.do working again. --- zpu/ChangeLog | 4 + zpu/hdl/example/.cvsignore | 2 + zpu/hdl/example/helloworld.vhd | 15002 ++++++-------------------------- zpu/hdl/example/log.txt | 22 +- zpu/hdl/example/simzpu.do | 29 - zpu/hdl/example/simzpu_small.do | 29 + zpu/hdl/index.html | 7 +- zpu/hdl/zpu4/src/dram_hello.vhd | 5167 ++++++----- zpu/hdl/zpu4/src/fasthello.do | 19 + zpu/hdl/zpu4/src/io.vhd | 23 +- zpu/hdl/zpu4/src/log.txt | 139 +- zpu/hdl/zpu4/src/sim_fpga_top.vhd | 11 +- zpu/hdl/zpu4/src/simzpu.do | 23 - zpu/hdl/zpu4/src/simzpu_intstack.do | 23 - zpu/hdl/zpu4/src/simzpu_medium.do | 28 + zpu/hdl/zpu4/src/zpu_config_trace.vhd | 6 +- zpu/hdl/zpu4/src/zpu_core.vhd | 4 +- zpu/hdl/zpu4/src/zpu_core_small.vhd | 13 + zpu/hdl/zpu4/src/zpuio.vhd | 32 +- zpu/hdl/zpu4/src/zpupkg.vhd | 11 - zpu/hdl/zpu4/test/dmips/build.sh | 1 + zpu/hdl/zpu4/test/dmips/dmips.ram | 5969 ++++++------- zpu/hdl/zpu4/test/hello/build.sh | 3 +- zpu/hdl/zpu4/test/hello/hello.bin | Bin 12664 -> 12224 bytes zpu/hdl/zpu4/test/hello/hello.c | 8 +- zpu/hdl/zpu4/test/hello/hello.elf | Bin 150455 -> 150384 bytes zpu/hdl/zpu4/test/hello/hello.ram | 5150 ++++++----- 27 files changed, 11100 insertions(+), 20625 deletions(-) create mode 100644 zpu/hdl/example/.cvsignore delete mode 100644 zpu/hdl/example/simzpu.do create mode 100644 zpu/hdl/example/simzpu_small.do create mode 100644 zpu/hdl/zpu4/src/fasthello.do delete mode 100644 zpu/hdl/zpu4/src/simzpu.do delete mode 100644 zpu/hdl/zpu4/src/simzpu_intstack.do create mode 100644 zpu/hdl/zpu4/src/simzpu_medium.do diff --git a/zpu/ChangeLog b/zpu/ChangeLog index 2921691..9a6495b 100644 --- a/zpu/ChangeLog +++ b/zpu/ChangeLog @@ -1,3 +1,7 @@ +2008-02-21 Øyvind Harboe + * zpu/zpu/hdl/index.html. Sharpened instructions and shows two working + examples. Small & medium ZPU. + * got zpu4/src/simzpu_medium.do working again. 2008-02-11 Øyvind Harboe * hdl/index.html. Fixed typo. Use objcopy and not objdump. 2008-01-02 Øyvind Harboe diff --git a/zpu/hdl/example/.cvsignore b/zpu/hdl/example/.cvsignore new file mode 100644 index 0000000..ab4e67c --- /dev/null +++ b/zpu/hdl/example/.cvsignore @@ -0,0 +1,2 @@ +work +vsim.wlf diff --git a/zpu/hdl/example/helloworld.vhd b/zpu/hdl/example/helloworld.vhd index 9c99259..2e5ce4e 100644 --- a/zpu/hdl/example/helloworld.vhd +++ b/zpu/hdl/example/helloworld.vhd @@ -28,15 +28,15 @@ shared variable ram : ram_type := ( 0 => x"0b0b0b0b", 1 => x"82700b0b", -2 => x"82f4e00c", -3 => x"3a0b0b81", -4 => x"e48c0400", +2 => x"80cfd80c", +3 => x"3a0b0b80", +4 => x"c6d00400", 5 => x"00000000", 6 => x"00000000", 7 => x"00000000", 8 => x"80088408", 9 => x"88080b0b", -10 => x"81e4fd2d", +10 => x"80c7972d", 11 => x"880c840c", 12 => x"800c0400", 13 => x"00000000", @@ -99,7 +99,7 @@ shared variable ram : ram_type := 70 => x"00000000", 71 => x"00000000", 72 => x"0b0b0b88", -73 => x"c9040000", +73 => x"c4040000", 74 => x"00000000", 75 => x"00000000", 76 => x"00000000", @@ -116,7 +116,7 @@ shared variable ram : ram_type := 87 => x"00000000", 88 => x"72729f06", 89 => x"0981050b", -90 => x"0b0b88ac", +90 => x"0b0b88a7", 91 => x"05040000", 92 => x"00000000", 93 => x"00000000", @@ -187,25 +187,25 @@ shared variable ram : ram_type := 158 => x"00000000", 159 => x"00000000", 160 => x"71fc0608", -161 => x"0b0b82f4", -162 => x"cc738306", +161 => x"0b0b80cf", +162 => x"c4738306", 163 => x"10100508", 164 => x"060b0b0b", -165 => x"88af0400", +165 => x"88aa0400", 166 => x"00000000", 167 => x"00000000", 168 => x"80088408", 169 => x"88087575", -170 => x"0b0b0b8e", -171 => x"c42d5050", +170 => x"0b0b0b8b", +171 => x"9f2d5050", 172 => x"80085688", 173 => x"0c840c80", 174 => x"0c510400", 175 => x"00000000", 176 => x"80088408", 177 => x"88087575", -178 => x"0b0b0b90", -179 => x"8d2d5050", +178 => x"0b0b0b8b", +179 => x"e32d5050", 180 => x"80085688", 181 => x"0c840c80", 182 => x"0c510400", @@ -235,7 +235,7 @@ shared variable ram : ram_type := 206 => x"00000000", 207 => x"00000000", 208 => x"810b0b0b", -209 => x"82f4dc0c", +209 => x"80cfd40c", 210 => x"51040000", 211 => x"00000000", 212 => x"00000000", @@ -282,12191 +282,2805 @@ shared variable ram : ram_type := 253 => x"00000000", 254 => x"00000000", 255 => x"00000000", -256 => x"0b0b0b83", -257 => x"e93f0b0b", -258 => x"82e4cc3f", -259 => x"04101010", +256 => x"82c53f80", +257 => x"c6d93f04", +258 => x"10101010", +259 => x"10101010", 260 => x"10101010", 261 => x"10101010", 262 => x"10101010", 263 => x"10101010", 264 => x"10101010", -265 => x"10101010", -266 => x"10101010", -267 => x"53510473", -268 => x"81ff0673", -269 => x"83060981", -270 => x"05830510", -271 => x"10102b07", -272 => x"72fc060c", -273 => x"5151043c", -274 => x"04727280", -275 => x"728106ff", -276 => x"05097206", -277 => x"05711052", -278 => x"720a100a", -279 => x"5372ed38", -280 => x"51515351", -281 => x"04fe3d0d", -282 => x"0b0b8384", -283 => x"e8085384", -284 => x"13087088", -285 => x"2a708106", -286 => x"51525270", -287 => x"802e0b0b", -288 => x"0b0bec38", -289 => x"7181ff06", -290 => x"800c843d", -291 => x"0d04ff3d", -292 => x"0d0b0b83", -293 => x"84e80852", -294 => x"71087088", -295 => x"2a813270", -296 => x"81065151", -297 => x"51700b0b", -298 => x"0b0bed38", -299 => x"73720c83", -300 => x"3d0d040b", -301 => x"0b82f4dc", -302 => x"08802e0b", -303 => x"0b0b0bae", -304 => x"380b0b82", -305 => x"f4e00882", -306 => x"2e0b0b0b", -307 => x"80c53883", -308 => x"80800b0b", -309 => x"0b8384e8", -310 => x"0c82a080", -311 => x"0b0b0b83", -312 => x"84ec0c82", -313 => x"90800b0b", -314 => x"0b8384f0", -315 => x"0c04f880", -316 => x"8080a40b", -317 => x"0b0b8384", -318 => x"e80cf880", -319 => x"8082800b", -320 => x"0b0b8384", -321 => x"ec0cf880", -322 => x"8084800b", -323 => x"0b0b8384", -324 => x"f00c0480", -325 => x"c0a8808c", -326 => x"0b0b0b83", -327 => x"84e80c80", -328 => x"c0a88094", -329 => x"0b0b0b83", -330 => x"84ec0c0b", -331 => x"0b82ed90", -332 => x"0b0b0b83", -333 => x"84f00c04", -334 => x"f23d0d60", -335 => x"0b0b8384", -336 => x"ec08565d", -337 => x"82750c80", -338 => x"59805a80", -339 => x"0b8f3d5d", -340 => x"5b7a1010", -341 => x"15700871", -342 => x"08719f2c", -343 => x"7e852b58", -344 => x"55557d53", -345 => x"59570b0b", -346 => x"0b81d13f", -347 => x"7d7f7a72", -348 => x"077c7207", -349 => x"71716081", -350 => x"05415f5d", -351 => x"5b595755", -352 => x"817b270b", -353 => x"0b0b0b8f", -354 => x"38767d0c", -355 => x"77841e0c", -356 => x"7c800c90", -357 => x"3d0d040b", -358 => x"0b8384ec", -359 => x"08550b0b", -360 => x"0bffae39", -361 => x"70700b0b", -362 => x"8384f433", -363 => x"51700b0b", -364 => x"0b0bb738", -365 => x"0b0b82f4", -366 => x"e8087008", -367 => x"52527080", -368 => x"2e0b0b0b", -369 => x"0b9c3884", -370 => x"120b0b82", -371 => x"f4e80c70", -372 => x"2d0b0b82", -373 => x"f4e80870", -374 => x"08525270", -375 => x"0b0b0b0b", -376 => x"e638810b", -377 => x"0b0b8384", -378 => x"f4345050", -379 => x"0404700b", -380 => x"0b8384e4", -381 => x"08802e0b", -382 => x"0b0b0b92", -383 => x"380b0b0b", -384 => x"0b800b80", -385 => x"2e098106", -386 => x"0b0b0b0b", -387 => x"83385004", -388 => x"0b0b8384", -389 => x"e4510b0b", -390 => x"0bf3e53f", -391 => x"5004048c", -392 => x"08028c0c", -393 => x"ff3d0d0b", -394 => x"0b82ed94", -395 => x"510b0b0b", -396 => x"88ab3f71", -397 => x"800c833d", -398 => x"0d8c0c04", -399 => x"8c08028c", -400 => x"0cf53d0d", -401 => x"8c089405", -402 => x"080b0b0b", -403 => x"0ba0388c", -404 => x"088c0508", -405 => x"8c089005", -406 => x"088c0888", -407 => x"05085856", -408 => x"5473760c", -409 => x"7484170c", -410 => x"0b0b0b81", -411 => x"ca39800b", -412 => x"8c08f005", -413 => x"0c800b8c", -414 => x"08f4050c", -415 => x"8c088c05", -416 => x"088c0890", -417 => x"05085654", -418 => x"738c08f0", -419 => x"050c748c", -420 => x"08f4050c", -421 => x"8c08f805", -422 => x"8c08f005", -423 => x"56568870", -424 => x"54755376", -425 => x"52540b0b", -426 => x"0b85e03f", -427 => x"a00b8c08", -428 => x"94050831", -429 => x"8c08ec05", -430 => x"0c8c08ec", -431 => x"05088024", -432 => x"0b0b0b0b", -433 => x"a138800b", -434 => x"8c08f405", -435 => x"0c8c08ec", -436 => x"0508308c", -437 => x"08fc0508", -438 => x"712b8c08", -439 => x"f0050c54", -440 => x"0b0b0b0b", -441 => x"b9398c08", -442 => x"fc05088c", -443 => x"08ec0508", -444 => x"2a8c08e8", -445 => x"050c8c08", -446 => x"fc05088c", -447 => x"08940508", -448 => x"2b8c08f4", -449 => x"050c8c08", -450 => x"f805088c", -451 => x"08940508", -452 => x"2b708c08", -453 => x"e8050807", -454 => x"8c08f005", -455 => x"0c548c08", -456 => x"f005088c", -457 => x"08f40508", -458 => x"8c088805", -459 => x"08585654", -460 => x"73760c74", -461 => x"84170c8c", -462 => x"08880508", -463 => x"800c8d3d", -464 => x"0d8c0c04", -465 => x"8c08028c", -466 => x"0cf93d0d", -467 => x"800b8c08", -468 => x"fc050c8c", -469 => x"08880508", -470 => x"80250b0b", -471 => x"0b0baf38", -472 => x"8c088805", -473 => x"08308c08", -474 => x"88050c80", -475 => x"0b8c08f4", -476 => x"050c8c08", -477 => x"fc05080b", -478 => x"0b0b0b88", -479 => x"38810b8c", -480 => x"08f4050c", -481 => x"8c08f405", -482 => x"088c08fc", -483 => x"050c8c08", -484 => x"8c050880", -485 => x"250b0b0b", -486 => x"0baf388c", -487 => x"088c0508", -488 => x"308c088c", -489 => x"050c800b", -490 => x"8c08f005", -491 => x"0c8c08fc", -492 => x"05080b0b", -493 => x"0b0b8838", -494 => x"810b8c08", -495 => x"f0050c8c", -496 => x"08f00508", -497 => x"8c08fc05", -498 => x"0c80538c", -499 => x"088c0508", -500 => x"528c0888", -501 => x"0508510b", -502 => x"0b0b81bb", -503 => x"3f800870", -504 => x"8c08f805", -505 => x"0c548c08", -506 => x"fc050880", -507 => x"2e0b0b0b", -508 => x"0b8c388c", -509 => x"08f80508", -510 => x"308c08f8", -511 => x"050c8c08", -512 => x"f8050870", -513 => x"800c5489", -514 => x"3d0d8c0c", -515 => x"048c0802", -516 => x"8c0cfb3d", -517 => x"0d800b8c", -518 => x"08fc050c", -519 => x"8c088805", -520 => x"0880250b", -521 => x"0b0b0b93", -522 => x"388c0888", -523 => x"0508308c", -524 => x"0888050c", -525 => x"810b8c08", -526 => x"fc050c8c", -527 => x"088c0508", -528 => x"80250b0b", -529 => x"0b0b8c38", -530 => x"8c088c05", -531 => x"08308c08", -532 => x"8c050c81", -533 => x"538c088c", -534 => x"0508528c", -535 => x"08880508", -536 => x"510b0b0b", -537 => x"0bb13f80", -538 => x"08708c08", -539 => x"f8050c54", -540 => x"8c08fc05", -541 => x"08802e0b", -542 => x"0b0b0b8c", -543 => x"388c08f8", -544 => x"0508308c", -545 => x"08f8050c", -546 => x"8c08f805", -547 => x"0870800c", -548 => x"54873d0d", -549 => x"8c0c048c", -550 => x"08028c0c", -551 => x"70707070", -552 => x"810b8c08", -553 => x"fc050c80", -554 => x"0b8c08f8", -555 => x"050c8c08", -556 => x"8c05088c", -557 => x"08880508", -558 => x"270b0b0b", -559 => x"0bb8388c", -560 => x"08fc0508", -561 => x"802e0b0b", -562 => x"0b0bab38", -563 => x"800b8c08", -564 => x"8c050824", -565 => x"0b0b0b0b", -566 => x"9d388c08", -567 => x"8c050810", -568 => x"8c088c05", -569 => x"0c8c08fc", -570 => x"0508108c", -571 => x"08fc050c", -572 => x"0b0b0bff", -573 => x"b9398c08", -574 => x"fc050880", -575 => x"2e0b0b0b", -576 => x"80d0388c", -577 => x"088c0508", -578 => x"8c088805", -579 => x"08260b0b", -580 => x"0b0ba138", -581 => x"8c088805", -582 => x"088c088c", -583 => x"0508318c", -584 => x"0888050c", -585 => x"8c08f805", -586 => x"088c08fc", -587 => x"0508078c", -588 => x"08f8050c", -589 => x"8c08fc05", -590 => x"08812a8c", -591 => x"08fc050c", -592 => x"8c088c05", -593 => x"08812a8c", -594 => x"088c050c", -595 => x"0b0b0bff", -596 => x"a5398c08", -597 => x"90050880", -598 => x"2e0b0b0b", -599 => x"0b93388c", -600 => x"08880508", -601 => x"708c08f4", -602 => x"050c510b", -603 => x"0b0b0b8d", -604 => x"398c08f8", -605 => x"0508708c", -606 => x"08f4050c", -607 => x"518c08f4", -608 => x"0508800c", -609 => x"50505050", -610 => x"8c0c04fc", -611 => x"3d0d7670", -612 => x"797b5555", -613 => x"55558f72", -614 => x"270b0b0b", -615 => x"0b903872", -616 => x"75078306", -617 => x"5170802e", -618 => x"0b0b0b0b", -619 => x"af38ff12", -620 => x"5271ff2e", -621 => x"0b0b0b0b", -622 => x"9c387270", -623 => x"81055433", -624 => x"74708105", -625 => x"5634ff12", -626 => x"5271ff2e", -627 => x"0981060b", -628 => x"0b0b0be6", -629 => x"3874800c", -630 => x"863d0d04", -631 => x"74517270", -632 => x"84055408", -633 => x"71708405", -634 => x"530c7270", -635 => x"84055408", -636 => x"71708405", -637 => x"530c7270", -638 => x"84055408", -639 => x"71708405", -640 => x"530c7270", -641 => x"84055408", -642 => x"71708405", -643 => x"530cf012", -644 => x"52718f26", -645 => x"0b0b0b0b", -646 => x"c5388372", -647 => x"270b0b0b", -648 => x"0b993872", -649 => x"70840554", -650 => x"08717084", -651 => x"05530cfc", -652 => x"12527183", -653 => x"260b0b0b", -654 => x"0be93870", -655 => x"540b0b0b", -656 => x"feec39fb", -657 => x"3d0d7789", -658 => x"3d880555", -659 => x"79548811", -660 => x"0853510b", -661 => x"0b0b80e3", -662 => x"3f873d0d", -663 => x"04fc3d0d", -664 => x"873d7070", -665 => x"84055208", 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x"00002da8", +2925 => x"00002da8", +2926 => x"00002db0", +2927 => x"00002db0", +2928 => x"00002db8", +2929 => x"00002db8", +2930 => x"00002dc0", +2931 => x"00002dc0", +2932 => x"00002dc8", +2933 => x"00002dc8", +2934 => x"00002dd0", +2935 => x"00002dd0", +2936 => x"00002dd8", +2937 => x"00002dd8", +2938 => x"00002de0", +2939 => x"00002de0", +2940 => x"00002de8", +2941 => x"00002de8", +2942 => x"00002df0", +2943 => x"00002df0", +2944 => x"00002df8", +2945 => x"00002df8", +2946 => x"00002e00", +2947 => x"00002e00", +2948 => x"00002e08", +2949 => x"00002e08", +2950 => x"00002e10", +2951 => x"00002e10", +2952 => x"00002e18", +2953 => x"00002e18", +2954 => x"00002e20", +2955 => x"00002e20", +2956 => x"00002e28", +2957 => x"00002e28", +2958 => x"00002e30", +2959 => x"00002e30", +2960 => x"00002e38", +2961 => x"00002e38", +2962 => x"00002e40", +2963 => x"00002e40", +2964 => x"00002e48", +2965 => x"00002e48", +2966 => x"00002e50", +2967 => x"00002e50", +2968 => x"00002e58", +2969 => x"00002e58", +2970 => x"00002e60", +2971 => x"00002e60", +2972 => x"00002e68", +2973 => x"00002e68", +2974 => x"00002e70", +2975 => x"00002e70", +2976 => x"00002e78", +2977 => x"00002e78", +2978 => x"00002e80", +2979 => x"00002e80", +2980 => x"00002e88", +2981 => x"00002e88", +2982 => x"00002e90", +2983 => x"00002e90", +2984 => x"00002e98", +2985 => x"00002e98", +2986 => x"00002ea0", +2987 => x"00002ea0", +2988 => x"00002ea8", +2989 => x"00002ea8", +2990 => x"00002eb0", +2991 => x"00002eb0", +2992 => x"00002eb8", +2993 => x"00002eb8", +2994 => x"00002ec0", +2995 => x"00002ec0", +2996 => x"00002ec8", +2997 => x"00002ec8", +2998 => x"00002ed0", +2999 => x"00002ed0", +3000 => x"00002ed8", +3001 => x"00002ed8", +3002 => x"00002ee0", +3003 => x"00002ee0", +3004 => x"00002ee8", +3005 => x"00002ee8", +3006 => x"00002ef0", +3007 => x"00002ef0", +3008 => x"00002ef8", +3009 => x"00002ef8", +3010 => x"00002f00", +3011 => x"00002f00", +3012 => x"00002f08", +3013 => x"00002f08", +3014 => x"00002f10", +3015 => x"00002f10", +3016 => x"00002f18", +3017 => x"00002f18", +3018 => x"00002f20", +3019 => x"00002f20", +3020 => x"00002f28", +3021 => x"00002f28", +3022 => x"00002f30", +3023 => x"00002f30", +3024 => x"00002f38", +3025 => x"00002f38", +3026 => x"00002f40", +3027 => x"00002f40", +3028 => x"00002f48", +3029 => x"00002f48", +3030 => x"00002f50", +3031 => x"00002f50", +3032 => x"00002f58", +3033 => x"00002f58", +3034 => x"00002f60", +3035 => x"00002f60", +3036 => x"00002f68", +3037 => x"00002f68", +3038 => x"00002f70", +3039 => x"00002f70", +3040 => x"00002f78", +3041 => x"00002f78", +3042 => x"00002f80", +3043 => x"00002f80", +3044 => x"00002f88", +3045 => x"00002f88", +3046 => x"00002f90", +3047 => x"00002f90", +3048 => x"00002f98", +3049 => x"00002f98", +3050 => x"000027b8", +3051 => x"ffffffff", +3052 => x"00000000", +3053 => x"ffffffff", +3054 => x"00000000", others => x"00000000" ); diff --git a/zpu/hdl/example/log.txt b/zpu/hdl/example/log.txt index 6954a81..6966062 100644 --- a/zpu/hdl/example/log.txt +++ b/zpu/hdl/example/log.txt @@ -9,7 +9,27 @@ o r l d -! + +1 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +2 diff --git a/zpu/hdl/example/simzpu.do b/zpu/hdl/example/simzpu.do deleted file mode 100644 index 083187f..0000000 --- a/zpu/hdl/example/simzpu.do +++ /dev/null @@ -1,29 +0,0 @@ -# Xilinx WebPack modelsim script -# -# 1. Change directory to this source directory -# cd C:/workspace/zpunew/hdl/example -# "do zimzpu.do" - -set BreakOnAssertion 1 -vlib work - -vcom -93 -explicit zpu_config.vhd -vcom -93 -explicit ../zpu4/src/zpupkg.vhd -vcom -93 -explicit ../zpu4/src/txt_util.vhd -vcom -93 -explicit sim_fpga_top.vhd -vcom -93 -explicit ../zpu4/src/zpu_core_small.vhd -vcom -93 -explicit helloworld.vhd -vcom -93 -explicit ../zpu4/src/timer.vhd -vcom -93 -explicit io.vhd -vcom -93 -explicit ../zpu4/src/trace.vhd - -# run ZPU -vsim fpga_top -view wave -add wave -recursive fpga_top/zpu/* -#add wave -recursive fpga_top/* -view structure -#view signals - -# Enough to run tiny programs -run 10 ms diff --git a/zpu/hdl/example/simzpu_small.do b/zpu/hdl/example/simzpu_small.do new file mode 100644 index 0000000..5fb906d --- /dev/null +++ b/zpu/hdl/example/simzpu_small.do @@ -0,0 +1,29 @@ +# Xilinx WebPack modelsim script +# +# +# cd C:/workspace/zpu/zpu/hdl/example +# do simzpu_small.do + +set BreakOnAssertion 1 +vlib work + +vcom -93 -explicit zpu_config.vhd +vcom -93 -explicit ../zpu4/src/zpupkg.vhd +vcom -93 -explicit ../zpu4/src/txt_util.vhd +vcom -93 -explicit sim_fpga_top.vhd +vcom -93 -explicit ../zpu4/src/zpu_core_small.vhd +vcom -93 -explicit helloworld.vhd +vcom -93 -explicit ../zpu4/src/timer.vhd +vcom -93 -explicit io.vhd +vcom -93 -explicit ../zpu4/src/trace.vhd + +# run ZPU +vsim fpga_top +view wave +add wave -recursive fpga_top/zpu/* +#add wave -recursive fpga_top/* +view structure +#view signals + +# Enough to run tiny programs +run 10 ms diff --git a/zpu/hdl/index.html b/zpu/hdl/index.html index 271d46a..d5bc256 100644 --- a/zpu/hdl/index.html +++ b/zpu/hdl/index.html @@ -4,7 +4,8 @@ The simplest version of the ZPU uses BRAM. When getting accustomed to the ZPU, a BRAM ZPU with a UART is a good place to start.

    -You'll find a working simulation script in hdl/example/simzpu.do. +You'll find a working simulation script in hdl/example/simzpu_small.do and hdl/zpu4/src/simzpu_medium.do, which +show simulation of the small(zpu_core_small.vhd) and medium sized ZPU(zpu_core.vhd).

    When implementing the ZPU, copy the following files and modify them to your needs:

      @@ -23,10 +24,10 @@ java -classpath ../simulator/zpusim.jar com.zylin.zpu.simulator.tools.MakeRam he The hdl/example directory has a simulation written for Xilinx WebPack ModelSim. From the ModelSim command prompt:
      1. cd c:/<installfolder>/hdl/example -
      2. do zpusim.do +
      3. do zpusim_small.do

      -After running the hello world simulation (see zpusim.do), two files are written to the hdl/exmaple directory: +After running the hello world simulation (see zpusim.do), two files are written to the hdl/example directory:

      1. log.txt - contains the "Hello world!" text written to the debug channel/simplified UART.
      2. trace.txt - a trace file for the CPU. The instruction set simulator has the capability of taking diff --git a/zpu/hdl/zpu4/src/dram_hello.vhd b/zpu/hdl/zpu4/src/dram_hello.vhd index dc46dbb..3f7788a 100644 --- a/zpu/hdl/zpu4/src/dram_hello.vhd +++ b/zpu/hdl/zpu4/src/dram_hello.vhd @@ -9,6 +9,7 @@ use work.zpupkg.all; entity dram is port (clk : in std_logic; +areset : std_logic; mem_writeEnable : in std_logic; mem_readEnable : in std_logic; mem_addr : in std_logic_vector(maxAddrBit downto 0); @@ -21,21 +22,21 @@ end dram; architecture dram_arch of dram is -type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); +type ram_type is array(0 to ((2**(maxAddrBitDRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); shared variable ram : ram_type := ( 0 => x"0b0b0b0b", -1 => x"80700b0b", -2 => x"80d3900c", +1 => x"82700b0b", +2 => x"80cfd80c", 3 => x"3a0b0b80", -4 => x"c8b20400", +4 => x"c6d00400", 5 => x"00000000", 6 => x"00000000", 7 => x"00000000", 8 => x"80088408", 9 => x"88080b0b", -10 => x"80c8fb2d", +10 => x"80c7972d", 11 => x"880c840c", 12 => x"800c0400", 13 => x"00000000", @@ -186,8 +187,8 @@ shared variable ram : ram_type := 158 => x"00000000", 159 => x"00000000", 160 => x"71fc0608", -161 => x"0b0b80d2", -162 => x"fc738306", +161 => x"0b0b80cf", +162 => x"c4738306", 163 => x"10100508", 164 => x"060b0b0b", 165 => x"88aa0400", @@ -195,16 +196,16 @@ shared variable ram : ram_type := 167 => x"00000000", 168 => x"80088408", 169 => x"88087575", -170 => x"0b0b0b8d", -171 => x"872d5050", +170 => x"0b0b0b8b", +171 => x"9f2d5050", 172 => x"80085688", 173 => x"0c840c80", 174 => x"0c510400", 175 => x"00000000", 176 => x"80088408", 177 => x"88087575", -178 => x"0b0b0b8d", -179 => x"cb2d5050", +178 => x"0b0b0b8b", +179 => x"e32d5050", 180 => x"80085688", 181 => x"0c840c80", 182 => x"0c510400", @@ -234,7 +235,7 @@ shared variable ram : ram_type := 206 => x"00000000", 207 => x"00000000", 208 => x"810b0b0b", -209 => x"80d38c0c", +209 => x"80cfd40c", 210 => x"51040000", 211 => x"00000000", 212 => x"00000000", @@ -281,8 +282,8 @@ shared variable ram : ram_type := 253 => x"00000000", 254 => x"00000000", 255 => x"00000000", -256 => x"83d93f80", -257 => x"ca953f04", +256 => x"82c53f80", +257 => x"c6d93f04", 258 => x"10101010", 259 => x"10101010", 260 => x"10101010", @@ -305,2394 +306,2394 @@ shared variable ram : ram_type := 277 => x"0a100a53", 278 => x"72ed3851", 279 => x"51535104", -280 => x"ff3d0d0b", -281 => x"0b80e2f8", -282 => x"08528412", -283 => x"08708106", -284 => x"515170f6", -285 => x"38710881", -286 => x"ff06800c", -287 => x"833d0d04", -288 => x"ff3d0d0b", -289 => x"0b80e2f8", -290 => x"08528412", -291 => x"08700a10", -292 => x"0a708106", -293 => x"51515170", -294 => x"f1387372", -295 => x"0c833d0d", -296 => x"0480d38c", -297 => x"08802ea8", -298 => x"38838080", -299 => x"0b0b0b80", -300 => x"e2f80c82", -301 => x"a0800b0b", -302 => x"0b80e2fc", -303 => x"0c829080", -304 => x"0b80e38c", -305 => x"0c0b0b80", -306 => x"e3800b80", -307 => x"e3900c04", -308 => x"f8808080", -309 => x"a40b0b0b", -310 => x"80e2f80c", -311 => x"f8808082", -312 => x"800b0b0b", -313 => x"80e2fc0c", -314 => x"f8808084", -315 => x"800b80e3", -316 => x"8c0cf880", -317 => x"8080940b", -318 => x"80e3900c", -319 => x"f8808080", -320 => x"9c0b80e3", -321 => x"880cf880", -322 => x"8080a00b", -323 => x"80e3940c", -324 => x"04f23d0d", -325 => x"600b0b80", -326 => x"e2fc0856", -327 => x"5d82750c", -328 => x"8059805a", -329 => x"800b8f3d", -330 => x"71101017", -331 => x"70085957", -332 => x"5d5b8076", -333 => x"81ff067c", -334 => x"832b5658", -335 => x"5276537b", -336 => x"5181fa3f", -337 => x"7d7f7a72", -338 => x"077c7207", -339 => x"71716081", -340 => x"05415f5d", -341 => x"5b595755", -342 => x"7a8724bb", -343 => x"380b0b80", -344 => x"e2fc087b", -345 => x"10101170", -346 => x"08585155", -347 => x"807681ff", -348 => x"067c832b", -349 => x"56585276", -350 => x"537b5181", -351 => x"c03f7d7f", -352 => x"7a72077c", -353 => x"72077171", -354 => x"60810541", -355 => x"5f5d5b59", -356 => x"5755877b", -357 => x"25c73876", -358 => x"7d0c7784", -359 => x"1e0c7c80", -360 => x"0c903d0d", -361 => x"04ff3d0d", -362 => x"80e38433", -363 => x"5170a738", -364 => x"80d39808", -365 => x"70085252", -366 => x"70802e94", -367 => x"38841280", -368 => x"d3980c70", -369 => x"2d80d398", -370 => x"08700852", -371 => x"5270ee38", -372 => x"810b80e3", -373 => x"8434833d", -374 => x"0d040480", -375 => x"3d0d0b0b", -376 => x"80e2f408", -377 => x"802e8e38", -378 => x"0b0b0b0b", -379 => x"800b802e", -380 => x"09810685", -381 => x"38823d0d", -382 => x"040b0b80", -383 => x"e2f4510b", -384 => x"0b0bf3fc", -385 => x"3f823d0d", -386 => x"0404fe3d", -387 => x"0d89530b", -388 => x"0b80d2c8", -389 => x"51838d3f", -390 => x"0b0b80d2", -391 => x"d8518384", -392 => x"3f810a0b", -393 => x"80e3980c", -394 => x"ff0b80e3", -395 => x"9c0cff13", -396 => x"53728025", -397 => x"da387280", -398 => x"0c843d0d", -399 => x"04f93d0d", -400 => x"797b7d7f", -401 => x"56545254", -402 => x"72802ea0", -403 => x"38705771", -404 => x"58a07331", -405 => x"52807225", -406 => x"a1387770", -407 => x"742b5770", -408 => x"732a7875", -409 => x"2b075651", -410 => x"74765351", -411 => x"70740c71", -412 => x"84150c73", -413 => x"800c893d", -414 => x"0d048056", -415 => x"7772302b", -416 => x"55747653", -417 => x"51e639fb", -418 => x"3d0d7779", -419 => x"55558056", -420 => x"757524ab", -421 => x"38807424", -422 => x"9d388053", -423 => x"73527451", -424 => x"80e13f80", -425 => x"08547580", -426 => x"2e853880", -427 => x"08305473", -428 => x"800c873d", -429 => x"0d047330", -430 => x"76813257", -431 => x"54dc3974", -432 => x"30558156", -433 => x"738025d2", -434 => x"38ec39fa", -435 => x"3d0d787a", -436 => x"57558057", -437 => x"767524a4", -438 => x"38759f2c", -439 => x"54815375", -440 => x"74327431", -441 => x"5274519b", -442 => x"3f800854", -443 => x"76802e85", -444 => x"38800830", -445 => x"5473800c", -446 => x"883d0d04", -447 => x"74305581", -448 => x"57d739fc", -449 => x"3d0d7678", -450 => x"53548153", -451 => x"80747326", -452 => x"52557280", -453 => x"2e983870", -454 => x"802eab38", -455 => x"807224a6", -456 => x"38711073", -457 => x"10757226", -458 => x"53545272", -459 => x"ea387351", -460 => x"78833874", -461 => x"5170800c", -462 => x"863d0d04", -463 => x"720a100a", -464 => x"720a100a", -465 => x"53537280", -466 => x"2ee43871", -467 => x"7426ed38", -468 => x"73723175", -469 => x"7407740a", -470 => x"100a740a", -471 => x"100a5555", -472 => x"5654e339", -473 => x"f73d0d7c", -474 => x"70525380", -475 => x"f93f7254", -476 => x"80085580", -477 => x"d2e85681", -478 => x"57800881", -479 => x"055a8b3d", -480 => x"e4115953", -481 => x"8259f413", -482 => x"527b8811", -483 => x"08525381", -484 => x"b03f8008", -485 => x"30708008", -486 => x"079f2c8a", -487 => x"07800c53", -488 => x"8b3d0d04", -489 => x"f63d0d7c", -490 => x"80d39c08", -491 => x"71535553", -492 => x"b53f7255", -493 => x"80085680", -494 => x"d2e85781", -495 => x"58800881", -496 => x"055b8c3d", -497 => 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x"00000000", +2639 => x"00000000", +2640 => x"00000000", +2641 => x"00000000", +2642 => x"00000000", +2643 => x"00000000", +2644 => x"00000000", +2645 => x"00000000", +2646 => x"00000000", +2647 => x"00000000", +2648 => x"00000000", +2649 => x"00000000", +2650 => x"00000000", +2651 => x"00000000", +2652 => x"00000000", +2653 => x"00000000", +2654 => x"00000000", +2655 => x"00000000", +2656 => x"00000000", +2657 => x"00000000", +2658 => x"00000000", 2659 => x"00000000", 2660 => x"00000000", 2661 => x"00000000", -2662 => x"00003170", -2663 => x"000029a0", +2662 => x"00000000", +2663 => x"00000000", 2664 => x"00000000", -2665 => x"00002c08", -2666 => x"00002c64", -2667 => x"00002cc0", +2665 => x"00000000", +2666 => x"00000000", +2667 => x"00000000", 2668 => x"00000000", 2669 => x"00000000", 2670 => x"00000000", @@ -2702,7 +2703,7 @@ shared variable ram : ram_type := 2674 => x"00000000", 2675 => x"00000000", 2676 => x"00000000", -2677 => x"0000296c", +2677 => x"00000000", 2678 => x"00000000", 2679 => x"00000000", 2680 => x"00000000", @@ -2731,11 +2732,11 @@ shared variable ram : ram_type := 2703 => x"00000000", 2704 => x"00000000", 2705 => x"00000000", -2706 => x"00000001", -2707 => x"330eabcd", -2708 => x"1234e66d", -2709 => x"deec0005", -2710 => x"000b0000", +2706 => x"00000000", +2707 => x"00000000", +2708 => x"00000000", +2709 => x"00000000", +2710 => x"00000000", 2711 => x"00000000", 2712 => x"00000000", 2713 => x"00000000", @@ -2814,121 +2815,121 @@ shared variable ram : ram_type := 2786 => x"00000000", 2787 => x"00000000", 2788 => x"00000000", -2789 => x"00000000", +2789 => x"ffffffff", 2790 => x"00000000", -2791 => x"00000000", +2791 => x"00020000", 2792 => x"00000000", 2793 => x"00000000", -2794 => x"00000000", -2795 => x"00000000", -2796 => x"00000000", -2797 => x"00000000", -2798 => x"00000000", -2799 => x"00000000", -2800 => x"00000000", -2801 => x"00000000", -2802 => x"00000000", -2803 => x"00000000", -2804 => x"00000000", -2805 => x"00000000", -2806 => x"00000000", -2807 => x"00000000", -2808 => x"00000000", -2809 => x"00000000", -2810 => x"00000000", -2811 => x"00000000", -2812 => x"00000000", -2813 => x"00000000", -2814 => x"00000000", -2815 => x"00000000", -2816 => x"00000000", -2817 => x"00000000", -2818 => x"00000000", -2819 => x"00000000", -2820 => x"00000000", -2821 => x"00000000", -2822 => x"00000000", -2823 => x"00000000", -2824 => x"00000000", -2825 => x"00000000", -2826 => x"00000000", -2827 => x"00000000", -2828 => x"00000000", -2829 => x"00000000", -2830 => x"00000000", -2831 => x"00000000", -2832 => x"00000000", -2833 => x"00000000", -2834 => x"00000000", -2835 => x"00000000", -2836 => x"00000000", -2837 => x"00000000", -2838 => x"00000000", -2839 => x"00000000", -2840 => x"00000000", -2841 => x"00000000", -2842 => x"00000000", -2843 => x"00000000", -2844 => x"00000000", -2845 => x"00000000", -2846 => x"00000000", -2847 => x"00000000", -2848 => x"00000000", -2849 => x"00000000", -2850 => x"00000000", -2851 => x"00000000", -2852 => x"00000000", -2853 => x"00000000", -2854 => x"00000000", -2855 => x"00000000", -2856 => x"00000000", -2857 => x"00000000", -2858 => x"00000000", -2859 => x"00000000", -2860 => x"00000000", -2861 => x"00000000", -2862 => x"00000000", -2863 => x"00000000", -2864 => x"00000000", -2865 => x"00000000", -2866 => x"00000000", -2867 => x"00000000", -2868 => x"00000000", -2869 => x"00000000", -2870 => x"00000000", -2871 => x"00000000", -2872 => x"00000000", -2873 => x"00000000", -2874 => x"00000000", -2875 => x"00000000", -2876 => x"00000000", -2877 => x"00000000", -2878 => x"00000000", -2879 => x"00000000", -2880 => x"00000000", -2881 => x"00000000", -2882 => x"00000000", -2883 => x"00000000", -2884 => x"00000000", -2885 => x"00000000", -2886 => x"00000000", -2887 => x"00000000", -2888 => x"00000000", -2889 => x"00000000", -2890 => x"00000000", -2891 => x"00000000", -2892 => x"00000000", -2893 => x"00000000", -2894 => x"00000000", -2895 => x"00000000", -2896 => x"00000000", -2897 => x"00000000", -2898 => x"00000000", -2899 => x"ffffffff", -2900 => x"00000000", -2901 => x"00020000", -2902 => x"00000000", -2903 => x"00000000", +2794 => x"00002ba0", +2795 => x"00002ba0", +2796 => x"00002ba8", +2797 => x"00002ba8", +2798 => x"00002bb0", +2799 => x"00002bb0", +2800 => x"00002bb8", +2801 => x"00002bb8", +2802 => x"00002bc0", +2803 => x"00002bc0", +2804 => x"00002bc8", +2805 => x"00002bc8", +2806 => x"00002bd0", +2807 => x"00002bd0", +2808 => x"00002bd8", +2809 => x"00002bd8", +2810 => x"00002be0", +2811 => x"00002be0", +2812 => x"00002be8", +2813 => x"00002be8", +2814 => x"00002bf0", +2815 => x"00002bf0", +2816 => x"00002bf8", +2817 => x"00002bf8", +2818 => x"00002c00", +2819 => x"00002c00", +2820 => x"00002c08", +2821 => x"00002c08", +2822 => x"00002c10", +2823 => x"00002c10", +2824 => x"00002c18", +2825 => x"00002c18", +2826 => x"00002c20", +2827 => x"00002c20", +2828 => x"00002c28", +2829 => x"00002c28", +2830 => x"00002c30", +2831 => x"00002c30", +2832 => x"00002c38", +2833 => x"00002c38", +2834 => x"00002c40", +2835 => x"00002c40", +2836 => x"00002c48", +2837 => x"00002c48", +2838 => x"00002c50", +2839 => x"00002c50", +2840 => x"00002c58", +2841 => x"00002c58", +2842 => x"00002c60", +2843 => x"00002c60", +2844 => x"00002c68", +2845 => x"00002c68", +2846 => x"00002c70", +2847 => x"00002c70", +2848 => x"00002c78", +2849 => x"00002c78", +2850 => x"00002c80", +2851 => x"00002c80", +2852 => x"00002c88", +2853 => x"00002c88", +2854 => x"00002c90", +2855 => x"00002c90", +2856 => x"00002c98", +2857 => x"00002c98", +2858 => x"00002ca0", +2859 => x"00002ca0", +2860 => x"00002ca8", +2861 => x"00002ca8", +2862 => x"00002cb0", +2863 => x"00002cb0", +2864 => x"00002cb8", +2865 => x"00002cb8", +2866 => x"00002cc0", +2867 => x"00002cc0", +2868 => x"00002cc8", +2869 => x"00002cc8", +2870 => x"00002cd0", +2871 => x"00002cd0", +2872 => x"00002cd8", +2873 => x"00002cd8", +2874 => x"00002ce0", +2875 => x"00002ce0", +2876 => x"00002ce8", +2877 => x"00002ce8", +2878 => x"00002cf0", +2879 => x"00002cf0", +2880 => x"00002cf8", +2881 => x"00002cf8", +2882 => x"00002d00", +2883 => x"00002d00", +2884 => x"00002d08", +2885 => x"00002d08", +2886 => x"00002d10", +2887 => x"00002d10", +2888 => x"00002d18", +2889 => x"00002d18", +2890 => x"00002d20", +2891 => x"00002d20", +2892 => x"00002d28", +2893 => x"00002d28", +2894 => x"00002d30", +2895 => x"00002d30", +2896 => x"00002d38", +2897 => x"00002d38", +2898 => x"00002d40", +2899 => x"00002d40", +2900 => x"00002d48", +2901 => x"00002d48", +2902 => x"00002d50", +2903 => x"00002d50", 2904 => x"00002d58", 2905 => x"00002d58", 2906 => x"00002d60", @@ -3075,133 +3076,25 @@ shared variable ram : ram_type := 3047 => x"00002f90", 3048 => x"00002f98", 3049 => x"00002f98", -3050 => x"00002fa0", -3051 => x"00002fa0", -3052 => x"00002fa8", -3053 => x"00002fa8", -3054 => x"00002fb0", -3055 => x"00002fb0", -3056 => x"00002fb8", -3057 => x"00002fb8", -3058 => x"00002fc0", -3059 => x"00002fc0", -3060 => x"00002fc8", -3061 => x"00002fc8", -3062 => x"00002fd0", -3063 => x"00002fd0", -3064 => x"00002fd8", -3065 => x"00002fd8", -3066 => x"00002fe0", -3067 => x"00002fe0", -3068 => x"00002fe8", -3069 => x"00002fe8", -3070 => x"00002ff0", -3071 => x"00002ff0", -3072 => x"00002ff8", -3073 => x"00002ff8", -3074 => x"00003000", -3075 => x"00003000", -3076 => x"00003008", -3077 => x"00003008", -3078 => x"00003010", -3079 => x"00003010", -3080 => x"00003018", -3081 => x"00003018", -3082 => x"00003020", -3083 => x"00003020", -3084 => x"00003028", -3085 => x"00003028", -3086 => x"00003030", -3087 => x"00003030", -3088 => x"00003038", -3089 => x"00003038", -3090 => x"00003040", -3091 => x"00003040", -3092 => x"00003048", -3093 => x"00003048", -3094 => x"00003050", -3095 => x"00003050", -3096 => x"00003058", -3097 => x"00003058", -3098 => x"00003060", -3099 => x"00003060", -3100 => x"00003068", -3101 => x"00003068", -3102 => x"00003070", -3103 => x"00003070", -3104 => x"00003078", -3105 => x"00003078", -3106 => x"00003080", -3107 => x"00003080", -3108 => x"00003088", -3109 => x"00003088", -3110 => x"00003090", -3111 => x"00003090", -3112 => x"00003098", -3113 => x"00003098", -3114 => x"000030a0", -3115 => x"000030a0", -3116 => x"000030a8", -3117 => x"000030a8", -3118 => x"000030b0", -3119 => x"000030b0", -3120 => x"000030b8", -3121 => x"000030b8", -3122 => x"000030c0", -3123 => x"000030c0", -3124 => x"000030c8", -3125 => x"000030c8", -3126 => x"000030d0", -3127 => x"000030d0", -3128 => x"000030d8", -3129 => x"000030d8", -3130 => x"000030e0", -3131 => x"000030e0", -3132 => x"000030e8", -3133 => x"000030e8", -3134 => x"000030f0", -3135 => x"000030f0", -3136 => x"000030f8", -3137 => x"000030f8", -3138 => x"00003100", -3139 => x"00003100", -3140 => x"00003108", -3141 => x"00003108", -3142 => x"00003110", -3143 => x"00003110", -3144 => x"00003118", -3145 => x"00003118", -3146 => x"00003120", -3147 => x"00003120", -3148 => x"00003128", -3149 => x"00003128", -3150 => x"00003130", -3151 => x"00003130", -3152 => x"00003138", -3153 => x"00003138", -3154 => x"00003140", -3155 => x"00003140", -3156 => x"00003148", -3157 => x"00003148", -3158 => x"00003150", -3159 => x"00003150", -3160 => x"00002970", -3161 => x"ffffffff", -3162 => x"00000000", -3163 => x"ffffffff", -3164 => x"00000000", +3050 => x"000027b8", +3051 => x"ffffffff", +3052 => x"00000000", +3053 => x"ffffffff", +3054 => x"00000000", others => x"00000000" ); begin -process (clk) +mem_busy<=mem_readEnable; -- we're done on the cycle after we serve the read request + +process (clk, areset) begin - if (clk'event and clk = '1') then - mem_busy<=mem_writeEnable or mem_readEnable; - if (mem_writeEnable = '1') then - ram(conv_integer(mem_addr(maxAddrBit downto minAddrBit))) := mem_write; - end if; + if areset = '1' then + elsif (clk'event and clk = '1') then + if (mem_writeEnable = '1') then + ram(conv_integer(mem_addr(maxAddrBit downto minAddrBit))) := mem_write; + end if; if (mem_readEnable = '1') then mem_read <= ram(conv_integer(mem_addr(maxAddrBit downto minAddrBit))); end if; diff --git a/zpu/hdl/zpu4/src/fasthello.do b/zpu/hdl/zpu4/src/fasthello.do new file mode 100644 index 0000000..d49aeab --- /dev/null +++ b/zpu/hdl/zpu4/src/fasthello.do @@ -0,0 +1,19 @@ +set BreakOnAssertion 1 +vlib work + +vcom -93 -explicit zpu_config_fastsim.vhd +vcom -93 -explicit zpupkg.vhd +vcom -93 -explicit txt_util.vhd +vcom -93 -explicit sim_fpga_top.vhd +vcom -93 -explicit zpu_core.vhd +vcom -93 -explicit dram_hello.vhd +vcom -93 -explicit timer.vhd +vcom -93 -explicit io.vhd +vcom -93 -explicit trace.vhd + + +vsim fpga_top +view wave + +# run ZPU +run 60000 ms diff --git a/zpu/hdl/zpu4/src/io.vhd b/zpu/hdl/zpu4/src/io.vhd index b5465d1..7dbe36f 100644 --- a/zpu/hdl/zpu4/src/io.vhd +++ b/zpu/hdl/zpu4/src/io.vhd @@ -19,8 +19,8 @@ entity zpu_io is busy : out std_logic; writeEnable : in std_logic; readEnable : in std_logic; - write : in std_logic_vector(7 downto 0); - read : out std_logic_vector(7 downto 0); + write : in std_logic_vector(wordSize-1 downto 0); + read : out std_logic_vector(wordSize-1 downto 0); addr : in std_logic_vector(maxAddrBit downto minAddrBit) ); end zpu_io; @@ -45,7 +45,7 @@ begin clk => clk, areset => areset, we => timer_we, - din => write, + din => write(7 downto 0), adr => addr(4 downto 2), dout => timer_read); @@ -60,7 +60,7 @@ begin -- timer_we <= '0'; if writeEnable = '1' then -- external interface - if addr=x"1000" then + if addr=x"2028003" then -- Write to UART -- report "" & character'image(conv_integer(memBint)) severity note; print(l_file, character'val(conv_integer(write))); @@ -68,20 +68,25 @@ begin -- report "xxx" severity failure; -- timer_we <= '1'; else - report "Illegal IO write" severity failure; + print(l_file, character'val(conv_integer(write))); + report "Illegal IO write" severity warning; end if; end if; - read <= (others => 'U'); + read <= (others => '0'); if (readEnable = '1') then if addr=x"1001" then read <= (0=>'1', others => '0'); -- recieve empty elsif addr(12)='1' then - read <= timer_read; + read(7 downto 0) <= timer_read; elsif addr(11)='1' then - read <= ZPU_Frequency; + read(7 downto 0) <= ZPU_Frequency; + elsif addr=x"2028003" then + read <= (others => '0'); else - report "Illegal IO read" severity failure; + read <= (others => '0'); + read(8) <= '1'; + report "Illegal IO read" severity warning; end if; end if; end if; diff --git a/zpu/hdl/zpu4/src/log.txt b/zpu/hdl/zpu4/src/log.txt index af58c93..10f0eaa 100644 --- a/zpu/hdl/zpu4/src/log.txt +++ b/zpu/hdl/zpu4/src/log.txt @@ -11,10 +11,10 @@ l d 1 + - - + H @@ -30,10 +30,10 @@ l d 2 + - - + H @@ -49,10 +49,10 @@ l d 1 + - - + H @@ -68,10 +68,10 @@ l d 2 + - - + H @@ -87,10 +87,10 @@ l d 1 + - - + H @@ -106,10 +106,10 @@ l d 2 + - - + H @@ -125,10 +125,10 @@ l d 1 + - - + H @@ -144,10 +144,10 @@ l d 2 + - - + H @@ -163,10 +163,10 @@ l d 1 + - - + H @@ -182,10 +182,10 @@ l d 2 + - - + H @@ -201,10 +201,10 @@ l d 1 + - - + H @@ -220,10 +220,10 @@ l d 2 + - - + H @@ -239,10 +239,10 @@ l d 1 + - - + H @@ -258,10 +258,10 @@ l d 2 + - - + H @@ -277,10 +277,10 @@ l d 1 + - - + H @@ -296,85 +296,10 @@ l d 2 + - - + H -e -l -l -o - -w -o -r -l -d - -1 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -2 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -1 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -2 - - - - - - diff --git a/zpu/hdl/zpu4/src/sim_fpga_top.vhd b/zpu/hdl/zpu4/src/sim_fpga_top.vhd index 2905505..4defc82 100644 --- a/zpu/hdl/zpu4/src/sim_fpga_top.vhd +++ b/zpu/hdl/zpu4/src/sim_fpga_top.vhd @@ -52,8 +52,8 @@ component zpu_io is busy : out std_logic; writeEnable : in std_logic; readEnable : in std_logic; - write : in std_logic_vector(7 downto 0); - read : out std_logic_vector(7 downto 0); + write : in std_logic_vector(wordSize-1 downto 0); + read : out std_logic_vector(wordSize-1 downto 0); addr : in std_logic_vector(maxAddrBit downto minAddrBit) ); end component; @@ -82,7 +82,7 @@ signal dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0); signal io_busy : std_logic; -signal io_mem_read : std_logic_vector(7 downto 0); +signal io_mem_read : std_logic_vector(wordSize-1 downto 0); signal io_mem_writeEnable : std_logic; signal io_mem_readEnable : std_logic; @@ -131,7 +131,7 @@ begin busy => io_busy, writeEnable => io_mem_writeEnable, readEnable => io_mem_readEnable, - write => mem_write(7 downto 0), + write => mem_write(wordSize-1 downto 0), read => io_mem_read, addr => mem_addr(maxAddrBit downto minAddrBit) ); @@ -154,8 +154,7 @@ begin end if; if io_ready='1' then - mem_read <= (others => '0'); - mem_read(7 downto 0) <= io_mem_read; + mem_read <= io_mem_read; end if; end process; diff --git a/zpu/hdl/zpu4/src/simzpu.do b/zpu/hdl/zpu4/src/simzpu.do deleted file mode 100644 index e6e3068..0000000 --- a/zpu/hdl/zpu4/src/simzpu.do +++ /dev/null @@ -1,23 +0,0 @@ -set BreakOnAssertion 1 -vlib work - -vcom -93 -explicit zpu_config.vhd -vcom -93 -explicit zpupkg.vhd -vcom -93 -explicit txt_util.vhd -vcom -93 -explicit sim_fpga_top.vhd -vcom -93 -explicit zpu_core.vhd -vcom -93 -explicit dram.vhd -vcom -93 -explicit timer.vhd -vcom -93 -explicit io.vhd -vcom -93 -explicit trace.vhd - -# run ZPU -vsim fpga_top -view wave -add wave -recursive fpga_top/zpu/* -#add wave -recursive fpga_top/* -view structure -#view signals - -# Enough to run tiny programs -run 1000 ms diff --git a/zpu/hdl/zpu4/src/simzpu_intstack.do b/zpu/hdl/zpu4/src/simzpu_intstack.do deleted file mode 100644 index cec4873..0000000 --- a/zpu/hdl/zpu4/src/simzpu_intstack.do +++ /dev/null @@ -1,23 +0,0 @@ -set BreakOnAssertion 1 -vlib work - -vcom -93 -explicit zpu_config_trace.vhd -vcom -93 -explicit zpupkg.vhd -vcom -93 -explicit txt_util.vhd -vcom -93 -explicit sim_fpga_top.vhd -vcom -93 -explicit zpu_core_intstack.vhd -vcom -93 -explicit dram_hello.vhd -vcom -93 -explicit timer.vhd -vcom -93 -explicit io.vhd -vcom -93 -explicit trace.vhd - -# run ZPU -vsim fpga_top -view wave -add wave -recursive fpga_top/zpu/* -#add wave -recursive fpga_top/* -view structure -#view signals - -# Enough to run tiny programs -run 15 ms diff --git a/zpu/hdl/zpu4/src/simzpu_medium.do b/zpu/hdl/zpu4/src/simzpu_medium.do new file mode 100644 index 0000000..a6c1fe2 --- /dev/null +++ b/zpu/hdl/zpu4/src/simzpu_medium.do @@ -0,0 +1,28 @@ +# Xilinx WebPack modelsim script +# +# cd C:/workspace/zpu/zpu/hdl/zpu4/src +# do simzpu_medium.do + +set BreakOnAssertion 1 +vlib work + +vcom -93 -explicit zpu_config_trace.vhd +vcom -93 -explicit zpupkg.vhd +vcom -93 -explicit txt_util.vhd +vcom -93 -explicit sim_fpga_top.vhd +vcom -93 -explicit zpu_core.vhd +vcom -93 -explicit dram_hello.vhd +vcom -93 -explicit timer.vhd +vcom -93 -explicit io.vhd +vcom -93 -explicit trace.vhd + +# run ZPU +vsim fpga_top +view wave +add wave -recursive fpga_top/zpu/* +#add wave -recursive fpga_top/* +view structure +#view signals + +# Enough to run tiny programs +run 1000 ms diff --git a/zpu/hdl/zpu4/src/zpu_config_trace.vhd b/zpu/hdl/zpu4/src/zpu_config_trace.vhd index d1bbbbb..a2d7d9d 100644 --- a/zpu/hdl/zpu4/src/zpu_config_trace.vhd +++ b/zpu/hdl/zpu4/src/zpu_config_trace.vhd @@ -5,11 +5,13 @@ use ieee.std_logic_unsigned.all; package zpu_config is constant Generate_Trace : boolean := true; - constant wordPower : integer := 5; + constant wordPower : integer := 5; -- during simulation, set this to '0' to get matching trace.txt constant DontCareValue : std_logic := '0'; -- Clock frequency in MHz. constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64"; - constant maxAddrBitIncIO : integer := 15; + constant maxAddrBitIncIO : integer := 27; + constant maxAddrBitDRAM : integer := 16; + constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"001fff8"; end zpu_config; diff --git a/zpu/hdl/zpu4/src/zpu_core.vhd b/zpu/hdl/zpu4/src/zpu_core.vhd index c7093e2..a603fe9 100644 --- a/zpu/hdl/zpu4/src/zpu_core.vhd +++ b/zpu/hdl/zpu4/src/zpu_core.vhd @@ -210,9 +210,7 @@ begin if areset = '1' then state <= State_Idle; break <= '0'; - -- point to top of RAM-8 - sp <= (others => '0'); - sp(maxAddrBit downto minAddrBit+1) <= (others => '1'); + sp <= spStart(maxAddrBitIncIO downto minAddrBit); pc <= (others => '0'); idim_flag <= '0'; diff --git a/zpu/hdl/zpu4/src/zpu_core_small.vhd b/zpu/hdl/zpu4/src/zpu_core_small.vhd index 4d73f88..8ebd40d 100644 --- a/zpu/hdl/zpu4/src/zpu_core_small.vhd +++ b/zpu/hdl/zpu4/src/zpu_core_small.vhd @@ -27,6 +27,19 @@ end zpu_core; architecture behave of zpu_core is +component dualport_ram is +port (clk : in std_logic; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memAWrite : in std_logic_vector(wordSize-1 downto 0); + memARead : out std_logic_vector(wordSize-1 downto 0); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memBWrite : in std_logic_vector(wordSize-1 downto 0); + memBRead : out std_logic_vector(wordSize-1 downto 0)); +end component; + + signal readIO : std_logic; diff --git a/zpu/hdl/zpu4/src/zpuio.vhd b/zpu/hdl/zpu4/src/zpuio.vhd index d14629e..09a1ddd 100644 --- a/zpu/hdl/zpu4/src/zpuio.vhd +++ b/zpu/hdl/zpu4/src/zpuio.vhd @@ -115,30 +115,6 @@ ram_imp: dram port map ( mem_writeMask => mem_writeMask); - -- Read/write are on different addresses - -- The registers are 8 bits and mapped to bit[7:0] - -- - -- 0xC000 Write: Writes to UART TX FIFO (4 byte FIFO) - -- Read : Reads from UART RX FIFO (4 byte FIFO) - -- 0xC004 Read : UART status register - -- Bit 0 = RX FIFO empty - -- Bit 1 = TX FIFO full - -- 0xA000 Skrive: LED's (8 stk.) - - -- 0x9000 Write: bit 0: 1= reset counter - -- 0= counter running - -- bit 1: 1= sample counter (when set to 1) - -- 0=not used - -- Read : counter bit[7:0] - -- 0x9004 Read: counter bit [15:8] - -- 0x9008 Read: counter bit [23:16] - -- 0x900C Read: counter bit [31:24] - -- 0x9010 Read: counter bit [39:32] - -- 0x9014 Read: counter bit [47:40] - -- 0x9018 Read: counter bit [55:48] - -- 0x901C Read: counter bit [63:56] - -- - -- 0x8800 Read: unsigned 8-bit integer with FPGA frequency (in MHz) fauxUart: process(cpu_clk, areset) @@ -158,7 +134,7 @@ ram_imp: dram port map ( end if; if io_writeEnable = '1' then - if io_addr=x"1000" then + if io_addr=x"2028003" then -- Write to UART uartData <= mem_write(7 downto 0); uartTXPending <= '1'; @@ -167,11 +143,11 @@ ram_imp: dram port map ( timer_we <= '1'; io_busy <= '1'; else - report "Illegal IO write" severity failure; +-- report "Illegal IO write" severity failure; end if; end if; if (io_readEnable = '1') then - if io_addr=x"1001" then + if io_addr=x"2028003" then io_read <= (0=>'1', -- recieve empty 1 => uartTXPending, -- tx full others => '0'); @@ -183,7 +159,7 @@ ram_imp: dram port map ( io_read <= ZPU_Frequency; io_busy <= '1'; else - report "Illegal IO read" severity failure; +-- report "Illegal IO read" severity failure; end if; else diff --git a/zpu/hdl/zpu4/src/zpupkg.vhd b/zpu/hdl/zpu4/src/zpupkg.vhd index 30c3e46..fd00b9e 100644 --- a/zpu/hdl/zpu4/src/zpupkg.vhd +++ b/zpu/hdl/zpu4/src/zpupkg.vhd @@ -23,17 +23,6 @@ package zpupkg is constant stack_bits : integer := 5; constant stack_size : integer := 2**stack_bits; - component dualport_ram is - port (clk : in std_logic; - memAWriteEnable : in std_logic; - memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); - memAWrite : in std_logic_vector(wordSize-1 downto 0); - memARead : out std_logic_vector(wordSize-1 downto 0); - memBWriteEnable : in std_logic; - memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); - memBWrite : in std_logic_vector(wordSize-1 downto 0); - memBRead : out std_logic_vector(wordSize-1 downto 0)); - end component; component dram is port (clk : in std_logic; diff --git a/zpu/hdl/zpu4/test/dmips/build.sh b/zpu/hdl/zpu4/test/dmips/build.sh index 51ff3de..161c748 100644 --- a/zpu/hdl/zpu4/test/dmips/build.sh +++ b/zpu/hdl/zpu4/test/dmips/build.sh @@ -1,3 +1,4 @@ zpu-elf-gcc -DTIME $ZPUDIR/dhrystone/dhry_*.c -O3 -Wl,--gc-sections -Wl,--relax -abel -o dmips.elf zpu-elf-objdump --disassemble-all >dmips.dis dmips.elf zpu-elf-objcopy -O binary dmips.elf dmips.bin +java -classpath ../../../../sw/simulator/zpusim.jar com.zylin.zpu.simulator.tools.MakeRam dmips.bin >dmips.ram diff --git a/zpu/hdl/zpu4/test/dmips/dmips.ram b/zpu/hdl/zpu4/test/dmips/dmips.ram index 27b991d..89047d5 100644 --- a/zpu/hdl/zpu4/test/dmips/dmips.ram +++ b/zpu/hdl/zpu4/test/dmips/dmips.ram @@ -1,14 +1,14 @@ 0 => x"0b0b0b0b", 1 => x"80700b0b", -2 => x"80dde00c", -3 => x"3a0b0b0b", -4 => x"b9990400", +2 => x"80e2a40c", +3 => x"3a0b0b80", +4 => x"c6fc0400", 5 => x"00000000", 6 => x"00000000", 7 => x"00000000", 8 => x"80088408", 9 => x"88080b0b", -10 => x"0bb9e02d", +10 => x"80c7c32d", 11 => x"880c840c", 12 => x"800c0400", 13 => x"00000000", @@ -159,8 +159,8 @@ 158 => x"00000000", 159 => x"00000000", 160 => x"71fc0608", -161 => x"0b0b80dd", -162 => x"cc738306", +161 => x"0b0b80e2", +162 => x"90738306", 163 => x"10100508", 164 => x"060b0b0b", 165 => x"88aa0400", @@ -168,16 +168,16 @@ 167 => x"00000000", 168 => x"80088408", 169 => x"88087575", -170 => x"0b0b0ba1", -171 => x"c92d5050", +170 => x"0b0b0baf", +171 => x"ac2d5050", 172 => x"80085688", 173 => x"0c840c80", 174 => x"0c510400", 175 => x"00000000", 176 => x"80088408", 177 => x"88087575", -178 => x"0b0b0ba2", -179 => x"8d2d5050", +178 => x"0b0b0baf", +179 => x"f02d5050", 180 => x"80085688", 181 => x"0c840c80", 182 => x"0c510400", @@ -207,7 +207,7 @@ 206 => x"00000000", 207 => x"00000000", 208 => x"810b0b0b", -209 => x"80dddc0c", +209 => x"80e2a00c", 210 => x"51040000", 211 => x"00000000", 212 => x"00000000", @@ -255,7 +255,7 @@ 254 => x"00000000", 255 => x"00000000", 256 => x"83d93f80", -257 => x"c78e3f04", +257 => x"cbcf3f04", 258 => x"10101010", 259 => x"10101010", 260 => x"10101010", @@ -279,7 +279,7 @@ 278 => x"72ed3851", 279 => x"51535104", 280 => x"ff3d0d0b", -281 => x"0b80edd0", +281 => x"0b80f294", 282 => x"08528412", 283 => x"08708106", 284 => x"515170f6", @@ -287,44 +287,44 @@ 286 => x"ff06800c", 287 => x"833d0d04", 288 => x"ff3d0d0b", -289 => x"0b80edd0", +289 => x"0b80f294", 290 => x"08528412", 291 => x"08700a10", 292 => x"0a708106", 293 => x"51515170", 294 => x"f1387372", 295 => x"0c833d0d", -296 => x"0480dddc", +296 => x"0480e2a0", 297 => x"08802ea8", 298 => x"38838080", 299 => x"0b0b0b80", -300 => x"edd00c82", +300 => x"f2940c82", 301 => x"a0800b0b", -302 => x"0b80edd4", +302 => x"0b80f298", 303 => x"0c829080", -304 => x"0b80ede4", +304 => x"0b80f2a8", 305 => x"0c0b0b80", -306 => x"edd80b80", -307 => x"ede80c04", +306 => x"f29c0b80", +307 => x"f2ac0c04", 308 => x"f8808080", 309 => x"a40b0b0b", -310 => x"80edd00c", +310 => x"80f2940c", 311 => x"f8808082", 312 => x"800b0b0b", -313 => x"80edd40c", +313 => x"80f2980c", 314 => x"f8808084", -315 => x"800b80ed", -316 => x"e40cf880", +315 => x"800b80f2", +316 => x"a80cf880", 317 => x"8080940b", -318 => x"80ede80c", +318 => x"80f2ac0c", 319 => x"f8808080", -320 => x"9c0b80ed", -321 => x"e00cf880", +320 => x"9c0b80f2", +321 => x"a40cf880", 322 => x"8080a00b", -323 => x"80edec0c", +323 => x"80f2b00c", 324 => x"04f23d0d", 325 => x"600b0b80", -326 => x"edd40856", +326 => x"f2980856", 327 => x"5d82750c", 328 => x"8059805a", 329 => x"800b8f3d", @@ -334,7 +334,7 @@ 333 => x"81ff067c", 334 => x"832b5658", 335 => x"5276537b", -336 => x"5196bc3f", +336 => x"519af33f", 337 => x"7d7f7a72", 338 => x"077c7207", 339 => x"71716081", @@ -342,14 +342,14 @@ 341 => x"5b595755", 342 => x"7a8724bb", 343 => x"380b0b80", -344 => x"edd4087b", +344 => x"f298087b", 345 => x"10101170", 346 => x"08585155", 347 => x"807681ff", 348 => x"067c832b", 349 => x"56585276", -350 => x"537b5196", -351 => x"823f7d7f", +350 => x"537b519a", +351 => x"b93f7d7f", 352 => x"7a72077c", 353 => x"72077171", 354 => x"60810541", @@ -360,28 +360,28 @@ 359 => x"1e0c7c80", 360 => x"0c903d0d", 361 => x"04ff3d0d", -362 => x"80eddc33", +362 => x"80f2a033", 363 => x"5170a738", -364 => x"80dde808", +364 => x"80e2ac08", 365 => x"70085252", 366 => x"70802e94", 367 => x"38841280", -368 => x"dde80c70", -369 => x"2d80dde8", +368 => x"e2ac0c70", +369 => x"2d80e2ac", 370 => x"08700852", 371 => x"5270ee38", -372 => x"810b80ed", -373 => x"dc34833d", +372 => x"810b80f2", +373 => x"a034833d", 374 => x"0d040480", 375 => x"3d0d0b0b", -376 => x"80edcc08", +376 => x"80f29008", 377 => x"802e8e38", 378 => x"0b0b0b0b", 379 => x"800b802e", 380 => x"09810685", 381 => x"38823d0d", 382 => x"040b0b80", -383 => x"edcc510b", +383 => x"f290510b", 384 => x"0b0bf3fc", 385 => x"3f823d0d", 386 => x"0404ff3d", @@ -477,116 +477,116 @@ 476 => x"56758024", 477 => x"fef338fe", 478 => x"8f398a52", -479 => x"7351938d", +479 => x"7351a0f0", 480 => x"3f80080b", -481 => x"0b80cfc0", +481 => x"0b80d484", 482 => x"05337670", 483 => x"81055834", 484 => x"8a527351", -485 => x"92b33f80", +485 => x"a0963f80", 486 => x"08548008", 487 => x"802effac", 488 => x"388a5273", -489 => x"5192e63f", +489 => x"51a0c93f", 490 => x"80080b0b", -491 => x"80cfc005", +491 => x"80d48405", 492 => x"33767081", 493 => x"0558348a", -494 => x"52735192", -495 => x"8c3f8008", +494 => x"5273519f", +495 => x"ef3f8008", 496 => x"548008ff", 497 => x"b538ff84", 498 => x"39745276", 499 => x"53b43dff", -500 => x"b8055190", -501 => x"ff3fa33d", +500 => x"b8055195", +501 => x"b63fa33d", 502 => x"0856fed9", 503 => x"39803d0d", 504 => x"80c10b81", -505 => x"bc9c3480", -506 => x"0b81bdf4", +505 => x"c0f43480", +506 => x"0b81c2d0", 507 => x"0c70800c", 508 => x"823d0d04", 509 => x"ff3d0d80", -510 => x"0b81bc9c", +510 => x"0b81c0f4", 511 => x"33525270", 512 => x"80c12e99", -513 => x"387181bd", -514 => x"f4080781", -515 => x"bdf40c80", -516 => x"c20b81bc", -517 => x"a0347080", +513 => x"387181c2", +514 => x"d0080781", +515 => x"c2d00c80", +516 => x"c20b81c0", +517 => x"f8347080", 518 => x"0c833d0d", 519 => x"04810b81", -520 => x"bdf40807", -521 => x"81bdf40c", +520 => x"c2d00807", +521 => x"81c2d00c", 522 => x"80c20b81", -523 => x"bca03470", +523 => x"c0f83470", 524 => x"800c833d", 525 => x"0d04fd3d", 526 => x"0d757008", 527 => x"8a055353", -528 => x"81bc9c33", +528 => x"81c0f433", 529 => x"517080c1", 530 => x"2e8b3873", 531 => x"f3387080", 532 => x"0c853d0d", 533 => x"04ff1270", -534 => x"81bc9808", +534 => x"81c0f008", 535 => x"31740c80", 536 => x"0c853d0d", 537 => x"04fc3d0d", -538 => x"81bca408", +538 => x"81c0fc08", 539 => x"5574802e", 540 => x"8c387675", 541 => x"08710c81", -542 => x"bca40856", +542 => x"c0fc0856", 543 => x"548c1553", -544 => x"81bc9808", -545 => x"528a518d", -546 => x"b83f7380", +544 => x"81c0f008", +545 => x"528a5190", +546 => x"f03f7380", 547 => x"0c863d0d", 548 => x"04fb3d0d", 549 => x"77700856", 550 => x"56b05381", -551 => x"bca40852", -552 => x"74519ed1", +551 => x"c0fc0852", +552 => x"7451acb4", 553 => x"3f850b8c", 554 => x"170c850b", 555 => x"8c160c75", 556 => x"08750c81", -557 => x"bca40854", +557 => x"c0fc0854", 558 => x"73802e8a", 559 => x"38730875", -560 => x"0c81bca4", +560 => x"0c81c0fc", 561 => x"08548c14", -562 => x"5381bc98", +562 => x"5381c0f0", 563 => x"08528a51", -564 => x"8cef3f84", +564 => x"90a73f84", 565 => x"1508ad38", 566 => x"860b8c16", 567 => x"0c881552", 568 => x"88160851", -569 => x"8bfb3f81", -570 => x"bca40870", +569 => x"8fb33f81", +570 => x"c0fc0870", 571 => x"08760c54", 572 => x"8c157054", 573 => x"548a5273", -574 => x"08518cc5", +574 => x"08518ffd", 575 => x"3f73800c", 576 => x"873d0d04", 577 => x"750854b0", 578 => x"53735275", -579 => x"519de63f", +579 => x"51abc93f", 580 => x"73800c87", -581 => x"3d0d04e1", +581 => x"3d0d04d9", 582 => x"3d0db051", -583 => x"91883f80", -584 => x"0881bc94", -585 => x"0cb05190", -586 => x"fd3f8008", -587 => x"81bca40c", -588 => x"81bc9408", +583 => x"9eeb3f80", +584 => x"0881c0ec", +585 => x"0cb0519e", +586 => x"e03f8008", +587 => x"81c0fc0c", +588 => x"81c0ec08", 589 => x"80080c80", 590 => x"0b800884", 591 => x"050c820b", @@ -594,2838 +594,2838 @@ 593 => x"0ca80b80", 594 => x"088c050c", 595 => x"9f530b0b", -596 => x"80cfcc52", +596 => x"80d49052", 597 => x"80089005", -598 => x"519d9a3f", -599 => x"993d5c9f", +598 => x"51aafd3f", +599 => x"a13d5e9f", 600 => x"530b0b80", -601 => x"cfec527b", -602 => x"519d8a3f", -603 => x"8a0b80fa", -604 => x"dc0c0b0b", -605 => x"80da9051", +601 => x"d4b0527d", +602 => x"51aaed3f", +603 => x"8a0b80ff", +604 => x"b00c0b0b", +605 => x"80ded451", 606 => x"f9b43f0b", -607 => x"0b80d08c", +607 => x"0b80d4d0", 608 => x"51f9ab3f", -609 => x"0b0b80da", -610 => x"9051f9a2", -611 => x"3f80ddf0", -612 => x"08802e89", -613 => x"aa380b0b", -614 => x"80d0bc51", +609 => x"0b0b80de", +610 => x"d451f9a2", +611 => x"3f80e2b4", +612 => x"08802e8a", +613 => x"cf380b0b", +614 => x"80d58051", 615 => x"f9903f0b", -616 => x"0b80da90", +616 => x"0b80ded4", 617 => x"51f9873f", -618 => x"80ddec08", +618 => x"80e2b008", 619 => x"520b0b80", -620 => x"d0e851f8", -621 => x"f93f8051", -622 => x"aecb3f80", -623 => x"0880edfc", -624 => x"0c810b92", -625 => x"3d5c5880", -626 => x"0b80ddec", -627 => x"082582d5", -628 => x"388e3d5d", -629 => x"80c10b81", -630 => x"bc9c3481", -631 => x"0b81bdf4", -632 => x"0c80c20b", -633 => x"81bca034", -634 => x"825e835a", -635 => x"9f530b0b", -636 => x"80d19852", -637 => x"7a519bfd", -638 => x"3f815f80", -639 => x"7b537c52", -640 => x"558be23f", -641 => x"8008752e", -642 => x"09810683", -643 => x"38815574", -644 => x"81bdf40c", -645 => x"7d705755", -646 => x"748325a1", -647 => x"38741010", -648 => x"15fd0540", -649 => x"a13dffbc", -650 => x"05538352", -651 => x"75518a91", -652 => x"3f811e70", -653 => x"5f705755", -654 => x"837524e1", -655 => x"387f5474", -656 => x"5380ee80", -657 => x"5281bcac", -658 => x"518a863f", -659 => x"81bca408", -660 => x"70085757", -661 => x"b0537652", -662 => x"75519b99", -663 => x"3f850b8c", -664 => x"180c850b", -665 => x"8c170c76", -666 => x"08760c81", -667 => x"bca40855", -668 => x"74802e8a", -669 => x"38740876", -670 => x"0c81bca4", -671 => x"08558c15", -672 => x"5381bc98", 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x"2074696d", +3045 => x"6520746f", +3046 => x"6f20736d", +3047 => x"616c6c20", +3048 => x"746f206f", +3049 => x"62746169", +3050 => x"6e206d65", +3051 => x"616e696e", +3052 => x"6766756c", +3053 => x"20726573", +3054 => x"756c7473", +3055 => x"0a000000", +3056 => x"506c6561", +3057 => x"73652069", +3058 => x"6e637265", +3059 => x"61736520", +3060 => x"6e756d62", +3061 => x"6572206f", +3062 => x"66207275", +3063 => x"6e730a00", +3064 => x"44485259", +3065 => x"53544f4e", +3066 => x"45205052", +3067 => x"4f475241", +3068 => x"4d2c2033", +3069 => x"27524420", +3070 => x"53545249", +3071 => x"4e470000", +3072 => x"00010202", +3073 => x"03030303", +3074 => x"04040404", +3075 => x"04040404", +3076 => x"05050505", +3077 => x"05050505", +3078 => x"05050505", +3079 => x"05050505", +3080 => x"06060606", +3081 => x"06060606", +3082 => x"06060606", +3083 => x"06060606", +3084 => x"06060606", +3085 => x"06060606", +3086 => x"06060606", +3087 => x"06060606", +3088 => x"07070707", +3089 => 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x"08080808", +3135 => x"08080808", +3136 => x"43000000", +3137 => x"64756d6d", +3138 => x"792e6578", +3139 => x"65000000", +3140 => x"00ffffff", +3141 => x"ff00ffff", +3142 => x"ffff00ff", +3143 => x"ffffff00", +3144 => x"00000000", +3145 => x"00000000", +3146 => x"00000000", +3147 => x"0000390c", +3148 => x"000004d2", +3149 => x"00000000", +3150 => x"00000000", +3151 => x"00000000", +3152 => x"00000000", +3153 => x"00000000", +3154 => x"00000000", +3155 => x"00000000", +3156 => x"00000000", +3157 => x"00000000", +3158 => x"00000000", +3159 => x"00000000", +3160 => x"00000000", +3161 => x"00000000", +3162 => x"ffffffff", +3163 => x"00000000", +3164 => x"00020000", +3165 => x"00000000", +3166 => x"00000000", +3167 => x"00003174", +3168 => x"00003174", +3169 => x"0000317c", +3170 => x"0000317c", +3171 => x"00003184", +3172 => x"00003184", +3173 => x"0000318c", +3174 => x"0000318c", +3175 => x"00003194", +3176 => x"00003194", +3177 => x"0000319c", +3178 => x"0000319c", +3179 => x"000031a4", +3180 => x"000031a4", +3181 => x"000031ac", +3182 => x"000031ac", +3183 => x"000031b4", +3184 => x"000031b4", +3185 => x"000031bc", +3186 => x"000031bc", +3187 => x"000031c4", +3188 => x"000031c4", +3189 => x"000031cc", +3190 => x"000031cc", +3191 => x"000031d4", +3192 => x"000031d4", +3193 => x"000031dc", +3194 => x"000031dc", +3195 => x"000031e4", +3196 => x"000031e4", +3197 => x"000031ec", +3198 => x"000031ec", +3199 => x"000031f4", +3200 => x"000031f4", +3201 => x"000031fc", +3202 => x"000031fc", +3203 => x"00003204", +3204 => x"00003204", +3205 => x"0000320c", +3206 => x"0000320c", +3207 => x"00003214", +3208 => x"00003214", +3209 => x"0000321c", +3210 => x"0000321c", +3211 => x"00003224", +3212 => x"00003224", +3213 => x"0000322c", +3214 => x"0000322c", +3215 => x"00003234", +3216 => x"00003234", +3217 => x"0000323c", +3218 => x"0000323c", +3219 => x"00003244", +3220 => x"00003244", +3221 => x"0000324c", +3222 => x"0000324c", +3223 => x"00003254", +3224 => x"00003254", +3225 => x"0000325c", +3226 => x"0000325c", +3227 => x"00003264", +3228 => x"00003264", +3229 => x"0000326c", +3230 => x"0000326c", +3231 => x"00003274", +3232 => x"00003274", +3233 => x"0000327c", +3234 => x"0000327c", +3235 => x"00003284", +3236 => x"00003284", +3237 => x"0000328c", +3238 => x"0000328c", +3239 => x"00003294", +3240 => x"00003294", +3241 => x"0000329c", +3242 => x"0000329c", +3243 => x"000032a4", +3244 => x"000032a4", +3245 => x"000032ac", +3246 => x"000032ac", +3247 => x"000032b4", +3248 => x"000032b4", +3249 => x"000032bc", +3250 => x"000032bc", +3251 => x"000032c4", +3252 => x"000032c4", +3253 => x"000032cc", +3254 => x"000032cc", +3255 => x"000032d4", +3256 => x"000032d4", +3257 => x"000032dc", +3258 => x"000032dc", +3259 => x"000032e4", +3260 => x"000032e4", +3261 => x"000032ec", +3262 => x"000032ec", +3263 => x"000032f4", +3264 => x"000032f4", +3265 => x"000032fc", +3266 => x"000032fc", +3267 => x"00003304", +3268 => x"00003304", +3269 => x"0000330c", +3270 => x"0000330c", +3271 => x"00003314", +3272 => x"00003314", +3273 => x"0000331c", +3274 => x"0000331c", +3275 => x"00003324", +3276 => x"00003324", +3277 => x"0000332c", +3278 => x"0000332c", +3279 => x"00003334", +3280 => x"00003334", +3281 => x"0000333c", +3282 => x"0000333c", +3283 => x"00003344", +3284 => x"00003344", +3285 => x"0000334c", +3286 => x"0000334c", +3287 => x"00003354", +3288 => x"00003354", +3289 => x"0000335c", +3290 => x"0000335c", +3291 => x"00003364", +3292 => x"00003364", +3293 => x"0000336c", +3294 => x"0000336c", +3295 => x"00003374", +3296 => x"00003374", +3297 => x"0000337c", +3298 => x"0000337c", +3299 => x"00003384", +3300 => x"00003384", +3301 => x"0000338c", +3302 => x"0000338c", +3303 => x"00003394", +3304 => x"00003394", +3305 => x"0000339c", +3306 => x"0000339c", +3307 => x"000033a4", +3308 => x"000033a4", +3309 => x"000033ac", +3310 => x"000033ac", +3311 => x"000033b4", +3312 => x"000033b4", +3313 => x"000033bc", +3314 => x"000033bc", +3315 => x"000033c4", +3316 => x"000033c4", +3317 => x"000033cc", +3318 => x"000033cc", +3319 => x"000033d4", +3320 => x"000033d4", +3321 => x"000033dc", +3322 => x"000033dc", +3323 => x"000033e4", +3324 => x"000033e4", +3325 => x"000033ec", +3326 => x"000033ec", +3327 => x"000033f4", +3328 => x"000033f4", +3329 => x"000033fc", +3330 => x"000033fc", +3331 => x"00003404", +3332 => x"00003404", +3333 => x"0000340c", +3334 => x"0000340c", +3335 => x"00003414", +3336 => x"00003414", +3337 => x"0000341c", +3338 => x"0000341c", +3339 => x"00003424", +3340 => x"00003424", +3341 => x"0000342c", +3342 => x"0000342c", +3343 => x"00003434", +3344 => x"00003434", +3345 => x"0000343c", +3346 => x"0000343c", +3347 => x"00003444", +3348 => x"00003444", +3349 => x"0000344c", +3350 => x"0000344c", +3351 => x"00003454", +3352 => x"00003454", +3353 => x"0000345c", +3354 => x"0000345c", +3355 => x"00003464", +3356 => x"00003464", +3357 => x"0000346c", +3358 => x"0000346c", +3359 => x"00003474", +3360 => x"00003474", +3361 => x"0000347c", +3362 => x"0000347c", +3363 => x"00003484", +3364 => x"00003484", +3365 => x"0000348c", +3366 => x"0000348c", +3367 => x"00003494", +3368 => x"00003494", +3369 => x"0000349c", +3370 => x"0000349c", +3371 => x"000034a4", +3372 => x"000034a4", +3373 => x"000034ac", +3374 => x"000034ac", +3375 => x"000034b4", +3376 => x"000034b4", +3377 => x"000034bc", +3378 => x"000034bc", +3379 => x"000034c4", +3380 => x"000034c4", +3381 => x"000034cc", +3382 => x"000034cc", +3383 => x"000034d4", +3384 => x"000034d4", +3385 => x"000034dc", +3386 => x"000034dc", +3387 => x"000034e4", +3388 => x"000034e4", +3389 => x"000034ec", +3390 => x"000034ec", +3391 => x"000034f4", +3392 => x"000034f4", +3393 => x"000034fc", +3394 => x"000034fc", +3395 => x"00003504", +3396 => x"00003504", +3397 => x"0000350c", +3398 => x"0000350c", +3399 => x"00003514", +3400 => x"00003514", +3401 => x"0000351c", +3402 => x"0000351c", +3403 => x"00003524", +3404 => x"00003524", +3405 => x"0000352c", +3406 => x"0000352c", +3407 => x"00003534", +3408 => x"00003534", +3409 => x"0000353c", +3410 => x"0000353c", +3411 => x"00003544", +3412 => x"00003544", +3413 => x"0000354c", +3414 => x"0000354c", +3415 => x"00003554", +3416 => x"00003554", +3417 => x"0000355c", +3418 => x"0000355c", +3419 => x"00003564", +3420 => x"00003564", +3421 => x"0000356c", +3422 => x"0000356c", +3423 => x"00003580", 3424 => x"00000000", -3425 => x"00000000", -3426 => x"00000000", -3427 => x"00000000", +3425 => x"000037e8", +3426 => x"00003844", +3427 => x"000038a0", 3428 => x"00000000", 3429 => x"00000000", 3430 => x"00000000", @@ -3435,7 +3435,7 @@ 3434 => x"00000000", 3435 => x"00000000", 3436 => x"00000000", -3437 => x"00000000", +3437 => x"00003100", 3438 => x"00000000", 3439 => x"00000000", 3440 => x"00000000", @@ -3464,11 +3464,11 @@ 3463 => x"00000000", 3464 => x"00000000", 3465 => x"00000000", -3466 => x"00000000", -3467 => x"00000000", -3468 => x"00000000", -3469 => x"00000000", -3470 => x"00000000", +3466 => x"00000001", +3467 => x"330eabcd", +3468 => x"1234e66d", +3469 => x"deec0005", +3470 => x"000b0000", 3471 => x"00000000", 3472 => x"00000000", 3473 => x"00000000", @@ -3500,8 +3500,153 @@ 3499 => x"00000000", 3500 => x"00000000", 3501 => x"00000000", -3502 => x"00002dc0", -3503 => x"ffffffff", +3502 => x"00000000", +3503 => x"00000000", 3504 => x"00000000", -3505 => x"ffffffff", +3505 => x"00000000", 3506 => x"00000000", +3507 => x"00000000", +3508 => x"00000000", +3509 => x"00000000", +3510 => x"00000000", +3511 => x"00000000", +3512 => x"00000000", +3513 => x"00000000", +3514 => x"00000000", +3515 => x"00000000", +3516 => x"00000000", +3517 => x"00000000", +3518 => x"00000000", +3519 => x"00000000", +3520 => x"00000000", +3521 => x"00000000", +3522 => x"00000000", +3523 => x"00000000", +3524 => x"00000000", +3525 => x"00000000", +3526 => x"00000000", +3527 => x"00000000", +3528 => x"00000000", +3529 => x"00000000", +3530 => x"00000000", +3531 => x"00000000", +3532 => x"00000000", +3533 => x"00000000", +3534 => x"00000000", +3535 => x"00000000", +3536 => x"00000000", +3537 => x"00000000", +3538 => x"00000000", +3539 => x"00000000", +3540 => x"00000000", +3541 => x"00000000", +3542 => x"00000000", +3543 => x"00000000", +3544 => x"00000000", +3545 => x"00000000", +3546 => x"00000000", +3547 => x"00000000", +3548 => x"00000000", +3549 => x"00000000", +3550 => x"00000000", +3551 => x"00000000", +3552 => x"00000000", +3553 => x"00000000", +3554 => x"00000000", +3555 => x"00000000", +3556 => x"00000000", +3557 => x"00000000", +3558 => x"00000000", +3559 => x"00000000", +3560 => x"00000000", +3561 => x"00000000", +3562 => x"00000000", +3563 => x"00000000", +3564 => x"00000000", +3565 => x"00000000", +3566 => x"00000000", +3567 => x"00000000", +3568 => x"00000000", +3569 => x"00000000", +3570 => x"00000000", +3571 => x"00000000", +3572 => x"00000000", +3573 => x"00000000", +3574 => x"00000000", +3575 => x"00000000", +3576 => x"00000000", +3577 => x"00000000", +3578 => x"00000000", +3579 => x"00000000", +3580 => x"00000000", +3581 => x"00000000", +3582 => x"00000000", +3583 => x"00000000", +3584 => x"00000000", +3585 => x"00000000", +3586 => x"00000000", +3587 => x"00000000", +3588 => x"00000000", +3589 => x"00000000", +3590 => x"00000000", +3591 => x"00000000", +3592 => x"00000000", +3593 => x"00000000", +3594 => x"00000000", +3595 => x"00000000", +3596 => x"00000000", +3597 => x"00000000", +3598 => x"00000000", +3599 => x"00000000", +3600 => x"00000000", +3601 => x"00000000", +3602 => x"00000000", +3603 => x"00000000", +3604 => x"00000000", +3605 => x"00000000", +3606 => x"00000000", +3607 => x"00000000", +3608 => x"00000000", +3609 => x"00000000", +3610 => x"00000000", +3611 => x"00000000", +3612 => x"00000000", +3613 => x"00000000", +3614 => x"00000000", +3615 => x"00000000", +3616 => x"00000000", +3617 => x"00000000", +3618 => x"00000000", +3619 => x"00000000", +3620 => x"00000000", +3621 => x"00000000", +3622 => x"00000000", +3623 => x"00000000", +3624 => x"00000000", +3625 => x"00000000", +3626 => x"00000000", +3627 => x"00000000", +3628 => x"00000000", +3629 => x"00000000", +3630 => x"00000000", +3631 => x"00000000", +3632 => x"00000000", +3633 => x"00000000", +3634 => x"00000000", +3635 => x"00000000", +3636 => x"00000000", +3637 => x"00000000", +3638 => x"00000000", +3639 => x"00000000", +3640 => x"00000000", +3641 => x"00000000", +3642 => x"00000000", +3643 => x"00000000", +3644 => x"00000000", +3645 => x"00000000", +3646 => x"00000000", +3647 => x"00003104", +3648 => x"ffffffff", +3649 => x"00000000", +3650 => x"ffffffff", +3651 => x"00000000", diff --git a/zpu/hdl/zpu4/test/hello/build.sh b/zpu/hdl/zpu4/test/hello/build.sh index 0d81138..dd87410 100644 --- a/zpu/hdl/zpu4/test/hello/build.sh +++ b/zpu/hdl/zpu4/test/hello/build.sh @@ -1,3 +1,4 @@ -zpu-elf-gcc -O3 -abel `pwd`/hello.c -o hello.elf -Wl,--relax -Wl,--gc-sections -g +zpu-elf-gcc -O3 -phi `pwd`/hello.c -o hello.elf -Wl,--relax -Wl,--gc-sections -g zpu-elf-objdump --disassemble-all >hello.dis hello.elf zpu-elf-objcopy -O binary hello.elf hello.bin +java -classpath ../../../../sw/simulator/zpusim.jar com.zylin.zpu.simulator.tools.MakeRam hello.bin >hello.ram diff --git a/zpu/hdl/zpu4/test/hello/hello.bin b/zpu/hdl/zpu4/test/hello/hello.bin index fe17308..7c37759 100644 Binary files a/zpu/hdl/zpu4/test/hello/hello.bin and b/zpu/hdl/zpu4/test/hello/hello.bin differ diff --git a/zpu/hdl/zpu4/test/hello/hello.c b/zpu/hdl/zpu4/test/hello/hello.c index ea3dbb8..609c163 100644 --- a/zpu/hdl/zpu4/test/hello/hello.c +++ b/zpu/hdl/zpu4/test/hello/hello.c @@ -1,10 +1,6 @@ /* - -zpu-elf-gcc -abel `pwd`/hello.c -o hello.elf -Wl,--relax -Wl,--gc-sections -g -zpu-elf-objdump --disassemble-all >hello.dis hello.elf -zpu-elf-objcopy -O binary hello.elf hello.bin - - * */ + * Small hello world example, does not use printf() + */ #include int j; diff --git a/zpu/hdl/zpu4/test/hello/hello.elf b/zpu/hdl/zpu4/test/hello/hello.elf index 999b9a3..73d28e7 100644 Binary files a/zpu/hdl/zpu4/test/hello/hello.elf and b/zpu/hdl/zpu4/test/hello/hello.elf differ diff --git a/zpu/hdl/zpu4/test/hello/hello.ram b/zpu/hdl/zpu4/test/hello/hello.ram index f310151..175d3a8 100644 --- a/zpu/hdl/zpu4/test/hello/hello.ram +++ b/zpu/hdl/zpu4/test/hello/hello.ram @@ -1,14 +1,14 @@ 0 => x"0b0b0b0b", -1 => x"80700b0b", -2 => x"80d3900c", +1 => x"82700b0b", +2 => x"80cfd80c", 3 => x"3a0b0b80", -4 => x"c8b20400", +4 => x"c6d00400", 5 => x"00000000", 6 => x"00000000", 7 => x"00000000", 8 => x"80088408", 9 => x"88080b0b", -10 => x"80c8fb2d", +10 => x"80c7972d", 11 => x"880c840c", 12 => x"800c0400", 13 => x"00000000", @@ -159,8 +159,8 @@ 158 => x"00000000", 159 => x"00000000", 160 => x"71fc0608", -161 => x"0b0b80d2", -162 => x"fc738306", +161 => x"0b0b80cf", +162 => x"c4738306", 163 => x"10100508", 164 => x"060b0b0b", 165 => x"88aa0400", @@ -168,16 +168,16 @@ 167 => x"00000000", 168 => x"80088408", 169 => x"88087575", -170 => x"0b0b0b8d", -171 => x"872d5050", +170 => x"0b0b0b8b", +171 => x"9f2d5050", 172 => x"80085688", 173 => x"0c840c80", 174 => x"0c510400", 175 => x"00000000", 176 => x"80088408", 177 => x"88087575", -178 => x"0b0b0b8d", -179 => x"cb2d5050", +178 => x"0b0b0b8b", +179 => x"e32d5050", 180 => x"80085688", 181 => x"0c840c80", 182 => x"0c510400", @@ -207,7 +207,7 @@ 206 => x"00000000", 207 => x"00000000", 208 => x"810b0b0b", -209 => x"80d38c0c", +209 => x"80cfd40c", 210 => x"51040000", 211 => x"00000000", 212 => x"00000000", @@ -254,8 +254,8 @@ 253 => x"00000000", 254 => x"00000000", 255 => x"00000000", -256 => x"83d93f80", -257 => x"ca953f04", +256 => x"82c53f80", +257 => x"c6d93f04", 258 => x"10101010", 259 => x"10101010", 260 => x"10101010", @@ -278,2394 +278,2394 @@ 277 => x"0a100a53", 278 => x"72ed3851", 279 => x"51535104", -280 => x"ff3d0d0b", -281 => x"0b80e2f8", -282 => x"08528412", -283 => x"08708106", -284 => x"515170f6", -285 => x"38710881", -286 => x"ff06800c", -287 => x"833d0d04", -288 => x"ff3d0d0b", -289 => x"0b80e2f8", -290 => x"08528412", -291 => x"08700a10", -292 => x"0a708106", -293 => x"51515170", -294 => x"f1387372", -295 => x"0c833d0d", -296 => x"0480d38c", -297 => x"08802ea8", -298 => x"38838080", -299 => x"0b0b0b80", -300 => x"e2f80c82", -301 => x"a0800b0b", -302 => x"0b80e2fc", -303 => x"0c829080", -304 => x"0b80e38c", -305 => x"0c0b0b80", -306 => x"e3800b80", -307 => x"e3900c04", -308 => x"f8808080", -309 => x"a40b0b0b", -310 => x"80e2f80c", -311 => x"f8808082", -312 => x"800b0b0b", -313 => x"80e2fc0c", -314 => x"f8808084", -315 => x"800b80e3", -316 => x"8c0cf880", -317 => x"8080940b", -318 => x"80e3900c", -319 => x"f8808080", -320 => x"9c0b80e3", -321 => x"880cf880", -322 => x"8080a00b", -323 => x"80e3940c", -324 => x"04f23d0d", -325 => x"600b0b80", -326 => x"e2fc0856", -327 => x"5d82750c", -328 => x"8059805a", -329 => x"800b8f3d", -330 => x"71101017", -331 => x"70085957", -332 => x"5d5b8076", -333 => x"81ff067c", -334 => x"832b5658", -335 => x"5276537b", -336 => x"5181fa3f", -337 => x"7d7f7a72", -338 => x"077c7207", -339 => x"71716081", -340 => x"05415f5d", -341 => x"5b595755", -342 => x"7a8724bb", -343 => x"380b0b80", -344 => x"e2fc087b", -345 => x"10101170", -346 => x"08585155", -347 => x"807681ff", -348 => x"067c832b", -349 => x"56585276", -350 => x"537b5181", -351 => x"c03f7d7f", -352 => x"7a72077c", -353 => x"72077171", -354 => x"60810541", -355 => x"5f5d5b59", -356 => x"5755877b", -357 => x"25c73876", -358 => x"7d0c7784", -359 => x"1e0c7c80", -360 => x"0c903d0d", -361 => x"04ff3d0d", -362 => x"80e38433", -363 => x"5170a738", -364 => x"80d39808", -365 => x"70085252", -366 => x"70802e94", -367 => x"38841280", -368 => x"d3980c70", -369 => x"2d80d398", -370 => x"08700852", -371 => x"5270ee38", -372 => x"810b80e3", -373 => x"8434833d", -374 => x"0d040480", -375 => x"3d0d0b0b", -376 => x"80e2f408", -377 => x"802e8e38", -378 => x"0b0b0b0b", -379 => x"800b802e", -380 => x"09810685", -381 => x"38823d0d", -382 => x"040b0b80", -383 => x"e2f4510b", -384 => x"0b0bf3fc", -385 => x"3f823d0d", -386 => x"0404fe3d", -387 => x"0d89530b", -388 => x"0b80d2c8", -389 => x"51838d3f", -390 => x"0b0b80d2", -391 => x"d8518384", -392 => x"3f810a0b", -393 => x"80e3980c", -394 => x"ff0b80e3", -395 => x"9c0cff13", -396 => x"53728025", -397 => x"da387280", -398 => x"0c843d0d", -399 => x"04f93d0d", -400 => x"797b7d7f", -401 => x"56545254", -402 => x"72802ea0", -403 => x"38705771", -404 => x"58a07331", -405 => x"52807225", -406 => x"a1387770", -407 => x"742b5770", -408 => x"732a7875", -409 => x"2b075651", -410 => x"74765351", -411 => x"70740c71", -412 => x"84150c73", -413 => x"800c893d", -414 => x"0d048056", -415 => x"7772302b", -416 => x"55747653", -417 => x"51e639fb", -418 => x"3d0d7779", -419 => x"55558056", -420 => x"757524ab", -421 => x"38807424", -422 => x"9d388053", -423 => x"73527451", -424 => x"80e13f80", -425 => x"08547580", -426 => x"2e853880", -427 => x"08305473", -428 => x"800c873d", -429 => x"0d047330", -430 => x"76813257", -431 => x"54dc3974", -432 => x"30558156", -433 => x"738025d2", -434 => x"38ec39fa", -435 => x"3d0d787a", -436 => x"57558057", -437 => x"767524a4", -438 => x"38759f2c", -439 => x"54815375", -440 => x"74327431", -441 => x"5274519b", -442 => x"3f800854", -443 => x"76802e85", -444 => x"38800830", -445 => x"5473800c", -446 => x"883d0d04", -447 => x"74305581", -448 => x"57d739fc", -449 => x"3d0d7678", -450 => x"53548153", -451 => x"80747326", -452 => x"52557280", -453 => x"2e983870", -454 => x"802eab38", -455 => x"807224a6", -456 => x"38711073", -457 => x"10757226", -458 => x"53545272", -459 => x"ea387351", -460 => x"78833874", -461 => x"5170800c", -462 => x"863d0d04", -463 => x"720a100a", -464 => x"720a100a", -465 => x"53537280", -466 => x"2ee43871", -467 => x"7426ed38", -468 => x"73723175", -469 => x"7407740a", -470 => x"100a740a", -471 => x"100a5555", -472 => x"5654e339", -473 => x"f73d0d7c", -474 => x"70525380", -475 => x"f93f7254", -476 => x"80085580", -477 => x"d2e85681", -478 => x"57800881", -479 => x"055a8b3d", -480 => x"e4115953", -481 => x"8259f413", -482 => x"527b8811", -483 => x"08525381", -484 => x"b03f8008", -485 => x"30708008", -486 => x"079f2c8a", -487 => x"07800c53", -488 => x"8b3d0d04", -489 => x"f63d0d7c", -490 => x"80d39c08", -491 => x"71535553", -492 => x"b53f7255", -493 => x"80085680", -494 => x"d2e85781", -495 => x"58800881", -496 => x"055b8c3d", -497 => x"e4115a53", -498 => x"825af413", -499 => x"52881408", -500 => x"5180ee3f", -501 => x"80083070", -502 => x"8008079f", -503 => x"2c8a0780", -504 => x"0c548c3d", -505 => x"0d04fd3d", -506 => x"0d757071", -507 => x"83065355", -508 => x"5270b438", -509 => x"71700870", -510 => x"09f7fbfd", -511 => x"ff1206f8", -512 => x"84828180", -513 => x"06545253", -514 => x"719b3884", -515 => x"13700870", -516 => x"09f7fbfd", -517 => x"ff1206f8", -518 => x"84828180", -519 => x"06545253", -520 => x"71802ee7", -521 => x"38725271", -522 => x"33537280", -523 => x"2e8a3881", -524 => x"12703354", -525 => x"5272f838", -526 => x"71743180", -527 => x"0c853d0d", -528 => x"04f23d0d", -529 => x"60628811", -530 => x"08705856", -531 => x"5f5a7380", -532 => x"2e818c38", -533 => x"8c1a2270", -534 => x"832a8132", -535 => x"81065658", -536 => x"74863890", -537 => x"1a089138", -538 => x"795190b7", -539 => x"3fff5580", -540 => x"0880ec38", -541 => x"8c1a2258", -542 => x"7d085580", -543 => x"7883ffff", -544 => x"06700a10", -545 => x"0a810641", -546 => x"5c577e77", -547 => x"2e80d738", -548 => x"76903874", -549 => x"08841608", -550 => x"88175758", -551 => x"5676802e", -552 => x"f2387654", -553 => x"88807727", -554 => x"84388880", -555 => x"54735375", -556 => x"529c1a08", -557 => x"51a41a08", -558 => x"58772d80", -559 => x"0b800825", -560 => x"82e03880", -561 => x"08167780", -562 => x"08317f88", -563 => x"05088008", -564 => x"31706188", -565 => x"050c5b58", -566 => x"5678ffb4", -567 => x"38805574", -568 => x"800c903d", -569 => x"0d047a81", -570 => x"32810677", -571 => x"40567580", -572 => x"2e81bd38", -573 => x"76903874", -574 => x"08841608", -575 => x"88175758", -576 => x"5976802e", -577 => x"f238881a", -578 => x"087883ff", -579 => x"ff067089", -580 => x"2a810656", -581 => x"59567380", -582 => x"2e82f838", -583 => x"7577278b", -584 => x"3877872a", -585 => x"81065c7b", -586 => x"82b53876", -587 => x"76278338", -588 => x"76567553", -589 => x"78527908", -590 => x"5185833f", -591 => x"881a0876", -592 => x"31881b0c", -593 => x"7908167a", -594 => x"0c765675", -595 => x"19777731", -596 => x"7f880508", -597 => x"78317061", -598 => x"88050c41", -599 => x"58597e80", -600 => x"2efefa38", -601 => x"8c1a2258", -602 => x"ff8a3978", -603 => x"79547c53", -604 => x"7b525684", -605 => x"c93f881a", -606 => x"08793188", -607 => x"1b0c7908", -608 => x"197a0c7c", -609 => x"76315d7c", -610 => x"8e387951", -611 => x"8ff23f80", -612 => x"08818f38", -613 => x"80085f75", -614 => x"1c777731", -615 => x"7f880508", -616 => x"78317061", -617 => x"88050c5d", -618 => x"585c7a80", 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x"70565a57", -667 => x"5280d39c", -668 => x"08518494", -669 => x"3f800880", -670 => x"2effa738", -671 => x"8008901b", -672 => x"0c800816", -673 => x"7a0c7794", -674 => x"1b0c7688", -675 => x"1b0c7656", -676 => x"fd993979", -677 => x"0858901a", -678 => x"08782783", -679 => x"38815475", -680 => x"77278438", -681 => x"73b33894", -682 => x"1a085473", -683 => x"772680d3", -684 => x"38735378", -685 => x"529c1a08", -686 => x"51a41a08", -687 => x"58772d80", -688 => x"08568008", -689 => x"8024fd83", -690 => x"388c1a22", -691 => x"80c0075e", -692 => x"7d8c1b23", -693 => x"ff55fed7", -694 => x"39755378", -695 => x"52775181", -696 => x"dd3f7908", -697 => x"167a0c79", -698 => x"518d953f", -699 => x"8008802e", -700 => x"fcd9388c", -701 => x"1a2280c0", -702 => x"075e7d8c", -703 => x"1b23ff55", -704 => x"fead3976", -705 => x"77547953", -706 => x"78525681", -707 => x"b13f881a", -708 => x"08773188", -709 => x"1b0c7908", -710 => x"177a0cfc", -711 => x"ae39fa3d", -712 => x"0d7a7902", -713 => x"8805a705", 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x"00002ca8", +2862 => x"00002cb0", +2863 => x"00002cb0", +2864 => x"00002cb8", +2865 => x"00002cb8", +2866 => x"00002cc0", +2867 => x"00002cc0", +2868 => x"00002cc8", +2869 => x"00002cc8", +2870 => x"00002cd0", +2871 => x"00002cd0", +2872 => x"00002cd8", +2873 => x"00002cd8", +2874 => x"00002ce0", +2875 => x"00002ce0", +2876 => x"00002ce8", +2877 => x"00002ce8", +2878 => x"00002cf0", +2879 => x"00002cf0", +2880 => x"00002cf8", +2881 => x"00002cf8", +2882 => x"00002d00", +2883 => x"00002d00", +2884 => x"00002d08", +2885 => x"00002d08", +2886 => x"00002d10", +2887 => x"00002d10", +2888 => x"00002d18", +2889 => x"00002d18", +2890 => x"00002d20", +2891 => x"00002d20", +2892 => x"00002d28", +2893 => x"00002d28", +2894 => x"00002d30", +2895 => x"00002d30", +2896 => x"00002d38", +2897 => x"00002d38", +2898 => x"00002d40", +2899 => x"00002d40", +2900 => x"00002d48", +2901 => x"00002d48", +2902 => x"00002d50", +2903 => x"00002d50", 2904 => x"00002d58", 2905 => x"00002d58", 2906 => x"00002d60", @@ -3048,118 +3048,8 @@ 3047 => x"00002f90", 3048 => x"00002f98", 3049 => x"00002f98", -3050 => x"00002fa0", -3051 => x"00002fa0", -3052 => x"00002fa8", -3053 => x"00002fa8", -3054 => x"00002fb0", -3055 => x"00002fb0", -3056 => x"00002fb8", -3057 => x"00002fb8", -3058 => x"00002fc0", -3059 => x"00002fc0", -3060 => x"00002fc8", -3061 => x"00002fc8", -3062 => x"00002fd0", -3063 => x"00002fd0", -3064 => x"00002fd8", -3065 => x"00002fd8", -3066 => x"00002fe0", -3067 => x"00002fe0", -3068 => x"00002fe8", -3069 => x"00002fe8", -3070 => x"00002ff0", -3071 => x"00002ff0", -3072 => x"00002ff8", -3073 => x"00002ff8", -3074 => x"00003000", -3075 => x"00003000", -3076 => x"00003008", -3077 => x"00003008", -3078 => x"00003010", -3079 => x"00003010", -3080 => x"00003018", -3081 => x"00003018", -3082 => x"00003020", -3083 => x"00003020", -3084 => x"00003028", -3085 => x"00003028", -3086 => x"00003030", -3087 => x"00003030", -3088 => x"00003038", -3089 => x"00003038", -3090 => x"00003040", -3091 => x"00003040", -3092 => x"00003048", -3093 => x"00003048", -3094 => x"00003050", -3095 => x"00003050", -3096 => x"00003058", -3097 => x"00003058", -3098 => x"00003060", -3099 => x"00003060", -3100 => x"00003068", -3101 => x"00003068", -3102 => x"00003070", -3103 => x"00003070", -3104 => x"00003078", -3105 => x"00003078", -3106 => x"00003080", -3107 => x"00003080", -3108 => x"00003088", -3109 => x"00003088", -3110 => x"00003090", -3111 => x"00003090", -3112 => x"00003098", -3113 => x"00003098", -3114 => x"000030a0", -3115 => x"000030a0", -3116 => x"000030a8", -3117 => x"000030a8", -3118 => x"000030b0", -3119 => x"000030b0", -3120 => x"000030b8", -3121 => x"000030b8", -3122 => x"000030c0", -3123 => x"000030c0", -3124 => x"000030c8", -3125 => x"000030c8", -3126 => x"000030d0", -3127 => x"000030d0", -3128 => x"000030d8", -3129 => x"000030d8", -3130 => x"000030e0", -3131 => x"000030e0", -3132 => x"000030e8", -3133 => x"000030e8", -3134 => x"000030f0", -3135 => x"000030f0", -3136 => x"000030f8", -3137 => x"000030f8", -3138 => x"00003100", -3139 => x"00003100", -3140 => x"00003108", -3141 => x"00003108", -3142 => x"00003110", -3143 => x"00003110", -3144 => x"00003118", -3145 => x"00003118", -3146 => x"00003120", -3147 => x"00003120", -3148 => x"00003128", -3149 => x"00003128", -3150 => x"00003130", -3151 => x"00003130", -3152 => x"00003138", -3153 => x"00003138", -3154 => x"00003140", -3155 => x"00003140", -3156 => x"00003148", -3157 => x"00003148", -3158 => x"00003150", -3159 => x"00003150", -3160 => x"00002970", -3161 => x"ffffffff", -3162 => x"00000000", -3163 => x"ffffffff", -3164 => x"00000000", +3050 => x"000027b8", +3051 => x"ffffffff", +3052 => x"00000000", +3053 => x"ffffffff", +3054 => x"00000000", -- cgit v1.1 From e5627082149dbce408555bd3a128fd5d128880d2 Mon Sep 17 00:00:00 2001 From: oharboe Date: Thu, 21 Feb 2008 19:17:03 +0000 Subject: * zpu/zpu/sw/index.html. Changed it a bit to make installation easier. --- zpu/ChangeLog | 1 + zpu/hdl/zpu4/src/dmipstrace.do | 5 + zpu/hdl/zpu4/src/dmipstraceintstack.do | 25 - zpu/hdl/zpu4/src/dram_dmips.vhd | 6374 +++++++++++++++---------------- zpu/hdl/zpu4/src/fastdmips.do | 19 - zpu/hdl/zpu4/src/fastdmipsintstack.do | 19 - zpu/hdl/zpu4/src/fastdmipssmall.do | 21 - zpu/hdl/zpu4/src/fasthello.do | 19 - zpu/hdl/zpu4/src/fastsimzpu.do | 19 - zpu/hdl/zpu4/src/log.txt | 347 +- zpu/hdl/zpu4/src/zpu_config_fastsim.vhd | 15 - zpu/hdl/zpu4/test/dmips/build.sh | 2 +- zpu/hdl/zpu4/test/dmips/dmips.bin | Bin 14612 -> 13028 bytes zpu/hdl/zpu4/test/dmips/dmips.elf | Bin 89778 -> 82460 bytes zpu/hdl/zpu4/test/dmips/dmips.ram | 6370 +++++++++++++++--------------- zpu/sw/env.sh | 2 + zpu/sw/index.html | 8 +- zpu/sw/setup.sh | 6 + 18 files changed, 6095 insertions(+), 7157 deletions(-) delete mode 100644 zpu/hdl/zpu4/src/dmipstraceintstack.do delete mode 100644 zpu/hdl/zpu4/src/fastdmips.do delete mode 100644 zpu/hdl/zpu4/src/fastdmipsintstack.do delete mode 100644 zpu/hdl/zpu4/src/fastdmipssmall.do delete mode 100644 zpu/hdl/zpu4/src/fasthello.do delete mode 100644 zpu/hdl/zpu4/src/fastsimzpu.do delete mode 100644 zpu/hdl/zpu4/src/zpu_config_fastsim.vhd create mode 100644 zpu/sw/env.sh create mode 100644 zpu/sw/setup.sh diff --git a/zpu/ChangeLog b/zpu/ChangeLog index 9a6495b..1e5545b 100644 --- a/zpu/ChangeLog +++ b/zpu/ChangeLog @@ -1,4 +1,5 @@ 2008-02-21 Øyvind Harboe + * zpu/zpu/sw/index.html. Changed it a bit to make installation easier. * zpu/zpu/hdl/index.html. Sharpened instructions and shows two working examples. Small & medium ZPU. * got zpu4/src/simzpu_medium.do working again. diff --git a/zpu/hdl/zpu4/src/dmipstrace.do b/zpu/hdl/zpu4/src/dmipstrace.do index 8d5f430..64cf8fd 100644 --- a/zpu/hdl/zpu4/src/dmipstrace.do +++ b/zpu/hdl/zpu4/src/dmipstrace.do @@ -1,3 +1,8 @@ +# Xilinx WebPack modelsim script +# +# cd C:/workspace/zpu/zpu/hdl/zpu4/src +# do dmipstrace.do + set BreakOnAssertion 1 vlib work diff --git a/zpu/hdl/zpu4/src/dmipstraceintstack.do b/zpu/hdl/zpu4/src/dmipstraceintstack.do deleted file mode 100644 index b2addb4..0000000 --- a/zpu/hdl/zpu4/src/dmipstraceintstack.do +++ /dev/null @@ -1,25 +0,0 @@ -set BreakOnAssertion 1 -vlib work - -vcom -93 -explicit zpu_config_trace.vhd -vcom -93 -explicit zpupkg.vhd -vcom -93 -explicit txt_util.vhd -vcom -93 -explicit sim_fpga_top.vhd -vcom -93 -explicit zpu_core_intstack.vhd -vcom -93 -explicit dram_dmips.vhd -vcom -93 -explicit timer.vhd -vcom -93 -explicit io.vhd -vcom -93 -explicit trace.vhd - - -vsim fpga_top -view wave - -add wave -recursive fpga_top/zpu/* -#--add wave -recursive fpga_top/ioMap/* -#add wave -recursive fpga_top/* -view structure - - -# run ZPU -run 5 ms diff --git a/zpu/hdl/zpu4/src/dram_dmips.vhd b/zpu/hdl/zpu4/src/dram_dmips.vhd index e63a27a..a289fd7 100644 --- a/zpu/hdl/zpu4/src/dram_dmips.vhd +++ b/zpu/hdl/zpu4/src/dram_dmips.vhd @@ -22,21 +22,21 @@ end dram; architecture dram_arch of dram is -type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); +type ram_type is array(0 to ((2**(maxAddrBitDRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); shared variable ram : ram_type := ( 0 => x"0b0b0b0b", -1 => x"80700b0b", -2 => x"80e2a40c", +1 => x"82700b0b", +2 => x"80d5f40c", 3 => x"3a0b0b80", -4 => x"c6fc0400", +4 => x"c4fb0400", 5 => x"00000000", 6 => x"00000000", 7 => x"00000000", 8 => x"80088408", 9 => x"88080b0b", -10 => x"80c7c32d", +10 => x"80c5c22d", 11 => x"880c840c", 12 => x"800c0400", 13 => x"00000000", @@ -99,7 +99,7 @@ shared variable ram : ram_type := 70 => x"00000000", 71 => x"00000000", 72 => x"0b0b0b88", -73 => x"c4040000", +73 => x"c3040000", 74 => x"00000000", 75 => x"00000000", 76 => x"00000000", @@ -116,7 +116,7 @@ shared variable ram : ram_type := 87 => x"00000000", 88 => x"72729f06", 89 => x"0981050b", -90 => x"0b0b88a7", +90 => x"0b0b88a6", 91 => x"05040000", 92 => x"00000000", 93 => x"00000000", @@ -187,25 +187,25 @@ shared variable ram : ram_type := 158 => x"00000000", 159 => x"00000000", 160 => x"71fc0608", -161 => x"0b0b80e2", -162 => x"90738306", +161 => x"0b0b80d5", +162 => x"e0738306", 163 => x"10100508", 164 => x"060b0b0b", -165 => x"88aa0400", +165 => x"88a90400", 166 => x"00000000", 167 => x"00000000", 168 => x"80088408", 169 => x"88087575", -170 => x"0b0b0baf", -171 => x"ac2d5050", +170 => x"0b0b0bad", +171 => x"aa2d5050", 172 => x"80085688", 173 => x"0c840c80", 174 => x"0c510400", 175 => x"00000000", 176 => x"80088408", 177 => x"88087575", -178 => x"0b0b0baf", -179 => x"f02d5050", +178 => x"0b0b0bad", +179 => x"ee2d5050", 180 => x"80085688", 181 => x"0c840c80", 182 => x"0c510400", @@ -235,7 +235,7 @@ shared variable ram : ram_type := 206 => x"00000000", 207 => x"00000000", 208 => x"810b0b0b", -209 => x"80e2a00c", +209 => x"80d5f00c", 210 => x"51040000", 211 => x"00000000", 212 => x"00000000", @@ -282,8 +282,8 @@ shared variable ram : ram_type := 253 => x"00000000", 254 => x"00000000", 255 => x"00000000", -256 => x"83d93f80", -257 => x"cbcf3f04", +256 => x"82fd3fbf", +257 => x"a03f0410", 258 => x"10101010", 259 => x"10101010", 260 => x"10101010", @@ -291,2890 +291,2890 @@ shared variable ram : ram_type := 262 => x"10101010", 263 => x"10101010", 264 => x"10101010", -265 => x"10101053", -266 => x"51047381", -267 => x"ff067383", -268 => x"06098105", -269 => x"83051010", -270 => x"102b0772", -271 => x"fc060c51", -272 => x"51043c04", -273 => x"72728072", -274 => x"8106ff05", -275 => x"09720605", -276 => x"71105272", -277 => x"0a100a53", -278 => x"72ed3851", -279 => x"51535104", -280 => x"ff3d0d0b", -281 => x"0b80f294", -282 => x"08528412", -283 => x"08708106", -284 => x"515170f6", -285 => x"38710881", -286 => x"ff06800c", +265 => x"10105351", +266 => x"047381ff", +267 => x"06738306", +268 => x"09810583", +269 => x"05101010", +270 => x"2b0772fc", +271 => x"060c5151", +272 => x"043c0472", +273 => x"72807281", +274 => x"06ff0509", +275 => x"72060571", +276 => x"1052720a", +277 => x"100a5372", +278 => x"ed385151", +279 => x"535104ff", +280 => x"3d0d0b0b", +281 => x"80e5e408", +282 => x"52710870", +283 => x"882a8132", +284 => x"70810651", +285 => x"515170f1", +286 => x"3873720c", 287 => x"833d0d04", -288 => x"ff3d0d0b", -289 => x"0b80f294", -290 => x"08528412", -291 => x"08700a10", -292 => x"0a708106", -293 => x"51515170", -294 => x"f1387372", -295 => x"0c833d0d", -296 => x"0480e2a0", -297 => x"08802ea8", -298 => x"38838080", -299 => x"0b0b0b80", -300 => x"f2940c82", -301 => x"a0800b0b", -302 => x"0b80f298", -303 => x"0c829080", -304 => x"0b80f2a8", -305 => x"0c0b0b80", -306 => x"f29c0b80", -307 => x"f2ac0c04", -308 => x"f8808080", -309 => x"a40b0b0b", -310 => x"80f2940c", -311 => x"f8808082", -312 => x"800b0b0b", -313 => x"80f2980c", -314 => x"f8808084", -315 => x"800b80f2", -316 => x"a80cf880", -317 => x"8080940b", -318 => x"80f2ac0c", -319 => x"f8808080", -320 => x"9c0b80f2", -321 => x"a40cf880", -322 => x"8080a00b", -323 => x"80f2b00c", -324 => x"04f23d0d", -325 => x"600b0b80", -326 => x"f2980856", -327 => x"5d82750c", -328 => x"8059805a", -329 => x"800b8f3d", -330 => x"71101017", -331 => x"70085957", -332 => x"5d5b8076", -333 => x"81ff067c", -334 => x"832b5658", -335 => x"5276537b", -336 => x"519af33f", -337 => x"7d7f7a72", -338 => x"077c7207", -339 => x"71716081", -340 => x"05415f5d", -341 => x"5b595755", -342 => x"7a8724bb", -343 => x"380b0b80", -344 => x"f298087b", -345 => x"10101170", -346 => x"08585155", -347 => x"807681ff", -348 => x"067c832b", -349 => x"56585276", -350 => x"537b519a", -351 => x"b93f7d7f", -352 => x"7a72077c", -353 => x"72077171", -354 => x"60810541", -355 => x"5f5d5b59", -356 => x"5755877b", -357 => x"25c73876", -358 => x"7d0c7784", -359 => x"1e0c7c80", -360 => x"0c903d0d", -361 => x"04ff3d0d", -362 => x"80f2a033", -363 => x"5170a738", -364 => x"80e2ac08", -365 => x"70085252", -366 => x"70802e94", -367 => x"38841280", -368 => x"e2ac0c70", -369 => x"2d80e2ac", -370 => x"08700852", -371 => x"5270ee38", -372 => x"810b80f2", -373 => x"a034833d", -374 => x"0d040480", -375 => x"3d0d0b0b", -376 => x"80f29008", -377 => x"802e8e38", -378 => x"0b0b0b0b", -379 => x"800b802e", -380 => x"09810685", -381 => x"38823d0d", -382 => x"040b0b80", -383 => x"f290510b", -384 => x"0b0bf3fc", -385 => x"3f823d0d", -386 => x"0404ff3d", -387 => x"0d028f05", -388 => x"3352718a", -389 => x"2e8a3871", -390 => x"51fce53f", -391 => x"833d0d04", -392 => x"8d51fcdc", -393 => x"3f7151fc", -394 => x"d73f833d", -395 => x"0d04ce3d", -396 => x"0db53d70", -397 => x"70840552", -398 => x"088c8a5c", -399 => x"56a53d5e", -400 => x"5c807570", -401 => x"81055733", -402 => x"765b5558", -403 => x"73782e80", -404 => x"c1388e3d", -405 => x"5b73a52e", -406 => x"09810680", -407 => x"c5387870", -408 => x"81055a33", -409 => x"547380e4", -410 => x"2e81b638", -411 => x"7380e424", -412 => x"80c63873", -413 => x"80e32ea1", -414 => x"388052a5", -415 => x"51792d80", -416 => x"52735179", -417 => x"2d821858", -418 => x"78708105", -419 => x"5a335473", -420 => x"c4387780", -421 => x"0cb43d0d", -422 => x"047b841d", -423 => x"83123356", -424 => x"5d578052", -425 => x"7351792d", -426 => x"81187970", -427 => x"81055b33", -428 => x"555873ff", -429 => x"a038db39", -430 => x"7380f32e", -431 => x"098106ff", -432 => x"b8387b84", -433 => x"1d710859", -434 => x"5d568077", -435 => x"33555673", -436 => x"762e8d38", -437 => x"81167018", -438 => x"70335755", -439 => x"5674f538", -440 => x"ff165580", -441 => x"7625ffa0", -442 => x"38767081", -443 => x"05583354", -444 => x"80527351", -445 => x"792d8118", -446 => x"75ff1757", -447 => x"57588076", -448 => x"25ff8538", -449 => x"76708105", -450 => x"58335480", -451 => x"52735179", -452 => x"2d811875", -453 => x"ff175757", -454 => x"58758024", -455 => x"cc38fee8", -456 => x"397b841d", -457 => x"71087071", -458 => x"9f2c5953", -459 => x"595d5680", -460 => x"75248195", -461 => x"38757d7c", -462 => x"58565480", -463 => x"5773772e", -464 => x"098106b6", -465 => x"38b07b34", -466 => x"02b50556", -467 => x"7a762e97", -468 => x"38ff1656", -469 => x"75337570", -470 => x"81055734", -471 => x"8117577a", -472 => x"762e0981", -473 => x"06eb3880", -474 => x"7534767d", -475 => x"ff125758", -476 => x"56758024", -477 => x"fef338fe", -478 => x"8f398a52", -479 => x"7351a0f0", -480 => x"3f80080b", -481 => x"0b80d484", -482 => x"05337670", -483 => x"81055834", -484 => x"8a527351", -485 => x"a0963f80", -486 => x"08548008", -487 => x"802effac", -488 => x"388a5273", -489 => x"51a0c93f", -490 => x"80080b0b", -491 => x"80d48405", -492 => x"33767081", -493 => x"0558348a", -494 => x"5273519f", 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x"65000000", +2744 => x"00ffffff", +2745 => x"ff00ffff", +2746 => x"ffff00ff", +2747 => x"ffffff00", +2748 => x"00000000", +2749 => x"00000000", +2750 => x"00000000", +2751 => x"000032dc", +2752 => x"0000c350", +2753 => x"00000000", +2754 => x"00000000", +2755 => x"00000000", +2756 => x"00000000", +2757 => x"00000000", +2758 => x"00000000", +2759 => x"00000000", +2760 => x"00000000", +2761 => x"00000000", +2762 => x"00000000", +2763 => x"00000000", +2764 => x"00000000", +2765 => x"00000000", +2766 => x"ffffffff", +2767 => x"00000000", +2768 => x"00020000", +2769 => x"00000000", +2770 => x"00000000", +2771 => x"00002b44", +2772 => x"00002b44", +2773 => x"00002b4c", +2774 => x"00002b4c", +2775 => x"00002b54", +2776 => x"00002b54", +2777 => x"00002b5c", +2778 => x"00002b5c", +2779 => x"00002b64", +2780 => x"00002b64", +2781 => x"00002b6c", +2782 => x"00002b6c", +2783 => x"00002b74", +2784 => x"00002b74", +2785 => x"00002b7c", +2786 => x"00002b7c", +2787 => x"00002b84", +2788 => x"00002b84", +2789 => x"00002b8c", +2790 => x"00002b8c", +2791 => x"00002b94", +2792 => x"00002b94", +2793 => x"00002b9c", +2794 => x"00002b9c", +2795 => x"00002ba4", +2796 => x"00002ba4", +2797 => x"00002bac", +2798 => x"00002bac", +2799 => x"00002bb4", +2800 => x"00002bb4", +2801 => x"00002bbc", +2802 => x"00002bbc", +2803 => x"00002bc4", +2804 => x"00002bc4", +2805 => x"00002bcc", +2806 => x"00002bcc", +2807 => x"00002bd4", +2808 => x"00002bd4", +2809 => x"00002bdc", +2810 => x"00002bdc", +2811 => x"00002be4", +2812 => x"00002be4", +2813 => x"00002bec", +2814 => x"00002bec", +2815 => x"00002bf4", +2816 => x"00002bf4", +2817 => x"00002bfc", +2818 => x"00002bfc", +2819 => x"00002c04", +2820 => x"00002c04", +2821 => x"00002c0c", +2822 => x"00002c0c", +2823 => x"00002c14", +2824 => x"00002c14", +2825 => x"00002c1c", +2826 => x"00002c1c", +2827 => x"00002c24", +2828 => x"00002c24", +2829 => x"00002c2c", +2830 => x"00002c2c", +2831 => x"00002c34", +2832 => x"00002c34", +2833 => x"00002c3c", +2834 => x"00002c3c", +2835 => x"00002c44", +2836 => x"00002c44", +2837 => x"00002c4c", +2838 => x"00002c4c", +2839 => x"00002c54", +2840 => x"00002c54", +2841 => x"00002c5c", +2842 => x"00002c5c", +2843 => x"00002c64", +2844 => x"00002c64", +2845 => x"00002c6c", +2846 => x"00002c6c", +2847 => x"00002c74", +2848 => x"00002c74", +2849 => x"00002c7c", +2850 => x"00002c7c", +2851 => x"00002c84", +2852 => x"00002c84", +2853 => x"00002c8c", +2854 => x"00002c8c", +2855 => x"00002c94", +2856 => x"00002c94", +2857 => x"00002c9c", +2858 => x"00002c9c", +2859 => x"00002ca4", +2860 => x"00002ca4", +2861 => x"00002cac", +2862 => x"00002cac", +2863 => x"00002cb4", +2864 => x"00002cb4", +2865 => x"00002cbc", +2866 => x"00002cbc", +2867 => x"00002cc4", +2868 => x"00002cc4", +2869 => x"00002ccc", +2870 => x"00002ccc", +2871 => x"00002cd4", +2872 => x"00002cd4", +2873 => x"00002cdc", +2874 => x"00002cdc", +2875 => x"00002ce4", +2876 => x"00002ce4", +2877 => x"00002cec", +2878 => x"00002cec", +2879 => x"00002cf4", +2880 => x"00002cf4", +2881 => x"00002cfc", +2882 => x"00002cfc", +2883 => x"00002d04", +2884 => x"00002d04", +2885 => x"00002d0c", +2886 => x"00002d0c", +2887 => x"00002d14", +2888 => x"00002d14", +2889 => x"00002d1c", +2890 => x"00002d1c", +2891 => x"00002d24", +2892 => x"00002d24", +2893 => x"00002d2c", +2894 => x"00002d2c", +2895 => x"00002d34", +2896 => x"00002d34", +2897 => x"00002d3c", +2898 => x"00002d3c", +2899 => x"00002d44", +2900 => x"00002d44", +2901 => x"00002d4c", +2902 => x"00002d4c", +2903 => x"00002d54", +2904 => x"00002d54", +2905 => x"00002d5c", +2906 => x"00002d5c", +2907 => x"00002d64", +2908 => x"00002d64", +2909 => x"00002d6c", +2910 => x"00002d6c", +2911 => x"00002d74", +2912 => x"00002d74", +2913 => x"00002d7c", +2914 => x"00002d7c", +2915 => x"00002d84", +2916 => x"00002d84", +2917 => x"00002d8c", +2918 => x"00002d8c", +2919 => x"00002d94", +2920 => x"00002d94", +2921 => x"00002d9c", +2922 => x"00002d9c", +2923 => x"00002da4", +2924 => x"00002da4", +2925 => x"00002dac", +2926 => x"00002dac", +2927 => x"00002db4", +2928 => x"00002db4", +2929 => x"00002dbc", +2930 => x"00002dbc", +2931 => x"00002dc4", +2932 => x"00002dc4", +2933 => x"00002dcc", +2934 => x"00002dcc", +2935 => x"00002dd4", +2936 => x"00002dd4", +2937 => x"00002ddc", +2938 => x"00002ddc", +2939 => x"00002de4", +2940 => x"00002de4", +2941 => x"00002dec", +2942 => x"00002dec", +2943 => x"00002df4", +2944 => x"00002df4", +2945 => x"00002dfc", +2946 => x"00002dfc", +2947 => x"00002e04", +2948 => x"00002e04", +2949 => x"00002e0c", +2950 => x"00002e0c", +2951 => x"00002e14", +2952 => x"00002e14", +2953 => x"00002e1c", +2954 => x"00002e1c", +2955 => x"00002e24", +2956 => x"00002e24", +2957 => x"00002e2c", +2958 => x"00002e2c", +2959 => x"00002e34", +2960 => x"00002e34", +2961 => x"00002e3c", +2962 => x"00002e3c", +2963 => x"00002e44", +2964 => x"00002e44", +2965 => x"00002e4c", +2966 => x"00002e4c", +2967 => x"00002e54", +2968 => x"00002e54", +2969 => x"00002e5c", +2970 => x"00002e5c", +2971 => x"00002e64", +2972 => x"00002e64", +2973 => x"00002e6c", +2974 => x"00002e6c", +2975 => x"00002e74", +2976 => x"00002e74", +2977 => x"00002e7c", +2978 => x"00002e7c", +2979 => x"00002e84", +2980 => x"00002e84", +2981 => x"00002e8c", +2982 => x"00002e8c", +2983 => x"00002e94", +2984 => x"00002e94", +2985 => x"00002e9c", +2986 => x"00002e9c", +2987 => x"00002ea4", +2988 => x"00002ea4", +2989 => x"00002eac", +2990 => x"00002eac", +2991 => x"00002eb4", +2992 => x"00002eb4", +2993 => x"00002ebc", +2994 => x"00002ebc", +2995 => x"00002ec4", +2996 => x"00002ec4", +2997 => x"00002ecc", +2998 => x"00002ecc", +2999 => x"00002ed4", +3000 => x"00002ed4", +3001 => x"00002edc", +3002 => x"00002edc", +3003 => x"00002ee4", +3004 => x"00002ee4", +3005 => x"00002eec", +3006 => x"00002eec", +3007 => x"00002ef4", +3008 => x"00002ef4", +3009 => x"00002efc", +3010 => x"00002efc", +3011 => x"00002f04", +3012 => x"00002f04", +3013 => x"00002f0c", +3014 => x"00002f0c", +3015 => x"00002f14", +3016 => x"00002f14", +3017 => x"00002f1c", +3018 => x"00002f1c", +3019 => x"00002f24", +3020 => x"00002f24", +3021 => x"00002f2c", +3022 => x"00002f2c", +3023 => x"00002f34", +3024 => x"00002f34", +3025 => x"00002f3c", +3026 => x"00002f3c", +3027 => x"00002f50", +3028 => x"00000000", +3029 => x"000031b8", +3030 => x"00003214", +3031 => x"00003270", +3032 => x"00000000", +3033 => x"00000000", +3034 => x"00000000", +3035 => x"00000000", +3036 => x"00000000", +3037 => x"00000000", +3038 => x"00000000", +3039 => x"00000000", +3040 => x"00000000", +3041 => x"00002ad0", +3042 => x"00000000", +3043 => x"00000000", +3044 => x"00000000", +3045 => x"00000000", +3046 => x"00000000", +3047 => x"00000000", +3048 => x"00000000", +3049 => x"00000000", +3050 => x"00000000", +3051 => x"00000000", +3052 => x"00000000", +3053 => x"00000000", +3054 => x"00000000", +3055 => x"00000000", +3056 => x"00000000", +3057 => x"00000000", +3058 => x"00000000", +3059 => x"00000000", +3060 => x"00000000", +3061 => x"00000000", +3062 => x"00000000", +3063 => x"00000000", +3064 => x"00000000", +3065 => x"00000000", +3066 => x"00000000", +3067 => x"00000000", +3068 => x"00000000", +3069 => x"00000000", +3070 => x"00000001", +3071 => x"330eabcd", +3072 => x"1234e66d", +3073 => x"deec0005", +3074 => x"000b0000", +3075 => x"00000000", +3076 => x"00000000", +3077 => x"00000000", +3078 => x"00000000", +3079 => x"00000000", +3080 => x"00000000", +3081 => x"00000000", +3082 => x"00000000", +3083 => x"00000000", +3084 => x"00000000", +3085 => x"00000000", +3086 => x"00000000", +3087 => x"00000000", +3088 => x"00000000", +3089 => x"00000000", +3090 => x"00000000", +3091 => x"00000000", +3092 => x"00000000", +3093 => x"00000000", +3094 => x"00000000", +3095 => x"00000000", +3096 => x"00000000", +3097 => x"00000000", +3098 => x"00000000", +3099 => x"00000000", +3100 => x"00000000", +3101 => x"00000000", +3102 => x"00000000", +3103 => x"00000000", +3104 => x"00000000", +3105 => x"00000000", +3106 => x"00000000", +3107 => x"00000000", +3108 => x"00000000", +3109 => x"00000000", +3110 => x"00000000", +3111 => x"00000000", +3112 => x"00000000", +3113 => x"00000000", +3114 => x"00000000", +3115 => x"00000000", +3116 => x"00000000", +3117 => x"00000000", +3118 => x"00000000", +3119 => x"00000000", +3120 => x"00000000", +3121 => x"00000000", +3122 => x"00000000", +3123 => x"00000000", +3124 => x"00000000", +3125 => x"00000000", +3126 => x"00000000", +3127 => x"00000000", +3128 => x"00000000", +3129 => x"00000000", +3130 => x"00000000", +3131 => x"00000000", +3132 => x"00000000", +3133 => x"00000000", +3134 => x"00000000", +3135 => x"00000000", +3136 => x"00000000", +3137 => x"00000000", +3138 => x"00000000", +3139 => x"00000000", +3140 => x"00000000", +3141 => x"00000000", +3142 => x"00000000", +3143 => x"00000000", 3144 => x"00000000", 3145 => x"00000000", 3146 => x"00000000", -3147 => x"0000390c", -3148 => x"000004d2", -- iterations 0x4d2=1234 +3147 => x"00000000", +3148 => x"00000000", 3149 => x"00000000", 3150 => x"00000000", 3151 => x"00000000", @@ -3188,496 +3188,100 @@ shared variable ram : ram_type := 3159 => x"00000000", 3160 => x"00000000", 3161 => x"00000000", -3162 => x"ffffffff", +3162 => x"00000000", 3163 => x"00000000", -3164 => x"00020000", +3164 => x"00000000", 3165 => x"00000000", 3166 => x"00000000", -3167 => x"00003174", -3168 => x"00003174", -3169 => x"0000317c", -3170 => x"0000317c", -3171 => x"00003184", -3172 => x"00003184", -3173 => x"0000318c", -3174 => x"0000318c", -3175 => x"00003194", -3176 => x"00003194", -3177 => x"0000319c", -3178 => x"0000319c", -3179 => x"000031a4", -3180 => x"000031a4", -3181 => x"000031ac", -3182 => x"000031ac", -3183 => x"000031b4", -3184 => x"000031b4", -3185 => x"000031bc", -3186 => x"000031bc", -3187 => x"000031c4", -3188 => x"000031c4", -3189 => x"000031cc", -3190 => x"000031cc", -3191 => x"000031d4", -3192 => x"000031d4", -3193 => x"000031dc", -3194 => x"000031dc", -3195 => x"000031e4", -3196 => x"000031e4", -3197 => x"000031ec", -3198 => x"000031ec", -3199 => x"000031f4", -3200 => x"000031f4", -3201 => x"000031fc", -3202 => x"000031fc", -3203 => x"00003204", -3204 => x"00003204", -3205 => x"0000320c", -3206 => x"0000320c", -3207 => x"00003214", -3208 => x"00003214", -3209 => x"0000321c", -3210 => x"0000321c", -3211 => x"00003224", -3212 => x"00003224", -3213 => x"0000322c", -3214 => x"0000322c", -3215 => x"00003234", -3216 => x"00003234", -3217 => x"0000323c", -3218 => x"0000323c", -3219 => x"00003244", -3220 => x"00003244", -3221 => x"0000324c", -3222 => x"0000324c", -3223 => x"00003254", -3224 => x"00003254", -3225 => x"0000325c", -3226 => x"0000325c", -3227 => x"00003264", -3228 => x"00003264", -3229 => x"0000326c", -3230 => x"0000326c", -3231 => x"00003274", -3232 => x"00003274", -3233 => x"0000327c", -3234 => x"0000327c", -3235 => x"00003284", -3236 => x"00003284", -3237 => x"0000328c", -3238 => x"0000328c", -3239 => x"00003294", -3240 => x"00003294", -3241 => x"0000329c", -3242 => x"0000329c", -3243 => x"000032a4", -3244 => x"000032a4", -3245 => x"000032ac", -3246 => x"000032ac", -3247 => x"000032b4", -3248 => x"000032b4", -3249 => x"000032bc", -3250 => x"000032bc", -3251 => x"000032c4", -3252 => x"000032c4", -3253 => x"000032cc", -3254 => x"000032cc", -3255 => x"000032d4", -3256 => x"000032d4", -3257 => x"000032dc", -3258 => x"000032dc", -3259 => x"000032e4", -3260 => x"000032e4", -3261 => x"000032ec", -3262 => x"000032ec", -3263 => x"000032f4", -3264 => x"000032f4", -3265 => x"000032fc", -3266 => x"000032fc", -3267 => x"00003304", -3268 => x"00003304", -3269 => x"0000330c", -3270 => x"0000330c", -3271 => x"00003314", -3272 => x"00003314", -3273 => x"0000331c", -3274 => x"0000331c", -3275 => x"00003324", -3276 => x"00003324", -3277 => x"0000332c", -3278 => x"0000332c", -3279 => x"00003334", -3280 => x"00003334", -3281 => x"0000333c", -3282 => x"0000333c", -3283 => x"00003344", -3284 => x"00003344", -3285 => x"0000334c", -3286 => x"0000334c", -3287 => x"00003354", -3288 => x"00003354", -3289 => x"0000335c", -3290 => x"0000335c", -3291 => x"00003364", -3292 => x"00003364", -3293 => x"0000336c", -3294 => x"0000336c", -3295 => x"00003374", -3296 => x"00003374", -3297 => x"0000337c", -3298 => x"0000337c", -3299 => x"00003384", -3300 => x"00003384", -3301 => x"0000338c", -3302 => x"0000338c", -3303 => x"00003394", -3304 => x"00003394", -3305 => x"0000339c", -3306 => x"0000339c", -3307 => x"000033a4", -3308 => x"000033a4", -3309 => x"000033ac", -3310 => x"000033ac", -3311 => x"000033b4", -3312 => x"000033b4", -3313 => x"000033bc", -3314 => x"000033bc", -3315 => x"000033c4", -3316 => x"000033c4", -3317 => x"000033cc", -3318 => x"000033cc", -3319 => x"000033d4", -3320 => x"000033d4", -3321 => x"000033dc", -3322 => x"000033dc", -3323 => x"000033e4", -3324 => x"000033e4", -3325 => x"000033ec", -3326 => x"000033ec", -3327 => x"000033f4", -3328 => x"000033f4", -3329 => x"000033fc", -3330 => x"000033fc", -3331 => x"00003404", -3332 => x"00003404", -3333 => x"0000340c", -3334 => x"0000340c", -3335 => x"00003414", -3336 => x"00003414", -3337 => x"0000341c", -3338 => x"0000341c", -3339 => x"00003424", -3340 => x"00003424", -3341 => x"0000342c", -3342 => x"0000342c", -3343 => x"00003434", -3344 => x"00003434", -3345 => x"0000343c", -3346 => x"0000343c", -3347 => x"00003444", -3348 => x"00003444", -3349 => x"0000344c", -3350 => x"0000344c", -3351 => x"00003454", -3352 => x"00003454", -3353 => x"0000345c", -3354 => x"0000345c", -3355 => x"00003464", -3356 => x"00003464", -3357 => x"0000346c", -3358 => x"0000346c", -3359 => x"00003474", -3360 => x"00003474", -3361 => x"0000347c", -3362 => x"0000347c", -3363 => x"00003484", -3364 => x"00003484", -3365 => x"0000348c", -3366 => x"0000348c", -3367 => x"00003494", -3368 => x"00003494", -3369 => x"0000349c", -3370 => x"0000349c", -3371 => x"000034a4", -3372 => x"000034a4", -3373 => x"000034ac", -3374 => x"000034ac", -3375 => x"000034b4", -3376 => x"000034b4", -3377 => x"000034bc", -3378 => x"000034bc", -3379 => x"000034c4", -3380 => x"000034c4", -3381 => x"000034cc", -3382 => x"000034cc", -3383 => x"000034d4", -3384 => x"000034d4", -3385 => x"000034dc", -3386 => x"000034dc", -3387 => x"000034e4", -3388 => x"000034e4", -3389 => x"000034ec", -3390 => x"000034ec", -3391 => x"000034f4", -3392 => x"000034f4", -3393 => x"000034fc", -3394 => x"000034fc", -3395 => x"00003504", -3396 => x"00003504", -3397 => x"0000350c", -3398 => x"0000350c", -3399 => x"00003514", -3400 => x"00003514", -3401 => x"0000351c", -3402 => x"0000351c", -3403 => x"00003524", -3404 => x"00003524", -3405 => x"0000352c", -3406 => x"0000352c", -3407 => x"00003534", -3408 => x"00003534", -3409 => x"0000353c", -3410 => x"0000353c", -3411 => x"00003544", -3412 => x"00003544", -3413 => x"0000354c", -3414 => x"0000354c", -3415 => x"00003554", -3416 => x"00003554", -3417 => x"0000355c", -3418 => x"0000355c", -3419 => x"00003564", -3420 => x"00003564", -3421 => x"0000356c", -3422 => x"0000356c", -3423 => x"00003580", -3424 => x"00000000", -3425 => x"000037e8", -3426 => x"00003844", -3427 => x"000038a0", -3428 => x"00000000", -3429 => x"00000000", -3430 => x"00000000", -3431 => x"00000000", -3432 => x"00000000", -3433 => x"00000000", -3434 => x"00000000", -3435 => x"00000000", -3436 => x"00000000", -3437 => x"00003100", -3438 => x"00000000", -3439 => x"00000000", -3440 => x"00000000", -3441 => x"00000000", -3442 => x"00000000", -3443 => x"00000000", -3444 => x"00000000", -3445 => x"00000000", -3446 => x"00000000", -3447 => x"00000000", -3448 => x"00000000", -3449 => x"00000000", -3450 => x"00000000", -3451 => x"00000000", -3452 => x"00000000", -3453 => x"00000000", -3454 => x"00000000", -3455 => x"00000000", -3456 => x"00000000", -3457 => x"00000000", -3458 => x"00000000", -3459 => x"00000000", -3460 => x"00000000", -3461 => x"00000000", -3462 => x"00000000", -3463 => x"00000000", -3464 => x"00000000", -3465 => x"00000000", -3466 => x"00000001", -3467 => x"330eabcd", -3468 => x"1234e66d", -3469 => x"deec0005", -3470 => x"000b0000", -3471 => x"00000000", -3472 => x"00000000", -3473 => x"00000000", -3474 => x"00000000", -3475 => x"00000000", -3476 => x"00000000", -3477 => x"00000000", -3478 => x"00000000", -3479 => x"00000000", -3480 => x"00000000", -3481 => x"00000000", -3482 => x"00000000", -3483 => x"00000000", -3484 => x"00000000", -3485 => x"00000000", -3486 => x"00000000", -3487 => x"00000000", -3488 => x"00000000", -3489 => x"00000000", -3490 => x"00000000", -3491 => x"00000000", -3492 => x"00000000", -3493 => x"00000000", -3494 => x"00000000", -3495 => x"00000000", -3496 => x"00000000", -3497 => x"00000000", -3498 => x"00000000", -3499 => x"00000000", -3500 => x"00000000", -3501 => x"00000000", -3502 => x"00000000", -3503 => x"00000000", -3504 => x"00000000", -3505 => x"00000000", -3506 => x"00000000", -3507 => x"00000000", -3508 => x"00000000", -3509 => x"00000000", -3510 => x"00000000", -3511 => x"00000000", -3512 => x"00000000", -3513 => x"00000000", -3514 => x"00000000", -3515 => x"00000000", -3516 => x"00000000", -3517 => x"00000000", -3518 => x"00000000", -3519 => x"00000000", -3520 => x"00000000", -3521 => x"00000000", -3522 => x"00000000", -3523 => x"00000000", -3524 => x"00000000", -3525 => x"00000000", -3526 => x"00000000", -3527 => x"00000000", -3528 => x"00000000", -3529 => x"00000000", -3530 => x"00000000", -3531 => x"00000000", -3532 => x"00000000", -3533 => x"00000000", -3534 => x"00000000", -3535 => x"00000000", -3536 => x"00000000", -3537 => x"00000000", -3538 => x"00000000", -3539 => x"00000000", -3540 => x"00000000", -3541 => x"00000000", -3542 => x"00000000", -3543 => x"00000000", -3544 => x"00000000", -3545 => x"00000000", -3546 => x"00000000", -3547 => x"00000000", -3548 => x"00000000", -3549 => x"00000000", -3550 => x"00000000", -3551 => x"00000000", -3552 => x"00000000", -3553 => x"00000000", -3554 => x"00000000", -3555 => x"00000000", -3556 => x"00000000", -3557 => x"00000000", -3558 => x"00000000", -3559 => x"00000000", -3560 => x"00000000", -3561 => x"00000000", -3562 => x"00000000", -3563 => x"00000000", -3564 => x"00000000", -3565 => x"00000000", -3566 => x"00000000", -3567 => x"00000000", -3568 => x"00000000", -3569 => x"00000000", -3570 => x"00000000", -3571 => x"00000000", -3572 => x"00000000", -3573 => x"00000000", -3574 => x"00000000", -3575 => x"00000000", -3576 => x"00000000", -3577 => x"00000000", -3578 => x"00000000", -3579 => x"00000000", -3580 => x"00000000", -3581 => x"00000000", -3582 => x"00000000", -3583 => x"00000000", -3584 => x"00000000", -3585 => x"00000000", -3586 => x"00000000", -3587 => x"00000000", -3588 => x"00000000", -3589 => x"00000000", -3590 => x"00000000", -3591 => x"00000000", -3592 => x"00000000", -3593 => x"00000000", -3594 => x"00000000", -3595 => x"00000000", -3596 => x"00000000", -3597 => x"00000000", -3598 => x"00000000", -3599 => x"00000000", -3600 => x"00000000", -3601 => x"00000000", -3602 => x"00000000", -3603 => x"00000000", -3604 => x"00000000", -3605 => x"00000000", -3606 => x"00000000", -3607 => x"00000000", -3608 => x"00000000", -3609 => x"00000000", -3610 => x"00000000", -3611 => x"00000000", -3612 => x"00000000", -3613 => x"00000000", -3614 => x"00000000", -3615 => x"00000000", -3616 => x"00000000", -3617 => x"00000000", -3618 => x"00000000", -3619 => x"00000000", -3620 => x"00000000", -3621 => x"00000000", -3622 => x"00000000", -3623 => x"00000000", -3624 => x"00000000", -3625 => x"00000000", -3626 => x"00000000", -3627 => x"00000000", -3628 => x"00000000", -3629 => x"00000000", -3630 => x"00000000", -3631 => x"00000000", -3632 => x"00000000", -3633 => x"00000000", -3634 => x"00000000", -3635 => x"00000000", -3636 => x"00000000", -3637 => x"00000000", -3638 => x"00000000", -3639 => x"00000000", -3640 => x"00000000", -3641 => x"00000000", -3642 => x"00000000", -3643 => x"00000000", -3644 => x"00000000", -3645 => x"00000000", -3646 => x"00000000", -3647 => x"00003104", -3648 => x"ffffffff", -3649 => x"00000000", -3650 => x"ffffffff", -3651 => x"00000000", +3167 => x"00000000", +3168 => x"00000000", +3169 => x"00000000", +3170 => x"00000000", +3171 => x"00000000", +3172 => x"00000000", +3173 => x"00000000", +3174 => x"00000000", +3175 => x"00000000", +3176 => x"00000000", +3177 => x"00000000", +3178 => x"00000000", +3179 => x"00000000", +3180 => x"00000000", +3181 => x"00000000", +3182 => x"00000000", +3183 => x"00000000", +3184 => x"00000000", +3185 => x"00000000", +3186 => x"00000000", +3187 => x"00000000", +3188 => x"00000000", +3189 => x"00000000", +3190 => x"00000000", +3191 => x"00000000", +3192 => x"00000000", +3193 => x"00000000", +3194 => x"00000000", +3195 => x"00000000", +3196 => x"00000000", +3197 => x"00000000", +3198 => x"00000000", +3199 => x"00000000", +3200 => x"00000000", +3201 => x"00000000", +3202 => x"00000000", +3203 => x"00000000", +3204 => x"00000000", +3205 => x"00000000", +3206 => x"00000000", +3207 => x"00000000", +3208 => x"00000000", +3209 => x"00000000", +3210 => x"00000000", +3211 => x"00000000", +3212 => x"00000000", +3213 => x"00000000", +3214 => x"00000000", +3215 => x"00000000", +3216 => x"00000000", +3217 => x"00000000", +3218 => x"00000000", +3219 => x"00000000", +3220 => x"00000000", +3221 => x"00000000", +3222 => x"00000000", +3223 => x"00000000", +3224 => x"00000000", +3225 => x"00000000", +3226 => x"00000000", +3227 => x"00000000", +3228 => x"00000000", +3229 => x"00000000", +3230 => x"00000000", +3231 => x"00000000", +3232 => x"00000000", +3233 => x"00000000", +3234 => x"00000000", +3235 => x"00000000", +3236 => x"00000000", +3237 => x"00000000", +3238 => x"00000000", +3239 => x"00000000", +3240 => x"00000000", +3241 => x"00000000", +3242 => x"00000000", +3243 => x"00000000", +3244 => x"00000000", +3245 => x"00000000", +3246 => x"00000000", +3247 => x"00000000", +3248 => x"00000000", +3249 => x"00000000", +3250 => x"00000000", +3251 => x"00002ad4", +3252 => x"ffffffff", +3253 => x"00000000", +3254 => x"ffffffff", +3255 => x"00000000", others => x"00000000" ); @@ -3692,7 +3296,9 @@ begin if (mem_writeEnable = '1') then ram(conv_integer(mem_addr(maxAddrBit downto minAddrBit))) := mem_write; end if; + if (mem_readEnable = '1') then mem_read <= ram(conv_integer(mem_addr(maxAddrBit downto minAddrBit))); + end if; end if; end process; diff --git a/zpu/hdl/zpu4/src/fastdmips.do b/zpu/hdl/zpu4/src/fastdmips.do deleted file mode 100644 index 504bf60..0000000 --- a/zpu/hdl/zpu4/src/fastdmips.do +++ /dev/null @@ -1,19 +0,0 @@ -set BreakOnAssertion 1 -vlib work - -vcom -93 -explicit zpu_config_fastsim.vhd -vcom -93 -explicit zpupkg.vhd -vcom -93 -explicit txt_util.vhd -vcom -93 -explicit sim_fpga_top.vhd -vcom -93 -explicit zpu_core.vhd -vcom -93 -explicit dram_dmips.vhd -vcom -93 -explicit timer.vhd -vcom -93 -explicit io.vhd -vcom -93 -explicit trace.vhd - - -vsim fpga_top -view wave - -# run ZPU -run 60000 ms diff --git a/zpu/hdl/zpu4/src/fastdmipsintstack.do b/zpu/hdl/zpu4/src/fastdmipsintstack.do deleted file mode 100644 index ee9571e..0000000 --- a/zpu/hdl/zpu4/src/fastdmipsintstack.do +++ /dev/null @@ -1,19 +0,0 @@ -set BreakOnAssertion 1 -vlib work - -vcom -93 -explicit zpu_config_fastsim.vhd -vcom -93 -explicit zpupkg.vhd -vcom -93 -explicit txt_util.vhd -vcom -93 -explicit sim_fpga_top.vhd -vcom -93 -explicit zpu_core_intstack.vhd -vcom -93 -explicit dram_dmips.vhd -vcom -93 -explicit timer.vhd -vcom -93 -explicit io.vhd -vcom -93 -explicit trace.vhd - - -vsim fpga_top -view wave - -# run ZPU -run 60000 ms diff --git a/zpu/hdl/zpu4/src/fastdmipssmall.do b/zpu/hdl/zpu4/src/fastdmipssmall.do deleted file mode 100644 index 3eaa083..0000000 --- a/zpu/hdl/zpu4/src/fastdmipssmall.do +++ /dev/null @@ -1,21 +0,0 @@ -set BreakOnAssertion 1 -vlib work - - -vcom -93 -explicit zpu_config_trace.vhd -vcom -93 -explicit zpupkg.vhd -vcom -93 -explicit txt_util.vhd -vcom -93 -explicit sim_fpga_top.vhd -vcom -93 -explicit zpu_core_small.vhd -vcom -93 -explicit bram_dmips.vhd -vcom -93 -explicit dram_dmips.vhd -vcom -93 -explicit timer.vhd -vcom -93 -explicit io.vhd -vcom -93 -explicit trace.vhd - - -vsim fpga_top -view wave - -# run ZPU -run 60000 ms diff --git a/zpu/hdl/zpu4/src/fasthello.do b/zpu/hdl/zpu4/src/fasthello.do deleted file mode 100644 index d49aeab..0000000 --- a/zpu/hdl/zpu4/src/fasthello.do +++ /dev/null @@ -1,19 +0,0 @@ -set BreakOnAssertion 1 -vlib work - -vcom -93 -explicit zpu_config_fastsim.vhd -vcom -93 -explicit zpupkg.vhd -vcom -93 -explicit txt_util.vhd -vcom -93 -explicit sim_fpga_top.vhd -vcom -93 -explicit zpu_core.vhd -vcom -93 -explicit dram_hello.vhd -vcom -93 -explicit timer.vhd -vcom -93 -explicit io.vhd -vcom -93 -explicit trace.vhd - - -vsim fpga_top -view wave - -# run ZPU -run 60000 ms diff --git a/zpu/hdl/zpu4/src/fastsimzpu.do b/zpu/hdl/zpu4/src/fastsimzpu.do deleted file mode 100644 index 504bf60..0000000 --- a/zpu/hdl/zpu4/src/fastsimzpu.do +++ /dev/null @@ -1,19 +0,0 @@ -set BreakOnAssertion 1 -vlib work - -vcom -93 -explicit zpu_config_fastsim.vhd -vcom -93 -explicit zpupkg.vhd -vcom -93 -explicit txt_util.vhd -vcom -93 -explicit sim_fpga_top.vhd -vcom -93 -explicit zpu_core.vhd -vcom -93 -explicit dram_dmips.vhd -vcom -93 -explicit timer.vhd -vcom -93 -explicit io.vhd -vcom -93 -explicit trace.vhd - - -vsim fpga_top -view wave - -# run ZPU -run 60000 ms diff --git a/zpu/hdl/zpu4/src/log.txt b/zpu/hdl/zpu4/src/log.txt index 10f0eaa..47b8a65 100644 --- a/zpu/hdl/zpu4/src/log.txt +++ b/zpu/hdl/zpu4/src/log.txt @@ -1,305 +1,156 @@ -H -e -l -l -o - -w -o -r -l -d - -1 - - - -H -e -l -l -o - -w -o +D +h r -l -d - -2 - - - - - - -H -e -l -l +y +s +t o - -w -o -r -l -d - -1 - - - - - - -H +n e -l -l -o -w -o -r -l -d - -2 - - - - - - -H +B e -l -l -o - -w -o +n +c +h +m +a r -l -d +k +, -1 - - - - - - -H +V e -l -l -o - -w -o r -l -d - -2 - - - - - - -H -e -l -l +s +i o +n -w -o -r -l -d - +2 +. 1 - - - - - - -H -e -l -l -o -w -o -r -l -d - -2 - - - - - - -H +( +L +a +n +g +u +a +g e -l -l -o - -w -o -r -l -d +: -1 +C +) -H -e -l -l -o - -w -o +P r -l -d - -2 - - - - - - -H -e -l -l o +g +r +a +m -w +c o -r +m +p +i l -d - -1 - - - - - - -H e -l -l -o +d w +i +t +h o -r -l -d +u +t -2 - - - - - - -H +' +r +e +g +i +s +t e -l -l -o - -w -o r -l -d +' -1 +a +t +t +r +i +b +u +t +e -H +E +x e -l -l +c +u +t +i o +n -w -o +s +t +a r -l -d +t +s +, -2 - - - - - - -H -e -l -l -o +5 +0 +0 +0 +0 -w -o r -l -d +u +n +s -1 - - - - - - -H -e -l -l +t +h +r o +u +g +h -w -o +D +h r -l -d - -2 - - - +y +s +t +o +n +e -H + diff --git a/zpu/hdl/zpu4/src/zpu_config_fastsim.vhd b/zpu/hdl/zpu4/src/zpu_config_fastsim.vhd deleted file mode 100644 index d39c9e9..0000000 --- a/zpu/hdl/zpu4/src/zpu_config_fastsim.vhd +++ /dev/null @@ -1,15 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -package zpu_config is - - constant Generate_Trace : boolean := false; - constant wordPower : integer := 5; - -- during simulation, set this to '0' to get matching trace.txt - constant DontCareValue : std_logic := '0'; - -- Clock frequency in MHz. - constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"50"; -- 80MHz - constant maxAddrBitIncIO : integer := 15; - -end zpu_config; diff --git a/zpu/hdl/zpu4/test/dmips/build.sh b/zpu/hdl/zpu4/test/dmips/build.sh index 161c748..44ead41 100644 --- a/zpu/hdl/zpu4/test/dmips/build.sh +++ b/zpu/hdl/zpu4/test/dmips/build.sh @@ -1,4 +1,4 @@ -zpu-elf-gcc -DTIME $ZPUDIR/dhrystone/dhry_*.c -O3 -Wl,--gc-sections -Wl,--relax -abel -o dmips.elf +zpu-elf-gcc -DTIME ../../../../../../roadshow/dhrystone/dhry_*.c -O3 -Wl,--gc-sections -Wl,--relax -phi -o dmips.elf zpu-elf-objdump --disassemble-all >dmips.dis dmips.elf zpu-elf-objcopy -O binary dmips.elf dmips.bin java -classpath ../../../../sw/simulator/zpusim.jar com.zylin.zpu.simulator.tools.MakeRam dmips.bin >dmips.ram diff --git a/zpu/hdl/zpu4/test/dmips/dmips.bin b/zpu/hdl/zpu4/test/dmips/dmips.bin index 1330fe3..ee1a6fe 100644 Binary files a/zpu/hdl/zpu4/test/dmips/dmips.bin and b/zpu/hdl/zpu4/test/dmips/dmips.bin differ diff --git a/zpu/hdl/zpu4/test/dmips/dmips.elf b/zpu/hdl/zpu4/test/dmips/dmips.elf index 7254a5d..3a04a5b 100644 Binary files a/zpu/hdl/zpu4/test/dmips/dmips.elf and b/zpu/hdl/zpu4/test/dmips/dmips.elf differ diff --git a/zpu/hdl/zpu4/test/dmips/dmips.ram b/zpu/hdl/zpu4/test/dmips/dmips.ram index 89047d5..0919ce1 100644 --- a/zpu/hdl/zpu4/test/dmips/dmips.ram +++ b/zpu/hdl/zpu4/test/dmips/dmips.ram @@ -1,14 +1,14 @@ 0 => x"0b0b0b0b", -1 => x"80700b0b", -2 => x"80e2a40c", +1 => x"82700b0b", +2 => x"80d5f40c", 3 => x"3a0b0b80", -4 => x"c6fc0400", +4 => x"c4fb0400", 5 => x"00000000", 6 => x"00000000", 7 => x"00000000", 8 => x"80088408", 9 => x"88080b0b", -10 => x"80c7c32d", +10 => x"80c5c22d", 11 => x"880c840c", 12 => x"800c0400", 13 => x"00000000", @@ -71,7 +71,7 @@ 70 => x"00000000", 71 => x"00000000", 72 => x"0b0b0b88", -73 => x"c4040000", +73 => x"c3040000", 74 => x"00000000", 75 => x"00000000", 76 => x"00000000", @@ -88,7 +88,7 @@ 87 => x"00000000", 88 => x"72729f06", 89 => x"0981050b", -90 => x"0b0b88a7", +90 => x"0b0b88a6", 91 => x"05040000", 92 => x"00000000", 93 => x"00000000", @@ -159,25 +159,25 @@ 158 => x"00000000", 159 => x"00000000", 160 => x"71fc0608", -161 => x"0b0b80e2", -162 => x"90738306", +161 => x"0b0b80d5", +162 => x"e0738306", 163 => x"10100508", 164 => x"060b0b0b", -165 => x"88aa0400", +165 => x"88a90400", 166 => x"00000000", 167 => x"00000000", 168 => x"80088408", 169 => x"88087575", -170 => x"0b0b0baf", -171 => x"ac2d5050", +170 => x"0b0b0bad", +171 => x"aa2d5050", 172 => x"80085688", 173 => x"0c840c80", 174 => x"0c510400", 175 => x"00000000", 176 => x"80088408", 177 => x"88087575", -178 => x"0b0b0baf", -179 => x"f02d5050", +178 => x"0b0b0bad", +179 => x"ee2d5050", 180 => x"80085688", 181 => x"0c840c80", 182 => x"0c510400", @@ -207,7 +207,7 @@ 206 => x"00000000", 207 => x"00000000", 208 => x"810b0b0b", -209 => x"80e2a00c", +209 => x"80d5f00c", 210 => x"51040000", 211 => x"00000000", 212 => x"00000000", @@ -254,8 +254,8 @@ 253 => x"00000000", 254 => x"00000000", 255 => x"00000000", -256 => x"83d93f80", -257 => x"cbcf3f04", +256 => x"82fd3fbf", +257 => x"a03f0410", 258 => x"10101010", 259 => x"10101010", 260 => x"10101010", @@ -263,2890 +263,2890 @@ 262 => x"10101010", 263 => x"10101010", 264 => x"10101010", -265 => x"10101053", -266 => x"51047381", -267 => x"ff067383", -268 => x"06098105", -269 => x"83051010", -270 => x"102b0772", -271 => x"fc060c51", -272 => x"51043c04", -273 => x"72728072", -274 => x"8106ff05", -275 => x"09720605", -276 => x"71105272", -277 => x"0a100a53", -278 => x"72ed3851", -279 => x"51535104", -280 => x"ff3d0d0b", -281 => x"0b80f294", -282 => x"08528412", -283 => x"08708106", -284 => x"515170f6", -285 => x"38710881", -286 => x"ff06800c", +265 => x"10105351", +266 => x"047381ff", +267 => x"06738306", +268 => x"09810583", +269 => x"05101010", +270 => x"2b0772fc", +271 => x"060c5151", +272 => x"043c0472", +273 => x"72807281", +274 => x"06ff0509", +275 => x"72060571", +276 => x"1052720a", +277 => x"100a5372", +278 => x"ed385151", +279 => x"535104ff", +280 => x"3d0d0b0b", +281 => x"80e5e408", +282 => x"52710870", +283 => x"882a8132", +284 => x"70810651", +285 => x"515170f1", +286 => x"3873720c", 287 => x"833d0d04", -288 => x"ff3d0d0b", -289 => x"0b80f294", -290 => x"08528412", -291 => x"08700a10", -292 => x"0a708106", -293 => x"51515170", -294 => x"f1387372", -295 => x"0c833d0d", -296 => x"0480e2a0", -297 => x"08802ea8", -298 => x"38838080", -299 => x"0b0b0b80", -300 => x"f2940c82", -301 => x"a0800b0b", -302 => x"0b80f298", -303 => x"0c829080", -304 => x"0b80f2a8", -305 => x"0c0b0b80", -306 => x"f29c0b80", -307 => x"f2ac0c04", -308 => x"f8808080", -309 => x"a40b0b0b", -310 => x"80f2940c", -311 => x"f8808082", -312 => x"800b0b0b", -313 => x"80f2980c", -314 => x"f8808084", -315 => x"800b80f2", -316 => x"a80cf880", -317 => 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x"00000001", +3071 => x"330eabcd", +3072 => x"1234e66d", +3073 => x"deec0005", +3074 => x"000b0000", +3075 => x"00000000", +3076 => x"00000000", +3077 => x"00000000", +3078 => x"00000000", +3079 => x"00000000", +3080 => x"00000000", +3081 => x"00000000", +3082 => x"00000000", +3083 => x"00000000", +3084 => x"00000000", +3085 => x"00000000", +3086 => x"00000000", +3087 => x"00000000", +3088 => x"00000000", +3089 => x"00000000", +3090 => x"00000000", +3091 => x"00000000", +3092 => x"00000000", +3093 => x"00000000", +3094 => x"00000000", +3095 => x"00000000", +3096 => x"00000000", +3097 => x"00000000", +3098 => x"00000000", +3099 => x"00000000", +3100 => x"00000000", +3101 => x"00000000", +3102 => x"00000000", +3103 => x"00000000", +3104 => x"00000000", +3105 => x"00000000", +3106 => x"00000000", +3107 => x"00000000", +3108 => x"00000000", +3109 => x"00000000", +3110 => x"00000000", +3111 => x"00000000", +3112 => x"00000000", +3113 => x"00000000", +3114 => x"00000000", +3115 => x"00000000", +3116 => x"00000000", +3117 => x"00000000", +3118 => x"00000000", +3119 => x"00000000", +3120 => x"00000000", +3121 => x"00000000", +3122 => x"00000000", +3123 => x"00000000", +3124 => x"00000000", +3125 => x"00000000", +3126 => x"00000000", +3127 => x"00000000", +3128 => x"00000000", +3129 => x"00000000", +3130 => x"00000000", +3131 => x"00000000", +3132 => x"00000000", +3133 => x"00000000", +3134 => x"00000000", +3135 => x"00000000", +3136 => x"00000000", +3137 => x"00000000", +3138 => x"00000000", +3139 => x"00000000", +3140 => x"00000000", +3141 => x"00000000", +3142 => x"00000000", +3143 => x"00000000", 3144 => x"00000000", 3145 => x"00000000", 3146 => x"00000000", -3147 => x"0000390c", -3148 => x"000004d2", +3147 => x"00000000", +3148 => x"00000000", 3149 => x"00000000", 3150 => x"00000000", 3151 => x"00000000", @@ -3160,493 +3160,97 @@ 3159 => x"00000000", 3160 => x"00000000", 3161 => x"00000000", -3162 => x"ffffffff", +3162 => x"00000000", 3163 => x"00000000", -3164 => x"00020000", +3164 => x"00000000", 3165 => x"00000000", 3166 => x"00000000", -3167 => x"00003174", -3168 => x"00003174", -3169 => x"0000317c", -3170 => x"0000317c", -3171 => x"00003184", -3172 => x"00003184", -3173 => x"0000318c", -3174 => x"0000318c", -3175 => x"00003194", -3176 => x"00003194", -3177 => x"0000319c", -3178 => x"0000319c", -3179 => x"000031a4", -3180 => x"000031a4", -3181 => x"000031ac", -3182 => x"000031ac", -3183 => x"000031b4", -3184 => x"000031b4", -3185 => x"000031bc", -3186 => x"000031bc", -3187 => x"000031c4", -3188 => x"000031c4", -3189 => x"000031cc", -3190 => x"000031cc", -3191 => x"000031d4", -3192 => x"000031d4", -3193 => x"000031dc", -3194 => x"000031dc", -3195 => x"000031e4", -3196 => x"000031e4", -3197 => x"000031ec", -3198 => x"000031ec", -3199 => x"000031f4", -3200 => x"000031f4", -3201 => x"000031fc", -3202 => x"000031fc", -3203 => x"00003204", -3204 => x"00003204", -3205 => x"0000320c", -3206 => x"0000320c", -3207 => x"00003214", -3208 => x"00003214", -3209 => x"0000321c", -3210 => x"0000321c", -3211 => x"00003224", -3212 => x"00003224", -3213 => x"0000322c", -3214 => x"0000322c", -3215 => x"00003234", -3216 => x"00003234", -3217 => x"0000323c", -3218 => x"0000323c", -3219 => x"00003244", -3220 => x"00003244", -3221 => x"0000324c", -3222 => x"0000324c", -3223 => x"00003254", -3224 => x"00003254", -3225 => x"0000325c", -3226 => x"0000325c", -3227 => x"00003264", -3228 => x"00003264", -3229 => x"0000326c", -3230 => x"0000326c", -3231 => x"00003274", -3232 => x"00003274", -3233 => x"0000327c", -3234 => x"0000327c", -3235 => x"00003284", -3236 => x"00003284", -3237 => x"0000328c", -3238 => x"0000328c", -3239 => x"00003294", -3240 => x"00003294", -3241 => x"0000329c", -3242 => x"0000329c", -3243 => x"000032a4", -3244 => x"000032a4", -3245 => x"000032ac", -3246 => x"000032ac", -3247 => x"000032b4", -3248 => x"000032b4", -3249 => x"000032bc", -3250 => x"000032bc", -3251 => x"000032c4", -3252 => x"000032c4", -3253 => x"000032cc", -3254 => x"000032cc", -3255 => x"000032d4", -3256 => x"000032d4", -3257 => x"000032dc", -3258 => x"000032dc", -3259 => x"000032e4", -3260 => x"000032e4", -3261 => x"000032ec", -3262 => x"000032ec", -3263 => x"000032f4", -3264 => x"000032f4", -3265 => x"000032fc", -3266 => x"000032fc", -3267 => x"00003304", -3268 => x"00003304", -3269 => x"0000330c", -3270 => x"0000330c", -3271 => x"00003314", -3272 => x"00003314", -3273 => x"0000331c", -3274 => x"0000331c", -3275 => x"00003324", -3276 => x"00003324", -3277 => x"0000332c", -3278 => x"0000332c", -3279 => x"00003334", -3280 => x"00003334", -3281 => x"0000333c", -3282 => x"0000333c", -3283 => x"00003344", -3284 => x"00003344", -3285 => x"0000334c", -3286 => x"0000334c", -3287 => x"00003354", -3288 => x"00003354", -3289 => x"0000335c", -3290 => x"0000335c", -3291 => x"00003364", -3292 => x"00003364", -3293 => x"0000336c", -3294 => x"0000336c", -3295 => x"00003374", -3296 => x"00003374", -3297 => x"0000337c", -3298 => x"0000337c", -3299 => x"00003384", -3300 => x"00003384", -3301 => x"0000338c", -3302 => x"0000338c", -3303 => x"00003394", -3304 => x"00003394", -3305 => x"0000339c", -3306 => x"0000339c", -3307 => x"000033a4", -3308 => x"000033a4", -3309 => x"000033ac", -3310 => x"000033ac", -3311 => x"000033b4", -3312 => x"000033b4", -3313 => x"000033bc", -3314 => x"000033bc", -3315 => x"000033c4", -3316 => x"000033c4", -3317 => x"000033cc", -3318 => x"000033cc", -3319 => x"000033d4", -3320 => x"000033d4", -3321 => x"000033dc", -3322 => x"000033dc", -3323 => x"000033e4", -3324 => x"000033e4", -3325 => x"000033ec", -3326 => x"000033ec", -3327 => x"000033f4", -3328 => x"000033f4", -3329 => x"000033fc", -3330 => x"000033fc", -3331 => x"00003404", -3332 => x"00003404", -3333 => x"0000340c", -3334 => x"0000340c", -3335 => x"00003414", -3336 => x"00003414", -3337 => x"0000341c", -3338 => x"0000341c", -3339 => x"00003424", -3340 => x"00003424", -3341 => x"0000342c", -3342 => x"0000342c", -3343 => x"00003434", -3344 => x"00003434", -3345 => x"0000343c", -3346 => x"0000343c", -3347 => x"00003444", -3348 => x"00003444", -3349 => x"0000344c", -3350 => x"0000344c", -3351 => x"00003454", -3352 => x"00003454", -3353 => x"0000345c", -3354 => x"0000345c", -3355 => x"00003464", -3356 => x"00003464", -3357 => x"0000346c", -3358 => x"0000346c", -3359 => x"00003474", -3360 => x"00003474", -3361 => x"0000347c", -3362 => x"0000347c", -3363 => x"00003484", -3364 => x"00003484", -3365 => x"0000348c", -3366 => x"0000348c", -3367 => x"00003494", -3368 => x"00003494", -3369 => x"0000349c", -3370 => x"0000349c", -3371 => x"000034a4", -3372 => x"000034a4", -3373 => x"000034ac", -3374 => x"000034ac", -3375 => x"000034b4", -3376 => x"000034b4", -3377 => x"000034bc", -3378 => x"000034bc", -3379 => x"000034c4", -3380 => x"000034c4", -3381 => x"000034cc", -3382 => x"000034cc", -3383 => x"000034d4", -3384 => x"000034d4", -3385 => x"000034dc", -3386 => x"000034dc", -3387 => x"000034e4", -3388 => x"000034e4", -3389 => x"000034ec", -3390 => x"000034ec", -3391 => x"000034f4", -3392 => x"000034f4", -3393 => x"000034fc", -3394 => x"000034fc", -3395 => x"00003504", -3396 => x"00003504", -3397 => x"0000350c", -3398 => x"0000350c", -3399 => x"00003514", -3400 => x"00003514", -3401 => x"0000351c", -3402 => x"0000351c", -3403 => x"00003524", -3404 => x"00003524", -3405 => x"0000352c", -3406 => x"0000352c", -3407 => x"00003534", -3408 => x"00003534", -3409 => x"0000353c", -3410 => x"0000353c", -3411 => x"00003544", -3412 => x"00003544", -3413 => x"0000354c", -3414 => x"0000354c", -3415 => x"00003554", -3416 => x"00003554", -3417 => x"0000355c", -3418 => x"0000355c", -3419 => x"00003564", -3420 => x"00003564", -3421 => x"0000356c", -3422 => x"0000356c", -3423 => x"00003580", -3424 => x"00000000", -3425 => x"000037e8", -3426 => x"00003844", -3427 => x"000038a0", -3428 => x"00000000", -3429 => x"00000000", -3430 => x"00000000", -3431 => x"00000000", -3432 => x"00000000", -3433 => x"00000000", -3434 => x"00000000", -3435 => x"00000000", -3436 => x"00000000", -3437 => x"00003100", -3438 => x"00000000", -3439 => x"00000000", -3440 => x"00000000", -3441 => x"00000000", -3442 => x"00000000", -3443 => x"00000000", -3444 => x"00000000", -3445 => x"00000000", -3446 => x"00000000", -3447 => x"00000000", -3448 => x"00000000", -3449 => x"00000000", -3450 => x"00000000", -3451 => x"00000000", -3452 => x"00000000", -3453 => x"00000000", -3454 => x"00000000", -3455 => x"00000000", -3456 => x"00000000", -3457 => x"00000000", -3458 => x"00000000", -3459 => x"00000000", -3460 => x"00000000", -3461 => x"00000000", -3462 => x"00000000", -3463 => x"00000000", -3464 => x"00000000", -3465 => x"00000000", -3466 => x"00000001", -3467 => x"330eabcd", -3468 => x"1234e66d", -3469 => x"deec0005", -3470 => x"000b0000", -3471 => x"00000000", -3472 => x"00000000", -3473 => x"00000000", -3474 => x"00000000", -3475 => x"00000000", -3476 => x"00000000", -3477 => x"00000000", -3478 => x"00000000", -3479 => x"00000000", -3480 => x"00000000", -3481 => x"00000000", -3482 => x"00000000", -3483 => x"00000000", -3484 => x"00000000", -3485 => x"00000000", -3486 => x"00000000", -3487 => x"00000000", -3488 => x"00000000", -3489 => x"00000000", -3490 => x"00000000", -3491 => x"00000000", -3492 => x"00000000", -3493 => x"00000000", -3494 => x"00000000", -3495 => x"00000000", -3496 => x"00000000", -3497 => x"00000000", -3498 => x"00000000", -3499 => x"00000000", -3500 => x"00000000", -3501 => x"00000000", -3502 => x"00000000", -3503 => x"00000000", -3504 => x"00000000", -3505 => x"00000000", -3506 => x"00000000", -3507 => x"00000000", -3508 => x"00000000", -3509 => x"00000000", -3510 => x"00000000", -3511 => x"00000000", -3512 => x"00000000", -3513 => x"00000000", -3514 => x"00000000", -3515 => x"00000000", -3516 => x"00000000", -3517 => x"00000000", -3518 => x"00000000", -3519 => x"00000000", -3520 => x"00000000", -3521 => x"00000000", -3522 => x"00000000", -3523 => x"00000000", -3524 => x"00000000", -3525 => x"00000000", -3526 => x"00000000", -3527 => x"00000000", -3528 => x"00000000", -3529 => x"00000000", -3530 => x"00000000", -3531 => x"00000000", -3532 => x"00000000", -3533 => x"00000000", -3534 => x"00000000", -3535 => x"00000000", -3536 => x"00000000", -3537 => x"00000000", -3538 => x"00000000", -3539 => x"00000000", -3540 => x"00000000", -3541 => x"00000000", -3542 => x"00000000", -3543 => x"00000000", -3544 => x"00000000", -3545 => x"00000000", -3546 => x"00000000", -3547 => x"00000000", -3548 => x"00000000", -3549 => x"00000000", -3550 => x"00000000", -3551 => x"00000000", -3552 => x"00000000", -3553 => x"00000000", -3554 => x"00000000", -3555 => x"00000000", -3556 => x"00000000", -3557 => x"00000000", -3558 => x"00000000", -3559 => x"00000000", -3560 => x"00000000", -3561 => x"00000000", -3562 => x"00000000", -3563 => x"00000000", -3564 => x"00000000", -3565 => x"00000000", -3566 => x"00000000", -3567 => x"00000000", -3568 => x"00000000", -3569 => x"00000000", -3570 => x"00000000", -3571 => x"00000000", -3572 => x"00000000", -3573 => x"00000000", -3574 => x"00000000", -3575 => x"00000000", -3576 => x"00000000", -3577 => x"00000000", -3578 => x"00000000", -3579 => x"00000000", -3580 => x"00000000", -3581 => x"00000000", -3582 => x"00000000", -3583 => x"00000000", -3584 => x"00000000", -3585 => x"00000000", -3586 => x"00000000", -3587 => x"00000000", -3588 => x"00000000", -3589 => x"00000000", -3590 => x"00000000", -3591 => x"00000000", -3592 => x"00000000", -3593 => x"00000000", -3594 => x"00000000", -3595 => x"00000000", -3596 => x"00000000", -3597 => x"00000000", -3598 => x"00000000", -3599 => x"00000000", -3600 => x"00000000", -3601 => x"00000000", -3602 => x"00000000", -3603 => x"00000000", -3604 => x"00000000", -3605 => x"00000000", -3606 => x"00000000", -3607 => x"00000000", -3608 => x"00000000", -3609 => x"00000000", -3610 => x"00000000", -3611 => x"00000000", -3612 => x"00000000", -3613 => x"00000000", -3614 => x"00000000", -3615 => x"00000000", -3616 => x"00000000", -3617 => x"00000000", -3618 => x"00000000", -3619 => x"00000000", -3620 => x"00000000", -3621 => x"00000000", -3622 => x"00000000", -3623 => x"00000000", -3624 => x"00000000", -3625 => x"00000000", -3626 => x"00000000", -3627 => x"00000000", -3628 => x"00000000", -3629 => x"00000000", -3630 => x"00000000", -3631 => x"00000000", -3632 => x"00000000", -3633 => x"00000000", -3634 => x"00000000", -3635 => x"00000000", -3636 => x"00000000", -3637 => x"00000000", -3638 => x"00000000", -3639 => x"00000000", -3640 => x"00000000", -3641 => x"00000000", -3642 => x"00000000", -3643 => x"00000000", -3644 => x"00000000", -3645 => x"00000000", -3646 => x"00000000", -3647 => x"00003104", -3648 => x"ffffffff", -3649 => x"00000000", -3650 => x"ffffffff", -3651 => x"00000000", +3167 => x"00000000", +3168 => x"00000000", +3169 => x"00000000", +3170 => x"00000000", +3171 => x"00000000", +3172 => x"00000000", +3173 => x"00000000", +3174 => x"00000000", +3175 => x"00000000", +3176 => x"00000000", +3177 => x"00000000", +3178 => x"00000000", +3179 => x"00000000", +3180 => x"00000000", +3181 => x"00000000", +3182 => x"00000000", +3183 => x"00000000", +3184 => x"00000000", +3185 => x"00000000", +3186 => x"00000000", +3187 => x"00000000", +3188 => x"00000000", +3189 => x"00000000", +3190 => x"00000000", +3191 => x"00000000", +3192 => x"00000000", +3193 => x"00000000", +3194 => x"00000000", +3195 => x"00000000", +3196 => x"00000000", +3197 => x"00000000", +3198 => x"00000000", +3199 => x"00000000", +3200 => x"00000000", +3201 => x"00000000", +3202 => x"00000000", +3203 => x"00000000", +3204 => x"00000000", +3205 => x"00000000", +3206 => x"00000000", +3207 => x"00000000", +3208 => x"00000000", +3209 => x"00000000", +3210 => x"00000000", +3211 => x"00000000", +3212 => x"00000000", +3213 => x"00000000", +3214 => x"00000000", +3215 => x"00000000", +3216 => x"00000000", +3217 => x"00000000", +3218 => x"00000000", +3219 => x"00000000", +3220 => x"00000000", +3221 => x"00000000", +3222 => x"00000000", +3223 => x"00000000", +3224 => x"00000000", +3225 => x"00000000", +3226 => x"00000000", +3227 => x"00000000", +3228 => x"00000000", +3229 => x"00000000", +3230 => x"00000000", +3231 => x"00000000", +3232 => x"00000000", +3233 => x"00000000", +3234 => x"00000000", +3235 => x"00000000", +3236 => x"00000000", +3237 => x"00000000", +3238 => x"00000000", +3239 => x"00000000", +3240 => x"00000000", +3241 => x"00000000", +3242 => x"00000000", +3243 => x"00000000", +3244 => x"00000000", +3245 => x"00000000", +3246 => x"00000000", +3247 => x"00000000", +3248 => x"00000000", +3249 => x"00000000", +3250 => x"00000000", +3251 => x"00002ad4", +3252 => x"ffffffff", +3253 => x"00000000", +3254 => x"ffffffff", +3255 => x"00000000", diff --git a/zpu/sw/env.sh b/zpu/sw/env.sh new file mode 100644 index 0000000..8ed43f0 --- /dev/null +++ b/zpu/sw/env.sh @@ -0,0 +1,2 @@ +export ZPUSW=`pwd` +export PATH=$PATH:/tmp/zpu/install/bin diff --git a/zpu/sw/index.html b/zpu/sw/index.html index 6c860a9..fd0a1b4 100644 --- a/zpu/sw/index.html +++ b/zpu/sw/index.html @@ -9,10 +9,10 @@ some very basic peripherals defined: counter, timer interrupt and a debug output
      3. Install Java
      4. Start Cygwin bash
      5. cd zpu/sw -
      6. unzip tools/zputoolchain.zip -
      7. zpu/sw/install/bin now has the .exe files for the GCC toolchain & GDB -
      8. You may want to add install/bin from zputoolchain.zip to PATH.
        -export PATH=$PATH:<unzipdir>/install/bin +
      9. sh setup.sh +
      10. /tmp/zpu/install/bin now has the .exe files for the GCC toolchain & GDB +
      11. Optionally you may set up PATH variables to point to /tmp/zpu/install/bin
        +source env.sh

      Hello world example

      The ZPU toolchain comes with newlib & libstdc++ support which means that many C/C++ programs can be compiled without modification. diff --git a/zpu/sw/setup.sh b/zpu/sw/setup.sh new file mode 100644 index 0000000..57747f8 --- /dev/null +++ b/zpu/sw/setup.sh @@ -0,0 +1,6 @@ +. env.sh +rm -rf /tmp/zpu +mkdir -p /tmp/zpu/install/bin +cd /tmp/zpu +unzip $ZPUSW/tools/zputoolchain.zip + -- cgit v1.1 From fbe743288c676e94b52849f083a9f3d5015a13ed Mon Sep 17 00:00:00 2001 From: oharboe Date: Fri, 22 Feb 2008 07:57:20 +0000 Subject: wip porting zpu_core_bram.vhd from ZPU3. --- zpu/hdl/zpu4/src/bram_dmips.vhd | 6 +- zpu/hdl/zpu4/src/simzpu_bram.do | 28 ++ zpu/hdl/zpu4/src/zpu_config_trace.vhd | 1 + zpu/hdl/zpu4/src/zpu_core_bram.vhd | 780 ++++++++++++++++++++++++++++++++++ zpu/hdl/zpu4/src/zpu_core_small.vhd | 13 - zpu/hdl/zpu4/src/zpupkg.vhd | 13 + 6 files changed, 825 insertions(+), 16 deletions(-) create mode 100644 zpu/hdl/zpu4/src/simzpu_bram.do create mode 100644 zpu/hdl/zpu4/src/zpu_core_bram.vhd diff --git a/zpu/hdl/zpu4/src/bram_dmips.vhd b/zpu/hdl/zpu4/src/bram_dmips.vhd index 1c85e0d..83bfc28 100644 --- a/zpu/hdl/zpu4/src/bram_dmips.vhd +++ b/zpu/hdl/zpu4/src/bram_dmips.vhd @@ -10,11 +10,11 @@ use work.zpupkg.all; entity dualport_ram is port (clk : in std_logic; memAWriteEnable : in std_logic; - memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit); + memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); memAWrite : in std_logic_vector(wordSize-1 downto 0); memARead : out std_logic_vector(wordSize-1 downto 0); memBWriteEnable : in std_logic; - memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit); + memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); memBWrite : in std_logic_vector(wordSize-1 downto 0); memBRead : out std_logic_vector(wordSize-1 downto 0)); end dualport_ram; @@ -22,7 +22,7 @@ end dualport_ram; architecture dualport_ram_arch of dualport_ram is -type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); +type ram_type is array(0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); shared variable ram : ram_type := ( diff --git a/zpu/hdl/zpu4/src/simzpu_bram.do b/zpu/hdl/zpu4/src/simzpu_bram.do new file mode 100644 index 0000000..1c8673d --- /dev/null +++ b/zpu/hdl/zpu4/src/simzpu_bram.do @@ -0,0 +1,28 @@ +# Xilinx WebPack modelsim script +# +# cd C:/workspace/zpu/zpu/hdl/zpu4/src +# do simzpu_bram.do + +set BreakOnAssertion 1 +vlib work + +vcom -93 -explicit zpu_config_trace.vhd +vcom -93 -explicit zpupkg.vhd +vcom -93 -explicit txt_util.vhd +vcom -93 -explicit sim_fpga_top.vhd +vcom -93 -explicit zpu_core_bram.vhd +vcom -93 -explicit bram_dmips.vhd +vcom -93 -explicit timer.vhd +vcom -93 -explicit io.vhd +vcom -93 -explicit trace.vhd + +# run ZPU +vsim fpga_top +view wave +add wave -recursive fpga_top/zpu/* +#add wave -recursive fpga_top/* +view structure +#view signals + +# Enough to run tiny programs +run 1us diff --git a/zpu/hdl/zpu4/src/zpu_config_trace.vhd b/zpu/hdl/zpu4/src/zpu_config_trace.vhd index a2d7d9d..4d0f15f 100644 --- a/zpu/hdl/zpu4/src/zpu_config_trace.vhd +++ b/zpu/hdl/zpu4/src/zpu_config_trace.vhd @@ -12,6 +12,7 @@ package zpu_config is constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64"; constant maxAddrBitIncIO : integer := 27; constant maxAddrBitDRAM : integer := 16; + constant maxAddrBitBRAM : integer := 16; constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"001fff8"; end zpu_config; diff --git a/zpu/hdl/zpu4/src/zpu_core_bram.vhd b/zpu/hdl/zpu4/src/zpu_core_bram.vhd new file mode 100644 index 0000000..0bedba3 --- /dev/null +++ b/zpu/hdl/zpu4/src/zpu_core_bram.vhd @@ -0,0 +1,780 @@ +-- Company: ZPU3 +-- Engineer: Øyvind Harboe + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.STD_LOGIC_arith.ALL; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + + +-- io_busy : in std_logic; +-- io_read : in std_logic_vector(7 downto 0); +-- io_write : out std_logic_vector(7 downto 0); +-- io_addr : out std_logic_vector(maxAddrBit downto minAddrBit); +-- io_writeEnable : out std_logic; +-- io_readEnable : out std_logic; + + +entity zpu_core is + Port ( clk : in std_logic; + areset : in std_logic; + enable : in std_logic; + in_mem_busy : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + out_mem_writeEnable : out std_logic; + out_mem_readEnable : out std_logic; + mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + interrupt : in std_logic; + break : out std_logic); +end zpu_core; + + +architecture behave of zpu_core is + +signal readIO : std_logic; + + + +signal memAWriteEnable : std_logic; +signal memAAddr : std_logic_vector(maxAddrBit downto minAddrBit); +signal memAWrite : std_logic_vector(wordSize-1 downto 0); +signal memARead : std_logic_vector(wordSize-1 downto 0); +signal memBWriteEnable : std_logic; +signal memBAddr : std_logic_vector(maxAddrBit downto minAddrBit); +signal memBWrite : std_logic_vector(wordSize-1 downto 0); +signal memBRead : std_logic_vector(wordSize-1 downto 0); + + + +signal pc : std_logic_vector(maxAddrBit downto 0); +signal sp : std_logic_vector(maxAddrBit downto minAddrBit); + +signal idim_flag : std_logic; + +--signal storeToStack : std_logic; +--signal fetchNextInstruction : std_logic; +--signal extraCycle : std_logic; +signal busy : std_logic; +--signal fetching : std_logic; + +signal begin_inst : std_logic; + + + +signal trace_opcode : std_logic_vector(7 downto 0); +signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); +signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); +signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); + +-- state machine. + +type State_Type is +( +State_ResyncDecode, +State_WriteIODone, +State_Execute, +State_StoreToStack, +State_Add, +State_Or, +State_And, +State_Store, +State_ReadIO, +State_WriteIO, +State_Load, +State_ResyncStack, +State_AddSP, +State_ReadIODone, +State_Decode, +State_LoadByte1, +State_LoadByte2, +State_StoreByte1, +State_StoreByte2, +State_Mult1, +State_Mult2, +State_Mult3 +); + +type DecodedOpcodeType is +( +Decoded_Nop, +Decoded_Im, +Decoded_ImShift, +Decoded_LoadSP, +Decoded_StoreSP, +Decoded_AddSP, +Decoded_Emulate, +Decoded_Break, +Decoded_PushPC, +Decoded_PushSP, +Decoded_PopPC, +Decoded_Add, +Decoded_Or, +Decoded_And, +Decoded_Load, +Decoded_Not, +Decoded_Flip, +Decoded_Store, +Decoded_PopSP, +Decoded_Ashiftleft, +Decoded_Ashiftright, +Decoded_Lshiftright, +Decoded_Eqbranch, +Decoded_Neqbranch, +Decoded_Eq, +Decoded_Neq, +Decoded_Loadb, +Decoded_Lessthan, +Decoded_Lessthanorequal, +Decoded_Ulessthan, +Decoded_Ulessthanorequal, +Decoded_Storeb, +Decoded_Lshift2, +Decoded_DoubleIm, +Decoded_AddIm, +Decoded_Mult16x16, +Decoded_Swap, +Decoded_Callpcrel, +Decoded_Pushspadd +); + + +signal mult1 : std_logic_vector(wordSize/2-1 downto 0); +signal mult2 : std_logic_vector(wordSize/2-1 downto 0); +signal multResult : std_logic_vector(wordSize-1 downto 0); + +signal storeByte : std_logic_vector(7 downto 0); +signal byteSelect : std_logic_vector(minAddrBit-1 downto 0); + +signal opcode : std_logic_vector(OpCode_Size-1 downto 0); +signal opcode2 : std_logic_vector(OpCode_Size-1 downto 0); + +signal decodedOpcode : DecodedOpcodeType; + +signal state : State_Type; + +begin + traceFileGenerate: + if Generate_Trace generate + trace_file: trace port map ( + clk => clk, + begin_inst => begin_inst, + pc => trace_pc, + opcode => trace_opcode, + sp => trace_sp, + memA => trace_topOfStack, + memB => trace_topOfStackB, + busy => busy, + intsp => (others => 'U') + ); + end generate; + + + memory: dualport_ram port map ( + clk => clk, + memAWriteEnable => memAWriteEnable, + memAAddr => memAAddr(maxAddrBitBRAM downto minAddrBit), + memAWrite => memAWrite, + memARead => memARead, + memBWriteEnable => memBWriteEnable, + memBAddr => memBAddr(maxAddrBitBRAM downto minAddrBit), + memBWrite => memBWrite, + memBRead => memBRead + ); + + + + process(clk, areset) + begin + if (clk'event and clk = '1') then + multResult <= mult1 * mult2; + end if; + end process; + + + + opcodeControl: + process(clk, areset) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + variable tOpcode2 : std_logic_vector(OpCode_Size-1 downto 0); + variable spOffset : std_logic_vector(4 downto 0); + variable spOffset2 : std_logic_vector(4 downto 0); + variable nextPC : std_logic_vector(maxAddrBit downto 0); + variable pushspaddTemp : std_logic_vector(maxAddrBit downto minAddrBit); + variable tempVal : std_logic_vector(wordSize-1 downto 0); + variable compareA : signed(wordSize-1 downto 0); + variable compareB : signed(wordSize-1 downto 0); + begin + if areset = '1' then + mult1 <= (others => '0'); + mult2 <= (others => '0'); + state <= State_ResyncDecode; + break <= '0'; + sp <= spStart(maxAddrBit downto minAddrBit); + pc <= (others => '0'); + idim_flag <= '0'; + begin_inst <= '0'; + memAAddr <= (others => '0'); + memBAddr <= (others => '0'); + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + out_mem_writeEnable <= '0'; + out_mem_readEnable <= '0'; + decodedOpcode <= Decoded_Break; + memAWrite <= (others => '0'); + memBWrite <= (others => '0'); + opcode <= (others => '0'); + out_mem_addr <= (others => '0'); + mem_write <= (others => '0'); + elsif (clk'event and clk = '1') then + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + + out_mem_writeEnable <= '0'; + out_mem_readEnable <= '0'; + out_mem_addr <= memARead(maxAddrBitIncIO downto 0); + begin_inst <= '0'; + + case state is + when State_Decode => + nextPC:=pc+1; + case pc(1 downto 0) is + when "00" => tOpcode := memARead(31 downto 24); + when "01" => tOpcode := memARead(23 downto 16); + when "10" => tOpcode := memARead(15 downto 8); + when others => tOpcode := memARead(7 downto 0); + end case; + case nextPC(1 downto 0) is + when "00" => tOpcode2 := memBRead(31 downto 24); + when "01" => tOpcode2 := memBRead(23 downto 16); + when "10" => tOpcode2 := memBRead(15 downto 8); + when others => tOpcode2 := memBRead(7 downto 0); + end case; + idim_flag <= tOpcode(7); + opcode <= tOpcode; + opcode2 <= tOpcode2; + if (tOpcode(7 downto 7)=OpCode_Im and tOpcode2(7 downto 4)=0 and tOpcode2(3 downto 0)=Opcode_Add and idim_flag='0') then + idim_flag <= '0'; + decodedOpcode <= Decoded_AddIm; + nextPC := pc + 2; + elsif (tOpcode(7 downto 7)=OpCode_Im and tOpcode2(7 downto 7)=OpCode_Im and idim_flag='0') then + decodedOpcode <= Decoded_DoubleIm; + nextPC := pc + 2; + elsif (tOpcode(7 downto 4)=OpCode_AddSP and tOpcode(3 downto 0)=0 and + tOpcode2(7 downto 4)=OpCode_AddSP and tOpcode2(3 downto 0)=0) then + decodedOpcode <= Decoded_Lshift2; + nextPC := pc + 2; + elsif (tOpcode(7 downto 7)=OpCode_Im) then + if (idim_flag='1') then + decodedOpcode<=Decoded_ImShift; + else + decodedOpcode<=Decoded_Im; + end if; + elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then + decodedOpcode<=Decoded_StoreSP; + elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then + decodedOpcode<=Decoded_LoadSP; + elsif (tOpcode(7 downto 5)=OpCode_Emulate) then + if tOpcode(5 downto 0)=OpCode_Eqbranch then + decodedOpcode <= Decoded_Eqbranch; + elsif tOpcode(5 downto 0)=OpCode_Neqbranch then + decodedOpcode <= Decoded_Neqbranch; + elsif tOpcode(5 downto 0)=OpCode_Eq then + decodedOpcode <= Decoded_Eq; + elsif tOpcode(5 downto 0)=OpCode_Neq then + decodedOpcode <= Decoded_Neq; + elsif tOpcode(5 downto 0)=OpCode_Lessthan then + decodedOpcode <= Decoded_Lessthan; + elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then + decodedOpcode <= Decoded_Lessthanorequal; + elsif tOpcode(5 downto 0)=OpCode_Ulessthan then + decodedOpcode <= Decoded_Ulessthan; + elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then + decodedOpcode <= Decoded_Ulessthanorequal; + elsif tOpcode(5 downto 0)=OpCode_Loadb then + decodedOpcode <= Decoded_Loadb; + elsif tOpcode(5 downto 0)=OpCode_Storeb then + decodedOpcode <= Decoded_Storeb; + elsif tOpcode(5 downto 0)=OpCode_Mult16x16 then + decodedOpcode <= Decoded_Mult16x16; + elsif tOpcode(5 downto 0)=OpCode_Swap then + decodedOpcode <= Decoded_Swap; + elsif tOpcode(5 downto 0)=OpCode_Callpcrel then + decodedOpcode <= Decoded_Callpcrel; + elsif tOpcode(5 downto 0)=OpCode_Pushspadd then + decodedOpcode <= Decoded_Pushspadd; +-- elsif tOpcode(5 downto 0)=OpCode_Lshiftright then +-- decodedOpcode <= Decoded_Lshiftright; +-- elsif tOpcode(5 downto 0)=OpCode_Ashiftleft then +-- decodedOpcode <= Decoded_Ashiftleft; +-- elsif tOpcode(5 downto 0)=OpCode_Ashiftright then +-- decodedOpcode <= Decoded_Ashiftright; + else + decodedOpcode<=Decoded_Emulate; + end if; + elsif (tOpcode(7 downto 4)=OpCode_AddSP) then + decodedOpcode<=Decoded_AddSP; + else + case tOpcode(3 downto 0) is + when OpCode_PushSP => + decodedOpcode<=Decoded_PushSP; + when OpCode_PopPC => + decodedOpcode<=Decoded_PopPC; + when OpCode_Add => + decodedOpcode<=Decoded_Add; + when OpCode_Or => + decodedOpcode<=Decoded_Or; + when OpCode_And => + decodedOpcode<=Decoded_And; + when OpCode_Load => + decodedOpcode<=Decoded_Load; + when OpCode_Not => + decodedOpcode<=Decoded_Not; + when OpCode_Flip => + decodedOpcode<=Decoded_Flip; + when OpCode_Store => + decodedOpcode<=Decoded_Store; + when OpCode_PopSP => + decodedOpcode<=Decoded_PopSP; + when OpCode_Break => + decodedOpcode<=Decoded_Break; + when others => + decodedOpcode<=Decoded_Nop; + end case; + end if; + -- Fetch the two next opcodes... :-) + memAAddr <= nextPC(maxAddrBit downto minAddrBit); + nextPC:=nextPC+1; + memBAddr <= nextPC(maxAddrBit downto minAddrBit); + state <= State_Execute; + when State_Execute => + state <= State_Decode; + -- at this point: + -- memBRead contains opcode word + -- memARead contains top of stack + pc <= pc + 1; + + -- trace + begin_inst <= '1'; + trace_pc <= (others => '0'); + trace_pc(maxAddrBit downto 0) <= pc; + trace_sp <= (others => '0'); + trace_sp(maxAddrBit downto minAddrBit) <= sp; + trace_opcode <= opcode; + trace_topOfStack <= memARead; + trace_topOfStackB <= memBRead; + + + -- during the next cycle we'll be reading the next opcode + spOffset(4):=not opcode(4); + spOffset(3 downto 0):=opcode(3 downto 0); + spOffset2(4):=not opcode2(4); + spOffset2(3 downto 0):=opcode2(3 downto 0); + + case decodedOpcode is + + when Decoded_DoubleIm => + memAWriteEnable <= '1'; + sp <= sp - 1; + memAAddr <= sp-1; + for i in wordSize-1 downto 14 loop + memAWrite(i) <= opcode(6); + end loop; + memAWrite(13 downto 7) <= opcode(6 downto 0); + memAWrite(6 downto 0) <= opcode2(6 downto 0); + memBAddr <= sp; + memBWrite <= memARead; + memBWriteEnable <= '1'; + pc <= pc + 2; + when Decoded_Im => + memAWriteEnable <= '1'; + sp <= sp - 1; + memAAddr <= sp-1; + for i in wordSize-1 downto 7 loop + memAWrite(i) <= opcode(6); + end loop; + memAWrite(6 downto 0) <= opcode(6 downto 0); + memBAddr <= sp; + memBWrite <= memARead; + memBWriteEnable <= '1'; + when Decoded_ImShift => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0); + memAWrite(6 downto 0) <= opcode(6 downto 0); + memBAddr <= sp + 1; + when Decoded_StoreSP => + memAWriteEnable <= '1'; + memAAddr <= sp+spOffset; + memAWrite <= memARead; + -- avoid address crashes. + memBAddr <= sp - 1; + sp <= sp + 1; + state <= State_ResyncDecode; + when Decoded_LoadSP => + sp <= sp - 1; + if (spOffset = 0) then + -- This is a duplicate instruction. + memAAddr <= sp-1; + memAWriteEnable <= '1'; + memAWrite <= memARead; + else + memAAddr <= sp+spOffset; + end if; + memBAddr <= sp; + memBWrite <= memARead; + memBWriteEnable <= '1'; + when Decoded_Callpcrel => + memAWriteEnable <= '1'; + memAAddr <= sp; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto 0) <= pc + 1; + memBAddr <= sp+1; + pc <= pc + memARead(maxAddrBit downto 0); + state <= State_ResyncDecode; + when Decoded_Emulate => + sp <= sp - 1; + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto 0) <= pc + 1; + memBAddr <= sp; + memBWrite <= memARead; + memBWriteEnable <= '1'; + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= (others => '0'); + pc(9 downto 5) <= opcode(4 downto 0); + state <= State_ResyncDecode; + when Decoded_AddSP => + if spOffset=0 then + -- avoid address line crashes... + -- FIX!!! is this an issue? + -- oh-well. While we are at it, we've got a faster + -- shift operation without updating the toolchain. + memAWriteEnable <= '1'; + memAAddr <= sp; + memAWrite <= memARead + memARead; + memBAddr <= sp+1; + else + memAWriteEnable <= '1'; + memAAddr <= sp; + memAWrite <= memARead; + memBAddr <= sp+spOffset; + state <= State_AddSP; + end if; + when Decoded_Break => + report "Break instruction encountered" severity failure; + break <= '1'; + when Decoded_PushSP => + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + sp <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto minAddrBit) <= sp; + memBAddr <= sp; + memBWrite <= memARead; + memBWriteEnable <= '1'; + when Decoded_Pushspadd => + memAWriteEnable <= '1'; + memAAddr <= sp; + memAWrite <= (others => DontCareValue); + pushspaddTemp := memARead(maxAddrBit-minAddrBit downto 0); + memAWrite(maxAddrBit downto minAddrBit) <= sp+pushspaddTemp; + memBAddr <= sp+1; + when Decoded_PopPC => + memAAddr <= sp; + pc <= memARead(maxAddrBit downto 0); + sp <= sp + 1; + state <= State_ResyncDecode; + when Decoded_AddIm => + memAWriteEnable <= '1'; + memAAddr <= sp; + tempVal(wordSize-1 downto 7) := (others => tOpcode(6)); + tempVal(6 downto 0) := tOpcode(6 downto 0); + memAWrite <= memARead + tempVal; + memBAddr <= sp + 1; + pc <= pc + 2; + when Decoded_Add => + memAWriteEnable <= '1'; + memAWrite <= memARead + memBRead; + memAAddr <= sp + 1; + memBAddr <= sp + 2; + sp <= sp + 1; + when Decoded_Or => + sp <= sp + 1; + memAWriteEnable <= '1'; + memAWrite <= memARead or memBRead; + memAWriteEnable <= '1'; + memAAddr <= sp + 1; + memBAddr <= sp + 2; + when Decoded_And => + sp <= sp + 1; + memAWriteEnable <= '1'; + memAWrite <= memARead and memBRead; + memAWriteEnable <= '1'; + memAAddr <= sp + 1; + memBAddr <= sp + 2; + when Decoded_Load => + if (memARead(ioBit)='1') then + out_mem_addr <= memARead(maxAddrBitIncIO downto 0); + out_mem_readEnable <= '1'; + state <= State_ReadIO; + else + memAAddr <= memARead(maxAddrBit downto minAddrBit); + memBAddr <= sp + 1; + end if; + when Decoded_Swap => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite(wordSize/2-1 downto 0) <= memARead(wordSize-1 downto wordSize/2); + memAWrite(wordSize-1 downto wordSize/2) <= memARead(wordSize/2-1 downto 0); + memBAddr <= sp + 1; + when Decoded_Not => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= not memARead; + memBAddr <= sp + 1; + when Decoded_Flip => + memAAddr <= sp; + memAWriteEnable <= '1'; + for i in 0 to wordSize-1 loop + memAWrite(i) <= memARead(wordSize-1-i); + end loop; + memBAddr <= sp + 1; + when Decoded_Lshift2 => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite(1 downto 0) <= (others => '0'); + memAWrite(wordSize-1 downto 2) <= memARead(wordSize-1-2 downto 0); + memBAddr <= sp + 1; + pc <= pc + 2; + when Decoded_Store => + sp <= sp + 2; + if (memARead(ioBit)='1') then + out_mem_writeEnable <= '1'; + out_mem_addr <= memARead(maxAddrBitIncIO downto 0); + mem_write <= memBRead; + state <= State_WriteIO; + else + memAWriteEnable <= '1'; + memAAddr <= memARead(maxAddrBit downto minAddrBit); + memAWrite <= memBRead; + state <= State_ResyncDecode; + end if; + when Decoded_PopSP => + sp <= memARead(maxAddrBit downto minAddrBit); + state <= State_ResyncDecode; + when Decoded_Ashiftleft => + memAWrite(wordSize-1 downto conv_integer(memARead(wordPower-1 downto 0))) <= + memBRead(wordSize-conv_integer(memARead(wordPower-1 downto 0))-1 downto 0); + if memARead(wordPower-1 downto 0)/=0 then + memAWrite(conv_integer(memARead(wordPower-1 downto 0))-1 downto 0) <= (others => '0'); + end if; + memAWriteEnable <= '1'; + memAAddr <= sp + 1; + memBAddr <= sp + 2; + sp <= sp + 1; + when Decoded_Ashiftright | Decoded_Lshiftright => + memAWrite(wordSize-1-conv_integer(memARead(wordPower-1 downto 0)) downto 0) <= + memBRead(wordSize-1 downto conv_integer(memARead(wordPower-1 downto 0))); + if memARead(wordPower-1 downto 0)/=0 then + if decodedOpcode=Decoded_Ashiftright and memBRead(wordSize-1)='1' then + memAWrite(wordSize-1 downto wordSize-conv_integer(memARead(wordPower-1 downto 0))-1) <= (others => '1'); + else + memAWrite(wordSize-1 downto wordSize-conv_integer(memARead(wordPower-1 downto 0))-1) <= (others => '0'); + end if; + end if; + memAWriteEnable <= '1'; + memAAddr <= sp + 1; + memBAddr <= sp + 2; + sp <= sp + 1; + when Decoded_Eqbranch => + sp <= sp + 2; + if (memBRead=0) then + pc <= memARead(maxAddrBit downto 0) + pc; + end if; + state <= State_ResyncDecode; + when Decoded_Neqbranch => + sp <= sp + 2; + if (memBRead/=0) then + pc <= memARead(maxAddrBit downto 0) + pc; + end if; + state <= State_ResyncDecode; + when Decoded_Eq => + sp <= sp + 1; + memAWrite <= (others => '0'); + if (memARead=memBRead) then + memAWrite(0) <= '1'; + end if; + memAAddr <= sp + 1; + memAWriteEnable <= '1'; + memBAddr <= sp + 2; + when Decoded_Neq => + sp <= sp + 1; + memAWrite <= (others => '0'); + if (memARead/=memBRead) then + memAWrite(0) <= '1'; + end if; + memAAddr <= sp + 1; + memAWriteEnable <= '1'; + memBAddr <= sp + 2; + when Decoded_Ulessthan => + sp <= sp + 1; + memAWrite <= (others => '0'); + if (memARead + sp <= sp + 1; + memAWrite <= (others => '0'); + if (memARead<=memBRead) then + memAWrite(0) <= '1'; + end if; + memAAddr <= sp + 1; + memAWriteEnable <= '1'; + memBAddr <= sp + 2; + when Decoded_Lessthan => + sp <= sp + 1; + memAWrite <= (others => '0'); + compareA := signed(memARead); + compareB := signed(memBRead); + if (compareA + sp <= sp + 1; + memAWrite <= (others => '0'); + compareA := signed(memARead); + compareB := signed(memBRead); + if (compareA<=compareB) then + memAWrite(0) <= '1'; + end if; + memAAddr <= sp + 1; + memAWriteEnable <= '1'; + memBAddr <= sp + 2; + when Decoded_Loadb => + byteSelect <= memARead(minAddrBit-1 downto 0); + memAAddr <= memARead(maxAddrBit downto minAddrBit); + state <= State_LoadByte1; + when Decoded_Storeb => + sp <= sp + 2; + byteSelect <= memARead(minAddrBit-1 downto 0); + storeByte <= memBRead(7 downto 0); + memAAddr <= memARead(maxAddrBit downto minAddrBit); + memBAddr <= sp; + state <= State_StoreByte1; + when Decoded_Mult16x16 => + mult1 <= memARead(wordSize/2-1 downto 0); + mult2 <= memBRead(wordSize/2-1 downto 0); + sp <= sp + 1; + state <= State_Mult1; + when others => + -- nop. Here we persist whatever was loaded into + -- memARead + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead; + memBAddr <= sp + 1; + + end case; + when State_ReadIO => + state <= State_ReadIODone; + when State_ReadIODone => + if (in_mem_busy = '0') then + state <= State_ResyncDecode; + memAWriteEnable <= '1'; + memAWrite <= (others => '0'); + memAWrite <= mem_read; + memAAddr <= sp; + end if; + when State_WriteIO => + state <= State_WriteIODone; + when State_WriteIODone => + if (in_mem_busy = '0') then + state <= State_ResyncDecode; + end if; + when State_ResyncDecode => + memAAddr <= pc(maxAddrBit downto minAddrBit); + nextPC:=pc+1; + memBAddr <= nextPC(maxAddrBit downto minAddrBit); + state <= State_ResyncStack; + when State_ResyncStack => + memAAddr <= sp; + memBAddr <= sp+1; + state <= State_Decode; + when State_AddSP => + memAAddr <= pc(maxAddrBit downto minAddrBit); + nextPC:=pc+1; + memBAddr <= nextPC(maxAddrBit downto minAddrBit); + state <= State_Add; + when State_Add => + memAWriteEnable <= '1'; + memAWrite <= memARead + memBRead; + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Decode; + when State_LoadByte1 => + memAAddr <= pc(maxAddrBit downto minAddrBit); + nextPC:=pc+1; + memBAddr <= nextPC(maxAddrBit downto minAddrBit); + state <= State_LoadByte2; + when State_LoadByte2 => + memAWriteEnable <= '1'; + memAAddr <= sp; + memAWrite <= (others => '0'); + case byteSelect is + when "00" => memAWrite(7 downto 0) <= memARead(31 downto 24); + when "01" => memAWrite(7 downto 0) <= memARead(23 downto 16); + when "10" => memAWrite(7 downto 0) <= memARead(15 downto 8); + when others => memAWrite(7 downto 0) <= memARead(7 downto 0); + end case; + memBAddr <= sp + 1; + state <= State_Decode; + when State_StoreByte1 => + state <= State_StoreByte2; + when State_StoreByte2 => + memAWriteEnable <= '1'; + memAAddr <= memBRead(maxAddrBit downto minAddrBit); + memAWrite <= memARead; + case byteSelect is + when "00" => memAWrite(31 downto 24) <= storeByte; + when "01" => memAWrite(23 downto 16) <= storeByte; + when "10" => memAWrite(15 downto 8) <= storeByte; + when others => memAWrite(7 downto 0) <= storeByte; + end case; + state <= State_ResyncDecode; + when State_Mult1 => + memAAddr <= pc(maxAddrBit downto minAddrBit); + nextPC:=pc+1; + memBAddr <= nextPC(maxAddrBit downto minAddrBit); + state <= State_Mult2; + when State_Mult2 => + memAWriteEnable <= '1'; + memAWrite <= multResult; + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Decode; + + when others => + null; + end case; + end if; + end process; + + + +end behave; diff --git a/zpu/hdl/zpu4/src/zpu_core_small.vhd b/zpu/hdl/zpu4/src/zpu_core_small.vhd index 8ebd40d..4d73f88 100644 --- a/zpu/hdl/zpu4/src/zpu_core_small.vhd +++ b/zpu/hdl/zpu4/src/zpu_core_small.vhd @@ -27,19 +27,6 @@ end zpu_core; architecture behave of zpu_core is -component dualport_ram is -port (clk : in std_logic; - memAWriteEnable : in std_logic; - memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); - memAWrite : in std_logic_vector(wordSize-1 downto 0); - memARead : out std_logic_vector(wordSize-1 downto 0); - memBWriteEnable : in std_logic; - memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); - memBWrite : in std_logic_vector(wordSize-1 downto 0); - memBRead : out std_logic_vector(wordSize-1 downto 0)); -end component; - - signal readIO : std_logic; diff --git a/zpu/hdl/zpu4/src/zpupkg.vhd b/zpu/hdl/zpu4/src/zpupkg.vhd index fd00b9e..32e162b 100644 --- a/zpu/hdl/zpu4/src/zpupkg.vhd +++ b/zpu/hdl/zpu4/src/zpupkg.vhd @@ -24,6 +24,19 @@ package zpupkg is constant stack_size : integer := 2**stack_bits; + component dualport_ram is + port (clk : in std_logic; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memAWrite : in std_logic_vector(wordSize-1 downto 0); + memARead : out std_logic_vector(wordSize-1 downto 0); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memBWrite : in std_logic_vector(wordSize-1 downto 0); + memBRead : out std_logic_vector(wordSize-1 downto 0)); + end component; + + component dram is port (clk : in std_logic; areset : in std_logic; -- cgit v1.1 From 648a70893907a9cb446f1546d4fd39cf6457f0e8 Mon Sep 17 00:00:00 2001 From: oharboe Date: Fri, 22 Feb 2008 12:38:46 +0000 Subject: * Hooked up support for the simulator to the Zylin Embedded CDT --- zpu/sw/simulator/.classpath | 1 + zpu/sw/simulator/.project | 11 + zpu/sw/simulator/ChangeLog | 2 + zpu/sw/simulator/META-INF/MANIFEST.MF | 11 + zpu/sw/simulator/build.properties | 3 + zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java | 2 +- .../simulator/com/zylin/zpu/simulator/SimApp.java | 93 +++++- .../com/zylin/zpu/simulator/Simulator.java | 2 + .../simulator/exceptions/EndSessionException.java | 24 ++ .../com/zylin/zpu/simulator/gdb/GDBServer.java | 313 +++------------------ .../com/zylin/zpu/simulator/gdb/Packet.java | 23 +- 11 files changed, 188 insertions(+), 297 deletions(-) create mode 100644 zpu/sw/simulator/META-INF/MANIFEST.MF create mode 100644 zpu/sw/simulator/build.properties diff --git a/zpu/sw/simulator/.classpath b/zpu/sw/simulator/.classpath index 617be7e..5e4fa9f 100644 --- a/zpu/sw/simulator/.classpath +++ b/zpu/sw/simulator/.classpath @@ -2,5 +2,6 @@ + diff --git a/zpu/sw/simulator/.project b/zpu/sw/simulator/.project index 9cd2fd7..29c7a4f 100644 --- a/zpu/sw/simulator/.project +++ b/zpu/sw/simulator/.project @@ -10,8 +10,19 @@ + + org.eclipse.pde.ManifestBuilder + + + + + org.eclipse.pde.SchemaBuilder + + + org.eclipse.jdt.core.javanature + org.eclipse.pde.PluginNature diff --git a/zpu/sw/simulator/ChangeLog b/zpu/sw/simulator/ChangeLog index c645841..18b0981 100644 --- a/zpu/sw/simulator/ChangeLog +++ b/zpu/sw/simulator/ChangeLog @@ -1,2 +1,4 @@ +2008-02-22 Øyvind Harboe + * Hooked up support for the simulator to the Zylin Embedded CDT 2007-08-04 Øyvind Harboe * First version after open sourcing ZPU diff --git a/zpu/sw/simulator/META-INF/MANIFEST.MF b/zpu/sw/simulator/META-INF/MANIFEST.MF new file mode 100644 index 0000000..b0ad5b9 --- /dev/null +++ b/zpu/sw/simulator/META-INF/MANIFEST.MF @@ -0,0 +1,11 @@ +Manifest-Version: 1.0 +Bundle-ManifestVersion: 2 +Bundle-Name: ZPU simulator +Bundle-SymbolicName: com.zylin.zpu.simulator +Bundle-Version: 1.0.0 +Export-Package: com.zylin.zpu.simulator, + com.zylin.zpu.simulator.applet, + com.zylin.zpu.simulator.exceptions, + com.zylin.zpu.simulator.gdb, + com.zylin.zpu.simulator.tools, + com.zylin.zpu.stats diff --git a/zpu/sw/simulator/build.properties b/zpu/sw/simulator/build.properties new file mode 100644 index 0000000..19c7019 --- /dev/null +++ b/zpu/sw/simulator/build.properties @@ -0,0 +1,3 @@ +source.. = . +bin.includes = META-INF/,\ + . diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java b/zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java index 862deae..0e3e7a1 100644 --- a/zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java +++ b/zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java @@ -98,7 +98,7 @@ public class Phi extends Simulator } } - Phi() throws CPUException + public Phi() throws CPUException { } diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/SimApp.java b/zpu/sw/simulator/com/zylin/zpu/simulator/SimApp.java index 8008275..3f6e1a9 100644 --- a/zpu/sw/simulator/com/zylin/zpu/simulator/SimApp.java +++ b/zpu/sw/simulator/com/zylin/zpu/simulator/SimApp.java @@ -2,6 +2,8 @@ package com.zylin.zpu.simulator; import java.io.IOException; import java.net.InetSocketAddress; +import java.net.ServerSocket; +import java.net.Socket; import java.nio.channels.ServerSocketChannel; import com.zylin.zpu.simulator.exceptions.CPUException; @@ -10,7 +12,6 @@ import com.zylin.zpu.simulator.gdb.GDBServer; public class SimApp { private static Simulator simulator; - public ServerSocketChannel channel; private String[] args; private int portNumber; private SimFactory simFactory; @@ -40,39 +41,65 @@ public class SimApp void run(String[] args) { this.args=args; + createSimulator(); parseArgs(); + moreParse(); + runSimAndGDB(); + } + Object launched=new Object(); + private boolean doneLaunching; + private boolean manyGDBSessions; + public ServerSocket serverSocket; + public void runSimAndGDB() + { try { - channel = ServerSocketChannel.open(); + serverSocket = new ServerSocket(portNumber); try { + serverSocket.setReuseAddress(true); System.out.println("Listening on port " + portNumber); - channel.socket().bind(new InetSocketAddress(portNumber)); - for (;;) - { + setLaunchedFlag(); + do + { try { - simulator=simFactory.create(); - simulator.suspend(); - moreParse(); - run(); + runGDBServer(); } catch (CPUException e) { e.printStackTrace(); - } - } + } + } while (manyGDBSessions); } finally { - channel.close(); + serverSocket.close(); } } catch (IOException e1) { e1.printStackTrace(); + } finally + { + setLaunchedFlag(); } } - private void run() throws CPUException + private void setLaunchedFlag() + { + synchronized(launched) + { + doneLaunching=true; + launched.notify(); + } + } + + public void createSimulator() + { + simulator=simFactory.create(); + simulator.suspend(); + } + + private void runGDBServer() throws CPUException { final GDBServer gdbServer=new GDBServer(simulator, this); simulator.setSyscall(gdbServer); @@ -98,7 +125,6 @@ public class SimApp } finally { - try { thread.join(); @@ -109,4 +135,43 @@ public class SimApp } } + + public Simulator getSimulator() + { + return simulator; + } + + public void setPort(int i) + { + portNumber=i; + } + + /** synchronous launch of GDB server */ + public void launchGDBServer() + { + Thread t=new Thread(new Runnable() + { + + public void run() + { + runSimAndGDB(); + } + }); + t.start(); + synchronized (launched) + { + while (!doneLaunching) + { + try + { + launched.wait(2000); + } catch (InterruptedException e) + { + e.printStackTrace(); + } + } + } + + + } } diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/Simulator.java b/zpu/sw/simulator/com/zylin/zpu/simulator/Simulator.java index c1b86d4..791e253 100644 --- a/zpu/sw/simulator/com/zylin/zpu/simulator/Simulator.java +++ b/zpu/sw/simulator/com/zylin/zpu/simulator/Simulator.java @@ -268,6 +268,8 @@ public class Simulator implements ZPU, Machine, Sim **/ private void dumpGmon() { + if (memory==null) + return; try { ByteArrayOutputStream b=new ByteArrayOutputStream(); diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/EndSessionException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/EndSessionException.java index 7dd27e0..13fc875 100644 --- a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/EndSessionException.java +++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/EndSessionException.java @@ -15,6 +15,30 @@ package com.zylin.zpu.simulator.exceptions; public class EndSessionException extends Exception { + public EndSessionException() + { + super(); + // TODO Auto-generated constructor stub + } + + public EndSessionException(String arg0, Throwable arg1) + { + super(arg0, arg1); + // TODO Auto-generated constructor stub + } + + public EndSessionException(String arg0) + { + super(arg0); + // TODO Auto-generated constructor stub + } + + public EndSessionException(Throwable arg0) + { + super(arg0); + // TODO Auto-generated constructor stub + } + /** * */ diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/gdb/GDBServer.java b/zpu/sw/simulator/com/zylin/zpu/simulator/gdb/GDBServer.java index 2580ded..182e426 100644 --- a/zpu/sw/simulator/com/zylin/zpu/simulator/gdb/GDBServer.java +++ b/zpu/sw/simulator/com/zylin/zpu/simulator/gdb/GDBServer.java @@ -5,6 +5,7 @@ package com.zylin.zpu.simulator.gdb; import java.io.IOException; +import java.net.Socket; import java.nio.ByteBuffer; import java.nio.channels.SelectionKey; import java.nio.channels.Selector; @@ -23,30 +24,25 @@ import com.zylin.zpu.simulator.exceptions.UnsupportedSyscallException; public class GDBServer implements Host { + /* logging filter */ static final boolean UNKNOWN=false; static final boolean ALL=false; static final boolean CPUEXCEPTION = false; static protected boolean MINIMAL=true; - static boolean PACKET=false; - static boolean REPLY=false; + static boolean PACKET=true; + static boolean REPLY=true; static protected boolean IGNOREDEXCEPTIONS=false; + + + protected Throwable packetException; protected Object packetReady=new Object(); private Packet packet; boolean done; - private Thread asyncMessage; - private Object listenBreak=new Object(); - private boolean listenForBreak; - private boolean sleeping; - private ByteBuffer readBuffer; - private ByteBuffer writeBuffer; - private SocketChannel sc; - private Selector selectorRead; - private Selector selectorWrite; + private Socket sc; public boolean alive; static private int sessionNr; private SimApp app; - private boolean stopAsyncMessage; Sim simulator; public GDBServer(Sim simulator, SimApp app) @@ -66,39 +62,10 @@ public class GDBServer implements Host /** infinite loop that waits for debug sessions to be initiated via TCP/IP */ public void gdbServer() throws MemoryAccessException, IOException, GDBServerException, EndSessionException { + sc=app.serverSocket.accept(); try { - asyncMessage = new Thread(new Runnable() - { - public void run() - { - asyncMessage(); - } - }); - asyncMessage.start(); - try - { - readBuffer = ByteBuffer.allocate(1); - writeBuffer = ByteBuffer.allocate(128); - debugSession(); - } - finally - { - /* tell it to stop waiting for break chars and wake up the thread */ - stopAsyncMessage = true; - synchronized(listenBreak) - { - listenBreak.notify(); - } - - try - { - asyncMessage.join(); - } catch (InterruptedException e3) - { - e3.printStackTrace(); - } - } + debugSession(); } catch (IOException e) { // the session failed... @@ -119,111 +86,12 @@ public class GDBServer implements Host { // some terrible unforseen failure. e.printStackTrace(); - } - } - - /** - * We have to wait for break, but as soon as the main thread wants to wait - * for packets again, we have to stop waiting for a break. - * - * Tricky.... - */ - private void asyncMessage() - { - for (;;) + } finally { - synchronized(listenBreak) - { - if (stopAsyncMessage) - { - /* shutting down */ - return; - } - try - { - sleeping=true; - listenBreak.notify(); - - listenBreak.wait(); - sleeping=false; - listenBreak.notify(); - } catch (InterruptedException e) - { - e.printStackTrace(); - } - if (stopAsyncMessage) - { - /* shutting down */ - return; - } - } - - while (listenForBreak) - { - try - { - if (waitSelect(selectorRead, true)) - { - int t = read(); - if (t == 0x03) - { - // We received a ctrl-c while processing a package, - // this - // would be a suspend - simulator.suspend(); - } else - { - // ignore garbage. Shouldn't happen. - } - } else - { - // we've been awoken since we're ready to send - // the reply to the package... -// int x=0; - } - } catch (IOException e) - { - // Perfectly normal. This would happen if the connection - // is terminated. - } - } + sc.close(); } } - /** wait for read/write ready */ - private boolean waitSelect(Selector selector, boolean read) throws IOException - { - boolean gotit=false; - - selector.select(1000); - if (!sc.isOpen()) - { - throw new IOException("Channel closed"); - } - if (!sc.isConnected()) - { - throw new IOException("Channel not connected"); - } - - // Get list of selection keys with pending events - Iterator it = selector.selectedKeys().iterator(); - // Process each key at a time - while (it.hasNext()) - { - // Get the selection key - SelectionKey selKey = (SelectionKey) it.next(); - // Remove it from the list to indicate that it is being - // processed - it.remove(); - if (selKey.isValid() && - ((read && selKey.isReadable()) || (!read && selKey.isWritable()))) - { - gotit=true; - } - - } - return gotit; - } protected void sleepABit() @@ -243,44 +111,18 @@ public class GDBServer implements Host { print(MINIMAL, "GDB server waiting for connection " + sessionNr++ + "..."); - writeBuffer.clear(); - readBuffer.clear(); - - - selectorRead = Selector.open(); try { - selectorWrite = Selector.open(); - try - { - sc = app.channel.accept(); - try - { - sc.socket().setKeepAlive(true); - sc.configureBlocking(false); - sc.register(selectorRead, SelectionKey.OP_READ); - sc.register(selectorWrite, SelectionKey.OP_WRITE); - - sessionStarted(); - - expect('+'); // connection ack. - - sessionLoop(); - } finally - { - sc.close(); - - print(MINIMAL, "Session ended"); - } - } finally - { - selectorWrite.close(); - } + sessionStarted(); + + expect('+'); // connection ack. + + sessionLoop(); } finally { - selectorRead.close(); + print(MINIMAL, "Session ended"); } - + } private void sessionStarted() @@ -301,19 +143,8 @@ public class GDBServer implements Host packet=new Packet(this); packet.receive(); - enterListenForCtrlC(); - - try - { - // During execution we can receive an abort/suspend command... - packet.parseAndExecute(); - } - finally - { - leaveListenForCtrlC(); - } - - packet.sendReply(); + // During execution we can receive an abort/suspend command... + packet.parseAndExecute(); if (!alive) throw new EndSessionException(); @@ -337,41 +168,6 @@ public class GDBServer implements Host } } - private void enterListenForCtrlC() - { - setBreakListen(true); - } - - private void leaveListenForCtrlC() - { - /* we don't want to wait for the select to time out as that would make - * the protocol excruciatingly slow */ - setBreakListen(false); - selectorRead.wakeup(); - synchronized(listenBreak) - { - try - { - while (!sleeping) - { - listenBreak.notify(); - listenBreak.wait(); - } - } catch (InterruptedException e) - { - e.printStackTrace(); - } - } - } - - private void setBreakListen(boolean state) - { - synchronized(listenBreak) - { - listenForBreak=state; - listenBreak.notify(); - } - } @@ -387,19 +183,9 @@ public class GDBServer implements Host int read() throws IOException { flush(); - readBuffer.clear(); - for (;;) - { - int n; - n = sc.read(readBuffer); - if (n == 1) - { - break; - } - while (!waitSelect(selectorRead, true)); - } - readBuffer.flip(); - int t = readBuffer.get(0); + int t=sc.getInputStream().read(); + if (t==-1) + throw new IOException(); return t; } @@ -429,42 +215,12 @@ public class GDBServer implements Host public void write(byte[] bytes) throws IOException { - int i=0; - while (i0) - { - writeBuffer.flip(); - int len=writeBuffer.limit(); - - int j=0; - while (j Date: Fri, 22 Feb 2008 17:38:08 +0000 Subject: * reduced memory for Phi to 2mByte to avoid Java heap out of memory. Why does Java have trouble allocating a meagre 32mByte long array? :-) --- zpu/sw/simulator/ChangeLog | 2 ++ zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java | 2 +- zpu/sw/simulator/com/zylin/zpu/simulator/Simulator.java | 2 +- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/zpu/sw/simulator/ChangeLog b/zpu/sw/simulator/ChangeLog index 18b0981..2f54967 100644 --- a/zpu/sw/simulator/ChangeLog +++ b/zpu/sw/simulator/ChangeLog @@ -1,4 +1,6 @@ 2008-02-22 Øyvind Harboe + * reduced memory for Phi to 2mByte to avoid Java heap out of memory. + Why does Java have trouble allocating a meagre 32mByte long array? :-) * Hooked up support for the simulator to the Zylin Embedded CDT 2007-08-04 Øyvind Harboe * First version after open sourcing ZPU diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java b/zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java index 0e3e7a1..663e68f 100644 --- a/zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java +++ b/zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java @@ -114,7 +114,7 @@ public class Phi extends Simulator protected int getRAMSIZE() { - return 32*1024*1024; + return 2*1024*1024; } diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/Simulator.java b/zpu/sw/simulator/com/zylin/zpu/simulator/Simulator.java index 791e253..cf6cf41 100644 --- a/zpu/sw/simulator/com/zylin/zpu/simulator/Simulator.java +++ b/zpu/sw/simulator/com/zylin/zpu/simulator/Simulator.java @@ -1942,7 +1942,7 @@ public class Simulator implements ZPU, Machine, Sim protected int getRAMSIZE() { - return (16*1024*1024); + return (2*1024*1024); } protected int getStartStack() -- cgit v1.1 From d2ee4c79d7b0abdfd70eaf2e46da54183a2caeaa Mon Sep 17 00:00:00 2001 From: oharboe Date: Thu, 6 Mar 2008 20:04:57 +0000 Subject: * zpu/zpu/hdl/example/zpuromgen.c - generate rom files without java --- zpu/ChangeLog | 3 +++ zpu/hdl/example/zpuromgen.c | 59 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+) create mode 100644 zpu/hdl/example/zpuromgen.c diff --git a/zpu/ChangeLog b/zpu/ChangeLog index 1e5545b..7878ea1 100644 --- a/zpu/ChangeLog +++ b/zpu/ChangeLog @@ -1,3 +1,6 @@ +2008-03-06 Adam Pierce + * zpu/zpu/hdl/example/zpuromgen.c - generate rom files + without java 2008-02-21 Øyvind Harboe * zpu/zpu/sw/index.html. Changed it a bit to make installation easier. * zpu/zpu/hdl/index.html. Sharpened instructions and shows two working diff --git a/zpu/hdl/example/zpuromgen.c b/zpu/hdl/example/zpuromgen.c new file mode 100644 index 0000000..fb8c4ba --- /dev/null +++ b/zpu/hdl/example/zpuromgen.c @@ -0,0 +1,59 @@ +// zpuromgen.c +// +// Program to turn a binary file into a VHDL lookup table. +// by Adam Pierce +// 29-Feb-2008 +// +// This software is free to use by anyone for any purpose. +// + +#include +#include + +typedef uint8_t BYTE; + +main(int argc, char **argv) +{ + BYTE opcode[4]; + int fd; + int addr = 0; + ssize_t s; + +// Check the user has given us an input file. + if(argc < 2) + { + printf("Usage: %s \n\n", argv[0]); + return 1; + } + +// Open the input file. + fd = open(argv[1], 0); + if(fd == -1) + { + perror("File Open"); + return 2; + } + + while(1) + { + // Read 32 bits. + s = read(fd, opcode, 4); + if(s == -1) + { + perror("File read"); + return 3; + } + + if(s == 0) + break; // End of file. + + // Output to STDOUT. + printf("%6d => x\"%02x%02x%02x%02x\",\n", + addr++, opcode[0], opcode[1], + opcode[2], opcode[3]); + } + + close(fd); + return 0; +} + -- cgit v1.1 From 830f2d5f90f9a864ad76a9d43a8fcf362ac2b18e Mon Sep 17 00:00:00 2001 From: oharboe Date: Sat, 5 Apr 2008 05:45:13 +0000 Subject: * zpu/docs/zpuphiregs.odt - ZPU Phi register overview --- zpu/.cvsignore | 1 + zpu/ChangeLog | 2 ++ zpu/docs/zpuphiregs.odt | Bin 0 -> 27013 bytes 3 files changed, 3 insertions(+) create mode 100644 zpu/.cvsignore create mode 100644 zpu/docs/zpuphiregs.odt diff --git a/zpu/.cvsignore b/zpu/.cvsignore new file mode 100644 index 0000000..7c32f55 --- /dev/null +++ b/zpu/.cvsignore @@ -0,0 +1 @@ +install diff --git a/zpu/ChangeLog b/zpu/ChangeLog index 7878ea1..8cc3b5b 100644 --- a/zpu/ChangeLog +++ b/zpu/ChangeLog @@ -1,3 +1,5 @@ +2008-04-05 Øyvind Harboe + * zpu/docs/zpuphiregs.odt - ZPU Phi register overview 2008-03-06 Adam Pierce * zpu/zpu/hdl/example/zpuromgen.c - generate rom files without java diff --git a/zpu/docs/zpuphiregs.odt b/zpu/docs/zpuphiregs.odt new file mode 100644 index 0000000..4b64d50 Binary files /dev/null and b/zpu/docs/zpuphiregs.odt differ -- cgit v1.1 From 4f29574821f2931771b30ee8e2be33030e7695a8 Mon Sep 17 00:00:00 2001 From: oharboe Date: Tue, 15 Apr 2008 05:58:32 +0000 Subject: * zpu/simzpu_bram.do - retired. * zpu/zpu_core_bram.vhd - retired * zpu/hdl/zpu3 - retired --- zpu/ChangeLog | 4 + zpu/hdl/zpu3/src/.cvsignore | 1 - zpu/hdl/zpu3/src/build.xml | 114 - zpu/hdl/zpu3/src/clocks.vhd | 246 -- zpu/hdl/zpu3/src/ddr_bridge.vhd | 203 -- zpu/hdl/zpu3/src/dmips_ram.vhd | 3824 -------------------- zpu/hdl/zpu3/src/dualport_ram.vhd | 4996 ------------------------- zpu/hdl/zpu3/src/dualport_ram_synplicity.vhd | 5012 -------------------------- zpu/hdl/zpu3/src/helloworld_ram.vhd | 3345 ----------------- zpu/hdl/zpu3/src/ic300.bitgen | 27 - zpu/hdl/zpu3/src/ic300.lso | 1 - zpu/hdl/zpu3/src/ic300.ucf | 146 - zpu/hdl/zpu3/src/ic300.vhd | 144 - zpu/hdl/zpu3/src/ic300_config.vhd | 20 - zpu/hdl/zpu3/src/ic300pkg.vhd | 88 - zpu/hdl/zpu3/src/io.vhd | 95 - zpu/hdl/zpu3/src/log.txt | 156 - zpu/hdl/zpu3/src/niltrace.vhd | 26 - zpu/hdl/zpu3/src/sim_fpga_top.vhd | 127 - zpu/hdl/zpu3/src/status.txt | 67 - zpu/hdl/zpu3/src/testlut.vhd | 106 - zpu/hdl/zpu3/src/timer.vhd | 157 - zpu/hdl/zpu3/src/trace.vhd | 80 - zpu/hdl/zpu3/src/txt_util.vhd | 586 --- zpu/hdl/zpu3/src/xilinx_dualport.vhd | 1482 -------- zpu/hdl/zpu3/src/xmake.filelist | 5 - zpu/hdl/zpu3/src/xmake.xst | 53 - zpu/hdl/zpu3/src/zpu_config.vhd | 25 - zpu/hdl/zpu3/src/zpu_pipelined.vhd | 852 ----- zpu/hdl/zpu3/src/zpu_top.vhd | 421 --- zpu/hdl/zpu3/src/zpu_top_medium.vhd | 768 ---- zpu/hdl/zpu3/src/zpuio.vhd | 180 - zpu/hdl/zpu3/src/zpupkg.vhd | 130 - zpu/hdl/zpu4/src/simzpu_bram.do | 28 - zpu/hdl/zpu4/src/zpu_core_bram.vhd | 780 ---- zpu/roadshow/roadshow/helloworld/test.c | 1 + 36 files changed, 5 insertions(+), 24291 deletions(-) delete mode 100644 zpu/hdl/zpu3/src/.cvsignore delete mode 100644 zpu/hdl/zpu3/src/build.xml delete mode 100644 zpu/hdl/zpu3/src/clocks.vhd delete mode 100644 zpu/hdl/zpu3/src/ddr_bridge.vhd delete mode 100644 zpu/hdl/zpu3/src/dmips_ram.vhd delete mode 100644 zpu/hdl/zpu3/src/dualport_ram.vhd delete mode 100644 zpu/hdl/zpu3/src/dualport_ram_synplicity.vhd delete mode 100644 zpu/hdl/zpu3/src/helloworld_ram.vhd delete mode 100644 zpu/hdl/zpu3/src/ic300.bitgen delete mode 100644 zpu/hdl/zpu3/src/ic300.lso delete mode 100644 zpu/hdl/zpu3/src/ic300.ucf delete mode 100644 zpu/hdl/zpu3/src/ic300.vhd delete mode 100644 zpu/hdl/zpu3/src/ic300_config.vhd delete mode 100644 zpu/hdl/zpu3/src/ic300pkg.vhd delete mode 100644 zpu/hdl/zpu3/src/io.vhd delete mode 100644 zpu/hdl/zpu3/src/log.txt delete mode 100644 zpu/hdl/zpu3/src/niltrace.vhd delete mode 100644 zpu/hdl/zpu3/src/sim_fpga_top.vhd delete mode 100644 zpu/hdl/zpu3/src/status.txt delete mode 100644 zpu/hdl/zpu3/src/testlut.vhd delete mode 100644 zpu/hdl/zpu3/src/timer.vhd delete mode 100644 zpu/hdl/zpu3/src/trace.vhd delete mode 100644 zpu/hdl/zpu3/src/txt_util.vhd delete mode 100644 zpu/hdl/zpu3/src/xilinx_dualport.vhd delete mode 100644 zpu/hdl/zpu3/src/xmake.filelist delete mode 100644 zpu/hdl/zpu3/src/xmake.xst delete mode 100644 zpu/hdl/zpu3/src/zpu_config.vhd delete mode 100644 zpu/hdl/zpu3/src/zpu_pipelined.vhd delete mode 100644 zpu/hdl/zpu3/src/zpu_top.vhd delete mode 100644 zpu/hdl/zpu3/src/zpu_top_medium.vhd delete mode 100644 zpu/hdl/zpu3/src/zpuio.vhd delete mode 100644 zpu/hdl/zpu3/src/zpupkg.vhd delete mode 100644 zpu/hdl/zpu4/src/simzpu_bram.do delete mode 100644 zpu/hdl/zpu4/src/zpu_core_bram.vhd diff --git a/zpu/ChangeLog b/zpu/ChangeLog index 8cc3b5b..e883d0d 100644 --- a/zpu/ChangeLog +++ b/zpu/ChangeLog @@ -1,3 +1,7 @@ +2008-04-15 Øyvind Harboe + * zpu/simzpu_bram.do - retired. + * zpu/zpu_core_bram.vhd - retired + * zpu/hdl/zpu3 - retired 2008-04-05 Øyvind Harboe * zpu/docs/zpuphiregs.odt - ZPU Phi register overview 2008-03-06 Adam Pierce diff --git a/zpu/hdl/zpu3/src/.cvsignore b/zpu/hdl/zpu3/src/.cvsignore deleted file mode 100644 index 760be11..0000000 --- a/zpu/hdl/zpu3/src/.cvsignore +++ /dev/null @@ -1 +0,0 @@ -xilinx_device_details.xml diff --git a/zpu/hdl/zpu3/src/build.xml b/zpu/hdl/zpu3/src/build.xml deleted file mode 100644 index e1b268a..0000000 --- a/zpu/hdl/zpu3/src/build.xml +++ /dev/null @@ -1,114 +0,0 @@ - - - - - - - eCosBoard firmware build file - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/zpu/hdl/zpu3/src/clocks.vhd b/zpu/hdl/zpu3/src/clocks.vhd deleted file mode 100644 index a352b3c..0000000 --- a/zpu/hdl/zpu3/src/clocks.vhd +++ /dev/null @@ -1,246 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library UNISIM; -use UNISIM.vcomponents.all; - -entity clocks is - port ( areset : in std_logic; - cpu_clk_p : in std_logic; - sdr_clk_fb_p : in std_logic; - cpu_clk : out std_logic; - cpu_clk_2x : out std_logic; - cpu_clk_4x : out std_logic; - ddr_in_clk : out std_logic; - ddr_in_clk_2x : out std_logic; - locked : out std_logic_vector(2 downto 0)); -end clocks; - -architecture behave of clocks is - -signal low : std_logic; - -signal cpu_clk_in : std_logic; -signal sdr_clk_fb_in : std_logic; - -signal dcm_cpu1 : std_logic; -signal dcm_cpu2 : std_logic; -signal dcm_cpu2_dum : std_logic; -signal dcm_cpu4 : std_logic; -signal dcm_ddr2 : std_logic; -signal dcm_ddr2_2x : std_logic; - -signal cpu_clk_int : std_logic; -signal cpu_clk_2x_int : std_logic; -signal cpu_clk_2x_dum_int : std_logic; -signal cpu_clk_4x_int : std_logic; -signal ddr_in_clk_int : std_logic; -signal ddr_in_clk_2x_int : std_logic; - -signal dcm1_locked_del : std_logic; -signal dcm2_locked_del : std_logic; -signal dcm2_reset : std_logic; -signal dcm3_reset : std_logic; - -signal locked_int : std_logic_vector(2 downto 0); -signal del_addr : std_logic_vector(3 downto 0); - -begin - - low <= '0'; - del_addr <= "1111"; - - cpu_clk <= cpu_clk_int; - cpu_clk_2x <= cpu_clk_2x_int; - cpu_clk_4x <= cpu_clk_4x_int; - ddr_in_clk <= ddr_in_clk_int; - ddr_in_clk_2x <= ddr_in_clk_2x_int; - locked <= locked_int; - - - CPU_IBUFG: - IBUFG port map ( - O => cpu_clk_in, - I => cpu_clk_p); - - SDR_FB_IBUFG: - IBUFG port map ( - O => sdr_clk_fb_in, - I => sdr_clk_fb_p); - - dcm2_rst: - SRL16 generic map ( - INIT => X"0000") - port map ( - Q => dcm1_locked_del, - A0 => del_addr(0), - A1 => del_addr(1), - A2 => del_addr(2), - A3 => del_addr(3), - CLK => cpu_clk_int, - D => locked_int(0)); - - dcm2_reset <= not(dcm1_locked_del); - - dcm3_rst: - SRL16 generic map ( - INIT => X"0000") - port map ( - Q => dcm2_locked_del, - A0 => del_addr(0), - A1 => del_addr(1), - A2 => del_addr(2), - A3 => del_addr(3), - CLK => cpu_clk_int, - D => locked_int(1)); - - dcm3_reset <= not(dcm2_locked_del); - - cpu1_dcm: - DCM generic map ( - CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 - -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 - CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 - CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32 - CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature - CLKIN_PERIOD => 15.625, -- Specify period of input clock - CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE - CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X - DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or - -- an integer from 0 to 15 - DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis - DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL - DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE - FACTORY_JF => X"8080", -- FACTORY JF Values - PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 - STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE - port map ( - CLK0 => dcm_cpu1, -- 0 degree DCM CLK ouptput - CLK180 => open, -- 180 degree DCM CLK output - CLK270 => open, -- 270 degree DCM CLK output - CLK2X => dcm_cpu2, -- 2X DCM CLK output - CLK2X180 => open, -- 2X, 180 degree DCM CLK out - CLK90 => open, -- 90 degree DCM CLK output - CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) - CLKFX => open, -- DCM CLK synthesis out (M/D) - CLKFX180 => open, -- 180 degree CLK synthesis out - LOCKED => locked_int(0), -- DCM LOCK status output - PSDONE => open, -- Dynamic phase adjust done output - STATUS => open, -- 8-bit DCM status bits output - CLKFB => cpu_clk_int, -- DCM clock feedback - CLKIN => cpu_clk_in, -- Clock input (from IBUFG, BUFG or DCM) - PSCLK => low, -- Dynamic phase adjust clock input - PSEN => low, -- Dynamic phase adjust enable input - PSINCDEC => low, -- Dynamic phase adjust increment/decrement - RST => areset); -- DCM asynchronous reset input - - cpu2_dcm: - DCM generic map ( - CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 - -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 - CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 - CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32 - CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature - CLKIN_PERIOD => 7.8125, -- Specify period of input clock - CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE - CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X - DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or - -- an integer from 0 to 15 - DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis - DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL - DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE - FACTORY_JF => X"8080", -- FACTORY JF Values - PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 - STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE - port map ( - CLK0 => dcm_cpu2_dum, -- 0 degree DCM CLK ouptput - CLK180 => open, -- 180 degree DCM CLK output - CLK270 => open, -- 270 degree DCM CLK output - CLK2X => dcm_cpu4, -- 2X DCM CLK output - CLK2X180 => open, -- 2X, 180 degree DCM CLK out - CLK90 => open, -- 90 degree DCM CLK output - CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) - CLKFX => open, -- DCM CLK synthesis out (M/D) - CLKFX180 => open, -- 180 degree CLK synthesis out - LOCKED => locked_int(1), -- DCM LOCK status output - PSDONE => open, -- Dynamic phase adjust done output - STATUS => open, -- 8-bit DCM status bits output - CLKFB => cpu_clk_2x_dum_int, -- DCM clock feedback - CLKIN => cpu_clk_2x_int, -- Clock input (from IBUFG, BUFG or DCM) - PSCLK => low, -- Dynamic phase adjust clock input - PSEN => low, -- Dynamic phase adjust enable input - PSINCDEC => low, -- Dynamic phase adjust increment/decrement - RST => dcm2_reset); -- DCM asynchronous reset input - - ddr_read_dcm: - DCM generic map ( - CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 - -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 - CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 - CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32 - CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature - CLKIN_PERIOD => 7.8125, -- Specify period of input clock - CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift of NONE, FIXED or VARIABLE --- CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE - CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X - DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or - -- an integer from 0 to 15 - DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis - DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL - DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE - FACTORY_JF => X"8080", -- FACTORY JF Values - PHASE_SHIFT => 103, -- Amount of fixed phase shift from -255 to 255 --- PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 - STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE - port map ( - CLK0 => dcm_ddr2, -- 0 degree DCM CLK ouptput - CLK180 => open, -- 180 degree DCM CLK output - CLK270 => open, -- 270 degree DCM CLK output - CLK2X => dcm_ddr2_2x, -- 2X DCM CLK output - CLK2X180 => open, -- 2X, 180 degree DCM CLK out - CLK90 => open, -- 90 degree DCM CLK output - CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) - CLKFX => open, -- DCM CLK synthesis out (M/D) - CLKFX180 => open, -- 180 degree CLK synthesis out - LOCKED => locked_int(2), -- DCM LOCK status output - PSDONE => open, -- Dynamic phase adjust done output - STATUS => open, -- 8-bit DCM status bits output - CLKFB => ddr_in_clk_int, -- DCM clock feedback - CLKIN => sdr_clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM) - PSCLK => low, -- Dynamic phase adjust clock input - PSEN => low, -- Dynamic phase adjust enable input - PSINCDEC => low, -- Dynamic phase adjust increment/decrement - RST => dcm3_reset); -- DCM asynchronous reset input - - cpu1: - BUFG port map ( - I => dcm_cpu1, - O => cpu_clk_int); - - cpu2: - BUFG port map ( - I => dcm_cpu2, - O => cpu_clk_2x_int); - - cpu2_dum: - BUFG port map ( - I => dcm_cpu2_dum, - O => cpu_clk_2x_dum_int); - - cpu4: - BUFG port map ( - I => dcm_cpu4, - O => cpu_clk_4x_int); - - ddr_clk: - BUFG port map ( - I => dcm_ddr2, - O => ddr_in_clk_int); - - ddr_clk_2x: - BUFG port map ( - I => dcm_ddr2_2x, - O => ddr_in_clk_2x_int); - -end behave; \ No newline at end of file diff --git a/zpu/hdl/zpu3/src/ddr_bridge.vhd b/zpu/hdl/zpu3/src/ddr_bridge.vhd deleted file mode 100644 index 7dece76..0000000 --- a/zpu/hdl/zpu3/src/ddr_bridge.vhd +++ /dev/null @@ -1,203 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library UNISIM; -use UNISIM.vcomponents.all; - -library zylin; -use zylin.ddr.all; - -library work; -use work.phi_config.all; - -entity ddr_bridge is - port ( areset : in std_logic; - cpu_clk : in std_logic; - cpu_clk_2x : in std_logic; - cpu_clk_4x : in std_logic; - ddr_in_clk : in std_logic; - ddr_in_clk_2x : in std_logic; - - cpu_we : in std_logic_vector(1 downto 0); - cpu_re : in std_logic; - cpu_din : in std_logic_vector(15 downto 0); - cpu_a : in std_logic_vector(20 downto 0); - cpu_dout : inout std_logic_vector(15 downto 0); - - sdr_clk_p : out std_logic; -- ddr_sdram_clock - sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock - cke_q_p : out std_logic; -- clock enable - cs_qn_p : out std_logic; -- /chip select - ras_qn_p : inout std_logic; -- /ras - cas_qn_p : inout std_logic; -- /cas - we_qn_p : inout std_logic; -- /write enable - dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00" - dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write - ba_q_p : out std_logic_vector(1 downto 0); -- bank select - sdr_a_p : out std_logic_vector(12 downto 0); -- address bus - sdr_d_p : inout std_logic_vector(15 downto 0)); -- bidir data bus -end ddr_bridge; - -architecture behave of ddr_bridge is - -signal refresh_en : std_logic; -signal ddr_command_we : std_logic; -signal ddr_command : std_logic_vector(15 downto 0); - -signal ddr_req : std_logic; -signal ddr_req_adr : std_logic_vector(23 downto 1); -signal ddr_rd_wr_n : std_logic; -signal ddr_req_len : std_logic; - -signal ddr_read_en : std_logic; -signal ddr_write_en : std_logic; -signal ddr_data_read : std_logic_vector(31 downto 0); -signal ddr_data_write : std_logic_vector(35 downto 0); - -signal ddr_read_smp : std_logic_vector(31 downto 0); -signal ddr_read_delay : std_logic_vector(15 downto 0); - -signal ddr_write_smp : std_logic_vector(15 downto 0); -signal ddr_addr_smp : std_logic_vector(15 downto 0); - -signal ddr_req_type_smp : std_logic; -signal ddr_req_on : std_logic; -signal ddr_req_off : std_logic; -signal ddr_req_int : std_logic; - -constant Sim_Delay : time := 1.0 ns; - -begin - - ddr_req_len <= '0'; - ddr_data_write <= "0000" & ddr_write_smp & ddr_write_smp; - ddr_req_adr <= "0000000" & ddr_addr_smp; - ddr_rd_wr_n <= ddr_req_type_smp; - ddr_req <= ddr_req_int; - - process(cpu_clk, areset) -- CPU writeable registers - begin - if areset = '1' then - refresh_en <= '0'; - ddr_command_we <= '0'; - ddr_command <= "0000000000000000"; - ddr_write_smp <= "0000000000000000"; - ddr_req_type_smp <= '0'; - ddr_req_on <= '0'; - elsif (cpu_clk'event and cpu_clk = '1') then - - if cpu_we(0) = '1' and cpu_a(19 downto 17) = Fpga_DDR_Ctrl_Base and cpu_a(3 downto 1) = DDR_Ctrl_Reg_Addr then - refresh_en <= cpu_din(0); - else - refresh_en <= refresh_en; - end if; - - if cpu_we(0) = '1' and cpu_a(19 downto 17) = Fpga_DDR_Ctrl_Base and cpu_a(3 downto 1) = DDR_Mode_Reg_Addr then - ddr_command <= cpu_din; - ddr_command_we <= '1'; - else - ddr_command <= ddr_command; - ddr_command_we <= '0'; - end if; - - if cpu_we(0) = '1' and cpu_a(19 downto 17) = Fpga_DDR_Ctrl_Base and cpu_a(3 downto 1) = DDR_Data_Reg_Addr then - ddr_write_smp <= cpu_din; - else - ddr_write_smp <= ddr_write_smp; - end if; - - if cpu_we(0) = '1' and cpu_a(19 downto 17) = Fpga_DDR_Ctrl_Base and cpu_a(3 downto 1) = DDR_Addr_Reg_Addr then - ddr_addr_smp <= cpu_din; - else - ddr_addr_smp <= ddr_addr_smp; - end if; - - if cpu_we(0) = '1' and cpu_a(19 downto 17) = Fpga_DDR_Ctrl_Base and cpu_a(3 downto 1) = DDR_Req_Reg_Addr then - ddr_req_type_smp <= cpu_din(0); - ddr_req_on <= '1'; - else - ddr_req_type_smp <= ddr_req_type_smp; - ddr_req_on <= '0'; - end if; - - end if; - end process; - - -- CPU readable registers - cpu_dout <= ddr_read_delay when (cpu_re = '1' and cpu_a(19 downto 17) = Fpga_DDR_Ctrl_Base and cpu_a(3 downto 1) = DDR_Data_Reg_Addr) else "ZZZZZZZZZZZZZZZZ"; - - -- Capture data read from DDR - process(cpu_clk_2x, areset) - begin - if areset = '1' then - ddr_read_smp <= (others => '0'); - elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then - if ddr_read_en = '1' then - ddr_read_smp <= ddr_data_read after Sim_Delay; - else - ddr_read_smp <= ddr_read_smp after Sim_Delay; - end if; - end if; - end process; - - -- Move captured data from DDR to cpu_clk domain (for better routing timing) - process(cpu_clk, areset) - begin - if areset = '1' then - ddr_read_delay <= "0000000000000000"; - elsif (cpu_clk'event and cpu_clk = '1') then - ddr_read_delay <= ddr_read_smp(15 downto 0); - end if; - end process; - - process(cpu_clk_2x, areset) - begin - if areset = '1' then - ddr_req_int <= '0'; - elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then - if ddr_req_on = '1' then - ddr_req_int <= '1' after Sim_Delay; - elsif ddr_read_en = '1' or ddr_write_en = '1' then - ddr_req_int <= '0' after Sim_Delay; - else - ddr_req_int <= ddr_req_int after Sim_Delay; - end if; - end if; - end process; - - - ddr_interface: - ddr_top port map( - areset => areset, - cpu_clk => cpu_clk, - cpu_clk_2x => cpu_clk_2x, - cpu_clk_4x => cpu_clk_4x, - ddr_in_clk => ddr_in_clk, - ddr_in_clk_2x => ddr_in_clk_2x, - ddr_command => ddr_command, - ddr_command_we => ddr_command_we, - refresh_en => refresh_en, - ddr_data_read => ddr_data_read, - ddr_data_write => ddr_data_write, - ddr_req => ddr_req, - ddr_req_adr => ddr_req_adr, - ddr_rd_wr_n => ddr_rd_wr_n, - ddr_req_len => ddr_req_len, - ddr_read_en => ddr_read_en, - ddr_write_en => ddr_write_en, - sdr_clk_p => sdr_clk_p, - sdr_clk_n_p => sdr_clk_n_p, - cke_q_p => cke_q_p, - cs_qn_p => cs_qn_p, - ras_qn_p => ras_qn_p, - cas_qn_p => cas_qn_p, - we_qn_p => we_qn_p, - dm_q_p => dm_q_p, - dqs_q_p => dqs_q_p, - ba_q_p => ba_q_p, - sdr_a_p => sdr_a_p, - sdr_d_p => sdr_d_p); - - -end behave; diff --git a/zpu/hdl/zpu3/src/dmips_ram.vhd b/zpu/hdl/zpu3/src/dmips_ram.vhd deleted file mode 100644 index f472653..0000000 --- a/zpu/hdl/zpu3/src/dmips_ram.vhd +++ /dev/null @@ -1,3824 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - - -library zylin; -use zylin.zpu_config.all; -use zylin.zpupkg.all; - -entity dualport_ram is -port (clk : in std_logic; - memAWriteEnable : in std_logic; - memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit); - memAWrite : in std_logic_vector(wordSize-1 downto 0); - memARead : out std_logic_vector(wordSize-1 downto 0); - memBWriteEnable : in std_logic; - memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit); - memBWrite : in std_logic_vector(wordSize-1 downto 0); - memBRead : out std_logic_vector(wordSize-1 downto 0)); -end dualport_ram; - -architecture dualport_ram_arch of dualport_ram is - - -type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); - -shared variable ram : ram_type := -( -0 => x"800b0b0b", -1 => x"0b0b8070", -2 => x"0b0b80e5", -3 => x"d00c3a0b", -4 => x"0b0bbed7", -5 => x"04000000", -6 => x"00000000", -7 => x"00000000", -8 => x"80088408", -9 => x"88080b0b", -10 => x"0bbfa72d", -11 => x"880c840c", -12 => x"800c0400", -13 => x"00000000", -14 => x"00000000", -15 => x"00000000", -16 => x"71fd0608", -17 => x"72830609", -18 => x"81058205", -19 => x"832b2a83", -20 => x"ffff0652", -21 => x"0b0b0400", -22 => x"00000000", -23 => x"00000000", -24 => x"71fd0608", -25 => x"83ffff73", -26 => x"83060981", -27 => x"05820583", -28 => x"2b2b0906", -29 => x"7383ffff", -30 => x"0b0b0b0b", -31 => x"83a70400", -32 => x"72098105", -33 => x"72057373", -34 => x"09060906", -35 => x"73097306", -36 => x"070a8106", -37 => x"530b0b51", -38 => x"04000000", -39 => x"00000000", -40 => x"72722473", -41 => x"732e0753", -42 => x"0b0b5104", -43 => x"00000000", -44 => x"00000000", -45 => x"00000000", -46 => x"00000000", -47 => x"00000000", -48 => x"71737109", -49 => x"71068106", -50 => x"30720a10", -51 => x"0a720a10", -52 => x"0a31050a", -53 => x"81065151", -54 => x"530b0b51", -55 => x"04000000", -56 => x"72722673", -57 => x"732e0753", -58 => x"0b0b5104", -59 => x"00000000", -60 => x"00000000", -61 => x"00000000", -62 => x"00000000", -63 => x"00000000", -64 => x"00000000", -65 => x"00000000", -66 => x"00000000", -67 => x"00000000", -68 => x"00000000", -69 => x"00000000", -70 => x"00000000", -71 => x"00000000", -72 => x"0b0b0b88", -73 => x"c6040000", -74 => x"00000000", -75 => x"00000000", -76 => x"00000000", -77 => x"00000000", -78 => x"00000000", -79 => x"00000000", -80 => x"720a722b", -81 => x"0a530b0b", -82 => x"51040000", -83 => x"00000000", -84 => x"00000000", -85 => x"00000000", -86 => x"00000000", -87 => x"00000000", -88 => x"72729f06", -89 => x"0981050b", -90 => x"0b0b88a7", -91 => x"05040000", -92 => x"00000000", -93 => x"00000000", -94 => x"00000000", -95 => x"00000000", -96 => x"72722aff", -97 => x"739f062a", -98 => x"0974090a", -99 => x"8106ff05", -100 => x"0607530b", -101 => x"0b510400", -102 => x"00000000", -103 => x"00000000", -104 => x"7171530b", -105 => x"0b510406", -106 => x"73830609", -107 => x"81058205", -108 => x"832b0b2b", -109 => x"0772fc06", -110 => x"0c515104", -111 => x"00000000", -112 => x"72098105", -113 => x"72050970", -114 => x"81050906", -115 => x"0a810653", -116 => x"0b0b5104", -117 => x"00000000", -118 => x"00000000", -119 => x"00000000", -120 => x"72098105", -121 => x"72050970", -122 => x"81050906", -123 => x"0a098106", -124 => x"530b0b51", -125 => x"04000000", -126 => x"00000000", -127 => x"00000000", -128 => x"71098105", -129 => x"520b0b04", -130 => x"00000000", -131 => x"00000000", -132 => x"00000000", -133 => x"00000000", -134 => x"00000000", -135 => x"00000000", -136 => x"72720981", -137 => x"0505530b", -138 => x"0b510400", -139 => x"00000000", -140 => x"00000000", -141 => x"00000000", -142 => x"00000000", -143 => x"00000000", -144 => x"72097206", -145 => x"73730906", -146 => x"07530b0b", -147 => x"51040000", -148 => x"00000000", -149 => x"00000000", -150 => x"00000000", -151 => x"00000000", -152 => x"71fc0608", -153 => x"72830609", -154 => x"81058305", -155 => x"1010102a", -156 => x"81ff0652", -157 => x"0b0b0400", -158 => x"00000000", -159 => x"00000000", -160 => x"71fc0608", -161 => x"0b0b80e5", -162 => x"bc738306", -163 => x"10100508", -164 => x"060b0b0b", -165 => x"88ac0400", -166 => x"00000000", -167 => x"00000000", -168 => x"80088408", -169 => x"88087575", -170 => x"0b0b0ba3", -171 => x"fa2d5050", -172 => x"80085688", -173 => x"0c840c80", -174 => x"0c510400", -175 => x"00000000", -176 => x"80088408", -177 => x"88087575", -178 => x"0b0b0ba4", -179 => x"ca2d5050", -180 => x"80085688", -181 => x"0c840c80", -182 => x"0c510400", -183 => x"00000000", -184 => x"72097081", -185 => x"0509060a", -186 => x"8106ff05", -187 => x"70540b0b", -188 => x"71067309", -189 => x"727405ff", -190 => x"05060751", -191 => x"51510400", -192 => x"72097081", -193 => x"0509060a", -194 => x"098106ff", -195 => x"0570540b", -196 => x"0b710673", -197 => x"09727405", -198 => x"ff050607", -199 => x"51515104", -200 => x"05ff0504", -201 => x"00000000", -202 => x"00000000", -203 => x"00000000", -204 => x"00000000", -205 => x"00000000", -206 => x"00000000", -207 => x"00000000", -208 => x"810b0b0b", -209 => x"80e5cc0c", -210 => x"51040000", -211 => x"00000000", -212 => x"00000000", -213 => x"00000000", -214 => x"00000000", -215 => x"00000000", -216 => x"71810552", -217 => x"0b0b0400", -218 => x"00000000", -219 => x"00000000", -220 => x"00000000", -221 => x"00000000", -222 => x"00000000", -223 => x"00000000", -224 => x"00000000", -225 => x"00000000", -226 => x"00000000", -227 => x"00000000", -228 => x"00000000", -229 => x"00000000", -230 => x"00000000", -231 => x"00000000", -232 => x"02840572", -233 => x"10100552", -234 => x"0b0b0400", -235 => x"00000000", -236 => x"00000000", -237 => x"00000000", -238 => x"00000000", -239 => x"00000000", -240 => x"00000000", -241 => x"00000000", -242 => x"00000000", -243 => x"00000000", -244 => x"00000000", -245 => x"00000000", -246 => x"00000000", -247 => x"00000000", -248 => x"717105ff", -249 => x"0571530b", -250 => x"0b510400", -251 => x"00000000", -252 => x"00000000", -253 => x"00000000", -254 => x"00000000", -255 => x"00000000", -256 => x"84803f80", -257 => x"cef23f04", -258 => x"10101010", -259 => x"10101010", -260 => x"10101010", -261 => x"10101010", -262 => x"10101010", -263 => x"10101010", -264 => x"10101010", -265 => x"10101053", -266 => x"0b0b5104", -267 => x"7381ff06", -268 => x"73830609", -269 => x"81058305", -270 => x"1010102b", -271 => x"0772fc06", -272 => x"0c515104", -273 => x"3c047272", -274 => x"80728106", -275 => x"ff050972", -276 => x"06057110", -277 => x"520b0b72", -278 => x"0a100a53", -279 => x"0b0b72e9", -280 => x"38515153", -281 => x"0b0b5104", -282 => x"70700b0b", -283 => x"80f5c008", -284 => x"520b0b84", -285 => x"0b720508", -286 => x"70810651", -287 => x"510b0b70", -288 => x"f2387108", -289 => x"81ff0680", -290 => x"0c505004", -291 => x"70700b0b", -292 => x"80f5c008", -293 => x"520b0b84", -294 => x"0b720508", -295 => x"700a100a", -296 => x"70810651", -297 => x"51510b0b", -298 => x"70ed3873", -299 => x"720c5050", -300 => x"0480e5cc", -301 => x"08802ea8", -302 => x"38838080", -303 => x"0b0b0b80", -304 => x"f5c00c82", -305 => x"a0800b0b", -306 => x"0b80f5c4", -307 => x"0c829080", -308 => x"0b80f5d4", -309 => x"0c0b0b80", -310 => x"f5c80b80", -311 => x"f5d80c04", -312 => x"f8808080", -313 => x"a40b0b0b", -314 => x"80f5c00c", -315 => x"f8808082", -316 => x"800b0b0b", -317 => x"80f5c40c", -318 => x"f8808084", -319 => x"800b80f5", -320 => x"d40cf880", -321 => x"8080940b", -322 => x"80f5d80c", -323 => x"f8808080", -324 => x"9c0b80f5", -325 => x"d00cf880", -326 => x"8080a00b", -327 => x"80f5dc0c", -328 => x"04f23d0d", -329 => x"600b0b80", -330 => x"f5c40856", -331 => x"5d82750c", -332 => x"8059805a", -333 => x"800b8f3d", -334 => x"71101017", -335 => x"70085957", -336 => x"5d5b8076", -337 => x"81ff067c", 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x"00003430", -3343 => x"00003430", -3344 => x"00003438", -3345 => x"00003438", -3346 => x"00003440", -3347 => x"00003440", -3348 => x"00003448", -3349 => x"00003448", -3350 => x"00003450", -3351 => x"00003450", -3352 => x"00003458", -3353 => x"00003458", -3354 => x"00003460", -3355 => x"00003460", -3356 => x"00003468", -3357 => x"00003468", -3358 => x"00003470", -3359 => x"00003470", -3360 => x"00003478", -3361 => x"00003478", -3362 => x"00003480", -3363 => x"00003480", -3364 => x"00003488", -3365 => x"00003488", -3366 => x"00003490", -3367 => x"00003490", -3368 => x"00003498", -3369 => x"00003498", -3370 => x"000034a0", -3371 => x"000034a0", -3372 => x"000034a8", -3373 => x"000034a8", -3374 => x"000034b0", -3375 => x"000034b0", -3376 => x"000034b8", -3377 => x"000034b8", -3378 => x"000034c0", -3379 => x"000034c0", -3380 => x"000034c8", -3381 => x"000034c8", -3382 => x"000034d0", -3383 => x"000034d0", -3384 => x"000034d8", -3385 => x"000034d8", -3386 => x"000034e0", -3387 => x"000034e0", -3388 => x"000034e8", -3389 => x"000034e8", -3390 => x"000034f0", -3391 => x"000034f0", -3392 => x"000034f8", -3393 => x"000034f8", -3394 => x"00003500", -3395 => x"00003500", -3396 => x"00003508", -3397 => x"00003508", -3398 => x"00003510", -3399 => x"00003510", -3400 => x"00003518", -3401 => x"00003518", -3402 => x"00003520", -3403 => x"00003520", -3404 => x"00003528", -3405 => x"00003528", -3406 => x"00003530", -3407 => x"00003530", -3408 => x"00003538", -3409 => x"00003538", -3410 => x"00003540", -3411 => x"00003540", -3412 => x"00003548", -3413 => x"00003548", -3414 => x"00003550", -3415 => x"00003550", -3416 => x"00003558", -3417 => x"00003558", -3418 => x"00003560", -3419 => x"00003560", -3420 => x"00003568", -3421 => x"00003568", -3422 => x"00003570", -3423 => x"00003570", -3424 => x"00003578", -3425 => x"00003578", -3426 => x"00003580", -3427 => x"00003580", -3428 => x"00003588", -3429 => x"00003588", -3430 => x"00003590", -3431 => x"00003590", -3432 => x"00003598", -3433 => x"00003598", -3434 => x"000035a0", -3435 => x"000035a0", -3436 => x"000035a8", -3437 => x"000035a8", -3438 => x"000035b0", -3439 => x"000035b0", -3440 => x"000035b8", -3441 => x"000035b8", -3442 => x"000035c0", -3443 => x"000035c0", -3444 => x"000035c8", -3445 => x"000035c8", -3446 => x"000035d0", -3447 => x"000035d0", -3448 => x"000035d8", -3449 => x"000035d8", -3450 => x"000035e0", -3451 => x"000035e0", -3452 => x"000035e8", -3453 => x"000035e8", -3454 => x"000035f0", -3455 => x"000035f0", -3456 => x"000035f8", -3457 => x"000035f8", -3458 => x"00003600", -3459 => x"00003600", -3460 => x"00003608", -3461 => x"00003608", -3462 => x"00003610", -3463 => x"00003610", -3464 => x"00003618", -3465 => x"00003618", -3466 => x"00003620", -3467 => x"00003620", -3468 => x"00003628", -3469 => x"00003628", -3470 => x"00003630", -3471 => x"00003630", -3472 => x"00003638", -3473 => x"00003638", -3474 => x"00003640", -3475 => x"00003640", -3476 => x"00003648", -3477 => x"00003648", -3478 => x"00003650", -3479 => x"00003650", -3480 => x"00003658", -3481 => x"00003658", -3482 => x"00003660", -3483 => x"00003660", -3484 => x"00003668", -3485 => x"00003668", -3486 => x"00003670", -3487 => x"00003670", -3488 => x"00003678", -3489 => x"00003678", -3490 => x"00003680", -3491 => x"00003680", -3492 => x"00003688", -3493 => x"00003688", -3494 => x"00003690", -3495 => x"00003690", -3496 => x"00003698", -3497 => x"00003698", -3498 => x"000036a0", -3499 => x"000036a0", -3500 => x"000036a8", -3501 => x"000036a8", -3502 => x"000036b0", -3503 => x"000036b0", -3504 => x"000036b8", -3505 => x"000036b8", -3506 => x"000036c0", -3507 => x"000036c0", -3508 => x"000036c8", -3509 => x"000036c8", -3510 => x"000036d0", -3511 => x"000036d0", -3512 => x"000036d8", -3513 => x"000036d8", -3514 => x"000036e0", -3515 => x"000036e0", -3516 => x"000036e8", -3517 => x"000036e8", -3518 => x"000036f0", -3519 => x"000036f0", -3520 => x"000036f8", -3521 => x"000036f8", -3522 => x"00003700", -3523 => x"00003700", -3524 => x"00003708", -3525 => x"00003708", -3526 => x"00003710", -3527 => x"00003710", -3528 => x"00003718", -3529 => x"00003718", -3530 => x"0000372c", -3531 => x"00000000", -3532 => x"00003994", -3533 => x"000039f0", -3534 => x"00003a4c", -3535 => x"00000000", -3536 => x"00000000", -3537 => x"00000000", -3538 => x"00000000", -3539 => x"00000000", -3540 => x"00000000", -3541 => x"00000000", -3542 => x"00000000", -3543 => x"00000000", -3544 => x"000031ac", -3545 => x"00000000", -3546 => x"00000000", -3547 => x"00000000", -3548 => x"00000000", -3549 => x"00000000", -3550 => x"00000000", -3551 => x"00000000", -3552 => x"00000000", -3553 => x"00000000", -3554 => x"00000000", -3555 => x"00000000", -3556 => x"00000000", -3557 => x"00000000", -3558 => x"00000000", -3559 => x"00000000", -3560 => x"00000000", -3561 => x"00000000", -3562 => x"00000000", -3563 => x"00000000", -3564 => x"00000000", -3565 => x"00000000", -3566 => x"00000000", -3567 => x"00000000", -3568 => x"00000000", -3569 => x"00000000", -3570 => x"00000000", -3571 => x"00000000", -3572 => x"00000000", -3573 => x"00000001", -3574 => x"330eabcd", -3575 => x"1234e66d", -3576 => x"deec0005", -3577 => x"000b0000", -3578 => x"00000000", -3579 => x"00000000", -3580 => x"00000000", -3581 => x"00000000", -3582 => x"00000000", -3583 => x"00000000", -3584 => x"00000000", -3585 => x"00000000", -3586 => x"00000000", -3587 => x"00000000", -3588 => x"00000000", -3589 => x"00000000", -3590 => x"00000000", -3591 => x"00000000", -3592 => x"00000000", -3593 => x"00000000", -3594 => x"00000000", -3595 => x"00000000", -3596 => x"00000000", -3597 => x"00000000", -3598 => x"00000000", -3599 => x"00000000", -3600 => x"00000000", -3601 => x"00000000", -3602 => x"00000000", -3603 => x"00000000", -3604 => x"00000000", -3605 => x"00000000", -3606 => x"00000000", -3607 => x"00000000", -3608 => x"00000000", -3609 => x"00000000", -3610 => x"00000000", -3611 => x"00000000", -3612 => x"00000000", -3613 => x"00000000", -3614 => x"00000000", -3615 => x"00000000", -3616 => x"00000000", -3617 => x"00000000", -3618 => x"00000000", -3619 => x"00000000", -3620 => x"00000000", -3621 => x"00000000", -3622 => x"00000000", -3623 => x"00000000", -3624 => x"00000000", -3625 => x"00000000", -3626 => x"00000000", -3627 => x"00000000", -3628 => x"00000000", -3629 => x"00000000", -3630 => x"00000000", -3631 => x"00000000", -3632 => x"00000000", -3633 => x"00000000", -3634 => x"00000000", -3635 => x"00000000", -3636 => x"00000000", -3637 => x"00000000", -3638 => x"00000000", -3639 => x"00000000", -3640 => x"00000000", -3641 => x"00000000", -3642 => x"00000000", -3643 => x"00000000", -3644 => x"00000000", -3645 => x"00000000", -3646 => x"00000000", -3647 => x"00000000", -3648 => x"00000000", -3649 => x"00000000", -3650 => x"00000000", -3651 => x"00000000", -3652 => x"00000000", -3653 => x"00000000", -3654 => x"00000000", -3655 => x"00000000", -3656 => x"00000000", -3657 => x"00000000", -3658 => x"00000000", -3659 => x"00000000", -3660 => x"00000000", -3661 => x"00000000", -3662 => x"00000000", -3663 => x"00000000", -3664 => x"00000000", -3665 => x"00000000", -3666 => x"00000000", -3667 => x"00000000", -3668 => x"00000000", -3669 => x"00000000", -3670 => x"00000000", -3671 => x"00000000", -3672 => x"00000000", -3673 => x"00000000", -3674 => x"00000000", -3675 => x"00000000", -3676 => x"00000000", -3677 => x"00000000", -3678 => x"00000000", -3679 => x"00000000", -3680 => x"00000000", -3681 => x"00000000", -3682 => x"00000000", -3683 => x"00000000", -3684 => x"00000000", -3685 => x"00000000", -3686 => x"00000000", -3687 => x"00000000", -3688 => x"00000000", -3689 => x"00000000", -3690 => x"00000000", -3691 => x"00000000", -3692 => x"00000000", -3693 => x"00000000", -3694 => x"00000000", -3695 => x"00000000", -3696 => x"00000000", -3697 => x"00000000", -3698 => x"00000000", -3699 => x"00000000", -3700 => x"00000000", -3701 => x"00000000", -3702 => x"00000000", -3703 => x"00000000", -3704 => x"00000000", -3705 => x"00000000", -3706 => x"00000000", -3707 => x"00000000", -3708 => x"00000000", -3709 => x"00000000", -3710 => x"00000000", -3711 => x"00000000", -3712 => x"00000000", -3713 => x"00000000", -3714 => x"00000000", -3715 => x"00000000", -3716 => x"00000000", -3717 => x"00000000", -3718 => x"00000000", -3719 => x"00000000", -3720 => x"00000000", -3721 => x"00000000", -3722 => x"00000000", -3723 => x"00000000", -3724 => x"00000000", -3725 => x"00000000", -3726 => x"00000000", -3727 => x"00000000", -3728 => x"00000000", -3729 => x"00000000", -3730 => x"00000000", -3731 => x"00000000", -3732 => x"00000000", -3733 => x"00000000", -3734 => x"00000000", -3735 => x"00000000", -3736 => x"00000000", -3737 => x"00000000", -3738 => x"00000000", -3739 => x"00000000", -3740 => x"00000000", -3741 => x"00000000", -3742 => x"00000000", -3743 => x"00000000", -3744 => x"00000000", -3745 => x"00000000", -3746 => x"00000000", -3747 => x"00000000", -3748 => x"00000000", -3749 => x"00000000", -3750 => x"00000000", -3751 => x"00000000", -3752 => x"00000000", -3753 => x"00000000", -3754 => x"000031b0", -3755 => x"ffffffff", -3756 => x"00000000", -3757 => x"ffffffff", -3758 => x"00000000", - others => x"00000000" -); - -begin - -process (clk) -begin - if (clk'event and clk = '1') then - if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then - report "write collision" severity failure; - end if; - - if (memAWriteEnable = '1') then - ram(conv_integer(memAAddr)) := memAWrite; - memARead <= memAWrite; - else - memARead <= ram(conv_integer(memAAddr)); - end if; - end if; -end process; - -process (clk) -begin - if (clk'event and clk = '1') then - if (memBWriteEnable = '1') then - ram(conv_integer(memBAddr)) := memBWrite; - memBRead <= memBWrite; - else - memBRead <= ram(conv_integer(memBAddr)); - end if; - end if; -end process; - - - - -end dualport_ram_arch; diff --git a/zpu/hdl/zpu3/src/dualport_ram.vhd b/zpu/hdl/zpu3/src/dualport_ram.vhd deleted file mode 100644 index 54380ce..0000000 --- a/zpu/hdl/zpu3/src/dualport_ram.vhd +++ /dev/null @@ -1,4996 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - - -library zylin; -use zylin.zpu_config.all; -use zylin.zpupkg.all; - -entity dualport_ram is -port (clk : in std_logic; - memAWriteEnable : in std_logic; - memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit); - memAWrite : in std_logic_vector(wordSize-1 downto 0); - memARead : out std_logic_vector(wordSize-1 downto 0); - memBWriteEnable : in std_logic; - memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit); - memBWrite : in std_logic_vector(wordSize-1 downto 0); - memBRead : out std_logic_vector(wordSize-1 downto 0)); -end dualport_ram; - -architecture dualport_ram_arch of dualport_ram is - - -type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); - -shared variable ram : ram_type := -( -0 => x"800b0b0b", -1 => x"0b0b8070", -2 => x"0b0b818a", -3 => x"880c3a0b", -4 => x"0b80fae8", -5 => x"04000000", -6 => x"00000000", -7 => x"00000000", -8 => x"80088408", -9 => x"88080b0b", -10 => x"80fbba2d", -11 => x"880c840c", -12 => x"800c0400", -13 => x"00000000", -14 => x"00000000", -15 => x"00000000", -16 => x"71fd0608", -17 => x"72830609", -18 => x"81058205", -19 => x"832b2a83", -20 => x"ffff0652", -21 => x"04000000", -22 => x"00000000", -23 => x"00000000", -24 => x"71fd0608", -25 => x"83ffff73", -26 => x"83060981", -27 => x"05820583", -28 => x"2b2b0906", -29 => x"7383ffff", -30 => x"0b0b0b0b", -31 => x"83a70400", -32 => x"72098105", -33 => x"72057373", -34 => x"09060906", -35 => x"73097306", -36 => x"070a8106", -37 => x"530b0b51", -38 => x"04000000", -39 => x"00000000", -40 => x"72722473", -41 => x"732e0753", -42 => x"0b0b5104", -43 => x"00000000", -44 => x"00000000", -45 => x"00000000", -46 => x"00000000", -47 => x"00000000", -48 => x"71737109", -49 => x"71068106", -50 => x"30720a10", -51 => x"0a720a10", -52 => x"0a31050a", -53 => x"81065151", -54 => x"530b0b51", -55 => x"04000000", -56 => x"72722673", -57 => x"732e0753", -58 => x"0b0b5104", -59 => x"00000000", -60 => x"00000000", -61 => x"00000000", -62 => x"00000000", -63 => x"00000000", -64 => x"00000000", -65 => x"00000000", -66 => x"00000000", -67 => x"00000000", -68 => x"00000000", -69 => x"00000000", -70 => x"00000000", -71 => x"00000000", -72 => x"72728072", -73 => x"8106ff05", -74 => x"09720605", -75 => x"71105272", -76 => x"0a100a53", -77 => x"0b0b72eb", -78 => x"38515153", -79 => x"0b0b5104", -80 => x"720a722b", -81 => x"0a530b0b", -82 => x"51040000", -83 => x"00000000", -84 => x"00000000", -85 => x"00000000", -86 => x"00000000", -87 => x"00000000", -88 => x"72729f06", -89 => x"0981050b", -90 => x"0b0b88a7", -91 => x"05040000", -92 => x"00000000", -93 => x"00000000", -94 => x"00000000", -95 => x"00000000", -96 => x"72722aff", -97 => x"739f062a", -98 => x"0974090a", -99 => x"8106ff05", -100 => x"0607530b", -101 => x"0b510400", -102 => x"00000000", -103 => x"00000000", -104 => x"7171530b", -105 => x"0b510406", -106 => x"73830609", -107 => x"81058205", -108 => x"832b0b2b", -109 => x"0772fc06", -110 => x"0c515104", -111 => x"00000000", -112 => x"72098105", -113 => x"72050970", -114 => x"81050906", -115 => x"0a810653", -116 => x"0b0b5104", -117 => x"00000000", -118 => x"00000000", -119 => x"00000000", -120 => x"72098105", -121 => x"72050970", -122 => x"81050906", -123 => x"0a098106", -124 => x"530b0b51", -125 => x"04000000", -126 => x"00000000", -127 => x"00000000", -128 => x"71098105", -129 => x"52040000", -130 => x"00000000", -131 => x"00000000", -132 => x"00000000", -133 => x"00000000", -134 => x"00000000", -135 => x"00000000", -136 => x"72720981", -137 => x"0505530b", -138 => x"0b510400", -139 => x"00000000", -140 => x"00000000", -141 => x"00000000", -142 => x"00000000", -143 => x"00000000", -144 => x"72097206", -145 => x"73730906", -146 => x"07530b0b", -147 => x"51040000", -148 => x"00000000", -149 => x"00000000", -150 => x"00000000", -151 => x"00000000", -152 => x"71fc0608", -153 => x"72830609", -154 => x"81058305", -155 => x"1010102a", -156 => x"81ff0652", -157 => x"04000000", -158 => x"00000000", -159 => x"00000000", -160 => x"71fc0608", -161 => x"0b0b8189", -162 => x"f4738306", -163 => x"10100508", -164 => x"060b0b0b", -165 => x"88ac0400", -166 => x"00000000", -167 => x"00000000", -168 => x"80088408", -169 => x"88087575", -170 => x"0b0b0b8f", -171 => x"e42d5050", -172 => x"80085688", -173 => x"0c840c80", -174 => x"0c510400", -175 => x"00000000", -176 => x"80088408", -177 => x"88087575", -178 => x"0b0b0b91", -179 => x"9c2d5050", -180 => x"80085688", -181 => x"0c840c80", -182 => x"0c510400", -183 => x"00000000", -184 => x"72097081", -185 => x"0509060a", -186 => x"8106ff05", -187 => x"70540b0b", -188 => x"71067309", -189 => x"727405ff", -190 => x"05060751", -191 => x"51510400", -192 => x"72097081", -193 => x"0509060a", -194 => x"098106ff", -195 => x"0570540b", -196 => x"0b710673", -197 => x"09727405", -198 => x"ff050607", -199 => x"51515104", -200 => x"05ff0504", -201 => x"00000000", -202 => x"00000000", -203 => x"00000000", -204 => x"00000000", -205 => x"00000000", -206 => x"00000000", -207 => x"00000000", -208 => x"810b0b0b", -209 => x"818a840c", -210 => x"51040000", -211 => x"00000000", -212 => x"00000000", -213 => x"00000000", -214 => x"00000000", -215 => x"00000000", -216 => x"71810552", -217 => x"04000000", -218 => x"00000000", -219 => x"00000000", -220 => x"00000000", -221 => x"00000000", -222 => x"00000000", -223 => x"00000000", -224 => x"00000000", -225 => x"00000000", -226 => x"00000000", -227 => x"00000000", -228 => x"00000000", -229 => x"00000000", -230 => x"00000000", -231 => x"00000000", -232 => x"02840572", -233 => x"10100552", -234 => x"04000000", -235 => x"00000000", -236 => x"00000000", -237 => x"00000000", -238 => x"00000000", -239 => x"00000000", -240 => x"00000000", -241 => x"00000000", -242 => x"00000000", -243 => x"00000000", -244 => x"00000000", -245 => x"00000000", -246 => x"00000000", -247 => x"00000000", -248 => x"717105ff", -249 => x"0571530b", -250 => x"0b510400", -251 => x"00000000", -252 => x"00000000", -253 => x"00000000", -254 => x"00000000", -255 => x"00000000", -256 => x"83cd3f80", -257 => x"fd803f04", -258 => x"10101010", -259 => x"10101010", -260 => x"10101010", -261 => x"10101010", -262 => x"10101010", -263 => x"10101010", -264 => x"10101010", -265 => x"10101053", -266 => x"0b0b5104", -267 => x"7381ff06", -268 => x"73830609", -269 => x"81058305", -270 => x"1010102b", -271 => x"0772fc06", -272 => x"0c515104", -273 => x"3c047070", -274 => x"0b0b819a", -275 => x"90085284", -276 => x"0b720508", -277 => x"70810651", -278 => x"510b0b70", -279 => x"f2387108", -280 => x"81ff0680", -281 => x"0c505004", -282 => x"70700b0b", -283 => x"819a9008", -284 => x"52840b72", -285 => x"0508700a", -286 => x"100a7081", -287 => x"06515151", -288 => x"0b0b70ed", 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x"00000000", -4602 => x"00000000", -4603 => x"00000000", -4604 => x"00000000", -4605 => x"00000000", -4606 => x"00000000", -4607 => x"00000000", -4608 => x"00000000", -4609 => x"00000000", -4610 => x"00000000", -4611 => x"00000000", -4612 => x"00000000", -4613 => x"00000000", -4614 => x"00000000", -4615 => x"00000000", -4616 => x"00000000", -4617 => x"00000000", -4618 => x"00000000", -4619 => x"00000000", -4620 => x"00000000", -4621 => x"00000000", -4622 => x"00000000", -4623 => x"00000000", -4624 => x"00000000", -4625 => x"00000000", -4626 => x"00000000", -4627 => x"00000000", -4628 => x"00000000", -4629 => x"00000000", -4630 => x"00000000", -4631 => x"00000000", -4632 => x"00000000", -4633 => x"00000000", -4634 => x"00000000", -4635 => x"00000000", -4636 => x"00000000", -4637 => x"00000000", -4638 => x"00000000", -4639 => x"00000000", -4640 => x"00000000", -4641 => x"00000000", -4642 => x"00000000", -4643 => x"00000000", -4644 => x"00000000", -4645 => x"43000000", -4646 => x"00000000", -4647 => x"00000000", -4648 => x"00000000", -4649 => x"00000000", -4650 => x"00000000", -4651 => x"00000001", -4652 => x"000044dc", -4653 => x"00000000", -4654 => x"00000000", -4655 => x"00000000", -4656 => x"00000000", -4657 => x"00000000", -4658 => x"00000000", -4659 => x"00000000", -4660 => x"00000000", -4661 => x"00000000", -4662 => x"00000000", -4663 => x"00000000", -4664 => x"00000000", -4665 => x"ffffffff", -4666 => x"00000000", -4667 => x"00020000", -4668 => x"00000000", -4669 => x"00000000", -4670 => x"000048f0", -4671 => x"000048f0", -4672 => x"000048f8", -4673 => x"000048f8", -4674 => x"00004900", -4675 => x"00004900", -4676 => x"00004908", -4677 => x"00004908", -4678 => x"00004910", -4679 => x"00004910", -4680 => x"00004918", -4681 => x"00004918", -4682 => x"00004920", -4683 => x"00004920", -4684 => x"00004928", -4685 => x"00004928", -4686 => x"00004930", -4687 => x"00004930", -4688 => x"00004938", -4689 => x"00004938", -4690 => x"00004940", -4691 => x"00004940", -4692 => x"00004948", -4693 => x"00004948", -4694 => x"00004950", -4695 => x"00004950", -4696 => x"00004958", -4697 => x"00004958", -4698 => x"00004960", -4699 => x"00004960", -4700 => x"00004968", -4701 => x"00004968", -4702 => x"00004970", -4703 => x"00004970", -4704 => x"00004978", -4705 => x"00004978", -4706 => x"00004980", -4707 => x"00004980", -4708 => x"00004988", -4709 => x"00004988", -4710 => x"00004990", -4711 => x"00004990", -4712 => x"00004998", -4713 => x"00004998", -4714 => x"000049a0", -4715 => x"000049a0", -4716 => x"000049a8", -4717 => x"000049a8", -4718 => x"000049b0", -4719 => x"000049b0", -4720 => x"000049b8", -4721 => x"000049b8", -4722 => x"000049c0", -4723 => x"000049c0", -4724 => x"000049c8", -4725 => x"000049c8", -4726 => x"000049d0", -4727 => x"000049d0", -4728 => x"000049d8", -4729 => x"000049d8", -4730 => x"000049e0", -4731 => x"000049e0", -4732 => x"000049e8", -4733 => x"000049e8", -4734 => x"000049f0", -4735 => x"000049f0", -4736 => x"000049f8", -4737 => x"000049f8", -4738 => x"00004a00", -4739 => x"00004a00", -4740 => x"00004a08", -4741 => x"00004a08", -4742 => x"00004a10", -4743 => x"00004a10", -4744 => x"00004a18", -4745 => x"00004a18", -4746 => x"00004a20", -4747 => x"00004a20", -4748 => x"00004a28", -4749 => x"00004a28", -4750 => x"00004a30", -4751 => x"00004a30", -4752 => x"00004a38", -4753 => x"00004a38", -4754 => x"00004a40", -4755 => x"00004a40", -4756 => x"00004a48", -4757 => x"00004a48", -4758 => x"00004a50", -4759 => x"00004a50", -4760 => x"00004a58", -4761 => x"00004a58", -4762 => x"00004a60", -4763 => x"00004a60", -4764 => x"00004a68", -4765 => x"00004a68", -4766 => x"00004a70", -4767 => x"00004a70", -4768 => x"00004a78", -4769 => x"00004a78", -4770 => x"00004a80", -4771 => x"00004a80", -4772 => x"00004a88", -4773 => x"00004a88", -4774 => x"00004a90", -4775 => x"00004a90", -4776 => x"00004a98", -4777 => x"00004a98", -4778 => x"00004aa0", -4779 => x"00004aa0", -4780 => x"00004aa8", -4781 => x"00004aa8", -4782 => x"00004ab0", -4783 => x"00004ab0", -4784 => x"00004ab8", -4785 => x"00004ab8", -4786 => x"00004ac0", -4787 => x"00004ac0", -4788 => x"00004ac8", -4789 => x"00004ac8", -4790 => x"00004ad0", -4791 => x"00004ad0", -4792 => x"00004ad8", -4793 => x"00004ad8", -4794 => x"00004ae0", -4795 => x"00004ae0", -4796 => x"00004ae8", -4797 => x"00004ae8", -4798 => x"00004af0", -4799 => x"00004af0", -4800 => x"00004af8", -4801 => x"00004af8", -4802 => x"00004b00", -4803 => x"00004b00", -4804 => x"00004b08", -4805 => x"00004b08", -4806 => x"00004b10", -4807 => x"00004b10", -4808 => x"00004b18", -4809 => x"00004b18", -4810 => x"00004b20", -4811 => x"00004b20", -4812 => x"00004b28", -4813 => x"00004b28", -4814 => x"00004b30", -4815 => x"00004b30", -4816 => x"00004b38", -4817 => x"00004b38", -4818 => x"00004b40", -4819 => x"00004b40", -4820 => x"00004b48", -4821 => x"00004b48", -4822 => x"00004b50", -4823 => x"00004b50", -4824 => x"00004b58", -4825 => x"00004b58", -4826 => x"00004b60", -4827 => x"00004b60", -4828 => x"00004b68", -4829 => x"00004b68", -4830 => x"00004b70", -4831 => x"00004b70", -4832 => x"00004b78", -4833 => x"00004b78", -4834 => x"00004b80", -4835 => x"00004b80", -4836 => x"00004b88", -4837 => x"00004b88", -4838 => x"00004b90", -4839 => x"00004b90", -4840 => x"00004b98", -4841 => x"00004b98", -4842 => x"00004ba0", -4843 => x"00004ba0", -4844 => x"00004ba8", -4845 => x"00004ba8", -4846 => x"00004bb0", -4847 => x"00004bb0", -4848 => x"00004bb8", -4849 => x"00004bb8", -4850 => x"00004bc0", -4851 => x"00004bc0", -4852 => x"00004bc8", -4853 => x"00004bc8", -4854 => x"00004bd0", -4855 => x"00004bd0", -4856 => x"00004bd8", -4857 => x"00004bd8", -4858 => x"00004be0", -4859 => x"00004be0", -4860 => x"00004be8", -4861 => x"00004be8", -4862 => x"00004bf0", -4863 => x"00004bf0", -4864 => x"00004bf8", -4865 => x"00004bf8", -4866 => x"00004c00", -4867 => x"00004c00", -4868 => x"00004c08", -4869 => x"00004c08", -4870 => x"00004c10", -4871 => x"00004c10", -4872 => x"00004c18", -4873 => x"00004c18", -4874 => x"00004c20", -4875 => x"00004c20", -4876 => x"00004c28", -4877 => x"00004c28", -4878 => x"00004c30", -4879 => x"00004c30", -4880 => x"00004c38", -4881 => x"00004c38", -4882 => x"00004c40", -4883 => x"00004c40", -4884 => x"00004c48", -4885 => x"00004c48", -4886 => x"00004c50", -4887 => x"00004c50", -4888 => x"00004c58", -4889 => x"00004c58", -4890 => x"00004c60", -4891 => x"00004c60", -4892 => x"00004c68", -4893 => x"00004c68", -4894 => x"00004c70", -4895 => x"00004c70", -4896 => x"00004c78", -4897 => x"00004c78", -4898 => x"00004c80", -4899 => x"00004c80", -4900 => x"00004c88", -4901 => x"00004c88", -4902 => x"00004c90", -4903 => x"00004c90", -4904 => x"00004c98", -4905 => x"00004c98", -4906 => x"00004ca0", -4907 => x"00004ca0", -4908 => x"00004ca8", -4909 => x"00004ca8", -4910 => x"00004cb0", -4911 => x"00004cb0", -4912 => x"00004cb8", -4913 => x"00004cb8", -4914 => x"00004cc0", -4915 => x"00004cc0", -4916 => x"00004cc8", -4917 => x"00004cc8", -4918 => x"00004cd0", -4919 => x"00004cd0", -4920 => x"00004cd8", -4921 => x"00004cd8", -4922 => x"00004ce0", -4923 => x"00004ce0", -4924 => x"00004ce8", -4925 => x"00004ce8", -4926 => x"000044e8", -4927 => x"ffffffff", -4928 => x"00000000", -4929 => x"ffffffff", -4930 => x"00000000", - others => x"00000000" -); - -begin - -process (clk) -begin - if (clk'event and clk = '1') then - if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then - report "write collision" severity failure; - end if; - - if (memAWriteEnable = '1') then - ram(conv_integer(memAAddr)) := memAWrite; - memARead <= memAWrite; - else - memARead <= ram(conv_integer(memAAddr)); - end if; - end if; -end process; - -process (clk) -begin - if (clk'event and clk = '1') then - if (memBWriteEnable = '1') then - ram(conv_integer(memBAddr)) := memBWrite; - memBRead <= memBWrite; - else - memBRead <= ram(conv_integer(memBAddr)); - end if; - end if; -end process; - - - - -end dualport_ram_arch; diff --git a/zpu/hdl/zpu3/src/dualport_ram_synplicity.vhd b/zpu/hdl/zpu3/src/dualport_ram_synplicity.vhd deleted file mode 100644 index 83a7de2..0000000 --- a/zpu/hdl/zpu3/src/dualport_ram_synplicity.vhd +++ /dev/null @@ -1,5012 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - - -library zylin; -use zylin.zpu_config.all; -use zylin.zpupkg.all; - -entity dualport_ram is -port (clk : in std_logic; - memAWriteEnable : in std_logic; - memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit); - memAWrite : in std_logic_vector(wordSize-1 downto 0); - memARead : out std_logic_vector(wordSize-1 downto 0); - memBWriteEnable : in std_logic; - memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit); - memBWrite : in std_logic_vector(wordSize-1 downto 0); - memBRead : out std_logic_vector(wordSize-1 downto 0)); -end dualport_ram; - -architecture dualport_ram_arch of dualport_ram is - - -type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); - - ---shared variable ram : ram_type := -signal ram : ram_type := -( -0 => x"800b0b0b", -1 => x"0b0b8070", -2 => x"0b0b818a", -3 => x"dc0c3a0b", -4 => x"0b80dab4", -5 => x"04000000", -6 => x"00000000", -7 => x"00000000", -8 => x"80088408", -9 => x"88080b0b", -10 => x"80db972d", -11 => x"880c840c", -12 => x"800c0400", -13 => x"00000000", -14 => x"00000000", -15 => x"00000000", -16 => x"71fd0608", -17 => x"72830609", -18 => x"81058205", -19 => x"832b0b2a", -20 => x"83ffff06", -21 => x"52810504", -22 => x"00000000", -23 => x"00000000", -24 => x"71fd0608", -25 => x"83ffff73", -26 => x"83060981", -27 => x"05820583", -28 => x"2b0b2b09", -29 => x"067383ff", -30 => x"ff0b0b0b", -31 => x"0b83a704", -32 => x"72098105", -33 => x"72057373", -34 => x"09060906", -35 => x"73097306", -36 => x"070a8106", -37 => x"53518105", -38 => x"04000000", -39 => x"00000000", -40 => x"72722473", -41 => x"732e0753", -42 => x"51810504", -43 => x"00000000", -44 => x"00000000", -45 => x"00000000", -46 => x"00000000", -47 => x"00000000", -48 => x"71737109", -49 => x"71068106", -50 => x"30720a10", -51 => x"0a720a10", -52 => x"0a31050a", -53 => x"81065151", -54 => x"53518105", -55 => x"04000000", -56 => x"72722673", -57 => x"732e0753", -58 => x"51810504", -59 => x"00000000", -60 => x"00000000", -61 => x"00000000", -62 => x"00000000", -63 => x"00000000", -64 => x"72ff0571", -65 => x"81050673", -66 => x"ff050972", -67 => x"74058005", -68 => x"06075350", -69 => x"50040000", -70 => x"00000000", -71 => x"00000000", -72 => x"0b0b0b8c", -73 => x"f8040000", -74 => x"00000000", -75 => x"00000000", -76 => x"00000000", -77 => x"00000000", -78 => x"00000000", -79 => x"00000000", -80 => x"720a722b", -81 => x"0a535181", -82 => x"05040000", -83 => x"00000000", -84 => x"00000000", -85 => x"00000000", -86 => x"00000000", -87 => x"00000000", -88 => x"72729f06", -89 => x"0981050b", -90 => x"0b0b88a7", -91 => x"05040000", -92 => x"00000000", -93 => x"00000000", -94 => x"00000000", -95 => x"00000000", -96 => x"72722aff", -97 => x"739f062a", -98 => x"0974090a", -99 => x"8106ff05", -100 => x"06075351", -101 => x"81050400", -102 => x"00000000", -103 => x"00000000", -104 => x"71718105", -105 => x"53510406", -106 => x"73830609", -107 => x"81058205", -108 => x"832b0b2b", -109 => x"0772fc06", -110 => x"0c515181", -111 => x"05040000", -112 => x"72098105", -113 => x"72050970", -114 => x"81050906", -115 => x"0a810653", -116 => x"51810504", -117 => x"00000000", -118 => x"00000000", -119 => x"00000000", -120 => x"72098105", -121 => x"72050970", -122 => x"81050906", -123 => x"0a098106", -124 => x"53518105", -125 => x"04000000", -126 => x"00000000", -127 => x"00000000", -128 => x"71098105", -129 => x"52810504", -130 => x"00000000", -131 => x"00000000", -132 => x"00000000", -133 => x"00000000", -134 => x"00000000", -135 => x"00000000", -136 => x"72720981", -137 => x"05055351", -138 => x"81050409", -139 => x"81058305", -140 => x"1010102b", -141 => x"0772fc06", -142 => x"0c515181", -143 => x"05040000", -144 => x"72097206", -145 => x"73730906", -146 => x"07535181", -147 => x"05040000", -148 => x"00000000", -149 => x"00000000", -150 => x"00000000", -151 => x"00000000", -152 => x"71fc0608", -153 => x"72830609", -154 => x"81058305", -155 => x"1010102a", -156 => x"81ff0652", -157 => x"81050400", -158 => x"00000000", -159 => x"00000000", -160 => x"71fc0608", -161 => x"0b0b818a", -162 => x"88738306", -163 => x"10100508", -164 => x"067381ff", -165 => x"06738306", -166 => x"0b0b0b84", -167 => x"ab040000", -168 => x"80088408", -169 => x"88087575", -170 => x"0b0b0bb3", -171 => x"912d5050", -172 => x"80085688", -173 => x"0c840c80", -174 => x"0c810551", -175 => x"04000000", -176 => x"80088408", -177 => x"88087575", -178 => x"0b0b0bb4", -179 => x"8a2d5050", -180 => x"80085688", -181 => x"0c840c80", -182 => x"0c810551", -183 => x"04000000", -184 => x"72097081", -185 => x"0509060a", -186 => x"8106ff05", -187 => x"70547181", -188 => x"05067309", -189 => x"72740580", -190 => x"05060753", -191 => x"50500400", -192 => x"72097081", -193 => x"0509060a", -194 => x"098106ff", -195 => x"05705471", -196 => x"81050673", -197 => x"09727405", -198 => x"80050607", -199 => x"53505004", -200 => x"05800504", -201 => x"00000000", -202 => x"00000000", -203 => x"00000000", -204 => x"00000000", -205 => x"00000000", -206 => x"00000000", -207 => x"00000000", -208 => x"810b0b0b", -209 => x"818ad80c", -210 => x"51810504", -211 => x"00000000", -212 => x"00000000", -213 => x"00000000", -214 => x"00000000", -215 => x"00000000", -216 => x"72830610", -217 => x"10728306", -218 => x"0710100b", -219 => x"0b818a98", -220 => x"05080400", -221 => x"00000000", -222 => x"00000000", -223 => x"00000000", -224 => x"00000000", -225 => x"00000000", -226 => x"00000000", -227 => x"00000000", -228 => x"00000000", -229 => x"00000000", -230 => x"00000000", -231 => x"00000000", -232 => x"02840572", -233 => x"10100552", -234 => x"81050400", -235 => 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x"00000000", -4867 => x"00000000", -4868 => x"00000000", -4869 => x"00000000", -4870 => x"00000000", -4871 => x"00000000", -4872 => x"00000000", -4873 => x"00000000", -4874 => x"00000000", -4875 => x"00000000", -4876 => x"00000000", -4877 => x"00000000", -4878 => x"00000000", -4879 => x"00000000", -4880 => x"00000000", -4881 => x"00000000", -4882 => x"00000000", -4883 => x"00000000", -4884 => x"00000000", -4885 => x"00000000", -4886 => x"00000000", -4887 => x"00000000", -4888 => x"00000000", -4889 => x"00000000", -4890 => x"00000000", -4891 => x"00000000", -4892 => x"00000000", -4893 => x"00000000", -4894 => x"00000000", -4895 => x"00000000", -4896 => x"00000000", -4897 => x"00000000", -4898 => x"00000000", -4899 => x"00000000", -4900 => x"00000000", -4901 => x"00000000", -4902 => x"00000000", -4903 => x"00000000", -4904 => x"00000000", -4905 => x"00000000", -4906 => x"00000000", -4907 => x"00000000", -4908 => x"00000000", -4909 => x"00000000", -4910 => x"00000000", -4911 => x"00000000", -4912 => x"00000000", -4913 => x"00000000", -4914 => x"00000000", -4915 => x"00000000", -4916 => x"00000000", -4917 => x"00000000", -4918 => x"00000000", -4919 => x"00000000", -4920 => x"00000000", -4921 => x"00000000", -4922 => x"00000000", -4923 => x"00000000", -4924 => x"00000000", -4925 => x"00000000", -4926 => x"00000000", -4927 => x"00000000", -4928 => x"00000000", -4929 => x"00000000", -4930 => x"00000000", -4931 => x"00000000", -4932 => x"00000000", -4933 => x"00000000", -4934 => x"00000000", -4935 => x"00000000", -4936 => x"00000000", -4937 => x"00000000", -4938 => x"00000000", -4939 => x"00000000", -4940 => x"00000000", -4941 => x"000043fc", -4942 => x"ffffffff", -4943 => x"00000000", -4944 => x"ffffffff", -4945 => x"00000000", - others => x"00000000" -); - -attribute syn_ramstyle : string; -attribute syn_ramstyle of ram : signal is "no_rw_check" ; - -begin - -process (clk) -begin - if (clk'event and clk = '1') then - if (memAWriteEnable = '1') then - ram(conv_integer(memAAddr)) <= memAWrite; - memARead <= memAWrite; - else - memARead <= ram(conv_integer(memAAddr)); - end if; - end if; -end process; - -process (clk) -begin - if (clk'event and clk = '1') then - if (memBWriteEnable = '1') then - ram(conv_integer(memBAddr)) <= memBWrite; - memBRead <= memBWrite; - else - memBRead <= ram(conv_integer(memBAddr)); - end if; - end if; -end process; - - - - -end dualport_ram_arch; diff --git a/zpu/hdl/zpu3/src/helloworld_ram.vhd b/zpu/hdl/zpu3/src/helloworld_ram.vhd deleted file mode 100644 index 2e1d35d..0000000 --- a/zpu/hdl/zpu3/src/helloworld_ram.vhd +++ /dev/null @@ -1,3345 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -library zylin; -use zylin.zpu_config.all; -use zylin.zpupkg.all; - -entity dualport_ram is -port (clk : in std_logic; - memAWriteEnable : in std_logic; - memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit); - memAWrite : in std_logic_vector(wordSize-1 downto 0); - memARead : out std_logic_vector(wordSize-1 downto 0); - memBWriteEnable : in std_logic; - memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit); - memBWrite : in std_logic_vector(wordSize-1 downto 0); - memBRead : out std_logic_vector(wordSize-1 downto 0)); -end dualport_ram; - -architecture dualport_ram_arch of dualport_ram is - - -type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); - -shared variable ram : ram_type := -( -0 => x"800b0b0b", -1 => x"0b0b8070", -2 => x"0b0b80d6", -3 => x"f00c3a0b", -4 => x"0b80cd92", -5 => x"04000000", -6 => x"00000000", -7 => x"00000000", -8 => x"80088408", -9 => x"88080b0b", -10 => x"80cde02d", -11 => x"880c840c", -12 => x"800c0400", -13 => x"00000000", -14 => x"00000000", -15 => x"00000000", -16 => x"71fd0608", -17 => x"72830609", -18 => x"81058205", -19 => x"832b0b2a", -20 => x"83ffff06", -21 => x"52040000", -22 => x"00000000", -23 => x"00000000", -24 => x"71fd0608", -25 => x"83ffff73", -26 => x"83060981", -27 => x"05820583", -28 => x"2b0b2b09", -29 => x"067383ff", -30 => x"ff0b0b0b", -31 => x"0b83a504", -32 => x"72098105", -33 => x"72057373", -34 => x"09060906", -35 => x"73097306", -36 => x"070a8106", -37 => x"53510400", -38 => x"00000000", -39 => x"00000000", -40 => x"72722473", -41 => x"732e0753", -42 => x"51040000", -43 => x"00000000", -44 => x"00000000", -45 => x"00000000", -46 => x"00000000", -47 => x"00000000", -48 => x"71737109", -49 => x"71068106", -50 => x"30720a10", -51 => x"0a720a10", -52 => x"0a31050a", -53 => x"81065151", -54 => x"53510400", -55 => x"00000000", -56 => x"72722673", -57 => x"732e0753", -58 => x"51040000", -59 => x"00000000", -60 => x"00000000", -61 => x"00000000", -62 => x"00000000", -63 => x"00000000", -64 => x"00000000", -65 => x"00000000", -66 => x"00000000", -67 => x"00000000", -68 => x"00000000", -69 => x"00000000", -70 => x"00000000", -71 => x"00000000", -72 => x"72728072", -73 => x"8106ff05", -74 => x"09720605", -75 => x"71105272", -76 => x"0a100a53", -77 => x"72ed3851", -78 => x"51535104", -79 => x"00000000", -80 => x"720a722b", -81 => x"0a535104", -82 => x"00000000", -83 => x"00000000", -84 => x"00000000", -85 => x"00000000", -86 => x"00000000", -87 => x"00000000", -88 => x"72729f06", -89 => x"0981050b", -90 => x"0b0b88a7", -91 => x"05040000", -92 => x"00000000", -93 => x"00000000", -94 => x"00000000", -95 => x"00000000", -96 => x"72722aff", -97 => x"739f062a", -98 => x"0974090a", -99 => x"8106ff05", -100 => x"06075351", -101 => x"04000000", -102 => x"00000000", -103 => x"00000000", -104 => x"71715351", -105 => x"04067383", -106 => x"06098105", -107 => x"8205832b", -108 => x"0b2b0772", -109 => x"fc060c51", -110 => x"51040000", -111 => x"00000000", -112 => x"72098105", -113 => x"72050970", -114 => x"81050906", -115 => x"0a810653", -116 => x"51040000", -117 => x"00000000", -118 => x"00000000", -119 => x"00000000", -120 => x"72098105", -121 => x"72050970", -122 => x"81050906", -123 => x"0a098106", -124 => x"53510400", -125 => x"00000000", -126 => x"00000000", -127 => x"00000000", -128 => x"71098105", -129 => x"52040000", -130 => x"00000000", -131 => x"00000000", -132 => x"00000000", -133 => x"00000000", -134 => x"00000000", -135 => x"00000000", -136 => x"72720981", -137 => x"05055351", -138 => x"04098105", -139 => x"83051010", -140 => x"102b0772", -141 => x"fc060c51", -142 => x"51040000", -143 => x"00000000", -144 => x"72097206", -145 => x"73730906", -146 => x"07535104", -147 => x"00000000", -148 => x"00000000", -149 => x"00000000", -150 => x"00000000", -151 => x"00000000", -152 => x"71fc0608", -153 => x"72830609", -154 => x"81058305", -155 => x"1010102a", -156 => x"81ff0652", -157 => x"04000000", -158 => x"00000000", -159 => x"00000000", -160 => x"71fc0608", -161 => x"0b0b80d6", -162 => x"dc738306", -163 => x"10100508", -164 => x"067381ff", -165 => x"06738306", -166 => x"0b0b0b84", -167 => x"a9040000", -168 => x"80088408", -169 => x"88087575", -170 => x"0b0b0b8e", -171 => x"fd2d5050", -172 => x"80085688", -173 => x"0c840c80", -174 => x"0c510400", -175 => x"00000000", -176 => x"80088408", -177 => x"88087575", -178 => x"0b0b0b90", -179 => x"af2d5050", -180 => x"80085688", -181 => x"0c840c80", -182 => x"0c510400", -183 => x"00000000", -184 => x"72097081", -185 => x"0509060a", -186 => x"8106ff05", -187 => x"70547106", -188 => x"73097274", -189 => x"05ff0506", -190 => x"07535050", -191 => x"04000000", -192 => x"72097081", -193 => x"0509060a", -194 => x"098106ff", -195 => x"05705471", -196 => x"06730972", -197 => x"7405ff05", -198 => x"06075350", -199 => x"50040000", -200 => x"05ff0504", -201 => x"00000000", -202 => x"00000000", -203 => x"00000000", -204 => x"00000000", -205 => x"00000000", -206 => x"00000000", -207 => x"00000000", -208 => x"810b0b0b", -209 => x"80d6ec0c", -210 => x"51040000", -211 => x"00000000", -212 => x"00000000", -213 => x"00000000", -214 => x"00000000", -215 => x"00000000", -216 => x"71810552", -217 => x"04000000", -218 => x"00000000", -219 => x"00000000", -220 => x"00000000", -221 => x"00000000", -222 => x"00000000", -223 => x"00000000", -224 => x"00000000", -225 => x"00000000", -226 => x"00000000", -227 => x"00000000", -228 => x"00000000", -229 => x"00000000", -230 => x"00000000", -231 => x"00000000", -232 => x"02840572", -233 => x"10100552", -234 => x"04000000", -235 => x"00000000", -236 => x"00000000", -237 => x"00000000", -238 => x"00000000", -239 => x"00000000", -240 => x"00000000", -241 => x"00000000", -242 => x"00000000", -243 => x"00000000", -244 => x"00000000", -245 => x"00000000", -246 => x"00000000", -247 => x"00000000", -248 => x"717105ff", -249 => x"05715351", -250 => x"04000000", -251 => x"00000000", -252 => x"00000000", -253 => x"00000000", -254 => x"00000000", -255 => x"00000000", -256 => x"839f3f80", -257 => x"cdf83f04", -258 => x"10101010", -259 => x"10101010", -260 => x"10101010", -261 => x"10101010", -262 => x"10101010", -263 => x"10101010", -264 => x"10101010", -265 => x"10101053", -266 => x"51043c04", -267 => x"70700b0b", -268 => x"80e6d808", -269 => x"52841208", -270 => x"70810651", -271 => x"5170f638", -272 => x"710881ff", -273 => x"06800c50", -274 => x"50047070", -275 => x"0b0b80e6", -276 => x"d8085284", -277 => x"1208700a", -278 => x"100a7081", -279 => x"06515151", -280 => x"70f13873", -281 => x"720c5050", -282 => x"0480d6ec", -283 => x"08802ea8", -284 => x"38838080", -285 => x"0b0b0b80", -286 => x"e6d80c82", -287 => x"a0800b0b", -288 => x"0b80e6dc", -289 => x"0c829080", -290 => x"0b80e6ec", -291 => x"0c0b0b80", -292 => x"e6e00b80", -293 => x"e6f00c04", -294 => x"f8808080", -295 => x"a40b0b0b", -296 => x"80e6d80c", -297 => x"f8808082", -298 => x"800b0b0b", -299 => x"80e6dc0c", -300 => x"f8808084", -301 => x"800b80e6", -302 => x"ec0cf880", -303 => x"8080940b", -304 => x"80e6f00c", -305 => x"f8808080", -306 => x"9c0b80e6", -307 => x"e80cf880", -308 => x"8080a00b", -309 => x"80e6f40c", -310 => x"04f23d0d", -311 => x"600b0b80", -312 => x"e6dc0856", -313 => x"5d82750c", -314 => x"8059805a", -315 => x"800b8f3d", -316 => x"71101017", -317 => x"70085a57", -318 => x"5d5b8077", -319 => x"81ff067c", -320 => x"832b5658", -321 => x"5276537b", -322 => x"5182fc3f", -323 => x"7d7f7a72", -324 => x"077c7207", -325 => x"71716081", -326 => x"05415f5d", -327 => x"5b595755", -328 => x"7a8724bb", -329 => x"380b0b80", -330 => x"e6dc087b", -331 => x"10101170", -332 => x"08595155", -333 => x"807781ff", -334 => x"067c832b", -335 => x"56585276", -336 => x"537b5182", -337 => x"c23f7d7f", -338 => x"7a72077c", -339 => x"72077171", -340 => x"60810541", -341 => x"5f5d5b59", -342 => x"5755877b", -343 => x"25c73876", -344 => x"7d0c7784", -345 => x"1e0c7c80", -346 => x"0c903d0d", -347 => x"04707080", -348 => x"e6e43351", -349 => x"70a73880", -350 => x"d6f80870", -351 => x"08525270", -352 => x"802e9438", -353 => x"841280d6", -354 => x"f80c702d", -355 => x"80d6f808", -356 => x"70085252", -357 => x"70ee3881", -358 => x"0b80e6e4", -359 => x"34505004", -360 => x"04700b0b", -361 => x"80e6d408", -362 => x"802e8e38", -363 => x"0b0b0b0b", -364 => x"800b802e", -365 => x"09810683", -366 => x"3850040b", -367 => x"0b80e6d4", -368 => x"510b0b0b", -369 => x"f4ba3f50", -370 => x"04048c08", -371 => x"028c0c70", -372 => x"70707080", -373 => x"0b8c08fc", -374 => x"050c8c08", -375 => x"fc050889", -376 => x"24818e38", -377 => x"0b0b80d6", -378 => x"a85188f3", -379 => x"3f0b0b80", -380 => x"d6b85188", -381 => x"ea3ffc0b", -382 => x"80e6f80c", -383 => x"80e6f808", -384 => x"812c5372", -385 => x"fe2e8438", -386 => x"86f13f8a", -387 => x"0b80e6fc", -388 => x"0c80e6fc", -389 => x"0880e6f8", -390 => x"08295372", -391 => x"d82e8438", -392 => x"86d93f8a", -393 => x"0b80e6f8", -394 => x"0c84e2ad", -395 => x"800b80e6", -396 => x"fc0c80e6", -397 => x"fc0880e6", -398 => x"f8082953", -399 => x"72afd7c2", -400 => x"802e8438", -401 => x"86b53f81", -402 => x"0a0b80e6", -403 => x"f80cff0b", -404 => x"80e6fc0c", -405 => x"80e6fc08", -406 => x"80e6f808", -407 => x"25843886", -408 => x"9a3f8c08", -409 => x"fc050881", -410 => x"058c08fc", -411 => x"050cfeea", -412 => x"398c08fc", -413 => x"05088a2e", -414 => x"843885ff", -415 => x"3f72800c", -416 => x"50505050", -417 => x"8c0c048c", -418 => x"08028c0c", -419 => x"f53d0d8c", -420 => x"08940508", -421 => x"9d388c08", -422 => x"8c05088c", -423 => x"08900508", -424 => x"8c088805", -425 => x"08585654", -426 => x"73760c74", -427 => x"84170c81", -428 => x"bf39800b", -429 => x"8c08f005", -430 => x"0c800b8c", -431 => x"08f4050c", -432 => x"8c088c05", -433 => x"088c0890", -434 => x"05085654", -435 => x"738c08f0", -436 => x"050c748c", -437 => x"08f4050c", -438 => x"8c08f805", -439 => x"8c08f005", -440 => x"56568870", -441 => x"54755376", -442 => x"5254859a", -443 => x"3fa00b8c", -444 => x"08940508", -445 => x"318c08ec", -446 => x"050c8c08", -447 => x"ec050880", -448 => x"249d3880", -449 => x"0b8c08f4", -450 => x"050c8c08", -451 => x"ec050830", -452 => x"8c08fc05", -453 => x"08712b8c", -454 => x"08f0050c", -455 => x"54b9398c", -456 => x"08fc0508", -457 => x"8c08ec05", -458 => x"082a8c08", -459 => x"e8050c8c", -460 => x"08fc0508", -461 => x"8c089405", -462 => x"082b8c08", -463 => x"f4050c8c", -464 => x"08f80508", -465 => x"8c089405", -466 => x"082b708c", -467 => x"08e80508", -468 => x"078c08f0", -469 => x"050c548c", -470 => x"08f00508", -471 => x"8c08f405", -472 => x"088c0888", -473 => x"05085856", -474 => x"5473760c", -475 => x"7484170c", -476 => x"8c088805", -477 => x"08800c8d", -478 => x"3d0d8c0c", -479 => x"048c0802", -480 => x"8c0cf93d", -481 => x"0d800b8c", -482 => x"08fc050c", -483 => x"8c088805", -484 => x"088025ab", -485 => x"388c0888", -486 => x"0508308c", -487 => x"0888050c", -488 => x"800b8c08", -489 => x"f4050c8c", -490 => x"08fc0508", -491 => x"8838810b", -492 => x"8c08f405", -493 => x"0c8c08f4", -494 => x"05088c08", -495 => x"fc050c8c", -496 => x"088c0508", -497 => x"8025ab38", -498 => x"8c088c05", -499 => x"08308c08", -500 => x"8c050c80", -501 => x"0b8c08f0", -502 => x"050c8c08", -503 => x"fc050888", -504 => x"38810b8c", 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x"00003058", -3097 => x"00003058", -3098 => x"00003060", -3099 => x"00003060", -3100 => x"00003068", -3101 => x"00003068", -3102 => x"00003070", -3103 => x"00003070", -3104 => x"00003078", -3105 => x"00003078", -3106 => x"00003080", -3107 => x"00003080", -3108 => x"00003088", -3109 => x"00003088", -3110 => x"00003090", -3111 => x"00003090", -3112 => x"00003098", -3113 => x"00003098", -3114 => x"000030a0", -3115 => x"000030a0", -3116 => x"000030a8", -3117 => x"000030a8", -3118 => x"000030b0", -3119 => x"000030b0", -3120 => x"000030b8", -3121 => x"000030b8", -3122 => x"000030c0", -3123 => x"000030c0", -3124 => x"000030c8", -3125 => x"000030c8", -3126 => x"000030d0", -3127 => x"000030d0", -3128 => x"000030d8", -3129 => x"000030d8", -3130 => x"000030e0", -3131 => x"000030e0", -3132 => x"000030e8", -3133 => x"000030e8", -3134 => x"000030f0", -3135 => x"000030f0", -3136 => x"000030f8", -3137 => x"000030f8", -3138 => x"00003100", -3139 => x"00003100", -3140 => x"00003108", -3141 => x"00003108", -3142 => x"00003110", -3143 => x"00003110", -3144 => x"00003118", -3145 => x"00003118", -3146 => x"00003120", -3147 => x"00003120", -3148 => x"00003128", -3149 => x"00003128", -3150 => x"00003130", -3151 => x"00003130", -3152 => x"00003138", -3153 => x"00003138", -3154 => x"00003140", -3155 => x"00003140", -3156 => x"00003148", -3157 => x"00003148", -3158 => x"00003150", -3159 => x"00003150", -3160 => x"00003158", -3161 => x"00003158", -3162 => x"00003160", -3163 => x"00003160", -3164 => x"00003168", -3165 => x"00003168", -3166 => x"00003170", -3167 => x"00003170", -3168 => x"00003178", -3169 => x"00003178", -3170 => x"00003180", -3171 => x"00003180", -3172 => x"00003188", -3173 => x"00003188", -3174 => x"00003190", -3175 => x"00003190", -3176 => x"00003198", -3177 => x"00003198", -3178 => x"000031a0", -3179 => x"000031a0", -3180 => x"000031a8", -3181 => x"000031a8", -3182 => x"000031b0", -3183 => x"000031b0", -3184 => x"000031b8", -3185 => x"000031b8", -3186 => x"000031c0", -3187 => x"000031c0", -3188 => x"000031c8", -3189 => x"000031c8", -3190 => x"000031d0", -3191 => x"000031d0", -3192 => x"000031d8", -3193 => x"000031d8", -3194 => x"000031e0", -3195 => x"000031e0", -3196 => x"000031e8", -3197 => x"000031e8", -3198 => x"000031f0", -3199 => x"000031f0", -3200 => x"000031f8", -3201 => x"000031f8", -3202 => x"00003200", -3203 => x"00003200", -3204 => x"00003208", -3205 => x"00003208", -3206 => x"00003210", -3207 => x"00003210", -3208 => x"00003218", -3209 => x"00003218", -3210 => x"00003220", -3211 => x"00003220", -3212 => x"00003228", -3213 => x"00003228", -3214 => x"00003230", -3215 => x"00003230", -3216 => x"00003238", -3217 => x"00003238", -3218 => x"00003240", -3219 => x"00003240", -3220 => x"00003248", -3221 => x"00003248", -3222 => x"00003250", -3223 => x"00003250", -3224 => x"00003258", -3225 => x"00003258", -3226 => x"00003260", -3227 => x"00003260", -3228 => x"00003268", -3229 => x"00003268", -3230 => x"00003270", -3231 => x"00003270", -3232 => x"00003278", -3233 => x"00003278", -3234 => x"00003280", -3235 => x"00003280", -3236 => x"00003288", -3237 => x"00003288", -3238 => x"00003290", -3239 => x"00003290", -3240 => x"00003298", -3241 => x"00003298", -3242 => x"000032a0", -3243 => x"000032a0", -3244 => x"000032a8", -3245 => x"000032a8", -3246 => x"000032b0", -3247 => x"000032b0", -3248 => x"000032b8", -3249 => x"000032b8", -3250 => x"000032c0", -3251 => x"000032c0", -3252 => x"000032c8", -3253 => x"000032c8", -3254 => x"000032d0", -3255 => x"000032d0", -3256 => x"000032d8", -3257 => x"000032d8", -3258 => x"000032e0", -3259 => x"000032e0", -3260 => x"000032e8", -3261 => x"000032e8", -3262 => x"000032f0", -3263 => x"000032f0", -3264 => x"000032f8", -3265 => x"000032f8", -3266 => x"00003300", -3267 => x"00003300", -3268 => x"00003308", -3269 => x"00003308", -3270 => x"00003310", -3271 => x"00003310", -3272 => x"00003318", -3273 => x"00003318", -3274 => x"00003320", -3275 => x"00003320", -3276 => x"00003328", -3277 => x"00003328", -3278 => x"00003330", -3279 => x"00003330", -3280 => x"00002b50", -3281 => x"ffffffff", -3282 => x"00000000", -3283 => x"ffffffff", -3284 => x"00000000", - others => x"00000000" -); - -begin - -process (clk) -begin - if (clk'event and clk = '1') then - if (memAWriteEnable = '1') then - ram(conv_integer(memAAddr)) := memAWrite; - memARead <= memAWrite; - else - memARead <= ram(conv_integer(memAAddr)); - end if; - end if; -end process; - -process (clk) -begin - if (clk'event and clk = '1') then - if (memBWriteEnable = '1') then - ram(conv_integer(memBAddr)) := memBWrite; - memBRead <= memBWrite; - else - memBRead <= ram(conv_integer(memBAddr)); - end if; - end if; -end process; - - - - -end dualport_ram_arch; diff --git a/zpu/hdl/zpu3/src/ic300.bitgen b/zpu/hdl/zpu3/src/ic300.bitgen deleted file mode 100644 index 1095099..0000000 --- a/zpu/hdl/zpu3/src/ic300.bitgen +++ /dev/null @@ -1,27 +0,0 @@ --g DebugBitstream:No --g Binary:yes --g CRC:Enable --g ConfigRate:50 --g CclkPin:Pullnone --g M0Pin:Pullnone --g M1Pin:Pullnone --g M2Pin:Pullnone --g ProgPin:PullUp --g DonePin:Pullnone --g TckPin:Pullnone --g TdiPin:Pullnone --g TdoPin:Pullnone --g TmsPin:Pullnone --g UnusedPin:Pullnone --g UserID:0xFFFFFFFF --g DCMShutDown:Disable --g DCIUpdateMode:AsRequired --g StartUpClk:CClk --g DONE_cycle:4 --g GTS_cycle:5 --g GWE_cycle:6 --g LCK_cycle:NoWait --g Security:Level1 --g DonePipe:No --g DriveDone:Yes - diff --git a/zpu/hdl/zpu3/src/ic300.lso b/zpu/hdl/zpu3/src/ic300.lso deleted file mode 100644 index 22de730..0000000 --- a/zpu/hdl/zpu3/src/ic300.lso +++ /dev/null @@ -1 +0,0 @@ -work diff --git a/zpu/hdl/zpu3/src/ic300.ucf b/zpu/hdl/zpu3/src/ic300.ucf deleted file mode 100644 index e11357f..0000000 --- a/zpu/hdl/zpu3/src/ic300.ucf +++ /dev/null @@ -1,146 +0,0 @@ -# clock inputs -net "cpu_clk_p" loc = "R9" | iostandard=LVTTL; - -# input pins -net "cpu_a_p(0)" loc = "N15" | iostandard=LVTTL; -net "cpu_a_p(1)" loc = "P16" | iostandard=LVTTL; -net "cpu_a_p(2)" loc = "P13" | iostandard=LVTTL; -net "cpu_a_p(3)" loc = "N16" | iostandard=LVTTL; -net "cpu_a_p(4)" loc = "P15" | iostandard=LVTTL; -net "cpu_a_p(5)" loc = "R11" | iostandard=LVTTL; -net "cpu_a_p(6)" loc = "T14" | iostandard=LVTTL; -net "cpu_a_p(7)" loc = "R16" | iostandard=LVTTL; -net "cpu_a_p(8)" loc = "P14" | iostandard=LVTTL; -net "cpu_a_p(9)" loc = "T13" | iostandard=LVTTL; -net "cpu_a_p(10)" loc = "R13" | iostandard=LVTTL; -net "cpu_a_p(11)" loc = "P7" | iostandard=LVTTL; -net "cpu_a_p(12)" loc = "N12" | iostandard=LVTTL; -net "cpu_a_p(13)" loc = "R12" | iostandard=LVTTL; -net "cpu_a_p(14)" loc = "L13" | iostandard=LVTTL; -net "cpu_a_p(15)" loc = "K12" | iostandard=LVTTL; -net "cpu_a_p(16)" loc = "K15" | iostandard=LVTTL; -net "cpu_a_p(17)" loc = "T10" | iostandard=LVTTL; -net "cpu_a_p(18)" loc = "T9" | iostandard=LVTTL; -net "cpu_a_p(19)" loc = "N10" | iostandard=LVTTL; -net "cpu_a_p(20)" loc = "T8" | iostandard=LVTTL; -net "cpu_wr_n_p(0)" loc = "L15" | iostandard=LVTTL; -net "cpu_wr_n_p(1)" loc = "N14" | iostandard=LVTTL; -net "cpu_oe_n_p" loc = "T12" | iostandard=LVTTL; -net "cpu_cs_n_p(1)" loc = "R3" | iostandard=LVTTL; -net "cpu_cs_n_p(2)" loc = "M16" | iostandard=LVTTL; -net "cpu_cs_n_p(3)" loc = "P11" | iostandard=LVTTL; - -#net "sdr_clk_fb_p" loc = "B8" | iostandard=SSTL2_I; - -# output pins -net "cpu_fiq_p" loc = "K16" | iostandard=LVTTL; -net "cpu_irq_p(0)" loc = "M14" | iostandard=LVTTL; -net "cpu_irq_p(1)" loc = "J16" | iostandard=LVTTL; -net "cpu_wait_n_p" loc = "M15" | iostandard=LVTTL; - -#net "sdr_clk_p" loc = "D8" | iostandard=SSTL2_I | FAST; -#net "sdr_clk_n_p" loc = "F5" | iostandard=SSTL2_I | FAST; -#net "cke_q_p" loc = "F4" | iostandard=SSTL2_I | FAST; -#net "cs_qn_p" loc = "M2" | iostandard=SSTL2_I | FAST | PULLUP; -#net "ras_qn_p" loc = "J2" | iostandard=SSTL2_I | FAST | PULLUP | NODELAY; -#net "cas_qn_p" loc = "M3" | iostandard=SSTL2_I | FAST | PULLUP | NODELAY; -#net "we_qn_p" loc = "K4" | iostandard=SSTL2_I | FAST | PULLUP | NODELAY; -#net "dm_q_p(0)" loc = "L4" | iostandard=SSTL2_I | FAST; -#net "dm_q_p(1)" loc = "E4" | iostandard=SSTL2_I | FAST; -#net "dqs_q_p(0)" loc = "L3" | iostandard=SSTL2_I | FAST; -#net "dqs_q_p(1)" loc = "D3" | iostandard=SSTL2_I | FAST; -#net "ba_q_p(0)" loc = "M1" | iostandard=SSTL2_I | FAST; -#net "ba_q_p(1)" loc = "J3" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(0)" loc = "J4" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(1)" loc = "N2" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(2)" loc = "H4" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(3)" loc = "P2" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(4)" loc = "E7" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(5)" loc = "G4" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(6)" loc = "D7" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(7)" loc = "G5" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(8)" loc = "C7" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(9)" loc = "F3" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(10)" loc = "N3" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(11)" loc = "E6" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(12)" loc = "D6" | iostandard=SSTL2_I | FAST; - -# bidirectional pins -net "cpu_d_p(0)" loc = "M11" | iostandard=LVTTL; -net "cpu_d_p(1)" loc = "N11" | iostandard=LVTTL; -net "cpu_d_p(2)" loc = "P10" | iostandard=LVTTL; -net "cpu_d_p(3)" loc = "R10" | iostandard=LVTTL; -net "cpu_d_p(4)" loc = "T7" | iostandard=LVTTL; -net "cpu_d_p(5)" loc = "R7" | iostandard=LVTTL; -net "cpu_d_p(6)" loc = "N6" | iostandard=LVTTL; -net "cpu_d_p(7)" loc = "M6" | iostandard=LVTTL; -net "cpu_d_p(8)" loc = "K13" | iostandard=LVTTL; -net "cpu_d_p(9)" loc = "M10" | iostandard=LVTTL; -net "cpu_d_p(10)" loc = "L12" | iostandard=LVTTL; -net "cpu_d_p(11)" loc = "M13" | iostandard=LVTTL; -net "cpu_d_p(12)" loc = "K14" | iostandard=LVTTL; -net "cpu_d_p(13)" loc = "L14" | iostandard=LVTTL; -net "cpu_d_p(14)" loc = "J13" | iostandard=LVTTL; -net "cpu_d_p(15)" loc = "J14" | iostandard=LVTTL; - -#net "sdr_d_p(0)" loc = "G1" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(1)" loc = "H3" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(2)" loc = "G3" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(3)" loc = "K2" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(4)" loc = "F2" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(5)" loc = "L2" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(6)" loc = "E1" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(7)" loc = "M4" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(8)" loc = "C6" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(9)" loc = "E2" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(10)" loc = "C2" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(11)" loc = "D1" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(12)" loc = "B7" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(13)" loc = "D2" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(14)" loc = "B6" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(15)" loc = "B5" | iostandard=SSTL2_I | NODELAY | FAST; - -# TIMING -# Create timing names -NET "cpu_clk_p" TNM_NET = "cpu_clk_p"; -NET "sdr_clk_fb_p" TNM_NET = "sdr_clk_fb_p"; -#NET "cpu_clk" TNM_NET = "cpu_clk"; -#NET "cpu_clk_2x" TNM_NET = "cpu_clk_2x"; -#NET "cpu_clk_4x" TNM_NET = "cpu_clk_4x"; -#NET "ddr_in_clk" TNM_NET = "ddr_in_clk"; -#NET "ddr_in_clk_2x" TNM_NET = "ddr_in_clk_2x"; - -## Create timing - -# Periode timing -TIMESPEC "TS_cpu_clk" = PERIOD "cpu_clk_p" 15.6 ns HIGH 50 %; -#TIMESPEC "TS_sdr_clk_fb_p" = PERIOD "sdr_clk_fb_p" 7.8 ns HIGH 50 %; - -# Clock domain crossing timing -#TIMESPEC "TS_cpu1_to_cpu2" = FROM "cpu_clk" TO "cpu_clk_2x" 7.8 ns; -#TIMESPEC "TS_cpu1_to_cpu4" = FROM "cpu_clk" TO "cpu_clk_4x" 3.9 ns; -#TIMESPEC "TS_cpu1_to_ddr2" = FROM "cpu_clk" TO "ddr_in_clk" 7.8 ns; -#TIMESPEC "TS_cpu1_to_ddr2_2x" = FROM "cpu_clk" TO "ddr_in_clk_2x" 3.9 ns; - -#TIMESPEC "TS_cpu2_to_cpu1" = FROM "cpu_clk_2x" TO "cpu_clk" 7.8 ns; -#TIMESPEC "TS_cpu2_to_cpu4" = FROM "cpu_clk_2x" TO "cpu_clk_4x" 3.9 ns; -#TIMESPEC "TS_cpu2_to_ddr2" = FROM "cpu_clk_2x" TO "ddr_in_clk" 7.8 ns; -#TIMESPEC "TS_cpu2_to_ddr_2x" = FROM "cpu_clk_2x" TO "ddr_in_clk_2x" 3.9 ns; - -#TIMESPEC "TS_cpu4_to_cpu1" = FROM "cpu_clk_4x" TO "cpu_clk" 3.9 ns; -#TIMESPEC "TS_cpu4_to_cpu2" = FROM "cpu_clk_4x" TO "cpu_clk_2x" 3.9 ns; -#TIMESPEC "TS_cpu4_to_ddr2" = FROM "cpu_clk_4x" TO "ddr_in_clk" 3.9 ns; -#TIMESPEC "TS_cpu4_to_ddr2_2x" = FROM "cpu_clk_4x" TO "ddr_in_clk_2x" 3.9 ns; - -#TIMESPEC "TS_ddr2_to_cpu1" = FROM "ddr_in_clk" TO "cpu_clk" 7.8 ns; -#TIMESPEC "TS_ddr2_to_cpu2" = FROM "ddr_in_clk" TO "cpu_clk_2x" 7.8 ns; -#TIMESPEC "TS_ddr2_to_cpu4" = FROM "ddr_in_clk" TO "cpu_clk_4x" 3.9 ns; -#TIMESPEC "TS_ddr2_to_ddr2_2x" = FROM "ddr_in_clk" TO "ddr_in_clk_2x" 3.9 ns; - -#TIMESPEC "TS_ddr2_2x_to_cpu1" = FROM "ddr_in_clk_2x" TO "cpu_clk" 3.9 ns; -#TIMESPEC "TS_ddr2_2x_to_cpu2" = FROM "ddr_in_clk_2x" TO "cpu_clk_2x" 3.9 ns; -#TIMESPEC "TS_ddr2_2x_to_cpu4" = FROM "ddr_in_clk_2x" TO "cpu_clk_4x" 3.9 ns; -#TIMESPEC "TS_ddr2_2x_to_ddr2" = FROM "ddr_in_clk_2x" TO "ddr_in_clk" 3.9 ns; - - - diff --git a/zpu/hdl/zpu3/src/ic300.vhd b/zpu/hdl/zpu3/src/ic300.vhd deleted file mode 100644 index a1b4f41..0000000 --- a/zpu/hdl/zpu3/src/ic300.vhd +++ /dev/null @@ -1,144 +0,0 @@ --------------------------------------------------------------------------------- --- Company: Zylin AS --- Engineer: Tore Ramsland --- --- Create Date: 21:47:41 07/03/05 --- Design Name: ic300 --- Module Name: ic300 - behave --- Project Name: eCosBoard --- Target Device: XC3S400400-FG256 --- Tool versions: 7.1i --- Description: Top level --- --- Dependencies: --- --- Revision: --- 2005-07-11 Updated to test FPGA --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -library zylin; -use zylin.arm7.all; - -library zylin; -use zylin.zpu_config.all; -use zylin.zpupkg.all; - -library work; -use work.phi_config.all; -use work.ic300pkg.all; - -entity ic300 is - generic( - simulate_io_time : boolean := false); - port ( -- Clock inputs - cpu_clk_p : in std_logic; - - -- CPU interface signals - cpu_a_p : in std_logic_vector(20 downto 0); - cpu_wr_n_p : in std_logic_vector(1 downto 0); - cpu_cs_n_p : in std_logic_vector(3 downto 1); - cpu_oe_n_p : in std_logic; - cpu_d_p : inout std_logic_vector(15 downto 0); - cpu_irq_p : out std_logic_vector(1 downto 0); - cpu_fiq_p : out std_logic; - cpu_wait_n_p : out std_logic; - - -- DDR SDRAM Signals - sdr_clk_p : out std_logic; -- ddr_sdram_clock - sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock - cke_q_p : out std_logic; -- clock enable - cs_qn_p : out std_logic; -- /chip select - ras_qn_p : inout std_logic; -- /ras - cas_qn_p : inout std_logic; -- /cas - we_qn_p : inout std_logic; -- /write enable - dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00" - dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write - ba_q_p : out std_logic_vector(1 downto 0); -- bank select - sdr_a_p : out std_logic_vector(12 downto 0); -- address bus - sdr_d_p : inout std_logic_vector(15 downto 0); -- bidir data bus - sdr_clk_fb_p : in std_logic -- DDR clock feedback - ); -end ic300; - -architecture behave of ic300 is - -signal cpu_we : std_logic_vector(1 downto 0); -- Write signal for lower(0) and upper(1) 8 data bits -signal cpu_re : std_logic; -- Read enable signal for all 16 bits -signal areset : std_logic; -- Asyncronous active high reset (for initialization) -signal areset_dummy : std_logic; - --- Clock module signals -signal clk_status : std_logic_vector(2 downto 0); -- DLL lock status (from 3 DLL's) -signal cpu_clk : std_logic; -- 64 MHz CPU clk -signal cpu_clk_2x : std_logic; -- 128 MHz CPU clk (in phase with 64 MHz) -signal cpu_clk_4x : std_logic; -- 256 MHz CPU clk (in phase with 64 MHz) -signal ddr_in_clk : std_logic; -- 128 MHz clock from DDR SDRAM -signal ddr_in_clk_2x : std_logic; -- 256 MHz clock from DDR SDRAM - -- NOTE! Phase relation to 64 MHz clock unknown - --- Internal CPU interface signals -signal cpu_din : std_logic_vector(15 downto 0); -- 16-bit data from CPU -signal cpu_dout : std_logic_vector(15 downto 0); -- 16-bit data to CPU -signal cpu_a : std_logic_vector(20 downto 0); -- 21-bit address from CPU - -begin - --- areset <= '0'; - areset_dummy <= '0'; - - global_init_reset: - rocbuf port map(I=>areset_dummy,O=>areset); - - allclocks: - clocks port map( - areset => areset, - cpu_clk_p => cpu_clk_p, - cpu_clk => cpu_clk, - cpu_clk_2x => cpu_clk_2x, - cpu_clk_4x => cpu_clk_4x, - sdr_clk_fb_p => sdr_clk_fb_p, - ddr_in_clk => ddr_in_clk, - ddr_in_clk_2x => ddr_in_clk_2x, - locked => clk_status); - - arm7cpu: - arm7wb generic map (simulate_io_time => simulate_io_time) - port map( - areset => areset, - cpu_clk => cpu_clk, - cpu_clk_2x => cpu_clk_2x, - cpu_a_p => cpu_a_p, - cpu_wr_n_p => cpu_wr_n_p, - cpu_cs_n_p => cpu_cs_n_p, - cpu_oe_n_p => cpu_oe_n_p, - cpu_d_p => cpu_d_p, - cpu_irq_p => cpu_irq_p, - cpu_fiq_p => cpu_fiq_p, - cpu_wait_n_p => cpu_wait_n_p, - cpu_din => cpu_din, - cpu_a => cpu_a, - cpu_we => cpu_we, - cpu_re => cpu_re, - cpu_dout => cpu_dout); - - - cpu_fpga_regs: - zpuio port map( - areset => areset, - cpu_clk => cpu_clk, - clk_status => clk_status, - cpu_din => cpu_din, - cpu_a => cpu_a, - cpu_we => cpu_we, - cpu_re => cpu_re, - cpu_dout => cpu_dout); - - -end behave; diff --git a/zpu/hdl/zpu3/src/ic300_config.vhd b/zpu/hdl/zpu3/src/ic300_config.vhd deleted file mode 100644 index 9d3f939..0000000 --- a/zpu/hdl/zpu3/src/ic300_config.vhd +++ /dev/null @@ -1,20 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.all; - -package phi_config is - - constant Fpga_Global_Base : std_logic_vector(19 downto 17) := "000"; -- 0x0280.... - constant Clock_Stat_Reg_Addr : std_logic_vector(3 downto 1) := "000"; -- 0x....0000 - constant Testreg32_Lower_Addr : std_logic_vector(3 downto 1) := "110"; -- 0x....000C - constant Testreg32_Upper_Addr : std_logic_vector(3 downto 1) := "111"; -- 0x....000E - - constant Fpga_DDR_Ctrl_Base : std_logic_vector(19 downto 17) := "111"; -- 0x028E.... - constant DDR_Ctrl_Reg_Addr : std_logic_vector(3 downto 1) := "000"; -- 0x....0000 - constant DDR_Mode_Reg_Addr : std_logic_vector(3 downto 1) := "001"; -- 0x....0002 - - -- These are temporary test registers only! - constant DDR_Data_Reg_Addr : std_logic_vector(3 downto 1) := "100"; -- 0x....0008 - constant DDR_Addr_Reg_Addr : std_logic_vector(3 downto 1) := "101"; -- 0x....000A - constant DDR_Req_Reg_Addr : std_logic_vector(3 downto 1) := "110"; -- 0x....000C - -end phi_config; diff --git a/zpu/hdl/zpu3/src/ic300pkg.vhd b/zpu/hdl/zpu3/src/ic300pkg.vhd deleted file mode 100644 index 13da306..0000000 --- a/zpu/hdl/zpu3/src/ic300pkg.vhd +++ /dev/null @@ -1,88 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.all; - -package ic300pkg is - - component ic300 is - port ( -- Clock inputs - cpu_clk_p : in std_logic; - - -- CPU interface signals - cpu_a_p : in std_logic_vector(20 downto 0); - cpu_wr_n_p : in std_logic_vector(1 downto 0); - cpu_cs_n_p : in std_logic_vector(3 downto 1); - cpu_oe_n_p : in std_logic; - cpu_d_p : inout std_logic_vector(15 downto 0); - cpu_irq_p : out std_logic_vector(1 downto 0); - cpu_fiq_p : out std_logic; - cpu_wait_n_p : out std_logic; - - -- DDR SDRAM Signals - sdr_clk_p : out std_logic; -- ddr_sdram_clock - sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock - cke_q_p : out std_logic; -- clock enable - cs_qn_p : out std_logic; -- /chip select - ras_qn_p : inout std_logic; -- /ras - cas_qn_p : inout std_logic; -- /cas - we_qn_p : inout std_logic; -- /write enable - dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00" - dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write - ba_q_p : out std_logic_vector(1 downto 0); -- bank select - sdr_a_p : out std_logic_vector(12 downto 0); -- address bus - sdr_d_p : inout std_logic_vector(15 downto 0); -- bidir data bus - sdr_clk_fb_p : in std_logic -- DDR clock feedback - ); - end component; - - component clocks is - port ( areset : in std_logic; - cpu_clk_p : in std_logic; - sdr_clk_fb_p : in std_logic; - cpu_clk : out std_logic; - cpu_clk_2x : out std_logic; - cpu_clk_4x : out std_logic; - ddr_in_clk : out std_logic; - ddr_in_clk_2x : out std_logic; - locked : out std_logic_vector(2 downto 0)); - end component; - - component cpu_regs is - port ( areset : in std_logic; - cpu_clk : in std_logic; - clk_status : in std_logic_vector(2 downto 0); - cpu_din : in std_logic_vector(15 downto 0); - cpu_a : in std_logic_vector(20 downto 0); - cpu_we : in std_logic_vector(1 downto 0); - cpu_re : in std_logic; - cpu_dout : inout std_logic_vector(15 downto 0)); - end component; - - component ddr_bridge is - port ( areset : in std_logic; - cpu_clk : in std_logic; - cpu_clk_2x : in std_logic; - cpu_clk_4x : in std_logic; - ddr_in_clk : in std_logic; - ddr_in_clk_2x : in std_logic; - - cpu_we : in std_logic_vector(1 downto 0); - cpu_re : in std_logic; - cpu_din : in std_logic_vector(15 downto 0); - cpu_a : in std_logic_vector(20 downto 0); - cpu_dout : inout std_logic_vector(15 downto 0); - - sdr_clk_p : out std_logic; -- ddr_sdram_clock - sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock - cke_q_p : out std_logic; -- clock enable - cs_qn_p : out std_logic; -- /chip select - ras_qn_p : inout std_logic; -- /ras - cas_qn_p : inout std_logic; -- /cas - we_qn_p : inout std_logic; -- /write enable - dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00" - dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write - ba_q_p : out std_logic_vector(1 downto 0); -- bank select - sdr_a_p : out std_logic_vector(12 downto 0); -- address bus - sdr_d_p : inout std_logic_vector(15 downto 0)); -- bidir data bus - end component; - -end ic300pkg; diff --git a/zpu/hdl/zpu3/src/io.vhd b/zpu/hdl/zpu3/src/io.vhd deleted file mode 100644 index 6b50ca1..0000000 --- a/zpu/hdl/zpu3/src/io.vhd +++ /dev/null @@ -1,95 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -use std.textio.all; - -library zylin; -use zylin.zpu_config.all; -use zylin.zpupkg.all; -use zylin.txt_util.all; - -entity zpu_io is - generic ( - log_file: string := "log.txt" - ); - port( - clk : in std_logic; - areset : in std_logic; - busy : out std_logic; - writeEnable : in std_logic; - readEnable : in std_logic; - write : in std_logic_vector(7 downto 0); - read : out std_logic_vector(7 downto 0); - addr : in std_logic_vector(maxAddrBit downto minAddrBit) - ); -end zpu_io; - - -architecture behave of zpu_io is - - - -signal timer_read : std_logic_vector(7 downto 0); ---signal timer_write : std_logic_vector(7 downto 0); -signal timer_we : std_logic; - -file l_file : TEXT open write_mode is log_file; - -begin - - - timerinst: timer port map ( - clk => clk, - areset => areset, - we => timer_we, - din => write, - adr => addr(4 downto 2), - dout => timer_read); - - - process(areset, clk) - begin - if (areset = '1') then - timer_we <= '0'; - busy <= '1'; - elsif (clk'event and clk = '1') then - busy <= '1'; - timer_we <= '0'; - if writeEnable = '1' then - -- external interface - if addr=x"1000" then - -- Write to UART - -- report "" & character'image(conv_integer(memBint)) severity note; - print(l_file, character'val(conv_integer(write))); - busy <= '0'; - elsif addr(12)='1' then - timer_we <= '1'; - busy <= '0'; - else - report "Illegal IO write" severity failure; - end if; - - end if; - if (readEnable = '1') then - if addr=x"1001" then - read <= (0=>'1', others => '0'); -- recieve empty - busy <= '0'; - elsif addr(12)='1' then - read <= timer_read; - busy <= '0'; - elsif addr(11)='1' then - read <= ZPU_Frequency; - busy <= '0'; - else - report "Illegal IO read" severity failure; - end if; - else - read <= (others => '1'); - end if; - end if; - end process; - - -end behave; - diff --git a/zpu/hdl/zpu3/src/log.txt b/zpu/hdl/zpu3/src/log.txt deleted file mode 100644 index 5557b06..0000000 --- a/zpu/hdl/zpu3/src/log.txt +++ /dev/null @@ -1,156 +0,0 @@ - - - -D -h -r -y -s -t -o -n -e - -B -e -n -c -h -m -a -r -k -, - -V -e -r -s -i -o -n - -2 -. -1 - -( -L -a -n -g -u -a -g -e -: - -C -) - - - - - - -P -r -o -g -r -a -m - -c -o -m -p -i -l -e -d - -w -i -t -h -o -u -t - -' -r -e -g -i -s -t -e -r -' - -a -t -t -r -i -b -u -t -e - - - - - - -E -x -e -c -u -t -i -o -n - -s -t -a -r -t -s -, - -2 -0 -0 -0 -0 -0 - -r -u -n -s - -t -h -r -o -u -g -h - -D -h -r -y -s -t -o -n -e - - - diff --git a/zpu/hdl/zpu3/src/niltrace.vhd b/zpu/hdl/zpu3/src/niltrace.vhd deleted file mode 100644 index 40fc1ca..0000000 --- a/zpu/hdl/zpu3/src/niltrace.vhd +++ /dev/null @@ -1,26 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -use std.textio.all; -use work.zpu_config.all; - - -entity trace is - port( - clk : in std_logic; - begin_inst : in std_logic; - pc : in std_logic_vector(maxAddrBit downto 0); - opcode : in std_logic_vector(7 downto 0); - sp : in std_logic_vector(maxAddrBit downto 2); - memA : in std_logic_vector(wordSize-1 downto 0); - busy : in std_logic); -end trace; - - -architecture behave of trace is - -begin - -end behave; - diff --git a/zpu/hdl/zpu3/src/sim_fpga_top.vhd b/zpu/hdl/zpu3/src/sim_fpga_top.vhd deleted file mode 100644 index 3044606..0000000 --- a/zpu/hdl/zpu3/src/sim_fpga_top.vhd +++ /dev/null @@ -1,127 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 20:15:31 04/14/05 --- Design Name: --- Module Name: fpga_top - behave --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. -library UNISIM; -use UNISIM.VComponents.all; - -library zylin; -use zylin.zpu_config.all; -use zylin.zpupkg.all; - -entity fpga_top is -end fpga_top; - -architecture behave of fpga_top is - - -signal clk : std_logic; - -signal areset : std_logic; - - -component zpu_top is - Port ( clk : in std_logic; - areset : in std_logic; - io_busy : in std_logic; - io_read : in std_logic_vector(7 downto 0); - io_write : out std_logic_vector(7 downto 0); - io_addr : out std_logic_vector(maxAddrBit downto minAddrBit); - io_writeEnable : out std_logic; - io_readEnable : out std_logic; - interrupt : in std_logic; - break : out std_logic); -end component; - - -component zpu_io is - generic ( - log_file: string := "log.txt" - ); - port( - clk : in std_logic; - areset : in std_logic; - busy : out std_logic; - writeEnable : in std_logic; - readEnable : in std_logic; - write : in std_logic_vector(7 downto 0); - read : out std_logic_vector(7 downto 0); - addr : in std_logic_vector(maxAddrBit downto minAddrBit) - ); -end component; - - - -signal io_busy : std_logic; -signal io_read : std_logic_vector(7 downto 0); -signal io_write : std_logic_vector(7 downto 0); -signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit); -signal io_writeEnable : std_logic; -signal io_readEnable : std_logic; - -signal break : std_logic; - -begin - poweronreset: roc port map (O => areset); - - - - zpu: zpu_top port map ( - clk => clk , - areset => areset, - io_busy => io_busy, - io_read => io_read, - io_write => io_write, - io_addr => io_addr, - io_writeEnable => io_writeEnable, - io_readEnable => io_readEnable, - interrupt => '0', - break => break); - - - ioMap: zpu_io port map ( - clk => clk, - areset => areset, - busy => io_busy, - writeEnable => io_writeEnable, - readEnable => io_readEnable, - write => io_write, - read => io_read, - addr => io_addr - ); - - - - -- wiggle the clock @ 100MHz - clock : PROCESS - begin - clk <= '0'; - wait for 5 ns; - clk <= '1'; - wait for 5 ns; - end PROCESS clock; - - -end behave; diff --git a/zpu/hdl/zpu3/src/status.txt b/zpu/hdl/zpu3/src/status.txt deleted file mode 100644 index df8773a..0000000 --- a/zpu/hdl/zpu3/src/status.txt +++ /dev/null @@ -1,67 +0,0 @@ -- Make LOADSP/STORESP/ADDSP/PUSHPC & OR emulated => From 444 => 428 LUT. - A pitiful saving in return for destroying performance. -- If I reduce datapath to 8(which is useless) => 197 LUT. - -Bare bones version of ZPU3: - -- remove NOP, PUSHPC, STORESP, LOADSP, ADDSP and OR instructions. This requires - modification to the GCC toolchain and will result in a fairly significant - code increase. We should still do better than ARM though. -- reduce datapath to 16 bits. This will reduce stack usage, which is good. -- 4kBytes of RAM. - - [exec] ========================================================================= - [exec] Device utilization summary: - [exec] --------------------------- - [exec] Selected Device : 3s400ft256-4 - [exec] Number of Slices: 167 out of 3584 4% - [exec] Number of Slice Flip Flops: 126 out of 7168 1% - [exec] Number of 4 input LUTs: 288 out of 7168 4% - [exec] Number of bonded IOBs: 49 out of 173 28% - [exec] Number of BRAMs: 1 out of 16 6% - [exec] Number of GCLKs: 1 out of 8 12% - [exec] ========================================================================= - - - - -Measurements: - -- Removing PUSHPC(which is possible) reduces usage by 2 LUT's. -- I tried to introduce the instructions as seperate states at the top level, - but did not succeed in reducing LUT count. This might be an avenue to - pursue if asynchronous(?) ROM's could replace logic. -- 550 LUT @ 76MHz. 32 bit datapath & 8 bit instructions. Added seperate decode - stage. -- Tried to move memAControl into decoded opcode. Usage went up to 594 from 550. - -- using 16 bit opcodes to encode signals directly. 466 LUT's. -- w/2kBytes 32 RAM & 32 bit opcodes. 415 LUT's. -- 16 bit opcode, 16 bit datapath and 1kbyte RAM. 292 LUT's. - -- 725 LUT's @ 63MHz - Minimum period: 15.909ns{1} (Maximum frequency: 62.858MHz) -- removed addsp, loadsp & storesp. => 670 LUT's. -- removed all pushes & pops to sp. => 638 LUT's. -- removed OR instruction. => 672 LUT's. -- on the second cycle an ADD is done regardless => 713 LUT's. -- using others => 'x' for e.g. pushsp. 713 => 703. -- switching from lots of prioritized if() for decoding instruction to a case - statement. 713 => 631. -- Using ZPU1's memory scheme instead of inferred memory. 713 => 715, i.e. no - difference. -- Removing AddSP. 715 => 704 LUT's. -- Add COMPARE. 715 => 743 LUT's. -- Slight reorganization of binary operand & NOP 715 => 704. -- STORE only pops 1 (which can be fixed in the assembler). 704 => 701. -- Remove NOP. NOP is only used to clear idim_flag. Use NOT instead. -- Removing FLIP. 681 => 646. Using a different way to generate the FLIP, - 681 => 679. -- Add a seperate memory system for code? -- Use IDIM_FLAG to cache value before IM and make add single cycle. - -- by expanding the opcode to 32 bits, encoding everything in the opcode & - using case statements. 713 => 433 LUT. -- 32 bit opcode w/encoded state & 16 bit datapath. => 325 LUT -- by using 512 byte RAM, 16 bit datapath and 32 bit instructions => 285. - diff --git a/zpu/hdl/zpu3/src/testlut.vhd b/zpu/hdl/zpu3/src/testlut.vhd deleted file mode 100644 index fcc8fde..0000000 --- a/zpu/hdl/zpu3/src/testlut.vhd +++ /dev/null @@ -1,106 +0,0 @@ --- Company: Zylin AS --- --- Hooks up the ZPU to physical pads to ensure that it is not optimized to --- oblivion. This is purely to have something to measure LUT usage against. --- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library zylin; -use zylin.zpu_config.all; -use zylin.zpupkg.all; - -entity ic300 is - port ( -- Clock inputs - cpu_clk_p : in std_logic; - - -- CPU interface signals - cpu_a_p : in std_logic_vector(20 downto 0); - cpu_wr_n_p : in std_logic_vector(1 downto 0); - cpu_cs_n_p : in std_logic_vector(3 downto 1); - cpu_oe_n_p : in std_logic; - cpu_d_p : out std_logic_vector(15 downto 0); - cpu_irq_p : out std_logic_vector(1 downto 0); - cpu_fiq_p : out std_logic; - cpu_wait_n_p : out std_logic; - - sdr_clk_fb_p : in std_logic -- DDR clock feedback - ); -end ic300; - -architecture behave of ic300 is - - -signal io_busy : std_logic; -signal io_read : std_logic_vector(7 downto 0); -signal io_write : std_logic_vector(7 downto 0); -signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit); -signal io_writeEnable : std_logic; -signal io_readEnable : std_logic; - - -signal cpu_we : std_logic_vector(1 downto 0); -signal cpu_re : std_logic; -signal areset : std_logic; - --- Clock module signals -signal clk_status : std_logic_vector(2 downto 0); -signal cpu_clk : std_logic; -signal cpu_clk_2x : std_logic; -signal cpu_clk_4x : std_logic; -signal ddr_in_clk : std_logic; - - --- Internal CPU interface signals -signal cpu_din : std_logic_vector(15 downto 0); -signal cpu_dout : std_logic_vector(15 downto 0); -signal cpu_a : std_logic_vector(20 downto 0); - -signal dummy : std_logic_vector(maxAddrBit downto minAddrBit+5); - -begin - - areset <= '0'; -- MUST BE CHANGED TO SOMETHING CORRECT - --- cpu_d_p <= (others => '0'); - cpu_irq_p <= (others => '0'); - cpu_fiq_p <= '0'; - cpu_wait_n_p <= '0'; - - cpu_d_p(15 downto 15) <= (others => '0'); - - -- delay signals going out/in w/1 clk so the - -- ZPU does not have to drive those pins. - -- - -- these registers can be placed close to the ZPU and these - -- registers then have a full clock to drive the pins. - process(cpu_clk_p, areset) - begin - if (cpu_clk_p'event and cpu_clk_p = '1') then - cpu_d_p(0) <= io_writeEnable; - cpu_d_p(1) <= io_readEnable; - cpu_d_p(9 downto 2) <= io_write; - io_read <= cpu_a_p(7 downto 0); - -- 32 read/write registers is plenty realisitic for a minimal size - -- soft-CPU - cpu_d_p(14 downto 10) <= io_addr(minAddrBit+4 downto minAddrBit); - end if; - end process; - - - zpu: zpu_top port map ( - clk => cpu_clk_p , - areset => areset, - io_busy => '0', - io_writeEnable => io_writeEnable, - io_readEnable => io_readEnable, - io_write => io_write, - io_read => io_read, - io_addr => io_addr, - interrupt => '0' - ); - - - -end behave; diff --git a/zpu/hdl/zpu3/src/timer.vhd b/zpu/hdl/zpu3/src/timer.vhd deleted file mode 100644 index 65836f0..0000000 --- a/zpu/hdl/zpu3/src/timer.vhd +++ /dev/null @@ -1,157 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity timer is - port( - clk : in std_logic; - areset : in std_logic; - we : in std_logic; - din : in std_logic_vector(7 downto 0); - adr : in std_logic_vector(2 downto 0); - dout : out std_logic_vector(7 downto 0)); -end timer; - - -architecture behave of timer is - -signal sample : std_logic; -signal reset : std_logic; - -signal c : std_logic_vector(1 to 7); - -signal cnt : std_logic_vector(63 downto 0); -signal cnt_smp : std_logic_vector(63 downto 0); - -begin - - reset <= '1' when (we = '1' and din(0) = '1') else '0'; - sample <= '1' when (we = '1' and din(1) = '1') else '0'; - - process(clk, areset) -- Carry generation - begin - if areset = '1' then - c <= "0000000"; - elsif (clk'event and clk = '1') then - if reset = '1' then - c <= "0000000"; - else - if cnt(7 downto 0) = "11111110" then - c(1) <= '1'; - else - c(1) <= '0'; - end if; - if cnt(15 downto 8) = "11111111" then - c(2) <= '1'; - else - c(2) <= '0'; - end if; - if cnt(23 downto 16) = "11111111" and c(2) = '1' then - c(3) <= '1'; - else - c(3) <= '0'; - end if; - if cnt(31 downto 24) = "11111111" and c(3) = '1' then - c(4) <= '1'; - else - c(4) <= '0'; - end if; - if cnt(39 downto 32) = "11111111" and c(4) = '1' then - c(5) <= '1'; - else - c(5) <= '0'; - end if; - if cnt(47 downto 40) = "11111111" and c(5) = '1' then - c(6) <= '1'; - else - c(6) <= '0'; - end if; - if cnt(55 downto 48) = "11111111" and c(6) = '1' then - c(7) <= '1'; - else - c(7) <= '0'; - end if; - end if; - end if; - end process; - - process(clk, areset) - begin - if areset = '1' then - cnt <= (others=>'0'); - elsif (clk'event and clk = '1') then - if reset = '1' then - cnt <= (others=>'0'); - else - cnt(7 downto 0) <= cnt(7 downto 0) + '1'; - if c(1) = '1' then - cnt(15 downto 8) <= cnt(15 downto 8) + '1'; - else - cnt(15 downto 8) <= cnt(15 downto 8); - end if; - if c(2) = '1' and c(1) = '1' then - cnt(23 downto 16) <= cnt(23 downto 16) + '1'; - else - cnt(23 downto 16) <= cnt(23 downto 16); - end if; - if c(3) = '1' and c(1) = '1' then - cnt(31 downto 24) <= cnt(31 downto 24) + '1'; - else - cnt(31 downto 24) <= cnt(31 downto 24); - end if; - if c(4) = '1' and c(1) = '1' then - cnt(39 downto 32) <= cnt(39 downto 32) + '1'; - else - cnt(39 downto 32) <= cnt(39 downto 32); - end if; - if c(5) = '1' and c(1) = '1' then - cnt(47 downto 40) <= cnt(47 downto 40) + '1'; - else - cnt(47 downto 40) <= cnt(47 downto 40); - end if; - if c(6) = '1' and c(1) = '1' then - cnt(55 downto 48) <= cnt(55 downto 48) + '1'; - else - cnt(55 downto 48) <= cnt(55 downto 48); - end if; - if c(7) = '1' and c(1) = '1' then - cnt(63 downto 56) <= cnt(63 downto 56) + '1'; - else - cnt(63 downto 56) <= cnt(63 downto 56); - end if; - end if; - end if; - end process; - - process(clk, areset) - begin - if areset = '1' then - cnt_smp <= (others=>'0'); - elsif (clk'event and clk = '1') then - if reset = '1' then - cnt_smp <= (others=>'0'); - elsif sample = '1' then - cnt_smp <= cnt; - else - cnt_smp <= cnt_smp; - end if; - end if; - end process; - - process(cnt_smp, adr) - begin - case adr is - when "000" => dout <= cnt_smp(7 downto 0); - when "001" => dout <= cnt_smp(15 downto 8); - when "010" => dout <= cnt_smp(23 downto 16); - when "011" => dout <= cnt_smp(31 downto 24); - when "100" => dout <= cnt_smp(39 downto 32); - when "101" => dout <= cnt_smp(47 downto 40); - when "110" => dout <= cnt_smp(55 downto 48); - when others => dout <= cnt_smp(63 downto 56); - end case; - end process; - - -end behave; - diff --git a/zpu/hdl/zpu3/src/trace.vhd b/zpu/hdl/zpu3/src/trace.vhd deleted file mode 100644 index 81eb448..0000000 --- a/zpu/hdl/zpu3/src/trace.vhd +++ /dev/null @@ -1,80 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; ---use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -use std.textio.all; - -library zylin; -use zylin.zpu_config.all; -use zylin.zpupkg.all; -use zylin.txt_util.all; - - -entity trace is - generic ( - log_file: string := "trace.txt" - ); - port( - clk : in std_logic; - begin_inst : in std_logic; - pc : in std_logic_vector(maxAddrBit downto 0); - opcode : in std_logic_vector(7 downto 0); - sp : in std_logic_vector(maxAddrBit downto 2); - memA : in std_logic_vector(wordSize-1 downto 0); - memB : in std_logic_vector(wordSize-1 downto 0); - busy : in std_logic - ); -end trace; - - -architecture behave of trace is - - -file l_file : TEXT open write_mode is log_file; - - -begin - - --- write data and control information to a file - -receive_data: process - -variable l: line; -variable t : std_logic_vector(wordSize-1 downto 0); -variable t2 : std_logic_vector(maxAddrBit downto 0); - - - -begin - - t:= (others => '0'); - t2:= (others => '0'); - - -- print header for the logfile - print(l_file, "#pc,opcode,sp,top_of_stack "); - print(l_file, "#----------"); - print(l_file, " "); - - wait until clk = '1'; - wait until clk = '0'; - - while true loop - - if begin_inst = '1' then - t(maxAddrBit downto 2):=sp; - t2:=pc; - print(l_file, "0x" & hstr(t2) & " 0x" & hstr(opcode) & " 0x" & hstr(t) & " 0x" & hstr(memA) & " 0x" & hstr(memB)); - end if; - - wait until clk = '0'; - - end loop; - - end process receive_data; - - - -end behave; - diff --git a/zpu/hdl/zpu3/src/txt_util.vhd b/zpu/hdl/zpu3/src/txt_util.vhd deleted file mode 100644 index d42303b..0000000 --- a/zpu/hdl/zpu3/src/txt_util.vhd +++ /dev/null @@ -1,586 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use std.textio.all; - - -package txt_util is - - -- prints a message to the screen - procedure print(text: string); - - -- prints the message when active - -- useful for debug switches - procedure print(active: boolean; text: string); - - -- converts std_logic into a character - function chr(sl: std_logic) return character; - - -- converts std_logic into a string (1 to 1) - function str(sl: std_logic) return string; - - -- converts std_logic_vector into a string (binary base) - function str(slv: std_logic_vector) return string; - - -- converts boolean into a string - function str(b: boolean) return string; - - -- converts an integer into a single character - -- (can also be used for hex conversion and other bases) - function chr(int: integer) return character; - - -- converts integer into string using specified base - function str(int: integer; base: integer) return string; - - -- converts integer to string, using base 10 - function str(int: integer) return string; - - -- convert std_logic_vector into a string in hex format - function hstr(slv: std_logic_vector) return string; - - - -- functions to manipulate strings - ----------------------------------- - - -- convert a character to upper case - function to_upper(c: character) return character; - - -- convert a character to lower case - function to_lower(c: character) return character; - - -- convert a string to upper case - function to_upper(s: string) return string; - - -- convert a string to lower case - function to_lower(s: string) return string; - - - - -- functions to convert strings into other formats - -------------------------------------------------- - - -- converts a character into std_logic - function to_std_logic(c: character) return std_logic; - - -- converts a string into std_logic_vector - function to_std_logic_vector(s: string) return std_logic_vector; - - - - -- file I/O - ----------- - - -- read variable length string from input file - procedure str_read(file in_file: TEXT; - res_string: out string); - - -- print string to a file and start new line - procedure print(file out_file: TEXT; - new_string: in string); - - -- print character to a file and start new line - procedure print(file out_file: TEXT; - char: in character); - -end txt_util; - - - - -package body txt_util is - - - - - -- prints text to the screen - - procedure print(text: string) is - variable msg_line: line; - begin - write(msg_line, text); - writeline(output, msg_line); - end print; - - - - - -- prints text to the screen when active - - procedure print(active: boolean; text: string) is - begin - if active then - print(text); - end if; - end print; - - - -- converts std_logic into a character - - function chr(sl: std_logic) return character is - variable c: character; - begin - case sl is - when 'U' => c:= 'U'; - when 'X' => c:= 'X'; - when '0' => c:= '0'; - when '1' => c:= '1'; - when 'Z' => c:= 'Z'; - when 'W' => c:= 'W'; - when 'L' => c:= 'L'; - when 'H' => c:= 'H'; - when '-' => c:= '-'; - end case; - return c; - end chr; - - - - -- converts std_logic into a string (1 to 1) - - function str(sl: std_logic) return string is - variable s: string(1 to 1); - begin - s(1) := chr(sl); - return s; - end str; - - - - -- converts std_logic_vector into a string (binary base) - -- (this also takes care of the fact that the range of - -- a string is natural while a std_logic_vector may - -- have an integer range) - - function str(slv: std_logic_vector) return string is - variable result : string (1 to slv'length); - variable r : integer; - begin - r := 1; - for i in slv'range loop - result(r) := chr(slv(i)); - r := r + 1; - end loop; - return result; - end str; - - - function str(b: boolean) return string is - - begin - if b then - return "true"; - else - return "false"; - end if; - end str; - - - -- converts an integer into a character - -- for 0 to 9 the obvious mapping is used, higher - -- values are mapped to the characters A-Z - -- (this is usefull for systems with base > 10) - -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) - - function chr(int: integer) return character is - variable c: character; - begin - case int is - when 0 => c := '0'; - when 1 => c := '1'; - when 2 => c := '2'; - when 3 => c := '3'; - when 4 => c := '4'; - when 5 => c := '5'; - when 6 => c := '6'; - when 7 => c := '7'; - when 8 => c := '8'; - when 9 => c := '9'; - when 10 => c := 'A'; - when 11 => c := 'B'; - when 12 => c := 'C'; - when 13 => c := 'D'; - when 14 => c := 'E'; - when 15 => c := 'F'; - when 16 => c := 'G'; - when 17 => c := 'H'; - when 18 => c := 'I'; - when 19 => c := 'J'; - when 20 => c := 'K'; - when 21 => c := 'L'; - when 22 => c := 'M'; - when 23 => c := 'N'; - when 24 => c := 'O'; - when 25 => c := 'P'; - when 26 => c := 'Q'; - when 27 => c := 'R'; - when 28 => c := 'S'; - when 29 => c := 'T'; - when 30 => c := 'U'; - when 31 => c := 'V'; - when 32 => c := 'W'; - when 33 => c := 'X'; - when 34 => c := 'Y'; - when 35 => c := 'Z'; - when others => c := '?'; - end case; - return c; - end chr; - - - - -- convert integer to string using specified base - -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) - - function str(int: integer; base: integer) return string is - - variable temp: string(1 to 10); - variable num: integer; - variable abs_int: integer; - variable len: integer := 1; - variable power: integer := 1; - - begin - - -- bug fix for negative numbers - abs_int := abs(int); - - num := abs_int; - - while num >= base loop -- Determine how many - len := len + 1; -- characters required - num := num / base; -- to represent the - end loop ; -- number. - - for i in len downto 1 loop -- Convert the number to - temp(i) := chr(abs_int/power mod base); -- a string starting - power := power * base; -- with the right hand - end loop ; -- side. - - -- return result and add sign if required - if int < 0 then - return '-'& temp(1 to len); - else - return temp(1 to len); - end if; - - end str; - - - -- convert integer to string, using base 10 - function str(int: integer) return string is - - begin - - return str(int, 10) ; - - end str; - - - - -- converts a std_logic_vector into a hex string. - function hstr(slv: std_logic_vector) return string is - variable hexlen: integer; - variable longslv : std_logic_vector(67 downto 0) := (others => '0'); - variable hex : string(1 to 16); - variable fourbit : std_logic_vector(3 downto 0); - begin - hexlen := (slv'left+1)/4; - if (slv'left+1) mod 4 /= 0 then - hexlen := hexlen + 1; - end if; - longslv(slv'left downto 0) := slv; - for i in (hexlen -1) downto 0 loop - fourbit := longslv(((i*4)+3) downto (i*4)); - case fourbit is - when "0000" => hex(hexlen -I) := '0'; - when "0001" => hex(hexlen -I) := '1'; - when "0010" => hex(hexlen -I) := '2'; - when "0011" => hex(hexlen -I) := '3'; - when "0100" => hex(hexlen -I) := '4'; - when "0101" => hex(hexlen -I) := '5'; - when "0110" => hex(hexlen -I) := '6'; - when "0111" => hex(hexlen -I) := '7'; - when "1000" => hex(hexlen -I) := '8'; - when "1001" => hex(hexlen -I) := '9'; - when "1010" => hex(hexlen -I) := 'A'; - when "1011" => hex(hexlen -I) := 'B'; - when "1100" => hex(hexlen -I) := 'C'; - when "1101" => hex(hexlen -I) := 'D'; - when "1110" => hex(hexlen -I) := 'E'; - when "1111" => hex(hexlen -I) := 'F'; - when "ZZZZ" => hex(hexlen -I) := 'z'; - when "UUUU" => hex(hexlen -I) := 'u'; - when "XXXX" => hex(hexlen -I) := 'x'; - when others => hex(hexlen -I) := '?'; - end case; - end loop; - return hex(1 to hexlen); - end hstr; - - - - -- functions to manipulate strings - ----------------------------------- - - - -- convert a character to upper case - - function to_upper(c: character) return character is - - variable u: character; - - begin - - case c is - when 'a' => u := 'A'; - when 'b' => u := 'B'; - when 'c' => u := 'C'; - when 'd' => u := 'D'; - when 'e' => u := 'E'; - when 'f' => u := 'F'; - when 'g' => u := 'G'; - when 'h' => u := 'H'; - when 'i' => u := 'I'; - when 'j' => u := 'J'; - when 'k' => u := 'K'; - when 'l' => u := 'L'; - when 'm' => u := 'M'; - when 'n' => u := 'N'; - when 'o' => u := 'O'; - when 'p' => u := 'P'; - when 'q' => u := 'Q'; - when 'r' => u := 'R'; - when 's' => u := 'S'; - when 't' => u := 'T'; - when 'u' => u := 'U'; - when 'v' => u := 'V'; - when 'w' => u := 'W'; - when 'x' => u := 'X'; - when 'y' => u := 'Y'; - when 'z' => u := 'Z'; - when others => u := c; - end case; - - return u; - - end to_upper; - - - -- convert a character to lower case - - function to_lower(c: character) return character is - - variable l: character; - - begin - - case c is - when 'A' => l := 'a'; - when 'B' => l := 'b'; - when 'C' => l := 'c'; - when 'D' => l := 'd'; - when 'E' => l := 'e'; - when 'F' => l := 'f'; - when 'G' => l := 'g'; - when 'H' => l := 'h'; - when 'I' => l := 'i'; - when 'J' => l := 'j'; - when 'K' => l := 'k'; - when 'L' => l := 'l'; - when 'M' => l := 'm'; - when 'N' => l := 'n'; - when 'O' => l := 'o'; - when 'P' => l := 'p'; - when 'Q' => l := 'q'; - when 'R' => l := 'r'; - when 'S' => l := 's'; - when 'T' => l := 't'; - when 'U' => l := 'u'; - when 'V' => l := 'v'; - when 'W' => l := 'w'; - when 'X' => l := 'x'; - when 'Y' => l := 'y'; - when 'Z' => l := 'z'; - when others => l := c; - end case; - - return l; - - end to_lower; - - - - -- convert a string to upper case - - function to_upper(s: string) return string is - - variable uppercase: string (s'range); - - begin - - for i in s'range loop - uppercase(i):= to_upper(s(i)); - end loop; - return uppercase; - - end to_upper; - - - - -- convert a string to lower case - - function to_lower(s: string) return string is - - variable lowercase: string (s'range); - - begin - - for i in s'range loop - lowercase(i):= to_lower(s(i)); - end loop; - return lowercase; - - end to_lower; - - - --- functions to convert strings into other types - - --- converts a character into a std_logic - -function to_std_logic(c: character) return std_logic is - variable sl: std_logic; - begin - case c is - when 'U' => - sl := 'U'; - when 'X' => - sl := 'X'; - when '0' => - sl := '0'; - when '1' => - sl := '1'; - when 'Z' => - sl := 'Z'; - when 'W' => - sl := 'W'; - when 'L' => - sl := 'L'; - when 'H' => - sl := 'H'; - when '-' => - sl := '-'; - when others => - sl := 'X'; - end case; - return sl; - end to_std_logic; - - --- converts a string into std_logic_vector - -function to_std_logic_vector(s: string) return std_logic_vector is - variable slv: std_logic_vector(s'high-s'low downto 0); - variable k: integer; -begin - k := s'high-s'low; - for i in s'range loop - slv(k) := to_std_logic(s(i)); - k := k - 1; - end loop; - return slv; -end to_std_logic_vector; - - - - - - ----------------- --- file I/O -- ----------------- - - - --- read variable length string from input file - -procedure str_read(file in_file: TEXT; - res_string: out string) is - - variable l: line; - variable c: character; - variable is_string: boolean; - - begin - - readline(in_file, l); - -- clear the contents of the result string - for i in res_string'range loop - res_string(i) := ' '; - end loop; - -- read all characters of the line, up to the length - -- of the results string - for i in res_string'range loop - read(l, c, is_string); - res_string(i) := c; - if not is_string then -- found end of line - exit; - end if; - end loop; - -end str_read; - - --- print string to a file -procedure print(file out_file: TEXT; - new_string: in string) is - - variable l: line; - - begin - - write(l, new_string); - writeline(out_file, l); - -end print; - - --- print character to a file and start new line -procedure print(file out_file: TEXT; - char: in character) is - - variable l: line; - - begin - - write(l, char); - writeline(out_file, l); - -end print; - - - --- appends contents of a string to a file until line feed occurs --- (LF is considered to be the end of the string) - -procedure str_write(file out_file: TEXT; - new_string: in string) is - begin - - for i in new_string'range loop - print(out_file, new_string(i)); - if new_string(i) = LF then -- end of string - exit; - end if; - end loop; - -end str_write; - - - - -end txt_util; - - - - diff --git a/zpu/hdl/zpu3/src/xilinx_dualport.vhd b/zpu/hdl/zpu3/src/xilinx_dualport.vhd deleted file mode 100644 index 0e6edc9..0000000 --- a/zpu/hdl/zpu3/src/xilinx_dualport.vhd +++ /dev/null @@ -1,1482 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11:47:36 03/22/05 --- Design Name: --- Module Name: mem_sys - behave --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. -library UNISIM; -use UNISIM.VComponents.all; -library zylin; -use zylin.zpu_config.all; - -entity dualport_ram is -port (clk : in std_logic; - memAWriteEnable : in std_logic; - memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit); - memAWrite : in std_logic_vector(wordSize-1 downto 0); - memARead : out std_logic_vector(wordSize-1 downto 0); - memBWriteEnable : in std_logic; - memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit); - memBWrite : in std_logic_vector(wordSize-1 downto 0); - memBRead : out std_logic_vector(wordSize-1 downto 0)); -end dualport_ram; - -architecture dualport_ram_arch of dualport_ram is - - -signal low : std_logic; -signal high : std_logic; -signal re : std_logic; - -begin - - high <= '1'; - low <= '0'; - re <= '1'; - - - ZPU_RAM0 : RAMB16_S2_S2 - generic map ( - INIT_A => X"0", -- Value of output RAM registers on Port A at startup - INIT_B => X"0", -- Value of output RAM registers on Port B at startup - SRVAL_A => X"0", -- Port A ouput value upon SSR assertion - SRVAL_B => X"0", -- Port B ouput value upon SSR assertion - WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE - WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE - SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" - INIT_00 => X"01A100E100010001003600770002006D000F0000000F06AD000302940008003C", - INIT_01 => X"7D4000000741F68100C800030000377935990003000300030003002A00150001", - INIT_02 => X"0007584101010C3D55555555370000000092800000001490000000066A594EBB", - INIT_03 => X"0009015555932D564C093A4024055555564CB555593C1569EA90C00000007000", - INIT_04 => X"BF8AA55961BE2A956586C40A4CB00932C00024A80000024C9569C893C0024E90", - INIT_05 => X"18A1251E2A956586F8AA55961BF8AA55961BE2A956586FE2A956586F8AA55961", - INIT_06 => X"51349D53764E258A2043E21BE5645DE5C4FC00E0100430C140E4665595558750", - INIT_07 => X"47B1656A855555D435575A815D077558E475559E755715A1C364945042425555", - INIT_08 => X"5555F123348C17657C405070D5E745A518B58DD5555F55551D5506F00D707B15", - INIT_09 => X"C141C74DD5137120D51C0715094CC4F01006A8131DD91531B913118944815155", - INIT_0A => X"5E559655003D3549550D458C5994A04D476568D05B0F45451D143E53D0F2CD6B", - INIT_0B => X"4D1E1C5D3474C5C5A1E1C5D34787171C44DC7844D3451D37974D164DD55DD555", - INIT_0C => X"2074532E4C3A5074DE129D074D1137134477D546C01D374DD348774DE15D3717", - INIT_0D => X"875650117671948CB05545A5A2615074889149341D04D4956F843575543E1A19", - INIT_0E => X"F804036D9753106651D5140E6905C158D8979404C7459123540DD9955A43F563", - INIT_0F => X"7958D037C3557056405549520F96E88622775767141BA3755D1418E1BE234480", - INIT_10 => X"294A1C405ACCC3705D5599D55037776149584D8F98F98F98FDD00D904D205421", - INIT_11 => X"74710D5C26798346751441DD555BE179544D8F98F98F98FDD00D910DC3D357C3", - INIT_12 => X"605D5570051840119D04C0DC3755B61D7951D9A9522D995D51D5BB106B90F7C0", - INIT_13 => X"D81BC3646611D695A02D1A9419695D695422C40110C0F85D6F899E4D0D555BC3", - INIT_14 => X"28531104D5F01EDD204141807555735D38346423303676407555545F6B945696", - INIT_15 => X"5212D7645155503146685C599546660676E81041C85D570DCE1B07116F116021", - INIT_16 => X"5F9D03530F840406A5725910604E420D910DD521D6170F9AF0F940D91836445D", - INIT_17 => X"83E03E03C03414D5D5F5D9BE7550DD55775514A145E5405657024C3664F3059C", - INIT_18 => X"444C7584143756C431049D594DC444FD19CE181427555124440155503F58E14D", - INIT_19 => X"D54521B201810644D895159C568F40C6C85503E135203FCF555151102C7343CC", - INIT_1A => X"5A95904431351D93820C4D1AA2C7FD0CD95555311185802971639A1755607515", - INIT_1B => X"E7D41815C826057201815C826057201815C806057209815C82741C75D1BF4336", - INIT_1C => X"41BD443664E14155000C4191440445305B46A8D40443A3E115495503116861C3", - INIT_1D => X"A1520F9C10F850FC18DB80D4777F1D5757195241D35F9754D755DD35F40D9D99", - INIT_1E => X"65E6A10F206870F0557411545536F0D5FA1765C8D5443E658956E52727558D14", - INIT_1F => X"DDD2151D31A956A0400F03FC754175510FD4A34252E0DC4076A5EC66A10FB312", - INIT_20 => X"77C1676610FBD310C3C3CC76F05C9FF20755DC17ECE5451D3472D9D215D34C40", - INIT_21 => X"55556189C508B6C3F0F0FF1D9F4561676610F207A5EF52D7957CC0F8800F7726", - INIT_22 => X"8890203480C224080B251D4352F126920C8CF13E00C15A16445A44DA4F105554", - INIT_23 => X"0F203CF4495240B82923890203080E20B8809249524080C2C0B490210C803203", - INIT_24 => X"854F25C74C20400C1030000B24838A6F858A08E24080F2823890203C80D203C8", - INIT_25 => X"00000C000000001F75D5D74FC0000000000000003FFFFFFFEAAA95438104DA47", - INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_28 => X"0000000000000000000000000000000000000000000154000000000000000000", - INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000", - INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000") - port map ( - DOA => memARead(1 downto 0), -- Port A 2-bit Data Output - DOB => memBRead(1 downto 0), -- Port B 2-bit Data Output - ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input - ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input - CLKA => clk, -- Port A Clock - CLKB => clk, -- Port B Clock - DIA => memAWrite(1 downto 0), -- Port A 2-bit Data Input - DIB => memBWrite(1 downto 0), -- Port B 2-bit Data Input - ENA => re, -- Port A RAM Enable Input - ENB => high, -- PortB RAM Enable Input - SSRA => low, -- Port A Synchronous Set/Reset Input - SSRB => low, -- Port B Synchronous Set/Reset Input - WEA => low, -- Port A Write Enable Input - WEB => memBWriteEnable -- Port B Write Enable Input - ); - ZPU_RAM1 : RAMB16_S2_S2 - generic map ( - INIT_A => X"0", -- Value of output RAM registers on Port A at startup - INIT_B => X"0", -- Value of output RAM registers on Port B at startup - SRVAL_A => X"0", -- Port A ouput value upon SSR assertion - SRVAL_B => X"0", -- Port B ouput value upon SSR assertion - WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE - WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE - SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" - INIT_00 => X"01510111000100020061006B0000004000100002001005510001059A00360064", - INIT_01 => X"40300000064005640380001E0001543802180002000200010002000500110005", - INIT_02 => X"000653709D19C24E555555552400000000920000000024000000000162843876", - INIT_03 => X"0000CC55555DC1557EC5DC00033155555577055555D315607655000000007000", - INIT_04 => X"74818211417206084505C705770000F940000398000001765560745D30017700", - INIT_05 => X"165081C206084505C8182114174818211417206084505D206084505C81821141", - INIT_06 => X"51200592163801450816D095E0044564ADB5C58C82606080118051A1162881C8", - INIT_07 => X"550175554516163566505D44014118AA4818516C185014519662131830201616", - INIT_08 => X"96140906D01981608AF43685992015DA5245D45628675859062835B511755017", - INIT_09 => X"6000B8F861B22CE39C0EC602ED202FC596B59458405845C55118595694001162", - INIT_0A => X"55A58300016D31668D5941040556516111611710005B4D4545716E190280595B", - INIT_0B => X"C968C00BA5BE80B2C68C00B65A3002C1BC8BA32CBE70C3EA02C9CAC89C59458A", - INIT_0C => X"0B1A0D6164EC408F8A047008D9CB622E2D19546CB32362C8BE8312FACC4BA202", - INIT_0D => X"4455CCCC1601143B2E45916976DC147401104104059F14685B456418596D1171", - INIT_0E => X"B4B55655D7453C5DA01654441070416015693378C475DC495A0458256156D15F", - INIT_0F => X"468751645665865943F040105B8164446641416011165018A11454D15D007415", - INIT_10 => X"8175134656FB96434615446289641B554684057595597595D066598611165695", - INIT_11 => X"18A6599B55F856501AD764059656556684017495497495C066598559C91D555D", - INIT_12 => X"5346166005EB404406411356518A35554684656685DD4686446112185F85B684", - INIT_13 => X"D555D6601585546854151468D5568546895EB4044115B4595F454E12599655D6", - INIT_14 => X"335D511B5557C55D467C504218A4E119C7135101456604AE1A05A1555F861668", - INIT_15 => X"91101161116169E0F5D448156855955595171C7110462859E41D55815FD556C1", - INIT_16 => X"153011465B440F059A495550560474598A50591544045B8105B8459841662905", - INIT_17 => X"16E16C16C16514546104654E051C0615418A9450651A1155A1B165662D1D417D", - INIT_18 => X"700111F690095D6159A445904D270024D7D3C3B711855915976D62896C56D165", - INIT_19 => X"62A10F7C5B0C0557D468857E5149D00170C316D15CCD6EC558AD0441D72116D2", - INIT_1A => X"97681F4400824581000023D4516DE3E2517161920D8D38057557861185921514", - INIT_1B => X"E152154484F551212D544846551210954484D551212154484515A45C3B78F895", - INIT_1C => X"457E256626804961925697473A0E2C44D0F51470F47849C431468400D048CD56", - INIT_1D => X"51105B8C05B445B315555C05417946285153C440619C2166018A4619C8598151", - INIT_1E => X"4595955BA2EA0761584405655975B59920519556E9056E0566859A4581645C14", - INIT_1F => X"9055965A909455530D5B16F1185118A55B15520D55159076C55AF455155B50B6", - INIT_20 => X"8085515155B6E90616D6E0146830806841851156724A0EC620DD04559653A415", - INIT_21 => X"75858C001F40514145B5B40507C305515155BA2D93E496D5695545B4605B9418", - INIT_22 => X"0810203080F20408032DA18003C200E266D1C15050400CF788038803844E58A1", - INIT_23 => X"0F203CCF4CF040B12103010203480F208C80A24CF04080D0C03C1023BC82F203", - INIT_24 => X"0600F6CFD04155043040000C38832340070840C04080F2103010203C803203C8", - INIT_25 => X"0A000C00000020061C7185CFEAAAAAAAAAAAAAAA95555555555555540B080387", - INIT_26 => X"0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A", - INIT_27 => X"313A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A", - INIT_28 => X"00000000000000000000000000000000000000000001F0000000000000030000", - INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000", - INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000") - port map ( - DOA => memARead(3 downto 2), -- Port A 2-bit Data Output - DOB => memBRead(3 downto 2), -- Port B 2-bit Data Output - ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input - ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input - CLKA => clk, -- Port A Clock - CLKB => clk, -- Port B Clock - DIA => memAWrite(3 downto 2), -- Port A 2-bit Data Input - DIB => memBWrite(3 downto 2), -- Port B 2-bit Data Input - ENA => re, -- Port A RAM Enable Input - ENB => high, -- PortB RAM Enable Input - SSRA => low, -- Port A Synchronous Set/Reset Input - SSRB => low, -- Port B Synchronous Set/Reset Input - WEA => memAWriteEnable, -- Port A Write Enable Input - WEB => memBWriteEnable -- Port B Write Enable Input - ); - ZPU_RAM2 : RAMB16_S2_S2 - generic map ( - INIT_A => X"0", -- Value of output RAM registers on Port A at startup - INIT_B => X"0", -- Value of output RAM registers on Port B at startup - SRVAL_A => X"0", -- Port A ouput value upon SSR assertion - SRVAL_B => X"0", -- Port B ouput value upon SSR assertion - WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE - WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE - SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" - INIT_00 => X"0008000800000000000000010001002A000200000002000800000080000800C6", - INIT_01 => X"023AAAAAA028A040002A0000000002B000000000000000000000000000080000", - INIT_02 => X"AAA00B000020000C0000000002AAAAAAAA082AAAAAAA828AAAAAAAA008223032", - INIT_03 => X"AAA8CC000000E0000CC00E2AA33000000003800000030008300C2AAAAAAA3AAA", - INIT_04 => X"3C2828002830A0A000A0C020038AA8F02AAAA302AAAAA8000008300032A8038A", - INIT_05 => X"820800C0A0A000A0C282800283C2828002830A0A000A0F0A0A000A0C28280028", - INIT_06 => X"00000C00303000208600C841C0008C028AB00806C170000010000C0080002A30", - INIT_07 => X"8AB83808200000C000020C2000023002A830001E300380080002A00230100000", - INIT_08 => X"0000C00C00322300330800E0008020C088C0E280000B0003CC0020F08038AB83", - INIT_09 => X"40001DA0C0200401080400000CD880A23C00C23008C00A3B20303010102C8000", - INIT_0A => X"0000002AEC0C70000A0093220A8008C0230028EE00032A008CA00C230004F00B", - INIT_0B => X"9030420240C820130704202C1C108041C900C10A2CD04E0C00B34C80380E4000", - INIT_0C => X"8E32028C080030DA0244070DA342C0BC26AA40880A36C0A020D1008304020040", - INIT_0D => X"20A0303230280000AC0020A828028A20220000000C2080000B200030000C82C2", - INIT_0E => X"323200204380C300000080880B80A80B83008D037820E3A00008C0400000C203", - INIT_0F => X"00004800400008012C2000000300820808A323008D800A30008083C81C801000", - INIT_10 => X"8030808000C0002F8C0008C0000230000002200882883881C8CB0002FA000000", - INIT_11 => X"3080000A8030002A3220A08C0002800002200882883881C8CB000200C1200170", - INIT_12 => X"2F8C000AB0282A0A8CAFA006230000040008C8300080100408C08A820B003028", - INIT_13 => X"0002C0020208400002C8C1020800040002C282A0A800320003203C02000000C0", - INIT_14 => X"28002208005C2A840002A08A3009090828820E0900000A823200200507004300", - INIT_15 => X"0880A3000000020F00420E030000A080A0208208828C00000821810007080322", - INIT_16 => X"85002D080320300040088382000800000008C080E0AA0300E030A0000000008C", - INIT_17 => X"80C00C00C0010088C088C83C00028C002300800820000200013834000010B03C", - INIT_18 => X"0A20108A00290E4080038C088C00A20081C12810A30000E0A0A000000C02C804", - INIT_19 => X"C000020C0223C020C300000C002300C20882C0C813280FEF0008C0A8280900C0", - INIT_1A => X"8200000030428C0E008C100108E0CC084020000ABA882800380702E300026028", - INIT_1B => X"C0CE4280A240A02890280A240A02890280A200A02880280A2230228824330210", - INIT_1C => X"081C8000008000008C00C204DC280368800042CE0002C1C0A0000383A00E0280", - INIT_1D => X"0880030E803200308281822223088C00020082C0C08C630003008C08CA000000", - INIT_1E => X"00206003248C882E00238008023030008EB33021D0D00C002020400323020E80", - INIT_1F => X"08CA008A00888008AE0300F230223002030008AE02A00808A040812060030823", - INIT_20 => X"88B0060A0032E00880C0C8322821A22AA3020D83B00D808C182E28CA00878020", - INIT_21 => X"20000C003280A28E2030320C8B8220060A003248C6EA80C3003820302403026A", - INIT_22 => X"C2BA0AAC2AA0AE82A93AAEABA2A0B110EAAFA3EFEE8ABBAAC2C442444F300000", - INIT_23 => X"A90AA4BABAAAE82F04946BA0AAC2AA0AC82AE0BAAAE82AB24E5ABA09E42B90AA", - INIT_24 => X"AA8FAAAAACFBBEE8BED8AAA9EC0AEEBECAC1251AE82A905946BA0AA42AA0AA42", - INIT_25 => X"FAA00C000000700562A2FC8FC00000000000000000000000000000000E02C44E", - INIT_26 => X"FAA5500FFAA5500FFAA5500FFAA5500FFAA5500FFAA5500FFAA5500FFAA5500F", - INIT_27 => X"0D25500FFAA5500FFAA5500FFAA5500FFAA5500FFAA5500FFAA5500FFAA5500F", - INIT_28 => X"0000000000000000000000000000000000000000000080000000000000020000", - INIT_29 => X"00000000000000000CF000000000000000000000000000000000000000000000", - INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000") - port map ( - DOA => memARead(5 downto 4), -- Port A 2-bit Data Output - DOB => memBRead(5 downto 4), -- Port B 2-bit Data Output - ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input - ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input - CLKA => clk, -- Port A Clock - CLKB => clk, -- Port B Clock - DIA => memAWrite(5 downto 4), -- Port A 2-bit Data Input - DIB => memBWrite(5 downto 4), -- Port B 2-bit Data Input - ENA => re, -- Port A RAM Enable Input - ENB => high, -- PortB RAM Enable Input - SSRA => low, -- Port A Synchronous Set/Reset Input - SSRB => low, -- Port B Synchronous Set/Reset Input - WEA => memAWriteEnable, -- Port A Write Enable Input - WEB => memBWriteEnable -- Port B Write Enable Input - ); - ZPU_RAM3 : RAMB16_S2_S2 - generic map ( - INIT_A => X"0", -- Value of output RAM registers on Port A at startup - INIT_B => X"0", -- Value of output RAM registers on Port B at startup - SRVAL_A => X"0", -- Port A ouput value upon SSR assertion - SRVAL_B => X"0", -- Port B ouput value upon SSR assertion - WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE - WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE - SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" - INIT_00 => X"00040044000000020008000200020115000500020005000400020000000C0089", - INIT_01 => X"2975555550165082031500000000017218820002000200020002002000040000", - INIT_02 => X"5550070B0150281C000000008155555555849555555561555555555404117230", - INIT_03 => X"5555EE000000D8000CE00D9557B8000000036000000B80053000555555553555", - INIT_04 => X"31141484143450521050E090036555F0955557015555540000053200B9540365", - INIT_05 => X"4305181450521050D1414841431141484143450521050C450521050D14148414", - INIT_06 => X"088A0C0830B088305988C583C9824C914136660AEABA8A2AAA2A08084081160A", - INIT_07 => X"1544300C14808010800A0C1694A932055632082D3208420448095991A8684080", - INIT_08 => X"008210800A02130B030A8092006990C04620C540821702028C8290F568315443", - INIT_09 => X"9AB92A20C8084AAB01A820AB082640D53AA081A164C265B750A1702032124808", - INIT_0A => X"08016955148DF82021207E5595420685930996D9952351204C588C926A2FC00B", - INIT_0B => X"20E9A590C3A2192A9E9A590C3A6964A7A312A6830CEBA08A6433AA21310CA020", - INIT_0C => X"6E31A15036890AA312FD78AA33A084ACBE61820106E8843108A6A4229A90C4A4", - INIT_0D => X"11510AC9309402005C20185021614512190A28A28CF042020F108232008C45C4", - INIT_0E => X"31214814832100080940422454855404420142448520CC9E00A4C2C40808D90B", - INIT_0F => X"20268482C800150257062188232541244453130942420532044203C43C593612", - INIT_10 => X"7830466802C008134C8064C8208132082025942102102103D4C6202525980008", - INIT_11 => X"3241200540B2481531105A4C0002082025942102102103D4C6202520FB5002B0", - INIT_12 => X"134C801D711635AD4C525809932060882024C4202648202924C855430F223516", - INIT_13 => X"8282C80B91A8820265040201042028202691635AD44231040B103C99200003C8", - INIT_14 => X"9600999400AC154C98015A653207468C14C808871080914131A01A0A0F24C301", - INIT_15 => X"044853098808030C00C111820210C16080C44104654C8220949E86A80B240B19", - INIT_16 => X"4B46A224231280A0801E421B0AA401202064C048D1552324123252026480814C", - INIT_17 => X"48E88E88E8828204C864C42C90814C8053204205108099080A743C809070883D", - INIT_18 => X"0596A8858AA60CAA58004C066C60594203DB16B053201012505808208D03C468", - INIT_19 => X"C818807D4458A0C2C202603D081702E6862888C460988FDF02089AD4164688C6", - INIT_1A => X"420200A2B99B4C29286E640205F1CC088844081F49601684300F25132009D084", - INIT_1B => X"C9C2831215A0C4856831215A0C4856831215A0C485683121593251515C730222", - INIT_1C => X"203D4080904A20086864E4682C918096010081C30A0292C6442020EBD9160148", - INIT_1D => X"0548232D623112344203115113204C82084015E8C94D930063204C94D5202448", - INIT_1E => X"1080842348196501021064050170B2005553108554208C902010C06313012D42", - INIT_1F => X"04C500542A464205692388F93219320523420569084206041080560084234606", - INIT_20 => X"660408084234C2A548C8D63106851905632142433C9D654C965D54C5005B0A92", - INIT_21 => X"00201E21706259615232358C576854080842348195C541C3003112361A235591", - INIT_22 => X"005000100050140005055541515105505555514554414515441544554002020A", - INIT_23 => X"0500145455514015051545000140050014001055514000514054500114005001", - INIT_24 => X"4545554554515544005000055401555541414551400050515450001400500140", - INIT_25 => X"FFF00C000000501394E93A4FC000000000000000000000000000000005041545", - INIT_26 => X"FFFFFFFAAAAAAAA5555555500000000FFFFFFFFAAAAAAAA5555555500000000F", - INIT_27 => X"093FFFFAAAAAAAA5555555500000000FFFFFFFFAAAAAAAA5555555500000000F", - INIT_28 => X"0000000000000000000000000000000000000000000070000000000000000000", - INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000", - INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000") - port map ( - DOA => memARead(7 downto 6), -- Port A 2-bit Data Output - DOB => memBRead(7 downto 6), -- Port B 2-bit Data Output - ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input - ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input - CLKA => clk, -- Port A Clock - CLKB => clk, -- Port B Clock - DIA => memAWrite(7 downto 6), -- Port A 2-bit Data Input - DIB => memBWrite(7 downto 6), -- Port B 2-bit Data Input - ENA => re, -- Port A RAM Enable Input - ENB => high, -- PortB RAM Enable Input - SSRA => low, -- Port A Synchronous Set/Reset Input - SSRB => low, -- Port B Synchronous Set/Reset Input - WEA => memAWriteEnable, -- Port A Write Enable Input - WEB => memBWriteEnable -- Port B Write Enable Input - ); - ZPU_RAM4 : RAMB16_S2_S2 - generic map ( - INIT_A => X"0", -- Value of output RAM registers on Port A at startup - INIT_B => X"0", -- Value of output RAM registers on Port B at startup - SRVAL_A => X"0", -- Port A ouput value upon SSR assertion - SRVAL_B => X"0", -- Port B ouput value upon SSR assertion - WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE - WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE - SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" - INIT_00 => X"02550195000200030077007600030359001E0003001C09DD000307EA00000064", - INIT_01 => X"706555555755A365027600130001222837780003000300030003001600120005", - INIT_02 => X"555709831042087800000000D355555554DA5555555536355555554D5AA46DF7", - INIT_03 => X"5541AA00002A2800AC82A25506A8000000A8A00002A200018329555555559555", - INIT_04 => X"A6956586F8AA55961BE2AAACA89541B85555060D555554AAC001822A2154A895", - INIT_05 => X"15564C3A55961BE2A956586F8A6956586F8AA55961BE29A55961BE2A956586F8", - INIT_06 => X"C4DD0F9C3E254D554C5A94D4A3500F07C1D00B5C330CF3C3F3CC5544DD52494A", - INIT_07 => X"E1B5D755571D97818E76755CE71835646436755036461D5558E13248A5555D99", - INIT_08 => X"DD953042010B03E0024CD486B931E7579D27491D5550765A0D55154409D21B5D", - INIT_09 => X"4424F150D91D3714CDB070020425D4601515551100F8018994D19555114041D5", - INIT_0A => X"75543554959F55D556679190489D554403E0072C4060DE140F41BA11D6E44451", - INIT_0B => X"6845704D611544DC545704D5111C1371144C1DC79E5C71E113697174D0747754", - INIT_0C => X"38344823553107174E413471697193C477905D84C7455344DE19D378574D9313", - INIT_0D => X"55DD48483E1B310505675CCD58860351454104100F441D5552558C3655B95098", - INIT_0E => X"65111AF8DD1AD055541D1D54F08F41D115509285CE0754B47450F82DDB5B6556", - INIT_0F => X"D550499F18E4B076DA4214846A8499649843C3E382555435685D9495496C3106", - INIT_10 => X"4DD55C3555001BD40D9110D5558C3701D5515951951D5114D0D2678221658145", - INIT_11 => X"340D6B9445289AC434711C0F9F15CDD5515951951D5114D0D2678267C4950175", - INIT_12 => X"F40D912D604235CD0D221D444356E005D550D1555381555500D97D875686A420", - INIT_13 => X"80549BE357DF5D553D7DD55A1DD555D557D4336CD746A5475E5D6A216391175A", - INIT_14 => X"010501F5405D40C8D5940C1435580D3849CE5740B18E1910340745C556881D5B", - INIT_15 => X"9B4603E049D9C0084555521555D5710555774D34040D536B8421F9D453441141", - INIT_16 => X"041175106E554455555F9551036500638510F943D169668356285678818E340F", - INIT_17 => X"D8F98F98F98FDD00D920DD6A08440D9103545D563755637555C621AE0505C164", - INIT_18 => X"1157D3918169757BC8590F9710611503950440C103644653210DD555BE179544", - INIT_19 => X"D54C433594B0854455550145755140154527D89514BD8B95754C1CD64F0D1906", - INIT_1A => X"5551405045830F8D75D16D155464110C4D99D918486C8049DD528503667CD750", - INIT_1B => X"A3429553102554C409553102554C409553102554C4095531003C972139044313", - INIT_1C => X"D151519E005111D94414170D204D0484CA4555500503216C59D5301C3526441B", - INIT_1D => X"57046685066556A495D5DD4103D10D51773591C0DE4C83E503570DE4CD6B889D", - INIT_1E => X"1775776F4CCF97A4766261D877D536396DC347407021AA255525558D03E7055D", - INIT_1F => X"30F31DBD15BBDD56706F9BF83648357C6F5D547377B6FD0855545F35776F3A33", - INIT_20 => X"8837575776B0C15859D9843C816FE39A4366411D28401C0D41F3E0FB1D9F4566", - INIT_21 => X"07670D146590C32F1676610FF31267545776B40CCCCFC89D59D5A6E8DC6F2CDF", - INIT_22 => X"CC30300C00300C000C320499A95208E1C4535A2755E92DCB882389238A427556", - INIT_23 => X"000002951C50C080313003030BC02D003400811C50C002CB87E43003F803E300", - INIT_24 => X"5841550C544F955C0740000C380831B1C14C8C00C0C023330030300800D00000", - INIT_25 => X"FFF00C000000F01400FFEAB3C0000000000000003FFFFFFFEAAA9543850823A8", - INIT_26 => X"555555555555555555555555555555500000000000000000000000000000000F", - INIT_27 => X"3A3FFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA5", - INIT_28 => X"00000000000000000000000000000000000000000000B0000000000000020000", - INIT_29 => X"00000000000000000CE000000000000000000000000000000000000000000000", - INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000") - port map ( - DOA => memARead(9 downto 8), -- Port A 2-bit Data Output - DOB => memBRead(9 downto 8), -- Port B 2-bit Data Output - ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input - ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input - CLKA => clk, -- Port A Clock - CLKB => clk, -- Port B Clock - DIA => memAWrite(9 downto 8), -- Port A 2-bit Data Input - DIB => memBWrite(9 downto 8), -- Port B 2-bit Data Input - ENA => re, -- Port A RAM Enable Input - ENB => high, -- PortB RAM Enable Input - SSRA => low, -- Port A Synchronous Set/Reset Input - SSRB => low, -- Port B Synchronous Set/Reset Input - WEA => memAWriteEnable, -- Port A Write Enable Input - WEB => memBWriteEnable -- Port B Write Enable Input - ); - ZPU_RAM5 : RAMB16_S2_S2 - generic map ( - INIT_A => X"0", -- Value of output RAM registers on Port A at startup - INIT_B => X"0", -- Value of output RAM registers on Port B at startup - SRVAL_A => X"0", -- Port A ouput value upon SSR assertion - SRVAL_B => X"0", -- Port B ouput value upon SSR assertion - WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE - WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE - SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" - INIT_00 => X"0028016800040002006B00A40002002500150002001500200002078500620060", - INIT_01 => X"090555555A16501F0555001E00011554543400020002000200020008001C0004", - INIT_02 => X"555A082282D08E55000000009355555555841555555561455555555058510938", - INIT_03 => X"5564320000C598030D3C595590C80000031660000C58C0246FC1555555550555", - INIT_04 => X"12084505C8182114172040DF165564345555903D55555715C0246FC58D571655", - INIT_05 => X"96296A48211417206084505C81A084505C8182114172058211417206084505C8", - INIT_06 => X"E18B5B896D1CD962A7546A5450CF5B71580861C4E138618E91B8586205916041", - INIT_07 => X"17146758A54584656E0B18A04CF16646C1660945661A862854D183703F0F0588", - INIT_08 => X"0582C0F063C156D030459915F861A18480718705961516185996751FBC617146", - INIT_09 => X"378E9CA59823E272012C64BB400C144101558A49B5B4BD50710945615F380059", - INIT_0A => X"1852855419554461645F509EE3462926D6D2F546F1595CCC5B756511B2343155", - INIT_0B => X"B7702AFAD5CB6C8B1702AFAD9C0AB629CBD9C4BA28082E8CBEA02C8E801A1166", - INIT_0C => X"0166AC531C4502C8D941902C80263E735D40066BA5723A8DA8CCBEA322DAFEBE", - INIT_0D => X"A01240416D1107E5A19151016694527B3730C30C5B44061651A15D6601668510", - INIT_0E => X"DA01D4D9861C12585D05065D2811A8519615D0104661940514C5B41453955451", - INIT_0F => X"6168095D15E114149C58BE2F5542950D5956D6D080162966440614694692E3C5", - INIT_10 => X"40628441544996DA5988A599654D643461695D65165D65D45596534A07012D74", - INIT_11 => X"668D5784B55457D16459CA5B8496B061695D65165D65D4559653465304D4BC14", - INIT_12 => X"CA5985D59F72958459207121566453606155996169016161A5985D5559451715", - INIT_13 => X"4D5555D195940616913116116061606165B7295844555A2759A175215B85D555", - INIT_14 => X"70B417352F056B6A715694656668C4C6756858D0D14D121D66E164A05D440611", - INIT_15 => X"80ACD6D20058E080458A141616C58D8595B41041C55991577DC058B25D774D57", - INIT_16 => X"A01F145855A314C58515165132DC89574495B80B0855514715545534054D025B", - INIT_17 => X"17495497495C066598559D45356659889666462941859D185867416D14046975", - INIT_18 => X"99524CDD7720192513505B84634995CA1454710996622409D9C0596565546840", - INIT_19 => X"996DF895A74805A21616894518A86430CC0D5568440545001645484671C4D444", - INIT_1A => X"561B22C94D195B472D1345162807D10000A4582043DF16F464514116627A61A5", - INIT_1B => X"5100966998A59A662966998A59A662966998A59A66296699896E9892E1FC400C", - INIT_1C => X"6545195D1AC85458697806A50148143DF1458A102C00D046646190140D247717", - INIT_1D => X"280F5144451A15D51616D05456C1599118412815927256E196655927215B4460", - INIT_1E => X"11858751486456951621685817855578511641A9DF0165016105845C16E02E06", - INIT_1F => X"35B8051B0CB846294559D7456619664659462A441B75B441C587E5058759A619", - INIT_20 => X"641759587598E0C15454556E8BAA56A5566140865C12B2596B3255B40507C305", - INIT_21 => X"C1632BBD073618665515155B50B647595875948676CA8846106405D4D05DA420", - INIT_22 => X"C030003C40F10C040D284715799040C1155498499FE9FDA30103010304C41658", - INIT_23 => X"0D1036025D60C0F617D18300080422103440125D60C0420B00C4301190424003", - INIT_24 => X"D0456C31905419FC4108000C300999F50245F460C000C14D1830003040D10344", - INIT_25 => X"AAA00C000000002AAA555573EAAAAAAAAAAAAAAA955555555555555407010320", - INIT_26 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA", - INIT_27 => X"003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", - INIT_28 => X"0000000000000000000000000000000000000000000060000000000000020000", - INIT_29 => X"00000000000000000CE000000000000000000000000000000000000000000000", - INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000") - port map ( - DOA => memARead(11 downto 10), -- Port A 2-bit Data Output - DOB => memBRead(11 downto 10), -- Port B 2-bit Data Output - ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input - ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input - CLKA => clk, -- Port A Clock - CLKB => clk, -- Port B Clock - DIA => memAWrite(11 downto 10), -- Port A 2-bit Data Input - DIB => memBWrite(11 downto 10), -- Port B 2-bit Data Input - ENA => re, -- Port A RAM Enable Input - ENB => high, -- PortB RAM Enable Input - SSRA => low, -- Port A Synchronous Set/Reset Input - SSRB => low, -- Port B Synchronous Set/Reset Input - WEA => memAWriteEnable, -- Port A Write Enable Input - WEB => memBWriteEnable -- Port B Write Enable Input - ); - ZPU_RAM6 : RAMB16_S2_S2 - generic map ( - INIT_A => X"0", -- Value of output RAM registers on Port A at startup - INIT_B => X"0", -- Value of output RAM registers on Port B at startup - SRVAL_A => X"0", -- Port A ouput value upon SSR assertion - SRVAL_B => X"0", -- Port B ouput value upon SSR assertion - WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE - WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE - SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" - INIT_00 => X"00000000000000000001000200000000000200000002008800000300000000B0", - INIT_01 => X"202000000800080A010000000000080202B20000000000000000000200000000", - INIT_02 => X"0008A20300A00C02AAAAAAAA0B00000000020000000000000000000002002830", - INIT_03 => X"0000B8AAAAC002AB2CBC000002E2AAAAAB000AAAAC0EEA800FC8000000000000", - INIT_04 => X"84A000A0C2828002830A22CF000000B00000023C00000300EA800FC0EC030000", - INIT_05 => X"000003028002830A0A000A0C284A000A0C2828002830A328002830A0A000A0C2", - INIT_06 => X"3C0003000CA33000040300400B38030004028238020082002600000C8C080000", - INIT_07 => X"8A08CB00028C0A803C31300EA08000208000200800208C0003C8380232828C02", - INIT_08 => X"8C000B04881380C8800F0400B03803020093020C000A30280000202224C0A08C", - INIT_09 => X"003914C000B6C0E02C000003000820C882A00080003200900D800800B802D8C0", - INIT_0A => X"30003002B808C8C004033000800C020000C802409E0608CE03080080A00C0302", - INIT_0B => X"C0D00083034C08010D100830340028034CB3403C3000030420C004DA00322302", - INIT_0C => X"E0002A07384C004DB0C22004D00B6894C2820CAE22D364D8304820C120932820", - INIT_0D => X"00E002C00C811C0028A3282C08228A2400CB2CB203C08C0000002C0008000200", - INIT_0E => X"000E80CACC0B80002A0C0C80280088C20008800A22B32C0E30803220CB808800", - INIT_0F => X"C002283E00C289320830C830042028000200C0C8200000002A8C80000022BC30", - INIT_10 => X"88C0020880BB82C800080000003C02F8C0000C08408008008002032202088038", - INIT_11 => X"022C0B02300202C0000020030A00B8C0000C0840800800800203220B08800010", - INIT_12 => X"C8000A04800A12240020200280022F80C000000001080000200000010020A080", - INIT_13 => X"BE8081C90A260C0010BA8008A8C000C00100A122401000030C0030880F0A0080", - INIT_14 => X"0A00822000040020688002080028208008480200401C8A80002302800C200C08", - INIT_15 => X"00A000C8D8C0C0800000028000E00C20200082082000080B202050200E020802", - INIT_16 => X"000218020C02208000050088F8834C0F2A20300FB400002380C20072201CA803", - INIT_17 => X"00882883881C8CB000200C008880000800028C00230002300003203C81004038", - INIT_18 => X"000008428210320A080A03020820002200880A80000202B92028C00028000022", - INIT_19 => X"00890210803420210000280A30001020B8C8C200000C1800302F82430A2083B2", - INIT_1A => X"0000D0B68823032CC0A208000200000C20A8C0E000830008C800228000B06320", - INIT_1B => X"0820808E8CA023A12808E84A023A12808E84A023A12808E8480C0B8AE0040304", - INIT_1C => X"C808003C8233A0C00C30080800009008320000000B83A00828C0082808800001", - INIT_1D => X"00B00820E0C000A08080022200C6000A322860C0083880C000020083800F2028", - INIT_1E => X"E320230E188022AA300E24C13380203035000332ED0C20800080020E80C03C8C", - INIT_1F => X"70320C8A08388C003602C18800000022028C00363330F3888002A2E0230A2220", - INIT_20 => X"2263020230E1E0880182800C92308AAA0000384C8C202300C23220320C8B8220", - INIT_21 => X"E303800A0100820A0060A003082303020230E18800DAB48C08C8B0E0C80202AA", - INIT_22 => X"4AAA2AA4AAA2AA8AAB2AEEEAE2A12512CFEFA2FAAA8F2AA2C59444944F803000", - INIT_23 => X"A32A8CAAABAAA8EF04892AA3AC4AB02AD0AAC2ABAAA8AB12CF7EAA2B4CA932AA", - INIT_24 => X"AE8EEAAFA8FBFAA8AE94AAAAAC8FABAA8A81224AA8EA305892AA3A8CAAB2A8CA", - INIT_25 => X"00000C000000100000000033C00000000000000000000000000000000A04944E", - INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_27 => X"1500000000000000000000000000000000000000000000000000000000000000", - INIT_28 => X"00000000000000000000000000000000000000000000A0000000000000000000", - INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000", - INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000") - port map ( - DOA => memARead(13 downto 12), -- Port A 2-bit Data Output - DOB => memBRead(13 downto 12), -- Port B 2-bit Data Output - ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input - ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input - CLKA => clk, -- Port A Clock - CLKB => clk, -- Port B Clock - DIA => memAWrite(13 downto 12), -- Port A 2-bit Data Input - DIB => memBWrite(13 downto 12), -- Port B 2-bit Data Input - ENA => re, -- Port A RAM Enable Input - ENB => high, -- PortB RAM Enable Input - SSRA => low, -- Port A Synchronous Set/Reset Input - SSRB => low, -- Port B Synchronous Set/Reset Input - WEA => memAWriteEnable, -- Port A Write Enable Input - WEB => memBWriteEnable -- Port B Write Enable Input - ); - ZPU_RAM7 : RAMB16_S2_S2 - generic map ( - INIT_A => X"0", -- Value of output RAM registers on Port A at startup - INIT_B => X"0", -- Value of output RAM registers on Port B at startup - SRVAL_A => X"0", -- Port A ouput value upon SSR assertion - SRVAL_B => X"0", -- Port B ouput value upon SSR assertion - WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE - WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE - SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" - INIT_00 => X"028200020002000000020081000001800000000000000A4600000320002A00CA", - INIT_01 => X"905000000C800680020000080000444101710000000000000000001100000002", - INIT_02 => X"000C51A6981A9A015555555587000000002140000000081000000006010850B2", - INIT_03 => X"0001745555E001579D7E000005D15555578005555E0DD5410FE400000000A000", - INIT_04 => X"4C521050D1414841434519CF80000172000005BC00000380D5410FE0DC038000", - INIT_05 => X"00800311484143450521050D148521050D1414841434521484143450521050D1", - INIT_06 => X"B21023208C60000808020082040823582DA15A0A0A828A202A0202024C040620", - INIT_07 => X"5454C702054C25583CB23201564080111480B02080B14C8202C4451530504C29", - INIT_08 => X"4C2CD70F843F88C6782C0E40B2442321A663258C008530942000508418C9454C", - INIT_09 => X"90332AA202A8C4867C420A02E68152956550205C02310276425C64087C4124C0", - INIT_0A => X"320900014031E4C8090F7980048C817008C409D4390C4DAD23442049465EBE08", - INIT_0B => X"A6EA40229BAA42128EA40229BA900843AA22A93A69924E9A08A64AA22E319301", - INIT_0C => X"1080551FB198A8AA21E92A8AA64A88A82A6D8C6B22EA88A329A508A694328808", - INIT_0D => X"091921E08C46AC38145316580551649C4024924923E24C8008083C80A4202506", - INIT_0E => X"809103D78C9C4802118C8C50462554C94085486515E31E1D32123198C7831708", - INIT_0F => X"C805903D82C942314421C0700C1514904108C8C518408080114C42002005E000", - INIT_10 => X"64C82514423FC3D4202E1200002C8134C8000C048048048202080B1484546834", - INIT_11 => X"81380F25708102D882181023258074C8000C048048048202080B140BA642AAA2", - INIT_12 => X"D42025987905A11A208844A948010368C80200080368080812025822081080C0", - INIT_13 => X"0D4202C615198C803475408494C808C802D05A11A220C0A30C0830540B258202", - INIT_14 => X"45A24450AAA8001ED44005148016322E0482011A9C2C554C8013056A0C128C84", - INIT_15 => X"267108C424C2CAA22020854080D02C10102165961120040B501AB6060C09A404", - INIT_16 => X"2A80668308085210208B405C3410A90B1512326F49010C17408110F1542C5423", - INIT_17 => X"42102102103D4C6202520C204660202E08014C80932001320243982C52A28031", - INIT_18 => X"800422C160763185560523251E58003082160568080B914B1814C00020820259", - INIT_19 => X"00470222620A101A808054213206208A2193C202621C225A301FD1A305320225", - INIT_1A => X"408028096013231C01580480818028AE6674C292201F5104C60814480A709312", - INIT_1B => X"05A8405D4A5017529405D4A5017529405D4A5017529405D4A48D445D900A2B99", - INIT_1C => X"C421882C5F0098C24E6697488A6D6201F520208A80EBD91434C81A9690E40082", - INIT_1D => X"81700C11108080C14040851988D92005316491C20534C8C808012053440F1254", - INIT_1E => X"1310130866891415309108C2332080B255482315568030580850212D48C9BC4C", - INIT_1F => X"B2358C41A1714C810908C22080848011084C81093370B4E690215110130841A2", - INIT_20 => X"119301013086DA150202108D206544150809068C5E980520407852358C576850", - INIT_21 => X"D30B40018241451440808423460613010130866895E50E4C84C54086C6085545", - INIT_22 => X"4410101440510404051545555151455155455154554145554515451540283001", - INIT_23 => X"0510145455504015151141010144051054405055504040514154101054415101", - INIT_24 => X"5445551554515554415400041401555541454450404051511410101440510144", - INIT_25 => X"55500C000000D00000000033C000000000000000000000000000000005051544", - INIT_26 => X"5555555555555555555555555555555555555555555555555555555555555555", - INIT_27 => X"1515555555555555555555555555555555555555555555555555555555555555", - INIT_28 => X"00000000000000000000000000000000000000000000E0000000000000010000", - INIT_29 => X"00000000000000000CD000000000000000000000000000000000000000000000", - INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000") - port map ( - DOA => memARead(15 downto 14), -- Port A 2-bit Data Output - DOB => memBRead(15 downto 14), -- Port B 2-bit Data Output - ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input - ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input - CLKA => clk, -- Port A Clock - CLKB => clk, -- Port B Clock - DIA => memAWrite(15 downto 14), -- Port A 2-bit Data Input - DIB => memBWrite(15 downto 14), -- Port B 2-bit Data Input - ENA => re, -- Port A RAM Enable Input - ENB => high, -- PortB RAM Enable Input - SSRA => low, -- Port A Synchronous Set/Reset Input - SSRB => low, -- Port B Synchronous Set/Reset Input - WEA => memAWriteEnable, -- Port A Write Enable Input - WEB => memBWriteEnable -- Port B Write Enable Input - ); - ZPU_RAM8 : RAMB16_S2_S2 - generic map ( - INIT_A => X"0", -- Value of output RAM registers on Port A at startup - INIT_B => X"0", -- Value of output RAM registers on Port B at startup - SRVAL_A => X"0", -- Port A ouput value upon SSR assertion - SRVAL_B => X"0", -- Port B ouput value upon SSR assertion - WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE - WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE - SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" - INIT_00 => X"015502550005000300F6005200030357002A0003002A066500030BDD001C000F", - INIT_01 => X"793000000D4EC7C70123002F0001191522250003000300030003003D00060009", - INIT_02 => X"000D601010C040A555555554DA00000001DCC000000077600000001645953DFD", - INIT_03 => X"0024C9555693855A7CB92A00932555555A4E15556932D564899E00000000A000", - INIT_04 => X"5D961BE2A956586F8AA567064E0024F0000093A4000002405564CB932C024A80", - INIT_05 => X"5D510E56586F8AA55961BE2A955961BE2A956586F8AA566586F8AA55961BE2A9", - INIT_06 => X"A2CD6E8D995445D50415505D54486DAC86F2014401004100D90F76420F951317", - INIT_07 => X"1510D0756C0F85016A08356D69D1AE7545BE09D1BE090D551595211564540F86", - INIT_08 => X"0F805644C511DB9595044165E874C364C783450F96543E146F9B074370D9510D", - INIT_09 => X"D0059716B8C5137DC0372001534D13641227546416A51443126409D9590120F9", - INIT_0A => X"36560854A95A40D9CF52944C950D51909A94912C5C5517E569C5555639E4D274", - INIT_0B => X"1C5D34787171C74DC5D34787174D1531714974D1874D34571E113716083403E4", - INIT_0C => X"11BC45059E74587172579D87113C5A54D9100D71F15C56148574D215D3785A1E", - INIT_0D => X"57101951A951691C0443C079D85206791520820865500D917555498E15555D43", - INIT_0E => X"5643D4020DC94C76460F0D54FD2FB0F89D9E0713B48365143E566570FDD56475", - INIT_0F => X"D9515D4955A1203DB50398E455555344471A9996A41D51BE6B0D1D51D5B6B105", - INIT_10 => X"10D5514C5D3FD4116B8D1639C1459E40D9C401D0DD3DD2DD36BE5659440CD400", - INIT_11 => X"9F7C5E85475555A1AF08416284DD00D9F401D01D31D21D36BE56595B07104410", - INIT_12 => X"016B86C4001110346B344830DAE76470D916F1D9C089D9C816783811755571F1", - INIT_13 => X"905DD595B4040D9C0A341D9FD0D9C0D98D1111034FC55553757DD5545E865D17", - INIT_14 => X"11907484261415500C0179A5BE6373A31C467445C5596D8D8C03C3F0755C0D9D", - INIT_15 => X"83E4589420F845D51755749D9C37408777410410826F9657E7434002771C0034", - INIT_16 => X"354053475556521764441D2BC0A4815E5456A851083F555955557525B559536A", - INIT_17 => X"951951D5114D0D2678263DD55BD1678D58E60D5903659436431C1549535241DD", - INIT_18 => X"44003B04E4403403010B6681900440719D0110345BE343C85440F9715CDD5515", - INIT_19 => X"7986431374C5975D9D99B9D835502D49FC805555310551403E56034C107395E0", - INIT_1A => X"9D9120C85C8066553413241D5C5014B168B0F8D350CD1D40D275549BE1100366", - INIT_1B => X"54B49D071CE741C739D071CE741C739D071C2741C739D071CD815C8654051858", - INIT_1C => X"D1D145596B4080F8C1518D8456E6310CD53754060C2C353430D91D85BC110115", - INIT_1D => X"5264555525557571DDDD84001BD76B9437189636B0241BA01AE46B024D525D40", - INIT_1E => X"0377485474C5E3903E3400F03FC755E86D59C3478B415575D96767055BA26C0D", - INIT_1F => X"E6A10F207A310D5D0455154D8E21AE7F540D550437D5EC0C6767EA6748574D31", - INIT_20 => X"EF2D7675C576C499D515DDAD233DBA2F18E0360D814C1E67410C66A10FB31265", - INIT_21 => X"03E10116505841CC7565776BFB332B767485444C49EF430D90DD1554E856A57E", - INIT_22 => X"060010B042F18004022C024D1C0C8C024C88055CCD9726B03330313015D43E70", - INIT_23 => X"2E10B94C860800712F77200103040C105040C086080040C8029A0013B84AE10B", - INIT_24 => X"7D02A0C02689FCD84294002EC00712EB68CBDDC80042C2F7720010B040210B84", - INIT_25 => X"00008C00000000000000003CC0000000000000003FFFFFFFEAAA954349323032", - INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_28 => X"0000000000000000000000000000000000000000000C20000000000000000000", - INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000", - INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000") - port map ( - DOA => memARead(17 downto 16), -- Port A 2-bit Data Output - DOB => memBRead(17 downto 16), -- Port B 2-bit Data Output - ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input - ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input - CLKA => clk, -- Port A Clock - CLKB => clk, -- Port B Clock - DIA => memAWrite(17 downto 16), -- Port A 2-bit Data Input - DIB => memBWrite(17 downto 16), -- Port B 2-bit Data Input - ENA => re, -- Port A RAM Enable Input - ENB => high, -- PortB RAM Enable Input - SSRA => low, -- Port A Synchronous Set/Reset Input - SSRB => low, -- Port B Synchronous Set/Reset Input - WEA => memAWriteEnable, -- Port A Write Enable Input - WEB => memBWriteEnable -- Port B Write Enable Input - ); - ZPU_RAM9 : RAMB16_S2_S2 - generic map ( - INIT_A => X"0", -- Value of output RAM registers on Port A at startup - INIT_B => X"0", -- Value of output RAM registers on Port B at startup - SRVAL_A => X"0", -- Port A ouput value upon SSR assertion - SRVAL_B => X"0", -- Port B ouput value upon SSR assertion - WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE - WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE - SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" - INIT_00 => X"009600160000000600E4009200060557000C0006000C02960006039300FA003A", - INIT_01 => X"B5D000000581E4BC081000060000110A155A0006000600060006004200740002", - INIT_02 => X"000959D19C274612555555558600000001AD000000006B60000000120541D009", - INIT_03 => X"00176555560F45581050E6005D955555583D155560F955579000000000002000", - INIT_04 => X"811417206084505C818201B03D00174C00005DC0000000331557D00F94003980", - INIT_05 => X"05904844505C8182114172060811417206084505C818204505C8182114172060", - INIT_06 => X"00B95D4956847059025610062B41597E299E04403812086A800816305B801AB3", - INIT_07 => X"16159116405B452D7501664AC09D5E01854D00657D01599654685565C7F75B44", - INIT_08 => X"5B405444511054691C433355D45496618696555B86456D155784919B25916159", - INIT_09 => X"970A02C57472B208C4E68B5073F10827B8D166E7551A574890E7B45841D905B8", - INIT_0A => X"6608B8000D640598E4514E75D5599B9D54695D15555904C55955628C08C3901A", - INIT_0B => X"C00B65A3002C1BE880B25A3002E96FA02CB02E9C30CB670268CB22CAE16696E1", - INIT_0C => X"356F85644232302C85304B02CBE7201284D6591C100B20C8302FA0CCBEB32C68", - INIT_0D => X"5A1BF03D468501103796DC24564AC421C50C30C3550C59841859454D1161632D", - INIT_0E => X"85D4D448590820161C5B595667C5A5B00581FCE8121643C16C95DA45B0D65418", - INIT_0F => X"985951471451596F6CB8120458A153154515546A2F45996E0059061061011525", - INIT_10 => X"659969F546555451534615B81D455DA5981400574554574665B551AAF5F542E5", - INIT_11 => X"6E55514D618A545D4CF26151450565984400574554574665B151AA555CD50306", - INIT_12 => X"615B4500879C03135F4F516357E04A6598053058E04058E495F4D4C818A5A16D", - INIT_13 => X"2B06D5689712598E0D3485815598E5986439C031312585AA184862965D454615", - INIT_14 => X"5C56557980C2D511356D69554E245A019110147CD1668D555F16CD6E18AD5981", - INIT_15 => X"4547156A05B44C709165B5058C4155014151861854578151255C0A1E1890E155", - INIT_16 => X"2C2148055859485162900507A804095DA5159403033C58A4458A051A45469451", - INIT_17 => X"D65165D65D4559653465B062850D534657E159901662056619D03156BAC41061", - INIT_18 => X"B40CA027558966CDB0B5594581EB405406459A4355D1A9405265B84963061695", - INIT_19 => X"B88C400052E3616445894869665813035A621616A3C160716E0031309D5A160E", - INIT_1A => X"85810003DF1055A137F7C24592C0B0534655B4753E2568459918A017D1809655", - INIT_1B => X"2ABF45A916115A458456916115A458456916D15A4584569161554844B32CD4D2", - INIT_1C => X"90665146A34835B4405B2243F45997E25841667C00140D3415982F3F5F100D16", - INIT_1D => X"914458A14585B58D0505057316525381649A743537DD175394E25B7DD251A445", - INIT_1E => X"564156596A42E5216D10D5B16F1195145157D6798BF562805801602E55501859", - INIT_1F => X"55955BA2D8F159910159565D4D217E105A5995016785D8328160E61156594E90", - INIT_20 => X"ED891416A5952D91D6561D652197FA6617D2065983117557579455155B50B645", - INIT_21 => X"96D1C15CCF5965D07595875966192514156597A438065D59859925A5D55A7182", - INIT_22 => X"86601098427198040F00102D2065F4638C0066147C25890194D197D1A48D6E32", - INIT_23 => X"2F10BD01DBE980D133F4660103040C10F04001DBE98040CF435E60123048C109", - INIT_24 => X"41CC71F0461277C043200020184454DCA90C7D198042D31F466010B440F10BC4", - INIT_25 => X"00000C00000000000000003CEAAAAAAAAAAAAAAA95555555555555540D14D180", - INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_28 => X"0000000000000000000000000000000000000000000B70000000000000000000", - INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000", - INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000") - port map ( - DOA => memARead(19 downto 18), -- Port A 2-bit Data Output - DOB => memBRead(19 downto 18), -- Port B 2-bit Data Output - ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input - ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input - CLKA => clk, -- Port A Clock - CLKB => clk, -- Port B Clock - DIA => memAWrite(19 downto 18), -- Port A 2-bit Data Input - DIB => memBWrite(19 downto 18), -- Port B 2-bit Data Input - ENA => re, -- Port A RAM Enable Input - ENB => high, -- PortB RAM Enable Input - SSRA => low, -- Port A Synchronous Set/Reset Input - SSRB => low, -- Port B Synchronous Set/Reset Input - WEA => memAWriteEnable, -- Port A Write Enable Input - WEB => memBWriteEnable -- Port B Write Enable Input - ); - ZPU_RAM10 : RAMB16_S2_S2 - generic map ( - INIT_A => X"0", -- Value of output RAM registers on Port A at startup - INIT_B => X"0", -- Value of output RAM registers on Port B at startup - SRVAL_A => X"0", -- Port A ouput value upon SSR assertion - SRVAL_B => X"0", -- Port B ouput value upon SSR assertion - WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE - WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE - SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" - INIT_00 => X"00000000000200000042000800000003000A0000000A00000000038300200000", - INIT_01 => X"300AAAAAA020C232008800040000088008000000000000000000000800020000", - INIT_02 => X"AAA00002000008000000000000AAAAAAA8042AAAAAAA010AAAAAAA8020080088", - INIT_03 => X"AA800000008F00020208C0AA00000000023C000008F00000088CAAAAAAAA0AAA", - INIT_04 => X"0002830A0A000A0C282820323C2A800CAAAA00E2AAAAAA330000C88F02AA302A", - INIT_05 => X"8C0800000A0C2828002830A0A0002830A0A000A0C2828000A0C2828002830A0A", - INIT_06 => X"00300020200000C0A1000A0C000002088CA200005C130CB400003000030080C3", - INIT_07 => X"020002302E0320083088002282802C00880C88C83C880000C000083000800320", - INIT_08 => X"0322C80CE030C20033203A80C2CB0000E00022030A800C830F0A2321A0082000", - INIT_09 => X"020C00407253203845C00010EF0EF6002003008C60406000008C08C000200030", - INIT_0A => X"000003AAA80820008C020809000002318101802138028CC00E20000838403030", - INIT_0B => X"4202C0C108040C8010241C108090720804C0093413A20D00B042004C0C0000C0", - INIT_0C => X"802D008C8E130004D020800042893401283000252C01344D1008344020C13030", - INIT_0D => X"008A4000100000328380C228C82C20A028000000063200023000082C800000C0", - INIT_0E => X"02A8408800BCD830040300828028A0328C009022AA0000000EA0800030C08030", - INIT_0F => X"00A0000A0008280C031A0E8000000B8020C18000808C083C0A000C08C0A20800", - INIT_10 => X"000000808C9540880F24C0F0A0183C8000A2A0C78C78C68C90B000080080A800", - INIT_11 => X"0C100020230080883C080804208C8000A2A0C78C78C68C90B00008020822A882", - INIT_12 => X"880720A2880288820F00008800C0A800008070C0C0A8C0C140320BE030002868", - INIT_13 => X"A00C000080A0000C0A120C004000C000880028882000002E3028C0000C208C00", - INIT_14 => X"02A03008AA200022008010800C001222002A3008243000041C40D082300C0002", - INIT_15 => X"20808202003208CF6300308C0EA32823032C208220030202210210BA32028B30", - INIT_16 => X"08D080B10000B62300200C028200260C0080C20B80FF0000000030003800020C", - INIT_17 => X"C084080080080020322030C02A200B2401C0000880028000200AA000258210C8", - INIT_18 => X"82A22200A08000200A0A0820C2282A1A8CA0000800C90280080030A00B8C0000", - INIT_19 => X"7038030C21E023288C0238C80023663238A100000C2002080C000822021200A2", - INIT_1A => X"8C0C088083000C003020CD8C08382EA2083032C0008420000A3000C0C8000020", - INIT_1B => X"00F08C08A0A3022828C08A0A3022828C08A023022828C08A08280A2C0D0B6882", - INIT_1C => X"00C800000108003200820121208428084F63002088280880B000FC0A230B8800", - INIT_1D => X"088000002000300C8C0CB208838A0300000AA21072EA030B82C00F2EA2000820", - INIT_1E => X"802328022802E2A80C8AE0300F2320023A02C0294F080038C023003C03080E00", - INIT_1F => X"206003248E340008E002008C3C903C08020008E00380E000E30008A328021E00", - INIT_20 => X"ECAA3232802208C0C0808C386200BAA2C3C8E20012002B0B0281206003082300", - INIT_21 => X"00C82C04338C00893020230E2220EA32328022800A22AC00000AA020E00200AA", - INIT_22 => X"8BAA2AC8AB22EA8AAA3AAAABAEF12242EAEEFAAAEAEAB9EB858904893FB00C38", - INIT_23 => X"B62ADAAFAAAEA88604013AA2AD8AB62AA8AAA3AAAEA8AB6ECAA3AA299CAE72AC", - INIT_24 => X"FA8BABAAF8BEAEACBAC0AABBF88B3FAB8FC1804EA8AB706013AA2ADCAA22AD8A", - INIT_25 => X"00000C00000000000000003CC00000000000000000000000000000000B05893B", - INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_28 => X"00000000000000000000000000000000000000000002C0000000000000000000", - INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000", - INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000") - port map ( - DOA => memARead(21 downto 20), -- Port A 2-bit Data Output - DOB => memBRead(21 downto 20), -- Port B 2-bit Data Output - ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input - ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input - CLKA => clk, -- Port A Clock - CLKB => clk, -- Port B Clock - DIA => memAWrite(21 downto 20), -- Port A 2-bit Data Input - DIB => memBWrite(21 downto 20), -- Port B 2-bit Data Input - ENA => re, -- Port A RAM Enable Input - ENB => high, -- PortB RAM Enable Input - SSRA => low, -- Port A Synchronous Set/Reset Input - SSRB => low, -- Port B Synchronous Set/Reset Input - WEA => memAWriteEnable, -- Port A Write Enable Input - WEB => memBWriteEnable -- Port B Write Enable Input - ); - ZPU_RAM11 : RAMB16_S2_S2 - generic map ( - INIT_A => X"0", -- Value of output RAM registers on Port A at startup - INIT_B => X"0", -- Value of output RAM registers on Port B at startup - SRVAL_A => X"0", -- Port A ouput value upon SSR assertion - SRVAL_B => X"0", -- Port B ouput value upon SSR assertion - WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE - WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE - SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" - INIT_00 => X"010002800005000000C1008400000003002100000021040000000B0B00000080", - INIT_01 => X"300555555818C13E024600280002446044400000000000000000001400210008", - INIT_02 => X"5558001502C05488000000002055555554085555555502055555554490240A60", - INIT_03 => X"55400000005F20014925C05500000000017C800005F080001652555555554555", - INIT_04 => X"284143450521050D141494397C95402E555500D95555557B8000D65F09557015", - INIT_05 => X"4C06A011050D1414841434505284143450521050D1414A1050D1414841434505", - INIT_06 => X"08300810202228C05A80858C82220C544955A62AAEABAEBA2AA230A8232640C7", - INIT_07 => X"81820930112311843064801515403C98683C64CC3C642000820254B002222311", - INIT_08 => X"2319C42EE8BAC200709BF860C11608091088112325648C440F25531652041820", - INIT_09 => X"0AAA64A0B1AA88B6AE80A0F9CB0D89600123002ED080D0A1082E04C2601C8232", - INIT_0A => X"80B1F855540592024B086067802000BB42034297B9016AC008640821B6A83830", - INIT_0B => X"A590C3A6964A7A3129083A696430E8864AA6423AE830CEA4A9A084AA0C8048C8", - INIT_0C => X"402E609E6DA6824AA1855024A08AA99B160820AA6292A9AA6A4229A908A6A9E9", - INIT_0D => X"0155C680202440B64308D144C55D125014820820088920293200203C44080420", - INIT_0E => X"21158224204A263099232052441402364C257115550828288DD0801236C05232", - INIT_0F => X"025008204204448D20BD0F420204075350030300404C042C95208C84C8591480", - INIT_10 => X"120000824C6A82140F18C0B258202D42025358CF4CF4CF4C70F6080202425682", - INIT_11 => X"2D2E0814132042102D960C0C114C42025358CF4CF4CF4C70F608020811195469", - INIT_12 => X"140F1159658164C80B60264402C9144202E0B8C2CA74C2C6C0F140DA32001498", - INIT_13 => X"508C820240D8202CA5A58C268202C2024698164C8BB0201D3214C8120C114C82", - INIT_14 => X"41582246551A8099826834902C91209986B53201DC3018282FC8F041320C2024", - INIT_15 => X"14404302823121C09300314C2D531653231C1041590B25085301B0E5318547A2", - INIT_16 => X"812A614202024993081A8C9343921D0C01408167603C02062020808004200508", - INIT_17 => X"C048048048202080B140B8C815580B1803C9200648096080914544201F19B8C4", - INIT_18 => X"635309A05A60803045A50814A916352D4C51801602C6196216023258074C8000", - INIT_19 => X"B2642B997AD453154C2904C48011F864F8BA80800C1809048C988C8B81208071", - INIT_1A => X"4C2886A01F5A0808B007D24C040A0258047231C180889E2205320603C46A4810", - INIT_1B => X"80704C945513251544C945513251544C945513251544C9455031215D42809601", - INIT_1C => X"08C528201A2E02316950461B05582C08889300706A9690E6B2029C005E94E8C0", - INIT_1D => X"044202085020302C4C8C718442140B248247C1B0F4D18206C3C90B4D15080612", - INIT_1E => X"4813140150A9C5588C5692388F9310815542C81567040804C25309BC02058D20", - INIT_1F => X"80842348197820041901405C3C782C95012004188320C6849309555314016C2A", - INIT_20 => X"CC55313140158184C0404C219A25715003C510202846A50F6A46008423460610", - INIT_21 => X"08C41C890A4D24963010130841A215313140150A91905D2022045012D6015414", - INIT_22 => X"4050001400501400051411551455445144445554554505515511551140808CB4", - INIT_23 => X"0500154555414015155545000500140050004155414001414154500154015001", - INIT_24 => X"5545515054551554015400055445555541451551400051455450001400500140", - INIT_25 => X"00000C00000000000000003CC000000000000000000000000000000001151151", - INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_28 => X"0000000000000000000000000000000000000000000300000000000000000000", - INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000", - INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000") - port map ( - DOA => memARead(23 downto 22), -- Port A 2-bit Data Output - DOB => memBRead(23 downto 22), -- Port B 2-bit Data Output - ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input - ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input - CLKA => clk, -- Port A Clock - CLKB => clk, -- Port B Clock - DIA => memAWrite(23 downto 22), -- Port A 2-bit Data Input - DIB => memBWrite(23 downto 22), -- Port B 2-bit Data Input - ENA => re, -- Port A RAM Enable Input - ENB => high, -- PortB RAM Enable Input - SSRA => low, -- Port A Synchronous Set/Reset Input - SSRB => low, -- Port B Synchronous Set/Reset Input - WEA => memAWriteEnable, -- Port A Write Enable Input - WEB => memBWriteEnable -- Port B Write Enable Input - ); - ZPU_RAM12 : RAMB16_S2_S2 - generic map ( - INIT_A => X"0", -- Value of output RAM registers on Port A at startup - INIT_B => X"0", -- Value of output RAM registers on Port B at startup - SRVAL_A => X"0", -- Port A ouput value upon SSR assertion - SRVAL_B => X"0", -- Port B ouput value upon SSR assertion - WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE - WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE - SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" - INIT_00 => X"039A019A000D000B001200DA0007023A001E000F001E0FDA000F0BD9003C00CC", - INIT_01 => X"B69555554C5750DF077600150001D65619160003000B0003000B007E00620009", - INIT_02 => X"554C39042084105A00000001DD55555555D955555555769555555565615EB5BE", - INIT_03 => X"554AAC0000192000620183552AB000000064800001B8800A0819555555549555", - INIT_04 => X"686F8AA55961BE2A9565862064954A8855552A255555506A800A481B855060D5", - INIT_05 => X"0F947491BE2A956586F8AA559686F8AA55961BE2A9565A1BE2A956586F8AA559", - INIT_06 => X"55E4555D553130F9471D940D531356044986430CC330E31F333C3E346A848391", - INIT_07 => X"35D6B03E5162555DD551BE454D416A32594950D1695D6F969D55D0B050106257", - INIT_08 => X"6A55650674135555948D2557551899E1D319DC6686C599575286C34146735D6B", - INIT_09 => X"0B511375E55C5CCB20300054564209022543E5E74557415004E410F8141746E8", - INIT_0A => X"AE0A5E5545D396F84475FC1100639791155105719777D7445735D550CB8C5434", - INIT_0B => X"704D5111C1371164C4DA119C13584551371134971C79E5D3C571D371018C5BA1", - INIT_0C => X"994753E402D391371FF80D1371A5C46D51346795104DC671DD378774DE15C546", - INIT_0D => X"5B5A9011555CD497541A5760FB60D8541C4D34D354C86B843665D9495DD99522", - INIT_0E => X"64695D546782203E03646F924107E6D50F86A6360919C905A7E55556E49D9436", - INIT_0F => X"B8440DDE1D5511B9048D4B53755C343160951559A40F957A056F0D90D94114C7", - INIT_10 => X"D679D4140D155DD85255D5E851D14116B87360F80F80F00D0537757F43D40796", - INIT_11 => X"7410755803559DF9600C1C55540FD6387360F80F80F00D0534757C75D144000D", - INIT_12 => X"D8525415078455CE5804350557A1910638D530F845D0F840E5651B0C35474055", - INIT_13 => X"450D5D5551C06F8451150F8B46F8467840C8455CEC0766083640D5A775540D9D", - INIT_14 => X"C435C39600054001D41427915A29110183343D0001D5B8055FDAF500354C6B86", - INIT_15 => X"5E50155F46A5765083E7050F8583D043C3C4D34D43568A75400001C83704D943", - INIT_16 => X"092310E176738BC3E0850F1317C143755645556B5856754057556754DDD55B55", - INIT_17 => X"1D05D35D25D36BE56595F0D52318565417A1679C5AE171AE108065D5B81070DC", - INIT_18 => X"137710413751AC75D19455584241371D0D284586159535150C16284DD40D9740", - INIT_19 => X"68B51C594F5503C60F85C0DDBE728B201C6CDD960905D341AA04DCE847119D04", - INIT_1A => X"0F8C5FD0CDD555441033720F9048321F20C6655390C4D1167C355C5495C159F5", - INIT_1B => X"54650F25F943C97E50F25F943C97E50F25F943C97E50F25F99553100D20C86C8", - INIT_1C => X"B0D3CDD5C10D16651A0001CA4C27190C4C83E467FD85FC2686B8D90E8F841C1D", - INIT_1D => X"9B517557476727680F0FB03495F05689BECE30C59D995556D6A05DD991756036", - INIT_1E => X"9AC3CC76F058CBDDA96706F9BF837755E8D719DE3645D500F8C3E26C15549C6B", - INIT_1F => X"75776F40CEB46F9098761DF5694D6A1D776B9C198FF7418483E18F83EC767C15", - INIT_20 => X"CF6C3C3EC76E0CC7DD9D71515318703B9794416707741951E1AF35776F3A3327", - INIT_21 => X"1995184149CDC7DFA76748564D310C3C3CC76F45BAFA416F86F01755E5775604", - INIT_22 => X"C13000BC02E04C002D999D80225BDDC38B0652041E3E0C672F772F7700859A10", - INIT_23 => X"3900D6125104C0BE1369130006001000D000C25104C001872DE13009E407500B", - INIT_24 => X"9B24DA1D155701E2091800057049300F44449A44C003B116913000DC02D00F40", - INIT_25 => X"00000C00000000000000003F00000000000000003FFFFFFFEAAA954314EF7729", - INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_28 => X"00000000000000000000000000000000000000000002B0000000000000000000", - INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000", - INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", - 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SRVAL_A => X"0", -- Port A ouput value upon SSR assertion - SRVAL_B => X"0", -- Port B ouput value upon SSR assertion - WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE - WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE - SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" - INIT_00 => X"048000800000000200D00184000A017000000002000011200002000000180188", - INIT_01 => X"7C5555555854138606440000000108641104000E0006000A0002005000C00000", - INIT_02 => X"5558042D08A0B41A00000001AD555555549155555555E41555555541A0206648", - INIT_03 => X"55715C000240F00919240F55C57000000903C000243480300640555555555555", - INIT_04 => X"405C8182114172060845114903D571635555C5955555590C80300643455903D5", - INIT_05 => X"5B801D017206084505C818211405C8182114172060845017206084505C818211", - INIT_06 => X"CF9158A961AC95B82D05825991BD5A818146BA784E178E05EE196D1F5140921C", - INIT_07 => X"B005756E115DA14862955E25811175003146959146905384061691264ACA55A0", - INIT_08 => X"59A42C80120D1614043907018A5255D15255DD5D458556865145564855BB005F", - INIT_09 => X"01CCB2259A0B2392C28EB25C2C44439D7556E1C065846DC42FC145B4B017F5D4", - INIT_0A => X"5D045055085455F440192D596B5B87059615B7094314F0445810596FD2990D67", - INIT_0B => X"2AFAD9C0AB629CBFAFADDC0ABEB572DBE2CBEB0208A280BA712A3A2C017F5451", - INIT_0C => X"11556380E4B31F22CC8459F22A00B2C9AD2F53440AC8B22C8BAA332CA8CCB170", - INIT_0D => X"20521D116161320750D75445BA63043113F3CF3C5A8353456600614680580100", - INIT_0E => X"61C0465D5B55056D2C59536A410615565B4484160756D1354445850590451166", - INIT_0F => X"34540464C6282165840F2FC01644185361165611845B8175155F598598574301", - INIT_10 => X"95B81610590006D555A145D454614515B44D55B85B05B059451518414910F155", - INIT_11 => X"754218A4566586A15676D758A25B95745945B85B05B05945151841195403B8C5", - INIT_12 => X"D551A2D57526556851549CC515512185746555B44C55B454651AD2896651552D", - INIT_13 => X"8559861581715344E5155B4405F4557449226556808162B96615991018A25946", - INIT_14 => X"26810900EE302D971042C7156514441D7E116C47006114D165575485665C5744", - INIT_15 => X"A0C05611F51A011016E3015B4416DC56D6D50410605144194847857167575649", - INIT_16 => X"8501D75816390056D02C5B13154B001851558A06B000164401658184C0614458", - INIT_17 => X"0574554574665B151AA515999DD755A194515B8256D1855D195248612057559C", - INIT_18 => X"294541ADD1C95F545C0658A6DD729444592D35B5D46841BCF6D5145056598440", - INIT_19 => X"149C18D3853DD6ED5B46C5954E2306988017058001305075452D168064440507", - INIT_1A => X"5B45DE3E255C5866C889405B844000F7C4859A19500318D5F56654D4686755D5", - INIT_1B => X"94C55B661556D98555B661556D98555B661556D98555B6615966998090003DF1", - INIT_1C => X"3592E46160BFE5DAB10482E8425701001416E005E33F6F15057471E127141505", - INIT_1D => X"80C9165B516301415B5B0701161251457D340D55D4531628D7525D4509184AA5", - INIT_1E => X"16D6E0146835CA997694559D7456518A815556F59C405905B416D01856291657", - INIT_1F => X"8587514864C4538C5A1605E146B57504145784994C01A31416D14956D0141E0C", - INIT_20 => X"CD516D6D0145C6464505A965E90EB3E9566B0C5F1536A2596A25058759A61921", - INIT_21 => X"5468563D4019C7D5514156594E90616D6E0146C37529415345B4115925148658", - INIT_22 => X"01C0003000C07000268DD053D75C7D13203354162007003471F473F46485451C", - INIT_23 => X"020009137507003F200E1C000C003400D00003750700030D29C1C00BC00F0003", - INIT_24 => X"CC244C4D1D8522020A340015444E300FD448038700000200E1C0000002D00080", - INIT_25 => X"00000C00000000000000003F2AAAAAAAAAAAAAAA95555555555555541931F475", - INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_28 => X"0000000000000000000000000000000000000000000300000000000000000000", - INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000", - INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000") - port map ( - DOA => memARead(27 downto 26), -- Port A 2-bit Data Output - DOB => memBRead(27 downto 26), -- Port B 2-bit Data Output - ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input - ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input - CLKA => clk, -- Port A Clock - CLKB => clk, -- Port B Clock - DIA => memAWrite(27 downto 26), -- Port A 2-bit Data Input - DIB => memBWrite(27 downto 26), -- Port B 2-bit Data Input - ENA => re, -- Port A RAM Enable Input - ENB => high, -- PortB RAM Enable Input - SSRA => low, -- Port A Synchronous Set/Reset Input - SSRB => low, -- Port B Synchronous Set/Reset Input - WEA => memAWriteEnable, -- Port A Write Enable Input - WEB => memBWriteEnable -- Port B Write Enable Input - ); - ZPU_RAM14 : RAMB16_S2_S2 - generic map ( - INIT_A => X"0", -- Value of output RAM registers on Port A at startup - INIT_B => X"0", -- Value of output RAM registers on Port B at startup - SRVAL_A => X"0", -- Port A ouput value upon SSR assertion - SRVAL_B => X"0", -- Port B ouput value upon SSR assertion - WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE - WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE - SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" - INIT_00 => X"000A000A00020008000A0002000400B2000A0008000A008A000C000A00100010", - INIT_01 => X"3C00000002000B2100020000000000020882000C000800000004000A00060002", - INIT_02 => X"0002800A00C02800AAAAAAA80400000003080000000042000000000008082020", - INIT_03 => X"00300EAAA808FAA00C008F00C03AAAAAA023EAAA80B02AB22008000000000000", - INIT_04 => X"2A0C2828002830A0A000802023C0303B0000C0000000002E2AB2200B000023C0", - INIT_05 => X"0302A00830A0A000A0C2828002A0C2828002830A0A000A830A0A000A0C282800", - INIT_06 => X"322C0000000F2030098C00000AC20218800000408020003A00A00C9008220000", - INIT_07 => X"3000B00C08080028C0002C008CC030B82000000000000B0A0C00001031310403", - INIT_08 => X"080003203C800000000302230088C3CB2C00CF0420E030020020000200F3000F", - INIT_09 => X"0284200000013410000200FB000402024000C082C002C087A08260320D0F0002", - INIT_0A => X"1C88F20068CB00320032CA23C00F020B000B0203C230201A00B0C00610320001", - INIT_0B => X"00830340024034CA0830340020C0D302C0420C0001C30028D0036C04002D0108", - INIT_0C => X"CC390F8224230200473B002007401083A38D0B0080801204828C120B304810D1", - INIT_0D => X"2B020380000CCE810202820030002ACC0B082082000003200008C80000C02802", - INIT_0E => X"004C8C800F22000C8E0E072BB02AA0A003228022B000F80018400000228C0000", - INIT_0F => X"7202A8CC8C002008E004CD363022A22F0A808008200300308807000000200D83", - INIT_10 => X"4070A00200000C00000240C208C0188072012030030030004022302201020A80", - INIT_11 => X"3802300200028CA00A8A040000030032012030030030004022302232C0A80B28", - INIT_12 => X"000000000880004802201A200008A820F24020320800321260002A2000232800", - INIT_13 => X"A0008C000C4A0B208080032230B210720008000488830208000000823000008C", - INIT_14 => X"0008812A02CA808202280340308C0A8280900FC200C08BE03940902800240B22", - INIT_15 => X"0234800B00400A0000C3A0032000C200C0C820820A0022322904885000800281", - INIT_16 => X"2209082030310040C888038181680230000000030082302223002302E8C00200", - INIT_17 => X"0C78C78C68C90B0000802000A02800020008070001C8203C880808C0A0281003", - INIT_18 => X"A121A82029842D1002A00002420A1204002880CA000088080A004208C8000A2A", - INIT_19 => X"0233E882882000C80320E0080C0E0A284C208C024008C0AC10800488800A8C00", - INIT_1A => X"032E0CC0840800023421000303022020C080C00080C20BA070002200000E03C0", - INIT_1B => X"0B000302E000C0B800302E000C0B800302E000C0B800302E0808E84000880830", - INIT_1C => X"B002E8C088442000220300C83023800C1400C300CC0A33000032C00B0700280C", - INIT_1D => X"003630032303A32803032088808800201CC82C30E08A000243080E0882302220", - INIT_1E => X"82C0C8322820D2881003602C1880230035C081C88008C0A032C0C80E00000C0B", - INIT_1F => X"20230E18800B030389304CE000303088320703880C23280000C88880C8322E08", - INIT_20 => X"DE080C0C8320883A8C8CA008A00036AA8300AE0F0221300E1312E0230A2220E3", - INIT_21 => X"03000BCE003CC3C2A32328021E00880C0C83228208AAA00720B0E32A223212A9", - INIT_22 => X"0ABA2A90AA42AE8AB02AAEFA8AC18042EFAACFBAAB4AAEAB060104013F402082", - INIT_23 => X"AC2AB3AAAEEAE8940911ABA2AB8AAE2AB8AAE2AEEAE8AAE84B2ABA2DB0A6C2A9", - INIT_24 => X"AB4EAAEAB2AAAAB4BA84AAAAB08BAAAA2A42C46AE8AAD0B11ABA2AB4AB42AB0A", - INIT_25 => X"00000C00000000000000003F000000000000000000000000000000002E06012A", - INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_28 => X"0000000000000000000000000000000000000000000170000000000000000000", - INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000", - INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000") - port map ( - DOA => memARead(29 downto 28), -- Port A 2-bit Data Output - DOB => memBRead(29 downto 28), -- Port B 2-bit Data Output - ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input - ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input - CLKA => clk, -- Port A Clock - CLKB => clk, -- Port B Clock - DIA => memAWrite(29 downto 28), -- Port A 2-bit Data Input - DIB => memBWrite(29 downto 28), -- Port B 2-bit Data Input - ENA => re, -- Port A RAM Enable Input - ENB => high, -- PortB RAM Enable Input - SSRA => low, -- Port A Synchronous Set/Reset Input - SSRB => low, -- Port B Synchronous Set/Reset Input - WEA => memAWriteEnable, -- Port A Write Enable Input - WEB => memBWriteEnable -- Port B Write Enable Input - ); - ZPU_RAM15 : RAMB16_S2_S2 - generic map ( - INIT_A => X"0", -- Value of output RAM registers on Port A at startup - INIT_B => X"0", -- Value of output RAM registers on Port B at startup - SRVAL_A => X"0", -- Port A ouput value upon SSR assertion - SRVAL_B => X"0", -- Port B ouput value upon SSR assertion - WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE - WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE - SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" - INIT_00 => X"012501250005000C00850021000C04790015000800150445000C06A500A20022", - INIT_01 => X"3E0000000102861A0021001A000062014461000800080008000C000500090005", - INIT_02 => X"00016181A9A606405555555408000000020400000000C1800000002406860012", - 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INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000") - port map ( - DOA => memARead(31 downto 30), -- Port A 2-bit Data Output - DOB => memBRead(31 downto 30), -- Port B 2-bit Data Output - ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input - ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input - CLKA => clk, -- Port A Clock - CLKB => clk, -- Port B Clock - DIA => memAWrite(31 downto 30), -- Port A 2-bit Data Input - DIB => memBWrite(31 downto 30), -- Port B 2-bit Data Input - ENA => re, -- Port A RAM Enable Input - ENB => high, -- PortB RAM Enable Input - SSRA => low, -- Port A Synchronous Set/Reset Input - SSRB => low, -- Port B Synchronous Set/Reset Input - WEA => memAWriteEnable, -- Port A Write Enable Input - WEB => memBWriteEnable -- Port B Write Enable Input - ); -end dualport_ram_arch; diff --git a/zpu/hdl/zpu3/src/xmake.filelist b/zpu/hdl/zpu3/src/xmake.filelist deleted file mode 100644 index 3d0a779..0000000 --- a/zpu/hdl/zpu3/src/xmake.filelist +++ /dev/null @@ -1,5 +0,0 @@ -vhdl zylin "zpu_config.vhd" -vhdl zylin "zpupkg.vhd" -vhdl work "dmips_ram.vhd" -vhdl zylin "zpu_top_bram_intstack.vhd" -vhdl work "testlut.vhd" diff --git a/zpu/hdl/zpu3/src/xmake.xst b/zpu/hdl/zpu3/src/xmake.xst deleted file mode 100644 index bfdb23f..0000000 --- a/zpu/hdl/zpu3/src/xmake.xst +++ /dev/null @@ -1,53 +0,0 @@ -set -tmpdir ../tmp -set -xsthdpdir ../xst -run --ifn xmake.filelist --ifmt mixed --ofn ../syn/ic300 --ofmt NGC --p xc3s400-4-ft256 --top ic300 --opt_mode Area --opt_level 2 --iuc NO --lso ic300.lso --keep_hierarchy NO --glob_opt AllClockNets --rtlview Yes --read_cores YES --write_timing_constraints NO --cross_clock_analysis NO --hierarchy_separator / --bus_delimiter <> --case maintain --slice_utilization_ratio 100 --verilog2001 YES --fsm_extract YES -fsm_encoding Auto --safe_implementation No --fsm_style lut --ram_extract Yes --ram_style Auto --rom_extract Yes --rom_style Auto --mux_extract YES --mux_style Auto --decoder_extract YES --priority_extract YES --shreg_extract YES --shift_extract YES --xor_collapse YES --resource_sharing YES --mult_style auto --iobuf YES --max_fanout 500 --bufg 8 --register_duplication YES --equivalent_register_removal NO --register_balancing No --slice_packing YES --optimize_primitives NO --use_clock_enable Yes --use_sync_set No --use_sync_reset No --iob true --slice_utilization_ratio_maxmargin 5 diff --git a/zpu/hdl/zpu3/src/zpu_config.vhd b/zpu/hdl/zpu3/src/zpu_config.vhd deleted file mode 100644 index 506121c..0000000 --- a/zpu/hdl/zpu3/src/zpu_config.vhd +++ /dev/null @@ -1,25 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -package zpu_config is - - constant Generate_Trace : boolean := false; - -- during simulation, set this to '0' to get matching trace.txt - constant DontCareValue : std_logic := '0'; - -- Clock frequency in MHz. - constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64"; - -- maximum address includes upper bit for IO registers - -- the rest is RAM - constant maxAddrBit : integer := 14; - constant minAddrBit : integer := 2; - -- This bit is set for read/writes to IO - -- FIX!!! eventually this should be set to wordSize-1 so as to - -- to make the address of IO independent of amount of memory - -- reserved for CPU. Requires trivial tweaks in toolchain/runtime - -- libraries. - constant ioBit : integer := maxAddrBit+1; - constant wordPower : integer := 5; - constant wordSize : integer := 2**wordPower; - -end zpu_config; diff --git a/zpu/hdl/zpu3/src/zpu_pipelined.vhd b/zpu/hdl/zpu3/src/zpu_pipelined.vhd deleted file mode 100644 index 207939d..0000000 --- a/zpu/hdl/zpu3/src/zpu_pipelined.vhd +++ /dev/null @@ -1,852 +0,0 @@ --- Company: ZPU3 --- Engineer: Øyvind Harboe - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -use IEEE.STD_LOGIC_arith.ALL; - -library zylin; -use zylin.zpu_config.all; -use zylin.zpupkg.all; - - -entity zpu_top is - Port ( clk : in std_logic; - areset : in std_logic; - io_busy : in std_logic; - io_read : in std_logic_vector(7 downto 0); - io_write : out std_logic_vector(7 downto 0); - io_addr : out std_logic_vector(maxAddrBit downto minAddrBit); - io_writeEnable : out std_logic; - io_readEnable : out std_logic; - interrupt : in std_logic; - break : out std_logic); -end zpu_top; - -architecture behave of zpu_top is - -signal readIO : std_logic; - - - -signal memAWriteEnable : std_logic; -signal memAAddr : std_logic_vector(maxAddrBit downto minAddrBit); -signal memAWrite : std_logic_vector(wordSize-1 downto 0); -signal memARead : std_logic_vector(wordSize-1 downto 0); -signal memBWriteEnable : std_logic; -signal memBAddr : std_logic_vector(maxAddrBit downto minAddrBit); -signal memBWrite : std_logic_vector(wordSize-1 downto 0); -signal memBRead : std_logic_vector(wordSize-1 downto 0); - - -signal busy : std_logic; - -signal begin_inst : std_logic; - - - -signal trace_opcode : std_logic_vector(7 downto 0); -signal trace_pc : std_logic_vector(maxAddrBit downto 0); -signal trace_sp : std_logic_vector(maxAddrBit downto minAddrBit); -signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); -signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); - -type DecodedOpcodeType is -( -Decoded_Stall , -Decoded_Nop , -Decoded_Im , -Decoded_ImShift , -Decoded_LoadSP , -Decoded_StoreSP , -Decoded_AddSP , -Decoded_Emulate , -Decoded_Break , -Decoded_PushPC , -Decoded_PushSP , -Decoded_PopPC , -Decoded_Add , -Decoded_Or , -Decoded_And , -Decoded_Load , -Decoded_Not , -Decoded_Flip , -Decoded_Store , -Decoded_Storeb , -Decoded_PopSP , -Decoded_Ashiftleft , -Decoded_Ashiftright , -Decoded_Lshiftright , -Decoded_Eqbranch , -Decoded_Neqbranch , -Decoded_Eq , -Decoded_Neq , -Decoded_Loadb , -Decoded_Lessthan , -Decoded_Lessthanorequal , -Decoded_Ulessthan , -Decoded_Ulessthanorequal , -Decoded_Duplicate , -Decoded_Duplicate2 , -Decoded_Duplicate3 , -Decoded_MoveDown, -Decoded_MoveDown2, -Decoded_MoveDown3, -Decoded_Pushspadd, -Decoded_Callpcrel, -Decoded_Sub -); - - -signal decode_pc : std_logic_vector(maxAddrBit downto 0); -signal decode_fetchedPC : std_logic_vector(maxAddrBit downto 0); -signal decode_fetched : std_logic; -signal decode_opcode : std_logic_vector(OpCode_Size-1 downto 0); -signal decode_opcodeWord : std_logic_vector(wordSize-1 downto 0); -signal decode_starved : std_logic; -signal decode_wordStarved : std_logic; -signal decode_willBeStarved : std_logic; -signal decode_idim_flag : std_logic; - -signal execute1_stall : std_logic; -signal execute1_fetched : std_logic; -signal execute1_decodedOpcode : DecodedOpcodeType; -signal execute1_fetchedPC : std_logic_vector(maxAddrBit downto 0); -signal execute1_sp : std_logic_vector(maxAddrBit downto minAddrBit); -signal execute1_opcode : std_logic_vector(opCode_Size-1 downto 0); -signal execute1_spOffset : std_logic_vector(4 downto 0); -signal execute1_fetchPC : std_logic_vector(maxAddrBit downto 0); -signal execute1_push1 : std_logic; -signal execute1_push2 : std_logic; -signal execute1_pop1 : std_logic; -signal execute1_pop2 : std_logic; -signal execute1_antialias : std_logic; -signal execute1_savedTopOfStack : std_logic_vector(wordSize-1 downto 0); - - -signal load_decodedOpcode : DecodedOpcodeType; -signal load_opcode : std_logic_vector(opCode_Size-1 downto 0); -signal load_spOffset : std_logic_vector(4 downto 0); -signal load_stall : std_logic; -signal load_willBeStalled : std_logic; - -signal execute2_opcode : std_logic_vector(opCode_Size-1 downto 0); -signal execute2_topOfStack : std_logic_vector(wordSize-1 downto 0); -signal execute2_addResult : std_logic_vector(wordSize-1 downto 0); -signal execute2_topOfStackB : std_logic_vector(wordSize-1 downto 0); -signal execute2_pc : std_logic_vector(maxAddrBit downto 0); -signal execute2_sp : std_logic_vector(maxAddrBit downto minAddrBit); -signal execute2_loading : std_logic; -signal execute2_loadByte : std_logic; -signal execute2_storeByte : std_logic; -signal execute2_loadingDone : std_logic; -signal execute2_decodedOpcode : DecodedOpcodeType; -signal execute2_spOffset : std_logic_vector(4 downto 0); -signal execute2_persistTopOfStack : std_logic; -signal execute2_persistTopOfStackB : std_logic; -signal execute2_resync : std_logic; -signal execute2_resync2 : std_logic; -signal execute2_resync3 : std_logic; -signal execute2_resync4 : std_logic; -signal execute2_resync5 : std_logic; -signal execute2_resync6 : std_logic; -signal execute2_resync7 : std_logic; -signal execute2_resync8 : std_logic; -signal execute2_resync9 : std_logic; -signal execute2_resync10 : std_logic; - - -begin - traceFileGenerate: - if Generate_Trace generate - trace_file: trace port map ( - clk => clk, - begin_inst => begin_inst, - pc => trace_pc, - opcode => trace_opcode, - sp => trace_sp, - memA => trace_topOfStack, - memB => trace_topOfStackB, - busy => busy - ); - end generate; - - - memory: dualport_ram port map ( - clk => clk, - memAWriteEnable => memAWriteEnable, - memAAddr => memAAddr, - memAWrite => memAWrite, - memARead => memARead, - memBWriteEnable => memBWriteEnable, - memBAddr => memBAddr, - memBWrite => memBWrite, - memBRead => memBRead - ); - - opcodeControl: - process(clk, areset) - variable compareA : signed(wordSize-1 downto 0); - variable compareB : signed(wordSize-1 downto 0); - variable execute1_doFetch : boolean; - begin - if areset = '1' then - break <= '0'; - begin_inst <= '0'; - memAAddr <= (others => '0'); - memBAddr <= (others => '0'); - memAWriteEnable <= '0'; - memBWriteEnable <= '0'; - memAWrite <= (others => '0'); - memBWrite <= (others => '0'); - - memBAddr <= (others => '0'); - memBWrite <= (others => '0'); - - - io_writeEnable <= '0'; - io_readEnable <= '0'; - io_addr <= (others => '0'); - io_write <= (others => '0'); - - -- stage 1. Don't care since this is driven by stage2 - decode_pc <= (others => '0'); - decode_fetched <= '0'; - decode_starved <= '0'; - decode_opcode <= (others => '0'); - decode_opcodeWord <= (others => '0'); - - -- stage 2. - execute1_antialias <= '0'; - execute1_fetchPC <= (others => '0'); - execute1_fetched <= '0'; - execute1_decodedOpcode <= Decoded_Stall; - execute1_sp <= (2 => '0', others => '1'); - execute1_push1 <= '0'; - execute1_push2 <= '0'; - execute1_pop1 <= '0'; - execute1_pop2 <= '0'; - execute1_stall <= '1'; - - -- stage 3 - load_decodedOpcode <= Decoded_Stall; - load_stall <= '1'; - load_willBeStalled <= '1'; - - -- stage 4 - decode_idim_flag <= '0'; - execute2_pc <= (others => '0'); - execute2_sp <= (2 => '0', others => '1'); - execute2_loading <= '0'; - execute2_loadByte <= '0'; - execute2_storeByte <= '0'; - execute2_loadingDone <= '0'; - execute2_decodedOpcode <= Decoded_Stall; - execute2_resync <= '1'; - execute2_resync2 <= '0'; - execute2_resync3 <= '0'; - execute2_resync4 <= '0'; - execute2_resync5 <= '0'; - execute2_resync6 <= '0'; - execute2_resync7 <= '0'; - execute2_resync8 <= '0'; - execute2_resync9 <= '0'; - execute2_resync10 <= '0'; - execute2_persistTopOfStack <= '0'; - execute2_persistTopOfStackB <= '0'; - - -- stage 5 - memBWriteEnable <= '0'; - - - elsif (clk'event and clk = '1') then - memAWriteEnable <= '0'; - memBWriteEnable <= '0'; - io_writeEnable <= '0'; - io_readEnable <= '0'; - begin_inst <= '0'; - - -- stage0: fetch - decode_willBeStarved <= '0'; - if (decode_fetched='1') then - -- resync #4 - decode_opcodeWord <= memARead; - decode_pc <= decode_fetchedPC; - elsif (decode_pc(minAddrBit-1 downto 0)=b"11") then - decode_willBeStarved <= '1'; - else - -- we can continue decoding. - decode_pc <= decode_pc + 1; - end if; - - -- stage 0b: move to byte.. - -- resync #5 - decode_starved <= decode_willBeStarved; - case decode_pc(minAddrBit-1 downto 0) is - when "00" => decode_opcode <= decode_opcodeWord(31 downto 24); - when "01" => decode_opcode <= decode_opcodeWord(23 downto 16); - when "10" => decode_opcode <= decode_opcodeWord(15 downto 8); - when others => decode_opcode <= decode_opcodeWord(7 downto 0); - end case; - - -- stage1: decode 1 - execute1_opcode <= decode_opcode; - - execute1_spOffset(4)<=not decode_opcode(4); - execute1_spOffset(3 downto 0)<=decode_opcode(3 downto 0); - - execute1_decodedOpcode<=Decoded_Break; - - decode_idim_flag <= '0'; - - -- resync #6 - -- resync #1 - if (decode_starved = '1') then - execute1_decodedOpcode<=Decoded_Stall; - decode_idim_flag <= decode_idim_flag; - elsif (decode_opcode(7 downto 7)=OpCode_Im) then - decode_idim_flag <= '1'; - if (decode_idim_flag = '0') then - execute1_decodedOpcode<=Decoded_Im; - else - execute1_decodedOpcode<=Decoded_ImShift; - end if; - elsif (decode_opcode(7 downto 5)=OpCode_StoreSP) then - if (decode_opcode(4 downto 0)=b"10001") then - execute1_decodedOpcode<=Decoded_MoveDown; - elsif (decode_opcode(4 downto 0)=b"10010") then - execute1_decodedOpcode<=Decoded_MoveDown2; --- elsif (decode_opcode(4 downto 0)=b"10011") then --- execute1_decodedOpcode<=Decoded_MoveDown3; - else - execute1_decodedOpcode<=Decoded_StoreSP; - end if; - elsif (decode_opcode(7 downto 5)=OpCode_LoadSP) then - if (decode_opcode(4 downto 0)=b"10000") then - execute1_decodedOpcode<=Decoded_Duplicate; - elsif (decode_opcode(4 downto 0)=b"10001") then - execute1_decodedOpcode<=Decoded_Duplicate2; - elsif (decode_opcode(4 downto 0)=b"10010") then - execute1_decodedOpcode<=Decoded_Duplicate3; - else - execute1_decodedOpcode<=Decoded_LoadSP; - end if; - elsif (decode_opcode(7 downto 5)=OpCode_Emulate) then - execute1_decodedOpcode<=Decoded_Emulate; - if decode_opcode(5 downto 0)=OpCode_Neqbranch then - execute1_decodedOpcode <= Decoded_Neqbranch; - elsif decode_opcode(5 downto 0)=OpCode_Eq then - execute1_decodedOpcode <= Decoded_Eq; - elsif decode_opcode(5 downto 0)=OpCode_Lessthan then - execute1_decodedOpcode <= Decoded_Lessthan; - elsif decode_opcode(5 downto 0)=OpCode_Ulessthan then - execute1_decodedOpcode <= Decoded_Ulessthan; - elsif decode_opcode(5 downto 0)=OpCode_Loadb then - execute1_decodedOpcode <= Decoded_Loadb; - elsif decode_opcode(5 downto 0)=OpCode_Storeb then - execute1_decodedOpcode <= Decoded_Storeb; - elsif decode_opcode(5 downto 0)=OpCode_Pushspadd then - execute1_decodedOpcode <= Decoded_Pushspadd; - elsif decode_opcode(5 downto 0)=OpCode_Callpcrel then - execute1_decodedOpcode <= Decoded_Callpcrel; - elsif decode_opcode(5 downto 0)=OpCode_Sub then - execute1_decodedOpcode <= Decoded_Sub; - end if; - elsif (decode_opcode(7 downto 4)=OpCode_AddSP) then - if (decode_opcode(3 downto 0) = 0) then - execute1_decodedOpcode<=Decoded_Ashiftleft; - elsif (decode_opcode(3 downto 0) = 1) then --- execute1_decodedOpcode<=Decoded_AddSP; - elsif (decode_opcode(3 downto 0) = 2) then --- execute1_decodedOpcode<=Decoded_AddSP; - else - execute1_decodedOpcode<=Decoded_AddSP; - end if; - else - case decode_opcode(3 downto 0) is - when OpCode_Nop => - execute1_decodedOpcode<=Decoded_Nop; - when OpCode_PushSP => - execute1_decodedOpcode<=Decoded_PushSP; - when OpCode_PopPC => - execute1_decodedOpcode<=Decoded_PopPC; - when OpCode_Add => - execute1_decodedOpcode<=Decoded_Add; - when OpCode_Or => - execute1_decodedOpcode<=Decoded_Or; - when OpCode_And => - execute1_decodedOpcode<=Decoded_And; - when OpCode_Load => - execute1_decodedOpcode<=Decoded_Load; - when OpCode_Not => - execute1_decodedOpcode<=Decoded_Not; - when OpCode_Flip => - execute1_decodedOpcode<=Decoded_Flip; - when OpCode_Store => - execute1_decodedOpcode<=Decoded_Store; - when OpCode_PopSP => - execute1_decodedOpcode<=Decoded_PopSP; - when others => - execute1_decodedOpcode<=Decoded_Break; - end case; - end if; - - - -- stage 2: execute 1 - load stage. - -- - -- the address must be known without using the value on top of the stack... - -- resync #3 - execute1_fetched <= '0'; - decode_fetched <= execute1_fetched; -- the value in memAAddr will be valid for 1 cycle only - decode_fetchedPC <= execute1_fetchedPC; - - if (execute1_fetchPC(1 downto 0)/=b"00") then - execute1_fetchPC <= execute1_fetchPC+1; - end if; - - execute1_push1 <= '0'; - execute1_push2 <= execute1_push1; - execute1_pop1 <= '0'; - execute1_pop2 <= execute1_pop1; - - if ((execute1_push1 and execute1_push2)='1') then - memAWrite <= execute2_topOfStack; - else - memAWrite <= execute2_topOfStackB; - end if; - - -- resync #7 - case execute1_decodedOpcode is - when Decoded_Neqbranch | Decoded_MoveDown3 | Decoded_Load | Decoded_Loadb | Decoded_Store | Decoded_Storeb | Decoded_Emulate | Decoded_PopSP | Decoded_PopPC| Decoded_Callpcrel => - execute1_stall <= '1'; - when others => - -- nothing... - end case; - - execute1_antialias <= load_stall; - execute1_doFetch := false; - case execute1_decodedOpcode is - when Decoded_PushSP | Decoded_Emulate => - execute1_sp <= execute1_sp - 1; - execute1_push1 <= '1'; - execute1_doFetch := true; - when Decoded_Duplicate3 => - memAWriteEnable <= ((execute1_push1 and execute1_push2) or - (execute1_push1 and not execute1_pop2) or - (execute1_push2 and not execute1_pop1)) and - (not execute1_antialias and not execute1_stall); - memAAddr <= execute1_sp + 2; - execute1_sp <= execute1_sp - 1; - execute1_push1 <= '1'; - when Decoded_Im | Decoded_Duplicate | Decoded_Duplicate2 => - execute1_sp <= execute1_sp - 1; - execute1_push1 <= '1'; - execute1_doFetch := true; - when Decoded_LoadSP => - memAAddr <= execute1_sp+execute1_spOffset; - execute1_sp <= execute1_sp - 1; - execute1_push1 <= '1'; - when Decoded_AddSP => - memAAddr <= execute1_sp+execute1_spOffset; - when Decoded_MoveDown2 => - execute1_sp <= execute1_sp + 1; - execute1_pop1 <= '1'; - execute1_doFetch := true; - when Decoded_Ulessthan | Decoded_Lessthan | Decoded_Eq | Decoded_Neqbranch | Decoded_MoveDown3 | Decoded_MoveDown | Decoded_Add | Decoded_Sub | Decoded_Or | Decoded_And | Decoded_PopPC | Decoded_StoreSP => - -- be afraid :-) - memAWriteEnable <= ((execute1_push1 and execute1_push2) or - (execute1_push1 and not execute1_pop2) or - (execute1_push2 and not execute1_pop1)) and - (not execute1_antialias and not execute1_stall); - memAAddr <= execute1_sp + 2; - execute1_sp <= execute1_sp + 1; - execute1_pop1 <= '1'; - when others => - execute1_doFetch := true; - end case; - - if execute1_doFetch then - -- resync #2 - -- some instruction that does not change the stack pointer - -- and does not need use a memory operand. - -- We can fetch the next word to be decoded to avoid stalls - execute1_fetchPC <= execute1_fetchPC+1; - memAAddr <= execute1_fetchPC(maxAddrBit downto minAddrBit); - execute1_fetchedPC <= execute1_fetchPC; - execute1_fetched <= '1'; - end if; - - - -- stage 3: fetching memory takes 1 cycle - -- here we also verify that we've fetched & decoded the right - -- opcode. - -- resync #8 - load_decodedOpcode <= execute1_decodedOpcode; - load_opcode <= execute1_opcode; - load_spOffset <= execute1_spOffset; - load_stall <= execute1_stall; - -- resync #9 - if (load_stall = '1') then - execute2_decodedOpcode <= Decoded_Stall; - else - execute2_decodedOpcode <= load_decodedOpcode; - end if; - execute2_opcode <= load_opcode; - execute2_spOffset <= load_spOffset; - - -- stage 4: execute 2 - we now have both operands. This is the - -- main execute stage... - begin_inst <= '1'; - trace_pc <= execute2_pc; - trace_opcode <= execute2_opcode; - trace_sp <= execute2_sp; - trace_topOfStack <= execute2_topOfStack; - trace_topOfStackB <= execute2_topOfStackB; - - execute2_pc <= execute2_pc + 1; - execute2_loading <= '0'; - memBWriteEnable <= '0'; - - case execute2_decodedOpcode is - when Decoded_PopSP => - execute2_sp <= execute2_topOfStack(maxAddrBit downto minAddrBit); - - memBWriteEnable <= '1'; - memBAddr <= execute2_sp + 1; - memBWrite <= execute2_topOfStackB; - execute2_resync <= '1'; - when Decoded_Callpcrel => - execute2_topOfStack <= (others => DontCareValue); - execute2_topOfStack(maxAddrBit downto 0) <= execute2_pc + 1; - execute2_pc <= execute2_pc + execute2_topOfStack(maxAddrBit downto 0); - execute2_persistTopOfStack <= '1'; - when Decoded_PopPC => - execute2_pc <= execute2_topOfStack(maxAddrBit downto 0); - execute2_sp <= execute2_sp + 1; - - memBWriteEnable <= '1'; - memBAddr <= execute2_sp + 1; - memBWrite <= execute2_topOfStackB; - execute2_resync <= '1'; - when Decoded_Emulate => - execute2_sp <= execute2_sp - 1; - - execute2_topOfStack <= (others => DontCareValue); - execute2_topOfStack(maxAddrBit downto 0) <= execute2_pc + 1; - execute2_topOfStackB <= execute2_topOfStack; - - memBWriteEnable <= '1'; - memBAddr <= execute2_sp+1; - memBWrite <= execute2_topOfStackB; - -- The emulate address is: - -- 98 7654 3210 - -- 0000 00aa aaa0 0000 - execute2_pc <= (others => '0'); - execute2_pc(9 downto 5) <= execute2_opcode(4 downto 0); - execute2_persistTopOfStack <= '1'; - when Decoded_Im => - execute2_sp <= execute2_sp - 1; - for i in wordSize-1 downto 7 loop - execute2_topOfStack(i) <= execute2_opcode(6); - end loop; - execute2_topOfStack(6 downto 0) <= execute2_opcode(6 downto 0); - - execute2_topOfStackB <= execute2_topOfStack; - memBWriteEnable <= '1'; - memBAddr <= execute2_sp + 1; - memBWrite <= execute2_topOfStackB; - when Decoded_ImShift => - execute2_topOfStack(wordSize-1 downto 7) <= execute2_topOfStack(wordSize-8 downto 0); - execute2_topOfStack(6 downto 0) <= execute2_opcode(6 downto 0); - when Decoded_LoadSP => - execute2_sp <= execute2_sp - 1; - execute2_topOfStack <= memARead; - execute2_topOfStackB <= execute2_topOfStack; - memBWriteEnable <= '1'; - memBAddr <= execute2_sp + 1; - memBWrite <= execute2_topOfStackB; - when Decoded_Break => - report "Break instruction encountered" severity failure; - break <= '1'; - when Decoded_PushSP => - execute2_topOfStack <= (others => DontCareValue); - execute2_topOfStack(maxAddrBit downto minAddrBit) <= execute2_sp; - - execute2_sp <= execute2_sp - 1; - execute2_topOfStackB <= execute2_topOfStack; - memBWriteEnable <= '1'; - memBAddr <= execute2_sp + 1; - memBWrite <= execute2_topOfStackB; - when Decoded_Add => - execute2_sp <= execute2_sp + 1; - execute2_topOfStack <= execute2_topOfStackB + execute2_topOfStack; - execute2_topOfStackB <= memARead; - when Decoded_Sub => - execute2_sp <= execute2_sp + 1; - execute2_topOfStack <= execute2_topOfStackB - execute2_topOfStack; - execute2_topOfStackB <= memARead; - when Decoded_AddSP => - execute2_topOfStack <= execute2_topOfStack + memARead; - when Decoded_Or => - execute2_sp <= execute2_sp + 1; - execute2_topOfStack <= execute2_topOfStackB or execute2_topOfStack; - execute2_topOfStackB <= memARead; - when Decoded_And => - execute2_sp <= execute2_sp + 1; - execute2_topOfStack <= execute2_topOfStackB and execute2_topOfStack; - execute2_topOfStackB <= memARead; - when Decoded_Load | Decoded_Loadb | Decoded_Storeb => - if (execute2_topOfStack(ioBit)='1') then - io_addr <= execute2_topOfStack(maxAddrBit downto minAddrBit); - io_readEnable <= '1'; - else - memAAddr <= execute2_topOfStack(maxAddrBit downto minAddrBit); - execute1_fetched <= '0'; - end if; - if (execute2_decodedOpcode = Decoded_Loadb) then - execute2_loadByte <= '1'; - else - execute2_loadByte <= '0'; - end if; - if (execute2_decodedOpcode = Decoded_Storeb) then - execute2_storeByte <= '1'; - else - execute2_storebyte <= '0'; - end if; - execute2_loading <= '1'; - when Decoded_Ashiftleft => - execute2_topOfStack(wordSize-1 downto 1) <= execute2_topOfStack(wordSize-2 downto 0); - execute2_topOfStack(0) <= '0'; - when Decoded_MoveDown => - execute2_sp <= execute2_sp + 1; - execute2_topOfStackB <= memARead; - when Decoded_MoveDown2 => - execute2_sp <= execute2_sp + 1; - execute2_topOfStack <= execute2_topOfStackB; - execute2_topOfStackB <= execute2_topOfStack; - when Decoded_MoveDown3 => - execute2_sp <= execute2_sp + 1; - memBWriteEnable <= '1'; - memBAddr <= execute2_sp+execute2_spOffset; - memBWrite <= execute2_topOfStack; - - execute2_topOfStack <= execute2_topOfStackB; - execute2_topOfStackB <= memARead; - execute2_persistTopOfStack <= '1'; - when Decoded_Duplicate => - execute2_topOfStackB <= execute2_topOfStack; - execute2_sp <= execute2_sp - 1; - memBWriteEnable <= '1'; - memBAddr <= execute2_sp + 1; - memBWrite <= execute2_topOfStackB; - when Decoded_Duplicate2 => - execute2_topOfStack <= execute2_topOfStackB; - execute2_topOfStackB <= execute2_topOfStack; - execute2_sp <= execute2_sp - 1; - memBWriteEnable <= '1'; - memBAddr <= execute2_sp + 1; - memBWrite <= execute2_topOfStackB; - when Decoded_Duplicate3 => - execute2_topOfStack <= memARead; - execute2_topOfStackB <= execute2_topOfStack; - execute2_sp <= execute2_sp - 1; - memBWriteEnable <= '1'; - memBAddr <= execute2_sp + 1; - memBWrite <= execute2_topOfStackB; - when Decoded_Pushspadd => - execute2_topOfStack <= (others => DontCareValue); - execute2_topOfStack(maxAddrBit downto minAddrBit) <= execute2_sp + execute2_topOfStack(maxAddrBit-minAddrBit downto 0); - when Decoded_Not => - execute2_topOfStack <= not execute2_topOfStack; - when Decoded_Flip => - for i in 0 to wordSize-1 loop - execute2_topOfStack(i) <= execute2_topOfStack(wordSize-1-i); - end loop; - when Decoded_Store => - execute2_sp <= execute2_sp + 2; - if (execute2_topOfStack(ioBit)='0') then - memBAddr <= execute2_topOfStack(maxAddrBit downto minAddrBit); - memBWrite <= execute2_topOfStackB; - memBWriteEnable <= '1'; - else - io_addr <= execute2_topOfStack(maxAddrBit downto minAddrBit); - io_write <= execute2_topOfStackB(7 downto 0); - io_writeEnable <= '1'; - end if; - execute2_resync <= '1'; - when Decoded_StoreSP => - execute2_sp <= execute2_sp + 1; - memBWriteEnable <= '1'; - memBAddr <= execute2_sp+execute2_spOffset; - memBWrite <= execute2_topOfStack; - - execute2_topOfStack <= execute2_topOfStackB; - execute2_topOfStackB <= memARead; - when Decoded_Neqbranch => - execute2_sp <= execute2_sp + 2; - if (execute2_topOfStackB/=0) then - execute2_pc <= execute2_topOfStack(maxAddrBit downto 0) + execute2_pc; - end if; - execute2_resync <= '1'; - when Decoded_Eq => - execute2_sp <= execute2_sp + 1; - execute2_topOfStack <= (others => '0'); - if (execute2_topOfStack=execute2_topOfStackB) then - execute2_topOfStack(0) <= '1'; - end if; - execute2_topOfStackB <= memARead; - when Decoded_Ulessthan => - execute2_sp <= execute2_sp + 1; - execute2_topOfStack <= (others => '0'); - if (execute2_topOfStack - execute2_sp <= execute2_sp + 1; - execute2_topOfStack <= (others => '0'); - compareA := signed(execute2_topOfStack); - compareB := signed(execute2_topOfStackB); - if (compareA - begin_inst <= '0'; - execute2_pc <= execute2_pc; - when others => - -- nop - end case; - - -- load cycle... - execute2_loadingDone <= execute2_loading; - if (execute2_loadingDone ='1') then - if (execute2_topOfStack(ioBit)='1') then - if (io_busy = '0') then - execute2_topOfStack <= (others => '0'); - execute2_topOfStack(7 downto 0) <= io_read; - execute2_persistTopOfStack <= '1'; - else - execute2_loadingDone <= '1'; - end if; - else - if (execute2_storeByte = '1') then - execute2_sp <= execute2_sp + 2; - memBWriteEnable <= '1'; - memBAddr <= execute2_topOfStack(maxAddrBit downto minAddrBit); - memBWrite <= memARead; - case execute2_topOfStack(minAddrBit-1 downto 0) is - when "00" => memBWrite(31 downto 24) <= execute2_topOfStackB(7 downto 0); - when "01" => memBWrite(23 downto 16) <= execute2_topOfStackB(7 downto 0); - when "10" => memBWrite(15 downto 8) <= execute2_topOfStackB(7 downto 0); - when others => memBWrite(7 downto 0) <= execute2_topOfStackB(7 downto 0); - end case; --- case execute2_topOfStack(0 downto 0) is --- when "1" => memBWrite(15 downto 8) <= execute2_topOfStackB(7 downto 0); --- when others => memBWrite(7 downto 0) <= execute2_topOfStackB(7 downto 0); --- end case; - execute2_resync <= '1'; - elsif (execute2_loadByte = '1') then - execute2_topOfStack <= (others => '0'); - case execute2_topOfStack(minAddrBit-1 downto 0) is - when "00" => execute2_topOfStack(7 downto 0) <= memARead(31 downto 24); - when "01" => execute2_topOfStack(7 downto 0) <= memARead(23 downto 16); - when "10" => execute2_topOfStack(7 downto 0) <= memARead(15 downto 8); - when others => execute2_topOfStack(7 downto 0) <= memARead(7 downto 0); - end case; --- case execute2_topOfStack(0 downto 0) is --- when "1" => execute2_topOfStack(7 downto 0) <= memARead(15 downto 8); --- when others => execute2_topOfStack(7 downto 0) <= memARead(7 downto 0); --- end case; - execute2_persistTopOfStack <= '1'; - else - execute2_topOfStack <= memARead; - execute2_persistTopOfStack <= '1'; - end if; - end if; - end if; - - -- write top of stack... - execute2_persistTopOfStackB <= execute2_persistTopOfStack; - if (execute2_persistTopOfStack = '1') then - execute2_persistTopOfStack <= '0'; - memBWriteEnable <= '1'; - memBAddr <= execute2_sp; - memBWrite <= execute2_topOfStack; - end if; - if (execute2_persistTopOfStackB = '1') then - memBWriteEnable <= '1'; - memBAddr <= execute2_sp+1; - memBWrite <= execute2_topOfStackB; - - execute2_resync <= '1'; - end if; - - -- here we resync the pipeline. - -- a number of things have to happen on certain cycles - execute2_resync2 <= execute2_resync; - execute2_resync3 <= execute2_resync2; - execute2_resync4 <= execute2_resync3; - execute2_resync5 <= execute2_resync4; - execute2_resync6 <= execute2_resync5; - execute2_resync7 <= execute2_resync6; - execute2_resync8 <= execute2_resync7; - execute2_resync9 <= execute2_resync8; - execute2_resync10 <= execute2_resync9; - - if (execute2_resync = '1' ) then - -- resync #1 - execute2_resync <= '0'; - decode_starved <= '1'; - memAAddr <= execute2_sp; - end if; - if (execute2_resync2 = '1') then - -- resync #2 - execute1_fetchPC <= execute2_pc; - memAAddr <= execute2_sp + 1; - end if; - if (execute2_resync3 = '1') then - -- resync #3 - execute2_topOfStack <= memARead; - end if; - if (execute2_resync4 = '1') then - -- resync #4 - -- during this cycle the address is set to the opcode - execute2_topOfStackB <= memARead; - end if; - if (execute2_resync5 = '1') then - -- resync #5 - execute1_pop1 <= '0'; - execute1_push1 <= '0'; - end if; - if (execute2_resync6 = '1') then - -- resync #6 - decode_idim_flag <= '0'; - execute1_pop1 <= '0'; - execute1_push1 <= '0'; - end if; - if (execute2_resync7 = '1') then - -- resync #7 - execute1_sp <= execute2_sp; - execute1_stall <= '0'; - end if; - if (execute2_resync8 = '1') then - -- resync #8 --- load_stall <= '0'; - end if; - if (execute2_resync9 = '1') then - -- resync #9 - end if; - if (execute2_resync10 = '1') then - end if; - - - - - end if; - end process; - - - -end behave; diff --git a/zpu/hdl/zpu3/src/zpu_top.vhd b/zpu/hdl/zpu3/src/zpu_top.vhd deleted file mode 100644 index 0ac6df4..0000000 --- a/zpu/hdl/zpu3/src/zpu_top.vhd +++ /dev/null @@ -1,421 +0,0 @@ --- Company: ZPU3 --- Engineer: Øyvind Harboe - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library zylin; -use zylin.zpu_config.all; -use zylin.zpupkg.all; - - -entity zpu_top is - Port ( clk : in std_logic; - areset : in std_logic; - io_busy : in std_logic; - io_read : in std_logic_vector(7 downto 0); - io_write : out std_logic_vector(7 downto 0); - io_addr : out std_logic_vector(maxAddrBit downto minAddrBit); - io_writeEnable : out std_logic; - io_readEnable : out std_logic; - interrupt : in std_logic; - break : out std_logic); -end zpu_top; - -architecture behave of zpu_top is - -signal readIO : std_logic; - - - -signal memAWriteEnable : std_logic; -signal memAAddr : std_logic_vector(maxAddrBit downto minAddrBit); -signal memAWrite : std_logic_vector(wordSize-1 downto 0); -signal memARead : std_logic_vector(wordSize-1 downto 0); -signal memBWriteEnable : std_logic; -signal memBAddr : std_logic_vector(maxAddrBit downto minAddrBit); -signal memBWrite : std_logic_vector(wordSize-1 downto 0); -signal memBRead : std_logic_vector(wordSize-1 downto 0); - - - -signal pc : std_logic_vector(maxAddrBit downto 0); -signal sp : std_logic_vector(maxAddrBit downto minAddrBit); - -signal idim_flag : std_logic; - ---signal storeToStack : std_logic; ---signal fetchNextInstruction : std_logic; ---signal extraCycle : std_logic; -signal busy : std_logic; ---signal fetching : std_logic; - -signal begin_inst : std_logic; - - - -signal trace_opcode : std_logic_vector(7 downto 0); -signal trace_pc : std_logic_vector(maxAddrBit downto 0); -signal trace_sp : std_logic_vector(maxAddrBit downto minAddrBit); -signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); -signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); - --- state machine. - -subtype State_Type is std_logic_vector(3 downto 0); -constant State_Fetch : State_Type := b"0000"; -constant State_WriteIODone : State_Type := b"0001"; -constant State_Execute : State_Type := b"0010"; -constant State_StoreToStack : State_Type := b"0011"; -constant State_Add : State_Type := b"0100"; -constant State_Or : State_Type := b"0101"; -constant State_And : State_Type := b"0110"; -constant State_Store : State_Type := b"0111"; -constant State_ReadIO : State_Type := b"1000"; -constant State_WriteIO : State_Type := b"1001"; -constant State_Load : State_Type := b"1010"; -constant State_FetchNext : State_Type := b"1011"; -constant State_AddSP : State_Type := b"1100"; -constant State_ReadIODone : State_Type := b"1101"; -constant State_Decode : State_Type := b"1110"; -constant State_Resync : State_Type := b"1111"; - - -subtype DecodedOpcodeType is std_logic_vector(4 downto 0); -constant Decoded_Nop : DecodedOpcodeType := b"00000"; -constant Decoded_Im : DecodedOpcodeType := b"00001"; -constant Decoded_ImShift : DecodedOpcodeType := b"00010"; -constant Decoded_LoadSP : DecodedOpcodeType := b"00011"; -constant Decoded_StoreSP : DecodedOpcodeType := b"00100"; -constant Decoded_AddSP : DecodedOpcodeType := b"00101"; -constant Decoded_Emulate : DecodedOpcodeType := b"00110"; -constant Decoded_Break : DecodedOpcodeType := b"00111"; -constant Decoded_PushPC : DecodedOpcodeType := b"01000"; -constant Decoded_PushSP : DecodedOpcodeType := b"01001"; -constant Decoded_PopPC : DecodedOpcodeType := b"01010"; -constant Decoded_Add : DecodedOpcodeType := b"01011"; -constant Decoded_Or : DecodedOpcodeType := b"01100"; -constant Decoded_And : DecodedOpcodeType := b"01101"; -constant Decoded_Load : DecodedOpcodeType := b"01110"; -constant Decoded_Not : DecodedOpcodeType := b"01111"; -constant Decoded_Flip : DecodedOpcodeType := b"10000"; -constant Decoded_Store : DecodedOpcodeType := b"10001"; -constant Decoded_PopSP : DecodedOpcodeType := b"10010"; - -signal opcode : std_logic_vector(OpCode_Size-1 downto 0); - -signal decodedOpcode : DecodedOpcodeType; - -signal state : State_Type; - -begin - traceFileGenerate: - if Generate_Trace generate - trace_file: trace port map ( - clk => clk, - begin_inst => begin_inst, - pc => trace_pc, - opcode => trace_opcode, - sp => trace_sp, - memA => trace_topOfStack, - memB => trace_topOfStackB, - busy => busy - ); - end generate; - - - memory: dualport_ram port map ( - clk => clk, - memAWriteEnable => memAWriteEnable, - memAAddr => memAAddr, - memAWrite => memAWrite, - memARead => memARead, - memBWriteEnable => memBWriteEnable, - memBAddr => memBAddr, - memBWrite => memBWrite, - memBRead => memBRead - ); - - - - - opcodeControl: - process(clk, areset) - variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); - variable spOffset : std_logic_vector(4 downto 0); - begin - if areset = '1' then - state <= State_Resync; - break <= '0'; - sp <= (2 => '0', others => '1'); - pc <= (others => '0'); - idim_flag <= '0'; - begin_inst <= '0'; - memAAddr <= (others => '0'); - memBAddr <= (others => '0'); - memAWriteEnable <= '0'; - memBWriteEnable <= '0'; - io_writeEnable <= '0'; - io_readEnable <= '0'; - decodedOpcode <= (others => '0'); - memAWrite <= (others => '0'); - memBWrite <= (others => '0'); - opcode <= (others => '0'); - io_addr <= (others => '0'); - io_write <= (others => '0'); - elsif (clk'event and clk = '1') then - memAWriteEnable <= '0'; - memBWriteEnable <= '0'; - -- This saves ca. 100 LUT's, by explicitly declaring that the - -- memAWrite can be left at whatever value if memAWriteEnable is - -- not set. - memAWrite <= (others => DontCareValue); - memBWrite <= (others => DontCareValue); - opcode <= (others => DontCareValue); --- io_addr <= (others => DontCareValue); --- io_write <= (others => DontCareValue); - spOffset := (others => DontCareValue); - memAAddr <= (others => DontCareValue); - memBAddr <= (others => DontCareValue); - - io_writeEnable <= '0'; - io_readEnable <= '0'; - begin_inst <= '0'; - - case state is - when State_Execute => - state <= State_Fetch; - -- at this point: - -- memBRead contains opcode word - -- memARead contains top of stack - pc <= pc + 1; - - -- trace - begin_inst <= '1'; - trace_pc <= pc; - trace_opcode <= opcode; - trace_sp <= sp; - trace_topOfStack <= memARead; - trace_topOfStackB <= memBRead; - - -- during the next cycle we'll be reading the next opcode - spOffset(4):=not opcode(4); - spOffset(3 downto 0):=opcode(3 downto 0); - - case decodedOpcode is - when Decoded_Im => - memAWriteEnable <= '1'; - sp <= sp - 1; - memAAddr <= sp-1; - for i in wordSize-1 downto 7 loop - memAWrite(i) <= opcode(6); - end loop; - memAWrite(6 downto 0) <= opcode(6 downto 0); - when Decoded_ImShift => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0); - memAWrite(6 downto 0) <= opcode(6 downto 0); - when Decoded_StoreSP => - memBWriteEnable <= '1'; - memBAddr <= sp+spOffset; - memBWrite <= memARead; - sp <= sp + 1; - state <= State_Resync; - when Decoded_LoadSP => - sp <= sp - 1; - memAAddr <= sp+spOffset; - when Decoded_Emulate => - sp <= sp - 1; - memAWriteEnable <= '1'; - memAAddr <= sp - 1; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto 0) <= pc + 1; - -- The emulate address is: - -- 98 7654 3210 - -- 0000 00aa aaa0 0000 - pc <= (others => '0'); - pc(9 downto 5) <= opcode(4 downto 0); - when Decoded_AddSP => - memAAddr <= sp; - memBAddr <= sp+spOffset; - state <= State_AddSP; - when Decoded_Break => - report "Break instruction encountered" severity failure; - break <= '1'; - when Decoded_PushSP => - memAWriteEnable <= '1'; - memAAddr <= sp - 1; - sp <= sp - 1; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto minAddrBit) <= sp; - when Decoded_PopPC => - pc <= memARead(maxAddrBit downto 0); - sp <= sp + 1; - state <= State_Resync; - when Decoded_Add => - sp <= sp + 1; - state <= State_Add; - when Decoded_Or => - sp <= sp + 1; - state <= State_Or; - when Decoded_And => - sp <= sp + 1; - state <= State_And; - when Decoded_Load => - if (memARead(ioBit)='1') then - io_addr <= memARead(maxAddrBit downto minAddrBit); - io_readEnable <= '1'; - state <= State_ReadIO; - else - memAAddr <= memARead(maxAddrBit downto minAddrBit); - end if; - when Decoded_Not => - memAAddr <= sp(maxAddrBit downto minAddrBit); - memAWriteEnable <= '1'; - memAWrite <= not memARead; - when Decoded_Flip => - memAAddr <= sp(maxAddrBit downto minAddrBit); - memAWriteEnable <= '1'; - for i in 0 to wordSize-1 loop - memAWrite(i) <= memARead(wordSize-1-i); - end loop; - when Decoded_Store => - memBAddr <= sp + 1; - sp <= sp + 1; - if (memARead(ioBit)='1') then - state <= State_WriteIO; - else - state <= State_Store; - end if; - when Decoded_PopSP => - sp <= memARead(maxAddrBit downto minAddrBit); - state <= State_Resync; - when Decoded_Nop => - memAAddr <= sp; - when others => - null; - end case; - when State_ReadIO => - if (io_busy = '0') then - state <= State_Fetch; - memAWriteEnable <= '1'; - memAWrite <= (others => '0'); - memAWrite(7 downto 0) <= io_read; - end if; - when State_WriteIO => - sp <= sp + 1; - io_writeEnable <= '1'; - io_addr <= memARead(maxAddrBit downto minAddrBit); - io_write <= memBRead(7 downto 0); - state <= State_WriteIODone; - when State_WriteIODone => - if (io_busy = '0') then - state <= State_Resync; - end if; - when State_Fetch => - -- We need to resync. During the *next* cycle - -- we'll fetch the opcode @ pc and thus it will - -- be available for State_Execute the cycle after - -- next - memBAddr <= pc(maxAddrBit downto minAddrBit); - state <= State_FetchNext; - when State_FetchNext => - -- at this point memARead contains the value that is either - -- from the top of stack or should be copied to the top of the stack - memAWriteEnable <= '1'; - memAWrite <= memARead; - memAAddr <= sp; - memBAddr <= sp + 1; - state <= State_Decode; - when State_Decode => - case pc(1 downto 0) is - when "00" => tOpcode := memBRead(31 downto 24); - when "01" => tOpcode := memBRead(23 downto 16); - when "10" => tOpcode := memBRead(15 downto 8); - when others => tOpcode := memBRead(7 downto 0); - end case; - idim_flag <= tOpcode(7); - opcode <= tOpcode; - if (tOpcode(7 downto 7)=OpCode_Im) then - if (idim_flag='1') then - decodedOpcode<=Decoded_ImShift; - else - decodedOpcode<=Decoded_Im; - end if; - elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then - decodedOpcode<=Decoded_StoreSP; - elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then - decodedOpcode<=Decoded_LoadSP; - elsif (tOpcode(7 downto 5)=OpCode_Emulate) then - decodedOpcode<=Decoded_Emulate; - elsif (tOpcode(7 downto 4)=OpCode_AddSP) then - decodedOpcode<=Decoded_AddSP; - else - case tOpcode(3 downto 0) is - when OpCode_Break => - decodedOpcode<=Decoded_Break; - when OpCode_PushSP => - decodedOpcode<=Decoded_PushSP; - when OpCode_PopPC => - decodedOpcode<=Decoded_PopPC; - when OpCode_Add => - decodedOpcode<=Decoded_Add; - when OpCode_Or => - decodedOpcode<=Decoded_Or; - when OpCode_And => - decodedOpcode<=Decoded_And; - when OpCode_Load => - decodedOpcode<=Decoded_Load; - when OpCode_Not => - decodedOpcode<=Decoded_Not; - when OpCode_Flip => - decodedOpcode<=Decoded_Flip; - when OpCode_Store => - decodedOpcode<=Decoded_Store; - when OpCode_PopSP => - decodedOpcode<=Decoded_PopSP; - when others => - decodedOpcode<=Decoded_Nop; - end case; - end if; - -- during the State_Execute cycle we'll be fetching SP+1 - memAAddr <= sp; - memBAddr <= sp + 1; - state <= State_Execute; - when State_Store => - sp <= sp + 1; - memAWriteEnable <= '1'; - memAAddr <= memARead(maxAddrBit downto minAddrBit); - memAWrite <= memBRead; - state <= State_Resync; - when State_AddSP => - state <= State_Add; - when State_Add => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead + memBRead; - state <= State_Fetch; - when State_Or => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead or memBRead; - state <= State_Fetch; - when State_Resync => - memAAddr <= sp; - state <= State_Fetch; - when State_And => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead and memBRead; - state <= State_Fetch; - when others => - null; - end case; - end if; - end process; - - - -end behave; diff --git a/zpu/hdl/zpu3/src/zpu_top_medium.vhd b/zpu/hdl/zpu3/src/zpu_top_medium.vhd deleted file mode 100644 index 4896b30..0000000 --- a/zpu/hdl/zpu3/src/zpu_top_medium.vhd +++ /dev/null @@ -1,768 +0,0 @@ --- Company: ZPU3 --- Engineer: Øyvind Harboe - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -use IEEE.STD_LOGIC_arith.ALL; - -library zylin; -use zylin.zpu_config.all; -use zylin.zpupkg.all; - - -entity zpu_top is - Port ( clk : in std_logic; - areset : in std_logic; - io_busy : in std_logic; - io_read : in std_logic_vector(7 downto 0); - io_write : out std_logic_vector(7 downto 0); - io_addr : out std_logic_vector(maxAddrBit downto minAddrBit); - io_writeEnable : out std_logic; - io_readEnable : out std_logic; - interrupt : in std_logic; - break : out std_logic); -end zpu_top; - -architecture behave of zpu_top is - -signal readIO : std_logic; - - - -signal memAWriteEnable : std_logic; -signal memAAddr : std_logic_vector(maxAddrBit downto minAddrBit); -signal memAWrite : std_logic_vector(wordSize-1 downto 0); -signal memARead : std_logic_vector(wordSize-1 downto 0); -signal memBWriteEnable : std_logic; -signal memBAddr : std_logic_vector(maxAddrBit downto minAddrBit); -signal memBWrite : std_logic_vector(wordSize-1 downto 0); -signal memBRead : std_logic_vector(wordSize-1 downto 0); - - - -signal pc : std_logic_vector(maxAddrBit downto 0); -signal sp : std_logic_vector(maxAddrBit downto minAddrBit); - -signal idim_flag : std_logic; - ---signal storeToStack : std_logic; ---signal fetchNextInstruction : std_logic; ---signal extraCycle : std_logic; -signal busy : std_logic; ---signal fetching : std_logic; - -signal begin_inst : std_logic; - - - -signal trace_opcode : std_logic_vector(7 downto 0); -signal trace_pc : std_logic_vector(maxAddrBit downto 0); -signal trace_sp : std_logic_vector(maxAddrBit downto minAddrBit); -signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); - --- state machine. - -subtype State_Type is std_logic_vector(4 downto 0); -constant State_ResyncDecode : State_Type := b"00000"; -constant State_WriteIODone : State_Type := b"00001"; -constant State_Execute : State_Type := b"00010"; -constant State_StoreToStack : State_Type := b"00011"; -constant State_Add : State_Type := b"00100"; -constant State_Or : State_Type := b"00101"; -constant State_And : State_Type := b"00110"; -constant State_Store : State_Type := b"00111"; -constant State_ReadIO : State_Type := b"01000"; -constant State_WriteIO : State_Type := b"01001"; -constant State_Load : State_Type := b"01010"; -constant State_ResyncStack : State_Type := b"01011"; -constant State_AddSP : State_Type := b"01100"; -constant State_ReadIODone : State_Type := b"01101"; -constant State_Decode : State_Type := b"01110"; -constant State_LoadByte1 : State_Type := b"01111"; -constant State_LoadByte2 : State_Type := b"10000"; -constant State_StoreByte1 : State_Type := b"10001"; -constant State_StoreByte2 : State_Type := b"10010"; -constant State_Mult1 : State_Type := b"10011"; -constant State_Mult2 : State_Type := b"10100"; -constant State_Mult3 : State_Type := b"10101"; - - -subtype DecodedOpcodeType is std_logic_vector(5 downto 0); -constant Decoded_Nop : DecodedOpcodeType := b"000000"; -constant Decoded_Im : DecodedOpcodeType := b"000001"; -constant Decoded_ImShift : DecodedOpcodeType := b"000010"; -constant Decoded_LoadSP : DecodedOpcodeType := b"000011"; -constant Decoded_StoreSP : DecodedOpcodeType := b"000100"; -constant Decoded_AddSP : DecodedOpcodeType := b"000101"; -constant Decoded_Emulate : DecodedOpcodeType := b"000110"; -constant Decoded_Break : DecodedOpcodeType := b"000111"; -constant Decoded_PushPC : DecodedOpcodeType := b"001000"; -constant Decoded_PushSP : DecodedOpcodeType := b"001001"; -constant Decoded_PopPC : DecodedOpcodeType := b"001010"; -constant Decoded_Add : DecodedOpcodeType := b"001011"; -constant Decoded_Or : DecodedOpcodeType := b"001100"; -constant Decoded_And : DecodedOpcodeType := b"001101"; -constant Decoded_Load : DecodedOpcodeType := b"001110"; -constant Decoded_Not : DecodedOpcodeType := b"001111"; -constant Decoded_Flip : DecodedOpcodeType := b"010000"; -constant Decoded_Store : DecodedOpcodeType := b"010001"; -constant Decoded_PopSP : DecodedOpcodeType := b"010010"; -constant Decoded_Ashiftleft : DecodedOpcodeType := b"010011"; -constant Decoded_Ashiftright : DecodedOpcodeType := b"010100"; -constant Decoded_Lshiftright : DecodedOpcodeType := b"010101"; -constant Decoded_Eqbranch : DecodedOpcodeType := b"010110"; -constant Decoded_Neqbranch : DecodedOpcodeType := b"010111"; -constant Decoded_Eq : DecodedOpcodeType := b"011000"; -constant Decoded_Neq : DecodedOpcodeType := b"011001"; -constant Decoded_Loadb : DecodedOpcodeType := b"011010"; -constant Decoded_Lessthan : DecodedOpcodeType := b"011011"; -constant Decoded_Lessthanorequal : DecodedOpcodeType := b"011100"; -constant Decoded_Ulessthan : DecodedOpcodeType := b"011101"; -constant Decoded_Ulessthanorequal : DecodedOpcodeType := b"011110"; -constant Decoded_Storeb : DecodedOpcodeType := b"011111"; -constant Decoded_Lshift2 : DecodedOpcodeType := b"100000"; -constant Decoded_DoubleIm : DecodedOpcodeType := b"100001"; -constant Decoded_AddIm : DecodedOpcodeType := b"100011"; -constant Decoded_Mult16x16 : DecodedOpcodeType := b"100100"; -constant Decoded_Swap : DecodedOpcodeType := b"100101"; -constant Decoded_Callpcrel : DecodedOpcodeType := b"100110"; -constant Decoded_Pushspadd : DecodedOpcodeType := b"100111"; - - -signal mult1 : std_logic_vector(wordSize/2-1 downto 0); -signal mult2 : std_logic_vector(wordSize/2-1 downto 0); -signal multResult : std_logic_vector(wordSize-1 downto 0); - -signal storeByte : std_logic_vector(7 downto 0); -signal byteSelect : std_logic_vector(minAddrBit-1 downto 0); - -signal opcode : std_logic_vector(OpCode_Size-1 downto 0); -signal opcode2 : std_logic_vector(OpCode_Size-1 downto 0); - -signal decodedOpcode : DecodedOpcodeType; - -signal state : State_Type; - -begin - traceFileGenerate: - if Generate_Trace generate - trace_file: trace port map ( - clk => clk, - begin_inst => begin_inst, - pc => trace_pc, - opcode => trace_opcode, - sp => trace_sp, - memA => trace_topOfStack, - busy => busy - ); - end generate; - - - memory: dualport_ram port map ( - clk => clk, - memAWriteEnable => memAWriteEnable, - memAAddr => memAAddr, - memAWrite => memAWrite, - memARead => memARead, - memBWriteEnable => memBWriteEnable, - memBAddr => memBAddr, - memBWrite => memBWrite, - memBRead => memBRead - ); - - - process(clk, areset) - begin - if (clk'event and clk = '1') then - multResult <= mult1 * mult2; - end if; - end process; - - - - opcodeControl: - process(clk, areset) - variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); - variable tOpcode2 : std_logic_vector(OpCode_Size-1 downto 0); - variable spOffset : std_logic_vector(4 downto 0); - variable spOffset2 : std_logic_vector(4 downto 0); - variable nextPC : std_logic_vector(maxAddrBit downto 0); - variable pushspaddTemp : std_logic_vector(maxAddrBit downto minAddrBit); - variable tempVal : std_logic_vector(wordSize-1 downto 0); - variable compareA : signed(wordSize-1 downto 0); - variable compareB : signed(wordSize-1 downto 0); - begin - if areset = '1' then - mult1 <= (others => '0'); - mult2 <= (others => '0'); - state <= State_ResyncDecode; - break <= '0'; - sp <= (2 => '0', others => '1'); - pc <= (others => '0'); - idim_flag <= '0'; - begin_inst <= '0'; - memAAddr <= (others => '0'); - memBAddr <= (others => '0'); - memAWriteEnable <= '0'; - memBWriteEnable <= '0'; - io_writeEnable <= '0'; - io_readEnable <= '0'; - decodedOpcode <= (others => '0'); - memAWrite <= (others => '0'); - memBWrite <= (others => '0'); - opcode <= (others => '0'); - io_addr <= (others => '0'); - io_write <= (others => '0'); - elsif (clk'event and clk = '1') then - memAWriteEnable <= '0'; - memBWriteEnable <= '0'; - - io_writeEnable <= '0'; - io_readEnable <= '0'; - begin_inst <= '0'; - - case state is - when State_Decode => - nextPC:=pc+1; - case pc(1 downto 0) is - when "00" => tOpcode := memARead(31 downto 24); - when "01" => tOpcode := memARead(23 downto 16); - when "10" => tOpcode := memARead(15 downto 8); - when others => tOpcode := memARead(7 downto 0); - end case; - case nextPC(1 downto 0) is - when "00" => tOpcode2 := memBRead(31 downto 24); - when "01" => tOpcode2 := memBRead(23 downto 16); - when "10" => tOpcode2 := memBRead(15 downto 8); - when others => tOpcode2 := memBRead(7 downto 0); - end case; - idim_flag <= tOpcode(7); - opcode <= tOpcode; - opcode2 <= tOpcode2; - if (tOpcode(7 downto 7)=OpCode_Im and tOpcode2(7 downto 4)=0 and tOpcode2(3 downto 0)=Opcode_Add and idim_flag='0') then - idim_flag <= '0'; - decodedOpcode <= Decoded_AddIm; - nextPC := pc + 2; - elsif (tOpcode(7 downto 7)=OpCode_Im and tOpcode2(7 downto 7)=OpCode_Im and idim_flag='0') then - decodedOpcode <= Decoded_DoubleIm; - nextPC := pc + 2; - elsif (tOpcode(7 downto 4)=OpCode_AddSP and tOpcode(3 downto 0)=0 and - tOpcode2(7 downto 4)=OpCode_AddSP and tOpcode2(3 downto 0)=0) then - decodedOpcode <= Decoded_Lshift2; - nextPC := pc + 2; - elsif (tOpcode(7 downto 7)=OpCode_Im) then - if (idim_flag='1') then - decodedOpcode<=Decoded_ImShift; - else - decodedOpcode<=Decoded_Im; - end if; - elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then - decodedOpcode<=Decoded_StoreSP; - elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then - decodedOpcode<=Decoded_LoadSP; - elsif (tOpcode(7 downto 5)=OpCode_Emulate) then - if tOpcode(5 downto 0)=OpCode_Eqbranch then - decodedOpcode <= Decoded_Eqbranch; - elsif tOpcode(5 downto 0)=OpCode_Neqbranch then - decodedOpcode <= Decoded_Neqbranch; - elsif tOpcode(5 downto 0)=OpCode_Eq then - decodedOpcode <= Decoded_Eq; - elsif tOpcode(5 downto 0)=OpCode_Neq then - decodedOpcode <= Decoded_Neq; - elsif tOpcode(5 downto 0)=OpCode_Lessthan then - decodedOpcode <= Decoded_Lessthan; - elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then - decodedOpcode <= Decoded_Lessthanorequal; - elsif tOpcode(5 downto 0)=OpCode_Ulessthan then - decodedOpcode <= Decoded_Ulessthan; - elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then - decodedOpcode <= Decoded_Ulessthanorequal; - elsif tOpcode(5 downto 0)=OpCode_Loadb then - decodedOpcode <= Decoded_Loadb; - elsif tOpcode(5 downto 0)=OpCode_Storeb then - decodedOpcode <= Decoded_Storeb; - elsif tOpcode(5 downto 0)=OpCode_Mult16x16 then - decodedOpcode <= Decoded_Mult16x16; - elsif tOpcode(5 downto 0)=OpCode_Swap then - decodedOpcode <= Decoded_Swap; - elsif tOpcode(5 downto 0)=OpCode_Callpcrel then - decodedOpcode <= Decoded_Callpcrel; - elsif tOpcode(5 downto 0)=OpCode_Pushspadd then - decodedOpcode <= Decoded_Pushspadd; --- elsif tOpcode(5 downto 0)=OpCode_Lshiftright then --- decodedOpcode <= Decoded_Lshiftright; --- elsif tOpcode(5 downto 0)=OpCode_Ashiftleft then --- decodedOpcode <= Decoded_Ashiftleft; --- elsif tOpcode(5 downto 0)=OpCode_Ashiftright then --- decodedOpcode <= Decoded_Ashiftright; - else - decodedOpcode<=Decoded_Emulate; - end if; - elsif (tOpcode(7 downto 4)=OpCode_AddSP) then - decodedOpcode<=Decoded_AddSP; - else - case tOpcode(3 downto 0) is - when OpCode_Break => - decodedOpcode<=Decoded_Break; - when OpCode_PushPC => - decodedOpcode<=Decoded_PushPC; - when OpCode_PushSP => - decodedOpcode<=Decoded_PushSP; - when OpCode_PopPC => - decodedOpcode<=Decoded_PopPC; - when OpCode_Add => - decodedOpcode<=Decoded_Add; - when OpCode_Or => - decodedOpcode<=Decoded_Or; - when OpCode_And => - decodedOpcode<=Decoded_And; - when OpCode_Load => - decodedOpcode<=Decoded_Load; - when OpCode_Not => - decodedOpcode<=Decoded_Not; - when OpCode_Flip => - decodedOpcode<=Decoded_Flip; - when OpCode_Store => - decodedOpcode<=Decoded_Store; - when OpCode_PopSP => - decodedOpcode<=Decoded_PopSP; - when others => - decodedOpcode<=Decoded_Nop; - end case; - end if; - -- Fetch the two next opcodes... :-) - memAAddr <= nextPC(maxAddrBit downto minAddrBit); - nextPC:=nextPC+1; - memBAddr <= nextPC(maxAddrBit downto minAddrBit); - state <= State_Execute; - when State_Execute => - state <= State_Decode; - -- at this point: - -- memBRead contains opcode word - -- memARead contains top of stack - pc <= pc + 1; - - -- trace - begin_inst <= '1'; - trace_pc <= pc; - trace_opcode <= opcode; - trace_sp <= sp; - trace_topOfStack <= memARead; - - -- during the next cycle we'll be reading the next opcode - spOffset(4):=not opcode(4); - spOffset(3 downto 0):=opcode(3 downto 0); - spOffset2(4):=not opcode2(4); - spOffset2(3 downto 0):=opcode2(3 downto 0); - - case decodedOpcode is - - when Decoded_DoubleIm => - memAWriteEnable <= '1'; - sp <= sp - 1; - memAAddr <= sp-1; - for i in wordSize-1 downto 14 loop - memAWrite(i) <= opcode(6); - end loop; - memAWrite(13 downto 7) <= opcode(6 downto 0); - memAWrite(6 downto 0) <= opcode2(6 downto 0); - memBAddr <= sp; - memBWrite <= memARead; - memBWriteEnable <= '1'; - pc <= pc + 2; - when Decoded_Im => - memAWriteEnable <= '1'; - sp <= sp - 1; - memAAddr <= sp-1; - for i in wordSize-1 downto 7 loop - memAWrite(i) <= opcode(6); - end loop; - memAWrite(6 downto 0) <= opcode(6 downto 0); - memBAddr <= sp; - memBWrite <= memARead; - memBWriteEnable <= '1'; - when Decoded_ImShift => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0); - memAWrite(6 downto 0) <= opcode(6 downto 0); - memBAddr <= sp + 1; - when Decoded_StoreSP => - memAWriteEnable <= '1'; - memAAddr <= sp+spOffset; - memAWrite <= memARead; - -- avoid address crashes. - memBAddr <= sp - 1; - sp <= sp + 1; - state <= State_ResyncDecode; - when Decoded_LoadSP => - sp <= sp - 1; - if (spOffset = 0) then - -- This is a duplicate instruction. - memAAddr <= sp-1; - memAWriteEnable <= '1'; - memAWrite <= memARead; - else - memAAddr <= sp+spOffset; - end if; - memBAddr <= sp; - memBWrite <= memARead; - memBWriteEnable <= '1'; - when Decoded_Callpcrel => - memAWriteEnable <= '1'; - memAAddr <= sp; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto 0) <= pc + 1; - memBAddr <= sp+1; - pc <= pc + memARead(maxAddrBit downto 0); - state <= State_ResyncDecode; - when Decoded_Emulate => - sp <= sp - 1; - memAWriteEnable <= '1'; - memAAddr <= sp - 1; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto 0) <= pc; - memBAddr <= sp; - memBWrite <= memARead; - memBWriteEnable <= '1'; - -- The emulate address is: - -- 98 7654 3210 - -- 0000 00aa aaa0 0000 - pc <= (others => '0'); - pc(9 downto 5) <= opcode(4 downto 0); - state <= State_ResyncDecode; - when Decoded_AddSP => - if spOffset=0 then - -- avoid address line crashes... - -- FIX!!! is this an issue? - -- oh-well. While we are at it, we've got a faster - -- shift operation without updating the toolchain. - memAWriteEnable <= '1'; - memAAddr <= sp; - memAWrite <= memARead + memARead; - memBAddr <= sp+1; - else - memAWriteEnable <= '1'; - memAAddr <= sp; - memAWrite <= memARead; - memBAddr <= sp+spOffset; - state <= State_AddSP; - end if; - when Decoded_Break => - report "Break instruction encountered" severity failure; - break <= '1'; - when Decoded_PushPC => - memAWriteEnable <= '1'; - memAAddr <= sp - 1; - sp <= sp - 1; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto 0) <= pc; - memBAddr <= sp; - memBWrite <= memARead; - memBWriteEnable <= '1'; - when Decoded_PushSP => - memAWriteEnable <= '1'; - memAAddr <= sp - 1; - sp <= sp - 1; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto minAddrBit) <= sp; - memBAddr <= sp; - memBWrite <= memARead; - memBWriteEnable <= '1'; - when Decoded_Pushspadd => - memAWriteEnable <= '1'; - memAAddr <= sp; - memAWrite <= (others => DontCareValue); - pushspaddTemp := memARead(maxAddrBit-minAddrBit downto 0); - memAWrite(maxAddrBit downto minAddrBit) <= sp+pushspaddTemp; - memBAddr <= sp+1; - when Decoded_PopPC => - memAAddr <= sp; - pc <= memARead(maxAddrBit downto 0); - sp <= sp + 1; - state <= State_ResyncDecode; - when Decoded_AddIm => - memAWriteEnable <= '1'; - memAAddr <= sp; - tempVal(wordSize-1 downto 7) := (others => tOpcode(6)); - tempVal(6 downto 0) := tOpcode(6 downto 0); - memAWrite <= memARead + tempVal; - memBAddr <= sp + 1; - pc <= pc + 2; - when Decoded_Add => - memAWriteEnable <= '1'; - memAWrite <= memARead + memBRead; - memAAddr <= sp + 1; - memBAddr <= sp + 2; - sp <= sp + 1; - when Decoded_Or => - sp <= sp + 1; - memAWriteEnable <= '1'; - memAWrite <= memARead or memBRead; - memAWriteEnable <= '1'; - memAAddr <= sp + 1; - memBAddr <= sp + 2; - when Decoded_And => - sp <= sp + 1; - memAWriteEnable <= '1'; - memAWrite <= memARead and memBRead; - memAWriteEnable <= '1'; - memAAddr <= sp + 1; - memBAddr <= sp + 2; - when Decoded_Load => - if (memARead(ioBit)='1') then - io_addr <= memARead(maxAddrBit downto minAddrBit); - io_readEnable <= '1'; - state <= State_ReadIO; - else - memAAddr <= memARead(maxAddrBit downto minAddrBit); - memBAddr <= sp + 1; - end if; - when Decoded_Swap => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite(wordSize/2-1 downto 0) <= memARead(wordSize-1 downto wordSize/2); - memAWrite(wordSize-1 downto wordSize/2) <= memARead(wordSize/2-1 downto 0); - memBAddr <= sp + 1; - when Decoded_Not => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= not memARead; - memBAddr <= sp + 1; - when Decoded_Flip => - memAAddr <= sp; - memAWriteEnable <= '1'; - for i in 0 to wordSize-1 loop - memAWrite(i) <= memARead(wordSize-1-i); - end loop; - memBAddr <= sp + 1; - when Decoded_Lshift2 => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite(1 downto 0) <= (others => '0'); - memAWrite(wordSize-1 downto 2) <= memARead(wordSize-1-2 downto 0); - memBAddr <= sp + 1; - pc <= pc + 2; - when Decoded_Store => - sp <= sp + 2; - if (memARead(ioBit)='1') then - io_writeEnable <= '1'; - io_addr <= memARead(maxAddrBit downto minAddrBit); - io_write <= memBRead(7 downto 0); - state <= State_WriteIO; - else - memAWriteEnable <= '1'; - memAAddr <= memARead(maxAddrBit downto minAddrBit); - memAWrite <= memBRead; - state <= State_ResyncDecode; - end if; - when Decoded_PopSP => - sp <= memARead(maxAddrBit downto minAddrBit); - state <= State_ResyncDecode; - when Decoded_Ashiftleft => - memAWrite(wordSize-1 downto conv_integer(memARead(wordPower-1 downto 0))) <= - memBRead(wordSize-conv_integer(memARead(wordPower-1 downto 0))-1 downto 0); - if memARead(wordPower-1 downto 0)/=0 then - memAWrite(conv_integer(memARead(wordPower-1 downto 0))-1 downto 0) <= (others => '0'); - end if; - memAWriteEnable <= '1'; - memAAddr <= sp + 1; - memBAddr <= sp + 2; - sp <= sp + 1; - when Decoded_Ashiftright | Decoded_Lshiftright => - memAWrite(wordSize-1-conv_integer(memARead(wordPower-1 downto 0)) downto 0) <= - memBRead(wordSize-1 downto conv_integer(memARead(wordPower-1 downto 0))); - if memARead(wordPower-1 downto 0)/=0 then - if decodedOpcode=Decoded_Ashiftright and memBRead(wordSize-1)='1' then - memAWrite(wordSize-1 downto wordSize-conv_integer(memARead(wordPower-1 downto 0))-1) <= (others => '1'); - else - memAWrite(wordSize-1 downto wordSize-conv_integer(memARead(wordPower-1 downto 0))-1) <= (others => '0'); - end if; - end if; - memAWriteEnable <= '1'; - memAAddr <= sp + 1; - memBAddr <= sp + 2; - sp <= sp + 1; - when Decoded_Eqbranch => - sp <= sp + 2; - if (memBRead=0) then - pc <= memARead(maxAddrBit downto 0) + pc; - end if; - state <= State_ResyncDecode; - when Decoded_Neqbranch => - sp <= sp + 2; - if (memBRead/=0) then - pc <= memARead(maxAddrBit downto 0) + pc; - end if; - state <= State_ResyncDecode; - when Decoded_Eq => - sp <= sp + 1; - memAWrite <= (others => '0'); - if (memARead=memBRead) then - memAWrite(0) <= '1'; - end if; - memAAddr <= sp + 1; - memAWriteEnable <= '1'; - memBAddr <= sp + 2; - when Decoded_Neq => - sp <= sp + 1; - memAWrite <= (others => '0'); - if (memARead/=memBRead) then - memAWrite(0) <= '1'; - end if; - memAAddr <= sp + 1; - memAWriteEnable <= '1'; - memBAddr <= sp + 2; - when Decoded_Ulessthan => - sp <= sp + 1; - memAWrite <= (others => '0'); - if (memARead - sp <= sp + 1; - memAWrite <= (others => '0'); - if (memARead<=memBRead) then - memAWrite(0) <= '1'; - end if; - memAAddr <= sp + 1; - memAWriteEnable <= '1'; - memBAddr <= sp + 2; - when Decoded_Lessthan => - sp <= sp + 1; - memAWrite <= (others => '0'); - compareA := signed(memARead); - compareB := signed(memBRead); - if (compareA - sp <= sp + 1; - memAWrite <= (others => '0'); - compareA := signed(memARead); - compareB := signed(memBRead); - if (compareA<=compareB) then - memAWrite(0) <= '1'; - end if; - memAAddr <= sp + 1; - memAWriteEnable <= '1'; - memBAddr <= sp + 2; - when Decoded_Loadb => - byteSelect <= memARead(minAddrBit-1 downto 0); - memAAddr <= memARead(maxAddrBit downto minAddrBit); - state <= State_LoadByte1; - when Decoded_Storeb => - sp <= sp + 2; - byteSelect <= memARead(minAddrBit-1 downto 0); - storeByte <= memBRead(7 downto 0); - memAAddr <= memARead(maxAddrBit downto minAddrBit); - memBAddr <= sp; - state <= State_StoreByte1; - when Decoded_Mult16x16 => - mult1 <= memARead(wordSize/2-1 downto 0); - mult2 <= memBRead(wordSize/2-1 downto 0); - sp <= sp + 1; - state <= State_Mult1; - when others => - -- nop. Here we persist whatever was loaded into - -- memARead - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead; - memBAddr <= sp + 1; - - end case; - when State_ReadIO => - state <= State_ReadIODone; - when State_ReadIODone => - if (io_busy = '0') then - state <= State_ResyncDecode; - memAWriteEnable <= '1'; - memAWrite <= (others => '0'); - memAWrite(7 downto 0) <= io_read; - memAAddr <= sp; - end if; - when State_WriteIO => - state <= State_WriteIODone; - when State_WriteIODone => - if (io_busy = '0') then - state <= State_ResyncDecode; - end if; - when State_ResyncDecode => - memAAddr <= pc(maxAddrBit downto minAddrBit); - nextPC:=pc+1; - memBAddr <= nextPC(maxAddrBit downto minAddrBit); - state <= State_ResyncStack; - when State_ResyncStack => - memAAddr <= sp; - memBAddr <= sp+1; - state <= State_Decode; - when State_AddSP => - memAAddr <= pc(maxAddrBit downto minAddrBit); - nextPC:=pc+1; - memBAddr <= nextPC(maxAddrBit downto minAddrBit); - state <= State_Add; - when State_Add => - memAWriteEnable <= '1'; - memAWrite <= memARead + memBRead; - memAAddr <= sp; - memBAddr <= sp + 1; - state <= State_Decode; - when State_LoadByte1 => - memAAddr <= pc(maxAddrBit downto minAddrBit); - nextPC:=pc+1; - memBAddr <= nextPC(maxAddrBit downto minAddrBit); - state <= State_LoadByte2; - when State_LoadByte2 => - memAWriteEnable <= '1'; - memAAddr <= sp; - memAWrite <= (others => '0'); - case byteSelect is - when "00" => memAWrite(7 downto 0) <= memARead(31 downto 24); - when "01" => memAWrite(7 downto 0) <= memARead(23 downto 16); - when "10" => memAWrite(7 downto 0) <= memARead(15 downto 8); - when others => memAWrite(7 downto 0) <= memARead(7 downto 0); - end case; - memBAddr <= sp + 1; - state <= State_Decode; - when State_StoreByte1 => - state <= State_StoreByte2; - when State_StoreByte2 => - memAWriteEnable <= '1'; - memAAddr <= memBRead(maxAddrBit downto minAddrBit); - memAWrite <= memARead; - case byteSelect is - when "00" => memAWrite(31 downto 24) <= storeByte; - when "01" => memAWrite(23 downto 16) <= storeByte; - when "10" => memAWrite(15 downto 8) <= storeByte; - when others => memAWrite(7 downto 0) <= storeByte; - end case; - state <= State_ResyncDecode; - when State_Mult1 => - memAAddr <= pc(maxAddrBit downto minAddrBit); - nextPC:=pc+1; - memBAddr <= nextPC(maxAddrBit downto minAddrBit); - state <= State_Mult2; - when State_Mult2 => - memAWriteEnable <= '1'; - memAWrite <= multResult; - memAAddr <= sp; - memBAddr <= sp + 1; - state <= State_Decode; - - when others => - null; - end case; - end if; - end process; - - - -end behave; diff --git a/zpu/hdl/zpu3/src/zpuio.vhd b/zpu/hdl/zpu3/src/zpuio.vhd deleted file mode 100644 index 96e9aea..0000000 --- a/zpu/hdl/zpu3/src/zpuio.vhd +++ /dev/null @@ -1,180 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library zylin; -use zylin.arm7.all; - -library zylin; -use zylin.zpu_config.all; -use zylin.zpupkg.all; - -entity zpuio is - port ( areset : in std_logic; - cpu_clk : in std_logic; - clk_status : in std_logic_vector(2 downto 0); - cpu_din : in std_logic_vector(15 downto 0); - cpu_a : in std_logic_vector(20 downto 0); - cpu_we : in std_logic_vector(1 downto 0); - cpu_re : in std_logic; - cpu_dout : inout std_logic_vector(15 downto 0)); -end zpuio; - -architecture behave of zpuio is - -signal timer_read : std_logic_vector(7 downto 0); ---signal timer_write : std_logic_vector(7 downto 0); -signal timer_we : std_logic; - - -signal io_busy : std_logic; -signal io_read : std_logic_vector(7 downto 0); -signal io_write : std_logic_vector(7 downto 0); -signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit); -signal io_writeEnable : std_logic; -signal io_readEnable : std_logic; - -signal din : std_logic_vector(7 downto 0); -signal dout : std_logic_vector(7 downto 0); -signal adr : std_logic_vector(15 downto 0); -signal break : std_logic; -signal we : std_logic; -signal re : std_logic; - - --- uart forwarding... - -signal uartTXPending : std_logic; -signal uartTXCleared : std_logic; -signal uartData : std_logic_vector(7 downto 0); - -signal readingTimer : std_logic; -begin - - timerinst: timer port map ( - clk => cpu_clk, - areset => areset, - we => timer_we, - din => io_write, - adr => io_addr(4 downto 2), - dout => timer_read); - - zpu: zpu_top port map ( - clk => cpu_clk , - areset => areset, - io_busy => io_busy, - io_writeEnable => io_writeEnable, - io_readEnable => io_readEnable, - io_write => io_write, - io_read => io_read, - io_addr => io_addr, - interrupt => '0' - --, --- break => cpu_fiq_p -); - - - -- Read/write are on different addresses - -- The registers are 8 bits and mapped to bit[7:0] - -- - -- 0xC000 Write: Writes to UART TX FIFO (4 byte FIFO) - -- Read : Reads from UART RX FIFO (4 byte FIFO) - -- 0xC004 Read : UART status register - -- Bit 0 = RX FIFO empty - -- Bit 1 = TX FIFO full - -- 0xA000 Skrive: LED's (8 stk.) - - -- 0x9000 Write: bit 0: 1= reset counter - -- 0= counter running - -- bit 1: 1= sample counter (when set to 1) - -- 0=not used - -- Read : counter bit[7:0] - -- 0x9004 Read: counter bit [15:8] - -- 0x9008 Read: counter bit [23:16] - -- 0x900C Read: counter bit [31:24] - -- 0x9010 Read: counter bit [39:32] - -- 0x9014 Read: counter bit [47:40] - -- 0x9018 Read: counter bit [55:48] - -- 0x901C Read: counter bit [63:56] - -- - -- 0x8800 Read: unsigned 8-bit integer with FPGA frequency (in MHz) - - fauxUart: - process(cpu_clk, areset) - begin - if areset = '1' then - io_busy <= '0'; - uartTXPending <= '0'; - timer_we <= '0'; - io_busy <= '1'; - uartData <= x"58"; -- 'X' - readingTimer <= '0'; - elsif (cpu_clk'event and cpu_clk = '1') then - timer_we <= '0'; - io_busy <= '1'; - if uartTXCleared = '1' then - uartTXPending <= '0'; - end if; - - if io_writeEnable = '1' then - if io_addr=x"1000" then - -- Write to UART - uartData <= io_write; - uartTXPending <= '1'; - io_busy <= '0'; - elsif io_addr(12)='1' then - timer_we <= '1'; - io_busy <= '0'; - else - report "Illegal IO write" severity failure; - end if; - end if; - if (io_readEnable = '1') then - if io_addr=x"1001" then - io_read <= (0=>'1', -- recieve empty - 1 => uartTXPending, -- tx full - others => '0'); - io_busy <= '0'; - elsif io_addr(12)='1' then - readingTimer <= '1'; - io_busy <= '1'; - elsif io_addr(11)='1' then - io_read <= ZPU_Frequency; - io_busy <= '0'; - else - report "Illegal IO read" severity failure; - end if; - - else - if (readingTimer = '1') then - readingTimer <= '0'; - io_read <= timer_read; - io_busy <= '0'; - else - io_read <= (others => '1'); - end if; - end if; - end if; - end process; - - - forwardUARTOutputToARM: - process(cpu_clk, areset) - begin - if areset = '1' then - uartTXCleared <= '0'; - elsif (cpu_clk = '1' and cpu_clk'event) then - if cpu_we(0) = '1' and cpu_a(3 downto 1) = "000" then - uartTXCleared <= cpu_din(0); - else - uartTXCleared <= uartTXCleared; - end if; - end if; - end process; - - cpu_dout(7 downto 0) <= uartData when (cpu_re = '1' and cpu_a(3 downto 1) = "001") else (others => 'Z'); - cpu_dout <= (0 => uartTXPending, others => '0') when (cpu_re = '1' and cpu_a(3 downto 1) = "000") else (others => 'Z'); - - - -end behave; diff --git a/zpu/hdl/zpu3/src/zpupkg.vhd b/zpu/hdl/zpu3/src/zpupkg.vhd deleted file mode 100644 index a904b11..0000000 --- a/zpu/hdl/zpu3/src/zpupkg.vhd +++ /dev/null @@ -1,130 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.STD_LOGIC_ARITH.all; - -library zylin; -use zylin.zpu_config.all; - -package zpupkg is - - component dualport_ram is - port (clk : in std_logic; - memAWriteEnable : in std_logic; - memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit); - memAWrite : in std_logic_vector(wordSize-1 downto 0); - memARead : out std_logic_vector(wordSize-1 downto 0); - memBWriteEnable : in std_logic; - memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit); - memBWrite : in std_logic_vector(wordSize-1 downto 0); - memBRead : out std_logic_vector(wordSize-1 downto 0)); - end component; - - - component trace is - port( - clk : in std_logic; - begin_inst : in std_logic; - pc : in std_logic_vector(maxAddrBit downto 0); - opcode : in std_logic_vector(7 downto 0); - sp : in std_logic_vector(maxAddrBit downto minAddrBit); - memA : in std_logic_vector(wordSize-1 downto 0); - memB : in std_logic_vector(wordSize-1 downto 0); - busy : in std_logic - ); - end component; - - component zpu_top is - Port ( clk : in std_logic; - areset : in std_logic; - io_busy : in std_logic; - io_read : in std_logic_vector(7 downto 0); - io_write : out std_logic_vector(7 downto 0); - io_addr : out std_logic_vector(maxAddrBit downto minAddrBit); - io_writeEnable : out std_logic; - io_readEnable : out std_logic; - interrupt : in std_logic; - break : out std_logic); - end component; - - - component timer is - port( - clk : in std_logic; - areset : in std_logic; - we : in std_logic; - din : in std_logic_vector(7 downto 0); - adr : in std_logic_vector(2 downto 0); - dout : out std_logic_vector(7 downto 0)); - end component; - - - component zpuio is - port ( areset : in std_logic; - cpu_clk : in std_logic; - clk_status : in std_logic_vector(2 downto 0); - cpu_din : in std_logic_vector(15 downto 0); - cpu_a : in std_logic_vector(20 downto 0); - cpu_we : in std_logic_vector(1 downto 0); - cpu_re : in std_logic; - cpu_dout : inout std_logic_vector(15 downto 0)); - end component; - - - -- opcode decode constants - constant OpCode_Im : std_logic_vector(7 downto 7) := "1"; - constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010"; - constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011"; - constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001"; - constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001"; - constant OpCode_Short : std_logic_vector(7 downto 4) := "0000"; - - constant OpCode_Break : std_logic_vector(3 downto 0) := "0000"; - constant OpCode_Shiftleft: std_logic_vector(3 downto 0) := "0001"; - constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010"; - constant OpCode_PushInt : std_logic_vector(3 downto 0) := "0011"; - - constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100"; - constant OpCode_Add : std_logic_vector(3 downto 0) := "0101"; - constant OpCode_And : std_logic_vector(3 downto 0) := "0110"; - constant OpCode_Or : std_logic_vector(3 downto 0) := "0111"; - - constant OpCode_Load : std_logic_vector(3 downto 0) := "1000"; - constant OpCode_Not : std_logic_vector(3 downto 0) := "1001"; - constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010"; - constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011"; - - constant OpCode_Store : std_logic_vector(3 downto 0) := "1100"; - constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101"; - constant OpCode_Compare : std_logic_vector(3 downto 0) := "1110"; - constant OpCode_PopInt : std_logic_vector(3 downto 0) := "1111"; - - constant OpCode_Lessthan : std_logic_vector(5 downto 0) := conv_std_logic_vector(36, 6); - constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := conv_std_logic_vector(37, 6); - constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := conv_std_logic_vector(38, 6); - constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := conv_std_logic_vector(39, 6); - - constant OpCode_Swap : std_logic_vector(5 downto 0) := conv_std_logic_vector(40, 6); - - constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := conv_std_logic_vector(42, 6); - constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := conv_std_logic_vector(43, 6); - constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := conv_std_logic_vector(44, 6); - - constant OpCode_Eq : std_logic_vector(5 downto 0) := conv_std_logic_vector(46, 6); - constant OpCode_Neq : std_logic_vector(5 downto 0) := conv_std_logic_vector(47, 6); - - constant OpCode_Sub : std_logic_vector(5 downto 0) := conv_std_logic_vector(49, 6); - constant OpCode_Loadb : std_logic_vector(5 downto 0) := conv_std_logic_vector(51, 6); - constant OpCode_Storeb : std_logic_vector(5 downto 0) := conv_std_logic_vector(52, 6); - - constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := conv_std_logic_vector(55, 6); - constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := conv_std_logic_vector(56, 6); - - constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := conv_std_logic_vector(61, 6); - constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := conv_std_logic_vector(62, 6); - constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := conv_std_logic_vector(63, 6); - - - - constant OpCode_Size : integer := 8; - -end zpupkg; diff --git a/zpu/hdl/zpu4/src/simzpu_bram.do b/zpu/hdl/zpu4/src/simzpu_bram.do deleted file mode 100644 index 1c8673d..0000000 --- a/zpu/hdl/zpu4/src/simzpu_bram.do +++ /dev/null @@ -1,28 +0,0 @@ -# Xilinx WebPack modelsim script -# -# cd C:/workspace/zpu/zpu/hdl/zpu4/src -# do simzpu_bram.do - -set BreakOnAssertion 1 -vlib work - -vcom -93 -explicit zpu_config_trace.vhd -vcom -93 -explicit zpupkg.vhd -vcom -93 -explicit txt_util.vhd -vcom -93 -explicit sim_fpga_top.vhd -vcom -93 -explicit zpu_core_bram.vhd -vcom -93 -explicit bram_dmips.vhd -vcom -93 -explicit timer.vhd -vcom -93 -explicit io.vhd -vcom -93 -explicit trace.vhd - -# run ZPU -vsim fpga_top -view wave -add wave -recursive fpga_top/zpu/* -#add wave -recursive fpga_top/* -view structure -#view signals - -# Enough to run tiny programs -run 1us diff --git a/zpu/hdl/zpu4/src/zpu_core_bram.vhd b/zpu/hdl/zpu4/src/zpu_core_bram.vhd deleted file mode 100644 index 0bedba3..0000000 --- a/zpu/hdl/zpu4/src/zpu_core_bram.vhd +++ /dev/null @@ -1,780 +0,0 @@ --- Company: ZPU3 --- Engineer: Øyvind Harboe - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -use IEEE.STD_LOGIC_arith.ALL; - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - - --- io_busy : in std_logic; --- io_read : in std_logic_vector(7 downto 0); --- io_write : out std_logic_vector(7 downto 0); --- io_addr : out std_logic_vector(maxAddrBit downto minAddrBit); --- io_writeEnable : out std_logic; --- io_readEnable : out std_logic; - - -entity zpu_core is - Port ( clk : in std_logic; - areset : in std_logic; - enable : in std_logic; - in_mem_busy : in std_logic; - mem_read : in std_logic_vector(wordSize-1 downto 0); - mem_write : out std_logic_vector(wordSize-1 downto 0); - out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); - out_mem_writeEnable : out std_logic; - out_mem_readEnable : out std_logic; - mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); - interrupt : in std_logic; - break : out std_logic); -end zpu_core; - - -architecture behave of zpu_core is - -signal readIO : std_logic; - - - -signal memAWriteEnable : std_logic; -signal memAAddr : std_logic_vector(maxAddrBit downto minAddrBit); -signal memAWrite : std_logic_vector(wordSize-1 downto 0); -signal memARead : std_logic_vector(wordSize-1 downto 0); -signal memBWriteEnable : std_logic; -signal memBAddr : std_logic_vector(maxAddrBit downto minAddrBit); -signal memBWrite : std_logic_vector(wordSize-1 downto 0); -signal memBRead : std_logic_vector(wordSize-1 downto 0); - - - -signal pc : std_logic_vector(maxAddrBit downto 0); -signal sp : std_logic_vector(maxAddrBit downto minAddrBit); - -signal idim_flag : std_logic; - ---signal storeToStack : std_logic; ---signal fetchNextInstruction : std_logic; ---signal extraCycle : std_logic; -signal busy : std_logic; ---signal fetching : std_logic; - -signal begin_inst : std_logic; - - - -signal trace_opcode : std_logic_vector(7 downto 0); -signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); -signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); -signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); - --- state machine. - -type State_Type is -( -State_ResyncDecode, -State_WriteIODone, -State_Execute, -State_StoreToStack, -State_Add, -State_Or, -State_And, -State_Store, -State_ReadIO, -State_WriteIO, -State_Load, -State_ResyncStack, -State_AddSP, -State_ReadIODone, -State_Decode, -State_LoadByte1, -State_LoadByte2, -State_StoreByte1, -State_StoreByte2, -State_Mult1, -State_Mult2, -State_Mult3 -); - -type DecodedOpcodeType is -( -Decoded_Nop, -Decoded_Im, -Decoded_ImShift, -Decoded_LoadSP, -Decoded_StoreSP, -Decoded_AddSP, -Decoded_Emulate, -Decoded_Break, -Decoded_PushPC, -Decoded_PushSP, -Decoded_PopPC, -Decoded_Add, -Decoded_Or, -Decoded_And, -Decoded_Load, -Decoded_Not, -Decoded_Flip, -Decoded_Store, -Decoded_PopSP, -Decoded_Ashiftleft, -Decoded_Ashiftright, -Decoded_Lshiftright, -Decoded_Eqbranch, -Decoded_Neqbranch, -Decoded_Eq, -Decoded_Neq, -Decoded_Loadb, -Decoded_Lessthan, -Decoded_Lessthanorequal, -Decoded_Ulessthan, -Decoded_Ulessthanorequal, -Decoded_Storeb, -Decoded_Lshift2, -Decoded_DoubleIm, -Decoded_AddIm, -Decoded_Mult16x16, -Decoded_Swap, -Decoded_Callpcrel, -Decoded_Pushspadd -); - - -signal mult1 : std_logic_vector(wordSize/2-1 downto 0); -signal mult2 : std_logic_vector(wordSize/2-1 downto 0); -signal multResult : std_logic_vector(wordSize-1 downto 0); - -signal storeByte : std_logic_vector(7 downto 0); -signal byteSelect : std_logic_vector(minAddrBit-1 downto 0); - -signal opcode : std_logic_vector(OpCode_Size-1 downto 0); -signal opcode2 : std_logic_vector(OpCode_Size-1 downto 0); - -signal decodedOpcode : DecodedOpcodeType; - -signal state : State_Type; - -begin - traceFileGenerate: - if Generate_Trace generate - trace_file: trace port map ( - clk => clk, - begin_inst => begin_inst, - pc => trace_pc, - opcode => trace_opcode, - sp => trace_sp, - memA => trace_topOfStack, - memB => trace_topOfStackB, - busy => busy, - intsp => (others => 'U') - ); - end generate; - - - memory: dualport_ram port map ( - clk => clk, - memAWriteEnable => memAWriteEnable, - memAAddr => memAAddr(maxAddrBitBRAM downto minAddrBit), - memAWrite => memAWrite, - memARead => memARead, - memBWriteEnable => memBWriteEnable, - memBAddr => memBAddr(maxAddrBitBRAM downto minAddrBit), - memBWrite => memBWrite, - memBRead => memBRead - ); - - - - process(clk, areset) - begin - if (clk'event and clk = '1') then - multResult <= mult1 * mult2; - end if; - end process; - - - - opcodeControl: - process(clk, areset) - variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); - variable tOpcode2 : std_logic_vector(OpCode_Size-1 downto 0); - variable spOffset : std_logic_vector(4 downto 0); - variable spOffset2 : std_logic_vector(4 downto 0); - variable nextPC : std_logic_vector(maxAddrBit downto 0); - variable pushspaddTemp : std_logic_vector(maxAddrBit downto minAddrBit); - variable tempVal : std_logic_vector(wordSize-1 downto 0); - variable compareA : signed(wordSize-1 downto 0); - variable compareB : signed(wordSize-1 downto 0); - begin - if areset = '1' then - mult1 <= (others => '0'); - mult2 <= (others => '0'); - state <= State_ResyncDecode; - break <= '0'; - sp <= spStart(maxAddrBit downto minAddrBit); - pc <= (others => '0'); - idim_flag <= '0'; - begin_inst <= '0'; - memAAddr <= (others => '0'); - memBAddr <= (others => '0'); - memAWriteEnable <= '0'; - memBWriteEnable <= '0'; - out_mem_writeEnable <= '0'; - out_mem_readEnable <= '0'; - decodedOpcode <= Decoded_Break; - memAWrite <= (others => '0'); - memBWrite <= (others => '0'); - opcode <= (others => '0'); - out_mem_addr <= (others => '0'); - mem_write <= (others => '0'); - elsif (clk'event and clk = '1') then - memAWriteEnable <= '0'; - memBWriteEnable <= '0'; - - out_mem_writeEnable <= '0'; - out_mem_readEnable <= '0'; - out_mem_addr <= memARead(maxAddrBitIncIO downto 0); - begin_inst <= '0'; - - case state is - when State_Decode => - nextPC:=pc+1; - case pc(1 downto 0) is - when "00" => tOpcode := memARead(31 downto 24); - when "01" => tOpcode := memARead(23 downto 16); - when "10" => tOpcode := memARead(15 downto 8); - when others => tOpcode := memARead(7 downto 0); - end case; - case nextPC(1 downto 0) is - when "00" => tOpcode2 := memBRead(31 downto 24); - when "01" => tOpcode2 := memBRead(23 downto 16); - when "10" => tOpcode2 := memBRead(15 downto 8); - when others => tOpcode2 := memBRead(7 downto 0); - end case; - idim_flag <= tOpcode(7); - opcode <= tOpcode; - opcode2 <= tOpcode2; - if (tOpcode(7 downto 7)=OpCode_Im and tOpcode2(7 downto 4)=0 and tOpcode2(3 downto 0)=Opcode_Add and idim_flag='0') then - idim_flag <= '0'; - decodedOpcode <= Decoded_AddIm; - nextPC := pc + 2; - elsif (tOpcode(7 downto 7)=OpCode_Im and tOpcode2(7 downto 7)=OpCode_Im and idim_flag='0') then - decodedOpcode <= Decoded_DoubleIm; - nextPC := pc + 2; - elsif (tOpcode(7 downto 4)=OpCode_AddSP and tOpcode(3 downto 0)=0 and - tOpcode2(7 downto 4)=OpCode_AddSP and tOpcode2(3 downto 0)=0) then - decodedOpcode <= Decoded_Lshift2; - nextPC := pc + 2; - elsif (tOpcode(7 downto 7)=OpCode_Im) then - if (idim_flag='1') then - decodedOpcode<=Decoded_ImShift; - else - decodedOpcode<=Decoded_Im; - end if; - elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then - decodedOpcode<=Decoded_StoreSP; - elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then - decodedOpcode<=Decoded_LoadSP; - elsif (tOpcode(7 downto 5)=OpCode_Emulate) then - if tOpcode(5 downto 0)=OpCode_Eqbranch then - decodedOpcode <= Decoded_Eqbranch; - elsif tOpcode(5 downto 0)=OpCode_Neqbranch then - decodedOpcode <= Decoded_Neqbranch; - elsif tOpcode(5 downto 0)=OpCode_Eq then - decodedOpcode <= Decoded_Eq; - elsif tOpcode(5 downto 0)=OpCode_Neq then - decodedOpcode <= Decoded_Neq; - elsif tOpcode(5 downto 0)=OpCode_Lessthan then - decodedOpcode <= Decoded_Lessthan; - elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then - decodedOpcode <= Decoded_Lessthanorequal; - elsif tOpcode(5 downto 0)=OpCode_Ulessthan then - decodedOpcode <= Decoded_Ulessthan; - elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then - decodedOpcode <= Decoded_Ulessthanorequal; - elsif tOpcode(5 downto 0)=OpCode_Loadb then - decodedOpcode <= Decoded_Loadb; - elsif tOpcode(5 downto 0)=OpCode_Storeb then - decodedOpcode <= Decoded_Storeb; - elsif tOpcode(5 downto 0)=OpCode_Mult16x16 then - decodedOpcode <= Decoded_Mult16x16; - elsif tOpcode(5 downto 0)=OpCode_Swap then - decodedOpcode <= Decoded_Swap; - elsif tOpcode(5 downto 0)=OpCode_Callpcrel then - decodedOpcode <= Decoded_Callpcrel; - elsif tOpcode(5 downto 0)=OpCode_Pushspadd then - decodedOpcode <= Decoded_Pushspadd; --- elsif tOpcode(5 downto 0)=OpCode_Lshiftright then --- decodedOpcode <= Decoded_Lshiftright; --- elsif tOpcode(5 downto 0)=OpCode_Ashiftleft then --- decodedOpcode <= Decoded_Ashiftleft; --- elsif tOpcode(5 downto 0)=OpCode_Ashiftright then --- decodedOpcode <= Decoded_Ashiftright; - else - decodedOpcode<=Decoded_Emulate; - end if; - elsif (tOpcode(7 downto 4)=OpCode_AddSP) then - decodedOpcode<=Decoded_AddSP; - else - case tOpcode(3 downto 0) is - when OpCode_PushSP => - decodedOpcode<=Decoded_PushSP; - when OpCode_PopPC => - decodedOpcode<=Decoded_PopPC; - when OpCode_Add => - decodedOpcode<=Decoded_Add; - when OpCode_Or => - decodedOpcode<=Decoded_Or; - when OpCode_And => - decodedOpcode<=Decoded_And; - when OpCode_Load => - decodedOpcode<=Decoded_Load; - when OpCode_Not => - decodedOpcode<=Decoded_Not; - when OpCode_Flip => - decodedOpcode<=Decoded_Flip; - when OpCode_Store => - decodedOpcode<=Decoded_Store; - when OpCode_PopSP => - decodedOpcode<=Decoded_PopSP; - when OpCode_Break => - decodedOpcode<=Decoded_Break; - when others => - decodedOpcode<=Decoded_Nop; - end case; - end if; - -- Fetch the two next opcodes... :-) - memAAddr <= nextPC(maxAddrBit downto minAddrBit); - nextPC:=nextPC+1; - memBAddr <= nextPC(maxAddrBit downto minAddrBit); - state <= State_Execute; - when State_Execute => - state <= State_Decode; - -- at this point: - -- memBRead contains opcode word - -- memARead contains top of stack - pc <= pc + 1; - - -- trace - begin_inst <= '1'; - trace_pc <= (others => '0'); - trace_pc(maxAddrBit downto 0) <= pc; - trace_sp <= (others => '0'); - trace_sp(maxAddrBit downto minAddrBit) <= sp; - trace_opcode <= opcode; - trace_topOfStack <= memARead; - trace_topOfStackB <= memBRead; - - - -- during the next cycle we'll be reading the next opcode - spOffset(4):=not opcode(4); - spOffset(3 downto 0):=opcode(3 downto 0); - spOffset2(4):=not opcode2(4); - spOffset2(3 downto 0):=opcode2(3 downto 0); - - case decodedOpcode is - - when Decoded_DoubleIm => - memAWriteEnable <= '1'; - sp <= sp - 1; - memAAddr <= sp-1; - for i in wordSize-1 downto 14 loop - memAWrite(i) <= opcode(6); - end loop; - memAWrite(13 downto 7) <= opcode(6 downto 0); - memAWrite(6 downto 0) <= opcode2(6 downto 0); - memBAddr <= sp; - memBWrite <= memARead; - memBWriteEnable <= '1'; - pc <= pc + 2; - when Decoded_Im => - memAWriteEnable <= '1'; - sp <= sp - 1; - memAAddr <= sp-1; - for i in wordSize-1 downto 7 loop - memAWrite(i) <= opcode(6); - end loop; - memAWrite(6 downto 0) <= opcode(6 downto 0); - memBAddr <= sp; - memBWrite <= memARead; - memBWriteEnable <= '1'; - when Decoded_ImShift => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0); - memAWrite(6 downto 0) <= opcode(6 downto 0); - memBAddr <= sp + 1; - when Decoded_StoreSP => - memAWriteEnable <= '1'; - memAAddr <= sp+spOffset; - memAWrite <= memARead; - -- avoid address crashes. - memBAddr <= sp - 1; - sp <= sp + 1; - state <= State_ResyncDecode; - when Decoded_LoadSP => - sp <= sp - 1; - if (spOffset = 0) then - -- This is a duplicate instruction. - memAAddr <= sp-1; - memAWriteEnable <= '1'; - memAWrite <= memARead; - else - memAAddr <= sp+spOffset; - end if; - memBAddr <= sp; - memBWrite <= memARead; - memBWriteEnable <= '1'; - when Decoded_Callpcrel => - memAWriteEnable <= '1'; - memAAddr <= sp; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto 0) <= pc + 1; - memBAddr <= sp+1; - pc <= pc + memARead(maxAddrBit downto 0); - state <= State_ResyncDecode; - when Decoded_Emulate => - sp <= sp - 1; - memAWriteEnable <= '1'; - memAAddr <= sp - 1; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto 0) <= pc + 1; - memBAddr <= sp; - memBWrite <= memARead; - memBWriteEnable <= '1'; - -- The emulate address is: - -- 98 7654 3210 - -- 0000 00aa aaa0 0000 - pc <= (others => '0'); - pc(9 downto 5) <= opcode(4 downto 0); - state <= State_ResyncDecode; - when Decoded_AddSP => - if spOffset=0 then - -- avoid address line crashes... - -- FIX!!! is this an issue? - -- oh-well. While we are at it, we've got a faster - -- shift operation without updating the toolchain. - memAWriteEnable <= '1'; - memAAddr <= sp; - memAWrite <= memARead + memARead; - memBAddr <= sp+1; - else - memAWriteEnable <= '1'; - memAAddr <= sp; - memAWrite <= memARead; - memBAddr <= sp+spOffset; - state <= State_AddSP; - end if; - when Decoded_Break => - report "Break instruction encountered" severity failure; - break <= '1'; - when Decoded_PushSP => - memAWriteEnable <= '1'; - memAAddr <= sp - 1; - sp <= sp - 1; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto minAddrBit) <= sp; - memBAddr <= sp; - memBWrite <= memARead; - memBWriteEnable <= '1'; - when Decoded_Pushspadd => - memAWriteEnable <= '1'; - memAAddr <= sp; - memAWrite <= (others => DontCareValue); - pushspaddTemp := memARead(maxAddrBit-minAddrBit downto 0); - memAWrite(maxAddrBit downto minAddrBit) <= sp+pushspaddTemp; - memBAddr <= sp+1; - when Decoded_PopPC => - memAAddr <= sp; - pc <= memARead(maxAddrBit downto 0); - sp <= sp + 1; - state <= State_ResyncDecode; - when Decoded_AddIm => - memAWriteEnable <= '1'; - memAAddr <= sp; - tempVal(wordSize-1 downto 7) := (others => tOpcode(6)); - tempVal(6 downto 0) := tOpcode(6 downto 0); - memAWrite <= memARead + tempVal; - memBAddr <= sp + 1; - pc <= pc + 2; - when Decoded_Add => - memAWriteEnable <= '1'; - memAWrite <= memARead + memBRead; - memAAddr <= sp + 1; - memBAddr <= sp + 2; - sp <= sp + 1; - when Decoded_Or => - sp <= sp + 1; - memAWriteEnable <= '1'; - memAWrite <= memARead or memBRead; - memAWriteEnable <= '1'; - memAAddr <= sp + 1; - memBAddr <= sp + 2; - when Decoded_And => - sp <= sp + 1; - memAWriteEnable <= '1'; - memAWrite <= memARead and memBRead; - memAWriteEnable <= '1'; - memAAddr <= sp + 1; - memBAddr <= sp + 2; - when Decoded_Load => - if (memARead(ioBit)='1') then - out_mem_addr <= memARead(maxAddrBitIncIO downto 0); - out_mem_readEnable <= '1'; - state <= State_ReadIO; - else - memAAddr <= memARead(maxAddrBit downto minAddrBit); - memBAddr <= sp + 1; - end if; - when Decoded_Swap => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite(wordSize/2-1 downto 0) <= memARead(wordSize-1 downto wordSize/2); - memAWrite(wordSize-1 downto wordSize/2) <= memARead(wordSize/2-1 downto 0); - memBAddr <= sp + 1; - when Decoded_Not => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= not memARead; - memBAddr <= sp + 1; - when Decoded_Flip => - memAAddr <= sp; - memAWriteEnable <= '1'; - for i in 0 to wordSize-1 loop - memAWrite(i) <= memARead(wordSize-1-i); - end loop; - memBAddr <= sp + 1; - when Decoded_Lshift2 => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite(1 downto 0) <= (others => '0'); - memAWrite(wordSize-1 downto 2) <= memARead(wordSize-1-2 downto 0); - memBAddr <= sp + 1; - pc <= pc + 2; - when Decoded_Store => - sp <= sp + 2; - if (memARead(ioBit)='1') then - out_mem_writeEnable <= '1'; - out_mem_addr <= memARead(maxAddrBitIncIO downto 0); - mem_write <= memBRead; - state <= State_WriteIO; - else - memAWriteEnable <= '1'; - memAAddr <= memARead(maxAddrBit downto minAddrBit); - memAWrite <= memBRead; - state <= State_ResyncDecode; - end if; - when Decoded_PopSP => - sp <= memARead(maxAddrBit downto minAddrBit); - state <= State_ResyncDecode; - when Decoded_Ashiftleft => - memAWrite(wordSize-1 downto conv_integer(memARead(wordPower-1 downto 0))) <= - memBRead(wordSize-conv_integer(memARead(wordPower-1 downto 0))-1 downto 0); - if memARead(wordPower-1 downto 0)/=0 then - memAWrite(conv_integer(memARead(wordPower-1 downto 0))-1 downto 0) <= (others => '0'); - end if; - memAWriteEnable <= '1'; - memAAddr <= sp + 1; - memBAddr <= sp + 2; - sp <= sp + 1; - when Decoded_Ashiftright | Decoded_Lshiftright => - memAWrite(wordSize-1-conv_integer(memARead(wordPower-1 downto 0)) downto 0) <= - memBRead(wordSize-1 downto conv_integer(memARead(wordPower-1 downto 0))); - if memARead(wordPower-1 downto 0)/=0 then - if decodedOpcode=Decoded_Ashiftright and memBRead(wordSize-1)='1' then - memAWrite(wordSize-1 downto wordSize-conv_integer(memARead(wordPower-1 downto 0))-1) <= (others => '1'); - else - memAWrite(wordSize-1 downto wordSize-conv_integer(memARead(wordPower-1 downto 0))-1) <= (others => '0'); - end if; - end if; - memAWriteEnable <= '1'; - memAAddr <= sp + 1; - memBAddr <= sp + 2; - sp <= sp + 1; - when Decoded_Eqbranch => - sp <= sp + 2; - if (memBRead=0) then - pc <= memARead(maxAddrBit downto 0) + pc; - end if; - state <= State_ResyncDecode; - when Decoded_Neqbranch => - sp <= sp + 2; - if (memBRead/=0) then - pc <= memARead(maxAddrBit downto 0) + pc; - end if; - state <= State_ResyncDecode; - when Decoded_Eq => - sp <= sp + 1; - memAWrite <= (others => '0'); - if (memARead=memBRead) then - memAWrite(0) <= '1'; - end if; - memAAddr <= sp + 1; - memAWriteEnable <= '1'; - memBAddr <= sp + 2; - when Decoded_Neq => - sp <= sp + 1; - memAWrite <= (others => '0'); - if (memARead/=memBRead) then - memAWrite(0) <= '1'; - end if; - memAAddr <= sp + 1; - memAWriteEnable <= '1'; - memBAddr <= sp + 2; - when Decoded_Ulessthan => - sp <= sp + 1; - memAWrite <= (others => '0'); - if (memARead - sp <= sp + 1; - memAWrite <= (others => '0'); - if (memARead<=memBRead) then - memAWrite(0) <= '1'; - end if; - memAAddr <= sp + 1; - memAWriteEnable <= '1'; - memBAddr <= sp + 2; - when Decoded_Lessthan => - sp <= sp + 1; - memAWrite <= (others => '0'); - compareA := signed(memARead); - compareB := signed(memBRead); - if (compareA - sp <= sp + 1; - memAWrite <= (others => '0'); - compareA := signed(memARead); - compareB := signed(memBRead); - if (compareA<=compareB) then - memAWrite(0) <= '1'; - end if; - memAAddr <= sp + 1; - memAWriteEnable <= '1'; - memBAddr <= sp + 2; - when Decoded_Loadb => - byteSelect <= memARead(minAddrBit-1 downto 0); - memAAddr <= memARead(maxAddrBit downto minAddrBit); - state <= State_LoadByte1; - when Decoded_Storeb => - sp <= sp + 2; - byteSelect <= memARead(minAddrBit-1 downto 0); - storeByte <= memBRead(7 downto 0); - memAAddr <= memARead(maxAddrBit downto minAddrBit); - memBAddr <= sp; - state <= State_StoreByte1; - when Decoded_Mult16x16 => - mult1 <= memARead(wordSize/2-1 downto 0); - mult2 <= memBRead(wordSize/2-1 downto 0); - sp <= sp + 1; - state <= State_Mult1; - when others => - -- nop. Here we persist whatever was loaded into - -- memARead - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead; - memBAddr <= sp + 1; - - end case; - when State_ReadIO => - state <= State_ReadIODone; - when State_ReadIODone => - if (in_mem_busy = '0') then - state <= State_ResyncDecode; - memAWriteEnable <= '1'; - memAWrite <= (others => '0'); - memAWrite <= mem_read; - memAAddr <= sp; - end if; - when State_WriteIO => - state <= State_WriteIODone; - when State_WriteIODone => - if (in_mem_busy = '0') then - state <= State_ResyncDecode; - end if; - when State_ResyncDecode => - memAAddr <= pc(maxAddrBit downto minAddrBit); - nextPC:=pc+1; - memBAddr <= nextPC(maxAddrBit downto minAddrBit); - state <= State_ResyncStack; - when State_ResyncStack => - memAAddr <= sp; - memBAddr <= sp+1; - state <= State_Decode; - when State_AddSP => - memAAddr <= pc(maxAddrBit downto minAddrBit); - nextPC:=pc+1; - memBAddr <= nextPC(maxAddrBit downto minAddrBit); - state <= State_Add; - when State_Add => - memAWriteEnable <= '1'; - memAWrite <= memARead + memBRead; - memAAddr <= sp; - memBAddr <= sp + 1; - state <= State_Decode; - when State_LoadByte1 => - memAAddr <= pc(maxAddrBit downto minAddrBit); - nextPC:=pc+1; - memBAddr <= nextPC(maxAddrBit downto minAddrBit); - state <= State_LoadByte2; - when State_LoadByte2 => - memAWriteEnable <= '1'; - memAAddr <= sp; - memAWrite <= (others => '0'); - case byteSelect is - when "00" => memAWrite(7 downto 0) <= memARead(31 downto 24); - when "01" => memAWrite(7 downto 0) <= memARead(23 downto 16); - when "10" => memAWrite(7 downto 0) <= memARead(15 downto 8); - when others => memAWrite(7 downto 0) <= memARead(7 downto 0); - end case; - memBAddr <= sp + 1; - state <= State_Decode; - when State_StoreByte1 => - state <= State_StoreByte2; - when State_StoreByte2 => - memAWriteEnable <= '1'; - memAAddr <= memBRead(maxAddrBit downto minAddrBit); - memAWrite <= memARead; - case byteSelect is - when "00" => memAWrite(31 downto 24) <= storeByte; - when "01" => memAWrite(23 downto 16) <= storeByte; - when "10" => memAWrite(15 downto 8) <= storeByte; - when others => memAWrite(7 downto 0) <= storeByte; - end case; - state <= State_ResyncDecode; - when State_Mult1 => - memAAddr <= pc(maxAddrBit downto minAddrBit); - nextPC:=pc+1; - memBAddr <= nextPC(maxAddrBit downto minAddrBit); - state <= State_Mult2; - when State_Mult2 => - memAWriteEnable <= '1'; - memAWrite <= multResult; - memAAddr <= sp; - memBAddr <= sp + 1; - state <= State_Decode; - - when others => - null; - end case; - end if; - end process; - - - -end behave; diff --git a/zpu/roadshow/roadshow/helloworld/test.c b/zpu/roadshow/roadshow/helloworld/test.c index 8c33640..5243468 100644 --- a/zpu/roadshow/roadshow/helloworld/test.c +++ b/zpu/roadshow/roadshow/helloworld/test.c @@ -1,3 +1,4 @@ +/* zpu-elf-gcc -g -Wl,--relax test.c -phi -o hello.elf */ int main(int argc, char **argv) { for (;;) -- cgit v1.1 From af198f5c76764dd55a5eed7a29ab24b032792e89 Mon Sep 17 00:00:00 2001 From: oharboe Date: Tue, 15 Apr 2008 06:00:18 +0000 Subject: retired --- zpu/hdl/zpu4/src/status.txt | 109 -------------------------------------------- 1 file changed, 109 deletions(-) delete mode 100644 zpu/hdl/zpu4/src/status.txt diff --git a/zpu/hdl/zpu4/src/status.txt b/zpu/hdl/zpu4/src/status.txt deleted file mode 100644 index df01caf..0000000 --- a/zpu/hdl/zpu4/src/status.txt +++ /dev/null @@ -1,109 +0,0 @@ -- Before NEQBRANCH opt 4.684 DMIPS 8.0 cycles average, after -- opcode pairs - -0x6060 0.1519223038446077 75961 9.048362120309708 LOADSP + LOADSP -0x4040 0.13967027934055867 69835 11.08668042546436 STORESP + STORESP -0x8038 0.10230620461240922 51153 10.251102204408818 IM + NEQBRANCH -0x4060 0.09856219712439425 49281 9.822802471596571 STORESP + LOADSP -0x6080 0.09734219468438937 48671 6.483415478886373 LOADSP + IM -0x3860 0.08642217284434568 43211 12.616350364963504 NEQBRANCH + LOADSP -0x8080 0.060966121932243864 30483 4.275915275634731 IM + IM -0x8005 0.05317010634021268 26585 6.572311495673671 IM + ADD -0x540 0.05215210430420861 26076 9.339541547277937 ADD + STORESP -0x3d0d 0.050808101616203236 25404 12.398243045387995 -0xd04 0.0466000932001864 23300 20.0 -0x6040 0.04389608779217558 21948 9.460344827586207 -0x4080 0.043648087296174594 21824 7.630769230769231 -0xc80 0.03966807933615867 19834 11.438292964244521 -0x8010 0.0391500783001566 19575 6.1248435544430535 -0x480 0.038798077596155195 19399 10.941342357586013 - - -- zpu_core.vhd: 1500 LUTs. Xilinx ISE reports 83MHz maximum frequency after P&R - which matches what I've found w/my ic300.vhd testbench - -- zpu_core_instack.vhd - - problems w/simulation trace since storeb/loadb will run into undefined memory - during emulation. Solution: implement loadb+storeb. - - simulation needs to read cycles from ModelSim trace so as to m ake readcycles - not cause false positives. This has other interesting potentials w.r.t. - knowing which instructions take the longest. - -- Ca. 1700 LUT inc. all instructions. Removing all higher level instructions - => 1300. - -- Review memory interface - - When is mem_busy high? Will it be high on the next cycle after - I've send mem_read/writeEnable? - - Should I hold off posting a read/write until mem_busy = '0'? - - Write posting could increase performance somewhat. Should there be - a seperate write busy signal? - - Synchronous reset? The ARM7 will have to copy the program to DRAM and - then start the ZPU. - -- Current instruction set has - - 31 DMIPS single cycle performance Simulator.java - - 8 DMIPS w/single cycle RAM access in ModelSim - -112 0.06100380865858346 67215918 -56 0.04139603650830458 45611457 -129 0.0375812381475752 41408192 -5 0.03703417264799563 40805418 -113 0.03540341331682748 39008596 -128 0.0343154384313754 37809831 -83 0.03322159422742951 36604599 -114 0.03213492807203279 35407276 -132 0.03158580962697109 34802240 -12 0.03049709687915076 33602662 -8 0.029409690138646426 32404523 -115 0.026690690908727877 29408644 -46 0.025054316381406774 27605635 -82 0.023965804208719754 26406278 -84 0.023961360698074072 26401382 -116 0.023417718589457643 25802380 -81 0.02179306727026773 24012288 -117 0.021783900714401432 24002188 -4 0.01797685126990833 19807461 -6 0.016340292503890113 18004249 -85 0.016339001017850734 18002826 -255 0.016338918428089957 18002735 -86 0.016337281154151066 18000931 -11 0.011984767180825744 13205194 -51 0.0114390303780569 12603884 -38 0.010892246228211845 12001420 -118 0.010347263624247446 11400941 -131 0.009257503529350904 10200209 -7 0.008713386756504965 9600684 -22 0.008712946580307425 9600199 - - -64 0.16176824859336478 178241352 -96 0.23147927881894828 255051161 -128 0.2646966482624612 291651105 - - -- Alternate memory interface to allow more caching in memory subsystem? - --- The memory interface allows a dual port memory to be used --- to increase performance. --- --- Also it is possible to implement a zero cycle register file instead --- of memory, though obviously that will cause problems w.r.t. max --- frequency for the ZPU. --- --- mem_writeEnable - set to '1' for a single cycle to send off a write request. --- mem_write is valid only while mem_writeEnable='1'. --- mem_readEnable - set to '1' for a single cycle to send off a read request. --- mem_read is a single cycle while mem_read_busy='0'. --- --- mem_read/write_busy - It is illegal to send off a read/write request when mem_read/write_busy='1'. --- Set to '0' when mem_read is valid after a read request. Note that --- the definition allows zero wait state ram. --- mem_read/write_addr - address for read/write request --- mem_read - read data. Valid only on the cycle after mem_busy='0' after --- mem_readEnable='1' for a single cycle. --- mem_write - data to write --- mem_writeMask - set to '1' for those bits that are to be written to memory upon --- write request --- break - set to '1' when CPU hits break instruction --- interrupt - set to '1' until interrupts are cleared by CPU. -- cgit v1.1 From 23eeb5e93c3305c196f8d0811b0347000df7a36f Mon Sep 17 00:00:00 2001 From: oharboe Date: Tue, 15 Apr 2008 06:48:28 +0000 Subject: * zpu/docs/zpu_arch.odt - a short summary of the architecture --- zpu/ChangeLog | 1 + zpu/docs/zpu_arch.odt | Bin 0 -> 22228 bytes zpu/docs/zpuprotoarch.odt | Bin 23961 -> 0 bytes 3 files changed, 1 insertion(+) create mode 100644 zpu/docs/zpu_arch.odt delete mode 100644 zpu/docs/zpuprotoarch.odt diff --git a/zpu/ChangeLog b/zpu/ChangeLog index e883d0d..0b787b1 100644 --- a/zpu/ChangeLog +++ b/zpu/ChangeLog @@ -1,4 +1,5 @@ 2008-04-15 Øyvind Harboe + * zpu/docs/zpu_arch.odt - a short summary of the architecture * zpu/simzpu_bram.do - retired. * zpu/zpu_core_bram.vhd - retired * zpu/hdl/zpu3 - retired diff --git a/zpu/docs/zpu_arch.odt b/zpu/docs/zpu_arch.odt new file mode 100644 index 0000000..047f74e Binary files /dev/null and b/zpu/docs/zpu_arch.odt differ diff --git a/zpu/docs/zpuprotoarch.odt b/zpu/docs/zpuprotoarch.odt deleted file mode 100644 index 67a4171..0000000 Binary files a/zpu/docs/zpuprotoarch.odt and /dev/null differ -- cgit v1.1 From fbce0c049625e1c756a4eaddfa8e115bc2c4fc01 Mon Sep 17 00:00:00 2001 From: oharboe Date: Wed, 16 Apr 2008 07:03:32 +0000 Subject: wip --- zpu/docs/zpu_arch.html | 335 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 335 insertions(+) create mode 100644 zpu/docs/zpu_arch.html diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html new file mode 100644 index 0000000..ca18fae --- /dev/null +++ b/zpu/docs/zpu_arch.html @@ -0,0 +1,335 @@ + + +

      Instruction set

      +Only the base instructions are implemented in the architecture. More advanced instructions, like ASHIFTLEFT are emulated in the illegal instruction vector. + +All operations are 32 bit wide. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      NameOpcodeDescriptionDefinition
      + BREAKPOINT + + 00000000 + + The debugger sets a memory location to this value to set a breakpoint. Once a JTAG-like + debugger interface is added, it will be convenient to be able to distinguish + between a breakpoint and an illegal(possibly emulated) instruction. + + No effect on registers +
      + IM + + 1xxx xxxx + + Pushes 7 bit sign extended integer and sets the a «instruction decode interrupt mask» flag(IDIM). +

      + If the IDIM flag is already set, this instruction shifts the value on the stack left by 7 bits and stores the 7 bit immediate value into the lower 7 bits. +

      + Unless an instruction is listed as treating the IDIM flag specially, it should be assumed to clear the IDIM flag. +

      + To push a 14 bit integer onto the stack, use two consequtive IM instructions. +

      + If multiple immediate integers are to be pushed onto the stack, they must be interleaved with another instruction, typically NOP. +

      		+ +
      + STORESP + + 010x xxxx + + Pop value off stack and store it in the SP+xxxxx*4 memory location, where xxxxx is a positive integer. + + Fix! +
      + LOADSP + + 011x xxxx + + Push value of memory location SP+xxxxx*4, where xxxxx is a positive integer, onto stack. + + Fix! +
      + ADDSP + + 0001 xxxx + + Add value of memory location SP+xxxx*4 to value on top of stack. + + Fix! +
      + EMULATE + + 001x xxxx + + Push PC to stack and set PC to 0x0+xxxxx*32. This is used to emulate opcodes. See zpupgk.vhd for list of emulate opcode values used. zpu_core.vhd contains reference implementations of these instructions rather than letting the ZPU execute the EMULATE instruction + + Fix! +
      + PUSHPC + + emulated + + Pushes program counter onto the stack. + + Fix! +
      + POPPC + + 0000 0100 + + Pops address off stack and sets PC + + Fix! +
      + LOAD + + 0000 1000 + + Pops address stored on stack and loads the value of that address onto stack. + + Fix! +
      + LOAD + + 0000 1000 + + Pops address stored on stack and loads the value of that address onto stack. +

      + Bit 0 and 1 of address are always 0. +

      		+ Fix! +
      + STORE + + 0000 1100 + + Pops address, then value from stack and stores the value into the memory location of the address. +

      + Bit 0 and 1 of address are always 0 +

      		+ Fix! +
      + PUSHSP + + 0000 0010 + + Pushes stack pointer. + + Fix! +
      + POPSP + + 0000 1101 + + Used to allocate/deallocate space on stack for variables or when changing threads. + + Fix! +
      + ADD + + 0000 0101 + + Pops two values on stack adds them and pushes the result + + Fix! +
      + AND + + 0000 0110 + + Pops two values off the stack and does a bitwise-and & pushes the result onto the stack + + Fix! +
      + OR + + 0000 0111 + + Pops two integers, does a bitwise or and pushes result + + Fix! +
      + NOT + + 0000 1001 + + Bitwise inverse of value on stack + + + Fix! +
      + FLIP + + 0000 1010 + + Reverses the bit order of the value on the stack, i.e. abc->cba, 100->001, 110->011, etc. + + Fix! +
      + NOP + + 0000 1011 + + No operation + + Fix! +
      + Fix! add emulated instructions! Listed in zpupkg.vhd + + 001x xxxx + + Fix!! + + Fix! +
      + +

      Vectors

      + + + + + + + + + + + + + + + + + +
      AddressNameDescription
      0x000Reset + 1.When the ZPU boots, this is the first instruction to be executed. +

      + 2.The stack pointer is initialised to maximum RAM address +

      0x020Interrupt + This is the entry point for interrupts. +
      0x040-Emulated instructions + Emulated opcode 34. Note that opcode 32 and opcode 33 are not normally used to emulate instructions as these memory addresses are already used by boot vector, GCC registers and the interrupt vector. +
      + + + \ No newline at end of file -- cgit v1.1 From 034794137533316abb06191976c9fa254124da40 Mon Sep 17 00:00:00 2001 From: oharboe Date: Wed, 16 Apr 2008 07:14:57 +0000 Subject: * zpu/docs/zpu_arch.html: added. Need to define instruction set. * zpu/docs/zpu_arch.odt: retired --- zpu/ChangeLog | 3 +++ zpu/docs/zpu_arch.html | 16 +++++++++++++++- zpu/docs/zpu_arch.odt | Bin 22228 -> 0 bytes 3 files changed, 18 insertions(+), 1 deletion(-) delete mode 100644 zpu/docs/zpu_arch.odt diff --git a/zpu/ChangeLog b/zpu/ChangeLog index 0b787b1..5a82aef 100644 --- a/zpu/ChangeLog +++ b/zpu/ChangeLog @@ -1,3 +1,6 @@ +2008-04-16 Øyvind Harboe + * zpu/docs/zpu_arch.html: added. Need to define instruction set. + * zpu/docs/zpu_arch.odt: retired 2008-04-15 Øyvind Harboe * zpu/docs/zpu_arch.odt - a short summary of the architecture * zpu/simzpu_bram.do - retired. diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index ca18fae..3f306f1 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -41,7 +41,21 @@ All operations are 32 bit wide. If multiple immediate integers are to be pushed onto the stack, they must be interleaved with another instruction, typically NOP. - + +pc <= pc + 1
      +idim <= 1
      +if (idim=0) then
      + sp <= sp - 1;
      + for i in wordSize-1 downto 7 loop
      + mem(sp)(i) <= opcode(6)
      + end loop
      + mem(sp)(6 downto 0) <= opcode(6 downto 0)
      +else
      + mem(sp)(wordSize-1 downto 7) <= mem(sp)(wordSize-8 downto 0)
      + mem(sp)(6 downto 0) <= opcode(6 downto 0)
      +end if +       + diff --git a/zpu/docs/zpu_arch.odt b/zpu/docs/zpu_arch.odt deleted file mode 100644 index 047f74e..0000000 Binary files a/zpu/docs/zpu_arch.odt and /dev/null differ -- cgit v1.1 From f0ef5e051f422887eff80cd8e6d8ab224e5e9114 Mon Sep 17 00:00:00 2001 From: oharboe Date: Wed, 16 Apr 2008 08:29:27 +0000 Subject: * zpu/docs/zpu_arch.html: added Phi memory map to end of zpu_arch.html * zpu/docs/zpuphiregs.odt: retired --- zpu/ChangeLog | 2 + zpu/docs/zpu_arch.html | 377 ++++++++++++++++++++++++++++++++++++++++++++++++ zpu/docs/zpuphiregs.odt | Bin 27013 -> 0 bytes 3 files changed, 379 insertions(+) delete mode 100644 zpu/docs/zpuphiregs.odt diff --git a/zpu/ChangeLog b/zpu/ChangeLog index 5a82aef..052c479 100644 --- a/zpu/ChangeLog +++ b/zpu/ChangeLog @@ -1,4 +1,6 @@ 2008-04-16 Øyvind Harboe + * zpu/docs/zpu_arch.html: added Phi memory map to end of zpu_arch.html + * zpu/docs/zpuphiregs.odt: retired * zpu/docs/zpu_arch.html: added. Need to define instruction set. * zpu/docs/zpu_arch.odt: retired 2008-04-15 Øyvind Harboe diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index 3f306f1..df692a7 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -344,6 +344,383 @@ end if + +

      Phi memory map

      +The ZPU architecture does not define a memory map as such, but the GCC + libgloss + ecos hal library uses the +memory map below. +

      + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      +

      Address

      +       		+

      Type

      +       		+

      Name

      +       		+

      Description

      +
      +

      0x080A0000

      +       		+

      Write

      +       		+

      ZPU + enable

      +       		+

      Bit + [31:1] Not used

      +

      Bit + [0] Enable ZPU operations

      +

      0 ZPU + is held in Idle mode

      +

      1 ZPU + running

      +
      +

      0x080A000C

      +       		+

      Read/

      +

      Write

      +       		+

      ZPU + UART to ARM7 TX

      +

      NOTE! + ZPU side

      +       		+

      Bit + [31:9] Not used

      +

      Bit + [8] TX buffer ready (valid on ready)

      +

      0 TX + buffer not ready (full)

      +

      1 TX + buffer ready

      +

      Bit + [7:0] TX byte (valid on write)

      +
      +

      0x080A0010

      +       		+

      Read

      +       		+

      ZPU + UART to ARM7 RX

      +

      NOTE! + ZPU side

      +       		+

      Bit + [31:9] Not used

      +

      Bit + [8] RX buffer data valid

      +

      0 TX + buffer not valid

      +

      1 TX + buffer valid

      +

      Bit + [7:0] RX byte (when valid)

      +
      +

      0x080A0014

      +       		+

      Read/

      +

      Write

      +       		+

      Counter(1)

      +       		+

      Bit + [0] Reset counter (valid for write)

      +

      0 N/A

      +

      1 Reset + counter

      +

      Bit + [1] Sample counter (valid for write)

      +

      0 N/A

      +

      1 Sample + counter

      +

      Bit + [31:0] Counter bit 31:0

      +
      +

      0x080A0018

      +       		+

      Read

      +       		+

      Counter(2)

      +       		+

      Bit + [31:0] Counter bit 63:32

      +
      +

      0x080A0020

      +       		+

      Read + / Write

      +       		+

      Global_Interrupt_mask

      +       		+

      Bit + [31:1] Not used

      +

      Bit + [0] Global intr. Mask

      +

      0 Interrupts + enabled

      +

      1 Interrupts + disabled

      +
      +

      0x080A0024

      +       		+

      Write

      +       		+

      UART_INTERRUPT_ENABLE

      +       		+

      Bit + [31:1] Not used

      +

      Bit + [0] UART RX interrupt enable

      +

      0 Interrupt + disable

      +

      1 Interrupt + enable

      +
      +

      0x080A0028

      +       		+

      Read

      +

      Write

      +       		+

      UART_interrupt

      +       		+

      Bit + [31:1] Not used

      +

      Bit + [0] UART RX interrupt pending (Read)

      +

      0 No + interrupt pending

      +

      1 Interrupt + pending

      +

      Bit + [0] Clear UART interrupt (Write)

      +

      0 N/A

      +

      1 Interrupt + cleared

      +
      +

      0x080A002C

      +       		+

      Write

      +       		+

      Timer_Interrupt_enable

      +       		+

      Bit + [31:1] Not used

      +

      Bit + [0] Timer interrupt enable

      +

      0 Interrupt + disable

      +

      1 Interrupt + enable

      +
      +

      0x080A0030

      +       		+

      Read + /

      +

      Write

      +       		+

      Timer_interrupt

      +       		+

      Bit + [31:2] Not used

      +

      Bit + [0] Timer interrupt pending (Read)

      +

      0 No + interrupt pending

      +

      1 Interrupt + pending

      +

      Bit + [1] Reset Timer counter (Write)

      +

      0 N/A

      +

      1 Timer + counter reset

      +

      Bit + [0] Clear Timer interrupt (Write)

      +

      0 N/A

      +

      1 Interrupt + cleared

      +
      +

      0x080A0034

      +       		+

      Write

      +       		+

      Timer_Period

      +       		+

      Bit + [31:0] Interrupt period (write)

      +

      Number + of clock cycles

      +

      between + timer interrupts

      +

      NOTE! + The timer will start at Timer_Periode value and count down + to zero, and generate an interrupt

      +
      +

      .0x080A0038

      +       		+

      Read

      +       		+

      Timer_Counter

      +       		+

      Bit + [31:0] Timer counter (read)

      +


      +

      +
      +


      +

      +       		+


      +

      +       		+


      +

      +       		+


      +

      +
      +


      +

      +       		+


      +

      +       		+


      +

      +       		+


      +

      +
      +


      +

      +       		+


      +

      +       		+


      +

      +       		+


      +

      +
      +


      +

      +       		+


      +

      +       		+


      +

      +       		+


      +

      +
      + \ No newline at end of file diff --git a/zpu/docs/zpuphiregs.odt b/zpu/docs/zpuphiregs.odt deleted file mode 100644 index 4b64d50..0000000 Binary files a/zpu/docs/zpuphiregs.odt and /dev/null differ -- cgit v1.1 From af5b54efbbcbe6e80478ddb24ac2e95a33e63a2d Mon Sep 17 00:00:00 2001 From: oharboe Date: Wed, 16 Apr 2008 12:49:31 +0000 Subject: * zpu/doc/zpupresentation_old.odt: interesting bits moved into zpu_arch.html * zpu/doc/zpupresentation.*: interesting bits moved into zpu_arch.html --- zpu/ChangeLog | 2 ++ zpu/docs/zpu_arch.html | 47 +++++++++++++++++++++++++++++++++++++++ zpu/docs/zpupresentation.odp | Bin 78518 -> 0 bytes zpu/docs/zpupresentation.ppt | Bin 150016 -> 0 bytes zpu/docs/zpupresentation_old.odt | Bin 126772 -> 0 bytes 5 files changed, 49 insertions(+) delete mode 100644 zpu/docs/zpupresentation.odp delete mode 100644 zpu/docs/zpupresentation.ppt delete mode 100644 zpu/docs/zpupresentation_old.odt diff --git a/zpu/ChangeLog b/zpu/ChangeLog index 052c479..3c432e8 100644 --- a/zpu/ChangeLog +++ b/zpu/ChangeLog @@ -1,4 +1,6 @@ 2008-04-16 Øyvind Harboe + * zpu/doc/zpupresentation_old.odt: interesting bits moved into zpu_arch.html + * zpu/doc/zpupresentation.*: interesting bits moved into zpu_arch.html * zpu/docs/zpu_arch.html: added Phi memory map to end of zpu_arch.html * zpu/docs/zpuphiregs.odt: retired * zpu/docs/zpu_arch.html: added. Need to define instruction set. diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index df692a7..a1f61a1 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -1,5 +1,52 @@ +

      Introduction

      +The ZPU is a zero operand, or stack based CPU. The opcodes have a fixed width of 8 bits. +

      +Example: +

      +

      + + IM 5 ; push 5 onto the stack + LOADSP 20 ; push value at memory location SP+20 + ADD ; pop 2 values on the stack and push the result + +
      +As can be seen, a lot of information is packed into the 8 bits, e.g. the IM instruction pushes a 7 bit signed integer onto the stack. +

      +The choice of opcodes is intimately tied to the GCC toolchain capabilities. +

      +

      + + /* simple program showing some interesting qualities of the ZPU toolchain */ + void bar(int); + int j; + void foo(int a, int b, int c) + { + a++; + b+=a; + j=c; + bar(b); + } + +foo: + loadsp 4 ; a is at memory location SP+4 + im 1 + add + loadsp 12 ; b is now at memory location SP+12 + add + loadsp 16 ; c is now at memory location SP+16 + im 24 ; «j» is at absolute memory location 24. +; Notice how the ZPU toolchain is using link-time relaxation +; to squeeze the address into a single no-op + store + im 22 ; the fn bar is at address 22 + call + im 12 + return ; 12 bytes of arguments + return from fn + +
      +

      Instruction set

      Only the base instructions are implemented in the architecture. More advanced instructions, like ASHIFTLEFT are emulated in the illegal instruction vector. diff --git a/zpu/docs/zpupresentation.odp b/zpu/docs/zpupresentation.odp deleted file mode 100644 index 28d9a7b..0000000 Binary files a/zpu/docs/zpupresentation.odp and /dev/null differ diff --git a/zpu/docs/zpupresentation.ppt b/zpu/docs/zpupresentation.ppt deleted file mode 100644 index 100c4a4..0000000 Binary files a/zpu/docs/zpupresentation.ppt and /dev/null differ diff --git a/zpu/docs/zpupresentation_old.odt b/zpu/docs/zpupresentation_old.odt deleted file mode 100644 index 53e1f98..0000000 Binary files a/zpu/docs/zpupresentation_old.odt and /dev/null differ -- cgit v1.1 From 748de9774226a19c32ee1ed6a4e6474e9e0acb27 Mon Sep 17 00:00:00 2001 From: oharboe Date: Thu, 17 Apr 2008 06:42:27 +0000 Subject: * retired Xilinx synthesizing example. It messes up the zpu4 directory. --- zpu/ChangeLog | 2 + zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7pkg.vhd | 31 - zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7wb.vhd | 213 ---- .../dummyfpgalib/ddrsdram/simscripts/ddr_tb.do | 17 - .../dummyfpgalib/ddrsdram/simscripts/ddr_top.do | 111 -- zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_pkg.vhd | 90 -- zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_tb.vhd | 301 ----- zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_top.vhd | 660 ---------- .../zpu4/dummyfpgalib/ddrsdram/src/mt46v16m16.vhd | 1320 -------------------- zpu/hdl/zpu4/src/build.xml | 114 -- zpu/hdl/zpu4/src/ic300.bitgen | 27 - zpu/hdl/zpu4/src/ic300.lso | 1 - zpu/hdl/zpu4/src/ic300.ucf | 146 --- zpu/hdl/zpu4/src/ic300.vhd | 144 --- zpu/hdl/zpu4/src/ic300_config.vhd | 26 - zpu/hdl/zpu4/src/ic300pkg.vhd | 88 -- zpu/hdl/zpu4/src/xmake.filelist | 12 - zpu/hdl/zpu4/src/xmake.filelist.bramsmall | 5 - zpu/hdl/zpu4/src/xmake.xst | 53 - zpu/hdl/zpu4/src/zpuio_bram.vhd | 229 ---- 20 files changed, 2 insertions(+), 3588 deletions(-) delete mode 100644 zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7pkg.vhd delete mode 100644 zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7wb.vhd delete mode 100644 zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_tb.do delete mode 100644 zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_top.do delete mode 100644 zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_pkg.vhd delete mode 100644 zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_tb.vhd delete mode 100644 zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_top.vhd delete mode 100644 zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/mt46v16m16.vhd delete mode 100644 zpu/hdl/zpu4/src/build.xml delete mode 100644 zpu/hdl/zpu4/src/ic300.bitgen delete mode 100644 zpu/hdl/zpu4/src/ic300.lso delete mode 100644 zpu/hdl/zpu4/src/ic300.ucf delete mode 100644 zpu/hdl/zpu4/src/ic300.vhd delete mode 100644 zpu/hdl/zpu4/src/ic300_config.vhd delete mode 100644 zpu/hdl/zpu4/src/ic300pkg.vhd delete mode 100644 zpu/hdl/zpu4/src/xmake.filelist delete mode 100644 zpu/hdl/zpu4/src/xmake.filelist.bramsmall delete mode 100644 zpu/hdl/zpu4/src/xmake.xst delete mode 100644 zpu/hdl/zpu4/src/zpuio_bram.vhd diff --git a/zpu/ChangeLog b/zpu/ChangeLog index 3c432e8..9b722e8 100644 --- a/zpu/ChangeLog +++ b/zpu/ChangeLog @@ -1,3 +1,5 @@ +2008-04-17 Øyvind Harboe + * retired Xilinx synthesizing example. It messes up the zpu4 directory. 2008-04-16 Øyvind Harboe * zpu/doc/zpupresentation_old.odt: interesting bits moved into zpu_arch.html * zpu/doc/zpupresentation.*: interesting bits moved into zpu_arch.html diff --git a/zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7pkg.vhd b/zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7pkg.vhd deleted file mode 100644 index 95fbc18..0000000 --- a/zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7pkg.vhd +++ /dev/null @@ -1,31 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -package arm7 is - - component arm7wb - generic( - simulate_io_time : boolean := false); - port ( areset : in std_logic; - cpu_clk : in std_logic; - cpu_clk_2x : in std_logic; - cpu_a_p : in std_logic_vector(20 downto 0); - cpu_wr_n_p : in std_logic_vector(1 downto 0); - cpu_cs_n_p : in std_logic_vector(3 downto 1); - cpu_oe_n_p : in std_logic; - cpu_d_p : inout std_logic_vector(15 downto 0); - cpu_irq_p : out std_logic_vector(1 downto 0); - cpu_fiq_p : out std_logic; - cpu_wait_n_p : out std_logic; - - cpu_din : out std_logic_vector(15 downto 0); - cpu_a : out std_logic_vector(20 downto 0); - cpu_we : out std_logic_vector(1 downto 0); - cpu_re : out std_logic; - cpu_dout : in std_logic_vector(15 downto 0)); - end component; - -end arm7; - - \ No newline at end of file diff --git a/zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7wb.vhd b/zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7wb.vhd deleted file mode 100644 index 55b8125..0000000 --- a/zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7wb.vhd +++ /dev/null @@ -1,213 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity arm7wb is - generic( - simulate_io_time : boolean := false); - port ( areset : in std_logic; - cpu_clk : in std_logic; - cpu_clk_2x : in std_logic; - cpu_a_p : in std_logic_vector(20 downto 0); - cpu_wr_n_p : in std_logic_vector(1 downto 0); - cpu_cs_n_p : in std_logic_vector(3 downto 1); - cpu_oe_n_p : in std_logic; - cpu_d_p : inout std_logic_vector(15 downto 0); - cpu_irq_p : out std_logic_vector(1 downto 0); - cpu_fiq_p : out std_logic; - cpu_wait_n_p : out std_logic; - - cpu_din : out std_logic_vector(15 downto 0); - cpu_a : out std_logic_vector(20 downto 0); - cpu_we : out std_logic_vector(1 downto 0); - cpu_re : out std_logic; - cpu_dout : in std_logic_vector(15 downto 0)); -end arm7wb; - -architecture behave of arm7wb is - -attribute keep : string; - -signal cpu_oe_n : std_logic; -signal cpu_fiq : std_logic; -signal cpu_wait_n : std_logic; -signal cpu_clk_toggle : std_logic; -signal cpu_clk_smp1 : std_logic; -signal cpu_clk_smp2 : std_logic; -signal cpu_clk_phase : std_logic; -signal cpu_oe_n_del : std_logic; -signal cpu_a_smp : std_logic_vector(20 downto 0); -signal cpu_d_smp : std_logic_vector(15 downto 0); - -signal int_oe_n : std_logic_vector(15 downto 0); -attribute keep of int_oe_n:signal is "true"; - -signal cpu_irq : std_logic_vector(1 downto 0); -signal cpu_wr_n : std_logic_vector(1 downto 0); -signal cpu_cs_n : std_logic_vector(3 downto 1); - -signal dout : std_logic_vector(15 downto 0); -signal cpu_d_p_out : std_logic_vector(15 downto 0); -signal read_cnt : std_logic_vector(1 downto 0); - -signal cpu_wr_n_p_del : std_logic_vector(1 downto 0); -signal cpu_a_p_del : std_logic_vector(20 downto 0); -signal cpu_d_p_del : std_logic_vector(15 downto 0); -signal cpu_cs_n_p_del : std_logic_vector(3 downto 1); -signal cpu_oe_n_p_del : std_logic; - -constant Sim_Delay : time := 0.5 ns; -constant Clock_2_Out : time := 5.5 ns; -constant Input_Setup : time := 2.5 ns; - -begin - - cpu_wait_n <= '1'; - cpu_fiq <= '1'; - cpu_irq <= "11"; - - iotimingon: - if simulate_io_time generate - begin - cpu_wr_n_p_del <= "XX" after 0 ns, cpu_wr_n_p after Input_Setup; - cpu_a_p_del <= "XXXXXXXXXXXXXXXXXXXXX" after 0 ns, cpu_a_p after Input_Setup; - cpu_d_p_del <= "XXXXXXXXXXXXXXXX" after 0 ns, cpu_d_p after Input_Setup; - cpu_cs_n_p_del <= "XXX" after 0 ns, cpu_cs_n_p after Input_Setup; - cpu_oe_n_p_del <= 'X' after 0 ns, cpu_oe_n_p after Input_Setup; - end generate; - - iotimingoff: - if not simulate_io_time generate - begin - cpu_wr_n_p_del <= cpu_wr_n_p; - cpu_a_p_del <= cpu_a_p; - cpu_d_p_del <= cpu_d_p; - cpu_cs_n_p_del <= cpu_cs_n_p; - cpu_oe_n_p_del <= cpu_oe_n_p; - end generate; - - process(cpu_clk, areset) -- Toggle FF with 1x clock to find phase - begin - if areset = '1' then - cpu_clk_toggle <= '0'; - elsif (cpu_clk'event and cpu_clk = '1') then - cpu_clk_toggle <= not(cpu_clk_toggle); - end if; - end process; - - process(cpu_clk_2x, areset) -- Find phase relationsship between 1x and 2x clock - begin - if areset = '1' then - cpu_clk_smp1 <= '0'; - cpu_clk_smp2 <= '1'; - cpu_clk_phase <= '0'; - elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then - cpu_clk_smp1 <= cpu_clk_toggle; - cpu_clk_smp2 <= cpu_clk_smp1; - if cpu_clk_smp1 = '1' and cpu_clk_smp2 = '0' then - cpu_clk_phase <= '0' after Sim_Delay; - else - cpu_clk_phase <= not(cpu_clk_phase) after Sim_Delay; - end if; - end if; - end process; - - process(cpu_clk_2x, areset) -- Sample input signals - begin - if areset = '1' then - cpu_oe_n <= '1'; - cpu_a_smp <= "000000000000000000000"; - cpu_d_smp <= "0000000000000000"; - cpu_wr_n <= "11"; - cpu_cs_n <= "111"; - elsif (cpu_clk_2x = '1' and cpu_clk_2x'event) then - cpu_oe_n <= cpu_oe_n_p_del after Sim_Delay; - cpu_a_smp <= cpu_a_p_del after Sim_Delay; - cpu_d_smp <= cpu_d_p_del after Sim_Delay; - cpu_wr_n <= cpu_wr_n_p_del after Sim_Delay; - cpu_cs_n <= cpu_cs_n_p_del after Sim_Delay; - end if; - end process; - - cpu_d_out: - for i in 0 to 15 generate - begin - process(cpu_clk_2x, areset) - begin - if areset = '1' then - cpu_d_p(i) <= 'Z'; - elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then - if int_oe_n(i) = '0' then - cpu_d_p(i) <= cpu_d_p_out(i) after Clock_2_Out; - else - cpu_d_p(i) <= 'Z' after Clock_2_Out; - end if; - end if; - end process; - end generate; - - process(cpu_clk, areset) -- Clocked output pins - begin - if areset = '1' then - cpu_d_p_out <= "1111111111111111"; - cpu_wait_n_p <= '1'; - cpu_irq_p <= "11"; - cpu_fiq_p <= '1'; - elsif (cpu_clk = '1' and cpu_clk'event) then - cpu_d_p_out <= cpu_dout; - cpu_wait_n_p <= '1'; - cpu_irq_p <= "11"; - cpu_fiq_p <= '1'; - end if; - end process; - - process(cpu_clk, areset) -- Generate control signals - begin - if areset = '1' then - int_oe_n <= "1111111111111111"; - read_cnt <= "00"; - cpu_we <= "00"; - cpu_re <= '0'; - cpu_a <= "000000000000000000000"; - cpu_din <= "0000000000000000"; - elsif (cpu_clk = '1' and cpu_clk'event) then - - cpu_a <= cpu_a_smp; - cpu_din <= cpu_d_smp; - - cpu_oe_n_del <= cpu_oe_n; - - if cpu_cs_n(1) = '1' then - read_cnt <= "00"; - else - read_cnt <= read_cnt + '1'; - end if; - - if read_cnt = "01" and cpu_cs_n(1) = '0' and cpu_wr_n(0) = '0' then - cpu_we(0) <= '1'; - else - cpu_we(0) <= '0'; - end if; - - if read_cnt = "01" and cpu_cs_n(1) = '0' and cpu_wr_n(1) = '0' then - cpu_we(1) <= '1'; - else - cpu_we(1) <= '0'; - end if; - - if read_cnt = "00" and cpu_cs_n(1) = '0' and cpu_oe_n = '0' then - cpu_re <= '1'; - else - cpu_re <= '0'; - end if; - - if read_cnt = "01" and cpu_cs_n(1) = '0' and cpu_oe_n = '0' then - int_oe_n <= "0000000000000000"; - else - int_oe_n <= "1111111111111111"; - end if; - - end if; - end process; - -end behave; diff --git a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_tb.do b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_tb.do deleted file mode 100644 index d2c22cf..0000000 --- a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_tb.do +++ /dev/null @@ -1,17 +0,0 @@ -vlib zylin -vcom -93 -explicit -work zylin ../ddrsdram/src/ddr_pkg.vhd -vcom -93 -explicit -work zylin ../ddrsdram/src/ddr_top.vhd -vcom -93 -explicit -work zylin ../ddrsdram/src/mt46v16m16.vhd -vcom -93 -explicit -work zylin ../ddrsdram/src/ddr_tb.vhd -vlib work -vsim -t 1ps zylin.ddr_tb -view wave -view signals -radix hex -add wave * -add wave sim:/ddr_tb/ddr_ctrl/* -force -freeze sim:/ddr_tb/areset 1 0 -run 10 ns -force -freeze sim:/ddr_tb/areset 0 0 -when sim:/ddr_tb/break_out stop -run 10 ms \ No newline at end of file diff --git a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_top.do b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_top.do deleted file mode 100644 index 31dd294..0000000 --- a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_top.do +++ /dev/null @@ -1,111 +0,0 @@ -vlib zylin -vcom -93 -explicit -work zylin ../ddrsdram/src/ddr_pkg.vhd -vcom -93 -explicit -work zylin ../ddrsdram/src/ddr_top.vhd -vlib work -vsim -t 1ps zylin.ddr_top -view wave -view signals -radix hex -# Add wave signals - -add wave -divider "System" -add wave sim:/ddr_top/areset -add wave sim:/ddr_top/cpu_clk -add wave sim:/ddr_top/cpu_clk_2x -add wave sim:/ddr_top/cpu_clk_4x -add wave sim:/ddr_top/ddr_in_clk -add wave sim:/ddr_top/ddr_in_clk_2x - -add wave -divider "Ctrl interface" -add wave sim:/ddr_top/cpu_clk -add wave sim:/ddr_top/ddr_data_read -add wave sim:/ddr_top/ddr_data_write -add wave sim:/ddr_top/ddr_req -add wave sim:/ddr_top/ddr_rd_wr_n -add wave sim:/ddr_top/ddr_req_len -add wave sim:/ddr_top/ddr_wr_mask -add wave sim:/ddr_top/ddr_read_en -add wave sim:/ddr_top/ddr_write_en -add wave sim:/ddr_top/ddr_command -add wave sim:/ddr_top/ddr_command_we - -add wave -divider "DDR interface" -add wave sim:/ddr_top/sdr_clk_p -add wave sim:/ddr_top/sdr_clk_n_p -add wave sim:/ddr_top/cke_q_p -add wave sim:/ddr_top/cs_qn_p -add wave sim:/ddr_top/ras_qn_p -add wave sim:/ddr_top/cas_qn_p -add wave sim:/ddr_top/we_qn_p -add wave sim:/ddr_top/dm_q_p -add wave sim:/ddr_top/dqs_q_p -add wave sim:/ddr_top/ba_q_p -add wave sim:/ddr_top/sdr_a_p -add wave sim:/ddr_top/sdr_d_p - -add wave -divider "Internal signals" -add wave sim:/ddr_top/clk2_phase -add wave sim:/ddr_top/clk4_phase -add wave sim:/ddr_top/ddr_state -add wave sim:/ddr_top/sdr_oe_n -add wave sim:/ddr_top/sdr_smp -add wave sim:/ddr_top/sdr_d - - -# Add input signals -force -freeze sim:/ddr_top/cpu_clk_4x 1 0, 0 {1.875 ns} -r 3.75 -run 100 ps -force -freeze sim:/ddr_top/cpu_clk_2x 1 0, 0 {3.75 ns} -r 7.5 -run 100 ps -force -freeze sim:/ddr_top/cpu_clk 1 0, 0 {7.5 ns} -r 15 -force -freeze sim:/ddr_top/ddr_in_clk 1 2ns, 0 {5.75 ns} -r 7.5 -force -freeze sim:/ddr_top/ddr_in_clk_2x 0 0.125ns, 1 {2 ns} -r 3.75 - -force -freeze sim:/ddr_top/areset 1 0 -force -freeze sim:/ddr_top/ddr_command 0000 0 -force -freeze sim:/ddr_top/ddr_command_we 0 0 -force -freeze sim:/ddr_top/ddr_data_write 1234abcd 0 -force -freeze sim:/ddr_top/ddr_req 0 0 -force -freeze sim:/ddr_top/ddr_req_adr 000000 0 -force -freeze sim:/ddr_top/ddr_rd_wr_n 0 0 -force -freeze sim:/ddr_top/ddr_req_len 000 0 -force -freeze sim:/ddr_top/ddr_wr_mask 0 0 - -# Start simulation -run 45 -force -freeze sim:/ddr_top/areset 0 0 -run 92 -# DDR Command -force -freeze sim:/ddr_top/ddr_command 000A 0 -force -freeze sim:/ddr_top/ddr_command_we 1 0 -run 15 -force -freeze sim:/ddr_top/ddr_command 0000 0 -force -freeze sim:/ddr_top/ddr_command_we 0 0 -run 90 -# DDR Read -force -freeze sim:/ddr_top/ddr_req 1 0 -force -freeze sim:/ddr_top/ddr_req_adr 00ABCD 0 -force -freeze sim:/ddr_top/ddr_rd_wr_n 1 0 -force -freeze sim:/ddr_top/ddr_req_len 000 0 -force -freeze sim:/ddr_top/ddr_wr_mask 0 0 -run 15 -force -freeze sim:/ddr_top/ddr_req 0 0 -force -freeze sim:/ddr_top/ddr_req_adr 000000 0 -force -freeze sim:/ddr_top/ddr_rd_wr_n 0 0 -force -freeze sim:/ddr_top/ddr_req_len 000 0 -force -freeze sim:/ddr_top/ddr_wr_mask 0 0 -run 150 -# DDR Write -force -freeze sim:/ddr_top/ddr_req 1 0 -force -freeze sim:/ddr_top/ddr_req_adr 00ABCD 0 -force -freeze sim:/ddr_top/ddr_rd_wr_n 0 0 -force -freeze sim:/ddr_top/ddr_req_len 000 0 -force -freeze sim:/ddr_top/ddr_wr_mask 0 0 -run 15 -force -freeze sim:/ddr_top/ddr_req 0 0 -force -freeze sim:/ddr_top/ddr_req_adr 000000 0 -force -freeze sim:/ddr_top/ddr_rd_wr_n 0 0 -force -freeze sim:/ddr_top/ddr_req_len 000 0 -force -freeze sim:/ddr_top/ddr_wr_mask 0 0 -run 180 - diff --git a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_pkg.vhd b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_pkg.vhd deleted file mode 100644 index 95f4b8a..0000000 --- a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_pkg.vhd +++ /dev/null @@ -1,90 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -package ddr is - - component ddr_top - generic( - simulate_io_time : boolean := false); - port ( -- Asyncronous reset and clocks - areset : in std_logic; - cpu_clk : in std_logic; - cpu_clk_2x : in std_logic; - cpu_clk_4x : in std_logic; - ddr_in_clk : in std_logic; - ddr_in_clk_2x : in std_logic; - - -- Command interface - ddr_command : in std_logic_vector(15 downto 0); - ddr_command_we : in std_logic; - refresh_en : in std_logic; - - - -- Data interface signals - ddr_data_read : out std_logic_vector(31 downto 0); -- Data read from DDR SDRAM - ddr_data_write : in std_logic_vector(35 downto 0); -- Data to be written to DDR SDRAM - ddr_req_adr : in std_logic_vector(23 downto 1); -- Request address - ddr_req : in std_logic; -- Request DDR SDRAM access - ddr_req_ack : out std_logic; -- Request acknowledge - ddr_busy : out std_logic; -- Request acknowledge - ddr_rd_wr_n : in std_logic; -- Access type 1=READ, 0=WRITE - ddr_req_len : in std_logic; -- Number of 16-bits words to transfer (0=2, 1=8) - ddr_read_en : out std_logic; -- Enable signal for read data - ddr_write_en : out std_logic; -- Enable (read) signal for data write - - -- DDR SDRAM Signals - sdr_clk_p : out std_logic; -- ddr_sdram_clock - sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock - cke_q_p : out std_logic; -- clock enable - cs_qn_p : out std_logic; -- /chip select - ras_qn_p : inout std_logic; -- /ras - cas_qn_p : inout std_logic; -- /cas - we_qn_p : inout std_logic; -- /write enable - dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00" - dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write - ba_q_p : out std_logic_vector(1 downto 0); -- bank select - sdr_a_p : out std_logic_vector(12 downto 0); -- address bus - sdr_d_p : inout std_logic_vector(15 downto 0)); -- bidir data bus - end component; - - component MT46V16M16 - GENERIC ( -- Timing for -75Z CL2 - tCK : TIME := 7.500 ns; - tCH : TIME := 3.375 ns; -- 0.45*tCK - tCL : TIME := 3.375 ns; -- 0.45*tCK - tDH : TIME := 0.500 ns; - tDS : TIME := 0.500 ns; - tIH : TIME := 0.900 ns; - tIS : TIME := 0.900 ns; - tMRD : TIME := 15.000 ns; - tRAS : TIME := 40.000 ns; - tRAP : TIME := 20.000 ns; - tRC : TIME := 65.000 ns; - tRFC : TIME := 75.000 ns; - tRCD : TIME := 20.000 ns; - tRP : TIME := 20.000 ns; - tRRD : TIME := 15.000 ns; - tWR : TIME := 15.000 ns; - addr_bits : INTEGER := 13; - data_bits : INTEGER := 16; - cols_bits : INTEGER := 9 - ); - PORT ( - Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); - Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ"; - Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - Clk : IN STD_LOGIC; - Clk_n : IN STD_LOGIC; - Cke : IN STD_LOGIC; - Cs_n : IN STD_LOGIC; - Ras_n : IN STD_LOGIC; - Cas_n : IN STD_LOGIC; - We_n : IN STD_LOGIC; - Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); - end component; - -end ddr; - \ No newline at end of file diff --git a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_tb.vhd b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_tb.vhd deleted file mode 100644 index 5666532..0000000 --- a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_tb.vhd +++ /dev/null @@ -1,301 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -library zylin; -use zylin.ddr.all; - -entity ddr_tb is - port ( areset : in std_logic; - break_out : out std_logic); -end ddr_tb; - -architecture behave of ddr_tb is - -signal cpu_clk : std_logic; -signal cpu_clk_2x : std_logic; -signal cpu_clk_4x : std_logic; -signal ddr_in_clk : std_logic; -signal ddr_in_clk_2x : std_logic; - -signal ddr_command : std_logic_vector(15 downto 0); -signal ddr_command_we : std_logic; - -signal ddr_data_read : std_logic_vector(31 downto 0); -- Data read from DDR SDRAM -signal ddr_data_write : std_logic_vector(35 downto 0); -- Data to be written to DDR SDRAM -signal ddr_req_adr : std_logic_vector(23 downto 1); -- Request address -signal ddr_req : std_logic; -- Request DDR SDRAM access -signal ddr_req_ack : std_logic; -- Request acknowledge -signal ddr_busy : std_logic; -- Request acknowledge -signal ddr_rd_wr_n : std_logic; -- Access type 1=READ, 0=WRITE -signal ddr_req_len : std_logic; -- Number of 16-bits words to transfer -signal ddr_read_en : std_logic; -- Enable signal for read data -signal ddr_write_en : std_logic; -- Enable (read) signal for data write -signal refresh_en : std_logic; - -signal sdr_clk_p : std_logic; -- ddr_sdram_clock -signal sdr_clk_n_p : std_logic; -- /ddr_sdram_clock -signal cke_q_p : std_logic; -- clock enable -signal cs_qn_p : std_logic; -- /chip select -signal ras_qn_p : std_logic; -- /ras -signal cas_qn_p : std_logic; -- /cas -signal we_qn_p : std_logic; -- /write enable -signal dm_q_p : std_logic_vector(1 downto 0); -- data mask bits, set to "00" -signal dqs_q_p : std_logic_vector(1 downto 0); -- data strobe, only for write -signal ba_q_p : std_logic_vector(1 downto 0); -- bank select -signal sdr_a_p : std_logic_vector(12 downto 0); -- address bus -signal sdr_d_p : std_logic_vector(15 downto 0); -- bidir data bus - -constant min_time : time := 1.875 ns; - -begin - - clock1: - process - begin - loop - cpu_clk_4x <= '1'; - wait for min_time; - cpu_clk_4x <= '0'; - wait for min_time; - end loop; - end process; - - clock2: - process - begin - loop - cpu_clk_2x <= '1' after 100 ps; - wait until rising_edge(cpu_clk_4x); - cpu_clk_2x <= '0' after 100 ps; - wait until rising_edge(cpu_clk_4x); - end loop; - end process; - - clock3: - process - begin - loop - cpu_clk <= '1' after 100 ps; - wait until rising_edge(cpu_clk_2x); - cpu_clk <= '0' after 100 ps; - wait until rising_edge(cpu_clk_2x); - end loop; - end process; - - ddr_in_clk_2x <= cpu_clk_4x after 1 ns; - - clock4: - process - begin - loop - ddr_in_clk <= '0' after 100 ps; - wait until rising_edge(ddr_in_clk_2x); - ddr_in_clk <= '1' after 100 ps; - wait until rising_edge(ddr_in_clk_2x); - end loop; - end process; - - inputdata: - process - begin - -- Wait until global reset released - loop - ddr_command <= x"0000"; - ddr_command_we <= '0'; - ddr_data_write <= x"000000000"; - ddr_req <= '0'; - ddr_req_adr <= "00000000000000000000000"; - ddr_rd_wr_n <= '0'; - ddr_req_len <= '0'; - break_out <= '0'; - refresh_en <= '0'; - - wait until falling_edge(areset); - - -- DDR initialization sequence - -- Wait more than 200 us - wait for 201000 ns; - - -- Send precharge command - wait until rising_edge(cpu_clk); - ddr_command <= x"8000"; - ddr_command_we <= '1'; - wait until rising_edge(cpu_clk); - ddr_command <= x"0000"; - ddr_command_we <= '0'; - - -- Wait for 1 us - wait for 1000 ns; - - -- Load extended mode register - -- Enable DLL - -- Normal drive strength - wait until rising_edge(cpu_clk); - ddr_command <= x"2000"; - ddr_command_we <= '1'; - wait until rising_edge(cpu_clk); - ddr_command <= x"0000"; - ddr_command_we <= '0'; - - -- Wait for 1 us - wait for 1000 ns; - - -- Load mode register - -- Burst length: 2 - -- Burst type: Sequential - -- Cas latency: 2 - -- Reset DLL - wait until rising_edge(cpu_clk); - ddr_command <= x"0121"; - ddr_command_we <= '1'; - wait until rising_edge(cpu_clk); - ddr_command <= x"0000"; - ddr_command_we <= '0'; - - -- Wait for 1 us - wait for 1000 ns; - - -- Send precharge command - wait until rising_edge(cpu_clk); - ddr_command <= x"8000"; - ddr_command_we <= '1'; - wait until rising_edge(cpu_clk); - ddr_command <= x"0000"; - ddr_command_we <= '0'; - - -- Enable refresh - refresh_en <= '1'; - - -- Wait 30 us (minimum 2 autorefresh cycles) - wait for 30000 ns; - - -- Load mode register - -- Burst length: 2 - -- Burst type: Sequential - -- Cas latency: 2 - -- Deactivate Reset DLL - wait until rising_edge(cpu_clk); - ddr_command <= x"0021"; - ddr_command_we <= '1'; - wait until rising_edge(cpu_clk); - ddr_command <= x"0000"; - ddr_command_we <= '0'; - - -- Wait for 2 us (DLL stable) - wait for 2000 ns; - - -- Write data to DDR - wait until rising_edge(cpu_clk_2x); - ddr_data_write <= x"312345678"; - ddr_req <= '1'; - ddr_req_adr <= "00000000000000000000000"; - ddr_rd_wr_n <= '0'; - ddr_req_len <= '0'; - wait until rising_edge(ddr_write_en); - wait until rising_edge(cpu_clk_2x); - ddr_req <= '0'; - ddr_req_adr <= "00000000000000000000000"; - ddr_rd_wr_n <= '0'; - ddr_req_len <= '0'; - ddr_data_write <= x"000000000"; - wait for 100 ns; - - -- Read data from DDR - wait until rising_edge(cpu_clk_2x); - ddr_req <= '1'; - ddr_req_adr <= "00000000000000000000000"; - ddr_rd_wr_n <= '1'; - ddr_req_len <= '0'; - wait until rising_edge(ddr_req_ack); - wait until rising_edge(cpu_clk_2x); - ddr_req <= '0'; - ddr_req_adr <= "00000000000000000000000"; - ddr_rd_wr_n <= '0'; - ddr_req_len <= '0'; - ddr_data_write <= x"000000000"; - - - - wait for 100 ns; - break_out <= '1'; - wait for 100 ns; - - end loop; - - end process; - - ddr_ctrl: - ddr_top port map( - areset => areset, - cpu_clk => cpu_clk, - cpu_clk_2x => cpu_clk_2x, - cpu_clk_4x => cpu_clk_4x, - ddr_in_clk => ddr_in_clk, - ddr_in_clk_2x => ddr_in_clk_2x, - - -- Command interface - ddr_command => ddr_command, - ddr_command_we => ddr_command_we, - refresh_en => refresh_en, - - -- Data interface signals - ddr_data_read => ddr_data_read, - ddr_data_write => ddr_data_write, - ddr_req_adr => ddr_req_adr, - ddr_req => ddr_req, - ddr_req_ack => ddr_req_ack, - ddr_busy => ddr_busy, - ddr_rd_wr_n => ddr_rd_wr_n, - ddr_req_len => ddr_req_len, - ddr_read_en => ddr_read_en, - ddr_write_en => ddr_write_en, - -- DDR SDRAM Signals - sdr_clk_p => sdr_clk_p, - sdr_clk_n_p => sdr_clk_n_p, - cke_q_p => cke_q_p, - cs_qn_p => cs_qn_p, - ras_qn_p => ras_qn_p, - cas_qn_p => cas_qn_p, - we_qn_p => we_qn_p, - dm_q_p => dm_q_p, - dqs_q_p => dqs_q_p, - ba_q_p => ba_q_p, - sdr_a_p => sdr_a_p, - sdr_d_p => sdr_d_p); - - myram: - MT46V16M16 generic map( - tCK => 7.500 ns, - tCH => 3.375 ns, -- 0.45*tCK - tCL => 3.375 ns, -- 0.45*tCK - tDH => 0.500 ns, - tDS => 0.500 ns, - tIH => 0.900 ns, - tIS => 0.900 ns, - tMRD => 15.000 ns, - tRAS => 40.000 ns, - tRAP => 20.000 ns, - tRC => 65.000 ns, - tRFC => 75.000 ns, - tRCD => 20.000 ns, - tRP => 20.000 ns, - tRRD => 15.000 ns, - tWR => 15.000 ns, - addr_bits => 13, - data_bits => 16, - cols_bits => 9) - port map( - Dq => sdr_d_p, - Dqs => dqs_q_p, - Addr => sdr_a_p, - Ba => ba_q_p, - Clk => sdr_clk_p, - Clk_n => sdr_clk_n_p, - Cke => cke_q_p, - Cs_n => cs_qn_p, - Ras_n => ras_qn_p, - Cas_n => cas_qn_p, - We_n => we_qn_p, - Dm => dm_q_p); - -end behave; diff --git a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_top.vhd b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_top.vhd deleted file mode 100644 index d5e98e1..0000000 --- a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_top.vhd +++ /dev/null @@ -1,660 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity ddr_top is - generic( - simulate_io_time : boolean := false); - port ( -- Asyncronous reset and clocks - areset : in std_logic; - cpu_clk : in std_logic; - cpu_clk_2x : in std_logic; - cpu_clk_4x : in std_logic; - ddr_in_clk : in std_logic; - ddr_in_clk_2x : in std_logic; - - -- Command interface - ddr_command : in std_logic_vector(15 downto 0); - ddr_command_we : in std_logic; - refresh_en : in std_logic; - - -- Data interface signals - ddr_data_read : out std_logic_vector(31 downto 0); -- Data read from DDR SDRAM - ddr_data_write : in std_logic_vector(35 downto 0); -- Data to be written to DDR SDRAM - ddr_req_adr : in std_logic_vector(23 downto 1); -- Request address - ddr_req : in std_logic; -- Request DDR SDRAM access - ddr_req_ack : out std_logic; -- Request acknowledge - ddr_busy : out std_logic; -- Request acknowledge - ddr_rd_wr_n : in std_logic; -- Access type 1=READ, 0=WRITE - ddr_req_len : in std_logic; -- Number of 16-bits words to transfer (0=2, 1=8) - ddr_read_en : out std_logic; -- Enable signal for read data - ddr_write_en : out std_logic; -- Enable (read) signal for data write - - -- DDR SDRAM Signals - sdr_clk_p : out std_logic; -- ddr_sdram_clock - sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock - cke_q_p : out std_logic; -- clock enable - cs_qn_p : out std_logic; -- /chip select - ras_qn_p : inout std_logic; -- /ras - cas_qn_p : inout std_logic; -- /cas - we_qn_p : inout std_logic; -- /write enable - dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00" - dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write - ba_q_p : out std_logic_vector(1 downto 0); -- bank select - sdr_a_p : out std_logic_vector(12 downto 0); -- address bus - sdr_d_p : inout std_logic_vector(15 downto 0)); -- bidir data bus -end ddr_top; - -architecture behave of ddr_top is - -attribute keep : string; - -signal cpu_clk_tog : std_logic; -signal ddr_cmd : std_logic_vector(15 downto 0); -signal ddr_cmd_we_smp : std_logic; -signal new_command : std_logic; - -signal cpu_clk_2x_smp1 : std_logic; -signal cpu_clk_2x_smp2 : std_logic; -signal cpu_clk_4x_smp1 : std_logic; -signal cpu_clk_4x_smp2 : std_logic; - -signal clk2_phase : std_logic; -signal clk4_phase : std_logic_vector(3 downto 0); -signal clk4_phase_short : std_logic_vector(1 downto 0); - -signal ddr_clk_tog : std_logic; -signal ddr_clk_smp1 : std_logic; -signal ddr_clk_smp2 : std_logic; -signal ddr_clk_phase : std_logic; - -signal smp_req_adr : std_logic_vector(23 downto 1); -signal smp_req_type : std_logic; -signal smp_req_len : std_logic; -signal ddr_write_en_int : std_logic; -signal ddr_read_en_int : std_logic; - -signal dqs_q : std_logic_vector(1 downto 0); -signal dqs_oe_n : std_logic_vector(1 downto 0); -attribute keep of dqs_oe_n:signal is "true"; -signal cas_qn : std_logic; -signal ras_qn : std_logic; -signal we_qn : std_logic; -signal ba_q : std_logic_vector(1 downto 0); -signal sdr_clk : std_logic; -signal sdr_clk_n : std_logic; -signal sdr_a : std_logic_vector(12 downto 0); -signal sdr_d : std_logic_vector(15 downto 0); -signal sdr_smp : std_logic_vector(35 downto 0); -signal sdr_oe_n : std_logic_vector(15 downto 0); -attribute keep of sdr_oe_n:signal is "true"; -signal sdr_oe_ctrl : std_logic; -signal sdr_wr_msw : std_logic_vector(17 downto 0); -attribute keep of sdr_wr_msw:signal is "true"; -signal dm_q : std_logic_vector(1 downto 0); - -signal cas_n_smp : std_logic; -signal ras_n_smp : std_logic; -signal we_n_smp : std_logic; -signal read_start_sig : std_logic; -signal sdr_d_in : std_logic_vector(15 downto 0); -signal read_time_cnt : std_logic_vector(1 downto 0); -signal read_input_en : std_logic; -signal ddr_data_read_int : std_logic_vector(31 downto 0); - -signal refresh_pend : std_logic; -signal refresh_end : std_logic; -signal refresh_cnt : std_logic_vector(9 downto 0); -signal refresh_wait_cnt : std_logic_vector(2 downto 0); -signal refresh_wait_end : std_logic; - -signal cas_qn_p_del : std_logic; -signal ras_qn_p_del : std_logic; -signal we_qn_p_del : std_logic; -signal sdr_d_p_del : std_logic_vector(15 downto 0); - -type state_type is (idle, act, act_nop1, act_nop2, rd_wr, rd_nop1, - rd_nop2, pre, pre_nop1, pre_nop2, wr_nop1, wr_nop2, - wr_nop3, cmd, cpu_pre, refresh, refresh_wait); -signal ddr_state : state_type; - -constant Clk_to_Output : time := 2.2 ns; -constant Sim_Delay : time := 0.5 ns; -constant Input_Setup : time := 2.5 ns; - -constant Refresh_Interval : std_logic_vector(9 downto 0) := "1111100110"; - -begin - - iotimingon: - if simulate_io_time generate - begin - cas_qn_p_del <= 'X' after 0 ns, cas_qn_p after Input_Setup; - ras_qn_p_del <= 'X' after 0 ns, ras_qn_p after Input_Setup; - we_qn_p_del <= 'X' after 0 ns, we_qn_p after Input_Setup; - sdr_d_p_del <= "XXXXXXXXXXXXXXXX" after 0 ns, sdr_d_p after Input_Setup; - end generate; - - iotimingoff: - if not simulate_io_time generate - begin - cas_qn_p_del <= cas_qn_p; - ras_qn_p_del <= ras_qn_p; - we_qn_p_del <= we_qn_p; - sdr_d_p_del <= sdr_d_p; - end generate; - - ddr_write_en <= ddr_write_en_int; - ddr_read_en <= ddr_read_en_int; - ddr_data_read <= ddr_data_read_int; - - process(cpu_clk, areset) -- Toggle a flip-flop with cpu_clk, in order - begin -- to find phase relation with 2x and 4x clocks - if areset = '1' then - cpu_clk_tog <= '0'; - elsif (cpu_clk'event and cpu_clk = '1') then - cpu_clk_tog <= not(cpu_clk_tog) after Sim_Delay; - end if; - end process; - - process(cpu_clk_2x, areset) -- Find phase relation between cpu_clk and cpu_clk_2x - begin - if areset = '1' then - cpu_clk_2x_smp1 <= '0'; - cpu_clk_2x_smp2 <= '0'; - clk2_phase <= '0'; - elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then - cpu_clk_2x_smp1 <= cpu_clk_tog after Sim_Delay; - cpu_clk_2x_smp2 <= cpu_clk_2x_smp1 after Sim_Delay; - if (cpu_clk_2x_smp1 = '1' and cpu_clk_2x_smp2 = '0') then - clk2_phase <= '0' after Sim_Delay; - else - clk2_phase <= not(clk2_phase) after Sim_Delay; - end if; - end if; - end process; - - process(cpu_clk_4x, areset) -- Find phase relation between cpu_clk and cpu_clk_4x - begin - if areset = '1' then - cpu_clk_4x_smp1 <= '0'; - cpu_clk_4x_smp2 <= '0'; - clk4_phase <= "0000"; - clk4_phase_short <= "00"; - elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then - cpu_clk_4x_smp1 <= cpu_clk_tog after Sim_Delay; - cpu_clk_4x_smp2 <= cpu_clk_4x_smp1 after Sim_Delay; - if (cpu_clk_4x_smp1 = '1' and cpu_clk_4x_smp2 = '0') then - clk4_phase <= "0100" after Sim_Delay; - clk4_phase_short <= "01" after Sim_Delay; - else - clk4_phase <= (clk4_phase(2 downto 0) & clk4_phase(3)) after Sim_Delay; - clk4_phase_short <= clk4_phase_short(0) & clk4_phase_short(1); - end if; - end if; - end process; - - process(cpu_clk_4x, areset) -- - begin - if areset = '1' then - sdr_clk <= '0'; - sdr_clk_n <= '0'; - elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then - if clk4_phase_short(0) = '1' then - sdr_clk <= '1' after Sim_Delay; - else - sdr_clk <= '0' after Sim_Delay; - end if; - if clk4_phase_short(1) = '1' then - sdr_clk_n <= '1' after Sim_Delay; - else - sdr_clk_n <= '0' after Sim_Delay; - end if; - end if; - end process; - - cke_q_p <= '1' after Clk_to_Output; - cs_qn_p <= '0' after Clk_to_Output; - - process(cpu_clk_4x, areset) -- - begin - if areset = '1' then - ras_qn_p <= '1'; - cas_qn_p <= '1'; - we_qn_p <= '1'; - dqs_q_p <= "ZZ"; - sdr_a_p <= "0000000000000"; - ba_q_p <= "00"; - sdr_clk_p <= '0'; - sdr_clk_n_p <= '1'; - elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then - ras_qn_p <= transport ras_qn after Clk_to_Output; - cas_qn_p <= transport cas_qn after Clk_to_Output; - we_qn_p <= transport we_qn after Clk_to_Output; - if dqs_oe_n(0) = '0' then - dqs_q_p(0) <= transport dqs_q(0) after Clk_to_Output; - else - dqs_q_p(0) <= transport 'Z' after Clk_to_Output; - end if; - if dqs_oe_n(1) = '0' then - dqs_q_p(1) <= transport dqs_q(1) after Clk_to_Output; - else - dqs_q_p(1) <= transport 'Z' after Clk_to_Output; - end if; - sdr_a_p <= transport sdr_a after Clk_to_Output; - ba_q_p <= transport ba_q after Clk_to_Output; - sdr_clk_p <= transport sdr_clk after Clk_to_Output; - sdr_clk_n_p <= transport sdr_clk_n after Clk_to_Output; - end if; - end process; - - process(cpu_clk_2x, areset) -- - begin - if areset = '1' then - ddr_state <= idle; - ras_qn <= '1'; - cas_qn <= '1'; - we_qn <= '1'; - smp_req_adr <= (others => '0'); - smp_req_type <= '0'; - smp_req_len <= '0'; - sdr_a <= "XXXXXXXXXXXXX"; - ba_q <= "00"; - ddr_req_ack <= '0'; - ddr_busy <= '1'; - ddr_write_en_int <= '0'; - ddr_read_en_int <= '0'; - elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then - - -- Default values - ras_qn <= '1' after Sim_Delay; - cas_qn <= '1' after Sim_Delay; - we_qn <= '1' after Sim_Delay; - sdr_a <= "XXXXXXXXXXXXX" after Sim_Delay; - ba_q <= "00" after Sim_Delay; - ddr_req_ack <= '0' after Sim_Delay; - ddr_busy <= '1' after Sim_Delay; - ddr_write_en_int <= '0' after Sim_Delay; - ddr_read_en_int <= '0' after Sim_Delay; - - case ddr_state is - when idle => - smp_req_adr <= ddr_req_adr after Sim_Delay; - smp_req_type <= ddr_rd_wr_n after Sim_Delay; - smp_req_len <= ddr_req_len after Sim_Delay; - ddr_busy <= '0' after Sim_Delay; - if refresh_pend = '1' then - ddr_state <= refresh after Sim_Delay; - elsif new_command = '1' then - if ddr_cmd(15) = '1' then - ddr_state <= cpu_pre after Sim_Delay; - else - ddr_state <= cmd after Sim_Delay; - end if; - elsif ddr_req = '1' then - ddr_state <= act after Sim_Delay; - else - ddr_state <= idle after Sim_Delay; - end if; - when act => - sdr_a <= smp_req_adr(23 downto 11) after Sim_Delay; - ras_qn <= '0' after Sim_Delay; - ddr_state <= act_nop1 after Sim_Delay; - ddr_req_ack <= '1' after Sim_Delay; - ddr_write_en_int <= not(smp_req_type) after Sim_Delay; - when act_nop1 => - ddr_state <= act_nop2 after Sim_Delay; - when act_nop2 => - ddr_state <= rd_wr after Sim_Delay; - when rd_wr => - sdr_a(10) <= '0' after Sim_Delay; -- Disable auto precharge - sdr_a(9 downto 0) <= smp_req_adr(10 downto 1) after Sim_Delay; - cas_qn <= '0' after Sim_Delay; - we_qn <= smp_req_type after Sim_Delay; - if smp_req_type = '1' then - ddr_state <= rd_nop1 after Sim_Delay; - else - ddr_state <= wr_nop1 after Sim_Delay; - end if; - when wr_nop1 => - ddr_state <= wr_nop2 after Sim_Delay; - when wr_nop2 => - ddr_state <= wr_nop3 after Sim_Delay; - when wr_nop3 => - ddr_state <= pre after Sim_Delay; - when rd_nop1 => - ddr_state <= rd_nop2 after Sim_Delay; - when rd_nop2 => - ddr_state <= pre after Sim_Delay; - when pre => - ras_qn <= '0' after Sim_Delay; - we_qn <= '0' after Sim_Delay; - sdr_a(10) <= '1' after Sim_Delay; -- Precharge all banks - ddr_state <= pre_nop1 after Sim_Delay; - ddr_read_en_int <= smp_req_type after Sim_Delay; - when pre_nop1 => - ddr_state <= pre_nop2 after Sim_Delay; - when cmd => - cas_qn <= '0' after Sim_Delay; - ras_qn <= '0' after Sim_Delay; - we_qn <= '0' after Sim_Delay; - ba_q <= ddr_cmd(14 downto 13) after Sim_Delay; - sdr_a <= ddr_cmd(12 downto 0) after Sim_Delay; - ddr_state <= idle after Sim_Delay; - when cpu_pre => - ddr_state <= pre after Sim_Delay; - when refresh => - cas_qn <= '0' after Sim_Delay; - ras_qn <= '0' after Sim_Delay; - ddr_state <= refresh_wait after Sim_Delay; - when refresh_wait => - if refresh_wait_end = '1' then - ddr_state <= pre after Sim_Delay; - end if; - when pre_nop2 => - ddr_state <= idle after Sim_Delay; - when others => - ddr_state <= idle after Sim_Delay; - end case; - end if; - end process; - - process(cpu_clk, areset) -- - begin - if areset = '1' then - ddr_cmd <= "0000000000000000"; - elsif (cpu_clk'event and cpu_clk = '1') then - if ddr_command_we = '1' then - ddr_cmd <= ddr_command after Sim_Delay; - else - ddr_cmd <= ddr_cmd after Sim_Delay; - end if; - end if; - end process; - - process(cpu_clk_2x, areset) -- - begin - if areset = '1' then - ddr_cmd_we_smp <= '0'; - new_command <= '0'; - sdr_smp <= "000000000000000000000000000000000000"; - elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then - ddr_cmd_we_smp <= ddr_command_we after Sim_Delay; - if ddr_command_we = '0' and ddr_cmd_we_smp = '1' then - new_command <= '1' after Sim_Delay; - elsif ddr_state = cmd or ddr_state = cpu_pre then - new_command <= '0' after Sim_Delay; - else - new_command <= new_command after Sim_Delay; - end if; - - if ddr_write_en_int = '1' then - sdr_smp <= ddr_data_write after Sim_Delay; - else - sdr_smp <= sdr_smp after Sim_Delay; - end if; - - end if; - end process; - - process(cpu_clk_4x, areset) -- - begin - if areset = '1' then - dqs_q <= "00"; - dqs_oe_n <= "11"; - sdr_oe_ctrl <= '1'; - sdr_wr_msw <= "000000000000000000"; - elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then - - if ddr_state = wr_nop1 and clk4_phase_short(0) = '1' then - sdr_oe_ctrl <= '0' after Sim_Delay; - elsif ddr_state = wr_nop3 and clk4_phase_short(0) = '1' then - sdr_oe_ctrl <= '1' after Sim_Delay; - else - sdr_oe_ctrl <= sdr_oe_ctrl after Sim_Delay; - end if; - - if ddr_state = idle or ddr_state = wr_nop3 then - dqs_oe_n <= "11" after Sim_Delay; - elsif ddr_state = wr_nop1 then - dqs_oe_n <= "00" after Sim_Delay; - else - dqs_oe_n <= dqs_oe_n after Sim_Delay; - end if; - - if (ddr_state = wr_nop2 and clk4_phase_short(0) = '1') then - dqs_q <= "11" after Sim_Delay; - else - dqs_q <= "00" after Sim_Delay; - end if; - - if ddr_state = wr_nop1 and clk4_phase_short(1) = '1' then - sdr_wr_msw <= "111111111111111111" after Sim_Delay; - else - sdr_wr_msw <= "000000000000000000" after Sim_Delay; - end if; - - end if; - end process; - - -- NOTE! DATA OUTPUT PATH. CLOCKED ON FALLING 4X CLOCK - process(cpu_clk_4x, areset) -- - begin - if areset = '1' then - sdr_d_p <= "ZZZZZZZZZZZZZZZZ"; - dm_q_p <= "11"; - sdr_oe_n <= "1111111111111111"; - sdr_d <= "0000000000000000"; - dm_q <= "11"; - elsif (cpu_clk_4x'event and cpu_clk_4x = '0') then - - for i in 0 to 15 loop - if sdr_oe_n(i) = '0' then - sdr_d_p(i) <= transport sdr_d(i) after Clk_to_Output; - else - sdr_d_p(i) <= transport 'Z' after Clk_to_Output; - end if; - end loop; - - dm_q_p <= transport dm_q after Clk_to_Output; - - if sdr_oe_ctrl = '0' then - sdr_oe_n <= "0000000000000000" after Sim_Delay; - else - sdr_oe_n <= "1111111111111111" after Sim_Delay; - end if; - - for i in 0 to 15 loop - if sdr_wr_msw(i) = '0' then - sdr_d(i) <= sdr_smp(i) after Sim_Delay; - else - sdr_d(i) <= sdr_smp(i+16) after Sim_Delay; - end if; - end loop; - - for i in 0 to 1 loop - if sdr_wr_msw(i+16) = '0' then - dm_q(i) <= sdr_smp(i+32) after Sim_Delay; - else - dm_q(i) <= sdr_smp(i+34) after Sim_Delay; - end if; - end loop; - - end if; - end process; - - process(cpu_clk_2x, areset) -- - begin - if areset = '1' then - refresh_cnt <= "0000000000"; - refresh_pend <= '0'; - refresh_end <= '0'; - refresh_wait_cnt <= "000"; - refresh_wait_end <= '0'; - elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then - - if refresh_cnt = Refresh_Interval then - refresh_end <= '1'; - else - refresh_end <= '0'; - end if; - - if refresh_end = '1' then - refresh_cnt <= "0000000000"; - else - refresh_cnt <= refresh_cnt + '1'; - end if; - - if refresh_end = '1' and refresh_en = '1' then - refresh_pend <= '1' after Sim_Delay; - elsif ddr_state = refresh then - refresh_pend <= '0' after Sim_Delay; - else - refresh_pend <= refresh_pend after Sim_Delay; - end if; - - if ddr_state = refresh_wait then - refresh_wait_cnt <= refresh_wait_cnt + '1'; - else - refresh_wait_cnt <= "000"; - end if; - - if refresh_wait_cnt = "111" then - refresh_wait_end <= '1' after Sim_Delay; - else - refresh_wait_end <= '0' after Sim_Delay; - end if; - - end if; - end process; - - -- 911. THIS IS A DUMMY FOR FGPA IMPEMENTATION TESTING - - process(ddr_in_clk, areset) - begin - if areset = '1' then - ddr_clk_tog <= '0'; - elsif (ddr_in_clk'event and ddr_in_clk = '1') then - ddr_clk_tog <= not(ddr_clk_tog) after Sim_Delay; - end if; - end process; - - process(ddr_in_clk_2x, areset) - begin - if areset = '1' then - ddr_clk_smp1 <= '0'; - ddr_clk_smp2 <= '0'; - ddr_clk_phase <= '0'; - elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then - ddr_clk_smp1 <= ddr_clk_tog after Sim_Delay; - ddr_clk_smp2 <= ddr_clk_smp1 after Sim_Delay; - if ddr_clk_smp1 = '1' and ddr_clk_smp2 = '0' then - ddr_clk_phase <= '0'; - else - ddr_clk_phase <= not(ddr_clk_phase); - end if; - end if; - end process; - - process(ddr_in_clk_2x, areset) - begin - if areset = '1' then - cas_n_smp <= '0'; - ras_n_smp <= '0'; - we_n_smp <= '0'; - read_start_sig <= '0'; - elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then - cas_n_smp <= cas_qn_p_del after Sim_Delay; - ras_n_smp <= ras_qn_p_del after Sim_Delay; - we_n_smp <= we_qn_p_del after Sim_Delay; - if ras_n_smp = '1' and cas_n_smp = '0' and we_n_smp = '1' and ddr_clk_phase = '1' then - read_start_sig <= '1' after Sim_Delay; - else - read_start_sig <= '0' after Sim_Delay; - end if; - end if; - end process; - - process(ddr_in_clk_2x, areset) - begin - if areset = '1' then - sdr_d_in <= "0000000000000000"; - elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then - sdr_d_in <= sdr_d_p_del after Sim_Delay; - end if; - end process; - - process(ddr_in_clk_2x, areset) - begin - if areset = '1' then - read_time_cnt <= "00"; - read_input_en <= '0'; - elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then - - if read_start_sig = '1' then - read_time_cnt <= "01" after Sim_Delay; - elsif read_time_cnt = "00" then - read_time_cnt <= read_time_cnt after Sim_Delay; - else - read_time_cnt <= read_time_cnt + '1' after Sim_Delay; - end if; - - if read_time_cnt = "11" then - read_input_en <= '1' after Sim_Delay; - else - read_input_en <= '0' after Sim_Delay; - end if; - - end if; - end process; - - process(ddr_in_clk_2x, areset) - begin - if areset = '1' then - ddr_data_read_int <= "00000000000000000000000000000000"; - elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then - ddr_data_read_int(31 downto 16) <= "0000000000000000" after Sim_Delay; - if read_input_en = '1' then - ddr_data_read_int(15 downto 0) <= sdr_d_in after Sim_Delay; - else - ddr_data_read_int(15 downto 0) <= ddr_data_read_int(15 downto 0) after Sim_Delay; - end if; - end if; - end process; - - - - - - - - - -- ############### - - process(cpu_clk, areset) -- - begin - if areset = '1' then - elsif (cpu_clk'event and cpu_clk = '1') then - end if; - end process; - - - process(cpu_clk_2x, areset) -- - begin - if areset = '1' then - elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then - end if; - end process; - - - process(cpu_clk_4x, areset) -- - begin - if areset = '1' then - elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then - end if; - end process; - - -end behave; - - diff --git a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/mt46v16m16.vhd b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/mt46v16m16.vhd deleted file mode 100644 index 6b89345..0000000 --- a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/mt46v16m16.vhd +++ /dev/null @@ -1,1320 +0,0 @@ ------------------------------------------------------------------------------------------ --- --- File Name: MT46V16M16.VHD --- Version: 2.1 --- Date: January 14th, 2002 --- Model: Behavioral --- Simulator: NCDesktop - http://www.cadence.com --- ModelSim PE - http://www.model.com --- --- Dependencies: None --- --- Author: Son P. Huynh --- Email: sphuynh@micron.com --- Phone: (208) 368-3825 --- Company: Micron Technology, Inc. --- Part Number: MT46V16M16 (4 Mb x 16 x 4 Banks) --- --- Description: Micron 256 Mb SDRAM DDR (Double Data Rate) --- --- Limitation: Doesn't model internal refresh counter --- --- Note: --- --- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY --- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY --- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR --- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. --- --- Copyright (c) 1998 Micron Semiconductor Products, Inc. --- All rights researved --- --- Rev Author Date Changes --- --- ---------------------------- ---------- ------------------------------------- --- 2.1 Son P. Huynh 01/14/2002 - Fix Burst_counter --- Micron Technology, Inc. --- --- 2.0 Son P. Huynh 11/08/2001 - Second release --- Micron Technology, Inc. - Rewrote and remove SHARED VARIABLE --- ------------------------------------------------------------------------------------------ - -LIBRARY IEEE; - USE IEEE.STD_LOGIC_1164.ALL; - USE IEEE.STD_LOGIC_UNSIGNED.ALL; - USE IEEE.STD_LOGIC_ARITH.ALL; - -ENTITY MT46V16M16 IS - GENERIC ( -- Timing for -75Z CL2 - tCK : TIME := 7.500 ns; - tCH : TIME := 3.375 ns; -- 0.45*tCK - tCL : TIME := 3.375 ns; -- 0.45*tCK - tDH : TIME := 0.500 ns; - tDS : TIME := 0.500 ns; - tIH : TIME := 0.900 ns; - tIS : TIME := 0.900 ns; - tMRD : TIME := 15.000 ns; - tRAS : TIME := 40.000 ns; - tRAP : TIME := 20.000 ns; - tRC : TIME := 65.000 ns; - tRFC : TIME := 75.000 ns; - tRCD : TIME := 20.000 ns; - tRP : TIME := 20.000 ns; - tRRD : TIME := 15.000 ns; - tWR : TIME := 15.000 ns; - addr_bits : INTEGER := 13; - data_bits : INTEGER := 16; - cols_bits : INTEGER := 9 - ); - PORT ( - Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); - Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ"; - Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - Clk : IN STD_LOGIC; - Clk_n : IN STD_LOGIC; - Cke : IN STD_LOGIC; - Cs_n : IN STD_LOGIC; - Ras_n : IN STD_LOGIC; - Cas_n : IN STD_LOGIC; - We_n : IN STD_LOGIC; - Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); -END MT46V16M16; - -ARCHITECTURE behave OF MT46V16M16 IS - -- Array for Read pipeline - TYPE Array_Read_cmnd IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Read_bank IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); - TYPE Array_Read_cols IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); - - -- Array for Write pipeline - TYPE Array_Write_cmnd IS ARRAY (2 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Write_bank IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); - TYPE Array_Write_cols IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); - - -- Array for Auto Precharge - TYPE Array_Read_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Write_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Count_precharge IS ARRAY (3 DOWNTO 0) OF INTEGER; - - -- Array for Manual Precharge - TYPE Array_A10_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Bank_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); - TYPE Array_Cmnd_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; - - -- Array for Burst Terminate - TYPE Array_Cmnd_bst IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; - - -- Array for Memory Access - TYPE Array_ram_type IS ARRAY (2**cols_bits - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0); - TYPE Array_ram_pntr IS ACCESS Array_ram_type; - TYPE Array_ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF Array_ram_pntr; - - -- Data pair - SIGNAL Dq_pair : STD_LOGIC_VECTOR (2 * data_bits - 1 DOWNTO 0); - SIGNAL Dm_pair : STD_LOGIC_VECTOR (3 DOWNTO 0); - - -- Mode Register - SIGNAL Mode_reg : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); - - -- Command Decode Variables - SIGNAL Active_enable, Aref_enable, Burst_term, Ext_mode_enable : STD_LOGIC := '0'; - SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : STD_LOGIC := '0'; - - -- Burst Length Decode Variables - SIGNAL Burst_length_2, Burst_length_4, Burst_length_8, Burst_length_f : STD_LOGIC := '0'; - - -- Cas Latency Decode Variables - SIGNAL Cas_latency_15, Cas_latency_2, Cas_latency_25, Cas_latency_3, Cas_latency_4 : STD_LOGIC := '0'; - - -- Internal Control Signals - SIGNAL Cs_in, Ras_in, Cas_in, We_in : STD_LOGIC := '0'; - - -- System Clock - SIGNAL Sys_clk : STD_LOGIC := '0'; - - -- Dqs buffer - SIGNAL Dqs_out : STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ"; - -BEGIN - -- Strip the strength - Cs_in <= To_X01 (Cs_n); - Ras_in <= To_X01 (Ras_n); - Cas_in <= To_X01 (Cas_n); - We_in <= To_X01 (We_n); - - -- Commands Decode - Active_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND We_in; - Aref_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND We_in; - Burst_term <= NOT(Cs_in) AND Ras_in AND Cas_in AND NOT(We_in); - Ext_mode_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND Ba(0) AND NOT(Ba(1)); - Mode_reg_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND NOT(Ba(0)) AND NOT(Ba(1)); - Prech_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND NOT(We_in); - Read_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND We_in; - Write_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND NOT(We_in); - - -- Burst Length Decode - Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0); - Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0)); - Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0); - Burst_length_f <= (Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0); - - -- CAS Latency Decode - Cas_latency_15 <= Mode_reg(6) AND NOT(Mode_reg(5)) AND (Mode_reg(4)); - Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4)); - Cas_latency_25 <= Mode_reg(6) AND Mode_reg(5) AND NOT(Mode_reg(4)); - Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4); - Cas_latency_4 <= (Mode_reg(6)) AND NOT(Mode_reg(5)) AND NOT(Mode_reg(4)); - - -- Dqs buffer - Dqs <= Dqs_out; - - -- - -- System Clock - -- - int_clk : PROCESS (Clk, Clk_n) - VARIABLE ClkZ, CkeZ : STD_LOGIC := '0'; - begin - IF Clk = '1' AND Clk_n = '0' THEN - ClkZ := '1'; - CkeZ := Cke; - ELSIF Clk = '0' AND Clk_n = '1' THEN - ClkZ := '0'; - END IF; - Sys_clk <= CkeZ AND ClkZ; - END PROCESS; - - -- - -- Main Process - -- - state_register : PROCESS - -- Precharge Variables - VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : STD_LOGIC := '0'; - - -- Activate Variables - VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : STD_LOGIC := '1'; - - -- Data IO variables - VARIABLE Data_in_enable, Data_out_enable : STD_LOGIC := '0'; - - -- Internal address mux variables - VARIABLE Cols_brst : STD_LOGIC_VECTOR (2 DOWNTO 0); - VARIABLE Prev_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; - VARIABLE Bank_addr : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; - VARIABLE Cols_addr : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); - VARIABLE Rows_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - VARIABLE B0_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - VARIABLE B1_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - VARIABLE B2_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - VARIABLE B3_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - - -- DLL Reset variables - VARIABLE DLL_enable : STD_LOGIC := '0'; - VARIABLE DLL_reset : STD_LOGIC := '0'; - VARIABLE DLL_done : STD_LOGIC := '0'; - VARIABLE DLL_count : INTEGER := 0; - - -- Timing Check - VARIABLE MRD_chk : TIME := 0 ns; - VARIABLE RFC_chk : TIME := 0 ns; - VARIABLE RRD_chk : TIME := 0 ns; - VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns; - VARIABLE RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3 : TIME := 0 ns; - VARIABLE RC_chk0, RC_chk1, RC_chk2, RC_chk3 : TIME := 0 ns; - VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns; - VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns; - VARIABLE WR_chk0, WR_chk1, WR_chk2, WR_chk3 : TIME := 0 ns; - - -- Read pipeline variables - VARIABLE Read_cmnd : Array_Read_cmnd; - VARIABLE Read_bank : Array_Read_bank; - VARIABLE Read_cols : Array_Read_cols; - - -- Write pipeline variables - VARIABLE Write_cmnd : Array_Write_cmnd; - VARIABLE Write_bank : Array_Write_bank; - VARIABLE Write_cols : Array_Write_cols; - - -- Auto Precharge variables - VARIABLE Read_precharge : Array_Read_precharge := ('0' & '0' & '0' & '0'); - VARIABLE Write_precharge : Array_Write_precharge := ('0' & '0' & '0' & '0'); - VARIABLE Count_precharge : Array_Count_precharge := ( 0 & 0 & 0 & 0 ); - - -- Manual Precharge variables - VARIABLE A10_precharge : Array_A10_precharge; - VARIABLE Bank_precharge : Array_Bank_precharge; - VARIABLE Cmnd_precharge : Array_Cmnd_precharge; - - -- Burst Terminate variable - VARIABLE Cmnd_bst : Array_Cmnd_bst; - - -- Memory Banks - VARIABLE Bank0 : Array_ram_stor; - VARIABLE Bank1 : Array_ram_stor; - VARIABLE Bank2 : Array_ram_stor; - VARIABLE Bank3 : Array_ram_stor; - - -- Burst Counter - VARIABLE Burst_counter : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); - - -- Internal Dqs initialize - VARIABLE Dqs_int : STD_LOGIC := '0'; - - -- Data buffer for DM Mask - VARIABLE Data_buf : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); - - -- - -- Initialize empty rows - -- - PROCEDURE Init_mem (Bank : STD_LOGIC_VECTOR; Row_index : INTEGER) IS - VARIABLE i, j : INTEGER := 0; - BEGIN - IF Bank = "00" THEN - IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty - Bank0 (Row_index) := NEW Array_ram_type; -- Open new row for access - FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros - FOR j IN (data_bits - 1) DOWNTO 0 LOOP - Bank0 (Row_index) (i) (j) := '0'; - END LOOP; - END LOOP; - END IF; - ELSIF Bank = "01" THEN - IF Bank1 (Row_index) = NULL THEN - Bank1 (Row_index) := NEW Array_ram_type; - FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP - FOR j IN (data_bits - 1) DOWNTO 0 LOOP - Bank1 (Row_index) (i) (j) := '0'; - END LOOP; - END LOOP; - END IF; - ELSIF Bank = "10" THEN - IF Bank2 (Row_index) = NULL THEN - Bank2 (Row_index) := NEW Array_ram_type; - FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP - FOR j IN (data_bits - 1) DOWNTO 0 LOOP - Bank2 (Row_index) (i) (j) := '0'; - END LOOP; - END LOOP; - END IF; - ELSIF Bank = "11" THEN - IF Bank3 (Row_index) = NULL THEN - Bank3 (Row_index) := NEW Array_ram_type; - FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP - FOR j IN (data_bits - 1) DOWNTO 0 LOOP - Bank3 (Row_index) (i) (j) := '0'; - END LOOP; - END LOOP; - END IF; - END IF; - END; - - -- - -- Burst Counter - -- - PROCEDURE Burst_decode IS - VARIABLE Cols_temp : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0) := (OTHERS => '0'); - BEGIN - -- Advance burst counter - Burst_counter := Burst_counter + 1; - - -- Burst Type - IF Mode_reg (3) = '0' THEN - Cols_temp := Cols_addr + 1; - ELSIF Mode_reg (3) = '1' THEN - Cols_temp (2) := Burst_counter (2) XOR Cols_brst (2); - Cols_temp (1) := Burst_counter (1) XOR Cols_brst (1); - Cols_temp (0) := Burst_counter (0) XOR Cols_brst (0); - END IF; - - -- Burst Length - IF Burst_length_2 = '1' THEN - Cols_addr (0) := Cols_temp (0); - ELSIF Burst_length_4 = '1' THEN - Cols_addr (1 DOWNTO 0) := Cols_temp (1 DOWNTO 0); - ELSIF Burst_length_8 = '1' THEN - Cols_addr (2 DOWNTO 0) := Cols_temp (2 DOWNTO 0); - ELSE - Cols_addr := Cols_temp; - END IF; - - -- Data counter - IF Burst_length_2 = '1' THEN - IF Burst_counter >= 2 THEN - IF Data_in_enable = '1' THEN - Data_in_enable := '0'; - ELSIF Data_out_enable = '1' THEN - Data_out_enable := '0'; - END IF; - END IF; - ELSIF Burst_length_4 = '1' THEN - IF Burst_counter >= 4 THEN - IF Data_in_enable = '1' THEN - Data_in_enable := '0'; - ELSIF Data_out_enable = '1' THEN - Data_out_enable := '0'; - END IF; - END IF; - ELSIF Burst_length_8 = '1' THEN - IF Burst_counter >= 8 THEN - IF Data_in_enable = '1' THEN - Data_in_enable := '0'; - ELSIF Data_out_enable = '1' THEN - Data_out_enable := '0'; - END IF; - END IF; - END IF; - END; - - BEGIN - WAIT ON Sys_clk; - - -- - -- Manual Precharge Pipeline - -- - IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN - -- A10 Precharge Pipeline - A10_precharge(0) := A10_precharge(1); - A10_precharge(1) := A10_precharge(2); - A10_precharge(2) := A10_precharge(3); - A10_precharge(3) := A10_precharge(4); - A10_precharge(4) := A10_precharge(5); - A10_precharge(5) := A10_precharge(6); - A10_precharge(6) := A10_precharge(7); - A10_precharge(7) := A10_precharge(8); - A10_precharge(8) := '0'; - - -- Bank Precharge Pipeline - Bank_precharge(0) := Bank_precharge(1); - Bank_precharge(1) := Bank_precharge(2); - Bank_precharge(2) := Bank_precharge(3); - Bank_precharge(3) := Bank_precharge(4); - Bank_precharge(4) := Bank_precharge(5); - Bank_precharge(5) := Bank_precharge(6); - Bank_precharge(6) := Bank_precharge(7); - Bank_precharge(7) := Bank_precharge(8); - Bank_precharge(8) := "00"; - - -- Command Precharge Pipeline - Cmnd_precharge(0) := Cmnd_precharge(1); - Cmnd_precharge(1) := Cmnd_precharge(2); - Cmnd_precharge(2) := Cmnd_precharge(3); - Cmnd_precharge(3) := Cmnd_precharge(4); - Cmnd_precharge(4) := Cmnd_precharge(5); - Cmnd_precharge(5) := Cmnd_precharge(6); - Cmnd_precharge(6) := Cmnd_precharge(7); - Cmnd_precharge(7) := Cmnd_precharge(8); - Cmnd_precharge(8) := '0'; - - -- Terminate Read if same bank or all banks - IF ((Cmnd_precharge (0) = '1') AND - (Bank_precharge (0) = Bank_addr OR A10_precharge (0) = '1') AND - (Data_out_enable = '1')) THEN - Data_out_enable := '0'; - END IF; - END IF; - - -- - -- Burst Terminate Pipeline - -- - IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN - -- Burst Terminate pipeline - Cmnd_bst (0) := Cmnd_bst (1); - Cmnd_bst (1) := Cmnd_bst (2); - Cmnd_bst (2) := Cmnd_bst (3); - Cmnd_bst (3) := Cmnd_bst (4); - Cmnd_bst (4) := Cmnd_bst (5); - Cmnd_bst (5) := Cmnd_bst (6); - Cmnd_bst (6) := Cmnd_bst (7); - Cmnd_bst (7) := Cmnd_bst (8); - Cmnd_bst (8) := '0'; - - -- Terminate current Read - IF ((Cmnd_bst (0) = '1') AND (Data_out_enable = '1')) THEN - Data_out_enable := '0'; - END IF; - END IF; - - -- - -- Dq and Dqs Drivers - -- - IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN - -- Read Command Pipeline - Read_cmnd (0) := Read_cmnd (1); - Read_cmnd (1) := Read_cmnd (2); - Read_cmnd (2) := Read_cmnd (3); - Read_cmnd (3) := Read_cmnd (4); - Read_cmnd (4) := Read_cmnd (5); - Read_cmnd (5) := Read_cmnd (6); - Read_cmnd (6) := Read_cmnd (7); - Read_cmnd (7) := Read_cmnd (8); - Read_cmnd (8) := '0'; - - -- Read Bank Pipeline - Read_bank (0) := Read_bank (1); - Read_bank (1) := Read_bank (2); - Read_bank (2) := Read_bank (3); - Read_bank (3) := Read_bank (4); - Read_bank (4) := Read_bank (5); - Read_bank (5) := Read_bank (6); - Read_bank (6) := Read_bank (7); - Read_bank (7) := Read_bank (8); - Read_bank (8) := "00"; - - -- Read Column Pipeline - Read_cols (0) := Read_cols (1); - Read_cols (1) := Read_cols (2); - Read_cols (2) := Read_cols (3); - Read_cols (3) := Read_cols (4); - Read_cols (4) := Read_cols (5); - Read_cols (5) := Read_cols (6); - Read_cols (6) := Read_cols (7); - Read_cols (7) := Read_cols (8); - Read_cols (8) := (OTHERS => '0'); - - -- Initialize Read command - IF Read_cmnd (0) = '1' THEN - Data_out_enable := '1'; - Bank_addr := Read_bank (0); - Cols_addr := Read_cols (0); - Cols_brst := Cols_addr (2 DOWNTO 0); - Burst_counter := (OTHERS => '0'); - - -- Row address mux - CASE Bank_addr IS - WHEN "00" => Rows_addr := B0_row_addr; - WHEN "01" => Rows_addr := B1_row_addr; - WHEN "10" => Rows_addr := B2_row_addr; - WHEN OTHERS => Rows_addr := B3_row_addr; - END CASE; - END IF; - - -- Toggle Dqs during Read command - IF Data_out_enable = '1' THEN - Dqs_int := '0'; - IF Dqs_out = "00" THEN - Dqs_out <= "11"; - ELSIF Dqs_out = "11" THEN - Dqs_out <= "00"; - ELSE - Dqs_out <= "00"; - END IF; - ELSIF Data_out_enable = '0' AND Dqs_int = '0' THEN - Dqs_out <= "ZZ"; - END IF; - - -- Initialize Dqs for Read command - IF Read_cmnd (2) = '1' THEN - IF Data_out_enable = '0' THEN - Dqs_int := '1'; - Dqs_out <= "00"; - END IF; - END IF; - - -- Read Latch - IF Data_out_enable = '1' THEN - -- Initialize Memory - Init_mem (Bank_addr, CONV_INTEGER(Rows_addr)); - - -- Output Data - CASE Bank_addr IS - WHEN "00" => Dq <= Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "01" => Dq <= Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "10" => Dq <= Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN OTHERS => Dq <= Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - END CASE; - - -- Increase Burst Counter - Burst_decode; - ELSE - Dq <= (OTHERS => 'Z'); - END IF; - END IF; - - -- - -- Write FIFO and DM Mask Logic - -- - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - -- Write command pipeline - Write_cmnd (0) := Write_cmnd (1); - Write_cmnd (1) := Write_cmnd (2); - Write_cmnd (2) := '0'; - - -- Write command pipeline - Write_bank (0) := Write_bank (1); - Write_bank (1) := Write_bank (2); - Write_bank (2) := "00"; - - -- Write column pipeline - Write_cols (0) := Write_cols (1); - Write_cols (1) := Write_cols (2); - Write_cols (2) := (OTHERS => '0'); - - -- Initialize Write command - IF Write_cmnd (0) = '1' THEN - Data_in_enable := '1'; - Bank_addr := Write_bank (0); - Cols_addr := Write_cols (0); - Cols_brst := Cols_addr (2 DOWNTO 0); - Burst_counter := (OTHERS => '0'); - - -- Row address mux - CASE Bank_addr IS - WHEN "00" => Rows_addr := B0_row_addr; - WHEN "01" => Rows_addr := B1_row_addr; - WHEN "10" => Rows_addr := B2_row_addr; - WHEN OTHERS => Rows_addr := B3_row_addr; - END CASE; - END IF; - - -- Write data - IF Data_in_enable = '1' THEN - -- Initialize memory - Init_mem (Bank_addr, CONV_INTEGER(Rows_addr)); - - -- Write first data - IF Dm_pair (1) = '0' OR Dm_pair (0) = '0' THEN - -- Data Buffer - CASE Bank_addr IS - WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - END CASE; - - -- Perform DM Mask - IF Dm_pair (0) = '0' THEN - Data_buf ( 7 DOWNTO 0) := Dq_pair ( 7 DOWNTO 0); - END IF; - IF Dm_pair (1) = '0' THEN - Data_buf (15 DOWNTO 8) := Dq_pair (15 DOWNTO 8); - END IF; - - -- Write Data - CASE Bank_addr IS - WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - END CASE; - END IF; - - -- Increase Burst Counter - Burst_decode; - - -- Write second data - IF Dm_pair (3) = '0' OR Dm_pair (2) = '0' THEN - -- Data Buffer - CASE Bank_addr IS - WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - END CASE; - - -- Perform DM Mask - IF Dm_pair (2) = '0' THEN - Data_buf ( 7 DOWNTO 0) := Dq_pair (23 DOWNTO 16); - END IF; - IF Dm_pair (3) = '0' THEN - Data_buf (15 DOWNTO 8) := Dq_pair (31 DOWNTO 24); - END IF; - - -- Write Data - CASE Bank_addr IS - WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - END CASE; - END IF; - - -- Increase Burst Counter - Burst_decode; - - -- tWR start and tWTR check - IF Dm_pair (3 DOWNTO 2) = "00" OR Dm_pair (1 DOWNTO 0) = "00" THEN - CASE Bank_addr IS - WHEN "00" => WR_chk0 := NOW; - WHEN "01" => WR_chk1 := NOW; - WHEN "10" => WR_chk2 := NOW; - WHEN OTHERS => WR_chk3 := NOW; - END CASE; - - -- tWTR check - ASSERT (Read_enable = '0') - REPORT "tWTR violation during Read" - SEVERITY WARNING; - END IF; - END IF; - END IF; - - -- - -- Auto Precharge Calculation - -- - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - -- Precharge counter - IF Read_precharge (0) = '1' OR Write_precharge (0) = '1' THEN - Count_precharge (0) := Count_precharge (0) + 1; - END IF; - IF Read_precharge (1) = '1' OR Write_precharge (1) = '1' THEN - Count_precharge (1) := Count_precharge (1) + 1; - END IF; - IF Read_precharge (2) = '1' OR Write_precharge (2) = '1' THEN - Count_precharge (2) := Count_precharge (2) + 1; - END IF; - IF Read_precharge (3) = '1' OR Write_precharge (3) = '1' THEN - Count_precharge (3) := Count_precharge (3) + 1; - END IF; - - -- Read with AutoPrecharge Calculation - -- The device start internal precharge when: - -- 1. Meet tRAS requirement - -- 2. BL/2 cycles after command - IF ((Read_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge(0) >= 1) OR - (Burst_length_4 = '1' AND Count_precharge(0) >= 2) OR - (Burst_length_8 = '1' AND Count_precharge(0) >= 4)) THEN - Pc_b0 := '1'; - Act_b0 := '0'; - RP_chk0 := NOW; - Read_precharge(0) := '0'; - END IF; - END IF; - IF ((Read_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge(1) >= 1) OR - (Burst_length_4 = '1' AND Count_precharge(1) >= 2) OR - (Burst_length_8 = '1' AND Count_precharge(1) >= 4)) THEN - Pc_b1 := '1'; - Act_b1 := '0'; - RP_chk1 := NOW; - Read_precharge(1) := '0'; - END IF; - END IF; - IF ((Read_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge(2) >= 1) OR - (Burst_length_4 = '1' AND Count_precharge(2) >= 2) OR - (Burst_length_8 = '1' AND Count_precharge(2) >= 4)) THEN - Pc_b2 := '1'; - Act_b2 := '0'; - RP_chk2 := NOW; - Read_precharge(2) := '0'; - END IF; - END IF; - IF ((Read_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge(3) >= 1) OR - (Burst_length_4 = '1' AND Count_precharge(3) >= 2) OR - (Burst_length_8 = '1' AND Count_precharge(3) >= 4)) THEN - Pc_b3 := '1'; - Act_b3 := '0'; - RP_chk3 := NOW; - Read_precharge(3) := '0'; - END IF; - END IF; - - -- Write with AutoPrecharge Calculation - -- The device start internal precharge when: - -- 1. Meet tRAS requirement - -- 2. Two clock after last burst - -- Since tWR is time base, the model will compensate tRP - IF ((Write_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge (0) >= 4) OR - (Burst_length_4 = '1' AND Count_precharge (0) >= 5) OR - (Burst_length_8 = '1' AND Count_precharge (0) >= 7)) THEN - Pc_b0 := '1'; - Act_b0 := '0'; - RP_chk0 := NOW - ((2 * tCK) - tWR); - Write_precharge(0) := '0'; - END IF; - END IF; - IF ((Write_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge (1) >= 4) OR - (Burst_length_4 = '1' AND Count_precharge (1) >= 5) OR - (Burst_length_8 = '1' AND Count_precharge (1) >= 7)) THEN - Pc_b1 := '1'; - Act_b1 := '0'; - RP_chk1 := NOW - ((2 * tCK) - tWR); - Write_precharge(1) := '0'; - END IF; - END IF; - IF ((Write_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge (2) >= 4) OR - (Burst_length_4 = '1' AND Count_precharge (2) >= 5) OR - (Burst_length_8 = '1' AND Count_precharge (2) >= 7)) THEN - Pc_b2 := '1'; - Act_b2 := '0'; - RP_chk2 := NOW - ((2 * tCK) - tWR); - Write_precharge(2) := '0'; - END IF; - END IF; - IF ((Write_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge (3) >= 4) OR - (Burst_length_4 = '1' AND Count_precharge (3) >= 5) OR - (Burst_length_8 = '1' AND Count_precharge (3) >= 7)) THEN - Pc_b3 := '1'; - Act_b3 := '0'; - RP_chk3 := NOW - ((2 * tCK) - tWR); - Write_precharge(3) := '0'; - END IF; - END IF; - END IF; - - -- - -- DLL Counter - -- - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - IF (DLL_Reset = '1' AND DLL_done = '0') THEN - DLL_count := DLL_count + 1; - IF (DLL_count >= 200) THEN - DLL_done := '1'; - END IF; - END IF; - END IF; - - -- - -- Control Logic - -- - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - -- Auto Refresh - IF Aref_enable = '1' THEN - -- Auto Refresh to Auto Refresh - ASSERT (NOW - RFC_chk >= tRFC) - REPORT "tRFC violation during Auto Refresh" - SEVERITY WARNING; - - -- Precharge to Auto Refresh - ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND - (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) - REPORT "tRP violation during Auto Refresh" - SEVERITY WARNING; - - -- Precharge to Auto Refresh - ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') - REPORT "All banks must be Precharge before Auto Refresh" - SEVERITY WARNING; - - -- Record current tRFC time - RFC_chk := NOW; - END IF; - - -- Extended Load Mode Register - IF Ext_mode_enable = '1' THEN - IF (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') THEN - IF (Addr (0) = '0') THEN - DLL_enable := '1'; - ELSE - DLL_enable := '0'; - END IF; - END IF; - - -- Precharge to EMR - ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') - REPORT "All bank must be Precharged before Extended Mode Register" - SEVERITY WARNING; - - -- Precharge to EMR - ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND - (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) - REPORT "tRP violation during Extended Load Register" - SEVERITY WARNING; - - -- LMR/EMR to EMR - ASSERT (NOW - MRD_chk >= tMRD) - REPORT "tMRD violation during Extended Mode Register" - SEVERITY WARNING; - - -- Record current tMRD time - MRD_chk := NOW; - END IF; - - -- Load Mode Register - IF Mode_reg_enable = '1' THEN - -- Register mode - Mode_reg <= Addr; - - -- DLL Reset - IF (DLL_enable = '1' AND Addr (8) = '1') THEN - DLL_reset := '1'; - DLL_done := '0'; - DLL_count := 0; - ELSIF (DLL_enable = '1' AND DLL_reset = '0' AND Addr (8) = '0') THEN - ASSERT (FALSE) - REPORT "DLL is ENABLE: DLL RESET is require" - SEVERITY WARNING; - ELSIF (DLL_enable = '0' AND Addr (8) = '1') THEN - ASSERT (FALSE) - REPORT "DLL is DISABLE: DLL RESET will be ignored" - SEVERITY WARNING; - END IF; - - -- Precharge to LMR - ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') - REPORT "All bank must be Precharged before Load Mode Register" - SEVERITY WARNING; - - -- Precharge to EMR - ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND - (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) - REPORT "tRP violation during Load Mode Register" - SEVERITY WARNING; - - -- LMR/ELMR to LMR - ASSERT (NOW - MRD_chk >= tMRD) - REPORT "tMRD violation during Load Mode Register" - SEVERITY WARNING; - - -- Check for invalid Burst Length - ASSERT ((Addr (2 DOWNTO 0) = "001") OR -- BL = 2 - (Addr (2 DOWNTO 0) = "010") OR -- BL = 4 - (Addr (2 DOWNTO 0) = "011")) -- BL = 8 - REPORT "Invalid Burst Length during Load Mode Register" - SEVERITY WARNING; - - -- Check for invalid CAS Latency - ASSERT ((Addr (6 DOWNTO 4) = "010") OR -- CL = 2.0 - (Addr (6 DOWNTO 4) = "110")) -- CL = 2.5 - REPORT "Invalid CAS Latency during Load Mode Register" - SEVERITY WARNING; - - -- Record current tMRD time - MRD_chk := NOW; - END IF; - - -- Active Block (latch Bank and Row Address) - IF Active_enable = '1' THEN - -- Activate an OPEN bank can corrupt data - ASSERT ((Ba = "00" AND Act_b0 = '0') OR - (Ba = "01" AND Act_b1 = '0') OR - (Ba = "10" AND Act_b2 = '0') OR - (Ba = "11" AND Act_b3 = '0')) - REPORT "Bank is already activated - data can be corrupted" - SEVERITY WARNING; - - -- Activate Bank 0 - IF Ba = "00" AND Pc_b0 = '1' THEN - -- Activate to Activate (same bank) - ASSERT (NOW - RC_chk0 >= tRC) - REPORT "tRC violation during Activate Bank 0" - SEVERITY WARNING; - - -- Precharge to Active - ASSERT (NOW - RP_chk0 >= tRP) - REPORT "tRP violation during Activate Bank 0" - SEVERITY WARNING; - - -- Record Variables for checking violation - Act_b0 := '1'; - Pc_b0 := '0'; - B0_row_addr := Addr; - RC_chk0 := NOW; - RCD_chk0 := NOW; - RAS_chk0 := NOW; - RAP_chk0 := NOW; - END IF; - - -- Activate Bank 1 - IF Ba = "01" AND Pc_b1 = '1' THEN - -- Activate to Activate (same bank) - ASSERT (NOW - RC_chk1 >= tRC) - REPORT "tRC violation during Activate Bank 1" - SEVERITY WARNING; - - -- Precharge to Active - ASSERT (NOW - RP_chk1 >= tRP) - REPORT "tRP violation during Activate Bank 1" - SEVERITY WARNING; - - -- Record Variables for checking violation - Act_b1 := '1'; - Pc_b1 := '0'; - B1_row_addr := Addr; - RC_chk1 := NOW; - RCD_chk1 := NOW; - RAS_chk1 := NOW; - RAP_chk1 := NOW; - END IF; - - -- Activate Bank 2 - IF Ba = "10" AND Pc_b2 = '1' THEN - -- Activate to Activate (same bank) - ASSERT (NOW - RC_chk2 >= tRC) - REPORT "tRC violation during Activate Bank 2" - SEVERITY WARNING; - - -- Precharge to Active - ASSERT (NOW - RP_chk2 >= tRP) - REPORT "tRP violation during Activate Bank 2" - SEVERITY WARNING; - - -- Record Variables for checking violation - Act_b2 := '1'; - Pc_b2 := '0'; - B2_row_addr := Addr; - RC_chk2 := NOW; - RCD_chk2 := NOW; - RAS_chk2 := NOW; - RAP_chk2 := NOW; - END IF; - - -- Activate Bank 3 - IF Ba = "11" AND Pc_b3 = '1' THEN - -- Activate to Activate (same bank) - ASSERT (NOW - RC_chk3 >= tRC) - REPORT "tRC violation during Activate Bank 3" - SEVERITY WARNING; - - -- Precharge to Active - ASSERT (NOW - RP_chk3 >= tRP) - REPORT "tRP violation during Activate Bank 3" - SEVERITY WARNING; - - -- Record Variables for checking violation - Act_b3 := '1'; - Pc_b3 := '0'; - B3_row_addr := Addr; - RC_chk3 := NOW; - RCD_chk3 := NOW; - RAS_chk3 := NOW; - RAP_chk3 := NOW; - END IF; - - -- Activate Bank A to Activate Bank B - IF (Prev_bank /= Ba) THEN - ASSERT (NOW - RRD_chk >= tRRD) - REPORT "tRRD violation during Activate" - SEVERITY WARNING; - END IF; - - -- AutoRefresh to Activate - ASSERT (NOW - RFC_chk >= tRFC) - REPORT "tRFC violation during Activate" - SEVERITY WARNING; - - -- Record Variables for Checking Violation - RRD_chk := NOW; - Prev_bank := Ba; - END IF; - - -- Precharge Block - Consider NOP if bank already precharged or in process of precharging - IF Prech_enable = '1' THEN - -- EMR or LMR to Precharge - ASSERT (NOW - MRD_chk >= tMRD) - REPORT "tMRD violation during Precharge" - SEVERITY WARNING; - - -- Precharge Bank 0 - IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "00")) AND Act_b0 = '1') THEN - Act_b0 := '0'; - Pc_b0 := '1'; - RP_chk0 := NOW; - - -- Activate to Precharge bank 0 - ASSERT (NOW - RAS_chk0 >= tRAS) - REPORT "tRAS violation during Precharge" - SEVERITY WARNING; - - -- tWR violation check for Write - ASSERT (NOW - WR_chk0 >= tWR) - REPORT "tWR violation during Precharge" - SEVERITY WARNING; - END IF; - - -- Precharge Bank 1 - IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "01")) AND Act_b1 = '1') THEN - Act_b1 := '0'; - Pc_b1 := '1'; - RP_chk1 := NOW; - - -- Activate to Precharge - ASSERT (NOW - RAS_chk1 >= tRAS) - REPORT "tRAS violation during Precharge" - SEVERITY WARNING; - - -- tWR violation check for Write - ASSERT (NOW - WR_chk1 >= tWR) - REPORT "tWR violation during Precharge" - SEVERITY WARNING; - END IF; - - -- Precharge Bank 2 - IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "10")) AND Act_b2 = '1') THEN - Act_b2 := '0'; - Pc_b2 := '1'; - RP_chk2 := NOW; - - -- Activate to Precharge - ASSERT (NOW - RAS_chk2 >= tRAS) - REPORT "tRAS violation during Precharge" - SEVERITY WARNING; - - -- tWR violation check for Write - ASSERT (NOW - WR_chk2 >= tWR) - REPORT "tWR violation during Precharge" - SEVERITY WARNING; - END IF; - - -- Precharge Bank 3 - IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "11")) AND Act_b3 = '1') THEN - Act_b3 := '0'; - Pc_b3 := '1'; - RP_chk3 := NOW; - - -- Activate to Precharge - ASSERT (NOW - RAS_chk3 >= tRAS) - REPORT "tRAS violation during Precharge" - SEVERITY WARNING; - - -- tWR violation check for Write - ASSERT (NOW - WR_chk3 >= tWR) - REPORT "tWR violation during Precharge" - SEVERITY WARNING; - END IF; - - -- Pipeline for READ - IF CAS_latency_15 = '1' THEN - A10_precharge (3) := Addr(10); - Bank_precharge (3) := Ba; - Cmnd_precharge (3) := '1'; - ELSIF CAS_latency_2 = '1' THEN - A10_precharge (4) := Addr(10); - Bank_precharge (4) := Ba; - Cmnd_precharge (4) := '1'; - ELSIF CAS_latency_25 = '1' THEN - A10_precharge (5) := Addr(10); - Bank_precharge (5) := Ba; - Cmnd_precharge (5) := '1'; - ELSIF CAS_latency_3 = '1' THEN - A10_precharge (6) := Addr(10); - Bank_precharge (6) := Ba; - Cmnd_precharge (6) := '1'; - ELSIF CAS_latency_4 = '1' THEN - A10_precharge (8) := Addr(10); - Bank_precharge (8) := Ba; - Cmnd_precharge (8) := '1'; - END IF; - END IF; - - -- Burst Terminate - IF Burst_term = '1' THEN - -- Pipeline for Read - IF CAS_latency_15 = '1' THEN - Cmnd_bst (3) := '1'; - ELSIF CAS_latency_2 = '1' THEN - Cmnd_bst (4) := '1'; - ELSIF CAS_latency_25 = '1' THEN - Cmnd_bst (5) := '1'; - ELSIF CAS_latency_3 = '1' THEN - Cmnd_bst (6) := '1'; - ELSIF CAS_latency_4 = '1' THEN - Cmnd_bst (8) := '1'; - END IF; - - -- Terminate Write - ASSERT (Data_in_enable = '0') - REPORT "It's illegal to Burst Terminate a Write" - SEVERITY WARNING; - - -- Terminate Read with Auto Precharge - ASSERT (Read_precharge (0) = '0' AND Read_precharge (1) = '0' AND - Read_precharge (2) = '0' AND Read_precharge (3) = '0') - REPORT "It's illegal to Burst Terminate a Read with Auto Precharge" - SEVERITY WARNING; - END IF; - - -- Read Command - IF Read_enable = '1' THEN - -- CAS Latency Pipeline - IF Cas_latency_15 = '1' THEN - Read_cmnd (3) := '1'; - Read_bank (3) := Ba; - Read_cols (3) := Addr (8 DOWNTO 0); - ELSIF Cas_latency_2 = '1' THEN - Read_cmnd (4) := '1'; - Read_bank (4) := Ba; - Read_cols (4) := Addr (8 DOWNTO 0); - ELSIF Cas_latency_25 = '1' THEN - Read_cmnd (5) := '1'; - Read_bank (5) := Ba; - Read_cols (5) := Addr (8 DOWNTO 0); - ELSIF Cas_latency_3 = '1' THEN - Read_cmnd (6) := '1'; - Read_bank (6) := Ba; - Read_cols (6) := Addr (8 DOWNTO 0); - ELSIF Cas_latency_4 = '1' THEN - Read_cmnd (8) := '1'; - Read_bank (8) := Ba; - Read_cols (8) := Addr (8 DOWNTO 0); - END IF; - - -- Write to Read: Terminate Write Immediately - IF Data_in_enable = '1' THEN - Data_in_enable := '0'; - END IF; - - -- Interrupting a Read with Auto Precharge (same bank only) - ASSERT (Read_precharge(CONV_INTEGER(Ba)) = '0') - REPORT "It's illegal to interrupt a Read with Auto Precharge" - SEVERITY WARNING; - - -- Activate to Read - ASSERT ((Ba = "00" AND Act_b0 = '1') OR - (Ba = "01" AND Act_b1 = '1') OR - (Ba = "10" AND Act_b2 = '1') OR - (Ba = "11" AND Act_b3 = '1')) - REPORT "Bank is not Activated for Read" - SEVERITY WARNING; - - -- Activate to Read without Auto Precharge - IF Addr (10) = '0' THEN - ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR - (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR - (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR - (Ba = "11" AND NOW - RCD_chk3 >= tRCD)) - REPORT "tRCD violation during Read" - SEVERITY WARNING; - END IF; - - -- Activate to Read with Auto Precharge - IF Addr (10) = '1' THEN - ASSERT ((Ba = "00" AND NOW - RAP_chk0 >= tRAP) OR - (Ba = "01" AND NOW - RAP_chk1 >= tRAP) OR - (Ba = "10" AND NOW - RAP_chk2 >= tRAP) OR - (Ba = "11" AND NOW - RAP_chk3 >= tRAP)) - REPORT "tRAP violation during Read" - SEVERITY WARNING; - END IF; - - -- Auto precharge - IF Addr (10) = '1' THEN - Read_precharge (Conv_INTEGER(Ba)) := '1'; - Count_precharge (Conv_INTEGER(Ba)) := 0; - END IF; - - -- DLL Check - IF (DLL_reset = '1') THEN - ASSERT (DLL_done = '1') - REPORT "DLL RESET not complete" - SEVERITY WARNING; - END IF; - END IF; - - -- Write Command - IF Write_enable = '1' THEN - -- Pipeline for Write - Write_cmnd (2) := '1'; - Write_bank (2) := Ba; - Write_cols (2) := Addr (8 DOWNTO 0); - - -- Interrupting a Write with Auto Precharge (same bank only) - ASSERT (Write_precharge(CONV_INTEGER(Ba)) = '0') - REPORT "It's illegal to interrupt a Write with Auto Precharge" - SEVERITY WARNING; - - -- Activate to Write - ASSERT ((Ba = "00" AND Act_b0 = '1') OR - (Ba = "01" AND Act_b1 = '1') OR - (Ba = "10" AND Act_b2 = '1') OR - (Ba = "11" AND Act_b3 = '1')) - REPORT "Bank is not Activated for Write" - SEVERITY WARNING; - - -- Activate to Write - ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR - (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR - (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR - (Ba = "11" AND NOW - RCD_chk3 >= tRCD)) - REPORT "tRCD violation during Write" - SEVERITY WARNING; - - -- Auto precharge - IF Addr (10) = '1' THEN - Write_precharge (Conv_INTEGER(Ba)) := '1'; - Count_precharge (Conv_INTEGER(Ba)) := 0; - END IF; - END IF; - END IF; - END PROCESS; - - -- - -- Dqs Receiver - -- - dqs_rcvrs : PROCESS - VARIABLE Dm_temp : STD_LOGIC_VECTOR (1 DOWNTO 0); - VARIABLE Dq_temp : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0); - BEGIN - WAIT ON Dqs; - -- Latch data at posedge Dqs - IF Dqs'EVENT AND Dqs (1) = '1' AND Dqs (0) = '1' THEN - Dq_temp := Dq; - Dm_temp := Dm; - END IF; - -- Latch data at negedge Dqs - IF Dqs'EVENT AND Dqs (1) = '0' AND Dqs (0) = '0' THEN - Dq_pair <= (Dq & Dq_temp); - Dm_pair <= (Dm & Dm_temp); - END IF; - END PROCESS; - - -- - -- Setup timing checks - -- - Setup_check : PROCESS - BEGIN - WAIT ON Sys_clk; - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - ASSERT(Cke'LAST_EVENT >= tIS) - REPORT "CKE Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Cs_n'LAST_EVENT >= tIS) - REPORT "CS# Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Cas_n'LAST_EVENT >= tIS) - REPORT "CAS# Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Ras_n'LAST_EVENT >= tIS) - REPORT "RAS# Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(We_n'LAST_EVENT >= tIS) - REPORT "WE# Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Addr'LAST_EVENT >= tIS) - REPORT "ADDR Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Ba'LAST_EVENT >= tIS) - REPORT "BA Setup time violation -- tIS" - SEVERITY WARNING; - END IF; - END PROCESS; - - -- - -- Hold timing checks - -- - Hold_check : PROCESS - BEGIN - WAIT ON Sys_clk'DELAYED (tIH); - IF Sys_clk'DELAYED (tIH) = '1' THEN - ASSERT(Cke'LAST_EVENT >= tIH) - REPORT "CKE Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Cs_n'LAST_EVENT >= tIH) - REPORT "CS# Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Cas_n'LAST_EVENT >= tIH) - REPORT "CAS# Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Ras_n'LAST_EVENT >= tIH) - REPORT "RAS# Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(We_n'LAST_EVENT >= tIH) - REPORT "WE# Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Addr'LAST_EVENT >= tIH) - REPORT "ADDR Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Ba'LAST_EVENT >= tIH) - REPORT "BA Hold time violation -- tIH" - SEVERITY WARNING; - END IF; - END PROCESS; - -END behave; diff --git a/zpu/hdl/zpu4/src/build.xml b/zpu/hdl/zpu4/src/build.xml deleted file mode 100644 index e1b268a..0000000 --- a/zpu/hdl/zpu4/src/build.xml +++ /dev/null @@ -1,114 +0,0 @@ - - - - - - - eCosBoard firmware build file - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/zpu/hdl/zpu4/src/ic300.bitgen b/zpu/hdl/zpu4/src/ic300.bitgen deleted file mode 100644 index 1095099..0000000 --- a/zpu/hdl/zpu4/src/ic300.bitgen +++ /dev/null @@ -1,27 +0,0 @@ --g DebugBitstream:No --g Binary:yes --g CRC:Enable --g ConfigRate:50 --g CclkPin:Pullnone --g M0Pin:Pullnone --g M1Pin:Pullnone --g M2Pin:Pullnone --g ProgPin:PullUp --g DonePin:Pullnone --g TckPin:Pullnone --g TdiPin:Pullnone --g TdoPin:Pullnone --g TmsPin:Pullnone --g UnusedPin:Pullnone --g UserID:0xFFFFFFFF --g DCMShutDown:Disable --g DCIUpdateMode:AsRequired --g StartUpClk:CClk --g DONE_cycle:4 --g GTS_cycle:5 --g GWE_cycle:6 --g LCK_cycle:NoWait --g Security:Level1 --g DonePipe:No --g DriveDone:Yes - diff --git a/zpu/hdl/zpu4/src/ic300.lso b/zpu/hdl/zpu4/src/ic300.lso deleted file mode 100644 index 22de730..0000000 --- a/zpu/hdl/zpu4/src/ic300.lso +++ /dev/null @@ -1 +0,0 @@ -work diff --git a/zpu/hdl/zpu4/src/ic300.ucf b/zpu/hdl/zpu4/src/ic300.ucf deleted file mode 100644 index 4a141b9..0000000 --- a/zpu/hdl/zpu4/src/ic300.ucf +++ /dev/null @@ -1,146 +0,0 @@ -# clock inputs -net "cpu_clk_p" loc = "R9" | iostandard=LVTTL; - -# input pins -net "cpu_a_p(0)" loc = "N15" | iostandard=LVTTL; -net "cpu_a_p(1)" loc = "P16" | iostandard=LVTTL; -net "cpu_a_p(2)" loc = "P13" | iostandard=LVTTL; -net "cpu_a_p(3)" loc = "N16" | iostandard=LVTTL; -net "cpu_a_p(4)" loc = "P15" | iostandard=LVTTL; -net "cpu_a_p(5)" loc = "R11" | iostandard=LVTTL; -net "cpu_a_p(6)" loc = "T14" | iostandard=LVTTL; -net "cpu_a_p(7)" loc = "R16" | iostandard=LVTTL; -net "cpu_a_p(8)" loc = "P14" | iostandard=LVTTL; -net "cpu_a_p(9)" loc = "T13" | iostandard=LVTTL; -net "cpu_a_p(10)" loc = "R13" | iostandard=LVTTL; -net "cpu_a_p(11)" loc = "P7" | iostandard=LVTTL; -net "cpu_a_p(12)" loc = "N12" | iostandard=LVTTL; -net "cpu_a_p(13)" loc = "R12" | iostandard=LVTTL; -net "cpu_a_p(14)" loc = "L13" | iostandard=LVTTL; -net "cpu_a_p(15)" loc = "K12" | iostandard=LVTTL; -net "cpu_a_p(16)" loc = "K15" | iostandard=LVTTL; -net "cpu_a_p(17)" loc = "T10" | iostandard=LVTTL; -net "cpu_a_p(18)" loc = "T9" | iostandard=LVTTL; -net "cpu_a_p(19)" loc = "N10" | iostandard=LVTTL; -net "cpu_a_p(20)" loc = "T8" | iostandard=LVTTL; -net "cpu_wr_n_p(0)" loc = "L15" | iostandard=LVTTL; -net "cpu_wr_n_p(1)" loc = "N14" | iostandard=LVTTL; -net "cpu_oe_n_p" loc = "T12" | iostandard=LVTTL; -net "cpu_cs_n_p(1)" loc = "R3" | iostandard=LVTTL; -net "cpu_cs_n_p(2)" loc = "M16" | iostandard=LVTTL; -net "cpu_cs_n_p(3)" loc = "P11" | iostandard=LVTTL; - -#net "sdr_clk_fb_p" loc = "B8" | iostandard=SSTL2_I; - -# output pins -net "cpu_fiq_p" loc = "K16" | iostandard=LVTTL; -net "cpu_irq_p(0)" loc = "M14" | iostandard=LVTTL; -net "cpu_irq_p(1)" loc = "J16" | iostandard=LVTTL; -net "cpu_wait_n_p" loc = "M15" | iostandard=LVTTL; - -#net "sdr_clk_p" loc = "D8" | iostandard=SSTL2_I | FAST; -#net "sdr_clk_n_p" loc = "F5" | iostandard=SSTL2_I | FAST; -#net "cke_q_p" loc = "F4" | iostandard=SSTL2_I | FAST; -#net "cs_qn_p" loc = "M2" | iostandard=SSTL2_I | FAST | PULLUP; -#net "ras_qn_p" loc = "J2" | iostandard=SSTL2_I | FAST | PULLUP | NODELAY; -#net "cas_qn_p" loc = "M3" | iostandard=SSTL2_I | FAST | PULLUP | NODELAY; -#net "we_qn_p" loc = "K4" | iostandard=SSTL2_I | FAST | PULLUP | NODELAY; -#net "dm_q_p(0)" loc = "L4" | iostandard=SSTL2_I | FAST; -#net "dm_q_p(1)" loc = "E4" | iostandard=SSTL2_I | FAST; -#net "dqs_q_p(0)" loc = "L3" | iostandard=SSTL2_I | FAST; -#net "dqs_q_p(1)" loc = "D3" | iostandard=SSTL2_I | FAST; -#net "ba_q_p(0)" loc = "M1" | iostandard=SSTL2_I | FAST; -#net "ba_q_p(1)" loc = "J3" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(0)" loc = "J4" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(1)" loc = "N2" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(2)" loc = "H4" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(3)" loc = "P2" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(4)" loc = "E7" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(5)" loc = "G4" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(6)" loc = "D7" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(7)" loc = "G5" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(8)" loc = "C7" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(9)" loc = "F3" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(10)" loc = "N3" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(11)" loc = "E6" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(12)" loc = "D6" | iostandard=SSTL2_I | FAST; - -# bidirectional pins -net "cpu_d_p(0)" loc = "M11" | iostandard=LVTTL; -net "cpu_d_p(1)" loc = "N11" | iostandard=LVTTL; -net "cpu_d_p(2)" loc = "P10" | iostandard=LVTTL; -net "cpu_d_p(3)" loc = "R10" | iostandard=LVTTL; -net "cpu_d_p(4)" loc = "T7" | iostandard=LVTTL; -net "cpu_d_p(5)" loc = "R7" | iostandard=LVTTL; -net "cpu_d_p(6)" loc = "N6" | iostandard=LVTTL; -net "cpu_d_p(7)" loc = "M6" | iostandard=LVTTL; -net "cpu_d_p(8)" loc = "K13" | iostandard=LVTTL; -net "cpu_d_p(9)" loc = "M10" | iostandard=LVTTL; -net "cpu_d_p(10)" loc = "L12" | iostandard=LVTTL; -net "cpu_d_p(11)" loc = "M13" | iostandard=LVTTL; -net "cpu_d_p(12)" loc = "K14" | iostandard=LVTTL; -net "cpu_d_p(13)" loc = "L14" | iostandard=LVTTL; -net "cpu_d_p(14)" loc = "J13" | iostandard=LVTTL; -net "cpu_d_p(15)" loc = "J14" | iostandard=LVTTL; - -#net "sdr_d_p(0)" loc = "G1" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(1)" loc = "H3" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(2)" loc = "G3" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(3)" loc = "K2" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(4)" loc = "F2" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(5)" loc = "L2" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(6)" loc = "E1" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(7)" loc = "M4" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(8)" loc = "C6" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(9)" loc = "E2" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(10)" loc = "C2" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(11)" loc = "D1" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(12)" loc = "B7" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(13)" loc = "D2" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(14)" loc = "B6" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(15)" loc = "B5" | iostandard=SSTL2_I | NODELAY | FAST; - -# TIMING -# Create timing names -NET "cpu_clk_p" TNM_NET = "cpu_clk_p"; -NET "sdr_clk_fb_p" TNM_NET = "sdr_clk_fb_p"; -#NET "cpu_clk" TNM_NET = "cpu_clk"; -#NET "cpu_clk_2x" TNM_NET = "cpu_clk_2x"; -#NET "cpu_clk_4x" TNM_NET = "cpu_clk_4x"; -#NET "ddr_in_clk" TNM_NET = "ddr_in_clk"; -#NET "ddr_in_clk_2x" TNM_NET = "ddr_in_clk_2x"; - -## Create timing - -# Periode timing -TIMESPEC "TS_cpu_clk" = PERIOD "cpu_clk_p" 10 ns HIGH 50 %; -#TIMESPEC "TS_sdr_clk_fb_p" = PERIOD "sdr_clk_fb_p" 7.8 ns HIGH 50 %; - -# Clock domain crossing timing -#TIMESPEC "TS_cpu1_to_cpu2" = FROM "cpu_clk" TO "cpu_clk_2x" 7.8 ns; -#TIMESPEC "TS_cpu1_to_cpu4" = FROM "cpu_clk" TO "cpu_clk_4x" 3.9 ns; -#TIMESPEC "TS_cpu1_to_ddr2" = FROM "cpu_clk" TO "ddr_in_clk" 7.8 ns; -#TIMESPEC "TS_cpu1_to_ddr2_2x" = FROM "cpu_clk" TO "ddr_in_clk_2x" 3.9 ns; - -#TIMESPEC "TS_cpu2_to_cpu1" = FROM "cpu_clk_2x" TO "cpu_clk" 7.8 ns; -#TIMESPEC "TS_cpu2_to_cpu4" = FROM "cpu_clk_2x" TO "cpu_clk_4x" 3.9 ns; -#TIMESPEC "TS_cpu2_to_ddr2" = FROM "cpu_clk_2x" TO "ddr_in_clk" 7.8 ns; -#TIMESPEC "TS_cpu2_to_ddr_2x" = FROM "cpu_clk_2x" TO "ddr_in_clk_2x" 3.9 ns; - -#TIMESPEC "TS_cpu4_to_cpu1" = FROM "cpu_clk_4x" TO "cpu_clk" 3.9 ns; -#TIMESPEC "TS_cpu4_to_cpu2" = FROM "cpu_clk_4x" TO "cpu_clk_2x" 3.9 ns; -#TIMESPEC "TS_cpu4_to_ddr2" = FROM "cpu_clk_4x" TO "ddr_in_clk" 3.9 ns; -#TIMESPEC "TS_cpu4_to_ddr2_2x" = FROM "cpu_clk_4x" TO "ddr_in_clk_2x" 3.9 ns; - -#TIMESPEC "TS_ddr2_to_cpu1" = FROM "ddr_in_clk" TO "cpu_clk" 7.8 ns; -#TIMESPEC "TS_ddr2_to_cpu2" = FROM "ddr_in_clk" TO "cpu_clk_2x" 7.8 ns; -#TIMESPEC "TS_ddr2_to_cpu4" = FROM "ddr_in_clk" TO "cpu_clk_4x" 3.9 ns; -#TIMESPEC "TS_ddr2_to_ddr2_2x" = FROM "ddr_in_clk" TO "ddr_in_clk_2x" 3.9 ns; - -#TIMESPEC "TS_ddr2_2x_to_cpu1" = FROM "ddr_in_clk_2x" TO "cpu_clk" 3.9 ns; -#TIMESPEC "TS_ddr2_2x_to_cpu2" = FROM "ddr_in_clk_2x" TO "cpu_clk_2x" 3.9 ns; -#TIMESPEC "TS_ddr2_2x_to_cpu4" = FROM "ddr_in_clk_2x" TO "cpu_clk_4x" 3.9 ns; -#TIMESPEC "TS_ddr2_2x_to_ddr2" = FROM "ddr_in_clk_2x" TO "ddr_in_clk" 3.9 ns; - - - diff --git a/zpu/hdl/zpu4/src/ic300.vhd b/zpu/hdl/zpu4/src/ic300.vhd deleted file mode 100644 index a1b4f41..0000000 --- a/zpu/hdl/zpu4/src/ic300.vhd +++ /dev/null @@ -1,144 +0,0 @@ --------------------------------------------------------------------------------- --- Company: Zylin AS --- Engineer: Tore Ramsland --- --- Create Date: 21:47:41 07/03/05 --- Design Name: ic300 --- Module Name: ic300 - behave --- Project Name: eCosBoard --- Target Device: XC3S400400-FG256 --- Tool versions: 7.1i --- Description: Top level --- --- Dependencies: --- --- Revision: --- 2005-07-11 Updated to test FPGA --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -library zylin; -use zylin.arm7.all; - -library zylin; -use zylin.zpu_config.all; -use zylin.zpupkg.all; - -library work; -use work.phi_config.all; -use work.ic300pkg.all; - -entity ic300 is - generic( - simulate_io_time : boolean := false); - port ( -- Clock inputs - cpu_clk_p : in std_logic; - - -- CPU interface signals - cpu_a_p : in std_logic_vector(20 downto 0); - cpu_wr_n_p : in std_logic_vector(1 downto 0); - cpu_cs_n_p : in std_logic_vector(3 downto 1); - cpu_oe_n_p : in std_logic; - cpu_d_p : inout std_logic_vector(15 downto 0); - cpu_irq_p : out std_logic_vector(1 downto 0); - cpu_fiq_p : out std_logic; - cpu_wait_n_p : out std_logic; - - -- DDR SDRAM Signals - sdr_clk_p : out std_logic; -- ddr_sdram_clock - sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock - cke_q_p : out std_logic; -- clock enable - cs_qn_p : out std_logic; -- /chip select - ras_qn_p : inout std_logic; -- /ras - cas_qn_p : inout std_logic; -- /cas - we_qn_p : inout std_logic; -- /write enable - dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00" - dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write - ba_q_p : out std_logic_vector(1 downto 0); -- bank select - sdr_a_p : out std_logic_vector(12 downto 0); -- address bus - sdr_d_p : inout std_logic_vector(15 downto 0); -- bidir data bus - sdr_clk_fb_p : in std_logic -- DDR clock feedback - ); -end ic300; - -architecture behave of ic300 is - -signal cpu_we : std_logic_vector(1 downto 0); -- Write signal for lower(0) and upper(1) 8 data bits -signal cpu_re : std_logic; -- Read enable signal for all 16 bits -signal areset : std_logic; -- Asyncronous active high reset (for initialization) -signal areset_dummy : std_logic; - --- Clock module signals -signal clk_status : std_logic_vector(2 downto 0); -- DLL lock status (from 3 DLL's) -signal cpu_clk : std_logic; -- 64 MHz CPU clk -signal cpu_clk_2x : std_logic; -- 128 MHz CPU clk (in phase with 64 MHz) -signal cpu_clk_4x : std_logic; -- 256 MHz CPU clk (in phase with 64 MHz) -signal ddr_in_clk : std_logic; -- 128 MHz clock from DDR SDRAM -signal ddr_in_clk_2x : std_logic; -- 256 MHz clock from DDR SDRAM - -- NOTE! Phase relation to 64 MHz clock unknown - --- Internal CPU interface signals -signal cpu_din : std_logic_vector(15 downto 0); -- 16-bit data from CPU -signal cpu_dout : std_logic_vector(15 downto 0); -- 16-bit data to CPU -signal cpu_a : std_logic_vector(20 downto 0); -- 21-bit address from CPU - -begin - --- areset <= '0'; - areset_dummy <= '0'; - - global_init_reset: - rocbuf port map(I=>areset_dummy,O=>areset); - - allclocks: - clocks port map( - areset => areset, - cpu_clk_p => cpu_clk_p, - cpu_clk => cpu_clk, - cpu_clk_2x => cpu_clk_2x, - cpu_clk_4x => cpu_clk_4x, - sdr_clk_fb_p => sdr_clk_fb_p, - ddr_in_clk => ddr_in_clk, - ddr_in_clk_2x => ddr_in_clk_2x, - locked => clk_status); - - arm7cpu: - arm7wb generic map (simulate_io_time => simulate_io_time) - port map( - areset => areset, - cpu_clk => cpu_clk, - cpu_clk_2x => cpu_clk_2x, - cpu_a_p => cpu_a_p, - cpu_wr_n_p => cpu_wr_n_p, - cpu_cs_n_p => cpu_cs_n_p, - cpu_oe_n_p => cpu_oe_n_p, - cpu_d_p => cpu_d_p, - cpu_irq_p => cpu_irq_p, - cpu_fiq_p => cpu_fiq_p, - cpu_wait_n_p => cpu_wait_n_p, - cpu_din => cpu_din, - cpu_a => cpu_a, - cpu_we => cpu_we, - cpu_re => cpu_re, - cpu_dout => cpu_dout); - - - cpu_fpga_regs: - zpuio port map( - areset => areset, - cpu_clk => cpu_clk, - clk_status => clk_status, - cpu_din => cpu_din, - cpu_a => cpu_a, - cpu_we => cpu_we, - cpu_re => cpu_re, - cpu_dout => cpu_dout); - - -end behave; diff --git a/zpu/hdl/zpu4/src/ic300_config.vhd b/zpu/hdl/zpu4/src/ic300_config.vhd deleted file mode 100644 index b14ec79..0000000 --- a/zpu/hdl/zpu4/src/ic300_config.vhd +++ /dev/null @@ -1,26 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.all; - -package phi_config is - - constant Fpga_Global_Base : std_logic_vector(19 downto 17) := "000"; -- 0x0800.... - constant Clock_Stat_Reg_Addr : std_logic_vector(5 downto 2) := "0000"; -- 0x....0000 - constant Ctrl_Reg_Addr : std_logic_vector(5 downto 2) := "0001"; -- 0x....0004 - constant output_enable : std_logic_vector(5 downto 2) := "0010"; -- 0x....0008 - constant output_disable : std_logic_vector(5 downto 2) := "0011"; -- 0x....000C - constant data_status : std_logic_vector(5 downto 2) := "0100"; -- 0x....0010 - constant set_output_data : std_logic_vector(5 downto 2) := "0101"; -- 0x....0014 - constant clear_output_data : std_logic_vector(5 downto 2) := "0110"; -- 0x....0018 - constant data_in_read : std_logic_vector(5 downto 2) := "0111"; -- 0x....001C - constant output_status : std_logic_vector(5 downto 2) := "1000"; -- 0x....0020 - constant cpu_access_address : std_logic_vector(5 downto 2) := "1001"; -- 0x....0024 - - constant Fpga_Ethernet_Reg_Base : std_logic_vector(19 downto 17) := "110"; -- 0x080C0000 - - constant Fpga_DDR_Ctrl_Base : std_logic_vector(19 downto 17) := "111"; -- 0x080E.... - constant DDR_Ctrl_Reg_Addr : std_logic_vector(3 downto 2) := "00"; -- 0x....0000 - constant DDR_Mode_Reg_Addr : std_logic_vector(3 downto 2) := "01"; -- 0x....0004 - constant DDR_Page_Select_Addr : std_logic_vector(3 downto 2) := "10"; -- 0x....0008 - - -end phi_config; diff --git a/zpu/hdl/zpu4/src/ic300pkg.vhd b/zpu/hdl/zpu4/src/ic300pkg.vhd deleted file mode 100644 index 13da306..0000000 --- a/zpu/hdl/zpu4/src/ic300pkg.vhd +++ /dev/null @@ -1,88 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.all; - -package ic300pkg is - - component ic300 is - port ( -- Clock inputs - cpu_clk_p : in std_logic; - - -- CPU interface signals - cpu_a_p : in std_logic_vector(20 downto 0); - cpu_wr_n_p : in std_logic_vector(1 downto 0); - cpu_cs_n_p : in std_logic_vector(3 downto 1); - cpu_oe_n_p : in std_logic; - cpu_d_p : inout std_logic_vector(15 downto 0); - cpu_irq_p : out std_logic_vector(1 downto 0); - cpu_fiq_p : out std_logic; - cpu_wait_n_p : out std_logic; - - -- DDR SDRAM Signals - sdr_clk_p : out std_logic; -- ddr_sdram_clock - sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock - cke_q_p : out std_logic; -- clock enable - cs_qn_p : out std_logic; -- /chip select - ras_qn_p : inout std_logic; -- /ras - cas_qn_p : inout std_logic; -- /cas - we_qn_p : inout std_logic; -- /write enable - dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00" - dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write - ba_q_p : out std_logic_vector(1 downto 0); -- bank select - sdr_a_p : out std_logic_vector(12 downto 0); -- address bus - sdr_d_p : inout std_logic_vector(15 downto 0); -- bidir data bus - sdr_clk_fb_p : in std_logic -- DDR clock feedback - ); - end component; - - component clocks is - port ( areset : in std_logic; - cpu_clk_p : in std_logic; - sdr_clk_fb_p : in std_logic; - cpu_clk : out std_logic; - cpu_clk_2x : out std_logic; - cpu_clk_4x : out std_logic; - ddr_in_clk : out std_logic; - ddr_in_clk_2x : out std_logic; - locked : out std_logic_vector(2 downto 0)); - end component; - - component cpu_regs is - port ( areset : in std_logic; - cpu_clk : in std_logic; - clk_status : in std_logic_vector(2 downto 0); - cpu_din : in std_logic_vector(15 downto 0); - cpu_a : in std_logic_vector(20 downto 0); - cpu_we : in std_logic_vector(1 downto 0); - cpu_re : in std_logic; - cpu_dout : inout std_logic_vector(15 downto 0)); - end component; - - component ddr_bridge is - port ( areset : in std_logic; - cpu_clk : in std_logic; - cpu_clk_2x : in std_logic; - cpu_clk_4x : in std_logic; - ddr_in_clk : in std_logic; - ddr_in_clk_2x : in std_logic; - - cpu_we : in std_logic_vector(1 downto 0); - cpu_re : in std_logic; - cpu_din : in std_logic_vector(15 downto 0); - cpu_a : in std_logic_vector(20 downto 0); - cpu_dout : inout std_logic_vector(15 downto 0); - - sdr_clk_p : out std_logic; -- ddr_sdram_clock - sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock - cke_q_p : out std_logic; -- clock enable - cs_qn_p : out std_logic; -- /chip select - ras_qn_p : inout std_logic; -- /ras - cas_qn_p : inout std_logic; -- /cas - we_qn_p : inout std_logic; -- /write enable - dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00" - dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write - ba_q_p : out std_logic_vector(1 downto 0); -- bank select - sdr_a_p : out std_logic_vector(12 downto 0); -- address bus - sdr_d_p : inout std_logic_vector(15 downto 0)); -- bidir data bus - end component; - -end ic300pkg; diff --git a/zpu/hdl/zpu4/src/xmake.filelist b/zpu/hdl/zpu4/src/xmake.filelist deleted file mode 100644 index 91e623f..0000000 --- a/zpu/hdl/zpu4/src/xmake.filelist +++ /dev/null @@ -1,12 +0,0 @@ -vhdl work "ic300_config.vhd" -vhdl work "ic300pkg.vhd" -vhdl zylin "zpu_config.vhd" -vhdl zylin "zpupkg.vhd" -vhdl zylin "zpu_core.vhd" -vhdl work "bram.vhd" -vhdl zylin "zpuio.vhd" -vhdl zylin "..\dummyfpgalib\arm7\src\arm7pkg.vhd" -vhdl zylin "..\dummyfpgalib\arm7\src\arm7wb.vhd" -vhdl work "clocks.vhd" -vhdl work "timer.vhd" -vhdl work "ic300.vhd" \ No newline at end of file diff --git a/zpu/hdl/zpu4/src/xmake.filelist.bramsmall b/zpu/hdl/zpu4/src/xmake.filelist.bramsmall deleted file mode 100644 index 141633e..0000000 --- a/zpu/hdl/zpu4/src/xmake.filelist.bramsmall +++ /dev/null @@ -1,5 +0,0 @@ -vhdl work "zpu_config.vhd" -vhdl work "zpupkg.vhd" -vhdl work "zpu_core_small.vhd" -vhdl work "bram_dmips.vhd" -vhdl work "testlut.vhd" diff --git a/zpu/hdl/zpu4/src/xmake.xst b/zpu/hdl/zpu4/src/xmake.xst deleted file mode 100644 index bfdb23f..0000000 --- a/zpu/hdl/zpu4/src/xmake.xst +++ /dev/null @@ -1,53 +0,0 @@ -set -tmpdir ../tmp -set -xsthdpdir ../xst -run --ifn xmake.filelist --ifmt mixed --ofn ../syn/ic300 --ofmt NGC --p xc3s400-4-ft256 --top ic300 --opt_mode Area --opt_level 2 --iuc NO --lso ic300.lso --keep_hierarchy NO --glob_opt AllClockNets --rtlview Yes --read_cores YES --write_timing_constraints NO --cross_clock_analysis NO --hierarchy_separator / --bus_delimiter <> --case maintain --slice_utilization_ratio 100 --verilog2001 YES --fsm_extract YES -fsm_encoding Auto --safe_implementation No --fsm_style lut --ram_extract Yes --ram_style Auto --rom_extract Yes --rom_style Auto --mux_extract YES --mux_style Auto --decoder_extract YES --priority_extract YES --shreg_extract YES --shift_extract YES --xor_collapse YES --resource_sharing YES --mult_style auto --iobuf YES --max_fanout 500 --bufg 8 --register_duplication YES --equivalent_register_removal NO --register_balancing No --slice_packing YES --optimize_primitives NO --use_clock_enable Yes --use_sync_set No --use_sync_reset No --iob true --slice_utilization_ratio_maxmargin 5 diff --git a/zpu/hdl/zpu4/src/zpuio_bram.vhd b/zpu/hdl/zpu4/src/zpuio_bram.vhd deleted file mode 100644 index 5d3f409..0000000 --- a/zpu/hdl/zpu4/src/zpuio_bram.vhd +++ /dev/null @@ -1,229 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - -entity zpuio is - port ( areset : in std_logic; - cpu_clk : in std_logic; - clk_status : in std_logic_vector(2 downto 0); - cpu_din : in std_logic_vector(15 downto 0); - cpu_a : in std_logic_vector(20 downto 0); - cpu_we : in std_logic_vector(1 downto 0); - cpu_re : in std_logic; - cpu_dout : inout std_logic_vector(15 downto 0)); -end zpuio; - -architecture behave of zpuio is - -signal timer_read : std_logic_vector(7 downto 0); ---signal timer_write : std_logic_vector(7 downto 0); -signal timer_we : std_logic; - - -signal io_busy : std_logic; -signal io_read : std_logic_vector(7 downto 0); ---signal io_write : std_logic_vector(7 downto 0); -signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit); -signal io_writeEnable : std_logic; -signal Enable : std_logic; - -signal din : std_logic_vector(7 downto 0); -signal dout : std_logic_vector(7 downto 0); -signal adr : std_logic_vector(15 downto 0); -signal break : std_logic; -signal we : std_logic; -signal re : std_logic; - - --- uart forwarding... - -signal uartTXPending : std_logic; -signal uartTXCleared : std_logic; -signal uartData : std_logic_vector(7 downto 0); - -signal readingTimer : std_logic; - - - - -signal mem_busy : std_logic; -signal mem_read : std_logic_vector(wordSize-1 downto 0); -signal mem_write : std_logic_vector(wordSize-1 downto 0); -signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); -signal mem_writeEnable : std_logic; -signal mem_readEnable : std_logic; -signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0); - - - - ---signal io_mem_read : std_logic_vector(7 downto 0); ---signal io_mem_writeEnable : std_logic; ---signal io_mem_readEnable : std_logic; -signal io_readEnable : std_logic; - - - - - -begin - - io_addr <= mem_addr(maxAddrBit downto minAddrBit); - - timerinst: timer port map ( - clk => cpu_clk, - areset => areset, - we => timer_we, - din => mem_write(7 downto 0), - adr => io_addr(4 downto 2), - dout => timer_read); - - zpu: zpu_core port map ( - clk => cpu_clk , - areset => areset, - in_mem_busy => mem_busy, - mem_read => mem_read, - mem_write => mem_write, - out_mem_addr => mem_addr, - out_mem_writeEnable => mem_writeEnable, - out_mem_readEnable => mem_readEnable, - mem_writeMask => mem_writeMask, - interrupt => '0', - break => break); - - - - - -- Read/write are on different addresses - -- The registers are 8 bits and mapped to bit[7:0] - -- - -- 0xC000 Write: Writes to UART TX FIFO (4 byte FIFO) - -- Read : Reads from UART RX FIFO (4 byte FIFO) - -- 0xC004 Read : UART status register - -- Bit 0 = RX FIFO empty - -- Bit 1 = TX FIFO full - -- 0xA000 Skrive: LED's (8 stk.) - - -- 0x9000 Write: bit 0: 1= reset counter - -- 0= counter running - -- bit 1: 1= sample counter (when set to 1) - -- 0=not used - -- Read : counter bit[7:0] - -- 0x9004 Read: counter bit [15:8] - -- 0x9008 Read: counter bit [23:16] - -- 0x900C Read: counter bit [31:24] - -- 0x9010 Read: counter bit [39:32] - -- 0x9014 Read: counter bit [47:40] - -- 0x9018 Read: counter bit [55:48] - -- 0x901C Read: counter bit [63:56] - -- - -- 0x8800 Read: unsigned 8-bit integer with FPGA frequency (in MHz) - - fauxUart: - process(cpu_clk, areset) - begin - if areset = '1' then - io_busy <= '0'; - uartTXPending <= '0'; - timer_we <= '0'; - io_busy <= '0'; - uartData <= x"58"; -- 'X' - readingTimer <= '0'; - elsif (cpu_clk'event and cpu_clk = '1') then - timer_we <= '0'; - io_busy <= '0'; - if uartTXCleared = '1' then - uartTXPending <= '0'; - end if; - - if io_writeEnable = '1' then - if io_addr=x"1000" then - -- Write to UART - uartData <= mem_write(7 downto 0); - uartTXPending <= '1'; - io_busy <= '1'; - elsif io_addr(12)='1' then - timer_we <= '1'; - io_busy <= '1'; - else - report "Illegal IO write" severity failure; - end if; - end if; - if (io_readEnable = '1') then - if io_addr=x"1001" then - io_read <= (0=>'1', -- recieve empty - 1 => uartTXPending, -- tx full - others => '0'); - io_busy <= '1'; - elsif io_addr(12)='1' then - readingTimer <= '1'; - io_busy <= '1'; - elsif io_addr(11)='1' then - io_read <= ZPU_Frequency; - io_busy <= '1'; - else - report "Illegal IO read" severity failure; - end if; - - else - if (readingTimer = '1') then - readingTimer <= '0'; - io_read <= timer_read; - io_busy <= '0'; - else - io_read <= (others => '1'); - end if; - end if; - end if; - end process; - - - forwardUARTOutputToARM: - process(cpu_clk, areset) - begin - if areset = '1' then - uartTXCleared <= '0'; - elsif (cpu_clk = '1' and cpu_clk'event) then - if cpu_we(0) = '1' and cpu_a(3 downto 1) = "000" then - uartTXCleared <= cpu_din(0); - else - uartTXCleared <= uartTXCleared; - end if; - end if; - end process; - - cpu_dout(7 downto 0) <= uartData when (cpu_re = '1' and cpu_a(3 downto 1) = "001") else (others => 'Z'); - cpu_dout <= (0 => uartTXPending, others => '0') when (cpu_re = '1' and cpu_a(3 downto 1) = "000") else (others => 'Z'); - - io_writeEnable <= mem_writeEnable and mem_addr(ioBit); --- io_readEnable <= mem_readEnable and mem_addr(ioBit); - mem_busy <= io_busy or io_readEnable; - - -- Memory reads either come from IO or DRAM. We need to pick the right one. - memorycontrol: - process(cpu_clk, areset) - begin - if areset = '1' then - io_readEnable <= '0'; - - - elsif (cpu_clk'event and cpu_clk = '1') then - mem_read <= (others => '0'); - - if mem_addr(ioBit)='1' and mem_readEnable='1' then - io_readEnable <= '1'; - end if; - if io_readEnable='1' and io_busy='0' then - io_readEnable <= '0'; - mem_read(7 downto 0) <= io_read; - end if; - - end if; - end process; - - -end behave; -- cgit v1.1 From 167263dcae188a8812627ab52cfd96b8fdc5df8a Mon Sep 17 00:00:00 2001 From: oharboe Date: Thu, 17 Apr 2008 08:31:56 +0000 Subject: * deleted duplicate files from example folder. --- zpu/ChangeLog | 1 + zpu/hdl/example/io.vhd | 97 ----------------- zpu/hdl/example/sim_fpga_top.vhd | 179 -------------------------------- zpu/hdl/example/simzpu_small.do | 4 +- zpu/hdl/zpu4/src/sim_small_fpga_top.vhd | 179 ++++++++++++++++++++++++++++++++ 5 files changed, 182 insertions(+), 278 deletions(-) delete mode 100644 zpu/hdl/example/io.vhd delete mode 100644 zpu/hdl/example/sim_fpga_top.vhd create mode 100644 zpu/hdl/zpu4/src/sim_small_fpga_top.vhd diff --git a/zpu/ChangeLog b/zpu/ChangeLog index 9b722e8..331ea74 100644 --- a/zpu/ChangeLog +++ b/zpu/ChangeLog @@ -1,4 +1,5 @@ 2008-04-17 Øyvind Harboe + * deleted duplicate files from example folder. * retired Xilinx synthesizing example. It messes up the zpu4 directory. 2008-04-16 Øyvind Harboe * zpu/doc/zpupresentation_old.odt: interesting bits moved into zpu_arch.html diff --git a/zpu/hdl/example/io.vhd b/zpu/hdl/example/io.vhd deleted file mode 100644 index 7dbe36f..0000000 --- a/zpu/hdl/example/io.vhd +++ /dev/null @@ -1,97 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -use std.textio.all; - -library work; -use work.zpu_config.all; -use work.zpupkg.all; -use work.txt_util.all; - -entity zpu_io is - generic ( - log_file: string := "log.txt" - ); - port( - clk : in std_logic; - areset : in std_logic; - busy : out std_logic; - writeEnable : in std_logic; - readEnable : in std_logic; - write : in std_logic_vector(wordSize-1 downto 0); - read : out std_logic_vector(wordSize-1 downto 0); - addr : in std_logic_vector(maxAddrBit downto minAddrBit) - ); -end zpu_io; - - -architecture behave of zpu_io is - - - -signal timer_read : std_logic_vector(7 downto 0); ---signal timer_write : std_logic_vector(7 downto 0); -signal timer_we : std_logic; - -signal serving : std_logic; - -file l_file : TEXT open write_mode is log_file; - -begin - - - timerinst: timer port map ( - clk => clk, - areset => areset, - we => timer_we, - din => write(7 downto 0), - adr => addr(4 downto 2), - dout => timer_read); - - busy <= writeEnable or readEnable; - timer_we <= writeEnable and addr(12); - - process(areset, clk) - begin - if (areset = '1') then --- timer_we <= '0'; - elsif (clk'event and clk = '1') then --- timer_we <= '0'; - if writeEnable = '1' then - -- external interface - if addr=x"2028003" then - -- Write to UART - -- report "" & character'image(conv_integer(memBint)) severity note; - print(l_file, character'val(conv_integer(write))); - elsif addr(12)='1' then --- report "xxx" severity failure; --- timer_we <= '1'; - else - print(l_file, character'val(conv_integer(write))); - report "Illegal IO write" severity warning; - end if; - - end if; - read <= (others => '0'); - if (readEnable = '1') then - if addr=x"1001" then - read <= (0=>'1', others => '0'); -- recieve empty - elsif addr(12)='1' then - read(7 downto 0) <= timer_read; - elsif addr(11)='1' then - read(7 downto 0) <= ZPU_Frequency; - elsif addr=x"2028003" then - read <= (others => '0'); - else - read <= (others => '0'); - read(8) <= '1'; - report "Illegal IO read" severity warning; - end if; - end if; - end if; - end process; - - -end behave; - diff --git a/zpu/hdl/example/sim_fpga_top.vhd b/zpu/hdl/example/sim_fpga_top.vhd deleted file mode 100644 index b51fea0..0000000 --- a/zpu/hdl/example/sim_fpga_top.vhd +++ /dev/null @@ -1,179 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 20:15:31 04/14/05 --- Design Name: --- Module Name: fpga_top - behave --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - -entity fpga_top is -end fpga_top; - -architecture behave of fpga_top is - - -signal clk : std_logic; - -signal areset : std_logic; - - -component zpu_io is - generic ( - log_file: string := "log.txt" - ); - port( - clk : in std_logic; - areset : in std_logic; - busy : out std_logic; - writeEnable : in std_logic; - readEnable : in std_logic; - write : in std_logic_vector(wordSize-1 downto 0); - read : out std_logic_vector(wordSize-1 downto 0); - addr : in std_logic_vector(maxAddrBit downto minAddrBit) - ); -end component; - - - - - -signal mem_busy : std_logic; -signal mem_read : std_logic_vector(wordSize-1 downto 0); -signal mem_write : std_logic_vector(wordSize-1 downto 0); -signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); -signal mem_writeEnable : std_logic; -signal mem_readEnable : std_logic; -signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0); - -signal enable : std_logic; - -signal dram_mem_busy : std_logic; -signal dram_mem_read : std_logic_vector(wordSize-1 downto 0); -signal dram_mem_write : std_logic_vector(wordSize-1 downto 0); -signal dram_mem_writeEnable : std_logic; -signal dram_mem_readEnable : std_logic; -signal dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0); - - -signal io_busy : std_logic; - -signal io_mem_read : std_logic_vector(wordSize-1 downto 0); -signal io_mem_writeEnable : std_logic; -signal io_mem_readEnable : std_logic; - - -signal dram_ready : std_logic; -signal io_ready : std_logic; -signal io_reading : std_logic; - - -signal break : std_logic; - -begin - poweronreset: roc port map (O => areset); - - - - zpu: zpu_core port map ( - clk => clk , - areset => areset, - enable => enable, - in_mem_busy => mem_busy, - mem_read => mem_read, - mem_write => mem_write, - out_mem_addr => mem_addr, - out_mem_writeEnable => mem_writeEnable, - out_mem_readEnable => mem_readEnable, - mem_writeMask => mem_writeMask, - interrupt => '0', - break => break); - - - ioMap: zpu_io port map ( - clk => clk, - areset => areset, - busy => io_busy, - writeEnable => io_mem_writeEnable, - readEnable => io_mem_readEnable, - write => mem_write, - read => io_mem_read, - addr => mem_addr(maxAddrBit downto minAddrBit) - ); - - dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit); - dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit); - io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit); - io_mem_readEnable <= mem_readEnable and mem_addr(ioBit); - mem_busy <= io_busy; - - - - -- Memory reads either come from IO or DRAM. We need to pick the right one. - memorycontrol: - process(dram_mem_read, dram_ready, io_ready, io_mem_read) - begin - mem_read <= (others => 'U'); - if dram_ready='1' then - mem_read <= dram_mem_read; - end if; - - if io_ready='1' then - mem_read <= (others => '0'); - mem_read <= io_mem_read; - end if; - end process; - - - io_ready <= (io_reading or io_mem_readEnable) and not io_busy; - - memoryControlSync: - process(clk, areset) - begin - if areset = '1' then - enable <= '0'; - io_reading <= '0'; - dram_ready <= '0'; - elsif (clk'event and clk = '1') then - enable <= '1'; - io_reading <= io_busy or io_mem_readEnable; - dram_ready<=dram_mem_readEnable; - - end if; - end process; - - -- wiggle the clock @ 100MHz - clock : PROCESS - begin - clk <= '0'; - wait for 5 ns; - clk <= '1'; - wait for 5 ns; - end PROCESS clock; - - -end behave; diff --git a/zpu/hdl/example/simzpu_small.do b/zpu/hdl/example/simzpu_small.do index 5fb906d..1f8f358 100644 --- a/zpu/hdl/example/simzpu_small.do +++ b/zpu/hdl/example/simzpu_small.do @@ -10,11 +10,11 @@ vlib work vcom -93 -explicit zpu_config.vhd vcom -93 -explicit ../zpu4/src/zpupkg.vhd vcom -93 -explicit ../zpu4/src/txt_util.vhd -vcom -93 -explicit sim_fpga_top.vhd +vcom -93 -explicit ../zpu4/src/sim_small_fpga_top.vhd vcom -93 -explicit ../zpu4/src/zpu_core_small.vhd vcom -93 -explicit helloworld.vhd vcom -93 -explicit ../zpu4/src/timer.vhd -vcom -93 -explicit io.vhd +vcom -93 -explicit ../zpu4/src/io.vhd vcom -93 -explicit ../zpu4/src/trace.vhd # run ZPU diff --git a/zpu/hdl/zpu4/src/sim_small_fpga_top.vhd b/zpu/hdl/zpu4/src/sim_small_fpga_top.vhd new file mode 100644 index 0000000..b51fea0 --- /dev/null +++ b/zpu/hdl/zpu4/src/sim_small_fpga_top.vhd @@ -0,0 +1,179 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 20:15:31 04/14/05 +-- Design Name: +-- Module Name: fpga_top - behave +-- Project Name: +-- Target Device: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity fpga_top is +end fpga_top; + +architecture behave of fpga_top is + + +signal clk : std_logic; + +signal areset : std_logic; + + +component zpu_io is + generic ( + log_file: string := "log.txt" + ); + port( + clk : in std_logic; + areset : in std_logic; + busy : out std_logic; + writeEnable : in std_logic; + readEnable : in std_logic; + write : in std_logic_vector(wordSize-1 downto 0); + read : out std_logic_vector(wordSize-1 downto 0); + addr : in std_logic_vector(maxAddrBit downto minAddrBit) + ); +end component; + + + + + +signal mem_busy : std_logic; +signal mem_read : std_logic_vector(wordSize-1 downto 0); +signal mem_write : std_logic_vector(wordSize-1 downto 0); +signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); +signal mem_writeEnable : std_logic; +signal mem_readEnable : std_logic; +signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + +signal enable : std_logic; + +signal dram_mem_busy : std_logic; +signal dram_mem_read : std_logic_vector(wordSize-1 downto 0); +signal dram_mem_write : std_logic_vector(wordSize-1 downto 0); +signal dram_mem_writeEnable : std_logic; +signal dram_mem_readEnable : std_logic; +signal dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + + +signal io_busy : std_logic; + +signal io_mem_read : std_logic_vector(wordSize-1 downto 0); +signal io_mem_writeEnable : std_logic; +signal io_mem_readEnable : std_logic; + + +signal dram_ready : std_logic; +signal io_ready : std_logic; +signal io_reading : std_logic; + + +signal break : std_logic; + +begin + poweronreset: roc port map (O => areset); + + + + zpu: zpu_core port map ( + clk => clk , + areset => areset, + enable => enable, + in_mem_busy => mem_busy, + mem_read => mem_read, + mem_write => mem_write, + out_mem_addr => mem_addr, + out_mem_writeEnable => mem_writeEnable, + out_mem_readEnable => mem_readEnable, + mem_writeMask => mem_writeMask, + interrupt => '0', + break => break); + + + ioMap: zpu_io port map ( + clk => clk, + areset => areset, + busy => io_busy, + writeEnable => io_mem_writeEnable, + readEnable => io_mem_readEnable, + write => mem_write, + read => io_mem_read, + addr => mem_addr(maxAddrBit downto minAddrBit) + ); + + dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit); + dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit); + io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit); + io_mem_readEnable <= mem_readEnable and mem_addr(ioBit); + mem_busy <= io_busy; + + + + -- Memory reads either come from IO or DRAM. We need to pick the right one. + memorycontrol: + process(dram_mem_read, dram_ready, io_ready, io_mem_read) + begin + mem_read <= (others => 'U'); + if dram_ready='1' then + mem_read <= dram_mem_read; + end if; + + if io_ready='1' then + mem_read <= (others => '0'); + mem_read <= io_mem_read; + end if; + end process; + + + io_ready <= (io_reading or io_mem_readEnable) and not io_busy; + + memoryControlSync: + process(clk, areset) + begin + if areset = '1' then + enable <= '0'; + io_reading <= '0'; + dram_ready <= '0'; + elsif (clk'event and clk = '1') then + enable <= '1'; + io_reading <= io_busy or io_mem_readEnable; + dram_ready<=dram_mem_readEnable; + + end if; + end process; + + -- wiggle the clock @ 100MHz + clock : PROCESS + begin + clk <= '0'; + wait for 5 ns; + clk <= '1'; + wait for 5 ns; + end PROCESS clock; + + +end behave; -- cgit v1.1 From d09fa3de9df02a66c5084623076ac3e167b58274 Mon Sep 17 00:00:00 2001 From: oharboe Date: Tue, 22 Apr 2008 05:52:16 +0000 Subject: * zpu/hdl/example_ghdl/ghdl_import.sh, zpu/hdl/example_ghdl/ghdl_make.sh, zpu/hdl/example_ghdl/ghdl_options.sh, zpu/hdl/example_ghdl/README: GHDL example * zpu/hdl/zpu4/src/dmipssmalltrace_ghdl.sh: testcase for GHDL * zpu/hdl/zpu4/src/dmipstrace_ghdl.sh: testcase for GHDL * zpu/hdl/zpu4/src/simzpu_medium_ghdl.sh: testcase for GHDL * zpu/hdl/example/helloworld.vhd, zpu/hdl/zpu4/src/bram_dmips.vhd, zpu/hdl/zpu4/src/dmipssmalltrace_ghdl.sh, zpu/hdl/zpu4/src/dram_dmips.vhd, zpu/hdl/zpu4/src/dram_hello.vhd, zpu/hdl/zpu4/src/io.vhd, zpu/hdl/zpu4/src/sim_fpga_top.vhd, zpu/hdl/zpu4/src/sim_small_fpga_top.vhd, zpu/hdl/zpu4/src/timer.vhd, zpu/hdl/zpu4/src/trace.vhd, zpu/hdl/zpu4/src/zpu_config_trace.vhd, zpu/hdl/zpu4/src/zpu_core_small.vhd, zpu/hdl/zpu4/src/zpu_core.vhd, zpu/hdl/zpu4/src/zpupkg.vhd: conversion to numeric_std --- zpu/ChangeLog | 13 + zpu/hdl/example/helloworld.vhd | 12 +- zpu/hdl/example_ghdl/README | 74 ++ zpu/hdl/example_ghdl/ghdl_import.sh | 13 + zpu/hdl/example_ghdl/ghdl_make.sh | 4 + zpu/hdl/example_ghdl/ghdl_options.sh | 3 + zpu/hdl/zpu4/src/bram_dmips.vhd | 12 +- zpu/hdl/zpu4/src/dmipssmalltrace_ghdl.sh | 26 + zpu/hdl/zpu4/src/dmipstrace_ghdl.sh | 25 + zpu/hdl/zpu4/src/dram_dmips.vhd | 8 +- zpu/hdl/zpu4/src/dram_hello.vhd | 8 +- zpu/hdl/zpu4/src/io.vhd | 6 +- zpu/hdl/zpu4/src/log.txt | 414 +++++-- zpu/hdl/zpu4/src/sim_fpga_top.vhd | 377 ++++--- zpu/hdl/zpu4/src/sim_small_fpga_top.vhd | 356 +++--- zpu/hdl/zpu4/src/simzpu_medium_ghdl.sh | 25 + zpu/hdl/zpu4/src/timer.vhd | 6 +- zpu/hdl/zpu4/src/trace.vhd | 7 +- zpu/hdl/zpu4/src/zpu_config_trace.vhd | 1 - zpu/hdl/zpu4/src/zpu_core.vhd | 1795 +++++++++++++++--------------- zpu/hdl/zpu4/src/zpu_core_small.vhd | 880 ++++++++------- zpu/hdl/zpu4/src/zpupkg.vhd | 44 +- 22 files changed, 2262 insertions(+), 1847 deletions(-) create mode 100644 zpu/hdl/example_ghdl/README create mode 100644 zpu/hdl/example_ghdl/ghdl_import.sh create mode 100644 zpu/hdl/example_ghdl/ghdl_make.sh create mode 100644 zpu/hdl/example_ghdl/ghdl_options.sh create mode 100644 zpu/hdl/zpu4/src/dmipssmalltrace_ghdl.sh create mode 100644 zpu/hdl/zpu4/src/dmipstrace_ghdl.sh create mode 100644 zpu/hdl/zpu4/src/simzpu_medium_ghdl.sh diff --git a/zpu/ChangeLog b/zpu/ChangeLog index 331ea74..249ff02 100644 --- a/zpu/ChangeLog +++ b/zpu/ChangeLog @@ -1,3 +1,16 @@ +2008-04-17 Arnim Läuger + * zpu/hdl/example_ghdl/ghdl_import.sh, zpu/hdl/example_ghdl/ghdl_make.sh, + zpu/hdl/example_ghdl/ghdl_options.sh, zpu/hdl/example_ghdl/README: GHDL example + * zpu/hdl/zpu4/src/dmipssmalltrace_ghdl.sh: testcase for GHDL + * zpu/hdl/zpu4/src/dmipstrace_ghdl.sh: testcase for GHDL + * zpu/hdl/zpu4/src/simzpu_medium_ghdl.sh: testcase for GHDL + * zpu/hdl/example/helloworld.vhd, zpu/hdl/zpu4/src/bram_dmips.vhd, + zpu/hdl/zpu4/src/dmipssmalltrace_ghdl.sh, zpu/hdl/zpu4/src/dram_dmips.vhd, + zpu/hdl/zpu4/src/dram_hello.vhd, zpu/hdl/zpu4/src/io.vhd, + zpu/hdl/zpu4/src/sim_fpga_top.vhd, zpu/hdl/zpu4/src/sim_small_fpga_top.vhd, + zpu/hdl/zpu4/src/timer.vhd, zpu/hdl/zpu4/src/trace.vhd, + zpu/hdl/zpu4/src/zpu_config_trace.vhd, zpu/hdl/zpu4/src/zpu_core_small.vhd, + zpu/hdl/zpu4/src/zpu_core.vhd, zpu/hdl/zpu4/src/zpupkg.vhd: conversion to numeric_std 2008-04-17 Øyvind Harboe * deleted duplicate files from example folder. * retired Xilinx synthesizing example. It messes up the zpu4 directory. diff --git a/zpu/hdl/example/helloworld.vhd b/zpu/hdl/example/helloworld.vhd index 2e5ce4e..f9383fd 100644 --- a/zpu/hdl/example/helloworld.vhd +++ b/zpu/hdl/example/helloworld.vhd @@ -1,6 +1,6 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; library work; @@ -22,7 +22,7 @@ end dualport_ram; architecture dualport_ram_arch of dualport_ram is -type ram_type is array(0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); +type ram_type is array(natural range 0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); shared variable ram : ram_type := ( @@ -3094,10 +3094,10 @@ begin end if; if (memAWriteEnable = '1') then - ram(conv_integer(memAAddr)) := memAWrite; + ram(to_integer(unsigned(memAAddr))) := memAWrite; memARead <= memAWrite; else - memARead <= ram(conv_integer(memAAddr)); + memARead <= ram(to_integer(unsigned(memAAddr))); end if; end if; end process; @@ -3106,10 +3106,10 @@ process (clk) begin if (clk'event and clk = '1') then if (memBWriteEnable = '1') then - ram(conv_integer(memBAddr)) := memBWrite; + ram(to_integer(unsigned(memBAddr))) := memBWrite; memBRead <= memBWrite; else - memBRead <= ram(conv_integer(memBAddr)); + memBRead <= ram(to_integer(unsigned(memBAddr))); end if; end if; end process; diff --git a/zpu/hdl/example_ghdl/README b/zpu/hdl/example_ghdl/README new file mode 100644 index 0000000..c537284 --- /dev/null +++ b/zpu/hdl/example_ghdl/README @@ -0,0 +1,74 @@ +This directory contains a quick setup of the helloworld example for +the GHDL simulator. + + http://ghdl.free.fr/ + +Compiled by Arnim Laeuger, 17-Apr-2008. + + +Prerequisites +------------- + +The RTL source code references the ROC component from Xilinx' unisim +library. If not already done, you'll have to prepare this library containing +at least the roc entity and architecture objects. + +Decide where to store this library. This could be locally in this directory or +at some central place where it can be referenced from other projects. I'd +prefer the latter option. + + $ cd + +Prepare the sources for GHDL: + $ mkdir src + $ cd src + $ ghdl --chop /vhdl/src/unisims/* + $ cd .. + +Import the sources into the library: + $ mkdir unisim_v93 + $ ghdl -i --work=unisim --workdir=unisim_v93 --std=93 -fexplicit --no-vital-checks --ieee=synopsys src/* + +Compile the required component: + $ ghdl -m --syn-binding --work=unisim --workdir=unisim_v93 --std=93 -fexplicit --no-vital-checks --ieee=synopsys roc + $ rm roc + -> not required for library + +If you require more components from the unisim library for other projects, you +can repeat the compile step later on without running through the preparation +and import steps. + + +Compiling the example +--------------------- + +Edit ghdl_options.sh and point the variable UNISIM_DIR to the location of your +newly created unisim library. + +You need to import the project sources once by running + $ ./ghdl_import.sh + +Compilation (using GHDL's make feature) is invoked by + $ ./ghdl_make.sh + +Whenever the VHDL sources change, it's enough to execute ghdl_make.sh. GHDL +will trace the dependencies and will rebuild only the modified sources. + + +Simulation +---------- + +Simulation finally happens by running the fpga_top executable generated by the +compilation step. Don't forget to set a stop time or the testbench might run +forever: + + $ ./fpga_top --stop-time=2100us + +The log.txt and trace.txt files are generated as simulation progresses. They +should be compared to the files given in the example directory. + +Waveforms can be obtained by specifying the ghw file name: + + $ ./fpga_top --stop-time=1ms --wave=zpu.ghw + +They can be inspected with gtkwave from http://home.nc.rr.com/gtkwave/. diff --git a/zpu/hdl/example_ghdl/ghdl_import.sh b/zpu/hdl/example_ghdl/ghdl_import.sh new file mode 100644 index 0000000..299134b --- /dev/null +++ b/zpu/hdl/example_ghdl/ghdl_import.sh @@ -0,0 +1,13 @@ +#!/bin/sh +. ghdl_options.sh + +mkdir -p work +ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/zpu_config.vhd +ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/zpupkg.vhd +ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/helloworld.vhd +ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/txt_util.vhd +ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/trace.vhd +ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/zpu_core_small.vhd +ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/io.vhd +ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/timer.vhd +ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/sim_small_fpga_top.vhd diff --git a/zpu/hdl/example_ghdl/ghdl_make.sh b/zpu/hdl/example_ghdl/ghdl_make.sh new file mode 100644 index 0000000..948b100 --- /dev/null +++ b/zpu/hdl/example_ghdl/ghdl_make.sh @@ -0,0 +1,4 @@ +#!/bin/sh +. ghdl_options.sh + +ghdl -m ${MAKE_OPTIONS} fpga_top diff --git a/zpu/hdl/example_ghdl/ghdl_options.sh b/zpu/hdl/example_ghdl/ghdl_options.sh new file mode 100644 index 0000000..3883ee7 --- /dev/null +++ b/zpu/hdl/example_ghdl/ghdl_options.sh @@ -0,0 +1,3 @@ +UNISIM_DIR="'location of GHDL objects for unisim library'/unisim_v93" +IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work -P${UNISIM_DIR}" +MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding" diff --git a/zpu/hdl/zpu4/src/bram_dmips.vhd b/zpu/hdl/zpu4/src/bram_dmips.vhd index 83bfc28..1d62d21 100644 --- a/zpu/hdl/zpu4/src/bram_dmips.vhd +++ b/zpu/hdl/zpu4/src/bram_dmips.vhd @@ -1,6 +1,6 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; library work; @@ -22,7 +22,7 @@ end dualport_ram; architecture dualport_ram_arch of dualport_ram is -type ram_type is array(0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); +type ram_type is array(natural range 0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); shared variable ram : ram_type := ( @@ -3691,10 +3691,10 @@ begin end if; if (memAWriteEnable = '1') then - ram(conv_integer(memAAddr)) := memAWrite; + ram(to_integer(unsigned(memAAddr))) := memAWrite; memARead <= memAWrite; else - memARead <= ram(conv_integer(memAAddr)); + memARead <= ram(to_integer(unsigned(memAAddr))); end if; end if; end process; @@ -3703,10 +3703,10 @@ process (clk) begin if (clk'event and clk = '1') then if (memBWriteEnable = '1') then - ram(conv_integer(memBAddr)) := memBWrite; + ram(to_integer(unsigned(memBAddr))) := memBWrite; memBRead <= memBWrite; else - memBRead <= ram(conv_integer(memBAddr)); + memBRead <= ram(to_integer(unsigned(memBAddr))); end if; end if; end process; diff --git a/zpu/hdl/zpu4/src/dmipssmalltrace_ghdl.sh b/zpu/hdl/zpu4/src/dmipssmalltrace_ghdl.sh new file mode 100644 index 0000000..5e43b64 --- /dev/null +++ b/zpu/hdl/zpu4/src/dmipssmalltrace_ghdl.sh @@ -0,0 +1,26 @@ +#!/bin/sh + +UNISIM_DIR="'location of GHDL objects for unisim library'/unisim_v93" +IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work -P${UNISIM_DIR}" +MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding" + +if test ! -e work; then + echo "Building work library..." + mkdir work + ghdl -i ${IMPORT_OPTIONS} zpu_config_trace.vhd + ghdl -i ${IMPORT_OPTIONS} zpupkg.vhd + ghdl -i ${IMPORT_OPTIONS} txt_util.vhd + ghdl -i ${IMPORT_OPTIONS} sim_fpga_top.vhd + ghdl -i ${IMPORT_OPTIONS} zpu_core_small.vhd + ghdl -i ${IMPORT_OPTIONS} bram_dmips.vhd + ghdl -i ${IMPORT_OPTIONS} dram_dmips.vhd + ghdl -i ${IMPORT_OPTIONS} timer.vhd + ghdl -i ${IMPORT_OPTIONS} io.vhd + ghdl -i ${IMPORT_OPTIONS} trace.vhd +fi + +echo "Compiling design..." +if ghdl -m ${MAKE_OPTIONS} fpga_top; then + echo "Compilation finished, start simulation with" + echo " ./fpga_top --stop-time=1ms" +fi diff --git a/zpu/hdl/zpu4/src/dmipstrace_ghdl.sh b/zpu/hdl/zpu4/src/dmipstrace_ghdl.sh new file mode 100644 index 0000000..3be392f --- /dev/null +++ b/zpu/hdl/zpu4/src/dmipstrace_ghdl.sh @@ -0,0 +1,25 @@ +#!/bin/sh + +UNISIM_DIR="'location of GHDL objects for unisim library'/unisim_v93" +IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work -P${UNISIM_DIR}" +MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding" + +if test ! -e work; then + echo "Building work library..." + mkdir work + ghdl -i ${IMPORT_OPTIONS} zpu_config_trace.vhd + ghdl -i ${IMPORT_OPTIONS} zpupkg.vhd + ghdl -i ${IMPORT_OPTIONS} txt_util.vhd + ghdl -i ${IMPORT_OPTIONS} sim_fpga_top.vhd + ghdl -i ${IMPORT_OPTIONS} zpu_core.vhd + ghdl -i ${IMPORT_OPTIONS} dram_dmips.vhd + ghdl -i ${IMPORT_OPTIONS} timer.vhd + ghdl -i ${IMPORT_OPTIONS} io.vhd + ghdl -i ${IMPORT_OPTIONS} trace.vhd +fi + +echo "Compiling design..." +if ghdl -m ${MAKE_OPTIONS} fpga_top; then + echo "Compilation finished, start simulation with" + echo " ./fpga_top --stop-time=2500us" +fi diff --git a/zpu/hdl/zpu4/src/dram_dmips.vhd b/zpu/hdl/zpu4/src/dram_dmips.vhd index a289fd7..a9fd59e 100644 --- a/zpu/hdl/zpu4/src/dram_dmips.vhd +++ b/zpu/hdl/zpu4/src/dram_dmips.vhd @@ -1,6 +1,6 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; library work; @@ -22,7 +22,7 @@ end dram; architecture dram_arch of dram is -type ram_type is array(0 to ((2**(maxAddrBitDRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); +type ram_type is array(natural range 0 to ((2**(maxAddrBitDRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); shared variable ram : ram_type := ( @@ -3294,10 +3294,10 @@ begin if areset = '1' then elsif (clk'event and clk = '1') then if (mem_writeEnable = '1') then - ram(conv_integer(mem_addr(maxAddrBit downto minAddrBit))) := mem_write; + ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit)))) := mem_write; end if; if (mem_readEnable = '1') then - mem_read <= ram(conv_integer(mem_addr(maxAddrBit downto minAddrBit))); + mem_read <= ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit)))); end if; end if; end process; diff --git a/zpu/hdl/zpu4/src/dram_hello.vhd b/zpu/hdl/zpu4/src/dram_hello.vhd index 3f7788a..4f02cca 100644 --- a/zpu/hdl/zpu4/src/dram_hello.vhd +++ b/zpu/hdl/zpu4/src/dram_hello.vhd @@ -1,6 +1,6 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; library work; @@ -22,7 +22,7 @@ end dram; architecture dram_arch of dram is -type ram_type is array(0 to ((2**(maxAddrBitDRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); +type ram_type is array(natural range 0 to ((2**(maxAddrBitDRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); shared variable ram : ram_type := ( @@ -3093,10 +3093,10 @@ begin if areset = '1' then elsif (clk'event and clk = '1') then if (mem_writeEnable = '1') then - ram(conv_integer(mem_addr(maxAddrBit downto minAddrBit))) := mem_write; + ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit)))) := mem_write; end if; if (mem_readEnable = '1') then - mem_read <= ram(conv_integer(mem_addr(maxAddrBit downto minAddrBit))); + mem_read <= ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit)))); end if; end if; end process; diff --git a/zpu/hdl/zpu4/src/io.vhd b/zpu/hdl/zpu4/src/io.vhd index 7dbe36f..7a2601f 100644 --- a/zpu/hdl/zpu4/src/io.vhd +++ b/zpu/hdl/zpu4/src/io.vhd @@ -1,6 +1,6 @@ library ieee; use ieee.std_logic_1164.all; -use IEEE.STD_LOGIC_UNSIGNED.ALL; +use ieee.numeric_std.all; use std.textio.all; @@ -63,12 +63,12 @@ begin if addr=x"2028003" then -- Write to UART -- report "" & character'image(conv_integer(memBint)) severity note; - print(l_file, character'val(conv_integer(write))); + print(l_file, character'val(to_integer(unsigned(write)))); elsif addr(12)='1' then -- report "xxx" severity failure; -- timer_we <= '1'; else - print(l_file, character'val(conv_integer(write))); + print(l_file, character'val(to_integer(unsigned(write)))); report "Illegal IO write" severity warning; end if; diff --git a/zpu/hdl/zpu4/src/log.txt b/zpu/hdl/zpu4/src/log.txt index 47b8a65..7a82879 100644 --- a/zpu/hdl/zpu4/src/log.txt +++ b/zpu/hdl/zpu4/src/log.txt @@ -1,156 +1,380 @@ +H +e +l +l +o + +w +o +r +l +d + +1 -D -h -r -y -s -t -o -n + + + +H e +l +l +o -B -e -n -c -h -m -a +w +o r -k -, +l +d -V +2 + + + + + + +H e -r -s -i +l +l o -n -2 -. -1 +w +o +r +l +d -( -L -a -n -g -u -a -g +1 + + + + + + +H e -: +l +l +o + +w +o +r +l +d -C -) +2 -P +H +e +l +l +o + +w +o r +l +d + +1 + + + + + + +H +e +l +l +o + +w o -g r -a -m +l +d + +2 + + + + + + +H +e +l +l +o -c +w o -m -p -i +r l +d + +1 + + + + + + +H e +l +l +o + +w +o +r +l d +2 + + + + + + +H +e +l +l +o + w -i -t -h o -u -t +r +l +d + +1 + + + + + + +H +e +l +l +o -' +w +o r +l +d + +2 + + + + + + +H e -g -i -s -t +l +l +o + +w +o +r +l +d + +1 + + + + + + +H e +l +l +o + +w +o r -' +l +d + +2 + + + + + + +H +e +l +l +o -a -t -t +w +o r -i -b -u -t +l +d + +1 + + + + + + +H e +l +l +o + +w +o +r +l +d + +2 -E -x +H e -c -u -t -i +l +l o -n -s -t -a +w +o r -t -s -, +l +d -5 -0 -0 -0 -0 +1 + + + + + + +H +e +l +l +o +w +o r -u -n -s +l +d -t -h +2 + + + + + + +H +e +l +l +o + +w +o r +l +d + +1 + + + + + + +H +e +l +l o -u -g -h -D -h +w +o r -y -s -t +l +d + +2 + + + + + + +H +e +l +l o -n + +w +o +r +l +d + +1 + + + + + + +H e +l +l +o + +w +o +r +l +d + +2 + + + - diff --git a/zpu/hdl/zpu4/src/sim_fpga_top.vhd b/zpu/hdl/zpu4/src/sim_fpga_top.vhd index 4defc82..29151af 100644 --- a/zpu/hdl/zpu4/src/sim_fpga_top.vhd +++ b/zpu/hdl/zpu4/src/sim_fpga_top.vhd @@ -1,189 +1,188 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 20:15:31 04/14/05 --- Design Name: --- Module Name: fpga_top - behave --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - -entity fpga_top is -end fpga_top; - -architecture behave of fpga_top is - - -signal clk : std_logic; - -signal areset : std_logic; - - -component zpu_io is - generic ( - log_file: string := "log.txt" - ); - port( - clk : in std_logic; - areset : in std_logic; - busy : out std_logic; - writeEnable : in std_logic; - readEnable : in std_logic; - write : in std_logic_vector(wordSize-1 downto 0); - read : out std_logic_vector(wordSize-1 downto 0); - addr : in std_logic_vector(maxAddrBit downto minAddrBit) - ); -end component; - - - - - -signal mem_busy : std_logic; -signal mem_read : std_logic_vector(wordSize-1 downto 0); -signal mem_write : std_logic_vector(wordSize-1 downto 0); -signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); -signal mem_writeEnable : std_logic; -signal mem_readEnable : std_logic; -signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0); - -signal enable : std_logic; - -signal dram_mem_busy : std_logic; -signal dram_mem_read : std_logic_vector(wordSize-1 downto 0); -signal dram_mem_write : std_logic_vector(wordSize-1 downto 0); -signal dram_mem_writeEnable : std_logic; -signal dram_mem_readEnable : std_logic; -signal dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0); - - -signal io_busy : std_logic; - -signal io_mem_read : std_logic_vector(wordSize-1 downto 0); -signal io_mem_writeEnable : std_logic; -signal io_mem_readEnable : std_logic; - - -signal dram_ready : std_logic; -signal io_ready : std_logic; -signal io_reading : std_logic; - - -signal break : std_logic; - -begin - poweronreset: roc port map (O => areset); - - - - zpu: zpu_core port map ( - clk => clk , - areset => areset, - enable => enable, - in_mem_busy => mem_busy, - mem_read => mem_read, - mem_write => mem_write, - out_mem_addr => mem_addr, - out_mem_writeEnable => mem_writeEnable, - out_mem_readEnable => mem_readEnable, - mem_writeMask => mem_writeMask, - interrupt => '0', - break => break); - - dram_imp: dram port map ( - clk => clk , - areset => areset, - mem_busy => dram_mem_busy, - mem_read => dram_mem_read, - mem_write => mem_write, - mem_addr => mem_addr(maxAddrBit downto 0), - mem_writeEnable => dram_mem_writeEnable, - mem_readEnable => dram_mem_readEnable, - mem_writeMask => mem_writeMask); - - - ioMap: zpu_io port map ( - clk => clk, - areset => areset, - busy => io_busy, - writeEnable => io_mem_writeEnable, - readEnable => io_mem_readEnable, - write => mem_write(wordSize-1 downto 0), - read => io_mem_read, - addr => mem_addr(maxAddrBit downto minAddrBit) - ); - - dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit); - dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit); - io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit); - io_mem_readEnable <= mem_readEnable and mem_addr(ioBit); - mem_busy <= io_busy or dram_mem_busy or io_busy; - - - - -- Memory reads either come from IO or DRAM. We need to pick the right one. - memorycontrol: - process(dram_mem_read, dram_ready, io_ready, io_mem_read) - begin - mem_read <= (others => 'U'); - if dram_ready='1' then - mem_read <= dram_mem_read; - end if; - - if io_ready='1' then - mem_read <= io_mem_read; - end if; - end process; - - - io_ready <= (io_reading or io_mem_readEnable) and not io_busy; - - memoryControlSync: - process(clk, areset) - begin - if areset = '1' then - enable <= '0'; - io_reading <= '0'; - dram_ready <= '0'; - elsif (clk'event and clk = '1') then - enable <= '1'; - io_reading <= io_busy or io_mem_readEnable; - dram_ready<=dram_mem_readEnable; - - end if; - end process; - - -- wiggle the clock @ 100MHz - clock : PROCESS - begin - clk <= '0'; - wait for 5 ns; - clk <= '1'; - wait for 5 ns; - end PROCESS clock; - - -end behave; +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 20:15:31 04/14/05 +-- Design Name: +-- Module Name: fpga_top - behave +-- Project Name: +-- Target Device: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +library work; +use work.zpu_config.all; + +entity fpga_top is +end fpga_top; + +use work.zpupkg.all; + +architecture behave of fpga_top is + + +signal clk : std_logic; + +signal areset : std_logic; + + +component zpu_io is + generic ( + log_file: string := "log.txt" + ); + port( + clk : in std_logic; + areset : in std_logic; + busy : out std_logic; + writeEnable : in std_logic; + readEnable : in std_logic; + write : in std_logic_vector(wordSize-1 downto 0); + read : out std_logic_vector(wordSize-1 downto 0); + addr : in std_logic_vector(maxAddrBit downto minAddrBit) + ); +end component; + + + + + +signal mem_busy : std_logic; +signal mem_read : std_logic_vector(wordSize-1 downto 0); +signal mem_write : std_logic_vector(wordSize-1 downto 0); +signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); +signal mem_writeEnable : std_logic; +signal mem_readEnable : std_logic; +signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + +signal enable : std_logic; + +signal dram_mem_busy : std_logic; +signal dram_mem_read : std_logic_vector(wordSize-1 downto 0); +signal dram_mem_write : std_logic_vector(wordSize-1 downto 0); +signal dram_mem_writeEnable : std_logic; +signal dram_mem_readEnable : std_logic; +signal dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + + +signal io_busy : std_logic; + +signal io_mem_read : std_logic_vector(wordSize-1 downto 0); +signal io_mem_writeEnable : std_logic; +signal io_mem_readEnable : std_logic; + + +signal dram_ready : std_logic; +signal io_ready : std_logic; +signal io_reading : std_logic; + + +signal break : std_logic; + +begin + poweronreset: roc port map (O => areset); + + + + zpu: zpu_core port map ( + clk => clk , + areset => areset, + enable => enable, + in_mem_busy => mem_busy, + mem_read => mem_read, + mem_write => mem_write, + out_mem_addr => mem_addr, + out_mem_writeEnable => mem_writeEnable, + out_mem_readEnable => mem_readEnable, + mem_writeMask => mem_writeMask, + interrupt => '0', + break => break); + + dram_imp: dram port map ( + clk => clk , + areset => areset, + mem_busy => dram_mem_busy, + mem_read => dram_mem_read, + mem_write => mem_write, + mem_addr => mem_addr(maxAddrBit downto 0), + mem_writeEnable => dram_mem_writeEnable, + mem_readEnable => dram_mem_readEnable, + mem_writeMask => mem_writeMask); + + + ioMap: zpu_io port map ( + clk => clk, + areset => areset, + busy => io_busy, + writeEnable => io_mem_writeEnable, + readEnable => io_mem_readEnable, + write => mem_write(wordSize-1 downto 0), + read => io_mem_read, + addr => mem_addr(maxAddrBit downto minAddrBit) + ); + + dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit); + dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit); + io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit); + io_mem_readEnable <= mem_readEnable and mem_addr(ioBit); + mem_busy <= io_busy or dram_mem_busy or io_busy; + + + + -- Memory reads either come from IO or DRAM. We need to pick the right one. + memorycontrol: + process(dram_mem_read, dram_ready, io_ready, io_mem_read) + begin + mem_read <= (others => 'U'); + if dram_ready='1' then + mem_read <= dram_mem_read; + end if; + + if io_ready='1' then + mem_read <= io_mem_read; + end if; + end process; + + + io_ready <= (io_reading or io_mem_readEnable) and not io_busy; + + memoryControlSync: + process(clk, areset) + begin + if areset = '1' then + enable <= '0'; + io_reading <= '0'; + dram_ready <= '0'; + elsif (clk'event and clk = '1') then + enable <= '1'; + io_reading <= io_busy or io_mem_readEnable; + dram_ready<=dram_mem_readEnable; + + end if; + end process; + + -- wiggle the clock @ 100MHz + clock : PROCESS + begin + clk <= '0'; + wait for 5 ns; + clk <= '1'; + wait for 5 ns; + end PROCESS clock; + + +end behave; diff --git a/zpu/hdl/zpu4/src/sim_small_fpga_top.vhd b/zpu/hdl/zpu4/src/sim_small_fpga_top.vhd index b51fea0..5c05881 100644 --- a/zpu/hdl/zpu4/src/sim_small_fpga_top.vhd +++ b/zpu/hdl/zpu4/src/sim_small_fpga_top.vhd @@ -1,179 +1,177 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 20:15:31 04/14/05 --- Design Name: --- Module Name: fpga_top - behave --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - -entity fpga_top is -end fpga_top; - -architecture behave of fpga_top is - - -signal clk : std_logic; - -signal areset : std_logic; - - -component zpu_io is - generic ( - log_file: string := "log.txt" - ); - port( - clk : in std_logic; - areset : in std_logic; - busy : out std_logic; - writeEnable : in std_logic; - readEnable : in std_logic; - write : in std_logic_vector(wordSize-1 downto 0); - read : out std_logic_vector(wordSize-1 downto 0); - addr : in std_logic_vector(maxAddrBit downto minAddrBit) - ); -end component; - - - - - -signal mem_busy : std_logic; -signal mem_read : std_logic_vector(wordSize-1 downto 0); -signal mem_write : std_logic_vector(wordSize-1 downto 0); -signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); -signal mem_writeEnable : std_logic; -signal mem_readEnable : std_logic; -signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0); - -signal enable : std_logic; - -signal dram_mem_busy : std_logic; -signal dram_mem_read : std_logic_vector(wordSize-1 downto 0); -signal dram_mem_write : std_logic_vector(wordSize-1 downto 0); -signal dram_mem_writeEnable : std_logic; -signal dram_mem_readEnable : std_logic; -signal dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0); - - -signal io_busy : std_logic; - -signal io_mem_read : std_logic_vector(wordSize-1 downto 0); -signal io_mem_writeEnable : std_logic; -signal io_mem_readEnable : std_logic; - - -signal dram_ready : std_logic; -signal io_ready : std_logic; -signal io_reading : std_logic; - - -signal break : std_logic; - -begin - poweronreset: roc port map (O => areset); - - - - zpu: zpu_core port map ( - clk => clk , - areset => areset, - enable => enable, - in_mem_busy => mem_busy, - mem_read => mem_read, - mem_write => mem_write, - out_mem_addr => mem_addr, - out_mem_writeEnable => mem_writeEnable, - out_mem_readEnable => mem_readEnable, - mem_writeMask => mem_writeMask, - interrupt => '0', - break => break); - - - ioMap: zpu_io port map ( - clk => clk, - areset => areset, - busy => io_busy, - writeEnable => io_mem_writeEnable, - readEnable => io_mem_readEnable, - write => mem_write, - read => io_mem_read, - addr => mem_addr(maxAddrBit downto minAddrBit) - ); - - dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit); - dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit); - io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit); - io_mem_readEnable <= mem_readEnable and mem_addr(ioBit); - mem_busy <= io_busy; - - - - -- Memory reads either come from IO or DRAM. We need to pick the right one. - memorycontrol: - process(dram_mem_read, dram_ready, io_ready, io_mem_read) - begin - mem_read <= (others => 'U'); - if dram_ready='1' then - mem_read <= dram_mem_read; - end if; - - if io_ready='1' then - mem_read <= (others => '0'); - mem_read <= io_mem_read; - end if; - end process; - - - io_ready <= (io_reading or io_mem_readEnable) and not io_busy; - - memoryControlSync: - process(clk, areset) - begin - if areset = '1' then - enable <= '0'; - io_reading <= '0'; - dram_ready <= '0'; - elsif (clk'event and clk = '1') then - enable <= '1'; - io_reading <= io_busy or io_mem_readEnable; - dram_ready<=dram_mem_readEnable; - - end if; - end process; - - -- wiggle the clock @ 100MHz - clock : PROCESS - begin - clk <= '0'; - wait for 5 ns; - clk <= '1'; - wait for 5 ns; - end PROCESS clock; - - -end behave; +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 20:15:31 04/14/05 +-- Design Name: +-- Module Name: fpga_top - behave +-- Project Name: +-- Target Device: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity fpga_top is +end fpga_top; + +architecture behave of fpga_top is + + +signal clk : std_logic; + +signal areset : std_logic; + + +component zpu_io is + generic ( + log_file: string := "log.txt" + ); + port( + clk : in std_logic; + areset : in std_logic; + busy : out std_logic; + writeEnable : in std_logic; + readEnable : in std_logic; + write : in std_logic_vector(wordSize-1 downto 0); + read : out std_logic_vector(wordSize-1 downto 0); + addr : in std_logic_vector(maxAddrBit downto minAddrBit) + ); +end component; + + + + + +signal mem_busy : std_logic; +signal mem_read : std_logic_vector(wordSize-1 downto 0); +signal mem_write : std_logic_vector(wordSize-1 downto 0); +signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); +signal mem_writeEnable : std_logic; +signal mem_readEnable : std_logic; +signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + +signal enable : std_logic; + +signal dram_mem_busy : std_logic; +signal dram_mem_read : std_logic_vector(wordSize-1 downto 0); +signal dram_mem_write : std_logic_vector(wordSize-1 downto 0); +signal dram_mem_writeEnable : std_logic; +signal dram_mem_readEnable : std_logic; +signal dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + + +signal io_busy : std_logic; + +signal io_mem_read : std_logic_vector(wordSize-1 downto 0); +signal io_mem_writeEnable : std_logic; +signal io_mem_readEnable : std_logic; + + +signal dram_ready : std_logic; +signal io_ready : std_logic; +signal io_reading : std_logic; + + +signal break : std_logic; + +begin + poweronreset: roc port map (O => areset); + + + + zpu: zpu_core port map ( + clk => clk , + areset => areset, + enable => enable, + in_mem_busy => mem_busy, + mem_read => mem_read, + mem_write => mem_write, + out_mem_addr => mem_addr, + out_mem_writeEnable => mem_writeEnable, + out_mem_readEnable => mem_readEnable, + mem_writeMask => mem_writeMask, + interrupt => '0', + break => break); + + + ioMap: zpu_io port map ( + clk => clk, + areset => areset, + busy => io_busy, + writeEnable => io_mem_writeEnable, + readEnable => io_mem_readEnable, + write => mem_write, + read => io_mem_read, + addr => mem_addr(maxAddrBit downto minAddrBit) + ); + + dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit); + dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit); + io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit); + io_mem_readEnable <= mem_readEnable and mem_addr(ioBit); + mem_busy <= io_busy; + + + + -- Memory reads either come from IO or DRAM. We need to pick the right one. + memorycontrol: + process(dram_mem_read, dram_ready, io_ready, io_mem_read) + begin + mem_read <= (others => 'U'); + if dram_ready='1' then + mem_read <= dram_mem_read; + end if; + + if io_ready='1' then + mem_read <= (others => '0'); + mem_read <= io_mem_read; + end if; + end process; + + + io_ready <= (io_reading or io_mem_readEnable) and not io_busy; + + memoryControlSync: + process(clk, areset) + begin + if areset = '1' then + enable <= '0'; + io_reading <= '0'; + dram_ready <= '0'; + elsif (clk'event and clk = '1') then + enable <= '1'; + io_reading <= io_busy or io_mem_readEnable; + dram_ready<=dram_mem_readEnable; + + end if; + end process; + + -- wiggle the clock @ 100MHz + clock : PROCESS + begin + clk <= '0'; + wait for 5 ns; + clk <= '1'; + wait for 5 ns; + end PROCESS clock; + + +end behave; diff --git a/zpu/hdl/zpu4/src/simzpu_medium_ghdl.sh b/zpu/hdl/zpu4/src/simzpu_medium_ghdl.sh new file mode 100644 index 0000000..7a7f3df --- /dev/null +++ b/zpu/hdl/zpu4/src/simzpu_medium_ghdl.sh @@ -0,0 +1,25 @@ +#!/bin/sh + +UNISIM_DIR="'location of GHDL objects for unisim library'/unisim_v93" +IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work -P${UNISIM_DIR}" +MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding" + +if test ! -e work; then + echo "Building work library..." + mkdir work + ghdl -i ${IMPORT_OPTIONS} zpu_config_trace.vhd + ghdl -i ${IMPORT_OPTIONS} zpupkg.vhd + ghdl -i ${IMPORT_OPTIONS} txt_util.vhd + ghdl -i ${IMPORT_OPTIONS} sim_fpga_top.vhd + ghdl -i ${IMPORT_OPTIONS} zpu_core.vhd + ghdl -i ${IMPORT_OPTIONS} dram_hello.vhd + ghdl -i ${IMPORT_OPTIONS} timer.vhd + ghdl -i ${IMPORT_OPTIONS} io.vhd + ghdl -i ${IMPORT_OPTIONS} trace.vhd +fi + +echo "Compiling design..." +if ghdl -m ${MAKE_OPTIONS} fpga_top; then + echo "Compilation finished, start simulation with" + echo " ./fpga_top --stop-time=1ms" +fi diff --git a/zpu/hdl/zpu4/src/timer.vhd b/zpu/hdl/zpu4/src/timer.vhd index 60c8fe2..be1dbb8 100644 --- a/zpu/hdl/zpu4/src/timer.vhd +++ b/zpu/hdl/zpu4/src/timer.vhd @@ -1,6 +1,6 @@ library ieee; use ieee.std_logic_1164.all; -use IEEE.STD_LOGIC_UNSIGNED.ALL; +use ieee.numeric_std.all; entity timer is port( @@ -19,7 +19,7 @@ signal sample : std_logic; signal reset : std_logic; -signal cnt : std_logic_vector(63 downto 0); +signal cnt : unsigned(63 downto 0); signal cnt_smp : std_logic_vector(63 downto 0); begin @@ -36,7 +36,7 @@ begin cnt <= cnt + 1; if sample = '1' then -- report "sampling" severity failure; - cnt_smp <= cnt; + cnt_smp <= std_logic_vector(cnt); end if; end if; end process; diff --git a/zpu/hdl/zpu4/src/trace.vhd b/zpu/hdl/zpu4/src/trace.vhd index bc5279f..e687aaf 100644 --- a/zpu/hdl/zpu4/src/trace.vhd +++ b/zpu/hdl/zpu4/src/trace.vhd @@ -1,7 +1,6 @@ library ieee; use ieee.std_logic_1164.all; ---use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; +use ieee.numeric_std.all; use std.textio.all; @@ -45,7 +44,7 @@ receive_data: process variable l: line; variable t : std_logic_vector(wordSize-1 downto 0); variable t2 : std_logic_vector(maxAddrBitIncIO downto 0); -variable counter : std_logic_vector(63 downto 0); +variable counter : unsigned(63 downto 0); @@ -69,7 +68,7 @@ counter := (others => '0'); if begin_inst = '1' then t(maxAddrBitIncIO downto 2):=sp; t2:=pc; - print(l_file, "0x" & hstr(t2) & " 0x" & hstr(opcode) & " 0x" & hstr(t) & " 0x" & hstr(memA) & " 0x" & hstr(memB) & " 0x" & hstr(intSp) & " 0x" & hstr(counter)); + print(l_file, "0x" & hstr(t2) & " 0x" & hstr(opcode) & " 0x" & hstr(t) & " 0x" & hstr(memA) & " 0x" & hstr(memB) & " 0x" & hstr(intSp) & " 0x" & hstr(std_logic_vector(counter))); end if; wait until clk = '0'; diff --git a/zpu/hdl/zpu4/src/zpu_config_trace.vhd b/zpu/hdl/zpu4/src/zpu_config_trace.vhd index 4d0f15f..d765d9a 100644 --- a/zpu/hdl/zpu4/src/zpu_config_trace.vhd +++ b/zpu/hdl/zpu4/src/zpu_config_trace.vhd @@ -1,6 +1,5 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; package zpu_config is diff --git a/zpu/hdl/zpu4/src/zpu_core.vhd b/zpu/hdl/zpu4/src/zpu_core.vhd index a603fe9..37fa2d1 100644 --- a/zpu/hdl/zpu4/src/zpu_core.vhd +++ b/zpu/hdl/zpu4/src/zpu_core.vhd @@ -1,898 +1,897 @@ - --- Company: ZPU4 generic memory interface CPU --- Engineer: Øyvind Harboe - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -use IEEE.STD_LOGIC_arith.ALL; - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - - --- mem_writeEnable - set to '1' for a single cycle to send off a write request. --- mem_write is valid only while mem_writeEnable='1'. --- mem_readEnable - set to '1' for a single cycle to send off a read request. --- --- mem_busy - It is illegal to send off a read/write request when mem_busy='1'. --- Set to '0' when mem_read is valid after a read request. --- If it goes to '1'(busy), it is on the cycle after mem_read/writeEnable --- is '1'. --- mem_addr - address for read/write request --- mem_read - read data. Valid only on the cycle after mem_busy='0' after --- mem_readEnable='1' for a single cycle. --- mem_write - data to write --- mem_writeMask - set to '1' for those bits that are to be written to memory upon --- write request --- break - set to '1' when CPU hits break instruction --- interrupt - set to '1' until interrupts are cleared by CPU. - - - - -entity zpu_core is - Port ( clk : in std_logic; - areset : in std_logic; - enable : in std_logic; - in_mem_busy : in std_logic; - mem_read : in std_logic_vector(wordSize-1 downto 0); - mem_write : out std_logic_vector(wordSize-1 downto 0); - out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); - out_mem_writeEnable : out std_logic; - out_mem_readEnable : out std_logic; - mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); - interrupt : in std_logic; - break : out std_logic); -end zpu_core; - -architecture behave of zpu_core is - -type InsnType is -( -State_AddTop, -State_Dup, -State_DupStackB, -State_Pop, -State_Popdown, -State_Add, -State_Or, -State_And, -State_Store, -State_AddSP, -State_Shift, -State_Nop, -State_Im, -State_LoadSP, -State_StoreSP, -State_Emulate, -State_Load, -State_PushPC, -State_PushSP, -State_PopPC, -State_PopPCRel, -State_Not, -State_Flip, -State_PopSP, -State_Neqbranch, -State_Eq, -State_Loadb, -State_Mult, -State_Lessthan, -State_Lessthanorequal, -State_Ulessthanorequal, -State_Ulessthan, -State_Pushspadd, -State_Call, -State_Callpcrel, -State_Sub, -State_Break, -State_Storeb, -State_InsnFetch -); - -type StateType is -( -State_Load2, -State_Popped, -State_LoadSP2, -State_LoadSP3, -State_AddSP2, -State_Fetch, -State_Execute, -State_Decode, -State_Decode2, -State_Resync, - -State_StoreSP2, -State_Resync2, -State_Resync3, -State_Loadb2, -State_Storeb2, -State_Mult2, -State_Mult3, -State_Mult5, -State_Mult4, -State_BinaryOpResult2, -State_BinaryOpResult, -State_Idle -); - - -signal pc : std_logic_vector(maxAddrBitIncIO downto 0); -signal sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal incSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal incIncSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal decSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal stackA : std_logic_vector(wordSize-1 downto 0); -signal binaryOpResult : std_logic_vector(wordSize-1 downto 0); -signal binaryOpResult2 : std_logic_vector(wordSize-1 downto 0); -signal multResult2 : std_logic_vector(wordSize-1 downto 0); -signal multResult3 : std_logic_vector(wordSize-1 downto 0); -signal multResult : std_logic_vector(wordSize-1 downto 0); -signal multA : std_logic_vector(wordSize-1 downto 0); -signal multB : std_logic_vector(wordSize-1 downto 0); -signal stackB : std_logic_vector(wordSize-1 downto 0); -signal idim_flag : std_logic; -signal busy : std_logic; -signal mem_writeEnable : std_logic; -signal mem_readEnable : std_logic; -signal mem_addr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal mem_delayAddr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal mem_delayReadEnable : std_logic; - -signal decodeWord : std_logic_vector(wordSize-1 downto 0); - - -signal state : StateType; -signal insn : InsnType; -type InsnArray is array(0 to wordBytes-1) of InsnType; -signal decodedOpcode : InsnArray; - -type OpcodeArray is array(0 to wordBytes-1) of std_logic_vector(7 downto 0); - -signal opcode : OpcodeArray; - - - - -signal begin_inst : std_logic; -signal trace_opcode : std_logic_vector(7 downto 0); -signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); -signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); -signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); - --- state machine. - -begin - - - traceFileGenerate: - if Generate_Trace generate - trace_file: trace port map ( - clk => clk, - begin_inst => begin_inst, - pc => trace_pc, - opcode => trace_opcode, - sp => trace_sp, - memA => trace_topOfStack, - memB => trace_topOfStackB, - busy => busy, - intsp => (others => 'U') - ); - end generate; - - - -- the memory subsystem will tell us one cycle later whether or - -- not it is busy - out_mem_writeEnable <= mem_writeEnable; - out_mem_readEnable <= mem_readEnable; - out_mem_addr(maxAddrBitIncIO downto minAddrBit) <= mem_addr; - out_mem_addr(minAddrBit-1 downto 0) <= (others => '0'); - - incSp <= sp + 1; - incIncSp <= sp + 2; - decSp <= sp - 1; - - - opcodeControl: - process(clk, areset) - variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); - variable spOffset : std_logic_vector(4 downto 0); - variable tSpOffset : std_logic_vector(4 downto 0); - variable nextPC : std_logic_vector(maxAddrBitIncIO downto 0); - variable tNextState : InsnType; - variable tDecodedOpcode : InsnArray; - variable tMultResult : std_logic_vector(wordSize*2-1 downto 0); - begin - if areset = '1' then - state <= State_Idle; - break <= '0'; - sp <= spStart(maxAddrBitIncIO downto minAddrBit); - - pc <= (others => '0'); - idim_flag <= '0'; - begin_inst <= '0'; - mem_writeEnable <= '0'; - mem_readEnable <= '0'; - multA <= (others => '0'); - multB <= (others => '0'); - mem_writeMask <= (others => '1'); - elsif (clk'event and clk = '1') then - -- we must multiply unconditionally to get pipelined multiplication - tMultResult := multA * multB; - multResult3 <= multResult2; - multResult2 <= multResult; - multResult <= tMultResult(wordSize-1 downto 0); - - - binaryOpResult2 <= binaryOpResult; -- pipeline a bit. - - - multA <= (others => DontCareValue); - multB <= (others => DontCareValue); - - - mem_addr <= (others => DontCareValue); - mem_readEnable <='0'; - mem_writeEnable <='0'; - mem_write <= (others => DontCareValue); - - if (mem_writeEnable = '1') and (mem_readEnable = '1') then - report "read/write collision" severity failure; - end if; - - - - - spOffset(4):=not opcode(conv_integer(pc(byteBits-1 downto 0)))(4); - spOffset(3 downto 0):=opcode(conv_integer(pc(byteBits-1 downto 0)))(3 downto 0); - nextPC := pc + 1; - - -- prepare trace snapshot - trace_opcode <= opcode(conv_integer(pc(byteBits-1 downto 0))); - trace_pc <= pc; - trace_sp <= sp; - trace_topOfStack <= stackA; - trace_topOfStackB <= stackB; - begin_inst <= '0'; - - - case state is - when State_Idle => - if enable='1' then - state <= State_Resync; - end if; - -- Initial state of ZPU, fetch top of stack + first instruction - when State_Resync => - if in_mem_busy='0' then - mem_addr <= sp; - mem_readEnable <= '1'; - state <= State_Resync2; - end if; - when State_Resync2 => - if in_mem_busy='0' then - stackA <= mem_read; - mem_addr <= incSp; - mem_readEnable <= '1'; - state <= State_Resync3; - end if; - when State_Resync3 => - if in_mem_busy='0' then - stackB <= mem_read; - mem_addr <= pc(maxAddrBitIncIO downto minAddrBit); - mem_readEnable <= '1'; - state <= State_Decode; - end if; - when State_Decode => - if in_mem_busy='0' then - decodeWord <= mem_read; - state <= State_Decode2; - end if; - when State_Decode2 => - -- decode 4 instructions in parallel - for i in 0 to wordBytes-1 loop - tOpcode := decodeWord((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8); - - tSpOffset(4):=not tOpcode(4); - tSpOffset(3 downto 0):=tOpcode(3 downto 0); - - opcode(i) <= tOpcode; - if (tOpcode(7 downto 7)=OpCode_Im) then - tNextState:=State_Im; - elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then - if tSpOffset = 0 then - tNextState := State_Pop; - elsif tSpOffset=1 then - tNextState := State_PopDown; - else - tNextState :=State_StoreSP; - end if; - elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then - if tSpOffset = 0 then - tNextState :=State_Dup; - elsif tSpOffset = 1 then - tNextState :=State_DupStackB; - else - tNextState :=State_LoadSP; - end if; - elsif (tOpcode(7 downto 5)=OpCode_Emulate) then - tNextState :=State_Emulate; - if tOpcode(5 downto 0)=OpCode_Neqbranch then - tNextState :=State_Neqbranch; - elsif tOpcode(5 downto 0)=OpCode_Eq then - tNextState :=State_Eq; - elsif tOpcode(5 downto 0)=OpCode_Lessthan then - tNextState :=State_Lessthan; - elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then - --tNextState :=State_Lessthanorequal; - elsif tOpcode(5 downto 0)=OpCode_Ulessthan then - tNextState :=State_Ulessthan; - elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then - --tNextState :=State_Ulessthanorequal; - elsif tOpcode(5 downto 0)=OpCode_Loadb then - tNextState :=State_Loadb; - elsif tOpcode(5 downto 0)=OpCode_Mult then - tNextState :=State_Mult; - elsif tOpcode(5 downto 0)=OpCode_Storeb then - tNextState :=State_Storeb; - elsif tOpcode(5 downto 0)=OpCode_Pushspadd then - tNextState :=State_Pushspadd; - elsif tOpcode(5 downto 0)=OpCode_Callpcrel then - tNextState :=State_Callpcrel; - elsif tOpcode(5 downto 0)=OpCode_Call then - --tNextState :=State_Call; - elsif tOpcode(5 downto 0)=OpCode_Sub then - tNextState :=State_Sub; - elsif tOpcode(5 downto 0)=OpCode_PopPCRel then - --tNextState :=State_PopPCRel; - end if; - elsif (tOpcode(7 downto 4)=OpCode_AddSP) then - if tSpOffset = 0 then - tNextState := State_Shift; - elsif tSpOffset = 1 then - tNextState := State_AddTop; - else - tNextState :=State_AddSP; - end if; - else - case tOpcode(3 downto 0) is - when OpCode_Nop => - tNextState :=State_Nop; - when OpCode_PushSP => - tNextState :=State_PushSP; - when OpCode_PopPC => - tNextState :=State_PopPC; - when OpCode_Add => - tNextState :=State_Add; - when OpCode_Or => - tNextState :=State_Or; - when OpCode_And => - tNextState :=State_And; - when OpCode_Load => - tNextState :=State_Load; - when OpCode_Not => - tNextState :=State_Not; - when OpCode_Flip => - tNextState :=State_Flip; - when OpCode_Store => - tNextState :=State_Store; - when OpCode_PopSP => - tNextState :=State_PopSP; - when others => - tNextState := State_Break; - - end case; - end if; - tDecodedOpcode(i) := tNextState; - - end loop; - - insn <= tDecodedOpcode(conv_integer(pc(byteBits-1 downto 0))); - - -- once we wrap, we need to fetch - tDecodedOpcode(0) := State_InsnFetch; - - decodedOpcode <= tDecodedOpcode; - state <= State_Execute; - - - - -- Each instruction must: - -- - -- 1. set idim_flag - -- 2. increase pc if applicable - -- 3. set next state if appliable - -- 4. do it's operation - - when State_Execute => - insn <= decodedOpcode(conv_integer(nextPC(byteBits-1 downto 0))); - - case insn is - when State_InsnFetch => - state <= State_Fetch; - when State_Im => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '1'; - pc <= pc + 1; - - if idim_flag='1' then - stackA(wordSize-1 downto 7) <= stackA(wordSize-8 downto 0); - stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0); - else - mem_writeEnable <= '1'; - mem_addr <= incSp; - mem_write <= stackB; - stackB <= stackA; - sp <= decSp; - for i in wordSize-1 downto 7 loop - stackA(i) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6); - end loop; - stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0); - end if; - end if; - when State_StoreSP => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_StoreSP2; - - mem_writeEnable <= '1'; - mem_addr <= sp+spOffset; - mem_write <= stackA; - stackA <= stackB; - sp <= incSp; - end if; - - - when State_LoadSP => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_LoadSP2; - - sp <= decSp; - mem_writeEnable <= '1'; - mem_addr <= incSp; - mem_write <= stackB; - end if; - when State_Emulate => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - sp <= decSp; - mem_writeEnable <= '1'; - mem_addr <= incSp; - mem_write <= stackB; - stackA <= (others => DontCareValue); - stackA(maxAddrBitIncIO downto 0) <= pc + 1; - stackB <= stackA; - - -- The emulate address is: - -- 98 7654 3210 - -- 0000 00aa aaa0 0000 - pc <= (others => '0'); - pc(9 downto 5) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(4 downto 0); - state <= State_Fetch; - end if; - when State_Callpcrel => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - stackA <= (others => DontCareValue); - stackA(maxAddrBitIncIO downto 0) <= pc + 1; - - pc <= pc + stackA(maxAddrBitIncIO downto 0); - state <= State_Fetch; - end if; - when State_Call => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - stackA <= (others => DontCareValue); - stackA(maxAddrBitIncIO downto 0) <= pc + 1; - pc <= stackA(maxAddrBitIncIO downto 0); - state <= State_Fetch; - end if; - when State_AddSP => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_AddSP2; - - mem_readEnable <= '1'; - mem_addr <= sp+spOffset; - end if; - when State_PushSP => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - sp <= decSp; - stackA <= (others => '0'); - stackA(maxAddrBitIncIO downto minAddrBit) <= sp; - stackB <= stackA; - mem_writeEnable <= '1'; - mem_addr <= incSp; - mem_write <= stackB; - end if; - when State_PopPC => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= stackA(maxAddrBitIncIO downto 0); - sp <= incSp; - - mem_writeEnable <= '1'; - mem_addr <= incSp; - mem_write <= stackB; - state <= State_Resync; - end if; - when State_PopPCRel => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= stackA(maxAddrBitIncIO downto 0) + pc; - sp <= incSp; - - mem_writeEnable <= '1'; - mem_addr <= incSp; - mem_write <= stackB; - state <= State_Resync; - end if; - when State_Add => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - stackA <= stackA + stackB; - - mem_readEnable <= '1'; - mem_addr <= incIncSp; - sp <= incSp; - state <= State_Popped; - end if; - when State_Sub => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - binaryOpResult <= stackB - stackA; - state <= State_BinaryOpResult; - end if; - when State_Pop => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - mem_addr <= incIncSp; - mem_readEnable <= '1'; - sp <= incSp; - stackA <= stackB; - state <= State_Popped; - end if; - when State_PopDown => - if in_mem_busy='0' then - -- PopDown leaves top of stack unchanged - begin_inst <= '1'; - idim_flag <= '0'; - mem_addr <= incIncSp; - mem_readEnable <= '1'; - sp <= incSp; - state <= State_Popped; - end if; - when State_Or => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - stackA <= stackA or stackB; - mem_readEnable <= '1'; - mem_addr <= incIncSp; - sp <= incSp; - state <= State_Popped; - end if; - when State_And => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - - stackA <= stackA and stackB; - mem_readEnable <= '1'; - mem_addr <= incIncSp; - sp <= incSp; - state <= State_Popped; - end if; - when State_Eq => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (stackA=stackB) then - binaryOpResult(0) <= '1'; - end if; - state <= State_BinaryOpResult; - end if; - when State_Ulessthan => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (stackA - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (stackA<=stackB) then - binaryOpResult(0) <= '1'; - end if; - state <= State_BinaryOpResult; - end if; - when State_Lessthan => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (signed(stackA) - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (signed(stackA)<=signed(stackB)) then - binaryOpResult(0) <= '1'; - end if; - state <= State_BinaryOpResult; - end if; - when State_Load => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_Load2; - - mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); - mem_readEnable <= '1'; - end if; - - when State_Dup => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - sp <= decSp; - stackB <= stackA; - mem_write <= stackB; - mem_addr <= incSp; - mem_writeEnable <= '1'; - end if; - when State_DupStackB => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - sp <= decSp; - stackA <= stackB; - stackB <= stackA; - mem_write <= stackB; - mem_addr <= incSp; - mem_writeEnable <= '1'; - end if; - when State_Store => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); - mem_write <= stackB; - mem_writeEnable <= '1'; - sp <= incIncSp; - state <= State_Resync; - end if; - when State_PopSP => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - mem_write <= stackB; - mem_addr <= incSp; - mem_writeEnable <= '1'; - sp <= stackA(maxAddrBitIncIO downto minAddrBit); - state <= State_Resync; - end if; - when State_Nop => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - when State_Not => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - stackA <= not stackA; - when State_Flip => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - for i in 0 to wordSize-1 loop - stackA(i) <= stackA(wordSize-1-i); - end loop; - when State_AddTop => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - stackA <= stackA + stackB; - when State_Shift => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0); - stackA(0) <= '0'; - when State_Pushspadd => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - stackA <= (others => '0'); - stackA(maxAddrBitIncIO downto minAddrBit) <= stackA(maxAddrBitIncIO-minAddrBit downto 0)+sp; - when State_Neqbranch => - -- branches are almost always taken as they form loops - begin_inst <= '1'; - idim_flag <= '0'; - sp <= incIncSp; - if (stackB/=0) then - pc <= stackA(maxAddrBitIncIO downto 0) + pc; - else - pc <= pc + 1; - end if; - -- need to fetch stack again. - state <= State_Resync; - when State_Mult => - begin_inst <= '1'; - idim_flag <= '0'; - - multA <= stackA; - multB <= stackB; - state <= State_Mult2; - when State_Break => - report "Break instruction encountered" severity failure; - break <= '1'; - - when State_Loadb => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_Loadb2; - - mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); - mem_readEnable <= '1'; - end if; - when State_Storeb => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_Storeb2; - - mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); - mem_readEnable <= '1'; - end if; - - when others => - sp <= (others => DontCareValue); - report "Illegal instruction" severity failure; - break <= '1'; - end case; - - - when State_StoreSP2 => - if in_mem_busy='0' then - mem_addr <= incSp; - mem_readEnable <= '1'; - state <= State_Popped; - end if; - when State_LoadSP2 => - if in_mem_busy='0' then - state <= State_LoadSP3; - mem_readEnable <= '1'; - mem_addr <= sp+spOffset+1; - end if; - when State_LoadSP3 => - if in_mem_busy='0' then - pc <= pc + 1; - state <= State_Execute; - stackB <= stackA; - stackA <= mem_read; - end if; - when State_AddSP2 => - if in_mem_busy='0' then - pc <= pc + 1; - state <= State_Execute; - stackA <= stackA + mem_read; - end if; - when State_Load2 => - if in_mem_busy='0' then - stackA <= mem_read; - pc <= pc + 1; - state <= State_Execute; - end if; - when State_Loadb2 => - if in_mem_busy='0' then - stackA <= (others => '0'); - stackA(7 downto 0) <= mem_read(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8); - pc <= pc + 1; - state <= State_Execute; - end if; - when State_Storeb2 => - if in_mem_busy='0' then - mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); - mem_write <= mem_read; - mem_write(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8) <= stackB(7 downto 0) ; - mem_writeEnable <= '1'; - pc <= pc + 1; - sp <= incIncSp; - state <= State_Resync; - end if; - when State_Fetch => - if in_mem_busy='0' then - mem_addr <= pc(maxAddrBitIncIO downto minAddrBit); - mem_readEnable <= '1'; - state <= State_Decode; - end if; - when State_Mult2 => - state <= State_Mult3; - when State_Mult3 => - state <= State_Mult4; - when State_Mult4 => - state <= State_Mult5; - when State_Mult5 => - if in_mem_busy='0' then - stackA <= multResult3; - mem_readEnable <= '1'; - mem_addr <= incIncSp; - sp <= incSp; - state <= State_Popped; - end if; - when State_BinaryOpResult => - state <= State_BinaryOpResult2; - when State_BinaryOpResult2 => - mem_readEnable <= '1'; - mem_addr <= incIncSp; - sp <= incSp; - stackA <= binaryOpResult2; - state <= State_Popped; - when State_Popped => - if in_mem_busy='0' then - pc <= pc + 1; - stackB <= mem_read; - state <= State_Execute; - end if; - when others => - sp <= (others => DontCareValue); - report "Illegal state" severity failure; - break <= '1'; - end case; - end if; - end process; - - - -end behave; + +-- Company: ZPU4 generic memory interface CPU +-- Engineer: Øyvind Harboe + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use ieee.numeric_std.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + + +-- mem_writeEnable - set to '1' for a single cycle to send off a write request. +-- mem_write is valid only while mem_writeEnable='1'. +-- mem_readEnable - set to '1' for a single cycle to send off a read request. +-- +-- mem_busy - It is illegal to send off a read/write request when mem_busy='1'. +-- Set to '0' when mem_read is valid after a read request. +-- If it goes to '1'(busy), it is on the cycle after mem_read/writeEnable +-- is '1'. +-- mem_addr - address for read/write request +-- mem_read - read data. Valid only on the cycle after mem_busy='0' after +-- mem_readEnable='1' for a single cycle. +-- mem_write - data to write +-- mem_writeMask - set to '1' for those bits that are to be written to memory upon +-- write request +-- break - set to '1' when CPU hits break instruction +-- interrupt - set to '1' until interrupts are cleared by CPU. + + + + +entity zpu_core is + Port ( clk : in std_logic; + areset : in std_logic; + enable : in std_logic; + in_mem_busy : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + out_mem_writeEnable : out std_logic; + out_mem_readEnable : out std_logic; + mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + interrupt : in std_logic; + break : out std_logic); +end zpu_core; + +architecture behave of zpu_core is + +type InsnType is +( +State_AddTop, +State_Dup, +State_DupStackB, +State_Pop, +State_Popdown, +State_Add, +State_Or, +State_And, +State_Store, +State_AddSP, +State_Shift, +State_Nop, +State_Im, +State_LoadSP, +State_StoreSP, +State_Emulate, +State_Load, +State_PushPC, +State_PushSP, +State_PopPC, +State_PopPCRel, +State_Not, +State_Flip, +State_PopSP, +State_Neqbranch, +State_Eq, +State_Loadb, +State_Mult, +State_Lessthan, +State_Lessthanorequal, +State_Ulessthanorequal, +State_Ulessthan, +State_Pushspadd, +State_Call, +State_Callpcrel, +State_Sub, +State_Break, +State_Storeb, +State_InsnFetch +); + +type StateType is +( +State_Load2, +State_Popped, +State_LoadSP2, +State_LoadSP3, +State_AddSP2, +State_Fetch, +State_Execute, +State_Decode, +State_Decode2, +State_Resync, + +State_StoreSP2, +State_Resync2, +State_Resync3, +State_Loadb2, +State_Storeb2, +State_Mult2, +State_Mult3, +State_Mult5, +State_Mult4, +State_BinaryOpResult2, +State_BinaryOpResult, +State_Idle +); + + +signal pc : unsigned(maxAddrBitIncIO downto 0); +signal sp : unsigned(maxAddrBitIncIO downto minAddrBit); +signal incSp : unsigned(maxAddrBitIncIO downto minAddrBit); +signal incIncSp : unsigned(maxAddrBitIncIO downto minAddrBit); +signal decSp : unsigned(maxAddrBitIncIO downto minAddrBit); +signal stackA : unsigned(wordSize-1 downto 0); +signal binaryOpResult : unsigned(wordSize-1 downto 0); +signal binaryOpResult2 : unsigned(wordSize-1 downto 0); +signal multResult2 : unsigned(wordSize-1 downto 0); +signal multResult3 : unsigned(wordSize-1 downto 0); +signal multResult : unsigned(wordSize-1 downto 0); +signal multA : unsigned(wordSize-1 downto 0); +signal multB : unsigned(wordSize-1 downto 0); +signal stackB : unsigned(wordSize-1 downto 0); +signal idim_flag : std_logic; +signal busy : std_logic; +signal mem_writeEnable : std_logic; +signal mem_readEnable : std_logic; +signal mem_addr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal mem_delayAddr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal mem_delayReadEnable : std_logic; + +signal decodeWord : std_logic_vector(wordSize-1 downto 0); + + +signal state : StateType; +signal insn : InsnType; +type InsnArray is array(0 to wordBytes-1) of InsnType; +signal decodedOpcode : InsnArray; + +type OpcodeArray is array(0 to wordBytes-1) of std_logic_vector(7 downto 0); + +signal opcode : OpcodeArray; + + + + +signal begin_inst : std_logic; +signal trace_opcode : std_logic_vector(7 downto 0); +signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); +signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); +signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); + +-- state machine. + +begin + + + traceFileGenerate: + if Generate_Trace generate + trace_file: trace port map ( + clk => clk, + begin_inst => begin_inst, + pc => trace_pc, + opcode => trace_opcode, + sp => trace_sp, + memA => trace_topOfStack, + memB => trace_topOfStackB, + busy => busy, + intsp => (others => 'U') + ); + end generate; + + + -- the memory subsystem will tell us one cycle later whether or + -- not it is busy + out_mem_writeEnable <= mem_writeEnable; + out_mem_readEnable <= mem_readEnable; + out_mem_addr(maxAddrBitIncIO downto minAddrBit) <= mem_addr; + out_mem_addr(minAddrBit-1 downto 0) <= (others => '0'); + + incSp <= sp + 1; + incIncSp <= sp + 2; + decSp <= sp - 1; + + + opcodeControl: + process(clk, areset) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + variable spOffset : unsigned(4 downto 0); + variable tSpOffset : unsigned(4 downto 0); + variable nextPC : unsigned(maxAddrBitIncIO downto 0); + variable tNextState : InsnType; + variable tDecodedOpcode : InsnArray; + variable tMultResult : unsigned(wordSize*2-1 downto 0); + begin + if areset = '1' then + state <= State_Idle; + break <= '0'; + sp <= unsigned(spStart(maxAddrBitIncIO downto minAddrBit)); + + pc <= (others => '0'); + idim_flag <= '0'; + begin_inst <= '0'; + mem_writeEnable <= '0'; + mem_readEnable <= '0'; + multA <= (others => '0'); + multB <= (others => '0'); + mem_writeMask <= (others => '1'); + elsif (clk'event and clk = '1') then + -- we must multiply unconditionally to get pipelined multiplication + tMultResult := multA * multB; + multResult3 <= multResult2; + multResult2 <= multResult; + multResult <= tMultResult(wordSize-1 downto 0); + + + binaryOpResult2 <= binaryOpResult; -- pipeline a bit. + + + multA <= (others => DontCareValue); + multB <= (others => DontCareValue); + + + mem_addr <= (others => DontCareValue); + mem_readEnable <='0'; + mem_writeEnable <='0'; + mem_write <= (others => DontCareValue); + + if (mem_writeEnable = '1') and (mem_readEnable = '1') then + report "read/write collision" severity failure; + end if; + + + + + spOffset(4):=not opcode(to_integer(pc(byteBits-1 downto 0)))(4); + spOffset(3 downto 0):=unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(3 downto 0)); + nextPC := pc + 1; + + -- prepare trace snapshot + trace_opcode <= opcode(to_integer(pc(byteBits-1 downto 0))); + trace_pc <= std_logic_vector(pc); + trace_sp <= std_logic_vector(sp); + trace_topOfStack <= std_logic_vector(stackA); + trace_topOfStackB <= std_logic_vector(stackB); + begin_inst <= '0'; + + + case state is + when State_Idle => + if enable='1' then + state <= State_Resync; + end if; + -- Initial state of ZPU, fetch top of stack + first instruction + when State_Resync => + if in_mem_busy='0' then + mem_addr <= std_logic_vector(sp); + mem_readEnable <= '1'; + state <= State_Resync2; + end if; + when State_Resync2 => + if in_mem_busy='0' then + stackA <= unsigned(mem_read); + mem_addr <= std_logic_vector(incSp); + mem_readEnable <= '1'; + state <= State_Resync3; + end if; + when State_Resync3 => + if in_mem_busy='0' then + stackB <= unsigned(mem_read); + mem_addr <= std_logic_vector(pc(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + state <= State_Decode; + end if; + when State_Decode => + if in_mem_busy='0' then + decodeWord <= mem_read; + state <= State_Decode2; + end if; + when State_Decode2 => + -- decode 4 instructions in parallel + for i in 0 to wordBytes-1 loop + tOpcode := decodeWord((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8); + + tSpOffset(4):=not tOpcode(4); + tSpOffset(3 downto 0):=unsigned(tOpcode(3 downto 0)); + + opcode(i) <= tOpcode; + if (tOpcode(7 downto 7)=OpCode_Im) then + tNextState:=State_Im; + elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then + if tSpOffset = 0 then + tNextState := State_Pop; + elsif tSpOffset=1 then + tNextState := State_PopDown; + else + tNextState :=State_StoreSP; + end if; + elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then + if tSpOffset = 0 then + tNextState :=State_Dup; + elsif tSpOffset = 1 then + tNextState :=State_DupStackB; + else + tNextState :=State_LoadSP; + end if; + elsif (tOpcode(7 downto 5)=OpCode_Emulate) then + tNextState :=State_Emulate; + if tOpcode(5 downto 0)=OpCode_Neqbranch then + tNextState :=State_Neqbranch; + elsif tOpcode(5 downto 0)=OpCode_Eq then + tNextState :=State_Eq; + elsif tOpcode(5 downto 0)=OpCode_Lessthan then + tNextState :=State_Lessthan; + elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then + --tNextState :=State_Lessthanorequal; + elsif tOpcode(5 downto 0)=OpCode_Ulessthan then + tNextState :=State_Ulessthan; + elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then + --tNextState :=State_Ulessthanorequal; + elsif tOpcode(5 downto 0)=OpCode_Loadb then + tNextState :=State_Loadb; + elsif tOpcode(5 downto 0)=OpCode_Mult then + tNextState :=State_Mult; + elsif tOpcode(5 downto 0)=OpCode_Storeb then + tNextState :=State_Storeb; + elsif tOpcode(5 downto 0)=OpCode_Pushspadd then + tNextState :=State_Pushspadd; + elsif tOpcode(5 downto 0)=OpCode_Callpcrel then + tNextState :=State_Callpcrel; + elsif tOpcode(5 downto 0)=OpCode_Call then + --tNextState :=State_Call; + elsif tOpcode(5 downto 0)=OpCode_Sub then + tNextState :=State_Sub; + elsif tOpcode(5 downto 0)=OpCode_PopPCRel then + --tNextState :=State_PopPCRel; + end if; + elsif (tOpcode(7 downto 4)=OpCode_AddSP) then + if tSpOffset = 0 then + tNextState := State_Shift; + elsif tSpOffset = 1 then + tNextState := State_AddTop; + else + tNextState :=State_AddSP; + end if; + else + case tOpcode(3 downto 0) is + when OpCode_Nop => + tNextState :=State_Nop; + when OpCode_PushSP => + tNextState :=State_PushSP; + when OpCode_PopPC => + tNextState :=State_PopPC; + when OpCode_Add => + tNextState :=State_Add; + when OpCode_Or => + tNextState :=State_Or; + when OpCode_And => + tNextState :=State_And; + when OpCode_Load => + tNextState :=State_Load; + when OpCode_Not => + tNextState :=State_Not; + when OpCode_Flip => + tNextState :=State_Flip; + when OpCode_Store => + tNextState :=State_Store; + when OpCode_PopSP => + tNextState :=State_PopSP; + when others => + tNextState := State_Break; + + end case; + end if; + tDecodedOpcode(i) := tNextState; + + end loop; + + insn <= tDecodedOpcode(to_integer(pc(byteBits-1 downto 0))); + + -- once we wrap, we need to fetch + tDecodedOpcode(0) := State_InsnFetch; + + decodedOpcode <= tDecodedOpcode; + state <= State_Execute; + + + + -- Each instruction must: + -- + -- 1. set idim_flag + -- 2. increase pc if applicable + -- 3. set next state if appliable + -- 4. do it's operation + + when State_Execute => + insn <= decodedOpcode(to_integer(nextPC(byteBits-1 downto 0))); + + case insn is + when State_InsnFetch => + state <= State_Fetch; + when State_Im => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '1'; + pc <= pc + 1; + + if idim_flag='1' then + stackA(wordSize-1 downto 7) <= stackA(wordSize-8 downto 0); + stackA(6 downto 0) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(6 downto 0)); + else + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + stackB <= stackA; + sp <= decSp; + for i in wordSize-1 downto 7 loop + stackA(i) <= opcode(to_integer(pc(byteBits-1 downto 0)))(6); + end loop; + stackA(6 downto 0) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(6 downto 0)); + end if; + end if; + when State_StoreSP => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_StoreSP2; + + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(sp+spOffset); + mem_write <= std_logic_vector(stackA); + stackA <= stackB; + sp <= incSp; + end if; + + + when State_LoadSP => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_LoadSP2; + + sp <= decSp; + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + end if; + when State_Emulate => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + sp <= decSp; + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + stackB <= stackA; + + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= (others => '0'); + pc(9 downto 5) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(4 downto 0)); + state <= State_Fetch; + end if; + when State_Callpcrel => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + + pc <= pc + stackA(maxAddrBitIncIO downto 0); + state <= State_Fetch; + end if; + when State_Call => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + pc <= stackA(maxAddrBitIncIO downto 0); + state <= State_Fetch; + end if; + when State_AddSP => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_AddSP2; + + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(sp+spOffset); + end if; + when State_PushSP => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackA <= (others => '0'); + stackA(maxAddrBitIncIO downto minAddrBit) <= sp; + stackB <= stackA; + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + end if; + when State_PopPC => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= stackA(maxAddrBitIncIO downto 0); + sp <= incSp; + + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + state <= State_Resync; + end if; + when State_PopPCRel => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= stackA(maxAddrBitIncIO downto 0) + pc; + sp <= incSp; + + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + state <= State_Resync; + end if; + when State_Add => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= stackA + stackB; + + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + state <= State_Popped; + end if; + when State_Sub => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + binaryOpResult <= stackB - stackA; + state <= State_BinaryOpResult; + end if; + when State_Pop => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + mem_addr <= std_logic_vector(incIncSp); + mem_readEnable <= '1'; + sp <= incSp; + stackA <= stackB; + state <= State_Popped; + end if; + when State_PopDown => + if in_mem_busy='0' then + -- PopDown leaves top of stack unchanged + begin_inst <= '1'; + idim_flag <= '0'; + mem_addr <= std_logic_vector(incIncSp); + mem_readEnable <= '1'; + sp <= incSp; + state <= State_Popped; + end if; + when State_Or => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= stackA or stackB; + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + state <= State_Popped; + end if; + when State_And => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + stackA <= stackA and stackB; + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + state <= State_Popped; + end if; + when State_Eq => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA=stackB) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + end if; + when State_Ulessthan => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA<=stackB) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + end if; + when State_Lessthan => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (signed(stackA) + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (signed(stackA)<=signed(stackB)) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + end if; + when State_Load => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Load2; + + mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + end if; + + when State_Dup => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackB <= stackA; + mem_write <= std_logic_vector(stackB); + mem_addr <= std_logic_vector(incSp); + mem_writeEnable <= '1'; + end if; + when State_DupStackB => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackA <= stackB; + stackB <= stackA; + mem_write <= std_logic_vector(stackB); + mem_addr <= std_logic_vector(incSp); + mem_writeEnable <= '1'; + end if; + when State_Store => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); + mem_write <= std_logic_vector(stackB); + mem_writeEnable <= '1'; + sp <= incIncSp; + state <= State_Resync; + end if; + when State_PopSP => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + mem_write <= std_logic_vector(stackB); + mem_addr <= std_logic_vector(incSp); + mem_writeEnable <= '1'; + sp <= stackA(maxAddrBitIncIO downto minAddrBit); + state <= State_Resync; + end if; + when State_Nop => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + when State_Not => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= not stackA; + when State_Flip => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + for i in 0 to wordSize-1 loop + stackA(i) <= stackA(wordSize-1-i); + end loop; + when State_AddTop => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= stackA + stackB; + when State_Shift => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0); + stackA(0) <= '0'; + when State_Pushspadd => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= (others => '0'); + stackA(maxAddrBitIncIO downto minAddrBit) <= stackA(maxAddrBitIncIO-minAddrBit downto 0)+sp; + when State_Neqbranch => + -- branches are almost always taken as they form loops + begin_inst <= '1'; + idim_flag <= '0'; + sp <= incIncSp; + if (stackB/=0) then + pc <= stackA(maxAddrBitIncIO downto 0) + pc; + else + pc <= pc + 1; + end if; + -- need to fetch stack again. + state <= State_Resync; + when State_Mult => + begin_inst <= '1'; + idim_flag <= '0'; + + multA <= stackA; + multB <= stackB; + state <= State_Mult2; + when State_Break => + report "Break instruction encountered" severity failure; + break <= '1'; + + when State_Loadb => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Loadb2; + + mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + end if; + when State_Storeb => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Storeb2; + + mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + end if; + + when others => + sp <= (others => DontCareValue); + report "Illegal instruction" severity failure; + break <= '1'; + end case; + + + when State_StoreSP2 => + if in_mem_busy='0' then + mem_addr <= std_logic_vector(incSp); + mem_readEnable <= '1'; + state <= State_Popped; + end if; + when State_LoadSP2 => + if in_mem_busy='0' then + state <= State_LoadSP3; + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(sp+spOffset+1); + end if; + when State_LoadSP3 => + if in_mem_busy='0' then + pc <= pc + 1; + state <= State_Execute; + stackB <= stackA; + stackA <= unsigned(mem_read); + end if; + when State_AddSP2 => + if in_mem_busy='0' then + pc <= pc + 1; + state <= State_Execute; + stackA <= stackA + unsigned(mem_read); + end if; + when State_Load2 => + if in_mem_busy='0' then + stackA <= unsigned(mem_read); + pc <= pc + 1; + state <= State_Execute; + end if; + when State_Loadb2 => + if in_mem_busy='0' then + stackA <= (others => '0'); + stackA(7 downto 0) <= unsigned(mem_read(((wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8)); + pc <= pc + 1; + state <= State_Execute; + end if; + when State_Storeb2 => + if in_mem_busy='0' then + mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); + mem_write <= mem_read; + mem_write(((wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8) <= std_logic_vector(stackB(7 downto 0)); + mem_writeEnable <= '1'; + pc <= pc + 1; + sp <= incIncSp; + state <= State_Resync; + end if; + when State_Fetch => + if in_mem_busy='0' then + mem_addr <= std_logic_vector(pc(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + state <= State_Decode; + end if; + when State_Mult2 => + state <= State_Mult3; + when State_Mult3 => + state <= State_Mult4; + when State_Mult4 => + state <= State_Mult5; + when State_Mult5 => + if in_mem_busy='0' then + stackA <= multResult3; + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + state <= State_Popped; + end if; + when State_BinaryOpResult => + state <= State_BinaryOpResult2; + when State_BinaryOpResult2 => + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + stackA <= binaryOpResult2; + state <= State_Popped; + when State_Popped => + if in_mem_busy='0' then + pc <= pc + 1; + stackB <= unsigned(mem_read); + state <= State_Execute; + end if; + when others => + sp <= (others => DontCareValue); + report "Illegal state" severity failure; + break <= '1'; + end case; + end if; + end process; + + + +end behave; diff --git a/zpu/hdl/zpu4/src/zpu_core_small.vhd b/zpu/hdl/zpu4/src/zpu_core_small.vhd index 4d73f88..0d734d2 100644 --- a/zpu/hdl/zpu4/src/zpu_core_small.vhd +++ b/zpu/hdl/zpu4/src/zpu_core_small.vhd @@ -1,433 +1,447 @@ --- Company: ZPU3 --- Engineer: Øyvind Harboe - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - - -entity zpu_core is - Port ( clk : in std_logic; - areset : in std_logic; - enable : in std_logic; - in_mem_busy : in std_logic; - mem_read : in std_logic_vector(wordSize-1 downto 0); - mem_write : out std_logic_vector(wordSize-1 downto 0); - out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); - out_mem_writeEnable : out std_logic; - out_mem_readEnable : out std_logic; - mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); - interrupt : in std_logic; - break : out std_logic); -end zpu_core; - -architecture behave of zpu_core is - -signal readIO : std_logic; - - - -signal memAWriteEnable : std_logic; -signal memAAddr : std_logic_vector(maxAddrBit downto minAddrBit); -signal memAWrite : std_logic_vector(wordSize-1 downto 0); -signal memARead : std_logic_vector(wordSize-1 downto 0); -signal memBWriteEnable : std_logic; -signal memBAddr : std_logic_vector(maxAddrBit downto minAddrBit); -signal memBWrite : std_logic_vector(wordSize-1 downto 0); -signal memBRead : std_logic_vector(wordSize-1 downto 0); - - - -signal pc : std_logic_vector(maxAddrBit downto 0); -signal sp : std_logic_vector(maxAddrBit downto minAddrBit); - -signal idim_flag : std_logic; - ---signal storeToStack : std_logic; ---signal fetchNextInstruction : std_logic; ---signal extraCycle : std_logic; -signal busy : std_logic; ---signal fetching : std_logic; - -signal begin_inst : std_logic; - - - -signal trace_opcode : std_logic_vector(7 downto 0); -signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); -signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); -signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); - --- state machine. -type State_Type is -( -State_Fetch, -State_WriteIODone, -State_Execute, -State_StoreToStack, -State_Add, -State_Or, -State_And, -State_Store, -State_ReadIO, -State_WriteIO, -State_Load, -State_FetchNext, -State_AddSP, -State_ReadIODone, -State_Decode, -State_Resync -); - -type DecodedOpcodeType is -( -Decoded_Nop, -Decoded_Im, -Decoded_ImShift, -Decoded_LoadSP, -Decoded_StoreSP , -Decoded_AddSP, -Decoded_Emulate, -Decoded_Break, -Decoded_PushSP, -Decoded_PopPC, -Decoded_Add, -Decoded_Or, -Decoded_And, -Decoded_Load, -Decoded_Not, -Decoded_Flip, -Decoded_Store, -Decoded_PopSP -); - - - -signal sampledOpcode : std_logic_vector(OpCode_Size-1 downto 0); -signal opcode : std_logic_vector(OpCode_Size-1 downto 0); - -signal decodedOpcode : DecodedOpcodeType; -signal sampledDecodedOpcode : DecodedOpcodeType; - - -signal state : State_Type; - -begin - traceFileGenerate: - if Generate_Trace generate - trace_file: trace port map ( - clk => clk, - begin_inst => begin_inst, - pc => trace_pc, - opcode => trace_opcode, - sp => trace_sp, - memA => trace_topOfStack, - memB => trace_topOfStackB, - busy => busy, - intsp => (others => 'U') - ); - end generate; - - - memory: dualport_ram port map ( - clk => clk, - memAWriteEnable => memAWriteEnable, - memAAddr => memAAddr(maxAddrBitBRAM downto minAddrBit), - memAWrite => memAWrite, - memARead => memARead, - memBWriteEnable => memBWriteEnable, - memBAddr => memBAddr(maxAddrBitBRAM downto minAddrBit), - memBWrite => memBWrite, - memBRead => memBRead - ); - - - - decodeControl: - process(memBRead, pc) - variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); - begin - tOpcode := memBRead((wordBytes-1-conv_integer(pc(minAddrBit-1 downto 0))+1)*8-1 downto (wordBytes-1-conv_integer(pc(minAddrBit-1 downto 0)))*8); - - sampledOpcode <= tOpcode; - - if (tOpcode(7 downto 7)=OpCode_Im) then - sampledDecodedOpcode<=Decoded_Im; - elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then - sampledDecodedOpcode<=Decoded_StoreSP; - elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then - sampledDecodedOpcode<=Decoded_LoadSP; - elsif (tOpcode(7 downto 5)=OpCode_Emulate) then - sampledDecodedOpcode<=Decoded_Emulate; - elsif (tOpcode(7 downto 4)=OpCode_AddSP) then - sampledDecodedOpcode<=Decoded_AddSP; - else - case tOpcode(3 downto 0) is - when OpCode_Break => - sampledDecodedOpcode<=Decoded_Break; - when OpCode_PushSP => - sampledDecodedOpcode<=Decoded_PushSP; - when OpCode_PopPC => - sampledDecodedOpcode<=Decoded_PopPC; - when OpCode_Add => - sampledDecodedOpcode<=Decoded_Add; - when OpCode_Or => - sampledDecodedOpcode<=Decoded_Or; - when OpCode_And => - sampledDecodedOpcode<=Decoded_And; - when OpCode_Load => - sampledDecodedOpcode<=Decoded_Load; - when OpCode_Not => - sampledDecodedOpcode<=Decoded_Not; - when OpCode_Flip => - sampledDecodedOpcode<=Decoded_Flip; - when OpCode_Store => - sampledDecodedOpcode<=Decoded_Store; - when OpCode_PopSP => - sampledDecodedOpcode<=Decoded_PopSP; - when others => - sampledDecodedOpcode<=Decoded_Nop; - end case; - end if; - end process; - - - opcodeControl: - process(clk, areset) - variable spOffset : std_logic_vector(4 downto 0); - begin - if areset = '1' then - state <= State_Resync; - break <= '0'; - sp <= spStart(maxAddrBit downto minAddrBit); - pc <= (others => '0'); - idim_flag <= '0'; - begin_inst <= '0'; - memAAddr <= (others => '0'); - memBAddr <= (others => '0'); - memAWriteEnable <= '0'; - memBWriteEnable <= '0'; - out_mem_writeEnable <= '0'; - out_mem_readEnable <= '0'; - memAWrite <= (others => '0'); - memBWrite <= (others => '0'); - mem_writeMask <= (others => '1'); - elsif (clk'event and clk = '1') then - memAWriteEnable <= '0'; - memBWriteEnable <= '0'; - -- This saves ca. 100 LUT's, by explicitly declaring that the - -- memAWrite can be left at whatever value if memAWriteEnable is - -- not set. - memAWrite <= (others => DontCareValue); - memBWrite <= (others => DontCareValue); --- out_mem_addr <= (others => DontCareValue); --- mem_write <= (others => DontCareValue); - spOffset := (others => DontCareValue); - memAAddr <= (others => DontCareValue); - memBAddr <= (others => DontCareValue); - - out_mem_writeEnable <= '0'; - out_mem_readEnable <= '0'; - begin_inst <= '0'; - out_mem_addr <= memARead(maxAddrBitIncIO downto 0); - mem_write <= memBRead; - - decodedOpcode <= sampledDecodedOpcode; - opcode <= sampledOpcode; - - case state is - when State_Execute => - state <= State_Fetch; - -- at this point: - -- memBRead contains opcode word - -- memARead contains top of stack - pc <= pc + 1; - - -- trace - begin_inst <= '1'; - trace_pc <= (others => '0'); - trace_pc(maxAddrBit downto 0) <= pc; - trace_opcode <= opcode; - trace_sp <= (others => '0'); - trace_sp(maxAddrBit downto minAddrBit) <= sp; - trace_topOfStack <= memARead; - trace_topOfStackB <= memBRead; - - -- during the next cycle we'll be reading the next opcode - spOffset(4):=not opcode(4); - spOffset(3 downto 0):=opcode(3 downto 0); - - idim_flag <= '0'; - case decodedOpcode is - when Decoded_Im => - idim_flag <= '1'; - memAWriteEnable <= '1'; - if (idim_flag='0') then - sp <= sp - 1; - memAAddr <= sp-1; - for i in wordSize-1 downto 7 loop - memAWrite(i) <= opcode(6); - end loop; - memAWrite(6 downto 0) <= opcode(6 downto 0); - else - memAAddr <= sp; - memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0); - memAWrite(6 downto 0) <= opcode(6 downto 0); - end if; - when Decoded_StoreSP => - memBWriteEnable <= '1'; - memBAddr <= sp+spOffset; - memBWrite <= memARead; - sp <= sp + 1; - state <= State_Resync; - when Decoded_LoadSP => - sp <= sp - 1; - memAAddr <= sp+spOffset; - when Decoded_Emulate => - sp <= sp - 1; - memAWriteEnable <= '1'; - memAAddr <= sp - 1; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto 0) <= pc + 1; - -- The emulate address is: - -- 98 7654 3210 - -- 0000 00aa aaa0 0000 - pc <= (others => '0'); - pc(9 downto 5) <= opcode(4 downto 0); - when Decoded_AddSP => - memAAddr <= sp; - memBAddr <= sp+spOffset; - state <= State_AddSP; - when Decoded_Break => - report "Break instruction encountered" severity failure; - break <= '1'; - when Decoded_PushSP => - memAWriteEnable <= '1'; - memAAddr <= sp - 1; - sp <= sp - 1; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto minAddrBit) <= sp; - when Decoded_PopPC => - pc <= memARead(maxAddrBit downto 0); - sp <= sp + 1; - state <= State_Resync; - when Decoded_Add => - sp <= sp + 1; - state <= State_Add; - when Decoded_Or => - sp <= sp + 1; - state <= State_Or; - when Decoded_And => - sp <= sp + 1; - state <= State_And; - when Decoded_Load => - if (memARead(ioBit)='1') then - out_mem_addr <= memARead(maxAddrBitIncIO downto 0); - out_mem_readEnable <= '1'; - state <= State_ReadIO; - else - memAAddr <= memARead(maxAddrBit downto minAddrBit); - end if; - when Decoded_Not => - memAAddr <= sp(maxAddrBit downto minAddrBit); - memAWriteEnable <= '1'; - memAWrite <= not memARead; - when Decoded_Flip => - memAAddr <= sp(maxAddrBit downto minAddrBit); - memAWriteEnable <= '1'; - for i in 0 to wordSize-1 loop - memAWrite(i) <= memARead(wordSize-1-i); - end loop; - when Decoded_Store => - memBAddr <= sp + 1; - sp <= sp + 1; - if (memARead(ioBit)='1') then - state <= State_WriteIO; - else - state <= State_Store; - end if; - when Decoded_PopSP => - sp <= memARead(maxAddrBit downto minAddrBit); - state <= State_Resync; - when Decoded_Nop => - memAAddr <= sp; - when others => - null; - end case; - when State_ReadIO => - if (in_mem_busy = '0') then - state <= State_Fetch; - memAWriteEnable <= '1'; - memAWrite <= mem_read; - end if; - when State_WriteIO => - sp <= sp + 1; - out_mem_writeEnable <= '1'; - out_mem_addr <= memARead(maxAddrBitIncIO downto 0); - mem_write <= memBRead; - state <= State_WriteIODone; - when State_WriteIODone => - if (in_mem_busy = '0') then - state <= State_Resync; - end if; - when State_Fetch => - -- We need to resync. During the *next* cycle - -- we'll fetch the opcode @ pc and thus it will - -- be available for State_Execute the cycle after - -- next - memBAddr <= pc(maxAddrBit downto minAddrBit); - state <= State_FetchNext; - when State_FetchNext => - -- at this point memARead contains the value that is either - -- from the top of stack or should be copied to the top of the stack - memAWriteEnable <= '1'; - memAWrite <= memARead; - memAAddr <= sp; - memBAddr <= sp + 1; - state <= State_Decode; - when State_Decode => - -- during the State_Execute cycle we'll be fetching SP+1 - memAAddr <= sp; - memBAddr <= sp + 1; - state <= State_Execute; - when State_Store => - sp <= sp + 1; - memAWriteEnable <= '1'; - memAAddr <= memARead(maxAddrBit downto minAddrBit); - memAWrite <= memBRead; - state <= State_Resync; - when State_AddSP => - state <= State_Add; - when State_Add => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead + memBRead; - state <= State_Fetch; - when State_Or => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead or memBRead; - state <= State_Fetch; - when State_Resync => - memAAddr <= sp; - state <= State_Fetch; - when State_And => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead and memBRead; - state <= State_Fetch; - when others => - null; - end case; - - end if; - end process; - - - -end behave; +-- Company: ZPU3 +-- Engineer: Øyvind Harboe + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use ieee.numeric_std.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + + +entity zpu_core is + Port ( clk : in std_logic; + areset : in std_logic; + enable : in std_logic; + in_mem_busy : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + out_mem_writeEnable : out std_logic; + out_mem_readEnable : out std_logic; + mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + interrupt : in std_logic; + break : out std_logic); +end zpu_core; + +architecture behave of zpu_core is + +signal readIO : std_logic; + + + +signal memAWriteEnable : std_logic; +signal memAAddr : unsigned(maxAddrBit downto minAddrBit); +signal memAWrite : unsigned(wordSize-1 downto 0); +signal memARead : unsigned(wordSize-1 downto 0); +signal memBWriteEnable : std_logic; +signal memBAddr : unsigned(maxAddrBit downto minAddrBit); +signal memBWrite : unsigned(wordSize-1 downto 0); +signal memBRead : unsigned(wordSize-1 downto 0); + + + +signal pc : unsigned(maxAddrBit downto 0); +signal sp : unsigned(maxAddrBit downto minAddrBit); + +signal idim_flag : std_logic; + +--signal storeToStack : std_logic; +--signal fetchNextInstruction : std_logic; +--signal extraCycle : std_logic; +signal busy : std_logic; +--signal fetching : std_logic; + +signal begin_inst : std_logic; + + + +signal trace_opcode : std_logic_vector(7 downto 0); +signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); +signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); +signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); + +-- state machine. +type State_Type is +( +State_Fetch, +State_WriteIODone, +State_Execute, +State_StoreToStack, +State_Add, +State_Or, +State_And, +State_Store, +State_ReadIO, +State_WriteIO, +State_Load, +State_FetchNext, +State_AddSP, +State_ReadIODone, +State_Decode, +State_Resync +); + +type DecodedOpcodeType is +( +Decoded_Nop, +Decoded_Im, +Decoded_ImShift, +Decoded_LoadSP, +Decoded_StoreSP , +Decoded_AddSP, +Decoded_Emulate, +Decoded_Break, +Decoded_PushSP, +Decoded_PopPC, +Decoded_Add, +Decoded_Or, +Decoded_And, +Decoded_Load, +Decoded_Not, +Decoded_Flip, +Decoded_Store, +Decoded_PopSP +); + + + +signal sampledOpcode : std_logic_vector(OpCode_Size-1 downto 0); +signal opcode : std_logic_vector(OpCode_Size-1 downto 0); + +signal decodedOpcode : DecodedOpcodeType; +signal sampledDecodedOpcode : DecodedOpcodeType; + + +signal state : State_Type; + +subtype AddrBitBRAM_range is natural range maxAddrBitBRAM downto minAddrBit; +signal memAAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); +signal memAWrite_stdlogic : std_logic_vector(memAWrite'range); +signal memARead_stdlogic : std_logic_vector(memARead'range); +signal memBAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); +signal memBWrite_stdlogic : std_logic_vector(memBWrite'range); +signal memBRead_stdlogic : std_logic_vector(memBRead'range); + +begin + traceFileGenerate: + if Generate_Trace generate + trace_file: trace port map ( + clk => clk, + begin_inst => begin_inst, + pc => trace_pc, + opcode => trace_opcode, + sp => trace_sp, + memA => trace_topOfStack, + memB => trace_topOfStackB, + busy => busy, + intsp => (others => 'U') + ); + end generate; + + + memAAddr_stdlogic <= std_logic_vector(memAAddr(AddrBitBRAM_range)); + memAWrite_stdlogic <= std_logic_vector(memAWrite); + memBAddr_stdlogic <= std_logic_vector(memBAddr(AddrBitBRAM_range)); + memBWrite_stdlogic <= std_logic_vector(memBWrite); + memory: dualport_ram port map ( + clk => clk, + memAWriteEnable => memAWriteEnable, + memAAddr => memAAddr_stdlogic, + memAWrite => memAWrite_stdlogic, + memARead => memARead_stdlogic, + memBWriteEnable => memBWriteEnable, + memBAddr => memBAddr_stdlogic, + memBWrite => memBWrite_stdlogic, + memBRead => memBRead_stdlogic + ); + memARead <= unsigned(memARead_stdlogic); + memBRead <= unsigned(memBRead_stdlogic); + + + + decodeControl: + process(memBRead, pc) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + begin + tOpcode := std_logic_vector(memBRead((wordBytes-1-to_integer(pc(minAddrBit-1 downto 0))+1)*8-1 downto (wordBytes-1-to_integer(pc(minAddrBit-1 downto 0)))*8)); + + sampledOpcode <= tOpcode; + + if (tOpcode(7 downto 7)=OpCode_Im) then + sampledDecodedOpcode<=Decoded_Im; + elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then + sampledDecodedOpcode<=Decoded_StoreSP; + elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then + sampledDecodedOpcode<=Decoded_LoadSP; + elsif (tOpcode(7 downto 5)=OpCode_Emulate) then + sampledDecodedOpcode<=Decoded_Emulate; + elsif (tOpcode(7 downto 4)=OpCode_AddSP) then + sampledDecodedOpcode<=Decoded_AddSP; + else + case tOpcode(3 downto 0) is + when OpCode_Break => + sampledDecodedOpcode<=Decoded_Break; + when OpCode_PushSP => + sampledDecodedOpcode<=Decoded_PushSP; + when OpCode_PopPC => + sampledDecodedOpcode<=Decoded_PopPC; + when OpCode_Add => + sampledDecodedOpcode<=Decoded_Add; + when OpCode_Or => + sampledDecodedOpcode<=Decoded_Or; + when OpCode_And => + sampledDecodedOpcode<=Decoded_And; + when OpCode_Load => + sampledDecodedOpcode<=Decoded_Load; + when OpCode_Not => + sampledDecodedOpcode<=Decoded_Not; + when OpCode_Flip => + sampledDecodedOpcode<=Decoded_Flip; + when OpCode_Store => + sampledDecodedOpcode<=Decoded_Store; + when OpCode_PopSP => + sampledDecodedOpcode<=Decoded_PopSP; + when others => + sampledDecodedOpcode<=Decoded_Nop; + end case; + end if; + end process; + + + opcodeControl: + process(clk, areset) + variable spOffset : unsigned(4 downto 0); + begin + if areset = '1' then + state <= State_Resync; + break <= '0'; + sp <= unsigned(spStart(maxAddrBit downto minAddrBit)); + pc <= (others => '0'); + idim_flag <= '0'; + begin_inst <= '0'; + memAAddr <= (others => '0'); + memBAddr <= (others => '0'); + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + out_mem_writeEnable <= '0'; + out_mem_readEnable <= '0'; + memAWrite <= (others => '0'); + memBWrite <= (others => '0'); + mem_writeMask <= (others => '1'); + elsif (clk'event and clk = '1') then + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + -- This saves ca. 100 LUT's, by explicitly declaring that the + -- memAWrite can be left at whatever value if memAWriteEnable is + -- not set. + memAWrite <= (others => DontCareValue); + memBWrite <= (others => DontCareValue); +-- out_mem_addr <= (others => DontCareValue); +-- mem_write <= (others => DontCareValue); + spOffset := (others => DontCareValue); + memAAddr <= (others => DontCareValue); + memBAddr <= (others => DontCareValue); + + out_mem_writeEnable <= '0'; + out_mem_readEnable <= '0'; + begin_inst <= '0'; + out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); + mem_write <= std_logic_vector(memBRead); + + decodedOpcode <= sampledDecodedOpcode; + opcode <= sampledOpcode; + + case state is + when State_Execute => + state <= State_Fetch; + -- at this point: + -- memBRead contains opcode word + -- memARead contains top of stack + pc <= pc + 1; + + -- trace + begin_inst <= '1'; + trace_pc <= (others => '0'); + trace_pc(maxAddrBit downto 0) <= std_logic_vector(pc); + trace_opcode <= opcode; + trace_sp <= (others => '0'); + trace_sp(maxAddrBit downto minAddrBit) <= std_logic_vector(sp); + trace_topOfStack <= std_logic_vector(memARead); + trace_topOfStackB <= std_logic_vector(memBRead); + + -- during the next cycle we'll be reading the next opcode + spOffset(4):=not opcode(4); + spOffset(3 downto 0) := unsigned(opcode(3 downto 0)); + + idim_flag <= '0'; + case decodedOpcode is + when Decoded_Im => + idim_flag <= '1'; + memAWriteEnable <= '1'; + if (idim_flag='0') then + sp <= sp - 1; + memAAddr <= sp-1; + for i in wordSize-1 downto 7 loop + memAWrite(i) <= opcode(6); + end loop; + memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); + else + memAAddr <= sp; + memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0); + memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); + end if; + when Decoded_StoreSP => + memBWriteEnable <= '1'; + memBAddr <= sp+spOffset; + memBWrite <= memARead; + sp <= sp + 1; + state <= State_Resync; + when Decoded_LoadSP => + sp <= sp - 1; + memAAddr <= sp+spOffset; + when Decoded_Emulate => + sp <= sp - 1; + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto 0) <= pc + 1; + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= (others => '0'); + pc(9 downto 5) <= unsigned(opcode(4 downto 0)); + when Decoded_AddSP => + memAAddr <= sp; + memBAddr <= sp+spOffset; + state <= State_AddSP; + when Decoded_Break => + report "Break instruction encountered" severity failure; + break <= '1'; + when Decoded_PushSP => + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + sp <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto minAddrBit) <= sp; + when Decoded_PopPC => + pc <= memARead(maxAddrBit downto 0); + sp <= sp + 1; + state <= State_Resync; + when Decoded_Add => + sp <= sp + 1; + state <= State_Add; + when Decoded_Or => + sp <= sp + 1; + state <= State_Or; + when Decoded_And => + sp <= sp + 1; + state <= State_And; + when Decoded_Load => + if (memARead(ioBit)='1') then + out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); + out_mem_readEnable <= '1'; + state <= State_ReadIO; + else + memAAddr <= memARead(maxAddrBit downto minAddrBit); + end if; + when Decoded_Not => + memAAddr <= sp(maxAddrBit downto minAddrBit); + memAWriteEnable <= '1'; + memAWrite <= not memARead; + when Decoded_Flip => + memAAddr <= sp(maxAddrBit downto minAddrBit); + memAWriteEnable <= '1'; + for i in 0 to wordSize-1 loop + memAWrite(i) <= memARead(wordSize-1-i); + end loop; + when Decoded_Store => + memBAddr <= sp + 1; + sp <= sp + 1; + if (memARead(ioBit)='1') then + state <= State_WriteIO; + else + state <= State_Store; + end if; + when Decoded_PopSP => + sp <= memARead(maxAddrBit downto minAddrBit); + state <= State_Resync; + when Decoded_Nop => + memAAddr <= sp; + when others => + null; + end case; + when State_ReadIO => + if (in_mem_busy = '0') then + state <= State_Fetch; + memAWriteEnable <= '1'; + memAWrite <= unsigned(mem_read); + end if; + when State_WriteIO => + sp <= sp + 1; + out_mem_writeEnable <= '1'; + out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); + mem_write <= std_logic_vector(memBRead); + state <= State_WriteIODone; + when State_WriteIODone => + if (in_mem_busy = '0') then + state <= State_Resync; + end if; + when State_Fetch => + -- We need to resync. During the *next* cycle + -- we'll fetch the opcode @ pc and thus it will + -- be available for State_Execute the cycle after + -- next + memBAddr <= pc(maxAddrBit downto minAddrBit); + state <= State_FetchNext; + when State_FetchNext => + -- at this point memARead contains the value that is either + -- from the top of stack or should be copied to the top of the stack + memAWriteEnable <= '1'; + memAWrite <= memARead; + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Decode; + when State_Decode => + -- during the State_Execute cycle we'll be fetching SP+1 + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Execute; + when State_Store => + sp <= sp + 1; + memAWriteEnable <= '1'; + memAAddr <= memARead(maxAddrBit downto minAddrBit); + memAWrite <= memBRead; + state <= State_Resync; + when State_AddSP => + state <= State_Add; + when State_Add => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead + memBRead; + state <= State_Fetch; + when State_Or => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead or memBRead; + state <= State_Fetch; + when State_Resync => + memAAddr <= sp; + state <= State_Fetch; + when State_And => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead and memBRead; + state <= State_Fetch; + when others => + null; + end case; + + end if; + end process; + + + +end behave; diff --git a/zpu/hdl/zpu4/src/zpupkg.vhd b/zpu/hdl/zpu4/src/zpupkg.vhd index 32e162b..f3800b0 100644 --- a/zpu/hdl/zpu4/src/zpupkg.vhd +++ b/zpu/hdl/zpu4/src/zpupkg.vhd @@ -1,6 +1,6 @@ library IEEE; use IEEE.STD_LOGIC_1164.all; -use IEEE.STD_LOGIC_ARITH.all; +use ieee.numeric_std.all; library work; use work.zpu_config.all; @@ -133,33 +133,33 @@ package zpupkg is constant OpCode_Compare : std_logic_vector(3 downto 0) := "1110"; constant OpCode_PopInt : std_logic_vector(3 downto 0) := "1111"; - constant OpCode_Lessthan : std_logic_vector(5 downto 0) := conv_std_logic_vector(36, 6); - constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := conv_std_logic_vector(37, 6); - constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := conv_std_logic_vector(38, 6); - constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := conv_std_logic_vector(39, 6); + constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6)); + constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6)); + constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6)); + constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6)); - constant OpCode_Swap : std_logic_vector(5 downto 0) := conv_std_logic_vector(40, 6); - constant OpCode_Mult : std_logic_vector(5 downto 0) := conv_std_logic_vector(41, 6); + constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6)); + constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6)); - constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := conv_std_logic_vector(42, 6); - constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := conv_std_logic_vector(43, 6); - constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := conv_std_logic_vector(44, 6); - constant OpCode_Call : std_logic_vector(5 downto 0) := conv_std_logic_vector(45, 6); + constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6)); + constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6)); + constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6)); + constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6)); - constant OpCode_Eq : std_logic_vector(5 downto 0) := conv_std_logic_vector(46, 6); - constant OpCode_Neq : std_logic_vector(5 downto 0) := conv_std_logic_vector(47, 6); + constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6)); + constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6)); - constant OpCode_Sub : std_logic_vector(5 downto 0) := conv_std_logic_vector(49, 6); - constant OpCode_Loadb : std_logic_vector(5 downto 0) := conv_std_logic_vector(51, 6); - constant OpCode_Storeb : std_logic_vector(5 downto 0) := conv_std_logic_vector(52, 6); + constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6)); + constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6)); + constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6)); - constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := conv_std_logic_vector(55, 6); - constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := conv_std_logic_vector(56, 6); - constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := conv_std_logic_vector(57, 6); + constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6)); + constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6)); + constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6)); - constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := conv_std_logic_vector(61, 6); - constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := conv_std_logic_vector(62, 6); - constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := conv_std_logic_vector(63, 6); + constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6)); + constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6)); + constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6)); -- cgit v1.1 From c641936739878f3c47e248b82a5f318103fd72f2 Mon Sep 17 00:00:00 2001 From: oharboe Date: Wed, 30 Apr 2008 18:11:46 +0000 Subject: wip to fix some synthesizing problems w/Synopsis --- zpu/hdl/zpu4/src/zpu_core_small_wip.vhd | 957 ++++++++++++++++++++++++++++++++ 1 file changed, 957 insertions(+) create mode 100644 zpu/hdl/zpu4/src/zpu_core_small_wip.vhd diff --git a/zpu/hdl/zpu4/src/zpu_core_small_wip.vhd b/zpu/hdl/zpu4/src/zpu_core_small_wip.vhd new file mode 100644 index 0000000..60ad070 --- /dev/null +++ b/zpu/hdl/zpu4/src/zpu_core_small_wip.vhd @@ -0,0 +1,957 @@ +-- Company: ZPU3 + +-- Engineer: ï¿œyvind Harboe + + + +library IEEE; + +use IEEE.STD_LOGIC_1164.ALL; + +use ieee.numeric_std.all; + + + +library work; + +use work.zpu_config.all; + +use work.zpupkg.all; + + + +entity zpu_core is + + Port ( clk : in std_logic; + + areset : in std_logic; + + enable : in std_logic; + + in_mem_busy : in std_logic; + + mem_read : in std_logic_vector(wordSize-1 downto 0); + + mem_write : out std_logic_vector(wordSize-1 downto 0); + + out_mem_addr : out std_logic_vector(maxAddrBitIncIO + +downto 0); + + out_mem_writeEnable : out std_logic; + + out_mem_readEnable : out std_logic; + + mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + + interrupt : in std_logic; + + break : out std_logic + + ); + + + +end zpu_core; + + + +architecture behave of zpu_core is + + + +signal readIO : std_logic; + + + + + + + +signal memAWriteEnable : std_logic; + +signal memAAddr : unsigned(maxAddrBit downto minAddrBit); + +signal memAWrite : unsigned(wordSize-1 downto 0); + +signal memARead : unsigned(wordSize-1 downto 0); + +signal memBWriteEnable : std_logic; + +signal memBAddr : unsigned(maxAddrBit downto minAddrBit); + +signal memBWrite : unsigned(wordSize-1 downto 0); + +signal memBRead : unsigned(wordSize-1 downto 0); + + + +signal pc : unsigned(maxAddrBit downto 0); + +signal sp : unsigned(maxAddrBit downto minAddrBit); + + + +signal idim_flag : std_logic; + + + +--signal storeToStack : std_logic; + +--signal fetchNextInstruction : std_logic; + +--signal extraCycle : std_logic; + + + +signal busy : std_logic; + +--signal fetching : std_logic; + + + +signal begin_inst : std_logic; + + + +signal trace_opcode : std_logic_vector(7 downto 0); + +signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); + +signal trace_sp : std_logic_vector(maxAddrBitIncIO downto + +minAddrBit); + +signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); + +signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); + + + +-- state machine. + +type State_Type is + +( + +State_Fetch, + +State_WriteIODone, + +State_Execute, + +State_StoreToStack, + +State_Add, + +State_Or, + +State_And, + +State_Store, + +State_ReadIO, + +State_WriteIO, + +State_Load, + +State_FetchNext, + +State_AddSP, + +State_ReadIODone, + +State_Decode, + +State_Resync + +); + + + +type DecodedOpcodeType is + +( + +Decoded_Nop, + +Decoded_Im, + +Decoded_ImShift, + +Decoded_LoadSP, + +Decoded_StoreSP , + +Decoded_AddSP, + +Decoded_Emulate, + +Decoded_Break, + +Decoded_PushSP, + +Decoded_PopPC, + +Decoded_Add, + +Decoded_Or, + +Decoded_And, + +Decoded_Load, + +Decoded_Not, + +Decoded_Flip, + +Decoded_Store, + +Decoded_PopSP + +); + + + + + +signal sampledOpcode : std_logic_vector(OpCode_Size-1 downto 0); + +signal opcode : std_logic_vector(OpCode_Size-1 downto 0); + + + +signal decodedOpcode : DecodedOpcodeType; + +signal sampledDecodedOpcode : DecodedOpcodeType; + + + + + +signal state : State_Type; + + + +subtype AddrBitBRAM_range is natural range maxAddrBitBRAM downto + +minAddrBit; + +signal memAAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); + +signal memAWrite_stdlogic : std_logic_vector(memAWrite'range); + +signal memARead_stdlogic : std_logic_vector(memARead'range); + +signal memBAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); + +signal memBWrite_stdlogic : std_logic_vector(memBWrite'range); + +signal memBRead_stdlogic : std_logic_vector(memBRead'range); + + + +-- debug + +subtype index is integer range 0 to 31; + +signal tOpcode_sel : index; + + + + + +begin + + traceFileGenerate: + + if Generate_Trace generate + + trace_file: trace port map ( + + clk => clk, + + begin_inst => begin_inst, + + pc => trace_pc, + + opcode => trace_opcode, + + sp => trace_sp, + + memA => trace_topOfStack, + + memB => trace_topOfStackB, + + busy => busy, + + intsp => (others => 'U') + + ); + + end generate; + + + + -- not used in this design + + mem_writeMask <= (others => '1'); + + + + memAAddr_stdlogic <= std_logic_vector(memAAddr(AddrBitBRAM_range)); + + memAWrite_stdlogic <= std_logic_vector(memAWrite); + + memBAddr_stdlogic <= std_logic_vector(memBAddr(AddrBitBRAM_range)); + + memBWrite_stdlogic <= std_logic_vector(memBWrite); + + memory: dualport_ram port map ( + + clk => clk, + + memAWriteEnable => memAWriteEnable, + + memAAddr => memAAddr_stdlogic, + + memAWrite => memAWrite_stdlogic, + + memARead => memARead_stdlogic, + + memBWriteEnable => memBWriteEnable, + + memBAddr => memBAddr_stdlogic, + + memBWrite => memBWrite_stdlogic, + + memBRead => memBRead_stdlogic + + ); + + memARead <= unsigned(memARead_stdlogic); + + memBRead <= unsigned(memBRead_stdlogic); + + + +tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0)); + + + + decodeControl: + + process(memBRead, pc,tOpcode_sel) + + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + + begin + + -- not worked with synopsys + + -- tOpcode := + +std_logic_vector(memBRead((wordBytes-1-to_integer(pc(minAddrBit-1 + +downto 0))+1)*8-1 downto (wordBytes-1-to_integer(pc(minAddrBit-1 + +downto 0)))*8)); + + case (tOpcode_sel) is + + when 0 => tOpcode := std_logic_vector(memBRead(31 downto 24)); + + when 1 => tOpcode := std_logic_vector(memBRead(23 downto 16)); + + when 2 => tOpcode := std_logic_vector(memBRead(15 downto 8)); + + when 3 => tOpcode := std_logic_vector(memBRead(7 downto 0)); + + when others => tOpcode := std_logic_vector(memBRead(7 + +downto 0)); + + end case; + + sampledOpcode <= tOpcode; + + + + if (tOpcode(7 downto 7)=OpCode_Im) then + + sampledDecodedOpcode<=Decoded_Im; + + elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then + + sampledDecodedOpcode<=Decoded_StoreSP; + + elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then + + sampledDecodedOpcode<=Decoded_LoadSP; + + elsif (tOpcode(7 downto 5)=OpCode_Emulate) then + + sampledDecodedOpcode<=Decoded_Emulate; + + elsif (tOpcode(7 downto 4)=OpCode_AddSP) then + + sampledDecodedOpcode<=Decoded_AddSP; + + else + + case tOpcode(3 downto 0) is + + when OpCode_Break => + + sampledDecodedOpcode<=Decoded_Break; + + when OpCode_PushSP => + + sampledDecodedOpcode<=Decoded_PushSP; + + when OpCode_PopPC => + + sampledDecodedOpcode<=Decoded_PopPC; + + when OpCode_Add => + + sampledDecodedOpcode<=Decoded_Add; + + when OpCode_Or => + + sampledDecodedOpcode<=Decoded_Or; + + when OpCode_And => + + sampledDecodedOpcode<=Decoded_And; + + when OpCode_Load => + + sampledDecodedOpcode<=Decoded_Load; + + when OpCode_Not => + + sampledDecodedOpcode<=Decoded_Not; + + when OpCode_Flip => + + sampledDecodedOpcode<=Decoded_Flip; + + when OpCode_Store => + + sampledDecodedOpcode<=Decoded_Store; + + when OpCode_PopSP => + + sampledDecodedOpcode<=Decoded_PopSP; + + when others => + + sampledDecodedOpcode<=Decoded_Nop; + + end case; + + end if; + + end process; + + + + + + opcodeControl: + + process(clk, areset) + + variable spOffset : unsigned(4 downto 0); + + begin + + if areset = '1' then + + state <= State_Resync; + + break <= '0'; + + sp <= unsigned(spStart(maxAddrBit downto minAddrBit)); + + pc <= (others => '0'); + + idim_flag <= '0'; + + begin_inst <= '0'; + + memAAddr <= (others => '0'); + + memBAddr <= (others => '0'); + + memAWriteEnable <= '0'; + + memBWriteEnable <= '0'; + + out_mem_writeEnable <= '0'; + + out_mem_readEnable <= '0'; + + memAWrite <= (others => '0'); + + memBWrite <= (others => '0'); + + -- avoid Latch in synopsys + + -- mem_writeMask <= (others => '1'); + + elsif (clk'event and clk = '1') then + + memAWriteEnable <= '0'; + + memBWriteEnable <= '0'; + + -- This saves ca. 100 LUT's, by explicitly declaring that the + + -- memAWrite can be left at whatever value if + +memAWriteEnable is + + -- not set. + + memAWrite <= (others => DontCareValue); + + memBWrite <= (others => DontCareValue); + +-- out_mem_addr <= (others => DontCareValue); + +-- mem_write <= (others => DontCareValue); + + spOffset := (others => DontCareValue); + + memAAddr <= (others => DontCareValue); + + memBAddr <= (others => DontCareValue); + + + + out_mem_writeEnable <= '0'; + + out_mem_readEnable <= '0'; + + begin_inst <= '0'; + + out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO + +downto 0)); + + mem_write <= std_logic_vector(memBRead); + + + + decodedOpcode <= sampledDecodedOpcode; + + opcode <= sampledOpcode; + + + + case state is + + when State_Execute => + + state <= State_Fetch; + + -- at this point: + + -- memBRead contains opcode word + + -- memARead contains top of stack + + pc <= pc + 1; + + + + -- trace + + begin_inst <= '1'; + + trace_pc <= (others => '0'); + + trace_pc(maxAddrBit downto 0) <= std_logic_vector(pc); + + trace_opcode <= opcode; + + trace_sp <= (others => '0'); + + trace_sp(maxAddrBit downto minAddrBit) <= + +std_logic_vector(sp); + + trace_topOfStack <= std_logic_vector(memARead); + + trace_topOfStackB <= std_logic_vector(memBRead); + + + + -- during the next cycle we'll be reading the next + +opcode + + spOffset(4):=not opcode(4); + + spOffset(3 downto 0) := unsigned(opcode(3 downto 0)); + + + + idim_flag <= '0'; + + case decodedOpcode is + + when Decoded_Im => + + idim_flag <= '1'; + + memAWriteEnable <= '1'; + + if (idim_flag='0') then + + sp <= sp - 1; + + memAAddr <= sp-1; + + for i in wordSize-1 downto 7 loop + + memAWrite(i) <= opcode(6); + + end loop; + + memAWrite(6 downto 0) <= + +unsigned(opcode(6 downto 0)); + + else + + memAAddr <= sp; + + memAWrite(wordSize-1 downto 7) <= + +memARead(wordSize-8 downto 0); + + memAWrite(6 downto 0) <= + +unsigned(opcode(6 downto 0)); + + end if; + + when Decoded_StoreSP => + + memBWriteEnable <= '1'; + + memBAddr <= sp+spOffset; + + memBWrite <= memARead; + + sp <= sp + 1; + + state <= State_Resync; + + when Decoded_LoadSP => + + sp <= sp - 1; + + memAAddr <= sp+spOffset; + + when Decoded_Emulate => + + sp <= sp - 1; + + memAWriteEnable <= '1'; + + memAAddr <= sp - 1; + + memAWrite <= (others => DontCareValue); + + memAWrite(maxAddrBit downto 0) <= pc + 1; + + -- The emulate address is: + + -- 98 7654 3210 + + -- 0000 00aa aaa0 0000 + + pc <= (others => '0'); + + pc(9 downto 5) <= unsigned(opcode(4 downto + +0)); + + when Decoded_AddSP => + + memAAddr <= sp; + + memBAddr <= sp+spOffset; + + state <= State_AddSP; + + when Decoded_Break => + + report "Break instruction encountered" + +severity failure; + + break <= '1'; + + when Decoded_PushSP => + + memAWriteEnable <= '1'; + + memAAddr <= sp - 1; + + sp <= sp - 1; + + memAWrite <= (others => DontCareValue); + + memAWrite(maxAddrBit downto minAddrBit) <= sp; + + when Decoded_PopPC => + + pc <= memARead(maxAddrBit downto 0); + + sp <= sp + 1; + + state <= State_Resync; + + when Decoded_Add => + + sp <= sp + 1; + + state <= State_Add; + + when Decoded_Or => + + sp <= sp + 1; + + state <= State_Or; + + when Decoded_And => + + sp <= sp + 1; + + state <= State_And; + + when Decoded_Load => + + if (memARead(ioBit)='1') then + + out_mem_addr <= + +std_logic_vector(memARead(maxAddrBitIncIO downto 0)); + + out_mem_readEnable <= '1'; + + state <= State_ReadIO; + + else + + memAAddr <= memARead(maxAddrBit downto + +minAddrBit); + + end if; + + when Decoded_Not => + + memAAddr <= sp(maxAddrBit downto minAddrBit); + + memAWriteEnable <= '1'; + + memAWrite <= not memARead; + + when Decoded_Flip => + + memAAddr <= sp(maxAddrBit downto minAddrBit); + + memAWriteEnable <= '1'; + + for i in 0 to wordSize-1 loop + + memAWrite(i) <= memARead(wordSize-1-i); + + end loop; + + when Decoded_Store => + + memBAddr <= sp + 1; + + sp <= sp + 1; + + if (memARead(ioBit)='1') then + + state <= State_WriteIO; + + else + + state <= State_Store; + + end if; + + when Decoded_PopSP => + + sp <= memARead(maxAddrBit downto minAddrBit); + + state <= State_Resync; + + when Decoded_Nop => + + memAAddr <= sp; + + when others => + + null; + + end case; + + when State_ReadIO => + + if (in_mem_busy = '0') then + + state <= State_Fetch; + + memAWriteEnable <= '1'; + + memAWrite <= unsigned(mem_read); + + end if; + + when State_WriteIO => + + sp <= sp + 1; + + out_mem_writeEnable <= '1'; + + out_mem_addr <= + +std_logic_vector(memARead(maxAddrBitIncIO downto 0)); + + mem_write <= std_logic_vector(memBRead); + + state <= State_WriteIODone; + + when State_WriteIODone => + + if (in_mem_busy = '0') then + + state <= State_Resync; + + end if; + + when State_Fetch => + + -- We need to resync. During the *next* cycle + + -- we'll fetch the opcode @ pc and thus it will + + -- be available for State_Execute the cycle after + + -- next + + memBAddr <= pc(maxAddrBit downto minAddrBit); + + state <= State_FetchNext; + + when State_FetchNext => + + -- at this point memARead contains the value that + +is either + + -- from the top of stack or should be copied to + +the top of the stack + + memAWriteEnable <= '1'; + + memAWrite <= memARead; + + memAAddr <= sp; + + memBAddr <= sp + 1; + + state <= State_Decode; + + when State_Decode => + + -- during the State_Execute cycle we'll be + +fetching SP+1 + + memAAddr <= sp; + + memBAddr <= sp + 1; + + state <= State_Execute; + + when State_Store => + + sp <= sp + 1; + + memAWriteEnable <= '1'; + + memAAddr <= memARead(maxAddrBit downto minAddrBit); + + memAWrite <= memBRead; + + state <= State_Resync; + + when State_AddSP => + + state <= State_Add; + + when State_Add => + + memAAddr <= sp; + + memAWriteEnable <= '1'; + + memAWrite <= memARead + memBRead; + + state <= State_Fetch; + + when State_Or => + + memAAddr <= sp; + + memAWriteEnable <= '1'; + + memAWrite <= memARead or memBRead; + + state <= State_Fetch; + + when State_Resync => + + memAAddr <= sp; + + state <= State_Fetch; + + when State_And => + + memAAddr <= sp; + + memAWriteEnable <= '1'; + + memAWrite <= memARead and memBRead; + + state <= State_Fetch; + + when others => + + null; + + end case; + + + + end if; + + end process; + + + +end behave; -- cgit v1.1 From 7a1fb6dbe419749a2acf4ce583d7732480264ba6 Mon Sep 17 00:00:00 2001 From: oharboe Date: Wed, 30 Apr 2008 18:12:06 +0000 Subject: wip to fix some synthesizing problems w/Synopsis --- zpu/hdl/zpu4/src/zpu_core_small_wip.vhd | 1155 +++++++++---------------------- 1 file changed, 338 insertions(+), 817 deletions(-) diff --git a/zpu/hdl/zpu4/src/zpu_core_small_wip.vhd b/zpu/hdl/zpu4/src/zpu_core_small_wip.vhd index 60ad070..63e02e4 100644 --- a/zpu/hdl/zpu4/src/zpu_core_small_wip.vhd +++ b/zpu/hdl/zpu4/src/zpu_core_small_wip.vhd @@ -1,260 +1,131 @@ -- Company: ZPU3 - --- Engineer: ï¿œyvind Harboe - - +-- Engineer: Øyvind Harboe library IEEE; - use IEEE.STD_LOGIC_1164.ALL; - use ieee.numeric_std.all; - - library work; - use work.zpu_config.all; - use work.zpupkg.all; - entity zpu_core is - - Port ( clk : in std_logic; - - areset : in std_logic; - - enable : in std_logic; - - in_mem_busy : in std_logic; - - mem_read : in std_logic_vector(wordSize-1 downto 0); - - mem_write : out std_logic_vector(wordSize-1 downto 0); - - out_mem_addr : out std_logic_vector(maxAddrBitIncIO - -downto 0); - - out_mem_writeEnable : out std_logic; - - out_mem_readEnable : out std_logic; - - mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); - - interrupt : in std_logic; - - break : out std_logic - - ); - - - + Port ( clk : in std_logic; + areset : in std_logic; + enable : in std_logic; + in_mem_busy : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + out_mem_writeEnable : out std_logic; + out_mem_readEnable : out std_logic; + mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + interrupt : in std_logic; + break : out std_logic); end zpu_core; - - architecture behave of zpu_core is - - -signal readIO : std_logic; - - - - +signal readIO : std_logic; signal memAWriteEnable : std_logic; - signal memAAddr : unsigned(maxAddrBit downto minAddrBit); - signal memAWrite : unsigned(wordSize-1 downto 0); - signal memARead : unsigned(wordSize-1 downto 0); - signal memBWriteEnable : std_logic; - signal memBAddr : unsigned(maxAddrBit downto minAddrBit); - signal memBWrite : unsigned(wordSize-1 downto 0); - signal memBRead : unsigned(wordSize-1 downto 0); -signal pc : unsigned(maxAddrBit downto 0); - -signal sp : unsigned(maxAddrBit downto minAddrBit); - - - -signal idim_flag : std_logic; - - - ---signal storeToStack : std_logic; - ---signal fetchNextInstruction : std_logic; - ---signal extraCycle : std_logic; - - - -signal busy : std_logic; - ---signal fetching : std_logic; - - +signal pc : unsigned(maxAddrBit downto 0); +signal sp : unsigned(maxAddrBit downto minAddrBit); -signal begin_inst : std_logic; +signal idim_flag : std_logic; +--signal storeToStack : std_logic; +--signal fetchNextInstruction : std_logic; +--signal extraCycle : std_logic; +signal busy : std_logic; +--signal fetching : std_logic; +signal begin_inst : std_logic; -signal trace_opcode : std_logic_vector(7 downto 0); - -signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); - -signal trace_sp : std_logic_vector(maxAddrBitIncIO downto - -minAddrBit); - -signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); - -signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); +signal trace_opcode : std_logic_vector(7 downto 0); +signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); +signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); +signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); -- state machine. - type State_Type is - ( - State_Fetch, - State_WriteIODone, - State_Execute, - State_StoreToStack, - State_Add, - State_Or, - State_And, - State_Store, - State_ReadIO, - State_WriteIO, - State_Load, - State_FetchNext, - State_AddSP, - State_ReadIODone, - State_Decode, - State_Resync - ); - - type DecodedOpcodeType is - ( - Decoded_Nop, - Decoded_Im, - Decoded_ImShift, - Decoded_LoadSP, - -Decoded_StoreSP , - +Decoded_StoreSP , Decoded_AddSP, - Decoded_Emulate, - Decoded_Break, - Decoded_PushSP, - Decoded_PopPC, - Decoded_Add, - Decoded_Or, - Decoded_And, - Decoded_Load, - Decoded_Not, - Decoded_Flip, - Decoded_Store, - Decoded_PopSP - ); - - signal sampledOpcode : std_logic_vector(OpCode_Size-1 downto 0); - signal opcode : std_logic_vector(OpCode_Size-1 downto 0); - - signal decodedOpcode : DecodedOpcodeType; - signal sampledDecodedOpcode : DecodedOpcodeType; - - - signal state : State_Type; - - -subtype AddrBitBRAM_range is natural range maxAddrBitBRAM downto - -minAddrBit; - +subtype AddrBitBRAM_range is natural range maxAddrBitBRAM downto minAddrBit; signal memAAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); - signal memAWrite_stdlogic : std_logic_vector(memAWrite'range); - signal memARead_stdlogic : std_logic_vector(memARead'range); - signal memBAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); - signal memBWrite_stdlogic : std_logic_vector(memBWrite'range); - signal memBRead_stdlogic : std_logic_vector(memBRead'range); - - --- debug - -subtype index is integer range 0 to 31; +subtype index is integer range 0 to 3; signal tOpcode_sel : index; @@ -263,34 +134,20 @@ signal tOpcode_sel : index; begin - - traceFileGenerate: - + traceFileGenerate: if Generate_Trace generate - - trace_file: trace port map ( - - clk => clk, - - begin_inst => begin_inst, - - pc => trace_pc, - - opcode => trace_opcode, - - sp => trace_sp, - - memA => trace_topOfStack, - - memB => trace_topOfStackB, - - busy => busy, - - intsp => (others => 'U') - + trace_file: trace port map ( + clk => clk, + begin_inst => begin_inst, + pc => trace_pc, + opcode => trace_opcode, + sp => trace_sp, + memA => trace_topOfStack, + memB => trace_topOfStackB, + busy => busy, + intsp => (others => 'U') ); - - end generate; + end generate; @@ -300,64 +157,36 @@ begin - memAAddr_stdlogic <= std_logic_vector(memAAddr(AddrBitBRAM_range)); - - memAWrite_stdlogic <= std_logic_vector(memAWrite); - - memBAddr_stdlogic <= std_logic_vector(memBAddr(AddrBitBRAM_range)); - - memBWrite_stdlogic <= std_logic_vector(memBWrite); - - memory: dualport_ram port map ( - - clk => clk, - - memAWriteEnable => memAWriteEnable, - - memAAddr => memAAddr_stdlogic, - - memAWrite => memAWrite_stdlogic, - - memARead => memARead_stdlogic, - - memBWriteEnable => memBWriteEnable, - - memBAddr => memBAddr_stdlogic, - - memBWrite => memBWrite_stdlogic, - - memBRead => memBRead_stdlogic - + memAAddr_stdlogic <= std_logic_vector(memAAddr(AddrBitBRAM_range)); + memAWrite_stdlogic <= std_logic_vector(memAWrite); + memBAddr_stdlogic <= std_logic_vector(memBAddr(AddrBitBRAM_range)); + memBWrite_stdlogic <= std_logic_vector(memBWrite); + memory: dualport_ram port map ( + clk => clk, + memAWriteEnable => memAWriteEnable, + memAAddr => memAAddr_stdlogic, + memAWrite => memAWrite_stdlogic, + memARead => memARead_stdlogic, + memBWriteEnable => memBWriteEnable, + memBAddr => memBAddr_stdlogic, + memBWrite => memBWrite_stdlogic, + memBRead => memBRead_stdlogic ); - - memARead <= unsigned(memARead_stdlogic); - - memBRead <= unsigned(memBRead_stdlogic); - - - -tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0)); - + memARead <= unsigned(memARead_stdlogic); + memBRead <= unsigned(memBRead_stdlogic); - decodeControl: - process(memBRead, pc,tOpcode_sel) + tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0)); - variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); - begin - -- not worked with synopsys - - -- tOpcode := - -std_logic_vector(memBRead((wordBytes-1-to_integer(pc(minAddrBit-1 - -downto 0))+1)*8-1 downto (wordBytes-1-to_integer(pc(minAddrBit-1 - -downto 0)))*8)); + decodeControl: + process(memBRead, pc,tOpcode_sel) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + begin + -- simplify opcode selection a bit so it passes more synthesizers case (tOpcode_sel) is when 0 => tOpcode := std_logic_vector(memBRead(31 downto 24)); @@ -368,589 +197,281 @@ downto 0)))*8)); when 3 => tOpcode := std_logic_vector(memBRead(7 downto 0)); - when others => tOpcode := std_logic_vector(memBRead(7 - -downto 0)); - + when others => tOpcode := std_logic_vector(memBRead(7 downto 0)); end case; - sampledOpcode <= tOpcode; - - - - if (tOpcode(7 downto 7)=OpCode_Im) then - - sampledDecodedOpcode<=Decoded_Im; - - elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then - - sampledDecodedOpcode<=Decoded_StoreSP; - - elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then - - sampledDecodedOpcode<=Decoded_LoadSP; - - elsif (tOpcode(7 downto 5)=OpCode_Emulate) then - - sampledDecodedOpcode<=Decoded_Emulate; - - elsif (tOpcode(7 downto 4)=OpCode_AddSP) then - - sampledDecodedOpcode<=Decoded_AddSP; - - else - - case tOpcode(3 downto 0) is - - when OpCode_Break => - - sampledDecodedOpcode<=Decoded_Break; - - when OpCode_PushSP => - - sampledDecodedOpcode<=Decoded_PushSP; - - when OpCode_PopPC => - - sampledDecodedOpcode<=Decoded_PopPC; - - when OpCode_Add => - - sampledDecodedOpcode<=Decoded_Add; - - when OpCode_Or => - - sampledDecodedOpcode<=Decoded_Or; - - when OpCode_And => - - sampledDecodedOpcode<=Decoded_And; - - when OpCode_Load => - - sampledDecodedOpcode<=Decoded_Load; - - when OpCode_Not => - - sampledDecodedOpcode<=Decoded_Not; - - when OpCode_Flip => - - sampledDecodedOpcode<=Decoded_Flip; - - when OpCode_Store => - - sampledDecodedOpcode<=Decoded_Store; - - when OpCode_PopSP => - - sampledDecodedOpcode<=Decoded_PopSP; - - when others => - - sampledDecodedOpcode<=Decoded_Nop; - - end case; - - end if; - - end process; - - - - - - opcodeControl: - - process(clk, areset) - - variable spOffset : unsigned(4 downto 0); - - begin - - if areset = '1' then - - state <= State_Resync; - - break <= '0'; - - sp <= unsigned(spStart(maxAddrBit downto minAddrBit)); - - pc <= (others => '0'); - - idim_flag <= '0'; - - begin_inst <= '0'; - - memAAddr <= (others => '0'); - - memBAddr <= (others => '0'); - - memAWriteEnable <= '0'; - - memBWriteEnable <= '0'; - - out_mem_writeEnable <= '0'; - - out_mem_readEnable <= '0'; - - memAWrite <= (others => '0'); - - memBWrite <= (others => '0'); - - -- avoid Latch in synopsys - - -- mem_writeMask <= (others => '1'); - - elsif (clk'event and clk = '1') then - - memAWriteEnable <= '0'; - - memBWriteEnable <= '0'; - - -- This saves ca. 100 LUT's, by explicitly declaring that the - - -- memAWrite can be left at whatever value if - -memAWriteEnable is - - -- not set. - - memAWrite <= (others => DontCareValue); - - memBWrite <= (others => DontCareValue); - --- out_mem_addr <= (others => DontCareValue); - --- mem_write <= (others => DontCareValue); - - spOffset := (others => DontCareValue); - - memAAddr <= (others => DontCareValue); - - memBAddr <= (others => DontCareValue); - - - - out_mem_writeEnable <= '0'; - - out_mem_readEnable <= '0'; - - begin_inst <= '0'; - - out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO - -downto 0)); - - mem_write <= std_logic_vector(memBRead); - - - - decodedOpcode <= sampledDecodedOpcode; - - opcode <= sampledOpcode; - - - - case state is - - when State_Execute => - - state <= State_Fetch; - - -- at this point: - - -- memBRead contains opcode word - - -- memARead contains top of stack - - pc <= pc + 1; - - - - -- trace - - begin_inst <= '1'; - - trace_pc <= (others => '0'); - - trace_pc(maxAddrBit downto 0) <= std_logic_vector(pc); - - trace_opcode <= opcode; - - trace_sp <= (others => '0'); - - trace_sp(maxAddrBit downto minAddrBit) <= - -std_logic_vector(sp); - - trace_topOfStack <= std_logic_vector(memARead); - - trace_topOfStackB <= std_logic_vector(memBRead); - - - - -- during the next cycle we'll be reading the next - -opcode - - spOffset(4):=not opcode(4); - - spOffset(3 downto 0) := unsigned(opcode(3 downto 0)); - - - - idim_flag <= '0'; - - case decodedOpcode is - - when Decoded_Im => - - idim_flag <= '1'; - - memAWriteEnable <= '1'; - - if (idim_flag='0') then - - sp <= sp - 1; - - memAAddr <= sp-1; - - for i in wordSize-1 downto 7 loop - - memAWrite(i) <= opcode(6); - - end loop; - - memAWrite(6 downto 0) <= - -unsigned(opcode(6 downto 0)); - - else - - memAAddr <= sp; - - memAWrite(wordSize-1 downto 7) <= - -memARead(wordSize-8 downto 0); - - memAWrite(6 downto 0) <= - -unsigned(opcode(6 downto 0)); - - end if; - - when Decoded_StoreSP => - - memBWriteEnable <= '1'; - - memBAddr <= sp+spOffset; - - memBWrite <= memARead; - - sp <= sp + 1; - - state <= State_Resync; - - when Decoded_LoadSP => - - sp <= sp - 1; - - memAAddr <= sp+spOffset; - - when Decoded_Emulate => - - sp <= sp - 1; - - memAWriteEnable <= '1'; - - memAAddr <= sp - 1; - - memAWrite <= (others => DontCareValue); - - memAWrite(maxAddrBit downto 0) <= pc + 1; - - -- The emulate address is: - - -- 98 7654 3210 - - -- 0000 00aa aaa0 0000 - - pc <= (others => '0'); - - pc(9 downto 5) <= unsigned(opcode(4 downto - -0)); - - when Decoded_AddSP => - - memAAddr <= sp; - - memBAddr <= sp+spOffset; - - state <= State_AddSP; - - when Decoded_Break => - - report "Break instruction encountered" - -severity failure; - - break <= '1'; - - when Decoded_PushSP => - - memAWriteEnable <= '1'; - - memAAddr <= sp - 1; - - sp <= sp - 1; - - memAWrite <= (others => DontCareValue); - - memAWrite(maxAddrBit downto minAddrBit) <= sp; - - when Decoded_PopPC => - - pc <= memARead(maxAddrBit downto 0); - - sp <= sp + 1; - - state <= State_Resync; - - when Decoded_Add => - - sp <= sp + 1; - - state <= State_Add; - - when Decoded_Or => - - sp <= sp + 1; - - state <= State_Or; - - when Decoded_And => - - sp <= sp + 1; - - state <= State_And; - - when Decoded_Load => - - if (memARead(ioBit)='1') then - - out_mem_addr <= - -std_logic_vector(memARead(maxAddrBitIncIO downto 0)); - - out_mem_readEnable <= '1'; - - state <= State_ReadIO; - - else - - memAAddr <= memARead(maxAddrBit downto - -minAddrBit); - - end if; - - when Decoded_Not => - - memAAddr <= sp(maxAddrBit downto minAddrBit); - - memAWriteEnable <= '1'; - - memAWrite <= not memARead; - - when Decoded_Flip => - - memAAddr <= sp(maxAddrBit downto minAddrBit); - - memAWriteEnable <= '1'; - - for i in 0 to wordSize-1 loop - - memAWrite(i) <= memARead(wordSize-1-i); - - end loop; - - when Decoded_Store => - - memBAddr <= sp + 1; - - sp <= sp + 1; - - if (memARead(ioBit)='1') then - - state <= State_WriteIO; - - else - - state <= State_Store; - - end if; - - when Decoded_PopSP => - - sp <= memARead(maxAddrBit downto minAddrBit); - - state <= State_Resync; - - when Decoded_Nop => - - memAAddr <= sp; - - when others => - - null; - - end case; - - when State_ReadIO => - - if (in_mem_busy = '0') then - - state <= State_Fetch; - - memAWriteEnable <= '1'; - - memAWrite <= unsigned(mem_read); - - end if; - - when State_WriteIO => - - sp <= sp + 1; - - out_mem_writeEnable <= '1'; - - out_mem_addr <= - -std_logic_vector(memARead(maxAddrBitIncIO downto 0)); - - mem_write <= std_logic_vector(memBRead); - - state <= State_WriteIODone; - - when State_WriteIODone => - - if (in_mem_busy = '0') then - - state <= State_Resync; - - end if; - - when State_Fetch => - - -- We need to resync. During the *next* cycle - - -- we'll fetch the opcode @ pc and thus it will - - -- be available for State_Execute the cycle after - - -- next - - memBAddr <= pc(maxAddrBit downto minAddrBit); - - state <= State_FetchNext; - - when State_FetchNext => - - -- at this point memARead contains the value that - -is either - - -- from the top of stack or should be copied to - -the top of the stack - - memAWriteEnable <= '1'; - - memAWrite <= memARead; - - memAAddr <= sp; - - memBAddr <= sp + 1; - - state <= State_Decode; - - when State_Decode => - - -- during the State_Execute cycle we'll be - -fetching SP+1 - - memAAddr <= sp; - - memBAddr <= sp + 1; - - state <= State_Execute; - - when State_Store => - - sp <= sp + 1; - - memAWriteEnable <= '1'; - - memAAddr <= memARead(maxAddrBit downto minAddrBit); - - memAWrite <= memBRead; - - state <= State_Resync; - - when State_AddSP => - - state <= State_Add; - - when State_Add => - - memAAddr <= sp; - - memAWriteEnable <= '1'; - - memAWrite <= memARead + memBRead; - - state <= State_Fetch; - - when State_Or => - - memAAddr <= sp; - - memAWriteEnable <= '1'; - - memAWrite <= memARead or memBRead; - - state <= State_Fetch; - - when State_Resync => - - memAAddr <= sp; - - state <= State_Fetch; - - when State_And => - - memAAddr <= sp; - - memAWriteEnable <= '1'; - - memAWrite <= memARead and memBRead; - - state <= State_Fetch; - - when others => - - null; - - end case; - - - - end if; - - end process; + sampledOpcode <= tOpcode; + + if (tOpcode(7 downto 7)=OpCode_Im) then + sampledDecodedOpcode<=Decoded_Im; + elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then + sampledDecodedOpcode<=Decoded_StoreSP; + elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then + sampledDecodedOpcode<=Decoded_LoadSP; + elsif (tOpcode(7 downto 5)=OpCode_Emulate) then + sampledDecodedOpcode<=Decoded_Emulate; + elsif (tOpcode(7 downto 4)=OpCode_AddSP) then + sampledDecodedOpcode<=Decoded_AddSP; + else + case tOpcode(3 downto 0) is + when OpCode_Break => + sampledDecodedOpcode<=Decoded_Break; + when OpCode_PushSP => + sampledDecodedOpcode<=Decoded_PushSP; + when OpCode_PopPC => + sampledDecodedOpcode<=Decoded_PopPC; + when OpCode_Add => + sampledDecodedOpcode<=Decoded_Add; + when OpCode_Or => + sampledDecodedOpcode<=Decoded_Or; + when OpCode_And => + sampledDecodedOpcode<=Decoded_And; + when OpCode_Load => + sampledDecodedOpcode<=Decoded_Load; + when OpCode_Not => + sampledDecodedOpcode<=Decoded_Not; + when OpCode_Flip => + sampledDecodedOpcode<=Decoded_Flip; + when OpCode_Store => + sampledDecodedOpcode<=Decoded_Store; + when OpCode_PopSP => + sampledDecodedOpcode<=Decoded_PopSP; + when others => + sampledDecodedOpcode<=Decoded_Nop; + end case; + end if; + end process; + + + opcodeControl: + process(clk, areset) + variable spOffset : unsigned(4 downto 0); + begin + if areset = '1' then + state <= State_Resync; + break <= '0'; + sp <= unsigned(spStart(maxAddrBit downto minAddrBit)); + pc <= (others => '0'); + idim_flag <= '0'; + begin_inst <= '0'; + memAAddr <= (others => '0'); + memBAddr <= (others => '0'); + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + out_mem_writeEnable <= '0'; + out_mem_readEnable <= '0'; + memAWrite <= (others => '0'); + memBWrite <= (others => '0'); + elsif (clk'event and clk = '1') then + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + -- This saves ca. 100 LUT's, by explicitly declaring that the + -- memAWrite can be left at whatever value if memAWriteEnable is + -- not set. + memAWrite <= (others => DontCareValue); + memBWrite <= (others => DontCareValue); +-- out_mem_addr <= (others => DontCareValue); +-- mem_write <= (others => DontCareValue); + spOffset := (others => DontCareValue); + memAAddr <= (others => DontCareValue); + memBAddr <= (others => DontCareValue); + + out_mem_writeEnable <= '0'; + out_mem_readEnable <= '0'; + begin_inst <= '0'; + out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); + mem_write <= std_logic_vector(memBRead); + + decodedOpcode <= sampledDecodedOpcode; + opcode <= sampledOpcode; + + case state is + when State_Execute => + state <= State_Fetch; + -- at this point: + -- memBRead contains opcode word + -- memARead contains top of stack + pc <= pc + 1; + + -- trace + begin_inst <= '1'; + trace_pc <= (others => '0'); + trace_pc(maxAddrBit downto 0) <= std_logic_vector(pc); + trace_opcode <= opcode; + trace_sp <= (others => '0'); + trace_sp(maxAddrBit downto minAddrBit) <= std_logic_vector(sp); + trace_topOfStack <= std_logic_vector(memARead); + trace_topOfStackB <= std_logic_vector(memBRead); + + -- during the next cycle we'll be reading the next opcode + spOffset(4):=not opcode(4); + spOffset(3 downto 0) := unsigned(opcode(3 downto 0)); + + idim_flag <= '0'; + case decodedOpcode is + when Decoded_Im => + idim_flag <= '1'; + memAWriteEnable <= '1'; + if (idim_flag='0') then + sp <= sp - 1; + memAAddr <= sp-1; + for i in wordSize-1 downto 7 loop + memAWrite(i) <= opcode(6); + end loop; + memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); + else + memAAddr <= sp; + memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0); + memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); + end if; + when Decoded_StoreSP => + memBWriteEnable <= '1'; + memBAddr <= sp+spOffset; + memBWrite <= memARead; + sp <= sp + 1; + state <= State_Resync; + when Decoded_LoadSP => + sp <= sp - 1; + memAAddr <= sp+spOffset; + when Decoded_Emulate => + sp <= sp - 1; + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto 0) <= pc + 1; + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= (others => '0'); + pc(9 downto 5) <= unsigned(opcode(4 downto 0)); + when Decoded_AddSP => + memAAddr <= sp; + memBAddr <= sp+spOffset; + state <= State_AddSP; + when Decoded_Break => + report "Break instruction encountered" severity failure; + break <= '1'; + when Decoded_PushSP => + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + sp <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto minAddrBit) <= sp; + when Decoded_PopPC => + pc <= memARead(maxAddrBit downto 0); + sp <= sp + 1; + state <= State_Resync; + when Decoded_Add => + sp <= sp + 1; + state <= State_Add; + when Decoded_Or => + sp <= sp + 1; + state <= State_Or; + when Decoded_And => + sp <= sp + 1; + state <= State_And; + when Decoded_Load => + if (memARead(ioBit)='1') then + out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); + out_mem_readEnable <= '1'; + state <= State_ReadIO; + else + memAAddr <= memARead(maxAddrBit downto minAddrBit); + end if; + when Decoded_Not => + memAAddr <= sp(maxAddrBit downto minAddrBit); + memAWriteEnable <= '1'; + memAWrite <= not memARead; + when Decoded_Flip => + memAAddr <= sp(maxAddrBit downto minAddrBit); + memAWriteEnable <= '1'; + for i in 0 to wordSize-1 loop + memAWrite(i) <= memARead(wordSize-1-i); + end loop; + when Decoded_Store => + memBAddr <= sp + 1; + sp <= sp + 1; + if (memARead(ioBit)='1') then + state <= State_WriteIO; + else + state <= State_Store; + end if; + when Decoded_PopSP => + sp <= memARead(maxAddrBit downto minAddrBit); + state <= State_Resync; + when Decoded_Nop => + memAAddr <= sp; + when others => + null; + end case; + when State_ReadIO => + if (in_mem_busy = '0') then + state <= State_Fetch; + memAWriteEnable <= '1'; + memAWrite <= unsigned(mem_read); + end if; + when State_WriteIO => + sp <= sp + 1; + out_mem_writeEnable <= '1'; + out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); + mem_write <= std_logic_vector(memBRead); + state <= State_WriteIODone; + when State_WriteIODone => + if (in_mem_busy = '0') then + state <= State_Resync; + end if; + when State_Fetch => + -- We need to resync. During the *next* cycle + -- we'll fetch the opcode @ pc and thus it will + -- be available for State_Execute the cycle after + -- next + memBAddr <= pc(maxAddrBit downto minAddrBit); + state <= State_FetchNext; + when State_FetchNext => + -- at this point memARead contains the value that is either + -- from the top of stack or should be copied to the top of the stack + memAWriteEnable <= '1'; + memAWrite <= memARead; + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Decode; + when State_Decode => + -- during the State_Execute cycle we'll be fetching SP+1 + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Execute; + when State_Store => + sp <= sp + 1; + memAWriteEnable <= '1'; + memAAddr <= memARead(maxAddrBit downto minAddrBit); + memAWrite <= memBRead; + state <= State_Resync; + when State_AddSP => + state <= State_Add; + when State_Add => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead + memBRead; + state <= State_Fetch; + when State_Or => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead or memBRead; + state <= State_Fetch; + when State_Resync => + memAAddr <= sp; + state <= State_Fetch; + when State_And => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead and memBRead; + state <= State_Fetch; + when others => + null; + end case; + + end if; + end process; -- cgit v1.1 From 30faee20f811215e6d53ca2434119aa5cd059feb Mon Sep 17 00:00:00 2001 From: oharboe Date: Thu, 1 May 2008 08:20:02 +0000 Subject: work in progress. --- zpu/hdl/zpu4/src/zpu_core_wip.vhd | 948 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 948 insertions(+) create mode 100644 zpu/hdl/zpu4/src/zpu_core_wip.vhd diff --git a/zpu/hdl/zpu4/src/zpu_core_wip.vhd b/zpu/hdl/zpu4/src/zpu_core_wip.vhd new file mode 100644 index 0000000..882719d --- /dev/null +++ b/zpu/hdl/zpu4/src/zpu_core_wip.vhd @@ -0,0 +1,948 @@ + +-- Company: ZPU4 generic memory interface CPU +-- Engineer: Øyvind Harboe + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.STD_LOGIC_arith.ALL; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + + + + + +entity zpu_core is + Port ( clk : in std_logic; + areset : in std_logic; + enable : in std_logic; + mem_req : out std_logic; + mem_we : out std_logic; + mem_ack : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + interrupt : in std_logic; + break : out std_logic; + zpu_status : out std_logic_vector(63 downto 0)); +end zpu_core; + +architecture behave of zpu_core is + +type InsnType is +( +State_AddTop, +State_Dup, +State_DupStackB, +State_Pop, +State_Popdown, +State_Add, +State_Or, +State_And, +State_Store, +State_AddSP, +State_Shift, +State_Nop, +State_Im, +State_LoadSP, +State_StoreSP, +State_Emulate, +State_Load, +State_PushPC, +State_PushSP, +State_PopPC, +State_PopPCRel, +State_Not, +State_Flip, +State_PopSP, +State_Neqbranch, +State_Eq, +State_Loadb, +State_Mult, +State_Lessthan, +State_Lessthanorequal, +State_Ulessthanorequal, +State_Ulessthan, +State_Pushspadd, +State_Call, +State_Callpcrel, +State_Sub, +State_Break, +State_Storeb, +State_Interrupt, +State_InsnFetch +); + +type StateType is +( +State_Idle, -- using first state first on the list out of paranoia +State_Load2, +State_Popped, +State_LoadSP2, +State_LoadSP3, +State_AddSP2, +State_Fetch, +State_Execute, +State_Decode, +State_Decode2, +State_Resync, + +State_StoreSP2, +State_Resync2, +State_Resync3, +State_Loadb2, +State_Storeb2, +State_Mult2, +State_Mult3, +State_Mult5, +State_Mult6, +State_Mult4, +State_BinaryOpResult +); + + +signal pc : std_logic_vector(maxAddrBitIncIO downto 0); +signal sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal incSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal incIncSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal decSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal stackA : std_logic_vector(wordSize-1 downto 0); +signal binaryOpResult : std_logic_vector(wordSize-1 downto 0); +signal multResult2 : std_logic_vector(wordSize-1 downto 0); +signal multResult3 : std_logic_vector(wordSize-1 downto 0); +signal multResult : std_logic_vector(wordSize-1 downto 0); +signal multA : std_logic_vector(wordSize-1 downto 0); +signal multB : std_logic_vector(wordSize-1 downto 0); +signal stackB : std_logic_vector(wordSize-1 downto 0); +signal idim_flag : std_logic; +signal busy : std_logic; +signal mem_readEnable : std_logic; +signal mem_addr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal mem_delayAddr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal mem_delayReadEnable : std_logic; +signal mem_busy : std_logic; +signal decodeWord : std_logic_vector(wordSize-1 downto 0); + + +signal state : StateType; +signal insn : InsnType; +type InsnArray is array(0 to wordBytes-1) of InsnType; +signal decodedOpcode : InsnArray; + +type OpcodeArray is array(0 to wordBytes-1) of std_logic_vector(7 downto 0); + +signal opcode : OpcodeArray; + + + + +signal begin_inst : std_logic; +signal trace_opcode : std_logic_vector(7 downto 0); +signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); +signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); +signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); + +signal out_mem_req : std_logic; + +signal inInterrupt : std_logic; + +-- state machine. + +begin + + zpu_status(maxAddrBitIncIO downto 0) <= trace_pc; + zpu_status(31) <= '1'; + zpu_status(39 downto 32) <= trace_opcode; + zpu_status(40) <= '1' when (state = State_Idle) else '0'; + zpu_status(62) <= '1'; + + traceFileGenerate: + if Generate_Trace generate + trace_file: trace port map ( + clk => clk, + begin_inst => begin_inst, + pc => trace_pc, + opcode => trace_opcode, + sp => trace_sp, + memA => trace_topOfStack, + memB => trace_topOfStackB, + busy => busy, + intsp => (others => 'U') + ); + end generate; + + + -- the memory subsystem will tell us one cycle later whether or + -- not it is busy + out_mem_addr(maxAddrBitIncIO downto minAddrBit) <= mem_addr; + out_mem_addr(minAddrBit-1 downto 0) <= (others => '0'); + mem_req <= out_mem_req; + + incSp <= sp + 1; + incIncSp <= sp + 2; + decSp <= sp - 1; + + mem_busy <= out_mem_req and not mem_ack; -- '1' when the memory is busy + + opcodeControl: + process(clk, areset) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + variable spOffset : std_logic_vector(4 downto 0); + variable tSpOffset : std_logic_vector(4 downto 0); + variable nextPC : std_logic_vector(maxAddrBitIncIO downto 0); + variable tNextState : InsnType; + variable tDecodedOpcode : InsnArray; + variable tMultResult : std_logic_vector(wordSize*2-1 downto 0); + begin + if areset = '1' then + state <= State_Idle; + break <= '0'; + sp <= spStart(maxAddrBitIncIO downto minAddrBit); + + pc <= (others => '0'); + idim_flag <= '0'; + begin_inst <= '0'; + mem_we <= '0'; + multA <= (others => '0'); + multB <= (others => '0'); + mem_writeMask <= (others => '1'); + out_mem_req <= '0'; + mem_addr <= (others => DontCareValue); + mem_write <= (others => DontCareValue); + inInterrupt <= '0'; + elsif (clk'event and clk = '1') then + -- we must multiply unconditionally to get pipelined multiplication + tMultResult := multA * multB; + multResult3 <= multResult2; + multResult2 <= multResult; + multResult <= tMultResult(wordSize-1 downto 0); + + + spOffset(4):=not opcode(conv_integer(pc(byteBits-1 downto 0)))(4); + spOffset(3 downto 0):=opcode(conv_integer(pc(byteBits-1 downto 0)))(3 downto 0); + nextPC := pc + 1; + + -- prepare trace snapshot + trace_opcode <= opcode(conv_integer(pc(byteBits-1 downto 0))); + trace_pc <= pc; + trace_sp <= sp; + trace_topOfStack <= stackA; + trace_topOfStackB <= stackB; + begin_inst <= '0'; + + -- we terminate the requeset as soon as we get acknowledge + if mem_ack = '1' then + out_mem_req <= '0'; + mem_we <= '0'; + end if; + + if interrupt='0' then + inInterrupt <= '0'; -- no longer in an interrupt + end if; + + case state is + when State_Idle => + if enable='1' then + state <= State_Resync; + end if; + -- Initial state of ZPU, fetch top of stack + first instruction + when State_Resync => + if mem_busy='0' then + mem_addr <= sp; + out_mem_req <= '1'; + state <= State_Resync2; + end if; + when State_Resync2 => + if mem_busy='0' then + stackA <= mem_read; + mem_addr <= incSp; + out_mem_req <= '1'; + state <= State_Resync3; + end if; + when State_Resync3 => + if mem_busy='0' then + stackB <= mem_read; + mem_addr <= pc(maxAddrBitIncIO downto minAddrBit); + out_mem_req <= '1'; + state <= State_Decode; + end if; + when State_Decode => + if mem_busy='0' then + decodeWord <= mem_read; + state <= State_Decode2; + end if; + when State_Decode2 => + -- decode 4 instructions in parallel + for i in 0 to wordBytes-1 loop + tOpcode := decodeWord((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8); + + tSpOffset(4):=not tOpcode(4); + tSpOffset(3 downto 0):=tOpcode(3 downto 0); + + opcode(i) <= tOpcode; + if (tOpcode(7 downto 7)=OpCode_Im) then + tNextState:=State_Im; + elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then + if tSpOffset = 0 then + tNextState := State_Pop; + elsif tSpOffset=1 then + tNextState := State_PopDown; + else + tNextState :=State_StoreSP; + end if; + elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then + if tSpOffset = 0 then + tNextState :=State_Dup; + elsif tSpOffset = 1 then + tNextState :=State_DupStackB; + else + tNextState :=State_LoadSP; + end if; + elsif (tOpcode(7 downto 5)=OpCode_Emulate) then + tNextState :=State_Emulate; + if tOpcode(5 downto 0)=OpCode_Neqbranch then + tNextState :=State_Neqbranch; + elsif tOpcode(5 downto 0)=OpCode_Eq then + tNextState :=State_Eq; + elsif tOpcode(5 downto 0)=OpCode_Lessthan then + tNextState :=State_Lessthan; + elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then + --tNextState :=State_Lessthanorequal; + elsif tOpcode(5 downto 0)=OpCode_Ulessthan then + tNextState :=State_Ulessthan; + elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then + --tNextState :=State_Ulessthanorequal; + elsif tOpcode(5 downto 0)=OpCode_Loadb then + tNextState :=State_Loadb; + elsif tOpcode(5 downto 0)=OpCode_Mult then + tNextState :=State_Mult; + elsif tOpcode(5 downto 0)=OpCode_Storeb then + tNextState :=State_Storeb; + elsif tOpcode(5 downto 0)=OpCode_Pushspadd then + tNextState :=State_Pushspadd; + elsif tOpcode(5 downto 0)=OpCode_Callpcrel then + tNextState :=State_Callpcrel; + elsif tOpcode(5 downto 0)=OpCode_Call then + --tNextState :=State_Call; + elsif tOpcode(5 downto 0)=OpCode_Sub then + tNextState :=State_Sub; + elsif tOpcode(5 downto 0)=OpCode_PopPCRel then + --tNextState :=State_PopPCRel; + end if; + elsif (tOpcode(7 downto 4)=OpCode_AddSP) then + if tSpOffset = 0 then + tNextState := State_Shift; + elsif tSpOffset = 1 then + tNextState := State_AddTop; + else + tNextState :=State_AddSP; + end if; + else + case tOpcode(3 downto 0) is + when OpCode_Nop => + tNextState :=State_Nop; + when OpCode_PushSP => + tNextState :=State_PushSP; + when OpCode_PopPC => + tNextState :=State_PopPC; + when OpCode_Add => + tNextState :=State_Add; + when OpCode_Or => + tNextState :=State_Or; + when OpCode_And => + tNextState :=State_And; + when OpCode_Load => + tNextState :=State_Load; + when OpCode_Not => + tNextState :=State_Not; + when OpCode_Flip => + tNextState :=State_Flip; + when OpCode_Store => + tNextState :=State_Store; + when OpCode_PopSP => + tNextState :=State_PopSP; + when others => + tNextState := State_Break; + + end case; + end if; + tDecodedOpcode(i) := tNextState; + + end loop; + + insn <= tDecodedOpcode(conv_integer(pc(byteBits-1 downto 0))); + + -- once we wrap, we need to fetch + tDecodedOpcode(0) := State_InsnFetch; + + decodedOpcode <= tDecodedOpcode; + state <= State_Execute; + + + + -- Each instruction must: + -- + -- 1. set idim_flag + -- 2. increase pc if applicable + -- 3. set next state if appliable + -- 4. do it's operation + + when State_Execute => + insn <= decodedOpcode(conv_integer(nextPC(byteBits-1 downto 0))); + + case insn is + when State_InsnFetch => + state <= State_Fetch; + when State_Im => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '1'; + pc <= pc + 1; + + if idim_flag='1' then + stackA(wordSize-1 downto 7) <= stackA(wordSize-8 downto 0); + stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0); + else + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + stackB <= stackA; + sp <= decSp; + for i in wordSize-1 downto 7 loop + stackA(i) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6); + end loop; + stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0); + end if; + else + insn <= insn; + end if; + when State_StoreSP => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_StoreSP2; + + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= sp+spOffset; + mem_write <= stackA; + stackA <= stackB; + sp <= incSp; + else + insn <= insn; + end if; + + + when State_LoadSP => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_LoadSP2; + + sp <= decSp; + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + else + insn <= insn; + end if; + when State_Emulate => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + sp <= decSp; + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + stackB <= stackA; + + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= (others => '0'); + pc(9 downto 5) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(4 downto 0); + state <= State_Fetch; + else + insn <= insn; + end if; + when State_Callpcrel => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + + pc <= pc + stackA(maxAddrBitIncIO downto 0); + state <= State_Fetch; + else + insn <= insn; + end if; + when State_Call => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + pc <= stackA(maxAddrBitIncIO downto 0); + state <= State_Fetch; + else + insn <= insn; + end if; + when State_AddSP => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_AddSP2; + + out_mem_req <= '1'; + mem_addr <= sp+spOffset; + else + insn <= insn; + end if; + when State_PushSP => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackA <= (others => '0'); + stackA(maxAddrBitIncIO downto minAddrBit) <= sp; + stackB <= stackA; + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + else + insn <= insn; + end if; + when State_PopPC => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= stackA(maxAddrBitIncIO downto 0); + sp <= incSp; + + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + state <= State_Resync; + else + insn <= insn; + end if; + when State_PopPCRel => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= stackA(maxAddrBitIncIO downto 0) + pc; + sp <= incSp; + + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + state <= State_Resync; + else + insn <= insn; + end if; + when State_Add => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= stackA + stackB; + + out_mem_req <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + state <= State_Popped; + else + insn <= insn; + end if; + when State_Sub => + begin_inst <= '1'; + idim_flag <= '0'; + binaryOpResult <= stackB - stackA; + state <= State_BinaryOpResult; + when State_Pop => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + mem_addr <= incIncSp; + out_mem_req <= '1'; + sp <= incSp; + stackA <= stackB; + state <= State_Popped; + else + insn <= insn; + end if; + when State_PopDown => + if mem_busy='0' then + -- PopDown leaves top of stack unchanged + begin_inst <= '1'; + idim_flag <= '0'; + mem_addr <= incIncSp; + out_mem_req <= '1'; + sp <= incSp; + state <= State_Popped; + else + insn <= insn; + end if; + when State_Or => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= stackA or stackB; + out_mem_req <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + state <= State_Popped; + else + insn <= insn; + end if; + when State_And => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + stackA <= stackA and stackB; + out_mem_req <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + state <= State_Popped; + else + insn <= insn; + end if; + when State_Eq => + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA=stackB) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + when State_Ulessthan => + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA<=stackB) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + when State_Lessthan => + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (signed(stackA) + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (signed(stackA)<=signed(stackB)) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + when State_Load => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Load2; + + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + out_mem_req <= '1'; + else + insn <= insn; + end if; + + when State_Dup => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackB <= stackA; + mem_write <= stackB; + mem_addr <= incSp; + out_mem_req <= '1'; + mem_we <= '1'; + else + insn <= insn; + end if; + when State_DupStackB => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackA <= stackB; + stackB <= stackA; + mem_write <= stackB; + mem_addr <= incSp; + out_mem_req <= '1'; + mem_we <= '1'; + else + insn <= insn; + end if; + when State_Store => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + mem_write <= stackB; + out_mem_req <= '1'; + mem_we <= '1'; + sp <= incIncSp; + state <= State_Resync; + else + insn <= insn; + end if; + when State_PopSP => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + mem_write <= stackB; + mem_addr <= incSp; + out_mem_req <= '1'; + mem_we <= '1'; + sp <= stackA(maxAddrBitIncIO downto minAddrBit); + state <= State_Resync; + else + insn <= insn; + end if; + when State_Nop => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + when State_Not => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= not stackA; + when State_Flip => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + for i in 0 to wordSize-1 loop + stackA(i) <= stackA(wordSize-1-i); + end loop; + when State_AddTop => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= stackA + stackB; + when State_Shift => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0); + stackA(0) <= '0'; + when State_Pushspadd => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= (others => '0'); + stackA(maxAddrBitIncIO downto minAddrBit) <= stackA(maxAddrBitIncIO-minAddrBit downto 0)+sp; + when State_Neqbranch => + -- branches are almost always taken as they form loops + begin_inst <= '1'; + idim_flag <= '0'; + sp <= incIncSp; + if (stackB/=0) then + pc <= stackA(maxAddrBitIncIO downto 0) + pc; + else + pc <= pc + 1; + end if; + -- need to fetch stack again. + state <= State_Resync; + when State_Mult => + begin_inst <= '1'; + idim_flag <= '0'; + + multA <= stackA; + multB <= stackB; + state <= State_Mult2; + when State_Break => + report "Break instruction encountered" severity failure; + break <= '1'; + + when State_Loadb => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Loadb2; + + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + out_mem_req <= '1'; + else + insn <= insn; + end if; + when State_Storeb => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Storeb2; + + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + out_mem_req <= '1'; + else + insn <= insn; + end if; + + when others => +-- sp <= (others => DontCareValue); + report "Illegal instruction" severity failure; + break <= '1'; + end case; + + + when State_StoreSP2 => + if mem_busy='0' then + mem_addr <= incSp; + out_mem_req <= '1'; + state <= State_Popped; + end if; + when State_LoadSP2 => + if mem_busy='0' then + state <= State_LoadSP3; + out_mem_req <= '1'; + mem_addr <= sp+spOffset+1; + end if; + when State_LoadSP3 => + if mem_busy='0' then + pc <= pc + 1; + state <= State_Execute; + stackB <= stackA; + stackA <= mem_read; + end if; + when State_AddSP2 => + if mem_busy='0' then + pc <= pc + 1; + state <= State_Execute; + stackA <= stackA + mem_read; + end if; + when State_Load2 => + if mem_busy='0' then + stackA <= mem_read; + pc <= pc + 1; + state <= State_Execute; + end if; + when State_Loadb2 => + if mem_busy='0' then + stackA <= (others => '0'); + stackA(7 downto 0) <= mem_read(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8); + pc <= pc + 1; + state <= State_Execute; + end if; + when State_Storeb2 => + if mem_busy='0' then + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + mem_write <= mem_read; + mem_write(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8) <= stackB(7 downto 0) ; + out_mem_req <= '1'; + mem_we <= '1'; + pc <= pc + 1; + sp <= incIncSp; + state <= State_Resync; + end if; + when State_Fetch => + if mem_busy='0' then + if interrupt='1' and inInterrupt='0' and idim_flag='0' then + -- We got an interrupt + inInterrupt <= '1'; + + sp <= decSp; + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc; + stackB <= stackA; + + pc <= conv_std_logic_vector(32, maxAddrBitIncIo+1); -- interrupt address + + report "ZPU jumped to interrupt!" severity note; + else + mem_addr <= pc(maxAddrBitIncIO downto minAddrBit); + out_mem_req <= '1'; + state <= State_Decode; + end if; + end if; + when State_Mult2 => + state <= State_Mult3; + when State_Mult3 => + state <= State_Mult4; + when State_Mult4 => + state <= State_Mult5; + when State_Mult5 => + stackA <= multResult3; + state <= State_Mult6; + when State_Mult6 => + if mem_busy='0' then + out_mem_req <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + state <= State_Popped; + end if; + when State_BinaryOpResult => + if mem_busy='0' then + -- NB!!!! we know that the memory isn't busy at this point!!!! + out_mem_req <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + stackA <= binaryOpResult; + state <= State_Popped; + end if; + when State_Popped => + if mem_busy='0' then + pc <= pc + 1; + stackB <= mem_read; + state <= State_Execute; + end if; + when others => +-- sp <= (others => DontCareValue); + report "Illegal state" severity failure; + break <= '1'; + end case; + end if; + end process; + + + +end behave; -- cgit v1.1 From 0d7bc56eab8ff2d28aa9c4721a56b022385e13d9 Mon Sep 17 00:00:00 2001 From: oharboe Date: Thu, 1 May 2008 08:23:39 +0000 Subject: * zpu/hdl/zy1000 - ZPU implementation used on the zy1000 dev kit --- .settings/org.eclipse.core.resources.prefs | 3 + zpu/ChangeLog | 2 + zpu/hdl/zpu4/src/zpu_core_wip.vhd | 948 ----------------------------- zpu/hdl/zy2000/timer.vhd | 137 +++++ zpu/hdl/zy2000/trace.vhd | 84 +++ zpu/hdl/zy2000/txt_util.vhd | 587 ++++++++++++++++++ zpu/hdl/zy2000/zpu_config.vhd | 20 + zpu/hdl/zy2000/zpu_config_fast.vhd | 20 + zpu/hdl/zy2000/zpu_core.vhd | 948 +++++++++++++++++++++++++++++ zpu/hdl/zy2000/zpupkg.vhd | 168 +++++ 10 files changed, 1969 insertions(+), 948 deletions(-) create mode 100644 .settings/org.eclipse.core.resources.prefs delete mode 100644 zpu/hdl/zpu4/src/zpu_core_wip.vhd create mode 100644 zpu/hdl/zy2000/timer.vhd create mode 100644 zpu/hdl/zy2000/trace.vhd create mode 100644 zpu/hdl/zy2000/txt_util.vhd create mode 100644 zpu/hdl/zy2000/zpu_config.vhd create mode 100644 zpu/hdl/zy2000/zpu_config_fast.vhd create mode 100644 zpu/hdl/zy2000/zpu_core.vhd create mode 100644 zpu/hdl/zy2000/zpupkg.vhd diff --git a/.settings/org.eclipse.core.resources.prefs b/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 0000000..3f4041d --- /dev/null +++ b/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,3 @@ +#Wed Apr 30 20:08:12 CEST 2008 +eclipse.preferences.version=1 +encoding//zpu/hdl/zpu4/src/zpu_core_small_wip.vhd=UTF-8 diff --git a/zpu/ChangeLog b/zpu/ChangeLog index 249ff02..bb48431 100644 --- a/zpu/ChangeLog +++ b/zpu/ChangeLog @@ -1,3 +1,5 @@ +2008-05-01 Øyvind Harboe + * zpu/hdl/zy1000 - ZPU implementation used on the zy1000 dev kit 2008-04-17 Arnim Läuger * zpu/hdl/example_ghdl/ghdl_import.sh, zpu/hdl/example_ghdl/ghdl_make.sh, zpu/hdl/example_ghdl/ghdl_options.sh, zpu/hdl/example_ghdl/README: GHDL example diff --git a/zpu/hdl/zpu4/src/zpu_core_wip.vhd b/zpu/hdl/zpu4/src/zpu_core_wip.vhd deleted file mode 100644 index 882719d..0000000 --- a/zpu/hdl/zpu4/src/zpu_core_wip.vhd +++ /dev/null @@ -1,948 +0,0 @@ - --- Company: ZPU4 generic memory interface CPU --- Engineer: Øyvind Harboe - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -use IEEE.STD_LOGIC_arith.ALL; - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - - - - - -entity zpu_core is - Port ( clk : in std_logic; - areset : in std_logic; - enable : in std_logic; - mem_req : out std_logic; - mem_we : out std_logic; - mem_ack : in std_logic; - mem_read : in std_logic_vector(wordSize-1 downto 0); - mem_write : out std_logic_vector(wordSize-1 downto 0); - out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); - mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); - interrupt : in std_logic; - break : out std_logic; - zpu_status : out std_logic_vector(63 downto 0)); -end zpu_core; - -architecture behave of zpu_core is - -type InsnType is -( -State_AddTop, -State_Dup, -State_DupStackB, -State_Pop, -State_Popdown, -State_Add, -State_Or, -State_And, -State_Store, -State_AddSP, -State_Shift, -State_Nop, -State_Im, -State_LoadSP, -State_StoreSP, -State_Emulate, -State_Load, -State_PushPC, -State_PushSP, -State_PopPC, -State_PopPCRel, -State_Not, -State_Flip, -State_PopSP, -State_Neqbranch, -State_Eq, -State_Loadb, -State_Mult, -State_Lessthan, -State_Lessthanorequal, -State_Ulessthanorequal, -State_Ulessthan, -State_Pushspadd, -State_Call, -State_Callpcrel, -State_Sub, -State_Break, -State_Storeb, -State_Interrupt, -State_InsnFetch -); - -type StateType is -( -State_Idle, -- using first state first on the list out of paranoia -State_Load2, -State_Popped, -State_LoadSP2, -State_LoadSP3, -State_AddSP2, -State_Fetch, -State_Execute, -State_Decode, -State_Decode2, -State_Resync, - -State_StoreSP2, -State_Resync2, -State_Resync3, -State_Loadb2, -State_Storeb2, -State_Mult2, -State_Mult3, -State_Mult5, -State_Mult6, -State_Mult4, -State_BinaryOpResult -); - - -signal pc : std_logic_vector(maxAddrBitIncIO downto 0); -signal sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal incSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal incIncSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal decSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal stackA : std_logic_vector(wordSize-1 downto 0); -signal binaryOpResult : std_logic_vector(wordSize-1 downto 0); -signal multResult2 : std_logic_vector(wordSize-1 downto 0); -signal multResult3 : std_logic_vector(wordSize-1 downto 0); -signal multResult : std_logic_vector(wordSize-1 downto 0); -signal multA : std_logic_vector(wordSize-1 downto 0); -signal multB : std_logic_vector(wordSize-1 downto 0); -signal stackB : std_logic_vector(wordSize-1 downto 0); -signal idim_flag : std_logic; -signal busy : std_logic; -signal mem_readEnable : std_logic; -signal mem_addr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal mem_delayAddr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal mem_delayReadEnable : std_logic; -signal mem_busy : std_logic; -signal decodeWord : std_logic_vector(wordSize-1 downto 0); - - -signal state : StateType; -signal insn : InsnType; -type InsnArray is array(0 to wordBytes-1) of InsnType; -signal decodedOpcode : InsnArray; - -type OpcodeArray is array(0 to wordBytes-1) of std_logic_vector(7 downto 0); - -signal opcode : OpcodeArray; - - - - -signal begin_inst : std_logic; -signal trace_opcode : std_logic_vector(7 downto 0); -signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); -signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); -signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); - -signal out_mem_req : std_logic; - -signal inInterrupt : std_logic; - --- state machine. - -begin - - zpu_status(maxAddrBitIncIO downto 0) <= trace_pc; - zpu_status(31) <= '1'; - zpu_status(39 downto 32) <= trace_opcode; - zpu_status(40) <= '1' when (state = State_Idle) else '0'; - zpu_status(62) <= '1'; - - traceFileGenerate: - if Generate_Trace generate - trace_file: trace port map ( - clk => clk, - begin_inst => begin_inst, - pc => trace_pc, - opcode => trace_opcode, - sp => trace_sp, - memA => trace_topOfStack, - memB => trace_topOfStackB, - busy => busy, - intsp => (others => 'U') - ); - end generate; - - - -- the memory subsystem will tell us one cycle later whether or - -- not it is busy - out_mem_addr(maxAddrBitIncIO downto minAddrBit) <= mem_addr; - out_mem_addr(minAddrBit-1 downto 0) <= (others => '0'); - mem_req <= out_mem_req; - - incSp <= sp + 1; - incIncSp <= sp + 2; - decSp <= sp - 1; - - mem_busy <= out_mem_req and not mem_ack; -- '1' when the memory is busy - - opcodeControl: - process(clk, areset) - variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); - variable spOffset : std_logic_vector(4 downto 0); - variable tSpOffset : std_logic_vector(4 downto 0); - variable nextPC : std_logic_vector(maxAddrBitIncIO downto 0); - variable tNextState : InsnType; - variable tDecodedOpcode : InsnArray; - variable tMultResult : std_logic_vector(wordSize*2-1 downto 0); - begin - if areset = '1' then - state <= State_Idle; - break <= '0'; - sp <= spStart(maxAddrBitIncIO downto minAddrBit); - - pc <= (others => '0'); - idim_flag <= '0'; - begin_inst <= '0'; - mem_we <= '0'; - multA <= (others => '0'); - multB <= (others => '0'); - mem_writeMask <= (others => '1'); - out_mem_req <= '0'; - mem_addr <= (others => DontCareValue); - mem_write <= (others => DontCareValue); - inInterrupt <= '0'; - elsif (clk'event and clk = '1') then - -- we must multiply unconditionally to get pipelined multiplication - tMultResult := multA * multB; - multResult3 <= multResult2; - multResult2 <= multResult; - multResult <= tMultResult(wordSize-1 downto 0); - - - spOffset(4):=not opcode(conv_integer(pc(byteBits-1 downto 0)))(4); - spOffset(3 downto 0):=opcode(conv_integer(pc(byteBits-1 downto 0)))(3 downto 0); - nextPC := pc + 1; - - -- prepare trace snapshot - trace_opcode <= opcode(conv_integer(pc(byteBits-1 downto 0))); - trace_pc <= pc; - trace_sp <= sp; - trace_topOfStack <= stackA; - trace_topOfStackB <= stackB; - begin_inst <= '0'; - - -- we terminate the requeset as soon as we get acknowledge - if mem_ack = '1' then - out_mem_req <= '0'; - mem_we <= '0'; - end if; - - if interrupt='0' then - inInterrupt <= '0'; -- no longer in an interrupt - end if; - - case state is - when State_Idle => - if enable='1' then - state <= State_Resync; - end if; - -- Initial state of ZPU, fetch top of stack + first instruction - when State_Resync => - if mem_busy='0' then - mem_addr <= sp; - out_mem_req <= '1'; - state <= State_Resync2; - end if; - when State_Resync2 => - if mem_busy='0' then - stackA <= mem_read; - mem_addr <= incSp; - out_mem_req <= '1'; - state <= State_Resync3; - end if; - when State_Resync3 => - if mem_busy='0' then - stackB <= mem_read; - mem_addr <= pc(maxAddrBitIncIO downto minAddrBit); - out_mem_req <= '1'; - state <= State_Decode; - end if; - when State_Decode => - if mem_busy='0' then - decodeWord <= mem_read; - state <= State_Decode2; - end if; - when State_Decode2 => - -- decode 4 instructions in parallel - for i in 0 to wordBytes-1 loop - tOpcode := decodeWord((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8); - - tSpOffset(4):=not tOpcode(4); - tSpOffset(3 downto 0):=tOpcode(3 downto 0); - - opcode(i) <= tOpcode; - if (tOpcode(7 downto 7)=OpCode_Im) then - tNextState:=State_Im; - elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then - if tSpOffset = 0 then - tNextState := State_Pop; - elsif tSpOffset=1 then - tNextState := State_PopDown; - else - tNextState :=State_StoreSP; - end if; - elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then - if tSpOffset = 0 then - tNextState :=State_Dup; - elsif tSpOffset = 1 then - tNextState :=State_DupStackB; - else - tNextState :=State_LoadSP; - end if; - elsif (tOpcode(7 downto 5)=OpCode_Emulate) then - tNextState :=State_Emulate; - if tOpcode(5 downto 0)=OpCode_Neqbranch then - tNextState :=State_Neqbranch; - elsif tOpcode(5 downto 0)=OpCode_Eq then - tNextState :=State_Eq; - elsif tOpcode(5 downto 0)=OpCode_Lessthan then - tNextState :=State_Lessthan; - elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then - --tNextState :=State_Lessthanorequal; - elsif tOpcode(5 downto 0)=OpCode_Ulessthan then - tNextState :=State_Ulessthan; - elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then - --tNextState :=State_Ulessthanorequal; - elsif tOpcode(5 downto 0)=OpCode_Loadb then - tNextState :=State_Loadb; - elsif tOpcode(5 downto 0)=OpCode_Mult then - tNextState :=State_Mult; - elsif tOpcode(5 downto 0)=OpCode_Storeb then - tNextState :=State_Storeb; - elsif tOpcode(5 downto 0)=OpCode_Pushspadd then - tNextState :=State_Pushspadd; - elsif tOpcode(5 downto 0)=OpCode_Callpcrel then - tNextState :=State_Callpcrel; - elsif tOpcode(5 downto 0)=OpCode_Call then - --tNextState :=State_Call; - elsif tOpcode(5 downto 0)=OpCode_Sub then - tNextState :=State_Sub; - elsif tOpcode(5 downto 0)=OpCode_PopPCRel then - --tNextState :=State_PopPCRel; - end if; - elsif (tOpcode(7 downto 4)=OpCode_AddSP) then - if tSpOffset = 0 then - tNextState := State_Shift; - elsif tSpOffset = 1 then - tNextState := State_AddTop; - else - tNextState :=State_AddSP; - end if; - else - case tOpcode(3 downto 0) is - when OpCode_Nop => - tNextState :=State_Nop; - when OpCode_PushSP => - tNextState :=State_PushSP; - when OpCode_PopPC => - tNextState :=State_PopPC; - when OpCode_Add => - tNextState :=State_Add; - when OpCode_Or => - tNextState :=State_Or; - when OpCode_And => - tNextState :=State_And; - when OpCode_Load => - tNextState :=State_Load; - when OpCode_Not => - tNextState :=State_Not; - when OpCode_Flip => - tNextState :=State_Flip; - when OpCode_Store => - tNextState :=State_Store; - when OpCode_PopSP => - tNextState :=State_PopSP; - when others => - tNextState := State_Break; - - end case; - end if; - tDecodedOpcode(i) := tNextState; - - end loop; - - insn <= tDecodedOpcode(conv_integer(pc(byteBits-1 downto 0))); - - -- once we wrap, we need to fetch - tDecodedOpcode(0) := State_InsnFetch; - - decodedOpcode <= tDecodedOpcode; - state <= State_Execute; - - - - -- Each instruction must: - -- - -- 1. set idim_flag - -- 2. increase pc if applicable - -- 3. set next state if appliable - -- 4. do it's operation - - when State_Execute => - insn <= decodedOpcode(conv_integer(nextPC(byteBits-1 downto 0))); - - case insn is - when State_InsnFetch => - state <= State_Fetch; - when State_Im => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '1'; - pc <= pc + 1; - - if idim_flag='1' then - stackA(wordSize-1 downto 7) <= stackA(wordSize-8 downto 0); - stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0); - else - out_mem_req <= '1'; - mem_we <= '1'; - mem_addr <= incSp; - mem_write <= stackB; - stackB <= stackA; - sp <= decSp; - for i in wordSize-1 downto 7 loop - stackA(i) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6); - end loop; - stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0); - end if; - else - insn <= insn; - end if; - when State_StoreSP => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_StoreSP2; - - out_mem_req <= '1'; - mem_we <= '1'; - mem_addr <= sp+spOffset; - mem_write <= stackA; - stackA <= stackB; - sp <= incSp; - else - insn <= insn; - end if; - - - when State_LoadSP => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_LoadSP2; - - sp <= decSp; - out_mem_req <= '1'; - mem_we <= '1'; - mem_addr <= incSp; - mem_write <= stackB; - else - insn <= insn; - end if; - when State_Emulate => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - sp <= decSp; - out_mem_req <= '1'; - mem_we <= '1'; - mem_addr <= incSp; - mem_write <= stackB; - stackA <= (others => DontCareValue); - stackA(maxAddrBitIncIO downto 0) <= pc + 1; - stackB <= stackA; - - -- The emulate address is: - -- 98 7654 3210 - -- 0000 00aa aaa0 0000 - pc <= (others => '0'); - pc(9 downto 5) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(4 downto 0); - state <= State_Fetch; - else - insn <= insn; - end if; - when State_Callpcrel => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - stackA <= (others => DontCareValue); - stackA(maxAddrBitIncIO downto 0) <= pc + 1; - - pc <= pc + stackA(maxAddrBitIncIO downto 0); - state <= State_Fetch; - else - insn <= insn; - end if; - when State_Call => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - stackA <= (others => DontCareValue); - stackA(maxAddrBitIncIO downto 0) <= pc + 1; - pc <= stackA(maxAddrBitIncIO downto 0); - state <= State_Fetch; - else - insn <= insn; - end if; - when State_AddSP => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_AddSP2; - - out_mem_req <= '1'; - mem_addr <= sp+spOffset; - else - insn <= insn; - end if; - when State_PushSP => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - sp <= decSp; - stackA <= (others => '0'); - stackA(maxAddrBitIncIO downto minAddrBit) <= sp; - stackB <= stackA; - out_mem_req <= '1'; - mem_we <= '1'; - mem_addr <= incSp; - mem_write <= stackB; - else - insn <= insn; - end if; - when State_PopPC => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= stackA(maxAddrBitIncIO downto 0); - sp <= incSp; - - out_mem_req <= '1'; - mem_we <= '1'; - mem_addr <= incSp; - mem_write <= stackB; - state <= State_Resync; - else - insn <= insn; - end if; - when State_PopPCRel => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= stackA(maxAddrBitIncIO downto 0) + pc; - sp <= incSp; - - out_mem_req <= '1'; - mem_we <= '1'; - mem_addr <= incSp; - mem_write <= stackB; - state <= State_Resync; - else - insn <= insn; - end if; - when State_Add => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - stackA <= stackA + stackB; - - out_mem_req <= '1'; - mem_addr <= incIncSp; - sp <= incSp; - state <= State_Popped; - else - insn <= insn; - end if; - when State_Sub => - begin_inst <= '1'; - idim_flag <= '0'; - binaryOpResult <= stackB - stackA; - state <= State_BinaryOpResult; - when State_Pop => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - mem_addr <= incIncSp; - out_mem_req <= '1'; - sp <= incSp; - stackA <= stackB; - state <= State_Popped; - else - insn <= insn; - end if; - when State_PopDown => - if mem_busy='0' then - -- PopDown leaves top of stack unchanged - begin_inst <= '1'; - idim_flag <= '0'; - mem_addr <= incIncSp; - out_mem_req <= '1'; - sp <= incSp; - state <= State_Popped; - else - insn <= insn; - end if; - when State_Or => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - stackA <= stackA or stackB; - out_mem_req <= '1'; - mem_addr <= incIncSp; - sp <= incSp; - state <= State_Popped; - else - insn <= insn; - end if; - when State_And => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - - stackA <= stackA and stackB; - out_mem_req <= '1'; - mem_addr <= incIncSp; - sp <= incSp; - state <= State_Popped; - else - insn <= insn; - end if; - when State_Eq => - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (stackA=stackB) then - binaryOpResult(0) <= '1'; - end if; - state <= State_BinaryOpResult; - when State_Ulessthan => - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (stackA - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (stackA<=stackB) then - binaryOpResult(0) <= '1'; - end if; - state <= State_BinaryOpResult; - when State_Lessthan => - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (signed(stackA) - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (signed(stackA)<=signed(stackB)) then - binaryOpResult(0) <= '1'; - end if; - state <= State_BinaryOpResult; - when State_Load => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_Load2; - - mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); - out_mem_req <= '1'; - else - insn <= insn; - end if; - - when State_Dup => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - sp <= decSp; - stackB <= stackA; - mem_write <= stackB; - mem_addr <= incSp; - out_mem_req <= '1'; - mem_we <= '1'; - else - insn <= insn; - end if; - when State_DupStackB => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - sp <= decSp; - stackA <= stackB; - stackB <= stackA; - mem_write <= stackB; - mem_addr <= incSp; - out_mem_req <= '1'; - mem_we <= '1'; - else - insn <= insn; - end if; - when State_Store => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); - mem_write <= stackB; - out_mem_req <= '1'; - mem_we <= '1'; - sp <= incIncSp; - state <= State_Resync; - else - insn <= insn; - end if; - when State_PopSP => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - mem_write <= stackB; - mem_addr <= incSp; - out_mem_req <= '1'; - mem_we <= '1'; - sp <= stackA(maxAddrBitIncIO downto minAddrBit); - state <= State_Resync; - else - insn <= insn; - end if; - when State_Nop => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - when State_Not => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - stackA <= not stackA; - when State_Flip => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - for i in 0 to wordSize-1 loop - stackA(i) <= stackA(wordSize-1-i); - end loop; - when State_AddTop => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - stackA <= stackA + stackB; - when State_Shift => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0); - stackA(0) <= '0'; - when State_Pushspadd => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - stackA <= (others => '0'); - stackA(maxAddrBitIncIO downto minAddrBit) <= stackA(maxAddrBitIncIO-minAddrBit downto 0)+sp; - when State_Neqbranch => - -- branches are almost always taken as they form loops - begin_inst <= '1'; - idim_flag <= '0'; - sp <= incIncSp; - if (stackB/=0) then - pc <= stackA(maxAddrBitIncIO downto 0) + pc; - else - pc <= pc + 1; - end if; - -- need to fetch stack again. - state <= State_Resync; - when State_Mult => - begin_inst <= '1'; - idim_flag <= '0'; - - multA <= stackA; - multB <= stackB; - state <= State_Mult2; - when State_Break => - report "Break instruction encountered" severity failure; - break <= '1'; - - when State_Loadb => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_Loadb2; - - mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); - out_mem_req <= '1'; - else - insn <= insn; - end if; - when State_Storeb => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_Storeb2; - - mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); - out_mem_req <= '1'; - else - insn <= insn; - end if; - - when others => --- sp <= (others => DontCareValue); - report "Illegal instruction" severity failure; - break <= '1'; - end case; - - - when State_StoreSP2 => - if mem_busy='0' then - mem_addr <= incSp; - out_mem_req <= '1'; - state <= State_Popped; - end if; - when State_LoadSP2 => - if mem_busy='0' then - state <= State_LoadSP3; - out_mem_req <= '1'; - mem_addr <= sp+spOffset+1; - end if; - when State_LoadSP3 => - if mem_busy='0' then - pc <= pc + 1; - state <= State_Execute; - stackB <= stackA; - stackA <= mem_read; - end if; - when State_AddSP2 => - if mem_busy='0' then - pc <= pc + 1; - state <= State_Execute; - stackA <= stackA + mem_read; - end if; - when State_Load2 => - if mem_busy='0' then - stackA <= mem_read; - pc <= pc + 1; - state <= State_Execute; - end if; - when State_Loadb2 => - if mem_busy='0' then - stackA <= (others => '0'); - stackA(7 downto 0) <= mem_read(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8); - pc <= pc + 1; - state <= State_Execute; - end if; - when State_Storeb2 => - if mem_busy='0' then - mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); - mem_write <= mem_read; - mem_write(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8) <= stackB(7 downto 0) ; - out_mem_req <= '1'; - mem_we <= '1'; - pc <= pc + 1; - sp <= incIncSp; - state <= State_Resync; - end if; - when State_Fetch => - if mem_busy='0' then - if interrupt='1' and inInterrupt='0' and idim_flag='0' then - -- We got an interrupt - inInterrupt <= '1'; - - sp <= decSp; - out_mem_req <= '1'; - mem_we <= '1'; - mem_addr <= incSp; - mem_write <= stackB; - stackA <= (others => DontCareValue); - stackA(maxAddrBitIncIO downto 0) <= pc; - stackB <= stackA; - - pc <= conv_std_logic_vector(32, maxAddrBitIncIo+1); -- interrupt address - - report "ZPU jumped to interrupt!" severity note; - else - mem_addr <= pc(maxAddrBitIncIO downto minAddrBit); - out_mem_req <= '1'; - state <= State_Decode; - end if; - end if; - when State_Mult2 => - state <= State_Mult3; - when State_Mult3 => - state <= State_Mult4; - when State_Mult4 => - state <= State_Mult5; - when State_Mult5 => - stackA <= multResult3; - state <= State_Mult6; - when State_Mult6 => - if mem_busy='0' then - out_mem_req <= '1'; - mem_addr <= incIncSp; - sp <= incSp; - state <= State_Popped; - end if; - when State_BinaryOpResult => - if mem_busy='0' then - -- NB!!!! we know that the memory isn't busy at this point!!!! - out_mem_req <= '1'; - mem_addr <= incIncSp; - sp <= incSp; - stackA <= binaryOpResult; - state <= State_Popped; - end if; - when State_Popped => - if mem_busy='0' then - pc <= pc + 1; - stackB <= mem_read; - state <= State_Execute; - end if; - when others => --- sp <= (others => DontCareValue); - report "Illegal state" severity failure; - break <= '1'; - end case; - end if; - end process; - - - -end behave; diff --git a/zpu/hdl/zy2000/timer.vhd b/zpu/hdl/zy2000/timer.vhd new file mode 100644 index 0000000..bff82f2 --- /dev/null +++ b/zpu/hdl/zy2000/timer.vhd @@ -0,0 +1,137 @@ +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity timer is + port( + clk : in std_logic; + areset : in std_logic; + sample : in std_logic; + reset : in std_logic; + counter : out std_logic_vector(63 downto 0)); +end timer; + + +architecture behave of timer is + +signal c : std_logic_vector(1 to 7); + +signal cnt : std_logic_vector(63 downto 0); +signal cnt_smp : std_logic_vector(63 downto 0); + +begin + + counter <= cnt_smp; + + process(clk, areset) -- Carry generation + begin + if areset = '1' then + c <= "0000000"; + elsif (clk'event and clk = '1') then + if reset = '1' then + c <= "0000000"; + else + if cnt(7 downto 0) = "11111110" then + c(1) <= '1'; + else + c(1) <= '0'; + end if; + if cnt(15 downto 8) = "11111111" then + c(2) <= '1'; + else + c(2) <= '0'; + end if; + if cnt(23 downto 16) = "11111111" and c(2) = '1' then + c(3) <= '1'; + else + c(3) <= '0'; + end if; + if cnt(31 downto 24) = "11111111" and c(3) = '1' then + c(4) <= '1'; + else + c(4) <= '0'; + end if; + if cnt(39 downto 32) = "11111111" and c(4) = '1' then + c(5) <= '1'; + else + c(5) <= '0'; + end if; + if cnt(47 downto 40) = "11111111" and c(5) = '1' then + c(6) <= '1'; + else + c(6) <= '0'; + end if; + if cnt(55 downto 48) = "11111111" and c(6) = '1' then + c(7) <= '1'; + else + c(7) <= '0'; + end if; + end if; + end if; + end process; + + process(clk, areset) + begin + if areset = '1' then + cnt <= (others=>'0'); + elsif (clk'event and clk = '1') then + if reset = '1' then + cnt <= (others=>'0'); + else + cnt(7 downto 0) <= cnt(7 downto 0) + '1'; + if c(1) = '1' then + cnt(15 downto 8) <= cnt(15 downto 8) + '1'; + else + cnt(15 downto 8) <= cnt(15 downto 8); + end if; + if c(2) = '1' and c(1) = '1' then + cnt(23 downto 16) <= cnt(23 downto 16) + '1'; + else + cnt(23 downto 16) <= cnt(23 downto 16); + end if; + if c(3) = '1' and c(1) = '1' then + cnt(31 downto 24) <= cnt(31 downto 24) + '1'; + else + cnt(31 downto 24) <= cnt(31 downto 24); + end if; + if c(4) = '1' and c(1) = '1' then + cnt(39 downto 32) <= cnt(39 downto 32) + '1'; + else + cnt(39 downto 32) <= cnt(39 downto 32); + end if; + if c(5) = '1' and c(1) = '1' then + cnt(47 downto 40) <= cnt(47 downto 40) + '1'; + else + cnt(47 downto 40) <= cnt(47 downto 40); + end if; + if c(6) = '1' and c(1) = '1' then + cnt(55 downto 48) <= cnt(55 downto 48) + '1'; + else + cnt(55 downto 48) <= cnt(55 downto 48); + end if; + if c(7) = '1' and c(1) = '1' then + cnt(63 downto 56) <= cnt(63 downto 56) + '1'; + else + cnt(63 downto 56) <= cnt(63 downto 56); + end if; + end if; + end if; + end process; + + process(clk, areset) + begin + if areset = '1' then + cnt_smp <= (others=>'0'); + elsif (clk'event and clk = '1') then + if reset = '1' then + cnt_smp <= (others=>'0'); + elsif sample = '1' then + cnt_smp <= cnt; + else + cnt_smp <= cnt_smp; + end if; + end if; + end process; + +end behave; + diff --git a/zpu/hdl/zy2000/trace.vhd b/zpu/hdl/zy2000/trace.vhd new file mode 100644 index 0000000..bc5279f --- /dev/null +++ b/zpu/hdl/zy2000/trace.vhd @@ -0,0 +1,84 @@ +library ieee; +use ieee.std_logic_1164.all; +--use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +use std.textio.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; +use work.txt_util.all; + + +entity trace is + generic ( + log_file: string := "trace.txt" + ); + port( + clk : in std_logic; + begin_inst : in std_logic; + pc : in std_logic_vector(maxAddrBitIncIO downto 0); + opcode : in std_logic_vector(7 downto 0); + sp : in std_logic_vector(maxAddrBitIncIO downto 2); + memA : in std_logic_vector(wordSize-1 downto 0); + memB : in std_logic_vector(wordSize-1 downto 0); + busy : in std_logic; + intSp : in std_logic_vector(stack_bits-1 downto 0) + ); +end trace; + + +architecture behave of trace is + + +file l_file : TEXT open write_mode is log_file; + + +begin + + +-- write data and control information to a file + +receive_data: process + +variable l: line; +variable t : std_logic_vector(wordSize-1 downto 0); +variable t2 : std_logic_vector(maxAddrBitIncIO downto 0); +variable counter : std_logic_vector(63 downto 0); + + + +begin + + t:= (others => '0'); + t2:= (others => '0'); + +counter := (others => '0'); + -- print header for the logfile + print(l_file, "#pc,opcode,sp,top_of_stack "); + print(l_file, "#----------"); + print(l_file, " "); + + wait until clk = '1'; + wait until clk = '0'; + + while true loop + + counter := counter + 1; + if begin_inst = '1' then + t(maxAddrBitIncIO downto 2):=sp; + t2:=pc; + print(l_file, "0x" & hstr(t2) & " 0x" & hstr(opcode) & " 0x" & hstr(t) & " 0x" & hstr(memA) & " 0x" & hstr(memB) & " 0x" & hstr(intSp) & " 0x" & hstr(counter)); + end if; + + wait until clk = '0'; + + end loop; + + end process receive_data; + + + +end behave; + diff --git a/zpu/hdl/zy2000/txt_util.vhd b/zpu/hdl/zy2000/txt_util.vhd new file mode 100644 index 0000000..d3bf01a --- /dev/null +++ b/zpu/hdl/zy2000/txt_util.vhd @@ -0,0 +1,587 @@ +library ieee; +use ieee.std_logic_1164.all; +use std.textio.all; + +library work; + +package txt_util is + + -- prints a message to the screen + procedure print(text: string); + + -- prints the message when active + -- useful for debug switches + procedure print(active: boolean; text: string); + + -- converts std_logic into a character + function chr(sl: std_logic) return character; + + -- converts std_logic into a string (1 to 1) + function str(sl: std_logic) return string; + + -- converts std_logic_vector into a string (binary base) + function str(slv: std_logic_vector) return string; + + -- converts boolean into a string + function str(b: boolean) return string; + + -- converts an integer into a single character + -- (can also be used for hex conversion and other bases) + function chr(int: integer) return character; + + -- converts integer into string using specified base + function str(int: integer; base: integer) return string; + + -- converts integer to string, using base 10 + function str(int: integer) return string; + + -- convert std_logic_vector into a string in hex format + function hstr(slv: std_logic_vector) return string; + + + -- functions to manipulate strings + ----------------------------------- + + -- convert a character to upper case + function to_upper(c: character) return character; + + -- convert a character to lower case + function to_lower(c: character) return character; + + -- convert a string to upper case + function to_upper(s: string) return string; + + -- convert a string to lower case + function to_lower(s: string) return string; + + + + -- functions to convert strings into other formats + -------------------------------------------------- + + -- converts a character into std_logic + function to_std_logic(c: character) return std_logic; + + -- converts a string into std_logic_vector + function to_std_logic_vector(s: string) return std_logic_vector; + + + + -- file I/O + ----------- + + -- read variable length string from input file + procedure str_read(file in_file: TEXT; + res_string: out string); + + -- print string to a file and start new line + procedure print(file out_file: TEXT; + new_string: in string); + + -- print character to a file and start new line + procedure print(file out_file: TEXT; + char: in character); + +end txt_util; + + + + +package body txt_util is + + + + + -- prints text to the screen + + procedure print(text: string) is + variable msg_line: line; + begin + write(msg_line, text); + writeline(output, msg_line); + end print; + + + + + -- prints text to the screen when active + + procedure print(active: boolean; text: string) is + begin + if active then + print(text); + end if; + end print; + + + -- converts std_logic into a character + + function chr(sl: std_logic) return character is + variable c: character; + begin + case sl is + when 'U' => c:= 'U'; + when 'X' => c:= 'X'; + when '0' => c:= '0'; + when '1' => c:= '1'; + when 'Z' => c:= 'Z'; + when 'W' => c:= 'W'; + when 'L' => c:= 'L'; + when 'H' => c:= 'H'; + when '-' => c:= '-'; + end case; + return c; + end chr; + + + + -- converts std_logic into a string (1 to 1) + + function str(sl: std_logic) return string is + variable s: string(1 to 1); + begin + s(1) := chr(sl); + return s; + end str; + + + + -- converts std_logic_vector into a string (binary base) + -- (this also takes care of the fact that the range of + -- a string is natural while a std_logic_vector may + -- have an integer range) + + function str(slv: std_logic_vector) return string is + variable result : string (1 to slv'length); + variable r : integer; + begin + r := 1; + for i in slv'range loop + result(r) := chr(slv(i)); + r := r + 1; + end loop; + return result; + end str; + + + function str(b: boolean) return string is + + begin + if b then + return "true"; + else + return "false"; + end if; + end str; + + + -- converts an integer into a character + -- for 0 to 9 the obvious mapping is used, higher + -- values are mapped to the characters A-Z + -- (this is usefull for systems with base > 10) + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function chr(int: integer) return character is + variable c: character; + begin + case int is + when 0 => c := '0'; + when 1 => c := '1'; + when 2 => c := '2'; + when 3 => c := '3'; + when 4 => c := '4'; + when 5 => c := '5'; + when 6 => c := '6'; + when 7 => c := '7'; + when 8 => c := '8'; + when 9 => c := '9'; + when 10 => c := 'A'; + when 11 => c := 'B'; + when 12 => c := 'C'; + when 13 => c := 'D'; + when 14 => c := 'E'; + when 15 => c := 'F'; + when 16 => c := 'G'; + when 17 => c := 'H'; + when 18 => c := 'I'; + when 19 => c := 'J'; + when 20 => c := 'K'; + when 21 => c := 'L'; + when 22 => c := 'M'; + when 23 => c := 'N'; + when 24 => c := 'O'; + when 25 => c := 'P'; + when 26 => c := 'Q'; + when 27 => c := 'R'; + when 28 => c := 'S'; + when 29 => c := 'T'; + when 30 => c := 'U'; + when 31 => c := 'V'; + when 32 => c := 'W'; + when 33 => c := 'X'; + when 34 => c := 'Y'; + when 35 => c := 'Z'; + when others => c := '?'; + end case; + return c; + end chr; + + + + -- convert integer to string using specified base + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function str(int: integer; base: integer) return string is + + variable temp: string(1 to 10); + variable num: integer; + variable abs_int: integer; + variable len: integer := 1; + variable power: integer := 1; + + begin + + -- bug fix for negative numbers + abs_int := abs(int); + + num := abs_int; + + while num >= base loop -- Determine how many + len := len + 1; -- characters required + num := num / base; -- to represent the + end loop ; -- number. + + for i in len downto 1 loop -- Convert the number to + temp(i) := chr(abs_int/power mod base); -- a string starting + power := power * base; -- with the right hand + end loop ; -- side. + + -- return result and add sign if required + if int < 0 then + return '-'& temp(1 to len); + else + return temp(1 to len); + end if; + + end str; + + + -- convert integer to string, using base 10 + function str(int: integer) return string is + + begin + + return str(int, 10) ; + + end str; + + + + -- converts a std_logic_vector into a hex string. + function hstr(slv: std_logic_vector) return string is + variable hexlen: integer; + variable longslv : std_logic_vector(67 downto 0) := (others => '0'); + variable hex : string(1 to 16); + variable fourbit : std_logic_vector(3 downto 0); + begin + hexlen := (slv'left+1)/4; + if (slv'left+1) mod 4 /= 0 then + hexlen := hexlen + 1; + end if; + longslv(slv'left downto 0) := slv; + for i in (hexlen -1) downto 0 loop + fourbit := longslv(((i*4)+3) downto (i*4)); + case fourbit is + when "0000" => hex(hexlen -I) := '0'; + when "0001" => hex(hexlen -I) := '1'; + when "0010" => hex(hexlen -I) := '2'; + when "0011" => hex(hexlen -I) := '3'; + when "0100" => hex(hexlen -I) := '4'; + when "0101" => hex(hexlen -I) := '5'; + when "0110" => hex(hexlen -I) := '6'; + when "0111" => hex(hexlen -I) := '7'; + when "1000" => hex(hexlen -I) := '8'; + when "1001" => hex(hexlen -I) := '9'; + when "1010" => hex(hexlen -I) := 'A'; + when "1011" => hex(hexlen -I) := 'B'; + when "1100" => hex(hexlen -I) := 'C'; + when "1101" => hex(hexlen -I) := 'D'; + when "1110" => hex(hexlen -I) := 'E'; + when "1111" => hex(hexlen -I) := 'F'; + when "ZZZZ" => hex(hexlen -I) := 'z'; + when "UUUU" => hex(hexlen -I) := 'u'; + when "XXXX" => hex(hexlen -I) := 'x'; + when others => hex(hexlen -I) := '?'; + end case; + end loop; + return hex(1 to hexlen); + end hstr; + + + + -- functions to manipulate strings + ----------------------------------- + + + -- convert a character to upper case + + function to_upper(c: character) return character is + + variable u: character; + + begin + + case c is + when 'a' => u := 'A'; + when 'b' => u := 'B'; + when 'c' => u := 'C'; + when 'd' => u := 'D'; + when 'e' => u := 'E'; + when 'f' => u := 'F'; + when 'g' => u := 'G'; + when 'h' => u := 'H'; + when 'i' => u := 'I'; + when 'j' => u := 'J'; + when 'k' => u := 'K'; + when 'l' => u := 'L'; + when 'm' => u := 'M'; + when 'n' => u := 'N'; + when 'o' => u := 'O'; + when 'p' => u := 'P'; + when 'q' => u := 'Q'; + when 'r' => u := 'R'; + when 's' => u := 'S'; + when 't' => u := 'T'; + when 'u' => u := 'U'; + when 'v' => u := 'V'; + when 'w' => u := 'W'; + when 'x' => u := 'X'; + when 'y' => u := 'Y'; + when 'z' => u := 'Z'; + when others => u := c; + end case; + + return u; + + end to_upper; + + + -- convert a character to lower case + + function to_lower(c: character) return character is + + variable l: character; + + begin + + case c is + when 'A' => l := 'a'; + when 'B' => l := 'b'; + when 'C' => l := 'c'; + when 'D' => l := 'd'; + when 'E' => l := 'e'; + when 'F' => l := 'f'; + when 'G' => l := 'g'; + when 'H' => l := 'h'; + when 'I' => l := 'i'; + when 'J' => l := 'j'; + when 'K' => l := 'k'; + when 'L' => l := 'l'; + when 'M' => l := 'm'; + when 'N' => l := 'n'; + when 'O' => l := 'o'; + when 'P' => l := 'p'; + when 'Q' => l := 'q'; + when 'R' => l := 'r'; + when 'S' => l := 's'; + when 'T' => l := 't'; + when 'U' => l := 'u'; + when 'V' => l := 'v'; + when 'W' => l := 'w'; + when 'X' => l := 'x'; + when 'Y' => l := 'y'; + when 'Z' => l := 'z'; + when others => l := c; + end case; + + return l; + + end to_lower; + + + + -- convert a string to upper case + + function to_upper(s: string) return string is + + variable uppercase: string (s'range); + + begin + + for i in s'range loop + uppercase(i):= to_upper(s(i)); + end loop; + return uppercase; + + end to_upper; + + + + -- convert a string to lower case + + function to_lower(s: string) return string is + + variable lowercase: string (s'range); + + begin + + for i in s'range loop + lowercase(i):= to_lower(s(i)); + end loop; + return lowercase; + + end to_lower; + + + +-- functions to convert strings into other types + + +-- converts a character into a std_logic + +function to_std_logic(c: character) return std_logic is + variable sl: std_logic; + begin + case c is + when 'U' => + sl := 'U'; + when 'X' => + sl := 'X'; + when '0' => + sl := '0'; + when '1' => + sl := '1'; + when 'Z' => + sl := 'Z'; + when 'W' => + sl := 'W'; + when 'L' => + sl := 'L'; + when 'H' => + sl := 'H'; + when '-' => + sl := '-'; + when others => + sl := 'X'; + end case; + return sl; + end to_std_logic; + + +-- converts a string into std_logic_vector + +function to_std_logic_vector(s: string) return std_logic_vector is + variable slv: std_logic_vector(s'high-s'low downto 0); + variable k: integer; +begin + k := s'high-s'low; + for i in s'range loop + slv(k) := to_std_logic(s(i)); + k := k - 1; + end loop; + return slv; +end to_std_logic_vector; + + + + + + +---------------- +-- file I/O -- +---------------- + + + +-- read variable length string from input file + +procedure str_read(file in_file: TEXT; + res_string: out string) is + + variable l: line; + variable c: character; + variable is_string: boolean; + + begin + + readline(in_file, l); + -- clear the contents of the result string + for i in res_string'range loop + res_string(i) := ' '; + end loop; + -- read all characters of the line, up to the length + -- of the results string + for i in res_string'range loop + read(l, c, is_string); + res_string(i) := c; + if not is_string then -- found end of line + exit; + end if; + end loop; + +end str_read; + + +-- print string to a file +procedure print(file out_file: TEXT; + new_string: in string) is + + variable l: line; + + begin + + write(l, new_string); + writeline(out_file, l); + +end print; + + +-- print character to a file and start new line +procedure print(file out_file: TEXT; + char: in character) is + + variable l: line; + + begin + + write(l, char); + writeline(out_file, l); + +end print; + + + +-- appends contents of a string to a file until line feed occurs +-- (LF is considered to be the end of the string) + +procedure str_write(file out_file: TEXT; + new_string: in string) is + begin + + for i in new_string'range loop + print(out_file, new_string(i)); + if new_string(i) = LF then -- end of string + exit; + end if; + end loop; + +end str_write; + + + + +end txt_util; + + + + diff --git a/zpu/hdl/zy2000/zpu_config.vhd b/zpu/hdl/zy2000/zpu_config.vhd new file mode 100644 index 0000000..61949c5 --- /dev/null +++ b/zpu/hdl/zy2000/zpu_config.vhd @@ -0,0 +1,20 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +package zpu_config is + -- generate trace output or not. + constant Generate_Trace : boolean := false; + constant wordPower : integer := 5; + -- during simulation, set this to '0' to get matching trace.txt + constant DontCareValue : std_logic := '0'; + -- Clock frequency in MHz. + constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"40"; + -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) + constant maxAddrBitIncIO : integer := 27; + + -- start byte address of stack. + -- point to top of RAM - 2*words + constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"1fffff8"; + +end zpu_config; diff --git a/zpu/hdl/zy2000/zpu_config_fast.vhd b/zpu/hdl/zy2000/zpu_config_fast.vhd new file mode 100644 index 0000000..61949c5 --- /dev/null +++ b/zpu/hdl/zy2000/zpu_config_fast.vhd @@ -0,0 +1,20 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +package zpu_config is + -- generate trace output or not. + constant Generate_Trace : boolean := false; + constant wordPower : integer := 5; + -- during simulation, set this to '0' to get matching trace.txt + constant DontCareValue : std_logic := '0'; + -- Clock frequency in MHz. + constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"40"; + -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) + constant maxAddrBitIncIO : integer := 27; + + -- start byte address of stack. + -- point to top of RAM - 2*words + constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"1fffff8"; + +end zpu_config; diff --git a/zpu/hdl/zy2000/zpu_core.vhd b/zpu/hdl/zy2000/zpu_core.vhd new file mode 100644 index 0000000..2450f14 --- /dev/null +++ b/zpu/hdl/zy2000/zpu_core.vhd @@ -0,0 +1,948 @@ + +-- Company: ZPU4 generic memory interface CPU +-- Engineer: Øyvind Harboe + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.STD_LOGIC_arith.ALL; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + + + + + +entity zpu_core is + Port ( clk : in std_logic; + areset : in std_logic; + enable : in std_logic; + mem_req : out std_logic; + mem_we : out std_logic; + mem_ack : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + interrupt : in std_logic; + break : out std_logic; + zpu_status : out std_logic_vector(63 downto 0)); +end zpu_core; + +architecture behave of zpu_core is + +type InsnType is +( +State_AddTop, +State_Dup, +State_DupStackB, +State_Pop, +State_Popdown, +State_Add, +State_Or, +State_And, +State_Store, +State_AddSP, +State_Shift, +State_Nop, +State_Im, +State_LoadSP, +State_StoreSP, +State_Emulate, +State_Load, +State_PushPC, +State_PushSP, +State_PopPC, +State_PopPCRel, +State_Not, +State_Flip, +State_PopSP, +State_Neqbranch, +State_Eq, +State_Loadb, +State_Mult, +State_Lessthan, +State_Lessthanorequal, +State_Ulessthanorequal, +State_Ulessthan, +State_Pushspadd, +State_Call, +State_Callpcrel, +State_Sub, +State_Break, +State_Storeb, +State_Interrupt, +State_InsnFetch +); + +type StateType is +( +State_Idle, -- using first state first on the list out of paranoia +State_Load2, +State_Popped, +State_LoadSP2, +State_LoadSP3, +State_AddSP2, +State_Fetch, +State_Execute, +State_Decode, +State_Decode2, +State_Resync, + +State_StoreSP2, +State_Resync2, +State_Resync3, +State_Loadb2, +State_Storeb2, +State_Mult2, +State_Mult3, +State_Mult5, +State_Mult6, +State_Mult4, +State_BinaryOpResult +); + + +signal pc : std_logic_vector(maxAddrBitIncIO downto 0); +signal sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal incSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal incIncSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal decSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal stackA : std_logic_vector(wordSize-1 downto 0); +signal binaryOpResult : std_logic_vector(wordSize-1 downto 0); +signal multResult2 : std_logic_vector(wordSize-1 downto 0); +signal multResult3 : std_logic_vector(wordSize-1 downto 0); +signal multResult : std_logic_vector(wordSize-1 downto 0); +signal multA : std_logic_vector(wordSize-1 downto 0); +signal multB : std_logic_vector(wordSize-1 downto 0); +signal stackB : std_logic_vector(wordSize-1 downto 0); +signal idim_flag : std_logic; +signal busy : std_logic; +signal mem_readEnable : std_logic; +signal mem_addr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal mem_delayAddr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal mem_delayReadEnable : std_logic; +signal mem_busy : std_logic; +signal decodeWord : std_logic_vector(wordSize-1 downto 0); + + +signal state : StateType; +signal insn : InsnType; +type InsnArray is array(0 to wordBytes-1) of InsnType; +signal decodedOpcode : InsnArray; + +type OpcodeArray is array(0 to wordBytes-1) of std_logic_vector(7 downto 0); + +signal opcode : OpcodeArray; + + + + +signal begin_inst : std_logic; +signal trace_opcode : std_logic_vector(7 downto 0); +signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); +signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); +signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); + +signal out_mem_req : std_logic; + +signal inInterrupt : std_logic; + +-- state machine. + +begin + + zpu_status(maxAddrBitIncIO downto 0) <= trace_pc; + zpu_status(31) <= '1'; + zpu_status(39 downto 32) <= trace_opcode; + zpu_status(40) <= '1' when (state = State_Idle) else '0'; + zpu_status(62) <= '1'; + + traceFileGenerate: + if Generate_Trace generate + trace_file: trace port map ( + clk => clk, + begin_inst => begin_inst, + pc => trace_pc, + opcode => trace_opcode, + sp => trace_sp, + memA => trace_topOfStack, + memB => trace_topOfStackB, + busy => busy, + intsp => (others => 'U') + ); + end generate; + + + -- the memory subsystem will tell us one cycle later whether or + -- not it is busy + out_mem_addr(maxAddrBitIncIO downto minAddrBit) <= mem_addr; + out_mem_addr(minAddrBit-1 downto 0) <= (others => '0'); + mem_req <= out_mem_req; + + incSp <= sp + 1; + incIncSp <= sp + 2; + decSp <= sp - 1; + + mem_busy <= out_mem_req and not mem_ack; -- '1' when the memory is busy + + opcodeControl: + process(clk, areset) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + variable spOffset : std_logic_vector(4 downto 0); + variable tSpOffset : std_logic_vector(4 downto 0); + variable nextPC : std_logic_vector(maxAddrBitIncIO downto 0); + variable tNextState : InsnType; + variable tDecodedOpcode : InsnArray; + variable tMultResult : std_logic_vector(wordSize*2-1 downto 0); + begin + if areset = '1' then + state <= State_Idle; + break <= '0'; + sp <= spStart(maxAddrBitIncIO downto minAddrBit); + + pc <= (others => '0'); + idim_flag <= '0'; + begin_inst <= '0'; + mem_we <= '0'; + multA <= (others => '0'); + multB <= (others => '0'); + mem_writeMask <= (others => '1'); + out_mem_req <= '0'; + mem_addr <= (others => DontCareValue); + mem_write <= (others => DontCareValue); + inInterrupt <= '0'; + elsif (clk'event and clk = '1') then + -- we must multiply unconditionally to get pipelined multiplication + tMultResult := multA * multB; + multResult3 <= multResult2; + multResult2 <= multResult; + multResult <= tMultResult(wordSize-1 downto 0); + + + spOffset(4):=not opcode(conv_integer(pc(byteBits-1 downto 0)))(4); + spOffset(3 downto 0):=opcode(conv_integer(pc(byteBits-1 downto 0)))(3 downto 0); + nextPC := pc + 1; + + -- prepare trace snapshot + trace_opcode <= opcode(conv_integer(pc(byteBits-1 downto 0))); + trace_pc <= pc; + trace_sp <= sp; + trace_topOfStack <= stackA; + trace_topOfStackB <= stackB; + begin_inst <= '0'; + + -- we terminate the requeset as soon as we get acknowledge + if mem_ack = '1' then + out_mem_req <= '0'; + mem_we <= '0'; + end if; + + if interrupt='0' then + inInterrupt <= '0'; -- no longer in an interrupt + end if; + + case state is + when State_Idle => + if enable='1' then + state <= State_Resync; + end if; + -- Initial state of ZPU, fetch top of stack + first instruction + when State_Resync => + if mem_busy='0' then + mem_addr <= sp; + out_mem_req <= '1'; + state <= State_Resync2; + end if; + when State_Resync2 => + if mem_busy='0' then + stackA <= mem_read; + mem_addr <= incSp; + out_mem_req <= '1'; + state <= State_Resync3; + end if; + when State_Resync3 => + if mem_busy='0' then + stackB <= mem_read; + mem_addr <= pc(maxAddrBitIncIO downto minAddrBit); + out_mem_req <= '1'; + state <= State_Decode; + end if; + when State_Decode => + if mem_busy='0' then + decodeWord <= mem_read; + state <= State_Decode2; + end if; + when State_Decode2 => + -- decode 4 instructions in parallel + for i in 0 to wordBytes-1 loop + tOpcode := decodeWord((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8); + + tSpOffset(4):=not tOpcode(4); + tSpOffset(3 downto 0):=tOpcode(3 downto 0); + + opcode(i) <= tOpcode; + if (tOpcode(7 downto 7)=OpCode_Im) then + tNextState:=State_Im; + elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then + if tSpOffset = 0 then + tNextState := State_Pop; + elsif tSpOffset=1 then + tNextState := State_PopDown; + else + tNextState :=State_StoreSP; + end if; + elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then + if tSpOffset = 0 then + tNextState :=State_Dup; + elsif tSpOffset = 1 then + tNextState :=State_DupStackB; + else + tNextState :=State_LoadSP; + end if; + elsif (tOpcode(7 downto 5)=OpCode_Emulate) then + tNextState :=State_Emulate; + if tOpcode(5 downto 0)=OpCode_Neqbranch then + tNextState :=State_Neqbranch; + elsif tOpcode(5 downto 0)=OpCode_Eq then + tNextState :=State_Eq; + elsif tOpcode(5 downto 0)=OpCode_Lessthan then + tNextState :=State_Lessthan; + elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then + --tNextState :=State_Lessthanorequal; + elsif tOpcode(5 downto 0)=OpCode_Ulessthan then + tNextState :=State_Ulessthan; + elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then + --tNextState :=State_Ulessthanorequal; + elsif tOpcode(5 downto 0)=OpCode_Loadb then + tNextState :=State_Loadb; + elsif tOpcode(5 downto 0)=OpCode_Mult then + tNextState :=State_Mult; + elsif tOpcode(5 downto 0)=OpCode_Storeb then + tNextState :=State_Storeb; + elsif tOpcode(5 downto 0)=OpCode_Pushspadd then + tNextState :=State_Pushspadd; + elsif tOpcode(5 downto 0)=OpCode_Callpcrel then + tNextState :=State_Callpcrel; + elsif tOpcode(5 downto 0)=OpCode_Call then + --tNextState :=State_Call; + elsif tOpcode(5 downto 0)=OpCode_Sub then + tNextState :=State_Sub; + elsif tOpcode(5 downto 0)=OpCode_PopPCRel then + --tNextState :=State_PopPCRel; + end if; + elsif (tOpcode(7 downto 4)=OpCode_AddSP) then + if tSpOffset = 0 then + tNextState := State_Shift; + elsif tSpOffset = 1 then + tNextState := State_AddTop; + else + tNextState :=State_AddSP; + end if; + else + case tOpcode(3 downto 0) is + when OpCode_Nop => + tNextState :=State_Nop; + when OpCode_PushSP => + tNextState :=State_PushSP; + when OpCode_PopPC => + tNextState :=State_PopPC; + when OpCode_Add => + tNextState :=State_Add; + when OpCode_Or => + tNextState :=State_Or; + when OpCode_And => + tNextState :=State_And; + when OpCode_Load => + tNextState :=State_Load; + when OpCode_Not => + tNextState :=State_Not; + when OpCode_Flip => + tNextState :=State_Flip; + when OpCode_Store => + tNextState :=State_Store; + when OpCode_PopSP => + tNextState :=State_PopSP; + when others => + tNextState := State_Break; + + end case; + end if; + tDecodedOpcode(i) := tNextState; + + end loop; + + insn <= tDecodedOpcode(conv_integer(pc(byteBits-1 downto 0))); + + -- once we wrap, we need to fetch + tDecodedOpcode(0) := State_InsnFetch; + + decodedOpcode <= tDecodedOpcode; + state <= State_Execute; + + + + -- Each instruction must: + -- + -- 1. set idim_flag + -- 2. increase pc if applicable + -- 3. set next state if appliable + -- 4. do it's operation + + when State_Execute => + insn <= decodedOpcode(conv_integer(nextPC(byteBits-1 downto 0))); + + case insn is + when State_InsnFetch => + state <= State_Fetch; + when State_Im => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '1'; + pc <= pc + 1; + + if idim_flag='1' then + stackA(wordSize-1 downto 7) <= stackA(wordSize-8 downto 0); + stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0); + else + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + stackB <= stackA; + sp <= decSp; + for i in wordSize-1 downto 7 loop + stackA(i) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6); + end loop; + stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0); + end if; + else + insn <= insn; + end if; + when State_StoreSP => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_StoreSP2; + + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= sp+spOffset; + mem_write <= stackA; + stackA <= stackB; + sp <= incSp; + else + insn <= insn; + end if; + + + when State_LoadSP => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_LoadSP2; + + sp <= decSp; + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + else + insn <= insn; + end if; + when State_Emulate => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + sp <= decSp; + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + stackB <= stackA; + + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= (others => '0'); + pc(9 downto 5) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(4 downto 0); + state <= State_Fetch; + else + insn <= insn; + end if; + when State_Callpcrel => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + + pc <= pc + stackA(maxAddrBitIncIO downto 0); + state <= State_Fetch; + else + insn <= insn; + end if; + when State_Call => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + pc <= stackA(maxAddrBitIncIO downto 0); + state <= State_Fetch; + else + insn <= insn; + end if; + when State_AddSP => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_AddSP2; + + out_mem_req <= '1'; + mem_addr <= sp+spOffset; + else + insn <= insn; + end if; + when State_PushSP => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackA <= (others => '0'); + stackA(maxAddrBitIncIO downto minAddrBit) <= sp; + stackB <= stackA; + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + else + insn <= insn; + end if; + when State_PopPC => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= stackA(maxAddrBitIncIO downto 0); + sp <= incSp; + + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + state <= State_Resync; + else + insn <= insn; + end if; + when State_PopPCRel => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= stackA(maxAddrBitIncIO downto 0) + pc; + sp <= incSp; + + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + state <= State_Resync; + else + insn <= insn; + end if; + when State_Add => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= stackA + stackB; + + out_mem_req <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + state <= State_Popped; + else + insn <= insn; + end if; + when State_Sub => + begin_inst <= '1'; + idim_flag <= '0'; + binaryOpResult <= stackB - stackA; + state <= State_BinaryOpResult; + when State_Pop => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + mem_addr <= incIncSp; + out_mem_req <= '1'; + sp <= incSp; + stackA <= stackB; + state <= State_Popped; + else + insn <= insn; + end if; + when State_PopDown => + if mem_busy='0' then + -- PopDown leaves top of stack unchanged + begin_inst <= '1'; + idim_flag <= '0'; + mem_addr <= incIncSp; + out_mem_req <= '1'; + sp <= incSp; + state <= State_Popped; + else + insn <= insn; + end if; + when State_Or => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= stackA or stackB; + out_mem_req <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + state <= State_Popped; + else + insn <= insn; + end if; + when State_And => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + stackA <= stackA and stackB; + out_mem_req <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + state <= State_Popped; + else + insn <= insn; + end if; + when State_Eq => + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA=stackB) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + when State_Ulessthan => + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA<=stackB) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + when State_Lessthan => + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (signed(stackA) + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (signed(stackA)<=signed(stackB)) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + when State_Load => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Load2; + + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + out_mem_req <= '1'; + else + insn <= insn; + end if; + + when State_Dup => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackB <= stackA; + mem_write <= stackB; + mem_addr <= incSp; + out_mem_req <= '1'; + mem_we <= '1'; + else + insn <= insn; + end if; + when State_DupStackB => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackA <= stackB; + stackB <= stackA; + mem_write <= stackB; + mem_addr <= incSp; + out_mem_req <= '1'; + mem_we <= '1'; + else + insn <= insn; + end if; + when State_Store => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + mem_write <= stackB; + out_mem_req <= '1'; + mem_we <= '1'; + sp <= incIncSp; + state <= State_Resync; + else + insn <= insn; + end if; + when State_PopSP => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + mem_write <= stackB; + mem_addr <= incSp; + out_mem_req <= '1'; + mem_we <= '1'; + sp <= stackA(maxAddrBitIncIO downto minAddrBit); + state <= State_Resync; + else + insn <= insn; + end if; + when State_Nop => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + when State_Not => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= not stackA; + when State_Flip => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + for i in 0 to wordSize-1 loop + stackA(i) <= stackA(wordSize-1-i); + end loop; + when State_AddTop => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= stackA + stackB; + when State_Shift => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0); + stackA(0) <= '0'; + when State_Pushspadd => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= (others => '0'); + stackA(maxAddrBitIncIO downto minAddrBit) <= stackA(maxAddrBitIncIO-minAddrBit downto 0)+sp; + when State_Neqbranch => + -- branches are almost always taken as they form loops + begin_inst <= '1'; + idim_flag <= '0'; + sp <= incIncSp; + if (stackB/=0) then + pc <= stackA(maxAddrBitIncIO downto 0) + pc; + else + pc <= pc + 1; + end if; + -- need to fetch stack again. + state <= State_Resync; + when State_Mult => + begin_inst <= '1'; + idim_flag <= '0'; + + multA <= stackA; + multB <= stackB; + state <= State_Mult2; + when State_Break => + report "Break instruction encountered" severity failure; + break <= '1'; + + when State_Loadb => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Loadb2; + + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + out_mem_req <= '1'; + else + insn <= insn; + end if; + when State_Storeb => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Storeb2; + + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + out_mem_req <= '1'; + else + insn <= insn; + end if; + + when others => +-- sp <= (others => DontCareValue); + report "Illegal instruction" severity failure; + break <= '1'; + end case; + + + when State_StoreSP2 => + if mem_busy='0' then + mem_addr <= incSp; + out_mem_req <= '1'; + state <= State_Popped; + end if; + when State_LoadSP2 => + if mem_busy='0' then + state <= State_LoadSP3; + out_mem_req <= '1'; + mem_addr <= sp+spOffset+1; + end if; + when State_LoadSP3 => + if mem_busy='0' then + pc <= pc + 1; + state <= State_Execute; + stackB <= stackA; + stackA <= mem_read; + end if; + when State_AddSP2 => + if mem_busy='0' then + pc <= pc + 1; + state <= State_Execute; + stackA <= stackA + mem_read; + end if; + when State_Load2 => + if mem_busy='0' then + stackA <= mem_read; + pc <= pc + 1; + state <= State_Execute; + end if; + when State_Loadb2 => + if mem_busy='0' then + stackA <= (others => '0'); + stackA(7 downto 0) <= mem_read(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8); + pc <= pc + 1; + state <= State_Execute; + end if; + when State_Storeb2 => + if mem_busy='0' then + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + mem_write <= mem_read; + mem_write(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8) <= stackB(7 downto 0) ; + out_mem_req <= '1'; + mem_we <= '1'; + pc <= pc + 1; + sp <= incIncSp; + state <= State_Resync; + end if; + when State_Fetch => + if mem_busy='0' then + if interrupt='1' and inInterrupt='0' and idim_flag='0' then + -- We got an interrupt + inInterrupt <= '1'; + + sp <= decSp; + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc; + stackB <= stackA; + + pc <= conv_std_logic_vector(32, maxAddrBitIncIo+1); -- interrupt address + + report "ZPU jumped to interrupt!" severity note; + else + mem_addr <= pc(maxAddrBitIncIO downto minAddrBit); + out_mem_req <= '1'; + state <= State_Decode; + end if; + end if; + when State_Mult2 => + state <= State_Mult3; + when State_Mult3 => + state <= State_Mult4; + when State_Mult4 => + state <= State_Mult5; + when State_Mult5 => + stackA <= multResult3; + state <= State_Mult6; + when State_Mult6 => + if mem_busy='0' then + out_mem_req <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + state <= State_Popped; + end if; + when State_BinaryOpResult => + if mem_busy='0' then + -- NB!!!! we know that the memory isn't busy at this point!!!! + out_mem_req <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + stackA <= binaryOpResult; + state <= State_Popped; + end if; + when State_Popped => + if mem_busy='0' then + pc <= pc + 1; + stackB <= mem_read; + state <= State_Execute; + end if; + when others => +-- sp <= (others => DontCareValue); + report "Illegal state" severity failure; + break <= '1'; + end case; + end if; + end process; + + + +end behave; diff --git a/zpu/hdl/zy2000/zpupkg.vhd b/zpu/hdl/zy2000/zpupkg.vhd new file mode 100644 index 0000000..1a01563 --- /dev/null +++ b/zpu/hdl/zy2000/zpupkg.vhd @@ -0,0 +1,168 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; + +library work; +use work.zpu_config.all; + +package zpupkg is + + -- This bit is set for read/writes to IO + -- FIX!!! eventually this should be set to wordSize-1 so as to + -- to make the address of IO independent of amount of memory + -- reserved for CPU. Requires trivial tweaks in toolchain/runtime + -- libraries. + + constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes + constant maxAddrBit : integer := maxAddrBitIncIO-1; + constant ioBit : integer := maxAddrBit+1; + constant wordSize : integer := 2**wordPower; + constant wordBytes : integer := wordSize/8; + constant minAddrBit : integer := byteBits; + -- configurable internal stack size. Probably going to be 16 after toolchain is done + constant stack_bits : integer := 5; + constant stack_size : integer := 2**stack_bits; + + component dualport_ram is + port (clk : in std_logic; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit); + memAWrite : in std_logic_vector(wordSize-1 downto 0); + memARead : out std_logic_vector(wordSize-1 downto 0); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit); + memBWrite : in std_logic_vector(wordSize-1 downto 0); + memBRead : out std_logic_vector(wordSize-1 downto 0)); + end component; + + component dram is + port (clk : in std_logic; + areset : in std_logic; + mem_writeEnable : in std_logic; + mem_readEnable : in std_logic; + mem_addr : in std_logic_vector(maxAddrBit downto 0); + mem_write : in std_logic_vector(wordSize-1 downto 0); + mem_read : out std_logic_vector(wordSize-1 downto 0); + mem_busy : out std_logic; + mem_writeMask : in std_logic_vector(wordBytes-1 downto 0)); + end component; + + + component trace is + port( + clk : in std_logic; + begin_inst : in std_logic; + pc : in std_logic_vector(maxAddrBitIncIO downto 0); + opcode : in std_logic_vector(7 downto 0); + sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit); + memA : in std_logic_vector(wordSize-1 downto 0); + memB : in std_logic_vector(wordSize-1 downto 0); + busy : in std_logic; + intSp : in std_logic_vector(stack_bits-1 downto 0) + ); + end component; + + component zpu_core is + port ( clk : in std_logic; + areset : in std_logic; + enable : in std_logic; + mem_req : out std_logic; + mem_we : out std_logic; + mem_ack : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + interrupt : in std_logic; + break : out std_logic; + zpu_status : out std_logic_vector(63 downto 0)); + end component; + + + + component timer is + port( + clk : in std_logic; + areset : in std_logic; + sample : in std_logic; + reset : in std_logic; + counter : out std_logic_vector(63 downto 0)); + end component; + + component zpuio is + port ( areset : in std_logic; + cpu_clk : in std_logic; + clk_status : in std_logic_vector(2 downto 0); + cpu_din : in std_logic_vector(15 downto 0); + cpu_a : in std_logic_vector(20 downto 0); + cpu_we : in std_logic_vector(1 downto 0); + cpu_re : in std_logic; + cpu_dout : inout std_logic_vector(15 downto 0)); + end component; + + + + + -- opcode decode constants + constant OpCode_Im : std_logic_vector(7 downto 7) := "1"; + constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010"; + constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011"; + constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001"; + constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001"; + constant OpCode_Short : std_logic_vector(7 downto 4) := "0000"; + + constant OpCode_Break : std_logic_vector(3 downto 0) := "0000"; + constant OpCode_Shiftleft: std_logic_vector(3 downto 0) := "0001"; + constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010"; + constant OpCode_PushInt : std_logic_vector(3 downto 0) := "0011"; + + constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100"; + constant OpCode_Add : std_logic_vector(3 downto 0) := "0101"; + constant OpCode_And : std_logic_vector(3 downto 0) := "0110"; + constant OpCode_Or : std_logic_vector(3 downto 0) := "0111"; + + constant OpCode_Load : std_logic_vector(3 downto 0) := "1000"; + constant OpCode_Not : std_logic_vector(3 downto 0) := "1001"; + constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010"; + constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011"; + + constant OpCode_Store : std_logic_vector(3 downto 0) := "1100"; + constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101"; + constant OpCode_Compare : std_logic_vector(3 downto 0) := "1110"; + constant OpCode_PopInt : std_logic_vector(3 downto 0) := "1111"; + + constant OpCode_Lessthan : std_logic_vector(5 downto 0) := conv_std_logic_vector(36, 6); + constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := conv_std_logic_vector(37, 6); + constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := conv_std_logic_vector(38, 6); + constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := conv_std_logic_vector(39, 6); + + constant OpCode_Swap : std_logic_vector(5 downto 0) := conv_std_logic_vector(40, 6); + constant OpCode_Mult : std_logic_vector(5 downto 0) := conv_std_logic_vector(41, 6); + + constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := conv_std_logic_vector(42, 6); + constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := conv_std_logic_vector(43, 6); + constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := conv_std_logic_vector(44, 6); + constant OpCode_Call : std_logic_vector(5 downto 0) := conv_std_logic_vector(45, 6); + + constant OpCode_Eq : std_logic_vector(5 downto 0) := conv_std_logic_vector(46, 6); + constant OpCode_Neq : std_logic_vector(5 downto 0) := conv_std_logic_vector(47, 6); + + constant OpCode_Sub : std_logic_vector(5 downto 0) := conv_std_logic_vector(49, 6); + constant OpCode_Loadb : std_logic_vector(5 downto 0) := conv_std_logic_vector(51, 6); + constant OpCode_Storeb : std_logic_vector(5 downto 0) := conv_std_logic_vector(52, 6); + + constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := conv_std_logic_vector(55, 6); + constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := conv_std_logic_vector(56, 6); + constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := conv_std_logic_vector(57, 6); + + constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := conv_std_logic_vector(61, 6); + constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := conv_std_logic_vector(62, 6); + constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := conv_std_logic_vector(63, 6); + + + + constant OpCode_Size : integer := 8; + + + +end zpupkg; -- cgit v1.1 From 47fd50b7c9654cf750e6c2024c9169a9eab2d6ad Mon Sep 17 00:00:00 2001 From: oharboe Date: Thu, 1 May 2008 08:44:59 +0000 Subject: wip --- zpu/hdl/zpu4/src/zpu_core_small_wip.vhd | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/zpu/hdl/zpu4/src/zpu_core_small_wip.vhd b/zpu/hdl/zpu4/src/zpu_core_small_wip.vhd index 63e02e4..8d87804 100644 --- a/zpu/hdl/zpu4/src/zpu_core_small_wip.vhd +++ b/zpu/hdl/zpu4/src/zpu_core_small_wip.vhd @@ -81,7 +81,9 @@ State_FetchNext, State_AddSP, State_ReadIODone, State_Decode, -State_Resync +State_Resync, +State_Interrupt + ); type DecodedOpcodeType is @@ -130,6 +132,7 @@ subtype index is integer range 0 to 3; signal tOpcode_sel : index; +signal inInterrupt : std_logic; @@ -262,6 +265,7 @@ begin out_mem_readEnable <= '0'; memAWrite <= (others => '0'); memBWrite <= (others => '0'); + inInterrupt <= '0'; elsif (clk'event and clk = '1') then memAWriteEnable <= '0'; memBWriteEnable <= '0'; @@ -284,6 +288,9 @@ begin decodedOpcode <= sampledDecodedOpcode; opcode <= sampledOpcode; + if interrupt='0' then + inInterrupt <= '0'; -- no longer in an interrupt + end if; case state is when State_Execute => @@ -309,6 +316,14 @@ begin idim_flag <= '0'; case decodedOpcode is + when Decoded_Interrupt => + sp <= sp - 1; + memAAddr <= sp - 1; + memAWriteEnable <= '1'; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBitIncIO downto 0) <= pc; + pc <= conv_std_logic_vector(32, maxAddrBitIncIo+1); -- interrupt address + report "ZPU jumped to interrupt!" severity note; when Decoded_Im => idim_flag <= '1'; memAWriteEnable <= '1'; @@ -436,6 +451,10 @@ begin memBAddr <= sp + 1; state <= State_Decode; when State_Decode => + if interrupt='1' and inInterrupt='0' and idim_flag='0' then + -- We got an interrupt, execute interrupt instead of next instruction + decodedOpcode <= Decoded_Interrupt; + end if; -- during the State_Execute cycle we'll be fetching SP+1 memAAddr <= sp; memBAddr <= sp + 1; -- cgit v1.1 From ed14271c9743490ebc4947ba7904adaa0d16e279 Mon Sep 17 00:00:00 2001 From: oharboe Date: Thu, 1 May 2008 18:49:10 +0000 Subject: wip for interrupts --- zpu/hdl/zpu4/test/interrupt/build.sh | 4 ++++ zpu/hdl/zpu4/test/interrupt/int.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+) create mode 100644 zpu/hdl/zpu4/test/interrupt/build.sh create mode 100644 zpu/hdl/zpu4/test/interrupt/int.c diff --git a/zpu/hdl/zpu4/test/interrupt/build.sh b/zpu/hdl/zpu4/test/interrupt/build.sh new file mode 100644 index 0000000..3d617e9 --- /dev/null +++ b/zpu/hdl/zpu4/test/interrupt/build.sh @@ -0,0 +1,4 @@ +zpu-elf-gcc -O3 -phi `pwd`/int.c -o int.elf -Wl,--relax -Wl,--gc-sections -g +zpu-elf-objdump --disassemble-all >int.dis int.elf +zpu-elf-objcopy -O binary int.elf int.bin +java -classpath ../../../../sw/simulator/zpusim.jar com.zylin.zpu.simulator.tools.MakeRam int.bin >int.ram diff --git a/zpu/hdl/zpu4/test/interrupt/int.c b/zpu/hdl/zpu4/test/interrupt/int.c new file mode 100644 index 0000000..2be6483 --- /dev/null +++ b/zpu/hdl/zpu4/test/interrupt/int.c @@ -0,0 +1,32 @@ +/* + * Shows usage of interrupts. Goes along with zpu_core_small_wip.vhd. + */ +#include + + +int counter; + +/* Example of single, fixed interval non-maskable, nested interrupt */ +void _zpu_interrupt(void) +{ + /* interrupts are enabled so we need to finish up quickly, + * lest we will get infinite recursion!*/ + counter++; +} + +int main(int argc, char **argv) +{ + int t; + t=counter; + for (;;) + { + if (t==counter) + { + puts("No interrupt\n"); + } else + { + puts("Got interrupt\n"); + } + } + +} -- cgit v1.1 From 1362bd4ace3ce962ed744a153e5f969154bb6682 Mon Sep 17 00:00:00 2001 From: oharboe Date: Sun, 4 May 2008 19:29:07 +0000 Subject: * Make code synthesize on Synopsis zpu/hdl/zpu4/src/zpu_core_small.vhd zpu/hdl/zpu4/src/io.vhd --- zpu/hdl/example/sim_small_fpga_top.vhd | 177 ++++++++++++++++++++++++++++++++ zpu/hdl/example/simzpu_small.do | 2 +- zpu/hdl/zpu4/src/io.vhd | 15 +-- zpu/hdl/zpu4/src/sim_small_fpga_top.vhd | 177 -------------------------------- zpu/hdl/zpu4/src/zpu_core_small.vhd | 25 ++++- zpu/hdl/zpu4/test/interrupt/int.c | 5 +- 6 files changed, 212 insertions(+), 189 deletions(-) create mode 100644 zpu/hdl/example/sim_small_fpga_top.vhd delete mode 100644 zpu/hdl/zpu4/src/sim_small_fpga_top.vhd diff --git a/zpu/hdl/example/sim_small_fpga_top.vhd b/zpu/hdl/example/sim_small_fpga_top.vhd new file mode 100644 index 0000000..5c05881 --- /dev/null +++ b/zpu/hdl/example/sim_small_fpga_top.vhd @@ -0,0 +1,177 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 20:15:31 04/14/05 +-- Design Name: +-- Module Name: fpga_top - behave +-- Project Name: +-- Target Device: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity fpga_top is +end fpga_top; + +architecture behave of fpga_top is + + +signal clk : std_logic; + +signal areset : std_logic; + + +component zpu_io is + generic ( + log_file: string := "log.txt" + ); + port( + clk : in std_logic; + areset : in std_logic; + busy : out std_logic; + writeEnable : in std_logic; + readEnable : in std_logic; + write : in std_logic_vector(wordSize-1 downto 0); + read : out std_logic_vector(wordSize-1 downto 0); + addr : in std_logic_vector(maxAddrBit downto minAddrBit) + ); +end component; + + + + + +signal mem_busy : std_logic; +signal mem_read : std_logic_vector(wordSize-1 downto 0); +signal mem_write : std_logic_vector(wordSize-1 downto 0); +signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); +signal mem_writeEnable : std_logic; +signal mem_readEnable : std_logic; +signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + +signal enable : std_logic; + +signal dram_mem_busy : std_logic; +signal dram_mem_read : std_logic_vector(wordSize-1 downto 0); +signal dram_mem_write : std_logic_vector(wordSize-1 downto 0); +signal dram_mem_writeEnable : std_logic; +signal dram_mem_readEnable : std_logic; +signal dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + + +signal io_busy : std_logic; + +signal io_mem_read : std_logic_vector(wordSize-1 downto 0); +signal io_mem_writeEnable : std_logic; +signal io_mem_readEnable : std_logic; + + +signal dram_ready : std_logic; +signal io_ready : std_logic; +signal io_reading : std_logic; + + +signal break : std_logic; + +begin + poweronreset: roc port map (O => areset); + + + + zpu: zpu_core port map ( + clk => clk , + areset => areset, + enable => enable, + in_mem_busy => mem_busy, + mem_read => mem_read, + mem_write => mem_write, + out_mem_addr => mem_addr, + out_mem_writeEnable => mem_writeEnable, + out_mem_readEnable => mem_readEnable, + mem_writeMask => mem_writeMask, + interrupt => '0', + break => break); + + + ioMap: zpu_io port map ( + clk => clk, + areset => areset, + busy => io_busy, + writeEnable => io_mem_writeEnable, + readEnable => io_mem_readEnable, + write => mem_write, + read => io_mem_read, + addr => mem_addr(maxAddrBit downto minAddrBit) + ); + + dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit); + dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit); + io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit); + io_mem_readEnable <= mem_readEnable and mem_addr(ioBit); + mem_busy <= io_busy; + + + + -- Memory reads either come from IO or DRAM. We need to pick the right one. + memorycontrol: + process(dram_mem_read, dram_ready, io_ready, io_mem_read) + begin + mem_read <= (others => 'U'); + if dram_ready='1' then + mem_read <= dram_mem_read; + end if; + + if io_ready='1' then + mem_read <= (others => '0'); + mem_read <= io_mem_read; + end if; + end process; + + + io_ready <= (io_reading or io_mem_readEnable) and not io_busy; + + memoryControlSync: + process(clk, areset) + begin + if areset = '1' then + enable <= '0'; + io_reading <= '0'; + dram_ready <= '0'; + elsif (clk'event and clk = '1') then + enable <= '1'; + io_reading <= io_busy or io_mem_readEnable; + dram_ready<=dram_mem_readEnable; + + end if; + end process; + + -- wiggle the clock @ 100MHz + clock : PROCESS + begin + clk <= '0'; + wait for 5 ns; + clk <= '1'; + wait for 5 ns; + end PROCESS clock; + + +end behave; diff --git a/zpu/hdl/example/simzpu_small.do b/zpu/hdl/example/simzpu_small.do index 1f8f358..095069a 100644 --- a/zpu/hdl/example/simzpu_small.do +++ b/zpu/hdl/example/simzpu_small.do @@ -10,7 +10,7 @@ vlib work vcom -93 -explicit zpu_config.vhd vcom -93 -explicit ../zpu4/src/zpupkg.vhd vcom -93 -explicit ../zpu4/src/txt_util.vhd -vcom -93 -explicit ../zpu4/src/sim_small_fpga_top.vhd +vcom -93 -explicit sim_small_fpga_top.vhd vcom -93 -explicit ../zpu4/src/zpu_core_small.vhd vcom -93 -explicit helloworld.vhd vcom -93 -explicit ../zpu4/src/timer.vhd diff --git a/zpu/hdl/zpu4/src/io.vhd b/zpu/hdl/zpu4/src/io.vhd index 7a2601f..9e65929 100644 --- a/zpu/hdl/zpu4/src/io.vhd +++ b/zpu/hdl/zpu4/src/io.vhd @@ -59,8 +59,9 @@ begin elsif (clk'event and clk = '1') then -- timer_we <= '0'; if writeEnable = '1' then - -- external interface - if addr=x"2028003" then + -- external interface (fixed address) + -- extend compare to avoid waring messages + if ("000" & addr)=x"2028003" then -- Write to UART -- report "" & character'image(conv_integer(memBint)) severity note; print(l_file, character'val(to_integer(unsigned(write)))); @@ -69,24 +70,26 @@ begin -- timer_we <= '1'; else print(l_file, character'val(to_integer(unsigned(write)))); - report "Illegal IO write" severity warning; + -- report "Illegal IO write" severity warning; end if; end if; read <= (others => '0'); if (readEnable = '1') then - if addr=x"1001" then + -- extend compare to avoid waring messages + if ("000" & addr)=x"0001001" then read <= (0=>'1', others => '0'); -- recieve empty elsif addr(12)='1' then read(7 downto 0) <= timer_read; elsif addr(11)='1' then read(7 downto 0) <= ZPU_Frequency; - elsif addr=x"2028003" then + -- extend compare to avoid waring messages + elsif ("000" & addr)=x"2028003" then read <= (others => '0'); else read <= (others => '0'); read(8) <= '1'; - report "Illegal IO read" severity warning; + -- report "Illegal IO read" severity warning; end if; end if; end if; diff --git a/zpu/hdl/zpu4/src/sim_small_fpga_top.vhd b/zpu/hdl/zpu4/src/sim_small_fpga_top.vhd deleted file mode 100644 index 5c05881..0000000 --- a/zpu/hdl/zpu4/src/sim_small_fpga_top.vhd +++ /dev/null @@ -1,177 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 20:15:31 04/14/05 --- Design Name: --- Module Name: fpga_top - behave --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - -entity fpga_top is -end fpga_top; - -architecture behave of fpga_top is - - -signal clk : std_logic; - -signal areset : std_logic; - - -component zpu_io is - generic ( - log_file: string := "log.txt" - ); - port( - clk : in std_logic; - areset : in std_logic; - busy : out std_logic; - writeEnable : in std_logic; - readEnable : in std_logic; - write : in std_logic_vector(wordSize-1 downto 0); - read : out std_logic_vector(wordSize-1 downto 0); - addr : in std_logic_vector(maxAddrBit downto minAddrBit) - ); -end component; - - - - - -signal mem_busy : std_logic; -signal mem_read : std_logic_vector(wordSize-1 downto 0); -signal mem_write : std_logic_vector(wordSize-1 downto 0); -signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); -signal mem_writeEnable : std_logic; -signal mem_readEnable : std_logic; -signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0); - -signal enable : std_logic; - -signal dram_mem_busy : std_logic; -signal dram_mem_read : std_logic_vector(wordSize-1 downto 0); -signal dram_mem_write : std_logic_vector(wordSize-1 downto 0); -signal dram_mem_writeEnable : std_logic; -signal dram_mem_readEnable : std_logic; -signal dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0); - - -signal io_busy : std_logic; - -signal io_mem_read : std_logic_vector(wordSize-1 downto 0); -signal io_mem_writeEnable : std_logic; -signal io_mem_readEnable : std_logic; - - -signal dram_ready : std_logic; -signal io_ready : std_logic; -signal io_reading : std_logic; - - -signal break : std_logic; - -begin - poweronreset: roc port map (O => areset); - - - - zpu: zpu_core port map ( - clk => clk , - areset => areset, - enable => enable, - in_mem_busy => mem_busy, - mem_read => mem_read, - mem_write => mem_write, - out_mem_addr => mem_addr, - out_mem_writeEnable => mem_writeEnable, - out_mem_readEnable => mem_readEnable, - mem_writeMask => mem_writeMask, - interrupt => '0', - break => break); - - - ioMap: zpu_io port map ( - clk => clk, - areset => areset, - busy => io_busy, - writeEnable => io_mem_writeEnable, - readEnable => io_mem_readEnable, - write => mem_write, - read => io_mem_read, - addr => mem_addr(maxAddrBit downto minAddrBit) - ); - - dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit); - dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit); - io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit); - io_mem_readEnable <= mem_readEnable and mem_addr(ioBit); - mem_busy <= io_busy; - - - - -- Memory reads either come from IO or DRAM. We need to pick the right one. - memorycontrol: - process(dram_mem_read, dram_ready, io_ready, io_mem_read) - begin - mem_read <= (others => 'U'); - if dram_ready='1' then - mem_read <= dram_mem_read; - end if; - - if io_ready='1' then - mem_read <= (others => '0'); - mem_read <= io_mem_read; - end if; - end process; - - - io_ready <= (io_reading or io_mem_readEnable) and not io_busy; - - memoryControlSync: - process(clk, areset) - begin - if areset = '1' then - enable <= '0'; - io_reading <= '0'; - dram_ready <= '0'; - elsif (clk'event and clk = '1') then - enable <= '1'; - io_reading <= io_busy or io_mem_readEnable; - dram_ready<=dram_mem_readEnable; - - end if; - end process; - - -- wiggle the clock @ 100MHz - clock : PROCESS - begin - clk <= '0'; - wait for 5 ns; - clk <= '1'; - wait for 5 ns; - end PROCESS clock; - - -end behave; diff --git a/zpu/hdl/zpu4/src/zpu_core_small.vhd b/zpu/hdl/zpu4/src/zpu_core_small.vhd index 0d734d2..9cda01c 100644 --- a/zpu/hdl/zpu4/src/zpu_core_small.vhd +++ b/zpu/hdl/zpu4/src/zpu_core_small.vhd @@ -125,6 +125,11 @@ signal memBAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); signal memBWrite_stdlogic : std_logic_vector(memBWrite'range); signal memBRead_stdlogic : std_logic_vector(memBRead'range); +-- debug +subtype index is integer range 0 to 3; +signal tOpcode_sel : index; + + begin traceFileGenerate: if Generate_Trace generate @@ -141,6 +146,8 @@ begin ); end generate; + -- not used in this design + mem_writeMask <= (others => '1'); memAAddr_stdlogic <= std_logic_vector(memAAddr(AddrBitBRAM_range)); memAWrite_stdlogic <= std_logic_vector(memAWrite); @@ -160,14 +167,23 @@ begin memARead <= unsigned(memARead_stdlogic); memBRead <= unsigned(memBRead_stdlogic); +tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0)); decodeControl: - process(memBRead, pc) + process(memBRead, pc,tOpcode_sel) variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); begin - tOpcode := std_logic_vector(memBRead((wordBytes-1-to_integer(pc(minAddrBit-1 downto 0))+1)*8-1 downto (wordBytes-1-to_integer(pc(minAddrBit-1 downto 0)))*8)); - + -- not worked with synopsys + -- tOpcode := std_logic_vector(memBRead((wordBytes-1-to_integer(pc(minAddrBit-1 downto 0))+1)*8-1 downto (wordBytes-1-to_integer(pc(minAddrBit-1 downto 0)))*8)); + -- use full case + case (tOpcode_sel) is + when 0 => tOpcode := std_logic_vector(memBRead(31 downto 24)); + when 1 => tOpcode := std_logic_vector(memBRead(23 downto 16)); + when 2 => tOpcode := std_logic_vector(memBRead(15 downto 8)); + when 3 => tOpcode := std_logic_vector(memBRead(7 downto 0)); + when others => tOpcode := std_logic_vector(memBRead(7 downto 0)); + end case; sampledOpcode <= tOpcode; if (tOpcode(7 downto 7)=OpCode_Im) then @@ -230,7 +246,8 @@ begin out_mem_readEnable <= '0'; memAWrite <= (others => '0'); memBWrite <= (others => '0'); - mem_writeMask <= (others => '1'); + -- avoid Latch in synopsys + -- mem_writeMask <= (others => '1'); elsif (clk'event and clk = '1') then memAWriteEnable <= '0'; memBWriteEnable <= '0'; diff --git a/zpu/hdl/zpu4/test/interrupt/int.c b/zpu/hdl/zpu4/test/interrupt/int.c index 2be6483..1b6ec01 100644 --- a/zpu/hdl/zpu4/test/interrupt/int.c +++ b/zpu/hdl/zpu4/test/interrupt/int.c @@ -6,7 +6,10 @@ int counter; -/* Example of single, fixed interval non-maskable, nested interrupt */ +/* Example of single, fixed interval non-maskable, nested interrupt. The interrupt signal is + * held high for enough cycles to guarantee that it will be noticed, i.e. longer than + * any io access + 4 cycles roughly. + */ void _zpu_interrupt(void) { /* interrupts are enabled so we need to finish up quickly, -- cgit v1.1 From b93ac48f3c323a11a97a39338897c521780a16b9 Mon Sep 17 00:00:00 2001 From: oharboe Date: Sun, 4 May 2008 20:44:27 +0000 Subject: * moved ZPU core files to seperate folder * deleted some obsolete files --- .settings/org.eclipse.core.resources.prefs | 4 +- zpu/ChangeLog | 5 +- zpu/hdl/example/simzpu_small.do | 4 +- zpu/hdl/example_ghdl/dmipssmalltrace_ghdl.sh | 26 + zpu/hdl/example_ghdl/dmipstrace_ghdl.sh | 25 + zpu/hdl/example_ghdl/simzpu_medium_ghdl.sh | 25 + zpu/hdl/example_medium/sim_fpga_top.vhd | 188 ++++++ zpu/hdl/example_medium/simzpu_medium.do | 28 + zpu/hdl/sim/dmipssmalltrace.do | 26 + zpu/hdl/sim/dmipstrace.do | 30 + zpu/hdl/zpu4/core/zpu_config.vhd | 16 + zpu/hdl/zpu4/core/zpu_core.vhd | 897 +++++++++++++++++++++++++++ zpu/hdl/zpu4/core/zpu_core_small.vhd | 464 ++++++++++++++ zpu/hdl/zpu4/core/zpu_core_small_wip.vhd | 497 +++++++++++++++ zpu/hdl/zpu4/core/zpupkg.vhd | 170 +++++ zpu/hdl/zpu4/src/dmipssmalltrace.do | 26 - zpu/hdl/zpu4/src/dmipssmalltrace_ghdl.sh | 26 - zpu/hdl/zpu4/src/dmipstrace.do | 30 - zpu/hdl/zpu4/src/dmipstrace_ghdl.sh | 25 - zpu/hdl/zpu4/src/log.txt | 380 ------------ zpu/hdl/zpu4/src/niltrace.vhd | 26 - zpu/hdl/zpu4/src/sim_fpga_top.vhd | 188 ------ zpu/hdl/zpu4/src/simzpu_medium.do | 28 - zpu/hdl/zpu4/src/simzpu_medium_ghdl.sh | 25 - zpu/hdl/zpu4/src/testlut.vhd | 114 ---- zpu/hdl/zpu4/src/zpu_config.vhd | 16 - zpu/hdl/zpu4/src/zpu_core.vhd | 897 --------------------------- zpu/hdl/zpu4/src/zpu_core_small.vhd | 464 -------------- zpu/hdl/zpu4/src/zpu_core_small_wip.vhd | 497 --------------- zpu/hdl/zpu4/src/zpupkg.vhd | 170 ----- 30 files changed, 2400 insertions(+), 2917 deletions(-) create mode 100644 zpu/hdl/example_ghdl/dmipssmalltrace_ghdl.sh create mode 100644 zpu/hdl/example_ghdl/dmipstrace_ghdl.sh create mode 100644 zpu/hdl/example_ghdl/simzpu_medium_ghdl.sh create mode 100644 zpu/hdl/example_medium/sim_fpga_top.vhd create mode 100644 zpu/hdl/example_medium/simzpu_medium.do create mode 100644 zpu/hdl/sim/dmipssmalltrace.do create mode 100644 zpu/hdl/sim/dmipstrace.do create mode 100644 zpu/hdl/zpu4/core/zpu_config.vhd create mode 100644 zpu/hdl/zpu4/core/zpu_core.vhd create mode 100644 zpu/hdl/zpu4/core/zpu_core_small.vhd create mode 100644 zpu/hdl/zpu4/core/zpu_core_small_wip.vhd create mode 100644 zpu/hdl/zpu4/core/zpupkg.vhd delete mode 100644 zpu/hdl/zpu4/src/dmipssmalltrace.do delete mode 100644 zpu/hdl/zpu4/src/dmipssmalltrace_ghdl.sh delete mode 100644 zpu/hdl/zpu4/src/dmipstrace.do delete mode 100644 zpu/hdl/zpu4/src/dmipstrace_ghdl.sh delete mode 100644 zpu/hdl/zpu4/src/log.txt delete mode 100644 zpu/hdl/zpu4/src/niltrace.vhd delete mode 100644 zpu/hdl/zpu4/src/sim_fpga_top.vhd delete mode 100644 zpu/hdl/zpu4/src/simzpu_medium.do delete mode 100644 zpu/hdl/zpu4/src/simzpu_medium_ghdl.sh delete mode 100644 zpu/hdl/zpu4/src/testlut.vhd delete mode 100644 zpu/hdl/zpu4/src/zpu_config.vhd delete mode 100644 zpu/hdl/zpu4/src/zpu_core.vhd delete mode 100644 zpu/hdl/zpu4/src/zpu_core_small.vhd delete mode 100644 zpu/hdl/zpu4/src/zpu_core_small_wip.vhd delete mode 100644 zpu/hdl/zpu4/src/zpupkg.vhd diff --git a/.settings/org.eclipse.core.resources.prefs b/.settings/org.eclipse.core.resources.prefs index 3f4041d..197db03 100644 --- a/.settings/org.eclipse.core.resources.prefs +++ b/.settings/org.eclipse.core.resources.prefs @@ -1,3 +1,3 @@ -#Wed Apr 30 20:08:12 CEST 2008 +#Sun May 04 22:37:24 CEST 2008 eclipse.preferences.version=1 -encoding//zpu/hdl/zpu4/src/zpu_core_small_wip.vhd=UTF-8 +encoding//zpu/hdl/zpu4/core/zpu_core_small_wip.vhd=UTF-8 diff --git a/zpu/ChangeLog b/zpu/ChangeLog index bb48431..3100fdb 100644 --- a/zpu/ChangeLog +++ b/zpu/ChangeLog @@ -1,5 +1,8 @@ +2008-05-04 Øyvind Harboe + * moved ZPU core files to seperate folder + * deleted some obsolete files 2008-05-01 Øyvind Harboe - * zpu/hdl/zy1000 - ZPU implementation used on the zy1000 dev kit + * zpu/hdl/zy2000 - ZPU implementation used on the zy2000 dev kit 2008-04-17 Arnim Läuger * zpu/hdl/example_ghdl/ghdl_import.sh, zpu/hdl/example_ghdl/ghdl_make.sh, zpu/hdl/example_ghdl/ghdl_options.sh, zpu/hdl/example_ghdl/README: GHDL example diff --git a/zpu/hdl/example/simzpu_small.do b/zpu/hdl/example/simzpu_small.do index 095069a..12d231b 100644 --- a/zpu/hdl/example/simzpu_small.do +++ b/zpu/hdl/example/simzpu_small.do @@ -8,10 +8,10 @@ set BreakOnAssertion 1 vlib work vcom -93 -explicit zpu_config.vhd -vcom -93 -explicit ../zpu4/src/zpupkg.vhd +vcom -93 -explicit ../zpu4/core/zpupkg.vhd vcom -93 -explicit ../zpu4/src/txt_util.vhd vcom -93 -explicit sim_small_fpga_top.vhd -vcom -93 -explicit ../zpu4/src/zpu_core_small.vhd +vcom -93 -explicit ../zpu4/core/zpu_core_small.vhd vcom -93 -explicit helloworld.vhd vcom -93 -explicit ../zpu4/src/timer.vhd vcom -93 -explicit ../zpu4/src/io.vhd diff --git a/zpu/hdl/example_ghdl/dmipssmalltrace_ghdl.sh b/zpu/hdl/example_ghdl/dmipssmalltrace_ghdl.sh new file mode 100644 index 0000000..5e43b64 --- /dev/null +++ b/zpu/hdl/example_ghdl/dmipssmalltrace_ghdl.sh @@ -0,0 +1,26 @@ +#!/bin/sh + +UNISIM_DIR="'location of GHDL objects for unisim library'/unisim_v93" +IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work -P${UNISIM_DIR}" +MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding" + +if test ! -e work; then + echo "Building work library..." + mkdir work + ghdl -i ${IMPORT_OPTIONS} zpu_config_trace.vhd + ghdl -i ${IMPORT_OPTIONS} zpupkg.vhd + ghdl -i ${IMPORT_OPTIONS} txt_util.vhd + ghdl -i ${IMPORT_OPTIONS} sim_fpga_top.vhd + ghdl -i ${IMPORT_OPTIONS} zpu_core_small.vhd + ghdl -i ${IMPORT_OPTIONS} bram_dmips.vhd + ghdl -i ${IMPORT_OPTIONS} dram_dmips.vhd + ghdl -i ${IMPORT_OPTIONS} timer.vhd + ghdl -i ${IMPORT_OPTIONS} io.vhd + ghdl -i ${IMPORT_OPTIONS} trace.vhd +fi + +echo "Compiling design..." +if ghdl -m ${MAKE_OPTIONS} fpga_top; then + echo "Compilation finished, start simulation with" + echo " ./fpga_top --stop-time=1ms" +fi diff --git a/zpu/hdl/example_ghdl/dmipstrace_ghdl.sh b/zpu/hdl/example_ghdl/dmipstrace_ghdl.sh new file mode 100644 index 0000000..3be392f --- /dev/null +++ b/zpu/hdl/example_ghdl/dmipstrace_ghdl.sh @@ -0,0 +1,25 @@ +#!/bin/sh + +UNISIM_DIR="'location of GHDL objects for unisim library'/unisim_v93" +IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work -P${UNISIM_DIR}" +MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding" + +if test ! -e work; then + echo "Building work library..." + mkdir work + ghdl -i ${IMPORT_OPTIONS} zpu_config_trace.vhd + ghdl -i ${IMPORT_OPTIONS} zpupkg.vhd + ghdl -i ${IMPORT_OPTIONS} txt_util.vhd + ghdl -i ${IMPORT_OPTIONS} sim_fpga_top.vhd + ghdl -i ${IMPORT_OPTIONS} zpu_core.vhd + ghdl -i ${IMPORT_OPTIONS} dram_dmips.vhd + ghdl -i ${IMPORT_OPTIONS} timer.vhd + ghdl -i ${IMPORT_OPTIONS} io.vhd + ghdl -i ${IMPORT_OPTIONS} trace.vhd +fi + +echo "Compiling design..." +if ghdl -m ${MAKE_OPTIONS} fpga_top; then + echo "Compilation finished, start simulation with" + echo " ./fpga_top --stop-time=2500us" +fi diff --git a/zpu/hdl/example_ghdl/simzpu_medium_ghdl.sh b/zpu/hdl/example_ghdl/simzpu_medium_ghdl.sh new file mode 100644 index 0000000..7a7f3df --- /dev/null +++ b/zpu/hdl/example_ghdl/simzpu_medium_ghdl.sh @@ -0,0 +1,25 @@ +#!/bin/sh + +UNISIM_DIR="'location of GHDL objects for unisim library'/unisim_v93" +IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work -P${UNISIM_DIR}" +MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding" + +if test ! -e work; then + echo "Building work library..." + mkdir work + ghdl -i ${IMPORT_OPTIONS} zpu_config_trace.vhd + ghdl -i ${IMPORT_OPTIONS} zpupkg.vhd + ghdl -i ${IMPORT_OPTIONS} txt_util.vhd + ghdl -i ${IMPORT_OPTIONS} sim_fpga_top.vhd + ghdl -i ${IMPORT_OPTIONS} zpu_core.vhd + ghdl -i ${IMPORT_OPTIONS} dram_hello.vhd + ghdl -i ${IMPORT_OPTIONS} timer.vhd + ghdl -i ${IMPORT_OPTIONS} io.vhd + ghdl -i ${IMPORT_OPTIONS} trace.vhd +fi + +echo "Compiling design..." +if ghdl -m ${MAKE_OPTIONS} fpga_top; then + echo "Compilation finished, start simulation with" + echo " ./fpga_top --stop-time=1ms" +fi diff --git a/zpu/hdl/example_medium/sim_fpga_top.vhd b/zpu/hdl/example_medium/sim_fpga_top.vhd new file mode 100644 index 0000000..29151af --- /dev/null +++ b/zpu/hdl/example_medium/sim_fpga_top.vhd @@ -0,0 +1,188 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 20:15:31 04/14/05 +-- Design Name: +-- Module Name: fpga_top - behave +-- Project Name: +-- Target Device: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +library work; +use work.zpu_config.all; + +entity fpga_top is +end fpga_top; + +use work.zpupkg.all; + +architecture behave of fpga_top is + + +signal clk : std_logic; + +signal areset : std_logic; + + +component zpu_io is + generic ( + log_file: string := "log.txt" + ); + port( + clk : in std_logic; + areset : in std_logic; + busy : out std_logic; + writeEnable : in std_logic; + readEnable : in std_logic; + write : in std_logic_vector(wordSize-1 downto 0); + read : out std_logic_vector(wordSize-1 downto 0); + addr : in std_logic_vector(maxAddrBit downto minAddrBit) + ); +end component; + + + + + +signal mem_busy : std_logic; +signal mem_read : std_logic_vector(wordSize-1 downto 0); +signal mem_write : std_logic_vector(wordSize-1 downto 0); +signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); +signal mem_writeEnable : std_logic; +signal mem_readEnable : std_logic; +signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + +signal enable : std_logic; + +signal dram_mem_busy : std_logic; +signal dram_mem_read : std_logic_vector(wordSize-1 downto 0); +signal dram_mem_write : std_logic_vector(wordSize-1 downto 0); +signal dram_mem_writeEnable : std_logic; +signal dram_mem_readEnable : std_logic; +signal dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + + +signal io_busy : std_logic; + +signal io_mem_read : std_logic_vector(wordSize-1 downto 0); +signal io_mem_writeEnable : std_logic; +signal io_mem_readEnable : std_logic; + + +signal dram_ready : std_logic; +signal io_ready : std_logic; +signal io_reading : std_logic; + + +signal break : std_logic; + +begin + poweronreset: roc port map (O => areset); + + + + zpu: zpu_core port map ( + clk => clk , + areset => areset, + enable => enable, + in_mem_busy => mem_busy, + mem_read => mem_read, + mem_write => mem_write, + out_mem_addr => mem_addr, + out_mem_writeEnable => mem_writeEnable, + out_mem_readEnable => mem_readEnable, + mem_writeMask => mem_writeMask, + interrupt => '0', + break => break); + + dram_imp: dram port map ( + clk => clk , + areset => areset, + mem_busy => dram_mem_busy, + mem_read => dram_mem_read, + mem_write => mem_write, + mem_addr => mem_addr(maxAddrBit downto 0), + mem_writeEnable => dram_mem_writeEnable, + mem_readEnable => dram_mem_readEnable, + mem_writeMask => mem_writeMask); + + + ioMap: zpu_io port map ( + clk => clk, + areset => areset, + busy => io_busy, + writeEnable => io_mem_writeEnable, + readEnable => io_mem_readEnable, + write => mem_write(wordSize-1 downto 0), + read => io_mem_read, + addr => mem_addr(maxAddrBit downto minAddrBit) + ); + + dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit); + dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit); + io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit); + io_mem_readEnable <= mem_readEnable and mem_addr(ioBit); + mem_busy <= io_busy or dram_mem_busy or io_busy; + + + + -- Memory reads either come from IO or DRAM. We need to pick the right one. + memorycontrol: + process(dram_mem_read, dram_ready, io_ready, io_mem_read) + begin + mem_read <= (others => 'U'); + if dram_ready='1' then + mem_read <= dram_mem_read; + end if; + + if io_ready='1' then + mem_read <= io_mem_read; + end if; + end process; + + + io_ready <= (io_reading or io_mem_readEnable) and not io_busy; + + memoryControlSync: + process(clk, areset) + begin + if areset = '1' then + enable <= '0'; + io_reading <= '0'; + dram_ready <= '0'; + elsif (clk'event and clk = '1') then + enable <= '1'; + io_reading <= io_busy or io_mem_readEnable; + dram_ready<=dram_mem_readEnable; + + end if; + end process; + + -- wiggle the clock @ 100MHz + clock : PROCESS + begin + clk <= '0'; + wait for 5 ns; + clk <= '1'; + wait for 5 ns; + end PROCESS clock; + + +end behave; diff --git a/zpu/hdl/example_medium/simzpu_medium.do b/zpu/hdl/example_medium/simzpu_medium.do new file mode 100644 index 0000000..a6c1fe2 --- /dev/null +++ b/zpu/hdl/example_medium/simzpu_medium.do @@ -0,0 +1,28 @@ +# Xilinx WebPack modelsim script +# +# cd C:/workspace/zpu/zpu/hdl/zpu4/src +# do simzpu_medium.do + +set BreakOnAssertion 1 +vlib work + +vcom -93 -explicit zpu_config_trace.vhd +vcom -93 -explicit zpupkg.vhd +vcom -93 -explicit txt_util.vhd +vcom -93 -explicit sim_fpga_top.vhd +vcom -93 -explicit zpu_core.vhd +vcom -93 -explicit dram_hello.vhd +vcom -93 -explicit timer.vhd +vcom -93 -explicit io.vhd +vcom -93 -explicit trace.vhd + +# run ZPU +vsim fpga_top +view wave +add wave -recursive fpga_top/zpu/* +#add wave -recursive fpga_top/* +view structure +#view signals + +# Enough to run tiny programs +run 1000 ms diff --git a/zpu/hdl/sim/dmipssmalltrace.do b/zpu/hdl/sim/dmipssmalltrace.do new file mode 100644 index 0000000..eb4c6fe --- /dev/null +++ b/zpu/hdl/sim/dmipssmalltrace.do @@ -0,0 +1,26 @@ +set BreakOnAssertion 1 +vlib work + +vcom -93 -explicit zpu_config_trace.vhd +vcom -93 -explicit zpupkg.vhd +vcom -93 -explicit txt_util.vhd +vcom -93 -explicit sim_fpga_top.vhd +vcom -93 -explicit zpu_core_small.vhd +vcom -93 -explicit bram_dmips.vhd +vcom -93 -explicit dram_dmips.vhd +vcom -93 -explicit timer.vhd +vcom -93 -explicit io.vhd +vcom -93 -explicit trace.vhd + + +vsim fpga_top +view wave + +add wave -recursive fpga_top/zpu/* +#--add wave -recursive fpga_top/ioMap/* +#add wave -recursive fpga_top/* +view structure + + +# run ZPU +run 5 ms diff --git a/zpu/hdl/sim/dmipstrace.do b/zpu/hdl/sim/dmipstrace.do new file mode 100644 index 0000000..64cf8fd --- /dev/null +++ b/zpu/hdl/sim/dmipstrace.do @@ -0,0 +1,30 @@ +# Xilinx WebPack modelsim script +# +# cd C:/workspace/zpu/zpu/hdl/zpu4/src +# do dmipstrace.do + +set BreakOnAssertion 1 +vlib work + +vcom -93 -explicit zpu_config_trace.vhd +vcom -93 -explicit zpupkg.vhd +vcom -93 -explicit txt_util.vhd +vcom -93 -explicit sim_fpga_top.vhd +vcom -93 -explicit zpu_core.vhd +vcom -93 -explicit dram_dmips.vhd +vcom -93 -explicit timer.vhd +vcom -93 -explicit io.vhd +vcom -93 -explicit trace.vhd + + +vsim fpga_top +view wave + +add wave -recursive fpga_top/zpu/* +#--add wave -recursive fpga_top/ioMap/* +#add wave -recursive fpga_top/* +view structure + + +# run ZPU +run 5 ms diff --git a/zpu/hdl/zpu4/core/zpu_config.vhd b/zpu/hdl/zpu4/core/zpu_config.vhd new file mode 100644 index 0000000..a13c0bf --- /dev/null +++ b/zpu/hdl/zpu4/core/zpu_config.vhd @@ -0,0 +1,16 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +package zpu_config is + -- generate trace output or not. + constant Generate_Trace : boolean := false; + constant wordPower : integer := 5; + -- during simulation, set this to '0' to get matching trace.txt + constant DontCareValue : std_logic := 'X'; + -- Clock frequency in MHz. + constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64"; + -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) + constant maxAddrBitIncIO : integer := 15; + +end zpu_config; diff --git a/zpu/hdl/zpu4/core/zpu_core.vhd b/zpu/hdl/zpu4/core/zpu_core.vhd new file mode 100644 index 0000000..37fa2d1 --- /dev/null +++ b/zpu/hdl/zpu4/core/zpu_core.vhd @@ -0,0 +1,897 @@ + +-- Company: ZPU4 generic memory interface CPU +-- Engineer: Øyvind Harboe + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use ieee.numeric_std.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + + +-- mem_writeEnable - set to '1' for a single cycle to send off a write request. +-- mem_write is valid only while mem_writeEnable='1'. +-- mem_readEnable - set to '1' for a single cycle to send off a read request. +-- +-- mem_busy - It is illegal to send off a read/write request when mem_busy='1'. +-- Set to '0' when mem_read is valid after a read request. +-- If it goes to '1'(busy), it is on the cycle after mem_read/writeEnable +-- is '1'. +-- mem_addr - address for read/write request +-- mem_read - read data. Valid only on the cycle after mem_busy='0' after +-- mem_readEnable='1' for a single cycle. +-- mem_write - data to write +-- mem_writeMask - set to '1' for those bits that are to be written to memory upon +-- write request +-- break - set to '1' when CPU hits break instruction +-- interrupt - set to '1' until interrupts are cleared by CPU. + + + + +entity zpu_core is + Port ( clk : in std_logic; + areset : in std_logic; + enable : in std_logic; + in_mem_busy : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + out_mem_writeEnable : out std_logic; + out_mem_readEnable : out std_logic; + mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + interrupt : in std_logic; + break : out std_logic); +end zpu_core; + +architecture behave of zpu_core is + +type InsnType is +( +State_AddTop, +State_Dup, +State_DupStackB, +State_Pop, +State_Popdown, +State_Add, +State_Or, +State_And, +State_Store, +State_AddSP, +State_Shift, +State_Nop, +State_Im, +State_LoadSP, +State_StoreSP, +State_Emulate, +State_Load, +State_PushPC, +State_PushSP, +State_PopPC, +State_PopPCRel, +State_Not, +State_Flip, +State_PopSP, +State_Neqbranch, +State_Eq, +State_Loadb, +State_Mult, +State_Lessthan, +State_Lessthanorequal, +State_Ulessthanorequal, +State_Ulessthan, +State_Pushspadd, +State_Call, +State_Callpcrel, +State_Sub, +State_Break, +State_Storeb, +State_InsnFetch +); + +type StateType is +( +State_Load2, +State_Popped, +State_LoadSP2, +State_LoadSP3, +State_AddSP2, +State_Fetch, +State_Execute, +State_Decode, +State_Decode2, +State_Resync, + +State_StoreSP2, +State_Resync2, +State_Resync3, +State_Loadb2, +State_Storeb2, +State_Mult2, +State_Mult3, +State_Mult5, +State_Mult4, +State_BinaryOpResult2, +State_BinaryOpResult, +State_Idle +); + + +signal pc : unsigned(maxAddrBitIncIO downto 0); +signal sp : unsigned(maxAddrBitIncIO downto minAddrBit); +signal incSp : unsigned(maxAddrBitIncIO downto minAddrBit); +signal incIncSp : unsigned(maxAddrBitIncIO downto minAddrBit); +signal decSp : unsigned(maxAddrBitIncIO downto minAddrBit); +signal stackA : unsigned(wordSize-1 downto 0); +signal binaryOpResult : unsigned(wordSize-1 downto 0); +signal binaryOpResult2 : unsigned(wordSize-1 downto 0); +signal multResult2 : unsigned(wordSize-1 downto 0); +signal multResult3 : unsigned(wordSize-1 downto 0); +signal multResult : unsigned(wordSize-1 downto 0); +signal multA : unsigned(wordSize-1 downto 0); +signal multB : unsigned(wordSize-1 downto 0); +signal stackB : unsigned(wordSize-1 downto 0); +signal idim_flag : std_logic; +signal busy : std_logic; +signal mem_writeEnable : std_logic; +signal mem_readEnable : std_logic; +signal mem_addr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal mem_delayAddr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal mem_delayReadEnable : std_logic; + +signal decodeWord : std_logic_vector(wordSize-1 downto 0); + + +signal state : StateType; +signal insn : InsnType; +type InsnArray is array(0 to wordBytes-1) of InsnType; +signal decodedOpcode : InsnArray; + +type OpcodeArray is array(0 to wordBytes-1) of std_logic_vector(7 downto 0); + +signal opcode : OpcodeArray; + + + + +signal begin_inst : std_logic; +signal trace_opcode : std_logic_vector(7 downto 0); +signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); +signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); +signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); + +-- state machine. + +begin + + + traceFileGenerate: + if Generate_Trace generate + trace_file: trace port map ( + clk => clk, + begin_inst => begin_inst, + pc => trace_pc, + opcode => trace_opcode, + sp => trace_sp, + memA => trace_topOfStack, + memB => trace_topOfStackB, + busy => busy, + intsp => (others => 'U') + ); + end generate; + + + -- the memory subsystem will tell us one cycle later whether or + -- not it is busy + out_mem_writeEnable <= mem_writeEnable; + out_mem_readEnable <= mem_readEnable; + out_mem_addr(maxAddrBitIncIO downto minAddrBit) <= mem_addr; + out_mem_addr(minAddrBit-1 downto 0) <= (others => '0'); + + incSp <= sp + 1; + incIncSp <= sp + 2; + decSp <= sp - 1; + + + opcodeControl: + process(clk, areset) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + variable spOffset : unsigned(4 downto 0); + variable tSpOffset : unsigned(4 downto 0); + variable nextPC : unsigned(maxAddrBitIncIO downto 0); + variable tNextState : InsnType; + variable tDecodedOpcode : InsnArray; + variable tMultResult : unsigned(wordSize*2-1 downto 0); + begin + if areset = '1' then + state <= State_Idle; + break <= '0'; + sp <= unsigned(spStart(maxAddrBitIncIO downto minAddrBit)); + + pc <= (others => '0'); + idim_flag <= '0'; + begin_inst <= '0'; + mem_writeEnable <= '0'; + mem_readEnable <= '0'; + multA <= (others => '0'); + multB <= (others => '0'); + mem_writeMask <= (others => '1'); + elsif (clk'event and clk = '1') then + -- we must multiply unconditionally to get pipelined multiplication + tMultResult := multA * multB; + multResult3 <= multResult2; + multResult2 <= multResult; + multResult <= tMultResult(wordSize-1 downto 0); + + + binaryOpResult2 <= binaryOpResult; -- pipeline a bit. + + + multA <= (others => DontCareValue); + multB <= (others => DontCareValue); + + + mem_addr <= (others => DontCareValue); + mem_readEnable <='0'; + mem_writeEnable <='0'; + mem_write <= (others => DontCareValue); + + if (mem_writeEnable = '1') and (mem_readEnable = '1') then + report "read/write collision" severity failure; + end if; + + + + + spOffset(4):=not opcode(to_integer(pc(byteBits-1 downto 0)))(4); + spOffset(3 downto 0):=unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(3 downto 0)); + nextPC := pc + 1; + + -- prepare trace snapshot + trace_opcode <= opcode(to_integer(pc(byteBits-1 downto 0))); + trace_pc <= std_logic_vector(pc); + trace_sp <= std_logic_vector(sp); + trace_topOfStack <= std_logic_vector(stackA); + trace_topOfStackB <= std_logic_vector(stackB); + begin_inst <= '0'; + + + case state is + when State_Idle => + if enable='1' then + state <= State_Resync; + end if; + -- Initial state of ZPU, fetch top of stack + first instruction + when State_Resync => + if in_mem_busy='0' then + mem_addr <= std_logic_vector(sp); + mem_readEnable <= '1'; + state <= State_Resync2; + end if; + when State_Resync2 => + if in_mem_busy='0' then + stackA <= unsigned(mem_read); + mem_addr <= std_logic_vector(incSp); + mem_readEnable <= '1'; + state <= State_Resync3; + end if; + when State_Resync3 => + if in_mem_busy='0' then + stackB <= unsigned(mem_read); + mem_addr <= std_logic_vector(pc(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + state <= State_Decode; + end if; + when State_Decode => + if in_mem_busy='0' then + decodeWord <= mem_read; + state <= State_Decode2; + end if; + when State_Decode2 => + -- decode 4 instructions in parallel + for i in 0 to wordBytes-1 loop + tOpcode := decodeWord((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8); + + tSpOffset(4):=not tOpcode(4); + tSpOffset(3 downto 0):=unsigned(tOpcode(3 downto 0)); + + opcode(i) <= tOpcode; + if (tOpcode(7 downto 7)=OpCode_Im) then + tNextState:=State_Im; + elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then + if tSpOffset = 0 then + tNextState := State_Pop; + elsif tSpOffset=1 then + tNextState := State_PopDown; + else + tNextState :=State_StoreSP; + end if; + elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then + if tSpOffset = 0 then + tNextState :=State_Dup; + elsif tSpOffset = 1 then + tNextState :=State_DupStackB; + else + tNextState :=State_LoadSP; + end if; + elsif (tOpcode(7 downto 5)=OpCode_Emulate) then + tNextState :=State_Emulate; + if tOpcode(5 downto 0)=OpCode_Neqbranch then + tNextState :=State_Neqbranch; + elsif tOpcode(5 downto 0)=OpCode_Eq then + tNextState :=State_Eq; + elsif tOpcode(5 downto 0)=OpCode_Lessthan then + tNextState :=State_Lessthan; + elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then + --tNextState :=State_Lessthanorequal; + elsif tOpcode(5 downto 0)=OpCode_Ulessthan then + tNextState :=State_Ulessthan; + elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then + --tNextState :=State_Ulessthanorequal; + elsif tOpcode(5 downto 0)=OpCode_Loadb then + tNextState :=State_Loadb; + elsif tOpcode(5 downto 0)=OpCode_Mult then + tNextState :=State_Mult; + elsif tOpcode(5 downto 0)=OpCode_Storeb then + tNextState :=State_Storeb; + elsif tOpcode(5 downto 0)=OpCode_Pushspadd then + tNextState :=State_Pushspadd; + elsif tOpcode(5 downto 0)=OpCode_Callpcrel then + tNextState :=State_Callpcrel; + elsif tOpcode(5 downto 0)=OpCode_Call then + --tNextState :=State_Call; + elsif tOpcode(5 downto 0)=OpCode_Sub then + tNextState :=State_Sub; + elsif tOpcode(5 downto 0)=OpCode_PopPCRel then + --tNextState :=State_PopPCRel; + end if; + elsif (tOpcode(7 downto 4)=OpCode_AddSP) then + if tSpOffset = 0 then + tNextState := State_Shift; + elsif tSpOffset = 1 then + tNextState := State_AddTop; + else + tNextState :=State_AddSP; + end if; + else + case tOpcode(3 downto 0) is + when OpCode_Nop => + tNextState :=State_Nop; + when OpCode_PushSP => + tNextState :=State_PushSP; + when OpCode_PopPC => + tNextState :=State_PopPC; + when OpCode_Add => + tNextState :=State_Add; + when OpCode_Or => + tNextState :=State_Or; + when OpCode_And => + tNextState :=State_And; + when OpCode_Load => + tNextState :=State_Load; + when OpCode_Not => + tNextState :=State_Not; + when OpCode_Flip => + tNextState :=State_Flip; + when OpCode_Store => + tNextState :=State_Store; + when OpCode_PopSP => + tNextState :=State_PopSP; + when others => + tNextState := State_Break; + + end case; + end if; + tDecodedOpcode(i) := tNextState; + + end loop; + + insn <= tDecodedOpcode(to_integer(pc(byteBits-1 downto 0))); + + -- once we wrap, we need to fetch + tDecodedOpcode(0) := State_InsnFetch; + + decodedOpcode <= tDecodedOpcode; + state <= State_Execute; + + + + -- Each instruction must: + -- + -- 1. set idim_flag + -- 2. increase pc if applicable + -- 3. set next state if appliable + -- 4. do it's operation + + when State_Execute => + insn <= decodedOpcode(to_integer(nextPC(byteBits-1 downto 0))); + + case insn is + when State_InsnFetch => + state <= State_Fetch; + when State_Im => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '1'; + pc <= pc + 1; + + if idim_flag='1' then + stackA(wordSize-1 downto 7) <= stackA(wordSize-8 downto 0); + stackA(6 downto 0) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(6 downto 0)); + else + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + stackB <= stackA; + sp <= decSp; + for i in wordSize-1 downto 7 loop + stackA(i) <= opcode(to_integer(pc(byteBits-1 downto 0)))(6); + end loop; + stackA(6 downto 0) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(6 downto 0)); + end if; + end if; + when State_StoreSP => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_StoreSP2; + + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(sp+spOffset); + mem_write <= std_logic_vector(stackA); + stackA <= stackB; + sp <= incSp; + end if; + + + when State_LoadSP => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_LoadSP2; + + sp <= decSp; + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + end if; + when State_Emulate => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + sp <= decSp; + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + stackB <= stackA; + + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= (others => '0'); + pc(9 downto 5) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(4 downto 0)); + state <= State_Fetch; + end if; + when State_Callpcrel => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + + pc <= pc + stackA(maxAddrBitIncIO downto 0); + state <= State_Fetch; + end if; + when State_Call => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + pc <= stackA(maxAddrBitIncIO downto 0); + state <= State_Fetch; + end if; + when State_AddSP => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_AddSP2; + + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(sp+spOffset); + end if; + when State_PushSP => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackA <= (others => '0'); + stackA(maxAddrBitIncIO downto minAddrBit) <= sp; + stackB <= stackA; + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + end if; + when State_PopPC => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= stackA(maxAddrBitIncIO downto 0); + sp <= incSp; + + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + state <= State_Resync; + end if; + when State_PopPCRel => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= stackA(maxAddrBitIncIO downto 0) + pc; + sp <= incSp; + + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + state <= State_Resync; + end if; + when State_Add => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= stackA + stackB; + + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + state <= State_Popped; + end if; + when State_Sub => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + binaryOpResult <= stackB - stackA; + state <= State_BinaryOpResult; + end if; + when State_Pop => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + mem_addr <= std_logic_vector(incIncSp); + mem_readEnable <= '1'; + sp <= incSp; + stackA <= stackB; + state <= State_Popped; + end if; + when State_PopDown => + if in_mem_busy='0' then + -- PopDown leaves top of stack unchanged + begin_inst <= '1'; + idim_flag <= '0'; + mem_addr <= std_logic_vector(incIncSp); + mem_readEnable <= '1'; + sp <= incSp; + state <= State_Popped; + end if; + when State_Or => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= stackA or stackB; + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + state <= State_Popped; + end if; + when State_And => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + stackA <= stackA and stackB; + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + state <= State_Popped; + end if; + when State_Eq => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA=stackB) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + end if; + when State_Ulessthan => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA<=stackB) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + end if; + when State_Lessthan => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (signed(stackA) + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (signed(stackA)<=signed(stackB)) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + end if; + when State_Load => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Load2; + + mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + end if; + + when State_Dup => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackB <= stackA; + mem_write <= std_logic_vector(stackB); + mem_addr <= std_logic_vector(incSp); + mem_writeEnable <= '1'; + end if; + when State_DupStackB => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackA <= stackB; + stackB <= stackA; + mem_write <= std_logic_vector(stackB); + mem_addr <= std_logic_vector(incSp); + mem_writeEnable <= '1'; + end if; + when State_Store => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); + mem_write <= std_logic_vector(stackB); + mem_writeEnable <= '1'; + sp <= incIncSp; + state <= State_Resync; + end if; + when State_PopSP => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + mem_write <= std_logic_vector(stackB); + mem_addr <= std_logic_vector(incSp); + mem_writeEnable <= '1'; + sp <= stackA(maxAddrBitIncIO downto minAddrBit); + state <= State_Resync; + end if; + when State_Nop => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + when State_Not => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= not stackA; + when State_Flip => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + for i in 0 to wordSize-1 loop + stackA(i) <= stackA(wordSize-1-i); + end loop; + when State_AddTop => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= stackA + stackB; + when State_Shift => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0); + stackA(0) <= '0'; + when State_Pushspadd => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= (others => '0'); + stackA(maxAddrBitIncIO downto minAddrBit) <= stackA(maxAddrBitIncIO-minAddrBit downto 0)+sp; + when State_Neqbranch => + -- branches are almost always taken as they form loops + begin_inst <= '1'; + idim_flag <= '0'; + sp <= incIncSp; + if (stackB/=0) then + pc <= stackA(maxAddrBitIncIO downto 0) + pc; + else + pc <= pc + 1; + end if; + -- need to fetch stack again. + state <= State_Resync; + when State_Mult => + begin_inst <= '1'; + idim_flag <= '0'; + + multA <= stackA; + multB <= stackB; + state <= State_Mult2; + when State_Break => + report "Break instruction encountered" severity failure; + break <= '1'; + + when State_Loadb => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Loadb2; + + mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + end if; + when State_Storeb => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Storeb2; + + mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + end if; + + when others => + sp <= (others => DontCareValue); + report "Illegal instruction" severity failure; + break <= '1'; + end case; + + + when State_StoreSP2 => + if in_mem_busy='0' then + mem_addr <= std_logic_vector(incSp); + mem_readEnable <= '1'; + state <= State_Popped; + end if; + when State_LoadSP2 => + if in_mem_busy='0' then + state <= State_LoadSP3; + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(sp+spOffset+1); + end if; + when State_LoadSP3 => + if in_mem_busy='0' then + pc <= pc + 1; + state <= State_Execute; + stackB <= stackA; + stackA <= unsigned(mem_read); + end if; + when State_AddSP2 => + if in_mem_busy='0' then + pc <= pc + 1; + state <= State_Execute; + stackA <= stackA + unsigned(mem_read); + end if; + when State_Load2 => + if in_mem_busy='0' then + stackA <= unsigned(mem_read); + pc <= pc + 1; + state <= State_Execute; + end if; + when State_Loadb2 => + if in_mem_busy='0' then + stackA <= (others => '0'); + stackA(7 downto 0) <= unsigned(mem_read(((wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8)); + pc <= pc + 1; + state <= State_Execute; + end if; + when State_Storeb2 => + if in_mem_busy='0' then + mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); + mem_write <= mem_read; + mem_write(((wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8) <= std_logic_vector(stackB(7 downto 0)); + mem_writeEnable <= '1'; + pc <= pc + 1; + sp <= incIncSp; + state <= State_Resync; + end if; + when State_Fetch => + if in_mem_busy='0' then + mem_addr <= std_logic_vector(pc(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + state <= State_Decode; + end if; + when State_Mult2 => + state <= State_Mult3; + when State_Mult3 => + state <= State_Mult4; + when State_Mult4 => + state <= State_Mult5; + when State_Mult5 => + if in_mem_busy='0' then + stackA <= multResult3; + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + state <= State_Popped; + end if; + when State_BinaryOpResult => + state <= State_BinaryOpResult2; + when State_BinaryOpResult2 => + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + stackA <= binaryOpResult2; + state <= State_Popped; + when State_Popped => + if in_mem_busy='0' then + pc <= pc + 1; + stackB <= unsigned(mem_read); + state <= State_Execute; + end if; + when others => + sp <= (others => DontCareValue); + report "Illegal state" severity failure; + break <= '1'; + end case; + end if; + end process; + + + +end behave; diff --git a/zpu/hdl/zpu4/core/zpu_core_small.vhd b/zpu/hdl/zpu4/core/zpu_core_small.vhd new file mode 100644 index 0000000..9cda01c --- /dev/null +++ b/zpu/hdl/zpu4/core/zpu_core_small.vhd @@ -0,0 +1,464 @@ +-- Company: ZPU3 +-- Engineer: Øyvind Harboe + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use ieee.numeric_std.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + + +entity zpu_core is + Port ( clk : in std_logic; + areset : in std_logic; + enable : in std_logic; + in_mem_busy : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + out_mem_writeEnable : out std_logic; + out_mem_readEnable : out std_logic; + mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + interrupt : in std_logic; + break : out std_logic); +end zpu_core; + +architecture behave of zpu_core is + +signal readIO : std_logic; + + + +signal memAWriteEnable : std_logic; +signal memAAddr : unsigned(maxAddrBit downto minAddrBit); +signal memAWrite : unsigned(wordSize-1 downto 0); +signal memARead : unsigned(wordSize-1 downto 0); +signal memBWriteEnable : std_logic; +signal memBAddr : unsigned(maxAddrBit downto minAddrBit); +signal memBWrite : unsigned(wordSize-1 downto 0); +signal memBRead : unsigned(wordSize-1 downto 0); + + + +signal pc : unsigned(maxAddrBit downto 0); +signal sp : unsigned(maxAddrBit downto minAddrBit); + +signal idim_flag : std_logic; + +--signal storeToStack : std_logic; +--signal fetchNextInstruction : std_logic; +--signal extraCycle : std_logic; +signal busy : std_logic; +--signal fetching : std_logic; + +signal begin_inst : std_logic; + + + +signal trace_opcode : std_logic_vector(7 downto 0); +signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); +signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); +signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); + +-- state machine. +type State_Type is +( +State_Fetch, +State_WriteIODone, +State_Execute, +State_StoreToStack, +State_Add, +State_Or, +State_And, +State_Store, +State_ReadIO, +State_WriteIO, +State_Load, +State_FetchNext, +State_AddSP, +State_ReadIODone, +State_Decode, +State_Resync +); + +type DecodedOpcodeType is +( +Decoded_Nop, +Decoded_Im, +Decoded_ImShift, +Decoded_LoadSP, +Decoded_StoreSP , +Decoded_AddSP, +Decoded_Emulate, +Decoded_Break, +Decoded_PushSP, +Decoded_PopPC, +Decoded_Add, +Decoded_Or, +Decoded_And, +Decoded_Load, +Decoded_Not, +Decoded_Flip, +Decoded_Store, +Decoded_PopSP +); + + + +signal sampledOpcode : std_logic_vector(OpCode_Size-1 downto 0); +signal opcode : std_logic_vector(OpCode_Size-1 downto 0); + +signal decodedOpcode : DecodedOpcodeType; +signal sampledDecodedOpcode : DecodedOpcodeType; + + +signal state : State_Type; + +subtype AddrBitBRAM_range is natural range maxAddrBitBRAM downto minAddrBit; +signal memAAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); +signal memAWrite_stdlogic : std_logic_vector(memAWrite'range); +signal memARead_stdlogic : std_logic_vector(memARead'range); +signal memBAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); +signal memBWrite_stdlogic : std_logic_vector(memBWrite'range); +signal memBRead_stdlogic : std_logic_vector(memBRead'range); + +-- debug +subtype index is integer range 0 to 3; +signal tOpcode_sel : index; + + +begin + traceFileGenerate: + if Generate_Trace generate + trace_file: trace port map ( + clk => clk, + begin_inst => begin_inst, + pc => trace_pc, + opcode => trace_opcode, + sp => trace_sp, + memA => trace_topOfStack, + memB => trace_topOfStackB, + busy => busy, + intsp => (others => 'U') + ); + end generate; + + -- not used in this design + mem_writeMask <= (others => '1'); + + memAAddr_stdlogic <= std_logic_vector(memAAddr(AddrBitBRAM_range)); + memAWrite_stdlogic <= std_logic_vector(memAWrite); + memBAddr_stdlogic <= std_logic_vector(memBAddr(AddrBitBRAM_range)); + memBWrite_stdlogic <= std_logic_vector(memBWrite); + memory: dualport_ram port map ( + clk => clk, + memAWriteEnable => memAWriteEnable, + memAAddr => memAAddr_stdlogic, + memAWrite => memAWrite_stdlogic, + memARead => memARead_stdlogic, + memBWriteEnable => memBWriteEnable, + memBAddr => memBAddr_stdlogic, + memBWrite => memBWrite_stdlogic, + memBRead => memBRead_stdlogic + ); + memARead <= unsigned(memARead_stdlogic); + memBRead <= unsigned(memBRead_stdlogic); + +tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0)); + + + decodeControl: + process(memBRead, pc,tOpcode_sel) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + begin + -- not worked with synopsys + -- tOpcode := std_logic_vector(memBRead((wordBytes-1-to_integer(pc(minAddrBit-1 downto 0))+1)*8-1 downto (wordBytes-1-to_integer(pc(minAddrBit-1 downto 0)))*8)); + -- use full case + case (tOpcode_sel) is + when 0 => tOpcode := std_logic_vector(memBRead(31 downto 24)); + when 1 => tOpcode := std_logic_vector(memBRead(23 downto 16)); + when 2 => tOpcode := std_logic_vector(memBRead(15 downto 8)); + when 3 => tOpcode := std_logic_vector(memBRead(7 downto 0)); + when others => tOpcode := std_logic_vector(memBRead(7 downto 0)); + end case; + sampledOpcode <= tOpcode; + + if (tOpcode(7 downto 7)=OpCode_Im) then + sampledDecodedOpcode<=Decoded_Im; + elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then + sampledDecodedOpcode<=Decoded_StoreSP; + elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then + sampledDecodedOpcode<=Decoded_LoadSP; + elsif (tOpcode(7 downto 5)=OpCode_Emulate) then + sampledDecodedOpcode<=Decoded_Emulate; + elsif (tOpcode(7 downto 4)=OpCode_AddSP) then + sampledDecodedOpcode<=Decoded_AddSP; + else + case tOpcode(3 downto 0) is + when OpCode_Break => + sampledDecodedOpcode<=Decoded_Break; + when OpCode_PushSP => + sampledDecodedOpcode<=Decoded_PushSP; + when OpCode_PopPC => + sampledDecodedOpcode<=Decoded_PopPC; + when OpCode_Add => + sampledDecodedOpcode<=Decoded_Add; + when OpCode_Or => + sampledDecodedOpcode<=Decoded_Or; + when OpCode_And => + sampledDecodedOpcode<=Decoded_And; + when OpCode_Load => + sampledDecodedOpcode<=Decoded_Load; + when OpCode_Not => + sampledDecodedOpcode<=Decoded_Not; + when OpCode_Flip => + sampledDecodedOpcode<=Decoded_Flip; + when OpCode_Store => + sampledDecodedOpcode<=Decoded_Store; + when OpCode_PopSP => + sampledDecodedOpcode<=Decoded_PopSP; + when others => + sampledDecodedOpcode<=Decoded_Nop; + end case; + end if; + end process; + + + opcodeControl: + process(clk, areset) + variable spOffset : unsigned(4 downto 0); + begin + if areset = '1' then + state <= State_Resync; + break <= '0'; + sp <= unsigned(spStart(maxAddrBit downto minAddrBit)); + pc <= (others => '0'); + idim_flag <= '0'; + begin_inst <= '0'; + memAAddr <= (others => '0'); + memBAddr <= (others => '0'); + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + out_mem_writeEnable <= '0'; + out_mem_readEnable <= '0'; + memAWrite <= (others => '0'); + memBWrite <= (others => '0'); + -- avoid Latch in synopsys + -- mem_writeMask <= (others => '1'); + elsif (clk'event and clk = '1') then + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + -- This saves ca. 100 LUT's, by explicitly declaring that the + -- memAWrite can be left at whatever value if memAWriteEnable is + -- not set. + memAWrite <= (others => DontCareValue); + memBWrite <= (others => DontCareValue); +-- out_mem_addr <= (others => DontCareValue); +-- mem_write <= (others => DontCareValue); + spOffset := (others => DontCareValue); + memAAddr <= (others => DontCareValue); + memBAddr <= (others => DontCareValue); + + out_mem_writeEnable <= '0'; + out_mem_readEnable <= '0'; + begin_inst <= '0'; + out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); + mem_write <= std_logic_vector(memBRead); + + decodedOpcode <= sampledDecodedOpcode; + opcode <= sampledOpcode; + + case state is + when State_Execute => + state <= State_Fetch; + -- at this point: + -- memBRead contains opcode word + -- memARead contains top of stack + pc <= pc + 1; + + -- trace + begin_inst <= '1'; + trace_pc <= (others => '0'); + trace_pc(maxAddrBit downto 0) <= std_logic_vector(pc); + trace_opcode <= opcode; + trace_sp <= (others => '0'); + trace_sp(maxAddrBit downto minAddrBit) <= std_logic_vector(sp); + trace_topOfStack <= std_logic_vector(memARead); + trace_topOfStackB <= std_logic_vector(memBRead); + + -- during the next cycle we'll be reading the next opcode + spOffset(4):=not opcode(4); + spOffset(3 downto 0) := unsigned(opcode(3 downto 0)); + + idim_flag <= '0'; + case decodedOpcode is + when Decoded_Im => + idim_flag <= '1'; + memAWriteEnable <= '1'; + if (idim_flag='0') then + sp <= sp - 1; + memAAddr <= sp-1; + for i in wordSize-1 downto 7 loop + memAWrite(i) <= opcode(6); + end loop; + memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); + else + memAAddr <= sp; + memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0); + memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); + end if; + when Decoded_StoreSP => + memBWriteEnable <= '1'; + memBAddr <= sp+spOffset; + memBWrite <= memARead; + sp <= sp + 1; + state <= State_Resync; + when Decoded_LoadSP => + sp <= sp - 1; + memAAddr <= sp+spOffset; + when Decoded_Emulate => + sp <= sp - 1; + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto 0) <= pc + 1; + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= (others => '0'); + pc(9 downto 5) <= unsigned(opcode(4 downto 0)); + when Decoded_AddSP => + memAAddr <= sp; + memBAddr <= sp+spOffset; + state <= State_AddSP; + when Decoded_Break => + report "Break instruction encountered" severity failure; + break <= '1'; + when Decoded_PushSP => + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + sp <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto minAddrBit) <= sp; + when Decoded_PopPC => + pc <= memARead(maxAddrBit downto 0); + sp <= sp + 1; + state <= State_Resync; + when Decoded_Add => + sp <= sp + 1; + state <= State_Add; + when Decoded_Or => + sp <= sp + 1; + state <= State_Or; + when Decoded_And => + sp <= sp + 1; + state <= State_And; + when Decoded_Load => + if (memARead(ioBit)='1') then + out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); + out_mem_readEnable <= '1'; + state <= State_ReadIO; + else + memAAddr <= memARead(maxAddrBit downto minAddrBit); + end if; + when Decoded_Not => + memAAddr <= sp(maxAddrBit downto minAddrBit); + memAWriteEnable <= '1'; + memAWrite <= not memARead; + when Decoded_Flip => + memAAddr <= sp(maxAddrBit downto minAddrBit); + memAWriteEnable <= '1'; + for i in 0 to wordSize-1 loop + memAWrite(i) <= memARead(wordSize-1-i); + end loop; + when Decoded_Store => + memBAddr <= sp + 1; + sp <= sp + 1; + if (memARead(ioBit)='1') then + state <= State_WriteIO; + else + state <= State_Store; + end if; + when Decoded_PopSP => + sp <= memARead(maxAddrBit downto minAddrBit); + state <= State_Resync; + when Decoded_Nop => + memAAddr <= sp; + when others => + null; + end case; + when State_ReadIO => + if (in_mem_busy = '0') then + state <= State_Fetch; + memAWriteEnable <= '1'; + memAWrite <= unsigned(mem_read); + end if; + when State_WriteIO => + sp <= sp + 1; + out_mem_writeEnable <= '1'; + out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); + mem_write <= std_logic_vector(memBRead); + state <= State_WriteIODone; + when State_WriteIODone => + if (in_mem_busy = '0') then + state <= State_Resync; + end if; + when State_Fetch => + -- We need to resync. During the *next* cycle + -- we'll fetch the opcode @ pc and thus it will + -- be available for State_Execute the cycle after + -- next + memBAddr <= pc(maxAddrBit downto minAddrBit); + state <= State_FetchNext; + when State_FetchNext => + -- at this point memARead contains the value that is either + -- from the top of stack or should be copied to the top of the stack + memAWriteEnable <= '1'; + memAWrite <= memARead; + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Decode; + when State_Decode => + -- during the State_Execute cycle we'll be fetching SP+1 + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Execute; + when State_Store => + sp <= sp + 1; + memAWriteEnable <= '1'; + memAAddr <= memARead(maxAddrBit downto minAddrBit); + memAWrite <= memBRead; + state <= State_Resync; + when State_AddSP => + state <= State_Add; + when State_Add => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead + memBRead; + state <= State_Fetch; + when State_Or => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead or memBRead; + state <= State_Fetch; + when State_Resync => + memAAddr <= sp; + state <= State_Fetch; + when State_And => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead and memBRead; + state <= State_Fetch; + when others => + null; + end case; + + end if; + end process; + + + +end behave; diff --git a/zpu/hdl/zpu4/core/zpu_core_small_wip.vhd b/zpu/hdl/zpu4/core/zpu_core_small_wip.vhd new file mode 100644 index 0000000..8d87804 --- /dev/null +++ b/zpu/hdl/zpu4/core/zpu_core_small_wip.vhd @@ -0,0 +1,497 @@ +-- Company: ZPU3 +-- Engineer: Øyvind Harboe + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use ieee.numeric_std.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + + +entity zpu_core is + Port ( clk : in std_logic; + areset : in std_logic; + enable : in std_logic; + in_mem_busy : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + out_mem_writeEnable : out std_logic; + out_mem_readEnable : out std_logic; + mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + interrupt : in std_logic; + break : out std_logic); +end zpu_core; + +architecture behave of zpu_core is + +signal readIO : std_logic; + + + +signal memAWriteEnable : std_logic; +signal memAAddr : unsigned(maxAddrBit downto minAddrBit); +signal memAWrite : unsigned(wordSize-1 downto 0); +signal memARead : unsigned(wordSize-1 downto 0); +signal memBWriteEnable : std_logic; +signal memBAddr : unsigned(maxAddrBit downto minAddrBit); +signal memBWrite : unsigned(wordSize-1 downto 0); +signal memBRead : unsigned(wordSize-1 downto 0); + + + +signal pc : unsigned(maxAddrBit downto 0); +signal sp : unsigned(maxAddrBit downto minAddrBit); + +signal idim_flag : std_logic; + +--signal storeToStack : std_logic; +--signal fetchNextInstruction : std_logic; +--signal extraCycle : std_logic; +signal busy : std_logic; +--signal fetching : std_logic; + +signal begin_inst : std_logic; + + + +signal trace_opcode : std_logic_vector(7 downto 0); +signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); +signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); +signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); + +-- state machine. +type State_Type is +( +State_Fetch, +State_WriteIODone, +State_Execute, +State_StoreToStack, +State_Add, +State_Or, +State_And, +State_Store, +State_ReadIO, +State_WriteIO, +State_Load, +State_FetchNext, +State_AddSP, +State_ReadIODone, +State_Decode, +State_Resync, +State_Interrupt + +); + +type DecodedOpcodeType is +( +Decoded_Nop, +Decoded_Im, +Decoded_ImShift, +Decoded_LoadSP, +Decoded_StoreSP , +Decoded_AddSP, +Decoded_Emulate, +Decoded_Break, +Decoded_PushSP, +Decoded_PopPC, +Decoded_Add, +Decoded_Or, +Decoded_And, +Decoded_Load, +Decoded_Not, +Decoded_Flip, +Decoded_Store, +Decoded_PopSP +); + + + +signal sampledOpcode : std_logic_vector(OpCode_Size-1 downto 0); +signal opcode : std_logic_vector(OpCode_Size-1 downto 0); + +signal decodedOpcode : DecodedOpcodeType; +signal sampledDecodedOpcode : DecodedOpcodeType; + + +signal state : State_Type; + +subtype AddrBitBRAM_range is natural range maxAddrBitBRAM downto minAddrBit; +signal memAAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); +signal memAWrite_stdlogic : std_logic_vector(memAWrite'range); +signal memARead_stdlogic : std_logic_vector(memARead'range); +signal memBAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); +signal memBWrite_stdlogic : std_logic_vector(memBWrite'range); +signal memBRead_stdlogic : std_logic_vector(memBRead'range); + +subtype index is integer range 0 to 3; + +signal tOpcode_sel : index; + + +signal inInterrupt : std_logic; + + + +begin + traceFileGenerate: + if Generate_Trace generate + trace_file: trace port map ( + clk => clk, + begin_inst => begin_inst, + pc => trace_pc, + opcode => trace_opcode, + sp => trace_sp, + memA => trace_topOfStack, + memB => trace_topOfStackB, + busy => busy, + intsp => (others => 'U') + ); + end generate; + + + + -- not used in this design + + mem_writeMask <= (others => '1'); + + + + memAAddr_stdlogic <= std_logic_vector(memAAddr(AddrBitBRAM_range)); + memAWrite_stdlogic <= std_logic_vector(memAWrite); + memBAddr_stdlogic <= std_logic_vector(memBAddr(AddrBitBRAM_range)); + memBWrite_stdlogic <= std_logic_vector(memBWrite); + memory: dualport_ram port map ( + clk => clk, + memAWriteEnable => memAWriteEnable, + memAAddr => memAAddr_stdlogic, + memAWrite => memAWrite_stdlogic, + memARead => memARead_stdlogic, + memBWriteEnable => memBWriteEnable, + memBAddr => memBAddr_stdlogic, + memBWrite => memBWrite_stdlogic, + memBRead => memBRead_stdlogic + ); + memARead <= unsigned(memARead_stdlogic); + memBRead <= unsigned(memBRead_stdlogic); + + + + tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0)); + + + + decodeControl: + process(memBRead, pc,tOpcode_sel) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + begin + + -- simplify opcode selection a bit so it passes more synthesizers + case (tOpcode_sel) is + + when 0 => tOpcode := std_logic_vector(memBRead(31 downto 24)); + + when 1 => tOpcode := std_logic_vector(memBRead(23 downto 16)); + + when 2 => tOpcode := std_logic_vector(memBRead(15 downto 8)); + + when 3 => tOpcode := std_logic_vector(memBRead(7 downto 0)); + + when others => tOpcode := std_logic_vector(memBRead(7 downto 0)); + end case; + + sampledOpcode <= tOpcode; + + if (tOpcode(7 downto 7)=OpCode_Im) then + sampledDecodedOpcode<=Decoded_Im; + elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then + sampledDecodedOpcode<=Decoded_StoreSP; + elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then + sampledDecodedOpcode<=Decoded_LoadSP; + elsif (tOpcode(7 downto 5)=OpCode_Emulate) then + sampledDecodedOpcode<=Decoded_Emulate; + elsif (tOpcode(7 downto 4)=OpCode_AddSP) then + sampledDecodedOpcode<=Decoded_AddSP; + else + case tOpcode(3 downto 0) is + when OpCode_Break => + sampledDecodedOpcode<=Decoded_Break; + when OpCode_PushSP => + sampledDecodedOpcode<=Decoded_PushSP; + when OpCode_PopPC => + sampledDecodedOpcode<=Decoded_PopPC; + when OpCode_Add => + sampledDecodedOpcode<=Decoded_Add; + when OpCode_Or => + sampledDecodedOpcode<=Decoded_Or; + when OpCode_And => + sampledDecodedOpcode<=Decoded_And; + when OpCode_Load => + sampledDecodedOpcode<=Decoded_Load; + when OpCode_Not => + sampledDecodedOpcode<=Decoded_Not; + when OpCode_Flip => + sampledDecodedOpcode<=Decoded_Flip; + when OpCode_Store => + sampledDecodedOpcode<=Decoded_Store; + when OpCode_PopSP => + sampledDecodedOpcode<=Decoded_PopSP; + when others => + sampledDecodedOpcode<=Decoded_Nop; + end case; + end if; + end process; + + + opcodeControl: + process(clk, areset) + variable spOffset : unsigned(4 downto 0); + begin + if areset = '1' then + state <= State_Resync; + break <= '0'; + sp <= unsigned(spStart(maxAddrBit downto minAddrBit)); + pc <= (others => '0'); + idim_flag <= '0'; + begin_inst <= '0'; + memAAddr <= (others => '0'); + memBAddr <= (others => '0'); + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + out_mem_writeEnable <= '0'; + out_mem_readEnable <= '0'; + memAWrite <= (others => '0'); + memBWrite <= (others => '0'); + inInterrupt <= '0'; + elsif (clk'event and clk = '1') then + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + -- This saves ca. 100 LUT's, by explicitly declaring that the + -- memAWrite can be left at whatever value if memAWriteEnable is + -- not set. + memAWrite <= (others => DontCareValue); + memBWrite <= (others => DontCareValue); +-- out_mem_addr <= (others => DontCareValue); +-- mem_write <= (others => DontCareValue); + spOffset := (others => DontCareValue); + memAAddr <= (others => DontCareValue); + memBAddr <= (others => DontCareValue); + + out_mem_writeEnable <= '0'; + out_mem_readEnable <= '0'; + begin_inst <= '0'; + out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); + mem_write <= std_logic_vector(memBRead); + + decodedOpcode <= sampledDecodedOpcode; + opcode <= sampledOpcode; + if interrupt='0' then + inInterrupt <= '0'; -- no longer in an interrupt + end if; + + case state is + when State_Execute => + state <= State_Fetch; + -- at this point: + -- memBRead contains opcode word + -- memARead contains top of stack + pc <= pc + 1; + + -- trace + begin_inst <= '1'; + trace_pc <= (others => '0'); + trace_pc(maxAddrBit downto 0) <= std_logic_vector(pc); + trace_opcode <= opcode; + trace_sp <= (others => '0'); + trace_sp(maxAddrBit downto minAddrBit) <= std_logic_vector(sp); + trace_topOfStack <= std_logic_vector(memARead); + trace_topOfStackB <= std_logic_vector(memBRead); + + -- during the next cycle we'll be reading the next opcode + spOffset(4):=not opcode(4); + spOffset(3 downto 0) := unsigned(opcode(3 downto 0)); + + idim_flag <= '0'; + case decodedOpcode is + when Decoded_Interrupt => + sp <= sp - 1; + memAAddr <= sp - 1; + memAWriteEnable <= '1'; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBitIncIO downto 0) <= pc; + pc <= conv_std_logic_vector(32, maxAddrBitIncIo+1); -- interrupt address + report "ZPU jumped to interrupt!" severity note; + when Decoded_Im => + idim_flag <= '1'; + memAWriteEnable <= '1'; + if (idim_flag='0') then + sp <= sp - 1; + memAAddr <= sp-1; + for i in wordSize-1 downto 7 loop + memAWrite(i) <= opcode(6); + end loop; + memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); + else + memAAddr <= sp; + memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0); + memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); + end if; + when Decoded_StoreSP => + memBWriteEnable <= '1'; + memBAddr <= sp+spOffset; + memBWrite <= memARead; + sp <= sp + 1; + state <= State_Resync; + when Decoded_LoadSP => + sp <= sp - 1; + memAAddr <= sp+spOffset; + when Decoded_Emulate => + sp <= sp - 1; + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto 0) <= pc + 1; + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= (others => '0'); + pc(9 downto 5) <= unsigned(opcode(4 downto 0)); + when Decoded_AddSP => + memAAddr <= sp; + memBAddr <= sp+spOffset; + state <= State_AddSP; + when Decoded_Break => + report "Break instruction encountered" severity failure; + break <= '1'; + when Decoded_PushSP => + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + sp <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto minAddrBit) <= sp; + when Decoded_PopPC => + pc <= memARead(maxAddrBit downto 0); + sp <= sp + 1; + state <= State_Resync; + when Decoded_Add => + sp <= sp + 1; + state <= State_Add; + when Decoded_Or => + sp <= sp + 1; + state <= State_Or; + when Decoded_And => + sp <= sp + 1; + state <= State_And; + when Decoded_Load => + if (memARead(ioBit)='1') then + out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); + out_mem_readEnable <= '1'; + state <= State_ReadIO; + else + memAAddr <= memARead(maxAddrBit downto minAddrBit); + end if; + when Decoded_Not => + memAAddr <= sp(maxAddrBit downto minAddrBit); + memAWriteEnable <= '1'; + memAWrite <= not memARead; + when Decoded_Flip => + memAAddr <= sp(maxAddrBit downto minAddrBit); + memAWriteEnable <= '1'; + for i in 0 to wordSize-1 loop + memAWrite(i) <= memARead(wordSize-1-i); + end loop; + when Decoded_Store => + memBAddr <= sp + 1; + sp <= sp + 1; + if (memARead(ioBit)='1') then + state <= State_WriteIO; + else + state <= State_Store; + end if; + when Decoded_PopSP => + sp <= memARead(maxAddrBit downto minAddrBit); + state <= State_Resync; + when Decoded_Nop => + memAAddr <= sp; + when others => + null; + end case; + when State_ReadIO => + if (in_mem_busy = '0') then + state <= State_Fetch; + memAWriteEnable <= '1'; + memAWrite <= unsigned(mem_read); + end if; + when State_WriteIO => + sp <= sp + 1; + out_mem_writeEnable <= '1'; + out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); + mem_write <= std_logic_vector(memBRead); + state <= State_WriteIODone; + when State_WriteIODone => + if (in_mem_busy = '0') then + state <= State_Resync; + end if; + when State_Fetch => + -- We need to resync. During the *next* cycle + -- we'll fetch the opcode @ pc and thus it will + -- be available for State_Execute the cycle after + -- next + memBAddr <= pc(maxAddrBit downto minAddrBit); + state <= State_FetchNext; + when State_FetchNext => + -- at this point memARead contains the value that is either + -- from the top of stack or should be copied to the top of the stack + memAWriteEnable <= '1'; + memAWrite <= memARead; + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Decode; + when State_Decode => + if interrupt='1' and inInterrupt='0' and idim_flag='0' then + -- We got an interrupt, execute interrupt instead of next instruction + decodedOpcode <= Decoded_Interrupt; + end if; + -- during the State_Execute cycle we'll be fetching SP+1 + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Execute; + when State_Store => + sp <= sp + 1; + memAWriteEnable <= '1'; + memAAddr <= memARead(maxAddrBit downto minAddrBit); + memAWrite <= memBRead; + state <= State_Resync; + when State_AddSP => + state <= State_Add; + when State_Add => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead + memBRead; + state <= State_Fetch; + when State_Or => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead or memBRead; + state <= State_Fetch; + when State_Resync => + memAAddr <= sp; + state <= State_Fetch; + when State_And => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead and memBRead; + state <= State_Fetch; + when others => + null; + end case; + + end if; + end process; + + + +end behave; diff --git a/zpu/hdl/zpu4/core/zpupkg.vhd b/zpu/hdl/zpu4/core/zpupkg.vhd new file mode 100644 index 0000000..f3800b0 --- /dev/null +++ b/zpu/hdl/zpu4/core/zpupkg.vhd @@ -0,0 +1,170 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use ieee.numeric_std.all; + +library work; +use work.zpu_config.all; + +package zpupkg is + + -- This bit is set for read/writes to IO + -- FIX!!! eventually this should be set to wordSize-1 so as to + -- to make the address of IO independent of amount of memory + -- reserved for CPU. Requires trivial tweaks in toolchain/runtime + -- libraries. + + constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes + constant maxAddrBit : integer := maxAddrBitIncIO-1; + constant ioBit : integer := maxAddrBit+1; + constant wordSize : integer := 2**wordPower; + constant wordBytes : integer := wordSize/8; + constant minAddrBit : integer := byteBits; + -- configurable internal stack size. Probably going to be 16 after toolchain is done + constant stack_bits : integer := 5; + constant stack_size : integer := 2**stack_bits; + + + component dualport_ram is + port (clk : in std_logic; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memAWrite : in std_logic_vector(wordSize-1 downto 0); + memARead : out std_logic_vector(wordSize-1 downto 0); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memBWrite : in std_logic_vector(wordSize-1 downto 0); + memBRead : out std_logic_vector(wordSize-1 downto 0)); + end component; + + + component dram is + port (clk : in std_logic; + areset : in std_logic; + mem_writeEnable : in std_logic; + mem_readEnable : in std_logic; + mem_addr : in std_logic_vector(maxAddrBit downto 0); + mem_write : in std_logic_vector(wordSize-1 downto 0); + mem_read : out std_logic_vector(wordSize-1 downto 0); + mem_busy : out std_logic; + mem_writeMask : in std_logic_vector(wordBytes-1 downto 0)); + end component; + + + component trace is + port( + clk : in std_logic; + begin_inst : in std_logic; + pc : in std_logic_vector(maxAddrBitIncIO downto 0); + opcode : in std_logic_vector(7 downto 0); + sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit); + memA : in std_logic_vector(wordSize-1 downto 0); + memB : in std_logic_vector(wordSize-1 downto 0); + busy : in std_logic; + intSp : in std_logic_vector(stack_bits-1 downto 0) + ); + end component; + + component zpu_core is + port ( clk : in std_logic; + areset : in std_logic; + enable : in std_logic; + in_mem_busy : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + out_mem_writeEnable : out std_logic; + out_mem_readEnable : out std_logic; + mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + interrupt : in std_logic; + break : out std_logic); + end component; + + + + component timer is + port( + clk : in std_logic; + areset : in std_logic; + we : in std_logic; + din : in std_logic_vector(7 downto 0); + adr : in std_logic_vector(2 downto 0); + dout : out std_logic_vector(7 downto 0)); + end component; + + component zpuio is + port ( areset : in std_logic; + cpu_clk : in std_logic; + clk_status : in std_logic_vector(2 downto 0); + cpu_din : in std_logic_vector(15 downto 0); + cpu_a : in std_logic_vector(20 downto 0); + cpu_we : in std_logic_vector(1 downto 0); + cpu_re : in std_logic; + cpu_dout : inout std_logic_vector(15 downto 0)); + end component; + + + + + -- opcode decode constants + constant OpCode_Im : std_logic_vector(7 downto 7) := "1"; + constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010"; + constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011"; + constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001"; + constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001"; + constant OpCode_Short : std_logic_vector(7 downto 4) := "0000"; + + constant OpCode_Break : std_logic_vector(3 downto 0) := "0000"; + constant OpCode_Shiftleft: std_logic_vector(3 downto 0) := "0001"; + constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010"; + constant OpCode_PushInt : std_logic_vector(3 downto 0) := "0011"; + + constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100"; + constant OpCode_Add : std_logic_vector(3 downto 0) := "0101"; + constant OpCode_And : std_logic_vector(3 downto 0) := "0110"; + constant OpCode_Or : std_logic_vector(3 downto 0) := "0111"; + + constant OpCode_Load : std_logic_vector(3 downto 0) := "1000"; + constant OpCode_Not : std_logic_vector(3 downto 0) := "1001"; + constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010"; + constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011"; + + constant OpCode_Store : std_logic_vector(3 downto 0) := "1100"; + constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101"; + constant OpCode_Compare : std_logic_vector(3 downto 0) := "1110"; + constant OpCode_PopInt : std_logic_vector(3 downto 0) := "1111"; + + constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6)); + constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6)); + constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6)); + constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6)); + + constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6)); + constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6)); + + constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6)); + constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6)); + constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6)); + constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6)); + + constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6)); + constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6)); + + constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6)); + constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6)); + constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6)); + + constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6)); + constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6)); + constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6)); + + constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6)); + constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6)); + constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6)); + + + + constant OpCode_Size : integer := 8; + + + +end zpupkg; diff --git a/zpu/hdl/zpu4/src/dmipssmalltrace.do b/zpu/hdl/zpu4/src/dmipssmalltrace.do deleted file mode 100644 index eb4c6fe..0000000 --- a/zpu/hdl/zpu4/src/dmipssmalltrace.do +++ /dev/null @@ -1,26 +0,0 @@ -set BreakOnAssertion 1 -vlib work - -vcom -93 -explicit zpu_config_trace.vhd -vcom -93 -explicit zpupkg.vhd -vcom -93 -explicit txt_util.vhd -vcom -93 -explicit sim_fpga_top.vhd -vcom -93 -explicit zpu_core_small.vhd -vcom -93 -explicit bram_dmips.vhd -vcom -93 -explicit dram_dmips.vhd -vcom -93 -explicit timer.vhd -vcom -93 -explicit io.vhd -vcom -93 -explicit trace.vhd - - -vsim fpga_top -view wave - -add wave -recursive fpga_top/zpu/* -#--add wave -recursive fpga_top/ioMap/* -#add wave -recursive fpga_top/* -view structure - - -# run ZPU -run 5 ms diff --git a/zpu/hdl/zpu4/src/dmipssmalltrace_ghdl.sh b/zpu/hdl/zpu4/src/dmipssmalltrace_ghdl.sh deleted file mode 100644 index 5e43b64..0000000 --- a/zpu/hdl/zpu4/src/dmipssmalltrace_ghdl.sh +++ /dev/null @@ -1,26 +0,0 @@ -#!/bin/sh - -UNISIM_DIR="'location of GHDL objects for unisim library'/unisim_v93" -IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work -P${UNISIM_DIR}" -MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding" - -if test ! -e work; then - echo "Building work library..." - mkdir work - ghdl -i ${IMPORT_OPTIONS} zpu_config_trace.vhd - ghdl -i ${IMPORT_OPTIONS} zpupkg.vhd - ghdl -i ${IMPORT_OPTIONS} txt_util.vhd - ghdl -i ${IMPORT_OPTIONS} sim_fpga_top.vhd - ghdl -i ${IMPORT_OPTIONS} zpu_core_small.vhd - ghdl -i ${IMPORT_OPTIONS} bram_dmips.vhd - ghdl -i ${IMPORT_OPTIONS} dram_dmips.vhd - ghdl -i ${IMPORT_OPTIONS} timer.vhd - ghdl -i ${IMPORT_OPTIONS} io.vhd - ghdl -i ${IMPORT_OPTIONS} trace.vhd -fi - -echo "Compiling design..." -if ghdl -m ${MAKE_OPTIONS} fpga_top; then - echo "Compilation finished, start simulation with" - echo " ./fpga_top --stop-time=1ms" -fi diff --git a/zpu/hdl/zpu4/src/dmipstrace.do b/zpu/hdl/zpu4/src/dmipstrace.do deleted file mode 100644 index 64cf8fd..0000000 --- a/zpu/hdl/zpu4/src/dmipstrace.do +++ /dev/null @@ -1,30 +0,0 @@ -# Xilinx WebPack modelsim script -# -# cd C:/workspace/zpu/zpu/hdl/zpu4/src -# do dmipstrace.do - -set BreakOnAssertion 1 -vlib work - -vcom -93 -explicit zpu_config_trace.vhd -vcom -93 -explicit zpupkg.vhd -vcom -93 -explicit txt_util.vhd -vcom -93 -explicit sim_fpga_top.vhd -vcom -93 -explicit zpu_core.vhd -vcom -93 -explicit dram_dmips.vhd -vcom -93 -explicit timer.vhd -vcom -93 -explicit io.vhd -vcom -93 -explicit trace.vhd - - -vsim fpga_top -view wave - -add wave -recursive fpga_top/zpu/* -#--add wave -recursive fpga_top/ioMap/* -#add wave -recursive fpga_top/* -view structure - - -# run ZPU -run 5 ms diff --git a/zpu/hdl/zpu4/src/dmipstrace_ghdl.sh b/zpu/hdl/zpu4/src/dmipstrace_ghdl.sh deleted file mode 100644 index 3be392f..0000000 --- a/zpu/hdl/zpu4/src/dmipstrace_ghdl.sh +++ /dev/null @@ -1,25 +0,0 @@ -#!/bin/sh - -UNISIM_DIR="'location of GHDL objects for unisim library'/unisim_v93" -IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work -P${UNISIM_DIR}" -MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding" - -if test ! -e work; then - echo "Building work library..." - mkdir work - ghdl -i ${IMPORT_OPTIONS} zpu_config_trace.vhd - ghdl -i ${IMPORT_OPTIONS} zpupkg.vhd - ghdl -i ${IMPORT_OPTIONS} txt_util.vhd - ghdl -i ${IMPORT_OPTIONS} sim_fpga_top.vhd - ghdl -i ${IMPORT_OPTIONS} zpu_core.vhd - ghdl -i ${IMPORT_OPTIONS} dram_dmips.vhd - ghdl -i ${IMPORT_OPTIONS} timer.vhd - ghdl -i ${IMPORT_OPTIONS} io.vhd - ghdl -i ${IMPORT_OPTIONS} trace.vhd -fi - -echo "Compiling design..." -if ghdl -m ${MAKE_OPTIONS} fpga_top; then - echo "Compilation finished, start simulation with" - echo " ./fpga_top --stop-time=2500us" -fi diff --git a/zpu/hdl/zpu4/src/log.txt b/zpu/hdl/zpu4/src/log.txt deleted file mode 100644 index 7a82879..0000000 --- a/zpu/hdl/zpu4/src/log.txt +++ /dev/null @@ -1,380 +0,0 @@ -H -e -l -l -o - -w -o -r -l -d - -1 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -2 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -1 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -2 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -1 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -2 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -1 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -2 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -1 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -2 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -1 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -2 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -1 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -2 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -1 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -2 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -1 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -2 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -1 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -2 - - - - - - diff --git a/zpu/hdl/zpu4/src/niltrace.vhd b/zpu/hdl/zpu4/src/niltrace.vhd deleted file mode 100644 index 40fc1ca..0000000 --- a/zpu/hdl/zpu4/src/niltrace.vhd +++ /dev/null @@ -1,26 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -use std.textio.all; -use work.zpu_config.all; - - -entity trace is - port( - clk : in std_logic; - begin_inst : in std_logic; - pc : in std_logic_vector(maxAddrBit downto 0); - opcode : in std_logic_vector(7 downto 0); - sp : in std_logic_vector(maxAddrBit downto 2); - memA : in std_logic_vector(wordSize-1 downto 0); - busy : in std_logic); -end trace; - - -architecture behave of trace is - -begin - -end behave; - diff --git a/zpu/hdl/zpu4/src/sim_fpga_top.vhd b/zpu/hdl/zpu4/src/sim_fpga_top.vhd deleted file mode 100644 index 29151af..0000000 --- a/zpu/hdl/zpu4/src/sim_fpga_top.vhd +++ /dev/null @@ -1,188 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 20:15:31 04/14/05 --- Design Name: --- Module Name: fpga_top - behave --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.zpu_config.all; - -entity fpga_top is -end fpga_top; - -use work.zpupkg.all; - -architecture behave of fpga_top is - - -signal clk : std_logic; - -signal areset : std_logic; - - -component zpu_io is - generic ( - log_file: string := "log.txt" - ); - port( - clk : in std_logic; - areset : in std_logic; - busy : out std_logic; - writeEnable : in std_logic; - readEnable : in std_logic; - write : in std_logic_vector(wordSize-1 downto 0); - read : out std_logic_vector(wordSize-1 downto 0); - addr : in std_logic_vector(maxAddrBit downto minAddrBit) - ); -end component; - - - - - -signal mem_busy : std_logic; -signal mem_read : std_logic_vector(wordSize-1 downto 0); -signal mem_write : std_logic_vector(wordSize-1 downto 0); -signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); -signal mem_writeEnable : std_logic; -signal mem_readEnable : std_logic; -signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0); - -signal enable : std_logic; - -signal dram_mem_busy : std_logic; -signal dram_mem_read : std_logic_vector(wordSize-1 downto 0); -signal dram_mem_write : std_logic_vector(wordSize-1 downto 0); -signal dram_mem_writeEnable : std_logic; -signal dram_mem_readEnable : std_logic; -signal dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0); - - -signal io_busy : std_logic; - -signal io_mem_read : std_logic_vector(wordSize-1 downto 0); -signal io_mem_writeEnable : std_logic; -signal io_mem_readEnable : std_logic; - - -signal dram_ready : std_logic; -signal io_ready : std_logic; -signal io_reading : std_logic; - - -signal break : std_logic; - -begin - poweronreset: roc port map (O => areset); - - - - zpu: zpu_core port map ( - clk => clk , - areset => areset, - enable => enable, - in_mem_busy => mem_busy, - mem_read => mem_read, - mem_write => mem_write, - out_mem_addr => mem_addr, - out_mem_writeEnable => mem_writeEnable, - out_mem_readEnable => mem_readEnable, - mem_writeMask => mem_writeMask, - interrupt => '0', - break => break); - - dram_imp: dram port map ( - clk => clk , - areset => areset, - mem_busy => dram_mem_busy, - mem_read => dram_mem_read, - mem_write => mem_write, - mem_addr => mem_addr(maxAddrBit downto 0), - mem_writeEnable => dram_mem_writeEnable, - mem_readEnable => dram_mem_readEnable, - mem_writeMask => mem_writeMask); - - - ioMap: zpu_io port map ( - clk => clk, - areset => areset, - busy => io_busy, - writeEnable => io_mem_writeEnable, - readEnable => io_mem_readEnable, - write => mem_write(wordSize-1 downto 0), - read => io_mem_read, - addr => mem_addr(maxAddrBit downto minAddrBit) - ); - - dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit); - dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit); - io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit); - io_mem_readEnable <= mem_readEnable and mem_addr(ioBit); - mem_busy <= io_busy or dram_mem_busy or io_busy; - - - - -- Memory reads either come from IO or DRAM. We need to pick the right one. - memorycontrol: - process(dram_mem_read, dram_ready, io_ready, io_mem_read) - begin - mem_read <= (others => 'U'); - if dram_ready='1' then - mem_read <= dram_mem_read; - end if; - - if io_ready='1' then - mem_read <= io_mem_read; - end if; - end process; - - - io_ready <= (io_reading or io_mem_readEnable) and not io_busy; - - memoryControlSync: - process(clk, areset) - begin - if areset = '1' then - enable <= '0'; - io_reading <= '0'; - dram_ready <= '0'; - elsif (clk'event and clk = '1') then - enable <= '1'; - io_reading <= io_busy or io_mem_readEnable; - dram_ready<=dram_mem_readEnable; - - end if; - end process; - - -- wiggle the clock @ 100MHz - clock : PROCESS - begin - clk <= '0'; - wait for 5 ns; - clk <= '1'; - wait for 5 ns; - end PROCESS clock; - - -end behave; diff --git a/zpu/hdl/zpu4/src/simzpu_medium.do b/zpu/hdl/zpu4/src/simzpu_medium.do deleted file mode 100644 index a6c1fe2..0000000 --- a/zpu/hdl/zpu4/src/simzpu_medium.do +++ /dev/null @@ -1,28 +0,0 @@ -# Xilinx WebPack modelsim script -# -# cd C:/workspace/zpu/zpu/hdl/zpu4/src -# do simzpu_medium.do - -set BreakOnAssertion 1 -vlib work - -vcom -93 -explicit zpu_config_trace.vhd -vcom -93 -explicit zpupkg.vhd -vcom -93 -explicit txt_util.vhd -vcom -93 -explicit sim_fpga_top.vhd -vcom -93 -explicit zpu_core.vhd -vcom -93 -explicit dram_hello.vhd -vcom -93 -explicit timer.vhd -vcom -93 -explicit io.vhd -vcom -93 -explicit trace.vhd - -# run ZPU -vsim fpga_top -view wave -add wave -recursive fpga_top/zpu/* -#add wave -recursive fpga_top/* -view structure -#view signals - -# Enough to run tiny programs -run 1000 ms diff --git a/zpu/hdl/zpu4/src/simzpu_medium_ghdl.sh b/zpu/hdl/zpu4/src/simzpu_medium_ghdl.sh deleted file mode 100644 index 7a7f3df..0000000 --- a/zpu/hdl/zpu4/src/simzpu_medium_ghdl.sh +++ /dev/null @@ -1,25 +0,0 @@ -#!/bin/sh - -UNISIM_DIR="'location of GHDL objects for unisim library'/unisim_v93" -IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work -P${UNISIM_DIR}" -MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding" - -if test ! -e work; then - echo "Building work library..." - mkdir work - ghdl -i ${IMPORT_OPTIONS} zpu_config_trace.vhd - ghdl -i ${IMPORT_OPTIONS} zpupkg.vhd - ghdl -i ${IMPORT_OPTIONS} txt_util.vhd - ghdl -i ${IMPORT_OPTIONS} sim_fpga_top.vhd - ghdl -i ${IMPORT_OPTIONS} zpu_core.vhd - ghdl -i ${IMPORT_OPTIONS} dram_hello.vhd - ghdl -i ${IMPORT_OPTIONS} timer.vhd - ghdl -i ${IMPORT_OPTIONS} io.vhd - ghdl -i ${IMPORT_OPTIONS} trace.vhd -fi - -echo "Compiling design..." -if ghdl -m ${MAKE_OPTIONS} fpga_top; then - echo "Compilation finished, start simulation with" - echo " ./fpga_top --stop-time=1ms" -fi diff --git a/zpu/hdl/zpu4/src/testlut.vhd b/zpu/hdl/zpu4/src/testlut.vhd deleted file mode 100644 index 668efcc..0000000 --- a/zpu/hdl/zpu4/src/testlut.vhd +++ /dev/null @@ -1,114 +0,0 @@ --- Company: Zylin AS --- --- Hooks up the ZPU to physical pads to ensure that it is not optimized to --- oblivion. This is purely to have something to measure LUT usage against. --- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - -entity ic300 is - port ( -- Clock inputs - cpu_clk_p : in std_logic; - - -- CPU interface signals - cpu_a_p : in std_logic_vector(20 downto 0); - cpu_wr_n_p : in std_logic_vector(1 downto 0); - cpu_cs_n_p : in std_logic_vector(3 downto 1); - cpu_oe_n_p : in std_logic; - cpu_d_p : out std_logic_vector(15 downto 0); - cpu_irq_p : out std_logic_vector(1 downto 0); - cpu_fiq_p : out std_logic; - cpu_wait_n_p : out std_logic; - - sdr_clk_fb_p : in std_logic -- DDR clock feedback - ); -end ic300; - -architecture behave of ic300 is - - -signal io_busy : std_logic; -signal io_read : std_logic_vector(7 downto 0); -signal io_write : std_logic_vector(7 downto 0); -signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit); -signal io_writeEnable : std_logic; -signal io_readEnable : std_logic; - - -signal cpu_we : std_logic_vector(1 downto 0); -signal cpu_re : std_logic; -signal areset : std_logic; - --- Clock module signals -signal clk_status : std_logic_vector(2 downto 0); -signal cpu_clk : std_logic; -signal cpu_clk_2x : std_logic; -signal cpu_clk_4x : std_logic; -signal ddr_in_clk : std_logic; - - --- Internal CPU interface signals -signal cpu_din : std_logic_vector(15 downto 0); -signal cpu_dout : std_logic_vector(15 downto 0); -signal cpu_a : std_logic_vector(20 downto 0); - -signal dummy : std_logic_vector(maxAddrBit downto minAddrBit+5); - -signal dummy2 : std_logic_vector(wordSize-1 downto 0); -signal dummy3 : std_logic_vector(wordSize-1 downto 0); -signal dummy4 : std_logic_vector(wordSize-1 downto 0); -begin - - areset <= '0'; -- MUST BE CHANGED TO SOMETHING CORRECT - --- cpu_d_p <= (others => '0'); - cpu_irq_p <= (others => '0'); - cpu_fiq_p <= '0'; - cpu_wait_n_p <= '0'; - - cpu_d_p(15 downto 15) <= (others => '0'); - - -- delay signals going out/in w/1 clk so the - -- ZPU does not have to drive those pins. - -- - -- these registers can be placed close to the ZPU and these - -- registers then have a full clock to drive the pins. - process(cpu_clk_p, areset) - begin - if (cpu_clk_p'event and cpu_clk_p = '1') then - cpu_d_p(0) <= io_writeEnable; - cpu_d_p(1) <= io_readEnable; - cpu_d_p(9 downto 2) <= io_write; - io_read <= cpu_a_p(7 downto 0); - -- 32 read/write registers is plenty realisitic for a minimal size - -- soft-CPU - cpu_d_p(14 downto 10) <= io_addr(minAddrBit+4 downto minAddrBit); - end if; - end process; - - - zpu: zpu_core port map ( - clk => cpu_clk_p , - areset => areset, - enable => '1', - - in_mem_busy => '0', - out_mem_writeEnable => io_writeEnable, - out_mem_readEnable => io_readEnable, - mem_write(7 downto 0) => io_write, - mem_write(wordSize-1 downto 8) => dummy3(wordSize-1 downto 8), - mem_read(7 downto 0) => io_read, - mem_read(wordSize-1 downto 8) => dummy2(wordSize-1 downto 8), - out_mem_addr(maxAddrBitIncIO) => dummy4(maxAddrBitIncIO), - out_mem_addr(minAddrBit-1 downto 0) => dummy4(minAddrBit-1 downto 0) , - out_mem_addr(maxAddrBit downto minAddrBit) => io_addr, - interrupt => '0' - ); - - -end behave; diff --git a/zpu/hdl/zpu4/src/zpu_config.vhd b/zpu/hdl/zpu4/src/zpu_config.vhd deleted file mode 100644 index a13c0bf..0000000 --- a/zpu/hdl/zpu4/src/zpu_config.vhd +++ /dev/null @@ -1,16 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -package zpu_config is - -- generate trace output or not. - constant Generate_Trace : boolean := false; - constant wordPower : integer := 5; - -- during simulation, set this to '0' to get matching trace.txt - constant DontCareValue : std_logic := 'X'; - -- Clock frequency in MHz. - constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64"; - -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) - constant maxAddrBitIncIO : integer := 15; - -end zpu_config; diff --git a/zpu/hdl/zpu4/src/zpu_core.vhd b/zpu/hdl/zpu4/src/zpu_core.vhd deleted file mode 100644 index 37fa2d1..0000000 --- a/zpu/hdl/zpu4/src/zpu_core.vhd +++ /dev/null @@ -1,897 +0,0 @@ - --- Company: ZPU4 generic memory interface CPU --- Engineer: Øyvind Harboe - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use ieee.numeric_std.all; - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - - --- mem_writeEnable - set to '1' for a single cycle to send off a write request. --- mem_write is valid only while mem_writeEnable='1'. --- mem_readEnable - set to '1' for a single cycle to send off a read request. --- --- mem_busy - It is illegal to send off a read/write request when mem_busy='1'. --- Set to '0' when mem_read is valid after a read request. --- If it goes to '1'(busy), it is on the cycle after mem_read/writeEnable --- is '1'. --- mem_addr - address for read/write request --- mem_read - read data. Valid only on the cycle after mem_busy='0' after --- mem_readEnable='1' for a single cycle. --- mem_write - data to write --- mem_writeMask - set to '1' for those bits that are to be written to memory upon --- write request --- break - set to '1' when CPU hits break instruction --- interrupt - set to '1' until interrupts are cleared by CPU. - - - - -entity zpu_core is - Port ( clk : in std_logic; - areset : in std_logic; - enable : in std_logic; - in_mem_busy : in std_logic; - mem_read : in std_logic_vector(wordSize-1 downto 0); - mem_write : out std_logic_vector(wordSize-1 downto 0); - out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); - out_mem_writeEnable : out std_logic; - out_mem_readEnable : out std_logic; - mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); - interrupt : in std_logic; - break : out std_logic); -end zpu_core; - -architecture behave of zpu_core is - -type InsnType is -( -State_AddTop, -State_Dup, -State_DupStackB, -State_Pop, -State_Popdown, -State_Add, -State_Or, -State_And, -State_Store, -State_AddSP, -State_Shift, -State_Nop, -State_Im, -State_LoadSP, -State_StoreSP, -State_Emulate, -State_Load, -State_PushPC, -State_PushSP, -State_PopPC, -State_PopPCRel, -State_Not, -State_Flip, -State_PopSP, -State_Neqbranch, -State_Eq, -State_Loadb, -State_Mult, -State_Lessthan, -State_Lessthanorequal, -State_Ulessthanorequal, -State_Ulessthan, -State_Pushspadd, -State_Call, -State_Callpcrel, -State_Sub, -State_Break, -State_Storeb, -State_InsnFetch -); - -type StateType is -( -State_Load2, -State_Popped, -State_LoadSP2, -State_LoadSP3, -State_AddSP2, -State_Fetch, -State_Execute, -State_Decode, -State_Decode2, -State_Resync, - -State_StoreSP2, -State_Resync2, -State_Resync3, -State_Loadb2, -State_Storeb2, -State_Mult2, -State_Mult3, -State_Mult5, -State_Mult4, -State_BinaryOpResult2, -State_BinaryOpResult, -State_Idle -); - - -signal pc : unsigned(maxAddrBitIncIO downto 0); -signal sp : unsigned(maxAddrBitIncIO downto minAddrBit); -signal incSp : unsigned(maxAddrBitIncIO downto minAddrBit); -signal incIncSp : unsigned(maxAddrBitIncIO downto minAddrBit); -signal decSp : unsigned(maxAddrBitIncIO downto minAddrBit); -signal stackA : unsigned(wordSize-1 downto 0); -signal binaryOpResult : unsigned(wordSize-1 downto 0); -signal binaryOpResult2 : unsigned(wordSize-1 downto 0); -signal multResult2 : unsigned(wordSize-1 downto 0); -signal multResult3 : unsigned(wordSize-1 downto 0); -signal multResult : unsigned(wordSize-1 downto 0); -signal multA : unsigned(wordSize-1 downto 0); -signal multB : unsigned(wordSize-1 downto 0); -signal stackB : unsigned(wordSize-1 downto 0); -signal idim_flag : std_logic; -signal busy : std_logic; -signal mem_writeEnable : std_logic; -signal mem_readEnable : std_logic; -signal mem_addr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal mem_delayAddr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal mem_delayReadEnable : std_logic; - -signal decodeWord : std_logic_vector(wordSize-1 downto 0); - - -signal state : StateType; -signal insn : InsnType; -type InsnArray is array(0 to wordBytes-1) of InsnType; -signal decodedOpcode : InsnArray; - -type OpcodeArray is array(0 to wordBytes-1) of std_logic_vector(7 downto 0); - -signal opcode : OpcodeArray; - - - - -signal begin_inst : std_logic; -signal trace_opcode : std_logic_vector(7 downto 0); -signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); -signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); -signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); - --- state machine. - -begin - - - traceFileGenerate: - if Generate_Trace generate - trace_file: trace port map ( - clk => clk, - begin_inst => begin_inst, - pc => trace_pc, - opcode => trace_opcode, - sp => trace_sp, - memA => trace_topOfStack, - memB => trace_topOfStackB, - busy => busy, - intsp => (others => 'U') - ); - end generate; - - - -- the memory subsystem will tell us one cycle later whether or - -- not it is busy - out_mem_writeEnable <= mem_writeEnable; - out_mem_readEnable <= mem_readEnable; - out_mem_addr(maxAddrBitIncIO downto minAddrBit) <= mem_addr; - out_mem_addr(minAddrBit-1 downto 0) <= (others => '0'); - - incSp <= sp + 1; - incIncSp <= sp + 2; - decSp <= sp - 1; - - - opcodeControl: - process(clk, areset) - variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); - variable spOffset : unsigned(4 downto 0); - variable tSpOffset : unsigned(4 downto 0); - variable nextPC : unsigned(maxAddrBitIncIO downto 0); - variable tNextState : InsnType; - variable tDecodedOpcode : InsnArray; - variable tMultResult : unsigned(wordSize*2-1 downto 0); - begin - if areset = '1' then - state <= State_Idle; - break <= '0'; - sp <= unsigned(spStart(maxAddrBitIncIO downto minAddrBit)); - - pc <= (others => '0'); - idim_flag <= '0'; - begin_inst <= '0'; - mem_writeEnable <= '0'; - mem_readEnable <= '0'; - multA <= (others => '0'); - multB <= (others => '0'); - mem_writeMask <= (others => '1'); - elsif (clk'event and clk = '1') then - -- we must multiply unconditionally to get pipelined multiplication - tMultResult := multA * multB; - multResult3 <= multResult2; - multResult2 <= multResult; - multResult <= tMultResult(wordSize-1 downto 0); - - - binaryOpResult2 <= binaryOpResult; -- pipeline a bit. - - - multA <= (others => DontCareValue); - multB <= (others => DontCareValue); - - - mem_addr <= (others => DontCareValue); - mem_readEnable <='0'; - mem_writeEnable <='0'; - mem_write <= (others => DontCareValue); - - if (mem_writeEnable = '1') and (mem_readEnable = '1') then - report "read/write collision" severity failure; - end if; - - - - - spOffset(4):=not opcode(to_integer(pc(byteBits-1 downto 0)))(4); - spOffset(3 downto 0):=unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(3 downto 0)); - nextPC := pc + 1; - - -- prepare trace snapshot - trace_opcode <= opcode(to_integer(pc(byteBits-1 downto 0))); - trace_pc <= std_logic_vector(pc); - trace_sp <= std_logic_vector(sp); - trace_topOfStack <= std_logic_vector(stackA); - trace_topOfStackB <= std_logic_vector(stackB); - begin_inst <= '0'; - - - case state is - when State_Idle => - if enable='1' then - state <= State_Resync; - end if; - -- Initial state of ZPU, fetch top of stack + first instruction - when State_Resync => - if in_mem_busy='0' then - mem_addr <= std_logic_vector(sp); - mem_readEnable <= '1'; - state <= State_Resync2; - end if; - when State_Resync2 => - if in_mem_busy='0' then - stackA <= unsigned(mem_read); - mem_addr <= std_logic_vector(incSp); - mem_readEnable <= '1'; - state <= State_Resync3; - end if; - when State_Resync3 => - if in_mem_busy='0' then - stackB <= unsigned(mem_read); - mem_addr <= std_logic_vector(pc(maxAddrBitIncIO downto minAddrBit)); - mem_readEnable <= '1'; - state <= State_Decode; - end if; - when State_Decode => - if in_mem_busy='0' then - decodeWord <= mem_read; - state <= State_Decode2; - end if; - when State_Decode2 => - -- decode 4 instructions in parallel - for i in 0 to wordBytes-1 loop - tOpcode := decodeWord((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8); - - tSpOffset(4):=not tOpcode(4); - tSpOffset(3 downto 0):=unsigned(tOpcode(3 downto 0)); - - opcode(i) <= tOpcode; - if (tOpcode(7 downto 7)=OpCode_Im) then - tNextState:=State_Im; - elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then - if tSpOffset = 0 then - tNextState := State_Pop; - elsif tSpOffset=1 then - tNextState := State_PopDown; - else - tNextState :=State_StoreSP; - end if; - elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then - if tSpOffset = 0 then - tNextState :=State_Dup; - elsif tSpOffset = 1 then - tNextState :=State_DupStackB; - else - tNextState :=State_LoadSP; - end if; - elsif (tOpcode(7 downto 5)=OpCode_Emulate) then - tNextState :=State_Emulate; - if tOpcode(5 downto 0)=OpCode_Neqbranch then - tNextState :=State_Neqbranch; - elsif tOpcode(5 downto 0)=OpCode_Eq then - tNextState :=State_Eq; - elsif tOpcode(5 downto 0)=OpCode_Lessthan then - tNextState :=State_Lessthan; - elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then - --tNextState :=State_Lessthanorequal; - elsif tOpcode(5 downto 0)=OpCode_Ulessthan then - tNextState :=State_Ulessthan; - elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then - --tNextState :=State_Ulessthanorequal; - elsif tOpcode(5 downto 0)=OpCode_Loadb then - tNextState :=State_Loadb; - elsif tOpcode(5 downto 0)=OpCode_Mult then - tNextState :=State_Mult; - elsif tOpcode(5 downto 0)=OpCode_Storeb then - tNextState :=State_Storeb; - elsif tOpcode(5 downto 0)=OpCode_Pushspadd then - tNextState :=State_Pushspadd; - elsif tOpcode(5 downto 0)=OpCode_Callpcrel then - tNextState :=State_Callpcrel; - elsif tOpcode(5 downto 0)=OpCode_Call then - --tNextState :=State_Call; - elsif tOpcode(5 downto 0)=OpCode_Sub then - tNextState :=State_Sub; - elsif tOpcode(5 downto 0)=OpCode_PopPCRel then - --tNextState :=State_PopPCRel; - end if; - elsif (tOpcode(7 downto 4)=OpCode_AddSP) then - if tSpOffset = 0 then - tNextState := State_Shift; - elsif tSpOffset = 1 then - tNextState := State_AddTop; - else - tNextState :=State_AddSP; - end if; - else - case tOpcode(3 downto 0) is - when OpCode_Nop => - tNextState :=State_Nop; - when OpCode_PushSP => - tNextState :=State_PushSP; - when OpCode_PopPC => - tNextState :=State_PopPC; - when OpCode_Add => - tNextState :=State_Add; - when OpCode_Or => - tNextState :=State_Or; - when OpCode_And => - tNextState :=State_And; - when OpCode_Load => - tNextState :=State_Load; - when OpCode_Not => - tNextState :=State_Not; - when OpCode_Flip => - tNextState :=State_Flip; - when OpCode_Store => - tNextState :=State_Store; - when OpCode_PopSP => - tNextState :=State_PopSP; - when others => - tNextState := State_Break; - - end case; - end if; - tDecodedOpcode(i) := tNextState; - - end loop; - - insn <= tDecodedOpcode(to_integer(pc(byteBits-1 downto 0))); - - -- once we wrap, we need to fetch - tDecodedOpcode(0) := State_InsnFetch; - - decodedOpcode <= tDecodedOpcode; - state <= State_Execute; - - - - -- Each instruction must: - -- - -- 1. set idim_flag - -- 2. increase pc if applicable - -- 3. set next state if appliable - -- 4. do it's operation - - when State_Execute => - insn <= decodedOpcode(to_integer(nextPC(byteBits-1 downto 0))); - - case insn is - when State_InsnFetch => - state <= State_Fetch; - when State_Im => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '1'; - pc <= pc + 1; - - if idim_flag='1' then - stackA(wordSize-1 downto 7) <= stackA(wordSize-8 downto 0); - stackA(6 downto 0) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(6 downto 0)); - else - mem_writeEnable <= '1'; - mem_addr <= std_logic_vector(incSp); - mem_write <= std_logic_vector(stackB); - stackB <= stackA; - sp <= decSp; - for i in wordSize-1 downto 7 loop - stackA(i) <= opcode(to_integer(pc(byteBits-1 downto 0)))(6); - end loop; - stackA(6 downto 0) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(6 downto 0)); - end if; - end if; - when State_StoreSP => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_StoreSP2; - - mem_writeEnable <= '1'; - mem_addr <= std_logic_vector(sp+spOffset); - mem_write <= std_logic_vector(stackA); - stackA <= stackB; - sp <= incSp; - end if; - - - when State_LoadSP => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_LoadSP2; - - sp <= decSp; - mem_writeEnable <= '1'; - mem_addr <= std_logic_vector(incSp); - mem_write <= std_logic_vector(stackB); - end if; - when State_Emulate => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - sp <= decSp; - mem_writeEnable <= '1'; - mem_addr <= std_logic_vector(incSp); - mem_write <= std_logic_vector(stackB); - stackA <= (others => DontCareValue); - stackA(maxAddrBitIncIO downto 0) <= pc + 1; - stackB <= stackA; - - -- The emulate address is: - -- 98 7654 3210 - -- 0000 00aa aaa0 0000 - pc <= (others => '0'); - pc(9 downto 5) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(4 downto 0)); - state <= State_Fetch; - end if; - when State_Callpcrel => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - stackA <= (others => DontCareValue); - stackA(maxAddrBitIncIO downto 0) <= pc + 1; - - pc <= pc + stackA(maxAddrBitIncIO downto 0); - state <= State_Fetch; - end if; - when State_Call => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - stackA <= (others => DontCareValue); - stackA(maxAddrBitIncIO downto 0) <= pc + 1; - pc <= stackA(maxAddrBitIncIO downto 0); - state <= State_Fetch; - end if; - when State_AddSP => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_AddSP2; - - mem_readEnable <= '1'; - mem_addr <= std_logic_vector(sp+spOffset); - end if; - when State_PushSP => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - sp <= decSp; - stackA <= (others => '0'); - stackA(maxAddrBitIncIO downto minAddrBit) <= sp; - stackB <= stackA; - mem_writeEnable <= '1'; - mem_addr <= std_logic_vector(incSp); - mem_write <= std_logic_vector(stackB); - end if; - when State_PopPC => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= stackA(maxAddrBitIncIO downto 0); - sp <= incSp; - - mem_writeEnable <= '1'; - mem_addr <= std_logic_vector(incSp); - mem_write <= std_logic_vector(stackB); - state <= State_Resync; - end if; - when State_PopPCRel => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= stackA(maxAddrBitIncIO downto 0) + pc; - sp <= incSp; - - mem_writeEnable <= '1'; - mem_addr <= std_logic_vector(incSp); - mem_write <= std_logic_vector(stackB); - state <= State_Resync; - end if; - when State_Add => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - stackA <= stackA + stackB; - - mem_readEnable <= '1'; - mem_addr <= std_logic_vector(incIncSp); - sp <= incSp; - state <= State_Popped; - end if; - when State_Sub => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - binaryOpResult <= stackB - stackA; - state <= State_BinaryOpResult; - end if; - when State_Pop => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - mem_addr <= std_logic_vector(incIncSp); - mem_readEnable <= '1'; - sp <= incSp; - stackA <= stackB; - state <= State_Popped; - end if; - when State_PopDown => - if in_mem_busy='0' then - -- PopDown leaves top of stack unchanged - begin_inst <= '1'; - idim_flag <= '0'; - mem_addr <= std_logic_vector(incIncSp); - mem_readEnable <= '1'; - sp <= incSp; - state <= State_Popped; - end if; - when State_Or => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - stackA <= stackA or stackB; - mem_readEnable <= '1'; - mem_addr <= std_logic_vector(incIncSp); - sp <= incSp; - state <= State_Popped; - end if; - when State_And => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - - stackA <= stackA and stackB; - mem_readEnable <= '1'; - mem_addr <= std_logic_vector(incIncSp); - sp <= incSp; - state <= State_Popped; - end if; - when State_Eq => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (stackA=stackB) then - binaryOpResult(0) <= '1'; - end if; - state <= State_BinaryOpResult; - end if; - when State_Ulessthan => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (stackA - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (stackA<=stackB) then - binaryOpResult(0) <= '1'; - end if; - state <= State_BinaryOpResult; - end if; - when State_Lessthan => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (signed(stackA) - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (signed(stackA)<=signed(stackB)) then - binaryOpResult(0) <= '1'; - end if; - state <= State_BinaryOpResult; - end if; - when State_Load => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_Load2; - - mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); - mem_readEnable <= '1'; - end if; - - when State_Dup => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - sp <= decSp; - stackB <= stackA; - mem_write <= std_logic_vector(stackB); - mem_addr <= std_logic_vector(incSp); - mem_writeEnable <= '1'; - end if; - when State_DupStackB => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - sp <= decSp; - stackA <= stackB; - stackB <= stackA; - mem_write <= std_logic_vector(stackB); - mem_addr <= std_logic_vector(incSp); - mem_writeEnable <= '1'; - end if; - when State_Store => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); - mem_write <= std_logic_vector(stackB); - mem_writeEnable <= '1'; - sp <= incIncSp; - state <= State_Resync; - end if; - when State_PopSP => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - mem_write <= std_logic_vector(stackB); - mem_addr <= std_logic_vector(incSp); - mem_writeEnable <= '1'; - sp <= stackA(maxAddrBitIncIO downto minAddrBit); - state <= State_Resync; - end if; - when State_Nop => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - when State_Not => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - stackA <= not stackA; - when State_Flip => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - for i in 0 to wordSize-1 loop - stackA(i) <= stackA(wordSize-1-i); - end loop; - when State_AddTop => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - stackA <= stackA + stackB; - when State_Shift => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0); - stackA(0) <= '0'; - when State_Pushspadd => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - stackA <= (others => '0'); - stackA(maxAddrBitIncIO downto minAddrBit) <= stackA(maxAddrBitIncIO-minAddrBit downto 0)+sp; - when State_Neqbranch => - -- branches are almost always taken as they form loops - begin_inst <= '1'; - idim_flag <= '0'; - sp <= incIncSp; - if (stackB/=0) then - pc <= stackA(maxAddrBitIncIO downto 0) + pc; - else - pc <= pc + 1; - end if; - -- need to fetch stack again. - state <= State_Resync; - when State_Mult => - begin_inst <= '1'; - idim_flag <= '0'; - - multA <= stackA; - multB <= stackB; - state <= State_Mult2; - when State_Break => - report "Break instruction encountered" severity failure; - break <= '1'; - - when State_Loadb => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_Loadb2; - - mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); - mem_readEnable <= '1'; - end if; - when State_Storeb => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_Storeb2; - - mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); - mem_readEnable <= '1'; - end if; - - when others => - sp <= (others => DontCareValue); - report "Illegal instruction" severity failure; - break <= '1'; - end case; - - - when State_StoreSP2 => - if in_mem_busy='0' then - mem_addr <= std_logic_vector(incSp); - mem_readEnable <= '1'; - state <= State_Popped; - end if; - when State_LoadSP2 => - if in_mem_busy='0' then - state <= State_LoadSP3; - mem_readEnable <= '1'; - mem_addr <= std_logic_vector(sp+spOffset+1); - end if; - when State_LoadSP3 => - if in_mem_busy='0' then - pc <= pc + 1; - state <= State_Execute; - stackB <= stackA; - stackA <= unsigned(mem_read); - end if; - when State_AddSP2 => - if in_mem_busy='0' then - pc <= pc + 1; - state <= State_Execute; - stackA <= stackA + unsigned(mem_read); - end if; - when State_Load2 => - if in_mem_busy='0' then - stackA <= unsigned(mem_read); - pc <= pc + 1; - state <= State_Execute; - end if; - when State_Loadb2 => - if in_mem_busy='0' then - stackA <= (others => '0'); - stackA(7 downto 0) <= unsigned(mem_read(((wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8)); - pc <= pc + 1; - state <= State_Execute; - end if; - when State_Storeb2 => - if in_mem_busy='0' then - mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); - mem_write <= mem_read; - mem_write(((wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8) <= std_logic_vector(stackB(7 downto 0)); - mem_writeEnable <= '1'; - pc <= pc + 1; - sp <= incIncSp; - state <= State_Resync; - end if; - when State_Fetch => - if in_mem_busy='0' then - mem_addr <= std_logic_vector(pc(maxAddrBitIncIO downto minAddrBit)); - mem_readEnable <= '1'; - state <= State_Decode; - end if; - when State_Mult2 => - state <= State_Mult3; - when State_Mult3 => - state <= State_Mult4; - when State_Mult4 => - state <= State_Mult5; - when State_Mult5 => - if in_mem_busy='0' then - stackA <= multResult3; - mem_readEnable <= '1'; - mem_addr <= std_logic_vector(incIncSp); - sp <= incSp; - state <= State_Popped; - end if; - when State_BinaryOpResult => - state <= State_BinaryOpResult2; - when State_BinaryOpResult2 => - mem_readEnable <= '1'; - mem_addr <= std_logic_vector(incIncSp); - sp <= incSp; - stackA <= binaryOpResult2; - state <= State_Popped; - when State_Popped => - if in_mem_busy='0' then - pc <= pc + 1; - stackB <= unsigned(mem_read); - state <= State_Execute; - end if; - when others => - sp <= (others => DontCareValue); - report "Illegal state" severity failure; - break <= '1'; - end case; - end if; - end process; - - - -end behave; diff --git a/zpu/hdl/zpu4/src/zpu_core_small.vhd b/zpu/hdl/zpu4/src/zpu_core_small.vhd deleted file mode 100644 index 9cda01c..0000000 --- a/zpu/hdl/zpu4/src/zpu_core_small.vhd +++ /dev/null @@ -1,464 +0,0 @@ --- Company: ZPU3 --- Engineer: Øyvind Harboe - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use ieee.numeric_std.all; - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - - -entity zpu_core is - Port ( clk : in std_logic; - areset : in std_logic; - enable : in std_logic; - in_mem_busy : in std_logic; - mem_read : in std_logic_vector(wordSize-1 downto 0); - mem_write : out std_logic_vector(wordSize-1 downto 0); - out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); - out_mem_writeEnable : out std_logic; - out_mem_readEnable : out std_logic; - mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); - interrupt : in std_logic; - break : out std_logic); -end zpu_core; - -architecture behave of zpu_core is - -signal readIO : std_logic; - - - -signal memAWriteEnable : std_logic; -signal memAAddr : unsigned(maxAddrBit downto minAddrBit); -signal memAWrite : unsigned(wordSize-1 downto 0); -signal memARead : unsigned(wordSize-1 downto 0); -signal memBWriteEnable : std_logic; -signal memBAddr : unsigned(maxAddrBit downto minAddrBit); -signal memBWrite : unsigned(wordSize-1 downto 0); -signal memBRead : unsigned(wordSize-1 downto 0); - - - -signal pc : unsigned(maxAddrBit downto 0); -signal sp : unsigned(maxAddrBit downto minAddrBit); - -signal idim_flag : std_logic; - ---signal storeToStack : std_logic; ---signal fetchNextInstruction : std_logic; ---signal extraCycle : std_logic; -signal busy : std_logic; ---signal fetching : std_logic; - -signal begin_inst : std_logic; - - - -signal trace_opcode : std_logic_vector(7 downto 0); -signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); -signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); -signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); - --- state machine. -type State_Type is -( -State_Fetch, -State_WriteIODone, -State_Execute, -State_StoreToStack, -State_Add, -State_Or, -State_And, -State_Store, -State_ReadIO, -State_WriteIO, -State_Load, -State_FetchNext, -State_AddSP, -State_ReadIODone, -State_Decode, -State_Resync -); - -type DecodedOpcodeType is -( -Decoded_Nop, -Decoded_Im, -Decoded_ImShift, -Decoded_LoadSP, -Decoded_StoreSP , -Decoded_AddSP, -Decoded_Emulate, -Decoded_Break, -Decoded_PushSP, -Decoded_PopPC, -Decoded_Add, -Decoded_Or, -Decoded_And, -Decoded_Load, -Decoded_Not, -Decoded_Flip, -Decoded_Store, -Decoded_PopSP -); - - - -signal sampledOpcode : std_logic_vector(OpCode_Size-1 downto 0); -signal opcode : std_logic_vector(OpCode_Size-1 downto 0); - -signal decodedOpcode : DecodedOpcodeType; -signal sampledDecodedOpcode : DecodedOpcodeType; - - -signal state : State_Type; - -subtype AddrBitBRAM_range is natural range maxAddrBitBRAM downto minAddrBit; -signal memAAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); -signal memAWrite_stdlogic : std_logic_vector(memAWrite'range); -signal memARead_stdlogic : std_logic_vector(memARead'range); -signal memBAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); -signal memBWrite_stdlogic : std_logic_vector(memBWrite'range); -signal memBRead_stdlogic : std_logic_vector(memBRead'range); - --- debug -subtype index is integer range 0 to 3; -signal tOpcode_sel : index; - - -begin - traceFileGenerate: - if Generate_Trace generate - trace_file: trace port map ( - clk => clk, - begin_inst => begin_inst, - pc => trace_pc, - opcode => trace_opcode, - sp => trace_sp, - memA => trace_topOfStack, - memB => trace_topOfStackB, - busy => busy, - intsp => (others => 'U') - ); - end generate; - - -- not used in this design - mem_writeMask <= (others => '1'); - - memAAddr_stdlogic <= std_logic_vector(memAAddr(AddrBitBRAM_range)); - memAWrite_stdlogic <= std_logic_vector(memAWrite); - memBAddr_stdlogic <= std_logic_vector(memBAddr(AddrBitBRAM_range)); - memBWrite_stdlogic <= std_logic_vector(memBWrite); - memory: dualport_ram port map ( - clk => clk, - memAWriteEnable => memAWriteEnable, - memAAddr => memAAddr_stdlogic, - memAWrite => memAWrite_stdlogic, - memARead => memARead_stdlogic, - memBWriteEnable => memBWriteEnable, - memBAddr => memBAddr_stdlogic, - memBWrite => memBWrite_stdlogic, - memBRead => memBRead_stdlogic - ); - memARead <= unsigned(memARead_stdlogic); - memBRead <= unsigned(memBRead_stdlogic); - -tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0)); - - - decodeControl: - process(memBRead, pc,tOpcode_sel) - variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); - begin - -- not worked with synopsys - -- tOpcode := std_logic_vector(memBRead((wordBytes-1-to_integer(pc(minAddrBit-1 downto 0))+1)*8-1 downto (wordBytes-1-to_integer(pc(minAddrBit-1 downto 0)))*8)); - -- use full case - case (tOpcode_sel) is - when 0 => tOpcode := std_logic_vector(memBRead(31 downto 24)); - when 1 => tOpcode := std_logic_vector(memBRead(23 downto 16)); - when 2 => tOpcode := std_logic_vector(memBRead(15 downto 8)); - when 3 => tOpcode := std_logic_vector(memBRead(7 downto 0)); - when others => tOpcode := std_logic_vector(memBRead(7 downto 0)); - end case; - sampledOpcode <= tOpcode; - - if (tOpcode(7 downto 7)=OpCode_Im) then - sampledDecodedOpcode<=Decoded_Im; - elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then - sampledDecodedOpcode<=Decoded_StoreSP; - elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then - sampledDecodedOpcode<=Decoded_LoadSP; - elsif (tOpcode(7 downto 5)=OpCode_Emulate) then - sampledDecodedOpcode<=Decoded_Emulate; - elsif (tOpcode(7 downto 4)=OpCode_AddSP) then - sampledDecodedOpcode<=Decoded_AddSP; - else - case tOpcode(3 downto 0) is - when OpCode_Break => - sampledDecodedOpcode<=Decoded_Break; - when OpCode_PushSP => - sampledDecodedOpcode<=Decoded_PushSP; - when OpCode_PopPC => - sampledDecodedOpcode<=Decoded_PopPC; - when OpCode_Add => - sampledDecodedOpcode<=Decoded_Add; - when OpCode_Or => - sampledDecodedOpcode<=Decoded_Or; - when OpCode_And => - sampledDecodedOpcode<=Decoded_And; - when OpCode_Load => - sampledDecodedOpcode<=Decoded_Load; - when OpCode_Not => - sampledDecodedOpcode<=Decoded_Not; - when OpCode_Flip => - sampledDecodedOpcode<=Decoded_Flip; - when OpCode_Store => - sampledDecodedOpcode<=Decoded_Store; - when OpCode_PopSP => - sampledDecodedOpcode<=Decoded_PopSP; - when others => - sampledDecodedOpcode<=Decoded_Nop; - end case; - end if; - end process; - - - opcodeControl: - process(clk, areset) - variable spOffset : unsigned(4 downto 0); - begin - if areset = '1' then - state <= State_Resync; - break <= '0'; - sp <= unsigned(spStart(maxAddrBit downto minAddrBit)); - pc <= (others => '0'); - idim_flag <= '0'; - begin_inst <= '0'; - memAAddr <= (others => '0'); - memBAddr <= (others => '0'); - memAWriteEnable <= '0'; - memBWriteEnable <= '0'; - out_mem_writeEnable <= '0'; - out_mem_readEnable <= '0'; - memAWrite <= (others => '0'); - memBWrite <= (others => '0'); - -- avoid Latch in synopsys - -- mem_writeMask <= (others => '1'); - elsif (clk'event and clk = '1') then - memAWriteEnable <= '0'; - memBWriteEnable <= '0'; - -- This saves ca. 100 LUT's, by explicitly declaring that the - -- memAWrite can be left at whatever value if memAWriteEnable is - -- not set. - memAWrite <= (others => DontCareValue); - memBWrite <= (others => DontCareValue); --- out_mem_addr <= (others => DontCareValue); --- mem_write <= (others => DontCareValue); - spOffset := (others => DontCareValue); - memAAddr <= (others => DontCareValue); - memBAddr <= (others => DontCareValue); - - out_mem_writeEnable <= '0'; - out_mem_readEnable <= '0'; - begin_inst <= '0'; - out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); - mem_write <= std_logic_vector(memBRead); - - decodedOpcode <= sampledDecodedOpcode; - opcode <= sampledOpcode; - - case state is - when State_Execute => - state <= State_Fetch; - -- at this point: - -- memBRead contains opcode word - -- memARead contains top of stack - pc <= pc + 1; - - -- trace - begin_inst <= '1'; - trace_pc <= (others => '0'); - trace_pc(maxAddrBit downto 0) <= std_logic_vector(pc); - trace_opcode <= opcode; - trace_sp <= (others => '0'); - trace_sp(maxAddrBit downto minAddrBit) <= std_logic_vector(sp); - trace_topOfStack <= std_logic_vector(memARead); - trace_topOfStackB <= std_logic_vector(memBRead); - - -- during the next cycle we'll be reading the next opcode - spOffset(4):=not opcode(4); - spOffset(3 downto 0) := unsigned(opcode(3 downto 0)); - - idim_flag <= '0'; - case decodedOpcode is - when Decoded_Im => - idim_flag <= '1'; - memAWriteEnable <= '1'; - if (idim_flag='0') then - sp <= sp - 1; - memAAddr <= sp-1; - for i in wordSize-1 downto 7 loop - memAWrite(i) <= opcode(6); - end loop; - memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); - else - memAAddr <= sp; - memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0); - memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); - end if; - when Decoded_StoreSP => - memBWriteEnable <= '1'; - memBAddr <= sp+spOffset; - memBWrite <= memARead; - sp <= sp + 1; - state <= State_Resync; - when Decoded_LoadSP => - sp <= sp - 1; - memAAddr <= sp+spOffset; - when Decoded_Emulate => - sp <= sp - 1; - memAWriteEnable <= '1'; - memAAddr <= sp - 1; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto 0) <= pc + 1; - -- The emulate address is: - -- 98 7654 3210 - -- 0000 00aa aaa0 0000 - pc <= (others => '0'); - pc(9 downto 5) <= unsigned(opcode(4 downto 0)); - when Decoded_AddSP => - memAAddr <= sp; - memBAddr <= sp+spOffset; - state <= State_AddSP; - when Decoded_Break => - report "Break instruction encountered" severity failure; - break <= '1'; - when Decoded_PushSP => - memAWriteEnable <= '1'; - memAAddr <= sp - 1; - sp <= sp - 1; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto minAddrBit) <= sp; - when Decoded_PopPC => - pc <= memARead(maxAddrBit downto 0); - sp <= sp + 1; - state <= State_Resync; - when Decoded_Add => - sp <= sp + 1; - state <= State_Add; - when Decoded_Or => - sp <= sp + 1; - state <= State_Or; - when Decoded_And => - sp <= sp + 1; - state <= State_And; - when Decoded_Load => - if (memARead(ioBit)='1') then - out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); - out_mem_readEnable <= '1'; - state <= State_ReadIO; - else - memAAddr <= memARead(maxAddrBit downto minAddrBit); - end if; - when Decoded_Not => - memAAddr <= sp(maxAddrBit downto minAddrBit); - memAWriteEnable <= '1'; - memAWrite <= not memARead; - when Decoded_Flip => - memAAddr <= sp(maxAddrBit downto minAddrBit); - memAWriteEnable <= '1'; - for i in 0 to wordSize-1 loop - memAWrite(i) <= memARead(wordSize-1-i); - end loop; - when Decoded_Store => - memBAddr <= sp + 1; - sp <= sp + 1; - if (memARead(ioBit)='1') then - state <= State_WriteIO; - else - state <= State_Store; - end if; - when Decoded_PopSP => - sp <= memARead(maxAddrBit downto minAddrBit); - state <= State_Resync; - when Decoded_Nop => - memAAddr <= sp; - when others => - null; - end case; - when State_ReadIO => - if (in_mem_busy = '0') then - state <= State_Fetch; - memAWriteEnable <= '1'; - memAWrite <= unsigned(mem_read); - end if; - when State_WriteIO => - sp <= sp + 1; - out_mem_writeEnable <= '1'; - out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); - mem_write <= std_logic_vector(memBRead); - state <= State_WriteIODone; - when State_WriteIODone => - if (in_mem_busy = '0') then - state <= State_Resync; - end if; - when State_Fetch => - -- We need to resync. During the *next* cycle - -- we'll fetch the opcode @ pc and thus it will - -- be available for State_Execute the cycle after - -- next - memBAddr <= pc(maxAddrBit downto minAddrBit); - state <= State_FetchNext; - when State_FetchNext => - -- at this point memARead contains the value that is either - -- from the top of stack or should be copied to the top of the stack - memAWriteEnable <= '1'; - memAWrite <= memARead; - memAAddr <= sp; - memBAddr <= sp + 1; - state <= State_Decode; - when State_Decode => - -- during the State_Execute cycle we'll be fetching SP+1 - memAAddr <= sp; - memBAddr <= sp + 1; - state <= State_Execute; - when State_Store => - sp <= sp + 1; - memAWriteEnable <= '1'; - memAAddr <= memARead(maxAddrBit downto minAddrBit); - memAWrite <= memBRead; - state <= State_Resync; - when State_AddSP => - state <= State_Add; - when State_Add => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead + memBRead; - state <= State_Fetch; - when State_Or => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead or memBRead; - state <= State_Fetch; - when State_Resync => - memAAddr <= sp; - state <= State_Fetch; - when State_And => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead and memBRead; - state <= State_Fetch; - when others => - null; - end case; - - end if; - end process; - - - -end behave; diff --git a/zpu/hdl/zpu4/src/zpu_core_small_wip.vhd b/zpu/hdl/zpu4/src/zpu_core_small_wip.vhd deleted file mode 100644 index 8d87804..0000000 --- a/zpu/hdl/zpu4/src/zpu_core_small_wip.vhd +++ /dev/null @@ -1,497 +0,0 @@ --- Company: ZPU3 --- Engineer: Øyvind Harboe - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use ieee.numeric_std.all; - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - - -entity zpu_core is - Port ( clk : in std_logic; - areset : in std_logic; - enable : in std_logic; - in_mem_busy : in std_logic; - mem_read : in std_logic_vector(wordSize-1 downto 0); - mem_write : out std_logic_vector(wordSize-1 downto 0); - out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); - out_mem_writeEnable : out std_logic; - out_mem_readEnable : out std_logic; - mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); - interrupt : in std_logic; - break : out std_logic); -end zpu_core; - -architecture behave of zpu_core is - -signal readIO : std_logic; - - - -signal memAWriteEnable : std_logic; -signal memAAddr : unsigned(maxAddrBit downto minAddrBit); -signal memAWrite : unsigned(wordSize-1 downto 0); -signal memARead : unsigned(wordSize-1 downto 0); -signal memBWriteEnable : std_logic; -signal memBAddr : unsigned(maxAddrBit downto minAddrBit); -signal memBWrite : unsigned(wordSize-1 downto 0); -signal memBRead : unsigned(wordSize-1 downto 0); - - - -signal pc : unsigned(maxAddrBit downto 0); -signal sp : unsigned(maxAddrBit downto minAddrBit); - -signal idim_flag : std_logic; - ---signal storeToStack : std_logic; ---signal fetchNextInstruction : std_logic; ---signal extraCycle : std_logic; -signal busy : std_logic; ---signal fetching : std_logic; - -signal begin_inst : std_logic; - - - -signal trace_opcode : std_logic_vector(7 downto 0); -signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); -signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); -signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); - --- state machine. -type State_Type is -( -State_Fetch, -State_WriteIODone, -State_Execute, -State_StoreToStack, -State_Add, -State_Or, -State_And, -State_Store, -State_ReadIO, -State_WriteIO, -State_Load, -State_FetchNext, -State_AddSP, -State_ReadIODone, -State_Decode, -State_Resync, -State_Interrupt - -); - -type DecodedOpcodeType is -( -Decoded_Nop, -Decoded_Im, -Decoded_ImShift, -Decoded_LoadSP, -Decoded_StoreSP , -Decoded_AddSP, -Decoded_Emulate, -Decoded_Break, -Decoded_PushSP, -Decoded_PopPC, -Decoded_Add, -Decoded_Or, -Decoded_And, -Decoded_Load, -Decoded_Not, -Decoded_Flip, -Decoded_Store, -Decoded_PopSP -); - - - -signal sampledOpcode : std_logic_vector(OpCode_Size-1 downto 0); -signal opcode : std_logic_vector(OpCode_Size-1 downto 0); - -signal decodedOpcode : DecodedOpcodeType; -signal sampledDecodedOpcode : DecodedOpcodeType; - - -signal state : State_Type; - -subtype AddrBitBRAM_range is natural range maxAddrBitBRAM downto minAddrBit; -signal memAAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); -signal memAWrite_stdlogic : std_logic_vector(memAWrite'range); -signal memARead_stdlogic : std_logic_vector(memARead'range); -signal memBAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); -signal memBWrite_stdlogic : std_logic_vector(memBWrite'range); -signal memBRead_stdlogic : std_logic_vector(memBRead'range); - -subtype index is integer range 0 to 3; - -signal tOpcode_sel : index; - - -signal inInterrupt : std_logic; - - - -begin - traceFileGenerate: - if Generate_Trace generate - trace_file: trace port map ( - clk => clk, - begin_inst => begin_inst, - pc => trace_pc, - opcode => trace_opcode, - sp => trace_sp, - memA => trace_topOfStack, - memB => trace_topOfStackB, - busy => busy, - intsp => (others => 'U') - ); - end generate; - - - - -- not used in this design - - mem_writeMask <= (others => '1'); - - - - memAAddr_stdlogic <= std_logic_vector(memAAddr(AddrBitBRAM_range)); - memAWrite_stdlogic <= std_logic_vector(memAWrite); - memBAddr_stdlogic <= std_logic_vector(memBAddr(AddrBitBRAM_range)); - memBWrite_stdlogic <= std_logic_vector(memBWrite); - memory: dualport_ram port map ( - clk => clk, - memAWriteEnable => memAWriteEnable, - memAAddr => memAAddr_stdlogic, - memAWrite => memAWrite_stdlogic, - memARead => memARead_stdlogic, - memBWriteEnable => memBWriteEnable, - memBAddr => memBAddr_stdlogic, - memBWrite => memBWrite_stdlogic, - memBRead => memBRead_stdlogic - ); - memARead <= unsigned(memARead_stdlogic); - memBRead <= unsigned(memBRead_stdlogic); - - - - tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0)); - - - - decodeControl: - process(memBRead, pc,tOpcode_sel) - variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); - begin - - -- simplify opcode selection a bit so it passes more synthesizers - case (tOpcode_sel) is - - when 0 => tOpcode := std_logic_vector(memBRead(31 downto 24)); - - when 1 => tOpcode := std_logic_vector(memBRead(23 downto 16)); - - when 2 => tOpcode := std_logic_vector(memBRead(15 downto 8)); - - when 3 => tOpcode := std_logic_vector(memBRead(7 downto 0)); - - when others => tOpcode := std_logic_vector(memBRead(7 downto 0)); - end case; - - sampledOpcode <= tOpcode; - - if (tOpcode(7 downto 7)=OpCode_Im) then - sampledDecodedOpcode<=Decoded_Im; - elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then - sampledDecodedOpcode<=Decoded_StoreSP; - elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then - sampledDecodedOpcode<=Decoded_LoadSP; - elsif (tOpcode(7 downto 5)=OpCode_Emulate) then - sampledDecodedOpcode<=Decoded_Emulate; - elsif (tOpcode(7 downto 4)=OpCode_AddSP) then - sampledDecodedOpcode<=Decoded_AddSP; - else - case tOpcode(3 downto 0) is - when OpCode_Break => - sampledDecodedOpcode<=Decoded_Break; - when OpCode_PushSP => - sampledDecodedOpcode<=Decoded_PushSP; - when OpCode_PopPC => - sampledDecodedOpcode<=Decoded_PopPC; - when OpCode_Add => - sampledDecodedOpcode<=Decoded_Add; - when OpCode_Or => - sampledDecodedOpcode<=Decoded_Or; - when OpCode_And => - sampledDecodedOpcode<=Decoded_And; - when OpCode_Load => - sampledDecodedOpcode<=Decoded_Load; - when OpCode_Not => - sampledDecodedOpcode<=Decoded_Not; - when OpCode_Flip => - sampledDecodedOpcode<=Decoded_Flip; - when OpCode_Store => - sampledDecodedOpcode<=Decoded_Store; - when OpCode_PopSP => - sampledDecodedOpcode<=Decoded_PopSP; - when others => - sampledDecodedOpcode<=Decoded_Nop; - end case; - end if; - end process; - - - opcodeControl: - process(clk, areset) - variable spOffset : unsigned(4 downto 0); - begin - if areset = '1' then - state <= State_Resync; - break <= '0'; - sp <= unsigned(spStart(maxAddrBit downto minAddrBit)); - pc <= (others => '0'); - idim_flag <= '0'; - begin_inst <= '0'; - memAAddr <= (others => '0'); - memBAddr <= (others => '0'); - memAWriteEnable <= '0'; - memBWriteEnable <= '0'; - out_mem_writeEnable <= '0'; - out_mem_readEnable <= '0'; - memAWrite <= (others => '0'); - memBWrite <= (others => '0'); - inInterrupt <= '0'; - elsif (clk'event and clk = '1') then - memAWriteEnable <= '0'; - memBWriteEnable <= '0'; - -- This saves ca. 100 LUT's, by explicitly declaring that the - -- memAWrite can be left at whatever value if memAWriteEnable is - -- not set. - memAWrite <= (others => DontCareValue); - memBWrite <= (others => DontCareValue); --- out_mem_addr <= (others => DontCareValue); --- mem_write <= (others => DontCareValue); - spOffset := (others => DontCareValue); - memAAddr <= (others => DontCareValue); - memBAddr <= (others => DontCareValue); - - out_mem_writeEnable <= '0'; - out_mem_readEnable <= '0'; - begin_inst <= '0'; - out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); - mem_write <= std_logic_vector(memBRead); - - decodedOpcode <= sampledDecodedOpcode; - opcode <= sampledOpcode; - if interrupt='0' then - inInterrupt <= '0'; -- no longer in an interrupt - end if; - - case state is - when State_Execute => - state <= State_Fetch; - -- at this point: - -- memBRead contains opcode word - -- memARead contains top of stack - pc <= pc + 1; - - -- trace - begin_inst <= '1'; - trace_pc <= (others => '0'); - trace_pc(maxAddrBit downto 0) <= std_logic_vector(pc); - trace_opcode <= opcode; - trace_sp <= (others => '0'); - trace_sp(maxAddrBit downto minAddrBit) <= std_logic_vector(sp); - trace_topOfStack <= std_logic_vector(memARead); - trace_topOfStackB <= std_logic_vector(memBRead); - - -- during the next cycle we'll be reading the next opcode - spOffset(4):=not opcode(4); - spOffset(3 downto 0) := unsigned(opcode(3 downto 0)); - - idim_flag <= '0'; - case decodedOpcode is - when Decoded_Interrupt => - sp <= sp - 1; - memAAddr <= sp - 1; - memAWriteEnable <= '1'; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBitIncIO downto 0) <= pc; - pc <= conv_std_logic_vector(32, maxAddrBitIncIo+1); -- interrupt address - report "ZPU jumped to interrupt!" severity note; - when Decoded_Im => - idim_flag <= '1'; - memAWriteEnable <= '1'; - if (idim_flag='0') then - sp <= sp - 1; - memAAddr <= sp-1; - for i in wordSize-1 downto 7 loop - memAWrite(i) <= opcode(6); - end loop; - memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); - else - memAAddr <= sp; - memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0); - memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); - end if; - when Decoded_StoreSP => - memBWriteEnable <= '1'; - memBAddr <= sp+spOffset; - memBWrite <= memARead; - sp <= sp + 1; - state <= State_Resync; - when Decoded_LoadSP => - sp <= sp - 1; - memAAddr <= sp+spOffset; - when Decoded_Emulate => - sp <= sp - 1; - memAWriteEnable <= '1'; - memAAddr <= sp - 1; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto 0) <= pc + 1; - -- The emulate address is: - -- 98 7654 3210 - -- 0000 00aa aaa0 0000 - pc <= (others => '0'); - pc(9 downto 5) <= unsigned(opcode(4 downto 0)); - when Decoded_AddSP => - memAAddr <= sp; - memBAddr <= sp+spOffset; - state <= State_AddSP; - when Decoded_Break => - report "Break instruction encountered" severity failure; - break <= '1'; - when Decoded_PushSP => - memAWriteEnable <= '1'; - memAAddr <= sp - 1; - sp <= sp - 1; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto minAddrBit) <= sp; - when Decoded_PopPC => - pc <= memARead(maxAddrBit downto 0); - sp <= sp + 1; - state <= State_Resync; - when Decoded_Add => - sp <= sp + 1; - state <= State_Add; - when Decoded_Or => - sp <= sp + 1; - state <= State_Or; - when Decoded_And => - sp <= sp + 1; - state <= State_And; - when Decoded_Load => - if (memARead(ioBit)='1') then - out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); - out_mem_readEnable <= '1'; - state <= State_ReadIO; - else - memAAddr <= memARead(maxAddrBit downto minAddrBit); - end if; - when Decoded_Not => - memAAddr <= sp(maxAddrBit downto minAddrBit); - memAWriteEnable <= '1'; - memAWrite <= not memARead; - when Decoded_Flip => - memAAddr <= sp(maxAddrBit downto minAddrBit); - memAWriteEnable <= '1'; - for i in 0 to wordSize-1 loop - memAWrite(i) <= memARead(wordSize-1-i); - end loop; - when Decoded_Store => - memBAddr <= sp + 1; - sp <= sp + 1; - if (memARead(ioBit)='1') then - state <= State_WriteIO; - else - state <= State_Store; - end if; - when Decoded_PopSP => - sp <= memARead(maxAddrBit downto minAddrBit); - state <= State_Resync; - when Decoded_Nop => - memAAddr <= sp; - when others => - null; - end case; - when State_ReadIO => - if (in_mem_busy = '0') then - state <= State_Fetch; - memAWriteEnable <= '1'; - memAWrite <= unsigned(mem_read); - end if; - when State_WriteIO => - sp <= sp + 1; - out_mem_writeEnable <= '1'; - out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); - mem_write <= std_logic_vector(memBRead); - state <= State_WriteIODone; - when State_WriteIODone => - if (in_mem_busy = '0') then - state <= State_Resync; - end if; - when State_Fetch => - -- We need to resync. During the *next* cycle - -- we'll fetch the opcode @ pc and thus it will - -- be available for State_Execute the cycle after - -- next - memBAddr <= pc(maxAddrBit downto minAddrBit); - state <= State_FetchNext; - when State_FetchNext => - -- at this point memARead contains the value that is either - -- from the top of stack or should be copied to the top of the stack - memAWriteEnable <= '1'; - memAWrite <= memARead; - memAAddr <= sp; - memBAddr <= sp + 1; - state <= State_Decode; - when State_Decode => - if interrupt='1' and inInterrupt='0' and idim_flag='0' then - -- We got an interrupt, execute interrupt instead of next instruction - decodedOpcode <= Decoded_Interrupt; - end if; - -- during the State_Execute cycle we'll be fetching SP+1 - memAAddr <= sp; - memBAddr <= sp + 1; - state <= State_Execute; - when State_Store => - sp <= sp + 1; - memAWriteEnable <= '1'; - memAAddr <= memARead(maxAddrBit downto minAddrBit); - memAWrite <= memBRead; - state <= State_Resync; - when State_AddSP => - state <= State_Add; - when State_Add => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead + memBRead; - state <= State_Fetch; - when State_Or => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead or memBRead; - state <= State_Fetch; - when State_Resync => - memAAddr <= sp; - state <= State_Fetch; - when State_And => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead and memBRead; - state <= State_Fetch; - when others => - null; - end case; - - end if; - end process; - - - -end behave; diff --git a/zpu/hdl/zpu4/src/zpupkg.vhd b/zpu/hdl/zpu4/src/zpupkg.vhd deleted file mode 100644 index f3800b0..0000000 --- a/zpu/hdl/zpu4/src/zpupkg.vhd +++ /dev/null @@ -1,170 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use ieee.numeric_std.all; - -library work; -use work.zpu_config.all; - -package zpupkg is - - -- This bit is set for read/writes to IO - -- FIX!!! eventually this should be set to wordSize-1 so as to - -- to make the address of IO independent of amount of memory - -- reserved for CPU. Requires trivial tweaks in toolchain/runtime - -- libraries. - - constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes - constant maxAddrBit : integer := maxAddrBitIncIO-1; - constant ioBit : integer := maxAddrBit+1; - constant wordSize : integer := 2**wordPower; - constant wordBytes : integer := wordSize/8; - constant minAddrBit : integer := byteBits; - -- configurable internal stack size. Probably going to be 16 after toolchain is done - constant stack_bits : integer := 5; - constant stack_size : integer := 2**stack_bits; - - - component dualport_ram is - port (clk : in std_logic; - memAWriteEnable : in std_logic; - memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); - memAWrite : in std_logic_vector(wordSize-1 downto 0); - memARead : out std_logic_vector(wordSize-1 downto 0); - memBWriteEnable : in std_logic; - memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); - memBWrite : in std_logic_vector(wordSize-1 downto 0); - memBRead : out std_logic_vector(wordSize-1 downto 0)); - end component; - - - component dram is - port (clk : in std_logic; - areset : in std_logic; - mem_writeEnable : in std_logic; - mem_readEnable : in std_logic; - mem_addr : in std_logic_vector(maxAddrBit downto 0); - mem_write : in std_logic_vector(wordSize-1 downto 0); - mem_read : out std_logic_vector(wordSize-1 downto 0); - mem_busy : out std_logic; - mem_writeMask : in std_logic_vector(wordBytes-1 downto 0)); - end component; - - - component trace is - port( - clk : in std_logic; - begin_inst : in std_logic; - pc : in std_logic_vector(maxAddrBitIncIO downto 0); - opcode : in std_logic_vector(7 downto 0); - sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit); - memA : in std_logic_vector(wordSize-1 downto 0); - memB : in std_logic_vector(wordSize-1 downto 0); - busy : in std_logic; - intSp : in std_logic_vector(stack_bits-1 downto 0) - ); - end component; - - component zpu_core is - port ( clk : in std_logic; - areset : in std_logic; - enable : in std_logic; - in_mem_busy : in std_logic; - mem_read : in std_logic_vector(wordSize-1 downto 0); - mem_write : out std_logic_vector(wordSize-1 downto 0); - out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); - out_mem_writeEnable : out std_logic; - out_mem_readEnable : out std_logic; - mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); - interrupt : in std_logic; - break : out std_logic); - end component; - - - - component timer is - port( - clk : in std_logic; - areset : in std_logic; - we : in std_logic; - din : in std_logic_vector(7 downto 0); - adr : in std_logic_vector(2 downto 0); - dout : out std_logic_vector(7 downto 0)); - end component; - - component zpuio is - port ( areset : in std_logic; - cpu_clk : in std_logic; - clk_status : in std_logic_vector(2 downto 0); - cpu_din : in std_logic_vector(15 downto 0); - cpu_a : in std_logic_vector(20 downto 0); - cpu_we : in std_logic_vector(1 downto 0); - cpu_re : in std_logic; - cpu_dout : inout std_logic_vector(15 downto 0)); - end component; - - - - - -- opcode decode constants - constant OpCode_Im : std_logic_vector(7 downto 7) := "1"; - constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010"; - constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011"; - constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001"; - constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001"; - constant OpCode_Short : std_logic_vector(7 downto 4) := "0000"; - - constant OpCode_Break : std_logic_vector(3 downto 0) := "0000"; - constant OpCode_Shiftleft: std_logic_vector(3 downto 0) := "0001"; - constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010"; - constant OpCode_PushInt : std_logic_vector(3 downto 0) := "0011"; - - constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100"; - constant OpCode_Add : std_logic_vector(3 downto 0) := "0101"; - constant OpCode_And : std_logic_vector(3 downto 0) := "0110"; - constant OpCode_Or : std_logic_vector(3 downto 0) := "0111"; - - constant OpCode_Load : std_logic_vector(3 downto 0) := "1000"; - constant OpCode_Not : std_logic_vector(3 downto 0) := "1001"; - constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010"; - constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011"; - - constant OpCode_Store : std_logic_vector(3 downto 0) := "1100"; - constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101"; - constant OpCode_Compare : std_logic_vector(3 downto 0) := "1110"; - constant OpCode_PopInt : std_logic_vector(3 downto 0) := "1111"; - - constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6)); - constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6)); - constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6)); - constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6)); - - constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6)); - constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6)); - - constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6)); - constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6)); - constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6)); - constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6)); - - constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6)); - constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6)); - - constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6)); - constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6)); - constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6)); - - constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6)); - constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6)); - constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6)); - - constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6)); - constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6)); - constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6)); - - - - constant OpCode_Size : integer := 8; - - - -end zpupkg; -- cgit v1.1 From c82fe03eaaf5216776c55dd43e01191cd558eb92 Mon Sep 17 00:00:00 2001 From: oharboe Date: Mon, 5 May 2008 08:07:29 +0000 Subject: added a bit about interrupts --- zpu/docs/zpu_arch.html | 37 +++++++++++++++++++++++++++++++++++-- 1 file changed, 35 insertions(+), 2 deletions(-) diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index a1f61a1..8582afb 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -1,5 +1,14 @@ +

      Index

      + +

      Introduction

      The ZPU is a zero operand, or stack based CPU. The opcodes have a fixed width of 8 bits.

      @@ -47,6 +56,7 @@ foo: +

      Instruction set

      Only the base instructions are implemented in the architecture. More advanced instructions, like ASHIFTLEFT are emulated in the illegal instruction vector. @@ -364,6 +374,7 @@ end if +

      Vectors

      @@ -392,6 +403,7 @@ end if
      AddressNameDescription
      +

      Phi memory map

      The ZPU architecture does not define a memory map as such, but the GCC + libgloss + ecos hal library uses the memory map below. @@ -767,7 +779,28 @@ memory map below. - - +       +

      Interrupts

      +The ZPU supports interrupts. +

      +To trigger an interrupt, the interrupt signal must be asserted. The ZPU does +not define any interrupt disabling mechanism, this must be implemented by the +interrupt controller and controlled via memory mapped IO. +

      +Interrupts are masked when the IDIM flag is set, i.e. +with consequtive IM instructions. +

      +The ZPU has an edge triggered interrupt. As the ZPU notices that the interrupt +is asserted, it will execute the interrupt instruction. The interrupt signal +must stay asserted until the ZPU acknowledges it. +

      +When the interrupt instruction is executed, the PC will be pushed onto the +stack and the PC will be set to the interrupt vector address (0x20). +

      +Note that the GCC compiler requires three registers r0,r1,r2,r3 for some +rather uncommon operations. These 32 registers are mapped to memory locations 0x0, +0x4, 0x8, 0xc. The default interrupt vector at address 0x20 will load the +value of these memory locations onto the stack, call _zpu_interrupt and +restore them. \ No newline at end of file -- cgit v1.1 From ef1ebefa6075994c4f0a76035b585def8c5c1d3a Mon Sep 17 00:00:00 2001 From: oharboe Date: Mon, 5 May 2008 11:40:45 +0000 Subject: wip --- zpu/hdl/zpu4/core/zpu_core_small_wip.vhd | 1 + 1 file changed, 1 insertion(+) diff --git a/zpu/hdl/zpu4/core/zpu_core_small_wip.vhd b/zpu/hdl/zpu4/core/zpu_core_small_wip.vhd index 8d87804..a169103 100644 --- a/zpu/hdl/zpu4/core/zpu_core_small_wip.vhd +++ b/zpu/hdl/zpu4/core/zpu_core_small_wip.vhd @@ -453,6 +453,7 @@ begin when State_Decode => if interrupt='1' and inInterrupt='0' and idim_flag='0' then -- We got an interrupt, execute interrupt instead of next instruction + inInterrupt <= '1'; decodedOpcode <= Decoded_Interrupt; end if; -- during the State_Execute cycle we'll be fetching SP+1 -- cgit v1.1 From 68e306c13274f504281a94a52b5fb2f8ed4d9a75 Mon Sep 17 00:00:00 2001 From: oharboe Date: Mon, 5 May 2008 11:56:28 +0000 Subject: wip --- zpu/hdl/zpu4/test/interrupt/int.bin | Bin 0 -> 12232 bytes zpu/hdl/zpu4/test/interrupt/int.elf | Bin 0 -> 150454 bytes zpu/hdl/zpu4/test/interrupt/int.ram | 3057 +++++++++++++++++++++++++++++++++++ 3 files changed, 3057 insertions(+) create mode 100644 zpu/hdl/zpu4/test/interrupt/int.bin create mode 100644 zpu/hdl/zpu4/test/interrupt/int.elf create mode 100644 zpu/hdl/zpu4/test/interrupt/int.ram diff --git a/zpu/hdl/zpu4/test/interrupt/int.bin b/zpu/hdl/zpu4/test/interrupt/int.bin new file mode 100644 index 0000000..94cbe31 Binary files /dev/null and b/zpu/hdl/zpu4/test/interrupt/int.bin differ diff --git a/zpu/hdl/zpu4/test/interrupt/int.elf b/zpu/hdl/zpu4/test/interrupt/int.elf new file mode 100644 index 0000000..a550987 Binary files /dev/null and b/zpu/hdl/zpu4/test/interrupt/int.elf differ diff --git a/zpu/hdl/zpu4/test/interrupt/int.ram b/zpu/hdl/zpu4/test/interrupt/int.ram new file mode 100644 index 0000000..bcb424a --- /dev/null +++ b/zpu/hdl/zpu4/test/interrupt/int.ram @@ -0,0 +1,3057 @@ +0 => x"0b0b0b0b", +1 => x"82700b0b", +2 => x"80cfe00c", +3 => x"3a0b0b80", +4 => x"c6e10400", +5 => x"00000000", +6 => x"00000000", +7 => x"00000000", +8 => x"80088408", +9 => x"88080b0b", +10 => x"0b8af02d", +11 => x"880c840c", +12 => x"800c0400", +13 => x"00000000", +14 => x"00000000", +15 => x"00000000", +16 => x"71fd0608", +17 => x"72830609", +18 => x"81058205", +19 => x"832b2a83", +20 => x"ffff0652", +21 => x"04000000", +22 => x"00000000", +23 => x"00000000", +24 => x"71fd0608", +25 => x"83ffff73", +26 => x"83060981", +27 => x"05820583", +28 => x"2b2b0906", +29 => x"7383ffff", +30 => x"0b0b0b0b", +31 => x"83a70400", +32 => x"72098105", +33 => x"72057373", +34 => x"09060906", +35 => x"73097306", +36 => x"070a8106", +37 => x"53510400", +38 => x"00000000", +39 => x"00000000", +40 => x"72722473", +41 => x"732e0753", +42 => x"51040000", +43 => x"00000000", +44 => x"00000000", +45 => x"00000000", +46 => x"00000000", +47 => x"00000000", +48 => x"71737109", +49 => x"71068106", +50 => x"30720a10", +51 => x"0a720a10", +52 => x"0a31050a", +53 => x"81065151", +54 => x"53510400", +55 => x"00000000", +56 => x"72722673", +57 => x"732e0753", +58 => x"51040000", +59 => x"00000000", +60 => x"00000000", +61 => x"00000000", +62 => x"00000000", +63 => x"00000000", +64 => x"00000000", +65 => x"00000000", +66 => x"00000000", +67 => x"00000000", +68 => x"00000000", +69 => x"00000000", +70 => x"00000000", +71 => x"00000000", +72 => x"0b0b0b88", +73 => x"c4040000", +74 => x"00000000", +75 => x"00000000", +76 => x"00000000", +77 => x"00000000", +78 => x"00000000", +79 => x"00000000", +80 => x"720a722b", +81 => x"0a535104", +82 => x"00000000", +83 => x"00000000", +84 => x"00000000", +85 => x"00000000", +86 => x"00000000", +87 => x"00000000", +88 => x"72729f06", +89 => x"0981050b", +90 => x"0b0b88a7", +91 => x"05040000", +92 => x"00000000", +93 => x"00000000", +94 => x"00000000", +95 => x"00000000", +96 => x"72722aff", +97 => x"739f062a", +98 => x"0974090a", +99 => x"8106ff05", +100 => x"06075351", +101 => x"04000000", +102 => x"00000000", +103 => x"00000000", +104 => x"71715351", +105 => x"020d0406", +106 => x"73830609", +107 => x"81058205", +108 => x"832b0b2b", +109 => x"0772fc06", +110 => x"0c515104", +111 => x"00000000", +112 => x"72098105", +113 => x"72050970", +114 => x"81050906", +115 => x"0a810653", +116 => x"51040000", +117 => x"00000000", +118 => x"00000000", +119 => x"00000000", +120 => x"72098105", +121 => x"72050970", +122 => x"81050906", +123 => x"0a098106", +124 => x"53510400", +125 => x"00000000", +126 => x"00000000", +127 => x"00000000", +128 => x"71098105", +129 => x"52040000", +130 => x"00000000", +131 => x"00000000", +132 => x"00000000", +133 => x"00000000", +134 => x"00000000", +135 => x"00000000", +136 => x"72720981", +137 => x"05055351", +138 => x"04000000", +139 => x"00000000", +140 => x"00000000", +141 => x"00000000", +142 => x"00000000", +143 => x"00000000", +144 => x"72097206", +145 => x"73730906", +146 => x"07535104", +147 => x"00000000", +148 => x"00000000", +149 => x"00000000", +150 => x"00000000", +151 => x"00000000", +152 => x"71fc0608", +153 => x"72830609", +154 => x"81058305", +155 => x"1010102a", +156 => x"81ff0652", +157 => x"04000000", +158 => x"00000000", +159 => x"00000000", +160 => x"71fc0608", +161 => x"0b0b80cf", +162 => x"cc738306", +163 => x"10100508", +164 => x"060b0b0b", +165 => x"88aa0400", +166 => x"00000000", +167 => x"00000000", +168 => x"80088408", +169 => x"88087575", +170 => x"0b0b0b8b", +171 => x"ac2d5050", +172 => x"80085688", +173 => x"0c840c80", +174 => x"0c510400", +175 => x"00000000", +176 => x"80088408", +177 => x"88087575", +178 => x"0b0b0b8b", +179 => x"f02d5050", +180 => x"80085688", +181 => x"0c840c80", +182 => x"0c510400", +183 => x"00000000", +184 => x"72097081", +185 => x"0509060a", +186 => x"8106ff05", +187 => x"70547106", +188 => x"73097274", +189 => x"05ff0506", +190 => x"07515151", +191 => x"04000000", +192 => x"72097081", +193 => x"0509060a", +194 => x"098106ff", +195 => x"05705471", +196 => x"06730972", +197 => x"7405ff05", +198 => x"06075151", +199 => x"51040000", +200 => x"05ff0504", +201 => x"00000000", +202 => x"00000000", +203 => x"00000000", +204 => x"00000000", +205 => x"00000000", +206 => x"00000000", +207 => x"00000000", +208 => x"810b0b0b", +209 => x"80cfdc0c", +210 => x"51040000", +211 => x"00000000", +212 => x"00000000", +213 => x"00000000", +214 => x"00000000", +215 => x"00000000", +216 => x"71810552", +217 => x"04000000", +218 => x"00000000", +219 => x"00000000", +220 => x"00000000", +221 => x"00000000", +222 => x"00000000", +223 => x"00000000", +224 => x"00000000", +225 => x"00000000", +226 => x"00000000", +227 => x"00000000", +228 => x"00000000", +229 => x"00000000", +230 => x"00000000", +231 => x"00000000", +232 => x"02840572", +233 => x"10100552", +234 => x"04000000", +235 => x"00000000", +236 => x"00000000", +237 => x"00000000", +238 => x"00000000", +239 => x"00000000", +240 => x"00000000", +241 => x"00000000", +242 => x"00000000", +243 => x"00000000", +244 => x"00000000", +245 => x"00000000", +246 => x"00000000", +247 => x"00000000", +248 => x"717105ff", +249 => x"05715351", +250 => x"020d0400", +251 => x"00000000", +252 => x"00000000", +253 => x"00000000", +254 => x"00000000", +255 => x"00000000", +256 => x"82c53f80", +257 => x"c6e73f04", +258 => x"10101010", +259 => x"10101010", +260 => x"10101010", +261 => x"10101010", +262 => x"10101010", +263 => x"10101010", +264 => x"10101010", +265 => x"10101053", +266 => x"51047381", +267 => x"ff067383", +268 => x"06098105", +269 => x"83051010", +270 => x"102b0772", +271 => x"fc060c51", +272 => x"51043c04", +273 => x"72728072", +274 => x"8106ff05", +275 => x"09720605", +276 => x"71105272", +277 => x"0a100a53", +278 => x"72ed3851", +279 => x"51535104", +280 => x"fe3d0d0b", +281 => x"0b80dfc8", +282 => x"08538413", +283 => x"0870882a", +284 => x"70810651", +285 => x"52527080", +286 => x"2ef03871", +287 => x"81ff0680", +288 => x"0c843d0d", +289 => x"04ff3d0d", +290 => x"0b0b80df", +291 => x"c8085271", +292 => x"0870882a", +293 => x"81327081", +294 => x"06515151", +295 => x"70f13873", +296 => x"720c833d", +297 => x"0d0480cf", +298 => x"dc08802e", +299 => x"a43880cf", +300 => x"e008822e", +301 => x"bd388380", +302 => x"800b0b0b", +303 => x"80dfc80c", +304 => x"82a0800b", +305 => x"80dfcc0c", +306 => x"8290800b", +307 => x"80dfd00c", +308 => x"04f88080", +309 => x"80a40b0b", +310 => x"0b80dfc8", +311 => x"0cf88080", +312 => x"82800b80", +313 => x"dfcc0cf8", +314 => x"80808480", +315 => x"0b80dfd0", +316 => x"0c0480c0", +317 => x"a8808c0b", +318 => x"0b0b80df", +319 => x"c80c80c0", +320 => x"a880940b", +321 => x"80dfcc0c", +322 => x"0b0b80cf", +323 => x"980b80df", +324 => x"d00c0470", +325 => x"7080dfd4", +326 => x"335170a7", +327 => x"3880cfe8", +328 => x"08700852", +329 => x"5270802e", +330 => x"94388412", +331 => x"80cfe80c", +332 => x"702d80cf", +333 => x"e8087008", +334 => x"525270ee", +335 => x"38810b80", +336 => x"dfd43450", +337 => x"50040470", +338 => x"0b0b80df", +339 => x"c408802e", +340 => x"8e380b0b", +341 => x"0b0b800b", +342 => x"802e0981", +343 => x"06833850", +344 => x"040b0b80", +345 => x"dfc4510b", +346 => x"0b0bf594", +347 => x"3f500404", +348 => x"80dfe008", +349 => x"810580df", +350 => x"e00c04fe", +351 => x"3d0d80df", +352 => x"e0087054", +353 => x"5272722e", +354 => x"953880cf", +355 => x"9c5182bb", +356 => x"3f80dfe0", +357 => x"08527272", +358 => x"2e098106", +359 => x"ed3880cf", +360 => x"ac5182a7", +361 => x"3f80dfe0", +362 => x"0852eb39", +363 => x"fb3d0d77", +364 => x"79555580", +365 => x"56757524", +366 => x"ab388074", +367 => x"249d3880", +368 => x"53735274", +369 => x"5180e13f", +370 => x"80085475", +371 => x"802e8538", +372 => x"80083054", +373 => x"73800c87", +374 => x"3d0d0473", +375 => x"30768132", +376 => x"5754dc39", +377 => x"74305581", +378 => x"56738025", +379 => x"d238ec39", +380 => x"fa3d0d78", +381 => x"7a575580", +382 => x"57767524", +383 => x"a438759f", +384 => x"2c548153", +385 => x"75743274", +386 => x"31527451", +387 => x"9b3f8008", +388 => x"5476802e", +389 => x"85388008", +390 => x"30547380", +391 => x"0c883d0d", +392 => x"04743055", +393 => x"8157d739", +394 => x"fc3d0d76", +395 => x"78535481", +396 => x"53807473", +397 => x"26525572", +398 => x"802e9838", +399 => x"70802eab", +400 => x"38807224", +401 => x"a6387110", +402 => x"73107572", +403 => x"26535452", +404 => x"72ea3873", +405 => x"51788338", +406 => x"74517080", +407 => x"0c863d0d", +408 => x"04720a10", +409 => x"0a720a10", +410 => x"0a535372", +411 => x"802ee438", +412 => x"717426ed", +413 => x"38737231", +414 => x"75740774", +415 => x"0a100a74", +416 => x"0a100a55", +417 => x"555654e3", +418 => x"39f73d0d", +419 => x"7c705253", +420 => x"80fd3f72", +421 => x"54800855", +422 => x"0b0b80cf", +423 => x"b8568157", +424 => x"80088105", +425 => x"5a8b3de4", +426 => x"11595382", +427 => x"59f41352", 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x"00002f30", +3024 => x"00002f38", +3025 => x"00002f38", +3026 => x"00002f40", +3027 => x"00002f40", +3028 => x"00002f48", +3029 => x"00002f48", +3030 => x"00002f50", +3031 => x"00002f50", +3032 => x"00002f58", +3033 => x"00002f58", +3034 => x"00002f60", +3035 => x"00002f60", +3036 => x"00002f68", +3037 => x"00002f68", +3038 => x"00002f70", +3039 => x"00002f70", +3040 => x"00002f78", +3041 => x"00002f78", +3042 => x"00002f80", +3043 => x"00002f80", +3044 => x"00002f88", +3045 => x"00002f88", +3046 => x"00002f90", +3047 => x"00002f90", +3048 => x"00002f98", +3049 => x"00002f98", +3050 => x"00002fa0", +3051 => x"00002fa0", +3052 => x"000027c0", +3053 => x"ffffffff", +3054 => x"00000000", +3055 => x"ffffffff", +3056 => x"00000000", -- cgit v1.1 From 28011391a8f5ed1cfd5b289ab3a016e4da69f772 Mon Sep 17 00:00:00 2001 From: oharboe Date: Mon, 5 May 2008 18:31:21 +0000 Subject: * added eCos HAL for ZPU zpu/zpu/sw/ecos/repository --- zpu/ChangeLog | 3 + .../current/cdl/phi_opencores_ethmac_drivers.cdl | 127 +++++++ .../current/include/devs_eth_zpu_opencores_phi.inl | 92 ++++++ .../zpu/opencores/phi/current/src/if_opencores.c | 112 +++++++ .../repository/hal/zylin/arch/current/ChangeLog | 39 +++ .../hal/zylin/arch/current/cdl/hal_zylin.cdl | 108 ++++++ .../hal/zylin/arch/current/include/arch.inc | 79 +++++ .../hal/zylin/arch/current/include/basetype.h | 83 +++++ .../hal/zylin/arch/current/include/hal_arch.h | 255 ++++++++++++++ .../hal/zylin/arch/current/include/hal_intr.h | 261 +++++++++++++++ .../hal/zylin/arch/current/include/hal_io.h | 305 +++++++++++++++++ .../hal/zylin/arch/current/src/context.S | 324 ++++++++++++++++++ .../hal/zylin/arch/current/src/hal_misc.c | 177 ++++++++++ .../hal/zylin/arch/current/src/hal_mk_defs.c | 102 ++++++ .../hal/zylin/arch/current/src/vectors.c | 116 +++++++ .../repository/hal/zylin/arch/current/src/zylin.ld | 226 +++++++++++++ .../hal/zylin/zpu/abel/current/ChangeLog | 39 +++ .../zpu/abel/current/cdl/hal_zylin_zpu_abel.cdl | 298 +++++++++++++++++ .../zpu/abel/current/include/hal_platform_ints.h | 79 +++++ .../include/pkgconf/mlt_zylin_zpu_abel_ram.h | 17 + .../include/pkgconf/mlt_zylin_zpu_abel_ram.ldi | 27 ++ .../hal/zylin/zpu/abel/current/include/plf_io.h | 64 ++++ .../zylin/zpu/abel/current/misc/redboot_RAM.ecm | 53 +++ .../hal/zylin/zpu/abel/current/src/abel_misc.c | 61 ++++ .../repository/hal/zylin/zpu/phi/current/ChangeLog | 39 +++ .../zpu/phi/current/cdl/hal_zylin_zpu_phi.cdl | 292 ++++++++++++++++ .../zpu/phi/current/include/hal_platform_ints.h | 81 +++++ .../include/pkgconf/mlt_zylin_zpu_phi_ram.h | 17 + .../include/pkgconf/mlt_zylin_zpu_phi_ram.ldi | 27 ++ .../hal/zylin/zpu/phi/current/include/plf_io.h | 58 ++++ .../hal/zylin/zpu/phi/current/src/phi_misc.c | 72 ++++ .../repository/hal/zylin/zpu/var/current/ChangeLog | 38 +++ .../zylin/zpu/var/current/cdl/hal_zylin_zpu.cdl | 83 +++++ .../hal/zylin/zpu/var/current/include/hal_cache.h | 192 +++++++++++ .../hal/zylin/zpu/var/current/include/hal_diag.h | 90 +++++ .../hal/zylin/zpu/var/current/include/plf_stub.h | 85 +++++ .../hal/zylin/zpu/var/current/include/var_arch.h | 73 ++++ .../hal/zylin/zpu/var/current/include/var_io.h | 73 ++++ .../hal/zylin/zpu/var/current/src/hal_diag.c | 88 +++++ .../hal/zylin/zpu/var/current/src/zpu_misc.c | 252 ++++++++++++++ .../hal/zylin/zpu/zeta/current/ChangeLog | 39 +++ .../zpu/zeta/current/cdl/hal_zylin_zpu_zeta.cdl | 298 +++++++++++++++++ .../zpu/zeta/current/include/hal_platform_ints.h | 79 +++++ .../include/pkgconf/mlt_zylin_zpu_zeta_ram.h | 17 + .../include/pkgconf/mlt_zylin_zpu_zeta_ram.ldi | 27 ++ .../hal/zylin/zpu/zeta/current/include/plf_io.h | 58 ++++ .../zylin/zpu/zeta/current/misc/redboot_RAM.ecm | 53 +++ .../hal/zylin/zpu/zeta/current/src/zeta_misc.c | 64 ++++ .../repository/net/zylin/current/cdl/phi_net.cdl | 56 ++++ .../net/zylin/current/src/phi_network_support.c | 368 +++++++++++++++++++++ zpu/sw/ecos/repository/pkgconf/rules.mak | 210 ++++++++++++ 51 files changed, 5876 insertions(+) create mode 100644 zpu/sw/ecos/repository/dev/eth/zpu/opencores/phi/current/cdl/phi_opencores_ethmac_drivers.cdl create mode 100644 zpu/sw/ecos/repository/dev/eth/zpu/opencores/phi/current/include/devs_eth_zpu_opencores_phi.inl create mode 100644 zpu/sw/ecos/repository/dev/eth/zpu/opencores/phi/current/src/if_opencores.c create mode 100644 zpu/sw/ecos/repository/hal/zylin/arch/current/ChangeLog create mode 100644 zpu/sw/ecos/repository/hal/zylin/arch/current/cdl/hal_zylin.cdl create mode 100644 zpu/sw/ecos/repository/hal/zylin/arch/current/include/arch.inc create mode 100644 zpu/sw/ecos/repository/hal/zylin/arch/current/include/basetype.h create mode 100644 zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_arch.h create mode 100644 zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_intr.h create mode 100644 zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_io.h create mode 100644 zpu/sw/ecos/repository/hal/zylin/arch/current/src/context.S create mode 100644 zpu/sw/ecos/repository/hal/zylin/arch/current/src/hal_misc.c create mode 100644 zpu/sw/ecos/repository/hal/zylin/arch/current/src/hal_mk_defs.c create mode 100644 zpu/sw/ecos/repository/hal/zylin/arch/current/src/vectors.c create mode 100644 zpu/sw/ecos/repository/hal/zylin/arch/current/src/zylin.ld create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/ChangeLog create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/cdl/hal_zylin_zpu_abel.cdl create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/hal_platform_ints.h create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/pkgconf/mlt_zylin_zpu_abel_ram.h create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/pkgconf/mlt_zylin_zpu_abel_ram.ldi create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/plf_io.h create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/misc/redboot_RAM.ecm create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/src/abel_misc.c create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/ChangeLog create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/cdl/hal_zylin_zpu_phi.cdl create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/hal_platform_ints.h create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/pkgconf/mlt_zylin_zpu_phi_ram.h create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/pkgconf/mlt_zylin_zpu_phi_ram.ldi create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/plf_io.h create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/src/phi_misc.c create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/var/current/ChangeLog create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/var/current/cdl/hal_zylin_zpu.cdl create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/hal_cache.h create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/hal_diag.h create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/plf_stub.h create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/var_arch.h create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/var_io.h create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/var/current/src/hal_diag.c create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/var/current/src/zpu_misc.c create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/ChangeLog create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/cdl/hal_zylin_zpu_zeta.cdl create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/hal_platform_ints.h create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/pkgconf/mlt_zylin_zpu_zeta_ram.h create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/pkgconf/mlt_zylin_zpu_zeta_ram.ldi create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/plf_io.h create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/misc/redboot_RAM.ecm create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/src/zeta_misc.c create mode 100644 zpu/sw/ecos/repository/net/zylin/current/cdl/phi_net.cdl create mode 100644 zpu/sw/ecos/repository/net/zylin/current/src/phi_network_support.c create mode 100644 zpu/sw/ecos/repository/pkgconf/rules.mak diff --git a/zpu/ChangeLog b/zpu/ChangeLog index 3100fdb..8384d0d 100644 --- a/zpu/ChangeLog +++ b/zpu/ChangeLog @@ -1,3 +1,6 @@ +2008-05-05 Øyvind Harboe + * added eCos HAL for ZPU + zpu/zpu/sw/ecos/repository 2008-05-04 Øyvind Harboe * moved ZPU core files to seperate folder * deleted some obsolete files diff --git a/zpu/sw/ecos/repository/dev/eth/zpu/opencores/phi/current/cdl/phi_opencores_ethmac_drivers.cdl b/zpu/sw/ecos/repository/dev/eth/zpu/opencores/phi/current/cdl/phi_opencores_ethmac_drivers.cdl new file mode 100644 index 0000000..580890d --- /dev/null +++ b/zpu/sw/ecos/repository/dev/eth/zpu/opencores/phi/current/cdl/phi_opencores_ethmac_drivers.cdl @@ -0,0 +1,127 @@ +# ==================================================================== +# +# phi_opencores_ethmac_drivers.cdl +# +# Ethernet drivers - support for Opencores ethermac controller +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): Gaisler Research, (Konrad Eisele) +# Contributors: Zylin AS, (Edgar Grimberg) +# Date: 2005-01-20 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI { + + display "PHI opencores ethernet driver" + + parent CYGPKG_IO_ETH_DRIVERS + active_if CYGPKG_IO_ETH_DRIVERS + active_if CYGPKG_HAL_ZYLIN_ZPU_PHI + + requires CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC + description "Ethernet driver for ethermac in on a Zylin Phi Board." + + include_dir cyg/io + compile -library=libextras.a if_opencores.c + + define_proc { + puts $::cdl_system_header "/***** ethernet driver proc output start *****/" + puts $::cdl_system_header "#define CYGDAT_DEVS_ETH_OPENCORES_ETHERMAC_INL " + puts $::cdl_system_header "#define CYGDAT_DEVS_ETH_OPENCORES_ETHERMAC_CFG " + puts $::cdl_system_header "/***** ethernet driver proc output end *****/" + } + + # Arguably this should do in the generic package + # but then there is a logic loop so you can never enable it. + + cdl_interface CYGINT_DEVS_ETH_OPENCORES_ETHERMAC_REQUIRED { + display "opencores ethermac driver required" + } + + cdl_component CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI_ETH0 { + display "Ethernet port 0 driver" + flavor bool + default_value 1 + + implements CYGHWR_NET_DRIVERS + implements CYGHWR_NET_DRIVER_ETH0 + implements CYGINT_DEVS_ETH_OPENCORES_ETHERMAC_REQUIRED + + cdl_option CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI_ETH0_NAME { + display "Device name for the ethernet driver" + flavor data + default_value {"\"eth0\""} + description " + This option sets the name of the ethernet device for the + ethernet port." + } + + cdl_option CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI_ETH0_ESA { + display "The ethernet station address (MAC)" + flavor data + default_value {"{0x00, 0x00, 0x5E, 0x21, 0x00, 0x01}"} + description "A static ethernet station address. + Caution: Booting two systems with the same MAC on the same + network, will cause severe conflicts." + } + } + + cdl_component CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI_OPTIONS { + display "Opencores ethermac driver build options" + flavor none + no_define + + cdl_option CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "-D_KERNEL -D__ECOS" } + description " + This option modifies the set of compiler flags for + building the opencores ethermac driver package. + These flags are used in addition + to the set of global flags." + } + } + +} + +# EOF phi_opencores_ethmac_drivers.cdl diff --git a/zpu/sw/ecos/repository/dev/eth/zpu/opencores/phi/current/include/devs_eth_zpu_opencores_phi.inl b/zpu/sw/ecos/repository/dev/eth/zpu/opencores/phi/current/include/devs_eth_zpu_opencores_phi.inl new file mode 100644 index 0000000..7cfa114 --- /dev/null +++ b/zpu/sw/ecos/repository/dev/eth/zpu/opencores/phi/current/include/devs_eth_zpu_opencores_phi.inl @@ -0,0 +1,92 @@ +//========================================================================== +// +// +// +// Opencores ethermac I/O definitions. +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Gaisler Research, (Konrad Eisele) +// Contributors: +// Date: 2000-11-22 +//####DESCRIPTIONEND#### +//========================================================================== + +#include +#include + +#define CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC_ETH0_ESA CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI_ETH0_ESA +#define CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC_INITFN openeth_phi_init + +#ifdef CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI_ETH0 + +//structs and tables for eth0 +static oeth_info openeth_priv; +ETH_DRV_SC(oeth_sc, + &openeth_priv, // Driver specific data + CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI_ETH0_NAME, // Name for device + openeth_start, + openeth_stop, + openeth_ioctl, + openeth_can_send, + openeth_send, + openeth_recv, + openeth_deliver, + openeth_poll, + openeth_int_vector +); + +NETDEVTAB_ENTRY(oeth_netdev, + "openeth_" CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI_ETH0_NAME, + openeth_init, + &oeth_sc); +#endif + +#if CYGNUM_DEVS_ETH_OPENCORES_ETHERMAC_DEV_COUNT > 1 +#error Only 1 ethermac at a time supported yet (eth0) +#endif + +oeth_info *openeth_priv_array[CYGNUM_DEVS_ETH_OPENCORES_ETHERMAC_DEV_COUNT] = { +#ifdef CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI_ETH0 + &openeth_priv +#endif +}; + + +//EOF devs_eth_zpu_opencorec_phi.inl + + diff --git a/zpu/sw/ecos/repository/dev/eth/zpu/opencores/phi/current/src/if_opencores.c b/zpu/sw/ecos/repository/dev/eth/zpu/opencores/phi/current/src/if_opencores.c new file mode 100644 index 0000000..c18caca --- /dev/null +++ b/zpu/sw/ecos/repository/dev/eth/zpu/opencores/phi/current/src/if_opencores.c @@ -0,0 +1,112 @@ +//========================================================================== +// +// +// +// Ethernet device driver for Opencore's ethermac on Zylin Phi +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//####BSDCOPYRIGHTBEGIN#### +// +// ------------------------------------------- +// +// Portions of this software may have been derived from OpenBSD or other sources, +// and are covered by the appropriate copyright disclaimers included herein. +// +// ------------------------------------------- +// +//####BSDCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Gaisler Research, (Konrad Eisele) +// Contributors: +// Date: 2005-01-20 +// Purpose: +// Description: hardware driver for Opencores ethernet +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include +#ifdef CYGPKG_IO_ETH_DRIVERS +#include +#endif +#include + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CYGPKG_NET +#include +#include +#include /* Needed for struct ifnet */ +#endif + +#include +#include +//#include + +externC void openeth_device_init(struct eth_drv_sc *sc, cyg_uint32 idx, cyg_uint32 base, cyg_uint32 irq); + +bool openeth_phi_init(struct cyg_netdevtab_entry *ndp) +{ + struct eth_drv_sc *sc = (struct eth_drv_sc *)(ndp->device_instance); + +#if !defined(CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC_FLUSH) +#error "CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC_FLUSH must be 1 for Zylin Phi" +#endif + +#if 0 + int i,j; + amba_ahb_device adev[CYGNUM_DEVS_ETH_OPENCORES_ETHERMAC_DEV_COUNT]; + j = amba_get_free_ahbslv_devices (VENDOR_GAISLER, GAISLER_ETHAHB, adev, CYGNUM_DEVS_ETH_OPENCORES_ETHERMAC_DEV_COUNT); + for (i = 0;i < j;i++) { + openeth_device_init(sc,i,adev[i].start[0],adev[i].irq); + } +#endif + openeth_device_init(sc, 0, 0x080C0000, CYGNUM_HAL_INTERRUPT_ETHERMAC); + return 1; +} diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/ChangeLog b/zpu/sw/ecos/repository/hal/zylin/arch/current/ChangeLog new file mode 100644 index 0000000..6403c63 --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/ChangeLog @@ -0,0 +1,39 @@ +2004-11-05 Øyvind Harboe + + * First cut of ZYLIN support + + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/cdl/hal_zylin.cdl b/zpu/sw/ecos/repository/hal/zylin/arch/current/cdl/hal_zylin.cdl new file mode 100644 index 0000000..cecc879 --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/cdl/hal_zylin.cdl @@ -0,0 +1,108 @@ +# ==================================================================== +# +# hal_zylin.cdl +# +# ZYLIN architectural HAL package configuration data +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): bartv +# Original data: gthomas +# Contributors: +# Date: 1999-06-13 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== +cdl_package CYGPKG_HAL_ZYLIN { + display "ZYLIN architecture" + parent CYGPKG_HAL + hardware + include_dir cyg/hal + requires !CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT + define_header hal_zylin.h + description " + The ZYLIN architecture HAL package provides generic + support for this processor architecture. It is also + necessary to select a specific target platform HAL + package." + + compile hal_misc.c context.S vectors.c + + # The "-o file" is a workaround for CR100958 - without it the + # output file would end up in the source directory under CygWin. + # n.b. grep does not behave itself under win32 + make -priority 1 { + zylin.inc : /src/hal_mk_defs.c + $(CC) $(CFLAGS) $(INCLUDE_PATH) -Wp,-MD,zylin.tmp -o hal_mk_defs.tmp -S $< + fgrep .equ hal_mk_defs.tmp | sed s/#// > $@ + @echo $@ ": \\" > $(notdir $@).deps + @tail -n +2 zylin.tmp >> $(notdir $@).deps + @echo >> $(notdir $@).deps + @rm zylin.tmp hal_mk_defs.tmp + } + + make { + /lib/vectors.o : /src/vectors.c + $(CC) -Wp,-MD,vectors.tmp $(INCLUDE_PATH) $(CFLAGS) -c -o $@ $< + @echo $@ ": \\" > $(notdir $@).deps + @tail -n +2 vectors.tmp >> $(notdir $@).deps + @echo >> $(notdir $@).deps + @rm vectors.tmp + } + + + make { + /lib/target.ld: /src/zylin.ld + $(CC) -E -P -Wp,-MD,target.tmp -xc $(INCLUDE_PATH) $(CFLAGS) -o $@ $< + @echo $@ ": \\" > $(notdir $@).deps + @tail -n +2 target.tmp >> $(notdir $@).deps + @echo >> $(notdir $@).deps + @rm target.tmp + } + + + cdl_option CYGBLD_LINKER_SCRIPT { + display "Linker script" + flavor data + no_define + calculated { "src/zylin.ld" } + } + +} + +# EOF hal_zylin.cdl diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/include/arch.inc b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/arch.inc new file mode 100644 index 0000000..a30819e --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/arch.inc @@ -0,0 +1,79 @@ +##============================================================================= +## +## arch.inc +## +## ZYLIN architecture assembler header file +## +##============================================================================= +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): jskov +## Contributors:jskov +## Date: 2000-11-15 +## Purpose: ZYLIN definitions. +## Description: This file contains various definitions and macros that are +## useful for writing assembly code for the ZYLIN +## It also includes the variant/platform assembly header file. +## Usage: +## #include +## ... +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include + +##----------------------------------------------------------------------------- +## ZYLIN entry definitions. This allows _ prefixing to change by modifying +## the CYG_LABEL_DEFN macro. + +#define FUNC_START(name) \ + .type CYG_LABEL_DEFN(name),@function; \ + .globl CYG_LABEL_DEFN(name); \ +CYG_LABEL_DEFN(name): + +#define FUNC_END(name) \ + .globl CYG_LABEL_DEFN(name); \ +CYG_LABEL_DEFN(name): + +#define SYM_DEF(name) \ + .globl CYG_LABEL_DEFN(name); \ +CYG_LABEL_DEFN(name): + +#------------------------------------------------------------------------------ +# end of arch.inc diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/include/basetype.h b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/basetype.h new file mode 100644 index 0000000..6f2c2c7 --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/basetype.h @@ -0,0 +1,83 @@ +#ifndef CYGONCE_HAL_BASETYPE_H +#define CYGONCE_HAL_BASETYPE_H + +//============================================================================= +// +// basetype.h +// +// Standard types for this architecture. +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, gthomas +// Contributors: nickg, gthomas +// Date: 1998-09-11 +// Purpose: Define architecture base types. +// Usage: Included by "cyg_type.h", do not use directly + +// +//####DESCRIPTIONEND#### +// + +//----------------------------------------------------------------------------- +// Characterize the architecture + +#define CYG_BYTEORDER CYG_MSBFIRST // Big endian +#define CYG_DOUBLE_BYTEORDER CYG_MSBFIRST // Big? endian + +//----------------------------------------------------------------------------- +// ZYLIN does not usually use labels with underscores. + +#define CYG_LABEL_NAME(_name_) _name_ +#define CYG_LABEL_DEFN(_name_) _name_ + +//----------------------------------------------------------------------------- +// Override the alignment definitions from cyg_type.h. ZYLIN only allows 4 +// byte alignment whereas the default is 8 byte. + +#define CYGARC_ALIGNMENT 4 +#define CYGARC_P2ALIGNMENT 2 + +//----------------------------------------------------------------------------- +// Define the standard variable sizes + +// The ZYLIN architecture uses the default definitions of the base types, +// so we do not need to define any here. + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_BASETYPE_H +// End of basetype.h diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_arch.h b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_arch.h new file mode 100644 index 0000000..cd61277 --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_arch.h @@ -0,0 +1,255 @@ +#ifndef CYGONCE_HAL_ARCH_H +#define CYGONCE_HAL_ARCH_H + +//========================================================================== +// +// hal_arch.h +// +// Architecture specific abstractions +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, gthomas +// Contributors: nickg, gthomas +// Date: 1999-02-20 +// Purpose: Define architecture abstractions +// Usage: #include + +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include // To decide on stack usage +#include +#include +#ifdef CYGBLD_HAL_ZYLIN_PLF_ARCH_H +#include +#endif + +#ifdef CYGBLD_HAL_ZYLIN_VAR_ARCH_H +#include +#endif + + +// It seems that r0-r3,r12 are considered scratch by function calls + +typedef struct +{ + cyg_uint32 reg[8]; + cyg_uint32 interrupt; + cyg_uint32 pc; // must be last... +} HAL_SavedRegisters; + +//------------------------------------------------------------------------- +// Exception handling function. +// This function is defined by the kernel according to this prototype. It is +// invoked from the HAL to deal with any CPU exceptions that the HAL does +// not want to deal with itself. It usually invokes the kernel's exception +// delivery mechanism. + +externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data ); + +//------------------------------------------------------------------------- +// Bit manipulation macros + +externC int hal_lsbindex(int); +externC int hal_msbindex(int); + +#define HAL_LSBIT_INDEX(index, mask) index = hal_lsbindex(mask) +#define HAL_MSBIT_INDEX(index, mask) index = hal_msbindex(mask) + +//------------------------------------------------------------------------- +// Context Initialization +// Initialize the context of a thread. +// Arguments: +// _sparg_ name of variable containing current sp, will be changed to new sp +// _thread_ thread object address, passed as argument to entry point +// _entry_ entry point address. +// _id_ bit pattern used in initializing registers, for debugging. + +#define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ ) \ + CYG_MACRO_START \ + cyg_uint32 *_sp_=(cyg_uint32 *)(((CYG_WORD)_sparg_) &~3); \ + *--_sp_=(CYG_ADDRWORD)_thread_; \ + *--_sp_=(CYG_ADDRWORD)0xffffffff; /* dummy return address */ \ + *--_sp_=(cyg_uint32)(_entry_); /* PC = [initial] entry point */ \ + *--_sp_= 0; /* interrupt mask */ \ + *--_sp_= (_id_)|7; \ + *--_sp_= (_id_)|6; \ + *--_sp_= (_id_)|5; \ + *--_sp_= (_id_)|4; \ + *--_sp_= (_id_)|3; \ + *--_sp_= (_id_)|2; \ + *--_sp_= (_id_)|1; \ + *--_sp_=(_id_)|0; \ + _sparg_ = (CYG_ADDRWORD)_sp_; \ + CYG_MACRO_END + +//-------------------------------------------------------------------------- +// Context switch macros. +// The arguments are pointers to locations where the stack pointer +// of the current thread is to be stored, and from where the sp of the +// next thread is to be fetched. + +externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from ); +externC void hal_thread_load_context( CYG_ADDRESS to ) + __attribute__ ((noreturn)); + +#define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_) \ + hal_thread_switch_context((CYG_ADDRESS)_tspptr_, \ + (CYG_ADDRESS)_fspptr_); + +#define HAL_THREAD_LOAD_CONTEXT(_tspptr_) \ + hal_thread_load_context( (CYG_ADDRESS)_tspptr_ ); + +//-------------------------------------------------------------------------- +// Execution reorder barrier. +// When optimizing the compiler can reorder code. In multithreaded systems +// where the order of actions is vital, this can sometimes cause problems. +// This macro may be inserted into places where reordering should not happen. + +#define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" ) + +//-------------------------------------------------------------------------- +// Breakpoint support +// HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to happen +// if executed. +// HAL_BREAKINST is the value of the breakpoint instruction and +// HAL_BREAKINST_SIZE is its size in bytes. + +#define _stringify1(__arg) #__arg +#define _stringify(__arg) _stringify1(__arg) + +#define HAL_BREAKINST_ZYLIN 0 +#define HAL_BREAKINST_ZYLIN_SIZE 1 + + +#define HAL_BREAKPOINT(_label_) \ +asm volatile (" .globl " #_label_ ";" \ + #_label_":" \ + " .byte " _stringify(HAL_BREAKINST_ZYLIN) \ + ); + +//#define HAL_BREAKINST {0xFE, 0xDE, 0xFF, 0xE7} +#define HAL_BREAKINST HAL_BREAKINST_ZYLIN +#define HAL_BREAKINST_SIZE HAL_BREAKINST_ZYLIN_SIZE +#define HAL_BREAKINST_TYPE cyg_uint8 + +extern cyg_uint32 __zylin_breakinst; +#define HAL_BREAKINST_ADDR(x) (void*)&__zylin_breakinst) + + +// Translate a stack pointer as saved by the thread context macros above into +// a pointer to a HAL_SavedRegisters structure. +#define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \ + (_regs_) = (HAL_SavedRegisters *)(_sp_) + + + +//-------------------------------------------------------------------------- +// HAL setjmp + +#define CYGARC_JMP_BUF_SIZE 16 // Actually 11, but some room left over + +typedef cyg_uint32 hal_jmp_buf[CYGARC_JMP_BUF_SIZE]; + +externC int hal_setjmp(hal_jmp_buf env); +externC void hal_longjmp(hal_jmp_buf env, int val); + + +//-------------------------------------------------------------------------- +// Idle thread code. +// This macro is called in the idle thread loop, and gives the HAL the +// chance to insert code. Typical idle thread behaviour might be to halt the +// processor. Here we only supply a default fallback if the variant/platform +// doesn't define anything. + +#ifndef HAL_IDLE_THREAD_ACTION +#define HAL_IDLE_THREAD_ACTION(_count_) CYG_EMPTY_STATEMENT +#endif + +//--------------------------------------------------------------------------- + +// Minimal and sensible stack sizes: the intention is that applications +// will use these to provide a stack size in the first instance prior to +// proper analysis. Idle thread stack should be this big. + +// THESE ARE NOT INTENDED TO BE MICROMETRICALLY ACCURATE FIGURES. +// THEY ARE HOWEVER ENOUGH TO START PROGRAMMING. +// YOU MUST MAKE YOUR STACKS LARGER IF YOU HAVE LARGE "AUTO" VARIABLES! + +// This is not a config option because it should not be adjusted except +// under "enough rope" sort of disclaimers. + +// A minimal, optimized stack frame, rounded up - no autos +#define CYGNUM_HAL_STACK_FRAME_SIZE (4 * 80) + +// Stack needed for a context switch: this is implicit in the estimate for +// interrupts so not explicitly used below: +#define CYGNUM_HAL_STACK_CONTEXT_SIZE (4 * 80) + +// Interrupt + call to ISR, interrupt_end() and the DSR +#define CYGNUM_HAL_STACK_INTERRUPT_SIZE \ + ((4 * 80) + 2 * CYGNUM_HAL_STACK_FRAME_SIZE) + +// Space for the maximum number of nested interrupts, plus room to call functions +#define CYGNUM_HAL_MAX_INTERRUPT_NESTING 16 + +#if 0 +#define CYGNUM_HAL_STACK_SIZE_MINIMUM + (CYGNUM_HAL_MAX_INTERRUPT_NESTING * CYGNUM_HAL_STACK_INTERRUPT_SIZE + \ + 2 * CYGNUM_HAL_STACK_FRAME_SIZE) + +#define CYGNUM_HAL_STACK_SIZE_TYPICAL \ + (CYGNUM_HAL_STACK_SIZE_MINIMUM + \ + 16 * CYGNUM_HAL_STACK_FRAME_SIZE) +#else +#define CYGNUM_HAL_STACK_SIZE_MINIMUM 16384 // KLUDGE!!! until interrupt stacks can be added + +#define CYGNUM_HAL_STACK_SIZE_TYPICAL 32768 // KLUDGE!!! until interrupt stacks can be added + +#endif + +//-------------------------------------------------------------------------- +// Macros for switching context between two eCos instances (jump from +// code in ROM to code in RAM or vice versa). +#define CYGARC_HAL_SAVE_GP() +#define CYGARC_HAL_RESTORE_GP() + +#endif // CYGONCE_HAL_ARCH_H +// End of hal_arch.h diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_intr.h b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_intr.h new file mode 100644 index 0000000..6ec6070 --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_intr.h @@ -0,0 +1,261 @@ +#ifndef CYGONCE_HAL_INTR_H +#define CYGONCE_HAL_INTR_H + +//========================================================================== +// +// hal_intr.h +// +// HAL Interrupt and clock support +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, gthomas +// Contributors: nickg, gthomas, +// jlzylinour +// Date: 1999-02-20 +// Purpose: Define Interrupt support +// Description: The macros defined here provide the HAL APIs for handling +// interrupts and the clock. +// +// Usage: #include +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include + +#include + +// This is to allow a variant to decide that there is no platform-specific +// interrupts file; and that in turn can be overridden by a platform that +// refines the variant's ideas. +#ifdef CYGBLD_HAL_PLF_INTS_H +# include CYGBLD_HAL_PLF_INTS_H // should include variant data as required +#else +# ifdef CYGBLD_HAL_VAR_INTS_H +# include CYGBLD_HAL_VAR_INTS_H +# else +# include // default less-complex platforms +# endif +#endif + +// Spurious interrupt (no interrupt source could be found) +#define CYGNUM_HAL_INTERRUPT_NONE -1 + +//-------------------------------------------------------------------------- +// ZYLIN exception vectors. + +// These vectors correspond to VSRs. These values are the ones to use for +// HAL_VSR_GET/SET + +#define CYGNUM_HAL_VECTOR_RESET 0 +#define CYGNUM_HAL_VECTOR_UNDEF_INSTRUCTION 1 +#define CYGNUM_HAL_VECTOR_MISC 2 +#define CYGNUM_HAL_VECTOR_IRQ 3 +#define CYGNUM_HAL_VECTOR_MEMORY 4 + +#define CYGNUM_HAL_VSR_MIN 0 +#define CYGNUM_HAL_VSR_MAX 4 +#define CYGNUM_HAL_VSR_COUNT 5 + +// Exception vectors. These are the values used when passed out to an +// external exception handler using cyg_hal_deliver_exception() + +#define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION \ + CYGNUM_HAL_VECTOR_UNDEF_INSTRUCTION +#define CYGNUM_HAL_EXCEPTION_INTERRUPT \ + CYGNUM_HAL_VECTOR_SOFTWARE_INTERRUPT +#define CYGNUM_HAL_EXCEPTION_CODE_ACCESS CYGNUM_HAL_VECTOR_MEMORY +#define CYGNUM_HAL_EXCEPTION_DATA_ACCESS CYGNUM_HAL_VECTOR_MEMORY + +#define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_VSR_MIN +#define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_VSR_MAX +#define CYGNUM_HAL_EXCEPTION_COUNT (CYGNUM_HAL_EXCEPTION_MAX - \ + CYGNUM_HAL_EXCEPTION_MIN + 1) + +//-------------------------------------------------------------------------- +// Static data used by HAL + +// ISR tables + +externC CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT]; +externC CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT]; +externC CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT]; + +// VSR table +externC CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_COUNT]; + +//-------------------------------------------------------------------------- +// Default ISR +// The #define is used to test whether this routine exists, and to allow +// code outside the HAL to call it. + +externC cyg_uint32 hal_default_isr(cyg_uint32 vector, CYG_ADDRWORD data); + +#define HAL_DEFAULT_ISR hal_default_isr + +//-------------------------------------------------------------------------- +// Interrupt state storage + +typedef cyg_uint32 CYG_INTERRUPT_STATE; + +//-------------------------------------------------------------------------- +// Interrupt control macros + +externC cyg_uint32 zpu_disable_interrupts(); +externC void zpu_enable_interrupts(); +externC void zpu_restore_interrupts(cyg_uint32); +externC cyg_uint32 zpu_query_interrupts(); + +#define HAL_DISABLE_INTERRUPTS(_old_) {_old_=zpu_disable_interrupts();} +#define HAL_ENABLE_INTERRUPTS() zpu_enable_interrupts() +#define HAL_RESTORE_INTERRUPTS(_old_) { zpu_restore_interrupts(_old_); } +#define HAL_QUERY_INTERRUPTS(_old_) { _old_=zpu_query_interrupts(); } + + +//-------------------------------------------------------------------------- +// Vector translation. + +#ifndef HAL_TRANSLATE_VECTOR +#define HAL_TRANSLATE_VECTOR(_vector_,_index_) \ + (_index_) = (_vector_) +#endif + +//-------------------------------------------------------------------------- +// Interrupt and VSR attachment macros + +#define HAL_INTERRUPT_IN_USE( _vector_, _state_) \ + CYG_MACRO_START \ + cyg_uint32 _index_; \ + HAL_TRANSLATE_VECTOR ((_vector_), _index_); \ + \ + if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr ) \ + (_state_) = 0; \ + else \ + (_state_) = 1; \ + CYG_MACRO_END + +#define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \ + CYG_MACRO_START \ + if( hal_interrupt_handlers[_vector_] == (CYG_ADDRESS)hal_default_isr ) \ + { \ + hal_interrupt_handlers[_vector_] = (CYG_ADDRESS)_isr_; \ + hal_interrupt_data[_vector_] = (CYG_ADDRWORD) _data_; \ + hal_interrupt_objects[_vector_] = (CYG_ADDRESS)_object_; \ + } \ + CYG_MACRO_END + +#define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \ + CYG_MACRO_START \ + if( hal_interrupt_handlers[_vector_] == (CYG_ADDRESS)_isr_ ) \ + { \ + hal_interrupt_handlers[_vector_] = (CYG_ADDRESS)hal_default_isr; \ + hal_interrupt_data[_vector_] = 0; \ + hal_interrupt_objects[_vector_] = 0; \ + } \ + CYG_MACRO_END + +#define HAL_VSR_GET( _vector_, _pvsr_ ) \ + *(CYG_ADDRESS *)(_pvsr_) = hal_vsr_table[_vector_]; + + +#define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) \ + CYG_MACRO_START \ + if( _poldvsr_ != NULL ) \ + *(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_]; \ + hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_; \ + CYG_MACRO_END + +//-------------------------------------------------------------------------- +// Interrupt controller access + +externC void hal_interrupt_mask(int); +externC void hal_interrupt_unmask(int); +externC void hal_interrupt_acknowledge(int); +externC void hal_interrupt_configure(int, int, int); +externC void hal_interrupt_set_level(int, int); + +#define HAL_INTERRUPT_MASK( _vector_ ) \ + hal_interrupt_mask( _vector_ ) +#define HAL_INTERRUPT_UNMASK( _vector_ ) \ + hal_interrupt_unmask( _vector_ ) +#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \ + hal_interrupt_acknowledge( _vector_ ) +#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \ + hal_interrupt_configure( _vector_, _level_, _up_ ) +#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \ + hal_interrupt_set_level( _vector_, _level_ ) + +//-------------------------------------------------------------------------- +// Clock control + +externC void hal_clock_initialize(cyg_uint32); +externC void hal_clock_read(cyg_uint32 *); +externC void hal_clock_reset(cyg_uint32, cyg_uint32); + +#define HAL_CLOCK_INITIALIZE( _period_ ) hal_clock_initialize( _period_ ) +#define HAL_CLOCK_RESET( _vec_, _period_ ) hal_clock_reset( _vec_, _period_ ) +#define HAL_CLOCK_READ( _pvalue_ ) hal_clock_read( _pvalue_ ) +#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY +# ifndef HAL_CLOCK_LATENCY +# define HAL_CLOCK_LATENCY( _pvalue_ ) HAL_CLOCK_READ( (cyg_uint32 *)_pvalue_ ) +# endif +#endif + + +#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK +externC void hal_interrupt_stack_call_pending_DSRs(void); +#define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \ + hal_interrupt_stack_call_pending_DSRs() + +// these are offered solely for stack usage testing +// if they are not defined, then there is no interrupt stack. +#define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base +#define HAL_INTERRUPT_STACK_TOP cyg_interrupt_stack +// use them to declare these extern however you want: +// extern char HAL_INTERRUPT_STACK_BASE[]; +// extern char HAL_INTERRUPT_STACK_TOP[]; +// is recommended +#endif + + +//-------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_INTR_H +// End of hal_intr.h diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_io.h b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_io.h new file mode 100644 index 0000000..64ad695 --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_io.h @@ -0,0 +1,305 @@ +#ifndef CYGONCE_HAL_IO_H +#define CYGONCE_HAL_IO_H + +//============================================================================= +// +// hal_io.h +// +// HAL device IO register support. +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, gthomas +// Contributors: Fabrice Gautier +// Date: 1998-09-11 +// Purpose: Define IO register support +// Description: The macros defined here provide the HAL APIs for handling +// device IO control registers. +// +// Usage: +// #include +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include +#include + +#include + +//----------------------------------------------------------------------------- +// Include plf_io.h for platforms. Either via var_io.h or directly. +#ifdef CYGBLD_HAL_ZYLIN_VAR_IO_H +#include +#else +#include +#endif + + +//----------------------------------------------------------------------------- +// IO Register address. +// This type is for recording the address of an IO register. + +typedef volatile CYG_ADDRWORD HAL_IO_REGISTER; + +//----------------------------------------------------------------------------- +// HAL IO macros. +#ifndef HAL_IO_MACROS_DEFINED + +//----------------------------------------------------------------------------- +// BYTE Register access. +// Individual and vectorized access to 8 bit registers. + +// Little-endian version or big-endian version that doesn't need address munging +#if (CYG_BYTEORDER == CYG_LSBFIRST) || defined(HAL_IO_MACROS_NO_ADDRESS_MUNGING) + +#define HAL_READ_UINT8( _register_, _value_ ) \ + ((_value_) = *((volatile CYG_BYTE *)(_register_))) + +#define HAL_WRITE_UINT8( _register_, _value_ ) \ + (*((volatile CYG_BYTE *)(_register_)) = (_value_)) + +#define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + (_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_j_]; \ + CYG_MACRO_END + +#define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + ((volatile CYG_BYTE *)(_register_))[_j_] = (_buf_)[_i_]; \ + CYG_MACRO_END + +#define HAL_READ_UINT8_STRING( _register_, _buf_, _count_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_; \ + for( _i_ = 0; _i_ < (_count_); _i_++) \ + (_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_i_]; \ + CYG_MACRO_END + +#define HAL_WRITE_UINT8_STRING( _register_, _buf_, _count_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_; \ + for( _i_ = 0; _i_ < (_count_); _i_++) \ + ((volatile CYG_BYTE *)(_register_)) = (_buf_)[_i_]; \ + CYG_MACRO_END + +#else // Big-endian version + +#define HAL_READ_UINT8( _register_, _value_ ) \ + ((_value_) = *((volatile CYG_BYTE *)((CYG_ADDRWORD)(_register_)^3))) + +#define HAL_WRITE_UINT8( _register_, _value_ ) \ + (*((volatile CYG_BYTE *)((CYG_ADDRWORD)(_register_)^3)) = (_value_)) + +#define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + volatile CYG_BYTE* _r_ = ((CYG_ADDRWORD)(_register_)^3); \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + (_buf_)[_i_] = _r_[_j_]; \ + CYG_MACRO_END + +#define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + volatile CYG_BYTE* _r_ = ((CYG_ADDRWORD)(_register_)^3); \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + _r_[_j_] = (_buf_)[_i_]; \ + CYG_MACRO_END + +#define HAL_READ_UINT8_STRING( _register_, _buf_, _count_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_; \ + volatile CYG_BYTE* _r_ = ((CYG_ADDRWORD)(_register_)^3); \ + for( _i_ = 0; _i_ < (_count_); _i_++; \ + (_buf_)[_i_] = _r_[_i_]; \ + CYG_MACRO_END + +#define HAL_WRITE_UINT8_STRING( _register_, _buf_, _count_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_; \ + volatile CYG_BYTE* _r_ = ((CYG_ADDRWORD)(_register_)^3); \ + for( _i_ = 0; _i_ < (_count_); _i_++) \ + _r_[_i_] = (_buf_)[_i_]; \ + CYG_MACRO_END + +#endif // Big-endian + +//----------------------------------------------------------------------------- +// 16 bit access. +// Individual and vectorized access to 16 bit registers. + +// Little-endian version or big-endian version that doesn't need address munging +#if (CYG_BYTEORDER == CYG_LSBFIRST) || defined(HAL_IO_MACROS_NO_ADDRESS_MUNGING) + +#define HAL_READ_UINT16( _register_, _value_ ) \ + ((_value_) = *((volatile CYG_WORD16 *)(_register_))) + +#define HAL_WRITE_UINT16( _register_, _value_ ) \ + (*((volatile CYG_WORD16 *)(_register_)) = (_value_)) + +#define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + (_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_j_]; \ + CYG_MACRO_END + +#define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + ((volatile CYG_WORD16 *)(_register_))[_j_] = (_buf_)[_i_]; \ + CYG_MACRO_END + +#define HAL_READ_UINT16_STRING( _register_, _buf_, _count_) \ + CYG_MACRO_START \ + cyg_count32 _i_; \ + for( _i_ = 0; _i_ < (_count_); _i_++) \ + (_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_i_]; \ + CYG_MACRO_END + +#define HAL_WRITE_UINT16_STRING( _register_, _buf_, _count_) \ + CYG_MACRO_START \ + cyg_count32 _i_; \ + for( _i_ = 0; _i_ < (_count_); _i_++) \ + ((volatile CYG_WORD16 *)(_register_))[_i_] = (_buf_)[_i_]; \ + CYG_MACRO_END + + +#else // Big-endian version + +#define HAL_READ_UINT16( _register_, _value_ ) \ + ((_value_) = *((volatile CYG_WORD16 *)((CYG_ADDRWORD)(_register_)^3))) + +#define HAL_WRITE_UINT16( _register_, _value_ ) \ + (*((volatile CYG_WORD16 *)((CYG_ADDRWORD)(_register_)^3)) = (_value_)) + +#define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + volatile CYG_WORD16* _r_ = ((CYG_ADDRWORD)(_register_)^3); \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + (_buf_)[_i_] = _r_[_j_]; \ + CYG_MACRO_END + +#define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + volatile CYG_WORD16* _r_ = ((CYG_ADDRWORD)(_register_)^3); \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + _r_[_j_] = (_buf_)[_i_]; \ + CYG_MACRO_END + +#define HAL_READ_UINT16_STRING( _register_, _buf_, _count_) \ + CYG_MACRO_START \ + cyg_count32 _i_; \ + volatile CYG_WORD16* _r_ = ((CYG_ADDRWORD)(_register_)^3); \ + for( _i_ = 0 = 0; _i_ < (_count_); _i_++) \ + (_buf_)[_i_] = _r_[_i_]; \ + CYG_MACRO_END + +#define HAL_WRITE_UINT16_STRING( _register_, _buf_, _count_) \ + CYG_MACRO_START \ + cyg_count32 _i_; \ + volatile CYG_WORD16* _r_ = ((CYG_ADDRWORD)(_register_)^3); \ + for( _i_ = 0 = 0; _i_ < (_count_); _i_++) \ + _r_[_i_] = (_buf_)[_i_]; \ + CYG_MACRO_END + + +#endif // Big-endian + +//----------------------------------------------------------------------------- +// 32 bit access. +// Individual and vectorized access to 32 bit registers. + +// Note: same macros for little- and big-endian systems. + +#define HAL_READ_UINT32( _register_, _value_ ) \ + ((_value_) = *((volatile CYG_WORD32 *)(_register_))) + +#define HAL_WRITE_UINT32( _register_, _value_ ) \ + (*((volatile CYG_WORD32 *)(_register_)) = (_value_)) + +#define HAL_READ_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + (_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_j_]; \ + CYG_MACRO_END + +#define HAL_WRITE_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \ + CYG_MACRO_START \ + cyg_count32 _i_,_j_; \ + for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ + ((volatile CYG_WORD32 *)(_register_))[_j_] = (_buf_)[_i_]; \ + CYG_MACRO_END + +#define HAL_READ_UINT32_STRING( _register_, _buf_, _count_) \ + CYG_MACRO_START \ + cyg_count32 _i_; \ + for( _i_ = 0; _i_ < (_count_); _i_++) \ + (_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_i_]; \ + CYG_MACRO_END + +#define HAL_WRITE_UINT32_STRING( _register_, _buf_, _count_) \ + CYG_MACRO_START \ + cyg_count32 _i_; \ + for( _i_ = 0; _i_ < (_count_); _i_++) \ + ((volatile CYG_WORD32 *)(_register_))[_i_] = (_buf_)[_i_]; \ + CYG_MACRO_END + + +#define HAL_IO_MACROS_DEFINED + +#endif // !HAL_IO_MACROS_DEFINED + +// Enforce a flow "barrier" to prevent optimizing compiler from reordering +// operations. +#define HAL_IO_BARRIER() + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_IO_H +// End of hal_io.h diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/src/context.S b/zpu/sw/ecos/repository/hal/zylin/arch/current/src/context.S new file mode 100644 index 0000000..6b0b833 --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/src/context.S @@ -0,0 +1,324 @@ +// #=========================================================================== +// # +// # context.S +// # +// # ZYLIN context switch code +// # +// #=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +// #=========================================================================== +// ######DESCRIPTIONBEGIN#### +// # +// # Author(s): nickg, gthomas +// # Contributors: nickg, gthomas +// # Date: 1998-09-15 +// # Purpose: ZYLIN context switch code +// # Description: This file contains implementations of the thread context +// # switch routines. It also contains the longjmp() and setjmp() +// # routines. +// # +// #####DESCRIPTIONEND#### +// # +// #=========================================================================== + +#include +#ifdef CYGPKG_KERNEL // no CDL yet +#include +#else +# undef CYGFUN_HAL_COMMON_KERNEL_SUPPORT +# undef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK +#endif + + + + +#include "zylin.inc" + + .text + + +;; By using a macro, we get multiple breakpoint sites + .macro LOAD_STATE + popsp + ; stack pointer now points to beginning of HAL_SavedRegisters + ; we now pop the state of the CPU + + ; this will restore r0-r3 + im 0 + store + im 4 + store + im 8 + store + im 12 + store + im 16 + store + im 20 + store + im 24 + store + im 28 + store + + ;; restore interrupts + im INTERRUPT_MASK + load + store + + + .endm + + +// ---------------------------------------------------------------------------- +// hal_thread_switch_context +// Switch thread contexts + + + .globl hal_thread_switch_context +hal_thread_switch_context: + + ;; save interrupt state + im INTERRUPT_MASK + load + load + + ; store current state on stack + im 28 + load + im 24 + load + im 20 + load + im 16 + load + im 12 + load + im 8 + load + im 4 + load + im 0 + load + + + ;; store pointer to SP in "from" pointer + pushsp + pushsp + im 8+8*4+4+4 + add + load + store + + ;; put pointer to '*to' on stack + pushsp + im 4+8*4+4 + add + load + load + + LOAD_STATE + + poppc ; voila! jump to saved pc + + + + +// ---------------------------------------------------------------------------- +// hal_thread_load_context +// Load thread context + + .globl hal_thread_load_context +hal_thread_load_context: + pushsp + im 4 + add + load + load ; pointer to HAL_SavedRegisters on stack + +load_state_internal: + LOAD_STATE + + poppc ; voila! jump to saved pc + +// ---------------------------------------------------------------------------- +// HAL longjmp, setjmp implementations + + .globl hal_setjmp +hal_setjmp: + .byte 0 + + + .globl hal_longjmp + hal_longjmp: + .byte 0 + +// ---------------------------------------------------------------------------- +// end of context.S + +#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK + + ; push 1 onto stack if we're already switched, 0 otherwise + .macro check_thread_stack + pushsp ; 0xda68 + im __interrupt_stack ; 0x241a + lessthan ; => 1 + im __interrupt_stack_base + pushsp + lessthan + or + + .endm + + ; push 1 onto stack if we're already switched, 0 otherwise + .macro switch_stack + pushsp + im __interrupt_stack-4 + store ; saved stack pointer on interrupt stack. + + im __interrupt_stack-4 + popsp + ; we're now on the interrupt stack + + .endm + + .macro switch_stack_back + ; return to thread stack + popsp + .endm + +_zpu_invoke_zpu_interrupt_stack: + im hal_IRQ_handler + call + im 0 + load ; return value - source + + im _zpu_interrupt_stack + call + im 0 + load ; return value - result + + ; we've got source and ISR result args on the stack + im _zpu_interrupt_thread + call + storesp 0 ; destroy args + storesp 0 + + poppc + + +// switch to interrupt stack, invoke interrupt handler, switch back to original stack, enable interrupts + .globl _zpu_interrupt +_zpu_interrupt: + ; disable interrupts, we don't nest + im 1 + nop + im INTERRUPT_MASK + load + store + + ; if we're interrupting the DSRs then + ; we're already on the interrupt stack + check_thread_stack + + impcrel _already_switched + eqbranch + +_zpu_interrupt_switch_stack: + switch_stack + + im _zpu_invoke_zpu_interrupt_stack + call + + switch_stack_back + + im .already_switched2 + poppc + +_already_switched: + im _zpu_invoke_zpu_interrupt_stack + call + +.already_switched2: + ; turn on interrupts and run on thread stack. + im 0 + nop + im INTERRUPT_MASK + load + store ; unmask interrupts + + ; we're now running on thread stack + + im _zpu_interrupt_thread + call + + poppc + + .globl hal_interrupt_stack_call_pending_DSRs +hal_interrupt_stack_call_pending_DSRs: + ; the scheduler is not running, so only interrupts + ; could have switched stacks at this point and + ; since we're running, interrupts are not + switch_stack + + im cyg_interrupt_call_pending_DSRs + call + + switch_stack_back + + ; back on thread stack + poppc + + + + +// Runtime stack used during all interrupt processing +#ifndef CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE +#define CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE 4096 +#endif + .bss + .balign 4,0 + .global cyg_interrupt_stack_base +cyg_interrupt_stack_base: +__interrupt_stack_base: + .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + .byte 0 + .endr + .balign 4,0 + .global cyg_interrupt_stack +cyg_interrupt_stack: +__interrupt_stack: +#endif + + diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/src/hal_misc.c b/zpu/sw/ecos/repository/hal/zylin/arch/current/src/hal_misc.c new file mode 100644 index 0000000..eea2465 --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/src/hal_misc.c @@ -0,0 +1,177 @@ +/*========================================================================== +// +// hal_misc.c +// +// HAL miscellaneous functions +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, gthomas +// Contributors: nickg, gthomas +// Date: 1999-02-20 +// Purpose: HAL miscellaneous functions +// Description: This file contains miscellaneous functions provided by the +// HAL. +// +//####DESCRIPTIONEND#### +// +//=========================================================================*/ + +#include +#include +#ifdef CYGPKG_KERNEL +#include +#endif +#ifdef CYGPKG_CYGMON +#include +#endif + +#include +#include // tracing macros +#include // assertion macros + +#include // HAL header +#include // HAL header + +#include +#include + +externC void diag_printf(const char *fmt, ...); + +/*------------------------------------------------------------------------*/ +/* First level C exception handler. */ + + +/*------------------------------------------------------------------------*/ +/* C++ support - run initial constructors */ + +#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG +cyg_bool cyg_hal_stop_constructors; +#endif + +typedef void (*pfunc) (void); +extern pfunc __CTOR_LIST__[]; +extern pfunc __CTOR_END__[]; + +void +cyg_hal_invoke_constructors (void) +{ +#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG + static pfunc *p = &__CTOR_END__[-1]; + + cyg_hal_stop_constructors = 0; + for (; p >= __CTOR_LIST__; p--) { + (*p) (); + if (cyg_hal_stop_constructors) { + p--; + break; + } + } +#else + pfunc *p; + + for (p = &__CTOR_END__[-1]; p >= __CTOR_LIST__; p--) + (*p) (); +#endif +} + + +/*-------------------------------------------------------------------------*/ +/* Misc functions */ + +int +hal_lsbindex(int mask) +{ + int i; + for (i = 0; i < 32; i++) { + if (mask & (1<= 0; i--) { + if (mask & (1< + +#include // HAL header +#include // HAL header +#ifdef CYGPKG_KERNEL +# include +# include +#endif +#include + +/* + * This program is used to generate definitions needed by + * assembly language modules. + * + * This technique was first used in the OSF Mach kernel code: + * generate asm statements containing #defines, + * compile this file to assembler, and then extract the + * #defines from the assembly-language output. + */ + +#define DEFINE(sym, val) \ + asm volatile("\n\t.equ\t" #sym ",%0" : : "i" (val)) + +int +main(void) +{ + DEFINE(CYGNUM_HAL_ISR_COUNT, CYGNUM_HAL_ISR_COUNT); + DEFINE(CYGNUM_HAL_VSR_COUNT, CYGNUM_HAL_VSR_COUNT); + DEFINE(CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION, + CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION); + DEFINE(CYGNUM_HAL_EXCEPTION_CODE_ACCESS, + CYGNUM_HAL_EXCEPTION_CODE_ACCESS); + DEFINE(CYGNUM_HAL_EXCEPTION_DATA_ACCESS, + CYGNUM_HAL_EXCEPTION_DATA_ACCESS); + DEFINE(CYGNUM_HAL_VECTOR_IRQ, CYGNUM_HAL_VECTOR_IRQ); +#ifdef CYGPKG_KERNEL + DEFINE(RAISE_INTR, CYG_INSTRUMENT_CLASS_INTR|CYG_INSTRUMENT_EVENT_INTR_RAISE); +#endif +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT) + DEFINE(CYGNUM_CALL_IF_TABLE_SIZE, CYGNUM_CALL_IF_TABLE_SIZE); +#endif + DEFINE(CYGNUM_HAL_INTERRUPT_NONE, CYGNUM_HAL_INTERRUPT_NONE); + return 0; +} + + +/*------------------------------------------------------------------------*/ +// EOF hal_mk_defs.c diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/src/vectors.c b/zpu/sw/ecos/repository/hal/zylin/arch/current/src/vectors.c new file mode 100644 index 0000000..b254a85 --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/src/vectors.c @@ -0,0 +1,116 @@ +#include +#include +#ifdef CYGPKG_KERNEL +#include +#endif +#ifdef CYGPKG_CYGMON +#include +#endif + +#include +#include // tracing macros +#include // assertion macros + +#include // HAL header +#include // HAL header +#include +#include // Register state info + +extern char __bss_start[]; +extern char __bss_end[]; + +externC void cyg_hal_invoke_constructors (void); +externC void cyg_start (void); +externC void hal_hardware_init (void); +externC void _initIO(); + +void _premain(void) +{ + // clear BSS + memset(__bss_start, 0, __bss_end-__bss_start); + + _initIO(); + + hal_hardware_init(); + + cyg_hal_invoke_constructors(); + + cyg_start(); + + __asm("breakpoint"); // stop debugger/sim here for now +// for (;;); // hang forever +} + +CYG_ADDRWORD hal_vsr_table[CYGNUM_HAL_VSR_COUNT]; +CYG_ADDRWORD hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT]; +CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT]; +CYG_ADDRWORD hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT]; + +externC cyg_ucount32 cyg_scheduler_sched_lock; +externC cyg_uint32 hal_IRQ_handler(); + +externC void interrupt_end( + cyg_uint32 isr_ret, + CYG_ADDRWORD intr, + HAL_SavedRegisters *ctx + ); + + +#ifndef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK + + +void _zpu_interrupt(void) +{ + cyg_uint32 source; +#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT + cyg_scheduler_sched_lock++; +#endif + /* we don't support reentrant interrupts, so we disable interrupts here. */ + cyg_uint32 t; + HAL_DISABLE_INTERRUPTS(t); + + source=hal_IRQ_handler(); + if (source!=CYGNUM_HAL_INTERRUPT_NONE) + { + + cyg_uint32 result; + + result=((cyg_uint32 (*)(cyg_uint32, CYG_ADDRWORD))hal_interrupt_handlers[source])(source, hal_interrupt_data[source]); + /* restore interrupts again. */ + HAL_ENABLE_INTERRUPTS(); + /* Interrupts must be enabled here as the scheduler is invoked here. */ + interrupt_end(result, hal_interrupt_objects[source], NULL); + } else + { + /* restore interrupts again. */ + HAL_ENABLE_INTERRUPTS(); + } +} +#else +/* low-level interrupt handling routine */ +cyg_uint32 _zpu_interrupt_stack(cyg_uint32 source) +{ +#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT + cyg_scheduler_sched_lock++; +#endif + /* we don't support reentrant interrupts, so we disable interrupts here. */ + cyg_uint32 t; + HAL_DISABLE_INTERRUPTS(t); + + cyg_uint32 result=0; + if (source!=CYGNUM_HAL_INTERRUPT_NONE) + { + cyg_uint32 result; + result=((cyg_uint32 (*)(cyg_uint32, CYG_ADDRWORD))hal_interrupt_handlers[source])(source, hal_interrupt_data[source]); + } + return result; +} +void _zpu_interrupt_thread(cyg_uint32 source, cyg_uint32 result) +{ + if (source!=CYGNUM_HAL_INTERRUPT_NONE) + { + /* Interrupts must be enabled here as the scheduler is invoked here. */ + interrupt_end(result, hal_interrupt_objects[source], NULL); + } +} +#endif diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/src/zylin.ld b/zpu/sw/ecos/repository/hal/zylin/arch/current/src/zylin.ld new file mode 100644 index 0000000..eef2cd7 --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/src/zylin.ld @@ -0,0 +1,226 @@ +//============================================================================= +// +// MLT linker script for ZYLIN +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= + +#include + +STARTUP(crt0.o) +ENTRY(_start) +INPUT(crt_io.o) +INPUT(extras.o) +INPUT(vectors.o) +GROUP(libtarget.a libgcc.a libsupc++.a) + +// Keep RODATA in separate sections. +#define MERGE_IN_RODATA + +#define ALIGN_LMA 4 +#define FOLLOWING(_section_) AT ((LOADADDR (_section_) + SIZEOF (_section_) + ALIGN_LMA - 1) & ~ (ALIGN_LMA - 1)) +#define LMA_EQ_VMA +#define FORCE_OUTPUT . = . + +#define SECTIONS_BEGIN + +#define SECTION_fixed_vectors(_region_, _vma_, _lma_) \ + .fixed_vectors _vma_ : _lma_ \ + { FORCE_OUTPUT; KEEP (*(.fixed_vectors)) } \ + > _region_ + +#define SECTION_rom_vectors(_region_, _vma_, _lma_) \ + .rom_vectors _vma_ : _lma_ \ + { __rom_vectors_vma = ABSOLUTE(.); \ + FORCE_OUTPUT; KEEP (*(.vectors)) } \ + > _region_ \ + __rom_vectors_lma = LOADADDR(.rom_vectors); + +#define SECTION_text(_region_, _vma_, _lma_) \ + .text _vma_ : _lma_ \ + { _stext = ABSOLUTE(.); \ + PROVIDE (__stext = ABSOLUTE(.)); \ + *(.text*) *(.gnu.warning) *(.gnu.linkonce.t.*) *(.init) \ + *(.glue_7) *(.glue_7t) \ + } > _region_ \ + _etext = .; PROVIDE (__etext = .); + +#define SECTION_fini(_region_, _vma_, _lma_) \ + .fini _vma_ : _lma_ \ + { FORCE_OUTPUT; *(.fini) } \ + > _region_ + +#define SECTION_rodata(_region_, _vma_, _lma_) \ + .rodata _vma_ : _lma_ \ + { FORCE_OUTPUT; *(.rodata*) *(.gnu.linkonce.r.*) } \ + > _region_ + +#define SECTION_rodata1(_region_, _vma_, _lma_) \ + .rodata1 _vma_ : _lma_ \ + { FORCE_OUTPUT; *(.rodata1) } \ + > _region_ + +#define SECTION_fixup(_region_, _vma_, _lma_) \ + .fixup _vma_ : _lma_ \ + { FORCE_OUTPUT; *(.fixup) } \ + > _region_ + +#define SECTION_gcc_except_table(_region_, _vma_, _lma_) \ + .gcc_except_table _vma_ : _lma_ \ + { FORCE_OUTPUT; *(.gcc_except_table) } \ + > _region_ + +#define SECTION_eh_frame(_region_, _vma_, _lma_) \ + .eh_frame _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; __EH_FRAME_BEGIN__ = .; \ + KEEP(*(.eh_frame)) \ + __FRAME_END__ = .; \ + . = . + 8; \ + } > _region_ = 0 + +#define SECTION_RELOCS(_region_, _vma_, _lma_) \ + .rel.text : \ + { \ + *(.rel.text) \ + *(.rel.text.*) \ + *(.rel.gnu.linkonce.t*) \ + } > _region_ \ + .rela.text : \ + { \ + *(.rela.text) \ + *(.rela.text.*) \ + *(.rela.gnu.linkonce.t*) \ + } > _region_ \ + .rel.data : \ + { \ + *(.rel.data) \ + *(.rel.data.*) \ + *(.rel.gnu.linkonce.d*) \ + } > _region_ \ + .rela.data : \ + { \ + *(.rela.data) \ + *(.rela.data.*) \ + *(.rela.gnu.linkonce.d*) \ + } > _region_ \ + .rel.rodata : \ + { \ + *(.rel.rodata) \ + *(.rel.rodata.*) \ + *(.rel.gnu.linkonce.r*) \ + } > _region_ \ + .rela.rodata : \ + { \ + *(.rela.rodata) \ + *(.rela.rodata.*) \ + *(.rela.gnu.linkonce.r*) \ + } > _region_ \ + .rel.got : { *(.rel.got) } > _region_ \ + .rela.got : { *(.rela.got) } > _region_ \ + .rel.ctors : { *(.rel.ctors) } > _region_ \ + .rela.ctors : { *(.rela.ctors) } > _region_ \ + .rel.dtors : { *(.rel.dtors) } > _region_ \ + .rela.dtors : { *(.rela.dtors) } > _region_ \ + .rel.init : { *(.rel.init) } > _region_ \ + .rela.init : { *(.rela.init) } > _region_ \ + .rel.fini : { *(.rel.fini) } > _region_ \ + .rela.fini : { *(.rela.fini) } > _region_ \ + .rel.bss : { *(.rel.bss) } > _region_ \ + .rela.bss : { *(.rela.bss) } > _region_ \ + .rel.plt : { *(.rel.plt) } > _region_ \ + .rela.plt : { *(.rela.plt) } > _region_ \ + .rel.dyn : { *(.rel.dyn) } > _region_ + +#define SECTION_got(_region_, _vma_, _lma_) \ + .got _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; *(.got.plt) *(.got) \ + _GOT1_START_ = ABSOLUTE (.); *(.got1) _GOT1_END_ = ABSOLUTE (.); \ + _GOT2_START_ = ABSOLUTE (.); *(.got2) _GOT2_END_ = ABSOLUTE (.); \ + } > _region_ + +#define SECTION_mmu_tables(_region_, _vma_, _lma_) \ + .mmu_tables _vma_ : _lma_ \ + { FORCE_OUTPUT; *(.mmu_tables) } \ + > _region_ + +#define SECTION_sram(_region_, _vma_, _lma_) \ + .sram _vma_ : _lma_ \ + { FORCE_OUTPUT; *(.sram*) } \ + > _region_ + +#define SECTION_data(_region_, _vma_, _lma_) \ + .data _vma_ : _lma_ \ + { __ram_data_start = ABSOLUTE (.); \ + *(.data*) *(.data1) *(.gnu.linkonce.d.*) MERGE_IN_RODATA \ + . = ALIGN (4); \ + KEEP(*( SORT (.ecos.table.*))) ; \ + . = ALIGN (4); \ + __CTOR_LIST__ = ABSOLUTE (.); KEEP (*(SORT (.ctors*))) __CTOR_END__ = ABSOLUTE (.); \ + __DTOR_LIST__ = ABSOLUTE (.); KEEP (*(SORT (.dtors*))) __DTOR_END__ = ABSOLUTE (.); \ + *(.dynamic) *(.sdata*) *(.gnu.linkonce.s.*) \ + . = ALIGN (4); *(.2ram.*) } \ + > _region_ \ + __rom_data_start = LOADADDR (.data); \ + __ram_data_end = .; PROVIDE (__ram_data_end = .); _edata = .; PROVIDE (edata = .); \ + PROVIDE (__rom_data_end = LOADADDR (.data) + SIZEOF(.data)); + +#define SECTION_bss(_region_, _vma_, _lma_) \ + .bss _vma_ : _lma_ \ + { __bss_start = ABSOLUTE (.); \ + *(.scommon) *(.dynsbss) *(.sbss*) *(.gnu.linkonce.sb.*) \ + *(.dynbss) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON) \ + __bss_end = ABSOLUTE (.); } \ + > _region_ + +// Some versions of gcc define "zpu" which causes problems with .note.arm.ident +#undef zpu +#define SECTIONS_END . = ALIGN(4); _end = .; PROVIDE (end = .); \ + /* Debug information */ \ + .debug_aranges 0 : { *(.debug_aranges) } \ + .debug_pubnames 0 : { *(.debug_pubnames) } \ + .debug_info 0 : { *(.debug_info) } \ + .debug_abbrev 0 : { *(.debug_abbrev) } \ + .debug_line 0 : { *(.debug_line) } \ + .debug_frame 0 : { *(.debug_frame) } \ + .debug_str 0 : { *(.debug_str) } \ + .debug_loc 0 : { *(.debug_loc) } \ + .debug_macinfo 0 : { *(.debug_macinfo) } \ + .note.gnu.zpu.ident 0 : { KEEP (*(.note.gnu.zpu.ident)) } + + +#include +#include CYGHWR_MEMORY_LAYOUT_LDI diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/ChangeLog b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/ChangeLog new file mode 100644 index 0000000..a29dbf8 --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/ChangeLog @@ -0,0 +1,39 @@ +2004-09-16 Øyvind Harboe + + * first cut HAL support for ZPU + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2003 Nick Garnett +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/cdl/hal_zylin_zpu_abel.cdl b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/cdl/hal_zylin_zpu_abel.cdl new file mode 100644 index 0000000..f5c2f81 --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/cdl/hal_zylin_zpu_abel.cdl @@ -0,0 +1,298 @@ +# ==================================================================== +# +# hal_zpu.cdl +# +# ZPU HAL package configuration data +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): +# Contributors: +# Date: 2001-07-12 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_HAL_ZYLIN_ZPU_ABEL { + display "Zylin ZPU HAL" + parent CYGPKG_HAL_ZYLIN_ZPU + define_header hal_zylin_zpu_abel.h + include_dir cyg/hal + hardware + description " + The Zylin ZPU HAL package provides the support needed to run + eCos on an Zylin ZPU board using the Abel board." + + compile abel_misc.c + + requires { CYGHWR_HAL_ZYLIN_ZPU == "ZPU1" } + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H " + puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H " + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H " + puts $::cdl_header "#define HAL_PLATFORM_CPU \"ZPU1\"" + puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Zylin Abel\"" + puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" + } + + # Real-time clock/counter specifics + cdl_option CYGNUM_HAL_ZYLIN_ZPU_CLOCK_SPEED { + display "CPU clock speed" + flavor data + default_value 90000000 + } + + cdl_component CYGNUM_HAL_RTC_CONSTANTS { + display "Real-time clock constants" + flavor none + + cdl_option CYGNUM_HAL_RTC_NUMERATOR { + display "Real-time clock numerator" + flavor data + default_value 1000000000 + } + cdl_option CYGNUM_HAL_RTC_DENOMINATOR { + display "Real-time clock denominator" + flavor data + default_value 100 + } + cdl_option CYGNUM_HAL_RTC_PERIOD { + display "Real-time clock period" + flavor data + default_value (CYGNUM_HAL_ZYLIN_ZPU_CLOCK_SPEED / CYGNUM_HAL_RTC_DENOMINATOR) + } + } + + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + default_value {"RAM"} + legal_values {"RAM"} + no_define + define -file system.h CYG_HAL_STARTUP + description " + When targetting the ZPU board it is possible to build + the system for either RAM bootstrap or ROM bootstrap(s). Select + 'ram' when building programs to load into RAM using onboard + debug software such as Angel or eCos GDB stubs. Select 'rom' + when building a stand-alone application which will be put + into ROM. Using ROMRAM will allow the program to exist in + ROM, but be copied to RAM during startup." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + calculated 1 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + This option + chooses which port will be used to connect to a host + running GDB." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + This option + chooses which port will be used for diagnostic output." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { + display "Diagnostic serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 38400 + description " + This option selects the baud rate used for the diagnostic port." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD { + display "GDB serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 38400 + description " + This option controls the baud rate used for the GDB connection." + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" } + description " + Enable this option if this program is to be used as a ROM monitor, + i.e. applications will be loaded into RAM on the board, and this + ROM monitor may process exceptions or interrupts generated from the + application. This enables features such as utilizing a separate + interrupt stack when exceptions are generated." + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor booldata + legal_values { "Generic" } + default_value { 0 } + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "RAM" } + description " + Support can be enabled for different varieties of ROM monitor. + This support changes various eCos semantics such as the encoding + of diagnostic output, or the overriding of hardware interrupt + vectors. + Firstly there is \"Generic\" support which prevents the HAL + from overriding the hardware vectors that it does not use, to + instead allow an installed ROM monitor to handle them. This is + the most basic support which is likely to be common to most + implementations of ROM monitor. + \"GDB_stubs\" provides support when GDB stubs are included in + the ROM monitor or boot ROM." + } + + cdl_component CYGPKG_REDBOOT_HAL_OPTIONS { + display "Redboot HAL options" + flavor none + no_define + parent CYGPKG_REDBOOT + active_if CYGPKG_REDBOOT + description " + This option lists the target's requirements for a valid Redboot + configuration." + + cdl_option CYGBLD_BUILD_REDBOOT_BIN { + display "Build Redboot ROM binary image" + active_if CYGBLD_BUILD_REDBOOT + default_value 1 + no_define + description "This option enables the conversion of the Redboot ELF + image to a binary image suitable for ROM programming." + + make -priority 325 { + /bin/redboot.bin : /bin/redboot.elf + $(OBJCOPY) --strip-debug $< $(@:.bin=.img) + $(OBJCOPY) -O srec $< $(@:.bin=.srec) + $(OBJCOPY) -O binary $< $@ + } + + } + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + parent CYGPKG_NONE + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "zpu-elf" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { "-Wall -Wpointer-arith -Winline -Wundef -g -Os -ffunction-sections -fdata-sections -fno-exceptions -finit-priority -abel" } + description " + This option controls the global compiler flags which are used to + compile all packages by default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { "-Wl,--gc-sections -Wl,-static -g -nostdlib -abel -Wl,--relax -Os" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { (CYG_HAL_STARTUP == "RAM") ? "zpu_ram" : + (CYG_HAL_STARTUP == "ROMRAM") ? "zpu_romram" : + "zpu_rom" } + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { (CYG_HAL_STARTUP == "RAM") ? "" : + (CYG_HAL_STARTUP == "ROMRAM") ? "" : + "" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { (CYG_HAL_STARTUP == "RAM") ? "" : + (CYG_HAL_STARTUP == "ROMRAM") ? "" : + "" } + } + } +} diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/hal_platform_ints.h b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/hal_platform_ints.h new file mode 100644 index 0000000..9ff0029 --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/hal_platform_ints.h @@ -0,0 +1,79 @@ +#ifndef CYGONCE_HAL_PLATFORM_INTS_H +#define CYGONCE_HAL_PLATFORM_INTS_H +//========================================================================== +// +// hal_platform_ints.h +// +// HAL Interrupt and clock assignments for ZPU +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 2001-07-12 +// Purpose: Define Interrupt support +// Description: The interrupt specifics for the ZPU board/platform are +// defined here. +// +// Usage: #include +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#define CYGNUM_HAL_INTERRUPT_TIMER 0 + +#define CYGNUM_HAL_ISR_MIN 0 + +#define CYGNUM_HAL_ISR_MAX 0 + +#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX + 1) + +// The vector used by the Real time clock +#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER + + +//---------------------------------------------------------------------------- +// Reset. +__externC void hal_zpu_reset_cpu(void); +#define HAL_PLATFORM_RESET() hal_zpu_reset_cpu() + + + +#endif // CYGONCE_HAL_PLATFORM_INTS_H diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/pkgconf/mlt_zylin_zpu_abel_ram.h b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/pkgconf/mlt_zylin_zpu_abel_ram.h new file mode 100644 index 0000000..4d31221 --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/pkgconf/mlt_zylin_zpu_abel_ram.h @@ -0,0 +1,17 @@ +// eCos memory layout - Mon Jul 23 11:49:04 2001 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include +#include + +#endif +#define CYGMEM_REGION_ram (0x00000000) +#define CYGMEM_REGION_ram_SIZE (0x00008000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE ((CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE) - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/pkgconf/mlt_zylin_zpu_abel_ram.ldi b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/pkgconf/mlt_zylin_zpu_abel_ram.ldi new file mode 100644 index 0000000..9a50a17 --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/pkgconf/mlt_zylin_zpu_abel_ram.ldi @@ -0,0 +1,27 @@ +// eCos memory layout - Mon Jul 23 11:49:04 2001 + +// This is a generated file - do not edit + +#include + +MEMORY +{ + ram : ORIGIN = 0x00000000, LENGTH = 0x8000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_fixed_vectors (ram, 0x0, LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rom_vectors (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/plf_io.h b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/plf_io.h new file mode 100644 index 0000000..7e6a234 --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/plf_io.h @@ -0,0 +1,64 @@ +#ifndef CYGONCE_HAL_PLF_IO_H +#define CYGONCE_HAL_PLF_IO_H +//============================================================================= +// +// plf_io.h +// +// ZPU board specific registers +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): tkoeller +// Contributors: tdrury +// Date: 2002-06-22 +// Purpose: Zylin ZPU board specific registers +// Description: +// Usage: #include +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +/* cause an "interrupt" from the idle thread */ + +void _zpu_interrupt(void); +/* KLUDGE!!!! some linker problem with _zpu_interrupt() that I'll solve later */ +#define HAL_IDLE_THREAD_ACTION(_count_) ((void (*)())0x20)(); + +//----------------------------------------------------------------------------- +// end of plf_io.h +#endif // CYGONCE_HAL_PLF_IO_H diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/misc/redboot_RAM.ecm b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/misc/redboot_RAM.ecm new file mode 100644 index 0000000..04eae62 --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/misc/redboot_RAM.ecm @@ -0,0 +1,53 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware zpu_board ; + template redboot ; + package -hardware CYGPKG_HAL_ZPU current ; + package -hardware CYGPKG_HAL_ZPU_CPU current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; +}; + + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGOPT_REDBOOT_FIS { + user_value 0 +}; + +cdl_component CYGSEM_REDBOOT_FLASH_CONFIG { + user_value 0 +}; + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC { + user_value 0 +}; + diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/src/abel_misc.c b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/src/abel_misc.c new file mode 100644 index 0000000..ed5a0e9 --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/src/abel_misc.c @@ -0,0 +1,61 @@ +//========================================================================== +// +// zpu_misc.c +// +// HAL misc board support code for Zylin ZPU board +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2003 Nick Garnett +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas, jskov, tkoeller, tdrury, nickg +// Date: 2002-05-30 +// Purpose: HAL board support +// Description: Implementations of HAL board interfaces +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include + +#include // base types +#include // low level i/o +#include // common registers +#include // platform registers + + diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/ChangeLog b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/ChangeLog new file mode 100644 index 0000000..a29dbf8 --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/ChangeLog @@ -0,0 +1,39 @@ +2004-09-16 Øyvind Harboe + + * first cut HAL support for ZPU + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2003 Nick Garnett +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/cdl/hal_zylin_zpu_phi.cdl b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/cdl/hal_zylin_zpu_phi.cdl new file mode 100644 index 0000000..d7b7234 --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/cdl/hal_zylin_zpu_phi.cdl @@ -0,0 +1,292 @@ +# ==================================================================== +# +# hal_zpu.cdl +# +# ZPU HAL package configuration data +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): +# Contributors: +# Date: 2001-07-12 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_HAL_ZYLIN_ZPU_PHI { + display "Zylin ZPU HAL" + parent CYGPKG_HAL_ZYLIN_ZPU + define_header hal_zylin_zpu_phi.h + include_dir cyg/hal + hardware + description " + The Zylin ZPU HAL package provides the support needed to run + eCos on an Zylin ZPU board." + + compile phi_misc.c + + requires { CYGHWR_HAL_ZYLIN_ZPU == "ZPU1" } + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H " + puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H " + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H " + puts $::cdl_header "#define HAL_PLATFORM_CPU \"ZPU1\"" + puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Zylin Phi\"" + puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" + } + + # Real-time clock/counter specifics + cdl_option CYGNUM_HAL_ZYLIN_ZPU_CLOCK_SPEED { + display "CPU clock speed" + flavor data + default_value 64000000 + } + + cdl_component CYGNUM_HAL_RTC_CONSTANTS { + display "Real-time clock constants" + flavor none + + cdl_option CYGNUM_HAL_RTC_NUMERATOR { + display "Real-time clock numerator" + flavor data + default_value 1000000000 + } + cdl_option CYGNUM_HAL_RTC_DENOMINATOR { + display "Real-time clock denominator" + flavor data + default_value 100 + description "How many times a second to invoke the timer interrupt, normally 100" + } + cdl_option CYGNUM_HAL_RTC_PERIOD { + display "Real-time clock period" + flavor data + default_value (CYGNUM_HAL_ZYLIN_ZPU_CLOCK_SPEED / CYGNUM_HAL_RTC_DENOMINATOR) + } + } + + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + default_value {"RAM"} + legal_values {"RAM"} + no_define + define -file system.h CYG_HAL_STARTUP + description "For now the eCosBoard only supports DRAM startup" + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + calculated 1 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + This option + chooses which port will be used to connect to a host + running GDB." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + This option + chooses which port will be used for diagnostic output." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { + display "Diagnostic serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 38400 + description " + This option selects the baud rate used for the diagnostic port." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD { + display "GDB serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 38400 + description " + This option controls the baud rate used for the GDB connection." + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" } + description " + Enable this option if this program is to be used as a ROM monitor, + i.e. applications will be loaded into RAM on the board, and this + ROM monitor may process exceptions or interrupts generated from the + application. This enables features such as utilizing a separate + interrupt stack when exceptions are generated." + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor booldata + legal_values { "Generic" } + default_value { 0 } + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "RAM" } + description " + Support can be enabled for different varieties of ROM monitor. + This support changes various eCos semantics such as the encoding + of diagnostic output, or the overriding of hardware interrupt + vectors. + Firstly there is \"Generic\" support which prevents the HAL + from overriding the hardware vectors that it does not use, to + instead allow an installed ROM monitor to handle them. This is + the most basic support which is likely to be common to most + implementations of ROM monitor. + \"GDB_stubs\" provides support when GDB stubs are included in + the ROM monitor or boot ROM." + } + + cdl_component CYGPKG_REDBOOT_HAL_OPTIONS { + display "Redboot HAL options" + flavor none + no_define + parent CYGPKG_REDBOOT + active_if CYGPKG_REDBOOT + description " + This option lists the target's requirements for a valid Redboot + configuration." + + cdl_option CYGBLD_BUILD_REDBOOT_BIN { + display "Build Redboot ROM binary image" + active_if CYGBLD_BUILD_REDBOOT + default_value 1 + no_define + description "This option enables the conversion of the Redboot ELF + image to a binary image suitable for ROM programming." + + make -priority 325 { + /bin/redboot.bin : /bin/redboot.elf + $(OBJCOPY) --strip-debug $< $(@:.bin=.img) + $(OBJCOPY) -O srec $< $(@:.bin=.srec) + $(OBJCOPY) -O binary $< $@ + } + + } + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + parent CYGPKG_NONE + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "zpu-elf" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { "-Wall -Wpointer-arith -Winline -Wundef -g -Os -ffunction-sections -fdata-sections -fno-exceptions -phi" } + description " + This option controls the global compiler flags which are used to + compile all packages by default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { "-Wl,--gc-sections -Wl,-static -g -nostdlib -phi -Wl,--relax -Os" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { (CYG_HAL_STARTUP == "RAM") ? "zpu_ram" : + (CYG_HAL_STARTUP == "ROMRAM") ? "zpu_romram" : + "zpu_rom" } + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { (CYG_HAL_STARTUP == "RAM") ? "" : + (CYG_HAL_STARTUP == "ROMRAM") ? "" : + "" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { (CYG_HAL_STARTUP == "RAM") ? "" : + (CYG_HAL_STARTUP == "ROMRAM") ? "" : + "" } + } + } +} diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/hal_platform_ints.h b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/hal_platform_ints.h new file mode 100644 index 0000000..1ec0475 --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/hal_platform_ints.h @@ -0,0 +1,81 @@ +#ifndef CYGONCE_HAL_PLATFORM_INTS_H +#define CYGONCE_HAL_PLATFORM_INTS_H +//========================================================================== +// +// hal_platform_ints.h +// +// HAL Interrupt and clock assignments for ZPU +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 2001-07-12 +// Purpose: Define Interrupt support +// Description: The interrupt specifics for the ZPU board/platform are +// defined here. +// +// Usage: #include +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#define CYGNUM_HAL_INTERRUPT_TIMER 0 +#define CYGNUM_HAL_INTERRUPT_UART 1 +#define CYGNUM_HAL_INTERRUPT_ETHERMAC 2 + +#define CYGNUM_HAL_ISR_MIN 0 + +#define CYGNUM_HAL_ISR_MAX 2 + +#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX + 1) + +// The vector used by the Real time clock +#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER + + +//---------------------------------------------------------------------------- +// Reset. +__externC void hal_zpu_reset_cpu(void); +#define HAL_PLATFORM_RESET() hal_zpu_reset_cpu() + + + +#endif // CYGONCE_HAL_PLATFORM_INTS_H diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/pkgconf/mlt_zylin_zpu_phi_ram.h b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/pkgconf/mlt_zylin_zpu_phi_ram.h new file mode 100644 index 0000000..165467f --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/pkgconf/mlt_zylin_zpu_phi_ram.h @@ -0,0 +1,17 @@ +// eCos memory layout - Mon Jul 23 11:49:04 2001 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include +#include + +#endif +#define CYGMEM_REGION_ram (0x00000000) +#define CYGMEM_REGION_ram_SIZE (0x01ff0000) // 0x10000 as startup stack... +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE ((CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE) - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/pkgconf/mlt_zylin_zpu_phi_ram.ldi b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/pkgconf/mlt_zylin_zpu_phi_ram.ldi new file mode 100644 index 0000000..ef5947c --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/pkgconf/mlt_zylin_zpu_phi_ram.ldi @@ -0,0 +1,27 @@ +// eCos memory layout - Mon Jul 23 11:49:04 2001 + +// This is a generated file - do not edit + +#include + +MEMORY +{ + ram : ORIGIN = 0x00000000, LENGTH = 0x01ff0000 // 0x10000 as startup stack... +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_fixed_vectors (ram, 0x0, LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rom_vectors (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/plf_io.h b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/plf_io.h new file mode 100644 index 0000000..1c6f53b --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/plf_io.h @@ -0,0 +1,58 @@ +#ifndef CYGONCE_HAL_PLF_IO_H +#define CYGONCE_HAL_PLF_IO_H +//============================================================================= +// +// plf_io.h +// +// ZPU board specific registers +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): tkoeller +// Contributors: tdrury +// Date: 2002-06-22 +// Purpose: Zylin ZPU board specific registers +// Description: +// Usage: #include +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +//----------------------------------------------------------------------------- +// end of plf_io.h +#endif // CYGONCE_HAL_PLF_IO_H diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/src/phi_misc.c b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/src/phi_misc.c new file mode 100644 index 0000000..f7393f7 --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/src/phi_misc.c @@ -0,0 +1,72 @@ +//========================================================================== +// +// zpu_misc.c +// +// HAL misc board support code for Zylin ZPU board +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2003 Nick Garnett +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas, jskov, tkoeller, tdrury, nickg +// Date: 2002-05-30 +// Purpose: HAL board support +// Description: Implementations of HAL board interfaces +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include + +#include // base types +#include // low level i/o +#include // common registers +#include // platform registers + + +volatile int *INTERRUPT_MASK=(volatile int *)0x080a0020; + +volatile int *TIMER_PERIOD=(volatile int *)0x080a0034; +volatile int *TIMER_INTERRUPT=(volatile int *)0x080a0030; +volatile int *TIMER_ENABLE=(volatile int *)0x080a002c; +volatile int *TIMER_COUNTER=(volatile int *)0x080a0038; +volatile int *UART_INTERRUPT=(volatile int *)0x080a0028; +volatile int *UART_ENABLE=(volatile int *)0x080a0024; + + + diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/ChangeLog b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/ChangeLog new file mode 100644 index 0000000..519b620 --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/ChangeLog @@ -0,0 +1,38 @@ +2004-12-05 Øyvind Harboe + + * first cut ZPU HAL + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/cdl/hal_zylin_zpu.cdl b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/cdl/hal_zylin_zpu.cdl new file mode 100644 index 0000000..8d96088 --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/cdl/hal_zylin_zpu.cdl @@ -0,0 +1,83 @@ +# ==================================================================== +# +# hal_zpu.cdl +# +# Zylin ZPU HAL package configuration data +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## Copyright (C) 2003 Nick Garnett +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): gthomas +# Contributors: gthomas, tkoeller, tdrury, nickg +# Date: 2001-07-12 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_HAL_ZYLIN_ZPU { + display "Zylin ZPU variant HAL" + parent CYGPKG_HAL_ZYLIN + define_header hal_zylin_zpu.h + include_dir cyg/hal + hardware + description " + The ZPU HAL package provides the support needed to run + eCos on Zylin ZPU based targets." + + compile hal_diag.c zpu_misc.c + + + # Let the architectural HAL see this variant's files + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_ZPU_VAR_IO_H" + puts $::cdl_system_header "#define CYGBLD_HAL_ZPU_VAR_ARCH_H" + } + + cdl_option CYGHWR_HAL_ZYLIN_ZPU { + display "ZPU variant used" + flavor data + default_value {"ZPU1"} + legal_values {"ZPU1"} + description "The ZPU microcontroller family has several variants, + the main differences being the amount of on-chip SRAM, + peripherals and their layout. This option allows the + platform HALs to select the specific microcontroller + being used." + } + +} diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/hal_cache.h b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/hal_cache.h new file mode 100644 index 0000000..d3fef4f --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/hal_cache.h @@ -0,0 +1,192 @@ +#ifndef CYGONCE_HAL_CACHE_H +#define CYGONCE_HAL_CACHE_H + +//============================================================================= +// +// hal_cache.h +// +// HAL cache control API +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, gthomas +// Contributors: nickg, gthomas +// Date: 1998-09-28 +// Purpose: Cache control API +// Description: The macros defined here provide the HAL APIs for handling +// cache control operations. +// Usage: +// #include +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include + +//----------------------------------------------------------------------------- +// Cache dimensions + +// Data cache +//#define HAL_DCACHE_SIZE 0 // Size of data cache in bytes +//#define HAL_DCACHE_LINE_SIZE 0 // Size of a data cache line +//#define HAL_DCACHE_WAYS 0 // Associativity of the cache + +// Instruction cache +//#define HAL_ICACHE_SIZE 0 // Size of cache in bytes +//#define HAL_ICACHE_LINE_SIZE 0 // Size of a cache line +//#define HAL_ICACHE_WAYS 0 // Associativity of the cache + +//#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) +//#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) + +//----------------------------------------------------------------------------- +// Global control of data cache + +// Enable the data cache +#define HAL_DCACHE_ENABLE() + +// Disable the data cache +#define HAL_DCACHE_DISABLE() + +// Invalidate the entire cache +#define HAL_DCACHE_INVALIDATE_ALL() + +// Synchronize the contents of the cache with memory. +#define HAL_DCACHE_SYNC() + +// Purge contents of data cache +#define HAL_DCACHE_PURGE_ALL() + +// Query the state of the data cache (does not affect the caching) +#define HAL_DCACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + (_state_) = 0; \ + CYG_MACRO_END + +// Set the data cache refill burst size +//#define HAL_DCACHE_BURST_SIZE(_size_) + +// Set the data cache write mode +//#define HAL_DCACHE_WRITE_MODE( _mode_ ) + +//#define HAL_DCACHE_WRITETHRU_MODE 0 +//#define HAL_DCACHE_WRITEBACK_MODE 1 + +// Load the contents of the given address range into the data cache +// and then lock the cache so that it stays there. +//#define HAL_DCACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_DCACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +//#define HAL_DCACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Data cache line control + +// Allocate cache lines for the given address range without reading its +// contents from memory. +//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) + +// Write dirty cache lines to memory and invalidate the cache entries +// for the given address range. +//#define HAL_DCACHE_FLUSH( _base_ , _size_ ) + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) + +// Write dirty cache lines to memory for the given address range. +//#define HAL_DCACHE_STORE( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of reading +// from it later. +//#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of writing +// to it later. +//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) + +// Allocate and zero the cache lines associated with the given range. +//#define HAL_DCACHE_ZERO( _base_ , _size_ ) + +//----------------------------------------------------------------------------- +// Global control of Instruction cache + +// Enable the instruction cache +#define HAL_ICACHE_ENABLE() + +// Disable the instruction cache +#define HAL_ICACHE_DISABLE() + +// Invalidate the entire cache +#define HAL_ICACHE_INVALIDATE_ALL() + +// Synchronize the contents of the cache with memory. +#define HAL_ICACHE_SYNC() + +// Query the state of the instruction cache (does not affect the caching) +#define HAL_ICACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + (_state_) = 0; \ + CYG_MACRO_END + +// Set the instruction cache refill burst size +//#define HAL_ICACHE_BURST_SIZE(_size_) + +// Load the contents of the given address range into the instruction cache +// and then lock the cache so that it stays there. +//#define HAL_ICACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_ICACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +//#define HAL_ICACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Instruction cache line control + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_CACHE_H +// End of hal_cache.h diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/hal_diag.h b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/hal_diag.h new file mode 100644 index 0000000..3a9dba4 --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/hal_diag.h @@ -0,0 +1,90 @@ +#ifndef CYGONCE_HAL_DIAG_H +#define CYGONCE_HAL_DIAG_H + +//============================================================================= +// +// hal_diag.h +// +// HAL Support for Kernel Diagnostic Routines +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov, gthomas, tkoeller +// Date: 2001-07-12 +// Purpose: HAL Support for Kernel Diagnostic Routines +// Description: Diagnostic routines for use during kernel development. +// Usage: #include +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include + +#include + +#include + +externC void zpu_if_diag_init(void); +externC void zpu_if_diag_write_char(char c); +externC void zpu_if_diag_read_char(char *c); + +#define HAL_DIAG_INIT() zpu_if_diag_init() +#define HAL_DIAG_WRITE_CHAR(_c_) zpu_if_diag_write_char(_c_) +#define HAL_DIAG_READ_CHAR(_c_) zpu_if_diag_read_char(&_c_) + +//----------------------------------------------------------------------------- +// LED +externC void hal_diag_led(int mask); + +externC void hal_zpu_set_leds(int mask); + +//----------------------------------------------------------------------------- +// delay + +externC void hal_delay_us(cyg_int32 usecs); +#define HAL_DELAY_US(n) hal_delay_us(n); + +//----------------------------------------------------------------------------- +// reset + +extern void hal_zpu_reset_cpu(void); + +//----------------------------------------------------------------------------- +// end of hal_diag.h +#endif // CYGONCE_HAL_DIAG_H diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/plf_stub.h b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/plf_stub.h new file mode 100644 index 0000000..eb87958 --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/plf_stub.h @@ -0,0 +1,85 @@ +#ifndef CYGONCE_HAL_PLF_STUB_H +#define CYGONCE_HAL_PLF_STUB_H + +//============================================================================= +// +// plf_stub.h +// +// Platform header for GDB stub support. +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov, gthomas +// Date: 2001-07-12 +// Purpose: Platform HAL stub support for ZPU boards. +// Usage: #include +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include +#include CYGBLD_HAL_PLATFORM_H + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include // CYG_UNUSED_PARAM + + +//---------------------------------------------------------------------------- +// Define some platform specific communication details. This is mostly +// handled by hal_if now, but we need to make sure the comms tables are +// properly initialized. + +externC void cyg_hal_plf_comms_init(void); + +#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init() + +#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud)) +#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0 +#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT + +//---------------------------------------------------------------------------- +// Stub initializer. +#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT + +#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_PLF_STUB_H +// End of plf_stub.h diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/var_arch.h b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/var_arch.h new file mode 100644 index 0000000..293d7fc --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/var_arch.h @@ -0,0 +1,73 @@ +#ifndef CYGONCE_HAL_VAR_ARCH_H +#define CYGONCE_HAL_VAR_ARCH_H +//============================================================================= +// +// var_arch.h +// +// ZPU variant architecture overrides +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2003 Jonathan Larmour +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting the copyright +// holders. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jlarmour +// Contributors: Daniel Neri +// Date: 2003-06-24 +// Purpose: ZPU variant architecture overrides +// Description: +// Usage: #include +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include +#include + +//-------------------------------------------------------------------------- +// Idle thread code. +// This macro is called in the idle thread loop, and gives the HAL the +// chance to insert code. Typical idle thread behaviour might be to halt the +// processor. These implementations halt the system core clock. + +#ifndef HAL_IDLE_THREAD_ACTION +#define HAL_IDLE_THREAD_ACTION(_count_) \ +CYG_MACRO_START \ +CYG_MACRO_END +#endif + +//----------------------------------------------------------------------------- +// end of var_arch.h +#endif // CYGONCE_HAL_VAR_ARCH_H diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/var_io.h b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/var_io.h new file mode 100644 index 0000000..f1ef035 --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/var_io.h @@ -0,0 +1,73 @@ +#ifndef CYGONCE_HAL_VAR_IO_H +#define CYGONCE_HAL_VAR_IO_H +//============================================================================= +// +// var_io.h +// +// Variant specific registers +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2003 Nick Garnett +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov, gthomas, tkoeller, tdrury, nickg +// Date: 2001-07-12 +// Purpose: ZPU variant specific registers +// Description: +// Usage: #include +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include + + +extern volatile int *INTERRUPT_MASK; +extern volatile int *TIMER_PERIOD; +extern volatile int *TIMER_INTERRUPT; +extern volatile int *TIMER_ENABLE; +extern volatile int *TIMER_COUNTER; +extern volatile int *UART_INTERRUPT; +extern volatile int *UART_ENABLE; +void ethermac_enable(int enable); +int ethermac_interrupt(); +void ethermac_ack(); + +//----------------------------------------------------------------------------- +// end of var_io.h +#endif // CYGONCE_HAL_VAR_IO_H diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/src/hal_diag.c b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/src/hal_diag.c new file mode 100644 index 0000000..0b0f901 --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/src/hal_diag.c @@ -0,0 +1,88 @@ +/*============================================================================= +// +// hal_diag.c +// +// HAL diagnostic output code +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov, gthomas +// Date: 2001-07-12 +// Purpose: HAL diagnostic output +// Description: Implementations of HAL diagnostic output support. +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include +#include CYGBLD_HAL_PLATFORM_H + +#include // base types + +#include // SAVE/RESTORE GP macros +#include // IO macros +#include // interface API +#include // HAL_ENABLE/MASK/UNMASK_INTERRUPTS +#include // Helper functions +#include // CYG_ISR_HANDLED +#include + +#include // USART registers + +void zpu_if_diag_init(void) +{ +} + +extern void outbyte(int c); +extern int inbyte(); + +void +zpu_if_diag_write_char(char c) +{ + outbyte(c); +} + +void +zpu_if_diag_read_char(char *c) +{ + *c=inbyte(); +} + +//----------------------------------------------------------------------------- +// End of hal_diag.c diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/src/zpu_misc.c b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/src/zpu_misc.c new file mode 100644 index 0000000..019e024 --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/src/zpu_misc.c @@ -0,0 +1,252 @@ +/*========================================================================== +// +// zpu_misc.c +// +// HAL misc board support code for Zylin ZPU +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2003 Nick Garnett +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas, jskov, nickg, tkoeller +// Date: 2001-07-12 +// Purpose: HAL board support +// Description: Implementations of HAL board interfaces +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include + +#include // base types +#include // tracing macros +#include // assertion macros + +#include // IO macros +#include // Register state info +#include +#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT +#include // HAL ISR support +#endif +#include // necessary? + +#include +#include // calling interface +#include // helper functions +#include // platform registers + + + + + +// ------------------------------------------------------------------------- +// Clock support + +static cyg_uint32 _period; + + +void hal_clock_initialize(cyg_uint32 period) +{ + _period=period; + *TIMER_PERIOD=period; + *TIMER_INTERRUPT=0x2; // reset counter +} + +void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period) +{ + /* the next interrupt will happen without further action */ +} + + +long long _readCycles(); + +void hal_clock_read(cyg_uint32 *pvalue) +{ + *pvalue=_period-1-*TIMER_COUNTER; +} + +// ------------------------------------------------------------------------- +// +void hal_delay_us(cyg_int32 usecs) +{ + long long until=_readCycles(); + until+=((long long)usecs*(long long)(CYGNUM_HAL_ZYLIN_ZPU_CLOCK_SPEED))/(long long)1000000; + + /* waiting for the moment to pass.... */ + for (;;) + { + if (_readCycles()>until) + { + break; + } + } +} + +// ------------------------------------------------------------------------- +// Hardware init + +void hal_hardware_init(void) +{ + int i; + for (i=0; i= CYGNUM_HAL_ISR_MIN , "Invalid vector"); + + if (vector==CYGNUM_HAL_INTERRUPT_TIMER) + { + *TIMER_ENABLE=0; + } else if (vector==CYGNUM_HAL_INTERRUPT_UART) + { + *UART_ENABLE=0; + } +#ifdef CYGPKG_IO_ETH_DRIVERS + else if (vector==CYGNUM_HAL_INTERRUPT_ETHERMAC) + { + ethermac_enable(0); + } +#endif +} + +void hal_interrupt_unmask(int vector) +{ + CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX && + vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector"); + if (vector==CYGNUM_HAL_INTERRUPT_TIMER) + { + *TIMER_ENABLE=1; + } else if (vector==CYGNUM_HAL_INTERRUPT_UART) + { + *UART_ENABLE=1; + } +#ifdef CYGPKG_IO_ETH_DRIVERS + else if (vector==CYGNUM_HAL_INTERRUPT_ETHERMAC) + { + ethermac_enable(1); + } +#endif + +} + +void hal_interrupt_acknowledge(int vector) +{ + if (vector==CYGNUM_HAL_INTERRUPT_TIMER) + { + *TIMER_INTERRUPT=0x1; + } else if (vector==CYGNUM_HAL_INTERRUPT_UART) + { + *UART_INTERRUPT=0x1; + } +#ifdef CYGPKG_IO_ETH_DRIVERS + else if (vector==CYGNUM_HAL_INTERRUPT_ETHERMAC) + { + ethermac_ack(); + } +#endif + +} + +void hal_interrupt_configure(int vector, int level, int up) +{ + CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX && + vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector"); +} + +void hal_interrupt_set_level(int vector, int level) +{ + CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX && + vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector"); + CYG_ASSERT(level >= 0 && level <= 7, "Invalid level"); + +} + +void hal_show_IRQ(int vector, int data, int handler) +{ +} + + +/* Use the watchdog to generate a reset */ +void hal_zpu_reset_cpu(void) +{ +} + +/* nothing to do by default */ +cyg_uint32 +hal_default_isr(cyg_uint32 vector, CYG_ADDRWORD data) +{ + return 0; +} + +//-------------------------------------------------------------------------- +// EOF zpu_misc.c diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/ChangeLog b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/ChangeLog new file mode 100644 index 0000000..a29dbf8 --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/ChangeLog @@ -0,0 +1,39 @@ +2004-09-16 Øyvind Harboe + + * first cut HAL support for ZPU + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2003 Nick Garnett +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/cdl/hal_zylin_zpu_zeta.cdl b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/cdl/hal_zylin_zpu_zeta.cdl new file mode 100644 index 0000000..65a8d59 --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/cdl/hal_zylin_zpu_zeta.cdl @@ -0,0 +1,298 @@ +# ==================================================================== +# +# hal_zpu.cdl +# +# ZPU HAL package configuration data +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): +# Contributors: +# Date: 2001-07-12 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_HAL_ZYLIN_ZPU_ZETA { + display "Zylin ZPU HAL" + parent CYGPKG_HAL_ZYLIN_ZPU + define_header hal_zylin_zpu_zeta.h + include_dir cyg/hal + hardware + description " + The Zylin ZPU HAL package provides the support needed to run + eCos on an Zylin ZPU board." + + compile zeta_misc.c + + requires { CYGHWR_HAL_ZYLIN_ZPU == "ZPU1" } + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H " + puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H " + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H " + puts $::cdl_header "#define HAL_PLATFORM_CPU \"ZPU1\"" + puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Zylin Zeta\"" + puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" + } + + # Real-time clock/counter specifics + cdl_option CYGNUM_HAL_ZYLIN_ZPU_CLOCK_SPEED { + display "CPU clock speed" + flavor data + default_value 90000000 + } + + cdl_component CYGNUM_HAL_RTC_CONSTANTS { + display "Real-time clock constants" + flavor none + + cdl_option CYGNUM_HAL_RTC_NUMERATOR { + display "Real-time clock numerator" + flavor data + default_value 1000000000 + } + cdl_option CYGNUM_HAL_RTC_DENOMINATOR { + display "Real-time clock denominator" + flavor data + default_value 100 + } + cdl_option CYGNUM_HAL_RTC_PERIOD { + display "Real-time clock period" + flavor data + default_value (CYGNUM_HAL_ZYLIN_ZPU_CLOCK_SPEED / CYGNUM_HAL_RTC_DENOMINATOR) + } + } + + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + default_value {"RAM"} + legal_values {"RAM"} + no_define + define -file system.h CYG_HAL_STARTUP + description " + When targetting the ZPU board it is possible to build + the system for either RAM bootstrap or ROM bootstrap(s). Select + 'ram' when building programs to load into RAM using onboard + debug software such as Angel or eCos GDB stubs. Select 'rom' + when building a stand-alone application which will be put + into ROM. Using ROMRAM will allow the program to exist in + ROM, but be copied to RAM during startup." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + calculated 1 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + This option + chooses which port will be used to connect to a host + running GDB." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + This option + chooses which port will be used for diagnostic output." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { + display "Diagnostic serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 38400 + description " + This option selects the baud rate used for the diagnostic port." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD { + display "GDB serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 38400 + description " + This option controls the baud rate used for the GDB connection." + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" } + description " + Enable this option if this program is to be used as a ROM monitor, + i.e. applications will be loaded into RAM on the board, and this + ROM monitor may process exceptions or interrupts generated from the + application. This enables features such as utilizing a separate + interrupt stack when exceptions are generated." + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor booldata + legal_values { "Generic" } + default_value { 0 } + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "RAM" } + description " + Support can be enabled for different varieties of ROM monitor. + This support changes various eCos semantics such as the encoding + of diagnostic output, or the overriding of hardware interrupt + vectors. + Firstly there is \"Generic\" support which prevents the HAL + from overriding the hardware vectors that it does not use, to + instead allow an installed ROM monitor to handle them. This is + the most basic support which is likely to be common to most + implementations of ROM monitor. + \"GDB_stubs\" provides support when GDB stubs are included in + the ROM monitor or boot ROM." + } + + cdl_component CYGPKG_REDBOOT_HAL_OPTIONS { + display "Redboot HAL options" + flavor none + no_define + parent CYGPKG_REDBOOT + active_if CYGPKG_REDBOOT + description " + This option lists the target's requirements for a valid Redboot + configuration." + + cdl_option CYGBLD_BUILD_REDBOOT_BIN { + display "Build Redboot ROM binary image" + active_if CYGBLD_BUILD_REDBOOT + default_value 1 + no_define + description "This option enables the conversion of the Redboot ELF + image to a binary image suitable for ROM programming." + + make -priority 325 { + /bin/redboot.bin : /bin/redboot.elf + $(OBJCOPY) --strip-debug $< $(@:.bin=.img) + $(OBJCOPY) -O srec $< $(@:.bin=.srec) + $(OBJCOPY) -O binary $< $@ + } + + } + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + parent CYGPKG_NONE + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "zpu-elf" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { "-Wall -Wpointer-arith -Winline -Wundef -g -Os -ffunction-sections -fdata-sections -fno-exceptions -finit-priority -zeta" } + description " + This option controls the global compiler flags which are used to + compile all packages by default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { "-Wl,--gc-sections -Wl,-static -g -nostdlib -zeta -Wl,--relax -Os" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { (CYG_HAL_STARTUP == "RAM") ? "zpu_ram" : + (CYG_HAL_STARTUP == "ROMRAM") ? "zpu_romram" : + "zpu_rom" } + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { (CYG_HAL_STARTUP == "RAM") ? "" : + (CYG_HAL_STARTUP == "ROMRAM") ? "" : + "" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { (CYG_HAL_STARTUP == "RAM") ? "" : + (CYG_HAL_STARTUP == "ROMRAM") ? "" : + "" } + } + } +} diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/hal_platform_ints.h b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/hal_platform_ints.h new file mode 100644 index 0000000..9ff0029 --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/hal_platform_ints.h @@ -0,0 +1,79 @@ +#ifndef CYGONCE_HAL_PLATFORM_INTS_H +#define CYGONCE_HAL_PLATFORM_INTS_H +//========================================================================== +// +// hal_platform_ints.h +// +// HAL Interrupt and clock assignments for ZPU +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 2001-07-12 +// Purpose: Define Interrupt support +// Description: The interrupt specifics for the ZPU board/platform are +// defined here. +// +// Usage: #include +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#define CYGNUM_HAL_INTERRUPT_TIMER 0 + +#define CYGNUM_HAL_ISR_MIN 0 + +#define CYGNUM_HAL_ISR_MAX 0 + +#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX + 1) + +// The vector used by the Real time clock +#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER + + +//---------------------------------------------------------------------------- +// Reset. +__externC void hal_zpu_reset_cpu(void); +#define HAL_PLATFORM_RESET() hal_zpu_reset_cpu() + + + +#endif // CYGONCE_HAL_PLATFORM_INTS_H diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/pkgconf/mlt_zylin_zpu_zeta_ram.h b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/pkgconf/mlt_zylin_zpu_zeta_ram.h new file mode 100644 index 0000000..ddbaae8 --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/pkgconf/mlt_zylin_zpu_zeta_ram.h @@ -0,0 +1,17 @@ +// eCos memory layout - Mon Jul 23 11:49:04 2001 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include +#include + +#endif +#define CYGMEM_REGION_ram (0x10000000) +#define CYGMEM_REGION_ram_SIZE (0x00100000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE ((CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE) - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/pkgconf/mlt_zylin_zpu_zeta_ram.ldi b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/pkgconf/mlt_zylin_zpu_zeta_ram.ldi new file mode 100644 index 0000000..d9a14be --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/pkgconf/mlt_zylin_zpu_zeta_ram.ldi @@ -0,0 +1,27 @@ +// eCos memory layout - Mon Jul 23 11:49:04 2001 + +// This is a generated file - do not edit + +#include + +MEMORY +{ + ram : ORIGIN = 0x00000000, LENGTH = 0x100000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_fixed_vectors (ram, 0x0, LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rom_vectors (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/plf_io.h b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/plf_io.h new file mode 100644 index 0000000..1c6f53b --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/plf_io.h @@ -0,0 +1,58 @@ +#ifndef CYGONCE_HAL_PLF_IO_H +#define CYGONCE_HAL_PLF_IO_H +//============================================================================= +// +// plf_io.h +// +// ZPU board specific registers +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): tkoeller +// Contributors: tdrury +// Date: 2002-06-22 +// Purpose: Zylin ZPU board specific registers +// Description: +// Usage: #include +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +//----------------------------------------------------------------------------- +// end of plf_io.h +#endif // CYGONCE_HAL_PLF_IO_H diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/misc/redboot_RAM.ecm b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/misc/redboot_RAM.ecm new file mode 100644 index 0000000..04eae62 --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/misc/redboot_RAM.ecm @@ -0,0 +1,53 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware zpu_board ; + template redboot ; + package -hardware CYGPKG_HAL_ZPU current ; + package -hardware CYGPKG_HAL_ZPU_CPU current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; +}; + + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGOPT_REDBOOT_FIS { + user_value 0 +}; + +cdl_component CYGSEM_REDBOOT_FLASH_CONFIG { + user_value 0 +}; + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC { + user_value 0 +}; + diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/src/zeta_misc.c b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/src/zeta_misc.c new file mode 100644 index 0000000..b8b2e39 --- /dev/null +++ b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/src/zeta_misc.c @@ -0,0 +1,64 @@ +//========================================================================== +// +// zpu_misc.c +// +// HAL misc board support code for Zylin ZPU board +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2003 Nick Garnett +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas, jskov, tkoeller, tdrury, nickg +// Date: 2002-05-30 +// Purpose: HAL board support +// Description: Implementations of HAL board interfaces +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include + +#include // base types +#include // low level i/o +#include // common registers +#include // platform registers + + +void hal_zpu_set_leds(int leds) +{ +} diff --git a/zpu/sw/ecos/repository/net/zylin/current/cdl/phi_net.cdl b/zpu/sw/ecos/repository/net/zylin/current/cdl/phi_net.cdl new file mode 100644 index 0000000..d98bc96 --- /dev/null +++ b/zpu/sw/ecos/repository/net/zylin/current/cdl/phi_net.cdl @@ -0,0 +1,56 @@ +# ==================================================================== +# +# net.cdl +# +# Networking configuration data +# +# ==================================================================== +#####ECOSPDCOPYRIGHTBEGIN#### +# +# Copyright (C) 2000, 2001, 2002 Red Hat, Inc. +# All Rights Reserved. +# +# Permission is granted to use, copy, modify and redistribute this +# file. +# +#####ECOSPDCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): gthomas +# Original data: gthomas +# Contributors: +# Date: 1999-11-29 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_PHI_NET { + display "Basic networking framework" + doc nothing.html + include_dir . + requires CYGPKG_IO + requires CYGPKG_ISOINFRA + requires CYGINT_ISO_C_TIME_TYPES + requires CYGINT_ISO_STRERROR + requires CYGINT_ISO_ERRNO + requires CYGINT_ISO_ERRNO_CODES + requires CYGINT_ISO_MALLOC + requires CYGINT_ISO_STRING_BSD_FUNCS + requires CYGPKG_NET + description "Basic networking support, including TCP/IP." + + cdl_component CYGPKG_PHI_NET_INET { + display "INET support" + active_if CYGPKG_NET_STACK_INET + flavor bool + no_define + default_value 1 + description " + This option enables support for PHI INET (IP) network processing." + compile \ + phi_network_support.c + + } +} diff --git a/zpu/sw/ecos/repository/net/zylin/current/src/phi_network_support.c b/zpu/sw/ecos/repository/net/zylin/current/src/phi_network_support.c new file mode 100644 index 0000000..c297651 --- /dev/null +++ b/zpu/sw/ecos/repository/net/zylin/current/src/phi_network_support.c @@ -0,0 +1,368 @@ +//========================================================================== +// +// ph_network_support.c +// +// Misc network support functions +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2003 Andrew Lunn +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas, sorin@netappi.com ("Sorin Babeanu"), hmt, jlarmour, +// andrew.lunn@ascom.ch +// Date: 2000-01-10 +// Purpose: +// Description: +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +// BOOTP support + +#include +#undef _KERNEL +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include // for 'sprintf()' +#include // for strncpy and strtok_r +#include +#include +#include + +#ifdef CYGPKG_IO_PCMCIA +#include +#endif + +#ifdef CYGPKG_NET_DHCP +#include +#endif + +#ifdef CYGPKG_NS_DNS +#include +#endif + +#ifdef CYGHWR_NET_DRIVER_ETH0 +//struct bootp eth0_bootp_data; +//cyg_bool_t eth0_up = false; +//const char *eth0_name = "eth0"; +#endif +#ifdef CYGHWR_NET_DRIVER_ETH1 +struct bootp eth1_bootp_data; +//cyg_bool_t eth1_up = false; +//const char *eth1_name = "eth1"; +#endif + +#define _string(s) #s +#define string(s) _string(s) + +#ifndef CYGPKG_LIBC_STDIO +#define perror(s) diag_printf(#s ": %s\n", strerror(errno)) +#endif + + +static int hasIP(char *ip, char *mask, char *broadcast, char *gateway, char *server) +{ + int retVal = false; + int len = -1; + char buf[81]; + char *ptr1 = NULL; + char *token = NULL; + + if(ip == NULL) + return 0; + + //try to open ip file + int fd = open("/jffs2/ip", O_RDONLY); + if(fd < 0) + { + ip[0] = '\0'; + return 0; + } + //return ip address + if( (len = read(fd, buf, 80)) > 0) + { + buf[len] = '\0'; + //get IP + token = strtok_r(buf, "_", &ptr1); + if(token != NULL) + strncpy(ip, token, 15); + else + { + close(fd); + return 0; + } + //get MASK + token = strtok_r(NULL, "_", &ptr1); + if(token != NULL) + strncpy(mask, token, 15); + else + { + close(fd); + return 0; + } + //get broadcast + token = strtok_r(NULL, "_", &ptr1); + if(token != NULL) + strncpy(broadcast, token, 15); + else + { + close(fd); + return 0; + } + //get gateway + token = strtok_r(NULL, "_", &ptr1); + if(token != NULL) + strncpy(gateway, token, 15); + else + { + close(fd); + return 0; + } + //get server + token = strtok_r(NULL, "_", &ptr1); + if(token != NULL) + strncpy(server, token, 15); + else + { + close(fd); + return 0; + } + + retVal = 1; + } + else + { + retVal = 0; + ip[0] = '\0'; + } + return retVal; +} + +// +// Initialize network interface[s] using BOOTP/DHCP +// +void +phi_init_all_network_interfaces(void) +{ + static volatile int in_init_all_network_interfaces = 0; + +#ifdef CYGOPT_NET_IPV6_ROUTING_THREAD + int rs_wait = 40; +#endif + + cyg_scheduler_lock(); + while ( in_init_all_network_interfaces ) { + // Another thread is doing this... + cyg_scheduler_unlock(); + cyg_thread_delay( 10 ); + cyg_scheduler_lock(); + } + in_init_all_network_interfaces = 1; + cyg_scheduler_unlock(); + +#ifdef CYGHWR_NET_DRIVER_ETH0 + if ( ! eth0_up ) { // Make this call idempotent + char ip[16], mask[16], broadcast[16], gateway[16], server[16]; + if(!hasIP(ip, mask, broadcast, gateway, server)) + { + // Perform a complete initialization, using BOOTP/DHCP + eth0_up = true; + eth0_dhcpstate = 0; // Says that initialization is external to dhcp + if (do_dhcp(eth0_name, ð0_bootp_data, ð0_dhcpstate, ð0_lease)) +// { +// if (do_bootp(eth0_name, ð0_bootp_data)) + { + show_bootp(eth0_name, ð0_bootp_data); + } else { + diag_printf("BOOTP/DHCP failed on eth0\n"); + eth0_up = false; + } +// } + } + else + { + + eth0_up = true; + build_bootp_record(ð0_bootp_data, + eth0_name, + ip, + mask, + broadcast, + gateway, + server); + show_bootp(eth0_name, ð0_bootp_data); + } + } +#endif // CYGHWR_NET_DRIVER_ETH0 +#ifdef CYGHWR_NET_DRIVER_ETH1 + if ( ! eth1_up ) { // Make this call idempotent +#ifdef CYGHWR_NET_DRIVER_ETH1_BOOTP + // Perform a complete initialization, using BOOTP/DHCP + eth1_up = true; +#ifdef CYGHWR_NET_DRIVER_ETH1_DHCP + eth1_dhcpstate = 0; // Says that initialization is external to dhcp + if (do_dhcp(eth1_name, ð1_bootp_data, ð1_dhcpstate, ð1_lease)) +#else +#ifdef CYGPKG_NET_DHCP + eth1_dhcpstate = DHCPSTATE_BOOTP_FALLBACK; + // so the dhcp machine does no harm if called +#endif + if (do_bootp(eth1_name, ð1_bootp_data)) +#endif + { +#ifdef CYGHWR_NET_DRIVER_ETH1_BOOTP_SHOW + show_bootp(eth1_name, ð1_bootp_data); +#endif + } else { + diag_printf("BOOTP/DHCP failed on eth1\n"); + eth1_up = false; + } +#elif defined(CYGHWR_NET_DRIVER_ETH1_ADDRS_IP) + eth1_up = true; + build_bootp_record(ð1_bootp_data, + eth1_name, + string(CYGHWR_NET_DRIVER_ETH1_ADDRS_IP), + string(CYGHWR_NET_DRIVER_ETH1_ADDRS_NETMASK), + string(CYGHWR_NET_DRIVER_ETH1_ADDRS_BROADCAST), + string(CYGHWR_NET_DRIVER_ETH1_ADDRS_GATEWAY), + string(CYGHWR_NET_DRIVER_ETH1_ADDRS_SERVER)); + show_bootp(eth1_name, ð1_bootp_data); +#endif + } +#endif // CYGHWR_NET_DRIVER_ETH1 +#ifdef CYGHWR_NET_DRIVER_ETH0 +#ifndef CYGHWR_NET_DRIVER_ETH0_MANUAL + if (eth0_up) { + if (!init_net(eth0_name, ð0_bootp_data)) { + diag_printf("Network initialization failed for eth0\n"); + eth0_up = false; + } +#ifdef CYGHWR_NET_DRIVER_ETH0_IPV6_PREFIX + if (!init_net_IPv6(eth0_name, ð0_bootp_data, + string(CYGHWR_NET_DRIVER_ETH0_IPV6_PREFIX))) { + diag_printf("Static IPv6 network initialization failed for eth0\n"); + eth0_up = false; // ??? + } +#endif + } +#endif +#endif +#ifdef CYGHWR_NET_DRIVER_ETH1 +#ifndef CYGHWR_NET_DRIVER_ETH1_MANUAL + if (eth1_up) { + if (!init_net(eth1_name, ð1_bootp_data)) { + diag_printf("Network initialization failed for eth1\n"); + eth1_up = false; + } +#ifdef CYGHWR_NET_DRIVER_ETH1_IPV6_PREFIX + if (!init_net_IPv6(eth1_name, ð1_bootp_data, + string(CYGHWR_NET_DRIVER_ETH1_IPV6_PREFIX))) { + diag_printf("Static IPv6 network initialization failed for eth1\n"); + eth1_up = false; // ??? + } +#endif + } +#endif +#endif + +#ifdef CYGPKG_NET_NLOOP +#if 0 < CYGPKG_NET_NLOOP + { + static int loop_init = 0; + int i; + if ( 0 == loop_init++ ) + for ( i = 0; i < CYGPKG_NET_NLOOP; i++ ) + init_loopback_interface( i ); + } +#endif +#endif + +#ifdef CYGOPT_NET_DHCP_DHCP_THREAD + dhcp_start_dhcp_mgt_thread(); +#endif + +#ifdef CYGOPT_NET_IPV6_ROUTING_THREAD + ipv6_start_routing_thread(); + + // Wait for router solicit process to happen. + while (rs_wait-- && !cyg_net_get_ipv6_advrouter(NULL)) { + cyg_thread_delay(10); + } + if (rs_wait == 0 ) { + diag_printf("No router solicit received\n"); + } else { + // Give Duplicate Address Detection time to work + cyg_thread_delay(200); + } +#endif + +#ifdef CYGDAT_NS_DNS_DEFAULT_SERVER + cyg_dns_res_start(string(CYGDAT_NS_DNS_DEFAULT_SERVER)); +#endif + +#ifdef CYGDAT_NS_DNS_DOMAINNAME_NAME +#define _NAME string(CYGDAT_NS_DNS_DOMAINNAME_NAME) + { + const char buf[] = _NAME; + int len = strlen(_NAME); + + setdomainname(buf,len); + } +#endif + // Open the monitor to other threads. + in_init_all_network_interfaces = 0; + +} + +// EOF phi_network_support.c diff --git a/zpu/sw/ecos/repository/pkgconf/rules.mak b/zpu/sw/ecos/repository/pkgconf/rules.mak new file mode 100644 index 0000000..e043efa --- /dev/null +++ b/zpu/sw/ecos/repository/pkgconf/rules.mak @@ -0,0 +1,210 @@ +#============================================================================= +# +# rules.mak +# +# Generic rules for inclusion by all package makefiles. +# +#============================================================================= +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +#============================================================================= +#####DESCRIPTIONBEGIN#### +# +# Author(s): jld +# Contributors: bartv +# Date: 1999-11-04 +# Purpose: Generic rules for inclusion by all package makefiles +# Description: +# +#####DESCRIPTIONEND#### +#============================================================================= + +# FIXME: This definition belongs in the top-level makefile. +export HOST_CC := gcc + +.PHONY: default build clean tests headers mlt_headers + +# include any dependency rules generated previously +ifneq ($(wildcard *.deps),) +include $(wildcard *.deps) +endif + +# GCC since 2.95 does -finit-priority by default so remove it from old HALs +CFLAGS := $(subst -finit-priority,,$(CFLAGS)) + +# -fvtable-gc is known to be broken in all recent GCC. +CFLAGS := $(subst -fvtable-gc,,$(CFLAGS)) + +# To support more recent GCC whilst preserving existing behaviour, we need +# to increase the inlining limit globally from the default 600. Note this +# will break GCC 2.95 based tools and earlier. You must use "make OLDGCC=1" +# to avoid this. +ifneq ($(OLDGCC),1) +CFLAGS := -finline-limit=7000 $(CFLAGS) +endif + +# Separate C++ flags out from C flags. +ACTUAL_CFLAGS = $(CFLAGS) +ACTUAL_CFLAGS := $(subst -fno-rtti,,$(ACTUAL_CFLAGS)) +ACTUAL_CFLAGS := $(subst -frtti,,$(ACTUAL_CFLAGS)) +ACTUAL_CFLAGS := $(subst -Woverloaded-virtual,,$(ACTUAL_CFLAGS)) +ACTUAL_CFLAGS := $(subst -fvtable-gc,,$(ACTUAL_CFLAGS)) + +ACTUAL_CXXFLAGS = $(subst -Wstrict-prototypes,,$(CFLAGS)) + +# pattern matching rules to generate a library object from source code +# object filenames are prefixed to avoid name clashes +# a single dependency rule is generated (file extension = ".o.d") +%.o.d : %.c +ifeq ($(HOST),CYGWIN) + @mkdir -p `cygpath -w "$(dir $@)" | sed "s@\\\\\\\\@/@g"` +else + @mkdir -p $(dir $@) +endif + $(CC) -c $(INCLUDE_PATH) -I$(dir $<) $(ACTUAL_CFLAGS) -Wp,-MD,$(@:.o.d=.tmp) -o $(dir $@)$(OBJECT_PREFIX)_$(notdir $(@:.o.d=.o)) $< + @sed -e '/^ *\\/d' -e "s#.*: #$@: #" $(@:.o.d=.tmp) > $@ + @rm $(@:.o.d=.tmp) + +%.o.d : %.cxx +ifeq ($(HOST),CYGWIN) + @mkdir -p `cygpath -w "$(dir $@)" | sed "s@\\\\\\\\@/@g"` +else + @mkdir -p $(dir $@) +endif + $(CC) -c $(INCLUDE_PATH) -I$(dir $<) $(ACTUAL_CXXFLAGS) -Wp,-MD,$(@:.o.d=.tmp) -o $(dir $@)$(OBJECT_PREFIX)_$(notdir $(@:.o.d=.o)) $< + @sed -e '/^ *\\/d' -e "s#.*: #$@: #" $(@:.o.d=.tmp) > $@ + @rm $(@:.o.d=.tmp) + +%.o.d : %.cpp +ifeq ($(HOST),CYGWIN) + @mkdir -p `cygpath -w "$(dir $@)" | sed "s@\\\\\\\\@/@g"` +else + @mkdir -p $(dir $@) +endif + $(CC) -c $(INCLUDE_PATH) -I$(dir $<) $(ACTUAL_CXXFLAGS) -Wp,-MD,$(@:.o.d=.tmp) -o $(dir $@)$(OBJECT_PREFIX)_$(notdir $(@:.o.d=.o)) $< + @sed -e '/^ *\\/d' -e "s#.*: #$@: #" $(@:.o.d=.tmp) > $@ + @rm $(@:.o.d=.tmp) + +%.o.d : %.S +ifeq ($(HOST),CYGWIN) + @mkdir -p `cygpath -w "$(dir $@)" | sed "s@\\\\\\\\@/@g"` +else + @mkdir -p $(dir $@) +endif + $(CC) -c $(INCLUDE_PATH) -I$(dir $<) $(ACTUAL_CFLAGS) -Wp,-MD,$(@:.o.d=.tmp) -o $(dir $@)$(OBJECT_PREFIX)_$(notdir $(@:.o.d=.o)) $< + @sed -e '/^ *\\/d' -e "s#.*: #$@: #" $(@:.o.d=.tmp) > $@ + @rm $(@:.o.d=.tmp) + +# pattern matching rules to generate a test object from source code +# object filenames are not prefixed +# a single dependency rule is generated (file extension = ".d") +%.d : %.c +ifeq ($(HOST),CYGWIN) + @mkdir -p `cygpath -w "$(dir $@)" | sed "s@\\\\\\\\@/@g"` +else + @mkdir -p $(dir $@) +endif + $(CC) -c $(INCLUDE_PATH) -I$(dir $<) $(ACTUAL_CFLAGS) -Wp,-MD,$(@:.d=.tmp) -o $(@:.d=.o) $< + @sed -e '/^ *\\/d' -e "s#.*: #$@: #" $(@:.d=.tmp) > $@ + @rm $(@:.d=.tmp) + +%.d : %.cxx +ifeq ($(HOST),CYGWIN) + @mkdir -p `cygpath -w "$(dir $@)" | sed "s@\\\\\\\\@/@g"` +else + @mkdir -p $(dir $@) +endif + $(CC) -c $(INCLUDE_PATH) -I$(dir $<) $(ACTUAL_CXXFLAGS) -Wp,-MD,$(@:.d=.tmp) -o $(@:.d=.o) $< + @sed -e '/^ *\\/d' -e "s#.*: #$@: #" $(@:.d=.tmp) > $@ + @rm $(@:.d=.tmp) + +%.d : %.cpp +ifeq ($(HOST),CYGWIN) + @mkdir -p `cygpath -w "$(dir $@)" | sed "s@\\\\\\\\@/@g"` +else + @mkdir -p $(dir $@) +endif + $(CC) -c $(INCLUDE_PATH) -I$(dir $<) $(ACTUAL_CXXFLAGS) -Wp,-MD,$(@:.d=.tmp) -o $(@:.d=.o) $< + @sed -e '/^ *\\/d' -e "s#.*: #$@: #" $(@:.d=.tmp) > $@ + @rm $(@:.d=.tmp) + +%.d : %.S +ifeq ($(HOST),CYGWIN) + @mkdir -p `cygpath -w "$(dir $@)" | sed "s@\\\\\\\\@/@g"` +else + @mkdir -p $(dir $@) +endif + $(CC) -c $(INCLUDE_PATH) -I$(dir $<) $(ACTUAL_CFLAGS) -Wp,-MD,$(@:.d=.tmp) -o $(@:.d=.o) $< + @sed -e '/^ *\\/d' -e "s#.*: #$@: #" $(@:.d=.tmp) > $@ + @rm $(@:.d=.tmp) + +# rule to generate a test executable from object code +$(PREFIX)/tests/$(PACKAGE)/%$(EXEEXT): %.d $(wildcard $(PREFIX)/lib/target.ld) $(wildcard $(PREFIX)/lib/*.[ao]) +ifeq ($(HOST),CYGWIN) + @mkdir -p `cygpath -w "$(dir $@)" | sed "s@\\\\\\\\@/@g"` +else + @mkdir -p $(dir $@) +endif +ifneq ($(IGNORE_LINK_ERRORS),) + -$(CC) -L$(PREFIX)/lib -Ttarget.ld -o $@ $(<:.d=.o) $(LDFLAGS) +else + $(CC) -L$(PREFIX)/lib -Ttarget.ld -o $@ $(<:.d=.o) $(LDFLAGS) +endif + +# rule to generate all tests and create a dependency file "tests.deps" by +# concatenating the individual dependency rule files (file extension = ".d") +# generated during compilation +tests: tests.stamp + +TESTS := $(TESTS:.cpp=) +TESTS := $(TESTS:.cxx=) +TESTS := $(TESTS:.c=) +TESTS := $(TESTS:.S=) +tests.stamp: $(foreach target,$(TESTS),$(target).d $(PREFIX)/tests/$(PACKAGE)/$(target)$(EXEEXT)) +ifneq ($(strip $(TESTS)),) + @cat $(TESTS:%=%.d) > $(@:.stamp=.deps) +endif + @touch $@ + +# rule to clean the build tree +clean: + @find . -type f -print | grep -v makefile | xargs rm -f + +# rule to copy MLT files +mlt_headers: $(foreach x,$(MLT),$(PREFIX)/include/pkgconf/$(notdir $x)) + +$(foreach x,$(MLT),$(PREFIX)/include/pkgconf/$(notdir $x)): $(MLT) + @cp $(dir $<)/$(notdir $@) $(PREFIX)/include/pkgconf + @chmod u+w $(PREFIX)/include/pkgconf/$(notdir $@) + +# end of file -- cgit v1.1 From 3d2b8306640ae65aa9b48f70f50c3396324455be Mon Sep 17 00:00:00 2001 From: oharboe Date: Tue, 6 May 2008 06:00:31 +0000 Subject: forgot to commit log message. --- zpu/ChangeLog | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/zpu/ChangeLog b/zpu/ChangeLog index 8384d0d..7d881d9 100644 --- a/zpu/ChangeLog +++ b/zpu/ChangeLog @@ -4,6 +4,10 @@ 2008-05-04 Øyvind Harboe * moved ZPU core files to seperate folder * deleted some obsolete files +2008-05-04 jurij kostasenko + * Make code synthesize on Synopsis + zpu/hdl/zpu4/src/zpu_core_small.vhd + zpu/hdl/zpu4/src/io.vhd 2008-05-01 Øyvind Harboe * zpu/hdl/zy2000 - ZPU implementation used on the zy2000 dev kit 2008-04-17 Arnim Läuger -- cgit v1.1 From 6c7ee841131808466eb0c93e5c8f112771004fbf Mon Sep 17 00:00:00 2001 From: oharboe Date: Tue, 6 May 2008 06:39:21 +0000 Subject: * Small ZPU now supports interrupts * added simulation example demonstrating interrupts --- .settings/org.eclipse.core.resources.prefs | 3 - zpu/ChangeLog | 3 + zpu/docs/zpu_arch.html | 9 + zpu/hdl/example/bram_dmips.vhd | 3717 +++++++++++++++++++++++ zpu/hdl/example/interrupt.vhd | 3122 +++++++++++++++++++ zpu/hdl/example/log.txt | 58 +- zpu/hdl/example/sim_small_fpga_top.vhd | 19 +- zpu/hdl/example/simzpu_interrupt.do | 29 + zpu/hdl/example_medium/.cvsignore | 4 + zpu/hdl/example_medium/dram_dmips.vhd | 3308 ++++++++++++++++++++ zpu/hdl/example_medium/dram_hello.vhd | 3107 +++++++++++++++++++ zpu/hdl/example_medium/simzpu_medium.do | 14 +- zpu/hdl/example_medium/zpu_config_trace.vhd | 17 + zpu/hdl/index.html | 5 +- zpu/hdl/zpu4/core/zpu_core_small.vhd | 83 +- zpu/hdl/zpu4/core/zpu_core_small_wip.vhd | 498 --- zpu/hdl/zpu4/src/bram.vhd | 3807 ----------------------- zpu/hdl/zpu4/src/bram_dmips.vhd | 3717 ----------------------- zpu/hdl/zpu4/src/dram_dmips.vhd | 3308 -------------------- zpu/hdl/zpu4/src/dram_hello.vhd | 3107 ------------------- zpu/hdl/zpu4/src/zpu_config_trace.vhd | 17 - zpu/hdl/zpu4/test/interrupt/int.bin | Bin 12232 -> 12232 bytes zpu/hdl/zpu4/test/interrupt/int.c | 7 +- zpu/hdl/zpu4/test/interrupt/int.elf | Bin 150454 -> 150458 bytes zpu/hdl/zpu4/test/interrupt/int.ram | 4380 +++++++++++++-------------- 25 files changed, 15638 insertions(+), 16701 deletions(-) delete mode 100644 .settings/org.eclipse.core.resources.prefs create mode 100644 zpu/hdl/example/bram_dmips.vhd create mode 100644 zpu/hdl/example/interrupt.vhd create mode 100644 zpu/hdl/example/simzpu_interrupt.do create mode 100644 zpu/hdl/example_medium/.cvsignore create mode 100644 zpu/hdl/example_medium/dram_dmips.vhd create mode 100644 zpu/hdl/example_medium/dram_hello.vhd create mode 100644 zpu/hdl/example_medium/zpu_config_trace.vhd delete mode 100644 zpu/hdl/zpu4/core/zpu_core_small_wip.vhd delete mode 100644 zpu/hdl/zpu4/src/bram.vhd delete mode 100644 zpu/hdl/zpu4/src/bram_dmips.vhd delete mode 100644 zpu/hdl/zpu4/src/dram_dmips.vhd delete mode 100644 zpu/hdl/zpu4/src/dram_hello.vhd delete mode 100644 zpu/hdl/zpu4/src/zpu_config_trace.vhd diff --git a/.settings/org.eclipse.core.resources.prefs b/.settings/org.eclipse.core.resources.prefs deleted file mode 100644 index 197db03..0000000 --- a/.settings/org.eclipse.core.resources.prefs +++ /dev/null @@ -1,3 +0,0 @@ -#Sun May 04 22:37:24 CEST 2008 -eclipse.preferences.version=1 -encoding//zpu/hdl/zpu4/core/zpu_core_small_wip.vhd=UTF-8 diff --git a/zpu/ChangeLog b/zpu/ChangeLog index 7d881d9..e7bbb93 100644 --- a/zpu/ChangeLog +++ b/zpu/ChangeLog @@ -1,3 +1,6 @@ +2008-05-06 Øyvind Harboe + * Small ZPU now supports interrupts + * added simulation example demonstrating interrupts 2008-05-05 Øyvind Harboe * added eCos HAL for ZPU zpu/zpu/sw/ecos/repository diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index 8582afb..021e987 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -2,12 +2,18 @@

      Index

       + +

      Getting started

      +The ZPU comes with a few simulation examples. +

      +Start with VHDL synthesis examples

      Introduction

      The ZPU is a zero operand, or stack based CPU. The opcodes have a fixed width of 8 bits. @@ -802,5 +808,8 @@ rather uncommon operations. These 32 registers are mapped to memory locations 0x 0x4, 0x8, 0xc. The default interrupt vector at address 0x20 will load the value of these memory locations onto the stack, call _zpu_interrupt and restore them. +

      +See zpu/hdl/zpu4/test/interrupt/ for C code and zpu/hdl/example/simzpu_interrupt.do +for simulation example. \ No newline at end of file diff --git a/zpu/hdl/example/bram_dmips.vhd b/zpu/hdl/example/bram_dmips.vhd new file mode 100644 index 0000000..1d62d21 --- /dev/null +++ b/zpu/hdl/example/bram_dmips.vhd @@ -0,0 +1,3717 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity dualport_ram is +port (clk : in std_logic; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memAWrite : in std_logic_vector(wordSize-1 downto 0); + memARead : out std_logic_vector(wordSize-1 downto 0); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memBWrite : in std_logic_vector(wordSize-1 downto 0); + memBRead : out std_logic_vector(wordSize-1 downto 0)); +end dualport_ram; + +architecture dualport_ram_arch of dualport_ram is + + +type ram_type is array(natural range 0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); + +shared variable ram : ram_type := +( +0 => x"0b0b0b0b", +1 => x"80700b0b", +2 => x"80e2a40c", +3 => x"3a0b0b80", +4 => x"c6fc0400", +5 => x"00000000", +6 => x"00000000", +7 => x"00000000", +8 => x"80088408", +9 => x"88080b0b", +10 => x"80c7c32d", +11 => x"880c840c", +12 => x"800c0400", +13 => x"00000000", +14 => x"00000000", +15 => x"00000000", +16 => x"71fd0608", +17 => x"72830609", +18 => x"81058205", +19 => x"832b2a83", +20 => x"ffff0652", +21 => x"04000000", +22 => x"00000000", +23 => x"00000000", +24 => x"71fd0608", +25 => x"83ffff73", +26 => x"83060981", +27 => x"05820583", +28 => x"2b2b0906", +29 => x"7383ffff", +30 => x"0b0b0b0b", +31 => x"83a70400", +32 => x"72098105", +33 => x"72057373", +34 => x"09060906", +35 => x"73097306", +36 => x"070a8106", +37 => x"53510400", +38 => x"00000000", +39 => x"00000000", +40 => x"72722473", +41 => x"732e0753", +42 => x"51040000", +43 => x"00000000", +44 => x"00000000", +45 => x"00000000", +46 => x"00000000", +47 => x"00000000", +48 => x"71737109", +49 => x"71068106", +50 => x"30720a10", +51 => x"0a720a10", +52 => x"0a31050a", +53 => x"81065151", +54 => x"53510400", +55 => x"00000000", +56 => x"72722673", +57 => x"732e0753", +58 => x"51040000", +59 => x"00000000", +60 => x"00000000", +61 => x"00000000", +62 => x"00000000", +63 => x"00000000", +64 => x"00000000", +65 => x"00000000", +66 => x"00000000", +67 => x"00000000", +68 => x"00000000", +69 => x"00000000", +70 => x"00000000", +71 => x"00000000", +72 => x"0b0b0b88", +73 => x"c4040000", +74 => x"00000000", +75 => x"00000000", +76 => x"00000000", +77 => x"00000000", +78 => x"00000000", +79 => x"00000000", +80 => x"720a722b", +81 => x"0a535104", +82 => x"00000000", +83 => x"00000000", +84 => x"00000000", +85 => x"00000000", +86 => x"00000000", +87 => x"00000000", +88 => x"72729f06", +89 => x"0981050b", +90 => x"0b0b88a7", +91 => x"05040000", +92 => x"00000000", +93 => x"00000000", +94 => x"00000000", +95 => x"00000000", +96 => x"72722aff", +97 => x"739f062a", +98 => x"0974090a", +99 => x"8106ff05", +100 => x"06075351", +101 => x"04000000", +102 => x"00000000", +103 => x"00000000", +104 => x"71715351", +105 => x"020d0406", +106 => x"73830609", +107 => x"81058205", +108 => x"832b0b2b", +109 => x"0772fc06", +110 => x"0c515104", +111 => x"00000000", +112 => x"72098105", +113 => x"72050970", +114 => x"81050906", +115 => x"0a810653", +116 => x"51040000", +117 => x"00000000", +118 => x"00000000", +119 => x"00000000", +120 => x"72098105", +121 => x"72050970", +122 => x"81050906", +123 => x"0a098106", +124 => x"53510400", +125 => x"00000000", +126 => x"00000000", +127 => x"00000000", +128 => x"71098105", +129 => x"52040000", +130 => x"00000000", +131 => x"00000000", +132 => x"00000000", +133 => x"00000000", +134 => x"00000000", +135 => x"00000000", +136 => x"72720981", +137 => x"05055351", +138 => x"04000000", +139 => x"00000000", +140 => x"00000000", +141 => x"00000000", +142 => x"00000000", +143 => x"00000000", +144 => x"72097206", +145 => x"73730906", +146 => x"07535104", +147 => x"00000000", +148 => x"00000000", +149 => x"00000000", +150 => x"00000000", +151 => x"00000000", +152 => x"71fc0608", +153 => x"72830609", +154 => x"81058305", +155 => x"1010102a", +156 => x"81ff0652", +157 => x"04000000", +158 => x"00000000", +159 => x"00000000", +160 => x"71fc0608", +161 => x"0b0b80e2", +162 => x"90738306", +163 => x"10100508", +164 => x"060b0b0b", +165 => x"88aa0400", +166 => x"00000000", +167 => x"00000000", +168 => x"80088408", +169 => x"88087575", +170 => x"0b0b0baf", +171 => x"ac2d5050", +172 => x"80085688", +173 => x"0c840c80", +174 => x"0c510400", +175 => x"00000000", +176 => x"80088408", +177 => x"88087575", +178 => x"0b0b0baf", +179 => x"f02d5050", +180 => x"80085688", +181 => x"0c840c80", +182 => x"0c510400", +183 => x"00000000", +184 => x"72097081", +185 => x"0509060a", +186 => x"8106ff05", +187 => x"70547106", +188 => x"73097274", +189 => x"05ff0506", +190 => x"07515151", +191 => x"04000000", +192 => x"72097081", +193 => x"0509060a", +194 => x"098106ff", +195 => x"05705471", +196 => x"06730972", +197 => x"7405ff05", +198 => x"06075151", +199 => x"51040000", +200 => x"05ff0504", +201 => x"00000000", +202 => x"00000000", +203 => x"00000000", +204 => x"00000000", +205 => x"00000000", +206 => x"00000000", +207 => x"00000000", +208 => x"810b0b0b", +209 => x"80e2a00c", +210 => x"51040000", +211 => x"00000000", +212 => x"00000000", +213 => x"00000000", +214 => x"00000000", +215 => x"00000000", +216 => x"71810552", +217 => x"04000000", +218 => x"00000000", +219 => x"00000000", +220 => x"00000000", +221 => x"00000000", +222 => x"00000000", +223 => x"00000000", +224 => x"00000000", +225 => x"00000000", +226 => x"00000000", +227 => x"00000000", +228 => x"00000000", +229 => x"00000000", +230 => x"00000000", +231 => x"00000000", +232 => x"02840572", +233 => x"10100552", +234 => x"04000000", +235 => x"00000000", +236 => x"00000000", +237 => x"00000000", +238 => x"00000000", +239 => x"00000000", +240 => x"00000000", +241 => x"00000000", +242 => x"00000000", +243 => x"00000000", +244 => x"00000000", +245 => x"00000000", +246 => x"00000000", +247 => x"00000000", +248 => x"717105ff", +249 => x"05715351", +250 => x"020d0400", +251 => x"00000000", +252 => x"00000000", +253 => x"00000000", +254 => x"00000000", +255 => x"00000000", +256 => x"83d93f80", +257 => x"cbcf3f04", +258 => x"10101010", +259 => x"10101010", +260 => x"10101010", +261 => x"10101010", +262 => x"10101010", +263 => x"10101010", +264 => x"10101010", +265 => x"10101053", +266 => x"51047381", +267 => x"ff067383", +268 => x"06098105", +269 => x"83051010", +270 => x"102b0772", +271 => x"fc060c51", +272 => x"51043c04", +273 => x"72728072", +274 => x"8106ff05", +275 => x"09720605", +276 => x"71105272", +277 => x"0a100a53", +278 => x"72ed3851", +279 => x"51535104", +280 => x"ff3d0d0b", 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x"1234e66d", +3469 => x"deec0005", +3470 => x"000b0000", +3471 => x"00000000", +3472 => x"00000000", +3473 => x"00000000", +3474 => x"00000000", +3475 => x"00000000", +3476 => x"00000000", +3477 => x"00000000", +3478 => x"00000000", +3479 => x"00000000", +3480 => x"00000000", +3481 => x"00000000", +3482 => x"00000000", +3483 => x"00000000", +3484 => x"00000000", +3485 => x"00000000", +3486 => x"00000000", +3487 => x"00000000", +3488 => x"00000000", +3489 => x"00000000", +3490 => x"00000000", +3491 => x"00000000", +3492 => x"00000000", +3493 => x"00000000", +3494 => x"00000000", +3495 => x"00000000", +3496 => x"00000000", +3497 => x"00000000", +3498 => x"00000000", +3499 => x"00000000", +3500 => x"00000000", +3501 => x"00000000", +3502 => x"00000000", +3503 => x"00000000", +3504 => x"00000000", +3505 => x"00000000", +3506 => x"00000000", +3507 => x"00000000", +3508 => x"00000000", +3509 => x"00000000", +3510 => x"00000000", +3511 => x"00000000", +3512 => x"00000000", +3513 => x"00000000", +3514 => x"00000000", +3515 => x"00000000", +3516 => x"00000000", +3517 => x"00000000", +3518 => x"00000000", +3519 => x"00000000", +3520 => x"00000000", +3521 => x"00000000", +3522 => x"00000000", +3523 => x"00000000", +3524 => x"00000000", +3525 => x"00000000", +3526 => x"00000000", +3527 => x"00000000", +3528 => x"00000000", +3529 => x"00000000", +3530 => x"00000000", +3531 => x"00000000", +3532 => x"00000000", +3533 => x"00000000", +3534 => x"00000000", +3535 => x"00000000", +3536 => x"00000000", +3537 => x"00000000", +3538 => x"00000000", +3539 => x"00000000", +3540 => x"00000000", +3541 => x"00000000", +3542 => x"00000000", +3543 => x"00000000", +3544 => x"00000000", +3545 => x"00000000", +3546 => x"00000000", +3547 => x"00000000", +3548 => x"00000000", +3549 => x"00000000", +3550 => x"00000000", +3551 => x"00000000", +3552 => x"00000000", +3553 => x"00000000", +3554 => x"00000000", +3555 => x"00000000", +3556 => x"00000000", +3557 => x"00000000", +3558 => x"00000000", +3559 => x"00000000", +3560 => x"00000000", +3561 => x"00000000", +3562 => x"00000000", +3563 => x"00000000", +3564 => x"00000000", +3565 => x"00000000", +3566 => x"00000000", +3567 => x"00000000", +3568 => x"00000000", +3569 => x"00000000", +3570 => x"00000000", +3571 => x"00000000", +3572 => x"00000000", +3573 => x"00000000", +3574 => x"00000000", +3575 => x"00000000", +3576 => x"00000000", +3577 => x"00000000", +3578 => x"00000000", +3579 => x"00000000", +3580 => x"00000000", +3581 => x"00000000", +3582 => x"00000000", +3583 => x"00000000", +3584 => x"00000000", +3585 => x"00000000", +3586 => x"00000000", +3587 => x"00000000", +3588 => x"00000000", +3589 => x"00000000", +3590 => x"00000000", +3591 => x"00000000", +3592 => x"00000000", +3593 => x"00000000", +3594 => x"00000000", +3595 => x"00000000", +3596 => x"00000000", +3597 => x"00000000", +3598 => x"00000000", +3599 => x"00000000", +3600 => x"00000000", +3601 => x"00000000", +3602 => x"00000000", +3603 => x"00000000", +3604 => x"00000000", +3605 => x"00000000", +3606 => x"00000000", +3607 => x"00000000", +3608 => x"00000000", +3609 => x"00000000", +3610 => x"00000000", +3611 => x"00000000", +3612 => x"00000000", +3613 => x"00000000", +3614 => x"00000000", +3615 => x"00000000", +3616 => x"00000000", +3617 => x"00000000", +3618 => x"00000000", +3619 => x"00000000", +3620 => x"00000000", +3621 => x"00000000", +3622 => x"00000000", +3623 => x"00000000", +3624 => x"00000000", +3625 => x"00000000", +3626 => x"00000000", +3627 => x"00000000", +3628 => x"00000000", +3629 => x"00000000", +3630 => x"00000000", +3631 => x"00000000", +3632 => x"00000000", +3633 => x"00000000", +3634 => x"00000000", +3635 => x"00000000", +3636 => x"00000000", +3637 => x"00000000", +3638 => x"00000000", +3639 => x"00000000", +3640 => x"00000000", +3641 => x"00000000", +3642 => x"00000000", +3643 => x"00000000", +3644 => x"00000000", +3645 => x"00000000", +3646 => x"00000000", +3647 => x"00003104", +3648 => x"ffffffff", +3649 => x"00000000", +3650 => x"ffffffff", +3651 => x"00000000", + others => x"00000000" +); + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then + report "write collision" severity failure; + end if; + + if (memAWriteEnable = '1') then + ram(to_integer(unsigned(memAAddr))) := memAWrite; + memARead <= memAWrite; + else + memARead <= ram(to_integer(unsigned(memAAddr))); + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (memBWriteEnable = '1') then + ram(to_integer(unsigned(memBAddr))) := memBWrite; + memBRead <= memBWrite; + else + memBRead <= ram(to_integer(unsigned(memBAddr))); + end if; + end if; +end process; + + + + +end dualport_ram_arch; diff --git a/zpu/hdl/example/interrupt.vhd b/zpu/hdl/example/interrupt.vhd new file mode 100644 index 0000000..821e29a --- /dev/null +++ b/zpu/hdl/example/interrupt.vhd @@ -0,0 +1,3122 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity dualport_ram is +port (clk : in std_logic; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memAWrite : in std_logic_vector(wordSize-1 downto 0); + memARead : out std_logic_vector(wordSize-1 downto 0); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memBWrite : in std_logic_vector(wordSize-1 downto 0); + memBRead : out std_logic_vector(wordSize-1 downto 0)); +end dualport_ram; + +architecture dualport_ram_arch of dualport_ram is + + +type ram_type is array(natural range 0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); + +shared variable ram : ram_type := +( +0 => x"0b0b0b0b", +1 => x"82700b0b", +2 => x"80cfe00c", +3 => x"3a0b0b80", +4 => x"c6e00400", +5 => x"00000000", +6 => x"00000000", +7 => x"00000000", +8 => x"80088408", +9 => x"88080b0b", +10 => x"0b8af02d", +11 => x"880c840c", +12 => x"800c0400", +13 => x"00000000", +14 => x"00000000", +15 => x"00000000", +16 => x"71fd0608", +17 => x"72830609", +18 => x"81058205", +19 => x"832b2a83", +20 => x"ffff0652", +21 => x"04000000", +22 => x"00000000", +23 => x"00000000", +24 => x"71fd0608", +25 => x"83ffff73", +26 => x"83060981", +27 => x"05820583", +28 => x"2b2b0906", +29 => x"7383ffff", +30 => x"0b0b0b0b", +31 => x"83a70400", +32 => x"72098105", +33 => x"72057373", +34 => x"09060906", +35 => x"73097306", +36 => x"070a8106", +37 => x"53510400", +38 => x"00000000", +39 => x"00000000", +40 => x"72722473", +41 => x"732e0753", +42 => x"51040000", +43 => x"00000000", +44 => x"00000000", +45 => x"00000000", +46 => x"00000000", +47 => x"00000000", +48 => x"71737109", +49 => x"71068106", +50 => x"30720a10", +51 => x"0a720a10", +52 => x"0a31050a", +53 => x"81065151", +54 => x"53510400", +55 => x"00000000", +56 => x"72722673", +57 => x"732e0753", +58 => x"51040000", +59 => x"00000000", +60 => x"00000000", +61 => x"00000000", +62 => x"00000000", +63 => x"00000000", +64 => x"00000000", +65 => x"00000000", +66 => x"00000000", +67 => x"00000000", +68 => x"00000000", +69 => x"00000000", +70 => x"00000000", +71 => x"00000000", +72 => x"0b0b0b88", +73 => x"c4040000", +74 => x"00000000", +75 => x"00000000", +76 => x"00000000", +77 => x"00000000", +78 => x"00000000", +79 => x"00000000", +80 => x"720a722b", +81 => x"0a535104", +82 => x"00000000", +83 => x"00000000", +84 => x"00000000", +85 => x"00000000", +86 => x"00000000", +87 => x"00000000", +88 => x"72729f06", +89 => x"0981050b", +90 => x"0b0b88a7", +91 => x"05040000", +92 => x"00000000", +93 => x"00000000", +94 => x"00000000", +95 => x"00000000", +96 => x"72722aff", +97 => x"739f062a", +98 => x"0974090a", +99 => x"8106ff05", +100 => x"06075351", +101 => x"04000000", +102 => x"00000000", +103 => x"00000000", +104 => x"71715351", +105 => x"020d0406", +106 => x"73830609", +107 => x"81058205", +108 => x"832b0b2b", +109 => x"0772fc06", +110 => x"0c515104", +111 => x"00000000", +112 => x"72098105", +113 => x"72050970", +114 => x"81050906", +115 => x"0a810653", +116 => x"51040000", +117 => x"00000000", +118 => x"00000000", +119 => x"00000000", +120 => x"72098105", +121 => x"72050970", +122 => x"81050906", +123 => x"0a098106", +124 => x"53510400", +125 => x"00000000", +126 => x"00000000", +127 => x"00000000", +128 => x"71098105", +129 => x"52040000", +130 => x"00000000", +131 => x"00000000", +132 => x"00000000", +133 => x"00000000", +134 => x"00000000", +135 => x"00000000", +136 => x"72720981", +137 => x"05055351", +138 => x"04000000", +139 => x"00000000", +140 => x"00000000", +141 => x"00000000", +142 => x"00000000", +143 => x"00000000", +144 => x"72097206", +145 => x"73730906", +146 => x"07535104", +147 => x"00000000", +148 => x"00000000", +149 => x"00000000", +150 => x"00000000", +151 => x"00000000", +152 => x"71fc0608", +153 => x"72830609", +154 => x"81058305", +155 => x"1010102a", +156 => x"81ff0652", +157 => x"04000000", +158 => x"00000000", +159 => x"00000000", +160 => x"71fc0608", +161 => x"0b0b80cf", +162 => x"cc738306", +163 => x"10100508", +164 => x"060b0b0b", +165 => x"88aa0400", +166 => x"00000000", +167 => x"00000000", +168 => x"80088408", +169 => x"88087575", +170 => x"0b0b0b8b", +171 => x"ab2d5050", +172 => x"80085688", +173 => x"0c840c80", +174 => x"0c510400", +175 => x"00000000", +176 => x"80088408", +177 => x"88087575", +178 => x"0b0b0b8b", +179 => x"ef2d5050", +180 => x"80085688", +181 => x"0c840c80", +182 => x"0c510400", +183 => x"00000000", +184 => x"72097081", +185 => x"0509060a", +186 => x"8106ff05", +187 => x"70547106", +188 => x"73097274", +189 => x"05ff0506", +190 => x"07515151", +191 => x"04000000", +192 => x"72097081", +193 => x"0509060a", +194 => x"098106ff", +195 => x"05705471", +196 => x"06730972", +197 => x"7405ff05", +198 => x"06075151", +199 => x"51040000", +200 => x"05ff0504", +201 => x"00000000", +202 => x"00000000", +203 => x"00000000", +204 => x"00000000", +205 => x"00000000", +206 => x"00000000", +207 => x"00000000", +208 => x"810b0b0b", +209 => x"80cfdc0c", +210 => x"51040000", +211 => x"00000000", +212 => x"00000000", +213 => x"00000000", +214 => x"00000000", +215 => x"00000000", +216 => x"71810552", +217 => x"04000000", +218 => x"00000000", +219 => x"00000000", +220 => x"00000000", +221 => x"00000000", +222 => x"00000000", +223 => x"00000000", +224 => x"00000000", +225 => x"00000000", +226 => x"00000000", +227 => x"00000000", +228 => x"00000000", +229 => x"00000000", +230 => x"00000000", +231 => x"00000000", +232 => x"02840572", +233 => x"10100552", +234 => x"04000000", +235 => x"00000000", +236 => x"00000000", +237 => x"00000000", +238 => x"00000000", +239 => x"00000000", +240 => x"00000000", +241 => x"00000000", +242 => x"00000000", +243 => x"00000000", +244 => x"00000000", +245 => x"00000000", +246 => x"00000000", +247 => x"00000000", +248 => x"717105ff", +249 => x"05715351", +250 => x"020d0400", +251 => x"00000000", +252 => x"00000000", +253 => x"00000000", +254 => x"00000000", +255 => x"00000000", +256 => x"82c53f80", +257 => x"c6e63f04", +258 => x"10101010", +259 => x"10101010", +260 => x"10101010", +261 => x"10101010", +262 => x"10101010", +263 => x"10101010", +264 => x"10101010", +265 => x"10101053", +266 => x"51047381", +267 => x"ff067383", +268 => x"06098105", +269 => x"83051010", +270 => x"102b0772", +271 => x"fc060c51", +272 => x"51043c04", +273 => x"72728072", +274 => x"8106ff05", +275 => x"09720605", +276 => x"71105272", +277 => x"0a100a53", +278 => x"72ed3851", +279 => x"51535104", +280 => x"fe3d0d0b", +281 => x"0b80dfc8", +282 => x"08538413", +283 => x"0870882a", +284 => x"70810651", +285 => x"52527080", +286 => x"2ef03871", +287 => x"81ff0680", +288 => x"0c843d0d", +289 => x"04ff3d0d", +290 => x"0b0b80df", +291 => x"c8085271", +292 => x"0870882a", +293 => x"81327081", +294 => x"06515151", +295 => x"70f13873", +296 => x"720c833d", +297 => x"0d0480cf", +298 => x"dc08802e", +299 => x"a43880cf", +300 => x"e008822e", +301 => x"bd388380", +302 => x"800b0b0b", +303 => x"80dfc80c", +304 => x"82a0800b", +305 => x"80dfcc0c", +306 => x"8290800b", +307 => x"80dfd00c", +308 => x"04f88080", +309 => x"80a40b0b", +310 => x"0b80dfc8", +311 => x"0cf88080", +312 => x"82800b80", +313 => x"dfcc0cf8", +314 => x"80808480", +315 => x"0b80dfd0", +316 => x"0c0480c0", +317 => x"a8808c0b", +318 => x"0b0b80df", +319 => x"c80c80c0", +320 => x"a880940b", +321 => x"80dfcc0c", +322 => x"0b0b80cf", +323 => x"980b80df", +324 => x"d00c0470", +325 => x"7080dfd4", +326 => x"335170a7", +327 => x"3880cfe8", +328 => x"08700852", +329 => x"5270802e", +330 => x"94388412", +331 => x"80cfe80c", +332 => x"702d80cf", +333 => x"e8087008", +334 => x"525270ee", +335 => x"38810b80", +336 => x"dfd43450", +337 => x"50040470", +338 => x"0b0b80df", +339 => x"c408802e", +340 => x"8e380b0b", +341 => x"0b0b800b", +342 => x"802e0981", +343 => x"06833850", +344 => x"040b0b80", +345 => x"dfc4510b", +346 => x"0b0bf594", +347 => x"3f500404", +348 => x"803d0d80", +349 => x"dfe00881", +350 => x"1180dfe0", +351 => x"0c51823d", +352 => x"0d04fe3d", +353 => x"0d80dfe0", +354 => x"085380df", +355 => x"e0085272", +356 => x"722e8f38", +357 => x"80cf9c51", +358 => x"82b03f80", +359 => x"dfe00853", +360 => x"e93980cf", +361 => x"ac5182a2", +362 => x"3fe039fb", +363 => x"3d0d7779", +364 => x"55558056", +365 => x"757524ab", +366 => x"38807424", +367 => x"9d388053", +368 => x"73527451", +369 => x"80e13f80", +370 => x"08547580", +371 => x"2e853880", +372 => x"08305473", +373 => x"800c873d", +374 => x"0d047330", +375 => x"76813257", +376 => x"54dc3974", +377 => x"30558156", +378 => x"738025d2", +379 => x"38ec39fa", +380 => x"3d0d787a", +381 => x"57558057", +382 => x"767524a4", +383 => x"38759f2c", +384 => x"54815375", +385 => x"74327431", +386 => x"5274519b", +387 => x"3f800854", +388 => x"76802e85", +389 => x"38800830", +390 => x"5473800c", +391 => x"883d0d04", +392 => x"74305581", +393 => x"57d739fc", +394 => x"3d0d7678", +395 => x"53548153", +396 => x"80747326", +397 => x"52557280", +398 => x"2e983870", +399 => x"802eab38", +400 => x"807224a6", +401 => x"38711073", +402 => x"10757226", +403 => x"53545272", +404 => x"ea387351", +405 => x"78833874", +406 => x"5170800c", +407 => x"863d0d04", +408 => x"720a100a", +409 => x"720a100a", +410 => x"53537280", +411 => x"2ee43871", +412 => x"7426ed38", +413 => x"73723175", +414 => x"7407740a", +415 => x"100a740a", +416 => x"100a5555", +417 => x"5654e339", +418 => x"f73d0d7c", +419 => x"70525380", +420 => x"fd3f7254", +421 => x"8008550b", +422 => x"0b80cfb8", +423 => x"56815780", +424 => x"0881055a", +425 => x"8b3de411", +426 => x"59538259", +427 => x"f413527b", +428 => x"88110852", +429 => x"5381b43f", +430 => x"80083070", +431 => x"8008079f", +432 => x"2c8a0780", +433 => x"0c538b3d", +434 => x"0d04f63d", +435 => x"0d7c80cf", +436 => x"ec087153", +437 => x"5553b73f", +438 => x"72558008", +439 => x"560b0b80", +440 => x"cfb85781", +441 => x"58800881", +442 => x"055b8c3d", +443 => x"e4115a53", +444 => x"825af413", +445 => x"52881408", +446 => x"5180f03f", +447 => x"80083070", +448 => x"8008079f", +449 => x"2c8a0780", +450 => x"0c548c3d", +451 => x"0d047070", +452 => x"70707570", +453 => x"71830653", +454 => x"555270b4", +455 => x"38717008", +456 => x"7009f7fb", +457 => x"fdff1206", +458 => x"f8848281", +459 => x"80065452", +460 => x"53719b38", +461 => x"84137008", +462 => x"7009f7fb", +463 => x"fdff1206", +464 => x"f8848281", +465 => x"80065452", +466 => x"5371802e", +467 => x"e7387252", +468 => x"71335372", +469 => x"802e8a38", +470 => x"81127033", +471 => x"545272f8", +472 => x"38717431", +473 => x"800c5050", +474 => x"505004f2", +475 => x"3d0d6062", +476 => x"88110870", +477 => x"58565f5a", +478 => x"73802e81", +479 => x"8c388c1a", +480 => x"2270832a", +481 => x"81328106", +482 => x"56587486", +483 => x"38901a08", +484 => x"91387951", +485 => x"90b73fff", +486 => x"55800880", +487 => x"ec388c1a", +488 => x"22587d08", +489 => x"55807883", +490 => x"ffff0670", +491 => x"0a100a81", +492 => x"06415c57", +493 => x"7e772e80", +494 => x"d7387690", +495 => x"38740884", +496 => x"16088817", +497 => x"57585676", +498 => x"802ef238", +499 => x"76548880", +500 => x"77278438", +501 => x"88805473", +502 => x"5375529c", +503 => x"1a0851a4", +504 => x"1a085877", +505 => x"2d800b80", +506 => x"082582e0", +507 => x"38800816", +508 => x"77800831", +509 => x"7f880508", +510 => x"80083170", +511 => x"6188050c", +512 => x"5b585678", +513 => x"ffb43880", +514 => x"5574800c", +515 => x"903d0d04", +516 => x"7a813281", +517 => x"06774056", +518 => x"75802e81", +519 => x"bd387690", +520 => x"38740884", +521 => x"16088817", +522 => x"57585976", +523 => x"802ef238", +524 => x"881a0878", +525 => x"83ffff06", +526 => x"70892a81", +527 => x"06565956", +528 => x"73802e82", +529 => x"f8387577", +530 => x"278b3877", +531 => x"872a8106", +532 => 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x"38807424", +2493 => x"b5387382", +2494 => x"2b781188", +2495 => x"05565681", +2496 => x"80190877", +2497 => x"06537280", +2498 => x"2eb63878", +2499 => x"16700853", +2500 => x"53795174", +2501 => x"0853722d", +2502 => x"ff14fc17", +2503 => x"fc177981", +2504 => x"2c5a5757", +2505 => x"54738025", +2506 => x"d6387708", +2507 => x"5877ffad", +2508 => x"3880cfec", +2509 => x"0853bc13", +2510 => x"08a53879", +2511 => x"51f8e53f", +2512 => x"74085372", +2513 => x"2dff14fc", +2514 => x"17fc1779", +2515 => x"812c5a57", +2516 => x"57547380", +2517 => x"25ffa838", +2518 => x"d1398057", +2519 => x"ff933972", +2520 => x"51bc1308", +2521 => x"54732d79", +2522 => x"51f8b93f", +2523 => x"707080df", +2524 => x"b80bfc05", +2525 => x"70085252", +2526 => x"70ff2e91", +2527 => x"38702dfc", +2528 => x"12700852", +2529 => x"5270ff2e", +2530 => x"098106f1", +2531 => x"38505004", +2532 => x"04ffbaff", +2533 => x"3f040000", +2534 => x"00000040", +2535 => x"476f7420", +2536 => x"696e7465", +2537 => x"72727570", +2538 => x"740a0000", +2539 => x"4e6f2069", +2540 => x"6e746572", +2541 => x"72757074", +2542 => x"0a000000", +2543 => x"43000000", +2544 => x"64756d6d", +2545 => x"792e6578", +2546 => x"65000000", +2547 => x"00ffffff", +2548 => x"ff00ffff", +2549 => x"ffff00ff", +2550 => x"ffffff00", +2551 => x"00000000", +2552 => x"00000000", +2553 => x"00000000", +2554 => x"00002fc0", +2555 => x"000027f0", +2556 => x"00000000", +2557 => x"00002a58", +2558 => x"00002ab4", +2559 => x"00002b10", +2560 => x"00000000", +2561 => x"00000000", +2562 => x"00000000", +2563 => x"00000000", +2564 => x"00000000", +2565 => x"00000000", +2566 => x"00000000", +2567 => x"00000000", +2568 => x"00000000", +2569 => x"000027bc", +2570 => x"00000000", +2571 => x"00000000", +2572 => x"00000000", +2573 => x"00000000", +2574 => x"00000000", +2575 => x"00000000", +2576 => x"00000000", +2577 => x"00000000", +2578 => x"00000000", +2579 => x"00000000", +2580 => x"00000000", +2581 => x"00000000", +2582 => x"00000000", +2583 => x"00000000", +2584 => x"00000000", +2585 => x"00000000", +2586 => x"00000000", +2587 => x"00000000", +2588 => x"00000000", +2589 => x"00000000", +2590 => x"00000000", +2591 => x"00000000", +2592 => x"00000000", +2593 => x"00000000", +2594 => x"00000000", +2595 => x"00000000", +2596 => x"00000000", +2597 => x"00000000", +2598 => x"00000001", +2599 => x"330eabcd", +2600 => x"1234e66d", +2601 => x"deec0005", +2602 => x"000b0000", +2603 => x"00000000", +2604 => x"00000000", +2605 => x"00000000", +2606 => x"00000000", +2607 => x"00000000", +2608 => x"00000000", +2609 => x"00000000", +2610 => x"00000000", +2611 => x"00000000", +2612 => x"00000000", +2613 => x"00000000", +2614 => x"00000000", +2615 => x"00000000", +2616 => x"00000000", +2617 => x"00000000", +2618 => x"00000000", +2619 => x"00000000", +2620 => x"00000000", +2621 => x"00000000", +2622 => x"00000000", +2623 => x"00000000", +2624 => x"00000000", +2625 => x"00000000", +2626 => x"00000000", +2627 => x"00000000", +2628 => x"00000000", +2629 => x"00000000", +2630 => x"00000000", +2631 => x"00000000", +2632 => x"00000000", +2633 => x"00000000", +2634 => x"00000000", +2635 => x"00000000", +2636 => x"00000000", +2637 => x"00000000", +2638 => x"00000000", +2639 => x"00000000", +2640 => x"00000000", +2641 => x"00000000", +2642 => x"00000000", +2643 => x"00000000", +2644 => x"00000000", +2645 => x"00000000", +2646 => x"00000000", +2647 => x"00000000", +2648 => x"00000000", +2649 => x"00000000", +2650 => x"00000000", +2651 => x"00000000", +2652 => x"00000000", +2653 => x"00000000", +2654 => x"00000000", +2655 => x"00000000", +2656 => x"00000000", +2657 => x"00000000", +2658 => x"00000000", +2659 => x"00000000", +2660 => x"00000000", +2661 => x"00000000", +2662 => x"00000000", +2663 => x"00000000", +2664 => x"00000000", +2665 => x"00000000", +2666 => x"00000000", +2667 => x"00000000", +2668 => x"00000000", +2669 => x"00000000", +2670 => x"00000000", +2671 => x"00000000", +2672 => x"00000000", +2673 => x"00000000", +2674 => x"00000000", +2675 => x"00000000", +2676 => x"00000000", +2677 => x"00000000", +2678 => x"00000000", +2679 => x"00000000", +2680 => x"00000000", +2681 => x"00000000", +2682 => x"00000000", +2683 => x"00000000", +2684 => x"00000000", +2685 => x"00000000", +2686 => x"00000000", +2687 => x"00000000", +2688 => x"00000000", +2689 => x"00000000", +2690 => x"00000000", +2691 => x"00000000", +2692 => x"00000000", +2693 => x"00000000", +2694 => x"00000000", +2695 => x"00000000", +2696 => x"00000000", +2697 => x"00000000", +2698 => x"00000000", +2699 => x"00000000", +2700 => x"00000000", +2701 => x"00000000", +2702 => x"00000000", +2703 => x"00000000", +2704 => x"00000000", +2705 => x"00000000", +2706 => x"00000000", +2707 => x"00000000", +2708 => x"00000000", +2709 => x"00000000", +2710 => x"00000000", +2711 => x"00000000", +2712 => x"00000000", +2713 => x"00000000", +2714 => x"00000000", +2715 => x"00000000", +2716 => x"00000000", +2717 => x"00000000", +2718 => x"00000000", +2719 => x"00000000", +2720 => x"00000000", +2721 => x"00000000", +2722 => x"00000000", +2723 => x"00000000", +2724 => x"00000000", +2725 => x"00000000", +2726 => x"00000000", +2727 => x"00000000", +2728 => x"00000000", +2729 => x"00000000", +2730 => x"00000000", +2731 => x"00000000", +2732 => x"00000000", +2733 => x"00000000", +2734 => x"00000000", +2735 => x"00000000", +2736 => x"00000000", +2737 => x"00000000", +2738 => x"00000000", +2739 => x"00000000", +2740 => x"00000000", +2741 => x"00000000", +2742 => x"00000000", +2743 => x"00000000", +2744 => x"00000000", +2745 => x"00000000", +2746 => x"00000000", +2747 => x"00000000", +2748 => x"00000000", +2749 => x"00000000", +2750 => x"00000000", +2751 => x"00000000", +2752 => x"00000000", +2753 => x"00000000", +2754 => x"00000000", +2755 => x"00000000", +2756 => x"00000000", +2757 => x"00000000", +2758 => x"00000000", +2759 => x"00000000", +2760 => x"00000000", +2761 => x"00000000", +2762 => x"00000000", +2763 => x"00000000", +2764 => x"00000000", +2765 => x"00000000", +2766 => x"00000000", +2767 => x"00000000", +2768 => x"00000000", +2769 => x"00000000", +2770 => x"00000000", +2771 => x"00000000", +2772 => x"00000000", +2773 => x"00000000", +2774 => x"00000000", +2775 => x"00000000", +2776 => x"00000000", +2777 => x"00000000", +2778 => x"00000000", +2779 => x"00000000", +2780 => x"00000000", +2781 => x"00000000", +2782 => x"00000000", +2783 => x"00000000", +2784 => x"00000000", +2785 => x"00000000", +2786 => x"00000000", +2787 => x"00000000", +2788 => x"00000000", +2789 => x"00000000", +2790 => x"00000000", +2791 => x"ffffffff", +2792 => x"00000000", +2793 => x"00020000", +2794 => x"00000000", +2795 => x"00000000", +2796 => x"00002ba8", +2797 => x"00002ba8", +2798 => x"00002bb0", +2799 => x"00002bb0", +2800 => x"00002bb8", +2801 => x"00002bb8", +2802 => x"00002bc0", +2803 => x"00002bc0", +2804 => x"00002bc8", +2805 => x"00002bc8", +2806 => x"00002bd0", +2807 => x"00002bd0", +2808 => x"00002bd8", +2809 => x"00002bd8", +2810 => x"00002be0", +2811 => x"00002be0", +2812 => x"00002be8", +2813 => x"00002be8", +2814 => x"00002bf0", +2815 => x"00002bf0", +2816 => x"00002bf8", +2817 => x"00002bf8", +2818 => x"00002c00", +2819 => x"00002c00", +2820 => x"00002c08", +2821 => x"00002c08", +2822 => x"00002c10", +2823 => x"00002c10", +2824 => x"00002c18", +2825 => x"00002c18", +2826 => x"00002c20", +2827 => x"00002c20", +2828 => x"00002c28", +2829 => x"00002c28", +2830 => x"00002c30", +2831 => x"00002c30", +2832 => x"00002c38", +2833 => x"00002c38", +2834 => x"00002c40", +2835 => x"00002c40", +2836 => x"00002c48", +2837 => x"00002c48", +2838 => x"00002c50", +2839 => x"00002c50", +2840 => x"00002c58", +2841 => x"00002c58", +2842 => x"00002c60", +2843 => x"00002c60", +2844 => x"00002c68", +2845 => x"00002c68", +2846 => x"00002c70", +2847 => x"00002c70", +2848 => x"00002c78", +2849 => x"00002c78", +2850 => x"00002c80", +2851 => x"00002c80", +2852 => x"00002c88", +2853 => x"00002c88", +2854 => x"00002c90", +2855 => x"00002c90", +2856 => x"00002c98", +2857 => x"00002c98", +2858 => x"00002ca0", +2859 => x"00002ca0", +2860 => x"00002ca8", +2861 => x"00002ca8", +2862 => x"00002cb0", +2863 => x"00002cb0", +2864 => x"00002cb8", +2865 => x"00002cb8", +2866 => x"00002cc0", +2867 => x"00002cc0", +2868 => x"00002cc8", +2869 => x"00002cc8", +2870 => x"00002cd0", +2871 => x"00002cd0", +2872 => x"00002cd8", +2873 => x"00002cd8", +2874 => x"00002ce0", +2875 => x"00002ce0", +2876 => x"00002ce8", +2877 => x"00002ce8", +2878 => x"00002cf0", +2879 => x"00002cf0", +2880 => x"00002cf8", +2881 => x"00002cf8", +2882 => x"00002d00", +2883 => x"00002d00", +2884 => x"00002d08", +2885 => x"00002d08", +2886 => x"00002d10", +2887 => x"00002d10", +2888 => x"00002d18", +2889 => x"00002d18", +2890 => x"00002d20", +2891 => x"00002d20", +2892 => x"00002d28", +2893 => x"00002d28", +2894 => x"00002d30", +2895 => x"00002d30", +2896 => x"00002d38", +2897 => x"00002d38", +2898 => x"00002d40", +2899 => x"00002d40", +2900 => x"00002d48", +2901 => x"00002d48", +2902 => x"00002d50", +2903 => x"00002d50", +2904 => x"00002d58", +2905 => x"00002d58", +2906 => x"00002d60", +2907 => x"00002d60", +2908 => x"00002d68", +2909 => x"00002d68", +2910 => x"00002d70", +2911 => x"00002d70", +2912 => x"00002d78", +2913 => x"00002d78", +2914 => x"00002d80", +2915 => x"00002d80", +2916 => x"00002d88", +2917 => x"00002d88", +2918 => x"00002d90", +2919 => x"00002d90", +2920 => x"00002d98", +2921 => x"00002d98", +2922 => x"00002da0", +2923 => x"00002da0", +2924 => x"00002da8", +2925 => x"00002da8", +2926 => x"00002db0", +2927 => x"00002db0", +2928 => x"00002db8", +2929 => x"00002db8", +2930 => x"00002dc0", +2931 => x"00002dc0", +2932 => x"00002dc8", +2933 => x"00002dc8", +2934 => x"00002dd0", +2935 => x"00002dd0", +2936 => x"00002dd8", +2937 => x"00002dd8", +2938 => x"00002de0", +2939 => x"00002de0", +2940 => x"00002de8", +2941 => x"00002de8", +2942 => x"00002df0", +2943 => x"00002df0", +2944 => x"00002df8", +2945 => x"00002df8", +2946 => x"00002e00", +2947 => x"00002e00", +2948 => x"00002e08", +2949 => x"00002e08", +2950 => x"00002e10", +2951 => x"00002e10", +2952 => x"00002e18", +2953 => x"00002e18", +2954 => x"00002e20", +2955 => x"00002e20", +2956 => x"00002e28", +2957 => x"00002e28", +2958 => x"00002e30", +2959 => x"00002e30", +2960 => x"00002e38", +2961 => x"00002e38", +2962 => x"00002e40", +2963 => x"00002e40", +2964 => x"00002e48", +2965 => x"00002e48", +2966 => x"00002e50", +2967 => x"00002e50", +2968 => x"00002e58", +2969 => x"00002e58", +2970 => x"00002e60", +2971 => x"00002e60", +2972 => x"00002e68", +2973 => x"00002e68", +2974 => x"00002e70", +2975 => x"00002e70", +2976 => x"00002e78", +2977 => x"00002e78", +2978 => x"00002e80", +2979 => x"00002e80", +2980 => x"00002e88", +2981 => x"00002e88", +2982 => x"00002e90", +2983 => x"00002e90", +2984 => x"00002e98", +2985 => x"00002e98", +2986 => x"00002ea0", +2987 => x"00002ea0", +2988 => x"00002ea8", +2989 => x"00002ea8", +2990 => x"00002eb0", +2991 => x"00002eb0", +2992 => x"00002eb8", +2993 => x"00002eb8", +2994 => x"00002ec0", +2995 => x"00002ec0", +2996 => x"00002ec8", +2997 => x"00002ec8", +2998 => x"00002ed0", +2999 => x"00002ed0", +3000 => x"00002ed8", +3001 => x"00002ed8", +3002 => x"00002ee0", +3003 => x"00002ee0", +3004 => x"00002ee8", +3005 => x"00002ee8", +3006 => x"00002ef0", +3007 => x"00002ef0", +3008 => x"00002ef8", +3009 => x"00002ef8", +3010 => x"00002f00", +3011 => x"00002f00", +3012 => x"00002f08", +3013 => x"00002f08", +3014 => x"00002f10", +3015 => x"00002f10", +3016 => x"00002f18", +3017 => x"00002f18", +3018 => x"00002f20", +3019 => x"00002f20", +3020 => x"00002f28", +3021 => x"00002f28", +3022 => x"00002f30", +3023 => x"00002f30", +3024 => x"00002f38", +3025 => x"00002f38", +3026 => x"00002f40", +3027 => x"00002f40", +3028 => x"00002f48", +3029 => x"00002f48", +3030 => x"00002f50", +3031 => x"00002f50", +3032 => x"00002f58", +3033 => x"00002f58", +3034 => x"00002f60", +3035 => x"00002f60", +3036 => x"00002f68", +3037 => x"00002f68", +3038 => x"00002f70", +3039 => x"00002f70", +3040 => x"00002f78", +3041 => x"00002f78", +3042 => x"00002f80", +3043 => x"00002f80", +3044 => x"00002f88", +3045 => x"00002f88", +3046 => x"00002f90", +3047 => x"00002f90", +3048 => x"00002f98", +3049 => x"00002f98", +3050 => x"00002fa0", +3051 => x"00002fa0", +3052 => x"000027c0", +3053 => x"ffffffff", +3054 => x"00000000", +3055 => x"ffffffff", +3056 => x"00000000", + others => x"00000000" +); + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then + report "write collision" severity failure; + end if; + + if (memAWriteEnable = '1') then + ram(to_integer(unsigned(memAAddr))) := memAWrite; + memARead <= memAWrite; + else + memARead <= ram(to_integer(unsigned(memAAddr))); + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (memBWriteEnable = '1') then + ram(to_integer(unsigned(memBAddr))) := memBWrite; + memBRead <= memBWrite; + else + memBRead <= ram(to_integer(unsigned(memBAddr))); + end if; + end if; +end process; + + + + +end dualport_ram_arch; diff --git a/zpu/hdl/example/log.txt b/zpu/hdl/example/log.txt index 6966062..a8b4893 100644 --- a/zpu/hdl/example/log.txt +++ b/zpu/hdl/example/log.txt @@ -1,35 +1,55 @@ -H -e -l -l +N o -w -o +i +n +t +e r -l -d - -1 +r +u +p +t -H -e -l -l +G o +t -w -o +i +n +t +e +r r -l -d +u +p +t + + + + + + +N +o -2 +i +n +t +e +r +r +u +p +t + + + diff --git a/zpu/hdl/example/sim_small_fpga_top.vhd b/zpu/hdl/example/sim_small_fpga_top.vhd index 5c05881..2a7a9f5 100644 --- a/zpu/hdl/example/sim_small_fpga_top.vhd +++ b/zpu/hdl/example/sim_small_fpga_top.vhd @@ -19,6 +19,7 @@ -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; +use ieee.numeric_std.all; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. @@ -88,6 +89,9 @@ signal io_mem_readEnable : std_logic; signal dram_ready : std_logic; signal io_ready : std_logic; signal io_reading : std_logic; +signal interruptcounter : unsigned(15 downto 0); +signal interrupt : std_logic; + signal break : std_logic; @@ -108,7 +112,7 @@ begin out_mem_writeEnable => mem_writeEnable, out_mem_readEnable => mem_readEnable, mem_writeMask => mem_writeMask, - interrupt => '0', + interrupt => interrupt, break => break); @@ -146,6 +150,7 @@ begin end if; end process; + io_ready <= (io_reading or io_mem_readEnable) and not io_busy; @@ -156,11 +161,23 @@ begin enable <= '0'; io_reading <= '0'; dram_ready <= '0'; + + interruptcounter <= to_unsigned(32, 16); + interrupt <= '0'; + elsif (clk'event and clk = '1') then enable <= '1'; io_reading <= io_busy or io_mem_readEnable; dram_ready<=dram_mem_readEnable; + -- keep interrupt signal high for 16 cycles + interruptcounter <= interruptcounter + 1; + if (interruptcounter < 16) then + report "Interrupt asserted!" severity note; + interrupt <='1'; + else + interrupt <='0'; + end if; end if; end process; diff --git a/zpu/hdl/example/simzpu_interrupt.do b/zpu/hdl/example/simzpu_interrupt.do new file mode 100644 index 0000000..864bf76 --- /dev/null +++ b/zpu/hdl/example/simzpu_interrupt.do @@ -0,0 +1,29 @@ +# Xilinx WebPack modelsim script +# +# +# cd C:/workspace/zpu/zpu/hdl/example +# do simzpu_interrupt.do + +set BreakOnAssertion 1 +vlib work + +vcom -93 -explicit zpu_config.vhd +vcom -93 -explicit ../zpu4/core/zpupkg.vhd +vcom -93 -explicit ../zpu4/src/txt_util.vhd +vcom -93 -explicit sim_small_fpga_top.vhd +vcom -93 -explicit ../zpu4/core/zpu_core_small.vhd +vcom -93 -explicit interrupt.vhd +vcom -93 -explicit ../zpu4/src/timer.vhd +vcom -93 -explicit ../zpu4/src/io.vhd +vcom -93 -explicit ../zpu4/src/trace.vhd + +# run ZPU +vsim fpga_top +view wave +add wave -recursive fpga_top/zpu/* +#add wave -recursive fpga_top/* +view structure +#view signals + +# Enough to run tiny programs +run 10 ms diff --git a/zpu/hdl/example_medium/.cvsignore b/zpu/hdl/example_medium/.cvsignore new file mode 100644 index 0000000..3add443 --- /dev/null +++ b/zpu/hdl/example_medium/.cvsignore @@ -0,0 +1,4 @@ +vsim.wlf +work +log.txt +trace.txt diff --git a/zpu/hdl/example_medium/dram_dmips.vhd b/zpu/hdl/example_medium/dram_dmips.vhd new file mode 100644 index 0000000..a9fd59e --- /dev/null +++ b/zpu/hdl/example_medium/dram_dmips.vhd @@ -0,0 +1,3308 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity dram is +port (clk : in std_logic; +areset : std_logic; + mem_writeEnable : in std_logic; + mem_readEnable : in std_logic; + mem_addr : in std_logic_vector(maxAddrBit downto 0); + mem_write : in std_logic_vector(wordSize-1 downto 0); + mem_read : out std_logic_vector(wordSize-1 downto 0); + mem_busy : out std_logic; + mem_writeMask : in std_logic_vector(wordBytes-1 downto 0)); +end dram; + +architecture dram_arch of dram is + + +type ram_type is array(natural range 0 to ((2**(maxAddrBitDRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); + +shared variable ram : ram_type := +( +0 => x"0b0b0b0b", +1 => x"82700b0b", +2 => x"80d5f40c", +3 => x"3a0b0b80", +4 => x"c4fb0400", +5 => x"00000000", +6 => x"00000000", +7 => x"00000000", +8 => x"80088408", +9 => x"88080b0b", +10 => x"80c5c22d", +11 => x"880c840c", +12 => x"800c0400", +13 => x"00000000", +14 => x"00000000", +15 => x"00000000", +16 => x"71fd0608", +17 => x"72830609", +18 => x"81058205", +19 => x"832b2a83", +20 => x"ffff0652", +21 => x"04000000", +22 => x"00000000", +23 => x"00000000", +24 => x"71fd0608", +25 => x"83ffff73", +26 => x"83060981", +27 => x"05820583", +28 => x"2b2b0906", +29 => x"7383ffff", +30 => x"0b0b0b0b", +31 => x"83a70400", +32 => x"72098105", +33 => x"72057373", +34 => x"09060906", +35 => x"73097306", +36 => x"070a8106", +37 => x"53510400", +38 => x"00000000", +39 => x"00000000", +40 => x"72722473", +41 => x"732e0753", +42 => x"51040000", +43 => x"00000000", +44 => x"00000000", +45 => x"00000000", +46 => x"00000000", +47 => x"00000000", +48 => x"71737109", +49 => x"71068106", +50 => x"30720a10", +51 => x"0a720a10", +52 => x"0a31050a", +53 => x"81065151", +54 => x"53510400", +55 => x"00000000", +56 => x"72722673", +57 => x"732e0753", +58 => x"51040000", +59 => x"00000000", +60 => x"00000000", +61 => x"00000000", +62 => x"00000000", +63 => x"00000000", +64 => x"00000000", +65 => x"00000000", +66 => x"00000000", +67 => x"00000000", +68 => x"00000000", +69 => x"00000000", +70 => x"00000000", +71 => x"00000000", +72 => x"0b0b0b88", +73 => x"c3040000", +74 => x"00000000", +75 => x"00000000", +76 => x"00000000", +77 => x"00000000", +78 => x"00000000", +79 => x"00000000", +80 => x"720a722b", +81 => x"0a535104", +82 => x"00000000", +83 => x"00000000", +84 => x"00000000", +85 => x"00000000", +86 => x"00000000", +87 => x"00000000", +88 => x"72729f06", +89 => x"0981050b", +90 => x"0b0b88a6", +91 => x"05040000", +92 => x"00000000", +93 => x"00000000", +94 => x"00000000", +95 => x"00000000", +96 => x"72722aff", +97 => x"739f062a", +98 => x"0974090a", +99 => x"8106ff05", +100 => x"06075351", +101 => x"04000000", +102 => x"00000000", +103 => x"00000000", +104 => x"71715351", +105 => x"020d0406", +106 => x"73830609", +107 => x"81058205", +108 => x"832b0b2b", +109 => x"0772fc06", +110 => x"0c515104", +111 => x"00000000", +112 => x"72098105", +113 => x"72050970", +114 => x"81050906", +115 => x"0a810653", +116 => x"51040000", +117 => x"00000000", +118 => x"00000000", +119 => x"00000000", +120 => x"72098105", +121 => x"72050970", +122 => x"81050906", +123 => x"0a098106", +124 => x"53510400", +125 => x"00000000", +126 => x"00000000", +127 => x"00000000", +128 => x"71098105", +129 => x"52040000", +130 => x"00000000", +131 => x"00000000", +132 => x"00000000", +133 => x"00000000", +134 => x"00000000", +135 => x"00000000", +136 => x"72720981", +137 => x"05055351", +138 => x"04000000", +139 => x"00000000", +140 => x"00000000", +141 => x"00000000", +142 => x"00000000", +143 => x"00000000", +144 => x"72097206", +145 => x"73730906", +146 => x"07535104", +147 => x"00000000", +148 => x"00000000", +149 => x"00000000", +150 => x"00000000", +151 => x"00000000", +152 => x"71fc0608", +153 => x"72830609", +154 => x"81058305", +155 => x"1010102a", +156 => x"81ff0652", +157 => x"04000000", +158 => x"00000000", +159 => x"00000000", +160 => x"71fc0608", +161 => x"0b0b80d5", +162 => x"e0738306", +163 => x"10100508", +164 => x"060b0b0b", +165 => x"88a90400", +166 => x"00000000", +167 => x"00000000", +168 => x"80088408", +169 => x"88087575", +170 => x"0b0b0bad", +171 => x"aa2d5050", +172 => x"80085688", +173 => x"0c840c80", +174 => x"0c510400", +175 => x"00000000", +176 => x"80088408", +177 => x"88087575", +178 => x"0b0b0bad", +179 => x"ee2d5050", +180 => x"80085688", +181 => x"0c840c80", +182 => x"0c510400", +183 => x"00000000", +184 => x"72097081", +185 => x"0509060a", +186 => x"8106ff05", +187 => x"70547106", +188 => x"73097274", +189 => x"05ff0506", +190 => x"07515151", +191 => x"04000000", +192 => x"72097081", +193 => x"0509060a", +194 => x"098106ff", +195 => x"05705471", +196 => x"06730972", +197 => x"7405ff05", +198 => x"06075151", +199 => x"51040000", +200 => x"05ff0504", +201 => x"00000000", +202 => x"00000000", +203 => x"00000000", +204 => x"00000000", +205 => x"00000000", +206 => x"00000000", +207 => x"00000000", +208 => x"810b0b0b", +209 => x"80d5f00c", +210 => x"51040000", +211 => x"00000000", +212 => x"00000000", +213 => x"00000000", +214 => x"00000000", +215 => x"00000000", +216 => x"71810552", +217 => x"04000000", +218 => x"00000000", +219 => x"00000000", +220 => x"00000000", +221 => x"00000000", +222 => x"00000000", +223 => x"00000000", +224 => x"00000000", +225 => x"00000000", +226 => x"00000000", +227 => x"00000000", +228 => x"00000000", +229 => x"00000000", +230 => x"00000000", +231 => x"00000000", +232 => x"02840572", +233 => x"10100552", +234 => x"04000000", +235 => x"00000000", +236 => x"00000000", +237 => x"00000000", +238 => x"00000000", +239 => x"00000000", +240 => x"00000000", +241 => x"00000000", +242 => x"00000000", +243 => x"00000000", +244 => x"00000000", +245 => x"00000000", +246 => x"00000000", +247 => x"00000000", +248 => x"717105ff", +249 => x"05715351", +250 => x"020d0400", +251 => x"00000000", +252 => x"00000000", +253 => x"00000000", +254 => x"00000000", +255 => x"00000000", +256 => x"82fd3fbf", +257 => x"a03f0410", +258 => x"10101010", +259 => x"10101010", +260 => x"10101010", +261 => x"10101010", +262 => x"10101010", +263 => x"10101010", +264 => x"10101010", +265 => x"10105351", +266 => x"047381ff", +267 => x"06738306", +268 => x"09810583", +269 => x"05101010", +270 => x"2b0772fc", +271 => x"060c5151", +272 => x"043c0472", +273 => x"72807281", +274 => x"06ff0509", +275 => x"72060571", +276 => x"1052720a", +277 => x"100a5372", +278 => x"ed385151", +279 => x"535104ff", +280 => x"3d0d0b0b", +281 => x"80e5e408", +282 => x"52710870", +283 => x"882a8132", +284 => x"70810651", +285 => x"515170f1", +286 => x"3873720c", +287 => x"833d0d04", +288 => x"80d5f008", +289 => x"802ea438", +290 => x"80d5f408", +291 => x"822ebd38", +292 => x"8380800b", +293 => x"0b0b80e5", +294 => x"e40c82a0", +295 => x"800b80e5", +296 => x"e80c8290", +297 => x"800b80e5", +298 => x"ec0c04f8", +299 => x"808080a4", +300 => x"0b0b0b80", +301 => x"e5e40cf8", +302 => x"80808280", +303 => x"0b80e5e8", +304 => x"0cf88080", +305 => x"84800b80", +306 => x"e5ec0c04", +307 => x"80c0a880", +308 => x"8c0b0b0b", +309 => x"80e5e40c", +310 => x"80c0a880", +311 => x"940b80e5", +312 => x"e80c0b0b", +313 => x"80c7d00b", +314 => x"80e5ec0c", +315 => x"04f23d0d", +316 => x"6080e5e8", +317 => x"08565d82", +318 => x"750c8059", +319 => x"805a800b", +320 => x"8f3d5d5b", +321 => x"7a101015", +322 => x"70087108", +323 => x"719f2c7e", +324 => x"852b5855", +325 => x"557d5359", +326 => x"5799993f", +327 => x"7d7f7a72", +328 => x"077c7207", +329 => x"71716081", +330 => x"05415f5d", +331 => x"5b595755", +332 => x"817b278f", +333 => x"38767d0c", +334 => x"77841e0c", +335 => x"7c800c90", +336 => x"3d0d0480", +337 => x"e5e80855", +338 => x"ffba3970", +339 => x"7080e5f0", +340 => x"335170a7", +341 => x"3880d5fc", +342 => x"08700852", +343 => x"5270802e", +344 => x"94388412", +345 => x"80d5fc0c", +346 => x"702d80d5", +347 => x"fc087008", +348 => x"525270ee", +349 => x"38810b80", +350 => x"e5f03450", +351 => x"50040470", +352 => x"0b0b80e5", +353 => x"e008802e", +354 => x"8e380b0b", +355 => x"0b0b800b", +356 => x"802e0981", +357 => x"06833850", +358 => x"040b0b80", +359 => x"e5e0510b", +360 => x"0b0bf4dc", +361 => x"3f500404", +362 => x"ff3d0d02", +363 => x"8f053352", +364 => x"718a2e8a", +365 => x"387151fd", +366 => x"a63f833d", +367 => x"0d048d51", +368 => x"fd9d3f71", +369 => x"51fd983f", +370 => x"833d0d04", +371 => x"ce3d0db5", +372 => x"3d707084", +373 => x"0552088b", +374 => x"a85c56a5", +375 => x"3d5e5c80", +376 => x"75708105", +377 => x"5733765b", +378 => x"55587378", +379 => x"2e80c138", +380 => x"8e3d5b73", +381 => x"a52e0981", +382 => x"0680c538", +383 => x"78708105", +384 => x"5a335473", +385 => x"80e42e81", +386 => x"b6387380", +387 => x"e42480c6", +388 => x"387380e3", +389 => x"2ea13880", +390 => x"52a55179", +391 => x"2d805273", +392 => x"51792d82", +393 => x"18587870", +394 => x"81055a33", +395 => x"5473c438", +396 => x"77800cb4", +397 => x"3d0d047b", +398 => x"841d8312", +399 => x"33565d57", +400 => x"80527351", +401 => x"792d8118", +402 => x"79708105", +403 => x"5b335558", +404 => x"73ffa038", +405 => x"db397380", +406 => x"f32e0981", +407 => x"06ffb838", +408 => x"7b841d71", +409 => x"08595d56", +410 => x"80773355", +411 => x"5673762e", +412 => x"8d388116", +413 => x"70187033", +414 => x"57555674", +415 => x"f538ff16", +416 => x"55807625", +417 => x"ffa03876", +418 => x"70810558", +419 => x"33548052", +420 => x"7351792d", +421 => x"811875ff", +422 => x"17575758", +423 => x"807625ff", +424 => x"85387670", +425 => x"81055833", +426 => x"54805273", +427 => x"51792d81", +428 => x"1875ff17", +429 => x"57575875", +430 => x"8024cc38", +431 => x"fee8397b", +432 => x"841d7108", +433 => x"70719f2c", +434 => x"5953595d", +435 => x"56807524", +436 => x"81913875", +437 => x"7d7c5856", +438 => x"54805773", +439 => x"772e0981", +440 => x"06b638b0", +441 => x"7b3402b5", +442 => x"05567a76", +443 => x"2e9738ff", +444 => x"16567533", +445 => x"75708105", +446 => x"57348117", +447 => x"577a762e", +448 => x"098106eb", +449 => x"38807534", +450 => x"767dff12", +451 => x"57585675", +452 => x"8024fef3", +453 => x"38fe8f39", +454 => x"8a527351", +455 => x"9fd03f80", +456 => x"0880c7d4", +457 => x"05337670", +458 => x"81055834", +459 => x"8a527351", +460 => x"9ef83f80", +461 => x"08548008", +462 => x"802effae", +463 => x"388a5273", +464 => x"519fab3f", +465 => x"800880c7", +466 => x"d4053376", +467 => x"70810558", +468 => x"348a5273", +469 => x"519ed33f", +470 => x"80085480", +471 => x"08ffb938", +472 => x"ff883974", +473 => x"527653b4", +474 => x"3dffb805", +475 => x"51949a3f", +476 => x"a33d0856", +477 => x"fedd3980", +478 => x"3d0d80c1", +479 => x"0b81b4bc", +480 => x"34800b81", +481 => x"b6980c70", +482 => x"800c823d", +483 => x"0d04ff3d", +484 => x"0d800b81", +485 => x"b4bc3352", +486 => x"527080c1", +487 => x"2e993871", +488 => x"81b69808", +489 => x"0781b698", +490 => x"0c80c20b", +491 => x"81b4c034", +492 => x"70800c83", +493 => x"3d0d0481", +494 => x"0b81b698", +495 => x"080781b6", +496 => x"980c80c2", +497 => x"0b81b4c0", +498 => x"3470800c", +499 => x"833d0d04", +500 => x"fd3d0d75", +501 => x"70088a05", +502 => x"535381b4", +503 => x"bc335170", +504 => x"80c12e8b", +505 => x"3873f338", +506 => x"70800c85", +507 => x"3d0d04ff", +508 => x"127081b4", +509 => x"b8083174", +510 => x"0c800c85", +511 => x"3d0d04fc", +512 => x"3d0d81b4", +513 => x"c4085574", +514 => x"802e8c38", +515 => x"76750871", +516 => x"0c81b4c4", +517 => x"0856548c", +518 => x"155381b4", +519 => x"b808528a", +520 => x"518fd43f", +521 => x"73800c86", +522 => x"3d0d04fb", +523 => x"3d0d7770", +524 => x"085656b0", +525 => x"5381b4c4", +526 => x"08527451", +527 => x"ab943f85", +528 => x"0b8c170c", +529 => x"850b8c16", +530 => x"0c750875", +531 => x"0c81b4c4", +532 => x"08547380", +533 => x"2e8a3873", +534 => x"08750c81", +535 => x"b4c40854", +536 => x"8c145381", +537 => x"b4b80852", +538 => x"8a518f8b", +539 => x"3f841508", +540 => x"ad38860b", +541 => x"8c160c88", +542 => x"15528816", +543 => x"08518e97", +544 => x"3f81b4c4", +545 => x"08700876", +546 => x"0c548c15", +547 => x"7054548a", +548 => x"52730851", +549 => x"8ee13f73", +550 => x"800c873d", +551 => x"0d047508", +552 => x"54b05373", +553 => x"527551aa", +554 => x"a93f7380", +555 => x"0c873d0d", +556 => x"04d93d0d", +557 => x"b0519dcf", +558 => x"3f800881", +559 => x"b4b40cb0", +560 => x"519dc43f", +561 => x"800881b4", +562 => x"c40c81b4", +563 => x"b4088008", +564 => x"0c800b80", +565 => x"0884050c", +566 => x"820b8008", +567 => x"88050ca8", +568 => x"0b80088c", +569 => x"050c9f53", +570 => x"80c7e052", +571 => x"80089005", +572 => x"51a9df3f", +573 => x"a13d5e9f", +574 => x"5380c880", +575 => x"527d51a9", +576 => x"d13f8a0b", +577 => x"80f2f80c", +578 => x"80d2a451", +579 => x"f9be3f80", +580 => x"c8a051f9", +581 => x"b73f80d2", +582 => x"a451f9b0", +583 => x"3f80d684", +584 => x"08802e89", +585 => x"d33880c8", +586 => x"d051f9a0", +587 => x"3f80d2a4", +588 => x"51f9993f", +589 => x"80d68008", +590 => x"5280c8fc", +591 => x"51f98d3f", +592 => x"80e69451", +593 => x"b2ff3f81", +594 => x"0b9a3d5e", +595 => x"5b800b80", +596 => x"d6800825", +597 => x"82d43890", +598 => x"3d5f80c1", +599 => x"0b81b4bc", +600 => x"34810b81", +601 => x"b6980c80", +602 => x"c20b81b4", +603 => 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x"2025730a", +2560 => x"00000000", +2561 => x"20202020", +2562 => x"20202020", +2563 => x"73686f75", +2564 => x"6c642062", +2565 => x"653a2020", +2566 => x"20444852", +2567 => x"5953544f", +2568 => x"4e452050", +2569 => x"524f4752", +2570 => x"414d2c20", +2571 => x"31275354", +2572 => x"20535452", +2573 => x"494e470a", +2574 => x"00000000", +2575 => x"5374725f", +2576 => x"325f4c6f", +2577 => x"633a2020", +2578 => x"20202020", +2579 => x"20202020", +2580 => x"2025730a", +2581 => x"00000000", +2582 => x"20202020", +2583 => x"20202020", +2584 => x"73686f75", +2585 => x"6c642062", +2586 => x"653a2020", +2587 => x"20444852", +2588 => x"5953544f", +2589 => x"4e452050", +2590 => x"524f4752", +2591 => x"414d2c20", +2592 => x"32274e44", +2593 => x"20535452", +2594 => x"494e470a", +2595 => x"00000000", +2596 => x"55736572", +2597 => x"2074696d", +2598 => x"653a2025", +2599 => x"640a0000", +2600 => x"4d696372", +2601 => x"6f736563", +2602 => x"6f6e6473", +2603 => x"20666f72", +2604 => x"206f6e65", +2605 => x"2072756e", +2606 => x"20746872", +2607 => x"6f756768", +2608 => x"20446872", +2609 => x"7973746f", +2610 => x"6e653a20", +2611 => x"00000000", +2612 => x"2564200a", +2613 => x"00000000", +2614 => x"44687279", +2615 => x"73746f6e", +2616 => x"65732070", +2617 => x"65722053", +2618 => x"65636f6e", +2619 => x"643a2020", +2620 => x"20202020", +2621 => x"20202020", +2622 => x"20202020", +2623 => x"20202020", +2624 => x"20202020", +2625 => x"00000000", +2626 => x"56415820", +2627 => x"4d495053", +2628 => x"20726174", +2629 => x"696e6720", +2630 => x"2a203130", +2631 => x"3030203d", +2632 => x"20256420", +2633 => x"0a000000", +2634 => x"50726f67", +2635 => x"72616d20", +2636 => x"636f6d70", +2637 => x"696c6564", +2638 => x"20776974", +2639 => x"686f7574", +2640 => x"20277265", +2641 => x"67697374", +2642 => x"65722720", +2643 => x"61747472", +2644 => x"69627574", +2645 => x"650a0000", +2646 => x"4d656173", +2647 => x"75726564", +2648 => x"2074696d", +2649 => x"6520746f", +2650 => x"6f20736d", +2651 => x"616c6c20", +2652 => x"746f206f", +2653 => x"62746169", +2654 => x"6e206d65", +2655 => x"616e696e", +2656 => x"6766756c", +2657 => x"20726573", +2658 => x"756c7473", +2659 => x"0a000000", +2660 => x"506c6561", +2661 => x"73652069", +2662 => x"6e637265", +2663 => x"61736520", +2664 => x"6e756d62", +2665 => x"6572206f", +2666 => x"66207275", +2667 => x"6e730a00", +2668 => x"44485259", +2669 => x"53544f4e", +2670 => x"45205052", +2671 => x"4f475241", +2672 => x"4d2c2033", +2673 => x"27524420", +2674 => x"53545249", +2675 => x"4e470000", +2676 => x"00010202", +2677 => x"03030303", +2678 => x"04040404", +2679 => x"04040404", +2680 => x"05050505", +2681 => x"05050505", +2682 => x"05050505", +2683 => x"05050505", +2684 => x"06060606", +2685 => x"06060606", +2686 => x"06060606", +2687 => x"06060606", +2688 => x"06060606", +2689 => x"06060606", +2690 => x"06060606", +2691 => x"06060606", +2692 => x"07070707", +2693 => x"07070707", +2694 => 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x"08080808", +2740 => x"43000000", +2741 => x"64756d6d", +2742 => x"792e6578", +2743 => x"65000000", +2744 => x"00ffffff", +2745 => x"ff00ffff", +2746 => x"ffff00ff", +2747 => x"ffffff00", +2748 => x"00000000", +2749 => x"00000000", +2750 => x"00000000", +2751 => x"000032dc", +2752 => x"0000c350", +2753 => x"00000000", +2754 => x"00000000", +2755 => x"00000000", +2756 => x"00000000", +2757 => x"00000000", +2758 => x"00000000", +2759 => x"00000000", +2760 => x"00000000", +2761 => x"00000000", +2762 => x"00000000", +2763 => x"00000000", +2764 => x"00000000", +2765 => x"00000000", +2766 => x"ffffffff", +2767 => x"00000000", +2768 => x"00020000", +2769 => x"00000000", +2770 => x"00000000", +2771 => x"00002b44", +2772 => x"00002b44", +2773 => x"00002b4c", +2774 => x"00002b4c", +2775 => x"00002b54", +2776 => x"00002b54", +2777 => x"00002b5c", +2778 => x"00002b5c", +2779 => x"00002b64", +2780 => x"00002b64", +2781 => x"00002b6c", +2782 => x"00002b6c", +2783 => x"00002b74", +2784 => x"00002b74", +2785 => x"00002b7c", +2786 => x"00002b7c", +2787 => x"00002b84", +2788 => x"00002b84", +2789 => x"00002b8c", +2790 => x"00002b8c", +2791 => x"00002b94", +2792 => x"00002b94", +2793 => x"00002b9c", +2794 => x"00002b9c", +2795 => x"00002ba4", +2796 => x"00002ba4", +2797 => x"00002bac", +2798 => x"00002bac", +2799 => x"00002bb4", +2800 => x"00002bb4", +2801 => x"00002bbc", +2802 => x"00002bbc", +2803 => x"00002bc4", +2804 => x"00002bc4", +2805 => x"00002bcc", +2806 => x"00002bcc", +2807 => x"00002bd4", +2808 => x"00002bd4", +2809 => x"00002bdc", +2810 => x"00002bdc", +2811 => x"00002be4", +2812 => x"00002be4", +2813 => x"00002bec", +2814 => x"00002bec", +2815 => x"00002bf4", +2816 => x"00002bf4", +2817 => x"00002bfc", +2818 => x"00002bfc", +2819 => x"00002c04", +2820 => x"00002c04", +2821 => x"00002c0c", +2822 => x"00002c0c", +2823 => x"00002c14", +2824 => x"00002c14", +2825 => x"00002c1c", +2826 => x"00002c1c", +2827 => x"00002c24", +2828 => x"00002c24", +2829 => x"00002c2c", +2830 => x"00002c2c", +2831 => x"00002c34", +2832 => x"00002c34", +2833 => x"00002c3c", +2834 => x"00002c3c", +2835 => x"00002c44", +2836 => x"00002c44", +2837 => x"00002c4c", +2838 => x"00002c4c", +2839 => x"00002c54", +2840 => x"00002c54", +2841 => x"00002c5c", +2842 => x"00002c5c", +2843 => x"00002c64", +2844 => x"00002c64", +2845 => x"00002c6c", +2846 => x"00002c6c", +2847 => x"00002c74", +2848 => x"00002c74", +2849 => x"00002c7c", +2850 => x"00002c7c", +2851 => x"00002c84", +2852 => x"00002c84", +2853 => x"00002c8c", +2854 => x"00002c8c", +2855 => x"00002c94", +2856 => x"00002c94", +2857 => x"00002c9c", +2858 => x"00002c9c", +2859 => x"00002ca4", +2860 => x"00002ca4", +2861 => x"00002cac", +2862 => x"00002cac", +2863 => x"00002cb4", +2864 => x"00002cb4", +2865 => x"00002cbc", +2866 => x"00002cbc", +2867 => x"00002cc4", +2868 => x"00002cc4", +2869 => x"00002ccc", +2870 => x"00002ccc", +2871 => x"00002cd4", +2872 => x"00002cd4", +2873 => x"00002cdc", +2874 => x"00002cdc", +2875 => x"00002ce4", +2876 => x"00002ce4", +2877 => x"00002cec", +2878 => x"00002cec", +2879 => x"00002cf4", +2880 => x"00002cf4", +2881 => x"00002cfc", +2882 => x"00002cfc", +2883 => x"00002d04", +2884 => x"00002d04", +2885 => x"00002d0c", +2886 => x"00002d0c", +2887 => x"00002d14", +2888 => x"00002d14", +2889 => x"00002d1c", +2890 => x"00002d1c", +2891 => x"00002d24", +2892 => x"00002d24", +2893 => x"00002d2c", +2894 => x"00002d2c", +2895 => x"00002d34", +2896 => x"00002d34", +2897 => x"00002d3c", +2898 => x"00002d3c", +2899 => x"00002d44", +2900 => x"00002d44", +2901 => x"00002d4c", +2902 => x"00002d4c", +2903 => x"00002d54", +2904 => x"00002d54", +2905 => x"00002d5c", +2906 => x"00002d5c", +2907 => x"00002d64", +2908 => x"00002d64", +2909 => x"00002d6c", +2910 => x"00002d6c", +2911 => x"00002d74", +2912 => x"00002d74", +2913 => x"00002d7c", +2914 => x"00002d7c", +2915 => x"00002d84", +2916 => x"00002d84", +2917 => x"00002d8c", +2918 => x"00002d8c", +2919 => x"00002d94", +2920 => x"00002d94", +2921 => x"00002d9c", +2922 => x"00002d9c", +2923 => x"00002da4", +2924 => x"00002da4", +2925 => x"00002dac", +2926 => x"00002dac", +2927 => x"00002db4", +2928 => x"00002db4", +2929 => x"00002dbc", +2930 => x"00002dbc", +2931 => x"00002dc4", +2932 => x"00002dc4", +2933 => x"00002dcc", +2934 => x"00002dcc", +2935 => x"00002dd4", +2936 => x"00002dd4", +2937 => x"00002ddc", +2938 => x"00002ddc", +2939 => x"00002de4", +2940 => x"00002de4", +2941 => x"00002dec", +2942 => x"00002dec", +2943 => x"00002df4", +2944 => x"00002df4", +2945 => x"00002dfc", +2946 => x"00002dfc", +2947 => x"00002e04", +2948 => x"00002e04", +2949 => x"00002e0c", +2950 => x"00002e0c", +2951 => x"00002e14", +2952 => x"00002e14", +2953 => x"00002e1c", +2954 => x"00002e1c", +2955 => x"00002e24", +2956 => x"00002e24", +2957 => x"00002e2c", +2958 => x"00002e2c", +2959 => x"00002e34", +2960 => x"00002e34", +2961 => x"00002e3c", +2962 => x"00002e3c", +2963 => x"00002e44", +2964 => x"00002e44", +2965 => x"00002e4c", +2966 => x"00002e4c", +2967 => x"00002e54", +2968 => x"00002e54", +2969 => x"00002e5c", +2970 => x"00002e5c", +2971 => x"00002e64", +2972 => x"00002e64", +2973 => x"00002e6c", +2974 => x"00002e6c", +2975 => x"00002e74", +2976 => x"00002e74", +2977 => x"00002e7c", +2978 => x"00002e7c", +2979 => x"00002e84", +2980 => x"00002e84", +2981 => x"00002e8c", +2982 => x"00002e8c", +2983 => x"00002e94", +2984 => x"00002e94", +2985 => x"00002e9c", +2986 => x"00002e9c", +2987 => x"00002ea4", +2988 => x"00002ea4", +2989 => x"00002eac", +2990 => x"00002eac", +2991 => x"00002eb4", +2992 => x"00002eb4", +2993 => x"00002ebc", +2994 => x"00002ebc", +2995 => x"00002ec4", +2996 => x"00002ec4", +2997 => x"00002ecc", +2998 => x"00002ecc", +2999 => x"00002ed4", +3000 => x"00002ed4", +3001 => x"00002edc", +3002 => x"00002edc", +3003 => x"00002ee4", +3004 => x"00002ee4", +3005 => x"00002eec", +3006 => x"00002eec", +3007 => x"00002ef4", +3008 => x"00002ef4", +3009 => x"00002efc", +3010 => x"00002efc", +3011 => x"00002f04", +3012 => x"00002f04", +3013 => x"00002f0c", +3014 => x"00002f0c", +3015 => x"00002f14", +3016 => x"00002f14", +3017 => x"00002f1c", +3018 => x"00002f1c", +3019 => x"00002f24", +3020 => x"00002f24", +3021 => x"00002f2c", +3022 => x"00002f2c", +3023 => x"00002f34", +3024 => x"00002f34", +3025 => x"00002f3c", +3026 => x"00002f3c", +3027 => x"00002f50", +3028 => x"00000000", +3029 => x"000031b8", +3030 => x"00003214", +3031 => x"00003270", +3032 => x"00000000", +3033 => x"00000000", +3034 => x"00000000", +3035 => x"00000000", +3036 => x"00000000", +3037 => x"00000000", +3038 => x"00000000", +3039 => x"00000000", +3040 => x"00000000", +3041 => x"00002ad0", +3042 => x"00000000", +3043 => x"00000000", +3044 => x"00000000", +3045 => x"00000000", +3046 => x"00000000", +3047 => x"00000000", +3048 => x"00000000", +3049 => x"00000000", +3050 => x"00000000", +3051 => x"00000000", +3052 => x"00000000", +3053 => x"00000000", +3054 => x"00000000", +3055 => x"00000000", +3056 => x"00000000", +3057 => x"00000000", +3058 => x"00000000", +3059 => x"00000000", +3060 => x"00000000", +3061 => x"00000000", +3062 => x"00000000", +3063 => x"00000000", +3064 => x"00000000", +3065 => x"00000000", +3066 => x"00000000", +3067 => x"00000000", +3068 => x"00000000", +3069 => x"00000000", +3070 => x"00000001", +3071 => x"330eabcd", +3072 => x"1234e66d", +3073 => x"deec0005", +3074 => x"000b0000", +3075 => x"00000000", +3076 => x"00000000", +3077 => x"00000000", +3078 => x"00000000", +3079 => x"00000000", +3080 => x"00000000", +3081 => x"00000000", +3082 => x"00000000", +3083 => x"00000000", +3084 => x"00000000", +3085 => x"00000000", +3086 => x"00000000", +3087 => x"00000000", +3088 => x"00000000", +3089 => x"00000000", +3090 => x"00000000", +3091 => x"00000000", +3092 => x"00000000", +3093 => x"00000000", +3094 => x"00000000", +3095 => x"00000000", +3096 => x"00000000", +3097 => x"00000000", +3098 => x"00000000", +3099 => x"00000000", +3100 => x"00000000", +3101 => x"00000000", +3102 => x"00000000", +3103 => x"00000000", +3104 => x"00000000", +3105 => x"00000000", +3106 => x"00000000", +3107 => x"00000000", +3108 => x"00000000", +3109 => x"00000000", +3110 => x"00000000", +3111 => x"00000000", +3112 => x"00000000", +3113 => x"00000000", +3114 => x"00000000", +3115 => x"00000000", +3116 => x"00000000", +3117 => x"00000000", +3118 => x"00000000", +3119 => x"00000000", +3120 => x"00000000", +3121 => x"00000000", +3122 => x"00000000", +3123 => x"00000000", +3124 => x"00000000", +3125 => x"00000000", +3126 => x"00000000", +3127 => x"00000000", +3128 => x"00000000", +3129 => x"00000000", +3130 => x"00000000", +3131 => x"00000000", +3132 => x"00000000", +3133 => x"00000000", +3134 => x"00000000", +3135 => x"00000000", +3136 => x"00000000", +3137 => x"00000000", +3138 => x"00000000", +3139 => x"00000000", +3140 => x"00000000", +3141 => x"00000000", +3142 => x"00000000", +3143 => x"00000000", +3144 => x"00000000", +3145 => x"00000000", +3146 => x"00000000", +3147 => x"00000000", +3148 => x"00000000", +3149 => x"00000000", +3150 => x"00000000", +3151 => x"00000000", +3152 => x"00000000", +3153 => x"00000000", +3154 => x"00000000", +3155 => x"00000000", +3156 => x"00000000", +3157 => x"00000000", +3158 => x"00000000", +3159 => x"00000000", +3160 => x"00000000", +3161 => x"00000000", +3162 => x"00000000", +3163 => x"00000000", +3164 => x"00000000", +3165 => x"00000000", +3166 => x"00000000", +3167 => x"00000000", +3168 => x"00000000", +3169 => x"00000000", +3170 => x"00000000", +3171 => x"00000000", +3172 => x"00000000", +3173 => x"00000000", +3174 => x"00000000", +3175 => x"00000000", +3176 => x"00000000", +3177 => x"00000000", +3178 => x"00000000", +3179 => x"00000000", +3180 => x"00000000", +3181 => x"00000000", +3182 => x"00000000", +3183 => x"00000000", +3184 => x"00000000", +3185 => x"00000000", +3186 => x"00000000", +3187 => x"00000000", +3188 => x"00000000", +3189 => x"00000000", +3190 => x"00000000", +3191 => x"00000000", +3192 => x"00000000", +3193 => x"00000000", +3194 => x"00000000", +3195 => x"00000000", +3196 => x"00000000", +3197 => x"00000000", +3198 => x"00000000", +3199 => x"00000000", +3200 => x"00000000", +3201 => x"00000000", +3202 => x"00000000", +3203 => x"00000000", +3204 => x"00000000", +3205 => x"00000000", +3206 => x"00000000", +3207 => x"00000000", +3208 => x"00000000", +3209 => x"00000000", +3210 => x"00000000", +3211 => x"00000000", +3212 => x"00000000", +3213 => x"00000000", +3214 => x"00000000", +3215 => x"00000000", +3216 => x"00000000", +3217 => x"00000000", +3218 => x"00000000", +3219 => x"00000000", +3220 => x"00000000", +3221 => x"00000000", +3222 => x"00000000", +3223 => x"00000000", +3224 => x"00000000", +3225 => x"00000000", +3226 => x"00000000", +3227 => x"00000000", +3228 => x"00000000", +3229 => x"00000000", +3230 => x"00000000", +3231 => x"00000000", +3232 => x"00000000", +3233 => x"00000000", +3234 => x"00000000", +3235 => x"00000000", +3236 => x"00000000", +3237 => x"00000000", +3238 => x"00000000", +3239 => x"00000000", +3240 => x"00000000", +3241 => x"00000000", +3242 => x"00000000", +3243 => x"00000000", +3244 => x"00000000", +3245 => x"00000000", +3246 => x"00000000", +3247 => x"00000000", +3248 => x"00000000", +3249 => x"00000000", +3250 => x"00000000", +3251 => x"00002ad4", +3252 => x"ffffffff", +3253 => x"00000000", +3254 => x"ffffffff", +3255 => x"00000000", + others => x"00000000" +); + +begin + +mem_busy<=mem_readEnable; -- we're done on the cycle after we serve the read request + +process (clk, areset) +begin + if areset = '1' then + elsif (clk'event and clk = '1') then + if (mem_writeEnable = '1') then + ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit)))) := mem_write; + end if; + if (mem_readEnable = '1') then + mem_read <= ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit)))); + end if; + end if; +end process; + + + + +end dram_arch; diff --git a/zpu/hdl/example_medium/dram_hello.vhd b/zpu/hdl/example_medium/dram_hello.vhd new file mode 100644 index 0000000..4f02cca --- /dev/null +++ b/zpu/hdl/example_medium/dram_hello.vhd @@ -0,0 +1,3107 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity dram is +port (clk : in std_logic; +areset : std_logic; + mem_writeEnable : in std_logic; + mem_readEnable : in std_logic; + mem_addr : in std_logic_vector(maxAddrBit downto 0); + mem_write : in std_logic_vector(wordSize-1 downto 0); + mem_read : out std_logic_vector(wordSize-1 downto 0); + mem_busy : out std_logic; + mem_writeMask : in std_logic_vector(wordBytes-1 downto 0)); +end dram; + +architecture dram_arch of dram is + + +type ram_type is array(natural range 0 to ((2**(maxAddrBitDRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); + +shared variable ram : ram_type := +( +0 => x"0b0b0b0b", +1 => x"82700b0b", +2 => x"80cfd80c", +3 => x"3a0b0b80", +4 => x"c6d00400", +5 => x"00000000", +6 => x"00000000", +7 => x"00000000", +8 => x"80088408", +9 => x"88080b0b", +10 => x"80c7972d", +11 => x"880c840c", +12 => x"800c0400", +13 => x"00000000", +14 => x"00000000", +15 => x"00000000", +16 => x"71fd0608", +17 => x"72830609", +18 => x"81058205", +19 => x"832b2a83", +20 => x"ffff0652", +21 => x"04000000", +22 => x"00000000", +23 => x"00000000", +24 => x"71fd0608", +25 => x"83ffff73", +26 => x"83060981", +27 => x"05820583", +28 => x"2b2b0906", +29 => x"7383ffff", +30 => x"0b0b0b0b", +31 => x"83a70400", +32 => x"72098105", +33 => x"72057373", +34 => x"09060906", +35 => x"73097306", +36 => x"070a8106", +37 => x"53510400", +38 => x"00000000", +39 => x"00000000", +40 => x"72722473", +41 => x"732e0753", +42 => x"51040000", +43 => x"00000000", +44 => x"00000000", +45 => x"00000000", +46 => x"00000000", +47 => x"00000000", +48 => x"71737109", +49 => x"71068106", +50 => x"30720a10", +51 => x"0a720a10", +52 => x"0a31050a", +53 => x"81065151", +54 => x"53510400", +55 => x"00000000", +56 => x"72722673", +57 => x"732e0753", +58 => x"51040000", +59 => x"00000000", +60 => x"00000000", +61 => x"00000000", +62 => x"00000000", +63 => x"00000000", +64 => x"00000000", +65 => x"00000000", +66 => x"00000000", +67 => x"00000000", +68 => x"00000000", +69 => x"00000000", +70 => x"00000000", +71 => x"00000000", +72 => x"0b0b0b88", +73 => x"c4040000", +74 => x"00000000", +75 => x"00000000", +76 => x"00000000", +77 => x"00000000", +78 => x"00000000", +79 => x"00000000", +80 => x"720a722b", +81 => x"0a535104", +82 => x"00000000", +83 => x"00000000", +84 => x"00000000", +85 => x"00000000", +86 => x"00000000", +87 => x"00000000", +88 => x"72729f06", +89 => x"0981050b", +90 => x"0b0b88a7", +91 => x"05040000", +92 => x"00000000", +93 => x"00000000", +94 => x"00000000", +95 => x"00000000", +96 => x"72722aff", +97 => x"739f062a", +98 => x"0974090a", +99 => x"8106ff05", +100 => x"06075351", +101 => x"04000000", +102 => x"00000000", +103 => x"00000000", +104 => x"71715351", +105 => x"020d0406", +106 => x"73830609", +107 => x"81058205", +108 => x"832b0b2b", +109 => x"0772fc06", +110 => x"0c515104", +111 => x"00000000", +112 => x"72098105", +113 => x"72050970", +114 => x"81050906", +115 => x"0a810653", +116 => x"51040000", +117 => x"00000000", +118 => x"00000000", +119 => x"00000000", +120 => x"72098105", +121 => x"72050970", +122 => x"81050906", +123 => x"0a098106", +124 => x"53510400", +125 => x"00000000", +126 => x"00000000", +127 => x"00000000", +128 => x"71098105", +129 => x"52040000", +130 => x"00000000", +131 => x"00000000", +132 => x"00000000", +133 => x"00000000", +134 => x"00000000", +135 => x"00000000", +136 => x"72720981", +137 => x"05055351", +138 => x"04000000", +139 => x"00000000", +140 => x"00000000", +141 => x"00000000", +142 => x"00000000", +143 => x"00000000", +144 => x"72097206", +145 => x"73730906", +146 => x"07535104", +147 => x"00000000", +148 => x"00000000", +149 => x"00000000", +150 => x"00000000", +151 => x"00000000", +152 => x"71fc0608", +153 => x"72830609", +154 => x"81058305", +155 => x"1010102a", +156 => x"81ff0652", +157 => x"04000000", +158 => x"00000000", +159 => x"00000000", +160 => x"71fc0608", +161 => x"0b0b80cf", +162 => x"c4738306", +163 => x"10100508", +164 => x"060b0b0b", +165 => x"88aa0400", +166 => x"00000000", +167 => x"00000000", +168 => x"80088408", +169 => x"88087575", +170 => x"0b0b0b8b", +171 => x"9f2d5050", +172 => x"80085688", +173 => x"0c840c80", +174 => x"0c510400", +175 => x"00000000", +176 => x"80088408", +177 => x"88087575", +178 => x"0b0b0b8b", +179 => x"e32d5050", +180 => x"80085688", +181 => x"0c840c80", +182 => x"0c510400", +183 => x"00000000", +184 => x"72097081", +185 => x"0509060a", +186 => x"8106ff05", +187 => x"70547106", +188 => x"73097274", +189 => x"05ff0506", +190 => x"07515151", +191 => x"04000000", +192 => x"72097081", +193 => x"0509060a", +194 => x"098106ff", +195 => x"05705471", +196 => x"06730972", +197 => x"7405ff05", +198 => x"06075151", +199 => x"51040000", +200 => x"05ff0504", +201 => x"00000000", +202 => x"00000000", +203 => x"00000000", +204 => x"00000000", +205 => x"00000000", +206 => x"00000000", +207 => x"00000000", +208 => x"810b0b0b", +209 => x"80cfd40c", +210 => x"51040000", +211 => x"00000000", +212 => x"00000000", +213 => x"00000000", +214 => x"00000000", +215 => x"00000000", +216 => x"71810552", +217 => x"04000000", +218 => x"00000000", +219 => x"00000000", +220 => x"00000000", +221 => x"00000000", +222 => x"00000000", +223 => x"00000000", +224 => x"00000000", +225 => x"00000000", +226 => x"00000000", +227 => x"00000000", +228 => x"00000000", +229 => x"00000000", +230 => x"00000000", +231 => x"00000000", +232 => x"02840572", +233 => x"10100552", +234 => x"04000000", +235 => x"00000000", +236 => x"00000000", +237 => x"00000000", +238 => x"00000000", +239 => x"00000000", +240 => x"00000000", +241 => x"00000000", +242 => x"00000000", +243 => x"00000000", +244 => x"00000000", +245 => x"00000000", +246 => x"00000000", +247 => x"00000000", +248 => x"717105ff", +249 => x"05715351", +250 => x"020d0400", +251 => x"00000000", +252 => x"00000000", +253 => x"00000000", +254 => x"00000000", +255 => x"00000000", +256 => x"82c53f80", +257 => x"c6d93f04", +258 => x"10101010", +259 => x"10101010", +260 => x"10101010", +261 => x"10101010", +262 => x"10101010", +263 => x"10101010", +264 => x"10101010", +265 => x"10101053", +266 => x"51047381", +267 => x"ff067383", +268 => x"06098105", +269 => x"83051010", +270 => x"102b0772", +271 => x"fc060c51", +272 => x"51043c04", +273 => x"72728072", +274 => x"8106ff05", +275 => x"09720605", +276 => x"71105272", +277 => x"0a100a53", +278 => x"72ed3851", +279 => x"51535104", +280 => x"fe3d0d0b", +281 => x"0b80dfc0", +282 => x"08538413", +283 => x"0870882a", +284 => x"70810651", +285 => x"52527080", +286 => x"2ef03871", +287 => x"81ff0680", +288 => x"0c843d0d", +289 => x"04ff3d0d", +290 => x"0b0b80df", +291 => x"c0085271", +292 => x"0870882a", +293 => x"81327081", +294 => x"06515151", +295 => x"70f13873", +296 => x"720c833d", +297 => x"0d0480cf", +298 => x"d408802e", +299 => x"a43880cf", +300 => x"d808822e", +301 => x"bd388380", +302 => x"800b0b0b", +303 => x"80dfc00c", +304 => x"82a0800b", +305 => x"80dfc40c", +306 => x"8290800b", +307 => x"80dfc80c", +308 => x"04f88080", +309 => x"80a40b0b", +310 => x"0b80dfc0", +311 => x"0cf88080", +312 => x"82800b80", +313 => x"dfc40cf8", +314 => x"80808480", +315 => x"0b80dfc8", +316 => x"0c0480c0", +317 => x"a8808c0b", +318 => x"0b0b80df", +319 => x"c00c80c0", +320 => x"a880940b", +321 => x"80dfc40c", +322 => x"0b0b80cf", +323 => x"8c0b80df", +324 => x"c80c0470", +325 => x"7080dfcc", +326 => x"335170a7", +327 => x"3880cfe0", +328 => x"08700852", +329 => x"5270802e", +330 => x"94388412", +331 => x"80cfe00c", +332 => x"702d80cf", +333 => x"e0087008", +334 => x"525270ee", +335 => x"38810b80", +336 => x"dfcc3450", +337 => x"50040470", +338 => x"0b0b80df", +339 => x"bc08802e", +340 => x"8e380b0b", +341 => x"0b0b800b", +342 => x"802e0981", +343 => x"06833850", +344 => x"040b0b80", +345 => x"dfbc510b", +346 => x"0b0bf594", +347 => x"3f500404", +348 => x"fe3d0d89", +349 => x"5380cf90", +350 => x"5182c13f", +351 => x"80cfa051", +352 => x"82ba3f81", +353 => x"0a0b80df", +354 => x"d80cff0b", +355 => x"80dfdc0c", +356 => x"ff135372", +357 => x"8025de38", +358 => x"72800c84", +359 => x"3d0d04fb", +360 => x"3d0d7779", +361 => x"55558056", +362 => x"757524ab", +363 => x"38807424", +364 => x"9d388053", +365 => x"73527451", +366 => x"80e13f80", +367 => x"08547580", +368 => x"2e853880", +369 => x"08305473", +370 => x"800c873d", +371 => x"0d047330", +372 => x"76813257", +373 => x"54dc3974", +374 => x"30558156", +375 => x"738025d2", +376 => x"38ec39fa", +377 => x"3d0d787a", +378 => x"57558057", +379 => x"767524a4", +380 => x"38759f2c", +381 => x"54815375", +382 => x"74327431", +383 => x"5274519b", +384 => x"3f800854", +385 => x"76802e85", +386 => x"38800830", +387 => x"5473800c", +388 => x"883d0d04", +389 => x"74305581", +390 => x"57d739fc", +391 => x"3d0d7678", +392 => x"53548153", +393 => x"80747326", +394 => x"52557280", +395 => x"2e983870", +396 => x"802eab38", +397 => x"807224a6", +398 => x"38711073", +399 => x"10757226", +400 => x"53545272", +401 => x"ea387351", +402 => x"78833874", +403 => x"5170800c", +404 => x"863d0d04", +405 => x"720a100a", +406 => x"720a100a", +407 => x"53537280", +408 => x"2ee43871", +409 => x"7426ed38", +410 => x"73723175", +411 => x"7407740a", +412 => x"100a740a", +413 => x"100a5555", +414 => x"5654e339", +415 => x"f73d0d7c", +416 => x"70525380", +417 => x"f93f7254", +418 => x"80085580", +419 => x"cfb05681", +420 => x"57800881", +421 => x"055a8b3d", +422 => x"e4115953", +423 => x"8259f413", +424 => x"527b8811", +425 => x"08525381", +426 => x"b23f8008", +427 => x"30708008", +428 => x"079f2c8a", +429 => x"07800c53", +430 => x"8b3d0d04", +431 => x"f63d0d7c", +432 => x"80cfe408", +433 => x"71535553", +434 => x"b53f7255", +435 => x"80085680", +436 => x"cfb05781", +437 => x"58800881", +438 => x"055b8c3d", +439 => x"e4115a53", +440 => x"825af413", +441 => x"52881408", +442 => x"5180f03f", +443 => x"80083070", +444 => x"8008079f", +445 => x"2c8a0780", +446 => x"0c548c3d", +447 => x"0d047070", +448 => x"70707570", +449 => x"71830653", +450 => x"555270b4", +451 => x"38717008", +452 => x"7009f7fb", +453 => x"fdff1206", +454 => x"f8848281", +455 => x"80065452", +456 => x"53719b38", +457 => x"84137008", +458 => x"7009f7fb", +459 => x"fdff1206", +460 => x"f8848281", +461 => x"80065452", +462 => x"5371802e", +463 => x"e7387252", +464 => x"71335372", +465 => x"802e8a38", +466 => x"81127033", +467 => x"545272f8", +468 => x"38717431", +469 => x"800c5050", +470 => x"505004f2", +471 => x"3d0d6062", +472 => x"88110870", +473 => x"58565f5a", +474 => x"73802e81", +475 => x"8c388c1a", +476 => x"2270832a", +477 => x"81328106", +478 => x"56587486", +479 => x"38901a08", +480 => x"91387951", +481 => x"90b73fff", +482 => x"55800880", +483 => x"ec388c1a", +484 => x"22587d08", +485 => x"55807883", +486 => x"ffff0670", +487 => x"0a100a81", +488 => x"06415c57", +489 => x"7e772e80", +490 => x"d7387690", +491 => x"38740884", +492 => x"16088817", +493 => x"57585676", +494 => x"802ef238", +495 => x"76548880", +496 => x"77278438", +497 => x"88805473", +498 => x"5375529c", +499 => x"1a0851a4", +500 => x"1a085877", +501 => x"2d800b80", +502 => x"082582e0", +503 => x"38800816", +504 => x"77800831", +505 => x"7f880508", +506 => x"80083170", +507 => x"6188050c", +508 => x"5b585678", +509 => x"ffb43880", +510 => x"5574800c", +511 => x"903d0d04", +512 => x"7a813281", +513 => x"06774056", +514 => x"75802e81", +515 => x"bd387690", +516 => x"38740884", +517 => x"16088817", +518 => x"57585976", +519 => x"802ef238", +520 => x"881a0878", +521 => x"83ffff06", +522 => x"70892a81", +523 => x"06565956", +524 => x"73802e82", +525 => x"f8387577", +526 => x"278b3877", +527 => x"872a8106", +528 => x"5c7b82b5", +529 => x"38767627", +530 => x"83387656", +531 => x"75537852", +532 => x"79085185", +533 => x"833f881a", +534 => x"08763188", +535 => x"1b0c7908", +536 => x"167a0c76", +537 => x"56751977", +538 => x"77317f88", +539 => x"05087831", +540 => x"70618805", +541 => x"0c415859", +542 => x"7e802efe", +543 => x"fa388c1a", +544 => x"2258ff8a", +545 => x"39787954", +546 => x"7c537b52", +547 => x"5684c93f", +548 => x"881a0879", +549 => x"31881b0c", +550 => x"7908197a", +551 => x"0c7c7631", +552 => x"5d7c8e38", +553 => x"79518ff2", +554 => x"3f800881", +555 => x"8f388008", +556 => x"5f751c77", +557 => x"77317f88", +558 => x"05087831", +559 => x"70618805", +560 => x"0c5d585c", +561 => x"7a802efe", +562 => x"ae387681", +563 => x"83387408", +564 => x"84160888", +565 => x"1757585c", +566 => x"76802ef2", +567 => x"3876538a", +568 => x"527b5182", +569 => x"d33f8008", +570 => x"7c318105", +571 => x"5d800884", +572 => x"3881175d", +573 => x"815f7c59", +574 => x"767d2783", +575 => x"38765994", +576 => x"1a08881b", +577 => x"08115758", +578 => x"807a085c", +579 => x"54901a08", +580 => x"7b278338", +581 => x"81547579", +582 => x"25843873", +583 => x"ba387779", +584 => x"24fee238", +585 => x"77537b52", +586 => x"9c1a0851", +587 => x"a41a0859", +588 => x"782d8008", +589 => x"56800880", +590 => x"24fee238", +591 => x"8c1a2280", +592 => x"c0075e7d", +593 => x"8c1b23ff", +594 => x"5574800c", +595 => x"903d0d04", +596 => x"7effa338", +597 => x"ff873975", +598 => x"537b527a", +599 => x"5182f93f", +600 => x"7908167a", +601 => x"0c79518e", +602 => x"b13f8008", +603 => x"cf387c76", +604 => x"315d7cfe", +605 => x"bc38feac", +606 => x"39901a08", +607 => x"7a087131", +608 => x"78117056", +609 => x"5a575280", +610 => x"cfe40851", +611 => x"84943f80", +612 => x"08802eff", +613 => x"a7388008", +614 => x"901b0c80", +615 => x"08167a0c", +616 => x"77941b0c", +617 => x"76881b0c", +618 => x"7656fd99", +619 => x"39790858", +620 => x"901a0878", +621 => x"27833881", +622 => x"54757727", +623 => x"843873b3", +624 => x"38941a08", +625 => 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x"00000000", +2626 => x"00000000", +2627 => x"00000000", +2628 => x"00000000", +2629 => x"00000000", +2630 => x"00000000", +2631 => x"00000000", +2632 => x"00000000", +2633 => x"00000000", +2634 => x"00000000", +2635 => x"00000000", +2636 => x"00000000", +2637 => x"00000000", +2638 => x"00000000", +2639 => x"00000000", +2640 => x"00000000", +2641 => x"00000000", +2642 => x"00000000", +2643 => x"00000000", +2644 => x"00000000", +2645 => x"00000000", +2646 => x"00000000", +2647 => x"00000000", +2648 => x"00000000", +2649 => x"00000000", +2650 => x"00000000", +2651 => x"00000000", +2652 => x"00000000", +2653 => x"00000000", +2654 => x"00000000", +2655 => x"00000000", +2656 => x"00000000", +2657 => x"00000000", +2658 => x"00000000", +2659 => x"00000000", +2660 => x"00000000", +2661 => x"00000000", +2662 => x"00000000", +2663 => x"00000000", +2664 => x"00000000", +2665 => x"00000000", +2666 => x"00000000", +2667 => x"00000000", +2668 => x"00000000", +2669 => x"00000000", +2670 => x"00000000", +2671 => x"00000000", +2672 => x"00000000", +2673 => x"00000000", +2674 => x"00000000", +2675 => x"00000000", +2676 => x"00000000", +2677 => x"00000000", +2678 => x"00000000", +2679 => x"00000000", +2680 => x"00000000", +2681 => x"00000000", +2682 => x"00000000", +2683 => x"00000000", +2684 => x"00000000", +2685 => x"00000000", +2686 => x"00000000", +2687 => x"00000000", +2688 => x"00000000", +2689 => x"00000000", +2690 => x"00000000", +2691 => x"00000000", +2692 => x"00000000", +2693 => x"00000000", +2694 => x"00000000", +2695 => x"00000000", +2696 => x"00000000", +2697 => x"00000000", +2698 => x"00000000", +2699 => x"00000000", +2700 => x"00000000", +2701 => x"00000000", +2702 => x"00000000", +2703 => x"00000000", +2704 => x"00000000", +2705 => x"00000000", +2706 => x"00000000", +2707 => x"00000000", +2708 => x"00000000", +2709 => x"00000000", +2710 => x"00000000", +2711 => x"00000000", +2712 => x"00000000", +2713 => x"00000000", +2714 => x"00000000", +2715 => x"00000000", +2716 => x"00000000", +2717 => x"00000000", +2718 => x"00000000", +2719 => x"00000000", +2720 => x"00000000", +2721 => x"00000000", +2722 => x"00000000", +2723 => x"00000000", +2724 => x"00000000", +2725 => x"00000000", +2726 => x"00000000", +2727 => x"00000000", +2728 => x"00000000", +2729 => x"00000000", +2730 => x"00000000", +2731 => x"00000000", +2732 => x"00000000", +2733 => x"00000000", +2734 => x"00000000", +2735 => x"00000000", +2736 => x"00000000", +2737 => x"00000000", +2738 => x"00000000", +2739 => x"00000000", +2740 => x"00000000", +2741 => x"00000000", +2742 => x"00000000", +2743 => x"00000000", +2744 => x"00000000", +2745 => x"00000000", +2746 => x"00000000", +2747 => x"00000000", +2748 => x"00000000", +2749 => x"00000000", +2750 => x"00000000", +2751 => x"00000000", +2752 => x"00000000", +2753 => x"00000000", +2754 => x"00000000", +2755 => x"00000000", +2756 => x"00000000", +2757 => x"00000000", +2758 => x"00000000", +2759 => x"00000000", +2760 => x"00000000", +2761 => x"00000000", +2762 => x"00000000", +2763 => x"00000000", +2764 => x"00000000", +2765 => x"00000000", +2766 => x"00000000", +2767 => x"00000000", +2768 => x"00000000", +2769 => x"00000000", +2770 => x"00000000", +2771 => x"00000000", +2772 => x"00000000", +2773 => x"00000000", +2774 => x"00000000", +2775 => x"00000000", +2776 => x"00000000", +2777 => x"00000000", +2778 => x"00000000", +2779 => x"00000000", +2780 => x"00000000", +2781 => x"00000000", +2782 => x"00000000", +2783 => x"00000000", +2784 => x"00000000", +2785 => x"00000000", +2786 => x"00000000", +2787 => x"00000000", +2788 => x"00000000", +2789 => x"ffffffff", +2790 => x"00000000", +2791 => x"00020000", +2792 => x"00000000", +2793 => x"00000000", +2794 => x"00002ba0", +2795 => x"00002ba0", +2796 => x"00002ba8", +2797 => x"00002ba8", +2798 => x"00002bb0", +2799 => x"00002bb0", +2800 => x"00002bb8", +2801 => x"00002bb8", +2802 => x"00002bc0", +2803 => x"00002bc0", +2804 => x"00002bc8", +2805 => x"00002bc8", +2806 => x"00002bd0", +2807 => x"00002bd0", +2808 => x"00002bd8", +2809 => x"00002bd8", +2810 => x"00002be0", +2811 => x"00002be0", +2812 => x"00002be8", +2813 => x"00002be8", +2814 => x"00002bf0", +2815 => x"00002bf0", +2816 => x"00002bf8", +2817 => x"00002bf8", +2818 => x"00002c00", +2819 => x"00002c00", +2820 => x"00002c08", +2821 => x"00002c08", +2822 => x"00002c10", +2823 => x"00002c10", +2824 => x"00002c18", +2825 => x"00002c18", +2826 => x"00002c20", +2827 => x"00002c20", +2828 => x"00002c28", +2829 => x"00002c28", +2830 => x"00002c30", +2831 => x"00002c30", +2832 => x"00002c38", +2833 => x"00002c38", +2834 => x"00002c40", +2835 => x"00002c40", +2836 => x"00002c48", +2837 => x"00002c48", +2838 => x"00002c50", +2839 => x"00002c50", +2840 => x"00002c58", +2841 => x"00002c58", +2842 => x"00002c60", +2843 => x"00002c60", +2844 => x"00002c68", +2845 => x"00002c68", +2846 => x"00002c70", +2847 => x"00002c70", +2848 => x"00002c78", +2849 => x"00002c78", +2850 => x"00002c80", +2851 => x"00002c80", +2852 => x"00002c88", +2853 => x"00002c88", +2854 => x"00002c90", +2855 => x"00002c90", +2856 => x"00002c98", +2857 => x"00002c98", +2858 => x"00002ca0", +2859 => x"00002ca0", +2860 => x"00002ca8", +2861 => x"00002ca8", +2862 => x"00002cb0", +2863 => x"00002cb0", +2864 => x"00002cb8", +2865 => x"00002cb8", +2866 => x"00002cc0", +2867 => x"00002cc0", +2868 => x"00002cc8", +2869 => x"00002cc8", +2870 => x"00002cd0", +2871 => x"00002cd0", +2872 => x"00002cd8", +2873 => x"00002cd8", +2874 => x"00002ce0", +2875 => x"00002ce0", +2876 => x"00002ce8", +2877 => x"00002ce8", +2878 => x"00002cf0", +2879 => x"00002cf0", +2880 => x"00002cf8", +2881 => x"00002cf8", +2882 => x"00002d00", +2883 => x"00002d00", +2884 => x"00002d08", +2885 => x"00002d08", +2886 => x"00002d10", +2887 => x"00002d10", +2888 => x"00002d18", +2889 => x"00002d18", +2890 => x"00002d20", +2891 => x"00002d20", +2892 => x"00002d28", +2893 => x"00002d28", +2894 => x"00002d30", +2895 => x"00002d30", +2896 => x"00002d38", +2897 => x"00002d38", +2898 => x"00002d40", +2899 => x"00002d40", +2900 => x"00002d48", +2901 => x"00002d48", +2902 => x"00002d50", +2903 => x"00002d50", +2904 => x"00002d58", +2905 => x"00002d58", +2906 => x"00002d60", +2907 => x"00002d60", +2908 => x"00002d68", +2909 => x"00002d68", +2910 => x"00002d70", +2911 => x"00002d70", +2912 => x"00002d78", +2913 => x"00002d78", +2914 => x"00002d80", +2915 => x"00002d80", +2916 => x"00002d88", +2917 => x"00002d88", +2918 => x"00002d90", +2919 => x"00002d90", +2920 => x"00002d98", +2921 => x"00002d98", +2922 => x"00002da0", +2923 => x"00002da0", +2924 => x"00002da8", +2925 => x"00002da8", +2926 => x"00002db0", +2927 => x"00002db0", +2928 => x"00002db8", +2929 => x"00002db8", +2930 => x"00002dc0", +2931 => x"00002dc0", +2932 => x"00002dc8", +2933 => x"00002dc8", +2934 => x"00002dd0", +2935 => x"00002dd0", +2936 => x"00002dd8", +2937 => x"00002dd8", +2938 => x"00002de0", +2939 => x"00002de0", +2940 => x"00002de8", +2941 => x"00002de8", +2942 => x"00002df0", +2943 => x"00002df0", +2944 => x"00002df8", +2945 => x"00002df8", +2946 => x"00002e00", +2947 => x"00002e00", +2948 => x"00002e08", +2949 => x"00002e08", +2950 => x"00002e10", +2951 => x"00002e10", +2952 => x"00002e18", +2953 => x"00002e18", +2954 => x"00002e20", +2955 => x"00002e20", +2956 => x"00002e28", +2957 => x"00002e28", +2958 => x"00002e30", +2959 => x"00002e30", +2960 => x"00002e38", +2961 => x"00002e38", +2962 => x"00002e40", +2963 => x"00002e40", +2964 => x"00002e48", +2965 => x"00002e48", +2966 => x"00002e50", +2967 => x"00002e50", +2968 => x"00002e58", +2969 => x"00002e58", +2970 => x"00002e60", +2971 => x"00002e60", +2972 => x"00002e68", +2973 => x"00002e68", +2974 => x"00002e70", +2975 => x"00002e70", +2976 => x"00002e78", +2977 => x"00002e78", +2978 => x"00002e80", +2979 => x"00002e80", +2980 => x"00002e88", +2981 => x"00002e88", +2982 => x"00002e90", +2983 => x"00002e90", +2984 => x"00002e98", +2985 => x"00002e98", +2986 => x"00002ea0", +2987 => x"00002ea0", +2988 => x"00002ea8", +2989 => x"00002ea8", +2990 => x"00002eb0", +2991 => x"00002eb0", +2992 => x"00002eb8", +2993 => x"00002eb8", +2994 => x"00002ec0", +2995 => x"00002ec0", +2996 => x"00002ec8", +2997 => x"00002ec8", +2998 => x"00002ed0", +2999 => x"00002ed0", +3000 => x"00002ed8", +3001 => x"00002ed8", +3002 => x"00002ee0", +3003 => x"00002ee0", +3004 => x"00002ee8", +3005 => x"00002ee8", +3006 => x"00002ef0", +3007 => x"00002ef0", +3008 => x"00002ef8", +3009 => x"00002ef8", +3010 => x"00002f00", +3011 => x"00002f00", +3012 => x"00002f08", +3013 => x"00002f08", +3014 => x"00002f10", +3015 => x"00002f10", +3016 => x"00002f18", +3017 => x"00002f18", +3018 => x"00002f20", +3019 => x"00002f20", +3020 => x"00002f28", +3021 => x"00002f28", +3022 => x"00002f30", +3023 => x"00002f30", +3024 => x"00002f38", +3025 => x"00002f38", +3026 => x"00002f40", +3027 => x"00002f40", +3028 => x"00002f48", +3029 => x"00002f48", +3030 => x"00002f50", +3031 => x"00002f50", +3032 => x"00002f58", +3033 => x"00002f58", +3034 => x"00002f60", +3035 => x"00002f60", +3036 => x"00002f68", +3037 => x"00002f68", +3038 => x"00002f70", +3039 => x"00002f70", +3040 => x"00002f78", +3041 => x"00002f78", +3042 => x"00002f80", +3043 => x"00002f80", +3044 => x"00002f88", +3045 => x"00002f88", +3046 => x"00002f90", +3047 => x"00002f90", +3048 => x"00002f98", +3049 => x"00002f98", +3050 => x"000027b8", +3051 => x"ffffffff", +3052 => x"00000000", +3053 => x"ffffffff", +3054 => x"00000000", + others => x"00000000" +); + +begin + +mem_busy<=mem_readEnable; -- we're done on the cycle after we serve the read request + +process (clk, areset) +begin + if areset = '1' then + elsif (clk'event and clk = '1') then + if (mem_writeEnable = '1') then + ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit)))) := mem_write; + end if; + if (mem_readEnable = '1') then + mem_read <= ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit)))); + end if; + end if; +end process; + + + + +end dram_arch; diff --git a/zpu/hdl/example_medium/simzpu_medium.do b/zpu/hdl/example_medium/simzpu_medium.do index a6c1fe2..2b77ba6 100644 --- a/zpu/hdl/example_medium/simzpu_medium.do +++ b/zpu/hdl/example_medium/simzpu_medium.do @@ -1,20 +1,20 @@ # Xilinx WebPack modelsim script # -# cd C:/workspace/zpu/zpu/hdl/zpu4/src +# cd C:/workspace/zpu/zpu/hdl/example_medium # do simzpu_medium.do set BreakOnAssertion 1 vlib work vcom -93 -explicit zpu_config_trace.vhd -vcom -93 -explicit zpupkg.vhd -vcom -93 -explicit txt_util.vhd +vcom -93 -explicit ../zpu4/core/zpupkg.vhd +vcom -93 -explicit ../zpu4/src/txt_util.vhd vcom -93 -explicit sim_fpga_top.vhd -vcom -93 -explicit zpu_core.vhd +vcom -93 -explicit ../zpu4/core/zpu_core.vhd vcom -93 -explicit dram_hello.vhd -vcom -93 -explicit timer.vhd -vcom -93 -explicit io.vhd -vcom -93 -explicit trace.vhd +vcom -93 -explicit ../zpu4/src/timer.vhd +vcom -93 -explicit ../zpu4/src/io.vhd +vcom -93 -explicit ../zpu4/src/trace.vhd # run ZPU vsim fpga_top diff --git a/zpu/hdl/example_medium/zpu_config_trace.vhd b/zpu/hdl/example_medium/zpu_config_trace.vhd new file mode 100644 index 0000000..d765d9a --- /dev/null +++ b/zpu/hdl/example_medium/zpu_config_trace.vhd @@ -0,0 +1,17 @@ +library ieee; +use ieee.std_logic_1164.all; + +package zpu_config is + + constant Generate_Trace : boolean := true; + constant wordPower : integer := 5; + -- during simulation, set this to '0' to get matching trace.txt + constant DontCareValue : std_logic := '0'; + -- Clock frequency in MHz. + constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64"; + constant maxAddrBitIncIO : integer := 27; + constant maxAddrBitDRAM : integer := 16; + constant maxAddrBitBRAM : integer := 16; + constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"001fff8"; + +end zpu_config; diff --git a/zpu/hdl/index.html b/zpu/hdl/index.html index d5bc256..e206113 100644 --- a/zpu/hdl/index.html +++ b/zpu/hdl/index.html @@ -4,8 +4,9 @@ The simplest version of the ZPU uses BRAM. When getting accustomed to the ZPU, a BRAM ZPU with a UART is a good place to start.

      -You'll find a working simulation script in hdl/example/simzpu_small.do and hdl/zpu4/src/simzpu_medium.do, which -show simulation of the small(zpu_core_small.vhd) and medium sized ZPU(zpu_core.vhd). +You'll find a working simulation script in hdl/example/simzpu_small.do and hdl/example_medium/simzpu_medium.do, which +show simulation of the small(zpu_core_small.vhd) and medium sized ZPU(zpu_core.vhd). hdl/example/simzpu_interrupt.do +shows use of interrupts.

      When implementing the ZPU, copy the following files and modify them to your needs:

        diff --git a/zpu/hdl/zpu4/core/zpu_core_small.vhd b/zpu/hdl/zpu4/core/zpu_core_small.vhd index 9cda01c..03526bd 100644 --- a/zpu/hdl/zpu4/core/zpu_core_small.vhd +++ b/zpu/hdl/zpu4/core/zpu_core_small.vhd @@ -81,7 +81,9 @@ State_FetchNext, State_AddSP, State_ReadIODone, State_Decode, -State_Resync +State_Resync, +State_Interrupt + ); type DecodedOpcodeType is @@ -103,7 +105,8 @@ Decoded_Load, Decoded_Not, Decoded_Flip, Decoded_Store, -Decoded_PopSP +Decoded_PopSP, +Decoded_Interrupt ); @@ -125,11 +128,15 @@ signal memBAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); signal memBWrite_stdlogic : std_logic_vector(memBWrite'range); signal memBRead_stdlogic : std_logic_vector(memBRead'range); --- debug -subtype index is integer range 0 to 3; -signal tOpcode_sel : index; - - +subtype index is integer range 0 to 3; + +signal tOpcode_sel : index; + + +signal inInterrupt : std_logic; + + + begin traceFileGenerate: if Generate_Trace generate @@ -146,8 +153,13 @@ begin ); end generate; - -- not used in this design - mem_writeMask <= (others => '1'); + + + -- not used in this design + + mem_writeMask <= (others => '1'); + + memAAddr_stdlogic <= std_logic_vector(memAAddr(AddrBitBRAM_range)); memAWrite_stdlogic <= std_logic_vector(memAWrite); @@ -167,23 +179,31 @@ begin memARead <= unsigned(memARead_stdlogic); memBRead <= unsigned(memBRead_stdlogic); -tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0)); + + + tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0)); + decodeControl: - process(memBRead, pc,tOpcode_sel) + process(memBRead, pc,tOpcode_sel) variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); begin - -- not worked with synopsys - -- tOpcode := std_logic_vector(memBRead((wordBytes-1-to_integer(pc(minAddrBit-1 downto 0))+1)*8-1 downto (wordBytes-1-to_integer(pc(minAddrBit-1 downto 0)))*8)); - -- use full case - case (tOpcode_sel) is - when 0 => tOpcode := std_logic_vector(memBRead(31 downto 24)); - when 1 => tOpcode := std_logic_vector(memBRead(23 downto 16)); - when 2 => tOpcode := std_logic_vector(memBRead(15 downto 8)); - when 3 => tOpcode := std_logic_vector(memBRead(7 downto 0)); - when others => tOpcode := std_logic_vector(memBRead(7 downto 0)); - end case; + + -- simplify opcode selection a bit so it passes more synthesizers + case (tOpcode_sel) is + + when 0 => tOpcode := std_logic_vector(memBRead(31 downto 24)); + + when 1 => tOpcode := std_logic_vector(memBRead(23 downto 16)); + + when 2 => tOpcode := std_logic_vector(memBRead(15 downto 8)); + + when 3 => tOpcode := std_logic_vector(memBRead(7 downto 0)); + + when others => tOpcode := std_logic_vector(memBRead(7 downto 0)); + end case; + sampledOpcode <= tOpcode; if (tOpcode(7 downto 7)=OpCode_Im) then @@ -246,13 +266,12 @@ tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0)); out_mem_readEnable <= '0'; memAWrite <= (others => '0'); memBWrite <= (others => '0'); - -- avoid Latch in synopsys - -- mem_writeMask <= (others => '1'); + inInterrupt <= '0'; elsif (clk'event and clk = '1') then memAWriteEnable <= '0'; memBWriteEnable <= '0'; -- This saves ca. 100 LUT's, by explicitly declaring that the - -- memAWrite can be left at whatever value if memAWriteEnable is + -- memAWrite can be left at whatever value if memAWriteEnable is -- not set. memAWrite <= (others => DontCareValue); memBWrite <= (others => DontCareValue); @@ -270,6 +289,9 @@ tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0)); decodedOpcode <= sampledDecodedOpcode; opcode <= sampledOpcode; + if interrupt='0' then + inInterrupt <= '0'; -- no longer in an interrupt + end if; case state is when State_Execute => @@ -295,6 +317,14 @@ tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0)); idim_flag <= '0'; case decodedOpcode is + when Decoded_Interrupt => + sp <= sp - 1; + memAAddr <= sp - 1; + memAWriteEnable <= '1'; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto 0) <= pc; + pc <= to_unsigned(32, maxAddrBit+1); -- interrupt address + report "ZPU jumped to interrupt!" severity note; when Decoded_Im => idim_flag <= '1'; memAWriteEnable <= '1'; @@ -422,6 +452,11 @@ tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0)); memBAddr <= sp + 1; state <= State_Decode; when State_Decode => + if interrupt='1' and inInterrupt='0' and idim_flag='0' then + -- We got an interrupt, execute interrupt instead of next instruction + inInterrupt <= '1'; + decodedOpcode <= Decoded_Interrupt; + end if; -- during the State_Execute cycle we'll be fetching SP+1 memAAddr <= sp; memBAddr <= sp + 1; diff --git a/zpu/hdl/zpu4/core/zpu_core_small_wip.vhd b/zpu/hdl/zpu4/core/zpu_core_small_wip.vhd deleted file mode 100644 index a169103..0000000 --- a/zpu/hdl/zpu4/core/zpu_core_small_wip.vhd +++ /dev/null @@ -1,498 +0,0 @@ --- Company: ZPU3 --- Engineer: Øyvind Harboe - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use ieee.numeric_std.all; - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - - -entity zpu_core is - Port ( clk : in std_logic; - areset : in std_logic; - enable : in std_logic; - in_mem_busy : in std_logic; - mem_read : in std_logic_vector(wordSize-1 downto 0); - mem_write : out std_logic_vector(wordSize-1 downto 0); - out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); - out_mem_writeEnable : out std_logic; - out_mem_readEnable : out std_logic; - mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); - interrupt : in std_logic; - break : out std_logic); -end zpu_core; - -architecture behave of zpu_core is - -signal readIO : std_logic; - - - -signal memAWriteEnable : std_logic; -signal memAAddr : unsigned(maxAddrBit downto minAddrBit); -signal memAWrite : unsigned(wordSize-1 downto 0); -signal memARead : unsigned(wordSize-1 downto 0); -signal memBWriteEnable : std_logic; -signal memBAddr : unsigned(maxAddrBit downto minAddrBit); -signal memBWrite : unsigned(wordSize-1 downto 0); -signal memBRead : unsigned(wordSize-1 downto 0); - - - -signal pc : unsigned(maxAddrBit downto 0); -signal sp : unsigned(maxAddrBit downto minAddrBit); - -signal idim_flag : std_logic; - ---signal storeToStack : std_logic; ---signal fetchNextInstruction : std_logic; ---signal extraCycle : std_logic; -signal busy : std_logic; ---signal fetching : std_logic; - -signal begin_inst : std_logic; - - - -signal trace_opcode : std_logic_vector(7 downto 0); -signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); -signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); -signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); - --- state machine. -type State_Type is -( -State_Fetch, -State_WriteIODone, -State_Execute, -State_StoreToStack, -State_Add, -State_Or, -State_And, -State_Store, -State_ReadIO, -State_WriteIO, -State_Load, -State_FetchNext, -State_AddSP, -State_ReadIODone, -State_Decode, -State_Resync, -State_Interrupt - -); - -type DecodedOpcodeType is -( -Decoded_Nop, -Decoded_Im, -Decoded_ImShift, -Decoded_LoadSP, -Decoded_StoreSP , -Decoded_AddSP, -Decoded_Emulate, -Decoded_Break, -Decoded_PushSP, -Decoded_PopPC, -Decoded_Add, -Decoded_Or, -Decoded_And, -Decoded_Load, -Decoded_Not, -Decoded_Flip, -Decoded_Store, -Decoded_PopSP -); - - - -signal sampledOpcode : std_logic_vector(OpCode_Size-1 downto 0); -signal opcode : std_logic_vector(OpCode_Size-1 downto 0); - -signal decodedOpcode : DecodedOpcodeType; -signal sampledDecodedOpcode : DecodedOpcodeType; - - -signal state : State_Type; - -subtype AddrBitBRAM_range is natural range maxAddrBitBRAM downto minAddrBit; -signal memAAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); -signal memAWrite_stdlogic : std_logic_vector(memAWrite'range); -signal memARead_stdlogic : std_logic_vector(memARead'range); -signal memBAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); -signal memBWrite_stdlogic : std_logic_vector(memBWrite'range); -signal memBRead_stdlogic : std_logic_vector(memBRead'range); - -subtype index is integer range 0 to 3; - -signal tOpcode_sel : index; - - -signal inInterrupt : std_logic; - - - -begin - traceFileGenerate: - if Generate_Trace generate - trace_file: trace port map ( - clk => clk, - begin_inst => begin_inst, - pc => trace_pc, - opcode => trace_opcode, - sp => trace_sp, - memA => trace_topOfStack, - memB => trace_topOfStackB, - busy => busy, - intsp => (others => 'U') - ); - end generate; - - - - -- not used in this design - - mem_writeMask <= (others => '1'); - - - - memAAddr_stdlogic <= std_logic_vector(memAAddr(AddrBitBRAM_range)); - memAWrite_stdlogic <= std_logic_vector(memAWrite); - memBAddr_stdlogic <= std_logic_vector(memBAddr(AddrBitBRAM_range)); - memBWrite_stdlogic <= std_logic_vector(memBWrite); - memory: dualport_ram port map ( - clk => clk, - memAWriteEnable => memAWriteEnable, - memAAddr => memAAddr_stdlogic, - memAWrite => memAWrite_stdlogic, - memARead => memARead_stdlogic, - memBWriteEnable => memBWriteEnable, - memBAddr => memBAddr_stdlogic, - memBWrite => memBWrite_stdlogic, - memBRead => memBRead_stdlogic - ); - memARead <= unsigned(memARead_stdlogic); - memBRead <= unsigned(memBRead_stdlogic); - - - - tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0)); - - - - decodeControl: - process(memBRead, pc,tOpcode_sel) - variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); - begin - - -- simplify opcode selection a bit so it passes more synthesizers - case (tOpcode_sel) is - - when 0 => tOpcode := std_logic_vector(memBRead(31 downto 24)); - - when 1 => tOpcode := std_logic_vector(memBRead(23 downto 16)); - - when 2 => tOpcode := std_logic_vector(memBRead(15 downto 8)); - - when 3 => tOpcode := std_logic_vector(memBRead(7 downto 0)); - - when others => tOpcode := std_logic_vector(memBRead(7 downto 0)); - end case; - - sampledOpcode <= tOpcode; - - if (tOpcode(7 downto 7)=OpCode_Im) then - sampledDecodedOpcode<=Decoded_Im; - elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then - sampledDecodedOpcode<=Decoded_StoreSP; - elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then - sampledDecodedOpcode<=Decoded_LoadSP; - elsif (tOpcode(7 downto 5)=OpCode_Emulate) then - sampledDecodedOpcode<=Decoded_Emulate; - elsif (tOpcode(7 downto 4)=OpCode_AddSP) then - sampledDecodedOpcode<=Decoded_AddSP; - else - case tOpcode(3 downto 0) is - when OpCode_Break => - sampledDecodedOpcode<=Decoded_Break; - when OpCode_PushSP => - sampledDecodedOpcode<=Decoded_PushSP; - when OpCode_PopPC => - sampledDecodedOpcode<=Decoded_PopPC; - when OpCode_Add => - sampledDecodedOpcode<=Decoded_Add; - when OpCode_Or => - sampledDecodedOpcode<=Decoded_Or; - when OpCode_And => - sampledDecodedOpcode<=Decoded_And; - when OpCode_Load => - sampledDecodedOpcode<=Decoded_Load; - when OpCode_Not => - sampledDecodedOpcode<=Decoded_Not; - when OpCode_Flip => - sampledDecodedOpcode<=Decoded_Flip; - when OpCode_Store => - sampledDecodedOpcode<=Decoded_Store; - when OpCode_PopSP => - sampledDecodedOpcode<=Decoded_PopSP; - when others => - sampledDecodedOpcode<=Decoded_Nop; - end case; - end if; - end process; - - - opcodeControl: - process(clk, areset) - variable spOffset : unsigned(4 downto 0); - begin - if areset = '1' then - state <= State_Resync; - break <= '0'; - sp <= unsigned(spStart(maxAddrBit downto minAddrBit)); - pc <= (others => '0'); - idim_flag <= '0'; - begin_inst <= '0'; - memAAddr <= (others => '0'); - memBAddr <= (others => '0'); - memAWriteEnable <= '0'; - memBWriteEnable <= '0'; - out_mem_writeEnable <= '0'; - out_mem_readEnable <= '0'; - memAWrite <= (others => '0'); - memBWrite <= (others => '0'); - inInterrupt <= '0'; - elsif (clk'event and clk = '1') then - memAWriteEnable <= '0'; - memBWriteEnable <= '0'; - -- This saves ca. 100 LUT's, by explicitly declaring that the - -- memAWrite can be left at whatever value if memAWriteEnable is - -- not set. - memAWrite <= (others => DontCareValue); - memBWrite <= (others => DontCareValue); --- out_mem_addr <= (others => DontCareValue); --- mem_write <= (others => DontCareValue); - spOffset := (others => DontCareValue); - memAAddr <= (others => DontCareValue); - memBAddr <= (others => DontCareValue); - - out_mem_writeEnable <= '0'; - out_mem_readEnable <= '0'; - begin_inst <= '0'; - out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); - mem_write <= std_logic_vector(memBRead); - - decodedOpcode <= sampledDecodedOpcode; - opcode <= sampledOpcode; - if interrupt='0' then - inInterrupt <= '0'; -- no longer in an interrupt - end if; - - case state is - when State_Execute => - state <= State_Fetch; - -- at this point: - -- memBRead contains opcode word - -- memARead contains top of stack - pc <= pc + 1; - - -- trace - begin_inst <= '1'; - trace_pc <= (others => '0'); - trace_pc(maxAddrBit downto 0) <= std_logic_vector(pc); - trace_opcode <= opcode; - trace_sp <= (others => '0'); - trace_sp(maxAddrBit downto minAddrBit) <= std_logic_vector(sp); - trace_topOfStack <= std_logic_vector(memARead); - trace_topOfStackB <= std_logic_vector(memBRead); - - -- during the next cycle we'll be reading the next opcode - spOffset(4):=not opcode(4); - spOffset(3 downto 0) := unsigned(opcode(3 downto 0)); - - idim_flag <= '0'; - case decodedOpcode is - when Decoded_Interrupt => - sp <= sp - 1; - memAAddr <= sp - 1; - memAWriteEnable <= '1'; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBitIncIO downto 0) <= pc; - pc <= conv_std_logic_vector(32, maxAddrBitIncIo+1); -- interrupt address - report "ZPU jumped to interrupt!" severity note; - when Decoded_Im => - idim_flag <= '1'; - memAWriteEnable <= '1'; - if (idim_flag='0') then - sp <= sp - 1; - memAAddr <= sp-1; - for i in wordSize-1 downto 7 loop - memAWrite(i) <= opcode(6); - end loop; - memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); - else - memAAddr <= sp; - memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0); - memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); - end if; - when Decoded_StoreSP => - memBWriteEnable <= '1'; - memBAddr <= sp+spOffset; - memBWrite <= memARead; - sp <= sp + 1; - state <= State_Resync; - when Decoded_LoadSP => - sp <= sp - 1; - memAAddr <= sp+spOffset; - when Decoded_Emulate => - sp <= sp - 1; - memAWriteEnable <= '1'; - memAAddr <= sp - 1; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto 0) <= pc + 1; - -- The emulate address is: - -- 98 7654 3210 - -- 0000 00aa aaa0 0000 - pc <= (others => '0'); - pc(9 downto 5) <= unsigned(opcode(4 downto 0)); - when Decoded_AddSP => - memAAddr <= sp; - memBAddr <= sp+spOffset; - state <= State_AddSP; - when Decoded_Break => - report "Break instruction encountered" severity failure; - break <= '1'; - when Decoded_PushSP => - memAWriteEnable <= '1'; - memAAddr <= sp - 1; - sp <= sp - 1; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto minAddrBit) <= sp; - when Decoded_PopPC => - pc <= memARead(maxAddrBit downto 0); - sp <= sp + 1; - state <= State_Resync; - when Decoded_Add => - sp <= sp + 1; - state <= State_Add; - when Decoded_Or => - sp <= sp + 1; - state <= State_Or; - when Decoded_And => - sp <= sp + 1; - state <= State_And; - when Decoded_Load => - if (memARead(ioBit)='1') then - out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); - out_mem_readEnable <= '1'; - state <= State_ReadIO; - else - memAAddr <= memARead(maxAddrBit downto minAddrBit); - end if; - when Decoded_Not => - memAAddr <= sp(maxAddrBit downto minAddrBit); - memAWriteEnable <= '1'; - memAWrite <= not memARead; - when Decoded_Flip => - memAAddr <= sp(maxAddrBit downto minAddrBit); - memAWriteEnable <= '1'; - for i in 0 to wordSize-1 loop - memAWrite(i) <= memARead(wordSize-1-i); - end loop; - when Decoded_Store => - memBAddr <= sp + 1; - sp <= sp + 1; - if (memARead(ioBit)='1') then - state <= State_WriteIO; - else - state <= State_Store; - end if; - when Decoded_PopSP => - sp <= memARead(maxAddrBit downto minAddrBit); - state <= State_Resync; - when Decoded_Nop => - memAAddr <= sp; - when others => - null; - end case; - when State_ReadIO => - if (in_mem_busy = '0') then - state <= State_Fetch; - memAWriteEnable <= '1'; - memAWrite <= unsigned(mem_read); - end if; - when State_WriteIO => - sp <= sp + 1; - out_mem_writeEnable <= '1'; - out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); - mem_write <= std_logic_vector(memBRead); - state <= State_WriteIODone; - when State_WriteIODone => - if (in_mem_busy = '0') then - state <= State_Resync; - end if; - when State_Fetch => - -- We need to resync. During the *next* cycle - -- we'll fetch the opcode @ pc and thus it will - -- be available for State_Execute the cycle after - -- next - memBAddr <= pc(maxAddrBit downto minAddrBit); - state <= State_FetchNext; - when State_FetchNext => - -- at this point memARead contains the value that is either - -- from the top of stack or should be copied to the top of the stack - memAWriteEnable <= '1'; - memAWrite <= memARead; - memAAddr <= sp; - memBAddr <= sp + 1; - state <= State_Decode; - when State_Decode => - if interrupt='1' and inInterrupt='0' and idim_flag='0' then - -- We got an interrupt, execute interrupt instead of next instruction - inInterrupt <= '1'; - decodedOpcode <= Decoded_Interrupt; - end if; - -- during the State_Execute cycle we'll be fetching SP+1 - memAAddr <= sp; - memBAddr <= sp + 1; - state <= State_Execute; - when State_Store => - sp <= sp + 1; - memAWriteEnable <= '1'; - memAAddr <= memARead(maxAddrBit downto minAddrBit); - memAWrite <= memBRead; - state <= State_Resync; - when State_AddSP => - state <= State_Add; - when State_Add => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead + memBRead; - state <= State_Fetch; - when State_Or => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead or memBRead; - state <= State_Fetch; - when State_Resync => - memAAddr <= sp; - state <= State_Fetch; - when State_And => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead and memBRead; - state <= State_Fetch; - when others => - null; - end case; - - end if; - end process; - - - -end behave; diff --git a/zpu/hdl/zpu4/src/bram.vhd b/zpu/hdl/zpu4/src/bram.vhd deleted file mode 100644 index 435f3f4..0000000 --- a/zpu/hdl/zpu4/src/bram.vhd +++ /dev/null @@ -1,3807 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - - -library zylin; -use zylin.zpu_config.all; -use zylin.zpupkg.all; - -entity dram is -port (clk : in std_logic; - areset : in std_logic; - mem_writeEnable : in std_logic; - mem_readEnable : in std_logic; - mem_addr : in std_logic_vector(maxAddrBit downto 0); - mem_write : in std_logic_vector(wordSize-1 downto 0); - mem_read : out std_logic_vector(wordSize-1 downto 0); - mem_busy : out std_logic; - mem_writeMask : in std_logic_vector(wordBytes-1 downto 0)); -end dram; - -architecture dram_arch of dram is - -type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); - -shared variable ram : ram_type := -( -0 => x"800b0b0b", -1 => x"0b0b8070", -2 => x"0b0b80e5", -3 => x"d00c3a0b", -4 => x"0b0bbed7", -5 => x"04000000", -6 => x"00000000", -7 => x"00000000", -8 => x"80088408", -9 => x"88080b0b", -10 => x"0bbfa72d", -11 => x"880c840c", -12 => x"800c0400", -13 => x"00000000", -14 => x"00000000", -15 => x"00000000", -16 => x"71fd0608", -17 => x"72830609", -18 => x"81058205", -19 => x"832b2a83", -20 => x"ffff0652", -21 => x"0b0b0400", -22 => x"00000000", -23 => x"00000000", -24 => x"71fd0608", -25 => x"83ffff73", -26 => x"83060981", -27 => x"05820583", -28 => x"2b2b0906", -29 => x"7383ffff", -30 => x"0b0b0b0b", -31 => x"83a70400", -32 => x"72098105", -33 => x"72057373", -34 => x"09060906", -35 => x"73097306", -36 => x"070a8106", -37 => x"530b0b51", -38 => x"04000000", -39 => x"00000000", -40 => x"72722473", -41 => x"732e0753", -42 => x"0b0b5104", -43 => x"00000000", -44 => x"00000000", -45 => x"00000000", -46 => x"00000000", -47 => x"00000000", -48 => x"71737109", -49 => x"71068106", -50 => x"30720a10", -51 => x"0a720a10", -52 => x"0a31050a", -53 => x"81065151", -54 => x"530b0b51", -55 => x"04000000", -56 => x"72722673", -57 => x"732e0753", -58 => x"0b0b5104", -59 => x"00000000", -60 => x"00000000", -61 => x"00000000", -62 => x"00000000", -63 => x"00000000", -64 => x"00000000", -65 => x"00000000", -66 => x"00000000", -67 => x"00000000", -68 => x"00000000", -69 => x"00000000", -70 => x"00000000", -71 => x"00000000", -72 => x"0b0b0b88", -73 => x"c6040000", -74 => x"00000000", -75 => x"00000000", -76 => x"00000000", -77 => x"00000000", -78 => x"00000000", -79 => x"00000000", -80 => x"720a722b", -81 => x"0a530b0b", -82 => x"51040000", -83 => x"00000000", -84 => x"00000000", -85 => x"00000000", -86 => x"00000000", -87 => x"00000000", -88 => x"72729f06", -89 => x"0981050b", -90 => x"0b0b88a7", -91 => x"05040000", -92 => x"00000000", -93 => x"00000000", -94 => x"00000000", -95 => x"00000000", -96 => x"72722aff", -97 => x"739f062a", -98 => x"0974090a", -99 => x"8106ff05", -100 => x"0607530b", -101 => x"0b510400", -102 => x"00000000", -103 => x"00000000", -104 => x"7171530b", -105 => x"0b510406", -106 => x"73830609", -107 => x"81058205", -108 => x"832b0b2b", -109 => x"0772fc06", -110 => x"0c515104", -111 => x"00000000", -112 => x"72098105", -113 => x"72050970", -114 => x"81050906", -115 => x"0a810653", -116 => x"0b0b5104", -117 => x"00000000", -118 => x"00000000", -119 => x"00000000", -120 => x"72098105", -121 => x"72050970", -122 => x"81050906", -123 => x"0a098106", -124 => x"530b0b51", -125 => x"04000000", -126 => x"00000000", -127 => x"00000000", -128 => x"71098105", -129 => x"520b0b04", -130 => x"00000000", -131 => x"00000000", -132 => x"00000000", -133 => x"00000000", -134 => x"00000000", -135 => x"00000000", -136 => x"72720981", -137 => x"0505530b", -138 => x"0b510400", -139 => x"00000000", -140 => x"00000000", -141 => x"00000000", -142 => x"00000000", -143 => x"00000000", -144 => x"72097206", -145 => x"73730906", -146 => x"07530b0b", -147 => x"51040000", -148 => x"00000000", -149 => x"00000000", -150 => x"00000000", -151 => x"00000000", -152 => x"71fc0608", -153 => x"72830609", -154 => x"81058305", -155 => x"1010102a", -156 => x"81ff0652", -157 => x"0b0b0400", -158 => x"00000000", -159 => x"00000000", -160 => x"71fc0608", -161 => x"0b0b80e5", -162 => x"bc738306", -163 => x"10100508", -164 => x"060b0b0b", -165 => x"88ac0400", -166 => x"00000000", -167 => x"00000000", -168 => x"80088408", -169 => x"88087575", -170 => x"0b0b0ba3", -171 => x"fa2d5050", -172 => x"80085688", -173 => x"0c840c80", -174 => x"0c510400", -175 => x"00000000", -176 => x"80088408", -177 => x"88087575", -178 => x"0b0b0ba4", -179 => x"ca2d5050", -180 => x"80085688", -181 => x"0c840c80", -182 => x"0c510400", -183 => x"00000000", -184 => x"72097081", -185 => x"0509060a", -186 => x"8106ff05", -187 => x"70540b0b", -188 => x"71067309", -189 => x"727405ff", -190 => x"05060751", -191 => x"51510400", -192 => x"72097081", -193 => x"0509060a", -194 => x"098106ff", -195 => x"0570540b", -196 => x"0b710673", -197 => x"09727405", -198 => x"ff050607", -199 => x"51515104", -200 => x"05ff0504", -201 => x"00000000", -202 => x"00000000", -203 => x"00000000", -204 => x"00000000", -205 => x"00000000", -206 => x"00000000", -207 => x"00000000", -208 => x"810b0b0b", -209 => x"80e5cc0c", -210 => x"51040000", -211 => x"00000000", -212 => x"00000000", -213 => x"00000000", -214 => x"00000000", -215 => x"00000000", -216 => x"71810552", -217 => x"0b0b0400", -218 => x"00000000", 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x"04040404", -3186 => x"04040404", -3187 => x"05050505", -3188 => x"05050505", -3189 => x"05050505", -3190 => x"05050505", -3191 => x"06060606", -3192 => x"06060606", -3193 => x"06060606", -3194 => x"06060606", -3195 => x"06060606", -3196 => x"06060606", -3197 => x"06060606", -3198 => x"06060606", -3199 => x"07070707", -3200 => x"07070707", -3201 => x"07070707", -3202 => x"07070707", -3203 => x"07070707", -3204 => x"07070707", -3205 => x"07070707", -3206 => x"07070707", -3207 => x"07070707", -3208 => x"07070707", -3209 => x"07070707", -3210 => x"07070707", -3211 => x"07070707", -3212 => x"07070707", -3213 => x"07070707", -3214 => x"07070707", -3215 => x"08080808", -3216 => x"08080808", -3217 => x"08080808", -3218 => x"08080808", -3219 => x"08080808", -3220 => x"08080808", -3221 => x"08080808", -3222 => x"08080808", -3223 => x"08080808", -3224 => x"08080808", -3225 => x"08080808", -3226 => x"08080808", -3227 => x"08080808", -3228 => x"08080808", -3229 => x"08080808", -3230 => x"08080808", -3231 => x"08080808", -3232 => x"08080808", -3233 => x"08080808", -3234 => x"08080808", -3235 => x"08080808", -3236 => x"08080808", -3237 => x"08080808", -3238 => x"08080808", -3239 => x"08080808", -3240 => x"08080808", -3241 => x"08080808", -3242 => x"08080808", -3243 => x"08080808", -3244 => x"08080808", -3245 => x"08080808", -3246 => x"08080808", -3247 => x"00ffffff", -3248 => x"ff00ffff", -3249 => x"ffff00ff", -3250 => x"ffffff00", -3251 => x"00000000", -3252 => x"00000000", -3253 => x"00000000", -3254 => x"00003ab8", -3255 => x"000186a0", -- iterations -3256 => x"00000000", -3257 => x"00000000", -3258 => x"00000000", -3259 => x"00000000", -3260 => x"00000000", -3261 => x"00000000", -3262 => x"00000000", -3263 => x"00000000", -3264 => x"00000000", -3265 => x"00000000", -3266 => x"00000000", -3267 => x"00000000", -3268 => x"00000000", -3269 => x"ffffffff", -3270 => x"00000000", -3271 => x"00020000", -3272 => x"00000000", -3273 => x"00000000", -3274 => x"00003320", -3275 => x"00003320", -3276 => x"00003328", -3277 => x"00003328", -3278 => x"00003330", -3279 => x"00003330", -3280 => x"00003338", -3281 => x"00003338", -3282 => x"00003340", -3283 => x"00003340", -3284 => x"00003348", -3285 => x"00003348", -3286 => x"00003350", -3287 => x"00003350", -3288 => x"00003358", -3289 => x"00003358", -3290 => x"00003360", -3291 => x"00003360", -3292 => x"00003368", -3293 => x"00003368", -3294 => x"00003370", -3295 => x"00003370", -3296 => x"00003378", -3297 => x"00003378", -3298 => x"00003380", -3299 => x"00003380", -3300 => x"00003388", -3301 => x"00003388", -3302 => x"00003390", -3303 => x"00003390", -3304 => x"00003398", -3305 => x"00003398", -3306 => x"000033a0", -3307 => x"000033a0", -3308 => x"000033a8", -3309 => x"000033a8", -3310 => x"000033b0", -3311 => x"000033b0", -3312 => x"000033b8", -3313 => x"000033b8", -3314 => x"000033c0", -3315 => x"000033c0", -3316 => x"000033c8", -3317 => x"000033c8", -3318 => x"000033d0", -3319 => x"000033d0", -3320 => x"000033d8", -3321 => x"000033d8", -3322 => x"000033e0", -3323 => x"000033e0", -3324 => x"000033e8", -3325 => x"000033e8", -3326 => x"000033f0", -3327 => x"000033f0", -3328 => x"000033f8", -3329 => x"000033f8", -3330 => x"00003400", -3331 => x"00003400", -3332 => x"00003408", -3333 => x"00003408", -3334 => x"00003410", -3335 => x"00003410", -3336 => x"00003418", -3337 => x"00003418", -3338 => x"00003420", -3339 => x"00003420", -3340 => x"00003428", -3341 => x"00003428", -3342 => x"00003430", -3343 => x"00003430", -3344 => x"00003438", -3345 => x"00003438", -3346 => x"00003440", -3347 => x"00003440", -3348 => x"00003448", -3349 => x"00003448", -3350 => x"00003450", -3351 => x"00003450", -3352 => x"00003458", -3353 => x"00003458", -3354 => x"00003460", -3355 => x"00003460", -3356 => x"00003468", -3357 => x"00003468", -3358 => x"00003470", -3359 => x"00003470", -3360 => x"00003478", -3361 => x"00003478", -3362 => x"00003480", -3363 => x"00003480", -3364 => x"00003488", -3365 => x"00003488", -3366 => x"00003490", -3367 => x"00003490", -3368 => x"00003498", -3369 => x"00003498", -3370 => x"000034a0", -3371 => x"000034a0", -3372 => x"000034a8", -3373 => x"000034a8", -3374 => x"000034b0", -3375 => x"000034b0", -3376 => x"000034b8", -3377 => x"000034b8", -3378 => x"000034c0", -3379 => x"000034c0", -3380 => x"000034c8", -3381 => x"000034c8", -3382 => x"000034d0", -3383 => x"000034d0", -3384 => x"000034d8", -3385 => x"000034d8", -3386 => x"000034e0", -3387 => x"000034e0", -3388 => x"000034e8", -3389 => x"000034e8", -3390 => x"000034f0", -3391 => x"000034f0", -3392 => x"000034f8", -3393 => x"000034f8", -3394 => x"00003500", -3395 => x"00003500", -3396 => x"00003508", -3397 => x"00003508", -3398 => x"00003510", -3399 => x"00003510", -3400 => x"00003518", -3401 => x"00003518", -3402 => x"00003520", -3403 => x"00003520", -3404 => x"00003528", -3405 => x"00003528", -3406 => x"00003530", -3407 => x"00003530", -3408 => x"00003538", -3409 => x"00003538", -3410 => x"00003540", -3411 => x"00003540", -3412 => x"00003548", -3413 => x"00003548", -3414 => x"00003550", -3415 => x"00003550", -3416 => x"00003558", -3417 => x"00003558", -3418 => x"00003560", -3419 => x"00003560", -3420 => x"00003568", -3421 => x"00003568", -3422 => x"00003570", -3423 => x"00003570", -3424 => x"00003578", -3425 => x"00003578", -3426 => x"00003580", -3427 => x"00003580", -3428 => x"00003588", -3429 => x"00003588", -3430 => x"00003590", -3431 => x"00003590", -3432 => x"00003598", -3433 => x"00003598", -3434 => x"000035a0", -3435 => x"000035a0", -3436 => x"000035a8", -3437 => x"000035a8", -3438 => x"000035b0", -3439 => x"000035b0", -3440 => x"000035b8", -3441 => x"000035b8", -3442 => x"000035c0", -3443 => x"000035c0", -3444 => x"000035c8", -3445 => x"000035c8", -3446 => x"000035d0", -3447 => x"000035d0", -3448 => x"000035d8", -3449 => x"000035d8", -3450 => x"000035e0", -3451 => x"000035e0", -3452 => x"000035e8", -3453 => x"000035e8", -3454 => x"000035f0", -3455 => x"000035f0", -3456 => x"000035f8", -3457 => x"000035f8", -3458 => x"00003600", -3459 => x"00003600", -3460 => x"00003608", -3461 => x"00003608", -3462 => x"00003610", -3463 => x"00003610", -3464 => x"00003618", -3465 => x"00003618", -3466 => x"00003620", -3467 => x"00003620", -3468 => x"00003628", -3469 => x"00003628", -3470 => x"00003630", -3471 => x"00003630", -3472 => x"00003638", -3473 => x"00003638", -3474 => x"00003640", -3475 => x"00003640", -3476 => x"00003648", -3477 => x"00003648", -3478 => x"00003650", -3479 => x"00003650", -3480 => x"00003658", -3481 => x"00003658", -3482 => x"00003660", -3483 => x"00003660", -3484 => x"00003668", -3485 => x"00003668", -3486 => x"00003670", -3487 => x"00003670", -3488 => x"00003678", -3489 => x"00003678", -3490 => x"00003680", -3491 => x"00003680", -3492 => x"00003688", -3493 => x"00003688", -3494 => x"00003690", -3495 => x"00003690", -3496 => x"00003698", -3497 => x"00003698", -3498 => x"000036a0", -3499 => x"000036a0", -3500 => x"000036a8", -3501 => x"000036a8", -3502 => x"000036b0", -3503 => x"000036b0", -3504 => x"000036b8", -3505 => x"000036b8", -3506 => x"000036c0", -3507 => x"000036c0", -3508 => x"000036c8", -3509 => x"000036c8", -3510 => x"000036d0", -3511 => x"000036d0", -3512 => x"000036d8", -3513 => x"000036d8", -3514 => x"000036e0", -3515 => x"000036e0", -3516 => x"000036e8", -3517 => x"000036e8", -3518 => x"000036f0", -3519 => x"000036f0", -3520 => x"000036f8", -3521 => x"000036f8", -3522 => x"00003700", -3523 => x"00003700", -3524 => x"00003708", -3525 => x"00003708", -3526 => x"00003710", -3527 => x"00003710", -3528 => x"00003718", -3529 => x"00003718", -3530 => x"0000372c", -3531 => x"00000000", -3532 => x"00003994", -3533 => x"000039f0", -3534 => x"00003a4c", -3535 => x"00000000", -3536 => x"00000000", -3537 => x"00000000", -3538 => x"00000000", -3539 => x"00000000", -3540 => x"00000000", -3541 => x"00000000", -3542 => x"00000000", -3543 => x"00000000", -3544 => x"000031ac", -3545 => x"00000000", -3546 => x"00000000", -3547 => x"00000000", -3548 => x"00000000", -3549 => x"00000000", -3550 => x"00000000", -3551 => x"00000000", -3552 => x"00000000", -3553 => x"00000000", -3554 => x"00000000", -3555 => x"00000000", -3556 => x"00000000", -3557 => x"00000000", -3558 => x"00000000", -3559 => x"00000000", -3560 => x"00000000", -3561 => x"00000000", -3562 => x"00000000", -3563 => x"00000000", -3564 => x"00000000", -3565 => x"00000000", -3566 => x"00000000", -3567 => x"00000000", -3568 => x"00000000", -3569 => x"00000000", -3570 => x"00000000", -3571 => x"00000000", -3572 => x"00000000", -3573 => x"00000001", -3574 => x"330eabcd", -3575 => x"1234e66d", -3576 => x"deec0005", -3577 => x"000b0000", -3578 => x"00000000", -3579 => x"00000000", -3580 => x"00000000", -3581 => x"00000000", -3582 => x"00000000", -3583 => x"00000000", -3584 => x"00000000", -3585 => x"00000000", -3586 => x"00000000", -3587 => x"00000000", -3588 => x"00000000", -3589 => x"00000000", -3590 => x"00000000", -3591 => x"00000000", -3592 => x"00000000", -3593 => x"00000000", -3594 => x"00000000", -3595 => x"00000000", -3596 => x"00000000", -3597 => x"00000000", -3598 => x"00000000", -3599 => x"00000000", -3600 => x"00000000", -3601 => x"00000000", -3602 => x"00000000", -3603 => x"00000000", -3604 => x"00000000", -3605 => x"00000000", -3606 => x"00000000", -3607 => x"00000000", -3608 => x"00000000", -3609 => x"00000000", -3610 => x"00000000", -3611 => x"00000000", -3612 => x"00000000", -3613 => x"00000000", -3614 => x"00000000", -3615 => x"00000000", -3616 => x"00000000", -3617 => x"00000000", -3618 => x"00000000", -3619 => x"00000000", -3620 => x"00000000", -3621 => x"00000000", -3622 => x"00000000", -3623 => x"00000000", -3624 => x"00000000", -3625 => x"00000000", -3626 => x"00000000", -3627 => x"00000000", -3628 => x"00000000", -3629 => x"00000000", -3630 => x"00000000", -3631 => x"00000000", -3632 => x"00000000", -3633 => x"00000000", -3634 => x"00000000", -3635 => x"00000000", -3636 => x"00000000", -3637 => x"00000000", -3638 => x"00000000", -3639 => x"00000000", -3640 => x"00000000", -3641 => x"00000000", -3642 => x"00000000", -3643 => x"00000000", -3644 => x"00000000", -3645 => x"00000000", -3646 => x"00000000", -3647 => x"00000000", -3648 => x"00000000", -3649 => x"00000000", -3650 => x"00000000", -3651 => x"00000000", -3652 => x"00000000", -3653 => x"00000000", -3654 => x"00000000", -3655 => x"00000000", -3656 => x"00000000", -3657 => x"00000000", -3658 => x"00000000", -3659 => x"00000000", -3660 => x"00000000", -3661 => x"00000000", -3662 => x"00000000", -3663 => x"00000000", -3664 => x"00000000", -3665 => x"00000000", -3666 => x"00000000", -3667 => x"00000000", -3668 => x"00000000", -3669 => x"00000000", -3670 => x"00000000", -3671 => x"00000000", -3672 => x"00000000", -3673 => x"00000000", -3674 => x"00000000", -3675 => x"00000000", -3676 => x"00000000", -3677 => x"00000000", -3678 => x"00000000", -3679 => x"00000000", -3680 => x"00000000", -3681 => x"00000000", -3682 => x"00000000", -3683 => x"00000000", -3684 => x"00000000", -3685 => x"00000000", -3686 => x"00000000", -3687 => x"00000000", -3688 => x"00000000", -3689 => x"00000000", -3690 => x"00000000", -3691 => x"00000000", -3692 => x"00000000", -3693 => x"00000000", -3694 => x"00000000", -3695 => x"00000000", -3696 => x"00000000", -3697 => x"00000000", -3698 => x"00000000", -3699 => x"00000000", -3700 => x"00000000", -3701 => x"00000000", -3702 => x"00000000", -3703 => x"00000000", -3704 => x"00000000", -3705 => x"00000000", -3706 => x"00000000", -3707 => x"00000000", -3708 => x"00000000", -3709 => x"00000000", -3710 => x"00000000", -3711 => x"00000000", -3712 => x"00000000", -3713 => x"00000000", -3714 => x"00000000", -3715 => x"00000000", -3716 => x"00000000", -3717 => x"00000000", -3718 => x"00000000", -3719 => x"00000000", -3720 => x"00000000", -3721 => x"00000000", -3722 => x"00000000", -3723 => x"00000000", -3724 => x"00000000", -3725 => x"00000000", -3726 => x"00000000", -3727 => x"00000000", -3728 => x"00000000", -3729 => x"00000000", -3730 => x"00000000", -3731 => x"00000000", -3732 => x"00000000", -3733 => x"00000000", -3734 => x"00000000", -3735 => x"00000000", -3736 => x"00000000", -3737 => x"00000000", -3738 => x"00000000", -3739 => x"00000000", -3740 => x"00000000", -3741 => x"00000000", -3742 => x"00000000", -3743 => x"00000000", -3744 => x"00000000", -3745 => x"00000000", -3746 => x"00000000", -3747 => x"00000000", -3748 => x"00000000", -3749 => x"00000000", -3750 => x"00000000", -3751 => x"00000000", -3752 => x"00000000", -3753 => x"00000000", -3754 => x"000031b0", -3755 => x"ffffffff", -3756 => x"00000000", -3757 => x"ffffffff", -3758 => x"00000000", - others => x"00000000" -); - -begin - -mem_busy <= '0'; - -process (clk) -begin - if (clk'event and clk = '1') then - if (mem_writeEnable = '1') then - ram(conv_integer(mem_addr)) := mem_write; - end if; - mem_read <= ram(conv_integer(mem_addr)); - end if; -end process; - - - - -end dram_arch; diff --git a/zpu/hdl/zpu4/src/bram_dmips.vhd b/zpu/hdl/zpu4/src/bram_dmips.vhd deleted file mode 100644 index 1d62d21..0000000 --- a/zpu/hdl/zpu4/src/bram_dmips.vhd +++ /dev/null @@ -1,3717 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - -entity dualport_ram is -port (clk : in std_logic; - memAWriteEnable : in std_logic; - memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); - memAWrite : in std_logic_vector(wordSize-1 downto 0); - memARead : out std_logic_vector(wordSize-1 downto 0); - memBWriteEnable : in std_logic; - memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); - memBWrite : in std_logic_vector(wordSize-1 downto 0); - memBRead : out std_logic_vector(wordSize-1 downto 0)); -end dualport_ram; - -architecture dualport_ram_arch of dualport_ram is - - -type ram_type is array(natural range 0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); - -shared variable ram : ram_type := -( -0 => x"0b0b0b0b", -1 => x"80700b0b", -2 => x"80e2a40c", -3 => x"3a0b0b80", -4 => x"c6fc0400", -5 => x"00000000", -6 => x"00000000", -7 => x"00000000", -8 => x"80088408", -9 => x"88080b0b", -10 => x"80c7c32d", -11 => x"880c840c", -12 => x"800c0400", -13 => x"00000000", -14 => x"00000000", -15 => x"00000000", -16 => x"71fd0608", -17 => x"72830609", -18 => x"81058205", -19 => x"832b2a83", -20 => x"ffff0652", -21 => x"04000000", -22 => x"00000000", -23 => x"00000000", -24 => x"71fd0608", -25 => x"83ffff73", -26 => x"83060981", -27 => x"05820583", -28 => x"2b2b0906", -29 => x"7383ffff", -30 => x"0b0b0b0b", -31 => x"83a70400", -32 => x"72098105", -33 => x"72057373", -34 => x"09060906", -35 => x"73097306", -36 => x"070a8106", -37 => x"53510400", -38 => x"00000000", -39 => x"00000000", -40 => x"72722473", -41 => x"732e0753", -42 => x"51040000", -43 => x"00000000", -44 => x"00000000", -45 => x"00000000", -46 => x"00000000", -47 => x"00000000", -48 => x"71737109", -49 => x"71068106", -50 => x"30720a10", -51 => x"0a720a10", -52 => x"0a31050a", -53 => x"81065151", -54 => x"53510400", -55 => x"00000000", -56 => x"72722673", -57 => x"732e0753", -58 => x"51040000", -59 => x"00000000", -60 => x"00000000", -61 => x"00000000", -62 => x"00000000", -63 => x"00000000", -64 => x"00000000", -65 => x"00000000", -66 => x"00000000", -67 => x"00000000", -68 => x"00000000", -69 => x"00000000", -70 => x"00000000", -71 => x"00000000", -72 => x"0b0b0b88", -73 => x"c4040000", -74 => x"00000000", -75 => x"00000000", -76 => x"00000000", -77 => x"00000000", -78 => x"00000000", -79 => x"00000000", -80 => x"720a722b", -81 => x"0a535104", -82 => x"00000000", -83 => x"00000000", -84 => x"00000000", -85 => x"00000000", -86 => x"00000000", -87 => x"00000000", -88 => x"72729f06", -89 => x"0981050b", -90 => x"0b0b88a7", -91 => x"05040000", -92 => x"00000000", -93 => x"00000000", -94 => x"00000000", -95 => x"00000000", -96 => x"72722aff", -97 => x"739f062a", -98 => x"0974090a", -99 => x"8106ff05", -100 => x"06075351", -101 => x"04000000", -102 => x"00000000", -103 => x"00000000", -104 => x"71715351", -105 => x"020d0406", -106 => x"73830609", -107 => x"81058205", -108 => x"832b0b2b", -109 => x"0772fc06", -110 => x"0c515104", -111 => x"00000000", -112 => x"72098105", -113 => x"72050970", -114 => x"81050906", -115 => x"0a810653", -116 => x"51040000", -117 => x"00000000", -118 => x"00000000", -119 => x"00000000", -120 => x"72098105", -121 => x"72050970", -122 => x"81050906", -123 => x"0a098106", -124 => x"53510400", -125 => x"00000000", -126 => x"00000000", -127 => x"00000000", -128 => x"71098105", -129 => x"52040000", -130 => x"00000000", -131 => x"00000000", -132 => x"00000000", -133 => x"00000000", -134 => x"00000000", -135 => x"00000000", -136 => x"72720981", -137 => x"05055351", -138 => x"04000000", -139 => x"00000000", -140 => x"00000000", -141 => x"00000000", -142 => x"00000000", -143 => x"00000000", -144 => x"72097206", -145 => x"73730906", -146 => x"07535104", -147 => x"00000000", -148 => x"00000000", -149 => x"00000000", -150 => x"00000000", -151 => x"00000000", -152 => x"71fc0608", -153 => x"72830609", -154 => x"81058305", -155 => x"1010102a", -156 => x"81ff0652", -157 => x"04000000", -158 => x"00000000", -159 => x"00000000", -160 => x"71fc0608", -161 => x"0b0b80e2", -162 => x"90738306", -163 => x"10100508", -164 => x"060b0b0b", -165 => x"88aa0400", -166 => x"00000000", -167 => x"00000000", -168 => x"80088408", -169 => x"88087575", -170 => x"0b0b0baf", -171 => x"ac2d5050", -172 => x"80085688", -173 => x"0c840c80", -174 => x"0c510400", -175 => x"00000000", -176 => x"80088408", -177 => x"88087575", -178 => x"0b0b0baf", -179 => x"f02d5050", -180 => x"80085688", -181 => x"0c840c80", -182 => x"0c510400", -183 => x"00000000", -184 => x"72097081", -185 => x"0509060a", -186 => x"8106ff05", -187 => x"70547106", -188 => x"73097274", -189 => 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x"4e470000", -2708 => x"44687279", -2709 => x"73746f6e", -2710 => x"65204265", -2711 => x"6e63686d", -2712 => x"61726b2c", -2713 => x"20566572", -2714 => x"73696f6e", -2715 => x"20322e31", -2716 => x"20284c61", -2717 => x"6e677561", -2718 => x"67653a20", -2719 => x"43290a00", -2720 => x"50726f67", -2721 => x"72616d20", -2722 => x"636f6d70", -2723 => x"696c6564", -2724 => x"20776974", -2725 => x"68202772", -2726 => x"65676973", -2727 => x"74657227", -2728 => x"20617474", -2729 => x"72696275", -2730 => x"74650a00", -2731 => x"45786563", -2732 => x"7574696f", -2733 => x"6e207374", -2734 => x"61727473", -2735 => x"2c202564", -2736 => x"2072756e", -2737 => x"73207468", -2738 => x"726f7567", -2739 => x"68204468", -2740 => x"72797374", -2741 => x"6f6e650a", -2742 => x"00000000", -2743 => x"44485259", -2744 => x"53544f4e", -2745 => x"45205052", -2746 => x"4f475241", -2747 => x"4d2c2032", -2748 => x"274e4420", -2749 => x"53545249", -2750 => x"4e470000", -2751 => x"45786563", -2752 => x"7574696f", -2753 => x"6e20656e", -2754 => x"64730a00", -2755 => x"46696e61", -2756 => x"6c207661", -2757 => x"6c756573", -2758 => x"206f6620", -2759 => x"74686520", -2760 => x"76617269", -2761 => x"61626c65", -2762 => x"73207573", -2763 => x"65642069", -2764 => x"6e207468", -2765 => x"65206265", -2766 => x"6e63686d", -2767 => x"61726b3a", -2768 => x"0a000000", -2769 => x"496e745f", -2770 => x"476c6f62", -2771 => x"3a202020", -2772 => x"20202020", -2773 => x"20202020", -2774 => x"2025640a", -2775 => x"00000000", -2776 => x"20202020", -2777 => x"20202020", -2778 => x"73686f75", -2779 => x"6c642062", -2780 => x"653a2020", -2781 => x"2025640a", -2782 => x"00000000", -2783 => x"426f6f6c", -2784 => x"5f476c6f", -2785 => x"623a2020", -2786 => x"20202020", -2787 => x"20202020", -2788 => x"2025640a", -2789 => x"00000000", -2790 => x"43685f31", -2791 => x"5f476c6f", -2792 => x"623a2020", -2793 => x"20202020", -2794 => x"20202020", -2795 => x"2025630a", -2796 => x"00000000", -2797 => x"20202020", -2798 => x"20202020", -2799 => x"73686f75", -2800 => x"6c642062", -2801 => x"653a2020", -2802 => x"2025630a", -2803 => x"00000000", -2804 => x"43685f32", -2805 => x"5f476c6f", -2806 => x"623a2020", -2807 => x"20202020", -2808 => x"20202020", -2809 => x"2025630a", -2810 => x"00000000", -2811 => x"4172725f", -2812 => x"315f476c", -2813 => x"6f625b38", -2814 => x"5d3a2020", -2815 => x"20202020", -2816 => x"2025640a", -2817 => x"00000000", -2818 => x"4172725f", -2819 => x"325f476c", -2820 => x"6f625b38", -2821 => x"5d5b375d", -2822 => x"3a202020", -2823 => x"2025640a", -2824 => x"00000000", -2825 => x"20202020", -2826 => x"20202020", -2827 => x"73686f75", -2828 => x"6c642062", -2829 => x"653a2020", -2830 => x"204e756d", -2831 => x"6265725f", -2832 => x"4f665f52", -2833 => x"756e7320", -2834 => x"2b203130", -2835 => x"0a000000", -2836 => x"5074725f", -2837 => x"476c6f62", -2838 => x"2d3e0a00", -2839 => x"20205074", -2840 => x"725f436f", -2841 => x"6d703a20", -2842 => x"20202020", -2843 => x"20202020", -2844 => x"2025640a", -2845 => x"00000000", -2846 => x"20202020", -2847 => x"20202020", -2848 => x"73686f75", -2849 => x"6c642062", -2850 => x"653a2020", -2851 => x"2028696d", -2852 => x"706c656d", -2853 => x"656e7461", -2854 => x"74696f6e", -2855 => x"2d646570", -2856 => x"656e6465", -2857 => x"6e74290a", -2858 => x"00000000", -2859 => x"20204469", -2860 => x"7363723a", -2861 => x"20202020", -2862 => x"20202020", -2863 => x"20202020", -2864 => x"2025640a", -2865 => x"00000000", -2866 => x"2020456e", -2867 => x"756d5f43", -2868 => x"6f6d703a", -2869 => x"20202020", -2870 => x"20202020", -2871 => x"2025640a", -2872 => x"00000000", -2873 => x"2020496e", -2874 => x"745f436f", -2875 => x"6d703a20", -2876 => x"20202020", -2877 => x"20202020", -2878 => x"2025640a", -2879 => x"00000000", -2880 => x"20205374", -2881 => x"725f436f", -2882 => x"6d703a20", -2883 => x"20202020", -2884 => x"20202020", -2885 => x"2025730a", -2886 => x"00000000", -2887 => x"20202020", -2888 => x"20202020", -2889 => x"73686f75", -2890 => x"6c642062", -2891 => x"653a2020", -2892 => x"20444852", -2893 => x"5953544f", -2894 => x"4e452050", -2895 => x"524f4752", -2896 => x"414d2c20", -2897 => x"534f4d45", -2898 => x"20535452", -2899 => x"494e470a", -2900 => x"00000000", -2901 => x"4e657874", -2902 => x"5f507472", -2903 => x"5f476c6f", -2904 => x"622d3e0a", -2905 => x"00000000", -2906 => x"20202020", -2907 => x"20202020", -2908 => x"73686f75", -2909 => x"6c642062", -2910 => x"653a2020", -2911 => x"2028696d", -2912 => x"706c656d", -2913 => x"656e7461", -2914 => x"74696f6e", -2915 => x"2d646570", -2916 => x"656e6465", -2917 => x"6e74292c", -2918 => x"2073616d", -2919 => x"65206173", -2920 => x"2061626f", -2921 => x"76650a00", -2922 => x"496e745f", -2923 => x"315f4c6f", -2924 => x"633a2020", -2925 => x"20202020", -2926 => x"20202020", -2927 => x"2025640a", -2928 => x"00000000", -2929 => x"496e745f", -2930 => x"325f4c6f", -2931 => x"633a2020", -2932 => x"20202020", -2933 => x"20202020", -2934 => x"2025640a", -2935 => x"00000000", -2936 => x"496e745f", -2937 => x"335f4c6f", -2938 => x"633a2020", -2939 => x"20202020", -2940 => x"20202020", -2941 => x"2025640a", -2942 => x"00000000", -2943 => x"456e756d", -2944 => x"5f4c6f63", -2945 => x"3a202020", -2946 => x"20202020", -2947 => x"20202020", -2948 => x"2025640a", -2949 => x"00000000", -2950 => x"5374725f", -2951 => x"315f4c6f", -2952 => x"633a2020", -2953 => x"20202020", -2954 => x"20202020", -2955 => x"2025730a", -2956 => x"00000000", -2957 => x"20202020", -2958 => x"20202020", -2959 => x"73686f75", -2960 => x"6c642062", -2961 => x"653a2020", -2962 => x"20444852", -2963 => x"5953544f", -2964 => x"4e452050", -2965 => x"524f4752", -2966 => x"414d2c20", -2967 => x"31275354", -2968 => x"20535452", -2969 => x"494e470a", -2970 => x"00000000", -2971 => x"5374725f", -2972 => x"325f4c6f", -2973 => x"633a2020", -2974 => x"20202020", -2975 => x"20202020", -2976 => x"2025730a", -2977 => x"00000000", -2978 => x"20202020", -2979 => x"20202020", -2980 => x"73686f75", -2981 => x"6c642062", -2982 => x"653a2020", -2983 => x"20444852", -2984 => x"5953544f", -2985 => x"4e452050", -2986 => x"524f4752", -2987 => x"414d2c20", -2988 => x"32274e44", -2989 => x"20535452", -2990 => x"494e470a", -2991 => x"00000000", -2992 => x"55736572", -2993 => x"2074696d", -2994 => x"653a2025", -2995 => x"640a0000", -2996 => x"4d696372", -2997 => x"6f736563", -2998 => x"6f6e6473", -2999 => x"20666f72", -3000 => x"206f6e65", -3001 => x"2072756e", -3002 => x"20746872", -3003 => x"6f756768", -3004 => x"20446872", -3005 => x"7973746f", -3006 => x"6e653a20", -3007 => x"00000000", -3008 => x"2564200a", -3009 => x"00000000", -3010 => x"44687279", -3011 => x"73746f6e", -3012 => x"65732070", -3013 => x"65722053", -3014 => x"65636f6e", -3015 => x"643a2020", -3016 => x"20202020", -3017 => x"20202020", -3018 => x"20202020", -3019 => x"20202020", -3020 => x"20202020", -3021 => x"00000000", -3022 => x"56415820", -3023 => x"4d495053", -3024 => x"20726174", -3025 => x"696e6720", -3026 => x"2a203130", -3027 => x"3030203d", -3028 => x"20256420", -3029 => x"0a000000", -3030 => x"50726f67", -3031 => x"72616d20", -3032 => x"636f6d70", -3033 => x"696c6564", -3034 => x"20776974", -3035 => x"686f7574", -3036 => x"20277265", -3037 => x"67697374", -3038 => x"65722720", -3039 => x"61747472", -3040 => x"69627574", -3041 => x"650a0000", -3042 => x"4d656173", -3043 => x"75726564", -3044 => x"2074696d", -3045 => x"6520746f", -3046 => x"6f20736d", -3047 => x"616c6c20", -3048 => x"746f206f", -3049 => x"62746169", -3050 => x"6e206d65", -3051 => x"616e696e", -3052 => x"6766756c", -3053 => x"20726573", -3054 => x"756c7473", -3055 => x"0a000000", -3056 => x"506c6561", -3057 => x"73652069", -3058 => x"6e637265", -3059 => x"61736520", -3060 => x"6e756d62", -3061 => x"6572206f", -3062 => x"66207275", -3063 => x"6e730a00", -3064 => x"44485259", -3065 => x"53544f4e", -3066 => x"45205052", -3067 => x"4f475241", -3068 => x"4d2c2033", -3069 => x"27524420", -3070 => x"53545249", -3071 => x"4e470000", -3072 => x"00010202", -3073 => x"03030303", -3074 => x"04040404", -3075 => x"04040404", -3076 => x"05050505", -3077 => x"05050505", -3078 => x"05050505", -3079 => x"05050505", -3080 => x"06060606", -3081 => x"06060606", -3082 => x"06060606", -3083 => x"06060606", -3084 => x"06060606", -3085 => x"06060606", -3086 => x"06060606", -3087 => x"06060606", -3088 => x"07070707", -3089 => x"07070707", -3090 => x"07070707", -3091 => x"07070707", -3092 => x"07070707", -3093 => x"07070707", -3094 => x"07070707", -3095 => x"07070707", -3096 => x"07070707", -3097 => x"07070707", -3098 => x"07070707", -3099 => x"07070707", -3100 => x"07070707", -3101 => x"07070707", -3102 => x"07070707", -3103 => x"07070707", -3104 => x"08080808", -3105 => x"08080808", -3106 => x"08080808", -3107 => x"08080808", -3108 => x"08080808", -3109 => x"08080808", -3110 => x"08080808", -3111 => x"08080808", -3112 => x"08080808", -3113 => x"08080808", -3114 => x"08080808", -3115 => x"08080808", -3116 => x"08080808", -3117 => x"08080808", -3118 => x"08080808", -3119 => x"08080808", -3120 => x"08080808", -3121 => x"08080808", -3122 => x"08080808", -3123 => x"08080808", -3124 => x"08080808", -3125 => x"08080808", -3126 => x"08080808", -3127 => x"08080808", -3128 => x"08080808", -3129 => x"08080808", -3130 => x"08080808", -3131 => x"08080808", -3132 => x"08080808", -3133 => x"08080808", -3134 => x"08080808", -3135 => x"08080808", -3136 => x"43000000", -3137 => x"64756d6d", -3138 => x"792e6578", -3139 => x"65000000", -3140 => x"00ffffff", -3141 => x"ff00ffff", -3142 => x"ffff00ff", -3143 => x"ffffff00", -3144 => x"00000000", -3145 => x"00000000", -3146 => x"00000000", -3147 => x"0000390c", -3148 => x"000004d2", -- iterations 0x4d2=1234 -3149 => x"00000000", -3150 => x"00000000", -3151 => x"00000000", -3152 => x"00000000", -3153 => x"00000000", -3154 => x"00000000", -3155 => x"00000000", -3156 => x"00000000", -3157 => x"00000000", -3158 => x"00000000", -3159 => x"00000000", -3160 => x"00000000", -3161 => x"00000000", -3162 => x"ffffffff", -3163 => x"00000000", -3164 => x"00020000", -3165 => x"00000000", -3166 => x"00000000", -3167 => x"00003174", -3168 => x"00003174", -3169 => x"0000317c", -3170 => x"0000317c", -3171 => x"00003184", -3172 => x"00003184", -3173 => x"0000318c", -3174 => x"0000318c", -3175 => x"00003194", -3176 => x"00003194", -3177 => x"0000319c", -3178 => x"0000319c", -3179 => x"000031a4", -3180 => x"000031a4", -3181 => x"000031ac", -3182 => x"000031ac", -3183 => x"000031b4", -3184 => x"000031b4", -3185 => x"000031bc", -3186 => x"000031bc", -3187 => x"000031c4", -3188 => x"000031c4", -3189 => x"000031cc", -3190 => x"000031cc", -3191 => x"000031d4", -3192 => x"000031d4", -3193 => x"000031dc", -3194 => x"000031dc", -3195 => x"000031e4", -3196 => x"000031e4", -3197 => x"000031ec", -3198 => x"000031ec", -3199 => x"000031f4", -3200 => x"000031f4", -3201 => x"000031fc", -3202 => x"000031fc", -3203 => x"00003204", -3204 => x"00003204", -3205 => x"0000320c", -3206 => x"0000320c", -3207 => x"00003214", -3208 => x"00003214", -3209 => x"0000321c", -3210 => x"0000321c", -3211 => x"00003224", -3212 => x"00003224", -3213 => x"0000322c", -3214 => x"0000322c", -3215 => x"00003234", -3216 => x"00003234", -3217 => x"0000323c", -3218 => x"0000323c", -3219 => x"00003244", -3220 => x"00003244", -3221 => x"0000324c", -3222 => x"0000324c", -3223 => x"00003254", -3224 => x"00003254", -3225 => x"0000325c", -3226 => x"0000325c", -3227 => x"00003264", -3228 => x"00003264", -3229 => x"0000326c", -3230 => x"0000326c", -3231 => x"00003274", -3232 => x"00003274", -3233 => x"0000327c", -3234 => x"0000327c", -3235 => x"00003284", -3236 => x"00003284", -3237 => x"0000328c", -3238 => x"0000328c", -3239 => x"00003294", -3240 => x"00003294", -3241 => x"0000329c", -3242 => x"0000329c", -3243 => x"000032a4", -3244 => x"000032a4", -3245 => x"000032ac", -3246 => x"000032ac", -3247 => x"000032b4", -3248 => x"000032b4", -3249 => x"000032bc", -3250 => x"000032bc", -3251 => x"000032c4", -3252 => x"000032c4", -3253 => x"000032cc", -3254 => x"000032cc", -3255 => x"000032d4", -3256 => x"000032d4", -3257 => x"000032dc", -3258 => x"000032dc", -3259 => x"000032e4", -3260 => x"000032e4", -3261 => x"000032ec", -3262 => x"000032ec", -3263 => x"000032f4", -3264 => x"000032f4", -3265 => x"000032fc", -3266 => x"000032fc", -3267 => x"00003304", -3268 => x"00003304", -3269 => x"0000330c", -3270 => x"0000330c", -3271 => x"00003314", -3272 => x"00003314", -3273 => x"0000331c", -3274 => x"0000331c", -3275 => x"00003324", -3276 => x"00003324", -3277 => x"0000332c", -3278 => x"0000332c", -3279 => x"00003334", -3280 => x"00003334", -3281 => x"0000333c", -3282 => x"0000333c", -3283 => x"00003344", -3284 => x"00003344", -3285 => x"0000334c", -3286 => x"0000334c", -3287 => x"00003354", -3288 => x"00003354", -3289 => x"0000335c", -3290 => x"0000335c", -3291 => x"00003364", -3292 => x"00003364", -3293 => x"0000336c", -3294 => x"0000336c", -3295 => x"00003374", -3296 => x"00003374", -3297 => x"0000337c", -3298 => x"0000337c", -3299 => x"00003384", -3300 => x"00003384", -3301 => x"0000338c", -3302 => x"0000338c", -3303 => x"00003394", -3304 => x"00003394", -3305 => x"0000339c", -3306 => x"0000339c", -3307 => x"000033a4", -3308 => x"000033a4", -3309 => x"000033ac", -3310 => x"000033ac", -3311 => x"000033b4", -3312 => x"000033b4", -3313 => x"000033bc", -3314 => x"000033bc", -3315 => x"000033c4", -3316 => x"000033c4", -3317 => x"000033cc", -3318 => x"000033cc", -3319 => x"000033d4", -3320 => x"000033d4", -3321 => x"000033dc", -3322 => x"000033dc", -3323 => x"000033e4", -3324 => x"000033e4", -3325 => x"000033ec", -3326 => x"000033ec", -3327 => x"000033f4", -3328 => x"000033f4", -3329 => x"000033fc", -3330 => x"000033fc", -3331 => x"00003404", -3332 => x"00003404", -3333 => x"0000340c", -3334 => x"0000340c", -3335 => x"00003414", -3336 => x"00003414", -3337 => x"0000341c", -3338 => x"0000341c", -3339 => x"00003424", -3340 => x"00003424", -3341 => x"0000342c", -3342 => x"0000342c", -3343 => x"00003434", -3344 => x"00003434", -3345 => x"0000343c", -3346 => x"0000343c", -3347 => x"00003444", -3348 => x"00003444", -3349 => x"0000344c", -3350 => x"0000344c", -3351 => x"00003454", -3352 => x"00003454", -3353 => x"0000345c", -3354 => x"0000345c", -3355 => x"00003464", -3356 => x"00003464", -3357 => x"0000346c", -3358 => x"0000346c", -3359 => x"00003474", -3360 => x"00003474", -3361 => x"0000347c", -3362 => x"0000347c", -3363 => x"00003484", -3364 => x"00003484", -3365 => x"0000348c", -3366 => x"0000348c", -3367 => x"00003494", -3368 => x"00003494", -3369 => x"0000349c", -3370 => x"0000349c", -3371 => x"000034a4", -3372 => x"000034a4", -3373 => x"000034ac", -3374 => x"000034ac", -3375 => x"000034b4", -3376 => x"000034b4", -3377 => x"000034bc", -3378 => x"000034bc", -3379 => x"000034c4", -3380 => x"000034c4", -3381 => x"000034cc", -3382 => x"000034cc", -3383 => x"000034d4", -3384 => x"000034d4", -3385 => x"000034dc", -3386 => x"000034dc", -3387 => x"000034e4", -3388 => x"000034e4", -3389 => x"000034ec", -3390 => x"000034ec", -3391 => x"000034f4", -3392 => x"000034f4", -3393 => x"000034fc", -3394 => x"000034fc", -3395 => x"00003504", -3396 => x"00003504", -3397 => x"0000350c", -3398 => x"0000350c", -3399 => x"00003514", -3400 => x"00003514", -3401 => x"0000351c", -3402 => x"0000351c", -3403 => x"00003524", -3404 => x"00003524", -3405 => x"0000352c", -3406 => x"0000352c", -3407 => x"00003534", -3408 => x"00003534", -3409 => x"0000353c", -3410 => x"0000353c", -3411 => x"00003544", -3412 => x"00003544", -3413 => x"0000354c", -3414 => x"0000354c", -3415 => x"00003554", -3416 => x"00003554", -3417 => x"0000355c", -3418 => x"0000355c", -3419 => x"00003564", -3420 => x"00003564", -3421 => x"0000356c", -3422 => x"0000356c", -3423 => x"00003580", -3424 => x"00000000", -3425 => x"000037e8", -3426 => x"00003844", -3427 => x"000038a0", -3428 => x"00000000", -3429 => x"00000000", -3430 => x"00000000", -3431 => x"00000000", -3432 => x"00000000", -3433 => x"00000000", -3434 => x"00000000", -3435 => x"00000000", -3436 => x"00000000", -3437 => x"00003100", -3438 => x"00000000", -3439 => x"00000000", -3440 => x"00000000", -3441 => x"00000000", -3442 => x"00000000", -3443 => x"00000000", -3444 => x"00000000", -3445 => x"00000000", -3446 => x"00000000", -3447 => x"00000000", -3448 => x"00000000", -3449 => x"00000000", -3450 => x"00000000", -3451 => x"00000000", -3452 => x"00000000", -3453 => x"00000000", -3454 => x"00000000", -3455 => x"00000000", -3456 => x"00000000", -3457 => x"00000000", -3458 => x"00000000", -3459 => x"00000000", -3460 => x"00000000", -3461 => x"00000000", -3462 => x"00000000", -3463 => x"00000000", -3464 => x"00000000", -3465 => x"00000000", -3466 => x"00000001", -3467 => x"330eabcd", -3468 => x"1234e66d", -3469 => x"deec0005", -3470 => x"000b0000", -3471 => x"00000000", -3472 => x"00000000", -3473 => x"00000000", -3474 => x"00000000", -3475 => x"00000000", -3476 => x"00000000", -3477 => x"00000000", -3478 => x"00000000", -3479 => x"00000000", -3480 => x"00000000", -3481 => x"00000000", -3482 => x"00000000", -3483 => x"00000000", -3484 => x"00000000", -3485 => x"00000000", -3486 => x"00000000", -3487 => x"00000000", -3488 => x"00000000", -3489 => x"00000000", -3490 => x"00000000", -3491 => x"00000000", -3492 => x"00000000", -3493 => x"00000000", -3494 => x"00000000", -3495 => x"00000000", -3496 => x"00000000", -3497 => x"00000000", -3498 => x"00000000", -3499 => x"00000000", -3500 => x"00000000", -3501 => x"00000000", -3502 => x"00000000", -3503 => x"00000000", -3504 => x"00000000", -3505 => x"00000000", -3506 => x"00000000", -3507 => x"00000000", -3508 => x"00000000", -3509 => x"00000000", -3510 => x"00000000", -3511 => x"00000000", -3512 => x"00000000", -3513 => x"00000000", -3514 => x"00000000", -3515 => x"00000000", -3516 => x"00000000", -3517 => x"00000000", -3518 => x"00000000", -3519 => x"00000000", -3520 => x"00000000", -3521 => x"00000000", -3522 => x"00000000", -3523 => x"00000000", -3524 => x"00000000", -3525 => x"00000000", -3526 => x"00000000", -3527 => x"00000000", -3528 => x"00000000", -3529 => x"00000000", -3530 => x"00000000", -3531 => x"00000000", -3532 => x"00000000", -3533 => x"00000000", -3534 => x"00000000", -3535 => x"00000000", -3536 => x"00000000", -3537 => x"00000000", -3538 => x"00000000", -3539 => x"00000000", -3540 => x"00000000", -3541 => x"00000000", -3542 => x"00000000", -3543 => x"00000000", -3544 => x"00000000", -3545 => x"00000000", -3546 => x"00000000", -3547 => x"00000000", -3548 => x"00000000", -3549 => x"00000000", -3550 => x"00000000", -3551 => x"00000000", -3552 => x"00000000", -3553 => x"00000000", -3554 => x"00000000", -3555 => x"00000000", -3556 => x"00000000", -3557 => x"00000000", -3558 => x"00000000", -3559 => x"00000000", -3560 => x"00000000", -3561 => x"00000000", -3562 => x"00000000", -3563 => x"00000000", -3564 => x"00000000", -3565 => x"00000000", -3566 => x"00000000", -3567 => x"00000000", -3568 => x"00000000", -3569 => x"00000000", -3570 => x"00000000", -3571 => x"00000000", -3572 => x"00000000", -3573 => x"00000000", -3574 => x"00000000", -3575 => x"00000000", -3576 => x"00000000", -3577 => x"00000000", -3578 => x"00000000", -3579 => x"00000000", -3580 => x"00000000", -3581 => x"00000000", -3582 => x"00000000", -3583 => x"00000000", -3584 => x"00000000", -3585 => x"00000000", -3586 => x"00000000", -3587 => x"00000000", -3588 => x"00000000", -3589 => x"00000000", -3590 => x"00000000", -3591 => x"00000000", -3592 => x"00000000", -3593 => x"00000000", -3594 => x"00000000", -3595 => x"00000000", -3596 => x"00000000", -3597 => x"00000000", -3598 => x"00000000", -3599 => x"00000000", -3600 => x"00000000", -3601 => x"00000000", -3602 => x"00000000", -3603 => x"00000000", -3604 => x"00000000", -3605 => x"00000000", -3606 => x"00000000", -3607 => x"00000000", -3608 => x"00000000", -3609 => x"00000000", -3610 => x"00000000", -3611 => x"00000000", -3612 => x"00000000", -3613 => x"00000000", -3614 => x"00000000", -3615 => x"00000000", -3616 => x"00000000", -3617 => x"00000000", -3618 => x"00000000", -3619 => x"00000000", -3620 => x"00000000", -3621 => x"00000000", -3622 => x"00000000", -3623 => x"00000000", -3624 => x"00000000", -3625 => x"00000000", -3626 => x"00000000", -3627 => x"00000000", -3628 => x"00000000", -3629 => x"00000000", -3630 => x"00000000", -3631 => x"00000000", -3632 => x"00000000", -3633 => x"00000000", -3634 => x"00000000", -3635 => x"00000000", -3636 => x"00000000", -3637 => x"00000000", -3638 => x"00000000", -3639 => x"00000000", -3640 => x"00000000", -3641 => x"00000000", -3642 => x"00000000", -3643 => x"00000000", -3644 => x"00000000", -3645 => x"00000000", -3646 => x"00000000", -3647 => x"00003104", -3648 => x"ffffffff", -3649 => x"00000000", -3650 => x"ffffffff", -3651 => x"00000000", - others => x"00000000" -); - -begin - -process (clk) -begin - if (clk'event and clk = '1') then - if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then - report "write collision" severity failure; - end if; - - if (memAWriteEnable = '1') then - ram(to_integer(unsigned(memAAddr))) := memAWrite; - memARead <= memAWrite; - else - memARead <= ram(to_integer(unsigned(memAAddr))); - end if; - end if; -end process; - -process (clk) -begin - if (clk'event and clk = '1') then - if (memBWriteEnable = '1') then - ram(to_integer(unsigned(memBAddr))) := memBWrite; - memBRead <= memBWrite; - else - memBRead <= ram(to_integer(unsigned(memBAddr))); - end if; - end if; -end process; - - - - -end dualport_ram_arch; diff --git a/zpu/hdl/zpu4/src/dram_dmips.vhd b/zpu/hdl/zpu4/src/dram_dmips.vhd deleted file mode 100644 index a9fd59e..0000000 --- a/zpu/hdl/zpu4/src/dram_dmips.vhd +++ /dev/null @@ -1,3308 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - -entity dram is -port (clk : in std_logic; -areset : std_logic; - mem_writeEnable : in std_logic; - mem_readEnable : in std_logic; - mem_addr : in std_logic_vector(maxAddrBit downto 0); - mem_write : in std_logic_vector(wordSize-1 downto 0); - mem_read : out std_logic_vector(wordSize-1 downto 0); - mem_busy : out std_logic; - mem_writeMask : in std_logic_vector(wordBytes-1 downto 0)); -end dram; - -architecture dram_arch of dram is - - -type ram_type is array(natural range 0 to ((2**(maxAddrBitDRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); - -shared variable ram : ram_type := -( -0 => x"0b0b0b0b", -1 => x"82700b0b", -2 => x"80d5f40c", -3 => x"3a0b0b80", -4 => x"c4fb0400", -5 => x"00000000", -6 => x"00000000", -7 => x"00000000", -8 => x"80088408", -9 => x"88080b0b", -10 => x"80c5c22d", -11 => x"880c840c", -12 => x"800c0400", -13 => x"00000000", -14 => x"00000000", -15 => x"00000000", -16 => x"71fd0608", -17 => x"72830609", -18 => x"81058205", -19 => x"832b2a83", -20 => x"ffff0652", -21 => x"04000000", -22 => x"00000000", -23 => x"00000000", -24 => x"71fd0608", -25 => x"83ffff73", -26 => x"83060981", -27 => x"05820583", -28 => x"2b2b0906", -29 => x"7383ffff", -30 => x"0b0b0b0b", -31 => x"83a70400", -32 => x"72098105", -33 => x"72057373", -34 => x"09060906", -35 => x"73097306", -36 => x"070a8106", -37 => x"53510400", -38 => x"00000000", -39 => x"00000000", -40 => x"72722473", -41 => x"732e0753", -42 => x"51040000", -43 => x"00000000", -44 => x"00000000", -45 => x"00000000", -46 => x"00000000", -47 => x"00000000", -48 => x"71737109", -49 => x"71068106", -50 => x"30720a10", -51 => x"0a720a10", -52 => x"0a31050a", -53 => x"81065151", -54 => x"53510400", -55 => x"00000000", -56 => x"72722673", -57 => x"732e0753", -58 => x"51040000", -59 => x"00000000", -60 => x"00000000", -61 => x"00000000", -62 => x"00000000", -63 => x"00000000", -64 => x"00000000", -65 => x"00000000", -66 => x"00000000", -67 => x"00000000", -68 => x"00000000", -69 => x"00000000", -70 => x"00000000", -71 => x"00000000", -72 => x"0b0b0b88", -73 => x"c3040000", -74 => x"00000000", -75 => x"00000000", -76 => x"00000000", -77 => x"00000000", -78 => x"00000000", -79 => x"00000000", -80 => x"720a722b", -81 => x"0a535104", -82 => x"00000000", -83 => x"00000000", -84 => x"00000000", -85 => x"00000000", -86 => x"00000000", -87 => x"00000000", -88 => x"72729f06", -89 => x"0981050b", -90 => x"0b0b88a6", -91 => x"05040000", -92 => x"00000000", -93 => x"00000000", -94 => x"00000000", -95 => x"00000000", -96 => x"72722aff", -97 => x"739f062a", -98 => x"0974090a", -99 => x"8106ff05", -100 => x"06075351", -101 => x"04000000", -102 => x"00000000", -103 => x"00000000", -104 => x"71715351", -105 => x"020d0406", -106 => x"73830609", -107 => x"81058205", -108 => x"832b0b2b", -109 => x"0772fc06", -110 => x"0c515104", -111 => x"00000000", -112 => x"72098105", -113 => x"72050970", -114 => x"81050906", -115 => x"0a810653", -116 => x"51040000", -117 => x"00000000", -118 => x"00000000", -119 => x"00000000", -120 => x"72098105", -121 => x"72050970", -122 => x"81050906", -123 => x"0a098106", -124 => x"53510400", -125 => x"00000000", -126 => x"00000000", -127 => x"00000000", -128 => x"71098105", -129 => x"52040000", -130 => x"00000000", -131 => x"00000000", -132 => x"00000000", -133 => x"00000000", -134 => x"00000000", -135 => x"00000000", -136 => x"72720981", -137 => x"05055351", -138 => x"04000000", -139 => x"00000000", -140 => x"00000000", -141 => x"00000000", -142 => x"00000000", -143 => x"00000000", -144 => x"72097206", -145 => x"73730906", -146 => x"07535104", -147 => x"00000000", -148 => x"00000000", -149 => x"00000000", -150 => x"00000000", -151 => x"00000000", -152 => x"71fc0608", -153 => x"72830609", -154 => x"81058305", -155 => x"1010102a", -156 => x"81ff0652", -157 => x"04000000", -158 => x"00000000", -159 => x"00000000", -160 => x"71fc0608", -161 => x"0b0b80d5", -162 => x"e0738306", -163 => x"10100508", -164 => x"060b0b0b", -165 => x"88a90400", -166 => x"00000000", -167 => x"00000000", -168 => x"80088408", -169 => x"88087575", -170 => x"0b0b0bad", -171 => x"aa2d5050", -172 => x"80085688", -173 => x"0c840c80", -174 => x"0c510400", -175 => x"00000000", -176 => x"80088408", -177 => x"88087575", -178 => x"0b0b0bad", -179 => x"ee2d5050", -180 => x"80085688", -181 => x"0c840c80", -182 => x"0c510400", -183 => x"00000000", -184 => x"72097081", -185 => x"0509060a", -186 => x"8106ff05", -187 => x"70547106", -188 => x"73097274", -189 => x"05ff0506", -190 => x"07515151", -191 => x"04000000", -192 => x"72097081", -193 => x"0509060a", -194 => x"098106ff", -195 => x"05705471", -196 => x"06730972", -197 => x"7405ff05", -198 => x"06075151", -199 => x"51040000", -200 => x"05ff0504", -201 => x"00000000", -202 => x"00000000", -203 => x"00000000", -204 => x"00000000", -205 => x"00000000", -206 => x"00000000", -207 => x"00000000", -208 => x"810b0b0b", -209 => x"80d5f00c", -210 => x"51040000", -211 => x"00000000", -212 => x"00000000", -213 => x"00000000", -214 => x"00000000", -215 => x"00000000", -216 => x"71810552", -217 => x"04000000", -218 => x"00000000", -219 => x"00000000", -220 => x"00000000", -221 => x"00000000", -222 => x"00000000", -223 => x"00000000", -224 => x"00000000", -225 => x"00000000", -226 => x"00000000", -227 => x"00000000", -228 => x"00000000", -229 => x"00000000", -230 => x"00000000", -231 => x"00000000", -232 => x"02840572", -233 => x"10100552", -234 => x"04000000", -235 => x"00000000", -236 => x"00000000", -237 => x"00000000", -238 => x"00000000", -239 => x"00000000", -240 => x"00000000", -241 => x"00000000", -242 => x"00000000", -243 => x"00000000", -244 => x"00000000", -245 => x"00000000", -246 => x"00000000", -247 => x"00000000", -248 => x"717105ff", -249 => x"05715351", -250 => x"020d0400", -251 => x"00000000", -252 => x"00000000", -253 => x"00000000", -254 => x"00000000", -255 => x"00000000", -256 => x"82fd3fbf", -257 => x"a03f0410", -258 => x"10101010", -259 => x"10101010", -260 => x"10101010", -261 => x"10101010", -262 => x"10101010", -263 => x"10101010", -264 => x"10101010", -265 => x"10105351", -266 => x"047381ff", -267 => x"06738306", -268 => x"09810583", -269 => x"05101010", -270 => x"2b0772fc", -271 => x"060c5151", -272 => x"043c0472", -273 => x"72807281", -274 => x"06ff0509", -275 => x"72060571", -276 => x"1052720a", -277 => x"100a5372", -278 => x"ed385151", -279 => x"535104ff", -280 => x"3d0d0b0b", -281 => x"80e5e408", -282 => x"52710870", -283 => x"882a8132", -284 => x"70810651", -285 => x"515170f1", -286 => x"3873720c", -287 => x"833d0d04", -288 => x"80d5f008", -289 => x"802ea438", -290 => x"80d5f408", -291 => x"822ebd38", -292 => x"8380800b", -293 => x"0b0b80e5", -294 => x"e40c82a0", -295 => x"800b80e5", -296 => x"e80c8290", -297 => x"800b80e5", -298 => x"ec0c04f8", -299 => x"808080a4", -300 => x"0b0b0b80", -301 => x"e5e40cf8", -302 => x"80808280", -303 => x"0b80e5e8", -304 => x"0cf88080", -305 => x"84800b80", -306 => x"e5ec0c04", -307 => x"80c0a880", -308 => x"8c0b0b0b", -309 => x"80e5e40c", -310 => x"80c0a880", -311 => x"940b80e5", -312 => x"e80c0b0b", -313 => x"80c7d00b", -314 => x"80e5ec0c", -315 => x"04f23d0d", -316 => x"6080e5e8", -317 => x"08565d82", -318 => x"750c8059", -319 => x"805a800b", -320 => x"8f3d5d5b", -321 => x"7a101015", -322 => x"70087108", -323 => x"719f2c7e", -324 => x"852b5855", -325 => x"557d5359", -326 => x"5799993f", -327 => x"7d7f7a72", -328 => x"077c7207", -329 => x"71716081", -330 => x"05415f5d", -331 => x"5b595755", -332 => x"817b278f", -333 => x"38767d0c", -334 => x"77841e0c", -335 => x"7c800c90", -336 => x"3d0d0480", -337 => x"e5e80855", -338 => x"ffba3970", -339 => x"7080e5f0", -340 => x"335170a7", -341 => x"3880d5fc", -342 => x"08700852", -343 => x"5270802e", -344 => x"94388412", -345 => x"80d5fc0c", -346 => x"702d80d5", -347 => x"fc087008", -348 => x"525270ee", -349 => x"38810b80", -350 => x"e5f03450", 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x"00002e0c", -2951 => x"00002e14", -2952 => x"00002e14", -2953 => x"00002e1c", -2954 => x"00002e1c", -2955 => x"00002e24", -2956 => x"00002e24", -2957 => x"00002e2c", -2958 => x"00002e2c", -2959 => x"00002e34", -2960 => x"00002e34", -2961 => x"00002e3c", -2962 => x"00002e3c", -2963 => x"00002e44", -2964 => x"00002e44", -2965 => x"00002e4c", -2966 => x"00002e4c", -2967 => x"00002e54", -2968 => x"00002e54", -2969 => x"00002e5c", -2970 => x"00002e5c", -2971 => x"00002e64", -2972 => x"00002e64", -2973 => x"00002e6c", -2974 => x"00002e6c", -2975 => x"00002e74", -2976 => x"00002e74", -2977 => x"00002e7c", -2978 => x"00002e7c", -2979 => x"00002e84", -2980 => x"00002e84", -2981 => x"00002e8c", -2982 => x"00002e8c", -2983 => x"00002e94", -2984 => x"00002e94", -2985 => x"00002e9c", -2986 => x"00002e9c", -2987 => x"00002ea4", -2988 => x"00002ea4", -2989 => x"00002eac", -2990 => x"00002eac", -2991 => x"00002eb4", -2992 => x"00002eb4", -2993 => x"00002ebc", -2994 => x"00002ebc", -2995 => x"00002ec4", -2996 => x"00002ec4", -2997 => x"00002ecc", -2998 => x"00002ecc", -2999 => x"00002ed4", -3000 => x"00002ed4", -3001 => x"00002edc", -3002 => x"00002edc", -3003 => x"00002ee4", -3004 => x"00002ee4", -3005 => x"00002eec", -3006 => x"00002eec", -3007 => x"00002ef4", -3008 => x"00002ef4", -3009 => x"00002efc", -3010 => x"00002efc", -3011 => x"00002f04", -3012 => x"00002f04", -3013 => x"00002f0c", -3014 => x"00002f0c", -3015 => x"00002f14", -3016 => x"00002f14", -3017 => x"00002f1c", -3018 => x"00002f1c", -3019 => x"00002f24", -3020 => x"00002f24", -3021 => x"00002f2c", -3022 => x"00002f2c", -3023 => x"00002f34", -3024 => x"00002f34", -3025 => x"00002f3c", -3026 => x"00002f3c", -3027 => x"00002f50", -3028 => x"00000000", -3029 => x"000031b8", -3030 => x"00003214", -3031 => x"00003270", -3032 => x"00000000", -3033 => x"00000000", -3034 => x"00000000", -3035 => x"00000000", -3036 => x"00000000", -3037 => x"00000000", -3038 => x"00000000", -3039 => x"00000000", -3040 => x"00000000", -3041 => x"00002ad0", -3042 => x"00000000", -3043 => x"00000000", -3044 => x"00000000", -3045 => x"00000000", -3046 => x"00000000", -3047 => x"00000000", -3048 => x"00000000", -3049 => x"00000000", -3050 => x"00000000", -3051 => x"00000000", -3052 => x"00000000", -3053 => x"00000000", -3054 => x"00000000", -3055 => x"00000000", -3056 => x"00000000", -3057 => x"00000000", -3058 => x"00000000", -3059 => x"00000000", -3060 => x"00000000", -3061 => x"00000000", -3062 => x"00000000", -3063 => x"00000000", -3064 => x"00000000", -3065 => x"00000000", -3066 => x"00000000", -3067 => x"00000000", -3068 => x"00000000", -3069 => x"00000000", -3070 => x"00000001", -3071 => x"330eabcd", -3072 => x"1234e66d", -3073 => x"deec0005", -3074 => x"000b0000", -3075 => x"00000000", -3076 => x"00000000", -3077 => x"00000000", -3078 => x"00000000", -3079 => x"00000000", -3080 => x"00000000", -3081 => x"00000000", -3082 => x"00000000", -3083 => x"00000000", -3084 => x"00000000", -3085 => x"00000000", -3086 => x"00000000", -3087 => x"00000000", -3088 => x"00000000", -3089 => x"00000000", -3090 => x"00000000", -3091 => x"00000000", -3092 => x"00000000", -3093 => x"00000000", -3094 => x"00000000", -3095 => x"00000000", -3096 => x"00000000", -3097 => x"00000000", -3098 => x"00000000", -3099 => x"00000000", -3100 => x"00000000", -3101 => x"00000000", -3102 => x"00000000", -3103 => x"00000000", -3104 => x"00000000", -3105 => x"00000000", -3106 => x"00000000", -3107 => x"00000000", -3108 => x"00000000", -3109 => x"00000000", -3110 => x"00000000", -3111 => x"00000000", -3112 => x"00000000", -3113 => x"00000000", -3114 => x"00000000", -3115 => x"00000000", -3116 => x"00000000", -3117 => x"00000000", -3118 => x"00000000", -3119 => x"00000000", -3120 => x"00000000", -3121 => x"00000000", -3122 => x"00000000", -3123 => x"00000000", -3124 => x"00000000", -3125 => x"00000000", -3126 => x"00000000", -3127 => x"00000000", -3128 => x"00000000", -3129 => x"00000000", -3130 => x"00000000", -3131 => x"00000000", -3132 => x"00000000", -3133 => x"00000000", -3134 => x"00000000", -3135 => x"00000000", -3136 => x"00000000", -3137 => x"00000000", -3138 => x"00000000", -3139 => x"00000000", -3140 => x"00000000", -3141 => x"00000000", -3142 => x"00000000", -3143 => x"00000000", -3144 => x"00000000", -3145 => x"00000000", -3146 => x"00000000", -3147 => x"00000000", -3148 => x"00000000", -3149 => x"00000000", -3150 => x"00000000", -3151 => x"00000000", -3152 => x"00000000", -3153 => x"00000000", -3154 => x"00000000", -3155 => x"00000000", -3156 => x"00000000", -3157 => x"00000000", -3158 => x"00000000", -3159 => x"00000000", -3160 => x"00000000", -3161 => x"00000000", -3162 => x"00000000", -3163 => x"00000000", -3164 => x"00000000", -3165 => x"00000000", -3166 => x"00000000", -3167 => x"00000000", -3168 => x"00000000", -3169 => x"00000000", -3170 => x"00000000", -3171 => x"00000000", -3172 => x"00000000", -3173 => x"00000000", -3174 => x"00000000", -3175 => x"00000000", -3176 => x"00000000", -3177 => x"00000000", -3178 => x"00000000", -3179 => x"00000000", -3180 => x"00000000", -3181 => x"00000000", -3182 => x"00000000", -3183 => x"00000000", -3184 => x"00000000", -3185 => x"00000000", -3186 => x"00000000", -3187 => x"00000000", -3188 => x"00000000", -3189 => x"00000000", -3190 => x"00000000", -3191 => x"00000000", -3192 => x"00000000", -3193 => x"00000000", -3194 => x"00000000", -3195 => x"00000000", -3196 => x"00000000", -3197 => x"00000000", -3198 => x"00000000", -3199 => x"00000000", -3200 => x"00000000", -3201 => x"00000000", -3202 => x"00000000", -3203 => x"00000000", -3204 => x"00000000", -3205 => x"00000000", -3206 => x"00000000", -3207 => x"00000000", -3208 => x"00000000", -3209 => x"00000000", -3210 => x"00000000", -3211 => x"00000000", -3212 => x"00000000", -3213 => x"00000000", -3214 => x"00000000", -3215 => x"00000000", -3216 => x"00000000", -3217 => x"00000000", -3218 => x"00000000", -3219 => x"00000000", -3220 => x"00000000", -3221 => x"00000000", -3222 => x"00000000", -3223 => x"00000000", -3224 => x"00000000", -3225 => x"00000000", -3226 => x"00000000", -3227 => x"00000000", -3228 => x"00000000", -3229 => x"00000000", -3230 => x"00000000", -3231 => x"00000000", -3232 => x"00000000", -3233 => x"00000000", -3234 => x"00000000", -3235 => x"00000000", -3236 => x"00000000", -3237 => x"00000000", -3238 => x"00000000", -3239 => x"00000000", -3240 => x"00000000", -3241 => x"00000000", -3242 => x"00000000", -3243 => x"00000000", -3244 => x"00000000", -3245 => x"00000000", -3246 => x"00000000", -3247 => x"00000000", -3248 => x"00000000", -3249 => x"00000000", -3250 => x"00000000", -3251 => x"00002ad4", -3252 => x"ffffffff", -3253 => x"00000000", -3254 => x"ffffffff", -3255 => x"00000000", - others => x"00000000" -); - -begin - -mem_busy<=mem_readEnable; -- we're done on the cycle after we serve the read request - -process (clk, areset) -begin - if areset = '1' then - elsif (clk'event and clk = '1') then - if (mem_writeEnable = '1') then - ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit)))) := mem_write; - end if; - if (mem_readEnable = '1') then - mem_read <= ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit)))); - end if; - end if; -end process; - - - - -end dram_arch; diff --git a/zpu/hdl/zpu4/src/dram_hello.vhd b/zpu/hdl/zpu4/src/dram_hello.vhd deleted file mode 100644 index 4f02cca..0000000 --- a/zpu/hdl/zpu4/src/dram_hello.vhd +++ /dev/null @@ -1,3107 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - -entity dram is -port (clk : in std_logic; -areset : std_logic; - mem_writeEnable : in std_logic; - mem_readEnable : in std_logic; - mem_addr : in std_logic_vector(maxAddrBit downto 0); - mem_write : in std_logic_vector(wordSize-1 downto 0); - mem_read : out std_logic_vector(wordSize-1 downto 0); - mem_busy : out std_logic; - mem_writeMask : in std_logic_vector(wordBytes-1 downto 0)); -end dram; - -architecture dram_arch of dram is - - -type ram_type is array(natural range 0 to ((2**(maxAddrBitDRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); - -shared variable ram : ram_type := -( -0 => x"0b0b0b0b", -1 => x"82700b0b", -2 => x"80cfd80c", -3 => x"3a0b0b80", -4 => x"c6d00400", -5 => x"00000000", -6 => x"00000000", -7 => x"00000000", -8 => x"80088408", -9 => x"88080b0b", -10 => x"80c7972d", -11 => x"880c840c", -12 => x"800c0400", -13 => x"00000000", -14 => x"00000000", -15 => x"00000000", -16 => x"71fd0608", -17 => x"72830609", -18 => x"81058205", -19 => x"832b2a83", -20 => x"ffff0652", -21 => x"04000000", -22 => x"00000000", -23 => x"00000000", -24 => x"71fd0608", -25 => x"83ffff73", -26 => x"83060981", -27 => x"05820583", -28 => x"2b2b0906", -29 => x"7383ffff", -30 => x"0b0b0b0b", -31 => x"83a70400", -32 => x"72098105", -33 => x"72057373", -34 => x"09060906", -35 => x"73097306", -36 => x"070a8106", -37 => x"53510400", -38 => x"00000000", -39 => x"00000000", -40 => x"72722473", -41 => x"732e0753", -42 => x"51040000", -43 => x"00000000", -44 => x"00000000", -45 => x"00000000", -46 => x"00000000", -47 => x"00000000", -48 => x"71737109", -49 => x"71068106", -50 => x"30720a10", -51 => x"0a720a10", -52 => x"0a31050a", -53 => x"81065151", -54 => x"53510400", -55 => x"00000000", -56 => x"72722673", -57 => x"732e0753", -58 => x"51040000", -59 => x"00000000", -60 => x"00000000", -61 => x"00000000", -62 => x"00000000", -63 => x"00000000", -64 => x"00000000", -65 => x"00000000", -66 => x"00000000", -67 => x"00000000", -68 => x"00000000", -69 => x"00000000", -70 => x"00000000", -71 => x"00000000", -72 => x"0b0b0b88", -73 => x"c4040000", -74 => x"00000000", -75 => x"00000000", -76 => x"00000000", -77 => x"00000000", -78 => x"00000000", -79 => x"00000000", -80 => x"720a722b", -81 => x"0a535104", -82 => x"00000000", -83 => x"00000000", -84 => x"00000000", -85 => x"00000000", -86 => x"00000000", -87 => x"00000000", -88 => x"72729f06", -89 => x"0981050b", -90 => x"0b0b88a7", -91 => x"05040000", -92 => x"00000000", -93 => x"00000000", -94 => x"00000000", -95 => x"00000000", -96 => x"72722aff", -97 => x"739f062a", -98 => x"0974090a", -99 => x"8106ff05", -100 => x"06075351", -101 => x"04000000", -102 => x"00000000", -103 => x"00000000", -104 => x"71715351", -105 => x"020d0406", -106 => x"73830609", -107 => x"81058205", -108 => x"832b0b2b", -109 => x"0772fc06", -110 => x"0c515104", -111 => x"00000000", -112 => x"72098105", -113 => x"72050970", -114 => x"81050906", -115 => x"0a810653", -116 => x"51040000", -117 => x"00000000", -118 => x"00000000", -119 => x"00000000", -120 => x"72098105", -121 => x"72050970", -122 => x"81050906", -123 => x"0a098106", -124 => x"53510400", -125 => x"00000000", -126 => x"00000000", -127 => x"00000000", -128 => x"71098105", -129 => x"52040000", -130 => x"00000000", -131 => x"00000000", -132 => x"00000000", -133 => x"00000000", -134 => x"00000000", -135 => x"00000000", -136 => x"72720981", -137 => x"05055351", -138 => x"04000000", -139 => x"00000000", -140 => x"00000000", -141 => x"00000000", -142 => x"00000000", -143 => x"00000000", -144 => x"72097206", -145 => x"73730906", -146 => x"07535104", -147 => x"00000000", -148 => x"00000000", -149 => x"00000000", -150 => x"00000000", -151 => x"00000000", -152 => x"71fc0608", -153 => x"72830609", -154 => x"81058305", -155 => x"1010102a", -156 => x"81ff0652", -157 => x"04000000", -158 => x"00000000", -159 => x"00000000", -160 => x"71fc0608", -161 => x"0b0b80cf", -162 => x"c4738306", -163 => x"10100508", -164 => x"060b0b0b", -165 => x"88aa0400", -166 => x"00000000", -167 => x"00000000", -168 => x"80088408", -169 => x"88087575", -170 => x"0b0b0b8b", -171 => x"9f2d5050", -172 => x"80085688", -173 => x"0c840c80", -174 => x"0c510400", -175 => x"00000000", -176 => x"80088408", -177 => x"88087575", -178 => x"0b0b0b8b", -179 => x"e32d5050", -180 => x"80085688", -181 => x"0c840c80", -182 => x"0c510400", -183 => x"00000000", -184 => x"72097081", -185 => x"0509060a", -186 => x"8106ff05", -187 => x"70547106", -188 => x"73097274", -189 => x"05ff0506", -190 => x"07515151", -191 => x"04000000", -192 => x"72097081", -193 => x"0509060a", -194 => x"098106ff", -195 => x"05705471", -196 => x"06730972", -197 => x"7405ff05", -198 => x"06075151", -199 => x"51040000", -200 => x"05ff0504", -201 => x"00000000", -202 => x"00000000", -203 => x"00000000", -204 => x"00000000", -205 => x"00000000", -206 => x"00000000", -207 => x"00000000", -208 => x"810b0b0b", -209 => x"80cfd40c", -210 => x"51040000", -211 => x"00000000", -212 => x"00000000", -213 => x"00000000", -214 => x"00000000", -215 => x"00000000", -216 => x"71810552", -217 => x"04000000", -218 => x"00000000", -219 => x"00000000", -220 => x"00000000", -221 => x"00000000", -222 => x"00000000", -223 => x"00000000", -224 => x"00000000", -225 => x"00000000", -226 => x"00000000", -227 => x"00000000", -228 => x"00000000", -229 => x"00000000", -230 => x"00000000", -231 => x"00000000", -232 => x"02840572", -233 => x"10100552", -234 => x"04000000", -235 => x"00000000", -236 => x"00000000", -237 => x"00000000", -238 => x"00000000", -239 => x"00000000", -240 => x"00000000", -241 => x"00000000", -242 => x"00000000", -243 => x"00000000", -244 => x"00000000", -245 => x"00000000", -246 => x"00000000", -247 => x"00000000", -248 => x"717105ff", -249 => x"05715351", -250 => x"020d0400", -251 => x"00000000", -252 => x"00000000", -253 => x"00000000", -254 => x"00000000", -255 => x"00000000", -256 => x"82c53f80", -257 => x"c6d93f04", -258 => x"10101010", -259 => x"10101010", -260 => x"10101010", -261 => x"10101010", -262 => x"10101010", -263 => x"10101010", -264 => x"10101010", -265 => x"10101053", -266 => x"51047381", -267 => x"ff067383", -268 => x"06098105", -269 => x"83051010", -270 => x"102b0772", -271 => x"fc060c51", -272 => x"51043c04", -273 => x"72728072", -274 => x"8106ff05", -275 => x"09720605", -276 => x"71105272", -277 => x"0a100a53", -278 => x"72ed3851", -279 => x"51535104", -280 => x"fe3d0d0b", -281 => x"0b80dfc0", -282 => x"08538413", -283 => x"0870882a", -284 => x"70810651", -285 => x"52527080", -286 => x"2ef03871", -287 => x"81ff0680", -288 => x"0c843d0d", -289 => x"04ff3d0d", -290 => x"0b0b80df", -291 => x"c0085271", -292 => x"0870882a", -293 => x"81327081", -294 => x"06515151", -295 => x"70f13873", -296 => x"720c833d", -297 => x"0d0480cf", -298 => x"d408802e", -299 => x"a43880cf", -300 => x"d808822e", -301 => x"bd388380", -302 => x"800b0b0b", -303 => x"80dfc00c", -304 => x"82a0800b", -305 => x"80dfc40c", -306 => x"8290800b", -307 => x"80dfc80c", -308 => x"04f88080", -309 => x"80a40b0b", -310 => x"0b80dfc0", -311 => x"0cf88080", -312 => x"82800b80", -313 => x"dfc40cf8", -314 => x"80808480", -315 => x"0b80dfc8", -316 => x"0c0480c0", -317 => x"a8808c0b", -318 => x"0b0b80df", -319 => x"c00c80c0", -320 => x"a880940b", -321 => x"80dfc40c", -322 => x"0b0b80cf", -323 => x"8c0b80df", -324 => x"c80c0470", -325 => x"7080dfcc", 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x"00002cf8", -2882 => x"00002d00", -2883 => x"00002d00", -2884 => x"00002d08", -2885 => x"00002d08", -2886 => x"00002d10", -2887 => x"00002d10", -2888 => x"00002d18", -2889 => x"00002d18", -2890 => x"00002d20", -2891 => x"00002d20", -2892 => x"00002d28", -2893 => x"00002d28", -2894 => x"00002d30", -2895 => x"00002d30", -2896 => x"00002d38", -2897 => x"00002d38", -2898 => x"00002d40", -2899 => x"00002d40", -2900 => x"00002d48", -2901 => x"00002d48", -2902 => x"00002d50", -2903 => x"00002d50", -2904 => x"00002d58", -2905 => x"00002d58", -2906 => x"00002d60", -2907 => x"00002d60", -2908 => x"00002d68", -2909 => x"00002d68", -2910 => x"00002d70", -2911 => x"00002d70", -2912 => x"00002d78", -2913 => x"00002d78", -2914 => x"00002d80", -2915 => x"00002d80", -2916 => x"00002d88", -2917 => x"00002d88", -2918 => x"00002d90", -2919 => x"00002d90", -2920 => x"00002d98", -2921 => x"00002d98", -2922 => x"00002da0", -2923 => x"00002da0", -2924 => x"00002da8", -2925 => x"00002da8", -2926 => x"00002db0", -2927 => x"00002db0", -2928 => x"00002db8", -2929 => x"00002db8", -2930 => x"00002dc0", -2931 => x"00002dc0", -2932 => x"00002dc8", -2933 => x"00002dc8", -2934 => x"00002dd0", -2935 => x"00002dd0", -2936 => x"00002dd8", -2937 => x"00002dd8", -2938 => x"00002de0", -2939 => x"00002de0", -2940 => x"00002de8", -2941 => x"00002de8", -2942 => x"00002df0", -2943 => x"00002df0", -2944 => x"00002df8", -2945 => x"00002df8", -2946 => x"00002e00", -2947 => x"00002e00", -2948 => x"00002e08", -2949 => x"00002e08", -2950 => x"00002e10", -2951 => x"00002e10", -2952 => x"00002e18", -2953 => x"00002e18", -2954 => x"00002e20", -2955 => x"00002e20", -2956 => x"00002e28", -2957 => x"00002e28", -2958 => x"00002e30", -2959 => x"00002e30", -2960 => x"00002e38", -2961 => x"00002e38", -2962 => x"00002e40", -2963 => x"00002e40", -2964 => x"00002e48", -2965 => x"00002e48", -2966 => x"00002e50", -2967 => x"00002e50", -2968 => x"00002e58", -2969 => x"00002e58", -2970 => x"00002e60", -2971 => x"00002e60", -2972 => x"00002e68", -2973 => x"00002e68", -2974 => x"00002e70", -2975 => x"00002e70", -2976 => x"00002e78", -2977 => x"00002e78", -2978 => x"00002e80", -2979 => x"00002e80", -2980 => x"00002e88", -2981 => x"00002e88", -2982 => x"00002e90", -2983 => x"00002e90", -2984 => x"00002e98", -2985 => x"00002e98", -2986 => x"00002ea0", -2987 => x"00002ea0", -2988 => x"00002ea8", -2989 => x"00002ea8", -2990 => x"00002eb0", -2991 => x"00002eb0", -2992 => x"00002eb8", -2993 => x"00002eb8", -2994 => x"00002ec0", -2995 => x"00002ec0", -2996 => x"00002ec8", -2997 => x"00002ec8", -2998 => x"00002ed0", -2999 => x"00002ed0", -3000 => x"00002ed8", -3001 => x"00002ed8", -3002 => x"00002ee0", -3003 => x"00002ee0", -3004 => x"00002ee8", -3005 => x"00002ee8", -3006 => x"00002ef0", -3007 => x"00002ef0", -3008 => x"00002ef8", -3009 => x"00002ef8", -3010 => x"00002f00", -3011 => x"00002f00", -3012 => x"00002f08", -3013 => x"00002f08", -3014 => x"00002f10", -3015 => x"00002f10", -3016 => x"00002f18", -3017 => x"00002f18", -3018 => x"00002f20", -3019 => x"00002f20", -3020 => x"00002f28", -3021 => x"00002f28", -3022 => x"00002f30", -3023 => x"00002f30", -3024 => x"00002f38", -3025 => x"00002f38", -3026 => x"00002f40", -3027 => x"00002f40", -3028 => x"00002f48", -3029 => x"00002f48", -3030 => x"00002f50", -3031 => x"00002f50", -3032 => x"00002f58", -3033 => x"00002f58", -3034 => x"00002f60", -3035 => x"00002f60", -3036 => x"00002f68", -3037 => x"00002f68", -3038 => x"00002f70", -3039 => x"00002f70", -3040 => x"00002f78", -3041 => x"00002f78", -3042 => x"00002f80", -3043 => x"00002f80", -3044 => x"00002f88", -3045 => x"00002f88", -3046 => x"00002f90", -3047 => x"00002f90", -3048 => x"00002f98", -3049 => x"00002f98", -3050 => x"000027b8", -3051 => x"ffffffff", -3052 => x"00000000", -3053 => x"ffffffff", -3054 => x"00000000", - others => x"00000000" -); - -begin - -mem_busy<=mem_readEnable; -- we're done on the cycle after we serve the read request - -process (clk, areset) -begin - if areset = '1' then - elsif (clk'event and clk = '1') then - if (mem_writeEnable = '1') then - ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit)))) := mem_write; - end if; - if (mem_readEnable = '1') then - mem_read <= ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit)))); - end if; - end if; -end process; - - - - -end dram_arch; diff --git a/zpu/hdl/zpu4/src/zpu_config_trace.vhd b/zpu/hdl/zpu4/src/zpu_config_trace.vhd deleted file mode 100644 index d765d9a..0000000 --- a/zpu/hdl/zpu4/src/zpu_config_trace.vhd +++ /dev/null @@ -1,17 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -package zpu_config is - - constant Generate_Trace : boolean := true; - constant wordPower : integer := 5; - -- during simulation, set this to '0' to get matching trace.txt - constant DontCareValue : std_logic := '0'; - -- Clock frequency in MHz. - constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64"; - constant maxAddrBitIncIO : integer := 27; - constant maxAddrBitDRAM : integer := 16; - constant maxAddrBitBRAM : integer := 16; - constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"001fff8"; - -end zpu_config; diff --git a/zpu/hdl/zpu4/test/interrupt/int.bin b/zpu/hdl/zpu4/test/interrupt/int.bin index 94cbe31..282f53b 100644 Binary files a/zpu/hdl/zpu4/test/interrupt/int.bin and b/zpu/hdl/zpu4/test/interrupt/int.bin differ diff --git a/zpu/hdl/zpu4/test/interrupt/int.c b/zpu/hdl/zpu4/test/interrupt/int.c index 1b6ec01..6ab28f7 100644 --- a/zpu/hdl/zpu4/test/interrupt/int.c +++ b/zpu/hdl/zpu4/test/interrupt/int.c @@ -4,11 +4,15 @@ #include -int counter; +volatile int counter; /* Example of single, fixed interval non-maskable, nested interrupt. The interrupt signal is * held high for enough cycles to guarantee that it will be noticed, i.e. longer than * any io access + 4 cycles roughly. + * + * Any non-trivial interrupt controller would have support for + * acknowledging interrupts(i.e. keep interrupts asserted until + * software acknowledges them via memory mapped IO). */ void _zpu_interrupt(void) { @@ -29,6 +33,7 @@ int main(int argc, char **argv) } else { puts("Got interrupt\n"); + t=counter; } } diff --git a/zpu/hdl/zpu4/test/interrupt/int.elf b/zpu/hdl/zpu4/test/interrupt/int.elf index a550987..346d148 100644 Binary files a/zpu/hdl/zpu4/test/interrupt/int.elf and b/zpu/hdl/zpu4/test/interrupt/int.elf differ diff --git a/zpu/hdl/zpu4/test/interrupt/int.ram b/zpu/hdl/zpu4/test/interrupt/int.ram index bcb424a..6751ec2 100644 --- a/zpu/hdl/zpu4/test/interrupt/int.ram +++ b/zpu/hdl/zpu4/test/interrupt/int.ram @@ -2,7 +2,7 @@ 1 => x"82700b0b", 2 => x"80cfe00c", 3 => x"3a0b0b80", -4 => x"c6e10400", +4 => x"c6e00400", 5 => x"00000000", 6 => x"00000000", 7 => x"00000000", @@ -169,7 +169,7 @@ 168 => x"80088408", 169 => x"88087575", 170 => x"0b0b0b8b", -171 => x"ac2d5050", +171 => x"ab2d5050", 172 => x"80085688", 173 => x"0c840c80", 174 => x"0c510400", @@ -177,7 +177,7 @@ 176 => x"80088408", 177 => x"88087575", 178 => x"0b0b0b8b", -179 => x"f02d5050", +179 => x"ef2d5050", 180 => x"80085688", 181 => x"0c840c80", 182 => x"0c510400", @@ -255,7 +255,7 @@ 254 => x"00000000", 255 => x"00000000", 256 => x"82c53f80", -257 => x"c6e73f04", +257 => x"c6e63f04", 258 => x"10101010", 259 => x"10101010", 260 => x"10101010", @@ -346,2192 +346,2192 @@ 345 => x"dfc4510b", 346 => x"0b0bf594", 347 => x"3f500404", -348 => x"80dfe008", -349 => x"810580df", -350 => x"e00c04fe", -351 => x"3d0d80df", -352 => x"e0087054", -353 => x"5272722e", -354 => x"953880cf", -355 => x"9c5182bb", -356 => x"3f80dfe0", -357 => x"08527272", -358 => x"2e098106", -359 => x"ed3880cf", -360 => x"ac5182a7", -361 => x"3f80dfe0", -362 => x"0852eb39", -363 => x"fb3d0d77", -364 => x"79555580", -365 => x"56757524", -366 => x"ab388074", -367 => x"249d3880", -368 => x"53735274", -369 => x"5180e13f", -370 => x"80085475", -371 => x"802e8538", -372 => x"80083054", -373 => x"73800c87", -374 => x"3d0d0473", -375 => x"30768132", -376 => x"5754dc39", -377 => x"74305581", -378 => x"56738025", -379 => x"d238ec39", -380 => x"fa3d0d78", -381 => x"7a575580", -382 => x"57767524", -383 => x"a438759f", -384 => x"2c548153", -385 => x"75743274", -386 => x"31527451", -387 => x"9b3f8008", -388 => x"5476802e", -389 => x"85388008", -390 => x"30547380", -391 => x"0c883d0d", -392 => x"04743055", -393 => x"8157d739", -394 => x"fc3d0d76", -395 => x"78535481", -396 => x"53807473", -397 => x"26525572", -398 => x"802e9838", -399 => x"70802eab", -400 => x"38807224", -401 => x"a6387110", -402 => x"73107572", -403 => x"26535452", -404 => x"72ea3873", -405 => x"51788338", -406 => x"74517080", -407 => x"0c863d0d", -408 => x"04720a10", -409 => x"0a720a10", -410 => x"0a535372", -411 => x"802ee438", -412 => x"717426ed", -413 => x"38737231", -414 => x"75740774", -415 => x"0a100a74", -416 => x"0a100a55", -417 => x"555654e3", -418 => x"39f73d0d", -419 => x"7c705253", -420 => x"80fd3f72", -421 => x"54800855", -422 => x"0b0b80cf", -423 => x"b8568157", -424 => x"80088105", -425 => x"5a8b3de4", -426 => x"11595382", -427 => x"59f41352", -428 => x"7b881108", -429 => x"525381b4", -430 => x"3f800830", -431 => x"70800807", -432 => x"9f2c8a07", -433 => x"800c538b", -434 => x"3d0d04f6", -435 => x"3d0d7c80", -436 => x"cfec0871", -437 => x"535553b7", -438 => x"3f725580", -439 => x"08560b0b", -440 => x"80cfb857", -441 => x"81588008", -442 => x"81055b8c", -443 => x"3de4115a", -444 => x"53825af4", -445 => x"13528814", -446 => x"085180f0", -447 => x"3f800830", -448 => x"70800807", -449 => x"9f2c8a07", -450 => x"800c548c", -451 => x"3d0d0470", -452 => x"70707075", -453 => x"70718306", -454 => x"53555270", -455 => x"b4387170", -456 => x"087009f7", -457 => x"fbfdff12", -458 => x"06f88482", -459 => x"81800654", -460 => x"5253719b", -461 => x"38841370", -462 => x"087009f7", -463 => x"fbfdff12", -464 => x"06f88482", -465 => x"81800654", -466 => x"52537180", -467 => x"2ee73872", -468 => x"52713353", -469 => x"72802e8a", -470 => x"38811270", -471 => x"33545272", -472 => x"f8387174", -473 => x"31800c50", -474 => x"50505004", -475 => x"f23d0d60", -476 => x"62881108", -477 => x"7058565f", -478 => x"5a73802e", -479 => x"818c388c", -480 => x"1a227083", -481 => x"2a813281", -482 => x"06565874", -483 => x"8638901a", -484 => x"08913879", -485 => x"5190b73f", -486 => x"ff558008", -487 => x"80ec388c", -488 => x"1a22587d", -489 => x"08558078", -490 => x"83ffff06", -491 => x"700a100a", -492 => x"8106415c", -493 => x"577e772e", -494 => x"80d73876", -495 => x"90387408", -496 => x"84160888", -497 => x"17575856", -498 => x"76802ef2", -499 => x"38765488", -500 => x"80772784", -501 => x"38888054", -502 => x"73537552", -503 => x"9c1a0851", -504 => x"a41a0858", -505 => x"772d800b", -506 => x"80082582", -507 => x"e0388008", -508 => x"16778008", -509 => x"317f8805", -510 => x"08800831", -511 => x"70618805", -512 => x"0c5b5856", -513 => x"78ffb438", -514 => x"80557480", -515 => x"0c903d0d", -516 => x"047a8132", -517 => x"81067740", -518 => x"5675802e", -519 => x"81bd3876", -520 => x"90387408", -521 => x"84160888", -522 => x"17575859", -523 => x"76802ef2", -524 => x"38881a08", -525 => x"7883ffff", -526 => x"0670892a", -527 => x"81065659", -528 => x"5673802e", -529 => x"82f83875", -530 => x"77278b38", -531 => x"77872a81", -532 => x"065c7b82", -533 => x"b5387676", -534 => x"27833876", -535 => x"56755378", -536 => x"52790851", -537 => x"85833f88", -538 => x"1a087631", -539 => x"881b0c79", -540 => x"08167a0c", -541 => x"76567519", -542 => x"7777317f", -543 => x"88050878", -544 => x"31706188", -545 => x"050c4158", -546 => x"597e802e", -547 => x"fefa388c", -548 => x"1a2258ff", -549 => x"8a397879", -550 => x"547c537b", -551 => x"525684c9", -552 => x"3f881a08", -553 => x"7931881b", -554 => x"0c790819", -555 => x"7a0c7c76", -556 => x"315d7c8e", -557 => x"3879518f", -558 => x"f23f8008", -559 => x"818f3880", -560 => x"085f751c", -561 => x"7777317f", -562 => x"88050878", -563 => x"31706188", -564 => x"050c5d58", -565 => x"5c7a802e", -566 => x"feae3876", -567 => x"81833874", -568 => x"08841608", -569 => x"88175758", -570 => x"5c76802e", -571 => x"f2387653", -572 => x"8a527b51", -573 => x"82d33f80", -574 => x"087c3181", -575 => x"055d8008", -576 => x"84388117", -577 => x"5d815f7c", -578 => x"59767d27", -579 => x"83387659", -580 => x"941a0888", -581 => x"1b081157", -582 => x"58807a08", -583 => x"5c54901a", -584 => x"087b2783", -585 => x"38815475", -586 => x"79258438", -587 => x"73ba3877", -588 => x"7924fee2", -589 => x"3877537b", -590 => x"529c1a08", -591 => x"51a41a08", -592 => x"59782d80", -593 => x"08568008", -594 => x"8024fee2", -595 => x"388c1a22", -596 => x"80c0075e", -597 => x"7d8c1b23", -598 => x"ff557480", -599 => x"0c903d0d", -600 => x"047effa3", -601 => x"38ff8739", -602 => x"75537b52", -603 => x"7a5182f9", -604 => x"3f790816", -605 => x"7a0c7951", -606 => x"8eb13f80", -607 => x"08cf387c", -608 => x"76315d7c", -609 => x"febc38fe", -610 => x"ac39901a", -611 => x"087a0871", -612 => x"31781170", -613 => x"565a5752", -614 => x"80cfec08", -615 => x"5184943f", -616 => x"8008802e", -617 => x"ffa73880", -618 => x"08901b0c", -619 => x"8008167a", -620 => x"0c77941b", -621 => x"0c76881b", -622 => x"0c7656fd", -623 => x"99397908", -624 => x"58901a08", -625 => x"78278338", -626 => x"81547577", -627 => x"27843873", -628 => x"b338941a", -629 => x"08547377", -630 => x"2680d338", -631 => x"73537852", -632 => x"9c1a0851", -633 => x"a41a0858", -634 => x"772d8008", -635 => x"56800880", -636 => x"24fd8338", -637 => x"8c1a2280", -638 => x"c0075e7d", -639 => x"8c1b23ff", -640 => x"55fed739", -641 => x"75537852", -642 => x"775181dd", -643 => x"3f790816", -644 => x"7a0c7951", -645 => x"8d953f80", -646 => x"08802efc", -647 => x"d9388c1a", -648 => x"2280c007", -649 => x"5e7d8c1b", -650 => x"23ff55fe", -651 => x"ad397677", -652 => x"54795378", -653 => x"525681b1", -654 => x"3f881a08", -655 => x"7731881b", -656 => x"0c790817", -657 => x"7a0cfcae", -658 => x"39fa3d0d", -659 => x"7a790288", -660 => x"05a70533", -661 => x"55535483", -662 => x"742780df", -663 => x"38718306", -664 => x"517080d7", -665 => x"38717157", -666 => x"55835175", -667 => x"82802913", -668 => x"ff125256", -669 => x"708025f3", -670 => x"38837427", -671 => x"bc387408", -672 => x"76327009", -673 => x"f7fbfdff", -674 => x"1206f884", -675 => x"82818006", -676 => x"51517080", -677 => x"2e983874", -678 => x"51805270", -679 => x"33577277", -680 => x"2eb93881", -681 => x"11811353", -682 => x"51837227", -683 => x"ee38fc14", -684 => x"84165654", -685 => x"738326c6", -686 => x"387452ff", -687 => x"145170ff", -688 => x"2e973871", -689 => x"33547274", -690 => x"2e983881", -691 => x"12ff1252", -692 => x"5270ff2e", -693 => x"098106eb", -694 => x"38805170", -695 => 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x"38767a23", +2386 => x"84195880", +2387 => x"70565798", +2388 => x"56741870", +2389 => x"3370782b", +2390 => x"79078118", +2391 => x"f81a5a58", +2392 => x"59515484", +2393 => x"7524ea38", +2394 => x"76821b23", +2395 => x"88195880", +2396 => x"70565798", +2397 => x"56741870", +2398 => x"3370782b", +2399 => x"79078118", +2400 => x"f81a5a58", +2401 => x"59515484", +2402 => x"7524ea38", +2403 => x"76841b0c", +2404 => x"8c195880", +2405 => x"70565798", +2406 => x"56741870", +2407 => x"3370782b", +2408 => x"79078118", +2409 => x"f81a5a58", +2410 => x"59515484", +2411 => x"7524ea38", +2412 => x"76881b23", +2413 => x"90195880", +2414 => x"70565798", +2415 => x"56741870", +2416 => x"3370782b", +2417 => x"79078118", +2418 => x"f81a5a58", +2419 => x"59515484", +2420 => x"7524ea38", +2421 => x"768a1b23", +2422 => x"94195880", +2423 => x"70565798", +2424 => x"56741870", +2425 => x"3370782b", +2426 => x"79078118", +2427 => x"f81a5a58", +2428 => x"59515484", +2429 => x"7524ea38", +2430 => x"768c1b23", +2431 => x"98195880", +2432 => x"70565798", +2433 => x"56741870", +2434 => x"3370782b", +2435 => x"79078118", +2436 => x"f81a5a58", +2437 => x"59515484", +2438 => x"7524ea38", +2439 => x"768e1b23", +2440 => x"9c195880", +2441 => x"705657b8", +2442 => x"56741870", +2443 => x"3370782b", +2444 => x"79078118", +2445 => x"f81a5a58", +2446 => x"595a5488", +2447 => x"7524ea38", +2448 => x"76901b0c", +2449 => x"8b3d0d04", +2450 => x"e93d0d6a", +2451 => x"80dfdc08", +2452 => x"57577593", +2453 => x"3880c080", +2454 => x"0b84180c", +2455 => x"75ac180c", +2456 => x"75800c99", +2457 => x"3d0d0489", +2458 => x"3d70556a", +2459 => x"54558a52", +2460 => x"993dffbc", +2461 => x"0551ffbb", +2462 => x"c93f8008", +2463 => x"77537552", +2464 => x"56fd953f", +2465 => x"bc3f7780", +2466 => x"080c7580", +2467 => x"0c993d0d", +2468 => x"04fc3d0d", +2469 => x"815480df", +2470 => x"dc088838", +2471 => x"73800c86", +2472 => x"3d0d0476", +2473 => x"5397b952", +2474 => x"863dfc05", +2475 => x"51ffbb92", +2476 => x"3f800854", +2477 => x"8c3f7480", +2478 => x"080c7380", +2479 => x"0c863d0d", +2480 => x"0480cfec", +2481 => x"08800c04", +2482 => x"f73d0d7b", +2483 => x"80cfec08", +2484 => x"82c81108", +2485 => x"5a545a77", +2486 => x"802e80da", +2487 => x"38818818", +2488 => x"841908ff", +2489 => x"0581712b", +2490 => x"59555980", +2491 => x"742480ea", +2492 => x"38807424", +2493 => x"b5387382", +2494 => x"2b781188", +2495 => x"05565681", +2496 => x"80190877", +2497 => x"06537280", +2498 => x"2eb63878", +2499 => x"16700853", +2500 => x"53795174", +2501 => x"0853722d", +2502 => x"ff14fc17", +2503 => x"fc177981", +2504 => x"2c5a5757", +2505 => x"54738025", +2506 => x"d6387708", +2507 => x"5877ffad", +2508 => x"3880cfec", +2509 => x"0853bc13", +2510 => x"08a53879", +2511 => x"51f8e53f", +2512 => x"74085372", +2513 => x"2dff14fc", +2514 => x"17fc1779", +2515 => x"812c5a57", +2516 => x"57547380", +2517 => x"25ffa838", +2518 => x"d1398057", +2519 => x"ff933972", +2520 => x"51bc1308", +2521 => x"54732d79", +2522 => x"51f8b93f", +2523 => x"707080df", +2524 => x"b80bfc05", +2525 => x"70085252", +2526 => x"70ff2e91", +2527 => x"38702dfc", +2528 => x"12700852", +2529 => x"5270ff2e", +2530 => x"098106f1", +2531 => x"38505004", +2532 => x"04ffbaff", +2533 => x"3f040000", 2534 => x"00000040", 2535 => x"476f7420", 2536 => x"696e7465", -- cgit v1.1 From 03472db15fd0f12cb019bc9158cd6d43aa5fc725 Mon Sep 17 00:00:00 2001 From: oharboe Date: Thu, 8 May 2008 06:46:38 +0000 Subject: wip from jurij.kostasenko --- wip/.project | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 wip/.project diff --git a/wip/.project b/wip/.project new file mode 100644 index 0000000..d645e5b --- /dev/null +++ b/wip/.project @@ -0,0 +1,11 @@ + + + wip + + + + + + + + -- cgit v1.1 From e9b757cdba91ceb77523f5d9bb092b8c723fabbb Mon Sep 17 00:00:00 2001 From: oharboe Date: Thu, 8 May 2008 07:32:52 +0000 Subject: Mike Frysinger found this file which is not needed. --- zpu/sw/simulator/gmon.out | Bin 120053 -> 0 bytes 1 file changed, 0 insertions(+), 0 deletions(-) delete mode 100644 zpu/sw/simulator/gmon.out diff --git a/zpu/sw/simulator/gmon.out b/zpu/sw/simulator/gmon.out deleted file mode 100644 index c49b3d7..0000000 Binary files a/zpu/sw/simulator/gmon.out and /dev/null differ -- cgit v1.1 -- cgit v1.1 From 6647b91cf267e7e155c95c6adbcfbc43f083356b Mon Sep 17 00:00:00 2001 From: oharboe Date: Tue, 17 Jun 2008 22:09:13 +0000 Subject: * io.vhd: fix address comparsion and added numerous outputs during simulation to make things a bit easier * zpu_config.vhd: do not use hardcoded startSp, allows more easily tinkering w/RAM size --- zpu/ChangeLog | 7 +++++++ zpu/hdl/example/zpu_config.vhd | 4 +++- zpu/hdl/zpu4/src/io.vhd | 35 ++++++++++++++++++++++------------- 3 files changed, 32 insertions(+), 14 deletions(-) diff --git a/zpu/ChangeLog b/zpu/ChangeLog index e7bbb93..c5ab833 100644 --- a/zpu/ChangeLog +++ b/zpu/ChangeLog @@ -1,3 +1,10 @@ +2008-05-06 Miguel Freitas + + * io.vhd: fix address comparsion and added numerous outputs + during simulation to make things a bit easier + * zpu_config.vhd: do not use hardcoded startSp, allows more easily + tinkering w/RAM size + 2008-05-06 Øyvind Harboe * Small ZPU now supports interrupts * added simulation example demonstrating interrupts diff --git a/zpu/hdl/example/zpu_config.vhd b/zpu/hdl/example/zpu_config.vhd index a59ac8e..dc2b666 100644 --- a/zpu/hdl/example/zpu_config.vhd +++ b/zpu/hdl/example/zpu_config.vhd @@ -1,6 +1,7 @@ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; package zpu_config is -- generate trace output @@ -16,5 +17,6 @@ package zpu_config is -- start byte address of stack. -- point to top of RAM - 2*words - constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"1fffff8"; + constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := + conv_std_logic_vector((2**(maxAddrBitBRAM+1))/4-8, maxAddrBitIncIO+1); end zpu_config; diff --git a/zpu/hdl/zpu4/src/io.vhd b/zpu/hdl/zpu4/src/io.vhd index 9e65929..f71f51d 100644 --- a/zpu/hdl/zpu4/src/io.vhd +++ b/zpu/hdl/zpu4/src/io.vhd @@ -37,6 +37,7 @@ signal timer_we : std_logic; signal serving : std_logic; file l_file : TEXT open write_mode is log_file; +constant lowAddrBits: std_logic_vector(minAddrBit-1 downto 0) := (others=>'0'); begin @@ -54,42 +55,50 @@ begin process(areset, clk) begin + taddr := (others => '0'); + taddr(maxAddrBit downto minAddrBit) := addr; + if (areset = '1') then -- timer_we <= '0'; elsif (clk'event and clk = '1') then -- timer_we <= '0'; if writeEnable = '1' then - -- external interface (fixed address) - -- extend compare to avoid waring messages - if ("000" & addr)=x"2028003" then + -- external interface (fixed address) + -- extend compare to avoid waring messages + if ("1" & addr & lowAddrBits)=x"80a000c" then + report "Write to UART[0]" & " :0x" & hstr(write); -- Write to UART -- report "" & character'image(conv_integer(memBint)) severity note; print(l_file, character'val(to_integer(unsigned(write)))); elsif addr(12)='1' then + report "Write to TIMER" & " :0x" & hstr(write); -- report "xxx" severity failure; -- timer_we <= '1'; else print(l_file, character'val(to_integer(unsigned(write)))); - -- report "Illegal IO write" severity warning; + report "Illegal IO write @" & "0x" & hstr(taddr) severity warning; end if; end if; read <= (others => '0'); if (readEnable = '1') then - -- extend compare to avoid waring messages - if ("000" & addr)=x"0001001" then - read <= (0=>'1', others => '0'); -- recieve empty + -- extend compare to avoid waring messages + if ("1" & addr & lowAddrBits)=x"80a000c" then + report "Read UART[0]"; + read(8) <= '0'; -- output fifo not full + read(9) <= '1'; -- receiver not empty + elsif ("1" & addr & lowAddrBits)=x"80a0010" then + report "Read UART[1]"; + read(8) <= '1'; -- receiver not empty + read(7 downto 0) <= (others => '0'); elsif addr(12)='1' then + report "Read TIMER"; read(7 downto 0) <= timer_read; elsif addr(11)='1' then + report "Read ZPU Freq"; read(7 downto 0) <= ZPU_Frequency; - -- extend compare to avoid waring messages - elsif ("000" & addr)=x"2028003" then - read <= (others => '0'); else - read <= (others => '0'); - read(8) <= '1'; - -- report "Illegal IO read" severity warning; + report "Illegal IO read @" & "0x" & hstr(taddr) severity warning; end if; end if; end if; -- cgit v1.1 From 0711a2b4fc2dec8bf65e5821095bed895976b83a Mon Sep 17 00:00:00 2001 From: oharboe Date: Wed, 18 Jun 2008 09:22:21 +0000 Subject: * Various ZY2000 vhdl files of more general interest made available as part of the ZPU project under the same license(FreeBSD). Files should have headers updated. --- misc/ChangeLog | 5 + misc/arm7/src/arm7pkg.vhd | 31 + misc/arm7/src/arm7wb.vhd | 236 ++++++ misc/ddrsdram/simscripts/ddr_tb.do | 16 + misc/ddrsdram/simscripts/ddr_top.do | 104 +++ misc/ddrsdram/simsrc/ddr_tb.vhd | 301 ++++++++ misc/ddrsdram/src/ddr_pkg.vhd | 107 +++ misc/ddrsdram/src/ddr_top.vhd | 743 +++++++++++++++++++ misc/ddrsdram/src/mt46v16m16.vhd | 1320 +++++++++++++++++++++++++++++++++ misc/readme.txt | 20 + misc/wishbone/src/atomic32_access.vhd | 132 ++++ misc/wishbone/src/wishbone_pkg.vhd | 52 ++ 12 files changed, 3067 insertions(+) create mode 100644 misc/ChangeLog create mode 100644 misc/arm7/src/arm7pkg.vhd create mode 100644 misc/arm7/src/arm7wb.vhd create mode 100644 misc/ddrsdram/simscripts/ddr_tb.do create mode 100644 misc/ddrsdram/simscripts/ddr_top.do create mode 100644 misc/ddrsdram/simsrc/ddr_tb.vhd create mode 100644 misc/ddrsdram/src/ddr_pkg.vhd create mode 100644 misc/ddrsdram/src/ddr_top.vhd create mode 100644 misc/ddrsdram/src/mt46v16m16.vhd create mode 100644 misc/readme.txt create mode 100644 misc/wishbone/src/atomic32_access.vhd create mode 100644 misc/wishbone/src/wishbone_pkg.vhd diff --git a/misc/ChangeLog b/misc/ChangeLog new file mode 100644 index 0000000..3225839 --- /dev/null +++ b/misc/ChangeLog @@ -0,0 +1,5 @@ +2008-06-18 Øyvind Harboe + + * Various ZY2000 vhdl files of more general interest made + available as part of the ZPU project under the same + license(FreeBSD). Files should have headers updated. diff --git a/misc/arm7/src/arm7pkg.vhd b/misc/arm7/src/arm7pkg.vhd new file mode 100644 index 0000000..855fbdb --- /dev/null +++ b/misc/arm7/src/arm7pkg.vhd @@ -0,0 +1,31 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library work; +use work.wishbone_pkg.all; + +package arm7 is + + component arm7wb + generic( + simulate_io_time : boolean := false); + port ( areset : in std_logic; + cpu_clk : in std_logic; + cpu_clk_2x : in std_logic; + cpu_a_p : in std_logic_vector(23 downto 1); + cpu_wr_n_p : in std_logic_vector(1 downto 0); + cpu_cs_n_p : in std_logic_vector(3 downto 1); + cpu_oe_n_p : in std_logic; + cpu_d_p : inout std_logic_vector(15 downto 0); + cpu_wait_n_p : out std_logic; + + arm7_debug : out std_logic; + arm7_debug2 : out std_logic; + + wb_o : out wishbone_bus_in; + wb_i : in wishbone_bus_out); + end component; + +end arm7; + + \ No newline at end of file diff --git a/misc/arm7/src/arm7wb.vhd b/misc/arm7/src/arm7wb.vhd new file mode 100644 index 0000000..3366352 --- /dev/null +++ b/misc/arm7/src/arm7wb.vhd @@ -0,0 +1,236 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library work; +use work.phi_config.all; +use work.wishbone_pkg.all; + +entity arm7wb is + generic( + simulate_io_time : boolean := false); + port ( areset : in std_logic; + cpu_clk : in std_logic; + cpu_clk_2x : in std_logic; + cpu_a_p : in std_logic_vector(23 downto 1); + cpu_wr_n_p : in std_logic_vector(1 downto 0); + cpu_cs_n_p : in std_logic_vector(3 downto 1); + cpu_oe_n_p : in std_logic; + cpu_d_p : inout std_logic_vector(15 downto 0); + cpu_wait_n_p : out std_logic; + + arm7_debug : out std_logic; + arm7_debug2 : out std_logic; + + wb_o : out wishbone_bus_in; + wb_i : in wishbone_bus_out); +end arm7wb; + +architecture behave of arm7wb is + +type cpu_state_type is (cpu_idle, cpu_cs, cpu_end); + +-- Input simulated delay +signal cpu_wr_n_p_del : std_logic_vector(1 downto 0); +signal cpu_a_p_del : std_logic_vector(23 downto 1); +signal cpu_d_p_del : std_logic_vector(15 downto 0); +signal cpu_cs_n_p_del : std_logic_vector(3 downto 1); +signal cpu_oe_n_p_del : std_logic; + +-- Clock phase detect signals +signal cpu_clk_toggle : std_logic; +signal cpu_clk_smp1 : std_logic; +signal cpu_clk_smp2 : std_logic; +signal cpu_clk_phase : std_logic; + +-- Internal version of control signal (for feedback) +signal arm7_din_int : std_logic_vector(15 downto 0); +signal arm7_dout_int : std_logic_vector(15 downto 0); +signal arm7_a_int : std_logic_vector(23 downto 1); +signal arm7_we_int : std_logic_vector(1 downto 0); +signal cyc_int : std_logic; +signal we_int : std_logic; +signal adr_reg : std_logic_vector(25 downto 24); + +-- Input sampled +signal cpu_a_smp : std_logic_vector(23 downto 1); +signal cpu_d_smp : std_logic_vector(15 downto 0); +signal cpu_cs_n : std_logic_vector(3 downto 1); +signal cpu_oe_n : std_logic; +signal cpu_wr_n : std_logic_vector(1 downto 0); + +-- Main FSM +signal cpu_state : cpu_state_type; + +constant Clock_2_Out : time := 5.5 ns; +constant Input_Setup : time := 2.5 ns; + +begin + + arm7_dout_int <= wb_i.dat(15 downto 0) when (arm7_a_int(1) = '0') else wb_i.dat(31 downto 16); + arm7_debug <= cpu_oe_n; + arm7_debug2 <= cpu_wr_n(0); + + -- Generate 64 MBytes address based on 3 CS_N signals from CPU + -- Memory map FPGA internal + -- 0x00000000 DDR 32 MBytes (CS_N2 and CS_N3) + -- 0x00200000 FPGA/Ethernet (CS_N1) + wb_o.adr(31 downto 26) <= "000000"; + wb_o.adr(25 downto 24) <= adr_reg; + wb_o.adr(23 downto 1) <= arm7_a_int(23 downto 1); + wb_o.adr(0) <= '0'; + + wb_o.dat <= (x"0000" & arm7_din_int) when (arm7_a_int(1) = '0') else (arm7_din_int & x"0000"); + wb_o.sel <= ("00" & arm7_we_int) when (arm7_a_int(1) = '0') else (arm7_we_int & "00"); + + wb_o.cyc <= cyc_int; + wb_o.stb <= cyc_int; + wb_o.we <= cpu_oe_n; + + iotimingon: + if simulate_io_time generate + begin + cpu_wr_n_p_del <= transport "XX" after 0 ns, cpu_wr_n_p after Input_Setup; + cpu_a_p_del <= transport "XXXXXXXXXXXXXXXXXXXXXXX" after 0 ns, cpu_a_p after Input_Setup; + cpu_d_p_del <= transport "XXXXXXXXXXXXXXXX" after 0 ns, cpu_d_p after Input_Setup; + cpu_cs_n_p_del <= transport "XXX" after 0 ns, cpu_cs_n_p after Input_Setup; + cpu_oe_n_p_del <= transport 'X' after 0 ns, cpu_oe_n_p after Input_Setup; + end generate; + + iotimingoff: + if not simulate_io_time generate + begin + cpu_wr_n_p_del <= cpu_wr_n_p; + cpu_a_p_del <= cpu_a_p; + cpu_d_p_del <= cpu_d_p; + cpu_cs_n_p_del <= cpu_cs_n_p; + cpu_oe_n_p_del <= cpu_oe_n_p; + end generate; + + process(cpu_clk, areset) -- Toggle FF with 1x clock to find phase + begin + if areset = '1' then + cpu_clk_toggle <= '0'; + elsif (cpu_clk'event and cpu_clk = '1') then + cpu_clk_toggle <= not(cpu_clk_toggle); + end if; + end process; + + process(cpu_clk_2x, areset) -- Find phase relationsship between 1x and 2x clock + begin + if areset = '1' then + cpu_clk_smp1 <= '0'; + cpu_clk_smp2 <= '1'; + cpu_clk_phase <= '0'; + elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then + cpu_clk_smp1 <= cpu_clk_toggle; + cpu_clk_smp2 <= cpu_clk_smp1; + if cpu_clk_smp1 = '1' and cpu_clk_smp2 = '0' then + cpu_clk_phase <= '0'; + else + cpu_clk_phase <= not(cpu_clk_phase); + end if; + end if; + end process; + + process(cpu_clk_2x, areset) -- Sample input signals on 2x clock + begin + if areset = '1' then + cpu_d_smp <= "0000000000000000"; + cpu_cs_n <= "111"; + elsif (cpu_clk_2x = '1' and cpu_clk_2x'event) then + cpu_d_smp <= cpu_d_p_del; + cpu_cs_n <= cpu_cs_n_p_del; + end if; + end process; + + process(cpu_clk, areset) -- Sample input signals on 1x clock + begin + if areset = '1' then + cpu_a_smp <= "00000000000000000000000"; + cpu_oe_n <= '1'; + cpu_wr_n <= "11"; + elsif (cpu_clk = '1' and cpu_clk'event) then + cpu_a_smp <= cpu_a_p_del; + cpu_oe_n <= cpu_oe_n_p_del; + cpu_wr_n <= cpu_wr_n_p_del; + end if; + end process; + + arm7_din_int <= cpu_d_smp; + arm7_a_int <= cpu_a_smp; + arm7_we_int <= not(cpu_wr_n); + + process(cpu_clk, areset) + begin + if areset = '1' then + cpu_state <= cpu_idle; + cyc_int <= '0'; + we_int <= '0'; + adr_reg <= "00"; + cpu_d_p <= (others => 'Z'); + elsif (cpu_clk'event and cpu_clk = '1') then + + cyc_int <= '0'; + we_int <= '0'; + cpu_d_p <= (others => 'Z') after Clock_2_Out; + + + case cpu_state is + + when cpu_idle => + if cpu_oe_n = '1' then + we_int <= '1'; + end if; + if cpu_cs_n(1) = '0' then + cyc_int <= '1'; + adr_reg <= "10"; + cpu_state <= cpu_cs; + end if; + if cpu_cs_n(2) = '0' then + cyc_int <= '1'; + adr_reg <= "00"; + cpu_state <= cpu_cs; + end if; + if cpu_cs_n(3) = '0' then + cyc_int <= '1'; + adr_reg <= "01"; + cpu_state <= cpu_cs; + end if; + + when cpu_cs => + if cpu_oe_n = '0' then + cpu_d_p <= arm7_dout_int after Clock_2_Out; + if wb_i.ack = '1' then + cpu_state <= cpu_end; + else + cyc_int <= '1'; + end if; + else + if wb_i.ack = '0' then + cyc_int <= '1'; + we_int <= '1'; + else + cpu_state <= cpu_end; + end if; + end if; + + when others => + cpu_state <= cpu_idle; + + end case; + end if; + end process; + + process(cpu_clk_2x, areset) + begin + if areset = '1' then + cpu_wait_n_p <= '1'; + elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then + cpu_wait_n_p <= '1' after Clock_2_Out; + if (cpu_state = cpu_cs and wb_i.ack = '0') then + cpu_wait_n_p <= '0' after Clock_2_Out; + end if; + end if; + end process; + +end behave; diff --git a/misc/ddrsdram/simscripts/ddr_tb.do b/misc/ddrsdram/simscripts/ddr_tb.do new file mode 100644 index 0000000..1f643f1 --- /dev/null +++ b/misc/ddrsdram/simscripts/ddr_tb.do @@ -0,0 +1,16 @@ +vlib work +vcom -93 -explicit ../src/ddr_pkg.vhd +vcom -93 -explicit ../src/ddr_top.vhd +vcom -93 -explicit ../src/mt46v16m16.vhd +vcom -93 -explicit ../simsrc/ddr_tb.vhd +vsim -t 1ps ddr_tb +view wave +view signals +radix hex +add wave * +add wave sim:/ddr_tb/ddr_ctrl/* +force -freeze sim:/ddr_tb/areset 1 0 +run 10 ns +force -freeze sim:/ddr_tb/areset 0 0 +when sim:/ddr_tb/break_out stop +run 10 ms \ No newline at end of file diff --git a/misc/ddrsdram/simscripts/ddr_top.do b/misc/ddrsdram/simscripts/ddr_top.do new file mode 100644 index 0000000..141e164 --- /dev/null +++ b/misc/ddrsdram/simscripts/ddr_top.do @@ -0,0 +1,104 @@ +vlib work +vcom -93 -explicit ../src/ddr_pkg.vhd +vcom -93 -explicit ../src/ddr_top.vhd +vsim -t 1ps ddr_top +view wave +view signals +radix hex +# Add wave signals + +add wave -divider "System" +add wave sim:/ddr_top/areset +add wave sim:/ddr_top/cpu_clk +add wave sim:/ddr_top/cpu_clk_2x +add wave sim:/ddr_top/cpu_clk_4x +add wave sim:/ddr_top/ddr_in_clk +add wave sim:/ddr_top/ddr_in_clk_2x + +add wave -divider "Ctrl interface" +add wave sim:/ddr_top/cpu_clk +add wave sim:/ddr_top/ddr_data_read +add wave sim:/ddr_top/ddr_data_write +add wave sim:/ddr_top/ddr_req +add wave sim:/ddr_top/ddr_rd_wr_n +add wave sim:/ddr_top/ddr_req_len +add wave sim:/ddr_top/ddr_read_en +add wave sim:/ddr_top/ddr_write_en +add wave sim:/ddr_top/ddr_command +add wave sim:/ddr_top/ddr_command_we + +add wave -divider "DDR interface" +add wave sim:/ddr_top/sdr_clk_p +add wave sim:/ddr_top/sdr_clk_n_p +add wave sim:/ddr_top/cke_q_p +add wave sim:/ddr_top/cs_qn_p +add wave sim:/ddr_top/ras_qn_p +add wave sim:/ddr_top/cas_qn_p +add wave sim:/ddr_top/we_qn_p +add wave sim:/ddr_top/dm_q_p +add wave sim:/ddr_top/dqs_q_p +add wave sim:/ddr_top/ba_q_p +add wave sim:/ddr_top/sdr_a_p +add wave sim:/ddr_top/sdr_d_p + +add wave -divider "Internal signals" +add wave sim:/ddr_top/clk2_phase +add wave sim:/ddr_top/clk4_phase +add wave sim:/ddr_top/ddr_state +add wave sim:/ddr_top/sdr_oe_n +add wave sim:/ddr_top/sdr_smp +add wave sim:/ddr_top/sdr_d + + +# Add input signals +force -freeze sim:/ddr_top/cpu_clk_4x 1 0, 0 {1.875 ns} -r 3.75 ns +run 100 ps +force -freeze sim:/ddr_top/cpu_clk_2x 1 0, 0 {3.75 ns} -r 7.5 ns +run 100 ps +force -freeze sim:/ddr_top/cpu_clk 1 0, 0 {7.5 ns} -r 15 ns +force -freeze sim:/ddr_top/ddr_in_clk 1 2ns, 0 {5.75 ns} -r 7.5 ns +force -freeze sim:/ddr_top/ddr_in_clk_2x 0 0.125ns, 1 {2 ns} -r 3.75 ns + +force -freeze sim:/ddr_top/areset 1 0 +force -freeze sim:/ddr_top/ddr_command 0000 0 +force -freeze sim:/ddr_top/ddr_command_we 0 0 +force -freeze sim:/ddr_top/ddr_data_write 1234abcd 0 +force -freeze sim:/ddr_top/ddr_req 0 0 +force -freeze sim:/ddr_top/ddr_req_adr 000000 0 +force -freeze sim:/ddr_top/ddr_rd_wr_n 0 0 +force -freeze sim:/ddr_top/ddr_req_len 0 0 + +# Start simulation +run 45 ns +force -freeze sim:/ddr_top/areset 0 0 +run 92 ns +# DDR Command +force -freeze sim:/ddr_top/ddr_command 000A 0 +force -freeze sim:/ddr_top/ddr_command_we 1 0 +run 15 ns +force -freeze sim:/ddr_top/ddr_command 0000 0 +force -freeze sim:/ddr_top/ddr_command_we 0 0 +run 90 ns +# DDR Read +force -freeze sim:/ddr_top/ddr_req 1 0 +force -freeze sim:/ddr_top/ddr_req_adr 00ABCD 0 +force -freeze sim:/ddr_top/ddr_rd_wr_n 1 0 +force -freeze sim:/ddr_top/ddr_req_len 0 0 +run 15 ns +force -freeze sim:/ddr_top/ddr_req 0 0 +force -freeze sim:/ddr_top/ddr_req_adr 000000 0 +force -freeze sim:/ddr_top/ddr_rd_wr_n 0 0 +force -freeze sim:/ddr_top/ddr_req_len 0 0 +run 150 ns +# DDR Write +force -freeze sim:/ddr_top/ddr_req 1 0 +force -freeze sim:/ddr_top/ddr_req_adr 00ABCD 0 +force -freeze sim:/ddr_top/ddr_rd_wr_n 0 0 +force -freeze sim:/ddr_top/ddr_req_len 0 0 +run 15 ns +force -freeze sim:/ddr_top/ddr_req 0 0 +force -freeze sim:/ddr_top/ddr_req_adr 000000 0 +force -freeze sim:/ddr_top/ddr_rd_wr_n 0 0 +force -freeze sim:/ddr_top/ddr_req_len 0 0 +run 180 ns + diff --git a/misc/ddrsdram/simsrc/ddr_tb.vhd b/misc/ddrsdram/simsrc/ddr_tb.vhd new file mode 100644 index 0000000..249dffb --- /dev/null +++ b/misc/ddrsdram/simsrc/ddr_tb.vhd @@ -0,0 +1,301 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library work; +use work.ddr.all; + +entity ddr_tb is + port ( areset : in std_logic; + break_out : out std_logic); +end ddr_tb; + +architecture behave of ddr_tb is + +signal cpu_clk : std_logic; +signal cpu_clk_2x : std_logic; +signal cpu_clk_4x : std_logic; +signal ddr_in_clk : std_logic; +signal ddr_in_clk_2x : std_logic; + +signal ddr_command : std_logic_vector(15 downto 0); +signal ddr_command_we : std_logic; + +signal ddr_data_read : std_logic_vector(31 downto 0); -- Data read from DDR SDRAM +signal ddr_data_write : std_logic_vector(35 downto 0); -- Data to be written to DDR SDRAM +signal ddr_req_adr : std_logic_vector(23 downto 1); -- Request address +signal ddr_req : std_logic; -- Request DDR SDRAM access +signal ddr_req_ack : std_logic; -- Request acknowledge +signal ddr_busy : std_logic; -- Request acknowledge +signal ddr_rd_wr_n : std_logic; -- Access type 1=READ, 0=WRITE +signal ddr_req_len : std_logic; -- Number of 16-bits words to transfer +signal ddr_read_en : std_logic; -- Enable signal for read data +signal ddr_write_en : std_logic; -- Enable (read) signal for data write +signal refresh_en : std_logic; + +signal sdr_clk_p : std_logic; -- ddr_sdram_clock +signal sdr_clk_n_p : std_logic; -- /ddr_sdram_clock +signal cke_q_p : std_logic; -- clock enable +signal cs_qn_p : std_logic; -- /chip select +signal ras_qn_p : std_logic; -- /ras +signal cas_qn_p : std_logic; -- /cas +signal we_qn_p : std_logic; -- /write enable +signal dm_q_p : std_logic_vector(1 downto 0); -- data mask bits, set to "00" +signal dqs_q_p : std_logic_vector(1 downto 0); -- data strobe, only for write +signal ba_q_p : std_logic_vector(1 downto 0); -- bank select +signal sdr_a_p : std_logic_vector(12 downto 0); -- address bus +signal sdr_d_p : std_logic_vector(15 downto 0); -- bidir data bus + +constant min_time : time := 1.875 ns; + +begin + + clock1: + process + begin + loop + cpu_clk_4x <= '1'; + wait for min_time; + cpu_clk_4x <= '0'; + wait for min_time; + end loop; + end process; + + clock2: + process + begin + loop + cpu_clk_2x <= '1' after 100 ps; + wait until rising_edge(cpu_clk_4x); + cpu_clk_2x <= '0' after 100 ps; + wait until rising_edge(cpu_clk_4x); + end loop; + end process; + + clock3: + process + begin + loop + cpu_clk <= '1' after 100 ps; + wait until rising_edge(cpu_clk_2x); + cpu_clk <= '0' after 100 ps; + wait until rising_edge(cpu_clk_2x); + end loop; + end process; + + ddr_in_clk_2x <= cpu_clk_4x after 1 ns; + + clock4: + process + begin + loop + ddr_in_clk <= '0' after 100 ps; + wait until rising_edge(ddr_in_clk_2x); + ddr_in_clk <= '1' after 100 ps; + wait until rising_edge(ddr_in_clk_2x); + end loop; + end process; + + inputdata: + process + begin + -- Wait until global reset released + loop + ddr_command <= x"0000"; + ddr_command_we <= '0'; + ddr_data_write <= x"000000000"; + ddr_req <= '0'; + ddr_req_adr <= "00000000000000000000000"; + ddr_rd_wr_n <= '0'; + ddr_req_len <= '0'; + break_out <= '0'; + refresh_en <= '0'; + + wait until falling_edge(areset); + + -- DDR initialization sequence + -- Wait more than 200 us + wait for 201000 ns; + + -- Send precharge command + wait until rising_edge(cpu_clk); + ddr_command <= x"8000"; + ddr_command_we <= '1'; + wait until rising_edge(cpu_clk); + ddr_command <= x"0000"; + ddr_command_we <= '0'; + + -- Wait for 1 us + wait for 1000 ns; + + -- Load extended mode register + -- Enable DLL + -- Normal drive strength + wait until rising_edge(cpu_clk); + ddr_command <= x"2000"; + ddr_command_we <= '1'; + wait until rising_edge(cpu_clk); + ddr_command <= x"0000"; + ddr_command_we <= '0'; + + -- Wait for 1 us + wait for 1000 ns; + + -- Load mode register + -- Burst length: 2 + -- Burst type: Sequential + -- Cas latency: 2 + -- Reset DLL + wait until rising_edge(cpu_clk); + ddr_command <= x"0121"; + ddr_command_we <= '1'; + wait until rising_edge(cpu_clk); + ddr_command <= x"0000"; + ddr_command_we <= '0'; + + -- Wait for 1 us + wait for 1000 ns; + + -- Send precharge command + wait until rising_edge(cpu_clk); + ddr_command <= x"8000"; + ddr_command_we <= '1'; + wait until rising_edge(cpu_clk); + ddr_command <= x"0000"; + ddr_command_we <= '0'; + + -- Enable refresh + refresh_en <= '1'; + + -- Wait 30 us (minimum 2 autorefresh cycles) + wait for 30000 ns; + + -- Load mode register + -- Burst length: 2 + -- Burst type: Sequential + -- Cas latency: 2 + -- Deactivate Reset DLL + wait until rising_edge(cpu_clk); + ddr_command <= x"0021"; + ddr_command_we <= '1'; + wait until rising_edge(cpu_clk); + ddr_command <= x"0000"; + ddr_command_we <= '0'; + + -- Wait for 2 us (DLL stable) + wait for 2000 ns; + + -- Write data to DDR + wait until rising_edge(cpu_clk_2x); + ddr_data_write <= x"312345678"; + ddr_req <= '1'; + ddr_req_adr <= "00000000000000000000000"; + ddr_rd_wr_n <= '0'; + ddr_req_len <= '0'; + wait until rising_edge(ddr_write_en); + wait until rising_edge(cpu_clk_2x); + ddr_req <= '0'; + ddr_req_adr <= "00000000000000000000000"; + ddr_rd_wr_n <= '0'; + ddr_req_len <= '0'; + ddr_data_write <= x"000000000"; + wait for 100 ns; + + -- Read data from DDR + wait until rising_edge(cpu_clk_2x); + ddr_req <= '1'; + ddr_req_adr <= "00000000000000000000000"; + ddr_rd_wr_n <= '1'; + ddr_req_len <= '0'; + wait until rising_edge(ddr_req_ack); + wait until rising_edge(cpu_clk_2x); + ddr_req <= '0'; + ddr_req_adr <= "00000000000000000000000"; + ddr_rd_wr_n <= '0'; + ddr_req_len <= '0'; + ddr_data_write <= x"000000000"; + + + + wait for 100 ns; + break_out <= '1'; + wait for 100 ns; + + end loop; + + end process; + + ddr_ctrl: + ddr_top port map( + areset => areset, + cpu_clk => cpu_clk, + cpu_clk_2x => cpu_clk_2x, + cpu_clk_4x => cpu_clk_4x, + ddr_in_clk => ddr_in_clk, + ddr_in_clk_2x => ddr_in_clk_2x, + + -- Command interface + ddr_command => ddr_command, + ddr_command_we => ddr_command_we, + refresh_en => refresh_en, + + -- Data interface signals + ddr_data_read => ddr_data_read, + ddr_data_write => ddr_data_write, + ddr_req_adr => ddr_req_adr, + ddr_req => ddr_req, + ddr_req_ack => ddr_req_ack, + ddr_busy => ddr_busy, + ddr_rd_wr_n => ddr_rd_wr_n, + ddr_req_len => ddr_req_len, + ddr_read_en => ddr_read_en, + ddr_write_en => ddr_write_en, + -- DDR SDRAM Signals + sdr_clk_p => sdr_clk_p, + sdr_clk_n_p => sdr_clk_n_p, + cke_q_p => cke_q_p, + cs_qn_p => cs_qn_p, + ras_qn_p => ras_qn_p, + cas_qn_p => cas_qn_p, + we_qn_p => we_qn_p, + dm_q_p => dm_q_p, + dqs_q_p => dqs_q_p, + ba_q_p => ba_q_p, + sdr_a_p => sdr_a_p, + sdr_d_p => sdr_d_p); + + myram: + MT46V16M16 generic map( + tCK => 7.500 ns, + tCH => 3.375 ns, -- 0.45*tCK + tCL => 3.375 ns, -- 0.45*tCK + tDH => 0.500 ns, + tDS => 0.500 ns, + tIH => 0.900 ns, + tIS => 0.900 ns, + tMRD => 15.000 ns, + tRAS => 40.000 ns, + tRAP => 20.000 ns, + tRC => 65.000 ns, + tRFC => 75.000 ns, + tRCD => 20.000 ns, + tRP => 20.000 ns, + tRRD => 15.000 ns, + tWR => 15.000 ns, + addr_bits => 13, + data_bits => 16, + cols_bits => 9) + port map( + Dq => sdr_d_p, + Dqs => dqs_q_p, + Addr => sdr_a_p, + Ba => ba_q_p, + Clk => sdr_clk_p, + Clk_n => sdr_clk_n_p, + Cke => cke_q_p, + Cs_n => cs_qn_p, + Ras_n => ras_qn_p, + Cas_n => cas_qn_p, + We_n => we_qn_p, + Dm => dm_q_p); + +end behave; diff --git a/misc/ddrsdram/src/ddr_pkg.vhd b/misc/ddrsdram/src/ddr_pkg.vhd new file mode 100644 index 0000000..0e41a88 --- /dev/null +++ b/misc/ddrsdram/src/ddr_pkg.vhd @@ -0,0 +1,107 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +package ddr is + + function mirror_bus32 ( org_sig : std_logic_vector) return std_logic_vector; + function mirror_bus4 ( org_sig : std_logic_vector) return std_logic_vector; + + component ddr_top + generic( + simulate_io_time : boolean := false); + port ( -- Asyncronous reset and clocks + areset : in std_logic; + cpu_clk : in std_logic; + cpu_clk_2x : in std_logic; + cpu_clk_4x : in std_logic; + ddr_in_clk : in std_logic; + ddr_in_clk_2x : in std_logic; + + -- Command interface + ddr_command : in std_logic_vector(15 downto 0); + ddr_command_we : in std_logic; + refresh_en : in std_logic; + + + -- Data interface signals + ddr_data_read : out std_logic_vector(31 downto 0); -- Data read from DDR SDRAM + ddr_data_write : in std_logic_vector(35 downto 0); -- Data to be written to DDR SDRAM + ddr_req_adr : in std_logic_vector(25 downto 1); -- Request address + ddr_req : in std_logic; -- Request DDR SDRAM access + ddr_busy : out std_logic; -- Request acknowledge + ddr_rd_wr_n : in std_logic; -- Access type 1=READ, 0=WRITE + ddr_req_len : in std_logic; -- Number of 16-bits words to transfer (0=2, 1=8) + ddr_read_en : out std_logic; -- Enable signal for read data + ddr_write_en : out std_logic; -- Enable (read) signal for data write + + -- DDR SDRAM Signals + sdr_clk_p : out std_logic; -- ddr_sdram_clock + sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock + cke_q_p : out std_logic; -- clock enable + cs_qn_p : out std_logic; -- /chip select + ras_qn_p : inout std_logic; -- /ras + cas_qn_p : inout std_logic; -- /cas + we_qn_p : inout std_logic; -- /write enable + dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00" + dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write + ba_q_p : out std_logic_vector(1 downto 0); -- bank select + sdr_a_p : out std_logic_vector(12 downto 0); -- address bus + sdr_d_p : inout std_logic_vector(15 downto 0)); -- bidir data bus + end component; + + component MT46V16M16 + GENERIC ( -- Timing for -75Z CL2 + tCK : TIME := 7.500 ns; + tCH : TIME := 3.375 ns; -- 0.45*tCK + tCL : TIME := 3.375 ns; -- 0.45*tCK + tDH : TIME := 0.500 ns; + tDS : TIME := 0.500 ns; + tIH : TIME := 0.900 ns; + tIS : TIME := 0.900 ns; + tMRD : TIME := 15.000 ns; + tRAS : TIME := 40.000 ns; + tRAP : TIME := 20.000 ns; + tRC : TIME := 65.000 ns; + tRFC : TIME := 75.000 ns; + tRCD : TIME := 20.000 ns; + tRP : TIME := 20.000 ns; + tRRD : TIME := 15.000 ns; + tWR : TIME := 15.000 ns; + addr_bits : INTEGER := 13; + data_bits : INTEGER := 16; + cols_bits : INTEGER := 9 + ); + PORT ( + Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); + Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ"; + Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + Clk : IN STD_LOGIC; + Clk_n : IN STD_LOGIC; + Cke : IN STD_LOGIC; + Cs_n : IN STD_LOGIC; + Ras_n : IN STD_LOGIC; + Cas_n : IN STD_LOGIC; + We_n : IN STD_LOGIC; + Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) + ); + end component; + +end; + +package body ddr is + + function mirror_bus32 ( org_sig : std_logic_vector) return std_logic_vector is + begin + return (org_sig(7 downto 0) & org_sig(15 downto 8) & org_sig(23 downto 16) & org_sig(31 downto 24)); + end function mirror_bus32; + + function mirror_bus4 ( org_sig : std_logic_vector) return std_logic_vector is + begin + return (org_sig(0) & org_sig(1) & org_sig(2) & org_sig(3)); + end function mirror_bus4; + +end package body; + + \ No newline at end of file diff --git a/misc/ddrsdram/src/ddr_top.vhd b/misc/ddrsdram/src/ddr_top.vhd new file mode 100644 index 0000000..033e9f8 --- /dev/null +++ b/misc/ddrsdram/src/ddr_top.vhd @@ -0,0 +1,743 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library UNISIM; +use UNISIM.vcomponents.all; + +entity ddr_top is + generic( + simulate_io_time : boolean := false); + port ( -- Asyncronous reset and clocks + areset : in std_logic; + cpu_clk : in std_logic; + cpu_clk_2x : in std_logic; + cpu_clk_4x : in std_logic; + ddr_in_clk : in std_logic; + ddr_in_clk_2x : in std_logic; + + -- Command interface + ddr_command : in std_logic_vector(15 downto 0); + ddr_command_we : in std_logic; + refresh_en : in std_logic; + + -- Data interface signals + ddr_data_read : out std_logic_vector(31 downto 0); -- Data read from DDR SDRAM + ddr_data_write : in std_logic_vector(35 downto 0); -- Data to be written to DDR SDRAM + ddr_req_adr : in std_logic_vector(25 downto 1); -- Request address + ddr_req : in std_logic; -- Request DDR SDRAM access + ddr_busy : out std_logic; -- Request acknowledge + ddr_rd_wr_n : in std_logic; -- Access type 1=READ, 0=WRITE + ddr_req_len : in std_logic; -- Number of 16-bits words to transfer (0=2, 1=8) + ddr_read_en : out std_logic; -- Enable signal for read data + ddr_write_en : out std_logic; -- Enable (read) signal for data write + + -- DDR SDRAM Signals + sdr_clk_p : out std_logic; -- ddr_sdram_clock + sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock + cke_q_p : out std_logic; -- clock enable + cs_qn_p : out std_logic; -- /chip select + ras_qn_p : inout std_logic; -- /ras + cas_qn_p : inout std_logic; -- /cas + we_qn_p : inout std_logic; -- /write enable + dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00" + dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write + ba_q_p : out std_logic_vector(1 downto 0); -- bank select + sdr_a_p : out std_logic_vector(12 downto 0); -- address bus + sdr_d_p : inout std_logic_vector(15 downto 0)); -- bidir data bus +end ddr_top; + +architecture behave of ddr_top is + +attribute keep : string; + +type clk4_type is array(0 to 15) of std_logic_vector(1 downto 0); + +signal cpu_clk_tog : std_logic; +signal ddr_cmd : std_logic_vector(15 downto 0); +signal ddr_cmd_we_smp : std_logic; +signal new_command : std_logic; + +signal cpu_clk_2x_smp1 : std_logic; +signal cpu_clk_2x_smp2 : std_logic; +signal cpu_clk_4x_smp1 : std_logic; +signal cpu_clk_4x_smp2 : std_logic; + +signal clk2_phase : std_logic; +signal clk4_phase : std_logic_vector(3 downto 0); +signal clk4_phase_short : clk4_type; +attribute keep of clk4_phase_short:signal is "true"; + +signal ddr_clk_tog : std_logic; +signal ddr_clk_smp1 : std_logic; +signal ddr_clk_smp2 : std_logic; +signal ddr_clk_phase : std_logic; + +signal smp_req_adr : std_logic_vector(25 downto 1); +signal smp_req_type : std_logic; +signal smp_req_len : std_logic; +signal ddr_write_en_int : std_logic; +signal ddr_read_en_int : std_logic; + +signal dqs_q : std_logic_vector(1 downto 0); +signal dqs_oe_n : std_logic_vector(1 downto 0); +attribute keep of dqs_oe_n:signal is "true"; +signal cas_qn : std_logic; +signal ras_qn : std_logic; +signal we_qn : std_logic; +signal ba_q : std_logic_vector(1 downto 0); +signal sdr_clk : std_logic; +signal sdr_clk_n : std_logic; +signal sdr_a : std_logic_vector(12 downto 0); +signal sdr_d : std_logic_vector(15 downto 0); +signal sdr_smp : std_logic_vector(35 downto 0); +signal sdr_oe_n : std_logic_vector(15 downto 0); +attribute keep of sdr_oe_n:signal is "true"; +signal sdr_oe_ctrl : std_logic_vector(15 downto 0); +attribute keep of sdr_oe_ctrl:signal is "true"; +signal sdr_wr_msw : std_logic_vector(17 downto 0); +attribute keep of sdr_wr_msw:signal is "true"; +signal dm_q : std_logic_vector(1 downto 0); + +signal nowin_idle_dqs : std_logic_vector(1 downto 0); +signal nowin_wr_nop1_d : std_logic_vector(15 downto 0); +signal nowin_wr_nop1_dqs : std_logic_vector(1 downto 0); +signal nowin_wr_nop1_dm : std_logic_vector(1 downto 0); +signal nowin_wr_nop2_dqs : std_logic_vector(1 downto 0); +signal nowin_wr_nop3_d : std_logic_vector(15 downto 0); +signal nowin_wr_nop3_dqs : std_logic_vector(1 downto 0); +attribute keep of nowin_idle_dqs:signal is "true"; +attribute keep of nowin_wr_nop1_d:signal is "true"; +attribute keep of nowin_wr_nop1_dqs:signal is "true"; +attribute keep of nowin_wr_nop1_dm:signal is "true"; +attribute keep of nowin_wr_nop2_dqs:signal is "true"; +attribute keep of nowin_wr_nop3_d:signal is "true"; +attribute keep of nowin_wr_nop3_dqs:signal is "true"; + +signal cas_n_smp : std_logic; +signal ras_n_smp : std_logic; +signal we_n_smp : std_logic; +signal read_start_sig : std_logic; +signal sdr_d_in : std_logic_vector(15 downto 0); +signal read_time_cnt : std_logic_vector(1 downto 0); +signal read_input_en : std_logic; +signal read_input_en_del : std_logic; +signal ddr_data_read_int : std_logic_vector(31 downto 0); + +signal refresh_pend : std_logic; +signal refresh_end : std_logic; +signal refresh_cnt : std_logic_vector(9 downto 0); +signal refresh_wait_cnt : std_logic_vector(3 downto 0); +signal refresh_wait_end : std_logic; + +signal cas_qn_p_del : std_logic; +signal ras_qn_p_del : std_logic; +signal we_qn_p_del : std_logic; +signal sdr_d_p_del : std_logic_vector(15 downto 0); + +signal saved_row : std_logic_vector(26 downto 11); +signal operation : std_logic_vector(1 downto 0); + +signal ddr_req_adr_int : std_logic_vector(25 downto 1); + +type state_type is (idle, act, act_nop1, act_nop2, rd_wr, rd_nop1, + rd_nop2,rd_nop3,rd_nop4, rd_nop5,pre, pre_nop1, pre_nop2, wr_nop1, wr_nop2, + wr_nop3, cmd, cpu_pre, refresh, refresh_wait); +signal ddr_state : state_type; + +constant Clk_to_Output : time := 2.2 ns; +constant Input_Setup : time := 2.5 ns; + +constant Refresh_Interval : std_logic_vector(9 downto 0) := "1111100110"; + +begin + + iotimingon: + if simulate_io_time generate + begin + cas_qn_p_del <= 'X' after 0 ns, cas_qn_p after Input_Setup; + ras_qn_p_del <= 'X' after 0 ns, ras_qn_p after Input_Setup; + we_qn_p_del <= 'X' after 0 ns, we_qn_p after Input_Setup; + sdr_d_p_del <= "XXXXXXXXXXXXXXXX" after 0 ns, sdr_d_p after Input_Setup; + end generate; + + iotimingoff: + if not simulate_io_time generate + begin + cas_qn_p_del <= cas_qn_p; + ras_qn_p_del <= ras_qn_p; + we_qn_p_del <= we_qn_p; + sdr_d_p_del <= sdr_d_p; + end generate; + + ddr_write_en <= ddr_write_en_int; + ddr_read_en <= ddr_read_en_int; + ddr_data_read <= ddr_data_read_int; + + ddr_req_adr_int <= (ddr_req_adr(24 downto 10) & '0' & ddr_req_adr(9 downto 1)) when (simulate_io_time) else ddr_req_adr; + + process(cpu_clk, areset) -- Toggle a flip-flop with cpu_clk, in order + begin -- to find phase relation with 2x and 4x clocks + if areset = '1' then + cpu_clk_tog <= '0'; + elsif (cpu_clk'event and cpu_clk = '1') then + cpu_clk_tog <= not(cpu_clk_tog); + end if; + end process; + + process(cpu_clk_2x, areset) -- Find phase relation between cpu_clk and cpu_clk_2x + begin + if areset = '1' then + cpu_clk_2x_smp1 <= '0'; + cpu_clk_2x_smp2 <= '0'; + clk2_phase <= '0'; + elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then + cpu_clk_2x_smp1 <= cpu_clk_tog; + cpu_clk_2x_smp2 <= cpu_clk_2x_smp1; + if (cpu_clk_2x_smp1 = '1' and cpu_clk_2x_smp2 = '0') then + clk2_phase <= '0'; + else + clk2_phase <= not(clk2_phase); + end if; + end if; + end process; + + process(cpu_clk_4x, areset) -- Find phase relation between cpu_clk and cpu_clk_4x + begin + if areset = '1' then + cpu_clk_4x_smp1 <= '0'; + cpu_clk_4x_smp2 <= '0'; + clk4_phase <= "0000"; + clk4_phase_short(0) <= "00"; + clk4_phase_short(1) <= "00"; + clk4_phase_short(2) <= "00"; + clk4_phase_short(3) <= "00"; + clk4_phase_short(4) <= "00"; + clk4_phase_short(5) <= "00"; + clk4_phase_short(6) <= "00"; + clk4_phase_short(7) <= "00"; + clk4_phase_short(8) <= "00"; + clk4_phase_short(9) <= "00"; + clk4_phase_short(10) <= "00"; + clk4_phase_short(11) <= "00"; + clk4_phase_short(12) <= "00"; + clk4_phase_short(13) <= "00"; + clk4_phase_short(14) <= "00"; + clk4_phase_short(15) <= "00"; + elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then + cpu_clk_4x_smp1 <= cpu_clk_tog; + cpu_clk_4x_smp2 <= cpu_clk_4x_smp1; + for i in 0 to 15 loop + if (cpu_clk_4x_smp1 = '1' and cpu_clk_4x_smp2 = '0') then + clk4_phase <= "0100"; + clk4_phase_short(i) <= "01"; + else + clk4_phase <= (clk4_phase(2 downto 0) & clk4_phase(3)); + clk4_phase_short(i) <= clk4_phase_short(i)(0) & clk4_phase_short(i)(1); + end if; + end loop; + end if; + end process; + + process(cpu_clk_4x, areset) -- + begin + if areset = '1' then + sdr_clk <= '0'; + sdr_clk_n <= '0'; + elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then + if clk4_phase_short(0)(0) = '1' then + sdr_clk <= '1'; + else + sdr_clk <= '0'; + end if; + if clk4_phase_short(0)(1) = '1' then + sdr_clk_n <= '1'; + else + sdr_clk_n <= '0'; + end if; + end if; + end process; + + cke_q_p <= '1' after Clk_to_Output; + cs_qn_p <= '0' after Clk_to_Output; + + process(cpu_clk_4x, areset) -- + begin + if areset = '1' then + ras_qn_p <= '1'; + cas_qn_p <= '1'; + we_qn_p <= '1'; + dqs_q_p <= "ZZ"; + sdr_a_p <= "0000000000000"; + ba_q_p <= "00"; + sdr_clk_p <= '0'; + sdr_clk_n_p <= '1'; + elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then + ras_qn_p <= transport ras_qn after Clk_to_Output; + cas_qn_p <= transport cas_qn after Clk_to_Output; + we_qn_p <= transport we_qn after Clk_to_Output; + if dqs_oe_n(0) = '0' then + dqs_q_p(0) <= transport dqs_q(0) after Clk_to_Output; + else + dqs_q_p(0) <= transport 'Z' after Clk_to_Output; + end if; + if dqs_oe_n(1) = '0' then + dqs_q_p(1) <= transport dqs_q(1) after Clk_to_Output; + else + dqs_q_p(1) <= transport 'Z' after Clk_to_Output; + end if; + sdr_a_p <= transport sdr_a after Clk_to_Output; + ba_q_p <= transport ba_q after Clk_to_Output; + sdr_clk_p <= transport sdr_clk after Clk_to_Output; + sdr_clk_n_p <= transport sdr_clk_n after Clk_to_Output; + end if; + end process; + + process(cpu_clk_2x, areset) -- + begin + if areset = '1' then + ddr_state <= idle; + ras_qn <= '1'; + cas_qn <= '1'; + we_qn <= '1'; + smp_req_adr <= (others => '0'); + smp_req_type <= '0'; + smp_req_len <= '0'; + sdr_a <= "XXXXXXXXXXXXX"; + ba_q <= "00"; + ddr_busy <= '1'; + saved_row <= "1000000000000000"; + ddr_write_en_int <= '0'; + ddr_read_en_int <= '0'; + nowin_idle_dqs <= "11"; + nowin_wr_nop1_d <= "0000000000000000"; + nowin_wr_nop1_dqs <= "00"; + nowin_wr_nop1_dm <= "00"; + nowin_wr_nop2_dqs <= "00"; + nowin_wr_nop3_d <= "0000000000000000"; + nowin_wr_nop3_dqs <= "00"; + elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then + + -- Default values + ras_qn <= '1'; + cas_qn <= '1'; + we_qn <= '1'; + sdr_a <= "XXXXXXXXXXXXX"; + ddr_busy <= '1'; + ddr_write_en_int <= '0'; + ddr_read_en_int <= '0'; + + nowin_idle_dqs <= "00"; + nowin_wr_nop1_d <= "0000000000000000"; + nowin_wr_nop1_dqs <= "00"; + nowin_wr_nop1_dm <= "00"; + nowin_wr_nop2_dqs <= "00"; + nowin_wr_nop3_d <= "0000000000000000"; + nowin_wr_nop3_dqs <= "00"; + + case ddr_state is + when idle => + smp_req_adr <= ddr_req_adr_int; + smp_req_type <= ddr_rd_wr_n; + smp_req_len <= ddr_req_len; + ddr_busy <= '0'; + operation <= "00"; + if refresh_pend = '1' then + operation <= "01"; + ddr_state <= pre; + elsif new_command = '1' then + if ddr_cmd(15) = '1' then + operation <= "10"; + ddr_state <= cpu_pre; + else + ddr_state <= cmd; + end if; + elsif (ddr_req = '1' and ddr_req_adr_int(25 downto 11) = saved_row(25 downto 11) and saved_row(26) = '0') then + operation <= "11"; + ddr_write_en_int <= not(ddr_rd_wr_n); + ddr_state <= rd_wr; + elsif ddr_req = '1' then + operation <= "11"; + ddr_state <= pre; + else + ddr_state <= idle; + nowin_idle_dqs <= "11"; + end if; + when act => + sdr_a <= smp_req_adr(23 downto 11); + ba_q <= smp_req_adr(25 downto 24); + ras_qn <= '0'; + ddr_write_en_int <= not(smp_req_type); + ddr_state <= act_nop1; + when act_nop1 => + ddr_state <= act_nop2; + when act_nop2 => + ddr_state <= rd_wr; + when rd_wr => + sdr_a(10) <= '0'; -- Disable auto precharge + sdr_a(9 downto 0) <= smp_req_adr(10 downto 1); + ba_q <= smp_req_adr(25 downto 24); + saved_row <= '0' & smp_req_adr(25 downto 11); + cas_qn <= '0'; + we_qn <= smp_req_type; + if smp_req_type = '1' then + ddr_state <= rd_nop1; + else + ddr_state <= wr_nop1; + nowin_wr_nop1_d <= "1111111111111111"; + nowin_wr_nop1_dqs <= "11"; + nowin_wr_nop1_dm <= "11"; + end if; + when wr_nop1 => + ddr_state <= wr_nop2; + nowin_wr_nop2_dqs <= "11"; + when wr_nop2 => + ddr_state <= wr_nop3; + nowin_wr_nop3_d <= "1111111111111111"; + nowin_wr_nop3_dqs <= "11"; + when wr_nop3 => + nowin_idle_dqs <= "11"; + ddr_state <= idle; + when rd_nop1 => + ddr_state <= rd_nop2; + when rd_nop2 => + if operation /= "11" then + nowin_idle_dqs <= "11"; + ddr_state <= idle; + else + ddr_state <= rd_nop3; + end if; + when rd_nop3 => + ddr_state <= rd_nop4; + when rd_nop4 => + ddr_read_en_int <= '1'; + ddr_state <= rd_nop5; + when rd_nop5 => + nowin_idle_dqs <= "11"; + ddr_state <= idle; + when pre => + ras_qn <= '0'; + we_qn <= '0'; + sdr_a(10) <= '1'; -- Precharge all banks + ba_q <= smp_req_adr(25 downto 24); + ddr_state <= pre_nop1; + when pre_nop1 => + ddr_state <= pre_nop2; + when cmd => + cas_qn <= '0'; + ras_qn <= '0'; + we_qn <= '0'; + ba_q <= ddr_cmd(14 downto 13); + sdr_a <= ddr_cmd(12 downto 0); + nowin_idle_dqs <= "11"; + ddr_state <= idle; + when cpu_pre => + ddr_state <= pre; + when refresh => + cas_qn <= '0'; + ras_qn <= '0'; + saved_row(26) <= '1'; + ddr_state <= refresh_wait; + when refresh_wait => + if refresh_wait_end = '1' then + ddr_state <= pre_nop2; + end if; + when pre_nop2 => + if operation = "01" then + operation <= "10"; + ddr_state <= refresh; + elsif operation = "10" then + nowin_idle_dqs <= "11"; + ddr_state <= idle; + else + ddr_state <= act; + end if; + when others => + ddr_state <= idle; + nowin_idle_dqs <= "11"; + end case; + end if; + end process; + + process(cpu_clk, areset) -- + begin + if areset = '1' then + ddr_cmd <= "0000000000000000"; + elsif (cpu_clk'event and cpu_clk = '1') then + if ddr_command_we = '1' then + ddr_cmd <= ddr_command; + else + ddr_cmd <= ddr_cmd; + end if; + end if; + end process; + + process(cpu_clk_2x, areset) -- + begin + if areset = '1' then + ddr_cmd_we_smp <= '0'; + new_command <= '0'; + sdr_smp <= "000000000000000000000000000000000000"; + elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then + ddr_cmd_we_smp <= ddr_command_we; + if ddr_command_we = '0' and ddr_cmd_we_smp = '1' then + new_command <= '1'; + elsif ddr_state = cmd or ddr_state = cpu_pre then + new_command <= '0'; + else + new_command <= new_command; + end if; + + if ddr_write_en_int = '1' then + sdr_smp <= ddr_data_write; + else + sdr_smp <= sdr_smp; + end if; + + end if; + end process; + + process(cpu_clk_4x, areset) -- + begin + if areset = '1' then + dqs_q <= "00"; + dqs_oe_n <= "11"; + sdr_oe_ctrl <= "1111111111111111"; + sdr_wr_msw <= "000000000000000000"; + elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then + + for i in 0 to 15 loop + if nowin_wr_nop1_d(i) = '1' and clk4_phase_short(i)(0) = '1' then + sdr_oe_ctrl(i) <= '0'; + elsif nowin_wr_nop3_d(i) = '1' and clk4_phase_short(i)(0) = '1' then + sdr_oe_ctrl(i) <= '1'; + end if; + end loop; + + for i in 0 to 1 loop + if nowin_idle_dqs(i) = '1' or nowin_wr_nop3_dqs(i) = '1' then + dqs_oe_n(i) <= '1'; + elsif nowin_wr_nop1_dqs(i) = '1' then + dqs_oe_n(i) <= '0'; + end if; + end loop; + + for i in 0 to 1 loop + if (nowin_wr_nop2_dqs(i) = '1' and clk4_phase_short(i)(0) = '1') then + dqs_q(i) <= '1'; + else + dqs_q(i) <= '0'; + end if; + end loop; + + for i in 0 to 15 loop + if nowin_wr_nop1_d(i) = '1' and clk4_phase_short(i)(1) = '1' then + sdr_wr_msw(i) <= '1'; + else + sdr_wr_msw(i) <= '0'; + end if; + end loop; + + for i in 0 to 1 loop + if nowin_wr_nop1_dm(i) = '1' and clk4_phase_short(i)(1) = '1' then + sdr_wr_msw(i+16) <= '1'; + else + sdr_wr_msw(i+16) <= '0'; + end if; + end loop; + + end if; + end process; + + -- NOTE! DATA OUTPUT PATH. CLOCKED ON FALLING 4X CLOCK + process(cpu_clk_4x, areset) -- + begin + if areset = '1' then + sdr_d_p <= "ZZZZZZZZZZZZZZZZ"; + dm_q_p <= "11"; + sdr_oe_n <= "1111111111111111"; + sdr_d <= "0000000000000000"; + dm_q <= "11"; + elsif (cpu_clk_4x'event and cpu_clk_4x = '0') then + + for i in 0 to 15 loop + if sdr_oe_n(i) = '0' then + sdr_d_p(i) <= transport sdr_d(i) after Clk_to_Output; + else + sdr_d_p(i) <= transport 'Z' after Clk_to_Output; + end if; + end loop; + + dm_q_p <= transport dm_q after Clk_to_Output; + + for i in 0 to 15 loop + if sdr_oe_ctrl(i) = '0' then + sdr_oe_n(i) <= '0'; + else + sdr_oe_n(i) <= '1'; + end if; + end loop; + + for i in 0 to 15 loop + if sdr_wr_msw(i) = '1' then + sdr_d(i) <= sdr_smp(i); + else + sdr_d(i) <= sdr_smp(i+16); + end if; + end loop; + + for i in 0 to 1 loop + if sdr_wr_msw(i+16) = '1' then + dm_q(i) <= sdr_smp(i+32); + else + dm_q(i) <= sdr_smp(i+34); + end if; + end loop; + + end if; + end process; + + process(cpu_clk_2x, areset) -- + begin + if areset = '1' then + refresh_cnt <= "0000000000"; + refresh_pend <= '0'; + refresh_end <= '0'; + refresh_wait_cnt <= "0000"; + refresh_wait_end <= '0'; + elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then + + if refresh_cnt = Refresh_Interval then + refresh_end <= '1'; + else + refresh_end <= '0'; + end if; + + if refresh_end = '1' then + refresh_cnt <= "0000000000"; + else + refresh_cnt <= refresh_cnt + '1'; + end if; + + if refresh_end = '1' and refresh_en = '1' then + refresh_pend <= '1'; + elsif ddr_state = refresh then + refresh_pend <= '0'; + else + refresh_pend <= refresh_pend; + end if; + + if ddr_state = refresh_wait then + refresh_wait_cnt <= refresh_wait_cnt + '1'; + else + refresh_wait_cnt <= "0000"; + end if; + + if refresh_wait_cnt = "1011" then + refresh_wait_end <= '1'; + else + refresh_wait_end <= '0'; + end if; + + end if; + end process; + + -- 911. THIS IS A DUMMY FOR FGPA IMPEMENTATION TESTING + + process(ddr_in_clk, areset) + begin + if areset = '1' then + ddr_clk_tog <= '0'; + elsif (ddr_in_clk'event and ddr_in_clk = '1') then + ddr_clk_tog <= not(ddr_clk_tog); + end if; + end process; + + process(ddr_in_clk_2x, areset) + begin + if areset = '1' then + ddr_clk_smp1 <= '0'; + ddr_clk_smp2 <= '0'; + ddr_clk_phase <= '0'; + elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then + ddr_clk_smp1 <= ddr_clk_tog; + ddr_clk_smp2 <= ddr_clk_smp1; + if ddr_clk_smp1 = '1' and ddr_clk_smp2 = '0' then + ddr_clk_phase <= '0'; + else + ddr_clk_phase <= not(ddr_clk_phase); + end if; + end if; + end process; + + process(ddr_in_clk_2x, areset) + begin + if areset = '1' then + cas_n_smp <= '0'; + ras_n_smp <= '0'; + we_n_smp <= '0'; + read_start_sig <= '0'; + elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then + cas_n_smp <= cas_qn_p_del; + ras_n_smp <= ras_qn_p_del; + we_n_smp <= we_qn_p_del; + if ras_n_smp = '1' and cas_n_smp = '0' and we_n_smp = '1' and ddr_clk_phase = '1' then + read_start_sig <= '1'; + else + read_start_sig <= '0'; + end if; + end if; + end process; + + process(ddr_in_clk_2x, areset) + begin + if areset = '1' then + sdr_d_in <= "0000000000000000"; + elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then + sdr_d_in <= sdr_d_p_del; + end if; + end process; + + process(ddr_in_clk_2x, areset) + begin + if areset = '1' then + read_time_cnt <= "00"; + read_input_en <= '0'; + elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then + + if read_start_sig = '1' then + read_time_cnt <= "01"; + elsif read_time_cnt = "00" then + read_time_cnt <= read_time_cnt; + else + read_time_cnt <= read_time_cnt + '1'; + end if; + + if read_time_cnt = "11" then + read_input_en <= '1'; + else + read_input_en <= '0'; + end if; + + read_input_en_del <= read_input_en; + + end if; + end process; + + process(ddr_in_clk_2x, areset) + begin + if areset = '1' then + ddr_data_read_int <= "00000000000000000000000000000000"; + elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then + if read_input_en = '1' then + ddr_data_read_int(15 downto 0) <= sdr_d_in; + end if; + if read_input_en_del = '1' then + ddr_data_read_int(31 downto 16) <= sdr_d_in; + end if; + end if; + end process; + +end behave; + + diff --git a/misc/ddrsdram/src/mt46v16m16.vhd b/misc/ddrsdram/src/mt46v16m16.vhd new file mode 100644 index 0000000..6b89345 --- /dev/null +++ b/misc/ddrsdram/src/mt46v16m16.vhd @@ -0,0 +1,1320 @@ +----------------------------------------------------------------------------------------- +-- +-- File Name: MT46V16M16.VHD +-- Version: 2.1 +-- Date: January 14th, 2002 +-- Model: Behavioral +-- Simulator: NCDesktop - http://www.cadence.com +-- ModelSim PE - http://www.model.com +-- +-- Dependencies: None +-- +-- Author: Son P. Huynh +-- Email: sphuynh@micron.com +-- Phone: (208) 368-3825 +-- Company: Micron Technology, Inc. +-- Part Number: MT46V16M16 (4 Mb x 16 x 4 Banks) +-- +-- Description: Micron 256 Mb SDRAM DDR (Double Data Rate) +-- +-- Limitation: Doesn't model internal refresh counter +-- +-- Note: +-- +-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY +-- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR +-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. +-- +-- Copyright (c) 1998 Micron Semiconductor Products, Inc. +-- All rights researved +-- +-- Rev Author Date Changes +-- --- ---------------------------- ---------- ------------------------------------- +-- 2.1 Son P. Huynh 01/14/2002 - Fix Burst_counter +-- Micron Technology, Inc. +-- +-- 2.0 Son P. Huynh 11/08/2001 - Second release +-- Micron Technology, Inc. - Rewrote and remove SHARED VARIABLE +-- +----------------------------------------------------------------------------------------- + +LIBRARY IEEE; + USE IEEE.STD_LOGIC_1164.ALL; + USE IEEE.STD_LOGIC_UNSIGNED.ALL; + USE IEEE.STD_LOGIC_ARITH.ALL; + +ENTITY MT46V16M16 IS + GENERIC ( -- Timing for -75Z CL2 + tCK : TIME := 7.500 ns; + tCH : TIME := 3.375 ns; -- 0.45*tCK + tCL : TIME := 3.375 ns; -- 0.45*tCK + tDH : TIME := 0.500 ns; + tDS : TIME := 0.500 ns; + tIH : TIME := 0.900 ns; + tIS : TIME := 0.900 ns; + tMRD : TIME := 15.000 ns; + tRAS : TIME := 40.000 ns; + tRAP : TIME := 20.000 ns; + tRC : TIME := 65.000 ns; + tRFC : TIME := 75.000 ns; + tRCD : TIME := 20.000 ns; + tRP : TIME := 20.000 ns; + tRRD : TIME := 15.000 ns; + tWR : TIME := 15.000 ns; + addr_bits : INTEGER := 13; + data_bits : INTEGER := 16; + cols_bits : INTEGER := 9 + ); + PORT ( + Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); + Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ"; + Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + Clk : IN STD_LOGIC; + Clk_n : IN STD_LOGIC; + Cke : IN STD_LOGIC; + Cs_n : IN STD_LOGIC; + Ras_n : IN STD_LOGIC; + Cas_n : IN STD_LOGIC; + We_n : IN STD_LOGIC; + Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) + ); +END MT46V16M16; + +ARCHITECTURE behave OF MT46V16M16 IS + -- Array for Read pipeline + TYPE Array_Read_cmnd IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; + TYPE Array_Read_bank IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); + TYPE Array_Read_cols IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); + + -- Array for Write pipeline + TYPE Array_Write_cmnd IS ARRAY (2 DOWNTO 0) OF STD_LOGIC; + TYPE Array_Write_bank IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); + TYPE Array_Write_cols IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); + + -- Array for Auto Precharge + TYPE Array_Read_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC; + TYPE Array_Write_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC; + TYPE Array_Count_precharge IS ARRAY (3 DOWNTO 0) OF INTEGER; + + -- Array for Manual Precharge + TYPE Array_A10_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; + TYPE Array_Bank_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); + TYPE Array_Cmnd_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; + + -- Array for Burst Terminate + TYPE Array_Cmnd_bst IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; + + -- Array for Memory Access + TYPE Array_ram_type IS ARRAY (2**cols_bits - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0); + TYPE Array_ram_pntr IS ACCESS Array_ram_type; + TYPE Array_ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF Array_ram_pntr; + + -- Data pair + SIGNAL Dq_pair : STD_LOGIC_VECTOR (2 * data_bits - 1 DOWNTO 0); + SIGNAL Dm_pair : STD_LOGIC_VECTOR (3 DOWNTO 0); + + -- Mode Register + SIGNAL Mode_reg : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); + + -- Command Decode Variables + SIGNAL Active_enable, Aref_enable, Burst_term, Ext_mode_enable : STD_LOGIC := '0'; + SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : STD_LOGIC := '0'; + + -- Burst Length Decode Variables + SIGNAL Burst_length_2, Burst_length_4, Burst_length_8, Burst_length_f : STD_LOGIC := '0'; + + -- Cas Latency Decode Variables + SIGNAL Cas_latency_15, Cas_latency_2, Cas_latency_25, Cas_latency_3, Cas_latency_4 : STD_LOGIC := '0'; + + -- Internal Control Signals + SIGNAL Cs_in, Ras_in, Cas_in, We_in : STD_LOGIC := '0'; + + -- System Clock + SIGNAL Sys_clk : STD_LOGIC := '0'; + + -- Dqs buffer + SIGNAL Dqs_out : STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ"; + +BEGIN + -- Strip the strength + Cs_in <= To_X01 (Cs_n); + Ras_in <= To_X01 (Ras_n); + Cas_in <= To_X01 (Cas_n); + We_in <= To_X01 (We_n); + + -- Commands Decode + Active_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND We_in; + Aref_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND We_in; + Burst_term <= NOT(Cs_in) AND Ras_in AND Cas_in AND NOT(We_in); + Ext_mode_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND Ba(0) AND NOT(Ba(1)); + Mode_reg_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND NOT(Ba(0)) AND NOT(Ba(1)); + Prech_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND NOT(We_in); + Read_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND We_in; + Write_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND NOT(We_in); + + -- Burst Length Decode + Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0); + Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0)); + Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0); + Burst_length_f <= (Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0); + + -- CAS Latency Decode + Cas_latency_15 <= Mode_reg(6) AND NOT(Mode_reg(5)) AND (Mode_reg(4)); + Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4)); + Cas_latency_25 <= Mode_reg(6) AND Mode_reg(5) AND NOT(Mode_reg(4)); + Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4); + Cas_latency_4 <= (Mode_reg(6)) AND NOT(Mode_reg(5)) AND NOT(Mode_reg(4)); + + -- Dqs buffer + Dqs <= Dqs_out; + + -- + -- System Clock + -- + int_clk : PROCESS (Clk, Clk_n) + VARIABLE ClkZ, CkeZ : STD_LOGIC := '0'; + begin + IF Clk = '1' AND Clk_n = '0' THEN + ClkZ := '1'; + CkeZ := Cke; + ELSIF Clk = '0' AND Clk_n = '1' THEN + ClkZ := '0'; + END IF; + Sys_clk <= CkeZ AND ClkZ; + END PROCESS; + + -- + -- Main Process + -- + state_register : PROCESS + -- Precharge Variables + VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : STD_LOGIC := '0'; + + -- Activate Variables + VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : STD_LOGIC := '1'; + + -- Data IO variables + VARIABLE Data_in_enable, Data_out_enable : STD_LOGIC := '0'; + + -- Internal address mux variables + VARIABLE Cols_brst : STD_LOGIC_VECTOR (2 DOWNTO 0); + VARIABLE Prev_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; + VARIABLE Bank_addr : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; + VARIABLE Cols_addr : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); + VARIABLE Rows_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + VARIABLE B0_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + VARIABLE B1_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + VARIABLE B2_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + VARIABLE B3_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + + -- DLL Reset variables + VARIABLE DLL_enable : STD_LOGIC := '0'; + VARIABLE DLL_reset : STD_LOGIC := '0'; + VARIABLE DLL_done : STD_LOGIC := '0'; + VARIABLE DLL_count : INTEGER := 0; + + -- Timing Check + VARIABLE MRD_chk : TIME := 0 ns; + VARIABLE RFC_chk : TIME := 0 ns; + VARIABLE RRD_chk : TIME := 0 ns; + VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns; + VARIABLE RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3 : TIME := 0 ns; + VARIABLE RC_chk0, RC_chk1, RC_chk2, RC_chk3 : TIME := 0 ns; + VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns; + VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns; + VARIABLE WR_chk0, WR_chk1, WR_chk2, WR_chk3 : TIME := 0 ns; + + -- Read pipeline variables + VARIABLE Read_cmnd : Array_Read_cmnd; + VARIABLE Read_bank : Array_Read_bank; + VARIABLE Read_cols : Array_Read_cols; + + -- Write pipeline variables + VARIABLE Write_cmnd : Array_Write_cmnd; + VARIABLE Write_bank : Array_Write_bank; + VARIABLE Write_cols : Array_Write_cols; + + -- Auto Precharge variables + VARIABLE Read_precharge : Array_Read_precharge := ('0' & '0' & '0' & '0'); + VARIABLE Write_precharge : Array_Write_precharge := ('0' & '0' & '0' & '0'); + VARIABLE Count_precharge : Array_Count_precharge := ( 0 & 0 & 0 & 0 ); + + -- Manual Precharge variables + VARIABLE A10_precharge : Array_A10_precharge; + VARIABLE Bank_precharge : Array_Bank_precharge; + VARIABLE Cmnd_precharge : Array_Cmnd_precharge; + + -- Burst Terminate variable + VARIABLE Cmnd_bst : Array_Cmnd_bst; + + -- Memory Banks + VARIABLE Bank0 : Array_ram_stor; + VARIABLE Bank1 : Array_ram_stor; + VARIABLE Bank2 : Array_ram_stor; + VARIABLE Bank3 : Array_ram_stor; + + -- Burst Counter + VARIABLE Burst_counter : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); + + -- Internal Dqs initialize + VARIABLE Dqs_int : STD_LOGIC := '0'; + + -- Data buffer for DM Mask + VARIABLE Data_buf : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); + + -- + -- Initialize empty rows + -- + PROCEDURE Init_mem (Bank : STD_LOGIC_VECTOR; Row_index : INTEGER) IS + VARIABLE i, j : INTEGER := 0; + BEGIN + IF Bank = "00" THEN + IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty + Bank0 (Row_index) := NEW Array_ram_type; -- Open new row for access + FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros + FOR j IN (data_bits - 1) DOWNTO 0 LOOP + Bank0 (Row_index) (i) (j) := '0'; + END LOOP; + END LOOP; + END IF; + ELSIF Bank = "01" THEN + IF Bank1 (Row_index) = NULL THEN + Bank1 (Row_index) := NEW Array_ram_type; + FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP + FOR j IN (data_bits - 1) DOWNTO 0 LOOP + Bank1 (Row_index) (i) (j) := '0'; + END LOOP; + END LOOP; + END IF; + ELSIF Bank = "10" THEN + IF Bank2 (Row_index) = NULL THEN + Bank2 (Row_index) := NEW Array_ram_type; + FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP + FOR j IN (data_bits - 1) DOWNTO 0 LOOP + Bank2 (Row_index) (i) (j) := '0'; + END LOOP; + END LOOP; + END IF; + ELSIF Bank = "11" THEN + IF Bank3 (Row_index) = NULL THEN + Bank3 (Row_index) := NEW Array_ram_type; + FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP + FOR j IN (data_bits - 1) DOWNTO 0 LOOP + Bank3 (Row_index) (i) (j) := '0'; + END LOOP; + END LOOP; + END IF; + END IF; + END; + + -- + -- Burst Counter + -- + PROCEDURE Burst_decode IS + VARIABLE Cols_temp : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0) := (OTHERS => '0'); + BEGIN + -- Advance burst counter + Burst_counter := Burst_counter + 1; + + -- Burst Type + IF Mode_reg (3) = '0' THEN + Cols_temp := Cols_addr + 1; + ELSIF Mode_reg (3) = '1' THEN + Cols_temp (2) := Burst_counter (2) XOR Cols_brst (2); + Cols_temp (1) := Burst_counter (1) XOR Cols_brst (1); + Cols_temp (0) := Burst_counter (0) XOR Cols_brst (0); + END IF; + + -- Burst Length + IF Burst_length_2 = '1' THEN + Cols_addr (0) := Cols_temp (0); + ELSIF Burst_length_4 = '1' THEN + Cols_addr (1 DOWNTO 0) := Cols_temp (1 DOWNTO 0); + ELSIF Burst_length_8 = '1' THEN + Cols_addr (2 DOWNTO 0) := Cols_temp (2 DOWNTO 0); + ELSE + Cols_addr := Cols_temp; + END IF; + + -- Data counter + IF Burst_length_2 = '1' THEN + IF Burst_counter >= 2 THEN + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + ELSIF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + ELSIF Burst_length_4 = '1' THEN + IF Burst_counter >= 4 THEN + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + ELSIF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + ELSIF Burst_length_8 = '1' THEN + IF Burst_counter >= 8 THEN + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + ELSIF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + END IF; + END; + + BEGIN + WAIT ON Sys_clk; + + -- + -- Manual Precharge Pipeline + -- + IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN + -- A10 Precharge Pipeline + A10_precharge(0) := A10_precharge(1); + A10_precharge(1) := A10_precharge(2); + A10_precharge(2) := A10_precharge(3); + A10_precharge(3) := A10_precharge(4); + A10_precharge(4) := A10_precharge(5); + A10_precharge(5) := A10_precharge(6); + A10_precharge(6) := A10_precharge(7); + A10_precharge(7) := A10_precharge(8); + A10_precharge(8) := '0'; + + -- Bank Precharge Pipeline + Bank_precharge(0) := Bank_precharge(1); + Bank_precharge(1) := Bank_precharge(2); + Bank_precharge(2) := Bank_precharge(3); + Bank_precharge(3) := Bank_precharge(4); + Bank_precharge(4) := Bank_precharge(5); + Bank_precharge(5) := Bank_precharge(6); + Bank_precharge(6) := Bank_precharge(7); + Bank_precharge(7) := Bank_precharge(8); + Bank_precharge(8) := "00"; + + -- Command Precharge Pipeline + Cmnd_precharge(0) := Cmnd_precharge(1); + Cmnd_precharge(1) := Cmnd_precharge(2); + Cmnd_precharge(2) := Cmnd_precharge(3); + Cmnd_precharge(3) := Cmnd_precharge(4); + Cmnd_precharge(4) := Cmnd_precharge(5); + Cmnd_precharge(5) := Cmnd_precharge(6); + Cmnd_precharge(6) := Cmnd_precharge(7); + Cmnd_precharge(7) := Cmnd_precharge(8); + Cmnd_precharge(8) := '0'; + + -- Terminate Read if same bank or all banks + IF ((Cmnd_precharge (0) = '1') AND + (Bank_precharge (0) = Bank_addr OR A10_precharge (0) = '1') AND + (Data_out_enable = '1')) THEN + Data_out_enable := '0'; + END IF; + END IF; + + -- + -- Burst Terminate Pipeline + -- + IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN + -- Burst Terminate pipeline + Cmnd_bst (0) := Cmnd_bst (1); + Cmnd_bst (1) := Cmnd_bst (2); + Cmnd_bst (2) := Cmnd_bst (3); + Cmnd_bst (3) := Cmnd_bst (4); + Cmnd_bst (4) := Cmnd_bst (5); + Cmnd_bst (5) := Cmnd_bst (6); + Cmnd_bst (6) := Cmnd_bst (7); + Cmnd_bst (7) := Cmnd_bst (8); + Cmnd_bst (8) := '0'; + + -- Terminate current Read + IF ((Cmnd_bst (0) = '1') AND (Data_out_enable = '1')) THEN + Data_out_enable := '0'; + END IF; + END IF; + + -- + -- Dq and Dqs Drivers + -- + IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN + -- Read Command Pipeline + Read_cmnd (0) := Read_cmnd (1); + Read_cmnd (1) := Read_cmnd (2); + Read_cmnd (2) := Read_cmnd (3); + Read_cmnd (3) := Read_cmnd (4); + Read_cmnd (4) := Read_cmnd (5); + Read_cmnd (5) := Read_cmnd (6); + Read_cmnd (6) := Read_cmnd (7); + Read_cmnd (7) := Read_cmnd (8); + Read_cmnd (8) := '0'; + + -- Read Bank Pipeline + Read_bank (0) := Read_bank (1); + Read_bank (1) := Read_bank (2); + Read_bank (2) := Read_bank (3); + Read_bank (3) := Read_bank (4); + Read_bank (4) := Read_bank (5); + Read_bank (5) := Read_bank (6); + Read_bank (6) := Read_bank (7); + Read_bank (7) := Read_bank (8); + Read_bank (8) := "00"; + + -- Read Column Pipeline + Read_cols (0) := Read_cols (1); + Read_cols (1) := Read_cols (2); + Read_cols (2) := Read_cols (3); + Read_cols (3) := Read_cols (4); + Read_cols (4) := Read_cols (5); + Read_cols (5) := Read_cols (6); + Read_cols (6) := Read_cols (7); + Read_cols (7) := Read_cols (8); + Read_cols (8) := (OTHERS => '0'); + + -- Initialize Read command + IF Read_cmnd (0) = '1' THEN + Data_out_enable := '1'; + Bank_addr := Read_bank (0); + Cols_addr := Read_cols (0); + Cols_brst := Cols_addr (2 DOWNTO 0); + Burst_counter := (OTHERS => '0'); + + -- Row address mux + CASE Bank_addr IS + WHEN "00" => Rows_addr := B0_row_addr; + WHEN "01" => Rows_addr := B1_row_addr; + WHEN "10" => Rows_addr := B2_row_addr; + WHEN OTHERS => Rows_addr := B3_row_addr; + END CASE; + END IF; + + -- Toggle Dqs during Read command + IF Data_out_enable = '1' THEN + Dqs_int := '0'; + IF Dqs_out = "00" THEN + Dqs_out <= "11"; + ELSIF Dqs_out = "11" THEN + Dqs_out <= "00"; + ELSE + Dqs_out <= "00"; + END IF; + ELSIF Data_out_enable = '0' AND Dqs_int = '0' THEN + Dqs_out <= "ZZ"; + END IF; + + -- Initialize Dqs for Read command + IF Read_cmnd (2) = '1' THEN + IF Data_out_enable = '0' THEN + Dqs_int := '1'; + Dqs_out <= "00"; + END IF; + END IF; + + -- Read Latch + IF Data_out_enable = '1' THEN + -- Initialize Memory + Init_mem (Bank_addr, CONV_INTEGER(Rows_addr)); + + -- Output Data + CASE Bank_addr IS + WHEN "00" => Dq <= Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); + WHEN "01" => Dq <= Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); + WHEN "10" => Dq <= Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); + WHEN OTHERS => Dq <= Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); + END CASE; + + -- Increase Burst Counter + Burst_decode; + ELSE + Dq <= (OTHERS => 'Z'); + END IF; + END IF; + + -- + -- Write FIFO and DM Mask Logic + -- + IF Sys_clk'EVENT AND Sys_clk = '1' THEN + -- Write command pipeline + Write_cmnd (0) := Write_cmnd (1); + Write_cmnd (1) := Write_cmnd (2); + Write_cmnd (2) := '0'; + + -- Write command pipeline + Write_bank (0) := Write_bank (1); + Write_bank (1) := Write_bank (2); + Write_bank (2) := "00"; + + -- Write column pipeline + Write_cols (0) := Write_cols (1); + Write_cols (1) := Write_cols (2); + Write_cols (2) := (OTHERS => '0'); + + -- Initialize Write command + IF Write_cmnd (0) = '1' THEN + Data_in_enable := '1'; + Bank_addr := Write_bank (0); + Cols_addr := Write_cols (0); + Cols_brst := Cols_addr (2 DOWNTO 0); + Burst_counter := (OTHERS => '0'); + + -- Row address mux + CASE Bank_addr IS + WHEN "00" => Rows_addr := B0_row_addr; + WHEN "01" => Rows_addr := B1_row_addr; + WHEN "10" => Rows_addr := B2_row_addr; + WHEN OTHERS => Rows_addr := B3_row_addr; + END CASE; + END IF; + + -- Write data + IF Data_in_enable = '1' THEN + -- Initialize memory + Init_mem (Bank_addr, CONV_INTEGER(Rows_addr)); + + -- Write first data + IF Dm_pair (1) = '0' OR Dm_pair (0) = '0' THEN + -- Data Buffer + CASE Bank_addr IS + WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); + WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); + WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); + WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); + END CASE; + + -- Perform DM Mask + IF Dm_pair (0) = '0' THEN + Data_buf ( 7 DOWNTO 0) := Dq_pair ( 7 DOWNTO 0); + END IF; + IF Dm_pair (1) = '0' THEN + Data_buf (15 DOWNTO 8) := Dq_pair (15 DOWNTO 8); + END IF; + + -- Write Data + CASE Bank_addr IS + WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; + WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; + WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; + WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; + END CASE; + END IF; + + -- Increase Burst Counter + Burst_decode; + + -- Write second data + IF Dm_pair (3) = '0' OR Dm_pair (2) = '0' THEN + -- Data Buffer + CASE Bank_addr IS + WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); + WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); + WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); + WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); + END CASE; + + -- Perform DM Mask + IF Dm_pair (2) = '0' THEN + Data_buf ( 7 DOWNTO 0) := Dq_pair (23 DOWNTO 16); + END IF; + IF Dm_pair (3) = '0' THEN + Data_buf (15 DOWNTO 8) := Dq_pair (31 DOWNTO 24); + END IF; + + -- Write Data + CASE Bank_addr IS + WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; + WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; + WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; + WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; + END CASE; + END IF; + + -- Increase Burst Counter + Burst_decode; + + -- tWR start and tWTR check + IF Dm_pair (3 DOWNTO 2) = "00" OR Dm_pair (1 DOWNTO 0) = "00" THEN + CASE Bank_addr IS + WHEN "00" => WR_chk0 := NOW; + WHEN "01" => WR_chk1 := NOW; + WHEN "10" => WR_chk2 := NOW; + WHEN OTHERS => WR_chk3 := NOW; + END CASE; + + -- tWTR check + ASSERT (Read_enable = '0') + REPORT "tWTR violation during Read" + SEVERITY WARNING; + END IF; + END IF; + END IF; + + -- + -- Auto Precharge Calculation + -- + IF Sys_clk'EVENT AND Sys_clk = '1' THEN + -- Precharge counter + IF Read_precharge (0) = '1' OR Write_precharge (0) = '1' THEN + Count_precharge (0) := Count_precharge (0) + 1; + END IF; + IF Read_precharge (1) = '1' OR Write_precharge (1) = '1' THEN + Count_precharge (1) := Count_precharge (1) + 1; + END IF; + IF Read_precharge (2) = '1' OR Write_precharge (2) = '1' THEN + Count_precharge (2) := Count_precharge (2) + 1; + END IF; + IF Read_precharge (3) = '1' OR Write_precharge (3) = '1' THEN + Count_precharge (3) := Count_precharge (3) + 1; + END IF; + + -- Read with AutoPrecharge Calculation + -- The device start internal precharge when: + -- 1. Meet tRAS requirement + -- 2. BL/2 cycles after command + IF ((Read_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN + IF ((Burst_length_2 = '1' AND Count_precharge(0) >= 1) OR + (Burst_length_4 = '1' AND Count_precharge(0) >= 2) OR + (Burst_length_8 = '1' AND Count_precharge(0) >= 4)) THEN + Pc_b0 := '1'; + Act_b0 := '0'; + RP_chk0 := NOW; + Read_precharge(0) := '0'; + END IF; + END IF; + IF ((Read_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN + IF ((Burst_length_2 = '1' AND Count_precharge(1) >= 1) OR + (Burst_length_4 = '1' AND Count_precharge(1) >= 2) OR + (Burst_length_8 = '1' AND Count_precharge(1) >= 4)) THEN + Pc_b1 := '1'; + Act_b1 := '0'; + RP_chk1 := NOW; + Read_precharge(1) := '0'; + END IF; + END IF; + IF ((Read_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN + IF ((Burst_length_2 = '1' AND Count_precharge(2) >= 1) OR + (Burst_length_4 = '1' AND Count_precharge(2) >= 2) OR + (Burst_length_8 = '1' AND Count_precharge(2) >= 4)) THEN + Pc_b2 := '1'; + Act_b2 := '0'; + RP_chk2 := NOW; + Read_precharge(2) := '0'; + END IF; + END IF; + IF ((Read_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN + IF ((Burst_length_2 = '1' AND Count_precharge(3) >= 1) OR + (Burst_length_4 = '1' AND Count_precharge(3) >= 2) OR + (Burst_length_8 = '1' AND Count_precharge(3) >= 4)) THEN + Pc_b3 := '1'; + Act_b3 := '0'; + RP_chk3 := NOW; + Read_precharge(3) := '0'; + END IF; + END IF; + + -- Write with AutoPrecharge Calculation + -- The device start internal precharge when: + -- 1. Meet tRAS requirement + -- 2. Two clock after last burst + -- Since tWR is time base, the model will compensate tRP + IF ((Write_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN + IF ((Burst_length_2 = '1' AND Count_precharge (0) >= 4) OR + (Burst_length_4 = '1' AND Count_precharge (0) >= 5) OR + (Burst_length_8 = '1' AND Count_precharge (0) >= 7)) THEN + Pc_b0 := '1'; + Act_b0 := '0'; + RP_chk0 := NOW - ((2 * tCK) - tWR); + Write_precharge(0) := '0'; + END IF; + END IF; + IF ((Write_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN + IF ((Burst_length_2 = '1' AND Count_precharge (1) >= 4) OR + (Burst_length_4 = '1' AND Count_precharge (1) >= 5) OR + (Burst_length_8 = '1' AND Count_precharge (1) >= 7)) THEN + Pc_b1 := '1'; + Act_b1 := '0'; + RP_chk1 := NOW - ((2 * tCK) - tWR); + Write_precharge(1) := '0'; + END IF; + END IF; + IF ((Write_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN + IF ((Burst_length_2 = '1' AND Count_precharge (2) >= 4) OR + (Burst_length_4 = '1' AND Count_precharge (2) >= 5) OR + (Burst_length_8 = '1' AND Count_precharge (2) >= 7)) THEN + Pc_b2 := '1'; + Act_b2 := '0'; + RP_chk2 := NOW - ((2 * tCK) - tWR); + Write_precharge(2) := '0'; + END IF; + END IF; + IF ((Write_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN + IF ((Burst_length_2 = '1' AND Count_precharge (3) >= 4) OR + (Burst_length_4 = '1' AND Count_precharge (3) >= 5) OR + (Burst_length_8 = '1' AND Count_precharge (3) >= 7)) THEN + Pc_b3 := '1'; + Act_b3 := '0'; + RP_chk3 := NOW - ((2 * tCK) - tWR); + Write_precharge(3) := '0'; + END IF; + END IF; + END IF; + + -- + -- DLL Counter + -- + IF Sys_clk'EVENT AND Sys_clk = '1' THEN + IF (DLL_Reset = '1' AND DLL_done = '0') THEN + DLL_count := DLL_count + 1; + IF (DLL_count >= 200) THEN + DLL_done := '1'; + END IF; + END IF; + END IF; + + -- + -- Control Logic + -- + IF Sys_clk'EVENT AND Sys_clk = '1' THEN + -- Auto Refresh + IF Aref_enable = '1' THEN + -- Auto Refresh to Auto Refresh + ASSERT (NOW - RFC_chk >= tRFC) + REPORT "tRFC violation during Auto Refresh" + SEVERITY WARNING; + + -- Precharge to Auto Refresh + ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND + (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) + REPORT "tRP violation during Auto Refresh" + SEVERITY WARNING; + + -- Precharge to Auto Refresh + ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') + REPORT "All banks must be Precharge before Auto Refresh" + SEVERITY WARNING; + + -- Record current tRFC time + RFC_chk := NOW; + END IF; + + -- Extended Load Mode Register + IF Ext_mode_enable = '1' THEN + IF (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') THEN + IF (Addr (0) = '0') THEN + DLL_enable := '1'; + ELSE + DLL_enable := '0'; + END IF; + END IF; + + -- Precharge to EMR + ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') + REPORT "All bank must be Precharged before Extended Mode Register" + SEVERITY WARNING; + + -- Precharge to EMR + ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND + (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) + REPORT "tRP violation during Extended Load Register" + SEVERITY WARNING; + + -- LMR/EMR to EMR + ASSERT (NOW - MRD_chk >= tMRD) + REPORT "tMRD violation during Extended Mode Register" + SEVERITY WARNING; + + -- Record current tMRD time + MRD_chk := NOW; + END IF; + + -- Load Mode Register + IF Mode_reg_enable = '1' THEN + -- Register mode + Mode_reg <= Addr; + + -- DLL Reset + IF (DLL_enable = '1' AND Addr (8) = '1') THEN + DLL_reset := '1'; + DLL_done := '0'; + DLL_count := 0; + ELSIF (DLL_enable = '1' AND DLL_reset = '0' AND Addr (8) = '0') THEN + ASSERT (FALSE) + REPORT "DLL is ENABLE: DLL RESET is require" + SEVERITY WARNING; + ELSIF (DLL_enable = '0' AND Addr (8) = '1') THEN + ASSERT (FALSE) + REPORT "DLL is DISABLE: DLL RESET will be ignored" + SEVERITY WARNING; + END IF; + + -- Precharge to LMR + ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') + REPORT "All bank must be Precharged before Load Mode Register" + SEVERITY WARNING; + + -- Precharge to EMR + ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND + (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) + REPORT "tRP violation during Load Mode Register" + SEVERITY WARNING; + + -- LMR/ELMR to LMR + ASSERT (NOW - MRD_chk >= tMRD) + REPORT "tMRD violation during Load Mode Register" + SEVERITY WARNING; + + -- Check for invalid Burst Length + ASSERT ((Addr (2 DOWNTO 0) = "001") OR -- BL = 2 + (Addr (2 DOWNTO 0) = "010") OR -- BL = 4 + (Addr (2 DOWNTO 0) = "011")) -- BL = 8 + REPORT "Invalid Burst Length during Load Mode Register" + SEVERITY WARNING; + + -- Check for invalid CAS Latency + ASSERT ((Addr (6 DOWNTO 4) = "010") OR -- CL = 2.0 + (Addr (6 DOWNTO 4) = "110")) -- CL = 2.5 + REPORT "Invalid CAS Latency during Load Mode Register" + SEVERITY WARNING; + + -- Record current tMRD time + MRD_chk := NOW; + END IF; + + -- Active Block (latch Bank and Row Address) + IF Active_enable = '1' THEN + -- Activate an OPEN bank can corrupt data + ASSERT ((Ba = "00" AND Act_b0 = '0') OR + (Ba = "01" AND Act_b1 = '0') OR + (Ba = "10" AND Act_b2 = '0') OR + (Ba = "11" AND Act_b3 = '0')) + REPORT "Bank is already activated - data can be corrupted" + SEVERITY WARNING; + + -- Activate Bank 0 + IF Ba = "00" AND Pc_b0 = '1' THEN + -- Activate to Activate (same bank) + ASSERT (NOW - RC_chk0 >= tRC) + REPORT "tRC violation during Activate Bank 0" + SEVERITY WARNING; + + -- Precharge to Active + ASSERT (NOW - RP_chk0 >= tRP) + REPORT "tRP violation during Activate Bank 0" + SEVERITY WARNING; + + -- Record Variables for checking violation + Act_b0 := '1'; + Pc_b0 := '0'; + B0_row_addr := Addr; + RC_chk0 := NOW; + RCD_chk0 := NOW; + RAS_chk0 := NOW; + RAP_chk0 := NOW; + END IF; + + -- Activate Bank 1 + IF Ba = "01" AND Pc_b1 = '1' THEN + -- Activate to Activate (same bank) + ASSERT (NOW - RC_chk1 >= tRC) + REPORT "tRC violation during Activate Bank 1" + SEVERITY WARNING; + + -- Precharge to Active + ASSERT (NOW - RP_chk1 >= tRP) + REPORT "tRP violation during Activate Bank 1" + SEVERITY WARNING; + + -- Record Variables for checking violation + Act_b1 := '1'; + Pc_b1 := '0'; + B1_row_addr := Addr; + RC_chk1 := NOW; + RCD_chk1 := NOW; + RAS_chk1 := NOW; + RAP_chk1 := NOW; + END IF; + + -- Activate Bank 2 + IF Ba = "10" AND Pc_b2 = '1' THEN + -- Activate to Activate (same bank) + ASSERT (NOW - RC_chk2 >= tRC) + REPORT "tRC violation during Activate Bank 2" + SEVERITY WARNING; + + -- Precharge to Active + ASSERT (NOW - RP_chk2 >= tRP) + REPORT "tRP violation during Activate Bank 2" + SEVERITY WARNING; + + -- Record Variables for checking violation + Act_b2 := '1'; + Pc_b2 := '0'; + B2_row_addr := Addr; + RC_chk2 := NOW; + RCD_chk2 := NOW; + RAS_chk2 := NOW; + RAP_chk2 := NOW; + END IF; + + -- Activate Bank 3 + IF Ba = "11" AND Pc_b3 = '1' THEN + -- Activate to Activate (same bank) + ASSERT (NOW - RC_chk3 >= tRC) + REPORT "tRC violation during Activate Bank 3" + SEVERITY WARNING; + + -- Precharge to Active + ASSERT (NOW - RP_chk3 >= tRP) + REPORT "tRP violation during Activate Bank 3" + SEVERITY WARNING; + + -- Record Variables for checking violation + Act_b3 := '1'; + Pc_b3 := '0'; + B3_row_addr := Addr; + RC_chk3 := NOW; + RCD_chk3 := NOW; + RAS_chk3 := NOW; + RAP_chk3 := NOW; + END IF; + + -- Activate Bank A to Activate Bank B + IF (Prev_bank /= Ba) THEN + ASSERT (NOW - RRD_chk >= tRRD) + REPORT "tRRD violation during Activate" + SEVERITY WARNING; + END IF; + + -- AutoRefresh to Activate + ASSERT (NOW - RFC_chk >= tRFC) + REPORT "tRFC violation during Activate" + SEVERITY WARNING; + + -- Record Variables for Checking Violation + RRD_chk := NOW; + Prev_bank := Ba; + END IF; + + -- Precharge Block - Consider NOP if bank already precharged or in process of precharging + IF Prech_enable = '1' THEN + -- EMR or LMR to Precharge + ASSERT (NOW - MRD_chk >= tMRD) + REPORT "tMRD violation during Precharge" + SEVERITY WARNING; + + -- Precharge Bank 0 + IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "00")) AND Act_b0 = '1') THEN + Act_b0 := '0'; + Pc_b0 := '1'; + RP_chk0 := NOW; + + -- Activate to Precharge bank 0 + ASSERT (NOW - RAS_chk0 >= tRAS) + REPORT "tRAS violation during Precharge" + SEVERITY WARNING; + + -- tWR violation check for Write + ASSERT (NOW - WR_chk0 >= tWR) + REPORT "tWR violation during Precharge" + SEVERITY WARNING; + END IF; + + -- Precharge Bank 1 + IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "01")) AND Act_b1 = '1') THEN + Act_b1 := '0'; + Pc_b1 := '1'; + RP_chk1 := NOW; + + -- Activate to Precharge + ASSERT (NOW - RAS_chk1 >= tRAS) + REPORT "tRAS violation during Precharge" + SEVERITY WARNING; + + -- tWR violation check for Write + ASSERT (NOW - WR_chk1 >= tWR) + REPORT "tWR violation during Precharge" + SEVERITY WARNING; + END IF; + + -- Precharge Bank 2 + IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "10")) AND Act_b2 = '1') THEN + Act_b2 := '0'; + Pc_b2 := '1'; + RP_chk2 := NOW; + + -- Activate to Precharge + ASSERT (NOW - RAS_chk2 >= tRAS) + REPORT "tRAS violation during Precharge" + SEVERITY WARNING; + + -- tWR violation check for Write + ASSERT (NOW - WR_chk2 >= tWR) + REPORT "tWR violation during Precharge" + SEVERITY WARNING; + END IF; + + -- Precharge Bank 3 + IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "11")) AND Act_b3 = '1') THEN + Act_b3 := '0'; + Pc_b3 := '1'; + RP_chk3 := NOW; + + -- Activate to Precharge + ASSERT (NOW - RAS_chk3 >= tRAS) + REPORT "tRAS violation during Precharge" + SEVERITY WARNING; + + -- tWR violation check for Write + ASSERT (NOW - WR_chk3 >= tWR) + REPORT "tWR violation during Precharge" + SEVERITY WARNING; + END IF; + + -- Pipeline for READ + IF CAS_latency_15 = '1' THEN + A10_precharge (3) := Addr(10); + Bank_precharge (3) := Ba; + Cmnd_precharge (3) := '1'; + ELSIF CAS_latency_2 = '1' THEN + A10_precharge (4) := Addr(10); + Bank_precharge (4) := Ba; + Cmnd_precharge (4) := '1'; + ELSIF CAS_latency_25 = '1' THEN + A10_precharge (5) := Addr(10); + Bank_precharge (5) := Ba; + Cmnd_precharge (5) := '1'; + ELSIF CAS_latency_3 = '1' THEN + A10_precharge (6) := Addr(10); + Bank_precharge (6) := Ba; + Cmnd_precharge (6) := '1'; + ELSIF CAS_latency_4 = '1' THEN + A10_precharge (8) := Addr(10); + Bank_precharge (8) := Ba; + Cmnd_precharge (8) := '1'; + END IF; + END IF; + + -- Burst Terminate + IF Burst_term = '1' THEN + -- Pipeline for Read + IF CAS_latency_15 = '1' THEN + Cmnd_bst (3) := '1'; + ELSIF CAS_latency_2 = '1' THEN + Cmnd_bst (4) := '1'; + ELSIF CAS_latency_25 = '1' THEN + Cmnd_bst (5) := '1'; + ELSIF CAS_latency_3 = '1' THEN + Cmnd_bst (6) := '1'; + ELSIF CAS_latency_4 = '1' THEN + Cmnd_bst (8) := '1'; + END IF; + + -- Terminate Write + ASSERT (Data_in_enable = '0') + REPORT "It's illegal to Burst Terminate a Write" + SEVERITY WARNING; + + -- Terminate Read with Auto Precharge + ASSERT (Read_precharge (0) = '0' AND Read_precharge (1) = '0' AND + Read_precharge (2) = '0' AND Read_precharge (3) = '0') + REPORT "It's illegal to Burst Terminate a Read with Auto Precharge" + SEVERITY WARNING; + END IF; + + -- Read Command + IF Read_enable = '1' THEN + -- CAS Latency Pipeline + IF Cas_latency_15 = '1' THEN + Read_cmnd (3) := '1'; + Read_bank (3) := Ba; + Read_cols (3) := Addr (8 DOWNTO 0); + ELSIF Cas_latency_2 = '1' THEN + Read_cmnd (4) := '1'; + Read_bank (4) := Ba; + Read_cols (4) := Addr (8 DOWNTO 0); + ELSIF Cas_latency_25 = '1' THEN + Read_cmnd (5) := '1'; + Read_bank (5) := Ba; + Read_cols (5) := Addr (8 DOWNTO 0); + ELSIF Cas_latency_3 = '1' THEN + Read_cmnd (6) := '1'; + Read_bank (6) := Ba; + Read_cols (6) := Addr (8 DOWNTO 0); + ELSIF Cas_latency_4 = '1' THEN + Read_cmnd (8) := '1'; + Read_bank (8) := Ba; + Read_cols (8) := Addr (8 DOWNTO 0); + END IF; + + -- Write to Read: Terminate Write Immediately + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + END IF; + + -- Interrupting a Read with Auto Precharge (same bank only) + ASSERT (Read_precharge(CONV_INTEGER(Ba)) = '0') + REPORT "It's illegal to interrupt a Read with Auto Precharge" + SEVERITY WARNING; + + -- Activate to Read + ASSERT ((Ba = "00" AND Act_b0 = '1') OR + (Ba = "01" AND Act_b1 = '1') OR + (Ba = "10" AND Act_b2 = '1') OR + (Ba = "11" AND Act_b3 = '1')) + REPORT "Bank is not Activated for Read" + SEVERITY WARNING; + + -- Activate to Read without Auto Precharge + IF Addr (10) = '0' THEN + ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR + (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR + (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR + (Ba = "11" AND NOW - RCD_chk3 >= tRCD)) + REPORT "tRCD violation during Read" + SEVERITY WARNING; + END IF; + + -- Activate to Read with Auto Precharge + IF Addr (10) = '1' THEN + ASSERT ((Ba = "00" AND NOW - RAP_chk0 >= tRAP) OR + (Ba = "01" AND NOW - RAP_chk1 >= tRAP) OR + (Ba = "10" AND NOW - RAP_chk2 >= tRAP) OR + (Ba = "11" AND NOW - RAP_chk3 >= tRAP)) + REPORT "tRAP violation during Read" + SEVERITY WARNING; + END IF; + + -- Auto precharge + IF Addr (10) = '1' THEN + Read_precharge (Conv_INTEGER(Ba)) := '1'; + Count_precharge (Conv_INTEGER(Ba)) := 0; + END IF; + + -- DLL Check + IF (DLL_reset = '1') THEN + ASSERT (DLL_done = '1') + REPORT "DLL RESET not complete" + SEVERITY WARNING; + END IF; + END IF; + + -- Write Command + IF Write_enable = '1' THEN + -- Pipeline for Write + Write_cmnd (2) := '1'; + Write_bank (2) := Ba; + Write_cols (2) := Addr (8 DOWNTO 0); + + -- Interrupting a Write with Auto Precharge (same bank only) + ASSERT (Write_precharge(CONV_INTEGER(Ba)) = '0') + REPORT "It's illegal to interrupt a Write with Auto Precharge" + SEVERITY WARNING; + + -- Activate to Write + ASSERT ((Ba = "00" AND Act_b0 = '1') OR + (Ba = "01" AND Act_b1 = '1') OR + (Ba = "10" AND Act_b2 = '1') OR + (Ba = "11" AND Act_b3 = '1')) + REPORT "Bank is not Activated for Write" + SEVERITY WARNING; + + -- Activate to Write + ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR + (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR + (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR + (Ba = "11" AND NOW - RCD_chk3 >= tRCD)) + REPORT "tRCD violation during Write" + SEVERITY WARNING; + + -- Auto precharge + IF Addr (10) = '1' THEN + Write_precharge (Conv_INTEGER(Ba)) := '1'; + Count_precharge (Conv_INTEGER(Ba)) := 0; + END IF; + END IF; + END IF; + END PROCESS; + + -- + -- Dqs Receiver + -- + dqs_rcvrs : PROCESS + VARIABLE Dm_temp : STD_LOGIC_VECTOR (1 DOWNTO 0); + VARIABLE Dq_temp : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0); + BEGIN + WAIT ON Dqs; + -- Latch data at posedge Dqs + IF Dqs'EVENT AND Dqs (1) = '1' AND Dqs (0) = '1' THEN + Dq_temp := Dq; + Dm_temp := Dm; + END IF; + -- Latch data at negedge Dqs + IF Dqs'EVENT AND Dqs (1) = '0' AND Dqs (0) = '0' THEN + Dq_pair <= (Dq & Dq_temp); + Dm_pair <= (Dm & Dm_temp); + END IF; + END PROCESS; + + -- + -- Setup timing checks + -- + Setup_check : PROCESS + BEGIN + WAIT ON Sys_clk; + IF Sys_clk'EVENT AND Sys_clk = '1' THEN + ASSERT(Cke'LAST_EVENT >= tIS) + REPORT "CKE Setup time violation -- tIS" + SEVERITY WARNING; + ASSERT(Cs_n'LAST_EVENT >= tIS) + REPORT "CS# Setup time violation -- tIS" + SEVERITY WARNING; + ASSERT(Cas_n'LAST_EVENT >= tIS) + REPORT "CAS# Setup time violation -- tIS" + SEVERITY WARNING; + ASSERT(Ras_n'LAST_EVENT >= tIS) + REPORT "RAS# Setup time violation -- tIS" + SEVERITY WARNING; + ASSERT(We_n'LAST_EVENT >= tIS) + REPORT "WE# Setup time violation -- tIS" + SEVERITY WARNING; + ASSERT(Addr'LAST_EVENT >= tIS) + REPORT "ADDR Setup time violation -- tIS" + SEVERITY WARNING; + ASSERT(Ba'LAST_EVENT >= tIS) + REPORT "BA Setup time violation -- tIS" + SEVERITY WARNING; + END IF; + END PROCESS; + + -- + -- Hold timing checks + -- + Hold_check : PROCESS + BEGIN + WAIT ON Sys_clk'DELAYED (tIH); + IF Sys_clk'DELAYED (tIH) = '1' THEN + ASSERT(Cke'LAST_EVENT >= tIH) + REPORT "CKE Hold time violation -- tIH" + SEVERITY WARNING; + ASSERT(Cs_n'LAST_EVENT >= tIH) + REPORT "CS# Hold time violation -- tIH" + SEVERITY WARNING; + ASSERT(Cas_n'LAST_EVENT >= tIH) + REPORT "CAS# Hold time violation -- tIH" + SEVERITY WARNING; + ASSERT(Ras_n'LAST_EVENT >= tIH) + REPORT "RAS# Hold time violation -- tIH" + SEVERITY WARNING; + ASSERT(We_n'LAST_EVENT >= tIH) + REPORT "WE# Hold time violation -- tIH" + SEVERITY WARNING; + ASSERT(Addr'LAST_EVENT >= tIH) + REPORT "ADDR Hold time violation -- tIH" + SEVERITY WARNING; + ASSERT(Ba'LAST_EVENT >= tIH) + REPORT "BA Hold time violation -- tIH" + SEVERITY WARNING; + END IF; + END PROCESS; + +END behave; diff --git a/misc/readme.txt b/misc/readme.txt new file mode 100644 index 0000000..0ae1786 --- /dev/null +++ b/misc/readme.txt @@ -0,0 +1,20 @@ +These files are provided as is under a FreeBSD license. + +Patches most gratefully accepted to document this better. + +These are parts of the VHDL code that went into ZY2000 that +can be used on other FPGA brands and with other parts than +went into ZY2000. + +http://www.zylin.com/protoboard.htm + +The long term plan is to split out these from the ZPU project +into a DDR controller and ARM7 wishbone bridge +project on OpenCores.org and document them. + +Directories +=========== +arm7 - ARM7 wishbone interface +ddsdram - a generic ddr ram controller. Implemented for Xilinx + mt46v16m16 but +can be adapted to other FPGA brands and DRAM chips +wishbone - atomic 32 bit wishbone access inside FPGA and in ARM7 SW, over a 16 bit CPU databus \ No newline at end of file diff --git a/misc/wishbone/src/atomic32_access.vhd b/misc/wishbone/src/atomic32_access.vhd new file mode 100644 index 0000000..b062f98 --- /dev/null +++ b/misc/wishbone/src/atomic32_access.vhd @@ -0,0 +1,132 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +--use work.phi_config.all; +use work.wishbone_pkg.all; + +entity atomic32_access is + port ( cpu_clk : in std_logic; + areset : in std_logic; + + -- Wishbone from CPU interface + wb_16_i : in wishbone_bus_in; + wb_16_o : out wishbone_bus_out; + + -- Wishbone to FPGA registers and ethernet core + wb_32_i : in wishbone_bus_out; + wb_32_o : out wishbone_bus_in); +end atomic32_access; + +architecture behave of atomic32_access is + +type eth_state_wr_type is (idle, lsb_msb, lsb, msb, write, ack, wait_st); +signal eth_state_wr : eth_state_wr_type; +type eth_state_rd_type is (idle, lsb_msb, lsb_read, lsb, wait_st2, msb); +signal eth_state_rd : eth_state_rd_type; +signal core_data : std_logic_vector(31 downto 0); +signal core_addr : std_logic_vector(31 downto 0); + +begin + process(cpu_clk, areset) + begin + if areset = '1' then + eth_state_wr <= idle; + eth_state_rd <= idle; + wb_32_o.stb <= '0'; + wb_32_o.cyc <= '0'; + wb_16_o.ack <= '0'; + core_data <= (others => '0'); + core_addr <= (others => '0'); + elsif (rising_edge(cpu_clk)) then + + case eth_state_wr is --write cycle + when idle => + if wb_16_i.cyc = '1' and wb_16_i.we = '1' then + eth_state_wr <= lsb_msb; + end if; + when lsb_msb => + if wb_16_i.adr(1) = '0' then + eth_state_wr <= lsb; + end if; + if wb_16_i.adr(1) = '1' then + eth_state_wr <= msb; + end if; + when lsb => + core_data(15 downto 0) <= wb_16_i.dat(15 downto 0); + wb_16_o.ack <= '1'; + eth_state_wr <= wait_st; + when msb => + core_data(31 downto 16) <= wb_16_i.dat(31 downto 16); + core_addr <= wb_16_i.adr(31 downto 2) & "00"; + eth_state_wr <= write; + when write => + wb_32_o.dat <= core_data; + wb_32_o.adr <= core_addr; + wb_32_o.sel <= "1111"; + wb_32_o.we <= '1'; + wb_32_o.stb <= '1'; + wb_32_o.cyc <= '1'; + eth_state_wr <= ack; + when ack => + if wb_32_i.ack = '1' then + wb_16_o.ack <= '1'; + eth_state_wr <= wait_st; + wb_32_o.stb <= '0'; + wb_32_o.cyc <= '0'; + wb_32_o.sel <= "0000"; + wb_32_o.we <= '0'; + end if; + when wait_st => + wb_16_o.ack <= '0'; + eth_state_wr <= idle; + when others => + eth_state_wr <= idle; + end case; + + case eth_state_rd is --read cycle + when idle => + if wb_16_i.cyc = '1' and wb_16_i.we = '0' then + core_addr <= wb_16_i.adr(31 downto 2) & "00"; + eth_state_rd <= lsb_msb; + end if; + when lsb_msb => + if wb_16_i.adr(1) = '0' then + wb_32_o.adr <= core_addr; + eth_state_rd <= lsb_read; + end if; + if wb_16_i.adr(1) = '1' then + wb_32_o.adr <= core_addr; + eth_state_rd <= msb; + end if; + when lsb_read => + wb_32_o.sel <= "1111"; + wb_32_o.we <= '0'; + wb_32_o.stb <= '1'; + wb_32_o.cyc <= '1'; + eth_state_rd <= lsb; + when lsb => + if wb_32_i.ack = '1' then + wb_32_o.sel <= "0000"; + wb_32_o.stb <= '0'; + wb_32_o.cyc <= '0'; + core_data <= wb_32_i.dat; + wb_16_o.dat <= x"0000" & wb_32_i.dat(15 downto 0); + wb_16_o.ack <= '1'; + eth_state_rd <= wait_st2; + end if; + when wait_st2 => + wb_16_o.ack <= '0'; + eth_state_rd <= idle; + when msb => + wb_16_o.ack <= '1'; + wb_16_o.dat <= core_data(31 downto 16) & x"0000"; + eth_state_rd <= wait_st2; + when others => + eth_state_rd <= idle; + end case; + end if; + end process; + +end behave; \ No newline at end of file diff --git a/misc/wishbone/src/wishbone_pkg.vhd b/misc/wishbone/src/wishbone_pkg.vhd new file mode 100644 index 0000000..c3b0d9b --- /dev/null +++ b/misc/wishbone/src/wishbone_pkg.vhd @@ -0,0 +1,52 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +package wishbone_pkg is + + type wishbone_bus_in is record + adr : std_logic_vector(31 downto 0); + sel : std_logic_vector(3 downto 0); + we : std_logic; + dat : std_logic_vector(31 downto 0); -- Note! Data written with 'we' + cyc : std_logic; + stb : std_logic; + end record; + + type wishbone_bus_out is record + dat : std_logic_vector(31 downto 0); + ack : std_logic; + end record; + + type wishbone_bus is record + insig : wishbone_bus_in; + outsig : wishbone_bus_out; + end record; + + component atomic32_access is + port ( cpu_clk : in std_logic; + areset : in std_logic; + + -- Wishbone from CPU interface + wb_16_i : in wishbone_bus_in; + wb_16_o : out wishbone_bus_out; + -- Wishbone to FPGA registers and ethernet core + wb_32_i : in wishbone_bus_out; + wb_32_o : out wishbone_bus_in); + end component; + + component eth_access_corr is + port ( cpu_clk : in std_logic; + areset : in std_logic; + + -- Wishbone from Wishbone MUX + eth_raw_o : out wishbone_bus_out; + eth_raw_i : in wishbone_bus_in; + + -- Wishbone ethernet core + eth_slave_i : in wishbone_bus_out; + eth_slave_o : out wishbone_bus_in); + end component; + + +end wishbone_pkg; -- cgit v1.1 From 8c213415fe0ddc1f9eae0b96e023eb89f89d1c47 Mon Sep 17 00:00:00 2001 From: oharboe Date: Wed, 18 Jun 2008 17:04:44 +0000 Subject: I'm also attaching another patch which removes unisim/roc dependency (it was used just to pulse the areset) and fixes paths for building the ghdl examples out of the box. I guess this is the easiest way to get zpu running on linux with minimum effort. You should check if the areset change doesn't break modelsim. It feels much simpler this way and seems to work the same, i might be missing something. --- zpu/ChangeLog | 15 +++++++++- zpu/hdl/example/sim_small_fpga_top.vhd | 10 +++---- zpu/hdl/example_ghdl/README | 42 ++++------------------------ zpu/hdl/example_ghdl/dmipssmalltrace_ghdl.sh | 22 +++++++-------- zpu/hdl/example_ghdl/dmipstrace_ghdl.sh | 21 +++++++------- zpu/hdl/example_ghdl/ghdl_import.sh | 6 ++-- zpu/hdl/example_ghdl/ghdl_options.sh | 3 +- zpu/hdl/example_ghdl/simzpu_medium_ghdl.sh | 21 +++++++------- zpu/hdl/example_medium/sim_fpga_top.vhd | 11 +++----- zpu/hdl/zpu4/src/io.vhd | 1 + 10 files changed, 63 insertions(+), 89 deletions(-) diff --git a/zpu/ChangeLog b/zpu/ChangeLog index c5ab833..72c76c0 100644 --- a/zpu/ChangeLog +++ b/zpu/ChangeLog @@ -1,4 +1,17 @@ -2008-05-06 Miguel Freitas +2008-05-18 Miguel Freitas + + * +I'm also attaching another patch which removes unisim/roc dependency +(it was used just to pulse the areset) and fixes paths for building +the ghdl examples out of the box. I guess this is the easiest way to +get zpu running on linux with minimum effort. + +You should check if the areset change doesn't break modelsim. It feels +much simpler this way and seems to work the same, i might be missing +something. + + +2008-05-16 Miguel Freitas * io.vhd: fix address comparsion and added numerous outputs during simulation to make things a bit easier diff --git a/zpu/hdl/example/sim_small_fpga_top.vhd b/zpu/hdl/example/sim_small_fpga_top.vhd index 2a7a9f5..0727bea 100644 --- a/zpu/hdl/example/sim_small_fpga_top.vhd +++ b/zpu/hdl/example/sim_small_fpga_top.vhd @@ -23,8 +23,8 @@ use ieee.numeric_std.all; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. -library UNISIM; -use UNISIM.VComponents.all; +--library UNISIM; +--use UNISIM.VComponents.all; library work; use work.zpu_config.all; @@ -38,7 +38,7 @@ architecture behave of fpga_top is signal clk : std_logic; -signal areset : std_logic; +signal areset : std_logic := '1'; component zpu_io is @@ -97,9 +97,6 @@ signal interrupt : std_logic; signal break : std_logic; begin - poweronreset: roc port map (O => areset); - - zpu: zpu_core port map ( clk => clk , @@ -188,6 +185,7 @@ begin wait for 5 ns; clk <= '1'; wait for 5 ns; + areset <= '0'; end PROCESS clock; diff --git a/zpu/hdl/example_ghdl/README b/zpu/hdl/example_ghdl/README index c537284..a098c0c 100644 --- a/zpu/hdl/example_ghdl/README +++ b/zpu/hdl/example_ghdl/README @@ -4,46 +4,16 @@ the GHDL simulator. http://ghdl.free.fr/ Compiled by Arnim Laeuger, 17-Apr-2008. - - -Prerequisites -------------- - -The RTL source code references the ROC component from Xilinx' unisim -library. If not already done, you'll have to prepare this library containing -at least the roc entity and architecture objects. - -Decide where to store this library. This could be locally in this directory or -at some central place where it can be referenced from other projects. I'd -prefer the latter option. - - $ cd - -Prepare the sources for GHDL: - $ mkdir src - $ cd src - $ ghdl --chop /vhdl/src/unisims/* - $ cd .. - -Import the sources into the library: - $ mkdir unisim_v93 - $ ghdl -i --work=unisim --workdir=unisim_v93 --std=93 -fexplicit --no-vital-checks --ieee=synopsys src/* - -Compile the required component: - $ ghdl -m --syn-binding --work=unisim --workdir=unisim_v93 --std=93 -fexplicit --no-vital-checks --ieee=synopsys roc - $ rm roc - -> not required for library - -If you require more components from the unisim library for other projects, you -can repeat the compile step later on without running through the preparation -and import steps. - +Removed ROC/unisim dependency 16-Jun-2008. Compiling the example --------------------- -Edit ghdl_options.sh and point the variable UNISIM_DIR to the location of your -newly created unisim library. +Make all shell scripts executable: + $ chmod +x *.sh + +On Linux, convert files from DOS format: + $ dos2unix *.sh You need to import the project sources once by running $ ./ghdl_import.sh diff --git a/zpu/hdl/example_ghdl/dmipssmalltrace_ghdl.sh b/zpu/hdl/example_ghdl/dmipssmalltrace_ghdl.sh index 5e43b64..b3be1a6 100644 --- a/zpu/hdl/example_ghdl/dmipssmalltrace_ghdl.sh +++ b/zpu/hdl/example_ghdl/dmipssmalltrace_ghdl.sh @@ -1,22 +1,20 @@ #!/bin/sh -UNISIM_DIR="'location of GHDL objects for unisim library'/unisim_v93" -IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work -P${UNISIM_DIR}" +IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work" MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding" if test ! -e work; then echo "Building work library..." mkdir work - ghdl -i ${IMPORT_OPTIONS} zpu_config_trace.vhd - ghdl -i ${IMPORT_OPTIONS} zpupkg.vhd - ghdl -i ${IMPORT_OPTIONS} txt_util.vhd - ghdl -i ${IMPORT_OPTIONS} sim_fpga_top.vhd - ghdl -i ${IMPORT_OPTIONS} zpu_core_small.vhd - ghdl -i ${IMPORT_OPTIONS} bram_dmips.vhd - ghdl -i ${IMPORT_OPTIONS} dram_dmips.vhd - ghdl -i ${IMPORT_OPTIONS} timer.vhd - ghdl -i ${IMPORT_OPTIONS} io.vhd - ghdl -i ${IMPORT_OPTIONS} trace.vhd + ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/zpu_config.vhd + ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpupkg.vhd + ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/txt_util.vhd + ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/sim_small_fpga_top.vhd + ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpu_core_small.vhd + ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/bram_dmips.vhd + ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/timer.vhd + ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/io.vhd + ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/trace.vhd fi echo "Compiling design..." diff --git a/zpu/hdl/example_ghdl/dmipstrace_ghdl.sh b/zpu/hdl/example_ghdl/dmipstrace_ghdl.sh index 3be392f..53474d4 100644 --- a/zpu/hdl/example_ghdl/dmipstrace_ghdl.sh +++ b/zpu/hdl/example_ghdl/dmipstrace_ghdl.sh @@ -1,21 +1,20 @@ #!/bin/sh -UNISIM_DIR="'location of GHDL objects for unisim library'/unisim_v93" -IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work -P${UNISIM_DIR}" +IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work" MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding" if test ! -e work; then echo "Building work library..." mkdir work - ghdl -i ${IMPORT_OPTIONS} zpu_config_trace.vhd - ghdl -i ${IMPORT_OPTIONS} zpupkg.vhd - ghdl -i ${IMPORT_OPTIONS} txt_util.vhd - ghdl -i ${IMPORT_OPTIONS} sim_fpga_top.vhd - ghdl -i ${IMPORT_OPTIONS} zpu_core.vhd - ghdl -i ${IMPORT_OPTIONS} dram_dmips.vhd - ghdl -i ${IMPORT_OPTIONS} timer.vhd - ghdl -i ${IMPORT_OPTIONS} io.vhd - ghdl -i ${IMPORT_OPTIONS} trace.vhd + ghdl -i ${IMPORT_OPTIONS} ../../hdl/example_medium/zpu_config_trace.vhd + ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpupkg.vhd + ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/txt_util.vhd + ghdl -i ${IMPORT_OPTIONS} ../../hdl/example_medium/sim_fpga_top.vhd + ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpu_core.vhd + ghdl -i ${IMPORT_OPTIONS} ../../hdl/example_medium/dram_dmips.vhd + ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/timer.vhd + ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/io.vhd + ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/trace.vhd fi echo "Compiling design..." diff --git a/zpu/hdl/example_ghdl/ghdl_import.sh b/zpu/hdl/example_ghdl/ghdl_import.sh index 299134b..a0ae61c 100644 --- a/zpu/hdl/example_ghdl/ghdl_import.sh +++ b/zpu/hdl/example_ghdl/ghdl_import.sh @@ -3,11 +3,11 @@ mkdir -p work ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/zpu_config.vhd -ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/zpupkg.vhd +ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpupkg.vhd ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/helloworld.vhd ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/txt_util.vhd ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/trace.vhd -ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/zpu_core_small.vhd +ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpu_core_small.vhd ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/io.vhd ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/timer.vhd -ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/sim_small_fpga_top.vhd +ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/sim_small_fpga_top.vhd diff --git a/zpu/hdl/example_ghdl/ghdl_options.sh b/zpu/hdl/example_ghdl/ghdl_options.sh index 3883ee7..aba231c 100644 --- a/zpu/hdl/example_ghdl/ghdl_options.sh +++ b/zpu/hdl/example_ghdl/ghdl_options.sh @@ -1,3 +1,2 @@ -UNISIM_DIR="'location of GHDL objects for unisim library'/unisim_v93" -IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work -P${UNISIM_DIR}" +IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work" MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding" diff --git a/zpu/hdl/example_ghdl/simzpu_medium_ghdl.sh b/zpu/hdl/example_ghdl/simzpu_medium_ghdl.sh index 7a7f3df..8ba5078 100644 --- a/zpu/hdl/example_ghdl/simzpu_medium_ghdl.sh +++ b/zpu/hdl/example_ghdl/simzpu_medium_ghdl.sh @@ -1,21 +1,20 @@ #!/bin/sh -UNISIM_DIR="'location of GHDL objects for unisim library'/unisim_v93" -IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work -P${UNISIM_DIR}" +IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work" MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding" if test ! -e work; then echo "Building work library..." mkdir work - ghdl -i ${IMPORT_OPTIONS} zpu_config_trace.vhd - ghdl -i ${IMPORT_OPTIONS} zpupkg.vhd - ghdl -i ${IMPORT_OPTIONS} txt_util.vhd - ghdl -i ${IMPORT_OPTIONS} sim_fpga_top.vhd - ghdl -i ${IMPORT_OPTIONS} zpu_core.vhd - ghdl -i ${IMPORT_OPTIONS} dram_hello.vhd - ghdl -i ${IMPORT_OPTIONS} timer.vhd - ghdl -i ${IMPORT_OPTIONS} io.vhd - ghdl -i ${IMPORT_OPTIONS} trace.vhd + ghdl -i ${IMPORT_OPTIONS} ../../hdl/example_medium/zpu_config_trace.vhd + ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpupkg.vhd + ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/txt_util.vhd + ghdl -i ${IMPORT_OPTIONS} ../../hdl/example_medium/sim_fpga_top.vhd + ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpu_core.vhd + ghdl -i ${IMPORT_OPTIONS} ../../hdl/example_medium/dram_hello.vhd + ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/timer.vhd + ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/io.vhd + ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/trace.vhd fi echo "Compiling design..." diff --git a/zpu/hdl/example_medium/sim_fpga_top.vhd b/zpu/hdl/example_medium/sim_fpga_top.vhd index 29151af..2191889 100644 --- a/zpu/hdl/example_medium/sim_fpga_top.vhd +++ b/zpu/hdl/example_medium/sim_fpga_top.vhd @@ -22,8 +22,8 @@ use IEEE.STD_LOGIC_1164.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. -library UNISIM; -use UNISIM.VComponents.all; +--library UNISIM; +--use UNISIM.VComponents.all; library work; use work.zpu_config.all; @@ -38,7 +38,7 @@ architecture behave of fpga_top is signal clk : std_logic; -signal areset : std_logic; +signal areset : std_logic := '1'; component zpu_io is @@ -94,10 +94,6 @@ signal io_reading : std_logic; signal break : std_logic; begin - poweronreset: roc port map (O => areset); - - - zpu: zpu_core port map ( clk => clk , areset => areset, @@ -182,6 +178,7 @@ begin wait for 5 ns; clk <= '1'; wait for 5 ns; + areset <= '0'; end PROCESS clock; diff --git a/zpu/hdl/zpu4/src/io.vhd b/zpu/hdl/zpu4/src/io.vhd index f71f51d..e2576e2 100644 --- a/zpu/hdl/zpu4/src/io.vhd +++ b/zpu/hdl/zpu4/src/io.vhd @@ -54,6 +54,7 @@ begin timer_we <= writeEnable and addr(12); process(areset, clk) + variable taddr : std_logic_vector(maxAddrBit downto 0); begin taddr := (others => '0'); taddr(maxAddrBit downto minAddrBit) := addr; -- cgit v1.1 From 24d353cdac17eca4851271c824f421e8ab5697f3 Mon Sep 17 00:00:00 2001 From: oharboe Date: Wed, 18 Jun 2008 17:21:36 +0000 Subject: take 2 --- zpu/hdl/zpu4/src/io.vhd | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/zpu/hdl/zpu4/src/io.vhd b/zpu/hdl/zpu4/src/io.vhd index e2576e2..a0e494a 100644 --- a/zpu/hdl/zpu4/src/io.vhd +++ b/zpu/hdl/zpu4/src/io.vhd @@ -38,6 +38,8 @@ signal serving : std_logic; file l_file : TEXT open write_mode is log_file; constant lowAddrBits: std_logic_vector(minAddrBit-1 downto 0) := (others=>'0'); +constant tx_full: std_logic := '0'; +constant rx_empty: std_logic := '1'; begin @@ -86,11 +88,11 @@ begin -- extend compare to avoid waring messages if ("1" & addr & lowAddrBits)=x"80a000c" then report "Read UART[0]"; - read(8) <= '0'; -- output fifo not full - read(9) <= '1'; -- receiver not empty + read(8) <= not tx_full; -- output fifo not full + read(9) <= not rx_empty; -- receiver not empty elsif ("1" & addr & lowAddrBits)=x"80a0010" then report "Read UART[1]"; - read(8) <= '1'; -- receiver not empty + read(8) <= not rx_empty; -- receiver not empty read(7 downto 0) <= (others => '0'); elsif addr(12)='1' then report "Read TIMER"; -- cgit v1.1 From f7c21b8d9c790fb8f59db5030e2b8f1a9fc96246 Mon Sep 17 00:00:00 2001 From: oharboe Date: Wed, 18 Jun 2008 18:20:36 +0000 Subject: Miguel Freitas log.txt and trace.txt currently on cvs were produced by interrupt.vhd. this patch will build example_ghdl with interrupt.vhd by default so user can compare results. adds a note about what user needs to edit to simulate helloworld.vhd without interrupts. --- zpu/hdl/example/sim_small_fpga_top.vhd | 2 +- zpu/hdl/example_ghdl/ghdl_import.sh | 5 ++++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/zpu/hdl/example/sim_small_fpga_top.vhd b/zpu/hdl/example/sim_small_fpga_top.vhd index 0727bea..72b2d7b 100644 --- a/zpu/hdl/example/sim_small_fpga_top.vhd +++ b/zpu/hdl/example/sim_small_fpga_top.vhd @@ -159,7 +159,7 @@ begin io_reading <= '0'; dram_ready <= '0'; - interruptcounter <= to_unsigned(32, 16); + interruptcounter <= to_unsigned(0, 16); interrupt <= '0'; elsif (clk'event and clk = '1') then diff --git a/zpu/hdl/example_ghdl/ghdl_import.sh b/zpu/hdl/example_ghdl/ghdl_import.sh index a0ae61c..b1c2713 100644 --- a/zpu/hdl/example_ghdl/ghdl_import.sh +++ b/zpu/hdl/example_ghdl/ghdl_import.sh @@ -4,7 +4,10 @@ mkdir -p work ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/zpu_config.vhd ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpupkg.vhd -ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/helloworld.vhd +ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/interrupt.vhd +# to execute helloworld comment interrupt.vhd above +# and edit sim_small_fpga_top.vhd to never assert interrupts +#ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/helloworld.vhd ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/txt_util.vhd ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/trace.vhd ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpu_core_small.vhd -- cgit v1.1 From eeff43d65567e8f0fa8634081682f0d92cee3cee Mon Sep 17 00:00:00 2001 From: oharboe Date: Wed, 18 Jun 2008 19:15:46 +0000 Subject: * zpu_config.vhd: Fixed startSp calculation (address in bytes not words) --- zpu/ChangeLog | 23 +++++++---------------- zpu/hdl/example/zpu_config.vhd | 2 +- 2 files changed, 8 insertions(+), 17 deletions(-) diff --git a/zpu/ChangeLog b/zpu/ChangeLog index 72c76c0..e489bda 100644 --- a/zpu/ChangeLog +++ b/zpu/ChangeLog @@ -1,23 +1,14 @@ -2008-05-18 Miguel Freitas - - * -I'm also attaching another patch which removes unisim/roc dependency -(it was used just to pulse the areset) and fixes paths for building -the ghdl examples out of the box. I guess this is the easiest way to -get zpu running on linux with minimum effort. - -You should check if the areset change doesn't break modelsim. It feels -much simpler this way and seems to work the same, i might be missing -something. - - -2008-05-16 Miguel Freitas - +2008-06-18 Miguel Freitas + * zpu_config.vhd: Fixed startSp calculation (address in bytes not words) +2008-06-18 Miguel Freitas + * Removed unisim/roc dependency (it was used just to pulse the areset) + and fixes paths for building the ghdl examples out of the box. + One should check if the areset change doesn't break modelsim. +2008-06-16 Miguel Freitas * io.vhd: fix address comparsion and added numerous outputs during simulation to make things a bit easier * zpu_config.vhd: do not use hardcoded startSp, allows more easily tinkering w/RAM size - 2008-05-06 Øyvind Harboe * Small ZPU now supports interrupts * added simulation example demonstrating interrupts diff --git a/zpu/hdl/example/zpu_config.vhd b/zpu/hdl/example/zpu_config.vhd index dc2b666..63f6fb9 100644 --- a/zpu/hdl/example/zpu_config.vhd +++ b/zpu/hdl/example/zpu_config.vhd @@ -18,5 +18,5 @@ package zpu_config is -- start byte address of stack. -- point to top of RAM - 2*words constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := - conv_std_logic_vector((2**(maxAddrBitBRAM+1))/4-8, maxAddrBitIncIO+1); + conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1); end zpu_config; -- cgit v1.1 From f3395f8b23ef4054d7a569b4bcf16ee651833d2a Mon Sep 17 00:00:00 2001 From: oharboe Date: Wed, 25 Jun 2008 06:09:31 +0000 Subject: * do not enable interrupts for simzpu_small.do. hello world does not have an interrupt handler, so this caused a BREAK instruction to be executed. --- zpu/ChangeLog | 4 + zpu/hdl/example/sim_small_fpga_top_noint.vhd | 178 +++++++++++++++++++++++++++ zpu/hdl/example/simzpu_small.do | 2 +- 3 files changed, 183 insertions(+), 1 deletion(-) create mode 100644 zpu/hdl/example/sim_small_fpga_top_noint.vhd diff --git a/zpu/ChangeLog b/zpu/ChangeLog index e489bda..c48b9c8 100644 --- a/zpu/ChangeLog +++ b/zpu/ChangeLog @@ -1,3 +1,7 @@ +2008-06-25 Øyvind Harboe + * do not enable interrupts for simzpu_small.do. hello world + does not have an interrupt handler, so this caused a BREAK + instruction to be executed. 2008-06-18 Miguel Freitas * zpu_config.vhd: Fixed startSp calculation (address in bytes not words) 2008-06-18 Miguel Freitas diff --git a/zpu/hdl/example/sim_small_fpga_top_noint.vhd b/zpu/hdl/example/sim_small_fpga_top_noint.vhd new file mode 100644 index 0000000..86f9a8b --- /dev/null +++ b/zpu/hdl/example/sim_small_fpga_top_noint.vhd @@ -0,0 +1,178 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 20:15:31 04/14/05 +-- Design Name: +-- Module Name: fpga_top - behave +-- Project Name: +-- Target Device: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use ieee.numeric_std.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity fpga_top is +end fpga_top; + +architecture behave of fpga_top is + + +signal clk : std_logic; + +signal areset : std_logic := '1'; + + +component zpu_io is + generic ( + log_file: string := "log.txt" + ); + port( + clk : in std_logic; + areset : in std_logic; + busy : out std_logic; + writeEnable : in std_logic; + readEnable : in std_logic; + write : in std_logic_vector(wordSize-1 downto 0); + read : out std_logic_vector(wordSize-1 downto 0); + addr : in std_logic_vector(maxAddrBit downto minAddrBit) + ); +end component; + + + + + +signal mem_busy : std_logic; +signal mem_read : std_logic_vector(wordSize-1 downto 0); +signal mem_write : std_logic_vector(wordSize-1 downto 0); +signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); +signal mem_writeEnable : std_logic; +signal mem_readEnable : std_logic; +signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + +signal enable : std_logic; + +signal dram_mem_busy : std_logic; +signal dram_mem_read : std_logic_vector(wordSize-1 downto 0); +signal dram_mem_write : std_logic_vector(wordSize-1 downto 0); +signal dram_mem_writeEnable : std_logic; +signal dram_mem_readEnable : std_logic; +signal dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + + +signal io_busy : std_logic; + +signal io_mem_read : std_logic_vector(wordSize-1 downto 0); +signal io_mem_writeEnable : std_logic; +signal io_mem_readEnable : std_logic; + + +signal dram_ready : std_logic; +signal io_ready : std_logic; +signal io_reading : std_logic; + + + +signal break : std_logic; + +begin + + zpu: zpu_core port map ( + clk => clk , + areset => areset, + enable => enable, + in_mem_busy => mem_busy, + mem_read => mem_read, + mem_write => mem_write, + out_mem_addr => mem_addr, + out_mem_writeEnable => mem_writeEnable, + out_mem_readEnable => mem_readEnable, + mem_writeMask => mem_writeMask, + interrupt => '0', + break => break); + + + ioMap: zpu_io port map ( + clk => clk, + areset => areset, + busy => io_busy, + writeEnable => io_mem_writeEnable, + readEnable => io_mem_readEnable, + write => mem_write, + read => io_mem_read, + addr => mem_addr(maxAddrBit downto minAddrBit) + ); + + dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit); + dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit); + io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit); + io_mem_readEnable <= mem_readEnable and mem_addr(ioBit); + mem_busy <= io_busy; + + + + -- Memory reads either come from IO or DRAM. We need to pick the right one. + memorycontrol: + process(dram_mem_read, dram_ready, io_ready, io_mem_read) + begin + mem_read <= (others => 'U'); + if dram_ready='1' then + mem_read <= dram_mem_read; + end if; + + if io_ready='1' then + mem_read <= (others => '0'); + mem_read <= io_mem_read; + end if; + end process; + + + + io_ready <= (io_reading or io_mem_readEnable) and not io_busy; + + memoryControlSync: + process(clk, areset) + begin + if areset = '1' then + enable <= '0'; + io_reading <= '0'; + dram_ready <= '0'; + + elsif (clk'event and clk = '1') then + enable <= '1'; + io_reading <= io_busy or io_mem_readEnable; + dram_ready<=dram_mem_readEnable; + end if; + end process; + + -- wiggle the clock @ 100MHz + clock : PROCESS + begin + clk <= '0'; + wait for 5 ns; + clk <= '1'; + wait for 5 ns; + areset <= '0'; + end PROCESS clock; + + +end behave; diff --git a/zpu/hdl/example/simzpu_small.do b/zpu/hdl/example/simzpu_small.do index 12d231b..2b64926 100644 --- a/zpu/hdl/example/simzpu_small.do +++ b/zpu/hdl/example/simzpu_small.do @@ -10,7 +10,7 @@ vlib work vcom -93 -explicit zpu_config.vhd vcom -93 -explicit ../zpu4/core/zpupkg.vhd vcom -93 -explicit ../zpu4/src/txt_util.vhd -vcom -93 -explicit sim_small_fpga_top.vhd +vcom -93 -explicit sim_small_fpga_top_noint.vhd vcom -93 -explicit ../zpu4/core/zpu_core_small.vhd vcom -93 -explicit helloworld.vhd vcom -93 -explicit ../zpu4/src/timer.vhd -- cgit v1.1 From 9d42abb28b464b9ae636540e5ff69994f21cdbf3 Mon Sep 17 00:00:00 2001 From: oharboe Date: Thu, 7 Aug 2008 11:19:42 +0000 Subject: added basic docs on emulated instructions. --- zpu/docs/zpu_arch.html | 431 ++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 427 insertions(+), 4 deletions(-) diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index 021e987..3597e82 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -358,7 +358,7 @@ end if 0000 1011 - No operation + No operation, clears IDIM flag as side effect Fix! @@ -366,18 +366,441 @@ end if - Fix! add emulated instructions! Listed in zpupkg.vhd + PUSHSPADD - 001x xxxx + 61 + + + a=sp;
        + b=popIntStack()*4;
        + pushIntStack(a+b);
        + + + Fix! + + + + + + POPPCREL + + + 57 + + + setPc(popIntStack()+getPc()); + + + Fix! + + + + + SUB + + + 49 + + + int a=popIntStack();
        + int b=popIntStack();
        + pushIntStack(b-a);
        + + + Fix! + + + + + XOR + + + 50 + + +pushIntStack(popIntStack() ^ popIntStack()); + + + Fix! + + + + + LOADB + + + 51 + + + pushIntStack(cpuReadByte(popIntStack())&0xff); + + + Fix! + + + + + STOREB + + + 52 + + + addr = popIntStack();
        + val = popIntStack();
        + cpuWriteByte(addr, val); + + + Fix! + + + + + LOADH + + + 34 + + + pushIntStack(cpuReadWord(popIntStack())); + + + Fix! + + + + + STOREH + + + 35 + + +addr = popIntStack();
        + val = popIntStack();
        + cpuWriteWord(addr, val); + + + Fix! + + + + + LESSTHAN + + + 36 + + + Signed comparison
        + a = popIntStack();
        + b = popIntStack();
        + pushIntStack((a < b) ? 1 : 0);
        + + + Fix! + + + + + LESSTHANOREQUAL + + + 37 + + + Signed comparison
        + a = popIntStack();
        + b = popIntStack();
        + pushIntStack((a <= b) ? 1 : 0); + + + Fix! + + + + + ULESSTHAN + + + 37 + + + Unsigned comparison
        + long a;//long is here 64 bit signed integer
        + long b;
        + a = ((long) popIntStack()) & INTMASK; // INTMASK is unsigned 0x00000000ffffffff
        + b = ((long) popIntStack()) & INTMASK;
        + pushIntStack((a < b) ? 1 : 0); + + + Fix! + + + + + ULESSTHANOREQUAL + + + 39 - Fix!! + Unsigned comparison
        + long a;//long is here 64 bit signed integer
        + long b;
        + a = ((long) popIntStack()) & INTMASK; // INTMASK is unsigned 0x00000000ffffffff
        + b = ((long) popIntStack()) & INTMASK;
        + pushIntStack((a <= b) ? 1 : 0); Fix! + + + EQBRANCH + + + 55 + + + int compare;
        + int target;
        + target = popIntStack() + pc;
        + compare = popIntStack();
        + if (compare == 0)
        + {
        + setPc(target);
        + } else
        + {
        + setPc(pc + 1);
        + } + + + Fix! + + + + + NEQBRANCH + + + 56 + + + int compare;
        + int target;
        + target = popIntStack() + pc;
        + compare = popIntStack();
        + if (compare != 0)
        + {
        + setPc(target);
        + } else
        + {
        + setPc(pc + 1);
        + }
        + + + Fix! + + + + + MULT + + + 41 + + + Signed 32 bit multiply
        + pushIntStack(popIntStack() * popIntStack()); + + + Fix! + + + + + DIV + + + 53 + + + Signed 32 bit integer divide.
        + a = popIntStack();
        + b = popIntStack();
        + if (b == 0)
        + {
        + // undefined
        + } + pushIntStack(a / b);
        + + + Fix! + + + + + MOD + + + 54 + + + Signed 32 bit integer modulo.
        + a = popIntStack();
        + b = popIntStack();
        + if (b == 0)
        + {
        + // undefined
        + }
        + pushIntStack(a % b);
        + + + Fix! + + + + + LSHIFTRIGHT + + + 42 + + + unsigned shift right.
        + long shift;
        + long valX;
        + int t;
        + shift = ((long) popIntStack()) & INTMASK;
        + valX = ((long) popIntStack()) & INTMASK;
        + t = (int) (valX >> (shift & 0x3f));
        + pushIntStack(t);
        + + + Fix! + + + + + ASHIFTLEFT + + + 43 + + + arithmetic(signed) shift left.
        + + long shift;
        + long valX;
        + shift = ((long) popIntStack()) & INTMASK;
        + valX = ((long) popIntStack()) & INTMASK;
        + int t = (int) (valX << (shift & 0x3f));
        + pushIntStack(t);
        + + + Fix! + + + + + ASHIFTRIGHT + + + 43 + + + arithmetic(signed) shift left.
        + long shift;
        + int valX;
        + shift = ((long) popIntStack()) & INTMASK;
        + valX = popIntStack();
        + int t = valX >> (shift & 0x3f);
        + pushIntStack(t);
        + + + + Fix! + + + + + + CALL + + + 45 + + + call procedure.
        +
        + int address = pop();
        + push(pc + 1);
        + setPc(address);
        + + + Fix! + + + + + CALLPCREL + + + 63 + + + call procedure pc relative
        +
        +int address = pop();
        + push(pc + 1);
        + setPc(address+pc); + + Fix! + + + + + + + EQ + + + 46 + + + pushIntStack((popIntStack() == popIntStack()) ? 1 : 0); + Fix! + + + + + NEQ + + + 48 + + + pushIntStack((popIntStack() != popIntStack()) ? 1 : 0); + Fix! + + + + + NEG + + + 47 + + + pushIntStack(-popIntStack()); + Fix! + + + +         -- cgit v1.1 From 10995e1545e11556e84665ff013313f5160f6161 Mon Sep 17 00:00:00 2001 From: oharboe Date: Thu, 7 Aug 2008 13:23:43 +0000 Subject: add missing defs. --- zpu/hdl/zpu4/core/zpu_config.vhd | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/zpu/hdl/zpu4/core/zpu_config.vhd b/zpu/hdl/zpu4/core/zpu_config.vhd index a13c0bf..ffc144b 100644 --- a/zpu/hdl/zpu4/core/zpu_config.vhd +++ b/zpu/hdl/zpu4/core/zpu_config.vhd @@ -1,6 +1,7 @@ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; package zpu_config is -- generate trace output or not. @@ -12,5 +13,10 @@ package zpu_config is constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64"; -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) constant maxAddrBitIncIO : integer := 15; + constant maxAddrBitBRAM : integer := 14; + -- start byte address of stack. + -- point to top of RAM - 2*words + constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := + conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1); end zpu_config; -- cgit v1.1 From 797d635849980a18a6261f3538c72abc52abea74 Mon Sep 17 00:00:00 2001 From: oharboe Date: Fri, 8 Aug 2008 12:04:17 +0000 Subject: added link. --- zpu/index.html | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/zpu/index.html b/zpu/index.html index bb5714f..161902b 100644 --- a/zpu/index.html +++ b/zpu/index.html @@ -1,9 +1,9 @@

        Getting started

        -FPGA: check out zpu/hdl, read zpu/hdl/index.html +FPGA: check out zpu/hdl, read         zpu/hdl/index.html

        -Software: check out zpu/sw, read zpu/sw/index.html +Software: check out zpu/sw, read zpu/sw/index.html

        Docs: check out zpu/docs, this is what's available as of writing. Further documentation exists in the eCosBoard 1.1 product: http://www.zylin.com/ecosboard.htm

        Other directories

        -- cgit v1.1 From d04fffa00db02f2392a962b3049780e59b87578c Mon Sep 17 00:00:00 2001 From: oharboe Date: Fri, 8 Aug 2008 12:07:08 +0000 Subject: link to zpu_arch.html --- zpu/index.html | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/zpu/index.html b/zpu/index.html index 161902b..7343ab6 100644 --- a/zpu/index.html +++ b/zpu/index.html @@ -5,7 +5,7 @@ FPGA: check out zpu/hdl, read zpu/hdl/index.html

        Software: check out zpu/sw, read zpu/sw/index.html

        -Docs: check out zpu/docs, this is what's available as of writing. Further documentation exists in the eCosBoard 1.1 product: http://www.zylin.com/ecosboard.htm +Docs: start with ZPU architecture doc

        Other directories

        You probably don't need or want to download other directories.
          -- cgit v1.1 From f9ddc2d50943be4bb9d4864cc277af99b03ade1f Mon Sep 17 00:00:00 2001 From: oharboe Date: Fri, 8 Aug 2008 12:13:24 +0000 Subject: 2008-08-08 Salvador E. Tropea * zpu/hdl/zpu4/core/histogram.perl - generate opcode histogram from HDL simulation output --- zpu/COPYING | 11 +- zpu/ChangeLog | 3 + zpu/hdl/zpu4/core/histogram.perl | 218 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 226 insertions(+), 6 deletions(-) create mode 100644 zpu/hdl/zpu4/core/histogram.perl diff --git a/zpu/COPYING b/zpu/COPYING index 9475e0f..4212a5b 100644 --- a/zpu/COPYING +++ b/zpu/COPYING @@ -1,16 +1,15 @@ About ZPU licensing: -The license for HDL implementations is BSD to be -friendly towards commercial projects, however the -architecture, documentation and tools will be GPL. This means that all -updates to the architecture must be shared, but actual +The license for HDL implementations is FreeBSD to be +friendly towards commercial projects and other open source +projects, however the architecture, documentation and tools will be GPL. + +This means that all updates to the architecture must be shared, but actual implementations(which are small and can be very project speific) can be friendly towards commercial considerations. - Patches to update files w/correct licensing info will be most appreciated! - The ZPU and all the files are per 1/1-2008 Copyright Zylin AS, i.e. Zylin is free to decide upon the BSD license for HDL implementation and GPL for architecture, tools and documentation. diff --git a/zpu/ChangeLog b/zpu/ChangeLog index c48b9c8..88bc650 100644 --- a/zpu/ChangeLog +++ b/zpu/ChangeLog @@ -1,3 +1,6 @@ +2008-08-08 Salvador E. Tropea + * zpu/hdl/zpu4/core/histogram.perl - generate opcode histogram from + HDL simulation output 2008-06-25 Øyvind Harboe * do not enable interrupts for simzpu_small.do. hello world does not have an interrupt handler, so this caused a BREAK diff --git a/zpu/hdl/zpu4/core/histogram.perl b/zpu/hdl/zpu4/core/histogram.perl new file mode 100644 index 0000000..479ee0f --- /dev/null +++ b/zpu/hdl/zpu4/core/histogram.perl @@ -0,0 +1,218 @@ +#!/usr/bin/perl +############################################################################## +# +# Copyright (c) 2008 Salvador E. Tropea +# Copyright (c) 2008 Instituto Nacional de Tecnología Industrial +# +############################################################################## +# +# Target: Any +# Language: Perl +# Interpreter used: v5.6.1/v5.8.4 +# Text editor: SETEdit 0.5.5 +# +############################################################################## +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA +# 02111-1307, USA +# +############################################################################## +# +# Description: Takes a ZPU trace and does some raw stats about opcodes +# frequency and speed. +# +############################################################################## +# +# TODO +# +# A lot ... +# + + +# 0x40-0x460 +# div y mod son especiales +@used=(); +@clks=(); + +$line=1; +$startLine=1; +#$endLine=10000; +$endLine=-1; +$lastClk=0; +$lastOpcode=-1; +while (<>) + { + if ($_=~/^(\S+) (\S+) (\S+) (\S+) (\S+) (\S+) (\S+)/) + { + $clk=hex($7); + #print "$line\n"; + if ($line>=$startLine) + { + #print $_; + $addr=hex($1); + $opcode=hex($2); + $sp=hex($3); + $a=hex($4); + $b=hex($5); + if ($addr>=0x40 and $addr<0x460) + { + @used[$opcode+0x100]++; + @clks[$lastOpcodeEmu]+=$clk-$lastClkEmu unless lastOpcodeEmu==-1; + $lastOpcodeEmu=$opcode+0x100; + $lastClkEmu=$clk; + } + else + { + @used[$opcode]++; + @clks[$lastOpcode]+=$clk-$lastClk unless $lastOpcode==-1; + #printf "%d+=%d\n",$lastOpcode,$clk-$lastClk; + $lastOpcode=$opcode; + $lastClk=$clk; + $lastOpcodeEmu=-1; + $lastClkEmu=$clk; + } + } + else + { + $lastClk=$clk; + } + last if $line==$endLine; + $line++; + } + } +@used[$lastOpcode]--; + +$id=0; +# Cluster them +AddSimple('breakpoint',0); +# 1=shiftleft, invalid +AddSimple('pushsp',2); +# 3=pushint, invalid +AddSimple('poppc',4); +AddSimple('add',5); +AddSimple('and',6); +AddSimple('or',7); +AddSimple('load',8); +AddSimple('not',9); +AddSimple('flip',10); +AddSimple('nop',11); +AddSimple('store',12); +AddSimple('popsp',13); +# 14=compare, invalid +# 15=popint, invalid +AddSimpleRange('addsp',16,31); +# 32-63 emulate +AddSimpleRange('storesp',64,95); +AddSimpleRange('loadsp',96,127); +AddSimpleRange('im',128,255); + +# 32 is the reset entry point +# 33 is the interrupt entry point +AddEmulate('loadh',34); +AddEmulate('storeh',35); +AddEmulate('lessthan',36); +AddEmulate('lessthanorequal',37); +AddEmulate('ulessthan',38); +AddEmulate('ulessthanorequal',39); +AddEmulate('swap',40); # unimplemented +AddEmulate('mult',41); +AddEmulate('lshiftright',42); +AddEmulate('ashiftleft',43); +AddEmulate('ashiftright',44); +AddEmulate('call',45); +AddEmulate('eq',46); +AddEmulate('neq',47); +AddEmulate('neg',48); +AddEmulate('sub',49); +AddEmulate('xor',50); +AddEmulate('loadb',51); +AddEmulate('storeb',52); +AddEmulate('div',53); +AddEmulate('mod',54); +AddEmulate('eqbranch',55); +AddEmulate('neqbranch',56); +AddEmulate('poppcrel',57); +AddEmulate('config',58); +AddEmulate('pushpc',59); +AddEmulate('syscall_emulate',60); # unimplemented +AddEmulate('pushspadd',61); +AddEmulate('halfmult',62); # unimplemented +AddEmulate('callpcrel',63); + +$maxID=$id; +print "Total clocks: $lastClk\n"; +print "Unsorted:\n\n"; +for ($i=0; $i<$maxID; $i++) + { + $used=@used_noemu[$i]; + $clkm=0; + $clkm=@clks_noemu[$i]/$used if $used; + printf "%-20s %8d %6.2f\n",$names[$i],$used,$clkm; + $by_times{$i}=$used; + $by_clks{$i}=@clks_noemu[$i]; + } +print "Sorted by consumed clocks:\n\n"; +foreach $key (sort { $by_clks{$b} <=> $by_clks{$a} } keys %by_clks) + { + printf "%5.2f %-20s %8d\n",$by_clks{$key}/$lastClk*100,$names[$key],$by_clks{$key}; + } + + +sub AddSimple +{ + my ($name, $opcode)=@_; + + $names[$id]=$name; + @used_noemu[$id]=@used[$opcode]; + @used_emu[$id]=@used[$opcode+0x100]; + @used_both[$id]=@used[$opcode]+@used[$opcode+0x100]; + @clks_noemu[$id]=@clks[$opcode]; + @clks_emu[$id]=@clks[$opcode+0x100]; + @clks_both[$id]=@clks[$opcode]+@clks[$opcode+0x100]; + $id++; +} + +sub AddEmulate +{ + my ($name, $opcode)=@_; + + $names[$id]=$name; + @used_noemu[$id]=@used[$opcode]; + @used_emu[$id]=@used[$opcode+0x100]; + @used_both[$id]=@used[$opcode]; + @clks_noemu[$id]=@clks[$opcode]; + @clks_emu[$id]=@clks[$opcode+0x100]; + @clks_both[$id]=@clks[$opcode]; + $id++; +} + +sub AddSimpleRange +{ + my ($name, $opStart, $opLast)=@_; + my $i; + + $names[$id]=$name; + for ($i=$opStart; $i<=$opLast; $i++) + { + @used_noemu[$id]+=@used[$i]; + @used_emu[$id]+=@used[$i+0x100]; + @used_both[$id]+=@used[$i]+@used[$i+0x100]; + @clks_noemu[$id]+=@clks[$i]; + @clks_emu[$id]+=@clks[$i+0x100]; + @clks_both[$id]+=@clks[$i]+@clks[$i+0x100]; + } + $id++; +} + + -- cgit v1.1 From 7aa2c04c916aae945be76e687c13cb40d4679788 Mon Sep 17 00:00:00 2001 From: oharboe Date: Tue, 12 Aug 2008 13:21:13 +0000 Subject: deleted reference to ic300 dating back to ZY2000 implementation. --- zpu/hdl/wishbone/zpu_system.vhd | 1 - 1 file changed, 1 deletion(-) diff --git a/zpu/hdl/wishbone/zpu_system.vhd b/zpu/hdl/wishbone/zpu_system.vhd index 6e79370..89f630d 100644 --- a/zpu/hdl/wishbone/zpu_system.vhd +++ b/zpu/hdl/wishbone/zpu_system.vhd @@ -6,7 +6,6 @@ library work; use work.wishbone_pkg.all; use work.zpupkg.all; use work.zpu_config.all; -use work.ic300pkg.all; entity zpu_system is generic( -- cgit v1.1 From eab67ae1b5d86c9c294ef057631d04a448e1727f Mon Sep 17 00:00:00 2001 From: oharboe Date: Fri, 15 Aug 2008 10:53:01 +0000 Subject: marked unused instruction opcodes as OpCode_NAx --- zpu/hdl/zpu4/core/zpupkg.vhd | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/zpu/hdl/zpu4/core/zpupkg.vhd b/zpu/hdl/zpu4/core/zpupkg.vhd index f3800b0..e8d54a3 100644 --- a/zpu/hdl/zpu4/core/zpupkg.vhd +++ b/zpu/hdl/zpu4/core/zpupkg.vhd @@ -114,9 +114,9 @@ package zpupkg is constant OpCode_Short : std_logic_vector(7 downto 4) := "0000"; constant OpCode_Break : std_logic_vector(3 downto 0) := "0000"; - constant OpCode_Shiftleft: std_logic_vector(3 downto 0) := "0001"; + constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001"; constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010"; - constant OpCode_PushInt : std_logic_vector(3 downto 0) := "0011"; + constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011"; constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100"; constant OpCode_Add : std_logic_vector(3 downto 0) := "0101"; @@ -130,8 +130,8 @@ package zpupkg is constant OpCode_Store : std_logic_vector(3 downto 0) := "1100"; constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101"; - constant OpCode_Compare : std_logic_vector(3 downto 0) := "1110"; - constant OpCode_PopInt : std_logic_vector(3 downto 0) := "1111"; + constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110"; + constant OpCode_NA : std_logic_vector(3 downto 0) := "1111"; constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6)); constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6)); -- cgit v1.1 From 17c84a1b81bd192d8a2268caaed66478e55c8e3a Mon Sep 17 00:00:00 2001 From: oharboe Date: Fri, 15 Aug 2008 19:01:14 +0000 Subject: some ideas. --- zpu/docs/zpu_arch.html | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index 3597e82..1346ecc 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -8,6 +8,7 @@
        • Jump vectors
        • Memory map
        • Interrupts +
        • Next generation ZPU

        Getting started

        @@ -1234,5 +1235,31 @@ restore them.

        See zpu/hdl/zpu4/test/interrupt/ for C code and zpu/hdl/example/simzpu_interrupt.do for simulation example. + +

        Next generation ZPU

        +Based on feedback here is a list of a tenuous "consensus" for the next generation +of the ZPU with some tentative ideas on implementation. +

        +The plan is to update zpu_core.vhd and zpu_core_small.vhd as examples/reference, +and to open up for innovation in the HDL implementation. + +

          +
        1. Reduce minimum code size footprint +
            +
          1. Modify GCC compiler to be able to emit function calls instead of instructions. +E.g instead of issuing MULT, generate function call. This reduces code size overhead +for applications that do not use MULT since the microcode does not need to be in place. +
          2. Add single entry for unknown instructions. PC and unsupported instruction is +pushed onto stack before jumping to unkonwn instruction vector. This makes it possible +to write denser microcode for missing instructions. +
          +
        2. Add floating point add and mult. FADD & FMULT. Option to generate the instructions +from the compiler. +
        3. Add some scheme to support custom instructions. +
        4. Add support to Zylin Embedded CDT for downloading fully functional ZPU +toolchain. The goal is to allow new users to write and simulate simple ZPU +programs in in less than an hour. +
        + \ No newline at end of file -- cgit v1.1 From fdc8e712265a1cc083ba51146a75cf15d6718feb Mon Sep 17 00:00:00 2001 From: oharboe Date: Fri, 15 Aug 2008 20:04:54 +0000 Subject: tips for rolling your own ZPU --- zpu/docs/zpu_arch.html | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index 1346ecc..e09b915 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -5,6 +5,7 @@
      1. Getting started
      2. Introduction
      3. Instruction set +
      4. Implementing your own ZPU
      5. Jump vectors
      6. Memory map
      7. Interrupts @@ -804,6 +805,34 @@ int address = pop();
        + +

        Implementing your own ZPU

        +One of the neat things about the ZPU is that the instruction set and architecture +is very small and it is easy to implement a ZPU from scratch or modify the +existing ZPU implementations. +

        +Implementing a ZPU can be done without understanding the toolchain in +detail, i.e. using exclusively HDL skills and only a rudimentary +understanding of standard GCC/GDB usage is sufficient. +

        +A few tips: +

          +
        • Run zpu_core.vhd or zpu_core_small.vhd and generate an instruction trace +from ModelSim or similar. To check that you own implementation is correctly +implemented, verify that the instruction trace for the new and old +ZPU implementations match. This gives you a simple way to do regression +tests as you develop your ZPU. +
        • To improve performance, you can add more instructions. The EMULATE instructions +are optional in HDL since they will be emulated in software if they are not +implemented in HDL. This allows you to run the ZPU executables unmodified +regardless of which EMULATE instructions you implement. +
        • Run the DMIPS test to measure your overall performance +
        • Run the histogram.perl script on the instruction trace to generate +histograms of the instructions. Profiling is essential to making +the right choices w.r.t. optimisation for your application. +
        + +

        Vectors

        -- cgit v1.1 From 5d329cc628e4174874382547397149e414ec0ad8 Mon Sep 17 00:00:00 2001 From: oharboe Date: Fri, 15 Aug 2008 20:11:36 +0000 Subject: added FreeBSD license. Finally. --- zpu/hdl/example/bram_dmips.vhd | 34 ++++++++++++++++++++ zpu/hdl/example/helloworld.vhd | 34 ++++++++++++++++++++ zpu/hdl/example/interrupt.vhd | 34 ++++++++++++++++++++ zpu/hdl/example/sim_small_fpga_top.vhd | 47 ++++++++++++++++++---------- zpu/hdl/example/sim_small_fpga_top_noint.vhd | 47 ++++++++++++++++++---------- zpu/hdl/example/zpu_config.vhd | 34 ++++++++++++++++++++ zpu/hdl/wishbone/wishbone_pkg.vhd | 34 ++++++++++++++++++++ zpu/hdl/wishbone/zpu_system.vhd | 34 ++++++++++++++++++++ zpu/hdl/wishbone/zpu_wb_bridge.vhd | 34 ++++++++++++++++++++ zpu/hdl/zpu4/core/zpu_config.vhd | 35 +++++++++++++++++++++ zpu/hdl/zpu4/core/zpu_core.vhd | 36 +++++++++++++++++++-- zpu/hdl/zpu4/core/zpu_core_small.vhd | 35 +++++++++++++++++++-- zpu/hdl/zpu4/core/zpupkg.vhd | 34 ++++++++++++++++++++ zpu/hdl/zpu4/src/trace.vhd | 34 ++++++++++++++++++++ zpu/hdl/zpu4/src/txt_util.vhd | 34 ++++++++++++++++++++ 15 files changed, 503 insertions(+), 37 deletions(-) diff --git a/zpu/hdl/example/bram_dmips.vhd b/zpu/hdl/example/bram_dmips.vhd index 1d62d21..53d9121 100644 --- a/zpu/hdl/example/bram_dmips.vhd +++ b/zpu/hdl/example/bram_dmips.vhd @@ -1,3 +1,37 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; diff --git a/zpu/hdl/example/helloworld.vhd b/zpu/hdl/example/helloworld.vhd index f9383fd..a11bbb7 100644 --- a/zpu/hdl/example/helloworld.vhd +++ b/zpu/hdl/example/helloworld.vhd @@ -1,3 +1,37 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; diff --git a/zpu/hdl/example/interrupt.vhd b/zpu/hdl/example/interrupt.vhd index 821e29a..ededf85 100644 --- a/zpu/hdl/example/interrupt.vhd +++ b/zpu/hdl/example/interrupt.vhd @@ -1,3 +1,37 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; diff --git a/zpu/hdl/example/sim_small_fpga_top.vhd b/zpu/hdl/example/sim_small_fpga_top.vhd index 72b2d7b..f36a285 100644 --- a/zpu/hdl/example/sim_small_fpga_top.vhd +++ b/zpu/hdl/example/sim_small_fpga_top.vhd @@ -1,22 +1,37 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: +-- ZPU -- --- Create Date: 20:15:31 04/14/05 --- Design Name: --- Module Name: fpga_top - behave --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: -- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. -- --------------------------------------------------------------------------------- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project.-------------------------------------------------------------------------------- + library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; diff --git a/zpu/hdl/example/sim_small_fpga_top_noint.vhd b/zpu/hdl/example/sim_small_fpga_top_noint.vhd index 86f9a8b..b342d26 100644 --- a/zpu/hdl/example/sim_small_fpga_top_noint.vhd +++ b/zpu/hdl/example/sim_small_fpga_top_noint.vhd @@ -1,22 +1,37 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: +-- ZPU -- --- Create Date: 20:15:31 04/14/05 --- Design Name: --- Module Name: fpga_top - behave --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: -- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. -- --------------------------------------------------------------------------------- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; diff --git a/zpu/hdl/example/zpu_config.vhd b/zpu/hdl/example/zpu_config.vhd index 63f6fb9..c4c09b5 100644 --- a/zpu/hdl/example/zpu_config.vhd +++ b/zpu/hdl/example/zpu_config.vhd @@ -1,3 +1,37 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; diff --git a/zpu/hdl/wishbone/wishbone_pkg.vhd b/zpu/hdl/wishbone/wishbone_pkg.vhd index c3b0d9b..97240de 100644 --- a/zpu/hdl/wishbone/wishbone_pkg.vhd +++ b/zpu/hdl/wishbone/wishbone_pkg.vhd @@ -1,3 +1,37 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_UNSIGNED.ALL; diff --git a/zpu/hdl/wishbone/zpu_system.vhd b/zpu/hdl/wishbone/zpu_system.vhd index 89f630d..5b95a80 100644 --- a/zpu/hdl/wishbone/zpu_system.vhd +++ b/zpu/hdl/wishbone/zpu_system.vhd @@ -1,3 +1,37 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_UNSIGNED.all; diff --git a/zpu/hdl/wishbone/zpu_wb_bridge.vhd b/zpu/hdl/wishbone/zpu_wb_bridge.vhd index 4182f7a..226d839 100644 --- a/zpu/hdl/wishbone/zpu_wb_bridge.vhd +++ b/zpu/hdl/wishbone/zpu_wb_bridge.vhd @@ -1,3 +1,37 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; diff --git a/zpu/hdl/zpu4/core/zpu_config.vhd b/zpu/hdl/zpu4/core/zpu_config.vhd index ffc144b..4fecf01 100644 --- a/zpu/hdl/zpu4/core/zpu_config.vhd +++ b/zpu/hdl/zpu4/core/zpu_config.vhd @@ -1,3 +1,38 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + + library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; diff --git a/zpu/hdl/zpu4/core/zpu_core.vhd b/zpu/hdl/zpu4/core/zpu_core.vhd index 37fa2d1..012fe1b 100644 --- a/zpu/hdl/zpu4/core/zpu_core.vhd +++ b/zpu/hdl/zpu4/core/zpu_core.vhd @@ -1,6 +1,36 @@ - --- Company: ZPU4 generic memory interface CPU --- Engineer: Øyvind Harboe +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. library IEEE; use IEEE.STD_LOGIC_1164.ALL; diff --git a/zpu/hdl/zpu4/core/zpu_core_small.vhd b/zpu/hdl/zpu4/core/zpu_core_small.vhd index 03526bd..69bbe1a 100644 --- a/zpu/hdl/zpu4/core/zpu_core_small.vhd +++ b/zpu/hdl/zpu4/core/zpu_core_small.vhd @@ -1,5 +1,36 @@ --- Company: ZPU3 --- Engineer: Øyvind Harboe +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. library IEEE; use IEEE.STD_LOGIC_1164.ALL; diff --git a/zpu/hdl/zpu4/core/zpupkg.vhd b/zpu/hdl/zpu4/core/zpupkg.vhd index e8d54a3..59d26e5 100644 --- a/zpu/hdl/zpu4/core/zpupkg.vhd +++ b/zpu/hdl/zpu4/core/zpupkg.vhd @@ -1,3 +1,37 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + library IEEE; use IEEE.STD_LOGIC_1164.all; use ieee.numeric_std.all; diff --git a/zpu/hdl/zpu4/src/trace.vhd b/zpu/hdl/zpu4/src/trace.vhd index e687aaf..2413970 100644 --- a/zpu/hdl/zpu4/src/trace.vhd +++ b/zpu/hdl/zpu4/src/trace.vhd @@ -1,3 +1,37 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; diff --git a/zpu/hdl/zpu4/src/txt_util.vhd b/zpu/hdl/zpu4/src/txt_util.vhd index d3bf01a..3d5297a 100644 --- a/zpu/hdl/zpu4/src/txt_util.vhd +++ b/zpu/hdl/zpu4/src/txt_util.vhd @@ -1,3 +1,37 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + library ieee; use ieee.std_logic_1164.all; use std.textio.all; -- cgit v1.1 From 0315a8cc7a7f58a8c539aa0e73fe6142ea44def0 Mon Sep 17 00:00:00 2001 From: oharboe Date: Fri, 15 Aug 2008 20:22:17 +0000 Subject: a few words about zpu_core.vhd and zpu_core_small.vhd --- zpu/docs/zpu_arch.html | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index e09b915..312bdb6 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -9,6 +9,8 @@
      8. Jump vectors
      9. Memory map
      10. Interrupts +
      11. About zpu_core_small.vhd +
      12. About zpu_core.vhd
      13. Next generation ZPU @@ -1264,6 +1266,34 @@ restore them.

        See zpu/hdl/zpu4/test/interrupt/ for C code and zpu/hdl/example/simzpu_interrupt.do for simulation example. + +

        About zpu_core_small.vhd

        +The small ZPU implements the minimum instruction set. It is optimized for size and simplicity +serving as a reference in both regards. +

        +It uses a BRAM (dual port RAM w/read/write to both ports) as data & code storage and +is implemented as a simple state machine. +

        +Essentially it has three states: +

          +
        1. Fetch - starts fetch of next instruction +
        2. FetchNext - sets up operands for execute cycle +
        3. Decode - decodes instruction +
        4. Execute - well.. executes instruction +
        +The tricky bit is that there is a tiny bit of interleaving of +states since the BRAM takes a cycle to perform a fetch/store. The above is the +normal states the ZPU cycles through unless memory fetch, jumps, etc. take +place. +         +

        About zpu_core.vhd

        +The zpu_core.vhd has a single port memory interface. All data, code and IO is +accessed through this memory interface. +

        +It performs better(despite having less memory bandwidth than zpu_core_small.vhd) +since it implements many more instructions. + +

        Next generation ZPU

        Based on feedback here is a list of a tenuous "consensus" for the next generation -- cgit v1.1 From cae9e8c62d8f3fd3900bd90148c20c90730324eb Mon Sep 17 00:00:00 2001 From: oharboe Date: Fri, 15 Aug 2008 20:32:50 +0000 Subject: some more docs. --- zpu/docs/zpu_arch.html | 133 ++++++++++++++++++++++++++----------------------- 1 file changed, 72 insertions(+), 61 deletions(-) diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index 312bdb6..825f0d2 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -136,7 +136,6 @@ end if Pop value off stack and store it in the SP+xxxxx*4 memory location, where xxxxx is a positive integer.
        14. @@ -150,7 +149,7 @@ end if Push value of memory location SP+xxxxx*4, where xxxxx is a positive integer, onto stack. @@ -164,7 +163,7 @@ end if Add value of memory location SP+xxxx*4 to value on top of stack. @@ -175,10 +174,16 @@ end if 001x xxxx @@ -192,7 +197,7 @@ end if Pushes program counter onto the stack. @@ -206,21 +211,7 @@ end if Pops address off stack and sets PC - - - - - - @@ -233,10 +224,13 @@ end if @@ -249,10 +243,10 @@ end if @@ -266,7 +260,7 @@ end if Pushes stack pointer. @@ -277,10 +271,10 @@ end if 0000 1101 @@ -294,7 +288,7 @@ end if Pops two values on stack adds them and pushes the result @@ -308,7 +302,7 @@ end if Pops two values off the stack and does a bitwise-and & pushes the result onto the stack @@ -322,7 +316,7 @@ end if Pops two integers, does a bitwise or and pushes result @@ -337,7 +331,7 @@ end if @@ -348,10 +342,12 @@ end if 0000 1010 @@ -362,10 +358,11 @@ end if 0000 1011 @@ -381,7 +378,7 @@ end if pushIntStack(a+b);
         @@ -396,7 +393,7 @@ end if setPc(popIntStack()+getPc()); @@ -412,7 +409,7 @@ end if pushIntStack(b-a);
         @@ -426,7 +423,7 @@ end if pushIntStack(popIntStack() ^ popIntStack()); @@ -437,10 +434,13 @@ pushIntStack(popIntStack() ^ popIntStack()); 51 @@ -451,12 +451,15 @@ pushIntStack(popIntStack() ^ popIntStack()); 52 @@ -467,10 +470,15 @@ pushIntStack(popIntStack() ^ popIntStack()); 34 @@ -481,12 +489,15 @@ pushIntStack(popIntStack() ^ popIntStack()); 35 @@ -503,7 +514,7 @@ addr = popIntStack();
        pushIntStack((a < b) ? 1 : 0);
         @@ -520,7 +531,7 @@ addr = popIntStack();
        pushIntStack((a <= b) ? 1 : 0);         @@ -539,7 +550,7 @@ addr = popIntStack();
        pushIntStack((a < b) ? 1 : 0);         @@ -558,7 +569,7 @@ addr = popIntStack();
        pushIntStack((a <= b) ? 1 : 0);         @@ -582,7 +593,7 @@ addr = popIntStack();
        }         @@ -606,7 +617,7 @@ addr = popIntStack();
        }
         @@ -621,7 +632,7 @@ addr = popIntStack();
        pushIntStack(popIntStack() * popIntStack());         @@ -642,7 +653,7 @@ addr = popIntStack();
        pushIntStack(a / b);
         @@ -663,7 +674,7 @@ addr = popIntStack();
        pushIntStack(a % b);
        @@ -684,7 +695,7 @@ addr = popIntStack();
        pushIntStack(t);
         @@ -705,7 +716,7 @@ addr = popIntStack();
        pushIntStack(t);
         @@ -726,7 +737,7 @@ addr = popIntStack();
         @@ -745,7 +756,7 @@ addr = popIntStack();
        setPc(address);
        @@ -762,7 +773,7 @@ int address = pop();
        push(pc + 1);
        setPc(address+pc);         @@ -776,7 +787,7 @@ int address = pop();
         @@ -788,7 +799,7 @@ int address = pop();
         @@ -800,7 +811,7 @@ int address = pop();
         -- cgit v1.1 From 701ad73b88cbd8014fc0f4de10b7e77b3bda87a2 Mon Sep 17 00:00:00 2001 From: oharboe Date: Fri, 15 Aug 2008 20:37:55 +0000 Subject: pdf versions --- zpu/docs/presentations/zpu.pdf | Bin 0 -> 112765 bytes zpu/docs/presentations/zpudemo.pdf | Bin 0 -> 254156 bytes 2 files changed, 0 insertions(+), 0 deletions(-) create mode 100644 zpu/docs/presentations/zpu.pdf create mode 100644 zpu/docs/presentations/zpudemo.pdf diff --git a/zpu/docs/presentations/zpu.pdf b/zpu/docs/presentations/zpu.pdf new file mode 100644 index 0000000..4bdd25b Binary files /dev/null and b/zpu/docs/presentations/zpu.pdf differ diff --git a/zpu/docs/presentations/zpudemo.pdf b/zpu/docs/presentations/zpudemo.pdf new file mode 100644 index 0000000..067cc78 Binary files /dev/null and b/zpu/docs/presentations/zpudemo.pdf differ -- cgit v1.1 From b535dbe12ad4e09256f4bbdd98054138e4b6fff5 Mon Sep 17 00:00:00 2001 From: oharboe Date: Sat, 16 Aug 2008 08:08:55 +0000 Subject: wip --- zpu/docs/zpu_arch.html | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index 825f0d2..ce24bdd 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -1322,14 +1322,34 @@ for applications that do not use MULT since the microcode does not need to be in
      14. Add single entry for unknown instructions. PC and unsupported instruction is pushed onto stack before jumping to unkonwn instruction vector. This makes it possible to write denser microcode for missing instructions. +
      15. Single entry for *all* unknown instructions does not limit emulation to the +EMULATE instructions today, but instructions such as OR, LOADSP, STORESP, ADDSP, +etc. can also be emulated. This opens up for further reduction in logic usage. +
      16. The single entry for all unknown instructions will make it easier to +write a compact custom crt0.s to fit an instruction subset. +
      17. The interrupt is basically an unknown instruction that is injected into +the execution stream.
      18. Add floating point add and mult. FADD & FMULT. Option to generate the instructions from the compiler. -
      19. Add some scheme to support custom instructions. +
      20. Add GCC support for seperate code/data bus. This may be as "simple" as +writing a custom linker script for the current GCC compiler. +
      21. Add some scheme to support custom instructions. Can this be combined with +single entry point for unknown instructions?
      22. Add support to Zylin Embedded CDT for downloading fully functional ZPU toolchain. The goal is to allow new users to write and simulate simple ZPU programs in in less than an hour. - +

        Next generation ZPU HDL work

        +
          +
        1. Incorporate feedback on FPGA tricks to reduce memory usage: do not +use asynchronous reset?, use BRAMs in synchronous mode to reduce +complexity of state machine?, seperate code/data bus? Reduce +instruction set further. Goal: <300 LUT's for 32 bit ZPU +
        2. Will someone be willing to contribute a heavily pipelined ZPU? +For this to make sense, the performance must hit 20 DMIPS w/DRAM & cache. +This ZPU could run a TCP/IP stack with relevant performance to compete +with stripped down ARM7 type systems. +
        \ No newline at end of file -- cgit v1.1 From 3c919f795b78bacdb9b3b7396ac5761f7457224a Mon Sep 17 00:00:00 2001 From: oharboe Date: Mon, 18 Aug 2008 07:25:24 +0000 Subject: wip --- zpu/docs/zpu_arch.html | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index ce24bdd..ccbd0df 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -1316,19 +1316,20 @@ and to open up for innovation in the HDL implementation.
        1. Reduce minimum code size footprint
            -
          1. Modify GCC compiler to be able to emit function calls instead of instructions. -E.g instead of issuing MULT, generate function call. This reduces code size overhead -for applications that do not use MULT since the microcode does not need to be in place.
          2. Add single entry for unknown instructions. PC and unsupported instruction is pushed onto stack before jumping to unkonwn instruction vector. This makes it possible -to write denser microcode for missing instructions. +to write denser microcode for missing instructions. For emulated opcodes that are +not in use, the microcode can more easily be disabled. Determining +that e.g. MULT is not used, can be a bit tricky, but disabling it is easy.
          3. Single entry for *all* unknown instructions does not limit emulation to the EMULATE instructions today, but instructions such as OR, LOADSP, STORESP, ADDSP, etc. can also be emulated. This opens up for further reduction in logic usage.
          4. The single entry for all unknown instructions will make it easier to -write a compact custom crt0.s to fit an instruction subset. +write a compact custom crt0.s to fit an instruction subset.
          5. The interrupt is basically an unknown instruction that is injected into the execution stream. +
          6. Possibly modify the java simulator to support the single entry for unknown +instructions.
        2. Add floating point add and mult. FADD & FMULT. Option to generate the instructions from the compiler. @@ -1339,6 +1340,10 @@ single entry point for unknown instructions?
        3. Add support to Zylin Embedded CDT for downloading fully functional ZPU toolchain. The goal is to allow new users to write and simulate simple ZPU programs in in less than an hour. +
        4. Strip away unused instructions from GCC and add options to GCC for not +emitting more advanced instructions. This will e.g. convert MULT/DIV into +function calls to libgcc and thus make it easier to determine that +microcode is not needed.

        Next generation ZPU HDL work

          -- cgit v1.1 From 431a1bf775d468bcd788c3dd716b97cc0fca1f34 Mon Sep 17 00:00:00 2001 From: oharboe Date: Mon, 18 Aug 2008 12:00:34 +0000 Subject: * duplicated crt0.s and some other stuff from libgloss into sw/startup. This makes it easier to tinker w/startup code. --- zpu/ChangeLog | 3 + zpu/docs/zpu_arch.html | 16 +- zpu/sw/startup/crt0.S | 957 ++++++++++++++++++++++++++++++++++++++++++++++++ zpu/sw/startup/crt_io.c | 91 +++++ zpu/sw/startup/time.c | 32 ++ 5 files changed, 1098 insertions(+), 1 deletion(-) create mode 100644 zpu/sw/startup/crt0.S create mode 100644 zpu/sw/startup/crt_io.c create mode 100644 zpu/sw/startup/time.c diff --git a/zpu/ChangeLog b/zpu/ChangeLog index 88bc650..02adb2c 100644 --- a/zpu/ChangeLog +++ b/zpu/ChangeLog @@ -1,3 +1,6 @@ +2008-08-18 Øyvind Harboe + * duplicated crt0.s and some other stuff from libgloss into + sw/startup. This makes it easier to tinker w/startup code. 2008-08-08 Salvador E. Tropea * zpu/hdl/zpu4/core/histogram.perl - generate opcode histogram from HDL simulation output diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index ccbd0df..d8d982d 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -5,6 +5,7 @@
        1. Getting started
        2. Introduction
        3. Instruction set +
        4. Custom startup code (aka crt0.s)
        5. Implementing your own ZPU
        6. Jump vectors
        7. Memory map @@ -817,7 +818,20 @@ int address = pop();
        23. - Fix!
        - Fix! +
        - Fix! +
        - Push PC to stack and set PC to 0x0+xxxxx*32. This is used to emulate opcodes. See zpupgk.vhd for list of emulate opcode values used. zpu_core.vhd contains reference implementations of these instructions rather than letting the ZPU execute the EMULATE instruction + Push PC to stack and set PC to 0x0+xxxxx*32. This is used to emulate opcodes. See + zpupgk.vhd for list of emulate opcode values used. zpu_core.vhd contains + reference implementations of these instructions rather than letting the ZPU execute the EMULATE instruction +

        + One way to improve performance of the ZPU is to implement some of + the EMULATE instructions. +

        		- Fix! +
        - Fix! +
        - Fix! -
        - LOAD - - 0000 1000 - - Pops address stored on stack and loads the value of that address onto stack. - - Fix! +
        Pops address stored on stack and loads the value of that address onto stack.

        - Bit 0 and 1 of address are always 0. + Bit 0 and 1 of address are always treated as 0(i.e. ignored) by + the HDL implementations and C code is guaranteed by the programming + model never to use 32 bit LOAD on non-32 bit aligned addresses(i.e. + if a program does this, then it has a bug).

        		- Fix! +
        Pops address, then value from stack and stores the value into the memory location of the address.

        - Bit 0 and 1 of address are always 0 + Bit 0 and 1 of address are always treated as 0

        		- Fix! +
        - Fix! +
        - Used to allocate/deallocate space on stack for variables or when changing threads. + Pops value off top of stack and sets SP to that value. Used to allocate/deallocate space on stack for variables or when changing threads. - Fix! +
        - Fix! +
        - Fix! +
        - Fix! +
        - Fix! +
        - Reverses the bit order of the value on the stack, i.e. abc->cba, 100->001, 110->011, etc. + Reverses the bit order of the value on the stack, i.e. abc->cba, 100->001, 110->011, etc. +

        + The raison d'etre for this instruction is mainly to emulate other instructions.

        		- Fix! +
        - No operation, clears IDIM flag as side effect + No operation, clears IDIM flag as side effect, i.e. used between two + consequtive IM instructions to push two values onto the stack. - Fix! +
        - Fix! +
        - Fix! +
        - Fix! +
        - Fix! +
        + 8 bit load instruction. Really only here for compatibility with + C programming model. Also it has a big impact on DMIPS test. +

        pushIntStack(cpuReadByte(popIntStack())&0xff);

        		- Fix! +
        + 8 bit store instruction. Really only here for compatibility with + C programming model. Also it has a big impact on DMIPS test. +

        addr = popIntStack();
        val = popIntStack();
        cpuWriteByte(addr, val);

        		- Fix! +
        + + 16 bit load instruction. Really only here for compatibility with + C programming model. +

        + pushIntStack(cpuReadWord(popIntStack()));

        		- Fix! +
        + 16 bit store instruction. Really only here for compatibility with + C programming model. +

        addr = popIntStack();
        val = popIntStack();
        cpuWriteWord(addr, val);

        		- Fix! +
        - Fix! +
        - Fix! +
        - Fix! +
        - Fix! +
        - Fix! +
        - Fix! +
        - Fix! +
        - Fix! +
        - Fix! +
        - Fix! +
        - Fix! +
        - Fix! +
        - Fix! +
        - Fix! +
        pushIntStack((popIntStack() == popIntStack()) ? 1 : 0); - Fix! +
        pushIntStack((popIntStack() != popIntStack()) ? 1 : 0); - Fix! +
        pushIntStack(-popIntStack()); - Fix! +
        - + +

        Custom startup code (aka crt0.s)

        +To minimize the size of an application, one important trick is to +strip down the startup code. The startup code contains emulation +of instructions that may never be used by a particular application. +

        +The startup code is found in the GCC source code under gcc/libgloss/zpu, +but to make the startup code more available, it has been duplicated +into zpu/sw/startup +

        +To minimize startup size, see codesize +demo. This is pretty standard GCC stuff and simple enough once you've +been over it a couple of times. +

        Implementing your own ZPU

        One of the neat things about the ZPU is that the instruction set and architecture diff --git a/zpu/sw/startup/crt0.S b/zpu/sw/startup/crt0.S new file mode 100644 index 0000000..00870c4 --- /dev/null +++ b/zpu/sw/startup/crt0.S @@ -0,0 +1,957 @@ +/* Startup code for ZPU + Copyright (C) 2005 Free Software Foundation, Inc. + +This file is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +In addition to the permissions in the GNU General Public License, the +Free Software Foundation gives you unlimited permission to link the +compiled version of this file with other programs, and to distribute +those programs without any restriction coming from the use of this +file. (The General Public License restrictions do apply in other +respects; for example, they cover modification of the file, and +distribution when not linked into another program.) + +This file is distributed in the hope that it will be useful, but +WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + .file "crt0.S" + + + + +; .section ".fixed_vectors","ax" +; KLUDGE!!! we remove the executable bit to avoid relaxation + .section ".fixed_vectors","a" + +; DANGER!!!! +; we need to align these code sections to 32 bytes, which +; means we must not use any assembler instructions that are relaxed +; at linker time +; DANGER!!!! + + .macro fixedim value + im \value + .endm + + .macro jsr address + + im 0 ; save R0 + load + im 4 ; save R1 + load + im 8 ; save R2 + load + + fixedim \address + call + + im 8 + store ; restore R2 + im 4 + store ; restore R1 + im 0 + store ; restore R0 + .endm + + + .macro jmp address + fixedim \address + poppc + .endm + + + .macro fast_neg + not + im 1 + add + .endm + + .macro cimpl funcname + ; save R0 + im 0 + load + + ; save R1 + im 4 + load + + ; save R2 + im 8 + load + + loadsp 20 + loadsp 20 + + fixedim \funcname + call + + ; destroy arguments on stack + storesp 0 + storesp 0 + + im 0 + load + + ; poke the result into the right slot + storesp 24 + + ; restore R2 + im 8 + store + + ; restore R1 + im 4 + store + + ; restore r0 + im 0 + store + + + storesp 4 + poppc + .endm + + .macro mult1bit + ; create mask of lowest bit in A + loadsp 8 ; A + im 1 + and + im -1 + add + not + loadsp 8 ; B + and + add ; accumulate in C + + ; shift B left 1 bit + loadsp 4 ; B + addsp 0 + storesp 8 ; B + + ; shift A right 1 bit + loadsp 8 ; A + flip + addsp 0 + flip + storesp 12 ; A + .endm + + + +/* vectors */ + .balign 32,0 +# offset 0x0000 0000 + .globl _start +_start: + ; intSp must be 0 when we jump to _premain + + im ZPU_ID + loadsp 0 + im _cpu_config + store + config + jmp _premain + + + + .balign 32,0 +# offset 0x0000 0020 + .globl _zpu_interrupt_vector +_zpu_interrupt_vector: + jsr _zpu_interrupt + poppc + + +/* instruction emulation code */ + +# opcode 34 +# offset 0x0000 0040 + .balign 32,0 +_loadh: + loadsp 4 + ; by not masking out bit 0, we cause a memory access error + ; on unaligned access + im ~0x2 + and + load + + ; mult 8 + loadsp 8 + im 3 + and + fast_neg + im 2 + add + im 3 + ashiftleft + ; shift right addr&3 * 8 + lshiftright + im 0xffff + and + storesp 8 + + poppc + +# opcode 35 +# offset 0x0000 0060 + .balign 32,0 +_storeh: + loadsp 4 + ; by not masking out bit 0, we cause a memory access error + ; on unaligned access + im ~0x2 + and + load + + ; mask + im 0xffff + loadsp 12 + im 3 + and + fast_neg + im 2 + add + im 3 + ashiftleft + ashiftleft + not + + and + + loadsp 12 + im 0xffff + + nop + + fixedim _storehtail + poppc + + +# opcode 36 +# offset 0x0000 0080 + .balign 32,0 +_lessthan: + loadsp 8 + fast_neg + loadsp 8 + add + + ; DANGER!!!! + ; 0x80000000 will overflow when negated, so we need to mask + ; the result above with the compare positive to negative + ; number case + loadsp 12 + loadsp 12 + not + and + not + and + + + ; handle case where we are comparing a negative number + ; and positve number. This can underflow. E.g. consider 0x8000000 < 0x1000 + loadsp 12 + not + loadsp 12 + and + + or + + + + flip + im 1 + and + + + storesp 12 + storesp 4 + poppc + + +# opcode 37 +# offset 0x0000 00a0 + .balign 32,0 +_lessthanorequal: + loadsp 8 + loadsp 8 + lessthan + loadsp 12 + loadsp 12 + eq + or + + storesp 12 + storesp 4 + poppc + + +# opcode 38 +# offset 0x0000 00c0 + .balign 32,0 +_ulessthan: + ; fish up arguments + loadsp 4 + loadsp 12 + + /* low: -1 if low bit dif is negative 0 otherwise: neg (not x&1 and (y&1)) + x&1 y&1 neg (not x&1 and (y&1)) + 1 1 0 + 1 0 0 + 0 1 -1 + 0 0 0 + + */ + loadsp 4 + not + loadsp 4 + and + im 1 + and + neg + + + /* high: upper 31-bit diff is only wrong when diff is 0 and low=-1 + high=x>>1 - y>>1 + low + + extremes + + 0000 - 1111: + low= neg(not 0 and 1) = 1111 (-1) + high=000+ neg(111) +low = 000 + 1001 + low = 1000 + OK + + 1111 - 0000 + low=neg(not 1 and 0) = 0 + high=111+neg(000) + low = 0111 + OK + + + */ + loadsp 8 + + flip + addsp 0 + flip + + loadsp 8 + + flip + addsp 0 + flip + + sub + + ; if they are equal, then the last bit decides... + add + + /* test if negative: result = flip(diff) & 1 */ + flip + im 1 + and + + ; destroy a&b which are on stack + storesp 4 + storesp 4 + + storesp 12 + storesp 4 + poppc + +# opcode 39 +# offset 0x0000 00e0 + .balign 32,0 +_ulessthanorequal: + loadsp 8 + loadsp 8 + ulessthan + loadsp 12 + loadsp 12 + eq + or + + storesp 12 + storesp 4 + poppc + + +# opcode 40 +# offset 0x0000 0100 + .balign 32,0 + .globl _swap +_swap: + breakpoint ; tbd + +# opcode 41 +# offset 0x0000 0120 + .balign 32,0 +_slowmult: + im _slowmultImpl + poppc + +# opcode 42 +# offset 0x0000 0140 + .balign 32,0 +_lshiftright: + loadsp 8 + flip + + loadsp 8 + ashiftleft + flip + + storesp 12 + storesp 4 + + poppc + + +# opcode 43 +# offset 0x0000 0160 + .balign 32,0 +_ashiftleft: + loadsp 8 + + loadsp 8 + im 0x1f + and + fast_neg + im _ashiftleftEnd + add + poppc + + + +# opcode 44 +# offset 0x0000 0180 + .balign 32,0 +_ashiftright: + loadsp 8 + loadsp 8 + lshiftright + + ; handle signed value + im -1 + loadsp 12 + im 0x1f + and + lshiftright + not ; now we have an integer on the stack with the signed + ; bits in the right position + + ; mask these bits with the signed bit. + loadsp 16 + not + flip + im 1 + and + im -1 + add + + and + + ; stuff in the signed bits... + or + + ; store result into correct stack slot + storesp 12 + + ; move up return value + storesp 4 + poppc + +# opcode 45 +# offset 0x0000 01a0 + .balign 32,0 +_call: + ; fn + loadsp 4 + + ; return address + loadsp 4 + + ; store return address + storesp 12 + + ; fn to call + storesp 4 + + pushsp ; flush internal stack + popsp + + poppc + +_storehtail: + + and + loadsp 12 + im 3 + and + fast_neg + im 2 + add + im 3 + ashiftleft + nop + ashiftleft + + or + + loadsp 8 + im ~0x3 + and + + store + + storesp 4 + storesp 4 + poppc + + +# opcode 46 +# offset 0x0000 01c0 + .balign 32,0 +_eq: + loadsp 8 + fast_neg + loadsp 8 + add + + not + loadsp 0 + im 1 + add + not + and + flip + im 1 + and + + storesp 12 + storesp 4 + poppc + +# opcode 47 +# offset 0x0000 01e0 + .balign 32,0 +_neq: + loadsp 8 + fast_neg + loadsp 8 + add + + not + loadsp 0 + im 1 + add + not + and + flip + + not + + im 1 + and + + storesp 12 + storesp 4 + poppc + + +# opcode 48 +# offset 0x0000 0200 + .balign 32,0 +_neg: + loadsp 4 + not + im 1 + add + storesp 8 + + poppc + + +# opcode 49 +# offset 0x0000 0220 + .balign 32,0 +_sub: + loadsp 8 + loadsp 8 + fast_neg + add + storesp 12 + + storesp 4 + + poppc + + +# opcode 50 +# offset 0x0000 0240 + .balign 32,0 +_xor: + loadsp 8 + not + loadsp 8 + and + + loadsp 12 + loadsp 12 + not + and + + or + + storesp 12 + storesp 4 + poppc + +# opcode 51 +# offset 0x0000 0260 + .balign 32,0 +_loadb: + loadsp 4 + im ~0x3 + and + load + + loadsp 8 + im 3 + and + fast_neg + im 3 + add + ; x8 + addsp 0 + addsp 0 + addsp 0 + + lshiftright + + im 0xff + and + storesp 8 + + poppc + + +# opcode 52 +# offset 0x0000 0280 + .balign 32,0 +_storeb: + loadsp 4 + im ~0x3 + and + load + + ; mask away destination + im _mask + loadsp 12 + im 3 + and + addsp 0 + addsp 0 + add + load + + and + + + im _storebtail + poppc + +# opcode 53 +# offset 0x0000 02a0 + .balign 32,0 +_div: + cimpl __divsi3 + +# opcode 54 +# offset 0x0000 02c0 + .balign 32,0 +_mod: + cimpl __modsi3 + +# opcode 55 +# offset 0x0000 02e0 + .balign 32,0 + .globl _eqbranch +_eqbranch: + loadsp 8 + + ; eq + + not + loadsp 0 + im 1 + add + not + and + flip + im 1 + and + + ; mask + im -1 + add + loadsp 0 + storesp 16 + + ; no branch address + loadsp 4 + + and + + ; fetch boolean & neg mask + loadsp 12 + not + + ; calc address & mask for branch + loadsp 8 + loadsp 16 + add + ; subtract 1 to find PC of branch instruction + im -1 + add + + and + + or + + storesp 4 + storesp 4 + storesp 4 + poppc + + +# opcode 56 +# offset 0x0000 0300 + .balign 32,0 + .globl _neqbranch +_neqbranch: + loadsp 8 + + ; neq + + not + loadsp 0 + im 1 + add + not + and + flip + + not + + im 1 + and + + ; mask + im -1 + add + loadsp 0 + storesp 16 + + ; no branch address + loadsp 4 + + and + + ; fetch boolean & neg mask + loadsp 12 + not + + ; calc address & mask for branch + loadsp 8 + loadsp 16 + add + ; find address of branch instruction + im -1 + add + + and + + or + + storesp 4 + storesp 4 + storesp 4 + poppc + +# opcode 57 +# offset 0x0000 0320 + .balign 32,0 + .globl _poppcrel +_poppcrel: + add + ; address of poppcrel + im -1 + add + poppc + +# opcode 58 +# offset 0x0000 0340 + .balign 32,0 + .globl _config +_config: + im 1 + nop + im _hardware + store + storesp 4 + poppc + +# opcode 59 +# offset 0x0000 0360 + .balign 32,0 +_pushpc: + loadsp 4 + im 1 + add + storesp 8 + poppc + +# opcode 60 +# offset 0x0000 0380 + .balign 32,0 +_syscall_emulate: + .byte 0 + +# opcode 61 +# offset 0x0000 03a0 + .balign 32,0 +_pushspadd: + pushsp + im 4 + add + loadsp 8 + addsp 0 + addsp 0 + add + storesp 8 + + poppc + +# opcode 62 +# offset 0x0000 03c0 + .balign 32,0 +_halfmult: + breakpoint + +# opcode 63 +# offset 0x0000 03e0 + .balign 32,0 +_callpcrel: + loadsp 4 + loadsp 4 + add + im -1 + add + loadsp 4 + + storesp 12 ; return address + storesp 4 + pushsp ; this will flush the internal stack. + popsp + poppc + + .text + + + + +_ashiftleftBegin: + .rept 0x1f + addsp 0 + .endr +_ashiftleftEnd: + storesp 12 + storesp 4 + poppc + +_storebtail: + loadsp 12 + im 0xff + and + loadsp 12 + im 3 + and + + fast_neg + im 3 + add + ; x8 + addsp 0 + addsp 0 + addsp 0 + + ashiftleft + + or + + loadsp 8 + im ~0x3 + and + + store + + storesp 4 + storesp 4 + poppc + + + + +; NB! this is not an EMULATE instruction. It is a varargs fn. + .globl _syscall +_syscall: + syscall + poppc + +_slowmultImpl: + + loadsp 8 ; A + loadsp 8 ; B + im 0 ; C + +.LmoreMult: + mult1bit + + ; cutoff + loadsp 8 + .byte (.LmoreMult-.Lbranch)&0x7f+0x80 +.Lbranch: + neqbranch + + storesp 4 + storesp 4 + storesp 12 + storesp 4 + poppc + + .data + .balign 4,0 +_mask: + .long 0x00ffffff + .long 0xff00ffff + .long 0xffff00ff + .long 0xffffff00 + + + .globl _hardware +_hardware: + .long 0 + .globl _cpu_config +_cpu_config: + .long 0 + diff --git a/zpu/sw/startup/crt_io.c b/zpu/sw/startup/crt_io.c new file mode 100644 index 0000000..966ae33 --- /dev/null +++ b/zpu/sw/startup/crt_io.c @@ -0,0 +1,91 @@ +#include +#include +#include +#include + +extern int _hardware; +/* _cpu_config==0 => Abel + * _cpu_config==1 => Zeta + * _cpu_config==2 => Phi + */ +extern int _cpu_config; +static volatile int *UART; +static volatile int *TIMER; +volatile int *MHZ; + + + +/* + * Wait indefinitely for input byte + */ + + +int __attribute__ ((weak)) inbyte() +{ + int val; + for (;;) + { + val=UART[1]; + if ((val&0x100)!=0) + { + return val&0xff; + } + } +} + + + +/* + * Output one character to the serial port + * + * + */ +void __attribute__ ((weak)) outbyte(int c) +{ + /* Wait for space in FIFO */ + while ((UART[0]&0x100)==0); + UART[0]=c; +} + +static const int mhz=64; + +void __attribute__ ((weak)) _initIO(void) +{ + if (_hardware) + { + if (_cpu_config==2) + { + /* Phi board addresses */ + UART=(volatile int *)0x080a000c; + TIMER=(volatile int *)0x080a0014; + MHZ=(volatile int *)&mhz; + } else + { + /* Abel board */ + UART=(volatile int *)0xc000; + TIMER=(volatile int *)0x9000; + MHZ=(volatile int *)0x8800; + } + } else + { + UART=(volatile int *)0x80000024; + TIMER=(volatile int *)0x80000100; + MHZ=(volatile int *)0x80000200; + } +} + + + +long long __attribute__ ((weak)) _readCycles() +{ + long long clock; + unsigned int i; + + TIMER[0]=0x2; /* sample timer */ + clock=0; + for (i=0; i<2; i++) + { + clock|=((long long )(TIMER[i]))<<(i*32); + } + return clock; +} diff --git a/zpu/sw/startup/time.c b/zpu/sw/startup/time.c new file mode 100644 index 0000000..767b62f --- /dev/null +++ b/zpu/sw/startup/time.c @@ -0,0 +1,32 @@ +#include <_ansi.h> +#include +#include + +extern long long _readCycles(); + + +extern volatile int *MHZ; + +long long _readMicroseconds() +{ + int Hz; + long long clock; + Hz=(*MHZ&0xff); + clock=_readCycles(); + return clock/(long long)Hz; +} + + + + +time_t +time (time_t *tloc) +{ + time_t t; + t=(time_t)(_readMicroseconds()/(long long )1000000); + if (tloc!=NULL) + { + *tloc=t; + } + return t; +} -- cgit v1.1 From 7792f314b6b259b9d5088337dad4c9e8519ce095 Mon Sep 17 00:00:00 2001 From: oharboe Date: Mon, 18 Aug 2008 12:28:59 +0000 Subject: very early work. --- zpu/docs/zpu_arch.html | 6 + zpu/sw/startup/nextgen_crt0.S | 894 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 900 insertions(+) create mode 100644 zpu/sw/startup/nextgen_crt0.S diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index d8d982d..21b7df5 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -1335,6 +1335,12 @@ pushed onto stack before jumping to unkonwn instruction vector. This makes it po to write denser microcode for missing instructions. For emulated opcodes that are not in use, the microcode can more easily be disabled. Determining that e.g. MULT is not used, can be a bit tricky, but disabling it is easy. +

        +The address of this entry will be 0x10. The reason 0x00 is not used is that +GCC needs 0x00-0x0b inclusive to store R0-R2(memory mapped GCC registers). +The reset vector remains 0x0 so the 0x00-0x0f addresses contains the +first few instructions executed by the ZPU. Some very early work has been +done in nextgen_crt0.S.

      23. Single entry for *all* unknown instructions does not limit emulation to the EMULATE instructions today, but instructions such as OR, LOADSP, STORESP, ADDSP, etc. can also be emulated. This opens up for further reduction in logic usage. diff --git a/zpu/sw/startup/nextgen_crt0.S b/zpu/sw/startup/nextgen_crt0.S new file mode 100644 index 0000000..3cf9112 --- /dev/null +++ b/zpu/sw/startup/nextgen_crt0.S @@ -0,0 +1,894 @@ +/* Startup code for ZPU + Copyright (C) 2005 Free Software Foundation, Inc. + +This file is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +In addition to the permissions in the GNU General Public License, the +Free Software Foundation gives you unlimited permission to link the +compiled version of this file with other programs, and to distribute +those programs without any restriction coming from the use of this +file. (The General Public License restrictions do apply in other +respects; for example, they cover modification of the file, and +distribution when not linked into another program.) + +This file is distributed in the hope that it will be useful, but +WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + .file "crt0.S" + + .section ".fixed_vectors","ax" + + + + + .macro fast_neg + not + im 1 + add + .endm + + .macro cimpl funcname + ; save R0 + im 0 + load + + ; save R1 + im 4 + load + + ; save R2 + im 8 + load + + loadsp 20 + loadsp 20 + + fixedim \funcname + call + + ; destroy arguments on stack + storesp 0 + storesp 0 + + im 0 + load + + ; poke the result into the right slot + storesp 24 + + ; restore R2 + im 8 + store + + ; restore R1 + im 4 + store + + ; restore r0 + im 0 + store + + storesp 4 + poppc + .endm + + + + +/* vectors */ + .balign 32,0 +# offset 0x0000 0000 + .globl _start +_start: + im _premain + poppc + + .balign 16,0 +# offset 0x0000 0010 + .globl _zpu_unknown_instruction_vector +_zpu_unknown_instruction: + /* We have unsupported instruction * 4 on stack */ + im _emulate_table + add + load + poppc + + .rodata + .balign 4,0 +_emulate_table: + .long _storeh + .long ... + +/* instruction emulation code */ + +# opcode 34 +# offset 0x0000 0040 + .balign 32,0 +_loadh: + loadsp 4 + ; by not masking out bit 0, we cause a memory access error + ; on unaligned access + im ~0x2 + and + load + + ; mult 8 + loadsp 8 + im 3 + and + fast_neg + im 2 + add + im 3 + ashiftleft + ; shift right addr&3 * 8 + lshiftright + im 0xffff + and + storesp 8 + + poppc + +# opcode 35 +# offset 0x0000 0060 + .balign 32,0 +_storeh: + loadsp 4 + ; by not masking out bit 0, we cause a memory access error + ; on unaligned access + im ~0x2 + and + load + + ; mask + im 0xffff + loadsp 12 + im 3 + and + fast_neg + im 2 + add + im 3 + ashiftleft + ashiftleft + not + + and + + loadsp 12 + im 0xffff + + nop + + fixedim _storehtail + poppc + + +# opcode 36 +# offset 0x0000 0080 + .balign 32,0 +_lessthan: + loadsp 8 + fast_neg + loadsp 8 + add + + ; DANGER!!!! + ; 0x80000000 will overflow when negated, so we need to mask + ; the result above with the compare positive to negative + ; number case + loadsp 12 + loadsp 12 + not + and + not + and + + + ; handle case where we are comparing a negative number + ; and positve number. This can underflow. E.g. consider 0x8000000 < 0x1000 + loadsp 12 + not + loadsp 12 + and + + or + + + + flip + im 1 + and + + + storesp 12 + storesp 4 + poppc + + +# opcode 37 +# offset 0x0000 00a0 + .balign 32,0 +_lessthanorequal: + loadsp 8 + loadsp 8 + lessthan + loadsp 12 + loadsp 12 + eq + or + + storesp 12 + storesp 4 + poppc + + +# opcode 38 +# offset 0x0000 00c0 + .balign 32,0 +_ulessthan: + ; fish up arguments + loadsp 4 + loadsp 12 + + /* low: -1 if low bit dif is negative 0 otherwise: neg (not x&1 and (y&1)) + x&1 y&1 neg (not x&1 and (y&1)) + 1 1 0 + 1 0 0 + 0 1 -1 + 0 0 0 + + */ + loadsp 4 + not + loadsp 4 + and + im 1 + and + neg + + + /* high: upper 31-bit diff is only wrong when diff is 0 and low=-1 + high=x>>1 - y>>1 + low + + extremes + + 0000 - 1111: + low= neg(not 0 and 1) = 1111 (-1) + high=000+ neg(111) +low = 000 + 1001 + low = 1000 + OK + + 1111 - 0000 + low=neg(not 1 and 0) = 0 + high=111+neg(000) + low = 0111 + OK + + + */ + loadsp 8 + + flip + addsp 0 + flip + + loadsp 8 + + flip + addsp 0 + flip + + sub + + ; if they are equal, then the last bit decides... + add + + /* test if negative: result = flip(diff) & 1 */ + flip + im 1 + and + + ; destroy a&b which are on stack + storesp 4 + storesp 4 + + storesp 12 + storesp 4 + poppc + +# opcode 39 +# offset 0x0000 00e0 + .balign 32,0 +_ulessthanorequal: + loadsp 8 + loadsp 8 + ulessthan + loadsp 12 + loadsp 12 + eq + or + + storesp 12 + storesp 4 + poppc + + +# opcode 40 +# offset 0x0000 0100 + .balign 32,0 + .globl _swap +_swap: + breakpoint ; tbd + +# opcode 41 +# offset 0x0000 0120 + .balign 32,0 +_slowmult: + im _slowmultImpl + poppc + +# opcode 42 +# offset 0x0000 0140 + .balign 32,0 +_lshiftright: + loadsp 8 + flip + + loadsp 8 + ashiftleft + flip + + storesp 12 + storesp 4 + + poppc + + +# opcode 43 +# offset 0x0000 0160 + .balign 32,0 +_ashiftleft: + loadsp 8 + + loadsp 8 + im 0x1f + and + fast_neg + im _ashiftleftEnd + add + poppc + + + +# opcode 44 +# offset 0x0000 0180 + .balign 32,0 +_ashiftright: + loadsp 8 + loadsp 8 + lshiftright + + ; handle signed value + im -1 + loadsp 12 + im 0x1f + and + lshiftright + not ; now we have an integer on the stack with the signed + ; bits in the right position + + ; mask these bits with the signed bit. + loadsp 16 + not + flip + im 1 + and + im -1 + add + + and + + ; stuff in the signed bits... + or + + ; store result into correct stack slot + storesp 12 + + ; move up return value + storesp 4 + poppc + +# opcode 45 +# offset 0x0000 01a0 + .balign 32,0 +_call: + ; fn + loadsp 4 + + ; return address + loadsp 4 + + ; store return address + storesp 12 + + ; fn to call + storesp 4 + + pushsp ; flush internal stack + popsp + + poppc + +_storehtail: + + and + loadsp 12 + im 3 + and + fast_neg + im 2 + add + im 3 + ashiftleft + nop + ashiftleft + + or + + loadsp 8 + im ~0x3 + and + + store + + storesp 4 + storesp 4 + poppc + + +# opcode 46 +# offset 0x0000 01c0 + .balign 32,0 +_eq: + loadsp 8 + fast_neg + loadsp 8 + add + + not + loadsp 0 + im 1 + add + not + and + flip + im 1 + and + + storesp 12 + storesp 4 + poppc + +# opcode 47 +# offset 0x0000 01e0 + .balign 32,0 +_neq: + loadsp 8 + fast_neg + loadsp 8 + add + + not + loadsp 0 + im 1 + add + not + and + flip + + not + + im 1 + and + + storesp 12 + storesp 4 + poppc + + +# opcode 48 +# offset 0x0000 0200 + .balign 32,0 +_neg: + loadsp 4 + not + im 1 + add + storesp 8 + + poppc + + +# opcode 49 +# offset 0x0000 0220 + .balign 32,0 +_sub: + loadsp 8 + loadsp 8 + fast_neg + add + storesp 12 + + storesp 4 + + poppc + + +# opcode 50 +# offset 0x0000 0240 + .balign 32,0 +_xor: + loadsp 8 + not + loadsp 8 + and + + loadsp 12 + loadsp 12 + not + and + + or + + storesp 12 + storesp 4 + poppc + +# opcode 51 +# offset 0x0000 0260 + .balign 32,0 +_loadb: + loadsp 4 + im ~0x3 + and + load + + loadsp 8 + im 3 + and + fast_neg + im 3 + add + ; x8 + addsp 0 + addsp 0 + addsp 0 + + lshiftright + + im 0xff + and + storesp 8 + + poppc + + +# opcode 52 +# offset 0x0000 0280 + .balign 32,0 +_storeb: + loadsp 4 + im ~0x3 + and + load + + ; mask away destination + im _mask + loadsp 12 + im 3 + and + addsp 0 + addsp 0 + add + load + + and + + + im _storebtail + poppc + +# opcode 53 +# offset 0x0000 02a0 + .balign 32,0 +_div: + cimpl __divsi3 + +# opcode 54 +# offset 0x0000 02c0 + .balign 32,0 +_mod: + cimpl __modsi3 + +# opcode 55 +# offset 0x0000 02e0 + .balign 32,0 + .globl _eqbranch +_eqbranch: + loadsp 8 + + ; eq + + not + loadsp 0 + im 1 + add + not + and + flip + im 1 + and + + ; mask + im -1 + add + loadsp 0 + storesp 16 + + ; no branch address + loadsp 4 + + and + + ; fetch boolean & neg mask + loadsp 12 + not + + ; calc address & mask for branch + loadsp 8 + loadsp 16 + add + ; subtract 1 to find PC of branch instruction + im -1 + add + + and + + or + + storesp 4 + storesp 4 + storesp 4 + poppc + + +# opcode 56 +# offset 0x0000 0300 + .balign 32,0 + .globl _neqbranch +_neqbranch: + loadsp 8 + + ; neq + + not + loadsp 0 + im 1 + add + not + and + flip + + not + + im 1 + and + + ; mask + im -1 + add + loadsp 0 + storesp 16 + + ; no branch address + loadsp 4 + + and + + ; fetch boolean & neg mask + loadsp 12 + not + + ; calc address & mask for branch + loadsp 8 + loadsp 16 + add + ; find address of branch instruction + im -1 + add + + and + + or + + storesp 4 + storesp 4 + storesp 4 + poppc + +# opcode 57 +# offset 0x0000 0320 + .balign 32,0 + .globl _poppcrel +_poppcrel: + add + ; address of poppcrel + im -1 + add + poppc + +# opcode 58 +# offset 0x0000 0340 + .balign 32,0 + .globl _config +_config: + im 1 + nop + im _hardware + store + storesp 4 + poppc + +# opcode 59 +# offset 0x0000 0360 + .balign 32,0 +_pushpc: + loadsp 4 + im 1 + add + storesp 8 + poppc + +# opcode 60 +# offset 0x0000 0380 + .balign 32,0 +_syscall_emulate: + .byte 0 + +# opcode 61 +# offset 0x0000 03a0 + .balign 32,0 +_pushspadd: + pushsp + im 4 + add + loadsp 8 + addsp 0 + addsp 0 + add + storesp 8 + + poppc + +# opcode 62 +# offset 0x0000 03c0 + .balign 32,0 +_halfmult: + breakpoint + +# opcode 63 +# offset 0x0000 03e0 + .balign 32,0 +_callpcrel: + loadsp 4 + loadsp 4 + add + im -1 + add + loadsp 4 + + storesp 12 ; return address + storesp 4 + pushsp ; this will flush the internal stack. + popsp + poppc + + .text + + + + +_ashiftleftBegin: + .rept 0x1f + addsp 0 + .endr +_ashiftleftEnd: + storesp 12 + storesp 4 + poppc + +_storebtail: + loadsp 12 + im 0xff + and + loadsp 12 + im 3 + and + + fast_neg + im 3 + add + ; x8 + addsp 0 + addsp 0 + addsp 0 + + ashiftleft + + or + + loadsp 8 + im ~0x3 + and + + store + + storesp 4 + storesp 4 + poppc + + + + +; NB! this is not an EMULATE instruction. It is a varargs fn. + .globl _syscall +_syscall: + syscall + poppc + +_slowmultImpl: + + loadsp 8 ; A + loadsp 8 ; B + im 0 ; C + +.LmoreMult: + mult1bit + + ; cutoff + loadsp 8 + .byte (.LmoreMult-.Lbranch)&0x7f+0x80 +.Lbranch: + neqbranch + + storesp 4 + storesp 4 + storesp 12 + storesp 4 + poppc + + .data + .balign 4,0 +_mask: + .long 0x00ffffff + .long 0xff00ffff + .long 0xffff00ff + .long 0xffffff00 + + + .globl _hardware +_hardware: + .long 0 + .globl _cpu_config +_cpu_config: + .long 0 + +; Pointers to emulated instructions -- cgit v1.1 From 16b20b21e402e6463b89f5a942073f19daaaecb8 Mon Sep 17 00:00:00 2001 From: oharboe Date: Mon, 18 Aug 2008 16:14:38 +0000 Subject: wip --- zpu/docs/zpu_arch.html | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index 21b7df5..f6fd8d1 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -10,6 +10,7 @@
      24. Jump vectors
      25. Memory map
      26. Interrupts +
      27. Wishbone
      28. About zpu_core_small.vhd
      29. About zpu_core.vhd
      30. Next generation ZPU @@ -1265,6 +1266,16 @@ memory map below. + +

        Wishbone

        +In         hdl/wishbone there is an implementation +of a wishbone bridge. +

        +However this wishbone bridge was used together with the hdl/zy2000 implementation +of the ZPU, which differs slightly from hdl/zpu4/core. +

        +The ZY2000 is a complete implementation of the ZPU including: DRAM, soft-MAC, wishbone bridges, GPIO subsystem, +etc. This also included an eCos HAL w/TCP/IP support.

        Interrupts

        The ZPU supports interrupts. -- cgit v1.1 From 952bcd56f3b4e412594920ef02d9d740b3ce119a Mon Sep 17 00:00:00 2001 From: oharboe Date: Thu, 21 Aug 2008 21:12:57 +0000 Subject: merging in some docs to zpu_arch.html --- zpu/docs/images/gccgdb.PNG | Bin 0 -> 34473 bytes zpu/docs/images/zpusim.PNG | Bin 0 -> 17817 bytes zpu/docs/zpu_arch.html | 106 +++++++++++++++++++++++++++++++++++++++---- zpu/hdl/index.html | 49 -------------------- zpu/index.html | 20 -------- zpu/sw/helloworld/gccgdb.PNG | Bin 34473 -> 0 bytes zpu/sw/helloworld/zpusim.PNG | Bin 17817 -> 0 bytes zpu/sw/index.html | 44 ------------------ 8 files changed, 98 insertions(+), 121 deletions(-) create mode 100644 zpu/docs/images/gccgdb.PNG create mode 100644 zpu/docs/images/zpusim.PNG delete mode 100644 zpu/hdl/index.html delete mode 100644 zpu/index.html delete mode 100644 zpu/sw/helloworld/gccgdb.PNG delete mode 100644 zpu/sw/helloworld/zpusim.PNG delete mode 100644 zpu/sw/index.html diff --git a/zpu/docs/images/gccgdb.PNG b/zpu/docs/images/gccgdb.PNG new file mode 100644 index 0000000..afdfc31 Binary files /dev/null and b/zpu/docs/images/gccgdb.PNG differ diff --git a/zpu/docs/images/zpusim.PNG b/zpu/docs/images/zpusim.PNG new file mode 100644 index 0000000..d8fc277 Binary files /dev/null and b/zpu/docs/images/zpusim.PNG differ diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index f6fd8d1..84ccc1a 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -2,8 +2,9 @@

        Index

         - -

        Getting started

        -The ZPU comes with a few simulation examples. + +         +

        Getting started - FPGA

        +The simplest version of the ZPU uses BRAM. When getting accustomed to the ZPU, a BRAM ZPU with a UART +is a good place to start. +

        +You'll find a working simulation script in hdl/example/simzpu_small.do and hdl/example_medium/simzpu_medium.do, which +show simulation of the small(zpu_core_small.vhd) and medium sized ZPU(zpu_core.vhd). hdl/example/simzpu_interrupt.do +shows use of interrupts. +

        +When implementing the ZPU, copy the following files and modify them to your needs: +

          +
        1. hdl/example/zpu_config.vhd - set up RAM size here +
        2. hdl/example/helloworld.vhd - dual port BRAM implementation. +
        +Obviously you must also connect the ZPU to the rest of your IO subsystem. IO is memory mapped(read/write) in the ZPU. +

        Generating VHDL BRAM initialization

        + + +../install/bin/zpu-elf-objcopy -O binary hello.elf hello.bin
        +java -classpath ../simulator/zpusim.jar com.zylin.zpu.simulator.tools.MakeRam hello.bin >hello.bram
        + +         +

        Running example simulation

        +The hdl/example directory has a simulation written for Xilinx WebPack ModelSim. From the ModelSim command prompt: +
          +
        1. cd c:/<installfolder>/hdl/example +
        2. do zpusim_small.do +
        +

        +After running the hello world simulation (see zpusim.do), two files are written to the hdl/example directory: +

          +
        1. log.txt - contains the "Hello world!" text written to the debug channel/simplified UART. +
        2. trace.txt - a trace file for the CPU. The instruction set simulator has the capability of taking +this file as input in order to verify that the HDL implementation matches the instruction set simulator. +When a mismatch is found, the GDB debugger will break. Very handy for debugging custom ZPU implementations. +
        +

        HDL Directories & files

        +
          +
        • example - contains example files & working ZPU. Start here. +
        • wishbone - contains wishbone interface for the ZPU +
        • zpu3 - if you are interested in developing ZPU cores and not only using them, then this directory contains various stuff of more or less historical interest. +
        • zpu4 - if you are interested in developing ZPU cores and not only using them, then this is the active development version. You'll also want to copy out the +files you need from this folder to your own project. +
        + +The HDL files need a bit of spit and polish! + +         +

        Getting started - software

        +The ZPU comes with a standard GCC toolchain and an instruction set simulator. This allows compiling, running & debugging simple test programs. The Simulator has +some very basic peripherals defined: counter, timer interrupt and a debug output port. +

        Installing

        +
          +
        1. Install Cygwin. http://www.cygwin.com +
        2. Install Java +
        3. Start Cygwin bash +
        4. cd zpu/sw +
        5. sh setup.sh +
        6. /tmp/zpu/install/bin now has the .exe files for the GCC toolchain & GDB +
        7. Optionally you may set up PATH variables to point to /tmp/zpu/install/bin
          +source env.sh +
        +

        Hello world example

        +The ZPU toolchain comes with newlib & libstdc++ support which means that many C/C++ programs can be compiled without modification. +

        + +cd zpu/sw/helloworld
        +../install/bin/zpu-elf-gcc -phi hello.c -o hello.elf
        +         +

        Running the hello world example in GDB

        +
          +
        1. cd zpu/sw/helloworld +
        2. Launch the simulator from a seperate bash shell:

          +java -classpath ../simulator/zpusim.jar -Xmx512m com.zylin.zpu.simulator.Phi 4444 +

          + +

        3. Launch GDB:

          +../install/bin/zpu-elf-gdb hello.elf +

        4. Connect to target, load and run application:

          + +(gdb) target remote localhost:4444
          +(gdb) load
          +(gdb) continue
          +

          -Start with VHDL synthesis examples + + +

        + + -

        Introduction

        +

        Architecture introduction

        The ZPU is a zero operand, or stack based CPU. The opcodes have a fixed width of 8 bits.

        Example: @@ -893,7 +980,8 @@ the right choices w.r.t. optimisation for your application.

        Phi memory map

        The ZPU architecture does not define a memory map as such, but the GCC + libgloss + ecos hal library uses the -memory map below. +memory map below. "Phi" is just a three letter word for the particular memory layout below that came about +while developing the ZPU.

        @@ -1387,5 +1475,7 @@ For this to make sense, the performance must hit 20 DMIPS w/DRAM & cache. This ZPU could run a TCP/IP stack with relevant performance to compete with stripped down ARM7 type systems. + + \ No newline at end of file diff --git a/zpu/hdl/index.html b/zpu/hdl/index.html deleted file mode 100644 index e206113..0000000 --- a/zpu/hdl/index.html +++ /dev/null @@ -1,49 +0,0 @@ - - -

        Getting started - FPGA

        -The simplest version of the ZPU uses BRAM. When getting accustomed to the ZPU, a BRAM ZPU with a UART -is a good place to start. -

        -You'll find a working simulation script in hdl/example/simzpu_small.do and hdl/example_medium/simzpu_medium.do, which -show simulation of the small(zpu_core_small.vhd) and medium sized ZPU(zpu_core.vhd). hdl/example/simzpu_interrupt.do -shows use of interrupts. -

        -When implementing the ZPU, copy the following files and modify them to your needs: -

          -
        1. hdl/example/zpu_config.vhd - set up RAM size here -
        2. hdl/example/helloworld.vhd - dual port BRAM implementation. -
        -Obviously you must also connect the ZPU to the rest of your IO subsystem. IO is memory mapped(read/write) in the ZPU. -

        Generating VHDL BRAM initialization

        - - -../install/bin/zpu-elf-objcopy -O binary hello.elf hello.bin
        -java -classpath ../simulator/zpusim.jar com.zylin.zpu.simulator.tools.MakeRam hello.bin >hello.bram
        - -         -

        Running example simulation

        -The hdl/example directory has a simulation written for Xilinx WebPack ModelSim. From the ModelSim command prompt: -
          -
        1. cd c:/<installfolder>/hdl/example -
        2. do zpusim_small.do -
        -

        -After running the hello world simulation (see zpusim.do), two files are written to the hdl/example directory: -

          -
        1. log.txt - contains the "Hello world!" text written to the debug channel/simplified UART. -
        2. trace.txt - a trace file for the CPU. The instruction set simulator has the capability of taking -this file as input in order to verify that the HDL implementation matches the instruction set simulator. -When a mismatch is found, the GDB debugger will break. Very handy for debugging custom ZPU implementations. -
        -

        HDL Directories & files

        -
          -
        • example - contains example files & working ZPU. Start here. -
        • wishbone - contains wishbone interface for the ZPU -
        • zpu3 - if you are interested in developing ZPU cores and not only using them, then this directory contains various stuff of more or less historical interest. -
        • zpu4 - if you are interested in developing ZPU cores and not only using them, then this is the active development version. You'll also want to copy out the -files you need from this folder to your own project. -
        - -The HDL files need a bit of spit and polish! - - diff --git a/zpu/index.html b/zpu/index.html deleted file mode 100644 index 7343ab6..0000000 --- a/zpu/index.html +++ /dev/null @@ -1,20 +0,0 @@ - - -

        Getting started

        -FPGA: check out zpu/hdl, read zpu/hdl/index.html -

        -Software: check out zpu/sw, read zpu/sw/index.html -

        -Docs: start with ZPU architecture doc -

        Other directories

        -You probably don't need or want to download other directories. -
          -
        • -gccsrc - the complete GCC toolchain source. Big! Almost certainly not something you need or want to download. This has been moved to /trunk/zpugccsrc to -avoid subversion choking. -
        • roadshow - various bits and bobs to demonstrate the ZPU that has not been sorted/reorganized yet. - -
        - - - diff --git a/zpu/sw/helloworld/gccgdb.PNG b/zpu/sw/helloworld/gccgdb.PNG deleted file mode 100644 index afdfc31..0000000 Binary files a/zpu/sw/helloworld/gccgdb.PNG and /dev/null differ diff --git a/zpu/sw/helloworld/zpusim.PNG b/zpu/sw/helloworld/zpusim.PNG deleted file mode 100644 index d8fc277..0000000 Binary files a/zpu/sw/helloworld/zpusim.PNG and /dev/null differ diff --git a/zpu/sw/index.html b/zpu/sw/index.html deleted file mode 100644 index fd0a1b4..0000000 --- a/zpu/sw/index.html +++ /dev/null @@ -1,44 +0,0 @@ - - -

        Getting started - a ZPU hello world program

        -The ZPU comes with a standard GCC toolchain and an instruction set simulator. This allows compiling, running & debugging simple test programs. The Simulator has -some very basic peripherals defined: counter, timer interrupt and a debug output port. -

        Installing

        -
          -
        1. Install Cygwin. http://www.cygwin.com -
        2. Install Java -
        3. Start Cygwin bash -
        4. cd zpu/sw -
        5. sh setup.sh -
        6. /tmp/zpu/install/bin now has the .exe files for the GCC toolchain & GDB -
        7. Optionally you may set up PATH variables to point to /tmp/zpu/install/bin
          -source env.sh -
        -

        Hello world example

        -The ZPU toolchain comes with newlib & libstdc++ support which means that many C/C++ programs can be compiled without modification. -

        - -cd zpu/sw/helloworld
        -../install/bin/zpu-elf-gcc -phi hello.c -o hello.elf
        -         -

        Running the hello world example in GDB

        -
          -
        1. cd zpu/sw/helloworld -
        2. Launch the simulator from a seperate bash shell:

          -java -classpath ../simulator/zpusim.jar -Xmx512m com.zylin.zpu.simulator.Phi 4444 -

          - -

        3. Launch GDB:

          -../install/bin/zpu-elf-gdb hello.elf -

        4. Connect to target, load and run application:

          - -(gdb) target remote localhost:4444
          -(gdb) load
          -(gdb) continue
          -           -

          - - - - - -- cgit v1.1 From 7e91fb42c0e203a15024f9d5014e2df516fbb037 Mon Sep 17 00:00:00 2001 From: oharboe Date: Thu, 21 Aug 2008 21:22:59 +0000 Subject: added some notes on speeding up the ZPU --- zpu/docs/zpu_arch.html | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index 84ccc1a..c7e20bc 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -11,6 +11,7 @@

        5. Jump vectors
        6. Memory map
        7. Interrupts +
        8. Speeding up the ZPU
        9. Wishbone
        10. About zpu_core_small.vhd
        11. About zpu_core.vhd @@ -1409,6 +1410,46 @@ The tricky bit is that there is a tiny bit of interleaving of states since the BRAM takes a cycle to perform a fetch/store. The above is the normal states the ZPU cycles through unless memory fetch, jumps, etc. take place. + +

          Speeding up the ZPU

          +There are two aspects of speeding up the ZPU: making it perform better +for a particular application and toying around with the ZPU architecture. +

          Performance tips

          +
            +
          1. Profile. Create a small sample and run in a simulator that is as close +to the real deployment as possible. zpu4/core/histogram.perl is a script +that will tell you which instructions take the most time. +
          2. Using the profile output, decide on which emulated instructions that +it makes sense to implement in HDL for your particular application. Modifying +zpu_core_small.vhd is not particularly hard. Most instructions can be +transliterated into zpu_core_small.vhd from zpu_core.vhd without too much +problem. +
          3. The memory subsystem may well turn out to be where you should concentrate +your efforts. +
          +

          Toying around with the architecture

          +Again: profile 90% of the time and spend the remaining 10% tinkering +with the architecture. +
            +
          • There is a DMIPS program you can use to measure the performance of +the ZPU in lieu of profiling a real application. The latter is obviously +a superior solution. +
          • Again: use histogram.perl to figure out which instructions you should add +in HDL. +
          • Tinker a bit with Fmax to find the maximum speed rating for your design. +
          • zpu_core_small.vhd should be ca. 1 DMIPS and zpu_core.vhd should yield +about 5-10 DMIPS before adding instructions runs out of steam. +
          +If you need to get ca. 20-50 DMIPS out of the ZPU you will have to +write a heavily pipelined architecture with caches(if you are running +against DRAM). This is *tricky*, but some proof of concept work was +done to show 20 DMIPS w/the ZPU(the actual result was discarded since +it was not complete and contained fatal flaws). +

          +Achieving above 50-100 DMIPS with the current ZPU architecture is probably +a non-starter and a more conventional RISC design makes more sense here. +

          +The unique advantages of the ZPU is size in terms of HDL & code size.

          About zpu_core.vhd

          The zpu_core.vhd has a single port memory interface. All data, code and IO is -- cgit v1.1 From e19e8f1a9124a87b859bd8e1cab5ad0a07892bdd Mon Sep 17 00:00:00 2001 From: oharboe Date: Thu, 21 Aug 2008 21:36:29 +0000 Subject: more docs merged into the big doc --- zpu/docs/images/GCC_logo.png | Bin 0 -> 23450 bytes zpu/docs/images/codesize1.PNG | Bin 0 -> 9329 bytes zpu/docs/images/codesize2.PNG | Bin 0 -> 16967 bytes zpu/docs/images/ecos.gif | Bin 0 -> 1660 bytes zpu/docs/images/elizadebug1.PNG | Bin 0 -> 72126 bytes zpu/docs/images/elizadebug2.PNG | Bin 0 -> 67822 bytes zpu/docs/zpu_arch.html | 203 +++++++++++++++++++++++++++++ zpu/roadshow/roadshow/codesize/index.html | 58 --------- zpu/roadshow/roadshow/ecos/index.html | 145 --------------------- zpu/roadshow/roadshow/pics/GCC_logo.png | Bin 23450 -> 0 bytes zpu/roadshow/roadshow/pics/codesize1.PNG | Bin 9329 -> 0 bytes zpu/roadshow/roadshow/pics/codesize2.PNG | Bin 16967 -> 0 bytes zpu/roadshow/roadshow/pics/ecos.gif | Bin 1660 -> 0 bytes zpu/roadshow/roadshow/pics/elizadebug1.PNG | Bin 72126 -> 0 bytes zpu/roadshow/roadshow/pics/elizadebug2.PNG | Bin 67822 -> 0 bytes 15 files changed, 203 insertions(+), 203 deletions(-) create mode 100644 zpu/docs/images/GCC_logo.png create mode 100644 zpu/docs/images/codesize1.PNG create mode 100644 zpu/docs/images/codesize2.PNG create mode 100644 zpu/docs/images/ecos.gif create mode 100644 zpu/docs/images/elizadebug1.PNG create mode 100644 zpu/docs/images/elizadebug2.PNG delete mode 100644 zpu/roadshow/roadshow/codesize/index.html delete mode 100644 zpu/roadshow/roadshow/ecos/index.html delete mode 100644 zpu/roadshow/roadshow/pics/GCC_logo.png delete mode 100644 zpu/roadshow/roadshow/pics/codesize1.PNG delete mode 100644 zpu/roadshow/roadshow/pics/codesize2.PNG delete mode 100644 zpu/roadshow/roadshow/pics/ecos.gif delete mode 100644 zpu/roadshow/roadshow/pics/elizadebug1.PNG delete mode 100644 zpu/roadshow/roadshow/pics/elizadebug2.PNG diff --git a/zpu/docs/images/GCC_logo.png b/zpu/docs/images/GCC_logo.png new file mode 100644 index 0000000..7b3435f Binary files /dev/null and b/zpu/docs/images/GCC_logo.png differ diff --git a/zpu/docs/images/codesize1.PNG b/zpu/docs/images/codesize1.PNG new file mode 100644 index 0000000..874ee9d Binary files /dev/null and b/zpu/docs/images/codesize1.PNG differ diff --git a/zpu/docs/images/codesize2.PNG b/zpu/docs/images/codesize2.PNG new file mode 100644 index 0000000..caa8c14 Binary files /dev/null and b/zpu/docs/images/codesize2.PNG differ diff --git a/zpu/docs/images/ecos.gif b/zpu/docs/images/ecos.gif new file mode 100644 index 0000000..3dad40c Binary files /dev/null and b/zpu/docs/images/ecos.gif differ diff --git a/zpu/docs/images/elizadebug1.PNG b/zpu/docs/images/elizadebug1.PNG new file mode 100644 index 0000000..f3c3f5f Binary files /dev/null and b/zpu/docs/images/elizadebug1.PNG differ diff --git a/zpu/docs/images/elizadebug2.PNG b/zpu/docs/images/elizadebug2.PNG new file mode 100644 index 0000000..13f046e Binary files /dev/null and b/zpu/docs/images/elizadebug2.PNG differ diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index c7e20bc..280cda3 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -15,7 +15,12 @@
        12. Wishbone
        13. About zpu_core_small.vhd
        14. About zpu_core.vhd +
        15. Optimizing for code size +
        16. Installing eCos build tools + +
        17. Next generation ZPU + @@ -1457,6 +1462,204 @@ accessed through this memory interface.

          It performs better(despite having less memory bandwidth than zpu_core_small.vhd) since it implements many more instructions. +

          Compiling hello world program with the ZPU GCC toolchain

          +The ZPU comes with a standard GCC toolchain and an instruction set simulator. This allows compiling, running & debugging simple test programs. The Simulator has +some very basic peripherals defined: counter, timer interrupt and a debug output port. +

          Installation

          +
            +
          1. Install Cygwin. http://www.cygwin.com +
          2. Start Cygwin bash +
          3. unzip zputoolchain.zip +
          4. Add install/bin from zputoolchain.zip to PATH.
            +export PATH=$PATH:/install/bin +
          +

          Hello world example

          +The ZPU toolchain comes with newlib & libstdc++ support which means that many C/C++ programs can be compiled without modification. +

          + +zpu-elf-gcc -Os -zeta hello.c -o hello.elf -Wl,--relax -Wl,--gc-sections
          +zpu-elf-size hello.elf
          +           + +           +

          Optimizing for code size

          +The ZPU toolchain produces highly compact code. +
            +
          1. Since the ZPU GCC toolchain supports standard ANSI C, it is easy to stumble across +functionality that takes up a lot of space. E.g. the standard printf() function is a beast. Some compilers drop e.g. floating point support +from the printf() function and thus boast a "smaller" printf() when in fact they have a non-standard printf(). newlib has a standard printf() function +and an alternative iprintf() function that works only on integers. +
          2. The ZPU ships with default startup code that works across various configurations of the ZPU, so be warned that there is some overhead that will +not occurr in the final application(anywhere between 1-4kBytes). +
          3. Compilation and linker options matter. The ZPU benefits greatly from the "-Wl,--relax -Wl,--gc-sections" options which is not used by +all architectures(e.g. GCC ARM does not implement/need -Wl,--relax). +
          +

          Small code example

          + +zpu-elf-gcc -Os -abel smallstd.c -o smallstd.elf -Wl,--relax -Wl,--gc-sections
          +zpu-elf-size small.elf
          +
          +$ zpu-elf-size small.elf
          + text data bss dec hex filename
          + 2845 952 36 3833 ef9 small.elf
          +
          +           + +

          Even smaller code example

          +If the ZPU implements the optional instructions, the RAM overhead can be reduced significantly. +

          + +zpu-elf-gcc -Os -abel crt0_phi.S small.c -o small.elf -Wl,--relax -Wl,--gc-sections -nostdlib
          +zpu-elf-size small.elf
          +
          +$ zpu-elf-size small.elf
          + text data bss dec hex filename
          + 56 8 0 64 40 small.elf
          +
          +           + + + +           +

          Installing eCos build tools

          + +tar -xjvf ecossnapshot.tar.bz2
          +tar -xjvf repository.tar.bz2
          +tar -xjvf ecostools.tar.bz2
          +# run this every time you open the shell
          +export PATH=$PATH:`pwd`/ecos-install
          +export ECOS_REPOSITORY=`pwd`/ecos/packages:`pwd`/repository
          +           +

          Compiling eCos tests

          + +ecosconfig new zeta default
          +ecosconfig tree
          +make
          +cd kernel/current
          +make tests
          +           + +

          Code size ZPU

          + +$ zpu-elf-size *
          + text data bss dec hex filename
          + 15761 1504 12060 29325 728d bin_sem0
          + 16907 1512 14436 32855 8057 bin_sem1
          + 17105 1524 30032 48661 be15 bin_sem2
          + 17186 1512 14436 33134 816e bin_sem3
          + 18986 1500 12036 32522 7f0a clock0
          + 15812 1504 13236 30552 7758 clock1
          + 25095 1972 13224 40291 9d63 clockcnv
          + 16437 1500 13224 31161 79b9 clocktruth
          + 15762 1504 12060 29326 728e cnt_sem0
          + 17124 1512 14436 33072 8130 cnt_sem1
          + 35947 1564 22512 60023 ea77 dhrystone
          + 16428 1500 13228 31156 79b4 except1
          + 15751 1504 12052 29307 727b flag0
          + 19145 1512 15624 36281 8db9 flag1
          + 20053 1516 102908 124477 1e63d fptest
          + 15998 1496 12092 29586 7392 intr0
          + 16080 1496 12200 29776 7450 kalarm0
          + 15327 1496 12036 28859 70bb kcache1
          + 15549 1496 13224 30269 763d kcache2
          + 18291 1500 12260 32051 7d33 kclock0
          + 16231 1500 13232 30963 78f3 kclock1
          + 16572 1496 13228 31296 7a40 kexcept1
          + 15618 1496 12060 29174 71f6 kflag0
          + 19287 1500 15624 36411 8e3b kflag1
          + 16887 1516 15628 34031 84ef kill
          + 16186 1496 12128 29810 7472 kintr0
          + 19724 1504 14516 35744 8ba0 klock
          + 18283 1500 14592 34375 8647 kmbox1
          + 15539 1496 12064 29099 71ab kmutex0
          + 16524 1504 15664 33692 839c kmutex1
          + 18272 1712 20348 40332 9d8c kmutex3
          + 18682 1608 20352 40642 9ec2 kmutex4
          + 15619 1496 14412 31527 7b27 ksched1
          + 15567 1496 12060 29123 71c3 ksem0
          + 17063 1500 14436 32999 80e7 ksem1
          + 15504 1496 13228 30228 7614 kthread0
          + 16167 1496 14412 32075 7d4b kthread1
          + 18281 1512 14580 34373 8645 mbox1
          + 20611 1508 14940 37059 90c3 mqueue1
          + 15672 1504 12064 29240 7238 mutex0
          + 16678 1516 15664 33858 8442 mutex1
          + 17694 1508 16868 36070 8ce6 mutex2
          + 18203 1720 20344 40267 9d4b mutex3
          + 16352 1508 14428 32288 7e20 release
          + 15890 1500 14412 31802 7c3a sched1
          + 44196 1612 286332 332140 5116c stress_threads
          + 17891 1524 16864 36279 8db7 sync2
          + 16943 1512 15644 34099 8533 sync3
          + 15467 1496 13064 30027 754b thread0
          + 16134 1496 14420 32050 7d32 thread1
          + 17560 1512 15636 34708 8794 thread2
          + 16279 1500 24028 41807 a34f thread_gdb
          + 17051 1504 20376 38931 9813 timeslice
          + 17146 1504 21564 40214 9d16 timeslice2
          + 37313 1512 422380 461205 70995 tm_basic
          +           +

          Code size ARM (non-thumb)

          +Thumb does not compile out of the box w/AT91 EB40a for which this test was made.

          + +$ arm-elf-size *
          + text data bss dec hex filename
          + 25204 692 16976 42872 a778 bin_sem0
          + 26644 700 22096 49440 c120 bin_sem1
          + 26996 712 55584 83292 1455c bin_sem2
          + 27008 700 22100 49808 c290 bin_sem3
          + 28992 688 16944 46624 b620 clock0
          + 25456 692 19532 45680 b270 clock1
          + 34572 1160 19520 55252 d7d4 clockcnv
          + 26224 688 19508 46420 b554 clocktruth
          + 25204 692 16976 42872 a778 cnt_sem0
          + 26888 700 22108 49696 c220 cnt_sem1
          + 44180 752 27416 72348 11a9c dhrystone
          + 26088 688 19520 46296 b4d8 except1
          + 25236 692 16968 42896 a790 flag0
          + 29532 700 24668 54900 d674 flag1
          + 29508 704 109652 139864 22258 fptest
          + 25932 684 17016 43632 aa70 intr0
          + 25824 684 17112 43620 aa64 kalarm0
          + 24728 684 16956 42368 a580 kcache1
          + 25168 684 19512 45364 b134 kcache2
          + 28112 688 17168 45968 b390 kclock0
          + 25976 688 19524 46188 b46c kclock1
          + 26372 684 19512 46568 b5e8 kexcept1
          + 25140 684 16968 42792 a728 kflag0
          + 29824 688 24660 55172 d784 kflag1
          + 26896 704 24656 52256 cc20 kill
          + 26088 684 17028 43800 ab18 kintr0
          + 30812 692 22176 53680 d1b0 klock
          + 28504 688 22260 51452 c8fc kmbox1
          + 24984 684 16984 42652 a69c kmutex0
          + 26504 692 24704 51900 cabc kmutex1
          + 28792 900 34892 64584 fc48 kmutex3
          + 29264 796 34896 64956 fdbc kmutex4
          + 25240 684 22084 48008 bb88 ksched1
          + 25044 684 16968 42696 a6c8 ksem0
          + 26988 688 22100 49776 c270 ksem1
          + 25028 684 19512 45224 b0a8 kthread0
          + 25996 684 22080 48760 be78 kthread1
          + 28552 700 22252 51504 c930 mbox1
          + 31324 696 22612 54632 d568 mqueue1
          + 25108 692 16980 42780 a71c mutex0
          + 26464 704 24700 51868 ca9c mutex1
          + 27624 696 27280 55600 d930 mutex2
          + 28596 908 34884 64388 fb84 mutex3
          + 26156 696 22100 48952 bf38 release
          + 25460 688 22084 48232 bc68 sched1
          + 56356 828 45892 103076 192a4 stress_threads
          + 27900 712 27288 55900 da5c sync2
          + 26760 700 24692 52152 cbb8 sync3
          + 24924 684 19356 44964 afa4 thread0
          + 25868 684 22084 48636 bdfc thread1
          + 27452 700 24680 52832 ce60 thread2
          + 26136 688 42704 69528 10f98 thread_gdb
          + 27212 692 34916 62820 f564 timeslice
          + 52728 700 123332 176760 2b278 tm_basic
          +           +           diff --git a/zpu/roadshow/roadshow/codesize/index.html b/zpu/roadshow/roadshow/codesize/index.html deleted file mode 100644 index 3f61b4e..0000000 --- a/zpu/roadshow/roadshow/codesize/index.html +++ /dev/null @@ -1,58 +0,0 @@ - - -

          Compiling hello world program with the ZPU GCC toolchain

          -The ZPU comes with a standard GCC toolchain and an instruction set simulator. This allows compiling, running & debugging simple test programs. The Simulator has -some very basic peripherals defined: counter, timer interrupt and a debug output port. -

          Installation

          -
            -
          1. Install Cygwin. http://www.cygwin.com -
          2. Start Cygwin bash -
          3. unzip zputoolchain.zip -
          4. Add install/bin from zputoolchain.zip to PATH.
            -export PATH=$PATH:/install/bin -
          -

          Hello world example

          -The ZPU toolchain comes with newlib & libstdc++ support which means that many C/C++ programs can be compiled without modification. -

          - -zpu-elf-gcc -Os -zeta hello.c -o hello.elf -Wl,--relax -Wl,--gc-sections
          -zpu-elf-size hello.elf
          -           -

          Optimizing for size

          -The ZPU toolchain produces highly compact code. -
            -
          1. Since the ZPU GCC toolchain supports standard ANSI C, it is easy to stumble across -functionality that takes up a lot of space. E.g. the standard printf() function is a beast. Some compilers drop e.g. floating point support -from the printf() function and thus boast a "smaller" printf() when in fact they have a non-standard printf(). newlib has a standard printf() function -and an alternative iprintf() function that works only on integers. -
          2. The ZPU ships with default startup code that works across various configurations of the ZPU, so be warned that there is some overhead that will -not occurr in the final application(anywhere between 1-4kBytes). -
          3. Compilation and linker options matter. The ZPU benefits greatly from the "-Wl,--relax -Wl,--gc-sections" options which is not used by -all architectures(e.g. GCC ARM does not implement/need -Wl,--relax). -
          -

          Small code example

          - -zpu-elf-gcc -Os -abel smallstd.c -o smallstd.elf -Wl,--relax -Wl,--gc-sections
          -zpu-elf-size small.elf
          -
          -$ zpu-elf-size small.elf
          - text data bss dec hex filename
          - 2845 952 36 3833 ef9 small.elf
          -
          -           - -

          Even smaller code example

          -If the ZPU implements the optional instructions, the RAM overhead can be reduced significantly. -

          - -zpu-elf-gcc -Os -abel crt0_phi.S small.c -o small.elf -Wl,--relax -Wl,--gc-sections -nostdlib
          -zpu-elf-size small.elf
          -
          -$ zpu-elf-size small.elf
          - text data bss dec hex filename
          - 56 8 0 64 40 small.elf
          -
          -           - - - diff --git a/zpu/roadshow/roadshow/ecos/index.html b/zpu/roadshow/roadshow/ecos/index.html deleted file mode 100644 index 5245459..0000000 --- a/zpu/roadshow/roadshow/ecos/index.html +++ /dev/null @@ -1,145 +0,0 @@ - - -

          Installing eCos build tools

          - -tar -xjvf ecossnapshot.tar.bz2
          -tar -xjvf repository.tar.bz2
          -tar -xjvf ecostools.tar.bz2
          -# run this every time you open the shell
          -export PATH=$PATH:`pwd`/ecos-install
          -export ECOS_REPOSITORY=`pwd`/ecos/packages:`pwd`/repository
          -           -

          Compiling eCos tests

          - -ecosconfig new zeta default
          -ecosconfig tree
          -make
          -cd kernel/current
          -make tests
          -           - -

          Code size ZPU

          - -$ zpu-elf-size *
          - text data bss dec hex filename
          - 15761 1504 12060 29325 728d bin_sem0
          - 16907 1512 14436 32855 8057 bin_sem1
          - 17105 1524 30032 48661 be15 bin_sem2
          - 17186 1512 14436 33134 816e bin_sem3
          - 18986 1500 12036 32522 7f0a clock0
          - 15812 1504 13236 30552 7758 clock1
          - 25095 1972 13224 40291 9d63 clockcnv
          - 16437 1500 13224 31161 79b9 clocktruth
          - 15762 1504 12060 29326 728e cnt_sem0
          - 17124 1512 14436 33072 8130 cnt_sem1
          - 35947 1564 22512 60023 ea77 dhrystone
          - 16428 1500 13228 31156 79b4 except1
          - 15751 1504 12052 29307 727b flag0
          - 19145 1512 15624 36281 8db9 flag1
          - 20053 1516 102908 124477 1e63d fptest
          - 15998 1496 12092 29586 7392 intr0
          - 16080 1496 12200 29776 7450 kalarm0
          - 15327 1496 12036 28859 70bb kcache1
          - 15549 1496 13224 30269 763d kcache2
          - 18291 1500 12260 32051 7d33 kclock0
          - 16231 1500 13232 30963 78f3 kclock1
          - 16572 1496 13228 31296 7a40 kexcept1
          - 15618 1496 12060 29174 71f6 kflag0
          - 19287 1500 15624 36411 8e3b kflag1
          - 16887 1516 15628 34031 84ef kill
          - 16186 1496 12128 29810 7472 kintr0
          - 19724 1504 14516 35744 8ba0 klock
          - 18283 1500 14592 34375 8647 kmbox1
          - 15539 1496 12064 29099 71ab kmutex0
          - 16524 1504 15664 33692 839c kmutex1
          - 18272 1712 20348 40332 9d8c kmutex3
          - 18682 1608 20352 40642 9ec2 kmutex4
          - 15619 1496 14412 31527 7b27 ksched1
          - 15567 1496 12060 29123 71c3 ksem0
          - 17063 1500 14436 32999 80e7 ksem1
          - 15504 1496 13228 30228 7614 kthread0
          - 16167 1496 14412 32075 7d4b kthread1
          - 18281 1512 14580 34373 8645 mbox1
          - 20611 1508 14940 37059 90c3 mqueue1
          - 15672 1504 12064 29240 7238 mutex0
          - 16678 1516 15664 33858 8442 mutex1
          - 17694 1508 16868 36070 8ce6 mutex2
          - 18203 1720 20344 40267 9d4b mutex3
          - 16352 1508 14428 32288 7e20 release
          - 15890 1500 14412 31802 7c3a sched1
          - 44196 1612 286332 332140 5116c stress_threads
          - 17891 1524 16864 36279 8db7 sync2
          - 16943 1512 15644 34099 8533 sync3
          - 15467 1496 13064 30027 754b thread0
          - 16134 1496 14420 32050 7d32 thread1
          - 17560 1512 15636 34708 8794 thread2
          - 16279 1500 24028 41807 a34f thread_gdb
          - 17051 1504 20376 38931 9813 timeslice
          - 17146 1504 21564 40214 9d16 timeslice2
          - 37313 1512 422380 461205 70995 tm_basic
          -           -

          Code size ARM (non-thumb)

          -Thumb does not compile out of the box w/AT91 EB40a for which this test was made.

          - -$ arm-elf-size *
          - text data bss dec hex filename
          - 25204 692 16976 42872 a778 bin_sem0
          - 26644 700 22096 49440 c120 bin_sem1
          - 26996 712 55584 83292 1455c bin_sem2
          - 27008 700 22100 49808 c290 bin_sem3
          - 28992 688 16944 46624 b620 clock0
          - 25456 692 19532 45680 b270 clock1
          - 34572 1160 19520 55252 d7d4 clockcnv
          - 26224 688 19508 46420 b554 clocktruth
          - 25204 692 16976 42872 a778 cnt_sem0
          - 26888 700 22108 49696 c220 cnt_sem1
          - 44180 752 27416 72348 11a9c dhrystone
          - 26088 688 19520 46296 b4d8 except1
          - 25236 692 16968 42896 a790 flag0
          - 29532 700 24668 54900 d674 flag1
          - 29508 704 109652 139864 22258 fptest
          - 25932 684 17016 43632 aa70 intr0
          - 25824 684 17112 43620 aa64 kalarm0
          - 24728 684 16956 42368 a580 kcache1
          - 25168 684 19512 45364 b134 kcache2
          - 28112 688 17168 45968 b390 kclock0
          - 25976 688 19524 46188 b46c kclock1
          - 26372 684 19512 46568 b5e8 kexcept1
          - 25140 684 16968 42792 a728 kflag0
          - 29824 688 24660 55172 d784 kflag1
          - 26896 704 24656 52256 cc20 kill
          - 26088 684 17028 43800 ab18 kintr0
          - 30812 692 22176 53680 d1b0 klock
          - 28504 688 22260 51452 c8fc kmbox1
          - 24984 684 16984 42652 a69c kmutex0
          - 26504 692 24704 51900 cabc kmutex1
          - 28792 900 34892 64584 fc48 kmutex3
          - 29264 796 34896 64956 fdbc kmutex4
          - 25240 684 22084 48008 bb88 ksched1
          - 25044 684 16968 42696 a6c8 ksem0
          - 26988 688 22100 49776 c270 ksem1
          - 25028 684 19512 45224 b0a8 kthread0
          - 25996 684 22080 48760 be78 kthread1
          - 28552 700 22252 51504 c930 mbox1
          - 31324 696 22612 54632 d568 mqueue1
          - 25108 692 16980 42780 a71c mutex0
          - 26464 704 24700 51868 ca9c mutex1
          - 27624 696 27280 55600 d930 mutex2
          - 28596 908 34884 64388 fb84 mutex3
          - 26156 696 22100 48952 bf38 release
          - 25460 688 22084 48232 bc68 sched1
          - 56356 828 45892 103076 192a4 stress_threads
          - 27900 712 27288 55900 da5c sync2
          - 26760 700 24692 52152 cbb8 sync3
          - 24924 684 19356 44964 afa4 thread0
          - 25868 684 22084 48636 bdfc thread1
          - 27452 700 24680 52832 ce60 thread2
          - 26136 688 42704 69528 10f98 thread_gdb
          - 27212 692 34916 62820 f564 timeslice
          - 52728 700 123332 176760 2b278 tm_basic
          -           - - - - - diff --git a/zpu/roadshow/roadshow/pics/GCC_logo.png b/zpu/roadshow/roadshow/pics/GCC_logo.png deleted file mode 100644 index 7b3435f..0000000 Binary files a/zpu/roadshow/roadshow/pics/GCC_logo.png and /dev/null differ diff --git a/zpu/roadshow/roadshow/pics/codesize1.PNG b/zpu/roadshow/roadshow/pics/codesize1.PNG deleted file mode 100644 index 874ee9d..0000000 Binary files a/zpu/roadshow/roadshow/pics/codesize1.PNG and /dev/null differ diff --git a/zpu/roadshow/roadshow/pics/codesize2.PNG b/zpu/roadshow/roadshow/pics/codesize2.PNG deleted file mode 100644 index caa8c14..0000000 Binary files a/zpu/roadshow/roadshow/pics/codesize2.PNG and /dev/null differ diff --git a/zpu/roadshow/roadshow/pics/ecos.gif b/zpu/roadshow/roadshow/pics/ecos.gif deleted file mode 100644 index 3dad40c..0000000 Binary files a/zpu/roadshow/roadshow/pics/ecos.gif and /dev/null differ diff --git a/zpu/roadshow/roadshow/pics/elizadebug1.PNG b/zpu/roadshow/roadshow/pics/elizadebug1.PNG deleted file mode 100644 index f3c3f5f..0000000 Binary files a/zpu/roadshow/roadshow/pics/elizadebug1.PNG and /dev/null differ diff --git a/zpu/roadshow/roadshow/pics/elizadebug2.PNG b/zpu/roadshow/roadshow/pics/elizadebug2.PNG deleted file mode 100644 index 13f046e..0000000 Binary files a/zpu/roadshow/roadshow/pics/elizadebug2.PNG and /dev/null differ -- cgit v1.1 From 6f3db230ca9d2e32df61dbd6137ea963de630629 Mon Sep 17 00:00:00 2001 From: oharboe Date: Fri, 22 Aug 2008 13:15:21 +0000 Subject: added uart section --- zpu/docs/zpu_arch.html | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index 280cda3..5d7fc5e 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -12,6 +12,7 @@

        18. Memory map
        19. Interrupts
        20. Speeding up the ZPU +
        21. Debug channel / UART
        22. Wishbone
        23. About zpu_core_small.vhd
        24. About zpu_core.vhd @@ -1040,7 +1041,7 @@ while developing the ZPU.
        @@ -1066,7 +1067,7 @@ while developing the ZPU. @@ -1160,7 +1161,7 @@ while developing the ZPU.

        Bit [31:1] Not used

        Bit - [0] UART RX interrupt enable

        + [0] Debug channel / UART RX interrupt enable

        0 Interrupt disable

        1 Interrupt @@ -1182,7 +1183,7 @@ while developing the ZPU.

        Bit [31:1] Not used

        Bit - [0] UART RX interrupt pending (Read)

        + [0] Debug channel / UART RX interrupt pending (Read)

        0 No interrupt pending

        1 Interrupt @@ -1455,6 +1456,25 @@ Achieving above 50-100 DMIPS with the current ZPU architecture is probably a non-starter and a more conventional RISC design makes more sense here.

        The unique advantages of the ZPU is size in terms of HDL & code size. + +

        Debug channel / UART

        +All self respecting embedded projects should have a debug channel +to print stuff to. Typically this is a standard RS232 or UART, but +it can also be something more exotic like a DCC JTAG channel. +

        +The point is that characters(bytes) are sent to/from the ZPU +via some terminal. +

        +The ZPU defines in the memory map a UART / debug channel. This +should be implemented by some suitable debug channel for +the device in which the ZPU is implemented. +

        +www.opencores.org has several UART implementations. This is one +of the simpler ones: + + +http://www.opencores.org/projects.cgi/web/uart/overview +

        About zpu_core.vhd

        The zpu_core.vhd has a single port memory interface. All data, code and IO is -- cgit v1.1 From 873e0043c4c132ff16d90fa6bf4196674e8482ad Mon Sep 17 00:00:00 2001 From: oharboe Date: Fri, 22 Aug 2008 19:50:10 +0000 Subject: more doc work in progress --- zpu/docs/images/compile.PNG | Bin 0 -> 17735 bytes zpu/docs/images/simulator.PNG | Bin 0 -> 42848 bytes zpu/docs/images/simulator2.PNG | Bin 0 -> 42623 bytes zpu/docs/images/simulator3.PNG | Bin 0 -> 69583 bytes zpu/docs/zpu_arch.html | 120 +++++++++++++++++++++++++++++++++++++++++ 5 files changed, 120 insertions(+) create mode 100644 zpu/docs/images/compile.PNG create mode 100644 zpu/docs/images/simulator.PNG create mode 100644 zpu/docs/images/simulator2.PNG create mode 100644 zpu/docs/images/simulator3.PNG diff --git a/zpu/docs/images/compile.PNG b/zpu/docs/images/compile.PNG new file mode 100644 index 0000000..8a00c07 Binary files /dev/null and b/zpu/docs/images/compile.PNG differ diff --git a/zpu/docs/images/simulator.PNG b/zpu/docs/images/simulator.PNG new file mode 100644 index 0000000..9765366 Binary files /dev/null and b/zpu/docs/images/simulator.PNG differ diff --git a/zpu/docs/images/simulator2.PNG b/zpu/docs/images/simulator2.PNG new file mode 100644 index 0000000..070084e Binary files /dev/null and b/zpu/docs/images/simulator2.PNG differ diff --git a/zpu/docs/images/simulator3.PNG b/zpu/docs/images/simulator3.PNG new file mode 100644 index 0000000..34e0540 Binary files /dev/null and b/zpu/docs/images/simulator3.PNG differ diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index 5d7fc5e..968ae34 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -2,6 +2,10 @@

        Index

         + +

        The worlds smallest 32 bit CPU with GCC toolchain +

        +

        This CPU is finding a new home at www.opencores.org, please +contact me if you are willing and able to help in shaping up the +www.opencores.org pages. +

        +

        The HDL, GCC toolchain and eCos HAL are actually done. Mainly I +could need a hand with writing up docs/web pages/examples/bug +reports.

        +

        The ZPU has a BSD license for the HDL and GPL for the rest(source +files are sadly out of date here, patches gladly accepted!). This +allows deployments to implement any version of the ZPU they want +without running into commercial problems, but if improvements are +done to the architecture as such, then they need to be contributed +back. +

        +

        One strength of the ZPU is that it is tiny and therefore easy to +implement from scratch to suit specialized needs and optimizations.

        +

        Currently there exists some pages at http://www.zylin.com/zpu.htm +that explains about the ZPU. According to OpenCores policy this +information should be moved to www.opencores.org. Patches gratefully +accepted to do so!

        +

        Per Jan 1. 2008, Zylin has the Copyright for the ZPU, i.e. Zylin +is free to decide that the ZPU shall have a BSD license for HDL + GPL +for the rest.

        +

        Sincerley,

        +

        Øyvind Harboe
        Zylin AS +

        +

        Features +

        +
          +

        • Small size: 442 LUT @ 95 MHz after + P&R w/32 bit datapath Xilinx XC3S400 +

          +

        • Wishbone +

          +

        • Code size 80% of ARM Thumb +

          +

        • GCC toolchain(GDB, newlib, + libstdc+) +

          +

        • eCos embedded operating system support

          +
        +

        Survey +

        +

        Please take the time to fill in this short survey so we can gather +information about where the ZPU can be the most useful:

        +

        http://www.zylin.com/zpusurvey.html

        +

        Status +

        +
          +

        • HDL works +

          +

        • GCC toolchain works +

          +

        • eCos HAL works, but could be less + RAM hungry +

          +

        • The main problem at this point is + not usage of the CPU, but that the documentation/CVS layout needs + attention +

          +

        • Needs GDB stub support in eCos +

          +

        • Could do with a Verilog implementation(ca. 600 lines to + translate)

          +
        +

        Simulator +

        +

        The ZPU simulator is integrated into the Zylin Embedded CDT plugin +to ease debugging of ZPU applications:

        +

        http://www.zylin.com/embeddedcdt.html

        +

        The ZPU simulator has many features besides debugging an +application:

        +
          +

        • taking output from simulation(e.g. + ModelSim) and matching that against the Java simulator, thus making + it much easier to debug HDL implementations and also getting real + world timing information +

          +

        • can generate gprof output +

          +

        • generate various statistics +

          +
        +

        The plugin is still pretty rough around the edges, and needs to +get GUI support for enabling the ModelSim trace input feature.

        +


        Compiling +ZPU application

        +


        Setting +up the simulator

        +


        Choosing +ZPU executable

        +


        Debug +session

        +


        +

        +

        Getting started - FPGA

        The simplest version of the ZPU uses BRAM. When getting accustomed to the ZPU, a BRAM ZPU with a UART @@ -1740,6 +1843,23 @@ This ZPU could run a TCP/IP stack with relevant performance to compete with stripped down ARM7 type systems. +         +

        Download source code

        +

        +

        The simplest way to get the ZPU HDL source and tools is to check +it out from CVS:

        +

        cvs -d :pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous co +zpu/zpu

        +

        Start by reading zpu/zpu/hdl/index.html

        +         +

        Creating a patch

        +


        If you have an changes, modify the files locally, create a +patch and email it to         zylin-zpu mailing list. Attach it +as an uncompressed .txt file:

        +

        cd zpu
        cvs diff -upN . > mypatch.txt

        + +

        Getting help - mailing list

        +The place to get help is the         zylin-zpu mailing list \ No newline at end of file -- cgit v1.1 From 398017e921a585cbd8785e21b49155832151fc0f Mon Sep 17 00:00:00 2001 From: oharboe Date: Mon, 25 Aug 2008 17:52:52 +0000 Subject: 2008-08-25 Salvador Eduardo Tropea * Fix typo in zpu_arch.html w.r.t. ZPU UART/Debug channel --- zpu/ChangeLog | 2 ++ zpu/docs/zpu_arch.html | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/zpu/ChangeLog b/zpu/ChangeLog index 02adb2c..fd0c8ac 100644 --- a/zpu/ChangeLog +++ b/zpu/ChangeLog @@ -1,3 +1,5 @@ +2008-08-25 Salvador Eduardo Tropea + * Fix typo in zpu_arch.html w.r.t. ZPU UART/Debug channel 2008-08-18 Øyvind Harboe * duplicated crt0.s and some other stuff from libgloss into sw/startup. This makes it easier to tinker w/startup code. diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index 968ae34..8230c69 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -1179,9 +1179,9 @@ while developing the ZPU. [31:9] Not used

        Bit [8] RX buffer data valid

        -

        0 TX +

        0 RX buffer not valid

        -

        1 TX +

        1 RX buffer valid

        Bit [7:0] RX byte (when valid)

        -- cgit v1.1 From 1427b02f2acf83073fd717a7ab47d56fd9b48e64 Mon Sep 17 00:00:00 2001 From: oharboe Date: Mon, 25 Aug 2008 18:00:26 +0000 Subject: improved instructions on creating a patch --- zpu/ChangeLog | 2 +- zpu/docs/zpu_arch.html | 21 +++++++++++++++++---- 2 files changed, 18 insertions(+), 5 deletions(-) diff --git a/zpu/ChangeLog b/zpu/ChangeLog index fd0c8ac..625573e 100644 --- a/zpu/ChangeLog +++ b/zpu/ChangeLog @@ -1,5 +1,5 @@ 2008-08-25 Salvador Eduardo Tropea - * Fix typo in zpu_arch.html w.r.t. ZPU UART/Debug channel + * zpu/docs/arch_html: Fix typo in zpu_arch.html w.r.t. ZPU UART/Debug channel 2008-08-18 Øyvind Harboe * duplicated crt0.s and some other stuff from libgloss into sw/startup. This makes it easier to tinker w/startup code. diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index 8230c69..832f822 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -1,5 +1,10 @@ +

        Latest version of this document

        +This is a snapshot of the zpu_arch.html document in CVS. Please check out +the latest version from CVS to get the latest version. +

        +$Id: zpu_arch.html,v 1.23 2008/08/25 18:00:27 oharboe Exp $

        Index

        ZPU - UART to ARM7 TX

        + Debug channel / UART to ARM7 TX

        NOTE! ZPU side

        ZPU - UART to ARM7 RX

        + Debug channel / UART to ARM7 RX

        NOTE! ZPU side
        + + + + + + + + + + + + + + + + +
        SymbolDirectionBit widthPurpose
        adrInput24Address where to read from SPI
        dat_oOutput32Data read from SPI
        clkInput1Input clock. Used for both interface and SPI
        ceInput1Chip Enable
        rstInput1Asynchronous reset
        ackOutput1Data valid ACK
        SPI_CLKOutput1SPI output clock
        SPI_MOSIOutput1SPI output data from controller to chip
        SPI_MISOInput1SPI input data from chip to controller
        SPI_SELNOutput1SPI nSEL (deselect, active low) signal
        + + + +

        License

        +The Verilog implementation is released under BSD license. See the file itself for more licensing details. + +

        Dowload

        +Download the Verilog code here: spi_controller.v + +

        Troubleshooting

        +The current implementation is timed and optimized for myself. Your parameters might not be the same +as those I defaulted, so read the code carefully. If you have any issue let me know. + + + +

        Zealot: Implementing in FPGAs

        -- cgit v1.1 From 9c7083205eed686d65dad3420b44838685a73875 Mon Sep 17 00:00:00 2001 From: oharboe Date: Tue, 23 Sep 2008 11:41:26 +0000 Subject: small ZPU --- zpu/hdl/zealot/helpers/zpu_small1.vhdl | 136 +++++++++++++++++++++++++++++++++ 1 file changed, 136 insertions(+) create mode 100644 zpu/hdl/zealot/helpers/zpu_small1.vhdl diff --git a/zpu/hdl/zealot/helpers/zpu_small1.vhdl b/zpu/hdl/zealot/helpers/zpu_small1.vhdl new file mode 100644 index 0000000..13dd485 --- /dev/null +++ b/zpu/hdl/zealot/helpers/zpu_small1.vhdl @@ -0,0 +1,136 @@ +------------------------------------------------------------------------------ +---- ---- +---- ZPU Small + PHI I/O + BRAM ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- ZPU is a 32 bits small stack cpu. This is a helper that joins the ---- +---- small version, the PHI I/O basic layout and a program BRAM. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Salvador E. Tropea ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the BSD license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: ZPU_Small1(Structural) (Entity and architecture) ---- +---- File name: zpu_small1.vhdl ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: work ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- zpu.zpupkg ---- +---- work.zpu_memory ---- +---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: GHDL [Sokcho edition] (0.2x) ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library zpu; +use zpu.zpupkg.all; + +-- RAM declaration +library work; +use work.zpu_memory.all; + +entity ZPU_Small1 is + generic( + WORD_SIZE : natural:=32; -- 32 bits data path + D_CARE_VAL : std_logic:='0'; -- Fill value + CLK_FREQ : positive:=50; -- 50 MHz clock + BRATE : positive:=115200; -- RS232 baudrate + ADDR_W : natural:=16; -- 16 bits address space=64 kB, 32 kB I/O + BRAM_W : natural:=15); -- 15 bits RAM space=32 kB + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + break_o : out std_logic; -- Break executed + dbg_o : out zpu_dbgo_t; -- Debug info + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic); -- UART Rx +end entity ZPU_Small1; + +architecture Structural of ZPU_Small1 is + constant BYTE_BITS : integer:=WORD_SIZE/16; -- # of bits in a word that addresses bytes + constant IO_BIT : integer:=ADDR_W-1; -- Address bit to determine this is an I/O + constant BRDIVISOR : positive:=CLK_FREQ*1e6/BRATE/4; + + -- Program+data+stack BRAM + -- Port A + signal a_we : std_logic; + signal a_addr : unsigned(BRAM_W-1 downto BYTE_BITS); + signal a_write : unsigned(WORD_SIZE-1 downto 0); + signal a_read : unsigned(WORD_SIZE-1 downto 0); + -- Port B + signal b_we : std_logic; + signal b_addr : unsigned(BRAM_W-1 downto BYTE_BITS); + signal b_write : unsigned(WORD_SIZE-1 downto 0); + signal b_read : unsigned(WORD_SIZE-1 downto 0); + + -- I/O space + signal io_busy : std_logic; + signal io_write : unsigned(WORD_SIZE-1 downto 0); + signal io_read : unsigned(WORD_SIZE-1 downto 0); + signal io_addr : unsigned(ADDR_W-1 downto 0); + signal phi_addr : unsigned(2 downto 0); + signal io_we : std_logic; + signal io_re : std_logic; +begin + memory: DualPortRAM + generic map( + WORD_SIZE => WORD_SIZE, BYTE_BITS => BYTE_BITS, BRAM_W => BRAM_W) + port map( + clk_i => clk_i, + -- Port A + a_we_i => a_we, a_addr_i => a_addr, a_write_i => a_write, + a_read_o => a_read, + -- Port B + b_we_i => b_we, b_addr_i => b_addr, b_write_i => b_write, + b_read_o => b_read); + + -- I/O: Phi layout + io_map: ZPUPhiIO + generic map( + BRDIVISOR => BRDIVISOR, LOG_FILE => "zpu_small1_io.log") + port map( + clk_i => clk_i, reset_i => rst_i, busy_o => io_busy, we_i => io_we, + re_i => io_re, data_i => io_write, data_o => io_read, + addr_i => phi_addr, rs232_rx_i => rs232_rx_i, rs232_tx_o => rs232_tx_o, + br_clk_i => '1'); + phi_addr <= io_addr(4 downto 2); + + zpu : ZPUSmallCore + generic map( + WORD_SIZE => WORD_SIZE, ADDR_W => ADDR_W, MEM_W => BRAM_W, + D_CARE_VAL => D_CARE_VAL) + port map( + clk_i => clk_i, reset_i => rst_i, interrupt_i => '0', + break_o => break_o, dbg_o => dbg_o, + -- BRAM (text, data, bss and stack) + a_we_o => a_we, a_addr_o => a_addr, a_o => a_write, a_i => a_read, + b_we_o => b_we, b_addr_o => b_addr, b_o => b_write, b_i => b_read, + -- Memory mapped I/O + mem_busy_i => io_busy, data_i => io_read, data_o => io_write, + addr_o => io_addr, write_en_o => io_we, read_en_o => io_re); +end architecture Structural; -- Entity: ZPU_Small1 + -- cgit v1.1 From 07df0bc85fffae0e271cbad3fd43260b486baebc Mon Sep 17 00:00:00 2001 From: oharboe Date: Tue, 23 Sep 2008 19:19:08 +0000 Subject: =?UTF-8?q?=C1lvaro=20Lopes=20=20spi=20control?= =?UTF-8?q?ler?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- zpu/hdl/spi/spi_controller.v | 235 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 235 insertions(+) create mode 100644 zpu/hdl/spi/spi_controller.v diff --git a/zpu/hdl/spi/spi_controller.v b/zpu/hdl/spi/spi_controller.v new file mode 100644 index 0000000..b22f294 --- /dev/null +++ b/zpu/hdl/spi/spi_controller.v @@ -0,0 +1,235 @@ +/* + SPI flash read-only controller + + Copyright 2008 Álvaro Lopes + + Version: 1.3 + + The FreeBSD license + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above + copyright notice, this list of conditions and the following + disclaimer in the documentation and/or other materials + provided with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY + EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + Changelog: + + 1.3: Remove async reset from spi_data shift register + Fix indentation of code + + 1.2: Fix read count for sequential fetch + + 1.1: Move port types outside module declaration. + Fix state machine to handle clock stop + Remove err out report + Fix SPI_CLK generation. +*/ + +module spi_controller ( + clk, // Clock + rst, // Reset + ce, // Chip Enable + ack, // Acknowledge + + adr, // Address in + dat_o, // Data out + + SPI_MOSI, // Master Out/Slave In for SPI + SPI_MISO, // Master In/Slave Out for SPI + SPI_CLK, // SPI clock + SPI_SELN // SPI nSEL +); + +parameter Tp = 0; // Propagation delay - for simulation +parameter INIT_CLOCK_CYCLE_WAIT = 2; // Clock cycles to wait before init +parameter DESELECT_CYCLES = 3; // Clock cycles to wait after deselection - should give 100ns at least +parameter SPI_REGISTER_SIZE = 40; +parameter SPI_ADDRESS_SIZE = 24; + +input clk; +input rst; +input ce; +output reg ack; + +input [SPI_ADDRESS_SIZE-1:0] adr; +output reg [31:0] dat_o; + +output reg SPI_MOSI; +input SPI_MISO; +output SPI_CLK; +output reg SPI_SELN; + + +// FSM states +localparam SPI_STATE_WAIT = 7'b0000001, + SPI_STATE_IDLE = 7'b0000010, + SPI_STATE_WACK = 7'b0000100, + SPI_STATE_SEND = 7'b0001000, + SPI_STATE_BREAD = 7'b0010000, + SPI_STATE_READ = 7'b0100000, + SPI_STATE_WDES = 7'b1000000; + +// SPI commands +localparam SPI_CMD_READ_FAST = 8'b00001011; + + +// Shift register to hold command to be sent to SPI +reg [SPI_REGISTER_SIZE-1:0] spi_shift_register_out; + +integer spi_reg_count; + +reg [8:0] spi_read_count; +reg [7:0] spi_data; +reg [3:0] data_valid_window; +reg [SPI_REGISTER_SIZE-1:0] next_address; + +integer dsel_dly; +integer spi_init_count; +reg spi_start_count; +reg spi_enable_clock; // Enable SPI clock +reg [6:0] spi_state; // SPI state machine + +/* + SPI clock generation +*/ + +assign SPI_CLK = spi_enable_clock?~clk:1'b0; + +reg seq_read; // Sequential read in progress + +always @(posedge clk or posedge rst) +begin + if ( rst ) begin + spi_enable_clock <= #Tp 1'b0; + spi_state <= #Tp SPI_STATE_WAIT; + spi_init_count <= #Tp INIT_CLOCK_CYCLE_WAIT; + SPI_SELN <= #Tp 1'b1; + ack <= #Tp 1'b0; + spi_start_count <= #Tp 1'b0; + next_address <= #Tp 32'hFFFFFFFF; + end else begin + + case (spi_state) + SPI_STATE_WAIT: + begin + if ( spi_init_count == 0 ) begin + spi_state <= SPI_STATE_IDLE; + end else begin + spi_init_count <= #Tp spi_init_count - 1; + end + end + SPI_STATE_IDLE: + begin + + if ( ce ) begin + next_address <= { adr[SPI_ADDRESS_SIZE-1:2], 2'b0 } + 4; + seq_read = adr[SPI_ADDRESS_SIZE-1:2] == next_address[SPI_ADDRESS_SIZE-1:2]; + // Latch address (24 bit wordsize) + spi_shift_register_out <= #Tp { SPI_CMD_READ_FAST, adr[SPI_ADDRESS_SIZE-1:2], 2'b0, 8'b0 }; + + spi_enable_clock <= #Tp 1'b1; + + if ( seq_read ) begin + spi_state <= #Tp SPI_STATE_BREAD; + end else begin + SPI_SELN <= 1'b1 ; + spi_reg_count <= #Tp SPI_REGISTER_SIZE; + dsel_dly <= DESELECT_CYCLES; + spi_state <= #Tp SPI_STATE_WDES; + end + end + end + SPI_STATE_WACK: + begin + ack <= 1'b0; + spi_state <= SPI_STATE_IDLE; + end + SPI_STATE_SEND: + begin + + SPI_SELN <=#Tp 1'b0; + + if (spi_reg_count == 0) + begin + spi_state <= #Tp SPI_STATE_BREAD; + end else begin + SPI_MOSI <= #Tp spi_shift_register_out[SPI_REGISTER_SIZE-1]; + spi_shift_register_out <= #Tp { spi_shift_register_out[SPI_REGISTER_SIZE-2:0], 1'b0 }; + spi_reg_count <= #Tp spi_reg_count - 1; + end + end + SPI_STATE_BREAD: + begin + spi_start_count <= #Tp 1'b1; + spi_state <= #Tp SPI_STATE_READ; + end + SPI_STATE_READ: + begin + spi_start_count <= #Tp 1'b0; + + // Stop clock a bit earlier + if ( data_valid_window[3] && spi_read_count[1] ) + spi_enable_clock <= 1'b0; + + if (spi_read_count[0]) + begin + + dat_o <= #Tp { dat_o[23:0], spi_data }; + + if ( data_valid_window[3] ) begin + ack <= #Tp 1'b1; + spi_state <= #Tp SPI_STATE_WACK; + end + end + end + SPI_STATE_WDES: + begin + if ( dsel_dly == 0 ) + spi_state <= SPI_STATE_SEND; + else + dsel_dly <= dsel_dly -1; + end + endcase + end +end + +always @(posedge clk) +begin + if (spi_start_count) begin + spi_read_count <= 8'b01000000; + data_valid_window <= #Tp 5'b00001; + end else begin + if ( spi_read_count[0] ) begin + data_valid_window <= #Tp { data_valid_window[3:0], 1'b0 }; + end + spi_read_count <= #Tp { spi_read_count[0] ,spi_read_count[7:1] }; + end +end + +// SPI data shift register + +always @(negedge clk) +begin + spi_data <= #Tp { spi_data[6:0], SPI_MISO }; +end + +endmodule -- cgit v1.1 From 104c29feaeee40e94580b952b8cf793d54727612 Mon Sep 17 00:00:00 2001 From: oharboe Date: Fri, 10 Oct 2008 07:07:57 +0000 Subject: a few words about the ZY1000 ZPU JTAG debugger --- zpu/docs/zpu_arch.html | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index e7cf30c..7ddbea7 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -23,6 +23,7 @@ $id$
      31. Speeding up the ZPU
      32. Debug channel / UART
      33. Wishbone +
      34. JTAG/hardware debugger for GDB
      35. About zpu_core_small.vhd
      36. About zpu_core.vhd
      37. Zealot: Implementing in FPGAs @@ -1481,6 +1482,29 @@ of the ZPU, which differs slightly from +

        JTAG/hardware debugger for GDB

        +The Zylin         ZY1000 JTAG debugger supports +the ZPU. Contact Zylin for pricing and details. +

        +There are two debug modes in which the ZY1000 can operate: +

          +
        • Classic. Here the ZY1000 controls the CPU and examines the state. The ZY1000 has a built in +GDB server that GDB talks to. +
        • Small footprint. If there isn't enough space on the device for the ZPU *and* the JTAG +controller, then the ZY1000 can run the ZPU externally. The JTAG communication channel is +then used to peek/poke peripherals and inside the FPGA instead of the ZPU there is then +a JTAG controller that peeks and pokes the peripherals of the ZPU. There are advantages +and disadvantages of this approach: it may be unfamiliar to embedded developers and +the timing is different from the "real" ZPU(interrupts are delayed, execution speed +differse, etc.) On the other hand there are other things +which are simpler: much more RAM can be available for the ZPU during development, +better debug consoles(faster), additional peripheral(timers, etc.) is available. This +approach is somewhat unique to the ZPU as the ZPU is simple enough that it can be +implemented efficiently in this manner. +
        +

        Interrupts

        The ZPU supports interrupts. -- cgit v1.1 From 5a2b72d6bdf7bc47f9001304c557b205c77e38ee Mon Sep 17 00:00:00 2001 From: oharboe Date: Fri, 10 Oct 2008 09:43:44 +0000 Subject: dmips test app in example folder --- zpu/docs/zpu_arch.html | 14 + zpu/hdl/example/.cvsignore | 1 + zpu/hdl/example/bram_dmips.vhd | 6909 ++++++++++++++++++--------------------- zpu/hdl/example/simzpu_dmips.do | 29 + zpu/hdl/example/zpuromgen.exe | Bin 0 -> 10274 bytes 5 files changed, 3301 insertions(+), 3652 deletions(-) create mode 100644 zpu/hdl/example/simzpu_dmips.do create mode 100644 zpu/hdl/example/zpuromgen.exe diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index 7ddbea7..0c57cae 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -157,6 +157,20 @@ Obviously you must also connect the ZPU to the rest of your IO subsystem. IO is java -classpath ../simulator/zpusim.jar com.zylin.zpu.simulator.tools.MakeRam hello.bin >hello.bram
        +

        Build another test application for example simulation

        +Here is how to build a rom image for an application using the +zpu/example simulation files. +

        +cd zpu/roadshow/roadshow/dhrystone
        +sh build.sh
        +cd zpu/hdl/example
        +gcc zpuromgen.c
        +$ ./a
        +Usage: ./a binary_file
        +./a ../../roadshow/roadshow/dhrystone/dhrystone.bin >app.txt
        +

        +Copy and paste app.txt into helloworld.vhd. +

        Running example simulation

        The hdl/example directory has a simulation written for Xilinx WebPack ModelSim. From the ModelSim command prompt:
          diff --git a/zpu/hdl/example/.cvsignore b/zpu/hdl/example/.cvsignore index ab4e67c..8238018 100644 --- a/zpu/hdl/example/.cvsignore +++ b/zpu/hdl/example/.cvsignore @@ -1,2 +1,3 @@ work vsim.wlf +install diff --git a/zpu/hdl/example/bram_dmips.vhd b/zpu/hdl/example/bram_dmips.vhd index 53d9121..733560e 100644 --- a/zpu/hdl/example/bram_dmips.vhd +++ b/zpu/hdl/example/bram_dmips.vhd @@ -60,3658 +60,3263 @@ type ram_type is array(natural range 0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_ shared variable ram : ram_type := ( -0 => x"0b0b0b0b", -1 => x"80700b0b", -2 => x"80e2a40c", -3 => x"3a0b0b80", -4 => x"c6fc0400", -5 => x"00000000", -6 => x"00000000", -7 => x"00000000", -8 => x"80088408", -9 => x"88080b0b", -10 => x"80c7c32d", -11 => x"880c840c", -12 => x"800c0400", -13 => x"00000000", -14 => x"00000000", -15 => x"00000000", -16 => x"71fd0608", -17 => x"72830609", -18 => x"81058205", -19 => x"832b2a83", -20 => x"ffff0652", -21 => x"04000000", -22 => x"00000000", -23 => x"00000000", -24 => x"71fd0608", -25 => x"83ffff73", -26 => x"83060981", -27 => x"05820583", -28 => x"2b2b0906", -29 => x"7383ffff", -30 => x"0b0b0b0b", -31 => x"83a70400", -32 => x"72098105", -33 => x"72057373", -34 => x"09060906", -35 => x"73097306", -36 => x"070a8106", -37 => x"53510400", -38 => x"00000000", -39 => x"00000000", -40 => x"72722473", -41 => x"732e0753", -42 => x"51040000", -43 => x"00000000", -44 => x"00000000", -45 => x"00000000", -46 => x"00000000", -47 => x"00000000", -48 => x"71737109", -49 => x"71068106", -50 => x"30720a10", -51 => x"0a720a10", -52 => x"0a31050a", -53 => x"81065151", -54 => x"53510400", -55 => x"00000000", -56 => x"72722673", -57 => x"732e0753", -58 => x"51040000", -59 => x"00000000", -60 => x"00000000", -61 => x"00000000", -62 => x"00000000", -63 => x"00000000", -64 => x"00000000", -65 => x"00000000", -66 => x"00000000", -67 => x"00000000", -68 => x"00000000", -69 => x"00000000", -70 => x"00000000", -71 => x"00000000", -72 => x"0b0b0b88", -73 => x"c4040000", -74 => x"00000000", -75 => x"00000000", -76 => x"00000000", -77 => x"00000000", -78 => x"00000000", -79 => x"00000000", -80 => x"720a722b", -81 => x"0a535104", -82 => x"00000000", -83 => x"00000000", -84 => x"00000000", -85 => x"00000000", -86 => x"00000000", -87 => x"00000000", -88 => x"72729f06", -89 => x"0981050b", -90 => x"0b0b88a7", -91 => x"05040000", -92 => x"00000000", -93 => x"00000000", -94 => x"00000000", -95 => x"00000000", -96 => x"72722aff", -97 => x"739f062a", -98 => x"0974090a", -99 => x"8106ff05", -100 => x"06075351", -101 => x"04000000", -102 => x"00000000", -103 => x"00000000", -104 => x"71715351", -105 => x"020d0406", -106 => x"73830609", -107 => x"81058205", -108 => x"832b0b2b", -109 => x"0772fc06", -110 => x"0c515104", -111 => x"00000000", -112 => x"72098105", -113 => x"72050970", -114 => x"81050906", -115 => x"0a810653", -116 => x"51040000", -117 => x"00000000", -118 => x"00000000", -119 => x"00000000", -120 => x"72098105", -121 => x"72050970", -122 => x"81050906", -123 => x"0a098106", -124 => x"53510400", -125 => x"00000000", -126 => x"00000000", -127 => x"00000000", -128 => x"71098105", -129 => x"52040000", -130 => x"00000000", -131 => x"00000000", -132 => x"00000000", -133 => x"00000000", -134 => x"00000000", -135 => x"00000000", -136 => x"72720981", -137 => x"05055351", -138 => x"04000000", -139 => x"00000000", -140 => x"00000000", -141 => x"00000000", -142 => x"00000000", -143 => x"00000000", -144 => x"72097206", -145 => x"73730906", -146 => x"07535104", -147 => x"00000000", -148 => x"00000000", -149 => x"00000000", -150 => x"00000000", -151 => x"00000000", -152 => x"71fc0608", -153 => x"72830609", -154 => x"81058305", -155 => x"1010102a", -156 => x"81ff0652", -157 => x"04000000", -158 => x"00000000", -159 => x"00000000", -160 => x"71fc0608", -161 => x"0b0b80e2", -162 => x"90738306", -163 => x"10100508", -164 => x"060b0b0b", -165 => x"88aa0400", -166 => x"00000000", -167 => x"00000000", -168 => x"80088408", -169 => x"88087575", -170 => x"0b0b0baf", -171 => x"ac2d5050", -172 => x"80085688", -173 => x"0c840c80", -174 => x"0c510400", -175 => x"00000000", -176 => x"80088408", -177 => x"88087575", -178 => x"0b0b0baf", -179 => x"f02d5050", -180 => x"80085688", -181 => x"0c840c80", -182 => x"0c510400", -183 => x"00000000", -184 => x"72097081", -185 => x"0509060a", -186 => x"8106ff05", -187 => x"70547106", -188 => x"73097274", -189 => x"05ff0506", -190 => x"07515151", -191 => x"04000000", -192 => x"72097081", -193 => x"0509060a", -194 => x"098106ff", -195 => x"05705471", -196 => x"06730972", -197 => x"7405ff05", -198 => x"06075151", -199 => x"51040000", -200 => x"05ff0504", -201 => x"00000000", -202 => x"00000000", -203 => x"00000000", -204 => x"00000000", -205 => x"00000000", -206 => x"00000000", -207 => x"00000000", -208 => x"810b0b0b", -209 => x"80e2a00c", -210 => x"51040000", -211 => x"00000000", -212 => x"00000000", -213 => x"00000000", -214 => x"00000000", -215 => x"00000000", -216 => x"71810552", -217 => x"04000000", -218 => x"00000000", -219 => x"00000000", -220 => x"00000000", -221 => x"00000000", -222 => x"00000000", -223 => x"00000000", -224 => x"00000000", -225 => x"00000000", -226 => x"00000000", -227 => x"00000000", -228 => x"00000000", -229 => x"00000000", -230 => x"00000000", -231 => x"00000000", -232 => x"02840572", -233 => x"10100552", -234 => x"04000000", -235 => x"00000000", -236 => x"00000000", -237 => x"00000000", -238 => x"00000000", -239 => x"00000000", -240 => x"00000000", -241 => x"00000000", -242 => x"00000000", -243 => x"00000000", -244 => x"00000000", -245 => x"00000000", -246 => x"00000000", -247 => x"00000000", -248 => x"717105ff", -249 => x"05715351", -250 => x"020d0400", -251 => x"00000000", -252 => x"00000000", -253 => x"00000000", -254 => x"00000000", -255 => x"00000000", -256 => x"83d93f80", -257 => x"cbcf3f04", -258 => x"10101010", -259 => x"10101010", -260 => x"10101010", -261 => x"10101010", -262 => x"10101010", -263 => x"10101010", -264 => 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x"6e207374", -2734 => x"61727473", -2735 => x"2c202564", -2736 => x"2072756e", -2737 => x"73207468", -2738 => x"726f7567", -2739 => x"68204468", -2740 => x"72797374", -2741 => x"6f6e650a", -2742 => x"00000000", -2743 => x"44485259", -2744 => x"53544f4e", -2745 => x"45205052", -2746 => x"4f475241", -2747 => x"4d2c2032", -2748 => x"274e4420", -2749 => x"53545249", -2750 => x"4e470000", -2751 => x"45786563", -2752 => x"7574696f", -2753 => x"6e20656e", -2754 => x"64730a00", -2755 => x"46696e61", -2756 => x"6c207661", -2757 => x"6c756573", -2758 => x"206f6620", -2759 => x"74686520", -2760 => x"76617269", -2761 => x"61626c65", -2762 => x"73207573", -2763 => x"65642069", -2764 => x"6e207468", -2765 => x"65206265", -2766 => x"6e63686d", -2767 => x"61726b3a", -2768 => x"0a000000", -2769 => x"496e745f", -2770 => x"476c6f62", -2771 => x"3a202020", -2772 => x"20202020", -2773 => x"20202020", -2774 => x"2025640a", -2775 => x"00000000", -2776 => x"20202020", -2777 => x"20202020", -2778 => x"73686f75", -2779 => x"6c642062", -2780 => x"653a2020", -2781 => x"2025640a", -2782 => x"00000000", -2783 => x"426f6f6c", -2784 => x"5f476c6f", -2785 => x"623a2020", -2786 => x"20202020", -2787 => x"20202020", -2788 => x"2025640a", -2789 => x"00000000", -2790 => x"43685f31", -2791 => x"5f476c6f", -2792 => x"623a2020", -2793 => x"20202020", -2794 => x"20202020", -2795 => x"2025630a", -2796 => x"00000000", -2797 => x"20202020", -2798 => x"20202020", -2799 => x"73686f75", -2800 => x"6c642062", -2801 => x"653a2020", -2802 => x"2025630a", -2803 => x"00000000", -2804 => x"43685f32", -2805 => x"5f476c6f", -2806 => x"623a2020", -2807 => x"20202020", -2808 => x"20202020", -2809 => x"2025630a", -2810 => x"00000000", -2811 => x"4172725f", -2812 => x"315f476c", -2813 => x"6f625b38", -2814 => x"5d3a2020", -2815 => x"20202020", -2816 => x"2025640a", -2817 => x"00000000", -2818 => x"4172725f", -2819 => x"325f476c", -2820 => x"6f625b38", -2821 => x"5d5b375d", -2822 => x"3a202020", -2823 => x"2025640a", -2824 => x"00000000", -2825 => x"20202020", -2826 => x"20202020", -2827 => x"73686f75", -2828 => x"6c642062", -2829 => x"653a2020", -2830 => x"204e756d", -2831 => x"6265725f", -2832 => x"4f665f52", -2833 => x"756e7320", -2834 => x"2b203130", -2835 => x"0a000000", -2836 => x"5074725f", -2837 => x"476c6f62", -2838 => x"2d3e0a00", -2839 => x"20205074", -2840 => x"725f436f", -2841 => x"6d703a20", -2842 => x"20202020", -2843 => x"20202020", -2844 => x"2025640a", -2845 => x"00000000", -2846 => x"20202020", -2847 => x"20202020", -2848 => x"73686f75", -2849 => x"6c642062", -2850 => x"653a2020", -2851 => x"2028696d", -2852 => x"706c656d", -2853 => x"656e7461", -2854 => x"74696f6e", -2855 => x"2d646570", -2856 => x"656e6465", -2857 => x"6e74290a", -2858 => x"00000000", -2859 => x"20204469", -2860 => x"7363723a", -2861 => x"20202020", -2862 => x"20202020", -2863 => x"20202020", -2864 => x"2025640a", -2865 => x"00000000", -2866 => x"2020456e", -2867 => x"756d5f43", -2868 => x"6f6d703a", -2869 => x"20202020", -2870 => x"20202020", -2871 => x"2025640a", -2872 => x"00000000", -2873 => x"2020496e", -2874 => x"745f436f", -2875 => x"6d703a20", -2876 => x"20202020", -2877 => x"20202020", -2878 => x"2025640a", -2879 => x"00000000", -2880 => x"20205374", -2881 => x"725f436f", -2882 => x"6d703a20", -2883 => x"20202020", -2884 => x"20202020", -2885 => x"2025730a", -2886 => x"00000000", -2887 => x"20202020", -2888 => x"20202020", -2889 => x"73686f75", -2890 => x"6c642062", -2891 => x"653a2020", -2892 => x"20444852", -2893 => x"5953544f", -2894 => x"4e452050", -2895 => x"524f4752", -2896 => x"414d2c20", -2897 => x"534f4d45", -2898 => x"20535452", -2899 => x"494e470a", -2900 => x"00000000", -2901 => x"4e657874", -2902 => x"5f507472", -2903 => x"5f476c6f", -2904 => x"622d3e0a", -2905 => x"00000000", -2906 => x"20202020", -2907 => x"20202020", -2908 => x"73686f75", -2909 => x"6c642062", -2910 => x"653a2020", -2911 => x"2028696d", -2912 => x"706c656d", -2913 => x"656e7461", -2914 => x"74696f6e", -2915 => x"2d646570", -2916 => x"656e6465", -2917 => x"6e74292c", -2918 => x"2073616d", -2919 => x"65206173", -2920 => x"2061626f", -2921 => x"76650a00", -2922 => x"496e745f", -2923 => x"315f4c6f", -2924 => x"633a2020", -2925 => x"20202020", -2926 => x"20202020", -2927 => x"2025640a", -2928 => x"00000000", -2929 => x"496e745f", -2930 => x"325f4c6f", -2931 => x"633a2020", -2932 => x"20202020", -2933 => x"20202020", -2934 => x"2025640a", -2935 => x"00000000", -2936 => x"496e745f", -2937 => x"335f4c6f", -2938 => x"633a2020", -2939 => x"20202020", -2940 => x"20202020", -2941 => x"2025640a", -2942 => x"00000000", -2943 => x"456e756d", -2944 => x"5f4c6f63", -2945 => x"3a202020", -2946 => x"20202020", -2947 => x"20202020", -2948 => x"2025640a", -2949 => x"00000000", -2950 => x"5374725f", -2951 => x"315f4c6f", -2952 => x"633a2020", -2953 => x"20202020", -2954 => x"20202020", -2955 => x"2025730a", -2956 => x"00000000", -2957 => x"20202020", -2958 => x"20202020", -2959 => x"73686f75", -2960 => x"6c642062", -2961 => x"653a2020", -2962 => x"20444852", -2963 => x"5953544f", -2964 => x"4e452050", -2965 => x"524f4752", -2966 => x"414d2c20", -2967 => x"31275354", -2968 => x"20535452", -2969 => x"494e470a", -2970 => x"00000000", -2971 => x"5374725f", -2972 => x"325f4c6f", -2973 => x"633a2020", -2974 => x"20202020", -2975 => x"20202020", -2976 => x"2025730a", -2977 => x"00000000", -2978 => x"20202020", -2979 => x"20202020", -2980 => x"73686f75", -2981 => x"6c642062", -2982 => x"653a2020", -2983 => x"20444852", -2984 => x"5953544f", -2985 => x"4e452050", -2986 => x"524f4752", -2987 => x"414d2c20", -2988 => x"32274e44", -2989 => x"20535452", -2990 => x"494e470a", -2991 => x"00000000", -2992 => x"55736572", -2993 => x"2074696d", -2994 => x"653a2025", -2995 => x"640a0000", -2996 => x"4d696372", -2997 => x"6f736563", -2998 => x"6f6e6473", -2999 => x"20666f72", -3000 => x"206f6e65", -3001 => x"2072756e", -3002 => x"20746872", -3003 => x"6f756768", -3004 => x"20446872", -3005 => x"7973746f", -3006 => x"6e653a20", -3007 => x"00000000", -3008 => x"2564200a", -3009 => x"00000000", -3010 => x"44687279", -3011 => x"73746f6e", -3012 => x"65732070", -3013 => x"65722053", -3014 => x"65636f6e", -3015 => x"643a2020", -3016 => x"20202020", -3017 => x"20202020", -3018 => x"20202020", -3019 => x"20202020", -3020 => x"20202020", -3021 => x"00000000", -3022 => x"56415820", -3023 => x"4d495053", -3024 => x"20726174", -3025 => x"696e6720", -3026 => x"2a203130", -3027 => x"3030203d", -3028 => x"20256420", -3029 => x"0a000000", -3030 => x"50726f67", -3031 => x"72616d20", -3032 => x"636f6d70", -3033 => x"696c6564", -3034 => x"20776974", -3035 => x"686f7574", -3036 => x"20277265", -3037 => x"67697374", -3038 => x"65722720", -3039 => x"61747472", -3040 => x"69627574", -3041 => x"650a0000", -3042 => x"4d656173", -3043 => x"75726564", -3044 => x"2074696d", -3045 => x"6520746f", -3046 => x"6f20736d", -3047 => x"616c6c20", -3048 => x"746f206f", -3049 => x"62746169", -3050 => x"6e206d65", -3051 => x"616e696e", -3052 => x"6766756c", -3053 => x"20726573", -3054 => x"756c7473", -3055 => x"0a000000", -3056 => x"506c6561", -3057 => x"73652069", -3058 => x"6e637265", -3059 => x"61736520", -3060 => x"6e756d62", -3061 => x"6572206f", -3062 => x"66207275", -3063 => x"6e730a00", -3064 => x"44485259", -3065 => x"53544f4e", -3066 => x"45205052", -3067 => x"4f475241", -3068 => x"4d2c2033", -3069 => x"27524420", -3070 => x"53545249", -3071 => x"4e470000", -3072 => x"00010202", -3073 => x"03030303", -3074 => x"04040404", -3075 => x"04040404", -3076 => x"05050505", -3077 => x"05050505", -3078 => x"05050505", -3079 => x"05050505", -3080 => x"06060606", -3081 => x"06060606", -3082 => x"06060606", -3083 => x"06060606", -3084 => x"06060606", -3085 => x"06060606", -3086 => x"06060606", -3087 => x"06060606", -3088 => x"07070707", -3089 => x"07070707", -3090 => x"07070707", -3091 => x"07070707", -3092 => x"07070707", -3093 => x"07070707", -3094 => x"07070707", -3095 => x"07070707", -3096 => x"07070707", -3097 => x"07070707", -3098 => x"07070707", -3099 => x"07070707", -3100 => x"07070707", -3101 => x"07070707", -3102 => x"07070707", -3103 => x"07070707", -3104 => x"08080808", -3105 => x"08080808", -3106 => x"08080808", -3107 => x"08080808", -3108 => x"08080808", -3109 => x"08080808", -3110 => x"08080808", -3111 => x"08080808", -3112 => x"08080808", -3113 => x"08080808", -3114 => x"08080808", -3115 => x"08080808", -3116 => x"08080808", -3117 => x"08080808", -3118 => x"08080808", -3119 => x"08080808", -3120 => x"08080808", -3121 => x"08080808", -3122 => x"08080808", -3123 => x"08080808", -3124 => x"08080808", -3125 => x"08080808", -3126 => x"08080808", -3127 => x"08080808", -3128 => x"08080808", -3129 => x"08080808", -3130 => x"08080808", -3131 => x"08080808", -3132 => x"08080808", -3133 => x"08080808", -3134 => x"08080808", -3135 => x"08080808", -3136 => x"43000000", -3137 => x"64756d6d", -3138 => x"792e6578", -3139 => x"65000000", -3140 => x"00ffffff", -3141 => x"ff00ffff", -3142 => x"ffff00ff", -3143 => x"ffffff00", -3144 => x"00000000", -3145 => x"00000000", -3146 => x"00000000", -3147 => x"0000390c", -3148 => x"000004d2", -- iterations 0x4d2=1234 -3149 => x"00000000", -3150 => x"00000000", -3151 => x"00000000", -3152 => x"00000000", -3153 => x"00000000", -3154 => x"00000000", -3155 => x"00000000", -3156 => x"00000000", -3157 => x"00000000", -3158 => x"00000000", -3159 => x"00000000", -3160 => x"00000000", -3161 => x"00000000", -3162 => x"ffffffff", -3163 => x"00000000", -3164 => x"00020000", -3165 => x"00000000", -3166 => x"00000000", -3167 => x"00003174", -3168 => x"00003174", -3169 => x"0000317c", -3170 => x"0000317c", -3171 => x"00003184", -3172 => x"00003184", -3173 => x"0000318c", -3174 => x"0000318c", -3175 => x"00003194", -3176 => x"00003194", -3177 => x"0000319c", -3178 => x"0000319c", -3179 => x"000031a4", -3180 => x"000031a4", -3181 => x"000031ac", -3182 => x"000031ac", -3183 => x"000031b4", -3184 => x"000031b4", -3185 => x"000031bc", -3186 => x"000031bc", -3187 => x"000031c4", -3188 => x"000031c4", -3189 => x"000031cc", -3190 => x"000031cc", -3191 => x"000031d4", -3192 => x"000031d4", -3193 => x"000031dc", -3194 => x"000031dc", -3195 => x"000031e4", -3196 => x"000031e4", -3197 => x"000031ec", -3198 => x"000031ec", -3199 => x"000031f4", -3200 => x"000031f4", -3201 => x"000031fc", -3202 => x"000031fc", -3203 => x"00003204", -3204 => x"00003204", -3205 => x"0000320c", -3206 => x"0000320c", -3207 => x"00003214", -3208 => x"00003214", -3209 => x"0000321c", -3210 => x"0000321c", -3211 => x"00003224", -3212 => x"00003224", -3213 => x"0000322c", -3214 => x"0000322c", -3215 => x"00003234", -3216 => x"00003234", -3217 => x"0000323c", -3218 => x"0000323c", -3219 => x"00003244", -3220 => x"00003244", -3221 => x"0000324c", -3222 => x"0000324c", -3223 => x"00003254", -3224 => x"00003254", -3225 => x"0000325c", -3226 => x"0000325c", -3227 => x"00003264", -3228 => x"00003264", -3229 => x"0000326c", -3230 => x"0000326c", -3231 => x"00003274", -3232 => x"00003274", -3233 => x"0000327c", -3234 => x"0000327c", -3235 => x"00003284", -3236 => x"00003284", -3237 => x"0000328c", -3238 => x"0000328c", -3239 => x"00003294", -3240 => x"00003294", -3241 => x"0000329c", -3242 => x"0000329c", -3243 => x"000032a4", -3244 => x"000032a4", -3245 => x"000032ac", -3246 => x"000032ac", -3247 => x"000032b4", -3248 => x"000032b4", -3249 => x"000032bc", -3250 => x"000032bc", -3251 => x"000032c4", -3252 => x"000032c4", -3253 => x"000032cc", -3254 => x"000032cc", -3255 => x"000032d4", -3256 => x"000032d4", -3257 => x"000032dc", -3258 => x"000032dc", -3259 => x"000032e4", -3260 => x"000032e4", -3261 => x"000032ec", -3262 => x"000032ec", -3263 => x"000032f4", -3264 => x"000032f4", -3265 => x"000032fc", -3266 => x"000032fc", -3267 => x"00003304", -3268 => x"00003304", -3269 => x"0000330c", -3270 => x"0000330c", -3271 => x"00003314", -3272 => x"00003314", -3273 => x"0000331c", -3274 => x"0000331c", -3275 => x"00003324", -3276 => x"00003324", -3277 => x"0000332c", -3278 => x"0000332c", -3279 => x"00003334", -3280 => x"00003334", -3281 => x"0000333c", -3282 => x"0000333c", -3283 => x"00003344", -3284 => x"00003344", -3285 => x"0000334c", -3286 => x"0000334c", -3287 => x"00003354", -3288 => x"00003354", -3289 => x"0000335c", -3290 => x"0000335c", -3291 => x"00003364", -3292 => x"00003364", -3293 => x"0000336c", -3294 => x"0000336c", -3295 => x"00003374", -3296 => x"00003374", -3297 => x"0000337c", -3298 => x"0000337c", -3299 => x"00003384", -3300 => x"00003384", -3301 => x"0000338c", -3302 => x"0000338c", -3303 => x"00003394", -3304 => x"00003394", -3305 => x"0000339c", -3306 => x"0000339c", -3307 => x"000033a4", -3308 => x"000033a4", -3309 => x"000033ac", -3310 => x"000033ac", -3311 => x"000033b4", -3312 => x"000033b4", -3313 => x"000033bc", -3314 => x"000033bc", -3315 => x"000033c4", -3316 => x"000033c4", -3317 => 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x"00002ad0", + 3042 => x"00000000", + 3043 => x"00000000", + 3044 => x"00000000", + 3045 => x"00000000", + 3046 => x"00000000", + 3047 => x"00000000", + 3048 => x"00000000", + 3049 => x"00000000", + 3050 => x"00000000", + 3051 => x"00000000", + 3052 => x"00000000", + 3053 => x"00000000", + 3054 => x"00000000", + 3055 => x"00000000", + 3056 => x"00000000", + 3057 => x"00000000", + 3058 => x"00000000", + 3059 => x"00000000", + 3060 => x"00000000", + 3061 => x"00000000", + 3062 => x"00000000", + 3063 => x"00000000", + 3064 => x"00000000", + 3065 => x"00000000", + 3066 => x"00000000", + 3067 => x"00000000", + 3068 => x"00000000", + 3069 => x"00000000", + 3070 => x"00000001", + 3071 => x"330eabcd", + 3072 => x"1234e66d", + 3073 => x"deec0005", + 3074 => x"000b0000", + 3075 => x"00000000", + 3076 => x"00000000", + 3077 => x"00000000", + 3078 => x"00000000", + 3079 => x"00000000", + 3080 => x"00000000", + 3081 => x"00000000", + 3082 => x"00000000", + 3083 => x"00000000", + 3084 => x"00000000", + 3085 => x"00000000", + 3086 => x"00000000", + 3087 => x"00000000", + 3088 => x"00000000", + 3089 => x"00000000", + 3090 => x"00000000", + 3091 => x"00000000", + 3092 => x"00000000", + 3093 => x"00000000", + 3094 => x"00000000", + 3095 => x"00000000", + 3096 => x"00000000", + 3097 => x"00000000", + 3098 => x"00000000", + 3099 => x"00000000", + 3100 => x"00000000", + 3101 => x"00000000", + 3102 => x"00000000", + 3103 => x"00000000", + 3104 => x"00000000", + 3105 => x"00000000", + 3106 => x"00000000", + 3107 => x"00000000", + 3108 => x"00000000", + 3109 => x"00000000", + 3110 => x"00000000", + 3111 => x"00000000", + 3112 => x"00000000", + 3113 => x"00000000", + 3114 => x"00000000", + 3115 => x"00000000", + 3116 => x"00000000", + 3117 => x"00000000", + 3118 => x"00000000", + 3119 => x"00000000", + 3120 => x"00000000", + 3121 => x"00000000", + 3122 => x"00000000", + 3123 => x"00000000", + 3124 => x"00000000", + 3125 => x"00000000", + 3126 => x"00000000", + 3127 => x"00000000", + 3128 => x"00000000", + 3129 => x"00000000", + 3130 => x"00000000", + 3131 => x"00000000", + 3132 => x"00000000", + 3133 => x"00000000", + 3134 => x"00000000", + 3135 => x"00000000", + 3136 => x"00000000", + 3137 => x"00000000", + 3138 => x"00000000", + 3139 => x"00000000", + 3140 => x"00000000", + 3141 => x"00000000", + 3142 => x"00000000", + 3143 => x"00000000", + 3144 => x"00000000", + 3145 => x"00000000", + 3146 => x"00000000", + 3147 => x"00000000", + 3148 => x"00000000", + 3149 => x"00000000", + 3150 => x"00000000", + 3151 => x"00000000", + 3152 => x"00000000", + 3153 => x"00000000", + 3154 => x"00000000", + 3155 => x"00000000", + 3156 => x"00000000", + 3157 => x"00000000", + 3158 => x"00000000", + 3159 => x"00000000", + 3160 => x"00000000", + 3161 => x"00000000", + 3162 => x"00000000", + 3163 => x"00000000", + 3164 => x"00000000", + 3165 => x"00000000", + 3166 => x"00000000", + 3167 => x"00000000", + 3168 => x"00000000", + 3169 => x"00000000", + 3170 => x"00000000", + 3171 => x"00000000", + 3172 => x"00000000", + 3173 => x"00000000", + 3174 => x"00000000", + 3175 => x"00000000", + 3176 => x"00000000", + 3177 => x"00000000", + 3178 => x"00000000", + 3179 => x"00000000", + 3180 => x"00000000", + 3181 => x"00000000", + 3182 => x"00000000", + 3183 => x"00000000", + 3184 => x"00000000", + 3185 => x"00000000", + 3186 => x"00000000", + 3187 => x"00000000", + 3188 => x"00000000", + 3189 => x"00000000", + 3190 => x"00000000", + 3191 => x"00000000", + 3192 => x"00000000", + 3193 => x"00000000", + 3194 => x"00000000", + 3195 => x"00000000", + 3196 => x"00000000", + 3197 => x"00000000", + 3198 => x"00000000", + 3199 => x"00000000", + 3200 => x"00000000", + 3201 => x"00000000", + 3202 => x"00000000", + 3203 => x"00000000", + 3204 => x"00000000", + 3205 => x"00000000", + 3206 => x"00000000", + 3207 => x"00000000", + 3208 => x"00000000", + 3209 => x"00000000", + 3210 => x"00000000", + 3211 => x"00000000", + 3212 => x"00000000", + 3213 => x"00000000", + 3214 => x"00000000", + 3215 => x"00000000", + 3216 => x"00000000", + 3217 => x"00000000", + 3218 => x"00000000", + 3219 => x"00000000", + 3220 => x"00000000", + 3221 => x"00000000", + 3222 => x"00000000", + 3223 => x"00000000", + 3224 => x"00000000", + 3225 => x"00000000", + 3226 => x"00000000", + 3227 => x"00000000", + 3228 => x"00000000", + 3229 => x"00000000", + 3230 => x"00000000", + 3231 => x"00000000", + 3232 => x"00000000", + 3233 => x"00000000", + 3234 => x"00000000", + 3235 => x"00000000", + 3236 => x"00000000", + 3237 => x"00000000", + 3238 => x"00000000", + 3239 => x"00000000", + 3240 => x"00000000", + 3241 => x"00000000", + 3242 => x"00000000", + 3243 => x"00000000", + 3244 => x"00000000", + 3245 => x"00000000", + 3246 => x"00000000", + 3247 => x"00000000", + 3248 => x"00000000", + 3249 => x"00000000", + 3250 => x"00000000", + 3251 => x"00002ad4", + 3252 => x"ffffffff", + 3253 => x"00000000", + 3254 => x"ffffffff", + 3255 => x"00000000", + 3256 => x"00000000", others => x"00000000" ); diff --git a/zpu/hdl/example/simzpu_dmips.do b/zpu/hdl/example/simzpu_dmips.do new file mode 100644 index 0000000..883259e --- /dev/null +++ b/zpu/hdl/example/simzpu_dmips.do @@ -0,0 +1,29 @@ +# Xilinx WebPack modelsim script +# +# +# cd C:/workspace/zpu/zpu/hdl/example +# do simzpu_dmips.do + +set BreakOnAssertion 1 +vlib work + +vcom -93 -explicit zpu_config.vhd +vcom -93 -explicit ../zpu4/core/zpupkg.vhd +vcom -93 -explicit ../zpu4/src/txt_util.vhd +vcom -93 -explicit sim_small_fpga_top_noint.vhd +vcom -93 -explicit ../zpu4/core/zpu_core_small.vhd +vcom -93 -explicit bram_dmips.vhd +vcom -93 -explicit ../zpu4/src/timer.vhd +vcom -93 -explicit ../zpu4/src/io.vhd +vcom -93 -explicit ../zpu4/src/trace.vhd + +# run ZPU +vsim fpga_top +view wave +add wave -recursive fpga_top/zpu/* +#add wave -recursive fpga_top/* +view structure +#view signals + +# Enough to run tiny programs +run 10 ms diff --git a/zpu/hdl/example/zpuromgen.exe b/zpu/hdl/example/zpuromgen.exe new file mode 100644 index 0000000..6655412 Binary files /dev/null and b/zpu/hdl/example/zpuromgen.exe differ -- cgit v1.1 From 709f5ff71d918f10835d89ed6f349aee9dea340b Mon Sep 17 00:00:00 2001 From: oharboe Date: Wed, 12 Nov 2008 20:50:06 +0000 Subject: =?UTF-8?q?2008-11-12=20=C1lvaro=20Lopes=20=20?= =?UTF-8?q?=09*=20zpu/hdl/zpu4/core/zpu=5Fcore.vhd:=20Basic=20interrupt=20?= =?UTF-8?q?implementation=20=09for=20zpu4=20core.?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- zpu/ChangeLog | 3 +++ zpu/hdl/zpu4/core/zpu_core.vhd | 32 +++++++++++++++++++++++++++++++- 2 files changed, 34 insertions(+), 1 deletion(-) diff --git a/zpu/ChangeLog b/zpu/ChangeLog index e190a9f..2ed7369 100644 --- a/zpu/ChangeLog +++ b/zpu/ChangeLog @@ -1,3 +1,6 @@ +2008-11-12 Álvaro Lopes + * zpu/hdl/zpu4/core/zpu_core.vhd: Basic interrupt implementation + for zpu4 core. 2008-09-16 Salvador Eduardo Tropea * zpu/hdl/zealot: added small ZPU core, testbenches and FPGA implementation 2008-09-11 Salvador Eduardo Tropea diff --git a/zpu/hdl/zpu4/core/zpu_core.vhd b/zpu/hdl/zpu4/core/zpu_core.vhd index 012fe1b..69da686 100644 --- a/zpu/hdl/zpu4/core/zpu_core.vhd +++ b/zpu/hdl/zpu4/core/zpu_core.vhd @@ -1,6 +1,7 @@ -- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- Copyright 2008 alvieboy - Álvaro Lopes - alvieboy@alvie.com -- -- The FreeBSD license -- @@ -145,7 +146,8 @@ State_Mult5, State_Mult4, State_BinaryOpResult2, State_BinaryOpResult, -State_Idle +State_Idle, +State_Interrupt ); @@ -171,6 +173,8 @@ signal mem_addr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); signal mem_delayAddr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); signal mem_delayReadEnable : std_logic; +signal inInterrupt: std_logic; + signal decodeWord : std_logic_vector(wordSize-1 downto 0); @@ -244,6 +248,7 @@ begin pc <= (others => '0'); idim_flag <= '0'; begin_inst <= '0'; + inInterrupt <= '0'; mem_writeEnable <= '0'; mem_readEnable <= '0'; multA <= (others => '0'); @@ -288,6 +293,10 @@ begin trace_topOfStackB <= std_logic_vector(stackB); begin_inst <= '0'; + if (interrupt='0') then + -- Interrupt ended, we can serve ISR again + inInterrupt <= '0'; + end if; case state is when State_Idle => @@ -319,6 +328,27 @@ begin if in_mem_busy='0' then decodeWord <= mem_read; state <= State_Decode2; + -- Do not recurse into ISR while interrupt line is active + if interrupt='1' and inInterrupt='0' and idim_flag='0' then + -- We got an interrupt, execute interrupt instead of next instruction + inInterrupt <= '1'; + sp <= decSp; + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc; + stackB <= stackA; + pc <= to_unsigned(32, maxAddrBitIncIO+1); + state <= State_Interrupt; + end if; + end if; + when State_Interrupt => + if in_mem_busy='0' then + mem_addr <= std_logic_vector(pc(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + state <= State_Decode; + report "ZPU jumped to interrupt!" severity note; end if; when State_Decode2 => -- decode 4 instructions in parallel -- cgit v1.1 From e68026ab045d371d6f3710276ecebd7f4645d26c Mon Sep 17 00:00:00 2001 From: oharboe Date: Sun, 14 Dec 2008 23:11:10 +0000 Subject: wip - added LIFO to list of ideas for next gen ZPU --- zpu/docs/zpu_arch.html | 50 +++++++++++++++++++++++++++++--------------------- 1 file changed, 29 insertions(+), 21 deletions(-) diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index 0c57cae..5cf7410 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -2002,24 +2002,42 @@ $ arm-elf-size *

          Next generation ZPU

          Based on feedback here is a list of a tenuous "consensus" for the next generation of the ZPU with some tentative ideas on implementation. -

          -The plan is to update zpu_core.vhd and zpu_core_small.vhd as examples/reference, -and to open up for innovation in the HDL implementation. - +

          Goals

            -
          1. Reduce minimum code size footprint +
          2. Reduce minimum code size footprint, i.e. BRAM code overhead. Non-trivial +usable applications in 4kBytes of BRAM (single BRAM block). +
          3. Reduce minimum FPGA logic footprint by 20% or more. Goal <300 LUT for +32 bit ZPU +
          4. Weed out unecessary ZPU variations +
          +

          Best current ideas on how to reach these goals

            +
          1. Introduce 16 entry 32 bit LIFO for instructions that change sp today. LOADSP/STORESP/ADDSP +refer to the normal stack but add/get values from the LIFO in addition.

            + +loadsp n ; load value from memory at address "sp + n" and put it into the LIFO.
            +im m ; put value into LIFO register
            +add ; get two values from LIFO register, put back result.
            +             +

            +NB! none of the instructions above change sp!!! +

            +If the LIFO is full, putting a value into the LIFO has no defined behaviour. Getting a value +from an empty LIFO has no defined behaviour. +

            +GCC will use 8 slots, instruction emulation and interrupts owns the remaining 8 slots. +

          2. Add single entry for unknown instructions. PC and unsupported instruction is -pushed onto stack before jumping to unkonwn instruction vector. This makes it possible +pushed onto stack before jumping to unknown instruction vector. This makes it possible to write denser microcode for missing instructions. For emulated opcodes that are not in use, the microcode can more easily be disabled. Determining that e.g. MULT is not used, can be a bit tricky, but disabling it is easy.

            -The address of this entry will be 0x10. The reason 0x00 is not used is that -GCC needs 0x00-0x0b inclusive to store R0-R2(memory mapped GCC registers). -The reset vector remains 0x0 so the 0x00-0x0f addresses contains the -first few instructions executed by the ZPU. Some very early work has been -done in nextgen_crt0.S. +The unsupported vectory entry address is 0x10. +

          3. GCC needs 4 registers. These are today mapped to memory. What addresses to use? +Today memory address 0x00-0x0f inclusive are used for this purpose. Introduce emulated +instruction to load/store these registers? That would allow using either hardware or +memory registers.
          4. Single entry for *all* unknown instructions does not limit emulation to the EMULATE instructions today, but instructions such as OR, LOADSP, STORESP, ADDSP, etc. can also be emulated. This opens up for further reduction in logic usage. @@ -2027,18 +2045,8 @@ etc. can also be emulated. This opens up for further reduction in logic usage. write a compact custom crt0.s to fit an instruction subset.
          5. The interrupt is basically an unknown instruction that is injected into the execution stream. -
          6. Possibly modify the java simulator to support the single entry for unknown -instructions. -
        1. Add floating point add and mult. FADD & FMULT. Option to generate the instructions from the compiler. -
        2. Add GCC support for seperate code/data bus. This may be as "simple" as -writing a custom linker script for the current GCC compiler. -
        3. Add some scheme to support custom instructions. Can this be combined with -single entry point for unknown instructions? -
        4. Add support to Zylin Embedded CDT for downloading fully functional ZPU -toolchain. The goal is to allow new users to write and simulate simple ZPU -programs in in less than an hour.
        5. Strip away unused instructions from GCC and add options to GCC for not emitting more advanced instructions. This will e.g. convert MULT/DIV into function calls to libgcc and thus make it easier to determine that -- cgit v1.1 From 26806927a9e6985fdc508c703c3525e5aedf3a23 Mon Sep 17 00:00:00 2001 From: oharboe Date: Wed, 17 Dec 2008 22:09:07 +0000 Subject: register stack wip --- zpu/docs/zpu_arch.html | 56 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index 5cf7410..9b69660 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -33,6 +33,7 @@ $id$
        6. Next generation ZPU +
        7. Register stack ZPU @@ -2090,5 +2091,60 @@ as an uncompressed .txt file

          Getting help - mailing list

          The place to get help is the           zylin-zpu mailing list + +

          Register stack

          +In order to reduce the size and complexity of the small ZPU, a register stack +has been put forward. It remains an open question as to whether this can +indeed reduce size and improve performance of the ZPU. +

          +Terminology: "stack" is the normal stack in memory pointed to +by the sp register. "register stack" is a different stack that is +not connected to memory directly or associated with the "stack". +

          +The idea is to push and pop the register stack such that bandwidth +is increased and complexity of memory access logic is reduced. +

          +Another clever bit is to mask interrupts while this stack is +not empty such that this stack never has to be +saved. It's depth would be fixed to something natural +for an FPGA, say 16 deep(doesn't that translate to a single +LUT for a bit?). + +

          Example of internal stack

          +im 1 ; push onto register stack
          +loadsp N ; load from memory pointed to by sp+N, push onto register stack
          +add ; pop values from register stack and add, push onto register stack
          + +

          Quick summary of instruction operation with register stack

          +This is not a "formal" definition of the instruction set, but should +give a pretty good idea of what the modified instruction looks like. +

          +Read up on the current definition of instructions and consider the +list below a guide to what changes have been made to fit a register +stack. The list is not complete, but covers the important categories +of instructions. If it is clear how the ADD instruction changed, +then it should be obvious how the AND isntruction must be similarly +modified. +

          +Note also that there are lots of tiny problems that have to be ironed +out before the instruction set and emulation can work. Below is just +a first stab, which hopefully is good enough to evaluate the approach. + + + + + + + + + + + + + + +
          IM push onto/modify top of register stack
          STORESP pop register stack store to memory SP+N
          LOADSP load memory SP+N push onto register stack
          EMULATE push PC+1 onto register stack and jump to EMULATE vector
          PUSHPC push pc onto register stack
          POPPC pop pc from register stack
          LOAD pop address from register stack, load from memory address, push onto register stack
          STORE pop register stack 2x store value to memory
          PUSHSP push sp onto register stack
          POPSP pop sp from register stack
          POPPC pop pc from register stack
          ADD pop 2x register stack, add, push to register stack
          NOT pop register stack, bit inverse value, push onto register stack
          +Emulate instructions and calling convention may have to change substantially. + \ No newline at end of file -- cgit v1.1 From 8e14f783818beeaae0786e8168ab1613d3cfbdd9 Mon Sep 17 00:00:00 2001 From: dez Date: Fri, 9 Jan 2009 11:17:10 -0500 Subject: this is a push test --- foo | 0 1 file changed, 0 insertions(+), 0 deletions(-) create mode 100644 foo diff --git a/foo b/foo new file mode 100644 index 0000000..e69de29 -- cgit v1.1 From dfe4db67d7b939ed3db9be43468508cff2418227 Mon Sep 17 00:00:00 2001 From: dez Date: Fri, 9 Jan 2009 11:19:20 -0500 Subject: not empty now --- foo | 1 + 1 file changed, 1 insertion(+) diff --git a/foo b/foo index e69de29..8bd6648 100644 --- a/foo +++ b/foo @@ -0,0 +1 @@ +asdf -- cgit v1.1 From 3a35af1a9d5a61c3af3c04cafcc3366ba04ba864 Mon Sep 17 00:00:00 2001 From: dez Date: Fri, 9 Jan 2009 11:36:29 -0500 Subject: this is a test --- bar | 0 1 file changed, 0 insertions(+), 0 deletions(-) create mode 100644 bar diff --git a/bar b/bar new file mode 100644 index 0000000..e69de29 -- cgit v1.1 From 97f353278c22287b1931eeefb7d9403c3276bfc5 Mon Sep 17 00:00:00 2001 From: dez Date: Fri, 9 Jan 2009 12:10:16 -0500 Subject: test cleanup --- bar | 0 foo | 1 - 2 files changed, 1 deletion(-) delete mode 100644 bar delete mode 100644 foo diff --git a/bar b/bar deleted file mode 100644 index e69de29..0000000 diff --git a/foo b/foo deleted file mode 100644 index 8bd6648..0000000 --- a/foo +++ /dev/null @@ -1 +0,0 @@ -asdf -- cgit v1.1 From 5af4810c230702ae3a2db9e3d0e5c783f3417105 Mon Sep 17 00:00:00 2001 From: dez_ambrose Date: Fri, 9 Jan 2009 12:46:03 -0500 Subject: Organizing document to make cleared seperation of architecture, implementations, and other design elements. --- zpu/docs/zpu_arch.html | 4533 +++++++++++++++++++++++++----------------------- 1 file changed, 2383 insertions(+), 2150 deletions(-) diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index 9b69660..a0187e6 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -1,2150 +1,2383 @@ - - -

          Latest version of this document

          -This is a snapshot of the zpu_arch.html document in CVS. Please check out -the latest version from CVS to get the latest version. -

          -$id$ -

          Index

          -           - - -

          The worlds smallest 32 bit CPU with GCC toolchain -

          -

          This CPU is finding a new home at www.opencores.org, please -contact me if you are willing and able to help in shaping up the -www.opencores.org pages. -

          -

          The HDL, GCC toolchain and eCos HAL are actually done. Mainly I -could need a hand with writing up docs/web pages/examples/bug -reports.

          -

          The ZPU has a BSD license for the HDL and GPL for the rest(source -files are sadly out of date here, patches gladly accepted!). This -allows deployments to implement any version of the ZPU they want -without running into commercial problems, but if improvements are -done to the architecture as such, then they need to be contributed -back. -

          -

          One strength of the ZPU is that it is tiny and therefore easy to -implement from scratch to suit specialized needs and optimizations.

          -

          Currently there exists some pages at http://www.zylin.com/zpu.htm -that explains about the ZPU. According to OpenCores policy this -information should be moved to www.opencores.org. Patches gratefully -accepted to do so!

          -

          Per Jan 1. 2008, Zylin has the Copyright for the ZPU, i.e. Zylin -is free to decide that the ZPU shall have a BSD license for HDL + GPL -for the rest.

          -

          Sincerley,

          -

          Øyvind Harboe
          Zylin AS -

          -

          Features -

          -
            -

          • Small size: 442 LUT @ 95 MHz after - P&R w/32 bit datapath Xilinx XC3S400 -

            -

          • Wishbone -

            -

          • Code size 80% of ARM Thumb -

            -

          • GCC toolchain(GDB, newlib, - libstdc+) -

            -

          • eCos embedded operating system support

            -
          -

          Survey -

          -

          Please take the time to fill in this short survey so we can gather -information about where the ZPU can be the most useful:

          -

          http://www.zylin.com/zpusurvey.html

          -

          Status -

          -
            -

          • HDL works -

            -

          • GCC toolchain works -

            -

          • eCos HAL works, but could be less - RAM hungry -

            -

          • The main problem at this point is - not usage of the CPU, but that the documentation/CVS layout needs - attention -

            -

          • Needs GDB stub support in eCos -

            -

          • Could do with a Verilog implementation(ca. 600 lines to - translate)

            -
          -

          Simulator -

          -

          The ZPU simulator is integrated into the Zylin Embedded CDT plugin -to ease debugging of ZPU applications:

          -

          http://www.zylin.com/embeddedcdt.html

          -

          The ZPU simulator has many features besides debugging an -application:

          -
            -

          • taking output from simulation(e.g. - ModelSim) and matching that against the Java simulator, thus making - it much easier to debug HDL implementations and also getting real - world timing information -

            -

          • can generate gprof output -

            -

          • generate various statistics -

            -
          -

          The plugin is still pretty rough around the edges, and needs to -get GUI support for enabling the ModelSim trace input feature.

          -


          Compiling -ZPU application

          -


          Setting -up the simulator

          -


          Choosing -ZPU executable

          -


          Debug -session

          -


          -

          - - -

          Getting started - FPGA

          -The simplest version of the ZPU uses BRAM. When getting accustomed to the ZPU, a BRAM ZPU with a UART -is a good place to start. -

          -You'll find a working simulation script in hdl/example/simzpu_small.do and hdl/example_medium/simzpu_medium.do, which -show simulation of the small(zpu_core_small.vhd) and medium sized ZPU(zpu_core.vhd). hdl/example/simzpu_interrupt.do -shows use of interrupts. -

          -When implementing the ZPU, copy the following files and modify them to your needs: -

            -
          1. hdl/example/zpu_config.vhd - set up RAM size here -
          2. hdl/example/helloworld.vhd - dual port BRAM implementation. -
          -Obviously you must also connect the ZPU to the rest of your IO subsystem. IO is memory mapped(read/write) in the ZPU. -

          Generating VHDL BRAM initialization

          - - -../install/bin/zpu-elf-objcopy -O binary hello.elf hello.bin
          -java -classpath ../simulator/zpusim.jar com.zylin.zpu.simulator.tools.MakeRam hello.bin >hello.bram
          - -           -

          Build another test application for example simulation

          -Here is how to build a rom image for an application using the -zpu/example simulation files. -

          -cd zpu/roadshow/roadshow/dhrystone
          -sh build.sh
          -cd zpu/hdl/example
          -gcc zpuromgen.c
          -$ ./a
          -Usage: ./a binary_file
          -./a ../../roadshow/roadshow/dhrystone/dhrystone.bin >app.txt
          -

          -Copy and paste app.txt into helloworld.vhd. - -

          Running example simulation

          -The hdl/example directory has a simulation written for Xilinx WebPack ModelSim. From the ModelSim command prompt: -
            -
          1. cd c:/<installfolder>/hdl/example -
          2. do zpusim_small.do -
          -

          -After running the hello world simulation (see zpusim.do), two files are written to the hdl/example directory: -

            -
          1. log.txt - contains the "Hello world!" text written to the debug channel/simplified UART. -
          2. trace.txt - a trace file for the CPU. The instruction set simulator has the capability of taking -this file as input in order to verify that the HDL implementation matches the instruction set simulator. -When a mismatch is found, the GDB debugger will break. Very handy for debugging custom ZPU implementations. -
          -

          HDL Directories & files

          -
            -
          • example - contains example files & working ZPU. Start here. -
          • wishbone - contains wishbone interface for the ZPU -
          • zpu3 - if you are interested in developing ZPU cores and not only using them, then this directory contains various stuff of more or less historical interest. -
          • zpu4 - if you are interested in developing ZPU cores and not only using them, then this is the active development version. You'll also want to copy out the -files you need from this folder to your own project. -
          - -The HDL files need a bit of spit and polish! - -           -

          Getting started - software

          -The ZPU comes with a standard GCC toolchain and an instruction set simulator. This allows compiling, running & debugging simple test programs. The Simulator has -some very basic peripherals defined: counter, timer interrupt and a debug output port. -

          Installing

          -
            -
          1. Install Cygwin. http://www.cygwin.com -
          2. Install Java -
          3. Start Cygwin bash -
          4. cd zpu/sw -
          5. sh setup.sh -
          6. /tmp/zpu/install/bin now has the .exe files for the GCC toolchain & GDB -
          7. Optionally you may set up PATH variables to point to /tmp/zpu/install/bin
            -source env.sh -
          -

          Hello world example

          -The ZPU toolchain comes with newlib & libstdc++ support which means that many C/C++ programs can be compiled without modification. -

          - -cd zpu/sw/helloworld
          -../install/bin/zpu-elf-gcc -phi hello.c -o hello.elf
          -           -

          Running the hello world example in GDB

          -
            -
          1. cd zpu/sw/helloworld -
          2. Launch the simulator from a seperate bash shell:

            -java -classpath ../simulator/zpusim.jar -Xmx512m com.zylin.zpu.simulator.Phi 4444 -

            - -

          3. Launch GDB:

            -../install/bin/zpu-elf-gdb hello.elf -

          4. Connect to target, load and run application:

            - -(gdb) target remote localhost:4444
            -(gdb) load
            -(gdb) continue
            -             -

            - - -

          - - -           -

          Architecture introduction

          -The ZPU is a zero operand, or stack based CPU. The opcodes have a fixed width of 8 bits. -

          -Example: -

          -

          - - IM 5 ; push 5 onto the stack - LOADSP 20 ; push value at memory location SP+20 - ADD ; pop 2 values on the stack and push the result - -
          -As can be seen, a lot of information is packed into the 8 bits, e.g. the IM instruction pushes a 7 bit signed integer onto the stack. -

          -The choice of opcodes is intimately tied to the GCC toolchain capabilities. -

          -

          - - /* simple program showing some interesting qualities of the ZPU toolchain */ - void bar(int); - int j; - void foo(int a, int b, int c) - { - a++; - b+=a; - j=c; - bar(b); - } - -foo: - loadsp 4 ; a is at memory location SP+4 - im 1 - add - loadsp 12 ; b is now at memory location SP+12 - add - loadsp 16 ; c is now at memory location SP+16 - im 24 ; «j» is at absolute memory location 24. -; Notice how the ZPU toolchain is using link-time relaxation -; to squeeze the address into a single no-op - store - im 22 ; the fn bar is at address 22 - call - im 12 - return ; 12 bytes of arguments + return from fn - -
          - -           -

          Instruction set

          -Only the base instructions are implemented in the architecture. More advanced instructions, like ASHIFTLEFT are emulated in the illegal instruction vector. - -All operations are 32 bit wide. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
          NameOpcodeDescriptionDefinition
          - BREAKPOINT - - 00000000 - - The debugger sets a memory location to this value to set a breakpoint. Once a JTAG-like - debugger interface is added, it will be convenient to be able to distinguish - between a breakpoint and an illegal(possibly emulated) instruction. - - No effect on registers -
          - IM - - 1xxx xxxx - - Pushes 7 bit sign extended integer and sets the a «instruction decode interrupt mask» flag(IDIM). -

          - If the IDIM flag is already set, this instruction shifts the value on the stack left by 7 bits and stores the 7 bit immediate value into the lower 7 bits. -

          - Unless an instruction is listed as treating the IDIM flag specially, it should be assumed to clear the IDIM flag. -

          - To push a 14 bit integer onto the stack, use two consequtive IM instructions. -

          - If multiple immediate integers are to be pushed onto the stack, they must be interleaved with another instruction, typically NOP. -

          		- -pc <= pc + 1
          -idim <= 1
          -if (idim=0) then
          - sp <= sp - 1;
          - for i in wordSize-1 downto 7 loop
          - mem(sp)(i) <= opcode(6)
          - end loop
          - mem(sp)(6 downto 0) <= opcode(6 downto 0)
          -else
          - mem(sp)(wordSize-1 downto 7) <= mem(sp)(wordSize-8 downto 0)
          - mem(sp)(6 downto 0) <= opcode(6 downto 0)
          -end if -           - -
          - STORESP - - 010x xxxx - - Pop value off stack and store it in the SP+xxxxx*4 memory location, where xxxxx is a positive integer. - -
          - LOADSP - - 011x xxxx - - Push value of memory location SP+xxxxx*4, where xxxxx is a positive integer, onto stack. - - -
          - ADDSP - - 0001 xxxx - - Add value of memory location SP+xxxx*4 to value on top of stack. - - -
          - EMULATE - - 001x xxxx - - Push PC to stack and set PC to 0x0+xxxxx*32. This is used to emulate opcodes. See - zpupgk.vhd for list of emulate opcode values used. zpu_core.vhd contains - reference implementations of these instructions rather than letting the ZPU execute the EMULATE instruction -

          - One way to improve performance of the ZPU is to implement some of - the EMULATE instructions. - -

          		- -
          - PUSHPC - - emulated - - Pushes program counter onto the stack. - - -
          - POPPC - - 0000 0100 - - Pops address off stack and sets PC - - -
          - LOAD - - 0000 1000 - - Pops address stored on stack and loads the value of that address onto stack. -

          - Bit 0 and 1 of address are always treated as 0(i.e. ignored) by - the HDL implementations and C code is guaranteed by the programming - model never to use 32 bit LOAD on non-32 bit aligned addresses(i.e. - if a program does this, then it has a bug). -

          		- -
          - STORE - - 0000 1100 - - Pops address, then value from stack and stores the value into the memory location of the address. -

          - Bit 0 and 1 of address are always treated as 0 -

          		- -
          - PUSHSP - - 0000 0010 - - Pushes stack pointer. - - -
          - POPSP - - 0000 1101 - - Pops value off top of stack and sets SP to that value. Used to allocate/deallocate space on stack for variables or when changing threads. - - -
          - ADD - - 0000 0101 - - Pops two values on stack adds them and pushes the result - - -
          - AND - - 0000 0110 - - Pops two values off the stack and does a bitwise-and & pushes the result onto the stack - - -
          - OR - - 0000 0111 - - Pops two integers, does a bitwise or and pushes result - - -
          - NOT - - 0000 1001 - - Bitwise inverse of value on stack - - - -
          - FLIP - - 0000 1010 - - Reverses the bit order of the value on the stack, i.e. abc->cba, 100->001, 110->011, etc. -

          - The raison d'etre for this instruction is mainly to emulate other instructions. -

          		- -
          - NOP - - 0000 1011 - - No operation, clears IDIM flag as side effect, i.e. used between two - consequtive IM instructions to push two values onto the stack. - - -
          - PUSHSPADD - - 61 - - a=sp;
          - b=popIntStack()*4;
          - pushIntStack(a+b);
          -           		- -
          - POPPCREL - - 57 - - setPc(popIntStack()+getPc()); - - -
          - SUB - - 49 - - int a=popIntStack();
          - int b=popIntStack();
          - pushIntStack(b-a);
          -           		- -
          - XOR - - 50 - -pushIntStack(popIntStack() ^ popIntStack()); - - -
          - LOADB - - 51 - - 8 bit load instruction. Really only here for compatibility with - C programming model. Also it has a big impact on DMIPS test. -

          - pushIntStack(cpuReadByte(popIntStack())&0xff); -

          		- -
          - STOREB - - 52 - - 8 bit store instruction. Really only here for compatibility with - C programming model. Also it has a big impact on DMIPS test. -

          - addr = popIntStack();
          - val = popIntStack();
          - cpuWriteByte(addr, val); -

          		 - -
          - LOADH - - 34 - - - 16 bit load instruction. Really only here for compatibility with - C programming model. -

          - - pushIntStack(cpuReadWord(popIntStack())); -

          		- -
          - STOREH - - 35 - - 16 bit store instruction. Really only here for compatibility with - C programming model. -

          -addr = popIntStack();
          - val = popIntStack();
          - cpuWriteWord(addr, val); -

          		- -
          - LESSTHAN - - 36 - - Signed comparison
          - a = popIntStack();
          - b = popIntStack();
          - pushIntStack((a < b) ? 1 : 0);
          -           		- -
          - LESSTHANOREQUAL - - 37 - - Signed comparison
          - a = popIntStack();
          - b = popIntStack();
          - pushIntStack((a <= b) ? 1 : 0); -           		- -
          - ULESSTHAN - - 37 - - Unsigned comparison
          - long a;//long is here 64 bit signed integer
          - long b;
          - a = ((long) popIntStack()) & INTMASK; // INTMASK is unsigned 0x00000000ffffffff
          - b = ((long) popIntStack()) & INTMASK;
          - pushIntStack((a < b) ? 1 : 0); -           		- -
          - ULESSTHANOREQUAL - - 39 - - Unsigned comparison
          - long a;//long is here 64 bit signed integer
          - long b;
          - a = ((long) popIntStack()) & INTMASK; // INTMASK is unsigned 0x00000000ffffffff
          - b = ((long) popIntStack()) & INTMASK;
          - pushIntStack((a <= b) ? 1 : 0); -           		- -
          - EQBRANCH - - 55 - - int compare;
          - int target;
          - target = popIntStack() + pc;
          - compare = popIntStack();
          - if (compare == 0)
          - {
          - setPc(target);
          - } else
          - {
          - setPc(pc + 1);
          - } -           		- -
          - NEQBRANCH - - 56 - - int compare;
          - int target;
          - target = popIntStack() + pc;
          - compare = popIntStack();
          - if (compare != 0)
          - {
          - setPc(target);
          - } else
          - {
          - setPc(pc + 1);
          - }
          -           		- -
          - MULT - - 41 - - Signed 32 bit multiply
          - pushIntStack(popIntStack() * popIntStack()); -           		- -
          - DIV - - 53 - - Signed 32 bit integer divide.
          - a = popIntStack();
          - b = popIntStack();
          - if (b == 0)
          - {
          - // undefined
          - } - pushIntStack(a / b);
          -           		- -
          - MOD - - 54 - - Signed 32 bit integer modulo.
          - a = popIntStack();
          - b = popIntStack();
          - if (b == 0)
          - {
          - // undefined
          - }
          - pushIntStack(a % b);
          -           		- -
          - LSHIFTRIGHT - - 42 - - unsigned shift right.
          - long shift;
          - long valX;
          - int t;
          - shift = ((long) popIntStack()) & INTMASK;
          - valX = ((long) popIntStack()) & INTMASK;
          - t = (int) (valX >> (shift & 0x3f));
          - pushIntStack(t);
          -           		- -
          - ASHIFTLEFT - - 43 - - arithmetic(signed) shift left.
          - - long shift;
          - long valX;
          - shift = ((long) popIntStack()) & INTMASK;
          - valX = ((long) popIntStack()) & INTMASK;
          - int t = (int) (valX << (shift & 0x3f));
          - pushIntStack(t);
          -           		- -
          - ASHIFTRIGHT - - 43 - - arithmetic(signed) shift left.
          - long shift;
          - int valX;
          - shift = ((long) popIntStack()) & INTMASK;
          - valX = popIntStack();
          - int t = valX >> (shift & 0x3f);
          - pushIntStack(t);
          - -           		- -
          - CALL - - 45 - - call procedure.
          -
          - int address = pop();
          - push(pc + 1);
          - setPc(address);
          -           		- -
          - CALLPCREL - - 63 - - call procedure pc relative
          -
          -int address = pop();
          - push(pc + 1);
          - setPc(address+pc);           		- -
          - EQ - - 46 - - pushIntStack((popIntStack() == popIntStack()) ? 1 : 0); - -
          - NEQ - - 48 - - pushIntStack((popIntStack() != popIntStack()) ? 1 : 0); - -
          - NEG - - 47 - - pushIntStack(-popIntStack()); - -
          -           -

          Custom startup code (aka crt0.s)

          -To minimize the size of an application, one important trick is to -strip down the startup code. The startup code contains emulation -of instructions that may never be used by a particular application. -

          -The startup code is found in the GCC source code under gcc/libgloss/zpu, -but to make the startup code more available, it has been duplicated -into zpu/sw/startup -

          -To minimize startup size, see codesize -demo. This is pretty standard GCC stuff and simple enough once you've -been over it a couple of times. - - -

          Implementing your own ZPU

          -One of the neat things about the ZPU is that the instruction set and architecture -is very small and it is easy to implement a ZPU from scratch or modify the -existing ZPU implementations. -

          -Implementing a ZPU can be done without understanding the toolchain in -detail, i.e. using exclusively HDL skills and only a rudimentary -understanding of standard GCC/GDB usage is sufficient. -

          -A few tips: -

            -
          • Run zpu_core.vhd or zpu_core_small.vhd and generate an instruction trace -from ModelSim or similar. To check that you own implementation is correctly -implemented, verify that the instruction trace for the new and old -ZPU implementations match. This gives you a simple way to do regression -tests as you develop your ZPU. -
          • To improve performance, you can add more instructions. The EMULATE instructions -are optional in HDL since they will be emulated in software if they are not -implemented in HDL. This allows you to run the ZPU executables unmodified -regardless of which EMULATE instructions you implement. -
          • Run the DMIPS test to measure your overall performance -
          • Run the histogram.perl script on the instruction trace to generate -histograms of the instructions. Profiling is essential to making -the right choices w.r.t. optimisation for your application. -
          - - -           -

          Vectors

          - - - - - - - - - - - - - - - - - -
          AddressNameDescription
          0x000Reset - 1.When the ZPU boots, this is the first instruction to be executed. -

          - 2.The stack pointer is initialised to maximum RAM address -

          0x020Interrupt - This is the entry point for interrupts. -
          0x040-Emulated instructions - Emulated opcode 34. Note that opcode 32 and opcode 33 are not normally used to emulate instructions as these memory addresses are already used by boot vector, GCC registers and the interrupt vector. -
          - -           -

          Phi memory map

          -The ZPU architecture does not define a memory map as such, but the GCC + libgloss + ecos hal library uses the -memory map below. "Phi" is just a three letter word for the particular memory layout below that came about -while developing the ZPU. -

          - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
          -

          Address

          -           		-

          Type

          -           		-

          Name

          -           		-

          Description

          -
          -

          0x080A0000

          -           		-

          Write

          -           		-

          ZPU - enable

          -           		-

          Bit - [31:1] Not used

          -

          Bit - [0] Enable ZPU operations

          -

          0 ZPU - is held in Idle mode

          -

          1 ZPU - running

          -
          -

          0x080A000C

          -           		-

          Read/

          -

          Write

          -           		-

          ZPU - Debug channel / UART to ARM7 TX

          -

          NOTE! - ZPU side

          -           		-

          Bit - [31:9] Not used

          -

          Bit - [8] TX buffer ready (valid on ready)

          -

          0 TX - buffer not ready (full)

          -

          1 TX - buffer ready

          -

          Bit - [7:0] TX byte (valid on write)

          -
          -

          0x080A0010

          -           		-

          Read

          -           		-

          ZPU - Debug channel / UART to ARM7 RX

          -

          NOTE! - ZPU side

          -           		-

          Bit - [31:9] Not used

          -

          Bit - [8] RX buffer data valid

          -

          0 RX - buffer not valid

          -

          1 RX - buffer valid

          -

          Bit - [7:0] RX byte (when valid)

          -
          -

          0x080A0014

          -           		-

          Read/

          -

          Write

          -           		-

          Counter(1)

          -           		-

          Bit - [0] Reset counter (valid for write)

          -

          0 N/A

          -

          1 Reset - counter

          -

          Bit - [1] Sample counter (valid for write)

          -

          0 N/A

          -

          1 Sample - counter

          -

          Bit - [31:0] Counter bit 31:0

          -
          -

          0x080A0018

          -           		-

          Read

          -           		-

          Counter(2)

          -           		-

          Bit - [31:0] Counter bit 63:32

          -
          -

          0x080A0020

          -           		-

          Read - / Write

          -           		-

          Global_Interrupt_mask

          -           		-

          Bit - [31:1] Not used

          -

          Bit - [0] Global intr. Mask

          -

          0 Interrupts - enabled

          -

          1 Interrupts - disabled

          -
          -

          0x080A0024

          -           		-

          Write

          -           		-

          UART_INTERRUPT_ENABLE

          -           		-

          Bit - [31:1] Not used

          -

          Bit - [0] Debug channel / UART RX interrupt enable

          -

          0 Interrupt - disable

          -

          1 Interrupt - enable

          -
          -

          0x080A0028

          -           		-

          Read

          -

          Write

          -           		-

          UART_interrupt

          -           		-

          Bit - [31:1] Not used

          -

          Bit - [0] Debug channel / UART RX interrupt pending (Read)

          -

          0 No - interrupt pending

          -

          1 Interrupt - pending

          -

          Bit - [0] Clear UART interrupt (Write)

          -

          0 N/A

          -

          1 Interrupt - cleared

          -
          -

          0x080A002C

          -           		-

          Write

          -           		-

          Timer_Interrupt_enable

          -           		-

          Bit - [31:1] Not used

          -

          Bit - [0] Timer interrupt enable

          -

          0 Interrupt - disable

          -

          1 Interrupt - enable

          -
          -

          0x080A0030

          -           		-

          Read - /

          -

          Write

          -           		-

          Timer_interrupt

          -           		-

          Bit - [31:2] Not used

          -

          Bit - [0] Timer interrupt pending (Read)

          -

          0 No - interrupt pending

          -

          1 Interrupt - pending

          -

          Bit - [1] Reset Timer counter (Write)

          -

          0 N/A

          -

          1 Timer - counter reset

          -

          Bit - [0] Clear Timer interrupt (Write)

          -

          0 N/A

          -

          1 Interrupt - cleared

          -
          -

          0x080A0034

          -           		-

          Write

          -           		-

          Timer_Period

          -           		-

          Bit - [31:0] Interrupt period (write)

          -

          Number - of clock cycles

          -

          between - timer interrupts

          -

          NOTE! - The timer will start at Timer_Periode value and count down - to zero, and generate an interrupt

          -
          -

          .0x080A0038

          -           		-

          Read

          -           		-

          Timer_Counter

          -           		-

          Bit - [31:0] Timer counter (read)

          -


          -

          -
          -


          -

          -           		-


          -

          -           		-


          -

          -           		-


          -

          -
          -


          -

          -           		-


          -

          -           		-


          -

          -           		-


          -

          -
          -


          -

          -           		-


          -

          -           		-


          -

          -           		-


          -

          -
          -


          -

          -           		-


          -

          -           		-


          -

          -           		-


          -

          -
          -           -

          Wishbone

          -In hdl/wishbone there is an implementation -of a wishbone bridge. -

          -However this wishbone bridge was used together with the hdl/zy2000 implementation -of the ZPU, which differs slightly from hdl/zpu4/core. -

          -The ZY2000 is a complete implementation of the ZPU including: DRAM, soft-MAC, wishbone bridges, GPIO subsystem, -etc. This also included an eCos HAL w/TCP/IP support. - - -

          JTAG/hardware debugger for GDB

          -The Zylin ZY1000 JTAG debugger supports -the ZPU. Contact Zylin for pricing and details. -

          -There are two debug modes in which the ZY1000 can operate: -

            -
          • Classic. Here the ZY1000 controls the CPU and examines the state. The ZY1000 has a built in -GDB server that GDB talks to. -
          • Small footprint. If there isn't enough space on the device for the ZPU *and* the JTAG -controller, then the ZY1000 can run the ZPU externally. The JTAG communication channel is -then used to peek/poke peripherals and inside the FPGA instead of the ZPU there is then -a JTAG controller that peeks and pokes the peripherals of the ZPU. There are advantages -and disadvantages of this approach: it may be unfamiliar to embedded developers and -the timing is different from the "real" ZPU(interrupts are delayed, execution speed -differse, etc.) On the other hand there are other things -which are simpler: much more RAM can be available for the ZPU during development, -better debug consoles(faster), additional peripheral(timers, etc.) is available. This -approach is somewhat unique to the ZPU as the ZPU is simple enough that it can be -implemented efficiently in this manner. -
          - - -

          Interrupts

          -The ZPU supports interrupts. -

          -To trigger an interrupt, the interrupt signal must be asserted. The ZPU does -not define any interrupt disabling mechanism, this must be implemented by the -interrupt controller and controlled via memory mapped IO. -

          -Interrupts are masked when the IDIM flag is set, i.e. -with consequtive IM instructions. -

          -The ZPU has an edge triggered interrupt. As the ZPU notices that the interrupt -is asserted, it will execute the interrupt instruction. The interrupt signal -must stay asserted until the ZPU acknowledges it. -

          -When the interrupt instruction is executed, the PC will be pushed onto the -stack and the PC will be set to the interrupt vector address (0x20). -

          -Note that the GCC compiler requires three registers r0,r1,r2,r3 for some -rather uncommon operations. These 32 registers are mapped to memory locations 0x0, -0x4, 0x8, 0xc. The default interrupt vector at address 0x20 will load the -value of these memory locations onto the stack, call _zpu_interrupt and -restore them. -

          -See zpu/hdl/zpu4/test/interrupt/ for C code and zpu/hdl/example/simzpu_interrupt.do -for simulation example. - -

          About zpu_core_small.vhd

          -The small ZPU implements the minimum instruction set. It is optimized for size and simplicity -serving as a reference in both regards. -

          -It uses a BRAM (dual port RAM w/read/write to both ports) as data & code storage and -is implemented as a simple state machine. -

          -Essentially it has three states: -

            -
          1. Fetch - starts fetch of next instruction -
          2. FetchNext - sets up operands for execute cycle -
          3. Decode - decodes instruction -
          4. Execute - well.. executes instruction -
          -The tricky bit is that there is a tiny bit of interleaving of -states since the BRAM takes a cycle to perform a fetch/store. The above is the -normal states the ZPU cycles through unless memory fetch, jumps, etc. take -place. -           -

          Speeding up the ZPU

          -There are two aspects of speeding up the ZPU: making it perform better -for a particular application and toying around with the ZPU architecture. -

          Performance tips

          -
            -
          1. Profile. Create a small sample and run in a simulator that is as close -to the real deployment as possible. zpu4/core/histogram.perl is a script -that will tell you which instructions take the most time. -
          2. Using the profile output, decide on which emulated instructions that -it makes sense to implement in HDL for your particular application. Modifying -zpu_core_small.vhd is not particularly hard. Most instructions can be -transliterated into zpu_core_small.vhd from zpu_core.vhd without too much -problem. -
          3. The memory subsystem may well turn out to be where you should concentrate -your efforts. -
          -

          Toying around with the architecture

          -Again: profile 90% of the time and spend the remaining 10% tinkering -with the architecture. -
            -
          • There is a DMIPS program you can use to measure the performance of -the ZPU in lieu of profiling a real application. The latter is obviously -a superior solution. -
          • Again: use histogram.perl to figure out which instructions you should add -in HDL. -
          • Tinker a bit with Fmax to find the maximum speed rating for your design. -
          • zpu_core_small.vhd should be ca. 1 DMIPS and zpu_core.vhd should yield -about 5-10 DMIPS before adding instructions runs out of steam. -
          -If you need to get ca. 20-50 DMIPS out of the ZPU you will have to -write a heavily pipelined architecture with caches(if you are running -against DRAM). This is *tricky*, but some proof of concept work was -done to show 20 DMIPS w/the ZPU(the actual result was discarded since -it was not complete and contained fatal flaws). -

          -Achieving above 50-100 DMIPS with the current ZPU architecture is probably -a non-starter and a more conventional RISC design makes more sense here. -

          -The unique advantages of the ZPU is size in terms of HDL & code size. - -

          Debug channel / UART

          -All self respecting embedded projects should have a debug channel -to print stuff to. Typically this is a standard RS232 or UART, but -it can also be something more exotic like a DCC JTAG channel. -

          -The point is that characters(bytes) are sent to/from the ZPU -via some terminal. -

          -The ZPU defines in the memory map a UART / debug channel. This -should be implemented by some suitable debug channel for -the device in which the ZPU is implemented. -

          -www.opencores.org has several UART implementations. This is one -of the simpler ones: - - -http://www.opencores.org/projects.cgi/web/uart/overview -

          Implementing your own UART / debug channel

          -The first thing you need to do is to choose a debug channel for your -hardware. This could be a UART, but it doesn't have to be. -

          -Secondly you should write a small HDL module that interface between -the ZPU memory map of debug channel to the UART. This should - be relatively simple as all you need to do is to let the ZPU - query the FIFO in/out for busy flag and allow the ZPU to read/write - data to the UART via the memory map. - -

          About zpu_core.vhd

          -The zpu_core.vhd has a single port memory interface. All data, code and IO is -accessed through this memory interface. -

          -It performs better(despite having less memory bandwidth than zpu_core_small.vhd) -since it implements many more instructions. -

          Compiling hello world program with the ZPU GCC toolchain

          -The ZPU comes with a standard GCC toolchain and an instruction set simulator. This allows compiling, running & debugging simple test programs. The Simulator has -some very basic peripherals defined: counter, timer interrupt and a debug output port. -

          Installation

          -
            -
          1. Install Cygwin. http://www.cygwin.com -
          2. Start Cygwin bash -
          3. unzip zputoolchain.zip -
          4. Add install/bin from zputoolchain.zip to PATH.
            -export PATH=$PATH:/install/bin -
          -

          Hello world example

          -The ZPU toolchain comes with newlib & libstdc++ support which means that many C/C++ programs can be compiled without modification. -

          - -zpu-elf-gcc -Os -zeta hello.c -o hello.elf -Wl,--relax -Wl,--gc-sections
          -zpu-elf-size hello.elf
          -           - - -           - -

          SPI flash controller (read-only)

          -This is a simple read-only SPI flash controller, with the following characteristics: - -
          -
        8. Fast-READ only implementation. -
        9. 32-bit only access -
        10. Fast sequential read access - Uses low-clock approach
          11. -
          - -

          Version

          -The current version is 1.2. This is also the first public version available. - -

          Timing overview

          - -

          Simple timing overview, with one nonsequential access to address 0x0, followed by a sequential access to address 0x4. -This simulation was done with Xilinx tools, after post-routing, and using a ZPU to access the SPI

          -
          - - -

          Image 1: Timing overview

          -
          - -On Image 2, you can see the clock almost perfectly centered on data, when we write to the SPI flash. - -
          - -

          Image 2: Issuing commands to the SPI

          -
          - -As you can see from Image 3, I assume the worst-case read delay from SPI (which is 15ns, as you can see from the marker). - -
          - -

          Image 3: Reading from the SPI

          -
          - -

          Usage

          - -Simple description of SPI controller interface: - - - - - - - - - - - - - - - - - - -
          SymbolDirectionBit widthPurpose
          adrInput24Address where to read from SPI
          dat_oOutput32Data read from SPI
          clkInput1Input clock. Used for both interface and SPI
          ceInput1Chip Enable
          rstInput1Asynchronous reset
          ackOutput1Data valid ACK
          SPI_CLKOutput1SPI output clock
          SPI_MOSIOutput1SPI output data from controller to chip
          SPI_MISOInput1SPI input data from chip to controller
          SPI_SELNOutput1SPI nSEL (deselect, active low) signal
          - - - -

          License

          -The Verilog implementation is released under BSD license. See the file itself for more licensing details. - -

          Dowload

          -Download the Verilog code here: spi_controller.v - -

          Troubleshooting

          -The current implementation is timed and optimized for myself. Your parameters might not be the same -as those I defaulted, so read the code carefully. If you have any issue let me know. - - - - - - -

          Zealot: Implementing in FPGAs

          - -The Zealot version of ZPU is a ZPU medium variant ready to be used with FPGAs. -It was tested using Xilinx Spartan 3 1500 FPGAs and was contributed by -Salvador E. Tropea. The key features are:

          - -

            -
          • Includes a very basic PHI I/O synthetizable core. -It implements the 64 bits clocks counter (timer) and the UART. This is enough -to run the DMIPS benchmark and a hello world application. I tested the UART -@ 9600 bps and @ 115200 bps.
            • -
          • The ZPU can be customized using generics. It allows the use of more -than one core in the same project without problems.
            • -
          • Implements the lshiftright instruction in hardware, this gives around -10% boost in the DMIPS benchmark (Medium version).
            • -
          • You can disable various instructions groups and let them to the -emulation soft, so you can experiment with various LUTs vs DMIPS -configurations (Medium version).
            • -
          • The medium version provides aprox. 2.6 DMIPS @ 50 MHz and the small -0.5 DMIPS @ 50 MHz.
            • -
          • Enhanced trace module, it includes the assembler for the executed -instruction and can also meassure how much stack was consumed during the -execution.
            • -
          • Includes ready to use memory images for a hello world program and the -DMIPS benchmark.
            • -
          • Memory and trace blocks outside ZPU. This provides better modularity.
            • -
          - -Simulation and implementation files are provided. You need 16 kB of BRAMs -for the "hello world" example and 32 kB for the DMIPS benchmark. The medium -version takes around 1030 slices and 3 multipliers and the small version -around 430 slices.

          - -The generics for the Zealot Medium ZPU are:

          - -

            -
          • WORD_SIZE (integer:=32) Data width, only 32 bits are really -tested/supported. Adding support for 16 bits should be simple, but the -toolchain needs to support it.
            • -
          • ADDR_W (integer:=16) Address bus width memory+I/O space. The MSB -selects the address space (1=I/O).
            • -
          • MEM_W (integer:=15) Memory address bus width. It includes program, -data and stack sections.
            • -
          • D_CARE_VAL (std_logic:='X') Value used to fill the unsused bits. -For simulations this should be '0', for synthesis this is a value that your -tools interprets as "don't care". Xilinx tools could get benefit from using -'X'. This is particularly true to assign default values and for unreached -cases. Note that I didn't find it useful.
            • -
          • MULT_PIPE (boolean:=false) Enables the multiplication pipeline. -This can allow faster clocks but will make the mult instruction slower (more -clocks consumed).
            • -
          • BINOP_PIPE (integer range 0 to 2:=0) Enables the pipeline for -the -, =, < and <= operations. This can allow faster clocks but will -make these instruction slower (more clocks consumed). This value is the -ammount of extra clocks added.
            • -
          • ENA_LEVEL0 (boolean:=true) Enables the hardware implementation of -eq, neqbranch, loadb and pushspadd instructions.
            • -
          • ENA_LEVEL1 (boolean:=true) Enables the hardware implementation of -lessthan, ulessthan, mult, storeb, callpcrel and sub instructions.
            • -
          • ENA_LEVEL2 (boolean:=false) Enables the hardware implementation of -lessthanorequal, ulessthanorequal, call and poppcrel instructions.
            • -
          • ENA_LSHR (boolean:=true) Enables the hardware implementation of -lshiftright instruction.
            • -
          • ENA_IDLE (boolean:=false) Enables the enable_i usage. This signal -can hold the CPU in an idle state if after reset this signal remains active. -When disabled the enable_i signal isn't used and the idle state is removed.
            • -
          • FAST_FETCH (boolean:=true) This version of the ZPU fetches 4 -instructions at ones (32 bits), then they are decoded (2 cycles) and finally -executed. The decoded instructions are stored in a "decode cache", the first -instruction is immediatly moved to the "current instruction" register and a -"special instruction" replaces the first slot. This "special instruction" -makes the CPU go to the fetch state. When you enable this generic the FSM -does the fetch instead of wating one clock cycle to go to the fetch state. -This makes instructions run a little bit faster, but it can cost area and/or -frequency.
            • -
          - -For more information read the 0README.txt file located inside the zealot -directory.

          - - - -

          Optimizing for code size

          -The ZPU toolchain produces highly compact code. -
            -
          1. Since the ZPU GCC toolchain supports standard ANSI C, it is easy to stumble across -functionality that takes up a lot of space. E.g. the standard printf() function is a beast. Some compilers drop e.g. floating point support -from the printf() function and thus boast a "smaller" printf() when in fact they have a non-standard printf(). newlib has a standard printf() function -and an alternative iprintf() function that works only on integers. -
          2. The ZPU ships with default startup code that works across various configurations of the ZPU, so be warned that there is some overhead that will -not occurr in the final application(anywhere between 1-4kBytes). -
          3. Compilation and linker options matter. The ZPU benefits greatly from the "-Wl,--relax -Wl,--gc-sections" options which is not used by -all architectures(e.g. GCC ARM does not implement/need -Wl,--relax). -
          -

          Small code example

          - -zpu-elf-gcc -Os -abel smallstd.c -o smallstd.elf -Wl,--relax -Wl,--gc-sections
          -zpu-elf-size small.elf
          -
          -$ zpu-elf-size small.elf
          - text data bss dec hex filename
          - 2845 952 36 3833 ef9 small.elf
          -
          -           - -

          Even smaller code example

          -If the ZPU implements the optional instructions, the RAM overhead can be reduced significantly. -

          - -zpu-elf-gcc -Os -abel crt0_phi.S small.c -o small.elf -Wl,--relax -Wl,--gc-sections -nostdlib
          -zpu-elf-size small.elf
          -
          -$ zpu-elf-size small.elf
          - text data bss dec hex filename
          - 56 8 0 64 40 small.elf
          -
          -           - - - -           -

          Installing eCos build tools

          - -tar -xjvf ecossnapshot.tar.bz2
          -tar -xjvf repository.tar.bz2
          -tar -xjvf ecostools.tar.bz2
          -# run this every time you open the shell
          -export PATH=$PATH:`pwd`/ecos-install
          -export ECOS_REPOSITORY=`pwd`/ecos/packages:`pwd`/repository
          -           -

          Compiling eCos tests

          - -ecosconfig new zeta default
          -ecosconfig tree
          -make
          -cd kernel/current
          -make tests
          -           - -

          Code size ZPU

          - -$ zpu-elf-size *
          - text data bss dec hex filename
          - 15761 1504 12060 29325 728d bin_sem0
          - 16907 1512 14436 32855 8057 bin_sem1
          - 17105 1524 30032 48661 be15 bin_sem2
          - 17186 1512 14436 33134 816e bin_sem3
          - 18986 1500 12036 32522 7f0a clock0
          - 15812 1504 13236 30552 7758 clock1
          - 25095 1972 13224 40291 9d63 clockcnv
          - 16437 1500 13224 31161 79b9 clocktruth
          - 15762 1504 12060 29326 728e cnt_sem0
          - 17124 1512 14436 33072 8130 cnt_sem1
          - 35947 1564 22512 60023 ea77 dhrystone
          - 16428 1500 13228 31156 79b4 except1
          - 15751 1504 12052 29307 727b flag0
          - 19145 1512 15624 36281 8db9 flag1
          - 20053 1516 102908 124477 1e63d fptest
          - 15998 1496 12092 29586 7392 intr0
          - 16080 1496 12200 29776 7450 kalarm0
          - 15327 1496 12036 28859 70bb kcache1
          - 15549 1496 13224 30269 763d kcache2
          - 18291 1500 12260 32051 7d33 kclock0
          - 16231 1500 13232 30963 78f3 kclock1
          - 16572 1496 13228 31296 7a40 kexcept1
          - 15618 1496 12060 29174 71f6 kflag0
          - 19287 1500 15624 36411 8e3b kflag1
          - 16887 1516 15628 34031 84ef kill
          - 16186 1496 12128 29810 7472 kintr0
          - 19724 1504 14516 35744 8ba0 klock
          - 18283 1500 14592 34375 8647 kmbox1
          - 15539 1496 12064 29099 71ab kmutex0
          - 16524 1504 15664 33692 839c kmutex1
          - 18272 1712 20348 40332 9d8c kmutex3
          - 18682 1608 20352 40642 9ec2 kmutex4
          - 15619 1496 14412 31527 7b27 ksched1
          - 15567 1496 12060 29123 71c3 ksem0
          - 17063 1500 14436 32999 80e7 ksem1
          - 15504 1496 13228 30228 7614 kthread0
          - 16167 1496 14412 32075 7d4b kthread1
          - 18281 1512 14580 34373 8645 mbox1
          - 20611 1508 14940 37059 90c3 mqueue1
          - 15672 1504 12064 29240 7238 mutex0
          - 16678 1516 15664 33858 8442 mutex1
          - 17694 1508 16868 36070 8ce6 mutex2
          - 18203 1720 20344 40267 9d4b mutex3
          - 16352 1508 14428 32288 7e20 release
          - 15890 1500 14412 31802 7c3a sched1
          - 44196 1612 286332 332140 5116c stress_threads
          - 17891 1524 16864 36279 8db7 sync2
          - 16943 1512 15644 34099 8533 sync3
          - 15467 1496 13064 30027 754b thread0
          - 16134 1496 14420 32050 7d32 thread1
          - 17560 1512 15636 34708 8794 thread2
          - 16279 1500 24028 41807 a34f thread_gdb
          - 17051 1504 20376 38931 9813 timeslice
          - 17146 1504 21564 40214 9d16 timeslice2
          - 37313 1512 422380 461205 70995 tm_basic
          -           -

          Code size ARM (non-thumb)

          -Thumb does not compile out of the box w/AT91 EB40a for which this test was made.

          - -$ arm-elf-size *
          - text data bss dec hex filename
          - 25204 692 16976 42872 a778 bin_sem0
          - 26644 700 22096 49440 c120 bin_sem1
          - 26996 712 55584 83292 1455c bin_sem2
          - 27008 700 22100 49808 c290 bin_sem3
          - 28992 688 16944 46624 b620 clock0
          - 25456 692 19532 45680 b270 clock1
          - 34572 1160 19520 55252 d7d4 clockcnv
          - 26224 688 19508 46420 b554 clocktruth
          - 25204 692 16976 42872 a778 cnt_sem0
          - 26888 700 22108 49696 c220 cnt_sem1
          - 44180 752 27416 72348 11a9c dhrystone
          - 26088 688 19520 46296 b4d8 except1
          - 25236 692 16968 42896 a790 flag0
          - 29532 700 24668 54900 d674 flag1
          - 29508 704 109652 139864 22258 fptest
          - 25932 684 17016 43632 aa70 intr0
          - 25824 684 17112 43620 aa64 kalarm0
          - 24728 684 16956 42368 a580 kcache1
          - 25168 684 19512 45364 b134 kcache2
          - 28112 688 17168 45968 b390 kclock0
          - 25976 688 19524 46188 b46c kclock1
          - 26372 684 19512 46568 b5e8 kexcept1
          - 25140 684 16968 42792 a728 kflag0
          - 29824 688 24660 55172 d784 kflag1
          - 26896 704 24656 52256 cc20 kill
          - 26088 684 17028 43800 ab18 kintr0
          - 30812 692 22176 53680 d1b0 klock
          - 28504 688 22260 51452 c8fc kmbox1
          - 24984 684 16984 42652 a69c kmutex0
          - 26504 692 24704 51900 cabc kmutex1
          - 28792 900 34892 64584 fc48 kmutex3
          - 29264 796 34896 64956 fdbc kmutex4
          - 25240 684 22084 48008 bb88 ksched1
          - 25044 684 16968 42696 a6c8 ksem0
          - 26988 688 22100 49776 c270 ksem1
          - 25028 684 19512 45224 b0a8 kthread0
          - 25996 684 22080 48760 be78 kthread1
          - 28552 700 22252 51504 c930 mbox1
          - 31324 696 22612 54632 d568 mqueue1
          - 25108 692 16980 42780 a71c mutex0
          - 26464 704 24700 51868 ca9c mutex1
          - 27624 696 27280 55600 d930 mutex2
          - 28596 908 34884 64388 fb84 mutex3
          - 26156 696 22100 48952 bf38 release
          - 25460 688 22084 48232 bc68 sched1
          - 56356 828 45892 103076 192a4 stress_threads
          - 27900 712 27288 55900 da5c sync2
          - 26760 700 24692 52152 cbb8 sync3
          - 24924 684 19356 44964 afa4 thread0
          - 25868 684 22084 48636 bdfc thread1
          - 27452 700 24680 52832 ce60 thread2
          - 26136 688 42704 69528 10f98 thread_gdb
          - 27212 692 34916 62820 f564 timeslice
          - 52728 700 123332 176760 2b278 tm_basic
          -           - - - -           -

          Next generation ZPU

          -Based on feedback here is a list of a tenuous "consensus" for the next generation -of the ZPU with some tentative ideas on implementation. -

          Goals

          -
            -
          1. Reduce minimum code size footprint, i.e. BRAM code overhead. Non-trivial -usable applications in 4kBytes of BRAM (single BRAM block). -
          2. Reduce minimum FPGA logic footprint by 20% or more. Goal <300 LUT for -32 bit ZPU -
          3. Weed out unecessary ZPU variations -
          -

          Best current ideas on how to reach these goals

          -
            -
          1. Introduce 16 entry 32 bit LIFO for instructions that change sp today. LOADSP/STORESP/ADDSP -refer to the normal stack but add/get values from the LIFO in addition.

            - -loadsp n ; load value from memory at address "sp + n" and put it into the LIFO.
            -im m ; put value into LIFO register
            -add ; get two values from LIFO register, put back result.
            -             -

            -NB! none of the instructions above change sp!!! -

            -If the LIFO is full, putting a value into the LIFO has no defined behaviour. Getting a value -from an empty LIFO has no defined behaviour. -

            -GCC will use 8 slots, instruction emulation and interrupts owns the remaining 8 slots. - -

          2. Add single entry for unknown instructions. PC and unsupported instruction is -pushed onto stack before jumping to unknown instruction vector. This makes it possible -to write denser microcode for missing instructions. For emulated opcodes that are -not in use, the microcode can more easily be disabled. Determining -that e.g. MULT is not used, can be a bit tricky, but disabling it is easy. -

            -The unsupported vectory entry address is 0x10. -

          3. GCC needs 4 registers. These are today mapped to memory. What addresses to use? -Today memory address 0x00-0x0f inclusive are used for this purpose. Introduce emulated -instruction to load/store these registers? That would allow using either hardware or -memory registers. -
          4. Single entry for *all* unknown instructions does not limit emulation to the -EMULATE instructions today, but instructions such as OR, LOADSP, STORESP, ADDSP, -etc. can also be emulated. This opens up for further reduction in logic usage. -
          5. The single entry for all unknown instructions will make it easier to -write a compact custom crt0.s to fit an instruction subset. -
          6. The interrupt is basically an unknown instruction that is injected into -the execution stream. -
          7. Add floating point add and mult. FADD & FMULT. Option to generate the instructions -from the compiler. -
          8. Strip away unused instructions from GCC and add options to GCC for not -emitting more advanced instructions. This will e.g. convert MULT/DIV into -function calls to libgcc and thus make it easier to determine that -microcode is not needed. -
          -

          Next generation ZPU HDL work

          -
            -
          1. Incorporate feedback on FPGA tricks to reduce memory usage: do not -use asynchronous reset?, use BRAMs in synchronous mode to reduce -complexity of state machine?, seperate code/data bus? Reduce -instruction set further. Goal: <300 LUT's for 32 bit ZPU -
          2. Will someone be willing to contribute a heavily pipelined ZPU? -For this to make sense, the performance must hit 20 DMIPS w/DRAM & cache. -This ZPU could run a TCP/IP stack with relevant performance to compete -with stripped down ARM7 type systems. -
          - -           -

          Download source code

          -

          -

          The simplest way to get the ZPU HDL source and tools is to check -it out from CVS:

          -

          cvs -d :pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous co -zpu/zpu

          -

          Start by reading zpu/zpu/hdl/index.html

          - -           -

          Creating a patch

          -


          Please submit changes to the           zylin-zpu mailing list as a patch. -

          -
            -
          1. Merge your changes with CVS HEAD. -
          2. Update the FreeBSD or GPL copyright with your name in the case -of non-trivial changes. If in doubt, add the copyright. -
          3. Add an entry to zpu/ChangeLog with date, your name, email, the -files you changed and a comment. -
          4. cd zpu
            cvs diff -upN . > mypatch.txt             -
          5. Email it to zylin-zpu mailing list. Attach it -as an uncompressed .txt file -
          - -

          Getting help - mailing list

          -The place to get help is the           zylin-zpu mailing list - -

          Register stack

          -In order to reduce the size and complexity of the small ZPU, a register stack -has been put forward. It remains an open question as to whether this can -indeed reduce size and improve performance of the ZPU. -

          -Terminology: "stack" is the normal stack in memory pointed to -by the sp register. "register stack" is a different stack that is -not connected to memory directly or associated with the "stack". -

          -The idea is to push and pop the register stack such that bandwidth -is increased and complexity of memory access logic is reduced. -

          -Another clever bit is to mask interrupts while this stack is -not empty such that this stack never has to be -saved. It's depth would be fixed to something natural -for an FPGA, say 16 deep(doesn't that translate to a single -LUT for a bit?). - -

          Example of internal stack

          -im 1 ; push onto register stack
          -loadsp N ; load from memory pointed to by sp+N, push onto register stack
          -add ; pop values from register stack and add, push onto register stack
          - -

          Quick summary of instruction operation with register stack

          -This is not a "formal" definition of the instruction set, but should -give a pretty good idea of what the modified instruction looks like. -

          -Read up on the current definition of instructions and consider the -list below a guide to what changes have been made to fit a register -stack. The list is not complete, but covers the important categories -of instructions. If it is clear how the ADD instruction changed, -then it should be obvious how the AND isntruction must be similarly -modified. -

          -Note also that there are lots of tiny problems that have to be ironed -out before the instruction set and emulation can work. Below is just -a first stab, which hopefully is good enough to evaluate the approach. - - - - - - - - - - - - - - -
          IM push onto/modify top of register stack
          STORESP pop register stack store to memory SP+N
          LOADSP load memory SP+N push onto register stack
          EMULATE push PC+1 onto register stack and jump to EMULATE vector
          PUSHPC push pc onto register stack
          POPPC pop pc from register stack
          LOAD pop address from register stack, load from memory address, push onto register stack
          STORE pop register stack 2x store value to memory
          PUSHSP push sp onto register stack
          POPSP pop sp from register stack
          POPPC pop pc from register stack
          ADD pop 2x register stack, add, push to register stack
          NOT pop register stack, bit inverse value, push onto register stack
          -Emulate instructions and calling convention may have to change substantially. - - - \ No newline at end of file + + +

          This Document

          +This is a snapshot of the zpu/zpu/docs/zpu_arch.html document in CVS. +

          +Several of the links will only work if you have checked out the zpu/zpu tree from opencores CVS. See Download below. +

          Index

          + + +
          + + +

          Introduction

          +

          TODO a new welcome message indicating goals/direction of project.

          +

          The worlds smallest 32 bit CPU with GCC toolchain. +

          Sincerely,

          +

          Øyvind Harboe
          Zylin AS +

          + +           +

          License

          +

          The project includes HDL, GCC toolchain and eCos HAL. + +

          The ZPU has a BSD license for the HDL and GPL for the rest. +This allows users to implement any version of the ZPU they want in +commercial products, but if improvements are done to the architecture +as such, then they need to be contributed back. +

          + +

          Per Jan 1. 2008, Zylin has the Copyright for the ZPU, i.e. Zylin +is free to decide that the ZPU shall have a BSD license for HDL + GPL +for the rest.

          + +           +

          Survey

          +

          Please take the time to fill in this short survey so we can gather +information about where the ZPU can be the most useful:

          +

          http://www.zylin.com/zpusurvey.html

          + + +

          Features

          +           + + +

          Status

          +
            +
          • HDL works +
          • GCC toolchain works +
          • eCos HAL works +
          +

          ... but there is a long TODO list

          +

          Expect churn as we converge onto a shorter list of implementations. + + +

          Download source code

          +

          +

          To get the ZPU HDL source and tools, check it out from CVS:

          +

          cvs -d :pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous co +zpu/zpu

          +There are more instructions +          here +and +here +. + +

          As of 01 JAN 2009, if you check out all of zpu it is about 200MB, and includes more than you need. It is recommended that you only checkout zpu/zpu. + + +

          Creating a patch

          +

          Please submit changes to the zylin-zpu mailing list as a patch. +

          +
            +
          1. Merge your changes with CVS HEAD. +
          2. Update the FreeBSD or GPL copyright with your name in the case +of non-trivial changes. If in doubt, add the copyright. +
          3. Add an entry to zpu/ChangeLog with date, your name, email, the +files you changed and a comment. +
          4. cd zpu
            cvs diff -upN . > mypatch.txt             +
          5. Email it to zylin-zpu mailing list. Attach it +as an uncompressed .txt file +
          + + +

          Getting help - mailing list

          +

          The place to get help is the zylin-zpu mailing list + +

          + +

          + + + +

          Architecture

          +The ZPU is a zero operand, or stack based CPU. The opcodes have a fixed width of 8 bits. +

          +Example: +

          +

          + + IM 5 ; push 5 onto the stack + LOADSP 20 ; push value at memory location SP+20 + ADD ; pop 2 values on the stack and push the result + +
          +As can be seen, a lot of information is packed into the 8 bits, e.g. the IM instruction pushes a 7 bit signed integer onto the stack. +

          +The choice of opcodes is intimately tied to the GCC toolchain capabilities. +

          +

          + + /* simple program showing some interesting qualities of the ZPU toolchain */ + void bar(int); + int j; + void foo(int a, int b, int c) + { + a++; + b+=a; + j=c; + bar(b); + } + +foo: + loadsp 4 ; a is at memory location SP+4 + im 1 + add + loadsp 12 ; b is now at memory location SP+12 + add + loadsp 16 ; c is now at memory location SP+16 + im 24 ; «j» is at absolute memory location 24. +; Notice how the ZPU toolchain is using link-time relaxation +; to squeeze the address into a single no-op + store + im 22 ; the fn bar is at address 22 + call + im 12 + return ; 12 bytes of arguments + return from fn + +
          + +           +

          Instruction set

          +

          A base set of instructions must be implemented in RTL, but the rest may be implemented as RTL or as microcode. This allows a tradeoff of core size vs code size and performance. +

          The instructions that may be implemented in RTL or microcode are referred to as emulated instructions. The microcode is in crt0.s. The implementation determines which instructions run as microcode. +

          All operations are 32 bit wide. +

          TODO Is the table broken? Fix it. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
          NameOpcodeDescriptionDefinition
          + BREAKPOINT + + 00000000 + + The debugger sets a memory location to this value to set a breakpoint. Once a JTAG-like + debugger interface is added, it will be convenient to be able to distinguish + between a breakpoint and an illegal(possibly emulated) instruction. + + No effect on registers +
          + IM + + 1xxx xxxx + + Pushes 7 bit sign extended integer and sets the a «instruction decode interrupt mask» flag(IDIM). +

          + If the IDIM flag is already set, this instruction shifts the value on the stack left by 7 bits and stores the 7 bit immediate value into the lower 7 bits. +

          + Unless an instruction is listed as treating the IDIM flag specially, it should be assumed to clear the IDIM flag. +

          + To push a 14 bit integer onto the stack, use two consecutive IM instructions. +

          + If multiple immediate integers are to be pushed onto the stack, they must be interleaved with another instruction, typically NOP. +

          		+ +pc <= pc + 1
          +idim <= 1
          +if (idim=0) then
          + sp <= sp - 1;
          + for i in wordSize-1 downto 7 loop
          + mem(sp)(i) <= opcode(6)
          + end loop
          + mem(sp)(6 downto 0) <= opcode(6 downto 0)
          +else
          + mem(sp)(wordSize-1 downto 7) <= mem(sp)(wordSize-8 downto 0)
          + mem(sp)(6 downto 0) <= opcode(6 downto 0)
          +end if +           + +
          + STORESP + + 010x xxxx + + Pop value off stack and store it in the SP+xxxxx*4 memory location, where xxxxx is a positive integer. + +
          + LOADSP + + 011x xxxx + + Push value of memory location SP+xxxxx*4, where xxxxx is a positive integer, onto stack. + + +
          + ADDSP + + 0001 xxxx + + Add value of memory location SP+xxxx*4 to value on top of stack. + + +
          + EMULATE + + 001x xxxx + + Push PC to stack and set PC to 0x0+xxxxx*32. This is used to emulate opcodes. See + zpupgk.vhd for list of emulate opcode values used. zpu_core.vhd contains + reference implementations of these instructions rather than letting the ZPU execute the EMULATE instruction +

          + One way to improve performance of the ZPU is to implement some of + the EMULATE instructions. + +

          		+ +
          + PUSHPC + + emulated + + Pushes program counter onto the stack. + + +
          + POPPC + + 0000 0100 + + Pops address off stack and sets PC + + +
          + LOAD + + 0000 1000 + + Pops address stored on stack and loads the value of that address onto stack. +

          + Bit 0 and 1 of address are always treated as 0(i.e. ignored) by + the HDL implementations and C code is guaranteed by the programming + model never to use 32 bit LOAD on non-32 bit aligned addresses(i.e. + if a program does this, then it has a bug). +

          		+ +
          + STORE + + 0000 1100 + + Pops address, then value from stack and stores the value into the memory location of the address. +

          + Bit 0 and 1 of address are always treated as 0 +

          		+ +
          + PUSHSP + + 0000 0010 + + Pushes stack pointer. + + +
          + POPSP + + 0000 1101 + + Pops value off top of stack and sets SP to that value. Used to allocate/deallocate space on stack for variables or when changing threads. + + +
          + ADD + + 0000 0101 + + Pops two values on stack adds them and pushes the result + + +
          + AND + + 0000 0110 + + Pops two values off the stack and does a bitwise-and & pushes the result onto the stack + + +
          + OR + + 0000 0111 + + Pops two integers, does a bitwise or and pushes result + + +
          + NOT + + 0000 1001 + + Bitwise inverse of value on stack + + + +
          + FLIP + + 0000 1010 + + Reverses the bit order of the value on the stack, i.e. abc->cba, 100->001, 110->011, etc. +

          + The raison d'etre for this instruction is mainly to emulate other instructions. +

          		+ +
          + NOP + + 0000 1011 + + No operation, clears IDIM flag as side effect, i.e. used between two + consecutive IM instructions to push two values onto the stack. + + +
          + PUSHSPADD + + 61 + + a=sp;
          + b=popIntStack()*4;
          + pushIntStack(a+b);
          +           		+ +
          + POPPCREL + + 57 + + setPc(popIntStack()+getPc()); + + +
          + SUB + + 49 + + int a=popIntStack();
          + int b=popIntStack();
          + pushIntStack(b-a);
          +           		+ +
          + XOR + + 50 + +pushIntStack(popIntStack() ^ popIntStack()); + + +
          + LOADB + + 51 + + 8 bit load instruction. Really only here for compatibility with + C programming model. Also it has a big impact on DMIPS test. +

          + pushIntStack(cpuReadByte(popIntStack())&0xff); +

          		+ +
          + STOREB + + 52 + + 8 bit store instruction. Really only here for compatibility with + C programming model. Also it has a big impact on DMIPS test. +

          + addr = popIntStack();
          + val = popIntStack();
          + cpuWriteByte(addr, val); +

          		 + +
          + LOADH + + 34 + + + 16 bit load instruction. Really only here for compatibility with + C programming model. +

          + + pushIntStack(cpuReadWord(popIntStack())); +

          		+ +
          + STOREH + + 35 + + 16 bit store instruction. Really only here for compatibility with + C programming model. +

          +addr = popIntStack();
          + val = popIntStack();
          + cpuWriteWord(addr, val); +

          		+ +
          + LESSTHAN + + 36 + + Signed comparison
          + a = popIntStack();
          + b = popIntStack();
          + pushIntStack((a < b) ? 1 : 0);
          +           		+ +
          + LESSTHANOREQUAL + + 37 + + Signed comparison
          + a = popIntStack();
          + b = popIntStack();
          + pushIntStack((a <= b) ? 1 : 0); +           		+ +
          + ULESSTHAN + + 37 + + Unsigned comparison
          + long a;//long is here 64 bit signed integer
          + long b;
          + a = ((long) popIntStack()) & INTMASK; // INTMASK is unsigned 0x00000000ffffffff
          + b = ((long) popIntStack()) & INTMASK;
          + pushIntStack((a < b) ? 1 : 0); +           		+ +
          + ULESSTHANOREQUAL + + 39 + + Unsigned comparison
          + long a;//long is here 64 bit signed integer
          + long b;
          + a = ((long) popIntStack()) & INTMASK; // INTMASK is unsigned 0x00000000ffffffff
          + b = ((long) popIntStack()) & INTMASK;
          + pushIntStack((a <= b) ? 1 : 0); +           		+ +
          + EQBRANCH + + 55 + + int compare;
          + int target;
          + target = popIntStack() + pc;
          + compare = popIntStack();
          + if (compare == 0)
          + {
          + setPc(target);
          + } else
          + {
          + setPc(pc + 1);
          + } +           		+ +
          + NEQBRANCH + + 56 + + int compare;
          + int target;
          + target = popIntStack() + pc;
          + compare = popIntStack();
          + if (compare != 0)
          + {
          + setPc(target);
          + } else
          + {
          + setPc(pc + 1);
          + }
          +           		+ +
          + MULT + + 41 + + Signed 32 bit multiply
          + pushIntStack(popIntStack() * popIntStack()); +           		+ +
          + DIV + + 53 + + Signed 32 bit integer divide.
          + a = popIntStack();
          + b = popIntStack();
          + if (b == 0)
          + {
          + // undefined
          + } + pushIntStack(a / b);
          +           		+ +
          + MOD + + 54 + + Signed 32 bit integer modulo.
          + a = popIntStack();
          + b = popIntStack();
          + if (b == 0)
          + {
          + // undefined
          + }
          + pushIntStack(a % b);
          +           		+ +
          + LSHIFTRIGHT + + 42 + + unsigned shift right.
          + long shift;
          + long valX;
          + int t;
          + shift = ((long) popIntStack()) & INTMASK;
          + valX = ((long) popIntStack()) & INTMASK;
          + t = (int) (valX >> (shift & 0x3f));
          + pushIntStack(t);
          +           		+ +
          + ASHIFTLEFT + + 43 + + arithmetic(signed) shift left.
          + + long shift;
          + long valX;
          + shift = ((long) popIntStack()) & INTMASK;
          + valX = ((long) popIntStack()) & INTMASK;
          + int t = (int) (valX << (shift & 0x3f));
          + pushIntStack(t);
          +           		+ +
          + ASHIFTRIGHT + + 43 + + arithmetic(signed) shift left.
          + long shift;
          + int valX;
          + shift = ((long) popIntStack()) & INTMASK;
          + valX = popIntStack();
          + int t = valX >> (shift & 0x3f);
          + pushIntStack(t);
          + +           		+ +
          + CALL + + 45 + + call procedure.
          +
          + int address = pop();
          + push(pc + 1);
          + setPc(address);
          +           		+ +
          + CALLPCREL + + 63 + + call procedure pc relative
          +
          +int address = pop();
          + push(pc + 1);
          + setPc(address+pc);           		+ +
          + EQ + + 46 + + pushIntStack((popIntStack() == popIntStack()) ? 1 : 0); + +
          + NEQ + + 48 + + pushIntStack((popIntStack() != popIntStack()) ? 1 : 0); + +
          + NEG + + 47 + + pushIntStack(-popIntStack()); + +
          + + +

          Interrupts

          +The ZPU supports interrupts. +

          +To trigger an interrupt, the interrupt signal must be asserted. The ZPU does +not define any interrupt disabling mechanism, this must be implemented by the +interrupt controller and controlled via memory mapped IO. +

          +Interrupts are masked when the IDIM flag is set, i.e. +with consecutive IM instructions. +

          +The ZPU has an edge triggered interrupt. As the ZPU notices that the interrupt +is asserted, it will execute the interrupt instruction. The interrupt signal +must stay asserted until the ZPU acknowledges it. +

          +When the interrupt instruction is executed, the PC will be pushed onto the +stack and the PC will be set to the interrupt vector address (0x20). +

          +Note that the GCC compiler requires three registers r0,r1,r2,r3 for some +rather uncommon operations. These 32 registers are mapped to memory locations 0x0, +0x4, 0x8, 0xc. The default interrupt vector at address 0x20 will load the +value of these memory locations onto the stack, call _zpu_interrupt and +restore them. +

          +See zpu/hdl/zpu4/test/interrupt/ for C code and zpu/hdl/example/simzpu_interrupt.do +for simulation example. + + +

          Custom startup code (aka crt0.s)

          +To minimize the size of an application, one important trick is to +strip down the startup code. The startup code contains microcode for emulation +of instructions that may never be used by a particular application, or are made redundant because the instructions are implemented in RTL. +

          +The startup code is found in the GCC source code under gcc/libgloss/zpu, +but to make the startup code more available, it has been duplicated +into zpu/sw/startup +

          +On the TODO list is work to make it easier to reduce code size. +

          +TODO is the following actually useful? if not remove or elaborate. +

          +To minimize startup size, see codesize +demo. This is pretty standard GCC stuff and simple enough once you've +been over it a couple of times. + + + +

          Vectors

          + + + + + + + + + + + + + + + + + +
          AddressNameDescription
          0x000Reset + 1.When the ZPU boots, this is the first instruction to be executed. +
          + 2.The stack pointer is initialised to maximum RAM address +
          0x020Interrupt + This is the entry point for interrupts. +
          0x040-Emulated instructions + Emulated opcode 34. Note that opcode 32 and opcode 33 are not normally used to emulate instructions as these memory addresses are already used by boot vector, GCC registers and the interrupt vector. +
          + +
          + +           +

          Core Implementations

          +zpu4 (superseding zpu3) are original work by Øyvind Harboe. All other implementations derive from zpu4. +

          +High on the TODO list is to reduce the number of implementations taking the best from all. For example interrupts are not universally implemented, IO naming is inconsistent and memory architectures differ. +

          +Ultimately we should try to get closer to the opencores coding standard. You can find the document in the opencores cvsroot/common. +

          +For now if you are starting a design, zpu4 or zealot are probably the safest. zealot offers more customization through generics, but lacks interrupts. zpu4 gets more attention. Take your pick. + + +

          Performance Summary

          + +TODO fill in performance table. +

          + + + + + + + + + + + + + + + + + + + + + +

          CORE/Config

          Spartan3e

          Cyclone3

          DMIPS @ 50MHz

          +zpu4 small
+maxAddrBit=?
+...
+
          		 
          +? LUT
+? REG
+? MULT18x18
+? BRAM
+? fmax
+
          		 
          +? LUT
+? REG
+? MULT18x18
+? M4K
+? fmax
+

          ???

          zpu4 medium

          		 
          +? LUT
+? REG
+? MULT18x18
+? BRAM
+? fmax
+
          		 
          +? LUT
+? REG
+? MULT18x18
+? M4K
+? fmax
+

          ???

          + +           +

          zpu4 small

          +Found in zpu/zpu/hdl/zpu4/core/zpu_core_small.vhd +

          +The small ZPU4 implements the minimum instruction set. It is optimized for size and simplicity +serving as a reference in both regards. +

          +It uses a BRAM (dual port RAM w/read/write to both ports) as data & code storage and +is implemented as a simple state machine. +

          +Essentially it has three states: +

            +
          1. Fetch - starts fetch of next instruction +
          2. FetchNext - sets up operands for execute cycle +
          3. Decode - decodes instruction +
          4. Execute - well.. executes instruction +
          +The tricky bit is that there is a tiny bit of interleaving of +states since the BRAM takes a cycle to perform a fetch/store. The above is the +normal states the ZPU cycles through unless memory fetch, jumps, etc. take +place. + + +

          zpu4 medium

          +Found in           zpu/zpu/hdl/zpu4/core/zpu_core.vhd +

          +The medium ZPU4 has a single port memory interface. All data, code and IO is +accessed through this memory interface. +

          +It performs better(despite having less memory bandwidth than zpu_core_small.vhd) +since it implements many more instructions. + + +

          Alvaro's pipelined ZPU

          +All the rave in the mailing list. TBA. + + +

          Zealot

          +Small found in           zpu/zpu/hdl/zealot/zpu_small.vhdl +

          +Medium found in zpu/zpu/hdl/zealot/zpu_medium.vhdl +

          +README found in zpu/zpu/hdl/zealot/0README.txt +

          +The Zealot version of ZPU was contributed by Salvador E. Tropea. +

          +The key features are: + + +

            +
          • Includes a very basic PHI I/O synthesizable core. +It implements the 64 bits clocks counter (timer) and the UART. This is enough +to run the DMIPS benchmark and a hello world application. I tested the UART +@ 9600 bps and @ 115200 bps.
            • +
          • The ZPU can be customized using generics. It allows the use of more +than one core in the same project without problems.
            • +
          • Implements the lshiftright instruction in hardware, this gives around +10% boost in the DMIPS benchmark (Medium version).
            • +
          • You can disable various instructions groups and let them to the +emulation soft, so you can experiment with various LUTs vs DMIPS +configurations (Medium version).
            • +
          • The medium version provides aprox. 2.6 DMIPS @ 50 MHz and the small +0.5 DMIPS @ 50 MHz.
            • +
          • Enhanced trace module, it includes the assembler for the executed +instruction and can also measure how much stack was consumed during the +execution.
            • +
          • Includes ready to use memory images for a hello world program and the +DMIPS benchmark.
            • +
          • Memory and trace blocks outside ZPU. This provides better modularity.
            • +
          + +Simulation and implementation files are provided. You need 16 kB of BRAMs +for the "hello world" example and 32 kB for the DMIPS benchmark. The medium +version takes around 1030 slices and 3 multipliers and the small version +around 430 slices.

          + +The generics for the Zealot Medium ZPU are:

          + +

            +
          • WORD_SIZE (integer:=32) Data width, only 32 bits are really +tested/supported. Adding support for 16 bits should be simple, but the +toolchain needs to support it.
            • +
          • ADDR_W (integer:=16) Address bus width memory+I/O space. The MSB +selects the address space (1=I/O).
            • +
          • MEM_W (integer:=15) Memory address bus width. It includes program, +data and stack sections.
            • +
          • D_CARE_VAL (std_logic:='X') Value used to fill the unsused bits. +For simulations this should be '0', for synthesis this is a value that your +tools interprets as "don't care". Xilinx tools could get benefit from using +'X'. This is particularly true to assign default values and for unreached +cases. Note that I didn't find it useful.
            • +
          • MULT_PIPE (boolean:=false) Enables the multiplication pipeline. +This can allow faster clocks but will make the mult instruction slower (more +clocks consumed).
            • +
          • BINOP_PIPE (integer range 0 to 2:=0) Enables the pipeline for +the -, =, < and <= operations. This can allow faster clocks but will +make these instruction slower (more clocks consumed). This value is the +amount of extra clocks added.
            • +
          • ENA_LEVEL0 (boolean:=true) Enables the hardware implementation of +eq, neqbranch, loadb and pushspadd instructions.
            • +
          • ENA_LEVEL1 (boolean:=true) Enables the hardware implementation of +lessthan, ulessthan, mult, storeb, callpcrel and sub instructions.
            • +
          • ENA_LEVEL2 (boolean:=false) Enables the hardware implementation of +lessthanorequal, ulessthanorequal, call and poppcrel instructions.
            • +
          • ENA_LSHR (boolean:=true) Enables the hardware implementation of +lshiftright instruction.
            • +
          • ENA_IDLE (boolean:=false) Enables the enable_i usage. This signal +can hold the CPU in an idle state if after reset this signal remains active. +When disabled the enable_i signal isn't used and the idle state is removed.
            • +
          • FAST_FETCH (boolean:=true) This version of the ZPU fetches 4 +instructions at ones (32 bits), then they are decoded (2 cycles) and finally +executed. The decoded instructions are stored in a "decode cache", the first +instruction is immediately moved to the "current instruction" register and a +"special instruction" replaces the first slot. This "special instruction" +makes the CPU go to the fetch state. When you enable this generic the FSM +does the fetch instead of waiting one clock cycle to go to the fetch state. +This makes instructions run a little bit faster, but it can cost area and/or +frequency.
            • +
          + + + +

          ZY2000

          +Found in           zpu/zpu/hdl/zy2000/zpu_core.vhd +Modified version of zpu4 medium for use with a wishbone bridge. +

          +The ZY2000 is a complete implementation including: ZPU, DRAM, soft-MAC, wishbone bridges, GPIO subsystem, etc. This also included an eCos HAL w/TCP/IP support. + + +

          Verilog translation

          +Found in zpu/wip/ZPU_CORE/src/zpu_core.v +

          +The verilog version of ZPU (zpu4) was contributed by Jurij Kostasenko. No-one appears to be maintaining it, but it should be a useful starting point for further work. There are some useful scripts there. + + +

          Implementing your own ZPU

          +One of the neat things about the ZPU is that the instruction set and architecture +is very small and it is easy to implement a ZPU from scratch or modify the +existing ZPU implementations. +

          +Implementing a ZPU can be done without understanding the toolchain in +detail, i.e. using exclusively HDL skills and only a rudimentary +understanding of standard GCC/GDB usage is sufficient. +

          +A few tips: +

            +
          • Run zpu_core.vhd or zpu_core_small.vhd and generate an instruction trace +from ModelSim or similar. To check that you own implementation is correctly +implemented, verify that the instruction trace for the new and old +ZPU implementations match. This gives you a simple way to do regression +tests as you develop your ZPU. +
          • To improve performance, you can add more instructions. The EMULATE instructions +are optional in HDL since they will be emulated in software if they are not +implemented in HDL. This allows you to run the ZPU executables unmodified +regardless of which EMULATE instructions you implement. +
          • Run the DMIPS test to measure your overall performance +
          • Run the histogram.perl script on the instruction trace to generate +histograms of the instructions. Profiling is essential to making +the right choices w.r.t. optimization for your application. +
          + +
          + + +           +

          Reference Designs

          +The zpu core is independent of IO and memory architecture. Here are three levels of reference designs a user can refer to in order to get started in their own design, regardless of chosen core. +

          +TODO converge on a single IO structure for core implementations. +

          +TODO re-org CVS to make it easy to keep appropriate SW, RTL(verilog and VHDL) , scripts, verification stuff together. +

          + + +

          Minimal (core+RAM)

          +The minimum design is a zpu core with true dual port RAMs attached. This is handy for size/fmax trial in a particular FPGA, and maybe HDL regression. Maybe not a very useful starting point, unless you can DMA all you IO. +

          +TODO provide FPGA scripts. +

          +TODO provide HDL regression environment. + + +

          Basic (core+RAM+UART+Timer)

          +The minimum design required for hello_world and DMIPS applications. Requires more RAM and a UART (or something) for stdio. This is handy as a starting point for a new users design, and to run DMIPS evaluation, and maybe HDL regression. +

          +TODO provide FPGA scripts. +

          +TODO provide HDL regression environment. + + +

          SOC (core+RAM+Wishbone+++)

          +Large design(s) for one or more chosen eval board. Features dictated by board and available IP. + + +

          Common - RAM models

          +single (1RW), simple dual(1R+1W), true dual(1RW+1RW), and xilinx distributed dual(1RW+1R) RAM models. Parameterized depth / width, and loadable from file. The goal is that ROM be independent of verilog/VHDL implementation of RAM. +

          +TODO RAM model contribution needed. What is in opencore/common is not adequate. + + +

          Common - Wishbone

          +In hdl/wishbone there is an implementation +of a wishbone bridge. It was designed to work with ZY2000 +

          +TODO make wishbone bridge re-usable with all cores + + +

          Common - UART

          + +All self respecting embedded projects should have a debug channel +to print stuff to. Typically this is a standard RS232 or UART, but +it can also be something more exotic like a DCC JTAG channel. +

          +The point is that characters(bytes) are sent to/from the ZPU +via some terminal. +

          +The ZPU defines in the memory map a UART / debug channel. This +should be implemented by some suitable debug channel for +the device in which the ZPU is implemented. +

          +www.opencores.org has several UART implementations. This is one +of the simpler ones: + + +http://www.opencores.org/projects.cgi/web/uart/overview +

          Implementing your own UART / debug channel

          +The first thing you need to do is to choose a debug channel for your +hardware. This could be a UART, but it doesn't have to be. +

          +Secondly you should write a small HDL module that interface between +the ZPU memory map of debug channel to the UART. This should + be relatively simple as all you need to do is to let the ZPU + query the FIFO in/out for busy flag and allow the ZPU to read/write + data to the UART via the memory map. + +

          +TODO explicit example with UART from opencores in the above ref designs. + + + +

          SPI flash controller (read-only)

          +This is a simple read-only SPI flash controller, with the following characteristics: + +
          +
        11. Fast-READ only implementation. +
        12. 32-bit only access +
        13. Fast sequential read access - Uses low-clock approach
          14. +
          + +

          Version

          +The current version is 1.2. This is also the first public version available. + +

          Timing overview

          + +

          Simple timing overview, with one nonsequential access to address 0x0, followed by a sequential access to address 0x4. +This simulation was done with Xilinx tools, after post-routing, and using a ZPU to access the SPI

          +
          + + +

          Image 1: Timing overview

          +
          + +On Image 2, you can see the clock almost perfectly centered on data, when we write to the SPI flash. + +
          + +

          Image 2: Issuing commands to the SPI

          +
          + +As you can see from Image 3, I assume the worst-case read delay from SPI (which is 15ns, as you can see from the marker). + +
          + +

          Image 3: Reading from the SPI

          +
          + +

          Usage

          + +Simple description of SPI controller interface: + + + + + + + + + + + + + + + + + + +
          SymbolDirectionBit widthPurpose
          adrInput24Address where to read from SPI
          dat_oOutput32Data read from SPI
          clkInput1Input clock. Used for both interface and SPI
          ceInput1Chip Enable
          rstInput1Asynchronous reset
          ackOutput1Data valid ACK
          SPI_CLKOutput1SPI output clock
          SPI_MOSIOutput1SPI output data from controller to chip
          SPI_MISOInput1SPI input data from chip to controller
          SPI_SELNOutput1SPI nSEL (deselect, active low) signal
          + +

          License

          +The Verilog implementation is released under BSD license. See the file itself for more licensing details. + +

          Dowload

          +Download the Verilog code here: spi_controller.v + +

          Troubleshooting

          +The current implementation is timed and optimized for myself. Your parameters might not be the same +as those I defaulted, so read the code carefully. If you have any issue let me know. + + + + +
          + + +

          Working with the tools and core

          +TODO discussion of tools needed and choose some to be supported by project. Need to deal with cygwin vs linux, VHDL vs verilog, open vs closed.... plus language support in simulators is sometimes lacking. +

          +Xilinx ISE webpack is available for windows and linux +
          +Altera Quartus web edition is windows only. +
          +Lattice ispLEVER starter edition is windows only. +

          +None appear to come with a standalone simulator anymore. Not sure if any built in simulators are worth looking at... never have been in the past. + +

          +Popular Simulation tools for this kind of project: Modelsim, GHDL, veriwell, cver, icarus, gtkwave... others? +

          + + +

          Setup - Linux toolchain

          +You will need Java installed to run the simulator and some other stuff. +

          +TODO setup.sh script needs to detect linux/cygwin, and should have install path option. +

          +$ cd zpu/zpu/sw     # path as appropriate
+$ sh setup.sh       # untars the tool chain to ... TODO
+$ . env.sh          # puts the tools in you path
+
          + +           +

          Setup - Cygwin toolchain

          +Install           Cygwin +You will need Java installed to run the simulator and some other stuff. +
          +$ cd zpu/zpu/sw     # path as appropriate
+$ sh setup.sh       # unzips the tool chain to /tmp/zpu/install/bin
+$ . env.sh          # puts the tools in you path
+
          + + +

          GCC to RAM

          +TODO some of this is generic, some is zpu4 specific. Should move to refdesign section when ref designs exist. +

          +The instructions are stored big endian. That is the first instruction is stored in the most significant byte, and the forth is in the least significant byte. +

          +

          Generating VHDL BRAM initialization

          +
          +$ zpu-elf-objcopy -O binary hello.elf hello.bin
+$ java -classpath ../simulator/zpusim.jar com.zylin.zpu.simulator.tools.MakeRam hello.bin >hello.bram
+
          +

          Build another test application for example simulation

          +Here is how to build a rom image for an application using the +zpu/example simulation files. +
          +$ cd zpu/roadshow/roadshow/dhrystone
+$ sh build.sh
+$ cd zpu/hdl/example
+$ gcc zpuromgen.c
+$ ./a
+Usage: ./a binary_file
+$ ./a ../../roadshow/roadshow/dhrystone/dhrystone.bin >app.txt
+
          +Copy and paste app.txt into helloworld.vhd. + +

          +TODO need to merge following with above. +

          + +The ZPU comes with a standard GCC toolchain and an instruction set simulator. This allows compiling, running & debugging simple test programs. The Simulator has +some very basic peripherals defined: counter, timer interrupt and a debug output port. + +

          Hello world example

          +The ZPU toolchain comes with newlib & libstdc++ support which means that many C/C++ programs can be compiled without modification. +

          +

          +$ cd zpu/sw/helloworld
+$ zpu-elf-gcc -Os -zeta hello.c -o hello.elf -Wl,--relax -Wl,--gc-sections
+or ? TODO which one
+$ zpu-elf-gcc -phi hello.c -o hello.elf 
+$ zpu-elf-size hello.elf
+
          + + +           +

          HDL simulation (ZPU4)

          +TODO some of this is generic, some is zpu4 specific. Should move to refdesign section when ref design exists. +

          +For new users you will also find scripts in the zealot area that may be useful. +

          +You'll find a working simulation script in hdl/example/simzpu_small.do and hdl/example_medium/simzpu_medium.do, which +show simulation of the small(zpu_core_small.vhd) and medium sized ZPU(zpu_core.vhd). hdl/example/simzpu_interrupt.do +shows use of interrupts. +

          +When implementing the ZPU, copy the following files and modify them to your needs: +

            +
          1. hdl/example/zpu_config.vhd - set up RAM size here +
          2. hdl/example/helloworld.vhd - dual port BRAM implementation. +
          +Obviously you must also connect the ZPU to the rest of your IO subsystem. IO is memory mapped(read/write) in the ZPU. + +

          Running example simulation

          +The hdl/example directory has a simulation written for Xilinx WebPack ModelSim. From the ModelSim command prompt: +
            +
          1. cd c:/<installfolder>/hdl/example +
          2. do zpusim_small.do +
          +

          +After running the hello world simulation (see zpusim.do), two files are written to the hdl/example directory: +

            +
          1. log.txt - contains the "Hello world!" text written to the debug channel/simplified UART. +
          2. trace.txt - a trace file for the CPU. The instruction set simulator has the capability of taking +this file as input in order to verify that the HDL implementation matches the instruction set simulator. +When a mismatch is found, the GDB debugger will break. Very handy for debugging custom ZPU implementations. +
          + + +           +

          GDB simulation

          +
            +
          1. cd zpu/sw/helloworld +
          2. Launch the simulator from a seperate bash shell:

            +java -classpath ../simulator/zpusim.jar -Xmx512m com.zylin.zpu.simulator.Phi 4444 +

            + +

          3. Launch GDB:

            +../install/bin/zpu-elf-gdb hello.elf +

          4. Connect to target, load and run application:

            +

            +(gdb) target remote localhost:4444
            
+(gdb) load
            
+(gdb) continue
            
+
            +

            + + +

          + + +           +

          Simulator

          +

          The ZPU simulator is integrated into the Zylin Embedded CDT plugin +to ease debugging of ZPU applications:

          +

          http://www.zylin.com/embeddedcdt.html

          +

          The ZPU simulator has many features besides debugging an +application:

          +
            +

          • taking output from simulation(e.g. + ModelSim) and matching that against the Java simulator, thus making + it much easier to debug HDL implementations and also getting real + world timing information +

            +

          • can generate gprof output +

            +

          • generate various statistics +

            +
          +

          The plugin is still pretty rough around the edges, and needs to +get GUI support for enabling the ModelSim trace input feature.

          +


          Compiling +ZPU application

          +


          Setting +up the simulator

          +


          Choosing +ZPU executable

          +


          Debug +session

          +


          +

          + + +
          + + +

          Misc

          +TODO Stuff that could probably find a better home. + +           +

          JTAG/hardware debugger for GDB

          +The Zylin           ZY1000 JTAG debugger supports +the ZPU. Contact Zylin for pricing and details. +

          +There are two debug modes in which the ZY1000 can operate: +

            +
          • Classic. Here the ZY1000 controls the CPU and examines the state. The ZY1000 has a built in +GDB server that GDB talks to. +
          • Small footprint. If there isn't enough space on the device for the ZPU *and* the JTAG +controller, then the ZY1000 can run the ZPU externally. The JTAG communication channel is +then used to peek/poke peripherals and inside the FPGA instead of the ZPU there is then +a JTAG controller that peeks and pokes the peripherals of the ZPU. There are advantages +and disadvantages of this approach: it may be unfamiliar to embedded developers and +the timing is different from the "real" ZPU(interrupts are delayed, execution speed +differse, etc.) On the other hand there are other things +which are simpler: much more RAM can be available for the ZPU during development, +better debug consoles(faster), additional peripheral(timers, etc.) is available. This +approach is somewhat unique to the ZPU as the ZPU is simple enough that it can be +implemented efficiently in this manner. +
          + + + +

          Speeding up the ZPU

          +There are two aspects of speeding up the ZPU: making it perform better +for a particular application and toying around with the ZPU architecture. +

          Performance tips

          +
            +
          1. Profile. Create a small sample and run in a simulator that is as close +to the real deployment as possible. zpu4/core/histogram.perl is a script +that will tell you which instructions take the most time. +
          2. Using the profile output, decide on which emulated instructions that +it makes sense to implement in HDL for your particular application. Modifying +zpu_core_small.vhd is not particularly hard. Most instructions can be +transliterated into zpu_core_small.vhd from zpu_core.vhd without too much +problem. +
          3. The memory subsystem may well turn out to be where you should concentrate +your efforts. +
          +

          Toying around with the architecture

          +Again: profile 90% of the time and spend the remaining 10% tinkering +with the architecture. +
            +
          • There is a DMIPS program you can use to measure the performance of +the ZPU in lieu of profiling a real application. The latter is obviously +a superior solution. +
          • Again: use histogram.perl to figure out which instructions you should add +in HDL. +
          • Tinker a bit with Fmax to find the maximum speed rating for your design. +
          • zpu_core_small.vhd should be ca. 1 DMIPS and zpu_core.vhd should yield +about 5-10 DMIPS before adding instructions runs out of steam. +
          +If you need to get ca. 20-50 DMIPS out of the ZPU you will have to +write a heavily pipelined architecture with caches(if you are running +against DRAM). This is *tricky*, but some proof of concept work was +done to show 20 DMIPS w/the ZPU(the actual result was discarded since +it was not complete and contained fatal flaws). +

          +Achieving above 50-100 DMIPS with the current ZPU architecture is probably +a non-starter and a more conventional RISC design makes more sense here. +

          +The unique advantages of the ZPU is size in terms of HDL & code size. + + + + +

          Optimizing for code size

          +The ZPU toolchain produces highly compact code. +
            +
          1. Since the ZPU GCC toolchain supports standard ANSI C, it is easy to stumble across +functionality that takes up a lot of space. E.g. the standard printf() function is a beast. Some compilers drop e.g. floating point support +from the printf() function and thus boast a "smaller" printf() when in fact they have a non-standard printf(). newlib has a standard printf() function +and an alternative iprintf() function that works only on integers. +
          2. The ZPU ships with default startup code that works across various configurations of the ZPU, so be warned that there is some overhead that will +not occur in the final application(anywhere between 1-4kBytes). +
          3. Compilation and linker options matter. The ZPU benefits greatly from the "-Wl,--relax -Wl,--gc-sections" options which is not used by +all architectures(e.g. GCC ARM does not implement/need -Wl,--relax). +
          +

          Small code example

          + +zpu-elf-gcc -Os -abel smallstd.c -o smallstd.elf -Wl,--relax -Wl,--gc-sections
          +zpu-elf-size small.elf
          +
          +$ zpu-elf-size small.elf
          + text data bss dec hex filename
          + 2845 952 36 3833 ef9 small.elf
          +
          +           + +

          Even smaller code example

          +If the ZPU implements the optional instructions, the RAM overhead can be reduced significantly. +

          + +zpu-elf-gcc -Os -abel crt0_phi.S small.c -o small.elf -Wl,--relax -Wl,--gc-sections -nostdlib
          +zpu-elf-size small.elf
          +
          +$ zpu-elf-size small.elf
          + text data bss dec hex filename
          + 56 8 0 64 40 small.elf
          +
          +           + +           +

          Installing eCos build tools

          + +tar -xjvf ecossnapshot.tar.bz2
          +tar -xjvf repository.tar.bz2
          +tar -xjvf ecostools.tar.bz2
          +# run this every time you open the shell
          +export PATH=$PATH:`pwd`/ecos-install
          +export ECOS_REPOSITORY=`pwd`/ecos/packages:`pwd`/repository
          +           +

          Compiling eCos tests

          + +ecosconfig new zeta default
          +ecosconfig tree
          +make
          +cd kernel/current
          +make tests
          +           + +

          Code size ZPU

          +
          +$ zpu-elf-size *
+   text    data     bss     dec     hex filename
+  15761    1504   12060   29325    728d bin_sem0
+  16907    1512   14436   32855    8057 bin_sem1
+  17105    1524   30032   48661    be15 bin_sem2
+  17186    1512   14436   33134    816e bin_sem3
+  18986    1500   12036   32522    7f0a clock0
+  15812    1504   13236   30552    7758 clock1
+  25095    1972   13224   40291    9d63 clockcnv
+  16437    1500   13224   31161    79b9 clocktruth
+  15762    1504   12060   29326    728e cnt_sem0
+  17124    1512   14436   33072    8130 cnt_sem1
+  35947    1564   22512   60023    ea77 dhrystone
+  16428    1500   13228   31156    79b4 except1
+  15751    1504   12052   29307    727b flag0
+  19145    1512   15624   36281    8db9 flag1
+  20053    1516  102908  124477   1e63d fptest
+  15998    1496   12092   29586    7392 intr0
+  16080    1496   12200   29776    7450 kalarm0
+  15327    1496   12036   28859    70bb kcache1
+  15549    1496   13224   30269    763d kcache2
+  18291    1500   12260   32051    7d33 kclock0
+  16231    1500   13232   30963    78f3 kclock1
+  16572    1496   13228   31296    7a40 kexcept1
+  15618    1496   12060   29174    71f6 kflag0
+  19287    1500   15624   36411    8e3b kflag1
+  16887    1516   15628   34031    84ef kill
+  16186    1496   12128   29810    7472 kintr0
+  19724    1504   14516   35744    8ba0 klock
+  18283    1500   14592   34375    8647 kmbox1
+  15539    1496   12064   29099    71ab kmutex0
+  16524    1504   15664   33692    839c kmutex1
+  18272    1712   20348   40332    9d8c kmutex3
+  18682    1608   20352   40642    9ec2 kmutex4
+  15619    1496   14412   31527    7b27 ksched1
+  15567    1496   12060   29123    71c3 ksem0
+  17063    1500   14436   32999    80e7 ksem1
+  15504    1496   13228   30228    7614 kthread0
+  16167    1496   14412   32075    7d4b kthread1
+  18281    1512   14580   34373    8645 mbox1
+  20611    1508   14940   37059    90c3 mqueue1
+  15672    1504   12064   29240    7238 mutex0
+  16678    1516   15664   33858    8442 mutex1
+  17694    1508   16868   36070    8ce6 mutex2
+  18203    1720   20344   40267    9d4b mutex3
+  16352    1508   14428   32288    7e20 release
+  15890    1500   14412   31802    7c3a sched1
+  44196    1612  286332  332140   5116c stress_threads
+  17891    1524   16864   36279    8db7 sync2
+  16943    1512   15644   34099    8533 sync3
+  15467    1496   13064   30027    754b thread0
+  16134    1496   14420   32050    7d32 thread1
+  17560    1512   15636   34708    8794 thread2
+  16279    1500   24028   41807    a34f thread_gdb
+  17051    1504   20376   38931    9813 timeslice
+  17146    1504   21564   40214    9d16 timeslice2
+  37313    1512  422380  461205   70995 tm_basic
+
          +

          Code size ARM (non-thumb)

          +Thumb does not compile out of the box w/AT91 EB40a for which this test was made.

          +

          +$ arm-elf-size *
+   text    data     bss     dec     hex filename
+  25204     692   16976   42872    a778 bin_sem0
+  26644     700   22096   49440    c120 bin_sem1
+  26996     712   55584   83292   1455c bin_sem2
+  27008     700   22100   49808    c290 bin_sem3
+  28992     688   16944   46624    b620 clock0
+  25456     692   19532   45680    b270 clock1
+  34572    1160   19520   55252    d7d4 clockcnv
+  26224     688   19508   46420    b554 clocktruth
+  25204     692   16976   42872    a778 cnt_sem0
+  26888     700   22108   49696    c220 cnt_sem1
+  44180     752   27416   72348   11a9c dhrystone
+  26088     688   19520   46296    b4d8 except1
+  25236     692   16968   42896    a790 flag0
+  29532     700   24668   54900    d674 flag1
+  29508     704  109652  139864   22258 fptest
+  25932     684   17016   43632    aa70 intr0
+  25824     684   17112   43620    aa64 kalarm0
+  24728     684   16956   42368    a580 kcache1
+  25168     684   19512   45364    b134 kcache2
+  28112     688   17168   45968    b390 kclock0
+  25976     688   19524   46188    b46c kclock1
+  26372     684   19512   46568    b5e8 kexcept1
+  25140     684   16968   42792    a728 kflag0
+  29824     688   24660   55172    d784 kflag1
+  26896     704   24656   52256    cc20 kill
+  26088     684   17028   43800    ab18 kintr0
+  30812     692   22176   53680    d1b0 klock
+  28504     688   22260   51452    c8fc kmbox1
+  24984     684   16984   42652    a69c kmutex0
+  26504     692   24704   51900    cabc kmutex1
+  28792     900   34892   64584    fc48 kmutex3
+  29264     796   34896   64956    fdbc kmutex4
+  25240     684   22084   48008    bb88 ksched1
+  25044     684   16968   42696    a6c8 ksem0
+  26988     688   22100   49776    c270 ksem1
+  25028     684   19512   45224    b0a8 kthread0
+  25996     684   22080   48760    be78 kthread1
+  28552     700   22252   51504    c930 mbox1
+  31324     696   22612   54632    d568 mqueue1
+  25108     692   16980   42780    a71c mutex0
+  26464     704   24700   51868    ca9c mutex1
+  27624     696   27280   55600    d930 mutex2
+  28596     908   34884   64388    fb84 mutex3
+  26156     696   22100   48952    bf38 release
+  25460     688   22084   48232    bc68 sched1
+  56356     828   45892  103076   192a4 stress_threads
+  27900     712   27288   55900    da5c sync2
+  26760     700   24692   52152    cbb8 sync3
+  24924     684   19356   44964    afa4 thread0
+  25868     684   22084   48636    bdfc thread1
+  27452     700   24680   52832    ce60 thread2
+  26136     688   42704   69528   10f98 thread_gdb
+  27212     692   34916   62820    f564 timeslice
+  52728     700  123332  176760   2b278 tm_basic
+
          + +           +

          Phi memory map

          +TODO This probably belongs in the refdesign section. For now leaving it here because zealot refers to it. Not sure what else uses it. +

          +The ZPU architecture does not define a memory map as such, but the GCC + libgloss + ecos hal library uses the +memory map below. "Phi" is just a three letter word for the particular memory layout below that came about +while developing the ZPU. +

          + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
          +

          Address

          +           		+

          Type

          +           		+

          Name

          +           		+

          Description

          +
          +

          0x080A0000

          +           		+

          Write

          +           		+

          ZPU + enable

          +           		+

          Bit + [31:1] Not used

          +

          Bit + [0] Enable ZPU operations

          +

          0 ZPU + is held in Idle mode

          +

          1 ZPU + running

          +
          +

          0x080A000C

          +           		+

          Read/

          +

          Write

          +           		+

          ZPU + Debug channel / UART to ARM7 TX

          +

          NOTE! + ZPU side

          +           		+

          Bit + [31:9] Not used

          +

          Bit + [8] TX buffer ready (valid on ready)

          +

          0 TX + buffer not ready (full)

          +

          1 TX + buffer ready

          +

          Bit + [7:0] TX byte (valid on write)

          +
          +

          0x080A0010

          +           		+

          Read

          +           		+

          ZPU + Debug channel / UART to ARM7 RX

          +

          NOTE! + ZPU side

          +           		+

          Bit + [31:9] Not used

          +

          Bit + [8] RX buffer data valid

          +

          0 RX + buffer not valid

          +

          1 RX + buffer valid

          +

          Bit + [7:0] RX byte (when valid)

          +
          +

          0x080A0014

          +           		+

          Read/

          +

          Write

          +           		+

          Counter(1)

          +           		+

          Bit + [0] Reset counter (valid for write)

          +

          0 N/A

          +

          1 Reset + counter

          +

          Bit + [1] Sample counter (valid for write)

          +

          0 N/A

          +

          1 Sample + counter

          +

          Bit + [31:0] Counter bit 31:0

          +
          +

          0x080A0018

          +           		+

          Read

          +           		+

          Counter(2)

          +           		+

          Bit + [31:0] Counter bit 63:32

          +
          +

          0x080A0020

          +           		+

          Read + / Write

          +           		+

          Global_Interrupt_mask

          +           		+

          Bit + [31:1] Not used

          +

          Bit + [0] Global intr. Mask

          +

          0 Interrupts + enabled

          +

          1 Interrupts + disabled

          +
          +

          0x080A0024

          +           		+

          Write

          +           		+

          UART_INTERRUPT_ENABLE

          +           		+

          Bit + [31:1] Not used

          +

          Bit + [0] Debug channel / UART RX interrupt enable

          +

          0 Interrupt + disable

          +

          1 Interrupt + enable

          +
          +

          0x080A0028

          +           		+

          Read

          +

          Write

          +           		+

          UART_interrupt

          +           		+

          Bit + [31:1] Not used

          +

          Bit + [0] Debug channel / UART RX interrupt pending (Read)

          +

          0 No + interrupt pending

          +

          1 Interrupt + pending

          +

          Bit + [0] Clear UART interrupt (Write)

          +

          0 N/A

          +

          1 Interrupt + cleared

          +
          +

          0x080A002C

          +           		+

          Write

          +           		+

          Timer_Interrupt_enable

          +           		+

          Bit + [31:1] Not used

          +

          Bit + [0] Timer interrupt enable

          +

          0 Interrupt + disable

          +

          1 Interrupt + enable

          +
          +

          0x080A0030

          +           		+

          Read + /

          +

          Write

          +           		+

          Timer_interrupt

          +           		+

          Bit + [31:2] Not used

          +

          Bit + [0] Timer interrupt pending (Read)

          +

          0 No + interrupt pending

          +

          1 Interrupt + pending

          +

          Bit + [1] Reset Timer counter (Write)

          +

          0 N/A

          +

          1 Timer + counter reset

          +

          Bit + [0] Clear Timer interrupt (Write)

          +

          0 N/A

          +

          1 Interrupt + cleared

          +
          +

          0x080A0034

          +           		+

          Write

          +           		+

          Timer_Period

          +           		+

          Bit + [31:0] Interrupt period (write)

          +

          Number + of clock cycles

          +

          between + timer interrupts

          +

          NOTE! + The timer will start at Timer_Periode value and count down + to zero, and generate an interrupt

          +
          +

          .0x080A0038

          +           		+

          Read

          +           		+

          Timer_Counter

          +           		+

          Bit + [31:0] Timer counter (read)

          +


          +

          +
          +


          +

          +           		+


          +

          +           		+


          +

          +           		+


          +

          +
          +


          +

          +           		+


          +

          +           		+


          +

          +           		+


          +

          +
          +


          +

          +           		+


          +

          +           		+


          +

          +           		+


          +

          +
          +


          +

          +           		+


          +

          +           		+


          +

          +           		+


          +

          +
          + +

          + +           +

          TODO

          + +           +

          TODO list

          +           + + +

          Repository Re-org

          +I am proposing the following structure for the repository. It follows somewhat the way I've organized this document with seperation of core, common, and three SOC ref designs. New users go straight to the SOC that best matches their needs. +
          +zpu/bin         # scripts and toolchain?  Want toolchain installed with project.  Tidier when working in multi user / multi project environment
+zpu/doc         # 
+zpu/core/rtl    # RTL for the various core implementations.
+zpu/core/sw     # crt0.s ?
+zpu/common/rtl  # Re-use RTL such as RAM and UART
+zpu/common/sim  # Re-use RTL and tools for regresion testing
+zpu/common/sw   # ?
+zpu/soc/minimal # Three levels of ref designs described above
+       /basic 
+       /board
+zpu/soc/*/rtl   # top level, arbiter, etc
+zpu/soc/*/sw    # helloworld, dmips, etc. makefile/ROMS
+zpu/soc/*/sim   # regression test area. makefile/scripts
+zpu/soc/*/fpga  # syn and par area. makefile/scripts
+zpu/tools       # zip/tarball of tool chains, simulator
+
          +Not sure where ecos fits. + +           +

          Next generation ZPU

          +Based on feedback here is a list of a tenuous "consensus" for the next generation +of the ZPU with some tentative ideas on implementation. +

          Goals

          +
            +
          1. Reduce minimum code size footprint, i.e. BRAM code overhead. Non-trivial +usable applications in 4kBytes of BRAM (single BRAM block). +
          2. Reduce minimum FPGA logic footprint by 20% or more. Goal <300 LUT for +32 bit ZPU +
          3. Weed out unnecessary ZPU variations +
          4. Will someone be willing to contribute a heavily pipelined ZPU? +For this to make sense, the performance must hit 20 DMIPS w/DRAM & cache. +This ZPU could run a TCP/IP stack with relevant performance to compete +with stripped down ARM7 type systems. +
          +

          Best current ideas on how to reach these goals

          +
            +
          1. Introduce 16 entry 32 bit LIFO for instructions that change sp today. LOADSP/STORESP/ADDSP +refer to the normal stack but add/get values from the LIFO in addition.

            + +loadsp n ; load value from memory at address "sp + n" and put it into the LIFO.
            +im m ; put value into LIFO register
            +add ; get two values from LIFO register, put back result.
            +             +

            +NB! none of the instructions above change sp!!! +

            +If the LIFO is full, putting a value into the LIFO has no defined behaviour. Getting a value +from an empty LIFO has no defined behaviour. +

            +GCC will use 8 slots, instruction emulation and interrupts owns the remaining 8 slots. + +

          2. Add single entry for unknown instructions. PC and unsupported instruction is +pushed onto stack before jumping to unknown instruction vector. This makes it possible +to write denser microcode for missing instructions. For emulated opcodes that are +not in use, the microcode can more easily be disabled. Determining +that e.g. MULT is not used, can be a bit tricky, but disabling it is easy. +

            +The unsupported vector entry address is 0x10. +

          3. GCC needs 4 registers. These are today mapped to memory. What addresses to use? +Today memory address 0x00-0x0f inclusive are used for this purpose. Introduce emulated +instruction to load/store these registers? That would allow using either hardware or +memory registers. +
          4. Single entry for *all* unknown instructions does not limit emulation to the +EMULATE instructions today, but instructions such as OR, LOADSP, STORESP, ADDSP, +etc. can also be emulated. This opens up for further reduction in logic usage. +
          5. The single entry for all unknown instructions will make it easier to +write a compact custom crt0.s to fit an instruction subset. +
          6. The interrupt is basically an unknown instruction that is injected into +the execution stream. +
          7. Add floating point add and mult. FADD & FMULT. Option to generate the instructions +from the compiler. +
          8. Strip away unused instructions from GCC and add options to GCC for not +emitting more advanced instructions. This will e.g. convert MULT/DIV into +function calls to libgcc and thus make it easier to determine that +microcode is not needed. + + +

            Register stack

            +In order to reduce the size and complexity of the small ZPU, a register stack +has been put forward. It remains an open question as to whether this can +indeed reduce size and improve performance of the ZPU. +

            +Terminology: "stack" is the normal stack in memory pointed to +by the sp register. "register stack" is a different stack that is +not connected to memory directly or associated with the "stack". +

            +The idea is to push and pop the register stack such that bandwidth +is increased and complexity of memory access logic is reduced. +

            +Another clever bit is to mask interrupts while this stack is +not empty such that this stack never has to be +saved. It's depth would be fixed to something natural +for an FPGA, say 16 deep(doesn't that translate to a single +LUT for a bit?). + +

            Example of internal stack

            +im 1 ; push onto register stack
            +loadsp N ; load from memory pointed to by sp+N, push onto register stack
            +add ; pop values from register stack and add, push onto register stack
            + +

            Quick summary of instruction operation with register stack

            +This is not a "formal" definition of the instruction set, but should +give a pretty good idea of what the modified instruction looks like. +

            +Read up on the current definition of instructions and consider the +list below a guide to what changes have been made to fit a register +stack. The list is not complete, but covers the important categories +of instructions. If it is clear how the ADD instruction changed, +then it should be obvious how the AND instruction must be similarly +modified. +

            +Note also that there are lots of tiny problems that have to be ironed +out before the instruction set and emulation can work. Below is just +a first stab, which hopefully is good enough to evaluate the approach. + + + + + + + + + + + + + + +
            IM push onto/modify top of register stack
            STORESP pop register stack store to memory SP+N
            LOADSP load memory SP+N push onto register stack
            EMULATE push PC+1 onto register stack and jump to EMULATE vector
            PUSHPC push pc onto register stack
            POPPC pop pc from register stack
            LOAD pop address from register stack, load from memory address, push onto register stack
            STORE pop register stack 2x store value to memory
            PUSHSP push sp onto register stack
            POPSP pop sp from register stack
            POPPC pop pc from register stack
            ADD pop 2x register stack, add, push to register stack
            NOT pop register stack, bit inverse value, push onto register stack
            +Emulate instructions and calling convention may have to change substantially. + + + + + -- cgit v1.1 From 047351652678c02fc3aa3a6202b0d0f1d996ed48 Mon Sep 17 00:00:00 2001 From: Oyvind Harboe Date: Mon, 12 Jan 2009 21:10:20 +0100 Subject: Test patches --- zpu/docs/zpu_arch.html | 186 +++++++++++++++++-------------------------------- 1 file changed, 63 insertions(+), 123 deletions(-) diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index a0187e6..5a55378 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -66,7 +66,6 @@ Several of the links will only work if you have checked out the zpu/zpu tree fro

          9. TODO list
          10. Repository Re-org
          11. Next generation ZPU -
          12. Register stack ZPU @@ -74,8 +73,34 @@ Several of the links will only work if you have checked out the zpu/zpu tree fro

            Introduction

            -

            TODO a new welcome message indicating goals/direction of project.

            The worlds smallest 32 bit CPU with GCC toolchain. +

            The ZPU is a small CPU in two ways: it takes up very little resources and +the architecture itself is small. The latter can be important when learning +about CPU architectures and implementing variations of the ZPU where +aspects of CPU design is examined. In academia students can learn VHDL, +CPU architecture in general and complete exercises in the course of a year.

            +

            +The current ZPU instruction set and architecture has not changed for +the last couple of years and can be considered quite stable. There is +a lot of discussion about various modifications to the ZPU architecture +in the zylin-zpu mailing list, but currently no actual modifications are +planned as the improvements that have been identified are relatively +slight(<30% performance/size improvement). +

            +

            +There are a handful of implementations of the ZPU. Most of these usually +have some strong points and there is some movement in the direction of +consolidating improvements into a few officially recommended ZPU +implementations. +

            +

            +For those that are interested in the Zylin ZPU, I recommend joining +up on the zylin-zpu mailing list and participating in the discussion +there. The zylin-zpu is a friendly place where people of different +skills, hardware, software, tools meet to exchange ideas about the ZPU +and microprocessor architecture in general. +

            +

            Sincerely,

            Øyvind Harboe
            Zylin AS

            @@ -121,38 +146,29 @@ information about where the ZPU can be the most useful:

            Download source code

            -

            -

            To get the ZPU HDL source and tools, check it out from CVS:

            -

            cvs -d :pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous co -zpu/zpu

            -There are more instructions -            here -and -here -. - -

            As of 01 JAN 2009, if you check out all of zpu it is about 200MB, and includes more than you need. It is recommended that you only checkout zpu/zpu. - +The ZPU HDL source code is available as a GIT repository from rep.xxx.cz. +You can download the latest sourcecode as a snapshot withing installing GIT. +

            +Previously the ZPU repository was hosted as a CVS repository at www.opencores.org, +but that ZPU CVS repository is there only for historical reference at this point. +Once www.opencores.org grows a GIT hosting service, the plan is to replicate +the GIT repository there. -

            Creating a patch

            -

            Please submit changes to the zylin-zpu mailing list as a patch. -

            -
              -
            1. Merge your changes with CVS HEAD. -
            2. Update the FreeBSD or GPL copyright with your name in the case -of non-trivial changes. If in doubt, add the copyright. -
            3. Add an entry to zpu/ChangeLog with date, your name, email, the -files you changed and a comment. -
            4. cd zpu
              cvs diff -upN . > mypatch.txt               -
            5. Email it to zylin-zpu mailing list. Attach it -as an uncompressed .txt file -
            - +

            GIT

            +For more advanced use of GIT, you will need to hit the books and read up +on the GIT documentation. +

            +That said, you can ask "silly" newbie questions about GIT on the zylin-zpu mailing +list and you should receive some friendly prodding in the right direction +w.r.t. finding reading material.

            Getting help - mailing list

            The place to get help is the zylin-zpu mailing list

            +The ZPU is an open source project and if you demonstrate that you have +made an effort to read the documentation and googled, then you will +normally get some help from this list if you ask clear questions.

            @@ -2274,110 +2290,34 @@ of the ZPU with some tentative ideas on implementation. usable applications in 4kBytes of BRAM (single BRAM block).
          13. Reduce minimum FPGA logic footprint by 20% or more. Goal <300 LUT for 32 bit ZPU -
          14. Weed out unnecessary ZPU variations +
          15. Weed out unnecessary ZPU variations and merge in useful +features to a few recommeneded ZPU implementations.
          16. Will someone be willing to contribute a heavily pipelined ZPU? -For this to make sense, the performance must hit 20 DMIPS w/DRAM & cache. +Performance goal of 10 DMIPS w/DRAM & cache. This ZPU could run a TCP/IP stack with relevant performance to compete with stripped down ARM7 type systems.
          -

          Best current ideas on how to reach these goals

          +

          GCC changes

          +The GCC changes planned are 100% backwards compatible with default +options. However, a raft of options will be added to disable +functionality so as to allow study and experimentation with the +ZPU architecture.
            -
          1. Introduce 16 entry 32 bit LIFO for instructions that change sp today. LOADSP/STORESP/ADDSP -refer to the normal stack but add/get values from the LIFO in addition.

            - -loadsp n ; load value from memory at address "sp + n" and put it into the LIFO.
            -im m ; put value into LIFO register
            -add ; get two values from LIFO register, put back result.
            -             -

            -NB! none of the instructions above change sp!!! -

            -If the LIFO is full, putting a value into the LIFO has no defined behaviour. Getting a value -from an empty LIFO has no defined behaviour. -

            -GCC will use 8 slots, instruction emulation and interrupts owns the remaining 8 slots. - -

          2. Add single entry for unknown instructions. PC and unsupported instruction is -pushed onto stack before jumping to unknown instruction vector. This makes it possible -to write denser microcode for missing instructions. For emulated opcodes that are -not in use, the microcode can more easily be disabled. Determining -that e.g. MULT is not used, can be a bit tricky, but disabling it is easy. -

            -The unsupported vector entry address is 0x10. -

          3. GCC needs 4 registers. These are today mapped to memory. What addresses to use? -Today memory address 0x00-0x0f inclusive are used for this purpose. Introduce emulated -instruction to load/store these registers? That would allow using either hardware or -memory registers. -
          4. Single entry for *all* unknown instructions does not limit emulation to the -EMULATE instructions today, but instructions such as OR, LOADSP, STORESP, ADDSP, -etc. can also be emulated. This opens up for further reduction in logic usage. -
          5. The single entry for all unknown instructions will make it easier to -write a compact custom crt0.s to fit an instruction subset. -
          6. The interrupt is basically an unknown instruction that is injected into -the execution stream. -
          7. Add floating point add and mult. FADD & FMULT. Option to generate the instructions -from the compiler. +
          8. Add options that allow defining single entry for all unknown instructions. Precisely +how unknown instructions are handled will be defined by the HDL implementation. +Currently the GCC backend places relatively strict limitations on how unknown/emulated +instructions are handled. This will allow HDL implementations to have +sparser instruction set support. Also this can allow sparse implementations +of emualted instructions. This is especially important to reduce minimal +BRAM requirements for small applications. +
          9. GCC needs 4 "hard" registers. These are today mapped to memory. GCC +will allow specifying what address to use or alternatively not to use +memory mapped hard registers at all.
          10. Strip away unused instructions from GCC and add options to GCC for not emitting more advanced instructions. This will e.g. convert MULT/DIV into function calls to libgcc and thus make it easier to determine that microcode is not needed. - - -

            Register stack

            -In order to reduce the size and complexity of the small ZPU, a register stack -has been put forward. It remains an open question as to whether this can -indeed reduce size and improve performance of the ZPU. -

            -Terminology: "stack" is the normal stack in memory pointed to -by the sp register. "register stack" is a different stack that is -not connected to memory directly or associated with the "stack". -

            -The idea is to push and pop the register stack such that bandwidth -is increased and complexity of memory access logic is reduced. -

            -Another clever bit is to mask interrupts while this stack is -not empty such that this stack never has to be -saved. It's depth would be fixed to something natural -for an FPGA, say 16 deep(doesn't that translate to a single -LUT for a bit?). - -

            Example of internal stack

            -im 1 ; push onto register stack
            -loadsp N ; load from memory pointed to by sp+N, push onto register stack
            -add ; pop values from register stack and add, push onto register stack
            - -

            Quick summary of instruction operation with register stack

            -This is not a "formal" definition of the instruction set, but should -give a pretty good idea of what the modified instruction looks like. -

            -Read up on the current definition of instructions and consider the -list below a guide to what changes have been made to fit a register -stack. The list is not complete, but covers the important categories -of instructions. If it is clear how the ADD instruction changed, -then it should be obvious how the AND instruction must be similarly -modified. -

            -Note also that there are lots of tiny problems that have to be ironed -out before the instruction set and emulation can work. Below is just -a first stab, which hopefully is good enough to evaluate the approach. - - - - - - - - - - - - - - -
            IM push onto/modify top of register stack
            STORESP pop register stack store to memory SP+N
            LOADSP load memory SP+N push onto register stack
            EMULATE push PC+1 onto register stack and jump to EMULATE vector
            PUSHPC push pc onto register stack
            POPPC pop pc from register stack
            LOAD pop address from register stack, load from memory address, push onto register stack
            STORE pop register stack 2x store value to memory
            PUSHSP push sp onto register stack
            POPSP pop sp from register stack
            POPPC pop pc from register stack
            ADD pop 2x register stack, add, push to register stack
            NOT pop register stack, bit inverse value, push onto register stack
            -Emulate instructions and calling convention may have to change substantially. - - +

          -- cgit v1.1 From 5c6feff72d5324c88e0e8d8980a7d7cfab7e1509 Mon Sep 17 00:00:00 2001 From: Oyvind Harboe Date: Tue, 27 Jan 2009 08:33:56 +0100 Subject: First cut of ZPU floating point support design --- zpu/docs/zpu_arch.html | 51 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index 5a55378..6266a03 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -66,6 +66,7 @@ Several of the links will only work if you have checked out the zpu/zpu tree fro
        14. TODO list
        15. Repository Re-org
        16. Next generation ZPU +
        17. Floating point support @@ -2319,5 +2320,55 @@ function calls to libgcc and thus make it easier to determine that microcode is not needed.
        + +

        Floating point support

        +The ZPU does not currently have floating point support. Feedback +from users indicates that single precision floating point support for +addition, multiplication and float-to-integer convesion would +be useful for small ZPU programs that sit in a tight control +loop. Essentially the ZPU is then measuring something, doing a +few calculations and then modifying the control signal. +

        +Such control loops can be written in fixed point math, but that +adds to the engineering effort and reduces clarity of the software +implementation and the performance will probably be worse than +for a hardware floating point version. +

        Pipelined floating point module

        +Design needs to be nailed down. +Goals: +
          +
        • 32 bit single precision floating point +
        • FADD => add two floats +
        • FMULT => multiply two floats +
        • FINT => convert float to int +
        +The problem is divided into two: + +
          +
        1. One top level VHDL module for each of the operations above. +
        2. Integration into ZPU's are a separate problem that will not be +addressed in this project. +
        3. add a memory mapped coprocessor interface to the above. This +yields an example of a coprocessor which can be used for any +custom calculations and allows interest to be gauged. +
        + +Throughput: + +
          +
        1. pipelined design where throughput is one operation per cycle +with a fixed number of cycles delay. +
        2. there is no flow control or enable signal. +
        + + + +GCC support is not hard, but modifying GCC should considered after +interest in this feature beyond a coprocessor has been gauged. + +

        VHDL module interface

        + +Patches anyone??? + -- cgit v1.1 From 24200bd858df8d55c8303a59b53e915ba85412b2 Mon Sep 17 00:00:00 2001 From: Oyvind Harboe Date: Tue, 27 Jan 2009 08:41:41 +0100 Subject: git servers documented --- zpu/docs/zpu_arch.html | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index 6266a03..574000d 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -147,13 +147,16 @@ information about where the ZPU can be the most useful:

        Download source code

        -The ZPU HDL source code is available as a GIT repository from rep.xxx.cz. -You can download the latest sourcecode as a snapshot withing installing GIT. +The ZPU HDL source code is available as a GIT repository from         http://repo.or.cz/w/zpu.git. +You can download the latest sourcecode as a snapshot without installing GIT.

        Previously the ZPU repository was hosted as a CVS repository at www.opencores.org, but that ZPU CVS repository is there only for historical reference at this point. Once www.opencores.org grows a GIT hosting service, the plan is to replicate the GIT repository there. + +

        +The GCC ZPU toolchain is available from "git://www.ecosforge.net:8100/zpu/toolchain.git". The ZPU GCC toolchain is BIG(over 100mBytes), otherwise it would have been hosted at repo.or.cz too.

        GIT

        For more advanced use of GIT, you will need to hit the books and read up -- cgit v1.1 From f4d6ae600be0975e11c64c238113f2fd43d35cbf Mon Sep 17 00:00:00 2001 From: "U-TEMPEST\\oyvind" Date: Mon, 15 Jun 2009 17:54:00 +0200 Subject: Remove reference to zeta, only phi is used now --- zpu/docs/zpu_arch.html | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index 574000d..8aaa132 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -1510,7 +1510,7 @@ The ZPU toolchain comes with newlib & libstdc++ support which means that many C/ 

         $ cd zpu/sw/helloworld
-$ zpu-elf-gcc -Os -zeta hello.c -o hello.elf -Wl,--relax -Wl,--gc-sections
+$ zpu-elf-gcc -Os -phi hello.c -o hello.elf -Wl,--relax -Wl,--gc-sections
 or ? TODO which one
 $ zpu-elf-gcc -phi hello.c -o hello.elf 
 $ zpu-elf-size hello.elf
@@ -1725,7 +1725,7 @@ export ECOS_REPOSITORY=`pwd`/ecos/packages:`pwd`/repository
        
 
 
        Compiling eCos tests
        
 
-ecosconfig new zeta default
        
+ecosconfig new phi default
        
 ecosconfig tree
        
 make
        
 cd kernel/current
        
-- 
cgit v1.1


From 879f385d7ae2bcef98f1970aba872235e940776b Mon Sep 17 00:00:00 2001
From: Antonio Anton 
Date: Mon, 14 Sep 2009 08:34:41 +0200
Subject: FreeRTOS port

---
 zpu/sw/freertos/port/port.c             | 271 ++++++++++++++++++++++++++++++++
 zpu/sw/freertos/port/portasm.s          | 142 +++++++++++++++++
 zpu/sw/freertos/port/portmacro.h        | 125 +++++++++++++++
 zpu/sw/freertos/readme.txt              |  40 +++++
 zpu/sw/freertos/sample/FreeRTOSConfig.h |  96 +++++++++++
 zpu/sw/freertos/sample/Makefile         |  50 ++++++
 zpu/sw/freertos/sample/test1.c          |  67 ++++++++
 7 files changed, 791 insertions(+)
 create mode 100644 zpu/sw/freertos/port/port.c
 create mode 100644 zpu/sw/freertos/port/portasm.s
 create mode 100644 zpu/sw/freertos/port/portmacro.h
 create mode 100644 zpu/sw/freertos/readme.txt
 create mode 100644 zpu/sw/freertos/sample/FreeRTOSConfig.h
 create mode 100644 zpu/sw/freertos/sample/Makefile
 create mode 100644 zpu/sw/freertos/sample/test1.c

diff --git a/zpu/sw/freertos/port/port.c b/zpu/sw/freertos/port/port.c
new file mode 100644
index 0000000..ff243ee
--- /dev/null
+++ b/zpu/sw/freertos/port/port.c
@@ -0,0 +1,271 @@
+/*
+	FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify it
+	under the terms of the GNU General Public License (version 2) as published
+	by the Free Software Foundation and modified by the FreeRTOS exception.
+	**NOTE** The exception to the GPL is included to allow you to distribute a
+	combined work that includes FreeRTOS.org without being obliged to provide
+	the source code for any proprietary components.  Alternative commercial
+	license and support terms are also available upon request.  See the 
+	licensing section of http://www.FreeRTOS.org for full details.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,	but WITHOUT
+	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+	FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+	more details.
+
+	You should have received a copy of the GNU General Public License along
+	with FreeRTOS.org; if not, write to the Free Software Foundation, Inc., 59
+	Temple Place, Suite 330, Boston, MA  02111-1307  USA.
+
+
+	***************************************************************************
+	*                                                                         *
+	* Get the FreeRTOS eBook!  See http://www.FreeRTOS.org/Documentation      *
+	*                                                                         *
+	* This is a concise, step by step, 'hands on' guide that describes both   *
+	* general multitasking concepts and FreeRTOS specifics. It presents and   *
+	* explains numerous examples that are written using the FreeRTOS API.     *
+	* Full source code for all the examples is provided in an accompanying    *
+	* .zip file.                                                              *
+	*                                                                         *
+	***************************************************************************
+
+	1 tab == 4 spaces!
+
+	Please ensure to read the configuration and relevant port sections of the
+	online documentation.
+
+	http://www.FreeRTOS.org - Documentation, latest information, license and
+	contact details.
+
+	http://www.SafeRTOS.com - A version that is certified for use in safety
+	critical systems.
+
+	http://www.OpenRTOS.com - Commercial support, development, porting,
+	licensing and training services.
+*/
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the MicroBlaze port.
+ *----------------------------------------------------------*/
+
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Standard includes. */
+#include 
+
+/* hardware/software platform specific defines */
+#define DISABLE_C_PROTOTYPES
+#include 
+
+/* Tasks are started with interrupts enabled. */
+#define portINITIAL_INTERRUPT_ENABLE	( ( portSTACK_TYPE ) INTERRUPT_GLOBAL_ENABLE )
+
+/* Tasks are started with a critical section nesting of 0 - however prior
+to the scheduler being commenced we don't want the critical nesting level
+to reach zero, so it is initialised to a high value. */
+#define portINITIAL_NESTING_VALUE	( 0xff )
+
+/* The stack used by the ISR is filled with a known value to assist in
+debugging. */
+#define portISR_STACK_FILL_VALUE	0x55555555
+
+/* Counts the nesting depth of calls to portENTER_CRITICAL().  Each task 
+maintains it's own count, so this variable is saved as part of the task
+context. */
+volatile unsigned portBASE_TYPE uxCriticalNesting = portINITIAL_NESTING_VALUE;
+
+/* To limit the amount of stack required by each task, this port uses a
+separate stack for interrupts. */
+unsigned portLONG *pulISRStack;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Sets up the periodic ISR used for the RTOS tick.  This uses timer 0, but
+ * could have alternatively used the watchdog timer or timer 1.
+ */
+static void prvSetupTimerInterrupt( void );
+/*-----------------------------------------------------------*/
+
+/* 
+ * Initialise the stack of a task to look exactly as if a call to 
+ * portSAVE_CONTEXT had been made.
+ * 
+ * See the header file portable.h.
+ */
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
+{
+	/* Function call parameters. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) pvParameters;
+
+	/* Place initial PC (task entry point) */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) pxCode;	/* PC */
+
+	/* Place initial value for INTERRUPT global ENABLE */
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_INTERRUPT_ENABLE;	/* interrupt state (global enable) */
+	
+	/* Stack an initial value for the critical section nesting.  This
+	is initialised to zero as tasks are started with interrupts enabled. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x00;
+
+	/* Place an initial value for all temporary registers mapped to mem[0..16] by gcc */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x11111111;	/* mem[0] */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x22222222;	/* mem[4] */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x33333333;	/* mem[8] */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x44444444;	/* mem[12] */
+
+	/* Return a pointer to the top of the stack we have generated so this can
+	be stored in the task control block for the task. */
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+portBASE_TYPE xPortStartScheduler( void )
+{
+extern void ( __FreeRTOS_interrupt_handler )( void );
+extern void ( vStartFirstTask )( void );
+
+	/* Setup the FreeRTOS interrupt handler */
+	*(volatile unsigned *) INTERRUPT_VECTOR = (unsigned) __FreeRTOS_interrupt_handler;
+
+	/* Setup the hardware to generate the tick.  Interrupts are disabled when
+	this function is called. */
+	prvSetupTimerInterrupt();
+
+	/* Allocate the stack to be used by the interrupt handler. */
+	pulISRStack = ( unsigned portLONG * ) pvPortMalloc( configMINIMAL_STACK_SIZE * sizeof( portSTACK_TYPE ) );
+
+	/* Restore the context of the first task that is going to run. */
+	if( pulISRStack != NULL )
+	{
+		/* Fill the ISR stack with a known value to facilitate debugging. */
+		memset( pulISRStack, portISR_STACK_FILL_VALUE, configMINIMAL_STACK_SIZE * sizeof( portSTACK_TYPE ) );
+		pulISRStack += ( configMINIMAL_STACK_SIZE - 1 );
+
+		/* Kick off the first task. */
+		vStartFirstTask();
+	}
+
+	/* Should not get here as the tasks are now running! */
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch called by portYIELD or taskYIELD.  
+ */
+void vPortYield( void )
+{
+extern void VPortYieldASM( void );
+
+	/* Perform the context switch in a critical section to assure it is
+	not interrupted by the tick ISR.  It is not a problem to do this as
+	each task maintains it's own interrupt status. */
+	portENTER_CRITICAL();
+		/* Jump directly to the yield function to ensure there is no
+		compiler generated prologue code. */
+		asm volatile (	"im VPortYieldASM		\n\t" \
+						"call					\n\t" );
+	portEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Hardware initialisation to generate the RTOS tick.   
+ */
+static void prvSetupTimerInterrupt( void )
+{
+const unsigned portLONG ulCounterValue = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+
+	/* Initialize and start timer1 counter */
+	*(volatile unsigned *) TIMER1_PORT = ulCounterValue;
+	*(volatile unsigned *) TIMERS_CONTROL = TIMER1_ENABLE;
+	
+	/* Enable timer1 interrupt while maintaining other bit states
+	   but disable global enable */
+	*(volatile unsigned *) INTERRUPT_ENABLE &= ~INTERRUPT_GLOBAL_ENABLE;
+	*(volatile unsigned *) INTERRUPT_ENABLE |= INTERRUPT_TIMER1;
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * The interrupt handler placed in the interrupt vector when the scheduler is
+ * started.  The task context has already been saved when this is called.
+ * This handler determines the interrupt source and calls the relevant 
+ * peripheral handler.
+ */
+void vTaskISRHandler( void )
+{
+void vTickISR(void);
+
+	unsigned int_status = *(volatile unsigned *) INTERRUPT_STATUS;
+	if(int_status & INTERRUPT_TIMER1)	vTickISR();
+}
+/*-----------------------------------------------------------*/
+
+/* 
+ * Handler for the timer interrupt.
+ */
+void vTickISR( void )
+{
+	/* Increment the RTOS tick - this might cause a task to unblock. */
+	vTaskIncrementTick();
+
+	/* Clear the timer interrupt */
+	/* ... in this platform, timer interrupt is cleared automatically */
+
+	/* If we are using the preemptive scheduler then we also need to determine
+	if this tick should cause a context switch. */
+	#if configUSE_PREEMPTION == 1
+		vTaskSwitchContext();
+	#endif
+}
+/*-----------------------------------------------------------*/
+
+void zpu_disable_interrupts(void)
+{	
+	*(volatile unsigned *) INTERRUPT_ENABLE &= ~INTERRUPT_GLOBAL_ENABLE;
+}
+
+void zpu_enable_interrupts(void)
+{
+	*(volatile unsigned *) INTERRUPT_ENABLE |= INTERRUPT_GLOBAL_ENABLE;
+}
+
+/*-----------------------------------------------------------*/
+
+void zpu_enter_critical(void)
+{
+	portDISABLE_INTERRUPTS();
+	uxCriticalNesting++;
+}
+									
+void zpu_exit_critical(void)
+{	
+	if( --uxCriticalNesting == 0 )
+	{
+  	  portENABLE_INTERRUPTS();
+  	}
+}
diff --git a/zpu/sw/freertos/port/portasm.s b/zpu/sw/freertos/port/portasm.s
new file mode 100644
index 0000000..29c41ab
--- /dev/null
+++ b/zpu/sw/freertos/port/portasm.s
@@ -0,0 +1,142 @@
+	.extern pxCurrentTCB
+	.extern vTaskISRHandler
+	.extern vTaskSwitchContext
+	.extern uxCriticalNesting
+	.extern pulISRStack
+
+	.global __FreeRTOS_interrupt_handler
+	.global VPortYieldASM
+	.global vStartFirstTask
+
+/* interrupt controller port */
+	.equ INTERRUPT_ENABLE,0x8020
+
+.macro portSAVE_CONTEXT
+	/* PC is at the top of stack */
+	
+	/* store interrupt global enable bit */
+	im INTERRUPT_ENABLE
+	load
+	im 1
+	and
+	
+	/* Store nesting critical level */
+	im uxCriticalNesting
+	load
+	
+	/* Store temporary registers */
+	im 0
+	load			/* store mem[0] */
+	im 4
+	load			/* store mem[4] */
+	im 8
+	load			/* store mem[8] */
+	im 12
+	load			/* store mem[12] */
+	
+	/* Store top of stack at pxCurrentTCB */
+	pushsp
+	im pxCurrentTCB
+	load
+	store
+.endm
+
+.macro portRESTORE_CONTEXT
+	im pxCurrentTCB		/* Load the top of stack value from the TCB. */
+	load
+	load
+	popsp
+	
+	/* Restore the temporary registers. */
+	im 12
+	store				/* restore mem[12] */
+	im 8
+	store				/* restore mem[8] */
+	im 4
+	store				/* restore mem[4] */
+	im 0
+	store				/* restore mem[0] */
+
+	/* Load the critical nesting value. */
+	im uxCriticalNesting
+	store
+
+	/* Set interrupt global enable status */
+	im INTERRUPT_ENABLE
+	load
+	im ~1
+	and
+	or
+	im INTERRUPT_ENABLE
+	store
+
+	/* restore PC and enable interrupts at ZPU level */
+	.byte 0x03			/* popint */
+.endm
+
+.macro portRESTORE_CONTEXT_NOINTERRUPT
+	im pxCurrentTCB		/* Load the top of stack value from the TCB. */
+	load
+	load
+	popsp
+	
+	/* Restore the temporary registers. */
+	im 12
+	store				/* restore mem[12] */
+	im 8
+	store				/* restore mem[8] */
+	im 4
+	store				/* restore mem[4] */
+	im 0
+	store				/* restore mem[0] */
+
+	/* Load the critical nesting value. */
+	im uxCriticalNesting
+	store
+
+	/* Set interrupt global enable status */
+	im INTERRUPT_ENABLE
+	load
+	im ~1
+	and
+	or
+	im INTERRUPT_ENABLE
+	store
+
+	/* restore PC */
+	poppc
+.endm
+
+	.text
+	.align  2
+
+__FreeRTOS_interrupt_handler:
+	portSAVE_CONTEXT
+
+	/* Now switch to use the ISR stack. */
+	im pulISRStack
+	load
+	popsp
+
+	/* Call function */
+	im vTaskISRHandler
+	call
+
+	portRESTORE_CONTEXT
+
+VPortYieldASM:
+	portSAVE_CONTEXT
+
+	/* Now switch to use the ISR stack. */
+	im pulISRStack
+	load
+	popsp
+
+	/* Call function to switch context */
+	im vTaskSwitchContext
+	call
+
+	portRESTORE_CONTEXT_NOINTERRUPT
+
+vStartFirstTask:
+	portRESTORE_CONTEXT_NOINTERRUPT
diff --git a/zpu/sw/freertos/port/portmacro.h b/zpu/sw/freertos/port/portmacro.h
new file mode 100644
index 0000000..2b4d35a
--- /dev/null
+++ b/zpu/sw/freertos/port/portmacro.h
@@ -0,0 +1,125 @@
+/*
+	FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify it
+	under the terms of the GNU General Public License (version 2) as published
+	by the Free Software Foundation and modified by the FreeRTOS exception.
+	**NOTE** The exception to the GPL is included to allow you to distribute a
+	combined work that includes FreeRTOS.org without being obliged to provide
+	the source code for any proprietary components.  Alternative commercial
+	license and support terms are also available upon request.  See the 
+	licensing section of http://www.FreeRTOS.org for full details.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,	but WITHOUT
+	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+	FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+	more details.
+
+	You should have received a copy of the GNU General Public License along
+	with FreeRTOS.org; if not, write to the Free Software Foundation, Inc., 59
+	Temple Place, Suite 330, Boston, MA  02111-1307  USA.
+
+
+	***************************************************************************
+	*                                                                         *
+	* Get the FreeRTOS eBook!  See http://www.FreeRTOS.org/Documentation      *
+	*                                                                         *
+	* This is a concise, step by step, 'hands on' guide that describes both   *
+	* general multitasking concepts and FreeRTOS specifics. It presents and   *
+	* explains numerous examples that are written using the FreeRTOS API.     *
+	* Full source code for all the examples is provided in an accompanying    *
+	* .zip file.                                                              *
+	*                                                                         *
+	***************************************************************************
+
+	1 tab == 4 spaces!
+
+	Please ensure to read the configuration and relevant port sections of the
+	online documentation.
+
+	http://www.FreeRTOS.org - Documentation, latest information, license and
+	contact details.
+
+	http://www.SafeRTOS.com - A version that is certified for use in safety
+	critical systems.
+
+	http://www.OpenRTOS.com - Commercial support, development, porting,
+	licensing and training services.
+*/
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.  
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	unsigned portLONG
+#define portBASE_TYPE	portLONG
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef unsigned portSHORT portTickType;
+	#define portMAX_DELAY ( portTickType ) 0xffff
+#else
+	typedef unsigned portLONG portTickType;
+	#define portMAX_DELAY ( portTickType ) 0xffffffff
+#endif
+/*-----------------------------------------------------------*/	
+
+/* Interrupt control macros. */
+void zpu_disable_interrupts(void);
+void zpu_enable_interrupts(void);
+#define portDISABLE_INTERRUPTS()	zpu_disable_interrupts()
+#define portENABLE_INTERRUPTS()		zpu_enable_interrupts()
+/*-----------------------------------------------------------*/
+
+/* Critical section macros. */
+void zpu_enter_critical(void);
+void zpu_exit_critical(void);
+#define portENTER_CRITICAL()		zpu_enter_critical()
+#define portEXIT_CRITICAL()			zpu_exit_critical()
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+void vPortYield( void );
+#define portYIELD() 				vPortYield()
+
+void vTaskSwitchContext();
+#define portYIELD_FROM_ISR() 		vTaskSwitchContext()
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			4
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_RATE_MS			( ( portTickType ) 1000 / configTICK_RATE_HZ )		
+#define portNOP()					asm volatile ( "nop\n" )
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/zpu/sw/freertos/readme.txt b/zpu/sw/freertos/readme.txt
new file mode 100644
index 0000000..a1f1c89
--- /dev/null
+++ b/zpu/sw/freertos/readme.txt
@@ -0,0 +1,40 @@
+The FreeRTOS port was contributed by
+Antonio Anton .
+
+Some of the files state that someone else is copyright
+holder, but I believe that to be copy and paste laziness
+and that, in fact, Antonio did this port.
+
+The port needs work, but is committed to ZPU git repository
+to get things started.
+
+Post questions to the zylin-zpu mailing list.
+
+Øyvind Harboe
+14/9-2009
+
+From Antonio:
+
+Ported version: 5.3.0
+Port goes to folder ${FREERTOS_ROOT}/Source/portable/GCC/ZPU
+
+portmacro.h : macro definitions for this port
+portasm.s   : contains code for context switch, interrupt handler and
+other initializations
+port.c      : other initialization functions that not need to be
+assembly code.
+
+(please note that #include  in port.c is specific for my ZPU
+port; it contains the definitions my peripherals)
+
+Each FreeRTOS application is compiled with the FreeRTOS port itself
+(source code).
+
+2nd file contains a sample application which includes the Makefile in
+order to compile & link against FreeRTOS port. It will link against some
+specific library (-lio) and specific linker file (sram-zpu.ld) which are
+not included. You must adapt these to your peripheral and memory
+configuration.
+
+At the moment there is no documentation but the source code is quite
+commented.
diff --git a/zpu/sw/freertos/sample/FreeRTOSConfig.h b/zpu/sw/freertos/sample/FreeRTOSConfig.h
new file mode 100644
index 0000000..d9470fd
--- /dev/null
+++ b/zpu/sw/freertos/sample/FreeRTOSConfig.h
@@ -0,0 +1,96 @@
+/*
+	FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify it
+	under the terms of the GNU General Public License (version 2) as published
+	by the Free Software Foundation and modified by the FreeRTOS exception.
+	**NOTE** The exception to the GPL is included to allow you to distribute a
+	combined work that includes FreeRTOS.org without being obliged to provide
+	the source code for any proprietary components.  Alternative commercial
+	license and support terms are also available upon request.  See the 
+	licensing section of http://www.FreeRTOS.org for full details.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,	but WITHOUT
+	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+	FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+	more details.
+
+	You should have received a copy of the GNU General Public License along
+	with FreeRTOS.org; if not, write to the Free Software Foundation, Inc., 59
+	Temple Place, Suite 330, Boston, MA  02111-1307  USA.
+
+
+	***************************************************************************
+	*                                                                         *
+	* Get the FreeRTOS eBook!  See http://www.FreeRTOS.org/Documentation      *
+	*                                                                         *
+	* This is a concise, step by step, 'hands on' guide that describes both   *
+	* general multitasking concepts and FreeRTOS specifics. It presents and   *
+	* explains numerous examples that are written using the FreeRTOS API.     *
+	* Full source code for all the examples is provided in an accompanying    *
+	* .zip file.                                                              *
+	*                                                                         *
+	***************************************************************************
+
+	1 tab == 4 spaces!
+
+	Please ensure to read the configuration and relevant port sections of the
+	online documentation.
+
+	http://www.FreeRTOS.org - Documentation, latest information, license and
+	contact details.
+
+	http://www.SafeRTOS.com - A version that is certified for use in safety
+	critical systems.
+
+	http://www.OpenRTOS.com - Commercial support, development, porting,
+	licensing and training services.
+*/
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. 
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION		1
+#define configUSE_IDLE_HOOK			0
+#define configUSE_TICK_HOOK			0
+#define configCPU_CLOCK_HZ			( ( unsigned portLONG ) 25000000 )
+#define configTICK_RATE_HZ			( ( portTickType ) 100 )
+#define configMAX_PRIORITIES		( ( unsigned portBASE_TYPE ) 4 )
+#define configMINIMAL_STACK_SIZE	( ( unsigned portLONG ) 256 )
+#define configTOTAL_HEAP_SIZE		( ( size_t ) ( 8 * 1024 ) )
+#define configMAX_TASK_NAME_LEN		( 5 )
+#define configUSE_TRACE_FACILITY	0
+#define configUSE_16_BIT_TICKS		0
+#define configIDLE_SHOULD_YIELD		1
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 		0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+
+#define INCLUDE_vTaskPrioritySet		1
+#define INCLUDE_uxTaskPriorityGet		1
+#define INCLUDE_vTaskDelete				0
+#define INCLUDE_vTaskCleanUpResources	0
+#define INCLUDE_vTaskSuspend			1
+#define INCLUDE_vTaskDelayUntil			1
+#define INCLUDE_vTaskDelay				1
+
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/zpu/sw/freertos/sample/Makefile b/zpu/sw/freertos/sample/Makefile
new file mode 100644
index 0000000..d3a6f6f
--- /dev/null
+++ b/zpu/sw/freertos/sample/Makefile
@@ -0,0 +1,50 @@
+PRJ      =  test1
+PATH_SW  =  /home/antonan/desarrollo/zpu/sw
+INCLUDES =  $(PATH_SW)/freertos/Source/portable/GCC/ZPU/portmacro.h \
+		 	FreeRTOSConfig.h
+SRCS_C   =  $(PATH_SW)/freertos/Source/portable/GCC/ZPU/port.c \
+			$(PATH_SW)/freertos/Source/portable/MemMang/heap_1.c \
+		    $(PATH_SW)/freertos/Source/croutine.c \
+			$(PATH_SW)/freertos/Source/list.c \
+			$(PATH_SW)/freertos/Source/queue.c \
+			$(PATH_SW)/freertos/Source/tasks.c \
+			test1.c
+SRCS_ASM =  $(PATH_SW)/freertos/Source/portable/GCC/ZPU/portasm.s
+PATH_INC = -I$(PATH_SW)/include \
+		   -I$(PATH_SW)/freertos/Source/include \
+		   -I$(PATH_SW)/freertos/Source/portable/GCC/ZPU \
+		   -I$(PATH_SW)/freertos/Demo/ZPU \
+		   -I.
+OPTIONS  = -g -Os -DGCC_ZPU 
+LINK 	 = -T $(PATH_SW)/ldscripts/zpu-sram.ld
+CRT      =  $(PATH_SW)/startup/crt-sram.o
+LLIB     = -L $(PATH_SW)/lib
+LIBS     = -lio -lgcc --start-group -lc -lbcc --end-group -lgcc -lio
+LFLAGS   = --relax --gc-sections
+
+OBJS_ASM = $(SRCS_ASM:.s=.o)
+OBJS_C   = $(SRCS_C:.c=.o)
+
+$(PRJ).srec: $(PRJ).out
+	zpu-elf-objcopy -O srec $(PRJ).out $(PRJ).srec
+	zpu-elf-objcopy -O binary $(PRJ).out $(PRJ).bin
+	bin2rom $(PRJ).bin $(PRJ).rom
+
+$(OBJS_ASM): $(SRCS_ASM)
+	zpu-elf-gcc $(OPTIONS) $(PATH_INC) -B. -c -Wa,-ahlms=$(@:.o=.lst) -o $@ $(@:.o=.s)
+
+$(OBJS_C): $(SRCS_C) $(INCLUDES)
+	zpu-elf-gcc $(OPTIONS) $(PATH_INC) -B. -c -Wa,-ahlms=$(@:.o=.lst) -o $@ $(@:.o=.c)
+
+$(PRJ).out: $(CRT) $(OBJS_C) $(OBJS_ASM)
+	zpu-elf-ld $(LLIB) $(LFLAGS) $(LINK) -Map=$(PRJ).map -o $(PRJ).out $(CRT) $(OBJS_C) $(OBJS_ASM) $(LIBS)
+
+
+clean:
+	-rm *.o
+	-rm *.out
+	-rm *.bin
+	-rm *.map
+	-rm *.lst
+	-rm *.srec
+	-rm *.rom
diff --git a/zpu/sw/freertos/sample/test1.c b/zpu/sw/freertos/sample/test1.c
new file mode 100644
index 0000000..41b4296
--- /dev/null
+++ b/zpu/sw/freertos/sample/test1.c
@@ -0,0 +1,67 @@
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#include "devices.h"
+
+#define mainTINY_STACK	256
+void vTest(void *pvParameters);
+void vTest2(void *pvParameters);
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Create all the demo tasks - then start the scheduler.
+ */
+int main (void) 
+{
+	/* When re-starting a debug session (rather than cold booting) we want
+	to ensure the installed interrupt handlers do not execute until after the
+	scheduler has been started. */
+	portDISABLE_INTERRUPTS();
+
+	#if configUSE_PREEMPTION == 1
+		xTaskCreate( vTest, "TST1", mainTINY_STACK, ( void * ) 10, tskIDLE_PRIORITY, NULL );
+		xTaskCreate( vTest2, "TST2", mainTINY_STACK, ( void * ) 10, tskIDLE_PRIORITY, NULL );
+	#endif
+
+	/* Finally start the scheduler. */
+	vTaskStartScheduler();
+
+	/* Should not get here as the processor is now under control of the 
+	scheduler! */
+
+   	return 0;
+}
+
+void vTest(void *pvParameters)
+{
+const portTickType xDelay = 100 / portTICK_RATE_MS;
+	unsigned bit = 16;
+	unsigned dir = 0;   
+	
+	for(;;)
+	{
+		CLEAR_BIT(SP3SK_GPIO, bit);
+		if(dir == 0) { if(++bit == 23) { dir=1; } }
+		else { if(--bit == 16) { dir=0;} }
+		SET_BIT(SP3SK_GPIO, bit);
+		vTaskDelay( xDelay );
+	}
+}
+
+void vTest2(void *pvParameters)
+{
+const portTickType xDelay = 250 / portTICK_RATE_MS;
+	unsigned pos;
+	char marcas[] = "|/-\\";
+	
+	for(;;)
+	{
+		uart1_printline("\r");
+		uart1_printline("Running...");
+		uart1_printchar(marcas[pos]);
+		if(++pos == 4) pos = 0;
+		vTaskDelay( xDelay );
+	}
+}
-- 
cgit v1.1


From 685ce53dfba47bf06a25f2566a157ed5cda8ba1d Mon Sep 17 00:00:00 2001
From: Antonio Anton 
Date: Tue, 15 Sep 2009 10:58:55 +0200
Subject: Avalanche ZPU implementation

---
 zpu/hdl/avalanche/core/zpu_core.v         |  749 +++++++++++++++++++++
 zpu/hdl/avalanche/core/zpu_core_defines.v |  322 +++++++++
 zpu/hdl/avalanche/core/zpu_core_rom.v     | 1017 +++++++++++++++++++++++++++++
 zpu/hdl/avalanche/readme.txt              |   91 +++
 4 files changed, 2179 insertions(+)
 create mode 100644 zpu/hdl/avalanche/core/zpu_core.v
 create mode 100644 zpu/hdl/avalanche/core/zpu_core_defines.v
 create mode 100644 zpu/hdl/avalanche/core/zpu_core_rom.v
 create mode 100644 zpu/hdl/avalanche/readme.txt

diff --git a/zpu/hdl/avalanche/core/zpu_core.v b/zpu/hdl/avalanche/core/zpu_core.v
new file mode 100644
index 0000000..e704fbc
--- /dev/null
+++ b/zpu/hdl/avalanche/core/zpu_core.v
@@ -0,0 +1,749 @@
+`timescale 1ns / 1ps
+`include "zpu_core_defines.v"
+
+/*      MODULE: zpu_core
+        DESCRIPTION: Contains ZPU cpu
+		AUTHOR: Antonio J. Anton (aj  anro-ingenieros.com)
+
+REVISION HISTORY:
+Revision 1.0, 14/09/2009
+Initial public release
+
+COPYRIGHT:
+Copyright (c) 2009 Antonio J. Anton
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the "Software"), to deal in
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+of the Software, and to permit persons to whom the Software is furnished to do
+so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.*/
+
+// --------- MICROPROGRAMMED ZPU CORE ---------------
+// all signals are polled on clk rising edge
+// all signals positive
+
+module zpu_core (
+`ifdef ENABLE_CPU_INTERRUPTS
+	interrupt,		// interrupt request
+`endif	
+	clk,			// clock on rising edge
+	reset,			// reset on rising edge
+	mem_read,		// request memory read
+	mem_write,		// request memory write
+	mem_done,		// memory operation completed
+	mem_addr,		// memory address
+	mem_data_read,	// data readed
+	mem_data_write,	// data written
+	byte_select		// byte select on memory operation
+);
+
+input			clk;
+input			reset;
+output			mem_read;
+output			mem_write;
+input			mem_done;
+input  [31:0]	mem_data_read;
+output [31:0] 	mem_data_write;
+output [31:0]	mem_addr;
+output [3:0]	byte_select;
+`ifdef ENABLE_CPU_INTERRUPTS
+input			interrupt;
+`endif
+
+wire 		clk;
+wire		reset;
+wire		mem_read;
+wire		mem_write;
+wire		mem_done;
+wire [31:0]	mem_data_read;
+wire [31:0] mem_data_write;
+wire [31:0]	mem_addr;
+`ifdef ENABLE_CPU_INTERRUPTS
+wire		interrupt;
+`endif
+
+`ifdef ENABLE_BYTE_SELECT
+// ------ unaligned byte/halfword memory operations -----
+/// TODO: think rewriting into microcode or in a less resource wasting way
+
+reg  [3:0]	byte_select;
+wire		byte_op;
+wire		halfw_op;
+
+reg  [31:0]	mem_data_read_int;	// aligned data from memory
+reg  [31:0] mem_data_write_out;	// write data already aligned
+wire [31:0] mem_data_write_int;	// write data from cpu to be aligned
+
+// --- byte select logic ---
+always @(mem_addr[1:0] or byte_op or halfw_op)
+begin
+  casez( { mem_addr[1:0], byte_op, halfw_op } )
+    4'b00_1_? : byte_select <= 4'b0001;		// byte select
+    4'b01_1_? : byte_select <= 4'b0010;
+    4'b10_1_? : byte_select <= 4'b0100;
+    4'b11_1_? : byte_select <= 4'b1000;
+    4'b0?_0_1 : byte_select <= 4'b0011;		// half word select
+    4'b1?_0_1 : byte_select <= 4'b1100;
+    default   : byte_select <= 4'b1111;		// word select
+  endcase
+end
+
+// --- input data to cpu ---
+always @(mem_data_read or mem_addr[1:0] or byte_op or halfw_op)
+begin
+  casez( { mem_addr[1:0], byte_op, halfw_op } )
+   4'b00_1_? : mem_data_read_int <= { 24'b0, mem_data_read[7:0] };	// 8 bit read
+   4'b01_1_? : mem_data_read_int <= { 24'b0, mem_data_read[15:8] };
+   4'b10_1_? : mem_data_read_int <= { 24'b0, mem_data_read[23:16] };
+   4'b11_1_? : mem_data_read_int <= { 24'b0, mem_data_read[31:24] };
+   4'b0?_0_1 : mem_data_read_int <= { 16'b0, mem_data_read[7:0], mem_data_read[15:8] };	// 16 bit read
+   4'b1?_0_1 : mem_data_read_int <= { 16'b0, mem_data_read[23:16], mem_data_read[31:24] };
+   default   : mem_data_read_int <= { mem_data_read[7:0], mem_data_read[15:8], mem_data_read[23:16], mem_data_read[31:24] };	// 32 bit access (default)
+  endcase
+end
+
+// --- output data from cpu ---
+assign mem_data_write = mem_data_write_out;
+
+always @(mem_data_write_int or mem_addr[1:0] or byte_op or halfw_op)
+begin
+  casez( {mem_addr[1:0], byte_op, halfw_op } )
+    4'b00_1_? : mem_data_write_out <= { 24'bX, mem_data_write_int[7:0] };		// 8 bit write
+    4'b01_1_? : mem_data_write_out <= { 16'bX, mem_data_write_int[7:0], 8'bX };
+    4'b10_1_? : mem_data_write_out <= { 8'bX, mem_data_write_int[7:0], 16'bX };
+    4'b11_1_? : mem_data_write_out <= { mem_data_write_int[7:0], 24'bX };
+    4'b0?_0_1 : mem_data_write_out <= { 16'bX, mem_data_write_int[7:0], mem_data_write_int[15:8] };		// 16 bit write
+    4'b1?_0_1 : mem_data_write_out <= { mem_data_write_int[7:0], mem_data_write_int[15:8], 16'bX };
+    default   : mem_data_write_out <= { mem_data_write_int[7:0], mem_data_write_int[15:8], mem_data_write_int[23:16], mem_data_write_int[31:24] };
+  endcase
+end
+`else
+// -------- only 32 bit memory access --------
+wire [3:0]	byte_select = 4'b1111;			// all memory operations are 32 bit wide
+wire [31:0] mem_data_read_int;				// no byte/halfword memory access by HW
+wire [31:0] mem_data_write_int;				// byte and halfword memory access must be emulated
+
+// ----- reorder bytes due to MSB-LSB configuration -----
+assign mem_data_read_int = { mem_data_read[7:0], mem_data_read[15:8], mem_data_read[23:16], mem_data_read[31:24] };
+assign mem_data_write = { mem_data_write_int[7:0], mem_data_write_int[15:8], mem_data_write_int[23:16], mem_data_write_int[31:24] };
+`endif
+
+// ------ datapath registers and connections -----------
+reg  [31:0]	pc;				// program counter (byte align)
+reg  [31:0] sp;				// stack counter (word align)
+reg  [31:0]	a;				// operand (address_out, data_out, alu_in)
+reg  [31:0]	b;				// operand (address_out)
+reg			idim;			// im opcode being processed
+reg   [7:0]	opcode;			// opcode being processed
+reg  [31:2]	pc_cached;		// cached PC
+reg  [31:0]	opcode_cache;	// cached opcodes (current word)
+`ifdef ENABLE_CPU_INTERRUPTS
+  reg		int_requested;	// interrupt has been requested
+  reg		on_interrupt;	// serving interrupt
+  wire		exit_interrupt;	// microcode says this is poppc_interrupt
+  wire		enter_interrupt; // microcode says we are entering interrupt
+`endif
+wire  [1:0]	sel_opcode = pc[1:0]; 	// which opcode is selected
+wire  		sel_read;		// mux for data-in
+wire  [1:0]	sel_alu;		// mux for alu
+wire  [1:0]	sel_addr;		// mux for addr
+wire		w_pc;			// write PC
+`ifdef ENABLE_PC_INCREMENT
+  wire		w_pc_increment;	// write PC+1
+`endif
+wire		w_sp;			// write SP
+wire		w_a;			// write A (from ALU result)
+wire		w_a_mem;		// write A (from MEM read)
+wire		w_b;			// write B
+wire		w_op;			// write OPCODE (opcode cache)
+wire		set_idim;		// set IDIM
+wire		clear_idim;		// clear IDIM
+wire		is_op_cached = (pc[31:2] == pc_cached) ? 1'b1 : 1'b0;	// is opcode available?
+wire		a_is_zero;		// A == 0
+wire		a_is_neg;		// A[31] == 1
+wire		busy;			// busy signal to microcode sequencer (stalls cpu)
+
+reg [`MC_MEM_BITS-1:0] 	mc_pc;		// microcode PC
+initial mc_pc <= `MC_ADDR_RESET-1;
+wire    [`MC_BITS-1:0]	mc_op;		// current microcode operation
+
+// memory addr / write ports
+assign mem_addr = (sel_addr == `SEL_ADDR_SP) ? sp :
+			      (sel_addr == `SEL_ADDR_A)  ? a  : 
+			   	  (sel_addr == `SEL_ADDR_B)  ? b  : pc;
+assign mem_data_write_int = a;			// only A can be written to memory
+
+// ------- alu instantiation -------
+wire [31:0]					alu_a;
+wire [31:0]					alu_b;
+wire [31:0]					alu_r;
+wire [`ALU_OP_WIDTH-1:0]	alu_op;
+wire						alu_done;
+
+// alu inputs multiplexors
+// constant in microcode is sign extended (in order to implement substractions like adds)
+assign alu_a = 	(sel_read == `SEL_READ_DATA)   ? mem_data_read_int : mem_addr;
+assign alu_b = 	(sel_alu == `SEL_ALU_MC_CONST) ? { {25{mc_op[`P_ADDR+6]}} , mc_op[`P_ADDR+6:`P_ADDR] } :	// most priority
+				(sel_alu == `SEL_ALU_A)		   ? a :
+				(sel_alu == `SEL_ALU_B)	       ? b : { {24{1'b0}} , opcode };	// `SEL_ALU_OPCODE is less priority
+
+zpu_core_alu alu(
+	.alu_a(alu_a),
+	.alu_b(alu_b),
+	.alu_r(alu_r),
+	.alu_op(alu_op),
+	.flag_idim(idim),
+	.clk(clk),
+	.done(alu_done)
+);
+
+// -------- pc : program counter --------
+always @(posedge clk)
+begin
+  if(w_pc)  pc <= alu_r;
+`ifdef ENABLE_PC_INCREMENT		// microcode optimization
+  else if(w_pc_increment) pc <= pc + 1;  // usually pc=pc+1
+`endif
+end
+
+// -------- sp : stack pointer --------
+always @(posedge clk)
+begin
+  if(w_sp) sp <= alu_r;
+end
+
+// -------- a : acumulator register ---------
+always @(posedge clk)
+begin
+  if(w_a) 		   a <= alu_r;
+  else if(w_a_mem) a <= mem_data_read_int;
+end
+
+// alu results over a register instead of alu result
+// in order to improve speed
+assign a_is_zero = (a == 0);
+assign a_is_neg  = a[31];
+
+// -------- b : auxiliary register ---------
+always @(posedge clk)
+begin
+  if(w_b)	b <= alu_r;
+end
+
+// -------- opcode and opcode_cache  --------
+always @(posedge clk)
+begin
+  if(w_op)
+  begin
+    opcode_cache <= alu_r;		// store all opcodes in the word
+    pc_cached <= pc[31:2];		// store PC address of cached opcodes
+  end
+end
+
+// -------- opcode : based on pc[1:0] ---------
+always @(sel_opcode or opcode_cache)	// select current opcode from 
+begin					// the cached opcode word
+    case(sel_opcode)
+	0 : opcode <= opcode_cache[31:24];
+	1 : opcode <= opcode_cache[23:16];
+	2 : opcode <= opcode_cache[15:8];
+	3 : opcode <= opcode_cache[7:0];
+    endcase
+end
+
+// ------- idim : immediate opcode handling  ----------
+always @(posedge clk)
+begin
+  if(set_idim)   	  idim <= 1'b1;
+  else if(clear_idim) idim <= 1'b0;
+end
+
+`ifdef ENABLE_CPU_INTERRUPTS
+// ------ on interrupt status bit -----
+always @(posedge clk)
+begin
+  if(reset | exit_interrupt) on_interrupt <= 1'b0;
+  else if(enter_interrupt)	 on_interrupt <= 1'b1;
+end
+`endif
+
+// ------ microcode execution unit --------
+assign sel_read  = mc_op[`P_SEL_READ];	// map datapath signals with microcode program bits
+assign sel_alu   = mc_op[`P_SEL_ALU+1:`P_SEL_ALU];
+assign sel_addr  = mc_op[`P_SEL_ADDR+1:`P_SEL_ADDR];
+assign alu_op    = mc_op[`P_ALU+3:`P_ALU];
+assign w_sp      = mc_op[`P_W_SP] & ~busy;
+assign w_pc      = mc_op[`P_W_PC] & ~busy;
+assign w_a       = mc_op[`P_W_A] & ~busy;
+assign w_a_mem   = mc_op[`P_W_A_MEM] & ~busy;
+assign w_b	 	 = mc_op[`P_W_B] & ~busy;
+assign w_op      = mc_op[`P_W_OPCODE] & ~busy;
+assign mem_read  = mc_op[`P_MEM_R];
+assign mem_write = mc_op[`P_MEM_W];
+assign set_idim  = mc_op[`P_SET_IDIM] & ~busy;
+assign clear_idim= mc_op[`P_CLEAR_IDIM] & ~busy;
+`ifdef ENABLE_BYTE_SELECT
+assign byte_op	 = mc_op[`P_BYTE];
+assign halfw_op  = mc_op[`P_HALFWORD];
+`endif
+`ifdef ENABLE_PC_INCREMENT
+  assign w_pc_increment = mc_op[`P_PC_INCREMENT] & ~busy;
+`endif
+`ifdef ENABLE_CPU_INTERRUPTS
+  assign exit_interrupt  = mc_op[`P_EXIT_INT]  & ~busy;
+  assign enter_interrupt = mc_op[`P_ENTER_INT] & ~busy;
+`endif
+
+wire   cond_op_not_cached = mc_op[`P_OP_NOT_CACHED];	// conditional: true if opcode not cached
+wire   cond_a_zero 	  	  = mc_op[`P_A_ZERO];			// conditional: true if A is zero
+wire   cond_a_neg 	  	  = mc_op[`P_A_NEG];			// conditional: true if A is negative
+wire   decode 		  	  = mc_op[`P_DECODE];			// decode means jumps to apropiate microcode based on zpu opcode
+wire   branch 		  	  = mc_op[`P_BRANCH];			// unconditional jump inside microcode
+
+wire [`MC_MEM_BITS-1:0]	mc_goto  = { mc_op[`P_ADDR+6:`P_ADDR], 2'b00 };	// microcode goto (goto = high 7 bits)
+wire [`MC_MEM_BITS-1:0] mc_entry = { opcode[6:0], 2'b00 };				// microcode entry point for opcode
+reg  [`MC_MEM_BITS-1:0] next_mc_pc;										// next microcode operation to be executed
+initial next_mc_pc <= `MC_ADDR_RESET-1;
+
+wire cond_branch = (cond_op_not_cached & ~is_op_cached) |		// sum of all conditionals
+				   (cond_a_zero & a_is_zero) |
+				   (cond_a_neg & a_is_neg);
+
+assign busy = ((mem_read | mem_write) & ~mem_done) | ~alu_done;	// busy signal for microcode sequencer
+
+// ------- handle interrupts ---------
+`ifdef ENABLE_CPU_INTERRUPTS
+always @(posedge clk)
+begin
+  if(reset | on_interrupt) int_requested <= 0;
+  else if(interrupt & ~on_interrupt & ~int_requested) int_requested <= 1;	// interrupt requested
+end
+`endif
+
+// ----- calculate next microcode address (next, decode, branch, specific opcode, etc.) -----
+always @(reset or mc_pc or mc_goto or opcode[7:4] or idim or 
+	     decode or branch or cond_branch or mc_entry or busy
+`ifdef ENABLE_CPU_INTERRUPTS
+	     or int_requested
+`endif
+)
+begin
+  // default, next microcode instruction
+  next_mc_pc  <= mc_pc + 1;
+  if(reset)								  next_mc_pc <= `MC_ADDR_RESET;
+  else if(~busy)
+  begin
+    // get next microcode instruction
+    if(branch | cond_branch) 			  next_mc_pc <= mc_goto;
+    else if(decode)						  // decode: entry point of a new zpu opcode
+    begin
+`ifdef ENABLE_CPU_INTERRUPTS
+      if(int_requested & ~idim)			  next_mc_pc <= `MC_ADDR_INTERRUPT;	// microde to enter interrupt mode
+      else
+`endif
+      if(opcode[7]        == `OP_IM) 	  next_mc_pc <= (idim ? `MC_ADDR_IM_IDIM : `MC_ADDR_IM_NOIDIM);
+      else if(opcode[7:5] == `OP_STORESP) next_mc_pc <= `MC_ADDR_STORESP;
+      else if(opcode[7:5] == `OP_LOADSP)  next_mc_pc <= `MC_ADDR_LOADSP;
+      else if(opcode[7:4] == `OP_ADDSP)   next_mc_pc <= `MC_ADDR_ADDSP;
+      else				  				  next_mc_pc <= mc_entry;	// includes EMULATE opcodes
+    end
+  end
+  else next_mc_pc <= mc_pc;		// in case of cpu stalled (busy=1)
+end
+
+// set microcode program counter
+always @(posedge clk) mc_pc <= next_mc_pc;
+
+// ----- microcode program ------
+zpu_core_rom microcode (
+	.addr(next_mc_pc),
+	.data(mc_op),
+	.clk(clk)
+);
+
+// -------------- ZPU debugger --------------------
+`ifdef ZPU_CORE_DEBUG
+//synthesis translate_off
+// ---- register operation dump ----
+always @(posedge clk)
+begin
+  if(~reset)
+  begin
+    if(w_pc) $display("zpu_core: set PC=0x%h", alu.alu_r);
+`ifdef ENABLE_PC_INCREMENT
+    if(w_pc_increment) $display("zpu_core: set PC=0x%h (PC+1)", pc);
+`endif
+    if(w_sp) $display("zpu_core: set SP=0x%h", alu.alu_r);
+    if(w_a) $display("zpu_core: set A=0x%h", alu.alu_r);
+    if(w_a_mem) $display("zpu_core: set A=0x%h (from MEM)", mem_data_read_int);
+    if(w_b)  $display("zpu_core: set B=0x%h", alu.alu_r);
+    if(w_op & ~is_op_cached) $display("zpu_core: set opcode_cache=0x%h, pc_cached=0x%h", alu.alu_r, {pc[31:2], 2'b0});
+`ifdef ENABLE_CPU_INTERRUPTS
+    if(~busy & mc_pc == `MC_ADDR_INTERRUPT) $display("zpu_core: ***** ENTERING INTERRUPT MICROCODE ******"); 
+    if(~busy & exit_interrupt)  $display("zpu_core: ***** INTERRUPT FLAG CLEARED *****");
+    if(~busy & enter_interrupt) $display("zpu_core: ***** INTERRUPT FLAG SET *****");    
+`endif
+    if(set_idim & ~idim) $display("zpu_core: IDIM=1");
+    if(clear_idim & idim) $display("zpu_core: IDIM=0");
+
+// ---- microcode debug ----
+`ifdef ZPU_CORE_DEBUG_MICROCODE
+    if(~busy)
+    begin
+      $display("zpu_core: mc_op[%d]=0b%b", mc_pc, mc_op);
+      if(branch)      $display("zpu_core: microcode: branch=%d", mc_goto);
+      if(cond_branch) $display("zpu_core: microcode: CONDITION branch=%d", mc_goto);
+      if(decode)      $display("zpu_core: decoding opcode=0x%h (0b%b) : branch to=%d ", opcode, opcode, mc_entry);
+    end
+    else $display("zpu_core: busy");
+`endif
+
+// ---- cpu abort in case of unaligned memory access ---
+`ifdef ASSERT_NON_ALIGNMENT
+  /* unaligned word access (except PC) */
+  if(sel_addr != `SEL_ADDR_PC & mem_addr[1:0] != 2'b00 & (mem_read | mem_write) & !byte_op & !halfw_op)
+  begin
+    $display("zpu_core: unaligned word operation at addr=0x%x", mem_addr);
+    $finish;
+  end
+  
+  /* unaligned halfword access */
+  if(mem_addr[0] & (mem_read | mem_write) & !byte_op & halfw_op)
+  begin
+    $display("zpu_core: unaligned halfword operation at addr=0x%x", mem_addr);
+    $finish;
+  end
+`endif
+
+  end
+end
+
+// ----- opcode dissasembler ------
+always @(posedge clk)
+begin
+if(~busy)
+case(mc_pc)
+0 : begin
+	 $display("zpu_core: ------  breakpoint ------");
+	 $finish;
+	end
+4 : $display("zpu_core: ------  shiftleft ------");
+8 : $display("zpu_core: ------  pushsp ------");
+12 : $display("zpu_core: ------  popint ------");
+16 : $display("zpu_core: ------  poppc ------");
+20 : $display("zpu_core: ------  add ------");
+24 : $display("zpu_core: ------  and ------");
+28 : $display("zpu_core: ------  or ------");
+32 : $display("zpu_core: ------  load ------");
+36 : $display("zpu_core: ------  not ------");
+40 : $display("zpu_core: ------  flip ------");
+44 : $display("zpu_core: ------  nop ------");
+48 : $display("zpu_core: ------  store ------");
+52 : $display("zpu_core: ------  popsp ------");
+56 : $display("zpu_core: ------  ipsum ------");
+60 : $display("zpu_core: ------  sncpy ------");
+
+`MC_ADDR_IM_NOIDIM : $display("zpu_core: ------  im 0x%h (1st) ------", opcode[6:0] );
+`MC_ADDR_IM_IDIM   : $display("zpu_core: ------  im 0x%h (cont) ------", opcode[6:0] );
+`MC_ADDR_STORESP   : $display("zpu_core: ------  storesp 0x%h ------", { ~opcode[4], opcode[3:0], 2'b0 } );
+`MC_ADDR_LOADSP    : $display("zpu_core: ------  loadsp 0x%h ------", { ~opcode[4], opcode[3:0], 2'b0 } );
+`MC_ADDR_ADDSP     : $display("zpu_core: ------  addsp 0x%h ------", { ~opcode[4], opcode[3:0], 2'b0 } );
+`MC_ADDR_EMULATE   : $display("zpu_core: ------  emulate 0x%h ------", b[2:0]); // opcode[5:0] );
+
+128 : $display("zpu_core: ------  mcpy ------");
+132 : $display("zpu_core: ------  mset ------");
+136 : $display("zpu_core: ------  loadh ------");
+140 : $display("zpu_core: ------  storeh ------");
+144 : $display("zpu_core: ------  lessthan ------");
+148 : $display("zpu_core: ------  lessthanorequal ------");
+152 : $display("zpu_core: ------  ulessthan ------");
+156 : $display("zpu_core: ------  ulessthanorequal ------");
+160 : $display("zpu_core: ------  swap ------");
+164 : $display("zpu_core: ------  mult ------");
+168 : $display("zpu_core: ------  lshiftright ------");
+172 : $display("zpu_core: ------  ashiftleft ------");
+176 : $display("zpu_core: ------  ashiftright ------");
+180 : $display("zpu_core: ------  call ------");
+184 : $display("zpu_core: ------  eq ------");
+188 : $display("zpu_core: ------  neq ------");
+192 : $display("zpu_core: ------  neg ------");
+196 : $display("zpu_core: ------  sub ------");
+200 : $display("zpu_core: ------  xor ------");
+204 : $display("zpu_core: ------  loadb ------");
+208 : $display("zpu_core: ------  storeb ------");
+212 : $display("zpu_core: ------  div ------");
+216 : $display("zpu_core: ------  mod ------");
+220 : $display("zpu_core: ------  eqbranch ------");
+224 : $display("zpu_core: ------  neqbranch ------");
+228 : $display("zpu_core: ------  poppcrel ------");
+232 : $display("zpu_core: ------  config ------");
+236 : $display("zpu_core: ------  pushpc ------");
+240 : $display("zpu_core: ------  syscall_emulate ------");
+244 : $display("zpu_core: ------  pushspadd ------");
+248 : $display("zpu_core: ------  halfmult ------");
+252 : $display("zpu_core: ------  callpcrel ------");
+//default : $display("zpu_core: mc_pc=0x%h", decode_mcpc);
+endcase
+end
+//synthesis translate_on
+`endif
+endmodule
+
+// --------- ZPU CORE ALU UNIT ---------------
+module zpu_core_alu(
+	alu_a,			// parameter A
+	alu_b,			// parameter B
+	alu_r,			// computed result
+	flag_idim,		// for IMM alu op
+	alu_op,			// ALU operation
+	clk,			// clock for syncronous multicycle operations
+	done			// done signal for alu operation
+);
+
+input [31:0]				alu_a;
+input [31:0]				alu_b;
+input [`ALU_OP_WIDTH-1:0]	alu_op;
+input						flag_idim;
+output [31:0]				alu_r;
+input						clk;
+output						done;
+
+wire [31:0]					alu_a;
+wire [31:0]					alu_b;
+wire [`ALU_OP_WIDTH-1:0]	alu_op;
+wire						flag_idim;
+reg  [31:0]					alu_r;
+wire						clk;
+reg							done;
+
+`ifdef ENABLE_MULT
+// implement 32 bit pipeline multiplier
+reg			mul_running;
+reg	[2:0]	mul_counter;
+wire		mul_done = (mul_counter == 3);
+reg	[31:0]	mul_result, mul_tmp1;
+reg	[31:0]	a_in, b_in;
+
+always@(posedge clk)
+begin
+  a_in		  <= 0;
+  b_in		  <= 0;
+  mul_tmp1	  <= 0;
+  mul_result  <= 0;
+  mul_counter <= 0;
+  if(mul_running)
+  begin	// infer pipeline multiplier
+    a_in		<= alu_a;
+    b_in		<= alu_b;
+    mul_tmp1	<= a_in * b_in;
+    mul_result	<= mul_tmp1;
+    mul_counter <= mul_counter + 1;
+  end
+end
+`endif
+
+`ifdef ENABLE_DIV
+// implement 32 bit divider
+// Unsigned/Signed division based on Patterson and Hennessy's algorithm.
+// Description: Calculates quotient.  The "sign" input determines whether
+// signs (two's complement) should be taken into consideration.
+// references: http://www.ece.lsu.edu/ee3755/2002/l07.html
+reg  [63:0]	  qr;
+wire [33:0]	  diff;
+wire [31:0]   quotient;
+wire [31:0]   dividend;
+wire [31:0]   divider; 	
+reg  [6:0]    bit;
+wire          div_done;
+reg			  div_running;
+reg			  divide_sign;
+reg			  negative_output;
+
+assign div_done = !bit;
+assign diff = qr[63:31] - {1'b0, divider};
+assign quotient  = (!negative_output) ? qr[31:0] : ~qr[31:0] + 1'b1;
+assign dividend  = (!divide_sign || !alu_a[31]) ? alu_a : ~alu_a + 1'b1;
+assign divider   = (!divide_sign || !alu_b[31]) ? alu_b : ~alu_b + 1'b1;
+   
+always@(posedge clk)
+begin
+	bit <= 7'b1_000000;				// divider stopped
+	if(div_running)
+	begin
+	  if(bit[6])					// divider started: initialize registers
+	  begin
+		  bit             <= 7'd32;
+		  qr              <= { 32'd0, dividend };
+          negative_output <= divide_sign && ((alu_b[31] && !alu_a[31]) || (!alu_b[31] && alu_a[31]));
+      end
+      else							// step by step divide
+	  begin
+        if( diff[32] ) 	qr <= { qr[62:0], 1'd0 };
+        else 			qr <= { diff[31:0], qr[30:0], 1'd1 };
+        bit <= bit - 1;
+      end
+   end
+end
+`endif
+
+`ifdef ENABLE_BARREL
+// implement 32 bit barrel shift
+// alu_b[6] == 1 ? left(only arithmetic) : right
+// alu_b[5] == 1 ? logical : arithmetic
+reg			  bs_running;
+reg [31:0]	  bs_result;
+reg  [4:0]	  bs_counter;				// 5 bits
+wire		  bs_left 	 = alu_b[6];
+wire		  bs_logical = alu_b[5];
+wire [4:0]	  bs_moves 	 = alu_b[4:0];
+wire		  bs_done	 = (bs_counter == bs_moves);
+
+always @(posedge clk)
+begin
+  bs_counter <= 0;
+  bs_result  <= alu_a;
+  if(bs_running)
+  begin
+	if(bs_left) 	 bs_result <= { bs_result[30:0], 1'b0 };						// shift left
+	else
+	begin
+	  if(bs_logical) bs_result <= { 1'b0, bs_result[31:1] };						// shift logical right
+	  else			 bs_result <= { bs_result[31], bs_result[31], bs_result[30:1] };// shift arithmetic right
+	end	  
+	bs_counter <= bs_counter + 1;
+  end
+end
+`endif
+
+// ----- alu add/sub  -----
+reg [31:0] alu_b_tmp;
+always @(alu_b or alu_op)
+begin
+  alu_b_tmp <= alu_b;	// by default, ALU_B as is
+  if(alu_op == `ALU_PLUS_OFFSET) alu_b_tmp <= { {25{1'b0}}, ~alu_b[4], alu_b[3:0], 2'b0 };	// ALU_B is an offset if ALU_PLUS_OFFSET operation
+end
+
+reg [31:0] alu_r_addsub;	// compute R=A+B or A-B based on opcode (ALU_PLUSxx / ALU_SUB-CMP)
+always @(alu_a or alu_b_tmp or alu_op)
+begin
+`ifdef ENABLE_CMP  
+  if(alu_op == `ALU_CMP_SIGNED || alu_op == `ALU_CMP_UNSIGNED)	// in case of sub or cmp --> operation is '-'
+  begin
+    alu_r_addsub <= alu_a - alu_b_tmp;
+  end
+  else
+`endif
+  begin
+    alu_r_addsub <= alu_a + alu_b_tmp;	// by default '+' operation
+  end
+end
+
+`ifdef ENABLE_CMP
+// handle overflow/underflow exceptions in ALU_CMP_SIGNED
+reg cmp_exception;
+always @(alu_a[31] or alu_b[31] or alu_r_addsub[31])
+begin
+  cmp_exception <= 0;
+  if( (alu_a[31] == 0 && alu_b[31] == 1 && alu_r_addsub[31] == 1) ||
+	  (alu_a[31] == 1 && alu_b[31] == 0 && alu_r_addsub[31] == 0) ) cmp_exception <= 1;
+end
+`endif
+
+// ----- alu operation selection -----
+always @(alu_a or alu_b or alu_op or flag_idim or alu_r_addsub
+`ifdef ENABLE_CMP
+		or cmp_exception
+`endif
+`ifdef ENABLE_MULT
+		or mul_done or mul_result
+`endif
+`ifdef ENABLE_BARREL
+		or bs_done or bs_result
+`endif
+`ifdef ENABLE_DIV
+		or div_done or div_result
+`endif
+)
+begin
+  done <= 1;		// default alu operations are 1 cycle
+`ifdef ENABLE_MULT
+  mul_running <= 0;
+`endif
+`ifdef ENABLE_BARREL
+  bs_running <= 0;
+`endif
+`ifdef ENABLE_DIV
+  div_running <= 0;
+`endif  
+  alu_r <= alu_r_addsub;	// ALU_PLUS, ALU_PLUS_OFFSET, ALU_SUB and part of ALU_CMP
+  case(alu_op)
+    `ALU_NOP		: alu_r <= alu_a;
+    `ALU_NOP_B		: alu_r <= alu_b;   
+    `ALU_AND		: alu_r <= alu_a & alu_b;
+    `ALU_OR			: alu_r <= alu_a | alu_b;
+    `ALU_NOT		: alu_r <= ~alu_a;
+    `ALU_FLIP		: alu_r <= { alu_a[0], alu_a[1], alu_a[2], alu_a[3], alu_a[4], alu_a[5], alu_a[6], alu_a[7], 
+				     	alu_a[8],alu_a[9],alu_a[10],alu_a[11],alu_a[12],alu_a[13],alu_a[14],alu_a[15],
+				     	alu_a[16],alu_a[17],alu_a[18],alu_a[19],alu_a[20],alu_a[21],alu_a[22],alu_a[23],
+				     	alu_a[24],alu_a[25],alu_a[26],alu_a[27],alu_a[28],alu_a[29],alu_a[30],alu_a[31] };
+    `ALU_IM			: if(flag_idim) alu_r <= { alu_a[24:0], alu_b[6:0] };
+			  		  else 		    alu_r <= { {25{alu_b[6]}}, alu_b[6:0] };
+`ifdef ENABLE_CMP
+	`ALU_CMP_UNSIGNED:if( (alu_a[31] == alu_b[31] && cmp_exception) || 
+						  (alu_a[31] != alu_b[31] && ~cmp_exception) )
+				      begin
+				        alu_r[31] <= ~alu_r_addsub[31];
+				      end
+	`ALU_CMP_SIGNED	: if(cmp_exception)
+				      begin
+				      	alu_r[31] <= ~alu_r_addsub[31];
+				      end
+`endif
+`ifdef ENABLE_XOR
+	`ALU_XOR		: alu_r <= alu_a ^ alu_b;
+`endif
+`ifdef ENABLE_A_SHIFT
+	`ALU_A_SHIFT_RIGHT: alu_r <= { alu_a[31], alu_a[31], alu_a[30:1] };	// arithmetic shift left
+`endif
+`ifdef ENABLE_MULT
+	`ALU_MULT 		: begin
+					    mul_running <= ~mul_done;
+					    done 		<= mul_done;
+					    alu_r 		<= mul_result;
+					  end
+`endif
+`ifdef ENABLE_BARREL
+	`ALU_BARREL		: begin
+					    bs_running <= ~bs_done;
+					    done 	   <= bs_done;
+					    alu_r 	   <= bs_result;
+					  end
+`endif
+`ifdef ENABLE_DIV
+	`ALU_DIV		: begin
+					    div_running<= ~div_done;
+					    done 	   <= div_done;
+					    alu_r 	   <= quotient;
+					  end
+	`ALU_MOD		: begin
+					    div_running<= ~div_done;
+					    done 	   <= div_done;
+					    alu_r 	   <= qr[31:0];
+					  end
+`endif
+  endcase
+end
+
+endmodule
diff --git a/zpu/hdl/avalanche/core/zpu_core_defines.v b/zpu/hdl/avalanche/core/zpu_core_defines.v
new file mode 100644
index 0000000..228f46b
--- /dev/null
+++ b/zpu/hdl/avalanche/core/zpu_core_defines.v
@@ -0,0 +1,322 @@
+/*      MODULE: zpu_core_defines
+        DESCRIPTION: Contains ZPU parameters and other cpu related definitions
+		AUTHOR: Antonio J. Anton (aj  anro-ingenieros.com)
+
+REVISION HISTORY:
+Revision 1.0, 14/09/2009
+Initial public release
+
+COPYRIGHT:
+Copyright (c) 2009 Antonio J. Anton
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the "Software"), to deal in
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+of the Software, and to permit persons to whom the Software is furnished to do
+so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.*/
+
+/* --------------- ISA DOCUMENTATION ------------------
+   stack: 	top of stack = sp, mem[sp]=valid data
+			push: sp=sp-1, then mem[sp]=data
+			pop: data=mem[sp], then sp=sp+1
+	
+   immediates: any opcode instead of im sets idim=0
+
+   MNEMONIC		OPCODE	   HEX	OPERATION
+-  im x			1_xxxxxxx		if(~idim) { idim=1; sp=sp-1; mem[sp]={{25{b[6]}},b[6:0]} }
+								else { idim=1; mem[sp]={mem[sp][24:0], b[6:0]} }
+-  emulate x	001_xxxxx		sp=sp-1; mem[sp]=pc+1; pc=mem[@VECTOR_EMULATE + ]; fetch (used only by microcode)
+-  storesp x	010_xxxxx		mem[sp+x<<2] = mem[sp]; sp=sp+1
+-  loadsp x		011_xxxxx		mem[sp-1] = mem [sp+x<<2]; sp=sp-1
+-  addsp x		0001_xxxx (1x)	mem[sp] = mem[sp]+mem[sp+x<<2]
+
+-  breakpoint	0000_0000 (00)	call exception vector
+   shiftleft	0000_0001 (01)
+-  pushsp		0000_0010 (02) 	mem[sp-1] = sp; sp = sp - 1
+-  popint		0000_0011 (03)  pc=mem[sp]; sp = sp + 1 ; fetch ; decode ; clear_interrupt_flag
+-  poppc		0000_0100 (04)	pc=mem[sp]; sp = sp + 1
+-  add			0000_0101 (05)	mem[sp+1] = mem[sp+1] + mem[sp]; sp = sp + 1
+-  and			0000_0110 (06)	mem[sp+1] = mem[sp+1] & mem[sp]; sp = sp + 1
+-  or			0000_0111 (07)	mem[sp+1] = mem[sp+1] | mem[sp]; sp = sp + 1
+-  load			0000_1000 (08)	mem[sp] = mem[ mem[sp] ]
+-  not			0000_1001 (09)	mem[sp] = ~mem[sp]
+-  flip			0000_1010 (0a)	mem[sp] = flip(mem[sp])
+-  nop			0000_1011 (0b)	-
+-  store		0000_1100 (0c)	mem[mem[sp]] = mem[sp+1]; sp = sp + 2
+-  popsp		0000_1101 (0d)	sp = mem[sp]
+   compare		0000_1110 (0e)  ???? --> opcode recycled (see below)
+   popint		0000_1111 (0f)  duplicated of 0x03 ????? --> opcode recycled (see below)
+
+-  ipsum	    0000_1110 (0e)	c=mem[sp],s=mem[sp+1]; sum=0; while(c-->0) {sum+=halfword(mem[s],s);s+=2}; sp=sp+1; mem[sp]=sum (overwrites mem[0] & mem[4] words)
+-  sncpy		0000_1111 (0f)  c=mem[sp],d=mem[sp+1],s=mem[sp+2]; while( *(char*)s != 0 && c>0 ) {*((char*)d++)=*((char*)s++));c--}; sp=sp+3 (overwrites mem[0] & mem[4] words)
+-  wcpy		    001_00000 (20)  c=mem[sp],d=mem[sp+1],s=mem[sp+2]; while(c-->0) mem[d++]=mem[s++]; sp=sp+3 (overwrites mem[0] & mem[4] words)
+-  wset 	    001_00001 (21)  v=mem[sp],c=mem[sp+1],d=mem[sp+2]; while(c-->0) mem[d++]=v; sp=sp+3 (overwrites mem[0] & mem[4] words)
+			    
+-  loadh		001_00010 (22)  mem[sp] = halfword[ mem[sp] ]
+-  storeh		001_00011 (23)  halfword[mem[sp]] = (mem[sp+1] & 0xFFFF); sp = sp + 2
+-  lessthan		001_00100 (24)	(mem[sp]-mem[sp+1]) < 0 ? mem[sp+1]=1 : mem[sp+1]=0; sp = sp + 1
+-  lessthanorequal 001_00101 (25) (mem[sp]-mem[sp+1]) <= 0 ? mem[sp+1]=1 : mem[sp+1]=0; sp = sp + 1
+-  ulessthan	001_00110 (26)	(unsigned(mem[sp])-unsigned(mem[sp+1]))  < 0 ? mem[sp+1]=1 : mem[sp+1]=0; sp = sp + 1
+-  ulessthanorequal 001_00111 (27) (unsigned(mem[sp])-unsigned(mem[sp+1])) <= 0 || == 0 ? mem[sp+1]=1 : mem[sp+1]=0; sp = sp + 1
+   swap			001_01000 (28)
+-  mult			001_01001 (29)	mem[sp+1] = mem[sp+1] * mem[sp]; sp = sp + 1
+-  lshiftright	001_01010 (2a)	mem[sp+1] = mem[sp+1] >> (mem[sp] & 0x1f); sp = sp + 1
+-  ashiftleft	001_01011 (2b)  mem[sp+1] = mem[sp+1] << (mem[sp] & 0x1f); sp = sp + 1
+-  ashiftright	001_01100 (2c)  mem[sp+1] = mem[sp+1] signed>> (mem[sp] & 0x1f); sp = sp + 1
+-  call			001_01101 (2d)  a = mem[sp]; mem[sp]=pc + 1; pc = a
+-  eq			001_01110 (2e)	mem[sp+1] = (mem[sp] == mem[sp+1]) ? 1 : 0; sp = sp + 1
+-  neq			001_01111 (2f)  mem[sp+1] = (mem[sp] != mem[sp+1]) ? 1 : 0; sp = sp + 1
+-  neg			001_10000 (30)	mem[sp] = NOT(mem[sp])+1
+-  sub			001_10001 (31)  mem[sp+1]=mem[sp+1]-mem[sp]; sp=sp+1
+-  xor			001_10010 (32)	mem[sp+1]=mem[sp] ^ mem[sp+1]; sp=sp+1
+-  loadb		001_10011 (33)  mem[sp] = byte[ mem[sp] ]
+-  storeb		001_10100 (34)  byte[mem[sp]] = (mem[sp+1] & 0xFF); sp = sp + 2
+   div			001_10101 (35)	
+   mod			001_10110 (36)	
+-  eqbranch		001_10111 (37)  mem[sp+1] == 0 ? pc = pc + mem[sp]; sp = sp + 2
+-  neqbranch	001_11000 (38)	mem[sp+1] != 0 ? pc = pc + mem[sp]; sp = sp + 2
+-  poppcrel		001_11001 (39)	pc = pc + mem[sp]; sp = sp + 1
+   config		001_11010 (3a)  
+-  pushpc		001_11011 (3b)	sp=sp-1; mem[sp]=pc
+   syscall		001_11100 (3c)
+-  pushspadd	001_11101 (3d)	mem[sp] = sp + (mem[sp] << 2)
+-  halfmult		001_11110 (3e)	mem[sp+1] = 16bits(mem[sp]) * 16bits(mem[sp+1]); sp = sp + 1
+-  callpcrel	001_11111 (3f)  a = mem[sp]; mem[sp]=pc+1; pc = pc + a;
+
+   gcc seems to be using only:
+
+   add, addsp, and, ashiftleft, ashiftright, call, callpcrel, div, eq, flip, im, lessthan, 
+   lessthanorequal, loadb, loadh, load, loadsp, lshiftright, mod, mult, neg, neqbranch,
+   not, or, poppc, poppcrel, popsp, pushpc, pushspadd, pushsp, storeb, storeh, store, storesp, 
+   sub, ulessthan, ulessthanorequal, xor
+   
+   --------- memory access ----------------------------
+   
+   data is stored in big-endian format into memory:
+   00 MSB .. .. LSB
+   05 ..  .. .. ..
+
+   ---------------------------------------------------- */
+`define SP_START			32'h10	// after reset change in startup code
+`define EMULATION_VECTOR	32'h10	// table of emulated opcodes (interrupt & exception vectors plus up to 5 emulated opcodes)
+`define RESET_VECTOR		32'h20	// reset entry point (can be moved up to 0x3c as per emulation table needs)
+
+// ---- zpu core optimizations/features ----
+`define ZPU_CORE_DEBUG
+//`define ZPU_CORE_DEBUG_MICROCODE
+`define	ASSERT_NON_ALIGNMENT	/* abort cpu in case of non-aligned memory access (only simulation) */
+
+`define ENABLE_BYTE_SELECT		/* allow byte / halfword memory accesses */
+`define ENABLE_CPU_INTERRUPTS	/* enable interrupts to cpu */
+//`define ENABLE_PC_INCREMENT	/* gain 1 clk per opcode but requires microcode changes ** not done at the moment ** */
+//`define ENABLE_A_SHIFT		/* 1 bit arithmetic shift (right) mutual exclusive with barrel shift */
+//`define ENABLE_XOR			/* 1 cycle x-or */
+//`define ENABLE_MULT			/* 32 bit pipelined (3 stages) multiplier */
+//`define ENABLE_DIV			/* 32 bit, up to 32 cycles serial divider */
+`define ENABLE_BARREL			/* n bit logical & arithmetic shift mutual exclusive with 1 bit shift */
+`define ENABLE_CMP				/* enable ALU_CMP_SIGNED and ALU_CMP_UNSIGNED */
+
+// ------- microcode zpu core datapath selectors --------
+`define SEL_READ_DATA		0
+`define SEL_READ_ADDR		1
+
+`define SEL_ALU_A			0
+`define SEL_ALU_OPCODE		1
+`define SEL_ALU_MC_CONST	2
+`define SEL_ALU_B			3
+
+`define SEL_ADDR_PC			0
+`define SEL_ADDR_SP			1
+`define SEL_ADDR_A			2
+`define SEL_ADDR_B			3
+
+`define ALU_OP_WIDTH		4	// alu operation is 4 bits
+
+`define ALU_NOP				0	// r = a
+`define ALU_NOP_B			1	// r = b
+`define ALU_PLUS			2	// r = a + b
+`define ALU_PLUS_OFFSET		3	// r = a + { 27'b0, ~b[4], b[3:0] }
+`define ALU_AND				4	// r = a AND b
+`define ALU_OR				5	// r = a OR b
+`define ALU_NOT				6	// r = NOT a
+`define ALU_FLIP			7	// r = FLIP a
+`define ALU_IM				8	// r = IDIM ? { a[24:0], b[6:0] } : { 25{b[6]}, b[6:0] }
+`ifdef ENABLE_CMP
+  `define ALU_CMP_UNSIGNED	9	// r = (unsigned)a - (unsigned)b (r[31] is overflow/underflow adjusted)
+  `define ALU_CMP_SIGNED	10	// r = (signed)a - (signed)b (r[31] is overflow/underflow adjusted)
+`endif
+`ifdef ENABLE_BARREL
+  `define ALU_BARREL		11	// r = a <<|>> b (logical, arithmetical)
+`endif
+`ifdef ENABLE_A_SHIFT
+  `define ALU_A_SHIFT_RIGHT	11	// r = { a[31], a[31], a[30:29] }  = (signed)a >> 1
+`endif
+`ifdef ENABLE_XOR
+  `define ALU_XOR			12	// r = a XOR b
+`endif
+`ifdef ENABLE_MULT
+  `define ALU_MULT			13	// r = a * b
+`endif
+`ifdef ENABLE_DIV
+  `define ALU_DIV			14	// r = a / b
+  `define ALU_MOD			15	// r = a mod b
+`endif
+
+// ------- special zpu opcodes ------
+`define OP_NOP				8'b0000_1011 // default value for opcode cache on reset
+`define OP_IM				1'b1
+`define OP_EMULATE			3'b001
+`define OP_STORESP			3'b010
+`define OP_LOADSP			3'b011
+`define OP_ADDSP			4'b0001
+
+// ------- microcode memory settings ------
+`define MC_MEM_BITS			9		// 512 microcode operations
+`define MC_BITS				36		// microcode opcode width
+
+// ------- microcode labels for opcode execution -------
+// based on microcode program
+`define MC_ADDR_IM_NOIDIM	488
+`define MC_ADDR_IM_IDIM		491
+`define MC_ADDR_STORESP		493
+`define MC_ADDR_LOADSP		496
+`define MC_ADDR_ADDSP		500
+`define MC_ADDR_EMULATE		504
+`define MC_ADDR_INTERRUPT	484
+`define MC_ADDR_FETCH_NEXT	480
+`define MC_ADDR_FETCH		476
+`define MC_ADDR_RESET		474
+
+// ---------- microcode settings --------------------
+`define P_SEL_READ		0	// alu-A multiplexor between data-in and addr-out (1 bit)
+`define P_SEL_ALU		1	// alu-B multiplexor between a, b, mc_const or opcode (2 bits)
+`define P_SEL_ADDR		3	// addr-out multiplexor between sp, pc, a, b (2 bits)
+`define P_ALU			5	// alu operation (4 bits)
+`define P_W_SP			9	// write sp (from alu-out)
+`define P_W_PC			10	// write pc (from alu-out)
+`define P_W_A			11	// write a (from alu-out)
+`define P_W_B			12	// write b (from alu-out)
+`define P_SET_IDIM		13	// set idim flag
+`define P_CLEAR_IDIM	14	// clear idim flag
+`define P_W_OPCODE		15	// write opcode  (from alu-out) : check if can be written directly from data-in
+`define P_DECODE		16	// jump to microcode entry point based on current opcode
+`define P_MEM_R			17	// request memory read
+`define P_MEM_W			18	// request memory write
+`define P_ADDR			19	// microcode address (7 bits (granularity is 4 words)) or constant to be used at microcode level
+`define P_BRANCH		26	// microcode inconditional branch to address
+`define P_OP_NOT_CACHED	27	// microcode branch if byte[pc] is not cached at opcode
+`define P_A_ZERO		28	// microcode branch if a is zero
+`define P_A_NEG			29	// microcode branch if a is negative a[31]=1
+`define P_W_A_MEM		30	// write a directly from data-in (alu datapath is free to perform any other operation in parallel)
+`ifdef ENABLE_BYTE_SELECT
+  `define P_BYTE			31	// byte memory operation
+  `define P_HALFWORD		32	// half word memory operation
+`endif
+`ifdef ENABLE_PC_INCREMENT
+  `define P_PC_INCREMENT	33	// autoincrement PC bypassing ALU (1 clock gain per opcode) : not implemented at microcode level
+`endif
+`ifdef ENABLE_CPU_INTERRUPTS
+  `define P_EXIT_INT		34	// clear interrupt flag (exit from interrupt)
+  `define P_ENTER_INT		35	// set interrupt flag (enter interrupt)
+`endif
+
+`define MC_SEL_READ_DATA		(`SEL_READ_DATA << `P_SEL_READ)		// 1 bit
+`define MC_SEL_READ_ADDR		(`SEL_READ_ADDR << `P_SEL_READ)
+
+`define MC_SEL_ALU_A			(`SEL_ALU_A << `P_SEL_ALU)			// 2 bit
+`define MC_SEL_ALU_OPCODE		(`SEL_ALU_OPCODE << `P_SEL_ALU)
+`define MC_SEL_ALU_MC_CONST		(`SEL_ALU_MC_CONST << `P_SEL_ALU)
+`define MC_SEL_ALU_B			(`SEL_ALU_B << `P_SEL_ALU)
+
+`define MC_SEL_ADDR_PC			(`SEL_ADDR_PC << `P_SEL_ADDR)		// 2 bits
+`define MC_SEL_ADDR_SP			(`SEL_ADDR_SP << `P_SEL_ADDR)
+`define MC_SEL_ADDR_A			(`SEL_ADDR_A <<  `P_SEL_ADDR)
+`define MC_SEL_ADDR_B			(`SEL_ADDR_B << `P_SEL_ADDR)
+
+`define MC_ALU_NOP				(`ALU_NOP << `P_ALU)				// 4 bits
+`define MC_ALU_NOP_B			(`ALU_NOP_B << `P_ALU)
+`define MC_ALU_PLUS				(`ALU_PLUS << `P_ALU)
+`define MC_ALU_AND				(`ALU_AND << `P_ALU)
+`define MC_ALU_OR				(`ALU_OR << `P_ALU)
+`define MC_ALU_NOT				(`ALU_NOT << `P_ALU)
+`define MC_ALU_FLIP				(`ALU_FLIP << `P_ALU)
+`define MC_ALU_IM				(`ALU_IM << `P_ALU)
+`define MC_ALU_PLUS_OFFSET		(`ALU_PLUS_OFFSET << `P_ALU)
+`ifdef ENABLE_CMP
+  `define MC_ALU_CMP_SIGNED		(`ALU_CMP_SIGNED << `P_ALU)
+  `define MC_ALU_CMP_UNSIGNED	(`ALU_CMP_UNSIGNED << `P_ALU)
+`endif
+`ifdef ENABLE_XOR
+  `define MC_ALU_XOR			(`ALU_XOR << `P_ALU)
+`endif
+`ifdef ENABLE_A_SHIFT
+  `define MC_ALU_A_SHIFT_RIGHT	(`ALU_A_SHIFT_RIGHT << `P_ALU)
+`endif
+`ifdef ENABLE_MULT
+  `define MC_ALU_MULT			(`ALU_MULT << `P_ALU)
+`endif
+`ifdef ENABLE_DIV
+  `define MC_ALU_DIV			(`ALU_DIV << `P_ALU)
+  `define MC_ALU_MOD			(`ALU_MOD << `P_ALU)
+`endif
+`ifdef ENABLE_BARREL
+  `define MC_ALU_BARREL			(`ALU_BARREL << `P_ALU)
+`endif
+
+`define MC_W_SP					(1 << `P_W_SP)
+`define MC_W_PC					(1 << `P_W_PC)
+`define MC_W_A					(1 << `P_W_A)
+`define MC_W_A_MEM				(1 << `P_W_A_MEM)
+`define MC_W_B					(1 << `P_W_B)
+`define MC_W_OPCODE				(1 << `P_W_OPCODE)
+`define MC_SET_IDIM				(1 << `P_SET_IDIM)
+`define MC_CLEAR_IDIM			(1 << `P_CLEAR_IDIM)
+`ifdef ENABLE_BYTE_SELECT
+  `define MC_BYTE				(1 << `P_BYTE)
+  `define MC_HALFWORD			(1 << `P_HALFWORD)
+`endif
+`ifdef ENABLE_PC_INCREMENT
+  `define MC_PC_INCREMENT		(1 << `P_PC_INCREMENT)
+`endif
+`ifdef ENABLE_CPU_INTERRUPTS
+  `define MC_EXIT_INTERRUPT		(1 << `P_EXIT_INT)
+  `define MC_ENTER_INTERRUPT	(1 << `P_ENTER_INT)
+`endif
+
+`define MC_MEM_R				(1 << `P_MEM_R)
+`define MC_MEM_W				(1 << `P_MEM_W)
+
+`define MC_DECODE				(1 << `P_DECODE)
+`define MC_BRANCH				(1 << `P_BRANCH)
+`define MC_BRANCHIF_OP_NOT_CACHED	(1 << `P_OP_NOT_CACHED)
+`define MC_BRANCHIF_A_ZERO		(1 << `P_A_ZERO)
+`define MC_BRANCHIF_A_NEG		(1 << `P_A_NEG)
+
+// microcode common operations
+
+`define MC_ADDR_FETCH_OP	( (`MC_ADDR_FETCH >> 2) << `P_ADDR)			// fetch opcode from memory then decode
+`define MC_ADDR_NEXT_OP		( (`MC_ADDR_FETCH_NEXT >> 2) << `P_ADDR)	// go to next opcode
+`define MC_ADDR_EMULATE_OP	( (`MC_ADDR_EMULATE >> 2) << `P_ADDR)		// EMULATE opcode
+
+`define MC_PC_PLUS_1	(`MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_SEL_ALU_MC_CONST | `MC_ALU_PLUS  | (1 << `P_ADDR) | `MC_W_PC)
+`define MC_SP_MINUS_4	(`MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_SEL_ALU_MC_CONST | `MC_ALU_PLUS  | ((-4 & 127) << `P_ADDR) | `MC_W_SP)
+`define MC_SP_PLUS_4	(`MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_SEL_ALU_MC_CONST | `MC_ALU_PLUS  | (4 << `P_ADDR) | `MC_W_SP)
+`define MC_EMULATE		(`MC_BRANCH | `MC_ADDR_EMULATE_OP)
+
+`define MC_FETCH		(`MC_BRANCHIF_OP_NOT_CACHED | `MC_ADDR_FETCH_OP | `MC_DECODE)	// fetch and decode current PC opcode
+`define MC_GO_NEXT		(`MC_BRANCH | `MC_ADDR_NEXT_OP)				// go to next opcode (PC=PC+1, fetch, decode)
+`define MC_GO_FETCH		(`MC_BRANCH | `MC_ADDR_FETCH_OP)			// go to fetch opcode at PC, then decode
+`define MC_GO_BREAKPOINT (`MC_BRANCH | ((0 >> 2) << `P_ADDR))		// go to breakpoint opcode
+
diff --git a/zpu/hdl/avalanche/core/zpu_core_rom.v b/zpu/hdl/avalanche/core/zpu_core_rom.v
new file mode 100644
index 0000000..62b7229
--- /dev/null
+++ b/zpu/hdl/avalanche/core/zpu_core_rom.v
@@ -0,0 +1,1017 @@
+`timescale 1ns / 1ps
+`include "zpu_core_defines.v"
+
+/*      MODULE: zpu_core_rom
+        DESCRIPTION: Contains microcode program
+		AUTHOR: Antonio J. Anton (aj  anro-ingenieros.com)
+
+REVISION HISTORY:
+Revision 1.0, 14/09/2009
+Initial public release
+
+COPYRIGHT:
+Copyright (c) 2009 Antonio J. Anton
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the "Software"), to deal in
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+of the Software, and to permit persons to whom the Software is furnished to do
+so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.*/
+
+module zpu_core_rom (
+	clk,
+	addr,
+	data
+);
+
+input [`MC_MEM_BITS-1:0]	addr;
+output [`MC_BITS-1:0]		data;
+input 				clk;
+
+wire [`MC_MEM_BITS-1:0]		addr;
+reg  [`MC_BITS-1:0]		data;
+reg  [`MC_BITS-1:0]		memory[(1<<`MC_MEM_BITS)-1:0];
+
+initial data <= 0;
+always @(posedge clk) data <= memory[addr];
+
+// --- clear all memory at startup; for any reason, xilinx xst
+// will not syntetize as block ram if not all memory is initialized ---
+integer n;
+initial begin
+// initialize all memory array
+for(n = 0; n < (1<<`MC_MEM_BITS); n = n + 1) memory[n] = 0;
+
+// ------------------------- MICROCODE MEMORY START -----------------------------------
+
+// As per zpu_core.v, each opcode is executed by microcode. Each opcode microcode entry point
+// is at  << 2 (example pushsp = 0x02 has microcode entry point of 0x08); this leaves
+// room of 4 microcode operations per opcode; if the opcode microcode needs more space,
+// it can jump & link to other microcode address (with the two lower bits at 0). The lower 256 addresses
+// of microcode memory are entry points and code for 0..127 opcodes; other specific opcodes like im, storesp, etc.
+// are directly hardwired to specific microcode addresses at the memory end. Upper 256 addresses are
+// used by microcode continuation (eg. opcodes which needs more microcode operations), entry points, initializations, etc.
+// the idea is to fit the microcode program in a xilinx blockram 512x36.
+
+// ----- OPCODES WITHOUT CONSTANT ------
+
+// 0000_0000 (00) breakpoint -------------------------------------
+memory[0] = `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) |		// b = 4 (#1 in emulate table)
+		`MC_W_B;
+memory[1] = `MC_EMULATE;												// emulate #1 (exception)
+
+// 0000_0001 (01) shiftleft  -------------------------------------
+memory[4] = `MC_GO_BREAKPOINT;
+
+// 0000_0010 (02) pushsp  -------------------------------------
+//	mem[sp-1] = sp
+//	sp = sp - 1
+memory[8] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | 		// a = sp
+		`MC_ALU_NOP | `MC_W_A;
+memory[9] = `MC_SP_MINUS_4;												// sp = sp - 1
+memory[10] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;					// mem[sp]=a
+
+// 0000_0011 (03) popint  -------------------------------------
+`ifdef ENABLE_CPU_INTERRUPTS
+// pc=mem[sp]-1		(emulate stores pc+1 but we must return to
+// sp=sp+1			 pc because interrupt takes precedence to decode)
+// fetch & decode, then clear_interrupt_flag
+// this guarantees that a continous interrupt allows to execute at least one
+// opcode of mainstream program before reentry to interrupt handler
+memory[12] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | 	// pc = mem[sp]-1
+		`MC_MEM_R | `MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST | 
+		((-1 & 127) << `P_ADDR) | `MC_W_PC;
+memory[13] = `MC_SEL_ADDR_PC | `MC_SEL_READ_DATA | `MC_MEM_R |			// opcode_cache = mem[pc]
+		 `MC_W_OPCODE; 
+memory[14] = `MC_SP_PLUS_4 | `MC_DECODE | `MC_EXIT_INTERRUPT;			// sp=sp+1, decode opcode, exit_interrupt
+`else
+memory[12] = `MC_GO_BREAKPOINT;
+`endif
+
+// 0000_0100 (04) poppc  -------------------------------------
+//	pc=mem[sp]
+//	sp = sp + 1
+memory[16] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | 	// pc = mem[sp]
+		`MC_MEM_R | `MC_W_PC; 	
+memory[17] = `MC_SP_PLUS_4;												// sp = sp + 1
+memory[18] = `MC_FETCH;													// opcode cached ? decode : fetch,decode
+
+// 0000_0101 (05) add   -------------------------------------
+//	mem[sp+1] = mem[sp+1] + mem[sp]
+//	sp = sp + 1
+memory[20] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | 			// a = mem[sp] || sp=sp+1
+		`MC_W_A_MEM | `MC_SP_PLUS_4;
+memory[21] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |			// a = a + mem[sp]
+		 `MC_ALU_PLUS | `MC_SEL_ALU_A | `MC_W_A;
+memory[22] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;					// mem[sp] = a
+
+// 0000_0110 (06) and   -------------------------------------
+//	mem[sp+1] = mem[sp+1] & mem[sp]
+//	sp = sp + 1
+memory[24] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R |				// a = mem[sp] || sp=sp+1
+		 `MC_W_A_MEM | `MC_SP_PLUS_4;
+memory[25] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |			// a = a & mem[sp]
+		 `MC_ALU_AND |`MC_SEL_ALU_A | `MC_W_A;
+memory[26] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;					// mem[sp] = a
+
+// 0000_0111 (07) or   -------------------------------------
+//	mem[sp+1] = mem[sp+1] | mem[sp]
+//	sp = sp + 1
+memory[28] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R |				// a = mem[sp] || sp=sp+1
+		 `MC_W_A_MEM | `MC_SP_PLUS_4;
+memory[29] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |	 		// a = a | mem[sp]
+		`MC_ALU_OR | `MC_SEL_ALU_A | `MC_W_A;
+memory[30] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;					// mem[sp] = a
+
+// 0000_1000 (08) load   -------------------------------------
+//	mem[sp] = mem[ mem[sp] ]
+memory[32] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |		// a = mem[sp]
+		 `MC_MEM_R | `MC_W_A;
+memory[33] = `MC_SEL_ADDR_A | `MC_SEL_READ_DATA | `MC_MEM_R | `MC_W_A; 	// a = mem[a]
+memory[34] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;					// mem[sp] = a
+
+// 0000_1001 (09) not   -------------------------------------
+//	mem[sp] = ~mem[sp]
+memory[36] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | 	// a = ~mem[sp]
+		 `MC_MEM_R | `MC_ALU_NOT | `MC_W_A; 							
+memory[37] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;					// mem[sp] = a
+
+// 0000_1010 (0a) flip   -------------------------------------
+//	mem[sp] = flip(mem[sp])
+memory[40] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |		// a = FLIP(mem[sp])
+		 `MC_MEM_R | `MC_ALU_FLIP | `MC_W_A; 							
+memory[41] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;					// mem[sp] = a
+
+// 0000_1011 (0b) nop   -------------------------------------
+memory[44] = `MC_CLEAR_IDIM | `MC_PC_PLUS_1;							// IDIM=0
+memory[45] = `MC_FETCH;
+
+// 0000_1100 (0c) store   -------------------------------------
+//	mem[mem[sp]] <= mem[sp+1]
+//	sp = sp + 2
+memory[48] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |		// b = mem[sp]
+		 `MC_MEM_R | `MC_W_B;
+memory[49] = `MC_SP_PLUS_4;												// sp = sp + 1
+memory[50] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM | `MC_SP_PLUS_4; // a = mem[sp] || sp = sp + 1
+memory[51] = `MC_SEL_ADDR_B | `MC_MEM_W | `MC_GO_NEXT;					// mem[b] = a
+
+// 0000_1101 (0d) popsp   -------------------------------------
+//	sp = mem[sp]
+memory[52] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R |				// sp = mem[sp]
+		 `MC_W_SP | `MC_GO_NEXT;
+
+// 0000_1110 (0e) ipsum    ------------------------------------
+// compare: opcode recycled --> ipsum
+// c=mem[sp];s=mem[sp+1]; sum=0; 
+// while(c-->0) {sum+=halfword(mem[s],s);s++};
+// sp=sp+1; mem[sp]=sum (overwrites mem[0] & mem[4] words)
+// requires HALFWORD memory access
+`ifdef ENABLE_BYTE_SELECT
+memory[56] = `MC_CLEAR_IDIM | `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST |	// b=0
+		(0 << `P_ADDR) | `MC_W_B;
+memory[57] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |		// a=pc+1	save next pc on mem[0]
+		`MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
+memory[58] = `MC_SEL_ADDR_B | `MC_MEM_W | `MC_ALU_NOP_B | `MC_W_B |		// mem[b]=a || b=4
+		`MC_SEL_ALU_MC_CONST | (4 << `P_ADDR);
+memory[59] = `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_W_A |			// a=sp || goto @ipsum_continue1
+		`MC_BRANCH | ((116 >> 2) << `P_ADDR);
+`else
+memory[56] = `MC_GO_BREAKPOINT;
+`endif
+
+// 0000_1111 (0f) sncpy   ---------------------------------------
+// c=mem[sp],d=mem[sp+1],s=mem[sp+2]; 
+// while( *(char*)s != 0 && c>0 ) { *((char*)d++)=*((char*)s++)); c-- }; 
+// sp=sp+1; mem[sp+1]=d; mem[sp]=c 
+// (overwrites mem[0] & mem[4] words)
+// requires BYTE memory access
+`ifdef ENABLE_BYTE_SELECT
+memory[60] = `MC_CLEAR_IDIM | `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST |	// b=0
+		(0 << `P_ADDR) | `MC_W_B;
+memory[61] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |		// a=pc+1	save next pc on mem[0]
+		`MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
+memory[62] = `MC_SEL_ADDR_B | `MC_MEM_W | `MC_ALU_NOP_B | `MC_W_B |		// mem[b]=a || b=4
+		`MC_SEL_ALU_MC_CONST | (4 << `P_ADDR);
+memory[63] = `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_W_A |			// a=sp || goto @sncpy_continue1
+		`MC_BRANCH | ((100 >> 2) << `P_ADDR);
+`else
+memory[60] = `MC_GO_BREAKPOINT;
+`endif
+
+// ------------- microcode opcode continuations ---------------
+// wset_continue1: ------------------------
+memory[64] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |		// a=a+12	save clear stack on mem[4]
+		`MC_SEL_ALU_MC_CONST | (12 << `P_ADDR) | `MC_W_A;
+memory[65] = `MC_SEL_ADDR_B | `MC_MEM_W;								// mem[b]=a
+memory[66] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_PC;// pc=mem[sp] (data)
+memory[67] = `MC_SP_PLUS_4;												// sp=sp+4
+memory[68] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_B; // b=mem[sp] (count)
+memory[69] = `MC_SP_PLUS_4;												// sp=sp+4
+memory[70] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_SP;// sp=mem[sp] (destination @)
+memory[71] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A;				// a=b (count)
+// wset_loop:
+memory[72] = `MC_BRANCHIF_A_ZERO | ( (80 >> 2) << `P_ADDR);					// if(a==0) goto @wset_end
+memory[73] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |		// b=b-1 (count)
+		`MC_SEL_ALU_MC_CONST | ((-1 & 127) << `P_ADDR) | `MC_W_B;
+memory[74] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_W_A;				// a=pc (data)
+memory[75] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_SP_PLUS_4;				// mem[sp]=a || sp=sp+4 (sp=destination@)
+memory[76] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A | 			// a=b (count) || goto @wset_loop
+		`MC_BRANCH | ((72 >> 2) << `P_ADDR);
+// wset_end: wcpy_end: sncpy_end:
+memory[80] = `MC_SEL_ADDR_A | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_PC;	// pc=mem[a] (a is 0)
+memory[81] = `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) |	// b=4
+		`MC_W_B;
+memory[82] = `MC_SEL_ADDR_B | `MC_MEM_R | `MC_SEL_READ_DATA | 			// sp=mem[b] || goto @fetch
+		`MC_W_SP | `MC_FETCH;
+		
+// wcpy_continue1: ------------------------
+memory[84] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |		// a=a+12	save clear stack on mem[4]
+		`MC_SEL_ALU_MC_CONST | (12 << `P_ADDR) | `MC_W_A;
+memory[85] = `MC_SEL_ADDR_B | `MC_MEM_W;								// mem[b]=a
+memory[86] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_B;	// b=mem[sp] (count)
+memory[87] = `MC_SP_PLUS_4;												// sp=sp+4
+memory[88] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_PC;// pc=mem[sp] (destination @)
+memory[89] = `MC_SP_PLUS_4;												// sp=sp+4
+memory[90] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_SP;// sp=mem[sp] (source @)
+memory[91] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A;				// a=b (count)
+// wcpy_loop:
+memory[92] = `MC_BRANCHIF_A_ZERO | ( (80 >> 2) << `P_ADDR);					// if(a==0) goto @wcpy_end
+memory[93] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |		// b=b-1 (count)
+		`MC_SEL_ALU_MC_CONST | ((-1 & 127) << `P_ADDR) | `MC_W_B;
+memory[94] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM |				// a=mem[sp] || sp=sp+4 (sp=source@)
+		`MC_SP_PLUS_4;
+memory[95] = `MC_SEL_ADDR_PC | `MC_MEM_W | `MC_SEL_READ_ADDR | 			// mem[pc]=a || pc=pc+4 (pc=destination@)
+		`MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) | `MC_W_PC;
+memory[96] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A | 			// a=b (count) || goto @wcpy_loop
+		`MC_BRANCH | ((92 >> 2) << `P_ADDR);
+
+`ifdef ENABLE_BYTE_SELECT
+// sncpy_continue1: ---------------------
+memory[100] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |		// a=a+12
+		`MC_SEL_ALU_MC_CONST | (12 << `P_ADDR) | `MC_W_A;
+memory[101] = `MC_SEL_ADDR_B | `MC_MEM_W;								// mem[b]=a
+memory[102] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_B;// b=mem[sp] (count)
+memory[103] = `MC_SP_PLUS_4;											// sp=sp+4
+memory[104] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_PC;// pc=mem[sp] (destination @)
+memory[105] = `MC_SP_PLUS_4;											// sp=sp+4
+memory[106] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_SP;// sp=mem[sp] (source @)
+memory[107] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A;				// a=b (count)
+// sncpy_loop:
+memory[108] = `MC_BRANCHIF_A_ZERO | ( (80 >> 2) << `P_ADDR);				// if(a==0) goto @sncpy_end  (count==0?)
+memory[109] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_BYTE | `MC_W_A_MEM |	// a=BYTE(mem[sp],sp) || sp=sp+1 (sp=source@)
+		`MC_SEL_READ_ADDR | `MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST | 
+		(1 << `P_ADDR) | `MC_W_SP;
+memory[110] = `MC_SEL_ADDR_PC | `MC_MEM_W | `MC_SEL_READ_ADDR |			// BYTE(mem[pc],pc)=a || pc=pc+1 (pc=destination@)
+		`MC_BYTE | `MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST | 
+		(1 << `P_ADDR) | `MC_W_PC;
+memory[111] = `MC_BRANCHIF_A_ZERO | ( (80 >> 2) << `P_ADDR);				// if(a==0) goto @sncpy_end  (mem[src]==0?)
+memory[112] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |		// b=b-1 (count)
+		`MC_SEL_ALU_MC_CONST | ((-1 & 127) << `P_ADDR) | `MC_W_B;
+memory[113] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A | 			// a=b (count) || goto @sncpy_loop
+		`MC_BRANCH | ((108 >> 2) << `P_ADDR);
+
+// ipsum_continue1: -------------------
+memory[116] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |		// a=a+4
+		`MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) | `MC_W_A;
+memory[117] = `MC_SEL_ADDR_B | `MC_MEM_W;								// mem[b]=a		save return sp on mem[4]
+memory[118] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | 		// pc=mem[sp] 	(count)
+		`MC_W_PC;
+memory[119] = `MC_SP_PLUS_4;											// sp=sp+4
+memory[120] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | 		// sp=mem[sp] 	(start @)
+		`MC_W_SP;
+memory[121] = `MC_SEL_ALU_MC_CONST | (0 << `P_ADDR) | `MC_W_B |			// b=0			(sum)
+		`MC_ALU_NOP_B;
+memory[122] = `MC_SEL_ADDR_PC | `MC_SEL_READ_DATA | `MC_W_A;			// a=pc (count)
+// ipsum_loop:
+memory[124] = `MC_BRANCHIF_A_ZERO | ((392 >> 2) << `P_ADDR);				// a == 0 ? goto @ipsum_end
+		
+memory[125] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_HALFWORD |				// b=mem[sp]+b
+		`MC_SEL_READ_DATA | `MC_ALU_PLUS | `MC_SEL_ALU_B | `MC_W_B;
+memory[126] = `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |		// sp=sp+2
+		`MC_SEL_ALU_MC_CONST | (2 << `P_ADDR) | `MC_W_SP;
+memory[127] = `MC_BRANCH | ((408 >> 2) << `P_ADDR);						// goto @ipsum_continue2
+`endif
+
+// -------------------------------------------------------------
+
+// 001_00000 (20) wcpy -----------------------------------------
+// before using this opcode you must save mem[0] & mem[4] words, then wcpy, then restore mems
+// c=mem[sp],d=mem[sp+1],s=mem[sp+2]; while(c-->0) mem[d++]=mem[s++]; sp=sp+3
+memory[128] = `MC_CLEAR_IDIM | `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST |	// b=0
+		(0 << `P_ADDR) | `MC_W_B;
+memory[129] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |		// a=pc+1
+		`MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
+memory[130] = `MC_SEL_ADDR_B | `MC_MEM_W | `MC_ALU_NOP_B | `MC_W_B |	// mem[b]=a || b=4
+		`MC_SEL_ALU_MC_CONST | (4 << `P_ADDR);
+memory[131] = `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_W_A |			// a=sp || goto @wcpy_continue1
+		`MC_BRANCH | ((84 >> 2) << `P_ADDR);
+
+// 001_00001 (21) wset ----------------------------------------
+// before using this opcode you must save mem[0] & mem[4] words, then wset, then restore mems
+// v=mem[sp],c=mem[sp+1],d=mem[sp+2]; while(c-->0) mem[d++]=v; sp=sp+3
+memory[132] = `MC_CLEAR_IDIM | `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST |	// b=0
+		(0 << `P_ADDR) | `MC_W_B;
+memory[133] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |		// a=pc+1
+		`MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
+memory[134] = `MC_SEL_ADDR_B | `MC_MEM_W | `MC_ALU_NOP_B | `MC_W_B |	// mem[b]=a || b=4
+		`MC_SEL_ALU_MC_CONST | (4 << `P_ADDR);
+memory[135] = `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_W_A |			// a=sp || goto @wset_continue1
+		`MC_BRANCH | ((64 >> 2) << `P_ADDR);
+
+// 001_00010 (22) loadh   -------------------------------------
+`ifdef ENABLE_BYTE_SELECT
+//	mem[sp] = HALFWORD(mem[sp], mem[mem[sp]])
+memory[136] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |	// a = mem[sp]
+		 `MC_MEM_R | `MC_W_A;
+memory[137] = `MC_SEL_ADDR_A | `MC_SEL_READ_DATA | `MC_MEM_R |			// a = halfword(a, mem[a])
+		 `MC_W_A | `MC_HALFWORD; 
+memory[138] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;				// mem[sp] = a
+`else
+memory[136] = `MC_GO_BREAKPOINT;
+`endif
+
+// 001_00011 (23) storeh   -------------------------------------
+`ifdef ENABLE_BYTE_SELECT
+//	HALFWORD( mem[mem[sp]] <= mem[sp+1] )
+//	sp = sp + 2
+memory[140] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |	// b = mem[sp]
+		 `MC_MEM_R | `MC_W_B; 
+memory[141] = `MC_SP_PLUS_4;											// sp = sp + 1
+memory[142] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM |				// a = mem[sp] || sp=sp+1
+		 `MC_SP_PLUS_4; 
+memory[143] = `MC_SEL_ADDR_B | `MC_MEM_W | `MC_HALFWORD | `MC_GO_NEXT;	// HALFWORD(mem[b] = a)
+`else
+memory[140] = `MC_GO_BREAKPOINT;
+`endif
+
+// 001_00100 (24) lessthan   -------------------------------------
+// (mem[sp]-mem[sp+1]) < 0 ? mem[sp+1]=1 : mem[sp+1]=0
+// sp=sp+1
+`ifdef ENABLE_CMP
+memory[144] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM |	// a=mem[sp] || sp=sp+1
+	`MC_SP_PLUS_4;
+memory[145] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | `MC_W_B;	// b=mem[sp]
+memory[146] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B |		// a = (a - b) with overflow/underflow correction || goto @lessthan_check
+	`MC_ALU_CMP_SIGNED | `MC_W_A | ((424>>2) << `P_ADDR) | `MC_BRANCH;
+`else
+memory[144] = `MC_GO_BREAKPOINT;
+`endif
+
+// 001_00101 (25) lessthanorequal   -------------------------------------
+// (mem[sp]-mem[sp+1]) <= 0 ? mem[sp+1]=1 : mem[sp+1]=0
+// sp=sp+1
+`ifdef ENABLE_CMP
+memory[148] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM |	// a=mem[sp] || sp=sp+1
+	`MC_SP_PLUS_4;
+memory[149] = `MC_SEL_ADDR_SP | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_B;	// b=mem[sp]
+memory[150] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B |		// a = (a - b) with overflow/underflow correction || goto @lessthanorequal_check
+	`MC_ALU_CMP_SIGNED | `MC_W_A | ((420>>2) << `P_ADDR) | `MC_BRANCH;
+`else
+memory[148] = `MC_GO_BREAKPOINT;
+`endif
+
+// 001_00110 (26) ulessthan   -------------------------------------
+// signA!=signB -> (unsigA < unsigB) == ~(sigA < sigA)
+// signA==signB -> (unsigA < unsigB) ==  (sigA < sigB)
+// (mem[sp]-mem[sp+1]) < 0 ? mem[sp+1]=1 : mem[sp+1]=0
+// sp=sp+1
+`ifdef ENABLE_CMP
+memory[152] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM |	// a=mem[sp] || sp=sp+1
+	`MC_SP_PLUS_4;
+memory[153] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | `MC_W_B;	// b=mem[sp]
+memory[154] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B |		// a = (a - b) with overflow/underflow correction || goto @lessthan_check
+	`MC_ALU_CMP_UNSIGNED | `MC_W_A | ((424>>2) << `P_ADDR) | `MC_BRANCH;
+`else
+memory[152] = `MC_GO_BREAKPOINT;
+`endif
+
+// 001_00111 (27) ulessthanorequal   -------------------------------------
+// (mem[sp]-mem[sp+1]) <= 0 ? mem[sp+1]=1 : mem[sp+1]=0
+// sp=sp+1
+`ifdef ENABLE_CMP
+memory[156] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM |	// a=mem[sp] || sp=sp+1
+	`MC_SP_PLUS_4;
+memory[157] = `MC_SEL_ADDR_SP | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_B;	// b=mem[sp]
+memory[158] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B |		// a = (a - b) with overflow/underflow correction || goto @lessthanorequal_check
+	`MC_ALU_CMP_UNSIGNED | `MC_W_A | ((420>>2) << `P_ADDR) | `MC_BRANCH;
+`else
+memory[156] = `MC_GO_BREAKPOINT;
+`endif
+
+// 001_01000 (28) swap   -------------------------------------
+memory[160] = `MC_GO_BREAKPOINT;
+
+// 001_01001 (29) mult   -------------------------------------
+`ifdef ENABLE_MULT
+//	mem[sp+1] = mem[sp+1] * mem[sp]
+//	sp = sp + 1
+memory[164] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R |			// a = mem[sp] || sp=sp+1
+		 `MC_W_A_MEM | `MC_SP_PLUS_4;
+memory[165] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |			// b = mem[sp]
+		  `MC_W_B;
+memory[166] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B |		// a = a * b   DON'T COMBINE MULTICYCLE ALU
+		  `MC_ALU_MULT | `MC_W_A;										// OPERATIONS WITH MEMORY READ/WRITE
+memory[167] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;				// mem[sp] = a
+`else
+memory[164] = `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | (8 << `P_ADDR) |	// b = 8 (#2 in emulate table)
+		`MC_W_B;
+memory[165] = `MC_EMULATE;												// emulate #2 (mult opcode)
+`endif
+
+// 001_01010 (2a) lshiftright   -------------------------------------
+`ifdef ENABLE_BARREL
+// b = mem[sp] & 5'b1111	: limit to 5 bits (max 31 shifts)
+// b = b | 7'b01_00000		: shift right, logical
+// sp=sp+1
+// a = mem[sp]
+// a = a >> b
+// mem[sp] = a
+memory[168] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |	// b = mem[sp] & 5'b11111
+		`MC_MEM_R | `MC_ALU_AND | `MC_SEL_ALU_MC_CONST | (31 << `P_ADDR) | `MC_W_B;
+memory[169] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_OR |			// b = b | 7'b01_00000 (shift right, logical)
+		`MC_SEL_ALU_MC_CONST | (32 << `P_ADDR) | `MC_W_B;
+memory[170] = `MC_SP_PLUS_4;											// sp = sp + 1
+memory[171] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |			// a = mem[sp] | goto @shift_cont
+		`MC_W_A_MEM | `MC_BRANCH | ((432 >> 2) << `P_ADDR);
+`else
+ `ifdef ENABLE_A_SHIFT
+// a = mem[sp] & 5'b11111
+// sp=sp+1
+// b = FLIP(mem[sp])
+// label: a <= 0 ? goto @fin
+// b = b << 1
+// a = a - 1 || goto @label
+// fin: a = FLIP(b)
+// mem[sp]=a
+memory[168] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |	// a = mem[sp] & 5'b11111
+		`MC_MEM_R | `MC_ALU_AND | `MC_SEL_ALU_MC_CONST | 
+		(31 << `P_ADDR) | `MC_W_A;
+memory[169] = `MC_SP_PLUS_4;											// sp = sp + 1
+memory[170] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |			// b = FLIP(mem[sp])
+		`MC_ALU_FLIP | `MC_W_B;
+memory[171] = `MC_BRANCH | ((448 >> 2) << `P_ADDR);						// goto @lshiftleft_loop
+ `else
+ memory[168] = `MC_GO_BREAKPOINT;
+ `endif
+`endif
+
+// 001_01011 (2b) ashiftleft   -------------------------------------
+`ifdef ENABLE_BARREL
+// b = mem[sp] & 5'b11111	: 5 bit shift
+// b = b | 7'b10_00000		: shift left, arithmetic
+// sp=sp+1
+// a = mem[sp]
+// a = a <> 2) << `P_ADDR);	
+`else
+// a = mem[sp] & 5'b11111
+// sp = sp + 1
+// b = mem[sp]
+// label: a <= 0 ? goto @fin
+// b = b << 1
+// a = a - 1 || goto @label
+// fin: a = b
+// mem[sp] = a
+memory[172] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |	// a = mem[sp] & 5'b11111
+		`MC_MEM_R | `MC_ALU_AND | `MC_SEL_ALU_MC_CONST | 
+		(31 << `P_ADDR) | `MC_W_A;
+memory[173] = `MC_SP_PLUS_4;											// sp = sp + 1
+memory[174] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |			// b = mem[sp]
+		`MC_W_B;
+memory[175] = `MC_BRANCH | ((440 >> 2) << `P_ADDR);						// goto @ashiftleft_loop
+`endif
+
+// 001_01100 (2c) ashiftright   -------------------------------------
+`ifdef ENABLE_BARREL
+// b = mem[sp] & 5'b11111	: 5 bit shift
+// b = b | 7'b00_00000		: shift right, arithmetic
+// sp=sp+1
+// a = mem[sp]
+// a = a >>signed b
+// mem[sp] = a
+memory[176] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |	// b = mem[sp] & 5'b11111
+		`MC_MEM_R | `MC_ALU_AND | `MC_SEL_ALU_MC_CONST |  (31 << `P_ADDR) | `MC_W_B;
+memory[177] = `MC_SP_PLUS_4;											// sp = sp + 1
+memory[178] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |			// a = mem[sp] | goto @shift_cont
+		`MC_W_A_MEM | `MC_BRANCH | ((432 >> 2) << `P_ADDR);
+`else
+ `ifdef ENABLE_A_SHIFT
+// a = mem[sp] & 5'b11111
+// sp = sp + 1
+// b = FLIP(mem[sp])
+// label: a <= 0 ? goto @fin
+// b = b signed_<< 1
+// a = a - 1 || goto @label
+// fin: a = FLIP(b)
+// mem[sp] = a
+memory[176] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |	// a = mem[sp] & 5'b11111
+		`MC_MEM_R | `MC_ALU_AND | `MC_SEL_ALU_MC_CONST | 
+		(31 << `P_ADDR) | `MC_W_A;
+memory[177] = `MC_SP_PLUS_4;											// sp = sp + 1
+memory[178] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |			// b = FLIP(mem[sp])
+		`MC_ALU_FLIP | `MC_W_B;
+memory[179] = `MC_BRANCH | ((432 >> 2) << `P_ADDR);						// goto @ashiftright_loop
+ `else
+memory[176] = `MC_GO_BREAKPOINT;
+ `endif
+`endif
+
+// 001_01101 (2d) call   -------------------------------------
+//	a = mem[sp]
+//	mem[sp]=pc+1
+//	pc = a
+memory[180] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |  	// b = mem[sp]
+		`MC_MEM_R | `MC_W_B;
+memory[181] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | 
+		`MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;				// a = pc + 1
+memory[182] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_ALU_NOP_B | 			// mem[sp] = a || pc = b
+		`MC_SEL_ALU_B | `MC_W_PC;
+memory[183] = `MC_FETCH;												// op_cached? decode : goto next
+
+// 001_01110 (2e) eq   -------------------------------------
+//	a = mem[sp]
+//	sp = sp + 1
+//	(mem[sp] - a == 0) ? mem[sp] = 1 : mem[sp] = 0
+memory[184] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | 			// a = NOT(mem[sp])
+		`MC_SEL_READ_DATA | `MC_ALU_NOT | `MC_W_A;
+memory[185] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR |`MC_ALU_PLUS |		// a = a + 1
+		`MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
+memory[186] = `MC_SP_PLUS_4;											// sp = sp + 1
+memory[187] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | 		// a = mem[sp] + a || goto @eq_check
+		`MC_ALU_PLUS |`MC_SEL_ALU_A | `MC_W_A | 
+		( (416 >> 2) << `P_ADDR) | `MC_BRANCH;
+
+// 001_01111 (2f) neq   -------------------------------------
+//	a = mem[sp]
+//	sp = sp + 1
+//	(mem[sp] - a != 0) ? mem[sp] = 1 : mem[sp] = 0
+memory[188] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |	// a = NOT(mem[sp])
+		`MC_MEM_R | `MC_ALU_NOT | `MC_W_A;
+memory[189] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR |`MC_ALU_PLUS |		// a = a + 1
+		`MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
+memory[190] = `MC_SP_PLUS_4;											// sp = sp + 1
+memory[191] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |			// a = mem[sp] + a || goto @neq_check
+		`MC_ALU_PLUS | `MC_SEL_ALU_A | `MC_W_A | 
+		( (412 >> 2) << `P_ADDR) | `MC_BRANCH;
+
+// 001_10000 (30) neg   -------------------------------------
+//	a = NOT(mem[sp])
+//	a = a + 1
+//	mem[sp] = a
+memory[192] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |	// a = NOT(mem[sp])
+		 `MC_MEM_R | `MC_ALU_NOT | `MC_W_A;
+memory[193] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | 		// a = a + 1
+		 (1 << `P_ADDR) | `MC_SEL_ALU_MC_CONST | `MC_W_A; 				
+memory[194] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;				// mem[sp] = a
+
+// 001_10001 (31) sub   -------------------------------------
+//	mem[sp+1] = mem[sp+1] - mem[sp]
+//  sp = sp + 1
+memory[196] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |	// a = NOT(mem[sp])
+		`MC_MEM_R | `MC_ALU_NOT | `MC_W_A;
+memory[197] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |		// a = a + 1
+		`MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
+memory[198] = `MC_SP_PLUS_4;											// sp = sp + 1
+memory[199] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |			// a = mem[sp] + a || goto @sub_cont (set_mem[sp]=a)
+		`MC_ALU_PLUS | `MC_SEL_ALU_A | `MC_W_A | ((400>>2) << `P_ADDR) |
+		`MC_BRANCH;
+
+// 001_10010 (32) xor   -------------------------------------
+`ifdef ENABLE_XOR
+//	mem[sp+1] = mem[sp+1] ^ mem[sp]
+//	sp = sp + 1
+memory[200] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R |			// a = mem[sp] || sp=sp+1
+		 `MC_W_A_MEM | `MC_SP_PLUS_4;
+memory[201] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |			// a = a ^ mem[sp]
+		 `MC_ALU_XOR |`MC_SEL_ALU_A | `MC_W_A;
+memory[202] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;				// mem[sp] = a
+`else
+// ALU doesn't perform XOR operation
+// mem[sp+1] = mem[sp] ^ mem[sp+1]  -> A^B=(A&~B)|(~A&B)
+// a = ~mem[sp] --> a = ~A
+// sp = sp + 1
+// a = mem[sp] & a --> a = ~A&B
+// b = ~a  --> b = A&~B
+// a = a | b --> a = ~A&B | A&~B
+// mem[sp] = a
+memory[200] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |			// a = ~mem[sp] --> a=~A
+		`MC_ALU_NOT	| `MC_W_A;
+memory[201] = `MC_SP_PLUS_4;											// sp = sp + 1
+memory[202] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |			// a = mem[sp] & a --> a = ~A&B
+		`MC_ALU_AND | `MC_SEL_ALU_A | `MC_W_A;
+memory[203] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_NOT |		// b = ~a || goto @xor_cont --> b = A&~B
+		`MC_W_B | `MC_BRANCH | ((428 >> 2) << `P_ADDR);
+`endif
+
+// 001_10011 (33) loadb   -------------------------------------
+`ifdef ENABLE_BYTE_SELECT
+//	mem[sp] = BYTE(mem[sp], mem[mem[sp]])
+memory[204] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |	// a = mem[sp]
+		 `MC_MEM_R | `MC_W_A;
+memory[205] = `MC_SEL_ADDR_A | `MC_SEL_READ_DATA | `MC_MEM_R |			// a = byte(a, mem[a])
+		 `MC_W_A | `MC_BYTE;
+memory[206] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;				// mem[sp] = a
+`else
+// b=pc
+// pc = mem[sp]
+// opcode_cache=mem[pc]
+// a = opcode
+// mem[sp]=a
+// pc=b
+// fetch
+memory[204] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR |	// b = pc
+		`MC_W_B;
+memory[205] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | 		// pc = mem[sp]
+		`MC_W_PC;
+memory[206] = `MC_SEL_ADDR_PC | `MC_SEL_READ_DATA | `MC_MEM_R |			// opcode_cache = mem[pc]
+		`MC_W_OPCODE;
+memory[207] = `MC_SEL_ALU_OPCODE | `MC_ALU_NOP_B | `MC_W_A |			// a = opcode -> byte(pc, mem[pc]) || goto @loadb_continued
+		`MC_BRANCH | ( (396 >> 2) << `P_ADDR);
+`endif
+
+// 001_10100 (34) storeb   -------------------------------------
+`ifdef ENABLE_BYTE_SELECT
+//	BYTE( mem[mem[sp]] <= mem[sp+1] )
+//	sp = sp + 2
+memory[208] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |	// b = mem[sp]
+		 `MC_MEM_R | `MC_W_B; 
+memory[209] = `MC_SP_PLUS_4;											// sp = sp + 1
+memory[210] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM |				// a = mem[sp] || sp=sp+1
+		 `MC_SP_PLUS_4; 
+memory[211] = `MC_SEL_ADDR_B | `MC_MEM_W | `MC_BYTE | `MC_GO_NEXT;		// BYTE(mem[b] = a)
+`else
+memory[208] = `MC_GO_BREAKPOINT;
+`endif
+
+// 001_10101 (35) div    -------------------------------------
+`ifdef ENABLE_DIV
+// *** TODO: CHECK IF DIVIDE BY ZERO AND RAISE EXCEPTION ***
+//	mem[sp+1] = mem[sp+1] / mem[sp]
+//	sp = sp + 1
+memory[212] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R |			// a = mem[sp] || sp=sp+1
+		 `MC_W_A_MEM | `MC_SP_PLUS_4;
+memory[213] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |			// b = mem[sp]
+		  `MC_W_B;
+memory[214] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B |		// a = a / b   DON'T COMBINE MULTICYCLE ALU
+		  `MC_ALU_DIV | `MC_W_A;										// OPERATIONS WITH MEMORY READ/WRITE
+memory[215] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;				// mem[sp] = a
+`else
+memory[212] = `MC_GO_BREAKPOINT;
+`endif
+
+// 001_10110 (36) mod   -------------------------------------
+`ifdef ENABLE_DIV
+//	mem[sp+1] = mem[sp+1] % mem[sp]
+//	sp = sp + 1
+memory[216] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R |			// a = mem[sp] || sp=sp+1
+		 `MC_W_A_MEM | `MC_SP_PLUS_4;
+memory[217] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |			// b = mem[sp]
+		  `MC_W_B;
+memory[218] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B |		// a = a % b   DON'T COMBINE MULTICYCLE ALU
+		  `MC_ALU_MOD | `MC_W_A;										// OPERATIONS WITH MEMORY READ/WRITE
+memory[219] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;				// mem[sp] = a
+`else
+memory[216] = `MC_GO_BREAKPOINT;
+`endif
+
+// 001_10111 (37) eqbranch   -------------------------------------
+//	a = sp + 1
+//	a = mem[a]
+//	a = mem[sp] || a == 0 ? { pc = pc + a; sp = sp + 2 }
+//	else { sp = sp + 2, pc = pc + 1 }
+memory[220] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR |	// a = sp + 1
+		  `MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) |
+		  `MC_W_A;
+memory[221] = `MC_SEL_ADDR_A | `MC_MEM_R | `MC_W_A;						// a = mem[a]
+memory[222] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A |					// a = mem[sp] || a == 0 ? goto 456 (sp=sp+2, pc=pc+a)
+		 `MC_BRANCHIF_A_ZERO | ((456>>2) << `P_ADDR);
+memory[223] = `MC_BRANCH | ((460>>2) << `P_ADDR);						// else goto 460 (sp=sp+2, pc=pc+1)
+
+// 001_11000 (38) neqbranch   -------------------------------------
+//	a = sp + 1
+//	a = mem[a]
+//	a = mem[sp] || a == 0 ? { sp = sp + 2, pc = pc + 1 }
+//	else { sp = sp + 2, pc = pc + a }
+memory[224] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR |	// a = sp + 1
+		  `MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) | 
+		  `MC_W_A;				
+memory[225] = `MC_SEL_ADDR_A | `MC_MEM_R | `MC_W_A;						// a = mem[a]
+memory[226] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A | 					// a = mem[sp] || a == 0 ? goto 460 (sp=sp+2, pc=pc+1)
+		 `MC_BRANCHIF_A_ZERO | ((460>>2) << `P_ADDR);	
+memory[227] = `MC_BRANCH | ((456>>2) << `P_ADDR);						// else goto 456 (sp=sp+2, pc=pc+a)
+
+// 001_11001 (39) poppcrel   -------------------------------------
+//	a = mem[sp]
+//	sp = sp + 1
+//	pc = pc + a
+memory[228] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R |			// a=mem[sp] || sp=sp+1
+		 `MC_W_A_MEM | `MC_SP_PLUS_4; 
+memory[229] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_SEL_ALU_A |		// pc = pc + a
+		 `MC_ALU_PLUS | `MC_W_PC; 
+memory[230] = `MC_FETCH;												// op_cached? decode : goto next
+
+// 001_11010 (3a) config   -------------------------------------
+memory[232] = `MC_GO_BREAKPOINT;
+
+// 001_11011 (3b) pushpc   -------------------------------------
+//	sp = sp - 1
+//	mem[sp] = pc
+memory[236] = `MC_CLEAR_IDIM | `MC_SP_MINUS_4 | `MC_W_A; 				// a = sp = sp - 1
+memory[237] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;				// mem[sp] = a
+
+// 001_11100 (3c) syscall_emulate  ------------------------------
+memory[240] = `MC_GO_BREAKPOINT;
+
+// 001_11101 (3d) pushspadd   -------------------------------------
+//	a = mem[sp] << 2
+//	mem[sp] = a + sp
+`ifdef ENABLE_BARREL
+memory[244] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | 			// a = mem[sp]
+		`MC_W_A_MEM;
+memory[245] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_BARREL |		// a = a << 2 (left,arithmetic->10_00010)
+		`MC_SEL_ALU_MC_CONST | ( 66 << `P_ADDR) | `MC_W_A;
+memory[246] = `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_SEL_ALU_A |		// a = a + sp
+		 `MC_ALU_PLUS | `MC_W_A; 
+memory[247] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;				// mem[sp] = a
+`else
+memory[244] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM; // a = mem[sp]
+memory[245] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_A |		// a = a + a
+		`MC_ALU_PLUS | `MC_W_A;
+memory[246] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_A |		// a = a + a
+		`MC_ALU_PLUS | `MC_W_A;
+memory[247] = `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_SEL_ALU_A |		// a = a + sp || goto @cont (->mem[sp] = a)
+		 `MC_ALU_PLUS | `MC_W_A | ((400>>2) << `P_ADDR) | `MC_BRANCH;
+`endif
+
+// 001_11110 (3e) halfmult   -------------------------------------
+memory[248] = `MC_GO_BREAKPOINT;
+
+// 001_11111 (3f) callpcrel   -------------------------------------
+//	a = mem[sp]
+//	mem[sp]=pc+1
+//	pc = pc + a
+memory[252] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | 	// b = mem[sp]
+		`MC_MEM_R | `MC_W_B; 
+memory[253] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |		// a = pc + 1
+		`MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;				
+memory[254] = `MC_SEL_ADDR_SP | `MC_MEM_W; 								// mem[sp] = a;
+memory[255] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B |		// pc = pc + b, goto @fetch
+		 `MC_ALU_PLUS | `MC_W_PC | `MC_GO_FETCH;
+
+// --------------------- MICROCODE HOLE -----------------------------------
+
+
+
+
+// --------------------- CONTINUATION OF COMPLEX OPCODES ------------------
+
+`ifdef ENABLE_BYTE_SELECT
+// ipsum_end: ----------
+memory[392] = `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | (0 << `P_ADDR) |	// sp=0
+		`MC_W_SP;
+memory[393] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA |			// pc=mem[sp]	restore next pc
+		`MC_W_PC;
+memory[394] = `MC_SP_PLUS_4;											// sp=sp+4
+memory[395] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA |			// sp=mem[sp]	restore sp
+		`MC_W_SP;
+memory[396] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A;				// a=b (sum)
+memory[397] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_FETCH;					// mem[sp]=a || fetch (return sum)
+`endif
+
+`ifndef ENABLE_BYTE_SELECT
+// loadb continued microcode -----
+// mem[sp]=a || pc=b
+// opcode_cache=mem[pc] || go next
+memory[396] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_SEL_ALU_B |				// mem[sp]=a || pc=b
+		`MC_ALU_NOP_B | `MC_W_PC;
+memory[397] = `MC_SEL_ADDR_PC | `MC_MEM_R | `MC_W_OPCODE | `MC_GO_NEXT;	// opcode_cache=mem[pc] || go next		
+`endif
+
+// sub/pushspadd continued microcode ----------------
+memory[400] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;				// mem[sp] = a
+
+// ----- hole ------
+
+`ifdef ENABLE_BYTE_SELECT
+// ipsum_continue2: ------------
+memory[408] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |		// pc=pc-1; a=pc
+		`MC_SEL_ALU_MC_CONST | ((-1 & 127) << `P_ADDR) | `MC_W_PC |
+		`MC_W_A;
+memory[409] = `MC_BRANCH | ((124 >> 2) << `P_ADDR);						// goto @ipsum_loop
+`endif
+
+// neqcheck ----------
+memory[412] = `MC_BRANCHIF_A_ZERO | ((468 >> 2) << `P_ADDR);				// a == 0 ? goto @set_mem[sp]=0
+memory[413] = `MC_BRANCH | ((464 >> 2) << `P_ADDR);						// else goto @set_mem[sp]=1
+
+// eqcheck ----------
+memory[416] = `MC_BRANCHIF_A_ZERO | ((464 >> 2) << `P_ADDR);				// a == 0 ? goto @set_mem[sp]=1
+memory[417] = `MC_BRANCH | ((468 >> 2) << `P_ADDR);						// else goto @set_mem[sp]=0
+
+// lessthanorequal_check ----
+memory[420] = `MC_BRANCHIF_A_ZERO | `MC_BRANCHIF_A_NEG | ((464 >> 2) << `P_ADDR); 	// a <= 0 ? goto @set_mem[sp]=1
+memory[421] = `MC_BRANCH | ((468 >> 2) << `P_ADDR);						// else goto @set_mem[sp]=0
+
+// lessthan_check ----
+memory[424] = `MC_BRANCHIF_A_NEG | ((464 >> 2) << `P_ADDR);					// a < 0 ? goto @set_mem[sp]=1
+memory[425] = `MC_BRANCH | ((468 >> 2) << `P_ADDR);						// else goto @set_mem[sp]=0
+
+// xor_cont continued microcode -----------------------------------
+`ifndef ENABLE_XOR
+memory[428] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_OR |			// a = a | b --> a = ~A&B | A&~B
+		`MC_SEL_ALU_B | `MC_W_A;
+memory[429] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;				// mem[sp] = a
+`endif
+
+// ashiftright_loop continued microcode -----------------------------------
+`ifdef ENABLE_BARREL
+memory[432] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_BARREL |		// a = a {<<|>>} b
+		`MC_SEL_ALU_B | `MC_W_A;
+memory[433] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;				// mem[sp] = a
+`else
+ `ifdef ENABLE_A_SHIFT
+memory[432] = `MC_BRANCHIF_A_ZERO | `MC_BRANCHIF_A_NEG | ((436 >> 2) << `P_ADDR); // (a <= 0) ? goto @ashiftright_exit
+memory[433] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |		// a = a + (-1)
+		`MC_SEL_ALU_MC_CONST | ( (-1 & 127) << `P_ADDR) | `MC_W_A;
+memory[434] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | 		// b = b signed_<< 1 || goto @ashiftright_loop
+		`MC_SEL_ALU_B | `MC_W_B | `MC_BRANCH | ((432 >>2) << `P_ADDR);
+// ashiftright_exit
+memory[436] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_FLIP |		// a = FLIP(b)
+		`MC_W_A;
+memory[437] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;				// mem[sp] = a
+ `endif
+`endif
+
+// ashiftleft_loop continued microcode -----------------------------------
+`ifndef ENABLE_BARREL
+memory[440] = `MC_BRANCHIF_A_ZERO | `MC_BRANCHIF_A_NEG | ((444 >> 2) << `P_ADDR);// (a <= 0) ? goto @ashiftleft_exit
+memory[441] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |		// a = a + (-1)
+		`MC_SEL_ALU_MC_CONST | ( (-1 & 127) << `P_ADDR) | `MC_W_A;
+memory[442] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |		// b = b << 1 || goto @ashiftleft_loop
+		`MC_SEL_ALU_B | `MC_W_B | `MC_BRANCH | ((440 >>2) << `P_ADDR);
+// ashiftleft_exit
+memory[444] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_NOP |		// a = b
+		`MC_W_A;
+memory[445] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;				// mem[sp] = a
+`endif
+
+// lshiftright_loop continued microcode -----------------------------------
+`ifdef ENABLE_A_SHIFT
+memory[448] = `MC_BRANCHIF_A_ZERO | `MC_BRANCHIF_A_NEG | ((452 >> 2) << `P_ADDR);// (a <= 0) ? goto @lshiftright_exit
+memory[449] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |		// a = a + (-1)
+		`MC_SEL_ALU_MC_CONST | ( (-1 & 127) << `P_ADDR) | `MC_W_A;
+memory[450] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |		// b = b << 1 || goto @lshiftright_loop
+		`MC_SEL_ALU_B | `MC_W_B | `MC_BRANCH | ((448 >>2) << `P_ADDR);
+// lshiftright_exit
+memory[452] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_FLIP |		// a = FLIP(b)
+		`MC_W_A;
+memory[453] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;				// mem[sp] = a
+`endif
+
+// neqbranch / eqbranch --- continued microcode   -------------------------------------
+//	sp = sp + 2
+// 	pc = pc + a
+memory[456] = `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | 		// sp = sp + 2
+		`MC_SEL_ALU_MC_CONST | (8 << `P_ADDR) | `MC_W_SP;				
+memory[457] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_SEL_ALU_A |		// pc = pc + a
+		 `MC_ALU_PLUS | `MC_W_PC; 
+memory[458] = `MC_FETCH;												// op_cached? decode : goto fetch
+
+// neqbranch / eqbranch  --- continued microcode   -------------------------------------
+//	sp = sp + 2
+//  pc = pc + 1
+memory[460] = `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | 		// sp = sp + 2
+		`MC_SEL_ALU_MC_CONST | (8 << `P_ADDR) | `MC_W_SP; 				
+memory[461] = `MC_PC_PLUS_1;											// pc = pc + 1
+memory[462] = `MC_FETCH;												// op_cached? decode : goto fetch
+
+// neq / eq / lessthan_1 --- continued microcode   --------------------
+// 	mem[sp] = 1
+memory[464] = `MC_SEL_ALU_MC_CONST | `MC_ALU_NOP_B | (1 << `P_ADDR) |	// a = 1
+		 `MC_W_A; 
+memory[465] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;				// mem[sp] = a
+
+// neq / eq / lessthan_0 --- continued microcode   --------------------
+//	mem[sp] = 0
+memory[468] = `MC_SEL_ALU_MC_CONST | `MC_ALU_NOP_B | (0 << `P_ADDR) |	// a = 0
+		 `MC_W_A; 
+memory[469] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;				// mem[sp] = a
+
+// MICROCODE ENTRY POINT AFTER RESET   -------------------------------
+// initialize cpu registers
+//	sp = @SP_START
+//	pc = @RESET_VECTOR
+memory[473] = 0; 														// reserved and empty for correct cpu startup
+memory[474] = `MC_CLEAR_IDIM |`MC_SEL_ALU_MC_CONST | `MC_ALU_NOP_B | 	// sp = @SP_START
+		(`SP_START << `P_ADDR) | `MC_W_SP;
+memory[475] = `MC_SEL_ALU_MC_CONST | `MC_ALU_NOP_B | `MC_W_PC |			// pc = @RESET
+		(`RESET_VECTOR << `P_ADDR) | `MC_EXIT_INTERRUPT;				// enable interrupts on reset
+// fall throught fetch/decode
+
+// FETCH / DECODE   -------------------------------------
+//	opcode=mem[pc]
+//	decode (goto microcode entry point for opcode)
+memory[476] = `MC_SEL_ADDR_PC | `MC_SEL_READ_DATA | `MC_MEM_R |			// opcode_cache = mem[pc]
+		 `MC_W_OPCODE; 
+memory[477] = `MC_DECODE;												// decode jump to microcode
+
+// NEXT OPCODE   -------------------------------------
+//	pc = pc + 1
+//  opcode cached ? decode : goto fetch
+memory[480] = `MC_PC_PLUS_1;											// pc = pc + 1
+memory[481] = `MC_FETCH;												// pc_cached ? decode else fetch,decode
+
+// INTERRUPT REQUEST   -------------------------------------
+//	sp = sp - 1
+//	mem[sp] = pc
+//	pc = mem[EMULATED_VECTORS + 0]
+memory[484] = `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | (0 << `P_ADDR) |	// b = 0 (#0 in emulate table) || disable interrupts
+		`MC_W_B | `MC_ENTER_INTERRUPT;
+memory[485] = `MC_EMULATE;												// emulate #0 (interrupt)
+
+// ---------------- OPCODES WITH PARAMETER IN OPCODE ----------------
+
+// im x (idim=0)	1_xxxxxxx   -------------------------------------
+//	sp = sp - 1
+//	mem[sp] = IMM(IDIM, opcode)
+//	idim = 1
+memory[488] = `MC_SP_MINUS_4;											// sp = sp - 1
+memory[489] = `MC_SEL_ALU_OPCODE | `MC_ALU_IM | `MC_W_A;				// a = IMM(IDIM, opcode)
+memory[490] = `MC_SET_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_W |				// MEM[sp] = a; IDIM=1
+	 `MC_GO_NEXT;
+
+// 1_xxxxxxx im x (idim=1)	   -------------------------------------
+//	mem[sp] = IMM(IDIM, mem[sp], opcode)
+memory[491] = `MC_SET_IDIM | `MC_SEL_READ_DATA | `MC_SEL_ADDR_SP |		// a = IMM(IDIM, MEM[sp], opcode)
+		 `MC_MEM_R | `MC_SEL_ALU_OPCODE | `MC_ALU_IM | `MC_W_A; 		
+memory[492] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;				// MEM[sp] = a
+
+// 010_xxxxx storesp x	
+//	mem[sp + x<<2] = mem[sp]
+//	sp = sp + 1
+memory[493] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR |	// b = sp + offset
+		 `MC_ALU_PLUS_OFFSET | `MC_SEL_ALU_OPCODE | `MC_W_B;		
+memory[494] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM |				// a=mem[sp] || sp=sp+1
+		 `MC_SP_PLUS_4; 
+memory[495] = `MC_SEL_ADDR_B | `MC_MEM_W | `MC_GO_NEXT;					// mem[b] = a
+
+// 011_xxxxx loadsp x	   -------------------------------------
+//	mem[sp-1] = mem [sp + x<<2]
+//	sp = sp - 1
+memory[496] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR |	// a = sp + offset
+		 `MC_ALU_PLUS_OFFSET | `MC_SEL_ALU_OPCODE | `MC_W_A; 			
+memory[497] = `MC_SEL_ADDR_A | `MC_SEL_READ_DATA | `MC_MEM_R | `MC_W_A; // a = mem[a]
+memory[498] = `MC_SP_MINUS_4;								 			// sp = sp - 1
+memory[499] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;				// mem[sp] = a
+
+// 0001_xxxx addsp x	   -------------------------------------
+// 	mem[sp] = mem[sp] + mem[sp + x<<2]
+memory[500] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR |	// a = sp + offset
+		 `MC_ALU_PLUS_OFFSET | `MC_SEL_ALU_OPCODE | `MC_W_A; 			
+memory[501] = `MC_SEL_ADDR_A | `MC_SEL_READ_DATA | `MC_MEM_R | `MC_W_A; // a = mem[a]
+memory[502] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
+		 `MC_ALU_PLUS | `MC_SEL_ALU_A | `MC_W_A; 						// a = a + mem[sp]
+memory[503] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;				// mem[sp] = a
+
+// 001_xxxxx emulate x	   -------------------------------------
+//  
+//	sp = sp - 1
+//	mem[sp] = pc + 1				emulated opcode microcode must set b to
+//  a=@EMULATION_TABLE				offset inside emulated_table prior to
+//  pc = mem[a + b]					calling the emulate microcode
+//  fetch
+memory[504] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR |	// a = pc + 1
+		`MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
+memory[505] = `MC_SP_MINUS_4;											// sp = sp - 1
+memory[506] = `MC_SEL_ADDR_SP | `MC_MEM_W;								// mem[sp] = a
+memory[507] = `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | `MC_W_A | 			// a = @vector_emulated
+		(`EMULATION_VECTOR << `P_ADDR);
+memory[508] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |		// a = a + b
+		`MC_SEL_ALU_B | `MC_W_A;
+memory[509] = `MC_SEL_ADDR_A | `MC_MEM_R | `MC_SEL_READ_DATA | 			// pc = mem[a]
+		`MC_ALU_NOP | `MC_W_PC;
+memory[510] = `MC_FETCH;
+
+// --------------------- END OF MICROCODE PROGRAM --------------------------
+end
+
+endmodule
diff --git a/zpu/hdl/avalanche/readme.txt b/zpu/hdl/avalanche/readme.txt
new file mode 100644
index 0000000..3eb1baf
--- /dev/null
+++ b/zpu/hdl/avalanche/readme.txt
@@ -0,0 +1,91 @@
+This ZPU implementation, codenamed "avalanche" was
+contributed by Antonio Anton .
+
+It's most interesting aspects are it's implementation using
+microcode, small size, reduced code size overhead and that
+it's implemented in Verilog.
+
+Please direct any questions to the zylin-zpu mailing list.
+
+The most urgently needed patches would be to provide working
+simulation examples and improved documentation.
+
+
+Øyvind Harboe
+
+
+Notes from Antonio:
+
+Hi,
+
+attached goes my zpu implementation in verilog in case anybody is
+interested in. Code is quite commented. Also microcode and opcodes are
+exhaustive commented (and more accurate that the HTML documentation in
+some cases :-) ).
+
+At the moment I have no time to send a working environment but I will
+get some time in next days and prepare a clean environment
+(software/hardware) and send to the list. The target HW is spartan3
+starter kit board (all peripherals working: vga, sram, uarts, etc.).
+
+Feel free to ask any question to the list I will do my best to answer
+quickly.
+
+Regards
+Antonio
+
+Hi,
+
+the zpu_core is complete and lot of bugs has been solved in the past but
+extensive testing and a complete test program has not been
+defined/executed; anyway I'm quite confident it works: this core
+executes eCos, FreeRTOS, Forth and other applications.
+
+Regarding FPGA resources for a "balanced" implementation (not the
+smallest, not the fastest):
+
+-cpu+alu+microcode rom: 671 LUT + 239 FF + 1 BRAM (50% of LUT is ALU)
+-complete soc (cpu, vga, uart, memory controller, interrupt controller,
+timers, gpio, spi, etc.): 1317 LUT + 716 FF + 1 BRAM
+
+Regarding "modelsim hello world"; I'm sorry but I don't modelsim;
+instead I use Icarus Verilog & gtkwave. The core has a "debug" facility
+which displays all opcode and registers (memory changes, sp, pc, etc..)
+during simulation execution.
+
+Regards
+Antonio
+
+	
+> > Regarding FPGA resources for a "balanced" implementation (not the
+> > smallest, not the fastest):
+> >
+> > -cpu+alu+microcode rom: 671 LUT + 239 FF + 1 BRAM (50% of LUT is ALU)
+>
+> Are there any emulated instructions not implemented in
+> microcode?
+>
+
+*All* zpu opcodes are microcoded. For some opcodes (like  *shift*),
+there are two versions; 32 bit barrel shift in HDL (up to 32 clocks) or
+1 bit shift in HDL microcode drived (up to ~130 clocks). They are
+selectable via `DEFINES in the zpu_core_defines.v
+
+Other opcodes like mult and div are 32 bit HDL only at the moment (there
+are enough room in microcode memory to implement as microcode) and
+software emulable as well.
+
+For the above figures (671 LUT + 239 FF): *shift* are 32 bit HDL and
+mult/div are software implemented.
+
+There are new opcodes (as per my needs) like memory bulk copy (sncpy,
+wcpy, wset) and ip checksum calculation (ipsum). There are room in
+microccode memory to define new opcodes using the holes in the ISA (for
+a complete list of opcodes and its function please see
+zpu_core_defines.v).
+
+Some future ideas (easy to implement in microcode)
+-on-chip debug
+-microcode update via software
+
+Regards
-- 
cgit v1.1


From c3a6c5f8c614919982ef31c9e8e324525ce105b1 Mon Sep 17 00:00:00 2001
From: Alvaro 
Date: Fri, 22 Oct 2010 18:18:33 +0200
Subject: zpu_core_small: load

memAAddr is not being initialized during IO read operations
(LOAD). This might cause spurious writes to invalid addresses,
and invalid values to be loaded onto the stack. This patch
explicitly sets memAAddr to correct value (sp).
---
 zpu/hdl/zpu4/core/zpu_core_small.vhd | 1 +
 1 file changed, 1 insertion(+)

diff --git a/zpu/hdl/zpu4/core/zpu_core_small.vhd b/zpu/hdl/zpu4/core/zpu_core_small.vhd
index f9484bb..681fb09 100644
--- a/zpu/hdl/zpu4/core/zpu_core_small.vhd
+++ b/zpu/hdl/zpu4/core/zpu_core_small.vhd
@@ -494,6 +494,7 @@ begin
 							null; 
 					end case;
 				when State_ReadIO =>
+					memAAddr <= sp;
 					if (in_mem_busy = '0') then
 						state <= State_Fetch;
 						memAWriteEnable <= '1';
-- 
cgit v1.1


From b103d820a57859fc4aad48f50029e12cc1db7611 Mon Sep 17 00:00:00 2001
From: Bert Lange 
Date: Tue, 1 Mar 2011 17:36:01 +0100
Subject: beautify

Signed-off-by: Bert Lange 
---
 zpu/hdl/zpu4/core/zpu_config.vhd     |   32 +-
 zpu/hdl/zpu4/core/zpu_core.vhd       | 1820 ++++++++++++++++++----------------
 zpu/hdl/zpu4/core/zpu_core_small.vhd | 1065 ++++++++++----------
 zpu/hdl/zpu4/core/zpupkg.vhd         |  338 ++++---
 4 files changed, 1679 insertions(+), 1576 deletions(-)

diff --git a/zpu/hdl/zpu4/core/zpu_config.vhd b/zpu/hdl/zpu4/core/zpu_config.vhd
index 4fecf01..112dd01 100644
--- a/zpu/hdl/zpu4/core/zpu_config.vhd
+++ b/zpu/hdl/zpu4/core/zpu_config.vhd
@@ -39,19 +39,21 @@ use ieee.std_logic_unsigned.all;
 use ieee.std_logic_arith.all;
 
 package zpu_config is
-	-- generate trace output or not.
-	constant	Generate_Trace		: boolean := false;
-	constant wordPower			: integer := 5;
-	-- during simulation, set this to '0' to get matching trace.txt 
-	constant	DontCareValue		: std_logic := 'X';
-	-- Clock frequency in MHz.
-	constant	ZPU_Frequency		: std_logic_vector(7 downto 0) := x"64";
-	-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
-	constant 	maxAddrBitIncIO		: integer := 15;
-	constant 	maxAddrBitBRAM		: integer := 14;
-	
-	-- start byte address of stack. 
-	-- point to top of RAM - 2*words
-	constant 	spStart				: std_logic_vector(maxAddrBitIncIO downto 0) :=
-					conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1);
+
+  -- generate trace output or not.
+  constant Generate_Trace  : boolean                      := false;
+  constant wordPower       : integer                      := 5;
+  -- during simulation, set this to '0' to get matching trace.txt 
+  constant DontCareValue   : std_logic                    := 'X';
+  -- Clock frequency in MHz.
+  constant ZPU_Frequency   : std_logic_vector(7 downto 0) := x"64";
+  -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
+  constant maxAddrBitIncIO : integer                      := 15;
+  constant maxAddrBitBRAM  : integer                      := 14;
+
+  -- start byte address of stack. 
+  -- point to top of RAM - 2*words
+  constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) :=
+    conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1);
+
 end zpu_config;
diff --git a/zpu/hdl/zpu4/core/zpu_core.vhd b/zpu/hdl/zpu4/core/zpu_core.vhd
index 69da686..ff9449f 100644
--- a/zpu/hdl/zpu4/core/zpu_core.vhd
+++ b/zpu/hdl/zpu4/core/zpu_core.vhd
@@ -33,8 +33,8 @@
 -- are those of the authors and should not be interpreted as representing
 -- official policies, either expressed or implied, of the ZPU Project.
 
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
+library ieee;
+use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
 library work;
@@ -58,899 +58,957 @@ use work.zpupkg.all;
 --                 write request
 -- break - set to '1' when CPU hits break instruction
 -- interrupt - set to '1' until interrupts are cleared by CPU. 
- 
+
 
 
 
 entity zpu_core is
-    Port ( clk : in std_logic;
-	 		  areset : in std_logic;
-	 		  enable : in std_logic; 
-	 		  in_mem_busy : in std_logic; 
-	 		  mem_read : in std_logic_vector(wordSize-1 downto 0);
-	 		  mem_write : out std_logic_vector(wordSize-1 downto 0);
-			  out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0);
-			  out_mem_writeEnable : out std_logic; 
-			  out_mem_readEnable : out std_logic;
-	 		  mem_writeMask: out std_logic_vector(wordBytes-1 downto 0);
-	 		  interrupt : in std_logic;
-	 		  break : out std_logic);
+  port (
+    clk                 : in  std_logic;
+    areset              : in  std_logic;
+    enable              : in  std_logic;
+    in_mem_busy         : in  std_logic;
+    mem_read            : in  std_logic_vector(wordSize-1 downto 0);
+    mem_write           : out std_logic_vector(wordSize-1 downto 0);
+    out_mem_addr        : out std_logic_vector(maxAddrBitIncIO downto 0);
+    out_mem_writeEnable : out std_logic;
+    out_mem_readEnable  : out std_logic;
+    mem_writeMask       : out std_logic_vector(wordBytes-1 downto 0);
+    interrupt           : in  std_logic;
+    break               : out std_logic
+    );
 end zpu_core;
 
 architecture behave of zpu_core is
 
-type InsnType is 
-(
-State_AddTop,
-State_Dup,
-State_DupStackB,
-State_Pop,
-State_Popdown,
-State_Add,
-State_Or,
-State_And,
-State_Store,
-State_AddSP,
-State_Shift,
-State_Nop,
-State_Im,
-State_LoadSP,
-State_StoreSP,
-State_Emulate,
-State_Load,
-State_PushPC,
-State_PushSP,
-State_PopPC,
-State_PopPCRel,
-State_Not,
-State_Flip,
-State_PopSP,
-State_Neqbranch,
-State_Eq,
-State_Loadb,
-State_Mult,
-State_Lessthan,
-State_Lessthanorequal,
-State_Ulessthanorequal,
-State_Ulessthan,
-State_Pushspadd,
-State_Call,
-State_Callpcrel,
-State_Sub,
-State_Break,
-State_Storeb,
-State_InsnFetch
-);
-
-type StateType is 
-(
-State_Load2,
-State_Popped,
-State_LoadSP2,
-State_LoadSP3,
-State_AddSP2,
-State_Fetch,
-State_Execute,
-State_Decode,
-State_Decode2,
-State_Resync,
-
-State_StoreSP2,
-State_Resync2,
-State_Resync3,
-State_Loadb2,
-State_Storeb2,
-State_Mult2,
-State_Mult3,
-State_Mult5,
-State_Mult4,
-State_BinaryOpResult2,
-State_BinaryOpResult,
-State_Idle,
-State_Interrupt
-); 
-
-
-signal	pc				: unsigned(maxAddrBitIncIO downto 0);
-signal	sp				: unsigned(maxAddrBitIncIO downto minAddrBit);
-signal	incSp			: unsigned(maxAddrBitIncIO downto minAddrBit);
-signal	incIncSp			: unsigned(maxAddrBitIncIO downto minAddrBit);
-signal	decSp			: unsigned(maxAddrBitIncIO downto minAddrBit);
-signal  stackA   		: unsigned(wordSize-1 downto 0);
-signal  binaryOpResult		: unsigned(wordSize-1 downto 0);
-signal  binaryOpResult2		: unsigned(wordSize-1 downto 0);
-signal  multResult2  		: unsigned(wordSize-1 downto 0);
-signal  multResult3  		: unsigned(wordSize-1 downto 0);
-signal  multResult  		: unsigned(wordSize-1 downto 0);
-signal  multA 		: unsigned(wordSize-1 downto 0);
-signal  multB  		: unsigned(wordSize-1 downto 0);
-signal  stackB  		: unsigned(wordSize-1 downto 0);
-signal	idim_flag			: std_logic;
-signal	busy 				: std_logic;
-signal mem_writeEnable : std_logic; 
-signal mem_readEnable : std_logic;
-signal mem_addr : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
-signal mem_delayAddr : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
-signal mem_delayReadEnable : std_logic;
-
-signal inInterrupt: std_logic;
-
-signal decodeWord : std_logic_vector(wordSize-1 downto 0);
-
-
-signal state : StateType;
-signal insn : InsnType;
-type InsnArray is array(0 to wordBytes-1) of InsnType;
-signal decodedOpcode : InsnArray;
-
-type OpcodeArray is array(0 to wordBytes-1) of std_logic_vector(7 downto 0);
-
-signal opcode : OpcodeArray;
-
-
-
-
-signal	begin_inst			: std_logic;
-signal trace_opcode		: std_logic_vector(7 downto 0);
-signal	trace_pc				: std_logic_vector(maxAddrBitIncIO downto 0);
-signal	trace_sp				: std_logic_vector(maxAddrBitIncIO downto minAddrBit);
-signal	trace_topOfStack				: std_logic_vector(wordSize-1 downto 0);
-signal	trace_topOfStackB				: std_logic_vector(wordSize-1 downto 0);
+  type InsnType is (
+    State_AddTop,
+    State_Dup,
+    State_DupStackB,
+    State_Pop,
+    State_Popdown,
+    State_Add,
+    State_Or,
+    State_And,
+    State_Store,
+    State_AddSP,
+    State_Shift,
+    State_Nop,
+    State_Im,
+    State_LoadSP,
+    State_StoreSP,
+    State_Emulate,
+    State_Load,
+    State_PushPC,
+    State_PushSP,
+    State_PopPC,
+    State_PopPCRel,
+    State_Not,
+    State_Flip,
+    State_PopSP,
+    State_Neqbranch,
+    State_Eq,
+    State_Loadb,
+    State_Mult,
+    State_Lessthan,
+    State_Lessthanorequal,
+    State_Ulessthanorequal,
+    State_Ulessthan,
+    State_Pushspadd,
+    State_Call,
+    State_Callpcrel,
+    State_Sub,
+    State_Break,
+    State_Storeb,
+    State_InsnFetch
+    );
+
+  type StateType is (
+    State_Load2,
+    State_Popped,
+    State_LoadSP2,
+    State_LoadSP3,
+    State_AddSP2,
+    State_Fetch,
+    State_Execute,
+    State_Decode,
+    State_Decode2,
+    State_Resync,
+
+    State_StoreSP2,
+    State_Resync2,
+    State_Resync3,
+    State_Loadb2,
+    State_Storeb2,
+    State_Mult2,
+    State_Mult3,
+    State_Mult5,
+    State_Mult4,
+    State_BinaryOpResult2,
+    State_BinaryOpResult,
+    State_Idle,
+    State_Interrupt
+    ); 
+
+
+  signal pc                  : unsigned(maxAddrBitIncIO downto 0);
+  signal sp                  : unsigned(maxAddrBitIncIO downto minAddrBit);
+  signal incSp               : unsigned(maxAddrBitIncIO downto minAddrBit);
+  signal incIncSp            : unsigned(maxAddrBitIncIO downto minAddrBit);
+  signal decSp               : unsigned(maxAddrBitIncIO downto minAddrBit);
+  signal stackA              : unsigned(wordSize-1 downto 0);
+  signal binaryOpResult      : unsigned(wordSize-1 downto 0);
+  signal binaryOpResult2     : unsigned(wordSize-1 downto 0);
+  signal multResult2         : unsigned(wordSize-1 downto 0);
+  signal multResult3         : unsigned(wordSize-1 downto 0);
+  signal multResult          : unsigned(wordSize-1 downto 0);
+  signal multA               : unsigned(wordSize-1 downto 0);
+  signal multB               : unsigned(wordSize-1 downto 0);
+  signal stackB              : unsigned(wordSize-1 downto 0);
+  signal idim_flag           : std_logic;
+  signal busy                : std_logic;
+  signal mem_writeEnable     : std_logic;
+  signal mem_readEnable      : std_logic;
+  signal mem_addr            : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+  signal mem_delayAddr       : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+  signal mem_delayReadEnable : std_logic;
+  --
+  signal inInterrupt         : std_logic;
+  --
+  signal decodeWord          : std_logic_vector(wordSize-1 downto 0);
+  --
+  --
+  signal state               : StateType;
+  signal insn                : InsnType;
+  type   InsnArray is array(0 to wordBytes-1) of InsnType;
+  signal decodedOpcode       : InsnArray;
+  --
+  type   OpcodeArray is array(0 to wordBytes-1) of std_logic_vector(7 downto 0);
+  --
+  signal opcode              : OpcodeArray;
+
+
+
+
+  signal begin_inst        : std_logic;
+  signal trace_opcode      : std_logic_vector(7 downto 0);
+  signal trace_pc          : std_logic_vector(maxAddrBitIncIO downto 0);
+  signal trace_sp          : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+  signal trace_topOfStack  : std_logic_vector(wordSize-1 downto 0);
+  signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0);
 
 -- state machine.
 
 begin
 
 
-	traceFileGenerate:
-   if Generate_Trace generate
-	trace_file: trace port map (
-       	clk => clk,
-       	begin_inst => begin_inst,
-       	pc => trace_pc,
-		opcode => trace_opcode,
-		sp => trace_sp,
-		memA => trace_topOfStack,
-		memB => trace_topOfStackB,
-		busy => busy,
-		intsp => (others => 'U')
-        );
-	end generate;
-
-	
-	-- the memory subsystem will tell us one cycle later whether or 
-	-- not it is busy
-	out_mem_writeEnable <= mem_writeEnable;
-	out_mem_readEnable <= mem_readEnable;
-	out_mem_addr(maxAddrBitIncIO downto minAddrBit) <= mem_addr;
-	out_mem_addr(minAddrBit-1 downto 0) <= (others => '0');
-	
-	incSp <= sp + 1;
-	incIncSp <= sp + 2;
-	decSp <= sp - 1;
-	
-
-	opcodeControl:
-	process(clk, areset)
-		variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0);
-		variable spOffset : unsigned(4 downto 0);
-		variable tSpOffset : unsigned(4 downto 0);
-		variable nextPC : unsigned(maxAddrBitIncIO downto 0);
-		variable tNextState : InsnType;
-		variable tDecodedOpcode : InsnArray;
-		variable tMultResult : unsigned(wordSize*2-1 downto 0);
-	begin
-		if areset = '1' then
-			state <= State_Idle;
-			break <= '0';
-			sp <= unsigned(spStart(maxAddrBitIncIO downto minAddrBit));
-			 
-			pc <= (others => '0');
-			idim_flag <= '0';
-			begin_inst <= '0';
-			inInterrupt <= '0';
-			mem_writeEnable <= '0'; 
-			mem_readEnable <= '0';
-			multA <= (others => '0');
-			multB <= (others => '0');
-			mem_writeMask <= (others => '1');
-		elsif (clk'event and clk = '1') then
-			-- we must multiply unconditionally to get pipelined multiplication
-        	tMultResult := multA * multB;
-    		multResult3 <= multResult2;
-    		multResult2 <= multResult;
-    		multResult <= tMultResult(wordSize-1 downto 0);
-    		
-    		
-			binaryOpResult2 <= binaryOpResult; -- pipeline a bit.
-
-
-			multA <= (others => DontCareValue);
-			multB <= (others => DontCareValue);
-			
-			
-			mem_addr <= (others => DontCareValue);
-			mem_readEnable <='0';
-			mem_writeEnable <='0';
-			mem_write <= (others => DontCareValue);
-
-			if (mem_writeEnable = '1') and (mem_readEnable = '1') then
-				report "read/write collision" severity failure;
-			end if;
-	
-
-
-			
-			spOffset(4):=not opcode(to_integer(pc(byteBits-1 downto 0)))(4);
-			spOffset(3 downto 0):=unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(3 downto 0));
-			nextPC := pc + 1;
-
-			-- prepare trace snapshot
-			trace_opcode <= opcode(to_integer(pc(byteBits-1 downto 0)));
-			trace_pc <= std_logic_vector(pc);
-			trace_sp <= std_logic_vector(sp);
-			trace_topOfStack <= std_logic_vector(stackA);
-			trace_topOfStackB <= std_logic_vector(stackB);
-			begin_inst <= '0';
-
-			if (interrupt='0') then
-				-- Interrupt ended, we can serve ISR again
-				inInterrupt <= '0';
-			end if;
-
-			case state is
-				when State_Idle =>
-					if enable='1' then
-						state <= State_Resync; 
-					end if;
-				-- Initial state of ZPU, fetch top of stack + first instruction 
-				when State_Resync =>
-					if in_mem_busy='0' then
-						mem_addr <= std_logic_vector(sp);
-						mem_readEnable <= '1';
-						state <= State_Resync2;
-					end if;
-				when State_Resync2 =>
-					if in_mem_busy='0' then
-						stackA <= unsigned(mem_read);
-						mem_addr <= std_logic_vector(incSp);
-						mem_readEnable <= '1';
-						state <= State_Resync3;
-					end if;
-				when State_Resync3 =>
-					if in_mem_busy='0' then
-						stackB <= unsigned(mem_read);
-						mem_addr <= std_logic_vector(pc(maxAddrBitIncIO downto minAddrBit));
-						mem_readEnable <= '1';
-						state <= State_Decode;
-					end if;
-				when State_Decode =>
-					if in_mem_busy='0' then
-						decodeWord <= mem_read;
-						state <= State_Decode2;
-						-- Do not recurse into ISR while interrupt line is active
-						if interrupt='1' and inInterrupt='0' and idim_flag='0' then
-							-- We got an interrupt, execute interrupt instead of next instruction
-							inInterrupt <= '1';
-							sp <= decSp;
-							mem_writeEnable <= '1';
-							mem_addr <= std_logic_vector(incSp);
-							mem_write <= std_logic_vector(stackB);
-							stackA <= (others => DontCareValue);
-							stackA(maxAddrBitIncIO downto 0) <= pc;
-							stackB <= stackA;
-							pc <= to_unsigned(32, maxAddrBitIncIO+1);
-							state <= State_Interrupt;
-						end if;
-					end if;
-				when State_Interrupt =>
-					if in_mem_busy='0' then
-						mem_addr <= std_logic_vector(pc(maxAddrBitIncIO downto minAddrBit));
-						mem_readEnable <= '1';
-						state <= State_Decode;
-						report "ZPU jumped to interrupt!" severity note;
-					end if;
-				when State_Decode2 =>
-					-- decode 4 instructions in parallel
-					for i in 0 to wordBytes-1 loop
-						tOpcode := decodeWord((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8);
-
-						tSpOffset(4):=not tOpcode(4);
-						tSpOffset(3 downto 0):=unsigned(tOpcode(3 downto 0));
-
-						opcode(i) <= tOpcode;
-						if (tOpcode(7 downto 7)=OpCode_Im) then
-							tNextState:=State_Im;
-						elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then
-							if tSpOffset = 0 then
-								tNextState := State_Pop;
-							elsif tSpOffset=1 then
-								tNextState := State_PopDown;
-							else
-								tNextState :=State_StoreSP;
-							end if;
-						elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then
-							if tSpOffset = 0 then
-								tNextState :=State_Dup;
-							elsif tSpOffset = 1 then
-								tNextState :=State_DupStackB;
-							else
-								tNextState :=State_LoadSP;
-							end if;
-						elsif (tOpcode(7 downto 5)=OpCode_Emulate) then
-							tNextState :=State_Emulate;
-							if tOpcode(5 downto 0)=OpCode_Neqbranch then
-								tNextState :=State_Neqbranch;
-							elsif tOpcode(5 downto 0)=OpCode_Eq then
-								tNextState :=State_Eq;
-							elsif tOpcode(5 downto 0)=OpCode_Lessthan then
-								tNextState :=State_Lessthan;
-							elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then
-								--tNextState :=State_Lessthanorequal;
-							elsif tOpcode(5 downto 0)=OpCode_Ulessthan then
-								tNextState :=State_Ulessthan;
-							elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then
-								--tNextState :=State_Ulessthanorequal;
-							elsif tOpcode(5 downto 0)=OpCode_Loadb then
-								tNextState :=State_Loadb;
-							elsif tOpcode(5 downto 0)=OpCode_Mult then
-								tNextState :=State_Mult;
-							elsif tOpcode(5 downto 0)=OpCode_Storeb then
-								tNextState :=State_Storeb;
-							elsif tOpcode(5 downto 0)=OpCode_Pushspadd then
-								tNextState :=State_Pushspadd;
-							elsif tOpcode(5 downto 0)=OpCode_Callpcrel then
-								tNextState :=State_Callpcrel;
-							elsif tOpcode(5 downto 0)=OpCode_Call then
-								--tNextState :=State_Call;
-							elsif tOpcode(5 downto 0)=OpCode_Sub then
-								tNextState :=State_Sub;
-							elsif tOpcode(5 downto 0)=OpCode_PopPCRel then
-								--tNextState :=State_PopPCRel;
-							end if;								
-						elsif (tOpcode(7 downto 4)=OpCode_AddSP) then
-							if tSpOffset = 0 then
-								tNextState := State_Shift;
-							elsif tSpOffset = 1 then
-								tNextState := State_AddTop;
-							else
-								tNextState :=State_AddSP;
-							end if;
-						else
-							case tOpcode(3 downto 0) is
-								when OpCode_Nop =>
-									tNextState :=State_Nop;
-								when OpCode_PushSP =>
-									tNextState :=State_PushSP;
-								when OpCode_PopPC =>
-									tNextState :=State_PopPC;
-								when OpCode_Add =>
-									tNextState :=State_Add;
-								when OpCode_Or =>
-									tNextState :=State_Or;
-								when OpCode_And =>
-									tNextState :=State_And;
-								when OpCode_Load =>
-									tNextState :=State_Load;
-								when OpCode_Not =>
-									tNextState :=State_Not;
-								when OpCode_Flip =>
-									tNextState :=State_Flip;
-								when OpCode_Store =>
-									tNextState :=State_Store;
-								when OpCode_PopSP =>
-									tNextState :=State_PopSP;
-								when others =>
-									tNextState := State_Break;
-
-							end case;
-						end if;
-						tDecodedOpcode(i) := tNextState;
-						
-					end loop;
-					
-					insn <= tDecodedOpcode(to_integer(pc(byteBits-1 downto 0)));
-					
-					-- once we wrap, we need to fetch
-					tDecodedOpcode(0) := State_InsnFetch;
-
-					decodedOpcode <= tDecodedOpcode;
-					state <= State_Execute;
-						
-
-
-					-- Each instruction must:
-					--
-					-- 1. set idim_flag
-					-- 2. increase pc if applicable
-					-- 3. set next state if appliable
-					-- 4. do it's operation
-					 
-				when State_Execute =>
-					insn <= decodedOpcode(to_integer(nextPC(byteBits-1 downto 0)));
-									
-					case insn is
-						when State_InsnFetch =>
-							state <= State_Fetch;
-						when State_Im =>
-							if in_mem_busy='0' then
-								begin_inst <= '1';
-								idim_flag <= '1';
-								pc <= pc + 1;
-								
-								if idim_flag='1' then 
-									stackA(wordSize-1 downto 7) <= stackA(wordSize-8 downto 0);
-									stackA(6 downto 0) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(6 downto 0));
-								else
-									mem_writeEnable <= '1';
-									mem_addr <= std_logic_vector(incSp);
-									mem_write <= std_logic_vector(stackB);
-									stackB <= stackA;
-									sp <= decSp;
-									for i in wordSize-1 downto 7 loop
-										stackA(i) <= opcode(to_integer(pc(byteBits-1 downto 0)))(6);
-									end loop;
-									stackA(6 downto 0) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(6 downto 0));
-								end if;
-							end if;
-						when State_StoreSP =>
-							if in_mem_busy='0' then
-								begin_inst <= '1';
-								idim_flag <= '0';
-								state <= State_StoreSP2;
-								
-								mem_writeEnable <= '1';
-								mem_addr <= std_logic_vector(sp+spOffset);
-								mem_write <= std_logic_vector(stackA);
-								stackA <= stackB;
-								sp <= incSp;
-							end if;
-
-					
-						when State_LoadSP =>
-							if in_mem_busy='0' then
-								begin_inst <= '1';
-								idim_flag <= '0';
-								state <= State_LoadSP2;
-		
-								sp <= decSp;
-								mem_writeEnable <= '1';
-								mem_addr <= std_logic_vector(incSp);
-								mem_write <= std_logic_vector(stackB);
-							end if;
-						when State_Emulate =>
-							if in_mem_busy='0' then
-								begin_inst <= '1';
-								idim_flag <= '0';
-								sp <= decSp;
-								mem_writeEnable <= '1';
-								mem_addr <= std_logic_vector(incSp);
-								mem_write <= std_logic_vector(stackB);
-								stackA <= (others => DontCareValue);
-								stackA(maxAddrBitIncIO downto 0) <= pc + 1;
-								stackB <= stackA;
-								
-								-- The emulate address is:
-								--        98 7654 3210
-								-- 0000 00aa aaa0 0000
-								pc <= (others => '0');
-								pc(9 downto 5) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(4 downto 0));
-								state <= State_Fetch;
-							end if;
-						when State_Callpcrel =>
-							if in_mem_busy='0' then
-								begin_inst <= '1';
-								idim_flag <= '0';
-								stackA <= (others => DontCareValue);
-								stackA(maxAddrBitIncIO downto 0) <= pc + 1;
-								
-								pc <= pc + stackA(maxAddrBitIncIO downto 0);
-								state <= State_Fetch;
-							end if;
-						when State_Call =>
-							if in_mem_busy='0' then
-								begin_inst <= '1';
-								idim_flag <= '0';
-								stackA <= (others => DontCareValue);
-								stackA(maxAddrBitIncIO downto 0) <= pc + 1;
-								pc <= stackA(maxAddrBitIncIO downto 0);
-								state <= State_Fetch;
-							end if;
-						when State_AddSP =>
-							if in_mem_busy='0' then
-								begin_inst <= '1';
-								idim_flag <= '0';
-								state <= State_AddSP2;
-								
-								mem_readEnable <= '1';
-								mem_addr <= std_logic_vector(sp+spOffset);
-							end if;
-						when State_PushSP =>
-							if in_mem_busy='0' then
-								begin_inst <= '1';
-								idim_flag <= '0';
-								pc <= pc + 1;
-								
-								sp <= decSp;
-								stackA <= (others => '0');
-								stackA(maxAddrBitIncIO downto minAddrBit) <= sp;
-								stackB <= stackA;
-								mem_writeEnable <= '1';
-								mem_addr <= std_logic_vector(incSp);
-								mem_write <= std_logic_vector(stackB);
-							end if;
-						when State_PopPC =>
-							if in_mem_busy='0' then
-								begin_inst <= '1';
-								idim_flag <= '0';
-								pc <= stackA(maxAddrBitIncIO downto 0);
-								sp <= incSp;
-								
-								mem_writeEnable <= '1';
-								mem_addr <= std_logic_vector(incSp);
-								mem_write <= std_logic_vector(stackB);
-								state <= State_Resync;
-							end if;
-						when State_PopPCRel =>
-							if in_mem_busy='0' then
-								begin_inst <= '1';
-								idim_flag <= '0';
-								pc <= stackA(maxAddrBitIncIO downto 0) + pc;
-								sp <= incSp;
-								
-								mem_writeEnable <= '1';
-								mem_addr <= std_logic_vector(incSp);
-								mem_write <= std_logic_vector(stackB);
-								state <= State_Resync;
-							end if;
-						when State_Add =>
-							if in_mem_busy='0' then
-								begin_inst <= '1';
-								idim_flag <= '0';
-								stackA <= stackA + stackB;
-								
-								mem_readEnable <= '1';
-								mem_addr <= std_logic_vector(incIncSp);
-								sp <= incSp;
-								state <= State_Popped;
-							end if;
-						when State_Sub =>
-							if in_mem_busy='0' then
-								begin_inst <= '1';
-								idim_flag <= '0';
-								binaryOpResult <= stackB - stackA;
-								state <= State_BinaryOpResult;
-							end if;
-						when State_Pop =>
-							if in_mem_busy='0' then
-								begin_inst <= '1';
-								idim_flag <= '0';
-								mem_addr <= std_logic_vector(incIncSp);
-								mem_readEnable <= '1';
-								sp <= incSp;
-								stackA <= stackB;
-								state <= State_Popped;						
-							end if;
-						when State_PopDown =>
-							if in_mem_busy='0' then
-								-- PopDown leaves top of stack unchanged
-								begin_inst <= '1';
-								idim_flag <= '0';
-								mem_addr <= std_logic_vector(incIncSp);
-								mem_readEnable <= '1';
-								sp <= incSp;
-								state <= State_Popped;						
-							end if;
-						when State_Or =>
-							if in_mem_busy='0' then
-								begin_inst <= '1';
-								idim_flag <= '0';
-								stackA <= stackA or stackB;
-								mem_readEnable <= '1';
-								mem_addr <= std_logic_vector(incIncSp);
-								sp <= incSp;
-								state <= State_Popped;
-							end if;
-						when State_And =>
-							if in_mem_busy='0' then
-								begin_inst <= '1';
-								idim_flag <= '0';
-		
-								stackA <= stackA and stackB;
-								mem_readEnable <= '1';
-								mem_addr <= std_logic_vector(incIncSp);
-								sp <= incSp;
-								state <= State_Popped;
-							end if;
-						when State_Eq =>
-							if in_mem_busy='0' then
-								begin_inst <= '1';
-								idim_flag <= '0';
-		
-			            		binaryOpResult <= (others => '0');
-			                	if (stackA=stackB) then
-			                		binaryOpResult(0) <= '1';
-			                	end if;
-								state <= State_BinaryOpResult;
-							end if;
-		                when State_Ulessthan =>
-							if in_mem_busy='0' then
-								begin_inst <= '1';
-								idim_flag <= '0';
-		
-			            		binaryOpResult <= (others => '0');
-			                	if (stackA
-							if in_mem_busy='0' then
-								begin_inst <= '1';
-								idim_flag <= '0';
-		
-			            		binaryOpResult <= (others => '0');
-			                	if (stackA<=stackB) then
-			                		binaryOpResult(0) <= '1';
-			                	end if;
-								state <= State_BinaryOpResult;
-							end if;
-		                when State_Lessthan =>
-							if in_mem_busy='0' then
-								begin_inst <= '1';
-								idim_flag <= '0';
-		
-			            		binaryOpResult <= (others => '0');
-			                	if (signed(stackA)
-							if in_mem_busy='0' then
-								begin_inst <= '1';
-								idim_flag <= '0';
-		
-			            		binaryOpResult <= (others => '0');
-			                	if (signed(stackA)<=signed(stackB)) then
-			                		binaryOpResult(0) <= '1';
-			                	end if;
-								state <= State_BinaryOpResult;
-							end if;
-						when State_Load =>
-							if in_mem_busy='0' then
-								begin_inst <= '1';
-								idim_flag <= '0';
-								state <= State_Load2;
-								
-								mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit));
-								mem_readEnable <= '1';
-							end if;
-
-						when State_Dup =>
-							if in_mem_busy='0' then
-								begin_inst <= '1';
-								idim_flag <= '0';
-								pc <= pc + 1; 
-								
-								sp <= decSp;
-								stackB <= stackA;
-								mem_write <= std_logic_vector(stackB);
-								mem_addr <= std_logic_vector(incSp);
-								mem_writeEnable <= '1';
-							end if;
-						when State_DupStackB =>
-							if in_mem_busy='0' then
-								begin_inst <= '1';
-								idim_flag <= '0';
-								pc <= pc + 1; 
-								
-								sp <= decSp;
-								stackA <= stackB;
-								stackB <= stackA;
-								mem_write <= std_logic_vector(stackB);
-								mem_addr <= std_logic_vector(incSp);
-								mem_writeEnable <= '1';
-							end if;
-						when State_Store =>
-							if in_mem_busy='0' then
-								begin_inst <= '1';
-								idim_flag <= '0';
-								pc <= pc + 1;
-								mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit));
-								mem_write <= std_logic_vector(stackB);
-								mem_writeEnable <= '1';
-								sp <= incIncSp;
-								state <= State_Resync;
-							end if;
-						when State_PopSP =>
-							if in_mem_busy='0' then
-								begin_inst <= '1';
-								idim_flag <= '0';
-								pc <= pc + 1;
-								
-								mem_write <= std_logic_vector(stackB);
-								mem_addr <= std_logic_vector(incSp);
-								mem_writeEnable <= '1';
-								sp <= stackA(maxAddrBitIncIO downto minAddrBit);
-								state <= State_Resync;
-							end if;
-						when State_Nop =>	
-							begin_inst <= '1';
-							idim_flag <= '0';
-							pc <= pc + 1;
-						when State_Not =>
-							begin_inst <= '1';
-							idim_flag <= '0';
-							pc <= pc + 1; 
-							
-							stackA <= not stackA;
-						when State_Flip =>
-							begin_inst <= '1';
-							idim_flag <= '0';
-							pc <= pc + 1; 
-							
-							for i in 0 to wordSize-1 loop
-								stackA(i) <= stackA(wordSize-1-i);
-				  			end loop;
-						when State_AddTop =>
-							begin_inst <= '1';
-							idim_flag <= '0';
-							pc <= pc + 1; 
-							
-							stackA <= stackA + stackB;
-						when State_Shift =>
-							begin_inst <= '1';
-							idim_flag <= '0';
-							pc <= pc + 1; 
-							
-							stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0);
-							stackA(0) <= '0';
-						when State_Pushspadd =>
-							begin_inst <= '1';
-							idim_flag <= '0';
-							pc <= pc + 1; 
-							
-							stackA <= (others => '0');
-							stackA(maxAddrBitIncIO downto minAddrBit) <= stackA(maxAddrBitIncIO-minAddrBit downto 0)+sp;
-						when State_Neqbranch =>
-							-- branches are almost always taken as they form loops
-							begin_inst <= '1';
-							idim_flag <= '0';
-							sp <= incIncSp;
-		                	if (stackB/=0) then
-		                		pc <= stackA(maxAddrBitIncIO downto 0) + pc;
-		                	else
-		                		pc <= pc + 1;
-		                	end if;		
-		                	-- need to fetch stack again.				
-							state <= State_Resync;
-		                when State_Mult =>
-							begin_inst <= '1';
-							idim_flag <= '0';
-		
-							multA <= stackA;
-							multB <= stackB;
-							state <= State_Mult2;
-						when State_Break =>
-							report "Break instruction encountered" severity failure;
-							break <= '1';
-
-						when State_Loadb =>
-							if in_mem_busy='0' then
-								begin_inst <= '1';
-								idim_flag <= '0';
-								state <= State_Loadb2;
-								
-								mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit));
-								mem_readEnable <= '1';
-							end if;
-						when State_Storeb =>
-							if in_mem_busy='0' then
-								begin_inst <= '1';
-								idim_flag <= '0';
-								state <= State_Storeb2;
-								
-								mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit));
-								mem_readEnable <= '1';
-							end if;
-				
-						when others =>
-							sp <= (others => DontCareValue);
-							report "Illegal instruction" severity failure;
-							break <= '1';
-					end case;
-
-
-				when State_StoreSP2 =>
-					if in_mem_busy='0' then
-						mem_addr <= std_logic_vector(incSp);
-						mem_readEnable <= '1';
-						state <= State_Popped;
-					end if;
-				when State_LoadSP2 =>
-					if in_mem_busy='0' then
-						state <= State_LoadSP3;
-						mem_readEnable <= '1';
-						mem_addr <= std_logic_vector(sp+spOffset+1);
-					end if;
-				when State_LoadSP3 =>
-					if in_mem_busy='0' then
-						pc <= pc + 1;
-						state <= State_Execute;
-						stackB <= stackA;
-						stackA <= unsigned(mem_read);
-					end if;
-				when State_AddSP2 =>
-					if in_mem_busy='0' then
-						pc <= pc + 1;
-						state <= State_Execute;
-						stackA <= stackA + unsigned(mem_read);
-					end if;
-				when State_Load2 =>
-					if in_mem_busy='0' then
-						stackA <= unsigned(mem_read);
-						pc <= pc + 1;
-						state <= State_Execute;
-					end if;
-				when State_Loadb2 =>
-					if in_mem_busy='0' then
-						stackA <= (others => '0');
-						stackA(7 downto 0) <= unsigned(mem_read(((wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8));
-						pc <= pc + 1;
-						state <= State_Execute;
-					end if;
-				when State_Storeb2 =>
-					if in_mem_busy='0' then
-						mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit));
-						mem_write <= mem_read;
-						mem_write(((wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8) <= std_logic_vector(stackB(7 downto 0));
-						mem_writeEnable <= '1';
-						pc <= pc + 1;
-						sp <= incIncSp;
-						state <= State_Resync;
-					end if;
-				when State_Fetch =>
-					if in_mem_busy='0' then
-						mem_addr <= std_logic_vector(pc(maxAddrBitIncIO downto minAddrBit));
-						mem_readEnable <= '1';
-						state <= State_Decode;
-					end if;
-                when State_Mult2 =>
-					state <= State_Mult3;
-                when State_Mult3 =>
-					state <= State_Mult4;
-                when State_Mult4 =>
-					state <= State_Mult5;
-                when State_Mult5 =>
-					if in_mem_busy='0' then
-	            		stackA <= multResult3;
-						mem_readEnable <= '1';
-						mem_addr <= std_logic_vector(incIncSp);
-						sp <= incSp;
-						state <= State_Popped;
-					end if;
-				when State_BinaryOpResult =>	
-					state <= State_BinaryOpResult2;
-				when State_BinaryOpResult2 =>
-					mem_readEnable <= '1';
-					mem_addr <= std_logic_vector(incIncSp);
-					sp <= incSp;
-					stackA <= binaryOpResult2;
-					state <= State_Popped;
-				when State_Popped =>
-					if in_mem_busy='0' then
-						pc <= pc + 1;
-						stackB <= unsigned(mem_read);
-						state <= State_Execute;
-					end if;
-				when others =>	
-					sp <= (others => DontCareValue);
-					report "Illegal state" severity failure;
-					break <= '1';
-			end case;
-		end if;
-	end process;
+  traceFileGenerate :
+  if Generate_Trace generate
+    trace_file : trace port map (
+      clk        => clk,
+      begin_inst => begin_inst,
+      pc         => trace_pc,
+      opcode     => trace_opcode,
+      sp         => trace_sp,
+      memA       => trace_topOfStack,
+      memB       => trace_topOfStackB,
+      busy       => busy,
+      intsp      => (others => 'U')
+      );
+  end generate;
+
+
+  -- the memory subsystem will tell us one cycle later whether or 
+  -- not it is busy
+  out_mem_writeEnable                             <= mem_writeEnable;
+  out_mem_readEnable                              <= mem_readEnable;
+  out_mem_addr(maxAddrBitIncIO downto minAddrBit) <= mem_addr;
+  out_mem_addr(minAddrBit-1 downto 0)             <= (others => '0');
+
+  incSp    <= sp + 1;
+  incIncSp <= sp + 2;
+  decSp    <= sp - 1;
+
+
+  opcodeControl : process(clk, areset)
+    variable tOpcode        : std_logic_vector(OpCode_Size-1 downto 0);
+    variable spOffset       : unsigned(4 downto 0);
+    variable tSpOffset      : unsigned(4 downto 0);
+    variable nextPC         : unsigned(maxAddrBitIncIO downto 0);
+    variable tNextState     : InsnType;
+    variable tDecodedOpcode : InsnArray;
+    variable tMultResult    : unsigned(wordSize*2-1 downto 0);
+  begin
+    if areset = '1' then
+      state <= State_Idle;
+      break <= '0';
+      sp    <= unsigned(spStart(maxAddrBitIncIO downto minAddrBit));
+
+      pc              <= (others => '0');
+      idim_flag       <= '0';
+      begin_inst      <= '0';
+      inInterrupt     <= '0';
+      mem_writeEnable <= '0';
+      mem_readEnable  <= '0';
+      multA           <= (others => '0');
+      multB           <= (others => '0');
+      mem_writeMask   <= (others => '1');
+    elsif (clk'event and clk = '1') then
+      -- we must multiply unconditionally to get pipelined multiplication
+      tMultResult := multA * multB;
+      multResult3 <= multResult2;
+      multResult2 <= multResult;
+      multResult  <= tMultResult(wordSize-1 downto 0);
+
+
+      binaryOpResult2 <= binaryOpResult;  -- pipeline a bit.
+
+
+      multA <= (others => DontCareValue);
+      multB <= (others => DontCareValue);
+
+
+      mem_addr        <= (others => DontCareValue);
+      mem_readEnable  <= '0';
+      mem_writeEnable <= '0';
+      mem_write       <= (others => DontCareValue);
+
+      if (mem_writeEnable = '1') and (mem_readEnable = '1') then
+        report "read/write collision" severity failure;
+      end if;
+
+
+
+
+      spOffset(4)          := not opcode(to_integer(pc(byteBits-1 downto 0)))(4);
+      spOffset(3 downto 0) := unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(3 downto 0));
+      nextPC               := pc + 1;
+
+      -- prepare trace snapshot
+      trace_opcode      <= opcode(to_integer(pc(byteBits-1 downto 0)));
+      trace_pc          <= std_logic_vector(pc);
+      trace_sp          <= std_logic_vector(sp);
+      trace_topOfStack  <= std_logic_vector(stackA);
+      trace_topOfStackB <= std_logic_vector(stackB);
+      begin_inst        <= '0';
+
+      if (interrupt = '0') then
+        -- Interrupt ended, we can serve ISR again
+        inInterrupt <= '0';
+      end if;
+
+      case state is
+
+        when State_Idle =>
+          if enable = '1' then
+            state <= State_Resync;
+          end if;
+          -- Initial state of ZPU, fetch top of stack + first instruction 
+
+        when State_Resync =>
+          if in_mem_busy = '0' then
+            mem_addr       <= std_logic_vector(sp);
+            mem_readEnable <= '1';
+            state          <= State_Resync2;
+          end if;
+
+        when State_Resync2 =>
+          if in_mem_busy = '0' then
+            stackA         <= unsigned(mem_read);
+            mem_addr       <= std_logic_vector(incSp);
+            mem_readEnable <= '1';
+            state          <= State_Resync3;
+          end if;
+
+        when State_Resync3 =>
+          if in_mem_busy = '0' then
+            stackB         <= unsigned(mem_read);
+            mem_addr       <= std_logic_vector(pc(maxAddrBitIncIO downto minAddrBit));
+            mem_readEnable <= '1';
+            state          <= State_Decode;
+          end if;
+
+        when State_Decode =>
+          if in_mem_busy = '0' then
+            decodeWord <= mem_read;
+            state      <= State_Decode2;
+            -- Do not recurse into ISR while interrupt line is active
+            if interrupt = '1' and inInterrupt = '0' and idim_flag = '0' then
+              -- We got an interrupt, execute interrupt instead of next instruction
+              inInterrupt                      <= '1';
+              sp                               <= decSp;
+              mem_writeEnable                  <= '1';
+              mem_addr                         <= std_logic_vector(incSp);
+              mem_write                        <= std_logic_vector(stackB);
+              stackA                           <= (others => DontCareValue);
+              stackA(maxAddrBitIncIO downto 0) <= pc;
+              stackB                           <= stackA;
+              pc                               <= to_unsigned(32, maxAddrBitIncIO+1);
+              state                            <= State_Interrupt;
+            end if; -- interrupt
+          end if; -- in_mem_busy
+
+        when State_Interrupt =>
+          if in_mem_busy = '0' then
+            mem_addr       <= std_logic_vector(pc(maxAddrBitIncIO downto minAddrBit));
+            mem_readEnable <= '1';
+            state          <= State_Decode;
+            report "ZPU jumped to interrupt!" severity note;
+          end if;
+
+        when State_Decode2 =>
+          -- decode 4 instructions in parallel
+          for i in 0 to wordBytes-1 loop
+            tOpcode := decodeWord((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8);
+
+            tSpOffset(4)          := not tOpcode(4);
+            tSpOffset(3 downto 0) := unsigned(tOpcode(3 downto 0));
+
+            opcode(i) <= tOpcode;
+            if (tOpcode(7 downto 7) = OpCode_Im) then
+              tNextState := State_Im;
+            elsif (tOpcode(7 downto 5) = OpCode_StoreSP) then
+              if tSpOffset = 0 then
+                tNextState := State_Pop;
+              elsif tSpOffset = 1 then
+                tNextState := State_PopDown;
+              else
+                tNextState := State_StoreSP;
+              end if;
+            elsif (tOpcode(7 downto 5) = OpCode_LoadSP) then
+              if tSpOffset = 0 then
+                tNextState := State_Dup;
+              elsif tSpOffset = 1 then
+                tNextState := State_DupStackB;
+              else
+                tNextState := State_LoadSP;
+              end if;
+            elsif (tOpcode(7 downto 5) = OpCode_Emulate) then
+              tNextState := State_Emulate;
+              if tOpcode(5 downto 0) = OpCode_Neqbranch then
+                tNextState := State_Neqbranch;
+              elsif tOpcode(5 downto 0) = OpCode_Eq then
+                tNextState := State_Eq;
+              elsif tOpcode(5 downto 0) = OpCode_Lessthan then
+                tNextState := State_Lessthan;
+              elsif tOpcode(5 downto 0) = OpCode_Lessthanorequal then
+                --tNextState :=State_Lessthanorequal;
+              elsif tOpcode(5 downto 0) = OpCode_Ulessthan then
+                tNextState := State_Ulessthan;
+              elsif tOpcode(5 downto 0) = OpCode_Ulessthanorequal then
+                --tNextState :=State_Ulessthanorequal;
+              elsif tOpcode(5 downto 0) = OpCode_Loadb then
+                tNextState := State_Loadb;
+              elsif tOpcode(5 downto 0) = OpCode_Mult then
+                tNextState := State_Mult;
+              elsif tOpcode(5 downto 0) = OpCode_Storeb then
+                tNextState := State_Storeb;
+              elsif tOpcode(5 downto 0) = OpCode_Pushspadd then
+                tNextState := State_Pushspadd;
+              elsif tOpcode(5 downto 0) = OpCode_Callpcrel then
+                tNextState := State_Callpcrel;
+              elsif tOpcode(5 downto 0) = OpCode_Call then
+                                        --tNextState :=State_Call;
+              elsif tOpcode(5 downto 0) = OpCode_Sub then
+                tNextState := State_Sub;
+              elsif tOpcode(5 downto 0) = OpCode_PopPCRel then
+                                        --tNextState :=State_PopPCRel;
+              end if;
+            elsif (tOpcode(7 downto 4) = OpCode_AddSP) then
+              if tSpOffset = 0 then
+                tNextState := State_Shift;
+              elsif tSpOffset = 1 then
+                tNextState := State_AddTop;
+              else
+                tNextState := State_AddSP;
+              end if;
+            else
+              case tOpcode(3 downto 0) is
+                when OpCode_Nop =>
+                  tNextState := State_Nop;
+                when OpCode_PushSP =>
+                  tNextState := State_PushSP;
+                when OpCode_PopPC =>
+                  tNextState := State_PopPC;
+                when OpCode_Add =>
+                  tNextState := State_Add;
+                when OpCode_Or =>
+                  tNextState := State_Or;
+                when OpCode_And =>
+                  tNextState := State_And;
+                when OpCode_Load =>
+                  tNextState := State_Load;
+                when OpCode_Not =>
+                  tNextState := State_Not;
+                when OpCode_Flip =>
+                  tNextState := State_Flip;
+                when OpCode_Store =>
+                  tNextState := State_Store;
+                when OpCode_PopSP =>
+                  tNextState := State_PopSP;
+                when others =>
+                  tNextState := State_Break;
+
+              end case; -- tOpcode(3 downto 0)
+            end if; -- tOpcode
+            tDecodedOpcode(i) := tNextState;
+            
+          end loop; -- 0 to wordBytes-1
+
+          insn <= tDecodedOpcode(to_integer(pc(byteBits-1 downto 0)));
+
+          -- once we wrap, we need to fetch
+          tDecodedOpcode(0) := State_InsnFetch;
+
+          decodedOpcode <= tDecodedOpcode;
+          state         <= State_Execute;
+
+
+
+          -- Each instruction must:
+          --
+          -- 1. set idim_flag
+          -- 2. increase pc if applicable
+          -- 3. set next state if appliable
+          -- 4. do it's operation
+          
+        when State_Execute =>
+          insn <= decodedOpcode(to_integer(nextPC(byteBits-1 downto 0)));
+
+          case insn is
+
+            when State_InsnFetch =>
+              state <= State_Fetch;
+
+            when State_Im =>
+              if in_mem_busy = '0' then
+                begin_inst <= '1';
+                idim_flag  <= '1';
+                pc         <= pc + 1;
+
+                if idim_flag = '1' then
+                  stackA(wordSize-1 downto 7) <= stackA(wordSize-8 downto 0);
+                  stackA(6 downto 0)          <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(6 downto 0));
+                else
+                  mem_writeEnable <= '1';
+                  mem_addr        <= std_logic_vector(incSp);
+                  mem_write       <= std_logic_vector(stackB);
+                  stackB          <= stackA;
+                  sp              <= decSp;
+                  for i in wordSize-1 downto 7 loop
+                    stackA(i) <= opcode(to_integer(pc(byteBits-1 downto 0)))(6);
+                  end loop;
+                  stackA(6 downto 0) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(6 downto 0));
+                end if; -- idim_flag
+              end if; -- in_mem_busy
+
+            when State_StoreSP =>
+              if in_mem_busy = '0' then
+                begin_inst <= '1';
+                idim_flag  <= '0';
+                state      <= State_StoreSP2;
+
+                mem_writeEnable <= '1';
+                mem_addr        <= std_logic_vector(sp+spOffset);
+                mem_write       <= std_logic_vector(stackA);
+                stackA          <= stackB;
+                sp              <= incSp;
+              end if;
+
+              
+            when State_LoadSP =>
+              if in_mem_busy = '0' then
+                begin_inst <= '1';
+                idim_flag  <= '0';
+                state      <= State_LoadSP2;
+
+                sp              <= decSp;
+                mem_writeEnable <= '1';
+                mem_addr        <= std_logic_vector(incSp);
+                mem_write       <= std_logic_vector(stackB);
+              end if;
+
+            when State_Emulate =>
+              if in_mem_busy = '0' then
+                begin_inst                       <= '1';
+                idim_flag                        <= '0';
+                sp                               <= decSp;
+                mem_writeEnable                  <= '1';
+                mem_addr                         <= std_logic_vector(incSp);
+                mem_write                        <= std_logic_vector(stackB);
+                stackA                           <= (others => DontCareValue);
+                stackA(maxAddrBitIncIO downto 0) <= pc + 1;
+                stackB                           <= stackA;
+
+                -- The emulate address is:
+                --        98 7654 3210
+                -- 0000 00aa aaa0 0000
+                pc             <= (others => '0');
+                pc(9 downto 5) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(4 downto 0));
+                state          <= State_Fetch;
+              end if; -- in_mem_busy
+
+            when State_Callpcrel =>
+              if in_mem_busy = '0' then
+                begin_inst                       <= '1';
+                idim_flag                        <= '0';
+                stackA                           <= (others => DontCareValue);
+                stackA(maxAddrBitIncIO downto 0) <= pc + 1;
+
+                pc    <= pc + stackA(maxAddrBitIncIO downto 0);
+                state <= State_Fetch;
+              end if;
+
+            when State_Call =>
+              if in_mem_busy = '0' then
+                begin_inst                       <= '1';
+                idim_flag                        <= '0';
+                stackA                           <= (others => DontCareValue);
+                stackA(maxAddrBitIncIO downto 0) <= pc + 1;
+                pc                               <= stackA(maxAddrBitIncIO downto 0);
+                state                            <= State_Fetch;
+              end if;
+
+            when State_AddSP =>
+              if in_mem_busy = '0' then
+                begin_inst <= '1';
+                idim_flag  <= '0';
+                state      <= State_AddSP2;
+
+                mem_readEnable <= '1';
+                mem_addr       <= std_logic_vector(sp+spOffset);
+              end if;
+
+            when State_PushSP =>
+              if in_mem_busy = '0' then
+                begin_inst <= '1';
+                idim_flag  <= '0';
+                pc         <= pc + 1;
+
+                sp                                        <= decSp;
+                stackA                                    <= (others => '0');
+                stackA(maxAddrBitIncIO downto minAddrBit) <= sp;
+                stackB                                    <= stackA;
+                mem_writeEnable                           <= '1';
+                mem_addr                                  <= std_logic_vector(incSp);
+                mem_write                                 <= std_logic_vector(stackB);
+              end if;
+
+            when State_PopPC =>
+              if in_mem_busy = '0' then
+                begin_inst <= '1';
+                idim_flag  <= '0';
+                pc         <= stackA(maxAddrBitIncIO downto 0);
+                sp         <= incSp;
+
+                mem_writeEnable <= '1';
+                mem_addr        <= std_logic_vector(incSp);
+                mem_write       <= std_logic_vector(stackB);
+                state           <= State_Resync;
+              end if;
+
+            when State_PopPCRel =>
+              if in_mem_busy = '0' then
+                begin_inst <= '1';
+                idim_flag  <= '0';
+                pc         <= stackA(maxAddrBitIncIO downto 0) + pc;
+                sp         <= incSp;
+
+                mem_writeEnable <= '1';
+                mem_addr        <= std_logic_vector(incSp);
+                mem_write       <= std_logic_vector(stackB);
+                state           <= State_Resync;
+              end if;
+
+            when State_Add =>
+              if in_mem_busy = '0' then
+                begin_inst <= '1';
+                idim_flag  <= '0';
+                stackA     <= stackA + stackB;
+
+                mem_readEnable <= '1';
+                mem_addr       <= std_logic_vector(incIncSp);
+                sp             <= incSp;
+                state          <= State_Popped;
+              end if;
+
+            when State_Sub =>
+              if in_mem_busy = '0' then
+                begin_inst     <= '1';
+                idim_flag      <= '0';
+                binaryOpResult <= stackB - stackA;
+                state          <= State_BinaryOpResult;
+              end if;
+
+            when State_Pop =>
+              if in_mem_busy = '0' then
+                begin_inst     <= '1';
+                idim_flag      <= '0';
+                mem_addr       <= std_logic_vector(incIncSp);
+                mem_readEnable <= '1';
+                sp             <= incSp;
+                stackA         <= stackB;
+                state          <= State_Popped;
+              end if;
+
+            when State_PopDown =>
+              if in_mem_busy = '0' then
+                                        -- PopDown leaves top of stack unchanged
+                begin_inst     <= '1';
+                idim_flag      <= '0';
+                mem_addr       <= std_logic_vector(incIncSp);
+                mem_readEnable <= '1';
+                sp             <= incSp;
+                state          <= State_Popped;
+              end if;
+
+            when State_Or =>
+              if in_mem_busy = '0' then
+                begin_inst     <= '1';
+                idim_flag      <= '0';
+                stackA         <= stackA or stackB;
+                mem_readEnable <= '1';
+                mem_addr       <= std_logic_vector(incIncSp);
+                sp             <= incSp;
+                state          <= State_Popped;
+              end if;
+
+            when State_And =>
+              if in_mem_busy = '0' then
+                begin_inst <= '1';
+                idim_flag  <= '0';
+
+                stackA         <= stackA and stackB;
+                mem_readEnable <= '1';
+                mem_addr       <= std_logic_vector(incIncSp);
+                sp             <= incSp;
+                state          <= State_Popped;
+              end if;
+
+            when State_Eq =>
+              if in_mem_busy = '0' then
+                begin_inst <= '1';
+                idim_flag  <= '0';
+
+                binaryOpResult <= (others => '0');
+                if (stackA = stackB) then
+                  binaryOpResult(0) <= '1';
+                end if;
+                state <= State_BinaryOpResult;
+              end if;
+
+            when State_Ulessthan =>
+              if in_mem_busy = '0' then
+                begin_inst <= '1';
+                idim_flag  <= '0';
+
+                binaryOpResult <= (others => '0');
+                if (stackA < stackB) then
+                  binaryOpResult(0) <= '1';
+                end if;
+                state <= State_BinaryOpResult;
+              end if;
+
+            when State_Ulessthanorequal =>
+              if in_mem_busy = '0' then
+                begin_inst <= '1';
+                idim_flag  <= '0';
+
+                binaryOpResult <= (others => '0');
+                if (stackA     <= stackB) then
+                  binaryOpResult(0) <= '1';
+                end if;
+                state <= State_BinaryOpResult;
+              end if;
+
+            when State_Lessthan =>
+              if in_mem_busy = '0' then
+                begin_inst <= '1';
+                idim_flag  <= '0';
+
+                binaryOpResult <= (others => '0');
+                if (signed(stackA) < signed(stackB)) then
+                  binaryOpResult(0) <= '1';
+                end if;
+                state <= State_BinaryOpResult;
+              end if;
+
+            when State_Lessthanorequal =>
+              if in_mem_busy = '0' then
+                begin_inst <= '1';
+                idim_flag  <= '0';
+
+                binaryOpResult     <= (others => '0');
+                if (signed(stackA) <= signed(stackB)) then
+                  binaryOpResult(0) <= '1';
+                end if;
+                state <= State_BinaryOpResult;
+              end if;
+
+            when State_Load =>
+              if in_mem_busy = '0' then
+                begin_inst <= '1';
+                idim_flag  <= '0';
+                state      <= State_Load2;
+
+                mem_addr       <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit));
+                mem_readEnable <= '1';
+              end if;
+
+            when State_Dup =>
+              if in_mem_busy = '0' then
+                begin_inst <= '1';
+                idim_flag  <= '0';
+                pc         <= pc + 1;
+
+                sp              <= decSp;
+                stackB          <= stackA;
+                mem_write       <= std_logic_vector(stackB);
+                mem_addr        <= std_logic_vector(incSp);
+                mem_writeEnable <= '1';
+              end if;
+
+            when State_DupStackB =>
+              if in_mem_busy = '0' then
+                begin_inst <= '1';
+                idim_flag  <= '0';
+                pc         <= pc + 1;
+
+                sp              <= decSp;
+                stackA          <= stackB;
+                stackB          <= stackA;
+                mem_write       <= std_logic_vector(stackB);
+                mem_addr        <= std_logic_vector(incSp);
+                mem_writeEnable <= '1';
+              end if;
+
+            when State_Store =>
+              if in_mem_busy = '0' then
+                begin_inst      <= '1';
+                idim_flag       <= '0';
+                pc              <= pc + 1;
+                mem_addr        <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit));
+                mem_write       <= std_logic_vector(stackB);
+                mem_writeEnable <= '1';
+                sp              <= incIncSp;
+                state           <= State_Resync;
+              end if;
+
+            when State_PopSP =>
+              if in_mem_busy = '0' then
+                begin_inst <= '1';
+                idim_flag  <= '0';
+                pc         <= pc + 1;
+
+                mem_write       <= std_logic_vector(stackB);
+                mem_addr        <= std_logic_vector(incSp);
+                mem_writeEnable <= '1';
+                sp              <= stackA(maxAddrBitIncIO downto minAddrBit);
+                state           <= State_Resync;
+              end if;
+
+            when State_Nop =>
+              begin_inst <= '1';
+              idim_flag  <= '0';
+              pc         <= pc + 1;
+
+            when State_Not =>
+              begin_inst <= '1';
+              idim_flag  <= '0';
+              pc         <= pc + 1;
+
+              stackA <= not stackA;
+
+            when State_Flip =>
+              begin_inst <= '1';
+              idim_flag  <= '0';
+              pc         <= pc + 1;
+
+              for i in 0 to wordSize-1 loop
+                stackA(i) <= stackA(wordSize-1-i);
+              end loop;
+
+            when State_AddTop =>
+              begin_inst <= '1';
+              idim_flag  <= '0';
+              pc         <= pc + 1;
+
+              stackA <= stackA + stackB;
+
+            when State_Shift =>
+              begin_inst <= '1';
+              idim_flag  <= '0';
+              pc         <= pc + 1;
+
+              stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0);
+              stackA(0)                   <= '0';
+
+            when State_Pushspadd =>
+              begin_inst <= '1';
+              idim_flag  <= '0';
+              pc         <= pc + 1;
+
+              stackA                                    <= (others => '0');
+              stackA(maxAddrBitIncIO downto minAddrBit) <= stackA(maxAddrBitIncIO-minAddrBit downto 0)+sp;
+
+            when State_Neqbranch =>
+              -- branches are almost always taken as they form loops
+              begin_inst <= '1';
+              idim_flag  <= '0';
+              sp         <= incIncSp;
+              if (stackB /= 0) then
+                pc <= stackA(maxAddrBitIncIO downto 0) + pc;
+              else
+                pc <= pc + 1;
+              end if;
+              -- need to fetch stack again.                           
+              state <= State_Resync;
+
+            when State_Mult =>
+              begin_inst <= '1';
+              idim_flag  <= '0';
+
+              multA <= stackA;
+              multB <= stackB;
+              state <= State_Mult2;
+
+            when State_Break =>
+              report "Break instruction encountered" severity failure;
+              break <= '1';
+
+            when State_Loadb =>
+              if in_mem_busy = '0' then
+                begin_inst <= '1';
+                idim_flag  <= '0';
+                state      <= State_Loadb2;
+
+                mem_addr       <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit));
+                mem_readEnable <= '1';
+              end if;
+
+            when State_Storeb =>
+              if in_mem_busy = '0' then
+                begin_inst <= '1';
+                idim_flag  <= '0';
+                state      <= State_Storeb2;
+
+                mem_addr       <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit));
+                mem_readEnable <= '1';
+              end if;
+              
+            when others =>
+              sp    <= (others => DontCareValue);
+              report "Illegal instruction" severity failure;
+              break <= '1';
+
+          end case; -- insn/State_Execute
+
+
+        when State_StoreSP2 =>
+          if in_mem_busy = '0' then
+            mem_addr       <= std_logic_vector(incSp);
+            mem_readEnable <= '1';
+            state          <= State_Popped;
+          end if;
+
+        when State_LoadSP2 =>
+          if in_mem_busy = '0' then
+            state          <= State_LoadSP3;
+            mem_readEnable <= '1';
+            mem_addr       <= std_logic_vector(sp+spOffset+1);
+          end if;
+
+        when State_LoadSP3 =>
+          if in_mem_busy = '0' then
+            pc     <= pc + 1;
+            state  <= State_Execute;
+            stackB <= stackA;
+            stackA <= unsigned(mem_read);
+          end if;
+
+        when State_AddSP2 =>
+          if in_mem_busy = '0' then
+            pc     <= pc + 1;
+            state  <= State_Execute;
+            stackA <= stackA + unsigned(mem_read);
+          end if;
+
+        when State_Load2 =>
+          if in_mem_busy = '0' then
+            stackA <= unsigned(mem_read);
+            pc     <= pc + 1;
+            state  <= State_Execute;
+          end if;
+
+        when State_Loadb2 =>
+          if in_mem_busy = '0' then
+            stackA             <= (others => '0');
+            stackA(7 downto 0) <= unsigned(mem_read(((wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8));
+            pc                 <= pc + 1;
+            state              <= State_Execute;
+          end if;
+
+        when State_Storeb2 =>
+          if in_mem_busy = '0' then
+            mem_addr                                                                                                                              <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit));
+            mem_write                                                                                                                             <= mem_read;
+            mem_write(((wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8) <= std_logic_vector(stackB(7 downto 0));
+            mem_writeEnable                                                                                                                       <= '1';
+            pc                                                                                                                                    <= pc + 1;
+            sp                                                                                                                                    <= incIncSp;
+            state                                                                                                                                 <= State_Resync;
+          end if;
+
+        when State_Fetch =>
+          if in_mem_busy = '0' then
+            mem_addr       <= std_logic_vector(pc(maxAddrBitIncIO downto minAddrBit));
+            mem_readEnable <= '1';
+            state          <= State_Decode;
+          end if;
+
+        when State_Mult2 =>
+          state <= State_Mult3;
+
+        when State_Mult3 =>
+          state <= State_Mult4;
+
+        when State_Mult4 =>
+          state <= State_Mult5;
+
+        when State_Mult5 =>
+          if in_mem_busy = '0' then
+            stackA         <= multResult3;
+            mem_readEnable <= '1';
+            mem_addr       <= std_logic_vector(incIncSp);
+            sp             <= incSp;
+            state          <= State_Popped;
+          end if;
+
+        when State_BinaryOpResult =>
+          state <= State_BinaryOpResult2;
+
+        when State_BinaryOpResult2 =>
+          mem_readEnable <= '1';
+          mem_addr       <= std_logic_vector(incIncSp);
+          sp             <= incSp;
+          stackA         <= binaryOpResult2;
+          state          <= State_Popped;
+
+        when State_Popped =>
+          if in_mem_busy = '0' then
+            pc     <= pc + 1;
+            stackB <= unsigned(mem_read);
+            state  <= State_Execute;
+          end if;
+
+        when others =>
+          sp    <= (others => DontCareValue);
+          report "Illegal state" severity failure;
+          break <= '1';
+
+      end case; -- state
+    end if; -- clk'event
+  end process;
 
 
 
diff --git a/zpu/hdl/zpu4/core/zpu_core_small.vhd b/zpu/hdl/zpu4/core/zpu_core_small.vhd
index 681fb09..1df9546 100644
--- a/zpu/hdl/zpu4/core/zpu_core_small.vhd
+++ b/zpu/hdl/zpu4/core/zpu_core_small.vhd
@@ -32,8 +32,8 @@
 -- are those of the authors and should not be interpreted as representing
 -- official policies, either expressed or implied, of the ZPU Project.
 
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
+library ieee;
+use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
 library work;
@@ -42,531 +42,560 @@ use work.zpupkg.all;
 
 
 entity zpu_core is
-    Port ( clk : in std_logic;
-    		  -- asynchronous reset signal
-	 		  areset : in std_logic;
-	 		  -- this particular implementation of the ZPU does not
-	 		  -- have a clocked enable signal
-	 		  enable : in std_logic; 
-	 		  in_mem_busy : in std_logic; 
-	 		  mem_read : in std_logic_vector(wordSize-1 downto 0);
-	 		  mem_write : out std_logic_vector(wordSize-1 downto 0);			  
-	 		  out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0);
-			  out_mem_writeEnable : out std_logic; 
-			  out_mem_readEnable : out std_logic;
-			  -- this implementation of the ZPU *always* reads and writes entire
-			  -- 32 bit words, so mem_writeMask is tied to (others => '1').
-	 		  mem_writeMask: out std_logic_vector(wordBytes-1 downto 0);
-	 		  -- Set to one to jump to interrupt vector
-	 		  -- The ZPU will communicate with the hardware that caused the
-	 		  -- interrupt via memory mapped IO or the interrupt flag can
-	 		  -- be cleared automatically
-	 		  interrupt : in std_logic;
-	 		  -- Signal that the break instruction is executed, normally only used
-	 		  -- in simulation to stop simulation
-	 		  break : out std_logic);
+  port ( 
+    clk                 : in std_logic;
+    -- asynchronous reset signal
+    areset              : in std_logic;
+    -- this particular implementation of the ZPU does not
+    -- have a clocked enable signal
+    enable              : in  std_logic;
+    in_mem_busy         : in  std_logic;
+    mem_read            : in  std_logic_vector(wordSize-1 downto 0);
+    mem_write           : out std_logic_vector(wordSize-1 downto 0);
+    out_mem_addr        : out std_logic_vector(maxAddrBitIncIO downto 0);
+    out_mem_writeEnable : out std_logic;
+    out_mem_readEnable  : out std_logic;
+    -- this implementation of the ZPU *always* reads and writes entire
+    -- 32 bit words, so mem_writeMask is tied to (others => '1').
+    mem_writeMask       : out std_logic_vector(wordBytes-1 downto 0);
+    -- Set to one to jump to interrupt vector
+    -- The ZPU will communicate with the hardware that caused the
+    -- interrupt via memory mapped IO or the interrupt flag can
+    -- be cleared automatically
+    interrupt           : in  std_logic;
+    -- Signal that the break instruction is executed, normally only used
+    -- in simulation to stop simulation
+    break               : out std_logic
+    );
 end zpu_core;
 
-architecture behave of zpu_core is
 
-signal		readIO : std_logic;
 
-
-
-signal memAWriteEnable : std_logic;
-signal memAAddr : unsigned(maxAddrBit downto minAddrBit);
-signal memAWrite : unsigned(wordSize-1 downto 0);
-signal memARead : unsigned(wordSize-1 downto 0);
-signal memBWriteEnable : std_logic;
-signal memBAddr : unsigned(maxAddrBit downto minAddrBit);
-signal memBWrite : unsigned(wordSize-1 downto 0);
-signal memBRead : unsigned(wordSize-1 downto 0);
-
-
-
-signal	pc				: unsigned(maxAddrBit downto 0);
-signal	sp				: unsigned(maxAddrBit downto minAddrBit);
-
--- this signal is set upon executing an IM instruction
--- the subsequence IM instruction will then behave differently.
--- all other instructions will clear the idim_flag.
--- this yields highly compact immediate instructions.
-signal	idim_flag			: std_logic;
-
-signal	busy 				: std_logic;
-
-signal	begin_inst			: std_logic;
-
-
-
-signal trace_opcode		: std_logic_vector(7 downto 0);
-signal	trace_pc				: std_logic_vector(maxAddrBitIncIO downto 0);
-signal	trace_sp				: std_logic_vector(maxAddrBitIncIO downto minAddrBit);
-signal	trace_topOfStack				: std_logic_vector(wordSize-1 downto 0);
-signal	trace_topOfStackB				: std_logic_vector(wordSize-1 downto 0);
-
--- state machine.
-type State_Type is
-(
-State_Fetch,
-State_WriteIODone,
-State_Execute,
-State_StoreToStack,
-State_Add,
-State_Or,
-State_And,
-State_Store,
-State_ReadIO,
-State_WriteIO,
-State_Load,
-State_FetchNext,
-State_AddSP,
-State_ReadIODone,
-State_Decode,
-State_Resync,
-State_Interrupt
-
-);
-
-type DecodedOpcodeType is
-(
-Decoded_Nop,
-Decoded_Im,
-Decoded_ImShift,
-Decoded_LoadSP,
-Decoded_StoreSP	,
-Decoded_AddSP,
-Decoded_Emulate,
-Decoded_Break,
-Decoded_PushSP,
-Decoded_PopPC,
-Decoded_Add,
-Decoded_Or,
-Decoded_And,
-Decoded_Load,
-Decoded_Not,
-Decoded_Flip,
-Decoded_Store,
-Decoded_PopSP,
-Decoded_Interrupt
-);
-
-
-
-signal sampledOpcode : std_logic_vector(OpCode_Size-1 downto 0);
-signal opcode : std_logic_vector(OpCode_Size-1 downto 0);
-
-signal decodedOpcode : DecodedOpcodeType;
-signal sampledDecodedOpcode : DecodedOpcodeType;
-
-
-signal state : State_Type;
-
-subtype AddrBitBRAM_range is natural range maxAddrBitBRAM downto minAddrBit;
-signal memAAddr_stdlogic  : std_logic_vector(AddrBitBRAM_range);
-signal memAWrite_stdlogic : std_logic_vector(memAWrite'range);
-signal memARead_stdlogic  : std_logic_vector(memARead'range);
-signal memBAddr_stdlogic  : std_logic_vector(AddrBitBRAM_range);
-signal memBWrite_stdlogic : std_logic_vector(memBWrite'range);
-signal memBRead_stdlogic  : std_logic_vector(memBRead'range);
-
-subtype index is integer range 0 to 3;
-
-signal tOpcode_sel : index;
-
-
-signal inInterrupt : std_logic;
+architecture behave of zpu_core is
+
+  signal memAWriteEnable : std_logic;
+  signal memAAddr        : unsigned(maxAddrBit downto minAddrBit);
+  signal memAWrite       : unsigned(wordSize-1 downto 0);
+  signal memARead        : unsigned(wordSize-1 downto 0);
+  signal memBWriteEnable : std_logic;
+  signal memBAddr        : unsigned(maxAddrBit downto minAddrBit);
+  signal memBWrite       : unsigned(wordSize-1 downto 0);
+  signal memBRead        : unsigned(wordSize-1 downto 0);
+
+
+
+  signal pc : unsigned(maxAddrBit downto 0);
+  signal sp : unsigned(maxAddrBit downto minAddrBit);
+
+  -- this signal is set upon executing an IM instruction
+  -- the subsequence IM instruction will then behave differently.
+  -- all other instructions will clear the idim_flag.
+  -- this yields highly compact immediate instructions.
+  signal idim_flag  : std_logic;
+  --
+  signal busy       : std_logic;
+  --
+  signal begin_inst : std_logic;
+
+
+  signal trace_opcode      : std_logic_vector(7 downto 0);
+  signal trace_pc          : std_logic_vector(maxAddrBitIncIO downto 0);
+  signal trace_sp          : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+  signal trace_topOfStack  : std_logic_vector(wordSize-1 downto 0);
+  signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0);
+
+  -- state machine.
+  type State_Type is (
+    State_Fetch,
+    State_WriteIODone,
+    State_Execute,
+    State_StoreToStack,
+    State_Add,
+    State_Or,
+    State_And,
+    State_Store,
+    State_ReadIO,
+    State_WriteIO,
+    State_Load,
+    State_FetchNext,
+    State_AddSP,
+    State_ReadIODone,
+    State_Decode,
+    State_Resync,
+    State_Interrupt
+    );
+
+  type DecodedOpcodeType is (
+    Decoded_Nop,
+    Decoded_Im,
+    Decoded_ImShift,
+    Decoded_LoadSP,
+    Decoded_StoreSP ,
+    Decoded_AddSP,
+    Decoded_Emulate,
+    Decoded_Break,
+    Decoded_PushSP,
+    Decoded_PopPC,
+    Decoded_Add,
+    Decoded_Or,
+    Decoded_And,
+    Decoded_Load,
+    Decoded_Not,
+    Decoded_Flip,
+    Decoded_Store,
+    Decoded_PopSP,
+    Decoded_Interrupt
+    );
+
+
+
+  signal sampledOpcode        : std_logic_vector(OpCode_Size-1 downto 0);
+  signal opcode               : std_logic_vector(OpCode_Size-1 downto 0);
+  --
+  signal decodedOpcode        : DecodedOpcodeType;
+  signal sampledDecodedOpcode : DecodedOpcodeType;
+
+
+  signal  state              : State_Type;
+  --
+  subtype AddrBitBRAM_range is natural range maxAddrBitBRAM downto minAddrBit;
+  signal  memAAddr_stdlogic  : std_logic_vector(AddrBitBRAM_range);
+  signal  memAWrite_stdlogic : std_logic_vector(memAWrite'range);
+  signal  memARead_stdlogic  : std_logic_vector(memARead'range);
+  signal  memBAddr_stdlogic  : std_logic_vector(AddrBitBRAM_range);
+  signal  memBWrite_stdlogic : std_logic_vector(memBWrite'range);
+  signal  memBRead_stdlogic  : std_logic_vector(memBRead'range);
+  --
+  subtype index is integer range 0 to 3;
+  --
+  signal  tOpcode_sel        : index;
+  --
+  signal  inInterrupt        : std_logic;
 
 
 
 begin
 
-	-- generate a trace file.
-	-- 
-	-- This is only used in simulation to see what instructions are
-	-- executed. 
-	--
-	-- a quick & dirty regression test is then to commit trace files
-	-- to CVS and compare the latest trace file against the last known
-	-- good trace file
-	traceFileGenerate:
-   if Generate_Trace generate
-	trace_file: trace port map (
-       	clk => clk,
-       	begin_inst => begin_inst,
-       	pc => trace_pc,
-		opcode => trace_opcode,
-		sp => trace_sp,
-		memA => trace_topOfStack,
-		memB => trace_topOfStackB,
-		busy => busy,
-		intsp => (others => 'U')
-        );
-	end generate;
-
-
-
-    -- mem_writeMask is not used in this design, tie it to 1
-    mem_writeMask <= (others => '1');
-
-
-
-	memAAddr_stdlogic  <= std_logic_vector(memAAddr(AddrBitBRAM_range));
-	memAWrite_stdlogic <= std_logic_vector(memAWrite);
-	memBAddr_stdlogic  <= std_logic_vector(memBAddr(AddrBitBRAM_range));
-	memBWrite_stdlogic <= std_logic_vector(memBWrite);
-	
-	
-	-- dualport_ram must be defined by the application. 
-	-- 
-	-- How this can be implemented is highly dependent on the FPGA
-	-- and synthesis technology used. 
-	--
-	-- sometimes it can be instantiated as in the 
-	-- zpu/example/helloworld.vhd, using inference,
-	-- but oftentimes it must be instantiated directly
-	-- portmapping to part specific FPGA resources
-	-- 
-	--
-	-- DANGER!!!!!! If inference fails, then synthesis will try
-	-- to implement the memory using basic logic resources. This
-	-- will almost certainly cause the compiler to get "stuck"
-	-- since synthesising such a huge number of basic logic resources
-	-- will take more or less forever.
-	--
-	-- So: if your compiler gets "stuck" then inference is not
-	-- the way to go.
-	memory: dualport_ram port map (
-       	clk => clk,
-	memAWriteEnable => memAWriteEnable,
-	memAAddr => memAAddr_stdlogic,
-	memAWrite => memAWrite_stdlogic,
-	memARead => memARead_stdlogic,
-	memBWriteEnable => memBWriteEnable,
-	memBAddr => memBAddr_stdlogic,
-	memBWrite => memBWrite_stdlogic,
-	memBRead => memBRead_stdlogic
-        );
-	memARead <= unsigned(memARead_stdlogic);
-	memBRead <= unsigned(memBRead_stdlogic);
-
-
-
-	tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0));
-
-
-
-	-- move out calculation of the opcode to a seperate process
-	-- to make things a bit easier to read
-	decodeControl:
-	process(memBRead, pc,tOpcode_sel)
-		variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0);
-	begin
-
-        -- simplify opcode selection a bit so it passes more synthesizers
-        case (tOpcode_sel) is
-
-            when 0 => tOpcode := std_logic_vector(memBRead(31 downto 24));
-
-            when 1 => tOpcode := std_logic_vector(memBRead(23 downto 16));
-
-            when 2 => tOpcode := std_logic_vector(memBRead(15 downto 8));
-
-            when 3 => tOpcode := std_logic_vector(memBRead(7 downto 0));
-
-            when others => tOpcode := std_logic_vector(memBRead(7 downto 0));
-        end case;
-
-		sampledOpcode <= tOpcode;
-
-		if (tOpcode(7 downto 7)=OpCode_Im) then
-			sampledDecodedOpcode<=Decoded_Im;
-		elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then
-			sampledDecodedOpcode<=Decoded_StoreSP;
-		elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then
-			sampledDecodedOpcode<=Decoded_LoadSP;
-		elsif (tOpcode(7 downto 5)=OpCode_Emulate) then
-			sampledDecodedOpcode<=Decoded_Emulate;
-		elsif (tOpcode(7 downto 4)=OpCode_AddSP) then
-			sampledDecodedOpcode<=Decoded_AddSP;
-		else
-			case tOpcode(3 downto 0) is
-				when OpCode_Break =>
-					sampledDecodedOpcode<=Decoded_Break;
-				when OpCode_PushSP =>
-					sampledDecodedOpcode<=Decoded_PushSP;
-				when OpCode_PopPC =>
-					sampledDecodedOpcode<=Decoded_PopPC;
-				when OpCode_Add =>
-					sampledDecodedOpcode<=Decoded_Add;
-				when OpCode_Or =>
-					sampledDecodedOpcode<=Decoded_Or;
-				when OpCode_And =>
-					sampledDecodedOpcode<=Decoded_And;
-				when OpCode_Load =>
-					sampledDecodedOpcode<=Decoded_Load;
-				when OpCode_Not =>
-					sampledDecodedOpcode<=Decoded_Not;
-				when OpCode_Flip =>
-					sampledDecodedOpcode<=Decoded_Flip;
-				when OpCode_Store =>
-					sampledDecodedOpcode<=Decoded_Store;
-				when OpCode_PopSP =>
-					sampledDecodedOpcode<=Decoded_PopSP;
-				when others =>
-					sampledDecodedOpcode<=Decoded_Nop;
-			end case;
-		end if;
-	end process;
-
-
-	opcodeControl:
-	process(clk, areset)
-		variable spOffset : unsigned(4 downto 0);
-	begin
-		if areset = '1' then
-			state <= State_Resync;
-			break <= '0';
-			sp <= unsigned(spStart(maxAddrBit downto minAddrBit));
-			pc <= (others => '0');
-			idim_flag <= '0';
-			begin_inst <= '0';
-			memAAddr <= (others => '0');
-			memBAddr <= (others => '0');
-			memAWriteEnable <= '0';
-			memBWriteEnable <= '0';
-			out_mem_writeEnable <= '0';
-			out_mem_readEnable <= '0';
-			memAWrite <= (others => '0');
-			memBWrite <= (others => '0');
-			inInterrupt <= '0';
-		elsif (clk'event and clk = '1') then
-			memAWriteEnable <= '0';
-			memBWriteEnable <= '0';
-			-- This saves ca. 100 LUT's, by explicitly declaring that the
-            -- memAWrite can be left at whatever value if memAWriteEnable is
-			-- not set.
-			memAWrite <= (others => DontCareValue);
-			memBWrite <= (others => DontCareValue);
---			out_mem_addr <= (others => DontCareValue);
---			mem_write <= (others => DontCareValue);
-			spOffset := (others => DontCareValue);
-			memAAddr <= (others => DontCareValue);
-			memBAddr <= (others => DontCareValue);
-			
-			out_mem_writeEnable <= '0';
-			out_mem_readEnable <= '0';
-			begin_inst <= '0';
-			out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0));
-			mem_write <= std_logic_vector(memBRead);
-			
-			decodedOpcode <= sampledDecodedOpcode;
-			opcode <= sampledOpcode;
-			if interrupt='0' then
-				inInterrupt <= '0'; -- no longer in an interrupt
-			end if;
-
-			case state is
-				when State_Execute =>
-					state <= State_Fetch;
-					-- at this point:
-					-- memBRead contains opcode word
-					-- memARead contains top of stack
-					pc <= pc + 1;
-	
-					-- trace
-					begin_inst <= '1';
-					trace_pc <= (others => '0');
-					trace_pc(maxAddrBit downto 0) <= std_logic_vector(pc);
-					trace_opcode <= opcode;
-					trace_sp <= (others => '0');
-					trace_sp(maxAddrBit downto minAddrBit) <= std_logic_vector(sp);
-					trace_topOfStack <= std_logic_vector(memARead);
-					trace_topOfStackB <= std_logic_vector(memBRead);
-
-					-- during the next cycle we'll be reading the next opcode	
-					spOffset(4):=not opcode(4);
-					spOffset(3 downto 0) := unsigned(opcode(3 downto 0));
-	
-					idim_flag <= '0';
-					case decodedOpcode is
-						when Decoded_Interrupt =>
-							sp <= sp - 1;
-							memAAddr <= sp - 1;
-							memAWriteEnable <= '1';
-							memAWrite <= (others => DontCareValue);
-							memAWrite(maxAddrBit downto 0) <= pc;
-							pc <= to_unsigned(32, maxAddrBit+1); -- interrupt address
-			  				report "ZPU jumped to interrupt!" severity note;
-						when Decoded_Im =>
-							idim_flag <= '1';
-							memAWriteEnable <= '1';
-							if (idim_flag='0') then
-								sp <= sp - 1;
-								memAAddr <= sp-1;
-								for i in wordSize-1 downto 7 loop
-									memAWrite(i) <= opcode(6);
-								end loop;
-								memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0));
-							else
-								memAAddr <= sp;
-								memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0);
-								memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0));
-							end if;
-						when Decoded_StoreSP =>
-							memBWriteEnable <= '1';
-							memBAddr <= sp+spOffset;
-							memBWrite <= memARead;
-							sp <= sp + 1;
-							state <= State_Resync;
-						when Decoded_LoadSP =>
-							sp <= sp - 1;
-							memAAddr <= sp+spOffset;
-						when Decoded_Emulate =>
-							sp <= sp - 1;
-							memAWriteEnable <= '1';
-							memAAddr <= sp - 1;
-							memAWrite <= (others => DontCareValue);
-							memAWrite(maxAddrBit downto 0) <= pc + 1;
-							-- The emulate address is:
-							--        98 7654 3210
-							-- 0000 00aa aaa0 0000
-							pc <= (others => '0');
-							pc(9 downto 5) <= unsigned(opcode(4 downto 0));
-						when Decoded_AddSP =>
-							memAAddr <= sp;
-							memBAddr <= sp+spOffset;
-							state <= State_AddSP;
-						when Decoded_Break =>
-							report "Break instruction encountered" severity failure;
-							break <= '1';
-						when Decoded_PushSP =>
-							memAWriteEnable <= '1';
-							memAAddr <= sp - 1;
-							sp <= sp - 1;
-							memAWrite <= (others => DontCareValue);
-							memAWrite(maxAddrBit downto minAddrBit) <= sp;
-						when Decoded_PopPC =>
-							pc <= memARead(maxAddrBit downto 0);
-							sp <= sp + 1;
-							state <= State_Resync;
-						when Decoded_Add =>
-							sp <= sp + 1;
-							state <= State_Add;
-						when Decoded_Or =>
-							sp <= sp + 1;
-							state <= State_Or;
-						when Decoded_And =>
-							sp <= sp + 1;
-							state <= State_And;
-						when Decoded_Load =>
-							if (memARead(ioBit)='1') then
-								out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0));
-								out_mem_readEnable <= '1';
-								state <= State_ReadIO;
-							else 
-								memAAddr <= memARead(maxAddrBit downto minAddrBit);
-							end if;
-						when Decoded_Not =>
-							memAAddr <= sp(maxAddrBit downto minAddrBit);
-							memAWriteEnable <= '1';
-							memAWrite <= not memARead;
-						when Decoded_Flip =>
-							memAAddr <= sp(maxAddrBit downto minAddrBit);
-							memAWriteEnable <= '1';
-							for i in 0 to wordSize-1 loop
-								memAWrite(i) <= memARead(wordSize-1-i);
-				  			end loop;
-						when Decoded_Store =>
-							memBAddr <= sp + 1;
-							sp <= sp + 1;
-							if (memARead(ioBit)='1') then
-								state <= State_WriteIO;
-							else
-								state <= State_Store;
-							end if;
-						when Decoded_PopSP =>
-							sp <= memARead(maxAddrBit downto minAddrBit);
-							state <= State_Resync;
-						when Decoded_Nop =>	
-							memAAddr <= sp;
-						when others =>	
-							null; 
-					end case;
-				when State_ReadIO =>
-					memAAddr <= sp;
-					if (in_mem_busy = '0') then
-						state <= State_Fetch;
-						memAWriteEnable <= '1';
-						memAWrite <= unsigned(mem_read);
-					end if;
-				when State_WriteIO =>
-					sp <= sp + 1;
-					out_mem_writeEnable <= '1';
-					out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0));
-					mem_write <= std_logic_vector(memBRead);
-					state <= State_WriteIODone;
-				when State_WriteIODone =>
-					if (in_mem_busy = '0') then
-						state <= State_Resync;
-					end if;
-				when State_Fetch =>
-					-- We need to resync. During the *next* cycle
-					-- we'll fetch the opcode @ pc and thus it will
-					-- be available for State_Execute the cycle after
-					-- next
-					memBAddr <= pc(maxAddrBit downto minAddrBit);
-					state <= State_FetchNext;
-				when State_FetchNext =>
-					-- at this point memARead contains the value that is either
-					-- from the top of stack or should be copied to the top of the stack
-					memAWriteEnable <= '1';
-					memAWrite <= memARead; 
-					memAAddr <= sp;
-					memBAddr <= sp + 1;
-					state <= State_Decode;
-				when State_Decode =>
-					if interrupt='1' and inInterrupt='0' and idim_flag='0' then
-						-- We got an interrupt, execute interrupt instead of next instruction
-						inInterrupt <= '1';
-						decodedOpcode <= Decoded_Interrupt;
-					end if;
-					-- during the State_Execute cycle we'll be fetching SP+1
-					memAAddr <= sp;
-					memBAddr <= sp + 1;
-					state <= State_Execute;
-				when State_Store =>
-					sp <= sp + 1;
-					memAWriteEnable <= '1';
-					memAAddr <= memARead(maxAddrBit downto minAddrBit);
-					memAWrite <= memBRead;
-					state <= State_Resync;
-				when State_AddSP =>
-					state <= State_Add;
-				when State_Add =>
-					memAAddr <= sp;
-					memAWriteEnable <= '1';
-					memAWrite <= memARead + memBRead;
-					state <= State_Fetch;
-				when State_Or =>
-					memAAddr <= sp;
-					memAWriteEnable <= '1';
-					memAWrite <= memARead or memBRead;
-					state <= State_Fetch;
-				when State_Resync =>
-					memAAddr <= sp;
-					state <= State_Fetch;
-				when State_And =>
-					memAAddr <= sp;
-					memAWriteEnable <= '1';
-					memAWrite <= memARead and memBRead;
-					state <= State_Fetch;
-				when others =>
-					null;
-			end case;
-			
-		end if;
-	end process;
+  -- generate a trace file.
+  -- 
+  -- This is only used in simulation to see what instructions are
+  -- executed. 
+  --
+  -- a quick & dirty regression test is then to commit trace files
+  -- to CVS and compare the latest trace file against the last known
+  -- good trace file
+  traceFileGenerate : if Generate_Trace generate
+    trace_file : trace port map (
+      clk        => clk,
+      begin_inst => begin_inst,
+      pc         => trace_pc,
+      opcode     => trace_opcode,
+      sp         => trace_sp,
+      memA       => trace_topOfStack,
+      memB       => trace_topOfStackB,
+      busy       => busy,
+      intsp      => (others => 'U')
+      );
+  end generate;
+
+
+  -- mem_writeMask is not used in this design, tie it to 1
+  mem_writeMask <= (others => '1');
+
+
+
+  memAAddr_stdlogic  <= std_logic_vector(memAAddr(AddrBitBRAM_range));
+  memAWrite_stdlogic <= std_logic_vector(memAWrite);
+  memBAddr_stdlogic  <= std_logic_vector(memBAddr(AddrBitBRAM_range));
+  memBWrite_stdlogic <= std_logic_vector(memBWrite);
+
+
+  -- dualport_ram must be defined by the application. 
+  -- 
+  -- How this can be implemented is highly dependent on the FPGA
+  -- and synthesis technology used. 
+  --
+  -- sometimes it can be instantiated as in the 
+  -- zpu/example/helloworld.vhd, using inference,
+  -- but oftentimes it must be instantiated directly
+  -- portmapping to part specific FPGA resources
+  -- 
+  --
+  -- DANGER!!!!!! If inference fails, then synthesis will try
+  -- to implement the memory using basic logic resources. This
+  -- will almost certainly cause the compiler to get "stuck"
+  -- since synthesising such a huge number of basic logic resources
+  -- will take more or less forever.
+  --
+  -- So: if your compiler gets "stuck" then inference is not
+  -- the way to go.
+  memory : dualport_ram port map (
+    clk             => clk,
+    memAWriteEnable => memAWriteEnable,
+    memAAddr        => memAAddr_stdlogic,
+    memAWrite       => memAWrite_stdlogic,
+    memARead        => memARead_stdlogic,
+    memBWriteEnable => memBWriteEnable,
+    memBAddr        => memBAddr_stdlogic,
+    memBWrite       => memBWrite_stdlogic,
+    memBRead        => memBRead_stdlogic
+    );
+  memARead <= unsigned(memARead_stdlogic);
+  memBRead <= unsigned(memBRead_stdlogic);
+
+
+
+  tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0));
+
+
+
+  -- move out calculation of the opcode to a seperate process
+  -- to make things a bit easier to read
+  decodeControl : process(memBRead, pc, tOpcode_sel)
+    variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0);
+  begin
+
+    -- simplify opcode selection a bit so it passes more synthesizers
+    case (tOpcode_sel) is
+
+      when 0 => tOpcode := std_logic_vector(memBRead(31 downto 24));
+
+      when 1 => tOpcode := std_logic_vector(memBRead(23 downto 16));
+
+      when 2 => tOpcode := std_logic_vector(memBRead(15 downto 8));
+
+      when 3 => tOpcode := std_logic_vector(memBRead(7 downto 0));
+
+      when others => tOpcode := std_logic_vector(memBRead(7 downto 0));
+    end case;
+
+    sampledOpcode <= tOpcode;
+
+    if (tOpcode(7 downto 7) = OpCode_Im) then
+      sampledDecodedOpcode <= Decoded_Im;
+    elsif (tOpcode(7 downto 5) = OpCode_StoreSP) then
+      sampledDecodedOpcode <= Decoded_StoreSP;
+    elsif (tOpcode(7 downto 5) = OpCode_LoadSP) then
+      sampledDecodedOpcode <= Decoded_LoadSP;
+    elsif (tOpcode(7 downto 5) = OpCode_Emulate) then
+      sampledDecodedOpcode <= Decoded_Emulate;
+    elsif (tOpcode(7 downto 4) = OpCode_AddSP) then
+      sampledDecodedOpcode <= Decoded_AddSP;
+    else
+      case tOpcode(3 downto 0) is
+        when OpCode_Break =>
+          sampledDecodedOpcode <= Decoded_Break;
+        when OpCode_PushSP =>
+          sampledDecodedOpcode <= Decoded_PushSP;
+        when OpCode_PopPC =>
+          sampledDecodedOpcode <= Decoded_PopPC;
+        when OpCode_Add =>
+          sampledDecodedOpcode <= Decoded_Add;
+        when OpCode_Or =>
+          sampledDecodedOpcode <= Decoded_Or;
+        when OpCode_And =>
+          sampledDecodedOpcode <= Decoded_And;
+        when OpCode_Load =>
+          sampledDecodedOpcode <= Decoded_Load;
+        when OpCode_Not =>
+          sampledDecodedOpcode <= Decoded_Not;
+        when OpCode_Flip =>
+          sampledDecodedOpcode <= Decoded_Flip;
+        when OpCode_Store =>
+          sampledDecodedOpcode <= Decoded_Store;
+        when OpCode_PopSP =>
+          sampledDecodedOpcode <= Decoded_PopSP;
+        when others =>
+          sampledDecodedOpcode <= Decoded_Nop;
+      end case;  -- tOpcode(3 downto 0)
+    end if; tOpcode
+  end process;
+
+
+  opcodeControl: process(clk, areset)
+    variable spOffset : unsigned(4 downto 0);
+  begin
+
+    if areset = '1' then
+      state               <= State_Resync;
+      break               <= '0';
+      sp                  <= unsigned(spStart(maxAddrBit downto minAddrBit));
+      pc                  <= (others => '0');
+      idim_flag           <= '0';
+      begin_inst          <= '0';
+      memAAddr            <= (others => '0');
+      memBAddr            <= (others => '0');
+      memAWriteEnable     <= '0';
+      memBWriteEnable     <= '0';
+      out_mem_writeEnable <= '0';
+      out_mem_readEnable  <= '0';
+      memAWrite           <= (others => '0');
+      memBWrite           <= (others => '0');
+      inInterrupt         <= '0';
+
+    elsif (clk'event and clk = '1') then
+      memAWriteEnable <= '0';
+      memBWriteEnable <= '0';
+      -- This saves ca. 100 LUT's, by explicitly declaring that the
+      -- memAWrite can be left at whatever value if memAWriteEnable is
+      -- not set.
+      memAWrite       <= (others => DontCareValue);
+      memBWrite       <= (others => DontCareValue);
+--    out_mem_addr    <= (others => DontCareValue);
+--    mem_write       <= (others => DontCareValue);
+      spOffset        := (others => DontCareValue);
+      memAAddr        <= (others => DontCareValue);
+      memBAddr        <= (others => DontCareValue);
+
+      out_mem_writeEnable <= '0';
+      out_mem_readEnable  <= '0';
+      begin_inst          <= '0';
+      out_mem_addr        <= std_logic_vector(memARead(maxAddrBitIncIO downto 0));
+      mem_write           <= std_logic_vector(memBRead);
+
+      decodedOpcode <= sampledDecodedOpcode;
+      opcode        <= sampledOpcode;
+      if interrupt = '0' then
+        inInterrupt <= '0';             -- no longer in an interrupt
+      end if;
+
+      case state is
+
+        when State_Execute =>
+          state <= State_Fetch;
+          -- at this point:
+          -- memBRead contains opcode word
+          -- memARead contains top of stack
+          pc    <= pc + 1;
+
+          -- trace
+          begin_inst                             <= '1';
+          trace_pc                               <= (others => '0');
+          trace_pc(maxAddrBit downto 0)          <= std_logic_vector(pc);
+          trace_opcode                           <= opcode;
+          trace_sp                               <= (others => '0');
+          trace_sp(maxAddrBit downto minAddrBit) <= std_logic_vector(sp);
+          trace_topOfStack                       <= std_logic_vector(memARead);
+          trace_topOfStackB                      <= std_logic_vector(memBRead);
+
+          -- during the next cycle we'll be reading the next opcode       
+          spOffset(4)          := not opcode(4);
+          spOffset(3 downto 0) := unsigned(opcode(3 downto 0));
+
+          idim_flag <= '0';
+
+          case decodedOpcode is
+
+            when Decoded_Interrupt =>
+              sp                             <= sp - 1;
+              memAAddr                       <= sp - 1;
+              memAWriteEnable                <= '1';
+              memAWrite                      <= (others => DontCareValue);
+              memAWrite(maxAddrBit downto 0) <= pc;
+              pc                             <= to_unsigned(32, maxAddrBit+1);  -- interrupt address
+              report "ZPU jumped to interrupt!" severity note;
+
+            when Decoded_Im =>
+              idim_flag       <= '1';
+              memAWriteEnable <= '1';
+              if (idim_flag = '0') then
+                sp       <= sp - 1;
+                memAAddr <= sp-1;
+                for i in wordSize-1 downto 7 loop
+                  memAWrite(i) <= opcode(6);
+                end loop;
+                memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0));
+              else
+                memAAddr                       <= sp;
+                memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0);
+                memAWrite(6 downto 0)          <= unsigned(opcode(6 downto 0));
+              end if;  -- idim_flag
+
+            when Decoded_StoreSP =>
+              memBWriteEnable <= '1';
+              memBAddr        <= sp+spOffset;
+              memBWrite       <= memARead;
+              sp              <= sp + 1;
+              state           <= State_Resync;
+
+            when Decoded_LoadSP =>
+              sp       <= sp - 1;
+              memAAddr <= sp+spOffset;
+
+            when Decoded_Emulate =>
+              sp                             <= sp - 1;
+              memAWriteEnable                <= '1';
+              memAAddr                       <= sp - 1;
+              memAWrite                      <= (others => DontCareValue);
+              memAWrite(maxAddrBit downto 0) <= pc + 1;
+              -- The emulate address is:
+              --        98 7654 3210
+              -- 0000 00aa aaa0 0000
+              pc                             <= (others => '0');
+              pc(9 downto 5)                 <= unsigned(opcode(4 downto 0));
+
+            when Decoded_AddSP =>
+              memAAddr <= sp;
+              memBAddr <= sp+spOffset;
+              state    <= State_AddSP;
+
+            when Decoded_Break =>
+              report "Break instruction encountered" severity failure;
+              break <= '1';
+
+            when Decoded_PushSP =>
+              memAWriteEnable                         <= '1';
+              memAAddr                                <= sp - 1;
+              sp                                      <= sp - 1;
+              memAWrite                               <= (others => DontCareValue);
+              memAWrite(maxAddrBit downto minAddrBit) <= sp;
+
+            when Decoded_PopPC =>
+              pc    <= memARead(maxAddrBit downto 0);
+              sp    <= sp + 1;
+              state <= State_Resync;
+
+            when Decoded_Add =>
+              sp    <= sp + 1;
+              state <= State_Add;
+
+            when Decoded_Or =>
+              sp    <= sp + 1;
+              state <= State_Or;
+
+            when Decoded_And =>
+              sp    <= sp + 1;
+              state <= State_And;
+
+            when Decoded_Load =>
+              if (memARead(ioBit) = '1') then
+                out_mem_addr       <= std_logic_vector(memARead(maxAddrBitIncIO downto 0));
+                out_mem_readEnable <= '1';
+                state              <= State_ReadIO;
+              else
+                memAAddr <= memARead(maxAddrBit downto minAddrBit);
+              end if;
+
+            when Decoded_Not =>
+              memAAddr        <= sp(maxAddrBit downto minAddrBit);
+              memAWriteEnable <= '1';
+              memAWrite       <= not memARead;
+
+            when Decoded_Flip =>
+              memAAddr        <= sp(maxAddrBit downto minAddrBit);
+              memAWriteEnable <= '1';
+              for i in 0 to wordSize-1 loop
+                memAWrite(i) <= memARead(wordSize-1-i);
+              end loop;
+
+            when Decoded_Store =>
+              memBAddr <= sp + 1;
+              sp       <= sp + 1;
+              if (memARead(ioBit) = '1') then
+                state <= State_WriteIO;
+              else
+                state <= State_Store;
+              end if;
+
+            when Decoded_PopSP =>
+              sp    <= memARead(maxAddrBit downto minAddrBit);
+              state <= State_Resync;
+
+            when Decoded_Nop =>
+              memAAddr <= sp;
+
+            when others =>
+              null;
+
+          end case;  -- decodedOpcode
+
+        when State_ReadIO =>
+          memAAddr <= sp;
+          if (in_mem_busy = '0') then
+            state           <= State_Fetch;
+            memAWriteEnable <= '1';
+            memAWrite       <= unsigned(mem_read);
+          end if;
+
+        when State_WriteIO =>
+          sp                  <= sp + 1;
+          out_mem_writeEnable <= '1';
+          out_mem_addr        <= std_logic_vector(memARead(maxAddrBitIncIO downto 0));
+          mem_write           <= std_logic_vector(memBRead);
+          state               <= State_WriteIODone;
+
+        when State_WriteIODone =>
+          if (in_mem_busy = '0') then
+            state <= State_Resync;
+          end if;
+
+        when State_Fetch =>
+          -- We need to resync. During the *next* cycle
+          -- we'll fetch the opcode @ pc and thus it will
+          -- be available for State_Execute the cycle after
+          -- next
+          memBAddr <= pc(maxAddrBit downto minAddrBit);
+          state    <= State_FetchNext;
+
+        when State_FetchNext =>
+          -- at this point memARead contains the value that is either
+          -- from the top of stack or should be copied to the top of the stack
+          memAWriteEnable <= '1';
+          memAWrite       <= memARead;
+          memAAddr        <= sp;
+          memBAddr        <= sp + 1;
+          state           <= State_Decode;
+
+        when State_Decode =>
+          if interrupt = '1' and inInterrupt = '0' and idim_flag = '0' then
+            -- We got an interrupt, execute interrupt instead of next instruction
+            inInterrupt   <= '1';
+            decodedOpcode <= Decoded_Interrupt;
+          end if;
+          -- during the State_Execute cycle we'll be fetching SP+1
+          memAAddr <= sp;
+          memBAddr <= sp + 1;
+          state    <= State_Execute;
+
+        when State_Store =>
+          sp              <= sp + 1;
+          memAWriteEnable <= '1';
+          memAAddr        <= memARead(maxAddrBit downto minAddrBit);
+          memAWrite       <= memBRead;
+          state           <= State_Resync;
+
+        when State_AddSP =>
+          state <= State_Add;
+
+        when State_Add =>
+          memAAddr        <= sp;
+          memAWriteEnable <= '1';
+          memAWrite       <= memARead + memBRead;
+          state           <= State_Fetch;
+
+        when State_Or =>
+          memAAddr        <= sp;
+          memAWriteEnable <= '1';
+          memAWrite       <= memARead or memBRead;
+          state           <= State_Fetch;
+
+        when State_Resync =>
+          memAAddr <= sp;
+          state    <= State_Fetch;
+
+        when State_And =>
+          memAAddr        <= sp;
+          memAWriteEnable <= '1';
+          memAWrite       <= memARead and memBRead;
+          state           <= State_Fetch;
+
+        when others =>
+          null;
+
+      end case;  -- state
+      
+    end if;  -- reset, enable
+  end process;
 
 
 
diff --git a/zpu/hdl/zpu4/core/zpupkg.vhd b/zpu/hdl/zpu4/core/zpupkg.vhd
index 59d26e5..f6823f5 100644
--- a/zpu/hdl/zpu4/core/zpupkg.vhd
+++ b/zpu/hdl/zpu4/core/zpupkg.vhd
@@ -32,173 +32,187 @@
 -- are those of the authors and should not be interpreted as representing
 -- official policies, either expressed or implied, of the ZPU Project.
 
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
+library ieee;
+use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
 library work;
 use work.zpu_config.all;
 
+
 package zpupkg is
 
-	-- This bit is set for read/writes to IO
-	-- FIX!!! eventually this should be set to wordSize-1 so as to
-	-- to make the address of IO independent of amount of memory
-	-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-	-- libraries.
-	
-	constant byteBits			: integer := wordPower-3; -- # of bits in a word that addresses bytes
-	constant maxAddrBit			: integer := maxAddrBitIncIO-1;
-	constant ioBit				: integer := maxAddrBit+1;
-	constant wordSize			: integer := 2**wordPower;
-	constant wordBytes			: integer := wordSize/8;
-	constant minAddrBit			: integer := byteBits;
-	-- configurable internal stack size. Probably going to be 16 after toolchain is done
-	constant	stack_bits		: integer := 5; 
-	constant	stack_size		: integer := 2**stack_bits; 
-
-
-	component dualport_ram is
-	port (clk : in std_logic;
-		memAWriteEnable : in std_logic;
-		memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
-		memAWrite : in std_logic_vector(wordSize-1 downto 0);
-		memARead : out std_logic_vector(wordSize-1 downto 0);
-		memBWriteEnable : in std_logic;
-		memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
-		memBWrite : in std_logic_vector(wordSize-1 downto 0);
-		memBRead : out std_logic_vector(wordSize-1 downto 0));
-	end component;
-	
-
-	component dram is
-		port (clk : in std_logic;
-			areset : in std_logic;
-			mem_writeEnable : in std_logic;
-			mem_readEnable : in std_logic;
-			mem_addr : in std_logic_vector(maxAddrBit downto 0);
-			mem_write : in std_logic_vector(wordSize-1 downto 0);
-			mem_read : out std_logic_vector(wordSize-1 downto 0);
-			mem_busy : out std_logic;
-			mem_writeMask : in std_logic_vector(wordBytes-1 downto 0));
-	end component;
-
-
-	component trace is
-	  port(
-	       	clk         : in std_logic;
-	       	begin_inst  : in std_logic;
-	       	pc          : in std_logic_vector(maxAddrBitIncIO downto 0);
-			opcode		: in std_logic_vector(7 downto 0);
-			sp			: in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
-			memA		: in std_logic_vector(wordSize-1 downto 0);
-			memB		: in std_logic_vector(wordSize-1 downto 0);
-			busy         : in std_logic;
-			intSp		: in std_logic_vector(stack_bits-1 downto 0)
-			);
-	end component;
-
-	component zpu_core is
-    port ( clk : in std_logic;
-	 		  areset : in std_logic;
-	 		  enable : in std_logic; 
-	 		  in_mem_busy : in std_logic; 
-	 		  mem_read : in std_logic_vector(wordSize-1 downto 0);
-	 		  mem_write : out std_logic_vector(wordSize-1 downto 0);
-			  out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0);
-			  out_mem_writeEnable : out std_logic; 
-			  out_mem_readEnable : out std_logic;
-	 		  mem_writeMask: out std_logic_vector(wordBytes-1 downto 0);
-	 		  interrupt : in std_logic;
-	 		  break : out std_logic);
-	end component;
-
-
-	
-	component timer is
-	  port(
-	       clk              : in std_logic;
-			 areset				: in std_logic;
-			 we					: in std_logic;
-			 din					: in std_logic_vector(7 downto 0);
-			 adr					: in std_logic_vector(2 downto 0);
-			 dout					: out std_logic_vector(7 downto 0));
-	end component;
-
-	component  zpuio is
-		port (	areset			: in std_logic;
-				cpu_clk			: in std_logic;
-				clk_status		: in std_logic_vector(2 downto 0);
-				cpu_din			: in std_logic_vector(15 downto 0);
-				cpu_a			: in std_logic_vector(20 downto 0);
-				cpu_we			: in std_logic_vector(1 downto 0);
-				cpu_re			: in std_logic;
-				cpu_dout		: inout std_logic_vector(15 downto 0));
-	end component;
-
-
-
-	
-	-- opcode decode constants
-	constant	OpCode_Im		: std_logic_vector(7 downto 7) := "1";
-	constant	OpCode_StoreSP	: std_logic_vector(7 downto 5) := "010";
-	constant	OpCode_LoadSP	: std_logic_vector(7 downto 5) := "011";
-	constant	OpCode_Emulate	: std_logic_vector(7 downto 5) := "001";
-	constant	OpCode_AddSP	: std_logic_vector(7 downto 4) := "0001";
-	constant	OpCode_Short	: std_logic_vector(7 downto 4) := "0000";
-	
-	constant	OpCode_Break	: std_logic_vector(3 downto 0) := "0000";
-	constant	OpCode_NA4      : std_logic_vector(3 downto 0) := "0001";
-	constant	OpCode_PushSP	: std_logic_vector(3 downto 0) := "0010";
-	constant	OpCode_NA3		: std_logic_vector(3 downto 0) := "0011";
-	
-	constant	OpCode_PopPC	: std_logic_vector(3 downto 0) := "0100";
-	constant	OpCode_Add		: std_logic_vector(3 downto 0) := "0101";
-	constant	OpCode_And		: std_logic_vector(3 downto 0) := "0110";
-	constant	OpCode_Or		: std_logic_vector(3 downto 0) := "0111";
-	
-	constant	OpCode_Load		: std_logic_vector(3 downto 0) := "1000";
-	constant	OpCode_Not		: std_logic_vector(3 downto 0) := "1001";
-	constant	OpCode_Flip		: std_logic_vector(3 downto 0) := "1010";
-	constant	OpCode_Nop		: std_logic_vector(3 downto 0) := "1011";
-	
-	constant	OpCode_Store	: std_logic_vector(3 downto 0) := "1100";
-	constant	OpCode_PopSP	: std_logic_vector(3 downto 0) := "1101";
-	constant	OpCode_NA2		: std_logic_vector(3 downto 0) := "1110";
-	constant	OpCode_NA		: std_logic_vector(3 downto 0) := "1111";
-	
-	constant	OpCode_Lessthan				: std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
-	constant	OpCode_Lessthanorequal		: std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
-	constant	OpCode_Ulessthan			: std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
-	constant	OpCode_Ulessthanorequal		: std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
-
-	constant	OpCode_Swap					: std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
-	constant	OpCode_Mult					: std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
-	
-	constant	OpCode_Lshiftright			: std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
-	constant	OpCode_Ashiftleft			: std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
-	constant	OpCode_Ashiftright			: std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
-	constant	OpCode_Call					: std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
-
-	constant	OpCode_Eq					: std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
-	constant	OpCode_Neq					: std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
-
-	constant	OpCode_Sub					: std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
-	constant	OpCode_Loadb				: std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
-	constant	OpCode_Storeb				: std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
-
-	constant	OpCode_Eqbranch				: std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
-	constant	OpCode_Neqbranch			: std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
-	constant	OpCode_Poppcrel				: std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
-
-	constant	OpCode_Pushspadd			: std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
-	constant	OpCode_Mult16x16			: std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
-	constant	OpCode_Callpcrel			: std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
-	
-
-
-	constant OpCode_Size		: integer := 8;
-
-
-		
+  -- This bit is set for read/writes to IO
+  -- FIX!!! eventually this should be set to wordSize-1 so as to
+  -- to make the address of IO independent of amount of memory
+  -- reserved for CPU. Requires trivial tweaks in toolchain/runtime
+  -- libraries.
+  
+  constant byteBits   : integer := wordPower-3;  -- # of bits in a word that addresses bytes
+  constant maxAddrBit : integer := maxAddrBitIncIO-1;
+  constant ioBit      : integer := maxAddrBit+1;
+  constant wordSize   : integer := 2**wordPower;
+  constant wordBytes  : integer := wordSize/8;
+  constant minAddrBit : integer := byteBits;
+  -- configurable internal stack size. Probably going to be 16 after toolchain is done
+  constant stack_bits : integer := 5;
+  constant stack_size : integer := 2**stack_bits;
+
+
+  ------------------------------------------------------------ 
+  -- components
+
+  component dualport_ram is
+    port (
+      clk             : in  std_logic;
+      memAWriteEnable : in  std_logic;
+      memAAddr        : in  std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+      memAWrite       : in  std_logic_vector(wordSize-1 downto 0);
+      memARead        : out std_logic_vector(wordSize-1 downto 0);
+      memBWriteEnable : in  std_logic;
+      memBAddr        : in  std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+      memBWrite       : in  std_logic_vector(wordSize-1 downto 0);
+      memBRead        : out std_logic_vector(wordSize-1 downto 0)
+      );
+  end component dualport_ram;
+
+
+  component dram is
+    port (
+      clk             : in  std_logic;
+      areset          : in  std_logic;
+      mem_writeEnable : in  std_logic;
+      mem_readEnable  : in  std_logic;
+      mem_addr        : in  std_logic_vector(maxAddrBit downto 0);
+      mem_write       : in  std_logic_vector(wordSize-1 downto 0);
+      mem_read        : out std_logic_vector(wordSize-1 downto 0);
+      mem_busy        : out std_logic;
+      mem_writeMask   : in  std_logic_vector(wordBytes-1 downto 0)
+      );
+  end component dram;
+
+
+  component trace is
+    port (
+      clk        : in std_logic;
+      begin_inst : in std_logic;
+      pc         : in std_logic_vector(maxAddrBitIncIO downto 0);
+      opcode     : in std_logic_vector(7 downto 0);
+      sp         : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+      memA       : in std_logic_vector(wordSize-1 downto 0);
+      memB       : in std_logic_vector(wordSize-1 downto 0);
+      busy       : in std_logic;
+      intSp      : in std_logic_vector(stack_bits-1 downto 0)
+      );
+  end component trace;
+
+
+  component zpu_core is
+    port ( 
+      clk                 : in  std_logic;
+      areset              : in  std_logic;
+      enable              : in  std_logic; 
+      in_mem_busy         : in  std_logic;
+      mem_read            : in  std_logic_vector(wordSize-1 downto 0);
+      mem_write           : out std_logic_vector(wordSize-1 downto 0);
+      out_mem_addr        : out std_logic_vector(maxAddrBitIncIO downto 0);
+      out_mem_writeEnable : out std_logic;
+      out_mem_readEnable  : out std_logic;
+      mem_writeMask       : out std_logic_vector(wordBytes-1 downto 0);
+      interrupt           : in  std_logic;
+      break               : out std_logic
+      );
+  end component zpu_core;
+
+
+  component timer is
+    port (
+      clk    : in  std_logic;
+      areset : in  std_logic;
+      we     : in  std_logic;
+      din    : in  std_logic_vector(7 downto 0);
+      adr    : in  std_logic_vector(2 downto 0);
+      dout   : out std_logic_vector(7 downto 0)
+      );
+  end component timer;
+
+
+  component zpuio is
+    port (
+      areset     : in    std_logic;
+      cpu_clk    : in    std_logic;
+      clk_status : in    std_logic_vector(2 downto 0);
+      cpu_din    : in    std_logic_vector(15 downto 0);
+      cpu_a      : in    std_logic_vector(20 downto 0);
+      cpu_we     : in    std_logic_vector(1 downto 0);
+      cpu_re     : in    std_logic;
+      cpu_dout   : inout std_logic_vector(15 downto 0)
+      );
+  end component zpuio;
+
+
+  ------------------------------------------------------------ 
+  -- constants
+
+  -- opcode decode constants
+  constant OpCode_Im               : std_logic_vector(7 downto 7) := "1";
+  constant OpCode_StoreSP          : std_logic_vector(7 downto 5) := "010";
+  constant OpCode_LoadSP           : std_logic_vector(7 downto 5) := "011";
+  constant OpCode_Emulate          : std_logic_vector(7 downto 5) := "001";
+  constant OpCode_AddSP            : std_logic_vector(7 downto 4) := "0001";
+  constant OpCode_Short            : std_logic_vector(7 downto 4) := "0000";
+  --
+  constant OpCode_Break            : std_logic_vector(3 downto 0) := "0000";
+  constant OpCode_NA4              : std_logic_vector(3 downto 0) := "0001";
+  constant OpCode_PushSP           : std_logic_vector(3 downto 0) := "0010";
+  constant OpCode_NA3              : std_logic_vector(3 downto 0) := "0011";
+  --
+  constant OpCode_PopPC            : std_logic_vector(3 downto 0) := "0100";
+  constant OpCode_Add              : std_logic_vector(3 downto 0) := "0101";
+  constant OpCode_And              : std_logic_vector(3 downto 0) := "0110";
+  constant OpCode_Or               : std_logic_vector(3 downto 0) := "0111";
+  --
+  constant OpCode_Load             : std_logic_vector(3 downto 0) := "1000";
+  constant OpCode_Not              : std_logic_vector(3 downto 0) := "1001";
+  constant OpCode_Flip             : std_logic_vector(3 downto 0) := "1010";
+  constant OpCode_Nop              : std_logic_vector(3 downto 0) := "1011";
+  --
+  constant OpCode_Store            : std_logic_vector(3 downto 0) := "1100";
+  constant OpCode_PopSP            : std_logic_vector(3 downto 0) := "1101";
+  constant OpCode_NA2              : std_logic_vector(3 downto 0) := "1110";
+  constant OpCode_NA               : std_logic_vector(3 downto 0) := "1111";
+  --
+  constant OpCode_Lessthan         : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
+  constant OpCode_Lessthanorequal  : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
+  constant OpCode_Ulessthan        : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
+  constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
+  --
+  constant OpCode_Swap             : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
+  constant OpCode_Mult             : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
+  --
+  constant OpCode_Lshiftright      : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
+  constant OpCode_Ashiftleft       : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
+  constant OpCode_Ashiftright      : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
+  constant OpCode_Call             : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
+  --
+  constant OpCode_Eq               : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
+  constant OpCode_Neq              : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
+  --
+  constant OpCode_Sub              : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
+  constant OpCode_Loadb            : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
+  constant OpCode_Storeb           : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
+  --
+  constant OpCode_Eqbranch         : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
+  constant OpCode_Neqbranch        : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
+  constant OpCode_Poppcrel         : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
+  --
+  constant OpCode_Pushspadd        : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
+  constant OpCode_Mult16x16        : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
+  constant OpCode_Callpcrel        : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
+  --
+  --
+  constant OpCode_Size             : integer                      := 8;
+
+
+  
 end zpupkg;
-- 
cgit v1.1


From 04772b6a0bbe7017f5f7b44cfa203c3f7efbff64 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=98yvind=20Harboe?= 
Date: Tue, 1 Mar 2011 20:52:55 +0100
Subject: whitespace fixes: use fromdos on all .vhd files
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Signed-off-by: Øyvind Harboe 
---
 misc/arm7/src/arm7pkg.vhd                    |   60 +-
 misc/arm7/src/arm7wb.vhd                     |  472 +-
 misc/ddrsdram/simsrc/ddr_tb.vhd              |  602 +--
 misc/ddrsdram/src/ddr_pkg.vhd                |  212 +-
 misc/ddrsdram/src/ddr_top.vhd                | 1486 +++---
 misc/ddrsdram/src/mt46v16m16.vhd             | 2640 +++++-----
 misc/wishbone/src/atomic32_access.vhd        |  262 +-
 misc/wishbone/src/wishbone_pkg.vhd           |  104 +-
 zpu/hdl/example/bram_dmips.vhd               | 6712 +++++++++++++-------------
 zpu/hdl/example/helloworld.vhd               | 6308 ++++++++++++------------
 zpu/hdl/example/interrupt.vhd                | 6312 ++++++++++++------------
 zpu/hdl/example/sim_small_fpga_top.vhd       |  414 +-
 zpu/hdl/example/sim_small_fpga_top_noint.vhd |  386 +-
 zpu/hdl/example/zpu_config.vhd               |  112 +-
 zpu/hdl/example_medium/dram_dmips.vhd        | 6616 ++++++++++++-------------
 zpu/hdl/example_medium/dram_hello.vhd        | 6214 ++++++++++++------------
 zpu/hdl/example_medium/sim_fpga_top.vhd      |  370 +-
 zpu/hdl/example_medium/zpu_config_trace.vhd  |   34 +-
 zpu/hdl/wishbone/wishbone_pkg.vhd            |  172 +-
 zpu/hdl/wishbone/zpu_system.vhd              |  208 +-
 zpu/hdl/wishbone/zpu_wb_bridge.vhd           |  166 +-
 zpu/hdl/zpu4/core/zpu_config.vhd             |   84 +-
 zpu/hdl/zpu4/core/zpu_core.vhd               |  154 +-
 zpu/hdl/zpu4/core/zpu_core_small.vhd         |  112 +-
 zpu/hdl/zpu4/core/zpupkg.vhd                 |   86 +-
 zpu/hdl/zpu4/src/clocks.vhd                  |  490 +-
 zpu/hdl/zpu4/src/io.vhd                      |  224 +-
 zpu/hdl/zpu4/src/timer.vhd                   |  122 +-
 zpu/hdl/zpu4/src/trace.vhd                   |  234 +-
 zpu/hdl/zpu4/src/txt_util.vhd                | 1242 ++---
 zpu/hdl/zpu4/src/zpuio.vhd                   |  464 +-
 zpu/hdl/zy2000/timer.vhd                     |  274 +-
 zpu/hdl/zy2000/trace.vhd                     |  168 +-
 zpu/hdl/zy2000/txt_util.vhd                  | 1174 ++---
 zpu/hdl/zy2000/zpu_config.vhd                |   40 +-
 zpu/hdl/zy2000/zpu_config_fast.vhd           |   40 +-
 zpu/hdl/zy2000/zpupkg.vhd                    |  336 +-
 37 files changed, 22553 insertions(+), 22553 deletions(-)

diff --git a/misc/arm7/src/arm7pkg.vhd b/misc/arm7/src/arm7pkg.vhd
index 855fbdb..4dcbb9c 100644
--- a/misc/arm7/src/arm7pkg.vhd
+++ b/misc/arm7/src/arm7pkg.vhd
@@ -1,31 +1,31 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-library work;
-use work.wishbone_pkg.all;
-
-package arm7 is
-
-	component arm7wb
-	generic(
-			simulate_io_time	: boolean := false);
-	port (	areset			: in std_logic;
-			cpu_clk			: in std_logic;
-			cpu_clk_2x		: in std_logic;
-			cpu_a_p			: in std_logic_vector(23 downto 1);
-			cpu_wr_n_p		: in std_logic_vector(1 downto 0);
-			cpu_cs_n_p		: in std_logic_vector(3 downto 1);
-			cpu_oe_n_p		: in std_logic;
-			cpu_d_p			: inout std_logic_vector(15 downto 0);
-			cpu_wait_n_p	: out std_logic;
-			
-			arm7_debug		: out std_logic;
-			arm7_debug2		: out std_logic;
-			
-			wb_o			: out wishbone_bus_in;
-			wb_i            : in wishbone_bus_out);			
-	end component;
-	
-end arm7;
-
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library work;
+use work.wishbone_pkg.all;
+
+package arm7 is
+
+	component arm7wb
+	generic(
+			simulate_io_time	: boolean := false);
+	port (	areset			: in std_logic;
+			cpu_clk			: in std_logic;
+			cpu_clk_2x		: in std_logic;
+			cpu_a_p			: in std_logic_vector(23 downto 1);
+			cpu_wr_n_p		: in std_logic_vector(1 downto 0);
+			cpu_cs_n_p		: in std_logic_vector(3 downto 1);
+			cpu_oe_n_p		: in std_logic;
+			cpu_d_p			: inout std_logic_vector(15 downto 0);
+			cpu_wait_n_p	: out std_logic;
+			
+			arm7_debug		: out std_logic;
+			arm7_debug2		: out std_logic;
+			
+			wb_o			: out wishbone_bus_in;
+			wb_i            : in wishbone_bus_out);			
+	end component;
+	
+end arm7;
+
 			
\ No newline at end of file
diff --git a/misc/arm7/src/arm7wb.vhd b/misc/arm7/src/arm7wb.vhd
index 3366352..85f0ef7 100644
--- a/misc/arm7/src/arm7wb.vhd
+++ b/misc/arm7/src/arm7wb.vhd
@@ -1,236 +1,236 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-library work;
-use work.phi_config.all;
-use work.wishbone_pkg.all;
-
-entity arm7wb is
-	generic(
-			simulate_io_time	: boolean := false);
-	port (	areset			: in std_logic;
-			cpu_clk			: in std_logic;
-			cpu_clk_2x		: in std_logic;
-			cpu_a_p			: in std_logic_vector(23 downto 1);
-			cpu_wr_n_p		: in std_logic_vector(1 downto 0);
-			cpu_cs_n_p		: in std_logic_vector(3 downto 1);
-			cpu_oe_n_p		: in std_logic;
-			cpu_d_p			: inout std_logic_vector(15 downto 0);
-			cpu_wait_n_p	: out std_logic;
-
-			arm7_debug		: out std_logic;
-			arm7_debug2		: out std_logic;
-
-			wb_o			: out wishbone_bus_in;
-			wb_i            : in wishbone_bus_out);			
-end arm7wb;
-			
-architecture behave of arm7wb is
-
-type	cpu_state_type		is (cpu_idle, cpu_cs, cpu_end);
-
--- Input simulated delay
-signal	cpu_wr_n_p_del		: std_logic_vector(1 downto 0);
-signal 	cpu_a_p_del			: std_logic_vector(23 downto 1);
-signal	cpu_d_p_del			: std_logic_vector(15 downto 0);
-signal	cpu_cs_n_p_del		: std_logic_vector(3 downto 1);
-signal	cpu_oe_n_p_del		: std_logic;
-
--- Clock phase detect signals
-signal	cpu_clk_toggle		: std_logic;
-signal	cpu_clk_smp1		: std_logic;
-signal	cpu_clk_smp2		: std_logic;
-signal	cpu_clk_phase		: std_logic;
-
--- Internal version of control signal (for feedback)
-signal	arm7_din_int		: std_logic_vector(15 downto 0);
-signal	arm7_dout_int		: std_logic_vector(15 downto 0);
-signal	arm7_a_int			: std_logic_vector(23 downto 1);
-signal	arm7_we_int			: std_logic_vector(1 downto 0);
-signal  cyc_int             : std_logic;
-signal	we_int				: std_logic;
-signal  adr_reg             : std_logic_vector(25 downto 24);
-
--- Input sampled
-signal	cpu_a_smp			: std_logic_vector(23 downto 1);
-signal	cpu_d_smp			: std_logic_vector(15 downto 0);
-signal	cpu_cs_n 			: std_logic_vector(3 downto 1);
-signal	cpu_oe_n			: std_logic;
-signal	cpu_wr_n 			: std_logic_vector(1 downto 0);
-
--- Main FSM
-signal	cpu_state			: cpu_state_type;
-
-constant	Clock_2_Out	: time := 5.5 ns;
-constant	Input_Setup	: time := 2.5 ns;
-
-begin
-
-	arm7_dout_int <= wb_i.dat(15 downto 0) when (arm7_a_int(1) = '0') else wb_i.dat(31 downto 16);
-	arm7_debug <= cpu_oe_n;
-	arm7_debug2 <= cpu_wr_n(0);
-
-	-- Generate 64 MBytes address based on 3 CS_N signals from CPU
-	-- Memory map FPGA internal
-	--  0x00000000 DDR 32 MBytes (CS_N2 and CS_N3)
-	--  0x00200000 FPGA/Ethernet (CS_N1)
-	wb_o.adr(31 downto 26) <= "000000";
-	wb_o.adr(25 downto 24) <= adr_reg;
-	wb_o.adr(23 downto 1) <= arm7_a_int(23 downto 1);
-	wb_o.adr(0) <= '0';
-	
-	wb_o.dat <= (x"0000" & arm7_din_int) when (arm7_a_int(1) = '0') else (arm7_din_int & x"0000");
-	wb_o.sel <= ("00" & arm7_we_int) when (arm7_a_int(1) = '0') else (arm7_we_int & "00");	
-	
-	wb_o.cyc <= cyc_int;
-	wb_o.stb <= cyc_int;
-	wb_o.we <= cpu_oe_n;
-
-	iotimingon:
-	if simulate_io_time generate
-	begin
-		cpu_wr_n_p_del <= transport "XX" after 0 ns, cpu_wr_n_p after Input_Setup;
-		cpu_a_p_del <= transport "XXXXXXXXXXXXXXXXXXXXXXX" after 0 ns, cpu_a_p after Input_Setup;
-		cpu_d_p_del <= transport "XXXXXXXXXXXXXXXX" after 0 ns, cpu_d_p after Input_Setup;
-		cpu_cs_n_p_del <= transport "XXX" after 0 ns, cpu_cs_n_p after Input_Setup;
-		cpu_oe_n_p_del <= transport 'X' after 0 ns, cpu_oe_n_p after Input_Setup;
-	end generate;
-	
-	iotimingoff:
-	if not simulate_io_time generate
-	begin
-		cpu_wr_n_p_del <= cpu_wr_n_p;
-		cpu_a_p_del <=  cpu_a_p;
-		cpu_d_p_del <= cpu_d_p;
-		cpu_cs_n_p_del <= cpu_cs_n_p;
-		cpu_oe_n_p_del <= cpu_oe_n_p;
-	end generate;
-	
-	process(cpu_clk, areset)	-- Toggle FF with 1x clock to find phase
-	begin
-		if areset = '1' then
-			cpu_clk_toggle <= '0';
-		elsif (cpu_clk'event and cpu_clk = '1') then
-			cpu_clk_toggle <= not(cpu_clk_toggle);
-		end if;
-	end process;
-	
-	process(cpu_clk_2x, areset)	-- Find phase relationsship between 1x and 2x clock
-	begin
-		if areset = '1' then
-			cpu_clk_smp1 <= '0';
-			cpu_clk_smp2 <= '1';
-			cpu_clk_phase <= '0';
-		elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
-			cpu_clk_smp1 <= cpu_clk_toggle;
-			cpu_clk_smp2 <= cpu_clk_smp1;
-			if cpu_clk_smp1 = '1' and cpu_clk_smp2 = '0' then
-				cpu_clk_phase <= '0';
-			else
-				cpu_clk_phase <= not(cpu_clk_phase);
-			end if;
-		end if;
-	end process;
-	
-	process(cpu_clk_2x, areset)	-- Sample input signals on 2x clock
-	begin
-		if areset = '1' then
-			cpu_d_smp <= "0000000000000000";
-			cpu_cs_n <= "111";
-		elsif (cpu_clk_2x = '1' and cpu_clk_2x'event) then
-			cpu_d_smp <= cpu_d_p_del;
-			cpu_cs_n <= cpu_cs_n_p_del;
-		end if;
-	end process;
-
-	process(cpu_clk, areset)	-- Sample input signals on 1x clock
-	begin
-		if areset = '1' then
-			cpu_a_smp <= "00000000000000000000000";
-			cpu_oe_n <= '1';
-			cpu_wr_n <= "11";
-		elsif (cpu_clk = '1' and cpu_clk'event) then
-			cpu_a_smp <= cpu_a_p_del;
-			cpu_oe_n <= cpu_oe_n_p_del;
-			cpu_wr_n <= cpu_wr_n_p_del;
-		end if;
-	end process;
-
-	arm7_din_int <= cpu_d_smp;
-	arm7_a_int <= cpu_a_smp;
-	arm7_we_int <= not(cpu_wr_n);
-	
-	process(cpu_clk, areset)
-	begin
-		if areset = '1' then
-			cpu_state <= cpu_idle;
-			cyc_int <= '0';
-			we_int <= '0';
-			adr_reg <= "00";
-			cpu_d_p	<= (others => 'Z');
-		elsif (cpu_clk'event and cpu_clk = '1') then
-			
-			cyc_int <= '0';
-			we_int <= '0';
-			cpu_d_p	<= (others => 'Z') after Clock_2_Out;
-			
-			
-			case cpu_state is
-			
-				when cpu_idle =>
-					if cpu_oe_n = '1' then
-						we_int <= '1';
-					end if;
-					if cpu_cs_n(1) = '0' then
-						cyc_int <= '1';
-						adr_reg <= "10";
-						cpu_state <= cpu_cs;
-					end if;
-					if cpu_cs_n(2) = '0' then
-						cyc_int <= '1';
-						adr_reg <= "00";
-						cpu_state <= cpu_cs;
-					end if;
-					if cpu_cs_n(3) = '0' then
-						cyc_int <= '1';
-						adr_reg <= "01";
-						cpu_state <= cpu_cs;
-					end if;
-					
-				when cpu_cs =>
-					if cpu_oe_n = '0' then
-						cpu_d_p <= arm7_dout_int after Clock_2_Out;
-						if wb_i.ack = '1' then
-							cpu_state <= cpu_end;
-						else
-							cyc_int <= '1';
-						end if;
-					else
-						if wb_i.ack = '0' then
-							cyc_int <= '1';
-							we_int <= '1';
-						else
-							cpu_state <= cpu_end;
-						end if;
-					end if;
-						
-				when others =>
-					cpu_state <= cpu_idle;
-
-			end case;
-		end if;
-	end process;
-	
-	process(cpu_clk_2x, areset)
-	begin
-		if areset = '1' then
-			cpu_wait_n_p <= '1';
-		elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
-			cpu_wait_n_p <= '1' after Clock_2_Out;
-			if (cpu_state = cpu_cs and wb_i.ack = '0') then
-			   	cpu_wait_n_p <= '0' after Clock_2_Out;
-			end if;
-		end if;
-	end process;
-	
-end behave;			
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library work;
+use work.phi_config.all;
+use work.wishbone_pkg.all;
+
+entity arm7wb is
+	generic(
+			simulate_io_time	: boolean := false);
+	port (	areset			: in std_logic;
+			cpu_clk			: in std_logic;
+			cpu_clk_2x		: in std_logic;
+			cpu_a_p			: in std_logic_vector(23 downto 1);
+			cpu_wr_n_p		: in std_logic_vector(1 downto 0);
+			cpu_cs_n_p		: in std_logic_vector(3 downto 1);
+			cpu_oe_n_p		: in std_logic;
+			cpu_d_p			: inout std_logic_vector(15 downto 0);
+			cpu_wait_n_p	: out std_logic;
+
+			arm7_debug		: out std_logic;
+			arm7_debug2		: out std_logic;
+
+			wb_o			: out wishbone_bus_in;
+			wb_i            : in wishbone_bus_out);			
+end arm7wb;
+			
+architecture behave of arm7wb is
+
+type	cpu_state_type		is (cpu_idle, cpu_cs, cpu_end);
+
+-- Input simulated delay
+signal	cpu_wr_n_p_del		: std_logic_vector(1 downto 0);
+signal 	cpu_a_p_del			: std_logic_vector(23 downto 1);
+signal	cpu_d_p_del			: std_logic_vector(15 downto 0);
+signal	cpu_cs_n_p_del		: std_logic_vector(3 downto 1);
+signal	cpu_oe_n_p_del		: std_logic;
+
+-- Clock phase detect signals
+signal	cpu_clk_toggle		: std_logic;
+signal	cpu_clk_smp1		: std_logic;
+signal	cpu_clk_smp2		: std_logic;
+signal	cpu_clk_phase		: std_logic;
+
+-- Internal version of control signal (for feedback)
+signal	arm7_din_int		: std_logic_vector(15 downto 0);
+signal	arm7_dout_int		: std_logic_vector(15 downto 0);
+signal	arm7_a_int			: std_logic_vector(23 downto 1);
+signal	arm7_we_int			: std_logic_vector(1 downto 0);
+signal  cyc_int             : std_logic;
+signal	we_int				: std_logic;
+signal  adr_reg             : std_logic_vector(25 downto 24);
+
+-- Input sampled
+signal	cpu_a_smp			: std_logic_vector(23 downto 1);
+signal	cpu_d_smp			: std_logic_vector(15 downto 0);
+signal	cpu_cs_n 			: std_logic_vector(3 downto 1);
+signal	cpu_oe_n			: std_logic;
+signal	cpu_wr_n 			: std_logic_vector(1 downto 0);
+
+-- Main FSM
+signal	cpu_state			: cpu_state_type;
+
+constant	Clock_2_Out	: time := 5.5 ns;
+constant	Input_Setup	: time := 2.5 ns;
+
+begin
+
+	arm7_dout_int <= wb_i.dat(15 downto 0) when (arm7_a_int(1) = '0') else wb_i.dat(31 downto 16);
+	arm7_debug <= cpu_oe_n;
+	arm7_debug2 <= cpu_wr_n(0);
+
+	-- Generate 64 MBytes address based on 3 CS_N signals from CPU
+	-- Memory map FPGA internal
+	--  0x00000000 DDR 32 MBytes (CS_N2 and CS_N3)
+	--  0x00200000 FPGA/Ethernet (CS_N1)
+	wb_o.adr(31 downto 26) <= "000000";
+	wb_o.adr(25 downto 24) <= adr_reg;
+	wb_o.adr(23 downto 1) <= arm7_a_int(23 downto 1);
+	wb_o.adr(0) <= '0';
+	
+	wb_o.dat <= (x"0000" & arm7_din_int) when (arm7_a_int(1) = '0') else (arm7_din_int & x"0000");
+	wb_o.sel <= ("00" & arm7_we_int) when (arm7_a_int(1) = '0') else (arm7_we_int & "00");	
+	
+	wb_o.cyc <= cyc_int;
+	wb_o.stb <= cyc_int;
+	wb_o.we <= cpu_oe_n;
+
+	iotimingon:
+	if simulate_io_time generate
+	begin
+		cpu_wr_n_p_del <= transport "XX" after 0 ns, cpu_wr_n_p after Input_Setup;
+		cpu_a_p_del <= transport "XXXXXXXXXXXXXXXXXXXXXXX" after 0 ns, cpu_a_p after Input_Setup;
+		cpu_d_p_del <= transport "XXXXXXXXXXXXXXXX" after 0 ns, cpu_d_p after Input_Setup;
+		cpu_cs_n_p_del <= transport "XXX" after 0 ns, cpu_cs_n_p after Input_Setup;
+		cpu_oe_n_p_del <= transport 'X' after 0 ns, cpu_oe_n_p after Input_Setup;
+	end generate;
+	
+	iotimingoff:
+	if not simulate_io_time generate
+	begin
+		cpu_wr_n_p_del <= cpu_wr_n_p;
+		cpu_a_p_del <=  cpu_a_p;
+		cpu_d_p_del <= cpu_d_p;
+		cpu_cs_n_p_del <= cpu_cs_n_p;
+		cpu_oe_n_p_del <= cpu_oe_n_p;
+	end generate;
+	
+	process(cpu_clk, areset)	-- Toggle FF with 1x clock to find phase
+	begin
+		if areset = '1' then
+			cpu_clk_toggle <= '0';
+		elsif (cpu_clk'event and cpu_clk = '1') then
+			cpu_clk_toggle <= not(cpu_clk_toggle);
+		end if;
+	end process;
+	
+	process(cpu_clk_2x, areset)	-- Find phase relationsship between 1x and 2x clock
+	begin
+		if areset = '1' then
+			cpu_clk_smp1 <= '0';
+			cpu_clk_smp2 <= '1';
+			cpu_clk_phase <= '0';
+		elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
+			cpu_clk_smp1 <= cpu_clk_toggle;
+			cpu_clk_smp2 <= cpu_clk_smp1;
+			if cpu_clk_smp1 = '1' and cpu_clk_smp2 = '0' then
+				cpu_clk_phase <= '0';
+			else
+				cpu_clk_phase <= not(cpu_clk_phase);
+			end if;
+		end if;
+	end process;
+	
+	process(cpu_clk_2x, areset)	-- Sample input signals on 2x clock
+	begin
+		if areset = '1' then
+			cpu_d_smp <= "0000000000000000";
+			cpu_cs_n <= "111";
+		elsif (cpu_clk_2x = '1' and cpu_clk_2x'event) then
+			cpu_d_smp <= cpu_d_p_del;
+			cpu_cs_n <= cpu_cs_n_p_del;
+		end if;
+	end process;
+
+	process(cpu_clk, areset)	-- Sample input signals on 1x clock
+	begin
+		if areset = '1' then
+			cpu_a_smp <= "00000000000000000000000";
+			cpu_oe_n <= '1';
+			cpu_wr_n <= "11";
+		elsif (cpu_clk = '1' and cpu_clk'event) then
+			cpu_a_smp <= cpu_a_p_del;
+			cpu_oe_n <= cpu_oe_n_p_del;
+			cpu_wr_n <= cpu_wr_n_p_del;
+		end if;
+	end process;
+
+	arm7_din_int <= cpu_d_smp;
+	arm7_a_int <= cpu_a_smp;
+	arm7_we_int <= not(cpu_wr_n);
+	
+	process(cpu_clk, areset)
+	begin
+		if areset = '1' then
+			cpu_state <= cpu_idle;
+			cyc_int <= '0';
+			we_int <= '0';
+			adr_reg <= "00";
+			cpu_d_p	<= (others => 'Z');
+		elsif (cpu_clk'event and cpu_clk = '1') then
+			
+			cyc_int <= '0';
+			we_int <= '0';
+			cpu_d_p	<= (others => 'Z') after Clock_2_Out;
+			
+			
+			case cpu_state is
+			
+				when cpu_idle =>
+					if cpu_oe_n = '1' then
+						we_int <= '1';
+					end if;
+					if cpu_cs_n(1) = '0' then
+						cyc_int <= '1';
+						adr_reg <= "10";
+						cpu_state <= cpu_cs;
+					end if;
+					if cpu_cs_n(2) = '0' then
+						cyc_int <= '1';
+						adr_reg <= "00";
+						cpu_state <= cpu_cs;
+					end if;
+					if cpu_cs_n(3) = '0' then
+						cyc_int <= '1';
+						adr_reg <= "01";
+						cpu_state <= cpu_cs;
+					end if;
+					
+				when cpu_cs =>
+					if cpu_oe_n = '0' then
+						cpu_d_p <= arm7_dout_int after Clock_2_Out;
+						if wb_i.ack = '1' then
+							cpu_state <= cpu_end;
+						else
+							cyc_int <= '1';
+						end if;
+					else
+						if wb_i.ack = '0' then
+							cyc_int <= '1';
+							we_int <= '1';
+						else
+							cpu_state <= cpu_end;
+						end if;
+					end if;
+						
+				when others =>
+					cpu_state <= cpu_idle;
+
+			end case;
+		end if;
+	end process;
+	
+	process(cpu_clk_2x, areset)
+	begin
+		if areset = '1' then
+			cpu_wait_n_p <= '1';
+		elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
+			cpu_wait_n_p <= '1' after Clock_2_Out;
+			if (cpu_state = cpu_cs and wb_i.ack = '0') then
+			   	cpu_wait_n_p <= '0' after Clock_2_Out;
+			end if;
+		end if;
+	end process;
+	
+end behave;			
diff --git a/misc/ddrsdram/simsrc/ddr_tb.vhd b/misc/ddrsdram/simsrc/ddr_tb.vhd
index 249dffb..92d1e4b 100644
--- a/misc/ddrsdram/simsrc/ddr_tb.vhd
+++ b/misc/ddrsdram/simsrc/ddr_tb.vhd
@@ -1,301 +1,301 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-library work;
-use work.ddr.all;
-
-entity ddr_tb is
-	port (	areset			: in std_logic;
-			break_out		: out std_logic);
-end ddr_tb;
-
-architecture behave of ddr_tb is
-
-signal	cpu_clk			: std_logic;
-signal	cpu_clk_2x		: std_logic;
-signal	cpu_clk_4x		: std_logic;
-signal	ddr_in_clk		: std_logic;
-signal	ddr_in_clk_2x	: std_logic;
-
-signal	ddr_command		: std_logic_vector(15 downto 0);
-signal	ddr_command_we	: std_logic;
-			
-signal	ddr_data_read	: std_logic_vector(31 downto 0);	-- Data read from DDR SDRAM
-signal	ddr_data_write	: std_logic_vector(35 downto 0);		-- Data to be written to DDR SDRAM
-signal	ddr_req_adr		: std_logic_vector(23 downto 1);		-- Request address
-signal	ddr_req			: std_logic;							-- Request DDR SDRAM access
-signal	ddr_req_ack		: std_logic;							-- Request acknowledge
-signal	ddr_busy		: std_logic;							-- Request acknowledge
-signal	ddr_rd_wr_n		: std_logic;							-- Access type 1=READ, 0=WRITE
-signal	ddr_req_len		: std_logic;							-- Number of 16-bits words to transfer
-signal	ddr_read_en		: std_logic;						-- Enable signal for read data
-signal	ddr_write_en	: std_logic;						-- Enable (read) signal for data write
-signal	refresh_en		: std_logic;
-
-signal	sdr_clk_p       : std_logic;    -- ddr_sdram_clock
-signal	sdr_clk_n_p     : std_logic;    -- /ddr_sdram_clock
-signal	cke_q_p         : std_logic;    -- clock enable
-signal	cs_qn_p         : std_logic;    -- /chip select
-signal	ras_qn_p        : std_logic;    -- /ras
-signal	cas_qn_p        : std_logic;    -- /cas
-signal	we_qn_p         : std_logic;    -- /write enable
-signal	dm_q_p          : std_logic_vector(1 downto 0);     -- data mask bits, set to "00"
-signal	dqs_q_p         : std_logic_vector(1 downto 0);    -- data strobe, only for write
-signal	ba_q_p          : std_logic_vector(1 downto 0);   -- bank select
-signal	sdr_a_p		    : std_logic_vector(12 downto 0);   -- address bus 
-signal	sdr_d_p         : std_logic_vector(15 downto 0); 			-- bidir data bus
-
-constant min_time	: time := 1.875 ns;
-
-begin
-
-	clock1:
-	process
-	begin
-		loop
-			cpu_clk_4x <= '1';
-			wait for min_time;
-			cpu_clk_4x <= '0';
-			wait for min_time;
-		end loop;
-	end process;
-
-	clock2:
-	process
-	begin
-		loop
-			cpu_clk_2x <= '1' after 100 ps;
-			wait until rising_edge(cpu_clk_4x);
-			cpu_clk_2x <= '0' after 100 ps;
-			wait until rising_edge(cpu_clk_4x);
-		end loop;
-	end process;
-
-	clock3:
-	process
-	begin
-		loop
-			cpu_clk <= '1' after 100 ps;
-			wait until rising_edge(cpu_clk_2x);
-			cpu_clk <= '0' after 100 ps;
-			wait until rising_edge(cpu_clk_2x);
-		end loop;
-	end process;
-	
-	ddr_in_clk_2x <= cpu_clk_4x after 1 ns;
-
-	clock4:
-	process
-	begin
-		loop
-			ddr_in_clk <= '0' after 100 ps;
-			wait until rising_edge(ddr_in_clk_2x);
-			ddr_in_clk <= '1' after 100 ps;
-			wait until rising_edge(ddr_in_clk_2x);
-		end loop;
-	end process;
-	
-	inputdata:
-	process
-	begin
-		-- Wait until global reset released
-		loop
-			ddr_command <= x"0000";
-			ddr_command_we <= '0';
-			ddr_data_write <= x"000000000";
-			ddr_req <= '0';
-			ddr_req_adr <= "00000000000000000000000";
-			ddr_rd_wr_n <= '0';
-			ddr_req_len <= '0';
-			break_out <= '0';
-			refresh_en <= '0';
-			
-			wait until falling_edge(areset);
-			
-			-- DDR initialization sequence
-				-- Wait more than 200 us
-				wait for 201000 ns;	
-				
-				-- Send precharge command
-				wait until rising_edge(cpu_clk);	
-				ddr_command <= x"8000";
-				ddr_command_we <= '1';
-				wait until rising_edge(cpu_clk);
-				ddr_command <= x"0000";
-				ddr_command_we <= '0';
-				
-				-- Wait for 1 us
-				wait for 1000 ns;
-				
-				-- Load extended mode register
-				--  Enable DLL
-				--  Normal drive strength
-				wait until rising_edge(cpu_clk);	
-				ddr_command <= x"2000";
-				ddr_command_we <= '1';
-				wait until rising_edge(cpu_clk);
-				ddr_command <= x"0000";
-				ddr_command_we <= '0';
-							
-				-- Wait for 1 us
-				wait for 1000 ns;
-				
-				-- Load mode register
-				--  Burst length: 2
-				--  Burst type: Sequential
-				--  Cas latency: 2
-				--  Reset DLL
-				wait until rising_edge(cpu_clk);	
-				ddr_command <= x"0121";
-				ddr_command_we <= '1';
-				wait until rising_edge(cpu_clk);
-				ddr_command <= x"0000";
-				ddr_command_we <= '0';
-							
-				-- Wait for 1 us
-				wait for 1000 ns;
-				
-				-- Send precharge command
-				wait until rising_edge(cpu_clk);	
-				ddr_command <= x"8000";
-				ddr_command_we <= '1';
-				wait until rising_edge(cpu_clk);
-				ddr_command <= x"0000";
-				ddr_command_we <= '0';
-				
-				-- Enable refresh
-				refresh_en <= '1';
-			
-				-- Wait 30 us (minimum 2 autorefresh cycles)
-				wait for 30000 ns;
-						
-				-- Load mode register
-				--  Burst length: 2
-				--  Burst type: Sequential
-				--  Cas latency: 2
-				--  Deactivate Reset DLL
-				wait until rising_edge(cpu_clk);	
-				ddr_command <= x"0021";
-				ddr_command_we <= '1';
-				wait until rising_edge(cpu_clk);
-				ddr_command <= x"0000";
-				ddr_command_we <= '0';
-	
-				-- Wait for 2 us (DLL stable)
-				wait for 2000 ns;
-				
-			-- Write data to DDR
-			wait until rising_edge(cpu_clk_2x);
-			ddr_data_write <= x"312345678";
-			ddr_req <= '1';
-			ddr_req_adr <= "00000000000000000000000";
-			ddr_rd_wr_n <= '0';
-			ddr_req_len <= '0';
-			wait until rising_edge(ddr_write_en);
-			wait until rising_edge(cpu_clk_2x);
-			ddr_req <= '0';
-			ddr_req_adr <= "00000000000000000000000";
-			ddr_rd_wr_n <= '0';
-			ddr_req_len <= '0';
-			ddr_data_write <= x"000000000";
-			wait for 100 ns;
-			
-			-- Read data from DDR
-			wait until rising_edge(cpu_clk_2x);
-			ddr_req <= '1';
-			ddr_req_adr <= "00000000000000000000000";
-			ddr_rd_wr_n <= '1';
-			ddr_req_len <= '0';
-			wait until rising_edge(ddr_req_ack);
-			wait until rising_edge(cpu_clk_2x);
-			ddr_req <= '0';
-			ddr_req_adr <= "00000000000000000000000";
-			ddr_rd_wr_n <= '0';
-			ddr_req_len <= '0';
-			ddr_data_write <= x"000000000";
-
-
-
-			wait for 100 ns;
-			break_out <= '1';
-			wait for 100 ns;
-						
-		end loop;
-		
-	end process;
-	
-	ddr_ctrl:
-	ddr_top port map(
-		areset => areset,
-		cpu_clk => cpu_clk,
-		cpu_clk_2x => cpu_clk_2x,
-		cpu_clk_4x => cpu_clk_4x,
-		ddr_in_clk => ddr_in_clk,
-		ddr_in_clk_2x => ddr_in_clk_2x,
-		
-		-- Command interface
-		ddr_command => ddr_command,
-		ddr_command_we => ddr_command_we,
-		refresh_en => refresh_en,			
-		
-		-- Data interface signals
-		ddr_data_read => ddr_data_read,
-		ddr_data_write => ddr_data_write,
-		ddr_req_adr => ddr_req_adr,
-		ddr_req => ddr_req,
-		ddr_req_ack => ddr_req_ack,
-		ddr_busy => ddr_busy,
-		ddr_rd_wr_n => ddr_rd_wr_n,
-		ddr_req_len => ddr_req_len,
-		ddr_read_en => ddr_read_en,
-		ddr_write_en => ddr_write_en,
-		    -- DDR SDRAM Signals
-	    sdr_clk_p => sdr_clk_p,
-	    sdr_clk_n_p => sdr_clk_n_p,
-	    cke_q_p => cke_q_p,
-	    cs_qn_p => cs_qn_p,
-	    ras_qn_p => ras_qn_p,
-	    cas_qn_p => cas_qn_p,
-	    we_qn_p => we_qn_p,
-	    dm_q_p => dm_q_p,
-	    dqs_q_p => dqs_q_p,
-	    ba_q_p => ba_q_p,
-	    sdr_a_p => sdr_a_p,
-	    sdr_d_p => sdr_d_p);
-	   
-	myram:
-	MT46V16M16 generic map(
-        tCK => 7.500 ns,
-        tCH => 3.375 ns,       -- 0.45*tCK
-        tCL => 3.375 ns,       -- 0.45*tCK
-        tDH => 0.500 ns,
-        tDS => 0.500 ns,
-        tIH => 0.900 ns,
-        tIS => 0.900 ns,
-        tMRD => 15.000 ns,
-        tRAS => 40.000 ns,
-        tRAP => 20.000 ns,
-        tRC => 65.000 ns,
-        tRFC => 75.000 ns,
-        tRCD => 20.000 ns,
-        tRP => 20.000 ns,
-        tRRD => 15.000 ns,
-        tWR => 15.000 ns,
-        addr_bits => 13,
-        data_bits => 16,
-        cols_bits => 9)
-    port map(
-        Dq => sdr_d_p,
-        Dqs => dqs_q_p,
-        Addr => sdr_a_p,
-        Ba => ba_q_p,
-        Clk => sdr_clk_p,
-        Clk_n => sdr_clk_n_p,
-        Cke => cke_q_p,
-        Cs_n => cs_qn_p,
-        Ras_n => ras_qn_p,
-        Cas_n => cas_qn_p,
-        We_n => we_qn_p,
-        Dm => dm_q_p);
-
-end behave;
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library work;
+use work.ddr.all;
+
+entity ddr_tb is
+	port (	areset			: in std_logic;
+			break_out		: out std_logic);
+end ddr_tb;
+
+architecture behave of ddr_tb is
+
+signal	cpu_clk			: std_logic;
+signal	cpu_clk_2x		: std_logic;
+signal	cpu_clk_4x		: std_logic;
+signal	ddr_in_clk		: std_logic;
+signal	ddr_in_clk_2x	: std_logic;
+
+signal	ddr_command		: std_logic_vector(15 downto 0);
+signal	ddr_command_we	: std_logic;
+			
+signal	ddr_data_read	: std_logic_vector(31 downto 0);	-- Data read from DDR SDRAM
+signal	ddr_data_write	: std_logic_vector(35 downto 0);		-- Data to be written to DDR SDRAM
+signal	ddr_req_adr		: std_logic_vector(23 downto 1);		-- Request address
+signal	ddr_req			: std_logic;							-- Request DDR SDRAM access
+signal	ddr_req_ack		: std_logic;							-- Request acknowledge
+signal	ddr_busy		: std_logic;							-- Request acknowledge
+signal	ddr_rd_wr_n		: std_logic;							-- Access type 1=READ, 0=WRITE
+signal	ddr_req_len		: std_logic;							-- Number of 16-bits words to transfer
+signal	ddr_read_en		: std_logic;						-- Enable signal for read data
+signal	ddr_write_en	: std_logic;						-- Enable (read) signal for data write
+signal	refresh_en		: std_logic;
+
+signal	sdr_clk_p       : std_logic;    -- ddr_sdram_clock
+signal	sdr_clk_n_p     : std_logic;    -- /ddr_sdram_clock
+signal	cke_q_p         : std_logic;    -- clock enable
+signal	cs_qn_p         : std_logic;    -- /chip select
+signal	ras_qn_p        : std_logic;    -- /ras
+signal	cas_qn_p        : std_logic;    -- /cas
+signal	we_qn_p         : std_logic;    -- /write enable
+signal	dm_q_p          : std_logic_vector(1 downto 0);     -- data mask bits, set to "00"
+signal	dqs_q_p         : std_logic_vector(1 downto 0);    -- data strobe, only for write
+signal	ba_q_p          : std_logic_vector(1 downto 0);   -- bank select
+signal	sdr_a_p		    : std_logic_vector(12 downto 0);   -- address bus 
+signal	sdr_d_p         : std_logic_vector(15 downto 0); 			-- bidir data bus
+
+constant min_time	: time := 1.875 ns;
+
+begin
+
+	clock1:
+	process
+	begin
+		loop
+			cpu_clk_4x <= '1';
+			wait for min_time;
+			cpu_clk_4x <= '0';
+			wait for min_time;
+		end loop;
+	end process;
+
+	clock2:
+	process
+	begin
+		loop
+			cpu_clk_2x <= '1' after 100 ps;
+			wait until rising_edge(cpu_clk_4x);
+			cpu_clk_2x <= '0' after 100 ps;
+			wait until rising_edge(cpu_clk_4x);
+		end loop;
+	end process;
+
+	clock3:
+	process
+	begin
+		loop
+			cpu_clk <= '1' after 100 ps;
+			wait until rising_edge(cpu_clk_2x);
+			cpu_clk <= '0' after 100 ps;
+			wait until rising_edge(cpu_clk_2x);
+		end loop;
+	end process;
+	
+	ddr_in_clk_2x <= cpu_clk_4x after 1 ns;
+
+	clock4:
+	process
+	begin
+		loop
+			ddr_in_clk <= '0' after 100 ps;
+			wait until rising_edge(ddr_in_clk_2x);
+			ddr_in_clk <= '1' after 100 ps;
+			wait until rising_edge(ddr_in_clk_2x);
+		end loop;
+	end process;
+	
+	inputdata:
+	process
+	begin
+		-- Wait until global reset released
+		loop
+			ddr_command <= x"0000";
+			ddr_command_we <= '0';
+			ddr_data_write <= x"000000000";
+			ddr_req <= '0';
+			ddr_req_adr <= "00000000000000000000000";
+			ddr_rd_wr_n <= '0';
+			ddr_req_len <= '0';
+			break_out <= '0';
+			refresh_en <= '0';
+			
+			wait until falling_edge(areset);
+			
+			-- DDR initialization sequence
+				-- Wait more than 200 us
+				wait for 201000 ns;	
+				
+				-- Send precharge command
+				wait until rising_edge(cpu_clk);	
+				ddr_command <= x"8000";
+				ddr_command_we <= '1';
+				wait until rising_edge(cpu_clk);
+				ddr_command <= x"0000";
+				ddr_command_we <= '0';
+				
+				-- Wait for 1 us
+				wait for 1000 ns;
+				
+				-- Load extended mode register
+				--  Enable DLL
+				--  Normal drive strength
+				wait until rising_edge(cpu_clk);	
+				ddr_command <= x"2000";
+				ddr_command_we <= '1';
+				wait until rising_edge(cpu_clk);
+				ddr_command <= x"0000";
+				ddr_command_we <= '0';
+							
+				-- Wait for 1 us
+				wait for 1000 ns;
+				
+				-- Load mode register
+				--  Burst length: 2
+				--  Burst type: Sequential
+				--  Cas latency: 2
+				--  Reset DLL
+				wait until rising_edge(cpu_clk);	
+				ddr_command <= x"0121";
+				ddr_command_we <= '1';
+				wait until rising_edge(cpu_clk);
+				ddr_command <= x"0000";
+				ddr_command_we <= '0';
+							
+				-- Wait for 1 us
+				wait for 1000 ns;
+				
+				-- Send precharge command
+				wait until rising_edge(cpu_clk);	
+				ddr_command <= x"8000";
+				ddr_command_we <= '1';
+				wait until rising_edge(cpu_clk);
+				ddr_command <= x"0000";
+				ddr_command_we <= '0';
+				
+				-- Enable refresh
+				refresh_en <= '1';
+			
+				-- Wait 30 us (minimum 2 autorefresh cycles)
+				wait for 30000 ns;
+						
+				-- Load mode register
+				--  Burst length: 2
+				--  Burst type: Sequential
+				--  Cas latency: 2
+				--  Deactivate Reset DLL
+				wait until rising_edge(cpu_clk);	
+				ddr_command <= x"0021";
+				ddr_command_we <= '1';
+				wait until rising_edge(cpu_clk);
+				ddr_command <= x"0000";
+				ddr_command_we <= '0';
+	
+				-- Wait for 2 us (DLL stable)
+				wait for 2000 ns;
+				
+			-- Write data to DDR
+			wait until rising_edge(cpu_clk_2x);
+			ddr_data_write <= x"312345678";
+			ddr_req <= '1';
+			ddr_req_adr <= "00000000000000000000000";
+			ddr_rd_wr_n <= '0';
+			ddr_req_len <= '0';
+			wait until rising_edge(ddr_write_en);
+			wait until rising_edge(cpu_clk_2x);
+			ddr_req <= '0';
+			ddr_req_adr <= "00000000000000000000000";
+			ddr_rd_wr_n <= '0';
+			ddr_req_len <= '0';
+			ddr_data_write <= x"000000000";
+			wait for 100 ns;
+			
+			-- Read data from DDR
+			wait until rising_edge(cpu_clk_2x);
+			ddr_req <= '1';
+			ddr_req_adr <= "00000000000000000000000";
+			ddr_rd_wr_n <= '1';
+			ddr_req_len <= '0';
+			wait until rising_edge(ddr_req_ack);
+			wait until rising_edge(cpu_clk_2x);
+			ddr_req <= '0';
+			ddr_req_adr <= "00000000000000000000000";
+			ddr_rd_wr_n <= '0';
+			ddr_req_len <= '0';
+			ddr_data_write <= x"000000000";
+
+
+
+			wait for 100 ns;
+			break_out <= '1';
+			wait for 100 ns;
+						
+		end loop;
+		
+	end process;
+	
+	ddr_ctrl:
+	ddr_top port map(
+		areset => areset,
+		cpu_clk => cpu_clk,
+		cpu_clk_2x => cpu_clk_2x,
+		cpu_clk_4x => cpu_clk_4x,
+		ddr_in_clk => ddr_in_clk,
+		ddr_in_clk_2x => ddr_in_clk_2x,
+		
+		-- Command interface
+		ddr_command => ddr_command,
+		ddr_command_we => ddr_command_we,
+		refresh_en => refresh_en,			
+		
+		-- Data interface signals
+		ddr_data_read => ddr_data_read,
+		ddr_data_write => ddr_data_write,
+		ddr_req_adr => ddr_req_adr,
+		ddr_req => ddr_req,
+		ddr_req_ack => ddr_req_ack,
+		ddr_busy => ddr_busy,
+		ddr_rd_wr_n => ddr_rd_wr_n,
+		ddr_req_len => ddr_req_len,
+		ddr_read_en => ddr_read_en,
+		ddr_write_en => ddr_write_en,
+		    -- DDR SDRAM Signals
+	    sdr_clk_p => sdr_clk_p,
+	    sdr_clk_n_p => sdr_clk_n_p,
+	    cke_q_p => cke_q_p,
+	    cs_qn_p => cs_qn_p,
+	    ras_qn_p => ras_qn_p,
+	    cas_qn_p => cas_qn_p,
+	    we_qn_p => we_qn_p,
+	    dm_q_p => dm_q_p,
+	    dqs_q_p => dqs_q_p,
+	    ba_q_p => ba_q_p,
+	    sdr_a_p => sdr_a_p,
+	    sdr_d_p => sdr_d_p);
+	   
+	myram:
+	MT46V16M16 generic map(
+        tCK => 7.500 ns,
+        tCH => 3.375 ns,       -- 0.45*tCK
+        tCL => 3.375 ns,       -- 0.45*tCK
+        tDH => 0.500 ns,
+        tDS => 0.500 ns,
+        tIH => 0.900 ns,
+        tIS => 0.900 ns,
+        tMRD => 15.000 ns,
+        tRAS => 40.000 ns,
+        tRAP => 20.000 ns,
+        tRC => 65.000 ns,
+        tRFC => 75.000 ns,
+        tRCD => 20.000 ns,
+        tRP => 20.000 ns,
+        tRRD => 15.000 ns,
+        tWR => 15.000 ns,
+        addr_bits => 13,
+        data_bits => 16,
+        cols_bits => 9)
+    port map(
+        Dq => sdr_d_p,
+        Dqs => dqs_q_p,
+        Addr => sdr_a_p,
+        Ba => ba_q_p,
+        Clk => sdr_clk_p,
+        Clk_n => sdr_clk_n_p,
+        Cke => cke_q_p,
+        Cs_n => cs_qn_p,
+        Ras_n => ras_qn_p,
+        Cas_n => cas_qn_p,
+        We_n => we_qn_p,
+        Dm => dm_q_p);
+
+end behave;
diff --git a/misc/ddrsdram/src/ddr_pkg.vhd b/misc/ddrsdram/src/ddr_pkg.vhd
index 0e41a88..af4a705 100644
--- a/misc/ddrsdram/src/ddr_pkg.vhd
+++ b/misc/ddrsdram/src/ddr_pkg.vhd
@@ -1,107 +1,107 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-package ddr is
-
-	function mirror_bus32 ( org_sig  : std_logic_vector) return std_logic_vector;
-	function mirror_bus4 ( org_sig  : std_logic_vector) return std_logic_vector;
-
-	component ddr_top
-	generic(
-			simulate_io_time	: boolean := false);
-	port (	-- Asyncronous reset and clocks
-			areset			: in std_logic;
-			cpu_clk			: in std_logic;
-			cpu_clk_2x		: in std_logic;
-			cpu_clk_4x		: in std_logic;
-			ddr_in_clk		: in std_logic;
-			ddr_in_clk_2x	: in std_logic;
-			
-			-- Command interface
-			ddr_command		: in std_logic_vector(15 downto 0);
-			ddr_command_we	: in std_logic;
-			refresh_en		: in std_logic;
-			
-			
-			-- Data interface signals
-			ddr_data_read	: out std_logic_vector(31 downto 0);	-- Data read from DDR SDRAM
-			ddr_data_write	: in std_logic_vector(35 downto 0);		-- Data to be written to DDR SDRAM
-			ddr_req_adr		: in std_logic_vector(25 downto 1);		-- Request address
-			ddr_req			: in std_logic;							-- Request DDR SDRAM access
-			ddr_busy		: out std_logic;							-- Request acknowledge
-			ddr_rd_wr_n		: in std_logic;							-- Access type 1=READ, 0=WRITE
-			ddr_req_len		: in std_logic;							-- Number of 16-bits words to transfer (0=2, 1=8)
-			ddr_read_en		: out std_logic;						-- Enable signal for read data
-			ddr_write_en	: out std_logic;						-- Enable (read) signal for data write
-
-		    -- DDR SDRAM Signals
-		    sdr_clk_p       : out std_logic;    -- ddr_sdram_clock
-		    sdr_clk_n_p     : out std_logic;    -- /ddr_sdram_clock
-		    cke_q_p         : out std_logic;    -- clock enable
-		    cs_qn_p         : out std_logic;    -- /chip select
-		    ras_qn_p        : inout std_logic;    -- /ras
-		    cas_qn_p        : inout std_logic;    -- /cas
-		    we_qn_p         : inout std_logic;    -- /write enable
-		    dm_q_p          : out std_logic_vector(1 downto 0);     -- data mask bits, set to "00"
-		    dqs_q_p         : out std_logic_vector(1 downto 0);    -- data strobe, only for write
-		    ba_q_p          : out std_logic_vector(1 downto 0);   -- bank select
-		    sdr_a_p		    : out std_logic_vector(12 downto 0);   -- address bus 
-		    sdr_d_p         : inout std_logic_vector(15 downto 0)); 			-- bidir data bus
-	end component;
-	
-	component MT46V16M16
-    GENERIC (                                   -- Timing for -75Z CL2
-        tCK       : TIME    :=  7.500 ns;
-        tCH       : TIME    :=  3.375 ns;       -- 0.45*tCK
-        tCL       : TIME    :=  3.375 ns;       -- 0.45*tCK
-        tDH       : TIME    :=  0.500 ns;
-        tDS       : TIME    :=  0.500 ns;
-        tIH       : TIME    :=  0.900 ns;
-        tIS       : TIME    :=  0.900 ns;
-        tMRD      : TIME    := 15.000 ns;
-        tRAS      : TIME    := 40.000 ns;
-        tRAP      : TIME    := 20.000 ns;
-        tRC       : TIME    := 65.000 ns;
-        tRFC      : TIME    := 75.000 ns;
-        tRCD      : TIME    := 20.000 ns;
-        tRP       : TIME    := 20.000 ns;
-        tRRD      : TIME    := 15.000 ns;
-        tWR       : TIME    := 15.000 ns;
-        addr_bits : INTEGER := 13;
-        data_bits : INTEGER := 16;
-        cols_bits : INTEGER :=  9
-    );
-    PORT (
-        Dq    : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
-        Dqs   : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
-        Addr  : IN    STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
-        Ba    : IN    STD_LOGIC_VECTOR (1 DOWNTO 0);
-        Clk   : IN    STD_LOGIC;
-        Clk_n : IN    STD_LOGIC;
-        Cke   : IN    STD_LOGIC;
-        Cs_n  : IN    STD_LOGIC;
-        Ras_n : IN    STD_LOGIC;
-        Cas_n : IN    STD_LOGIC;
-        We_n  : IN    STD_LOGIC;
-        Dm    : IN    STD_LOGIC_VECTOR (1 DOWNTO 0)
-    );
-	end component;
-	
-end;
-
-package body ddr is
-
-	function mirror_bus32 ( org_sig  : std_logic_vector) return std_logic_vector is
-	begin
-		return (org_sig(7 downto 0) & org_sig(15 downto 8) & org_sig(23 downto 16) & org_sig(31 downto 24));
-	end function mirror_bus32;
-
-	function mirror_bus4 ( org_sig  : std_logic_vector) return std_logic_vector is
-	begin
-		return (org_sig(0) & org_sig(1) & org_sig(2) & org_sig(3));
-	end function mirror_bus4;
-
-end package body;
-
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+package ddr is
+
+	function mirror_bus32 ( org_sig  : std_logic_vector) return std_logic_vector;
+	function mirror_bus4 ( org_sig  : std_logic_vector) return std_logic_vector;
+
+	component ddr_top
+	generic(
+			simulate_io_time	: boolean := false);
+	port (	-- Asyncronous reset and clocks
+			areset			: in std_logic;
+			cpu_clk			: in std_logic;
+			cpu_clk_2x		: in std_logic;
+			cpu_clk_4x		: in std_logic;
+			ddr_in_clk		: in std_logic;
+			ddr_in_clk_2x	: in std_logic;
+			
+			-- Command interface
+			ddr_command		: in std_logic_vector(15 downto 0);
+			ddr_command_we	: in std_logic;
+			refresh_en		: in std_logic;
+			
+			
+			-- Data interface signals
+			ddr_data_read	: out std_logic_vector(31 downto 0);	-- Data read from DDR SDRAM
+			ddr_data_write	: in std_logic_vector(35 downto 0);		-- Data to be written to DDR SDRAM
+			ddr_req_adr		: in std_logic_vector(25 downto 1);		-- Request address
+			ddr_req			: in std_logic;							-- Request DDR SDRAM access
+			ddr_busy		: out std_logic;							-- Request acknowledge
+			ddr_rd_wr_n		: in std_logic;							-- Access type 1=READ, 0=WRITE
+			ddr_req_len		: in std_logic;							-- Number of 16-bits words to transfer (0=2, 1=8)
+			ddr_read_en		: out std_logic;						-- Enable signal for read data
+			ddr_write_en	: out std_logic;						-- Enable (read) signal for data write
+
+		    -- DDR SDRAM Signals
+		    sdr_clk_p       : out std_logic;    -- ddr_sdram_clock
+		    sdr_clk_n_p     : out std_logic;    -- /ddr_sdram_clock
+		    cke_q_p         : out std_logic;    -- clock enable
+		    cs_qn_p         : out std_logic;    -- /chip select
+		    ras_qn_p        : inout std_logic;    -- /ras
+		    cas_qn_p        : inout std_logic;    -- /cas
+		    we_qn_p         : inout std_logic;    -- /write enable
+		    dm_q_p          : out std_logic_vector(1 downto 0);     -- data mask bits, set to "00"
+		    dqs_q_p         : out std_logic_vector(1 downto 0);    -- data strobe, only for write
+		    ba_q_p          : out std_logic_vector(1 downto 0);   -- bank select
+		    sdr_a_p		    : out std_logic_vector(12 downto 0);   -- address bus 
+		    sdr_d_p         : inout std_logic_vector(15 downto 0)); 			-- bidir data bus
+	end component;
+	
+	component MT46V16M16
+    GENERIC (                                   -- Timing for -75Z CL2
+        tCK       : TIME    :=  7.500 ns;
+        tCH       : TIME    :=  3.375 ns;       -- 0.45*tCK
+        tCL       : TIME    :=  3.375 ns;       -- 0.45*tCK
+        tDH       : TIME    :=  0.500 ns;
+        tDS       : TIME    :=  0.500 ns;
+        tIH       : TIME    :=  0.900 ns;
+        tIS       : TIME    :=  0.900 ns;
+        tMRD      : TIME    := 15.000 ns;
+        tRAS      : TIME    := 40.000 ns;
+        tRAP      : TIME    := 20.000 ns;
+        tRC       : TIME    := 65.000 ns;
+        tRFC      : TIME    := 75.000 ns;
+        tRCD      : TIME    := 20.000 ns;
+        tRP       : TIME    := 20.000 ns;
+        tRRD      : TIME    := 15.000 ns;
+        tWR       : TIME    := 15.000 ns;
+        addr_bits : INTEGER := 13;
+        data_bits : INTEGER := 16;
+        cols_bits : INTEGER :=  9
+    );
+    PORT (
+        Dq    : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
+        Dqs   : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
+        Addr  : IN    STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
+        Ba    : IN    STD_LOGIC_VECTOR (1 DOWNTO 0);
+        Clk   : IN    STD_LOGIC;
+        Clk_n : IN    STD_LOGIC;
+        Cke   : IN    STD_LOGIC;
+        Cs_n  : IN    STD_LOGIC;
+        Ras_n : IN    STD_LOGIC;
+        Cas_n : IN    STD_LOGIC;
+        We_n  : IN    STD_LOGIC;
+        Dm    : IN    STD_LOGIC_VECTOR (1 DOWNTO 0)
+    );
+	end component;
+	
+end;
+
+package body ddr is
+
+	function mirror_bus32 ( org_sig  : std_logic_vector) return std_logic_vector is
+	begin
+		return (org_sig(7 downto 0) & org_sig(15 downto 8) & org_sig(23 downto 16) & org_sig(31 downto 24));
+	end function mirror_bus32;
+
+	function mirror_bus4 ( org_sig  : std_logic_vector) return std_logic_vector is
+	begin
+		return (org_sig(0) & org_sig(1) & org_sig(2) & org_sig(3));
+	end function mirror_bus4;
+
+end package body;
+
 	
\ No newline at end of file
diff --git a/misc/ddrsdram/src/ddr_top.vhd b/misc/ddrsdram/src/ddr_top.vhd
index 033e9f8..2aceae9 100644
--- a/misc/ddrsdram/src/ddr_top.vhd
+++ b/misc/ddrsdram/src/ddr_top.vhd
@@ -1,743 +1,743 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library UNISIM;
-use UNISIM.vcomponents.all;
-
-entity ddr_top is
-	generic(
-			simulate_io_time	: boolean := false);
-	port (	-- Asyncronous reset and clocks
-			areset			: in std_logic;
-			cpu_clk			: in std_logic;
-			cpu_clk_2x		: in std_logic;
-			cpu_clk_4x		: in std_logic;
-			ddr_in_clk		: in std_logic;
-			ddr_in_clk_2x	: in std_logic;
-			
-			-- Command interface
-			ddr_command		: in std_logic_vector(15 downto 0);
-			ddr_command_we	: in std_logic;
-			refresh_en		: in std_logic;
-			
-			-- Data interface signals
-			ddr_data_read	: out std_logic_vector(31 downto 0);	-- Data read from DDR SDRAM
-			ddr_data_write	: in std_logic_vector(35 downto 0);		-- Data to be written to DDR SDRAM
-			ddr_req_adr		: in std_logic_vector(25 downto 1);		-- Request address
-			ddr_req			: in std_logic;							-- Request DDR SDRAM access
-			ddr_busy		: out std_logic;							-- Request acknowledge
-			ddr_rd_wr_n		: in std_logic;							-- Access type 1=READ, 0=WRITE
-			ddr_req_len		: in std_logic;							-- Number of 16-bits words to transfer (0=2, 1=8)
-			ddr_read_en		: out std_logic;						-- Enable signal for read data
-			ddr_write_en	: out std_logic;						-- Enable (read) signal for data write
-
-		    -- DDR SDRAM Signals
-		    sdr_clk_p       : out std_logic;    -- ddr_sdram_clock
-		    sdr_clk_n_p     : out std_logic;    -- /ddr_sdram_clock
-		    cke_q_p         : out std_logic;    -- clock enable
-		    cs_qn_p         : out std_logic;    -- /chip select
-		    ras_qn_p        : inout std_logic;    -- /ras
-		    cas_qn_p        : inout std_logic;    -- /cas
-		    we_qn_p         : inout std_logic;    -- /write enable
-		    dm_q_p          : out std_logic_vector(1 downto 0);     -- data mask bits, set to "00"
-		    dqs_q_p         : out std_logic_vector(1 downto 0);    -- data strobe, only for write
-		    ba_q_p          : out std_logic_vector(1 downto 0);   -- bank select
-		    sdr_a_p		    : out std_logic_vector(12 downto 0);   -- address bus 
-		    sdr_d_p         : inout std_logic_vector(15 downto 0)); 			-- bidir data bus
-end ddr_top;
-
-architecture behave of ddr_top is
-
-attribute keep : string;
-
-type	clk4_type			is array(0 to 15) of std_logic_vector(1 downto 0);
-
-signal	cpu_clk_tog			: std_logic;
-signal	ddr_cmd				: std_logic_vector(15 downto 0);
-signal	ddr_cmd_we_smp		: std_logic;
-signal	new_command			: std_logic;
-
-signal	cpu_clk_2x_smp1		: std_logic;		
-signal	cpu_clk_2x_smp2		: std_logic;		
-signal	cpu_clk_4x_smp1		: std_logic;		
-signal	cpu_clk_4x_smp2		: std_logic;
-
-signal	clk2_phase			: std_logic;	
-signal	clk4_phase			: std_logic_vector(3 downto 0);
-signal	clk4_phase_short	: clk4_type;
-attribute keep of clk4_phase_short:signal is "true";
-
-signal	ddr_clk_tog			: std_logic;
-signal	ddr_clk_smp1		: std_logic;
-signal	ddr_clk_smp2		: std_logic;
-signal	ddr_clk_phase		: std_logic;
-
-signal	smp_req_adr			: std_logic_vector(25 downto 1);
-signal	smp_req_type		: std_logic;
-signal	smp_req_len			: std_logic;
-signal	ddr_write_en_int	: std_logic;
-signal	ddr_read_en_int		: std_logic;
-
-signal	dqs_q				: std_logic_vector(1 downto 0);
-signal	dqs_oe_n			: std_logic_vector(1 downto 0);
-attribute keep of dqs_oe_n:signal is "true";
-signal	cas_qn				: std_logic;
-signal	ras_qn				: std_logic;
-signal	we_qn				: std_logic;
-signal	ba_q				: std_logic_vector(1 downto 0);
-signal	sdr_clk				: std_logic;
-signal	sdr_clk_n			: std_logic;
-signal	sdr_a				: std_logic_vector(12 downto 0);
-signal	sdr_d				: std_logic_vector(15 downto 0);
-signal	sdr_smp				: std_logic_vector(35 downto 0);
-signal	sdr_oe_n			: std_logic_vector(15 downto 0);
-attribute keep of sdr_oe_n:signal is "true";
-signal	sdr_oe_ctrl			: std_logic_vector(15 downto 0);
-attribute keep of sdr_oe_ctrl:signal is "true";
-signal	sdr_wr_msw			: std_logic_vector(17 downto 0);
-attribute keep of sdr_wr_msw:signal is "true";
-signal	dm_q				: std_logic_vector(1 downto 0);
-
-signal  nowin_idle_dqs      : std_logic_vector(1 downto 0);
-signal  nowin_wr_nop1_d     : std_logic_vector(15 downto 0);
-signal  nowin_wr_nop1_dqs   : std_logic_vector(1 downto 0);
-signal  nowin_wr_nop1_dm    : std_logic_vector(1 downto 0);
-signal  nowin_wr_nop2_dqs   : std_logic_vector(1 downto 0);
-signal  nowin_wr_nop3_d     : std_logic_vector(15 downto 0);
-signal  nowin_wr_nop3_dqs   : std_logic_vector(1 downto 0);
-attribute keep of nowin_idle_dqs:signal is "true";
-attribute keep of nowin_wr_nop1_d:signal is "true";
-attribute keep of nowin_wr_nop1_dqs:signal is "true";
-attribute keep of nowin_wr_nop1_dm:signal is "true";
-attribute keep of nowin_wr_nop2_dqs:signal is "true";
-attribute keep of nowin_wr_nop3_d:signal is "true";
-attribute keep of nowin_wr_nop3_dqs:signal is "true";
-
-signal	cas_n_smp			: std_logic;
-signal	ras_n_smp			: std_logic;
-signal	we_n_smp			: std_logic;
-signal	read_start_sig		: std_logic;
-signal	sdr_d_in			: std_logic_vector(15 downto 0);
-signal	read_time_cnt		: std_logic_vector(1 downto 0);
-signal	read_input_en		: std_logic;
-signal	read_input_en_del	: std_logic;
-signal	ddr_data_read_int	: std_logic_vector(31 downto 0);
-
-signal	refresh_pend		: std_logic;
-signal	refresh_end			: std_logic;
-signal	refresh_cnt			: std_logic_vector(9 downto 0);
-signal	refresh_wait_cnt	: std_logic_vector(3 downto 0);
-signal	refresh_wait_end	: std_logic;
-
-signal	cas_qn_p_del		: std_logic;
-signal	ras_qn_p_del		: std_logic;
-signal	we_qn_p_del			: std_logic;
-signal	sdr_d_p_del			: std_logic_vector(15 downto 0);
-
-signal	saved_row			: std_logic_vector(26 downto 11);
-signal	operation			: std_logic_vector(1 downto 0);
-
-signal	ddr_req_adr_int		: std_logic_vector(25 downto 1);
-
-type state_type is (idle, act, act_nop1, act_nop2, rd_wr, rd_nop1, 
-					rd_nop2,rd_nop3,rd_nop4, rd_nop5,pre, pre_nop1, pre_nop2, wr_nop1, wr_nop2, 
-					wr_nop3, cmd, cpu_pre, refresh, refresh_wait);
-signal	ddr_state			: state_type;
-
-constant	Clk_to_Output	: time := 2.2 ns;
-constant	Input_Setup	: time := 2.5 ns;
-
-constant	Refresh_Interval	: std_logic_vector(9 downto 0) := "1111100110";
-
-begin
-
-	iotimingon:
-	if simulate_io_time generate
-	begin
-		cas_qn_p_del <= 'X' after 0 ns, cas_qn_p after Input_Setup;
-		ras_qn_p_del <= 'X' after 0 ns, ras_qn_p after Input_Setup;
-		we_qn_p_del <= 'X' after 0 ns, we_qn_p after Input_Setup;
-		sdr_d_p_del <= "XXXXXXXXXXXXXXXX" after 0 ns, sdr_d_p after Input_Setup;
-	end generate;
-	
-	iotimingoff:
-	if not simulate_io_time generate
-	begin
-		cas_qn_p_del <= cas_qn_p;
-		ras_qn_p_del <= ras_qn_p;
-		we_qn_p_del <= we_qn_p;
-		sdr_d_p_del <= sdr_d_p;
-	end generate;
-	
-	ddr_write_en <= ddr_write_en_int;
-	ddr_read_en <= ddr_read_en_int;
-	ddr_data_read <= ddr_data_read_int;
-	
-	ddr_req_adr_int <= (ddr_req_adr(24 downto 10) & '0' & ddr_req_adr(9 downto 1)) when (simulate_io_time) else ddr_req_adr;
-
-	process(cpu_clk, areset)	-- Toggle a flip-flop with cpu_clk, in order 
-	begin						-- to find phase relation with 2x and 4x clocks
-		if areset = '1' then
-			cpu_clk_tog <= '0';
-		elsif (cpu_clk'event and cpu_clk = '1') then
-			cpu_clk_tog <= not(cpu_clk_tog);
-		end if;
-	end process;
-	
-	process(cpu_clk_2x, areset)	-- Find phase relation between cpu_clk and cpu_clk_2x
-	begin
-		if areset = '1' then
-			cpu_clk_2x_smp1 <= '0';
-			cpu_clk_2x_smp2 <= '0';
-			clk2_phase <= '0';
-		elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
-			cpu_clk_2x_smp1 <= cpu_clk_tog;
-			cpu_clk_2x_smp2 <= cpu_clk_2x_smp1;
-			if (cpu_clk_2x_smp1 = '1' and cpu_clk_2x_smp2 = '0') then
-				clk2_phase <= '0';
-			else
-				clk2_phase <= not(clk2_phase);
-			end if;
-		end if;
-	end process;
-	
-	process(cpu_clk_4x, areset)	-- Find phase relation between cpu_clk and cpu_clk_4x
-	begin
-		if areset = '1' then
-			cpu_clk_4x_smp1 <= '0';
-			cpu_clk_4x_smp2 <= '0';
-			clk4_phase <= "0000";
-			clk4_phase_short(0) <= "00";
-			clk4_phase_short(1) <= "00";
-			clk4_phase_short(2) <= "00";
-			clk4_phase_short(3) <= "00";
-			clk4_phase_short(4) <= "00";
-			clk4_phase_short(5) <= "00";
-			clk4_phase_short(6) <= "00";
-			clk4_phase_short(7) <= "00";
-			clk4_phase_short(8) <= "00";
-			clk4_phase_short(9) <= "00";
-			clk4_phase_short(10) <= "00";
-			clk4_phase_short(11) <= "00";
-			clk4_phase_short(12) <= "00";
-			clk4_phase_short(13) <= "00";
-			clk4_phase_short(14) <= "00";
-			clk4_phase_short(15) <= "00";
-		elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then
-			cpu_clk_4x_smp1 <= cpu_clk_tog;
-			cpu_clk_4x_smp2 <= cpu_clk_4x_smp1;
-			for i in 0 to 15 loop
-				if (cpu_clk_4x_smp1 = '1' and cpu_clk_4x_smp2 = '0') then
-					clk4_phase <= "0100";
-					clk4_phase_short(i) <= "01";
-				else
-					clk4_phase <= (clk4_phase(2 downto 0) & clk4_phase(3));
-					clk4_phase_short(i) <= clk4_phase_short(i)(0) & clk4_phase_short(i)(1);
-				end if;
-			end loop;
-		end if;
-	end process;
-
-	process(cpu_clk_4x, areset)	--
-	begin
-		if areset = '1' then
-			sdr_clk <= '0';			
-			sdr_clk_n <= '0';			
-		elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then
-			if clk4_phase_short(0)(0) = '1' then
-				sdr_clk <= '1';
-			else
-				sdr_clk <= '0';
-			end if;
-			if clk4_phase_short(0)(1) = '1' then
-				sdr_clk_n <= '1';
-			else
-				sdr_clk_n <= '0';
-			end if;
-		end if;
-	end process;
-	
-    cke_q_p <= '1' after Clk_to_Output;
-    cs_qn_p <= '0' after Clk_to_Output;
-	
-	process(cpu_clk_4x, areset)	--
-	begin
-		if areset = '1' then
-		    ras_qn_p <= '1';
-		    cas_qn_p <= '1';
-		    we_qn_p <= '1';
-		    dqs_q_p <= "ZZ";
-		    sdr_a_p <= "0000000000000";
-			ba_q_p <= "00";
-			sdr_clk_p <= '0';
-			sdr_clk_n_p <= '1';
-		elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then
-		    ras_qn_p <= transport ras_qn after Clk_to_Output;
-		    cas_qn_p <= transport cas_qn after Clk_to_Output;
-		    we_qn_p <= transport we_qn after Clk_to_Output;
-		    if dqs_oe_n(0) = '0' then
-		    	dqs_q_p(0) <= transport dqs_q(0) after Clk_to_Output;
-		    else
-		    	dqs_q_p(0) <= transport 'Z' after Clk_to_Output;
-		    end if;
-		    if dqs_oe_n(1) = '0' then
-		    	dqs_q_p(1) <= transport dqs_q(1) after Clk_to_Output;
-		    else
-		    	dqs_q_p(1) <= transport 'Z' after Clk_to_Output;
-		    end if;
-		    sdr_a_p <= transport sdr_a after Clk_to_Output;
-		    ba_q_p <= transport ba_q after Clk_to_Output;
-		    sdr_clk_p <= transport sdr_clk after Clk_to_Output;
-		    sdr_clk_n_p <= transport sdr_clk_n after Clk_to_Output;
-		end if;
-	end process;
-	
-	process(cpu_clk_2x, areset)	--
-	begin
-		if areset = '1' then
-			ddr_state <= idle;
-			ras_qn <= '1';
-			cas_qn <= '1';
-			we_qn <= '1';
-			smp_req_adr <= (others => '0');
-			smp_req_type <= '0';
-			smp_req_len <= '0';
-			sdr_a <= "XXXXXXXXXXXXX";
-			ba_q <= "00";
-			ddr_busy <= '1';
-			saved_row <= "1000000000000000";
-			ddr_write_en_int <= '0';
-			ddr_read_en_int <= '0';
-			nowin_idle_dqs <= "11";
-			nowin_wr_nop1_d <= "0000000000000000";
-			nowin_wr_nop1_dqs <= "00";
-			nowin_wr_nop1_dm <= "00";
-			nowin_wr_nop2_dqs <= "00";
-			nowin_wr_nop3_d <= "0000000000000000";
-			nowin_wr_nop3_dqs <= "00";
-		elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
-		
-			-- Default values
-			ras_qn <= '1';
-			cas_qn <= '1';
-			we_qn <= '1';
-			sdr_a <= "XXXXXXXXXXXXX";
-			ddr_busy <= '1';
-			ddr_write_en_int <= '0';
-			ddr_read_en_int <= '0';
-
-			nowin_idle_dqs <= "00";
-			nowin_wr_nop1_d <= "0000000000000000";
-			nowin_wr_nop1_dqs <= "00";
-			nowin_wr_nop1_dm <= "00";
-			nowin_wr_nop2_dqs <= "00";
-			nowin_wr_nop3_d <= "0000000000000000";
-			nowin_wr_nop3_dqs <= "00";
-		
-			case ddr_state is
-				when idle =>
-					smp_req_adr <= ddr_req_adr_int;
-					smp_req_type <= ddr_rd_wr_n;
-					smp_req_len <= ddr_req_len;
-					ddr_busy <= '0';
-					operation <= "00";
-					if refresh_pend = '1' then
-						operation <= "01";
-						ddr_state <= pre;
-					elsif new_command = '1' then
-						if ddr_cmd(15) = '1' then
-							operation <= "10";
-							ddr_state <= cpu_pre;
-						else
-							ddr_state <= cmd;
-						end if;
-					elsif (ddr_req = '1' and ddr_req_adr_int(25 downto 11) = saved_row(25 downto 11) and saved_row(26) = '0') then
-						operation <= "11";
-						ddr_write_en_int <= not(ddr_rd_wr_n);
-						ddr_state <= rd_wr;
-					elsif ddr_req = '1' then
-						operation <= "11";
-						ddr_state <= pre;
-					else
-						ddr_state <= idle;
-						nowin_idle_dqs <= "11";
-					end if;
-				when act =>
-					sdr_a <= smp_req_adr(23 downto 11);
-					ba_q <= smp_req_adr(25 downto 24);
-					ras_qn <= '0';
-					ddr_write_en_int <= not(smp_req_type);
-					ddr_state <= act_nop1;
-				when act_nop1 =>
-					ddr_state <= act_nop2;
-				when act_nop2 =>
-					ddr_state <= rd_wr;
-				when rd_wr =>
-					sdr_a(10) <= '0';		-- Disable auto precharge
-					sdr_a(9 downto 0) <= smp_req_adr(10 downto 1);
-					ba_q <= smp_req_adr(25 downto 24);
-					saved_row <= '0' & smp_req_adr(25 downto 11);
-					cas_qn <= '0';
-					we_qn <= smp_req_type;
-					if smp_req_type = '1' then
-						ddr_state <= rd_nop1;
-					else
-						ddr_state <= wr_nop1;
-						nowin_wr_nop1_d <= "1111111111111111";
-						nowin_wr_nop1_dqs <= "11";
-						nowin_wr_nop1_dm <= "11";
-					end if;
-				when wr_nop1 =>
-					ddr_state <= wr_nop2;	
-					nowin_wr_nop2_dqs <= "11";
-				when wr_nop2 =>
-					ddr_state <= wr_nop3;
-					nowin_wr_nop3_d <= "1111111111111111";
-					nowin_wr_nop3_dqs <= "11";
-				when wr_nop3 =>
-					nowin_idle_dqs <= "11";
-					ddr_state <= idle;
-				when rd_nop1 =>
-					ddr_state <= rd_nop2;
-				when rd_nop2 =>
-					if operation /= "11" then
-						nowin_idle_dqs <= "11";
-						ddr_state <= idle;
-					else
-						ddr_state <= rd_nop3;
-					end if;
-				when rd_nop3 =>
-					ddr_state <= rd_nop4;
-				when rd_nop4 =>
-					ddr_read_en_int <= '1';
-					ddr_state <= rd_nop5;
-				when rd_nop5 =>
-					nowin_idle_dqs <= "11";
-					ddr_state <= idle;
-				when pre =>					
-					ras_qn <= '0';
-					we_qn <= '0';
-					sdr_a(10) <= '1';	-- Precharge all banks
-					ba_q <= smp_req_adr(25 downto 24);
-					ddr_state <= pre_nop1;
-				when pre_nop1 =>
-					ddr_state <= pre_nop2;
-				when cmd =>
-					cas_qn <= '0';
-					ras_qn <= '0';
-					we_qn <= '0';
-					ba_q <= ddr_cmd(14 downto 13);
-					sdr_a <= ddr_cmd(12 downto 0);
-					nowin_idle_dqs <= "11";
-					ddr_state <= idle;
-				when cpu_pre =>
-					ddr_state <= pre;
-				when refresh =>
-					cas_qn <= '0';
-					ras_qn <= '0';
-					saved_row(26) <= '1';
-					ddr_state <= refresh_wait;
-				when refresh_wait =>
-					if refresh_wait_end = '1' then
-						ddr_state <= pre_nop2;
-					end if;
-				when pre_nop2 =>
-					if operation = "01" then
-						operation <= "10";
-						ddr_state <= refresh;
-					elsif operation = "10" then
-						nowin_idle_dqs <= "11";
-						ddr_state <= idle;
-					else
-						ddr_state <= act;
-					end if;
-				when others =>
-					ddr_state <= idle;
-					nowin_idle_dqs <= "11";
-			end case;
-		end if;
-	end process;
-	
-	process(cpu_clk, areset)	--
-	begin
-		if areset = '1' then
-			ddr_cmd <= "0000000000000000";
-		elsif (cpu_clk'event and cpu_clk = '1') then
-			if ddr_command_we = '1' then
-				ddr_cmd <= ddr_command;
-			else
-				ddr_cmd <= ddr_cmd;
-			end if;
-		end if;
-	end process;
-	
-	process(cpu_clk_2x, areset)	--
-	begin
-		if areset = '1' then
-			ddr_cmd_we_smp <= '0';
-			new_command <= '0';
-			sdr_smp <= "000000000000000000000000000000000000";
-		elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
-			ddr_cmd_we_smp <= ddr_command_we;
-			if ddr_command_we = '0' and ddr_cmd_we_smp = '1' then
-				new_command <= '1';
-			elsif ddr_state = cmd or ddr_state = cpu_pre then
-				new_command <= '0';
-			else
-				new_command <= new_command;
-			end if;
-			
-			if ddr_write_en_int = '1' then
-			   	sdr_smp <= ddr_data_write;
-			else
-				sdr_smp <= sdr_smp;
-			end if;
-			
-		end if;
-	end process;
-	
-	process(cpu_clk_4x, areset)	--
-	begin
-		if areset = '1' then
-			dqs_q <= "00";
-			dqs_oe_n <= "11";
-			sdr_oe_ctrl <= "1111111111111111";
-			sdr_wr_msw <= "000000000000000000";
-		elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then
-		
-			for i in 0 to 15 loop
-				if nowin_wr_nop1_d(i) = '1' and clk4_phase_short(i)(0) = '1' then
-					sdr_oe_ctrl(i) <= '0';
-				elsif nowin_wr_nop3_d(i) = '1' and clk4_phase_short(i)(0) = '1' then
-					sdr_oe_ctrl(i) <= '1';
-				end if;
-			end loop;
-		
-			for i in 0 to 1 loop
-				if nowin_idle_dqs(i) = '1' or nowin_wr_nop3_dqs(i) = '1' then
-					dqs_oe_n(i) <= '1';
-				elsif nowin_wr_nop1_dqs(i) = '1' then
-					dqs_oe_n(i)  <= '0';
-				end if;
-			end loop;
-
-			for i in 0 to 1 loop
-				if (nowin_wr_nop2_dqs(i) = '1' and clk4_phase_short(i)(0) = '1') then
-					dqs_q(i) <= '1';
-				else
-					dqs_q(i) <= '0';
-				end if;
-			end loop;
-
-			for i in 0 to 15 loop
-				if nowin_wr_nop1_d(i) = '1' and clk4_phase_short(i)(1) = '1' then
-					sdr_wr_msw(i) <= '1';
-				else
-					sdr_wr_msw(i) <= '0';
-				end if;
-			end loop;
-			
-			for i in 0 to 1 loop
-				if nowin_wr_nop1_dm(i) = '1' and clk4_phase_short(i)(1) = '1' then
-					sdr_wr_msw(i+16) <= '1';
-				else
-					sdr_wr_msw(i+16) <= '0';
-				end if;
-			end loop;
-
-		end if;
-	end process;
-	
-	-- NOTE! DATA OUTPUT PATH. CLOCKED ON FALLING 4X CLOCK
-	process(cpu_clk_4x, areset)	--
-	begin
-		if areset = '1' then
-		    sdr_d_p <= "ZZZZZZZZZZZZZZZZ";
-		    dm_q_p <= "11";
-		    sdr_oe_n <= "1111111111111111";
-		    sdr_d <= "0000000000000000";
-		    dm_q <= "11";
-		elsif (cpu_clk_4x'event and cpu_clk_4x = '0') then
-
-			for i in 0 to 15 loop
-				if sdr_oe_n(i) = '0' then
-					sdr_d_p(i) <= transport sdr_d(i) after Clk_to_Output;
-				else
-					sdr_d_p(i) <= transport 'Z' after Clk_to_Output;
-				end if;
-		   	end loop;			
-
-			dm_q_p <= transport dm_q after Clk_to_Output;
-
-			for i in 0 to 15 loop
-				if sdr_oe_ctrl(i) = '0' then
-					sdr_oe_n(i) <= '0';
-				else
-					sdr_oe_n(i) <= '1';
-				end if;
-			end loop;
-			
-			for i in 0 to 15 loop
-				if sdr_wr_msw(i) = '1' then
-		   			sdr_d(i) <= sdr_smp(i);
-		   		else
-	   				sdr_d(i) <= sdr_smp(i+16);
-	   			end if;
-		   	end loop;
-		   	
-			for i in 0 to 1 loop
-				if sdr_wr_msw(i+16) = '1' then
-		   			dm_q(i) <= sdr_smp(i+32);
-		   		else
-		   			dm_q(i) <= sdr_smp(i+34);
-		   		end if;
-		   	end loop;
-		   	
-		end if;
-	end process;
-	
-	process(cpu_clk_2x, areset)	--
-	begin
-		if areset = '1' then
-			refresh_cnt <= "0000000000";
-			refresh_pend <= '0';
-			refresh_end <= '0';
-			refresh_wait_cnt <= "0000";
-			refresh_wait_end <= '0';
-		elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
-		
-			if refresh_cnt = Refresh_Interval then
-				refresh_end <= '1';
-			else
-				refresh_end <= '0';
-			end if;
-			
-			if refresh_end = '1' then
-				refresh_cnt <= "0000000000";
-			else
-				refresh_cnt <= refresh_cnt + '1';
-			end if;
-			
-			if refresh_end = '1' and refresh_en = '1' then
-				refresh_pend <= '1';
-			elsif ddr_state = refresh then
-				refresh_pend <= '0';
-			else
-				refresh_pend <= refresh_pend;
-			end if;
-			
-			if ddr_state = refresh_wait then
-				refresh_wait_cnt <= refresh_wait_cnt + '1';
-			else
-				refresh_wait_cnt <= "0000";
-			end if;
-			
-			if refresh_wait_cnt = "1011" then
-				refresh_wait_end <= '1';
-			else
-				refresh_wait_end <= '0';
-			end if;
-			
-		end if;
-	end process;
-	
-	-- 911. THIS IS A DUMMY FOR FGPA IMPEMENTATION TESTING
-
-	process(ddr_in_clk, areset)
-	begin
-		if areset = '1' then
-			ddr_clk_tog <= '0';
-		elsif (ddr_in_clk'event and ddr_in_clk = '1') then
-			ddr_clk_tog <= not(ddr_clk_tog);
-		end if;
-	end process;	
-	
-	process(ddr_in_clk_2x, areset)
-	begin
-		if areset = '1' then
-			ddr_clk_smp1 <= '0';
-			ddr_clk_smp2 <= '0';
-			ddr_clk_phase <= '0';
-		elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then
-			ddr_clk_smp1 <= ddr_clk_tog;
-			ddr_clk_smp2 <= ddr_clk_smp1;
-			if ddr_clk_smp1 = '1' and ddr_clk_smp2 = '0' then
-				ddr_clk_phase <= '0';
-			else
-				ddr_clk_phase <= not(ddr_clk_phase);
-			end if;
-		end if;
-	end process;
-
-	process(ddr_in_clk_2x, areset)
-	begin
-		if areset = '1' then
-			cas_n_smp <= '0';
-			ras_n_smp <= '0';
-			we_n_smp <= '0';
-			read_start_sig <= '0';
-		elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then
-			cas_n_smp <= cas_qn_p_del;
-			ras_n_smp <= ras_qn_p_del;
-			we_n_smp <= we_qn_p_del;
-			if ras_n_smp = '1' and cas_n_smp = '0' and we_n_smp = '1' and ddr_clk_phase = '1' then
-				read_start_sig <= '1';
-			else
-				read_start_sig <= '0';
-			end if;
-		end if;
-	end process;
-
-	process(ddr_in_clk_2x, areset)
-	begin
-		if areset = '1' then
-			sdr_d_in <= "0000000000000000";
-		elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then
-			sdr_d_in <= sdr_d_p_del;
-		end if;
-	end process;
-	
-	process(ddr_in_clk_2x, areset)
-	begin
-		if areset = '1' then
-			read_time_cnt <= "00";
-			read_input_en <= '0';
-		elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then
-
-			if read_start_sig = '1' then	
-				read_time_cnt <= "01";
-			elsif read_time_cnt = "00" then
-				read_time_cnt <= read_time_cnt;
-			else
-				read_time_cnt <= read_time_cnt + '1';
-			end if;
-
-			if read_time_cnt = "11" then
-				read_input_en <= '1';
-			else
-				read_input_en <= '0';
-			end if;
-			
-			read_input_en_del <= read_input_en;
-
-		end if;
-	end process;
-	
-	process(ddr_in_clk_2x, areset)
-	begin
-		if areset = '1' then
-			ddr_data_read_int <= "00000000000000000000000000000000";
-		elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then
-			if read_input_en = '1' then
-				ddr_data_read_int(15 downto 0) <= sdr_d_in;
-			end if;
-			if read_input_en_del = '1' then
-				ddr_data_read_int(31 downto 16) <= sdr_d_in;
-			end if;
-		end if;
-	end process;
-
-end behave;
-
-
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity ddr_top is
+	generic(
+			simulate_io_time	: boolean := false);
+	port (	-- Asyncronous reset and clocks
+			areset			: in std_logic;
+			cpu_clk			: in std_logic;
+			cpu_clk_2x		: in std_logic;
+			cpu_clk_4x		: in std_logic;
+			ddr_in_clk		: in std_logic;
+			ddr_in_clk_2x	: in std_logic;
+			
+			-- Command interface
+			ddr_command		: in std_logic_vector(15 downto 0);
+			ddr_command_we	: in std_logic;
+			refresh_en		: in std_logic;
+			
+			-- Data interface signals
+			ddr_data_read	: out std_logic_vector(31 downto 0);	-- Data read from DDR SDRAM
+			ddr_data_write	: in std_logic_vector(35 downto 0);		-- Data to be written to DDR SDRAM
+			ddr_req_adr		: in std_logic_vector(25 downto 1);		-- Request address
+			ddr_req			: in std_logic;							-- Request DDR SDRAM access
+			ddr_busy		: out std_logic;							-- Request acknowledge
+			ddr_rd_wr_n		: in std_logic;							-- Access type 1=READ, 0=WRITE
+			ddr_req_len		: in std_logic;							-- Number of 16-bits words to transfer (0=2, 1=8)
+			ddr_read_en		: out std_logic;						-- Enable signal for read data
+			ddr_write_en	: out std_logic;						-- Enable (read) signal for data write
+
+		    -- DDR SDRAM Signals
+		    sdr_clk_p       : out std_logic;    -- ddr_sdram_clock
+		    sdr_clk_n_p     : out std_logic;    -- /ddr_sdram_clock
+		    cke_q_p         : out std_logic;    -- clock enable
+		    cs_qn_p         : out std_logic;    -- /chip select
+		    ras_qn_p        : inout std_logic;    -- /ras
+		    cas_qn_p        : inout std_logic;    -- /cas
+		    we_qn_p         : inout std_logic;    -- /write enable
+		    dm_q_p          : out std_logic_vector(1 downto 0);     -- data mask bits, set to "00"
+		    dqs_q_p         : out std_logic_vector(1 downto 0);    -- data strobe, only for write
+		    ba_q_p          : out std_logic_vector(1 downto 0);   -- bank select
+		    sdr_a_p		    : out std_logic_vector(12 downto 0);   -- address bus 
+		    sdr_d_p         : inout std_logic_vector(15 downto 0)); 			-- bidir data bus
+end ddr_top;
+
+architecture behave of ddr_top is
+
+attribute keep : string;
+
+type	clk4_type			is array(0 to 15) of std_logic_vector(1 downto 0);
+
+signal	cpu_clk_tog			: std_logic;
+signal	ddr_cmd				: std_logic_vector(15 downto 0);
+signal	ddr_cmd_we_smp		: std_logic;
+signal	new_command			: std_logic;
+
+signal	cpu_clk_2x_smp1		: std_logic;		
+signal	cpu_clk_2x_smp2		: std_logic;		
+signal	cpu_clk_4x_smp1		: std_logic;		
+signal	cpu_clk_4x_smp2		: std_logic;
+
+signal	clk2_phase			: std_logic;	
+signal	clk4_phase			: std_logic_vector(3 downto 0);
+signal	clk4_phase_short	: clk4_type;
+attribute keep of clk4_phase_short:signal is "true";
+
+signal	ddr_clk_tog			: std_logic;
+signal	ddr_clk_smp1		: std_logic;
+signal	ddr_clk_smp2		: std_logic;
+signal	ddr_clk_phase		: std_logic;
+
+signal	smp_req_adr			: std_logic_vector(25 downto 1);
+signal	smp_req_type		: std_logic;
+signal	smp_req_len			: std_logic;
+signal	ddr_write_en_int	: std_logic;
+signal	ddr_read_en_int		: std_logic;
+
+signal	dqs_q				: std_logic_vector(1 downto 0);
+signal	dqs_oe_n			: std_logic_vector(1 downto 0);
+attribute keep of dqs_oe_n:signal is "true";
+signal	cas_qn				: std_logic;
+signal	ras_qn				: std_logic;
+signal	we_qn				: std_logic;
+signal	ba_q				: std_logic_vector(1 downto 0);
+signal	sdr_clk				: std_logic;
+signal	sdr_clk_n			: std_logic;
+signal	sdr_a				: std_logic_vector(12 downto 0);
+signal	sdr_d				: std_logic_vector(15 downto 0);
+signal	sdr_smp				: std_logic_vector(35 downto 0);
+signal	sdr_oe_n			: std_logic_vector(15 downto 0);
+attribute keep of sdr_oe_n:signal is "true";
+signal	sdr_oe_ctrl			: std_logic_vector(15 downto 0);
+attribute keep of sdr_oe_ctrl:signal is "true";
+signal	sdr_wr_msw			: std_logic_vector(17 downto 0);
+attribute keep of sdr_wr_msw:signal is "true";
+signal	dm_q				: std_logic_vector(1 downto 0);
+
+signal  nowin_idle_dqs      : std_logic_vector(1 downto 0);
+signal  nowin_wr_nop1_d     : std_logic_vector(15 downto 0);
+signal  nowin_wr_nop1_dqs   : std_logic_vector(1 downto 0);
+signal  nowin_wr_nop1_dm    : std_logic_vector(1 downto 0);
+signal  nowin_wr_nop2_dqs   : std_logic_vector(1 downto 0);
+signal  nowin_wr_nop3_d     : std_logic_vector(15 downto 0);
+signal  nowin_wr_nop3_dqs   : std_logic_vector(1 downto 0);
+attribute keep of nowin_idle_dqs:signal is "true";
+attribute keep of nowin_wr_nop1_d:signal is "true";
+attribute keep of nowin_wr_nop1_dqs:signal is "true";
+attribute keep of nowin_wr_nop1_dm:signal is "true";
+attribute keep of nowin_wr_nop2_dqs:signal is "true";
+attribute keep of nowin_wr_nop3_d:signal is "true";
+attribute keep of nowin_wr_nop3_dqs:signal is "true";
+
+signal	cas_n_smp			: std_logic;
+signal	ras_n_smp			: std_logic;
+signal	we_n_smp			: std_logic;
+signal	read_start_sig		: std_logic;
+signal	sdr_d_in			: std_logic_vector(15 downto 0);
+signal	read_time_cnt		: std_logic_vector(1 downto 0);
+signal	read_input_en		: std_logic;
+signal	read_input_en_del	: std_logic;
+signal	ddr_data_read_int	: std_logic_vector(31 downto 0);
+
+signal	refresh_pend		: std_logic;
+signal	refresh_end			: std_logic;
+signal	refresh_cnt			: std_logic_vector(9 downto 0);
+signal	refresh_wait_cnt	: std_logic_vector(3 downto 0);
+signal	refresh_wait_end	: std_logic;
+
+signal	cas_qn_p_del		: std_logic;
+signal	ras_qn_p_del		: std_logic;
+signal	we_qn_p_del			: std_logic;
+signal	sdr_d_p_del			: std_logic_vector(15 downto 0);
+
+signal	saved_row			: std_logic_vector(26 downto 11);
+signal	operation			: std_logic_vector(1 downto 0);
+
+signal	ddr_req_adr_int		: std_logic_vector(25 downto 1);
+
+type state_type is (idle, act, act_nop1, act_nop2, rd_wr, rd_nop1, 
+					rd_nop2,rd_nop3,rd_nop4, rd_nop5,pre, pre_nop1, pre_nop2, wr_nop1, wr_nop2, 
+					wr_nop3, cmd, cpu_pre, refresh, refresh_wait);
+signal	ddr_state			: state_type;
+
+constant	Clk_to_Output	: time := 2.2 ns;
+constant	Input_Setup	: time := 2.5 ns;
+
+constant	Refresh_Interval	: std_logic_vector(9 downto 0) := "1111100110";
+
+begin
+
+	iotimingon:
+	if simulate_io_time generate
+	begin
+		cas_qn_p_del <= 'X' after 0 ns, cas_qn_p after Input_Setup;
+		ras_qn_p_del <= 'X' after 0 ns, ras_qn_p after Input_Setup;
+		we_qn_p_del <= 'X' after 0 ns, we_qn_p after Input_Setup;
+		sdr_d_p_del <= "XXXXXXXXXXXXXXXX" after 0 ns, sdr_d_p after Input_Setup;
+	end generate;
+	
+	iotimingoff:
+	if not simulate_io_time generate
+	begin
+		cas_qn_p_del <= cas_qn_p;
+		ras_qn_p_del <= ras_qn_p;
+		we_qn_p_del <= we_qn_p;
+		sdr_d_p_del <= sdr_d_p;
+	end generate;
+	
+	ddr_write_en <= ddr_write_en_int;
+	ddr_read_en <= ddr_read_en_int;
+	ddr_data_read <= ddr_data_read_int;
+	
+	ddr_req_adr_int <= (ddr_req_adr(24 downto 10) & '0' & ddr_req_adr(9 downto 1)) when (simulate_io_time) else ddr_req_adr;
+
+	process(cpu_clk, areset)	-- Toggle a flip-flop with cpu_clk, in order 
+	begin						-- to find phase relation with 2x and 4x clocks
+		if areset = '1' then
+			cpu_clk_tog <= '0';
+		elsif (cpu_clk'event and cpu_clk = '1') then
+			cpu_clk_tog <= not(cpu_clk_tog);
+		end if;
+	end process;
+	
+	process(cpu_clk_2x, areset)	-- Find phase relation between cpu_clk and cpu_clk_2x
+	begin
+		if areset = '1' then
+			cpu_clk_2x_smp1 <= '0';
+			cpu_clk_2x_smp2 <= '0';
+			clk2_phase <= '0';
+		elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
+			cpu_clk_2x_smp1 <= cpu_clk_tog;
+			cpu_clk_2x_smp2 <= cpu_clk_2x_smp1;
+			if (cpu_clk_2x_smp1 = '1' and cpu_clk_2x_smp2 = '0') then
+				clk2_phase <= '0';
+			else
+				clk2_phase <= not(clk2_phase);
+			end if;
+		end if;
+	end process;
+	
+	process(cpu_clk_4x, areset)	-- Find phase relation between cpu_clk and cpu_clk_4x
+	begin
+		if areset = '1' then
+			cpu_clk_4x_smp1 <= '0';
+			cpu_clk_4x_smp2 <= '0';
+			clk4_phase <= "0000";
+			clk4_phase_short(0) <= "00";
+			clk4_phase_short(1) <= "00";
+			clk4_phase_short(2) <= "00";
+			clk4_phase_short(3) <= "00";
+			clk4_phase_short(4) <= "00";
+			clk4_phase_short(5) <= "00";
+			clk4_phase_short(6) <= "00";
+			clk4_phase_short(7) <= "00";
+			clk4_phase_short(8) <= "00";
+			clk4_phase_short(9) <= "00";
+			clk4_phase_short(10) <= "00";
+			clk4_phase_short(11) <= "00";
+			clk4_phase_short(12) <= "00";
+			clk4_phase_short(13) <= "00";
+			clk4_phase_short(14) <= "00";
+			clk4_phase_short(15) <= "00";
+		elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then
+			cpu_clk_4x_smp1 <= cpu_clk_tog;
+			cpu_clk_4x_smp2 <= cpu_clk_4x_smp1;
+			for i in 0 to 15 loop
+				if (cpu_clk_4x_smp1 = '1' and cpu_clk_4x_smp2 = '0') then
+					clk4_phase <= "0100";
+					clk4_phase_short(i) <= "01";
+				else
+					clk4_phase <= (clk4_phase(2 downto 0) & clk4_phase(3));
+					clk4_phase_short(i) <= clk4_phase_short(i)(0) & clk4_phase_short(i)(1);
+				end if;
+			end loop;
+		end if;
+	end process;
+
+	process(cpu_clk_4x, areset)	--
+	begin
+		if areset = '1' then
+			sdr_clk <= '0';			
+			sdr_clk_n <= '0';			
+		elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then
+			if clk4_phase_short(0)(0) = '1' then
+				sdr_clk <= '1';
+			else
+				sdr_clk <= '0';
+			end if;
+			if clk4_phase_short(0)(1) = '1' then
+				sdr_clk_n <= '1';
+			else
+				sdr_clk_n <= '0';
+			end if;
+		end if;
+	end process;
+	
+    cke_q_p <= '1' after Clk_to_Output;
+    cs_qn_p <= '0' after Clk_to_Output;
+	
+	process(cpu_clk_4x, areset)	--
+	begin
+		if areset = '1' then
+		    ras_qn_p <= '1';
+		    cas_qn_p <= '1';
+		    we_qn_p <= '1';
+		    dqs_q_p <= "ZZ";
+		    sdr_a_p <= "0000000000000";
+			ba_q_p <= "00";
+			sdr_clk_p <= '0';
+			sdr_clk_n_p <= '1';
+		elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then
+		    ras_qn_p <= transport ras_qn after Clk_to_Output;
+		    cas_qn_p <= transport cas_qn after Clk_to_Output;
+		    we_qn_p <= transport we_qn after Clk_to_Output;
+		    if dqs_oe_n(0) = '0' then
+		    	dqs_q_p(0) <= transport dqs_q(0) after Clk_to_Output;
+		    else
+		    	dqs_q_p(0) <= transport 'Z' after Clk_to_Output;
+		    end if;
+		    if dqs_oe_n(1) = '0' then
+		    	dqs_q_p(1) <= transport dqs_q(1) after Clk_to_Output;
+		    else
+		    	dqs_q_p(1) <= transport 'Z' after Clk_to_Output;
+		    end if;
+		    sdr_a_p <= transport sdr_a after Clk_to_Output;
+		    ba_q_p <= transport ba_q after Clk_to_Output;
+		    sdr_clk_p <= transport sdr_clk after Clk_to_Output;
+		    sdr_clk_n_p <= transport sdr_clk_n after Clk_to_Output;
+		end if;
+	end process;
+	
+	process(cpu_clk_2x, areset)	--
+	begin
+		if areset = '1' then
+			ddr_state <= idle;
+			ras_qn <= '1';
+			cas_qn <= '1';
+			we_qn <= '1';
+			smp_req_adr <= (others => '0');
+			smp_req_type <= '0';
+			smp_req_len <= '0';
+			sdr_a <= "XXXXXXXXXXXXX";
+			ba_q <= "00";
+			ddr_busy <= '1';
+			saved_row <= "1000000000000000";
+			ddr_write_en_int <= '0';
+			ddr_read_en_int <= '0';
+			nowin_idle_dqs <= "11";
+			nowin_wr_nop1_d <= "0000000000000000";
+			nowin_wr_nop1_dqs <= "00";
+			nowin_wr_nop1_dm <= "00";
+			nowin_wr_nop2_dqs <= "00";
+			nowin_wr_nop3_d <= "0000000000000000";
+			nowin_wr_nop3_dqs <= "00";
+		elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
+		
+			-- Default values
+			ras_qn <= '1';
+			cas_qn <= '1';
+			we_qn <= '1';
+			sdr_a <= "XXXXXXXXXXXXX";
+			ddr_busy <= '1';
+			ddr_write_en_int <= '0';
+			ddr_read_en_int <= '0';
+
+			nowin_idle_dqs <= "00";
+			nowin_wr_nop1_d <= "0000000000000000";
+			nowin_wr_nop1_dqs <= "00";
+			nowin_wr_nop1_dm <= "00";
+			nowin_wr_nop2_dqs <= "00";
+			nowin_wr_nop3_d <= "0000000000000000";
+			nowin_wr_nop3_dqs <= "00";
+		
+			case ddr_state is
+				when idle =>
+					smp_req_adr <= ddr_req_adr_int;
+					smp_req_type <= ddr_rd_wr_n;
+					smp_req_len <= ddr_req_len;
+					ddr_busy <= '0';
+					operation <= "00";
+					if refresh_pend = '1' then
+						operation <= "01";
+						ddr_state <= pre;
+					elsif new_command = '1' then
+						if ddr_cmd(15) = '1' then
+							operation <= "10";
+							ddr_state <= cpu_pre;
+						else
+							ddr_state <= cmd;
+						end if;
+					elsif (ddr_req = '1' and ddr_req_adr_int(25 downto 11) = saved_row(25 downto 11) and saved_row(26) = '0') then
+						operation <= "11";
+						ddr_write_en_int <= not(ddr_rd_wr_n);
+						ddr_state <= rd_wr;
+					elsif ddr_req = '1' then
+						operation <= "11";
+						ddr_state <= pre;
+					else
+						ddr_state <= idle;
+						nowin_idle_dqs <= "11";
+					end if;
+				when act =>
+					sdr_a <= smp_req_adr(23 downto 11);
+					ba_q <= smp_req_adr(25 downto 24);
+					ras_qn <= '0';
+					ddr_write_en_int <= not(smp_req_type);
+					ddr_state <= act_nop1;
+				when act_nop1 =>
+					ddr_state <= act_nop2;
+				when act_nop2 =>
+					ddr_state <= rd_wr;
+				when rd_wr =>
+					sdr_a(10) <= '0';		-- Disable auto precharge
+					sdr_a(9 downto 0) <= smp_req_adr(10 downto 1);
+					ba_q <= smp_req_adr(25 downto 24);
+					saved_row <= '0' & smp_req_adr(25 downto 11);
+					cas_qn <= '0';
+					we_qn <= smp_req_type;
+					if smp_req_type = '1' then
+						ddr_state <= rd_nop1;
+					else
+						ddr_state <= wr_nop1;
+						nowin_wr_nop1_d <= "1111111111111111";
+						nowin_wr_nop1_dqs <= "11";
+						nowin_wr_nop1_dm <= "11";
+					end if;
+				when wr_nop1 =>
+					ddr_state <= wr_nop2;	
+					nowin_wr_nop2_dqs <= "11";
+				when wr_nop2 =>
+					ddr_state <= wr_nop3;
+					nowin_wr_nop3_d <= "1111111111111111";
+					nowin_wr_nop3_dqs <= "11";
+				when wr_nop3 =>
+					nowin_idle_dqs <= "11";
+					ddr_state <= idle;
+				when rd_nop1 =>
+					ddr_state <= rd_nop2;
+				when rd_nop2 =>
+					if operation /= "11" then
+						nowin_idle_dqs <= "11";
+						ddr_state <= idle;
+					else
+						ddr_state <= rd_nop3;
+					end if;
+				when rd_nop3 =>
+					ddr_state <= rd_nop4;
+				when rd_nop4 =>
+					ddr_read_en_int <= '1';
+					ddr_state <= rd_nop5;
+				when rd_nop5 =>
+					nowin_idle_dqs <= "11";
+					ddr_state <= idle;
+				when pre =>					
+					ras_qn <= '0';
+					we_qn <= '0';
+					sdr_a(10) <= '1';	-- Precharge all banks
+					ba_q <= smp_req_adr(25 downto 24);
+					ddr_state <= pre_nop1;
+				when pre_nop1 =>
+					ddr_state <= pre_nop2;
+				when cmd =>
+					cas_qn <= '0';
+					ras_qn <= '0';
+					we_qn <= '0';
+					ba_q <= ddr_cmd(14 downto 13);
+					sdr_a <= ddr_cmd(12 downto 0);
+					nowin_idle_dqs <= "11";
+					ddr_state <= idle;
+				when cpu_pre =>
+					ddr_state <= pre;
+				when refresh =>
+					cas_qn <= '0';
+					ras_qn <= '0';
+					saved_row(26) <= '1';
+					ddr_state <= refresh_wait;
+				when refresh_wait =>
+					if refresh_wait_end = '1' then
+						ddr_state <= pre_nop2;
+					end if;
+				when pre_nop2 =>
+					if operation = "01" then
+						operation <= "10";
+						ddr_state <= refresh;
+					elsif operation = "10" then
+						nowin_idle_dqs <= "11";
+						ddr_state <= idle;
+					else
+						ddr_state <= act;
+					end if;
+				when others =>
+					ddr_state <= idle;
+					nowin_idle_dqs <= "11";
+			end case;
+		end if;
+	end process;
+	
+	process(cpu_clk, areset)	--
+	begin
+		if areset = '1' then
+			ddr_cmd <= "0000000000000000";
+		elsif (cpu_clk'event and cpu_clk = '1') then
+			if ddr_command_we = '1' then
+				ddr_cmd <= ddr_command;
+			else
+				ddr_cmd <= ddr_cmd;
+			end if;
+		end if;
+	end process;
+	
+	process(cpu_clk_2x, areset)	--
+	begin
+		if areset = '1' then
+			ddr_cmd_we_smp <= '0';
+			new_command <= '0';
+			sdr_smp <= "000000000000000000000000000000000000";
+		elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
+			ddr_cmd_we_smp <= ddr_command_we;
+			if ddr_command_we = '0' and ddr_cmd_we_smp = '1' then
+				new_command <= '1';
+			elsif ddr_state = cmd or ddr_state = cpu_pre then
+				new_command <= '0';
+			else
+				new_command <= new_command;
+			end if;
+			
+			if ddr_write_en_int = '1' then
+			   	sdr_smp <= ddr_data_write;
+			else
+				sdr_smp <= sdr_smp;
+			end if;
+			
+		end if;
+	end process;
+	
+	process(cpu_clk_4x, areset)	--
+	begin
+		if areset = '1' then
+			dqs_q <= "00";
+			dqs_oe_n <= "11";
+			sdr_oe_ctrl <= "1111111111111111";
+			sdr_wr_msw <= "000000000000000000";
+		elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then
+		
+			for i in 0 to 15 loop
+				if nowin_wr_nop1_d(i) = '1' and clk4_phase_short(i)(0) = '1' then
+					sdr_oe_ctrl(i) <= '0';
+				elsif nowin_wr_nop3_d(i) = '1' and clk4_phase_short(i)(0) = '1' then
+					sdr_oe_ctrl(i) <= '1';
+				end if;
+			end loop;
+		
+			for i in 0 to 1 loop
+				if nowin_idle_dqs(i) = '1' or nowin_wr_nop3_dqs(i) = '1' then
+					dqs_oe_n(i) <= '1';
+				elsif nowin_wr_nop1_dqs(i) = '1' then
+					dqs_oe_n(i)  <= '0';
+				end if;
+			end loop;
+
+			for i in 0 to 1 loop
+				if (nowin_wr_nop2_dqs(i) = '1' and clk4_phase_short(i)(0) = '1') then
+					dqs_q(i) <= '1';
+				else
+					dqs_q(i) <= '0';
+				end if;
+			end loop;
+
+			for i in 0 to 15 loop
+				if nowin_wr_nop1_d(i) = '1' and clk4_phase_short(i)(1) = '1' then
+					sdr_wr_msw(i) <= '1';
+				else
+					sdr_wr_msw(i) <= '0';
+				end if;
+			end loop;
+			
+			for i in 0 to 1 loop
+				if nowin_wr_nop1_dm(i) = '1' and clk4_phase_short(i)(1) = '1' then
+					sdr_wr_msw(i+16) <= '1';
+				else
+					sdr_wr_msw(i+16) <= '0';
+				end if;
+			end loop;
+
+		end if;
+	end process;
+	
+	-- NOTE! DATA OUTPUT PATH. CLOCKED ON FALLING 4X CLOCK
+	process(cpu_clk_4x, areset)	--
+	begin
+		if areset = '1' then
+		    sdr_d_p <= "ZZZZZZZZZZZZZZZZ";
+		    dm_q_p <= "11";
+		    sdr_oe_n <= "1111111111111111";
+		    sdr_d <= "0000000000000000";
+		    dm_q <= "11";
+		elsif (cpu_clk_4x'event and cpu_clk_4x = '0') then
+
+			for i in 0 to 15 loop
+				if sdr_oe_n(i) = '0' then
+					sdr_d_p(i) <= transport sdr_d(i) after Clk_to_Output;
+				else
+					sdr_d_p(i) <= transport 'Z' after Clk_to_Output;
+				end if;
+		   	end loop;			
+
+			dm_q_p <= transport dm_q after Clk_to_Output;
+
+			for i in 0 to 15 loop
+				if sdr_oe_ctrl(i) = '0' then
+					sdr_oe_n(i) <= '0';
+				else
+					sdr_oe_n(i) <= '1';
+				end if;
+			end loop;
+			
+			for i in 0 to 15 loop
+				if sdr_wr_msw(i) = '1' then
+		   			sdr_d(i) <= sdr_smp(i);
+		   		else
+	   				sdr_d(i) <= sdr_smp(i+16);
+	   			end if;
+		   	end loop;
+		   	
+			for i in 0 to 1 loop
+				if sdr_wr_msw(i+16) = '1' then
+		   			dm_q(i) <= sdr_smp(i+32);
+		   		else
+		   			dm_q(i) <= sdr_smp(i+34);
+		   		end if;
+		   	end loop;
+		   	
+		end if;
+	end process;
+	
+	process(cpu_clk_2x, areset)	--
+	begin
+		if areset = '1' then
+			refresh_cnt <= "0000000000";
+			refresh_pend <= '0';
+			refresh_end <= '0';
+			refresh_wait_cnt <= "0000";
+			refresh_wait_end <= '0';
+		elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
+		
+			if refresh_cnt = Refresh_Interval then
+				refresh_end <= '1';
+			else
+				refresh_end <= '0';
+			end if;
+			
+			if refresh_end = '1' then
+				refresh_cnt <= "0000000000";
+			else
+				refresh_cnt <= refresh_cnt + '1';
+			end if;
+			
+			if refresh_end = '1' and refresh_en = '1' then
+				refresh_pend <= '1';
+			elsif ddr_state = refresh then
+				refresh_pend <= '0';
+			else
+				refresh_pend <= refresh_pend;
+			end if;
+			
+			if ddr_state = refresh_wait then
+				refresh_wait_cnt <= refresh_wait_cnt + '1';
+			else
+				refresh_wait_cnt <= "0000";
+			end if;
+			
+			if refresh_wait_cnt = "1011" then
+				refresh_wait_end <= '1';
+			else
+				refresh_wait_end <= '0';
+			end if;
+			
+		end if;
+	end process;
+	
+	-- 911. THIS IS A DUMMY FOR FGPA IMPEMENTATION TESTING
+
+	process(ddr_in_clk, areset)
+	begin
+		if areset = '1' then
+			ddr_clk_tog <= '0';
+		elsif (ddr_in_clk'event and ddr_in_clk = '1') then
+			ddr_clk_tog <= not(ddr_clk_tog);
+		end if;
+	end process;	
+	
+	process(ddr_in_clk_2x, areset)
+	begin
+		if areset = '1' then
+			ddr_clk_smp1 <= '0';
+			ddr_clk_smp2 <= '0';
+			ddr_clk_phase <= '0';
+		elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then
+			ddr_clk_smp1 <= ddr_clk_tog;
+			ddr_clk_smp2 <= ddr_clk_smp1;
+			if ddr_clk_smp1 = '1' and ddr_clk_smp2 = '0' then
+				ddr_clk_phase <= '0';
+			else
+				ddr_clk_phase <= not(ddr_clk_phase);
+			end if;
+		end if;
+	end process;
+
+	process(ddr_in_clk_2x, areset)
+	begin
+		if areset = '1' then
+			cas_n_smp <= '0';
+			ras_n_smp <= '0';
+			we_n_smp <= '0';
+			read_start_sig <= '0';
+		elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then
+			cas_n_smp <= cas_qn_p_del;
+			ras_n_smp <= ras_qn_p_del;
+			we_n_smp <= we_qn_p_del;
+			if ras_n_smp = '1' and cas_n_smp = '0' and we_n_smp = '1' and ddr_clk_phase = '1' then
+				read_start_sig <= '1';
+			else
+				read_start_sig <= '0';
+			end if;
+		end if;
+	end process;
+
+	process(ddr_in_clk_2x, areset)
+	begin
+		if areset = '1' then
+			sdr_d_in <= "0000000000000000";
+		elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then
+			sdr_d_in <= sdr_d_p_del;
+		end if;
+	end process;
+	
+	process(ddr_in_clk_2x, areset)
+	begin
+		if areset = '1' then
+			read_time_cnt <= "00";
+			read_input_en <= '0';
+		elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then
+
+			if read_start_sig = '1' then	
+				read_time_cnt <= "01";
+			elsif read_time_cnt = "00" then
+				read_time_cnt <= read_time_cnt;
+			else
+				read_time_cnt <= read_time_cnt + '1';
+			end if;
+
+			if read_time_cnt = "11" then
+				read_input_en <= '1';
+			else
+				read_input_en <= '0';
+			end if;
+			
+			read_input_en_del <= read_input_en;
+
+		end if;
+	end process;
+	
+	process(ddr_in_clk_2x, areset)
+	begin
+		if areset = '1' then
+			ddr_data_read_int <= "00000000000000000000000000000000";
+		elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then
+			if read_input_en = '1' then
+				ddr_data_read_int(15 downto 0) <= sdr_d_in;
+			end if;
+			if read_input_en_del = '1' then
+				ddr_data_read_int(31 downto 16) <= sdr_d_in;
+			end if;
+		end if;
+	end process;
+
+end behave;
+
+
diff --git a/misc/ddrsdram/src/mt46v16m16.vhd b/misc/ddrsdram/src/mt46v16m16.vhd
index 6b89345..356bb28 100644
--- a/misc/ddrsdram/src/mt46v16m16.vhd
+++ b/misc/ddrsdram/src/mt46v16m16.vhd
@@ -1,1320 +1,1320 @@
------------------------------------------------------------------------------------------
---
---     File Name: MT46V16M16.VHD
---       Version: 2.1
---          Date: January 14th, 2002
---         Model: Behavioral
---     Simulator: NCDesktop      - http://www.cadence.com
---                ModelSim PE    - http://www.model.com
---
---  Dependencies: None
---
---        Author: Son P. Huynh
---         Email: sphuynh@micron.com
---         Phone: (208) 368-3825
---       Company: Micron Technology, Inc.
---   Part Number: MT46V16M16 (4 Mb x 16 x 4 Banks)
---
---   Description: Micron 256 Mb SDRAM DDR (Double Data Rate)
---
---    Limitation: Doesn't model internal refresh counter
---
---          Note: 
---
---    Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
---                WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY 
---                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
---                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
---
---                Copyright (c) 1998 Micron Semiconductor Products, Inc.
---                All rights researved
---
---  Rev  Author                        Date        Changes
---  ---  ----------------------------  ----------  -------------------------------------
---  2.1  Son P. Huynh                  01/14/2002  - Fix Burst_counter
---       Micron Technology, Inc.
---
---  2.0  Son P. Huynh                  11/08/2001  - Second release
---       Micron Technology, Inc.                   - Rewrote and remove SHARED VARIABLE
---
------------------------------------------------------------------------------------------
-
-LIBRARY IEEE;
-    USE IEEE.STD_LOGIC_1164.ALL;
-    USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-    USE IEEE.STD_LOGIC_ARITH.ALL;
-
-ENTITY MT46V16M16 IS
-    GENERIC (                                   -- Timing for -75Z CL2
-        tCK       : TIME    :=  7.500 ns;
-        tCH       : TIME    :=  3.375 ns;       -- 0.45*tCK
-        tCL       : TIME    :=  3.375 ns;       -- 0.45*tCK
-        tDH       : TIME    :=  0.500 ns;
-        tDS       : TIME    :=  0.500 ns;
-        tIH       : TIME    :=  0.900 ns;
-        tIS       : TIME    :=  0.900 ns;
-        tMRD      : TIME    := 15.000 ns;
-        tRAS      : TIME    := 40.000 ns;
-        tRAP      : TIME    := 20.000 ns;
-        tRC       : TIME    := 65.000 ns;
-        tRFC      : TIME    := 75.000 ns;
-        tRCD      : TIME    := 20.000 ns;
-        tRP       : TIME    := 20.000 ns;
-        tRRD      : TIME    := 15.000 ns;
-        tWR       : TIME    := 15.000 ns;
-        addr_bits : INTEGER := 13;
-        data_bits : INTEGER := 16;
-        cols_bits : INTEGER :=  9
-    );
-    PORT (
-        Dq    : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
-        Dqs   : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
-        Addr  : IN    STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
-        Ba    : IN    STD_LOGIC_VECTOR (1 DOWNTO 0);
-        Clk   : IN    STD_LOGIC;
-        Clk_n : IN    STD_LOGIC;
-        Cke   : IN    STD_LOGIC;
-        Cs_n  : IN    STD_LOGIC;
-        Ras_n : IN    STD_LOGIC;
-        Cas_n : IN    STD_LOGIC;
-        We_n  : IN    STD_LOGIC;
-        Dm    : IN    STD_LOGIC_VECTOR (1 DOWNTO 0)
-    );
-END MT46V16M16;
-
-ARCHITECTURE behave OF MT46V16M16 IS
-    -- Array for Read pipeline
-    TYPE Array_Read_cmnd IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
-    TYPE Array_Read_bank IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
-    TYPE Array_Read_cols IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
-
-    -- Array for Write pipeline
-    TYPE Array_Write_cmnd IS ARRAY (2 DOWNTO 0) OF STD_LOGIC;
-    TYPE Array_Write_bank IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
-    TYPE Array_Write_cols IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
-
-    -- Array for Auto Precharge
-    TYPE Array_Read_precharge  IS ARRAY (3 DOWNTO 0) OF STD_LOGIC;
-    TYPE Array_Write_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC;
-    TYPE Array_Count_precharge IS ARRAY (3 DOWNTO 0) OF INTEGER;
-
-    -- Array for Manual Precharge
-    TYPE Array_A10_precharge  IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
-    TYPE Array_Bank_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
-    TYPE Array_Cmnd_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
-    
-    -- Array for Burst Terminate
-    TYPE Array_Cmnd_bst IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
-
-    -- Array for Memory Access
-    TYPE Array_ram_type IS ARRAY (2**cols_bits - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
-    TYPE Array_ram_pntr IS ACCESS Array_ram_type;
-    TYPE Array_ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF Array_ram_pntr;
-
-    -- Data pair
-    SIGNAL Dq_pair : STD_LOGIC_VECTOR (2 * data_bits - 1 DOWNTO 0);
-    SIGNAL Dm_pair : STD_LOGIC_VECTOR (3 DOWNTO 0);
-
-    -- Mode Register
-    SIGNAL Mode_reg : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
-    
-    -- Command Decode Variables
-    SIGNAL Active_enable, Aref_enable, Burst_term, Ext_mode_enable : STD_LOGIC := '0';
-    SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : STD_LOGIC := '0';
-    
-    -- Burst Length Decode Variables
-    SIGNAL Burst_length_2, Burst_length_4, Burst_length_8, Burst_length_f : STD_LOGIC := '0';
-    
-    -- Cas Latency Decode Variables
-    SIGNAL Cas_latency_15, Cas_latency_2, Cas_latency_25, Cas_latency_3, Cas_latency_4 : STD_LOGIC := '0';
-
-    -- Internal Control Signals
-    SIGNAL Cs_in, Ras_in, Cas_in, We_in : STD_LOGIC := '0';
-
-    -- System Clock
-    SIGNAL Sys_clk : STD_LOGIC := '0';
-
-    -- Dqs buffer
-    SIGNAL Dqs_out : STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
-
-BEGIN
-    -- Strip the strength
-    Cs_in  <= To_X01 (Cs_n);
-    Ras_in <= To_X01 (Ras_n);
-    Cas_in <= To_X01 (Cas_n);
-    We_in  <= To_X01 (We_n);
-    
-    -- Commands Decode
-    Active_enable   <= NOT(Cs_in) AND NOT(Ras_in) AND     Cas_in  AND     We_in;
-    Aref_enable     <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND     We_in;
-    Burst_term      <= NOT(Cs_in) AND     Ras_in  AND     Cas_in  AND NOT(We_in);
-    Ext_mode_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND     Ba(0)  AND NOT(Ba(1));
-    Mode_reg_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND NOT(Ba(0)) AND NOT(Ba(1));
-    Prech_enable    <= NOT(Cs_in) AND NOT(Ras_in) AND     Cas_in  AND NOT(We_in);
-    Read_enable     <= NOT(Cs_in) AND     Ras_in  AND NOT(Cas_in) AND     We_in;
-    Write_enable    <= NOT(Cs_in) AND     Ras_in  AND NOT(Cas_in) AND NOT(We_in);
-
-    -- Burst Length Decode
-    Burst_length_2  <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND     Mode_reg(0);
-    Burst_length_4  <= NOT(Mode_reg(2)) AND     Mode_reg(1)  AND NOT(Mode_reg(0));
-    Burst_length_8  <= NOT(Mode_reg(2)) AND     Mode_reg(1)  AND     Mode_reg(0);
-    Burst_length_f  <=    (Mode_reg(2)) AND     Mode_reg(1)  AND     Mode_reg(0);
-
-    -- CAS Latency Decode
-    Cas_latency_15  <=     Mode_reg(6)  AND NOT(Mode_reg(5)) AND    (Mode_reg(4));
-    Cas_latency_2   <= NOT(Mode_reg(6)) AND     Mode_reg(5)  AND NOT(Mode_reg(4));
-    Cas_latency_25  <=     Mode_reg(6)  AND     Mode_reg(5)  AND NOT(Mode_reg(4));
-    Cas_latency_3   <= NOT(Mode_reg(6)) AND     Mode_reg(5)  AND     Mode_reg(4);
-    Cas_latency_4   <=    (Mode_reg(6)) AND NOT(Mode_reg(5)) AND NOT(Mode_reg(4));
-
-    -- Dqs buffer
-    Dqs <= Dqs_out;
-
-    --
-    -- System Clock
-    --
-    int_clk : PROCESS (Clk, Clk_n)
-        VARIABLE ClkZ, CkeZ : STD_LOGIC := '0';
-    begin
-        IF Clk = '1' AND Clk_n = '0' THEN
-            ClkZ := '1';
-            CkeZ := Cke;
-        ELSIF Clk = '0' AND Clk_n = '1' THEN
-            ClkZ := '0';
-        END IF;
-        Sys_clk <= CkeZ AND ClkZ;
-    END PROCESS;
-
-    --
-    -- Main Process
-    --
-    state_register : PROCESS
-        -- Precharge Variables
-        VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : STD_LOGIC := '0';
-
-        -- Activate Variables
-        VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : STD_LOGIC := '1';
-
-        -- Data IO variables
-        VARIABLE Data_in_enable, Data_out_enable : STD_LOGIC := '0';
-
-        -- Internal address mux variables
-        VARIABLE Cols_brst : STD_LOGIC_VECTOR (2 DOWNTO 0);
-        VARIABLE Prev_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
-        VARIABLE Bank_addr : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
-        VARIABLE Cols_addr : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
-        VARIABLE Rows_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
-        VARIABLE B0_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
-        VARIABLE B1_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
-        VARIABLE B2_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
-        VARIABLE B3_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
-
-        -- DLL Reset variables
-        VARIABLE DLL_enable : STD_LOGIC := '0';
-        VARIABLE DLL_reset : STD_LOGIC := '0';
-        VARIABLE DLL_done : STD_LOGIC := '0';
-        VARIABLE DLL_count : INTEGER := 0;
-        
-        -- Timing Check
-        VARIABLE MRD_chk : TIME := 0 ns;
-        VARIABLE RFC_chk : TIME := 0 ns;
-        VARIABLE RRD_chk : TIME := 0 ns;
-        VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns;
-        VARIABLE RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3 : TIME := 0 ns;
-        VARIABLE RC_chk0, RC_chk1, RC_chk2, RC_chk3 : TIME := 0 ns;
-        VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns;
-        VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns;
-        VARIABLE WR_chk0, WR_chk1, WR_chk2, WR_chk3 : TIME := 0 ns;
-
-        -- Read pipeline variables
-        VARIABLE Read_cmnd : Array_Read_cmnd;
-        VARIABLE Read_bank : Array_Read_bank;
-        VARIABLE Read_cols : Array_Read_cols;
-
-        -- Write pipeline variables
-        VARIABLE Write_cmnd : Array_Write_cmnd;
-        VARIABLE Write_bank : Array_Write_bank;
-        VARIABLE Write_cols : Array_Write_cols;
-
-        -- Auto Precharge variables
-        VARIABLE Read_precharge  : Array_Read_precharge  := ('0' & '0' & '0' & '0');
-        VARIABLE Write_precharge : Array_Write_precharge := ('0' & '0' & '0' & '0');
-        VARIABLE Count_precharge : Array_Count_precharge := ( 0  &  0  &  0  &  0 );
-
-        -- Manual Precharge variables
-        VARIABLE A10_precharge  : Array_A10_precharge;
-        VARIABLE Bank_precharge : Array_Bank_precharge;
-        VARIABLE Cmnd_precharge : Array_Cmnd_precharge;
-
-        -- Burst Terminate variable
-        VARIABLE Cmnd_bst : Array_Cmnd_bst;
-
-        -- Memory Banks
-        VARIABLE Bank0 : Array_ram_stor;
-        VARIABLE Bank1 : Array_ram_stor;
-        VARIABLE Bank2 : Array_ram_stor;
-        VARIABLE Bank3 : Array_ram_stor;
-
-        -- Burst Counter
-        VARIABLE Burst_counter : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
-
-        -- Internal Dqs initialize
-        VARIABLE Dqs_int : STD_LOGIC := '0';
-
-        -- Data buffer for DM Mask
-        VARIABLE Data_buf : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
-
-        --
-        -- Initialize empty rows
-        --
-        PROCEDURE Init_mem (Bank : STD_LOGIC_VECTOR; Row_index : INTEGER) IS
-            VARIABLE i, j : INTEGER := 0;
-        BEGIN
-            IF Bank = "00" THEN
-                IF Bank0 (Row_index) = NULL THEN                        -- Check to see if row empty
-                    Bank0 (Row_index) := NEW Array_ram_type;            -- Open new row for access
-                    FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP           -- Filled row with zeros
-                        FOR j IN (data_bits - 1) DOWNTO 0 LOOP
-                            Bank0 (Row_index) (i) (j) := '0';
-                        END LOOP;
-                    END LOOP;
-                END IF;
-            ELSIF Bank = "01" THEN
-                IF Bank1 (Row_index) = NULL THEN
-                    Bank1 (Row_index) := NEW Array_ram_type;
-                    FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
-                        FOR j IN (data_bits - 1) DOWNTO 0 LOOP
-                            Bank1 (Row_index) (i) (j) := '0';
-                        END LOOP;
-                    END LOOP;
-                END IF;
-            ELSIF Bank = "10" THEN
-                IF Bank2 (Row_index) = NULL THEN
-                    Bank2 (Row_index) := NEW Array_ram_type;
-                    FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
-                        FOR j IN (data_bits - 1) DOWNTO 0 LOOP
-                            Bank2 (Row_index) (i) (j) := '0';
-                        END LOOP;
-                    END LOOP;
-                END IF;
-            ELSIF Bank = "11" THEN
-                IF Bank3 (Row_index) = NULL THEN
-                    Bank3 (Row_index) := NEW Array_ram_type;
-                    FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
-                        FOR j IN (data_bits - 1) DOWNTO 0 LOOP
-                            Bank3 (Row_index) (i) (j) := '0';
-                        END LOOP;
-                    END LOOP;
-                END IF;
-            END IF;
-        END;
-
-        --
-        -- Burst Counter
-        --
-        PROCEDURE Burst_decode IS
-            VARIABLE Cols_temp : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0) := (OTHERS => '0');
-        BEGIN
-            -- Advance burst counter
-            Burst_counter := Burst_counter + 1;
-
-            -- Burst Type
-            IF Mode_reg (3) = '0' THEN
-                Cols_temp := Cols_addr + 1;
-            ELSIF Mode_reg (3) = '1' THEN
-                Cols_temp (2) := Burst_counter (2) XOR Cols_brst (2);
-                Cols_temp (1) := Burst_counter (1) XOR Cols_brst (1);
-                Cols_temp (0) := Burst_counter (0) XOR Cols_brst (0);
-            END IF;
-
-            -- Burst Length
-            IF Burst_length_2 = '1' THEN
-                Cols_addr (0) := Cols_temp (0);
-            ELSIF Burst_length_4 = '1' THEN
-                Cols_addr (1 DOWNTO 0) := Cols_temp (1 DOWNTO 0);
-            ELSIF Burst_length_8 = '1' THEN
-                Cols_addr (2 DOWNTO 0) := Cols_temp (2 DOWNTO 0);
-            ELSE
-                Cols_addr := Cols_temp;
-            END IF;
-
-            -- Data counter
-            IF Burst_length_2 = '1' THEN
-                IF Burst_counter >= 2 THEN
-                    IF Data_in_enable = '1' THEN
-                        Data_in_enable := '0';
-                    ELSIF Data_out_enable = '1' THEN
-                        Data_out_enable := '0';
-                    END IF;
-                END IF;
-            ELSIF Burst_length_4 = '1' THEN
-                IF Burst_counter >= 4 THEN
-                    IF Data_in_enable = '1' THEN
-                        Data_in_enable := '0';
-                    ELSIF Data_out_enable = '1' THEN
-                        Data_out_enable := '0';
-                    END IF;
-                END IF;
-            ELSIF Burst_length_8 = '1' THEN
-                IF Burst_counter >= 8 THEN
-                    IF Data_in_enable = '1' THEN
-                        Data_in_enable := '0';
-                    ELSIF Data_out_enable = '1' THEN
-                        Data_out_enable := '0';
-                    END IF;
-                END IF;
-            END IF;
-        END;
-
-    BEGIN
-        WAIT ON Sys_clk;
-
-        --
-        -- Manual Precharge Pipeline
-        --
-        IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
-            -- A10 Precharge Pipeline
-            A10_precharge(0) := A10_precharge(1);
-            A10_precharge(1) := A10_precharge(2);
-            A10_precharge(2) := A10_precharge(3);
-            A10_precharge(3) := A10_precharge(4);
-            A10_precharge(4) := A10_precharge(5);
-            A10_precharge(5) := A10_precharge(6);
-            A10_precharge(6) := A10_precharge(7);
-            A10_precharge(7) := A10_precharge(8);
-            A10_precharge(8) := '0';
-
-            -- Bank Precharge Pipeline
-            Bank_precharge(0) := Bank_precharge(1);
-            Bank_precharge(1) := Bank_precharge(2);
-            Bank_precharge(2) := Bank_precharge(3);
-            Bank_precharge(3) := Bank_precharge(4);
-            Bank_precharge(4) := Bank_precharge(5);
-            Bank_precharge(5) := Bank_precharge(6);
-            Bank_precharge(6) := Bank_precharge(7);
-            Bank_precharge(7) := Bank_precharge(8);
-            Bank_precharge(8) := "00";
-
-            -- Command Precharge Pipeline
-            Cmnd_precharge(0) := Cmnd_precharge(1);
-            Cmnd_precharge(1) := Cmnd_precharge(2);
-            Cmnd_precharge(2) := Cmnd_precharge(3);
-            Cmnd_precharge(3) := Cmnd_precharge(4);
-            Cmnd_precharge(4) := Cmnd_precharge(5);
-            Cmnd_precharge(5) := Cmnd_precharge(6);
-            Cmnd_precharge(6) := Cmnd_precharge(7);
-            Cmnd_precharge(7) := Cmnd_precharge(8);
-            Cmnd_precharge(8) := '0';
-
-            -- Terminate Read if same bank or all banks
-            IF ((Cmnd_precharge (0) = '1') AND
-                (Bank_precharge (0) = Bank_addr OR A10_precharge (0) = '1') AND
-                (Data_out_enable = '1')) THEN
-                Data_out_enable := '0';
-            END IF;
-        END IF;
-
-        --
-        -- Burst Terminate Pipeline
-        --
-        IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
-            -- Burst Terminate pipeline
-            Cmnd_bst (0) := Cmnd_bst (1);
-            Cmnd_bst (1) := Cmnd_bst (2);
-            Cmnd_bst (2) := Cmnd_bst (3);
-            Cmnd_bst (3) := Cmnd_bst (4);
-            Cmnd_bst (4) := Cmnd_bst (5);
-            Cmnd_bst (5) := Cmnd_bst (6);
-            Cmnd_bst (6) := Cmnd_bst (7);
-            Cmnd_bst (7) := Cmnd_bst (8);
-            Cmnd_bst (8) := '0';
-
-            -- Terminate current Read
-            IF ((Cmnd_bst  (0) = '1') AND (Data_out_enable = '1')) THEN
-                Data_out_enable := '0';
-            END IF;
-        END IF;
-
-        --
-        -- Dq and Dqs Drivers
-        --
-        IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
-            -- Read Command Pipeline
-            Read_cmnd (0) := Read_cmnd (1);
-            Read_cmnd (1) := Read_cmnd (2);
-            Read_cmnd (2) := Read_cmnd (3);
-            Read_cmnd (3) := Read_cmnd (4);
-            Read_cmnd (4) := Read_cmnd (5);
-            Read_cmnd (5) := Read_cmnd (6);
-            Read_cmnd (6) := Read_cmnd (7);
-            Read_cmnd (7) := Read_cmnd (8);
-            Read_cmnd (8) := '0';
-
-            -- Read Bank Pipeline
-            Read_bank (0) := Read_bank (1);
-            Read_bank (1) := Read_bank (2);
-            Read_bank (2) := Read_bank (3);
-            Read_bank (3) := Read_bank (4);
-            Read_bank (4) := Read_bank (5);
-            Read_bank (5) := Read_bank (6);
-            Read_bank (6) := Read_bank (7);
-            Read_bank (7) := Read_bank (8);
-            Read_bank (8) := "00";
-
-            -- Read Column Pipeline
-            Read_cols (0) := Read_cols (1);
-            Read_cols (1) := Read_cols (2);
-            Read_cols (2) := Read_cols (3);
-            Read_cols (3) := Read_cols (4);
-            Read_cols (4) := Read_cols (5);
-            Read_cols (5) := Read_cols (6);
-            Read_cols (6) := Read_cols (7);
-            Read_cols (7) := Read_cols (8);
-            Read_cols (8) := (OTHERS => '0');
-
-            -- Initialize Read command
-            IF Read_cmnd (0) = '1' THEN
-                Data_out_enable := '1';
-                Bank_addr := Read_bank (0);
-                Cols_addr := Read_cols (0);
-                Cols_brst := Cols_addr (2 DOWNTO 0);
-                Burst_counter := (OTHERS => '0');
-
-                -- Row address mux
-                CASE Bank_addr IS
-                    WHEN "00"   => Rows_addr := B0_row_addr;
-                    WHEN "01"   => Rows_addr := B1_row_addr;
-                    WHEN "10"   => Rows_addr := B2_row_addr;
-                    WHEN OTHERS => Rows_addr := B3_row_addr;
-                END CASE;
-            END IF;
-
-            -- Toggle Dqs during Read command
-            IF Data_out_enable = '1' THEN
-                Dqs_int := '0';
-                IF Dqs_out = "00" THEN
-                    Dqs_out <= "11";
-                ELSIF Dqs_out = "11" THEN
-                    Dqs_out <= "00";
-                ELSE
-                    Dqs_out <= "00";
-                END IF;
-            ELSIF Data_out_enable = '0' AND Dqs_int = '0' THEN
-                Dqs_out <= "ZZ";
-            END IF;
-
-            -- Initialize Dqs for Read command
-            IF Read_cmnd (2) = '1' THEN
-                IF Data_out_enable = '0' THEN
-                    Dqs_int := '1';
-                    Dqs_out <= "00";
-                END IF;
-            END IF;
-
-            -- Read Latch
-            IF Data_out_enable = '1' THEN
-                -- Initialize Memory
-                Init_mem (Bank_addr, CONV_INTEGER(Rows_addr));
-                
-                -- Output Data
-                CASE Bank_addr IS
-                    WHEN "00"   => Dq <= Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
-                    WHEN "01"   => Dq <= Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
-                    WHEN "10"   => Dq <= Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
-                    WHEN OTHERS => Dq <= Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
-                END CASE;
-
-                --  Increase Burst Counter
-                Burst_decode;
-            ELSE
-                Dq <= (OTHERS => 'Z');
-            END IF;
-        END IF;
-
-        --
-        -- Write FIFO and DM Mask Logic
-        --
-        IF Sys_clk'EVENT AND Sys_clk = '1' THEN
-            -- Write command pipeline
-            Write_cmnd (0) := Write_cmnd (1);
-            Write_cmnd (1) := Write_cmnd (2);
-            Write_cmnd (2) := '0';
-
-            -- Write command pipeline
-            Write_bank (0) := Write_bank (1);
-            Write_bank (1) := Write_bank (2);
-            Write_bank (2) := "00";
-
-            -- Write column pipeline
-            Write_cols (0) := Write_cols (1);
-            Write_cols (1) := Write_cols (2);
-            Write_cols (2) := (OTHERS => '0');
-
-            -- Initialize Write command
-            IF Write_cmnd (0) = '1' THEN
-                Data_in_enable := '1';
-                Bank_addr := Write_bank (0);
-                Cols_addr := Write_cols (0);
-                Cols_brst := Cols_addr (2 DOWNTO 0);
-                Burst_counter := (OTHERS => '0');
-
-                -- Row address mux
-                CASE Bank_addr IS
-                    WHEN "00"   => Rows_addr := B0_row_addr;
-                    WHEN "01"   => Rows_addr := B1_row_addr;
-                    WHEN "10"   => Rows_addr := B2_row_addr;
-                    WHEN OTHERS => Rows_addr := B3_row_addr;
-                END CASE;
-            END IF;
-
-            -- Write data
-            IF Data_in_enable = '1' THEN
-                -- Initialize memory
-                Init_mem (Bank_addr, CONV_INTEGER(Rows_addr));
-                
-                -- Write first data
-                IF Dm_pair (1) = '0' OR Dm_pair (0) = '0' THEN
-                    -- Data Buffer
-                    CASE Bank_addr IS
-                        WHEN "00"   => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
-                        WHEN "01"   => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
-                        WHEN "10"   => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
-                        WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
-                    END CASE;
-
-                    -- Perform DM Mask
-                    IF Dm_pair (0) = '0' THEN
-                        Data_buf ( 7 DOWNTO 0) := Dq_pair ( 7 DOWNTO 0);
-                    END IF;
-                    IF Dm_pair (1) = '0' THEN
-                        Data_buf (15 DOWNTO 8) := Dq_pair (15 DOWNTO 8);
-                    END IF;
-
-                    -- Write Data
-                    CASE Bank_addr IS
-                        WHEN "00"   => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
-                        WHEN "01"   => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
-                        WHEN "10"   => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
-                        WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
-                    END CASE;
-                END IF;
-
-                --  Increase Burst Counter
-                Burst_decode;
-
-                -- Write second data
-                IF Dm_pair (3) = '0' OR Dm_pair (2) = '0' THEN
-                    -- Data Buffer
-                    CASE Bank_addr IS
-                        WHEN "00"   => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
-                        WHEN "01"   => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
-                        WHEN "10"   => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
-                        WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
-                    END CASE;
-
-                    -- Perform DM Mask
-                    IF Dm_pair (2) = '0' THEN
-                        Data_buf ( 7 DOWNTO 0) := Dq_pair (23 DOWNTO 16);
-                    END IF;
-                    IF Dm_pair (3) = '0' THEN
-                        Data_buf (15 DOWNTO 8) := Dq_pair (31 DOWNTO 24);
-                    END IF;
-
-                    -- Write Data
-                    CASE Bank_addr IS
-                        WHEN "00"   => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
-                        WHEN "01"   => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
-                        WHEN "10"   => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
-                        WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
-                    END CASE;
-                END IF;
-                
-                -- Increase Burst Counter
-                Burst_decode;
-
-                -- tWR start and tWTR check
-                IF Dm_pair (3 DOWNTO 2) = "00" OR Dm_pair (1 DOWNTO 0) = "00" THEN
-                    CASE Bank_addr IS
-                        WHEN "00"   => WR_chk0 := NOW;
-                        WHEN "01"   => WR_chk1 := NOW;
-                        WHEN "10"   => WR_chk2 := NOW;
-                        WHEN OTHERS => WR_chk3 := NOW;
-                    END CASE;
-
-                    -- tWTR check
-                    ASSERT (Read_enable = '0')
-                        REPORT "tWTR violation during Read"
-                        SEVERITY WARNING;
-                END IF;
-            END IF;
-        END IF;
-
-        --
-        -- Auto Precharge Calculation
-        --
-        IF Sys_clk'EVENT AND Sys_clk = '1' THEN
-            -- Precharge counter
-            IF Read_precharge (0) = '1' OR Write_precharge (0) = '1' THEN
-                Count_precharge (0) := Count_precharge (0) + 1;
-            END IF;
-            IF Read_precharge (1) = '1' OR Write_precharge (1) = '1' THEN
-                Count_precharge (1) := Count_precharge (1) + 1;
-            END IF;
-            IF Read_precharge (2) = '1' OR Write_precharge (2) = '1' THEN
-                Count_precharge (2) := Count_precharge (2) + 1;
-            END IF;
-            IF Read_precharge (3) = '1' OR Write_precharge (3) = '1' THEN
-                Count_precharge (3) := Count_precharge (3) + 1;
-            END IF;
-
-            -- Read with AutoPrecharge Calculation
-            --      The device start internal precharge when:
-            --          1.  Meet tRAS requirement
-            --          2.  BL/2 cycles after command
-            IF ((Read_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN
-                IF ((Burst_length_2 = '1' AND Count_precharge(0) >= 1)  OR
-                    (Burst_length_4 = '1' AND Count_precharge(0) >= 2)  OR
-                    (Burst_length_8 = '1' AND Count_precharge(0) >= 4)) THEN
-                    Pc_b0 := '1';
-                    Act_b0 := '0';
-                    RP_chk0 := NOW;
-                    Read_precharge(0) := '0';
-                END IF;
-            END IF;
-            IF ((Read_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN
-                IF ((Burst_length_2 = '1' AND Count_precharge(1) >= 1)  OR
-                    (Burst_length_4 = '1' AND Count_precharge(1) >= 2)  OR
-                    (Burst_length_8 = '1' AND Count_precharge(1) >= 4)) THEN
-                    Pc_b1 := '1';
-                    Act_b1 := '0';
-                    RP_chk1 := NOW;
-                    Read_precharge(1) := '0';
-                END IF;
-            END IF;
-            IF ((Read_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN
-                IF ((Burst_length_2 = '1' AND Count_precharge(2) >= 1)  OR
-                    (Burst_length_4 = '1' AND Count_precharge(2) >= 2)  OR
-                    (Burst_length_8 = '1' AND Count_precharge(2) >= 4)) THEN
-                    Pc_b2 := '1';
-                    Act_b2 := '0';
-                    RP_chk2 := NOW;
-                    Read_precharge(2) := '0';
-                END IF;
-            END IF;
-            IF ((Read_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN
-                IF ((Burst_length_2 = '1' AND Count_precharge(3) >= 1)  OR
-                    (Burst_length_4 = '1' AND Count_precharge(3) >= 2)  OR
-                    (Burst_length_8 = '1' AND Count_precharge(3) >= 4)) THEN
-                    Pc_b3 := '1';
-                    Act_b3 := '0';
-                    RP_chk3 := NOW;
-                    Read_precharge(3) := '0';
-                END IF;
-            END IF;
-
-            -- Write with AutoPrecharge Calculation
-            --      The device start internal precharge when:
-            --          1.  Meet tRAS requirement
-            --          2.  Two clock after last burst
-            -- Since tWR is time base, the model will compensate tRP
-            IF ((Write_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN
-                IF ((Burst_length_2 = '1' AND Count_precharge (0) >= 4) OR
-                    (Burst_length_4 = '1' AND Count_precharge (0) >= 5) OR
-                    (Burst_length_8 = '1' AND Count_precharge (0) >= 7)) THEN
-                    Pc_b0 := '1';
-                    Act_b0 := '0';
-                    RP_chk0 := NOW - ((2 * tCK) - tWR);
-                    Write_precharge(0) := '0';
-                END IF;
-            END IF;
-            IF ((Write_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN
-                IF ((Burst_length_2 = '1' AND Count_precharge (1) >= 4) OR
-                    (Burst_length_4 = '1' AND Count_precharge (1) >= 5) OR
-                    (Burst_length_8 = '1' AND Count_precharge (1) >= 7)) THEN
-                    Pc_b1 := '1';
-                    Act_b1 := '0';
-                    RP_chk1 := NOW - ((2 * tCK) - tWR);
-                    Write_precharge(1) := '0';
-                END IF;
-            END IF;
-            IF ((Write_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN
-                IF ((Burst_length_2 = '1' AND Count_precharge (2) >= 4) OR
-                    (Burst_length_4 = '1' AND Count_precharge (2) >= 5) OR
-                    (Burst_length_8 = '1' AND Count_precharge (2) >= 7)) THEN
-                    Pc_b2 := '1';
-                    Act_b2 := '0';
-                    RP_chk2 := NOW - ((2 * tCK) - tWR);
-                    Write_precharge(2) := '0';
-                END IF;
-            END IF;
-            IF ((Write_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN
-                IF ((Burst_length_2 = '1' AND Count_precharge (3) >= 4) OR
-                    (Burst_length_4 = '1' AND Count_precharge (3) >= 5) OR
-                    (Burst_length_8 = '1' AND Count_precharge (3) >= 7)) THEN
-                    Pc_b3 := '1';
-                    Act_b3 := '0';
-                    RP_chk3 := NOW - ((2 * tCK) - tWR);
-                    Write_precharge(3) := '0';
-                END IF;
-            END IF;
-        END IF;
-        
-        --
-        -- DLL Counter
-        --
-        IF Sys_clk'EVENT AND Sys_clk = '1' THEN
-            IF (DLL_Reset = '1' AND DLL_done = '0') THEN
-                DLL_count := DLL_count + 1;
-                IF (DLL_count >= 200) THEN
-                    DLL_done := '1';
-                END IF;
-            END IF;
-        END IF;
-
-        --
-        -- Control Logic
-        --
-        IF Sys_clk'EVENT AND Sys_clk = '1' THEN
-            -- Auto Refresh
-            IF Aref_enable = '1' THEN
-                -- Auto Refresh to Auto Refresh
-                ASSERT (NOW - RFC_chk >= tRFC)
-                    REPORT "tRFC violation during Auto Refresh"
-                    SEVERITY WARNING;
-
-                -- Precharge to Auto Refresh
-                ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
-                        (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
-                    REPORT "tRP violation during Auto Refresh"
-                    SEVERITY WARNING;
-
-                -- Precharge to Auto Refresh
-                ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
-                    REPORT "All banks must be Precharge before Auto Refresh"
-                    SEVERITY WARNING;
-
-                -- Record current tRFC time
-                RFC_chk := NOW;
-            END IF;
-
-            -- Extended Load Mode Register
-            IF Ext_mode_enable = '1' THEN
-                IF (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') THEN
-                    IF (Addr (0) = '0') THEN
-                        DLL_enable := '1';
-                    ELSE
-                        DLL_enable := '0';
-                    END IF;
-                END IF;
-                
-                -- Precharge to EMR
-                ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
-                    REPORT "All bank must be Precharged before Extended Mode Register"
-                    SEVERITY WARNING;
-                
-                -- Precharge to EMR
-                ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
-                        (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
-                    REPORT "tRP violation during Extended Load Register"
-                    SEVERITY WARNING;
-
-                -- LMR/EMR to EMR
-                ASSERT (NOW - MRD_chk >= tMRD)
-                    REPORT "tMRD violation during Extended Mode Register"
-                    SEVERITY WARNING;
-
-                -- Record current tMRD time
-                MRD_chk := NOW;
-            END IF;
-
-            -- Load Mode Register
-            IF Mode_reg_enable = '1' THEN
-                -- Register mode
-                Mode_reg <= Addr;
-                
-                -- DLL Reset
-                IF (DLL_enable = '1' AND Addr (8) = '1') THEN
-                    DLL_reset := '1';
-                    DLL_done  := '0';
-                    DLL_count := 0;
-                ELSIF (DLL_enable = '1' AND DLL_reset = '0' AND Addr (8) = '0') THEN
-                    ASSERT (FALSE)
-                        REPORT "DLL is ENABLE: DLL RESET is require"
-                        SEVERITY WARNING;
-                ELSIF (DLL_enable = '0' AND Addr (8) = '1') THEN
-                    ASSERT (FALSE)
-                        REPORT "DLL is DISABLE: DLL RESET will be ignored"
-                        SEVERITY WARNING;
-                END IF;
-
-                -- Precharge to LMR
-                ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
-                    REPORT "All bank must be Precharged before Load Mode Register"
-                    SEVERITY WARNING;
-
-                -- Precharge to EMR
-                ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
-                        (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
-                    REPORT "tRP violation during Load Mode Register"
-                    SEVERITY WARNING;
-
-                -- LMR/ELMR to LMR
-                ASSERT (NOW - MRD_chk >= tMRD)
-                    REPORT "tMRD violation during Load Mode Register"
-                    SEVERITY WARNING;
-
-                -- Check for invalid Burst Length
-                ASSERT ((Addr (2 DOWNTO 0) = "001") OR      -- BL = 2
-                        (Addr (2 DOWNTO 0) = "010") OR      -- BL = 4
-                        (Addr (2 DOWNTO 0) = "011"))        -- BL = 8
-                    REPORT "Invalid Burst Length during Load Mode Register"
-                    SEVERITY WARNING;
-
-                -- Check for invalid CAS Latency
-                ASSERT ((Addr (6 DOWNTO 4) = "010") OR      -- CL = 2.0
-                        (Addr (6 DOWNTO 4) = "110"))        -- CL = 2.5
-                    REPORT "Invalid CAS Latency during Load Mode Register"
-                    SEVERITY WARNING;
-
-                -- Record current tMRD time
-                MRD_chk := NOW;
-            END IF;
-
-            -- Active Block (latch Bank and Row Address)
-            IF Active_enable = '1' THEN
-                -- Activate an OPEN bank can corrupt data
-                ASSERT ((Ba = "00" AND Act_b0 = '0') OR
-                        (Ba = "01" AND Act_b1 = '0') OR
-                        (Ba = "10" AND Act_b2 = '0') OR
-                        (Ba = "11" AND Act_b3 = '0'))
-                    REPORT "Bank is already activated - data can be corrupted"
-                    SEVERITY WARNING;
-
-                -- Activate Bank 0
-                IF Ba = "00" AND Pc_b0 = '1' THEN
-                    -- Activate to Activate (same bank)
-                    ASSERT (NOW - RC_chk0 >= tRC)
-                        REPORT "tRC violation during Activate Bank 0"
-                        SEVERITY WARNING;
-
-                    -- Precharge to Active
-                    ASSERT (NOW - RP_chk0 >= tRP)
-                        REPORT "tRP violation during Activate Bank 0"
-                        SEVERITY WARNING;
-
-                    -- Record Variables for checking violation
-                    Act_b0 := '1';
-                    Pc_b0 := '0';
-                    B0_row_addr := Addr;
-                    RC_chk0 := NOW;
-                    RCD_chk0 := NOW;
-                    RAS_chk0 := NOW;
-                    RAP_chk0 := NOW;
-                END IF;
-
-                -- Activate Bank 1
-                IF Ba = "01" AND Pc_b1 = '1' THEN
-                    -- Activate to Activate (same bank)
-                    ASSERT (NOW - RC_chk1 >= tRC)
-                        REPORT "tRC violation during Activate Bank 1"
-                        SEVERITY WARNING;
-
-                    -- Precharge to Active
-                    ASSERT (NOW - RP_chk1 >= tRP)
-                        REPORT "tRP violation during Activate Bank 1"
-                        SEVERITY WARNING;
-
-                    -- Record Variables for checking violation
-                    Act_b1 := '1';
-                    Pc_b1 := '0';
-                    B1_row_addr := Addr;
-                    RC_chk1 := NOW;
-                    RCD_chk1 := NOW;
-                    RAS_chk1 := NOW;
-                    RAP_chk1 := NOW;
-                END IF;
-
-                -- Activate Bank 2
-                IF Ba = "10" AND Pc_b2 = '1' THEN
-                    -- Activate to Activate (same bank)
-                    ASSERT (NOW - RC_chk2 >= tRC)
-                        REPORT "tRC violation during Activate Bank 2"
-                        SEVERITY WARNING;
-
-                    -- Precharge to Active
-                    ASSERT (NOW - RP_chk2 >= tRP)
-                        REPORT "tRP violation during Activate Bank 2"
-                        SEVERITY WARNING;
-
-                    -- Record Variables for checking violation
-                    Act_b2 := '1';
-                    Pc_b2 := '0';
-                    B2_row_addr := Addr;
-                    RC_chk2 := NOW;
-                    RCD_chk2 := NOW;
-                    RAS_chk2 := NOW;
-                    RAP_chk2 := NOW;
-                END IF;
-
-                -- Activate Bank 3
-                IF Ba = "11" AND Pc_b3 = '1' THEN
-                    -- Activate to Activate (same bank)
-                    ASSERT (NOW - RC_chk3 >= tRC)
-                        REPORT "tRC violation during Activate Bank 3"
-                        SEVERITY WARNING;
-
-                    -- Precharge to Active
-                    ASSERT (NOW - RP_chk3 >= tRP)
-                        REPORT "tRP violation during Activate Bank 3"
-                        SEVERITY WARNING;
-
-                    -- Record Variables for checking violation
-                    Act_b3 := '1';
-                    Pc_b3 := '0';
-                    B3_row_addr := Addr;
-                    RC_chk3 := NOW;
-                    RCD_chk3 := NOW;
-                    RAS_chk3 := NOW;
-                    RAP_chk3 := NOW;
-                END IF;
-
-                -- Activate Bank A to Activate Bank B
-                IF (Prev_bank /= Ba) THEN
-                    ASSERT (NOW - RRD_chk >= tRRD)
-                        REPORT "tRRD violation during Activate"
-                        SEVERITY WARNING;
-                END IF;
-                
-                -- AutoRefresh to Activate
-                ASSERT (NOW - RFC_chk >= tRFC)
-                    REPORT "tRFC violation during Activate"
-                    SEVERITY WARNING;
-                
-                -- Record Variables for Checking Violation
-                RRD_chk := NOW;
-                Prev_bank := Ba;
-            END IF;
-
-            -- Precharge Block - Consider NOP if bank already precharged or in process of precharging
-            IF Prech_enable = '1' THEN
-                -- EMR or LMR to Precharge
-                ASSERT (NOW - MRD_chk >= tMRD)
-                    REPORT "tMRD violation during Precharge"
-                    SEVERITY WARNING;
-
-                -- Precharge Bank 0
-                IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "00")) AND Act_b0 = '1') THEN
-                    Act_b0 := '0';
-                    Pc_b0 := '1';
-                    RP_chk0 := NOW;
-
-                    -- Activate to Precharge bank 0
-                    ASSERT (NOW - RAS_chk0 >= tRAS)
-                        REPORT "tRAS violation during Precharge"
-                        SEVERITY WARNING;
-
-                    -- tWR violation check for Write
-                    ASSERT (NOW - WR_chk0 >= tWR)
-                        REPORT "tWR violation during Precharge"
-                        SEVERITY WARNING;
-                END IF;
-
-                -- Precharge Bank 1
-                IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "01")) AND Act_b1 = '1') THEN
-                    Act_b1 := '0';
-                    Pc_b1 := '1';
-                    RP_chk1 := NOW;
-
-                    -- Activate to Precharge
-                    ASSERT (NOW - RAS_chk1 >= tRAS)
-                        REPORT "tRAS violation during Precharge"
-                        SEVERITY WARNING;
-
-                    -- tWR violation check for Write
-                    ASSERT (NOW - WR_chk1 >= tWR)
-                        REPORT "tWR violation during Precharge"
-                        SEVERITY WARNING;
-                END IF;
-
-                -- Precharge Bank 2
-                IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "10")) AND Act_b2 = '1') THEN
-                    Act_b2 := '0';
-                    Pc_b2 := '1';
-                    RP_chk2 := NOW;
-
-                    -- Activate to Precharge
-                    ASSERT (NOW - RAS_chk2 >= tRAS)
-                        REPORT "tRAS violation during Precharge"
-                        SEVERITY WARNING;
-
-                    -- tWR violation check for Write
-                    ASSERT (NOW - WR_chk2 >= tWR)
-                        REPORT "tWR violation during Precharge"
-                        SEVERITY WARNING;
-                END IF;
-
-                -- Precharge Bank 3
-                IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "11")) AND Act_b3 = '1') THEN
-                    Act_b3 := '0';
-                    Pc_b3 := '1';
-                    RP_chk3 := NOW;
-
-                    -- Activate to Precharge
-                    ASSERT (NOW - RAS_chk3 >= tRAS)
-                        REPORT "tRAS violation during Precharge"
-                        SEVERITY WARNING;
-
-                    -- tWR violation check for Write
-                    ASSERT (NOW - WR_chk3 >= tWR)
-                        REPORT "tWR violation during Precharge"
-                        SEVERITY WARNING;
-                END IF;
-
-                -- Pipeline for READ
-                IF CAS_latency_15 = '1' THEN
-                    A10_precharge  (3) := Addr(10);
-                    Bank_precharge (3) := Ba;
-                    Cmnd_precharge (3) := '1';
-                ELSIF CAS_latency_2 = '1' THEN
-                    A10_precharge  (4) := Addr(10);
-                    Bank_precharge (4) := Ba;
-                    Cmnd_precharge (4) := '1';
-                ELSIF CAS_latency_25 = '1' THEN
-                    A10_precharge  (5) := Addr(10);
-                    Bank_precharge (5) := Ba;
-                    Cmnd_precharge (5) := '1';
-                ELSIF CAS_latency_3 = '1' THEN
-                    A10_precharge  (6) := Addr(10);
-                    Bank_precharge (6) := Ba;
-                    Cmnd_precharge (6) := '1';
-                ELSIF CAS_latency_4 = '1' THEN
-                    A10_precharge  (8) := Addr(10);
-                    Bank_precharge (8) := Ba;
-                    Cmnd_precharge (8) := '1';
-                END IF;
-            END IF;
-
-            -- Burst Terminate
-            IF Burst_term = '1' THEN
-                -- Pipeline for Read
-                IF CAS_latency_15 = '1' THEN
-                    Cmnd_bst (3) := '1';
-                ELSIF CAS_latency_2 = '1' THEN
-                    Cmnd_bst (4) := '1';
-                ELSIF CAS_latency_25 = '1' THEN
-                    Cmnd_bst (5) := '1';
-                ELSIF CAS_latency_3 = '1' THEN
-                    Cmnd_bst (6) := '1';
-                ELSIF CAS_latency_4 = '1' THEN
-                    Cmnd_bst (8) := '1';
-                END IF;
-
-                -- Terminate Write
-                ASSERT (Data_in_enable = '0')
-                    REPORT "It's illegal to Burst Terminate a Write"
-                    SEVERITY WARNING;
-
-                -- Terminate Read with Auto Precharge
-                ASSERT (Read_precharge (0) = '0' AND Read_precharge (1) = '0' AND
-                        Read_precharge (2) = '0' AND Read_precharge (3) = '0')
-                    REPORT "It's illegal to Burst Terminate a Read with Auto Precharge"
-                    SEVERITY WARNING;
-            END IF;
-
-            -- Read Command
-            IF Read_enable = '1' THEN
-                -- CAS Latency Pipeline
-                IF Cas_latency_15 = '1' THEN
-                    Read_cmnd (3) := '1';
-                    Read_bank (3) := Ba;
-                    Read_cols (3) := Addr (8 DOWNTO 0);
-                ELSIF Cas_latency_2 = '1' THEN
-                    Read_cmnd (4) := '1';
-                    Read_bank (4) := Ba;
-                    Read_cols (4) := Addr (8 DOWNTO 0);
-                ELSIF Cas_latency_25 = '1' THEN
-                    Read_cmnd (5) := '1';
-                    Read_bank (5) := Ba;
-                    Read_cols (5) := Addr (8 DOWNTO 0);
-                ELSIF Cas_latency_3 = '1' THEN
-                    Read_cmnd (6) := '1';
-                    Read_bank (6) := Ba;
-                    Read_cols (6) := Addr (8 DOWNTO 0);
-                ELSIF Cas_latency_4 = '1' THEN
-                    Read_cmnd (8) := '1';
-                    Read_bank (8) := Ba;
-                    Read_cols (8) := Addr (8 DOWNTO 0);
-                END IF;
-
-                -- Write to Read: Terminate Write Immediately
-                IF Data_in_enable = '1' THEN
-                    Data_in_enable := '0';
-                END IF;
-
-                -- Interrupting a Read with Auto Precharge (same bank only)
-                ASSERT (Read_precharge(CONV_INTEGER(Ba)) = '0')
-                    REPORT "It's illegal to interrupt a Read with Auto Precharge"
-                    SEVERITY WARNING;
-
-                -- Activate to Read
-                ASSERT ((Ba = "00" AND Act_b0 = '1') OR
-                        (Ba = "01" AND Act_b1 = '1') OR
-                        (Ba = "10" AND Act_b2 = '1') OR
-                        (Ba = "11" AND Act_b3 = '1'))
-                    REPORT "Bank is not Activated for Read"
-                    SEVERITY WARNING;
-
-                -- Activate to Read without Auto Precharge
-                IF Addr (10) = '0' THEN
-                    ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR
-                            (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR
-                            (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR
-                            (Ba = "11" AND NOW - RCD_chk3 >= tRCD))
-                        REPORT "tRCD violation during Read"
-                        SEVERITY WARNING;
-                END IF;
-
-                -- Activate to Read with Auto Precharge
-                IF Addr (10) = '1' THEN
-                    ASSERT ((Ba = "00" AND NOW - RAP_chk0 >= tRAP) OR
-                            (Ba = "01" AND NOW - RAP_chk1 >= tRAP) OR
-                            (Ba = "10" AND NOW - RAP_chk2 >= tRAP) OR
-                            (Ba = "11" AND NOW - RAP_chk3 >= tRAP))
-                        REPORT "tRAP violation during Read"
-                        SEVERITY WARNING;
-                END IF;
-
-                -- Auto precharge
-                IF Addr (10) = '1' THEN
-                    Read_precharge (Conv_INTEGER(Ba)) := '1';
-                    Count_precharge (Conv_INTEGER(Ba)) := 0;
-                END IF;
-
-                -- DLL Check
-                IF (DLL_reset = '1') THEN
-                    ASSERT (DLL_done = '1')
-                        REPORT "DLL RESET not complete"
-                        SEVERITY WARNING;
-                END IF;
-            END IF;
-
-            -- Write Command
-            IF Write_enable = '1' THEN
-                -- Pipeline for Write
-                Write_cmnd (2) := '1';
-                Write_bank (2) := Ba;
-                Write_cols (2) := Addr (8 DOWNTO 0);
-
-                -- Interrupting a Write with Auto Precharge (same bank only)
-                ASSERT (Write_precharge(CONV_INTEGER(Ba)) = '0')
-                    REPORT "It's illegal to interrupt a Write with Auto Precharge"
-                    SEVERITY WARNING;
-
-                -- Activate to Write
-                ASSERT ((Ba = "00" AND Act_b0 = '1') OR
-                        (Ba = "01" AND Act_b1 = '1') OR
-                        (Ba = "10" AND Act_b2 = '1') OR
-                        (Ba = "11" AND Act_b3 = '1'))
-                    REPORT "Bank is not Activated for Write"
-                    SEVERITY WARNING;
-
-                -- Activate to Write
-                ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR
-                        (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR
-                        (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR
-                        (Ba = "11" AND NOW - RCD_chk3 >= tRCD))
-                    REPORT "tRCD violation during Write"
-                    SEVERITY WARNING;
-
-                -- Auto precharge
-                IF Addr (10) = '1' THEN
-                    Write_precharge (Conv_INTEGER(Ba)) := '1';
-                    Count_precharge (Conv_INTEGER(Ba)) := 0;
-                END IF;
-            END IF;
-        END IF;
-    END PROCESS;
-
-    --
-    -- Dqs Receiver
-    --
-    dqs_rcvrs : PROCESS
-        VARIABLE Dm_temp : STD_LOGIC_VECTOR (1 DOWNTO 0);
-        VARIABLE Dq_temp : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
-    BEGIN
-        WAIT ON Dqs;
-        -- Latch data at posedge Dqs
-        IF Dqs'EVENT AND Dqs (1) = '1' AND Dqs (0) = '1' THEN
-            Dq_temp := Dq;
-            Dm_temp := Dm;
-        END IF;
-        -- Latch data at negedge Dqs
-        IF Dqs'EVENT AND Dqs (1) = '0' AND Dqs (0) = '0' THEN
-            Dq_pair <= (Dq & Dq_temp);
-            Dm_pair <= (Dm & Dm_temp);
-        END IF;
-    END PROCESS;
-
-    --
-    -- Setup timing checks
-    --
-    Setup_check : PROCESS
-    BEGIN
-        WAIT ON Sys_clk;
-        IF Sys_clk'EVENT AND Sys_clk = '1' THEN
-            ASSERT(Cke'LAST_EVENT >= tIS)
-                REPORT "CKE Setup time violation -- tIS"
-                SEVERITY WARNING;
-            ASSERT(Cs_n'LAST_EVENT >= tIS)
-                REPORT "CS# Setup time violation -- tIS"
-                SEVERITY WARNING;
-            ASSERT(Cas_n'LAST_EVENT >= tIS)
-                REPORT "CAS# Setup time violation -- tIS"
-                SEVERITY WARNING;
-            ASSERT(Ras_n'LAST_EVENT >= tIS)
-                REPORT "RAS# Setup time violation -- tIS"
-                SEVERITY WARNING;
-            ASSERT(We_n'LAST_EVENT >= tIS)
-                REPORT "WE# Setup time violation -- tIS"
-                SEVERITY WARNING;
-            ASSERT(Addr'LAST_EVENT >= tIS)
-                REPORT "ADDR Setup time violation -- tIS"
-                SEVERITY WARNING;
-            ASSERT(Ba'LAST_EVENT >= tIS)
-                REPORT "BA Setup time violation -- tIS"
-                SEVERITY WARNING;
-        END IF;   
-    END PROCESS;
-
-    --
-    -- Hold timing checks
-    --
-    Hold_check : PROCESS
-    BEGIN
-        WAIT ON Sys_clk'DELAYED (tIH);
-        IF Sys_clk'DELAYED (tIH) = '1' THEN
-            ASSERT(Cke'LAST_EVENT >= tIH)
-                REPORT "CKE Hold time violation -- tIH"
-                SEVERITY WARNING;
-            ASSERT(Cs_n'LAST_EVENT >= tIH)
-                REPORT "CS# Hold time violation -- tIH"
-                SEVERITY WARNING;
-            ASSERT(Cas_n'LAST_EVENT >= tIH)
-                REPORT "CAS# Hold time violation -- tIH"
-                SEVERITY WARNING;
-            ASSERT(Ras_n'LAST_EVENT >= tIH)
-                REPORT "RAS# Hold time violation -- tIH"
-                SEVERITY WARNING;
-            ASSERT(We_n'LAST_EVENT >= tIH)
-                REPORT "WE# Hold time violation -- tIH"
-                SEVERITY WARNING;
-            ASSERT(Addr'LAST_EVENT >= tIH)
-                REPORT "ADDR Hold time violation -- tIH"
-                SEVERITY WARNING;
-            ASSERT(Ba'LAST_EVENT >= tIH)
-                REPORT "BA Hold time violation -- tIH"
-                SEVERITY WARNING;
-        END IF;   
-    END PROCESS;
-
-END behave;
+-----------------------------------------------------------------------------------------
+--
+--     File Name: MT46V16M16.VHD
+--       Version: 2.1
+--          Date: January 14th, 2002
+--         Model: Behavioral
+--     Simulator: NCDesktop      - http://www.cadence.com
+--                ModelSim PE    - http://www.model.com
+--
+--  Dependencies: None
+--
+--        Author: Son P. Huynh
+--         Email: sphuynh@micron.com
+--         Phone: (208) 368-3825
+--       Company: Micron Technology, Inc.
+--   Part Number: MT46V16M16 (4 Mb x 16 x 4 Banks)
+--
+--   Description: Micron 256 Mb SDRAM DDR (Double Data Rate)
+--
+--    Limitation: Doesn't model internal refresh counter
+--
+--          Note: 
+--
+--    Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
+--                WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY 
+--                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
+--                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
+--
+--                Copyright (c) 1998 Micron Semiconductor Products, Inc.
+--                All rights researved
+--
+--  Rev  Author                        Date        Changes
+--  ---  ----------------------------  ----------  -------------------------------------
+--  2.1  Son P. Huynh                  01/14/2002  - Fix Burst_counter
+--       Micron Technology, Inc.
+--
+--  2.0  Son P. Huynh                  11/08/2001  - Second release
+--       Micron Technology, Inc.                   - Rewrote and remove SHARED VARIABLE
+--
+-----------------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+    USE IEEE.STD_LOGIC_1164.ALL;
+    USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+    USE IEEE.STD_LOGIC_ARITH.ALL;
+
+ENTITY MT46V16M16 IS
+    GENERIC (                                   -- Timing for -75Z CL2
+        tCK       : TIME    :=  7.500 ns;
+        tCH       : TIME    :=  3.375 ns;       -- 0.45*tCK
+        tCL       : TIME    :=  3.375 ns;       -- 0.45*tCK
+        tDH       : TIME    :=  0.500 ns;
+        tDS       : TIME    :=  0.500 ns;
+        tIH       : TIME    :=  0.900 ns;
+        tIS       : TIME    :=  0.900 ns;
+        tMRD      : TIME    := 15.000 ns;
+        tRAS      : TIME    := 40.000 ns;
+        tRAP      : TIME    := 20.000 ns;
+        tRC       : TIME    := 65.000 ns;
+        tRFC      : TIME    := 75.000 ns;
+        tRCD      : TIME    := 20.000 ns;
+        tRP       : TIME    := 20.000 ns;
+        tRRD      : TIME    := 15.000 ns;
+        tWR       : TIME    := 15.000 ns;
+        addr_bits : INTEGER := 13;
+        data_bits : INTEGER := 16;
+        cols_bits : INTEGER :=  9
+    );
+    PORT (
+        Dq    : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
+        Dqs   : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
+        Addr  : IN    STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
+        Ba    : IN    STD_LOGIC_VECTOR (1 DOWNTO 0);
+        Clk   : IN    STD_LOGIC;
+        Clk_n : IN    STD_LOGIC;
+        Cke   : IN    STD_LOGIC;
+        Cs_n  : IN    STD_LOGIC;
+        Ras_n : IN    STD_LOGIC;
+        Cas_n : IN    STD_LOGIC;
+        We_n  : IN    STD_LOGIC;
+        Dm    : IN    STD_LOGIC_VECTOR (1 DOWNTO 0)
+    );
+END MT46V16M16;
+
+ARCHITECTURE behave OF MT46V16M16 IS
+    -- Array for Read pipeline
+    TYPE Array_Read_cmnd IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
+    TYPE Array_Read_bank IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
+    TYPE Array_Read_cols IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
+
+    -- Array for Write pipeline
+    TYPE Array_Write_cmnd IS ARRAY (2 DOWNTO 0) OF STD_LOGIC;
+    TYPE Array_Write_bank IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
+    TYPE Array_Write_cols IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
+
+    -- Array for Auto Precharge
+    TYPE Array_Read_precharge  IS ARRAY (3 DOWNTO 0) OF STD_LOGIC;
+    TYPE Array_Write_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC;
+    TYPE Array_Count_precharge IS ARRAY (3 DOWNTO 0) OF INTEGER;
+
+    -- Array for Manual Precharge
+    TYPE Array_A10_precharge  IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
+    TYPE Array_Bank_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
+    TYPE Array_Cmnd_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
+    
+    -- Array for Burst Terminate
+    TYPE Array_Cmnd_bst IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
+
+    -- Array for Memory Access
+    TYPE Array_ram_type IS ARRAY (2**cols_bits - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
+    TYPE Array_ram_pntr IS ACCESS Array_ram_type;
+    TYPE Array_ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF Array_ram_pntr;
+
+    -- Data pair
+    SIGNAL Dq_pair : STD_LOGIC_VECTOR (2 * data_bits - 1 DOWNTO 0);
+    SIGNAL Dm_pair : STD_LOGIC_VECTOR (3 DOWNTO 0);
+
+    -- Mode Register
+    SIGNAL Mode_reg : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
+    
+    -- Command Decode Variables
+    SIGNAL Active_enable, Aref_enable, Burst_term, Ext_mode_enable : STD_LOGIC := '0';
+    SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : STD_LOGIC := '0';
+    
+    -- Burst Length Decode Variables
+    SIGNAL Burst_length_2, Burst_length_4, Burst_length_8, Burst_length_f : STD_LOGIC := '0';
+    
+    -- Cas Latency Decode Variables
+    SIGNAL Cas_latency_15, Cas_latency_2, Cas_latency_25, Cas_latency_3, Cas_latency_4 : STD_LOGIC := '0';
+
+    -- Internal Control Signals
+    SIGNAL Cs_in, Ras_in, Cas_in, We_in : STD_LOGIC := '0';
+
+    -- System Clock
+    SIGNAL Sys_clk : STD_LOGIC := '0';
+
+    -- Dqs buffer
+    SIGNAL Dqs_out : STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
+
+BEGIN
+    -- Strip the strength
+    Cs_in  <= To_X01 (Cs_n);
+    Ras_in <= To_X01 (Ras_n);
+    Cas_in <= To_X01 (Cas_n);
+    We_in  <= To_X01 (We_n);
+    
+    -- Commands Decode
+    Active_enable   <= NOT(Cs_in) AND NOT(Ras_in) AND     Cas_in  AND     We_in;
+    Aref_enable     <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND     We_in;
+    Burst_term      <= NOT(Cs_in) AND     Ras_in  AND     Cas_in  AND NOT(We_in);
+    Ext_mode_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND     Ba(0)  AND NOT(Ba(1));
+    Mode_reg_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND NOT(Ba(0)) AND NOT(Ba(1));
+    Prech_enable    <= NOT(Cs_in) AND NOT(Ras_in) AND     Cas_in  AND NOT(We_in);
+    Read_enable     <= NOT(Cs_in) AND     Ras_in  AND NOT(Cas_in) AND     We_in;
+    Write_enable    <= NOT(Cs_in) AND     Ras_in  AND NOT(Cas_in) AND NOT(We_in);
+
+    -- Burst Length Decode
+    Burst_length_2  <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND     Mode_reg(0);
+    Burst_length_4  <= NOT(Mode_reg(2)) AND     Mode_reg(1)  AND NOT(Mode_reg(0));
+    Burst_length_8  <= NOT(Mode_reg(2)) AND     Mode_reg(1)  AND     Mode_reg(0);
+    Burst_length_f  <=    (Mode_reg(2)) AND     Mode_reg(1)  AND     Mode_reg(0);
+
+    -- CAS Latency Decode
+    Cas_latency_15  <=     Mode_reg(6)  AND NOT(Mode_reg(5)) AND    (Mode_reg(4));
+    Cas_latency_2   <= NOT(Mode_reg(6)) AND     Mode_reg(5)  AND NOT(Mode_reg(4));
+    Cas_latency_25  <=     Mode_reg(6)  AND     Mode_reg(5)  AND NOT(Mode_reg(4));
+    Cas_latency_3   <= NOT(Mode_reg(6)) AND     Mode_reg(5)  AND     Mode_reg(4);
+    Cas_latency_4   <=    (Mode_reg(6)) AND NOT(Mode_reg(5)) AND NOT(Mode_reg(4));
+
+    -- Dqs buffer
+    Dqs <= Dqs_out;
+
+    --
+    -- System Clock
+    --
+    int_clk : PROCESS (Clk, Clk_n)
+        VARIABLE ClkZ, CkeZ : STD_LOGIC := '0';
+    begin
+        IF Clk = '1' AND Clk_n = '0' THEN
+            ClkZ := '1';
+            CkeZ := Cke;
+        ELSIF Clk = '0' AND Clk_n = '1' THEN
+            ClkZ := '0';
+        END IF;
+        Sys_clk <= CkeZ AND ClkZ;
+    END PROCESS;
+
+    --
+    -- Main Process
+    --
+    state_register : PROCESS
+        -- Precharge Variables
+        VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : STD_LOGIC := '0';
+
+        -- Activate Variables
+        VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : STD_LOGIC := '1';
+
+        -- Data IO variables
+        VARIABLE Data_in_enable, Data_out_enable : STD_LOGIC := '0';
+
+        -- Internal address mux variables
+        VARIABLE Cols_brst : STD_LOGIC_VECTOR (2 DOWNTO 0);
+        VARIABLE Prev_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
+        VARIABLE Bank_addr : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
+        VARIABLE Cols_addr : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
+        VARIABLE Rows_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
+        VARIABLE B0_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
+        VARIABLE B1_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
+        VARIABLE B2_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
+        VARIABLE B3_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
+
+        -- DLL Reset variables
+        VARIABLE DLL_enable : STD_LOGIC := '0';
+        VARIABLE DLL_reset : STD_LOGIC := '0';
+        VARIABLE DLL_done : STD_LOGIC := '0';
+        VARIABLE DLL_count : INTEGER := 0;
+        
+        -- Timing Check
+        VARIABLE MRD_chk : TIME := 0 ns;
+        VARIABLE RFC_chk : TIME := 0 ns;
+        VARIABLE RRD_chk : TIME := 0 ns;
+        VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns;
+        VARIABLE RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3 : TIME := 0 ns;
+        VARIABLE RC_chk0, RC_chk1, RC_chk2, RC_chk3 : TIME := 0 ns;
+        VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns;
+        VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns;
+        VARIABLE WR_chk0, WR_chk1, WR_chk2, WR_chk3 : TIME := 0 ns;
+
+        -- Read pipeline variables
+        VARIABLE Read_cmnd : Array_Read_cmnd;
+        VARIABLE Read_bank : Array_Read_bank;
+        VARIABLE Read_cols : Array_Read_cols;
+
+        -- Write pipeline variables
+        VARIABLE Write_cmnd : Array_Write_cmnd;
+        VARIABLE Write_bank : Array_Write_bank;
+        VARIABLE Write_cols : Array_Write_cols;
+
+        -- Auto Precharge variables
+        VARIABLE Read_precharge  : Array_Read_precharge  := ('0' & '0' & '0' & '0');
+        VARIABLE Write_precharge : Array_Write_precharge := ('0' & '0' & '0' & '0');
+        VARIABLE Count_precharge : Array_Count_precharge := ( 0  &  0  &  0  &  0 );
+
+        -- Manual Precharge variables
+        VARIABLE A10_precharge  : Array_A10_precharge;
+        VARIABLE Bank_precharge : Array_Bank_precharge;
+        VARIABLE Cmnd_precharge : Array_Cmnd_precharge;
+
+        -- Burst Terminate variable
+        VARIABLE Cmnd_bst : Array_Cmnd_bst;
+
+        -- Memory Banks
+        VARIABLE Bank0 : Array_ram_stor;
+        VARIABLE Bank1 : Array_ram_stor;
+        VARIABLE Bank2 : Array_ram_stor;
+        VARIABLE Bank3 : Array_ram_stor;
+
+        -- Burst Counter
+        VARIABLE Burst_counter : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
+
+        -- Internal Dqs initialize
+        VARIABLE Dqs_int : STD_LOGIC := '0';
+
+        -- Data buffer for DM Mask
+        VARIABLE Data_buf : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
+
+        --
+        -- Initialize empty rows
+        --
+        PROCEDURE Init_mem (Bank : STD_LOGIC_VECTOR; Row_index : INTEGER) IS
+            VARIABLE i, j : INTEGER := 0;
+        BEGIN
+            IF Bank = "00" THEN
+                IF Bank0 (Row_index) = NULL THEN                        -- Check to see if row empty
+                    Bank0 (Row_index) := NEW Array_ram_type;            -- Open new row for access
+                    FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP           -- Filled row with zeros
+                        FOR j IN (data_bits - 1) DOWNTO 0 LOOP
+                            Bank0 (Row_index) (i) (j) := '0';
+                        END LOOP;
+                    END LOOP;
+                END IF;
+            ELSIF Bank = "01" THEN
+                IF Bank1 (Row_index) = NULL THEN
+                    Bank1 (Row_index) := NEW Array_ram_type;
+                    FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
+                        FOR j IN (data_bits - 1) DOWNTO 0 LOOP
+                            Bank1 (Row_index) (i) (j) := '0';
+                        END LOOP;
+                    END LOOP;
+                END IF;
+            ELSIF Bank = "10" THEN
+                IF Bank2 (Row_index) = NULL THEN
+                    Bank2 (Row_index) := NEW Array_ram_type;
+                    FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
+                        FOR j IN (data_bits - 1) DOWNTO 0 LOOP
+                            Bank2 (Row_index) (i) (j) := '0';
+                        END LOOP;
+                    END LOOP;
+                END IF;
+            ELSIF Bank = "11" THEN
+                IF Bank3 (Row_index) = NULL THEN
+                    Bank3 (Row_index) := NEW Array_ram_type;
+                    FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
+                        FOR j IN (data_bits - 1) DOWNTO 0 LOOP
+                            Bank3 (Row_index) (i) (j) := '0';
+                        END LOOP;
+                    END LOOP;
+                END IF;
+            END IF;
+        END;
+
+        --
+        -- Burst Counter
+        --
+        PROCEDURE Burst_decode IS
+            VARIABLE Cols_temp : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0) := (OTHERS => '0');
+        BEGIN
+            -- Advance burst counter
+            Burst_counter := Burst_counter + 1;
+
+            -- Burst Type
+            IF Mode_reg (3) = '0' THEN
+                Cols_temp := Cols_addr + 1;
+            ELSIF Mode_reg (3) = '1' THEN
+                Cols_temp (2) := Burst_counter (2) XOR Cols_brst (2);
+                Cols_temp (1) := Burst_counter (1) XOR Cols_brst (1);
+                Cols_temp (0) := Burst_counter (0) XOR Cols_brst (0);
+            END IF;
+
+            -- Burst Length
+            IF Burst_length_2 = '1' THEN
+                Cols_addr (0) := Cols_temp (0);
+            ELSIF Burst_length_4 = '1' THEN
+                Cols_addr (1 DOWNTO 0) := Cols_temp (1 DOWNTO 0);
+            ELSIF Burst_length_8 = '1' THEN
+                Cols_addr (2 DOWNTO 0) := Cols_temp (2 DOWNTO 0);
+            ELSE
+                Cols_addr := Cols_temp;
+            END IF;
+
+            -- Data counter
+            IF Burst_length_2 = '1' THEN
+                IF Burst_counter >= 2 THEN
+                    IF Data_in_enable = '1' THEN
+                        Data_in_enable := '0';
+                    ELSIF Data_out_enable = '1' THEN
+                        Data_out_enable := '0';
+                    END IF;
+                END IF;
+            ELSIF Burst_length_4 = '1' THEN
+                IF Burst_counter >= 4 THEN
+                    IF Data_in_enable = '1' THEN
+                        Data_in_enable := '0';
+                    ELSIF Data_out_enable = '1' THEN
+                        Data_out_enable := '0';
+                    END IF;
+                END IF;
+            ELSIF Burst_length_8 = '1' THEN
+                IF Burst_counter >= 8 THEN
+                    IF Data_in_enable = '1' THEN
+                        Data_in_enable := '0';
+                    ELSIF Data_out_enable = '1' THEN
+                        Data_out_enable := '0';
+                    END IF;
+                END IF;
+            END IF;
+        END;
+
+    BEGIN
+        WAIT ON Sys_clk;
+
+        --
+        -- Manual Precharge Pipeline
+        --
+        IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
+            -- A10 Precharge Pipeline
+            A10_precharge(0) := A10_precharge(1);
+            A10_precharge(1) := A10_precharge(2);
+            A10_precharge(2) := A10_precharge(3);
+            A10_precharge(3) := A10_precharge(4);
+            A10_precharge(4) := A10_precharge(5);
+            A10_precharge(5) := A10_precharge(6);
+            A10_precharge(6) := A10_precharge(7);
+            A10_precharge(7) := A10_precharge(8);
+            A10_precharge(8) := '0';
+
+            -- Bank Precharge Pipeline
+            Bank_precharge(0) := Bank_precharge(1);
+            Bank_precharge(1) := Bank_precharge(2);
+            Bank_precharge(2) := Bank_precharge(3);
+            Bank_precharge(3) := Bank_precharge(4);
+            Bank_precharge(4) := Bank_precharge(5);
+            Bank_precharge(5) := Bank_precharge(6);
+            Bank_precharge(6) := Bank_precharge(7);
+            Bank_precharge(7) := Bank_precharge(8);
+            Bank_precharge(8) := "00";
+
+            -- Command Precharge Pipeline
+            Cmnd_precharge(0) := Cmnd_precharge(1);
+            Cmnd_precharge(1) := Cmnd_precharge(2);
+            Cmnd_precharge(2) := Cmnd_precharge(3);
+            Cmnd_precharge(3) := Cmnd_precharge(4);
+            Cmnd_precharge(4) := Cmnd_precharge(5);
+            Cmnd_precharge(5) := Cmnd_precharge(6);
+            Cmnd_precharge(6) := Cmnd_precharge(7);
+            Cmnd_precharge(7) := Cmnd_precharge(8);
+            Cmnd_precharge(8) := '0';
+
+            -- Terminate Read if same bank or all banks
+            IF ((Cmnd_precharge (0) = '1') AND
+                (Bank_precharge (0) = Bank_addr OR A10_precharge (0) = '1') AND
+                (Data_out_enable = '1')) THEN
+                Data_out_enable := '0';
+            END IF;
+        END IF;
+
+        --
+        -- Burst Terminate Pipeline
+        --
+        IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
+            -- Burst Terminate pipeline
+            Cmnd_bst (0) := Cmnd_bst (1);
+            Cmnd_bst (1) := Cmnd_bst (2);
+            Cmnd_bst (2) := Cmnd_bst (3);
+            Cmnd_bst (3) := Cmnd_bst (4);
+            Cmnd_bst (4) := Cmnd_bst (5);
+            Cmnd_bst (5) := Cmnd_bst (6);
+            Cmnd_bst (6) := Cmnd_bst (7);
+            Cmnd_bst (7) := Cmnd_bst (8);
+            Cmnd_bst (8) := '0';
+
+            -- Terminate current Read
+            IF ((Cmnd_bst  (0) = '1') AND (Data_out_enable = '1')) THEN
+                Data_out_enable := '0';
+            END IF;
+        END IF;
+
+        --
+        -- Dq and Dqs Drivers
+        --
+        IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
+            -- Read Command Pipeline
+            Read_cmnd (0) := Read_cmnd (1);
+            Read_cmnd (1) := Read_cmnd (2);
+            Read_cmnd (2) := Read_cmnd (3);
+            Read_cmnd (3) := Read_cmnd (4);
+            Read_cmnd (4) := Read_cmnd (5);
+            Read_cmnd (5) := Read_cmnd (6);
+            Read_cmnd (6) := Read_cmnd (7);
+            Read_cmnd (7) := Read_cmnd (8);
+            Read_cmnd (8) := '0';
+
+            -- Read Bank Pipeline
+            Read_bank (0) := Read_bank (1);
+            Read_bank (1) := Read_bank (2);
+            Read_bank (2) := Read_bank (3);
+            Read_bank (3) := Read_bank (4);
+            Read_bank (4) := Read_bank (5);
+            Read_bank (5) := Read_bank (6);
+            Read_bank (6) := Read_bank (7);
+            Read_bank (7) := Read_bank (8);
+            Read_bank (8) := "00";
+
+            -- Read Column Pipeline
+            Read_cols (0) := Read_cols (1);
+            Read_cols (1) := Read_cols (2);
+            Read_cols (2) := Read_cols (3);
+            Read_cols (3) := Read_cols (4);
+            Read_cols (4) := Read_cols (5);
+            Read_cols (5) := Read_cols (6);
+            Read_cols (6) := Read_cols (7);
+            Read_cols (7) := Read_cols (8);
+            Read_cols (8) := (OTHERS => '0');
+
+            -- Initialize Read command
+            IF Read_cmnd (0) = '1' THEN
+                Data_out_enable := '1';
+                Bank_addr := Read_bank (0);
+                Cols_addr := Read_cols (0);
+                Cols_brst := Cols_addr (2 DOWNTO 0);
+                Burst_counter := (OTHERS => '0');
+
+                -- Row address mux
+                CASE Bank_addr IS
+                    WHEN "00"   => Rows_addr := B0_row_addr;
+                    WHEN "01"   => Rows_addr := B1_row_addr;
+                    WHEN "10"   => Rows_addr := B2_row_addr;
+                    WHEN OTHERS => Rows_addr := B3_row_addr;
+                END CASE;
+            END IF;
+
+            -- Toggle Dqs during Read command
+            IF Data_out_enable = '1' THEN
+                Dqs_int := '0';
+                IF Dqs_out = "00" THEN
+                    Dqs_out <= "11";
+                ELSIF Dqs_out = "11" THEN
+                    Dqs_out <= "00";
+                ELSE
+                    Dqs_out <= "00";
+                END IF;
+            ELSIF Data_out_enable = '0' AND Dqs_int = '0' THEN
+                Dqs_out <= "ZZ";
+            END IF;
+
+            -- Initialize Dqs for Read command
+            IF Read_cmnd (2) = '1' THEN
+                IF Data_out_enable = '0' THEN
+                    Dqs_int := '1';
+                    Dqs_out <= "00";
+                END IF;
+            END IF;
+
+            -- Read Latch
+            IF Data_out_enable = '1' THEN
+                -- Initialize Memory
+                Init_mem (Bank_addr, CONV_INTEGER(Rows_addr));
+                
+                -- Output Data
+                CASE Bank_addr IS
+                    WHEN "00"   => Dq <= Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+                    WHEN "01"   => Dq <= Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+                    WHEN "10"   => Dq <= Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+                    WHEN OTHERS => Dq <= Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+                END CASE;
+
+                --  Increase Burst Counter
+                Burst_decode;
+            ELSE
+                Dq <= (OTHERS => 'Z');
+            END IF;
+        END IF;
+
+        --
+        -- Write FIFO and DM Mask Logic
+        --
+        IF Sys_clk'EVENT AND Sys_clk = '1' THEN
+            -- Write command pipeline
+            Write_cmnd (0) := Write_cmnd (1);
+            Write_cmnd (1) := Write_cmnd (2);
+            Write_cmnd (2) := '0';
+
+            -- Write command pipeline
+            Write_bank (0) := Write_bank (1);
+            Write_bank (1) := Write_bank (2);
+            Write_bank (2) := "00";
+
+            -- Write column pipeline
+            Write_cols (0) := Write_cols (1);
+            Write_cols (1) := Write_cols (2);
+            Write_cols (2) := (OTHERS => '0');
+
+            -- Initialize Write command
+            IF Write_cmnd (0) = '1' THEN
+                Data_in_enable := '1';
+                Bank_addr := Write_bank (0);
+                Cols_addr := Write_cols (0);
+                Cols_brst := Cols_addr (2 DOWNTO 0);
+                Burst_counter := (OTHERS => '0');
+
+                -- Row address mux
+                CASE Bank_addr IS
+                    WHEN "00"   => Rows_addr := B0_row_addr;
+                    WHEN "01"   => Rows_addr := B1_row_addr;
+                    WHEN "10"   => Rows_addr := B2_row_addr;
+                    WHEN OTHERS => Rows_addr := B3_row_addr;
+                END CASE;
+            END IF;
+
+            -- Write data
+            IF Data_in_enable = '1' THEN
+                -- Initialize memory
+                Init_mem (Bank_addr, CONV_INTEGER(Rows_addr));
+                
+                -- Write first data
+                IF Dm_pair (1) = '0' OR Dm_pair (0) = '0' THEN
+                    -- Data Buffer
+                    CASE Bank_addr IS
+                        WHEN "00"   => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+                        WHEN "01"   => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+                        WHEN "10"   => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+                        WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+                    END CASE;
+
+                    -- Perform DM Mask
+                    IF Dm_pair (0) = '0' THEN
+                        Data_buf ( 7 DOWNTO 0) := Dq_pair ( 7 DOWNTO 0);
+                    END IF;
+                    IF Dm_pair (1) = '0' THEN
+                        Data_buf (15 DOWNTO 8) := Dq_pair (15 DOWNTO 8);
+                    END IF;
+
+                    -- Write Data
+                    CASE Bank_addr IS
+                        WHEN "00"   => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
+                        WHEN "01"   => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
+                        WHEN "10"   => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
+                        WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
+                    END CASE;
+                END IF;
+
+                --  Increase Burst Counter
+                Burst_decode;
+
+                -- Write second data
+                IF Dm_pair (3) = '0' OR Dm_pair (2) = '0' THEN
+                    -- Data Buffer
+                    CASE Bank_addr IS
+                        WHEN "00"   => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+                        WHEN "01"   => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+                        WHEN "10"   => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+                        WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+                    END CASE;
+
+                    -- Perform DM Mask
+                    IF Dm_pair (2) = '0' THEN
+                        Data_buf ( 7 DOWNTO 0) := Dq_pair (23 DOWNTO 16);
+                    END IF;
+                    IF Dm_pair (3) = '0' THEN
+                        Data_buf (15 DOWNTO 8) := Dq_pair (31 DOWNTO 24);
+                    END IF;
+
+                    -- Write Data
+                    CASE Bank_addr IS
+                        WHEN "00"   => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
+                        WHEN "01"   => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
+                        WHEN "10"   => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
+                        WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
+                    END CASE;
+                END IF;
+                
+                -- Increase Burst Counter
+                Burst_decode;
+
+                -- tWR start and tWTR check
+                IF Dm_pair (3 DOWNTO 2) = "00" OR Dm_pair (1 DOWNTO 0) = "00" THEN
+                    CASE Bank_addr IS
+                        WHEN "00"   => WR_chk0 := NOW;
+                        WHEN "01"   => WR_chk1 := NOW;
+                        WHEN "10"   => WR_chk2 := NOW;
+                        WHEN OTHERS => WR_chk3 := NOW;
+                    END CASE;
+
+                    -- tWTR check
+                    ASSERT (Read_enable = '0')
+                        REPORT "tWTR violation during Read"
+                        SEVERITY WARNING;
+                END IF;
+            END IF;
+        END IF;
+
+        --
+        -- Auto Precharge Calculation
+        --
+        IF Sys_clk'EVENT AND Sys_clk = '1' THEN
+            -- Precharge counter
+            IF Read_precharge (0) = '1' OR Write_precharge (0) = '1' THEN
+                Count_precharge (0) := Count_precharge (0) + 1;
+            END IF;
+            IF Read_precharge (1) = '1' OR Write_precharge (1) = '1' THEN
+                Count_precharge (1) := Count_precharge (1) + 1;
+            END IF;
+            IF Read_precharge (2) = '1' OR Write_precharge (2) = '1' THEN
+                Count_precharge (2) := Count_precharge (2) + 1;
+            END IF;
+            IF Read_precharge (3) = '1' OR Write_precharge (3) = '1' THEN
+                Count_precharge (3) := Count_precharge (3) + 1;
+            END IF;
+
+            -- Read with AutoPrecharge Calculation
+            --      The device start internal precharge when:
+            --          1.  Meet tRAS requirement
+            --          2.  BL/2 cycles after command
+            IF ((Read_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN
+                IF ((Burst_length_2 = '1' AND Count_precharge(0) >= 1)  OR
+                    (Burst_length_4 = '1' AND Count_precharge(0) >= 2)  OR
+                    (Burst_length_8 = '1' AND Count_precharge(0) >= 4)) THEN
+                    Pc_b0 := '1';
+                    Act_b0 := '0';
+                    RP_chk0 := NOW;
+                    Read_precharge(0) := '0';
+                END IF;
+            END IF;
+            IF ((Read_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN
+                IF ((Burst_length_2 = '1' AND Count_precharge(1) >= 1)  OR
+                    (Burst_length_4 = '1' AND Count_precharge(1) >= 2)  OR
+                    (Burst_length_8 = '1' AND Count_precharge(1) >= 4)) THEN
+                    Pc_b1 := '1';
+                    Act_b1 := '0';
+                    RP_chk1 := NOW;
+                    Read_precharge(1) := '0';
+                END IF;
+            END IF;
+            IF ((Read_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN
+                IF ((Burst_length_2 = '1' AND Count_precharge(2) >= 1)  OR
+                    (Burst_length_4 = '1' AND Count_precharge(2) >= 2)  OR
+                    (Burst_length_8 = '1' AND Count_precharge(2) >= 4)) THEN
+                    Pc_b2 := '1';
+                    Act_b2 := '0';
+                    RP_chk2 := NOW;
+                    Read_precharge(2) := '0';
+                END IF;
+            END IF;
+            IF ((Read_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN
+                IF ((Burst_length_2 = '1' AND Count_precharge(3) >= 1)  OR
+                    (Burst_length_4 = '1' AND Count_precharge(3) >= 2)  OR
+                    (Burst_length_8 = '1' AND Count_precharge(3) >= 4)) THEN
+                    Pc_b3 := '1';
+                    Act_b3 := '0';
+                    RP_chk3 := NOW;
+                    Read_precharge(3) := '0';
+                END IF;
+            END IF;
+
+            -- Write with AutoPrecharge Calculation
+            --      The device start internal precharge when:
+            --          1.  Meet tRAS requirement
+            --          2.  Two clock after last burst
+            -- Since tWR is time base, the model will compensate tRP
+            IF ((Write_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN
+                IF ((Burst_length_2 = '1' AND Count_precharge (0) >= 4) OR
+                    (Burst_length_4 = '1' AND Count_precharge (0) >= 5) OR
+                    (Burst_length_8 = '1' AND Count_precharge (0) >= 7)) THEN
+                    Pc_b0 := '1';
+                    Act_b0 := '0';
+                    RP_chk0 := NOW - ((2 * tCK) - tWR);
+                    Write_precharge(0) := '0';
+                END IF;
+            END IF;
+            IF ((Write_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN
+                IF ((Burst_length_2 = '1' AND Count_precharge (1) >= 4) OR
+                    (Burst_length_4 = '1' AND Count_precharge (1) >= 5) OR
+                    (Burst_length_8 = '1' AND Count_precharge (1) >= 7)) THEN
+                    Pc_b1 := '1';
+                    Act_b1 := '0';
+                    RP_chk1 := NOW - ((2 * tCK) - tWR);
+                    Write_precharge(1) := '0';
+                END IF;
+            END IF;
+            IF ((Write_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN
+                IF ((Burst_length_2 = '1' AND Count_precharge (2) >= 4) OR
+                    (Burst_length_4 = '1' AND Count_precharge (2) >= 5) OR
+                    (Burst_length_8 = '1' AND Count_precharge (2) >= 7)) THEN
+                    Pc_b2 := '1';
+                    Act_b2 := '0';
+                    RP_chk2 := NOW - ((2 * tCK) - tWR);
+                    Write_precharge(2) := '0';
+                END IF;
+            END IF;
+            IF ((Write_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN
+                IF ((Burst_length_2 = '1' AND Count_precharge (3) >= 4) OR
+                    (Burst_length_4 = '1' AND Count_precharge (3) >= 5) OR
+                    (Burst_length_8 = '1' AND Count_precharge (3) >= 7)) THEN
+                    Pc_b3 := '1';
+                    Act_b3 := '0';
+                    RP_chk3 := NOW - ((2 * tCK) - tWR);
+                    Write_precharge(3) := '0';
+                END IF;
+            END IF;
+        END IF;
+        
+        --
+        -- DLL Counter
+        --
+        IF Sys_clk'EVENT AND Sys_clk = '1' THEN
+            IF (DLL_Reset = '1' AND DLL_done = '0') THEN
+                DLL_count := DLL_count + 1;
+                IF (DLL_count >= 200) THEN
+                    DLL_done := '1';
+                END IF;
+            END IF;
+        END IF;
+
+        --
+        -- Control Logic
+        --
+        IF Sys_clk'EVENT AND Sys_clk = '1' THEN
+            -- Auto Refresh
+            IF Aref_enable = '1' THEN
+                -- Auto Refresh to Auto Refresh
+                ASSERT (NOW - RFC_chk >= tRFC)
+                    REPORT "tRFC violation during Auto Refresh"
+                    SEVERITY WARNING;
+
+                -- Precharge to Auto Refresh
+                ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
+                        (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
+                    REPORT "tRP violation during Auto Refresh"
+                    SEVERITY WARNING;
+
+                -- Precharge to Auto Refresh
+                ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
+                    REPORT "All banks must be Precharge before Auto Refresh"
+                    SEVERITY WARNING;
+
+                -- Record current tRFC time
+                RFC_chk := NOW;
+            END IF;
+
+            -- Extended Load Mode Register
+            IF Ext_mode_enable = '1' THEN
+                IF (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') THEN
+                    IF (Addr (0) = '0') THEN
+                        DLL_enable := '1';
+                    ELSE
+                        DLL_enable := '0';
+                    END IF;
+                END IF;
+                
+                -- Precharge to EMR
+                ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
+                    REPORT "All bank must be Precharged before Extended Mode Register"
+                    SEVERITY WARNING;
+                
+                -- Precharge to EMR
+                ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
+                        (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
+                    REPORT "tRP violation during Extended Load Register"
+                    SEVERITY WARNING;
+
+                -- LMR/EMR to EMR
+                ASSERT (NOW - MRD_chk >= tMRD)
+                    REPORT "tMRD violation during Extended Mode Register"
+                    SEVERITY WARNING;
+
+                -- Record current tMRD time
+                MRD_chk := NOW;
+            END IF;
+
+            -- Load Mode Register
+            IF Mode_reg_enable = '1' THEN
+                -- Register mode
+                Mode_reg <= Addr;
+                
+                -- DLL Reset
+                IF (DLL_enable = '1' AND Addr (8) = '1') THEN
+                    DLL_reset := '1';
+                    DLL_done  := '0';
+                    DLL_count := 0;
+                ELSIF (DLL_enable = '1' AND DLL_reset = '0' AND Addr (8) = '0') THEN
+                    ASSERT (FALSE)
+                        REPORT "DLL is ENABLE: DLL RESET is require"
+                        SEVERITY WARNING;
+                ELSIF (DLL_enable = '0' AND Addr (8) = '1') THEN
+                    ASSERT (FALSE)
+                        REPORT "DLL is DISABLE: DLL RESET will be ignored"
+                        SEVERITY WARNING;
+                END IF;
+
+                -- Precharge to LMR
+                ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
+                    REPORT "All bank must be Precharged before Load Mode Register"
+                    SEVERITY WARNING;
+
+                -- Precharge to EMR
+                ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
+                        (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
+                    REPORT "tRP violation during Load Mode Register"
+                    SEVERITY WARNING;
+
+                -- LMR/ELMR to LMR
+                ASSERT (NOW - MRD_chk >= tMRD)
+                    REPORT "tMRD violation during Load Mode Register"
+                    SEVERITY WARNING;
+
+                -- Check for invalid Burst Length
+                ASSERT ((Addr (2 DOWNTO 0) = "001") OR      -- BL = 2
+                        (Addr (2 DOWNTO 0) = "010") OR      -- BL = 4
+                        (Addr (2 DOWNTO 0) = "011"))        -- BL = 8
+                    REPORT "Invalid Burst Length during Load Mode Register"
+                    SEVERITY WARNING;
+
+                -- Check for invalid CAS Latency
+                ASSERT ((Addr (6 DOWNTO 4) = "010") OR      -- CL = 2.0
+                        (Addr (6 DOWNTO 4) = "110"))        -- CL = 2.5
+                    REPORT "Invalid CAS Latency during Load Mode Register"
+                    SEVERITY WARNING;
+
+                -- Record current tMRD time
+                MRD_chk := NOW;
+            END IF;
+
+            -- Active Block (latch Bank and Row Address)
+            IF Active_enable = '1' THEN
+                -- Activate an OPEN bank can corrupt data
+                ASSERT ((Ba = "00" AND Act_b0 = '0') OR
+                        (Ba = "01" AND Act_b1 = '0') OR
+                        (Ba = "10" AND Act_b2 = '0') OR
+                        (Ba = "11" AND Act_b3 = '0'))
+                    REPORT "Bank is already activated - data can be corrupted"
+                    SEVERITY WARNING;
+
+                -- Activate Bank 0
+                IF Ba = "00" AND Pc_b0 = '1' THEN
+                    -- Activate to Activate (same bank)
+                    ASSERT (NOW - RC_chk0 >= tRC)
+                        REPORT "tRC violation during Activate Bank 0"
+                        SEVERITY WARNING;
+
+                    -- Precharge to Active
+                    ASSERT (NOW - RP_chk0 >= tRP)
+                        REPORT "tRP violation during Activate Bank 0"
+                        SEVERITY WARNING;
+
+                    -- Record Variables for checking violation
+                    Act_b0 := '1';
+                    Pc_b0 := '0';
+                    B0_row_addr := Addr;
+                    RC_chk0 := NOW;
+                    RCD_chk0 := NOW;
+                    RAS_chk0 := NOW;
+                    RAP_chk0 := NOW;
+                END IF;
+
+                -- Activate Bank 1
+                IF Ba = "01" AND Pc_b1 = '1' THEN
+                    -- Activate to Activate (same bank)
+                    ASSERT (NOW - RC_chk1 >= tRC)
+                        REPORT "tRC violation during Activate Bank 1"
+                        SEVERITY WARNING;
+
+                    -- Precharge to Active
+                    ASSERT (NOW - RP_chk1 >= tRP)
+                        REPORT "tRP violation during Activate Bank 1"
+                        SEVERITY WARNING;
+
+                    -- Record Variables for checking violation
+                    Act_b1 := '1';
+                    Pc_b1 := '0';
+                    B1_row_addr := Addr;
+                    RC_chk1 := NOW;
+                    RCD_chk1 := NOW;
+                    RAS_chk1 := NOW;
+                    RAP_chk1 := NOW;
+                END IF;
+
+                -- Activate Bank 2
+                IF Ba = "10" AND Pc_b2 = '1' THEN
+                    -- Activate to Activate (same bank)
+                    ASSERT (NOW - RC_chk2 >= tRC)
+                        REPORT "tRC violation during Activate Bank 2"
+                        SEVERITY WARNING;
+
+                    -- Precharge to Active
+                    ASSERT (NOW - RP_chk2 >= tRP)
+                        REPORT "tRP violation during Activate Bank 2"
+                        SEVERITY WARNING;
+
+                    -- Record Variables for checking violation
+                    Act_b2 := '1';
+                    Pc_b2 := '0';
+                    B2_row_addr := Addr;
+                    RC_chk2 := NOW;
+                    RCD_chk2 := NOW;
+                    RAS_chk2 := NOW;
+                    RAP_chk2 := NOW;
+                END IF;
+
+                -- Activate Bank 3
+                IF Ba = "11" AND Pc_b3 = '1' THEN
+                    -- Activate to Activate (same bank)
+                    ASSERT (NOW - RC_chk3 >= tRC)
+                        REPORT "tRC violation during Activate Bank 3"
+                        SEVERITY WARNING;
+
+                    -- Precharge to Active
+                    ASSERT (NOW - RP_chk3 >= tRP)
+                        REPORT "tRP violation during Activate Bank 3"
+                        SEVERITY WARNING;
+
+                    -- Record Variables for checking violation
+                    Act_b3 := '1';
+                    Pc_b3 := '0';
+                    B3_row_addr := Addr;
+                    RC_chk3 := NOW;
+                    RCD_chk3 := NOW;
+                    RAS_chk3 := NOW;
+                    RAP_chk3 := NOW;
+                END IF;
+
+                -- Activate Bank A to Activate Bank B
+                IF (Prev_bank /= Ba) THEN
+                    ASSERT (NOW - RRD_chk >= tRRD)
+                        REPORT "tRRD violation during Activate"
+                        SEVERITY WARNING;
+                END IF;
+                
+                -- AutoRefresh to Activate
+                ASSERT (NOW - RFC_chk >= tRFC)
+                    REPORT "tRFC violation during Activate"
+                    SEVERITY WARNING;
+                
+                -- Record Variables for Checking Violation
+                RRD_chk := NOW;
+                Prev_bank := Ba;
+            END IF;
+
+            -- Precharge Block - Consider NOP if bank already precharged or in process of precharging
+            IF Prech_enable = '1' THEN
+                -- EMR or LMR to Precharge
+                ASSERT (NOW - MRD_chk >= tMRD)
+                    REPORT "tMRD violation during Precharge"
+                    SEVERITY WARNING;
+
+                -- Precharge Bank 0
+                IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "00")) AND Act_b0 = '1') THEN
+                    Act_b0 := '0';
+                    Pc_b0 := '1';
+                    RP_chk0 := NOW;
+
+                    -- Activate to Precharge bank 0
+                    ASSERT (NOW - RAS_chk0 >= tRAS)
+                        REPORT "tRAS violation during Precharge"
+                        SEVERITY WARNING;
+
+                    -- tWR violation check for Write
+                    ASSERT (NOW - WR_chk0 >= tWR)
+                        REPORT "tWR violation during Precharge"
+                        SEVERITY WARNING;
+                END IF;
+
+                -- Precharge Bank 1
+                IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "01")) AND Act_b1 = '1') THEN
+                    Act_b1 := '0';
+                    Pc_b1 := '1';
+                    RP_chk1 := NOW;
+
+                    -- Activate to Precharge
+                    ASSERT (NOW - RAS_chk1 >= tRAS)
+                        REPORT "tRAS violation during Precharge"
+                        SEVERITY WARNING;
+
+                    -- tWR violation check for Write
+                    ASSERT (NOW - WR_chk1 >= tWR)
+                        REPORT "tWR violation during Precharge"
+                        SEVERITY WARNING;
+                END IF;
+
+                -- Precharge Bank 2
+                IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "10")) AND Act_b2 = '1') THEN
+                    Act_b2 := '0';
+                    Pc_b2 := '1';
+                    RP_chk2 := NOW;
+
+                    -- Activate to Precharge
+                    ASSERT (NOW - RAS_chk2 >= tRAS)
+                        REPORT "tRAS violation during Precharge"
+                        SEVERITY WARNING;
+
+                    -- tWR violation check for Write
+                    ASSERT (NOW - WR_chk2 >= tWR)
+                        REPORT "tWR violation during Precharge"
+                        SEVERITY WARNING;
+                END IF;
+
+                -- Precharge Bank 3
+                IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "11")) AND Act_b3 = '1') THEN
+                    Act_b3 := '0';
+                    Pc_b3 := '1';
+                    RP_chk3 := NOW;
+
+                    -- Activate to Precharge
+                    ASSERT (NOW - RAS_chk3 >= tRAS)
+                        REPORT "tRAS violation during Precharge"
+                        SEVERITY WARNING;
+
+                    -- tWR violation check for Write
+                    ASSERT (NOW - WR_chk3 >= tWR)
+                        REPORT "tWR violation during Precharge"
+                        SEVERITY WARNING;
+                END IF;
+
+                -- Pipeline for READ
+                IF CAS_latency_15 = '1' THEN
+                    A10_precharge  (3) := Addr(10);
+                    Bank_precharge (3) := Ba;
+                    Cmnd_precharge (3) := '1';
+                ELSIF CAS_latency_2 = '1' THEN
+                    A10_precharge  (4) := Addr(10);
+                    Bank_precharge (4) := Ba;
+                    Cmnd_precharge (4) := '1';
+                ELSIF CAS_latency_25 = '1' THEN
+                    A10_precharge  (5) := Addr(10);
+                    Bank_precharge (5) := Ba;
+                    Cmnd_precharge (5) := '1';
+                ELSIF CAS_latency_3 = '1' THEN
+                    A10_precharge  (6) := Addr(10);
+                    Bank_precharge (6) := Ba;
+                    Cmnd_precharge (6) := '1';
+                ELSIF CAS_latency_4 = '1' THEN
+                    A10_precharge  (8) := Addr(10);
+                    Bank_precharge (8) := Ba;
+                    Cmnd_precharge (8) := '1';
+                END IF;
+            END IF;
+
+            -- Burst Terminate
+            IF Burst_term = '1' THEN
+                -- Pipeline for Read
+                IF CAS_latency_15 = '1' THEN
+                    Cmnd_bst (3) := '1';
+                ELSIF CAS_latency_2 = '1' THEN
+                    Cmnd_bst (4) := '1';
+                ELSIF CAS_latency_25 = '1' THEN
+                    Cmnd_bst (5) := '1';
+                ELSIF CAS_latency_3 = '1' THEN
+                    Cmnd_bst (6) := '1';
+                ELSIF CAS_latency_4 = '1' THEN
+                    Cmnd_bst (8) := '1';
+                END IF;
+
+                -- Terminate Write
+                ASSERT (Data_in_enable = '0')
+                    REPORT "It's illegal to Burst Terminate a Write"
+                    SEVERITY WARNING;
+
+                -- Terminate Read with Auto Precharge
+                ASSERT (Read_precharge (0) = '0' AND Read_precharge (1) = '0' AND
+                        Read_precharge (2) = '0' AND Read_precharge (3) = '0')
+                    REPORT "It's illegal to Burst Terminate a Read with Auto Precharge"
+                    SEVERITY WARNING;
+            END IF;
+
+            -- Read Command
+            IF Read_enable = '1' THEN
+                -- CAS Latency Pipeline
+                IF Cas_latency_15 = '1' THEN
+                    Read_cmnd (3) := '1';
+                    Read_bank (3) := Ba;
+                    Read_cols (3) := Addr (8 DOWNTO 0);
+                ELSIF Cas_latency_2 = '1' THEN
+                    Read_cmnd (4) := '1';
+                    Read_bank (4) := Ba;
+                    Read_cols (4) := Addr (8 DOWNTO 0);
+                ELSIF Cas_latency_25 = '1' THEN
+                    Read_cmnd (5) := '1';
+                    Read_bank (5) := Ba;
+                    Read_cols (5) := Addr (8 DOWNTO 0);
+                ELSIF Cas_latency_3 = '1' THEN
+                    Read_cmnd (6) := '1';
+                    Read_bank (6) := Ba;
+                    Read_cols (6) := Addr (8 DOWNTO 0);
+                ELSIF Cas_latency_4 = '1' THEN
+                    Read_cmnd (8) := '1';
+                    Read_bank (8) := Ba;
+                    Read_cols (8) := Addr (8 DOWNTO 0);
+                END IF;
+
+                -- Write to Read: Terminate Write Immediately
+                IF Data_in_enable = '1' THEN
+                    Data_in_enable := '0';
+                END IF;
+
+                -- Interrupting a Read with Auto Precharge (same bank only)
+                ASSERT (Read_precharge(CONV_INTEGER(Ba)) = '0')
+                    REPORT "It's illegal to interrupt a Read with Auto Precharge"
+                    SEVERITY WARNING;
+
+                -- Activate to Read
+                ASSERT ((Ba = "00" AND Act_b0 = '1') OR
+                        (Ba = "01" AND Act_b1 = '1') OR
+                        (Ba = "10" AND Act_b2 = '1') OR
+                        (Ba = "11" AND Act_b3 = '1'))
+                    REPORT "Bank is not Activated for Read"
+                    SEVERITY WARNING;
+
+                -- Activate to Read without Auto Precharge
+                IF Addr (10) = '0' THEN
+                    ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR
+                            (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR
+                            (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR
+                            (Ba = "11" AND NOW - RCD_chk3 >= tRCD))
+                        REPORT "tRCD violation during Read"
+                        SEVERITY WARNING;
+                END IF;
+
+                -- Activate to Read with Auto Precharge
+                IF Addr (10) = '1' THEN
+                    ASSERT ((Ba = "00" AND NOW - RAP_chk0 >= tRAP) OR
+                            (Ba = "01" AND NOW - RAP_chk1 >= tRAP) OR
+                            (Ba = "10" AND NOW - RAP_chk2 >= tRAP) OR
+                            (Ba = "11" AND NOW - RAP_chk3 >= tRAP))
+                        REPORT "tRAP violation during Read"
+                        SEVERITY WARNING;
+                END IF;
+
+                -- Auto precharge
+                IF Addr (10) = '1' THEN
+                    Read_precharge (Conv_INTEGER(Ba)) := '1';
+                    Count_precharge (Conv_INTEGER(Ba)) := 0;
+                END IF;
+
+                -- DLL Check
+                IF (DLL_reset = '1') THEN
+                    ASSERT (DLL_done = '1')
+                        REPORT "DLL RESET not complete"
+                        SEVERITY WARNING;
+                END IF;
+            END IF;
+
+            -- Write Command
+            IF Write_enable = '1' THEN
+                -- Pipeline for Write
+                Write_cmnd (2) := '1';
+                Write_bank (2) := Ba;
+                Write_cols (2) := Addr (8 DOWNTO 0);
+
+                -- Interrupting a Write with Auto Precharge (same bank only)
+                ASSERT (Write_precharge(CONV_INTEGER(Ba)) = '0')
+                    REPORT "It's illegal to interrupt a Write with Auto Precharge"
+                    SEVERITY WARNING;
+
+                -- Activate to Write
+                ASSERT ((Ba = "00" AND Act_b0 = '1') OR
+                        (Ba = "01" AND Act_b1 = '1') OR
+                        (Ba = "10" AND Act_b2 = '1') OR
+                        (Ba = "11" AND Act_b3 = '1'))
+                    REPORT "Bank is not Activated for Write"
+                    SEVERITY WARNING;
+
+                -- Activate to Write
+                ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR
+                        (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR
+                        (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR
+                        (Ba = "11" AND NOW - RCD_chk3 >= tRCD))
+                    REPORT "tRCD violation during Write"
+                    SEVERITY WARNING;
+
+                -- Auto precharge
+                IF Addr (10) = '1' THEN
+                    Write_precharge (Conv_INTEGER(Ba)) := '1';
+                    Count_precharge (Conv_INTEGER(Ba)) := 0;
+                END IF;
+            END IF;
+        END IF;
+    END PROCESS;
+
+    --
+    -- Dqs Receiver
+    --
+    dqs_rcvrs : PROCESS
+        VARIABLE Dm_temp : STD_LOGIC_VECTOR (1 DOWNTO 0);
+        VARIABLE Dq_temp : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
+    BEGIN
+        WAIT ON Dqs;
+        -- Latch data at posedge Dqs
+        IF Dqs'EVENT AND Dqs (1) = '1' AND Dqs (0) = '1' THEN
+            Dq_temp := Dq;
+            Dm_temp := Dm;
+        END IF;
+        -- Latch data at negedge Dqs
+        IF Dqs'EVENT AND Dqs (1) = '0' AND Dqs (0) = '0' THEN
+            Dq_pair <= (Dq & Dq_temp);
+            Dm_pair <= (Dm & Dm_temp);
+        END IF;
+    END PROCESS;
+
+    --
+    -- Setup timing checks
+    --
+    Setup_check : PROCESS
+    BEGIN
+        WAIT ON Sys_clk;
+        IF Sys_clk'EVENT AND Sys_clk = '1' THEN
+            ASSERT(Cke'LAST_EVENT >= tIS)
+                REPORT "CKE Setup time violation -- tIS"
+                SEVERITY WARNING;
+            ASSERT(Cs_n'LAST_EVENT >= tIS)
+                REPORT "CS# Setup time violation -- tIS"
+                SEVERITY WARNING;
+            ASSERT(Cas_n'LAST_EVENT >= tIS)
+                REPORT "CAS# Setup time violation -- tIS"
+                SEVERITY WARNING;
+            ASSERT(Ras_n'LAST_EVENT >= tIS)
+                REPORT "RAS# Setup time violation -- tIS"
+                SEVERITY WARNING;
+            ASSERT(We_n'LAST_EVENT >= tIS)
+                REPORT "WE# Setup time violation -- tIS"
+                SEVERITY WARNING;
+            ASSERT(Addr'LAST_EVENT >= tIS)
+                REPORT "ADDR Setup time violation -- tIS"
+                SEVERITY WARNING;
+            ASSERT(Ba'LAST_EVENT >= tIS)
+                REPORT "BA Setup time violation -- tIS"
+                SEVERITY WARNING;
+        END IF;   
+    END PROCESS;
+
+    --
+    -- Hold timing checks
+    --
+    Hold_check : PROCESS
+    BEGIN
+        WAIT ON Sys_clk'DELAYED (tIH);
+        IF Sys_clk'DELAYED (tIH) = '1' THEN
+            ASSERT(Cke'LAST_EVENT >= tIH)
+                REPORT "CKE Hold time violation -- tIH"
+                SEVERITY WARNING;
+            ASSERT(Cs_n'LAST_EVENT >= tIH)
+                REPORT "CS# Hold time violation -- tIH"
+                SEVERITY WARNING;
+            ASSERT(Cas_n'LAST_EVENT >= tIH)
+                REPORT "CAS# Hold time violation -- tIH"
+                SEVERITY WARNING;
+            ASSERT(Ras_n'LAST_EVENT >= tIH)
+                REPORT "RAS# Hold time violation -- tIH"
+                SEVERITY WARNING;
+            ASSERT(We_n'LAST_EVENT >= tIH)
+                REPORT "WE# Hold time violation -- tIH"
+                SEVERITY WARNING;
+            ASSERT(Addr'LAST_EVENT >= tIH)
+                REPORT "ADDR Hold time violation -- tIH"
+                SEVERITY WARNING;
+            ASSERT(Ba'LAST_EVENT >= tIH)
+                REPORT "BA Hold time violation -- tIH"
+                SEVERITY WARNING;
+        END IF;   
+    END PROCESS;
+
+END behave;
diff --git a/misc/wishbone/src/atomic32_access.vhd b/misc/wishbone/src/atomic32_access.vhd
index b062f98..9bc9825 100644
--- a/misc/wishbone/src/atomic32_access.vhd
+++ b/misc/wishbone/src/atomic32_access.vhd
@@ -1,132 +1,132 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library work;
---use work.phi_config.all;
-use work.wishbone_pkg.all;
-
-entity atomic32_access is
-	port (	cpu_clk			: in std_logic;
-			areset			: in std_logic;
-	
-			-- Wishbone from CPU interface
-			wb_16_i			: in wishbone_bus_in;
-			wb_16_o     	: out wishbone_bus_out;
-			
-			-- Wishbone to FPGA registers and ethernet core
-			wb_32_i			: in wishbone_bus_out;
-			wb_32_o			: out wishbone_bus_in);
-end atomic32_access;
-
-architecture behave of atomic32_access is
-
-type eth_state_wr_type is (idle, lsb_msb, lsb, msb, write, ack, wait_st);
-signal	eth_state_wr : eth_state_wr_type;				
-type eth_state_rd_type is (idle, lsb_msb, lsb_read, lsb, wait_st2, msb);
-signal eth_state_rd : eth_state_rd_type;			
-signal core_data : std_logic_vector(31 downto 0);
-signal core_addr : std_logic_vector(31 downto 0);
-
-begin
-	process(cpu_clk, areset)
-	begin
-		if areset = '1' then
-			eth_state_wr <= idle;
-			eth_state_rd <= idle;
-			wb_32_o.stb <= '0';
-			wb_32_o.cyc <= '0';
-			wb_16_o.ack <= '0';
-			core_data <= (others => '0');
-			core_addr <= (others => '0');
-		elsif (rising_edge(cpu_clk)) then
-			
-			case eth_state_wr is						--write cycle
-				when idle =>
-					if wb_16_i.cyc = '1' and wb_16_i.we = '1' then
-						eth_state_wr <= lsb_msb;						
-					end if;					
-				when lsb_msb =>
-					if wb_16_i.adr(1) = '0' then
-						eth_state_wr <= lsb;
-					end if;
-					if wb_16_i.adr(1) = '1' then
-						eth_state_wr <= msb;
-					end if;
-				when lsb =>
-					core_data(15 downto 0) <= wb_16_i.dat(15 downto 0);
-					wb_16_o.ack <= '1';
-					eth_state_wr <= wait_st;
-				when msb =>
-					core_data(31 downto 16) <= wb_16_i.dat(31 downto 16);
-					core_addr <= wb_16_i.adr(31 downto 2) & "00";
-					eth_state_wr <= write;
-				when write =>
-					wb_32_o.dat <= core_data;
-					wb_32_o.adr <= core_addr;
-					wb_32_o.sel <= "1111";
-					wb_32_o.we <= '1';
-					wb_32_o.stb <= '1';
-					wb_32_o.cyc <= '1';
-					eth_state_wr <= ack;
-				when ack =>
-					if wb_32_i.ack = '1' then
-						wb_16_o.ack <= '1';
-						eth_state_wr <= wait_st;
-						wb_32_o.stb <= '0';	
-						wb_32_o.cyc <= '0';		
-						wb_32_o.sel <= "0000";	
-						wb_32_o.we <= '0';	
-					end if;
-				when wait_st =>
-					wb_16_o.ack <= '0';
-					eth_state_wr <= idle;
-				when others =>
-					eth_state_wr <= idle;
-			end case;
-	
-			case eth_state_rd is						--read cycle
-				when idle =>
-					if wb_16_i.cyc = '1' and wb_16_i.we = '0' then
-						core_addr <= wb_16_i.adr(31 downto 2) & "00";	
-						eth_state_rd <= lsb_msb;
-					end if;
-				when lsb_msb =>
-					if wb_16_i.adr(1) = '0' then
-						wb_32_o.adr <= core_addr;
-						eth_state_rd <= lsb_read;
-					end if;
-					if wb_16_i.adr(1) = '1' then
-						wb_32_o.adr <= core_addr;
-						eth_state_rd <= msb;
-					end if;
-				when lsb_read =>
-					wb_32_o.sel <= "1111";
-					wb_32_o.we <= '0';
-					wb_32_o.stb <= '1';
-					wb_32_o.cyc <= '1';							
-                	eth_state_rd <= lsb;
-				when lsb =>
-					if wb_32_i.ack = '1' then									
-						wb_32_o.sel <= "0000";
-						wb_32_o.stb <= '0';
-						wb_32_o.cyc <= '0';
-						core_data <= wb_32_i.dat;
-						wb_16_o.dat <= x"0000" & wb_32_i.dat(15 downto 0);							
-						wb_16_o.ack <= '1';
-						eth_state_rd <= wait_st2;
-					end if;
-				when wait_st2 =>
-					wb_16_o.ack <= '0';
-					eth_state_rd <= idle;
-				when msb =>
-					wb_16_o.ack <= '1';
-					wb_16_o.dat <= core_data(31 downto 16) & x"0000";
-					eth_state_rd <= wait_st2;
-				when others =>
-					eth_state_rd <= idle;
-			end case;
-		end if;
-	end process;
-
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library work;
+--use work.phi_config.all;
+use work.wishbone_pkg.all;
+
+entity atomic32_access is
+	port (	cpu_clk			: in std_logic;
+			areset			: in std_logic;
+	
+			-- Wishbone from CPU interface
+			wb_16_i			: in wishbone_bus_in;
+			wb_16_o     	: out wishbone_bus_out;
+			
+			-- Wishbone to FPGA registers and ethernet core
+			wb_32_i			: in wishbone_bus_out;
+			wb_32_o			: out wishbone_bus_in);
+end atomic32_access;
+
+architecture behave of atomic32_access is
+
+type eth_state_wr_type is (idle, lsb_msb, lsb, msb, write, ack, wait_st);
+signal	eth_state_wr : eth_state_wr_type;				
+type eth_state_rd_type is (idle, lsb_msb, lsb_read, lsb, wait_st2, msb);
+signal eth_state_rd : eth_state_rd_type;			
+signal core_data : std_logic_vector(31 downto 0);
+signal core_addr : std_logic_vector(31 downto 0);
+
+begin
+	process(cpu_clk, areset)
+	begin
+		if areset = '1' then
+			eth_state_wr <= idle;
+			eth_state_rd <= idle;
+			wb_32_o.stb <= '0';
+			wb_32_o.cyc <= '0';
+			wb_16_o.ack <= '0';
+			core_data <= (others => '0');
+			core_addr <= (others => '0');
+		elsif (rising_edge(cpu_clk)) then
+			
+			case eth_state_wr is						--write cycle
+				when idle =>
+					if wb_16_i.cyc = '1' and wb_16_i.we = '1' then
+						eth_state_wr <= lsb_msb;						
+					end if;					
+				when lsb_msb =>
+					if wb_16_i.adr(1) = '0' then
+						eth_state_wr <= lsb;
+					end if;
+					if wb_16_i.adr(1) = '1' then
+						eth_state_wr <= msb;
+					end if;
+				when lsb =>
+					core_data(15 downto 0) <= wb_16_i.dat(15 downto 0);
+					wb_16_o.ack <= '1';
+					eth_state_wr <= wait_st;
+				when msb =>
+					core_data(31 downto 16) <= wb_16_i.dat(31 downto 16);
+					core_addr <= wb_16_i.adr(31 downto 2) & "00";
+					eth_state_wr <= write;
+				when write =>
+					wb_32_o.dat <= core_data;
+					wb_32_o.adr <= core_addr;
+					wb_32_o.sel <= "1111";
+					wb_32_o.we <= '1';
+					wb_32_o.stb <= '1';
+					wb_32_o.cyc <= '1';
+					eth_state_wr <= ack;
+				when ack =>
+					if wb_32_i.ack = '1' then
+						wb_16_o.ack <= '1';
+						eth_state_wr <= wait_st;
+						wb_32_o.stb <= '0';	
+						wb_32_o.cyc <= '0';		
+						wb_32_o.sel <= "0000";	
+						wb_32_o.we <= '0';	
+					end if;
+				when wait_st =>
+					wb_16_o.ack <= '0';
+					eth_state_wr <= idle;
+				when others =>
+					eth_state_wr <= idle;
+			end case;
+	
+			case eth_state_rd is						--read cycle
+				when idle =>
+					if wb_16_i.cyc = '1' and wb_16_i.we = '0' then
+						core_addr <= wb_16_i.adr(31 downto 2) & "00";	
+						eth_state_rd <= lsb_msb;
+					end if;
+				when lsb_msb =>
+					if wb_16_i.adr(1) = '0' then
+						wb_32_o.adr <= core_addr;
+						eth_state_rd <= lsb_read;
+					end if;
+					if wb_16_i.adr(1) = '1' then
+						wb_32_o.adr <= core_addr;
+						eth_state_rd <= msb;
+					end if;
+				when lsb_read =>
+					wb_32_o.sel <= "1111";
+					wb_32_o.we <= '0';
+					wb_32_o.stb <= '1';
+					wb_32_o.cyc <= '1';							
+                	eth_state_rd <= lsb;
+				when lsb =>
+					if wb_32_i.ack = '1' then									
+						wb_32_o.sel <= "0000";
+						wb_32_o.stb <= '0';
+						wb_32_o.cyc <= '0';
+						core_data <= wb_32_i.dat;
+						wb_16_o.dat <= x"0000" & wb_32_i.dat(15 downto 0);							
+						wb_16_o.ack <= '1';
+						eth_state_rd <= wait_st2;
+					end if;
+				when wait_st2 =>
+					wb_16_o.ack <= '0';
+					eth_state_rd <= idle;
+				when msb =>
+					wb_16_o.ack <= '1';
+					wb_16_o.dat <= core_data(31 downto 16) & x"0000";
+					eth_state_rd <= wait_st2;
+				when others =>
+					eth_state_rd <= idle;
+			end case;
+		end if;
+	end process;
+
 end behave;
\ No newline at end of file
diff --git a/misc/wishbone/src/wishbone_pkg.vhd b/misc/wishbone/src/wishbone_pkg.vhd
index c3b0d9b..359a33f 100644
--- a/misc/wishbone/src/wishbone_pkg.vhd
+++ b/misc/wishbone/src/wishbone_pkg.vhd
@@ -1,52 +1,52 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-package wishbone_pkg is
-
-	type wishbone_bus_in is record
-		adr			: std_logic_vector(31 downto 0); 
-		sel			: std_logic_vector(3 downto 0); 
-		we			: std_logic;
-		dat			: std_logic_vector(31 downto 0); 	-- Note! Data written with 'we'
-		cyc			: std_logic; 
-		stb			: std_logic;
-	end record;
-
-	type wishbone_bus_out is record
-		dat		: std_logic_vector(31 downto 0);
-		ack			: std_logic;
-	end record;
-	
-	type wishbone_bus is record
-		insig		: wishbone_bus_in;
-		outsig  	: wishbone_bus_out;
-	end record;
-
-	component atomic32_access is
-	port (	cpu_clk			: in std_logic;
-			areset			: in std_logic;
-	
-			-- Wishbone from CPU interface
-			wb_16_i			: in wishbone_bus_in;
-			wb_16_o     	: out wishbone_bus_out;
-			-- Wishbone to FPGA registers and ethernet core
-			wb_32_i			: in wishbone_bus_out;
-			wb_32_o			: out wishbone_bus_in);
-	end component;
-	
-	component eth_access_corr is
-	port (	cpu_clk			: in std_logic;
-			areset			: in std_logic;
-	
-			-- Wishbone from Wishbone MUX
-			eth_raw_o		: out wishbone_bus_out;
-			eth_raw_i		: in wishbone_bus_in;
-			
-			-- Wishbone ethernet core
-			eth_slave_i 	: in wishbone_bus_out;
-			eth_slave_o		: out wishbone_bus_in);
-	end component;
-
-
-end wishbone_pkg;
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+package wishbone_pkg is
+
+	type wishbone_bus_in is record
+		adr			: std_logic_vector(31 downto 0); 
+		sel			: std_logic_vector(3 downto 0); 
+		we			: std_logic;
+		dat			: std_logic_vector(31 downto 0); 	-- Note! Data written with 'we'
+		cyc			: std_logic; 
+		stb			: std_logic;
+	end record;
+
+	type wishbone_bus_out is record
+		dat		: std_logic_vector(31 downto 0);
+		ack			: std_logic;
+	end record;
+	
+	type wishbone_bus is record
+		insig		: wishbone_bus_in;
+		outsig  	: wishbone_bus_out;
+	end record;
+
+	component atomic32_access is
+	port (	cpu_clk			: in std_logic;
+			areset			: in std_logic;
+	
+			-- Wishbone from CPU interface
+			wb_16_i			: in wishbone_bus_in;
+			wb_16_o     	: out wishbone_bus_out;
+			-- Wishbone to FPGA registers and ethernet core
+			wb_32_i			: in wishbone_bus_out;
+			wb_32_o			: out wishbone_bus_in);
+	end component;
+	
+	component eth_access_corr is
+	port (	cpu_clk			: in std_logic;
+			areset			: in std_logic;
+	
+			-- Wishbone from Wishbone MUX
+			eth_raw_o		: out wishbone_bus_out;
+			eth_raw_i		: in wishbone_bus_in;
+			
+			-- Wishbone ethernet core
+			eth_slave_i 	: in wishbone_bus_out;
+			eth_slave_o		: out wishbone_bus_in);
+	end component;
+
+
+end wishbone_pkg;
diff --git a/zpu/hdl/example/bram_dmips.vhd b/zpu/hdl/example/bram_dmips.vhd
index 733560e..07b19f4 100644
--- a/zpu/hdl/example/bram_dmips.vhd
+++ b/zpu/hdl/example/bram_dmips.vhd
@@ -1,3356 +1,3356 @@
--- ZPU
---
--- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
--- 
--- The FreeBSD license
--- 
--- Redistribution and use in source and binary forms, with or without
--- modification, are permitted provided that the following conditions
--- are met:
--- 
--- 1. Redistributions of source code must retain the above copyright
---    notice, this list of conditions and the following disclaimer.
--- 2. Redistributions in binary form must reproduce the above
---    copyright notice, this list of conditions and the following
---    disclaimer in the documentation and/or other materials
---    provided with the distribution.
--- 
--- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
--- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
--- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
--- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
--- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
--- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
--- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
--- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
--- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
--- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--- 
--- The views and conclusions contained in the software and documentation
--- are those of the authors and should not be interpreted as representing
--- official policies, either expressed or implied, of the ZPU Project.
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-
-library work;
-use work.zpu_config.all;
-use work.zpupkg.all;
-
-entity dualport_ram is
-port (clk : in std_logic;
-	memAWriteEnable : in std_logic;
-	memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
-	memAWrite : in std_logic_vector(wordSize-1 downto 0);
-	memARead : out std_logic_vector(wordSize-1 downto 0);
-	memBWriteEnable : in std_logic;
-	memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
-	memBWrite : in std_logic_vector(wordSize-1 downto 0);
-	memBRead : out std_logic_vector(wordSize-1 downto 0));
-end dualport_ram;
-
-architecture dualport_ram_arch of dualport_ram is
-
-
-type ram_type is array(natural range 0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
-
-shared variable ram : ram_type :=
-(
-     0 => x"0b0b0b0b",
-     1 => x"82700b0b",
-     2 => x"80d5f40c",
-     3 => x"3a0b0b80",
-     4 => x"c4fb0400",
-     5 => x"00000000",
-     6 => x"00000000",
-     7 => x"00000000",
-     8 => x"80088408",
-     9 => x"88080b0b",
-    10 => x"80c5c22d",
-    11 => x"880c840c",
-    12 => x"800c0400",
-    13 => x"00000000",
-    14 => x"00000000",
-    15 => x"00000000",
-    16 => x"71fd0608",
-    17 => x"72830609",
-    18 => x"81058205",
-    19 => x"832b2a83",
-    20 => x"ffff0652",
-    21 => x"04000000",
-    22 => x"00000000",
-    23 => x"00000000",
-    24 => x"71fd0608",
-    25 => x"83ffff73",
-    26 => x"83060981",
-    27 => x"05820583",
-    28 => x"2b2b0906",
-    29 => x"7383ffff",
-    30 => x"0b0b0b0b",
-    31 => x"83a70400",
-    32 => x"72098105",
-    33 => x"72057373",
-    34 => x"09060906",
-    35 => x"73097306",
-    36 => x"070a8106",
-    37 => x"53510400",
-    38 => x"00000000",
-    39 => x"00000000",
-    40 => x"72722473",
-    41 => x"732e0753",
-    42 => x"51040000",
-    43 => x"00000000",
-    44 => x"00000000",
-    45 => x"00000000",
-    46 => x"00000000",
-    47 => x"00000000",
-    48 => x"71737109",
-    49 => x"71068106",
-    50 => x"30720a10",
-    51 => x"0a720a10",
-    52 => x"0a31050a",
-    53 => x"81065151",
-    54 => x"53510400",
-    55 => x"00000000",
-    56 => x"72722673",
-    57 => x"732e0753",
-    58 => x"51040000",
-    59 => x"00000000",
-    60 => x"00000000",
-    61 => x"00000000",
-    62 => x"00000000",
-    63 => x"00000000",
-    64 => x"00000000",
-    65 => x"00000000",
-    66 => x"00000000",
-    67 => x"00000000",
-    68 => x"00000000",
-    69 => x"00000000",
-    70 => x"00000000",
-    71 => x"00000000",
-    72 => x"0b0b0b88",
-    73 => x"c3040000",
-    74 => x"00000000",
-    75 => x"00000000",
-    76 => x"00000000",
-    77 => x"00000000",
-    78 => x"00000000",
-    79 => x"00000000",
-    80 => x"720a722b",
-    81 => x"0a535104",
-    82 => x"00000000",
-    83 => x"00000000",
-    84 => x"00000000",
-    85 => x"00000000",
-    86 => x"00000000",
-    87 => x"00000000",
-    88 => x"72729f06",
-    89 => x"0981050b",
-    90 => x"0b0b88a6",
-    91 => x"05040000",
-    92 => x"00000000",
-    93 => x"00000000",
-    94 => x"00000000",
-    95 => x"00000000",
-    96 => x"72722aff",
-    97 => x"739f062a",
-    98 => x"0974090a",
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-  3048 => x"00000000",
-  3049 => x"00000000",
-  3050 => x"00000000",
-  3051 => x"00000000",
-  3052 => x"00000000",
-  3053 => x"00000000",
-  3054 => x"00000000",
-  3055 => x"00000000",
-  3056 => x"00000000",
-  3057 => x"00000000",
-  3058 => x"00000000",
-  3059 => x"00000000",
-  3060 => x"00000000",
-  3061 => x"00000000",
-  3062 => x"00000000",
-  3063 => x"00000000",
-  3064 => x"00000000",
-  3065 => x"00000000",
-  3066 => x"00000000",
-  3067 => x"00000000",
-  3068 => x"00000000",
-  3069 => x"00000000",
-  3070 => x"00000001",
-  3071 => x"330eabcd",
-  3072 => x"1234e66d",
-  3073 => x"deec0005",
-  3074 => x"000b0000",
-  3075 => x"00000000",
-  3076 => x"00000000",
-  3077 => x"00000000",
-  3078 => x"00000000",
-  3079 => x"00000000",
-  3080 => x"00000000",
-  3081 => x"00000000",
-  3082 => x"00000000",
-  3083 => x"00000000",
-  3084 => x"00000000",
-  3085 => x"00000000",
-  3086 => x"00000000",
-  3087 => x"00000000",
-  3088 => x"00000000",
-  3089 => x"00000000",
-  3090 => x"00000000",
-  3091 => x"00000000",
-  3092 => x"00000000",
-  3093 => x"00000000",
-  3094 => x"00000000",
-  3095 => x"00000000",
-  3096 => x"00000000",
-  3097 => x"00000000",
-  3098 => x"00000000",
-  3099 => x"00000000",
-  3100 => x"00000000",
-  3101 => x"00000000",
-  3102 => x"00000000",
-  3103 => x"00000000",
-  3104 => x"00000000",
-  3105 => x"00000000",
-  3106 => x"00000000",
-  3107 => x"00000000",
-  3108 => x"00000000",
-  3109 => x"00000000",
-  3110 => x"00000000",
-  3111 => x"00000000",
-  3112 => x"00000000",
-  3113 => x"00000000",
-  3114 => x"00000000",
-  3115 => x"00000000",
-  3116 => x"00000000",
-  3117 => x"00000000",
-  3118 => x"00000000",
-  3119 => x"00000000",
-  3120 => x"00000000",
-  3121 => x"00000000",
-  3122 => x"00000000",
-  3123 => x"00000000",
-  3124 => x"00000000",
-  3125 => x"00000000",
-  3126 => x"00000000",
-  3127 => x"00000000",
-  3128 => x"00000000",
-  3129 => x"00000000",
-  3130 => x"00000000",
-  3131 => x"00000000",
-  3132 => x"00000000",
-  3133 => x"00000000",
-  3134 => x"00000000",
-  3135 => x"00000000",
-  3136 => x"00000000",
-  3137 => x"00000000",
-  3138 => x"00000000",
-  3139 => x"00000000",
-  3140 => x"00000000",
-  3141 => x"00000000",
-  3142 => x"00000000",
-  3143 => x"00000000",
-  3144 => x"00000000",
-  3145 => x"00000000",
-  3146 => x"00000000",
-  3147 => x"00000000",
-  3148 => x"00000000",
-  3149 => x"00000000",
-  3150 => x"00000000",
-  3151 => x"00000000",
-  3152 => x"00000000",
-  3153 => x"00000000",
-  3154 => x"00000000",
-  3155 => x"00000000",
-  3156 => x"00000000",
-  3157 => x"00000000",
-  3158 => x"00000000",
-  3159 => x"00000000",
-  3160 => x"00000000",
-  3161 => x"00000000",
-  3162 => x"00000000",
-  3163 => x"00000000",
-  3164 => x"00000000",
-  3165 => x"00000000",
-  3166 => x"00000000",
-  3167 => x"00000000",
-  3168 => x"00000000",
-  3169 => x"00000000",
-  3170 => x"00000000",
-  3171 => x"00000000",
-  3172 => x"00000000",
-  3173 => x"00000000",
-  3174 => x"00000000",
-  3175 => x"00000000",
-  3176 => x"00000000",
-  3177 => x"00000000",
-  3178 => x"00000000",
-  3179 => x"00000000",
-  3180 => x"00000000",
-  3181 => x"00000000",
-  3182 => x"00000000",
-  3183 => x"00000000",
-  3184 => x"00000000",
-  3185 => x"00000000",
-  3186 => x"00000000",
-  3187 => x"00000000",
-  3188 => x"00000000",
-  3189 => x"00000000",
-  3190 => x"00000000",
-  3191 => x"00000000",
-  3192 => x"00000000",
-  3193 => x"00000000",
-  3194 => x"00000000",
-  3195 => x"00000000",
-  3196 => x"00000000",
-  3197 => x"00000000",
-  3198 => x"00000000",
-  3199 => x"00000000",
-  3200 => x"00000000",
-  3201 => x"00000000",
-  3202 => x"00000000",
-  3203 => x"00000000",
-  3204 => x"00000000",
-  3205 => x"00000000",
-  3206 => x"00000000",
-  3207 => x"00000000",
-  3208 => x"00000000",
-  3209 => x"00000000",
-  3210 => x"00000000",
-  3211 => x"00000000",
-  3212 => x"00000000",
-  3213 => x"00000000",
-  3214 => x"00000000",
-  3215 => x"00000000",
-  3216 => x"00000000",
-  3217 => x"00000000",
-  3218 => x"00000000",
-  3219 => x"00000000",
-  3220 => x"00000000",
-  3221 => x"00000000",
-  3222 => x"00000000",
-  3223 => x"00000000",
-  3224 => x"00000000",
-  3225 => x"00000000",
-  3226 => x"00000000",
-  3227 => x"00000000",
-  3228 => x"00000000",
-  3229 => x"00000000",
-  3230 => x"00000000",
-  3231 => x"00000000",
-  3232 => x"00000000",
-  3233 => x"00000000",
-  3234 => x"00000000",
-  3235 => x"00000000",
-  3236 => x"00000000",
-  3237 => x"00000000",
-  3238 => x"00000000",
-  3239 => x"00000000",
-  3240 => x"00000000",
-  3241 => x"00000000",
-  3242 => x"00000000",
-  3243 => x"00000000",
-  3244 => x"00000000",
-  3245 => x"00000000",
-  3246 => x"00000000",
-  3247 => x"00000000",
-  3248 => x"00000000",
-  3249 => x"00000000",
-  3250 => x"00000000",
-  3251 => x"00002ad4",
-  3252 => x"ffffffff",
-  3253 => x"00000000",
-  3254 => x"ffffffff",
-  3255 => x"00000000",
-  3256 => x"00000000",
-	others => x"00000000"
-);
-
-begin
-
-process (clk)
-begin
-	if (clk'event and clk = '1') then
-		if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then
-			report "write collision" severity failure;
-		end if;
-	
-		if (memAWriteEnable = '1') then
-			ram(to_integer(unsigned(memAAddr))) := memAWrite;
-			memARead <= memAWrite;
-		else
-			memARead <= ram(to_integer(unsigned(memAAddr)));
-		end if;
-	end if;
-end process;
-
-process (clk)
-begin
-	if (clk'event and clk = '1') then
-		if (memBWriteEnable = '1') then
-			ram(to_integer(unsigned(memBAddr))) := memBWrite;
-			memBRead <= memBWrite;
-		else
-			memBRead <= ram(to_integer(unsigned(memBAddr)));
-		end if;
-	end if;
-end process;
-
-
-
-
-end dualport_ram_arch;
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity dualport_ram is
+port (clk : in std_logic;
+	memAWriteEnable : in std_logic;
+	memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+	memAWrite : in std_logic_vector(wordSize-1 downto 0);
+	memARead : out std_logic_vector(wordSize-1 downto 0);
+	memBWriteEnable : in std_logic;
+	memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+	memBWrite : in std_logic_vector(wordSize-1 downto 0);
+	memBRead : out std_logic_vector(wordSize-1 downto 0));
+end dualport_ram;
+
+architecture dualport_ram_arch of dualport_ram is
+
+
+type ram_type is array(natural range 0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
+
+shared variable ram : ram_type :=
+(
+     0 => x"0b0b0b0b",
+     1 => x"82700b0b",
+     2 => x"80d5f40c",
+     3 => x"3a0b0b80",
+     4 => x"c4fb0400",
+     5 => x"00000000",
+     6 => x"00000000",
+     7 => x"00000000",
+     8 => x"80088408",
+     9 => x"88080b0b",
+    10 => x"80c5c22d",
+    11 => x"880c840c",
+    12 => x"800c0400",
+    13 => x"00000000",
+    14 => x"00000000",
+    15 => x"00000000",
+    16 => x"71fd0608",
+    17 => x"72830609",
+    18 => x"81058205",
+    19 => x"832b2a83",
+    20 => x"ffff0652",
+    21 => x"04000000",
+    22 => x"00000000",
+    23 => x"00000000",
+    24 => x"71fd0608",
+    25 => x"83ffff73",
+    26 => x"83060981",
+    27 => x"05820583",
+    28 => x"2b2b0906",
+    29 => x"7383ffff",
+    30 => x"0b0b0b0b",
+    31 => x"83a70400",
+    32 => x"72098105",
+    33 => x"72057373",
+    34 => x"09060906",
+    35 => x"73097306",
+    36 => x"070a8106",
+    37 => x"53510400",
+    38 => x"00000000",
+    39 => x"00000000",
+    40 => x"72722473",
+    41 => x"732e0753",
+    42 => x"51040000",
+    43 => x"00000000",
+    44 => x"00000000",
+    45 => x"00000000",
+    46 => x"00000000",
+    47 => x"00000000",
+    48 => x"71737109",
+    49 => x"71068106",
+    50 => x"30720a10",
+    51 => x"0a720a10",
+    52 => x"0a31050a",
+    53 => x"81065151",
+    54 => x"53510400",
+    55 => x"00000000",
+    56 => x"72722673",
+    57 => x"732e0753",
+    58 => x"51040000",
+    59 => x"00000000",
+    60 => x"00000000",
+    61 => x"00000000",
+    62 => x"00000000",
+    63 => x"00000000",
+    64 => x"00000000",
+    65 => x"00000000",
+    66 => x"00000000",
+    67 => x"00000000",
+    68 => x"00000000",
+    69 => x"00000000",
+    70 => x"00000000",
+    71 => x"00000000",
+    72 => x"0b0b0b88",
+    73 => x"c3040000",
+    74 => x"00000000",
+    75 => x"00000000",
+    76 => x"00000000",
+    77 => x"00000000",
+    78 => x"00000000",
+    79 => x"00000000",
+    80 => x"720a722b",
+    81 => x"0a535104",
+    82 => x"00000000",
+    83 => x"00000000",
+    84 => x"00000000",
+    85 => x"00000000",
+    86 => x"00000000",
+    87 => x"00000000",
+    88 => x"72729f06",
+    89 => x"0981050b",
+    90 => x"0b0b88a6",
+    91 => x"05040000",
+    92 => x"00000000",
+    93 => x"00000000",
+    94 => x"00000000",
+    95 => x"00000000",
+    96 => x"72722aff",
+    97 => x"739f062a",
+    98 => x"0974090a",
+    99 => x"8106ff05",
+   100 => x"06075351",
+   101 => x"04000000",
+   102 => x"00000000",
+   103 => x"00000000",
+   104 => x"71715351",
+   105 => x"020d0406",
+   106 => x"73830609",
+   107 => x"81058205",
+   108 => x"832b0b2b",
+   109 => x"0772fc06",
+   110 => x"0c515104",
+   111 => x"00000000",
+   112 => x"72098105",
+   113 => x"72050970",
+   114 => x"81050906",
+   115 => x"0a810653",
+   116 => x"51040000",
+   117 => x"00000000",
+   118 => x"00000000",
+   119 => x"00000000",
+   120 => x"72098105",
+   121 => x"72050970",
+   122 => x"81050906",
+   123 => x"0a098106",
+   124 => x"53510400",
+   125 => x"00000000",
+   126 => x"00000000",
+   127 => x"00000000",
+   128 => x"71098105",
+   129 => x"52040000",
+   130 => x"00000000",
+   131 => x"00000000",
+   132 => x"00000000",
+   133 => x"00000000",
+   134 => x"00000000",
+   135 => x"00000000",
+   136 => x"72720981",
+   137 => x"05055351",
+   138 => x"04000000",
+   139 => x"00000000",
+   140 => x"00000000",
+   141 => x"00000000",
+   142 => x"00000000",
+   143 => x"00000000",
+   144 => x"72097206",
+   145 => x"73730906",
+   146 => x"07535104",
+   147 => x"00000000",
+   148 => x"00000000",
+   149 => x"00000000",
+   150 => x"00000000",
+   151 => x"00000000",
+   152 => x"71fc0608",
+   153 => x"72830609",
+   154 => x"81058305",
+   155 => x"1010102a",
+   156 => x"81ff0652",
+   157 => x"04000000",
+   158 => x"00000000",
+   159 => x"00000000",
+   160 => x"71fc0608",
+   161 => x"0b0b80d5",
+   162 => x"e0738306",
+   163 => x"10100508",
+   164 => x"060b0b0b",
+   165 => x"88a90400",
+   166 => x"00000000",
+   167 => x"00000000",
+   168 => x"80088408",
+   169 => x"88087575",
+   170 => x"0b0b0bad",
+   171 => x"aa2d5050",
+   172 => x"80085688",
+   173 => x"0c840c80",
+   174 => x"0c510400",
+   175 => x"00000000",
+   176 => x"80088408",
+   177 => x"88087575",
+   178 => x"0b0b0bad",
+   179 => x"ee2d5050",
+   180 => x"80085688",
+   181 => x"0c840c80",
+   182 => x"0c510400",
+   183 => x"00000000",
+   184 => x"72097081",
+   185 => x"0509060a",
+   186 => x"8106ff05",
+   187 => x"70547106",
+   188 => x"73097274",
+   189 => x"05ff0506",
+   190 => x"07515151",
+   191 => x"04000000",
+   192 => x"72097081",
+   193 => x"0509060a",
+   194 => x"098106ff",
+   195 => x"05705471",
+   196 => x"06730972",
+   197 => x"7405ff05",
+   198 => x"06075151",
+   199 => x"51040000",
+   200 => x"05ff0504",
+   201 => x"00000000",
+   202 => x"00000000",
+   203 => x"00000000",
+   204 => x"00000000",
+   205 => x"00000000",
+   206 => x"00000000",
+   207 => x"00000000",
+   208 => x"810b0b0b",
+   209 => x"80d5f00c",
+   210 => x"51040000",
+   211 => x"00000000",
+   212 => x"00000000",
+   213 => x"00000000",
+   214 => x"00000000",
+   215 => x"00000000",
+   216 => x"71810552",
+   217 => x"04000000",
+   218 => x"00000000",
+   219 => x"00000000",
+   220 => x"00000000",
+   221 => x"00000000",
+   222 => x"00000000",
+   223 => x"00000000",
+   224 => x"00000000",
+   225 => x"00000000",
+   226 => x"00000000",
+   227 => x"00000000",
+   228 => x"00000000",
+   229 => x"00000000",
+   230 => x"00000000",
+   231 => x"00000000",
+   232 => x"02840572",
+   233 => x"10100552",
+   234 => x"04000000",
+   235 => x"00000000",
+   236 => x"00000000",
+   237 => x"00000000",
+   238 => x"00000000",
+   239 => x"00000000",
+   240 => x"00000000",
+   241 => x"00000000",
+   242 => x"00000000",
+   243 => x"00000000",
+   244 => x"00000000",
+   245 => x"00000000",
+   246 => x"00000000",
+   247 => x"00000000",
+   248 => x"717105ff",
+   249 => x"05715351",
+   250 => x"020d0400",
+   251 => x"00000000",
+   252 => x"00000000",
+   253 => x"00000000",
+   254 => x"00000000",
+   255 => x"00000000",
+   256 => x"82fd3fbf",
+   257 => x"a03f0410",
+   258 => x"10101010",
+   259 => x"10101010",
+   260 => x"10101010",
+   261 => x"10101010",
+   262 => x"10101010",
+   263 => x"10101010",
+   264 => x"10101010",
+   265 => x"10105351",
+   266 => x"047381ff",
+   267 => x"06738306",
+   268 => x"09810583",
+   269 => x"05101010",
+   270 => x"2b0772fc",
+   271 => x"060c5151",
+   272 => x"043c0472",
+   273 => x"72807281",
+   274 => x"06ff0509",
+   275 => x"72060571",
+   276 => x"1052720a",
+   277 => x"100a5372",
+   278 => x"ed385151",
+   279 => x"535104ff",
+   280 => x"3d0d0b0b",
+   281 => x"80e5e408",
+   282 => x"52710870",
+   283 => x"882a8132",
+   284 => x"70810651",
+   285 => x"515170f1",
+   286 => x"3873720c",
+   287 => x"833d0d04",
+   288 => x"80d5f008",
+   289 => x"802ea438",
+   290 => x"80d5f408",
+   291 => x"822ebd38",
+   292 => x"8380800b",
+   293 => x"0b0b80e5",
+   294 => x"e40c82a0",
+   295 => x"800b80e5",
+   296 => x"e80c8290",
+   297 => x"800b80e5",
+   298 => x"ec0c04f8",
+   299 => x"808080a4",
+   300 => x"0b0b0b80",
+   301 => x"e5e40cf8",
+   302 => x"80808280",
+   303 => x"0b80e5e8",
+   304 => x"0cf88080",
+   305 => x"84800b80",
+   306 => x"e5ec0c04",
+   307 => x"80c0a880",
+   308 => x"8c0b0b0b",
+   309 => x"80e5e40c",
+   310 => x"80c0a880",
+   311 => x"940b80e5",
+   312 => x"e80c0b0b",
+   313 => x"80c7d00b",
+   314 => x"80e5ec0c",
+   315 => x"04f23d0d",
+   316 => x"6080e5e8",
+   317 => x"08565d82",
+   318 => x"750c8059",
+   319 => x"805a800b",
+   320 => x"8f3d5d5b",
+   321 => x"7a101015",
+   322 => x"70087108",
+   323 => x"719f2c7e",
+   324 => x"852b5855",
+   325 => x"557d5359",
+   326 => x"5799993f",
+   327 => x"7d7f7a72",
+   328 => x"077c7207",
+   329 => x"71716081",
+   330 => x"05415f5d",
+   331 => x"5b595755",
+   332 => x"817b278f",
+   333 => x"38767d0c",
+   334 => x"77841e0c",
+   335 => x"7c800c90",
+   336 => x"3d0d0480",
+   337 => x"e5e80855",
+   338 => x"ffba3970",
+   339 => x"7080e5f0",
+   340 => x"335170a7",
+   341 => x"3880d5fc",
+   342 => x"08700852",
+   343 => x"5270802e",
+   344 => x"94388412",
+   345 => x"80d5fc0c",
+   346 => x"702d80d5",
+   347 => x"fc087008",
+   348 => x"525270ee",
+   349 => x"38810b80",
+   350 => x"e5f03450",
+   351 => x"50040470",
+   352 => x"0b0b80e5",
+   353 => x"e008802e",
+   354 => x"8e380b0b",
+   355 => x"0b0b800b",
+   356 => x"802e0981",
+   357 => x"06833850",
+   358 => x"040b0b80",
+   359 => x"e5e0510b",
+   360 => x"0b0bf4dc",
+   361 => x"3f500404",
+   362 => x"ff3d0d02",
+   363 => x"8f053352",
+   364 => x"718a2e8a",
+   365 => x"387151fd",
+   366 => x"a63f833d",
+   367 => x"0d048d51",
+   368 => x"fd9d3f71",
+   369 => x"51fd983f",
+   370 => x"833d0d04",
+   371 => x"ce3d0db5",
+   372 => x"3d707084",
+   373 => x"0552088b",
+   374 => x"a85c56a5",
+   375 => x"3d5e5c80",
+   376 => x"75708105",
+   377 => x"5733765b",
+   378 => x"55587378",
+   379 => x"2e80c138",
+   380 => x"8e3d5b73",
+   381 => x"a52e0981",
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+  2709 => x"08080808",
+  2710 => x"08080808",
+  2711 => x"08080808",
+  2712 => x"08080808",
+  2713 => x"08080808",
+  2714 => x"08080808",
+  2715 => x"08080808",
+  2716 => x"08080808",
+  2717 => x"08080808",
+  2718 => x"08080808",
+  2719 => x"08080808",
+  2720 => x"08080808",
+  2721 => x"08080808",
+  2722 => x"08080808",
+  2723 => x"08080808",
+  2724 => x"08080808",
+  2725 => x"08080808",
+  2726 => x"08080808",
+  2727 => x"08080808",
+  2728 => x"08080808",
+  2729 => x"08080808",
+  2730 => x"08080808",
+  2731 => x"08080808",
+  2732 => x"08080808",
+  2733 => x"08080808",
+  2734 => x"08080808",
+  2735 => x"08080808",
+  2736 => x"08080808",
+  2737 => x"08080808",
+  2738 => x"08080808",
+  2739 => x"08080808",
+  2740 => x"43000000",
+  2741 => x"64756d6d",
+  2742 => x"792e6578",
+  2743 => x"65000000",
+  2744 => x"00ffffff",
+  2745 => x"ff00ffff",
+  2746 => x"ffff00ff",
+  2747 => x"ffffff00",
+  2748 => x"00000000",
+  2749 => x"00000000",
+  2750 => x"00000000",
+  2751 => x"000032dc",
+  2752 => x"0000c350",
+  2753 => x"00000000",
+  2754 => x"00000000",
+  2755 => x"00000000",
+  2756 => x"00000000",
+  2757 => x"00000000",
+  2758 => x"00000000",
+  2759 => x"00000000",
+  2760 => x"00000000",
+  2761 => x"00000000",
+  2762 => x"00000000",
+  2763 => x"00000000",
+  2764 => x"00000000",
+  2765 => x"00000000",
+  2766 => x"ffffffff",
+  2767 => x"00000000",
+  2768 => x"00020000",
+  2769 => x"00000000",
+  2770 => x"00000000",
+  2771 => x"00002b44",
+  2772 => x"00002b44",
+  2773 => x"00002b4c",
+  2774 => x"00002b4c",
+  2775 => x"00002b54",
+  2776 => x"00002b54",
+  2777 => x"00002b5c",
+  2778 => x"00002b5c",
+  2779 => x"00002b64",
+  2780 => x"00002b64",
+  2781 => x"00002b6c",
+  2782 => x"00002b6c",
+  2783 => x"00002b74",
+  2784 => x"00002b74",
+  2785 => x"00002b7c",
+  2786 => x"00002b7c",
+  2787 => x"00002b84",
+  2788 => x"00002b84",
+  2789 => x"00002b8c",
+  2790 => x"00002b8c",
+  2791 => x"00002b94",
+  2792 => x"00002b94",
+  2793 => x"00002b9c",
+  2794 => x"00002b9c",
+  2795 => x"00002ba4",
+  2796 => x"00002ba4",
+  2797 => x"00002bac",
+  2798 => x"00002bac",
+  2799 => x"00002bb4",
+  2800 => x"00002bb4",
+  2801 => x"00002bbc",
+  2802 => x"00002bbc",
+  2803 => x"00002bc4",
+  2804 => x"00002bc4",
+  2805 => x"00002bcc",
+  2806 => x"00002bcc",
+  2807 => x"00002bd4",
+  2808 => x"00002bd4",
+  2809 => x"00002bdc",
+  2810 => x"00002bdc",
+  2811 => x"00002be4",
+  2812 => x"00002be4",
+  2813 => x"00002bec",
+  2814 => x"00002bec",
+  2815 => x"00002bf4",
+  2816 => x"00002bf4",
+  2817 => x"00002bfc",
+  2818 => x"00002bfc",
+  2819 => x"00002c04",
+  2820 => x"00002c04",
+  2821 => x"00002c0c",
+  2822 => x"00002c0c",
+  2823 => x"00002c14",
+  2824 => x"00002c14",
+  2825 => x"00002c1c",
+  2826 => x"00002c1c",
+  2827 => x"00002c24",
+  2828 => x"00002c24",
+  2829 => x"00002c2c",
+  2830 => x"00002c2c",
+  2831 => x"00002c34",
+  2832 => x"00002c34",
+  2833 => x"00002c3c",
+  2834 => x"00002c3c",
+  2835 => x"00002c44",
+  2836 => x"00002c44",
+  2837 => x"00002c4c",
+  2838 => x"00002c4c",
+  2839 => x"00002c54",
+  2840 => x"00002c54",
+  2841 => x"00002c5c",
+  2842 => x"00002c5c",
+  2843 => x"00002c64",
+  2844 => x"00002c64",
+  2845 => x"00002c6c",
+  2846 => x"00002c6c",
+  2847 => x"00002c74",
+  2848 => x"00002c74",
+  2849 => x"00002c7c",
+  2850 => x"00002c7c",
+  2851 => x"00002c84",
+  2852 => x"00002c84",
+  2853 => x"00002c8c",
+  2854 => x"00002c8c",
+  2855 => x"00002c94",
+  2856 => x"00002c94",
+  2857 => x"00002c9c",
+  2858 => x"00002c9c",
+  2859 => x"00002ca4",
+  2860 => x"00002ca4",
+  2861 => x"00002cac",
+  2862 => x"00002cac",
+  2863 => x"00002cb4",
+  2864 => x"00002cb4",
+  2865 => x"00002cbc",
+  2866 => x"00002cbc",
+  2867 => x"00002cc4",
+  2868 => x"00002cc4",
+  2869 => x"00002ccc",
+  2870 => x"00002ccc",
+  2871 => x"00002cd4",
+  2872 => x"00002cd4",
+  2873 => x"00002cdc",
+  2874 => x"00002cdc",
+  2875 => x"00002ce4",
+  2876 => x"00002ce4",
+  2877 => x"00002cec",
+  2878 => x"00002cec",
+  2879 => x"00002cf4",
+  2880 => x"00002cf4",
+  2881 => x"00002cfc",
+  2882 => x"00002cfc",
+  2883 => x"00002d04",
+  2884 => x"00002d04",
+  2885 => x"00002d0c",
+  2886 => x"00002d0c",
+  2887 => x"00002d14",
+  2888 => x"00002d14",
+  2889 => x"00002d1c",
+  2890 => x"00002d1c",
+  2891 => x"00002d24",
+  2892 => x"00002d24",
+  2893 => x"00002d2c",
+  2894 => x"00002d2c",
+  2895 => x"00002d34",
+  2896 => x"00002d34",
+  2897 => x"00002d3c",
+  2898 => x"00002d3c",
+  2899 => x"00002d44",
+  2900 => x"00002d44",
+  2901 => x"00002d4c",
+  2902 => x"00002d4c",
+  2903 => x"00002d54",
+  2904 => x"00002d54",
+  2905 => x"00002d5c",
+  2906 => x"00002d5c",
+  2907 => x"00002d64",
+  2908 => x"00002d64",
+  2909 => x"00002d6c",
+  2910 => x"00002d6c",
+  2911 => x"00002d74",
+  2912 => x"00002d74",
+  2913 => x"00002d7c",
+  2914 => x"00002d7c",
+  2915 => x"00002d84",
+  2916 => x"00002d84",
+  2917 => x"00002d8c",
+  2918 => x"00002d8c",
+  2919 => x"00002d94",
+  2920 => x"00002d94",
+  2921 => x"00002d9c",
+  2922 => x"00002d9c",
+  2923 => x"00002da4",
+  2924 => x"00002da4",
+  2925 => x"00002dac",
+  2926 => x"00002dac",
+  2927 => x"00002db4",
+  2928 => x"00002db4",
+  2929 => x"00002dbc",
+  2930 => x"00002dbc",
+  2931 => x"00002dc4",
+  2932 => x"00002dc4",
+  2933 => x"00002dcc",
+  2934 => x"00002dcc",
+  2935 => x"00002dd4",
+  2936 => x"00002dd4",
+  2937 => x"00002ddc",
+  2938 => x"00002ddc",
+  2939 => x"00002de4",
+  2940 => x"00002de4",
+  2941 => x"00002dec",
+  2942 => x"00002dec",
+  2943 => x"00002df4",
+  2944 => x"00002df4",
+  2945 => x"00002dfc",
+  2946 => x"00002dfc",
+  2947 => x"00002e04",
+  2948 => x"00002e04",
+  2949 => x"00002e0c",
+  2950 => x"00002e0c",
+  2951 => x"00002e14",
+  2952 => x"00002e14",
+  2953 => x"00002e1c",
+  2954 => x"00002e1c",
+  2955 => x"00002e24",
+  2956 => x"00002e24",
+  2957 => x"00002e2c",
+  2958 => x"00002e2c",
+  2959 => x"00002e34",
+  2960 => x"00002e34",
+  2961 => x"00002e3c",
+  2962 => x"00002e3c",
+  2963 => x"00002e44",
+  2964 => x"00002e44",
+  2965 => x"00002e4c",
+  2966 => x"00002e4c",
+  2967 => x"00002e54",
+  2968 => x"00002e54",
+  2969 => x"00002e5c",
+  2970 => x"00002e5c",
+  2971 => x"00002e64",
+  2972 => x"00002e64",
+  2973 => x"00002e6c",
+  2974 => x"00002e6c",
+  2975 => x"00002e74",
+  2976 => x"00002e74",
+  2977 => x"00002e7c",
+  2978 => x"00002e7c",
+  2979 => x"00002e84",
+  2980 => x"00002e84",
+  2981 => x"00002e8c",
+  2982 => x"00002e8c",
+  2983 => x"00002e94",
+  2984 => x"00002e94",
+  2985 => x"00002e9c",
+  2986 => x"00002e9c",
+  2987 => x"00002ea4",
+  2988 => x"00002ea4",
+  2989 => x"00002eac",
+  2990 => x"00002eac",
+  2991 => x"00002eb4",
+  2992 => x"00002eb4",
+  2993 => x"00002ebc",
+  2994 => x"00002ebc",
+  2995 => x"00002ec4",
+  2996 => x"00002ec4",
+  2997 => x"00002ecc",
+  2998 => x"00002ecc",
+  2999 => x"00002ed4",
+  3000 => x"00002ed4",
+  3001 => x"00002edc",
+  3002 => x"00002edc",
+  3003 => x"00002ee4",
+  3004 => x"00002ee4",
+  3005 => x"00002eec",
+  3006 => x"00002eec",
+  3007 => x"00002ef4",
+  3008 => x"00002ef4",
+  3009 => x"00002efc",
+  3010 => x"00002efc",
+  3011 => x"00002f04",
+  3012 => x"00002f04",
+  3013 => x"00002f0c",
+  3014 => x"00002f0c",
+  3015 => x"00002f14",
+  3016 => x"00002f14",
+  3017 => x"00002f1c",
+  3018 => x"00002f1c",
+  3019 => x"00002f24",
+  3020 => x"00002f24",
+  3021 => x"00002f2c",
+  3022 => x"00002f2c",
+  3023 => x"00002f34",
+  3024 => x"00002f34",
+  3025 => x"00002f3c",
+  3026 => x"00002f3c",
+  3027 => x"00002f50",
+  3028 => x"00000000",
+  3029 => x"000031b8",
+  3030 => x"00003214",
+  3031 => x"00003270",
+  3032 => x"00000000",
+  3033 => x"00000000",
+  3034 => x"00000000",
+  3035 => x"00000000",
+  3036 => x"00000000",
+  3037 => x"00000000",
+  3038 => x"00000000",
+  3039 => x"00000000",
+  3040 => x"00000000",
+  3041 => x"00002ad0",
+  3042 => x"00000000",
+  3043 => x"00000000",
+  3044 => x"00000000",
+  3045 => x"00000000",
+  3046 => x"00000000",
+  3047 => x"00000000",
+  3048 => x"00000000",
+  3049 => x"00000000",
+  3050 => x"00000000",
+  3051 => x"00000000",
+  3052 => x"00000000",
+  3053 => x"00000000",
+  3054 => x"00000000",
+  3055 => x"00000000",
+  3056 => x"00000000",
+  3057 => x"00000000",
+  3058 => x"00000000",
+  3059 => x"00000000",
+  3060 => x"00000000",
+  3061 => x"00000000",
+  3062 => x"00000000",
+  3063 => x"00000000",
+  3064 => x"00000000",
+  3065 => x"00000000",
+  3066 => x"00000000",
+  3067 => x"00000000",
+  3068 => x"00000000",
+  3069 => x"00000000",
+  3070 => x"00000001",
+  3071 => x"330eabcd",
+  3072 => x"1234e66d",
+  3073 => x"deec0005",
+  3074 => x"000b0000",
+  3075 => x"00000000",
+  3076 => x"00000000",
+  3077 => x"00000000",
+  3078 => x"00000000",
+  3079 => x"00000000",
+  3080 => x"00000000",
+  3081 => x"00000000",
+  3082 => x"00000000",
+  3083 => x"00000000",
+  3084 => x"00000000",
+  3085 => x"00000000",
+  3086 => x"00000000",
+  3087 => x"00000000",
+  3088 => x"00000000",
+  3089 => x"00000000",
+  3090 => x"00000000",
+  3091 => x"00000000",
+  3092 => x"00000000",
+  3093 => x"00000000",
+  3094 => x"00000000",
+  3095 => x"00000000",
+  3096 => x"00000000",
+  3097 => x"00000000",
+  3098 => x"00000000",
+  3099 => x"00000000",
+  3100 => x"00000000",
+  3101 => x"00000000",
+  3102 => x"00000000",
+  3103 => x"00000000",
+  3104 => x"00000000",
+  3105 => x"00000000",
+  3106 => x"00000000",
+  3107 => x"00000000",
+  3108 => x"00000000",
+  3109 => x"00000000",
+  3110 => x"00000000",
+  3111 => x"00000000",
+  3112 => x"00000000",
+  3113 => x"00000000",
+  3114 => x"00000000",
+  3115 => x"00000000",
+  3116 => x"00000000",
+  3117 => x"00000000",
+  3118 => x"00000000",
+  3119 => x"00000000",
+  3120 => x"00000000",
+  3121 => x"00000000",
+  3122 => x"00000000",
+  3123 => x"00000000",
+  3124 => x"00000000",
+  3125 => x"00000000",
+  3126 => x"00000000",
+  3127 => x"00000000",
+  3128 => x"00000000",
+  3129 => x"00000000",
+  3130 => x"00000000",
+  3131 => x"00000000",
+  3132 => x"00000000",
+  3133 => x"00000000",
+  3134 => x"00000000",
+  3135 => x"00000000",
+  3136 => x"00000000",
+  3137 => x"00000000",
+  3138 => x"00000000",
+  3139 => x"00000000",
+  3140 => x"00000000",
+  3141 => x"00000000",
+  3142 => x"00000000",
+  3143 => x"00000000",
+  3144 => x"00000000",
+  3145 => x"00000000",
+  3146 => x"00000000",
+  3147 => x"00000000",
+  3148 => x"00000000",
+  3149 => x"00000000",
+  3150 => x"00000000",
+  3151 => x"00000000",
+  3152 => x"00000000",
+  3153 => x"00000000",
+  3154 => x"00000000",
+  3155 => x"00000000",
+  3156 => x"00000000",
+  3157 => x"00000000",
+  3158 => x"00000000",
+  3159 => x"00000000",
+  3160 => x"00000000",
+  3161 => x"00000000",
+  3162 => x"00000000",
+  3163 => x"00000000",
+  3164 => x"00000000",
+  3165 => x"00000000",
+  3166 => x"00000000",
+  3167 => x"00000000",
+  3168 => x"00000000",
+  3169 => x"00000000",
+  3170 => x"00000000",
+  3171 => x"00000000",
+  3172 => x"00000000",
+  3173 => x"00000000",
+  3174 => x"00000000",
+  3175 => x"00000000",
+  3176 => x"00000000",
+  3177 => x"00000000",
+  3178 => x"00000000",
+  3179 => x"00000000",
+  3180 => x"00000000",
+  3181 => x"00000000",
+  3182 => x"00000000",
+  3183 => x"00000000",
+  3184 => x"00000000",
+  3185 => x"00000000",
+  3186 => x"00000000",
+  3187 => x"00000000",
+  3188 => x"00000000",
+  3189 => x"00000000",
+  3190 => x"00000000",
+  3191 => x"00000000",
+  3192 => x"00000000",
+  3193 => x"00000000",
+  3194 => x"00000000",
+  3195 => x"00000000",
+  3196 => x"00000000",
+  3197 => x"00000000",
+  3198 => x"00000000",
+  3199 => x"00000000",
+  3200 => x"00000000",
+  3201 => x"00000000",
+  3202 => x"00000000",
+  3203 => x"00000000",
+  3204 => x"00000000",
+  3205 => x"00000000",
+  3206 => x"00000000",
+  3207 => x"00000000",
+  3208 => x"00000000",
+  3209 => x"00000000",
+  3210 => x"00000000",
+  3211 => x"00000000",
+  3212 => x"00000000",
+  3213 => x"00000000",
+  3214 => x"00000000",
+  3215 => x"00000000",
+  3216 => x"00000000",
+  3217 => x"00000000",
+  3218 => x"00000000",
+  3219 => x"00000000",
+  3220 => x"00000000",
+  3221 => x"00000000",
+  3222 => x"00000000",
+  3223 => x"00000000",
+  3224 => x"00000000",
+  3225 => x"00000000",
+  3226 => x"00000000",
+  3227 => x"00000000",
+  3228 => x"00000000",
+  3229 => x"00000000",
+  3230 => x"00000000",
+  3231 => x"00000000",
+  3232 => x"00000000",
+  3233 => x"00000000",
+  3234 => x"00000000",
+  3235 => x"00000000",
+  3236 => x"00000000",
+  3237 => x"00000000",
+  3238 => x"00000000",
+  3239 => x"00000000",
+  3240 => x"00000000",
+  3241 => x"00000000",
+  3242 => x"00000000",
+  3243 => x"00000000",
+  3244 => x"00000000",
+  3245 => x"00000000",
+  3246 => x"00000000",
+  3247 => x"00000000",
+  3248 => x"00000000",
+  3249 => x"00000000",
+  3250 => x"00000000",
+  3251 => x"00002ad4",
+  3252 => x"ffffffff",
+  3253 => x"00000000",
+  3254 => x"ffffffff",
+  3255 => x"00000000",
+  3256 => x"00000000",
+	others => x"00000000"
+);
+
+begin
+
+process (clk)
+begin
+	if (clk'event and clk = '1') then
+		if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then
+			report "write collision" severity failure;
+		end if;
+	
+		if (memAWriteEnable = '1') then
+			ram(to_integer(unsigned(memAAddr))) := memAWrite;
+			memARead <= memAWrite;
+		else
+			memARead <= ram(to_integer(unsigned(memAAddr)));
+		end if;
+	end if;
+end process;
+
+process (clk)
+begin
+	if (clk'event and clk = '1') then
+		if (memBWriteEnable = '1') then
+			ram(to_integer(unsigned(memBAddr))) := memBWrite;
+			memBRead <= memBWrite;
+		else
+			memBRead <= ram(to_integer(unsigned(memBAddr)));
+		end if;
+	end if;
+end process;
+
+
+
+
+end dualport_ram_arch;
diff --git a/zpu/hdl/example/helloworld.vhd b/zpu/hdl/example/helloworld.vhd
index a11bbb7..cc8d8c6 100644
--- a/zpu/hdl/example/helloworld.vhd
+++ b/zpu/hdl/example/helloworld.vhd
@@ -1,3154 +1,3154 @@
--- ZPU
---
--- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
--- 
--- The FreeBSD license
--- 
--- Redistribution and use in source and binary forms, with or without
--- modification, are permitted provided that the following conditions
--- are met:
--- 
--- 1. Redistributions of source code must retain the above copyright
---    notice, this list of conditions and the following disclaimer.
--- 2. Redistributions in binary form must reproduce the above
---    copyright notice, this list of conditions and the following
---    disclaimer in the documentation and/or other materials
---    provided with the distribution.
--- 
--- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
--- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
--- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
--- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
--- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
--- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
--- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
--- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
--- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
--- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--- 
--- The views and conclusions contained in the software and documentation
--- are those of the authors and should not be interpreted as representing
--- official policies, either expressed or implied, of the ZPU Project.
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-
-library work;
-use work.zpu_config.all;
-use work.zpupkg.all;
-
-entity dualport_ram is
-port (clk : in std_logic;
-	memAWriteEnable : in std_logic;
-	memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
-	memAWrite : in std_logic_vector(wordSize-1 downto 0);
-	memARead : out std_logic_vector(wordSize-1 downto 0);
-	memBWriteEnable : in std_logic;
-	memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
-	memBWrite : in std_logic_vector(wordSize-1 downto 0);
-	memBRead : out std_logic_vector(wordSize-1 downto 0));
-end dualport_ram;
-
-architecture dualport_ram_arch of dualport_ram is
-
-
-type ram_type is array(natural range 0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
-
-shared variable ram : ram_type :=
-(
-0 => x"0b0b0b0b",
-1 => x"82700b0b",
-2 => x"80cfd80c",
-3 => x"3a0b0b80",
-4 => x"c6d00400",
-5 => x"00000000",
-6 => x"00000000",
-7 => x"00000000",
-8 => x"80088408",
-9 => x"88080b0b",
-10 => x"80c7972d",
-11 => x"880c840c",
-12 => x"800c0400",
-13 => x"00000000",
-14 => x"00000000",
-15 => x"00000000",
-16 => x"71fd0608",
-17 => x"72830609",
-18 => x"81058205",
-19 => x"832b2a83",
-20 => x"ffff0652",
-21 => x"04000000",
-22 => x"00000000",
-23 => x"00000000",
-24 => x"71fd0608",
-25 => x"83ffff73",
-26 => x"83060981",
-27 => x"05820583",
-28 => x"2b2b0906",
-29 => x"7383ffff",
-30 => x"0b0b0b0b",
-31 => x"83a70400",
-32 => x"72098105",
-33 => x"72057373",
-34 => x"09060906",
-35 => x"73097306",
-36 => x"070a8106",
-37 => x"53510400",
-38 => x"00000000",
-39 => x"00000000",
-40 => x"72722473",
-41 => x"732e0753",
-42 => x"51040000",
-43 => x"00000000",
-44 => x"00000000",
-45 => x"00000000",
-46 => x"00000000",
-47 => x"00000000",
-48 => x"71737109",
-49 => x"71068106",
-50 => x"30720a10",
-51 => x"0a720a10",
-52 => x"0a31050a",
-53 => x"81065151",
-54 => x"53510400",
-55 => x"00000000",
-56 => x"72722673",
-57 => x"732e0753",
-58 => x"51040000",
-59 => x"00000000",
-60 => x"00000000",
-61 => x"00000000",
-62 => x"00000000",
-63 => x"00000000",
-64 => x"00000000",
-65 => x"00000000",
-66 => x"00000000",
-67 => x"00000000",
-68 => x"00000000",
-69 => x"00000000",
-70 => x"00000000",
-71 => x"00000000",
-72 => x"0b0b0b88",
-73 => x"c4040000",
-74 => x"00000000",
-75 => x"00000000",
-76 => x"00000000",
-77 => x"00000000",
-78 => x"00000000",
-79 => x"00000000",
-80 => x"720a722b",
-81 => x"0a535104",
-82 => x"00000000",
-83 => x"00000000",
-84 => x"00000000",
-85 => x"00000000",
-86 => x"00000000",
-87 => x"00000000",
-88 => x"72729f06",
-89 => x"0981050b",
-90 => x"0b0b88a7",
-91 => x"05040000",
-92 => x"00000000",
-93 => x"00000000",
-94 => x"00000000",
-95 => x"00000000",
-96 => x"72722aff",
-97 => x"739f062a",
-98 => x"0974090a",
-99 => x"8106ff05",
-100 => x"06075351",
-101 => x"04000000",
-102 => x"00000000",
-103 => x"00000000",
-104 => x"71715351",
-105 => x"020d0406",
-106 => x"73830609",
-107 => x"81058205",
-108 => x"832b0b2b",
-109 => x"0772fc06",
-110 => x"0c515104",
-111 => x"00000000",
-112 => x"72098105",
-113 => x"72050970",
-114 => x"81050906",
-115 => x"0a810653",
-116 => x"51040000",
-117 => x"00000000",
-118 => x"00000000",
-119 => x"00000000",
-120 => x"72098105",
-121 => x"72050970",
-122 => x"81050906",
-123 => x"0a098106",
-124 => x"53510400",
-125 => x"00000000",
-126 => x"00000000",
-127 => x"00000000",
-128 => x"71098105",
-129 => x"52040000",
-130 => x"00000000",
-131 => x"00000000",
-132 => x"00000000",
-133 => x"00000000",
-134 => x"00000000",
-135 => x"00000000",
-136 => x"72720981",
-137 => x"05055351",
-138 => x"04000000",
-139 => x"00000000",
-140 => x"00000000",
-141 => x"00000000",
-142 => x"00000000",
-143 => x"00000000",
-144 => x"72097206",
-145 => x"73730906",
-146 => x"07535104",
-147 => x"00000000",
-148 => x"00000000",
-149 => x"00000000",
-150 => x"00000000",
-151 => x"00000000",
-152 => x"71fc0608",
-153 => x"72830609",
-154 => x"81058305",
-155 => x"1010102a",
-156 => x"81ff0652",
-157 => x"04000000",
-158 => x"00000000",
-159 => x"00000000",
-160 => x"71fc0608",
-161 => x"0b0b80cf",
-162 => x"c4738306",
-163 => x"10100508",
-164 => x"060b0b0b",
-165 => x"88aa0400",
-166 => x"00000000",
-167 => x"00000000",
-168 => x"80088408",
-169 => x"88087575",
-170 => x"0b0b0b8b",
-171 => x"9f2d5050",
-172 => x"80085688",
-173 => x"0c840c80",
-174 => x"0c510400",
-175 => x"00000000",
-176 => x"80088408",
-177 => x"88087575",
-178 => x"0b0b0b8b",
-179 => x"e32d5050",
-180 => x"80085688",
-181 => x"0c840c80",
-182 => x"0c510400",
-183 => x"00000000",
-184 => x"72097081",
-185 => x"0509060a",
-186 => x"8106ff05",
-187 => x"70547106",
-188 => x"73097274",
-189 => x"05ff0506",
-190 => x"07515151",
-191 => x"04000000",
-192 => x"72097081",
-193 => x"0509060a",
-194 => x"098106ff",
-195 => x"05705471",
-196 => x"06730972",
-197 => x"7405ff05",
-198 => x"06075151",
-199 => x"51040000",
-200 => x"05ff0504",
-201 => x"00000000",
-202 => x"00000000",
-203 => x"00000000",
-204 => x"00000000",
-205 => x"00000000",
-206 => x"00000000",
-207 => x"00000000",
-208 => x"810b0b0b",
-209 => x"80cfd40c",
-210 => x"51040000",
-211 => x"00000000",
-212 => x"00000000",
-213 => x"00000000",
-214 => x"00000000",
-215 => x"00000000",
-216 => x"71810552",
-217 => x"04000000",
-218 => x"00000000",
-219 => x"00000000",
-220 => x"00000000",
-221 => x"00000000",
-222 => x"00000000",
-223 => x"00000000",
-224 => x"00000000",
-225 => x"00000000",
-226 => x"00000000",
-227 => x"00000000",
-228 => x"00000000",
-229 => x"00000000",
-230 => x"00000000",
-231 => x"00000000",
-232 => x"02840572",
-233 => x"10100552",
-234 => x"04000000",
-235 => x"00000000",
-236 => x"00000000",
-237 => x"00000000",
-238 => x"00000000",
-239 => x"00000000",
-240 => x"00000000",
-241 => x"00000000",
-242 => x"00000000",
-243 => x"00000000",
-244 => x"00000000",
-245 => x"00000000",
-246 => x"00000000",
-247 => x"00000000",
-248 => x"717105ff",
-249 => x"05715351",
-250 => x"020d0400",
-251 => x"00000000",
-252 => x"00000000",
-253 => x"00000000",
-254 => x"00000000",
-255 => x"00000000",
-256 => x"82c53f80",
-257 => x"c6d93f04",
-258 => x"10101010",
-259 => x"10101010",
-260 => x"10101010",
-261 => x"10101010",
-262 => x"10101010",
-263 => x"10101010",
-264 => x"10101010",
-265 => x"10101053",
-266 => x"51047381",
-267 => x"ff067383",
-268 => x"06098105",
-269 => x"83051010",
-270 => x"102b0772",
-271 => x"fc060c51",
-272 => x"51043c04",
-273 => x"72728072",
-274 => x"8106ff05",
-275 => x"09720605",
-276 => x"71105272",
-277 => x"0a100a53",
-278 => x"72ed3851",
-279 => x"51535104",
-280 => x"fe3d0d0b",
-281 => x"0b80dfc0",
-282 => x"08538413",
-283 => x"0870882a",
-284 => x"70810651",
-285 => x"52527080",
-286 => x"2ef03871",
-287 => x"81ff0680",
-288 => x"0c843d0d",
-289 => x"04ff3d0d",
-290 => x"0b0b80df",
-291 => x"c0085271",
-292 => x"0870882a",
-293 => x"81327081",
-294 => x"06515151",
-295 => x"70f13873",
-296 => x"720c833d",
-297 => x"0d0480cf",
-298 => x"d408802e",
-299 => x"a43880cf",
-300 => x"d808822e",
-301 => x"bd388380",
-302 => x"800b0b0b",
-303 => x"80dfc00c",
-304 => x"82a0800b",
-305 => x"80dfc40c",
-306 => x"8290800b",
-307 => x"80dfc80c",
-308 => x"04f88080",
-309 => x"80a40b0b",
-310 => x"0b80dfc0",
-311 => x"0cf88080",
-312 => x"82800b80",
-313 => x"dfc40cf8",
-314 => x"80808480",
-315 => x"0b80dfc8",
-316 => x"0c0480c0",
-317 => x"a8808c0b",
-318 => x"0b0b80df",
-319 => x"c00c80c0",
-320 => x"a880940b",
-321 => x"80dfc40c",
-322 => x"0b0b80cf",
-323 => x"8c0b80df",
-324 => x"c80c0470",
-325 => x"7080dfcc",
-326 => x"335170a7",
-327 => x"3880cfe0",
-328 => x"08700852",
-329 => x"5270802e",
-330 => x"94388412",
-331 => x"80cfe00c",
-332 => x"702d80cf",
-333 => x"e0087008",
-334 => x"525270ee",
-335 => x"38810b80",
-336 => x"dfcc3450",
-337 => x"50040470",
-338 => x"0b0b80df",
-339 => x"bc08802e",
-340 => x"8e380b0b",
-341 => x"0b0b800b",
-342 => x"802e0981",
-343 => x"06833850",
-344 => x"040b0b80",
-345 => x"dfbc510b",
-346 => x"0b0bf594",
-347 => x"3f500404",
-348 => x"fe3d0d89",
-349 => x"5380cf90",
-350 => x"5182c13f",
-351 => x"80cfa051",
-352 => x"82ba3f81",
-353 => x"0a0b80df",
-354 => x"d80cff0b",
-355 => x"80dfdc0c",
-356 => x"ff135372",
-357 => x"8025de38",
-358 => x"72800c84",
-359 => x"3d0d04fb",
-360 => x"3d0d7779",
-361 => x"55558056",
-362 => x"757524ab",
-363 => x"38807424",
-364 => x"9d388053",
-365 => x"73527451",
-366 => x"80e13f80",
-367 => x"08547580",
-368 => x"2e853880",
-369 => x"08305473",
-370 => x"800c873d",
-371 => x"0d047330",
-372 => x"76813257",
-373 => x"54dc3974",
-374 => x"30558156",
-375 => x"738025d2",
-376 => x"38ec39fa",
-377 => x"3d0d787a",
-378 => x"57558057",
-379 => x"767524a4",
-380 => x"38759f2c",
-381 => x"54815375",
-382 => x"74327431",
-383 => x"5274519b",
-384 => x"3f800854",
-385 => x"76802e85",
-386 => x"38800830",
-387 => x"5473800c",
-388 => x"883d0d04",
-389 => x"74305581",
-390 => x"57d739fc",
-391 => x"3d0d7678",
-392 => x"53548153",
-393 => x"80747326",
-394 => x"52557280",
-395 => x"2e983870",
-396 => x"802eab38",
-397 => x"807224a6",
-398 => x"38711073",
-399 => x"10757226",
-400 => x"53545272",
-401 => x"ea387351",
-402 => x"78833874",
-403 => x"5170800c",
-404 => x"863d0d04",
-405 => x"720a100a",
-406 => x"720a100a",
-407 => x"53537280",
-408 => x"2ee43871",
-409 => x"7426ed38",
-410 => x"73723175",
-411 => x"7407740a",
-412 => x"100a740a",
-413 => x"100a5555",
-414 => x"5654e339",
-415 => x"f73d0d7c",
-416 => x"70525380",
-417 => x"f93f7254",
-418 => x"80085580",
-419 => x"cfb05681",
-420 => x"57800881",
-421 => x"055a8b3d",
-422 => x"e4115953",
-423 => x"8259f413",
-424 => x"527b8811",
-425 => x"08525381",
-426 => x"b23f8008",
-427 => x"30708008",
-428 => x"079f2c8a",
-429 => x"07800c53",
-430 => x"8b3d0d04",
-431 => x"f63d0d7c",
-432 => x"80cfe408",
-433 => x"71535553",
-434 => x"b53f7255",
-435 => x"80085680",
-436 => x"cfb05781",
-437 => x"58800881",
-438 => x"055b8c3d",
-439 => x"e4115a53",
-440 => x"825af413",
-441 => x"52881408",
-442 => x"5180f03f",
-443 => x"80083070",
-444 => x"8008079f",
-445 => x"2c8a0780",
-446 => x"0c548c3d",
-447 => x"0d047070",
-448 => x"70707570",
-449 => x"71830653",
-450 => x"555270b4",
-451 => x"38717008",
-452 => x"7009f7fb",
-453 => x"fdff1206",
-454 => x"f8848281",
-455 => x"80065452",
-456 => x"53719b38",
-457 => x"84137008",
-458 => x"7009f7fb",
-459 => x"fdff1206",
-460 => x"f8848281",
-461 => x"80065452",
-462 => x"5371802e",
-463 => x"e7387252",
-464 => x"71335372",
-465 => x"802e8a38",
-466 => x"81127033",
-467 => x"545272f8",
-468 => x"38717431",
-469 => x"800c5050",
-470 => x"505004f2",
-471 => x"3d0d6062",
-472 => x"88110870",
-473 => x"58565f5a",
-474 => x"73802e81",
-475 => x"8c388c1a",
-476 => x"2270832a",
-477 => x"81328106",
-478 => x"56587486",
-479 => x"38901a08",
-480 => x"91387951",
-481 => x"90b73fff",
-482 => x"55800880",
-483 => x"ec388c1a",
-484 => x"22587d08",
-485 => x"55807883",
-486 => x"ffff0670",
-487 => x"0a100a81",
-488 => x"06415c57",
-489 => x"7e772e80",
-490 => x"d7387690",
-491 => x"38740884",
-492 => x"16088817",
-493 => x"57585676",
-494 => x"802ef238",
-495 => x"76548880",
-496 => x"77278438",
-497 => x"88805473",
-498 => x"5375529c",
-499 => x"1a0851a4",
-500 => x"1a085877",
-501 => x"2d800b80",
-502 => x"082582e0",
-503 => x"38800816",
-504 => x"77800831",
-505 => x"7f880508",
-506 => x"80083170",
-507 => x"6188050c",
-508 => x"5b585678",
-509 => x"ffb43880",
-510 => x"5574800c",
-511 => x"903d0d04",
-512 => x"7a813281",
-513 => x"06774056",
-514 => x"75802e81",
-515 => x"bd387690",
-516 => x"38740884",
-517 => x"16088817",
-518 => x"57585976",
-519 => x"802ef238",
-520 => x"881a0878",
-521 => x"83ffff06",
-522 => x"70892a81",
-523 => x"06565956",
-524 => x"73802e82",
-525 => x"f8387577",
-526 => x"278b3877",
-527 => x"872a8106",
-528 => x"5c7b82b5",
-529 => x"38767627",
-530 => x"83387656",
-531 => x"75537852",
-532 => x"79085185",
-533 => x"833f881a",
-534 => x"08763188",
-535 => x"1b0c7908",
-536 => x"167a0c76",
-537 => x"56751977",
-538 => x"77317f88",
-539 => x"05087831",
-540 => x"70618805",
-541 => x"0c415859",
-542 => x"7e802efe",
-543 => x"fa388c1a",
-544 => x"2258ff8a",
-545 => x"39787954",
-546 => x"7c537b52",
-547 => x"5684c93f",
-548 => x"881a0879",
-549 => x"31881b0c",
-550 => x"7908197a",
-551 => x"0c7c7631",
-552 => x"5d7c8e38",
-553 => x"79518ff2",
-554 => x"3f800881",
-555 => x"8f388008",
-556 => x"5f751c77",
-557 => x"77317f88",
-558 => x"05087831",
-559 => x"70618805",
-560 => x"0c5d585c",
-561 => x"7a802efe",
-562 => x"ae387681",
-563 => x"83387408",
-564 => x"84160888",
-565 => x"1757585c",
-566 => x"76802ef2",
-567 => x"3876538a",
-568 => x"527b5182",
-569 => x"d33f8008",
-570 => x"7c318105",
-571 => x"5d800884",
-572 => x"3881175d",
-573 => x"815f7c59",
-574 => x"767d2783",
-575 => x"38765994",
-576 => x"1a08881b",
-577 => x"08115758",
-578 => x"807a085c",
-579 => x"54901a08",
-580 => x"7b278338",
-581 => x"81547579",
-582 => x"25843873",
-583 => x"ba387779",
-584 => x"24fee238",
-585 => x"77537b52",
-586 => x"9c1a0851",
-587 => x"a41a0859",
-588 => x"782d8008",
-589 => x"56800880",
-590 => x"24fee238",
-591 => x"8c1a2280",
-592 => x"c0075e7d",
-593 => x"8c1b23ff",
-594 => x"5574800c",
-595 => x"903d0d04",
-596 => x"7effa338",
-597 => x"ff873975",
-598 => x"537b527a",
-599 => x"5182f93f",
-600 => x"7908167a",
-601 => x"0c79518e",
-602 => x"b13f8008",
-603 => x"cf387c76",
-604 => x"315d7cfe",
-605 => x"bc38feac",
-606 => x"39901a08",
-607 => x"7a087131",
-608 => x"78117056",
-609 => x"5a575280",
-610 => x"cfe40851",
-611 => x"84943f80",
-612 => x"08802eff",
-613 => x"a7388008",
-614 => x"901b0c80",
-615 => x"08167a0c",
-616 => x"77941b0c",
-617 => x"76881b0c",
-618 => x"7656fd99",
-619 => x"39790858",
-620 => x"901a0878",
-621 => x"27833881",
-622 => x"54757727",
-623 => x"843873b3",
-624 => x"38941a08",
-625 => x"54737726",
-626 => x"80d33873",
-627 => x"5378529c",
-628 => x"1a0851a4",
-629 => x"1a085877",
-630 => x"2d800856",
-631 => x"80088024",
-632 => x"fd83388c",
-633 => x"1a2280c0",
-634 => x"075e7d8c",
-635 => x"1b23ff55",
-636 => x"fed73975",
-637 => x"53785277",
-638 => x"5181dd3f",
-639 => x"7908167a",
-640 => x"0c79518d",
-641 => x"953f8008",
-642 => x"802efcd9",
-643 => x"388c1a22",
-644 => x"80c0075e",
-645 => x"7d8c1b23",
-646 => x"ff55fead",
-647 => x"39767754",
-648 => x"79537852",
-649 => x"5681b13f",
-650 => x"881a0877",
-651 => x"31881b0c",
-652 => x"7908177a",
-653 => x"0cfcae39",
-654 => x"fa3d0d7a",
-655 => x"79028805",
-656 => x"a7053355",
-657 => x"53548374",
-658 => x"2780df38",
-659 => x"71830651",
-660 => x"7080d738",
-661 => x"71715755",
-662 => x"83517582",
-663 => x"802913ff",
-664 => x"12525670",
-665 => x"8025f338",
-666 => x"837427bc",
-667 => x"38740876",
-668 => x"327009f7",
-669 => x"fbfdff12",
-670 => x"06f88482",
-671 => x"81800651",
-672 => x"5170802e",
-673 => x"98387451",
-674 => x"80527033",
-675 => x"5772772e",
-676 => x"b9388111",
-677 => x"81135351",
-678 => x"837227ee",
-679 => x"38fc1484",
-680 => x"16565473",
-681 => x"8326c638",
-682 => x"7452ff14",
-683 => x"5170ff2e",
-684 => x"97387133",
-685 => x"5472742e",
-686 => x"98388112",
-687 => x"ff125252",
-688 => x"70ff2e09",
-689 => x"8106eb38",
-690 => x"80517080",
-691 => x"0c883d0d",
-692 => x"0471800c",
-693 => x"883d0d04",
-694 => x"fa3d0d78",
-695 => x"7a7c7272",
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-2564 => x"00000000",
-2565 => x"00000000",
-2566 => x"00000000",
-2567 => x"000027b4",
-2568 => x"00000000",
-2569 => x"00000000",
-2570 => x"00000000",
-2571 => x"00000000",
-2572 => x"00000000",
-2573 => x"00000000",
-2574 => x"00000000",
-2575 => x"00000000",
-2576 => x"00000000",
-2577 => x"00000000",
-2578 => x"00000000",
-2579 => x"00000000",
-2580 => x"00000000",
-2581 => x"00000000",
-2582 => x"00000000",
-2583 => x"00000000",
-2584 => x"00000000",
-2585 => x"00000000",
-2586 => x"00000000",
-2587 => x"00000000",
-2588 => x"00000000",
-2589 => x"00000000",
-2590 => x"00000000",
-2591 => x"00000000",
-2592 => x"00000000",
-2593 => x"00000000",
-2594 => x"00000000",
-2595 => x"00000000",
-2596 => x"00000001",
-2597 => x"330eabcd",
-2598 => x"1234e66d",
-2599 => x"deec0005",
-2600 => x"000b0000",
-2601 => x"00000000",
-2602 => x"00000000",
-2603 => x"00000000",
-2604 => x"00000000",
-2605 => x"00000000",
-2606 => x"00000000",
-2607 => x"00000000",
-2608 => x"00000000",
-2609 => x"00000000",
-2610 => x"00000000",
-2611 => x"00000000",
-2612 => x"00000000",
-2613 => x"00000000",
-2614 => x"00000000",
-2615 => x"00000000",
-2616 => x"00000000",
-2617 => x"00000000",
-2618 => x"00000000",
-2619 => x"00000000",
-2620 => x"00000000",
-2621 => x"00000000",
-2622 => x"00000000",
-2623 => x"00000000",
-2624 => x"00000000",
-2625 => x"00000000",
-2626 => x"00000000",
-2627 => x"00000000",
-2628 => x"00000000",
-2629 => x"00000000",
-2630 => x"00000000",
-2631 => x"00000000",
-2632 => x"00000000",
-2633 => x"00000000",
-2634 => x"00000000",
-2635 => x"00000000",
-2636 => x"00000000",
-2637 => x"00000000",
-2638 => x"00000000",
-2639 => x"00000000",
-2640 => x"00000000",
-2641 => x"00000000",
-2642 => x"00000000",
-2643 => x"00000000",
-2644 => x"00000000",
-2645 => x"00000000",
-2646 => x"00000000",
-2647 => x"00000000",
-2648 => x"00000000",
-2649 => x"00000000",
-2650 => x"00000000",
-2651 => x"00000000",
-2652 => x"00000000",
-2653 => x"00000000",
-2654 => x"00000000",
-2655 => x"00000000",
-2656 => x"00000000",
-2657 => x"00000000",
-2658 => x"00000000",
-2659 => x"00000000",
-2660 => x"00000000",
-2661 => x"00000000",
-2662 => x"00000000",
-2663 => x"00000000",
-2664 => x"00000000",
-2665 => x"00000000",
-2666 => x"00000000",
-2667 => x"00000000",
-2668 => x"00000000",
-2669 => x"00000000",
-2670 => x"00000000",
-2671 => x"00000000",
-2672 => x"00000000",
-2673 => x"00000000",
-2674 => x"00000000",
-2675 => x"00000000",
-2676 => x"00000000",
-2677 => x"00000000",
-2678 => x"00000000",
-2679 => x"00000000",
-2680 => x"00000000",
-2681 => x"00000000",
-2682 => x"00000000",
-2683 => x"00000000",
-2684 => x"00000000",
-2685 => x"00000000",
-2686 => x"00000000",
-2687 => x"00000000",
-2688 => x"00000000",
-2689 => x"00000000",
-2690 => x"00000000",
-2691 => x"00000000",
-2692 => x"00000000",
-2693 => x"00000000",
-2694 => x"00000000",
-2695 => x"00000000",
-2696 => x"00000000",
-2697 => x"00000000",
-2698 => x"00000000",
-2699 => x"00000000",
-2700 => x"00000000",
-2701 => x"00000000",
-2702 => x"00000000",
-2703 => x"00000000",
-2704 => x"00000000",
-2705 => x"00000000",
-2706 => x"00000000",
-2707 => x"00000000",
-2708 => x"00000000",
-2709 => x"00000000",
-2710 => x"00000000",
-2711 => x"00000000",
-2712 => x"00000000",
-2713 => x"00000000",
-2714 => x"00000000",
-2715 => x"00000000",
-2716 => x"00000000",
-2717 => x"00000000",
-2718 => x"00000000",
-2719 => x"00000000",
-2720 => x"00000000",
-2721 => x"00000000",
-2722 => x"00000000",
-2723 => x"00000000",
-2724 => x"00000000",
-2725 => x"00000000",
-2726 => x"00000000",
-2727 => x"00000000",
-2728 => x"00000000",
-2729 => x"00000000",
-2730 => x"00000000",
-2731 => x"00000000",
-2732 => x"00000000",
-2733 => x"00000000",
-2734 => x"00000000",
-2735 => x"00000000",
-2736 => x"00000000",
-2737 => x"00000000",
-2738 => x"00000000",
-2739 => x"00000000",
-2740 => x"00000000",
-2741 => x"00000000",
-2742 => x"00000000",
-2743 => x"00000000",
-2744 => x"00000000",
-2745 => x"00000000",
-2746 => x"00000000",
-2747 => x"00000000",
-2748 => x"00000000",
-2749 => x"00000000",
-2750 => x"00000000",
-2751 => x"00000000",
-2752 => x"00000000",
-2753 => x"00000000",
-2754 => x"00000000",
-2755 => x"00000000",
-2756 => x"00000000",
-2757 => x"00000000",
-2758 => x"00000000",
-2759 => x"00000000",
-2760 => x"00000000",
-2761 => x"00000000",
-2762 => x"00000000",
-2763 => x"00000000",
-2764 => x"00000000",
-2765 => x"00000000",
-2766 => x"00000000",
-2767 => x"00000000",
-2768 => x"00000000",
-2769 => x"00000000",
-2770 => x"00000000",
-2771 => x"00000000",
-2772 => x"00000000",
-2773 => x"00000000",
-2774 => x"00000000",
-2775 => x"00000000",
-2776 => x"00000000",
-2777 => x"00000000",
-2778 => x"00000000",
-2779 => x"00000000",
-2780 => x"00000000",
-2781 => x"00000000",
-2782 => x"00000000",
-2783 => x"00000000",
-2784 => x"00000000",
-2785 => x"00000000",
-2786 => x"00000000",
-2787 => x"00000000",
-2788 => x"00000000",
-2789 => x"ffffffff",
-2790 => x"00000000",
-2791 => x"00020000",
-2792 => x"00000000",
-2793 => x"00000000",
-2794 => x"00002ba0",
-2795 => x"00002ba0",
-2796 => x"00002ba8",
-2797 => x"00002ba8",
-2798 => x"00002bb0",
-2799 => x"00002bb0",
-2800 => x"00002bb8",
-2801 => x"00002bb8",
-2802 => x"00002bc0",
-2803 => x"00002bc0",
-2804 => x"00002bc8",
-2805 => x"00002bc8",
-2806 => x"00002bd0",
-2807 => x"00002bd0",
-2808 => x"00002bd8",
-2809 => x"00002bd8",
-2810 => x"00002be0",
-2811 => x"00002be0",
-2812 => x"00002be8",
-2813 => x"00002be8",
-2814 => x"00002bf0",
-2815 => x"00002bf0",
-2816 => x"00002bf8",
-2817 => x"00002bf8",
-2818 => x"00002c00",
-2819 => x"00002c00",
-2820 => x"00002c08",
-2821 => x"00002c08",
-2822 => x"00002c10",
-2823 => x"00002c10",
-2824 => x"00002c18",
-2825 => x"00002c18",
-2826 => x"00002c20",
-2827 => x"00002c20",
-2828 => x"00002c28",
-2829 => x"00002c28",
-2830 => x"00002c30",
-2831 => x"00002c30",
-2832 => x"00002c38",
-2833 => x"00002c38",
-2834 => x"00002c40",
-2835 => x"00002c40",
-2836 => x"00002c48",
-2837 => x"00002c48",
-2838 => x"00002c50",
-2839 => x"00002c50",
-2840 => x"00002c58",
-2841 => x"00002c58",
-2842 => x"00002c60",
-2843 => x"00002c60",
-2844 => x"00002c68",
-2845 => x"00002c68",
-2846 => x"00002c70",
-2847 => x"00002c70",
-2848 => x"00002c78",
-2849 => x"00002c78",
-2850 => x"00002c80",
-2851 => x"00002c80",
-2852 => x"00002c88",
-2853 => x"00002c88",
-2854 => x"00002c90",
-2855 => x"00002c90",
-2856 => x"00002c98",
-2857 => x"00002c98",
-2858 => x"00002ca0",
-2859 => x"00002ca0",
-2860 => x"00002ca8",
-2861 => x"00002ca8",
-2862 => x"00002cb0",
-2863 => x"00002cb0",
-2864 => x"00002cb8",
-2865 => x"00002cb8",
-2866 => x"00002cc0",
-2867 => x"00002cc0",
-2868 => x"00002cc8",
-2869 => x"00002cc8",
-2870 => x"00002cd0",
-2871 => x"00002cd0",
-2872 => x"00002cd8",
-2873 => x"00002cd8",
-2874 => x"00002ce0",
-2875 => x"00002ce0",
-2876 => x"00002ce8",
-2877 => x"00002ce8",
-2878 => x"00002cf0",
-2879 => x"00002cf0",
-2880 => x"00002cf8",
-2881 => x"00002cf8",
-2882 => x"00002d00",
-2883 => x"00002d00",
-2884 => x"00002d08",
-2885 => x"00002d08",
-2886 => x"00002d10",
-2887 => x"00002d10",
-2888 => x"00002d18",
-2889 => x"00002d18",
-2890 => x"00002d20",
-2891 => x"00002d20",
-2892 => x"00002d28",
-2893 => x"00002d28",
-2894 => x"00002d30",
-2895 => x"00002d30",
-2896 => x"00002d38",
-2897 => x"00002d38",
-2898 => x"00002d40",
-2899 => x"00002d40",
-2900 => x"00002d48",
-2901 => x"00002d48",
-2902 => x"00002d50",
-2903 => x"00002d50",
-2904 => x"00002d58",
-2905 => x"00002d58",
-2906 => x"00002d60",
-2907 => x"00002d60",
-2908 => x"00002d68",
-2909 => x"00002d68",
-2910 => x"00002d70",
-2911 => x"00002d70",
-2912 => x"00002d78",
-2913 => x"00002d78",
-2914 => x"00002d80",
-2915 => x"00002d80",
-2916 => x"00002d88",
-2917 => x"00002d88",
-2918 => x"00002d90",
-2919 => x"00002d90",
-2920 => x"00002d98",
-2921 => x"00002d98",
-2922 => x"00002da0",
-2923 => x"00002da0",
-2924 => x"00002da8",
-2925 => x"00002da8",
-2926 => x"00002db0",
-2927 => x"00002db0",
-2928 => x"00002db8",
-2929 => x"00002db8",
-2930 => x"00002dc0",
-2931 => x"00002dc0",
-2932 => x"00002dc8",
-2933 => x"00002dc8",
-2934 => x"00002dd0",
-2935 => x"00002dd0",
-2936 => x"00002dd8",
-2937 => x"00002dd8",
-2938 => x"00002de0",
-2939 => x"00002de0",
-2940 => x"00002de8",
-2941 => x"00002de8",
-2942 => x"00002df0",
-2943 => x"00002df0",
-2944 => x"00002df8",
-2945 => x"00002df8",
-2946 => x"00002e00",
-2947 => x"00002e00",
-2948 => x"00002e08",
-2949 => x"00002e08",
-2950 => x"00002e10",
-2951 => x"00002e10",
-2952 => x"00002e18",
-2953 => x"00002e18",
-2954 => x"00002e20",
-2955 => x"00002e20",
-2956 => x"00002e28",
-2957 => x"00002e28",
-2958 => x"00002e30",
-2959 => x"00002e30",
-2960 => x"00002e38",
-2961 => x"00002e38",
-2962 => x"00002e40",
-2963 => x"00002e40",
-2964 => x"00002e48",
-2965 => x"00002e48",
-2966 => x"00002e50",
-2967 => x"00002e50",
-2968 => x"00002e58",
-2969 => x"00002e58",
-2970 => x"00002e60",
-2971 => x"00002e60",
-2972 => x"00002e68",
-2973 => x"00002e68",
-2974 => x"00002e70",
-2975 => x"00002e70",
-2976 => x"00002e78",
-2977 => x"00002e78",
-2978 => x"00002e80",
-2979 => x"00002e80",
-2980 => x"00002e88",
-2981 => x"00002e88",
-2982 => x"00002e90",
-2983 => x"00002e90",
-2984 => x"00002e98",
-2985 => x"00002e98",
-2986 => x"00002ea0",
-2987 => x"00002ea0",
-2988 => x"00002ea8",
-2989 => x"00002ea8",
-2990 => x"00002eb0",
-2991 => x"00002eb0",
-2992 => x"00002eb8",
-2993 => x"00002eb8",
-2994 => x"00002ec0",
-2995 => x"00002ec0",
-2996 => x"00002ec8",
-2997 => x"00002ec8",
-2998 => x"00002ed0",
-2999 => x"00002ed0",
-3000 => x"00002ed8",
-3001 => x"00002ed8",
-3002 => x"00002ee0",
-3003 => x"00002ee0",
-3004 => x"00002ee8",
-3005 => x"00002ee8",
-3006 => x"00002ef0",
-3007 => x"00002ef0",
-3008 => x"00002ef8",
-3009 => x"00002ef8",
-3010 => x"00002f00",
-3011 => x"00002f00",
-3012 => x"00002f08",
-3013 => x"00002f08",
-3014 => x"00002f10",
-3015 => x"00002f10",
-3016 => x"00002f18",
-3017 => x"00002f18",
-3018 => x"00002f20",
-3019 => x"00002f20",
-3020 => x"00002f28",
-3021 => x"00002f28",
-3022 => x"00002f30",
-3023 => x"00002f30",
-3024 => x"00002f38",
-3025 => x"00002f38",
-3026 => x"00002f40",
-3027 => x"00002f40",
-3028 => x"00002f48",
-3029 => x"00002f48",
-3030 => x"00002f50",
-3031 => x"00002f50",
-3032 => x"00002f58",
-3033 => x"00002f58",
-3034 => x"00002f60",
-3035 => x"00002f60",
-3036 => x"00002f68",
-3037 => x"00002f68",
-3038 => x"00002f70",
-3039 => x"00002f70",
-3040 => x"00002f78",
-3041 => x"00002f78",
-3042 => x"00002f80",
-3043 => x"00002f80",
-3044 => x"00002f88",
-3045 => x"00002f88",
-3046 => x"00002f90",
-3047 => x"00002f90",
-3048 => x"00002f98",
-3049 => x"00002f98",
-3050 => x"000027b8",
-3051 => x"ffffffff",
-3052 => x"00000000",
-3053 => x"ffffffff",
-3054 => x"00000000",
-	others => x"00000000"
-);
-
-begin
-
-process (clk)
-begin
-	if (clk'event and clk = '1') then
-		if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then
-			report "write collision" severity failure;
-		end if;
-	
-		if (memAWriteEnable = '1') then
-			ram(to_integer(unsigned(memAAddr))) := memAWrite;
-			memARead <= memAWrite;
-		else
-			memARead <= ram(to_integer(unsigned(memAAddr)));
-		end if;
-	end if;
-end process;
-
-process (clk)
-begin
-	if (clk'event and clk = '1') then
-		if (memBWriteEnable = '1') then
-			ram(to_integer(unsigned(memBAddr))) := memBWrite;
-			memBRead <= memBWrite;
-		else
-			memBRead <= ram(to_integer(unsigned(memBAddr)));
-		end if;
-	end if;
-end process;
-
-
-
-
-end dualport_ram_arch;
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity dualport_ram is
+port (clk : in std_logic;
+	memAWriteEnable : in std_logic;
+	memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+	memAWrite : in std_logic_vector(wordSize-1 downto 0);
+	memARead : out std_logic_vector(wordSize-1 downto 0);
+	memBWriteEnable : in std_logic;
+	memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+	memBWrite : in std_logic_vector(wordSize-1 downto 0);
+	memBRead : out std_logic_vector(wordSize-1 downto 0));
+end dualport_ram;
+
+architecture dualport_ram_arch of dualport_ram is
+
+
+type ram_type is array(natural range 0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
+
+shared variable ram : ram_type :=
+(
+0 => x"0b0b0b0b",
+1 => x"82700b0b",
+2 => x"80cfd80c",
+3 => x"3a0b0b80",
+4 => x"c6d00400",
+5 => x"00000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"80c7972d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
+17 => x"72830609",
+18 => x"81058205",
+19 => x"832b2a83",
+20 => x"ffff0652",
+21 => x"04000000",
+22 => x"00000000",
+23 => x"00000000",
+24 => x"71fd0608",
+25 => x"83ffff73",
+26 => x"83060981",
+27 => x"05820583",
+28 => x"2b2b0906",
+29 => x"7383ffff",
+30 => x"0b0b0b0b",
+31 => x"83a70400",
+32 => x"72098105",
+33 => x"72057373",
+34 => x"09060906",
+35 => x"73097306",
+36 => x"070a8106",
+37 => x"53510400",
+38 => x"00000000",
+39 => x"00000000",
+40 => x"72722473",
+41 => x"732e0753",
+42 => x"51040000",
+43 => x"00000000",
+44 => x"00000000",
+45 => x"00000000",
+46 => x"00000000",
+47 => x"00000000",
+48 => x"71737109",
+49 => x"71068106",
+50 => x"30720a10",
+51 => x"0a720a10",
+52 => x"0a31050a",
+53 => x"81065151",
+54 => x"53510400",
+55 => x"00000000",
+56 => x"72722673",
+57 => x"732e0753",
+58 => x"51040000",
+59 => x"00000000",
+60 => x"00000000",
+61 => x"00000000",
+62 => x"00000000",
+63 => x"00000000",
+64 => x"00000000",
+65 => x"00000000",
+66 => x"00000000",
+67 => x"00000000",
+68 => x"00000000",
+69 => x"00000000",
+70 => x"00000000",
+71 => x"00000000",
+72 => x"0b0b0b88",
+73 => x"c4040000",
+74 => x"00000000",
+75 => x"00000000",
+76 => x"00000000",
+77 => x"00000000",
+78 => x"00000000",
+79 => x"00000000",
+80 => x"720a722b",
+81 => x"0a535104",
+82 => x"00000000",
+83 => x"00000000",
+84 => x"00000000",
+85 => x"00000000",
+86 => x"00000000",
+87 => x"00000000",
+88 => x"72729f06",
+89 => x"0981050b",
+90 => x"0b0b88a7",
+91 => x"05040000",
+92 => x"00000000",
+93 => x"00000000",
+94 => x"00000000",
+95 => x"00000000",
+96 => x"72722aff",
+97 => x"739f062a",
+98 => x"0974090a",
+99 => x"8106ff05",
+100 => x"06075351",
+101 => x"04000000",
+102 => x"00000000",
+103 => x"00000000",
+104 => x"71715351",
+105 => x"020d0406",
+106 => x"73830609",
+107 => x"81058205",
+108 => x"832b0b2b",
+109 => x"0772fc06",
+110 => x"0c515104",
+111 => x"00000000",
+112 => x"72098105",
+113 => x"72050970",
+114 => x"81050906",
+115 => x"0a810653",
+116 => x"51040000",
+117 => x"00000000",
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+2698 => x"00000000",
+2699 => x"00000000",
+2700 => x"00000000",
+2701 => x"00000000",
+2702 => x"00000000",
+2703 => x"00000000",
+2704 => x"00000000",
+2705 => x"00000000",
+2706 => x"00000000",
+2707 => x"00000000",
+2708 => x"00000000",
+2709 => x"00000000",
+2710 => x"00000000",
+2711 => x"00000000",
+2712 => x"00000000",
+2713 => x"00000000",
+2714 => x"00000000",
+2715 => x"00000000",
+2716 => x"00000000",
+2717 => x"00000000",
+2718 => x"00000000",
+2719 => x"00000000",
+2720 => x"00000000",
+2721 => x"00000000",
+2722 => x"00000000",
+2723 => x"00000000",
+2724 => x"00000000",
+2725 => x"00000000",
+2726 => x"00000000",
+2727 => x"00000000",
+2728 => x"00000000",
+2729 => x"00000000",
+2730 => x"00000000",
+2731 => x"00000000",
+2732 => x"00000000",
+2733 => x"00000000",
+2734 => x"00000000",
+2735 => x"00000000",
+2736 => x"00000000",
+2737 => x"00000000",
+2738 => x"00000000",
+2739 => x"00000000",
+2740 => x"00000000",
+2741 => x"00000000",
+2742 => x"00000000",
+2743 => x"00000000",
+2744 => x"00000000",
+2745 => x"00000000",
+2746 => x"00000000",
+2747 => x"00000000",
+2748 => x"00000000",
+2749 => x"00000000",
+2750 => x"00000000",
+2751 => x"00000000",
+2752 => x"00000000",
+2753 => x"00000000",
+2754 => x"00000000",
+2755 => x"00000000",
+2756 => x"00000000",
+2757 => x"00000000",
+2758 => x"00000000",
+2759 => x"00000000",
+2760 => x"00000000",
+2761 => x"00000000",
+2762 => x"00000000",
+2763 => x"00000000",
+2764 => x"00000000",
+2765 => x"00000000",
+2766 => x"00000000",
+2767 => x"00000000",
+2768 => x"00000000",
+2769 => x"00000000",
+2770 => x"00000000",
+2771 => x"00000000",
+2772 => x"00000000",
+2773 => x"00000000",
+2774 => x"00000000",
+2775 => x"00000000",
+2776 => x"00000000",
+2777 => x"00000000",
+2778 => x"00000000",
+2779 => x"00000000",
+2780 => x"00000000",
+2781 => x"00000000",
+2782 => x"00000000",
+2783 => x"00000000",
+2784 => x"00000000",
+2785 => x"00000000",
+2786 => x"00000000",
+2787 => x"00000000",
+2788 => x"00000000",
+2789 => x"ffffffff",
+2790 => x"00000000",
+2791 => x"00020000",
+2792 => x"00000000",
+2793 => x"00000000",
+2794 => x"00002ba0",
+2795 => x"00002ba0",
+2796 => x"00002ba8",
+2797 => x"00002ba8",
+2798 => x"00002bb0",
+2799 => x"00002bb0",
+2800 => x"00002bb8",
+2801 => x"00002bb8",
+2802 => x"00002bc0",
+2803 => x"00002bc0",
+2804 => x"00002bc8",
+2805 => x"00002bc8",
+2806 => x"00002bd0",
+2807 => x"00002bd0",
+2808 => x"00002bd8",
+2809 => x"00002bd8",
+2810 => x"00002be0",
+2811 => x"00002be0",
+2812 => x"00002be8",
+2813 => x"00002be8",
+2814 => x"00002bf0",
+2815 => x"00002bf0",
+2816 => x"00002bf8",
+2817 => x"00002bf8",
+2818 => x"00002c00",
+2819 => x"00002c00",
+2820 => x"00002c08",
+2821 => x"00002c08",
+2822 => x"00002c10",
+2823 => x"00002c10",
+2824 => x"00002c18",
+2825 => x"00002c18",
+2826 => x"00002c20",
+2827 => x"00002c20",
+2828 => x"00002c28",
+2829 => x"00002c28",
+2830 => x"00002c30",
+2831 => x"00002c30",
+2832 => x"00002c38",
+2833 => x"00002c38",
+2834 => x"00002c40",
+2835 => x"00002c40",
+2836 => x"00002c48",
+2837 => x"00002c48",
+2838 => x"00002c50",
+2839 => x"00002c50",
+2840 => x"00002c58",
+2841 => x"00002c58",
+2842 => x"00002c60",
+2843 => x"00002c60",
+2844 => x"00002c68",
+2845 => x"00002c68",
+2846 => x"00002c70",
+2847 => x"00002c70",
+2848 => x"00002c78",
+2849 => x"00002c78",
+2850 => x"00002c80",
+2851 => x"00002c80",
+2852 => x"00002c88",
+2853 => x"00002c88",
+2854 => x"00002c90",
+2855 => x"00002c90",
+2856 => x"00002c98",
+2857 => x"00002c98",
+2858 => x"00002ca0",
+2859 => x"00002ca0",
+2860 => x"00002ca8",
+2861 => x"00002ca8",
+2862 => x"00002cb0",
+2863 => x"00002cb0",
+2864 => x"00002cb8",
+2865 => x"00002cb8",
+2866 => x"00002cc0",
+2867 => x"00002cc0",
+2868 => x"00002cc8",
+2869 => x"00002cc8",
+2870 => x"00002cd0",
+2871 => x"00002cd0",
+2872 => x"00002cd8",
+2873 => x"00002cd8",
+2874 => x"00002ce0",
+2875 => x"00002ce0",
+2876 => x"00002ce8",
+2877 => x"00002ce8",
+2878 => x"00002cf0",
+2879 => x"00002cf0",
+2880 => x"00002cf8",
+2881 => x"00002cf8",
+2882 => x"00002d00",
+2883 => x"00002d00",
+2884 => x"00002d08",
+2885 => x"00002d08",
+2886 => x"00002d10",
+2887 => x"00002d10",
+2888 => x"00002d18",
+2889 => x"00002d18",
+2890 => x"00002d20",
+2891 => x"00002d20",
+2892 => x"00002d28",
+2893 => x"00002d28",
+2894 => x"00002d30",
+2895 => x"00002d30",
+2896 => x"00002d38",
+2897 => x"00002d38",
+2898 => x"00002d40",
+2899 => x"00002d40",
+2900 => x"00002d48",
+2901 => x"00002d48",
+2902 => x"00002d50",
+2903 => x"00002d50",
+2904 => x"00002d58",
+2905 => x"00002d58",
+2906 => x"00002d60",
+2907 => x"00002d60",
+2908 => x"00002d68",
+2909 => x"00002d68",
+2910 => x"00002d70",
+2911 => x"00002d70",
+2912 => x"00002d78",
+2913 => x"00002d78",
+2914 => x"00002d80",
+2915 => x"00002d80",
+2916 => x"00002d88",
+2917 => x"00002d88",
+2918 => x"00002d90",
+2919 => x"00002d90",
+2920 => x"00002d98",
+2921 => x"00002d98",
+2922 => x"00002da0",
+2923 => x"00002da0",
+2924 => x"00002da8",
+2925 => x"00002da8",
+2926 => x"00002db0",
+2927 => x"00002db0",
+2928 => x"00002db8",
+2929 => x"00002db8",
+2930 => x"00002dc0",
+2931 => x"00002dc0",
+2932 => x"00002dc8",
+2933 => x"00002dc8",
+2934 => x"00002dd0",
+2935 => x"00002dd0",
+2936 => x"00002dd8",
+2937 => x"00002dd8",
+2938 => x"00002de0",
+2939 => x"00002de0",
+2940 => x"00002de8",
+2941 => x"00002de8",
+2942 => x"00002df0",
+2943 => x"00002df0",
+2944 => x"00002df8",
+2945 => x"00002df8",
+2946 => x"00002e00",
+2947 => x"00002e00",
+2948 => x"00002e08",
+2949 => x"00002e08",
+2950 => x"00002e10",
+2951 => x"00002e10",
+2952 => x"00002e18",
+2953 => x"00002e18",
+2954 => x"00002e20",
+2955 => x"00002e20",
+2956 => x"00002e28",
+2957 => x"00002e28",
+2958 => x"00002e30",
+2959 => x"00002e30",
+2960 => x"00002e38",
+2961 => x"00002e38",
+2962 => x"00002e40",
+2963 => x"00002e40",
+2964 => x"00002e48",
+2965 => x"00002e48",
+2966 => x"00002e50",
+2967 => x"00002e50",
+2968 => x"00002e58",
+2969 => x"00002e58",
+2970 => x"00002e60",
+2971 => x"00002e60",
+2972 => x"00002e68",
+2973 => x"00002e68",
+2974 => x"00002e70",
+2975 => x"00002e70",
+2976 => x"00002e78",
+2977 => x"00002e78",
+2978 => x"00002e80",
+2979 => x"00002e80",
+2980 => x"00002e88",
+2981 => x"00002e88",
+2982 => x"00002e90",
+2983 => x"00002e90",
+2984 => x"00002e98",
+2985 => x"00002e98",
+2986 => x"00002ea0",
+2987 => x"00002ea0",
+2988 => x"00002ea8",
+2989 => x"00002ea8",
+2990 => x"00002eb0",
+2991 => x"00002eb0",
+2992 => x"00002eb8",
+2993 => x"00002eb8",
+2994 => x"00002ec0",
+2995 => x"00002ec0",
+2996 => x"00002ec8",
+2997 => x"00002ec8",
+2998 => x"00002ed0",
+2999 => x"00002ed0",
+3000 => x"00002ed8",
+3001 => x"00002ed8",
+3002 => x"00002ee0",
+3003 => x"00002ee0",
+3004 => x"00002ee8",
+3005 => x"00002ee8",
+3006 => x"00002ef0",
+3007 => x"00002ef0",
+3008 => x"00002ef8",
+3009 => x"00002ef8",
+3010 => x"00002f00",
+3011 => x"00002f00",
+3012 => x"00002f08",
+3013 => x"00002f08",
+3014 => x"00002f10",
+3015 => x"00002f10",
+3016 => x"00002f18",
+3017 => x"00002f18",
+3018 => x"00002f20",
+3019 => x"00002f20",
+3020 => x"00002f28",
+3021 => x"00002f28",
+3022 => x"00002f30",
+3023 => x"00002f30",
+3024 => x"00002f38",
+3025 => x"00002f38",
+3026 => x"00002f40",
+3027 => x"00002f40",
+3028 => x"00002f48",
+3029 => x"00002f48",
+3030 => x"00002f50",
+3031 => x"00002f50",
+3032 => x"00002f58",
+3033 => x"00002f58",
+3034 => x"00002f60",
+3035 => x"00002f60",
+3036 => x"00002f68",
+3037 => x"00002f68",
+3038 => x"00002f70",
+3039 => x"00002f70",
+3040 => x"00002f78",
+3041 => x"00002f78",
+3042 => x"00002f80",
+3043 => x"00002f80",
+3044 => x"00002f88",
+3045 => x"00002f88",
+3046 => x"00002f90",
+3047 => x"00002f90",
+3048 => x"00002f98",
+3049 => x"00002f98",
+3050 => x"000027b8",
+3051 => x"ffffffff",
+3052 => x"00000000",
+3053 => x"ffffffff",
+3054 => x"00000000",
+	others => x"00000000"
+);
+
+begin
+
+process (clk)
+begin
+	if (clk'event and clk = '1') then
+		if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then
+			report "write collision" severity failure;
+		end if;
+	
+		if (memAWriteEnable = '1') then
+			ram(to_integer(unsigned(memAAddr))) := memAWrite;
+			memARead <= memAWrite;
+		else
+			memARead <= ram(to_integer(unsigned(memAAddr)));
+		end if;
+	end if;
+end process;
+
+process (clk)
+begin
+	if (clk'event and clk = '1') then
+		if (memBWriteEnable = '1') then
+			ram(to_integer(unsigned(memBAddr))) := memBWrite;
+			memBRead <= memBWrite;
+		else
+			memBRead <= ram(to_integer(unsigned(memBAddr)));
+		end if;
+	end if;
+end process;
+
+
+
+
+end dualport_ram_arch;
diff --git a/zpu/hdl/example/interrupt.vhd b/zpu/hdl/example/interrupt.vhd
index ededf85..d2bc709 100644
--- a/zpu/hdl/example/interrupt.vhd
+++ b/zpu/hdl/example/interrupt.vhd
@@ -1,3156 +1,3156 @@
--- ZPU
---
--- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
--- 
--- The FreeBSD license
--- 
--- Redistribution and use in source and binary forms, with or without
--- modification, are permitted provided that the following conditions
--- are met:
--- 
--- 1. Redistributions of source code must retain the above copyright
---    notice, this list of conditions and the following disclaimer.
--- 2. Redistributions in binary form must reproduce the above
---    copyright notice, this list of conditions and the following
---    disclaimer in the documentation and/or other materials
---    provided with the distribution.
--- 
--- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
--- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
--- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
--- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
--- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
--- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
--- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
--- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
--- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
--- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--- 
--- The views and conclusions contained in the software and documentation
--- are those of the authors and should not be interpreted as representing
--- official policies, either expressed or implied, of the ZPU Project.
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-
-library work;
-use work.zpu_config.all;
-use work.zpupkg.all;
-
-entity dualport_ram is
-port (clk : in std_logic;
-	memAWriteEnable : in std_logic;
-	memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
-	memAWrite : in std_logic_vector(wordSize-1 downto 0);
-	memARead : out std_logic_vector(wordSize-1 downto 0);
-	memBWriteEnable : in std_logic;
-	memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
-	memBWrite : in std_logic_vector(wordSize-1 downto 0);
-	memBRead : out std_logic_vector(wordSize-1 downto 0));
-end dualport_ram;
-
-architecture dualport_ram_arch of dualport_ram is
-
-
-type ram_type is array(natural range 0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
-
-shared variable ram : ram_type :=
-(
-0 => x"0b0b0b0b",
-1 => x"82700b0b",
-2 => x"80cfe00c",
-3 => x"3a0b0b80",
-4 => x"c6e00400",
-5 => x"00000000",
-6 => x"00000000",
-7 => x"00000000",
-8 => x"80088408",
-9 => x"88080b0b",
-10 => x"0b8af02d",
-11 => x"880c840c",
-12 => x"800c0400",
-13 => x"00000000",
-14 => x"00000000",
-15 => x"00000000",
-16 => x"71fd0608",
-17 => x"72830609",
-18 => x"81058205",
-19 => x"832b2a83",
-20 => x"ffff0652",
-21 => x"04000000",
-22 => x"00000000",
-23 => x"00000000",
-24 => x"71fd0608",
-25 => x"83ffff73",
-26 => x"83060981",
-27 => x"05820583",
-28 => x"2b2b0906",
-29 => x"7383ffff",
-30 => x"0b0b0b0b",
-31 => x"83a70400",
-32 => x"72098105",
-33 => x"72057373",
-34 => x"09060906",
-35 => x"73097306",
-36 => x"070a8106",
-37 => x"53510400",
-38 => x"00000000",
-39 => x"00000000",
-40 => x"72722473",
-41 => x"732e0753",
-42 => x"51040000",
-43 => x"00000000",
-44 => x"00000000",
-45 => x"00000000",
-46 => x"00000000",
-47 => x"00000000",
-48 => x"71737109",
-49 => x"71068106",
-50 => x"30720a10",
-51 => x"0a720a10",
-52 => x"0a31050a",
-53 => x"81065151",
-54 => x"53510400",
-55 => x"00000000",
-56 => x"72722673",
-57 => x"732e0753",
-58 => x"51040000",
-59 => x"00000000",
-60 => x"00000000",
-61 => x"00000000",
-62 => x"00000000",
-63 => x"00000000",
-64 => x"00000000",
-65 => x"00000000",
-66 => x"00000000",
-67 => x"00000000",
-68 => x"00000000",
-69 => x"00000000",
-70 => x"00000000",
-71 => x"00000000",
-72 => x"0b0b0b88",
-73 => x"c4040000",
-74 => x"00000000",
-75 => x"00000000",
-76 => x"00000000",
-77 => x"00000000",
-78 => x"00000000",
-79 => x"00000000",
-80 => x"720a722b",
-81 => x"0a535104",
-82 => x"00000000",
-83 => x"00000000",
-84 => x"00000000",
-85 => x"00000000",
-86 => x"00000000",
-87 => x"00000000",
-88 => x"72729f06",
-89 => x"0981050b",
-90 => x"0b0b88a7",
-91 => x"05040000",
-92 => x"00000000",
-93 => x"00000000",
-94 => x"00000000",
-95 => x"00000000",
-96 => x"72722aff",
-97 => x"739f062a",
-98 => x"0974090a",
-99 => x"8106ff05",
-100 => x"06075351",
-101 => x"04000000",
-102 => x"00000000",
-103 => x"00000000",
-104 => x"71715351",
-105 => x"020d0406",
-106 => x"73830609",
-107 => x"81058205",
-108 => x"832b0b2b",
-109 => x"0772fc06",
-110 => x"0c515104",
-111 => x"00000000",
-112 => x"72098105",
-113 => x"72050970",
-114 => x"81050906",
-115 => x"0a810653",
-116 => x"51040000",
-117 => x"00000000",
-118 => x"00000000",
-119 => x"00000000",
-120 => x"72098105",
-121 => x"72050970",
-122 => x"81050906",
-123 => x"0a098106",
-124 => x"53510400",
-125 => x"00000000",
-126 => x"00000000",
-127 => x"00000000",
-128 => x"71098105",
-129 => x"52040000",
-130 => x"00000000",
-131 => x"00000000",
-132 => x"00000000",
-133 => x"00000000",
-134 => x"00000000",
-135 => x"00000000",
-136 => x"72720981",
-137 => x"05055351",
-138 => x"04000000",
-139 => x"00000000",
-140 => x"00000000",
-141 => x"00000000",
-142 => x"00000000",
-143 => x"00000000",
-144 => x"72097206",
-145 => x"73730906",
-146 => x"07535104",
-147 => x"00000000",
-148 => x"00000000",
-149 => x"00000000",
-150 => x"00000000",
-151 => x"00000000",
-152 => x"71fc0608",
-153 => x"72830609",
-154 => x"81058305",
-155 => x"1010102a",
-156 => x"81ff0652",
-157 => x"04000000",
-158 => x"00000000",
-159 => x"00000000",
-160 => x"71fc0608",
-161 => x"0b0b80cf",
-162 => x"cc738306",
-163 => x"10100508",
-164 => x"060b0b0b",
-165 => x"88aa0400",
-166 => x"00000000",
-167 => x"00000000",
-168 => x"80088408",
-169 => x"88087575",
-170 => x"0b0b0b8b",
-171 => x"ab2d5050",
-172 => x"80085688",
-173 => x"0c840c80",
-174 => x"0c510400",
-175 => x"00000000",
-176 => x"80088408",
-177 => x"88087575",
-178 => x"0b0b0b8b",
-179 => x"ef2d5050",
-180 => x"80085688",
-181 => x"0c840c80",
-182 => x"0c510400",
-183 => x"00000000",
-184 => x"72097081",
-185 => x"0509060a",
-186 => x"8106ff05",
-187 => x"70547106",
-188 => x"73097274",
-189 => x"05ff0506",
-190 => x"07515151",
-191 => x"04000000",
-192 => x"72097081",
-193 => x"0509060a",
-194 => x"098106ff",
-195 => x"05705471",
-196 => x"06730972",
-197 => x"7405ff05",
-198 => x"06075151",
-199 => x"51040000",
-200 => x"05ff0504",
-201 => x"00000000",
-202 => x"00000000",
-203 => x"00000000",
-204 => x"00000000",
-205 => x"00000000",
-206 => x"00000000",
-207 => x"00000000",
-208 => x"810b0b0b",
-209 => x"80cfdc0c",
-210 => x"51040000",
-211 => x"00000000",
-212 => x"00000000",
-213 => x"00000000",
-214 => x"00000000",
-215 => x"00000000",
-216 => x"71810552",
-217 => x"04000000",
-218 => x"00000000",
-219 => x"00000000",
-220 => x"00000000",
-221 => x"00000000",
-222 => x"00000000",
-223 => x"00000000",
-224 => x"00000000",
-225 => x"00000000",
-226 => x"00000000",
-227 => x"00000000",
-228 => x"00000000",
-229 => x"00000000",
-230 => x"00000000",
-231 => x"00000000",
-232 => x"02840572",
-233 => x"10100552",
-234 => x"04000000",
-235 => x"00000000",
-236 => x"00000000",
-237 => x"00000000",
-238 => x"00000000",
-239 => x"00000000",
-240 => x"00000000",
-241 => x"00000000",
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-2820 => x"00002c08",
-2821 => x"00002c08",
-2822 => x"00002c10",
-2823 => x"00002c10",
-2824 => x"00002c18",
-2825 => x"00002c18",
-2826 => x"00002c20",
-2827 => x"00002c20",
-2828 => x"00002c28",
-2829 => x"00002c28",
-2830 => x"00002c30",
-2831 => x"00002c30",
-2832 => x"00002c38",
-2833 => x"00002c38",
-2834 => x"00002c40",
-2835 => x"00002c40",
-2836 => x"00002c48",
-2837 => x"00002c48",
-2838 => x"00002c50",
-2839 => x"00002c50",
-2840 => x"00002c58",
-2841 => x"00002c58",
-2842 => x"00002c60",
-2843 => x"00002c60",
-2844 => x"00002c68",
-2845 => x"00002c68",
-2846 => x"00002c70",
-2847 => x"00002c70",
-2848 => x"00002c78",
-2849 => x"00002c78",
-2850 => x"00002c80",
-2851 => x"00002c80",
-2852 => x"00002c88",
-2853 => x"00002c88",
-2854 => x"00002c90",
-2855 => x"00002c90",
-2856 => x"00002c98",
-2857 => x"00002c98",
-2858 => x"00002ca0",
-2859 => x"00002ca0",
-2860 => x"00002ca8",
-2861 => x"00002ca8",
-2862 => x"00002cb0",
-2863 => x"00002cb0",
-2864 => x"00002cb8",
-2865 => x"00002cb8",
-2866 => x"00002cc0",
-2867 => x"00002cc0",
-2868 => x"00002cc8",
-2869 => x"00002cc8",
-2870 => x"00002cd0",
-2871 => x"00002cd0",
-2872 => x"00002cd8",
-2873 => x"00002cd8",
-2874 => x"00002ce0",
-2875 => x"00002ce0",
-2876 => x"00002ce8",
-2877 => x"00002ce8",
-2878 => x"00002cf0",
-2879 => x"00002cf0",
-2880 => x"00002cf8",
-2881 => x"00002cf8",
-2882 => x"00002d00",
-2883 => x"00002d00",
-2884 => x"00002d08",
-2885 => x"00002d08",
-2886 => x"00002d10",
-2887 => x"00002d10",
-2888 => x"00002d18",
-2889 => x"00002d18",
-2890 => x"00002d20",
-2891 => x"00002d20",
-2892 => x"00002d28",
-2893 => x"00002d28",
-2894 => x"00002d30",
-2895 => x"00002d30",
-2896 => x"00002d38",
-2897 => x"00002d38",
-2898 => x"00002d40",
-2899 => x"00002d40",
-2900 => x"00002d48",
-2901 => x"00002d48",
-2902 => x"00002d50",
-2903 => x"00002d50",
-2904 => x"00002d58",
-2905 => x"00002d58",
-2906 => x"00002d60",
-2907 => x"00002d60",
-2908 => x"00002d68",
-2909 => x"00002d68",
-2910 => x"00002d70",
-2911 => x"00002d70",
-2912 => x"00002d78",
-2913 => x"00002d78",
-2914 => x"00002d80",
-2915 => x"00002d80",
-2916 => x"00002d88",
-2917 => x"00002d88",
-2918 => x"00002d90",
-2919 => x"00002d90",
-2920 => x"00002d98",
-2921 => x"00002d98",
-2922 => x"00002da0",
-2923 => x"00002da0",
-2924 => x"00002da8",
-2925 => x"00002da8",
-2926 => x"00002db0",
-2927 => x"00002db0",
-2928 => x"00002db8",
-2929 => x"00002db8",
-2930 => x"00002dc0",
-2931 => x"00002dc0",
-2932 => x"00002dc8",
-2933 => x"00002dc8",
-2934 => x"00002dd0",
-2935 => x"00002dd0",
-2936 => x"00002dd8",
-2937 => x"00002dd8",
-2938 => x"00002de0",
-2939 => x"00002de0",
-2940 => x"00002de8",
-2941 => x"00002de8",
-2942 => x"00002df0",
-2943 => x"00002df0",
-2944 => x"00002df8",
-2945 => x"00002df8",
-2946 => x"00002e00",
-2947 => x"00002e00",
-2948 => x"00002e08",
-2949 => x"00002e08",
-2950 => x"00002e10",
-2951 => x"00002e10",
-2952 => x"00002e18",
-2953 => x"00002e18",
-2954 => x"00002e20",
-2955 => x"00002e20",
-2956 => x"00002e28",
-2957 => x"00002e28",
-2958 => x"00002e30",
-2959 => x"00002e30",
-2960 => x"00002e38",
-2961 => x"00002e38",
-2962 => x"00002e40",
-2963 => x"00002e40",
-2964 => x"00002e48",
-2965 => x"00002e48",
-2966 => x"00002e50",
-2967 => x"00002e50",
-2968 => x"00002e58",
-2969 => x"00002e58",
-2970 => x"00002e60",
-2971 => x"00002e60",
-2972 => x"00002e68",
-2973 => x"00002e68",
-2974 => x"00002e70",
-2975 => x"00002e70",
-2976 => x"00002e78",
-2977 => x"00002e78",
-2978 => x"00002e80",
-2979 => x"00002e80",
-2980 => x"00002e88",
-2981 => x"00002e88",
-2982 => x"00002e90",
-2983 => x"00002e90",
-2984 => x"00002e98",
-2985 => x"00002e98",
-2986 => x"00002ea0",
-2987 => x"00002ea0",
-2988 => x"00002ea8",
-2989 => x"00002ea8",
-2990 => x"00002eb0",
-2991 => x"00002eb0",
-2992 => x"00002eb8",
-2993 => x"00002eb8",
-2994 => x"00002ec0",
-2995 => x"00002ec0",
-2996 => x"00002ec8",
-2997 => x"00002ec8",
-2998 => x"00002ed0",
-2999 => x"00002ed0",
-3000 => x"00002ed8",
-3001 => x"00002ed8",
-3002 => x"00002ee0",
-3003 => x"00002ee0",
-3004 => x"00002ee8",
-3005 => x"00002ee8",
-3006 => x"00002ef0",
-3007 => x"00002ef0",
-3008 => x"00002ef8",
-3009 => x"00002ef8",
-3010 => x"00002f00",
-3011 => x"00002f00",
-3012 => x"00002f08",
-3013 => x"00002f08",
-3014 => x"00002f10",
-3015 => x"00002f10",
-3016 => x"00002f18",
-3017 => x"00002f18",
-3018 => x"00002f20",
-3019 => x"00002f20",
-3020 => x"00002f28",
-3021 => x"00002f28",
-3022 => x"00002f30",
-3023 => x"00002f30",
-3024 => x"00002f38",
-3025 => x"00002f38",
-3026 => x"00002f40",
-3027 => x"00002f40",
-3028 => x"00002f48",
-3029 => x"00002f48",
-3030 => x"00002f50",
-3031 => x"00002f50",
-3032 => x"00002f58",
-3033 => x"00002f58",
-3034 => x"00002f60",
-3035 => x"00002f60",
-3036 => x"00002f68",
-3037 => x"00002f68",
-3038 => x"00002f70",
-3039 => x"00002f70",
-3040 => x"00002f78",
-3041 => x"00002f78",
-3042 => x"00002f80",
-3043 => x"00002f80",
-3044 => x"00002f88",
-3045 => x"00002f88",
-3046 => x"00002f90",
-3047 => x"00002f90",
-3048 => x"00002f98",
-3049 => x"00002f98",
-3050 => x"00002fa0",
-3051 => x"00002fa0",
-3052 => x"000027c0",
-3053 => x"ffffffff",
-3054 => x"00000000",
-3055 => x"ffffffff",
-3056 => x"00000000",
-	others => x"00000000"
-);
-
-begin
-
-process (clk)
-begin
-	if (clk'event and clk = '1') then
-		if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then
-			report "write collision" severity failure;
-		end if;
-	
-		if (memAWriteEnable = '1') then
-			ram(to_integer(unsigned(memAAddr))) := memAWrite;
-			memARead <= memAWrite;
-		else
-			memARead <= ram(to_integer(unsigned(memAAddr)));
-		end if;
-	end if;
-end process;
-
-process (clk)
-begin
-	if (clk'event and clk = '1') then
-		if (memBWriteEnable = '1') then
-			ram(to_integer(unsigned(memBAddr))) := memBWrite;
-			memBRead <= memBWrite;
-		else
-			memBRead <= ram(to_integer(unsigned(memBAddr)));
-		end if;
-	end if;
-end process;
-
-
-
-
-end dualport_ram_arch;
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity dualport_ram is
+port (clk : in std_logic;
+	memAWriteEnable : in std_logic;
+	memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+	memAWrite : in std_logic_vector(wordSize-1 downto 0);
+	memARead : out std_logic_vector(wordSize-1 downto 0);
+	memBWriteEnable : in std_logic;
+	memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+	memBWrite : in std_logic_vector(wordSize-1 downto 0);
+	memBRead : out std_logic_vector(wordSize-1 downto 0));
+end dualport_ram;
+
+architecture dualport_ram_arch of dualport_ram is
+
+
+type ram_type is array(natural range 0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
+
+shared variable ram : ram_type :=
+(
+0 => x"0b0b0b0b",
+1 => x"82700b0b",
+2 => x"80cfe00c",
+3 => x"3a0b0b80",
+4 => x"c6e00400",
+5 => x"00000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"0b8af02d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
+17 => x"72830609",
+18 => x"81058205",
+19 => x"832b2a83",
+20 => x"ffff0652",
+21 => x"04000000",
+22 => x"00000000",
+23 => x"00000000",
+24 => x"71fd0608",
+25 => x"83ffff73",
+26 => x"83060981",
+27 => x"05820583",
+28 => x"2b2b0906",
+29 => x"7383ffff",
+30 => x"0b0b0b0b",
+31 => x"83a70400",
+32 => x"72098105",
+33 => x"72057373",
+34 => x"09060906",
+35 => x"73097306",
+36 => x"070a8106",
+37 => x"53510400",
+38 => x"00000000",
+39 => x"00000000",
+40 => x"72722473",
+41 => x"732e0753",
+42 => x"51040000",
+43 => x"00000000",
+44 => x"00000000",
+45 => x"00000000",
+46 => x"00000000",
+47 => x"00000000",
+48 => x"71737109",
+49 => x"71068106",
+50 => x"30720a10",
+51 => x"0a720a10",
+52 => x"0a31050a",
+53 => x"81065151",
+54 => x"53510400",
+55 => x"00000000",
+56 => x"72722673",
+57 => x"732e0753",
+58 => x"51040000",
+59 => x"00000000",
+60 => x"00000000",
+61 => x"00000000",
+62 => x"00000000",
+63 => x"00000000",
+64 => x"00000000",
+65 => x"00000000",
+66 => x"00000000",
+67 => x"00000000",
+68 => x"00000000",
+69 => x"00000000",
+70 => x"00000000",
+71 => x"00000000",
+72 => x"0b0b0b88",
+73 => x"c4040000",
+74 => x"00000000",
+75 => x"00000000",
+76 => x"00000000",
+77 => x"00000000",
+78 => x"00000000",
+79 => x"00000000",
+80 => x"720a722b",
+81 => x"0a535104",
+82 => x"00000000",
+83 => x"00000000",
+84 => x"00000000",
+85 => x"00000000",
+86 => x"00000000",
+87 => x"00000000",
+88 => x"72729f06",
+89 => x"0981050b",
+90 => x"0b0b88a7",
+91 => x"05040000",
+92 => x"00000000",
+93 => x"00000000",
+94 => x"00000000",
+95 => x"00000000",
+96 => x"72722aff",
+97 => x"739f062a",
+98 => x"0974090a",
+99 => x"8106ff05",
+100 => x"06075351",
+101 => x"04000000",
+102 => x"00000000",
+103 => x"00000000",
+104 => x"71715351",
+105 => x"020d0406",
+106 => x"73830609",
+107 => x"81058205",
+108 => x"832b0b2b",
+109 => x"0772fc06",
+110 => x"0c515104",
+111 => x"00000000",
+112 => x"72098105",
+113 => x"72050970",
+114 => x"81050906",
+115 => x"0a810653",
+116 => x"51040000",
+117 => x"00000000",
+118 => x"00000000",
+119 => x"00000000",
+120 => x"72098105",
+121 => x"72050970",
+122 => x"81050906",
+123 => x"0a098106",
+124 => x"53510400",
+125 => x"00000000",
+126 => x"00000000",
+127 => x"00000000",
+128 => x"71098105",
+129 => x"52040000",
+130 => x"00000000",
+131 => x"00000000",
+132 => x"00000000",
+133 => x"00000000",
+134 => x"00000000",
+135 => x"00000000",
+136 => x"72720981",
+137 => x"05055351",
+138 => x"04000000",
+139 => x"00000000",
+140 => x"00000000",
+141 => x"00000000",
+142 => x"00000000",
+143 => x"00000000",
+144 => x"72097206",
+145 => x"73730906",
+146 => x"07535104",
+147 => x"00000000",
+148 => x"00000000",
+149 => x"00000000",
+150 => x"00000000",
+151 => x"00000000",
+152 => x"71fc0608",
+153 => x"72830609",
+154 => x"81058305",
+155 => x"1010102a",
+156 => x"81ff0652",
+157 => x"04000000",
+158 => x"00000000",
+159 => x"00000000",
+160 => x"71fc0608",
+161 => x"0b0b80cf",
+162 => x"cc738306",
+163 => x"10100508",
+164 => x"060b0b0b",
+165 => x"88aa0400",
+166 => x"00000000",
+167 => x"00000000",
+168 => x"80088408",
+169 => x"88087575",
+170 => x"0b0b0b8b",
+171 => x"ab2d5050",
+172 => x"80085688",
+173 => x"0c840c80",
+174 => x"0c510400",
+175 => x"00000000",
+176 => x"80088408",
+177 => x"88087575",
+178 => x"0b0b0b8b",
+179 => x"ef2d5050",
+180 => x"80085688",
+181 => x"0c840c80",
+182 => x"0c510400",
+183 => x"00000000",
+184 => x"72097081",
+185 => x"0509060a",
+186 => x"8106ff05",
+187 => x"70547106",
+188 => x"73097274",
+189 => x"05ff0506",
+190 => x"07515151",
+191 => x"04000000",
+192 => x"72097081",
+193 => x"0509060a",
+194 => x"098106ff",
+195 => x"05705471",
+196 => x"06730972",
+197 => x"7405ff05",
+198 => x"06075151",
+199 => x"51040000",
+200 => x"05ff0504",
+201 => x"00000000",
+202 => x"00000000",
+203 => x"00000000",
+204 => x"00000000",
+205 => x"00000000",
+206 => x"00000000",
+207 => x"00000000",
+208 => x"810b0b0b",
+209 => x"80cfdc0c",
+210 => x"51040000",
+211 => x"00000000",
+212 => x"00000000",
+213 => x"00000000",
+214 => x"00000000",
+215 => x"00000000",
+216 => x"71810552",
+217 => x"04000000",
+218 => x"00000000",
+219 => x"00000000",
+220 => x"00000000",
+221 => x"00000000",
+222 => x"00000000",
+223 => x"00000000",
+224 => x"00000000",
+225 => x"00000000",
+226 => x"00000000",
+227 => x"00000000",
+228 => x"00000000",
+229 => x"00000000",
+230 => x"00000000",
+231 => x"00000000",
+232 => x"02840572",
+233 => x"10100552",
+234 => x"04000000",
+235 => x"00000000",
+236 => x"00000000",
+237 => x"00000000",
+238 => x"00000000",
+239 => x"00000000",
+240 => x"00000000",
+241 => x"00000000",
+242 => x"00000000",
+243 => x"00000000",
+244 => x"00000000",
+245 => x"00000000",
+246 => x"00000000",
+247 => x"00000000",
+248 => x"717105ff",
+249 => x"05715351",
+250 => x"020d0400",
+251 => x"00000000",
+252 => x"00000000",
+253 => x"00000000",
+254 => x"00000000",
+255 => x"00000000",
+256 => x"82c53f80",
+257 => x"c6e63f04",
+258 => x"10101010",
+259 => x"10101010",
+260 => x"10101010",
+261 => x"10101010",
+262 => x"10101010",
+263 => x"10101010",
+264 => x"10101010",
+265 => x"10101053",
+266 => x"51047381",
+267 => x"ff067383",
+268 => x"06098105",
+269 => x"83051010",
+270 => x"102b0772",
+271 => x"fc060c51",
+272 => x"51043c04",
+273 => x"72728072",
+274 => x"8106ff05",
+275 => x"09720605",
+276 => x"71105272",
+277 => x"0a100a53",
+278 => x"72ed3851",
+279 => x"51535104",
+280 => x"fe3d0d0b",
+281 => x"0b80dfc8",
+282 => x"08538413",
+283 => x"0870882a",
+284 => x"70810651",
+285 => x"52527080",
+286 => x"2ef03871",
+287 => x"81ff0680",
+288 => x"0c843d0d",
+289 => x"04ff3d0d",
+290 => x"0b0b80df",
+291 => x"c8085271",
+292 => x"0870882a",
+293 => x"81327081",
+294 => x"06515151",
+295 => x"70f13873",
+296 => x"720c833d",
+297 => x"0d0480cf",
+298 => x"dc08802e",
+299 => x"a43880cf",
+300 => x"e008822e",
+301 => x"bd388380",
+302 => x"800b0b0b",
+303 => x"80dfc80c",
+304 => x"82a0800b",
+305 => x"80dfcc0c",
+306 => x"8290800b",
+307 => x"80dfd00c",
+308 => x"04f88080",
+309 => x"80a40b0b",
+310 => x"0b80dfc8",
+311 => x"0cf88080",
+312 => x"82800b80",
+313 => x"dfcc0cf8",
+314 => x"80808480",
+315 => x"0b80dfd0",
+316 => x"0c0480c0",
+317 => x"a8808c0b",
+318 => x"0b0b80df",
+319 => x"c80c80c0",
+320 => x"a880940b",
+321 => x"80dfcc0c",
+322 => x"0b0b80cf",
+323 => x"980b80df",
+324 => x"d00c0470",
+325 => x"7080dfd4",
+326 => x"335170a7",
+327 => x"3880cfe8",
+328 => x"08700852",
+329 => x"5270802e",
+330 => x"94388412",
+331 => x"80cfe80c",
+332 => x"702d80cf",
+333 => x"e8087008",
+334 => x"525270ee",
+335 => x"38810b80",
+336 => x"dfd43450",
+337 => x"50040470",
+338 => x"0b0b80df",
+339 => x"c408802e",
+340 => x"8e380b0b",
+341 => x"0b0b800b",
+342 => x"802e0981",
+343 => x"06833850",
+344 => x"040b0b80",
+345 => x"dfc4510b",
+346 => x"0b0bf594",
+347 => x"3f500404",
+348 => x"803d0d80",
+349 => x"dfe00881",
+350 => x"1180dfe0",
+351 => x"0c51823d",
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+2920 => x"00002d98",
+2921 => x"00002d98",
+2922 => x"00002da0",
+2923 => x"00002da0",
+2924 => x"00002da8",
+2925 => x"00002da8",
+2926 => x"00002db0",
+2927 => x"00002db0",
+2928 => x"00002db8",
+2929 => x"00002db8",
+2930 => x"00002dc0",
+2931 => x"00002dc0",
+2932 => x"00002dc8",
+2933 => x"00002dc8",
+2934 => x"00002dd0",
+2935 => x"00002dd0",
+2936 => x"00002dd8",
+2937 => x"00002dd8",
+2938 => x"00002de0",
+2939 => x"00002de0",
+2940 => x"00002de8",
+2941 => x"00002de8",
+2942 => x"00002df0",
+2943 => x"00002df0",
+2944 => x"00002df8",
+2945 => x"00002df8",
+2946 => x"00002e00",
+2947 => x"00002e00",
+2948 => x"00002e08",
+2949 => x"00002e08",
+2950 => x"00002e10",
+2951 => x"00002e10",
+2952 => x"00002e18",
+2953 => x"00002e18",
+2954 => x"00002e20",
+2955 => x"00002e20",
+2956 => x"00002e28",
+2957 => x"00002e28",
+2958 => x"00002e30",
+2959 => x"00002e30",
+2960 => x"00002e38",
+2961 => x"00002e38",
+2962 => x"00002e40",
+2963 => x"00002e40",
+2964 => x"00002e48",
+2965 => x"00002e48",
+2966 => x"00002e50",
+2967 => x"00002e50",
+2968 => x"00002e58",
+2969 => x"00002e58",
+2970 => x"00002e60",
+2971 => x"00002e60",
+2972 => x"00002e68",
+2973 => x"00002e68",
+2974 => x"00002e70",
+2975 => x"00002e70",
+2976 => x"00002e78",
+2977 => x"00002e78",
+2978 => x"00002e80",
+2979 => x"00002e80",
+2980 => x"00002e88",
+2981 => x"00002e88",
+2982 => x"00002e90",
+2983 => x"00002e90",
+2984 => x"00002e98",
+2985 => x"00002e98",
+2986 => x"00002ea0",
+2987 => x"00002ea0",
+2988 => x"00002ea8",
+2989 => x"00002ea8",
+2990 => x"00002eb0",
+2991 => x"00002eb0",
+2992 => x"00002eb8",
+2993 => x"00002eb8",
+2994 => x"00002ec0",
+2995 => x"00002ec0",
+2996 => x"00002ec8",
+2997 => x"00002ec8",
+2998 => x"00002ed0",
+2999 => x"00002ed0",
+3000 => x"00002ed8",
+3001 => x"00002ed8",
+3002 => x"00002ee0",
+3003 => x"00002ee0",
+3004 => x"00002ee8",
+3005 => x"00002ee8",
+3006 => x"00002ef0",
+3007 => x"00002ef0",
+3008 => x"00002ef8",
+3009 => x"00002ef8",
+3010 => x"00002f00",
+3011 => x"00002f00",
+3012 => x"00002f08",
+3013 => x"00002f08",
+3014 => x"00002f10",
+3015 => x"00002f10",
+3016 => x"00002f18",
+3017 => x"00002f18",
+3018 => x"00002f20",
+3019 => x"00002f20",
+3020 => x"00002f28",
+3021 => x"00002f28",
+3022 => x"00002f30",
+3023 => x"00002f30",
+3024 => x"00002f38",
+3025 => x"00002f38",
+3026 => x"00002f40",
+3027 => x"00002f40",
+3028 => x"00002f48",
+3029 => x"00002f48",
+3030 => x"00002f50",
+3031 => x"00002f50",
+3032 => x"00002f58",
+3033 => x"00002f58",
+3034 => x"00002f60",
+3035 => x"00002f60",
+3036 => x"00002f68",
+3037 => x"00002f68",
+3038 => x"00002f70",
+3039 => x"00002f70",
+3040 => x"00002f78",
+3041 => x"00002f78",
+3042 => x"00002f80",
+3043 => x"00002f80",
+3044 => x"00002f88",
+3045 => x"00002f88",
+3046 => x"00002f90",
+3047 => x"00002f90",
+3048 => x"00002f98",
+3049 => x"00002f98",
+3050 => x"00002fa0",
+3051 => x"00002fa0",
+3052 => x"000027c0",
+3053 => x"ffffffff",
+3054 => x"00000000",
+3055 => x"ffffffff",
+3056 => x"00000000",
+	others => x"00000000"
+);
+
+begin
+
+process (clk)
+begin
+	if (clk'event and clk = '1') then
+		if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then
+			report "write collision" severity failure;
+		end if;
+	
+		if (memAWriteEnable = '1') then
+			ram(to_integer(unsigned(memAAddr))) := memAWrite;
+			memARead <= memAWrite;
+		else
+			memARead <= ram(to_integer(unsigned(memAAddr)));
+		end if;
+	end if;
+end process;
+
+process (clk)
+begin
+	if (clk'event and clk = '1') then
+		if (memBWriteEnable = '1') then
+			ram(to_integer(unsigned(memBAddr))) := memBWrite;
+			memBRead <= memBWrite;
+		else
+			memBRead <= ram(to_integer(unsigned(memBAddr)));
+		end if;
+	end if;
+end process;
+
+
+
+
+end dualport_ram_arch;
diff --git a/zpu/hdl/example/sim_small_fpga_top.vhd b/zpu/hdl/example/sim_small_fpga_top.vhd
index f36a285..e671460 100644
--- a/zpu/hdl/example/sim_small_fpga_top.vhd
+++ b/zpu/hdl/example/sim_small_fpga_top.vhd
@@ -1,207 +1,207 @@
--- ZPU
---
--- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
--- 
--- The FreeBSD license
--- 
--- Redistribution and use in source and binary forms, with or without
--- modification, are permitted provided that the following conditions
--- are met:
--- 
--- 1. Redistributions of source code must retain the above copyright
---    notice, this list of conditions and the following disclaimer.
--- 2. Redistributions in binary form must reproduce the above
---    copyright notice, this list of conditions and the following
---    disclaimer in the documentation and/or other materials
---    provided with the distribution.
--- 
--- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
--- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
--- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
--- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
--- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
--- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
--- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
--- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
--- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
--- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--- 
--- The views and conclusions contained in the software and documentation
--- are those of the authors and should not be interpreted as representing
--- official policies, either expressed or implied, of the ZPU Project.--------------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use ieee.numeric_std.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-library work;
-use work.zpu_config.all;
-use work.zpupkg.all;
-
-entity fpga_top is
-end fpga_top;
-
-architecture behave of fpga_top is
-
-
-signal clk : std_logic;
-
-signal	areset			: std_logic := '1';
-
-
-component  zpu_io is
-  generic (
-           log_file:       string  := "log.txt"
-          );
-  port(
-       	clk         : in std_logic;
-       	areset        : in std_logic;
-		busy : out std_logic;
-		writeEnable : in std_logic;
-		readEnable : in std_logic;
-		write	: in std_logic_vector(wordSize-1 downto 0);
-		read	: out std_logic_vector(wordSize-1 downto 0);
-		addr : in std_logic_vector(maxAddrBit downto minAddrBit)
-		);
-end component;
-
-
-
-
-
-signal			  mem_busy : std_logic;
-signal			  mem_read : std_logic_vector(wordSize-1 downto 0);
-signal			  mem_write : std_logic_vector(wordSize-1 downto 0);
-signal			  mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);
-signal			  mem_writeEnable : std_logic; 
-signal			  mem_readEnable : std_logic;
-signal			  mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
-
-signal			  enable : std_logic;
-
-signal			  dram_mem_busy : std_logic;
-signal			  dram_mem_read : std_logic_vector(wordSize-1 downto 0);
-signal			  dram_mem_write : std_logic_vector(wordSize-1 downto 0);
-signal			  dram_mem_writeEnable : std_logic; 
-signal			  dram_mem_readEnable : std_logic;
-signal			  dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
-
-
-signal	 		  io_busy : std_logic;
-
-signal			  io_mem_read : std_logic_vector(wordSize-1 downto 0);
-signal			  io_mem_writeEnable : std_logic; 
-signal			  io_mem_readEnable : std_logic;
-
-
-signal			  dram_ready : std_logic;
-signal			  io_ready : std_logic;
-signal			  io_reading : std_logic;
-signal			  interruptcounter : unsigned(15 downto 0);
-signal			  interrupt : std_logic;
-
-
-
-signal break : std_logic;
-
-begin
-
-	zpu: zpu_core port map (
-		clk => clk ,
-	 	areset => areset,
-	 	enable => enable,
- 		in_mem_busy => mem_busy, 
- 		mem_read => mem_read,
- 		mem_write => mem_write, 
-		out_mem_addr => mem_addr, 
-		out_mem_writeEnable => mem_writeEnable,  
-		out_mem_readEnable => mem_readEnable,
- 		mem_writeMask => mem_writeMask, 
- 		interrupt => interrupt,
- 		break  => break);
-
-
-	ioMap: zpu_io port map (
-       	clk => clk,
-	 	areset => areset,
-		busy => io_busy,
-		writeEnable => io_mem_writeEnable,
-		readEnable => io_mem_readEnable,
-		write	=> mem_write,
-		read	=> io_mem_read,
-		addr => mem_addr(maxAddrBit downto minAddrBit)
-	);
-
-	dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit);
-	dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit);
-	io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit);
-	io_mem_readEnable <= mem_readEnable and mem_addr(ioBit);
-	mem_busy <= io_busy;
-	
-	
-
-	-- Memory reads either come from IO or DRAM. We need to pick the right one.
-	memorycontrol:
-	process(dram_mem_read, dram_ready, io_ready, io_mem_read)
-	begin
-		mem_read <= (others => 'U');
-		if dram_ready='1' then
-			mem_read <= dram_mem_read;
-		end if;
-			 
-		if io_ready='1' then
-			mem_read <= (others => '0');
-			mem_read <= io_mem_read;
-		end if;
-	end process;
-
-
-	
-	io_ready <= (io_reading or io_mem_readEnable) and not io_busy;
-
-	memoryControlSync:
-	process(clk, areset)
-	begin
-		if areset = '1' then
-			enable <= '0';
-			io_reading <= '0';
-			dram_ready <= '0';
-			
-		    interruptcounter <= to_unsigned(0, 16);
-			interrupt <= '0'; 
-		    
-		elsif (clk'event and clk = '1') then
-			enable <= '1';
-			io_reading <= io_busy or io_mem_readEnable; 
-			dram_ready<=dram_mem_readEnable;
-			
-			-- keep interrupt signal high for 16 cycles
-		    interruptcounter <= interruptcounter + 1;
-			if (interruptcounter < 16) then
-  				report "Interrupt asserted!" severity note;
-				interrupt <='1';
-			else
-				interrupt <='0';
-			end if;
-		end if;
-	end process;
-
-	-- wiggle the clock @ 100MHz
-	clock : PROCESS
-	   begin
-   			clk <= '0';
-		   wait for 5 ns; 
-   			clk <= '1';
-		   wait for 5 ns; 
-		   areset <= '0';
-	end PROCESS clock;
-
-
-end behave;
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.--------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity fpga_top is
+end fpga_top;
+
+architecture behave of fpga_top is
+
+
+signal clk : std_logic;
+
+signal	areset			: std_logic := '1';
+
+
+component  zpu_io is
+  generic (
+           log_file:       string  := "log.txt"
+          );
+  port(
+       	clk         : in std_logic;
+       	areset        : in std_logic;
+		busy : out std_logic;
+		writeEnable : in std_logic;
+		readEnable : in std_logic;
+		write	: in std_logic_vector(wordSize-1 downto 0);
+		read	: out std_logic_vector(wordSize-1 downto 0);
+		addr : in std_logic_vector(maxAddrBit downto minAddrBit)
+		);
+end component;
+
+
+
+
+
+signal			  mem_busy : std_logic;
+signal			  mem_read : std_logic_vector(wordSize-1 downto 0);
+signal			  mem_write : std_logic_vector(wordSize-1 downto 0);
+signal			  mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);
+signal			  mem_writeEnable : std_logic; 
+signal			  mem_readEnable : std_logic;
+signal			  mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
+
+signal			  enable : std_logic;
+
+signal			  dram_mem_busy : std_logic;
+signal			  dram_mem_read : std_logic_vector(wordSize-1 downto 0);
+signal			  dram_mem_write : std_logic_vector(wordSize-1 downto 0);
+signal			  dram_mem_writeEnable : std_logic; 
+signal			  dram_mem_readEnable : std_logic;
+signal			  dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
+
+
+signal	 		  io_busy : std_logic;
+
+signal			  io_mem_read : std_logic_vector(wordSize-1 downto 0);
+signal			  io_mem_writeEnable : std_logic; 
+signal			  io_mem_readEnable : std_logic;
+
+
+signal			  dram_ready : std_logic;
+signal			  io_ready : std_logic;
+signal			  io_reading : std_logic;
+signal			  interruptcounter : unsigned(15 downto 0);
+signal			  interrupt : std_logic;
+
+
+
+signal break : std_logic;
+
+begin
+
+	zpu: zpu_core port map (
+		clk => clk ,
+	 	areset => areset,
+	 	enable => enable,
+ 		in_mem_busy => mem_busy, 
+ 		mem_read => mem_read,
+ 		mem_write => mem_write, 
+		out_mem_addr => mem_addr, 
+		out_mem_writeEnable => mem_writeEnable,  
+		out_mem_readEnable => mem_readEnable,
+ 		mem_writeMask => mem_writeMask, 
+ 		interrupt => interrupt,
+ 		break  => break);
+
+
+	ioMap: zpu_io port map (
+       	clk => clk,
+	 	areset => areset,
+		busy => io_busy,
+		writeEnable => io_mem_writeEnable,
+		readEnable => io_mem_readEnable,
+		write	=> mem_write,
+		read	=> io_mem_read,
+		addr => mem_addr(maxAddrBit downto minAddrBit)
+	);
+
+	dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit);
+	dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit);
+	io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit);
+	io_mem_readEnable <= mem_readEnable and mem_addr(ioBit);
+	mem_busy <= io_busy;
+	
+	
+
+	-- Memory reads either come from IO or DRAM. We need to pick the right one.
+	memorycontrol:
+	process(dram_mem_read, dram_ready, io_ready, io_mem_read)
+	begin
+		mem_read <= (others => 'U');
+		if dram_ready='1' then
+			mem_read <= dram_mem_read;
+		end if;
+			 
+		if io_ready='1' then
+			mem_read <= (others => '0');
+			mem_read <= io_mem_read;
+		end if;
+	end process;
+
+
+	
+	io_ready <= (io_reading or io_mem_readEnable) and not io_busy;
+
+	memoryControlSync:
+	process(clk, areset)
+	begin
+		if areset = '1' then
+			enable <= '0';
+			io_reading <= '0';
+			dram_ready <= '0';
+			
+		    interruptcounter <= to_unsigned(0, 16);
+			interrupt <= '0'; 
+		    
+		elsif (clk'event and clk = '1') then
+			enable <= '1';
+			io_reading <= io_busy or io_mem_readEnable; 
+			dram_ready<=dram_mem_readEnable;
+			
+			-- keep interrupt signal high for 16 cycles
+		    interruptcounter <= interruptcounter + 1;
+			if (interruptcounter < 16) then
+  				report "Interrupt asserted!" severity note;
+				interrupt <='1';
+			else
+				interrupt <='0';
+			end if;
+		end if;
+	end process;
+
+	-- wiggle the clock @ 100MHz
+	clock : PROCESS
+	   begin
+   			clk <= '0';
+		   wait for 5 ns; 
+   			clk <= '1';
+		   wait for 5 ns; 
+		   areset <= '0';
+	end PROCESS clock;
+
+
+end behave;
diff --git a/zpu/hdl/example/sim_small_fpga_top_noint.vhd b/zpu/hdl/example/sim_small_fpga_top_noint.vhd
index b342d26..0edb8c7 100644
--- a/zpu/hdl/example/sim_small_fpga_top_noint.vhd
+++ b/zpu/hdl/example/sim_small_fpga_top_noint.vhd
@@ -1,193 +1,193 @@
--- ZPU
---
--- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
--- 
--- The FreeBSD license
--- 
--- Redistribution and use in source and binary forms, with or without
--- modification, are permitted provided that the following conditions
--- are met:
--- 
--- 1. Redistributions of source code must retain the above copyright
---    notice, this list of conditions and the following disclaimer.
--- 2. Redistributions in binary form must reproduce the above
---    copyright notice, this list of conditions and the following
---    disclaimer in the documentation and/or other materials
---    provided with the distribution.
--- 
--- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
--- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
--- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
--- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
--- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
--- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
--- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
--- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
--- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
--- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--- 
--- The views and conclusions contained in the software and documentation
--- are those of the authors and should not be interpreted as representing
--- official policies, either expressed or implied, of the ZPU Project.
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use ieee.numeric_std.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-library work;
-use work.zpu_config.all;
-use work.zpupkg.all;
-
-entity fpga_top is
-end fpga_top;
-
-architecture behave of fpga_top is
-
-
-signal clk : std_logic;
-
-signal	areset			: std_logic := '1';
-
-
-component  zpu_io is
-  generic (
-           log_file:       string  := "log.txt"
-          );
-  port(
-       	clk         : in std_logic;
-       	areset        : in std_logic;
-		busy : out std_logic;
-		writeEnable : in std_logic;
-		readEnable : in std_logic;
-		write	: in std_logic_vector(wordSize-1 downto 0);
-		read	: out std_logic_vector(wordSize-1 downto 0);
-		addr : in std_logic_vector(maxAddrBit downto minAddrBit)
-		);
-end component;
-
-
-
-
-
-signal			  mem_busy : std_logic;
-signal			  mem_read : std_logic_vector(wordSize-1 downto 0);
-signal			  mem_write : std_logic_vector(wordSize-1 downto 0);
-signal			  mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);
-signal			  mem_writeEnable : std_logic; 
-signal			  mem_readEnable : std_logic;
-signal			  mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
-
-signal			  enable : std_logic;
-
-signal			  dram_mem_busy : std_logic;
-signal			  dram_mem_read : std_logic_vector(wordSize-1 downto 0);
-signal			  dram_mem_write : std_logic_vector(wordSize-1 downto 0);
-signal			  dram_mem_writeEnable : std_logic; 
-signal			  dram_mem_readEnable : std_logic;
-signal			  dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
-
-
-signal	 		  io_busy : std_logic;
-
-signal			  io_mem_read : std_logic_vector(wordSize-1 downto 0);
-signal			  io_mem_writeEnable : std_logic; 
-signal			  io_mem_readEnable : std_logic;
-
-
-signal			  dram_ready : std_logic;
-signal			  io_ready : std_logic;
-signal			  io_reading : std_logic;
-
-
-
-signal break : std_logic;
-
-begin
-
-	zpu: zpu_core port map (
-		clk => clk ,
-	 	areset => areset,
-	 	enable => enable,
- 		in_mem_busy => mem_busy, 
- 		mem_read => mem_read,
- 		mem_write => mem_write, 
-		out_mem_addr => mem_addr, 
-		out_mem_writeEnable => mem_writeEnable,  
-		out_mem_readEnable => mem_readEnable,
- 		mem_writeMask => mem_writeMask, 
- 		interrupt => '0',
- 		break  => break);
-
-
-	ioMap: zpu_io port map (
-       	clk => clk,
-	 	areset => areset,
-		busy => io_busy,
-		writeEnable => io_mem_writeEnable,
-		readEnable => io_mem_readEnable,
-		write	=> mem_write,
-		read	=> io_mem_read,
-		addr => mem_addr(maxAddrBit downto minAddrBit)
-	);
-
-	dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit);
-	dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit);
-	io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit);
-	io_mem_readEnable <= mem_readEnable and mem_addr(ioBit);
-	mem_busy <= io_busy;
-	
-	
-
-	-- Memory reads either come from IO or DRAM. We need to pick the right one.
-	memorycontrol:
-	process(dram_mem_read, dram_ready, io_ready, io_mem_read)
-	begin
-		mem_read <= (others => 'U');
-		if dram_ready='1' then
-			mem_read <= dram_mem_read;
-		end if;
-			 
-		if io_ready='1' then
-			mem_read <= (others => '0');
-			mem_read <= io_mem_read;
-		end if;
-	end process;
-
-
-	
-	io_ready <= (io_reading or io_mem_readEnable) and not io_busy;
-
-	memoryControlSync:
-	process(clk, areset)
-	begin
-		if areset = '1' then
-			enable <= '0';
-			io_reading <= '0';
-			dram_ready <= '0';
-			
-		elsif (clk'event and clk = '1') then
-			enable <= '1';
-			io_reading <= io_busy or io_mem_readEnable; 
-			dram_ready<=dram_mem_readEnable;
-		end if;
-	end process;
-
-	-- wiggle the clock @ 100MHz
-	clock : PROCESS
-	   begin
-   			clk <= '0';
-		   wait for 5 ns; 
-   			clk <= '1';
-		   wait for 5 ns; 
-		   areset <= '0';
-	end PROCESS clock;
-
-
-end behave;
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity fpga_top is
+end fpga_top;
+
+architecture behave of fpga_top is
+
+
+signal clk : std_logic;
+
+signal	areset			: std_logic := '1';
+
+
+component  zpu_io is
+  generic (
+           log_file:       string  := "log.txt"
+          );
+  port(
+       	clk         : in std_logic;
+       	areset        : in std_logic;
+		busy : out std_logic;
+		writeEnable : in std_logic;
+		readEnable : in std_logic;
+		write	: in std_logic_vector(wordSize-1 downto 0);
+		read	: out std_logic_vector(wordSize-1 downto 0);
+		addr : in std_logic_vector(maxAddrBit downto minAddrBit)
+		);
+end component;
+
+
+
+
+
+signal			  mem_busy : std_logic;
+signal			  mem_read : std_logic_vector(wordSize-1 downto 0);
+signal			  mem_write : std_logic_vector(wordSize-1 downto 0);
+signal			  mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);
+signal			  mem_writeEnable : std_logic; 
+signal			  mem_readEnable : std_logic;
+signal			  mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
+
+signal			  enable : std_logic;
+
+signal			  dram_mem_busy : std_logic;
+signal			  dram_mem_read : std_logic_vector(wordSize-1 downto 0);
+signal			  dram_mem_write : std_logic_vector(wordSize-1 downto 0);
+signal			  dram_mem_writeEnable : std_logic; 
+signal			  dram_mem_readEnable : std_logic;
+signal			  dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
+
+
+signal	 		  io_busy : std_logic;
+
+signal			  io_mem_read : std_logic_vector(wordSize-1 downto 0);
+signal			  io_mem_writeEnable : std_logic; 
+signal			  io_mem_readEnable : std_logic;
+
+
+signal			  dram_ready : std_logic;
+signal			  io_ready : std_logic;
+signal			  io_reading : std_logic;
+
+
+
+signal break : std_logic;
+
+begin
+
+	zpu: zpu_core port map (
+		clk => clk ,
+	 	areset => areset,
+	 	enable => enable,
+ 		in_mem_busy => mem_busy, 
+ 		mem_read => mem_read,
+ 		mem_write => mem_write, 
+		out_mem_addr => mem_addr, 
+		out_mem_writeEnable => mem_writeEnable,  
+		out_mem_readEnable => mem_readEnable,
+ 		mem_writeMask => mem_writeMask, 
+ 		interrupt => '0',
+ 		break  => break);
+
+
+	ioMap: zpu_io port map (
+       	clk => clk,
+	 	areset => areset,
+		busy => io_busy,
+		writeEnable => io_mem_writeEnable,
+		readEnable => io_mem_readEnable,
+		write	=> mem_write,
+		read	=> io_mem_read,
+		addr => mem_addr(maxAddrBit downto minAddrBit)
+	);
+
+	dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit);
+	dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit);
+	io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit);
+	io_mem_readEnable <= mem_readEnable and mem_addr(ioBit);
+	mem_busy <= io_busy;
+	
+	
+
+	-- Memory reads either come from IO or DRAM. We need to pick the right one.
+	memorycontrol:
+	process(dram_mem_read, dram_ready, io_ready, io_mem_read)
+	begin
+		mem_read <= (others => 'U');
+		if dram_ready='1' then
+			mem_read <= dram_mem_read;
+		end if;
+			 
+		if io_ready='1' then
+			mem_read <= (others => '0');
+			mem_read <= io_mem_read;
+		end if;
+	end process;
+
+
+	
+	io_ready <= (io_reading or io_mem_readEnable) and not io_busy;
+
+	memoryControlSync:
+	process(clk, areset)
+	begin
+		if areset = '1' then
+			enable <= '0';
+			io_reading <= '0';
+			dram_ready <= '0';
+			
+		elsif (clk'event and clk = '1') then
+			enable <= '1';
+			io_reading <= io_busy or io_mem_readEnable; 
+			dram_ready<=dram_mem_readEnable;
+		end if;
+	end process;
+
+	-- wiggle the clock @ 100MHz
+	clock : PROCESS
+	   begin
+   			clk <= '0';
+		   wait for 5 ns; 
+   			clk <= '1';
+		   wait for 5 ns; 
+		   areset <= '0';
+	end PROCESS clock;
+
+
+end behave;
diff --git a/zpu/hdl/example/zpu_config.vhd b/zpu/hdl/example/zpu_config.vhd
index c4c09b5..c3c60c1 100644
--- a/zpu/hdl/example/zpu_config.vhd
+++ b/zpu/hdl/example/zpu_config.vhd
@@ -1,56 +1,56 @@
--- ZPU
---
--- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
--- 
--- The FreeBSD license
--- 
--- Redistribution and use in source and binary forms, with or without
--- modification, are permitted provided that the following conditions
--- are met:
--- 
--- 1. Redistributions of source code must retain the above copyright
---    notice, this list of conditions and the following disclaimer.
--- 2. Redistributions in binary form must reproduce the above
---    copyright notice, this list of conditions and the following
---    disclaimer in the documentation and/or other materials
---    provided with the distribution.
--- 
--- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
--- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
--- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
--- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
--- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
--- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
--- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
--- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
--- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
--- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--- 
--- The views and conclusions contained in the software and documentation
--- are those of the authors and should not be interpreted as representing
--- official policies, either expressed or implied, of the ZPU Project.
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.std_logic_arith.all;
-
-package zpu_config is
-	-- generate trace output
-	constant	Generate_Trace		: boolean := true;
-	constant 	wordPower			: integer := 5;
-	-- during simulation, set this to '0' to get matching trace.txt 
-	constant	DontCareValue		: std_logic := '0';
-	-- Clock frequency in MHz.
-	constant	ZPU_Frequency		: std_logic_vector(7 downto 0) := x"64";
-	-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
-	constant 	maxAddrBitIncIO		: integer := 27;
-	constant 	maxAddrBitBRAM		: integer := 16;
-		
-	-- start byte address of stack. 
-	-- point to top of RAM - 2*words
-	constant 	spStart				: std_logic_vector(maxAddrBitIncIO downto 0) :=
-					conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1);
-end zpu_config;
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+
+package zpu_config is
+	-- generate trace output
+	constant	Generate_Trace		: boolean := true;
+	constant 	wordPower			: integer := 5;
+	-- during simulation, set this to '0' to get matching trace.txt 
+	constant	DontCareValue		: std_logic := '0';
+	-- Clock frequency in MHz.
+	constant	ZPU_Frequency		: std_logic_vector(7 downto 0) := x"64";
+	-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
+	constant 	maxAddrBitIncIO		: integer := 27;
+	constant 	maxAddrBitBRAM		: integer := 16;
+		
+	-- start byte address of stack. 
+	-- point to top of RAM - 2*words
+	constant 	spStart				: std_logic_vector(maxAddrBitIncIO downto 0) :=
+					conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1);
+end zpu_config;
diff --git a/zpu/hdl/example_medium/dram_dmips.vhd b/zpu/hdl/example_medium/dram_dmips.vhd
index a9fd59e..0437adc 100644
--- a/zpu/hdl/example_medium/dram_dmips.vhd
+++ b/zpu/hdl/example_medium/dram_dmips.vhd
@@ -1,3308 +1,3308 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-
-library work;
-use work.zpu_config.all;
-use work.zpupkg.all;
-
-entity dram is
-port (clk : in std_logic;
-areset : std_logic;
-		mem_writeEnable : in std_logic;
-		mem_readEnable : in std_logic;
-		mem_addr : in std_logic_vector(maxAddrBit downto 0);
-		mem_write : in std_logic_vector(wordSize-1 downto 0);
-		mem_read : out std_logic_vector(wordSize-1 downto 0);
-		mem_busy : out std_logic;
-		mem_writeMask : in std_logic_vector(wordBytes-1 downto 0));
-end dram;
-
-architecture dram_arch of dram is
-
-
-type ram_type is array(natural range 0 to ((2**(maxAddrBitDRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
-
-shared variable ram : ram_type :=
-(
-0 => x"0b0b0b0b",
-1 => x"82700b0b",
-2 => x"80d5f40c",
-3 => x"3a0b0b80",
-4 => x"c4fb0400",
-5 => x"00000000",
-6 => x"00000000",
-7 => x"00000000",
-8 => x"80088408",
-9 => x"88080b0b",
-10 => x"80c5c22d",
-11 => x"880c840c",
-12 => x"800c0400",
-13 => x"00000000",
-14 => x"00000000",
-15 => x"00000000",
-16 => x"71fd0608",
-17 => x"72830609",
-18 => x"81058205",
-19 => x"832b2a83",
-20 => x"ffff0652",
-21 => x"04000000",
-22 => x"00000000",
-23 => x"00000000",
-24 => x"71fd0608",
-25 => x"83ffff73",
-26 => x"83060981",
-27 => x"05820583",
-28 => x"2b2b0906",
-29 => x"7383ffff",
-30 => x"0b0b0b0b",
-31 => x"83a70400",
-32 => x"72098105",
-33 => x"72057373",
-34 => x"09060906",
-35 => x"73097306",
-36 => x"070a8106",
-37 => x"53510400",
-38 => x"00000000",
-39 => x"00000000",
-40 => x"72722473",
-41 => x"732e0753",
-42 => x"51040000",
-43 => x"00000000",
-44 => x"00000000",
-45 => x"00000000",
-46 => x"00000000",
-47 => x"00000000",
-48 => x"71737109",
-49 => x"71068106",
-50 => x"30720a10",
-51 => x"0a720a10",
-52 => x"0a31050a",
-53 => x"81065151",
-54 => x"53510400",
-55 => x"00000000",
-56 => x"72722673",
-57 => x"732e0753",
-58 => x"51040000",
-59 => x"00000000",
-60 => x"00000000",
-61 => x"00000000",
-62 => x"00000000",
-63 => x"00000000",
-64 => x"00000000",
-65 => x"00000000",
-66 => x"00000000",
-67 => x"00000000",
-68 => x"00000000",
-69 => x"00000000",
-70 => x"00000000",
-71 => x"00000000",
-72 => x"0b0b0b88",
-73 => x"c3040000",
-74 => x"00000000",
-75 => x"00000000",
-76 => x"00000000",
-77 => x"00000000",
-78 => x"00000000",
-79 => x"00000000",
-80 => x"720a722b",
-81 => x"0a535104",
-82 => x"00000000",
-83 => x"00000000",
-84 => x"00000000",
-85 => x"00000000",
-86 => x"00000000",
-87 => x"00000000",
-88 => x"72729f06",
-89 => x"0981050b",
-90 => x"0b0b88a6",
-91 => x"05040000",
-92 => x"00000000",
-93 => x"00000000",
-94 => x"00000000",
-95 => x"00000000",
-96 => x"72722aff",
-97 => x"739f062a",
-98 => x"0974090a",
-99 => x"8106ff05",
-100 => x"06075351",
-101 => x"04000000",
-102 => x"00000000",
-103 => x"00000000",
-104 => x"71715351",
-105 => x"020d0406",
-106 => x"73830609",
-107 => x"81058205",
-108 => x"832b0b2b",
-109 => x"0772fc06",
-110 => x"0c515104",
-111 => x"00000000",
-112 => x"72098105",
-113 => x"72050970",
-114 => x"81050906",
-115 => x"0a810653",
-116 => x"51040000",
-117 => x"00000000",
-118 => x"00000000",
-119 => x"00000000",
-120 => x"72098105",
-121 => x"72050970",
-122 => x"81050906",
-123 => x"0a098106",
-124 => x"53510400",
-125 => x"00000000",
-126 => x"00000000",
-127 => x"00000000",
-128 => x"71098105",
-129 => x"52040000",
-130 => x"00000000",
-131 => x"00000000",
-132 => x"00000000",
-133 => x"00000000",
-134 => x"00000000",
-135 => x"00000000",
-136 => x"72720981",
-137 => x"05055351",
-138 => x"04000000",
-139 => x"00000000",
-140 => x"00000000",
-141 => x"00000000",
-142 => x"00000000",
-143 => x"00000000",
-144 => x"72097206",
-145 => x"73730906",
-146 => x"07535104",
-147 => x"00000000",
-148 => x"00000000",
-149 => x"00000000",
-150 => x"00000000",
-151 => x"00000000",
-152 => x"71fc0608",
-153 => x"72830609",
-154 => x"81058305",
-155 => x"1010102a",
-156 => x"81ff0652",
-157 => x"04000000",
-158 => x"00000000",
-159 => x"00000000",
-160 => x"71fc0608",
-161 => x"0b0b80d5",
-162 => x"e0738306",
-163 => x"10100508",
-164 => x"060b0b0b",
-165 => x"88a90400",
-166 => x"00000000",
-167 => x"00000000",
-168 => x"80088408",
-169 => x"88087575",
-170 => x"0b0b0bad",
-171 => x"aa2d5050",
-172 => x"80085688",
-173 => x"0c840c80",
-174 => x"0c510400",
-175 => x"00000000",
-176 => x"80088408",
-177 => x"88087575",
-178 => x"0b0b0bad",
-179 => x"ee2d5050",
-180 => x"80085688",
-181 => x"0c840c80",
-182 => x"0c510400",
-183 => x"00000000",
-184 => x"72097081",
-185 => x"0509060a",
-186 => x"8106ff05",
-187 => x"70547106",
-188 => x"73097274",
-189 => x"05ff0506",
-190 => x"07515151",
-191 => x"04000000",
-192 => x"72097081",
-193 => x"0509060a",
-194 => x"098106ff",
-195 => x"05705471",
-196 => x"06730972",
-197 => x"7405ff05",
-198 => x"06075151",
-199 => x"51040000",
-200 => x"05ff0504",
-201 => x"00000000",
-202 => x"00000000",
-203 => x"00000000",
-204 => x"00000000",
-205 => x"00000000",
-206 => x"00000000",
-207 => x"00000000",
-208 => x"810b0b0b",
-209 => x"80d5f00c",
-210 => x"51040000",
-211 => x"00000000",
-212 => x"00000000",
-213 => x"00000000",
-214 => x"00000000",
-215 => x"00000000",
-216 => x"71810552",
-217 => x"04000000",
-218 => x"00000000",
-219 => x"00000000",
-220 => x"00000000",
-221 => x"00000000",
-222 => x"00000000",
-223 => x"00000000",
-224 => x"00000000",
-225 => x"00000000",
-226 => x"00000000",
-227 => x"00000000",
-228 => x"00000000",
-229 => x"00000000",
-230 => x"00000000",
-231 => x"00000000",
-232 => x"02840572",
-233 => x"10100552",
-234 => x"04000000",
-235 => x"00000000",
-236 => x"00000000",
-237 => x"00000000",
-238 => x"00000000",
-239 => x"00000000",
-240 => x"00000000",
-241 => x"00000000",
-242 => x"00000000",
-243 => x"00000000",
-244 => x"00000000",
-245 => x"00000000",
-246 => x"00000000",
-247 => x"00000000",
-248 => x"717105ff",
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-2771 => x"00002b44",
-2772 => x"00002b44",
-2773 => x"00002b4c",
-2774 => x"00002b4c",
-2775 => x"00002b54",
-2776 => x"00002b54",
-2777 => x"00002b5c",
-2778 => x"00002b5c",
-2779 => x"00002b64",
-2780 => x"00002b64",
-2781 => x"00002b6c",
-2782 => x"00002b6c",
-2783 => x"00002b74",
-2784 => x"00002b74",
-2785 => x"00002b7c",
-2786 => x"00002b7c",
-2787 => x"00002b84",
-2788 => x"00002b84",
-2789 => x"00002b8c",
-2790 => x"00002b8c",
-2791 => x"00002b94",
-2792 => x"00002b94",
-2793 => x"00002b9c",
-2794 => x"00002b9c",
-2795 => x"00002ba4",
-2796 => x"00002ba4",
-2797 => x"00002bac",
-2798 => x"00002bac",
-2799 => x"00002bb4",
-2800 => x"00002bb4",
-2801 => x"00002bbc",
-2802 => x"00002bbc",
-2803 => x"00002bc4",
-2804 => x"00002bc4",
-2805 => x"00002bcc",
-2806 => x"00002bcc",
-2807 => x"00002bd4",
-2808 => x"00002bd4",
-2809 => x"00002bdc",
-2810 => x"00002bdc",
-2811 => x"00002be4",
-2812 => x"00002be4",
-2813 => x"00002bec",
-2814 => x"00002bec",
-2815 => x"00002bf4",
-2816 => x"00002bf4",
-2817 => x"00002bfc",
-2818 => x"00002bfc",
-2819 => x"00002c04",
-2820 => x"00002c04",
-2821 => x"00002c0c",
-2822 => x"00002c0c",
-2823 => x"00002c14",
-2824 => x"00002c14",
-2825 => x"00002c1c",
-2826 => x"00002c1c",
-2827 => x"00002c24",
-2828 => x"00002c24",
-2829 => x"00002c2c",
-2830 => x"00002c2c",
-2831 => x"00002c34",
-2832 => x"00002c34",
-2833 => x"00002c3c",
-2834 => x"00002c3c",
-2835 => x"00002c44",
-2836 => x"00002c44",
-2837 => x"00002c4c",
-2838 => x"00002c4c",
-2839 => x"00002c54",
-2840 => x"00002c54",
-2841 => x"00002c5c",
-2842 => x"00002c5c",
-2843 => x"00002c64",
-2844 => x"00002c64",
-2845 => x"00002c6c",
-2846 => x"00002c6c",
-2847 => x"00002c74",
-2848 => x"00002c74",
-2849 => x"00002c7c",
-2850 => x"00002c7c",
-2851 => x"00002c84",
-2852 => x"00002c84",
-2853 => x"00002c8c",
-2854 => x"00002c8c",
-2855 => x"00002c94",
-2856 => x"00002c94",
-2857 => x"00002c9c",
-2858 => x"00002c9c",
-2859 => x"00002ca4",
-2860 => x"00002ca4",
-2861 => x"00002cac",
-2862 => x"00002cac",
-2863 => x"00002cb4",
-2864 => x"00002cb4",
-2865 => x"00002cbc",
-2866 => x"00002cbc",
-2867 => x"00002cc4",
-2868 => x"00002cc4",
-2869 => x"00002ccc",
-2870 => x"00002ccc",
-2871 => x"00002cd4",
-2872 => x"00002cd4",
-2873 => x"00002cdc",
-2874 => x"00002cdc",
-2875 => x"00002ce4",
-2876 => x"00002ce4",
-2877 => x"00002cec",
-2878 => x"00002cec",
-2879 => x"00002cf4",
-2880 => x"00002cf4",
-2881 => x"00002cfc",
-2882 => x"00002cfc",
-2883 => x"00002d04",
-2884 => x"00002d04",
-2885 => x"00002d0c",
-2886 => x"00002d0c",
-2887 => x"00002d14",
-2888 => x"00002d14",
-2889 => x"00002d1c",
-2890 => x"00002d1c",
-2891 => x"00002d24",
-2892 => x"00002d24",
-2893 => x"00002d2c",
-2894 => x"00002d2c",
-2895 => x"00002d34",
-2896 => x"00002d34",
-2897 => x"00002d3c",
-2898 => x"00002d3c",
-2899 => x"00002d44",
-2900 => x"00002d44",
-2901 => x"00002d4c",
-2902 => x"00002d4c",
-2903 => x"00002d54",
-2904 => x"00002d54",
-2905 => x"00002d5c",
-2906 => x"00002d5c",
-2907 => x"00002d64",
-2908 => x"00002d64",
-2909 => x"00002d6c",
-2910 => x"00002d6c",
-2911 => x"00002d74",
-2912 => x"00002d74",
-2913 => x"00002d7c",
-2914 => x"00002d7c",
-2915 => x"00002d84",
-2916 => x"00002d84",
-2917 => x"00002d8c",
-2918 => x"00002d8c",
-2919 => x"00002d94",
-2920 => x"00002d94",
-2921 => x"00002d9c",
-2922 => x"00002d9c",
-2923 => x"00002da4",
-2924 => x"00002da4",
-2925 => x"00002dac",
-2926 => x"00002dac",
-2927 => x"00002db4",
-2928 => x"00002db4",
-2929 => x"00002dbc",
-2930 => x"00002dbc",
-2931 => x"00002dc4",
-2932 => x"00002dc4",
-2933 => x"00002dcc",
-2934 => x"00002dcc",
-2935 => x"00002dd4",
-2936 => x"00002dd4",
-2937 => x"00002ddc",
-2938 => x"00002ddc",
-2939 => x"00002de4",
-2940 => x"00002de4",
-2941 => x"00002dec",
-2942 => x"00002dec",
-2943 => x"00002df4",
-2944 => x"00002df4",
-2945 => x"00002dfc",
-2946 => x"00002dfc",
-2947 => x"00002e04",
-2948 => x"00002e04",
-2949 => x"00002e0c",
-2950 => x"00002e0c",
-2951 => x"00002e14",
-2952 => x"00002e14",
-2953 => x"00002e1c",
-2954 => x"00002e1c",
-2955 => x"00002e24",
-2956 => x"00002e24",
-2957 => x"00002e2c",
-2958 => x"00002e2c",
-2959 => x"00002e34",
-2960 => x"00002e34",
-2961 => x"00002e3c",
-2962 => x"00002e3c",
-2963 => x"00002e44",
-2964 => x"00002e44",
-2965 => x"00002e4c",
-2966 => x"00002e4c",
-2967 => x"00002e54",
-2968 => x"00002e54",
-2969 => x"00002e5c",
-2970 => x"00002e5c",
-2971 => x"00002e64",
-2972 => x"00002e64",
-2973 => x"00002e6c",
-2974 => x"00002e6c",
-2975 => x"00002e74",
-2976 => x"00002e74",
-2977 => x"00002e7c",
-2978 => x"00002e7c",
-2979 => x"00002e84",
-2980 => x"00002e84",
-2981 => x"00002e8c",
-2982 => x"00002e8c",
-2983 => x"00002e94",
-2984 => x"00002e94",
-2985 => x"00002e9c",
-2986 => x"00002e9c",
-2987 => x"00002ea4",
-2988 => x"00002ea4",
-2989 => x"00002eac",
-2990 => x"00002eac",
-2991 => x"00002eb4",
-2992 => x"00002eb4",
-2993 => x"00002ebc",
-2994 => x"00002ebc",
-2995 => x"00002ec4",
-2996 => x"00002ec4",
-2997 => x"00002ecc",
-2998 => x"00002ecc",
-2999 => x"00002ed4",
-3000 => x"00002ed4",
-3001 => x"00002edc",
-3002 => x"00002edc",
-3003 => x"00002ee4",
-3004 => x"00002ee4",
-3005 => x"00002eec",
-3006 => x"00002eec",
-3007 => x"00002ef4",
-3008 => x"00002ef4",
-3009 => x"00002efc",
-3010 => x"00002efc",
-3011 => x"00002f04",
-3012 => x"00002f04",
-3013 => x"00002f0c",
-3014 => x"00002f0c",
-3015 => x"00002f14",
-3016 => x"00002f14",
-3017 => x"00002f1c",
-3018 => x"00002f1c",
-3019 => x"00002f24",
-3020 => x"00002f24",
-3021 => x"00002f2c",
-3022 => x"00002f2c",
-3023 => x"00002f34",
-3024 => x"00002f34",
-3025 => x"00002f3c",
-3026 => x"00002f3c",
-3027 => x"00002f50",
-3028 => x"00000000",
-3029 => x"000031b8",
-3030 => x"00003214",
-3031 => x"00003270",
-3032 => x"00000000",
-3033 => x"00000000",
-3034 => x"00000000",
-3035 => x"00000000",
-3036 => x"00000000",
-3037 => x"00000000",
-3038 => x"00000000",
-3039 => x"00000000",
-3040 => x"00000000",
-3041 => x"00002ad0",
-3042 => x"00000000",
-3043 => x"00000000",
-3044 => x"00000000",
-3045 => x"00000000",
-3046 => x"00000000",
-3047 => x"00000000",
-3048 => x"00000000",
-3049 => x"00000000",
-3050 => x"00000000",
-3051 => x"00000000",
-3052 => x"00000000",
-3053 => x"00000000",
-3054 => x"00000000",
-3055 => x"00000000",
-3056 => x"00000000",
-3057 => x"00000000",
-3058 => x"00000000",
-3059 => x"00000000",
-3060 => x"00000000",
-3061 => x"00000000",
-3062 => x"00000000",
-3063 => x"00000000",
-3064 => x"00000000",
-3065 => x"00000000",
-3066 => x"00000000",
-3067 => x"00000000",
-3068 => x"00000000",
-3069 => x"00000000",
-3070 => x"00000001",
-3071 => x"330eabcd",
-3072 => x"1234e66d",
-3073 => x"deec0005",
-3074 => x"000b0000",
-3075 => x"00000000",
-3076 => x"00000000",
-3077 => x"00000000",
-3078 => x"00000000",
-3079 => x"00000000",
-3080 => x"00000000",
-3081 => x"00000000",
-3082 => x"00000000",
-3083 => x"00000000",
-3084 => x"00000000",
-3085 => x"00000000",
-3086 => x"00000000",
-3087 => x"00000000",
-3088 => x"00000000",
-3089 => x"00000000",
-3090 => x"00000000",
-3091 => x"00000000",
-3092 => x"00000000",
-3093 => x"00000000",
-3094 => x"00000000",
-3095 => x"00000000",
-3096 => x"00000000",
-3097 => x"00000000",
-3098 => x"00000000",
-3099 => x"00000000",
-3100 => x"00000000",
-3101 => x"00000000",
-3102 => x"00000000",
-3103 => x"00000000",
-3104 => x"00000000",
-3105 => x"00000000",
-3106 => x"00000000",
-3107 => x"00000000",
-3108 => x"00000000",
-3109 => x"00000000",
-3110 => x"00000000",
-3111 => x"00000000",
-3112 => x"00000000",
-3113 => x"00000000",
-3114 => x"00000000",
-3115 => x"00000000",
-3116 => x"00000000",
-3117 => x"00000000",
-3118 => x"00000000",
-3119 => x"00000000",
-3120 => x"00000000",
-3121 => x"00000000",
-3122 => x"00000000",
-3123 => x"00000000",
-3124 => x"00000000",
-3125 => x"00000000",
-3126 => x"00000000",
-3127 => x"00000000",
-3128 => x"00000000",
-3129 => x"00000000",
-3130 => x"00000000",
-3131 => x"00000000",
-3132 => x"00000000",
-3133 => x"00000000",
-3134 => x"00000000",
-3135 => x"00000000",
-3136 => x"00000000",
-3137 => x"00000000",
-3138 => x"00000000",
-3139 => x"00000000",
-3140 => x"00000000",
-3141 => x"00000000",
-3142 => x"00000000",
-3143 => x"00000000",
-3144 => x"00000000",
-3145 => x"00000000",
-3146 => x"00000000",
-3147 => x"00000000",
-3148 => x"00000000",
-3149 => x"00000000",
-3150 => x"00000000",
-3151 => x"00000000",
-3152 => x"00000000",
-3153 => x"00000000",
-3154 => x"00000000",
-3155 => x"00000000",
-3156 => x"00000000",
-3157 => x"00000000",
-3158 => x"00000000",
-3159 => x"00000000",
-3160 => x"00000000",
-3161 => x"00000000",
-3162 => x"00000000",
-3163 => x"00000000",
-3164 => x"00000000",
-3165 => x"00000000",
-3166 => x"00000000",
-3167 => x"00000000",
-3168 => x"00000000",
-3169 => x"00000000",
-3170 => x"00000000",
-3171 => x"00000000",
-3172 => x"00000000",
-3173 => x"00000000",
-3174 => x"00000000",
-3175 => x"00000000",
-3176 => x"00000000",
-3177 => x"00000000",
-3178 => x"00000000",
-3179 => x"00000000",
-3180 => x"00000000",
-3181 => x"00000000",
-3182 => x"00000000",
-3183 => x"00000000",
-3184 => x"00000000",
-3185 => x"00000000",
-3186 => x"00000000",
-3187 => x"00000000",
-3188 => x"00000000",
-3189 => x"00000000",
-3190 => x"00000000",
-3191 => x"00000000",
-3192 => x"00000000",
-3193 => x"00000000",
-3194 => x"00000000",
-3195 => x"00000000",
-3196 => x"00000000",
-3197 => x"00000000",
-3198 => x"00000000",
-3199 => x"00000000",
-3200 => x"00000000",
-3201 => x"00000000",
-3202 => x"00000000",
-3203 => x"00000000",
-3204 => x"00000000",
-3205 => x"00000000",
-3206 => x"00000000",
-3207 => x"00000000",
-3208 => x"00000000",
-3209 => x"00000000",
-3210 => x"00000000",
-3211 => x"00000000",
-3212 => x"00000000",
-3213 => x"00000000",
-3214 => x"00000000",
-3215 => x"00000000",
-3216 => x"00000000",
-3217 => x"00000000",
-3218 => x"00000000",
-3219 => x"00000000",
-3220 => x"00000000",
-3221 => x"00000000",
-3222 => x"00000000",
-3223 => x"00000000",
-3224 => x"00000000",
-3225 => x"00000000",
-3226 => x"00000000",
-3227 => x"00000000",
-3228 => x"00000000",
-3229 => x"00000000",
-3230 => x"00000000",
-3231 => x"00000000",
-3232 => x"00000000",
-3233 => x"00000000",
-3234 => x"00000000",
-3235 => x"00000000",
-3236 => x"00000000",
-3237 => x"00000000",
-3238 => x"00000000",
-3239 => x"00000000",
-3240 => x"00000000",
-3241 => x"00000000",
-3242 => x"00000000",
-3243 => x"00000000",
-3244 => x"00000000",
-3245 => x"00000000",
-3246 => x"00000000",
-3247 => x"00000000",
-3248 => x"00000000",
-3249 => x"00000000",
-3250 => x"00000000",
-3251 => x"00002ad4",
-3252 => x"ffffffff",
-3253 => x"00000000",
-3254 => x"ffffffff",
-3255 => x"00000000",
-	others => x"00000000"
-);
-
-begin
-
-mem_busy<=mem_readEnable; -- we're done on the cycle after we serve the read request
-
-process (clk, areset)
-begin
-		if areset = '1' then
-		elsif (clk'event and clk = '1') then
-			if (mem_writeEnable = '1') then
-				ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit)))) := mem_write;
-			end if;
-		if (mem_readEnable = '1') then
-			mem_read <= ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit))));
-		end if;
-	end if;
-end process;
-
-
-
-
-end dram_arch;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity dram is
+port (clk : in std_logic;
+areset : std_logic;
+		mem_writeEnable : in std_logic;
+		mem_readEnable : in std_logic;
+		mem_addr : in std_logic_vector(maxAddrBit downto 0);
+		mem_write : in std_logic_vector(wordSize-1 downto 0);
+		mem_read : out std_logic_vector(wordSize-1 downto 0);
+		mem_busy : out std_logic;
+		mem_writeMask : in std_logic_vector(wordBytes-1 downto 0));
+end dram;
+
+architecture dram_arch of dram is
+
+
+type ram_type is array(natural range 0 to ((2**(maxAddrBitDRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
+
+shared variable ram : ram_type :=
+(
+0 => x"0b0b0b0b",
+1 => x"82700b0b",
+2 => x"80d5f40c",
+3 => x"3a0b0b80",
+4 => x"c4fb0400",
+5 => x"00000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"80c5c22d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
+17 => x"72830609",
+18 => x"81058205",
+19 => x"832b2a83",
+20 => x"ffff0652",
+21 => x"04000000",
+22 => x"00000000",
+23 => x"00000000",
+24 => x"71fd0608",
+25 => x"83ffff73",
+26 => x"83060981",
+27 => x"05820583",
+28 => x"2b2b0906",
+29 => x"7383ffff",
+30 => x"0b0b0b0b",
+31 => x"83a70400",
+32 => x"72098105",
+33 => x"72057373",
+34 => x"09060906",
+35 => x"73097306",
+36 => x"070a8106",
+37 => x"53510400",
+38 => x"00000000",
+39 => x"00000000",
+40 => x"72722473",
+41 => x"732e0753",
+42 => x"51040000",
+43 => x"00000000",
+44 => x"00000000",
+45 => x"00000000",
+46 => x"00000000",
+47 => x"00000000",
+48 => x"71737109",
+49 => x"71068106",
+50 => x"30720a10",
+51 => x"0a720a10",
+52 => x"0a31050a",
+53 => x"81065151",
+54 => x"53510400",
+55 => x"00000000",
+56 => x"72722673",
+57 => x"732e0753",
+58 => x"51040000",
+59 => x"00000000",
+60 => x"00000000",
+61 => x"00000000",
+62 => x"00000000",
+63 => x"00000000",
+64 => x"00000000",
+65 => x"00000000",
+66 => x"00000000",
+67 => x"00000000",
+68 => x"00000000",
+69 => x"00000000",
+70 => x"00000000",
+71 => x"00000000",
+72 => x"0b0b0b88",
+73 => x"c3040000",
+74 => x"00000000",
+75 => x"00000000",
+76 => x"00000000",
+77 => x"00000000",
+78 => x"00000000",
+79 => x"00000000",
+80 => x"720a722b",
+81 => x"0a535104",
+82 => x"00000000",
+83 => x"00000000",
+84 => x"00000000",
+85 => x"00000000",
+86 => x"00000000",
+87 => x"00000000",
+88 => x"72729f06",
+89 => x"0981050b",
+90 => x"0b0b88a6",
+91 => x"05040000",
+92 => x"00000000",
+93 => x"00000000",
+94 => x"00000000",
+95 => x"00000000",
+96 => x"72722aff",
+97 => x"739f062a",
+98 => x"0974090a",
+99 => x"8106ff05",
+100 => x"06075351",
+101 => x"04000000",
+102 => x"00000000",
+103 => x"00000000",
+104 => x"71715351",
+105 => x"020d0406",
+106 => x"73830609",
+107 => x"81058205",
+108 => x"832b0b2b",
+109 => x"0772fc06",
+110 => x"0c515104",
+111 => x"00000000",
+112 => x"72098105",
+113 => x"72050970",
+114 => x"81050906",
+115 => x"0a810653",
+116 => x"51040000",
+117 => x"00000000",
+118 => x"00000000",
+119 => x"00000000",
+120 => x"72098105",
+121 => x"72050970",
+122 => x"81050906",
+123 => x"0a098106",
+124 => x"53510400",
+125 => x"00000000",
+126 => x"00000000",
+127 => x"00000000",
+128 => x"71098105",
+129 => x"52040000",
+130 => x"00000000",
+131 => x"00000000",
+132 => x"00000000",
+133 => x"00000000",
+134 => x"00000000",
+135 => x"00000000",
+136 => x"72720981",
+137 => x"05055351",
+138 => x"04000000",
+139 => x"00000000",
+140 => x"00000000",
+141 => x"00000000",
+142 => x"00000000",
+143 => x"00000000",
+144 => x"72097206",
+145 => x"73730906",
+146 => x"07535104",
+147 => x"00000000",
+148 => x"00000000",
+149 => x"00000000",
+150 => x"00000000",
+151 => x"00000000",
+152 => x"71fc0608",
+153 => x"72830609",
+154 => x"81058305",
+155 => x"1010102a",
+156 => x"81ff0652",
+157 => x"04000000",
+158 => x"00000000",
+159 => x"00000000",
+160 => x"71fc0608",
+161 => x"0b0b80d5",
+162 => x"e0738306",
+163 => x"10100508",
+164 => x"060b0b0b",
+165 => x"88a90400",
+166 => x"00000000",
+167 => x"00000000",
+168 => x"80088408",
+169 => x"88087575",
+170 => x"0b0b0bad",
+171 => x"aa2d5050",
+172 => x"80085688",
+173 => x"0c840c80",
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+2705 => x"07070707",
+2706 => x"07070707",
+2707 => x"07070707",
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+2735 => x"08080808",
+2736 => x"08080808",
+2737 => x"08080808",
+2738 => x"08080808",
+2739 => x"08080808",
+2740 => x"43000000",
+2741 => x"64756d6d",
+2742 => x"792e6578",
+2743 => x"65000000",
+2744 => x"00ffffff",
+2745 => x"ff00ffff",
+2746 => x"ffff00ff",
+2747 => x"ffffff00",
+2748 => x"00000000",
+2749 => x"00000000",
+2750 => x"00000000",
+2751 => x"000032dc",
+2752 => x"0000c350",
+2753 => x"00000000",
+2754 => x"00000000",
+2755 => x"00000000",
+2756 => x"00000000",
+2757 => x"00000000",
+2758 => x"00000000",
+2759 => x"00000000",
+2760 => x"00000000",
+2761 => x"00000000",
+2762 => x"00000000",
+2763 => x"00000000",
+2764 => x"00000000",
+2765 => x"00000000",
+2766 => x"ffffffff",
+2767 => x"00000000",
+2768 => x"00020000",
+2769 => x"00000000",
+2770 => x"00000000",
+2771 => x"00002b44",
+2772 => x"00002b44",
+2773 => x"00002b4c",
+2774 => x"00002b4c",
+2775 => x"00002b54",
+2776 => x"00002b54",
+2777 => x"00002b5c",
+2778 => x"00002b5c",
+2779 => x"00002b64",
+2780 => x"00002b64",
+2781 => x"00002b6c",
+2782 => x"00002b6c",
+2783 => x"00002b74",
+2784 => x"00002b74",
+2785 => x"00002b7c",
+2786 => x"00002b7c",
+2787 => x"00002b84",
+2788 => x"00002b84",
+2789 => x"00002b8c",
+2790 => x"00002b8c",
+2791 => x"00002b94",
+2792 => x"00002b94",
+2793 => x"00002b9c",
+2794 => x"00002b9c",
+2795 => x"00002ba4",
+2796 => x"00002ba4",
+2797 => x"00002bac",
+2798 => x"00002bac",
+2799 => x"00002bb4",
+2800 => x"00002bb4",
+2801 => x"00002bbc",
+2802 => x"00002bbc",
+2803 => x"00002bc4",
+2804 => x"00002bc4",
+2805 => x"00002bcc",
+2806 => x"00002bcc",
+2807 => x"00002bd4",
+2808 => x"00002bd4",
+2809 => x"00002bdc",
+2810 => x"00002bdc",
+2811 => x"00002be4",
+2812 => x"00002be4",
+2813 => x"00002bec",
+2814 => x"00002bec",
+2815 => x"00002bf4",
+2816 => x"00002bf4",
+2817 => x"00002bfc",
+2818 => x"00002bfc",
+2819 => x"00002c04",
+2820 => x"00002c04",
+2821 => x"00002c0c",
+2822 => x"00002c0c",
+2823 => x"00002c14",
+2824 => x"00002c14",
+2825 => x"00002c1c",
+2826 => x"00002c1c",
+2827 => x"00002c24",
+2828 => x"00002c24",
+2829 => x"00002c2c",
+2830 => x"00002c2c",
+2831 => x"00002c34",
+2832 => x"00002c34",
+2833 => x"00002c3c",
+2834 => x"00002c3c",
+2835 => x"00002c44",
+2836 => x"00002c44",
+2837 => x"00002c4c",
+2838 => x"00002c4c",
+2839 => x"00002c54",
+2840 => x"00002c54",
+2841 => x"00002c5c",
+2842 => x"00002c5c",
+2843 => x"00002c64",
+2844 => x"00002c64",
+2845 => x"00002c6c",
+2846 => x"00002c6c",
+2847 => x"00002c74",
+2848 => x"00002c74",
+2849 => x"00002c7c",
+2850 => x"00002c7c",
+2851 => x"00002c84",
+2852 => x"00002c84",
+2853 => x"00002c8c",
+2854 => x"00002c8c",
+2855 => x"00002c94",
+2856 => x"00002c94",
+2857 => x"00002c9c",
+2858 => x"00002c9c",
+2859 => x"00002ca4",
+2860 => x"00002ca4",
+2861 => x"00002cac",
+2862 => x"00002cac",
+2863 => x"00002cb4",
+2864 => x"00002cb4",
+2865 => x"00002cbc",
+2866 => x"00002cbc",
+2867 => x"00002cc4",
+2868 => x"00002cc4",
+2869 => x"00002ccc",
+2870 => x"00002ccc",
+2871 => x"00002cd4",
+2872 => x"00002cd4",
+2873 => x"00002cdc",
+2874 => x"00002cdc",
+2875 => x"00002ce4",
+2876 => x"00002ce4",
+2877 => x"00002cec",
+2878 => x"00002cec",
+2879 => x"00002cf4",
+2880 => x"00002cf4",
+2881 => x"00002cfc",
+2882 => x"00002cfc",
+2883 => x"00002d04",
+2884 => x"00002d04",
+2885 => x"00002d0c",
+2886 => x"00002d0c",
+2887 => x"00002d14",
+2888 => x"00002d14",
+2889 => x"00002d1c",
+2890 => x"00002d1c",
+2891 => x"00002d24",
+2892 => x"00002d24",
+2893 => x"00002d2c",
+2894 => x"00002d2c",
+2895 => x"00002d34",
+2896 => x"00002d34",
+2897 => x"00002d3c",
+2898 => x"00002d3c",
+2899 => x"00002d44",
+2900 => x"00002d44",
+2901 => x"00002d4c",
+2902 => x"00002d4c",
+2903 => x"00002d54",
+2904 => x"00002d54",
+2905 => x"00002d5c",
+2906 => x"00002d5c",
+2907 => x"00002d64",
+2908 => x"00002d64",
+2909 => x"00002d6c",
+2910 => x"00002d6c",
+2911 => x"00002d74",
+2912 => x"00002d74",
+2913 => x"00002d7c",
+2914 => x"00002d7c",
+2915 => x"00002d84",
+2916 => x"00002d84",
+2917 => x"00002d8c",
+2918 => x"00002d8c",
+2919 => x"00002d94",
+2920 => x"00002d94",
+2921 => x"00002d9c",
+2922 => x"00002d9c",
+2923 => x"00002da4",
+2924 => x"00002da4",
+2925 => x"00002dac",
+2926 => x"00002dac",
+2927 => x"00002db4",
+2928 => x"00002db4",
+2929 => x"00002dbc",
+2930 => x"00002dbc",
+2931 => x"00002dc4",
+2932 => x"00002dc4",
+2933 => x"00002dcc",
+2934 => x"00002dcc",
+2935 => x"00002dd4",
+2936 => x"00002dd4",
+2937 => x"00002ddc",
+2938 => x"00002ddc",
+2939 => x"00002de4",
+2940 => x"00002de4",
+2941 => x"00002dec",
+2942 => x"00002dec",
+2943 => x"00002df4",
+2944 => x"00002df4",
+2945 => x"00002dfc",
+2946 => x"00002dfc",
+2947 => x"00002e04",
+2948 => x"00002e04",
+2949 => x"00002e0c",
+2950 => x"00002e0c",
+2951 => x"00002e14",
+2952 => x"00002e14",
+2953 => x"00002e1c",
+2954 => x"00002e1c",
+2955 => x"00002e24",
+2956 => x"00002e24",
+2957 => x"00002e2c",
+2958 => x"00002e2c",
+2959 => x"00002e34",
+2960 => x"00002e34",
+2961 => x"00002e3c",
+2962 => x"00002e3c",
+2963 => x"00002e44",
+2964 => x"00002e44",
+2965 => x"00002e4c",
+2966 => x"00002e4c",
+2967 => x"00002e54",
+2968 => x"00002e54",
+2969 => x"00002e5c",
+2970 => x"00002e5c",
+2971 => x"00002e64",
+2972 => x"00002e64",
+2973 => x"00002e6c",
+2974 => x"00002e6c",
+2975 => x"00002e74",
+2976 => x"00002e74",
+2977 => x"00002e7c",
+2978 => x"00002e7c",
+2979 => x"00002e84",
+2980 => x"00002e84",
+2981 => x"00002e8c",
+2982 => x"00002e8c",
+2983 => x"00002e94",
+2984 => x"00002e94",
+2985 => x"00002e9c",
+2986 => x"00002e9c",
+2987 => x"00002ea4",
+2988 => x"00002ea4",
+2989 => x"00002eac",
+2990 => x"00002eac",
+2991 => x"00002eb4",
+2992 => x"00002eb4",
+2993 => x"00002ebc",
+2994 => x"00002ebc",
+2995 => x"00002ec4",
+2996 => x"00002ec4",
+2997 => x"00002ecc",
+2998 => x"00002ecc",
+2999 => x"00002ed4",
+3000 => x"00002ed4",
+3001 => x"00002edc",
+3002 => x"00002edc",
+3003 => x"00002ee4",
+3004 => x"00002ee4",
+3005 => x"00002eec",
+3006 => x"00002eec",
+3007 => x"00002ef4",
+3008 => x"00002ef4",
+3009 => x"00002efc",
+3010 => x"00002efc",
+3011 => x"00002f04",
+3012 => x"00002f04",
+3013 => x"00002f0c",
+3014 => x"00002f0c",
+3015 => x"00002f14",
+3016 => x"00002f14",
+3017 => x"00002f1c",
+3018 => x"00002f1c",
+3019 => x"00002f24",
+3020 => x"00002f24",
+3021 => x"00002f2c",
+3022 => x"00002f2c",
+3023 => x"00002f34",
+3024 => x"00002f34",
+3025 => x"00002f3c",
+3026 => x"00002f3c",
+3027 => x"00002f50",
+3028 => x"00000000",
+3029 => x"000031b8",
+3030 => x"00003214",
+3031 => x"00003270",
+3032 => x"00000000",
+3033 => x"00000000",
+3034 => x"00000000",
+3035 => x"00000000",
+3036 => x"00000000",
+3037 => x"00000000",
+3038 => x"00000000",
+3039 => x"00000000",
+3040 => x"00000000",
+3041 => x"00002ad0",
+3042 => x"00000000",
+3043 => x"00000000",
+3044 => x"00000000",
+3045 => x"00000000",
+3046 => x"00000000",
+3047 => x"00000000",
+3048 => x"00000000",
+3049 => x"00000000",
+3050 => x"00000000",
+3051 => x"00000000",
+3052 => x"00000000",
+3053 => x"00000000",
+3054 => x"00000000",
+3055 => x"00000000",
+3056 => x"00000000",
+3057 => x"00000000",
+3058 => x"00000000",
+3059 => x"00000000",
+3060 => x"00000000",
+3061 => x"00000000",
+3062 => x"00000000",
+3063 => x"00000000",
+3064 => x"00000000",
+3065 => x"00000000",
+3066 => x"00000000",
+3067 => x"00000000",
+3068 => x"00000000",
+3069 => x"00000000",
+3070 => x"00000001",
+3071 => x"330eabcd",
+3072 => x"1234e66d",
+3073 => x"deec0005",
+3074 => x"000b0000",
+3075 => x"00000000",
+3076 => x"00000000",
+3077 => x"00000000",
+3078 => x"00000000",
+3079 => x"00000000",
+3080 => x"00000000",
+3081 => x"00000000",
+3082 => x"00000000",
+3083 => x"00000000",
+3084 => x"00000000",
+3085 => x"00000000",
+3086 => x"00000000",
+3087 => x"00000000",
+3088 => x"00000000",
+3089 => x"00000000",
+3090 => x"00000000",
+3091 => x"00000000",
+3092 => x"00000000",
+3093 => x"00000000",
+3094 => x"00000000",
+3095 => x"00000000",
+3096 => x"00000000",
+3097 => x"00000000",
+3098 => x"00000000",
+3099 => x"00000000",
+3100 => x"00000000",
+3101 => x"00000000",
+3102 => x"00000000",
+3103 => x"00000000",
+3104 => x"00000000",
+3105 => x"00000000",
+3106 => x"00000000",
+3107 => x"00000000",
+3108 => x"00000000",
+3109 => x"00000000",
+3110 => x"00000000",
+3111 => x"00000000",
+3112 => x"00000000",
+3113 => x"00000000",
+3114 => x"00000000",
+3115 => x"00000000",
+3116 => x"00000000",
+3117 => x"00000000",
+3118 => x"00000000",
+3119 => x"00000000",
+3120 => x"00000000",
+3121 => x"00000000",
+3122 => x"00000000",
+3123 => x"00000000",
+3124 => x"00000000",
+3125 => x"00000000",
+3126 => x"00000000",
+3127 => x"00000000",
+3128 => x"00000000",
+3129 => x"00000000",
+3130 => x"00000000",
+3131 => x"00000000",
+3132 => x"00000000",
+3133 => x"00000000",
+3134 => x"00000000",
+3135 => x"00000000",
+3136 => x"00000000",
+3137 => x"00000000",
+3138 => x"00000000",
+3139 => x"00000000",
+3140 => x"00000000",
+3141 => x"00000000",
+3142 => x"00000000",
+3143 => x"00000000",
+3144 => x"00000000",
+3145 => x"00000000",
+3146 => x"00000000",
+3147 => x"00000000",
+3148 => x"00000000",
+3149 => x"00000000",
+3150 => x"00000000",
+3151 => x"00000000",
+3152 => x"00000000",
+3153 => x"00000000",
+3154 => x"00000000",
+3155 => x"00000000",
+3156 => x"00000000",
+3157 => x"00000000",
+3158 => x"00000000",
+3159 => x"00000000",
+3160 => x"00000000",
+3161 => x"00000000",
+3162 => x"00000000",
+3163 => x"00000000",
+3164 => x"00000000",
+3165 => x"00000000",
+3166 => x"00000000",
+3167 => x"00000000",
+3168 => x"00000000",
+3169 => x"00000000",
+3170 => x"00000000",
+3171 => x"00000000",
+3172 => x"00000000",
+3173 => x"00000000",
+3174 => x"00000000",
+3175 => x"00000000",
+3176 => x"00000000",
+3177 => x"00000000",
+3178 => x"00000000",
+3179 => x"00000000",
+3180 => x"00000000",
+3181 => x"00000000",
+3182 => x"00000000",
+3183 => x"00000000",
+3184 => x"00000000",
+3185 => x"00000000",
+3186 => x"00000000",
+3187 => x"00000000",
+3188 => x"00000000",
+3189 => x"00000000",
+3190 => x"00000000",
+3191 => x"00000000",
+3192 => x"00000000",
+3193 => x"00000000",
+3194 => x"00000000",
+3195 => x"00000000",
+3196 => x"00000000",
+3197 => x"00000000",
+3198 => x"00000000",
+3199 => x"00000000",
+3200 => x"00000000",
+3201 => x"00000000",
+3202 => x"00000000",
+3203 => x"00000000",
+3204 => x"00000000",
+3205 => x"00000000",
+3206 => x"00000000",
+3207 => x"00000000",
+3208 => x"00000000",
+3209 => x"00000000",
+3210 => x"00000000",
+3211 => x"00000000",
+3212 => x"00000000",
+3213 => x"00000000",
+3214 => x"00000000",
+3215 => x"00000000",
+3216 => x"00000000",
+3217 => x"00000000",
+3218 => x"00000000",
+3219 => x"00000000",
+3220 => x"00000000",
+3221 => x"00000000",
+3222 => x"00000000",
+3223 => x"00000000",
+3224 => x"00000000",
+3225 => x"00000000",
+3226 => x"00000000",
+3227 => x"00000000",
+3228 => x"00000000",
+3229 => x"00000000",
+3230 => x"00000000",
+3231 => x"00000000",
+3232 => x"00000000",
+3233 => x"00000000",
+3234 => x"00000000",
+3235 => x"00000000",
+3236 => x"00000000",
+3237 => x"00000000",
+3238 => x"00000000",
+3239 => x"00000000",
+3240 => x"00000000",
+3241 => x"00000000",
+3242 => x"00000000",
+3243 => x"00000000",
+3244 => x"00000000",
+3245 => x"00000000",
+3246 => x"00000000",
+3247 => x"00000000",
+3248 => x"00000000",
+3249 => x"00000000",
+3250 => x"00000000",
+3251 => x"00002ad4",
+3252 => x"ffffffff",
+3253 => x"00000000",
+3254 => x"ffffffff",
+3255 => x"00000000",
+	others => x"00000000"
+);
+
+begin
+
+mem_busy<=mem_readEnable; -- we're done on the cycle after we serve the read request
+
+process (clk, areset)
+begin
+		if areset = '1' then
+		elsif (clk'event and clk = '1') then
+			if (mem_writeEnable = '1') then
+				ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit)))) := mem_write;
+			end if;
+		if (mem_readEnable = '1') then
+			mem_read <= ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit))));
+		end if;
+	end if;
+end process;
+
+
+
+
+end dram_arch;
diff --git a/zpu/hdl/example_medium/dram_hello.vhd b/zpu/hdl/example_medium/dram_hello.vhd
index 4f02cca..aae18fd 100644
--- a/zpu/hdl/example_medium/dram_hello.vhd
+++ b/zpu/hdl/example_medium/dram_hello.vhd
@@ -1,3107 +1,3107 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-
-library work;
-use work.zpu_config.all;
-use work.zpupkg.all;
-
-entity dram is
-port (clk : in std_logic;
-areset : std_logic;
-		mem_writeEnable : in std_logic;
-		mem_readEnable : in std_logic;
-		mem_addr : in std_logic_vector(maxAddrBit downto 0);
-		mem_write : in std_logic_vector(wordSize-1 downto 0);
-		mem_read : out std_logic_vector(wordSize-1 downto 0);
-		mem_busy : out std_logic;
-		mem_writeMask : in std_logic_vector(wordBytes-1 downto 0));
-end dram;
-
-architecture dram_arch of dram is
-
-
-type ram_type is array(natural range 0 to ((2**(maxAddrBitDRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
-
-shared variable ram : ram_type :=
-(
-0 => x"0b0b0b0b",
-1 => x"82700b0b",
-2 => x"80cfd80c",
-3 => x"3a0b0b80",
-4 => x"c6d00400",
-5 => x"00000000",
-6 => x"00000000",
-7 => x"00000000",
-8 => x"80088408",
-9 => x"88080b0b",
-10 => x"80c7972d",
-11 => x"880c840c",
-12 => x"800c0400",
-13 => x"00000000",
-14 => x"00000000",
-15 => x"00000000",
-16 => x"71fd0608",
-17 => x"72830609",
-18 => x"81058205",
-19 => x"832b2a83",
-20 => x"ffff0652",
-21 => x"04000000",
-22 => x"00000000",
-23 => x"00000000",
-24 => x"71fd0608",
-25 => x"83ffff73",
-26 => x"83060981",
-27 => x"05820583",
-28 => x"2b2b0906",
-29 => x"7383ffff",
-30 => x"0b0b0b0b",
-31 => x"83a70400",
-32 => x"72098105",
-33 => x"72057373",
-34 => x"09060906",
-35 => x"73097306",
-36 => x"070a8106",
-37 => x"53510400",
-38 => x"00000000",
-39 => x"00000000",
-40 => x"72722473",
-41 => x"732e0753",
-42 => x"51040000",
-43 => x"00000000",
-44 => x"00000000",
-45 => x"00000000",
-46 => x"00000000",
-47 => x"00000000",
-48 => x"71737109",
-49 => x"71068106",
-50 => x"30720a10",
-51 => x"0a720a10",
-52 => x"0a31050a",
-53 => x"81065151",
-54 => x"53510400",
-55 => x"00000000",
-56 => x"72722673",
-57 => x"732e0753",
-58 => x"51040000",
-59 => x"00000000",
-60 => x"00000000",
-61 => x"00000000",
-62 => x"00000000",
-63 => x"00000000",
-64 => x"00000000",
-65 => x"00000000",
-66 => x"00000000",
-67 => x"00000000",
-68 => x"00000000",
-69 => x"00000000",
-70 => x"00000000",
-71 => x"00000000",
-72 => x"0b0b0b88",
-73 => x"c4040000",
-74 => x"00000000",
-75 => x"00000000",
-76 => x"00000000",
-77 => x"00000000",
-78 => x"00000000",
-79 => x"00000000",
-80 => x"720a722b",
-81 => x"0a535104",
-82 => x"00000000",
-83 => x"00000000",
-84 => x"00000000",
-85 => x"00000000",
-86 => x"00000000",
-87 => x"00000000",
-88 => x"72729f06",
-89 => x"0981050b",
-90 => x"0b0b88a7",
-91 => x"05040000",
-92 => x"00000000",
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-2671 => x"00000000",
-2672 => x"00000000",
-2673 => x"00000000",
-2674 => x"00000000",
-2675 => x"00000000",
-2676 => x"00000000",
-2677 => x"00000000",
-2678 => x"00000000",
-2679 => x"00000000",
-2680 => x"00000000",
-2681 => x"00000000",
-2682 => x"00000000",
-2683 => x"00000000",
-2684 => x"00000000",
-2685 => x"00000000",
-2686 => x"00000000",
-2687 => x"00000000",
-2688 => x"00000000",
-2689 => x"00000000",
-2690 => x"00000000",
-2691 => x"00000000",
-2692 => x"00000000",
-2693 => x"00000000",
-2694 => x"00000000",
-2695 => x"00000000",
-2696 => x"00000000",
-2697 => x"00000000",
-2698 => x"00000000",
-2699 => x"00000000",
-2700 => x"00000000",
-2701 => x"00000000",
-2702 => x"00000000",
-2703 => x"00000000",
-2704 => x"00000000",
-2705 => x"00000000",
-2706 => x"00000000",
-2707 => x"00000000",
-2708 => x"00000000",
-2709 => x"00000000",
-2710 => x"00000000",
-2711 => x"00000000",
-2712 => x"00000000",
-2713 => x"00000000",
-2714 => x"00000000",
-2715 => x"00000000",
-2716 => x"00000000",
-2717 => x"00000000",
-2718 => x"00000000",
-2719 => x"00000000",
-2720 => x"00000000",
-2721 => x"00000000",
-2722 => x"00000000",
-2723 => x"00000000",
-2724 => x"00000000",
-2725 => x"00000000",
-2726 => x"00000000",
-2727 => x"00000000",
-2728 => x"00000000",
-2729 => x"00000000",
-2730 => x"00000000",
-2731 => x"00000000",
-2732 => x"00000000",
-2733 => x"00000000",
-2734 => x"00000000",
-2735 => x"00000000",
-2736 => x"00000000",
-2737 => x"00000000",
-2738 => x"00000000",
-2739 => x"00000000",
-2740 => x"00000000",
-2741 => x"00000000",
-2742 => x"00000000",
-2743 => x"00000000",
-2744 => x"00000000",
-2745 => x"00000000",
-2746 => x"00000000",
-2747 => x"00000000",
-2748 => x"00000000",
-2749 => x"00000000",
-2750 => x"00000000",
-2751 => x"00000000",
-2752 => x"00000000",
-2753 => x"00000000",
-2754 => x"00000000",
-2755 => x"00000000",
-2756 => x"00000000",
-2757 => x"00000000",
-2758 => x"00000000",
-2759 => x"00000000",
-2760 => x"00000000",
-2761 => x"00000000",
-2762 => x"00000000",
-2763 => x"00000000",
-2764 => x"00000000",
-2765 => x"00000000",
-2766 => x"00000000",
-2767 => x"00000000",
-2768 => x"00000000",
-2769 => x"00000000",
-2770 => x"00000000",
-2771 => x"00000000",
-2772 => x"00000000",
-2773 => x"00000000",
-2774 => x"00000000",
-2775 => x"00000000",
-2776 => x"00000000",
-2777 => x"00000000",
-2778 => x"00000000",
-2779 => x"00000000",
-2780 => x"00000000",
-2781 => x"00000000",
-2782 => x"00000000",
-2783 => x"00000000",
-2784 => x"00000000",
-2785 => x"00000000",
-2786 => x"00000000",
-2787 => x"00000000",
-2788 => x"00000000",
-2789 => x"ffffffff",
-2790 => x"00000000",
-2791 => x"00020000",
-2792 => x"00000000",
-2793 => x"00000000",
-2794 => x"00002ba0",
-2795 => x"00002ba0",
-2796 => x"00002ba8",
-2797 => x"00002ba8",
-2798 => x"00002bb0",
-2799 => x"00002bb0",
-2800 => x"00002bb8",
-2801 => x"00002bb8",
-2802 => x"00002bc0",
-2803 => x"00002bc0",
-2804 => x"00002bc8",
-2805 => x"00002bc8",
-2806 => x"00002bd0",
-2807 => x"00002bd0",
-2808 => x"00002bd8",
-2809 => x"00002bd8",
-2810 => x"00002be0",
-2811 => x"00002be0",
-2812 => x"00002be8",
-2813 => x"00002be8",
-2814 => x"00002bf0",
-2815 => x"00002bf0",
-2816 => x"00002bf8",
-2817 => x"00002bf8",
-2818 => x"00002c00",
-2819 => x"00002c00",
-2820 => x"00002c08",
-2821 => x"00002c08",
-2822 => x"00002c10",
-2823 => x"00002c10",
-2824 => x"00002c18",
-2825 => x"00002c18",
-2826 => x"00002c20",
-2827 => x"00002c20",
-2828 => x"00002c28",
-2829 => x"00002c28",
-2830 => x"00002c30",
-2831 => x"00002c30",
-2832 => x"00002c38",
-2833 => x"00002c38",
-2834 => x"00002c40",
-2835 => x"00002c40",
-2836 => x"00002c48",
-2837 => x"00002c48",
-2838 => x"00002c50",
-2839 => x"00002c50",
-2840 => x"00002c58",
-2841 => x"00002c58",
-2842 => x"00002c60",
-2843 => x"00002c60",
-2844 => x"00002c68",
-2845 => x"00002c68",
-2846 => x"00002c70",
-2847 => x"00002c70",
-2848 => x"00002c78",
-2849 => x"00002c78",
-2850 => x"00002c80",
-2851 => x"00002c80",
-2852 => x"00002c88",
-2853 => x"00002c88",
-2854 => x"00002c90",
-2855 => x"00002c90",
-2856 => x"00002c98",
-2857 => x"00002c98",
-2858 => x"00002ca0",
-2859 => x"00002ca0",
-2860 => x"00002ca8",
-2861 => x"00002ca8",
-2862 => x"00002cb0",
-2863 => x"00002cb0",
-2864 => x"00002cb8",
-2865 => x"00002cb8",
-2866 => x"00002cc0",
-2867 => x"00002cc0",
-2868 => x"00002cc8",
-2869 => x"00002cc8",
-2870 => x"00002cd0",
-2871 => x"00002cd0",
-2872 => x"00002cd8",
-2873 => x"00002cd8",
-2874 => x"00002ce0",
-2875 => x"00002ce0",
-2876 => x"00002ce8",
-2877 => x"00002ce8",
-2878 => x"00002cf0",
-2879 => x"00002cf0",
-2880 => x"00002cf8",
-2881 => x"00002cf8",
-2882 => x"00002d00",
-2883 => x"00002d00",
-2884 => x"00002d08",
-2885 => x"00002d08",
-2886 => x"00002d10",
-2887 => x"00002d10",
-2888 => x"00002d18",
-2889 => x"00002d18",
-2890 => x"00002d20",
-2891 => x"00002d20",
-2892 => x"00002d28",
-2893 => x"00002d28",
-2894 => x"00002d30",
-2895 => x"00002d30",
-2896 => x"00002d38",
-2897 => x"00002d38",
-2898 => x"00002d40",
-2899 => x"00002d40",
-2900 => x"00002d48",
-2901 => x"00002d48",
-2902 => x"00002d50",
-2903 => x"00002d50",
-2904 => x"00002d58",
-2905 => x"00002d58",
-2906 => x"00002d60",
-2907 => x"00002d60",
-2908 => x"00002d68",
-2909 => x"00002d68",
-2910 => x"00002d70",
-2911 => x"00002d70",
-2912 => x"00002d78",
-2913 => x"00002d78",
-2914 => x"00002d80",
-2915 => x"00002d80",
-2916 => x"00002d88",
-2917 => x"00002d88",
-2918 => x"00002d90",
-2919 => x"00002d90",
-2920 => x"00002d98",
-2921 => x"00002d98",
-2922 => x"00002da0",
-2923 => x"00002da0",
-2924 => x"00002da8",
-2925 => x"00002da8",
-2926 => x"00002db0",
-2927 => x"00002db0",
-2928 => x"00002db8",
-2929 => x"00002db8",
-2930 => x"00002dc0",
-2931 => x"00002dc0",
-2932 => x"00002dc8",
-2933 => x"00002dc8",
-2934 => x"00002dd0",
-2935 => x"00002dd0",
-2936 => x"00002dd8",
-2937 => x"00002dd8",
-2938 => x"00002de0",
-2939 => x"00002de0",
-2940 => x"00002de8",
-2941 => x"00002de8",
-2942 => x"00002df0",
-2943 => x"00002df0",
-2944 => x"00002df8",
-2945 => x"00002df8",
-2946 => x"00002e00",
-2947 => x"00002e00",
-2948 => x"00002e08",
-2949 => x"00002e08",
-2950 => x"00002e10",
-2951 => x"00002e10",
-2952 => x"00002e18",
-2953 => x"00002e18",
-2954 => x"00002e20",
-2955 => x"00002e20",
-2956 => x"00002e28",
-2957 => x"00002e28",
-2958 => x"00002e30",
-2959 => x"00002e30",
-2960 => x"00002e38",
-2961 => x"00002e38",
-2962 => x"00002e40",
-2963 => x"00002e40",
-2964 => x"00002e48",
-2965 => x"00002e48",
-2966 => x"00002e50",
-2967 => x"00002e50",
-2968 => x"00002e58",
-2969 => x"00002e58",
-2970 => x"00002e60",
-2971 => x"00002e60",
-2972 => x"00002e68",
-2973 => x"00002e68",
-2974 => x"00002e70",
-2975 => x"00002e70",
-2976 => x"00002e78",
-2977 => x"00002e78",
-2978 => x"00002e80",
-2979 => x"00002e80",
-2980 => x"00002e88",
-2981 => x"00002e88",
-2982 => x"00002e90",
-2983 => x"00002e90",
-2984 => x"00002e98",
-2985 => x"00002e98",
-2986 => x"00002ea0",
-2987 => x"00002ea0",
-2988 => x"00002ea8",
-2989 => x"00002ea8",
-2990 => x"00002eb0",
-2991 => x"00002eb0",
-2992 => x"00002eb8",
-2993 => x"00002eb8",
-2994 => x"00002ec0",
-2995 => x"00002ec0",
-2996 => x"00002ec8",
-2997 => x"00002ec8",
-2998 => x"00002ed0",
-2999 => x"00002ed0",
-3000 => x"00002ed8",
-3001 => x"00002ed8",
-3002 => x"00002ee0",
-3003 => x"00002ee0",
-3004 => x"00002ee8",
-3005 => x"00002ee8",
-3006 => x"00002ef0",
-3007 => x"00002ef0",
-3008 => x"00002ef8",
-3009 => x"00002ef8",
-3010 => x"00002f00",
-3011 => x"00002f00",
-3012 => x"00002f08",
-3013 => x"00002f08",
-3014 => x"00002f10",
-3015 => x"00002f10",
-3016 => x"00002f18",
-3017 => x"00002f18",
-3018 => x"00002f20",
-3019 => x"00002f20",
-3020 => x"00002f28",
-3021 => x"00002f28",
-3022 => x"00002f30",
-3023 => x"00002f30",
-3024 => x"00002f38",
-3025 => x"00002f38",
-3026 => x"00002f40",
-3027 => x"00002f40",
-3028 => x"00002f48",
-3029 => x"00002f48",
-3030 => x"00002f50",
-3031 => x"00002f50",
-3032 => x"00002f58",
-3033 => x"00002f58",
-3034 => x"00002f60",
-3035 => x"00002f60",
-3036 => x"00002f68",
-3037 => x"00002f68",
-3038 => x"00002f70",
-3039 => x"00002f70",
-3040 => x"00002f78",
-3041 => x"00002f78",
-3042 => x"00002f80",
-3043 => x"00002f80",
-3044 => x"00002f88",
-3045 => x"00002f88",
-3046 => x"00002f90",
-3047 => x"00002f90",
-3048 => x"00002f98",
-3049 => x"00002f98",
-3050 => x"000027b8",
-3051 => x"ffffffff",
-3052 => x"00000000",
-3053 => x"ffffffff",
-3054 => x"00000000",
-	others => x"00000000"
-);
-
-begin
-
-mem_busy<=mem_readEnable; -- we're done on the cycle after we serve the read request
-
-process (clk, areset)
-begin
-		if areset = '1' then
-		elsif (clk'event and clk = '1') then
-			if (mem_writeEnable = '1') then
-				ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit)))) := mem_write;
-			end if;
-		if (mem_readEnable = '1') then
-			mem_read <= ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit))));
-		end if;
-	end if;
-end process;
-
-
-
-
-end dram_arch;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity dram is
+port (clk : in std_logic;
+areset : std_logic;
+		mem_writeEnable : in std_logic;
+		mem_readEnable : in std_logic;
+		mem_addr : in std_logic_vector(maxAddrBit downto 0);
+		mem_write : in std_logic_vector(wordSize-1 downto 0);
+		mem_read : out std_logic_vector(wordSize-1 downto 0);
+		mem_busy : out std_logic;
+		mem_writeMask : in std_logic_vector(wordBytes-1 downto 0));
+end dram;
+
+architecture dram_arch of dram is
+
+
+type ram_type is array(natural range 0 to ((2**(maxAddrBitDRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
+
+shared variable ram : ram_type :=
+(
+0 => x"0b0b0b0b",
+1 => x"82700b0b",
+2 => x"80cfd80c",
+3 => x"3a0b0b80",
+4 => x"c6d00400",
+5 => x"00000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"80c7972d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
+17 => x"72830609",
+18 => x"81058205",
+19 => x"832b2a83",
+20 => x"ffff0652",
+21 => x"04000000",
+22 => x"00000000",
+23 => x"00000000",
+24 => x"71fd0608",
+25 => x"83ffff73",
+26 => x"83060981",
+27 => x"05820583",
+28 => x"2b2b0906",
+29 => x"7383ffff",
+30 => x"0b0b0b0b",
+31 => x"83a70400",
+32 => x"72098105",
+33 => x"72057373",
+34 => x"09060906",
+35 => x"73097306",
+36 => x"070a8106",
+37 => x"53510400",
+38 => x"00000000",
+39 => x"00000000",
+40 => x"72722473",
+41 => x"732e0753",
+42 => x"51040000",
+43 => x"00000000",
+44 => x"00000000",
+45 => x"00000000",
+46 => x"00000000",
+47 => x"00000000",
+48 => x"71737109",
+49 => x"71068106",
+50 => x"30720a10",
+51 => x"0a720a10",
+52 => x"0a31050a",
+53 => x"81065151",
+54 => x"53510400",
+55 => x"00000000",
+56 => x"72722673",
+57 => x"732e0753",
+58 => x"51040000",
+59 => x"00000000",
+60 => x"00000000",
+61 => x"00000000",
+62 => x"00000000",
+63 => x"00000000",
+64 => x"00000000",
+65 => x"00000000",
+66 => x"00000000",
+67 => x"00000000",
+68 => x"00000000",
+69 => x"00000000",
+70 => x"00000000",
+71 => x"00000000",
+72 => x"0b0b0b88",
+73 => x"c4040000",
+74 => x"00000000",
+75 => x"00000000",
+76 => x"00000000",
+77 => x"00000000",
+78 => x"00000000",
+79 => x"00000000",
+80 => x"720a722b",
+81 => x"0a535104",
+82 => x"00000000",
+83 => x"00000000",
+84 => x"00000000",
+85 => x"00000000",
+86 => x"00000000",
+87 => x"00000000",
+88 => x"72729f06",
+89 => x"0981050b",
+90 => x"0b0b88a7",
+91 => x"05040000",
+92 => x"00000000",
+93 => x"00000000",
+94 => x"00000000",
+95 => x"00000000",
+96 => x"72722aff",
+97 => x"739f062a",
+98 => x"0974090a",
+99 => x"8106ff05",
+100 => x"06075351",
+101 => x"04000000",
+102 => x"00000000",
+103 => x"00000000",
+104 => x"71715351",
+105 => x"020d0406",
+106 => x"73830609",
+107 => x"81058205",
+108 => x"832b0b2b",
+109 => x"0772fc06",
+110 => x"0c515104",
+111 => x"00000000",
+112 => x"72098105",
+113 => x"72050970",
+114 => x"81050906",
+115 => x"0a810653",
+116 => x"51040000",
+117 => x"00000000",
+118 => x"00000000",
+119 => x"00000000",
+120 => x"72098105",
+121 => x"72050970",
+122 => x"81050906",
+123 => x"0a098106",
+124 => x"53510400",
+125 => x"00000000",
+126 => x"00000000",
+127 => x"00000000",
+128 => x"71098105",
+129 => x"52040000",
+130 => x"00000000",
+131 => x"00000000",
+132 => x"00000000",
+133 => x"00000000",
+134 => x"00000000",
+135 => x"00000000",
+136 => x"72720981",
+137 => x"05055351",
+138 => x"04000000",
+139 => x"00000000",
+140 => x"00000000",
+141 => x"00000000",
+142 => x"00000000",
+143 => x"00000000",
+144 => x"72097206",
+145 => x"73730906",
+146 => x"07535104",
+147 => x"00000000",
+148 => x"00000000",
+149 => x"00000000",
+150 => x"00000000",
+151 => x"00000000",
+152 => x"71fc0608",
+153 => x"72830609",
+154 => x"81058305",
+155 => x"1010102a",
+156 => x"81ff0652",
+157 => x"04000000",
+158 => x"00000000",
+159 => x"00000000",
+160 => x"71fc0608",
+161 => x"0b0b80cf",
+162 => x"c4738306",
+163 => x"10100508",
+164 => x"060b0b0b",
+165 => x"88aa0400",
+166 => x"00000000",
+167 => x"00000000",
+168 => x"80088408",
+169 => x"88087575",
+170 => x"0b0b0b8b",
+171 => x"9f2d5050",
+172 => x"80085688",
+173 => x"0c840c80",
+174 => x"0c510400",
+175 => x"00000000",
+176 => x"80088408",
+177 => x"88087575",
+178 => x"0b0b0b8b",
+179 => x"e32d5050",
+180 => x"80085688",
+181 => x"0c840c80",
+182 => x"0c510400",
+183 => x"00000000",
+184 => x"72097081",
+185 => x"0509060a",
+186 => x"8106ff05",
+187 => x"70547106",
+188 => x"73097274",
+189 => x"05ff0506",
+190 => x"07515151",
+191 => x"04000000",
+192 => x"72097081",
+193 => x"0509060a",
+194 => x"098106ff",
+195 => x"05705471",
+196 => x"06730972",
+197 => x"7405ff05",
+198 => x"06075151",
+199 => x"51040000",
+200 => x"05ff0504",
+201 => x"00000000",
+202 => x"00000000",
+203 => x"00000000",
+204 => x"00000000",
+205 => x"00000000",
+206 => x"00000000",
+207 => x"00000000",
+208 => x"810b0b0b",
+209 => x"80cfd40c",
+210 => x"51040000",
+211 => x"00000000",
+212 => x"00000000",
+213 => x"00000000",
+214 => x"00000000",
+215 => x"00000000",
+216 => x"71810552",
+217 => x"04000000",
+218 => x"00000000",
+219 => x"00000000",
+220 => x"00000000",
+221 => x"00000000",
+222 => x"00000000",
+223 => x"00000000",
+224 => x"00000000",
+225 => x"00000000",
+226 => x"00000000",
+227 => x"00000000",
+228 => x"00000000",
+229 => x"00000000",
+230 => x"00000000",
+231 => x"00000000",
+232 => x"02840572",
+233 => x"10100552",
+234 => x"04000000",
+235 => x"00000000",
+236 => x"00000000",
+237 => x"00000000",
+238 => x"00000000",
+239 => x"00000000",
+240 => x"00000000",
+241 => x"00000000",
+242 => x"00000000",
+243 => x"00000000",
+244 => x"00000000",
+245 => x"00000000",
+246 => x"00000000",
+247 => x"00000000",
+248 => x"717105ff",
+249 => x"05715351",
+250 => x"020d0400",
+251 => x"00000000",
+252 => x"00000000",
+253 => x"00000000",
+254 => x"00000000",
+255 => x"00000000",
+256 => x"82c53f80",
+257 => x"c6d93f04",
+258 => x"10101010",
+259 => x"10101010",
+260 => x"10101010",
+261 => x"10101010",
+262 => x"10101010",
+263 => x"10101010",
+264 => x"10101010",
+265 => x"10101053",
+266 => x"51047381",
+267 => x"ff067383",
+268 => x"06098105",
+269 => x"83051010",
+270 => x"102b0772",
+271 => x"fc060c51",
+272 => x"51043c04",
+273 => x"72728072",
+274 => x"8106ff05",
+275 => x"09720605",
+276 => x"71105272",
+277 => x"0a100a53",
+278 => x"72ed3851",
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+2849 => x"00002c78",
+2850 => x"00002c80",
+2851 => x"00002c80",
+2852 => x"00002c88",
+2853 => x"00002c88",
+2854 => x"00002c90",
+2855 => x"00002c90",
+2856 => x"00002c98",
+2857 => x"00002c98",
+2858 => x"00002ca0",
+2859 => x"00002ca0",
+2860 => x"00002ca8",
+2861 => x"00002ca8",
+2862 => x"00002cb0",
+2863 => x"00002cb0",
+2864 => x"00002cb8",
+2865 => x"00002cb8",
+2866 => x"00002cc0",
+2867 => x"00002cc0",
+2868 => x"00002cc8",
+2869 => x"00002cc8",
+2870 => x"00002cd0",
+2871 => x"00002cd0",
+2872 => x"00002cd8",
+2873 => x"00002cd8",
+2874 => x"00002ce0",
+2875 => x"00002ce0",
+2876 => x"00002ce8",
+2877 => x"00002ce8",
+2878 => x"00002cf0",
+2879 => x"00002cf0",
+2880 => x"00002cf8",
+2881 => x"00002cf8",
+2882 => x"00002d00",
+2883 => x"00002d00",
+2884 => x"00002d08",
+2885 => x"00002d08",
+2886 => x"00002d10",
+2887 => x"00002d10",
+2888 => x"00002d18",
+2889 => x"00002d18",
+2890 => x"00002d20",
+2891 => x"00002d20",
+2892 => x"00002d28",
+2893 => x"00002d28",
+2894 => x"00002d30",
+2895 => x"00002d30",
+2896 => x"00002d38",
+2897 => x"00002d38",
+2898 => x"00002d40",
+2899 => x"00002d40",
+2900 => x"00002d48",
+2901 => x"00002d48",
+2902 => x"00002d50",
+2903 => x"00002d50",
+2904 => x"00002d58",
+2905 => x"00002d58",
+2906 => x"00002d60",
+2907 => x"00002d60",
+2908 => x"00002d68",
+2909 => x"00002d68",
+2910 => x"00002d70",
+2911 => x"00002d70",
+2912 => x"00002d78",
+2913 => x"00002d78",
+2914 => x"00002d80",
+2915 => x"00002d80",
+2916 => x"00002d88",
+2917 => x"00002d88",
+2918 => x"00002d90",
+2919 => x"00002d90",
+2920 => x"00002d98",
+2921 => x"00002d98",
+2922 => x"00002da0",
+2923 => x"00002da0",
+2924 => x"00002da8",
+2925 => x"00002da8",
+2926 => x"00002db0",
+2927 => x"00002db0",
+2928 => x"00002db8",
+2929 => x"00002db8",
+2930 => x"00002dc0",
+2931 => x"00002dc0",
+2932 => x"00002dc8",
+2933 => x"00002dc8",
+2934 => x"00002dd0",
+2935 => x"00002dd0",
+2936 => x"00002dd8",
+2937 => x"00002dd8",
+2938 => x"00002de0",
+2939 => x"00002de0",
+2940 => x"00002de8",
+2941 => x"00002de8",
+2942 => x"00002df0",
+2943 => x"00002df0",
+2944 => x"00002df8",
+2945 => x"00002df8",
+2946 => x"00002e00",
+2947 => x"00002e00",
+2948 => x"00002e08",
+2949 => x"00002e08",
+2950 => x"00002e10",
+2951 => x"00002e10",
+2952 => x"00002e18",
+2953 => x"00002e18",
+2954 => x"00002e20",
+2955 => x"00002e20",
+2956 => x"00002e28",
+2957 => x"00002e28",
+2958 => x"00002e30",
+2959 => x"00002e30",
+2960 => x"00002e38",
+2961 => x"00002e38",
+2962 => x"00002e40",
+2963 => x"00002e40",
+2964 => x"00002e48",
+2965 => x"00002e48",
+2966 => x"00002e50",
+2967 => x"00002e50",
+2968 => x"00002e58",
+2969 => x"00002e58",
+2970 => x"00002e60",
+2971 => x"00002e60",
+2972 => x"00002e68",
+2973 => x"00002e68",
+2974 => x"00002e70",
+2975 => x"00002e70",
+2976 => x"00002e78",
+2977 => x"00002e78",
+2978 => x"00002e80",
+2979 => x"00002e80",
+2980 => x"00002e88",
+2981 => x"00002e88",
+2982 => x"00002e90",
+2983 => x"00002e90",
+2984 => x"00002e98",
+2985 => x"00002e98",
+2986 => x"00002ea0",
+2987 => x"00002ea0",
+2988 => x"00002ea8",
+2989 => x"00002ea8",
+2990 => x"00002eb0",
+2991 => x"00002eb0",
+2992 => x"00002eb8",
+2993 => x"00002eb8",
+2994 => x"00002ec0",
+2995 => x"00002ec0",
+2996 => x"00002ec8",
+2997 => x"00002ec8",
+2998 => x"00002ed0",
+2999 => x"00002ed0",
+3000 => x"00002ed8",
+3001 => x"00002ed8",
+3002 => x"00002ee0",
+3003 => x"00002ee0",
+3004 => x"00002ee8",
+3005 => x"00002ee8",
+3006 => x"00002ef0",
+3007 => x"00002ef0",
+3008 => x"00002ef8",
+3009 => x"00002ef8",
+3010 => x"00002f00",
+3011 => x"00002f00",
+3012 => x"00002f08",
+3013 => x"00002f08",
+3014 => x"00002f10",
+3015 => x"00002f10",
+3016 => x"00002f18",
+3017 => x"00002f18",
+3018 => x"00002f20",
+3019 => x"00002f20",
+3020 => x"00002f28",
+3021 => x"00002f28",
+3022 => x"00002f30",
+3023 => x"00002f30",
+3024 => x"00002f38",
+3025 => x"00002f38",
+3026 => x"00002f40",
+3027 => x"00002f40",
+3028 => x"00002f48",
+3029 => x"00002f48",
+3030 => x"00002f50",
+3031 => x"00002f50",
+3032 => x"00002f58",
+3033 => x"00002f58",
+3034 => x"00002f60",
+3035 => x"00002f60",
+3036 => x"00002f68",
+3037 => x"00002f68",
+3038 => x"00002f70",
+3039 => x"00002f70",
+3040 => x"00002f78",
+3041 => x"00002f78",
+3042 => x"00002f80",
+3043 => x"00002f80",
+3044 => x"00002f88",
+3045 => x"00002f88",
+3046 => x"00002f90",
+3047 => x"00002f90",
+3048 => x"00002f98",
+3049 => x"00002f98",
+3050 => x"000027b8",
+3051 => x"ffffffff",
+3052 => x"00000000",
+3053 => x"ffffffff",
+3054 => x"00000000",
+	others => x"00000000"
+);
+
+begin
+
+mem_busy<=mem_readEnable; -- we're done on the cycle after we serve the read request
+
+process (clk, areset)
+begin
+		if areset = '1' then
+		elsif (clk'event and clk = '1') then
+			if (mem_writeEnable = '1') then
+				ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit)))) := mem_write;
+			end if;
+		if (mem_readEnable = '1') then
+			mem_read <= ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit))));
+		end if;
+	end if;
+end process;
+
+
+
+
+end dram_arch;
diff --git a/zpu/hdl/example_medium/sim_fpga_top.vhd b/zpu/hdl/example_medium/sim_fpga_top.vhd
index 2191889..a10da37 100644
--- a/zpu/hdl/example_medium/sim_fpga_top.vhd
+++ b/zpu/hdl/example_medium/sim_fpga_top.vhd
@@ -1,185 +1,185 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    20:15:31 04/14/05
--- Design Name:    
--- Module Name:    fpga_top - behave
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-library work;
-use work.zpu_config.all;
-
-entity fpga_top is
-end fpga_top;
-
-use work.zpupkg.all;
-
-architecture behave of fpga_top is
-
-
-signal clk : std_logic;
-
-signal	areset			: std_logic := '1';
-
-
-component  zpu_io is
-  generic (
-           log_file:       string  := "log.txt"
-          );
-  port(
-       	clk         : in std_logic;
-       	areset        : in std_logic;
-		busy : out std_logic;
-		writeEnable : in std_logic;
-		readEnable : in std_logic;
-		write	: in std_logic_vector(wordSize-1 downto 0);
-		read	: out std_logic_vector(wordSize-1 downto 0);
-		addr : in std_logic_vector(maxAddrBit downto minAddrBit)
-		);
-end component;
-
-
-
-
-
-signal			  mem_busy : std_logic;
-signal			  mem_read : std_logic_vector(wordSize-1 downto 0);
-signal			  mem_write : std_logic_vector(wordSize-1 downto 0);
-signal			  mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);
-signal			  mem_writeEnable : std_logic; 
-signal			  mem_readEnable : std_logic;
-signal			  mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
-
-signal			  enable : std_logic;
-
-signal			  dram_mem_busy : std_logic;
-signal			  dram_mem_read : std_logic_vector(wordSize-1 downto 0);
-signal			  dram_mem_write : std_logic_vector(wordSize-1 downto 0);
-signal			  dram_mem_writeEnable : std_logic; 
-signal			  dram_mem_readEnable : std_logic;
-signal			  dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
-
-
-signal	 		  io_busy : std_logic;
-
-signal			  io_mem_read : std_logic_vector(wordSize-1 downto 0);
-signal			  io_mem_writeEnable : std_logic; 
-signal			  io_mem_readEnable : std_logic;
-
-
-signal			  dram_ready : std_logic;
-signal			  io_ready : std_logic;
-signal			  io_reading : std_logic;
-
-
-signal break : std_logic;
-
-begin
-	zpu: zpu_core port map (
-		clk => clk ,
-	 	areset => areset,
-	 	enable => enable,
- 		in_mem_busy => mem_busy, 
- 		mem_read => mem_read,
- 		mem_write => mem_write, 
-		out_mem_addr => mem_addr, 
-		out_mem_writeEnable => mem_writeEnable,  
-		out_mem_readEnable => mem_readEnable,
- 		mem_writeMask => mem_writeMask, 
- 		interrupt => '0',
- 		break  => break);
-
-	dram_imp: dram port map (
-		clk => clk ,
-		areset => areset,
- 		mem_busy => dram_mem_busy, 
- 		mem_read => dram_mem_read,
- 		mem_write => mem_write, 
-		mem_addr => mem_addr(maxAddrBit downto 0), 
-		mem_writeEnable => dram_mem_writeEnable,  
-		mem_readEnable => dram_mem_readEnable,
- 		mem_writeMask => mem_writeMask);
-
-
-	ioMap: zpu_io port map (
-       	clk => clk,
-	 	areset => areset,
-		busy => io_busy,
-		writeEnable => io_mem_writeEnable,
-		readEnable => io_mem_readEnable,
-		write	=> mem_write(wordSize-1 downto 0),
-		read	=> io_mem_read,
-		addr => mem_addr(maxAddrBit downto minAddrBit)
-	);
-
-	dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit);
-	dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit);
-	io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit);
-	io_mem_readEnable <= mem_readEnable and mem_addr(ioBit);
-	mem_busy <= io_busy or dram_mem_busy or io_busy;
-	
-	
-
-	-- Memory reads either come from IO or DRAM. We need to pick the right one.
-	memorycontrol:
-	process(dram_mem_read, dram_ready, io_ready, io_mem_read)
-	begin
-		mem_read <= (others => 'U');
-		if dram_ready='1' then
-			mem_read <= dram_mem_read;
-		end if;
-			 
-		if io_ready='1' then
-			mem_read <= io_mem_read;
-		end if;
-	end process;
-
-	
-	io_ready <= (io_reading or io_mem_readEnable) and not io_busy;
-
-	memoryControlSync:
-	process(clk, areset)
-	begin
-		if areset = '1' then
-			enable <= '0';
-			io_reading <= '0';
-			dram_ready <= '0';
-		elsif (clk'event and clk = '1') then
-			enable <= '1';
-			io_reading <= io_busy or io_mem_readEnable; 
-			dram_ready<=dram_mem_readEnable;
-			
-		end if;
-	end process;
-
-	-- wiggle the clock @ 100MHz
-	clock : PROCESS
-	   begin
-   			clk <= '0';
-		   wait for 5 ns; 
-   			clk <= '1';
-		   wait for 5 ns; 
-		   areset <= '0';
-	end PROCESS clock;
-
-
-end behave;
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:    20:15:31 04/14/05
+-- Design Name:    
+-- Module Name:    fpga_top - behave
+-- Project Name:   
+-- Target Device:  
+-- Tool versions:  
+-- Description:
+--
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+library work;
+use work.zpu_config.all;
+
+entity fpga_top is
+end fpga_top;
+
+use work.zpupkg.all;
+
+architecture behave of fpga_top is
+
+
+signal clk : std_logic;
+
+signal	areset			: std_logic := '1';
+
+
+component  zpu_io is
+  generic (
+           log_file:       string  := "log.txt"
+          );
+  port(
+       	clk         : in std_logic;
+       	areset        : in std_logic;
+		busy : out std_logic;
+		writeEnable : in std_logic;
+		readEnable : in std_logic;
+		write	: in std_logic_vector(wordSize-1 downto 0);
+		read	: out std_logic_vector(wordSize-1 downto 0);
+		addr : in std_logic_vector(maxAddrBit downto minAddrBit)
+		);
+end component;
+
+
+
+
+
+signal			  mem_busy : std_logic;
+signal			  mem_read : std_logic_vector(wordSize-1 downto 0);
+signal			  mem_write : std_logic_vector(wordSize-1 downto 0);
+signal			  mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);
+signal			  mem_writeEnable : std_logic; 
+signal			  mem_readEnable : std_logic;
+signal			  mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
+
+signal			  enable : std_logic;
+
+signal			  dram_mem_busy : std_logic;
+signal			  dram_mem_read : std_logic_vector(wordSize-1 downto 0);
+signal			  dram_mem_write : std_logic_vector(wordSize-1 downto 0);
+signal			  dram_mem_writeEnable : std_logic; 
+signal			  dram_mem_readEnable : std_logic;
+signal			  dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
+
+
+signal	 		  io_busy : std_logic;
+
+signal			  io_mem_read : std_logic_vector(wordSize-1 downto 0);
+signal			  io_mem_writeEnable : std_logic; 
+signal			  io_mem_readEnable : std_logic;
+
+
+signal			  dram_ready : std_logic;
+signal			  io_ready : std_logic;
+signal			  io_reading : std_logic;
+
+
+signal break : std_logic;
+
+begin
+	zpu: zpu_core port map (
+		clk => clk ,
+	 	areset => areset,
+	 	enable => enable,
+ 		in_mem_busy => mem_busy, 
+ 		mem_read => mem_read,
+ 		mem_write => mem_write, 
+		out_mem_addr => mem_addr, 
+		out_mem_writeEnable => mem_writeEnable,  
+		out_mem_readEnable => mem_readEnable,
+ 		mem_writeMask => mem_writeMask, 
+ 		interrupt => '0',
+ 		break  => break);
+
+	dram_imp: dram port map (
+		clk => clk ,
+		areset => areset,
+ 		mem_busy => dram_mem_busy, 
+ 		mem_read => dram_mem_read,
+ 		mem_write => mem_write, 
+		mem_addr => mem_addr(maxAddrBit downto 0), 
+		mem_writeEnable => dram_mem_writeEnable,  
+		mem_readEnable => dram_mem_readEnable,
+ 		mem_writeMask => mem_writeMask);
+
+
+	ioMap: zpu_io port map (
+       	clk => clk,
+	 	areset => areset,
+		busy => io_busy,
+		writeEnable => io_mem_writeEnable,
+		readEnable => io_mem_readEnable,
+		write	=> mem_write(wordSize-1 downto 0),
+		read	=> io_mem_read,
+		addr => mem_addr(maxAddrBit downto minAddrBit)
+	);
+
+	dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit);
+	dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit);
+	io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit);
+	io_mem_readEnable <= mem_readEnable and mem_addr(ioBit);
+	mem_busy <= io_busy or dram_mem_busy or io_busy;
+	
+	
+
+	-- Memory reads either come from IO or DRAM. We need to pick the right one.
+	memorycontrol:
+	process(dram_mem_read, dram_ready, io_ready, io_mem_read)
+	begin
+		mem_read <= (others => 'U');
+		if dram_ready='1' then
+			mem_read <= dram_mem_read;
+		end if;
+			 
+		if io_ready='1' then
+			mem_read <= io_mem_read;
+		end if;
+	end process;
+
+	
+	io_ready <= (io_reading or io_mem_readEnable) and not io_busy;
+
+	memoryControlSync:
+	process(clk, areset)
+	begin
+		if areset = '1' then
+			enable <= '0';
+			io_reading <= '0';
+			dram_ready <= '0';
+		elsif (clk'event and clk = '1') then
+			enable <= '1';
+			io_reading <= io_busy or io_mem_readEnable; 
+			dram_ready<=dram_mem_readEnable;
+			
+		end if;
+	end process;
+
+	-- wiggle the clock @ 100MHz
+	clock : PROCESS
+	   begin
+   			clk <= '0';
+		   wait for 5 ns; 
+   			clk <= '1';
+		   wait for 5 ns; 
+		   areset <= '0';
+	end PROCESS clock;
+
+
+end behave;
diff --git a/zpu/hdl/example_medium/zpu_config_trace.vhd b/zpu/hdl/example_medium/zpu_config_trace.vhd
index d765d9a..a5b9192 100644
--- a/zpu/hdl/example_medium/zpu_config_trace.vhd
+++ b/zpu/hdl/example_medium/zpu_config_trace.vhd
@@ -1,17 +1,17 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-package zpu_config is
-
-	constant	Generate_Trace		: boolean := true;
-	constant 	wordPower			: integer := 5;
-	-- during simulation, set this to '0' to get matching trace.txt 
-	constant	DontCareValue		: std_logic := '0';
-	-- Clock frequency in MHz.
-	constant	ZPU_Frequency		: std_logic_vector(7 downto 0) := x"64";
-	constant 	maxAddrBitIncIO		: integer := 27;
-	constant 	maxAddrBitDRAM		: integer := 16;
-	constant 	maxAddrBitBRAM		: integer := 16;
-	constant 	spStart				: std_logic_vector(maxAddrBitIncIO downto 0) := x"001fff8"; 	
-	
-end zpu_config;
+library ieee;
+use ieee.std_logic_1164.all;
+
+package zpu_config is
+
+	constant	Generate_Trace		: boolean := true;
+	constant 	wordPower			: integer := 5;
+	-- during simulation, set this to '0' to get matching trace.txt 
+	constant	DontCareValue		: std_logic := '0';
+	-- Clock frequency in MHz.
+	constant	ZPU_Frequency		: std_logic_vector(7 downto 0) := x"64";
+	constant 	maxAddrBitIncIO		: integer := 27;
+	constant 	maxAddrBitDRAM		: integer := 16;
+	constant 	maxAddrBitBRAM		: integer := 16;
+	constant 	spStart				: std_logic_vector(maxAddrBitIncIO downto 0) := x"001fff8"; 	
+	
+end zpu_config;
diff --git a/zpu/hdl/wishbone/wishbone_pkg.vhd b/zpu/hdl/wishbone/wishbone_pkg.vhd
index 97240de..b6d30ee 100644
--- a/zpu/hdl/wishbone/wishbone_pkg.vhd
+++ b/zpu/hdl/wishbone/wishbone_pkg.vhd
@@ -1,86 +1,86 @@
--- ZPU
---
--- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
--- 
--- The FreeBSD license
--- 
--- Redistribution and use in source and binary forms, with or without
--- modification, are permitted provided that the following conditions
--- are met:
--- 
--- 1. Redistributions of source code must retain the above copyright
---    notice, this list of conditions and the following disclaimer.
--- 2. Redistributions in binary form must reproduce the above
---    copyright notice, this list of conditions and the following
---    disclaimer in the documentation and/or other materials
---    provided with the distribution.
--- 
--- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
--- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
--- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
--- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
--- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
--- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
--- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
--- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
--- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
--- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--- 
--- The views and conclusions contained in the software and documentation
--- are those of the authors and should not be interpreted as representing
--- official policies, either expressed or implied, of the ZPU Project.
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-package wishbone_pkg is
-
-	type wishbone_bus_in is record
-		adr			: std_logic_vector(31 downto 0); 
-		sel			: std_logic_vector(3 downto 0); 
-		we			: std_logic;
-		dat			: std_logic_vector(31 downto 0); 	-- Note! Data written with 'we'
-		cyc			: std_logic; 
-		stb			: std_logic;
-	end record;
-
-	type wishbone_bus_out is record
-		dat		: std_logic_vector(31 downto 0);
-		ack			: std_logic;
-	end record;
-	
-	type wishbone_bus is record
-		insig		: wishbone_bus_in;
-		outsig  	: wishbone_bus_out;
-	end record;
-
-	component atomic32_access is
-	port (	cpu_clk			: in std_logic;
-			areset			: in std_logic;
-	
-			-- Wishbone from CPU interface
-			wb_16_i			: in wishbone_bus_in;
-			wb_16_o     	: out wishbone_bus_out;
-			-- Wishbone to FPGA registers and ethernet core
-			wb_32_i			: in wishbone_bus_out;
-			wb_32_o			: out wishbone_bus_in);
-	end component;
-	
-	component eth_access_corr is
-	port (	cpu_clk			: in std_logic;
-			areset			: in std_logic;
-	
-			-- Wishbone from Wishbone MUX
-			eth_raw_o		: out wishbone_bus_out;
-			eth_raw_i		: in wishbone_bus_in;
-			
-			-- Wishbone ethernet core
-			eth_slave_i 	: in wishbone_bus_out;
-			eth_slave_o		: out wishbone_bus_in);
-	end component;
-
-
-end wishbone_pkg;
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+package wishbone_pkg is
+
+	type wishbone_bus_in is record
+		adr			: std_logic_vector(31 downto 0); 
+		sel			: std_logic_vector(3 downto 0); 
+		we			: std_logic;
+		dat			: std_logic_vector(31 downto 0); 	-- Note! Data written with 'we'
+		cyc			: std_logic; 
+		stb			: std_logic;
+	end record;
+
+	type wishbone_bus_out is record
+		dat		: std_logic_vector(31 downto 0);
+		ack			: std_logic;
+	end record;
+	
+	type wishbone_bus is record
+		insig		: wishbone_bus_in;
+		outsig  	: wishbone_bus_out;
+	end record;
+
+	component atomic32_access is
+	port (	cpu_clk			: in std_logic;
+			areset			: in std_logic;
+	
+			-- Wishbone from CPU interface
+			wb_16_i			: in wishbone_bus_in;
+			wb_16_o     	: out wishbone_bus_out;
+			-- Wishbone to FPGA registers and ethernet core
+			wb_32_i			: in wishbone_bus_out;
+			wb_32_o			: out wishbone_bus_in);
+	end component;
+	
+	component eth_access_corr is
+	port (	cpu_clk			: in std_logic;
+			areset			: in std_logic;
+	
+			-- Wishbone from Wishbone MUX
+			eth_raw_o		: out wishbone_bus_out;
+			eth_raw_i		: in wishbone_bus_in;
+			
+			-- Wishbone ethernet core
+			eth_slave_i 	: in wishbone_bus_out;
+			eth_slave_o		: out wishbone_bus_in);
+	end component;
+
+
+end wishbone_pkg;
diff --git a/zpu/hdl/wishbone/zpu_system.vhd b/zpu/hdl/wishbone/zpu_system.vhd
index 5b95a80..07c5bdc 100644
--- a/zpu/hdl/wishbone/zpu_system.vhd
+++ b/zpu/hdl/wishbone/zpu_system.vhd
@@ -1,104 +1,104 @@
--- ZPU
---
--- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
--- 
--- The FreeBSD license
--- 
--- Redistribution and use in source and binary forms, with or without
--- modification, are permitted provided that the following conditions
--- are met:
--- 
--- 1. Redistributions of source code must retain the above copyright
---    notice, this list of conditions and the following disclaimer.
--- 2. Redistributions in binary form must reproduce the above
---    copyright notice, this list of conditions and the following
---    disclaimer in the documentation and/or other materials
---    provided with the distribution.
--- 
--- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
--- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
--- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
--- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
--- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
--- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
--- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
--- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
--- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
--- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--- 
--- The views and conclusions contained in the software and documentation
--- are those of the authors and should not be interpreted as representing
--- official policies, either expressed or implied, of the ZPU Project.
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_UNSIGNED.all; 
-
-library work;
-use work.wishbone_pkg.all;
-use work.zpupkg.all;
-use work.zpu_config.all;
-
-entity zpu_system is
-	generic(
-			simulate		: boolean := false);
-	port (	areset			: in std_logic;
-			cpu_clk			: in std_logic;
-
-			-- ZPU Control signals
-			enable			: in std_logic;
-			interrupt		: in std_logic;
-
-			zpu_status		: out std_logic_vector(63 downto 0);
-
-			-- wishbone interfaces
-			zpu_wb_i		: in wishbone_bus_out;
-			zpu_wb_o		: out wishbone_bus_in);
-end zpu_system;
-
-architecture behave of zpu_system is
-
-signal	mem_req					: std_logic;
-signal	mem_we 					: std_logic;
-signal	mem_ack 				: std_logic; 
-signal	mem_read 				: std_logic_vector(wordSize-1 downto 0);
-signal	mem_write 				: std_logic_vector(wordSize-1 downto 0);
-signal	out_mem_addr 			: std_logic_vector(maxAddrBitIncIO downto 0);
-signal	mem_writeMask			: std_logic_vector(wordBytes-1 downto 0);
-
-
-begin
-
-	my_zpu_core:
-	zpu_core port map (
-    	clk 				=> cpu_clk, 
-		areset 				=> areset,
-	 	enable 				=> enable,
-	  	mem_req 			=> mem_req,
-	 	mem_we 				=> mem_we,
-	 	mem_ack 			=> mem_ack, 
-	 	mem_read 			=> mem_read,
-	 	mem_write 			=> mem_write,
-		out_mem_addr 		=> out_mem_addr,
-	 	mem_writeMask		=> mem_writeMask,
-	 	interrupt			=> interrupt,
-	 	zpu_status			=> zpu_status,
-	 	break				=> open);
-
-	my_zpu_wb_bridge:
-	zpu_wb_bridge port map (
-		clk 				=> cpu_clk,
-	 	areset 				=> areset,
-	  	mem_req 			=> mem_req,
-	 	mem_we 				=> mem_we,
-	 	mem_ack 			=> mem_ack, 
-	 	mem_read 			=> mem_read,
-	 	mem_write 			=> mem_write,
-		out_mem_addr 		=> out_mem_addr,
-	 	mem_writeMask		=> mem_writeMask,
-		zpu_wb_i			=> zpu_wb_i,
-		zpu_wb_o			=> zpu_wb_o);
-
-end behave;
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.all; 
+
+library work;
+use work.wishbone_pkg.all;
+use work.zpupkg.all;
+use work.zpu_config.all;
+
+entity zpu_system is
+	generic(
+			simulate		: boolean := false);
+	port (	areset			: in std_logic;
+			cpu_clk			: in std_logic;
+
+			-- ZPU Control signals
+			enable			: in std_logic;
+			interrupt		: in std_logic;
+
+			zpu_status		: out std_logic_vector(63 downto 0);
+
+			-- wishbone interfaces
+			zpu_wb_i		: in wishbone_bus_out;
+			zpu_wb_o		: out wishbone_bus_in);
+end zpu_system;
+
+architecture behave of zpu_system is
+
+signal	mem_req					: std_logic;
+signal	mem_we 					: std_logic;
+signal	mem_ack 				: std_logic; 
+signal	mem_read 				: std_logic_vector(wordSize-1 downto 0);
+signal	mem_write 				: std_logic_vector(wordSize-1 downto 0);
+signal	out_mem_addr 			: std_logic_vector(maxAddrBitIncIO downto 0);
+signal	mem_writeMask			: std_logic_vector(wordBytes-1 downto 0);
+
+
+begin
+
+	my_zpu_core:
+	zpu_core port map (
+    	clk 				=> cpu_clk, 
+		areset 				=> areset,
+	 	enable 				=> enable,
+	  	mem_req 			=> mem_req,
+	 	mem_we 				=> mem_we,
+	 	mem_ack 			=> mem_ack, 
+	 	mem_read 			=> mem_read,
+	 	mem_write 			=> mem_write,
+		out_mem_addr 		=> out_mem_addr,
+	 	mem_writeMask		=> mem_writeMask,
+	 	interrupt			=> interrupt,
+	 	zpu_status			=> zpu_status,
+	 	break				=> open);
+
+	my_zpu_wb_bridge:
+	zpu_wb_bridge port map (
+		clk 				=> cpu_clk,
+	 	areset 				=> areset,
+	  	mem_req 			=> mem_req,
+	 	mem_we 				=> mem_we,
+	 	mem_ack 			=> mem_ack, 
+	 	mem_read 			=> mem_read,
+	 	mem_write 			=> mem_write,
+		out_mem_addr 		=> out_mem_addr,
+	 	mem_writeMask		=> mem_writeMask,
+		zpu_wb_i			=> zpu_wb_i,
+		zpu_wb_o			=> zpu_wb_o);
+
+end behave;
diff --git a/zpu/hdl/wishbone/zpu_wb_bridge.vhd b/zpu/hdl/wishbone/zpu_wb_bridge.vhd
index 226d839..086ae11 100644
--- a/zpu/hdl/wishbone/zpu_wb_bridge.vhd
+++ b/zpu/hdl/wishbone/zpu_wb_bridge.vhd
@@ -1,83 +1,83 @@
--- ZPU
---
--- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
--- 
--- The FreeBSD license
--- 
--- Redistribution and use in source and binary forms, with or without
--- modification, are permitted provided that the following conditions
--- are met:
--- 
--- 1. Redistributions of source code must retain the above copyright
---    notice, this list of conditions and the following disclaimer.
--- 2. Redistributions in binary form must reproduce the above
---    copyright notice, this list of conditions and the following
---    disclaimer in the documentation and/or other materials
---    provided with the distribution.
--- 
--- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
--- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
--- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
--- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
--- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
--- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
--- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
--- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
--- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
--- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--- 
--- The views and conclusions contained in the software and documentation
--- are those of the authors and should not be interpreted as representing
--- official policies, either expressed or implied, of the ZPU Project.
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library work;
-use work.phi_config.all;
-use work.wishbone_pkg.all;
-use work.zpupkg.all;
-use work.zpu_config.all;
-
-entity zpu_wb_bridge is
-	port (	-- Native ZPU interface
- 			clk 				: in std_logic;
-	 		areset 				: in std_logic;
-
-	 		mem_req 			: in std_logic;
-	 		mem_we				: in std_logic;
-	 		mem_ack				: out std_logic; 
-	 		mem_read 			: out std_logic_vector(wordSize-1 downto 0);
-	 		mem_write 			: in std_logic_vector(wordSize-1 downto 0);
-			out_mem_addr 		: in std_logic_vector(maxAddrBitIncIO downto 0);
-	 		mem_writeMask		: in std_logic_vector(wordBytes-1 downto 0);
-			
-			-- Wishbone from ZPU
-			zpu_wb_i			: in wishbone_bus_out;
-			zpu_wb_o			: out wishbone_bus_in);
-
-end zpu_wb_bridge;
-
-architecture behave of zpu_wb_bridge is
-
-begin
-
-	mem_read <= zpu_wb_i.dat;
-	mem_ack <= zpu_wb_i.ack;
-	
-	zpu_wb_o.adr <= "000000" & out_mem_addr(27) & out_mem_addr(24 downto 0);
-	zpu_wb_o.dat <= mem_write;
-	zpu_wb_o.sel <= mem_writeMask;
-	zpu_wb_o.stb <= mem_req;
-	zpu_wb_o.cyc <= mem_req;
-	zpu_wb_o.we <= mem_we;
-
-end behave;
-
-			
-
-	
-
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library work;
+use work.phi_config.all;
+use work.wishbone_pkg.all;
+use work.zpupkg.all;
+use work.zpu_config.all;
+
+entity zpu_wb_bridge is
+	port (	-- Native ZPU interface
+ 			clk 				: in std_logic;
+	 		areset 				: in std_logic;
+
+	 		mem_req 			: in std_logic;
+	 		mem_we				: in std_logic;
+	 		mem_ack				: out std_logic; 
+	 		mem_read 			: out std_logic_vector(wordSize-1 downto 0);
+	 		mem_write 			: in std_logic_vector(wordSize-1 downto 0);
+			out_mem_addr 		: in std_logic_vector(maxAddrBitIncIO downto 0);
+	 		mem_writeMask		: in std_logic_vector(wordBytes-1 downto 0);
+			
+			-- Wishbone from ZPU
+			zpu_wb_i			: in wishbone_bus_out;
+			zpu_wb_o			: out wishbone_bus_in);
+
+end zpu_wb_bridge;
+
+architecture behave of zpu_wb_bridge is
+
+begin
+
+	mem_read <= zpu_wb_i.dat;
+	mem_ack <= zpu_wb_i.ack;
+	
+	zpu_wb_o.adr <= "000000" & out_mem_addr(27) & out_mem_addr(24 downto 0);
+	zpu_wb_o.dat <= mem_write;
+	zpu_wb_o.sel <= mem_writeMask;
+	zpu_wb_o.stb <= mem_req;
+	zpu_wb_o.cyc <= mem_req;
+	zpu_wb_o.we <= mem_we;
+
+end behave;
+
+			
+
+	
+
diff --git a/zpu/hdl/zpu4/core/zpu_config.vhd b/zpu/hdl/zpu4/core/zpu_config.vhd
index 112dd01..5b3110c 100644
--- a/zpu/hdl/zpu4/core/zpu_config.vhd
+++ b/zpu/hdl/zpu4/core/zpu_config.vhd
@@ -1,44 +1,44 @@
--- ZPU
---
--- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
--- 
--- The FreeBSD license
--- 
--- Redistribution and use in source and binary forms, with or without
--- modification, are permitted provided that the following conditions
--- are met:
--- 
--- 1. Redistributions of source code must retain the above copyright
---    notice, this list of conditions and the following disclaimer.
--- 2. Redistributions in binary form must reproduce the above
---    copyright notice, this list of conditions and the following
---    disclaimer in the documentation and/or other materials
---    provided with the distribution.
--- 
--- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
--- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
--- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
--- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
--- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
--- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
--- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
--- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
--- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
--- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--- 
--- The views and conclusions contained in the software and documentation
--- are those of the authors and should not be interpreted as representing
--- official policies, either expressed or implied, of the ZPU Project.
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.std_logic_arith.all;
-
-package zpu_config is
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+
+package zpu_config is
 
   -- generate trace output or not.
   constant Generate_Trace  : boolean                      := false;
@@ -56,4 +56,4 @@ package zpu_config is
   constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) :=
     conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1);
 
-end zpu_config;
+end zpu_config;
diff --git a/zpu/hdl/zpu4/core/zpu_core.vhd b/zpu/hdl/zpu4/core/zpu_core.vhd
index ff9449f..e2e4781 100644
--- a/zpu/hdl/zpu4/core/zpu_core.vhd
+++ b/zpu/hdl/zpu4/core/zpu_core.vhd
@@ -1,68 +1,68 @@
--- ZPU
---
--- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
--- Copyright 2008 alvieboy - Álvaro Lopes - alvieboy@alvie.com
--- 
--- The FreeBSD license
--- 
--- Redistribution and use in source and binary forms, with or without
--- modification, are permitted provided that the following conditions
--- are met:
--- 
--- 1. Redistributions of source code must retain the above copyright
---    notice, this list of conditions and the following disclaimer.
--- 2. Redistributions in binary form must reproduce the above
---    copyright notice, this list of conditions and the following
---    disclaimer in the documentation and/or other materials
---    provided with the distribution.
--- 
--- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
--- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
--- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
--- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
--- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
--- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
--- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
--- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
--- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
--- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--- 
--- The views and conclusions contained in the software and documentation
--- are those of the authors and should not be interpreted as representing
--- official policies, either expressed or implied, of the ZPU Project.
-
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+-- Copyright 2008 alvieboy - Álvaro Lopes - alvieboy@alvie.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
 library ieee;
 use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.zpu_config.all;
-use work.zpupkg.all;
-
-
--- mem_writeEnable - set to '1' for a single cycle to send off a write request.
---                   mem_write is valid only while mem_writeEnable='1'.
--- mem_readEnable - set to '1' for a single cycle to send off a read request.
--- 
--- mem_busy - It is illegal to send off a read/write request when mem_busy='1'.
---            Set to '0' when mem_read  is valid after a read request.
---            If it goes to '1'(busy), it is on the cycle after mem_read/writeEnable
---            is '1'.
--- mem_addr - address for read/write request
--- mem_read - read data. Valid only on the cycle after mem_busy='0' after 
---            mem_readEnable='1' for a single cycle.
--- mem_write - data to write
--- mem_writeMask - set to '1' for those bits that are to be written to memory upon
---                 write request
--- break - set to '1' when CPU hits break instruction
--- interrupt - set to '1' until interrupts are cleared by CPU. 
-
-
-
-
-entity zpu_core is
+use ieee.numeric_std.all;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+
+-- mem_writeEnable - set to '1' for a single cycle to send off a write request.
+--                   mem_write is valid only while mem_writeEnable='1'.
+-- mem_readEnable - set to '1' for a single cycle to send off a read request.
+-- 
+-- mem_busy - It is illegal to send off a read/write request when mem_busy='1'.
+--            Set to '0' when mem_read  is valid after a read request.
+--            If it goes to '1'(busy), it is on the cycle after mem_read/writeEnable
+--            is '1'.
+-- mem_addr - address for read/write request
+-- mem_read - read data. Valid only on the cycle after mem_busy='0' after 
+--            mem_readEnable='1' for a single cycle.
+-- mem_write - data to write
+-- mem_writeMask - set to '1' for those bits that are to be written to memory upon
+--                 write request
+-- break - set to '1' when CPU hits break instruction
+-- interrupt - set to '1' until interrupts are cleared by CPU. 
+
+
+
+
+entity zpu_core is
   port (
     clk                 : in  std_logic;
     areset              : in  std_logic;
@@ -77,10 +77,10 @@ entity zpu_core is
     interrupt           : in  std_logic;
     break               : out std_logic
     );
-end zpu_core;
-
-architecture behave of zpu_core is
-
+end zpu_core;
+
+architecture behave of zpu_core is
+
   type InsnType is (
     State_AddTop,
     State_Dup,
@@ -196,12 +196,12 @@ architecture behave of zpu_core is
   signal trace_sp          : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
   signal trace_topOfStack  : std_logic_vector(wordSize-1 downto 0);
   signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0);
-
--- state machine.
-
-begin
-
-
+
+-- state machine.
+
+begin
+
+
   traceFileGenerate :
   if Generate_Trace generate
     trace_file : trace port map (
@@ -1009,7 +1009,7 @@ begin
       end case; -- state
     end if; -- clk'event
   end process;
-
-
-
-end behave;
+
+
+
+end behave;
diff --git a/zpu/hdl/zpu4/core/zpu_core_small.vhd b/zpu/hdl/zpu4/core/zpu_core_small.vhd
index 1df9546..757d056 100644
--- a/zpu/hdl/zpu4/core/zpu_core_small.vhd
+++ b/zpu/hdl/zpu4/core/zpu_core_small.vhd
@@ -1,47 +1,47 @@
--- ZPU
---
--- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
--- 
--- The FreeBSD license
--- 
--- Redistribution and use in source and binary forms, with or without
--- modification, are permitted provided that the following conditions
--- are met:
--- 
--- 1. Redistributions of source code must retain the above copyright
---    notice, this list of conditions and the following disclaimer.
--- 2. Redistributions in binary form must reproduce the above
---    copyright notice, this list of conditions and the following
---    disclaimer in the documentation and/or other materials
---    provided with the distribution.
--- 
--- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
--- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
--- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
--- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
--- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
--- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
--- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
--- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
--- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
--- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--- 
--- The views and conclusions contained in the software and documentation
--- are those of the authors and should not be interpreted as representing
--- official policies, either expressed or implied, of the ZPU Project.
-
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
 library ieee;
 use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.zpu_config.all;
-use work.zpupkg.all;
-
-
-entity zpu_core is
+use ieee.numeric_std.all;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+
+entity zpu_core is
   port ( 
     clk                 : in std_logic;
     -- asynchronous reset signal
@@ -67,12 +67,12 @@ entity zpu_core is
     -- in simulation to stop simulation
     break               : out std_logic
     );
-end zpu_core;
-
-
-
+end zpu_core;
+
+
+
 architecture behave of zpu_core is
-
+
   signal memAWriteEnable : std_logic;
   signal memAAddr        : unsigned(maxAddrBit downto minAddrBit);
   signal memAWrite       : unsigned(wordSize-1 downto 0);
@@ -171,11 +171,11 @@ architecture behave of zpu_core is
   signal  tOpcode_sel        : index;
   --
   signal  inInterrupt        : std_logic;
-
-
-
-begin
-
+
+
+
+begin
+
   -- generate a trace file.
   -- 
   -- This is only used in simulation to see what instructions are
@@ -596,7 +596,7 @@ begin
       
     end if;  -- reset, enable
   end process;
-
-
-
-end behave;
+
+
+
+end behave;
diff --git a/zpu/hdl/zpu4/core/zpupkg.vhd b/zpu/hdl/zpu4/core/zpupkg.vhd
index f6823f5..a6e749d 100644
--- a/zpu/hdl/zpu4/core/zpupkg.vhd
+++ b/zpu/hdl/zpu4/core/zpupkg.vhd
@@ -1,47 +1,47 @@
--- ZPU
---
--- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
--- 
--- The FreeBSD license
--- 
--- Redistribution and use in source and binary forms, with or without
--- modification, are permitted provided that the following conditions
--- are met:
--- 
--- 1. Redistributions of source code must retain the above copyright
---    notice, this list of conditions and the following disclaimer.
--- 2. Redistributions in binary form must reproduce the above
---    copyright notice, this list of conditions and the following
---    disclaimer in the documentation and/or other materials
---    provided with the distribution.
--- 
--- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
--- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
--- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
--- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
--- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
--- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
--- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
--- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
--- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
--- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--- 
--- The views and conclusions contained in the software and documentation
--- are those of the authors and should not be interpreted as representing
--- official policies, either expressed or implied, of the ZPU Project.
-
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
 library ieee;
 use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.zpu_config.all;
-
-
-package zpupkg is
-
+use ieee.numeric_std.all;
+
+library work;
+use work.zpu_config.all;
+
+
+package zpupkg is
+
   -- This bit is set for read/writes to IO
   -- FIX!!! eventually this should be set to wordSize-1 so as to
   -- to make the address of IO independent of amount of memory
@@ -215,4 +215,4 @@ package zpupkg is
 
 
   
-end zpupkg;
+end zpupkg;
diff --git a/zpu/hdl/zpu4/src/clocks.vhd b/zpu/hdl/zpu4/src/clocks.vhd
index a352b3c..704d790 100644
--- a/zpu/hdl/zpu4/src/clocks.vhd
+++ b/zpu/hdl/zpu4/src/clocks.vhd
@@ -1,246 +1,246 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library UNISIM;
-use UNISIM.vcomponents.all;
-
-entity clocks is
-	port (	areset			: in std_logic;
-			cpu_clk_p		: in std_logic;
-			sdr_clk_fb_p	: in std_logic;
-			cpu_clk			: out std_logic;
-			cpu_clk_2x		: out std_logic;
-			cpu_clk_4x		: out std_logic;
-			ddr_in_clk		: out std_logic;
-			ddr_in_clk_2x	: out std_logic;
-			locked			: out std_logic_vector(2 downto 0));
-end clocks;
-
-architecture behave of clocks is
-
-signal	low					: std_logic;
-
-signal	cpu_clk_in			: std_logic;
-signal	sdr_clk_fb_in		: std_logic;
-
-signal	dcm_cpu1			: std_logic;
-signal	dcm_cpu2			: std_logic;
-signal	dcm_cpu2_dum		: std_logic;
-signal	dcm_cpu4			: std_logic;
-signal	dcm_ddr2			: std_logic;
-signal	dcm_ddr2_2x			: std_logic;
-
-signal	cpu_clk_int			: std_logic;
-signal	cpu_clk_2x_int		: std_logic;
-signal	cpu_clk_2x_dum_int	: std_logic;
-signal	cpu_clk_4x_int		: std_logic;
-signal	ddr_in_clk_int		: std_logic;
-signal	ddr_in_clk_2x_int	: std_logic;
-
-signal	dcm1_locked_del		: std_logic;
-signal	dcm2_locked_del		: std_logic;
-signal	dcm2_reset			: std_logic;
-signal	dcm3_reset			: std_logic;
-
-signal	locked_int			: std_logic_vector(2 downto 0);
-signal	del_addr			: std_logic_vector(3 downto 0);
-
-begin
-
-	low <= '0';				
-	del_addr <= "1111";
-	
-	cpu_clk <= cpu_clk_int;
-	cpu_clk_2x <= cpu_clk_2x_int;
-	cpu_clk_4x <= cpu_clk_4x_int;
-	ddr_in_clk <= ddr_in_clk_int;
-	ddr_in_clk_2x <= ddr_in_clk_2x_int;
-	locked <= locked_int;
-	
-
-   	CPU_IBUFG: 
-   	IBUFG port map (
-      	O => cpu_clk_in,
-      	I => cpu_clk_p);
-	
-   	SDR_FB_IBUFG: 
-   	IBUFG port map (
-      	O => sdr_clk_fb_in,
-      	I => sdr_clk_fb_p);
-      	
-   dcm2_rst: 
-   SRL16 generic map (
-      	INIT => X"0000")
-   port map (
-      	Q => dcm1_locked_del,
-      	A0 => del_addr(0),
-      	A1 => del_addr(1),
-      	A2 => del_addr(2),
-      	A3 => del_addr(3),
-      	CLK => cpu_clk_int,
-      	D => locked_int(0));
-      	
-	dcm2_reset <= not(dcm1_locked_del);      	
-	
-   dcm3_rst: 
-   SRL16 generic map (
-      	INIT => X"0000")
-   port map (
-      	Q => dcm2_locked_del,
-      	A0 => del_addr(0),
-      	A1 => del_addr(1),
-      	A2 => del_addr(2),
-      	A3 => del_addr(3),
-      	CLK => cpu_clk_int,
-      	D => locked_int(1));
-      	
-	dcm3_reset <= not(dcm2_locked_del);      	
-	
-   	cpu1_dcm: 
-   	DCM generic map (
-      	CLKDV_DIVIDE => 2.0, --  Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-                           --     7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
-      	CLKFX_DIVIDE => 1,   --  Can be any interger from 1 to 32
-      	CLKFX_MULTIPLY => 4, --  Can be any integer from 1 to 32
-      	CLKIN_DIVIDE_BY_2 => FALSE, --  TRUE/FALSE to enable CLKIN divide by two feature
-      	CLKIN_PERIOD => 15.625,          --  Specify period of input clock
-      	CLKOUT_PHASE_SHIFT => "NONE", --  Specify phase shift of NONE, FIXED or VARIABLE
-      	CLK_FEEDBACK => "1X",         --  Specify clock feedback of NONE, 1X or 2X
-      	DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", --  SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-                                             --     an integer from 0 to 15
-      	DFS_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for frequency synthesis
-      	DLL_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for DLL
-      	DUTY_CYCLE_CORRECTION => TRUE, --  Duty cycle correction, TRUE or FALSE
-      	FACTORY_JF => X"8080",          --  FACTORY JF Values
-      	PHASE_SHIFT => 0,        --  Amount of fixed phase shift from -255 to 255
-      	STARTUP_WAIT => FALSE) --  Delay configuration DONE until DCM LOCK, TRUE/FALSE
-   	port map (
-      	CLK0 => dcm_cpu1,   -- 0 degree DCM CLK ouptput
-      	CLK180 => open, 	-- 180 degree DCM CLK output
-      	CLK270 => open,	 	-- 270 degree DCM CLK output
-      	CLK2X => dcm_cpu2, 	-- 2X DCM CLK output
-      	CLK2X180 => open, -- 2X, 180 degree DCM CLK out
-      	CLK90 => open,   	-- 90 degree DCM CLK output
-      	CLKDV => open,   	-- Divided DCM CLK out (CLKDV_DIVIDE)
-      	CLKFX => open,   	-- DCM CLK synthesis out (M/D)
-      	CLKFX180 => open, 	-- 180 degree CLK synthesis out
-      	LOCKED => locked_int(0), -- DCM LOCK status output
-      	PSDONE => open, 	-- Dynamic phase adjust done output
-      	STATUS => open, 	-- 8-bit DCM status bits output
-      	CLKFB => cpu_clk_int,   -- DCM clock feedback
-      	CLKIN => cpu_clk_in,   -- Clock input (from IBUFG, BUFG or DCM)
-      	PSCLK => low,   	-- Dynamic phase adjust clock input
-      	PSEN => low,     	-- Dynamic phase adjust enable input
-      	PSINCDEC => low, 	-- Dynamic phase adjust increment/decrement
-      	RST => areset);     -- DCM asynchronous reset input
-   
-   	cpu2_dcm: 
-   	DCM generic map (
-      	CLKDV_DIVIDE => 2.0, --  Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-                           --     7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
-      	CLKFX_DIVIDE => 1,   --  Can be any interger from 1 to 32
-      	CLKFX_MULTIPLY => 4, --  Can be any integer from 1 to 32
-      	CLKIN_DIVIDE_BY_2 => FALSE, --  TRUE/FALSE to enable CLKIN divide by two feature
-      	CLKIN_PERIOD => 7.8125,          --  Specify period of input clock
-      	CLKOUT_PHASE_SHIFT => "NONE", --  Specify phase shift of NONE, FIXED or VARIABLE
-      	CLK_FEEDBACK => "1X",         --  Specify clock feedback of NONE, 1X or 2X
-      	DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", --  SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-                                             --     an integer from 0 to 15
-      	DFS_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for frequency synthesis
-      	DLL_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for DLL
-      	DUTY_CYCLE_CORRECTION => TRUE, --  Duty cycle correction, TRUE or FALSE
-      	FACTORY_JF => X"8080",          --  FACTORY JF Values
-      	PHASE_SHIFT => 0,        --  Amount of fixed phase shift from -255 to 255
-      	STARTUP_WAIT => FALSE) --  Delay configuration DONE until DCM LOCK, TRUE/FALSE
-   	port map (
-      	CLK0 => dcm_cpu2_dum,     	-- 0 degree DCM CLK ouptput
-      	CLK180 => open,		 -- 180 degree DCM CLK output
-      	CLK270 => open,	 	-- 270 degree DCM CLK output
-      	CLK2X => dcm_cpu4,  -- 2X DCM CLK output
-      	CLK2X180 => open, 	-- 2X, 180 degree DCM CLK out
-      	CLK90 => open,   	-- 90 degree DCM CLK output
-      	CLKDV => open,   	-- Divided DCM CLK out (CLKDV_DIVIDE)
-      	CLKFX => open,   	-- DCM CLK synthesis out (M/D)
-      	CLKFX180 => open, 	-- 180 degree CLK synthesis out
-      	LOCKED => locked_int(1), -- DCM LOCK status output
-      	PSDONE => open, 	-- Dynamic phase adjust done output
-      	STATUS => open, 	-- 8-bit DCM status bits output
-      	CLKFB => cpu_clk_2x_dum_int,   -- DCM clock feedback
-      	CLKIN => cpu_clk_2x_int,   -- Clock input (from IBUFG, BUFG or DCM)
-      	PSCLK => low,   	-- Dynamic phase adjust clock input
-      	PSEN => low,     	-- Dynamic phase adjust enable input
-      	PSINCDEC => low, 	-- Dynamic phase adjust increment/decrement
-      	RST => dcm2_reset);     -- DCM asynchronous reset input
-   
-   	ddr_read_dcm: 
-   	DCM generic map (
-      	CLKDV_DIVIDE => 2.0, --  Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-                           --     7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
-      	CLKFX_DIVIDE => 1,   --  Can be any interger from 1 to 32
-      	CLKFX_MULTIPLY => 4, --  Can be any integer from 1 to 32
-      	CLKIN_DIVIDE_BY_2 => FALSE, --  TRUE/FALSE to enable CLKIN divide by two feature
-      	CLKIN_PERIOD => 7.8125,          --  Specify period of input clock
-     	CLKOUT_PHASE_SHIFT => "FIXED", --  Specify phase shift of NONE, FIXED or VARIABLE
---      	CLKOUT_PHASE_SHIFT => "NONE", --  Specify phase shift of NONE, FIXED or VARIABLE
-      	CLK_FEEDBACK => "1X",         --  Specify clock feedback of NONE, 1X or 2X
-      	DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", --  SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-                                             --     an integer from 0 to 15
-      	DFS_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for frequency synthesis
-      	DLL_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for DLL
-      	DUTY_CYCLE_CORRECTION => TRUE, --  Duty cycle correction, TRUE or FALSE
-      	FACTORY_JF => X"8080",          --  FACTORY JF Values
-      	PHASE_SHIFT => 103,        --  Amount of fixed phase shift from -255 to 255
---      	PHASE_SHIFT => 0,        --  Amount of fixed phase shift from -255 to 255
-      	STARTUP_WAIT => FALSE) --  Delay configuration DONE until DCM LOCK, TRUE/FALSE
-   	port map (
-      	CLK0 => dcm_ddr2,     	-- 0 degree DCM CLK ouptput
-      	CLK180 => open,		 -- 180 degree DCM CLK output
-      	CLK270 => open,	 	-- 270 degree DCM CLK output
-      	CLK2X => dcm_ddr2_2x,  -- 2X DCM CLK output
-      	CLK2X180 => open, 	-- 2X, 180 degree DCM CLK out
-      	CLK90 => open,   	-- 90 degree DCM CLK output
-      	CLKDV => open,   	-- Divided DCM CLK out (CLKDV_DIVIDE)
-      	CLKFX => open,   	-- DCM CLK synthesis out (M/D)
-      	CLKFX180 => open, 	-- 180 degree CLK synthesis out
-      	LOCKED => locked_int(2), -- DCM LOCK status output
-      	PSDONE => open, 	-- Dynamic phase adjust done output
-      	STATUS => open, 	-- 8-bit DCM status bits output
-      	CLKFB => ddr_in_clk_int,   -- DCM clock feedback
-      	CLKIN => sdr_clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM)
-      	PSCLK => low,   	-- Dynamic phase adjust clock input
-      	PSEN => low,     	-- Dynamic phase adjust enable input
-      	PSINCDEC => low, 	-- Dynamic phase adjust increment/decrement
-      	RST => dcm3_reset);     -- DCM asynchronous reset input
-   
-   	cpu1:
-	BUFG port map (
-		I => dcm_cpu1,
-		O => cpu_clk_int);
-		
-   	cpu2:
-	BUFG port map (
-		I => dcm_cpu2,
-		O => cpu_clk_2x_int);
-		
-   	cpu2_dum:
-	BUFG port map (
-		I => dcm_cpu2_dum,
-		O => cpu_clk_2x_dum_int);
-		
-   	cpu4:
-	BUFG port map (
-		I => dcm_cpu4,
-		O => cpu_clk_4x_int);
-		
-   	ddr_clk:
-	BUFG port map (
-		I => dcm_ddr2,
-		O => ddr_in_clk_int);
-
-   	ddr_clk_2x:
-	BUFG port map (
-		I => dcm_ddr2_2x,
-		O => ddr_in_clk_2x_int);
-
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity clocks is
+	port (	areset			: in std_logic;
+			cpu_clk_p		: in std_logic;
+			sdr_clk_fb_p	: in std_logic;
+			cpu_clk			: out std_logic;
+			cpu_clk_2x		: out std_logic;
+			cpu_clk_4x		: out std_logic;
+			ddr_in_clk		: out std_logic;
+			ddr_in_clk_2x	: out std_logic;
+			locked			: out std_logic_vector(2 downto 0));
+end clocks;
+
+architecture behave of clocks is
+
+signal	low					: std_logic;
+
+signal	cpu_clk_in			: std_logic;
+signal	sdr_clk_fb_in		: std_logic;
+
+signal	dcm_cpu1			: std_logic;
+signal	dcm_cpu2			: std_logic;
+signal	dcm_cpu2_dum		: std_logic;
+signal	dcm_cpu4			: std_logic;
+signal	dcm_ddr2			: std_logic;
+signal	dcm_ddr2_2x			: std_logic;
+
+signal	cpu_clk_int			: std_logic;
+signal	cpu_clk_2x_int		: std_logic;
+signal	cpu_clk_2x_dum_int	: std_logic;
+signal	cpu_clk_4x_int		: std_logic;
+signal	ddr_in_clk_int		: std_logic;
+signal	ddr_in_clk_2x_int	: std_logic;
+
+signal	dcm1_locked_del		: std_logic;
+signal	dcm2_locked_del		: std_logic;
+signal	dcm2_reset			: std_logic;
+signal	dcm3_reset			: std_logic;
+
+signal	locked_int			: std_logic_vector(2 downto 0);
+signal	del_addr			: std_logic_vector(3 downto 0);
+
+begin
+
+	low <= '0';				
+	del_addr <= "1111";
+	
+	cpu_clk <= cpu_clk_int;
+	cpu_clk_2x <= cpu_clk_2x_int;
+	cpu_clk_4x <= cpu_clk_4x_int;
+	ddr_in_clk <= ddr_in_clk_int;
+	ddr_in_clk_2x <= ddr_in_clk_2x_int;
+	locked <= locked_int;
+	
+
+   	CPU_IBUFG: 
+   	IBUFG port map (
+      	O => cpu_clk_in,
+      	I => cpu_clk_p);
+	
+   	SDR_FB_IBUFG: 
+   	IBUFG port map (
+      	O => sdr_clk_fb_in,
+      	I => sdr_clk_fb_p);
+      	
+   dcm2_rst: 
+   SRL16 generic map (
+      	INIT => X"0000")
+   port map (
+      	Q => dcm1_locked_del,
+      	A0 => del_addr(0),
+      	A1 => del_addr(1),
+      	A2 => del_addr(2),
+      	A3 => del_addr(3),
+      	CLK => cpu_clk_int,
+      	D => locked_int(0));
+      	
+	dcm2_reset <= not(dcm1_locked_del);      	
+	
+   dcm3_rst: 
+   SRL16 generic map (
+      	INIT => X"0000")
+   port map (
+      	Q => dcm2_locked_del,
+      	A0 => del_addr(0),
+      	A1 => del_addr(1),
+      	A2 => del_addr(2),
+      	A3 => del_addr(3),
+      	CLK => cpu_clk_int,
+      	D => locked_int(1));
+      	
+	dcm3_reset <= not(dcm2_locked_del);      	
+	
+   	cpu1_dcm: 
+   	DCM generic map (
+      	CLKDV_DIVIDE => 2.0, --  Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
+                           --     7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
+      	CLKFX_DIVIDE => 1,   --  Can be any interger from 1 to 32
+      	CLKFX_MULTIPLY => 4, --  Can be any integer from 1 to 32
+      	CLKIN_DIVIDE_BY_2 => FALSE, --  TRUE/FALSE to enable CLKIN divide by two feature
+      	CLKIN_PERIOD => 15.625,          --  Specify period of input clock
+      	CLKOUT_PHASE_SHIFT => "NONE", --  Specify phase shift of NONE, FIXED or VARIABLE
+      	CLK_FEEDBACK => "1X",         --  Specify clock feedback of NONE, 1X or 2X
+      	DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", --  SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
+                                             --     an integer from 0 to 15
+      	DFS_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for frequency synthesis
+      	DLL_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for DLL
+      	DUTY_CYCLE_CORRECTION => TRUE, --  Duty cycle correction, TRUE or FALSE
+      	FACTORY_JF => X"8080",          --  FACTORY JF Values
+      	PHASE_SHIFT => 0,        --  Amount of fixed phase shift from -255 to 255
+      	STARTUP_WAIT => FALSE) --  Delay configuration DONE until DCM LOCK, TRUE/FALSE
+   	port map (
+      	CLK0 => dcm_cpu1,   -- 0 degree DCM CLK ouptput
+      	CLK180 => open, 	-- 180 degree DCM CLK output
+      	CLK270 => open,	 	-- 270 degree DCM CLK output
+      	CLK2X => dcm_cpu2, 	-- 2X DCM CLK output
+      	CLK2X180 => open, -- 2X, 180 degree DCM CLK out
+      	CLK90 => open,   	-- 90 degree DCM CLK output
+      	CLKDV => open,   	-- Divided DCM CLK out (CLKDV_DIVIDE)
+      	CLKFX => open,   	-- DCM CLK synthesis out (M/D)
+      	CLKFX180 => open, 	-- 180 degree CLK synthesis out
+      	LOCKED => locked_int(0), -- DCM LOCK status output
+      	PSDONE => open, 	-- Dynamic phase adjust done output
+      	STATUS => open, 	-- 8-bit DCM status bits output
+      	CLKFB => cpu_clk_int,   -- DCM clock feedback
+      	CLKIN => cpu_clk_in,   -- Clock input (from IBUFG, BUFG or DCM)
+      	PSCLK => low,   	-- Dynamic phase adjust clock input
+      	PSEN => low,     	-- Dynamic phase adjust enable input
+      	PSINCDEC => low, 	-- Dynamic phase adjust increment/decrement
+      	RST => areset);     -- DCM asynchronous reset input
+   
+   	cpu2_dcm: 
+   	DCM generic map (
+      	CLKDV_DIVIDE => 2.0, --  Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
+                           --     7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
+      	CLKFX_DIVIDE => 1,   --  Can be any interger from 1 to 32
+      	CLKFX_MULTIPLY => 4, --  Can be any integer from 1 to 32
+      	CLKIN_DIVIDE_BY_2 => FALSE, --  TRUE/FALSE to enable CLKIN divide by two feature
+      	CLKIN_PERIOD => 7.8125,          --  Specify period of input clock
+      	CLKOUT_PHASE_SHIFT => "NONE", --  Specify phase shift of NONE, FIXED or VARIABLE
+      	CLK_FEEDBACK => "1X",         --  Specify clock feedback of NONE, 1X or 2X
+      	DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", --  SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
+                                             --     an integer from 0 to 15
+      	DFS_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for frequency synthesis
+      	DLL_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for DLL
+      	DUTY_CYCLE_CORRECTION => TRUE, --  Duty cycle correction, TRUE or FALSE
+      	FACTORY_JF => X"8080",          --  FACTORY JF Values
+      	PHASE_SHIFT => 0,        --  Amount of fixed phase shift from -255 to 255
+      	STARTUP_WAIT => FALSE) --  Delay configuration DONE until DCM LOCK, TRUE/FALSE
+   	port map (
+      	CLK0 => dcm_cpu2_dum,     	-- 0 degree DCM CLK ouptput
+      	CLK180 => open,		 -- 180 degree DCM CLK output
+      	CLK270 => open,	 	-- 270 degree DCM CLK output
+      	CLK2X => dcm_cpu4,  -- 2X DCM CLK output
+      	CLK2X180 => open, 	-- 2X, 180 degree DCM CLK out
+      	CLK90 => open,   	-- 90 degree DCM CLK output
+      	CLKDV => open,   	-- Divided DCM CLK out (CLKDV_DIVIDE)
+      	CLKFX => open,   	-- DCM CLK synthesis out (M/D)
+      	CLKFX180 => open, 	-- 180 degree CLK synthesis out
+      	LOCKED => locked_int(1), -- DCM LOCK status output
+      	PSDONE => open, 	-- Dynamic phase adjust done output
+      	STATUS => open, 	-- 8-bit DCM status bits output
+      	CLKFB => cpu_clk_2x_dum_int,   -- DCM clock feedback
+      	CLKIN => cpu_clk_2x_int,   -- Clock input (from IBUFG, BUFG or DCM)
+      	PSCLK => low,   	-- Dynamic phase adjust clock input
+      	PSEN => low,     	-- Dynamic phase adjust enable input
+      	PSINCDEC => low, 	-- Dynamic phase adjust increment/decrement
+      	RST => dcm2_reset);     -- DCM asynchronous reset input
+   
+   	ddr_read_dcm: 
+   	DCM generic map (
+      	CLKDV_DIVIDE => 2.0, --  Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
+                           --     7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
+      	CLKFX_DIVIDE => 1,   --  Can be any interger from 1 to 32
+      	CLKFX_MULTIPLY => 4, --  Can be any integer from 1 to 32
+      	CLKIN_DIVIDE_BY_2 => FALSE, --  TRUE/FALSE to enable CLKIN divide by two feature
+      	CLKIN_PERIOD => 7.8125,          --  Specify period of input clock
+     	CLKOUT_PHASE_SHIFT => "FIXED", --  Specify phase shift of NONE, FIXED or VARIABLE
+--      	CLKOUT_PHASE_SHIFT => "NONE", --  Specify phase shift of NONE, FIXED or VARIABLE
+      	CLK_FEEDBACK => "1X",         --  Specify clock feedback of NONE, 1X or 2X
+      	DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", --  SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
+                                             --     an integer from 0 to 15
+      	DFS_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for frequency synthesis
+      	DLL_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for DLL
+      	DUTY_CYCLE_CORRECTION => TRUE, --  Duty cycle correction, TRUE or FALSE
+      	FACTORY_JF => X"8080",          --  FACTORY JF Values
+      	PHASE_SHIFT => 103,        --  Amount of fixed phase shift from -255 to 255
+--      	PHASE_SHIFT => 0,        --  Amount of fixed phase shift from -255 to 255
+      	STARTUP_WAIT => FALSE) --  Delay configuration DONE until DCM LOCK, TRUE/FALSE
+   	port map (
+      	CLK0 => dcm_ddr2,     	-- 0 degree DCM CLK ouptput
+      	CLK180 => open,		 -- 180 degree DCM CLK output
+      	CLK270 => open,	 	-- 270 degree DCM CLK output
+      	CLK2X => dcm_ddr2_2x,  -- 2X DCM CLK output
+      	CLK2X180 => open, 	-- 2X, 180 degree DCM CLK out
+      	CLK90 => open,   	-- 90 degree DCM CLK output
+      	CLKDV => open,   	-- Divided DCM CLK out (CLKDV_DIVIDE)
+      	CLKFX => open,   	-- DCM CLK synthesis out (M/D)
+      	CLKFX180 => open, 	-- 180 degree CLK synthesis out
+      	LOCKED => locked_int(2), -- DCM LOCK status output
+      	PSDONE => open, 	-- Dynamic phase adjust done output
+      	STATUS => open, 	-- 8-bit DCM status bits output
+      	CLKFB => ddr_in_clk_int,   -- DCM clock feedback
+      	CLKIN => sdr_clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM)
+      	PSCLK => low,   	-- Dynamic phase adjust clock input
+      	PSEN => low,     	-- Dynamic phase adjust enable input
+      	PSINCDEC => low, 	-- Dynamic phase adjust increment/decrement
+      	RST => dcm3_reset);     -- DCM asynchronous reset input
+   
+   	cpu1:
+	BUFG port map (
+		I => dcm_cpu1,
+		O => cpu_clk_int);
+		
+   	cpu2:
+	BUFG port map (
+		I => dcm_cpu2,
+		O => cpu_clk_2x_int);
+		
+   	cpu2_dum:
+	BUFG port map (
+		I => dcm_cpu2_dum,
+		O => cpu_clk_2x_dum_int);
+		
+   	cpu4:
+	BUFG port map (
+		I => dcm_cpu4,
+		O => cpu_clk_4x_int);
+		
+   	ddr_clk:
+	BUFG port map (
+		I => dcm_ddr2,
+		O => ddr_in_clk_int);
+
+   	ddr_clk_2x:
+	BUFG port map (
+		I => dcm_ddr2_2x,
+		O => ddr_in_clk_2x_int);
+
 end behave;
\ No newline at end of file
diff --git a/zpu/hdl/zpu4/src/io.vhd b/zpu/hdl/zpu4/src/io.vhd
index a0e494a..159df6f 100644
--- a/zpu/hdl/zpu4/src/io.vhd
+++ b/zpu/hdl/zpu4/src/io.vhd
@@ -1,112 +1,112 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-use std.textio.all;
-
-library work;
-use work.zpu_config.all;
-use work.zpupkg.all;
-use work.txt_util.all;
- 
-entity  zpu_io is
-  generic (
-           log_file:       string  := "log.txt"
-          );
-  port(
-       	clk         : in std_logic;
-       	areset        : in std_logic;
-		busy : out std_logic;
-		writeEnable : in std_logic;
-		readEnable : in std_logic;
-		write	: in std_logic_vector(wordSize-1 downto 0);
-		read	: out std_logic_vector(wordSize-1 downto 0);
-		addr : in std_logic_vector(maxAddrBit downto minAddrBit)
-		);
-end zpu_io;
-   
-   
-architecture behave of zpu_io is
-
-
-
-signal timer_read : std_logic_vector(7 downto 0);
---signal timer_write : std_logic_vector(7 downto 0);
-signal timer_we : std_logic;
-
-signal serving : std_logic;
-
-file 		l_file		: TEXT open write_mode is log_file;
-constant lowAddrBits: std_logic_vector(minAddrBit-1 downto 0) := (others=>'0');
-constant tx_full: std_logic := '0';
-constant rx_empty: std_logic := '1';
-
-begin
-
-	
-	timerinst: timer port map (
-       clk => clk,
-		 areset => areset,
-		 we => timer_we,
-		 din => write(7 downto 0),
-		 adr => addr(4 downto 2),
-		 dout => timer_read);
-	
-	busy <= writeEnable or readEnable;
-	timer_we <= writeEnable and addr(12);
-	
-	process(areset, clk)
-	variable taddr  : std_logic_vector(maxAddrBit downto 0);
-	begin
-		taddr := (others => '0');
-		taddr(maxAddrBit downto minAddrBit) := addr;
-
-		if (areset = '1') then
---			timer_we <= '0';
-		elsif (clk'event and clk = '1') then
---			timer_we <= '0';
-			if writeEnable = '1' then
-				-- external interface (fixed address)
-				-- extend compare to avoid waring messages
-				if ("1" & addr & lowAddrBits)=x"80a000c" then
-					report "Write to UART[0]" & " :0x" & hstr(write);
-					-- Write to UART
-					-- report "" & character'image(conv_integer(memBint)) severity note;
-				    print(l_file, character'val(to_integer(unsigned(write))));
-				elsif addr(12)='1' then
-					report "Write to TIMER" & " :0x" & hstr(write);
---				    report "xxx" severity failure;
--- 					timer_we <= '1';
-				else
-					print(l_file, character'val(to_integer(unsigned(write))));
-					report "Illegal IO write @" & "0x" & hstr(taddr) severity warning;
-				end if;
-				
-			end if;
-			read <= (others => '0');
-			if (readEnable = '1') then
-				-- extend compare to avoid waring messages
-				if ("1" & addr & lowAddrBits)=x"80a000c" then
-					report "Read UART[0]";
-					read(8) <= not tx_full; -- output fifo not full
-					read(9) <= not rx_empty; -- receiver not empty
-				elsif ("1" & addr & lowAddrBits)=x"80a0010" then
-					report "Read UART[1]";
-					read(8) <= not rx_empty; -- receiver not empty
-					read(7 downto 0) <= (others => '0');
- 				elsif addr(12)='1' then
-					report "Read TIMER";
- 					read(7 downto 0) <= timer_read;
- 				elsif addr(11)='1' then
-					report "Read ZPU Freq";
- 					read(7 downto 0) <= ZPU_Frequency;
-				else
-					report "Illegal IO read @" & "0x" & hstr(taddr) severity warning;
-				end if;
-			end if;
-		end if;
-	end process;
-
-
-end behave;
- 
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use std.textio.all;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+use work.txt_util.all;
+ 
+entity  zpu_io is
+  generic (
+           log_file:       string  := "log.txt"
+          );
+  port(
+       	clk         : in std_logic;
+       	areset        : in std_logic;
+		busy : out std_logic;
+		writeEnable : in std_logic;
+		readEnable : in std_logic;
+		write	: in std_logic_vector(wordSize-1 downto 0);
+		read	: out std_logic_vector(wordSize-1 downto 0);
+		addr : in std_logic_vector(maxAddrBit downto minAddrBit)
+		);
+end zpu_io;
+   
+   
+architecture behave of zpu_io is
+
+
+
+signal timer_read : std_logic_vector(7 downto 0);
+--signal timer_write : std_logic_vector(7 downto 0);
+signal timer_we : std_logic;
+
+signal serving : std_logic;
+
+file 		l_file		: TEXT open write_mode is log_file;
+constant lowAddrBits: std_logic_vector(minAddrBit-1 downto 0) := (others=>'0');
+constant tx_full: std_logic := '0';
+constant rx_empty: std_logic := '1';
+
+begin
+
+	
+	timerinst: timer port map (
+       clk => clk,
+		 areset => areset,
+		 we => timer_we,
+		 din => write(7 downto 0),
+		 adr => addr(4 downto 2),
+		 dout => timer_read);
+	
+	busy <= writeEnable or readEnable;
+	timer_we <= writeEnable and addr(12);
+	
+	process(areset, clk)
+	variable taddr  : std_logic_vector(maxAddrBit downto 0);
+	begin
+		taddr := (others => '0');
+		taddr(maxAddrBit downto minAddrBit) := addr;
+
+		if (areset = '1') then
+--			timer_we <= '0';
+		elsif (clk'event and clk = '1') then
+--			timer_we <= '0';
+			if writeEnable = '1' then
+				-- external interface (fixed address)
+				-- extend compare to avoid waring messages
+				if ("1" & addr & lowAddrBits)=x"80a000c" then
+					report "Write to UART[0]" & " :0x" & hstr(write);
+					-- Write to UART
+					-- report "" & character'image(conv_integer(memBint)) severity note;
+				    print(l_file, character'val(to_integer(unsigned(write))));
+				elsif addr(12)='1' then
+					report "Write to TIMER" & " :0x" & hstr(write);
+--				    report "xxx" severity failure;
+-- 					timer_we <= '1';
+				else
+					print(l_file, character'val(to_integer(unsigned(write))));
+					report "Illegal IO write @" & "0x" & hstr(taddr) severity warning;
+				end if;
+				
+			end if;
+			read <= (others => '0');
+			if (readEnable = '1') then
+				-- extend compare to avoid waring messages
+				if ("1" & addr & lowAddrBits)=x"80a000c" then
+					report "Read UART[0]";
+					read(8) <= not tx_full; -- output fifo not full
+					read(9) <= not rx_empty; -- receiver not empty
+				elsif ("1" & addr & lowAddrBits)=x"80a0010" then
+					report "Read UART[1]";
+					read(8) <= not rx_empty; -- receiver not empty
+					read(7 downto 0) <= (others => '0');
+ 				elsif addr(12)='1' then
+					report "Read TIMER";
+ 					read(7 downto 0) <= timer_read;
+ 				elsif addr(11)='1' then
+					report "Read ZPU Freq";
+ 					read(7 downto 0) <= ZPU_Frequency;
+				else
+					report "Illegal IO read @" & "0x" & hstr(taddr) severity warning;
+				end if;
+			end if;
+		end if;
+	end process;
+
+
+end behave;
+ 
diff --git a/zpu/hdl/zpu4/src/timer.vhd b/zpu/hdl/zpu4/src/timer.vhd
index be1dbb8..c60c172 100644
--- a/zpu/hdl/zpu4/src/timer.vhd
+++ b/zpu/hdl/zpu4/src/timer.vhd
@@ -1,61 +1,61 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
- 
-entity timer is
-  port(
-       clk              : in std_logic;
-		 areset				: in std_logic;
-		 we					: in std_logic;
-		 din					: in std_logic_vector(7 downto 0);
-		 adr					: in std_logic_vector(2 downto 0);
-		 dout					: out std_logic_vector(7 downto 0));
-end timer;
-   
-   
-architecture behave of timer is
-
-signal	sample	: std_logic;
-signal	reset		: std_logic;
-
-
-signal	cnt		: unsigned(63 downto 0);
-signal	cnt_smp	: std_logic_vector(63 downto 0);
-
-begin
-
-	reset <= '1' when (we = '1' and din(0) = '1') else '0';
-	sample <= '1' when (we = '1' and din(1) = '1') else '0';
-
-	process(clk, areset)	-- Carry generation
-	begin
-		if areset = '1' then
-			cnt <= (others => '0');
-			cnt_smp <= (others => '0');
-		elsif (clk'event and clk = '1') then
-			cnt <= cnt + 1;
-			if sample = '1' then
---				report "sampling" severity failure;
-				cnt_smp <= std_logic_vector(cnt);
-			end if;
-		end if;
-	end process;
-	
-	
-	process(cnt_smp, adr)
-	begin
-		case adr is
-			when "000"	=> dout <= cnt_smp(7 downto 0);
-			when "001"	=> dout <= cnt_smp(15 downto 8);
-			when "010"	=> dout <= cnt_smp(23 downto 16);
-			when "011"	=> dout <= cnt_smp(31 downto 24);
-			when "100"	=> dout <= cnt_smp(39 downto 32);
-			when "101"	=> dout <= cnt_smp(47 downto 40);
-			when "110"	=> dout <= cnt_smp(55 downto 48);
-			when others	=> dout <= cnt_smp(63 downto 56);
-		end case;
-	end process;
-	
-
-end behave;
- 
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+entity timer is
+  port(
+       clk              : in std_logic;
+		 areset				: in std_logic;
+		 we					: in std_logic;
+		 din					: in std_logic_vector(7 downto 0);
+		 adr					: in std_logic_vector(2 downto 0);
+		 dout					: out std_logic_vector(7 downto 0));
+end timer;
+   
+   
+architecture behave of timer is
+
+signal	sample	: std_logic;
+signal	reset		: std_logic;
+
+
+signal	cnt		: unsigned(63 downto 0);
+signal	cnt_smp	: std_logic_vector(63 downto 0);
+
+begin
+
+	reset <= '1' when (we = '1' and din(0) = '1') else '0';
+	sample <= '1' when (we = '1' and din(1) = '1') else '0';
+
+	process(clk, areset)	-- Carry generation
+	begin
+		if areset = '1' then
+			cnt <= (others => '0');
+			cnt_smp <= (others => '0');
+		elsif (clk'event and clk = '1') then
+			cnt <= cnt + 1;
+			if sample = '1' then
+--				report "sampling" severity failure;
+				cnt_smp <= std_logic_vector(cnt);
+			end if;
+		end if;
+	end process;
+	
+	
+	process(cnt_smp, adr)
+	begin
+		case adr is
+			when "000"	=> dout <= cnt_smp(7 downto 0);
+			when "001"	=> dout <= cnt_smp(15 downto 8);
+			when "010"	=> dout <= cnt_smp(23 downto 16);
+			when "011"	=> dout <= cnt_smp(31 downto 24);
+			when "100"	=> dout <= cnt_smp(39 downto 32);
+			when "101"	=> dout <= cnt_smp(47 downto 40);
+			when "110"	=> dout <= cnt_smp(55 downto 48);
+			when others	=> dout <= cnt_smp(63 downto 56);
+		end case;
+	end process;
+	
+
+end behave;
+ 
diff --git a/zpu/hdl/zpu4/src/trace.vhd b/zpu/hdl/zpu4/src/trace.vhd
index 2413970..00ac3a8 100644
--- a/zpu/hdl/zpu4/src/trace.vhd
+++ b/zpu/hdl/zpu4/src/trace.vhd
@@ -1,117 +1,117 @@
--- ZPU
---
--- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
--- 
--- The FreeBSD license
--- 
--- Redistribution and use in source and binary forms, with or without
--- modification, are permitted provided that the following conditions
--- are met:
--- 
--- 1. Redistributions of source code must retain the above copyright
---    notice, this list of conditions and the following disclaimer.
--- 2. Redistributions in binary form must reproduce the above
---    copyright notice, this list of conditions and the following
---    disclaimer in the documentation and/or other materials
---    provided with the distribution.
--- 
--- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
--- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
--- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
--- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
--- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
--- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
--- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
--- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
--- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
--- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--- 
--- The views and conclusions contained in the software and documentation
--- are those of the authors and should not be interpreted as representing
--- official policies, either expressed or implied, of the ZPU Project.
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-use std.textio.all;
-
-library work;
-use work.zpu_config.all;
-use work.zpupkg.all;
-use work.txt_util.all;
- 
- 
-entity trace is
-  generic (
-           log_file:       string  := "trace.txt"
-          );
-  port(
-       	clk         : in std_logic;
-       	begin_inst  : in std_logic;
-       	pc          : in std_logic_vector(maxAddrBitIncIO downto 0);
-		opcode		: in std_logic_vector(7 downto 0);
-		sp			: in std_logic_vector(maxAddrBitIncIO downto 2);
-		memA		: in std_logic_vector(wordSize-1 downto 0);
-		memB		: in std_logic_vector(wordSize-1 downto 0);
-		busy  : in std_logic;
-		intSp		: in std_logic_vector(stack_bits-1 downto 0)
-		);
-end trace;
-   
-   
-architecture behave of trace is
-  
-  
-file 		l_file		: TEXT open write_mode is log_file;
-
-
-begin
-
-
--- write data and control information to a file
-
-receive_data: process
-
-variable l: line;
-variable t	: std_logic_vector(wordSize-1 downto 0);
-variable t2	: std_logic_vector(maxAddrBitIncIO downto 0);
-variable counter : unsigned(63 downto 0);
-   
-   
-   
-begin                                       
-
-	t:= (others => '0');
-	t2:= (others => '0');
-
-counter := (others => '0');
-   -- print header for the logfile
-   print(l_file, "#pc,opcode,sp,top_of_stack ");
-   print(l_file, "#----------");
-   print(l_file, " ");
-
-	wait until clk = '1';
-	wait until clk = '0'; 
-
-   while true loop
-
-		counter := counter + 1;
-		if begin_inst = '1' then
-			t(maxAddrBitIncIO downto 2):=sp;
-			t2:=pc;
-     		print(l_file, "0x" & hstr(t2) & " 0x" & hstr(opcode) & " 0x" & hstr(t) & " 0x" & hstr(memA) & " 0x" & hstr(memB) & " 0x" & hstr(intSp) & " 0x" & hstr(std_logic_vector(counter)));
-		end if;
-		
-     	wait until clk = '0';
-    
-   end loop;
-
- end process receive_data;
-
-
-
-end behave;
- 
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use std.textio.all;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+use work.txt_util.all;
+ 
+ 
+entity trace is
+  generic (
+           log_file:       string  := "trace.txt"
+          );
+  port(
+       	clk         : in std_logic;
+       	begin_inst  : in std_logic;
+       	pc          : in std_logic_vector(maxAddrBitIncIO downto 0);
+		opcode		: in std_logic_vector(7 downto 0);
+		sp			: in std_logic_vector(maxAddrBitIncIO downto 2);
+		memA		: in std_logic_vector(wordSize-1 downto 0);
+		memB		: in std_logic_vector(wordSize-1 downto 0);
+		busy  : in std_logic;
+		intSp		: in std_logic_vector(stack_bits-1 downto 0)
+		);
+end trace;
+   
+   
+architecture behave of trace is
+  
+  
+file 		l_file		: TEXT open write_mode is log_file;
+
+
+begin
+
+
+-- write data and control information to a file
+
+receive_data: process
+
+variable l: line;
+variable t	: std_logic_vector(wordSize-1 downto 0);
+variable t2	: std_logic_vector(maxAddrBitIncIO downto 0);
+variable counter : unsigned(63 downto 0);
+   
+   
+   
+begin                                       
+
+	t:= (others => '0');
+	t2:= (others => '0');
+
+counter := (others => '0');
+   -- print header for the logfile
+   print(l_file, "#pc,opcode,sp,top_of_stack ");
+   print(l_file, "#----------");
+   print(l_file, " ");
+
+	wait until clk = '1';
+	wait until clk = '0'; 
+
+   while true loop
+
+		counter := counter + 1;
+		if begin_inst = '1' then
+			t(maxAddrBitIncIO downto 2):=sp;
+			t2:=pc;
+     		print(l_file, "0x" & hstr(t2) & " 0x" & hstr(opcode) & " 0x" & hstr(t) & " 0x" & hstr(memA) & " 0x" & hstr(memB) & " 0x" & hstr(intSp) & " 0x" & hstr(std_logic_vector(counter)));
+		end if;
+		
+     	wait until clk = '0';
+    
+   end loop;
+
+ end process receive_data;
+
+
+
+end behave;
+ 
diff --git a/zpu/hdl/zpu4/src/txt_util.vhd b/zpu/hdl/zpu4/src/txt_util.vhd
index 3d5297a..6432294 100644
--- a/zpu/hdl/zpu4/src/txt_util.vhd
+++ b/zpu/hdl/zpu4/src/txt_util.vhd
@@ -1,621 +1,621 @@
--- ZPU
---
--- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
--- 
--- The FreeBSD license
--- 
--- Redistribution and use in source and binary forms, with or without
--- modification, are permitted provided that the following conditions
--- are met:
--- 
--- 1. Redistributions of source code must retain the above copyright
---    notice, this list of conditions and the following disclaimer.
--- 2. Redistributions in binary form must reproduce the above
---    copyright notice, this list of conditions and the following
---    disclaimer in the documentation and/or other materials
---    provided with the distribution.
--- 
--- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
--- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
--- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
--- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
--- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
--- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
--- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
--- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
--- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
--- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--- 
--- The views and conclusions contained in the software and documentation
--- are those of the authors and should not be interpreted as representing
--- official policies, either expressed or implied, of the ZPU Project.
-
-library ieee;
-use ieee.std_logic_1164.all;
-use std.textio.all;
-
-library work;
-
-package txt_util is
-
-    -- prints a message to the screen
-    procedure print(text: string);
-
-    -- prints the message when active
-    -- useful for debug switches
-    procedure print(active: boolean; text: string);
-
-    -- converts std_logic into a character
-    function chr(sl: std_logic) return character;
-
-    -- converts std_logic into a string (1 to 1)
-    function str(sl: std_logic) return string;
-
-    -- converts std_logic_vector into a string (binary base)
-    function str(slv: std_logic_vector) return string;
-
-    -- converts boolean into a string
-    function str(b: boolean) return string;
-
-    -- converts an integer into a single character
-    -- (can also be used for hex conversion and other bases)
-    function chr(int: integer) return character;
-
-    -- converts integer into string using specified base
-    function str(int: integer; base: integer) return string;
-
-    -- converts integer to string, using base 10
-    function str(int: integer) return string;
-
-    -- convert std_logic_vector into a string in hex format
-    function hstr(slv: std_logic_vector) return string;
-
-
-    -- functions to manipulate strings
-    -----------------------------------
-
-    -- convert a character to upper case
-    function to_upper(c: character) return character;
-
-    -- convert a character to lower case
-    function to_lower(c: character) return character;
-
-    -- convert a string to upper case
-    function to_upper(s: string) return string;
-
-    -- convert a string to lower case
-    function to_lower(s: string) return string;
-
-   
-    
-    -- functions to convert strings into other formats
-    --------------------------------------------------
-    
-    -- converts a character into std_logic
-    function to_std_logic(c: character) return std_logic; 
-    
-    -- converts a string into std_logic_vector
-    function to_std_logic_vector(s: string) return std_logic_vector; 
-
-
-  
-    -- file I/O
-    -----------
-       
-    -- read variable length string from input file
-    procedure str_read(file in_file: TEXT; 
-                       res_string: out string);
-        
-    -- print string to a file and start new line
-    procedure print(file out_file: TEXT;
-                    new_string: in  string);
-    
-    -- print character to a file and start new line
-    procedure print(file out_file: TEXT;
-                    char:       in  character);
-                    
-end txt_util;
-
-
-
-
-package body txt_util is
-
-
-
-
-   -- prints text to the screen
-
-   procedure print(text: string) is
-     variable msg_line: line;
-     begin
-       write(msg_line, text);
-       writeline(output, msg_line);
-   end print;
-
-
-
-
-   -- prints text to the screen when active
-
-   procedure print(active: boolean; text: string)  is
-     begin
-      if active then
-         print(text);
-      end if;
-   end print;
-
-
-   -- converts std_logic into a character
-
-   function chr(sl: std_logic) return character is
-    variable c: character;
-    begin
-      case sl is
-         when 'U' => c:= 'U';
-         when 'X' => c:= 'X';
-         when '0' => c:= '0';
-         when '1' => c:= '1';
-         when 'Z' => c:= 'Z';
-         when 'W' => c:= 'W';
-         when 'L' => c:= 'L';
-         when 'H' => c:= 'H';
-         when '-' => c:= '-';
-      end case;
-    return c;
-   end chr;
-
-
-
-   -- converts std_logic into a string (1 to 1)
-
-   function str(sl: std_logic) return string is
-    variable s: string(1 to 1);
-    begin
-        s(1) := chr(sl);
-        return s;
-   end str;
-
-
-
-   -- converts std_logic_vector into a string (binary base)
-   -- (this also takes care of the fact that the range of
-   --  a string is natural while a std_logic_vector may
-   --  have an integer range)
-
-   function str(slv: std_logic_vector) return string is
-     variable result : string (1 to slv'length);
-     variable r : integer;
-   begin
-     r := 1;
-     for i in slv'range loop
-        result(r) := chr(slv(i));
-        r := r + 1;
-     end loop;
-     return result;
-   end str;
-
-
-   function str(b: boolean) return string is
-
-    begin
-       if b then
-          return "true";
-      else
-        return "false";
-       end if;
-    end str;
-
-
-   -- converts an integer into a character
-   -- for 0 to 9 the obvious mapping is used, higher
-   -- values are mapped to the characters A-Z
-   -- (this is usefull for systems with base > 10)
-   -- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
-
-   function chr(int: integer) return character is
-    variable c: character;
-   begin
-        case int is
-          when  0 => c := '0';
-          when  1 => c := '1';
-          when  2 => c := '2';
-          when  3 => c := '3';
-          when  4 => c := '4';
-          when  5 => c := '5';
-          when  6 => c := '6';
-          when  7 => c := '7';
-          when  8 => c := '8';
-          when  9 => c := '9';
-          when 10 => c := 'A';
-          when 11 => c := 'B';
-          when 12 => c := 'C';
-          when 13 => c := 'D';
-          when 14 => c := 'E';
-          when 15 => c := 'F';
-          when 16 => c := 'G';
-          when 17 => c := 'H';
-          when 18 => c := 'I';
-          when 19 => c := 'J';
-          when 20 => c := 'K';
-          when 21 => c := 'L';
-          when 22 => c := 'M';
-          when 23 => c := 'N';
-          when 24 => c := 'O';
-          when 25 => c := 'P';
-          when 26 => c := 'Q';
-          when 27 => c := 'R';
-          when 28 => c := 'S';
-          when 29 => c := 'T';
-          when 30 => c := 'U';
-          when 31 => c := 'V';
-          when 32 => c := 'W';
-          when 33 => c := 'X';
-          when 34 => c := 'Y';
-          when 35 => c := 'Z';
-          when others => c := '?';
-        end case;
-        return c;
-    end chr;
-
-
-
-   -- convert integer to string using specified base
-   -- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
-
-   function str(int: integer; base: integer) return string is
-
-    variable temp:      string(1 to 10);
-    variable num:       integer;
-    variable abs_int:   integer;
-    variable len:       integer := 1;
-    variable power:     integer := 1;
-
-   begin
-
-    -- bug fix for negative numbers
-    abs_int := abs(int);
-
-    num     := abs_int;
-
-    while num >= base loop                     -- Determine how many
-      len := len + 1;                          -- characters required
-      num := num / base;                       -- to represent the
-    end loop ;                                 -- number.
-
-    for i in len downto 1 loop                 -- Convert the number to
-      temp(i) := chr(abs_int/power mod base);  -- a string starting
-      power := power * base;                   -- with the right hand
-    end loop ;                                 -- side.
-
-    -- return result and add sign if required
-    if int < 0 then
-       return '-'& temp(1 to len);
-     else
-       return temp(1 to len);
-    end if;
-
-   end str;
-
-
-  -- convert integer to string, using base 10
-  function str(int: integer) return string is
-
-   begin
-
-    return str(int, 10) ;
-
-   end str;
-
-
-
-   -- converts a std_logic_vector into a hex string.
-   function hstr(slv: std_logic_vector) return string is
-       variable hexlen: integer;
-       variable longslv : std_logic_vector(67 downto 0) := (others => '0');
-       variable hex : string(1 to 16);
-       variable fourbit : std_logic_vector(3 downto 0);
-     begin
-       hexlen := (slv'left+1)/4;
-       if (slv'left+1) mod 4 /= 0 then
-         hexlen := hexlen + 1;
-       end if;
-       longslv(slv'left downto 0) := slv;
-       for i in (hexlen -1) downto 0 loop
-         fourbit := longslv(((i*4)+3) downto (i*4));
-         case fourbit is
-           when "0000" => hex(hexlen -I) := '0';
-           when "0001" => hex(hexlen -I) := '1';
-           when "0010" => hex(hexlen -I) := '2';
-           when "0011" => hex(hexlen -I) := '3';
-           when "0100" => hex(hexlen -I) := '4';
-           when "0101" => hex(hexlen -I) := '5';
-           when "0110" => hex(hexlen -I) := '6';
-           when "0111" => hex(hexlen -I) := '7';
-           when "1000" => hex(hexlen -I) := '8';
-           when "1001" => hex(hexlen -I) := '9';
-           when "1010" => hex(hexlen -I) := 'A';
-           when "1011" => hex(hexlen -I) := 'B';
-           when "1100" => hex(hexlen -I) := 'C';
-           when "1101" => hex(hexlen -I) := 'D';
-           when "1110" => hex(hexlen -I) := 'E';
-           when "1111" => hex(hexlen -I) := 'F';
-           when "ZZZZ" => hex(hexlen -I) := 'z';
-           when "UUUU" => hex(hexlen -I) := 'u';
-           when "XXXX" => hex(hexlen -I) := 'x';
-           when others => hex(hexlen -I) := '?';
-         end case;
-       end loop;
-       return hex(1 to hexlen);
-     end hstr;
-
-
-
-   -- functions to manipulate strings
-   -----------------------------------
-
-
-   -- convert a character to upper case
-
-   function to_upper(c: character) return character is
-
-      variable u: character;
-
-    begin
-
-       case c is
-        when 'a' => u := 'A';
-        when 'b' => u := 'B';
-        when 'c' => u := 'C';
-        when 'd' => u := 'D';
-        when 'e' => u := 'E';
-        when 'f' => u := 'F';
-        when 'g' => u := 'G';
-        when 'h' => u := 'H';
-        when 'i' => u := 'I';
-        when 'j' => u := 'J';
-        when 'k' => u := 'K';
-        when 'l' => u := 'L';
-        when 'm' => u := 'M';
-        when 'n' => u := 'N';
-        when 'o' => u := 'O';
-        when 'p' => u := 'P';
-        when 'q' => u := 'Q';
-        when 'r' => u := 'R';
-        when 's' => u := 'S';
-        when 't' => u := 'T';
-        when 'u' => u := 'U';
-        when 'v' => u := 'V';
-        when 'w' => u := 'W';
-        when 'x' => u := 'X';
-        when 'y' => u := 'Y';
-        when 'z' => u := 'Z';
-        when others => u := c;
-    end case;
-
-      return u;
-
-   end to_upper;
-
-
-   -- convert a character to lower case
-
-   function to_lower(c: character) return character is
-
-      variable l: character;
-
-    begin
-
-       case c is
-        when 'A' => l := 'a';
-        when 'B' => l := 'b';
-        when 'C' => l := 'c';
-        when 'D' => l := 'd';
-        when 'E' => l := 'e';
-        when 'F' => l := 'f';
-        when 'G' => l := 'g';
-        when 'H' => l := 'h';
-        when 'I' => l := 'i';
-        when 'J' => l := 'j';
-        when 'K' => l := 'k';
-        when 'L' => l := 'l';
-        when 'M' => l := 'm';
-        when 'N' => l := 'n';
-        when 'O' => l := 'o';
-        when 'P' => l := 'p';
-        when 'Q' => l := 'q';
-        when 'R' => l := 'r';
-        when 'S' => l := 's';
-        when 'T' => l := 't';
-        when 'U' => l := 'u';
-        when 'V' => l := 'v';
-        when 'W' => l := 'w';
-        when 'X' => l := 'x';
-        when 'Y' => l := 'y';
-        when 'Z' => l := 'z';
-        when others => l := c;
-    end case;
-
-      return l;
-
-   end to_lower;
-
-
-
-   -- convert a string to upper case
-
-   function to_upper(s: string) return string is
-
-     variable uppercase: string (s'range);
-
-   begin
-
-     for i in s'range loop
-        uppercase(i):= to_upper(s(i));
-     end loop;
-     return uppercase;
-
-   end to_upper;
-
-
-
-   -- convert a string to lower case
-
-   function to_lower(s: string) return string is
-
-     variable lowercase: string (s'range);
-
-   begin
-
-     for i in s'range loop
-        lowercase(i):= to_lower(s(i));
-     end loop;
-     return lowercase;
-
-   end to_lower;
-
-
-
--- functions to convert strings into other types
-
-
--- converts a character into a std_logic
-
-function to_std_logic(c: character) return std_logic is 
-    variable sl: std_logic;
-    begin
-      case c is
-        when 'U' => 
-           sl := 'U'; 
-        when 'X' =>
-           sl := 'X';
-        when '0' => 
-           sl := '0';
-        when '1' => 
-           sl := '1';
-        when 'Z' => 
-           sl := 'Z';
-        when 'W' => 
-           sl := 'W';
-        when 'L' => 
-           sl := 'L';
-        when 'H' => 
-           sl := 'H';
-        when '-' => 
-           sl := '-';
-        when others =>
-           sl := 'X'; 
-    end case;
-   return sl;
-  end to_std_logic;
-
-
--- converts a string into std_logic_vector
-
-function to_std_logic_vector(s: string) return std_logic_vector is 
-  variable slv: std_logic_vector(s'high-s'low downto 0);
-  variable k: integer;
-begin
-   k := s'high-s'low;
-  for i in s'range loop
-     slv(k) := to_std_logic(s(i));
-     k      := k - 1;
-  end loop;
-  return slv;
-end to_std_logic_vector;                                       
-                                       
-                                       
-                                       
-                                       
-                                       
-                                       
-----------------
---  file I/O  --
-----------------
-
-
-
--- read variable length string from input file
-     
-procedure str_read(file in_file: TEXT; 
-                   res_string: out string) is
-       
-       variable l:         line;
-       variable c:         character;
-       variable is_string: boolean;
-       
-   begin
-           
-     readline(in_file, l);
-     -- clear the contents of the result string
-     for i in res_string'range loop
-         res_string(i) := ' ';
-     end loop;   
-     -- read all characters of the line, up to the length  
-     -- of the results string
-     for i in res_string'range loop
-        read(l, c, is_string);
-        res_string(i) := c;
-        if not is_string then -- found end of line
-           exit;
-        end if;   
-     end loop; 
-                     
-end str_read;
-
-
--- print string to a file
-procedure print(file out_file: TEXT;
-                new_string: in  string) is
-       
-       variable l: line;
-       
-   begin
-      
-     write(l, new_string);
-     writeline(out_file, l);
-                     
-end print;
-
-
--- print character to a file and start new line
-procedure print(file out_file: TEXT;
-                char: in  character) is
-       
-       variable l: line;
-       
-   begin
-      
-     write(l, char);
-     writeline(out_file, l);
-                     
-end print;
-
-
-
--- appends contents of a string to a file until line feed occurs
--- (LF is considered to be the end of the string)
-
-procedure str_write(file out_file: TEXT; 
-                    new_string: in  string) is
- begin
-      
-   for i in new_string'range loop
-      print(out_file, new_string(i));
-      if new_string(i) = LF then -- end of string
-         exit;
-      end if;
-   end loop;               
-                     
-end str_write;
-
-
-
-
-end txt_util;
-
-
-
-
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use std.textio.all;
+
+library work;
+
+package txt_util is
+
+    -- prints a message to the screen
+    procedure print(text: string);
+
+    -- prints the message when active
+    -- useful for debug switches
+    procedure print(active: boolean; text: string);
+
+    -- converts std_logic into a character
+    function chr(sl: std_logic) return character;
+
+    -- converts std_logic into a string (1 to 1)
+    function str(sl: std_logic) return string;
+
+    -- converts std_logic_vector into a string (binary base)
+    function str(slv: std_logic_vector) return string;
+
+    -- converts boolean into a string
+    function str(b: boolean) return string;
+
+    -- converts an integer into a single character
+    -- (can also be used for hex conversion and other bases)
+    function chr(int: integer) return character;
+
+    -- converts integer into string using specified base
+    function str(int: integer; base: integer) return string;
+
+    -- converts integer to string, using base 10
+    function str(int: integer) return string;
+
+    -- convert std_logic_vector into a string in hex format
+    function hstr(slv: std_logic_vector) return string;
+
+
+    -- functions to manipulate strings
+    -----------------------------------
+
+    -- convert a character to upper case
+    function to_upper(c: character) return character;
+
+    -- convert a character to lower case
+    function to_lower(c: character) return character;
+
+    -- convert a string to upper case
+    function to_upper(s: string) return string;
+
+    -- convert a string to lower case
+    function to_lower(s: string) return string;
+
+   
+    
+    -- functions to convert strings into other formats
+    --------------------------------------------------
+    
+    -- converts a character into std_logic
+    function to_std_logic(c: character) return std_logic; 
+    
+    -- converts a string into std_logic_vector
+    function to_std_logic_vector(s: string) return std_logic_vector; 
+
+
+  
+    -- file I/O
+    -----------
+       
+    -- read variable length string from input file
+    procedure str_read(file in_file: TEXT; 
+                       res_string: out string);
+        
+    -- print string to a file and start new line
+    procedure print(file out_file: TEXT;
+                    new_string: in  string);
+    
+    -- print character to a file and start new line
+    procedure print(file out_file: TEXT;
+                    char:       in  character);
+                    
+end txt_util;
+
+
+
+
+package body txt_util is
+
+
+
+
+   -- prints text to the screen
+
+   procedure print(text: string) is
+     variable msg_line: line;
+     begin
+       write(msg_line, text);
+       writeline(output, msg_line);
+   end print;
+
+
+
+
+   -- prints text to the screen when active
+
+   procedure print(active: boolean; text: string)  is
+     begin
+      if active then
+         print(text);
+      end if;
+   end print;
+
+
+   -- converts std_logic into a character
+
+   function chr(sl: std_logic) return character is
+    variable c: character;
+    begin
+      case sl is
+         when 'U' => c:= 'U';
+         when 'X' => c:= 'X';
+         when '0' => c:= '0';
+         when '1' => c:= '1';
+         when 'Z' => c:= 'Z';
+         when 'W' => c:= 'W';
+         when 'L' => c:= 'L';
+         when 'H' => c:= 'H';
+         when '-' => c:= '-';
+      end case;
+    return c;
+   end chr;
+
+
+
+   -- converts std_logic into a string (1 to 1)
+
+   function str(sl: std_logic) return string is
+    variable s: string(1 to 1);
+    begin
+        s(1) := chr(sl);
+        return s;
+   end str;
+
+
+
+   -- converts std_logic_vector into a string (binary base)
+   -- (this also takes care of the fact that the range of
+   --  a string is natural while a std_logic_vector may
+   --  have an integer range)
+
+   function str(slv: std_logic_vector) return string is
+     variable result : string (1 to slv'length);
+     variable r : integer;
+   begin
+     r := 1;
+     for i in slv'range loop
+        result(r) := chr(slv(i));
+        r := r + 1;
+     end loop;
+     return result;
+   end str;
+
+
+   function str(b: boolean) return string is
+
+    begin
+       if b then
+          return "true";
+      else
+        return "false";
+       end if;
+    end str;
+
+
+   -- converts an integer into a character
+   -- for 0 to 9 the obvious mapping is used, higher
+   -- values are mapped to the characters A-Z
+   -- (this is usefull for systems with base > 10)
+   -- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
+
+   function chr(int: integer) return character is
+    variable c: character;
+   begin
+        case int is
+          when  0 => c := '0';
+          when  1 => c := '1';
+          when  2 => c := '2';
+          when  3 => c := '3';
+          when  4 => c := '4';
+          when  5 => c := '5';
+          when  6 => c := '6';
+          when  7 => c := '7';
+          when  8 => c := '8';
+          when  9 => c := '9';
+          when 10 => c := 'A';
+          when 11 => c := 'B';
+          when 12 => c := 'C';
+          when 13 => c := 'D';
+          when 14 => c := 'E';
+          when 15 => c := 'F';
+          when 16 => c := 'G';
+          when 17 => c := 'H';
+          when 18 => c := 'I';
+          when 19 => c := 'J';
+          when 20 => c := 'K';
+          when 21 => c := 'L';
+          when 22 => c := 'M';
+          when 23 => c := 'N';
+          when 24 => c := 'O';
+          when 25 => c := 'P';
+          when 26 => c := 'Q';
+          when 27 => c := 'R';
+          when 28 => c := 'S';
+          when 29 => c := 'T';
+          when 30 => c := 'U';
+          when 31 => c := 'V';
+          when 32 => c := 'W';
+          when 33 => c := 'X';
+          when 34 => c := 'Y';
+          when 35 => c := 'Z';
+          when others => c := '?';
+        end case;
+        return c;
+    end chr;
+
+
+
+   -- convert integer to string using specified base
+   -- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
+
+   function str(int: integer; base: integer) return string is
+
+    variable temp:      string(1 to 10);
+    variable num:       integer;
+    variable abs_int:   integer;
+    variable len:       integer := 1;
+    variable power:     integer := 1;
+
+   begin
+
+    -- bug fix for negative numbers
+    abs_int := abs(int);
+
+    num     := abs_int;
+
+    while num >= base loop                     -- Determine how many
+      len := len + 1;                          -- characters required
+      num := num / base;                       -- to represent the
+    end loop ;                                 -- number.
+
+    for i in len downto 1 loop                 -- Convert the number to
+      temp(i) := chr(abs_int/power mod base);  -- a string starting
+      power := power * base;                   -- with the right hand
+    end loop ;                                 -- side.
+
+    -- return result and add sign if required
+    if int < 0 then
+       return '-'& temp(1 to len);
+     else
+       return temp(1 to len);
+    end if;
+
+   end str;
+
+
+  -- convert integer to string, using base 10
+  function str(int: integer) return string is
+
+   begin
+
+    return str(int, 10) ;
+
+   end str;
+
+
+
+   -- converts a std_logic_vector into a hex string.
+   function hstr(slv: std_logic_vector) return string is
+       variable hexlen: integer;
+       variable longslv : std_logic_vector(67 downto 0) := (others => '0');
+       variable hex : string(1 to 16);
+       variable fourbit : std_logic_vector(3 downto 0);
+     begin
+       hexlen := (slv'left+1)/4;
+       if (slv'left+1) mod 4 /= 0 then
+         hexlen := hexlen + 1;
+       end if;
+       longslv(slv'left downto 0) := slv;
+       for i in (hexlen -1) downto 0 loop
+         fourbit := longslv(((i*4)+3) downto (i*4));
+         case fourbit is
+           when "0000" => hex(hexlen -I) := '0';
+           when "0001" => hex(hexlen -I) := '1';
+           when "0010" => hex(hexlen -I) := '2';
+           when "0011" => hex(hexlen -I) := '3';
+           when "0100" => hex(hexlen -I) := '4';
+           when "0101" => hex(hexlen -I) := '5';
+           when "0110" => hex(hexlen -I) := '6';
+           when "0111" => hex(hexlen -I) := '7';
+           when "1000" => hex(hexlen -I) := '8';
+           when "1001" => hex(hexlen -I) := '9';
+           when "1010" => hex(hexlen -I) := 'A';
+           when "1011" => hex(hexlen -I) := 'B';
+           when "1100" => hex(hexlen -I) := 'C';
+           when "1101" => hex(hexlen -I) := 'D';
+           when "1110" => hex(hexlen -I) := 'E';
+           when "1111" => hex(hexlen -I) := 'F';
+           when "ZZZZ" => hex(hexlen -I) := 'z';
+           when "UUUU" => hex(hexlen -I) := 'u';
+           when "XXXX" => hex(hexlen -I) := 'x';
+           when others => hex(hexlen -I) := '?';
+         end case;
+       end loop;
+       return hex(1 to hexlen);
+     end hstr;
+
+
+
+   -- functions to manipulate strings
+   -----------------------------------
+
+
+   -- convert a character to upper case
+
+   function to_upper(c: character) return character is
+
+      variable u: character;
+
+    begin
+
+       case c is
+        when 'a' => u := 'A';
+        when 'b' => u := 'B';
+        when 'c' => u := 'C';
+        when 'd' => u := 'D';
+        when 'e' => u := 'E';
+        when 'f' => u := 'F';
+        when 'g' => u := 'G';
+        when 'h' => u := 'H';
+        when 'i' => u := 'I';
+        when 'j' => u := 'J';
+        when 'k' => u := 'K';
+        when 'l' => u := 'L';
+        when 'm' => u := 'M';
+        when 'n' => u := 'N';
+        when 'o' => u := 'O';
+        when 'p' => u := 'P';
+        when 'q' => u := 'Q';
+        when 'r' => u := 'R';
+        when 's' => u := 'S';
+        when 't' => u := 'T';
+        when 'u' => u := 'U';
+        when 'v' => u := 'V';
+        when 'w' => u := 'W';
+        when 'x' => u := 'X';
+        when 'y' => u := 'Y';
+        when 'z' => u := 'Z';
+        when others => u := c;
+    end case;
+
+      return u;
+
+   end to_upper;
+
+
+   -- convert a character to lower case
+
+   function to_lower(c: character) return character is
+
+      variable l: character;
+
+    begin
+
+       case c is
+        when 'A' => l := 'a';
+        when 'B' => l := 'b';
+        when 'C' => l := 'c';
+        when 'D' => l := 'd';
+        when 'E' => l := 'e';
+        when 'F' => l := 'f';
+        when 'G' => l := 'g';
+        when 'H' => l := 'h';
+        when 'I' => l := 'i';
+        when 'J' => l := 'j';
+        when 'K' => l := 'k';
+        when 'L' => l := 'l';
+        when 'M' => l := 'm';
+        when 'N' => l := 'n';
+        when 'O' => l := 'o';
+        when 'P' => l := 'p';
+        when 'Q' => l := 'q';
+        when 'R' => l := 'r';
+        when 'S' => l := 's';
+        when 'T' => l := 't';
+        when 'U' => l := 'u';
+        when 'V' => l := 'v';
+        when 'W' => l := 'w';
+        when 'X' => l := 'x';
+        when 'Y' => l := 'y';
+        when 'Z' => l := 'z';
+        when others => l := c;
+    end case;
+
+      return l;
+
+   end to_lower;
+
+
+
+   -- convert a string to upper case
+
+   function to_upper(s: string) return string is
+
+     variable uppercase: string (s'range);
+
+   begin
+
+     for i in s'range loop
+        uppercase(i):= to_upper(s(i));
+     end loop;
+     return uppercase;
+
+   end to_upper;
+
+
+
+   -- convert a string to lower case
+
+   function to_lower(s: string) return string is
+
+     variable lowercase: string (s'range);
+
+   begin
+
+     for i in s'range loop
+        lowercase(i):= to_lower(s(i));
+     end loop;
+     return lowercase;
+
+   end to_lower;
+
+
+
+-- functions to convert strings into other types
+
+
+-- converts a character into a std_logic
+
+function to_std_logic(c: character) return std_logic is 
+    variable sl: std_logic;
+    begin
+      case c is
+        when 'U' => 
+           sl := 'U'; 
+        when 'X' =>
+           sl := 'X';
+        when '0' => 
+           sl := '0';
+        when '1' => 
+           sl := '1';
+        when 'Z' => 
+           sl := 'Z';
+        when 'W' => 
+           sl := 'W';
+        when 'L' => 
+           sl := 'L';
+        when 'H' => 
+           sl := 'H';
+        when '-' => 
+           sl := '-';
+        when others =>
+           sl := 'X'; 
+    end case;
+   return sl;
+  end to_std_logic;
+
+
+-- converts a string into std_logic_vector
+
+function to_std_logic_vector(s: string) return std_logic_vector is 
+  variable slv: std_logic_vector(s'high-s'low downto 0);
+  variable k: integer;
+begin
+   k := s'high-s'low;
+  for i in s'range loop
+     slv(k) := to_std_logic(s(i));
+     k      := k - 1;
+  end loop;
+  return slv;
+end to_std_logic_vector;                                       
+                                       
+                                       
+                                       
+                                       
+                                       
+                                       
+----------------
+--  file I/O  --
+----------------
+
+
+
+-- read variable length string from input file
+     
+procedure str_read(file in_file: TEXT; 
+                   res_string: out string) is
+       
+       variable l:         line;
+       variable c:         character;
+       variable is_string: boolean;
+       
+   begin
+           
+     readline(in_file, l);
+     -- clear the contents of the result string
+     for i in res_string'range loop
+         res_string(i) := ' ';
+     end loop;   
+     -- read all characters of the line, up to the length  
+     -- of the results string
+     for i in res_string'range loop
+        read(l, c, is_string);
+        res_string(i) := c;
+        if not is_string then -- found end of line
+           exit;
+        end if;   
+     end loop; 
+                     
+end str_read;
+
+
+-- print string to a file
+procedure print(file out_file: TEXT;
+                new_string: in  string) is
+       
+       variable l: line;
+       
+   begin
+      
+     write(l, new_string);
+     writeline(out_file, l);
+                     
+end print;
+
+
+-- print character to a file and start new line
+procedure print(file out_file: TEXT;
+                char: in  character) is
+       
+       variable l: line;
+       
+   begin
+      
+     write(l, char);
+     writeline(out_file, l);
+                     
+end print;
+
+
+
+-- appends contents of a string to a file until line feed occurs
+-- (LF is considered to be the end of the string)
+
+procedure str_write(file out_file: TEXT; 
+                    new_string: in  string) is
+ begin
+      
+   for i in new_string'range loop
+      print(out_file, new_string(i));
+      if new_string(i) = LF then -- end of string
+         exit;
+      end if;
+   end loop;               
+                     
+end str_write;
+
+
+
+
+end txt_util;
+
+
+
+
diff --git a/zpu/hdl/zpu4/src/zpuio.vhd b/zpu/hdl/zpu4/src/zpuio.vhd
index 09a1ddd..2c7fd41 100644
--- a/zpu/hdl/zpu4/src/zpuio.vhd
+++ b/zpu/hdl/zpu4/src/zpuio.vhd
@@ -1,232 +1,232 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library work;
-use work.zpu_config.all;
-use work.zpupkg.all;
-
-entity zpuio is
-	port (	areset			: in std_logic;
-			cpu_clk			: in std_logic;
-			clk_status		: in std_logic_vector(2 downto 0);
-			cpu_din			: in std_logic_vector(15 downto 0);
-			cpu_a			: in std_logic_vector(20 downto 0);
-			cpu_we			: in std_logic_vector(1 downto 0);
-			cpu_re			: in std_logic;
-			cpu_dout		: inout std_logic_vector(15 downto 0));
-end zpuio;
-
-architecture behave of zpuio is
-
-signal timer_read : std_logic_vector(7 downto 0);
---signal timer_write : std_logic_vector(7 downto 0);
-signal timer_we : std_logic;
-
-
-signal io_busy : std_logic;
-signal io_read : std_logic_vector(7 downto 0);
---signal io_write : std_logic_vector(7 downto 0);
-signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit);
-signal io_writeEnable : std_logic;
-signal Enable : std_logic;
-
-signal		  din :  std_logic_vector(7 downto 0);
-signal	 		  dout : std_logic_vector(7 downto 0);
-signal			  adr : std_logic_vector(15 downto 0);
-signal			  break : std_logic;
-signal			  we : std_logic;
-signal			  re : std_logic;
-
-
--- uart forwarding...
-
-signal uartTXPending : std_logic;
-signal uartTXCleared : std_logic;
-signal uartData : std_logic_vector(7 downto 0);
-
-signal readingTimer : std_logic;
-
-
-
-
-signal			  mem_busy : std_logic;
-signal			  mem_read : std_logic_vector(wordSize-1 downto 0);
-signal			  mem_write : std_logic_vector(wordSize-1 downto 0);
-signal			  mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);
-signal			  mem_writeEnable : std_logic; 
-signal			  mem_readEnable : std_logic;
-signal			  mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
-
-signal			  dram_mem_busy : std_logic;
-signal			  dram_mem_read : std_logic_vector(wordSize-1 downto 0);
-signal			  dram_mem_write : std_logic_vector(wordSize-1 downto 0);
-signal			  dram_mem_writeEnable : std_logic; 
-signal			  dram_mem_readEnable : std_logic;
-signal			  dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
-
-
-
---signal			  io_mem_read : std_logic_vector(7 downto 0);
---signal			  io_mem_writeEnable : std_logic; 
---signal			  io_mem_readEnable : std_logic;
-signal			  io_readEnable : std_logic;
-
-
-signal			  dram_read : std_logic;
-
-
-
-begin
-
-	io_addr <= mem_addr(maxAddrBit downto minAddrBit);
-	
-	timerinst: timer port map (
-       clk => cpu_clk,
-		 areset => areset,
-		 we => timer_we,
-		 din => mem_write(7 downto 0),
-		 adr => io_addr(4 downto 2),
-		 dout => timer_read);
-
-		zpu: zpu_core port map (
-		clk => cpu_clk ,
-	 	areset => areset,
- 		in_mem_busy => mem_busy, 
- 		mem_read => mem_read,
- 		mem_write => mem_write, 
-		out_mem_addr => mem_addr, 
-		out_mem_writeEnable => mem_writeEnable,  
-		out_mem_readEnable => mem_readEnable,
- 		mem_writeMask => mem_writeMask, 
- 		interrupt => '0',
- 		break  => break);
-
-
-ram_imp: dram port map (
-		clk => cpu_clk ,
-		areset => areset,
- 		mem_busy => dram_mem_busy, 
- 		mem_read => dram_mem_read,
- 		mem_write => mem_write, 
-		mem_addr => mem_addr(maxAddrBit downto 0), 
-		mem_writeEnable => dram_mem_writeEnable,  
-		mem_readEnable => dram_mem_readEnable,
- 		mem_writeMask => mem_writeMask);
-
-
-	
-	fauxUart:
-	process(cpu_clk, areset)
-	begin
-		if areset = '1' then
-			io_busy <= '0';
-			uartTXPending <= '0';
-			timer_we <= '0';
-			io_busy <= '0';
-			uartData <= x"58"; -- 'X'
-			readingTimer <= '0';
-		elsif (cpu_clk'event and cpu_clk = '1') then
-			timer_we <= '0';
-			io_busy <= '0';
-			if uartTXCleared = '1' then
-				uartTXPending <= '0';
-			end if;
-		
-			if io_writeEnable = '1' then
-				if io_addr=x"2028003" then
-					-- Write to UART
-					uartData <= mem_write(7 downto 0);
-					uartTXPending <= '1';
-					io_busy <= '1';
- 				elsif io_addr(12)='1' then
- 					timer_we <= '1';
-					io_busy <= '1';
-				else
---					report "Illegal IO write" severity failure;
-				end if;
-			end if;
-			if (io_readEnable = '1') then
-				if io_addr=x"2028003" then
-					io_read <= (0=>'1',  		-- recieve empty
- 					            1 => uartTXPending,   -- tx full
- 					            others => '0');
- 					io_busy <= '1';
- 				elsif io_addr(12)='1' then
- 					readingTimer <= '1';
- 					io_busy <= '1';
- 				elsif io_addr(11)='1' then
- 					io_read <= ZPU_Frequency;
- 					io_busy <= '1';
-				else
---					report "Illegal IO read" severity failure;
-				end if;
-				
-			else 
-				if (readingTimer = '1') then
-					readingTimer <= '0';
- 					io_read <= timer_read;
- 					io_busy <= '0';
- 				else
-					io_read <= (others => '1');
- 				end if;
-			end if;
-		end if;
-	end process;
-
-
-	forwardUARTOutputToARM:
-	process(cpu_clk, areset)
-	begin
-		if areset = '1' then
-			uartTXCleared <= '0';
-		elsif (cpu_clk = '1' and cpu_clk'event) then
-			if cpu_we(0) = '1' and cpu_a(3 downto 1) = "000" then
-				uartTXCleared <= cpu_din(0);
-			else
-				uartTXCleared <= uartTXCleared;
-			end if;
-		end if;
-	end process;	
-
-	cpu_dout(7 downto 0) <= uartData when (cpu_re = '1' and cpu_a(3 downto 1) = "001") else (others => 'Z');
-	cpu_dout <= (0 => uartTXPending, others => '0') when (cpu_re = '1' and cpu_a(3 downto 1) = "000") else (others => 'Z');
-	
-	dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit);
-	dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit);
-	io_writeEnable <= mem_writeEnable and mem_addr(ioBit);
---	io_readEnable <= mem_readEnable and mem_addr(ioBit);
-	mem_busy <= io_busy or dram_mem_busy or dram_read or io_readEnable;
-
-	-- Memory reads either come from IO or DRAM. We need to pick the right one.
-	memorycontrol:
-	process(cpu_clk, areset)
-	begin
-		if areset = '1' then
-			dram_read <= '0';
-			io_readEnable <= '0';
-
-		
-		elsif (cpu_clk'event and cpu_clk = '1') then
-			mem_read <= (others => '0');
-			if mem_addr(ioBit)='0' and mem_readEnable='1' then
-				dram_read <= '1';
-			end if;
-			if dram_read='1' and dram_mem_busy='0' then
-				dram_read <= '0';
-				mem_read <= dram_mem_read;
-			end if;
-			 
-			if mem_addr(ioBit)='1' and mem_readEnable='1' then
-				io_readEnable <= '1';
-			end if;
-			if io_readEnable='1' and io_busy='0' then
-				io_readEnable <= '0';
-				mem_read(7 downto 0) <= io_read;
-			end if;
-			
-		end if;
-	end process;
-
-
-end behave;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity zpuio is
+	port (	areset			: in std_logic;
+			cpu_clk			: in std_logic;
+			clk_status		: in std_logic_vector(2 downto 0);
+			cpu_din			: in std_logic_vector(15 downto 0);
+			cpu_a			: in std_logic_vector(20 downto 0);
+			cpu_we			: in std_logic_vector(1 downto 0);
+			cpu_re			: in std_logic;
+			cpu_dout		: inout std_logic_vector(15 downto 0));
+end zpuio;
+
+architecture behave of zpuio is
+
+signal timer_read : std_logic_vector(7 downto 0);
+--signal timer_write : std_logic_vector(7 downto 0);
+signal timer_we : std_logic;
+
+
+signal io_busy : std_logic;
+signal io_read : std_logic_vector(7 downto 0);
+--signal io_write : std_logic_vector(7 downto 0);
+signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit);
+signal io_writeEnable : std_logic;
+signal Enable : std_logic;
+
+signal		  din :  std_logic_vector(7 downto 0);
+signal	 		  dout : std_logic_vector(7 downto 0);
+signal			  adr : std_logic_vector(15 downto 0);
+signal			  break : std_logic;
+signal			  we : std_logic;
+signal			  re : std_logic;
+
+
+-- uart forwarding...
+
+signal uartTXPending : std_logic;
+signal uartTXCleared : std_logic;
+signal uartData : std_logic_vector(7 downto 0);
+
+signal readingTimer : std_logic;
+
+
+
+
+signal			  mem_busy : std_logic;
+signal			  mem_read : std_logic_vector(wordSize-1 downto 0);
+signal			  mem_write : std_logic_vector(wordSize-1 downto 0);
+signal			  mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);
+signal			  mem_writeEnable : std_logic; 
+signal			  mem_readEnable : std_logic;
+signal			  mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
+
+signal			  dram_mem_busy : std_logic;
+signal			  dram_mem_read : std_logic_vector(wordSize-1 downto 0);
+signal			  dram_mem_write : std_logic_vector(wordSize-1 downto 0);
+signal			  dram_mem_writeEnable : std_logic; 
+signal			  dram_mem_readEnable : std_logic;
+signal			  dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
+
+
+
+--signal			  io_mem_read : std_logic_vector(7 downto 0);
+--signal			  io_mem_writeEnable : std_logic; 
+--signal			  io_mem_readEnable : std_logic;
+signal			  io_readEnable : std_logic;
+
+
+signal			  dram_read : std_logic;
+
+
+
+begin
+
+	io_addr <= mem_addr(maxAddrBit downto minAddrBit);
+	
+	timerinst: timer port map (
+       clk => cpu_clk,
+		 areset => areset,
+		 we => timer_we,
+		 din => mem_write(7 downto 0),
+		 adr => io_addr(4 downto 2),
+		 dout => timer_read);
+
+		zpu: zpu_core port map (
+		clk => cpu_clk ,
+	 	areset => areset,
+ 		in_mem_busy => mem_busy, 
+ 		mem_read => mem_read,
+ 		mem_write => mem_write, 
+		out_mem_addr => mem_addr, 
+		out_mem_writeEnable => mem_writeEnable,  
+		out_mem_readEnable => mem_readEnable,
+ 		mem_writeMask => mem_writeMask, 
+ 		interrupt => '0',
+ 		break  => break);
+
+
+ram_imp: dram port map (
+		clk => cpu_clk ,
+		areset => areset,
+ 		mem_busy => dram_mem_busy, 
+ 		mem_read => dram_mem_read,
+ 		mem_write => mem_write, 
+		mem_addr => mem_addr(maxAddrBit downto 0), 
+		mem_writeEnable => dram_mem_writeEnable,  
+		mem_readEnable => dram_mem_readEnable,
+ 		mem_writeMask => mem_writeMask);
+
+
+	
+	fauxUart:
+	process(cpu_clk, areset)
+	begin
+		if areset = '1' then
+			io_busy <= '0';
+			uartTXPending <= '0';
+			timer_we <= '0';
+			io_busy <= '0';
+			uartData <= x"58"; -- 'X'
+			readingTimer <= '0';
+		elsif (cpu_clk'event and cpu_clk = '1') then
+			timer_we <= '0';
+			io_busy <= '0';
+			if uartTXCleared = '1' then
+				uartTXPending <= '0';
+			end if;
+		
+			if io_writeEnable = '1' then
+				if io_addr=x"2028003" then
+					-- Write to UART
+					uartData <= mem_write(7 downto 0);
+					uartTXPending <= '1';
+					io_busy <= '1';
+ 				elsif io_addr(12)='1' then
+ 					timer_we <= '1';
+					io_busy <= '1';
+				else
+--					report "Illegal IO write" severity failure;
+				end if;
+			end if;
+			if (io_readEnable = '1') then
+				if io_addr=x"2028003" then
+					io_read <= (0=>'1',  		-- recieve empty
+ 					            1 => uartTXPending,   -- tx full
+ 					            others => '0');
+ 					io_busy <= '1';
+ 				elsif io_addr(12)='1' then
+ 					readingTimer <= '1';
+ 					io_busy <= '1';
+ 				elsif io_addr(11)='1' then
+ 					io_read <= ZPU_Frequency;
+ 					io_busy <= '1';
+				else
+--					report "Illegal IO read" severity failure;
+				end if;
+				
+			else 
+				if (readingTimer = '1') then
+					readingTimer <= '0';
+ 					io_read <= timer_read;
+ 					io_busy <= '0';
+ 				else
+					io_read <= (others => '1');
+ 				end if;
+			end if;
+		end if;
+	end process;
+
+
+	forwardUARTOutputToARM:
+	process(cpu_clk, areset)
+	begin
+		if areset = '1' then
+			uartTXCleared <= '0';
+		elsif (cpu_clk = '1' and cpu_clk'event) then
+			if cpu_we(0) = '1' and cpu_a(3 downto 1) = "000" then
+				uartTXCleared <= cpu_din(0);
+			else
+				uartTXCleared <= uartTXCleared;
+			end if;
+		end if;
+	end process;	
+
+	cpu_dout(7 downto 0) <= uartData when (cpu_re = '1' and cpu_a(3 downto 1) = "001") else (others => 'Z');
+	cpu_dout <= (0 => uartTXPending, others => '0') when (cpu_re = '1' and cpu_a(3 downto 1) = "000") else (others => 'Z');
+	
+	dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit);
+	dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit);
+	io_writeEnable <= mem_writeEnable and mem_addr(ioBit);
+--	io_readEnable <= mem_readEnable and mem_addr(ioBit);
+	mem_busy <= io_busy or dram_mem_busy or dram_read or io_readEnable;
+
+	-- Memory reads either come from IO or DRAM. We need to pick the right one.
+	memorycontrol:
+	process(cpu_clk, areset)
+	begin
+		if areset = '1' then
+			dram_read <= '0';
+			io_readEnable <= '0';
+
+		
+		elsif (cpu_clk'event and cpu_clk = '1') then
+			mem_read <= (others => '0');
+			if mem_addr(ioBit)='0' and mem_readEnable='1' then
+				dram_read <= '1';
+			end if;
+			if dram_read='1' and dram_mem_busy='0' then
+				dram_read <= '0';
+				mem_read <= dram_mem_read;
+			end if;
+			 
+			if mem_addr(ioBit)='1' and mem_readEnable='1' then
+				io_readEnable <= '1';
+			end if;
+			if io_readEnable='1' and io_busy='0' then
+				io_readEnable <= '0';
+				mem_read(7 downto 0) <= io_read;
+			end if;
+			
+		end if;
+	end process;
+
+
+end behave;
diff --git a/zpu/hdl/zy2000/timer.vhd b/zpu/hdl/zy2000/timer.vhd
index bff82f2..735d55c 100644
--- a/zpu/hdl/zy2000/timer.vhd
+++ b/zpu/hdl/zy2000/timer.vhd
@@ -1,137 +1,137 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
- 
-entity timer is
-  port(
-       	clk             : in std_logic;
-		areset			: in std_logic;
-		sample			: in std_logic;
-		reset			: in std_logic;
-		counter			: out std_logic_vector(63 downto 0));
-end timer;
-   
-   
-architecture behave of timer is
-
-signal	c			: std_logic_vector(1 to 7);
-
-signal	cnt		: std_logic_vector(63 downto 0);
-signal	cnt_smp	: std_logic_vector(63 downto 0);
-
-begin
-
-	counter <= cnt_smp;
-
-	process(clk, areset)	-- Carry generation
-	begin
-		if areset = '1' then
-			c <= "0000000";
-		elsif (clk'event and clk = '1') then
-			if reset = '1' then
-				c <= "0000000";
-			else
-				if cnt(7 downto 0) = "11111110" then
-					c(1) <= '1';
-				else
-					c(1) <= '0';
-				end if;
-				if cnt(15 downto 8) = "11111111" then
-					c(2) <= '1';
-				else
-					c(2) <= '0';
-				end if;
-				if cnt(23 downto 16) = "11111111" and c(2) = '1' then
-					c(3) <= '1';
-				else
-					c(3) <= '0';
-				end if;
-				if cnt(31 downto 24) = "11111111" and c(3) = '1' then
-					c(4) <= '1';
-				else
-					c(4) <= '0';
-				end if;
-				if cnt(39 downto 32) = "11111111" and c(4) = '1' then
-					c(5) <= '1';
-				else
-					c(5) <= '0';
-				end if;
-				if cnt(47 downto 40) = "11111111" and c(5) = '1' then
-					c(6) <= '1';
-				else
-					c(6) <= '0';
-				end if;
-				if cnt(55 downto 48) = "11111111" and c(6) = '1' then
-					c(7) <= '1';
-				else
-					c(7) <= '0';
-				end if;
-			end if;	
-		end if;
-	end process;
-	
-	process(clk, areset)
-	begin
-		if areset = '1' then
-			cnt <= (others=>'0');
-		elsif (clk'event and clk = '1') then
-			if reset = '1' then
-				cnt <= (others=>'0');
-			else
-				cnt(7 downto 0) <= cnt(7 downto 0) + '1';
-				if c(1) = '1' then
-					cnt(15 downto 8) <= cnt(15 downto 8) + '1';
-				else
-					cnt(15 downto 8) <= cnt(15 downto 8);
-				end if;
-				if c(2) = '1' and c(1) = '1' then
-					cnt(23 downto 16) <= cnt(23 downto 16) + '1';
-				else
-					cnt(23 downto 16) <= cnt(23 downto 16);
-				end if;
-				if c(3) = '1' and c(1) = '1' then
-					cnt(31 downto 24) <= cnt(31 downto 24) + '1';
-				else
-					cnt(31 downto 24) <= cnt(31 downto 24);
-				end if;
-				if c(4) = '1' and c(1) = '1' then
-					cnt(39 downto 32) <= cnt(39 downto 32) + '1';
-				else
-					cnt(39 downto 32) <= cnt(39 downto 32);
-				end if;
-				if c(5) = '1' and c(1) = '1' then
-					cnt(47 downto 40) <= cnt(47 downto 40) + '1';
-				else
-					cnt(47 downto 40) <= cnt(47 downto 40);
-				end if;
-				if c(6) = '1' and c(1) = '1' then
-					cnt(55 downto 48) <= cnt(55 downto 48) + '1';
-				else
-					cnt(55 downto 48) <= cnt(55 downto 48);
-				end if;
-				if c(7) = '1' and c(1) = '1' then
-					cnt(63 downto 56) <= cnt(63 downto 56) + '1';
-				else
-					cnt(63 downto 56) <= cnt(63 downto 56);
-				end if;
-			end if;
-		end if;
-	end process;
-	
-	process(clk, areset)
-	begin
-		if areset = '1' then
-			cnt_smp <= (others=>'0');
-		elsif (clk'event and clk = '1') then
-			if reset = '1' then
-				cnt_smp <= (others=>'0');
-			elsif sample = '1' then
-				cnt_smp <= cnt;
-			else
-				cnt_smp <= cnt_smp;
-			end if;
-		end if;
-	end process;
-	
-end behave;
- 
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+ 
+entity timer is
+  port(
+       	clk             : in std_logic;
+		areset			: in std_logic;
+		sample			: in std_logic;
+		reset			: in std_logic;
+		counter			: out std_logic_vector(63 downto 0));
+end timer;
+   
+   
+architecture behave of timer is
+
+signal	c			: std_logic_vector(1 to 7);
+
+signal	cnt		: std_logic_vector(63 downto 0);
+signal	cnt_smp	: std_logic_vector(63 downto 0);
+
+begin
+
+	counter <= cnt_smp;
+
+	process(clk, areset)	-- Carry generation
+	begin
+		if areset = '1' then
+			c <= "0000000";
+		elsif (clk'event and clk = '1') then
+			if reset = '1' then
+				c <= "0000000";
+			else
+				if cnt(7 downto 0) = "11111110" then
+					c(1) <= '1';
+				else
+					c(1) <= '0';
+				end if;
+				if cnt(15 downto 8) = "11111111" then
+					c(2) <= '1';
+				else
+					c(2) <= '0';
+				end if;
+				if cnt(23 downto 16) = "11111111" and c(2) = '1' then
+					c(3) <= '1';
+				else
+					c(3) <= '0';
+				end if;
+				if cnt(31 downto 24) = "11111111" and c(3) = '1' then
+					c(4) <= '1';
+				else
+					c(4) <= '0';
+				end if;
+				if cnt(39 downto 32) = "11111111" and c(4) = '1' then
+					c(5) <= '1';
+				else
+					c(5) <= '0';
+				end if;
+				if cnt(47 downto 40) = "11111111" and c(5) = '1' then
+					c(6) <= '1';
+				else
+					c(6) <= '0';
+				end if;
+				if cnt(55 downto 48) = "11111111" and c(6) = '1' then
+					c(7) <= '1';
+				else
+					c(7) <= '0';
+				end if;
+			end if;	
+		end if;
+	end process;
+	
+	process(clk, areset)
+	begin
+		if areset = '1' then
+			cnt <= (others=>'0');
+		elsif (clk'event and clk = '1') then
+			if reset = '1' then
+				cnt <= (others=>'0');
+			else
+				cnt(7 downto 0) <= cnt(7 downto 0) + '1';
+				if c(1) = '1' then
+					cnt(15 downto 8) <= cnt(15 downto 8) + '1';
+				else
+					cnt(15 downto 8) <= cnt(15 downto 8);
+				end if;
+				if c(2) = '1' and c(1) = '1' then
+					cnt(23 downto 16) <= cnt(23 downto 16) + '1';
+				else
+					cnt(23 downto 16) <= cnt(23 downto 16);
+				end if;
+				if c(3) = '1' and c(1) = '1' then
+					cnt(31 downto 24) <= cnt(31 downto 24) + '1';
+				else
+					cnt(31 downto 24) <= cnt(31 downto 24);
+				end if;
+				if c(4) = '1' and c(1) = '1' then
+					cnt(39 downto 32) <= cnt(39 downto 32) + '1';
+				else
+					cnt(39 downto 32) <= cnt(39 downto 32);
+				end if;
+				if c(5) = '1' and c(1) = '1' then
+					cnt(47 downto 40) <= cnt(47 downto 40) + '1';
+				else
+					cnt(47 downto 40) <= cnt(47 downto 40);
+				end if;
+				if c(6) = '1' and c(1) = '1' then
+					cnt(55 downto 48) <= cnt(55 downto 48) + '1';
+				else
+					cnt(55 downto 48) <= cnt(55 downto 48);
+				end if;
+				if c(7) = '1' and c(1) = '1' then
+					cnt(63 downto 56) <= cnt(63 downto 56) + '1';
+				else
+					cnt(63 downto 56) <= cnt(63 downto 56);
+				end if;
+			end if;
+		end if;
+	end process;
+	
+	process(clk, areset)
+	begin
+		if areset = '1' then
+			cnt_smp <= (others=>'0');
+		elsif (clk'event and clk = '1') then
+			if reset = '1' then
+				cnt_smp <= (others=>'0');
+			elsif sample = '1' then
+				cnt_smp <= cnt;
+			else
+				cnt_smp <= cnt_smp;
+			end if;
+		end if;
+	end process;
+	
+end behave;
+ 
diff --git a/zpu/hdl/zy2000/trace.vhd b/zpu/hdl/zy2000/trace.vhd
index bc5279f..ec6be57 100644
--- a/zpu/hdl/zy2000/trace.vhd
+++ b/zpu/hdl/zy2000/trace.vhd
@@ -1,84 +1,84 @@
-library ieee;
-use ieee.std_logic_1164.all;
---use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-use std.textio.all;
-
-library work;
-use work.zpu_config.all;
-use work.zpupkg.all;
-use work.txt_util.all;
- 
- 
-entity trace is
-  generic (
-           log_file:       string  := "trace.txt"
-          );
-  port(
-       	clk         : in std_logic;
-       	begin_inst  : in std_logic;
-       	pc          : in std_logic_vector(maxAddrBitIncIO downto 0);
-		opcode		: in std_logic_vector(7 downto 0);
-		sp			: in std_logic_vector(maxAddrBitIncIO downto 2);
-		memA		: in std_logic_vector(wordSize-1 downto 0);
-		memB		: in std_logic_vector(wordSize-1 downto 0);
-		busy  : in std_logic;
-		intSp		: in std_logic_vector(stack_bits-1 downto 0)
-		);
-end trace;
-   
-   
-architecture behave of trace is
-  
-  
-file 		l_file		: TEXT open write_mode is log_file;
-
-
-begin
-
-
--- write data and control information to a file
-
-receive_data: process
-
-variable l: line;
-variable t	: std_logic_vector(wordSize-1 downto 0);
-variable t2	: std_logic_vector(maxAddrBitIncIO downto 0);
-variable counter : std_logic_vector(63 downto 0);
-   
-   
-   
-begin                                       
-
-	t:= (others => '0');
-	t2:= (others => '0');
-
-counter := (others => '0');
-   -- print header for the logfile
-   print(l_file, "#pc,opcode,sp,top_of_stack ");
-   print(l_file, "#----------");
-   print(l_file, " ");
-
-	wait until clk = '1';
-	wait until clk = '0'; 
-
-   while true loop
-
-		counter := counter + 1;
-		if begin_inst = '1' then
-			t(maxAddrBitIncIO downto 2):=sp;
-			t2:=pc;
-     		print(l_file, "0x" & hstr(t2) & " 0x" & hstr(opcode) & " 0x" & hstr(t) & " 0x" & hstr(memA) & " 0x" & hstr(memB) & " 0x" & hstr(intSp) & " 0x" & hstr(counter));
-		end if;
-		
-     	wait until clk = '0';
-    
-   end loop;
-
- end process receive_data;
-
-
-
-end behave;
- 
+library ieee;
+use ieee.std_logic_1164.all;
+--use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+use std.textio.all;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+use work.txt_util.all;
+ 
+ 
+entity trace is
+  generic (
+           log_file:       string  := "trace.txt"
+          );
+  port(
+       	clk         : in std_logic;
+       	begin_inst  : in std_logic;
+       	pc          : in std_logic_vector(maxAddrBitIncIO downto 0);
+		opcode		: in std_logic_vector(7 downto 0);
+		sp			: in std_logic_vector(maxAddrBitIncIO downto 2);
+		memA		: in std_logic_vector(wordSize-1 downto 0);
+		memB		: in std_logic_vector(wordSize-1 downto 0);
+		busy  : in std_logic;
+		intSp		: in std_logic_vector(stack_bits-1 downto 0)
+		);
+end trace;
+   
+   
+architecture behave of trace is
+  
+  
+file 		l_file		: TEXT open write_mode is log_file;
+
+
+begin
+
+
+-- write data and control information to a file
+
+receive_data: process
+
+variable l: line;
+variable t	: std_logic_vector(wordSize-1 downto 0);
+variable t2	: std_logic_vector(maxAddrBitIncIO downto 0);
+variable counter : std_logic_vector(63 downto 0);
+   
+   
+   
+begin                                       
+
+	t:= (others => '0');
+	t2:= (others => '0');
+
+counter := (others => '0');
+   -- print header for the logfile
+   print(l_file, "#pc,opcode,sp,top_of_stack ");
+   print(l_file, "#----------");
+   print(l_file, " ");
+
+	wait until clk = '1';
+	wait until clk = '0'; 
+
+   while true loop
+
+		counter := counter + 1;
+		if begin_inst = '1' then
+			t(maxAddrBitIncIO downto 2):=sp;
+			t2:=pc;
+     		print(l_file, "0x" & hstr(t2) & " 0x" & hstr(opcode) & " 0x" & hstr(t) & " 0x" & hstr(memA) & " 0x" & hstr(memB) & " 0x" & hstr(intSp) & " 0x" & hstr(counter));
+		end if;
+		
+     	wait until clk = '0';
+    
+   end loop;
+
+ end process receive_data;
+
+
+
+end behave;
+ 
diff --git a/zpu/hdl/zy2000/txt_util.vhd b/zpu/hdl/zy2000/txt_util.vhd
index d3bf01a..40d39b9 100644
--- a/zpu/hdl/zy2000/txt_util.vhd
+++ b/zpu/hdl/zy2000/txt_util.vhd
@@ -1,587 +1,587 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use std.textio.all;
-
-library work;
-
-package txt_util is
-
-    -- prints a message to the screen
-    procedure print(text: string);
-
-    -- prints the message when active
-    -- useful for debug switches
-    procedure print(active: boolean; text: string);
-
-    -- converts std_logic into a character
-    function chr(sl: std_logic) return character;
-
-    -- converts std_logic into a string (1 to 1)
-    function str(sl: std_logic) return string;
-
-    -- converts std_logic_vector into a string (binary base)
-    function str(slv: std_logic_vector) return string;
-
-    -- converts boolean into a string
-    function str(b: boolean) return string;
-
-    -- converts an integer into a single character
-    -- (can also be used for hex conversion and other bases)
-    function chr(int: integer) return character;
-
-    -- converts integer into string using specified base
-    function str(int: integer; base: integer) return string;
-
-    -- converts integer to string, using base 10
-    function str(int: integer) return string;
-
-    -- convert std_logic_vector into a string in hex format
-    function hstr(slv: std_logic_vector) return string;
-
-
-    -- functions to manipulate strings
-    -----------------------------------
-
-    -- convert a character to upper case
-    function to_upper(c: character) return character;
-
-    -- convert a character to lower case
-    function to_lower(c: character) return character;
-
-    -- convert a string to upper case
-    function to_upper(s: string) return string;
-
-    -- convert a string to lower case
-    function to_lower(s: string) return string;
-
-   
-    
-    -- functions to convert strings into other formats
-    --------------------------------------------------
-    
-    -- converts a character into std_logic
-    function to_std_logic(c: character) return std_logic; 
-    
-    -- converts a string into std_logic_vector
-    function to_std_logic_vector(s: string) return std_logic_vector; 
-
-
-  
-    -- file I/O
-    -----------
-       
-    -- read variable length string from input file
-    procedure str_read(file in_file: TEXT; 
-                       res_string: out string);
-        
-    -- print string to a file and start new line
-    procedure print(file out_file: TEXT;
-                    new_string: in  string);
-    
-    -- print character to a file and start new line
-    procedure print(file out_file: TEXT;
-                    char:       in  character);
-                    
-end txt_util;
-
-
-
-
-package body txt_util is
-
-
-
-
-   -- prints text to the screen
-
-   procedure print(text: string) is
-     variable msg_line: line;
-     begin
-       write(msg_line, text);
-       writeline(output, msg_line);
-   end print;
-
-
-
-
-   -- prints text to the screen when active
-
-   procedure print(active: boolean; text: string)  is
-     begin
-      if active then
-         print(text);
-      end if;
-   end print;
-
-
-   -- converts std_logic into a character
-
-   function chr(sl: std_logic) return character is
-    variable c: character;
-    begin
-      case sl is
-         when 'U' => c:= 'U';
-         when 'X' => c:= 'X';
-         when '0' => c:= '0';
-         when '1' => c:= '1';
-         when 'Z' => c:= 'Z';
-         when 'W' => c:= 'W';
-         when 'L' => c:= 'L';
-         when 'H' => c:= 'H';
-         when '-' => c:= '-';
-      end case;
-    return c;
-   end chr;
-
-
-
-   -- converts std_logic into a string (1 to 1)
-
-   function str(sl: std_logic) return string is
-    variable s: string(1 to 1);
-    begin
-        s(1) := chr(sl);
-        return s;
-   end str;
-
-
-
-   -- converts std_logic_vector into a string (binary base)
-   -- (this also takes care of the fact that the range of
-   --  a string is natural while a std_logic_vector may
-   --  have an integer range)
-
-   function str(slv: std_logic_vector) return string is
-     variable result : string (1 to slv'length);
-     variable r : integer;
-   begin
-     r := 1;
-     for i in slv'range loop
-        result(r) := chr(slv(i));
-        r := r + 1;
-     end loop;
-     return result;
-   end str;
-
-
-   function str(b: boolean) return string is
-
-    begin
-       if b then
-          return "true";
-      else
-        return "false";
-       end if;
-    end str;
-
-
-   -- converts an integer into a character
-   -- for 0 to 9 the obvious mapping is used, higher
-   -- values are mapped to the characters A-Z
-   -- (this is usefull for systems with base > 10)
-   -- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
-
-   function chr(int: integer) return character is
-    variable c: character;
-   begin
-        case int is
-          when  0 => c := '0';
-          when  1 => c := '1';
-          when  2 => c := '2';
-          when  3 => c := '3';
-          when  4 => c := '4';
-          when  5 => c := '5';
-          when  6 => c := '6';
-          when  7 => c := '7';
-          when  8 => c := '8';
-          when  9 => c := '9';
-          when 10 => c := 'A';
-          when 11 => c := 'B';
-          when 12 => c := 'C';
-          when 13 => c := 'D';
-          when 14 => c := 'E';
-          when 15 => c := 'F';
-          when 16 => c := 'G';
-          when 17 => c := 'H';
-          when 18 => c := 'I';
-          when 19 => c := 'J';
-          when 20 => c := 'K';
-          when 21 => c := 'L';
-          when 22 => c := 'M';
-          when 23 => c := 'N';
-          when 24 => c := 'O';
-          when 25 => c := 'P';
-          when 26 => c := 'Q';
-          when 27 => c := 'R';
-          when 28 => c := 'S';
-          when 29 => c := 'T';
-          when 30 => c := 'U';
-          when 31 => c := 'V';
-          when 32 => c := 'W';
-          when 33 => c := 'X';
-          when 34 => c := 'Y';
-          when 35 => c := 'Z';
-          when others => c := '?';
-        end case;
-        return c;
-    end chr;
-
-
-
-   -- convert integer to string using specified base
-   -- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
-
-   function str(int: integer; base: integer) return string is
-
-    variable temp:      string(1 to 10);
-    variable num:       integer;
-    variable abs_int:   integer;
-    variable len:       integer := 1;
-    variable power:     integer := 1;
-
-   begin
-
-    -- bug fix for negative numbers
-    abs_int := abs(int);
-
-    num     := abs_int;
-
-    while num >= base loop                     -- Determine how many
-      len := len + 1;                          -- characters required
-      num := num / base;                       -- to represent the
-    end loop ;                                 -- number.
-
-    for i in len downto 1 loop                 -- Convert the number to
-      temp(i) := chr(abs_int/power mod base);  -- a string starting
-      power := power * base;                   -- with the right hand
-    end loop ;                                 -- side.
-
-    -- return result and add sign if required
-    if int < 0 then
-       return '-'& temp(1 to len);
-     else
-       return temp(1 to len);
-    end if;
-
-   end str;
-
-
-  -- convert integer to string, using base 10
-  function str(int: integer) return string is
-
-   begin
-
-    return str(int, 10) ;
-
-   end str;
-
-
-
-   -- converts a std_logic_vector into a hex string.
-   function hstr(slv: std_logic_vector) return string is
-       variable hexlen: integer;
-       variable longslv : std_logic_vector(67 downto 0) := (others => '0');
-       variable hex : string(1 to 16);
-       variable fourbit : std_logic_vector(3 downto 0);
-     begin
-       hexlen := (slv'left+1)/4;
-       if (slv'left+1) mod 4 /= 0 then
-         hexlen := hexlen + 1;
-       end if;
-       longslv(slv'left downto 0) := slv;
-       for i in (hexlen -1) downto 0 loop
-         fourbit := longslv(((i*4)+3) downto (i*4));
-         case fourbit is
-           when "0000" => hex(hexlen -I) := '0';
-           when "0001" => hex(hexlen -I) := '1';
-           when "0010" => hex(hexlen -I) := '2';
-           when "0011" => hex(hexlen -I) := '3';
-           when "0100" => hex(hexlen -I) := '4';
-           when "0101" => hex(hexlen -I) := '5';
-           when "0110" => hex(hexlen -I) := '6';
-           when "0111" => hex(hexlen -I) := '7';
-           when "1000" => hex(hexlen -I) := '8';
-           when "1001" => hex(hexlen -I) := '9';
-           when "1010" => hex(hexlen -I) := 'A';
-           when "1011" => hex(hexlen -I) := 'B';
-           when "1100" => hex(hexlen -I) := 'C';
-           when "1101" => hex(hexlen -I) := 'D';
-           when "1110" => hex(hexlen -I) := 'E';
-           when "1111" => hex(hexlen -I) := 'F';
-           when "ZZZZ" => hex(hexlen -I) := 'z';
-           when "UUUU" => hex(hexlen -I) := 'u';
-           when "XXXX" => hex(hexlen -I) := 'x';
-           when others => hex(hexlen -I) := '?';
-         end case;
-       end loop;
-       return hex(1 to hexlen);
-     end hstr;
-
-
-
-   -- functions to manipulate strings
-   -----------------------------------
-
-
-   -- convert a character to upper case
-
-   function to_upper(c: character) return character is
-
-      variable u: character;
-
-    begin
-
-       case c is
-        when 'a' => u := 'A';
-        when 'b' => u := 'B';
-        when 'c' => u := 'C';
-        when 'd' => u := 'D';
-        when 'e' => u := 'E';
-        when 'f' => u := 'F';
-        when 'g' => u := 'G';
-        when 'h' => u := 'H';
-        when 'i' => u := 'I';
-        when 'j' => u := 'J';
-        when 'k' => u := 'K';
-        when 'l' => u := 'L';
-        when 'm' => u := 'M';
-        when 'n' => u := 'N';
-        when 'o' => u := 'O';
-        when 'p' => u := 'P';
-        when 'q' => u := 'Q';
-        when 'r' => u := 'R';
-        when 's' => u := 'S';
-        when 't' => u := 'T';
-        when 'u' => u := 'U';
-        when 'v' => u := 'V';
-        when 'w' => u := 'W';
-        when 'x' => u := 'X';
-        when 'y' => u := 'Y';
-        when 'z' => u := 'Z';
-        when others => u := c;
-    end case;
-
-      return u;
-
-   end to_upper;
-
-
-   -- convert a character to lower case
-
-   function to_lower(c: character) return character is
-
-      variable l: character;
-
-    begin
-
-       case c is
-        when 'A' => l := 'a';
-        when 'B' => l := 'b';
-        when 'C' => l := 'c';
-        when 'D' => l := 'd';
-        when 'E' => l := 'e';
-        when 'F' => l := 'f';
-        when 'G' => l := 'g';
-        when 'H' => l := 'h';
-        when 'I' => l := 'i';
-        when 'J' => l := 'j';
-        when 'K' => l := 'k';
-        when 'L' => l := 'l';
-        when 'M' => l := 'm';
-        when 'N' => l := 'n';
-        when 'O' => l := 'o';
-        when 'P' => l := 'p';
-        when 'Q' => l := 'q';
-        when 'R' => l := 'r';
-        when 'S' => l := 's';
-        when 'T' => l := 't';
-        when 'U' => l := 'u';
-        when 'V' => l := 'v';
-        when 'W' => l := 'w';
-        when 'X' => l := 'x';
-        when 'Y' => l := 'y';
-        when 'Z' => l := 'z';
-        when others => l := c;
-    end case;
-
-      return l;
-
-   end to_lower;
-
-
-
-   -- convert a string to upper case
-
-   function to_upper(s: string) return string is
-
-     variable uppercase: string (s'range);
-
-   begin
-
-     for i in s'range loop
-        uppercase(i):= to_upper(s(i));
-     end loop;
-     return uppercase;
-
-   end to_upper;
-
-
-
-   -- convert a string to lower case
-
-   function to_lower(s: string) return string is
-
-     variable lowercase: string (s'range);
-
-   begin
-
-     for i in s'range loop
-        lowercase(i):= to_lower(s(i));
-     end loop;
-     return lowercase;
-
-   end to_lower;
-
-
-
--- functions to convert strings into other types
-
-
--- converts a character into a std_logic
-
-function to_std_logic(c: character) return std_logic is 
-    variable sl: std_logic;
-    begin
-      case c is
-        when 'U' => 
-           sl := 'U'; 
-        when 'X' =>
-           sl := 'X';
-        when '0' => 
-           sl := '0';
-        when '1' => 
-           sl := '1';
-        when 'Z' => 
-           sl := 'Z';
-        when 'W' => 
-           sl := 'W';
-        when 'L' => 
-           sl := 'L';
-        when 'H' => 
-           sl := 'H';
-        when '-' => 
-           sl := '-';
-        when others =>
-           sl := 'X'; 
-    end case;
-   return sl;
-  end to_std_logic;
-
-
--- converts a string into std_logic_vector
-
-function to_std_logic_vector(s: string) return std_logic_vector is 
-  variable slv: std_logic_vector(s'high-s'low downto 0);
-  variable k: integer;
-begin
-   k := s'high-s'low;
-  for i in s'range loop
-     slv(k) := to_std_logic(s(i));
-     k      := k - 1;
-  end loop;
-  return slv;
-end to_std_logic_vector;                                       
-                                       
-                                       
-                                       
-                                       
-                                       
-                                       
-----------------
---  file I/O  --
-----------------
-
-
-
--- read variable length string from input file
-     
-procedure str_read(file in_file: TEXT; 
-                   res_string: out string) is
-       
-       variable l:         line;
-       variable c:         character;
-       variable is_string: boolean;
-       
-   begin
-           
-     readline(in_file, l);
-     -- clear the contents of the result string
-     for i in res_string'range loop
-         res_string(i) := ' ';
-     end loop;   
-     -- read all characters of the line, up to the length  
-     -- of the results string
-     for i in res_string'range loop
-        read(l, c, is_string);
-        res_string(i) := c;
-        if not is_string then -- found end of line
-           exit;
-        end if;   
-     end loop; 
-                     
-end str_read;
-
-
--- print string to a file
-procedure print(file out_file: TEXT;
-                new_string: in  string) is
-       
-       variable l: line;
-       
-   begin
-      
-     write(l, new_string);
-     writeline(out_file, l);
-                     
-end print;
-
-
--- print character to a file and start new line
-procedure print(file out_file: TEXT;
-                char: in  character) is
-       
-       variable l: line;
-       
-   begin
-      
-     write(l, char);
-     writeline(out_file, l);
-                     
-end print;
-
-
-
--- appends contents of a string to a file until line feed occurs
--- (LF is considered to be the end of the string)
-
-procedure str_write(file out_file: TEXT; 
-                    new_string: in  string) is
- begin
-      
-   for i in new_string'range loop
-      print(out_file, new_string(i));
-      if new_string(i) = LF then -- end of string
-         exit;
-      end if;
-   end loop;               
-                     
-end str_write;
-
-
-
-
-end txt_util;
-
-
-
-
+library ieee;
+use ieee.std_logic_1164.all;
+use std.textio.all;
+
+library work;
+
+package txt_util is
+
+    -- prints a message to the screen
+    procedure print(text: string);
+
+    -- prints the message when active
+    -- useful for debug switches
+    procedure print(active: boolean; text: string);
+
+    -- converts std_logic into a character
+    function chr(sl: std_logic) return character;
+
+    -- converts std_logic into a string (1 to 1)
+    function str(sl: std_logic) return string;
+
+    -- converts std_logic_vector into a string (binary base)
+    function str(slv: std_logic_vector) return string;
+
+    -- converts boolean into a string
+    function str(b: boolean) return string;
+
+    -- converts an integer into a single character
+    -- (can also be used for hex conversion and other bases)
+    function chr(int: integer) return character;
+
+    -- converts integer into string using specified base
+    function str(int: integer; base: integer) return string;
+
+    -- converts integer to string, using base 10
+    function str(int: integer) return string;
+
+    -- convert std_logic_vector into a string in hex format
+    function hstr(slv: std_logic_vector) return string;
+
+
+    -- functions to manipulate strings
+    -----------------------------------
+
+    -- convert a character to upper case
+    function to_upper(c: character) return character;
+
+    -- convert a character to lower case
+    function to_lower(c: character) return character;
+
+    -- convert a string to upper case
+    function to_upper(s: string) return string;
+
+    -- convert a string to lower case
+    function to_lower(s: string) return string;
+
+   
+    
+    -- functions to convert strings into other formats
+    --------------------------------------------------
+    
+    -- converts a character into std_logic
+    function to_std_logic(c: character) return std_logic; 
+    
+    -- converts a string into std_logic_vector
+    function to_std_logic_vector(s: string) return std_logic_vector; 
+
+
+  
+    -- file I/O
+    -----------
+       
+    -- read variable length string from input file
+    procedure str_read(file in_file: TEXT; 
+                       res_string: out string);
+        
+    -- print string to a file and start new line
+    procedure print(file out_file: TEXT;
+                    new_string: in  string);
+    
+    -- print character to a file and start new line
+    procedure print(file out_file: TEXT;
+                    char:       in  character);
+                    
+end txt_util;
+
+
+
+
+package body txt_util is
+
+
+
+
+   -- prints text to the screen
+
+   procedure print(text: string) is
+     variable msg_line: line;
+     begin
+       write(msg_line, text);
+       writeline(output, msg_line);
+   end print;
+
+
+
+
+   -- prints text to the screen when active
+
+   procedure print(active: boolean; text: string)  is
+     begin
+      if active then
+         print(text);
+      end if;
+   end print;
+
+
+   -- converts std_logic into a character
+
+   function chr(sl: std_logic) return character is
+    variable c: character;
+    begin
+      case sl is
+         when 'U' => c:= 'U';
+         when 'X' => c:= 'X';
+         when '0' => c:= '0';
+         when '1' => c:= '1';
+         when 'Z' => c:= 'Z';
+         when 'W' => c:= 'W';
+         when 'L' => c:= 'L';
+         when 'H' => c:= 'H';
+         when '-' => c:= '-';
+      end case;
+    return c;
+   end chr;
+
+
+
+   -- converts std_logic into a string (1 to 1)
+
+   function str(sl: std_logic) return string is
+    variable s: string(1 to 1);
+    begin
+        s(1) := chr(sl);
+        return s;
+   end str;
+
+
+
+   -- converts std_logic_vector into a string (binary base)
+   -- (this also takes care of the fact that the range of
+   --  a string is natural while a std_logic_vector may
+   --  have an integer range)
+
+   function str(slv: std_logic_vector) return string is
+     variable result : string (1 to slv'length);
+     variable r : integer;
+   begin
+     r := 1;
+     for i in slv'range loop
+        result(r) := chr(slv(i));
+        r := r + 1;
+     end loop;
+     return result;
+   end str;
+
+
+   function str(b: boolean) return string is
+
+    begin
+       if b then
+          return "true";
+      else
+        return "false";
+       end if;
+    end str;
+
+
+   -- converts an integer into a character
+   -- for 0 to 9 the obvious mapping is used, higher
+   -- values are mapped to the characters A-Z
+   -- (this is usefull for systems with base > 10)
+   -- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
+
+   function chr(int: integer) return character is
+    variable c: character;
+   begin
+        case int is
+          when  0 => c := '0';
+          when  1 => c := '1';
+          when  2 => c := '2';
+          when  3 => c := '3';
+          when  4 => c := '4';
+          when  5 => c := '5';
+          when  6 => c := '6';
+          when  7 => c := '7';
+          when  8 => c := '8';
+          when  9 => c := '9';
+          when 10 => c := 'A';
+          when 11 => c := 'B';
+          when 12 => c := 'C';
+          when 13 => c := 'D';
+          when 14 => c := 'E';
+          when 15 => c := 'F';
+          when 16 => c := 'G';
+          when 17 => c := 'H';
+          when 18 => c := 'I';
+          when 19 => c := 'J';
+          when 20 => c := 'K';
+          when 21 => c := 'L';
+          when 22 => c := 'M';
+          when 23 => c := 'N';
+          when 24 => c := 'O';
+          when 25 => c := 'P';
+          when 26 => c := 'Q';
+          when 27 => c := 'R';
+          when 28 => c := 'S';
+          when 29 => c := 'T';
+          when 30 => c := 'U';
+          when 31 => c := 'V';
+          when 32 => c := 'W';
+          when 33 => c := 'X';
+          when 34 => c := 'Y';
+          when 35 => c := 'Z';
+          when others => c := '?';
+        end case;
+        return c;
+    end chr;
+
+
+
+   -- convert integer to string using specified base
+   -- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
+
+   function str(int: integer; base: integer) return string is
+
+    variable temp:      string(1 to 10);
+    variable num:       integer;
+    variable abs_int:   integer;
+    variable len:       integer := 1;
+    variable power:     integer := 1;
+
+   begin
+
+    -- bug fix for negative numbers
+    abs_int := abs(int);
+
+    num     := abs_int;
+
+    while num >= base loop                     -- Determine how many
+      len := len + 1;                          -- characters required
+      num := num / base;                       -- to represent the
+    end loop ;                                 -- number.
+
+    for i in len downto 1 loop                 -- Convert the number to
+      temp(i) := chr(abs_int/power mod base);  -- a string starting
+      power := power * base;                   -- with the right hand
+    end loop ;                                 -- side.
+
+    -- return result and add sign if required
+    if int < 0 then
+       return '-'& temp(1 to len);
+     else
+       return temp(1 to len);
+    end if;
+
+   end str;
+
+
+  -- convert integer to string, using base 10
+  function str(int: integer) return string is
+
+   begin
+
+    return str(int, 10) ;
+
+   end str;
+
+
+
+   -- converts a std_logic_vector into a hex string.
+   function hstr(slv: std_logic_vector) return string is
+       variable hexlen: integer;
+       variable longslv : std_logic_vector(67 downto 0) := (others => '0');
+       variable hex : string(1 to 16);
+       variable fourbit : std_logic_vector(3 downto 0);
+     begin
+       hexlen := (slv'left+1)/4;
+       if (slv'left+1) mod 4 /= 0 then
+         hexlen := hexlen + 1;
+       end if;
+       longslv(slv'left downto 0) := slv;
+       for i in (hexlen -1) downto 0 loop
+         fourbit := longslv(((i*4)+3) downto (i*4));
+         case fourbit is
+           when "0000" => hex(hexlen -I) := '0';
+           when "0001" => hex(hexlen -I) := '1';
+           when "0010" => hex(hexlen -I) := '2';
+           when "0011" => hex(hexlen -I) := '3';
+           when "0100" => hex(hexlen -I) := '4';
+           when "0101" => hex(hexlen -I) := '5';
+           when "0110" => hex(hexlen -I) := '6';
+           when "0111" => hex(hexlen -I) := '7';
+           when "1000" => hex(hexlen -I) := '8';
+           when "1001" => hex(hexlen -I) := '9';
+           when "1010" => hex(hexlen -I) := 'A';
+           when "1011" => hex(hexlen -I) := 'B';
+           when "1100" => hex(hexlen -I) := 'C';
+           when "1101" => hex(hexlen -I) := 'D';
+           when "1110" => hex(hexlen -I) := 'E';
+           when "1111" => hex(hexlen -I) := 'F';
+           when "ZZZZ" => hex(hexlen -I) := 'z';
+           when "UUUU" => hex(hexlen -I) := 'u';
+           when "XXXX" => hex(hexlen -I) := 'x';
+           when others => hex(hexlen -I) := '?';
+         end case;
+       end loop;
+       return hex(1 to hexlen);
+     end hstr;
+
+
+
+   -- functions to manipulate strings
+   -----------------------------------
+
+
+   -- convert a character to upper case
+
+   function to_upper(c: character) return character is
+
+      variable u: character;
+
+    begin
+
+       case c is
+        when 'a' => u := 'A';
+        when 'b' => u := 'B';
+        when 'c' => u := 'C';
+        when 'd' => u := 'D';
+        when 'e' => u := 'E';
+        when 'f' => u := 'F';
+        when 'g' => u := 'G';
+        when 'h' => u := 'H';
+        when 'i' => u := 'I';
+        when 'j' => u := 'J';
+        when 'k' => u := 'K';
+        when 'l' => u := 'L';
+        when 'm' => u := 'M';
+        when 'n' => u := 'N';
+        when 'o' => u := 'O';
+        when 'p' => u := 'P';
+        when 'q' => u := 'Q';
+        when 'r' => u := 'R';
+        when 's' => u := 'S';
+        when 't' => u := 'T';
+        when 'u' => u := 'U';
+        when 'v' => u := 'V';
+        when 'w' => u := 'W';
+        when 'x' => u := 'X';
+        when 'y' => u := 'Y';
+        when 'z' => u := 'Z';
+        when others => u := c;
+    end case;
+
+      return u;
+
+   end to_upper;
+
+
+   -- convert a character to lower case
+
+   function to_lower(c: character) return character is
+
+      variable l: character;
+
+    begin
+
+       case c is
+        when 'A' => l := 'a';
+        when 'B' => l := 'b';
+        when 'C' => l := 'c';
+        when 'D' => l := 'd';
+        when 'E' => l := 'e';
+        when 'F' => l := 'f';
+        when 'G' => l := 'g';
+        when 'H' => l := 'h';
+        when 'I' => l := 'i';
+        when 'J' => l := 'j';
+        when 'K' => l := 'k';
+        when 'L' => l := 'l';
+        when 'M' => l := 'm';
+        when 'N' => l := 'n';
+        when 'O' => l := 'o';
+        when 'P' => l := 'p';
+        when 'Q' => l := 'q';
+        when 'R' => l := 'r';
+        when 'S' => l := 's';
+        when 'T' => l := 't';
+        when 'U' => l := 'u';
+        when 'V' => l := 'v';
+        when 'W' => l := 'w';
+        when 'X' => l := 'x';
+        when 'Y' => l := 'y';
+        when 'Z' => l := 'z';
+        when others => l := c;
+    end case;
+
+      return l;
+
+   end to_lower;
+
+
+
+   -- convert a string to upper case
+
+   function to_upper(s: string) return string is
+
+     variable uppercase: string (s'range);
+
+   begin
+
+     for i in s'range loop
+        uppercase(i):= to_upper(s(i));
+     end loop;
+     return uppercase;
+
+   end to_upper;
+
+
+
+   -- convert a string to lower case
+
+   function to_lower(s: string) return string is
+
+     variable lowercase: string (s'range);
+
+   begin
+
+     for i in s'range loop
+        lowercase(i):= to_lower(s(i));
+     end loop;
+     return lowercase;
+
+   end to_lower;
+
+
+
+-- functions to convert strings into other types
+
+
+-- converts a character into a std_logic
+
+function to_std_logic(c: character) return std_logic is 
+    variable sl: std_logic;
+    begin
+      case c is
+        when 'U' => 
+           sl := 'U'; 
+        when 'X' =>
+           sl := 'X';
+        when '0' => 
+           sl := '0';
+        when '1' => 
+           sl := '1';
+        when 'Z' => 
+           sl := 'Z';
+        when 'W' => 
+           sl := 'W';
+        when 'L' => 
+           sl := 'L';
+        when 'H' => 
+           sl := 'H';
+        when '-' => 
+           sl := '-';
+        when others =>
+           sl := 'X'; 
+    end case;
+   return sl;
+  end to_std_logic;
+
+
+-- converts a string into std_logic_vector
+
+function to_std_logic_vector(s: string) return std_logic_vector is 
+  variable slv: std_logic_vector(s'high-s'low downto 0);
+  variable k: integer;
+begin
+   k := s'high-s'low;
+  for i in s'range loop
+     slv(k) := to_std_logic(s(i));
+     k      := k - 1;
+  end loop;
+  return slv;
+end to_std_logic_vector;                                       
+                                       
+                                       
+                                       
+                                       
+                                       
+                                       
+----------------
+--  file I/O  --
+----------------
+
+
+
+-- read variable length string from input file
+     
+procedure str_read(file in_file: TEXT; 
+                   res_string: out string) is
+       
+       variable l:         line;
+       variable c:         character;
+       variable is_string: boolean;
+       
+   begin
+           
+     readline(in_file, l);
+     -- clear the contents of the result string
+     for i in res_string'range loop
+         res_string(i) := ' ';
+     end loop;   
+     -- read all characters of the line, up to the length  
+     -- of the results string
+     for i in res_string'range loop
+        read(l, c, is_string);
+        res_string(i) := c;
+        if not is_string then -- found end of line
+           exit;
+        end if;   
+     end loop; 
+                     
+end str_read;
+
+
+-- print string to a file
+procedure print(file out_file: TEXT;
+                new_string: in  string) is
+       
+       variable l: line;
+       
+   begin
+      
+     write(l, new_string);
+     writeline(out_file, l);
+                     
+end print;
+
+
+-- print character to a file and start new line
+procedure print(file out_file: TEXT;
+                char: in  character) is
+       
+       variable l: line;
+       
+   begin
+      
+     write(l, char);
+     writeline(out_file, l);
+                     
+end print;
+
+
+
+-- appends contents of a string to a file until line feed occurs
+-- (LF is considered to be the end of the string)
+
+procedure str_write(file out_file: TEXT; 
+                    new_string: in  string) is
+ begin
+      
+   for i in new_string'range loop
+      print(out_file, new_string(i));
+      if new_string(i) = LF then -- end of string
+         exit;
+      end if;
+   end loop;               
+                     
+end str_write;
+
+
+
+
+end txt_util;
+
+
+
+
diff --git a/zpu/hdl/zy2000/zpu_config.vhd b/zpu/hdl/zy2000/zpu_config.vhd
index 61949c5..c0df294 100644
--- a/zpu/hdl/zy2000/zpu_config.vhd
+++ b/zpu/hdl/zy2000/zpu_config.vhd
@@ -1,20 +1,20 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-
-package zpu_config is
-	-- generate trace output or not.
-	constant	Generate_Trace		: boolean := false;
-	constant 	wordPower			: integer := 5;
-	-- during simulation, set this to '0' to get matching trace.txt 
-	constant	DontCareValue		: std_logic := '0';
-	-- Clock frequency in MHz.
-	constant	ZPU_Frequency		: std_logic_vector(7 downto 0) := x"40";
-	-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
-	constant 	maxAddrBitIncIO		: integer := 27;
-	
-	-- start byte address of stack. 
-	-- point to top of RAM - 2*words
-	constant 	spStart				: std_logic_vector(maxAddrBitIncIO downto 0) := x"1fffff8"; 
-	
-end zpu_config;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+package zpu_config is
+	-- generate trace output or not.
+	constant	Generate_Trace		: boolean := false;
+	constant 	wordPower			: integer := 5;
+	-- during simulation, set this to '0' to get matching trace.txt 
+	constant	DontCareValue		: std_logic := '0';
+	-- Clock frequency in MHz.
+	constant	ZPU_Frequency		: std_logic_vector(7 downto 0) := x"40";
+	-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
+	constant 	maxAddrBitIncIO		: integer := 27;
+	
+	-- start byte address of stack. 
+	-- point to top of RAM - 2*words
+	constant 	spStart				: std_logic_vector(maxAddrBitIncIO downto 0) := x"1fffff8"; 
+	
+end zpu_config;
diff --git a/zpu/hdl/zy2000/zpu_config_fast.vhd b/zpu/hdl/zy2000/zpu_config_fast.vhd
index 61949c5..c0df294 100644
--- a/zpu/hdl/zy2000/zpu_config_fast.vhd
+++ b/zpu/hdl/zy2000/zpu_config_fast.vhd
@@ -1,20 +1,20 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-
-package zpu_config is
-	-- generate trace output or not.
-	constant	Generate_Trace		: boolean := false;
-	constant 	wordPower			: integer := 5;
-	-- during simulation, set this to '0' to get matching trace.txt 
-	constant	DontCareValue		: std_logic := '0';
-	-- Clock frequency in MHz.
-	constant	ZPU_Frequency		: std_logic_vector(7 downto 0) := x"40";
-	-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
-	constant 	maxAddrBitIncIO		: integer := 27;
-	
-	-- start byte address of stack. 
-	-- point to top of RAM - 2*words
-	constant 	spStart				: std_logic_vector(maxAddrBitIncIO downto 0) := x"1fffff8"; 
-	
-end zpu_config;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+package zpu_config is
+	-- generate trace output or not.
+	constant	Generate_Trace		: boolean := false;
+	constant 	wordPower			: integer := 5;
+	-- during simulation, set this to '0' to get matching trace.txt 
+	constant	DontCareValue		: std_logic := '0';
+	-- Clock frequency in MHz.
+	constant	ZPU_Frequency		: std_logic_vector(7 downto 0) := x"40";
+	-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
+	constant 	maxAddrBitIncIO		: integer := 27;
+	
+	-- start byte address of stack. 
+	-- point to top of RAM - 2*words
+	constant 	spStart				: std_logic_vector(maxAddrBitIncIO downto 0) := x"1fffff8"; 
+	
+end zpu_config;
diff --git a/zpu/hdl/zy2000/zpupkg.vhd b/zpu/hdl/zy2000/zpupkg.vhd
index 1a01563..a7e6cf1 100644
--- a/zpu/hdl/zy2000/zpupkg.vhd
+++ b/zpu/hdl/zy2000/zpupkg.vhd
@@ -1,168 +1,168 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-
-library work;
-use work.zpu_config.all;
-
-package zpupkg is
-
-	-- This bit is set for read/writes to IO
-	-- FIX!!! eventually this should be set to wordSize-1 so as to
-	-- to make the address of IO independent of amount of memory
-	-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-	-- libraries.
-	
-	constant byteBits			: integer := wordPower-3; -- # of bits in a word that addresses bytes
-	constant maxAddrBit			: integer := maxAddrBitIncIO-1;
-	constant ioBit				: integer := maxAddrBit+1;
-	constant wordSize			: integer := 2**wordPower;
-	constant wordBytes			: integer := wordSize/8;
-	constant minAddrBit			: integer := byteBits;
-	-- configurable internal stack size. Probably going to be 16 after toolchain is done
-	constant	stack_bits		: integer := 5; 
-	constant	stack_size		: integer := 2**stack_bits; 
-
-	component dualport_ram is
-	port (clk : in std_logic;
-		memAWriteEnable : in std_logic;
-		memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
-		memAWrite : in std_logic_vector(wordSize-1 downto 0);
-		memARead : out std_logic_vector(wordSize-1 downto 0);
-		memBWriteEnable : in std_logic;
-		memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
-		memBWrite : in std_logic_vector(wordSize-1 downto 0);
-		memBRead : out std_logic_vector(wordSize-1 downto 0));
-	end component;
-
-	component dram is
-		port (clk : in std_logic;
-			areset : in std_logic;
-			mem_writeEnable : in std_logic;
-			mem_readEnable : in std_logic;
-			mem_addr : in std_logic_vector(maxAddrBit downto 0);
-			mem_write : in std_logic_vector(wordSize-1 downto 0);
-			mem_read : out std_logic_vector(wordSize-1 downto 0);
-			mem_busy : out std_logic;
-			mem_writeMask : in std_logic_vector(wordBytes-1 downto 0));
-	end component;
-
-
-	component trace is
-	  port(
-	       	clk         : in std_logic;
-	       	begin_inst  : in std_logic;
-	       	pc          : in std_logic_vector(maxAddrBitIncIO downto 0);
-			opcode		: in std_logic_vector(7 downto 0);
-			sp			: in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
-			memA		: in std_logic_vector(wordSize-1 downto 0);
-			memB		: in std_logic_vector(wordSize-1 downto 0);
-			busy         : in std_logic;
-			intSp		: in std_logic_vector(stack_bits-1 downto 0)
-			);
-	end component;
-
-	component zpu_core is
-    port ( clk : in std_logic;
-	 		  areset : in std_logic;
-	 		  enable : in std_logic; 
-	 		  mem_req : out std_logic;
-	 		  mem_we : out std_logic;
-	 		  mem_ack : in std_logic; 
-	 		  mem_read : in std_logic_vector(wordSize-1 downto 0);
-	 		  mem_write : out std_logic_vector(wordSize-1 downto 0);
-			  out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0);
-	 		  mem_writeMask: out std_logic_vector(wordBytes-1 downto 0);
-	 		  interrupt : in std_logic;
-	 		  break : out std_logic;
-	 		  zpu_status : out std_logic_vector(63 downto 0));
-	end component;
-
-
-	
-	component timer is
-  	port(
-       	clk             : in std_logic;
-		areset			: in std_logic;
-		sample			: in std_logic;
-		reset			: in std_logic;
-		counter			: out std_logic_vector(63 downto 0));
-	end component;
-
-	component  zpuio is
-		port (	areset			: in std_logic;
-				cpu_clk			: in std_logic;
-				clk_status		: in std_logic_vector(2 downto 0);
-				cpu_din			: in std_logic_vector(15 downto 0);
-				cpu_a			: in std_logic_vector(20 downto 0);
-				cpu_we			: in std_logic_vector(1 downto 0);
-				cpu_re			: in std_logic;
-				cpu_dout		: inout std_logic_vector(15 downto 0));
-	end component;
-
-
-
-	
-	-- opcode decode constants
-	constant	OpCode_Im		: std_logic_vector(7 downto 7) := "1";
-	constant	OpCode_StoreSP	: std_logic_vector(7 downto 5) := "010";
-	constant	OpCode_LoadSP	: std_logic_vector(7 downto 5) := "011";
-	constant	OpCode_Emulate	: std_logic_vector(7 downto 5) := "001";
-	constant	OpCode_AddSP	: std_logic_vector(7 downto 4) := "0001";
-	constant	OpCode_Short	: std_logic_vector(7 downto 4) := "0000";
-	
-	constant	OpCode_Break	: std_logic_vector(3 downto 0) := "0000";
-	constant	OpCode_Shiftleft: std_logic_vector(3 downto 0) := "0001";
-	constant	OpCode_PushSP	: std_logic_vector(3 downto 0) := "0010";
-	constant	OpCode_PushInt	: std_logic_vector(3 downto 0) := "0011";
-	
-	constant	OpCode_PopPC	: std_logic_vector(3 downto 0) := "0100";
-	constant	OpCode_Add		: std_logic_vector(3 downto 0) := "0101";
-	constant	OpCode_And		: std_logic_vector(3 downto 0) := "0110";
-	constant	OpCode_Or		: std_logic_vector(3 downto 0) := "0111";
-	
-	constant	OpCode_Load		: std_logic_vector(3 downto 0) := "1000";
-	constant	OpCode_Not		: std_logic_vector(3 downto 0) := "1001";
-	constant	OpCode_Flip		: std_logic_vector(3 downto 0) := "1010";
-	constant	OpCode_Nop		: std_logic_vector(3 downto 0) := "1011";
-	
-	constant	OpCode_Store	: std_logic_vector(3 downto 0) := "1100";
-	constant	OpCode_PopSP	: std_logic_vector(3 downto 0) := "1101";
-	constant	OpCode_Compare	: std_logic_vector(3 downto 0) := "1110";
-	constant	OpCode_PopInt	: std_logic_vector(3 downto 0) := "1111";
-	
-	constant	OpCode_Lessthan				: std_logic_vector(5 downto 0) := conv_std_logic_vector(36, 6);
-	constant	OpCode_Lessthanorequal		: std_logic_vector(5 downto 0) := conv_std_logic_vector(37, 6);
-	constant	OpCode_Ulessthan			: std_logic_vector(5 downto 0) := conv_std_logic_vector(38, 6);
-	constant	OpCode_Ulessthanorequal		: std_logic_vector(5 downto 0) := conv_std_logic_vector(39, 6);
-
-	constant	OpCode_Swap					: std_logic_vector(5 downto 0) := conv_std_logic_vector(40, 6);
-	constant	OpCode_Mult					: std_logic_vector(5 downto 0) := conv_std_logic_vector(41, 6);
-	
-	constant	OpCode_Lshiftright			: std_logic_vector(5 downto 0) := conv_std_logic_vector(42, 6);
-	constant	OpCode_Ashiftleft			: std_logic_vector(5 downto 0) := conv_std_logic_vector(43, 6);
-	constant	OpCode_Ashiftright			: std_logic_vector(5 downto 0) := conv_std_logic_vector(44, 6);
-	constant	OpCode_Call					: std_logic_vector(5 downto 0) := conv_std_logic_vector(45, 6);
-
-	constant	OpCode_Eq					: std_logic_vector(5 downto 0) := conv_std_logic_vector(46, 6);
-	constant	OpCode_Neq					: std_logic_vector(5 downto 0) := conv_std_logic_vector(47, 6);
-
-	constant	OpCode_Sub					: std_logic_vector(5 downto 0) := conv_std_logic_vector(49, 6);
-	constant	OpCode_Loadb				: std_logic_vector(5 downto 0) := conv_std_logic_vector(51, 6);
-	constant	OpCode_Storeb				: std_logic_vector(5 downto 0) := conv_std_logic_vector(52, 6);
-
-	constant	OpCode_Eqbranch				: std_logic_vector(5 downto 0) := conv_std_logic_vector(55, 6);
-	constant	OpCode_Neqbranch			: std_logic_vector(5 downto 0) := conv_std_logic_vector(56, 6);
-	constant	OpCode_Poppcrel				: std_logic_vector(5 downto 0) := conv_std_logic_vector(57, 6);
-
-	constant	OpCode_Pushspadd			: std_logic_vector(5 downto 0) := conv_std_logic_vector(61, 6);
-	constant	OpCode_Mult16x16			: std_logic_vector(5 downto 0) := conv_std_logic_vector(62, 6);
-	constant	OpCode_Callpcrel			: std_logic_vector(5 downto 0) := conv_std_logic_vector(63, 6);
-	
-
-
-	constant OpCode_Size		: integer := 8;
-
-
-		
-end zpupkg;
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+
+library work;
+use work.zpu_config.all;
+
+package zpupkg is
+
+	-- This bit is set for read/writes to IO
+	-- FIX!!! eventually this should be set to wordSize-1 so as to
+	-- to make the address of IO independent of amount of memory
+	-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
+	-- libraries.
+	
+	constant byteBits			: integer := wordPower-3; -- # of bits in a word that addresses bytes
+	constant maxAddrBit			: integer := maxAddrBitIncIO-1;
+	constant ioBit				: integer := maxAddrBit+1;
+	constant wordSize			: integer := 2**wordPower;
+	constant wordBytes			: integer := wordSize/8;
+	constant minAddrBit			: integer := byteBits;
+	-- configurable internal stack size. Probably going to be 16 after toolchain is done
+	constant	stack_bits		: integer := 5; 
+	constant	stack_size		: integer := 2**stack_bits; 
+
+	component dualport_ram is
+	port (clk : in std_logic;
+		memAWriteEnable : in std_logic;
+		memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
+		memAWrite : in std_logic_vector(wordSize-1 downto 0);
+		memARead : out std_logic_vector(wordSize-1 downto 0);
+		memBWriteEnable : in std_logic;
+		memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
+		memBWrite : in std_logic_vector(wordSize-1 downto 0);
+		memBRead : out std_logic_vector(wordSize-1 downto 0));
+	end component;
+
+	component dram is
+		port (clk : in std_logic;
+			areset : in std_logic;
+			mem_writeEnable : in std_logic;
+			mem_readEnable : in std_logic;
+			mem_addr : in std_logic_vector(maxAddrBit downto 0);
+			mem_write : in std_logic_vector(wordSize-1 downto 0);
+			mem_read : out std_logic_vector(wordSize-1 downto 0);
+			mem_busy : out std_logic;
+			mem_writeMask : in std_logic_vector(wordBytes-1 downto 0));
+	end component;
+
+
+	component trace is
+	  port(
+	       	clk         : in std_logic;
+	       	begin_inst  : in std_logic;
+	       	pc          : in std_logic_vector(maxAddrBitIncIO downto 0);
+			opcode		: in std_logic_vector(7 downto 0);
+			sp			: in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+			memA		: in std_logic_vector(wordSize-1 downto 0);
+			memB		: in std_logic_vector(wordSize-1 downto 0);
+			busy         : in std_logic;
+			intSp		: in std_logic_vector(stack_bits-1 downto 0)
+			);
+	end component;
+
+	component zpu_core is
+    port ( clk : in std_logic;
+	 		  areset : in std_logic;
+	 		  enable : in std_logic; 
+	 		  mem_req : out std_logic;
+	 		  mem_we : out std_logic;
+	 		  mem_ack : in std_logic; 
+	 		  mem_read : in std_logic_vector(wordSize-1 downto 0);
+	 		  mem_write : out std_logic_vector(wordSize-1 downto 0);
+			  out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0);
+	 		  mem_writeMask: out std_logic_vector(wordBytes-1 downto 0);
+	 		  interrupt : in std_logic;
+	 		  break : out std_logic;
+	 		  zpu_status : out std_logic_vector(63 downto 0));
+	end component;
+
+
+	
+	component timer is
+  	port(
+       	clk             : in std_logic;
+		areset			: in std_logic;
+		sample			: in std_logic;
+		reset			: in std_logic;
+		counter			: out std_logic_vector(63 downto 0));
+	end component;
+
+	component  zpuio is
+		port (	areset			: in std_logic;
+				cpu_clk			: in std_logic;
+				clk_status		: in std_logic_vector(2 downto 0);
+				cpu_din			: in std_logic_vector(15 downto 0);
+				cpu_a			: in std_logic_vector(20 downto 0);
+				cpu_we			: in std_logic_vector(1 downto 0);
+				cpu_re			: in std_logic;
+				cpu_dout		: inout std_logic_vector(15 downto 0));
+	end component;
+
+
+
+	
+	-- opcode decode constants
+	constant	OpCode_Im		: std_logic_vector(7 downto 7) := "1";
+	constant	OpCode_StoreSP	: std_logic_vector(7 downto 5) := "010";
+	constant	OpCode_LoadSP	: std_logic_vector(7 downto 5) := "011";
+	constant	OpCode_Emulate	: std_logic_vector(7 downto 5) := "001";
+	constant	OpCode_AddSP	: std_logic_vector(7 downto 4) := "0001";
+	constant	OpCode_Short	: std_logic_vector(7 downto 4) := "0000";
+	
+	constant	OpCode_Break	: std_logic_vector(3 downto 0) := "0000";
+	constant	OpCode_Shiftleft: std_logic_vector(3 downto 0) := "0001";
+	constant	OpCode_PushSP	: std_logic_vector(3 downto 0) := "0010";
+	constant	OpCode_PushInt	: std_logic_vector(3 downto 0) := "0011";
+	
+	constant	OpCode_PopPC	: std_logic_vector(3 downto 0) := "0100";
+	constant	OpCode_Add		: std_logic_vector(3 downto 0) := "0101";
+	constant	OpCode_And		: std_logic_vector(3 downto 0) := "0110";
+	constant	OpCode_Or		: std_logic_vector(3 downto 0) := "0111";
+	
+	constant	OpCode_Load		: std_logic_vector(3 downto 0) := "1000";
+	constant	OpCode_Not		: std_logic_vector(3 downto 0) := "1001";
+	constant	OpCode_Flip		: std_logic_vector(3 downto 0) := "1010";
+	constant	OpCode_Nop		: std_logic_vector(3 downto 0) := "1011";
+	
+	constant	OpCode_Store	: std_logic_vector(3 downto 0) := "1100";
+	constant	OpCode_PopSP	: std_logic_vector(3 downto 0) := "1101";
+	constant	OpCode_Compare	: std_logic_vector(3 downto 0) := "1110";
+	constant	OpCode_PopInt	: std_logic_vector(3 downto 0) := "1111";
+	
+	constant	OpCode_Lessthan				: std_logic_vector(5 downto 0) := conv_std_logic_vector(36, 6);
+	constant	OpCode_Lessthanorequal		: std_logic_vector(5 downto 0) := conv_std_logic_vector(37, 6);
+	constant	OpCode_Ulessthan			: std_logic_vector(5 downto 0) := conv_std_logic_vector(38, 6);
+	constant	OpCode_Ulessthanorequal		: std_logic_vector(5 downto 0) := conv_std_logic_vector(39, 6);
+
+	constant	OpCode_Swap					: std_logic_vector(5 downto 0) := conv_std_logic_vector(40, 6);
+	constant	OpCode_Mult					: std_logic_vector(5 downto 0) := conv_std_logic_vector(41, 6);
+	
+	constant	OpCode_Lshiftright			: std_logic_vector(5 downto 0) := conv_std_logic_vector(42, 6);
+	constant	OpCode_Ashiftleft			: std_logic_vector(5 downto 0) := conv_std_logic_vector(43, 6);
+	constant	OpCode_Ashiftright			: std_logic_vector(5 downto 0) := conv_std_logic_vector(44, 6);
+	constant	OpCode_Call					: std_logic_vector(5 downto 0) := conv_std_logic_vector(45, 6);
+
+	constant	OpCode_Eq					: std_logic_vector(5 downto 0) := conv_std_logic_vector(46, 6);
+	constant	OpCode_Neq					: std_logic_vector(5 downto 0) := conv_std_logic_vector(47, 6);
+
+	constant	OpCode_Sub					: std_logic_vector(5 downto 0) := conv_std_logic_vector(49, 6);
+	constant	OpCode_Loadb				: std_logic_vector(5 downto 0) := conv_std_logic_vector(51, 6);
+	constant	OpCode_Storeb				: std_logic_vector(5 downto 0) := conv_std_logic_vector(52, 6);
+
+	constant	OpCode_Eqbranch				: std_logic_vector(5 downto 0) := conv_std_logic_vector(55, 6);
+	constant	OpCode_Neqbranch			: std_logic_vector(5 downto 0) := conv_std_logic_vector(56, 6);
+	constant	OpCode_Poppcrel				: std_logic_vector(5 downto 0) := conv_std_logic_vector(57, 6);
+
+	constant	OpCode_Pushspadd			: std_logic_vector(5 downto 0) := conv_std_logic_vector(61, 6);
+	constant	OpCode_Mult16x16			: std_logic_vector(5 downto 0) := conv_std_logic_vector(62, 6);
+	constant	OpCode_Callpcrel			: std_logic_vector(5 downto 0) := conv_std_logic_vector(63, 6);
+	
+
+
+	constant OpCode_Size		: integer := 8;
+
+
+		
+end zpupkg;
-- 
cgit v1.1


From f54a7949bc551f4a4ecc20728453cfe09ae65aed Mon Sep 17 00:00:00 2001
From: Bert Lange 
Date: Fri, 4 Mar 2011 10:40:56 +0100
Subject: change: switch to ieee.numeric_std.all library

Signed-off-by: Bert Lange 
---
 zpu/hdl/example/zpu_config.vhd   | 5 ++---
 zpu/hdl/zpu4/core/zpu_config.vhd | 5 ++---
 2 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/zpu/hdl/example/zpu_config.vhd b/zpu/hdl/example/zpu_config.vhd
index c3c60c1..cd4163d 100644
--- a/zpu/hdl/example/zpu_config.vhd
+++ b/zpu/hdl/example/zpu_config.vhd
@@ -34,8 +34,7 @@
 
 library ieee;
 use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
 
 package zpu_config is
 	-- generate trace output
@@ -52,5 +51,5 @@ package zpu_config is
 	-- start byte address of stack. 
 	-- point to top of RAM - 2*words
 	constant 	spStart				: std_logic_vector(maxAddrBitIncIO downto 0) :=
-					conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1);
+					std_logic_vector(to_unsigned((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1));
 end zpu_config;
diff --git a/zpu/hdl/zpu4/core/zpu_config.vhd b/zpu/hdl/zpu4/core/zpu_config.vhd
index 5b3110c..b29c561 100644
--- a/zpu/hdl/zpu4/core/zpu_config.vhd
+++ b/zpu/hdl/zpu4/core/zpu_config.vhd
@@ -35,8 +35,7 @@
 
 library ieee;
 use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
 
 package zpu_config is
 
@@ -54,6 +53,6 @@ package zpu_config is
   -- start byte address of stack. 
   -- point to top of RAM - 2*words
   constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) :=
-    conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1);
+    std_logic_vector(to_unsigned((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1));
 
 end zpu_config;
-- 
cgit v1.1


From 509095f846aa8b2393ab7bf974eb2932846b950f Mon Sep 17 00:00:00 2001
From: Bert Lange 
Date: Thu, 9 Jun 2011 17:54:03 +0200
Subject: fix: missing comment

---
 zpu/hdl/zpu4/core/zpu_core_small.vhd | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/zpu/hdl/zpu4/core/zpu_core_small.vhd b/zpu/hdl/zpu4/core/zpu_core_small.vhd
index 757d056..b975977 100644
--- a/zpu/hdl/zpu4/core/zpu_core_small.vhd
+++ b/zpu/hdl/zpu4/core/zpu_core_small.vhd
@@ -308,7 +308,7 @@ begin
         when others =>
           sampledDecodedOpcode <= Decoded_Nop;
       end case;  -- tOpcode(3 downto 0)
-    end if; tOpcode
+    end if; -- tOpcode
   end process;
 
 
-- 
cgit v1.1


From e6d9de6465aecf64a53b941bf80830280e95c040 Mon Sep 17 00:00:00 2001
From: Bert Lange 
Date: Tue, 2 Aug 2011 09:53:37 +0200
Subject: fix: remove note on not existing JTAG/hardware debugger

---
 zpu/docs/zpu_arch.html | 24 ------------------------
 1 file changed, 24 deletions(-)

diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html
index 8aaa132..448d86c 100644
--- a/zpu/docs/zpu_arch.html
+++ b/zpu/docs/zpu_arch.html
@@ -56,7 +56,6 @@ Several of the links will only work if you have checked out the zpu/zpu tree fro
 
      38.  Miscellaneous
   
        39.  
-560 LUT
-388 REG
+561 LUT
+391 REG
   0 MULT18x18
   8 BRAM (RAMB36)
-140 fmax
+175 fmax
 
         
@@ -1159,7 +1159,7 @@ maxAddrBit=16
 
         
-1292 LUT
+1299 LUT
  490 REG
    3 MULT (DSP48E)
    8 BRAM (RAMB36)
-- 
cgit v1.1


From 105f8b40509ea2657e36e13af76b7580029fd2e5 Mon Sep 17 00:00:00 2001
From: Bert Lange 
Date: Tue, 25 Oct 2011 22:03:02 +0200
Subject: fix: zealot/zpu_small - load, see patch from Alvaro

---
 zpu/hdl/zealot/zpu_small.vhdl | 1 +
 1 file changed, 1 insertion(+)

diff --git a/zpu/hdl/zealot/zpu_small.vhdl b/zpu/hdl/zealot/zpu_small.vhdl
index 7e022d4..2e5f464 100644
--- a/zpu/hdl/zealot/zpu_small.vhdl
+++ b/zpu/hdl/zealot/zpu_small.vhdl
@@ -391,6 +391,7 @@ begin
                                 null;
                       end case;
                  when st_read_io =>
+                      a_addr_r <= sp_r;
                       -- Wait until memory I/O isn't busy
                       if mem_busy_i='0' then
                          state  <= st_fetch;
-- 
cgit v1.1


From c883cd4a4e4fa1974e5d7d72a79240de88bd26da Mon Sep 17 00:00:00 2001
From: Bert Lange 
Date: Tue, 25 Oct 2011 23:26:36 +0200
Subject: add: GPIO module to zealot SoC

---
 zpu/hdl/zealot/devices/gpio.vhdl                   |  107 ++
 zpu/hdl/zealot/devices/phi_io.vhdl                 |   71 +-
 .../zealot/fpga/avnet-eval-xc5vfx30t/simulation.sh |    1 +
 .../avnet-eval-xc5vfx30t/simulation_config/wave.do |   56 +-
 .../synthesis_config/avnet-eval-xc5vfx30t.ucf      |   13 +
 .../avnet-eval-xc5vfx30t/synthesis_config/top.prj  |    1 +
 zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd   |   58 +-
 .../zealot/fpga/avnet-eval-xc5vfx30t/top_tb.vhd    |    3 +
 .../fpga/digilent-starter-xc3s500e/simulation.sh   |    1 +
 .../simulation_config/run.do                       |    6 +-
 .../simulation_config/wave.do                      |   30 +
 .../synthesis_config/top.prj                       |   37 +-
 .../synthesis_config/top.ut                        |   44 +-
 .../synthesis_config/top.xst                       |  112 +-
 .../zealot/fpga/digilent-starter-xc3s500e/top.vhd  |  866 ++++++++--------
 .../fpga/digilent-starter-xc3s500e/top_tb.vhd      |  559 +++++-----
 zpu/hdl/zealot/fpga/dmips_med1.vhdl                |    8 +-
 zpu/hdl/zealot/fpga/dmips_small1.vhdl              |    8 +-
 zpu/hdl/zealot/fpga/hello_med1.vhdl                |    8 +-
 zpu/hdl/zealot/fpga/hello_small1.vhdl              |    8 +-
 .../fpga/xilinx-sp601-xc6slx16/simulation.sh       |    1 +
 .../xilinx-sp601-xc6slx16/simulation_config/run.do |    4 +-
 .../xilinx-sp601-xc6slx16/synthesis_config/top.prj |   37 +-
 .../xilinx-sp601-xc6slx16/synthesis_config/top.ut  |   60 +-
 .../xilinx-sp601-xc6slx16/synthesis_config/top.xst |  106 +-
 .../synthesis_config/xilinx-sp601-xc6slx16.ucf     |  606 +++++------
 zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top.vhd  | 1096 ++++++++++----------
 .../zealot/fpga/xilinx-sp601-xc6slx16/top_tb.vhd   |  800 +++++++-------
 zpu/hdl/zealot/helpers/zpu_med1.vhdl               |   29 +-
 zpu/hdl/zealot/helpers/zpu_small1.vhdl             |   29 +-
 zpu/hdl/zealot/testbenches/dmips_med1_tb.vhdl      |    9 +-
 zpu/hdl/zealot/testbenches/small1_tb.vhdl          |    9 +-
 zpu/hdl/zealot/zpu_pkg.vhdl                        |   27 +-
 33 files changed, 2590 insertions(+), 2220 deletions(-)
 create mode 100644 zpu/hdl/zealot/devices/gpio.vhdl
 create mode 100644 zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/wave.do

diff --git a/zpu/hdl/zealot/devices/gpio.vhdl b/zpu/hdl/zealot/devices/gpio.vhdl
new file mode 100644
index 0000000..fc66bde
--- /dev/null
+++ b/zpu/hdl/zealot/devices/gpio.vhdl
@@ -0,0 +1,107 @@
+--
+-- this module desribes a simple GPIO interface
+--
+-- data on port_in is synhronized to clk_i and can be read at
+-- address 0
+--
+-- any write to address 0 is mapped to port_out
+--
+-- at address 1 is a direction register (port_dir)
+-- initialized with '1's, what mean direction = in
+-- this register is useful for bidirectional pins, e.g. headers
+--
+--
+-- some examples:
+--
+-- to connect 4 buttons:
+-- port_in( 3 downto  0) <= gpio_button;
+--
+--
+-- to connect 8 LEDs:
+-- gpio_led <= port_out(7 downto 0); 
+--
+--
+-- to connect 2 bidirectional header pins:
+-- port_in(8)  <= gpio_pin(0);
+-- gpio_pin(0) <= port_out(8) when port_dir(8) = '0' else 'Z';
+--
+-- port_in(9)  <= gpio_pin(1);
+-- gpio_pin(1) <= port_out(9) when port_dir(9) = '0' else 'Z';
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+entity gpio is
+    port(
+        clk_i    : in  std_logic;
+        reset_i  : in  std_logic;
+        --
+        we_i     : in  std_logic;
+        data_i   : in  unsigned(31 downto 0);
+        addr_i   : in  unsigned( 0 downto 0);
+        data_o   : out unsigned(31 downto 0);
+        --
+        port_in  : in  std_logic_vector(31 downto 0);
+        port_out : out std_logic_vector(31 downto 0);
+        port_dir : out std_logic_vector(31 downto 0)
+    );
+end entity gpio;
+
+
+architecture rtl of gpio is
+
+    signal port_in_reg  : std_logic_vector(31 downto 0);
+    signal port_in_sync : std_logic_vector(31 downto 0);
+    --
+    signal direction    : std_logic_vector(31 downto 0) := (others => '1');
+
+begin
+
+    process
+    begin
+        wait until rising_edge( clk_i);
+        
+        -- synchronize all inputs with two registers
+        -- to avoid metastability
+        port_in_reg  <= port_in;
+        port_in_sync <= port_in_reg;
+
+        -- write access to gpio
+        if we_i = '1' then
+            -- data
+            if addr_i = "0" then
+                port_out  <= std_logic_vector( data_i);
+            end if;
+            -- direction
+            if addr_i = "1" then
+                direction <= std_logic_vector( data_i);
+            end if;
+        end if;
+
+        -- read access to gpio
+        -- data
+        if addr_i = "0" then
+            data_o <= unsigned( port_in_sync);
+        end if;
+        -- direction
+        if addr_i = "1" then
+            data_o <= unsigned( direction);
+        end if;
+
+        -- outputs
+        port_dir <= direction;
+
+        -- sync reset
+        if reset_i = '1' then
+            direction    <= (others => '1');
+            port_in_reg  <= (others => '0');
+            port_in_sync <= (others => '0');
+        end if;
+
+    end process;
+
+
+end architecture rtl;
diff --git a/zpu/hdl/zealot/devices/phi_io.vhdl b/zpu/hdl/zealot/devices/phi_io.vhdl
index 99e0f8f..71e881c 100644
--- a/zpu/hdl/zealot/devices/phi_io.vhdl
+++ b/zpu/hdl/zealot/devices/phi_io.vhdl
@@ -56,7 +56,8 @@ use IEEE.numeric_std.all;
 use std.textio.all;
 
 library zpu;
-use zpu.zpupkg.all;
+use zpu.zpupkg.timer;
+use zpu.zpupkg.gpio;
 use zpu.UART.all;
 use zpu.txt_util.all;
  
@@ -73,25 +74,31 @@ entity ZPUPhiIO is
       re_i       : in  std_logic; -- Read Enable
       data_i     : in  unsigned(31 downto 0);
       data_o     : out unsigned(31 downto 0);
-      addr_i     : in  unsigned(2 downto 0); -- Address bits 4-2
+      addr_i     : in  unsigned(2  downto 0); -- Address bits 4-2
+      --
       rs232_rx_i : in  std_logic;  -- UART Rx input
       rs232_tx_o : out std_logic;  -- UART Tx output
-      br_clk_i   : in  std_logic); -- UART base clock (enable)
+      br_clk_i   : in  std_logic;  -- UART base clock (enable)
+      --
+      gpio_in    : in  std_logic_vector(31 downto 0);
+      gpio_out   : out std_logic_vector(31 downto 0);
+      gpio_dir   : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
+      );
 end entity ZPUPhiIO;
    
    
 architecture Behave of ZPUPhiIO is
-   constant LOW_BITS : unsigned(1 downto 0):=(others=>'0');
-   constant TX_FULL  : std_logic:='0';
-   constant RX_EMPTY : std_logic:='1';
+   constant LOW_BITS  : unsigned(1 downto 0):=(others=>'0');
+   constant TX_FULL   : std_logic:='0';
+   constant RX_EMPTY  : std_logic:='1';
 
    -- "000" 0x00 is CPU enable ... useful?
-   -- "001" 0x04 Unused
-   -- "010" 0x08 Unused
-   constant UART_TX  : unsigned(2 downto 0):="011"; -- 0x0C
-   constant UART_RX  : unsigned(2 downto 0):="100"; -- 0x10
-   constant CNT_1    : unsigned(2 downto 0):="101"; -- 0x14
-   constant CNT_2    : unsigned(2 downto 0):="110"; -- 0x18
+   constant IO_DATA   : unsigned(2 downto 0):="001"; -- 0x04
+   constant IO_DIR    : unsigned(2 downto 0):="010"; -- 0x08
+   constant UART_TX   : unsigned(2 downto 0):="011"; -- 0x0C
+   constant UART_RX   : unsigned(2 downto 0):="100"; -- 0x10
+   constant CNT_1     : unsigned(2 downto 0):="101"; -- 0x14
+   constant CNT_2     : unsigned(2 downto 0):="110"; -- 0x18
    -- "111" 0x1C Unused
    -- Unimplemented: Interrupt control and timer (not counter ...?)
 
@@ -110,7 +117,13 @@ architecture Behave of ZPUPhiIO is
    signal uart_write : std_logic; -- ZPU is writing
    signal tx_busy    : std_logic; -- Tx can't get a new value
 
+   -- GPIO
+   signal gpio_we    : std_logic;
+   signal is_gpio    : std_logic;
+   signal gpio_read  : unsigned(31 downto 0);
+
    file l_file       : text open write_mode is LOG_FILE;
+
 begin
    -----------
    -- Timer --
@@ -155,6 +168,27 @@ begin
       generic map(COUNT => 4)  
       port map(
          clk_i => clk_i, reset_i => reset_i, ce_i => rx_br, o_o => tx_br);
+   
+   ----------
+   -- GPIO --
+   ----------
+   gpio_i0: gpio
+      port map(
+          clk_i    => clk_i,              -- : in  std_logic;
+          reset_i  => reset_i,            -- : in  std_logic;
+          --                              
+          we_i     => gpio_we,            -- : in  std_logic;
+          data_i   => data_i,             -- : in  unsigned(31 downto 0);
+          addr_i   => addr_i(1 downto 1), -- : in  unsigned( 0 downto 0);
+          data_o   => gpio_read,          -- : out unsigned(31 downto 0);
+          --                              
+          port_in  => gpio_in,            -- : std_logic_vector(31 downto 0);
+          port_out => gpio_out,           -- : std_logic_vector(31 downto 0);
+          port_dir => gpio_dir            -- : std_logic_vector(31 downto 0);
+          );
+   is_gpio <= '1' when addr_i = IO_DATA or addr_i = IO_DIR else '0'; -- 0x80A0004/8
+   gpio_we <= we_i and is_gpio;
+
 
    do_io:
    process(clk_i)
@@ -177,8 +211,10 @@ begin
                     else
                         std.textio.write(line_out, char);
                     end if;
+               elsif is_gpio = '1' and ENA_LOG then
+                  print("- Write GPIO: 0x" & hstr(data_i));
                elsif is_timer='1' and ENA_LOG then
-                  print("- Write to TIMER: 0x"&hstr(data_i));
+                  print("- Write to TIMER: 0x" & hstr(data_i));
                else
                   --print(l_file,character'val(to_integer(data_i)));
                   report "Illegal IO data_i=0x"&hstr(data_i)&" @0x"&
@@ -188,7 +224,12 @@ begin
             --synopsys translate on
             data_o <= (others => '0');
             if re_i='1' then
-               if addr_i=UART_TX then
+               if is_gpio = '1' then
+                  if ENA_LOG then
+                     print("- Read  GPIO: 0x" & hstr(gpio_read));
+                  end if;
+                  data_o <= gpio_read;
+               elsif addr_i=UART_TX then
                   if ENA_LOG then
                      print("- Read UART Tx");
                   end if;
@@ -201,7 +242,7 @@ begin
                   data_o(7 downto 0) <= unsigned(rx_data);
                elsif is_timer='1' then
                   if ENA_LOG then
-                     print("- Read TIMER: 0x"&hstr(timer_read));
+                     print("- Read TIMER: 0x" & hstr(timer_read));
                   end if;
                   data_o <= timer_read;
                else
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation.sh b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation.sh
index febf588..d525737 100755
--- a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation.sh
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation.sh
@@ -28,6 +28,7 @@ vcom -work zpu ../../helpers/zpu_med1.vhdl
 vcom -work zpu ../../devices/txt_util.vhdl
 vcom -work zpu ../../devices/phi_io.vhdl
 vcom -work zpu ../../devices/timer.vhdl
+vcom -work zpu ../../devices/gpio.vhdl
 vcom -work zpu ../../devices/rx_unit.vhdl
 vcom -work zpu ../../devices/tx_unit.vhdl
 vcom -work zpu ../../devices/br_gen.vhdl
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/wave.do b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/wave.do
index 20e68e0..d572a06 100644
--- a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/wave.do
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/wave.do
@@ -1,26 +1,30 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate /top_tb/tb_gpio_button(0)
-add wave -noupdate /top_tb/tb_clk_100mhz
-add wave -noupdate -divider 
-add wave -noupdate /top_tb/tb_rs232_rx
-add wave -noupdate /top_tb/tb_rs232_tx
-add wave -noupdate /top_tb/tb_rs232_rts
-add wave -noupdate /top_tb/tb_rs232_cts
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {0 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 2
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-configure wave -timelineunits ns
-update
-WaveRestoreZoom {0 ps} {1188293312 ps}
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /top_tb/tb_gpio_button(0)
+add wave -noupdate /top_tb/tb_clk_100MHz
+add wave -noupdate -divider 
+add wave -noupdate /top_tb/tb_rs232_rx
+add wave -noupdate /top_tb/tb_rs232_tx
+add wave -noupdate /top_tb/tb_rs232_rts
+add wave -noupdate /top_tb/tb_rs232_cts
+add wave -noupdate -divider Buttons
+add wave -noupdate /top_tb/tb_gpio_button
+add wave -noupdate -divider LEDs
+add wave -noupdate /top_tb/tb_gpio_led_n
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {0 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 2
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ps} {126912555 ps}
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/avnet-eval-xc5vfx30t.ucf b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/avnet-eval-xc5vfx30t.ucf
index 30b3982..8494af3 100644
--- a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/avnet-eval-xc5vfx30t.ucf
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/avnet-eval-xc5vfx30t.ucf
@@ -29,6 +29,19 @@ TIMESPEC "TS_clk_100" = PERIOD "clk_100" 100 MHz;
 
 
 ############################################################
+## design placement constraints
+############################################################
+#
+# the following constraint are need if you want to synthesize
+# zpu_medium with 125 MHz
+#
+INST "zpu_i0_medium.zpu_i0/zpu/*" AREA_GROUP = "zpu_block";
+AREA_GROUP "zpu_block" RANGE=SLICE_X18Y0:SLICE_X55Y41;
+AREA_GROUP "zpu_block" RANGE=DSP48_X0Y0:DSP48_X0Y15;
+AREA_GROUP "zpu_block" RANGE=RAMB36_X1Y0:RAMB36_X3Y7;
+
+
+############################################################
 ## pin placement constraints
 ############################################################
 
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj
index 81d56ef..24120d5 100644
--- a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj
@@ -12,6 +12,7 @@ vhdl zpu ../../../helpers/zpu_med1.vhdl
 vhdl zpu ../../../devices/txt_util.vhdl
 vhdl zpu ../../../devices/phi_io.vhdl
 vhdl zpu ../../../devices/timer.vhdl
+vhdl zpu ../../../devices/gpio.vhdl
 vhdl zpu ../../../devices/rx_unit.vhdl
 vhdl zpu ../../../devices/tx_unit.vhdl
 vhdl zpu ../../../devices/br_gen.vhdl
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd
index 1e2fa97..53383cc 100644
--- a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd
@@ -22,7 +22,7 @@ use unisim.vcomponents.dcm_base;
 entity top is
     port (
         -- pragma translate_off 
-        stop_simulation : out   std_logic;
+        stop_simulation     : out   std_logic;
         -- pragma translate_on 
         clk_100MHz          : in    std_logic;  -- 100 MHz clock
         clk_socket          : in    std_logic;  -- user clock
@@ -169,7 +169,10 @@ architecture rtl of top is
             break_o    : out std_logic;        -- Break executed
             dbg_o      : out zpu_dbgo_t;       -- Debug info
             rs232_tx_o : out std_logic;        -- UART Tx
-            rs232_rx_i : in  std_logic         -- UART Rx
+            rs232_rx_i : in  std_logic;        -- UART Rx
+            gpio_in    : in  std_logic_vector(31 downto 0);
+            gpio_out   : out std_logic_vector(31 downto 0);
+            gpio_dir   : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
             );
     end component zpu_small1;
 
@@ -188,7 +191,10 @@ architecture rtl of top is
             break_o    : out std_logic;        -- Break executed
             dbg_o      : out zpu_dbgo_t;       -- Debug info
             rs232_tx_o : out std_logic;        -- UART Tx
-            rs232_rx_i : in  std_logic         -- UART Rx
+            rs232_rx_i : in  std_logic;        -- UART Rx
+            gpio_in    : in  std_logic_vector(31 downto 0);
+            gpio_out   : out std_logic_vector(31 downto 0);
+            gpio_dir   : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
             );
     end component zpu_med1;
 
@@ -210,7 +216,11 @@ architecture rtl of top is
     --
     signal ibufds_i0_o       : std_ulogic;
     signal ibufds_i1_o       : std_ulogic;
-
+    --
+    signal gpio_in           : std_logic_vector(31 downto 0) := (others => '0');
+    signal zpu_i0_gpio_out   : std_logic_vector(31 downto 0);
+    signal zpu_i0_gpio_dir   : std_logic_vector(31 downto 0);
+    
 begin
   
     -- default output drivers
@@ -348,12 +358,15 @@ begin
                 clk_freq  => clk_frequency * clk_multiply / clk_divide
                 )
             port map (
-                clk_i      => clk,           -- : in  std_logic;   - CPU clock
-                rst_i      => reset_sync,    -- : in  std_logic;   - Reset
-                break_o    => zpu_i0_break,  -- : out std_logic;   - Break executed
-                dbg_o      => zpu_i0_dbg,    -- : out zpu_dbgo_t;  - Debug info
-                rs232_tx_o => rs232_tx,      -- : out std_logic;   - UART Tx
-                rs232_rx_i => rs232_rx       -- : in  std_logic    - UART Rx
+                clk_i      => clk,             -- : in  std_logic;   - CPU clock
+                rst_i      => reset_sync,      -- : in  std_logic;   - Reset
+                break_o    => zpu_i0_break,    -- : out std_logic;   - Break executed
+                dbg_o      => zpu_i0_dbg,      -- : out zpu_dbgo_t;  - Debug info
+                rs232_tx_o => rs232_tx,        -- : out std_logic;   - UART Tx
+                rs232_rx_i => rs232_rx,        -- : in  std_logic    - UART Rx
+                gpio_in    => gpio_in,         -- : in  std_logic_vector(31 downto 0);
+                gpio_out   => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
+                gpio_dir   => zpu_i0_gpio_dir  -- : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
                 );
     end generate zpu_i0_small;
 
@@ -365,12 +378,15 @@ begin
                 clk_freq  => clk_frequency * clk_multiply / clk_divide
                 )
             port map (
-                clk_i      => clk,           -- : in  std_logic;   - CPU clock
-                rst_i      => reset_sync,    -- : in  std_logic;   - Reset
-                break_o    => zpu_i0_break,  -- : out std_logic;   - Break executed
-                dbg_o      => zpu_i0_dbg,    -- : out zpu_dbgo_t;  - Debug info
-                rs232_tx_o => rs232_tx,      -- : out std_logic;   - UART Tx
-                rs232_rx_i => rs232_rx       -- : in  std_logic    - UART Rx
+                clk_i      => clk,             -- : in  std_logic;   - CPU clock
+                rst_i      => reset_sync,      -- : in  std_logic;   - Reset
+                break_o    => zpu_i0_break,    -- : out std_logic;   - Break executed
+                dbg_o      => zpu_i0_dbg,      -- : out zpu_dbgo_t;  - Debug info
+                rs232_tx_o => rs232_tx,        -- : out std_logic;   - UART Tx
+                rs232_rx_i => rs232_rx,        -- : in  std_logic    - UART Rx
+                gpio_in    => gpio_in,         -- : in  std_logic_vector(31 downto 0);
+                gpio_out   => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
+                gpio_dir   => zpu_i0_gpio_dir  -- : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
                 );
     end generate zpu_i0_medium;
 
@@ -392,17 +408,21 @@ begin
             );
     -- pragma translate_on
 
+    -- assign GPIOs
+    -- no bidirectional pins (e.g. headers), so
+    -- gpio_dir is unused
+    gpio_in(15 downto 8) <= gpio_dipswitch;
+    gpio_in( 3 downto 0) <= gpio_button;
+
 
     -- switch on all LEDs in case of break
     process
     begin
         wait until rising_edge(clk);
+        gpio_led_n <= not zpu_i0_gpio_out(7 downto 0);
         if zpu_i0_break = '1' then
             gpio_led_n <= (others => '0');
         end if;
-        if reset_sync = '1' then
-            gpio_led_n <= (others => '1');
-        end if;
     end process;
 
 
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top_tb.vhd b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top_tb.vhd
index 0d173e2..751ce22 100644
--- a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top_tb.vhd
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top_tb.vhd
@@ -144,6 +144,9 @@ begin
     tb_gpio_button(0) <= '1', '0' after 6.66 * clk_100MHz_period;
 
 
+    -- simulate keypress
+    tb_gpio_button(2) <= '0', '1' after 55 us, '0' after 56 us;
+
     -- dut
     top_i0 : entity work.top
         port map (
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation.sh b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation.sh
index febf588..d525737 100755
--- a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation.sh
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation.sh
@@ -28,6 +28,7 @@ vcom -work zpu ../../helpers/zpu_med1.vhdl
 vcom -work zpu ../../devices/txt_util.vhdl
 vcom -work zpu ../../devices/phi_io.vhdl
 vcom -work zpu ../../devices/timer.vhdl
+vcom -work zpu ../../devices/gpio.vhdl
 vcom -work zpu ../../devices/rx_unit.vhdl
 vcom -work zpu ../../devices/tx_unit.vhdl
 vcom -work zpu ../../devices/br_gen.vhdl
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/run.do b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/run.do
index 7c5e18f..0d29e0a 100644
--- a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/run.do
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/run.do
@@ -1,4 +1,2 @@
-add wave tb_rot_center
-add wave tb_clk_50mhz
-add wave tb_rs232_dce*
-run -all
+do wave.do
+run -all
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/wave.do b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/wave.do
new file mode 100644
index 0000000..12582ce
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/wave.do
@@ -0,0 +1,30 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /top_tb/tb_rot_center
+add wave -noupdate /top_tb/tb_clk_50mhz
+add wave -noupdate /top_tb/tb_rs232_dce_rxd
+add wave -noupdate /top_tb/tb_rs232_dce_txd
+add wave -noupdate -divider Buttons
+add wave -noupdate /top_tb/tb_btn_east
+add wave -noupdate /top_tb/tb_btn_north
+add wave -noupdate /top_tb/tb_btn_south
+add wave -noupdate /top_tb/tb_btn_west
+add wave -noupdate -divider LEDs
+add wave -noupdate /top_tb/top_i0/led
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {56714893 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 2
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ps} {151772250 ps}
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj
index 81d56ef..965ae4c 100644
--- a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj
@@ -1,18 +1,19 @@
-vhdl work ../top.vhd
-vhdl zpu ../../../zpu_pkg.vhdl
-vhdl zpu ../../../zpu_small.vhdl
-vhdl zpu ../../../zpu_medium.vhdl
-vhdl zpu ../../../roms/rom_pkg.vhdl
-#vhdl zpu ../../../roms/hello_dbram.vhdl
-#vhdl zpu ../../../roms/hello_bram.vhdl
-vhdl zpu ../../../roms/dmips_dbram.vhdl
-vhdl zpu ../../../roms/dmips_bram.vhdl
-vhdl zpu ../../../helpers/zpu_small1.vhdl
-vhdl zpu ../../../helpers/zpu_med1.vhdl
-vhdl zpu ../../../devices/txt_util.vhdl
-vhdl zpu ../../../devices/phi_io.vhdl
-vhdl zpu ../../../devices/timer.vhdl
-vhdl zpu ../../../devices/rx_unit.vhdl
-vhdl zpu ../../../devices/tx_unit.vhdl
-vhdl zpu ../../../devices/br_gen.vhdl
-vhdl zpu ../../../devices/trace.vhdl
+vhdl work ../top.vhd
+vhdl zpu ../../../zpu_pkg.vhdl
+vhdl zpu ../../../zpu_small.vhdl
+vhdl zpu ../../../zpu_medium.vhdl
+vhdl zpu ../../../roms/rom_pkg.vhdl
+#vhdl zpu ../../../roms/hello_dbram.vhdl
+#vhdl zpu ../../../roms/hello_bram.vhdl
+vhdl zpu ../../../roms/dmips_dbram.vhdl
+vhdl zpu ../../../roms/dmips_bram.vhdl
+vhdl zpu ../../../helpers/zpu_small1.vhdl
+vhdl zpu ../../../helpers/zpu_med1.vhdl
+vhdl zpu ../../../devices/txt_util.vhdl
+vhdl zpu ../../../devices/phi_io.vhdl
+vhdl zpu ../../../devices/timer.vhdl
+vhdl zpu ../../../devices/gpio.vhdl
+vhdl zpu ../../../devices/rx_unit.vhdl
+vhdl zpu ../../../devices/tx_unit.vhdl
+vhdl zpu ../../../devices/br_gen.vhdl
+vhdl zpu ../../../devices/trace.vhdl
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut
index 06de8d5..4bf13c6 100644
--- a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut
@@ -1,22 +1,22 @@
--w
--g DebugBitstream:No
--g Binary:no
--g CRC:Enable
--g ConfigRate:1
--g ProgPin:PullUp
--g DonePin:PullUp
--g TckPin:PullUp
--g TdiPin:PullUp
--g TdoPin:PullUp
--g TmsPin:PullUp
--g UnusedPin:PullDown
--g UserID:0xFFFFFFFF
--g DCMShutdown:Disable
--g StartUpClk:CClk
--g DONE_cycle:4
--g GTS_cycle:5
--g GWE_cycle:6
--g LCK_cycle:NoWait
--g Security:None
--g DonePipe:No
--g DriveDone:No
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g ConfigRate:1
+-g ProgPin:PullUp
+-g DonePin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g DCMShutdown:Disable
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.xst b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.xst
index fc7cc1d..d357860 100644
--- a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.xst
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.xst
@@ -1,56 +1,56 @@
-set -tmpdir "tmp"
-set -xsthdpdir "xst"
-run
--ifn ../synthesis_config/top.prj
--ifmt mixed
--ofn top
--ofmt NGC
--p xc3s500e-4-fg320
--top top
--opt_mode Speed
--opt_level 1
--iuc NO
--keep_hierarchy No
--netlist_hierarchy As_Optimized
--rtlview Yes
--glob_opt AllClockNets
--read_cores YES
--write_timing_constraints NO
--cross_clock_analysis NO
--hierarchy_separator /
--bus_delimiter <>
--case Maintain
--slice_utilization_ratio 100
--bram_utilization_ratio 100
--verilog2001 YES
--fsm_extract YES -fsm_encoding Auto
--safe_implementation No
--fsm_style LUT
--ram_extract Yes
--ram_style Auto
--rom_extract Yes
--mux_style Auto
--decoder_extract YES
--priority_extract Yes
--shreg_extract YES
--shift_extract YES
--xor_collapse YES
--rom_style Auto
--auto_bram_packing NO
--mux_extract Yes
--resource_sharing YES
--async_to_sync NO
--mult_style Auto
--iobuf YES
--max_fanout 500
--bufg 24
--register_duplication YES
--register_balancing No
--slice_packing YES
--optimize_primitives NO
--use_clock_enable Yes
--use_sync_set Yes
--use_sync_reset Yes
--iob Auto
--equivalent_register_removal YES
--slice_utilization_ratio_maxmargin 5
+set -tmpdir "tmp"
+set -xsthdpdir "xst"
+run
+-ifn ../synthesis_config/top.prj
+-ifmt mixed
+-ofn top
+-ofmt NGC
+-p xc3s500e-4-fg320
+-top top
+-opt_mode Speed
+-opt_level 1
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract Yes
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-auto_bram_packing NO
+-mux_extract Yes
+-resource_sharing YES
+-async_to_sync NO
+-mult_style Auto
+-iobuf YES
+-max_fanout 500
+-bufg 24
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Yes
+-use_sync_set Yes
+-use_sync_reset Yes
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top.vhd b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top.vhd
index 127f6a8..79668e5 100644
--- a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top.vhd
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top.vhd
@@ -1,419 +1,447 @@
--- top module of
--- Spartan-3E Starter Kit Board
---
--- using following external connections:
--- rotary pushbutton as reset
--- LEDs   for output
--- RS232 (DCE, the left one)
---
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-library zpu;
-use zpu.zpupkg.all;                     -- zpu_dbgo_t
-
-library unisim;
-use unisim.vcomponents.dcm_sp;
-
-
-entity top is
-    port (
-        -- pragma translate_off 
-        stop_simulation : out   std_logic;
-        -- pragma translate_on 
-        --
-        -- Analog-to-Digital Converter (ADC)
-        ad_conv         : out   std_logic;
-        -- Programmable Gain Amplifier (AMP)
-        amp_cs          : out   std_logic;  -- active low chip select
-        amp_dout        : in    std_logic;
-        amp_shdn        : out   std_logic;  -- active high shutdown, reset
-        -- Pushbuttons (BTN)
-        btn_east        : in    std_logic;
-        btn_north       : in    std_logic;
-        btn_south       : in    std_logic;
-        btn_west        : in    std_logic;
-        -- Clock inputs (CLK)
-        clk_50mhz       : in    std_logic;
-        clk_aux         : in    std_logic;
-        clk_sma         : in    std_logic;
-        -- Digital-to-Analog Converter (DAC)
-        dac_clr         : out   std_logic;  -- async, active low reset input
-        dac_cs          : out   std_logic;  -- active low chip select, conv start with rising edge
-        -- 1-Wire Secure EEPROM (DS)
-        ds_wire         : inout std_logic;
-        -- Ethernet PHY (E)
-        e_col           : in    std_logic;  -- MII collision detect
-        e_crs           : in    std_logic;  -- carrier sense
-        e_mdc           : out   std_logic;  -- management clock
-        e_mdio          : inout std_logic;  -- management data io
-        e_rx_clk        : in    std_logic;  -- receive clock 25MHz@100BaseTx or 2.5MHz@10Base-T
-        e_rx_dv         : in    std_logic;  -- receive data valid
-        e_rxd           : in    std_logic_vector(3 downto 0);
-        e_rx_er         : in    std_logic;
-        e_tx_clk        : in    std_logic;  -- transmit clock 25MHz@100BaseTx or 2.5MHz@10Base-T
-        e_tx_en         : out   std_logic;  -- transmit enable
-        e_txd           : out   std_logic_vector(3 downto 0);
-        e_tx_er         : out   std_logic;
-        -- FPGA Configuration Mode, INIT_B Pins (FPGA)
-        fpga_m0         : inout std_logic;
-        fpga_m1         : inout std_logic;
-        fpga_m2         : inout std_logic;
-        fpga_init_b     : inout std_logic;
-        fpga_rdwr_b     : in    std_logic;
-        fpga_hswap      : in    std_logic;
-        -- FX2 Connector (FX2)
-        fx2_clkin       : inout std_logic;
-        fx2_clkio       : inout std_logic;
-        fx2_clkout      : inout std_logic;
-        fx2_io          : inout std_logic_vector(40 downto 1);
-        -- These are shared connections with the FX2 connector
-        --j1              : inout std_logic_vector(3 downto 0);
-        --j2              : inout std_logic_vector(3 downto 0);
-        --j4              : inout std_logic_vector(3 downto 0);
-        --led             : out   std_logic_vector(7 downto 0);
-        -- Character LCD (LCD)
-        lcd_e           : out   std_logic;
-        lcd_rs          : out   std_logic;
-        lcd_rw          : out   std_logic;
-        -- LCD data connections are shared with StrataFlash connections SF_D<11:8>
-        --sf_d          : inout std_ulogic_vector(11 downto 8);
-        -- PS/2 Mouse/Keyboard Port (PS2)
-        ps2_clk         : inout std_logic;
-        ps2_data        : inout std_logic;
-        -- Rotary Pushbutton Switch (ROT)
-        rot_a           : in    std_logic;
-        rot_b           : in    std_logic;
-        rot_center      : in    std_logic;
-        -- RS-232 Serial Ports (RS232)
-        rs232_dce_rxd   : in    std_logic;
-        rs232_dce_txd   : out   std_logic;
-        rs232_dte_rxd   : in    std_logic;
-        rs232_dte_txd   : out   std_logic;
-        -- DDR SDRAM (SD) (I/O Bank 3, VCCO=2.5V)
-        sd_a            : out   std_logic_vector(12 downto 0);  -- address inputs
-        sd_dq           : inout std_logic_vector(15 downto 0);  -- data io
-        sd_ba           : out   std_logic_vector(1 downto 0);   -- bank address inputs
-        sd_ras          : out   std_logic;                      -- command output
-        sd_cas          : out   std_logic;                      -- command output
-        sd_we           : out   std_logic;                      -- command output 
-        sd_udm          : out   std_logic;                      -- data mask
-        sd_ldm          : out   std_logic;                      -- data mask
-        sd_udqs         : inout std_logic;                      -- data strobe
-        sd_ldqs         : inout std_logic;                      -- data strobe
-        sd_cs           : out   std_logic;                      -- active low chip select
-        sd_cke          : out   std_logic;                      -- active high clock enable
-        sd_ck_n         : out   std_logic;                      -- differential clock
-        sd_ck_p         : out   std_logic;                      -- differential clock
-        -- Path to allow connection to top DCM connection
-        sd_ck_fb        : in    std_logic;
-        -- Intel StrataFlash Parallel NOR Flash (SF)
-        sf_a            : out   std_logic_vector(23 downto 0);  -- sf_a<24> = fx_io32
-        sf_byte         : out   std_logic;
-        sf_ce0          : out   std_logic;
-        sf_d            : inout std_logic_vector(15 downto 1);
-        sf_oe           : out   std_logic;
-        sf_sts          : in    std_logic;
-        sf_we           : out   std_logic;
-        -- STMicro SPI serial Flash (SPI)
-        spi_mosi        : out   std_logic;  -- master out slave in
-        spi_miso        : in    std_logic;  -- master in  slave out
-        spi_sck         : out   std_logic;  -- clock
-        spi_ss_b        : out   std_logic;  -- active low slave select
-        spi_alt_cs_jp11 : out   std_logic;
-        -- Slide Switches (SW)
-        sw              : in    std_logic_vector(3 downto 0);
-        -- VGA Port (VGA)
-        vga_blue        : out   std_logic;
-        vga_green       : out   std_logic;
-        vga_hsync       : out   std_logic;
-        vga_red         : out   std_logic;
-        vga_vsync       : out   std_logic;
-        -- Xilinx CPLD (XC)
-        xc_cmd          : out   std_logic_vector(1 downto 0);
-        xc_cpld_en      : out   std_logic;
-        xc_d            : inout std_logic_vector(2 downto 0);
-        xc_trig         : in    std_logic;
-        xc_gck0         : inout std_logic;
-        gclk10          : inout std_logic
-        );
-end entity top;
-
-
-architecture rtl of top is
-
-    ---------------------------
-    -- type declarations
-    type zpu_type is (zpu_small, zpu_medium);
-
-    ---------------------------
-    -- constant declarations
-    constant zpu_flavour : zpu_type := zpu_medium;  -- choose your flavour HERE
-    --  modify frequency here
-    constant clk_multiply : positive := 3;  -- 2 for small, 3 for medium
-    constant clk_divide   : positive := 2;  -- 1 for small, 2 for medium
-    --
-    constant word_size_c  : natural  := 32; -- 32 bits data path
-    constant addr_w_c     : natural  := 18; -- 18 bits address space=256 kB, 128 kB I/O
-
-
-    constant spi_ss_b_disable    : std_ulogic := '1';  -- 1 = disable SPI serial flash
-    constant dac_cs_disable      : std_ulogic := '1';  -- 1 = disable DAC 
-    constant amp_cs_disable      : std_ulogic := '1';  -- 1 = disable programmable pre-amplifier
-    constant ad_conv_disable     : std_ulogic := '0';  -- 0 = disable ADC
-    constant sf_ce0_disable      : std_ulogic := '1';
-    constant fpga_init_b_disable : std_ulogic := '1';  -- 1 = disable pflatform flash PROM
-    --
-    -- connect ldc to fpga
-    constant sf_ce0_lcd_to_fpga  : std_ulogic := '1';
-    --
-    constant clk_frequency       : positive   := 50;   -- input frequency for correct calculation
-
-
-    ---------------------------
-    -- component declarations
-    component zpu_small1 is
-        generic (
-            word_size  : natural   := 32;      -- 32 bits data path
-            d_care_val : std_logic := '0';     -- Fill value
-            clk_freq   : positive  := 50;      -- 50 MHz clock
-            brate      : positive  := 115200;  -- RS232 baudrate
-            addr_w     : natural   := 16;      -- 16 bits address space=64 kB, 32 kB I/O
-            bram_w     : natural   := 15       -- 15 bits RAM space=32 kB
-            );
-        port (
-            clk_i      : in  std_logic;        -- CPU clock
-            rst_i      : in  std_logic;        -- Reset
-            break_o    : out std_logic;        -- Break executed
-            dbg_o      : out zpu_dbgo_t;       -- Debug info
-            rs232_tx_o : out std_logic;        -- UART Tx
-            rs232_rx_i : in  std_logic         -- UART Rx
-            );
-    end component zpu_small1;
-
-    component zpu_med1 is
-        generic(
-            word_size  : natural   := 32;      -- 32 bits data path
-            d_care_val : std_logic := '0';     -- Fill value
-            clk_freq   : positive  := 50;      -- 50 MHz clock
-            brate      : positive  := 115200;  -- RS232 baudrate
-            addr_w     : natural   := 18;      -- 18 bits address space=256 kB, 128 kB I/O
-            bram_w     : natural   := 15       -- 15 bits RAM space=32 kB
-            );
-        port(
-            clk_i      : in  std_logic;        -- CPU clock
-            rst_i      : in  std_logic;        -- Reset
-            break_o    : out std_logic;        -- Break executed
-            dbg_o      : out zpu_dbgo_t;       -- Debug info
-            rs232_tx_o : out std_logic;        -- UART Tx
-            rs232_rx_i : in  std_logic         -- UART Rx
-            );
-    end component zpu_med1;
-
-
-    ---------------------------
-    -- signal declarations
-    signal dcm_sp_i0_clk0  : std_ulogic;
-    signal dcm_sp_i0_clkfx : std_ulogic;
-    signal clk_fb          : std_ulogic;
-    signal clk             : std_ulogic;
-    --
-    signal reset_shift_reg : std_ulogic_vector(3 downto 0);
-    signal reset_sync      : std_ulogic;
-    --
-    signal zpu_i0_dbg      : zpu_dbgo_t;  -- Debug info
-    signal zpu_i0_break    : std_logic;
-
-    ---------------------------
-    -- alias declarations
-    alias led : std_logic_vector(7 downto 0) is fx2_io(20 downto 13);
-
-
-begin
-
-    -- default output drivers
-    -- to pass bitgen DRC 
-    -- outputs used by design are commented
-    --
-    ad_conv           <= ad_conv_disable;
-    amp_cs            <= amp_cs_disable;
-    amp_shdn          <= '1';
-    --
-    dac_clr           <= '0';
-    dac_cs            <= dac_cs_disable;
-    --
-    ds_wire           <= 'Z';
-    --
-    e_txd(3 downto 0) <= (others => '1');
-    e_tx_en           <= '0';
-    e_tx_er           <= '0';
-    e_mdc             <= '1';
-    e_mdio            <= 'Z';
-    --
-    fpga_m0           <= 'Z';
-    fpga_m1           <= 'Z';
-    fpga_m2           <= 'Z';
-    fpga_init_b       <= fpga_init_b_disable;
-    --
-    fx2_clkin         <= 'Z';
-    fx2_clkio         <= 'Z';
-    fx2_clkout        <= 'Z';
-    fx2_io            <= (others => 'Z');
-    --
-    lcd_e             <= '0';
-    lcd_rs            <= '0';
-    lcd_rw            <= '0';
-    --
-    ps2_clk           <= 'Z';
-    ps2_data          <= 'Z';
-    --
-    --rs232_dce_txd     <= '1';
-    rs232_dte_txd     <= '1';
-    --
-    sd_a              <= (others => '1');
-    sd_dq             <= (others => 'Z');
-    sd_ba             <= (others => '1');
-    sd_ras            <= '0';
-    sd_cas            <= '0';
-    sd_we             <= '0';
-    sd_udm            <= '1';
-    sd_ldm            <= '1';
-    sd_udqs           <= '1';
-    sd_ldqs           <= '1';
-    sd_cs             <= '1';
-    sd_cke            <= '1';
-    sd_ck_n           <= '0';
-    sd_ck_p           <= '1';
-    --
-    sf_a              <= (others => '0');
-    sf_byte           <= '0';
-    sf_ce0            <= sf_ce0_lcd_to_fpga;
-    sf_d              <= (others => 'Z');
-    sf_oe             <= '1';
-    sf_we             <= '0';
-    --
-    spi_mosi          <= '0';
-    spi_sck           <= '0';
-    spi_ss_b          <= spi_ss_b_disable;
-    spi_alt_cs_jp11   <= spi_ss_b_disable;
-    --
-    vga_red           <= '0';
-    vga_green         <= '0';
-    vga_blue          <= '0';
-    vga_hsync         <= '0';
-    vga_vsync         <= '0';
-    --
-    xc_cmd            <= "00";
-    xc_d              <= (others => 'Z');
-    xc_cpld_en        <= '0';
-    xc_gck0           <= 'Z';
-    gclk10            <= 'Z';
-    -- led out
-    --fx2_io(20 downto 13) <= (others => '0');
-
-
-    -- digital clock manager (DCM)
-    -- to generate higher/other system clock frequencys
-    dcm_sp_i0 : dcm_sp
-        generic map (
-            startup_wait   => true,     -- wait with DONE till locked
-            clkfx_multiply => clk_multiply,
-            clkfx_divide   => clk_divide, 
-            clk_feedback   => "1X"
-            )
-        port map (
-            clkin => clk_50mhz,
-            clk0  => dcm_sp_i0_clk0,
-            clkfx => dcm_sp_i0_clkfx,
-            clkfb => clk_fb
-            );
-
-    clk_fb <= dcm_sp_i0_clk0;
-    clk    <= dcm_sp_i0_clkfx;
-
-
-    -- reset synchronizer
-    -- generate synchronous reset
-    reset_synchronizer : process(clk, rot_center)
-    begin
-        if rot_center = '1' then
-            reset_shift_reg <= (others => '1');
-        elsif rising_edge(clk) then
-            reset_shift_reg <= reset_shift_reg(reset_shift_reg'high-1 downto 0) & '0';
-        end if;
-    end process;
-    reset_sync <= reset_shift_reg(reset_shift_reg'high);
-
-
-    -- select instance of zpu
-    zpu_i0_small : if zpu_flavour = zpu_small generate
-        zpu_i0 : zpu_small1
-            generic map (
-                addr_w    => addr_w_c,
-                word_size => word_size_c,
-                clk_freq  => clk_frequency * clk_multiply / clk_divide
-                )
-            port map (
-                clk_i      => clk,           -- : in  std_logic;   -- CPU clock
-                rst_i      => reset_sync,    -- : in  std_logic;   -- Reset
-                break_o    => zpu_i0_break,  -- : out std_logic;   -- Break executed
-                dbg_o      => zpu_i0_dbg,    -- : out zpu_dbgo_t;  -- Debug info
-                rs232_tx_o => rs232_dce_txd, -- : out std_logic;   -- UART Tx
-                rs232_rx_i => rs232_dce_rxd  -- : in  std_logic    -- UART Rx
-                );
-    end generate zpu_i0_small;
-
-    zpu_i0_medium : if zpu_flavour = zpu_medium generate
-        zpu_i0 : zpu_med1
-            generic map (
-                addr_w    => addr_w_c,
-                word_size => word_size_c,
-                clk_freq  => clk_frequency * clk_multiply / clk_divide
-                )
-            port map (
-                clk_i      => clk,            -- : in  std_logic;   -- CPU clock
-                rst_i      => reset_sync,     -- : in  std_logic;   -- Reset
-                break_o    => zpu_i0_break,   -- : out std_logic;   -- Break executed
-                dbg_o      => zpu_i0_dbg,     -- : out zpu_dbgo_t;  -- Debug info
-                rs232_tx_o => rs232_dce_txd,  -- : out std_logic;   -- UART Tx
-                rs232_rx_i => rs232_dce_rxd   -- : in  std_logic    -- UART Rx
-                );
-    end generate zpu_i0_medium;
-
-
-    -- pragma translate_off 
-    stop_simulation <= zpu_i0_break;
-
-
-    trace_mod : trace
-        generic map (
-            addr_w    => addr_w_c,
-            word_size => word_size_c,
-            log_file  => "zpu_trace.log"
-            )
-        port map (
-            clk_i  => clk,
-            dbg_i  => zpu_i0_dbg,
-            stop_i => zpu_i0_break,
-            busy_i => '0'
-            );
-    -- pragma translate_on
-
-
-    -- switch on all LEDs in case of break
-    process
-    begin
-        wait until rising_edge(clk);
-        if zpu_i0_break = '1' then
-            led <= (others => '1');
-        end if;
-        if reset_sync = '1' then
-            led <= (others => '0');
-        end if;
-    end process;
-
-    
-
-end architecture rtl;
+-- top module of
+-- Spartan-3E Starter Kit Board
+--
+-- using following external connections:
+-- rotary pushbutton as reset
+-- LEDs   for output
+-- RS232 (DCE, the left one)
+--
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library zpu;
+use zpu.zpupkg.all;                     -- zpu_dbgo_t
+
+library unisim;
+use unisim.vcomponents.dcm_sp;
+
+
+entity top is
+    port (
+        -- pragma translate_off 
+        stop_simulation : out   std_logic;
+        -- pragma translate_on 
+        --
+        -- Analog-to-Digital Converter (ADC)
+        ad_conv         : out   std_logic;
+        -- Programmable Gain Amplifier (AMP)
+        amp_cs          : out   std_logic;  -- active low chip select
+        amp_dout        : in    std_logic;
+        amp_shdn        : out   std_logic;  -- active high shutdown, reset
+        -- Pushbuttons (BTN)
+        btn_east        : in    std_logic;
+        btn_north       : in    std_logic;
+        btn_south       : in    std_logic;
+        btn_west        : in    std_logic;
+        -- Clock inputs (CLK)
+        clk_50mhz       : in    std_logic;
+        clk_aux         : in    std_logic;
+        clk_sma         : in    std_logic;
+        -- Digital-to-Analog Converter (DAC)
+        dac_clr         : out   std_logic;  -- async, active low reset input
+        dac_cs          : out   std_logic;  -- active low chip select, conv start with rising edge
+        -- 1-Wire Secure EEPROM (DS)
+        ds_wire         : inout std_logic;
+        -- Ethernet PHY (E)
+        e_col           : in    std_logic;  -- MII collision detect
+        e_crs           : in    std_logic;  -- carrier sense
+        e_mdc           : out   std_logic;  -- management clock
+        e_mdio          : inout std_logic;  -- management data io
+        e_rx_clk        : in    std_logic;  -- receive clock 25MHz@100BaseTx or 2.5MHz@10Base-T
+        e_rx_dv         : in    std_logic;  -- receive data valid
+        e_rxd           : in    std_logic_vector(3 downto 0);
+        e_rx_er         : in    std_logic;
+        e_tx_clk        : in    std_logic;  -- transmit clock 25MHz@100BaseTx or 2.5MHz@10Base-T
+        e_tx_en         : out   std_logic;  -- transmit enable
+        e_txd           : out   std_logic_vector(3 downto 0);
+        e_tx_er         : out   std_logic;
+        -- FPGA Configuration Mode, INIT_B Pins (FPGA)
+        fpga_m0         : inout std_logic;
+        fpga_m1         : inout std_logic;
+        fpga_m2         : inout std_logic;
+        fpga_init_b     : inout std_logic;
+        fpga_rdwr_b     : in    std_logic;
+        fpga_hswap      : in    std_logic;
+        -- FX2 Connector (FX2)
+        fx2_clkin       : inout std_logic;
+        fx2_clkio       : inout std_logic;
+        fx2_clkout      : inout std_logic;
+        fx2_io          : inout std_logic_vector(40 downto 1);
+        -- These are shared connections with the FX2 connector
+        --j1              : inout std_logic_vector(3 downto 0);
+        --j2              : inout std_logic_vector(3 downto 0);
+        --j4              : inout std_logic_vector(3 downto 0);
+        --led             : out   std_logic_vector(7 downto 0);
+        -- Character LCD (LCD)
+        lcd_e           : out   std_logic;
+        lcd_rs          : out   std_logic;
+        lcd_rw          : out   std_logic;
+        -- LCD data connections are shared with StrataFlash connections SF_D<11:8>
+        --sf_d          : inout std_ulogic_vector(11 downto 8);
+        -- PS/2 Mouse/Keyboard Port (PS2)
+        ps2_clk         : inout std_logic;
+        ps2_data        : inout std_logic;
+        -- Rotary Pushbutton Switch (ROT)
+        rot_a           : in    std_logic;
+        rot_b           : in    std_logic;
+        rot_center      : in    std_logic;
+        -- RS-232 Serial Ports (RS232)
+        rs232_dce_rxd   : in    std_logic;
+        rs232_dce_txd   : out   std_logic;
+        rs232_dte_rxd   : in    std_logic;
+        rs232_dte_txd   : out   std_logic;
+        -- DDR SDRAM (SD) (I/O Bank 3, VCCO=2.5V)
+        sd_a            : out   std_logic_vector(12 downto 0);  -- address inputs
+        sd_dq           : inout std_logic_vector(15 downto 0);  -- data io
+        sd_ba           : out   std_logic_vector(1 downto 0);   -- bank address inputs
+        sd_ras          : out   std_logic;                      -- command output
+        sd_cas          : out   std_logic;                      -- command output
+        sd_we           : out   std_logic;                      -- command output 
+        sd_udm          : out   std_logic;                      -- data mask
+        sd_ldm          : out   std_logic;                      -- data mask
+        sd_udqs         : inout std_logic;                      -- data strobe
+        sd_ldqs         : inout std_logic;                      -- data strobe
+        sd_cs           : out   std_logic;                      -- active low chip select
+        sd_cke          : out   std_logic;                      -- active high clock enable
+        sd_ck_n         : out   std_logic;                      -- differential clock
+        sd_ck_p         : out   std_logic;                      -- differential clock
+        -- Path to allow connection to top DCM connection
+        sd_ck_fb        : in    std_logic;
+        -- Intel StrataFlash Parallel NOR Flash (SF)
+        sf_a            : out   std_logic_vector(23 downto 0);  -- sf_a<24> = fx_io32
+        sf_byte         : out   std_logic;
+        sf_ce0          : out   std_logic;
+        sf_d            : inout std_logic_vector(15 downto 1);
+        sf_oe           : out   std_logic;
+        sf_sts          : in    std_logic;
+        sf_we           : out   std_logic;
+        -- STMicro SPI serial Flash (SPI)
+        spi_mosi        : out   std_logic;  -- master out slave in
+        spi_miso        : in    std_logic;  -- master in  slave out
+        spi_sck         : out   std_logic;  -- clock
+        spi_ss_b        : out   std_logic;  -- active low slave select
+        spi_alt_cs_jp11 : out   std_logic;
+        -- Slide Switches (SW)
+        sw              : in    std_logic_vector(3 downto 0);
+        -- VGA Port (VGA)
+        vga_blue        : out   std_logic;
+        vga_green       : out   std_logic;
+        vga_hsync       : out   std_logic;
+        vga_red         : out   std_logic;
+        vga_vsync       : out   std_logic;
+        -- Xilinx CPLD (XC)
+        xc_cmd          : out   std_logic_vector(1 downto 0);
+        xc_cpld_en      : out   std_logic;
+        xc_d            : inout std_logic_vector(2 downto 0);
+        xc_trig         : in    std_logic;
+        xc_gck0         : inout std_logic;
+        gclk10          : inout std_logic
+        );
+end entity top;
+
+
+architecture rtl of top is
+
+    ---------------------------
+    -- type declarations
+    type zpu_type is (zpu_small, zpu_medium);
+
+    ---------------------------
+    -- constant declarations
+    constant zpu_flavour : zpu_type := zpu_medium;  -- choose your flavour HERE
+    --  modify frequency here
+    constant clk_multiply : positive := 3;  -- 2 for small, 3 for medium
+    constant clk_divide   : positive := 2;  -- 1 for small, 2 for medium
+    --
+    constant word_size_c  : natural  := 32; -- 32 bits data path
+    constant addr_w_c     : natural  := 18; -- 18 bits address space=256 kB, 128 kB I/O
+
+
+    constant spi_ss_b_disable    : std_ulogic := '1';  -- 1 = disable SPI serial flash
+    constant dac_cs_disable      : std_ulogic := '1';  -- 1 = disable DAC 
+    constant amp_cs_disable      : std_ulogic := '1';  -- 1 = disable programmable pre-amplifier
+    constant ad_conv_disable     : std_ulogic := '0';  -- 0 = disable ADC
+    constant sf_ce0_disable      : std_ulogic := '1';
+    constant fpga_init_b_disable : std_ulogic := '1';  -- 1 = disable pflatform flash PROM
+    --
+    -- connect ldc to fpga
+    constant sf_ce0_lcd_to_fpga  : std_ulogic := '1';
+    --
+    constant clk_frequency       : positive   := 50;   -- input frequency for correct calculation
+
+
+    ---------------------------
+    -- component declarations
+    component zpu_small1 is
+        generic (
+            word_size  : natural   := 32;      -- 32 bits data path
+            d_care_val : std_logic := '0';     -- Fill value
+            clk_freq   : positive  := 50;      -- 50 MHz clock
+            brate      : positive  := 115200;  -- RS232 baudrate
+            addr_w     : natural   := 16;      -- 16 bits address space=64 kB, 32 kB I/O
+            bram_w     : natural   := 15       -- 15 bits RAM space=32 kB
+            );
+        port (
+            clk_i      : in  std_logic;        -- CPU clock
+            rst_i      : in  std_logic;        -- Reset
+            break_o    : out std_logic;        -- Break executed
+            dbg_o      : out zpu_dbgo_t;       -- Debug info
+            rs232_tx_o : out std_logic;        -- UART Tx
+            rs232_rx_i : in  std_logic;        -- UART Rx
+            gpio_in    : in  std_logic_vector(31 downto 0);
+            gpio_out   : out std_logic_vector(31 downto 0);
+            gpio_dir   : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
+            );
+    end component zpu_small1;
+
+    component zpu_med1 is
+        generic(
+            word_size  : natural   := 32;      -- 32 bits data path
+            d_care_val : std_logic := '0';     -- Fill value
+            clk_freq   : positive  := 50;      -- 50 MHz clock
+            brate      : positive  := 115200;  -- RS232 baudrate
+            addr_w     : natural   := 18;      -- 18 bits address space=256 kB, 128 kB I/O
+            bram_w     : natural   := 15       -- 15 bits RAM space=32 kB
+            );
+        port(
+            clk_i      : in  std_logic;        -- CPU clock
+            rst_i      : in  std_logic;        -- Reset
+            break_o    : out std_logic;        -- Break executed
+            dbg_o      : out zpu_dbgo_t;       -- Debug info
+            rs232_tx_o : out std_logic;        -- UART Tx
+            rs232_rx_i : in  std_logic;        -- UART Rx
+            gpio_in    : in  std_logic_vector(31 downto 0);
+            gpio_out   : out std_logic_vector(31 downto 0);
+            gpio_dir   : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
+            );
+    end component zpu_med1;
+
+
+    ---------------------------
+    -- signal declarations
+    signal dcm_sp_i0_clk0  : std_ulogic;
+    signal dcm_sp_i0_clkfx : std_ulogic;
+    signal clk_fb          : std_ulogic;
+    signal clk             : std_ulogic;
+    --
+    signal reset_shift_reg : std_ulogic_vector(3 downto 0);
+    signal reset_sync      : std_ulogic;
+    --
+    signal zpu_i0_dbg      : zpu_dbgo_t;  -- Debug info
+    signal zpu_i0_break    : std_logic;
+    --
+    signal gpio_in         : std_logic_vector(31 downto 0);
+    signal zpu_i0_gpio_out : std_logic_vector(31 downto 0);
+    signal zpu_i0_gpio_dir : std_logic_vector(31 downto 0);
+    
+    ---------------------------
+    -- alias declarations
+    alias led : std_logic_vector(7 downto 0) is fx2_io(20 downto 13);
+
+
+begin
+
+    -- default output drivers
+    -- to pass bitgen DRC 
+    -- outputs used by design are commented
+    --
+    ad_conv           <= ad_conv_disable;
+    amp_cs            <= amp_cs_disable;
+    amp_shdn          <= '1';
+    --
+    dac_clr           <= '0';
+    dac_cs            <= dac_cs_disable;
+    --
+    ds_wire           <= 'Z';
+    --
+    e_txd(3 downto 0) <= (others => '1');
+    e_tx_en           <= '0';
+    e_tx_er           <= '0';
+    e_mdc             <= '1';
+    e_mdio            <= 'Z';
+    --
+    fpga_m0           <= 'Z';
+    fpga_m1           <= 'Z';
+    fpga_m2           <= 'Z';
+    fpga_init_b       <= fpga_init_b_disable;
+    --
+    fx2_clkin         <= 'Z';
+    fx2_clkio         <= 'Z';
+    fx2_clkout        <= 'Z';
+    fx2_io            <= (others => 'Z');
+    --
+    lcd_e             <= '0';
+    lcd_rs            <= '0';
+    lcd_rw            <= '0';
+    --
+    ps2_clk           <= 'Z';
+    ps2_data          <= 'Z';
+    --
+    --rs232_dce_txd     <= '1';
+    rs232_dte_txd     <= '1';
+    --
+    sd_a              <= (others => '1');
+    sd_dq             <= (others => 'Z');
+    sd_ba             <= (others => '1');
+    sd_ras            <= '0';
+    sd_cas            <= '0';
+    sd_we             <= '0';
+    sd_udm            <= '1';
+    sd_ldm            <= '1';
+    sd_udqs           <= '1';
+    sd_ldqs           <= '1';
+    sd_cs             <= '1';
+    sd_cke            <= '1';
+    sd_ck_n           <= '0';
+    sd_ck_p           <= '1';
+    --
+    sf_a              <= (others => '0');
+    sf_byte           <= '0';
+    sf_ce0            <= sf_ce0_lcd_to_fpga;
+    sf_d              <= (others => 'Z');
+    sf_oe             <= '1';
+    sf_we             <= '0';
+    --
+    spi_mosi          <= '0';
+    spi_sck           <= '0';
+    spi_ss_b          <= spi_ss_b_disable;
+    spi_alt_cs_jp11   <= spi_ss_b_disable;
+    --
+    vga_red           <= '0';
+    vga_green         <= '0';
+    vga_blue          <= '0';
+    vga_hsync         <= '0';
+    vga_vsync         <= '0';
+    --
+    xc_cmd            <= "00";
+    xc_d              <= (others => 'Z');
+    xc_cpld_en        <= '0';
+    xc_gck0           <= 'Z';
+    gclk10            <= 'Z';
+    -- led out
+    --fx2_io(20 downto 13) <= (others => '0');
+
+
+    -- digital clock manager (DCM)
+    -- to generate higher/other system clock frequencys
+    dcm_sp_i0 : dcm_sp
+        generic map (
+            startup_wait   => true,     -- wait with DONE till locked
+            clkfx_multiply => clk_multiply,
+            clkfx_divide   => clk_divide, 
+            clk_feedback   => "1X"
+            )
+        port map (
+            clkin => clk_50mhz,
+            clk0  => dcm_sp_i0_clk0,
+            clkfx => dcm_sp_i0_clkfx,
+            clkfb => clk_fb
+            );
+
+    clk_fb <= dcm_sp_i0_clk0;
+    clk    <= dcm_sp_i0_clkfx;
+
+
+    -- reset synchronizer
+    -- generate synchronous reset
+    reset_synchronizer : process(clk, rot_center)
+    begin
+        if rot_center = '1' then
+            reset_shift_reg <= (others => '1');
+        elsif rising_edge(clk) then
+            reset_shift_reg <= reset_shift_reg(reset_shift_reg'high-1 downto 0) & '0';
+        end if;
+    end process;
+    reset_sync <= reset_shift_reg(reset_shift_reg'high);
+
+
+    -- select instance of zpu
+    zpu_i0_small : if zpu_flavour = zpu_small generate
+        zpu_i0 : zpu_small1
+            generic map (
+                addr_w    => addr_w_c,
+                word_size => word_size_c,
+                clk_freq  => clk_frequency * clk_multiply / clk_divide
+                )
+            port map (
+                clk_i      => clk,             -- : in  std_logic;   -- CPU clock
+                rst_i      => reset_sync,      -- : in  std_logic;   -- Reset
+                break_o    => zpu_i0_break,    -- : out std_logic;   -- Break executed
+                dbg_o      => zpu_i0_dbg,      -- : out zpu_dbgo_t;  -- Debug info
+                rs232_tx_o => rs232_dce_txd,   -- : out std_logic;   -- UART Tx
+                rs232_rx_i => rs232_dce_rxd,   -- : in  std_logic    -- UART Rx
+                gpio_in    => gpio_in,         -- : in  std_logic_vector(31 downto 0);
+                gpio_out   => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
+                gpio_dir   => zpu_i0_gpio_dir  -- : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
+                );
+    end generate zpu_i0_small;
+
+    zpu_i0_medium : if zpu_flavour = zpu_medium generate
+        zpu_i0 : zpu_med1
+            generic map (
+                addr_w    => addr_w_c,
+                word_size => word_size_c,
+                clk_freq  => clk_frequency * clk_multiply / clk_divide
+                )
+            port map (
+                clk_i      => clk,             -- : in  std_logic;   -- CPU clock
+                rst_i      => reset_sync,      -- : in  std_logic;   -- Reset
+                break_o    => zpu_i0_break,    -- : out std_logic;   -- Break executed
+                dbg_o      => zpu_i0_dbg,      -- : out zpu_dbgo_t;  -- Debug info
+                rs232_tx_o => rs232_dce_txd,   -- : out std_logic;   -- UART Tx
+                rs232_rx_i => rs232_dce_rxd,   -- : in  std_logic    -- UART Rx
+                gpio_in    => gpio_in,         -- : in  std_logic_vector(31 downto 0);
+                gpio_out   => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
+                gpio_dir   => zpu_i0_gpio_dir  -- : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
+                );
+    end generate zpu_i0_medium;
+
+
+    -- pragma translate_off 
+    stop_simulation <= zpu_i0_break;
+
+
+    trace_mod : trace
+        generic map (
+            addr_w    => addr_w_c,
+            word_size => word_size_c,
+            log_file  => "zpu_trace.log"
+            )
+        port map (
+            clk_i  => clk,
+            dbg_i  => zpu_i0_dbg,
+            stop_i => zpu_i0_break,
+            busy_i => '0'
+            );
+    -- pragma translate_on
+
+
+    -- assign GPIOs
+    -- no bidirectional pins (e.g. headers), so
+    -- gpio_dir is unused
+    gpio_in <= ((6) => rot_a,
+                (5) => rot_b,
+                (4) => rot_center,
+                --
+                (3) => btn_east,
+                (2) => btn_north,
+                (1) => btn_south,
+                (0) => btn_west,
+                others => '0');
+
+
+    -- switch on all LEDs in case of break
+    process
+    begin
+        wait until rising_edge(clk);
+        led <= zpu_i0_gpio_out(7 downto 0);
+        if zpu_i0_break = '1' then
+            led <= (others => '1');
+        end if;
+    end process;
+
+    
+
+end architecture rtl;
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top_tb.vhd b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top_tb.vhd
index c774e89..d62bed9 100644
--- a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top_tb.vhd
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top_tb.vhd
@@ -1,278 +1,281 @@
--- testbench for Digilent Spartan 3E Starter Board
---
--- includes "model" for clock generation
--- simulate press on Rotary Pushbutton Switch as reset
---
--- place models for external components (PHY, SDRAM) in this file
---
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-
-entity top_tb is
-end entity top_tb;
-
-architecture testbench of top_tb is
-
-    ---------------------------
-    -- constant declarations
-    constant clk_50mhz_period : time := 1 sec / 50_000_000;  -- 50 MHz
-
-
-    ---------------------------
-    -- signal declarations
-    signal simulation_run     : boolean                      := true;
-    signal tb_stop_simulation : std_logic;
-    --
-    -- Analog-to-Digital Converter (ADC)
-    signal tb_ad_conv         : std_logic;
-    -- Programmable Gain Amplifier (AMP)
-    signal tb_amp_cs          : std_logic;  -- active low chip select
-    signal tb_amp_dout        : std_logic                    := '1';
-    signal tb_amp_shdn        : std_logic;  -- active high shutdown, reset
-    -- Pushbuttons (BTN)
-    signal tb_btn_east        : std_logic                    := '0';
-    signal tb_btn_north       : std_logic                    := '0';
-    signal tb_btn_south       : std_logic                    := '0';
-    signal tb_btn_west        : std_logic                    := '0';
-    -- Clock inputs (CLK)
-    signal tb_clk_50mhz       : std_logic                    := '0';
-    signal tb_clk_aux         : std_logic                    := '0';
-    signal tb_clk_sma         : std_logic                    := '0';
-    -- Digital-to-Analog Converter (DAC)
-    signal tb_dac_clr         : std_logic;  -- async, active low reset input
-    signal tb_dac_cs          : std_logic;  -- active low chip select, conv start with rising edge
-    -- 1-Wire Secure EEPROM (DS)
-    signal tb_ds_wire         : std_logic;
-    -- Ethernet PHY (E)
-    signal tb_e_col           : std_logic                    := '0';  -- MII collision detect
-    signal tb_e_crs           : std_logic                    := '0';  -- carrier sense
-    signal tb_e_mdc           : std_logic;  -- management clock
-    signal tb_e_mdio          : std_logic;  -- management data io
-    signal tb_e_rx_clk        : std_logic                    := '0';  -- receive clock 25MHz@100BaseTx or 2.5MHz@10Base-T
-    signal tb_e_rx_dv         : std_logic                    := '0';  -- receive data valid
-    signal tb_e_rxd           : std_logic_vector(3 downto 0) := (others => '0');
-    signal tb_e_rx_er         : std_logic                    := '0';
-    signal tb_e_tx_clk        : std_logic                    := '0';  -- transmit clock 25MHz@100BaseTx or 2.5MHz@10Base-T
-    signal tb_e_tx_en         : std_logic;  -- transmit enable
-    signal tb_e_txd           : std_logic_vector(3 downto 0);
-    signal tb_e_tx_er         : std_logic;
-    -- FPGA Configuration Mode, INIT_B Pins (FPGA)
-    signal tb_fpga_m0         : std_logic;
-    signal tb_fpga_m1         : std_logic;
-    signal tb_fpga_m2         : std_logic;
-    signal tb_fpga_init_b     : std_logic;
-    signal tb_fpga_rdwr_b     : std_logic                    := '0';
-    signal tb_fpga_hswap      : std_logic                    := '0';
-    -- FX2 Connector (FX2)
-    signal tb_fx2_clkin       : std_logic;
-    signal tb_fx2_clkio       : std_logic;
-    signal tb_fx2_clkout      : std_logic;
-    signal tb_fx2_io          : std_logic_vector(40 downto 1);
-    -- Character LCD (LCD)
-    signal tb_lcd_e           : std_logic;
-    signal tb_lcd_rs          : std_logic;
-    signal tb_lcd_rw          : std_logic;
-    -- LCD data connections are shared with StrataFlash connections SF_D<11:8>
-    -- PS/2 Mouse/Keyboard Port (PS2)
-    signal tb_ps2_clk         : std_logic;
-    signal tb_ps2_data        : std_logic;
-    -- Rotary Pushbutton Switch (ROT)
-    signal tb_rot_a           : std_logic                    := '0';
-    signal tb_rot_b           : std_logic                    := '0';
-    signal tb_rot_center      : std_logic;  -- use as reset
-    -- RS-232 Serial Ports (RS232)
-    signal tb_rs232_dce_rxd   : std_logic                    := '1';
-    signal tb_rs232_dce_txd   : std_logic;
-    signal tb_rs232_dte_rxd   : std_logic                    := '1';
-    signal tb_rs232_dte_txd   : std_logic;
-    -- DDR SDRAM (SD) (I/O Bank 3, VCCO=2.5V)
-    signal tb_sd_a            : std_logic_vector(12 downto 0);  -- address inputs
-    signal tb_sd_dq           : std_logic_vector(15 downto 0);  -- data io
-    signal tb_sd_ba           : std_logic_vector(1 downto 0);  -- bank address inputs
-    signal tb_sd_ras          : std_logic;  -- command output
-    signal tb_sd_cas          : std_logic;  -- command output
-    signal tb_sd_we           : std_logic;  -- command output 
-    signal tb_sd_udm          : std_logic;  -- data mask
-    signal tb_sd_ldm          : std_logic;  -- data mask
-    signal tb_sd_udqs         : std_logic;  -- data strobe
-    signal tb_sd_ldqs         : std_logic;  -- data strobe
-    signal tb_sd_cs           : std_logic;  -- active low chip select
-    signal tb_sd_cke          : std_logic;  -- active high clock enable
-    signal tb_sd_ck_n         : std_logic;  -- differential clock
-    signal tb_sd_ck_p         : std_logic;  -- differential clock
-    -- Path to allow connection to top DCM connection
-    signal tb_sd_ck_fb        : std_logic;
-    -- Intel StrataFlash Parallel NOR Flash (SF)
-    signal tb_sf_a            : std_logic_vector(23 downto 0);  -- sf_a<24> = fx_io32 :-(
-    signal tb_sf_byte         : std_logic;
-    signal tb_sf_ce0          : std_logic;
-    signal tb_sf_d            : std_logic_vector(15 downto 1);
-    signal tb_sf_oe           : std_logic;
-    signal tb_sf_sts          : std_logic                    := '0';
-    signal tb_sf_we           : std_logic;
-    -- STMicro SPI serial Flash (SPI)
-    signal tb_spi_mosi        : std_logic;  -- master out slave in
-    signal tb_spi_miso        : std_logic                    := '0';  -- master in  slave out
-    signal tb_spi_sck         : std_logic;  -- clock
-    signal tb_spi_ss_b        : std_logic;  -- active low slave select
-    signal tb_spi_alt_cs_jp11 : std_logic;
-    -- Slide Switches (SW)
-    signal tb_sw              : std_logic_vector(3 downto 0) := (others => '0');
-    -- VGA Port (VGA)
-    signal tb_vga_blue        : std_logic;
-    signal tb_vga_green       : std_logic;
-    signal tb_vga_hsync       : std_logic;
-    signal tb_vga_red         : std_logic;
-    signal tb_vga_vsync       : std_logic;
-    -- Xilinx CPLD (XC)
-    signal tb_xc_cmd          : std_logic_vector(1 downto 0);
-    signal tb_xc_cpld_en      : std_logic;
-    signal tb_xc_d            : std_logic_vector(2 downto 0);
-    signal tb_xc_trig         : std_logic                    := '0';
-    signal tb_xc_gck0         : std_logic;
-    signal tb_gclk10          : std_logic;
-
-
-begin
-
-
-    -- generate clock
-    tb_clk_50mhz <= not tb_clk_50mhz after clk_50mhz_period / 2 when simulation_run;
-
-    -- generate reset
-    tb_rot_center <= '1', '0' after 6.66 * clk_50mhz_period;
-
-
-    -- clock feedback for SD-RAM (on board)
-    tb_sd_ck_fb <= tb_sd_ck_p;
-
-
-    -- dut
-    top_i0 : entity work.top
-        port map (
-            stop_simulation => tb_stop_simulation,  -- : out   std_logic;
-            -- Analog-to-Digital Converter (ADC)
-            ad_conv         => tb_ad_conv,          -- : out   std_logic;
-            -- Programmable Gain Amplifier (AMP)
-            amp_cs          => tb_amp_cs,           -- : out   std_logic;
-            amp_dout        => tb_amp_dout,         -- : in    std_logic;
-            amp_shdn        => tb_amp_shdn,         -- : out   std_logic;
-            -- Pushbuttons (BTN)
-            btn_east        => tb_btn_east,         -- : in    std_logic;
-            btn_north       => tb_btn_north,        -- : in    std_logic;
-            btn_south       => tb_btn_south,        -- : in    std_logic;
-            btn_west        => tb_btn_west,         -- : in    std_logic;
-            -- Clock inputs (CLK)
-            clk_50mhz       => tb_clk_50mhz,        -- : in    std_logic;
-            clk_aux         => tb_clk_aux,          -- : in    std_logic;
-            clk_sma         => tb_clk_sma,          -- : in    std_logic;
-            -- Digital-to-Analog Converter (DAC)
-            dac_clr         => tb_dac_clr,          -- : out   std_logic;
-            dac_cs          => tb_dac_cs,           -- : out   std_logic;
-            -- 1-Wire Secure EEPROM (DS)
-            ds_wire         => tb_ds_wire,          -- : inout std_logic;
-            -- Ethernet PHY (E)
-            e_col           => tb_e_col,            -- : in    std_logic;
-            e_crs           => tb_e_crs,            -- : in    std_logic;
-            e_mdc           => tb_e_mdc,            -- : out   std_logic;
-            e_mdio          => tb_e_mdio,           -- : inout std_logic;
-            e_rx_clk        => tb_e_rx_clk,         -- : in    std_logic;
-            e_rx_dv         => tb_e_rx_dv,          -- : in    std_logic;
-            e_rxd           => tb_e_rxd,            -- : in    std_logic_vector(3 downto 0);
-            e_rx_er         => tb_e_rx_er,          -- : in    std_logic;
-            e_tx_clk        => tb_e_tx_clk,         -- : in    std_logic;
-            e_tx_en         => tb_e_tx_en,          -- : out   std_logic;
-            e_txd           => tb_e_txd,            -- : out   std_logic_vector(3 downto 0);
-            e_tx_er         => tb_e_tx_er,          -- : out   std_logic;
-            -- FPGA Configuration Mode, INIT_B Pins (FPGA)
-            fpga_m0         => tb_fpga_m0,          -- : inout std_logic;
-            fpga_m1         => tb_fpga_m1,          -- : inout std_logic;
-            fpga_m2         => tb_fpga_m2,          -- : inout std_logic;
-            fpga_init_b     => tb_fpga_init_b,      -- : inout std_logic;
-            fpga_rdwr_b     => tb_fpga_rdwr_b,      -- : in    std_logic;
-            fpga_hswap      => tb_fpga_hswap,       -- : in    std_logic;
-            -- FX2 Connector (FX2)
-            fx2_clkin       => tb_fx2_clkin,        -- : inout std_logic;
-            fx2_clkio       => tb_fx2_clkio,        -- : inout std_logic;
-            fx2_clkout      => tb_fx2_clkout,       -- : inout std_logic;
-            fx2_io          => tb_fx2_io,           -- : inout std_logic_vector(40 downto 1);
-            -- Character LCD (LCD)
-            lcd_e           => tb_lcd_e,            -- : out   std_logic;
-            lcd_rs          => tb_lcd_rs,           -- : out   std_logic;
-            lcd_rw          => tb_lcd_rw,           -- : out   std_logic;
-            -- LCD data connections are shared with StrataFlash connections SF_D<11:8>
-            -- PS/2 Mouse/Keyboard Port (PS2)
-            ps2_clk         => tb_ps2_clk,          -- : inout std_logic;
-            ps2_data        => tb_ps2_data,         -- : inout std_logic;
-            -- Rotary Pushbutton Switch (ROT)
-            rot_a           => tb_rot_a,            -- : in    std_logic;
-            rot_b           => tb_rot_b,            -- : in    std_logic;
-            rot_center      => tb_rot_center,       -- : in    std_logic;
-            -- RS-232 Serial Ports (RS232)
-            rs232_dce_rxd   => tb_rs232_dce_rxd,    -- : in    std_logic;
-            rs232_dce_txd   => tb_rs232_dce_txd,    -- : out   std_logic;
-            rs232_dte_rxd   => tb_rs232_dte_rxd,    -- : in    std_logic;
-            rs232_dte_txd   => tb_rs232_dte_txd,    -- : out   std_logic;
-            -- DDR SDRAM (SD) (I/O Bank 3, VCCO=2.5V)
-            sd_a            => tb_sd_a,             -- : out   std_logic_vector(12 downto 0);
-            sd_dq           => tb_sd_dq,            -- : inout std_logic_vector(15 downto 0);
-            sd_ba           => tb_sd_ba,            -- : out   std_logic_vector(1 downto 0);
-            sd_ras          => tb_sd_ras,           -- : out   std_logic;
-            sd_cas          => tb_sd_cas,           -- : out   std_logic;
-            sd_we           => tb_sd_we,            -- : out   std_logic;
-            sd_udm          => tb_sd_udm,           -- : out   std_logic;
-            sd_ldm          => tb_sd_ldm,           -- : out   std_logic;
-            sd_udqs         => tb_sd_udqs,          -- : inout std_logic;
-            sd_ldqs         => tb_sd_ldqs,          -- : inout std_logic;
-            sd_cs           => tb_sd_cs,            -- : out   std_logic;
-            sd_cke          => tb_sd_cke,           -- : out   std_logic;
-            sd_ck_n         => tb_sd_ck_n,          -- : out   std_logic;
-            sd_ck_p         => tb_sd_ck_p,          -- : out   std_logic;
-            -- Path to allow connection to top DCM connection
-            sd_ck_fb        => tb_sd_ck_fb,         -- : in    std_logic;
-            -- Intel StrataFlash Parallel NOR Flash (SF)
-            sf_a            => tb_sf_a,             -- : out   std_logic_vector(23 downto 0);
-            sf_byte         => tb_sf_byte,          -- : out   std_logic;
-            sf_ce0          => tb_sf_ce0,           -- : out   std_logic;
-            sf_d            => tb_sf_d,             -- : inout std_logic_vector(15 downto 1);
-            sf_oe           => tb_sf_oe,            -- : out   std_logic;
-            sf_sts          => tb_sf_sts,           -- : in    std_logic;
-            sf_we           => tb_sf_we,            -- : out   std_logic;
-            -- STMicro SPI serial Flash (SPI)
-            spi_mosi        => tb_spi_mosi,         -- : out   std_logic;
-            spi_miso        => tb_spi_miso,         -- : in    std_logic;
-            spi_sck         => tb_spi_sck,          -- : out   std_logic;
-            spi_ss_b        => tb_spi_ss_b,         -- : out   std_logic;
-            spi_alt_cs_jp11 => tb_spi_alt_cs_jp11,  -- : out   std_logic;
-            -- Slide Switches (SW)
-            sw              => tb_sw,               -- : in    std_logic_vector(3 downto 0);
-            -- VGA Port (VGA)
-            vga_blue        => tb_vga_blue,         -- : out   std_logic;
-            vga_green       => tb_vga_green,        -- : out   std_logic;
-            vga_hsync       => tb_vga_hsync,        -- : out   std_logic;
-            vga_red         => tb_vga_red,          -- : out   std_logic;
-            vga_vsync       => tb_vga_vsync,        -- : out   std_logic;
-            -- Xilinx CPLD (XC)
-            xc_cmd          => tb_xc_cmd,           -- : out   std_logic_vector(1 downto 0);
-            xc_cpld_en      => tb_xc_cpld_en,       -- : out   std_logic;
-            xc_d            => tb_xc_d,             -- : inout std_logic_vector(2 downto 0);
-            xc_trig         => tb_xc_trig,          -- : in    std_logic;
-            xc_gck0         => tb_xc_gck0,          -- : inout std_logic;
-            gclk10          => tb_gclk10            -- : inout std_logic
-            );
-
-
-    -- check for simulation stopping
-    process (tb_stop_simulation)
-    begin
-        if tb_stop_simulation = '1' then
-            report "Simulation end." severity note;
-            simulation_run <= false;
-        end if;
-    end process;
-
-
-end architecture testbench;
+-- testbench for
+-- Digilent Spartan 3E Starter Board
+--
+-- includes "model" for clock generation
+-- simulate press on Rotary Pushbutton Switch as reset
+--
+-- place models for external components (PHY, SDRAM) in this file
+--
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity top_tb is
+end entity top_tb;
+
+architecture testbench of top_tb is
+
+    ---------------------------
+    -- constant declarations
+    constant clk_50mhz_period : time := 1 sec / 50_000_000;  -- 50 MHz
+
+
+    ---------------------------
+    -- signal declarations
+    signal simulation_run     : boolean                      := true;
+    signal tb_stop_simulation : std_logic;
+    --
+    -- Analog-to-Digital Converter (ADC)
+    signal tb_ad_conv         : std_logic;
+    -- Programmable Gain Amplifier (AMP)
+    signal tb_amp_cs          : std_logic;  -- active low chip select
+    signal tb_amp_dout        : std_logic                    := '1';
+    signal tb_amp_shdn        : std_logic;  -- active high shutdown, reset
+    -- Pushbuttons (BTN)
+    signal tb_btn_east        : std_logic                    := '0';
+    signal tb_btn_north       : std_logic                    := '0';
+    signal tb_btn_south       : std_logic                    := '0';
+    signal tb_btn_west        : std_logic                    := '0';
+    -- Clock inputs (CLK)
+    signal tb_clk_50mhz       : std_logic                    := '0';
+    signal tb_clk_aux         : std_logic                    := '0';
+    signal tb_clk_sma         : std_logic                    := '0';
+    -- Digital-to-Analog Converter (DAC)
+    signal tb_dac_clr         : std_logic;  -- async, active low reset input
+    signal tb_dac_cs          : std_logic;  -- active low chip select, conv start with rising edge
+    -- 1-Wire Secure EEPROM (DS)
+    signal tb_ds_wire         : std_logic;
+    -- Ethernet PHY (E)
+    signal tb_e_col           : std_logic                    := '0';  -- MII collision detect
+    signal tb_e_crs           : std_logic                    := '0';  -- carrier sense
+    signal tb_e_mdc           : std_logic;  -- management clock
+    signal tb_e_mdio          : std_logic;  -- management data io
+    signal tb_e_rx_clk        : std_logic                    := '0';  -- receive clock 25MHz@100BaseTx or 2.5MHz@10Base-T
+    signal tb_e_rx_dv         : std_logic                    := '0';  -- receive data valid
+    signal tb_e_rxd           : std_logic_vector(3 downto 0) := (others => '0');
+    signal tb_e_rx_er         : std_logic                    := '0';
+    signal tb_e_tx_clk        : std_logic                    := '0';  -- transmit clock 25MHz@100BaseTx or 2.5MHz@10Base-T
+    signal tb_e_tx_en         : std_logic;  -- transmit enable
+    signal tb_e_txd           : std_logic_vector(3 downto 0);
+    signal tb_e_tx_er         : std_logic;
+    -- FPGA Configuration Mode, INIT_B Pins (FPGA)
+    signal tb_fpga_m0         : std_logic;
+    signal tb_fpga_m1         : std_logic;
+    signal tb_fpga_m2         : std_logic;
+    signal tb_fpga_init_b     : std_logic;
+    signal tb_fpga_rdwr_b     : std_logic                    := '0';
+    signal tb_fpga_hswap      : std_logic                    := '0';
+    -- FX2 Connector (FX2)
+    signal tb_fx2_clkin       : std_logic;
+    signal tb_fx2_clkio       : std_logic;
+    signal tb_fx2_clkout      : std_logic;
+    signal tb_fx2_io          : std_logic_vector(40 downto 1);
+    -- Character LCD (LCD)
+    signal tb_lcd_e           : std_logic;
+    signal tb_lcd_rs          : std_logic;
+    signal tb_lcd_rw          : std_logic;
+    -- LCD data connections are shared with StrataFlash connections SF_D<11:8>
+    -- PS/2 Mouse/Keyboard Port (PS2)
+    signal tb_ps2_clk         : std_logic;
+    signal tb_ps2_data        : std_logic;
+    -- Rotary Pushbutton Switch (ROT)
+    signal tb_rot_a           : std_logic                    := '0';
+    signal tb_rot_b           : std_logic                    := '0';
+    signal tb_rot_center      : std_logic;  -- use as reset
+    -- RS-232 Serial Ports (RS232)
+    signal tb_rs232_dce_rxd   : std_logic                    := '1';
+    signal tb_rs232_dce_txd   : std_logic;
+    signal tb_rs232_dte_rxd   : std_logic                    := '1';
+    signal tb_rs232_dte_txd   : std_logic;
+    -- DDR SDRAM (SD) (I/O Bank 3, VCCO=2.5V)
+    signal tb_sd_a            : std_logic_vector(12 downto 0);  -- address inputs
+    signal tb_sd_dq           : std_logic_vector(15 downto 0);  -- data io
+    signal tb_sd_ba           : std_logic_vector(1 downto 0);  -- bank address inputs
+    signal tb_sd_ras          : std_logic;  -- command output
+    signal tb_sd_cas          : std_logic;  -- command output
+    signal tb_sd_we           : std_logic;  -- command output 
+    signal tb_sd_udm          : std_logic;  -- data mask
+    signal tb_sd_ldm          : std_logic;  -- data mask
+    signal tb_sd_udqs         : std_logic;  -- data strobe
+    signal tb_sd_ldqs         : std_logic;  -- data strobe
+    signal tb_sd_cs           : std_logic;  -- active low chip select
+    signal tb_sd_cke          : std_logic;  -- active high clock enable
+    signal tb_sd_ck_n         : std_logic;  -- differential clock
+    signal tb_sd_ck_p         : std_logic;  -- differential clock
+    -- Path to allow connection to top DCM connection
+    signal tb_sd_ck_fb        : std_logic;
+    -- Intel StrataFlash Parallel NOR Flash (SF)
+    signal tb_sf_a            : std_logic_vector(23 downto 0);  -- sf_a<24> = fx_io32 :-(
+    signal tb_sf_byte         : std_logic;
+    signal tb_sf_ce0          : std_logic;
+    signal tb_sf_d            : std_logic_vector(15 downto 1);
+    signal tb_sf_oe           : std_logic;
+    signal tb_sf_sts          : std_logic                    := '0';
+    signal tb_sf_we           : std_logic;
+    -- STMicro SPI serial Flash (SPI)
+    signal tb_spi_mosi        : std_logic;  -- master out slave in
+    signal tb_spi_miso        : std_logic                    := '0';  -- master in  slave out
+    signal tb_spi_sck         : std_logic;  -- clock
+    signal tb_spi_ss_b        : std_logic;  -- active low slave select
+    signal tb_spi_alt_cs_jp11 : std_logic;
+    -- Slide Switches (SW)
+    signal tb_sw              : std_logic_vector(3 downto 0) := (others => '0');
+    -- VGA Port (VGA)
+    signal tb_vga_blue        : std_logic;
+    signal tb_vga_green       : std_logic;
+    signal tb_vga_hsync       : std_logic;
+    signal tb_vga_red         : std_logic;
+    signal tb_vga_vsync       : std_logic;
+    -- Xilinx CPLD (XC)
+    signal tb_xc_cmd          : std_logic_vector(1 downto 0);
+    signal tb_xc_cpld_en      : std_logic;
+    signal tb_xc_d            : std_logic_vector(2 downto 0);
+    signal tb_xc_trig         : std_logic                    := '0';
+    signal tb_xc_gck0         : std_logic;
+    signal tb_gclk10          : std_logic;
+
+
+begin
+
+
+    -- generate clock
+    tb_clk_50mhz <= not tb_clk_50mhz after clk_50mhz_period / 2 when simulation_run;
+
+    -- generate reset
+    tb_rot_center <= '1', '0' after 6.66 * clk_50mhz_period;
+
+
+    -- clock feedback for SD-RAM (on board)
+    tb_sd_ck_fb <= tb_sd_ck_p;
+
+    -- simulate keypress
+    tb_btn_north <= '0', '1' after 55 us, '0' after 56 us;
+
+    -- dut
+    top_i0 : entity work.top
+        port map (
+            stop_simulation => tb_stop_simulation,  -- : out   std_logic;
+            -- Analog-to-Digital Converter (ADC)
+            ad_conv         => tb_ad_conv,          -- : out   std_logic;
+            -- Programmable Gain Amplifier (AMP)
+            amp_cs          => tb_amp_cs,           -- : out   std_logic;
+            amp_dout        => tb_amp_dout,         -- : in    std_logic;
+            amp_shdn        => tb_amp_shdn,         -- : out   std_logic;
+            -- Pushbuttons (BTN)
+            btn_east        => tb_btn_east,         -- : in    std_logic;
+            btn_north       => tb_btn_north,        -- : in    std_logic;
+            btn_south       => tb_btn_south,        -- : in    std_logic;
+            btn_west        => tb_btn_west,         -- : in    std_logic;
+            -- Clock inputs (CLK)
+            clk_50mhz       => tb_clk_50mhz,        -- : in    std_logic;
+            clk_aux         => tb_clk_aux,          -- : in    std_logic;
+            clk_sma         => tb_clk_sma,          -- : in    std_logic;
+            -- Digital-to-Analog Converter (DAC)
+            dac_clr         => tb_dac_clr,          -- : out   std_logic;
+            dac_cs          => tb_dac_cs,           -- : out   std_logic;
+            -- 1-Wire Secure EEPROM (DS)
+            ds_wire         => tb_ds_wire,          -- : inout std_logic;
+            -- Ethernet PHY (E)
+            e_col           => tb_e_col,            -- : in    std_logic;
+            e_crs           => tb_e_crs,            -- : in    std_logic;
+            e_mdc           => tb_e_mdc,            -- : out   std_logic;
+            e_mdio          => tb_e_mdio,           -- : inout std_logic;
+            e_rx_clk        => tb_e_rx_clk,         -- : in    std_logic;
+            e_rx_dv         => tb_e_rx_dv,          -- : in    std_logic;
+            e_rxd           => tb_e_rxd,            -- : in    std_logic_vector(3 downto 0);
+            e_rx_er         => tb_e_rx_er,          -- : in    std_logic;
+            e_tx_clk        => tb_e_tx_clk,         -- : in    std_logic;
+            e_tx_en         => tb_e_tx_en,          -- : out   std_logic;
+            e_txd           => tb_e_txd,            -- : out   std_logic_vector(3 downto 0);
+            e_tx_er         => tb_e_tx_er,          -- : out   std_logic;
+            -- FPGA Configuration Mode, INIT_B Pins (FPGA)
+            fpga_m0         => tb_fpga_m0,          -- : inout std_logic;
+            fpga_m1         => tb_fpga_m1,          -- : inout std_logic;
+            fpga_m2         => tb_fpga_m2,          -- : inout std_logic;
+            fpga_init_b     => tb_fpga_init_b,      -- : inout std_logic;
+            fpga_rdwr_b     => tb_fpga_rdwr_b,      -- : in    std_logic;
+            fpga_hswap      => tb_fpga_hswap,       -- : in    std_logic;
+            -- FX2 Connector (FX2)
+            fx2_clkin       => tb_fx2_clkin,        -- : inout std_logic;
+            fx2_clkio       => tb_fx2_clkio,        -- : inout std_logic;
+            fx2_clkout      => tb_fx2_clkout,       -- : inout std_logic;
+            fx2_io          => tb_fx2_io,           -- : inout std_logic_vector(40 downto 1);
+            -- Character LCD (LCD)
+            lcd_e           => tb_lcd_e,            -- : out   std_logic;
+            lcd_rs          => tb_lcd_rs,           -- : out   std_logic;
+            lcd_rw          => tb_lcd_rw,           -- : out   std_logic;
+            -- LCD data connections are shared with StrataFlash connections SF_D<11:8>
+            -- PS/2 Mouse/Keyboard Port (PS2)
+            ps2_clk         => tb_ps2_clk,          -- : inout std_logic;
+            ps2_data        => tb_ps2_data,         -- : inout std_logic;
+            -- Rotary Pushbutton Switch (ROT)
+            rot_a           => tb_rot_a,            -- : in    std_logic;
+            rot_b           => tb_rot_b,            -- : in    std_logic;
+            rot_center      => tb_rot_center,       -- : in    std_logic;
+            -- RS-232 Serial Ports (RS232)
+            rs232_dce_rxd   => tb_rs232_dce_rxd,    -- : in    std_logic;
+            rs232_dce_txd   => tb_rs232_dce_txd,    -- : out   std_logic;
+            rs232_dte_rxd   => tb_rs232_dte_rxd,    -- : in    std_logic;
+            rs232_dte_txd   => tb_rs232_dte_txd,    -- : out   std_logic;
+            -- DDR SDRAM (SD) (I/O Bank 3, VCCO=2.5V)
+            sd_a            => tb_sd_a,             -- : out   std_logic_vector(12 downto 0);
+            sd_dq           => tb_sd_dq,            -- : inout std_logic_vector(15 downto 0);
+            sd_ba           => tb_sd_ba,            -- : out   std_logic_vector(1 downto 0);
+            sd_ras          => tb_sd_ras,           -- : out   std_logic;
+            sd_cas          => tb_sd_cas,           -- : out   std_logic;
+            sd_we           => tb_sd_we,            -- : out   std_logic;
+            sd_udm          => tb_sd_udm,           -- : out   std_logic;
+            sd_ldm          => tb_sd_ldm,           -- : out   std_logic;
+            sd_udqs         => tb_sd_udqs,          -- : inout std_logic;
+            sd_ldqs         => tb_sd_ldqs,          -- : inout std_logic;
+            sd_cs           => tb_sd_cs,            -- : out   std_logic;
+            sd_cke          => tb_sd_cke,           -- : out   std_logic;
+            sd_ck_n         => tb_sd_ck_n,          -- : out   std_logic;
+            sd_ck_p         => tb_sd_ck_p,          -- : out   std_logic;
+            -- Path to allow connection to top DCM connection
+            sd_ck_fb        => tb_sd_ck_fb,         -- : in    std_logic;
+            -- Intel StrataFlash Parallel NOR Flash (SF)
+            sf_a            => tb_sf_a,             -- : out   std_logic_vector(23 downto 0);
+            sf_byte         => tb_sf_byte,          -- : out   std_logic;
+            sf_ce0          => tb_sf_ce0,           -- : out   std_logic;
+            sf_d            => tb_sf_d,             -- : inout std_logic_vector(15 downto 1);
+            sf_oe           => tb_sf_oe,            -- : out   std_logic;
+            sf_sts          => tb_sf_sts,           -- : in    std_logic;
+            sf_we           => tb_sf_we,            -- : out   std_logic;
+            -- STMicro SPI serial Flash (SPI)
+            spi_mosi        => tb_spi_mosi,         -- : out   std_logic;
+            spi_miso        => tb_spi_miso,         -- : in    std_logic;
+            spi_sck         => tb_spi_sck,          -- : out   std_logic;
+            spi_ss_b        => tb_spi_ss_b,         -- : out   std_logic;
+            spi_alt_cs_jp11 => tb_spi_alt_cs_jp11,  -- : out   std_logic;
+            -- Slide Switches (SW)
+            sw              => tb_sw,               -- : in    std_logic_vector(3 downto 0);
+            -- VGA Port (VGA)
+            vga_blue        => tb_vga_blue,         -- : out   std_logic;
+            vga_green       => tb_vga_green,        -- : out   std_logic;
+            vga_hsync       => tb_vga_hsync,        -- : out   std_logic;
+            vga_red         => tb_vga_red,          -- : out   std_logic;
+            vga_vsync       => tb_vga_vsync,        -- : out   std_logic;
+            -- Xilinx CPLD (XC)
+            xc_cmd          => tb_xc_cmd,           -- : out   std_logic_vector(1 downto 0);
+            xc_cpld_en      => tb_xc_cpld_en,       -- : out   std_logic;
+            xc_d            => tb_xc_d,             -- : inout std_logic_vector(2 downto 0);
+            xc_trig         => tb_xc_trig,          -- : in    std_logic;
+            xc_gck0         => tb_xc_gck0,          -- : inout std_logic;
+            gclk10          => tb_gclk10            -- : inout std_logic
+            );
+
+
+    -- check for simulation stopping
+    process (tb_stop_simulation)
+    begin
+        if tb_stop_simulation = '1' then
+            report "Simulation end." severity note;
+            simulation_run <= false;
+        end if;
+    end process;
+
+
+end architecture testbench;
diff --git a/zpu/hdl/zealot/fpga/dmips_med1.vhdl b/zpu/hdl/zealot/fpga/dmips_med1.vhdl
index 9920c2c..b95016c 100644
--- a/zpu/hdl/zealot/fpga/dmips_med1.vhdl
+++ b/zpu/hdl/zealot/fpga/dmips_med1.vhdl
@@ -100,7 +100,11 @@ architecture FPGA of DMIPS_Med1 is
          break_o    : out std_logic;  -- Break executed
          dbg_o      : out zpu_dbgo_t; -- Debug info
          rs232_tx_o : out std_logic;  -- UART Tx
-         rs232_rx_i : in  std_logic); -- UART Rx
+         rs232_rx_i : in  std_logic;  -- UART Rx
+         gpio_in    : in  std_logic_vector(31 downto 0);
+         gpio_out   : out std_logic_vector(31 downto 0);
+         gpio_dir   : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
+         );
    end component ZPU_Med1;
 begin
    zpu : ZPU_Med1
@@ -110,6 +114,6 @@ begin
          BRAM_W => BRAM_W)
       port map(
          clk_i => clk_i, rst_i => rst_i, rs232_tx_o => rs232_tx_o,
-         rs232_rx_i => rs232_rx_i, dbg_o => open);
+         rs232_rx_i => rs232_rx_i, dbg_o => open, gpio_in => (others => '0'));
 end architecture FPGA; -- Entity: DMIPS_Med1
 
diff --git a/zpu/hdl/zealot/fpga/dmips_small1.vhdl b/zpu/hdl/zealot/fpga/dmips_small1.vhdl
index 018ab2d..6edec00 100644
--- a/zpu/hdl/zealot/fpga/dmips_small1.vhdl
+++ b/zpu/hdl/zealot/fpga/dmips_small1.vhdl
@@ -101,7 +101,11 @@ architecture FPGA of DMIPS_Small1 is
          break_o    : out std_logic;  -- Break executed
          dbg_o      : out zpu_dbgo_t; -- Debug info
          rs232_tx_o : out std_logic;  -- UART Tx
-         rs232_rx_i : in  std_logic); -- UART Rx
+         rs232_rx_i : in  std_logic;  -- UART Rx
+         gpio_in    : in  std_logic_vector(31 downto 0);
+         gpio_out   : out std_logic_vector(31 downto 0);
+         gpio_dir   : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
+         );
    end component ZPU_Small1;
 begin
    zpu : ZPU_Small1
@@ -111,6 +115,6 @@ begin
          BRAM_W => BRAM_W)
       port map(
          clk_i => clk_i, rst_i => rst_i, rs232_tx_o => rs232_tx_o,
-         rs232_rx_i => rs232_rx_i, dbg_o => open);
+         rs232_rx_i => rs232_rx_i, dbg_o => open, gpio_in => (others => '0'));
 end architecture FPGA; -- Entity: DMIPS_Small1
 
diff --git a/zpu/hdl/zealot/fpga/hello_med1.vhdl b/zpu/hdl/zealot/fpga/hello_med1.vhdl
index 7356c72..5ffea1f 100644
--- a/zpu/hdl/zealot/fpga/hello_med1.vhdl
+++ b/zpu/hdl/zealot/fpga/hello_med1.vhdl
@@ -100,7 +100,11 @@ architecture FPGA of Hello_Med1 is
          break_o    : out std_logic;  -- Break executed
          dbg_o      : out zpu_dbgo_t; -- Debug info
          rs232_tx_o : out std_logic;  -- UART Tx
-         rs232_rx_i : in  std_logic); -- UART Rx
+         rs232_rx_i : in  std_logic;  -- UART Rx
+         gpio_in    : in  std_logic_vector(31 downto 0);
+         gpio_out   : out std_logic_vector(31 downto 0);
+         gpio_dir   : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
+         );
    end component ZPU_Med1;
 begin
    zpu : ZPU_Med1
@@ -110,6 +114,6 @@ begin
          BRAM_W => BRAM_W)
       port map(
          clk_i => clk_i, rst_i => rst_i, rs232_tx_o => rs232_tx_o,
-         rs232_rx_i => rs232_rx_i, dbg_o => open);
+         rs232_rx_i => rs232_rx_i, dbg_o => open, gpio_in => (others => '0'));
 end architecture FPGA; -- Entity: Hello_Med1
 
diff --git a/zpu/hdl/zealot/fpga/hello_small1.vhdl b/zpu/hdl/zealot/fpga/hello_small1.vhdl
index ccd87c5..a7e2c21 100644
--- a/zpu/hdl/zealot/fpga/hello_small1.vhdl
+++ b/zpu/hdl/zealot/fpga/hello_small1.vhdl
@@ -101,7 +101,11 @@ architecture FPGA of Hello_Small1 is
          break_o    : out std_logic;  -- Break executed
          dbg_o      : out zpu_dbgo_t; -- Debug info
          rs232_tx_o : out std_logic;  -- UART Tx
-         rs232_rx_i : in  std_logic); -- UART Rx
+         rs232_rx_i : in  std_logic;  -- UART Rx
+         gpio_in    : in  std_logic_vector(31 downto 0);
+         gpio_out   : out std_logic_vector(31 downto 0);
+         gpio_dir   : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
+         );
    end component ZPU_Small1;
 begin
    zpu : ZPU_Small1
@@ -111,6 +115,6 @@ begin
          BRAM_W => BRAM_W)
       port map(
          clk_i => clk_i, rst_i => rst_i, rs232_tx_o => rs232_tx_o,
-         rs232_rx_i => rs232_rx_i, dbg_o => open);
+         rs232_rx_i => rs232_rx_i, dbg_o => open, gpio_in => (others => '0'));
 end architecture FPGA; -- Entity: Hello_Small1
 
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation.sh b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation.sh
index febf588..d525737 100755
--- a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation.sh
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation.sh
@@ -28,6 +28,7 @@ vcom -work zpu ../../helpers/zpu_med1.vhdl
 vcom -work zpu ../../devices/txt_util.vhdl
 vcom -work zpu ../../devices/phi_io.vhdl
 vcom -work zpu ../../devices/timer.vhdl
+vcom -work zpu ../../devices/gpio.vhdl
 vcom -work zpu ../../devices/rx_unit.vhdl
 vcom -work zpu ../../devices/tx_unit.vhdl
 vcom -work zpu ../../devices/br_gen.vhdl
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/run.do b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/run.do
index acc1710..0d29e0a 100644
--- a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/run.do
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/run.do
@@ -1,2 +1,2 @@
-do wave.do
-run -all
+do wave.do
+run -all
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.prj b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.prj
index 81d56ef..965ae4c 100644
--- a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.prj
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.prj
@@ -1,18 +1,19 @@
-vhdl work ../top.vhd
-vhdl zpu ../../../zpu_pkg.vhdl
-vhdl zpu ../../../zpu_small.vhdl
-vhdl zpu ../../../zpu_medium.vhdl
-vhdl zpu ../../../roms/rom_pkg.vhdl
-#vhdl zpu ../../../roms/hello_dbram.vhdl
-#vhdl zpu ../../../roms/hello_bram.vhdl
-vhdl zpu ../../../roms/dmips_dbram.vhdl
-vhdl zpu ../../../roms/dmips_bram.vhdl
-vhdl zpu ../../../helpers/zpu_small1.vhdl
-vhdl zpu ../../../helpers/zpu_med1.vhdl
-vhdl zpu ../../../devices/txt_util.vhdl
-vhdl zpu ../../../devices/phi_io.vhdl
-vhdl zpu ../../../devices/timer.vhdl
-vhdl zpu ../../../devices/rx_unit.vhdl
-vhdl zpu ../../../devices/tx_unit.vhdl
-vhdl zpu ../../../devices/br_gen.vhdl
-vhdl zpu ../../../devices/trace.vhdl
+vhdl work ../top.vhd
+vhdl zpu ../../../zpu_pkg.vhdl
+vhdl zpu ../../../zpu_small.vhdl
+vhdl zpu ../../../zpu_medium.vhdl
+vhdl zpu ../../../roms/rom_pkg.vhdl
+#vhdl zpu ../../../roms/hello_dbram.vhdl
+#vhdl zpu ../../../roms/hello_bram.vhdl
+vhdl zpu ../../../roms/dmips_dbram.vhdl
+vhdl zpu ../../../roms/dmips_bram.vhdl
+vhdl zpu ../../../helpers/zpu_small1.vhdl
+vhdl zpu ../../../helpers/zpu_med1.vhdl
+vhdl zpu ../../../devices/txt_util.vhdl
+vhdl zpu ../../../devices/phi_io.vhdl
+vhdl zpu ../../../devices/timer.vhdl
+vhdl zpu ../../../devices/gpio.vhdl
+vhdl zpu ../../../devices/rx_unit.vhdl
+vhdl zpu ../../../devices/tx_unit.vhdl
+vhdl zpu ../../../devices/br_gen.vhdl
+vhdl zpu ../../../devices/trace.vhdl
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.ut b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.ut
index ea9319f..be56902 100644
--- a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.ut
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.ut
@@ -1,30 +1,30 @@
--w
--g DebugBitstream:No
--g Binary:no
--g CRC:Enable
--g Reset_on_err:No
--g ConfigRate:2
--g ProgPin:PullUp
--g TckPin:PullUp
--g TdiPin:PullUp
--g TdoPin:PullUp
--g TmsPin:PullUp
--g UnusedPin:PullDown
--g UserID:0xFFFFFFFF
--g ExtMasterCclk_en:No
--g SPI_buswidth:1
--g TIMER_CFG:0xFFFF
--g multipin_wakeup:No
--g StartUpClk:CClk
--g DONE_cycle:4
--g GTS_cycle:5
--g GWE_cycle:6
--g LCK_cycle:NoWait
--g Security:None
--g DonePipe:No
--g DriveDone:No
--g en_sw_gsr:No
--g drive_awake:No
--g sw_clk:Startupclk
--g sw_gwe_cycle:5
--g sw_gts_cycle:4
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g Reset_on_err:No
+-g ConfigRate:2
+-g ProgPin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g ExtMasterCclk_en:No
+-g SPI_buswidth:1
+-g TIMER_CFG:0xFFFF
+-g multipin_wakeup:No
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
+-g en_sw_gsr:No
+-g drive_awake:No
+-g sw_clk:Startupclk
+-g sw_gwe_cycle:5
+-g sw_gts_cycle:4
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.xst b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.xst
index 8952afe..ddddddd 100644
--- a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.xst
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.xst
@@ -1,53 +1,53 @@
-set -tmpdir "tmp"
-set -xsthdpdir "xst"
-run
--ifn ../synthesis_config/top.prj
--ifmt mixed
--ofn top
--ofmt NGC
--p xc6slx16-2-csg324
--top top
--opt_mode Speed
--opt_level 1
--power NO
--iuc NO
--keep_hierarchy No
--netlist_hierarchy As_Optimized
--rtlview Yes
--glob_opt AllClockNets
--read_cores YES
--write_timing_constraints NO
--cross_clock_analysis NO
--hierarchy_separator /
--bus_delimiter <>
--case Maintain
--slice_utilization_ratio 100
--bram_utilization_ratio 100
--dsp_utilization_ratio 100
--lc Auto
--reduce_control_sets Auto
--fsm_extract YES -fsm_encoding Auto
--safe_implementation No
--fsm_style LUT
--ram_extract Yes
--ram_style Auto
--rom_extract Yes
--shreg_extract YES
--rom_style Auto
--auto_bram_packing NO
--resource_sharing YES
--async_to_sync NO
--shreg_min_size 2
--use_dsp48 Auto
--iobuf YES
--max_fanout 100000
--bufg 16
--register_duplication YES
--register_balancing No
--optimize_primitives NO
--use_clock_enable Auto
--use_sync_set Auto
--use_sync_reset Auto
--iob Auto
--equivalent_register_removal YES
--slice_utilization_ratio_maxmargin 5
+set -tmpdir "tmp"
+set -xsthdpdir "xst"
+run
+-ifn ../synthesis_config/top.prj
+-ifmt mixed
+-ofn top
+-ofmt NGC
+-p xc6slx16-2-csg324
+-top top
+-opt_mode Speed
+-opt_level 1
+-power NO
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-dsp_utilization_ratio 100
+-lc Auto
+-reduce_control_sets Auto
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-shreg_extract YES
+-rom_style Auto
+-auto_bram_packing NO
+-resource_sharing YES
+-async_to_sync NO
+-shreg_min_size 2
+-use_dsp48 Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 16
+-register_duplication YES
+-register_balancing No
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/xilinx-sp601-xc6slx16.ucf b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/xilinx-sp601-xc6slx16.ucf
index c54705a..a0c60e7 100644
--- a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/xilinx-sp601-xc6slx16.ucf
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/xilinx-sp601-xc6slx16.ucf
@@ -1,303 +1,303 @@
-############################################################
-# SPARTAN-6 SP601 Board Constraints File
-#
-# Family:  Spartan6
-# Device:  XC6SLX16
-# Package: CSG324
-# Speed:   -2
-#
-#
-# Bank Voltage
-# Bank 0: 2.5 V
-# Bank 1: 2.5 V
-# Bank 2: 2.5 V
-# Bank 3: 1.8 V
-# VCCAUX: 2.5 V
-
-# following pins are connected to VCC1V8/2:
-# N3, M5, C1
-
-
-############################################################
-## clock/timing constraints
-############################################################
-
-TIMESPEC "TS_SYSCLK"         = PERIOD "SYSCLK" 200 MHz HIGH 50 %;
-TIMESPEC "TS_USER_SMA_CLOCK" = PERIOD "USER_SMA_CLOCK" 50 MHz HIGH 50 %;
-NET "USER_CLOCK"               PERIOD = 27 MHz HIGH 40%;
-
-
-############################################################
-## pin placement constraints
-############################################################
-
-NET "CPU_RESET"        LOC = "N4";
-
-## 128 MB DDR2 Component Memory
-NET "DDR2_A<12>"       LOC ="G6"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_A<11>"       LOC ="D3"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_A<10>"       LOC ="F4"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_A<9>"        LOC ="D1"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_A<8>"        LOC ="D2"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_A<7>"        LOC ="H6"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_A<6>"        LOC ="H3"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_A<5>"        LOC ="H4"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_A<4>"        LOC ="F3"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_A<3>"        LOC ="L7"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_A<2>"        LOC ="H5"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_A<1>"        LOC ="J6"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_A<0>"        LOC ="J7"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<15>"      LOC ="U1"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<14>"      LOC ="U2"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<13>"      LOC ="T1"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<12>"      LOC ="T2"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<11>"      LOC ="N1"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<10>"      LOC ="N2"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<9>"       LOC ="M1"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<8>"       LOC ="M3"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<7>"       LOC ="J1"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<6>"       LOC ="J3"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<5>"       LOC ="H1"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<4>"       LOC ="H2"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<3>"       LOC ="K1"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<2>"       LOC ="K2"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<1>"       LOC ="L1"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_DQ<0>"       LOC ="L2"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_WE_B"        LOC ="E3"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_UDQS_P"      LOC ="P2"; # | IOSTANDARD = DIFF_SSTL18_II;
-NET "DDR2_UDQS_N"      LOC ="P1"; # | IOSTANDARD = DIFF_SSTL18_II;
-NET "DDR2_UDM"         LOC ="K4"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_RAS_B"       LOC ="L5"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_ODT"         LOC ="K6"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_LDQS_P"      LOC ="L4"; # | IOSTANDARD = DIFF_SSTL18_II;
-NET "DDR2_LDQS_N"      LOC ="L3"; # | IOSTANDARD = DIFF_SSTL18_II;
-NET "DDR2_LDM"         LOC ="K3"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_CLK_P"       LOC ="G3"; # | IOSTANDARD = DIFF_SSTL18_II;
-NET "DDR2_CLK_N"       LOC ="G1"; # | IOSTANDARD = DIFF_SSTL18_II;
-NET "DDR2_CKE"         LOC ="H7"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_CAS_B"       LOC ="K5"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_BA<2>"       LOC ="E1"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_BA<1>"       LOC ="F1"; # | IOSTANDARD = SSTL18_II ;
-NET "DDR2_BA<0>"       LOC ="F2"; # | IOSTANDARD = SSTL18_II ;
-
-## Flash Memory
-NET "FLASH_A<0>"       LOC = "K18";
-NET "FLASH_A<1>"       LOC = "K17";
-NET "FLASH_A<2>"       LOC = "J18";
-NET "FLASH_A<3>"       LOC = "J16";
-NET "FLASH_A<4>"       LOC = "G18";
-NET "FLASH_A<5>"       LOC = "G16";
-NET "FLASH_A<6>"       LOC = "H16";
-NET "FLASH_A<7>"       LOC = "H15";
-NET "FLASH_A<8>"       LOC = "H14";
-NET "FLASH_A<9>"       LOC = "H13";
-NET "FLASH_A<10>"      LOC = "F18";
-NET "FLASH_A<11>"      LOC = "F17";
-NET "FLASH_A<12>"      LOC = "K13";
-NET "FLASH_A<13>"      LOC = "K12";
-NET "FLASH_A<14>"      LOC = "E18";
-NET "FLASH_A<15>"      LOC = "E16";
-NET "FLASH_A<16>"      LOC = "G13";
-NET "FLASH_A<17>"      LOC = "H12";
-NET "FLASH_A<18>"      LOC = "D18";
-NET "FLASH_A<19>"      LOC = "D17";
-NET "FLASH_A<20>"      LOC = "G14";
-NET "FLASH_A<21>"      LOC = "F14";
-NET "FLASH_A<22>"      LOC = "C18";
-NET "FLASH_A<23>"      LOC = "C17";
-NET "FLASH_A<24>"      LOC = "F16";
-#NET "FLASH_D<0>"       LOC = "R13" | SLEW = "SLOW" | DRIVE = 2;
-#NET "FLASH_D<1>"       LOC = "T14" | SLEW = "SLOW" | DRIVE = 2;
-#NET "FLASH_D<2>"       LOC = "V14" | SLEW = "SLOW" | DRIVE = 2;
-NET "FLASH_D<3>"       LOC = "U5"  | SLEW = "SLOW" | DRIVE = 2;
-NET "FLASH_D<4>"       LOC = "V5"  | SLEW = "SLOW" | DRIVE = 2;
-NET "FLASH_D<5>"       LOC = "R3"  | SLEW = "SLOW" | DRIVE = 2;
-NET "FLASH_D<6>"       LOC = "T3"  | SLEW = "SLOW" | DRIVE = 2;
-NET "FLASH_D<7>"       LOC = "R5"  | SLEW = "SLOW" | DRIVE = 2;
-NET "FLASH_OE_B"       LOC = "L18";
-NET "FLASH_WE_B"       LOC = "M16";
-NET "FLASH_CE_B"       LOC = "L17";
-
-# FMC-Connector, Bank 0,2 (M2C = Mezzanine to Carrier, C2M = Carrier to Mezzanine)
-NET "FMC_CLK0_M2C_N"            LOC = "A10";
-NET "FMC_CLK0_M2C_P"            LOC = "C10";
-NET "FMC_CLK1_M2C_N"            LOC = "V9" ;
-NET "FMC_CLK1_M2C_P"            LOC = "T9" ;
-NET "FMC_LA00_CC_N"             LOC = "C9" ;
-NET "FMC_LA00_CC_P"             LOC = "D9" ;
-NET "FMC_LA01_CC_N"             LOC = "C11";
-NET "FMC_LA01_CC_P"             LOC = "D11";
-NET "FMC_LA02_N"                LOC = "A15";
-NET "FMC_LA02_P"                LOC = "C15";
-NET "FMC_LA03_N"                LOC = "A13";
-NET "FMC_LA03_P"                LOC = "C13";
-NET "FMC_LA04_N"                LOC = "A16";
-NET "FMC_LA04_P"                LOC = "B16";
-NET "FMC_LA05_N"                LOC = "A14";
-NET "FMC_LA05_P"                LOC = "B14";
-NET "FMC_LA06_N"                LOC = "C12";
-NET "FMC_LA06_P"                LOC = "D12";
-NET "FMC_LA07_N"                LOC = "E8" ;
-NET "FMC_LA07_P"                LOC = "E7" ;
-NET "FMC_LA08_N"                LOC = "E11";
-NET "FMC_LA08_P"                LOC = "F11";
-NET "FMC_LA09_N"                LOC = "F10";
-NET "FMC_LA09_P"                LOC = "G11";
-NET "FMC_LA10_N"                LOC = "C8" ;
-NET "FMC_LA10_P"                LOC = "D8" ;
-NET "FMC_LA11_N"                LOC = "A12";
-NET "FMC_LA11_P"                LOC = "B12";
-NET "FMC_LA12_N"                LOC = "C6" ;
-NET "FMC_LA12_P"                LOC = "D6" ;
-NET "FMC_LA13_N"                LOC = "A11";
-NET "FMC_LA13_P"                LOC = "B11";
-NET "FMC_LA14_N"                LOC = "A2" ;
-NET "FMC_LA14_P"                LOC = "B2" ;
-NET "FMC_LA15_N"                LOC = "F9" ;
-NET "FMC_LA15_P"                LOC = "G9" ;
-NET "FMC_LA16_N"                LOC = "A7" ;
-NET "FMC_LA16_P"                LOC = "C7" ;
-NET "FMC_LA17_CC_N"             LOC = "T8" ;
-NET "FMC_LA17_CC_P"             LOC = "R8" ;
-NET "FMC_LA18_CC_N"             LOC = "T10";
-NET "FMC_LA18_CC_P"             LOC = "R10";
-NET "FMC_LA19_N"                LOC = "P7" ;
-NET "FMC_LA19_P"                LOC = "N6" ;
-NET "FMC_LA20_N"                LOC = "P8" ;
-NET "FMC_LA20_P"                LOC = "N7" ;
-NET "FMC_LA21_N"                LOC = "V4" ;
-NET "FMC_LA21_P"                LOC = "T4" ;
-NET "FMC_LA22_N"                LOC = "T7" ;
-NET "FMC_LA22_P"                LOC = "R7" ;
-NET "FMC_LA23_N"                LOC = "P6" ;
-NET "FMC_LA23_P"                LOC = "N5" ;
-NET "FMC_LA24_N"                LOC = "V8" ;
-NET "FMC_LA24_P"                LOC = "U8" ;
-NET "FMC_LA25_N"                LOC = "N11";
-NET "FMC_LA25_P"                LOC = "M11";
-NET "FMC_LA26_N"                LOC = "V7" ;
-NET "FMC_LA26_P"                LOC = "U7" ;
-NET "FMC_LA27_N"                LOC = "T11";
-NET "FMC_LA27_P"                LOC = "R11";
-NET "FMC_LA28_N"                LOC = "V11";
-NET "FMC_LA28_P"                LOC = "U11";
-NET "FMC_LA29_N"                LOC = "N8" ;
-NET "FMC_LA29_P"                LOC = "M8" ;
-NET "FMC_LA30_N"                LOC = "V12";
-NET "FMC_LA30_P"                LOC = "T12";
-NET "FMC_LA31_N"                LOC = "V6" ;
-NET "FMC_LA31_P"                LOC = "T6" ;
-NET "FMC_LA32_N"                LOC = "V15";
-NET "FMC_LA32_P"                LOC = "U15";
-NET "FMC_LA33_N"                LOC = "N9" ;
-NET "FMC_LA33_P"                LOC = "M10";
-NET "FMC_PRSNT_M2C_L"           LOC = "U13";
-NET "FMC_PWR_GOOD_FLASH_RST_B"  LOC = "B3";
-
-# special FPGA pins
-NET "FPGA_AWAKE"                LOC = "P15"| SLEW = SLOW | DRIVE = 2;
-NET "FPGA_CCLK"                 LOC = "R15";
-NET "FPGA_CMP_CLK"              LOC = "U16";
-NET "FPGA_CMP_MOSI"             LOC = "V16";
-NET "FPGA_D0_DIN_MISO_MISO1"    LOC = "R13" | DRIVE = 4; ## 8 on U17 (thru series R187 100 ohm), 33 on U10, 6 on J12
-NET "FPGA_D1_MISO2"             LOC = "T14" | DRIVE = 4; ## 9 on U17 (thru series R186 100 ohm), 35 on U10, 3 on J12
-NET "FPGA_D2_MISO3"             LOC = "V14" | DRIVE = 4; ## 1 on U17, 38 on U10, 2 on J12
-NET "FPGA_HSWAPEN"              LOC = "D4";
-NET "FPGA_INIT_B"               LOC = "U3" | SLEW = SLOW | DRIVE = 4;
-NET "FPGA_M0_CMP_MISO"          LOC = "T15";
-NET "FPGA_M1"                   LOC = "N12";
-NET "FPGA_MOSI_CSI_B_MISO0"     LOC = "T13" | DRIVE = 4;
-NET "FPGA_ONCHIP_TERM1"         LOC = "L6";
-NET "FPGA_ONCHIP_TERM2"         LOC = "C2";
-NET "FPGA_VTEMP"                LOC = "P3";
-
-## Pushbuttons, Bank 3, external Pulldown
-NET "GPIO_BUTTON<0>"            LOC = "P4" ;
-NET "GPIO_BUTTON<1>"            LOC = "F6" ;
-NET "GPIO_BUTTON<2>"            LOC = "E4" ;
-NET "GPIO_BUTTON<3>"            LOC = "F5" ;
-NET "GPIO_BUTTON*"              TIG;
-
-## 8 Pin GPIO Header J13, Bank 0,1,2
-NET "GPIO_HEADER_LS<0>"         LOC = "N17"| SLEW = SLOW | DRIVE = 4 ;
-NET "GPIO_HEADER_LS<1>"         LOC = "M18"| SLEW = SLOW | DRIVE = 4 ; 
-NET "GPIO_HEADER_LS<2>"         LOC = "A3" | SLEW = SLOW | DRIVE = 4 ;
-NET "GPIO_HEADER_LS<3>"         LOC = "L15"| SLEW = SLOW | DRIVE = 4 ;
-NET "GPIO_HEADER_LS<4>"         LOC = "F15"| SLEW = SLOW | DRIVE = 4 ;
-NET "GPIO_HEADER_LS<5>"         LOC = "B4" | SLEW = SLOW | DRIVE = 4 ;
-NET "GPIO_HEADER_LS<6>"         LOC = "F13"| SLEW = SLOW | DRIVE = 4 ;
-NET "GPIO_HEADER_LS<7>"         LOC = "P12"| SLEW = SLOW | DRIVE = 4 ;
-
-## 4 GPIO LEDs, Bank 0
-NET "GPIO_LED<0>"               LOC = "E13"| SLEW = SLOW | DRIVE = 4 ;
-NET "GPIO_LED<1>"               LOC = "C14"| SLEW = SLOW | DRIVE = 4 ;
-NET "GPIO_LED<2>"               LOC = "C4" | SLEW = SLOW | DRIVE = 4 ;
-NET "GPIO_LED<3>"               LOC = "A4" | SLEW = SLOW | DRIVE = 4 ;
-NET "GPIO_LED*"                 TIG;
-
-## GPIO Dip Switches, Bank 0,2, external Pulldown
-NET "GPIO_SWITCH<0>"            LOC = "D14";
-NET "GPIO_SWITCH<1>"            LOC = "E12";
-NET "GPIO_SWITCH<2>"            LOC = "F12";
-NET "GPIO_SWITCH<3>"            LOC = "V13";
-NET "GPIO_SWITCH*"              TIG;
-
-## IIC Bus
-NET "IIC_SCL_MAIN"              LOC = "P11";
-NET "IIC_SDA_MAIN"              LOC = "N10";
-
-## 10/100/1000 Tri-Speed Ethernet PHY
-NET "PHY_COL"                   LOC = "L14";
-NET "PHY_CRS"                   LOC = "M13";
-NET "PHY_INT"                   LOC = "J13";
-NET "PHY_MDC"                   LOC = "N14" | SLEW = SLOW | DRIVE = 4;
-NET "PHY_MDIO"                  LOC = "P16" | SLEW = SLOW | DRIVE = 4;
-NET "PHY_RESET"                 LOC = "L13";
-NET "PHY_RXCLK"                 LOC = "L16";
-NET "PHY_RXCTL_RXDV"            LOC = "N18";
-NET "PHY_RXD<0>"                LOC = "M14";
-NET "PHY_RXD<1>"                LOC = "U18";
-NET "PHY_RXD<2>"                LOC = "U17";
-NET "PHY_RXD<3>"                LOC = "T18";
-NET "PHY_RXD<4>"                LOC = "T17";
-NET "PHY_RXD<5>"                LOC = "N16";
-NET "PHY_RXD<6>"                LOC = "N15";
-NET "PHY_RXD<7>"                LOC = "P18";
-NET "PHY_RXER"                  LOC = "P17";
-NET "PHY_TXCLK"                 LOC = "B9" ;
-NET "PHY_TXCTL_TXEN"            LOC = "B8"  | SLEW = SLOW | DRIVE = 4;
-NET "PHY_TXC_GTXCLK"            LOC = "A9" ;
-NET "PHY_TXD<0>"                LOC = "F8"  | SLEW = SLOW | DRIVE = 4;
-NET "PHY_TXD<1>"                LOC = "G8"  | SLEW = SLOW | DRIVE = 4;
-NET "PHY_TXD<2>"                LOC = "A6"  | SLEW = SLOW | DRIVE = 4;
-NET "PHY_TXD<3>"                LOC = "B6"  | SLEW = SLOW | DRIVE = 4;
-NET "PHY_TXD<4>"                LOC = "E6"  | SLEW = SLOW | DRIVE = 4;
-NET "PHY_TXD<5>"                LOC = "F7"  | SLEW = SLOW | DRIVE = 4;
-NET "PHY_TXD<6>"                LOC = "A5"  | SLEW = SLOW | DRIVE = 4;
-NET "PHY_TXD<7>"                LOC = "C5"  | SLEW = SLOW | DRIVE = 4;
-NET "PHY_TXER"                  LOC = "A8"  | SLEW = SLOW | DRIVE = 4;
-
-## SPI x4 Flash
-NET "SPI_CS_B"                  LOC = "V3";
-
-## 200 MHz oscillator (differential)
-NET "SYSCLK_N"                  LOC = "K16"| IOSTANDARD = LVDS_33 | TNM_NET = "SYSCLK";
-NET "SYSCLK_P"                  LOC = "K15"| IOSTANDARD = LVDS_33 | TNM_NET = "SYSCLK";
-
-## USB-UART
-## this names are real net names
-NET "USB_1_CTS"                 LOC = "U10"| DRIVE = 4 | SLEW = SLOW;   # RTS output
-NET "USB_1_RTS"                 LOC = "T5" ;                            # CTS input
-NET "USB_1_RX"                  LOC = "L12"| DRIVE = 4 | SLEW = SLOW;   # TX data out
-NET "USB_1_TX"                  LOC = "K14";                            # RX data in
-
-## 27 MHz
-NET "USER_CLOCK"                LOC = "V10"| IOSTANDARD = LVCMOS33 ;
-##
-NET "USER_SMA_CLOCK_N"          LOC = "H18"| TNM_NET = "USER_SMA_CLOCK";
-NET "USER_SMA_CLOCK_P"          LOC = "H17"| TNM_NET = "USER_SMA_CLOCK";
-
-# pins used for voltage termination
-CONFIG PROHIBIT = C1;
-CONFIG PROHIBIT = M5;
-CONFIG PROHIBIT = N3;
+############################################################
+# SPARTAN-6 SP601 Board Constraints File
+#
+# Family:  Spartan6
+# Device:  XC6SLX16
+# Package: CSG324
+# Speed:   -2
+#
+#
+# Bank Voltage
+# Bank 0: 2.5 V
+# Bank 1: 2.5 V
+# Bank 2: 2.5 V
+# Bank 3: 1.8 V
+# VCCAUX: 2.5 V
+
+# following pins are connected to VCC1V8/2:
+# N3, M5, C1
+
+
+############################################################
+## clock/timing constraints
+############################################################
+
+TIMESPEC "TS_SYSCLK"         = PERIOD "SYSCLK" 200 MHz HIGH 50 %;
+TIMESPEC "TS_USER_SMA_CLOCK" = PERIOD "USER_SMA_CLOCK" 50 MHz HIGH 50 %;
+NET "USER_CLOCK"               PERIOD = 27 MHz HIGH 40%;
+
+
+############################################################
+## pin placement constraints
+############################################################
+
+NET "CPU_RESET"        LOC = "N4";
+
+## 128 MB DDR2 Component Memory
+NET "DDR2_A<12>"       LOC ="G6"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<11>"       LOC ="D3"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<10>"       LOC ="F4"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<9>"        LOC ="D1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<8>"        LOC ="D2"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<7>"        LOC ="H6"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<6>"        LOC ="H3"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<5>"        LOC ="H4"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<4>"        LOC ="F3"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<3>"        LOC ="L7"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<2>"        LOC ="H5"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<1>"        LOC ="J6"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<0>"        LOC ="J7"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<15>"      LOC ="U1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<14>"      LOC ="U2"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<13>"      LOC ="T1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<12>"      LOC ="T2"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<11>"      LOC ="N1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<10>"      LOC ="N2"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<9>"       LOC ="M1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<8>"       LOC ="M3"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<7>"       LOC ="J1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<6>"       LOC ="J3"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<5>"       LOC ="H1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<4>"       LOC ="H2"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<3>"       LOC ="K1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<2>"       LOC ="K2"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<1>"       LOC ="L1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<0>"       LOC ="L2"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_WE_B"        LOC ="E3"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_UDQS_P"      LOC ="P2"; # | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_UDQS_N"      LOC ="P1"; # | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_UDM"         LOC ="K4"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_RAS_B"       LOC ="L5"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_ODT"         LOC ="K6"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_LDQS_P"      LOC ="L4"; # | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_LDQS_N"      LOC ="L3"; # | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_LDM"         LOC ="K3"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_CLK_P"       LOC ="G3"; # | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_CLK_N"       LOC ="G1"; # | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_CKE"         LOC ="H7"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_CAS_B"       LOC ="K5"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_BA<2>"       LOC ="E1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_BA<1>"       LOC ="F1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_BA<0>"       LOC ="F2"; # | IOSTANDARD = SSTL18_II ;
+
+## Flash Memory
+NET "FLASH_A<0>"       LOC = "K18";
+NET "FLASH_A<1>"       LOC = "K17";
+NET "FLASH_A<2>"       LOC = "J18";
+NET "FLASH_A<3>"       LOC = "J16";
+NET "FLASH_A<4>"       LOC = "G18";
+NET "FLASH_A<5>"       LOC = "G16";
+NET "FLASH_A<6>"       LOC = "H16";
+NET "FLASH_A<7>"       LOC = "H15";
+NET "FLASH_A<8>"       LOC = "H14";
+NET "FLASH_A<9>"       LOC = "H13";
+NET "FLASH_A<10>"      LOC = "F18";
+NET "FLASH_A<11>"      LOC = "F17";
+NET "FLASH_A<12>"      LOC = "K13";
+NET "FLASH_A<13>"      LOC = "K12";
+NET "FLASH_A<14>"      LOC = "E18";
+NET "FLASH_A<15>"      LOC = "E16";
+NET "FLASH_A<16>"      LOC = "G13";
+NET "FLASH_A<17>"      LOC = "H12";
+NET "FLASH_A<18>"      LOC = "D18";
+NET "FLASH_A<19>"      LOC = "D17";
+NET "FLASH_A<20>"      LOC = "G14";
+NET "FLASH_A<21>"      LOC = "F14";
+NET "FLASH_A<22>"      LOC = "C18";
+NET "FLASH_A<23>"      LOC = "C17";
+NET "FLASH_A<24>"      LOC = "F16";
+#NET "FLASH_D<0>"       LOC = "R13" | SLEW = "SLOW" | DRIVE = 2;
+#NET "FLASH_D<1>"       LOC = "T14" | SLEW = "SLOW" | DRIVE = 2;
+#NET "FLASH_D<2>"       LOC = "V14" | SLEW = "SLOW" | DRIVE = 2;
+NET "FLASH_D<3>"       LOC = "U5"  | SLEW = "SLOW" | DRIVE = 2;
+NET "FLASH_D<4>"       LOC = "V5"  | SLEW = "SLOW" | DRIVE = 2;
+NET "FLASH_D<5>"       LOC = "R3"  | SLEW = "SLOW" | DRIVE = 2;
+NET "FLASH_D<6>"       LOC = "T3"  | SLEW = "SLOW" | DRIVE = 2;
+NET "FLASH_D<7>"       LOC = "R5"  | SLEW = "SLOW" | DRIVE = 2;
+NET "FLASH_OE_B"       LOC = "L18";
+NET "FLASH_WE_B"       LOC = "M16";
+NET "FLASH_CE_B"       LOC = "L17";
+
+# FMC-Connector, Bank 0,2 (M2C = Mezzanine to Carrier, C2M = Carrier to Mezzanine)
+NET "FMC_CLK0_M2C_N"            LOC = "A10";
+NET "FMC_CLK0_M2C_P"            LOC = "C10";
+NET "FMC_CLK1_M2C_N"            LOC = "V9" ;
+NET "FMC_CLK1_M2C_P"            LOC = "T9" ;
+NET "FMC_LA00_CC_N"             LOC = "C9" ;
+NET "FMC_LA00_CC_P"             LOC = "D9" ;
+NET "FMC_LA01_CC_N"             LOC = "C11";
+NET "FMC_LA01_CC_P"             LOC = "D11";
+NET "FMC_LA02_N"                LOC = "A15";
+NET "FMC_LA02_P"                LOC = "C15";
+NET "FMC_LA03_N"                LOC = "A13";
+NET "FMC_LA03_P"                LOC = "C13";
+NET "FMC_LA04_N"                LOC = "A16";
+NET "FMC_LA04_P"                LOC = "B16";
+NET "FMC_LA05_N"                LOC = "A14";
+NET "FMC_LA05_P"                LOC = "B14";
+NET "FMC_LA06_N"                LOC = "C12";
+NET "FMC_LA06_P"                LOC = "D12";
+NET "FMC_LA07_N"                LOC = "E8" ;
+NET "FMC_LA07_P"                LOC = "E7" ;
+NET "FMC_LA08_N"                LOC = "E11";
+NET "FMC_LA08_P"                LOC = "F11";
+NET "FMC_LA09_N"                LOC = "F10";
+NET "FMC_LA09_P"                LOC = "G11";
+NET "FMC_LA10_N"                LOC = "C8" ;
+NET "FMC_LA10_P"                LOC = "D8" ;
+NET "FMC_LA11_N"                LOC = "A12";
+NET "FMC_LA11_P"                LOC = "B12";
+NET "FMC_LA12_N"                LOC = "C6" ;
+NET "FMC_LA12_P"                LOC = "D6" ;
+NET "FMC_LA13_N"                LOC = "A11";
+NET "FMC_LA13_P"                LOC = "B11";
+NET "FMC_LA14_N"                LOC = "A2" ;
+NET "FMC_LA14_P"                LOC = "B2" ;
+NET "FMC_LA15_N"                LOC = "F9" ;
+NET "FMC_LA15_P"                LOC = "G9" ;
+NET "FMC_LA16_N"                LOC = "A7" ;
+NET "FMC_LA16_P"                LOC = "C7" ;
+NET "FMC_LA17_CC_N"             LOC = "T8" ;
+NET "FMC_LA17_CC_P"             LOC = "R8" ;
+NET "FMC_LA18_CC_N"             LOC = "T10";
+NET "FMC_LA18_CC_P"             LOC = "R10";
+NET "FMC_LA19_N"                LOC = "P7" ;
+NET "FMC_LA19_P"                LOC = "N6" ;
+NET "FMC_LA20_N"                LOC = "P8" ;
+NET "FMC_LA20_P"                LOC = "N7" ;
+NET "FMC_LA21_N"                LOC = "V4" ;
+NET "FMC_LA21_P"                LOC = "T4" ;
+NET "FMC_LA22_N"                LOC = "T7" ;
+NET "FMC_LA22_P"                LOC = "R7" ;
+NET "FMC_LA23_N"                LOC = "P6" ;
+NET "FMC_LA23_P"                LOC = "N5" ;
+NET "FMC_LA24_N"                LOC = "V8" ;
+NET "FMC_LA24_P"                LOC = "U8" ;
+NET "FMC_LA25_N"                LOC = "N11";
+NET "FMC_LA25_P"                LOC = "M11";
+NET "FMC_LA26_N"                LOC = "V7" ;
+NET "FMC_LA26_P"                LOC = "U7" ;
+NET "FMC_LA27_N"                LOC = "T11";
+NET "FMC_LA27_P"                LOC = "R11";
+NET "FMC_LA28_N"                LOC = "V11";
+NET "FMC_LA28_P"                LOC = "U11";
+NET "FMC_LA29_N"                LOC = "N8" ;
+NET "FMC_LA29_P"                LOC = "M8" ;
+NET "FMC_LA30_N"                LOC = "V12";
+NET "FMC_LA30_P"                LOC = "T12";
+NET "FMC_LA31_N"                LOC = "V6" ;
+NET "FMC_LA31_P"                LOC = "T6" ;
+NET "FMC_LA32_N"                LOC = "V15";
+NET "FMC_LA32_P"                LOC = "U15";
+NET "FMC_LA33_N"                LOC = "N9" ;
+NET "FMC_LA33_P"                LOC = "M10";
+NET "FMC_PRSNT_M2C_L"           LOC = "U13";
+NET "FMC_PWR_GOOD_FLASH_RST_B"  LOC = "B3";
+
+# special FPGA pins
+NET "FPGA_AWAKE"                LOC = "P15"| SLEW = SLOW | DRIVE = 2;
+NET "FPGA_CCLK"                 LOC = "R15";
+NET "FPGA_CMP_CLK"              LOC = "U16";
+NET "FPGA_CMP_MOSI"             LOC = "V16";
+NET "FPGA_D0_DIN_MISO_MISO1"    LOC = "R13" | DRIVE = 4; ## 8 on U17 (thru series R187 100 ohm), 33 on U10, 6 on J12
+NET "FPGA_D1_MISO2"             LOC = "T14" | DRIVE = 4; ## 9 on U17 (thru series R186 100 ohm), 35 on U10, 3 on J12
+NET "FPGA_D2_MISO3"             LOC = "V14" | DRIVE = 4; ## 1 on U17, 38 on U10, 2 on J12
+NET "FPGA_HSWAPEN"              LOC = "D4";
+NET "FPGA_INIT_B"               LOC = "U3" | SLEW = SLOW | DRIVE = 4;
+NET "FPGA_M0_CMP_MISO"          LOC = "T15";
+NET "FPGA_M1"                   LOC = "N12";
+NET "FPGA_MOSI_CSI_B_MISO0"     LOC = "T13" | DRIVE = 4;
+NET "FPGA_ONCHIP_TERM1"         LOC = "L6";
+NET "FPGA_ONCHIP_TERM2"         LOC = "C2";
+NET "FPGA_VTEMP"                LOC = "P3";
+
+## Pushbuttons, Bank 3, external Pulldown
+NET "GPIO_BUTTON<0>"            LOC = "P4" ;
+NET "GPIO_BUTTON<1>"            LOC = "F6" ;
+NET "GPIO_BUTTON<2>"            LOC = "E4" ;
+NET "GPIO_BUTTON<3>"            LOC = "F5" ;
+NET "GPIO_BUTTON*"              TIG;
+
+## 8 Pin GPIO Header J13, Bank 0,1,2
+NET "GPIO_HEADER_LS<0>"         LOC = "N17"| SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_HEADER_LS<1>"         LOC = "M18"| SLEW = SLOW | DRIVE = 4 ; 
+NET "GPIO_HEADER_LS<2>"         LOC = "A3" | SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_HEADER_LS<3>"         LOC = "L15"| SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_HEADER_LS<4>"         LOC = "F15"| SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_HEADER_LS<5>"         LOC = "B4" | SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_HEADER_LS<6>"         LOC = "F13"| SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_HEADER_LS<7>"         LOC = "P12"| SLEW = SLOW | DRIVE = 4 ;
+
+## 4 GPIO LEDs, Bank 0
+NET "GPIO_LED<0>"               LOC = "E13"| SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_LED<1>"               LOC = "C14"| SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_LED<2>"               LOC = "C4" | SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_LED<3>"               LOC = "A4" | SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_LED*"                 TIG;
+
+## GPIO Dip Switches, Bank 0,2, external Pulldown
+NET "GPIO_SWITCH<0>"            LOC = "D14";
+NET "GPIO_SWITCH<1>"            LOC = "E12";
+NET "GPIO_SWITCH<2>"            LOC = "F12";
+NET "GPIO_SWITCH<3>"            LOC = "V13";
+NET "GPIO_SWITCH*"              TIG;
+
+## IIC Bus
+NET "IIC_SCL_MAIN"              LOC = "P11";
+NET "IIC_SDA_MAIN"              LOC = "N10";
+
+## 10/100/1000 Tri-Speed Ethernet PHY
+NET "PHY_COL"                   LOC = "L14";
+NET "PHY_CRS"                   LOC = "M13";
+NET "PHY_INT"                   LOC = "J13";
+NET "PHY_MDC"                   LOC = "N14" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_MDIO"                  LOC = "P16" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_RESET"                 LOC = "L13";
+NET "PHY_RXCLK"                 LOC = "L16";
+NET "PHY_RXCTL_RXDV"            LOC = "N18";
+NET "PHY_RXD<0>"                LOC = "M14";
+NET "PHY_RXD<1>"                LOC = "U18";
+NET "PHY_RXD<2>"                LOC = "U17";
+NET "PHY_RXD<3>"                LOC = "T18";
+NET "PHY_RXD<4>"                LOC = "T17";
+NET "PHY_RXD<5>"                LOC = "N16";
+NET "PHY_RXD<6>"                LOC = "N15";
+NET "PHY_RXD<7>"                LOC = "P18";
+NET "PHY_RXER"                  LOC = "P17";
+NET "PHY_TXCLK"                 LOC = "B9" ;
+NET "PHY_TXCTL_TXEN"            LOC = "B8"  | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXC_GTXCLK"            LOC = "A9" ;
+NET "PHY_TXD<0>"                LOC = "F8"  | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXD<1>"                LOC = "G8"  | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXD<2>"                LOC = "A6"  | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXD<3>"                LOC = "B6"  | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXD<4>"                LOC = "E6"  | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXD<5>"                LOC = "F7"  | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXD<6>"                LOC = "A5"  | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXD<7>"                LOC = "C5"  | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXER"                  LOC = "A8"  | SLEW = SLOW | DRIVE = 4;
+
+## SPI x4 Flash
+NET "SPI_CS_B"                  LOC = "V3";
+
+## 200 MHz oscillator (differential)
+NET "SYSCLK_N"                  LOC = "K16"| IOSTANDARD = LVDS_33 | TNM_NET = "SYSCLK";
+NET "SYSCLK_P"                  LOC = "K15"| IOSTANDARD = LVDS_33 | TNM_NET = "SYSCLK";
+
+## USB-UART
+## this names are real net names
+NET "USB_1_CTS"                 LOC = "U10"| DRIVE = 4 | SLEW = SLOW;   # RTS output
+NET "USB_1_RTS"                 LOC = "T5" ;                            # CTS input
+NET "USB_1_RX"                  LOC = "L12"| DRIVE = 4 | SLEW = SLOW;   # TX data out
+NET "USB_1_TX"                  LOC = "K14";                            # RX data in
+
+## 27 MHz
+NET "USER_CLOCK"                LOC = "V10"| IOSTANDARD = LVCMOS33 ;
+##
+NET "USER_SMA_CLOCK_N"          LOC = "H18"| TNM_NET = "USER_SMA_CLOCK";
+NET "USER_SMA_CLOCK_P"          LOC = "H17"| TNM_NET = "USER_SMA_CLOCK";
+
+# pins used for voltage termination
+CONFIG PROHIBIT = C1;
+CONFIG PROHIBIT = M5;
+CONFIG PROHIBIT = N3;
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top.vhd b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top.vhd
index 120b1cf..bbeb0a2 100644
--- a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top.vhd
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top.vhd
@@ -1,533 +1,563 @@
--- top module of
--- SP601 evaluation board
---
--- using following external connections:
---
--- cpu_reset (SW9)      reset
--- LEDs                 output
--- USB_UART             communication 
---
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-library zpu;
-use zpu.zpupkg.all;                     -- zpu_dbgo_t
-
-library unisim;
-use unisim.vcomponents.ibufgds;
-use unisim.vcomponents.dcm_sp;
-
-
-entity top is
-    port (
-        -- pragma translate_off 
-        stop_simulation : out   std_logic;
-        -- pragma translate_on 
-        --
-        cpu_reset                : in    std_logic;  -- SW9 pushbutton (active-high)
-        --
-        -- DDR2 memory 128 MB
-        ddr2_a                   : out   std_logic_vector(12 downto 0);
-        ddr2_ba                  : out   std_logic_vector(2 downto 0);
-        ddr2_cas_b               : out   std_logic;
-        ddr2_ras_b               : out   std_logic;
-        ddr2_we_b                : out   std_logic;
-        ddr2_cke                 : out   std_logic;
-        ddr2_clk_n               : out   std_logic;
-        ddr2_clk_p               : out   std_logic;
-        ddr2_dq                  : inout std_logic_vector(15 downto 0);
-        ddr2_ldm                 : out   std_logic;
-        ddr2_udm                 : out   std_logic;
-        ddr2_ldqs_n              : inout std_logic;
-        ddr2_ldqs_p              : inout std_logic;
-        ddr2_udqs_n              : inout std_logic;
-        ddr2_udqs_p              : inout std_logic;
-        ddr2_odt                 : out   std_logic;
-        --                                
-        -- flash memory                        
-        flash_a                  : out   std_logic_vector(24 downto 0);
-        flash_d                  : inout std_logic_vector(7 downto 3);
-        --
-        fpga_d0_din_miso_miso1   : inout std_logic;  -- dual use
-        fpga_d1_miso2            : inout std_logic;  -- dual use
-        fpga_d2_miso3            : inout std_logic;  -- dual use
-        flash_we_b               : out   std_logic;
-        flash_oe_b               : out   std_logic;
-        flash_ce_b               : out   std_logic;
-        --
-        -- FMC connector
-        -- M2C   Mezzanine to Carrier
-        -- C2M   Carrier to Mezzanine
-        fmc_clk0_m2c_n           : in    std_logic;
-        fmc_clk0_m2c_p           : in    std_logic;
-        fmc_clk1_m2c_n           : in    std_logic;
-        fmc_clk1_m2c_p           : in    std_logic;
-        -- IIC addresses:
-        -- M24C08:                 1010100..1010111
-        -- 2kb EEPROM on FMC card: 1010010
-        iic_scl_main             : inout std_logic;
-        iic_sda_main             : inout std_logic;
-        fmc_la00_cc_n            : inout std_logic;
-        fmc_la00_cc_p            : inout std_logic;
-        fmc_la01_cc_n            : inout std_logic;
-        fmc_la01_cc_p            : inout std_logic;
-        fmc_la02_n               : inout std_logic;
-        fmc_la02_p               : inout std_logic;
-        fmc_la03_n               : inout std_logic;
-        fmc_la03_p               : inout std_logic;
-        fmc_la04_n               : inout std_logic;
-        fmc_la04_p               : inout std_logic;
-        fmc_la05_n               : inout std_logic;
-        fmc_la05_p               : inout std_logic;
-        fmc_la06_n               : inout std_logic;
-        fmc_la06_p               : inout std_logic;
-        fmc_la07_n               : inout std_logic;
-        fmc_la07_p               : inout std_logic;
-        fmc_la08_n               : inout std_logic;
-        fmc_la08_p               : inout std_logic;
-        fmc_la09_n               : inout std_logic;
-        fmc_la09_p               : inout std_logic;
-        fmc_la10_n               : inout std_logic;
-        fmc_la10_p               : inout std_logic;
-        fmc_la11_n               : inout std_logic;
-        fmc_la11_p               : inout std_logic;
-        fmc_la12_n               : inout std_logic;
-        fmc_la12_p               : inout std_logic;
-        fmc_la13_n               : inout std_logic;
-        fmc_la13_p               : inout std_logic;
-        fmc_la14_n               : inout std_logic;
-        fmc_la14_p               : inout std_logic;
-        fmc_la15_n               : inout std_logic;
-        fmc_la15_p               : inout std_logic;
-        fmc_la16_n               : inout std_logic;
-        fmc_la16_p               : inout std_logic;
-        fmc_la17_cc_n            : inout std_logic;
-        fmc_la17_cc_p            : inout std_logic;
-        fmc_la18_cc_n            : inout std_logic;
-        fmc_la18_cc_p            : inout std_logic;
-        fmc_la19_n               : inout std_logic;
-        fmc_la19_p               : inout std_logic;
-        fmc_la20_n               : inout std_logic;
-        fmc_la20_p               : inout std_logic;
-        fmc_la21_n               : inout std_logic;
-        fmc_la21_p               : inout std_logic;
-        fmc_la22_n               : inout std_logic;
-        fmc_la22_p               : inout std_logic;
-        fmc_la23_n               : inout std_logic;
-        fmc_la23_p               : inout std_logic;
-        fmc_la24_n               : inout std_logic;
-        fmc_la24_p               : inout std_logic;
-        fmc_la25_n               : inout std_logic;
-        fmc_la25_p               : inout std_logic;
-        fmc_la26_n               : inout std_logic;
-        fmc_la26_p               : inout std_logic;
-        fmc_la27_n               : inout std_logic;
-        fmc_la27_p               : inout std_logic;
-        fmc_la28_n               : inout std_logic;
-        fmc_la28_p               : inout std_logic;
-        fmc_la29_n               : inout std_logic;
-        fmc_la29_p               : inout std_logic;
-        fmc_la30_n               : inout std_logic;
-        fmc_la30_p               : inout std_logic;
-        fmc_la31_n               : inout std_logic;
-        fmc_la31_p               : inout std_logic;
-        fmc_la32_n               : inout std_logic;
-        fmc_la32_p               : inout std_logic;
-        fmc_la33_n               : inout std_logic;
-        fmc_la33_p               : inout std_logic;
-        fmc_prsnt_m2c_l          : in    std_logic;
-        fmc_pwr_good_flash_rst_b : out   std_logic;  -- multiple destinations: 1 of Q2 (LED DS1 driver), U1 AB2 FPGA_PROG (through series R260 DNP), 44 of U25
-        --
-        fpga_awake               : out   std_logic;
-        fpga_cclk                : out   std_logic;
-        fpga_cmp_clk             : in    std_logic;
-        fpga_cmp_mosi            : in    std_logic;
-        --
-        fpga_hswapen             : in    std_logic;
-        fpga_init_b              : out   std_logic;  -- low active
-        fpga_m0_cmp_miso         : in    std_logic;  -- mode DIP switch SW1 active high
-        fpga_m1                  : in    std_logic;  -- mode DIP switch SW1 active high
-        fpga_mosi_csi_b_miso0    : inout std_logic;
-        fpga_onchip_term1        : inout std_logic;
-        fpga_onchip_term2        : inout std_logic;
-        fpga_vtemp               : in    std_logic;
-        --
-        -- GPIOs
-        gpio_button              : in    std_logic_vector(3 downto 0);  -- active high
-        gpio_header_ls           : inout std_logic_vector(7 downto 0);
-        gpio_led                 : out   std_logic_vector(3 downto 0);
-        gpio_switch              : in    std_logic_vector(3 downto 0);  -- active high
-        --
-        -- Ethernet Gigabit PHY, 
-        -- default settings:
-        -- phy address    = 0b00111
-        -- ANEG[3..0]     = "1111"
-        -- ENA_XC         = 1
-        -- DIS_125        = 1
-        -- HWCFG_MD[3..0] = "1111"
-        -- DIS_FC         = 1
-        -- DIS_SLEEP      = 1
-        -- SEL_BDT        = 0
-        -- INT_POL        = 1
-        -- 75/50Ohm       = 0
-        phy_col                  : in    std_logic;
-        phy_crs                  : in    std_logic;
-        phy_int                  : in    std_logic;
-        phy_mdc                  : out   std_logic;
-        phy_mdio                 : inout std_logic;
-        phy_reset                : out   std_logic;
-        phy_rxclk                : in    std_logic;
-        phy_rxctl_rxdv           : in    std_logic;
-        phy_rxd                  : in    std_logic_vector(7 downto 0);
-        phy_rxer                 : in    std_logic;
-        phy_txclk                : in    std_logic;
-        phy_txctl_txen           : out   std_logic;
-        phy_txc_gtxclk           : out   std_logic;
-        phy_txd                  : out   std_logic_vector(7 downto 0);
-        phy_txer                 : out   std_logic;
-        --
-        --
-        spi_cs_b                 : out   std_logic;
-        --
-        -- 200 MHz oscillator, jitter 50 ppm
-        sysclk_n                 : in    std_logic;
-        sysclk_p                 : in    std_logic;
-        --
-        -- RS232 via USB
-        usb_1_cts                : out   std_logic;  -- function: RTS output
-        usb_1_rts                : in    std_logic;  -- function: CTS input
-        usb_1_rx                 : out   std_logic;  -- function: TX data out
-        usb_1_tx                 : in    std_logic;  -- function: RX data in
-        --
-        --  27 MHz, oscillator socket
-        user_clock               : in    std_logic;
-        --
-        -- user clock provided per SMA
-        user_sma_clock_p         : in    std_logic;
-        user_sma_clock_n         : in    std_logic
-        );
-end entity top;
-
-
-architecture rtl of top is
-
-    ---------------------------
-    -- type declarations
-    type zpu_type is (zpu_small, zpu_medium);
-
-    ---------------------------
-    -- constant declarations
-    constant zpu_flavour   : zpu_type := zpu_medium;  -- choose your flavour HERE
-    --  modify frequency here
-    constant clk_multiply  : positive := 2;  -- 2 for small, 2 for medium
-    constant clk_divide    : positive := 5;  -- 4 for small, 5 for medium
-    --                     
-    --                     
-    constant word_size_c   : natural  := 32;  -- 32 bits data path
-    constant addr_w_c      : natural  := 18;  -- 18 bits address space=256 kB, 128 kB I/O
-    --
-    constant clk_frequency : positive := 200; -- input frequency for correct calculation
-
-
-    ---------------------------
-    -- component declarations
-    component zpu_small1 is
-        generic (
-            word_size  : natural   := 32;      -- 32 bits data path
-            d_care_val : std_logic := '0';     -- Fill value
-            clk_freq   : positive  := 50;      -- 50 MHz clock
-            brate      : positive  := 115200;  -- RS232 baudrate
-            addr_w     : natural   := 16;      -- 16 bits address space=64 kB, 32 kB I/O
-            bram_w     : natural   := 15       -- 15 bits RAM space=32 kB
-            );
-        port (
-            clk_i      : in  std_logic;        -- CPU clock
-            rst_i      : in  std_logic;        -- Reset
-            break_o    : out std_logic;        -- Break executed
-            dbg_o      : out zpu_dbgo_t;       -- Debug info
-            rs232_tx_o : out std_logic;        -- UART Tx
-            rs232_rx_i : in  std_logic         -- UART Rx
-            );
-    end component zpu_small1;
-
-    component zpu_med1 is
-        generic(
-            word_size  : natural   := 32;      -- 32 bits data path
-            d_care_val : std_logic := '0';     -- Fill value
-            clk_freq   : positive  := 50;      -- 50 MHz clock
-            brate      : positive  := 115200;  -- RS232 baudrate
-            addr_w     : natural   := 18;      -- 18 bits address space=256 kB, 128 kB I/O
-            bram_w     : natural   := 15       -- 15 bits RAM space=32 kB
-            );
-        port(
-            clk_i      : in  std_logic;        -- CPU clock
-            rst_i      : in  std_logic;        -- Reset
-            break_o    : out std_logic;        -- Break executed
-            dbg_o      : out zpu_dbgo_t;       -- Debug info
-            rs232_tx_o : out std_logic;        -- UART Tx
-            rs232_rx_i : in  std_logic         -- UART Rx
-            );
-    end component zpu_med1;
-
-
-    ---------------------------
-    -- signal declarations
-    signal sys_clk         : std_ulogic;
-    signal dcm_sp_i0_clk0  : std_ulogic;
-    signal dcm_sp_i0_clkfx : std_ulogic;
-    signal clk_fb          : std_ulogic;
-    signal clk             : std_ulogic;
-    --
-    signal reset_shift_reg : std_ulogic_vector(3 downto 0);
-    signal reset_sync      : std_ulogic;
-    --
-    signal zpu_i0_dbg      : zpu_dbgo_t;  -- Debug info
-    signal zpu_i0_break    : std_logic;
-
-
-begin
-
-    -- default output drivers
-    -- to pass bitgen DRC 
-    -- outputs used by design are commented
-    --
-    ddr2_a                   <= (others => '1');
-    ddr2_ba                  <= (others => '1');
-    ddr2_cas_b               <= '1';
-    ddr2_ras_b               <= '1';
-    ddr2_we_b                <= '1';
-    ddr2_cke                 <= '0';
-    ddr2_clk_n               <= '0';
-    ddr2_clk_p               <= '1';
-    ddr2_dq                  <= (others => 'Z');
-    ddr2_ldm                 <= '0';
-    ddr2_udm                 <= '0';
-    ddr2_ldqs_n              <= 'Z';
-    ddr2_ldqs_p              <= 'Z';
-    ddr2_udqs_n              <= 'Z';
-    ddr2_udqs_p              <= 'Z';
-    ddr2_odt                 <= '1';
-    --
-    flash_a                  <= (others => '1');
-    flash_d                  <= (others => 'Z');
-    flash_we_b               <= '1';
-    flash_oe_b               <= '1';
-    flash_ce_b               <= '1';
-    --
-    fpga_d0_din_miso_miso1   <= 'Z';
-    fpga_d1_miso2            <= 'Z';
-    fpga_d2_miso3            <= 'Z';
-    --
-    iic_scl_main             <= 'Z';
-    iic_sda_main             <= 'Z';
-    fmc_la00_cc_n            <= 'Z';
-    fmc_la00_cc_p            <= 'Z';
-    fmc_la01_cc_n            <= 'Z';
-    fmc_la01_cc_p            <= 'Z';
-    fmc_la02_n               <= 'Z';
-    fmc_la02_p               <= 'Z';
-    fmc_la03_n               <= 'Z';
-    fmc_la03_p               <= 'Z';
-    fmc_la04_n               <= 'Z';
-    fmc_la04_p               <= 'Z';
-    fmc_la05_n               <= 'Z';
-    fmc_la05_p               <= 'Z';
-    fmc_la06_n               <= 'Z';
-    fmc_la06_p               <= 'Z';
-    fmc_la07_n               <= 'Z';
-    fmc_la07_p               <= 'Z';
-    fmc_la08_n               <= 'Z';
-    fmc_la08_p               <= 'Z';
-    fmc_la09_n               <= 'Z';
-    fmc_la09_p               <= 'Z';
-    fmc_la10_n               <= 'Z';
-    fmc_la10_p               <= 'Z';
-    fmc_la11_n               <= 'Z';
-    fmc_la11_p               <= 'Z';
-    fmc_la12_n               <= 'Z';
-    fmc_la12_p               <= 'Z';
-    fmc_la13_n               <= 'Z';
-    fmc_la13_p               <= 'Z';
-    fmc_la14_n               <= 'Z';
-    fmc_la14_p               <= 'Z';
-    fmc_la15_n               <= 'Z';
-    fmc_la15_p               <= 'Z';
-    fmc_la16_n               <= 'Z';
-    fmc_la16_p               <= 'Z';
-    fmc_la17_cc_n            <= 'Z';
-    fmc_la17_cc_p            <= 'Z';
-    fmc_la18_cc_n            <= 'Z';
-    fmc_la18_cc_p            <= 'Z';
-    fmc_la19_n               <= 'Z';
-    fmc_la19_p               <= 'Z';
-    fmc_la20_n               <= 'Z';
-    fmc_la20_p               <= 'Z';
-    fmc_la21_n               <= 'Z';
-    fmc_la21_p               <= 'Z';
-    fmc_la22_n               <= 'Z';
-    fmc_la22_p               <= 'Z';
-    fmc_la23_n               <= 'Z';
-    fmc_la23_p               <= 'Z';
-    fmc_la24_n               <= 'Z';
-    fmc_la24_p               <= 'Z';
-    fmc_la25_n               <= 'Z';
-    fmc_la25_p               <= 'Z';
-    fmc_la26_n               <= 'Z';
-    fmc_la26_p               <= 'Z';
-    fmc_la27_n               <= 'Z';
-    fmc_la27_p               <= 'Z';
-    fmc_la28_n               <= 'Z';
-    fmc_la28_p               <= 'Z';
-    fmc_la29_n               <= 'Z';
-    fmc_la29_p               <= 'Z';
-    fmc_la30_n               <= 'Z';
-    fmc_la30_p               <= 'Z';
-    fmc_la31_n               <= 'Z';
-    fmc_la31_p               <= 'Z';
-    fmc_la32_n               <= 'Z';
-    fmc_la32_p               <= 'Z';
-    fmc_la33_n               <= 'Z';
-    fmc_la33_p               <= 'Z';
-    fmc_pwr_good_flash_rst_b <= '1';
-    --
-    fpga_awake               <= '1';
-    fpga_cclk                <= '1';    -- SPI clk
-    fpga_init_b              <= '1';
-    fpga_mosi_csi_b_miso0    <= 'Z';
-    fpga_onchip_term1        <= 'Z';
-    fpga_onchip_term2        <= 'Z';
-    --
-    --gpio_led               <= (others => '0'); 
-    gpio_header_ls           <= (others => 'Z');
-    --
-    phy_mdc                  <= '0';
-    phy_mdio                 <= 'Z';
-    phy_reset                <= '0';
-    phy_txc_gtxclk           <= '0';
-    phy_txctl_txen           <= '0';
-    phy_txd                  <= (others => '1');
-    phy_txer                 <= '0';
-    --
-    spi_cs_b                 <= '1';
-    --
-    --usb_1_rx               <= '1';    -- function: TX data out
-    usb_1_cts                <= '1';    -- function: RTS
-
-
-    -- global differential input buffer 
-    ibufgds_i0 : ibufgds
-        generic map (
-            diff_term => true
-            )
-        port map (
-            i  => sysclk_p,
-            ib => sysclk_n,
-            o  => sys_clk
-            );
-
-    -- digital clock manager (DCM)
-    -- to generate higher/other system clock frequencys
-    dcm_sp_i0 : dcm_sp
-        generic map (
-            startup_wait   => true,     -- wait with DONE till locked
-            clkfx_multiply => clk_multiply,        
-            clkfx_divide   => clk_divide,        
-            clk_feedback   => "1X"
-            )
-        port map (
-            clkin => sys_clk,
-            clk0  => dcm_sp_i0_clk0,
-            clkfx => dcm_sp_i0_clkfx,
-            clkfb => clk_fb
-            );
-
-    clk_fb <= dcm_sp_i0_clk0;
-    clk    <= dcm_sp_i0_clkfx;
-
-
-    -- reset synchronizer
-    -- generate synchronous reset
-    reset_synchronizer : process(clk, cpu_reset)
-    begin
-        if cpu_reset = '1' then
-            reset_shift_reg <= (others => '1');
-        elsif rising_edge(clk) then
-            reset_shift_reg <= reset_shift_reg(reset_shift_reg'high-1 downto 0) & '0';
-        end if;
-    end process;
-    reset_sync <= reset_shift_reg(reset_shift_reg'high);
-
-
-
-    -- select instance of zpu
-    zpu_i0_small : if zpu_flavour = zpu_small generate
-        zpu_i0 : zpu_small1
-            generic map (
-                addr_w    => addr_w_c,
-                word_size => word_size_c,
-                clk_freq  => clk_frequency * clk_multiply / clk_divide
-                )
-            port map (
-                clk_i      => clk,           -- : in  std_logic;   -- CPU clock
-                rst_i      => reset_sync,    -- : in  std_logic;   -- Reset
-                break_o    => zpu_i0_break,  -- : out std_logic;   -- Break executed
-                dbg_o      => zpu_i0_dbg,    -- : out zpu_dbgo_t;  -- Debug info
-                rs232_tx_o => usb_1_rx,      -- : out std_logic;   -- UART Tx
-                rs232_rx_i => usb_1_tx       -- : in  std_logic    -- UART Rx
-                );
-    end generate zpu_i0_small;
-
-    zpu_i0_medium : if zpu_flavour = zpu_medium generate
-        zpu_i0 : zpu_med1
-            generic map (
-                addr_w    => addr_w_c,
-                word_size => word_size_c,
-                clk_freq  => clk_frequency * clk_multiply / clk_divide
-                )
-            port map (
-                clk_i      => clk,           -- : in  std_logic;   -- CPU clock
-                rst_i      => reset_sync,    -- : in  std_logic;   -- Reset
-                break_o    => zpu_i0_break,  -- : out std_logic;   -- Break executed
-                dbg_o      => zpu_i0_dbg,    -- : out zpu_dbgo_t;  -- Debug info
-                rs232_tx_o => usb_1_rx,      -- : out std_logic;   -- UART Tx
-                rs232_rx_i => usb_1_tx       -- : in  std_logic    -- UART Rx
-                );
-    end generate zpu_i0_medium;
-
-
-    -- pragma translate_off 
-    stop_simulation <= zpu_i0_break;
- 
-
-    trace_mod : trace
-        generic map (
-            addr_w    => addr_w_c,
-            word_size => word_size_c,
-            log_file  => "zpu_trace.log"
-            )
-        port map (
-            clk_i  => clk,
-            dbg_i  => zpu_i0_dbg,
-            stop_i => zpu_i0_break,
-            busy_i => '0'
-            );
-    -- pragma translate_on
-
-
-    -- switch on all LEDs in case of break
-    process
-    begin
-        wait until rising_edge(clk);
-        if zpu_i0_break = '1' then
-            gpio_led <= (others => '1');
-        end if;
-        if reset_sync = '1' then
-            gpio_led <= (others => '0');
-        end if;
-    end process;
-
-    
-
-end architecture rtl;
+-- top module of
+-- SP601 evaluation board
+--
+-- using following external connections:
+--
+-- cpu_reset (SW9)      reset
+-- LEDs                 output
+-- USB_UART             communication 
+--
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library zpu;
+use zpu.zpupkg.all;                     -- zpu_dbgo_t
+
+library unisim;
+use unisim.vcomponents.ibufgds;
+use unisim.vcomponents.dcm_sp;
+
+
+entity top is
+    port (
+        -- pragma translate_off 
+        stop_simulation          : out   std_logic;
+        -- pragma translate_on 
+        --
+        cpu_reset                : in    std_logic;  -- SW9 pushbutton (active-high)
+        --
+        -- DDR2 memory 128 MB
+        ddr2_a                   : out   std_logic_vector(12 downto 0);
+        ddr2_ba                  : out   std_logic_vector(2 downto 0);
+        ddr2_cas_b               : out   std_logic;
+        ddr2_ras_b               : out   std_logic;
+        ddr2_we_b                : out   std_logic;
+        ddr2_cke                 : out   std_logic;
+        ddr2_clk_n               : out   std_logic;
+        ddr2_clk_p               : out   std_logic;
+        ddr2_dq                  : inout std_logic_vector(15 downto 0);
+        ddr2_ldm                 : out   std_logic;
+        ddr2_udm                 : out   std_logic;
+        ddr2_ldqs_n              : inout std_logic;
+        ddr2_ldqs_p              : inout std_logic;
+        ddr2_udqs_n              : inout std_logic;
+        ddr2_udqs_p              : inout std_logic;
+        ddr2_odt                 : out   std_logic;
+        --                                
+        -- flash memory                        
+        flash_a                  : out   std_logic_vector(24 downto 0);
+        flash_d                  : inout std_logic_vector(7 downto 3);
+        --
+        fpga_d0_din_miso_miso1   : inout std_logic;  -- dual use
+        fpga_d1_miso2            : inout std_logic;  -- dual use
+        fpga_d2_miso3            : inout std_logic;  -- dual use
+        flash_we_b               : out   std_logic;
+        flash_oe_b               : out   std_logic;
+        flash_ce_b               : out   std_logic;
+        --
+        -- FMC connector
+        -- M2C   Mezzanine to Carrier
+        -- C2M   Carrier to Mezzanine
+        fmc_clk0_m2c_n           : in    std_logic;
+        fmc_clk0_m2c_p           : in    std_logic;
+        fmc_clk1_m2c_n           : in    std_logic;
+        fmc_clk1_m2c_p           : in    std_logic;
+        -- IIC addresses:
+        -- M24C08:                 1010100..1010111
+        -- 2kb EEPROM on FMC card: 1010010
+        iic_scl_main             : inout std_logic;
+        iic_sda_main             : inout std_logic;
+        fmc_la00_cc_n            : inout std_logic;
+        fmc_la00_cc_p            : inout std_logic;
+        fmc_la01_cc_n            : inout std_logic;
+        fmc_la01_cc_p            : inout std_logic;
+        fmc_la02_n               : inout std_logic;
+        fmc_la02_p               : inout std_logic;
+        fmc_la03_n               : inout std_logic;
+        fmc_la03_p               : inout std_logic;
+        fmc_la04_n               : inout std_logic;
+        fmc_la04_p               : inout std_logic;
+        fmc_la05_n               : inout std_logic;
+        fmc_la05_p               : inout std_logic;
+        fmc_la06_n               : inout std_logic;
+        fmc_la06_p               : inout std_logic;
+        fmc_la07_n               : inout std_logic;
+        fmc_la07_p               : inout std_logic;
+        fmc_la08_n               : inout std_logic;
+        fmc_la08_p               : inout std_logic;
+        fmc_la09_n               : inout std_logic;
+        fmc_la09_p               : inout std_logic;
+        fmc_la10_n               : inout std_logic;
+        fmc_la10_p               : inout std_logic;
+        fmc_la11_n               : inout std_logic;
+        fmc_la11_p               : inout std_logic;
+        fmc_la12_n               : inout std_logic;
+        fmc_la12_p               : inout std_logic;
+        fmc_la13_n               : inout std_logic;
+        fmc_la13_p               : inout std_logic;
+        fmc_la14_n               : inout std_logic;
+        fmc_la14_p               : inout std_logic;
+        fmc_la15_n               : inout std_logic;
+        fmc_la15_p               : inout std_logic;
+        fmc_la16_n               : inout std_logic;
+        fmc_la16_p               : inout std_logic;
+        fmc_la17_cc_n            : inout std_logic;
+        fmc_la17_cc_p            : inout std_logic;
+        fmc_la18_cc_n            : inout std_logic;
+        fmc_la18_cc_p            : inout std_logic;
+        fmc_la19_n               : inout std_logic;
+        fmc_la19_p               : inout std_logic;
+        fmc_la20_n               : inout std_logic;
+        fmc_la20_p               : inout std_logic;
+        fmc_la21_n               : inout std_logic;
+        fmc_la21_p               : inout std_logic;
+        fmc_la22_n               : inout std_logic;
+        fmc_la22_p               : inout std_logic;
+        fmc_la23_n               : inout std_logic;
+        fmc_la23_p               : inout std_logic;
+        fmc_la24_n               : inout std_logic;
+        fmc_la24_p               : inout std_logic;
+        fmc_la25_n               : inout std_logic;
+        fmc_la25_p               : inout std_logic;
+        fmc_la26_n               : inout std_logic;
+        fmc_la26_p               : inout std_logic;
+        fmc_la27_n               : inout std_logic;
+        fmc_la27_p               : inout std_logic;
+        fmc_la28_n               : inout std_logic;
+        fmc_la28_p               : inout std_logic;
+        fmc_la29_n               : inout std_logic;
+        fmc_la29_p               : inout std_logic;
+        fmc_la30_n               : inout std_logic;
+        fmc_la30_p               : inout std_logic;
+        fmc_la31_n               : inout std_logic;
+        fmc_la31_p               : inout std_logic;
+        fmc_la32_n               : inout std_logic;
+        fmc_la32_p               : inout std_logic;
+        fmc_la33_n               : inout std_logic;
+        fmc_la33_p               : inout std_logic;
+        fmc_prsnt_m2c_l          : in    std_logic;
+        fmc_pwr_good_flash_rst_b : out   std_logic;  -- multiple destinations: 1 of Q2 (LED DS1 driver), U1 AB2 FPGA_PROG (through series R260 DNP), 44 of U25
+        --
+        fpga_awake               : out   std_logic;
+        fpga_cclk                : out   std_logic;
+        fpga_cmp_clk             : in    std_logic;
+        fpga_cmp_mosi            : in    std_logic;
+        --
+        fpga_hswapen             : in    std_logic;
+        fpga_init_b              : out   std_logic;  -- low active
+        fpga_m0_cmp_miso         : in    std_logic;  -- mode DIP switch SW1 active high
+        fpga_m1                  : in    std_logic;  -- mode DIP switch SW1 active high
+        fpga_mosi_csi_b_miso0    : inout std_logic;
+        fpga_onchip_term1        : inout std_logic;
+        fpga_onchip_term2        : inout std_logic;
+        fpga_vtemp               : in    std_logic;
+        --
+        -- GPIOs
+        gpio_button              : in    std_logic_vector(3 downto 0);  -- active high
+        gpio_header_ls           : inout std_logic_vector(7 downto 0);
+        gpio_led                 : out   std_logic_vector(3 downto 0);
+        gpio_switch              : in    std_logic_vector(3 downto 0);  -- active high
+        --
+        -- Ethernet Gigabit PHY, 
+        -- default settings:
+        -- phy address    = 0b00111
+        -- ANEG[3..0]     = "1111"
+        -- ENA_XC         = 1
+        -- DIS_125        = 1
+        -- HWCFG_MD[3..0] = "1111"
+        -- DIS_FC         = 1
+        -- DIS_SLEEP      = 1
+        -- SEL_BDT        = 0
+        -- INT_POL        = 1
+        -- 75/50Ohm       = 0
+        phy_col                  : in    std_logic;
+        phy_crs                  : in    std_logic;
+        phy_int                  : in    std_logic;
+        phy_mdc                  : out   std_logic;
+        phy_mdio                 : inout std_logic;
+        phy_reset                : out   std_logic;
+        phy_rxclk                : in    std_logic;
+        phy_rxctl_rxdv           : in    std_logic;
+        phy_rxd                  : in    std_logic_vector(7 downto 0);
+        phy_rxer                 : in    std_logic;
+        phy_txclk                : in    std_logic;
+        phy_txctl_txen           : out   std_logic;
+        phy_txc_gtxclk           : out   std_logic;
+        phy_txd                  : out   std_logic_vector(7 downto 0);
+        phy_txer                 : out   std_logic;
+        --
+        --
+        spi_cs_b                 : out   std_logic;
+        --
+        -- 200 MHz oscillator, jitter 50 ppm
+        sysclk_n                 : in    std_logic;
+        sysclk_p                 : in    std_logic;
+        --
+        -- RS232 via USB
+        usb_1_cts                : out   std_logic;  -- function: RTS output
+        usb_1_rts                : in    std_logic;  -- function: CTS input
+        usb_1_rx                 : out   std_logic;  -- function: TX data out
+        usb_1_tx                 : in    std_logic;  -- function: RX data in
+        --
+        --  27 MHz, oscillator socket
+        user_clock               : in    std_logic;
+        --
+        -- user clock provided per SMA
+        user_sma_clock_p         : in    std_logic;
+        user_sma_clock_n         : in    std_logic
+        );
+end entity top;
+
+
+architecture rtl of top is
+
+    ---------------------------
+    -- type declarations
+    type zpu_type is (zpu_small, zpu_medium);
+
+    ---------------------------
+    -- constant declarations
+    constant zpu_flavour   : zpu_type := zpu_medium;  -- choose your flavour HERE
+    --  modify frequency here
+    constant clk_multiply  : positive := 2;  -- 2 for small, 2 for medium
+    constant clk_divide    : positive := 5;  -- 4 for small, 5 for medium
+    --
+    --
+    constant word_size_c   : natural  := 32;  -- 32 bits data path
+    constant addr_w_c      : natural  := 18;  -- 18 bits address space=256 kB, 128 kB I/O
+    --
+    constant clk_frequency : positive := 200; -- input frequency for correct calculation
+
+
+    ---------------------------
+    -- component declarations
+    component zpu_small1 is
+        generic (
+            word_size  : natural   := 32;      -- 32 bits data path
+            d_care_val : std_logic := '0';     -- Fill value
+            clk_freq   : positive  := 50;      -- 50 MHz clock
+            brate      : positive  := 115200;  -- RS232 baudrate
+            addr_w     : natural   := 16;      -- 16 bits address space=64 kB, 32 kB I/O
+            bram_w     : natural   := 15       -- 15 bits RAM space=32 kB
+            );
+        port (
+            clk_i      : in  std_logic;        -- CPU clock
+            rst_i      : in  std_logic;        -- Reset
+            break_o    : out std_logic;        -- Break executed
+            dbg_o      : out zpu_dbgo_t;       -- Debug info
+            rs232_tx_o : out std_logic;        -- UART Tx
+            rs232_rx_i : in  std_logic;        -- UART Rx
+            gpio_in    : in  std_logic_vector(31 downto 0);
+            gpio_out   : out std_logic_vector(31 downto 0);
+            gpio_dir   : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
+            );
+    end component zpu_small1;
+
+    component zpu_med1 is
+        generic(
+            word_size  : natural   := 32;      -- 32 bits data path
+            d_care_val : std_logic := '0';     -- Fill value
+            clk_freq   : positive  := 50;      -- 50 MHz clock
+            brate      : positive  := 115200;  -- RS232 baudrate
+            addr_w     : natural   := 18;      -- 18 bits address space=256 kB, 128 kB I/O
+            bram_w     : natural   := 15       -- 15 bits RAM space=32 kB
+            );
+        port(
+            clk_i      : in  std_logic;        -- CPU clock
+            rst_i      : in  std_logic;        -- Reset
+            break_o    : out std_logic;        -- Break executed
+            dbg_o      : out zpu_dbgo_t;       -- Debug info
+            rs232_tx_o : out std_logic;        -- UART Tx
+            rs232_rx_i : in  std_logic;        -- UART Rx
+            gpio_in    : in  std_logic_vector(31 downto 0);
+            gpio_out   : out std_logic_vector(31 downto 0);
+            gpio_dir   : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
+            );
+    end component zpu_med1;
+
+
+
+    ---------------------------
+    -- signal declarations
+    signal sys_clk           : std_ulogic;
+    signal dcm_sp_i0_clk0    : std_ulogic;
+    signal dcm_sp_i0_clkfx   : std_ulogic;
+    signal clk_fb            : std_ulogic;
+    signal clk               : std_ulogic;
+    --
+    signal reset_shift_reg   : std_ulogic_vector(3 downto 0);
+    signal reset_sync        : std_ulogic;
+    --
+    signal zpu_i0_dbg        : zpu_dbgo_t;  -- Debug info
+    signal zpu_i0_break      : std_logic;
+    --
+    signal gpio_in           : std_logic_vector(31 downto 0) := (others => '0');
+    signal zpu_i0_gpio_out   : std_logic_vector(31 downto 0);
+    signal zpu_i0_gpio_dir   : std_logic_vector(31 downto 0);
+
+
+begin
+
+    -- default output drivers
+    -- to pass bitgen DRC 
+    -- outputs used by design are commented
+    --
+    ddr2_a                   <= (others => '1');
+    ddr2_ba                  <= (others => '1');
+    ddr2_cas_b               <= '1';
+    ddr2_ras_b               <= '1';
+    ddr2_we_b                <= '1';
+    ddr2_cke                 <= '0';
+    ddr2_clk_n               <= '0';
+    ddr2_clk_p               <= '1';
+    ddr2_dq                  <= (others => 'Z');
+    ddr2_ldm                 <= '0';
+    ddr2_udm                 <= '0';
+    ddr2_ldqs_n              <= 'Z';
+    ddr2_ldqs_p              <= 'Z';
+    ddr2_udqs_n              <= 'Z';
+    ddr2_udqs_p              <= 'Z';
+    ddr2_odt                 <= '1';
+    --
+    flash_a                  <= (others => '1');
+    flash_d                  <= (others => 'Z');
+    flash_we_b               <= '1';
+    flash_oe_b               <= '1';
+    flash_ce_b               <= '1';
+    --
+    fpga_d0_din_miso_miso1   <= 'Z';
+    fpga_d1_miso2            <= 'Z';
+    fpga_d2_miso3            <= 'Z';
+    --
+    iic_scl_main             <= 'Z';
+    iic_sda_main             <= 'Z';
+    fmc_la00_cc_n            <= 'Z';
+    fmc_la00_cc_p            <= 'Z';
+    fmc_la01_cc_n            <= 'Z';
+    fmc_la01_cc_p            <= 'Z';
+    fmc_la02_n               <= 'Z';
+    fmc_la02_p               <= 'Z';
+    fmc_la03_n               <= 'Z';
+    fmc_la03_p               <= 'Z';
+    fmc_la04_n               <= 'Z';
+    fmc_la04_p               <= 'Z';
+    fmc_la05_n               <= 'Z';
+    fmc_la05_p               <= 'Z';
+    fmc_la06_n               <= 'Z';
+    fmc_la06_p               <= 'Z';
+    fmc_la07_n               <= 'Z';
+    fmc_la07_p               <= 'Z';
+    fmc_la08_n               <= 'Z';
+    fmc_la08_p               <= 'Z';
+    fmc_la09_n               <= 'Z';
+    fmc_la09_p               <= 'Z';
+    fmc_la10_n               <= 'Z';
+    fmc_la10_p               <= 'Z';
+    fmc_la11_n               <= 'Z';
+    fmc_la11_p               <= 'Z';
+    fmc_la12_n               <= 'Z';
+    fmc_la12_p               <= 'Z';
+    fmc_la13_n               <= 'Z';
+    fmc_la13_p               <= 'Z';
+    fmc_la14_n               <= 'Z';
+    fmc_la14_p               <= 'Z';
+    fmc_la15_n               <= 'Z';
+    fmc_la15_p               <= 'Z';
+    fmc_la16_n               <= 'Z';
+    fmc_la16_p               <= 'Z';
+    fmc_la17_cc_n            <= 'Z';
+    fmc_la17_cc_p            <= 'Z';
+    fmc_la18_cc_n            <= 'Z';
+    fmc_la18_cc_p            <= 'Z';
+    fmc_la19_n               <= 'Z';
+    fmc_la19_p               <= 'Z';
+    fmc_la20_n               <= 'Z';
+    fmc_la20_p               <= 'Z';
+    fmc_la21_n               <= 'Z';
+    fmc_la21_p               <= 'Z';
+    fmc_la22_n               <= 'Z';
+    fmc_la22_p               <= 'Z';
+    fmc_la23_n               <= 'Z';
+    fmc_la23_p               <= 'Z';
+    fmc_la24_n               <= 'Z';
+    fmc_la24_p               <= 'Z';
+    fmc_la25_n               <= 'Z';
+    fmc_la25_p               <= 'Z';
+    fmc_la26_n               <= 'Z';
+    fmc_la26_p               <= 'Z';
+    fmc_la27_n               <= 'Z';
+    fmc_la27_p               <= 'Z';
+    fmc_la28_n               <= 'Z';
+    fmc_la28_p               <= 'Z';
+    fmc_la29_n               <= 'Z';
+    fmc_la29_p               <= 'Z';
+    fmc_la30_n               <= 'Z';
+    fmc_la30_p               <= 'Z';
+    fmc_la31_n               <= 'Z';
+    fmc_la31_p               <= 'Z';
+    fmc_la32_n               <= 'Z';
+    fmc_la32_p               <= 'Z';
+    fmc_la33_n               <= 'Z';
+    fmc_la33_p               <= 'Z';
+    fmc_pwr_good_flash_rst_b <= '1';
+    --
+    fpga_awake               <= '1';
+    fpga_cclk                <= '1';    -- SPI clk
+    fpga_init_b              <= '1';
+    fpga_mosi_csi_b_miso0    <= 'Z';
+    fpga_onchip_term1        <= 'Z';
+    fpga_onchip_term2        <= 'Z';
+    --
+    --gpio_led               <= (others => '0'); 
+    --gpio_header_ls         <= (others => 'Z');
+    --
+    phy_mdc                  <= '0';
+    phy_mdio                 <= 'Z';
+    phy_reset                <= '0';
+    phy_txc_gtxclk           <= '0';
+    phy_txctl_txen           <= '0';
+    phy_txd                  <= (others => '1');
+    phy_txer                 <= '0';
+    --
+    spi_cs_b                 <= '1';
+    --
+    --usb_1_rx               <= '1';    -- function: TX data out
+    usb_1_cts                <= '1';    -- function: RTS
+
+
+    -- global differential input buffer 
+    ibufgds_i0 : ibufgds
+        generic map (
+            diff_term => true
+            )
+        port map (
+            i  => sysclk_p,
+            ib => sysclk_n,
+            o  => sys_clk
+            );
+
+    -- digital clock manager (DCM)
+    -- to generate higher/other system clock frequencys
+    dcm_sp_i0 : dcm_sp
+        generic map (
+            startup_wait   => true,     -- wait with DONE till locked
+            clkfx_multiply => clk_multiply,        
+            clkfx_divide   => clk_divide,        
+            clk_feedback   => "1X"
+            )
+        port map (
+            clkin => sys_clk,
+            clk0  => dcm_sp_i0_clk0,
+            clkfx => dcm_sp_i0_clkfx,
+            clkfb => clk_fb
+            );
+
+    clk_fb <= dcm_sp_i0_clk0;
+    clk    <= dcm_sp_i0_clkfx;
+
+
+    -- reset synchronizer
+    -- generate synchronous reset
+    reset_synchronizer : process(clk, cpu_reset)
+    begin
+        if cpu_reset = '1' then
+            reset_shift_reg <= (others => '1');
+        elsif rising_edge(clk) then
+            reset_shift_reg <= reset_shift_reg(reset_shift_reg'high-1 downto 0) & '0';
+        end if;
+    end process;
+    reset_sync <= reset_shift_reg(reset_shift_reg'high);
+
+
+
+    -- select instance of zpu
+    zpu_i0_small: if zpu_flavour = zpu_small generate
+        zpu_i0 : zpu_small1
+            generic map (
+                addr_w    => addr_w_c,
+                word_size => word_size_c,
+                clk_freq  => clk_frequency * clk_multiply / clk_divide
+                )
+            port map (
+                clk_i      => clk,             -- : in  std_logic;   -- CPU clock
+                rst_i      => reset_sync,      -- : in  std_logic;   -- Reset
+                break_o    => zpu_i0_break,    -- : out std_logic;   -- Break executed
+                dbg_o      => zpu_i0_dbg,      -- : out zpu_dbgo_t;  -- Debug info
+                rs232_tx_o => usb_1_rx,        -- : out std_logic;   -- UART Tx
+                rs232_rx_i => usb_1_tx,        -- : in  std_logic    -- UART Rx
+                gpio_in    => gpio_in,         -- : in  std_logic_vector(31 downto 0);
+                gpio_out   => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
+                gpio_dir   => zpu_i0_gpio_dir  -- : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
+                );
+    end generate zpu_i0_small;
+
+    zpu_i0_medium: if zpu_flavour = zpu_medium generate
+        zpu_i0 : zpu_med1
+            generic map (
+                addr_w    => addr_w_c,
+                word_size => word_size_c,
+                clk_freq  => clk_frequency * clk_multiply / clk_divide
+                )
+            port map (
+                clk_i      => clk,             -- : in  std_logic;   -- CPU clock
+                rst_i      => reset_sync,      -- : in  std_logic;   -- Reset
+                break_o    => zpu_i0_break,    -- : out std_logic;   -- Break executed
+                dbg_o      => zpu_i0_dbg,      -- : out zpu_dbgo_t;  -- Debug info
+                rs232_tx_o => usb_1_rx,        -- : out std_logic;   -- UART Tx
+                rs232_rx_i => usb_1_tx,        -- : in  std_logic    -- UART Rx
+                gpio_in    => gpio_in,         -- : in  std_logic_vector(31 downto 0);
+                gpio_out   => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
+                gpio_dir   => zpu_i0_gpio_dir  -- : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
+                );
+    end generate zpu_i0_medium;
+
+
+    -- pragma translate_off 
+    stop_simulation <= zpu_i0_break; -- abort() causes to stop the simulation
+
+ 
+
+    trace_mod : trace
+        generic map (
+            addr_w    => addr_w_c,
+            word_size => word_size_c,
+            log_file  => "zpu_trace.log"
+            )
+        port map (
+            clk_i  => clk,
+            dbg_i  => zpu_i0_dbg,
+            stop_i => zpu_i0_break,
+            busy_i => '0'
+            );
+    -- pragma translate_on
+
+    -- assign GPIOs
+    gpio_in(23 downto 16) <= gpio_header_ls;
+    gpio_in(11 downto  8) <= gpio_switch;
+    gpio_in( 3 downto  0) <= gpio_button;
+
+    -- 3-state buffers for header_ls
+    gpio_header_ls(7) <= zpu_i0_gpio_out(23) when zpu_i0_gpio_dir(23) = '0' else 'Z';
+    gpio_header_ls(6) <= zpu_i0_gpio_out(22) when zpu_i0_gpio_dir(22) = '0' else 'Z';
+    gpio_header_ls(5) <= zpu_i0_gpio_out(21) when zpu_i0_gpio_dir(21) = '0' else 'Z';
+    gpio_header_ls(4) <= zpu_i0_gpio_out(20) when zpu_i0_gpio_dir(20) = '0' else 'Z';
+    gpio_header_ls(3) <= zpu_i0_gpio_out(19) when zpu_i0_gpio_dir(19) = '0' else 'Z';
+    gpio_header_ls(2) <= zpu_i0_gpio_out(18) when zpu_i0_gpio_dir(18) = '0' else 'Z';
+    gpio_header_ls(1) <= zpu_i0_gpio_out(17) when zpu_i0_gpio_dir(17) = '0' else 'Z';
+    gpio_header_ls(0) <= zpu_i0_gpio_out(16) when zpu_i0_gpio_dir(16) = '0' else 'Z';
+
+    -- switch on all LEDs in case of break
+    process
+    begin
+        wait until rising_edge(clk);
+        gpio_led <= zpu_i0_gpio_out(3 downto 0); 
+        if zpu_i0_break = '1' then
+            gpio_led <= (others => '1');
+        end if;
+    end process;
+
+
+
+end architecture rtl;
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top_tb.vhd b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top_tb.vhd
index b09b144..f089f29 100644
--- a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top_tb.vhd
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top_tb.vhd
@@ -1,398 +1,402 @@
--- testbench for 
--- SP601 evaluation board
---
--- includes "model" for clock generation
--- simulate press on cpu_reset as reset
---
--- place models for external components (PHY, DDR2) in this file
---
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-
-entity top_tb is
-end entity top_tb;
-
-architecture testbench of top_tb is
-
-    ---------------------------
-    -- constant declarations
-    constant sys_clk_period  : time := 1 sec / 200_000_000;  -- 200 MHz
-    constant user_clk_period : time := 1 sec / 27_000_000;   -- 27 MHz
-
-
-    ---------------------------
-    -- signal declarations
-    signal simulation_run              : boolean                      := true;
-    signal tb_stop_simulation          : std_logic;
-    --
-    signal tb_cpu_reset                : std_logic;  -- SW9 pushbutton (active-high)
-    --
-    -- DDR2 memory 128 MB
-    signal tb_ddr2_a                   : std_logic_vector(12 downto 0);
-    signal tb_ddr2_ba                  : std_logic_vector(2 downto 0);
-    signal tb_ddr2_cas_b               : std_logic;
-    signal tb_ddr2_ras_b               : std_logic;
-    signal tb_ddr2_we_b                : std_logic;
-    signal tb_ddr2_cke                 : std_logic;
-    signal tb_ddr2_clk_n               : std_logic;
-    signal tb_ddr2_clk_p               : std_logic;
-    signal tb_ddr2_dq                  : std_logic_vector(15 downto 0);
-    signal tb_ddr2_ldm                 : std_logic;
-    signal tb_ddr2_udm                 : std_logic;
-    signal tb_ddr2_ldqs_n              : std_logic;
-    signal tb_ddr2_ldqs_p              : std_logic;
-    signal tb_ddr2_udqs_n              : std_logic;
-    signal tb_ddr2_udqs_p              : std_logic;
-    signal tb_ddr2_odt                 : std_logic;
-    --                                
-    -- flash memory                        
-    signal tb_flash_a                  : std_logic_vector(24 downto 0);
-    signal tb_flash_d                  : std_logic_vector(7 downto 3);
-    signal tb_fpga_d0_din_miso_miso1   : std_logic;  -- dual use
-    signal tb_fpga_d1_miso2            : std_logic;  -- dual use
-    signal tb_fpga_d2_miso3            : std_logic;  -- dual use
-    signal tb_flash_we_b               : std_logic;
-    signal tb_flash_oe_b               : std_logic;
-    signal tb_flash_ce_b               : std_logic;
-    --
-    -- FMC connector
-    -- M2C   Mezzanine to Carrier
-    -- C2M   Carrier to Mezzanine
-    signal tb_fmc_clk0_m2c_n           : std_logic                    := '1';
-    signal tb_fmc_clk0_m2c_p           : std_logic                    := '0';
-    signal tb_fmc_clk1_m2c_n           : std_logic                    := '1';
-    signal tb_fmc_clk1_m2c_p           : std_logic                    := '0';
-    -- IIC addresses:
-    -- M24C08:                 1010100..1010111
-    -- 2kb EEPROM on FMC card: 1010010
-    signal tb_iic_scl_main             : std_logic;
-    signal tb_iic_sda_main             : std_logic;
-    signal tb_fmc_la00_cc_n            : std_logic;
-    signal tb_fmc_la00_cc_p            : std_logic;
-    signal tb_fmc_la01_cc_n            : std_logic;
-    signal tb_fmc_la01_cc_p            : std_logic;
-    signal tb_fmc_la02_n               : std_logic;
-    signal tb_fmc_la02_p               : std_logic;
-    signal tb_fmc_la03_n               : std_logic;
-    signal tb_fmc_la03_p               : std_logic;
-    signal tb_fmc_la04_n               : std_logic;
-    signal tb_fmc_la04_p               : std_logic;
-    signal tb_fmc_la05_n               : std_logic;
-    signal tb_fmc_la05_p               : std_logic;
-    signal tb_fmc_la06_n               : std_logic;
-    signal tb_fmc_la06_p               : std_logic;
-    signal tb_fmc_la07_n               : std_logic;
-    signal tb_fmc_la07_p               : std_logic;
-    signal tb_fmc_la08_n               : std_logic;
-    signal tb_fmc_la08_p               : std_logic;
-    signal tb_fmc_la09_n               : std_logic;
-    signal tb_fmc_la09_p               : std_logic;
-    signal tb_fmc_la10_n               : std_logic;
-    signal tb_fmc_la10_p               : std_logic;
-    signal tb_fmc_la11_n               : std_logic;
-    signal tb_fmc_la11_p               : std_logic;
-    signal tb_fmc_la12_n               : std_logic;
-    signal tb_fmc_la12_p               : std_logic;
-    signal tb_fmc_la13_n               : std_logic;
-    signal tb_fmc_la13_p               : std_logic;
-    signal tb_fmc_la14_n               : std_logic;
-    signal tb_fmc_la14_p               : std_logic;
-    signal tb_fmc_la15_n               : std_logic;
-    signal tb_fmc_la15_p               : std_logic;
-    signal tb_fmc_la16_n               : std_logic;
-    signal tb_fmc_la16_p               : std_logic;
-    signal tb_fmc_la17_cc_n            : std_logic;
-    signal tb_fmc_la17_cc_p            : std_logic;
-    signal tb_fmc_la18_cc_n            : std_logic;
-    signal tb_fmc_la18_cc_p            : std_logic;
-    signal tb_fmc_la19_n               : std_logic;
-    signal tb_fmc_la19_p               : std_logic;
-    signal tb_fmc_la20_n               : std_logic;
-    signal tb_fmc_la20_p               : std_logic;
-    signal tb_fmc_la21_n               : std_logic;
-    signal tb_fmc_la21_p               : std_logic;
-    signal tb_fmc_la22_n               : std_logic;
-    signal tb_fmc_la22_p               : std_logic;
-    signal tb_fmc_la23_n               : std_logic;
-    signal tb_fmc_la23_p               : std_logic;
-    signal tb_fmc_la24_n               : std_logic;
-    signal tb_fmc_la24_p               : std_logic;
-    signal tb_fmc_la25_n               : std_logic;
-    signal tb_fmc_la25_p               : std_logic;
-    signal tb_fmc_la26_n               : std_logic;
-    signal tb_fmc_la26_p               : std_logic;
-    signal tb_fmc_la27_n               : std_logic;
-    signal tb_fmc_la27_p               : std_logic;
-    signal tb_fmc_la28_n               : std_logic;
-    signal tb_fmc_la28_p               : std_logic;
-    signal tb_fmc_la29_n               : std_logic;
-    signal tb_fmc_la29_p               : std_logic;
-    signal tb_fmc_la30_n               : std_logic;
-    signal tb_fmc_la30_p               : std_logic;
-    signal tb_fmc_la31_n               : std_logic;
-    signal tb_fmc_la31_p               : std_logic;
-    signal tb_fmc_la32_n               : std_logic;
-    signal tb_fmc_la32_p               : std_logic;
-    signal tb_fmc_la33_n               : std_logic;
-    signal tb_fmc_la33_p               : std_logic;
-    signal tb_fmc_prsnt_m2c_l          : std_logic                    := '0';
-    signal tb_fmc_pwr_good_flash_rst_b : std_logic;  -- multiple destinations: 1 of Q2 (LED DS1 driver), U1 AB2 FPGA_PROG (through series R260 DNP), 44 of U25
-    --
-    signal tb_fpga_awake               : std_logic;
-    signal tb_fpga_cclk                : std_logic;
-    signal tb_fpga_cmp_clk             : std_logic                    := '0';
-    signal tb_fpga_cmp_mosi            : std_logic                    := '0';
-    signal tb_fpga_hswapen             : std_logic                    := '0';
-    signal tb_fpga_init_b              : std_logic;  -- low active
-    signal tb_fpga_m0_cmp_miso         : std_logic                    := '0';  -- mode DIP switch SW1 active high
-    signal tb_fpga_m1                  : std_logic                    := '0';  -- mode DIP switch SW1 active high
-    signal tb_fpga_mosi_csi_b_miso0    : std_logic;
-    signal tb_fpga_onchip_term1        : std_logic;
-    signal tb_fpga_onchip_term2        : std_logic;
-    signal tb_fpga_vtemp               : std_logic                    := '0';
-    --
-    -- GPIOs
-    signal tb_gpio_button              : std_logic_vector(3 downto 0) := (others => '0');  -- active high
-    signal tb_gpio_header_ls           : std_logic_vector(7 downto 0);  -- 
-    signal tb_gpio_led                 : std_logic_vector(3 downto 0);
-    signal tb_gpio_switch              : std_logic_vector(3 downto 0) := (others => '0');  -- active high
-    --
-    -- Ethernet Gigabit PHY 
-    signal tb_phy_col                  : std_logic                    := '0';
-    signal tb_phy_crs                  : std_logic                    := '0';
-    signal tb_phy_int                  : std_logic                    := '0';
-    signal tb_phy_mdc                  : std_logic;
-    signal tb_phy_mdio                 : std_logic;
-    signal tb_phy_reset                : std_logic;
-    signal tb_phy_rxclk                : std_logic                    := '0';
-    signal tb_phy_rxctl_rxdv           : std_logic                    := '0';
-    signal tb_phy_rxd                  : std_logic_vector(7 downto 0);
-    signal tb_phy_rxer                 : std_logic                    := '0';
-    signal tb_phy_txclk                : std_logic                    := '0';
-    signal tb_phy_txctl_txen           : std_logic;
-    signal tb_phy_txc_gtxclk           : std_logic;
-    signal tb_phy_txd                  : std_logic_vector(7 downto 0);
-    signal tb_phy_txer                 : std_logic;
-    --
-    --
-    signal tb_spi_cs_b                 : std_logic;
-    --
-    -- 200 MHz oscillator, jitter 50 ppm
-    signal tb_sysclk_n                 : std_logic                    := '1';
-    signal tb_sysclk_p                 : std_logic                    := '0';
-    --
-    -- RS232 via USB
-    signal tb_usb_1_cts                : std_logic;  -- function: RTS output
-    signal tb_usb_1_rts                : std_logic                    := '0';  -- function: CTS input
-    signal tb_usb_1_rx                 : std_logic;  -- function: TX data out
-    signal tb_usb_1_tx                 : std_logic                    := '0';  -- function: RX data in
-    --
-    --  27 MHz, oscillator socket
-    signal tb_user_clock               : std_logic                    := '0';
-    --
-    -- user clock provided per SMA
-    signal tb_user_sma_clock_p         : std_logic                    := '0';
-    signal tb_user_sma_clock_n         : std_logic                    := '0';
-
-
-
-begin
-
-    -- generate clocks
-    tb_sysclk_p   <= not tb_sysclk_p   after sys_clk_period / 2  when simulation_run;
-    tb_sysclk_n   <= not tb_sysclk_n   after sys_clk_period / 2  when simulation_run;
-    tb_user_clock <= not tb_user_clock after user_clk_period / 2 when simulation_run;
-
-    -- generate reset
-    tb_cpu_reset <= '1', '0' after 6.66 * sys_clk_period;
-
-    -- dut
-    top_i0 : entity work.top
-        port map (
-            stop_simulation          => tb_stop_simulation,        -- : out   std_logic;
-            --
-            cpu_reset                => tb_cpu_reset,              -- : in    std_logic;
-            --                                                     
-            -- DDR2 memory 128 MB                                  
-            ddr2_a                   => tb_ddr2_a,                 -- : out   std_logic_vector(12 downto 0);
-            ddr2_ba                  => tb_ddr2_ba,                -- : out   std_logic_vector(2 downto 0);
-            ddr2_cas_b               => tb_ddr2_cas_b,             -- : out   std_logic;
-            ddr2_ras_b               => tb_ddr2_ras_b,             -- : out   std_logic;
-            ddr2_we_b                => tb_ddr2_we_b,              -- : out   std_logic;
-            ddr2_cke                 => tb_ddr2_cke,               -- : out   std_logic;
-            ddr2_clk_n               => tb_ddr2_clk_n,             -- : out   std_logic; 
-            ddr2_clk_p               => tb_ddr2_clk_p,             -- : out   std_logic; 
-            ddr2_dq                  => tb_ddr2_dq,                -- : inout std_logic_vector(15 downto 0);
-            ddr2_ldm                 => tb_ddr2_ldm,               -- : out   std_logic;
-            ddr2_udm                 => tb_ddr2_udm,               -- : out   std_logic;
-            ddr2_ldqs_n              => tb_ddr2_ldqs_n,            -- : inout std_logic;
-            ddr2_ldqs_p              => tb_ddr2_ldqs_p,            -- : inout std_logic;
-            ddr2_udqs_n              => tb_ddr2_udqs_n,            -- : inout std_logic;
-            ddr2_udqs_p              => tb_ddr2_udqs_p,            -- : inout std_logic;
-            ddr2_odt                 => tb_ddr2_odt,               -- : out   std_logic;
-            --                                                     
-            -- flash memory                                        
-            flash_a                  => tb_flash_a,                -- : out   std_logic_vector(24 downto 0);
-            flash_d                  => tb_flash_d,                -- : inout std_logic_vector(7  downto 3);
-            --                              --
-            fpga_d0_din_miso_miso1   => tb_fpga_d0_din_miso_miso1, -- : inout std_logic;
-            fpga_d1_miso2            => tb_fpga_d1_miso2,          -- : inout std_logic;
-            fpga_d2_miso3            => tb_fpga_d2_miso3,          -- : inout std_logic;
-            flash_we_b               => tb_flash_we_b,             -- : out   std_logic;
-            flash_oe_b               => tb_flash_oe_b,             -- : out   std_logic;
-            flash_ce_b               => tb_flash_ce_b,             -- : out   std_logic;
-            --
-            -- FMC connector
-            -- M2C   Mezzanine to Carrier
-            -- C2M   Carrier to Mezzanine
-            fmc_clk0_m2c_n           => tb_fmc_clk0_m2c_n,         -- : in    std_logic;
-            fmc_clk0_m2c_p           => tb_fmc_clk0_m2c_p,         -- : in    std_logic;
-            fmc_clk1_m2c_n           => tb_fmc_clk1_m2c_n,         -- : in    std_logic;
-            fmc_clk1_m2c_p           => tb_fmc_clk1_m2c_p,         -- : in    std_logic;
-            iic_scl_main             => tb_iic_scl_main,           -- : inout std_logic;
-            iic_sda_main             => tb_iic_sda_main,           -- : inout std_logic;
-            fmc_la00_cc_n            => tb_fmc_la00_cc_n,          -- : inout std_logic;
-            fmc_la00_cc_p            => tb_fmc_la00_cc_p,          -- : inout std_logic;
-            fmc_la01_cc_n            => tb_fmc_la01_cc_n,          -- : inout std_logic;
-            fmc_la01_cc_p            => tb_fmc_la01_cc_p,          -- : inout std_logic;
-            fmc_la02_n               => tb_fmc_la02_n,             -- : inout std_logic;
-            fmc_la02_p               => tb_fmc_la02_p,             -- : inout std_logic;
-            fmc_la03_n               => tb_fmc_la03_n,             -- : inout std_logic;
-            fmc_la03_p               => tb_fmc_la03_p,             -- : inout std_logic;
-            fmc_la04_n               => tb_fmc_la04_n,             -- : inout std_logic;
-            fmc_la04_p               => tb_fmc_la04_p,             -- : inout std_logic;
-            fmc_la05_n               => tb_fmc_la05_n,             -- : inout std_logic;
-            fmc_la05_p               => tb_fmc_la05_p,             -- : inout std_logic;
-            fmc_la06_n               => tb_fmc_la06_n,             -- : inout std_logic;
-            fmc_la06_p               => tb_fmc_la06_p,             -- : inout std_logic;
-            fmc_la07_n               => tb_fmc_la07_n,             -- : inout std_logic;
-            fmc_la07_p               => tb_fmc_la07_p,             -- : inout std_logic;
-            fmc_la08_n               => tb_fmc_la08_n,             -- : inout std_logic;
-            fmc_la08_p               => tb_fmc_la08_p,             -- : inout std_logic;
-            fmc_la09_n               => tb_fmc_la09_n,             -- : inout std_logic;
-            fmc_la09_p               => tb_fmc_la09_p,             -- : inout std_logic;
-            fmc_la10_n               => tb_fmc_la10_n,             -- : inout std_logic;
-            fmc_la10_p               => tb_fmc_la10_p,             -- : inout std_logic;
-            fmc_la11_n               => tb_fmc_la11_n,             -- : inout std_logic;
-            fmc_la11_p               => tb_fmc_la11_p,             -- : inout std_logic;
-            fmc_la12_n               => tb_fmc_la12_n,             -- : inout std_logic;
-            fmc_la12_p               => tb_fmc_la12_p,             -- : inout std_logic;
-            fmc_la13_n               => tb_fmc_la13_n,             -- : inout std_logic;
-            fmc_la13_p               => tb_fmc_la13_p,             -- : inout std_logic;
-            fmc_la14_n               => tb_fmc_la14_n,             -- : inout std_logic;
-            fmc_la14_p               => tb_fmc_la14_p,             -- : inout std_logic;
-            fmc_la15_n               => tb_fmc_la15_n,             -- : inout std_logic;
-            fmc_la15_p               => tb_fmc_la15_p,             -- : inout std_logic;
-            fmc_la16_n               => tb_fmc_la16_n,             -- : inout std_logic;
-            fmc_la16_p               => tb_fmc_la16_p,             -- : inout std_logic;
-            fmc_la17_cc_n            => tb_fmc_la17_cc_n,          -- : inout std_logic;
-            fmc_la17_cc_p            => tb_fmc_la17_cc_p,          -- : inout std_logic;
-            fmc_la18_cc_n            => tb_fmc_la18_cc_n,          -- : inout std_logic;
-            fmc_la18_cc_p            => tb_fmc_la18_cc_p,          -- : inout std_logic;
-            fmc_la19_n               => tb_fmc_la19_n,             -- : inout std_logic;
-            fmc_la19_p               => tb_fmc_la19_p,             -- : inout std_logic;
-            fmc_la20_n               => tb_fmc_la20_n,             -- : inout std_logic;
-            fmc_la20_p               => tb_fmc_la20_p,             -- : inout std_logic;
-            fmc_la21_n               => tb_fmc_la21_n,             -- : inout std_logic;
-            fmc_la21_p               => tb_fmc_la21_p,             -- : inout std_logic;
-            fmc_la22_n               => tb_fmc_la22_n,             -- : inout std_logic;
-            fmc_la22_p               => tb_fmc_la22_p,             -- : inout std_logic;
-            fmc_la23_n               => tb_fmc_la23_n,             -- : inout std_logic;
-            fmc_la23_p               => tb_fmc_la23_p,             -- : inout std_logic;
-            fmc_la24_n               => tb_fmc_la24_n,             -- : inout std_logic;
-            fmc_la24_p               => tb_fmc_la24_p,             -- : inout std_logic;
-            fmc_la25_n               => tb_fmc_la25_n,             -- : inout std_logic;
-            fmc_la25_p               => tb_fmc_la25_p,             -- : inout std_logic;
-            fmc_la26_n               => tb_fmc_la26_n,             -- : inout std_logic;
-            fmc_la26_p               => tb_fmc_la26_p,             -- : inout std_logic;
-            fmc_la27_n               => tb_fmc_la27_n,             -- : inout std_logic;
-            fmc_la27_p               => tb_fmc_la27_p,             -- : inout std_logic;
-            fmc_la28_n               => tb_fmc_la28_n,             -- : inout std_logic;
-            fmc_la28_p               => tb_fmc_la28_p,             -- : inout std_logic;
-            fmc_la29_n               => tb_fmc_la29_n,             -- : inout std_logic;
-            fmc_la29_p               => tb_fmc_la29_p,             -- : inout std_logic;
-            fmc_la30_n               => tb_fmc_la30_n,             -- : inout std_logic;
-            fmc_la30_p               => tb_fmc_la30_p,             -- : inout std_logic;
-            fmc_la31_n               => tb_fmc_la31_n,             -- : inout std_logic;
-            fmc_la31_p               => tb_fmc_la31_p,             -- : inout std_logic;
-            fmc_la32_n               => tb_fmc_la32_n,             -- : inout std_logic;
-            fmc_la32_p               => tb_fmc_la32_p,             -- : inout std_logic;
-            fmc_la33_n               => tb_fmc_la33_n,             -- : inout std_logic;
-            fmc_la33_p               => tb_fmc_la33_p,             -- : inout std_logic;
-            fmc_prsnt_m2c_l          => tb_fmc_prsnt_m2c_l,        -- : in    std_logic;
-            fmc_pwr_good_flash_rst_b => tb_fmc_pwr_good_flash_rst_b,  -- : out   std_logic;
-            --
-            fpga_awake               => tb_fpga_awake,             -- : out   std_logic;
-            fpga_cclk                => tb_fpga_cclk,              -- : out   std_logic;
-            fpga_cmp_clk             => tb_fpga_cmp_clk,           -- : in    std_logic;
-            fpga_cmp_mosi            => tb_fpga_cmp_mosi,          -- : in    std_logic;
-            --                              --
-            fpga_hswapen             => tb_fpga_hswapen,           -- : in    std_logic;
-            fpga_init_b              => tb_fpga_init_b,            -- : out   std_logic;
-            fpga_m0_cmp_miso         => tb_fpga_m0_cmp_miso,       -- : in    std_logic;
-            fpga_m1                  => tb_fpga_m1,                -- : in    std_logic;
-            fpga_mosi_csi_b_miso0    => tb_fpga_mosi_csi_b_miso0,  -- : inout std_logic;
-            fpga_onchip_term1        => tb_fpga_onchip_term1,      -- : inout std_logic;
-            fpga_onchip_term2        => tb_fpga_onchip_term2,      -- : inout std_logic;
-            fpga_vtemp               => tb_fpga_vtemp,             -- : in    std_logic;
-            --
-            -- GPIOs
-            gpio_button              => tb_gpio_button,            -- : in    std_logic_vector(3 downto 0);
-            gpio_header_ls           => tb_gpio_header_ls,         -- : inout std_logic_vector(7 downto 0);
-            gpio_led                 => tb_gpio_led,               -- : out   std_logic_vector(3 downto 0);
-            gpio_switch              => tb_gpio_switch,            -- : in    std_logic_vector(3 downto 0);
-            --
-            -- Ethernet Gigabit PHY 
-            phy_col                  => tb_phy_col,                -- : in    std_logic;
-            phy_crs                  => tb_phy_crs,                -- : in    std_logic;
-            phy_int                  => tb_phy_int,                -- : in    std_logic;
-            phy_mdc                  => tb_phy_mdc,                -- : out   std_logic;
-            phy_mdio                 => tb_phy_mdio,               -- : inout std_logic;
-            phy_reset                => tb_phy_reset,              -- : out   std_logic;
-            phy_rxclk                => tb_phy_rxclk,              -- : in    std_logic;
-            phy_rxctl_rxdv           => tb_phy_rxctl_rxdv,         -- : in    std_logic;
-            phy_rxd                  => tb_phy_rxd,                -- : in    std_logic_vector(7 downto 0);
-            phy_rxer                 => tb_phy_rxer,               -- : in    std_logic;
-            phy_txclk                => tb_phy_txclk,              -- : in    std_logic;
-            phy_txctl_txen           => tb_phy_txctl_txen,         -- : out   std_logic;
-            phy_txc_gtxclk           => tb_phy_txc_gtxclk,         -- : out   std_logic;
-            phy_txd                  => tb_phy_txd,                -- : out   std_logic_vector(7 downto 0);
-            phy_txer                 => tb_phy_txer,               -- : out   std_logic;
-            --
-            --
-            spi_cs_b                 => tb_spi_cs_b,               -- : out   std_logic;
-            --                                                     
-            -- 200 MHz oscillator, jitter 50 ppm                   
-            sysclk_n                 => tb_sysclk_n,               -- : in    std_logic;
-            sysclk_p                 => tb_sysclk_p,               -- : in    std_logic;
-            --
-            -- RS232 via USB
-            usb_1_cts                => tb_usb_1_cts,              -- : out   std_logic;
-            usb_1_rts                => tb_usb_1_rts,              -- : in    std_logic;
-            usb_1_rx                 => tb_usb_1_rx,               -- : out   std_logic;
-            usb_1_tx                 => tb_usb_1_tx,               -- : in    std_logic;
-            --
-            --  27 MHz, oscillator socket
-            user_clock               => tb_user_clock,             -- : in    std_logic;
-            --
-            -- user clock provided per SMA
-            user_sma_clock_p         => tb_user_sma_clock_p,       -- : in    std_logic;
-            user_sma_clock_n         => tb_user_sma_clock_n        -- : in    std_logic
-            );
-
-
-    -- check for simulation stopping
-    process (tb_stop_simulation)
-    begin
-        if tb_stop_simulation = '1' then
-            report "Simulation end." severity note;
-            simulation_run <= false;
-        end if;
-    end process;
-
-
-end architecture testbench;
-
+-- testbench for
+-- SP601 evaluation board
+--
+-- includes "model" for clock generation
+-- simulate press on cpu_reset as reset
+--
+-- place models for external components (PHY, DDR2) in this file
+--
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity top_tb is
+end entity top_tb;
+
+architecture testbench of top_tb is
+
+    ---------------------------
+    -- constant declarations
+    constant sys_clk_period  : time := 1 sec / 200_000_000;  -- 200 MHz
+    constant user_clk_period : time := 1 sec / 27_000_000;   -- 27 MHz
+
+
+    ---------------------------
+    -- signal declarations
+    signal simulation_run              : boolean                      := true;
+    signal tb_stop_simulation          : std_logic;
+    --
+    signal tb_cpu_reset                : std_logic;  -- SW9 pushbutton (active-high)
+    --
+    -- DDR2 memory 128 MB
+    signal tb_ddr2_a                   : std_logic_vector(12 downto 0);
+    signal tb_ddr2_ba                  : std_logic_vector(2 downto 0);
+    signal tb_ddr2_cas_b               : std_logic;
+    signal tb_ddr2_ras_b               : std_logic;
+    signal tb_ddr2_we_b                : std_logic;
+    signal tb_ddr2_cke                 : std_logic;
+    signal tb_ddr2_clk_n               : std_logic;
+    signal tb_ddr2_clk_p               : std_logic;
+    signal tb_ddr2_dq                  : std_logic_vector(15 downto 0);
+    signal tb_ddr2_ldm                 : std_logic;
+    signal tb_ddr2_udm                 : std_logic;
+    signal tb_ddr2_ldqs_n              : std_logic;
+    signal tb_ddr2_ldqs_p              : std_logic;
+    signal tb_ddr2_udqs_n              : std_logic;
+    signal tb_ddr2_udqs_p              : std_logic;
+    signal tb_ddr2_odt                 : std_logic;
+    --                                
+    -- flash memory                        
+    signal tb_flash_a                  : std_logic_vector(24 downto 0);
+    signal tb_flash_d                  : std_logic_vector(7 downto 3);
+    signal tb_fpga_d0_din_miso_miso1   : std_logic;  -- dual use
+    signal tb_fpga_d1_miso2            : std_logic;  -- dual use
+    signal tb_fpga_d2_miso3            : std_logic;  -- dual use
+    signal tb_flash_we_b               : std_logic;
+    signal tb_flash_oe_b               : std_logic;
+    signal tb_flash_ce_b               : std_logic;
+    --
+    -- FMC connector
+    -- M2C   Mezzanine to Carrier
+    -- C2M   Carrier to Mezzanine
+    signal tb_fmc_clk0_m2c_n           : std_logic                    := '1';
+    signal tb_fmc_clk0_m2c_p           : std_logic                    := '0';
+    signal tb_fmc_clk1_m2c_n           : std_logic                    := '1';
+    signal tb_fmc_clk1_m2c_p           : std_logic                    := '0';
+    -- IIC addresses:
+    -- M24C08:                 1010100..1010111
+    -- 2kb EEPROM on FMC card: 1010010
+    signal tb_iic_scl_main             : std_logic;
+    signal tb_iic_sda_main             : std_logic;
+    signal tb_fmc_la00_cc_n            : std_logic;
+    signal tb_fmc_la00_cc_p            : std_logic;
+    signal tb_fmc_la01_cc_n            : std_logic;
+    signal tb_fmc_la01_cc_p            : std_logic;
+    signal tb_fmc_la02_n               : std_logic;
+    signal tb_fmc_la02_p               : std_logic;
+    signal tb_fmc_la03_n               : std_logic;
+    signal tb_fmc_la03_p               : std_logic;
+    signal tb_fmc_la04_n               : std_logic;
+    signal tb_fmc_la04_p               : std_logic;
+    signal tb_fmc_la05_n               : std_logic;
+    signal tb_fmc_la05_p               : std_logic;
+    signal tb_fmc_la06_n               : std_logic;
+    signal tb_fmc_la06_p               : std_logic;
+    signal tb_fmc_la07_n               : std_logic;
+    signal tb_fmc_la07_p               : std_logic;
+    signal tb_fmc_la08_n               : std_logic;
+    signal tb_fmc_la08_p               : std_logic;
+    signal tb_fmc_la09_n               : std_logic;
+    signal tb_fmc_la09_p               : std_logic;
+    signal tb_fmc_la10_n               : std_logic;
+    signal tb_fmc_la10_p               : std_logic;
+    signal tb_fmc_la11_n               : std_logic;
+    signal tb_fmc_la11_p               : std_logic;
+    signal tb_fmc_la12_n               : std_logic;
+    signal tb_fmc_la12_p               : std_logic;
+    signal tb_fmc_la13_n               : std_logic;
+    signal tb_fmc_la13_p               : std_logic;
+    signal tb_fmc_la14_n               : std_logic;
+    signal tb_fmc_la14_p               : std_logic;
+    signal tb_fmc_la15_n               : std_logic;
+    signal tb_fmc_la15_p               : std_logic;
+    signal tb_fmc_la16_n               : std_logic;
+    signal tb_fmc_la16_p               : std_logic;
+    signal tb_fmc_la17_cc_n            : std_logic;
+    signal tb_fmc_la17_cc_p            : std_logic;
+    signal tb_fmc_la18_cc_n            : std_logic;
+    signal tb_fmc_la18_cc_p            : std_logic;
+    signal tb_fmc_la19_n               : std_logic;
+    signal tb_fmc_la19_p               : std_logic;
+    signal tb_fmc_la20_n               : std_logic;
+    signal tb_fmc_la20_p               : std_logic;
+    signal tb_fmc_la21_n               : std_logic;
+    signal tb_fmc_la21_p               : std_logic;
+    signal tb_fmc_la22_n               : std_logic;
+    signal tb_fmc_la22_p               : std_logic;
+    signal tb_fmc_la23_n               : std_logic;
+    signal tb_fmc_la23_p               : std_logic;
+    signal tb_fmc_la24_n               : std_logic;
+    signal tb_fmc_la24_p               : std_logic;
+    signal tb_fmc_la25_n               : std_logic;
+    signal tb_fmc_la25_p               : std_logic;
+    signal tb_fmc_la26_n               : std_logic;
+    signal tb_fmc_la26_p               : std_logic;
+    signal tb_fmc_la27_n               : std_logic;
+    signal tb_fmc_la27_p               : std_logic;
+    signal tb_fmc_la28_n               : std_logic;
+    signal tb_fmc_la28_p               : std_logic;
+    signal tb_fmc_la29_n               : std_logic;
+    signal tb_fmc_la29_p               : std_logic;
+    signal tb_fmc_la30_n               : std_logic;
+    signal tb_fmc_la30_p               : std_logic;
+    signal tb_fmc_la31_n               : std_logic;
+    signal tb_fmc_la31_p               : std_logic;
+    signal tb_fmc_la32_n               : std_logic;
+    signal tb_fmc_la32_p               : std_logic;
+    signal tb_fmc_la33_n               : std_logic;
+    signal tb_fmc_la33_p               : std_logic;
+    signal tb_fmc_prsnt_m2c_l          : std_logic                    := '0';
+    signal tb_fmc_pwr_good_flash_rst_b : std_logic;  -- multiple destinations: 1 of Q2 (LED DS1 driver), U1 AB2 FPGA_PROG (through series R260 DNP), 44 of U25
+    --
+    signal tb_fpga_awake               : std_logic;
+    signal tb_fpga_cclk                : std_logic;
+    signal tb_fpga_cmp_clk             : std_logic                    := '0';
+    signal tb_fpga_cmp_mosi            : std_logic                    := '0';
+    signal tb_fpga_hswapen             : std_logic                    := '0';
+    signal tb_fpga_init_b              : std_logic;  -- low active
+    signal tb_fpga_m0_cmp_miso         : std_logic                    := '0';  -- mode DIP switch SW1 active high
+    signal tb_fpga_m1                  : std_logic                    := '0';  -- mode DIP switch SW1 active high
+    signal tb_fpga_mosi_csi_b_miso0    : std_logic;
+    signal tb_fpga_onchip_term1        : std_logic;
+    signal tb_fpga_onchip_term2        : std_logic;
+    signal tb_fpga_vtemp               : std_logic                    := '0';
+    --
+    -- GPIOs
+    signal tb_gpio_button              : std_logic_vector(3 downto 0) := (others => '0');  -- active high
+    signal tb_gpio_header_ls           : std_logic_vector(7 downto 0);  -- 
+    signal tb_gpio_led                 : std_logic_vector(3 downto 0);
+    signal tb_gpio_switch              : std_logic_vector(3 downto 0) := (others => '0');  -- active high
+    --
+    -- Ethernet Gigabit PHY 
+    signal tb_phy_col                  : std_logic                    := '0';
+    signal tb_phy_crs                  : std_logic                    := '0';
+    signal tb_phy_int                  : std_logic                    := '0';
+    signal tb_phy_mdc                  : std_logic;
+    signal tb_phy_mdio                 : std_logic;
+    signal tb_phy_reset                : std_logic;
+    signal tb_phy_rxclk                : std_logic                    := '0';
+    signal tb_phy_rxctl_rxdv           : std_logic                    := '0';
+    signal tb_phy_rxd                  : std_logic_vector(7 downto 0);
+    signal tb_phy_rxer                 : std_logic                    := '0';
+    signal tb_phy_txclk                : std_logic                    := '0';
+    signal tb_phy_txctl_txen           : std_logic;
+    signal tb_phy_txc_gtxclk           : std_logic;
+    signal tb_phy_txd                  : std_logic_vector(7 downto 0);
+    signal tb_phy_txer                 : std_logic;
+    --
+    --
+    signal tb_spi_cs_b                 : std_logic;
+    --
+    -- 200 MHz oscillator, jitter 50 ppm
+    signal tb_sysclk_n                 : std_logic                    := '1';
+    signal tb_sysclk_p                 : std_logic                    := '0';
+    --
+    -- RS232 via USB
+    signal tb_usb_1_cts                : std_logic;  -- function: RTS output
+    signal tb_usb_1_rts                : std_logic                    := '0';  -- function: CTS input
+    signal tb_usb_1_rx                 : std_logic;  -- function: TX data out
+    signal tb_usb_1_tx                 : std_logic                    := '0';  -- function: RX data in
+    --
+    --  27 MHz, oscillator socket
+    signal tb_user_clock               : std_logic                    := '0';
+    --
+    -- user clock provided per SMA
+    signal tb_user_sma_clock_p         : std_logic                    := '0';
+    signal tb_user_sma_clock_n         : std_logic                    := '0';
+
+
+
+begin
+
+    -- generate clocks
+    tb_sysclk_p   <= not tb_sysclk_p   after sys_clk_period / 2  when simulation_run;
+    tb_sysclk_n   <= not tb_sysclk_n   after sys_clk_period / 2  when simulation_run;
+    tb_user_clock <= not tb_user_clock after user_clk_period / 2 when simulation_run;
+
+    -- generate reset
+    tb_cpu_reset <= '1', '0' after 6.66 * sys_clk_period;
+
+
+    -- simulate keypress
+    tb_gpio_button(2) <= '0', '1' after 50 us, '0' after 52 us;
+
+    -- dut
+    top_i0 : entity work.top
+        port map (
+            stop_simulation          => tb_stop_simulation,        -- : out   std_logic;
+            --
+            cpu_reset                => tb_cpu_reset,              -- : in    std_logic;
+            --                                                     
+            -- DDR2 memory 128 MB                                  
+            ddr2_a                   => tb_ddr2_a,                 -- : out   std_logic_vector(12 downto 0);
+            ddr2_ba                  => tb_ddr2_ba,                -- : out   std_logic_vector(2 downto 0);
+            ddr2_cas_b               => tb_ddr2_cas_b,             -- : out   std_logic;
+            ddr2_ras_b               => tb_ddr2_ras_b,             -- : out   std_logic;
+            ddr2_we_b                => tb_ddr2_we_b,              -- : out   std_logic;
+            ddr2_cke                 => tb_ddr2_cke,               -- : out   std_logic;
+            ddr2_clk_n               => tb_ddr2_clk_n,             -- : out   std_logic; 
+            ddr2_clk_p               => tb_ddr2_clk_p,             -- : out   std_logic; 
+            ddr2_dq                  => tb_ddr2_dq,                -- : inout std_logic_vector(15 downto 0);
+            ddr2_ldm                 => tb_ddr2_ldm,               -- : out   std_logic;
+            ddr2_udm                 => tb_ddr2_udm,               -- : out   std_logic;
+            ddr2_ldqs_n              => tb_ddr2_ldqs_n,            -- : inout std_logic;
+            ddr2_ldqs_p              => tb_ddr2_ldqs_p,            -- : inout std_logic;
+            ddr2_udqs_n              => tb_ddr2_udqs_n,            -- : inout std_logic;
+            ddr2_udqs_p              => tb_ddr2_udqs_p,            -- : inout std_logic;
+            ddr2_odt                 => tb_ddr2_odt,               -- : out   std_logic;
+            --                                                     
+            -- flash memory                                        
+            flash_a                  => tb_flash_a,                -- : out   std_logic_vector(24 downto 0);
+            flash_d                  => tb_flash_d,                -- : inout std_logic_vector(7  downto 3);
+            --                              --
+            fpga_d0_din_miso_miso1   => tb_fpga_d0_din_miso_miso1, -- : inout std_logic;
+            fpga_d1_miso2            => tb_fpga_d1_miso2,          -- : inout std_logic;
+            fpga_d2_miso3            => tb_fpga_d2_miso3,          -- : inout std_logic;
+            flash_we_b               => tb_flash_we_b,             -- : out   std_logic;
+            flash_oe_b               => tb_flash_oe_b,             -- : out   std_logic;
+            flash_ce_b               => tb_flash_ce_b,             -- : out   std_logic;
+            --
+            -- FMC connector
+            -- M2C   Mezzanine to Carrier
+            -- C2M   Carrier to Mezzanine
+            fmc_clk0_m2c_n           => tb_fmc_clk0_m2c_n,         -- : in    std_logic;
+            fmc_clk0_m2c_p           => tb_fmc_clk0_m2c_p,         -- : in    std_logic;
+            fmc_clk1_m2c_n           => tb_fmc_clk1_m2c_n,         -- : in    std_logic;
+            fmc_clk1_m2c_p           => tb_fmc_clk1_m2c_p,         -- : in    std_logic;
+            iic_scl_main             => tb_iic_scl_main,           -- : inout std_logic;
+            iic_sda_main             => tb_iic_sda_main,           -- : inout std_logic;
+            fmc_la00_cc_n            => tb_fmc_la00_cc_n,          -- : inout std_logic;
+            fmc_la00_cc_p            => tb_fmc_la00_cc_p,          -- : inout std_logic;
+            fmc_la01_cc_n            => tb_fmc_la01_cc_n,          -- : inout std_logic;
+            fmc_la01_cc_p            => tb_fmc_la01_cc_p,          -- : inout std_logic;
+            fmc_la02_n               => tb_fmc_la02_n,             -- : inout std_logic;
+            fmc_la02_p               => tb_fmc_la02_p,             -- : inout std_logic;
+            fmc_la03_n               => tb_fmc_la03_n,             -- : inout std_logic;
+            fmc_la03_p               => tb_fmc_la03_p,             -- : inout std_logic;
+            fmc_la04_n               => tb_fmc_la04_n,             -- : inout std_logic;
+            fmc_la04_p               => tb_fmc_la04_p,             -- : inout std_logic;
+            fmc_la05_n               => tb_fmc_la05_n,             -- : inout std_logic;
+            fmc_la05_p               => tb_fmc_la05_p,             -- : inout std_logic;
+            fmc_la06_n               => tb_fmc_la06_n,             -- : inout std_logic;
+            fmc_la06_p               => tb_fmc_la06_p,             -- : inout std_logic;
+            fmc_la07_n               => tb_fmc_la07_n,             -- : inout std_logic;
+            fmc_la07_p               => tb_fmc_la07_p,             -- : inout std_logic;
+            fmc_la08_n               => tb_fmc_la08_n,             -- : inout std_logic;
+            fmc_la08_p               => tb_fmc_la08_p,             -- : inout std_logic;
+            fmc_la09_n               => tb_fmc_la09_n,             -- : inout std_logic;
+            fmc_la09_p               => tb_fmc_la09_p,             -- : inout std_logic;
+            fmc_la10_n               => tb_fmc_la10_n,             -- : inout std_logic;
+            fmc_la10_p               => tb_fmc_la10_p,             -- : inout std_logic;
+            fmc_la11_n               => tb_fmc_la11_n,             -- : inout std_logic;
+            fmc_la11_p               => tb_fmc_la11_p,             -- : inout std_logic;
+            fmc_la12_n               => tb_fmc_la12_n,             -- : inout std_logic;
+            fmc_la12_p               => tb_fmc_la12_p,             -- : inout std_logic;
+            fmc_la13_n               => tb_fmc_la13_n,             -- : inout std_logic;
+            fmc_la13_p               => tb_fmc_la13_p,             -- : inout std_logic;
+            fmc_la14_n               => tb_fmc_la14_n,             -- : inout std_logic;
+            fmc_la14_p               => tb_fmc_la14_p,             -- : inout std_logic;
+            fmc_la15_n               => tb_fmc_la15_n,             -- : inout std_logic;
+            fmc_la15_p               => tb_fmc_la15_p,             -- : inout std_logic;
+            fmc_la16_n               => tb_fmc_la16_n,             -- : inout std_logic;
+            fmc_la16_p               => tb_fmc_la16_p,             -- : inout std_logic;
+            fmc_la17_cc_n            => tb_fmc_la17_cc_n,          -- : inout std_logic;
+            fmc_la17_cc_p            => tb_fmc_la17_cc_p,          -- : inout std_logic;
+            fmc_la18_cc_n            => tb_fmc_la18_cc_n,          -- : inout std_logic;
+            fmc_la18_cc_p            => tb_fmc_la18_cc_p,          -- : inout std_logic;
+            fmc_la19_n               => tb_fmc_la19_n,             -- : inout std_logic;
+            fmc_la19_p               => tb_fmc_la19_p,             -- : inout std_logic;
+            fmc_la20_n               => tb_fmc_la20_n,             -- : inout std_logic;
+            fmc_la20_p               => tb_fmc_la20_p,             -- : inout std_logic;
+            fmc_la21_n               => tb_fmc_la21_n,             -- : inout std_logic;
+            fmc_la21_p               => tb_fmc_la21_p,             -- : inout std_logic;
+            fmc_la22_n               => tb_fmc_la22_n,             -- : inout std_logic;
+            fmc_la22_p               => tb_fmc_la22_p,             -- : inout std_logic;
+            fmc_la23_n               => tb_fmc_la23_n,             -- : inout std_logic;
+            fmc_la23_p               => tb_fmc_la23_p,             -- : inout std_logic;
+            fmc_la24_n               => tb_fmc_la24_n,             -- : inout std_logic;
+            fmc_la24_p               => tb_fmc_la24_p,             -- : inout std_logic;
+            fmc_la25_n               => tb_fmc_la25_n,             -- : inout std_logic;
+            fmc_la25_p               => tb_fmc_la25_p,             -- : inout std_logic;
+            fmc_la26_n               => tb_fmc_la26_n,             -- : inout std_logic;
+            fmc_la26_p               => tb_fmc_la26_p,             -- : inout std_logic;
+            fmc_la27_n               => tb_fmc_la27_n,             -- : inout std_logic;
+            fmc_la27_p               => tb_fmc_la27_p,             -- : inout std_logic;
+            fmc_la28_n               => tb_fmc_la28_n,             -- : inout std_logic;
+            fmc_la28_p               => tb_fmc_la28_p,             -- : inout std_logic;
+            fmc_la29_n               => tb_fmc_la29_n,             -- : inout std_logic;
+            fmc_la29_p               => tb_fmc_la29_p,             -- : inout std_logic;
+            fmc_la30_n               => tb_fmc_la30_n,             -- : inout std_logic;
+            fmc_la30_p               => tb_fmc_la30_p,             -- : inout std_logic;
+            fmc_la31_n               => tb_fmc_la31_n,             -- : inout std_logic;
+            fmc_la31_p               => tb_fmc_la31_p,             -- : inout std_logic;
+            fmc_la32_n               => tb_fmc_la32_n,             -- : inout std_logic;
+            fmc_la32_p               => tb_fmc_la32_p,             -- : inout std_logic;
+            fmc_la33_n               => tb_fmc_la33_n,             -- : inout std_logic;
+            fmc_la33_p               => tb_fmc_la33_p,             -- : inout std_logic;
+            fmc_prsnt_m2c_l          => tb_fmc_prsnt_m2c_l,        -- : in    std_logic;
+            fmc_pwr_good_flash_rst_b => tb_fmc_pwr_good_flash_rst_b,  -- : out   std_logic;
+            --
+            fpga_awake               => tb_fpga_awake,             -- : out   std_logic;
+            fpga_cclk                => tb_fpga_cclk,              -- : out   std_logic;
+            fpga_cmp_clk             => tb_fpga_cmp_clk,           -- : in    std_logic;
+            fpga_cmp_mosi            => tb_fpga_cmp_mosi,          -- : in    std_logic;
+            --                              --
+            fpga_hswapen             => tb_fpga_hswapen,           -- : in    std_logic;
+            fpga_init_b              => tb_fpga_init_b,            -- : out   std_logic;
+            fpga_m0_cmp_miso         => tb_fpga_m0_cmp_miso,       -- : in    std_logic;
+            fpga_m1                  => tb_fpga_m1,                -- : in    std_logic;
+            fpga_mosi_csi_b_miso0    => tb_fpga_mosi_csi_b_miso0,  -- : inout std_logic;
+            fpga_onchip_term1        => tb_fpga_onchip_term1,      -- : inout std_logic;
+            fpga_onchip_term2        => tb_fpga_onchip_term2,      -- : inout std_logic;
+            fpga_vtemp               => tb_fpga_vtemp,             -- : in    std_logic;
+            --
+            -- GPIOs
+            gpio_button              => tb_gpio_button,            -- : in    std_logic_vector(3 downto 0);
+            gpio_header_ls           => tb_gpio_header_ls,         -- : inout std_logic_vector(7 downto 0);
+            gpio_led                 => tb_gpio_led,               -- : out   std_logic_vector(3 downto 0);
+            gpio_switch              => tb_gpio_switch,            -- : in    std_logic_vector(3 downto 0);
+            --
+            -- Ethernet Gigabit PHY 
+            phy_col                  => tb_phy_col,                -- : in    std_logic;
+            phy_crs                  => tb_phy_crs,                -- : in    std_logic;
+            phy_int                  => tb_phy_int,                -- : in    std_logic;
+            phy_mdc                  => tb_phy_mdc,                -- : out   std_logic;
+            phy_mdio                 => tb_phy_mdio,               -- : inout std_logic;
+            phy_reset                => tb_phy_reset,              -- : out   std_logic;
+            phy_rxclk                => tb_phy_rxclk,              -- : in    std_logic;
+            phy_rxctl_rxdv           => tb_phy_rxctl_rxdv,         -- : in    std_logic;
+            phy_rxd                  => tb_phy_rxd,                -- : in    std_logic_vector(7 downto 0);
+            phy_rxer                 => tb_phy_rxer,               -- : in    std_logic;
+            phy_txclk                => tb_phy_txclk,              -- : in    std_logic;
+            phy_txctl_txen           => tb_phy_txctl_txen,         -- : out   std_logic;
+            phy_txc_gtxclk           => tb_phy_txc_gtxclk,         -- : out   std_logic;
+            phy_txd                  => tb_phy_txd,                -- : out   std_logic_vector(7 downto 0);
+            phy_txer                 => tb_phy_txer,               -- : out   std_logic;
+            --
+            --
+            spi_cs_b                 => tb_spi_cs_b,               -- : out   std_logic;
+            --                                                     
+            -- 200 MHz oscillator, jitter 50 ppm                   
+            sysclk_n                 => tb_sysclk_n,               -- : in    std_logic;
+            sysclk_p                 => tb_sysclk_p,               -- : in    std_logic;
+            --
+            -- RS232 via USB
+            usb_1_cts                => tb_usb_1_cts,              -- : out   std_logic;
+            usb_1_rts                => tb_usb_1_rts,              -- : in    std_logic;
+            usb_1_rx                 => tb_usb_1_rx,               -- : out   std_logic;
+            usb_1_tx                 => tb_usb_1_tx,               -- : in    std_logic;
+            --
+            --  27 MHz, oscillator socket
+            user_clock               => tb_user_clock,             -- : in    std_logic;
+            --
+            -- user clock provided per SMA
+            user_sma_clock_p         => tb_user_sma_clock_p,       -- : in    std_logic;
+            user_sma_clock_n         => tb_user_sma_clock_n        -- : in    std_logic
+            );
+
+
+    -- check for simulation stopping
+    process (tb_stop_simulation)
+    begin
+        if tb_stop_simulation = '1' then
+            report "Simulation end." severity note;
+            simulation_run <= false;
+        end if;
+    end process;
+
+
+end architecture testbench;
+
diff --git a/zpu/hdl/zealot/helpers/zpu_med1.vhdl b/zpu/hdl/zealot/helpers/zpu_med1.vhdl
index fb19e0c..a0cbcb2 100644
--- a/zpu/hdl/zealot/helpers/zpu_med1.vhdl
+++ b/zpu/hdl/zealot/helpers/zpu_med1.vhdl
@@ -67,7 +67,11 @@ entity ZPU_Med1 is
       break_o    : out std_logic;  -- Break executed
       dbg_o      : out zpu_dbgo_t; -- Debug info
       rs232_tx_o : out std_logic;  -- UART Tx
-      rs232_rx_i : in  std_logic); -- UART Rx
+      rs232_rx_i : in  std_logic;  -- UART Rx
+      gpio_in    : in  std_logic_vector(31 downto 0);
+      gpio_out   : out std_logic_vector(31 downto 0);
+      gpio_dir   : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
+      );
 end entity ZPU_Med1;
 
 architecture Structural of ZPU_Med1 is
@@ -114,12 +118,25 @@ begin
    -- I/O: Phi layout
    io_map: ZPUPhiIO
       generic map(
-         BRDIVISOR => BRDIVISOR, LOG_FILE => "zpu_med1_io.log")
+         BRDIVISOR => BRDIVISOR, 
+         LOG_FILE  => "zpu_med1_io.log"
+         )
       port map(
-         clk_i => clk_i, reset_i => rst_i, busy_o => io_busy, we_i => io_we,
-         re_i => io_re, data_i => mem_write, data_o => io_read,
-         addr_i => io_addr, rs232_rx_i => rs232_rx_i, rs232_tx_o => rs232_tx_o,
-         br_clk_i => '1');
+         clk_i      => clk_i, 
+         reset_i    => rst_i, 
+         busy_o     => io_busy, 
+         we_i       => io_we,
+         re_i       => io_re, 
+         data_i     => mem_write, 
+         data_o     => io_read,
+         addr_i     => io_addr, 
+         rs232_rx_i => rs232_rx_i, 
+         rs232_tx_o => rs232_tx_o,
+         br_clk_i   => '1',
+         gpio_in    => gpio_in,
+         gpio_out   => gpio_out,
+         gpio_dir   => gpio_dir
+         );
    io_addr  <= mem_addr(4 downto 2);
    -- Here we decode 0x8xxxx as I/O and not just 0x80A00xx
    -- Note: We define the address space as 256 kB, so writing to 0x80A00xx
diff --git a/zpu/hdl/zealot/helpers/zpu_small1.vhdl b/zpu/hdl/zealot/helpers/zpu_small1.vhdl
index 13dd485..52006e4 100644
--- a/zpu/hdl/zealot/helpers/zpu_small1.vhdl
+++ b/zpu/hdl/zealot/helpers/zpu_small1.vhdl
@@ -67,7 +67,11 @@ entity ZPU_Small1 is
       break_o    : out std_logic;  -- Break executed
       dbg_o      : out zpu_dbgo_t; -- Debug info
       rs232_tx_o : out std_logic;  -- UART Tx
-      rs232_rx_i : in  std_logic); -- UART Rx
+      rs232_rx_i : in  std_logic;  -- UART Rx
+      gpio_in    : in  std_logic_vector(31 downto 0);
+      gpio_out   : out std_logic_vector(31 downto 0);
+      gpio_dir   : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
+      );
 end entity ZPU_Small1;
 
 architecture Structural of ZPU_Small1 is
@@ -111,12 +115,25 @@ begin
    -- I/O: Phi layout
    io_map: ZPUPhiIO
       generic map(
-         BRDIVISOR => BRDIVISOR, LOG_FILE => "zpu_small1_io.log")
+         BRDIVISOR => BRDIVISOR, 
+         LOG_FILE  => "zpu_small1_io.log"
+         )
       port map(
-         clk_i => clk_i, reset_i => rst_i, busy_o => io_busy, we_i => io_we,
-         re_i => io_re, data_i => io_write, data_o => io_read,
-         addr_i => phi_addr, rs232_rx_i => rs232_rx_i, rs232_tx_o => rs232_tx_o,
-         br_clk_i => '1');
+         clk_i      => clk_i, 
+         reset_i    => rst_i, 
+         busy_o     => io_busy, 
+         we_i       => io_we,
+         re_i       => io_re, 
+         data_i     => io_write, 
+         data_o     => io_read,
+         addr_i     => phi_addr, 
+         rs232_rx_i => rs232_rx_i, 
+         rs232_tx_o => rs232_tx_o,
+         br_clk_i   => '1',
+         gpio_in    => gpio_in,
+         gpio_out   => gpio_out,
+         gpio_dir   => gpio_dir
+         );
    phi_addr <= io_addr(4 downto 2);
 
    zpu : ZPUSmallCore
diff --git a/zpu/hdl/zealot/testbenches/dmips_med1_tb.vhdl b/zpu/hdl/zealot/testbenches/dmips_med1_tb.vhdl
index 4361b9c..8bdcdd3 100644
--- a/zpu/hdl/zealot/testbenches/dmips_med1_tb.vhdl
+++ b/zpu/hdl/zealot/testbenches/dmips_med1_tb.vhdl
@@ -80,7 +80,11 @@ architecture Behave of DMIPS_Med1_TB is
          break_o    : out std_logic;  -- Break executed
          dbg_o      : out zpu_dbgo_t; -- Debug info
          rs232_tx_o : out std_logic;  -- UART Tx
-         rs232_rx_i : in  std_logic); -- UART Rx
+         rs232_rx_i : in  std_logic;  -- UART Rx
+         gpio_in    : in  std_logic_vector(31 downto 0);
+         gpio_out   : out std_logic_vector(31 downto 0);
+         gpio_dir   : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
+         );
    end component ZPU_Med1;
 
    signal clk          : std_logic;
@@ -98,7 +102,8 @@ begin
          BRAM_W => BRAM_W)
       port map(
          clk_i => clk, rst_i => reset, rs232_tx_o => rs232_tx,
-         rs232_rx_i => rs232_rx, break_o => break, dbg_o => dbg);
+         rs232_rx_i => rs232_rx, break_o => break, dbg_o => dbg,
+         gpio_in => (others => '0'));
 
    trace_mod : Trace
       generic map(
diff --git a/zpu/hdl/zealot/testbenches/small1_tb.vhdl b/zpu/hdl/zealot/testbenches/small1_tb.vhdl
index bada24b..a77e5bc 100644
--- a/zpu/hdl/zealot/testbenches/small1_tb.vhdl
+++ b/zpu/hdl/zealot/testbenches/small1_tb.vhdl
@@ -80,7 +80,11 @@ architecture Behave of Small1_TB is
          break_o    : out std_logic;  -- Break executed
          dbg_o      : out zpu_dbgo_t; -- Debug info
          rs232_tx_o : out std_logic;  -- UART Tx
-         rs232_rx_i : in  std_logic); -- UART Rx
+         rs232_rx_i : in  std_logic;  -- UART Rx
+         gpio_in    : in  std_logic_vector(31 downto 0);
+         gpio_out   : out std_logic_vector(31 downto 0);
+         gpio_dir   : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
+         );
    end component ZPU_Small1;
 
    signal clk          : std_logic;
@@ -98,7 +102,8 @@ begin
          BRAM_W => BRAM_W)
       port map(
          clk_i => clk, rst_i => reset, rs232_tx_o => rs232_tx,
-         rs232_rx_i => rs232_rx, break_o => break, dbg_o => dbg);
+         rs232_rx_i => rs232_rx, break_o => break, dbg_o => dbg,
+         gpio_in => (others => '0'));
 
    trace_mod : Trace
       generic map(
diff --git a/zpu/hdl/zealot/zpu_pkg.vhdl b/zpu/hdl/zealot/zpu_pkg.vhdl
index 2a15880..915f352 100644
--- a/zpu/hdl/zealot/zpu_pkg.vhdl
+++ b/zpu/hdl/zealot/zpu_pkg.vhdl
@@ -140,6 +140,23 @@ package zpupkg is
          data_o   : out unsigned(31 downto 0));
    end component Timer;
 
+   component gpio is
+      port(
+         clk_i    : in  std_logic;
+         reset_i  : in  std_logic;
+         --
+         we_i     : in  std_logic;
+         data_i   : in  unsigned(31 downto 0);
+         addr_i   : in  unsigned( 0 downto 0);
+         data_o   : out unsigned(31 downto 0);
+         --
+         port_in  : in  std_logic_vector(31 downto 0);
+         port_out : out std_logic_vector(31 downto 0);
+         port_dir : out std_logic_vector(31 downto 0)
+         );
+   end component gpio;
+
+
    component ZPUPhiIO is
       generic(
          BRDIVISOR : positive:=1;   -- Baud rate divisor i.e. br_clk/9600/4
@@ -153,10 +170,16 @@ package zpupkg is
          re_i       : in  std_logic; -- Read Enable
          data_i     : in  unsigned(31 downto 0);
          data_o     : out unsigned(31 downto 0);
-         addr_i     : in  unsigned(2 downto 0); -- Address bits 4-2
+         addr_i     : in  unsigned(2  downto 0); -- Address bits 4-2
+         --
          rs232_rx_i : in  std_logic;  -- UART Rx input
          rs232_tx_o : out std_logic;  -- UART Tx output
-         br_clk_i   : in  std_logic); -- UART base clock (enable)
+         br_clk_i   : in  std_logic;  -- UART base clock (enable)
+         --
+         gpio_in    : in  std_logic_vector(31 downto 0);
+         gpio_out   : out std_logic_vector(31 downto 0);
+         gpio_dir   : out std_logic_vector(31 downto 0)
+         );
    end component ZPUPhiIO;
 
    -- Opcode decode constants
-- 
cgit v1.1


From e0735185b998f1e0bf61831bb15d802fada4e4ae Mon Sep 17 00:00:00 2001
From: Bert Lange 
Date: Tue, 25 Oct 2011 23:28:58 +0200
Subject: add: software test for gpio module

---
 zpu/hdl/zpu4/test/gpiotest/build.sh   |  4 ++
 zpu/hdl/zpu4/test/gpiotest/gpiotest.c | 72 +++++++++++++++++++++++++++++++++++
 2 files changed, 76 insertions(+)
 create mode 100755 zpu/hdl/zpu4/test/gpiotest/build.sh
 create mode 100644 zpu/hdl/zpu4/test/gpiotest/gpiotest.c

diff --git a/zpu/hdl/zpu4/test/gpiotest/build.sh b/zpu/hdl/zpu4/test/gpiotest/build.sh
new file mode 100755
index 0000000..c0385ad
--- /dev/null
+++ b/zpu/hdl/zpu4/test/gpiotest/build.sh
@@ -0,0 +1,4 @@
+zpu-elf-gcc -O3 -phi `pwd`/gpiotest.c -o gpiotest.elf -Wl,--relax -Wl,--gc-sections  -g
+zpu-elf-objdump --disassemble-all >gpiotest.dis gpiotest.elf
+zpu-elf-objcopy -O binary gpiotest.elf gpiotest.bin
+java -classpath ../../../../sw/simulator/zpusim.jar com.zylin.zpu.simulator.tools.MakeRam gpiotest.bin >gpiotest.ram
diff --git a/zpu/hdl/zpu4/test/gpiotest/gpiotest.c b/zpu/hdl/zpu4/test/gpiotest/gpiotest.c
new file mode 100644
index 0000000..393ab9f
--- /dev/null
+++ b/zpu/hdl/zpu4/test/gpiotest/gpiotest.c
@@ -0,0 +1,72 @@
+/*
+ * Small test program to check GPIOs 
+ * 
+ * LED chaser until keypress
+ *
+ */
+
+// addresses refer to Phi memory layout
+#define GPIO_DATA   *((volatile unsigned int *) 0x080a0004)
+#define GPIO_DIR    *((volatile unsigned int *) 0x080a0008)
+
+
+#define BUTTON_EAST  (3)
+#define BUTTON_NORTH (2)
+#define BUTTON_SOUTH (1)
+#define BUTTON_WEST  (0)
+
+
+#define bit_is_set(var, bit)              ((var) & (1 << (bit)))
+#define bit_is_clear(var, bit)            ((!(var)) & (1 << (bit)))
+#define loop_until_bit_is_set(var, bit)   do { } while (bit_is_clear(var, bit))
+#define loop_until_bit_is_clear(var, bit) do { } while (bit_is_set(var, bit))
+
+
+void led_test( void)
+{
+    unsigned char runs;
+    unsigned char leds;
+
+    runs = 1;
+    leds = 0x01;
+
+    while( runs)
+    {
+        // output
+        GPIO_DATA = leds;
+
+        // read button status
+        if bit_is_set(GPIO_DATA, BUTTON_NORTH) 
+        {
+            runs = 0;
+        }
+
+        // LED chaser
+        leds = leds << 1;
+        if (leds == 0)
+        { 
+            leds = 0x01;
+        }
+    }
+}
+
+
+void header_test( void)
+{
+    // this test is special for the SP601 header connector
+    // check the output in simulation
+    GPIO_DATA = 0x00550000;
+    GPIO_DIR  = 0xff00ffff;
+    GPIO_DATA = 0x00aa0000;
+    GPIO_DIR  = 0xffffffff;
+}
+
+
+int main(int argc, char **argv)
+{
+
+    led_test();
+    header_test();
+
+    abort();
+}
-- 
cgit v1.1


From 5d41e2b45c7ccf2cb48a20aa77127e4ba1fa3eda Mon Sep 17 00:00:00 2001
From: Bert Lange 
Date: Tue, 25 Oct 2011 23:30:29 +0200
Subject: minor fix: permission of build-scripts

---
 zpu/hdl/zpu4/test/dmips/build.sh     | 0
 zpu/hdl/zpu4/test/hello/build.sh     | 0
 zpu/hdl/zpu4/test/interrupt/build.sh | 0
 3 files changed, 0 insertions(+), 0 deletions(-)
 mode change 100644 => 100755 zpu/hdl/zpu4/test/dmips/build.sh
 mode change 100644 => 100755 zpu/hdl/zpu4/test/hello/build.sh
 mode change 100644 => 100755 zpu/hdl/zpu4/test/interrupt/build.sh

diff --git a/zpu/hdl/zpu4/test/dmips/build.sh b/zpu/hdl/zpu4/test/dmips/build.sh
old mode 100644
new mode 100755
diff --git a/zpu/hdl/zpu4/test/hello/build.sh b/zpu/hdl/zpu4/test/hello/build.sh
old mode 100644
new mode 100755
diff --git a/zpu/hdl/zpu4/test/interrupt/build.sh b/zpu/hdl/zpu4/test/interrupt/build.sh
old mode 100644
new mode 100755
-- 
cgit v1.1


From 236b344634cef79b294b33ef0141462351c13639 Mon Sep 17 00:00:00 2001
From: Bert Lange 
Date: Tue, 25 Oct 2011 23:32:05 +0200
Subject: update: documentation

---
 zpu/docs/zpu_arch.html | 56 +++++++++++++++++++++++++++++++++++++++-----------
 1 file changed, 44 insertions(+), 12 deletions(-)

diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html
index ea48154..32a3ca2 100644
--- a/zpu/docs/zpu_arch.html
+++ b/zpu/docs/zpu_arch.html
@@ -9,7 +9,6 @@ Several of the links will only work if you have checked out the zpu/zpu tree fro
 
      39.  Introduction
   
           
   
        •  License
-  
        •  Survey
   
        •  Features
   
        •  Status
   
        •  Download
@@ -119,12 +118,6 @@ as such, then they need to be contributed back.
 is free to decide that the ZPU shall have a BSD license for HDL + GPL
 for the rest.
          
 
-
-
          Survey
           
-
          Please take the time to fill in this short survey so we can gather
-information about where the ZPU can be the most useful:
          
-
          http://www.zylin.com/zpusurvey.html
          
-
 
 
          Features
           
 
            
@@ -155,7 +148,7 @@ Once www.opencores.org grows a GIT hosting service, the plan is to replicate
 the GIT repository there.
 
 
            
-The GCC ZPU toolchain is available from "git://www.ecosforge.net:8100/zpu/toolchain.git". The ZPU GCC toolchain is BIG(over 100mBytes), otherwise it would have been hosted at repo.or.cz too.
+The GCC ZPU toolchain is available from http://repo.or.cz/w/zpugcc.git. The ZPU GCC toolchain is BIG (over 100 MBytes).
 
 
            GIT
             
 For more advanced use of GIT, you will need to hit the books and read up 
@@ -1002,7 +995,7 @@ rather uncommon operations. These 32 registers are mapped to memory locations 0x
 value of these memory locations onto the stack, call _zpu_interrupt and
 restore them.
 
            
-See zpu/hdl/zpu4/test/interrupt/ for C code and zpu/hdl/example/simzpu_interrupt.do
+See zpu/hdl/zpu4/test/interrupt/ for C code and zpu/hdl/example/simzpu_interrupt.do
 for simulation example.
 
 
@@ -1068,7 +1061,7 @@ For now if you are starting a design, zpu4 or zealot are probably the safest.  z
 
 
            Performance Summary
            
 
-TODO fill in performance table for Altera and Lattice.
+TODO fill in performance table for Altera and Lattice.
 
            
 Tests are done with the Zealot
  SoC-System and Xilinx ISE 12.2 with standard settings.
@@ -1229,7 +1222,7 @@ The key features are:
 
 
              
 
            • Includes a very basic PHI I/O synthesizable core.
-It implements the 64 bits clocks counter (timer) and the UART. This is enough
+It implements the 64 bits clocks counter (timer), GPIO and the UART. This is enough
 to run the DMIPS benchmark and a hello world application. I tested the UART
 @ 9600 bps and @ 115200 bps.
              • 
 
            • The ZPU can be customized using generics. It allows the use of more
@@ -1247,6 +1240,7 @@ execution.
              • 
 
            • Includes ready to use memory images for a hello world program and the
 DMIPS benchmark.
              • 
 
            • Memory and trace blocks outside ZPU. This provides better modularity.
              • 
+
            • Much better documented code than the original version.
              • 
 
            
 
 Simulation and implementation files are provided. You need 16 kB of BRAMs
@@ -1913,6 +1907,7 @@ while developing the ZPU.
         
            Description
            
       
     
+
     
       
         
            0x080A0000
            
@@ -1935,6 +1930,43 @@ while developing the ZPU.
         running
            
       
     
+
+
+    
+      
+        
            0x080A0004
            
+      
+      
+        
            Read/
            
+        
            Write
            
+      
+      
+        
            GPIO data
            
+      
+      
+        
            Bit [31:0] input  data 31:0
            
+        
            Bit [31:0] output data 31:0
            
+      
+    
+
+    
+      
+        
            0x080A0008
            
+      
+      
+        
            Read/
            
+        
            Write
            
+      
+      
+        
            GPIO direction
            
+      
+      
+        
            Bit [31:0] data direction 31:0
            
+        
            0 output
            
+        
            1 input (default)
            
+      
+    
+
     
       
         
            0x080A000C
            
@@ -2277,7 +2309,7 @@ while developing the ZPU.
 
          • fix the TODO in this doc that are just doc fixes
 
          • organize the TODO list by priority and assign responsibility... if there are takers.
 
          • converge on a single IO for core implementations.
-
          • fill in performance table.
+
          • fill in performance table for Altera and Lattice.
 
          • re-org CVS to make it easy to keep appropriate SW, RTL(verilog and VHDL) , scripts, verification stuff together.  separation of tools, core, common, and ref design
 
          • provide FPGA scripts.
 
          • provide HDL regression environment.
-- 
cgit v1.1


From 41c1038aa9d14583510b68165e907da3b896422b Mon Sep 17 00:00:00 2001
From: Bert Lange 
Date: Fri, 28 Oct 2011 10:17:38 +0200
Subject: beautify: break long comment lines

---
 zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd   | 13 +++++++++
 .../zealot/fpga/digilent-starter-xc3s500e/top.vhd  | 31 +++++++++++++++++-----
 zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top.vhd  | 11 ++++++++
 3 files changed, 48 insertions(+), 7 deletions(-)

diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd
index 53383cc..560e685 100644
--- a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd
@@ -411,6 +411,19 @@ begin
     -- assign GPIOs
     -- no bidirectional pins (e.g. headers), so
     -- gpio_dir is unused
+    --
+    -- bit   31 30 29 28 27 26 25 24  23 22 21 20 19 18 17 16
+    --
+    --  in   -- -- -- -- -- -- -- --  -- -- -- -- -- -- -- --
+    -- out   -- -- -- -- -- -- -- --  -- -- -- -- -- -- -- --
+    --
+    --
+    -- bit   15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
+    --                                                       
+    --  in   gpio_dipswitch(7.....0)  -- -- -- --  buttons3.0
+    -- out   -- -- -- -- -- -- -- --  led(7................0)
+    --
+
     gpio_in(15 downto 8) <= gpio_dipswitch;
     gpio_in( 3 downto 0) <= gpio_button;
 
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top.vhd b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top.vhd
index 79668e5..4adc18b 100644
--- a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top.vhd
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top.vhd
@@ -421,14 +421,31 @@ begin
     -- assign GPIOs
     -- no bidirectional pins (e.g. headers), so
     -- gpio_dir is unused
-    gpio_in <= ((6) => rot_a,
-                (5) => rot_b,
-                (4) => rot_center,
+    --
+    -- bit   31 30 29 28 27 26 25 24  23 22 21 20 19 18 17 16
+    --
+    --  in   -- -- -- -- -- -- -- --  -- -- -- -- -- -- -- --
+    -- out   -- -- -- -- -- -- -- --  -- -- -- -- -- -- -- --
+    --
+    --
+    -- bit   15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
+    --                                                       
+    --  in   -- -- -- -- sw(3.....0)  -- ra rb rc be bn bs bw
+    -- out   -- -- -- -- -- -- -- --  led(7................0)
+
+    gpio_in <= ((11) => sw(3),
+                (10) => sw(2),
+                ( 9) => sw(1),
+                ( 8) => sw(0),
+                --
+                ( 6) => rot_a,
+                ( 5) => rot_b,
+                ( 4) => rot_center,
                 --
-                (3) => btn_east,
-                (2) => btn_north,
-                (1) => btn_south,
-                (0) => btn_west,
+                ( 3) => btn_east,
+                ( 2) => btn_north,
+                ( 1) => btn_south,
+                ( 0) => btn_west,
                 others => '0');
 
 
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top.vhd b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top.vhd
index bbeb0a2..27d158f 100644
--- a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top.vhd
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top.vhd
@@ -534,6 +534,17 @@ begin
     -- pragma translate_on
 
     -- assign GPIOs
+    --
+    -- bit   31 30 29 28 27 26 25 24  23 22 21 20 19 18 17 16  
+    --
+    --  in   -- -- -- -- -- -- -- --  gpio_header_ls(7.....0)  
+    -- out   -- -- -- -- -- -- -- --  gpio_header_ls(7.....0)  
+    --
+    -- bit   15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
+    --                                                       
+    --  in   -- -- -- -- switch(3.0)  -- -- -- -- button(3.0)
+    -- out   -- -- -- -- -- -- -- --  gpio_led(7...........0)
+    --
     gpio_in(23 downto 16) <= gpio_header_ls;
     gpio_in(11 downto  8) <= gpio_switch;
     gpio_in( 3 downto  0) <= gpio_button;
-- 
cgit v1.1


From 662a6952bc04419ac063cf3eb2b5917978eec0a1 Mon Sep 17 00:00:00 2001
From: Bert Lange 
Date: Fri, 28 Oct 2011 10:59:45 +0200
Subject: add: Spartan3 reference design for zealot

---
 .../fpga/altium-livedesign-xc3s1000/clean_up.sh    |  16 +
 .../fpga/altium-livedesign-xc3s1000/simulation.sh  |  49 +++
 .../simulation_config/run.do                       |   2 +
 .../simulation_config/wave.do                      |  30 ++
 .../fpga/altium-livedesign-xc3s1000/synthesis.sh   |  36 ++
 .../altium-livedesign-xc3s1000.ucf                 | 397 +++++++++++++++++++++
 .../synthesis_config/top.prj                       |  19 +
 .../synthesis_config/top.ut                        |  29 ++
 .../synthesis_config/top.xst                       |  56 +++
 .../zealot/fpga/altium-livedesign-xc3s1000/top.vhd | 372 +++++++++++++++++++
 .../fpga/altium-livedesign-xc3s1000/top_tb.vhd     | 194 ++++++++++
 11 files changed, 1200 insertions(+)
 create mode 100755 zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/clean_up.sh
 create mode 100755 zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation.sh
 create mode 100644 zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/run.do
 create mode 100644 zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/wave.do
 create mode 100755 zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis.sh
 create mode 100644 zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/altium-livedesign-xc3s1000.ucf
 create mode 100644 zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.prj
 create mode 100644 zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.ut
 create mode 100644 zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.xst
 create mode 100644 zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top.vhd
 create mode 100644 zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top_tb.vhd

diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/clean_up.sh b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/clean_up.sh
new file mode 100755
index 0000000..3855f16
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/clean_up.sh
@@ -0,0 +1,16 @@
+#!/bin/sh
+
+# ise build stuff
+rm -rf build
+rm -f top.bit
+
+# modelsim compile stuff
+rm -rf work
+rm -rf zpu
+
+# modelsim simulation stuff
+rm -f vsim.wlf
+rm -f transcript
+rm -f zpu_trace.log
+rm -f zpu_med1_io.log
+rm -f zpu_small1_io.log
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation.sh b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation.sh
new file mode 100755
index 0000000..d525737
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation.sh
@@ -0,0 +1,49 @@
+#!/bin/sh
+
+# need project files:
+#    run.do
+#    wave.do
+
+# need ModelSim tools:
+#    vlib
+#    vcom
+#    vsim
+
+
+echo "###############"
+echo "compile zpu lib"
+echo "###############"
+vlib zpu
+vcom -work zpu ../../roms/hello_dbram.vhdl
+vcom -work zpu ../../roms/hello_bram.vhdl
+#vcom -work zpu ../../roms/dmips_dbram.vhdl
+#vcom -work zpu ../../roms/dmips_bram.vhdl
+
+vcom -work zpu ../../roms/rom_pkg.vhdl
+vcom -work zpu ../../zpu_pkg.vhdl
+vcom -work zpu ../../zpu_small.vhdl
+vcom -work zpu ../../zpu_medium.vhdl
+vcom -work zpu ../../helpers/zpu_small1.vhdl
+vcom -work zpu ../../helpers/zpu_med1.vhdl
+vcom -work zpu ../../devices/txt_util.vhdl
+vcom -work zpu ../../devices/phi_io.vhdl
+vcom -work zpu ../../devices/timer.vhdl
+vcom -work zpu ../../devices/gpio.vhdl
+vcom -work zpu ../../devices/rx_unit.vhdl
+vcom -work zpu ../../devices/tx_unit.vhdl
+vcom -work zpu ../../devices/br_gen.vhdl
+vcom -work zpu ../../devices/trace.vhdl
+
+
+echo "################"
+echo "compile work lib"
+echo "################"
+vlib work
+vcom top.vhd
+vcom top_tb.vhd
+
+
+echo "###################"
+echo "start simulator gui"
+echo "###################"
+vsim -gui top_tb -do simulation_config/run.do
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/run.do b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/run.do
new file mode 100644
index 0000000..acc1710
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/run.do
@@ -0,0 +1,2 @@
+do wave.do
+run -all
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/wave.do b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/wave.do
new file mode 100644
index 0000000..3f5d4fe
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/wave.do
@@ -0,0 +1,30 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /top_tb/tb_reset_n
+add wave -noupdate /top_tb/tb_clk
+add wave -noupdate -divider 
+add wave -noupdate /top_tb/tb_rs232_rx
+add wave -noupdate /top_tb/tb_rs232_tx
+add wave -noupdate /top_tb/tb_rs232_rts
+add wave -noupdate /top_tb/tb_rs232_cts
+add wave -noupdate -divider Buttons
+add wave -noupdate /top_tb/tb_button_n
+add wave -noupdate -divider LEDs
+add wave -noupdate /top_tb/tb_led
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {0 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 2
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {1294218073 ps} {1421130628 ps}
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis.sh b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis.sh
new file mode 100755
index 0000000..a7180fc
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis.sh
@@ -0,0 +1,36 @@
+#!/bin/sh
+
+# need project files:
+#    top.xst
+#    top.prj
+#    top.ut
+
+# need Xilinx tools:
+#    xst
+#    ngdbuild
+#    map
+#    par
+#    trce
+#    bitgen
+
+echo "########################"
+echo "generate build directory"
+echo "########################"
+mkdir build
+cd build 
+mkdir tmp
+
+echo "###############"
+echo "start processes"
+echo "###############"
+xst      -ifn "../synthesis_config/top.xst" -ofn "top.syr" 
+ngdbuild -dd _ngo -nt timestamp -uc ../synthesis_config/altium-livedesign-xc3s1000.ucf -p xc3s1000-fg456-4 top.ngc top.ngd  
+map      -p xc3s1000-fg456-4 -cm area -ir off -pr off -c 100 -o top_map.ncd top.ngd top.pcf 
+par      -w -ol high -t 1 top_map.ncd top.ncd top.pcf 
+trce     -v 3 -s 4 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf 
+bitgen   -f ../synthesis_config/top.ut top.ncd 
+
+echo "###########"
+echo "get bitfile"
+echo "###########"
+cp top.bit ..
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/altium-livedesign-xc3s1000.ucf b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/altium-livedesign-xc3s1000.ucf
new file mode 100644
index 0000000..ba22ee9
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/altium-livedesign-xc3s1000.ucf
@@ -0,0 +1,397 @@
+############################################################
+# Altium Livedesign Evaluation Board constraints file
+#
+# Familiy: Spartan-3 
+# Device:  XC3S1000
+# Package: FG456C
+# Speed:   -4
+#
+# all banks are powered with 3.3V
+#
+# config pins (M2, M1, M0): 101
+
+############################################################
+## clock/timing constraints
+############################################################
+
+NET "clk_50" period = 50 MHz ;
+
+
+############################################################
+## pin placement constraints
+############################################################
+
+NET "clk_50"         LOC = AA12 | IOSTANDARD = LVCMOS33;
+NET "reset_n"        LOC = Y17  | IOSTANDARD = LVCMOS33; # low active
+
+# Soft JTAG
+NET "soft_tdo"       LOC = D22  | IOSTANDARD = LVCMOS33;
+NET "soft_tms"       LOC = E21  | IOSTANDARD = LVCMOS33;
+NET "soft_tdi"       LOC = E22  | IOSTANDARD = LVCMOS33;
+NET "soft_tck"       LOC = F21  | IOSTANDARD = LVCMOS33;
+
+# SRAM 0
+NET "sram0_a<0>"     LOC = L6   | IOSTANDARD = LVCMOS33;
+NET "sram0_a<1>"     LOC = K4   | IOSTANDARD = LVCMOS33;
+NET "sram0_a<2>"     LOC = H5   | IOSTANDARD = LVCMOS33;
+NET "sram0_a<3>"     LOC = G6   | IOSTANDARD = LVCMOS33;
+NET "sram0_a<4>"     LOC = F3   | IOSTANDARD = LVCMOS33; 
+NET "sram0_a<5>"     LOC = G1   | IOSTANDARD = LVCMOS33; 
+NET "sram0_a<6>"     LOC = G2   | IOSTANDARD = LVCMOS33; 
+NET "sram0_a<7>"     LOC = K3   | IOSTANDARD = LVCMOS33; 
+NET "sram0_a<8>"     LOC = T2   | IOSTANDARD = LVCMOS33;
+NET "sram0_a<9>"     LOC = T1   | IOSTANDARD = LVCMOS33;
+NET "sram0_a<10>"    LOC = U2   | IOSTANDARD = LVCMOS33; 
+NET "sram0_a<11>"    LOC = V3   | IOSTANDARD = LVCMOS33; 
+NET "sram0_a<12>"    LOC = V1   | IOSTANDARD = LVCMOS33;
+NET "sram0_a<13>"    LOC = W1   | IOSTANDARD = LVCMOS33;
+NET "sram0_a<14>"    LOC = V2   | IOSTANDARD = LVCMOS33;
+NET "sram0_a<15>"    LOC = V5   | IOSTANDARD = LVCMOS33; 
+NET "sram0_a<16>"    LOC = V4   | IOSTANDARD = LVCMOS33;
+NET "sram0_a<17>"    LOC = U5   | IOSTANDARD = LVCMOS33;
+NET "sram0_a<18>"    LOC = U6   | IOSTANDARD = LVCMOS33; # n.c. 
+NET "sram0_d<0>"     LOC = L4   | IOSTANDARD = LVCMOS33;
+NET "sram0_d<1>"     LOC = L3   | IOSTANDARD = LVCMOS33;
+NET "sram0_d<2>"     LOC = M5   | IOSTANDARD = LVCMOS33;
+NET "sram0_d<3>"     LOC = M4   | IOSTANDARD = LVCMOS33;
+NET "sram0_d<4>"     LOC = M3   | IOSTANDARD = LVCMOS33;
+NET "sram0_d<5>"     LOC = N4   | IOSTANDARD = LVCMOS33;
+NET "sram0_d<6>"     LOC = N3   | IOSTANDARD = LVCMOS33;
+NET "sram0_d<7>"     LOC = T5   | IOSTANDARD = LVCMOS33;
+NET "sram0_d<8>"     LOC = T4   | IOSTANDARD = LVCMOS33;
+NET "sram0_d<9>"     LOC = T6   | IOSTANDARD = LVCMOS33;
+NET "sram0_d<10>"    LOC = M6   | IOSTANDARD = LVCMOS33; 
+NET "sram0_d<11>"    LOC = N2   | IOSTANDARD = LVCMOS33;
+NET "sram0_d<12>"    LOC = N1   | IOSTANDARD = LVCMOS33;
+NET "sram0_d<13>"    LOC = M2   | IOSTANDARD = LVCMOS33;
+NET "sram0_d<14>"    LOC = M1   | IOSTANDARD = LVCMOS33;
+NET "sram0_d<15>"    LOC = L2   | IOSTANDARD = LVCMOS33;
+NET "sram0_cs_n"     LOC = L5   | IOSTANDARD = LVCMOS33;
+NET "sram0_lb_n"     LOC = L1   | IOSTANDARD = LVCMOS33;
+NET "sram0_ub_n"     LOC = K2   | IOSTANDARD = LVCMOS33;
+NET "sram0_we_n"     LOC = U4   | IOSTANDARD = LVCMOS33;
+NET "sram0_oe_n"     LOC = K1   | IOSTANDARD = LVCMOS33;
+
+# SRAM 1
+NET "sram1_a<0>"     LOC = K21  | IOSTANDARD = LVCMOS33;
+NET "sram1_a<1>"     LOC = K22  | IOSTANDARD = LVCMOS33;
+NET "sram1_a<2>"     LOC = K20  | IOSTANDARD = LVCMOS33;
+NET "sram1_a<3>"     LOC = G21  | IOSTANDARD = LVCMOS33;
+NET "sram1_a<4>"     LOC = G22  | IOSTANDARD = LVCMOS33; 
+NET "sram1_a<5>"     LOC = M17  | IOSTANDARD = LVCMOS33; 
+NET "sram1_a<6>"     LOC = L18  | IOSTANDARD = LVCMOS33; 
+NET "sram1_a<7>"     LOC = K19  | IOSTANDARD = LVCMOS33; 
+NET "sram1_a<8>"     LOC = V19  | IOSTANDARD = LVCMOS33;
+NET "sram1_a<9>"     LOC = W20  | IOSTANDARD = LVCMOS33;
+NET "sram1_a<10>"    LOC = W19  | IOSTANDARD = LVCMOS33; 
+NET "sram1_a<11>"    LOC = Y20  | IOSTANDARD = LVCMOS33; 
+NET "sram1_a<12>"    LOC = Y21  | IOSTANDARD = LVCMOS33;
+NET "sram1_a<13>"    LOC = Y22  | IOSTANDARD = LVCMOS33;
+NET "sram1_a<14>"    LOC = W21  | IOSTANDARD = LVCMOS33;
+NET "sram1_a<15>"    LOC = W22  | IOSTANDARD = LVCMOS33; 
+NET "sram1_a<16>"    LOC = V21  | IOSTANDARD = LVCMOS33;
+NET "sram1_a<17>"    LOC = V22  | IOSTANDARD = LVCMOS33;
+NET "sram1_a<18>"    LOC = V20  | IOSTANDARD = LVCMOS33; # n.c. 
+NET "sram1_d<0>"     LOC = L21  | IOSTANDARD = LVCMOS33;
+NET "sram1_d<1>"     LOC = M22  | IOSTANDARD = LVCMOS33;
+NET "sram1_d<2>"     LOC = M21  | IOSTANDARD = LVCMOS33;
+NET "sram1_d<3>"     LOC = N22  | IOSTANDARD = LVCMOS33;
+NET "sram1_d<4>"     LOC = N21  | IOSTANDARD = LVCMOS33;
+NET "sram1_d<5>"     LOC = U20  | IOSTANDARD = LVCMOS33;
+NET "sram1_d<6>"     LOC = T22  | IOSTANDARD = LVCMOS33;
+NET "sram1_d<7>"     LOC = T21  | IOSTANDARD = LVCMOS33;
+NET "sram1_d<8>"     LOC = V18  | IOSTANDARD = LVCMOS33;
+NET "sram1_d<9>"     LOC = U19  | IOSTANDARD = LVCMOS33;
+NET "sram1_d<10>"    LOC = U18  | IOSTANDARD = LVCMOS33; 
+NET "sram1_d<11>"    LOC = T18  | IOSTANDARD = LVCMOS33;
+NET "sram1_d<12>"    LOC = R18  | IOSTANDARD = LVCMOS33;
+NET "sram1_d<13>"    LOC = T17  | IOSTANDARD = LVCMOS33;
+NET "sram1_d<14>"    LOC = M18  | IOSTANDARD = LVCMOS33;
+NET "sram1_d<15>"    LOC = M20  | IOSTANDARD = LVCMOS33;
+NET "sram1_cs_n"     LOC = L22  | IOSTANDARD = LVCMOS33;
+NET "sram1_lb_n"     LOC = M19  | IOSTANDARD = LVCMOS33;
+NET "sram1_ub_n"     LOC = L20  | IOSTANDARD = LVCMOS33;
+NET "sram1_we_n"     LOC = U21  | IOSTANDARD = LVCMOS33;
+NET "sram1_oe_n"     LOC = L19  | IOSTANDARD = LVCMOS33;
+
+# RS232
+NET "rs232_rx"       LOC = A5   | IOSTANDARD = LVCMOS33;
+NET "rs232_tx"       LOC = F7   | IOSTANDARD = LVCMOS33;
+NET "rs232_cts"      LOC = F2   | IOSTANDARD = LVCMOS33;
+NET "rs232_rts"      LOC = E1   | IOSTANDARD = LVCMOS33;
+                     
+# 2x PS2 connectors
+NET "mouse_clk"      LOC = L17  | IOSTANDARD = LVCMOS33;
+NET "mouse_data"     LOC = G18  | IOSTANDARD = LVCMOS33;
+NET "kbd_clk"        LOC = F20  | IOSTANDARD = LVCMOS33;
+NET "kbd_data"       LOC = G19  | IOSTANDARD = LVCMOS33;
+
+
+# VGA output (2**9 = 512 colors)
+NET "vga_blue<7>"    LOC = E14  | IOSTANDARD = LVCMOS33;
+NET "vga_blue<6>"    LOC = A13  | IOSTANDARD = LVCMOS33;
+NET "vga_blue<5>"    LOC = C13  | IOSTANDARD = LVCMOS33;
+NET "vga_green<7>"   LOC = E11  | IOSTANDARD = LVCMOS33;
+NET "vga_green<6>"   LOC = C11  | IOSTANDARD = LVCMOS33;
+NET "vga_green<5>"   LOC = D10  | IOSTANDARD = LVCMOS33;
+NET "vga_red<7>"     LOC = D6   | IOSTANDARD = LVCMOS33;
+NET "vga_red<6>"     LOC = D7   | IOSTANDARD = LVCMOS33;
+NET "vga_red<5>"     LOC = D9   | IOSTANDARD = LVCMOS33;
+NET "vga_hsync"      LOC = A8   | IOSTANDARD = LVCMOS33;
+NET "vga_vsync"      LOC = B14  | IOSTANDARD = LVCMOS33;
+
+
+# Stereo Audio out
+NET "audio_r"        LOC = U3   | IOSTANDARD = LVCMOS33;
+NET "audio_l"        LOC = W3   | IOSTANDARD = LVCMOS33;
+
+
+# GPIO DIP switches 7..0 left..right, low active
+NET "switch_n<0>"    LOC = Y6   | IOSTANDARD = LVCMOS33;
+NET "switch_n<1>"    LOC = V6   | IOSTANDARD = LVCMOS33;
+NET "switch_n<2>"    LOC = U7   | IOSTANDARD = LVCMOS33;
+NET "switch_n<3>"    LOC = AA4  | IOSTANDARD = LVCMOS33;
+NET "switch_n<4>"    LOC = AB4  | IOSTANDARD = LVCMOS33;
+NET "switch_n<5>"    LOC = AA5  | IOSTANDARD = LVCMOS33;
+NET "switch_n<6>"    LOC = AB5  | IOSTANDARD = LVCMOS33;
+NET "switch_n<7>"    LOC = AA6  | IOSTANDARD = LVCMOS33;
+
+# GPIO push buttons, low active
+NET "button_n<5>"    LOC = C21  | IOSTANDARD = LVCMOS33;
+NET "button_n<4>"    LOC = B20  | IOSTANDARD = LVCMOS33;
+NET "button_n<3>"    LOC = A15  | IOSTANDARD = LVCMOS33;
+NET "button_n<2>"    LOC = B6   | IOSTANDARD = LVCMOS33;
+NET "button_n<1>"    LOC = C1   | IOSTANDARD = LVCMOS33;
+NET "button_n<0>"    LOC = D1   | IOSTANDARD = LVCMOS33;
+
+# GPIO LEDs
+NET "led<7>"         LOC = W6   | IOSTANDARD = LVCMOS33; 
+NET "led<6>"         LOC = Y5   | IOSTANDARD = LVCMOS33;
+NET "led<5>"         LOC = W5   | IOSTANDARD = LVCMOS33;
+NET "led<4>"         LOC = W4   | IOSTANDARD = LVCMOS33;
+NET "led<3>"         LOC = Y3   | IOSTANDARD = LVCMOS33;
+NET "led<2>"         LOC = Y2   | IOSTANDARD = LVCMOS33;
+NET "led<1>"         LOC = Y1   | IOSTANDARD = LVCMOS33;
+NET "led<0>"         LOC = W2   | IOSTANDARD = LVCMOS33;
+
+# seven segment display (5=left 0=right)
+#
+# segment assignment:
+# .ABCDEFG
+# 76543210
+NET "dig0_seg<7>"    LOC = E20  | IOSTANDARD = LVCMOS33;
+NET "dig0_seg<6>"    LOC = C22  | IOSTANDARD = LVCMOS33;
+NET "dig0_seg<5>"    LOC = E18  | IOSTANDARD = LVCMOS33;
+NET "dig0_seg<4>"    LOC = D20  | IOSTANDARD = LVCMOS33;
+NET "dig0_seg<3>"    LOC = D21  | IOSTANDARD = LVCMOS33;
+NET "dig0_seg<2>"    LOC = E19  | IOSTANDARD = LVCMOS33;
+NET "dig0_seg<1>"    LOC = G17  | IOSTANDARD = LVCMOS33;
+NET "dig0_seg<0>"    LOC = F19  | IOSTANDARD = LVCMOS33;
+  
+NET "dig1_seg<7>"    LOC = F17  | IOSTANDARD = LVCMOS33;
+NET "dig1_seg<6>"    LOC = D18  | IOSTANDARD = LVCMOS33;
+NET "dig1_seg<5>"    LOC = B19  | IOSTANDARD = LVCMOS33;
+NET "dig1_seg<4>"    LOC = C18  | IOSTANDARD = LVCMOS33;
+NET "dig1_seg<3>"    LOC = C19  | IOSTANDARD = LVCMOS33;
+NET "dig1_seg<2>"    LOC = C20  | IOSTANDARD = LVCMOS33;
+NET "dig1_seg<1>"    LOC = F18  | IOSTANDARD = LVCMOS33;
+NET "dig1_seg<0>"    LOC = D19  | IOSTANDARD = LVCMOS33;
+
+NET "dig2_seg<7>"    LOC = A19  | IOSTANDARD = LVCMOS33;
+NET "dig2_seg<6>"    LOC = E17  | IOSTANDARD = LVCMOS33;
+NET "dig2_seg<5>"    LOC = C17  | IOSTANDARD = LVCMOS33;
+NET "dig2_seg<4>"    LOC = D17  | IOSTANDARD = LVCMOS33;
+NET "dig2_seg<3>"    LOC = B15  | IOSTANDARD = LVCMOS33;
+NET "dig2_seg<2>"    LOC = A18  | IOSTANDARD = LVCMOS33;
+NET "dig2_seg<1>"    LOC = B18  | IOSTANDARD = LVCMOS33;
+NET "dig2_seg<0>"    LOC = B17  | IOSTANDARD = LVCMOS33;
+
+NET "dig3_seg<7>"    LOC = D15  | IOSTANDARD = LVCMOS33;
+NET "dig3_seg<6>"    LOC = E13  | IOSTANDARD = LVCMOS33;
+NET "dig3_seg<5>"    LOC = B13  | IOSTANDARD = LVCMOS33;
+NET "dig3_seg<4>"    LOC = D13  | IOSTANDARD = LVCMOS33;
+NET "dig3_seg<3>"    LOC = D14  | IOSTANDARD = LVCMOS33;
+NET "dig3_seg<2>"    LOC = A14  | IOSTANDARD = LVCMOS33;
+NET "dig3_seg<1>"    LOC = E16  | IOSTANDARD = LVCMOS33;
+NET "dig3_seg<0>"    LOC = E15  | IOSTANDARD = LVCMOS33;
+
+NET "dig4_seg<7>"    LOC = D11  | IOSTANDARD = LVCMOS33;
+NET "dig4_seg<6>"    LOC = E9   | IOSTANDARD = LVCMOS33;
+NET "dig4_seg<5>"    LOC = A10  | IOSTANDARD = LVCMOS33;
+NET "dig4_seg<4>"    LOC = B9   | IOSTANDARD = LVCMOS33;
+NET "dig4_seg<3>"    LOC = A9   | IOSTANDARD = LVCMOS33;
+NET "dig4_seg<2>"    LOC = C10  | IOSTANDARD = LVCMOS33;
+NET "dig4_seg<1>"    LOC = A12  | IOSTANDARD = LVCMOS33;
+NET "dig4_seg<0>"    LOC = B10  | IOSTANDARD = LVCMOS33;
+
+NET "dig5_seg<7>"    LOC = C7   | IOSTANDARD = LVCMOS33;
+NET "dig5_seg<6>"    LOC = A4   | IOSTANDARD = LVCMOS33;
+NET "dig5_seg<5>"    LOC = B5   | IOSTANDARD = LVCMOS33;
+NET "dig5_seg<4>"    LOC = E6   | IOSTANDARD = LVCMOS33;
+NET "dig5_seg<3>"    LOC = C5   | IOSTANDARD = LVCMOS33;
+NET "dig5_seg<2>"    LOC = E7   | IOSTANDARD = LVCMOS33;
+NET "dig5_seg<1>"    LOC = B8   | IOSTANDARD = LVCMOS33;
+NET "dig5_seg<0>"    LOC = C6   | IOSTANDARD = LVCMOS33;
+
+
+# Header A (left)
+NET "header_a<2>"    LOC = V7   | IOSTANDARD = LVCMOS33;  
+NET "header_a<3>"    LOC = AA8  | IOSTANDARD = LVCMOS33; 
+NET "header_a<4>"    LOC = AB8  | IOSTANDARD = LVCMOS33; 
+NET "header_a<5>"    LOC = V8   | IOSTANDARD = LVCMOS33;  
+NET "header_a<6>"    LOC = Y10  | IOSTANDARD = LVCMOS33; 
+NET "header_a<7>"    LOC = V9   | IOSTANDARD = LVCMOS33;  
+NET "header_a<8>"    LOC = W9   | IOSTANDARD = LVCMOS33;  
+NET "header_a<9>"    LOC = AA10 | IOSTANDARD = LVCMOS33;
+NET "header_a<10>"   LOC = AB10 | IOSTANDARD = LVCMOS33; 
+NET "header_a<11>"   LOC = W10  | IOSTANDARD = LVCMOS33;  
+NET "header_a<12>"   LOC = AB11 | IOSTANDARD = LVCMOS33;
+NET "header_a<13>"   LOC = U11  | IOSTANDARD = LVCMOS33;
+NET "header_a<14>"   LOC = AB13 | IOSTANDARD = LVCMOS33;
+NET "header_a<15>"   LOC = AA13 | IOSTANDARD = LVCMOS33;
+NET "header_a<16>"   LOC = V10  | IOSTANDARD = LVCMOS33;
+NET "header_a<17>"   LOC = U10  | IOSTANDARD = LVCMOS33;
+NET "header_a<18>"   LOC = W13  | IOSTANDARD = LVCMOS33;
+NET "header_a<19>"   LOC = Y13  | IOSTANDARD = LVCMOS33;
+
+# Header B (right)
+NET "header_b<2>"    LOC = V14  | IOSTANDARD = LVCMOS33;  
+NET "header_b<3>"    LOC = V13  | IOSTANDARD = LVCMOS33;
+NET "header_b<4>"    LOC = AA15 | IOSTANDARD = LVCMOS33;
+NET "header_b<5>"    LOC = W14  | IOSTANDARD = LVCMOS33;
+NET "header_b<6>"    LOC = AB15 | IOSTANDARD = LVCMOS33;
+NET "header_b<7>"    LOC = Y16  | IOSTANDARD = LVCMOS33;
+NET "header_b<8>"    LOC = AA17 | IOSTANDARD = LVCMOS33;
+NET "header_b<9>"    LOC = AA18 | IOSTANDARD = LVCMOS33;
+NET "header_b<10>"   LOC = AB18 | IOSTANDARD = LVCMOS33;
+NET "header_b<11>"   LOC = Y18  | IOSTANDARD = LVCMOS33;
+NET "header_b<12>"   LOC = Y19  | IOSTANDARD = LVCMOS33;
+NET "header_b<13>"   LOC = AB20 | IOSTANDARD = LVCMOS33;
+NET "header_b<14>"   LOC = AA20 | IOSTANDARD = LVCMOS33;
+NET "header_b<15>"   LOC = U16  | IOSTANDARD = LVCMOS33;
+NET "header_b<16>"   LOC = V16  | IOSTANDARD = LVCMOS33;
+NET "header_b<17>"   LOC = V17  | IOSTANDARD = LVCMOS33;
+NET "header_b<18>"   LOC = W16  | IOSTANDARD = LVCMOS33;
+NET "header_b<19>"   LOC = W17  | IOSTANDARD = LVCMOS33;
+
+# usused pins
+CONFIG PROHIBIT = A3;
+CONFIG PROHIBIT = A7;
+CONFIG PROHIBIT = A11;
+CONFIG PROHIBIT = A16;
+CONFIG PROHIBIT = AA3;
+CONFIG PROHIBIT = AA7;
+CONFIG PROHIBIT = AA9;
+CONFIG PROHIBIT = AA11;
+CONFIG PROHIBIT = AA14;
+CONFIG PROHIBIT = AA16;
+CONFIG PROHIBIT = AA19;
+CONFIG PROHIBIT = AB7;
+CONFIG PROHIBIT = AB9;
+CONFIG PROHIBIT = AB12;
+CONFIG PROHIBIT = AB14;
+CONFIG PROHIBIT = AB16;
+CONFIG PROHIBIT = AB19;
+CONFIG PROHIBIT = B4;
+CONFIG PROHIBIT = B7;
+CONFIG PROHIBIT = B12;
+CONFIG PROHIBIT = B11;
+CONFIG PROHIBIT = B16;
+CONFIG PROHIBIT = C2;
+CONFIG PROHIBIT = C3;
+CONFIG PROHIBIT = C4;
+CONFIG PROHIBIT = C12;
+CONFIG PROHIBIT = C16;
+CONFIG PROHIBIT = D2;
+CONFIG PROHIBIT = D3;
+CONFIG PROHIBIT = D4;
+CONFIG PROHIBIT = D5;
+CONFIG PROHIBIT = D8;
+CONFIG PROHIBIT = D12;
+CONFIG PROHIBIT = D16;
+CONFIG PROHIBIT = E2;
+CONFIG PROHIBIT = E3;
+CONFIG PROHIBIT = E8;
+CONFIG PROHIBIT = E4;
+CONFIG PROHIBIT = E5;
+CONFIG PROHIBIT = F4;
+CONFIG PROHIBIT = E10;
+CONFIG PROHIBIT = E12;
+CONFIG PROHIBIT = F12;
+CONFIG PROHIBIT = F5;
+CONFIG PROHIBIT = F13;
+CONFIG PROHIBIT = F6;
+CONFIG PROHIBIT = F9;
+CONFIG PROHIBIT = F10;
+CONFIG PROHIBIT = F16;
+CONFIG PROHIBIT = F11;
+CONFIG PROHIBIT = F14;
+CONFIG PROHIBIT = G3;
+CONFIG PROHIBIT = G4;
+CONFIG PROHIBIT = G5;
+CONFIG PROHIBIT = G20;
+CONFIG PROHIBIT = H1;
+CONFIG PROHIBIT = H2;
+CONFIG PROHIBIT = H4;
+CONFIG PROHIBIT = H18;
+CONFIG PROHIBIT = H19;
+CONFIG PROHIBIT = H21;
+CONFIG PROHIBIT = H22;
+CONFIG PROHIBIT = J1;
+CONFIG PROHIBIT = J2;
+CONFIG PROHIBIT = J4;
+CONFIG PROHIBIT = J5;
+CONFIG PROHIBIT = J6;
+CONFIG PROHIBIT = J17;
+CONFIG PROHIBIT = J18;
+CONFIG PROHIBIT = J19;
+CONFIG PROHIBIT = J21;
+CONFIG PROHIBIT = J22;
+CONFIG PROHIBIT = K5;
+CONFIG PROHIBIT = K6;
+CONFIG PROHIBIT = K17;
+CONFIG PROHIBIT = K18;
+CONFIG PROHIBIT = N5;
+CONFIG PROHIBIT = N6;
+CONFIG PROHIBIT = N17;
+CONFIG PROHIBIT = N18;
+CONFIG PROHIBIT = N19;
+CONFIG PROHIBIT = N20;
+CONFIG PROHIBIT = P1;
+CONFIG PROHIBIT = P2;
+CONFIG PROHIBIT = P4;
+CONFIG PROHIBIT = P5;
+CONFIG PROHIBIT = P6;
+CONFIG PROHIBIT = P17;
+CONFIG PROHIBIT = P18;
+CONFIG PROHIBIT = P19;
+CONFIG PROHIBIT = P21;
+CONFIG PROHIBIT = P22;
+CONFIG PROHIBIT = R1;
+CONFIG PROHIBIT = R2;
+CONFIG PROHIBIT = R4;
+CONFIG PROHIBIT = R5;
+CONFIG PROHIBIT = R19;
+CONFIG PROHIBIT = R21;
+CONFIG PROHIBIT = R22;
+CONFIG PROHIBIT = T3;
+CONFIG PROHIBIT = T19;
+CONFIG PROHIBIT = T20;
+CONFIG PROHIBIT = U9;
+CONFIG PROHIBIT = U12;
+CONFIG PROHIBIT = U13;
+CONFIG PROHIBIT = U14;
+CONFIG PROHIBIT = U17;
+CONFIG PROHIBIT = V11;
+CONFIG PROHIBIT = V12;
+CONFIG PROHIBIT = V15;
+CONFIG PROHIBIT = W7;
+CONFIG PROHIBIT = W8;
+CONFIG PROHIBIT = W11;
+CONFIG PROHIBIT = W12;
+CONFIG PROHIBIT = W15;
+CONFIG PROHIBIT = W18;
+CONFIG PROHIBIT = Y4;
+CONFIG PROHIBIT = Y7;
+CONFIG PROHIBIT = Y11;
+CONFIG PROHIBIT = Y12;
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.prj b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.prj
new file mode 100644
index 0000000..24120d5
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.prj
@@ -0,0 +1,19 @@
+vhdl work ../top.vhd
+vhdl zpu ../../../zpu_pkg.vhdl
+vhdl zpu ../../../zpu_small.vhdl
+vhdl zpu ../../../zpu_medium.vhdl
+vhdl zpu ../../../roms/rom_pkg.vhdl
+#vhdl zpu ../../../roms/hello_dbram.vhdl
+#vhdl zpu ../../../roms/hello_bram.vhdl
+vhdl zpu ../../../roms/dmips_dbram.vhdl
+vhdl zpu ../../../roms/dmips_bram.vhdl
+vhdl zpu ../../../helpers/zpu_small1.vhdl
+vhdl zpu ../../../helpers/zpu_med1.vhdl
+vhdl zpu ../../../devices/txt_util.vhdl
+vhdl zpu ../../../devices/phi_io.vhdl
+vhdl zpu ../../../devices/timer.vhdl
+vhdl zpu ../../../devices/gpio.vhdl
+vhdl zpu ../../../devices/rx_unit.vhdl
+vhdl zpu ../../../devices/tx_unit.vhdl
+vhdl zpu ../../../devices/br_gen.vhdl
+vhdl zpu ../../../devices/trace.vhdl
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.ut b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.ut
new file mode 100644
index 0000000..765a6f3
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.ut
@@ -0,0 +1,29 @@
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g ConfigRate:6
+-g CclkPin:PullUp
+-g M0Pin:PullUp
+-g M1Pin:PullUp
+-g M2Pin:PullUp
+-g ProgPin:PullUp
+-g DonePin:PullUp
+-g HswapenPin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g DCMShutdown:Disable
+-g DCIUpdateMode:AsRequired
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Match_cycle:Auto
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.xst b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.xst
new file mode 100644
index 0000000..14873ea
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.xst
@@ -0,0 +1,56 @@
+set -tmpdir "tmp"
+set -xsthdpdir "xst"
+run
+-ifn ../synthesis_config/top.prj
+-ifmt mixed
+-ofn top
+-ofmt NGC
+-p xc3s1000-4-fg456
+-top top
+-opt_mode Speed
+-opt_level 1
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract Yes
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-auto_bram_packing NO
+-mux_extract Yes
+-resource_sharing YES
+-async_to_sync NO
+-mult_style Auto
+-iobuf YES
+-max_fanout 500
+-bufg 8
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Yes
+-use_sync_set Yes
+-use_sync_reset Yes
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top.vhd b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top.vhd
new file mode 100644
index 0000000..fbca62b
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top.vhd
@@ -0,0 +1,372 @@
+-- top module of
+-- Altium LiveDesign Board
+--
+-- using following external connections:
+-- test button as reset
+-- LEDs and 7 segment for output
+-- RS232
+--
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library zpu;
+use zpu.zpupkg.all;   -- zpu_dbgo_t
+
+library unisim;
+use unisim.vcomponents.dcm;
+
+
+entity top is
+    port (
+        -- pragma translate_off 
+        stop_simulation : out   std_logic;
+        -- pragma translate_on 
+        clk_50     : in    std_logic;
+        reset_n    : in    std_logic;
+        --
+        -- soft JTAG
+        soft_tdo   : out   std_logic;
+        soft_tms   : in    std_logic;
+        soft_tdi   : in    std_logic;
+        soft_tck   : in    std_logic;
+        --
+        -- SRAM 0 (256k x 16) pin connections
+        sram0_a    : out   std_logic_vector(18 downto 0);
+        sram0_d    : inout std_logic_vector(15 downto 0);
+        sram0_lb_n : out   std_logic;
+        sram0_ub_n : out   std_logic;
+        sram0_cs_n : out   std_logic;       -- chip select
+        sram0_we_n : out   std_logic;       -- write-enable
+        sram0_oe_n : out   std_logic;       -- output enable
+        --
+        -- SRAM 1 (256k x 16) pin connections
+        sram1_a    : out   std_logic_vector(18 downto 0);
+        sram1_d    : inout std_logic_vector(15 downto 0);
+        sram1_lb_n : out   std_logic;
+        sram1_ub_n : out   std_logic;
+        sram1_cs_n : out   std_logic;       -- chip select
+        sram1_we_n : out   std_logic;       -- write-enable
+        sram1_oe_n : out   std_logic;       -- output enable
+        --
+        -- RS232
+        rs232_rx   : in    std_logic;
+        rs232_tx   : out   std_logic;
+        rs232_cts  : in    std_logic;
+        rs232_rts  : out   std_logic;
+        --
+        -- PS2 connectors
+        mouse_clk  : inout std_logic;
+        mouse_data : inout std_logic;
+        kbd_clk    : inout std_logic;
+        kbd_data   : inout std_logic;
+        --
+        -- vga output
+        vga_red    : out   std_logic_vector(7 downto 5);
+        vga_green  : out   std_logic_vector(7 downto 5);
+        vga_blue   : out   std_logic_vector(7 downto 5);
+        vga_hsync  : out   std_logic;
+        vga_vsync  : out   std_logic;
+        --
+        -- Audio out
+        audio_r    : out   std_logic;
+        audio_l    : out   std_logic;
+        --
+        -- GPIOs
+        switch_n   : in    std_logic_vector(7 downto 0);
+        button_n   : in    std_logic_vector(5 downto 0);
+        led        : out   std_logic_vector(7 downto 0);
+        --
+        -- seven segment display
+        dig0_seg   : out   std_logic_vector(7 downto 0);
+        dig1_seg   : out   std_logic_vector(7 downto 0);
+        dig2_seg   : out   std_logic_vector(7 downto 0);
+        dig3_seg   : out   std_logic_vector(7 downto 0);
+        dig4_seg   : out   std_logic_vector(7 downto 0);
+        dig5_seg   : out   std_logic_vector(7 downto 0);
+        --
+        -- User Header
+        header_a   : inout std_logic_vector(19 downto 2);
+        header_b   : inout std_logic_vector(19 downto 2)
+    );
+end entity top;
+
+
+architecture rtl of top is
+
+
+    ---------------------------
+    -- type declarations
+    type zpu_type is (zpu_small, zpu_medium);
+
+    ---------------------------
+    -- constant declarations
+    constant zpu_flavour   : zpu_type := zpu_small;  -- choose your flavour HERE
+    --  modify frequency here
+    constant clk_multiply  : positive := 3; -- 9 for small, 3 for medium
+    constant clk_divide    : positive := 2; -- 5 for small, 2 for medium
+    --
+    constant word_size_c   : natural  := 32; -- 32 bits data path
+    constant addr_w_c      : natural  := 18; -- 18 bits address space=256 kB, 128 kB I/O
+
+    constant clk_frequency : positive := 50; -- input frequency for correct calculation
+
+
+    ---------------------------
+    -- component declarations
+    component zpu_small1 is
+        generic (
+            word_size  : natural   := 32;      -- 32 bits data path
+            d_care_val : std_logic := '0';     -- Fill value
+            clk_freq   : positive  := 50;      -- 50 MHz clock
+            brate      : positive  := 115200;  -- RS232 baudrate
+            addr_w     : natural   := 16;      -- 16 bits address space=64 kB, 32 kB I/O
+            bram_w     : natural   := 15       -- 15 bits RAM space=32 kB
+            );
+        port (
+            clk_i      : in  std_logic;        -- CPU clock
+            rst_i      : in  std_logic;        -- Reset
+            break_o    : out std_logic;        -- Break executed
+            dbg_o      : out zpu_dbgo_t;       -- Debug info
+            rs232_tx_o : out std_logic;        -- UART Tx
+            rs232_rx_i : in  std_logic;        -- UART Rx
+            gpio_in    : in  std_logic_vector(31 downto 0);
+            gpio_out   : out std_logic_vector(31 downto 0);
+            gpio_dir   : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
+            );
+    end component zpu_small1;
+
+    component zpu_med1 is
+        generic(
+            word_size  : natural   := 32;      -- 32 bits data path
+            d_care_val : std_logic := '0';     -- Fill value
+            clk_freq   : positive  := 50;      -- 50 MHz clock
+            brate      : positive  := 115200;  -- RS232 baudrate
+            addr_w     : natural   := 18;      -- 18 bits address space=256 kB, 128 kB I/O
+            bram_w     : natural   := 15       -- 15 bits RAM space=32 kB
+            );
+        port(
+            clk_i      : in  std_logic;        -- CPU clock
+            rst_i      : in  std_logic;        -- Reset
+            break_o    : out std_logic;        -- Break executed
+            dbg_o      : out zpu_dbgo_t;       -- Debug info
+            rs232_tx_o : out std_logic;        -- UART Tx
+            rs232_rx_i : in  std_logic;        -- UART Rx
+            gpio_in    : in  std_logic_vector(31 downto 0);
+            gpio_out   : out std_logic_vector(31 downto 0);
+            gpio_dir   : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
+            );
+    end component zpu_med1;
+
+
+    ---------------------------
+    -- signal declarations
+    signal dcm_i0_clk0     : std_ulogic;
+    signal dcm_i0_clkfx    : std_ulogic;
+    signal clk_fb          : std_ulogic;
+    signal clk             : std_ulogic;
+    --
+    signal reset_shift_reg : std_ulogic_vector(3 downto 0);
+    signal reset_sync      : std_ulogic;
+    --
+    signal zpu_i0_dbg      : zpu_dbgo_t;  -- Debug info
+    signal zpu_i0_break    : std_logic;
+    --
+    signal gpio_in         : std_logic_vector(31 downto 0) := (others => '0');
+    signal zpu_i0_gpio_out : std_logic_vector(31 downto 0);
+    signal zpu_i0_gpio_dir : std_logic_vector(31 downto 0);
+
+
+begin
+
+    -- default output drivers
+    -- to pass bitgen DRC 
+    -- outputs used by design are commented
+    soft_tdo   <= '1';
+    --
+    sram0_a    <= (others => '1');
+    sram0_d    <= (others => 'Z');
+    sram0_lb_n <= '1';
+    sram0_ub_n <= '1';
+    sram0_cs_n <= '1';
+    sram0_we_n <= '1';
+    sram0_oe_n <= '1';
+    --
+    sram1_a    <= (others => '1');
+    sram1_d    <= (others => 'Z');
+    sram1_lb_n <= '1';
+    sram1_ub_n <= '1';
+    sram1_cs_n <= '1';
+    sram1_we_n <= '1';
+    sram1_oe_n <= '1';
+    --
+    --rs232_tx   <= '1';
+    rs232_rts  <= '1';
+    --
+    mouse_clk  <= 'Z'; 
+    mouse_data <= 'Z'; 
+    kbd_clk    <= 'Z'; 
+    kbd_data   <= 'Z'; 
+    --
+    vga_red    <= (others => '1');
+    vga_green  <= (others => '1');
+    vga_blue   <= (others => '1');
+    vga_hsync  <= '1';
+    vga_vsync  <= '1';
+    --
+    audio_r    <= '0';
+    audio_l    <= '0';
+    --
+    --led        <= (others => '0');
+    --
+    --dig0_seg   <= (others => '0');
+    --dig1_seg   <= (others => '0');
+    dig2_seg   <= (others => '0');
+    dig3_seg   <= (others => '0');
+    dig4_seg   <= (others => '0');
+    dig5_seg   <= (others => '0');
+    --
+    header_a   <= (others => 'Z');
+    header_b   <= (others => 'Z');
+
+
+    -- digital clock manager (DCM)
+    -- to generate higher/other system clock frequencys
+    dcm_i0 : dcm
+        generic map (
+            startup_wait   => true,     -- wait with DONE till locked
+            clkfx_multiply => clk_multiply,
+            clkfx_divide   => clk_divide, 
+            clk_feedback   => "1X"
+            )
+        port map (
+            clkin => clk_50,
+            clk0  => dcm_i0_clk0,
+            clkfx => dcm_i0_clkfx,
+            clkfb => clk_fb
+            );
+
+    clk_fb <= dcm_i0_clk0;
+    clk    <= dcm_i0_clkfx;
+
+
+    -- reset synchronizer
+    -- generate synchronous reset
+    reset_synchronizer : process(clk, reset_n)
+    begin
+        if reset_n = '0' then
+            reset_shift_reg <= (others => '1');
+        elsif rising_edge(clk) then
+            reset_shift_reg <= reset_shift_reg(reset_shift_reg'high-1 downto 0) & '0';
+        end if;
+    end process;
+    reset_sync <= reset_shift_reg(reset_shift_reg'high);
+
+
+    -- select instance of zpu
+    zpu_i0_small : if zpu_flavour = zpu_small generate
+        zpu_i0 : zpu_small1
+            generic map (
+                addr_w    => addr_w_c,
+                word_size => word_size_c,
+                clk_freq  => clk_frequency * clk_multiply / clk_divide
+                )
+            port map (
+                clk_i      => clk,             -- : in  std_logic;   -- CPU clock
+                rst_i      => reset_sync,      -- : in  std_logic;   -- Reset
+                break_o    => zpu_i0_break,    -- : out std_logic;   -- Break executed
+                dbg_o      => zpu_i0_dbg,      -- : out zpu_dbgo_t;  -- Debug info
+                rs232_tx_o => rs232_tx,        -- : out std_logic;   -- UART Tx
+                rs232_rx_i => rs232_rx,        -- : in  std_logic    -- UART Rx
+                gpio_in    => gpio_in,         -- : in  std_logic_vector(31 downto 0);
+                gpio_out   => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
+                gpio_dir   => zpu_i0_gpio_dir  -- : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
+                );
+    end generate zpu_i0_small;
+
+    zpu_i0_medium : if zpu_flavour = zpu_medium generate
+        zpu_i0 : zpu_med1
+            generic map (
+                addr_w    => addr_w_c,
+                word_size => word_size_c,
+                clk_freq  => clk_frequency * clk_multiply / clk_divide
+                )
+            port map (
+                clk_i      => clk,             -- : in  std_logic;   -- CPU clock
+                rst_i      => reset_sync,      -- : in  std_logic;   -- Reset
+                break_o    => zpu_i0_break,    -- : out std_logic;   -- Break executed
+                dbg_o      => zpu_i0_dbg,      -- : out zpu_dbgo_t;  -- Debug info
+                rs232_tx_o => rs232_tx,        -- : out std_logic;   -- UART Tx
+                rs232_rx_i => rs232_rx,        -- : in  std_logic    -- UART Rx
+                gpio_in    => gpio_in,         -- : in  std_logic_vector(31 downto 0);
+                gpio_out   => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
+                gpio_dir   => zpu_i0_gpio_dir  -- : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
+                );
+    end generate zpu_i0_medium;
+
+
+    -- pragma translate_off 
+    stop_simulation <= zpu_i0_break;
+
+
+    trace_mod : trace
+        generic map (
+            addr_w    => addr_w_c,
+            word_size => word_size_c,
+            log_file  => "zpu_trace.log"
+            )
+        port map (
+            clk_i  => clk,
+            dbg_i  => zpu_i0_dbg,
+            stop_i => zpu_i0_break,
+            busy_i => '0'
+            );
+    -- pragma translate_on
+
+
+    -- assign GPIOs
+    --
+    -- bit   31 30 29 28 27 26 25 24  23 22 21 20 19 18 17 16  
+    --
+    --  in   header_a(19.........12)  -- -- -- -- -- -- -- --  
+    -- out   header_a(19.........12)  dig1_seg(7...........0)  
+    --
+    --
+    -- bit   15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
+    --                                                       
+    --  in   switch_n(7...........0)  -- --  button_n(5....0)
+    -- out   dig0_seg(7...........0)  led(7................0)
+    --
+
+    gpio_in(31 downto 24) <= header_a(19 downto 12);
+    gpio_in(15 downto 8)  <= switch_n;
+    gpio_in( 5 downto 0)  <= button_n;
+
+    -- 3-state buffers for some headers
+    header_a(19) <= zpu_i0_gpio_out(31) when zpu_i0_gpio_dir(31) = '0' else 'Z';
+    header_a(18) <= zpu_i0_gpio_out(30) when zpu_i0_gpio_dir(30) = '0' else 'Z';
+    header_a(17) <= zpu_i0_gpio_out(29) when zpu_i0_gpio_dir(29) = '0' else 'Z';
+    header_a(16) <= zpu_i0_gpio_out(28) when zpu_i0_gpio_dir(28) = '0' else 'Z';
+    header_a(15) <= zpu_i0_gpio_out(27) when zpu_i0_gpio_dir(27) = '0' else 'Z';
+    header_a(14) <= zpu_i0_gpio_out(26) when zpu_i0_gpio_dir(26) = '0' else 'Z';
+    header_a(13) <= zpu_i0_gpio_out(25) when zpu_i0_gpio_dir(25) = '0' else 'Z';
+    header_a(12) <= zpu_i0_gpio_out(24) when zpu_i0_gpio_dir(24) = '0' else 'Z';
+
+    -- outputs    
+    dig1_seg <= zpu_i0_gpio_out(23 downto 16);
+    dig0_seg <= zpu_i0_gpio_out(15 downto  8);
+
+    -- switch on all LEDs in case of break
+    process
+    begin
+        wait until rising_edge(clk);
+        led <= zpu_i0_gpio_out(7 downto 0);
+        if zpu_i0_break = '1' then
+            led <= (others => '1');
+        end if;
+    end process;
+
+
+end architecture rtl;
+
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top_tb.vhd b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top_tb.vhd
new file mode 100644
index 0000000..e42fc20
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top_tb.vhd
@@ -0,0 +1,194 @@
+-- testbench for
+-- Altium LiveDesign Board
+--
+-- includes "model" for clock generation
+-- simulate press on test/reset as reset
+--
+-- place models for external components (SRAM, PS2) in this file
+--
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity top_tb is
+end entity top_tb;
+
+architecture testbench of top_tb is
+
+    ---------------------------
+    -- constant declarations
+    constant clk_period : time := 1 sec / 50_000_000;  -- 50 MHz
+
+
+    ---------------------------
+    -- signal declarations
+    signal simulation_run     : boolean := true;
+    signal tb_stop_simulation : std_logic;
+    --
+    signal tb_clk             : std_logic                     := '0';
+    signal tb_reset_n         : std_logic;
+    --
+    -- soft JTAG
+    signal tb_soft_tdo        : std_logic;
+    signal tb_soft_tms        : std_logic                     := '1';
+    signal tb_soft_tdi        : std_logic                     := '1';
+    signal tb_soft_tck        : std_logic                     := '1';
+    --
+    -- SRAM 0 (256k x 16) pin connections
+    signal tb_sram0_a         : std_logic_vector(18 downto 0);
+    signal tb_sram0_d         : std_logic_vector(15 downto 0) := (others => 'Z');
+    signal tb_sram0_lb_n      : std_logic;
+    signal tb_sram0_ub_n      : std_logic;
+    signal tb_sram0_cs_n      : std_logic;     -- chip select
+    signal tb_sram0_we_n      : std_logic;     -- write-enable
+    signal tb_sram0_oe_n      : std_logic;     -- output enable
+    --
+    -- SRAM 1 (256k x 16) pin connections
+    signal tb_sram1_a         : std_logic_vector(18 downto 0);
+    signal tb_sram1_d         : std_logic_vector(15 downto 0) := (others => 'Z');
+    signal tb_sram1_lb_n      : std_logic;
+    signal tb_sram1_ub_n      : std_logic;
+    signal tb_sram1_cs_n      : std_logic;     -- chip select
+    signal tb_sram1_we_n      : std_logic;     -- write-enable
+    signal tb_sram1_oe_n      : std_logic;     -- output enable
+    --
+    -- RS232
+    signal tb_rs232_rx        : std_logic                     := '1';
+    signal tb_rs232_tx        : std_logic;
+    signal tb_rs232_cts       : std_logic                     := '1';
+    signal tb_rs232_rts       : std_logic;
+    --
+    -- PS2 connectors
+    signal tb_mouse_clk       : std_logic                     := 'Z';
+    signal tb_mouse_data      : std_logic                     := 'Z';
+    signal tb_kbd_clk         : std_logic                     := 'Z';
+    signal tb_kbd_data        : std_logic                     := 'Z';
+    --
+    -- vga output
+    signal tb_vga_red         : std_logic_vector(7 downto 5);
+    signal tb_vga_green       : std_logic_vector(7 downto 5);
+    signal tb_vga_blue        : std_logic_vector(7 downto 5);
+    signal tb_vga_hsync       : std_logic;
+    signal tb_vga_vsync       : std_logic;
+    --
+    -- Audio out
+    signal tb_audio_r         : std_logic;
+    signal tb_audio_l         : std_logic;
+    --
+    -- GPIOs
+    signal tb_switch_n        : std_logic_vector(7 downto 0)  := (others => '1');
+    signal tb_button_n        : std_logic_vector(5 downto 0)  := (others => '1');
+    signal tb_led             : std_logic_vector(7 downto 0);
+    --
+    -- seven segment display
+    signal tb_dig0_seg        : std_logic_vector(7 downto 0);
+    signal tb_dig1_seg        : std_logic_vector(7 downto 0);
+    signal tb_dig2_seg        : std_logic_vector(7 downto 0);
+    signal tb_dig3_seg        : std_logic_vector(7 downto 0);
+    signal tb_dig4_seg        : std_logic_vector(7 downto 0);
+    signal tb_dig5_seg        : std_logic_vector(7 downto 0);
+    --
+    -- User Header A
+    signal tb_header_a        : std_logic_vector(19 downto 2) := (others => 'Z');
+    signal tb_header_b        : std_logic_vector(19 downto 2) := (others => 'Z');
+
+begin
+
+    -- generate clock
+    tb_clk <= not tb_clk after clk_period / 2 when simulation_run;
+
+    -- generate reset
+    tb_reset_n <= '0', '1' after 6.66 * clk_period;
+
+
+    -- simulate keypress
+    tb_button_n(2) <= '1', '0' after 50 us, '1' after 52 us;
+
+    -- dut
+    top_i0 : entity work.top
+        port map (
+            stop_simulation => tb_stop_simulation, -- : out   std_logic;
+            --
+            clk_50     => tb_clk,        -- : in    std_logic;
+            reset_n    => tb_reset_n,    -- : in    std_logic;
+            --
+            -- soft JTAG
+            soft_tdo   => tb_soft_tdo,   -- : out   std_logic;
+            soft_tms   => tb_soft_tms,   -- : in    std_logic;
+            soft_tdi   => tb_soft_tdi,   -- : in    std_logic;
+            soft_tck   => tb_soft_tck,   -- : in    std_logic;
+            --
+            -- SRAM 0 (256k x 16) pin connections
+            sram0_a    => tb_sram0_a,    -- : out   std_logic_vector(18 downto 0);
+            sram0_d    => tb_sram0_d,    -- : inout std_logic_vector(15 downto 0);
+            sram0_lb_n => tb_sram0_lb_n, -- : out   std_logic;
+            sram0_ub_n => tb_sram0_ub_n, -- : out   std_logic;
+            sram0_cs_n => tb_sram0_cs_n, -- : out   std_logic;       -- chip select
+            sram0_we_n => tb_sram0_we_n, -- : out   std_logic;       -- write-enable
+            sram0_oe_n => tb_sram0_oe_n, -- : out   std_logic;       -- output enable
+            --
+            -- SRAM 1 (256k x 16) pin connections
+            sram1_a    => tb_sram1_a,    -- : out   std_logic_vector(18 downto 0);
+            sram1_d    => tb_sram1_d,    -- : inout std_logic_vector(15 downto 0);
+            sram1_lb_n => tb_sram1_lb_n, -- : out   std_logic;
+            sram1_ub_n => tb_sram1_ub_n, -- : out   std_logic;
+            sram1_cs_n => tb_sram1_cs_n, -- : out   std_logic;       -- chip select
+            sram1_we_n => tb_sram1_we_n, -- : out   std_logic;       -- write-enable
+            sram1_oe_n => tb_sram1_oe_n, -- : out   std_logic;       -- output enable
+            --
+            -- RS232
+            rs232_rx   => tb_rs232_rx,   -- : in    std_logic;
+            rs232_tx   => tb_rs232_tx,   -- : out   std_logic;
+            rs232_cts  => tb_rs232_cts,  -- : in    std_logic;
+            rs232_rts  => tb_rs232_rts,  -- : out   std_logic;
+            --
+            -- PS2 connectors
+            mouse_clk  => tb_mouse_clk,  -- : inout std_logic;
+            mouse_data => tb_mouse_data, -- : inout std_logic;
+            kbd_clk    => tb_kbd_clk,    -- : inout std_logic;
+            kbd_data   => tb_kbd_data,   -- : inout std_logic;
+            --
+            -- vga output
+            vga_red    => tb_vga_red,    -- : out   std_logic_vector(7 downto 5);
+            vga_green  => tb_vga_green,  -- : out   std_logic_vector(7 downto 5);
+            vga_blue   => tb_vga_blue,   -- : out   std_logic_vector(7 downto 5);
+            vga_hsync  => tb_vga_hsync,  -- : out   std_logic;
+            vga_vsync  => tb_vga_vsync,  -- : out   std_logic;
+            --
+            -- Audio out
+            audio_r    => tb_audio_r,    -- : out   std_logic;
+            audio_l    => tb_audio_l,    -- : out   std_logic;
+            --
+            -- GPIOs
+            switch_n   => tb_switch_n,   -- : in    std_logic_vector(7 downto 0);
+            button_n   => tb_button_n,   -- : in    std_logic_vector(5 downto 0);
+            led        => tb_led,        -- : out   std_logic_vector(7 downto 0);
+            --
+            -- seven segment display
+            dig0_seg   => tb_dig0_seg,   -- : out   std_logic_vector(7 downto 0);
+            dig1_seg   => tb_dig1_seg,   -- : out   std_logic_vector(7 downto 0);
+            dig2_seg   => tb_dig2_seg,   -- : out   std_logic_vector(7 downto 0);
+            dig3_seg   => tb_dig3_seg,   -- : out   std_logic_vector(7 downto 0);
+            dig4_seg   => tb_dig4_seg,   -- : out   std_logic_vector(7 downto 0);
+            dig5_seg   => tb_dig5_seg,   -- : out   std_logic_vector(7 downto 0);
+            --
+            -- User Header
+            header_a   => tb_header_a,   -- : inout std_logic_vector(19 downto 2);
+            header_b   => tb_header_b    -- : inout std_logic_vector(19 downto 2)
+        );
+
+
+    -- check for simulation stopping
+    process (tb_stop_simulation)
+    begin
+        if tb_stop_simulation = '1' then
+            report "Simulation end." severity note;
+            simulation_run <= false;
+        end if;
+    end process;
+
+
+end architecture testbench;
+
-- 
cgit v1.1


From 221eb9f6525789d20f2895b2de775bf345cf97cb Mon Sep 17 00:00:00 2001
From: Bert Lange 
Date: Fri, 28 Oct 2011 11:25:31 +0200
Subject: minor fix: reduce simulation warnings at 0 ps

---
 zpu/hdl/zealot/devices/phi_io.vhdl                     | 4 ++--
 zpu/hdl/zealot/devices/timer.vhdl                      | 2 +-
 zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top.vhd | 2 +-
 zpu/hdl/zealot/zpu_small.vhdl                          | 8 ++++----
 4 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/zpu/hdl/zealot/devices/phi_io.vhdl b/zpu/hdl/zealot/devices/phi_io.vhdl
index 71e881c..6e40d1d 100644
--- a/zpu/hdl/zealot/devices/phi_io.vhdl
+++ b/zpu/hdl/zealot/devices/phi_io.vhdl
@@ -135,7 +135,7 @@ begin
          data_o => timer_read);
    
    busy_o   <= we_i or re_i;
-   is_timer <= '1' when addr_i=CNT_1 or addr_i=CNT_2 else '0'; -- 0x80A0014/8
+   is_timer <= '1' when to_01(addr_i)=CNT_1 or to_01(addr_i)=CNT_2 else '0'; -- 0x80A0014/8
    timer_we <= we_i and is_timer;
 
    ----------
@@ -186,7 +186,7 @@ begin
           port_out => gpio_out,           -- : std_logic_vector(31 downto 0);
           port_dir => gpio_dir            -- : std_logic_vector(31 downto 0);
           );
-   is_gpio <= '1' when addr_i = IO_DATA or addr_i = IO_DIR else '0'; -- 0x80A0004/8
+   is_gpio <= '1' when to_01(addr_i) = IO_DATA or to_01(addr_i) = IO_DIR else '0'; -- 0x80A0004/8
    gpio_we <= we_i and is_gpio;
 
 
diff --git a/zpu/hdl/zealot/devices/timer.vhdl b/zpu/hdl/zealot/devices/timer.vhdl
index f485e4d..389868c 100644
--- a/zpu/hdl/zealot/devices/timer.vhdl
+++ b/zpu/hdl/zealot/devices/timer.vhdl
@@ -85,7 +85,7 @@ begin
       end if; -- rising_edge(clk_i)
    end process do_timer;
 
-   data_o <= cnt_smp(31 downto  0) when addr_i="0" else
+   data_o <= cnt_smp(31 downto  0) when to_01(addr_i)="0" else
              cnt_smp(63 downto 32);
 end architecture Behave; -- Entity: Timer
  
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top.vhd b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top.vhd
index fbca62b..4a93c4f 100644
--- a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top.vhd
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top.vhd
@@ -102,7 +102,7 @@ architecture rtl of top is
 
     ---------------------------
     -- constant declarations
-    constant zpu_flavour   : zpu_type := zpu_small;  -- choose your flavour HERE
+    constant zpu_flavour   : zpu_type := zpu_medium;  -- choose your flavour HERE
     --  modify frequency here
     constant clk_multiply  : positive := 3; -- 9 for small, 3 for medium
     constant clk_divide    : positive := 2; -- 5 for small, 2 for medium
diff --git a/zpu/hdl/zealot/zpu_small.vhdl b/zpu/hdl/zealot/zpu_small.vhdl
index 2e5f464..056b924 100644
--- a/zpu/hdl/zealot/zpu_small.vhdl
+++ b/zpu/hdl/zealot/zpu_small.vhdl
@@ -148,13 +148,13 @@ begin
       -- Select the addressed byte inside the fetched word
       case (to_integer(pc_r(BYTE_BITS-1 downto 0))) is
            when 0 =>
-                topcode:=b_i(31 downto 24);
+                topcode := to_01( b_i(31 downto 24));
            when 1 =>
-                topcode:=b_i(23 downto 16);
+                topcode := to_01( b_i(23 downto 16));
            when 2 =>
-                topcode:=b_i(15 downto 8);
+                topcode := to_01( b_i(15 downto 8));
            when others => -- 3
-                topcode:=b_i(7 downto 0);
+                topcode := to_01( b_i(7 downto 0));
       end case;
       opcode <= topcode;
 
-- 
cgit v1.1


From 6f2e0ea6433ae0042e75bf668c5f10b77e6e2bf7 Mon Sep 17 00:00:00 2001
From: Bert Lange 
Date: Fri, 30 Mar 2012 08:59:26 +0200
Subject: change: rename 'State' to 'Insn'

---
 zpu/hdl/zpu4/core/zpu_core.vhd | 243 ++++++++++++++++++++---------------------
 1 file changed, 121 insertions(+), 122 deletions(-)

diff --git a/zpu/hdl/zpu4/core/zpu_core.vhd b/zpu/hdl/zpu4/core/zpu_core.vhd
index 1b95444..f423f80 100644
--- a/zpu/hdl/zpu4/core/zpu_core.vhd
+++ b/zpu/hdl/zpu4/core/zpu_core.vhd
@@ -79,48 +79,48 @@ entity zpu_core is
     );
 end zpu_core;
 
+
 architecture behave of zpu_core is
 
   type InsnType is (
-    State_AddTop,
-    State_Dup,
-    State_DupStackB,
-    State_Pop,
-    State_Popdown,
-    State_Add,
-    State_Or,
-    State_And,
-    State_Store,
-    State_AddSP,
-    State_Shift,
-    State_Nop,
-    State_Im,
-    State_LoadSP,
-    State_StoreSP,
-    State_Emulate,
-    State_Load,
-    State_PushPC,
-    State_PushSP,
-    State_PopPC,
-    State_PopPCRel,
-    State_Not,
-    State_Flip,
-    State_PopSP,
-    State_Neqbranch,
-    State_Eq,
-    State_Loadb,
-    State_Mult,
-    State_Lessthan,
-    State_Lessthanorequal,
-    State_Ulessthanorequal,
-    State_Ulessthan,
-    State_Pushspadd,
-    State_Call,
-    State_Callpcrel,
-    State_Sub,
-    State_Break,
-    State_Storeb,
-    State_InsnFetch
+    Insn_AddTop,
+    Insn_Dup,
+    Insn_DupStackB,
+    Insn_Pop,
+    Insn_PopDown,
+    Insn_Add,
+    Insn_Or,
+    Insn_And,
+    Insn_Store,
+    Insn_AddSP,
+    Insn_Shift,
+    Insn_Nop,
+    Insn_Im,
+    Insn_LoadSP,
+    Insn_StoreSP,
+    Insn_Emulate,
+    Insn_Load,
+    Insn_PushSP,
+    Insn_PopPC,
+    Insn_PopPCrel,
+    Insn_Not,
+    Insn_Flip,
+    Insn_PopSP,
+    Insn_Neqbranch,
+    Insn_Eq,
+    Insn_Loadb,
+    Insn_Mult,
+    Insn_Lessthan,
+    Insn_Lessthanorequal,
+    Insn_Ulessthanorequal,
+    Insn_Ulessthan,
+    Insn_PushSPadd,
+    Insn_Call,
+    Insn_CallPCrel,
+    Insn_Sub,
+    Insn_Break,
+    Insn_Storeb,
+    Insn_InsnFetch
     );
 
   type StateType is (
@@ -189,7 +189,6 @@ architecture behave of zpu_core is
 
 
 
-
   signal begin_inst        : std_logic;
   signal trace_opcode      : std_logic_vector(7 downto 0);
   signal trace_pc          : std_logic_vector(maxAddrBitIncIO downto 0);
@@ -235,7 +234,7 @@ begin
     variable spOffset       : unsigned(4 downto 0);
     variable tSpOffset      : unsigned(4 downto 0);
     variable nextPC         : unsigned(maxAddrBitIncIO downto 0);
-    variable tNextState     : InsnType;
+    variable tNextInsn      : InsnType;
     variable tDecodedOpcode : InsnArray;
     variable tMultResult    : unsigned(wordSize*2-1 downto 0);
   begin
@@ -253,7 +252,7 @@ begin
       multA           <= (others => '0');
       multB           <= (others => '0');
       mem_writeMask   <= (others => '1');
-    elsif (clk'event and clk = '1') then
+    elsif rising_edge(clk) then
       -- we must multiply unconditionally to get pipelined multiplication
       tMultResult := multA * multB;
       multResult3 <= multResult2;
@@ -366,99 +365,99 @@ begin
 
             opcode(i) <= tOpcode;
             if (tOpcode(7 downto 7) = OpCode_Im) then
-              tNextState := State_Im;
+              tNextInsn := Insn_Im;
             elsif (tOpcode(7 downto 5) = OpCode_StoreSP) then
               if tSpOffset = 0 then
-                tNextState := State_Pop;
+                tNextInsn := Insn_Pop;
               elsif tSpOffset = 1 then
-                tNextState := State_PopDown;
+                tNextInsn := Insn_PopDown;
               else
-                tNextState := State_StoreSP;
+                tNextInsn := Insn_StoreSP;
               end if;
             elsif (tOpcode(7 downto 5) = OpCode_LoadSP) then
               if tSpOffset = 0 then
-                tNextState := State_Dup;
+                tNextInsn := Insn_Dup;
               elsif tSpOffset = 1 then
-                tNextState := State_DupStackB;
+                tNextInsn := Insn_DupStackB;
               else
-                tNextState := State_LoadSP;
+                tNextInsn := Insn_LoadSP;
               end if;
             elsif (tOpcode(7 downto 5) = OpCode_Emulate) then
-              tNextState := State_Emulate;
+              tNextInsn := Insn_Emulate;
               if tOpcode(5 downto 0) = OpCode_Neqbranch then
-                tNextState := State_Neqbranch;
+                tNextInsn := Insn_Neqbranch;
               elsif tOpcode(5 downto 0) = OpCode_Eq then
-                tNextState := State_Eq;
+                tNextInsn := Insn_Eq;
               elsif tOpcode(5 downto 0) = OpCode_Lessthan then
-                tNextState := State_Lessthan;
+                tNextInsn := Insn_Lessthan;
               elsif tOpcode(5 downto 0) = OpCode_Lessthanorequal then
-                --tNextState :=State_Lessthanorequal;
+                --tNextInsn :=Insn_Lessthanorequal;
               elsif tOpcode(5 downto 0) = OpCode_Ulessthan then
-                tNextState := State_Ulessthan;
+                tNextInsn := Insn_Ulessthan;
               elsif tOpcode(5 downto 0) = OpCode_Ulessthanorequal then
-                --tNextState :=State_Ulessthanorequal;
+                --tNextInsn :=Insn_Ulessthanorequal;
               elsif tOpcode(5 downto 0) = OpCode_Loadb then
-                tNextState := State_Loadb;
+                tNextInsn := Insn_Loadb;
               elsif tOpcode(5 downto 0) = OpCode_Mult then
-                tNextState := State_Mult;
+                tNextInsn := Insn_Mult;
               elsif tOpcode(5 downto 0) = OpCode_Storeb then
-                tNextState := State_Storeb;
+                tNextInsn := Insn_Storeb;
               elsif tOpcode(5 downto 0) = OpCode_Pushspadd then
-                tNextState := State_Pushspadd;
+                tNextInsn := Insn_PushSPadd;
               elsif tOpcode(5 downto 0) = OpCode_Callpcrel then
-                tNextState := State_Callpcrel;
+                tNextInsn := Insn_CallPCrel;
               elsif tOpcode(5 downto 0) = OpCode_Call then
-                                        --tNextState :=State_Call;
+                --tNextInsn :=Insn_Call;
               elsif tOpcode(5 downto 0) = OpCode_Sub then
-                tNextState := State_Sub;
+                tNextInsn := Insn_Sub;
               elsif tOpcode(5 downto 0) = OpCode_PopPCRel then
-                                        --tNextState :=State_PopPCRel;
+                --tNextInsn :=Insn_PopPCrel;
               end if;
             elsif (tOpcode(7 downto 4) = OpCode_AddSP) then
               if tSpOffset = 0 then
-                tNextState := State_Shift;
+                tNextInsn := Insn_Shift;
               elsif tSpOffset = 1 then
-                tNextState := State_AddTop;
+                tNextInsn := Insn_AddTop;
               else
-                tNextState := State_AddSP;
+                tNextInsn := Insn_AddSP;
               end if;
             else
               case tOpcode(3 downto 0) is
                 when OpCode_Nop =>
-                  tNextState := State_Nop;
+                  tNextInsn := Insn_Nop;
                 when OpCode_PushSP =>
-                  tNextState := State_PushSP;
+                  tNextInsn := Insn_PushSP;
                 when OpCode_PopPC =>
-                  tNextState := State_PopPC;
+                  tNextInsn := Insn_PopPC;
                 when OpCode_Add =>
-                  tNextState := State_Add;
+                  tNextInsn := Insn_Add;
                 when OpCode_Or =>
-                  tNextState := State_Or;
+                  tNextInsn := Insn_Or;
                 when OpCode_And =>
-                  tNextState := State_And;
+                  tNextInsn := Insn_And;
                 when OpCode_Load =>
-                  tNextState := State_Load;
+                  tNextInsn := Insn_Load;
                 when OpCode_Not =>
-                  tNextState := State_Not;
+                  tNextInsn := Insn_Not;
                 when OpCode_Flip =>
-                  tNextState := State_Flip;
+                  tNextInsn := Insn_Flip;
                 when OpCode_Store =>
-                  tNextState := State_Store;
+                  tNextInsn := Insn_Store;
                 when OpCode_PopSP =>
-                  tNextState := State_PopSP;
+                  tNextInsn := Insn_PopSP;
                 when others =>
-                  tNextState := State_Break;
+                  tNextInsn := Insn_Break;
 
               end case; -- tOpcode(3 downto 0)
             end if; -- tOpcode
-            tDecodedOpcode(i) := tNextState;
+            tDecodedOpcode(i) := tNextInsn;
             
           end loop; -- 0 to wordBytes-1
 
           insn <= tDecodedOpcode(to_integer(pc(byteBits-1 downto 0)));
 
           -- once we wrap, we need to fetch
-          tDecodedOpcode(0) := State_InsnFetch;
+          tDecodedOpcode(0) := Insn_InsnFetch;
 
           decodedOpcode <= tDecodedOpcode;
           state         <= State_Execute;
@@ -468,7 +467,7 @@ begin
           -- Each instruction must:
           --
           -- 1. set idim_flag
-          -- 2. increase pc if applicable
+          -- 2. increase PC if applicable
           -- 3. set next state if appliable
           -- 4. do it's operation
           
@@ -477,10 +476,10 @@ begin
 
           case insn is
 
-            when State_InsnFetch =>
+            when Insn_InsnFetch =>
               state <= State_Fetch;
 
-            when State_Im =>
+            when Insn_Im =>
               if in_mem_busy = '0' then
                 begin_inst <= '1';
                 idim_flag  <= '1';
@@ -502,7 +501,7 @@ begin
                 end if; -- idim_flag
               end if; -- in_mem_busy
 
-            when State_StoreSP =>
+            when Insn_StoreSP =>
               if in_mem_busy = '0' then
                 begin_inst <= '1';
                 idim_flag  <= '0';
@@ -516,7 +515,7 @@ begin
               end if;
 
               
-            when State_LoadSP =>
+            when Insn_LoadSP =>
               if in_mem_busy = '0' then
                 begin_inst <= '1';
                 idim_flag  <= '0';
@@ -528,7 +527,7 @@ begin
                 mem_write       <= std_logic_vector(stackB);
               end if;
 
-            when State_Emulate =>
+            when Insn_Emulate =>
               if in_mem_busy = '0' then
                 begin_inst                       <= '1';
                 idim_flag                        <= '0';
@@ -548,7 +547,7 @@ begin
                 state          <= State_Fetch;
               end if; -- in_mem_busy
 
-            when State_Callpcrel =>
+            when Insn_CallPCrel =>
               if in_mem_busy = '0' then
                 begin_inst                       <= '1';
                 idim_flag                        <= '0';
@@ -559,7 +558,7 @@ begin
                 state <= State_Fetch;
               end if;
 
-            when State_Call =>
+            when Insn_Call =>
               if in_mem_busy = '0' then
                 begin_inst                       <= '1';
                 idim_flag                        <= '0';
@@ -569,7 +568,7 @@ begin
                 state                            <= State_Fetch;
               end if;
 
-            when State_AddSP =>
+            when Insn_AddSP =>
               if in_mem_busy = '0' then
                 begin_inst <= '1';
                 idim_flag  <= '0';
@@ -579,7 +578,7 @@ begin
                 mem_addr       <= std_logic_vector(sp+spOffset);
               end if;
 
-            when State_PushSP =>
+            when Insn_PushSP =>
               if in_mem_busy = '0' then
                 begin_inst <= '1';
                 idim_flag  <= '0';
@@ -594,7 +593,7 @@ begin
                 mem_write                                 <= std_logic_vector(stackB);
               end if;
 
-            when State_PopPC =>
+            when Insn_PopPC =>
               if in_mem_busy = '0' then
                 begin_inst <= '1';
                 idim_flag  <= '0';
@@ -607,7 +606,7 @@ begin
                 state           <= State_Resync;
               end if;
 
-            when State_PopPCRel =>
+            when Insn_PopPCrel =>
               if in_mem_busy = '0' then
                 begin_inst <= '1';
                 idim_flag  <= '0';
@@ -620,7 +619,7 @@ begin
                 state           <= State_Resync;
               end if;
 
-            when State_Add =>
+            when Insn_Add =>
               if in_mem_busy = '0' then
                 begin_inst <= '1';
                 idim_flag  <= '0';
@@ -632,7 +631,7 @@ begin
                 state          <= State_Popped;
               end if;
 
-            when State_Sub =>
+            when Insn_Sub =>
               if in_mem_busy = '0' then
                 begin_inst     <= '1';
                 idim_flag      <= '0';
@@ -640,7 +639,7 @@ begin
                 state          <= State_BinaryOpResult;
               end if;
 
-            when State_Pop =>
+            when Insn_Pop =>
               if in_mem_busy = '0' then
                 begin_inst     <= '1';
                 idim_flag      <= '0';
@@ -651,7 +650,7 @@ begin
                 state          <= State_Popped;
               end if;
 
-            when State_PopDown =>
+            when Insn_PopDown =>
               if in_mem_busy = '0' then
                                         -- PopDown leaves top of stack unchanged
                 begin_inst     <= '1';
@@ -662,7 +661,7 @@ begin
                 state          <= State_Popped;
               end if;
 
-            when State_Or =>
+            when Insn_Or =>
               if in_mem_busy = '0' then
                 begin_inst     <= '1';
                 idim_flag      <= '0';
@@ -673,7 +672,7 @@ begin
                 state          <= State_Popped;
               end if;
 
-            when State_And =>
+            when Insn_And =>
               if in_mem_busy = '0' then
                 begin_inst <= '1';
                 idim_flag  <= '0';
@@ -685,7 +684,7 @@ begin
                 state          <= State_Popped;
               end if;
 
-            when State_Eq =>
+            when Insn_Eq =>
               if in_mem_busy = '0' then
                 begin_inst <= '1';
                 idim_flag  <= '0';
@@ -697,7 +696,7 @@ begin
                 state <= State_BinaryOpResult;
               end if;
 
-            when State_Ulessthan =>
+            when Insn_Ulessthan =>
               if in_mem_busy = '0' then
                 begin_inst <= '1';
                 idim_flag  <= '0';
@@ -709,7 +708,7 @@ begin
                 state <= State_BinaryOpResult;
               end if;
 
-            when State_Ulessthanorequal =>
+            when Insn_Ulessthanorequal =>
               if in_mem_busy = '0' then
                 begin_inst <= '1';
                 idim_flag  <= '0';
@@ -721,7 +720,7 @@ begin
                 state <= State_BinaryOpResult;
               end if;
 
-            when State_Lessthan =>
+            when Insn_Lessthan =>
               if in_mem_busy = '0' then
                 begin_inst <= '1';
                 idim_flag  <= '0';
@@ -733,7 +732,7 @@ begin
                 state <= State_BinaryOpResult;
               end if;
 
-            when State_Lessthanorequal =>
+            when Insn_Lessthanorequal =>
               if in_mem_busy = '0' then
                 begin_inst <= '1';
                 idim_flag  <= '0';
@@ -745,7 +744,7 @@ begin
                 state <= State_BinaryOpResult;
               end if;
 
-            when State_Load =>
+            when Insn_Load =>
               if in_mem_busy = '0' then
                 begin_inst <= '1';
                 idim_flag  <= '0';
@@ -755,7 +754,7 @@ begin
                 mem_readEnable <= '1';
               end if;
 
-            when State_Dup =>
+            when Insn_Dup =>
               if in_mem_busy = '0' then
                 begin_inst <= '1';
                 idim_flag  <= '0';
@@ -768,7 +767,7 @@ begin
                 mem_writeEnable <= '1';
               end if;
 
-            when State_DupStackB =>
+            when Insn_DupStackB =>
               if in_mem_busy = '0' then
                 begin_inst <= '1';
                 idim_flag  <= '0';
@@ -782,7 +781,7 @@ begin
                 mem_writeEnable <= '1';
               end if;
 
-            when State_Store =>
+            when Insn_Store =>
               if in_mem_busy = '0' then
                 begin_inst      <= '1';
                 idim_flag       <= '0';
@@ -794,7 +793,7 @@ begin
                 state           <= State_Resync;
               end if;
 
-            when State_PopSP =>
+            when Insn_PopSP =>
               if in_mem_busy = '0' then
                 begin_inst <= '1';
                 idim_flag  <= '0';
@@ -807,19 +806,19 @@ begin
                 state           <= State_Resync;
               end if;
 
-            when State_Nop =>
+            when Insn_Nop =>
               begin_inst <= '1';
               idim_flag  <= '0';
               pc         <= pc + 1;
 
-            when State_Not =>
+            when Insn_Not =>
               begin_inst <= '1';
               idim_flag  <= '0';
               pc         <= pc + 1;
 
-              stackA <= not stackA;
+              stackA     <= not stackA;
 
-            when State_Flip =>
+            when Insn_Flip =>
               begin_inst <= '1';
               idim_flag  <= '0';
               pc         <= pc + 1;
@@ -828,14 +827,14 @@ begin
                 stackA(i) <= stackA(wordSize-1-i);
               end loop;
 
-            when State_AddTop =>
+            when Insn_AddTop =>
               begin_inst <= '1';
               idim_flag  <= '0';
               pc         <= pc + 1;
 
-              stackA <= stackA + stackB;
+              stackA     <= stackA + stackB;
 
-            when State_Shift =>
+            when Insn_Shift =>
               begin_inst <= '1';
               idim_flag  <= '0';
               pc         <= pc + 1;
@@ -843,7 +842,7 @@ begin
               stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0);
               stackA(0)                   <= '0';
 
-            when State_Pushspadd =>
+            when Insn_PushSPadd =>
               begin_inst <= '1';
               idim_flag  <= '0';
               pc         <= pc + 1;
@@ -851,7 +850,7 @@ begin
               stackA                                    <= (others => '0');
               stackA(maxAddrBitIncIO downto minAddrBit) <= stackA(maxAddrBitIncIO-minAddrBit downto 0)+sp;
 
-            when State_Neqbranch =>
+            when Insn_Neqbranch =>
               -- branches are almost always taken as they form loops
               begin_inst <= '1';
               idim_flag  <= '0';
@@ -864,7 +863,7 @@ begin
               -- need to fetch stack again.                           
               state <= State_Resync;
 
-            when State_Mult =>
+            when Insn_Mult =>
               begin_inst <= '1';
               idim_flag  <= '0';
 
@@ -872,11 +871,11 @@ begin
               multB <= stackB;
               state <= State_Mult2;
 
-            when State_Break =>
+            when Insn_Break =>
               report "Break instruction encountered" severity failure;
               break <= '1';
 
-            when State_Loadb =>
+            when Insn_Loadb =>
               if in_mem_busy = '0' then
                 begin_inst <= '1';
                 idim_flag  <= '0';
@@ -886,7 +885,7 @@ begin
                 mem_readEnable <= '1';
               end if;
 
-            when State_Storeb =>
+            when Insn_Storeb =>
               if in_mem_busy = '0' then
                 begin_inst <= '1';
                 idim_flag  <= '0';
-- 
cgit v1.1


From b1bba840534b2e9a6f79564b006843b0e268e475 Mon Sep 17 00:00:00 2001
From: Bert Lange 
Date: Thu, 16 May 2013 09:16:33 +0200
Subject: fix: opcode numbering

---
 zpu/docs/zpu_arch.html | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html
index 32a3ca2..15b9ccf 100644
--- a/zpu/docs/zpu_arch.html
+++ b/zpu/docs/zpu_arch.html
@@ -948,7 +948,7 @@ int address = pop();
            
        NEQ
     
     
-      48
+      47
     
     
  pushIntStack((popIntStack() != popIntStack()) ? 1 : 0);    
@@ -960,7 +960,7 @@ int address = pop();
            
        NEG
     
     
-      47
+      48
     
     
  pushIntStack(-popIntStack());
-- 
cgit v1.1


From 8679e4f91dcae05aef40f96629f33f0f4161f14a Mon Sep 17 00:00:00 2001
From: Bert Lange 
Date: Fri, 11 Jul 2014 14:13:10 +0200
Subject: add: performance values for Lattice MachXO2

---
 zpu/docs/zpu_arch.html | 29 +++++++++++++++--------------
 1 file changed, 15 insertions(+), 14 deletions(-)

diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html
index 15b9ccf..62acdfa 100644
--- a/zpu/docs/zpu_arch.html
+++ b/zpu/docs/zpu_arch.html
@@ -1061,10 +1061,11 @@ For now if you are starting a design, zpu4 or zealot are probably the safest.  z
 
 
            Performance Summary
            
 
-            TODO fill in performance table for Altera and Lattice.
+TODO fill in performance table for Altera.
 
            
 Tests are done with the Zealot
  SoC-System and Xilinx ISE 12.2 with standard settings.
+ For the MachXO2 device Lattice Diamond 3.1 with Synplify Pro I-2013.09L was used.
 
            
 
@@ -1073,7 +1074,7 @@ Tests are done with the Zealot
-      
+      
     
@@ -1115,12 +1116,12 @@ maxAddrBit=16
 175 fmax
 
@@ -1159,12 +1160,12 @@ maxAddrBit=16
  125 fmax
 
-- 
cgit v1.1


            
     
            
        
            Spartan-3E
                         		
        
            Spartan-6
                         		
        
            Virtex-5
                         		 
            Cyclone-3
                         		 
            MachXO2
                         		
        
            DMIPS
                         		
     
             
 
             
            -
-? LUT
-? REG
-? MULT18x18
-? M4K
-? fmax
+
+886 LUT4
+459 REG
+
+4   EBR
+75  fmax
 
                         		
   
            0.5
                         		
 
             
 
             
            -
-? LUT
-? REG
-? MULT18x18
-? M4K
-? fmax
+
+2429 LUT4
+755  REG
+
+4    EBR
+65   fmax
 
                         		
 
            2.6