From 662a6952bc04419ac063cf3eb2b5917978eec0a1 Mon Sep 17 00:00:00 2001 From: Bert Lange Date: Fri, 28 Oct 2011 10:59:45 +0200 Subject: add: Spartan3 reference design for zealot --- .../fpga/altium-livedesign-xc3s1000/clean_up.sh | 16 + .../fpga/altium-livedesign-xc3s1000/simulation.sh | 49 +++ .../simulation_config/run.do | 2 + .../simulation_config/wave.do | 30 ++ .../fpga/altium-livedesign-xc3s1000/synthesis.sh | 36 ++ .../altium-livedesign-xc3s1000.ucf | 397 +++++++++++++++++++++ .../synthesis_config/top.prj | 19 + .../synthesis_config/top.ut | 29 ++ .../synthesis_config/top.xst | 56 +++ .../zealot/fpga/altium-livedesign-xc3s1000/top.vhd | 372 +++++++++++++++++++ .../fpga/altium-livedesign-xc3s1000/top_tb.vhd | 194 ++++++++++ 11 files changed, 1200 insertions(+) create mode 100755 zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/clean_up.sh create mode 100755 zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation.sh create mode 100644 zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/run.do create mode 100644 zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/wave.do create mode 100755 zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis.sh create mode 100644 zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/altium-livedesign-xc3s1000.ucf create mode 100644 zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.prj create mode 100644 zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.ut create mode 100644 zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.xst create mode 100644 zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top.vhd create mode 100644 zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top_tb.vhd diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/clean_up.sh b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/clean_up.sh new file mode 100755 index 0000000..3855f16 --- /dev/null +++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/clean_up.sh @@ -0,0 +1,16 @@ +#!/bin/sh + +# ise build stuff +rm -rf build +rm -f top.bit + +# modelsim compile stuff +rm -rf work +rm -rf zpu + +# modelsim simulation stuff +rm -f vsim.wlf +rm -f transcript +rm -f zpu_trace.log +rm -f zpu_med1_io.log +rm -f zpu_small1_io.log diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation.sh b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation.sh new file mode 100755 index 0000000..d525737 --- /dev/null +++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation.sh @@ -0,0 +1,49 @@ +#!/bin/sh + +# need project files: +# run.do +# wave.do + +# need ModelSim tools: +# vlib +# vcom +# vsim + + +echo "###############" +echo "compile zpu lib" +echo "###############" +vlib zpu +vcom -work zpu ../../roms/hello_dbram.vhdl +vcom -work zpu ../../roms/hello_bram.vhdl +#vcom -work zpu ../../roms/dmips_dbram.vhdl +#vcom -work zpu ../../roms/dmips_bram.vhdl + +vcom -work zpu ../../roms/rom_pkg.vhdl +vcom -work zpu ../../zpu_pkg.vhdl +vcom -work zpu ../../zpu_small.vhdl +vcom -work zpu ../../zpu_medium.vhdl +vcom -work zpu ../../helpers/zpu_small1.vhdl +vcom -work zpu ../../helpers/zpu_med1.vhdl +vcom -work zpu ../../devices/txt_util.vhdl +vcom -work zpu ../../devices/phi_io.vhdl +vcom -work zpu ../../devices/timer.vhdl +vcom -work zpu ../../devices/gpio.vhdl +vcom -work zpu ../../devices/rx_unit.vhdl +vcom -work zpu ../../devices/tx_unit.vhdl +vcom -work zpu ../../devices/br_gen.vhdl +vcom -work zpu ../../devices/trace.vhdl + + +echo "################" +echo "compile work lib" +echo "################" +vlib work +vcom top.vhd +vcom top_tb.vhd + + +echo "###################" +echo "start simulator gui" +echo "###################" +vsim -gui top_tb -do simulation_config/run.do diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/run.do b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/run.do new file mode 100644 index 0000000..acc1710 --- /dev/null +++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/run.do @@ -0,0 +1,2 @@ +do wave.do +run -all diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/wave.do b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/wave.do new file mode 100644 index 0000000..3f5d4fe --- /dev/null +++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/wave.do @@ -0,0 +1,30 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /top_tb/tb_reset_n +add wave -noupdate /top_tb/tb_clk +add wave -noupdate -divider +add wave -noupdate /top_tb/tb_rs232_rx +add wave -noupdate /top_tb/tb_rs232_tx +add wave -noupdate /top_tb/tb_rs232_rts +add wave -noupdate /top_tb/tb_rs232_cts +add wave -noupdate -divider Buttons +add wave -noupdate /top_tb/tb_button_n +add wave -noupdate -divider LEDs +add wave -noupdate /top_tb/tb_led +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 ps} 0} +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 2 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {1294218073 ps} {1421130628 ps} diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis.sh b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis.sh new file mode 100755 index 0000000..a7180fc --- /dev/null +++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis.sh @@ -0,0 +1,36 @@ +#!/bin/sh + +# need project files: +# top.xst +# top.prj +# top.ut + +# need Xilinx tools: +# xst +# ngdbuild +# map +# par +# trce +# bitgen + +echo "########################" +echo "generate build directory" +echo "########################" +mkdir build +cd build +mkdir tmp + +echo "###############" +echo "start processes" +echo "###############" +xst -ifn "../synthesis_config/top.xst" -ofn "top.syr" +ngdbuild -dd _ngo -nt timestamp -uc ../synthesis_config/altium-livedesign-xc3s1000.ucf -p xc3s1000-fg456-4 top.ngc top.ngd +map -p xc3s1000-fg456-4 -cm area -ir off -pr off -c 100 -o top_map.ncd top.ngd top.pcf +par -w -ol high -t 1 top_map.ncd top.ncd top.pcf +trce -v 3 -s 4 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf +bitgen -f ../synthesis_config/top.ut top.ncd + +echo "###########" +echo "get bitfile" +echo "###########" +cp top.bit .. diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/altium-livedesign-xc3s1000.ucf b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/altium-livedesign-xc3s1000.ucf new file mode 100644 index 0000000..ba22ee9 --- /dev/null +++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/altium-livedesign-xc3s1000.ucf @@ -0,0 +1,397 @@ +############################################################ +# Altium Livedesign Evaluation Board constraints file +# +# Familiy: Spartan-3 +# Device: XC3S1000 +# Package: FG456C +# Speed: -4 +# +# all banks are powered with 3.3V +# +# config pins (M2, M1, M0): 101 + +############################################################ +## clock/timing constraints +############################################################ + +NET "clk_50" period = 50 MHz ; + + +############################################################ +## pin placement constraints +############################################################ + +NET "clk_50" LOC = AA12 | IOSTANDARD = LVCMOS33; +NET "reset_n" LOC = Y17 | IOSTANDARD = LVCMOS33; # low active + +# Soft JTAG +NET "soft_tdo" LOC = D22 | IOSTANDARD = LVCMOS33; +NET "soft_tms" LOC = E21 | IOSTANDARD = LVCMOS33; +NET "soft_tdi" LOC = E22 | IOSTANDARD = LVCMOS33; +NET "soft_tck" LOC = F21 | IOSTANDARD = LVCMOS33; + +# SRAM 0 +NET "sram0_a<0>" LOC = L6 | IOSTANDARD = LVCMOS33; +NET "sram0_a<1>" LOC = K4 | IOSTANDARD = LVCMOS33; +NET "sram0_a<2>" LOC = H5 | IOSTANDARD = LVCMOS33; +NET "sram0_a<3>" LOC = G6 | IOSTANDARD = LVCMOS33; +NET "sram0_a<4>" LOC = F3 | IOSTANDARD = LVCMOS33; +NET "sram0_a<5>" LOC = G1 | IOSTANDARD = LVCMOS33; +NET "sram0_a<6>" LOC = G2 | IOSTANDARD = LVCMOS33; +NET "sram0_a<7>" LOC = K3 | IOSTANDARD = LVCMOS33; +NET "sram0_a<8>" LOC = T2 | IOSTANDARD = LVCMOS33; +NET "sram0_a<9>" LOC = T1 | IOSTANDARD = LVCMOS33; +NET "sram0_a<10>" LOC = U2 | IOSTANDARD = LVCMOS33; +NET "sram0_a<11>" LOC = V3 | IOSTANDARD = LVCMOS33; +NET "sram0_a<12>" LOC = V1 | IOSTANDARD = LVCMOS33; +NET "sram0_a<13>" LOC = W1 | IOSTANDARD = LVCMOS33; +NET "sram0_a<14>" LOC = V2 | IOSTANDARD = LVCMOS33; +NET "sram0_a<15>" LOC = V5 | IOSTANDARD = LVCMOS33; +NET "sram0_a<16>" LOC = V4 | IOSTANDARD = LVCMOS33; +NET "sram0_a<17>" LOC = U5 | IOSTANDARD = LVCMOS33; +NET "sram0_a<18>" LOC = U6 | IOSTANDARD = LVCMOS33; # n.c. +NET "sram0_d<0>" LOC = L4 | IOSTANDARD = LVCMOS33; +NET "sram0_d<1>" LOC = L3 | IOSTANDARD = LVCMOS33; +NET "sram0_d<2>" LOC = M5 | IOSTANDARD = LVCMOS33; +NET "sram0_d<3>" LOC = M4 | IOSTANDARD = LVCMOS33; +NET "sram0_d<4>" LOC = M3 | IOSTANDARD = LVCMOS33; +NET "sram0_d<5>" LOC = N4 | IOSTANDARD = LVCMOS33; +NET "sram0_d<6>" LOC = N3 | IOSTANDARD = LVCMOS33; +NET "sram0_d<7>" LOC = T5 | IOSTANDARD = LVCMOS33; +NET "sram0_d<8>" LOC = T4 | IOSTANDARD = LVCMOS33; +NET "sram0_d<9>" LOC = T6 | IOSTANDARD = LVCMOS33; +NET "sram0_d<10>" LOC = M6 | IOSTANDARD = LVCMOS33; +NET "sram0_d<11>" LOC = N2 | IOSTANDARD = LVCMOS33; +NET "sram0_d<12>" LOC = N1 | IOSTANDARD = LVCMOS33; +NET "sram0_d<13>" LOC = M2 | IOSTANDARD = LVCMOS33; +NET "sram0_d<14>" LOC = M1 | IOSTANDARD = LVCMOS33; +NET "sram0_d<15>" LOC = L2 | IOSTANDARD = LVCMOS33; +NET "sram0_cs_n" LOC = L5 | IOSTANDARD = LVCMOS33; +NET "sram0_lb_n" LOC = L1 | IOSTANDARD = LVCMOS33; +NET "sram0_ub_n" LOC = K2 | IOSTANDARD = LVCMOS33; +NET "sram0_we_n" LOC = U4 | IOSTANDARD = LVCMOS33; +NET "sram0_oe_n" LOC = K1 | IOSTANDARD = LVCMOS33; + +# SRAM 1 +NET "sram1_a<0>" LOC = K21 | IOSTANDARD = LVCMOS33; +NET "sram1_a<1>" LOC = K22 | IOSTANDARD = LVCMOS33; +NET "sram1_a<2>" LOC = K20 | IOSTANDARD = LVCMOS33; +NET "sram1_a<3>" LOC = G21 | IOSTANDARD = LVCMOS33; +NET "sram1_a<4>" LOC = G22 | IOSTANDARD = LVCMOS33; +NET "sram1_a<5>" LOC = M17 | IOSTANDARD = LVCMOS33; +NET "sram1_a<6>" LOC = L18 | IOSTANDARD = LVCMOS33; +NET "sram1_a<7>" LOC = K19 | IOSTANDARD = LVCMOS33; +NET "sram1_a<8>" LOC = V19 | IOSTANDARD = LVCMOS33; +NET "sram1_a<9>" LOC = W20 | IOSTANDARD = LVCMOS33; +NET "sram1_a<10>" LOC = W19 | IOSTANDARD = LVCMOS33; +NET "sram1_a<11>" LOC = Y20 | IOSTANDARD = LVCMOS33; +NET "sram1_a<12>" LOC = Y21 | IOSTANDARD = LVCMOS33; +NET "sram1_a<13>" LOC = Y22 | IOSTANDARD = LVCMOS33; +NET "sram1_a<14>" LOC = W21 | IOSTANDARD = LVCMOS33; +NET "sram1_a<15>" LOC = W22 | IOSTANDARD = LVCMOS33; +NET "sram1_a<16>" LOC = V21 | IOSTANDARD = LVCMOS33; +NET "sram1_a<17>" LOC = V22 | IOSTANDARD = LVCMOS33; +NET "sram1_a<18>" LOC = V20 | IOSTANDARD = LVCMOS33; # n.c. +NET "sram1_d<0>" LOC = L21 | IOSTANDARD = LVCMOS33; +NET "sram1_d<1>" LOC = M22 | IOSTANDARD = LVCMOS33; +NET "sram1_d<2>" LOC = M21 | IOSTANDARD = LVCMOS33; +NET "sram1_d<3>" LOC = N22 | IOSTANDARD = LVCMOS33; +NET "sram1_d<4>" LOC = N21 | IOSTANDARD = LVCMOS33; +NET "sram1_d<5>" LOC = U20 | IOSTANDARD = LVCMOS33; +NET "sram1_d<6>" LOC = T22 | IOSTANDARD = LVCMOS33; +NET "sram1_d<7>" LOC = T21 | IOSTANDARD = LVCMOS33; +NET "sram1_d<8>" LOC = V18 | IOSTANDARD = LVCMOS33; +NET "sram1_d<9>" LOC = U19 | IOSTANDARD = LVCMOS33; +NET "sram1_d<10>" LOC = U18 | IOSTANDARD = LVCMOS33; +NET "sram1_d<11>" LOC = T18 | IOSTANDARD = LVCMOS33; +NET "sram1_d<12>" LOC = R18 | IOSTANDARD = LVCMOS33; +NET "sram1_d<13>" LOC = T17 | IOSTANDARD = LVCMOS33; +NET "sram1_d<14>" LOC = M18 | IOSTANDARD = LVCMOS33; +NET "sram1_d<15>" LOC = M20 | IOSTANDARD = LVCMOS33; +NET "sram1_cs_n" LOC = L22 | IOSTANDARD = LVCMOS33; +NET "sram1_lb_n" LOC = M19 | IOSTANDARD = LVCMOS33; +NET "sram1_ub_n" LOC = L20 | IOSTANDARD = LVCMOS33; +NET "sram1_we_n" LOC = U21 | IOSTANDARD = LVCMOS33; +NET "sram1_oe_n" LOC = L19 | IOSTANDARD = LVCMOS33; + +# RS232 +NET "rs232_rx" LOC = A5 | IOSTANDARD = LVCMOS33; +NET "rs232_tx" LOC = F7 | IOSTANDARD = LVCMOS33; +NET "rs232_cts" LOC = F2 | IOSTANDARD = LVCMOS33; +NET "rs232_rts" LOC = E1 | IOSTANDARD = LVCMOS33; + +# 2x PS2 connectors +NET "mouse_clk" LOC = L17 | IOSTANDARD = LVCMOS33; +NET "mouse_data" LOC = G18 | IOSTANDARD = LVCMOS33; +NET "kbd_clk" LOC = F20 | IOSTANDARD = LVCMOS33; +NET "kbd_data" LOC = G19 | IOSTANDARD = LVCMOS33; + + +# VGA output (2**9 = 512 colors) +NET "vga_blue<7>" LOC = E14 | IOSTANDARD = LVCMOS33; +NET "vga_blue<6>" LOC = A13 | IOSTANDARD = LVCMOS33; +NET "vga_blue<5>" LOC = C13 | IOSTANDARD = LVCMOS33; +NET "vga_green<7>" LOC = E11 | IOSTANDARD = LVCMOS33; +NET "vga_green<6>" LOC = C11 | IOSTANDARD = LVCMOS33; +NET "vga_green<5>" LOC = D10 | IOSTANDARD = LVCMOS33; +NET "vga_red<7>" LOC = D6 | IOSTANDARD = LVCMOS33; +NET "vga_red<6>" LOC = D7 | IOSTANDARD = LVCMOS33; +NET "vga_red<5>" LOC = D9 | IOSTANDARD = LVCMOS33; +NET "vga_hsync" LOC = A8 | IOSTANDARD = LVCMOS33; +NET "vga_vsync" LOC = B14 | IOSTANDARD = LVCMOS33; + + +# Stereo Audio out +NET "audio_r" LOC = U3 | IOSTANDARD = LVCMOS33; +NET "audio_l" LOC = W3 | IOSTANDARD = LVCMOS33; + + +# GPIO DIP switches 7..0 left..right, low active +NET "switch_n<0>" LOC = Y6 | IOSTANDARD = LVCMOS33; +NET "switch_n<1>" LOC = V6 | IOSTANDARD = LVCMOS33; +NET "switch_n<2>" LOC = U7 | IOSTANDARD = LVCMOS33; +NET "switch_n<3>" LOC = AA4 | IOSTANDARD = LVCMOS33; +NET "switch_n<4>" LOC = AB4 | IOSTANDARD = LVCMOS33; +NET "switch_n<5>" LOC = AA5 | IOSTANDARD = LVCMOS33; +NET "switch_n<6>" LOC = AB5 | IOSTANDARD = LVCMOS33; +NET "switch_n<7>" LOC = AA6 | IOSTANDARD = LVCMOS33; + +# GPIO push buttons, low active +NET "button_n<5>" LOC = C21 | IOSTANDARD = LVCMOS33; +NET "button_n<4>" LOC = B20 | IOSTANDARD = LVCMOS33; +NET "button_n<3>" LOC = A15 | IOSTANDARD = LVCMOS33; +NET "button_n<2>" LOC = B6 | IOSTANDARD = LVCMOS33; +NET "button_n<1>" LOC = C1 | IOSTANDARD = LVCMOS33; +NET "button_n<0>" LOC = D1 | IOSTANDARD = LVCMOS33; + +# GPIO LEDs +NET "led<7>" LOC = W6 | IOSTANDARD = LVCMOS33; +NET "led<6>" LOC = Y5 | IOSTANDARD = LVCMOS33; +NET "led<5>" LOC = W5 | IOSTANDARD = LVCMOS33; +NET "led<4>" LOC = W4 | IOSTANDARD = LVCMOS33; +NET "led<3>" LOC = Y3 | IOSTANDARD = LVCMOS33; +NET "led<2>" LOC = Y2 | IOSTANDARD = LVCMOS33; +NET "led<1>" LOC = Y1 | IOSTANDARD = LVCMOS33; +NET "led<0>" LOC = W2 | IOSTANDARD = LVCMOS33; + +# seven segment display (5=left 0=right) +# +# segment assignment: +# .ABCDEFG +# 76543210 +NET "dig0_seg<7>" LOC = E20 | IOSTANDARD = LVCMOS33; +NET "dig0_seg<6>" LOC = C22 | IOSTANDARD = LVCMOS33; +NET "dig0_seg<5>" LOC = E18 | IOSTANDARD = LVCMOS33; +NET "dig0_seg<4>" LOC = D20 | IOSTANDARD = LVCMOS33; +NET "dig0_seg<3>" LOC = D21 | IOSTANDARD = LVCMOS33; +NET "dig0_seg<2>" LOC = E19 | IOSTANDARD = LVCMOS33; +NET "dig0_seg<1>" LOC = G17 | IOSTANDARD = LVCMOS33; +NET "dig0_seg<0>" LOC = F19 | IOSTANDARD = LVCMOS33; + +NET "dig1_seg<7>" LOC = F17 | IOSTANDARD = LVCMOS33; +NET "dig1_seg<6>" LOC = D18 | IOSTANDARD = LVCMOS33; +NET "dig1_seg<5>" LOC = B19 | IOSTANDARD = LVCMOS33; +NET "dig1_seg<4>" LOC = C18 | IOSTANDARD = LVCMOS33; +NET "dig1_seg<3>" LOC = C19 | IOSTANDARD = LVCMOS33; +NET "dig1_seg<2>" LOC = C20 | IOSTANDARD = LVCMOS33; +NET "dig1_seg<1>" LOC = F18 | IOSTANDARD = LVCMOS33; +NET "dig1_seg<0>" LOC = D19 | IOSTANDARD = LVCMOS33; + +NET "dig2_seg<7>" LOC = A19 | IOSTANDARD = LVCMOS33; +NET "dig2_seg<6>" LOC = E17 | IOSTANDARD = LVCMOS33; +NET "dig2_seg<5>" LOC = C17 | IOSTANDARD = LVCMOS33; +NET "dig2_seg<4>" LOC = D17 | IOSTANDARD = LVCMOS33; +NET "dig2_seg<3>" LOC = B15 | IOSTANDARD = LVCMOS33; +NET "dig2_seg<2>" LOC = A18 | IOSTANDARD = LVCMOS33; +NET "dig2_seg<1>" LOC = B18 | IOSTANDARD = LVCMOS33; +NET "dig2_seg<0>" LOC = B17 | IOSTANDARD = LVCMOS33; + +NET "dig3_seg<7>" LOC = D15 | IOSTANDARD = LVCMOS33; +NET "dig3_seg<6>" LOC = E13 | IOSTANDARD = LVCMOS33; +NET "dig3_seg<5>" LOC = B13 | IOSTANDARD = LVCMOS33; +NET "dig3_seg<4>" LOC = D13 | IOSTANDARD = LVCMOS33; +NET "dig3_seg<3>" LOC = D14 | IOSTANDARD = LVCMOS33; +NET "dig3_seg<2>" LOC = A14 | IOSTANDARD = LVCMOS33; +NET "dig3_seg<1>" LOC = E16 | IOSTANDARD = LVCMOS33; +NET "dig3_seg<0>" LOC = E15 | IOSTANDARD = LVCMOS33; + +NET "dig4_seg<7>" LOC = D11 | IOSTANDARD = LVCMOS33; +NET "dig4_seg<6>" LOC = E9 | IOSTANDARD = LVCMOS33; +NET "dig4_seg<5>" LOC = A10 | IOSTANDARD = LVCMOS33; +NET "dig4_seg<4>" LOC = B9 | IOSTANDARD = LVCMOS33; +NET "dig4_seg<3>" LOC = A9 | IOSTANDARD = LVCMOS33; +NET "dig4_seg<2>" LOC = C10 | IOSTANDARD = LVCMOS33; +NET "dig4_seg<1>" LOC = A12 | IOSTANDARD = LVCMOS33; +NET "dig4_seg<0>" LOC = B10 | IOSTANDARD = LVCMOS33; + +NET "dig5_seg<7>" LOC = C7 | IOSTANDARD = LVCMOS33; +NET "dig5_seg<6>" LOC = A4 | IOSTANDARD = LVCMOS33; +NET "dig5_seg<5>" LOC = B5 | IOSTANDARD = LVCMOS33; +NET "dig5_seg<4>" LOC = E6 | IOSTANDARD = LVCMOS33; +NET "dig5_seg<3>" LOC = C5 | IOSTANDARD = LVCMOS33; +NET "dig5_seg<2>" LOC = E7 | IOSTANDARD = LVCMOS33; +NET "dig5_seg<1>" LOC = B8 | IOSTANDARD = LVCMOS33; +NET "dig5_seg<0>" LOC = C6 | IOSTANDARD = LVCMOS33; + + +# Header A (left) +NET "header_a<2>" LOC = V7 | IOSTANDARD = LVCMOS33; +NET "header_a<3>" LOC = AA8 | IOSTANDARD = LVCMOS33; +NET "header_a<4>" LOC = AB8 | IOSTANDARD = LVCMOS33; +NET "header_a<5>" LOC = V8 | IOSTANDARD = LVCMOS33; +NET "header_a<6>" LOC = Y10 | IOSTANDARD = LVCMOS33; +NET "header_a<7>" LOC = V9 | IOSTANDARD = LVCMOS33; +NET "header_a<8>" LOC = W9 | IOSTANDARD = LVCMOS33; +NET "header_a<9>" LOC = AA10 | IOSTANDARD = LVCMOS33; +NET "header_a<10>" LOC = AB10 | IOSTANDARD = LVCMOS33; +NET "header_a<11>" LOC = W10 | IOSTANDARD = LVCMOS33; +NET "header_a<12>" LOC = AB11 | IOSTANDARD = LVCMOS33; +NET "header_a<13>" LOC = U11 | IOSTANDARD = LVCMOS33; +NET "header_a<14>" LOC = AB13 | IOSTANDARD = LVCMOS33; +NET "header_a<15>" LOC = AA13 | IOSTANDARD = LVCMOS33; +NET "header_a<16>" LOC = V10 | IOSTANDARD = LVCMOS33; +NET "header_a<17>" LOC = U10 | IOSTANDARD = LVCMOS33; +NET "header_a<18>" LOC = W13 | IOSTANDARD = LVCMOS33; +NET "header_a<19>" LOC = Y13 | IOSTANDARD = LVCMOS33; + +# Header B (right) +NET "header_b<2>" LOC = V14 | IOSTANDARD = LVCMOS33; +NET "header_b<3>" LOC = V13 | IOSTANDARD = LVCMOS33; +NET "header_b<4>" LOC = AA15 | IOSTANDARD = LVCMOS33; +NET "header_b<5>" LOC = W14 | IOSTANDARD = LVCMOS33; +NET "header_b<6>" LOC = AB15 | IOSTANDARD = LVCMOS33; +NET "header_b<7>" LOC = Y16 | IOSTANDARD = LVCMOS33; +NET "header_b<8>" LOC = AA17 | IOSTANDARD = LVCMOS33; +NET "header_b<9>" LOC = AA18 | IOSTANDARD = LVCMOS33; +NET "header_b<10>" LOC = AB18 | IOSTANDARD = LVCMOS33; +NET "header_b<11>" LOC = Y18 | IOSTANDARD = LVCMOS33; +NET "header_b<12>" LOC = Y19 | IOSTANDARD = LVCMOS33; +NET "header_b<13>" LOC = AB20 | IOSTANDARD = LVCMOS33; +NET "header_b<14>" LOC = AA20 | IOSTANDARD = LVCMOS33; +NET "header_b<15>" LOC = U16 | IOSTANDARD = LVCMOS33; +NET "header_b<16>" LOC = V16 | IOSTANDARD = LVCMOS33; +NET "header_b<17>" LOC = V17 | IOSTANDARD = LVCMOS33; +NET "header_b<18>" LOC = W16 | IOSTANDARD = LVCMOS33; +NET "header_b<19>" LOC = W17 | IOSTANDARD = LVCMOS33; + +# usused pins +CONFIG PROHIBIT = A3; +CONFIG PROHIBIT = A7; +CONFIG PROHIBIT = A11; +CONFIG PROHIBIT = A16; +CONFIG PROHIBIT = AA3; +CONFIG PROHIBIT = AA7; +CONFIG PROHIBIT = AA9; +CONFIG PROHIBIT = AA11; +CONFIG PROHIBIT = AA14; +CONFIG PROHIBIT = AA16; +CONFIG PROHIBIT = AA19; +CONFIG PROHIBIT = AB7; +CONFIG PROHIBIT = AB9; +CONFIG PROHIBIT = AB12; +CONFIG PROHIBIT = AB14; +CONFIG PROHIBIT = AB16; +CONFIG PROHIBIT = AB19; +CONFIG PROHIBIT = B4; +CONFIG PROHIBIT = B7; +CONFIG PROHIBIT = B12; +CONFIG PROHIBIT = B11; +CONFIG PROHIBIT = B16; +CONFIG PROHIBIT = C2; +CONFIG PROHIBIT = C3; +CONFIG PROHIBIT = C4; +CONFIG PROHIBIT = C12; +CONFIG PROHIBIT = C16; +CONFIG PROHIBIT = D2; +CONFIG PROHIBIT = D3; +CONFIG PROHIBIT = D4; +CONFIG PROHIBIT = D5; +CONFIG PROHIBIT = D8; +CONFIG PROHIBIT = D12; +CONFIG PROHIBIT = D16; +CONFIG PROHIBIT = E2; +CONFIG PROHIBIT = E3; +CONFIG PROHIBIT = E8; +CONFIG PROHIBIT = E4; +CONFIG PROHIBIT = E5; +CONFIG PROHIBIT = F4; +CONFIG PROHIBIT = E10; +CONFIG PROHIBIT = E12; +CONFIG PROHIBIT = F12; +CONFIG PROHIBIT = F5; +CONFIG PROHIBIT = F13; +CONFIG PROHIBIT = F6; +CONFIG PROHIBIT = F9; +CONFIG PROHIBIT = F10; +CONFIG PROHIBIT = F16; +CONFIG PROHIBIT = F11; +CONFIG PROHIBIT = F14; +CONFIG PROHIBIT = G3; +CONFIG PROHIBIT = G4; +CONFIG PROHIBIT = G5; +CONFIG PROHIBIT = G20; +CONFIG PROHIBIT = H1; +CONFIG PROHIBIT = H2; +CONFIG PROHIBIT = H4; +CONFIG PROHIBIT = H18; +CONFIG PROHIBIT = H19; +CONFIG PROHIBIT = H21; +CONFIG PROHIBIT = H22; +CONFIG PROHIBIT = J1; +CONFIG PROHIBIT = J2; +CONFIG PROHIBIT = J4; +CONFIG PROHIBIT = J5; +CONFIG PROHIBIT = J6; +CONFIG PROHIBIT = J17; +CONFIG PROHIBIT = J18; +CONFIG PROHIBIT = J19; +CONFIG PROHIBIT = J21; +CONFIG PROHIBIT = J22; +CONFIG PROHIBIT = K5; +CONFIG PROHIBIT = K6; +CONFIG PROHIBIT = K17; +CONFIG PROHIBIT = K18; +CONFIG PROHIBIT = N5; +CONFIG PROHIBIT = N6; +CONFIG PROHIBIT = N17; +CONFIG PROHIBIT = N18; +CONFIG PROHIBIT = N19; +CONFIG PROHIBIT = N20; +CONFIG PROHIBIT = P1; +CONFIG PROHIBIT = P2; +CONFIG PROHIBIT = P4; +CONFIG PROHIBIT = P5; +CONFIG PROHIBIT = P6; +CONFIG PROHIBIT = P17; +CONFIG PROHIBIT = P18; +CONFIG PROHIBIT = P19; +CONFIG PROHIBIT = P21; +CONFIG PROHIBIT = P22; +CONFIG PROHIBIT = R1; +CONFIG PROHIBIT = R2; +CONFIG PROHIBIT = R4; +CONFIG PROHIBIT = R5; +CONFIG PROHIBIT = R19; +CONFIG PROHIBIT = R21; +CONFIG PROHIBIT = R22; +CONFIG PROHIBIT = T3; +CONFIG PROHIBIT = T19; +CONFIG PROHIBIT = T20; +CONFIG PROHIBIT = U9; +CONFIG PROHIBIT = U12; +CONFIG PROHIBIT = U13; +CONFIG PROHIBIT = U14; +CONFIG PROHIBIT = U17; +CONFIG PROHIBIT = V11; +CONFIG PROHIBIT = V12; +CONFIG PROHIBIT = V15; +CONFIG PROHIBIT = W7; +CONFIG PROHIBIT = W8; +CONFIG PROHIBIT = W11; +CONFIG PROHIBIT = W12; +CONFIG PROHIBIT = W15; +CONFIG PROHIBIT = W18; +CONFIG PROHIBIT = Y4; +CONFIG PROHIBIT = Y7; +CONFIG PROHIBIT = Y11; +CONFIG PROHIBIT = Y12; diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.prj b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.prj new file mode 100644 index 0000000..24120d5 --- /dev/null +++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.prj @@ -0,0 +1,19 @@ +vhdl work ../top.vhd +vhdl zpu ../../../zpu_pkg.vhdl +vhdl zpu ../../../zpu_small.vhdl +vhdl zpu ../../../zpu_medium.vhdl +vhdl zpu ../../../roms/rom_pkg.vhdl +#vhdl zpu ../../../roms/hello_dbram.vhdl +#vhdl zpu ../../../roms/hello_bram.vhdl +vhdl zpu ../../../roms/dmips_dbram.vhdl +vhdl zpu ../../../roms/dmips_bram.vhdl +vhdl zpu ../../../helpers/zpu_small1.vhdl +vhdl zpu ../../../helpers/zpu_med1.vhdl +vhdl zpu ../../../devices/txt_util.vhdl +vhdl zpu ../../../devices/phi_io.vhdl +vhdl zpu ../../../devices/timer.vhdl +vhdl zpu ../../../devices/gpio.vhdl +vhdl zpu ../../../devices/rx_unit.vhdl +vhdl zpu ../../../devices/tx_unit.vhdl +vhdl zpu ../../../devices/br_gen.vhdl +vhdl zpu ../../../devices/trace.vhdl diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.ut b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.ut new file mode 100644 index 0000000..765a6f3 --- /dev/null +++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.ut @@ -0,0 +1,29 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g CRC:Enable +-g ConfigRate:6 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g HswapenPin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g DCMShutdown:Disable +-g DCIUpdateMode:AsRequired +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Match_cycle:Auto +-g Security:None +-g DonePipe:No +-g DriveDone:No diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.xst b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.xst new file mode 100644 index 0000000..14873ea --- /dev/null +++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.xst @@ -0,0 +1,56 @@ +set -tmpdir "tmp" +set -xsthdpdir "xst" +run +-ifn ../synthesis_config/top.prj +-ifmt mixed +-ofn top +-ofmt NGC +-p xc3s1000-4-fg456 +-top top +-opt_mode Speed +-opt_level 1 +-iuc NO +-keep_hierarchy No +-netlist_hierarchy As_Optimized +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case Maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style LUT +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract Yes +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract Yes +-resource_sharing YES +-async_to_sync NO +-mult_style Auto +-iobuf YES +-max_fanout 500 +-bufg 8 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob Auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top.vhd b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top.vhd new file mode 100644 index 0000000..fbca62b --- /dev/null +++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top.vhd @@ -0,0 +1,372 @@ +-- top module of +-- Altium LiveDesign Board +-- +-- using following external connections: +-- test button as reset +-- LEDs and 7 segment for output +-- RS232 +-- + + +library ieee; +use ieee.std_logic_1164.all; + +library zpu; +use zpu.zpupkg.all; -- zpu_dbgo_t + +library unisim; +use unisim.vcomponents.dcm; + + +entity top is + port ( + -- pragma translate_off + stop_simulation : out std_logic; + -- pragma translate_on + clk_50 : in std_logic; + reset_n : in std_logic; + -- + -- soft JTAG + soft_tdo : out std_logic; + soft_tms : in std_logic; + soft_tdi : in std_logic; + soft_tck : in std_logic; + -- + -- SRAM 0 (256k x 16) pin connections + sram0_a : out std_logic_vector(18 downto 0); + sram0_d : inout std_logic_vector(15 downto 0); + sram0_lb_n : out std_logic; + sram0_ub_n : out std_logic; + sram0_cs_n : out std_logic; -- chip select + sram0_we_n : out std_logic; -- write-enable + sram0_oe_n : out std_logic; -- output enable + -- + -- SRAM 1 (256k x 16) pin connections + sram1_a : out std_logic_vector(18 downto 0); + sram1_d : inout std_logic_vector(15 downto 0); + sram1_lb_n : out std_logic; + sram1_ub_n : out std_logic; + sram1_cs_n : out std_logic; -- chip select + sram1_we_n : out std_logic; -- write-enable + sram1_oe_n : out std_logic; -- output enable + -- + -- RS232 + rs232_rx : in std_logic; + rs232_tx : out std_logic; + rs232_cts : in std_logic; + rs232_rts : out std_logic; + -- + -- PS2 connectors + mouse_clk : inout std_logic; + mouse_data : inout std_logic; + kbd_clk : inout std_logic; + kbd_data : inout std_logic; + -- + -- vga output + vga_red : out std_logic_vector(7 downto 5); + vga_green : out std_logic_vector(7 downto 5); + vga_blue : out std_logic_vector(7 downto 5); + vga_hsync : out std_logic; + vga_vsync : out std_logic; + -- + -- Audio out + audio_r : out std_logic; + audio_l : out std_logic; + -- + -- GPIOs + switch_n : in std_logic_vector(7 downto 0); + button_n : in std_logic_vector(5 downto 0); + led : out std_logic_vector(7 downto 0); + -- + -- seven segment display + dig0_seg : out std_logic_vector(7 downto 0); + dig1_seg : out std_logic_vector(7 downto 0); + dig2_seg : out std_logic_vector(7 downto 0); + dig3_seg : out std_logic_vector(7 downto 0); + dig4_seg : out std_logic_vector(7 downto 0); + dig5_seg : out std_logic_vector(7 downto 0); + -- + -- User Header + header_a : inout std_logic_vector(19 downto 2); + header_b : inout std_logic_vector(19 downto 2) + ); +end entity top; + + +architecture rtl of top is + + + --------------------------- + -- type declarations + type zpu_type is (zpu_small, zpu_medium); + + --------------------------- + -- constant declarations + constant zpu_flavour : zpu_type := zpu_small; -- choose your flavour HERE + -- modify frequency here + constant clk_multiply : positive := 3; -- 9 for small, 3 for medium + constant clk_divide : positive := 2; -- 5 for small, 2 for medium + -- + constant word_size_c : natural := 32; -- 32 bits data path + constant addr_w_c : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O + + constant clk_frequency : positive := 50; -- input frequency for correct calculation + + + --------------------------- + -- component declarations + component zpu_small1 is + generic ( + word_size : natural := 32; -- 32 bits data path + d_care_val : std_logic := '0'; -- Fill value + clk_freq : positive := 50; -- 50 MHz clock + brate : positive := 115200; -- RS232 baudrate + addr_w : natural := 16; -- 16 bits address space=64 kB, 32 kB I/O + bram_w : natural := 15 -- 15 bits RAM space=32 kB + ); + port ( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + break_o : out std_logic; -- Break executed + dbg_o : out zpu_dbgo_t; -- Debug info + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic; -- UART Rx + gpio_in : in std_logic_vector(31 downto 0); + gpio_out : out std_logic_vector(31 downto 0); + gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out + ); + end component zpu_small1; + + component zpu_med1 is + generic( + word_size : natural := 32; -- 32 bits data path + d_care_val : std_logic := '0'; -- Fill value + clk_freq : positive := 50; -- 50 MHz clock + brate : positive := 115200; -- RS232 baudrate + addr_w : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O + bram_w : natural := 15 -- 15 bits RAM space=32 kB + ); + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + break_o : out std_logic; -- Break executed + dbg_o : out zpu_dbgo_t; -- Debug info + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic; -- UART Rx + gpio_in : in std_logic_vector(31 downto 0); + gpio_out : out std_logic_vector(31 downto 0); + gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out + ); + end component zpu_med1; + + + --------------------------- + -- signal declarations + signal dcm_i0_clk0 : std_ulogic; + signal dcm_i0_clkfx : std_ulogic; + signal clk_fb : std_ulogic; + signal clk : std_ulogic; + -- + signal reset_shift_reg : std_ulogic_vector(3 downto 0); + signal reset_sync : std_ulogic; + -- + signal zpu_i0_dbg : zpu_dbgo_t; -- Debug info + signal zpu_i0_break : std_logic; + -- + signal gpio_in : std_logic_vector(31 downto 0) := (others => '0'); + signal zpu_i0_gpio_out : std_logic_vector(31 downto 0); + signal zpu_i0_gpio_dir : std_logic_vector(31 downto 0); + + +begin + + -- default output drivers + -- to pass bitgen DRC + -- outputs used by design are commented + soft_tdo <= '1'; + -- + sram0_a <= (others => '1'); + sram0_d <= (others => 'Z'); + sram0_lb_n <= '1'; + sram0_ub_n <= '1'; + sram0_cs_n <= '1'; + sram0_we_n <= '1'; + sram0_oe_n <= '1'; + -- + sram1_a <= (others => '1'); + sram1_d <= (others => 'Z'); + sram1_lb_n <= '1'; + sram1_ub_n <= '1'; + sram1_cs_n <= '1'; + sram1_we_n <= '1'; + sram1_oe_n <= '1'; + -- + --rs232_tx <= '1'; + rs232_rts <= '1'; + -- + mouse_clk <= 'Z'; + mouse_data <= 'Z'; + kbd_clk <= 'Z'; + kbd_data <= 'Z'; + -- + vga_red <= (others => '1'); + vga_green <= (others => '1'); + vga_blue <= (others => '1'); + vga_hsync <= '1'; + vga_vsync <= '1'; + -- + audio_r <= '0'; + audio_l <= '0'; + -- + --led <= (others => '0'); + -- + --dig0_seg <= (others => '0'); + --dig1_seg <= (others => '0'); + dig2_seg <= (others => '0'); + dig3_seg <= (others => '0'); + dig4_seg <= (others => '0'); + dig5_seg <= (others => '0'); + -- + header_a <= (others => 'Z'); + header_b <= (others => 'Z'); + + + -- digital clock manager (DCM) + -- to generate higher/other system clock frequencys + dcm_i0 : dcm + generic map ( + startup_wait => true, -- wait with DONE till locked + clkfx_multiply => clk_multiply, + clkfx_divide => clk_divide, + clk_feedback => "1X" + ) + port map ( + clkin => clk_50, + clk0 => dcm_i0_clk0, + clkfx => dcm_i0_clkfx, + clkfb => clk_fb + ); + + clk_fb <= dcm_i0_clk0; + clk <= dcm_i0_clkfx; + + + -- reset synchronizer + -- generate synchronous reset + reset_synchronizer : process(clk, reset_n) + begin + if reset_n = '0' then + reset_shift_reg <= (others => '1'); + elsif rising_edge(clk) then + reset_shift_reg <= reset_shift_reg(reset_shift_reg'high-1 downto 0) & '0'; + end if; + end process; + reset_sync <= reset_shift_reg(reset_shift_reg'high); + + + -- select instance of zpu + zpu_i0_small : if zpu_flavour = zpu_small generate + zpu_i0 : zpu_small1 + generic map ( + addr_w => addr_w_c, + word_size => word_size_c, + clk_freq => clk_frequency * clk_multiply / clk_divide + ) + port map ( + clk_i => clk, -- : in std_logic; -- CPU clock + rst_i => reset_sync, -- : in std_logic; -- Reset + break_o => zpu_i0_break, -- : out std_logic; -- Break executed + dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; -- Debug info + rs232_tx_o => rs232_tx, -- : out std_logic; -- UART Tx + rs232_rx_i => rs232_rx, -- : in std_logic -- UART Rx + gpio_in => gpio_in, -- : in std_logic_vector(31 downto 0); + gpio_out => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0); + gpio_dir => zpu_i0_gpio_dir -- : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out + ); + end generate zpu_i0_small; + + zpu_i0_medium : if zpu_flavour = zpu_medium generate + zpu_i0 : zpu_med1 + generic map ( + addr_w => addr_w_c, + word_size => word_size_c, + clk_freq => clk_frequency * clk_multiply / clk_divide + ) + port map ( + clk_i => clk, -- : in std_logic; -- CPU clock + rst_i => reset_sync, -- : in std_logic; -- Reset + break_o => zpu_i0_break, -- : out std_logic; -- Break executed + dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; -- Debug info + rs232_tx_o => rs232_tx, -- : out std_logic; -- UART Tx + rs232_rx_i => rs232_rx, -- : in std_logic -- UART Rx + gpio_in => gpio_in, -- : in std_logic_vector(31 downto 0); + gpio_out => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0); + gpio_dir => zpu_i0_gpio_dir -- : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out + ); + end generate zpu_i0_medium; + + + -- pragma translate_off + stop_simulation <= zpu_i0_break; + + + trace_mod : trace + generic map ( + addr_w => addr_w_c, + word_size => word_size_c, + log_file => "zpu_trace.log" + ) + port map ( + clk_i => clk, + dbg_i => zpu_i0_dbg, + stop_i => zpu_i0_break, + busy_i => '0' + ); + -- pragma translate_on + + + -- assign GPIOs + -- + -- bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 + -- + -- in header_a(19.........12) -- -- -- -- -- -- -- -- + -- out header_a(19.........12) dig1_seg(7...........0) + -- + -- + -- bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + -- + -- in switch_n(7...........0) -- -- button_n(5....0) + -- out dig0_seg(7...........0) led(7................0) + -- + + gpio_in(31 downto 24) <= header_a(19 downto 12); + gpio_in(15 downto 8) <= switch_n; + gpio_in( 5 downto 0) <= button_n; + + -- 3-state buffers for some headers + header_a(19) <= zpu_i0_gpio_out(31) when zpu_i0_gpio_dir(31) = '0' else 'Z'; + header_a(18) <= zpu_i0_gpio_out(30) when zpu_i0_gpio_dir(30) = '0' else 'Z'; + header_a(17) <= zpu_i0_gpio_out(29) when zpu_i0_gpio_dir(29) = '0' else 'Z'; + header_a(16) <= zpu_i0_gpio_out(28) when zpu_i0_gpio_dir(28) = '0' else 'Z'; + header_a(15) <= zpu_i0_gpio_out(27) when zpu_i0_gpio_dir(27) = '0' else 'Z'; + header_a(14) <= zpu_i0_gpio_out(26) when zpu_i0_gpio_dir(26) = '0' else 'Z'; + header_a(13) <= zpu_i0_gpio_out(25) when zpu_i0_gpio_dir(25) = '0' else 'Z'; + header_a(12) <= zpu_i0_gpio_out(24) when zpu_i0_gpio_dir(24) = '0' else 'Z'; + + -- outputs + dig1_seg <= zpu_i0_gpio_out(23 downto 16); + dig0_seg <= zpu_i0_gpio_out(15 downto 8); + + -- switch on all LEDs in case of break + process + begin + wait until rising_edge(clk); + led <= zpu_i0_gpio_out(7 downto 0); + if zpu_i0_break = '1' then + led <= (others => '1'); + end if; + end process; + + +end architecture rtl; + diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top_tb.vhd b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top_tb.vhd new file mode 100644 index 0000000..e42fc20 --- /dev/null +++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top_tb.vhd @@ -0,0 +1,194 @@ +-- testbench for +-- Altium LiveDesign Board +-- +-- includes "model" for clock generation +-- simulate press on test/reset as reset +-- +-- place models for external components (SRAM, PS2) in this file +-- + + +library ieee; +use ieee.std_logic_1164.all; + + +entity top_tb is +end entity top_tb; + +architecture testbench of top_tb is + + --------------------------- + -- constant declarations + constant clk_period : time := 1 sec / 50_000_000; -- 50 MHz + + + --------------------------- + -- signal declarations + signal simulation_run : boolean := true; + signal tb_stop_simulation : std_logic; + -- + signal tb_clk : std_logic := '0'; + signal tb_reset_n : std_logic; + -- + -- soft JTAG + signal tb_soft_tdo : std_logic; + signal tb_soft_tms : std_logic := '1'; + signal tb_soft_tdi : std_logic := '1'; + signal tb_soft_tck : std_logic := '1'; + -- + -- SRAM 0 (256k x 16) pin connections + signal tb_sram0_a : std_logic_vector(18 downto 0); + signal tb_sram0_d : std_logic_vector(15 downto 0) := (others => 'Z'); + signal tb_sram0_lb_n : std_logic; + signal tb_sram0_ub_n : std_logic; + signal tb_sram0_cs_n : std_logic; -- chip select + signal tb_sram0_we_n : std_logic; -- write-enable + signal tb_sram0_oe_n : std_logic; -- output enable + -- + -- SRAM 1 (256k x 16) pin connections + signal tb_sram1_a : std_logic_vector(18 downto 0); + signal tb_sram1_d : std_logic_vector(15 downto 0) := (others => 'Z'); + signal tb_sram1_lb_n : std_logic; + signal tb_sram1_ub_n : std_logic; + signal tb_sram1_cs_n : std_logic; -- chip select + signal tb_sram1_we_n : std_logic; -- write-enable + signal tb_sram1_oe_n : std_logic; -- output enable + -- + -- RS232 + signal tb_rs232_rx : std_logic := '1'; + signal tb_rs232_tx : std_logic; + signal tb_rs232_cts : std_logic := '1'; + signal tb_rs232_rts : std_logic; + -- + -- PS2 connectors + signal tb_mouse_clk : std_logic := 'Z'; + signal tb_mouse_data : std_logic := 'Z'; + signal tb_kbd_clk : std_logic := 'Z'; + signal tb_kbd_data : std_logic := 'Z'; + -- + -- vga output + signal tb_vga_red : std_logic_vector(7 downto 5); + signal tb_vga_green : std_logic_vector(7 downto 5); + signal tb_vga_blue : std_logic_vector(7 downto 5); + signal tb_vga_hsync : std_logic; + signal tb_vga_vsync : std_logic; + -- + -- Audio out + signal tb_audio_r : std_logic; + signal tb_audio_l : std_logic; + -- + -- GPIOs + signal tb_switch_n : std_logic_vector(7 downto 0) := (others => '1'); + signal tb_button_n : std_logic_vector(5 downto 0) := (others => '1'); + signal tb_led : std_logic_vector(7 downto 0); + -- + -- seven segment display + signal tb_dig0_seg : std_logic_vector(7 downto 0); + signal tb_dig1_seg : std_logic_vector(7 downto 0); + signal tb_dig2_seg : std_logic_vector(7 downto 0); + signal tb_dig3_seg : std_logic_vector(7 downto 0); + signal tb_dig4_seg : std_logic_vector(7 downto 0); + signal tb_dig5_seg : std_logic_vector(7 downto 0); + -- + -- User Header A + signal tb_header_a : std_logic_vector(19 downto 2) := (others => 'Z'); + signal tb_header_b : std_logic_vector(19 downto 2) := (others => 'Z'); + +begin + + -- generate clock + tb_clk <= not tb_clk after clk_period / 2 when simulation_run; + + -- generate reset + tb_reset_n <= '0', '1' after 6.66 * clk_period; + + + -- simulate keypress + tb_button_n(2) <= '1', '0' after 50 us, '1' after 52 us; + + -- dut + top_i0 : entity work.top + port map ( + stop_simulation => tb_stop_simulation, -- : out std_logic; + -- + clk_50 => tb_clk, -- : in std_logic; + reset_n => tb_reset_n, -- : in std_logic; + -- + -- soft JTAG + soft_tdo => tb_soft_tdo, -- : out std_logic; + soft_tms => tb_soft_tms, -- : in std_logic; + soft_tdi => tb_soft_tdi, -- : in std_logic; + soft_tck => tb_soft_tck, -- : in std_logic; + -- + -- SRAM 0 (256k x 16) pin connections + sram0_a => tb_sram0_a, -- : out std_logic_vector(18 downto 0); + sram0_d => tb_sram0_d, -- : inout std_logic_vector(15 downto 0); + sram0_lb_n => tb_sram0_lb_n, -- : out std_logic; + sram0_ub_n => tb_sram0_ub_n, -- : out std_logic; + sram0_cs_n => tb_sram0_cs_n, -- : out std_logic; -- chip select + sram0_we_n => tb_sram0_we_n, -- : out std_logic; -- write-enable + sram0_oe_n => tb_sram0_oe_n, -- : out std_logic; -- output enable + -- + -- SRAM 1 (256k x 16) pin connections + sram1_a => tb_sram1_a, -- : out std_logic_vector(18 downto 0); + sram1_d => tb_sram1_d, -- : inout std_logic_vector(15 downto 0); + sram1_lb_n => tb_sram1_lb_n, -- : out std_logic; + sram1_ub_n => tb_sram1_ub_n, -- : out std_logic; + sram1_cs_n => tb_sram1_cs_n, -- : out std_logic; -- chip select + sram1_we_n => tb_sram1_we_n, -- : out std_logic; -- write-enable + sram1_oe_n => tb_sram1_oe_n, -- : out std_logic; -- output enable + -- + -- RS232 + rs232_rx => tb_rs232_rx, -- : in std_logic; + rs232_tx => tb_rs232_tx, -- : out std_logic; + rs232_cts => tb_rs232_cts, -- : in std_logic; + rs232_rts => tb_rs232_rts, -- : out std_logic; + -- + -- PS2 connectors + mouse_clk => tb_mouse_clk, -- : inout std_logic; + mouse_data => tb_mouse_data, -- : inout std_logic; + kbd_clk => tb_kbd_clk, -- : inout std_logic; + kbd_data => tb_kbd_data, -- : inout std_logic; + -- + -- vga output + vga_red => tb_vga_red, -- : out std_logic_vector(7 downto 5); + vga_green => tb_vga_green, -- : out std_logic_vector(7 downto 5); + vga_blue => tb_vga_blue, -- : out std_logic_vector(7 downto 5); + vga_hsync => tb_vga_hsync, -- : out std_logic; + vga_vsync => tb_vga_vsync, -- : out std_logic; + -- + -- Audio out + audio_r => tb_audio_r, -- : out std_logic; + audio_l => tb_audio_l, -- : out std_logic; + -- + -- GPIOs + switch_n => tb_switch_n, -- : in std_logic_vector(7 downto 0); + button_n => tb_button_n, -- : in std_logic_vector(5 downto 0); + led => tb_led, -- : out std_logic_vector(7 downto 0); + -- + -- seven segment display + dig0_seg => tb_dig0_seg, -- : out std_logic_vector(7 downto 0); + dig1_seg => tb_dig1_seg, -- : out std_logic_vector(7 downto 0); + dig2_seg => tb_dig2_seg, -- : out std_logic_vector(7 downto 0); + dig3_seg => tb_dig3_seg, -- : out std_logic_vector(7 downto 0); + dig4_seg => tb_dig4_seg, -- : out std_logic_vector(7 downto 0); + dig5_seg => tb_dig5_seg, -- : out std_logic_vector(7 downto 0); + -- + -- User Header + header_a => tb_header_a, -- : inout std_logic_vector(19 downto 2); + header_b => tb_header_b -- : inout std_logic_vector(19 downto 2) + ); + + + -- check for simulation stopping + process (tb_stop_simulation) + begin + if tb_stop_simulation = '1' then + report "Simulation end." severity note; + simulation_run <= false; + end if; + end process; + + +end architecture testbench; + -- cgit v1.1