From 5c6feff72d5324c88e0e8d8980a7d7cfab7e1509 Mon Sep 17 00:00:00 2001 From: Oyvind Harboe Date: Tue, 27 Jan 2009 08:33:56 +0100 Subject: First cut of ZPU floating point support design --- zpu/docs/zpu_arch.html | 51 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index 5a55378..6266a03 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -66,6 +66,7 @@ Several of the links will only work if you have checked out the zpu/zpu tree fro
  • TODO list
  • Repository Re-org
  • Next generation ZPU +
  • Floating point support @@ -2319,5 +2320,55 @@ function calls to libgcc and thus make it easier to determine that microcode is not needed. + +

    Floating point support

    +The ZPU does not currently have floating point support. Feedback +from users indicates that single precision floating point support for +addition, multiplication and float-to-integer convesion would +be useful for small ZPU programs that sit in a tight control +loop. Essentially the ZPU is then measuring something, doing a +few calculations and then modifying the control signal. +

    +Such control loops can be written in fixed point math, but that +adds to the engineering effort and reduces clarity of the software +implementation and the performance will probably be worse than +for a hardware floating point version. +

    Pipelined floating point module

    +Design needs to be nailed down. +Goals: +
      +
    • 32 bit single precision floating point +
    • FADD => add two floats +
    • FMULT => multiply two floats +
    • FINT => convert float to int +
    +The problem is divided into two: + +
      +
    1. One top level VHDL module for each of the operations above. +
    2. Integration into ZPU's are a separate problem that will not be +addressed in this project. +
    3. add a memory mapped coprocessor interface to the above. This +yields an example of a coprocessor which can be used for any +custom calculations and allows interest to be gauged. +
    + +Throughput: + +
      +
    1. pipelined design where throughput is one operation per cycle +with a fixed number of cycles delay. +
    2. there is no flow control or enable signal. +
    + + + +GCC support is not hard, but modifying GCC should considered after +interest in this feature beyond a coprocessor has been gauged. + +

    VHDL module interface

    + +Patches anyone??? + -- cgit v1.1