From 536db927b7577ee895677b1fa1d3cd3ae4c85940 Mon Sep 17 00:00:00 2001 From: oharboe Date: Sun, 21 Sep 2008 08:17:35 +0000 Subject: * zpu/hdl/zealot: added small ZPU core, testbenches and FPGA implementation --- zpu/ChangeLog | 2 + zpu/docs/zpu_arch.html | 12 +- zpu/hdl/zealot/0README.txt | 61 +- zpu/hdl/zealot/fpga/dmips_small1.vhdl | 116 + zpu/hdl/zealot/fpga/hello_small1.vhdl | 116 + zpu/hdl/zealot/roms/dmips_dbram.vhdl | 4485 +++++++++++++++++++++++++++++ zpu/hdl/zealot/roms/hello_dbram.vhdl | 3035 +++++++++++++++++++ zpu/hdl/zealot/testbenches/small1_tb.vhdl | 129 + zpu/hdl/zealot/zpu_pkg.vhdl | 539 ++-- zpu/hdl/zealot/zpu_small.vhdl | 471 +++ 10 files changed, 8682 insertions(+), 284 deletions(-) create mode 100644 zpu/hdl/zealot/fpga/dmips_small1.vhdl create mode 100644 zpu/hdl/zealot/fpga/hello_small1.vhdl create mode 100644 zpu/hdl/zealot/roms/dmips_dbram.vhdl create mode 100644 zpu/hdl/zealot/roms/hello_dbram.vhdl create mode 100644 zpu/hdl/zealot/testbenches/small1_tb.vhdl create mode 100644 zpu/hdl/zealot/zpu_small.vhdl diff --git a/zpu/ChangeLog b/zpu/ChangeLog index b447cfc..e190a9f 100644 --- a/zpu/ChangeLog +++ b/zpu/ChangeLog @@ -1,3 +1,5 @@ +2008-09-16 Salvador Eduardo Tropea + * zpu/hdl/zealot: added small ZPU core, testbenches and FPGA implementation 2008-09-11 Salvador Eduardo Tropea * zpu/docs/zpu_arch.html: added Zealot information. 2008-09-08 Salvador Eduardo Tropea diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index 882486f..6339031 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -1634,11 +1634,12 @@ to run the DMIPS benchmark and a hello world application. I tested the UART
  • The ZPU can be customized using generics. It allows the use of more than one core in the same project without problems.
  • Implements the lshiftright instruction in hardware, this gives around -10% boost in the DMIPS benchmark.
    • +10% boost in the DMIPS benchmark (Medium version).
  • You can disable various instructions groups and let them to the emulation soft, so you can experiment with various LUTs vs DMIPS -configurations.
    • -
  • Provides aprox. 2.6 DMIPS @ 50 MHz.
    • +configurations (Medium version). +
  • The medium version provides aprox. 2.6 DMIPS @ 50 MHz and the small +0.5 DMIPS @ 50 MHz.
  • Enhanced trace module, it includes the assembler for the executed instruction and can also meassure how much stack was consumed during the execution.
    • @@ -1648,8 +1649,9 @@ DMIPS benchmark. Simulation and implementation files are provided. You need 16 kB of BRAMs -for the "hello world" example and 32 kB for the DMIPS benchmark. The design -takes around 1030 slices and 3 multipliers.

    +for the "hello world" example and 32 kB for the DMIPS benchmark. The medium +version takes around 1030 slices and 3 multipliers and the small version +around 430 slices.

    The generics for the Zealot Medium ZPU are:

    diff --git a/zpu/hdl/zealot/0README.txt b/zpu/hdl/zealot/0README.txt index 364806c..4bb4546 100644 --- a/zpu/hdl/zealot/0README.txt +++ b/zpu/hdl/zealot/0README.txt @@ -19,6 +19,9 @@ What are the files? zpu_medium.vhdl ZPU CPU, medium version. +zpu_small.vhdl +ZPU CPU, small version (Dual Port RAM only!). + zpu_pkg.vhdl Package containing the declarations for the ZPU library. @@ -57,21 +60,40 @@ Version 2.1 (Language: C). This memory can be connected to the ZPU for simulation or hardware implementations. The code assumes a 50 MHz clock to compute the benchmark. The minimum size for this block should be 32 kB. +roms/dmips_dbram.vhdl +Same as roms/dmips_bram.vhdl, but dual ported. Suitable for the small ZPU. + roms/hello_bram.vhdl A memory that maps to Xilinx BRAMs and contains a simple "Hello World!" program (C compiled). This memory can be connected to the ZPU for simulation or hardware implementations. The minimum size for this block should be 16 kB. +roms/hello_dbram.vhdl +Same as roms/hello_bram.vhdl, but dual ported. Suitable for the small ZPU. helpers/zpu_med1.vhdl This is a helper that connects a ZPU to its memory and the PHI I/O space. testbenches/dmips_med1_tb.vhdl -A simple testbench to simulate the ZPU (behavior). +A simple testbench to simulate the medium ZPU (behavior). + +testbenches/small1_tb.vhdl +A simple testbench to simulate the small ZPU (behavior). fpga/dmips_med1.vhdl -A wrapper to implement the ZPU in an FPGA. This example was designed for a -GR-XC3S board from Pender, but should be easily adapted to other boards. +A wrapper to implement the medium ZPU in an FPGA. This example was designed +for a GR-XC3S board from Pender, but should be easily adapted to other +boards. + +fpga/hello_med1.vhdl +Same as fpga/dmips_med1.vhdl, but uses less memory, enough for the "Hello +Wold!" test. + +fpga/dmips_small1.vhdl +Same as fpga/dmips_med1.vhdl, but for the small ZPU. + +fpga/hello_small1.vhdl +Same as fpga/hello_med1.vhdl, but for the small ZPU. ZPU library? @@ -79,12 +101,12 @@ ZPU library? The following files are part of a library I called ZPU: -zpu_pkg.vhdl, zpu_medium.vhdl, txt_util.vhdl, timer.vhdl, rx_unit.vhdl, -tx_unit.vhdl, br_gen.vhdl, phi_io.vhdl and trace.vhdl. +zpu_pkg.vhdl, zpu_medium.vhdl, zpu_small.vhdl, txt_util.vhdl, timer.vhdl, +rx_unit.vhdl, tx_unit.vhdl, br_gen.vhdl, phi_io.vhdl and trace.vhdl. -You should group them inside a library called zpu. This procedure is tool-chain -dependent. In the ISE tool you must add a library and them move these files to -the library. +You should group them inside a library called zpu. This procedure is +tool-chain dependent. In the ISE tool you must add a library and them move +these files to the library. If you don't know how to do it with your tools you can just replace all the: @@ -105,6 +127,9 @@ You need all the files that compose the zpu library plus: roms/rom_pkg.vhdl and roms/dmips_bram.vhdl 2) A testbench (including the memory and I/O interconnections): aux/zpu_med1.vhdl and testbenches/dmips_med1_tb.vhdl +3) Be careful to include only the medium or the small ZPU. Also note that +the small uses dual port BRAMs, i.e. roms/dmips_dbram.vhdl The testbench +for the small ZPU is small1_tb.vhdl Which files are needed for synthesis? @@ -121,6 +146,8 @@ What resources are needed in the FPGA? The DMIPS benchmarks needs aprox (Xilinx Spartan 3): +Medium ZPU: + Flip Flops: 498 LUTs: 1877 Slices: 1032 @@ -130,11 +157,27 @@ Multipliers: 3 The hello world example needs less memory: Flip Flops: 496 -LUTs: 1872 +LUTs: 1871 Slices: 1027 BRAMs: 8 Multipliers: 3 + +Small ZPU: + +Flip Flops: 373 +LUTs: 706 +Slices: 434 +BRAMs: 16 + +The hello world example needs less memory: + +Flip Flops: 371 +LUTs: 701 +Slices: 431 +BRAMs: 8 + + The board should contain an RS-232 transceiver. A push button (active when pressed) is also used, for reset. diff --git a/zpu/hdl/zealot/fpga/dmips_small1.vhdl b/zpu/hdl/zealot/fpga/dmips_small1.vhdl new file mode 100644 index 0000000..018ab2d --- /dev/null +++ b/zpu/hdl/zealot/fpga/dmips_small1.vhdl @@ -0,0 +1,116 @@ +------------------------------------------------------------------------------ +---- ---- +---- ZPU Small connection to the FPGA pins ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- This module connects the ZPU_Small1 (zpu_small1.vhdl) core to a ---- +---- Spartan 3 1500 Xilinx FPGA available in the GR-XC3S board from ---- +---- Pender. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Salvador E. Tropea ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the GPL license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: DMIPS_Small1(FPGA) (Entity and architecture) ---- +---- File name: dmips_small1.vhdl ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: work ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- zpu.zpu_pkg ---- +---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: N/A ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library zpu; +use zpu.zpupkg.all; + +entity DMIPS_Small1 is + generic( + WORD_SIZE : natural:=32; -- 32 bits data path + D_CARE_VAL : std_logic:='0'; -- Fill value, I got better results with it + CLK_FREQ : positive:=50; -- 50 MHz clock + BRATE : positive:=115200; -- RS-232 baudrate + ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O + BRAM_W : natural:=15); -- 15 bits RAM space=32 kB + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic); -- UART Rx + + constant BRD_PB1_I : string:="D19"; -- SWITCH8==S2 + constant BRD_CLK1_I : string:="AA12"; -- 50 MHz clock + --constant BRD_CLK1_I : string:="AB12"; -- 40 MHz clock + -- UART: direct 1:1 cable + constant BRD_TX_O : string:="L4"; -- UART 1 (J1) TXD1 DB9 pin 2 + constant BRD_RX_I : string:="L3"; -- UART 1 (J1) RXD1 DB9 pin 3 + + ------------ + -- Pinout -- + ------------ + attribute LOC : string; + attribute IOSTANDARD : string; + constant IOSTD : string:="LVTTL"; + + attribute LOC of rst_i : signal is BRD_PB1_I; + attribute IOSTANDARD of rst_i : signal is IOSTD; + attribute LOC of clk_i : signal is BRD_CLK1_I; + attribute LOC of rs232_tx_o : signal is BRD_TX_O; + attribute IOSTANDARD of rs232_tx_o : signal is IOSTD; + attribute LOC of rs232_rx_i : signal is BRD_RX_I; + attribute IOSTANDARD of rs232_rx_i : signal is IOSTD; +end entity DMIPS_Small1; + +architecture FPGA of DMIPS_Small1 is + component ZPU_Small1 is + generic( + WORD_SIZE : natural:=32; -- 32 bits data path + D_CARE_VAL : std_logic:='0'; -- Fill value + CLK_FREQ : positive:=50; -- 50 MHz clock + BRATE : positive:=115200; -- RS232 baudrate + ADDR_W : natural:=16; -- 16 bits address space=64 kB, 32 kB I/O + BRAM_W : natural:=15); -- 15 bits RAM space=32 kB + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + break_o : out std_logic; -- Break executed + dbg_o : out zpu_dbgo_t; -- Debug info + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic); -- UART Rx + end component ZPU_Small1; +begin + zpu : ZPU_Small1 + generic map( + WORD_SIZE => WORD_SIZE, D_CARE_VAL => D_CARE_VAL, + CLK_FREQ => CLK_FREQ, BRATE => BRATE, ADDR_W => ADDR_W, + BRAM_W => BRAM_W) + port map( + clk_i => clk_i, rst_i => rst_i, rs232_tx_o => rs232_tx_o, + rs232_rx_i => rs232_rx_i, dbg_o => open); +end architecture FPGA; -- Entity: DMIPS_Small1 + diff --git a/zpu/hdl/zealot/fpga/hello_small1.vhdl b/zpu/hdl/zealot/fpga/hello_small1.vhdl new file mode 100644 index 0000000..ccd87c5 --- /dev/null +++ b/zpu/hdl/zealot/fpga/hello_small1.vhdl @@ -0,0 +1,116 @@ +------------------------------------------------------------------------------ +---- ---- +---- ZPU Small connection to the FPGA pins ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- This module connects the ZPU_Small1 (zpu_small1.vhdl) core to a ---- +---- Spartan 3 1500 Xilinx FPGA available in the GR-XC3S board from ---- +---- Pender. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Salvador E. Tropea ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the GPL license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: Hello_Small1(FPGA) (Entity and architecture) ---- +---- File name: hello_small1.vhdl ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: work ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- zpu.zpu_pkg ---- +---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: N/A ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library zpu; +use zpu.zpupkg.all; + +entity Hello_Small1 is + generic( + WORD_SIZE : natural:=32; -- 32 bits data path + D_CARE_VAL : std_logic:='0'; -- Fill value, I got better results with it + CLK_FREQ : positive:=50; -- 50 MHz clock + BRATE : positive:=115200; -- RS-232 baudrate + ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O + BRAM_W : natural:=14); -- 14 bits RAM space=16 kB + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic); -- UART Rx + + constant BRD_PB1_I : string:="D19"; -- SWITCH8==S2 + constant BRD_CLK1_I : string:="AA12"; -- 50 MHz clock + --constant BRD_CLK1_I : string:="AB12"; -- 40 MHz clock + -- UART: direct 1:1 cable + constant BRD_TX_O : string:="L4"; -- UART 1 (J1) TXD1 DB9 pin 2 + constant BRD_RX_I : string:="L3"; -- UART 1 (J1) RXD1 DB9 pin 3 + + ------------ + -- Pinout -- + ------------ + attribute LOC : string; + attribute IOSTANDARD : string; + constant IOSTD : string:="LVTTL"; + + attribute LOC of rst_i : signal is BRD_PB1_I; + attribute IOSTANDARD of rst_i : signal is IOSTD; + attribute LOC of clk_i : signal is BRD_CLK1_I; + attribute LOC of rs232_tx_o : signal is BRD_TX_O; + attribute IOSTANDARD of rs232_tx_o : signal is IOSTD; + attribute LOC of rs232_rx_i : signal is BRD_RX_I; + attribute IOSTANDARD of rs232_rx_i : signal is IOSTD; +end entity Hello_Small1; + +architecture FPGA of Hello_Small1 is + component ZPU_Small1 is + generic( + WORD_SIZE : natural:=32; -- 32 bits data path + D_CARE_VAL : std_logic:='0'; -- Fill value + CLK_FREQ : positive:=50; -- 50 MHz clock + BRATE : positive:=115200; -- RS232 baudrate + ADDR_W : natural:=16; -- 16 bits address space=64 kB, 32 kB I/O + BRAM_W : natural:=15); -- 15 bits RAM space=32 kB + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + break_o : out std_logic; -- Break executed + dbg_o : out zpu_dbgo_t; -- Debug info + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic); -- UART Rx + end component ZPU_Small1; +begin + zpu : ZPU_Small1 + generic map( + WORD_SIZE => WORD_SIZE, D_CARE_VAL => D_CARE_VAL, + CLK_FREQ => CLK_FREQ, BRATE => BRATE, ADDR_W => ADDR_W, + BRAM_W => BRAM_W) + port map( + clk_i => clk_i, rst_i => rst_i, rs232_tx_o => rs232_tx_o, + rs232_rx_i => rs232_rx_i, dbg_o => open); +end architecture FPGA; -- Entity: Hello_Small1 + diff --git a/zpu/hdl/zealot/roms/dmips_dbram.vhdl b/zpu/hdl/zealot/roms/dmips_dbram.vhdl new file mode 100644 index 0000000..32b6947 --- /dev/null +++ b/zpu/hdl/zealot/roms/dmips_dbram.vhdl @@ -0,0 +1,4485 @@ +------------------------------------------------------------------------------ +---- ---- +---- Dual Port RAM that maps to a Xilinx BRAM ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- This is a program+data memory for the ZPU. It maps to a Xilinx BRAM ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Øyvind Harboe, oyvind.harboe zylin.com ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Øyvind Harboe ---- +---- Copyright (c) 2008 Salvador E. Tropea ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the BSD license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: DualPortRAM(Xilinx) (Entity and architecture) ---- +---- File name: rom.in.vhdl (template used) ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: work ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: GHDL [Sokcho edition] (0.2x) ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity DualPortRAM is + generic( + WORD_SIZE : integer:=32; -- Word Size 16/32 + BYTE_BITS : integer:=2; -- Bits used to address bytes + BRAM_W : integer:=15); -- Address Width + port( + clk_i : in std_logic; + -- Port A + a_we_i : in std_logic; + a_addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS); + a_write_i : in unsigned(WORD_SIZE-1 downto 0); + a_read_o : out unsigned(WORD_SIZE-1 downto 0); + -- Port B + b_we_i : in std_logic; + b_addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS); + b_write_i : in unsigned(WORD_SIZE-1 downto 0); + b_read_o : out unsigned(WORD_SIZE-1 downto 0)); +end entity DualPortRAM; + +architecture Xilinx of DualPortRAM is + type ram_type is array(natural range 0 to ((2**BRAM_W)/4)-1) of unsigned(WORD_SIZE-1 downto 0); + + shared variable ram : ram_type:= +( + 0 => x"0b0b0b0b", + 1 => x"82700b0b", + 2 => x"80f8ec0c", + 3 => x"3a0b0b80", + 4 => x"e7ea0400", + 5 => x"00000000", + 6 => x"00000000", + 7 => x"00000000", + 8 => x"80088408", + 9 => x"88080b0b", + 10 => x"80e8b72d", + 11 => x"880c840c", + 12 => x"800c0400", + 13 => x"00000000", + 14 => x"00000000", + 15 => x"00000000", + 16 => x"71fd0608", + 17 => x"72830609", + 18 => x"81058205", + 19 => x"832b2a83", + 20 => x"ffff0652", + 21 => x"04000000", + 22 => x"00000000", + 23 => x"00000000", + 24 => x"71fd0608", + 25 => x"83ffff73", + 26 => x"83060981", + 27 => x"05820583", + 28 => x"2b2b0906", + 29 => x"7383ffff", + 30 => x"0b0b0b0b", + 31 => x"83a70400", + 32 => x"72098105", + 33 => x"72057373", + 34 => x"09060906", + 35 => x"73097306", + 36 => x"070a8106", + 37 => x"53510400", + 38 => x"00000000", + 39 => x"00000000", + 40 => x"72722473", + 41 => x"732e0753", + 42 => x"51040000", + 43 => x"00000000", + 44 => x"00000000", + 45 => x"00000000", + 46 => x"00000000", + 47 => x"00000000", + 48 => x"71737109", + 49 => x"71068106", + 50 => x"30720a10", + 51 => x"0a720a10", + 52 => x"0a31050a", + 53 => x"81065151", + 54 => x"53510400", + 55 => x"00000000", + 56 => x"72722673", + 57 => x"732e0753", + 58 => x"51040000", + 59 => x"00000000", + 60 => x"00000000", + 61 => x"00000000", + 62 => x"00000000", + 63 => x"00000000", + 64 => x"00000000", + 65 => x"00000000", + 66 => x"00000000", + 67 => x"00000000", + 68 => x"00000000", + 69 => x"00000000", + 70 => x"00000000", + 71 => x"00000000", + 72 => x"0b0b0b88", + 73 => x"c4040000", + 74 => x"00000000", + 75 => x"00000000", + 76 => x"00000000", + 77 => x"00000000", + 78 => x"00000000", + 79 => x"00000000", + 80 => x"720a722b", + 81 => x"0a535104", + 82 => x"00000000", + 83 => x"00000000", + 84 => x"00000000", + 85 => x"00000000", + 86 => x"00000000", + 87 => x"00000000", + 88 => x"72729f06", + 89 => x"0981050b", + 90 => x"0b0b88a7", + 91 => x"05040000", + 92 => x"00000000", + 93 => x"00000000", + 94 => x"00000000", + 95 => x"00000000", + 96 => x"72722aff", + 97 => x"739f062a", + 98 => x"0974090a", + 99 => x"8106ff05", + 100 => x"06075351", + 101 => x"04000000", + 102 => x"00000000", + 103 => x"00000000", + 104 => x"71715351", + 105 => x"020d0406", + 106 => x"73830609", + 107 => x"81058205", + 108 => x"832b0b2b", + 109 => x"0772fc06", + 110 => x"0c515104", + 111 => x"00000000", + 112 => x"72098105", + 113 => x"72050970", + 114 => x"81050906", + 115 => x"0a810653", + 116 => x"51040000", + 117 => x"00000000", + 118 => x"00000000", + 119 => x"00000000", + 120 => x"72098105", + 121 => x"72050970", + 122 => x"81050906", + 123 => x"0a098106", + 124 => x"53510400", + 125 => x"00000000", + 126 => x"00000000", + 127 => x"00000000", + 128 => x"71098105", + 129 => x"52040000", + 130 => x"00000000", + 131 => x"00000000", + 132 => x"00000000", + 133 => x"00000000", + 134 => x"00000000", + 135 => x"00000000", + 136 => x"72720981", + 137 => x"05055351", + 138 => x"04000000", + 139 => x"00000000", + 140 => x"00000000", + 141 => x"00000000", + 142 => x"00000000", + 143 => x"00000000", + 144 => x"72097206", + 145 => x"73730906", + 146 => x"07535104", + 147 => x"00000000", + 148 => x"00000000", + 149 => x"00000000", + 150 => x"00000000", + 151 => x"00000000", + 152 => x"71fc0608", + 153 => x"72830609", + 154 => x"81058305", + 155 => x"1010102a", + 156 => x"81ff0652", + 157 => x"04000000", + 158 => x"00000000", + 159 => x"00000000", + 160 => x"71fc0608", + 161 => x"0b0b80f8", + 162 => x"d8738306", + 163 => x"10100508", + 164 => x"060b0b0b", + 165 => x"88aa0400", + 166 => x"00000000", + 167 => x"00000000", + 168 => x"80088408", + 169 => x"88087575", + 170 => x"0b0b80ce", + 171 => x"b62d5050", + 172 => x"80085688", + 173 => x"0c840c80", + 174 => x"0c510400", + 175 => x"00000000", + 176 => x"80088408", + 177 => x"88087575", + 178 => x"0b0b80cf", + 179 => x"e82d5050", + 180 => x"80085688", + 181 => x"0c840c80", + 182 => x"0c510400", + 183 => x"00000000", + 184 => x"72097081", + 185 => x"0509060a", + 186 => x"8106ff05", + 187 => x"70547106", + 188 => x"73097274", + 189 => x"05ff0506", + 190 => x"07515151", + 191 => x"04000000", + 192 => x"72097081", + 193 => x"0509060a", + 194 => x"098106ff", + 195 => x"05705471", + 196 => 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x"00003d60", + 3931 => x"00003d60", + 3932 => x"00003d68", + 3933 => x"00003d68", + 3934 => x"00003d70", + 3935 => x"00003d70", + 3936 => x"00003d78", + 3937 => x"00003d78", + 3938 => x"00003d80", + 3939 => x"00003d80", + 3940 => x"00003d88", + 3941 => x"00003d88", + 3942 => x"00003d90", + 3943 => x"00003d90", + 3944 => x"00003d98", + 3945 => x"00003d98", + 3946 => x"00003da0", + 3947 => x"00003da0", + 3948 => x"00003da8", + 3949 => x"00003da8", + 3950 => x"00003db0", + 3951 => x"00003db0", + 3952 => x"00003db8", + 3953 => x"00003db8", + 3954 => x"00003dc0", + 3955 => x"00003dc0", + 3956 => x"00003dc8", + 3957 => x"00003dc8", + 3958 => x"00003dd0", + 3959 => x"00003dd0", + 3960 => x"00003dd8", + 3961 => x"00003dd8", + 3962 => x"00003de0", + 3963 => x"00003de0", + 3964 => x"00003de8", + 3965 => x"00003de8", + 3966 => x"00003df0", + 3967 => x"00003df0", + 3968 => x"00003df8", + 3969 => x"00003df8", + 3970 => x"00003e00", + 3971 => x"00003e00", + 3972 => x"00003e08", + 3973 => x"00003e08", + 3974 => x"00003e10", + 3975 => x"00003e10", + 3976 => x"00003e18", + 3977 => x"00003e18", + 3978 => x"00003e20", + 3979 => x"00003e20", + 3980 => x"00003e28", + 3981 => x"00003e28", + 3982 => x"00003e30", + 3983 => x"00003e30", + 3984 => x"00003e38", + 3985 => x"00003e38", + 3986 => x"00003e40", + 3987 => x"00003e40", + 3988 => x"00003e48", + 3989 => x"00003e48", + 3990 => x"00003e50", + 3991 => x"00003e50", + 3992 => x"00003e58", + 3993 => x"00003e58", + 3994 => x"00003e60", + 3995 => x"00003e60", + 3996 => x"00003e68", + 3997 => x"00003e68", + 3998 => x"00003e70", + 3999 => x"00003e70", + 4000 => x"00003e78", + 4001 => x"00003e78", + 4002 => x"00003e80", + 4003 => x"00003e80", + 4004 => x"00003e88", + 4005 => x"00003e88", + 4006 => x"00003e90", + 4007 => x"00003e90", + 4008 => x"00003e98", + 4009 => x"00003e98", + 4010 => x"00003ea0", + 4011 => x"00003ea0", + 4012 => x"00003ea8", + 4013 => x"00003ea8", + 4014 => x"00003eb0", + 4015 => x"00003eb0", + 4016 => x"00003eb8", + 4017 => x"00003eb8", + 4018 => x"00003ec0", + 4019 => x"00003ec0", + 4020 => x"00003ec8", + 4021 => x"00003ec8", + 4022 => x"00003ed0", + 4023 => x"00003ed0", + 4024 => x"00003ed8", + 4025 => x"00003ed8", + 4026 => x"00003ee0", + 4027 => x"00003ee0", + 4028 => x"00003ee8", + 4029 => x"00003ee8", + 4030 => x"00003ef0", + 4031 => x"00003ef0", + 4032 => x"00003ef8", + 4033 => x"00003ef8", + 4034 => x"00003f00", + 4035 => x"00003f00", + 4036 => x"00003f08", + 4037 => x"00003f08", + 4038 => x"00003f10", + 4039 => x"00003f10", + 4040 => x"00003f18", + 4041 => x"00003f18", + 4042 => x"00003f20", + 4043 => x"00003f20", + 4044 => x"00003f28", + 4045 => x"00003f28", + 4046 => x"00003f30", + 4047 => x"00003f30", + 4048 => x"00003f38", + 4049 => x"00003f38", + 4050 => x"00003f40", + 4051 => x"00003f40", + 4052 => x"00003f48", + 4053 => x"00003f48", + 4054 => x"00003f50", + 4055 => x"00003f50", + 4056 => x"00003f58", + 4057 => x"00003f58", + 4058 => x"00003f60", + 4059 => x"00003f60", + 4060 => x"00003f68", + 4061 => x"00003f68", + 4062 => x"00003f70", + 4063 => x"00003f70", + 4064 => x"00003f78", + 4065 => x"00003f78", + 4066 => x"00003f80", + 4067 => x"00003f80", + 4068 => x"00003f88", + 4069 => x"00003f88", + 4070 => x"00003f90", + 4071 => x"00003f90", + 4072 => x"00003f98", + 4073 => x"00003f98", + 4074 => x"00003fa0", + 4075 => x"00003fa0", + 4076 => x"00003fa8", + 4077 => x"00003fa8", + 4078 => x"00003fb0", + 4079 => x"00003fb0", + 4080 => x"00003fb8", + 4081 => x"00003fb8", + 4082 => x"00003fc0", + 4083 => x"00003fc0", + 4084 => x"00003fc8", + 4085 => x"00003fc8", + 4086 => x"00003fd0", + 4087 => x"00003fd0", + 4088 => x"00003fd8", + 4089 => x"00003fd8", + 4090 => x"00003fe0", + 4091 => x"00003fe0", + 4092 => x"00003fe8", + 4093 => x"00003fe8", + 4094 => x"00003ff0", + 4095 => x"00003ff0", + 4096 => x"00003ff8", + 4097 => x"00003ff8", + 4098 => x"00004000", + 4099 => x"00004000", + 4100 => x"00004008", + 4101 => x"00004008", + 4102 => x"00004010", + 4103 => x"00004010", + 4104 => x"00004018", + 4105 => x"00004018", + 4106 => x"00004020", + 4107 => x"00004020", + 4108 => x"00004028", + 4109 => x"00004028", + 4110 => x"00004030", + 4111 => x"00004030", + 4112 => x"00004038", + 4113 => x"00004038", + 4114 => x"00004040", + 4115 => x"00004040", + 4116 => x"00004048", + 4117 => x"00004048", + 4118 => x"00004050", + 4119 => x"00004050", + 4120 => x"00004058", + 4121 => x"00004058", + 4122 => x"00004060", + 4123 => x"00004060", + 4124 => x"00004068", + 4125 => x"00004068", + 4126 => x"00004070", + 4127 => x"00004070", + 4128 => x"00004078", + 4129 => x"00004078", + 4130 => x"00004080", + 4131 => x"00004080", + 4132 => x"00004088", + 4133 => x"00004088", + 4134 => x"00004090", + 4135 => x"00004090", + 4136 => x"00004098", + 4137 => x"00004098", + 4138 => x"000040a0", + 4139 => x"000040a0", + 4140 => x"000040a8", + 4141 => x"000040a8", + 4142 => x"000040b0", + 4143 => x"000040b0", + 4144 => x"000040b8", + 4145 => x"000040b8", + 4146 => x"000040cc", + 4147 => x"00000000", + 4148 => x"00004334", + 4149 => x"00004390", + 4150 => x"000043ec", + 4151 => x"00000000", + 4152 => x"00000000", + 4153 => x"00000000", + 4154 => x"00000000", + 4155 => x"00000000", + 4156 => x"00000000", + 4157 => x"00000000", + 4158 => x"00000000", + 4159 => x"00000000", + 4160 => x"00003c48", + 4161 => x"00000000", + 4162 => x"00000000", + 4163 => x"00000000", + 4164 => x"00000000", + 4165 => x"00000000", + 4166 => x"00000000", + 4167 => x"00000000", + 4168 => x"00000000", + 4169 => x"00000000", + 4170 => x"00000000", + 4171 => x"00000000", + 4172 => x"00000000", + 4173 => x"00000000", + 4174 => x"00000000", + 4175 => x"00000000", + 4176 => x"00000000", + 4177 => x"00000000", + 4178 => x"00000000", + 4179 => x"00000000", + 4180 => x"00000000", + 4181 => x"00000000", + 4182 => x"00000000", + 4183 => x"00000000", + 4184 => x"00000000", + 4185 => x"00000000", + 4186 => x"00000000", + 4187 => x"00000000", + 4188 => x"00000000", + 4189 => x"00000001", + 4190 => x"330eabcd", + 4191 => x"1234e66d", + 4192 => x"deec0005", + 4193 => x"000b0000", + 4194 => x"00000000", + 4195 => x"00000000", + 4196 => x"00000000", + 4197 => x"00000000", + 4198 => x"00000000", + 4199 => x"00000000", + 4200 => x"00000000", + 4201 => x"00000000", + 4202 => x"00000000", + 4203 => x"00000000", + 4204 => x"00000000", + 4205 => x"00000000", + 4206 => x"00000000", + 4207 => x"00000000", + 4208 => x"00000000", + 4209 => x"00000000", + 4210 => x"00000000", + 4211 => x"00000000", + 4212 => x"00000000", + 4213 => x"00000000", + 4214 => x"00000000", + 4215 => x"00000000", + 4216 => x"00000000", + 4217 => x"00000000", + 4218 => x"00000000", + 4219 => x"00000000", + 4220 => x"00000000", + 4221 => x"00000000", + 4222 => x"00000000", + 4223 => x"00000000", + 4224 => x"00000000", + 4225 => x"00000000", + 4226 => x"00000000", + 4227 => x"00000000", + 4228 => x"00000000", + 4229 => x"00000000", + 4230 => x"00000000", + 4231 => x"00000000", + 4232 => x"00000000", + 4233 => x"00000000", + 4234 => x"00000000", + 4235 => x"00000000", + 4236 => x"00000000", + 4237 => x"00000000", + 4238 => x"00000000", + 4239 => x"00000000", + 4240 => x"00000000", + 4241 => x"00000000", + 4242 => x"00000000", + 4243 => x"00000000", + 4244 => x"00000000", + 4245 => x"00000000", + 4246 => x"00000000", + 4247 => x"00000000", + 4248 => x"00000000", + 4249 => x"00000000", + 4250 => x"00000000", + 4251 => x"00000000", + 4252 => x"00000000", + 4253 => x"00000000", + 4254 => x"00000000", + 4255 => x"00000000", + 4256 => x"00000000", + 4257 => x"00000000", + 4258 => x"00000000", + 4259 => x"00000000", + 4260 => x"00000000", + 4261 => x"00000000", + 4262 => x"00000000", + 4263 => x"00000000", + 4264 => x"00000000", + 4265 => x"00000000", + 4266 => x"00000000", + 4267 => x"00000000", + 4268 => x"00000000", + 4269 => x"00000000", + 4270 => x"00000000", + 4271 => x"00000000", + 4272 => x"00000000", + 4273 => x"00000000", + 4274 => x"00000000", + 4275 => x"00000000", + 4276 => x"00000000", + 4277 => x"00000000", + 4278 => x"00000000", + 4279 => x"00000000", + 4280 => x"00000000", + 4281 => x"00000000", + 4282 => x"00000000", + 4283 => x"00000000", + 4284 => x"00000000", + 4285 => x"00000000", + 4286 => x"00000000", + 4287 => x"00000000", + 4288 => x"00000000", + 4289 => x"00000000", + 4290 => x"00000000", + 4291 => x"00000000", + 4292 => x"00000000", + 4293 => x"00000000", + 4294 => x"00000000", + 4295 => x"00000000", + 4296 => x"00000000", + 4297 => x"00000000", + 4298 => x"00000000", + 4299 => x"00000000", + 4300 => x"00000000", + 4301 => x"00000000", + 4302 => x"00000000", + 4303 => x"00000000", + 4304 => x"00000000", + 4305 => x"00000000", + 4306 => x"00000000", + 4307 => x"00000000", + 4308 => x"00000000", + 4309 => x"00000000", + 4310 => x"00000000", + 4311 => x"00000000", + 4312 => x"00000000", + 4313 => x"00000000", + 4314 => x"00000000", + 4315 => x"00000000", + 4316 => x"00000000", + 4317 => x"00000000", + 4318 => x"00000000", + 4319 => x"00000000", + 4320 => x"00000000", + 4321 => x"00000000", + 4322 => x"00000000", + 4323 => x"00000000", + 4324 => x"00000000", + 4325 => x"00000000", + 4326 => x"00000000", + 4327 => x"00000000", + 4328 => x"00000000", + 4329 => x"00000000", + 4330 => x"00000000", + 4331 => x"00000000", + 4332 => x"00000000", + 4333 => x"00000000", + 4334 => x"00000000", + 4335 => x"00000000", + 4336 => x"00000000", + 4337 => x"00000000", + 4338 => x"00000000", + 4339 => x"00000000", + 4340 => x"00000000", + 4341 => x"00000000", + 4342 => x"00000000", + 4343 => x"00000000", + 4344 => x"00000000", + 4345 => x"00000000", + 4346 => x"00000000", + 4347 => x"00000000", + 4348 => x"00000000", + 4349 => x"00000000", + 4350 => x"00000000", + 4351 => x"00000000", + 4352 => x"00000000", + 4353 => x"00000000", + 4354 => x"00000000", + 4355 => x"00000000", + 4356 => x"00000000", + 4357 => x"00000000", + 4358 => x"00000000", + 4359 => x"00000000", + 4360 => x"00000000", + 4361 => x"00000000", + 4362 => x"00000000", + 4363 => x"00000000", + 4364 => x"00000000", + 4365 => x"00000000", + 4366 => x"00000000", + 4367 => x"00000000", + 4368 => x"00000000", + 4369 => x"00000000", + 4370 => x"00003c4c", + 4371 => x"ffffffff", + 4372 => x"00000000", + 4373 => x"ffffffff", + 4374 => x"00000000", + 4375 => x"00000000", + +others => x"00000000" +); +begin + do_port_a: + process (clk_i) + variable iaddr : integer; + begin + if rising_edge(clk_i) then + if (a_we_i='1') and (b_we_i='1') and (a_addr_i=b_addr_i) and (a_write_i/=b_write_i) then + report "DualPortRAM write collision" severity failure; + end if; + iaddr:=to_integer(a_addr_i); + if a_we_i='1' then + ram(iaddr):=a_write_i; + -- Write First mode + a_read_o <= a_write_i; + else + a_read_o <= ram(iaddr); + end if; + end if; + end process do_port_a; + + do_port_b: + process (clk_i) + variable iaddr : integer; + begin + if rising_edge(clk_i) then + iaddr:=to_integer(b_addr_i); + if b_we_i='1' then + ram(iaddr):=b_write_i; + b_read_o <= b_write_i; + else + b_read_o <= ram(iaddr); + end if; + end if; + end process do_port_b; +end architecture Xilinx; -- Entity: DualPortRAM diff --git a/zpu/hdl/zealot/roms/hello_dbram.vhdl b/zpu/hdl/zealot/roms/hello_dbram.vhdl new file mode 100644 index 0000000..28cac6f --- /dev/null +++ b/zpu/hdl/zealot/roms/hello_dbram.vhdl @@ -0,0 +1,3035 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity DualPortRAM is + generic( + WORD_SIZE : integer:=32; -- Word Size 16/32 + BYTE_BITS : integer:=2; -- Bits used to address bytes + BRAM_W : integer:=15); -- Address Width + port( + clk_i : in std_logic; + -- Port A + a_we_i : in std_logic; + a_addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS); + a_write_i : in unsigned(WORD_SIZE-1 downto 0); + a_read_o : out unsigned(WORD_SIZE-1 downto 0); + -- Port B + b_we_i : in std_logic; + b_addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS); + b_write_i : in unsigned(WORD_SIZE-1 downto 0); + b_read_o : out unsigned(WORD_SIZE-1 downto 0)); +end entity DualPortRAM; + +architecture DualPort_Arch of DualPortRAM is + type ram_type is array(natural range 0 to ((2**BRAM_W)/4)-1) of unsigned(WORD_SIZE-1 downto 0); + + shared variable ram : ram_type:= +( + 0 => x"0b0b0b0b", + 1 => x"82700b0b", + 2 => x"80cd800c", + 3 => x"3a0b0b80", + 4 => x"c58f0400", + 5 => x"00000000", + 6 => x"00000000", + 7 => x"00000000", + 8 => x"80088408", + 9 => x"88080b0b", + 10 => x"80c5d62d", + 11 => x"880c840c", + 12 => x"800c0400", + 13 => x"00000000", + 14 => x"00000000", + 15 => x"00000000", + 16 => x"71fd0608", + 17 => x"72830609", + 18 => x"81058205", + 19 => x"832b2a83", + 20 => x"ffff0652", + 21 => x"04000000", + 22 => x"00000000", + 23 => x"00000000", + 24 => x"71fd0608", + 25 => x"83ffff73", + 26 => x"83060981", + 27 => x"05820583", + 28 => x"2b2b0906", + 29 => x"7383ffff", + 30 => x"0b0b0b0b", + 31 => x"83a70400", + 32 => x"72098105", + 33 => x"72057373", + 34 => x"09060906", + 35 => x"73097306", + 36 => x"070a8106", + 37 => x"53510400", + 38 => x"00000000", + 39 => x"00000000", + 40 => x"72722473", + 41 => x"732e0753", + 42 => x"51040000", + 43 => x"00000000", + 44 => x"00000000", + 45 => x"00000000", + 46 => x"00000000", + 47 => x"00000000", + 48 => x"71737109", + 49 => x"71068106", + 50 => x"30720a10", + 51 => x"0a720a10", + 52 => x"0a31050a", + 53 => x"81065151", + 54 => x"53510400", + 55 => x"00000000", + 56 => x"72722673", + 57 => x"732e0753", + 58 => x"51040000", + 59 => x"00000000", + 60 => x"00000000", + 61 => x"00000000", + 62 => x"00000000", + 63 => x"00000000", + 64 => x"00000000", + 65 => x"00000000", + 66 => x"00000000", + 67 => x"00000000", + 68 => x"00000000", + 69 => x"00000000", + 70 => x"00000000", + 71 => x"00000000", + 72 => x"0b0b0b88", + 73 => x"c4040000", + 74 => x"00000000", + 75 => x"00000000", + 76 => x"00000000", + 77 => x"00000000", + 78 => x"00000000", + 79 => x"00000000", + 80 => x"720a722b", + 81 => x"0a535104", + 82 => x"00000000", + 83 => x"00000000", + 84 => x"00000000", + 85 => x"00000000", + 86 => x"00000000", + 87 => x"00000000", + 88 => x"72729f06", + 89 => x"0981050b", + 90 => x"0b0b88a7", + 91 => x"05040000", + 92 => x"00000000", + 93 => x"00000000", + 94 => x"00000000", + 95 => x"00000000", + 96 => x"72722aff", + 97 => x"739f062a", + 98 => x"0974090a", + 99 => x"8106ff05", + 100 => x"06075351", + 101 => x"04000000", + 102 => x"00000000", + 103 => x"00000000", + 104 => x"71715351", + 105 => x"020d0406", + 106 => x"73830609", + 107 => x"81058205", + 108 => x"832b0b2b", + 109 => x"0772fc06", + 110 => x"0c515104", + 111 => x"00000000", + 112 => x"72098105", + 113 => x"72050970", + 114 => x"81050906", + 115 => x"0a810653", + 116 => x"51040000", + 117 => x"00000000", + 118 => x"00000000", + 119 => x"00000000", + 120 => x"72098105", + 121 => x"72050970", + 122 => x"81050906", + 123 => x"0a098106", + 124 => x"53510400", + 125 => x"00000000", + 126 => x"00000000", + 127 => x"00000000", + 128 => x"71098105", + 129 => x"52040000", + 130 => x"00000000", + 131 => x"00000000", + 132 => x"00000000", + 133 => x"00000000", + 134 => x"00000000", + 135 => x"00000000", + 136 => x"72720981", + 137 => x"05055351", + 138 => x"04000000", + 139 => x"00000000", + 140 => x"00000000", + 141 => x"00000000", + 142 => x"00000000", + 143 => x"00000000", + 144 => x"72097206", + 145 => x"73730906", + 146 => x"07535104", + 147 => x"00000000", + 148 => x"00000000", + 149 => x"00000000", + 150 => x"00000000", + 151 => x"00000000", + 152 => x"71fc0608", + 153 => x"72830609", + 154 => x"81058305", + 155 => x"1010102a", + 156 => x"81ff0652", + 157 => x"04000000", + 158 => x"00000000", + 159 => x"00000000", + 160 => x"71fc0608", + 161 => x"0b0b80cc", + 162 => x"ec738306", + 163 => x"10100508", + 164 => x"060b0b0b", + 165 => x"88aa0400", + 166 => x"00000000", + 167 => x"00000000", + 168 => x"80088408", + 169 => x"88087575", + 170 => x"0b0b0b8b", + 171 => x"8a2d5050", + 172 => x"80085688", + 173 => x"0c840c80", + 174 => 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x"00002b90", + 2792 => x"00002b98", + 2793 => x"00002b98", + 2794 => x"00002ba0", + 2795 => x"00002ba0", + 2796 => x"00002ba8", + 2797 => x"00002ba8", + 2798 => x"00002bb0", + 2799 => x"00002bb0", + 2800 => x"00002bb8", + 2801 => x"00002bb8", + 2802 => x"00002bc0", + 2803 => x"00002bc0", + 2804 => x"00002bc8", + 2805 => x"00002bc8", + 2806 => x"00002bd0", + 2807 => x"00002bd0", + 2808 => x"00002bd8", + 2809 => x"00002bd8", + 2810 => x"00002be0", + 2811 => x"00002be0", + 2812 => x"00002be8", + 2813 => x"00002be8", + 2814 => x"00002bf0", + 2815 => x"00002bf0", + 2816 => x"00002bf8", + 2817 => x"00002bf8", + 2818 => x"00002c00", + 2819 => x"00002c00", + 2820 => x"00002c08", + 2821 => x"00002c08", + 2822 => x"00002c10", + 2823 => x"00002c10", + 2824 => x"00002c18", + 2825 => x"00002c18", + 2826 => x"00002c20", + 2827 => x"00002c20", + 2828 => x"00002c28", + 2829 => x"00002c28", + 2830 => x"00002c30", + 2831 => x"00002c30", + 2832 => x"00002c38", + 2833 => x"00002c38", + 2834 => x"00002c40", + 2835 => x"00002c40", + 2836 => x"00002c48", + 2837 => x"00002c48", + 2838 => x"00002c50", + 2839 => x"00002c50", + 2840 => x"00002c58", + 2841 => x"00002c58", + 2842 => x"00002c60", + 2843 => x"00002c60", + 2844 => x"00002c68", + 2845 => x"00002c68", + 2846 => x"00002c70", + 2847 => x"00002c70", + 2848 => x"00002c78", + 2849 => x"00002c78", + 2850 => x"00002c80", + 2851 => x"00002c80", + 2852 => x"00002c88", + 2853 => x"00002c88", + 2854 => x"00002c90", + 2855 => x"00002c90", + 2856 => x"00002c98", + 2857 => x"00002c98", + 2858 => x"00002ca0", + 2859 => x"00002ca0", + 2860 => x"00002ca8", + 2861 => x"00002ca8", + 2862 => x"00002cb0", + 2863 => x"00002cb0", + 2864 => x"00002cb8", + 2865 => x"00002cb8", + 2866 => x"00002cc0", + 2867 => x"00002cc0", + 2868 => x"00002cc8", + 2869 => x"00002cc8", + 2870 => x"00002cd0", + 2871 => x"00002cd0", + 2872 => x"00002cd8", + 2873 => x"00002cd8", + 2874 => x"00002ce0", + 2875 => x"00002ce0", + 2876 => x"00002ce8", + 2877 => x"00002ce8", + 2878 => x"00002cf0", + 2879 => x"00002cf0", + 2880 => x"00002cf8", + 2881 => x"00002cf8", + 2882 => x"00002d00", + 2883 => x"00002d00", + 2884 => x"00002d08", + 2885 => x"00002d08", + 2886 => x"00002d10", + 2887 => x"00002d10", + 2888 => x"00002d18", + 2889 => x"00002d18", + 2890 => x"00002d20", + 2891 => x"00002d20", + 2892 => x"00002d28", + 2893 => x"00002d28", + 2894 => x"00002d30", + 2895 => x"00002d30", + 2896 => x"00002d38", + 2897 => x"00002d38", + 2898 => x"00002d40", + 2899 => x"00002d40", + 2900 => x"00002d48", + 2901 => x"00002d48", + 2902 => x"00002d50", + 2903 => x"00002d50", + 2904 => x"00002d58", + 2905 => x"00002d58", + 2906 => x"00002d60", + 2907 => x"00002d60", + 2908 => x"00002d68", + 2909 => x"00002d68", + 2910 => x"00002d70", + 2911 => x"00002d70", + 2912 => x"00002d78", + 2913 => x"00002d78", + 2914 => x"00002d80", + 2915 => x"00002d80", + 2916 => x"00002d88", + 2917 => x"00002d88", + 2918 => x"00002d90", + 2919 => x"00002d90", + 2920 => x"00002d98", + 2921 => x"00002d98", + 2922 => x"00002da0", + 2923 => x"00002da0", + 2924 => x"00002da8", + 2925 => x"00002da8", + 2926 => x"00002db0", + 2927 => x"00002db0", + 2928 => x"00002db8", + 2929 => x"00002db8", + 2930 => x"00002dc0", + 2931 => x"00002dc0", + 2932 => x"00002dc8", + 2933 => x"00002dc8", + 2934 => x"00002dd0", + 2935 => x"00002dd0", + 2936 => x"00002dd8", + 2937 => x"00002dd8", + 2938 => x"00002de0", + 2939 => x"00002de0", + 2940 => x"00002de8", + 2941 => x"00002de8", + 2942 => x"00002df0", + 2943 => x"00002df0", + 2944 => x"00002df8", + 2945 => x"00002df8", + 2946 => x"00002e00", + 2947 => x"00002e00", + 2948 => x"00002e08", + 2949 => x"00002e08", + 2950 => x"00002e10", + 2951 => x"00002e10", + 2952 => x"00002e18", + 2953 => x"00002e18", + 2954 => x"00002e20", + 2955 => x"00002e20", + 2956 => x"00002e28", + 2957 => x"00002e28", + 2958 => x"00002e30", + 2959 => x"00002e30", + 2960 => x"00002e38", + 2961 => x"00002e38", + 2962 => x"00002e40", + 2963 => x"00002e40", + 2964 => x"00002660", + 2965 => x"ffffffff", + 2966 => x"00000000", + 2967 => x"ffffffff", + 2968 => x"00000000", + 2969 => x"00000000", + +others => x"00000000" +); +begin + do_port_a: + process (clk_i) + variable iaddr : integer; + begin + if rising_edge(clk_i) then + if (a_we_i='1') and (b_we_i='1') and (a_addr_i=b_addr_i) and (a_write_i/=b_write_i) then + report "DualPortRAM write collision" severity failure; + end if; + iaddr:=to_integer(a_addr_i); + if a_we_i='1' then + ram(iaddr):=a_write_i; + a_read_o <= a_write_i; + else + a_read_o <= ram(iaddr); + end if; + end if; + end process do_port_a; + + do_port_b: + process (clk_i) + variable iaddr : integer; + begin + if rising_edge(clk_i) then + iaddr:=to_integer(b_addr_i); + if b_we_i='1' then + ram(iaddr):=b_write_i; + b_read_o <= b_write_i; + else + b_read_o <= ram(iaddr); + end if; + end if; + end process do_port_b; +end architecture DualPort_Arch; -- Entity: DualPortRAM diff --git a/zpu/hdl/zealot/testbenches/small1_tb.vhdl b/zpu/hdl/zealot/testbenches/small1_tb.vhdl new file mode 100644 index 0000000..bada24b --- /dev/null +++ b/zpu/hdl/zealot/testbenches/small1_tb.vhdl @@ -0,0 +1,129 @@ +------------------------------------------------------------------------------ +---- ---- +---- Testbench for the ZPU Small connection to the FPGA ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- This is a testbench to simulate the ZPU_Small1 core as used in the ---- +---- *_small1.vhdl ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Salvador E. Tropea ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the BSD license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: Small1_TB(Behave) (Entity and architecture) ---- +---- File name: small1_tb.vhdl ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: work ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- zpu.zpupkg ---- +---- zpu.txt_util ---- +---- work.zpu_memory ---- +---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: N/A ---- +---- Simulation tools: GHDL [Sokcho edition] (0.2x) ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library zpu; +use zpu.zpupkg.all; +use zpu.txt_util.all; + +library work; +use work.zpu_memory.all; + +entity Small1_TB is +end entity Small1_TB; + +architecture Behave of Small1_TB is + constant WORD_SIZE : natural:=32; -- 32 bits data path + constant ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O + constant BRAM_W : natural:=15; -- 15 bits RAM space=32 kB + constant D_CARE_VAL : std_logic:='0'; -- Fill value + constant CLK_FREQ : positive:=50; -- 50 MHz clock + constant CLK_S_PER : time:=1 us/(2.0*real(CLK_FREQ)); -- Clock semi period + constant BRATE : positive:=115200; + + component ZPU_Small1 is + generic( + WORD_SIZE : natural:=32; -- 32 bits data path + D_CARE_VAL : std_logic:='0'; -- Fill value + CLK_FREQ : positive:=50; -- 50 MHz clock + BRATE : positive:=115200; -- RS232 baudrate + ADDR_W : natural:=16; -- 16 bits address space=64 kB, 32 kB I/O + BRAM_W : natural:=15); -- 15 bits RAM space=32 kB + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + break_o : out std_logic; -- Break executed + dbg_o : out zpu_dbgo_t; -- Debug info + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic); -- UART Rx + end component ZPU_Small1; + + signal clk : std_logic; + signal reset : std_logic:='1'; + + signal break : std_logic; + signal dbg : zpu_dbgo_t; -- Debug info + signal rs232_tx : std_logic; + signal rs232_rx : std_logic; +begin + zpu : ZPU_Small1 + generic map( + WORD_SIZE => WORD_SIZE, D_CARE_VAL => D_CARE_VAL, + CLK_FREQ => CLK_FREQ, BRATE => BRATE, ADDR_W => ADDR_W, + BRAM_W => BRAM_W) + port map( + clk_i => clk, rst_i => reset, rs232_tx_o => rs232_tx, + rs232_rx_i => rs232_rx, break_o => break, dbg_o => dbg); + + trace_mod : Trace + generic map( + ADDR_W => ADDR_W, WORD_SIZE => WORD_SIZE, + LOG_FILE => "small1_trace.log") + port map( + clk_i => clk, dbg_i => dbg, stop_i => break, busy_i => '0'); + + do_clock: + process + begin + clk <= '0'; + wait for CLK_S_PER; + clk <= '1'; + wait for CLK_S_PER; + if break='1' then + print("* Break asserted, end of test"); + wait; + end if; + end process do_clock; + + do_reset: + process + begin + wait until rising_edge(clk); + reset <= '0'; + end process do_reset; +end architecture Behave; -- Entity: Small1_TB diff --git a/zpu/hdl/zealot/zpu_pkg.vhdl b/zpu/hdl/zealot/zpu_pkg.vhdl index 15ac700..2a15880 100644 --- a/zpu/hdl/zealot/zpu_pkg.vhdl +++ b/zpu/hdl/zealot/zpu_pkg.vhdl @@ -1,270 +1,269 @@ ------------------------------------------------------------------------------- ----- ---- ----- ZPU Package ---- ----- ---- ----- http://www.opencores.org/ ---- ----- ---- ----- Description: ---- ----- ZPU is a 32 bits small stack cpu. This is the package. ---- ----- ---- ----- To Do: ---- ----- - ---- ----- ---- ----- Author: ---- ----- - Øyvind Harboe, oyvind.harboe zylin.com ---- ----- - Salvador E. Tropea, salvador inti.gob.ar ---- ----- ---- ------------------------------------------------------------------------------- ----- ---- ----- Copyright (c) 2008 Øyvind Harboe ---- ----- Copyright (c) 2008 Salvador E. Tropea ---- ----- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- ----- ---- ----- Distributed under the BSD license ---- ----- ---- ------------------------------------------------------------------------------- ----- ---- ----- Design unit: zpupkg, UART (Package) ---- ----- File name: zpu_medium.vhdl ---- ----- Note: None ---- ----- Limitations: None known ---- ----- Errors: None known ---- ----- Library: zpu ---- ----- Dependencies: IEEE.std_logic_1164 ---- ----- IEEE.numeric_std ---- ----- Target FPGA: Spartan 3 (XC3S400-4-FT256) ---- ----- Language: VHDL ---- ----- Wishbone: No ---- ----- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- ----- Simulation tools: GHDL [Sokcho edition] (0.2x) ---- ----- Text editor: SETEdit 0.5.x ---- ----- ---- ------------------------------------------------------------------------------- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -package zpupkg is - constant OPCODE_W : integer:=8; - - -- Debug structure, currently only for the trace module - type zpu_dbgo_t is record - b_inst : std_logic; - opcode : unsigned(OPCODE_W-1 downto 0); - pc : unsigned(31 downto 0); - sp : unsigned(31 downto 0); - stk_a : unsigned(31 downto 0); - stk_b : unsigned(31 downto 0); - end record; - - component Trace is - generic( - LOG_FILE : string:="trace.txt"; -- Name of the trace file - ADDR_W : integer:=16; -- Address width - WORD_SIZE : integer:=32); -- 16/32 - port( - clk_i : in std_logic; - dbg_i : in zpu_dbgo_t; - stop_i : in std_logic; - busy_i : in std_logic - ); - end component Trace; - - component ZPUSmallCore is - generic( - WORD_SIZE : integer:=32; -- 16/32 (2**wordPower) - ADDR_W : integer:=16; -- maxAddrBitIncIO+1 - BRAM_W : integer:=15; -- maxAddrBitBRAM+1 - D_CARE_VAL : std_logic:='X'); -- Value used to fill the unsused bits - port( - clk_i : in std_logic; -- System Clock - reset_i : in std_logic; -- Synchronous Reset - enable_i : in std_logic; -- Not used - interrupt_i : in std_logic; -- Interrupt - break_o : out std_logic; -- Breakpoint opcode executed - dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log) - -- BRAM (text, data, bss and stack) - a_we_o : out std_logic; -- BRAM A port Write Enable - a_addr_o : out unsigned(BRAM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM A Address - a_write_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM A port - a_read_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM A port - b_we_o : out std_logic; -- BRAM B port Write Enable - b_addr_o : out unsigned(BRAM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM B Address - b_write_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM B port - b_read_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM B port - -- Memory mapped I/O - mem_busy_i : in std_logic; - data_i : in unsigned(WORD_SIZE-1 downto 0); - data_o : out unsigned(WORD_SIZE-1 downto 0); - addr_o : out unsigned(ADDR_W-1 downto 0); - write_en_o : out std_logic; - read_en_o : out std_logic); - end component ZPUSmallCore; - - component ZPUMediumCore is - generic( - WORD_SIZE : integer:=32; -- 16/32 (2**wordPower) - ADDR_W : integer:=16; -- Total address space width (incl. I/O) - MEM_W : integer:=15; -- Memory (prog+data+stack) width - D_CARE_VAL : std_logic:='X'; -- Value used to fill the unsused bits - MULT_PIPE : boolean:=false; -- Pipeline multiplication - BINOP_PIPE : integer range 0 to 2:=0; -- Pipeline binary operations (-, =, < and <=) - ENA_LEVEL0 : boolean:=true; -- eq, loadb, neqbranch and pushspadd - ENA_LEVEL1 : boolean:=true; -- lessthan, ulessthan, mult, storeb, callpcrel and sub - ENA_LEVEL2 : boolean:=false; -- lessthanorequal, ulessthanorequal, call and poppcrel - ENA_LSHR : boolean:=true; -- lshiftright - ENA_IDLE : boolean:=false; -- Enable the enable_i input - FAST_FETCH : boolean:=true); -- Merge the st_fetch with the st_execute states - port( - clk_i : in std_logic; -- CPU Clock - reset_i : in std_logic; -- Sync Reset - enable_i : in std_logic; -- Hold the CPU (after reset) - break_o : out std_logic; -- Break instruction executed - dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log) - -- Memory interface - mem_busy_i : in std_logic; -- Memory is busy - data_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from mem - data_o : out unsigned(WORD_SIZE-1 downto 0); -- Data to mem - addr_o : out unsigned(ADDR_W-1 downto 0); -- Memory address - write_en_o : out std_logic; -- Memory write enable - read_en_o : out std_logic); -- Memory read enable - end component ZPUMediumCore; - - component Timer is - port( - clk_i : in std_logic; - reset_i : in std_logic; - we_i : in std_logic; - data_i : in unsigned(31 downto 0); - addr_i : in unsigned(0 downto 0); - data_o : out unsigned(31 downto 0)); - end component Timer; - - component ZPUPhiIO is - generic( - BRDIVISOR : positive:=1; -- Baud rate divisor i.e. br_clk/9600/4 - ENA_LOG : boolean:=true; -- Enable log - LOG_FILE : string:="log.txt"); -- Name for the log file - port( - clk_i : in std_logic; -- System Clock - reset_i : in std_logic; -- Synchronous Reset - busy_o : out std_logic; -- I/O is busy - we_i : in std_logic; -- Write Enable - re_i : in std_logic; -- Read Enable - data_i : in unsigned(31 downto 0); - data_o : out unsigned(31 downto 0); - addr_i : in unsigned(2 downto 0); -- Address bits 4-2 - rs232_rx_i : in std_logic; -- UART Rx input - rs232_tx_o : out std_logic; -- UART Tx output - br_clk_i : in std_logic); -- UART base clock (enable) - end component ZPUPhiIO; - - -- Opcode decode constants - -- Note: these are the basic opcodes, always implemented using hardware. - constant OPCODE_IM : unsigned(7 downto 7):="1"; - constant OPCODE_STORESP : unsigned(7 downto 5):="010"; - constant OPCODE_LOADSP : unsigned(7 downto 5):="011"; - constant OPCODE_EMULATE : unsigned(7 downto 5):="001"; - constant OPCODE_ADDSP : unsigned(7 downto 4):="0001"; - constant OPCODE_SHORT : unsigned(7 downto 4):="0000"; - - constant OPCODE_BREAK : unsigned(3 downto 0):="0000"; - constant OPCODE_SHIFTLEFT : unsigned(3 downto 0):="0001"; - constant OPCODE_PUSHSP : unsigned(3 downto 0):="0010"; - constant OPCODE_PUSHINT : unsigned(3 downto 0):="0011"; - - constant OPCODE_POPPC : unsigned(3 downto 0):="0100"; - constant OPCODE_ADD : unsigned(3 downto 0):="0101"; - constant OPCODE_AND : unsigned(3 downto 0):="0110"; - constant OPCODE_OR : unsigned(3 downto 0):="0111"; - - constant OPCODE_LOAD : unsigned(3 downto 0):="1000"; - constant OPCODE_NOT : unsigned(3 downto 0):="1001"; - constant OPCODE_FLIP : unsigned(3 downto 0):="1010"; - constant OPCODE_NOP : unsigned(3 downto 0):="1011"; - - constant OPCODE_STORE : unsigned(3 downto 0):="1100"; - constant OPCODE_POPSP : unsigned(3 downto 0):="1101"; - constant OPCODE_COMPARE : unsigned(3 downto 0):="1110"; - constant OPCODE_POPINT : unsigned(3 downto 0):="1111"; - - -- The following instructions are emulated in the small version and - -- implemented as hardware in the full version. - -- The constants correpond to the "emulated" instruction number. - - -- Enabled by the ENA_LEVEL0 generic: - constant OPCODE_EQ : unsigned(5 downto 0):=to_unsigned(46,6); - constant OPCODE_LOADB : unsigned(5 downto 0):=to_unsigned(51,6); - constant OPCODE_NEQBRANCH : unsigned(5 downto 0):=to_unsigned(56,6); - constant OPCODE_PUSHSPADD : unsigned(5 downto 0):=to_unsigned(61,6); - -- Enabled by the ENA_LEVEL1 generic: - constant OPCODE_LESSTHAN : unsigned(5 downto 0):=to_unsigned(36,6); - constant OPCODE_ULESSTHAN : unsigned(5 downto 0):=to_unsigned(38,6); - constant OPCODE_MULT : unsigned(5 downto 0):=to_unsigned(41,6); - constant OPCODE_STOREB : unsigned(5 downto 0):=to_unsigned(52,6); - constant OPCODE_CALLPCREL : unsigned(5 downto 0):=to_unsigned(63,6); - constant OPCODE_SUB : unsigned(5 downto 0):=to_unsigned(49,6); - -- Enabled by the ENA_LEVEL2 generic: - constant OPCODE_LESSTHANOREQUAL : unsigned(5 downto 0):=to_unsigned(37,6); - constant OPCODE_ULESSTHANOREQUAL : unsigned(5 downto 0):=to_unsigned(39,6); - constant OPCODE_CALL : unsigned(5 downto 0):=to_unsigned(45,6); - constant OPCODE_POPPCREL : unsigned(5 downto 0):=to_unsigned(57,6); - -- Enabled by the ENA_LSHR generic: - constant OPCODE_LSHIFTRIGHT : unsigned(5 downto 0):=to_unsigned(42,6); - -- The following opcodes are always emulated. - constant OPCODE_LOADH : unsigned(5 downto 0):=to_unsigned(34,6); - constant OPCODE_STOREH : unsigned(5 downto 0):=to_unsigned(35,6); - constant OPCODE_ASHIFTLEFT : unsigned(5 downto 0):=to_unsigned(43,6); - constant OPCODE_ASHIFTRIGHT : unsigned(5 downto 0):=to_unsigned(44,6); - constant OPCODE_NEQ : unsigned(5 downto 0):=to_unsigned(47,6); - constant OPCODE_NEG : unsigned(5 downto 0):=to_unsigned(48,6); - constant OPCODE_XOR : unsigned(5 downto 0):=to_unsigned(50,6); - constant OPCODE_DIV : unsigned(5 downto 0):=to_unsigned(53,6); - constant OPCODE_MOD : unsigned(5 downto 0):=to_unsigned(54,6); - constant OPCODE_EQBRANCH : unsigned(5 downto 0):=to_unsigned(55,6); - constant OPCODE_CONFIG : unsigned(5 downto 0):=to_unsigned(58,6); - constant OPCODE_PUSHPC : unsigned(5 downto 0):=to_unsigned(59,6); -end package zpupkg; - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -package UART is - ---------------------- - -- Very simple UART -- - ---------------------- - component RxUnit is - port( - clk_i : in std_logic; -- System clock signal - reset_i : in std_logic; -- Reset input (sync) - enable_i : in std_logic; -- Enable input (rate*4) - read_i : in std_logic; -- Received Byte Read - rxd_i : in std_logic; -- RS-232 data input - rxav_o : out std_logic; -- Byte available - datao_o : out std_logic_vector(7 downto 0)); -- Byte received - end component RxUnit; - - component TxUnit is - port ( - clk_i : in std_logic; -- Clock signal - reset_i : in std_logic; -- Reset input - enable_i : in std_logic; -- Enable input - load_i : in std_logic; -- Load input - txd_o : out std_logic; -- RS-232 data output - busy_o : out std_logic; -- Tx Busy - datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit - end component TxUnit; - - component BRGen is - generic( - COUNT : integer range 0 to 65535);-- Count revolution - port ( - clk_i : in std_logic; -- Clock - reset_i : in std_logic; -- Reset input - ce_i : in std_logic; -- Chip Enable - o_o : out std_logic); -- Output - end component BRGen; -end package UART; - +------------------------------------------------------------------------------ +---- ---- +---- ZPU Package ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- ZPU is a 32 bits small stack cpu. This is the package. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Øyvind Harboe, oyvind.harboe zylin.com ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Øyvind Harboe ---- +---- Copyright (c) 2008 Salvador E. Tropea ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the BSD license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: zpupkg, UART (Package) ---- +---- File name: zpu_medium.vhdl ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: zpu ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- Target FPGA: Spartan 3 (XC3S400-4-FT256) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: GHDL [Sokcho edition] (0.2x) ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +package zpupkg is + constant OPCODE_W : integer:=8; + + -- Debug structure, currently only for the trace module + type zpu_dbgo_t is record + b_inst : std_logic; + opcode : unsigned(OPCODE_W-1 downto 0); + pc : unsigned(31 downto 0); + sp : unsigned(31 downto 0); + stk_a : unsigned(31 downto 0); + stk_b : unsigned(31 downto 0); + end record; + + component Trace is + generic( + LOG_FILE : string:="trace.txt"; -- Name of the trace file + ADDR_W : integer:=16; -- Address width + WORD_SIZE : integer:=32); -- 16/32 + port( + clk_i : in std_logic; + dbg_i : in zpu_dbgo_t; + stop_i : in std_logic; + busy_i : in std_logic + ); + end component Trace; + + component ZPUSmallCore is + generic( + WORD_SIZE : integer:=32; -- Data width 16/32 + ADDR_W : integer:=16; -- Total address space width (incl. I/O) + MEM_W : integer:=15; -- Memory (prog+data+stack) width + D_CARE_VAL : std_logic:='X'); -- Value used to fill the unsused bits + port( + clk_i : in std_logic; -- System Clock + reset_i : in std_logic; -- Synchronous Reset + interrupt_i : in std_logic; -- Interrupt + break_o : out std_logic; -- Breakpoint opcode executed + dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log) + -- BRAM (text, data, bss and stack) + a_we_o : out std_logic; -- BRAM A port Write Enable + a_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM A Address + a_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM A port + a_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM A port + b_we_o : out std_logic; -- BRAM B port Write Enable + b_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM B Address + b_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM B port + b_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM B port + -- Memory mapped I/O + mem_busy_i : in std_logic; + data_i : in unsigned(WORD_SIZE-1 downto 0); + data_o : out unsigned(WORD_SIZE-1 downto 0); + addr_o : out unsigned(ADDR_W-1 downto 0); + write_en_o : out std_logic; + read_en_o : out std_logic); + end component ZPUSmallCore; + + component ZPUMediumCore is + generic( + WORD_SIZE : integer:=32; -- Data width 16/32 + ADDR_W : integer:=16; -- Total address space width (incl. I/O) + MEM_W : integer:=15; -- Memory (prog+data+stack) width + D_CARE_VAL : std_logic:='X'; -- Value used to fill the unsused bits + MULT_PIPE : boolean:=false; -- Pipeline multiplication + BINOP_PIPE : integer range 0 to 2:=0; -- Pipeline binary operations (-, =, < and <=) + ENA_LEVEL0 : boolean:=true; -- eq, loadb, neqbranch and pushspadd + ENA_LEVEL1 : boolean:=true; -- lessthan, ulessthan, mult, storeb, callpcrel and sub + ENA_LEVEL2 : boolean:=false; -- lessthanorequal, ulessthanorequal, call and poppcrel + ENA_LSHR : boolean:=true; -- lshiftright + ENA_IDLE : boolean:=false; -- Enable the enable_i input + FAST_FETCH : boolean:=true); -- Merge the st_fetch with the st_execute states + port( + clk_i : in std_logic; -- CPU Clock + reset_i : in std_logic; -- Sync Reset + enable_i : in std_logic; -- Hold the CPU (after reset) + break_o : out std_logic; -- Break instruction executed + dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log) + -- Memory interface + mem_busy_i : in std_logic; -- Memory is busy + data_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from mem + data_o : out unsigned(WORD_SIZE-1 downto 0); -- Data to mem + addr_o : out unsigned(ADDR_W-1 downto 0); -- Memory address + write_en_o : out std_logic; -- Memory write enable + read_en_o : out std_logic); -- Memory read enable + end component ZPUMediumCore; + + component Timer is + port( + clk_i : in std_logic; + reset_i : in std_logic; + we_i : in std_logic; + data_i : in unsigned(31 downto 0); + addr_i : in unsigned(0 downto 0); + data_o : out unsigned(31 downto 0)); + end component Timer; + + component ZPUPhiIO is + generic( + BRDIVISOR : positive:=1; -- Baud rate divisor i.e. br_clk/9600/4 + ENA_LOG : boolean:=true; -- Enable log + LOG_FILE : string:="log.txt"); -- Name for the log file + port( + clk_i : in std_logic; -- System Clock + reset_i : in std_logic; -- Synchronous Reset + busy_o : out std_logic; -- I/O is busy + we_i : in std_logic; -- Write Enable + re_i : in std_logic; -- Read Enable + data_i : in unsigned(31 downto 0); + data_o : out unsigned(31 downto 0); + addr_i : in unsigned(2 downto 0); -- Address bits 4-2 + rs232_rx_i : in std_logic; -- UART Rx input + rs232_tx_o : out std_logic; -- UART Tx output + br_clk_i : in std_logic); -- UART base clock (enable) + end component ZPUPhiIO; + + -- Opcode decode constants + -- Note: these are the basic opcodes, always implemented using hardware. + constant OPCODE_IM : unsigned(7 downto 7):="1"; + constant OPCODE_STORESP : unsigned(7 downto 5):="010"; + constant OPCODE_LOADSP : unsigned(7 downto 5):="011"; + constant OPCODE_EMULATE : unsigned(7 downto 5):="001"; + constant OPCODE_ADDSP : unsigned(7 downto 4):="0001"; + constant OPCODE_SHORT : unsigned(7 downto 4):="0000"; + + constant OPCODE_BREAK : unsigned(3 downto 0):="0000"; + constant OPCODE_SHIFTLEFT : unsigned(3 downto 0):="0001"; + constant OPCODE_PUSHSP : unsigned(3 downto 0):="0010"; + constant OPCODE_PUSHINT : unsigned(3 downto 0):="0011"; + + constant OPCODE_POPPC : unsigned(3 downto 0):="0100"; + constant OPCODE_ADD : unsigned(3 downto 0):="0101"; + constant OPCODE_AND : unsigned(3 downto 0):="0110"; + constant OPCODE_OR : unsigned(3 downto 0):="0111"; + + constant OPCODE_LOAD : unsigned(3 downto 0):="1000"; + constant OPCODE_NOT : unsigned(3 downto 0):="1001"; + constant OPCODE_FLIP : unsigned(3 downto 0):="1010"; + constant OPCODE_NOP : unsigned(3 downto 0):="1011"; + + constant OPCODE_STORE : unsigned(3 downto 0):="1100"; + constant OPCODE_POPSP : unsigned(3 downto 0):="1101"; + constant OPCODE_COMPARE : unsigned(3 downto 0):="1110"; + constant OPCODE_POPINT : unsigned(3 downto 0):="1111"; + + -- The following instructions are emulated in the small version and + -- implemented as hardware in the full version. + -- The constants correpond to the "emulated" instruction number. + + -- Enabled by the ENA_LEVEL0 generic: + constant OPCODE_EQ : unsigned(5 downto 0):=to_unsigned(46,6); + constant OPCODE_LOADB : unsigned(5 downto 0):=to_unsigned(51,6); + constant OPCODE_NEQBRANCH : unsigned(5 downto 0):=to_unsigned(56,6); + constant OPCODE_PUSHSPADD : unsigned(5 downto 0):=to_unsigned(61,6); + -- Enabled by the ENA_LEVEL1 generic: + constant OPCODE_LESSTHAN : unsigned(5 downto 0):=to_unsigned(36,6); + constant OPCODE_ULESSTHAN : unsigned(5 downto 0):=to_unsigned(38,6); + constant OPCODE_MULT : unsigned(5 downto 0):=to_unsigned(41,6); + constant OPCODE_STOREB : unsigned(5 downto 0):=to_unsigned(52,6); + constant OPCODE_CALLPCREL : unsigned(5 downto 0):=to_unsigned(63,6); + constant OPCODE_SUB : unsigned(5 downto 0):=to_unsigned(49,6); + -- Enabled by the ENA_LEVEL2 generic: + constant OPCODE_LESSTHANOREQUAL : unsigned(5 downto 0):=to_unsigned(37,6); + constant OPCODE_ULESSTHANOREQUAL : unsigned(5 downto 0):=to_unsigned(39,6); + constant OPCODE_CALL : unsigned(5 downto 0):=to_unsigned(45,6); + constant OPCODE_POPPCREL : unsigned(5 downto 0):=to_unsigned(57,6); + -- Enabled by the ENA_LSHR generic: + constant OPCODE_LSHIFTRIGHT : unsigned(5 downto 0):=to_unsigned(42,6); + -- The following opcodes are always emulated. + constant OPCODE_LOADH : unsigned(5 downto 0):=to_unsigned(34,6); + constant OPCODE_STOREH : unsigned(5 downto 0):=to_unsigned(35,6); + constant OPCODE_ASHIFTLEFT : unsigned(5 downto 0):=to_unsigned(43,6); + constant OPCODE_ASHIFTRIGHT : unsigned(5 downto 0):=to_unsigned(44,6); + constant OPCODE_NEQ : unsigned(5 downto 0):=to_unsigned(47,6); + constant OPCODE_NEG : unsigned(5 downto 0):=to_unsigned(48,6); + constant OPCODE_XOR : unsigned(5 downto 0):=to_unsigned(50,6); + constant OPCODE_DIV : unsigned(5 downto 0):=to_unsigned(53,6); + constant OPCODE_MOD : unsigned(5 downto 0):=to_unsigned(54,6); + constant OPCODE_EQBRANCH : unsigned(5 downto 0):=to_unsigned(55,6); + constant OPCODE_CONFIG : unsigned(5 downto 0):=to_unsigned(58,6); + constant OPCODE_PUSHPC : unsigned(5 downto 0):=to_unsigned(59,6); +end package zpupkg; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +package UART is + ---------------------- + -- Very simple UART -- + ---------------------- + component RxUnit is + port( + clk_i : in std_logic; -- System clock signal + reset_i : in std_logic; -- Reset input (sync) + enable_i : in std_logic; -- Enable input (rate*4) + read_i : in std_logic; -- Received Byte Read + rxd_i : in std_logic; -- RS-232 data input + rxav_o : out std_logic; -- Byte available + datao_o : out std_logic_vector(7 downto 0)); -- Byte received + end component RxUnit; + + component TxUnit is + port ( + clk_i : in std_logic; -- Clock signal + reset_i : in std_logic; -- Reset input + enable_i : in std_logic; -- Enable input + load_i : in std_logic; -- Load input + txd_o : out std_logic; -- RS-232 data output + busy_o : out std_logic; -- Tx Busy + datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit + end component TxUnit; + + component BRGen is + generic( + COUNT : integer range 0 to 65535);-- Count revolution + port ( + clk_i : in std_logic; -- Clock + reset_i : in std_logic; -- Reset input + ce_i : in std_logic; -- Chip Enable + o_o : out std_logic); -- Output + end component BRGen; +end package UART; + diff --git a/zpu/hdl/zealot/zpu_small.vhdl b/zpu/hdl/zealot/zpu_small.vhdl new file mode 100644 index 0000000..7e022d4 --- /dev/null +++ b/zpu/hdl/zealot/zpu_small.vhdl @@ -0,0 +1,471 @@ +------------------------------------------------------------------------------ +---- ---- +---- ZPU Small ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- ZPU is a 32 bits small stack cpu. This is the small size version. ---- +---- It doesn't support external memories, needs a dual ported memory. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Øyvind Harboe, oyvind.harboe zylin.com ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Øyvind Harboe ---- +---- Copyright (c) 2008 Salvador E. Tropea ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the BSD license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: ZPUSmallCore(Behave) (Entity and architecture) ---- +---- File name: zpu_small.vhdl ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: zpu ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- zpu.zpupkg ---- +---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: GHDL [Sokcho edition] (0.2x) ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.ALL; +use IEEE.numeric_std.all; + +library zpu; +use zpu.zpupkg.all; + +entity ZPUSmallCore is + generic( + WORD_SIZE : integer:=32; -- Data width 16/32 + ADDR_W : integer:=16; -- Total address space width (incl. I/O) + MEM_W : integer:=15; -- Memory (prog+data+stack) width + D_CARE_VAL : std_logic:='X'); -- Value used to fill the unsused bits + port( + clk_i : in std_logic; -- System Clock + reset_i : in std_logic; -- Synchronous Reset + interrupt_i : in std_logic; -- Interrupt + break_o : out std_logic; -- Breakpoint opcode executed + dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log) + -- BRAM (text, data, bss and stack) + a_we_o : out std_logic; -- BRAM A port Write Enable + a_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM A Address + a_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM A port + a_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM A port + b_we_o : out std_logic; -- BRAM B port Write Enable + b_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM B Address + b_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM B port + b_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM B port + -- Memory mapped I/O + mem_busy_i : in std_logic; + data_i : in unsigned(WORD_SIZE-1 downto 0); + data_o : out unsigned(WORD_SIZE-1 downto 0); + addr_o : out unsigned(ADDR_W-1 downto 0); + write_en_o : out std_logic; + read_en_o : out std_logic); +end entity ZPUSmallCore; + +architecture Behave of ZPUSmallCore is + constant MAX_ADDR_BIT : integer:=ADDR_W-2; + constant BYTE_BITS : integer:=WORD_SIZE/16; -- # of bits in a word that addresses bytes + -- Stack Pointer initial value: BRAM size-8 + constant SP_START_1 : unsigned(ADDR_W-1 downto 0):=to_unsigned((2**MEM_W)-8,ADDR_W); + constant SP_START : unsigned(MAX_ADDR_BIT downto BYTE_BITS):= + SP_START_1(MAX_ADDR_BIT downto BYTE_BITS); + constant IO_BIT : integer:=ADDR_W-1; -- Address bit to determine this is an I/O + + -- Program counter + signal pc_r : unsigned(MAX_ADDR_BIT downto 0):=(others => '0'); + -- Stack pointer + signal sp_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=SP_START; + signal idim_r : std_logic:='0'; + + -- BRAM (text, data, bss and stack) + -- a_r is a register for the top of the stack [SP] + -- Note: as this is a stack CPU this is a very important register. + signal a_we_r : std_logic:='0'; + signal a_addr_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=(others => '0'); + signal a_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0'); + -- b_r is a register for the next value in the stack [SP+1] + -- We also use the B port to fetch instructions. + signal b_we_r : std_logic:='0'; + signal b_addr_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=(others => '0'); + signal b_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0'); + + -- State machine. + type state_t is (st_fetch, st_write_io_done, st_execute, st_add, st_or, + st_and, st_store, st_read_io, st_write_io, st_fetch_next, + st_add_sp, st_decode, st_resync); + signal state : state_t:=st_resync; + + -- Decoded Opcode + type decode_t is (dec_nop, dec_im, dec_load_sp, dec_store_sp, dec_add_sp, + dec_emulate, dec_break, dec_push_sp, dec_pop_pc, dec_add, + dec_or, dec_and, dec_load, dec_not, dec_flip, dec_store, + dec_pop_sp, dec_interrupt); + signal d_opcode_r : decode_t; + signal d_opcode : decode_t; + + signal opcode : unsigned(OPCODE_W-1 downto 0); -- Decoded + signal opcode_r : unsigned(OPCODE_W-1 downto 0); -- Registered + + -- IRQ flag + signal in_irq_r : std_logic:='0'; + -- I/O space address + signal addr_r : unsigned(ADDR_W-1 downto 0):=(others => '0'); +begin + -- Dual ported memory interface + a_we_o <= a_we_r; + a_addr_o <= a_addr_r(MEM_W-1 downto BYTE_BITS); + a_o <= a_r; + b_we_o <= b_we_r; + b_addr_o <= b_addr_r(MEM_W-1 downto BYTE_BITS); + b_o <= b_r; + + ------------------------- + -- Instruction Decoder -- + ------------------------- + -- Note: We use Port B memory to fetch the opcodes. + decode_control: + process(b_i, pc_r) + variable topcode : unsigned(OPCODE_W-1 downto 0); + begin + -- Select the addressed byte inside the fetched word + case (to_integer(pc_r(BYTE_BITS-1 downto 0))) is + when 0 => + topcode:=b_i(31 downto 24); + when 1 => + topcode:=b_i(23 downto 16); + when 2 => + topcode:=b_i(15 downto 8); + when others => -- 3 + topcode:=b_i(7 downto 0); + end case; + opcode <= topcode; + + if (topcode(7 downto 7)=OPCODE_IM) then + d_opcode <= dec_im; + elsif (topcode(7 downto 5)=OPCODE_STORESP) then + d_opcode <= dec_store_sp; + elsif (topcode(7 downto 5)=OPCODE_LOADSP) then + d_opcode <= dec_load_sp; + elsif (topcode(7 downto 5)=OPCODE_EMULATE) then + d_opcode <= dec_emulate; + elsif (topcode(7 downto 4)=OPCODE_ADDSP) then + d_opcode <= dec_add_sp; + else -- OPCODE_SHORT + case topcode(3 downto 0) is + when OPCODE_BREAK => + d_opcode <= dec_break; + when OPCODE_PUSHSP => + d_opcode <= dec_push_sp; + when OPCODE_POPPC => + d_opcode <= dec_pop_pc; + when OPCODE_ADD => + d_opcode <= dec_add; + when OPCODE_OR => + d_opcode <= dec_or; + when OPCODE_AND => + d_opcode <= dec_and; + when OPCODE_LOAD => + d_opcode <= dec_load; + when OPCODE_NOT => + d_opcode <= dec_not; + when OPCODE_FLIP => + d_opcode <= dec_flip; + when OPCODE_STORE => + d_opcode <= dec_store; + when OPCODE_POPSP => + d_opcode <= dec_pop_sp; + when others => -- OPCODE_NOP and others + d_opcode <= dec_nop; + end case; + end if; + end process decode_control; + + data_o <= b_i; + opcode_control: + process (clk_i) + variable sp_offset : unsigned(4 downto 0); + begin + if rising_edge(clk_i) then + break_o <= '0'; + write_en_o <= '0'; + read_en_o <= '0'; + dbg_o.b_inst <= '0'; + if reset_i='1' then + state <= st_resync; + sp_r <= SP_START; + pc_r <= (others => '0'); + idim_r <= '0'; + a_addr_r <= (others => '0'); + b_addr_r <= (others => '0'); + a_we_r <= '0'; + b_we_r <= '0'; + a_r <= (others => '0'); + b_r <= (others => '0'); + in_irq_r <= '0'; + addr_r <= (others => '0'); + else -- reset_i/='1' + a_we_r <= '0'; + b_we_r <= '0'; + -- This saves LUTs, by explicitly declaring that the + -- a_o can be left at whatever value if a_we_r is + -- not set. + a_r <= (others => D_CARE_VAL); + b_r <= (others => D_CARE_VAL); + sp_offset:=(others => D_CARE_VAL); + a_addr_r <= (others => D_CARE_VAL); + b_addr_r <= (others => D_CARE_VAL); + addr_r <= a_i(ADDR_W-1 downto 0); + d_opcode_r <= d_opcode; + opcode_r <= opcode; + if interrupt_i='0' then + in_irq_r <= '0'; -- no longer in an interrupt + end if; + + case state is + when st_execute => + state <= st_fetch; + -- At this point: + -- b_i contains opcode word + -- a_i contains top of stack + pc_r <= pc_r+1; + + -- Debug info (Trace) + dbg_o.b_inst <= '1'; + dbg_o.pc <= (others => '0'); + dbg_o.pc(MAX_ADDR_BIT downto 0) <= pc_r; + dbg_o.opcode <= opcode_r; + dbg_o.sp <= (others => '0'); + dbg_o.sp(MAX_ADDR_BIT downto BYTE_BITS) <= sp_r; + dbg_o.stk_a <= a_i; + dbg_o.stk_b <= b_i; + + -- During the next cycle we'll be reading the next opcode + sp_offset(4):=not opcode_r(4); + sp_offset(3 downto 0):=opcode_r(3 downto 0); + + idim_r <= '0'; + + -------------------- + -- Execution Unit -- + -------------------- + case d_opcode_r is + when dec_interrupt => + -- Not a real instruction, but an interrupt + -- Push(PC); PC=32 + sp_r <= sp_r-1; + a_addr_r <= sp_r-1; + a_we_r <= '1'; + a_r <= (others => D_CARE_VAL); + a_r(MAX_ADDR_BIT downto 0) <= pc_r; + -- Jump to ISR + pc_r <= to_unsigned(32,MAX_ADDR_BIT+1); -- interrupt address + --report "ZPU jumped to interrupt!" severity note; + when dec_im => + idim_r <= '1'; + a_we_r <= '1'; + if idim_r='0' then + -- First IM + -- Push the 7 bits (extending the sign) + sp_r <= sp_r-1; + a_addr_r <= sp_r-1; + a_r <= unsigned(resize(signed(opcode_r(6 downto 0)),WORD_SIZE)); + else + -- Next IMs, shift the word and put the new value in the lower + -- bits + a_addr_r <= sp_r; + a_r(WORD_SIZE-1 downto 7) <= a_i(WORD_SIZE-8 downto 0); + a_r(6 downto 0) <= opcode_r(6 downto 0); + end if; + when dec_store_sp => + -- [SP+Offset]=Pop() + b_we_r <= '1'; + b_addr_r <= sp_r+sp_offset; + b_r <= a_i; + sp_r <= sp_r+1; + state <= st_resync; + when dec_load_sp => + -- Push([SP+Offset]) + sp_r <= sp_r-1; + a_addr_r <= sp_r+sp_offset; + when dec_emulate => + -- Push(PC+1), PC=Opcode[4:0]*32 + sp_r <= sp_r-1; + a_we_r <= '1'; + a_addr_r <= sp_r-1; + a_r <= (others => D_CARE_VAL); + a_r(MAX_ADDR_BIT downto 0) <= pc_r+1; + -- Jump to NUM*32 + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc_r <= (others => '0'); + pc_r(9 downto 5) <= opcode_r(4 downto 0); + when dec_add_sp => + -- Push(Pop()+[SP+Offset]) + a_addr_r <= sp_r; + b_addr_r <= sp_r+sp_offset; + state <= st_add_sp; + when dec_break => + --report "Break instruction encountered" severity failure; + break_o <= '1'; + when dec_push_sp => + -- Push(SP) + sp_r <= sp_r-1; + a_we_r <= '1'; + a_addr_r <= sp_r-1; + a_r <= (others => D_CARE_VAL); + a_r(MAX_ADDR_BIT downto BYTE_BITS) <= sp_r; + when dec_pop_pc => + -- Pop(PC) + pc_r <= a_i(MAX_ADDR_BIT downto 0); + sp_r <= sp_r+1; + state <= st_resync; + when dec_add => + -- Push(Pop()+Pop()) + sp_r <= sp_r+1; + state <= st_add; + when dec_or => + -- Push(Pop() or Pop()) + sp_r <= sp_r+1; + state <= st_or; + when dec_and => + -- Push(Pop() and Pop()) + sp_r <= sp_r+1; + state <= st_and; + when dec_load => + -- Push([Pop()]) + if a_i(IO_BIT)='1' then + addr_r <= a_i(ADDR_W-1 downto 0); + read_en_o <= '1'; + state <= st_read_io; + else + a_addr_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS); + end if; + when dec_not => + -- Push(not(Pop())) + a_addr_r <= sp_r(MAX_ADDR_BIT downto BYTE_BITS); + a_we_r <= '1'; + a_r <= not a_i; + when dec_flip => + -- Push(flip(Pop())) + a_addr_r <= sp_r(MAX_ADDR_BIT downto BYTE_BITS); + a_we_r <= '1'; + for i in 0 to WORD_SIZE-1 loop + a_r(i) <= a_i(WORD_SIZE-1-i); + end loop; + when dec_store => + -- a=Pop(), b=Pop(), [a]=b + b_addr_r <= sp_r+1; + sp_r <= sp_r+1; + if a_i(IO_BIT)='1' then + state <= st_write_io; + else + state <= st_store; + end if; + when dec_pop_sp => + -- SP=Pop() + sp_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS); + state <= st_resync; + when dec_nop => + -- Default, keep addressing to of the stack (A) + a_addr_r <= sp_r; + when others => + null; + end case; + when st_read_io => + -- Wait until memory I/O isn't busy + if mem_busy_i='0' then + state <= st_fetch; + a_we_r <= '1'; + a_r <= data_i; + end if; + when st_write_io => + -- [A]=B + sp_r <= sp_r+1; + write_en_o <= '1'; + addr_r <= a_i(ADDR_W-1 downto 0); + state <= st_write_io_done; + when st_write_io_done => + -- Wait until memory I/O isn't busy + if mem_busy_i='0' then + state <= st_resync; + end if; + when st_fetch => + -- We need to resync. During the *next* cycle + -- we'll fetch the opcode @ pc and thus it will + -- be available for st_execute the cycle after + -- next + b_addr_r <= pc_r(MAX_ADDR_BIT downto BYTE_BITS); + state <= st_fetch_next; + when st_fetch_next => + -- At this point a_i contains the value that is either + -- from the top of stack or should be copied to the top of the stack + a_we_r <= '1'; + a_r <= a_i; + a_addr_r <= sp_r; + b_addr_r <= sp_r+1; + state <= st_decode; + when st_decode => + if interrupt_i='1' and in_irq_r='0' and idim_r='0' then + -- We got an interrupt, execute interrupt instead of next instruction + in_irq_r <= '1'; + d_opcode_r <= dec_interrupt; + end if; + -- during the st_execute cycle we'll be fetching SP+1 + a_addr_r <= sp_r; + b_addr_r <= sp_r+1; + state <= st_execute; + when st_store => + sp_r <= sp_r+1; + a_we_r <= '1'; + a_addr_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS); + a_r <= b_i; + state <= st_resync; + when st_add_sp => + state <= st_add; + when st_add => + a_addr_r <= sp_r; + a_we_r <= '1'; + a_r <= a_i+b_i; + state <= st_fetch; + when st_or => + a_addr_r <= sp_r; + a_we_r <= '1'; + a_r <= a_i or b_i; + state <= st_fetch; + when st_and => + a_addr_r <= sp_r; + a_we_r <= '1'; + a_r <= a_i and b_i; + state <= st_fetch; + when st_resync => + a_addr_r <= sp_r; + state <= st_fetch; + when others => + null; + end case; + end if; -- else reset_i/='1' + end if; -- rising_edge(clk_i) + end process opcode_control; + addr_o <= addr_r; + +end architecture Behave; -- Entity: ZPUSmallCore + -- cgit v1.1