From 26806927a9e6985fdc508c703c3525e5aedf3a23 Mon Sep 17 00:00:00 2001 From: oharboe Date: Wed, 17 Dec 2008 22:09:07 +0000 Subject: register stack wip --- zpu/docs/zpu_arch.html | 56 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index 5cf7410..9b69660 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -33,6 +33,7 @@ $id$
  • Next generation ZPU +
  • Register stack ZPU @@ -2090,5 +2091,60 @@ as an uncompressed .txt file

    Getting help - mailing list

    The place to get help is the     zylin-zpu mailing list + +

    Register stack

    +In order to reduce the size and complexity of the small ZPU, a register stack +has been put forward. It remains an open question as to whether this can +indeed reduce size and improve performance of the ZPU. +

    +Terminology: "stack" is the normal stack in memory pointed to +by the sp register. "register stack" is a different stack that is +not connected to memory directly or associated with the "stack". +

    +The idea is to push and pop the register stack such that bandwidth +is increased and complexity of memory access logic is reduced. +

    +Another clever bit is to mask interrupts while this stack is +not empty such that this stack never has to be +saved. It's depth would be fixed to something natural +for an FPGA, say 16 deep(doesn't that translate to a single +LUT for a bit?). + +

    Example of internal stack

    +im 1 ; push onto register stack
    +loadsp N ; load from memory pointed to by sp+N, push onto register stack
    +add ; pop values from register stack and add, push onto register stack
    + +

    Quick summary of instruction operation with register stack

    +This is not a "formal" definition of the instruction set, but should +give a pretty good idea of what the modified instruction looks like. +

    +Read up on the current definition of instructions and consider the +list below a guide to what changes have been made to fit a register +stack. The list is not complete, but covers the important categories +of instructions. If it is clear how the ADD instruction changed, +then it should be obvious how the AND isntruction must be similarly +modified. +

    +Note also that there are lots of tiny problems that have to be ironed +out before the instruction set and emulation can work. Below is just +a first stab, which hopefully is good enough to evaluate the approach. + + + + + + + + + + + + + + +
    IM push onto/modify top of register stack
    STORESP pop register stack store to memory SP+N
    LOADSP load memory SP+N push onto register stack
    EMULATE push PC+1 onto register stack and jump to EMULATE vector
    PUSHPC push pc onto register stack
    POPPC pop pc from register stack
    LOAD pop address from register stack, load from memory address, push onto register stack
    STORE pop register stack 2x store value to memory
    PUSHSP push sp onto register stack
    POPSP pop sp from register stack
    POPPC pop pc from register stack
    ADD pop 2x register stack, add, push to register stack
    NOT pop register stack, bit inverse value, push onto register stack
    +Emulate instructions and calling convention may have to change substantially. + \ No newline at end of file -- cgit v1.1