From 125ac6401ae856b57deac3c719d67c8ca2b1426e Mon Sep 17 00:00:00 2001 From: oharboe Date: Tue, 23 Sep 2008 10:40:48 +0000 Subject: =?UTF-8?q?=20=C1lvaro=20Lopes=20SPI=20flash?= =?UTF-8?q?=20controller=20documentation?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- zpu/docs/images/spi_read_timing.png | Bin 0 -> 12075 bytes zpu/docs/images/spi_readfast_timing.png | Bin 0 -> 7745 bytes zpu/docs/images/spi_timing_overview.png | Bin 0 -> 10241 bytes zpu/docs/zpu_arch.html | 78 ++++++++++++++++++++++++++++++++ 4 files changed, 78 insertions(+) create mode 100644 zpu/docs/images/spi_read_timing.png create mode 100644 zpu/docs/images/spi_readfast_timing.png create mode 100644 zpu/docs/images/spi_timing_overview.png diff --git a/zpu/docs/images/spi_read_timing.png b/zpu/docs/images/spi_read_timing.png new file mode 100644 index 0000000..f412562 Binary files /dev/null and b/zpu/docs/images/spi_read_timing.png differ diff --git a/zpu/docs/images/spi_readfast_timing.png b/zpu/docs/images/spi_readfast_timing.png new file mode 100644 index 0000000..3cd2e35 Binary files /dev/null and b/zpu/docs/images/spi_readfast_timing.png differ diff --git a/zpu/docs/images/spi_timing_overview.png b/zpu/docs/images/spi_timing_overview.png new file mode 100644 index 0000000..1e42156 Binary files /dev/null and b/zpu/docs/images/spi_timing_overview.png differ diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index 6339031..e7cf30c 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -28,6 +28,7 @@ $id$
  • Zealot: Implementing in FPGAs
  • Optimizing for code size
  • Installing eCos build tools +
  • SPI flash controller
  • Next generation ZPU @@ -1618,6 +1619,83 @@ zpu-elf-gcc -Os -zeta hello.c -o hello.elf -Wl,--relax -Wl,--gc-sections
    zpu-elf-size hello.elf
    + + + +

    SPI flash controller (read-only)

    +This is a simple read-only SPI flash controller, with the following characteristics: + +
    +
  • Fast-READ only implementation. +
  • 32-bit only access +
  • Fast sequential read access - Uses low-clock approach
    • +
    + +

    Version

    +The current version is 1.2. This is also the first public version available. + +

    Timing overview

    + +

    Simple timing overview, with one nonsequential access to address 0x0, followed by a sequential access to address 0x4. +This simulation was done with Xilinx tools, after post-routing, and using a ZPU to access the SPI

    +
    + + +

    Image 1: Timing overview

    +
    + +On Image 2, you can see the clock almost perfectly centered on data, when we write to the SPI flash. + +
    + +

    Image 2: Issuing commands to the SPI

    +
    + +As you can see from Image 3, I assume the worst-case read delay from SPI (which is 15ns, as you can see from the marker). + +
    + +

    Image 3: Reading from the SPI

    +
    + +

    Usage

    + +Simple description of SPI controller interface: + + + + + + + + + + + + + + + + + + +
    SymbolDirectionBit widthPurpose
    adrInput24Address where to read from SPI
    dat_oOutput32Data read from SPI
    clkInput1Input clock. Used for both interface and SPI
    ceInput1Chip Enable
    rstInput1Asynchronous reset
    ackOutput1Data valid ACK
    SPI_CLKOutput1SPI output clock
    SPI_MOSIOutput1SPI output data from controller to chip
    SPI_MISOInput1SPI input data from chip to controller
    SPI_SELNOutput1SPI nSEL (deselect, active low) signal
    + + + +

    License

    +The Verilog implementation is released under BSD license. See the file itself for more licensing details. + +

    Dowload

    +Download the Verilog code here: spi_controller.v + +

    Troubleshooting

    +The current implementation is timed and optimized for myself. Your parameters might not be the same +as those I defaulted, so read the code carefully. If you have any issue let me know. + + + +

    Zealot: Implementing in FPGAs

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