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-rw-r--r--zpu/.cvsignore1
-rw-r--r--zpu/.project11
-rw-r--r--zpu/COPYING16
-rw-r--r--zpu/ChangeLog90
-rw-r--r--zpu/STATUS11
-rw-r--r--zpu/docs/images/GCC_logo.pngbin0 -> 23450 bytes
-rw-r--r--zpu/docs/images/codesize1.PNGbin0 -> 9329 bytes
-rw-r--r--zpu/docs/images/codesize2.PNGbin0 -> 16967 bytes
-rw-r--r--zpu/docs/images/compile.PNGbin0 -> 17735 bytes
-rw-r--r--zpu/docs/images/ecos.gifbin0 -> 1660 bytes
-rw-r--r--zpu/docs/images/elizadebug1.PNGbin0 -> 72126 bytes
-rw-r--r--zpu/docs/images/elizadebug2.PNGbin0 -> 67822 bytes
-rw-r--r--zpu/docs/images/gccgdb.PNGbin0 -> 34473 bytes
-rw-r--r--zpu/docs/images/simulator.PNGbin0 -> 42848 bytes
-rw-r--r--zpu/docs/images/simulator2.PNGbin0 -> 42623 bytes
-rw-r--r--zpu/docs/images/simulator3.PNGbin0 -> 69583 bytes
-rw-r--r--zpu/docs/images/spi_read_timing.pngbin0 -> 12075 bytes
-rw-r--r--zpu/docs/images/spi_readfast_timing.pngbin0 -> 7745 bytes
-rw-r--r--zpu/docs/images/spi_timing_overview.pngbin0 -> 10241 bytes
-rw-r--r--zpu/docs/images/zpusim.PNGbin0 -> 17817 bytes
-rw-r--r--zpu/docs/presentations/zpu.odpbin0 -> 60715 bytes
-rw-r--r--zpu/docs/presentations/zpu.pdfbin0 -> 112765 bytes
-rw-r--r--zpu/docs/presentations/zpudemo.odpbin0 -> 222644 bytes
-rw-r--r--zpu/docs/presentations/zpudemo.pdfbin0 -> 254156 bytes
-rw-r--r--zpu/docs/zpu_arch.html2443
-rw-r--r--zpu/hdl/avalanche/core/zpu_core.v749
-rw-r--r--zpu/hdl/avalanche/core/zpu_core_defines.v322
-rw-r--r--zpu/hdl/avalanche/core/zpu_core_rom.v1017
-rw-r--r--zpu/hdl/avalanche/readme.txt91
-rw-r--r--zpu/hdl/example/.cvsignore3
-rw-r--r--zpu/hdl/example/bram_dmips.vhd3356
-rw-r--r--zpu/hdl/example/helloworld.vhd3154
-rw-r--r--zpu/hdl/example/interrupt.vhd3156
-rw-r--r--zpu/hdl/example/log.txt20
-rw-r--r--zpu/hdl/example/sim_small_fpga_top.vhd197
-rw-r--r--zpu/hdl/example/sim_small_fpga_top_noint.vhd184
-rw-r--r--zpu/hdl/example/simzpu_dmips.do29
-rw-r--r--zpu/hdl/example/simzpu_interrupt.do29
-rw-r--r--zpu/hdl/example/simzpu_small.do29
-rw-r--r--zpu/hdl/example/zpu_config.vhd55
-rw-r--r--zpu/hdl/example/zpuromgen.c59
-rw-r--r--zpu/hdl/example/zpuromgen.exebin0 -> 10274 bytes
-rw-r--r--zpu/hdl/example_ghdl/README44
-rw-r--r--zpu/hdl/example_ghdl/dmipssmalltrace_ghdl.sh24
-rw-r--r--zpu/hdl/example_ghdl/dmipstrace_ghdl.sh24
-rw-r--r--zpu/hdl/example_ghdl/ghdl_import.sh16
-rw-r--r--zpu/hdl/example_ghdl/ghdl_make.sh4
-rw-r--r--zpu/hdl/example_ghdl/ghdl_options.sh2
-rw-r--r--zpu/hdl/example_ghdl/simzpu_medium_ghdl.sh24
-rw-r--r--zpu/hdl/example_medium/.cvsignore4
-rw-r--r--zpu/hdl/example_medium/dram_dmips.vhd3308
-rw-r--r--zpu/hdl/example_medium/dram_hello.vhd3107
-rw-r--r--zpu/hdl/example_medium/sim_fpga_top.vhd194
-rw-r--r--zpu/hdl/example_medium/simzpu_medium.do28
-rw-r--r--zpu/hdl/example_medium/zpu_config_trace.vhd17
-rw-r--r--zpu/hdl/sim/dmipssmalltrace.do26
-rw-r--r--zpu/hdl/sim/dmipstrace.do30
-rw-r--r--zpu/hdl/spi/spi_controller.v235
-rw-r--r--zpu/hdl/wishbone/wishbone_pkg.vhd86
-rw-r--r--zpu/hdl/wishbone/zpu_system.vhd104
-rw-r--r--zpu/hdl/wishbone/zpu_wb_bridge.vhd83
-rw-r--r--zpu/hdl/zealot/0README.txt195
-rw-r--r--zpu/hdl/zealot/BSD20
-rw-r--r--zpu/hdl/zealot/GPL_V2341
-rw-r--r--zpu/hdl/zealot/devices/br_gen.vhdl91
-rw-r--r--zpu/hdl/zealot/devices/gpio.vhdl107
-rw-r--r--zpu/hdl/zealot/devices/phi_io.vhdl257
-rw-r--r--zpu/hdl/zealot/devices/rx_unit.vhdl108
-rw-r--r--zpu/hdl/zealot/devices/timer.vhdl91
-rw-r--r--zpu/hdl/zealot/devices/trace.vhdl258
-rw-r--r--zpu/hdl/zealot/devices/tx_unit.vhdl109
-rw-r--r--zpu/hdl/zealot/devices/txt_util.vhdl541
-rwxr-xr-xzpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/clean_up.sh16
-rwxr-xr-xzpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation.sh49
-rw-r--r--zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/run.do2
-rw-r--r--zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/wave.do30
-rwxr-xr-xzpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis.sh36
-rw-r--r--zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/altium-livedesign-xc3s1000.ucf397
-rw-r--r--zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.prj19
-rw-r--r--zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.ut29
-rw-r--r--zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.xst56
-rw-r--r--zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top.vhd372
-rw-r--r--zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top_tb.vhd194
-rwxr-xr-xzpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/clean_up.sh16
-rwxr-xr-xzpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation.sh49
-rw-r--r--zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/run.do2
-rw-r--r--zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/wave.do30
-rwxr-xr-xzpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis.sh36
-rw-r--r--zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/avnet-eval-xc5vfx30t.ucf482
-rw-r--r--zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj19
-rw-r--r--zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.ut39
-rw-r--r--zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.xst60
-rw-r--r--zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd444
-rw-r--r--zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top_tb.vhd271
-rwxr-xr-xzpu/hdl/zealot/fpga/digilent-starter-xc3s500e/clean_up.sh16
-rwxr-xr-xzpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation.sh49
-rw-r--r--zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/run.do2
-rw-r--r--zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/wave.do30
-rwxr-xr-xzpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis.sh36
-rw-r--r--zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/digilent-starter-xc3s500e.ucf356
-rw-r--r--zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj19
-rw-r--r--zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut22
-rw-r--r--zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.xst56
-rw-r--r--zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top.vhd464
-rw-r--r--zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top_tb.vhd281
-rw-r--r--zpu/hdl/zealot/fpga/dmips_med1.vhdl119
-rw-r--r--zpu/hdl/zealot/fpga/dmips_small1.vhdl120
-rw-r--r--zpu/hdl/zealot/fpga/hello_med1.vhdl119
-rw-r--r--zpu/hdl/zealot/fpga/hello_small1.vhdl120
-rwxr-xr-xzpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/clean_up.sh16
-rwxr-xr-xzpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation.sh49
-rw-r--r--zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/run.do2
-rw-r--r--zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/wave.do163
-rwxr-xr-xzpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis.sh36
-rw-r--r--zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.prj19
-rw-r--r--zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.ut30
-rw-r--r--zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.xst53
-rw-r--r--zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/xilinx-sp601-xc6slx16.ucf303
-rw-r--r--zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top.vhd574
-rw-r--r--zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top_tb.vhd402
-rw-r--r--zpu/hdl/zealot/helpers/zpu_med1.vhdl187
-rw-r--r--zpu/hdl/zealot/helpers/zpu_small1.vhdl153
-rw-r--r--zpu/hdl/zealot/roms/dmips_bram.vhdl4462
-rw-r--r--zpu/hdl/zealot/roms/dmips_dbram.vhdl4485
-rw-r--r--zpu/hdl/zealot/roms/hello_bram.vhdl3056
-rw-r--r--zpu/hdl/zealot/roms/hello_dbram.vhdl3035
-rw-r--r--zpu/hdl/zealot/roms/rom_pkg.vhdl80
-rw-r--r--zpu/hdl/zealot/testbenches/dmips_med1_tb.vhdl134
-rw-r--r--zpu/hdl/zealot/testbenches/small1_tb.vhdl134
-rw-r--r--zpu/hdl/zealot/zpu_medium.vhdl948
-rw-r--r--zpu/hdl/zealot/zpu_pkg.vhdl292
-rw-r--r--zpu/hdl/zealot/zpu_small.vhdl472
-rw-r--r--zpu/hdl/zpu4/core/histogram.perl218
-rw-r--r--zpu/hdl/zpu4/core/zpu_config.vhd58
-rw-r--r--zpu/hdl/zpu4/core/zpu_core.vhd1014
-rw-r--r--zpu/hdl/zpu4/core/zpu_core_small.vhd602
-rw-r--r--zpu/hdl/zpu4/core/zpupkg.vhd218
-rw-r--r--zpu/hdl/zpu4/src/.cvsignore5
-rw-r--r--zpu/hdl/zpu4/src/clocks.vhd198
-rw-r--r--zpu/hdl/zpu4/src/io.vhd119
-rw-r--r--zpu/hdl/zpu4/src/timer.vhd61
-rw-r--r--zpu/hdl/zpu4/src/trace.vhd107
-rw-r--r--zpu/hdl/zpu4/src/txt_util.vhd539
-rw-r--r--zpu/hdl/zpu4/src/zpuio.vhd218
-rwxr-xr-xzpu/hdl/zpu4/test/dmips/build.sh4
-rw-r--r--zpu/hdl/zpu4/test/dmips/dmips.binbin0 -> 13028 bytes
-rw-r--r--zpu/hdl/zpu4/test/dmips/dmips.elfbin0 -> 82460 bytes
-rw-r--r--zpu/hdl/zpu4/test/dmips/dmips.ram3256
-rwxr-xr-xzpu/hdl/zpu4/test/gpiotest/build.sh4
-rw-r--r--zpu/hdl/zpu4/test/gpiotest/gpiotest.c72
-rwxr-xr-xzpu/hdl/zpu4/test/hello/build.sh4
-rw-r--r--zpu/hdl/zpu4/test/hello/hello.binbin0 -> 12224 bytes
-rw-r--r--zpu/hdl/zpu4/test/hello/hello.c47
-rw-r--r--zpu/hdl/zpu4/test/hello/hello.elfbin0 -> 150384 bytes
-rw-r--r--zpu/hdl/zpu4/test/hello/hello.ram3055
-rwxr-xr-xzpu/hdl/zpu4/test/interrupt/build.sh4
-rw-r--r--zpu/hdl/zpu4/test/interrupt/int.binbin0 -> 12232 bytes
-rw-r--r--zpu/hdl/zpu4/test/interrupt/int.c40
-rw-r--r--zpu/hdl/zpu4/test/interrupt/int.elfbin0 -> 150458 bytes
-rw-r--r--zpu/hdl/zpu4/test/interrupt/int.ram3057
-rw-r--r--zpu/hdl/zy2000/timer.vhd137
-rw-r--r--zpu/hdl/zy2000/trace.vhd84
-rw-r--r--zpu/hdl/zy2000/txt_util.vhd587
-rw-r--r--zpu/hdl/zy2000/zpu_config.vhd20
-rw-r--r--zpu/hdl/zy2000/zpu_config_fast.vhd20
-rw-r--r--zpu/hdl/zy2000/zpu_core.vhd948
-rw-r--r--zpu/hdl/zy2000/zpupkg.vhd168
-rw-r--r--zpu/roadshow/roadshow/build/makefirmware.sh13
-rw-r--r--zpu/roadshow/roadshow/codesize/.cvsignore1
-rw-r--r--zpu/roadshow/roadshow/codesize/crt0_phi.S178
-rw-r--r--zpu/roadshow/roadshow/codesize/hello.c9
-rw-r--r--zpu/roadshow/roadshow/codesize/small.c9
-rw-r--r--zpu/roadshow/roadshow/codesize/small.elfbin0 -> 1577 bytes
-rw-r--r--zpu/roadshow/roadshow/codesize/smallstd.c9
-rw-r--r--zpu/roadshow/roadshow/dhrystone/.cvsignore2
-rw-r--r--zpu/roadshow/roadshow/dhrystone/RATIONALE361
-rw-r--r--zpu/roadshow/roadshow/dhrystone/README_C78
-rw-r--r--zpu/roadshow/roadshow/dhrystone/VARIATIONS157
-rw-r--r--zpu/roadshow/roadshow/dhrystone/build.sh7
-rw-r--r--zpu/roadshow/roadshow/dhrystone/dhry-c1779
-rw-r--r--zpu/roadshow/roadshow/dhrystone/dhry.h423
-rw-r--r--zpu/roadshow/roadshow/dhrystone/dhry_1.c533
-rw-r--r--zpu/roadshow/roadshow/dhrystone/dhry_2.c192
-rw-r--r--zpu/roadshow/roadshow/dhrystone/dhry_c.dif141
-rw-r--r--zpu/roadshow/roadshow/dhrystone/dhrystone.binbin0 -> 13028 bytes
-rw-r--r--zpu/roadshow/roadshow/dhrystone/dhrystone.zpubin0 -> 13069 bytes
-rw-r--r--zpu/roadshow/roadshow/dhrystone/submit.frm17
-rw-r--r--zpu/roadshow/roadshow/ecos/codesize/zpuarmcodesize.htm1049
-rw-r--r--zpu/roadshow/roadshow/ecos/repository.tar.bz2bin0 -> 28572 bytes
-rw-r--r--zpu/roadshow/roadshow/games/.cvsignore5
-rw-r--r--zpu/roadshow/roadshow/games/build.sh7
-rw-r--r--zpu/roadshow/roadshow/games/eliza.binbin0 -> 46920 bytes
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-rw-r--r--zpu/roadshow/roadshow/games/eliza.zpubin0 -> 46961 bytes
-rw-r--r--zpu/roadshow/roadshow/games/eliza/eliza.c269
-rw-r--r--zpu/roadshow/roadshow/games/eliza/parse.c719
-rw-r--r--zpu/roadshow/roadshow/games/eliza/parse.h33
-rw-r--r--zpu/roadshow/roadshow/games/eliza/response.c365
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-rw-r--r--zpu/roadshow/roadshow/games/sumeria.binbin0 -> 42324 bytes
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-rw-r--r--zpu/roadshow/roadshow/helloworld/build.sh6
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-rw-r--r--zpu/sw/ecos/repository/hal/zylin/arch/current/src/hal_mk_defs.c102
-rw-r--r--zpu/sw/ecos/repository/hal/zylin/arch/current/src/vectors.c116
-rw-r--r--zpu/sw/ecos/repository/hal/zylin/arch/current/src/zylin.ld226
-rw-r--r--zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/ChangeLog39
-rw-r--r--zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/cdl/hal_zylin_zpu_abel.cdl298
-rw-r--r--zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/hal_platform_ints.h79
-rw-r--r--zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/pkgconf/mlt_zylin_zpu_abel_ram.h17
-rw-r--r--zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/pkgconf/mlt_zylin_zpu_abel_ram.ldi27
-rw-r--r--zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/plf_io.h64
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-rw-r--r--zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/ChangeLog39
-rw-r--r--zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/cdl/hal_zylin_zpu_phi.cdl292
-rw-r--r--zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/hal_platform_ints.h81
-rw-r--r--zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/pkgconf/mlt_zylin_zpu_phi_ram.h17
-rw-r--r--zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/pkgconf/mlt_zylin_zpu_phi_ram.ldi27
-rw-r--r--zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/plf_io.h58
-rw-r--r--zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/src/phi_misc.c72
-rw-r--r--zpu/sw/ecos/repository/hal/zylin/zpu/var/current/ChangeLog38
-rw-r--r--zpu/sw/ecos/repository/hal/zylin/zpu/var/current/cdl/hal_zylin_zpu.cdl83
-rw-r--r--zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/hal_cache.h192
-rw-r--r--zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/hal_diag.h90
-rw-r--r--zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/plf_stub.h85
-rw-r--r--zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/var_arch.h73
-rw-r--r--zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/var_io.h73
-rw-r--r--zpu/sw/ecos/repository/hal/zylin/zpu/var/current/src/hal_diag.c88
-rw-r--r--zpu/sw/ecos/repository/hal/zylin/zpu/var/current/src/zpu_misc.c252
-rw-r--r--zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/ChangeLog39
-rw-r--r--zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/cdl/hal_zylin_zpu_zeta.cdl298
-rw-r--r--zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/hal_platform_ints.h79
-rw-r--r--zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/pkgconf/mlt_zylin_zpu_zeta_ram.h17
-rw-r--r--zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/pkgconf/mlt_zylin_zpu_zeta_ram.ldi27
-rw-r--r--zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/plf_io.h58
-rw-r--r--zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/misc/redboot_RAM.ecm53
-rw-r--r--zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/src/zeta_misc.c64
-rw-r--r--zpu/sw/ecos/repository/net/zylin/current/cdl/phi_net.cdl56
-rw-r--r--zpu/sw/ecos/repository/net/zylin/current/src/phi_network_support.c368
-rw-r--r--zpu/sw/ecos/repository/pkgconf/rules.mak210
-rw-r--r--zpu/sw/env.sh2
-rw-r--r--zpu/sw/freertos/port/port.c271
-rw-r--r--zpu/sw/freertos/port/portasm.s142
-rw-r--r--zpu/sw/freertos/port/portmacro.h125
-rw-r--r--zpu/sw/freertos/readme.txt40
-rw-r--r--zpu/sw/freertos/sample/FreeRTOSConfig.h96
-rw-r--r--zpu/sw/freertos/sample/Makefile50
-rw-r--r--zpu/sw/freertos/sample/test1.c67
-rw-r--r--zpu/sw/helloworld/gmon.outbin0 -> 120053 bytes
-rw-r--r--zpu/sw/helloworld/hello.binbin0 -> 49768 bytes
-rw-r--r--zpu/sw/helloworld/hello.bram12441
-rw-r--r--zpu/sw/helloworld/hello.c6
-rw-r--r--zpu/sw/helloworld/hello.elfbin0 -> 279938 bytes
-rw-r--r--zpu/sw/setup.sh6
-rw-r--r--zpu/sw/simulator/.classpath7
-rw-r--r--zpu/sw/simulator/.project28
-rw-r--r--zpu/sw/simulator/.settings/org.eclipse.jdt.core.prefs66
-rw-r--r--zpu/sw/simulator/ChangeLog6
-rw-r--r--zpu/sw/simulator/META-INF/MANIFEST.MF11
-rw-r--r--zpu/sw/simulator/build.properties3
-rw-r--r--zpu/sw/simulator/build.xml7
-rw-r--r--zpu/sw/simulator/com/zylin/zpu/simulator/Abel.java109
-rw-r--r--zpu/sw/simulator/com/zylin/zpu/simulator/FileTracer.java285
-rw-r--r--zpu/sw/simulator/com/zylin/zpu/simulator/Host.java46
-rw-r--r--zpu/sw/simulator/com/zylin/zpu/simulator/Machine.java17
-rw-r--r--zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java126
-rw-r--r--zpu/sw/simulator/com/zylin/zpu/simulator/PhiFeeble.java34
-rw-r--r--zpu/sw/simulator/com/zylin/zpu/simulator/Sim.java62
-rw-r--r--zpu/sw/simulator/com/zylin/zpu/simulator/SimApp.java177
-rw-r--r--zpu/sw/simulator/com/zylin/zpu/simulator/SimFactory.java8
-rw-r--r--zpu/sw/simulator/com/zylin/zpu/simulator/Simulator.java2065
-rw-r--r--zpu/sw/simulator/com/zylin/zpu/simulator/State.java9
-rw-r--r--zpu/sw/simulator/com/zylin/zpu/simulator/Tracer.java21
-rw-r--r--zpu/sw/simulator/com/zylin/zpu/simulator/ZPU.java14
-rw-r--r--zpu/sw/simulator/com/zylin/zpu/simulator/applet/ZPUApplet.java281
-rw-r--r--zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/BadPacketException.java22
-rw-r--r--zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/CPUException.java23
-rw-r--r--zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/DebuggerBreakpointException.java10
-rw-r--r--zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/EndSessionException.java46
-rw-r--r--zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/GDBServerException.java25
-rw-r--r--zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/HardwareWatchPointException.java12
-rw-r--r--zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/IllegalInstructionException.java23
-rw-r--r--zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/InterruptException.java23
-rw-r--r--zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/MemoryAccessException.java23
-rw-r--r--zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/NoAckException.java22
-rw-r--r--zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/TraceException.java22
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-rw-r--r--zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/UnsupportedSyscallException.java12
-rw-r--r--zpu/sw/simulator/com/zylin/zpu/simulator/gdb/GDBServer.java364
-rw-r--r--zpu/sw/simulator/com/zylin/zpu/simulator/gdb/Packet.java472
-rw-r--r--zpu/sw/simulator/com/zylin/zpu/simulator/tools/MakeDRAM.java39
-rw-r--r--zpu/sw/simulator/com/zylin/zpu/simulator/tools/MakeRam.java39
-rw-r--r--zpu/sw/simulator/com/zylin/zpu/stats/CountSequences.java94
-rw-r--r--zpu/sw/simulator/com/zylin/zpu/stats/DumpIt.java17
-rw-r--r--zpu/sw/simulator/com/zylin/zpu/stats/Instruction.java62
-rw-r--r--zpu/sw/simulator/com/zylin/zpu/stats/StatKeeper.java52
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-rw-r--r--zpu/sw/startup/crt0.S957
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-rw-r--r--zpu/sw/startup/nextgen_crt0.S894
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diff --git a/zpu/.cvsignore b/zpu/.cvsignore
new file mode 100644
index 0000000..7c32f55
--- /dev/null
+++ b/zpu/.cvsignore
@@ -0,0 +1 @@
+install
diff --git a/zpu/.project b/zpu/.project
new file mode 100644
index 0000000..55b1cb8
--- /dev/null
+++ b/zpu/.project
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>zpu</name>
+ <comment></comment>
+ <projects>
+ </projects>
+ <buildSpec>
+ </buildSpec>
+ <natures>
+ </natures>
+</projectDescription>
diff --git a/zpu/COPYING b/zpu/COPYING
new file mode 100644
index 0000000..4212a5b
--- /dev/null
+++ b/zpu/COPYING
@@ -0,0 +1,16 @@
+About ZPU licensing:
+
+The license for HDL implementations is FreeBSD to be
+friendly towards commercial projects and other open source
+projects, however the architecture, documentation and tools will be GPL.
+
+This means that all updates to the architecture must be shared, but actual
+implementations(which are small and can be very project speific) can
+be friendly towards commercial considerations.
+
+Patches to update files w/correct licensing info will be most appreciated!
+
+The ZPU and all the files are per 1/1-2008 Copyright Zylin AS, i.e.
+Zylin is free to decide upon the BSD license for HDL implementation
+and GPL for architecture, tools and documentation.
+ \ No newline at end of file
diff --git a/zpu/ChangeLog b/zpu/ChangeLog
new file mode 100644
index 0000000..2ed7369
--- /dev/null
+++ b/zpu/ChangeLog
@@ -0,0 +1,90 @@
+2008-11-12 Álvaro Lopes <alvieboy@alvie.com>
+ * zpu/hdl/zpu4/core/zpu_core.vhd: Basic interrupt implementation
+ for zpu4 core.
+2008-09-16 Salvador Eduardo Tropea <salvador@inti.gob.ar>
+ * zpu/hdl/zealot: added small ZPU core, testbenches and FPGA implementation
+2008-09-11 Salvador Eduardo Tropea <salvador@inti.gob.ar>
+ * zpu/docs/zpu_arch.html: added Zealot information.
+2008-09-08 Salvador Eduardo Tropea <salvador@inti.gob.ar>
+ * zpu/hdl/zealot: a complete ZPU implementation cleaned up and
+ with a UART.
+2008-08-25 Salvador Eduardo Tropea <salvador@inti.gov.ar>
+ * zpu/docs/arch_html: Fix typo in zpu_arch.html w.r.t. ZPU UART/Debug channel
+2008-08-18 Øyvind Harboe
+ * duplicated crt0.s and some other stuff from libgloss into
+ sw/startup. This makes it easier to tinker w/startup code.
+2008-08-08 Salvador E. Tropea
+ * zpu/hdl/zpu4/core/histogram.perl - generate opcode histogram from
+ HDL simulation output
+2008-06-25 Øyvind Harboe
+ * do not enable interrupts for simzpu_small.do. hello world
+ does not have an interrupt handler, so this caused a BREAK
+ instruction to be executed.
+2008-06-18 Miguel Freitas
+ * zpu_config.vhd: Fixed startSp calculation (address in bytes not words)
+2008-06-18 Miguel Freitas
+ * Removed unisim/roc dependency (it was used just to pulse the areset)
+ and fixes paths for building the ghdl examples out of the box.
+ One should check if the areset change doesn't break modelsim.
+2008-06-16 Miguel Freitas
+ * io.vhd: fix address comparsion and added numerous outputs
+ during simulation to make things a bit easier
+ * zpu_config.vhd: do not use hardcoded startSp, allows more easily
+ tinkering w/RAM size
+2008-05-06 Øyvind Harboe
+ * Small ZPU now supports interrupts
+ * added simulation example demonstrating interrupts
+2008-05-05 Øyvind Harboe
+ * added eCos HAL for ZPU
+ zpu/zpu/sw/ecos/repository
+2008-05-04 Øyvind Harboe
+ * moved ZPU core files to seperate folder
+ * deleted some obsolete files
+2008-05-04 jurij kostasenko
+ * Make code synthesize on Synopsis
+ zpu/hdl/zpu4/src/zpu_core_small.vhd
+ zpu/hdl/zpu4/src/io.vhd
+2008-05-01 Øyvind Harboe
+ * zpu/hdl/zy2000 - ZPU implementation used on the zy2000 dev kit
+2008-04-17 Arnim Läuger
+ * zpu/hdl/example_ghdl/ghdl_import.sh, zpu/hdl/example_ghdl/ghdl_make.sh,
+ zpu/hdl/example_ghdl/ghdl_options.sh, zpu/hdl/example_ghdl/README: GHDL example
+ * zpu/hdl/zpu4/src/dmipssmalltrace_ghdl.sh: testcase for GHDL
+ * zpu/hdl/zpu4/src/dmipstrace_ghdl.sh: testcase for GHDL
+ * zpu/hdl/zpu4/src/simzpu_medium_ghdl.sh: testcase for GHDL
+ * zpu/hdl/example/helloworld.vhd, zpu/hdl/zpu4/src/bram_dmips.vhd,
+ zpu/hdl/zpu4/src/dmipssmalltrace_ghdl.sh, zpu/hdl/zpu4/src/dram_dmips.vhd,
+ zpu/hdl/zpu4/src/dram_hello.vhd, zpu/hdl/zpu4/src/io.vhd,
+ zpu/hdl/zpu4/src/sim_fpga_top.vhd, zpu/hdl/zpu4/src/sim_small_fpga_top.vhd,
+ zpu/hdl/zpu4/src/timer.vhd, zpu/hdl/zpu4/src/trace.vhd,
+ zpu/hdl/zpu4/src/zpu_config_trace.vhd, zpu/hdl/zpu4/src/zpu_core_small.vhd,
+ zpu/hdl/zpu4/src/zpu_core.vhd, zpu/hdl/zpu4/src/zpupkg.vhd: conversion to numeric_std
+2008-04-17 Øyvind Harboe
+ * deleted duplicate files from example folder.
+ * retired Xilinx synthesizing example. It messes up the zpu4 directory.
+2008-04-16 Øyvind Harboe
+ * zpu/doc/zpupresentation_old.odt: interesting bits moved into zpu_arch.html
+ * zpu/doc/zpupresentation.*: interesting bits moved into zpu_arch.html
+ * zpu/docs/zpu_arch.html: added Phi memory map to end of zpu_arch.html
+ * zpu/docs/zpuphiregs.odt: retired
+ * zpu/docs/zpu_arch.html: added. Need to define instruction set.
+ * zpu/docs/zpu_arch.odt: retired
+2008-04-15 Øyvind Harboe
+ * zpu/docs/zpu_arch.odt - a short summary of the architecture
+ * zpu/simzpu_bram.do - retired.
+ * zpu/zpu_core_bram.vhd - retired
+ * zpu/hdl/zpu3 - retired
+2008-04-05 Øyvind Harboe
+ * zpu/docs/zpuphiregs.odt - ZPU Phi register overview
+2008-03-06 Adam Pierce
+ * zpu/zpu/hdl/example/zpuromgen.c - generate rom files
+ without java
+2008-02-21 Øyvind Harboe
+ * zpu/zpu/sw/index.html. Changed it a bit to make installation easier.
+ * zpu/zpu/hdl/index.html. Sharpened instructions and shows two working
+ examples. Small & medium ZPU.
+ * got zpu4/src/simzpu_medium.do working again.
+2008-02-11 Øyvind Harboe
+ * hdl/index.html. Fixed typo. Use objcopy and not objdump.
+2008-01-02 Øyvind Harboe
+ * Moved to www.opencores.org
diff --git a/zpu/STATUS b/zpu/STATUS
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--- /dev/null
+++ b/zpu/STATUS
@@ -0,0 +1,11 @@
+The current state of the ZPU:
+
+- Patches welcome!
+- Zylin is rummaging up the various files that might be of interest
+ to the open source ZPU project.
+- The ZPU, GCC toolchain and HDL works. Zylin eCosBoard 1.1 ships w/a
+ ZPU(see http://www.zylin.com), if you need a development board before
+ implementing on your own system.
+- The docs leave a lot to be desired at this point.
+- Licensing needs to be ironed out. After which lots of files will have
+ to be updated, strictly speaking. Patches welcome!
diff --git a/zpu/docs/images/GCC_logo.png b/zpu/docs/images/GCC_logo.png
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@@ -0,0 +1,2443 @@
+<html>
+<body>
+<h1>This Document</h1>
+This is a snapshot of the zpu/zpu/docs/zpu_arch.html document in CVS.
+<p>
+Several of the links will only work if you have checked out the zpu/zpu tree from opencores CVS. See <a href="#download">Download</a> below.
+<h1>Index</h1>
+<ul>
+<li> <a href="#introduction">Introduction</a>
+ <ul>
+ <li> <a href="#license">License</a>
+ <li> <a href="#features">Features</a>
+ <li> <a href="#status">Status</a>
+ <li> <a href="#download">Download</a>
+ <li> <a href="#patch">Creating a patch</a>
+ <li> <a href="#mailinglist">Getting help - mailing list</a>
+ </ul>
+<li> <a href="#architecture">Core Architecture</a>
+ <ul>
+ <li> <a href="#instructionset">Instruction set</a>
+ <li> <a href="#interrupts">Interrupts</a>
+ <li> <a href="#startup">Startup code (aka crt0.s)</a>
+ <li> <a href="#vectors">Jump vectors</a>
+ </ul>
+<li> <a href="#implementations">Core Implementations</a>
+ <ul>
+ <li> <a href="#performance">Performance Summary</a>
+ <li> <a href="#zpu4_small">zpu4 small</a>
+ <li> <a href="#zpu4_medium">zpu4 medium</a>
+ <li> <a href="#alzpu_pipe">alzpu pipelined</a>
+ <li> <a href="#zealot">Zealot medium and small</a>
+ <li> <a href="#zy2000">ZY2000 SOC</a>
+ <li> <a href="#verilogwip">Un-named verilog translation</a>
+ <li> <a href="#implementing">Implementing your own ZPU</a>
+ </ul>
+<li> <a href="#refdesign">Reference Designs</a>
+ <ul>
+ <li> <a href="#ref_min">SOC - Minimal (core+RAM)</a>
+ <li> <a href="#ref_basic">SOC - Basic (core+RAM+UART)</a>
+ <li> <a href="#ref_soc">SOC - Board (core+RAM+Wishbone+++)</a>
+ <li> <a href="#rams">Common - RAM models</a>
+ <li> <a href="#wishbone">Common - Wishbone</a>
+ <li> <a href="#uart">Common - UART</a>
+ <li> <a href="#spicontroller">Common - SPI flash controller</a>
+ </ul>
+<li> <a href="#tools">Working with tools and core</a>
+ <ul>
+ <li> <a href="#setuplinux">Setup - Linux toolchain</a>
+ <li> <a href="#setupcygwin">Setup - Cygwin toolchain</a>
+ <li> <a href="#gcc2ram">GCC to RAM</a>
+ <li> <a href="#hdlsim">HDL simulation (ZPU4)</a>
+ <li> <a href="#gdbsim">GDB simulation (ZPU4)</a>
+ <li> <a href="#simulator">Instruction Set Simulator</a>
+ </ul>
+<li> <a href="#misc">Miscellaneous</a>
+ <ul>
+ <li> <a href="#tuning">Speeding up the ZPU</a>
+ <li> <a href="#codesize">Optimizing for code size</a>
+ <li> <a href="#ecos">Installing eCos build tools</a>
+ <li> <a href="#memorymap">Memory map</a>
+ </ul>
+<li> <a href="#todo">TODO</a>
+ <ul>
+ <li> <a href="#todolist">TODO list</a>
+ <li> <a href="#repository">Repository Re-org</a>
+ <li> <a href="#nextgen">Next generation ZPU</a>
+ <li> <a href="#float">Floating point support</a>
+ </ul>
+</ul>
+
+<hr> <!-- +++++++++++++++++++++++++++++++++++++++++++++++++++++ -->
+
+<a name="introduction"/>
+<h1>Introduction</h1>
+<P>The worlds smallest 32 bit CPU with GCC toolchain.
+<P>The ZPU is a small CPU in two ways: it takes up very little resources and
+the architecture itself is small. The latter can be important when learning
+about CPU architectures and implementing variations of the ZPU where
+aspects of CPU design is examined. In academia students can learn VHDL,
+CPU architecture in general and complete exercises in the course of a year.</P>
+<P>
+The current ZPU instruction set and architecture has not changed for
+the last couple of years and can be considered quite stable. There is
+a lot of discussion about various modifications to the ZPU architecture
+in the zylin-zpu mailing list, but currently no actual modifications are
+planned as the improvements that have been identified are relatively
+slight(&lt;30% performance/size improvement).
+</P>
+<P>
+There are a handful of implementations of the ZPU. Most of these usually
+have some strong points and there is some movement in the direction of
+consolidating improvements into a few officially recommended ZPU
+implementations.
+</P>
+<P>
+For those that are interested in the Zylin ZPU, I recommend joining
+up on the zylin-zpu mailing list and participating in the discussion
+there. The zylin-zpu is a friendly place where people of different
+skills, hardware, software, tools meet to exchange ideas about the ZPU
+and microprocessor architecture in general.
+</P>
+
+<P>Sincerely,</P>
+<P>&Oslash;yvind Harboe <BR>Zylin AS
+</P>
+
+<a name="license"/>
+<h2>License</h2>
+<P>The project includes HDL, GCC toolchain and eCos HAL.
+
+<P>The ZPU has a BSD license for the HDL and GPL for the rest.
+This allows users to implement any version of the ZPU they want in
+commercial products, but if improvements are done to the architecture
+as such, then they need to be contributed back.
+</P>
+
+<P>Per Jan 1. 2008, Zylin has the Copyright for the ZPU, i.e. Zylin
+is free to decide that the ZPU shall have a BSD license for HDL + GPL
+for the rest.</P>
+
+<a name="features"/>
+<h2>Features</h2>
+<UL>
+ <LI>Small size: (See <a href="#implementations">performance summary</a>)
+ <LI>Code size 80% of ARM Thumb
+ <LI>GCC toolchain(GDB, newlib, libstdc+)
+ <LI>eCos embedded operating system support
+</UL>
+
+<a name="status"/>
+<h2>Status</h2>
+<UL>
+ <LI>HDL works
+ <LI>GCC toolchain works
+ <LI>eCos HAL works
+</UL>
+<P>... but there is a long <a href="#todo">TODO</a> list</P>
+<P>Expect churn as we converge onto a shorter list of <a href="#implementations">implementations</a>.
+
+<a name="download"/>
+<h2>Download source code</h2>
+The ZPU HDL source code is available as a GIT repository from <a href="http://repo.or.cz/w/zpu.git" target="_blank">http://repo.or.cz/w/zpu.git</a>.
+You can download the latest sourcecode as a snapshot without installing GIT.
+<p>
+Previously the ZPU repository was hosted as a CVS repository at www.opencores.org,
+but that ZPU CVS repository is there only for historical reference at this point.
+Once www.opencores.org grows a GIT hosting service, the plan is to replicate
+the GIT repository there.
+
+<p>
+The GCC ZPU toolchain is available from <a href ="http://repo.or.cz/w/zpugcc.git" target ="_blank">http://repo.or.cz/w/zpugcc.git</a>. The ZPU GCC toolchain is BIG (over 100 MBytes).
+<a name="patch"/>
+<h2>GIT</h2>
+For more advanced use of GIT, you will need to hit the books and read up
+on the GIT documentation.
+<p/>
+That said, you can ask "silly" newbie questions about GIT on the <a href="#mailinglist">zylin-zpu mailing
+list</a> and you should receive some friendly prodding in the right direction
+w.r.t. finding reading material.
+<a name="mailinglist"/>
+<h2>Getting help - mailing list</h2>
+<P>The place to get help is the <a href="http://www.zylin.com/mailinglist.html">zylin-zpu mailing list</a>
+
+<P>
+The ZPU is an open source project and if you demonstrate that you have
+made an effort to read the documentation and googled, then you will
+normally get some help from this list if you ask clear questions.
+
+<hr> <!-- +++++++++++++++++++++++++++++++++++++++++++++++++++++ -->
+
+
+<a name="architecture"/>
+<h1>Architecture</h1>
+The ZPU is a zero operand, or stack based CPU. The opcodes have a fixed width of 8 bits.
+<p>
+Example:
+<p>
+<div style="white-space:pre;background-color:#dddddd;">
+ <code style="white-space:pre;background-color:#dddddd;">
+ IM 5 ; push 5 onto the stack
+ LOADSP 20 ; push value at memory location SP+20
+ ADD ; pop 2 values on the stack and push the result
+ </code>
+</div>
+As can be seen, a lot of information is packed into the 8 bits, e.g. the IM instruction pushes a 7 bit signed integer onto the stack.
+<p>
+The choice of opcodes is intimately tied to the GCC toolchain capabilities.
+<p>
+<div style="white-space:pre;background-color:#dddddd;">
+ <code style="white-space:pre;background-color:#dddddd;">
+ /* simple program showing some interesting qualities of the ZPU toolchain */
+ void bar(int);
+ int j;
+ void foo(int a, int b, int c)
+ {
+ a++;
+ b+=a;
+ j=c;
+ bar(b);
+ }
+
+foo:
+ loadsp 4 ; a is at memory location SP+4
+ im 1
+ add
+ loadsp 12 ; b is now at memory location SP+12
+ add
+ loadsp 16 ; c is now at memory location SP+16
+ im 24 ; «j» is at absolute memory location 24.
+; Notice how the ZPU toolchain is using link-time relaxation
+; to squeeze the address into a single no-op
+ store
+ im 22 ; the fn bar is at address 22
+ call
+ im 12
+ return ; 12 bytes of arguments + return from fn
+</code>
+</div>
+
+<a name="instructionset"/>
+<h2>Instruction set</h2>
+<p>A base set of instructions must be implemented in RTL, but the rest may be implemented as RTL or as microcode. This allows a tradeoff of core size vs code size and performance.
+<p>The instructions that may be implemented in RTL or microcode are referred to as emulated instructions. The microcode is in crt0.s. The <a href="#implementations">implementation</a> determines which instructions run as microcode.
+<p>All operations are 32 bit wide.
+<p>TODO Is the table broken? Fix it.
+
+<table border="1">
+ <tr><td>Name</td><td>Opcode</td><td>Description</td><td>Definition</td></tr>
+ <tr>
+ <td>
+ BREAKPOINT
+ </td>
+ <td>
+ 00000000
+ </td>
+ <td>
+ The debugger sets a memory location to this value to set a breakpoint. Once a JTAG-like
+ debugger interface is added, it will be convenient to be able to distinguish
+ between a breakpoint and an illegal(possibly emulated) instruction.
+ </td>
+ <td>
+ No effect on registers
+ </td>
+ </tr>
+ <tr>
+ <td>
+ IM
+ </td>
+ <td>
+ 1xxx xxxx
+ </td>
+ <td>
+ Pushes 7 bit sign extended integer and sets the a «instruction decode interrupt mask» flag(IDIM).
+ <p>
+ If the IDIM flag is already set, this instruction shifts the value on the stack left by 7 bits and stores the 7 bit immediate value into the lower 7 bits.
+ <p>
+ Unless an instruction is listed as treating the IDIM flag specially, it should be assumed to clear the IDIM flag.
+ <p>
+ To push a 14 bit integer onto the stack, use two consecutive IM instructions.
+ <p>
+ If multiple immediate integers are to be pushed onto the stack, they must be interleaved with another instruction, typically NOP.
+ </td>
+ <td>
+ <code style="white-space:pre;">
+pc <= pc + 1 <br>
+idim <= 1 <br>
+if (idim=0) then <br>
+ sp <= sp - 1; <br>
+ for i in wordSize-1 downto 7 loop <br>
+ mem(sp)(i) <= opcode(6) <br>
+ end loop <br>
+ mem(sp)(6 downto 0) <= opcode(6 downto 0) <br>
+else <br>
+ mem(sp)(wordSize-1 downto 7) <= mem(sp)(wordSize-8 downto 0) <br>
+ mem(sp)(6 downto 0) <= opcode(6 downto 0) <br>
+end if
+ </code>
+
+ </td>
+ </tr>
+ <tr>
+ <td>
+ STORESP
+ </td>
+ <td>
+ 010x xxxx
+ </td>
+ <td>
+ Pop value off stack and store it in the SP+xxxxx*4 memory location, where xxxxx is a positive integer.
+ </td>
+ <td>
+ </td>
+ </tr>
+ <tr>
+ <td>
+ LOADSP
+ </td>
+ <td>
+ 011x xxxx
+ </td>
+ <td>
+ Push value of memory location SP+xxxxx*4, where xxxxx is a positive integer, onto stack.
+ </td>
+ <td>
+
+ </td>
+ </tr>
+ <tr>
+ <td>
+ ADDSP
+ </td>
+ <td>
+ 0001 xxxx
+ </td>
+ <td>
+ Add value of memory location SP+xxxx*4 to value on top of stack.
+ </td>
+ <td>
+
+ </td>
+ </tr>
+ <tr>
+ <td>
+ EMULATE
+ </td>
+ <td>
+ 001x xxxx
+ </td>
+ <td>
+ Push PC to stack and set PC to 0x0+xxxxx*32. This is used to emulate opcodes. See
+ zpupgk.vhd for list of emulate opcode values used. zpu_core.vhd contains
+ reference implementations of these instructions rather than letting the ZPU execute the EMULATE instruction
+ <p>
+ One way to improve performance of the ZPU is to implement some of
+ the EMULATE instructions.
+
+ </td>
+ <td>
+
+ </td>
+ </tr>
+ <tr>
+ <td>
+ PUSHPC
+ </td>
+ <td>
+ emulated
+ </td>
+ <td>
+ Pushes program counter onto the stack.
+ </td>
+ <td>
+
+ </td>
+ </tr>
+ <tr>
+ <td>
+ POPPC
+ </td>
+ <td>
+ 0000 0100
+ </td>
+ <td>
+ Pops address off stack and sets PC
+ </td>
+ <td>
+
+ </td>
+ </tr>
+ <tr>
+ <td>
+ LOAD
+ </td>
+ <td>
+ 0000 1000
+ </td>
+ <td>
+ Pops address stored on stack and loads the value of that address onto stack.
+ <p>
+ Bit 0 and 1 of address are always treated as 0(i.e. ignored) by
+ the HDL implementations and C code is guaranteed by the programming
+ model never to use 32 bit LOAD on non-32 bit aligned addresses(i.e.
+ if a program does this, then it has a bug).
+ </td>
+ <td>
+
+ </td>
+ </tr>
+ <tr>
+ <td>
+ STORE
+ </td>
+ <td>
+ 0000 1100
+ </td>
+ <td>
+ Pops address, then value from stack and stores the value into the memory location of the address.
+ <p>
+ Bit 0 and 1 of address are always treated as 0
+ </td>
+ <td>
+
+ </td>
+ </tr>
+ <tr>
+ <td>
+ PUSHSP
+ </td>
+ <td>
+ 0000 0010
+ </td>
+ <td>
+ Pushes stack pointer.
+ </td>
+ <td>
+
+ </td>
+ </tr>
+ <tr>
+ <td>
+ POPSP
+ </td>
+ <td>
+ 0000 1101
+ </td>
+ <td>
+ Pops value off top of stack and sets SP to that value. Used to allocate/deallocate space on stack for variables or when changing threads.
+ </td>
+ <td>
+
+ </td>
+ </tr>
+ <tr>
+ <td>
+ ADD
+ </td>
+ <td>
+ 0000 0101
+ </td>
+ <td>
+ Pops two values on stack adds them and pushes the result
+ </td>
+ <td>
+
+ </td>
+ </tr>
+ <tr>
+ <td>
+ AND
+ </td>
+ <td>
+ 0000 0110
+ </td>
+ <td>
+ Pops two values off the stack and does a bitwise-and & pushes the result onto the stack
+ </td>
+ <td>
+
+ </td>
+ </tr>
+ <tr>
+ <td>
+ OR
+ </td>
+ <td>
+ 0000 0111
+ </td>
+ <td>
+ Pops two integers, does a bitwise or and pushes result
+ </td>
+ <td>
+
+ </td>
+ </tr>
+ <tr>
+ <td>
+ NOT
+ </td>
+ <td>
+ 0000 1001
+ </td>
+ <td>
+ Bitwise inverse of value on stack
+
+ </td>
+ <td>
+
+ </td>
+ </tr>
+ <tr>
+ <td>
+ FLIP
+ </td>
+ <td>
+ 0000 1010
+ </td>
+ <td>
+ Reverses the bit order of the value on the stack, i.e. abc->cba, 100->001, 110->011, etc.
+ <p>
+ The raison d'etre for this instruction is mainly to emulate other instructions.
+ </td>
+ <td>
+
+ </td>
+ </tr>
+ <tr>
+ <td>
+ NOP
+ </td>
+ <td>
+ 0000 1011
+ </td>
+ <td>
+ No operation, clears IDIM flag as side effect, i.e. used between two
+ consecutive IM instructions to push two values onto the stack.
+ </td>
+ <td>
+
+ </td>
+ </tr>
+ <tr>
+ <td>
+ PUSHSPADD
+ </td>
+ <td>
+ 61
+ </td>
+ <td>
+ a=sp; <br>
+ b=popIntStack()*4;<br>
+ pushIntStack(a+b);<br>
+ </td>
+ <td>
+
+ </td>
+ </tr>
+
+ <tr>
+ <td>
+ POPPCREL
+ </td>
+ <td>
+ 57
+ </td>
+ <td>
+ setPc(popIntStack()+getPc());
+ </td>
+ <td>
+
+ </td>
+ </tr>
+ <tr>
+ <td>
+ SUB
+ </td>
+ <td>
+ 49
+ </td>
+ <td>
+ int a=popIntStack();<br>
+ int b=popIntStack();<br>
+ pushIntStack(b-a);<br>
+ </td>
+ <td>
+
+ </td>
+ </tr>
+ <tr>
+ <td>
+ XOR
+ </td>
+ <td>
+ 50
+ </td>
+ <td>
+pushIntStack(popIntStack() ^ popIntStack());
+ </td>
+ <td>
+
+ </td>
+ </tr>
+ <tr>
+ <td>
+ LOADB
+ </td>
+ <td>
+ 51
+ </td>
+ <td>
+ 8 bit load instruction. Really only here for compatibility with
+ C programming model. Also it has a big impact on DMIPS test.
+ <p>
+ pushIntStack(cpuReadByte(popIntStack())&0xff);
+ </td>
+ <td>
+
+ </td>
+ </tr>
+ <tr>
+ <td>
+ STOREB
+ </td>
+ <td>
+ 52
+ </td>
+ <td>
+ 8 bit store instruction. Really only here for compatibility with
+ C programming model. Also it has a big impact on DMIPS test.
+ <p>
+ addr = popIntStack();<br>
+ val = popIntStack();<br>
+ cpuWriteByte(addr, val);
+</td>
+ <td>
+
+ </td>
+ </tr>
+ <tr>
+ <td>
+ LOADH
+ </td>
+ <td>
+ 34
+ </td>
+ <td>
+
+ 16 bit load instruction. Really only here for compatibility with
+ C programming model.
+ <p>
+
+ pushIntStack(cpuReadWord(popIntStack()));
+ </td>
+ <td>
+
+ </td>
+ </tr>
+ <tr>
+ <td>
+ STOREH
+ </td>
+ <td>
+ 35
+ </td>
+ <td>
+ 16 bit store instruction. Really only here for compatibility with
+ C programming model.
+ <p>
+addr = popIntStack();<br>
+ val = popIntStack();<br>
+ cpuWriteWord(addr, val);
+ </td>
+ <td>
+
+ </td>
+ </tr>
+ <tr>
+ <td>
+ LESSTHAN
+ </td>
+ <td>
+ 36
+ </td>
+ <td>
+ Signed comparison<br>
+ a = popIntStack();<br>
+ b = popIntStack();<br>
+ pushIntStack((a < b) ? 1 : 0);<br>
+ </td>
+ <td>
+
+ </td>
+ </tr>
+ <tr>
+ <td>
+ LESSTHANOREQUAL
+ </td>
+ <td>
+ 37
+ </td>
+ <td>
+ Signed comparison<br>
+ a = popIntStack();<br>
+ b = popIntStack();<br>
+ pushIntStack((a <= b) ? 1 : 0);
+ </td>
+ <td>
+
+ </td>
+ </tr>
+ <tr>
+ <td>
+ ULESSTHAN
+ </td>
+ <td>
+ 38
+ </td>
+ <td>
+ Unsigned comparison<br>
+ long a;//long is here 64 bit signed integer<br>
+ long b;<br>
+ a = ((long) popIntStack()) & INTMASK; // INTMASK is unsigned 0x00000000ffffffff<br>
+ b = ((long) popIntStack()) & INTMASK;<br>
+ pushIntStack((a < b) ? 1 : 0);
+ </td>
+ <td>
+
+ </td>
+ </tr>
+ <tr>
+ <td>
+ ULESSTHANOREQUAL
+ </td>
+ <td>
+ 39
+ </td>
+ <td>
+ Unsigned comparison<br>
+ long a;//long is here 64 bit signed integer<br>
+ long b;<br>
+ a = ((long) popIntStack()) & INTMASK; // INTMASK is unsigned 0x00000000ffffffff<br>
+ b = ((long) popIntStack()) & INTMASK;<br>
+ pushIntStack((a <= b) ? 1 : 0);
+ </td>
+ <td>
+
+ </td>
+ </tr>
+ <tr>
+ <td>
+ EQBRANCH
+ </td>
+ <td>
+ 55
+ </td>
+ <td>
+ int compare;<br>
+ int target;<br>
+ target = popIntStack() + pc;<br>
+ compare = popIntStack();<br>
+ if (compare == 0)<br>
+ {<br>
+ setPc(target);<br>
+ } else<br>
+ {<br>
+ setPc(pc + 1);<br>
+ }
+ </td>
+ <td>
+
+ </td>
+ </tr>
+ <tr>
+ <td>
+ NEQBRANCH
+ </td>
+ <td>
+ 56
+ </td>
+ <td>
+ int compare;<br>
+ int target;<br>
+ target = popIntStack() + pc;<br>
+ compare = popIntStack();<br>
+ if (compare != 0)<br>
+ {<br>
+ setPc(target);<br>
+ } else<br>
+ {<br>
+ setPc(pc + 1);<br>
+ }<br>
+ </td>
+ <td>
+
+ </td>
+ </tr>
+ <tr>
+ <td>
+ MULT
+ </td>
+ <td>
+ 41
+ </td>
+ <td>
+ Signed 32 bit multiply <br>
+ pushIntStack(popIntStack() * popIntStack());
+ </td>
+ <td>
+
+ </td>
+ </tr>
+ <tr>
+ <td>
+ DIV
+ </td>
+ <td>
+ 53
+ </td>
+ <td>
+ Signed 32 bit integer divide.<br>
+ a = popIntStack();<br>
+ b = popIntStack();<br>
+ if (b == 0)<br>
+ {<br>
+ // undefined<br>
+ }
+ pushIntStack(a / b);<br>
+ </td>
+ <td>
+
+ </td>
+ </tr>
+ <tr>
+ <td>
+ MOD
+ </td>
+ <td>
+ 54
+ </td>
+ <td>
+ Signed 32 bit integer modulo.<br>
+ a = popIntStack(); <br>
+ b = popIntStack();<br>
+ if (b == 0)<br>
+ {<br>
+ // undefined <br>
+ }<br>
+ pushIntStack(a % b); <br>
+ </td>
+ <td>
+
+ </td>
+ </tr>
+ <tr>
+ <td>
+ LSHIFTRIGHT
+ </td>
+ <td>
+ 42
+ </td>
+ <td>
+ unsigned shift right.<br>
+ long shift;<br>
+ long valX;<br>
+ int t;<br>
+ shift = ((long) popIntStack()) & INTMASK;<br>
+ valX = ((long) popIntStack()) & INTMASK;<br>
+ t = (int) (valX >> (shift & 0x3f));<br>
+ pushIntStack(t);<br>
+ </td>
+ <td>
+
+ </td>
+ </tr>
+ <tr>
+ <td>
+ ASHIFTLEFT
+ </td>
+ <td>
+ 43
+ </td>
+ <td>
+ arithmetic(signed) shift left.<br>
+
+ long shift;<br>
+ long valX;<br>
+ shift = ((long) popIntStack()) & INTMASK;<br>
+ valX = ((long) popIntStack()) & INTMASK;<br>
+ int t = (int) (valX << (shift & 0x3f));<br>
+ pushIntStack(t);<br>
+ </td>
+ <td>
+
+ </td>
+ </tr>
+ <tr>
+ <td>
+ ASHIFTRIGHT
+ </td>
+ <td>
+ 43
+ </td>
+ <td>
+ arithmetic(signed) shift left.<br>
+ long shift;<br>
+ int valX;<br>
+ shift = ((long) popIntStack()) & INTMASK;<br>
+ valX = popIntStack();<br>
+ int t = valX >> (shift & 0x3f);<br>
+ pushIntStack(t);<br>
+
+ </td>
+ <td>
+
+ </td>
+ </tr>
+
+ <tr>
+ <td>
+ CALL
+ </td>
+ <td>
+ 45
+ </td>
+ <td>
+ call procedure.<br>
+ <br>
+ int address = pop();<br>
+ push(pc + 1);<br>
+ setPc(address); <br>
+ </td>
+ <td>
+
+ </td>
+ </tr>
+ <tr>
+ <td>
+ CALLPCREL
+ </td>
+ <td>
+ 63
+ </td>
+ <td>
+ call procedure pc relative<br>
+ <br>
+int address = pop();<br>
+ push(pc + 1);<br>
+ setPc(address+pc); </td>
+ <td>
+
+ </td>
+ </tr>
+
+
+ <tr>
+ <td>
+ EQ
+ </td>
+ <td>
+ 46
+ </td>
+ <td>
+ pushIntStack((popIntStack() == popIntStack()) ? 1 : 0); <td>
+
+ </td>
+ </tr>
+ <tr>
+ <td>
+ NEQ
+ </td>
+ <td>
+ 47
+ </td>
+ <td>
+ pushIntStack((popIntStack() != popIntStack()) ? 1 : 0); <td>
+
+ </td>
+ </tr>
+ <tr>
+ <td>
+ NEG
+ </td>
+ <td>
+ 48
+ </td>
+ <td>
+ pushIntStack(-popIntStack());<td>
+
+ </td>
+ </tr>
+
+
+</table>
+
+<a name="interrupts"/>
+<h2>Interrupts</h2>
+The ZPU supports interrupts.
+<p>
+To trigger an interrupt, the interrupt signal must be asserted. The ZPU does
+not define any interrupt disabling mechanism, this must be implemented by the
+interrupt controller and controlled via memory mapped IO.
+<p>
+Interrupts are masked when the IDIM flag is set, i.e.
+with consecutive IM instructions.
+<p>
+The ZPU has an edge triggered interrupt. As the ZPU notices that the interrupt
+is asserted, it will execute the interrupt instruction. The interrupt signal
+must stay asserted until the ZPU acknowledges it.
+<p>
+When the interrupt instruction is executed, the PC will be pushed onto the
+stack and the PC will be set to the interrupt vector address (0x20).
+<p>
+Note that the GCC compiler requires three registers r0,r1,r2,r3 for some
+rather uncommon operations. These 32 registers are mapped to memory locations 0x0,
+0x4, 0x8, 0xc. The default interrupt vector at address 0x20 will load the
+value of these memory locations onto the stack, call _zpu_interrupt and
+restore them.
+<p>
+See <a href="../hdl/zpu4/test/interrupt/">zpu/hdl/zpu4/test/interrupt/</a> for C code and <a href ="../hdl/example/simzpu_interrupt.do">zpu/hdl/example/simzpu_interrupt.do</a>
+for simulation example.
+
+<a name="startup"/>
+<h2>Custom startup code (aka crt0.s)</h2>
+To minimize the size of an application, one important trick is to
+strip down the startup code. The startup code contains microcode for emulation
+of instructions that may never be used by a particular application, or are made redundant because the instructions are implemented in RTL.
+<p>
+The startup code is found in the GCC source code under gcc/libgloss/zpu,
+but to make the startup code more available, it has been duplicated
+into <a href="../sw/startup">zpu/sw/startup</a>
+<p>
+On the <a href="#todo">TODO</a> list is work to make it easier to reduce code size.
+<p>
+TODO is the following actually useful? if not remove or elaborate.
+<p>
+To minimize startup size, see <a href="../roadshow/roadshow/codesize/">codesize</a>
+demo. This is pretty standard GCC stuff and simple enough once you've
+been over it a couple of times.
+
+
+<a name="vectors"/>
+<h3>Vectors</h3>
+<table border="1">
+ <tr><td>Address</td><td>Name</td><td>Description</td></tr>
+ <tr>
+ <td>0x000</td>
+ <td>Reset</td>
+ <td>
+ 1.When the ZPU boots, this is the first instruction to be executed.
+ <br>
+ 2.The stack pointer is initialised to maximum RAM address
+ </td>
+ </tr>
+ <tr>
+ <td>0x020</td>
+ <td>Interrupt</td>
+ <td>
+ This is the entry point for interrupts.
+ </td>
+ </tr>
+ <tr>
+ <td>0x040-</td>
+ <td>Emulated instructions</td>
+ <td>
+ Emulated opcode 34. Note that opcode 32 and opcode 33 are not normally used to emulate instructions as these memory addresses are already used by boot vector, GCC registers and the interrupt vector.
+ </td>
+ </tr>
+</table>
+
+<hr> <!-- +++++++++++++++++++++++++++++++++++++++++++++++++++++ -->
+
+<a name="implementations"/>
+<h1>Core Implementations</h1>
+zpu4 (superseding zpu3) are original work by &Oslash;yvind Harboe. All other implementations derive from zpu4.
+<p>
+High on the <a href="#todo">TODO</a> list is to reduce the number of implementations taking the best from all. For example interrupts are not universally implemented, IO naming is inconsistent and memory architectures differ.
+<p>
+Ultimately we should try to get closer to the opencores coding standard. You can find the document in the opencores cvsroot/common.
+<p>
+For now if you are starting a design, zpu4 or zealot are probably the safest. zealot offers more customization through generics, but lacks interrupts. zpu4 gets more attention. Take your pick.
+
+<a name="performance"/>
+<h2>Performance Summary</h2>
+
+<a href="#todo">TODO</a> fill in performance table for Altera.
+<p>
+Tests are done with the <a href="#zealot">Zealot</a>
+ SoC-System and Xilinx ISE 12.2 with standard settings.
+ For the MachXO2 device Lattice Diamond 3.1 with Synplify Pro I-2013.09L was used.
+<p>
+<TABLE WIDTH=604 BORDER=1 BORDERCOLOR="#000000" CELLPADDING=7 CELLSPACING=0 STYLE="page-break-after: avoid">
+ <TR VALIGN=TOP>
+ <TD WIDTH=85> <P><B>CORE/Config</B></P> </TD>
+ <TD WIDTH=85> <P><B>Spartan-3</B></P> </TD>
+ <TD WIDTH=85> <P><B>Spartan-3E</B></P> </TD>
+ <TD WIDTH=85> <P><B>Spartan-6</B></P> </TD>
+ <TD WIDTH=85> <P><B>Virtex-5</B></P> </TD>
+ <TD WIDTH=85> <P><B>MachXO2</B></P> </TD>
+ <TD WIDTH=85> <P><B>DMIPS</B></P> </TD>
+ </TR>
+
+<TR VALIGN=TOP>
+<TD WIDTH=85> <P>
+zpu4 small
+maxAddrBit=16
+</P> </TD>
+<TD WIDTH=85> <PRE>
+<!-- Spartan-3 -->
+591 LUT
+389 REG
+ 0 MULT18x18
+ 16 BRAM
+ 90 fmax
+</PRE> </TD>
+<TD WIDTH=85> <PRE>
+<!-- Spartan-3E -->
+626 LUT
+389 REG
+ 0 MULT18x18
+ 16 BRAM
+100 fmax
+</PRE> </TD>
+<TD WIDTH=85> <PRE>
+<!-- Spartan-6 -->
+639 LUT
+372 REG
+ 0 MULT18x18
+ 16 BRAM
+100 fmax
+</PRE> </TD>
+<TD WIDTH=85> <PRE>
+<!-- Virtex-5 -->
+561 LUT
+391 REG
+ 0 MULT18x18
+ 8 BRAM (RAMB36)
+175 fmax
+</PRE> </TD>
+<TD WIDTH=85> <PRE>
+<!-- MachXO2 -->
+886 LUT4
+459 REG
+
+4 EBR
+75 fmax
+</PRE> </TD>
+<TD WIDTH=85> <!-- DMIPS --> <P>0.5</P> </TD>
+</TR>
+
+<TR VALIGN=TOP> <TD WIDTH=85> <P>zpu4 medium</P> </TD>
+<TD WIDTH=85> <PRE>
+<!-- Spartan-3 -->
+1760 LUT
+ 514 REG
+ 3 MULT18x18
+ 16 BRAM (RAMB16)
+ 75 fmax
+</PRE> </TD>
+<TD WIDTH=85> <PRE>
+<!-- Spartan-3E -->
+1754 LUT
+ 509 REG
+ 3 MULT18x18
+ 16 BRAM (RAMB16)
+ 75 fmax
+</PRE> </TD>
+<TD WIDTH=85> <PRE>
+<!-- Spartan-6 -->
+1162 LUT
+ 481 REG
+ 3 MULT (DSP48A1)
+ 16 BRAM (RAMB16)
+ 80 fmax
+</PRE> </TD>
+<TD WIDTH=85> <PRE>
+<!-- Virtex-5 -->
+1299 LUT
+ 490 REG
+ 3 MULT (DSP48E)
+ 8 BRAM (RAMB36)
+ 125 fmax
+</PRE> </TD>
+<TD WIDTH=85> <PRE>
+<!-- MachXO2 -->
+2429 LUT4
+755 REG
+
+4 EBR
+65 fmax
+</PRE> </TD>
+<TD WIDTH=85><!-- DMIPS --><P>2.6</P> </TD>
+</TR>
+
+ </TABLE>
+
+<a name="zpu4_small"/>
+<h2>zpu4 small</h2>
+Found in <a href="../hdl/zpu4/core/zpu_core_small.vhd">zpu/zpu/hdl/zpu4/core/zpu_core_small.vhd</a>
+<p>
+The small ZPU4 implements the minimum instruction set. It is optimized for size and simplicity
+serving as a reference in both regards.
+<p>
+It uses a RAM (dual port RAM w/read/write to both ports) as data & code storage and
+is implemented as a simple state machine.
+<p>
+Essentially it has three states:
+<ol>
+<li>Fetch - starts fetch of next instruction
+<li>FetchNext - sets up operands for execute cycle
+<li>Decode - decodes instruction
+<li>Execute - well.. executes instruction
+</ol>
+The tricky bit is that there is a tiny bit of interleaving of
+states since the BRAM takes a cycle to perform a fetch/store. The above is the
+normal states the ZPU cycles through unless memory fetch, jumps, etc. take
+place.
+
+<a name="zpu4_medium"/>
+<h2>zpu4 medium</h2>
+Found in <a href="../hdl/zpu4/core/zpu_core.vhd">zpu/zpu/hdl/zpu4/core/zpu_core.vhd</a>
+<p>
+The medium ZPU4 has a single port memory interface. All data, code and IO is
+accessed through this memory interface.
+<p>
+It performs better(despite having less memory bandwidth than zpu_core_small.vhd)
+since it implements many more instructions.
+
+<a name="alzpu_pipe"/>
+<h2>Alvaro's pipelined ZPU</h2>
+All the rave in the mailing list. TBA.
+
+<a name="zealot"/>
+<h2>Zealot</h2>
+Small found in <a href="../hdl/zealot/zpu_small.vhdl">zpu/zpu/hdl/zealot/zpu_small.vhdl</a>
+<p>
+Medium found in <a href="../hdl/zealot/zpu_medium.vhdl">zpu/zpu/hdl/zealot/zpu_medium.vhdl</a>
+<p>
+README found in <a href="../hdl/zealot/0README.txt">zpu/zpu/hdl/zealot/0README.txt</a>
+<p>
+The Zealot version of ZPU was contributed by Salvador E. Tropea.
+<p>
+The key features are:
+
+
+<ul>
+<li>Includes a very basic <a href="#memorymap">PHI I/O</a> synthesizable core.
+It implements the 64 bits clocks counter (timer), GPIO and the UART. This is enough
+to run the DMIPS benchmark and a hello world application. I tested the UART
+@ 9600 bps and @ 115200 bps.</li>
+<li>The ZPU can be customized using generics. It allows the use of more
+than one core in the same project without problems.</li>
+<li>Implements the lshiftright instruction in hardware, this gives around
+10% boost in the DMIPS benchmark (Medium version).</li>
+<li>You can disable various instructions groups and let them to the
+emulation soft, so you can experiment with various LUTs vs DMIPS
+configurations (Medium version).</li>
+<li>The medium version provides aprox. 2.6 DMIPS @ 50 MHz and the small
+0.5 DMIPS @ 50 MHz.</li>
+<li>Enhanced trace module, it includes the assembler for the executed
+instruction and can also measure how much stack was consumed during the
+execution.</li>
+<li>Includes ready to use memory images for a hello world program and the
+DMIPS benchmark.</li>
+<li>Memory and trace blocks outside ZPU. This provides better modularity.</li>
+<li>Much better documented code than the original version.</li>
+</ul>
+
+Simulation and implementation files are provided. You need 16 kB of BRAMs
+for the "hello world" example and 32 kB for the DMIPS benchmark. The medium
+version takes around 1030 slices and 3 multipliers and the small version
+around 430 slices.<p>
+
+The generics for the Zealot Medium ZPU are:<p>
+
+<ul>
+<li><b>WORD_SIZE</b> (integer:=32) Data width, only 32 bits are really
+tested/supported. Adding support for 16 bits should be simple, but the
+toolchain needs to support it.</li>
+<li><b>ADDR_W</b> (integer:=16) Address bus width memory+I/O space. The MSB
+selects the address space (1=I/O).</li>
+<li><b>MEM_W</b> (integer:=15) Memory address bus width. It includes program,
+data and stack sections.</li>
+<li><b>D_CARE_VAL</b> (std_logic:='X') Value used to fill the unsused bits.
+For simulations this should be '0', for synthesis this is a value that your
+tools interprets as "don't care". Xilinx tools could get benefit from using
+'X'. This is particularly true to assign default values and for unreached
+cases. Note that I didn't find it useful.</li>
+<li><b>MULT_PIPE</b> (boolean:=false) Enables the multiplication pipeline.
+This can allow faster clocks but will make the mult instruction slower (more
+clocks consumed).</li>
+<li><b>BINOP_PIPE</b> (integer range 0 to 2:=0) Enables the pipeline for
+the -, =, &lt; and &lt;= operations. This can allow faster clocks but will
+make these instruction slower (more clocks consumed). This value is the
+amount of extra clocks added.</li>
+<li><b>ENA_LEVEL0</b> (boolean:=true) Enables the hardware implementation of
+eq, neqbranch, loadb and pushspadd instructions.</li>
+<li><b>ENA_LEVEL1</b> (boolean:=true) Enables the hardware implementation of
+lessthan, ulessthan, mult, storeb, callpcrel and sub instructions.</li>
+<li><b>ENA_LEVEL2</b> (boolean:=false) Enables the hardware implementation of
+lessthanorequal, ulessthanorequal, call and poppcrel instructions.</li>
+<li><b>ENA_LSHR</b> (boolean:=true) Enables the hardware implementation of
+lshiftright instruction.</li>
+<li><b>ENA_IDLE</b> (boolean:=false) Enables the enable_i usage. This signal
+can hold the CPU in an idle state if after reset this signal remains active.
+When disabled the enable_i signal isn't used and the idle state is removed.</li>
+<li><b>FAST_FETCH</b> (boolean:=true) This version of the ZPU fetches 4
+instructions at ones (32 bits), then they are decoded (2 cycles) and finally
+executed. The decoded instructions are stored in a "decode cache", the first
+instruction is immediately moved to the "current instruction" register and a
+"special instruction" replaces the first slot. This "special instruction"
+makes the CPU go to the fetch state. When you enable this generic the FSM
+does the fetch instead of waiting one clock cycle to go to the fetch state.
+This makes instructions run a little bit faster, but it can cost area and/or
+frequency.</li>
+</ul>
+
+
+<a name="zy2000"/>
+<h2>ZY2000</h2>
+Found in <a href="../hdl/zy2000/zpu_core.vhd">zpu/zpu/hdl/zy2000/zpu_core.vhd</a>
+Modified version of zpu4 medium for use with a wishbone bridge.
+<p>
+The ZY2000 is a complete implementation including: ZPU, DRAM, soft-MAC, wishbone bridges, GPIO subsystem, etc. This also included an eCos HAL w/TCP/IP support.
+
+<a name="verilogwip"/>
+<h2>Verilog translation</h2>
+Found in <a href="../../wip/ZPU_CORE/src/zpu_core.v">zpu/wip/ZPU_CORE/src/zpu_core.v</a>
+<p>
+The verilog version of ZPU (zpu4) was contributed by Jurij Kostasenko. No-one appears to be maintaining it, but it should be a useful starting point for further work. There are some useful scripts there.
+
+<a name="implementing"/>
+<h2>Implementing your own ZPU</h2>
+One of the neat things about the ZPU is that the instruction set and architecture
+is very small and it is easy to implement a ZPU from scratch or modify the
+existing ZPU implementations.
+<p>
+Implementing a ZPU can be done without understanding the toolchain in
+detail, i.e. using exclusively HDL skills and only a rudimentary
+understanding of standard GCC/GDB usage is sufficient.
+<p>
+A few tips:
+<ul>
+<li>Run zpu_core.vhd or zpu_core_small.vhd and generate an instruction trace
+from ModelSim or similar. To check that you own implementation is correctly
+implemented, verify that the instruction trace for the new and old
+ZPU implementations match. This gives you a simple way to do regression
+tests as you develop your ZPU.
+<li>To improve performance, you can add more instructions. The EMULATE instructions
+are optional in HDL since they will be emulated in software if they are not
+implemented in HDL. This allows you to run the ZPU executables unmodified
+regardless of which EMULATE instructions you implement.
+<li>Run the DMIPS test to measure your overall performance
+<li>Run the histogram.perl script on the instruction trace to generate
+histograms of the instructions. Profiling is essential to making
+the right choices w.r.t. optimization for your application.
+</ul>
+
+<hr> <!-- +++++++++++++++++++++++++++++++++++++++++++++++++++++ -->
+
+
+<a name="refdesign"/>
+<h1>Reference Designs</h1>
+The zpu core is independent of IO and memory architecture. Here are three levels of reference designs a user can refer to in order to get started in their own design, regardless of chosen core.
+<p>
+TODO converge on a single IO structure for core implementations.
+<p>
+TODO re-org CVS to make it easy to keep appropriate SW, RTL(verilog and VHDL) , scripts, verification stuff together.
+<p>
+
+<a name="ref_min"/>
+<h2>Minimal (core+RAM)</h2>
+The minimum design is a zpu core with true dual port RAMs attached. This is handy for size/fmax trial in a particular FPGA, and maybe HDL regression. Maybe not a very useful starting point, unless you can DMA all you IO.
+<p>
+TODO provide FPGA scripts.
+<p>
+TODO provide HDL regression environment.
+
+<a name="ref_basic"/>
+<h2>Basic (core+RAM+UART+Timer)</h2>
+The minimum design required for hello_world and DMIPS applications. Requires more RAM and a UART (or something) for stdio. This is handy as a starting point for a new users design, and to run DMIPS evaluation, and maybe HDL regression.
+<p>
+TODO provide FPGA scripts.
+<p>
+TODO provide HDL regression environment.
+
+<a name="ref_soc"/>
+<h2>SOC (core+RAM+Wishbone+++)</h2>
+Large design(s) for one or more chosen eval board. Features dictated by board and available IP.
+
+<a name="rams"/>
+<h2>Common - RAM models</h2>
+single (1RW), simple dual(1R+1W), true dual(1RW+1RW), and xilinx distributed dual(1RW+1R) RAM models. Parameterized depth / width, and loadable from file. The goal is that ROM be independent of verilog/VHDL implementation of RAM.
+<p>
+TODO RAM model contribution needed. What is in opencore/common is not adequate.
+
+<a name="wishbone"/>
+<h2>Common - Wishbone</h2>
+In <a href="../hdl/wishbone" target="_blank">hdl/wishbone</a> there is an implementation
+of a wishbone bridge. It was designed to work with <a href="#zy2000">ZY2000</a>
+<p>
+TODO make wishbone bridge re-usable with all cores
+
+<a name="uart"/>
+<h2>Common - UART</h2>
+
+All self respecting embedded projects should have a debug channel
+to print stuff to. Typically this is a standard RS232 or UART, but
+it can also be something more exotic like a DCC JTAG channel.
+<p>
+The point is that characters(bytes) are sent to/from the ZPU
+via some terminal.
+<p>
+The ZPU defines in the memory map a UART / debug channel. This
+should be implemented by some suitable debug channel for
+the device in which the ZPU is implemented.
+<p>
+www.opencores.org has several UART implementations. This is one
+of the simpler ones:
+
+<a href="http://www.opencores.org/projects.cgi/web/uart/overview">
+http://www.opencores.org/projects.cgi/web/uart/overview</a>
+<h3>Implementing your own UART / debug channel</h3>
+The first thing you need to do is to choose a debug channel for your
+hardware. This could be a UART, but it doesn't have to be.
+<p>
+Secondly you should write a small HDL module that interface between
+the ZPU memory map of debug channel to the UART. This should
+ be relatively simple as all you need to do is to let the ZPU
+ query the FIFO in/out for busy flag and allow the ZPU to read/write
+ data to the UART via the memory map.
+
+<p>
+TODO explicit example with UART from opencores in the above ref designs.
+
+<!-- SPI controller -->
+<a name="spicontroller">
+<h2>SPI flash controller (read-only)</h2>
+This is a simple read-only SPI flash controller, with the following characteristics:
+
+<dl>
+ <li>Fast-READ only implementation.
+ <li>32-bit only access
+ <li>Fast sequential read access - Uses low-clock approach</li>
+</dl>
+
+<h3>Version</h3>
+The current version is 1.2. This is also the first public version available.
+
+<h3>Timing overview</h3>
+
+<p>Simple timing overview, with one nonsequential access to address 0x0, followed by a sequential access to address 0x4.
+This simulation was done with Xilinx tools, after post-routing, and using a ZPU to access the SPI</p>
+<div>
+<img src="images/spi_timing_overview.png">
+</a>
+<p>Image 1: Timing overview</p>
+</div>
+
+On Image 2, you can see the clock almost perfectly centered on data, when we write to the SPI flash.
+
+<div>
+<img src="images/spi_readfast_timing.png">
+<p>Image 2: Issuing commands to the SPI</p>
+</div>
+
+As you can see from Image 3, I assume the worst-case read delay from SPI (which is 15ns, as you can see from the marker).
+
+<div>
+<img src="images/spi_read_timing.png">
+<p>Image 3: Reading from the SPI</p>
+</div>
+
+<h3>Usage</h3>
+
+Simple description of SPI controller interface:
+
+<table border="1">
+<tr>
+ <th>Symbol</th>
+ <th>Direction</th>
+ <th>Bit width</th>
+ <th>Purpose</th>
+</tr>
+<tr><td>adr</td><td>Input</td><td>24</td><td>Address where to read from SPI</td></tr>
+<tr><td>dat_o</td><td>Output</td><td>32</td><td>Data read from SPI</td></tr>
+<tr><td>clk</td><td>Input</td><td>1</td><td>Input clock. Used for both interface and SPI</td></tr>
+<tr><td>ce</td><td>Input</td><td>1</td><td>Chip Enable</td></tr>
+<tr><td>rst</td><td>Input</td><td>1</td><td>Asynchronous reset</td></tr>
+<tr><td>ack</td><td>Output</td><td>1</td><td>Data valid ACK</td></tr>
+<tr><td>SPI_CLK</td><td>Output</td><td>1</td><td>SPI output clock</td></tr>
+<tr><td>SPI_MOSI</td><td>Output</td><td>1</td><td>SPI output data from controller to chip</td></tr>
+<tr><td>SPI_MISO</td><td>Input</td><td>1</td><td>SPI input data from chip to controller</td></tr>
+<tr><td>SPI_SELN</td><td>Output</td><td>1</td><td>SPI nSEL (deselect, active low) signal</td></tr>
+</table>
+
+<h3>License</h3>
+The Verilog implementation is released under BSD license. See the file itself for more licensing details.
+
+<h3>Dowload</h3>
+Download the Verilog code here: <a href="/files/electronics/spi/spi_controller.v">spi_controller.v</a>
+
+<h3>Troubleshooting</h3>
+The current implementation is timed and optimized for myself. Your parameters might not be the same
+as those I defaulted, so read the code carefully. If you have any issue let me know.
+
+
+
+
+<hr> <!-- +++++++++++++++++++++++++++++++++++++++++++++++++++++ -->
+
+<a name="tools"/>
+<h1>Working with the tools and core</h1>
+TODO discussion of tools needed and choose some to be supported by project. Need to deal with cygwin vs linux, VHDL vs verilog, open vs closed.... plus language support in simulators is sometimes lacking.
+<p>
+Xilinx ISE webpack is available for windows and linux
+<br>
+Altera Quartus web edition is windows only.
+<br>
+Lattice ispLEVER starter edition is windows only.
+<p>
+None appear to come with a standalone simulator anymore. Not sure if any built in simulators are worth looking at... never have been in the past.
+
+<p>
+Popular Simulation tools for this kind of project: Modelsim, GHDL, veriwell, cver, icarus, gtkwave... others?
+<p>
+
+<a name="setuplinux"/>
+<h2>Setup - Linux toolchain</h2>
+You will need Java installed to run the simulator and some other stuff.
+<p>
+TODO setup.sh script needs to detect linux/cygwin, and should have install path option.
+<pre>
+$ cd zpu/zpu/sw # path as appropriate
+$ sh setup.sh # untars the tool chain to ... TODO
+$ . env.sh # puts the tools in you path
+</pre>
+
+<a name="setupcygwin"/>
+<h2>Setup - Cygwin toolchain</h2>
+Install <a href="http://www.cygwin.com">Cygwin</a>
+You will need Java installed to run the simulator and some other stuff.
+<pre>
+$ cd zpu/zpu/sw # path as appropriate
+$ sh setup.sh # unzips the tool chain to /tmp/zpu/install/bin
+$ . env.sh # puts the tools in you path
+</pre>
+
+<a name="gcc2ram"/>
+<h2>GCC to RAM</h2>
+TODO some of this is generic, some is zpu4 specific. Should move to refdesign section when ref designs exist.
+<p>
+The instructions are stored big endian. That is the first instruction is stored in the most significant byte, and the forth is in the least significant byte.
+<p>
+<h3>Generating VHDL BRAM initialization </h3>
+<pre>
+$ zpu-elf-objcopy -O binary hello.elf hello.bin
+$ java -classpath ../simulator/zpusim.jar com.zylin.zpu.simulator.tools.MakeRam hello.bin &gt;hello.bram
+</pre>
+<h3>Build another test application for example simulation</h3>
+Here is how to build a rom image for an application using the
+zpu/example simulation files.
+<pre>
+$ cd zpu/roadshow/roadshow/dhrystone
+$ sh build.sh
+$ cd zpu/hdl/example
+$ gcc zpuromgen.c
+$ ./a
+Usage: ./a binary_file
+$ ./a ../../roadshow/roadshow/dhrystone/dhrystone.bin >app.txt
+</pre>
+Copy and paste app.txt into helloworld.vhd.
+
+<p>
+TODO need to merge following with above.
+<p>
+
+The ZPU comes with a standard GCC toolchain and an instruction set simulator. This allows compiling, running & debugging simple test programs. The Simulator has
+some very basic peripherals defined: counter, timer interrupt and a debug output port.
+
+<h3>Hello world example</h3>
+The ZPU toolchain comes with newlib & libstdc++ support which means that many C/C++ programs can be compiled without modification.
+<p>
+<pre>
+$ cd zpu/sw/helloworld
+$ zpu-elf-gcc -Os -phi hello.c -o hello.elf -Wl,--relax -Wl,--gc-sections
+or ? TODO which one
+$ zpu-elf-gcc -phi hello.c -o hello.elf
+$ zpu-elf-size hello.elf
+</pre>
+
+
+<a name="hdlsim"/>
+<h2>HDL simulation (ZPU4)</h2>
+TODO some of this is generic, some is zpu4 specific. Should move to refdesign section when ref design exists.
+<p>
+For new users you will also find scripts in the zealot area that may be useful.
+<p>
+You'll find a working simulation script in hdl/example/simzpu_small.do and hdl/example_medium/simzpu_medium.do, which
+show simulation of the small(zpu_core_small.vhd) and medium sized ZPU(zpu_core.vhd). hdl/example/simzpu_interrupt.do
+shows use of interrupts.
+<p>
+When implementing the ZPU, copy the following files and modify them to your needs:
+<ol>
+ <li>hdl/example/zpu_config.vhd - set up RAM size here
+ <li>hdl/example/helloworld.vhd - dual port BRAM implementation.
+</ol>
+Obviously you must also connect the ZPU to the rest of your IO subsystem. IO is memory mapped(read/write) in the ZPU.
+
+<h3>Running example simulation</h3>
+The hdl/example directory has a simulation written for Xilinx WebPack ModelSim. From the ModelSim command prompt:
+<ol>
+<li>cd c:/&lt;installfolder&gt;/hdl/example
+<li>do zpusim_small.do
+</ol>
+<p>
+After running the hello world simulation (see zpusim.do), two files are written to the hdl/example directory:
+<ol>
+<li>log.txt - contains the "Hello world!" text written to the debug channel/simplified UART.
+<li>trace.txt - a trace file for the CPU. The instruction set simulator has the capability of taking
+this file as input in order to verify that the HDL implementation matches the instruction set simulator.
+When a mismatch is found, the GDB debugger will break. Very handy for debugging custom ZPU implementations.
+</ol>
+
+
+<a name="gdbsim"/>
+<h2>GDB simulation</h2>
+<ol>
+<li>cd zpu/sw/helloworld
+<li>Launch the simulator from a seperate bash shell:<p>
+java -classpath ../simulator/zpusim.jar -Xmx512m com.zylin.zpu.simulator.Phi 4444
+<p>
+<img src="images/zpusim.PNG" border=0>
+<li>Launch GDB:<p>
+../install/bin/zpu-elf-gdb hello.elf
+<li>Connect to target, load and run application:<p>
+<pre>
+(gdb) target remote localhost:4444<br>
+(gdb) load<br>
+(gdb) continue<br>
+</pre>
+<p>
+<img src="images/gccgdb.PNG">
+
+</ol>
+
+
+<a name="simulator"/>
+<h1>Simulator</h1>
+<P>The ZPU simulator is integrated into the Zylin Embedded CDT plugin
+to ease debugging of ZPU applications:</P>
+<P><A HREF="http://www.zylin.com/embeddedcdt.html">http://www.zylin.com/embeddedcdt.html</A></P>
+<P>The ZPU simulator has many features besides debugging an
+application:</P>
+<UL>
+ <LI><P STYLE="margin-bottom: 0in">taking output from simulation(e.g.
+ ModelSim) and matching that against the Java simulator, thus making
+ it much easier to debug HDL implementations and also getting real
+ world timing information
+ </P>
+ <LI><P STYLE="margin-bottom: 0in">can generate gprof output
+ </P>
+ <LI><P>generate various statistics
+ </P>
+</UL>
+<P>The plugin is still pretty rough around the edges, and needs to
+get GUI support for enabling the ModelSim trace input feature.</P>
+<P ALIGN=CENTER><IMG SRC="images/compile.PNG" NAME="graphics7" ALIGN=BOTTOM WIDTH=669 HEIGHT=302 BORDER=0><BR><I>Compiling
+ZPU application</I></P>
+<P ALIGN=CENTER><IMG SRC="images/simulator.PNG" NAME="graphics9" ALIGN=BOTTOM WIDTH=722 HEIGHT=583 BORDER=0><BR><I>Setting
+up the simulator</I></P>
+<P ALIGN=CENTER><IMG SRC="images/simulator2.PNG" NAME="graphics11" ALIGN=BOTTOM WIDTH=722 HEIGHT=583 BORDER=0><BR><I>Choosing
+ZPU executable</I></P>
+<P ALIGN=CENTER STYLE="margin-bottom: 0in"><IMG SRC="images/simulator3.PNG" NAME="graphics13" ALIGN=BOTTOM WIDTH=1100 HEIGHT=720 BORDER=0><BR><I>Debug
+session</I></P>
+<P STYLE="margin-bottom: 0in"><BR>
+</P>
+
+
+<hr> <!-- +++++++++++++++++++++++++++++++++++++++++++++++++++++ -->
+
+<a name="misc"/>
+<h1>Misc</h1>
+TODO Stuff that could probably find a better home.
+
+<a name="tuning"/>
+<h2>Speeding up the ZPU</h2>
+There are two aspects of speeding up the ZPU: making it perform better
+for a particular application and toying around with the ZPU architecture.
+<h3>Performance tips</h3>
+<ol>
+<li>Profile. Create a small sample and run in a simulator that is as close
+to the real deployment as possible. zpu4/core/histogram.perl is a script
+that will tell you which instructions take the most time.
+<li> Using the profile output, decide on which emulated instructions that
+it makes sense to implement in HDL for your particular application. Modifying
+zpu_core_small.vhd is not particularly hard. Most instructions can be
+transliterated into zpu_core_small.vhd from zpu_core.vhd without too much
+problem.
+<li>The memory subsystem may well turn out to be where you should concentrate
+your efforts.
+</ol>
+<h3>Toying around with the architecture</h3>
+Again: profile 90% of the time and spend the remaining 10% tinkering
+with the architecture.
+<ul>
+<li>There is a DMIPS program you can use to measure the performance of
+the ZPU in lieu of profiling a real application. The latter is obviously
+a superior solution.
+<li>Again: use histogram.perl to figure out which instructions you should add
+in HDL.
+<li>Tinker a bit with Fmax to find the maximum speed rating for your design.
+<li>zpu_core_small.vhd should be ca. 1 DMIPS and zpu_core.vhd should yield
+about 5-10 DMIPS before adding instructions runs out of steam.
+</ul>
+If you need to get ca. 20-50 DMIPS out of the ZPU you will have to
+write a heavily pipelined architecture with caches(if you are running
+against DRAM). This is *tricky*, but some proof of concept work was
+done to show 20 DMIPS w/the ZPU(the actual result was discarded since
+it was not complete and contained fatal flaws).
+<p>
+Achieving above 50-100 DMIPS with the current ZPU architecture is probably
+a non-starter and a more conventional RISC design makes more sense here.
+<p>
+The unique advantages of the ZPU is size in terms of HDL & code size.
+
+
+
+<a name="codesize"/>
+<h2>Optimizing for code size</h2>
+The ZPU toolchain produces highly compact code.
+<ol>
+<li>Since the ZPU GCC toolchain supports standard ANSI C, it is easy to stumble across
+functionality that takes up a lot of space. E.g. the standard printf() function is a beast. Some compilers drop e.g. floating point support
+from the printf() function and thus boast a "smaller" printf() when in fact they have a non-standard printf(). newlib has a standard printf() function
+and an alternative iprintf() function that works only on integers.
+<li>The ZPU ships with default startup code that works across various configurations of the ZPU, so be warned that there is some overhead that will
+not occur in the final application(anywhere between 1-4kBytes).
+<li>Compilation and linker options matter. The ZPU benefits greatly from the "-Wl,--relax -Wl,--gc-sections" options which is not used by
+all architectures(e.g. GCC ARM does not implement/need -Wl,--relax).
+</ol>
+<h3>Small code example</h3>
+<code>
+zpu-elf-gcc -Os -abel smallstd.c -o smallstd.elf -Wl,--relax -Wl,--gc-sections<br>
+zpu-elf-size small.elf<br>
+<br>
+$ zpu-elf-size small.elf<br>
+ text data bss dec hex filename<br>
+ 2845 952 36 3833 ef9 small.elf<br>
+<br>
+</code>
+
+<h3>Even smaller code example</h3>
+If the ZPU implements the optional instructions, the RAM overhead can be reduced significantly.
+<p>
+<code>
+zpu-elf-gcc -Os -abel crt0_phi.S small.c -o small.elf -Wl,--relax -Wl,--gc-sections -nostdlib <br>
+zpu-elf-size small.elf<br>
+<br>
+$ zpu-elf-size small.elf<br>
+ text data bss dec hex filename<br>
+ 56 8 0 64 40 small.elf<br>
+ <br>
+</code>
+
+<a name="ecos"/>
+<h2>Installing eCos build tools</h2>
+<code>
+tar -xjvf ecossnapshot.tar.bz2<br>
+tar -xjvf repository.tar.bz2<br>
+tar -xjvf ecostools.tar.bz2<br>
+# run this every time you open the shell<br>
+export PATH=$PATH:`pwd`/ecos-install<br>
+export ECOS_REPOSITORY=`pwd`/ecos/packages:`pwd`/repository<br>
+</code>
+<h3>Compiling eCos tests</h3>
+<code>
+ecosconfig new phi default<br>
+ecosconfig tree<br>
+make<br>
+cd kernel/current<br>
+make tests<br>
+</code>
+
+<h2>Code size ZPU</h2>
+<pre>
+$ zpu-elf-size *
+ text data bss dec hex filename
+ 15761 1504 12060 29325 728d bin_sem0
+ 16907 1512 14436 32855 8057 bin_sem1
+ 17105 1524 30032 48661 be15 bin_sem2
+ 17186 1512 14436 33134 816e bin_sem3
+ 18986 1500 12036 32522 7f0a clock0
+ 15812 1504 13236 30552 7758 clock1
+ 25095 1972 13224 40291 9d63 clockcnv
+ 16437 1500 13224 31161 79b9 clocktruth
+ 15762 1504 12060 29326 728e cnt_sem0
+ 17124 1512 14436 33072 8130 cnt_sem1
+ 35947 1564 22512 60023 ea77 dhrystone
+ 16428 1500 13228 31156 79b4 except1
+ 15751 1504 12052 29307 727b flag0
+ 19145 1512 15624 36281 8db9 flag1
+ 20053 1516 102908 124477 1e63d fptest
+ 15998 1496 12092 29586 7392 intr0
+ 16080 1496 12200 29776 7450 kalarm0
+ 15327 1496 12036 28859 70bb kcache1
+ 15549 1496 13224 30269 763d kcache2
+ 18291 1500 12260 32051 7d33 kclock0
+ 16231 1500 13232 30963 78f3 kclock1
+ 16572 1496 13228 31296 7a40 kexcept1
+ 15618 1496 12060 29174 71f6 kflag0
+ 19287 1500 15624 36411 8e3b kflag1
+ 16887 1516 15628 34031 84ef kill
+ 16186 1496 12128 29810 7472 kintr0
+ 19724 1504 14516 35744 8ba0 klock
+ 18283 1500 14592 34375 8647 kmbox1
+ 15539 1496 12064 29099 71ab kmutex0
+ 16524 1504 15664 33692 839c kmutex1
+ 18272 1712 20348 40332 9d8c kmutex3
+ 18682 1608 20352 40642 9ec2 kmutex4
+ 15619 1496 14412 31527 7b27 ksched1
+ 15567 1496 12060 29123 71c3 ksem0
+ 17063 1500 14436 32999 80e7 ksem1
+ 15504 1496 13228 30228 7614 kthread0
+ 16167 1496 14412 32075 7d4b kthread1
+ 18281 1512 14580 34373 8645 mbox1
+ 20611 1508 14940 37059 90c3 mqueue1
+ 15672 1504 12064 29240 7238 mutex0
+ 16678 1516 15664 33858 8442 mutex1
+ 17694 1508 16868 36070 8ce6 mutex2
+ 18203 1720 20344 40267 9d4b mutex3
+ 16352 1508 14428 32288 7e20 release
+ 15890 1500 14412 31802 7c3a sched1
+ 44196 1612 286332 332140 5116c stress_threads
+ 17891 1524 16864 36279 8db7 sync2
+ 16943 1512 15644 34099 8533 sync3
+ 15467 1496 13064 30027 754b thread0
+ 16134 1496 14420 32050 7d32 thread1
+ 17560 1512 15636 34708 8794 thread2
+ 16279 1500 24028 41807 a34f thread_gdb
+ 17051 1504 20376 38931 9813 timeslice
+ 17146 1504 21564 40214 9d16 timeslice2
+ 37313 1512 422380 461205 70995 tm_basic
+</pre>
+<h3>Code size ARM (non-thumb)</h3>
+Thumb does not compile out of the box w/AT91 EB40a for which this test was made.<p>
+<pre>
+$ arm-elf-size *
+ text data bss dec hex filename
+ 25204 692 16976 42872 a778 bin_sem0
+ 26644 700 22096 49440 c120 bin_sem1
+ 26996 712 55584 83292 1455c bin_sem2
+ 27008 700 22100 49808 c290 bin_sem3
+ 28992 688 16944 46624 b620 clock0
+ 25456 692 19532 45680 b270 clock1
+ 34572 1160 19520 55252 d7d4 clockcnv
+ 26224 688 19508 46420 b554 clocktruth
+ 25204 692 16976 42872 a778 cnt_sem0
+ 26888 700 22108 49696 c220 cnt_sem1
+ 44180 752 27416 72348 11a9c dhrystone
+ 26088 688 19520 46296 b4d8 except1
+ 25236 692 16968 42896 a790 flag0
+ 29532 700 24668 54900 d674 flag1
+ 29508 704 109652 139864 22258 fptest
+ 25932 684 17016 43632 aa70 intr0
+ 25824 684 17112 43620 aa64 kalarm0
+ 24728 684 16956 42368 a580 kcache1
+ 25168 684 19512 45364 b134 kcache2
+ 28112 688 17168 45968 b390 kclock0
+ 25976 688 19524 46188 b46c kclock1
+ 26372 684 19512 46568 b5e8 kexcept1
+ 25140 684 16968 42792 a728 kflag0
+ 29824 688 24660 55172 d784 kflag1
+ 26896 704 24656 52256 cc20 kill
+ 26088 684 17028 43800 ab18 kintr0
+ 30812 692 22176 53680 d1b0 klock
+ 28504 688 22260 51452 c8fc kmbox1
+ 24984 684 16984 42652 a69c kmutex0
+ 26504 692 24704 51900 cabc kmutex1
+ 28792 900 34892 64584 fc48 kmutex3
+ 29264 796 34896 64956 fdbc kmutex4
+ 25240 684 22084 48008 bb88 ksched1
+ 25044 684 16968 42696 a6c8 ksem0
+ 26988 688 22100 49776 c270 ksem1
+ 25028 684 19512 45224 b0a8 kthread0
+ 25996 684 22080 48760 be78 kthread1
+ 28552 700 22252 51504 c930 mbox1
+ 31324 696 22612 54632 d568 mqueue1
+ 25108 692 16980 42780 a71c mutex0
+ 26464 704 24700 51868 ca9c mutex1
+ 27624 696 27280 55600 d930 mutex2
+ 28596 908 34884 64388 fb84 mutex3
+ 26156 696 22100 48952 bf38 release
+ 25460 688 22084 48232 bc68 sched1
+ 56356 828 45892 103076 192a4 stress_threads
+ 27900 712 27288 55900 da5c sync2
+ 26760 700 24692 52152 cbb8 sync3
+ 24924 684 19356 44964 afa4 thread0
+ 25868 684 22084 48636 bdfc thread1
+ 27452 700 24680 52832 ce60 thread2
+ 26136 688 42704 69528 10f98 thread_gdb
+ 27212 692 34916 62820 f564 timeslice
+ 52728 700 123332 176760 2b278 tm_basic
+</pre>
+
+<a name="memorymap"/>
+<h2>Phi memory map</h2>
+TODO This probably belongs in the refdesign section. For now leaving it here because zealot refers to it. Not sure what else uses it.
+<p>
+The ZPU architecture does not define a memory map as such, but the GCC + libgloss + ecos hal library uses the
+memory map below. "Phi" is just a three letter word for the particular memory layout below that came about
+while developing the ZPU.
+<p>
+ <TABLE WIDTH=604 BORDER=1 BORDERCOLOR="#000000" CELLPADDING=7 CELLSPACING=0 STYLE="page-break-after: avoid">
+ <COL WIDTH=85>
+ <COL WIDTH=42>
+ <COL WIDTH=136>
+ <COL WIDTH=283>
+ <TR VALIGN=TOP>
+ <TD WIDTH=85>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2><B>Address</B></FONT></FONT></P>
+ </TD>
+ <TD WIDTH=42>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2><B>Type</B></FONT></FONT></P>
+ </TD>
+ <TD WIDTH=136>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2><B>Name</B></FONT></FONT></P>
+ </TD>
+ <TD WIDTH=283>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2><B>Description</B></FONT></FONT></P>
+ </TD>
+ </TR>
+
+ <TR VALIGN=TOP>
+ <TD WIDTH=85>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">0x080A0000</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=42>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Write</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=136>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">ZPU
+ enable</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=283>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Bit
+ [31:1] Not used</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Bit
+ [0] Enable ZPU operations</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt"> 0 ZPU
+ is held in Idle mode</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt"> 1 ZPU
+ running</FONT></FONT></P>
+ </TD>
+ </TR>
+
+
+ <TR VALIGN=TOP>
+ <TD WIDTH=85>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">0x080A0004</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=42>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Read/</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Write</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=136>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">GPIO data</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=283>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Bit [31:0] input data 31:0</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Bit [31:0] output data 31:0</FONT></FONT></P>
+ </TD>
+ </TR>
+
+ <TR VALIGN=TOP>
+ <TD WIDTH=85>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">0x080A0008</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=42>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Read/</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Write</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=136>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">GPIO direction</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=283>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Bit [31:0] data direction 31:0</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">0 output</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">1 input (default)</FONT></FONT></P>
+ </TD>
+ </TR>
+
+ <TR VALIGN=TOP>
+ <TD WIDTH=85>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">0x080A000C</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=42>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Read/</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Write</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=136>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">ZPU
+ Debug channel / UART to ARM7 TX</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt"><B>NOTE!
+ ZPU side</B></FONT></FONT></P>
+ </TD>
+ <TD WIDTH=283>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Bit
+ [31:9] Not used</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Bit
+ [8] TX buffer ready (valid on ready)</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt"> 0 TX
+ buffer not ready (full)</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt"> 1 TX
+ buffer ready</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Bit
+ [7:0] TX byte (valid on write)</FONT></FONT></P>
+ </TD>
+ </TR>
+ <TR VALIGN=TOP>
+ <TD WIDTH=85>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">0x080A0010</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=42>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Read</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=136>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">ZPU
+ Debug channel / UART to ARM7 RX</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt"><B>NOTE!
+ ZPU side</B></FONT></FONT></P>
+ </TD>
+ <TD WIDTH=283>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Bit
+ [31:9] Not used</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Bit
+ [8] RX buffer data valid</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt"> 0 RX
+ buffer not valid</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt"> 1 RX
+ buffer valid</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Bit
+ [7:0] RX byte (when valid)</FONT></FONT></P>
+ </TD>
+ </TR>
+ <TR VALIGN=TOP>
+ <TD WIDTH=85>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">0x080A0014</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=42>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Read/</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Write</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=136>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Counter(1)</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=283>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Bit
+ [0] Reset counter (valid for write)</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt"> 0 N/A</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt"> 1 Reset
+ counter</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Bit
+ [1] Sample counter (valid for write)</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt"> 0 N/A</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt"> 1 Sample
+ counter</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Bit
+ [31:0] Counter bit 31:0</FONT></FONT></P>
+ </TD>
+ </TR>
+ <TR VALIGN=TOP>
+ <TD WIDTH=85>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">0x080A0018</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=42>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Read</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=136>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Counter(2)</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=283>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Bit
+ [31:0] Counter bit 63:32</FONT></FONT></P>
+ </TD>
+ </TR>
+ <TR VALIGN=TOP>
+ <TD WIDTH=85>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">0x080A0020</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=42>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Read
+ / Write</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=136>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Global_Interrupt_mask</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=283>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Bit
+ [31:1] Not used</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Bit
+ [0] Global intr. Mask</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt"> 0 Interrupts
+ enabled</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt"> 1 Interrupts
+ disabled</FONT></FONT></P>
+ </TD>
+ </TR>
+ <TR VALIGN=TOP>
+ <TD WIDTH=85>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">0x080A0024</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=42>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Write</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=136>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">UART_INTERRUPT_ENABLE</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=283>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Bit
+ [31:1] Not used</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Bit
+ [0] Debug channel / UART RX interrupt enable</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt"> 0 Interrupt
+ disable</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt"> 1 Interrupt
+ enable</FONT></FONT></P>
+ </TD>
+ </TR>
+ <TR VALIGN=TOP>
+ <TD WIDTH=85>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">0x080A0028</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=42>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Read</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Write</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=136>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">UART_interrupt</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=283>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Bit
+ [31:1] Not used</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Bit
+ [0] Debug channel / UART RX interrupt pending (Read)</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt"> 0 No
+ interrupt pending</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt"> 1 Interrupt
+ pending</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Bit
+ [0] Clear UART interrupt (Write)</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt"> 0 N/A</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt"> 1 Interrupt
+ cleared</FONT></FONT></P>
+ </TD>
+ </TR>
+ <TR VALIGN=TOP>
+ <TD WIDTH=85>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">0x080A002C</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=42>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Write</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=136>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Timer_Interrupt_enable</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=283>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Bit
+ [31:1] Not used</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Bit
+ [0] Timer interrupt enable</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt"> 0 Interrupt
+ disable</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt"> 1 Interrupt
+ enable</FONT></FONT></P>
+ </TD>
+ </TR>
+ <TR VALIGN=TOP>
+ <TD WIDTH=85>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">0x080A0030</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=42>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Read
+ /</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Write</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=136>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Timer_interrupt</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=283>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Bit
+ [31:2] Not used</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Bit
+ [0] Timer interrupt pending (Read)</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt"> 0 No
+ interrupt pending</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt"> 1 Interrupt
+ pending</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Bit
+ [1] Reset Timer counter (Write)</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt"> 0 N/A</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt"> 1 Timer
+ counter reset</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Bit
+ [0] Clear Timer interrupt (Write)</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt"> 0 N/A</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt"> 1 Interrupt
+ cleared</FONT></FONT></P>
+ </TD>
+ </TR>
+ <TR VALIGN=TOP>
+ <TD WIDTH=85>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">0x080A0034</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=42>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Write</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=136>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Timer_Period</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=283>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Bit
+ [31:0] Interrupt period (write)</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt"> Number
+ of clock cycles</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt"> between
+ timer interrupts</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt"><B>NOTE!
+ </B>The timer will start at Timer_Periode value and count <B>down</B>
+ to zero, and generate an interrupt</FONT></FONT></P>
+ </TD>
+ </TR>
+ <TR VALIGN=TOP>
+ <TD WIDTH=85>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">.0x080A0038</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=42>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Read</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=136>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Timer_Counter</FONT></FONT></P>
+ </TD>
+ <TD WIDTH=283>
+ <P LANG="en-US" CLASS="western"><FONT FACE="Arial, sans-serif"><FONT SIZE=2 STYLE="font-size: 9pt">Bit
+ [31:0] Timer counter (read)</FONT></FONT></P>
+ <P LANG="en-US" CLASS="western"><BR>
+ </P>
+ </TD>
+ </TR>
+ <TR VALIGN=TOP>
+ <TD WIDTH=85>
+ <P LANG="en-US" CLASS="western"><BR>
+ </P>
+ </TD>
+ <TD WIDTH=42>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><BR>
+ </P>
+ </TD>
+ <TD WIDTH=136>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><BR>
+ </P>
+ </TD>
+ <TD WIDTH=283>
+ <P LANG="en-US" CLASS="western"><BR>
+ </P>
+ </TD>
+ </TR>
+ <TR VALIGN=TOP>
+ <TD WIDTH=85>
+ <P LANG="en-US" CLASS="western"><BR>
+ </P>
+ </TD>
+ <TD WIDTH=42>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><BR>
+ </P>
+ </TD>
+ <TD WIDTH=136>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><BR>
+ </P>
+ </TD>
+ <TD WIDTH=283>
+ <P LANG="en-US" CLASS="western"><BR>
+ </P>
+ </TD>
+ </TR>
+ <TR VALIGN=TOP>
+ <TD WIDTH=85>
+ <P LANG="en-US" CLASS="western"><BR>
+ </P>
+ </TD>
+ <TD WIDTH=42>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><BR>
+ </P>
+ </TD>
+ <TD WIDTH=136>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><BR>
+ </P>
+ </TD>
+ <TD WIDTH=283>
+ <P LANG="en-US" CLASS="western"><BR>
+ </P>
+ </TD>
+ </TR>
+ <TR VALIGN=TOP>
+ <TD WIDTH=85>
+ <P LANG="en-US" CLASS="western"><BR>
+ </P>
+ </TD>
+ <TD WIDTH=42>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><BR>
+ </P>
+ </TD>
+ <TD WIDTH=136>
+ <P LANG="en-US" CLASS="western" ALIGN=CENTER><BR>
+ </P>
+ </TD>
+ <TD WIDTH=283>
+ <P LANG="en-US" CLASS="western"><BR>
+ </P>
+ </TD>
+ </TR>
+ </TABLE>
+
+<hr> <!-- +++++++++++++++++++++++++++++++++++++++++++++++++++++ -->
+
+<a name="todo"/>
+<h1>TODO</h1>
+
+<a name="todolist"/>
+<h2>TODO list</h2>
+<ul>
+<li>fix the TODO in this doc that are just doc fixes
+<li>organize the TODO list by priority and assign responsibility... if there are takers.
+<li>converge on a single IO for core implementations.
+<li>fill in performance table for Altera and Lattice.
+<li>re-org CVS to make it easy to keep appropriate SW, RTL(verilog and VHDL) , scripts, verification stuff together. separation of tools, core, common, and ref design
+<li>provide FPGA scripts.
+<li>provide HDL regression environment.
+<li>RAM model contribution needed. What is in opencore/common is not adequate.
+<li>make wishbone bridge re-usable with all cores
+<li>explicit example with UART from opencores in the above ref designs.
+<li>discussion of tools needed and choose some to be supported by project. Need to deal with cygwin vs linux, VHDL vs verilog, open vs closed.... plus language support in simulators is sometimes lacking.
+<li>setup.sh script needs to detect linux/cygwin, and should have install path option.
+<li>shaping up the www.opencores.org pages.
+<li>BSD and GPL licenses in the appropriate places.
+<li>Currently there exists some pages at <A HREF="http://www.zylin.com/zpu.htm">http://www.zylin.com/zpu.htm</A> that explains about the ZPU. According to OpenCores policy this information should be moved to www.opencores.org. Patches gratefully accepted to do so!
+<li>eCos HAL could be less RAM hungry
+<li>Needs GDB stub support in eCos
+<li>Could do with a Verilog implementation(ca. 600 lines to translate)
+<li>Make little endian throughout. Currently instructions are stored big endian, loadb and storeb are big endian, but the data bus is treated as little endian. Creates some problems in type conversion.
+</ul>
+
+<a name="repository"/>
+<h2>Repository Re-org</h2>
+I am proposing the following structure for the repository. It follows somewhat the way I've organized this document with seperation of core, common, and three SOC ref designs. New users go straight to the SOC that best matches their needs.
+<pre>
+zpu/bin # scripts and toolchain? Want toolchain installed with project. Tidier when working in multi user / multi project environment
+zpu/doc #
+zpu/core/rtl # RTL for the various core implementations.
+zpu/core/sw # crt0.s ?
+zpu/common/rtl # Re-use RTL such as RAM and UART
+zpu/common/sim # Re-use RTL and tools for regresion testing
+zpu/common/sw # ?
+zpu/soc/minimal # Three levels of ref designs described above
+ /basic
+ /board
+zpu/soc/*/rtl # top level, arbiter, etc
+zpu/soc/*/sw # helloworld, dmips, etc. makefile/ROMS
+zpu/soc/*/sim # regression test area. makefile/scripts
+zpu/soc/*/fpga # syn and par area. makefile/scripts
+zpu/tools # zip/tarball of tool chains, simulator
+</pre>
+Not sure where ecos fits.
+
+<a name="nextgen"/>
+<h2>Next generation ZPU</h2>
+Based on feedback here is a list of a tenuous "consensus" for the next generation
+of the ZPU with some tentative ideas on implementation.
+<h3>Goals</h3>
+<ol>
+<li>Reduce minimum code size footprint, i.e. BRAM code overhead. Non-trivial
+usable applications in 4kBytes of BRAM (single BRAM block).
+<li>Reduce minimum FPGA logic footprint by 20% or more. Goal &lt;300 LUT for
+32 bit ZPU
+<li>Weed out unnecessary ZPU variations and merge in useful
+features to a few recommeneded ZPU implementations.
+<li>Will someone be willing to contribute a heavily pipelined ZPU?
+Performance goal of 10 DMIPS w/DRAM & cache.
+This ZPU could run a TCP/IP stack with relevant performance to compete
+with stripped down ARM7 type systems.
+</ol>
+<h2>GCC changes</h2>
+The GCC changes planned are 100% backwards compatible with default
+options. However, a raft of options will be added to disable
+functionality so as to allow study and experimentation with the
+ZPU architecture.
+<ol>
+<li>Add options that allow defining single entry for all unknown instructions. Precisely
+how unknown instructions are handled will be defined by the HDL implementation.
+Currently the GCC backend places relatively strict limitations on how unknown/emulated
+instructions are handled. This will allow HDL implementations to have
+sparser instruction set support. Also this can allow sparse implementations
+of emualted instructions. This is especially important to reduce minimal
+BRAM requirements for small applications.
+<li>GCC needs 4 "hard" registers. These are today mapped to memory. GCC
+will allow specifying what address to use or alternatively not to use
+memory mapped hard registers at all.
+<li>Strip away unused instructions from GCC and add options to GCC for not
+emitting more advanced instructions. This will e.g. convert MULT/DIV into
+function calls to libgcc and thus make it easier to determine that
+microcode is not needed.
+</ol>
+
+<a name="float"/>
+<h1>Floating point support</h1>
+The ZPU does not currently have floating point support. Feedback
+from users indicates that single precision floating point support for
+addition, multiplication and float-to-integer convesion would
+be useful for small ZPU programs that sit in a tight control
+loop. Essentially the ZPU is then measuring something, doing a
+few calculations and then modifying the control signal.
+<p>
+Such control loops can be written in fixed point math, but that
+adds to the engineering effort and reduces clarity of the software
+implementation and the performance will probably be worse than
+for a hardware floating point version.
+<h2>Pipelined floating point module</h2>
+Design needs to be nailed down.
+<b>Goals:</b>
+<ul>
+<li> 32 bit single precision floating point
+<li> FADD => add two floats
+<li> FMULT => multiply two floats
+<li> FINT => convert float to int
+</ul>
+The problem is divided into two:
+
+<ol>
+<li>One top level VHDL module for each of the operations above.
+<li>Integration into ZPU's are a separate problem that will not be
+addressed in this project.
+<li>add a memory mapped coprocessor interface to the above. This
+yields an example of a coprocessor which can be used for any
+custom calculations and allows interest to be gauged.
+</ol>
+
+Throughput:
+
+<ol>
+<li>pipelined design where throughput is one operation per cycle
+with a fixed number of cycles delay.
+<li>there is no flow control or enable signal.
+</ol>
+
+
+
+GCC support is not hard, but modifying GCC should considered after
+interest in this feature beyond a coprocessor has been gauged.
+
+<h2>VHDL module interface</h2>
+
+Patches anyone???
+
+</body>
+<html>
diff --git a/zpu/hdl/avalanche/core/zpu_core.v b/zpu/hdl/avalanche/core/zpu_core.v
new file mode 100644
index 0000000..e704fbc
--- /dev/null
+++ b/zpu/hdl/avalanche/core/zpu_core.v
@@ -0,0 +1,749 @@
+`timescale 1ns / 1ps
+`include "zpu_core_defines.v"
+
+/* MODULE: zpu_core
+ DESCRIPTION: Contains ZPU cpu
+ AUTHOR: Antonio J. Anton (aj <at> anro-ingenieros.com)
+
+REVISION HISTORY:
+Revision 1.0, 14/09/2009
+Initial public release
+
+COPYRIGHT:
+Copyright (c) 2009 Antonio J. Anton
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the "Software"), to deal in
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+of the Software, and to permit persons to whom the Software is furnished to do
+so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.*/
+
+// --------- MICROPROGRAMMED ZPU CORE ---------------
+// all signals are polled on clk rising edge
+// all signals positive
+
+module zpu_core (
+`ifdef ENABLE_CPU_INTERRUPTS
+ interrupt, // interrupt request
+`endif
+ clk, // clock on rising edge
+ reset, // reset on rising edge
+ mem_read, // request memory read
+ mem_write, // request memory write
+ mem_done, // memory operation completed
+ mem_addr, // memory address
+ mem_data_read, // data readed
+ mem_data_write, // data written
+ byte_select // byte select on memory operation
+);
+
+input clk;
+input reset;
+output mem_read;
+output mem_write;
+input mem_done;
+input [31:0] mem_data_read;
+output [31:0] mem_data_write;
+output [31:0] mem_addr;
+output [3:0] byte_select;
+`ifdef ENABLE_CPU_INTERRUPTS
+input interrupt;
+`endif
+
+wire clk;
+wire reset;
+wire mem_read;
+wire mem_write;
+wire mem_done;
+wire [31:0] mem_data_read;
+wire [31:0] mem_data_write;
+wire [31:0] mem_addr;
+`ifdef ENABLE_CPU_INTERRUPTS
+wire interrupt;
+`endif
+
+`ifdef ENABLE_BYTE_SELECT
+// ------ unaligned byte/halfword memory operations -----
+/// TODO: think rewriting into microcode or in a less resource wasting way
+
+reg [3:0] byte_select;
+wire byte_op;
+wire halfw_op;
+
+reg [31:0] mem_data_read_int; // aligned data from memory
+reg [31:0] mem_data_write_out; // write data already aligned
+wire [31:0] mem_data_write_int; // write data from cpu to be aligned
+
+// --- byte select logic ---
+always @(mem_addr[1:0] or byte_op or halfw_op)
+begin
+ casez( { mem_addr[1:0], byte_op, halfw_op } )
+ 4'b00_1_? : byte_select <= 4'b0001; // byte select
+ 4'b01_1_? : byte_select <= 4'b0010;
+ 4'b10_1_? : byte_select <= 4'b0100;
+ 4'b11_1_? : byte_select <= 4'b1000;
+ 4'b0?_0_1 : byte_select <= 4'b0011; // half word select
+ 4'b1?_0_1 : byte_select <= 4'b1100;
+ default : byte_select <= 4'b1111; // word select
+ endcase
+end
+
+// --- input data to cpu ---
+always @(mem_data_read or mem_addr[1:0] or byte_op or halfw_op)
+begin
+ casez( { mem_addr[1:0], byte_op, halfw_op } )
+ 4'b00_1_? : mem_data_read_int <= { 24'b0, mem_data_read[7:0] }; // 8 bit read
+ 4'b01_1_? : mem_data_read_int <= { 24'b0, mem_data_read[15:8] };
+ 4'b10_1_? : mem_data_read_int <= { 24'b0, mem_data_read[23:16] };
+ 4'b11_1_? : mem_data_read_int <= { 24'b0, mem_data_read[31:24] };
+ 4'b0?_0_1 : mem_data_read_int <= { 16'b0, mem_data_read[7:0], mem_data_read[15:8] }; // 16 bit read
+ 4'b1?_0_1 : mem_data_read_int <= { 16'b0, mem_data_read[23:16], mem_data_read[31:24] };
+ default : mem_data_read_int <= { mem_data_read[7:0], mem_data_read[15:8], mem_data_read[23:16], mem_data_read[31:24] }; // 32 bit access (default)
+ endcase
+end
+
+// --- output data from cpu ---
+assign mem_data_write = mem_data_write_out;
+
+always @(mem_data_write_int or mem_addr[1:0] or byte_op or halfw_op)
+begin
+ casez( {mem_addr[1:0], byte_op, halfw_op } )
+ 4'b00_1_? : mem_data_write_out <= { 24'bX, mem_data_write_int[7:0] }; // 8 bit write
+ 4'b01_1_? : mem_data_write_out <= { 16'bX, mem_data_write_int[7:0], 8'bX };
+ 4'b10_1_? : mem_data_write_out <= { 8'bX, mem_data_write_int[7:0], 16'bX };
+ 4'b11_1_? : mem_data_write_out <= { mem_data_write_int[7:0], 24'bX };
+ 4'b0?_0_1 : mem_data_write_out <= { 16'bX, mem_data_write_int[7:0], mem_data_write_int[15:8] }; // 16 bit write
+ 4'b1?_0_1 : mem_data_write_out <= { mem_data_write_int[7:0], mem_data_write_int[15:8], 16'bX };
+ default : mem_data_write_out <= { mem_data_write_int[7:0], mem_data_write_int[15:8], mem_data_write_int[23:16], mem_data_write_int[31:24] };
+ endcase
+end
+`else
+// -------- only 32 bit memory access --------
+wire [3:0] byte_select = 4'b1111; // all memory operations are 32 bit wide
+wire [31:0] mem_data_read_int; // no byte/halfword memory access by HW
+wire [31:0] mem_data_write_int; // byte and halfword memory access must be emulated
+
+// ----- reorder bytes due to MSB-LSB configuration -----
+assign mem_data_read_int = { mem_data_read[7:0], mem_data_read[15:8], mem_data_read[23:16], mem_data_read[31:24] };
+assign mem_data_write = { mem_data_write_int[7:0], mem_data_write_int[15:8], mem_data_write_int[23:16], mem_data_write_int[31:24] };
+`endif
+
+// ------ datapath registers and connections -----------
+reg [31:0] pc; // program counter (byte align)
+reg [31:0] sp; // stack counter (word align)
+reg [31:0] a; // operand (address_out, data_out, alu_in)
+reg [31:0] b; // operand (address_out)
+reg idim; // im opcode being processed
+reg [7:0] opcode; // opcode being processed
+reg [31:2] pc_cached; // cached PC
+reg [31:0] opcode_cache; // cached opcodes (current word)
+`ifdef ENABLE_CPU_INTERRUPTS
+ reg int_requested; // interrupt has been requested
+ reg on_interrupt; // serving interrupt
+ wire exit_interrupt; // microcode says this is poppc_interrupt
+ wire enter_interrupt; // microcode says we are entering interrupt
+`endif
+wire [1:0] sel_opcode = pc[1:0]; // which opcode is selected
+wire sel_read; // mux for data-in
+wire [1:0] sel_alu; // mux for alu
+wire [1:0] sel_addr; // mux for addr
+wire w_pc; // write PC
+`ifdef ENABLE_PC_INCREMENT
+ wire w_pc_increment; // write PC+1
+`endif
+wire w_sp; // write SP
+wire w_a; // write A (from ALU result)
+wire w_a_mem; // write A (from MEM read)
+wire w_b; // write B
+wire w_op; // write OPCODE (opcode cache)
+wire set_idim; // set IDIM
+wire clear_idim; // clear IDIM
+wire is_op_cached = (pc[31:2] == pc_cached) ? 1'b1 : 1'b0; // is opcode available?
+wire a_is_zero; // A == 0
+wire a_is_neg; // A[31] == 1
+wire busy; // busy signal to microcode sequencer (stalls cpu)
+
+reg [`MC_MEM_BITS-1:0] mc_pc; // microcode PC
+initial mc_pc <= `MC_ADDR_RESET-1;
+wire [`MC_BITS-1:0] mc_op; // current microcode operation
+
+// memory addr / write ports
+assign mem_addr = (sel_addr == `SEL_ADDR_SP) ? sp :
+ (sel_addr == `SEL_ADDR_A) ? a :
+ (sel_addr == `SEL_ADDR_B) ? b : pc;
+assign mem_data_write_int = a; // only A can be written to memory
+
+// ------- alu instantiation -------
+wire [31:0] alu_a;
+wire [31:0] alu_b;
+wire [31:0] alu_r;
+wire [`ALU_OP_WIDTH-1:0] alu_op;
+wire alu_done;
+
+// alu inputs multiplexors
+// constant in microcode is sign extended (in order to implement substractions like adds)
+assign alu_a = (sel_read == `SEL_READ_DATA) ? mem_data_read_int : mem_addr;
+assign alu_b = (sel_alu == `SEL_ALU_MC_CONST) ? { {25{mc_op[`P_ADDR+6]}} , mc_op[`P_ADDR+6:`P_ADDR] } : // most priority
+ (sel_alu == `SEL_ALU_A) ? a :
+ (sel_alu == `SEL_ALU_B) ? b : { {24{1'b0}} , opcode }; // `SEL_ALU_OPCODE is less priority
+
+zpu_core_alu alu(
+ .alu_a(alu_a),
+ .alu_b(alu_b),
+ .alu_r(alu_r),
+ .alu_op(alu_op),
+ .flag_idim(idim),
+ .clk(clk),
+ .done(alu_done)
+);
+
+// -------- pc : program counter --------
+always @(posedge clk)
+begin
+ if(w_pc) pc <= alu_r;
+`ifdef ENABLE_PC_INCREMENT // microcode optimization
+ else if(w_pc_increment) pc <= pc + 1; // usually pc=pc+1
+`endif
+end
+
+// -------- sp : stack pointer --------
+always @(posedge clk)
+begin
+ if(w_sp) sp <= alu_r;
+end
+
+// -------- a : acumulator register ---------
+always @(posedge clk)
+begin
+ if(w_a) a <= alu_r;
+ else if(w_a_mem) a <= mem_data_read_int;
+end
+
+// alu results over a register instead of alu result
+// in order to improve speed
+assign a_is_zero = (a == 0);
+assign a_is_neg = a[31];
+
+// -------- b : auxiliary register ---------
+always @(posedge clk)
+begin
+ if(w_b) b <= alu_r;
+end
+
+// -------- opcode and opcode_cache --------
+always @(posedge clk)
+begin
+ if(w_op)
+ begin
+ opcode_cache <= alu_r; // store all opcodes in the word
+ pc_cached <= pc[31:2]; // store PC address of cached opcodes
+ end
+end
+
+// -------- opcode : based on pc[1:0] ---------
+always @(sel_opcode or opcode_cache) // select current opcode from
+begin // the cached opcode word
+ case(sel_opcode)
+ 0 : opcode <= opcode_cache[31:24];
+ 1 : opcode <= opcode_cache[23:16];
+ 2 : opcode <= opcode_cache[15:8];
+ 3 : opcode <= opcode_cache[7:0];
+ endcase
+end
+
+// ------- idim : immediate opcode handling ----------
+always @(posedge clk)
+begin
+ if(set_idim) idim <= 1'b1;
+ else if(clear_idim) idim <= 1'b0;
+end
+
+`ifdef ENABLE_CPU_INTERRUPTS
+// ------ on interrupt status bit -----
+always @(posedge clk)
+begin
+ if(reset | exit_interrupt) on_interrupt <= 1'b0;
+ else if(enter_interrupt) on_interrupt <= 1'b1;
+end
+`endif
+
+// ------ microcode execution unit --------
+assign sel_read = mc_op[`P_SEL_READ]; // map datapath signals with microcode program bits
+assign sel_alu = mc_op[`P_SEL_ALU+1:`P_SEL_ALU];
+assign sel_addr = mc_op[`P_SEL_ADDR+1:`P_SEL_ADDR];
+assign alu_op = mc_op[`P_ALU+3:`P_ALU];
+assign w_sp = mc_op[`P_W_SP] & ~busy;
+assign w_pc = mc_op[`P_W_PC] & ~busy;
+assign w_a = mc_op[`P_W_A] & ~busy;
+assign w_a_mem = mc_op[`P_W_A_MEM] & ~busy;
+assign w_b = mc_op[`P_W_B] & ~busy;
+assign w_op = mc_op[`P_W_OPCODE] & ~busy;
+assign mem_read = mc_op[`P_MEM_R];
+assign mem_write = mc_op[`P_MEM_W];
+assign set_idim = mc_op[`P_SET_IDIM] & ~busy;
+assign clear_idim= mc_op[`P_CLEAR_IDIM] & ~busy;
+`ifdef ENABLE_BYTE_SELECT
+assign byte_op = mc_op[`P_BYTE];
+assign halfw_op = mc_op[`P_HALFWORD];
+`endif
+`ifdef ENABLE_PC_INCREMENT
+ assign w_pc_increment = mc_op[`P_PC_INCREMENT] & ~busy;
+`endif
+`ifdef ENABLE_CPU_INTERRUPTS
+ assign exit_interrupt = mc_op[`P_EXIT_INT] & ~busy;
+ assign enter_interrupt = mc_op[`P_ENTER_INT] & ~busy;
+`endif
+
+wire cond_op_not_cached = mc_op[`P_OP_NOT_CACHED]; // conditional: true if opcode not cached
+wire cond_a_zero = mc_op[`P_A_ZERO]; // conditional: true if A is zero
+wire cond_a_neg = mc_op[`P_A_NEG]; // conditional: true if A is negative
+wire decode = mc_op[`P_DECODE]; // decode means jumps to apropiate microcode based on zpu opcode
+wire branch = mc_op[`P_BRANCH]; // unconditional jump inside microcode
+
+wire [`MC_MEM_BITS-1:0] mc_goto = { mc_op[`P_ADDR+6:`P_ADDR], 2'b00 }; // microcode goto (goto = high 7 bits)
+wire [`MC_MEM_BITS-1:0] mc_entry = { opcode[6:0], 2'b00 }; // microcode entry point for opcode
+reg [`MC_MEM_BITS-1:0] next_mc_pc; // next microcode operation to be executed
+initial next_mc_pc <= `MC_ADDR_RESET-1;
+
+wire cond_branch = (cond_op_not_cached & ~is_op_cached) | // sum of all conditionals
+ (cond_a_zero & a_is_zero) |
+ (cond_a_neg & a_is_neg);
+
+assign busy = ((mem_read | mem_write) & ~mem_done) | ~alu_done; // busy signal for microcode sequencer
+
+// ------- handle interrupts ---------
+`ifdef ENABLE_CPU_INTERRUPTS
+always @(posedge clk)
+begin
+ if(reset | on_interrupt) int_requested <= 0;
+ else if(interrupt & ~on_interrupt & ~int_requested) int_requested <= 1; // interrupt requested
+end
+`endif
+
+// ----- calculate next microcode address (next, decode, branch, specific opcode, etc.) -----
+always @(reset or mc_pc or mc_goto or opcode[7:4] or idim or
+ decode or branch or cond_branch or mc_entry or busy
+`ifdef ENABLE_CPU_INTERRUPTS
+ or int_requested
+`endif
+)
+begin
+ // default, next microcode instruction
+ next_mc_pc <= mc_pc + 1;
+ if(reset) next_mc_pc <= `MC_ADDR_RESET;
+ else if(~busy)
+ begin
+ // get next microcode instruction
+ if(branch | cond_branch) next_mc_pc <= mc_goto;
+ else if(decode) // decode: entry point of a new zpu opcode
+ begin
+`ifdef ENABLE_CPU_INTERRUPTS
+ if(int_requested & ~idim) next_mc_pc <= `MC_ADDR_INTERRUPT; // microde to enter interrupt mode
+ else
+`endif
+ if(opcode[7] == `OP_IM) next_mc_pc <= (idim ? `MC_ADDR_IM_IDIM : `MC_ADDR_IM_NOIDIM);
+ else if(opcode[7:5] == `OP_STORESP) next_mc_pc <= `MC_ADDR_STORESP;
+ else if(opcode[7:5] == `OP_LOADSP) next_mc_pc <= `MC_ADDR_LOADSP;
+ else if(opcode[7:4] == `OP_ADDSP) next_mc_pc <= `MC_ADDR_ADDSP;
+ else next_mc_pc <= mc_entry; // includes EMULATE opcodes
+ end
+ end
+ else next_mc_pc <= mc_pc; // in case of cpu stalled (busy=1)
+end
+
+// set microcode program counter
+always @(posedge clk) mc_pc <= next_mc_pc;
+
+// ----- microcode program ------
+zpu_core_rom microcode (
+ .addr(next_mc_pc),
+ .data(mc_op),
+ .clk(clk)
+);
+
+// -------------- ZPU debugger --------------------
+`ifdef ZPU_CORE_DEBUG
+//synthesis translate_off
+// ---- register operation dump ----
+always @(posedge clk)
+begin
+ if(~reset)
+ begin
+ if(w_pc) $display("zpu_core: set PC=0x%h", alu.alu_r);
+`ifdef ENABLE_PC_INCREMENT
+ if(w_pc_increment) $display("zpu_core: set PC=0x%h (PC+1)", pc);
+`endif
+ if(w_sp) $display("zpu_core: set SP=0x%h", alu.alu_r);
+ if(w_a) $display("zpu_core: set A=0x%h", alu.alu_r);
+ if(w_a_mem) $display("zpu_core: set A=0x%h (from MEM)", mem_data_read_int);
+ if(w_b) $display("zpu_core: set B=0x%h", alu.alu_r);
+ if(w_op & ~is_op_cached) $display("zpu_core: set opcode_cache=0x%h, pc_cached=0x%h", alu.alu_r, {pc[31:2], 2'b0});
+`ifdef ENABLE_CPU_INTERRUPTS
+ if(~busy & mc_pc == `MC_ADDR_INTERRUPT) $display("zpu_core: ***** ENTERING INTERRUPT MICROCODE ******");
+ if(~busy & exit_interrupt) $display("zpu_core: ***** INTERRUPT FLAG CLEARED *****");
+ if(~busy & enter_interrupt) $display("zpu_core: ***** INTERRUPT FLAG SET *****");
+`endif
+ if(set_idim & ~idim) $display("zpu_core: IDIM=1");
+ if(clear_idim & idim) $display("zpu_core: IDIM=0");
+
+// ---- microcode debug ----
+`ifdef ZPU_CORE_DEBUG_MICROCODE
+ if(~busy)
+ begin
+ $display("zpu_core: mc_op[%d]=0b%b", mc_pc, mc_op);
+ if(branch) $display("zpu_core: microcode: branch=%d", mc_goto);
+ if(cond_branch) $display("zpu_core: microcode: CONDITION branch=%d", mc_goto);
+ if(decode) $display("zpu_core: decoding opcode=0x%h (0b%b) : branch to=%d ", opcode, opcode, mc_entry);
+ end
+ else $display("zpu_core: busy");
+`endif
+
+// ---- cpu abort in case of unaligned memory access ---
+`ifdef ASSERT_NON_ALIGNMENT
+ /* unaligned word access (except PC) */
+ if(sel_addr != `SEL_ADDR_PC & mem_addr[1:0] != 2'b00 & (mem_read | mem_write) & !byte_op & !halfw_op)
+ begin
+ $display("zpu_core: unaligned word operation at addr=0x%x", mem_addr);
+ $finish;
+ end
+
+ /* unaligned halfword access */
+ if(mem_addr[0] & (mem_read | mem_write) & !byte_op & halfw_op)
+ begin
+ $display("zpu_core: unaligned halfword operation at addr=0x%x", mem_addr);
+ $finish;
+ end
+`endif
+
+ end
+end
+
+// ----- opcode dissasembler ------
+always @(posedge clk)
+begin
+if(~busy)
+case(mc_pc)
+0 : begin
+ $display("zpu_core: ------ breakpoint ------");
+ $finish;
+ end
+4 : $display("zpu_core: ------ shiftleft ------");
+8 : $display("zpu_core: ------ pushsp ------");
+12 : $display("zpu_core: ------ popint ------");
+16 : $display("zpu_core: ------ poppc ------");
+20 : $display("zpu_core: ------ add ------");
+24 : $display("zpu_core: ------ and ------");
+28 : $display("zpu_core: ------ or ------");
+32 : $display("zpu_core: ------ load ------");
+36 : $display("zpu_core: ------ not ------");
+40 : $display("zpu_core: ------ flip ------");
+44 : $display("zpu_core: ------ nop ------");
+48 : $display("zpu_core: ------ store ------");
+52 : $display("zpu_core: ------ popsp ------");
+56 : $display("zpu_core: ------ ipsum ------");
+60 : $display("zpu_core: ------ sncpy ------");
+
+`MC_ADDR_IM_NOIDIM : $display("zpu_core: ------ im 0x%h (1st) ------", opcode[6:0] );
+`MC_ADDR_IM_IDIM : $display("zpu_core: ------ im 0x%h (cont) ------", opcode[6:0] );
+`MC_ADDR_STORESP : $display("zpu_core: ------ storesp 0x%h ------", { ~opcode[4], opcode[3:0], 2'b0 } );
+`MC_ADDR_LOADSP : $display("zpu_core: ------ loadsp 0x%h ------", { ~opcode[4], opcode[3:0], 2'b0 } );
+`MC_ADDR_ADDSP : $display("zpu_core: ------ addsp 0x%h ------", { ~opcode[4], opcode[3:0], 2'b0 } );
+`MC_ADDR_EMULATE : $display("zpu_core: ------ emulate 0x%h ------", b[2:0]); // opcode[5:0] );
+
+128 : $display("zpu_core: ------ mcpy ------");
+132 : $display("zpu_core: ------ mset ------");
+136 : $display("zpu_core: ------ loadh ------");
+140 : $display("zpu_core: ------ storeh ------");
+144 : $display("zpu_core: ------ lessthan ------");
+148 : $display("zpu_core: ------ lessthanorequal ------");
+152 : $display("zpu_core: ------ ulessthan ------");
+156 : $display("zpu_core: ------ ulessthanorequal ------");
+160 : $display("zpu_core: ------ swap ------");
+164 : $display("zpu_core: ------ mult ------");
+168 : $display("zpu_core: ------ lshiftright ------");
+172 : $display("zpu_core: ------ ashiftleft ------");
+176 : $display("zpu_core: ------ ashiftright ------");
+180 : $display("zpu_core: ------ call ------");
+184 : $display("zpu_core: ------ eq ------");
+188 : $display("zpu_core: ------ neq ------");
+192 : $display("zpu_core: ------ neg ------");
+196 : $display("zpu_core: ------ sub ------");
+200 : $display("zpu_core: ------ xor ------");
+204 : $display("zpu_core: ------ loadb ------");
+208 : $display("zpu_core: ------ storeb ------");
+212 : $display("zpu_core: ------ div ------");
+216 : $display("zpu_core: ------ mod ------");
+220 : $display("zpu_core: ------ eqbranch ------");
+224 : $display("zpu_core: ------ neqbranch ------");
+228 : $display("zpu_core: ------ poppcrel ------");
+232 : $display("zpu_core: ------ config ------");
+236 : $display("zpu_core: ------ pushpc ------");
+240 : $display("zpu_core: ------ syscall_emulate ------");
+244 : $display("zpu_core: ------ pushspadd ------");
+248 : $display("zpu_core: ------ halfmult ------");
+252 : $display("zpu_core: ------ callpcrel ------");
+//default : $display("zpu_core: mc_pc=0x%h", decode_mcpc);
+endcase
+end
+//synthesis translate_on
+`endif
+endmodule
+
+// --------- ZPU CORE ALU UNIT ---------------
+module zpu_core_alu(
+ alu_a, // parameter A
+ alu_b, // parameter B
+ alu_r, // computed result
+ flag_idim, // for IMM alu op
+ alu_op, // ALU operation
+ clk, // clock for syncronous multicycle operations
+ done // done signal for alu operation
+);
+
+input [31:0] alu_a;
+input [31:0] alu_b;
+input [`ALU_OP_WIDTH-1:0] alu_op;
+input flag_idim;
+output [31:0] alu_r;
+input clk;
+output done;
+
+wire [31:0] alu_a;
+wire [31:0] alu_b;
+wire [`ALU_OP_WIDTH-1:0] alu_op;
+wire flag_idim;
+reg [31:0] alu_r;
+wire clk;
+reg done;
+
+`ifdef ENABLE_MULT
+// implement 32 bit pipeline multiplier
+reg mul_running;
+reg [2:0] mul_counter;
+wire mul_done = (mul_counter == 3);
+reg [31:0] mul_result, mul_tmp1;
+reg [31:0] a_in, b_in;
+
+always@(posedge clk)
+begin
+ a_in <= 0;
+ b_in <= 0;
+ mul_tmp1 <= 0;
+ mul_result <= 0;
+ mul_counter <= 0;
+ if(mul_running)
+ begin // infer pipeline multiplier
+ a_in <= alu_a;
+ b_in <= alu_b;
+ mul_tmp1 <= a_in * b_in;
+ mul_result <= mul_tmp1;
+ mul_counter <= mul_counter + 1;
+ end
+end
+`endif
+
+`ifdef ENABLE_DIV
+// implement 32 bit divider
+// Unsigned/Signed division based on Patterson and Hennessy's algorithm.
+// Description: Calculates quotient. The "sign" input determines whether
+// signs (two's complement) should be taken into consideration.
+// references: http://www.ece.lsu.edu/ee3755/2002/l07.html
+reg [63:0] qr;
+wire [33:0] diff;
+wire [31:0] quotient;
+wire [31:0] dividend;
+wire [31:0] divider;
+reg [6:0] bit;
+wire div_done;
+reg div_running;
+reg divide_sign;
+reg negative_output;
+
+assign div_done = !bit;
+assign diff = qr[63:31] - {1'b0, divider};
+assign quotient = (!negative_output) ? qr[31:0] : ~qr[31:0] + 1'b1;
+assign dividend = (!divide_sign || !alu_a[31]) ? alu_a : ~alu_a + 1'b1;
+assign divider = (!divide_sign || !alu_b[31]) ? alu_b : ~alu_b + 1'b1;
+
+always@(posedge clk)
+begin
+ bit <= 7'b1_000000; // divider stopped
+ if(div_running)
+ begin
+ if(bit[6]) // divider started: initialize registers
+ begin
+ bit <= 7'd32;
+ qr <= { 32'd0, dividend };
+ negative_output <= divide_sign && ((alu_b[31] && !alu_a[31]) || (!alu_b[31] && alu_a[31]));
+ end
+ else // step by step divide
+ begin
+ if( diff[32] ) qr <= { qr[62:0], 1'd0 };
+ else qr <= { diff[31:0], qr[30:0], 1'd1 };
+ bit <= bit - 1;
+ end
+ end
+end
+`endif
+
+`ifdef ENABLE_BARREL
+// implement 32 bit barrel shift
+// alu_b[6] == 1 ? left(only arithmetic) : right
+// alu_b[5] == 1 ? logical : arithmetic
+reg bs_running;
+reg [31:0] bs_result;
+reg [4:0] bs_counter; // 5 bits
+wire bs_left = alu_b[6];
+wire bs_logical = alu_b[5];
+wire [4:0] bs_moves = alu_b[4:0];
+wire bs_done = (bs_counter == bs_moves);
+
+always @(posedge clk)
+begin
+ bs_counter <= 0;
+ bs_result <= alu_a;
+ if(bs_running)
+ begin
+ if(bs_left) bs_result <= { bs_result[30:0], 1'b0 }; // shift left
+ else
+ begin
+ if(bs_logical) bs_result <= { 1'b0, bs_result[31:1] }; // shift logical right
+ else bs_result <= { bs_result[31], bs_result[31], bs_result[30:1] };// shift arithmetic right
+ end
+ bs_counter <= bs_counter + 1;
+ end
+end
+`endif
+
+// ----- alu add/sub -----
+reg [31:0] alu_b_tmp;
+always @(alu_b or alu_op)
+begin
+ alu_b_tmp <= alu_b; // by default, ALU_B as is
+ if(alu_op == `ALU_PLUS_OFFSET) alu_b_tmp <= { {25{1'b0}}, ~alu_b[4], alu_b[3:0], 2'b0 }; // ALU_B is an offset if ALU_PLUS_OFFSET operation
+end
+
+reg [31:0] alu_r_addsub; // compute R=A+B or A-B based on opcode (ALU_PLUSxx / ALU_SUB-CMP)
+always @(alu_a or alu_b_tmp or alu_op)
+begin
+`ifdef ENABLE_CMP
+ if(alu_op == `ALU_CMP_SIGNED || alu_op == `ALU_CMP_UNSIGNED) // in case of sub or cmp --> operation is '-'
+ begin
+ alu_r_addsub <= alu_a - alu_b_tmp;
+ end
+ else
+`endif
+ begin
+ alu_r_addsub <= alu_a + alu_b_tmp; // by default '+' operation
+ end
+end
+
+`ifdef ENABLE_CMP
+// handle overflow/underflow exceptions in ALU_CMP_SIGNED
+reg cmp_exception;
+always @(alu_a[31] or alu_b[31] or alu_r_addsub[31])
+begin
+ cmp_exception <= 0;
+ if( (alu_a[31] == 0 && alu_b[31] == 1 && alu_r_addsub[31] == 1) ||
+ (alu_a[31] == 1 && alu_b[31] == 0 && alu_r_addsub[31] == 0) ) cmp_exception <= 1;
+end
+`endif
+
+// ----- alu operation selection -----
+always @(alu_a or alu_b or alu_op or flag_idim or alu_r_addsub
+`ifdef ENABLE_CMP
+ or cmp_exception
+`endif
+`ifdef ENABLE_MULT
+ or mul_done or mul_result
+`endif
+`ifdef ENABLE_BARREL
+ or bs_done or bs_result
+`endif
+`ifdef ENABLE_DIV
+ or div_done or div_result
+`endif
+)
+begin
+ done <= 1; // default alu operations are 1 cycle
+`ifdef ENABLE_MULT
+ mul_running <= 0;
+`endif
+`ifdef ENABLE_BARREL
+ bs_running <= 0;
+`endif
+`ifdef ENABLE_DIV
+ div_running <= 0;
+`endif
+ alu_r <= alu_r_addsub; // ALU_PLUS, ALU_PLUS_OFFSET, ALU_SUB and part of ALU_CMP
+ case(alu_op)
+ `ALU_NOP : alu_r <= alu_a;
+ `ALU_NOP_B : alu_r <= alu_b;
+ `ALU_AND : alu_r <= alu_a & alu_b;
+ `ALU_OR : alu_r <= alu_a | alu_b;
+ `ALU_NOT : alu_r <= ~alu_a;
+ `ALU_FLIP : alu_r <= { alu_a[0], alu_a[1], alu_a[2], alu_a[3], alu_a[4], alu_a[5], alu_a[6], alu_a[7],
+ alu_a[8],alu_a[9],alu_a[10],alu_a[11],alu_a[12],alu_a[13],alu_a[14],alu_a[15],
+ alu_a[16],alu_a[17],alu_a[18],alu_a[19],alu_a[20],alu_a[21],alu_a[22],alu_a[23],
+ alu_a[24],alu_a[25],alu_a[26],alu_a[27],alu_a[28],alu_a[29],alu_a[30],alu_a[31] };
+ `ALU_IM : if(flag_idim) alu_r <= { alu_a[24:0], alu_b[6:0] };
+ else alu_r <= { {25{alu_b[6]}}, alu_b[6:0] };
+`ifdef ENABLE_CMP
+ `ALU_CMP_UNSIGNED:if( (alu_a[31] == alu_b[31] && cmp_exception) ||
+ (alu_a[31] != alu_b[31] && ~cmp_exception) )
+ begin
+ alu_r[31] <= ~alu_r_addsub[31];
+ end
+ `ALU_CMP_SIGNED : if(cmp_exception)
+ begin
+ alu_r[31] <= ~alu_r_addsub[31];
+ end
+`endif
+`ifdef ENABLE_XOR
+ `ALU_XOR : alu_r <= alu_a ^ alu_b;
+`endif
+`ifdef ENABLE_A_SHIFT
+ `ALU_A_SHIFT_RIGHT: alu_r <= { alu_a[31], alu_a[31], alu_a[30:1] }; // arithmetic shift left
+`endif
+`ifdef ENABLE_MULT
+ `ALU_MULT : begin
+ mul_running <= ~mul_done;
+ done <= mul_done;
+ alu_r <= mul_result;
+ end
+`endif
+`ifdef ENABLE_BARREL
+ `ALU_BARREL : begin
+ bs_running <= ~bs_done;
+ done <= bs_done;
+ alu_r <= bs_result;
+ end
+`endif
+`ifdef ENABLE_DIV
+ `ALU_DIV : begin
+ div_running<= ~div_done;
+ done <= div_done;
+ alu_r <= quotient;
+ end
+ `ALU_MOD : begin
+ div_running<= ~div_done;
+ done <= div_done;
+ alu_r <= qr[31:0];
+ end
+`endif
+ endcase
+end
+
+endmodule
diff --git a/zpu/hdl/avalanche/core/zpu_core_defines.v b/zpu/hdl/avalanche/core/zpu_core_defines.v
new file mode 100644
index 0000000..228f46b
--- /dev/null
+++ b/zpu/hdl/avalanche/core/zpu_core_defines.v
@@ -0,0 +1,322 @@
+/* MODULE: zpu_core_defines
+ DESCRIPTION: Contains ZPU parameters and other cpu related definitions
+ AUTHOR: Antonio J. Anton (aj <at> anro-ingenieros.com)
+
+REVISION HISTORY:
+Revision 1.0, 14/09/2009
+Initial public release
+
+COPYRIGHT:
+Copyright (c) 2009 Antonio J. Anton
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the "Software"), to deal in
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+of the Software, and to permit persons to whom the Software is furnished to do
+so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.*/
+
+/* --------------- ISA DOCUMENTATION ------------------
+ stack: top of stack = sp, mem[sp]=valid data
+ push: sp=sp-1, then mem[sp]=data
+ pop: data=mem[sp], then sp=sp+1
+
+ immediates: any opcode instead of im sets idim=0
+
+ MNEMONIC OPCODE HEX OPERATION
+- im x 1_xxxxxxx if(~idim) { idim=1; sp=sp-1; mem[sp]={{25{b[6]}},b[6:0]} }
+ else { idim=1; mem[sp]={mem[sp][24:0], b[6:0]} }
+- emulate x 001_xxxxx sp=sp-1; mem[sp]=pc+1; pc=mem[@VECTOR_EMULATE + <b>]; fetch (used only by microcode)
+- storesp x 010_xxxxx mem[sp+x<<2] = mem[sp]; sp=sp+1
+- loadsp x 011_xxxxx mem[sp-1] = mem [sp+x<<2]; sp=sp-1
+- addsp x 0001_xxxx (1x) mem[sp] = mem[sp]+mem[sp+x<<2]
+
+- breakpoint 0000_0000 (00) call exception vector
+ shiftleft 0000_0001 (01)
+- pushsp 0000_0010 (02) mem[sp-1] = sp; sp = sp - 1
+- popint 0000_0011 (03) pc=mem[sp]; sp = sp + 1 ; fetch ; decode ; clear_interrupt_flag
+- poppc 0000_0100 (04) pc=mem[sp]; sp = sp + 1
+- add 0000_0101 (05) mem[sp+1] = mem[sp+1] + mem[sp]; sp = sp + 1
+- and 0000_0110 (06) mem[sp+1] = mem[sp+1] & mem[sp]; sp = sp + 1
+- or 0000_0111 (07) mem[sp+1] = mem[sp+1] | mem[sp]; sp = sp + 1
+- load 0000_1000 (08) mem[sp] = mem[ mem[sp] ]
+- not 0000_1001 (09) mem[sp] = ~mem[sp]
+- flip 0000_1010 (0a) mem[sp] = flip(mem[sp])
+- nop 0000_1011 (0b) -
+- store 0000_1100 (0c) mem[mem[sp]] = mem[sp+1]; sp = sp + 2
+- popsp 0000_1101 (0d) sp = mem[sp]
+ compare 0000_1110 (0e) ???? --> opcode recycled (see below)
+ popint 0000_1111 (0f) duplicated of 0x03 ????? --> opcode recycled (see below)
+
+- ipsum 0000_1110 (0e) c=mem[sp],s=mem[sp+1]; sum=0; while(c-->0) {sum+=halfword(mem[s],s);s+=2}; sp=sp+1; mem[sp]=sum (overwrites mem[0] & mem[4] words)
+- sncpy 0000_1111 (0f) c=mem[sp],d=mem[sp+1],s=mem[sp+2]; while( *(char*)s != 0 && c>0 ) {*((char*)d++)=*((char*)s++));c--}; sp=sp+3 (overwrites mem[0] & mem[4] words)
+- wcpy 001_00000 (20) c=mem[sp],d=mem[sp+1],s=mem[sp+2]; while(c-->0) mem[d++]=mem[s++]; sp=sp+3 (overwrites mem[0] & mem[4] words)
+- wset 001_00001 (21) v=mem[sp],c=mem[sp+1],d=mem[sp+2]; while(c-->0) mem[d++]=v; sp=sp+3 (overwrites mem[0] & mem[4] words)
+
+- loadh 001_00010 (22) mem[sp] = halfword[ mem[sp] ]
+- storeh 001_00011 (23) halfword[mem[sp]] = (mem[sp+1] & 0xFFFF); sp = sp + 2
+- lessthan 001_00100 (24) (mem[sp]-mem[sp+1]) < 0 ? mem[sp+1]=1 : mem[sp+1]=0; sp = sp + 1
+- lessthanorequal 001_00101 (25) (mem[sp]-mem[sp+1]) <= 0 ? mem[sp+1]=1 : mem[sp+1]=0; sp = sp + 1
+- ulessthan 001_00110 (26) (unsigned(mem[sp])-unsigned(mem[sp+1])) < 0 ? mem[sp+1]=1 : mem[sp+1]=0; sp = sp + 1
+- ulessthanorequal 001_00111 (27) (unsigned(mem[sp])-unsigned(mem[sp+1])) <= 0 || == 0 ? mem[sp+1]=1 : mem[sp+1]=0; sp = sp + 1
+ swap 001_01000 (28)
+- mult 001_01001 (29) mem[sp+1] = mem[sp+1] * mem[sp]; sp = sp + 1
+- lshiftright 001_01010 (2a) mem[sp+1] = mem[sp+1] >> (mem[sp] & 0x1f); sp = sp + 1
+- ashiftleft 001_01011 (2b) mem[sp+1] = mem[sp+1] << (mem[sp] & 0x1f); sp = sp + 1
+- ashiftright 001_01100 (2c) mem[sp+1] = mem[sp+1] signed>> (mem[sp] & 0x1f); sp = sp + 1
+- call 001_01101 (2d) a = mem[sp]; mem[sp]=pc + 1; pc = a
+- eq 001_01110 (2e) mem[sp+1] = (mem[sp] == mem[sp+1]) ? 1 : 0; sp = sp + 1
+- neq 001_01111 (2f) mem[sp+1] = (mem[sp] != mem[sp+1]) ? 1 : 0; sp = sp + 1
+- neg 001_10000 (30) mem[sp] = NOT(mem[sp])+1
+- sub 001_10001 (31) mem[sp+1]=mem[sp+1]-mem[sp]; sp=sp+1
+- xor 001_10010 (32) mem[sp+1]=mem[sp] ^ mem[sp+1]; sp=sp+1
+- loadb 001_10011 (33) mem[sp] = byte[ mem[sp] ]
+- storeb 001_10100 (34) byte[mem[sp]] = (mem[sp+1] & 0xFF); sp = sp + 2
+ div 001_10101 (35)
+ mod 001_10110 (36)
+- eqbranch 001_10111 (37) mem[sp+1] == 0 ? pc = pc + mem[sp]; sp = sp + 2
+- neqbranch 001_11000 (38) mem[sp+1] != 0 ? pc = pc + mem[sp]; sp = sp + 2
+- poppcrel 001_11001 (39) pc = pc + mem[sp]; sp = sp + 1
+ config 001_11010 (3a)
+- pushpc 001_11011 (3b) sp=sp-1; mem[sp]=pc
+ syscall 001_11100 (3c)
+- pushspadd 001_11101 (3d) mem[sp] = sp + (mem[sp] << 2)
+- halfmult 001_11110 (3e) mem[sp+1] = 16bits(mem[sp]) * 16bits(mem[sp+1]); sp = sp + 1
+- callpcrel 001_11111 (3f) a = mem[sp]; mem[sp]=pc+1; pc = pc + a;
+
+ gcc seems to be using only:
+
+ add, addsp, and, ashiftleft, ashiftright, call, callpcrel, div, eq, flip, im, lessthan,
+ lessthanorequal, loadb, loadh, load, loadsp, lshiftright, mod, mult, neg, neqbranch,
+ not, or, poppc, poppcrel, popsp, pushpc, pushspadd, pushsp, storeb, storeh, store, storesp,
+ sub, ulessthan, ulessthanorequal, xor
+
+ --------- memory access ----------------------------
+
+ data is stored in big-endian format into memory:
+ 00 MSB .. .. LSB
+ 05 .. .. .. ..
+
+ ---------------------------------------------------- */
+`define SP_START 32'h10 // after reset change in startup code
+`define EMULATION_VECTOR 32'h10 // table of emulated opcodes (interrupt & exception vectors plus up to 5 emulated opcodes)
+`define RESET_VECTOR 32'h20 // reset entry point (can be moved up to 0x3c as per emulation table needs)
+
+// ---- zpu core optimizations/features ----
+`define ZPU_CORE_DEBUG
+//`define ZPU_CORE_DEBUG_MICROCODE
+`define ASSERT_NON_ALIGNMENT /* abort cpu in case of non-aligned memory access (only simulation) */
+
+`define ENABLE_BYTE_SELECT /* allow byte / halfword memory accesses */
+`define ENABLE_CPU_INTERRUPTS /* enable interrupts to cpu */
+//`define ENABLE_PC_INCREMENT /* gain 1 clk per opcode but requires microcode changes ** not done at the moment ** */
+//`define ENABLE_A_SHIFT /* 1 bit arithmetic shift (right) mutual exclusive with barrel shift */
+//`define ENABLE_XOR /* 1 cycle x-or */
+//`define ENABLE_MULT /* 32 bit pipelined (3 stages) multiplier */
+//`define ENABLE_DIV /* 32 bit, up to 32 cycles serial divider */
+`define ENABLE_BARREL /* n bit logical & arithmetic shift mutual exclusive with 1 bit shift */
+`define ENABLE_CMP /* enable ALU_CMP_SIGNED and ALU_CMP_UNSIGNED */
+
+// ------- microcode zpu core datapath selectors --------
+`define SEL_READ_DATA 0
+`define SEL_READ_ADDR 1
+
+`define SEL_ALU_A 0
+`define SEL_ALU_OPCODE 1
+`define SEL_ALU_MC_CONST 2
+`define SEL_ALU_B 3
+
+`define SEL_ADDR_PC 0
+`define SEL_ADDR_SP 1
+`define SEL_ADDR_A 2
+`define SEL_ADDR_B 3
+
+`define ALU_OP_WIDTH 4 // alu operation is 4 bits
+
+`define ALU_NOP 0 // r = a
+`define ALU_NOP_B 1 // r = b
+`define ALU_PLUS 2 // r = a + b
+`define ALU_PLUS_OFFSET 3 // r = a + { 27'b0, ~b[4], b[3:0] }
+`define ALU_AND 4 // r = a AND b
+`define ALU_OR 5 // r = a OR b
+`define ALU_NOT 6 // r = NOT a
+`define ALU_FLIP 7 // r = FLIP a
+`define ALU_IM 8 // r = IDIM ? { a[24:0], b[6:0] } : { 25{b[6]}, b[6:0] }
+`ifdef ENABLE_CMP
+ `define ALU_CMP_UNSIGNED 9 // r = (unsigned)a - (unsigned)b (r[31] is overflow/underflow adjusted)
+ `define ALU_CMP_SIGNED 10 // r = (signed)a - (signed)b (r[31] is overflow/underflow adjusted)
+`endif
+`ifdef ENABLE_BARREL
+ `define ALU_BARREL 11 // r = a <<|>> b (logical, arithmetical)
+`endif
+`ifdef ENABLE_A_SHIFT
+ `define ALU_A_SHIFT_RIGHT 11 // r = { a[31], a[31], a[30:29] } = (signed)a >> 1
+`endif
+`ifdef ENABLE_XOR
+ `define ALU_XOR 12 // r = a XOR b
+`endif
+`ifdef ENABLE_MULT
+ `define ALU_MULT 13 // r = a * b
+`endif
+`ifdef ENABLE_DIV
+ `define ALU_DIV 14 // r = a / b
+ `define ALU_MOD 15 // r = a mod b
+`endif
+
+// ------- special zpu opcodes ------
+`define OP_NOP 8'b0000_1011 // default value for opcode cache on reset
+`define OP_IM 1'b1
+`define OP_EMULATE 3'b001
+`define OP_STORESP 3'b010
+`define OP_LOADSP 3'b011
+`define OP_ADDSP 4'b0001
+
+// ------- microcode memory settings ------
+`define MC_MEM_BITS 9 // 512 microcode operations
+`define MC_BITS 36 // microcode opcode width
+
+// ------- microcode labels for opcode execution -------
+// based on microcode program
+`define MC_ADDR_IM_NOIDIM 488
+`define MC_ADDR_IM_IDIM 491
+`define MC_ADDR_STORESP 493
+`define MC_ADDR_LOADSP 496
+`define MC_ADDR_ADDSP 500
+`define MC_ADDR_EMULATE 504
+`define MC_ADDR_INTERRUPT 484
+`define MC_ADDR_FETCH_NEXT 480
+`define MC_ADDR_FETCH 476
+`define MC_ADDR_RESET 474
+
+// ---------- microcode settings --------------------
+`define P_SEL_READ 0 // alu-A multiplexor between data-in and addr-out (1 bit)
+`define P_SEL_ALU 1 // alu-B multiplexor between a, b, mc_const or opcode (2 bits)
+`define P_SEL_ADDR 3 // addr-out multiplexor between sp, pc, a, b (2 bits)
+`define P_ALU 5 // alu operation (4 bits)
+`define P_W_SP 9 // write sp (from alu-out)
+`define P_W_PC 10 // write pc (from alu-out)
+`define P_W_A 11 // write a (from alu-out)
+`define P_W_B 12 // write b (from alu-out)
+`define P_SET_IDIM 13 // set idim flag
+`define P_CLEAR_IDIM 14 // clear idim flag
+`define P_W_OPCODE 15 // write opcode (from alu-out) : check if can be written directly from data-in
+`define P_DECODE 16 // jump to microcode entry point based on current opcode
+`define P_MEM_R 17 // request memory read
+`define P_MEM_W 18 // request memory write
+`define P_ADDR 19 // microcode address (7 bits (granularity is 4 words)) or constant to be used at microcode level
+`define P_BRANCH 26 // microcode inconditional branch to address
+`define P_OP_NOT_CACHED 27 // microcode branch if byte[pc] is not cached at opcode
+`define P_A_ZERO 28 // microcode branch if a is zero
+`define P_A_NEG 29 // microcode branch if a is negative a[31]=1
+`define P_W_A_MEM 30 // write a directly from data-in (alu datapath is free to perform any other operation in parallel)
+`ifdef ENABLE_BYTE_SELECT
+ `define P_BYTE 31 // byte memory operation
+ `define P_HALFWORD 32 // half word memory operation
+`endif
+`ifdef ENABLE_PC_INCREMENT
+ `define P_PC_INCREMENT 33 // autoincrement PC bypassing ALU (1 clock gain per opcode) : not implemented at microcode level
+`endif
+`ifdef ENABLE_CPU_INTERRUPTS
+ `define P_EXIT_INT 34 // clear interrupt flag (exit from interrupt)
+ `define P_ENTER_INT 35 // set interrupt flag (enter interrupt)
+`endif
+
+`define MC_SEL_READ_DATA (`SEL_READ_DATA << `P_SEL_READ) // 1 bit
+`define MC_SEL_READ_ADDR (`SEL_READ_ADDR << `P_SEL_READ)
+
+`define MC_SEL_ALU_A (`SEL_ALU_A << `P_SEL_ALU) // 2 bit
+`define MC_SEL_ALU_OPCODE (`SEL_ALU_OPCODE << `P_SEL_ALU)
+`define MC_SEL_ALU_MC_CONST (`SEL_ALU_MC_CONST << `P_SEL_ALU)
+`define MC_SEL_ALU_B (`SEL_ALU_B << `P_SEL_ALU)
+
+`define MC_SEL_ADDR_PC (`SEL_ADDR_PC << `P_SEL_ADDR) // 2 bits
+`define MC_SEL_ADDR_SP (`SEL_ADDR_SP << `P_SEL_ADDR)
+`define MC_SEL_ADDR_A (`SEL_ADDR_A << `P_SEL_ADDR)
+`define MC_SEL_ADDR_B (`SEL_ADDR_B << `P_SEL_ADDR)
+
+`define MC_ALU_NOP (`ALU_NOP << `P_ALU) // 4 bits
+`define MC_ALU_NOP_B (`ALU_NOP_B << `P_ALU)
+`define MC_ALU_PLUS (`ALU_PLUS << `P_ALU)
+`define MC_ALU_AND (`ALU_AND << `P_ALU)
+`define MC_ALU_OR (`ALU_OR << `P_ALU)
+`define MC_ALU_NOT (`ALU_NOT << `P_ALU)
+`define MC_ALU_FLIP (`ALU_FLIP << `P_ALU)
+`define MC_ALU_IM (`ALU_IM << `P_ALU)
+`define MC_ALU_PLUS_OFFSET (`ALU_PLUS_OFFSET << `P_ALU)
+`ifdef ENABLE_CMP
+ `define MC_ALU_CMP_SIGNED (`ALU_CMP_SIGNED << `P_ALU)
+ `define MC_ALU_CMP_UNSIGNED (`ALU_CMP_UNSIGNED << `P_ALU)
+`endif
+`ifdef ENABLE_XOR
+ `define MC_ALU_XOR (`ALU_XOR << `P_ALU)
+`endif
+`ifdef ENABLE_A_SHIFT
+ `define MC_ALU_A_SHIFT_RIGHT (`ALU_A_SHIFT_RIGHT << `P_ALU)
+`endif
+`ifdef ENABLE_MULT
+ `define MC_ALU_MULT (`ALU_MULT << `P_ALU)
+`endif
+`ifdef ENABLE_DIV
+ `define MC_ALU_DIV (`ALU_DIV << `P_ALU)
+ `define MC_ALU_MOD (`ALU_MOD << `P_ALU)
+`endif
+`ifdef ENABLE_BARREL
+ `define MC_ALU_BARREL (`ALU_BARREL << `P_ALU)
+`endif
+
+`define MC_W_SP (1 << `P_W_SP)
+`define MC_W_PC (1 << `P_W_PC)
+`define MC_W_A (1 << `P_W_A)
+`define MC_W_A_MEM (1 << `P_W_A_MEM)
+`define MC_W_B (1 << `P_W_B)
+`define MC_W_OPCODE (1 << `P_W_OPCODE)
+`define MC_SET_IDIM (1 << `P_SET_IDIM)
+`define MC_CLEAR_IDIM (1 << `P_CLEAR_IDIM)
+`ifdef ENABLE_BYTE_SELECT
+ `define MC_BYTE (1 << `P_BYTE)
+ `define MC_HALFWORD (1 << `P_HALFWORD)
+`endif
+`ifdef ENABLE_PC_INCREMENT
+ `define MC_PC_INCREMENT (1 << `P_PC_INCREMENT)
+`endif
+`ifdef ENABLE_CPU_INTERRUPTS
+ `define MC_EXIT_INTERRUPT (1 << `P_EXIT_INT)
+ `define MC_ENTER_INTERRUPT (1 << `P_ENTER_INT)
+`endif
+
+`define MC_MEM_R (1 << `P_MEM_R)
+`define MC_MEM_W (1 << `P_MEM_W)
+
+`define MC_DECODE (1 << `P_DECODE)
+`define MC_BRANCH (1 << `P_BRANCH)
+`define MC_BRANCHIF_OP_NOT_CACHED (1 << `P_OP_NOT_CACHED)
+`define MC_BRANCHIF_A_ZERO (1 << `P_A_ZERO)
+`define MC_BRANCHIF_A_NEG (1 << `P_A_NEG)
+
+// microcode common operations
+
+`define MC_ADDR_FETCH_OP ( (`MC_ADDR_FETCH >> 2) << `P_ADDR) // fetch opcode from memory then decode
+`define MC_ADDR_NEXT_OP ( (`MC_ADDR_FETCH_NEXT >> 2) << `P_ADDR) // go to next opcode
+`define MC_ADDR_EMULATE_OP ( (`MC_ADDR_EMULATE >> 2) << `P_ADDR) // EMULATE opcode
+
+`define MC_PC_PLUS_1 (`MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_SEL_ALU_MC_CONST | `MC_ALU_PLUS | (1 << `P_ADDR) | `MC_W_PC)
+`define MC_SP_MINUS_4 (`MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_SEL_ALU_MC_CONST | `MC_ALU_PLUS | ((-4 & 127) << `P_ADDR) | `MC_W_SP)
+`define MC_SP_PLUS_4 (`MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_SEL_ALU_MC_CONST | `MC_ALU_PLUS | (4 << `P_ADDR) | `MC_W_SP)
+`define MC_EMULATE (`MC_BRANCH | `MC_ADDR_EMULATE_OP)
+
+`define MC_FETCH (`MC_BRANCHIF_OP_NOT_CACHED | `MC_ADDR_FETCH_OP | `MC_DECODE) // fetch and decode current PC opcode
+`define MC_GO_NEXT (`MC_BRANCH | `MC_ADDR_NEXT_OP) // go to next opcode (PC=PC+1, fetch, decode)
+`define MC_GO_FETCH (`MC_BRANCH | `MC_ADDR_FETCH_OP) // go to fetch opcode at PC, then decode
+`define MC_GO_BREAKPOINT (`MC_BRANCH | ((0 >> 2) << `P_ADDR)) // go to breakpoint opcode
+
diff --git a/zpu/hdl/avalanche/core/zpu_core_rom.v b/zpu/hdl/avalanche/core/zpu_core_rom.v
new file mode 100644
index 0000000..62b7229
--- /dev/null
+++ b/zpu/hdl/avalanche/core/zpu_core_rom.v
@@ -0,0 +1,1017 @@
+`timescale 1ns / 1ps
+`include "zpu_core_defines.v"
+
+/* MODULE: zpu_core_rom
+ DESCRIPTION: Contains microcode program
+ AUTHOR: Antonio J. Anton (aj <at> anro-ingenieros.com)
+
+REVISION HISTORY:
+Revision 1.0, 14/09/2009
+Initial public release
+
+COPYRIGHT:
+Copyright (c) 2009 Antonio J. Anton
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the "Software"), to deal in
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+of the Software, and to permit persons to whom the Software is furnished to do
+so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.*/
+
+module zpu_core_rom (
+ clk,
+ addr,
+ data
+);
+
+input [`MC_MEM_BITS-1:0] addr;
+output [`MC_BITS-1:0] data;
+input clk;
+
+wire [`MC_MEM_BITS-1:0] addr;
+reg [`MC_BITS-1:0] data;
+reg [`MC_BITS-1:0] memory[(1<<`MC_MEM_BITS)-1:0];
+
+initial data <= 0;
+always @(posedge clk) data <= memory[addr];
+
+// --- clear all memory at startup; for any reason, xilinx xst
+// will not syntetize as block ram if not all memory is initialized ---
+integer n;
+initial begin
+// initialize all memory array
+for(n = 0; n < (1<<`MC_MEM_BITS); n = n + 1) memory[n] = 0;
+
+// ------------------------- MICROCODE MEMORY START -----------------------------------
+
+// As per zpu_core.v, each opcode is executed by microcode. Each opcode microcode entry point
+// is at <opcode> << 2 (example pushsp = 0x02 has microcode entry point of 0x08); this leaves
+// room of 4 microcode operations per opcode; if the opcode microcode needs more space,
+// it can jump & link to other microcode address (with the two lower bits at 0). The lower 256 addresses
+// of microcode memory are entry points and code for 0..127 opcodes; other specific opcodes like im, storesp, etc.
+// are directly hardwired to specific microcode addresses at the memory end. Upper 256 addresses are
+// used by microcode continuation (eg. opcodes which needs more microcode operations), entry points, initializations, etc.
+// the idea is to fit the microcode program in a xilinx blockram 512x36.
+
+// ----- OPCODES WITHOUT CONSTANT ------
+
+// 0000_0000 (00) breakpoint -------------------------------------
+memory[0] = `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) | // b = 4 (#1 in emulate table)
+ `MC_W_B;
+memory[1] = `MC_EMULATE; // emulate #1 (exception)
+
+// 0000_0001 (01) shiftleft -------------------------------------
+memory[4] = `MC_GO_BREAKPOINT;
+
+// 0000_0010 (02) pushsp -------------------------------------
+// mem[sp-1] = sp
+// sp = sp - 1
+memory[8] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | // a = sp
+ `MC_ALU_NOP | `MC_W_A;
+memory[9] = `MC_SP_MINUS_4; // sp = sp - 1
+memory[10] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp]=a
+
+// 0000_0011 (03) popint -------------------------------------
+`ifdef ENABLE_CPU_INTERRUPTS
+// pc=mem[sp]-1 (emulate stores pc+1 but we must return to
+// sp=sp+1 pc because interrupt takes precedence to decode)
+// fetch & decode, then clear_interrupt_flag
+// this guarantees that a continous interrupt allows to execute at least one
+// opcode of mainstream program before reentry to interrupt handler
+memory[12] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // pc = mem[sp]-1
+ `MC_MEM_R | `MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST |
+ ((-1 & 127) << `P_ADDR) | `MC_W_PC;
+memory[13] = `MC_SEL_ADDR_PC | `MC_SEL_READ_DATA | `MC_MEM_R | // opcode_cache = mem[pc]
+ `MC_W_OPCODE;
+memory[14] = `MC_SP_PLUS_4 | `MC_DECODE | `MC_EXIT_INTERRUPT; // sp=sp+1, decode opcode, exit_interrupt
+`else
+memory[12] = `MC_GO_BREAKPOINT;
+`endif
+
+// 0000_0100 (04) poppc -------------------------------------
+// pc=mem[sp]
+// sp = sp + 1
+memory[16] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // pc = mem[sp]
+ `MC_MEM_R | `MC_W_PC;
+memory[17] = `MC_SP_PLUS_4; // sp = sp + 1
+memory[18] = `MC_FETCH; // opcode cached ? decode : fetch,decode
+
+// 0000_0101 (05) add -------------------------------------
+// mem[sp+1] = mem[sp+1] + mem[sp]
+// sp = sp + 1
+memory[20] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | // a = mem[sp] || sp=sp+1
+ `MC_W_A_MEM | `MC_SP_PLUS_4;
+memory[21] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // a = a + mem[sp]
+ `MC_ALU_PLUS | `MC_SEL_ALU_A | `MC_W_A;
+memory[22] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+
+// 0000_0110 (06) and -------------------------------------
+// mem[sp+1] = mem[sp+1] & mem[sp]
+// sp = sp + 1
+memory[24] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | // a = mem[sp] || sp=sp+1
+ `MC_W_A_MEM | `MC_SP_PLUS_4;
+memory[25] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // a = a & mem[sp]
+ `MC_ALU_AND |`MC_SEL_ALU_A | `MC_W_A;
+memory[26] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+
+// 0000_0111 (07) or -------------------------------------
+// mem[sp+1] = mem[sp+1] | mem[sp]
+// sp = sp + 1
+memory[28] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | // a = mem[sp] || sp=sp+1
+ `MC_W_A_MEM | `MC_SP_PLUS_4;
+memory[29] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // a = a | mem[sp]
+ `MC_ALU_OR | `MC_SEL_ALU_A | `MC_W_A;
+memory[30] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+
+// 0000_1000 (08) load -------------------------------------
+// mem[sp] = mem[ mem[sp] ]
+memory[32] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // a = mem[sp]
+ `MC_MEM_R | `MC_W_A;
+memory[33] = `MC_SEL_ADDR_A | `MC_SEL_READ_DATA | `MC_MEM_R | `MC_W_A; // a = mem[a]
+memory[34] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+
+// 0000_1001 (09) not -------------------------------------
+// mem[sp] = ~mem[sp]
+memory[36] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // a = ~mem[sp]
+ `MC_MEM_R | `MC_ALU_NOT | `MC_W_A;
+memory[37] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+
+// 0000_1010 (0a) flip -------------------------------------
+// mem[sp] = flip(mem[sp])
+memory[40] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // a = FLIP(mem[sp])
+ `MC_MEM_R | `MC_ALU_FLIP | `MC_W_A;
+memory[41] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+
+// 0000_1011 (0b) nop -------------------------------------
+memory[44] = `MC_CLEAR_IDIM | `MC_PC_PLUS_1; // IDIM=0
+memory[45] = `MC_FETCH;
+
+// 0000_1100 (0c) store -------------------------------------
+// mem[mem[sp]] <= mem[sp+1]
+// sp = sp + 2
+memory[48] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // b = mem[sp]
+ `MC_MEM_R | `MC_W_B;
+memory[49] = `MC_SP_PLUS_4; // sp = sp + 1
+memory[50] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM | `MC_SP_PLUS_4; // a = mem[sp] || sp = sp + 1
+memory[51] = `MC_SEL_ADDR_B | `MC_MEM_W | `MC_GO_NEXT; // mem[b] = a
+
+// 0000_1101 (0d) popsp -------------------------------------
+// sp = mem[sp]
+memory[52] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | // sp = mem[sp]
+ `MC_W_SP | `MC_GO_NEXT;
+
+// 0000_1110 (0e) ipsum ------------------------------------
+// compare: opcode recycled --> ipsum
+// c=mem[sp];s=mem[sp+1]; sum=0;
+// while(c-->0) {sum+=halfword(mem[s],s);s++};
+// sp=sp+1; mem[sp]=sum (overwrites mem[0] & mem[4] words)
+// requires HALFWORD memory access
+`ifdef ENABLE_BYTE_SELECT
+memory[56] = `MC_CLEAR_IDIM | `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | // b=0
+ (0 << `P_ADDR) | `MC_W_B;
+memory[57] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a=pc+1 save next pc on mem[0]
+ `MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
+memory[58] = `MC_SEL_ADDR_B | `MC_MEM_W | `MC_ALU_NOP_B | `MC_W_B | // mem[b]=a || b=4
+ `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR);
+memory[59] = `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_W_A | // a=sp || goto @ipsum_continue1
+ `MC_BRANCH | ((116 >> 2) << `P_ADDR);
+`else
+memory[56] = `MC_GO_BREAKPOINT;
+`endif
+
+// 0000_1111 (0f) sncpy ---------------------------------------
+// c=mem[sp],d=mem[sp+1],s=mem[sp+2];
+// while( *(char*)s != 0 && c>0 ) { *((char*)d++)=*((char*)s++)); c-- };
+// sp=sp+1; mem[sp+1]=d; mem[sp]=c
+// (overwrites mem[0] & mem[4] words)
+// requires BYTE memory access
+`ifdef ENABLE_BYTE_SELECT
+memory[60] = `MC_CLEAR_IDIM | `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | // b=0
+ (0 << `P_ADDR) | `MC_W_B;
+memory[61] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a=pc+1 save next pc on mem[0]
+ `MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
+memory[62] = `MC_SEL_ADDR_B | `MC_MEM_W | `MC_ALU_NOP_B | `MC_W_B | // mem[b]=a || b=4
+ `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR);
+memory[63] = `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_W_A | // a=sp || goto @sncpy_continue1
+ `MC_BRANCH | ((100 >> 2) << `P_ADDR);
+`else
+memory[60] = `MC_GO_BREAKPOINT;
+`endif
+
+// ------------- microcode opcode continuations ---------------
+// wset_continue1: ------------------------
+memory[64] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a=a+12 save clear stack on mem[4]
+ `MC_SEL_ALU_MC_CONST | (12 << `P_ADDR) | `MC_W_A;
+memory[65] = `MC_SEL_ADDR_B | `MC_MEM_W; // mem[b]=a
+memory[66] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_PC;// pc=mem[sp] (data)
+memory[67] = `MC_SP_PLUS_4; // sp=sp+4
+memory[68] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_B; // b=mem[sp] (count)
+memory[69] = `MC_SP_PLUS_4; // sp=sp+4
+memory[70] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_SP;// sp=mem[sp] (destination @)
+memory[71] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A; // a=b (count)
+// wset_loop:
+memory[72] = `MC_BRANCHIF_A_ZERO | ( (80 >> 2) << `P_ADDR); // if(a==0) goto @wset_end
+memory[73] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // b=b-1 (count)
+ `MC_SEL_ALU_MC_CONST | ((-1 & 127) << `P_ADDR) | `MC_W_B;
+memory[74] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_W_A; // a=pc (data)
+memory[75] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_SP_PLUS_4; // mem[sp]=a || sp=sp+4 (sp=destination@)
+memory[76] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A | // a=b (count) || goto @wset_loop
+ `MC_BRANCH | ((72 >> 2) << `P_ADDR);
+// wset_end: wcpy_end: sncpy_end:
+memory[80] = `MC_SEL_ADDR_A | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_PC; // pc=mem[a] (a is 0)
+memory[81] = `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) | // b=4
+ `MC_W_B;
+memory[82] = `MC_SEL_ADDR_B | `MC_MEM_R | `MC_SEL_READ_DATA | // sp=mem[b] || goto @fetch
+ `MC_W_SP | `MC_FETCH;
+
+// wcpy_continue1: ------------------------
+memory[84] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a=a+12 save clear stack on mem[4]
+ `MC_SEL_ALU_MC_CONST | (12 << `P_ADDR) | `MC_W_A;
+memory[85] = `MC_SEL_ADDR_B | `MC_MEM_W; // mem[b]=a
+memory[86] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_B; // b=mem[sp] (count)
+memory[87] = `MC_SP_PLUS_4; // sp=sp+4
+memory[88] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_PC;// pc=mem[sp] (destination @)
+memory[89] = `MC_SP_PLUS_4; // sp=sp+4
+memory[90] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_SP;// sp=mem[sp] (source @)
+memory[91] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A; // a=b (count)
+// wcpy_loop:
+memory[92] = `MC_BRANCHIF_A_ZERO | ( (80 >> 2) << `P_ADDR); // if(a==0) goto @wcpy_end
+memory[93] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // b=b-1 (count)
+ `MC_SEL_ALU_MC_CONST | ((-1 & 127) << `P_ADDR) | `MC_W_B;
+memory[94] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM | // a=mem[sp] || sp=sp+4 (sp=source@)
+ `MC_SP_PLUS_4;
+memory[95] = `MC_SEL_ADDR_PC | `MC_MEM_W | `MC_SEL_READ_ADDR | // mem[pc]=a || pc=pc+4 (pc=destination@)
+ `MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) | `MC_W_PC;
+memory[96] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A | // a=b (count) || goto @wcpy_loop
+ `MC_BRANCH | ((92 >> 2) << `P_ADDR);
+
+`ifdef ENABLE_BYTE_SELECT
+// sncpy_continue1: ---------------------
+memory[100] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a=a+12
+ `MC_SEL_ALU_MC_CONST | (12 << `P_ADDR) | `MC_W_A;
+memory[101] = `MC_SEL_ADDR_B | `MC_MEM_W; // mem[b]=a
+memory[102] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_B;// b=mem[sp] (count)
+memory[103] = `MC_SP_PLUS_4; // sp=sp+4
+memory[104] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_PC;// pc=mem[sp] (destination @)
+memory[105] = `MC_SP_PLUS_4; // sp=sp+4
+memory[106] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_SP;// sp=mem[sp] (source @)
+memory[107] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A; // a=b (count)
+// sncpy_loop:
+memory[108] = `MC_BRANCHIF_A_ZERO | ( (80 >> 2) << `P_ADDR); // if(a==0) goto @sncpy_end (count==0?)
+memory[109] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_BYTE | `MC_W_A_MEM | // a=BYTE(mem[sp],sp) || sp=sp+1 (sp=source@)
+ `MC_SEL_READ_ADDR | `MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST |
+ (1 << `P_ADDR) | `MC_W_SP;
+memory[110] = `MC_SEL_ADDR_PC | `MC_MEM_W | `MC_SEL_READ_ADDR | // BYTE(mem[pc],pc)=a || pc=pc+1 (pc=destination@)
+ `MC_BYTE | `MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST |
+ (1 << `P_ADDR) | `MC_W_PC;
+memory[111] = `MC_BRANCHIF_A_ZERO | ( (80 >> 2) << `P_ADDR); // if(a==0) goto @sncpy_end (mem[src]==0?)
+memory[112] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // b=b-1 (count)
+ `MC_SEL_ALU_MC_CONST | ((-1 & 127) << `P_ADDR) | `MC_W_B;
+memory[113] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A | // a=b (count) || goto @sncpy_loop
+ `MC_BRANCH | ((108 >> 2) << `P_ADDR);
+
+// ipsum_continue1: -------------------
+memory[116] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a=a+4
+ `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) | `MC_W_A;
+memory[117] = `MC_SEL_ADDR_B | `MC_MEM_W; // mem[b]=a save return sp on mem[4]
+memory[118] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | // pc=mem[sp] (count)
+ `MC_W_PC;
+memory[119] = `MC_SP_PLUS_4; // sp=sp+4
+memory[120] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | // sp=mem[sp] (start @)
+ `MC_W_SP;
+memory[121] = `MC_SEL_ALU_MC_CONST | (0 << `P_ADDR) | `MC_W_B | // b=0 (sum)
+ `MC_ALU_NOP_B;
+memory[122] = `MC_SEL_ADDR_PC | `MC_SEL_READ_DATA | `MC_W_A; // a=pc (count)
+// ipsum_loop:
+memory[124] = `MC_BRANCHIF_A_ZERO | ((392 >> 2) << `P_ADDR); // a == 0 ? goto @ipsum_end
+
+memory[125] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_HALFWORD | // b=mem[sp]+b
+ `MC_SEL_READ_DATA | `MC_ALU_PLUS | `MC_SEL_ALU_B | `MC_W_B;
+memory[126] = `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // sp=sp+2
+ `MC_SEL_ALU_MC_CONST | (2 << `P_ADDR) | `MC_W_SP;
+memory[127] = `MC_BRANCH | ((408 >> 2) << `P_ADDR); // goto @ipsum_continue2
+`endif
+
+// -------------------------------------------------------------
+
+// 001_00000 (20) wcpy -----------------------------------------
+// before using this opcode you must save mem[0] & mem[4] words, then wcpy, then restore mems
+// c=mem[sp],d=mem[sp+1],s=mem[sp+2]; while(c-->0) mem[d++]=mem[s++]; sp=sp+3
+memory[128] = `MC_CLEAR_IDIM | `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | // b=0
+ (0 << `P_ADDR) | `MC_W_B;
+memory[129] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a=pc+1
+ `MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
+memory[130] = `MC_SEL_ADDR_B | `MC_MEM_W | `MC_ALU_NOP_B | `MC_W_B | // mem[b]=a || b=4
+ `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR);
+memory[131] = `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_W_A | // a=sp || goto @wcpy_continue1
+ `MC_BRANCH | ((84 >> 2) << `P_ADDR);
+
+// 001_00001 (21) wset ----------------------------------------
+// before using this opcode you must save mem[0] & mem[4] words, then wset, then restore mems
+// v=mem[sp],c=mem[sp+1],d=mem[sp+2]; while(c-->0) mem[d++]=v; sp=sp+3
+memory[132] = `MC_CLEAR_IDIM | `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | // b=0
+ (0 << `P_ADDR) | `MC_W_B;
+memory[133] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a=pc+1
+ `MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
+memory[134] = `MC_SEL_ADDR_B | `MC_MEM_W | `MC_ALU_NOP_B | `MC_W_B | // mem[b]=a || b=4
+ `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR);
+memory[135] = `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_W_A | // a=sp || goto @wset_continue1
+ `MC_BRANCH | ((64 >> 2) << `P_ADDR);
+
+// 001_00010 (22) loadh -------------------------------------
+`ifdef ENABLE_BYTE_SELECT
+// mem[sp] = HALFWORD(mem[sp], mem[mem[sp]])
+memory[136] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // a = mem[sp]
+ `MC_MEM_R | `MC_W_A;
+memory[137] = `MC_SEL_ADDR_A | `MC_SEL_READ_DATA | `MC_MEM_R | // a = halfword(a, mem[a])
+ `MC_W_A | `MC_HALFWORD;
+memory[138] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+`else
+memory[136] = `MC_GO_BREAKPOINT;
+`endif
+
+// 001_00011 (23) storeh -------------------------------------
+`ifdef ENABLE_BYTE_SELECT
+// HALFWORD( mem[mem[sp]] <= mem[sp+1] )
+// sp = sp + 2
+memory[140] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // b = mem[sp]
+ `MC_MEM_R | `MC_W_B;
+memory[141] = `MC_SP_PLUS_4; // sp = sp + 1
+memory[142] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM | // a = mem[sp] || sp=sp+1
+ `MC_SP_PLUS_4;
+memory[143] = `MC_SEL_ADDR_B | `MC_MEM_W | `MC_HALFWORD | `MC_GO_NEXT; // HALFWORD(mem[b] = a)
+`else
+memory[140] = `MC_GO_BREAKPOINT;
+`endif
+
+// 001_00100 (24) lessthan -------------------------------------
+// (mem[sp]-mem[sp+1]) < 0 ? mem[sp+1]=1 : mem[sp+1]=0
+// sp=sp+1
+`ifdef ENABLE_CMP
+memory[144] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM | // a=mem[sp] || sp=sp+1
+ `MC_SP_PLUS_4;
+memory[145] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | `MC_W_B; // b=mem[sp]
+memory[146] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B | // a = (a - b) with overflow/underflow correction || goto @lessthan_check
+ `MC_ALU_CMP_SIGNED | `MC_W_A | ((424>>2) << `P_ADDR) | `MC_BRANCH;
+`else
+memory[144] = `MC_GO_BREAKPOINT;
+`endif
+
+// 001_00101 (25) lessthanorequal -------------------------------------
+// (mem[sp]-mem[sp+1]) <= 0 ? mem[sp+1]=1 : mem[sp+1]=0
+// sp=sp+1
+`ifdef ENABLE_CMP
+memory[148] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM | // a=mem[sp] || sp=sp+1
+ `MC_SP_PLUS_4;
+memory[149] = `MC_SEL_ADDR_SP | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_B; // b=mem[sp]
+memory[150] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B | // a = (a - b) with overflow/underflow correction || goto @lessthanorequal_check
+ `MC_ALU_CMP_SIGNED | `MC_W_A | ((420>>2) << `P_ADDR) | `MC_BRANCH;
+`else
+memory[148] = `MC_GO_BREAKPOINT;
+`endif
+
+// 001_00110 (26) ulessthan -------------------------------------
+// signA!=signB -> (unsigA < unsigB) == ~(sigA < sigA)
+// signA==signB -> (unsigA < unsigB) == (sigA < sigB)
+// (mem[sp]-mem[sp+1]) < 0 ? mem[sp+1]=1 : mem[sp+1]=0
+// sp=sp+1
+`ifdef ENABLE_CMP
+memory[152] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM | // a=mem[sp] || sp=sp+1
+ `MC_SP_PLUS_4;
+memory[153] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | `MC_W_B; // b=mem[sp]
+memory[154] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B | // a = (a - b) with overflow/underflow correction || goto @lessthan_check
+ `MC_ALU_CMP_UNSIGNED | `MC_W_A | ((424>>2) << `P_ADDR) | `MC_BRANCH;
+`else
+memory[152] = `MC_GO_BREAKPOINT;
+`endif
+
+// 001_00111 (27) ulessthanorequal -------------------------------------
+// (mem[sp]-mem[sp+1]) <= 0 ? mem[sp+1]=1 : mem[sp+1]=0
+// sp=sp+1
+`ifdef ENABLE_CMP
+memory[156] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM | // a=mem[sp] || sp=sp+1
+ `MC_SP_PLUS_4;
+memory[157] = `MC_SEL_ADDR_SP | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_B; // b=mem[sp]
+memory[158] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B | // a = (a - b) with overflow/underflow correction || goto @lessthanorequal_check
+ `MC_ALU_CMP_UNSIGNED | `MC_W_A | ((420>>2) << `P_ADDR) | `MC_BRANCH;
+`else
+memory[156] = `MC_GO_BREAKPOINT;
+`endif
+
+// 001_01000 (28) swap -------------------------------------
+memory[160] = `MC_GO_BREAKPOINT;
+
+// 001_01001 (29) mult -------------------------------------
+`ifdef ENABLE_MULT
+// mem[sp+1] = mem[sp+1] * mem[sp]
+// sp = sp + 1
+memory[164] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | // a = mem[sp] || sp=sp+1
+ `MC_W_A_MEM | `MC_SP_PLUS_4;
+memory[165] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // b = mem[sp]
+ `MC_W_B;
+memory[166] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B | // a = a * b DON'T COMBINE MULTICYCLE ALU
+ `MC_ALU_MULT | `MC_W_A; // OPERATIONS WITH MEMORY READ/WRITE
+memory[167] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+`else
+memory[164] = `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | (8 << `P_ADDR) | // b = 8 (#2 in emulate table)
+ `MC_W_B;
+memory[165] = `MC_EMULATE; // emulate #2 (mult opcode)
+`endif
+
+// 001_01010 (2a) lshiftright -------------------------------------
+`ifdef ENABLE_BARREL
+// b = mem[sp] & 5'b1111 : limit to 5 bits (max 31 shifts)
+// b = b | 7'b01_00000 : shift right, logical
+// sp=sp+1
+// a = mem[sp]
+// a = a >> b
+// mem[sp] = a
+memory[168] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // b = mem[sp] & 5'b11111
+ `MC_MEM_R | `MC_ALU_AND | `MC_SEL_ALU_MC_CONST | (31 << `P_ADDR) | `MC_W_B;
+memory[169] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_OR | // b = b | 7'b01_00000 (shift right, logical)
+ `MC_SEL_ALU_MC_CONST | (32 << `P_ADDR) | `MC_W_B;
+memory[170] = `MC_SP_PLUS_4; // sp = sp + 1
+memory[171] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // a = mem[sp] | goto @shift_cont
+ `MC_W_A_MEM | `MC_BRANCH | ((432 >> 2) << `P_ADDR);
+`else
+ `ifdef ENABLE_A_SHIFT
+// a = mem[sp] & 5'b11111
+// sp=sp+1
+// b = FLIP(mem[sp])
+// label: a <= 0 ? goto @fin
+// b = b << 1
+// a = a - 1 || goto @label
+// fin: a = FLIP(b)
+// mem[sp]=a
+memory[168] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // a = mem[sp] & 5'b11111
+ `MC_MEM_R | `MC_ALU_AND | `MC_SEL_ALU_MC_CONST |
+ (31 << `P_ADDR) | `MC_W_A;
+memory[169] = `MC_SP_PLUS_4; // sp = sp + 1
+memory[170] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // b = FLIP(mem[sp])
+ `MC_ALU_FLIP | `MC_W_B;
+memory[171] = `MC_BRANCH | ((448 >> 2) << `P_ADDR); // goto @lshiftleft_loop
+ `else
+ memory[168] = `MC_GO_BREAKPOINT;
+ `endif
+`endif
+
+// 001_01011 (2b) ashiftleft -------------------------------------
+`ifdef ENABLE_BARREL
+// b = mem[sp] & 5'b11111 : 5 bit shift
+// b = b | 7'b10_00000 : shift left, arithmetic
+// sp=sp+1
+// a = mem[sp]
+// a = a <<signed b
+// mem[sp] = a
+memory[172] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // b = mem[sp] & 5'b11111
+ `MC_MEM_R | `MC_ALU_AND | `MC_SEL_ALU_MC_CONST | (31 << `P_ADDR) | `MC_W_B;
+memory[173] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_OR | // b = b | 7'b10_00000 (shift left, arithmetic)
+ `MC_SEL_ALU_MC_CONST | (64 << `P_ADDR) | `MC_W_B;
+memory[174] = `MC_SP_PLUS_4; // sp = sp + 1
+memory[175] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // a = mem[sp] | goto @shift_cont
+ `MC_W_A_MEM | `MC_BRANCH | ((432 >> 2) << `P_ADDR);
+`else
+// a = mem[sp] & 5'b11111
+// sp = sp + 1
+// b = mem[sp]
+// label: a <= 0 ? goto @fin
+// b = b << 1
+// a = a - 1 || goto @label
+// fin: a = b
+// mem[sp] = a
+memory[172] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // a = mem[sp] & 5'b11111
+ `MC_MEM_R | `MC_ALU_AND | `MC_SEL_ALU_MC_CONST |
+ (31 << `P_ADDR) | `MC_W_A;
+memory[173] = `MC_SP_PLUS_4; // sp = sp + 1
+memory[174] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // b = mem[sp]
+ `MC_W_B;
+memory[175] = `MC_BRANCH | ((440 >> 2) << `P_ADDR); // goto @ashiftleft_loop
+`endif
+
+// 001_01100 (2c) ashiftright -------------------------------------
+`ifdef ENABLE_BARREL
+// b = mem[sp] & 5'b11111 : 5 bit shift
+// b = b | 7'b00_00000 : shift right, arithmetic
+// sp=sp+1
+// a = mem[sp]
+// a = a >>signed b
+// mem[sp] = a
+memory[176] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // b = mem[sp] & 5'b11111
+ `MC_MEM_R | `MC_ALU_AND | `MC_SEL_ALU_MC_CONST | (31 << `P_ADDR) | `MC_W_B;
+memory[177] = `MC_SP_PLUS_4; // sp = sp + 1
+memory[178] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // a = mem[sp] | goto @shift_cont
+ `MC_W_A_MEM | `MC_BRANCH | ((432 >> 2) << `P_ADDR);
+`else
+ `ifdef ENABLE_A_SHIFT
+// a = mem[sp] & 5'b11111
+// sp = sp + 1
+// b = FLIP(mem[sp])
+// label: a <= 0 ? goto @fin
+// b = b signed_<< 1
+// a = a - 1 || goto @label
+// fin: a = FLIP(b)
+// mem[sp] = a
+memory[176] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // a = mem[sp] & 5'b11111
+ `MC_MEM_R | `MC_ALU_AND | `MC_SEL_ALU_MC_CONST |
+ (31 << `P_ADDR) | `MC_W_A;
+memory[177] = `MC_SP_PLUS_4; // sp = sp + 1
+memory[178] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // b = FLIP(mem[sp])
+ `MC_ALU_FLIP | `MC_W_B;
+memory[179] = `MC_BRANCH | ((432 >> 2) << `P_ADDR); // goto @ashiftright_loop
+ `else
+memory[176] = `MC_GO_BREAKPOINT;
+ `endif
+`endif
+
+// 001_01101 (2d) call -------------------------------------
+// a = mem[sp]
+// mem[sp]=pc+1
+// pc = a
+memory[180] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // b = mem[sp]
+ `MC_MEM_R | `MC_W_B;
+memory[181] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
+ `MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A; // a = pc + 1
+memory[182] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_ALU_NOP_B | // mem[sp] = a || pc = b
+ `MC_SEL_ALU_B | `MC_W_PC;
+memory[183] = `MC_FETCH; // op_cached? decode : goto next
+
+// 001_01110 (2e) eq -------------------------------------
+// a = mem[sp]
+// sp = sp + 1
+// (mem[sp] - a == 0) ? mem[sp] = 1 : mem[sp] = 0
+memory[184] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | // a = NOT(mem[sp])
+ `MC_SEL_READ_DATA | `MC_ALU_NOT | `MC_W_A;
+memory[185] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR |`MC_ALU_PLUS | // a = a + 1
+ `MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
+memory[186] = `MC_SP_PLUS_4; // sp = sp + 1
+memory[187] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // a = mem[sp] + a || goto @eq_check
+ `MC_ALU_PLUS |`MC_SEL_ALU_A | `MC_W_A |
+ ( (416 >> 2) << `P_ADDR) | `MC_BRANCH;
+
+// 001_01111 (2f) neq -------------------------------------
+// a = mem[sp]
+// sp = sp + 1
+// (mem[sp] - a != 0) ? mem[sp] = 1 : mem[sp] = 0
+memory[188] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // a = NOT(mem[sp])
+ `MC_MEM_R | `MC_ALU_NOT | `MC_W_A;
+memory[189] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR |`MC_ALU_PLUS | // a = a + 1
+ `MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
+memory[190] = `MC_SP_PLUS_4; // sp = sp + 1
+memory[191] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // a = mem[sp] + a || goto @neq_check
+ `MC_ALU_PLUS | `MC_SEL_ALU_A | `MC_W_A |
+ ( (412 >> 2) << `P_ADDR) | `MC_BRANCH;
+
+// 001_10000 (30) neg -------------------------------------
+// a = NOT(mem[sp])
+// a = a + 1
+// mem[sp] = a
+memory[192] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // a = NOT(mem[sp])
+ `MC_MEM_R | `MC_ALU_NOT | `MC_W_A;
+memory[193] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a = a + 1
+ (1 << `P_ADDR) | `MC_SEL_ALU_MC_CONST | `MC_W_A;
+memory[194] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+
+// 001_10001 (31) sub -------------------------------------
+// mem[sp+1] = mem[sp+1] - mem[sp]
+// sp = sp + 1
+memory[196] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // a = NOT(mem[sp])
+ `MC_MEM_R | `MC_ALU_NOT | `MC_W_A;
+memory[197] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a = a + 1
+ `MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
+memory[198] = `MC_SP_PLUS_4; // sp = sp + 1
+memory[199] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // a = mem[sp] + a || goto @sub_cont (set_mem[sp]=a)
+ `MC_ALU_PLUS | `MC_SEL_ALU_A | `MC_W_A | ((400>>2) << `P_ADDR) |
+ `MC_BRANCH;
+
+// 001_10010 (32) xor -------------------------------------
+`ifdef ENABLE_XOR
+// mem[sp+1] = mem[sp+1] ^ mem[sp]
+// sp = sp + 1
+memory[200] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | // a = mem[sp] || sp=sp+1
+ `MC_W_A_MEM | `MC_SP_PLUS_4;
+memory[201] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // a = a ^ mem[sp]
+ `MC_ALU_XOR |`MC_SEL_ALU_A | `MC_W_A;
+memory[202] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+`else
+// ALU doesn't perform XOR operation
+// mem[sp+1] = mem[sp] ^ mem[sp+1] -> A^B=(A&~B)|(~A&B)
+// a = ~mem[sp] --> a = ~A
+// sp = sp + 1
+// a = mem[sp] & a --> a = ~A&B
+// b = ~a --> b = A&~B
+// a = a | b --> a = ~A&B | A&~B
+// mem[sp] = a
+memory[200] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // a = ~mem[sp] --> a=~A
+ `MC_ALU_NOT | `MC_W_A;
+memory[201] = `MC_SP_PLUS_4; // sp = sp + 1
+memory[202] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // a = mem[sp] & a --> a = ~A&B
+ `MC_ALU_AND | `MC_SEL_ALU_A | `MC_W_A;
+memory[203] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_NOT | // b = ~a || goto @xor_cont --> b = A&~B
+ `MC_W_B | `MC_BRANCH | ((428 >> 2) << `P_ADDR);
+`endif
+
+// 001_10011 (33) loadb -------------------------------------
+`ifdef ENABLE_BYTE_SELECT
+// mem[sp] = BYTE(mem[sp], mem[mem[sp]])
+memory[204] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // a = mem[sp]
+ `MC_MEM_R | `MC_W_A;
+memory[205] = `MC_SEL_ADDR_A | `MC_SEL_READ_DATA | `MC_MEM_R | // a = byte(a, mem[a])
+ `MC_W_A | `MC_BYTE;
+memory[206] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+`else
+// b=pc
+// pc = mem[sp]
+// opcode_cache=mem[pc]
+// a = opcode
+// mem[sp]=a
+// pc=b
+// fetch
+memory[204] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | // b = pc
+ `MC_W_B;
+memory[205] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // pc = mem[sp]
+ `MC_W_PC;
+memory[206] = `MC_SEL_ADDR_PC | `MC_SEL_READ_DATA | `MC_MEM_R | // opcode_cache = mem[pc]
+ `MC_W_OPCODE;
+memory[207] = `MC_SEL_ALU_OPCODE | `MC_ALU_NOP_B | `MC_W_A | // a = opcode -> byte(pc, mem[pc]) || goto @loadb_continued
+ `MC_BRANCH | ( (396 >> 2) << `P_ADDR);
+`endif
+
+// 001_10100 (34) storeb -------------------------------------
+`ifdef ENABLE_BYTE_SELECT
+// BYTE( mem[mem[sp]] <= mem[sp+1] )
+// sp = sp + 2
+memory[208] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // b = mem[sp]
+ `MC_MEM_R | `MC_W_B;
+memory[209] = `MC_SP_PLUS_4; // sp = sp + 1
+memory[210] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM | // a = mem[sp] || sp=sp+1
+ `MC_SP_PLUS_4;
+memory[211] = `MC_SEL_ADDR_B | `MC_MEM_W | `MC_BYTE | `MC_GO_NEXT; // BYTE(mem[b] = a)
+`else
+memory[208] = `MC_GO_BREAKPOINT;
+`endif
+
+// 001_10101 (35) div -------------------------------------
+`ifdef ENABLE_DIV
+// *** TODO: CHECK IF DIVIDE BY ZERO AND RAISE EXCEPTION ***
+// mem[sp+1] = mem[sp+1] / mem[sp]
+// sp = sp + 1
+memory[212] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | // a = mem[sp] || sp=sp+1
+ `MC_W_A_MEM | `MC_SP_PLUS_4;
+memory[213] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // b = mem[sp]
+ `MC_W_B;
+memory[214] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B | // a = a / b DON'T COMBINE MULTICYCLE ALU
+ `MC_ALU_DIV | `MC_W_A; // OPERATIONS WITH MEMORY READ/WRITE
+memory[215] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+`else
+memory[212] = `MC_GO_BREAKPOINT;
+`endif
+
+// 001_10110 (36) mod -------------------------------------
+`ifdef ENABLE_DIV
+// mem[sp+1] = mem[sp+1] % mem[sp]
+// sp = sp + 1
+memory[216] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | // a = mem[sp] || sp=sp+1
+ `MC_W_A_MEM | `MC_SP_PLUS_4;
+memory[217] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | // b = mem[sp]
+ `MC_W_B;
+memory[218] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B | // a = a % b DON'T COMBINE MULTICYCLE ALU
+ `MC_ALU_MOD | `MC_W_A; // OPERATIONS WITH MEMORY READ/WRITE
+memory[219] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+`else
+memory[216] = `MC_GO_BREAKPOINT;
+`endif
+
+// 001_10111 (37) eqbranch -------------------------------------
+// a = sp + 1
+// a = mem[a]
+// a = mem[sp] || a == 0 ? { pc = pc + a; sp = sp + 2 }
+// else { sp = sp + 2, pc = pc + 1 }
+memory[220] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | // a = sp + 1
+ `MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) |
+ `MC_W_A;
+memory[221] = `MC_SEL_ADDR_A | `MC_MEM_R | `MC_W_A; // a = mem[a]
+memory[222] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A | // a = mem[sp] || a == 0 ? goto 456 (sp=sp+2, pc=pc+a)
+ `MC_BRANCHIF_A_ZERO | ((456>>2) << `P_ADDR);
+memory[223] = `MC_BRANCH | ((460>>2) << `P_ADDR); // else goto 460 (sp=sp+2, pc=pc+1)
+
+// 001_11000 (38) neqbranch -------------------------------------
+// a = sp + 1
+// a = mem[a]
+// a = mem[sp] || a == 0 ? { sp = sp + 2, pc = pc + 1 }
+// else { sp = sp + 2, pc = pc + a }
+memory[224] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | // a = sp + 1
+ `MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) |
+ `MC_W_A;
+memory[225] = `MC_SEL_ADDR_A | `MC_MEM_R | `MC_W_A; // a = mem[a]
+memory[226] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A | // a = mem[sp] || a == 0 ? goto 460 (sp=sp+2, pc=pc+1)
+ `MC_BRANCHIF_A_ZERO | ((460>>2) << `P_ADDR);
+memory[227] = `MC_BRANCH | ((456>>2) << `P_ADDR); // else goto 456 (sp=sp+2, pc=pc+a)
+
+// 001_11001 (39) poppcrel -------------------------------------
+// a = mem[sp]
+// sp = sp + 1
+// pc = pc + a
+memory[228] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | // a=mem[sp] || sp=sp+1
+ `MC_W_A_MEM | `MC_SP_PLUS_4;
+memory[229] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_SEL_ALU_A | // pc = pc + a
+ `MC_ALU_PLUS | `MC_W_PC;
+memory[230] = `MC_FETCH; // op_cached? decode : goto next
+
+// 001_11010 (3a) config -------------------------------------
+memory[232] = `MC_GO_BREAKPOINT;
+
+// 001_11011 (3b) pushpc -------------------------------------
+// sp = sp - 1
+// mem[sp] = pc
+memory[236] = `MC_CLEAR_IDIM | `MC_SP_MINUS_4 | `MC_W_A; // a = sp = sp - 1
+memory[237] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+
+// 001_11100 (3c) syscall_emulate ------------------------------
+memory[240] = `MC_GO_BREAKPOINT;
+
+// 001_11101 (3d) pushspadd -------------------------------------
+// a = mem[sp] << 2
+// mem[sp] = a + sp
+`ifdef ENABLE_BARREL
+memory[244] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | // a = mem[sp]
+ `MC_W_A_MEM;
+memory[245] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_BARREL | // a = a << 2 (left,arithmetic->10_00010)
+ `MC_SEL_ALU_MC_CONST | ( 66 << `P_ADDR) | `MC_W_A;
+memory[246] = `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_SEL_ALU_A | // a = a + sp
+ `MC_ALU_PLUS | `MC_W_A;
+memory[247] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+`else
+memory[244] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM; // a = mem[sp]
+memory[245] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_A | // a = a + a
+ `MC_ALU_PLUS | `MC_W_A;
+memory[246] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_A | // a = a + a
+ `MC_ALU_PLUS | `MC_W_A;
+memory[247] = `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_SEL_ALU_A | // a = a + sp || goto @cont (->mem[sp] = a)
+ `MC_ALU_PLUS | `MC_W_A | ((400>>2) << `P_ADDR) | `MC_BRANCH;
+`endif
+
+// 001_11110 (3e) halfmult -------------------------------------
+memory[248] = `MC_GO_BREAKPOINT;
+
+// 001_11111 (3f) callpcrel -------------------------------------
+// a = mem[sp]
+// mem[sp]=pc+1
+// pc = pc + a
+memory[252] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | // b = mem[sp]
+ `MC_MEM_R | `MC_W_B;
+memory[253] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a = pc + 1
+ `MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
+memory[254] = `MC_SEL_ADDR_SP | `MC_MEM_W; // mem[sp] = a;
+memory[255] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B | // pc = pc + b, goto @fetch
+ `MC_ALU_PLUS | `MC_W_PC | `MC_GO_FETCH;
+
+// --------------------- MICROCODE HOLE -----------------------------------
+
+
+
+
+// --------------------- CONTINUATION OF COMPLEX OPCODES ------------------
+
+`ifdef ENABLE_BYTE_SELECT
+// ipsum_end: ----------
+memory[392] = `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | (0 << `P_ADDR) | // sp=0
+ `MC_W_SP;
+memory[393] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | // pc=mem[sp] restore next pc
+ `MC_W_PC;
+memory[394] = `MC_SP_PLUS_4; // sp=sp+4
+memory[395] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | // sp=mem[sp] restore sp
+ `MC_W_SP;
+memory[396] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A; // a=b (sum)
+memory[397] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_FETCH; // mem[sp]=a || fetch (return sum)
+`endif
+
+`ifndef ENABLE_BYTE_SELECT
+// loadb continued microcode -----
+// mem[sp]=a || pc=b
+// opcode_cache=mem[pc] || go next
+memory[396] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_SEL_ALU_B | // mem[sp]=a || pc=b
+ `MC_ALU_NOP_B | `MC_W_PC;
+memory[397] = `MC_SEL_ADDR_PC | `MC_MEM_R | `MC_W_OPCODE | `MC_GO_NEXT; // opcode_cache=mem[pc] || go next
+`endif
+
+// sub/pushspadd continued microcode ----------------
+memory[400] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+
+// ----- hole ------
+
+`ifdef ENABLE_BYTE_SELECT
+// ipsum_continue2: ------------
+memory[408] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // pc=pc-1; a=pc
+ `MC_SEL_ALU_MC_CONST | ((-1 & 127) << `P_ADDR) | `MC_W_PC |
+ `MC_W_A;
+memory[409] = `MC_BRANCH | ((124 >> 2) << `P_ADDR); // goto @ipsum_loop
+`endif
+
+// neqcheck ----------
+memory[412] = `MC_BRANCHIF_A_ZERO | ((468 >> 2) << `P_ADDR); // a == 0 ? goto @set_mem[sp]=0
+memory[413] = `MC_BRANCH | ((464 >> 2) << `P_ADDR); // else goto @set_mem[sp]=1
+
+// eqcheck ----------
+memory[416] = `MC_BRANCHIF_A_ZERO | ((464 >> 2) << `P_ADDR); // a == 0 ? goto @set_mem[sp]=1
+memory[417] = `MC_BRANCH | ((468 >> 2) << `P_ADDR); // else goto @set_mem[sp]=0
+
+// lessthanorequal_check ----
+memory[420] = `MC_BRANCHIF_A_ZERO | `MC_BRANCHIF_A_NEG | ((464 >> 2) << `P_ADDR); // a <= 0 ? goto @set_mem[sp]=1
+memory[421] = `MC_BRANCH | ((468 >> 2) << `P_ADDR); // else goto @set_mem[sp]=0
+
+// lessthan_check ----
+memory[424] = `MC_BRANCHIF_A_NEG | ((464 >> 2) << `P_ADDR); // a < 0 ? goto @set_mem[sp]=1
+memory[425] = `MC_BRANCH | ((468 >> 2) << `P_ADDR); // else goto @set_mem[sp]=0
+
+// xor_cont continued microcode -----------------------------------
+`ifndef ENABLE_XOR
+memory[428] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_OR | // a = a | b --> a = ~A&B | A&~B
+ `MC_SEL_ALU_B | `MC_W_A;
+memory[429] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+`endif
+
+// ashiftright_loop continued microcode -----------------------------------
+`ifdef ENABLE_BARREL
+memory[432] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_BARREL | // a = a {<<|>>} b
+ `MC_SEL_ALU_B | `MC_W_A;
+memory[433] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+`else
+ `ifdef ENABLE_A_SHIFT
+memory[432] = `MC_BRANCHIF_A_ZERO | `MC_BRANCHIF_A_NEG | ((436 >> 2) << `P_ADDR); // (a <= 0) ? goto @ashiftright_exit
+memory[433] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a = a + (-1)
+ `MC_SEL_ALU_MC_CONST | ( (-1 & 127) << `P_ADDR) | `MC_W_A;
+memory[434] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // b = b signed_<< 1 || goto @ashiftright_loop
+ `MC_SEL_ALU_B | `MC_W_B | `MC_BRANCH | ((432 >>2) << `P_ADDR);
+// ashiftright_exit
+memory[436] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_FLIP | // a = FLIP(b)
+ `MC_W_A;
+memory[437] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+ `endif
+`endif
+
+// ashiftleft_loop continued microcode -----------------------------------
+`ifndef ENABLE_BARREL
+memory[440] = `MC_BRANCHIF_A_ZERO | `MC_BRANCHIF_A_NEG | ((444 >> 2) << `P_ADDR);// (a <= 0) ? goto @ashiftleft_exit
+memory[441] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a = a + (-1)
+ `MC_SEL_ALU_MC_CONST | ( (-1 & 127) << `P_ADDR) | `MC_W_A;
+memory[442] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // b = b << 1 || goto @ashiftleft_loop
+ `MC_SEL_ALU_B | `MC_W_B | `MC_BRANCH | ((440 >>2) << `P_ADDR);
+// ashiftleft_exit
+memory[444] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_NOP | // a = b
+ `MC_W_A;
+memory[445] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+`endif
+
+// lshiftright_loop continued microcode -----------------------------------
+`ifdef ENABLE_A_SHIFT
+memory[448] = `MC_BRANCHIF_A_ZERO | `MC_BRANCHIF_A_NEG | ((452 >> 2) << `P_ADDR);// (a <= 0) ? goto @lshiftright_exit
+memory[449] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a = a + (-1)
+ `MC_SEL_ALU_MC_CONST | ( (-1 & 127) << `P_ADDR) | `MC_W_A;
+memory[450] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // b = b << 1 || goto @lshiftright_loop
+ `MC_SEL_ALU_B | `MC_W_B | `MC_BRANCH | ((448 >>2) << `P_ADDR);
+// lshiftright_exit
+memory[452] = `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_FLIP | // a = FLIP(b)
+ `MC_W_A;
+memory[453] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+`endif
+
+// neqbranch / eqbranch --- continued microcode -------------------------------------
+// sp = sp + 2
+// pc = pc + a
+memory[456] = `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // sp = sp + 2
+ `MC_SEL_ALU_MC_CONST | (8 << `P_ADDR) | `MC_W_SP;
+memory[457] = `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_SEL_ALU_A | // pc = pc + a
+ `MC_ALU_PLUS | `MC_W_PC;
+memory[458] = `MC_FETCH; // op_cached? decode : goto fetch
+
+// neqbranch / eqbranch --- continued microcode -------------------------------------
+// sp = sp + 2
+// pc = pc + 1
+memory[460] = `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // sp = sp + 2
+ `MC_SEL_ALU_MC_CONST | (8 << `P_ADDR) | `MC_W_SP;
+memory[461] = `MC_PC_PLUS_1; // pc = pc + 1
+memory[462] = `MC_FETCH; // op_cached? decode : goto fetch
+
+// neq / eq / lessthan_1 --- continued microcode --------------------
+// mem[sp] = 1
+memory[464] = `MC_SEL_ALU_MC_CONST | `MC_ALU_NOP_B | (1 << `P_ADDR) | // a = 1
+ `MC_W_A;
+memory[465] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+
+// neq / eq / lessthan_0 --- continued microcode --------------------
+// mem[sp] = 0
+memory[468] = `MC_SEL_ALU_MC_CONST | `MC_ALU_NOP_B | (0 << `P_ADDR) | // a = 0
+ `MC_W_A;
+memory[469] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+
+// MICROCODE ENTRY POINT AFTER RESET -------------------------------
+// initialize cpu registers
+// sp = @SP_START
+// pc = @RESET_VECTOR
+memory[473] = 0; // reserved and empty for correct cpu startup
+memory[474] = `MC_CLEAR_IDIM |`MC_SEL_ALU_MC_CONST | `MC_ALU_NOP_B | // sp = @SP_START
+ (`SP_START << `P_ADDR) | `MC_W_SP;
+memory[475] = `MC_SEL_ALU_MC_CONST | `MC_ALU_NOP_B | `MC_W_PC | // pc = @RESET
+ (`RESET_VECTOR << `P_ADDR) | `MC_EXIT_INTERRUPT; // enable interrupts on reset
+// fall throught fetch/decode
+
+// FETCH / DECODE -------------------------------------
+// opcode=mem[pc]
+// decode (goto microcode entry point for opcode)
+memory[476] = `MC_SEL_ADDR_PC | `MC_SEL_READ_DATA | `MC_MEM_R | // opcode_cache = mem[pc]
+ `MC_W_OPCODE;
+memory[477] = `MC_DECODE; // decode jump to microcode
+
+// NEXT OPCODE -------------------------------------
+// pc = pc + 1
+// opcode cached ? decode : goto fetch
+memory[480] = `MC_PC_PLUS_1; // pc = pc + 1
+memory[481] = `MC_FETCH; // pc_cached ? decode else fetch,decode
+
+// INTERRUPT REQUEST -------------------------------------
+// sp = sp - 1
+// mem[sp] = pc
+// pc = mem[EMULATED_VECTORS + 0]
+memory[484] = `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | (0 << `P_ADDR) | // b = 0 (#0 in emulate table) || disable interrupts
+ `MC_W_B | `MC_ENTER_INTERRUPT;
+memory[485] = `MC_EMULATE; // emulate #0 (interrupt)
+
+// ---------------- OPCODES WITH PARAMETER IN OPCODE ----------------
+
+// im x (idim=0) 1_xxxxxxx -------------------------------------
+// sp = sp - 1
+// mem[sp] = IMM(IDIM, opcode)
+// idim = 1
+memory[488] = `MC_SP_MINUS_4; // sp = sp - 1
+memory[489] = `MC_SEL_ALU_OPCODE | `MC_ALU_IM | `MC_W_A; // a = IMM(IDIM, opcode)
+memory[490] = `MC_SET_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_W | // MEM[sp] = a; IDIM=1
+ `MC_GO_NEXT;
+
+// 1_xxxxxxx im x (idim=1) -------------------------------------
+// mem[sp] = IMM(IDIM, mem[sp], opcode)
+memory[491] = `MC_SET_IDIM | `MC_SEL_READ_DATA | `MC_SEL_ADDR_SP | // a = IMM(IDIM, MEM[sp], opcode)
+ `MC_MEM_R | `MC_SEL_ALU_OPCODE | `MC_ALU_IM | `MC_W_A;
+memory[492] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // MEM[sp] = a
+
+// 010_xxxxx storesp x
+// mem[sp + x<<2] = mem[sp]
+// sp = sp + 1
+memory[493] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | // b = sp + offset
+ `MC_ALU_PLUS_OFFSET | `MC_SEL_ALU_OPCODE | `MC_W_B;
+memory[494] = `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM | // a=mem[sp] || sp=sp+1
+ `MC_SP_PLUS_4;
+memory[495] = `MC_SEL_ADDR_B | `MC_MEM_W | `MC_GO_NEXT; // mem[b] = a
+
+// 011_xxxxx loadsp x -------------------------------------
+// mem[sp-1] = mem [sp + x<<2]
+// sp = sp - 1
+memory[496] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | // a = sp + offset
+ `MC_ALU_PLUS_OFFSET | `MC_SEL_ALU_OPCODE | `MC_W_A;
+memory[497] = `MC_SEL_ADDR_A | `MC_SEL_READ_DATA | `MC_MEM_R | `MC_W_A; // a = mem[a]
+memory[498] = `MC_SP_MINUS_4; // sp = sp - 1
+memory[499] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+
+// 0001_xxxx addsp x -------------------------------------
+// mem[sp] = mem[sp] + mem[sp + x<<2]
+memory[500] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | // a = sp + offset
+ `MC_ALU_PLUS_OFFSET | `MC_SEL_ALU_OPCODE | `MC_W_A;
+memory[501] = `MC_SEL_ADDR_A | `MC_SEL_READ_DATA | `MC_MEM_R | `MC_W_A; // a = mem[a]
+memory[502] = `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
+ `MC_ALU_PLUS | `MC_SEL_ALU_A | `MC_W_A; // a = a + mem[sp]
+memory[503] = `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT; // mem[sp] = a
+
+// 001_xxxxx emulate x -------------------------------------
+// <expects b = offset into table for emulated opcode>
+// sp = sp - 1
+// mem[sp] = pc + 1 emulated opcode microcode must set b to
+// a=@EMULATION_TABLE offset inside emulated_table prior to
+// pc = mem[a + b] calling the emulate microcode
+// fetch
+memory[504] = `MC_CLEAR_IDIM | `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | // a = pc + 1
+ `MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
+memory[505] = `MC_SP_MINUS_4; // sp = sp - 1
+memory[506] = `MC_SEL_ADDR_SP | `MC_MEM_W; // mem[sp] = a
+memory[507] = `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | `MC_W_A | // a = @vector_emulated
+ (`EMULATION_VECTOR << `P_ADDR);
+memory[508] = `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | // a = a + b
+ `MC_SEL_ALU_B | `MC_W_A;
+memory[509] = `MC_SEL_ADDR_A | `MC_MEM_R | `MC_SEL_READ_DATA | // pc = mem[a]
+ `MC_ALU_NOP | `MC_W_PC;
+memory[510] = `MC_FETCH;
+
+// --------------------- END OF MICROCODE PROGRAM --------------------------
+end
+
+endmodule
diff --git a/zpu/hdl/avalanche/readme.txt b/zpu/hdl/avalanche/readme.txt
new file mode 100644
index 0000000..3eb1baf
--- /dev/null
+++ b/zpu/hdl/avalanche/readme.txt
@@ -0,0 +1,91 @@
+This ZPU implementation, codenamed "avalanche" was
+contributed by Antonio Anton <antonio.anton@anro-ingenieros.com>.
+
+It's most interesting aspects are it's implementation using
+microcode, small size, reduced code size overhead and that
+it's implemented in Verilog.
+
+Please direct any questions to the zylin-zpu mailing list.
+
+The most urgently needed patches would be to provide working
+simulation examples and improved documentation.
+
+
+Øyvind Harboe
+
+
+Notes from Antonio:
+
+Hi,
+
+attached goes my zpu implementation in verilog in case anybody is
+interested in. Code is quite commented. Also microcode and opcodes are
+exhaustive commented (and more accurate that the HTML documentation in
+some cases :-) ).
+
+At the moment I have no time to send a working environment but I will
+get some time in next days and prepare a clean environment
+(software/hardware) and send to the list. The target HW is spartan3
+starter kit board (all peripherals working: vga, sram, uarts, etc.).
+
+Feel free to ask any question to the list I will do my best to answer
+quickly.
+
+Regards
+Antonio
+
+Hi,
+
+the zpu_core is complete and lot of bugs has been solved in the past but
+extensive testing and a complete test program has not been
+defined/executed; anyway I'm quite confident it works: this core
+executes eCos, FreeRTOS, Forth and other applications.
+
+Regarding FPGA resources for a "balanced" implementation (not the
+smallest, not the fastest):
+
+-cpu+alu+microcode rom: 671 LUT + 239 FF + 1 BRAM (50% of LUT is ALU)
+-complete soc (cpu, vga, uart, memory controller, interrupt controller,
+timers, gpio, spi, etc.): 1317 LUT + 716 FF + 1 BRAM
+
+Regarding "modelsim hello world"; I'm sorry but I don't modelsim;
+instead I use Icarus Verilog & gtkwave. The core has a "debug" facility
+which displays all opcode and registers (memory changes, sp, pc, etc..)
+during simulation execution.
+
+Regards
+Antonio
+
+
+> > Regarding FPGA resources for a "balanced" implementation (not the
+> > smallest, not the fastest):
+> >
+> > -cpu+alu+microcode rom: 671 LUT + 239 FF + 1 BRAM (50% of LUT is ALU)
+>
+> Are there any emulated instructions not implemented in
+> microcode?
+>
+
+*All* zpu opcodes are microcoded. For some opcodes (like *shift*),
+there are two versions; 32 bit barrel shift in HDL (up to 32 clocks) or
+1 bit shift in HDL microcode drived (up to ~130 clocks). They are
+selectable via `DEFINES in the zpu_core_defines.v
+
+Other opcodes like mult and div are 32 bit HDL only at the moment (there
+are enough room in microcode memory to implement as microcode) and
+software emulable as well.
+
+For the above figures (671 LUT + 239 FF): *shift* are 32 bit HDL and
+mult/div are software implemented.
+
+There are new opcodes (as per my needs) like memory bulk copy (sncpy,
+wcpy, wset) and ip checksum calculation (ipsum). There are room in
+microccode memory to define new opcodes using the holes in the ISA (for
+a complete list of opcodes and its function please see
+zpu_core_defines.v).
+
+Some future ideas (easy to implement in microcode)
+-on-chip debug
+-microcode update via software
+
+Regards
diff --git a/zpu/hdl/example/.cvsignore b/zpu/hdl/example/.cvsignore
new file mode 100644
index 0000000..8238018
--- /dev/null
+++ b/zpu/hdl/example/.cvsignore
@@ -0,0 +1,3 @@
+work
+vsim.wlf
+install
diff --git a/zpu/hdl/example/bram_dmips.vhd b/zpu/hdl/example/bram_dmips.vhd
new file mode 100644
index 0000000..07b19f4
--- /dev/null
+++ b/zpu/hdl/example/bram_dmips.vhd
@@ -0,0 +1,3356 @@
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+--
+-- The FreeBSD license
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+--
+-- 1. Redistributions of source code must retain the above copyright
+-- notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+-- copyright notice, this list of conditions and the following
+-- disclaimer in the documentation and/or other materials
+-- provided with the distribution.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity dualport_ram is
+port (clk : in std_logic;
+ memAWriteEnable : in std_logic;
+ memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+ memAWrite : in std_logic_vector(wordSize-1 downto 0);
+ memARead : out std_logic_vector(wordSize-1 downto 0);
+ memBWriteEnable : in std_logic;
+ memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+ memBWrite : in std_logic_vector(wordSize-1 downto 0);
+ memBRead : out std_logic_vector(wordSize-1 downto 0));
+end dualport_ram;
+
+architecture dualport_ram_arch of dualport_ram is
+
+
+type ram_type is array(natural range 0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
+
+shared variable ram : ram_type :=
+(
+ 0 => x"0b0b0b0b",
+ 1 => x"82700b0b",
+ 2 => x"80d5f40c",
+ 3 => x"3a0b0b80",
+ 4 => x"c4fb0400",
+ 5 => x"00000000",
+ 6 => x"00000000",
+ 7 => x"00000000",
+ 8 => x"80088408",
+ 9 => x"88080b0b",
+ 10 => x"80c5c22d",
+ 11 => x"880c840c",
+ 12 => x"800c0400",
+ 13 => x"00000000",
+ 14 => x"00000000",
+ 15 => x"00000000",
+ 16 => x"71fd0608",
+ 17 => x"72830609",
+ 18 => x"81058205",
+ 19 => x"832b2a83",
+ 20 => x"ffff0652",
+ 21 => x"04000000",
+ 22 => x"00000000",
+ 23 => x"00000000",
+ 24 => x"71fd0608",
+ 25 => x"83ffff73",
+ 26 => x"83060981",
+ 27 => x"05820583",
+ 28 => x"2b2b0906",
+ 29 => x"7383ffff",
+ 30 => x"0b0b0b0b",
+ 31 => x"83a70400",
+ 32 => x"72098105",
+ 33 => x"72057373",
+ 34 => x"09060906",
+ 35 => x"73097306",
+ 36 => x"070a8106",
+ 37 => x"53510400",
+ 38 => x"00000000",
+ 39 => x"00000000",
+ 40 => x"72722473",
+ 41 => x"732e0753",
+ 42 => x"51040000",
+ 43 => x"00000000",
+ 44 => x"00000000",
+ 45 => x"00000000",
+ 46 => x"00000000",
+ 47 => x"00000000",
+ 48 => x"71737109",
+ 49 => x"71068106",
+ 50 => x"30720a10",
+ 51 => x"0a720a10",
+ 52 => x"0a31050a",
+ 53 => x"81065151",
+ 54 => x"53510400",
+ 55 => x"00000000",
+ 56 => x"72722673",
+ 57 => x"732e0753",
+ 58 => x"51040000",
+ 59 => x"00000000",
+ 60 => x"00000000",
+ 61 => x"00000000",
+ 62 => x"00000000",
+ 63 => x"00000000",
+ 64 => x"00000000",
+ 65 => x"00000000",
+ 66 => x"00000000",
+ 67 => x"00000000",
+ 68 => x"00000000",
+ 69 => x"00000000",
+ 70 => x"00000000",
+ 71 => x"00000000",
+ 72 => x"0b0b0b88",
+ 73 => x"c3040000",
+ 74 => x"00000000",
+ 75 => x"00000000",
+ 76 => x"00000000",
+ 77 => x"00000000",
+ 78 => x"00000000",
+ 79 => x"00000000",
+ 80 => x"720a722b",
+ 81 => x"0a535104",
+ 82 => x"00000000",
+ 83 => x"00000000",
+ 84 => x"00000000",
+ 85 => x"00000000",
+ 86 => x"00000000",
+ 87 => x"00000000",
+ 88 => x"72729f06",
+ 89 => x"0981050b",
+ 90 => x"0b0b88a6",
+ 91 => x"05040000",
+ 92 => x"00000000",
+ 93 => x"00000000",
+ 94 => x"00000000",
+ 95 => x"00000000",
+ 96 => x"72722aff",
+ 97 => x"739f062a",
+ 98 => x"0974090a",
+ 99 => x"8106ff05",
+ 100 => x"06075351",
+ 101 => x"04000000",
+ 102 => x"00000000",
+ 103 => x"00000000",
+ 104 => x"71715351",
+ 105 => x"020d0406",
+ 106 => x"73830609",
+ 107 => x"81058205",
+ 108 => x"832b0b2b",
+ 109 => x"0772fc06",
+ 110 => x"0c515104",
+ 111 => x"00000000",
+ 112 => x"72098105",
+ 113 => x"72050970",
+ 114 => x"81050906",
+ 115 => x"0a810653",
+ 116 => x"51040000",
+ 117 => x"00000000",
+ 118 => x"00000000",
+ 119 => x"00000000",
+ 120 => x"72098105",
+ 121 => x"72050970",
+ 122 => x"81050906",
+ 123 => x"0a098106",
+ 124 => x"53510400",
+ 125 => x"00000000",
+ 126 => x"00000000",
+ 127 => x"00000000",
+ 128 => x"71098105",
+ 129 => x"52040000",
+ 130 => x"00000000",
+ 131 => x"00000000",
+ 132 => x"00000000",
+ 133 => x"00000000",
+ 134 => x"00000000",
+ 135 => x"00000000",
+ 136 => x"72720981",
+ 137 => x"05055351",
+ 138 => x"04000000",
+ 139 => x"00000000",
+ 140 => x"00000000",
+ 141 => x"00000000",
+ 142 => x"00000000",
+ 143 => x"00000000",
+ 144 => x"72097206",
+ 145 => x"73730906",
+ 146 => x"07535104",
+ 147 => x"00000000",
+ 148 => x"00000000",
+ 149 => x"00000000",
+ 150 => x"00000000",
+ 151 => x"00000000",
+ 152 => x"71fc0608",
+ 153 => x"72830609",
+ 154 => x"81058305",
+ 155 => x"1010102a",
+ 156 => x"81ff0652",
+ 157 => x"04000000",
+ 158 => x"00000000",
+ 159 => x"00000000",
+ 160 => x"71fc0608",
+ 161 => x"0b0b80d5",
+ 162 => x"e0738306",
+ 163 => x"10100508",
+ 164 => x"060b0b0b",
+ 165 => x"88a90400",
+ 166 => x"00000000",
+ 167 => x"00000000",
+ 168 => x"80088408",
+ 169 => x"88087575",
+ 170 => x"0b0b0bad",
+ 171 => x"aa2d5050",
+ 172 => x"80085688",
+ 173 => x"0c840c80",
+ 174 => x"0c510400",
+ 175 => x"00000000",
+ 176 => x"80088408",
+ 177 => x"88087575",
+ 178 => x"0b0b0bad",
+ 179 => x"ee2d5050",
+ 180 => x"80085688",
+ 181 => x"0c840c80",
+ 182 => x"0c510400",
+ 183 => x"00000000",
+ 184 => x"72097081",
+ 185 => x"0509060a",
+ 186 => x"8106ff05",
+ 187 => x"70547106",
+ 188 => x"73097274",
+ 189 => x"05ff0506",
+ 190 => x"07515151",
+ 191 => x"04000000",
+ 192 => x"72097081",
+ 193 => x"0509060a",
+ 194 => x"098106ff",
+ 195 => x"05705471",
+ 196 => x"06730972",
+ 197 => x"7405ff05",
+ 198 => x"06075151",
+ 199 => x"51040000",
+ 200 => x"05ff0504",
+ 201 => x"00000000",
+ 202 => x"00000000",
+ 203 => x"00000000",
+ 204 => x"00000000",
+ 205 => x"00000000",
+ 206 => x"00000000",
+ 207 => x"00000000",
+ 208 => x"810b0b0b",
+ 209 => x"80d5f00c",
+ 210 => x"51040000",
+ 211 => x"00000000",
+ 212 => x"00000000",
+ 213 => x"00000000",
+ 214 => x"00000000",
+ 215 => x"00000000",
+ 216 => x"71810552",
+ 217 => x"04000000",
+ 218 => x"00000000",
+ 219 => x"00000000",
+ 220 => x"00000000",
+ 221 => x"00000000",
+ 222 => x"00000000",
+ 223 => x"00000000",
+ 224 => x"00000000",
+ 225 => x"00000000",
+ 226 => x"00000000",
+ 227 => x"00000000",
+ 228 => x"00000000",
+ 229 => x"00000000",
+ 230 => x"00000000",
+ 231 => x"00000000",
+ 232 => x"02840572",
+ 233 => x"10100552",
+ 234 => x"04000000",
+ 235 => x"00000000",
+ 236 => x"00000000",
+ 237 => x"00000000",
+ 238 => x"00000000",
+ 239 => x"00000000",
+ 240 => x"00000000",
+ 241 => x"00000000",
+ 242 => x"00000000",
+ 243 => x"00000000",
+ 244 => x"00000000",
+ 245 => x"00000000",
+ 246 => x"00000000",
+ 247 => x"00000000",
+ 248 => x"717105ff",
+ 249 => x"05715351",
+ 250 => x"020d0400",
+ 251 => x"00000000",
+ 252 => x"00000000",
+ 253 => x"00000000",
+ 254 => x"00000000",
+ 255 => x"00000000",
+ 256 => x"82fd3fbf",
+ 257 => x"a03f0410",
+ 258 => x"10101010",
+ 259 => x"10101010",
+ 260 => x"10101010",
+ 261 => x"10101010",
+ 262 => x"10101010",
+ 263 => x"10101010",
+ 264 => x"10101010",
+ 265 => x"10105351",
+ 266 => x"047381ff",
+ 267 => x"06738306",
+ 268 => x"09810583",
+ 269 => x"05101010",
+ 270 => x"2b0772fc",
+ 271 => x"060c5151",
+ 272 => x"043c0472",
+ 273 => x"72807281",
+ 274 => x"06ff0509",
+ 275 => x"72060571",
+ 276 => x"1052720a",
+ 277 => x"100a5372",
+ 278 => x"ed385151",
+ 279 => x"535104ff",
+ 280 => x"3d0d0b0b",
+ 281 => x"80e5e408",
+ 282 => x"52710870",
+ 283 => x"882a8132",
+ 284 => x"70810651",
+ 285 => x"515170f1",
+ 286 => x"3873720c",
+ 287 => x"833d0d04",
+ 288 => x"80d5f008",
+ 289 => x"802ea438",
+ 290 => x"80d5f408",
+ 291 => x"822ebd38",
+ 292 => x"8380800b",
+ 293 => x"0b0b80e5",
+ 294 => x"e40c82a0",
+ 295 => x"800b80e5",
+ 296 => x"e80c8290",
+ 297 => x"800b80e5",
+ 298 => x"ec0c04f8",
+ 299 => x"808080a4",
+ 300 => x"0b0b0b80",
+ 301 => x"e5e40cf8",
+ 302 => x"80808280",
+ 303 => x"0b80e5e8",
+ 304 => x"0cf88080",
+ 305 => x"84800b80",
+ 306 => x"e5ec0c04",
+ 307 => x"80c0a880",
+ 308 => x"8c0b0b0b",
+ 309 => x"80e5e40c",
+ 310 => x"80c0a880",
+ 311 => x"940b80e5",
+ 312 => x"e80c0b0b",
+ 313 => x"80c7d00b",
+ 314 => x"80e5ec0c",
+ 315 => x"04f23d0d",
+ 316 => x"6080e5e8",
+ 317 => x"08565d82",
+ 318 => x"750c8059",
+ 319 => x"805a800b",
+ 320 => x"8f3d5d5b",
+ 321 => x"7a101015",
+ 322 => x"70087108",
+ 323 => x"719f2c7e",
+ 324 => x"852b5855",
+ 325 => x"557d5359",
+ 326 => x"5799993f",
+ 327 => x"7d7f7a72",
+ 328 => x"077c7207",
+ 329 => x"71716081",
+ 330 => x"05415f5d",
+ 331 => x"5b595755",
+ 332 => x"817b278f",
+ 333 => x"38767d0c",
+ 334 => x"77841e0c",
+ 335 => x"7c800c90",
+ 336 => x"3d0d0480",
+ 337 => x"e5e80855",
+ 338 => x"ffba3970",
+ 339 => x"7080e5f0",
+ 340 => x"335170a7",
+ 341 => x"3880d5fc",
+ 342 => x"08700852",
+ 343 => x"5270802e",
+ 344 => x"94388412",
+ 345 => x"80d5fc0c",
+ 346 => x"702d80d5",
+ 347 => x"fc087008",
+ 348 => x"525270ee",
+ 349 => x"38810b80",
+ 350 => x"e5f03450",
+ 351 => x"50040470",
+ 352 => x"0b0b80e5",
+ 353 => x"e008802e",
+ 354 => x"8e380b0b",
+ 355 => x"0b0b800b",
+ 356 => x"802e0981",
+ 357 => x"06833850",
+ 358 => x"040b0b80",
+ 359 => x"e5e0510b",
+ 360 => x"0b0bf4dc",
+ 361 => x"3f500404",
+ 362 => x"ff3d0d02",
+ 363 => x"8f053352",
+ 364 => x"718a2e8a",
+ 365 => x"387151fd",
+ 366 => x"a63f833d",
+ 367 => x"0d048d51",
+ 368 => x"fd9d3f71",
+ 369 => x"51fd983f",
+ 370 => x"833d0d04",
+ 371 => x"ce3d0db5",
+ 372 => x"3d707084",
+ 373 => x"0552088b",
+ 374 => x"a85c56a5",
+ 375 => x"3d5e5c80",
+ 376 => x"75708105",
+ 377 => x"5733765b",
+ 378 => x"55587378",
+ 379 => x"2e80c138",
+ 380 => x"8e3d5b73",
+ 381 => x"a52e0981",
+ 382 => x"0680c538",
+ 383 => x"78708105",
+ 384 => x"5a335473",
+ 385 => x"80e42e81",
+ 386 => x"b6387380",
+ 387 => x"e42480c6",
+ 388 => x"387380e3",
+ 389 => x"2ea13880",
+ 390 => x"52a55179",
+ 391 => x"2d805273",
+ 392 => x"51792d82",
+ 393 => x"18587870",
+ 394 => x"81055a33",
+ 395 => x"5473c438",
+ 396 => x"77800cb4",
+ 397 => x"3d0d047b",
+ 398 => x"841d8312",
+ 399 => x"33565d57",
+ 400 => x"80527351",
+ 401 => x"792d8118",
+ 402 => x"79708105",
+ 403 => x"5b335558",
+ 404 => x"73ffa038",
+ 405 => x"db397380",
+ 406 => x"f32e0981",
+ 407 => x"06ffb838",
+ 408 => x"7b841d71",
+ 409 => x"08595d56",
+ 410 => x"80773355",
+ 411 => x"5673762e",
+ 412 => x"8d388116",
+ 413 => x"70187033",
+ 414 => x"57555674",
+ 415 => x"f538ff16",
+ 416 => x"55807625",
+ 417 => x"ffa03876",
+ 418 => x"70810558",
+ 419 => x"33548052",
+ 420 => x"7351792d",
+ 421 => x"811875ff",
+ 422 => x"17575758",
+ 423 => x"807625ff",
+ 424 => x"85387670",
+ 425 => x"81055833",
+ 426 => x"54805273",
+ 427 => x"51792d81",
+ 428 => x"1875ff17",
+ 429 => x"57575875",
+ 430 => x"8024cc38",
+ 431 => x"fee8397b",
+ 432 => x"841d7108",
+ 433 => x"70719f2c",
+ 434 => x"5953595d",
+ 435 => x"56807524",
+ 436 => x"81913875",
+ 437 => x"7d7c5856",
+ 438 => x"54805773",
+ 439 => x"772e0981",
+ 440 => x"06b638b0",
+ 441 => x"7b3402b5",
+ 442 => x"05567a76",
+ 443 => x"2e9738ff",
+ 444 => x"16567533",
+ 445 => x"75708105",
+ 446 => x"57348117",
+ 447 => x"577a762e",
+ 448 => x"098106eb",
+ 449 => x"38807534",
+ 450 => x"767dff12",
+ 451 => x"57585675",
+ 452 => x"8024fef3",
+ 453 => x"38fe8f39",
+ 454 => x"8a527351",
+ 455 => x"9fd03f80",
+ 456 => x"0880c7d4",
+ 457 => x"05337670",
+ 458 => x"81055834",
+ 459 => x"8a527351",
+ 460 => x"9ef83f80",
+ 461 => x"08548008",
+ 462 => x"802effae",
+ 463 => x"388a5273",
+ 464 => x"519fab3f",
+ 465 => x"800880c7",
+ 466 => x"d4053376",
+ 467 => x"70810558",
+ 468 => x"348a5273",
+ 469 => x"519ed33f",
+ 470 => x"80085480",
+ 471 => x"08ffb938",
+ 472 => x"ff883974",
+ 473 => x"527653b4",
+ 474 => x"3dffb805",
+ 475 => x"51949a3f",
+ 476 => x"a33d0856",
+ 477 => x"fedd3980",
+ 478 => x"3d0d80c1",
+ 479 => x"0b81b4bc",
+ 480 => x"34800b81",
+ 481 => x"b6980c70",
+ 482 => x"800c823d",
+ 483 => x"0d04ff3d",
+ 484 => x"0d800b81",
+ 485 => x"b4bc3352",
+ 486 => x"527080c1",
+ 487 => x"2e993871",
+ 488 => x"81b69808",
+ 489 => x"0781b698",
+ 490 => x"0c80c20b",
+ 491 => x"81b4c034",
+ 492 => x"70800c83",
+ 493 => x"3d0d0481",
+ 494 => x"0b81b698",
+ 495 => x"080781b6",
+ 496 => x"980c80c2",
+ 497 => x"0b81b4c0",
+ 498 => x"3470800c",
+ 499 => x"833d0d04",
+ 500 => x"fd3d0d75",
+ 501 => x"70088a05",
+ 502 => x"535381b4",
+ 503 => x"bc335170",
+ 504 => x"80c12e8b",
+ 505 => x"3873f338",
+ 506 => x"70800c85",
+ 507 => x"3d0d04ff",
+ 508 => x"127081b4",
+ 509 => x"b8083174",
+ 510 => x"0c800c85",
+ 511 => x"3d0d04fc",
+ 512 => x"3d0d81b4",
+ 513 => x"c4085574",
+ 514 => x"802e8c38",
+ 515 => x"76750871",
+ 516 => x"0c81b4c4",
+ 517 => x"0856548c",
+ 518 => x"155381b4",
+ 519 => x"b808528a",
+ 520 => x"518fd43f",
+ 521 => x"73800c86",
+ 522 => x"3d0d04fb",
+ 523 => x"3d0d7770",
+ 524 => x"085656b0",
+ 525 => x"5381b4c4",
+ 526 => x"08527451",
+ 527 => x"ab943f85",
+ 528 => x"0b8c170c",
+ 529 => x"850b8c16",
+ 530 => x"0c750875",
+ 531 => x"0c81b4c4",
+ 532 => x"08547380",
+ 533 => x"2e8a3873",
+ 534 => x"08750c81",
+ 535 => x"b4c40854",
+ 536 => x"8c145381",
+ 537 => x"b4b80852",
+ 538 => x"8a518f8b",
+ 539 => x"3f841508",
+ 540 => x"ad38860b",
+ 541 => x"8c160c88",
+ 542 => x"15528816",
+ 543 => x"08518e97",
+ 544 => x"3f81b4c4",
+ 545 => x"08700876",
+ 546 => x"0c548c15",
+ 547 => x"7054548a",
+ 548 => x"52730851",
+ 549 => x"8ee13f73",
+ 550 => x"800c873d",
+ 551 => x"0d047508",
+ 552 => x"54b05373",
+ 553 => x"527551aa",
+ 554 => x"a93f7380",
+ 555 => x"0c873d0d",
+ 556 => x"04d93d0d",
+ 557 => x"b0519dcf",
+ 558 => x"3f800881",
+ 559 => x"b4b40cb0",
+ 560 => x"519dc43f",
+ 561 => x"800881b4",
+ 562 => x"c40c81b4",
+ 563 => x"b4088008",
+ 564 => x"0c800b80",
+ 565 => x"0884050c",
+ 566 => x"820b8008",
+ 567 => x"88050ca8",
+ 568 => x"0b80088c",
+ 569 => x"050c9f53",
+ 570 => x"80c7e052",
+ 571 => x"80089005",
+ 572 => x"51a9df3f",
+ 573 => x"a13d5e9f",
+ 574 => x"5380c880",
+ 575 => x"527d51a9",
+ 576 => x"d13f8a0b",
+ 577 => x"80f2f80c",
+ 578 => x"80d2a451",
+ 579 => x"f9be3f80",
+ 580 => x"c8a051f9",
+ 581 => x"b73f80d2",
+ 582 => x"a451f9b0",
+ 583 => x"3f80d684",
+ 584 => x"08802e89",
+ 585 => x"d33880c8",
+ 586 => x"d051f9a0",
+ 587 => x"3f80d2a4",
+ 588 => x"51f9993f",
+ 589 => x"80d68008",
+ 590 => x"5280c8fc",
+ 591 => x"51f98d3f",
+ 592 => x"80e69451",
+ 593 => x"b2ff3f81",
+ 594 => x"0b9a3d5e",
+ 595 => x"5b800b80",
+ 596 => x"d6800825",
+ 597 => x"82d43890",
+ 598 => x"3d5f80c1",
+ 599 => x"0b81b4bc",
+ 600 => x"34810b81",
+ 601 => x"b6980c80",
+ 602 => x"c20b81b4",
+ 603 => x"c0348240",
+ 604 => x"835a9f53",
+ 605 => x"80c9ac52",
+ 606 => x"7c51a8d6",
+ 607 => x"3f814180",
+ 608 => x"7d537e52",
+ 609 => x"568e943f",
+ 610 => x"8008762e",
+ 611 => x"09810683",
+ 612 => x"38815675",
+ 613 => x"81b6980c",
+ 614 => x"7f705856",
+ 615 => x"758325a2",
+ 616 => x"38751010",
+ 617 => x"16fd0542",
+ 618 => x"a93dffa4",
+ 619 => x"05538352",
+ 620 => x"76518cc3",
+ 621 => x"3f7f8105",
+ 622 => x"70417058",
+ 623 => x"56837624",
+ 624 => x"e0386154",
+ 625 => x"755380e6",
+ 626 => x"9c5281b4",
+ 627 => x"d0518cb7",
+ 628 => x"3f81b4c4",
+ 629 => x"08700858",
+ 630 => x"58b05377",
+ 631 => x"527651a7",
+ 632 => x"f13f850b",
+ 633 => x"8c190c85",
+ 634 => x"0b8c180c",
+ 635 => x"7708770c",
+ 636 => x"81b4c408",
+ 637 => x"5675802e",
+ 638 => x"8a387508",
+ 639 => x"770c81b4",
+ 640 => x"c408568c",
+ 641 => x"165381b4",
+ 642 => x"b808528a",
+ 643 => x"518be83f",
+ 644 => x"84170887",
+ 645 => x"ea38860b",
+ 646 => x"8c180c88",
+ 647 => x"17528818",
+ 648 => x"08518af3",
+ 649 => x"3f81b4c4",
+ 650 => x"08700878",
+ 651 => x"0c568c17",
+ 652 => x"7054598a",
+ 653 => x"52780851",
+ 654 => x"8bbd3f80",
+ 655 => x"c10b81b4",
+ 656 => x"c0335757",
+ 657 => x"767626a2",
+ 658 => x"3880c352",
+ 659 => x"76518ca1",
+ 660 => x"3f800861",
+ 661 => x"2e89e438",
+ 662 => x"81177081",
+ 663 => x"ff0681b4",
+ 664 => x"c0335858",
+ 665 => x"58757727",
+ 666 => x"e0387960",
+ 667 => x"29627054",
+ 668 => x"71535b59",
+ 669 => x"98b43f80",
+ 670 => x"0840787a",
+ 671 => x"31708729",
+ 672 => x"80083180",
+ 673 => x"088a0581",
+ 674 => x"b4bc3381",
+ 675 => x"b4b8085e",
+ 676 => x"5b525a56",
+ 677 => x"7780c12e",
+ 678 => x"89ce387b",
+ 679 => x"f738811b",
+ 680 => x"5b80d680",
+ 681 => x"087b25fd",
+ 682 => x"b13881b4",
+ 683 => x"ac51b095",
+ 684 => x"3f80c9cc",
+ 685 => x"51f6953f",
+ 686 => x"80d2a451",
+ 687 => x"f68e3f80",
+ 688 => x"c9dc51f6",
+ 689 => x"873f80d2",
+ 690 => x"a451f680",
+ 691 => x"3f81b4b8",
+ 692 => x"085280ca",
+ 693 => x"9451f5f4",
+ 694 => x"3f855280",
+ 695 => x"cab051f5",
+ 696 => x"eb3f81b6",
+ 697 => x"98085280",
+ 698 => x"cacc51f5",
+ 699 => x"df3f8152",
+ 700 => x"80cab051",
+ 701 => x"f5d63f81",
+ 702 => x"b4bc3352",
+ 703 => x"80cae851",
+ 704 => x"f5ca3f80",
+ 705 => x"c15280cb",
+ 706 => x"8451f5c0",
+ 707 => x"3f81b4c0",
+ 708 => x"335280cb",
+ 709 => x"a051f5b4",
+ 710 => x"3f80c252",
+ 711 => x"80cb8451",
+ 712 => x"f5aa3f81",
+ 713 => x"b4f00852",
+ 714 => x"80cbbc51",
+ 715 => x"f59e3f87",
+ 716 => x"5280cab0",
+ 717 => x"51f5953f",
+ 718 => x"80f2f808",
+ 719 => x"5280cbd8",
+ 720 => x"51f5893f",
+ 721 => x"80cbf451",
+ 722 => x"f5823f80",
+ 723 => x"cca051f4",
+ 724 => x"fb3f81b4",
+ 725 => x"c4087008",
+ 726 => x"535a80cc",
+ 727 => x"ac51f4ec",
+ 728 => x"3f80ccc8",
+ 729 => x"51f4e53f",
+ 730 => x"81b4c408",
+ 731 => x"84110853",
+ 732 => x"5680ccfc",
+ 733 => x"51f4d53f",
+ 734 => x"805280ca",
+ 735 => x"b051f4cc",
+ 736 => x"3f81b4c4",
+ 737 => x"08881108",
+ 738 => x"535880cd",
+ 739 => x"9851f4bc",
+ 740 => x"3f825280",
+ 741 => x"cab051f4",
+ 742 => x"b33f81b4",
+ 743 => x"c4088c11",
+ 744 => x"08535780",
+ 745 => x"cdb451f4",
+ 746 => x"a33f9152",
+ 747 => x"80cab051",
+ 748 => x"f49a3f81",
+ 749 => x"b4c40890",
+ 750 => x"055280cd",
+ 751 => x"d051f48c",
+ 752 => x"3f80cdec",
+ 753 => x"51f4853f",
+ 754 => x"80cea451",
+ 755 => x"f3fe3f81",
+ 756 => x"b4b40870",
+ 757 => x"08535f80",
+ 758 => x"ccac51f3",
+ 759 => x"ef3f80ce",
+ 760 => x"b851f3e8",
+ 761 => x"3f81b4b4",
+ 762 => x"08841108",
+ 763 => x"535b80cc",
+ 764 => x"fc51f3d8",
+ 765 => x"3f805280",
+ 766 => x"cab051f3",
+ 767 => x"cf3f81b4",
+ 768 => x"b4088811",
+ 769 => x"08535c80",
+ 770 => x"cd9851f3",
+ 771 => x"bf3f8152",
+ 772 => x"80cab051",
+ 773 => x"f3b63f81",
+ 774 => x"b4b4088c",
+ 775 => x"1108535a",
+ 776 => x"80cdb451",
+ 777 => x"f3a63f92",
+ 778 => x"5280cab0",
+ 779 => x"51f39d3f",
+ 780 => x"81b4b408",
+ 781 => x"90055280",
+ 782 => x"cdd051f3",
+ 783 => x"8f3f80cd",
+ 784 => x"ec51f388",
+ 785 => x"3f7f5280",
+ 786 => x"cef851f2",
+ 787 => x"ff3f8552",
+ 788 => x"80cab051",
+ 789 => x"f2f63f78",
+ 790 => x"5280cf94",
+ 791 => x"51f2ed3f",
+ 792 => x"8d5280ca",
+ 793 => x"b051f2e4",
+ 794 => x"3f615280",
+ 795 => x"cfb051f2",
+ 796 => x"db3f8752",
+ 797 => x"80cab051",
+ 798 => x"f2d23f60",
+ 799 => x"5280cfcc",
+ 800 => x"51f2c93f",
+ 801 => x"815280ca",
+ 802 => x"b051f2c0",
+ 803 => x"3f7d5280",
+ 804 => x"cfe851f2",
+ 805 => x"b73f80d0",
+ 806 => x"8451f2b0",
+ 807 => x"3f7c5280",
+ 808 => x"d0bc51f2",
+ 809 => x"a73f80d0",
+ 810 => x"d851f2a0",
+ 811 => x"3f80d2a4",
+ 812 => x"51f2993f",
+ 813 => x"81b4ac08",
+ 814 => x"81b4b008",
+ 815 => x"80e69408",
+ 816 => x"80e69808",
+ 817 => x"72713170",
+ 818 => x"74267574",
+ 819 => x"31707231",
+ 820 => x"80e68c0c",
+ 821 => x"444480e6",
+ 822 => x"900c80e6",
+ 823 => x"90085680",
+ 824 => x"d190555c",
+ 825 => x"595758f1",
+ 826 => x"e33f80e6",
+ 827 => x"8c085680",
+ 828 => x"762582a3",
+ 829 => x"3880d680",
+ 830 => x"0870719f",
+ 831 => x"2c9a3d53",
+ 832 => x"565680e6",
+ 833 => x"8c0880e6",
+ 834 => x"90084153",
+ 835 => x"7f547052",
+ 836 => x"5a89eb3f",
+ 837 => x"66685f80",
+ 838 => x"e5fc0c7d",
+ 839 => x"80e6800c",
+ 840 => x"80d68008",
+ 841 => x"709f2c58",
+ 842 => x"568058bd",
+ 843 => x"84c07855",
+ 844 => x"55765275",
+ 845 => x"53795187",
+ 846 => x"d13f953d",
+ 847 => x"80e68c08",
+ 848 => x"80e69008",
+ 849 => x"41557f56",
+ 850 => x"67694053",
+ 851 => x"7e547052",
+ 852 => x"5c89ab3f",
+ 853 => x"64665e80",
+ 854 => x"e6840c7c",
+ 855 => x"80e6880c",
+ 856 => x"80d68008",
+ 857 => x"709f2c40",
+ 858 => x"58805783",
+ 859 => x"dceb9480",
+ 860 => x"7755557e",
+ 861 => x"5277537b",
+ 862 => x"51878f3f",
+ 863 => x"64665d5b",
+ 864 => x"805e8ddd",
+ 865 => x"7e555580",
+ 866 => x"e68c0880",
+ 867 => x"e6900859",
+ 868 => x"52775379",
+ 869 => x"5186f33f",
+ 870 => x"66684054",
+ 871 => x"7e557a52",
+ 872 => x"7b53a93d",
+ 873 => x"ffa80551",
+ 874 => x"88d43f62",
+ 875 => x"645e81b4",
+ 876 => x"c80c7c81",
+ 877 => x"b4cc0c80",
+ 878 => x"d1a051f0",
+ 879 => x"8f3f80e6",
+ 880 => x"80085280",
+ 881 => x"d1d051f0",
+ 882 => x"833f80d1",
+ 883 => x"d851effc",
+ 884 => x"3f80e688",
+ 885 => x"085280d1",
+ 886 => x"d051eff0",
+ 887 => x"3f81b4cc",
+ 888 => x"085280d2",
+ 889 => x"8851efe4",
+ 890 => x"3f80d2a4",
+ 891 => x"51efdd3f",
+ 892 => x"800b800c",
+ 893 => x"a93d0d04",
+ 894 => x"80d2a851",
+ 895 => x"f6ac3977",
+ 896 => x"0857b053",
+ 897 => x"76527751",
+ 898 => x"9fc83f80",
+ 899 => x"c10b81b4",
+ 900 => x"c0335757",
+ 901 => x"f8ae3975",
+ 902 => x"8a3880e6",
+ 903 => x"90088126",
+ 904 => x"fdd33880",
+ 905 => x"d2d851ef",
+ 906 => x"a33f80d3",
+ 907 => x"9051ef9c",
+ 908 => x"3f80d2a4",
+ 909 => x"51ef953f",
+ 910 => x"80d68008",
+ 911 => x"70719f2c",
+ 912 => x"9a3d5356",
+ 913 => x"5680e68c",
+ 914 => x"0880e690",
+ 915 => x"0841537f",
+ 916 => x"5470525a",
+ 917 => x"87a83f66",
+ 918 => x"685f80e5",
+ 919 => x"fc0c7d80",
+ 920 => x"e6800c80",
+ 921 => x"d6800870",
+ 922 => x"9f2c5856",
+ 923 => x"8058bd84",
+ 924 => x"c0785555",
+ 925 => x"76527553",
+ 926 => x"7951858e",
+ 927 => x"3f953d80",
+ 928 => x"e68c0880",
+ 929 => x"e6900841",
+ 930 => x"557f5667",
+ 931 => x"6940537e",
+ 932 => x"5470525c",
+ 933 => x"86e83f64",
+ 934 => x"665e80e6",
+ 935 => x"840c7c80",
+ 936 => x"e6880c80",
+ 937 => x"d6800870",
+ 938 => x"9f2c4058",
+ 939 => x"805783dc",
+ 940 => x"eb948077",
+ 941 => x"55557e52",
+ 942 => x"77537b51",
+ 943 => x"84cc3f64",
+ 944 => x"665d5b80",
+ 945 => x"5e8ddd7e",
+ 946 => x"555580e6",
+ 947 => x"8c0880e6",
+ 948 => x"90085952",
+ 949 => x"77537951",
+ 950 => x"84b03f66",
+ 951 => x"6840547e",
+ 952 => x"557a527b",
+ 953 => x"53a93dff",
+ 954 => x"a8055186",
+ 955 => x"913f6264",
+ 956 => x"5e81b4c8",
+ 957 => x"0c7c81b4",
+ 958 => x"cc0c80d1",
+ 959 => x"a051edcc",
+ 960 => x"3f80e680",
+ 961 => x"085280d1",
+ 962 => x"d051edc0",
+ 963 => x"3f80d1d8",
+ 964 => x"51edb93f",
+ 965 => x"80e68808",
+ 966 => x"5280d1d0",
+ 967 => x"51edad3f",
+ 968 => x"81b4cc08",
+ 969 => x"5280d288",
+ 970 => x"51eda13f",
+ 971 => x"80d2a451",
+ 972 => x"ed9a3f80",
+ 973 => x"0b800ca9",
+ 974 => x"3d0d04a9",
+ 975 => x"3dffa005",
+ 976 => x"52805180",
+ 977 => x"d23f9f53",
+ 978 => x"80d3b052",
+ 979 => x"7c519d82",
+ 980 => x"3f7a7b81",
+ 981 => x"b4b80c81",
+ 982 => x"187081ff",
+ 983 => x"0681b4c0",
+ 984 => x"33595959",
+ 985 => x"5af5fe39",
+ 986 => x"ff16707b",
+ 987 => x"31600c5c",
+ 988 => x"800b811c",
+ 989 => x"5c5c80d6",
+ 990 => x"80087b25",
+ 991 => x"f3dc38f6",
+ 992 => x"a939ff3d",
+ 993 => x"0d738232",
+ 994 => x"70307072",
+ 995 => x"07802580",
+ 996 => x"0c525283",
+ 997 => x"3d0d04fe",
+ 998 => x"3d0d7476",
+ 999 => x"71535452",
+ 1000 => x"71822e83",
+ 1001 => x"38835171",
+ 1002 => x"812e9a38",
+ 1003 => x"8172269f",
+ 1004 => x"3871822e",
+ 1005 => x"b8387184",
+ 1006 => x"2ea93870",
+ 1007 => x"730c7080",
+ 1008 => x"0c843d0d",
+ 1009 => x"0480e40b",
+ 1010 => x"81b4b808",
+ 1011 => x"258b3880",
+ 1012 => x"730c7080",
+ 1013 => x"0c843d0d",
+ 1014 => x"0483730c",
+ 1015 => x"70800c84",
+ 1016 => x"3d0d0482",
+ 1017 => x"730c7080",
+ 1018 => x"0c843d0d",
+ 1019 => x"0481730c",
+ 1020 => x"70800c84",
+ 1021 => x"3d0d0480",
+ 1022 => x"3d0d7474",
+ 1023 => x"14820571",
+ 1024 => x"0c800c82",
+ 1025 => x"3d0d04f7",
+ 1026 => x"3d0d7b7d",
+ 1027 => x"7f618512",
+ 1028 => x"70822b75",
+ 1029 => x"11707471",
+ 1030 => x"70840553",
+ 1031 => x"0c5a5a5d",
+ 1032 => x"5b760c79",
+ 1033 => x"80f8180c",
+ 1034 => x"79861252",
+ 1035 => x"57585a5a",
+ 1036 => x"76762499",
+ 1037 => x"3876b329",
+ 1038 => x"822b7911",
+ 1039 => x"51537673",
+ 1040 => x"70840555",
+ 1041 => x"0c811454",
+ 1042 => x"757425f2",
+ 1043 => x"387681cc",
+ 1044 => x"2919fc11",
+ 1045 => x"088105fc",
+ 1046 => x"120c7a19",
+ 1047 => x"70089fa0",
+ 1048 => x"130c5856",
+ 1049 => x"850b81b4",
+ 1050 => x"b80c7580",
+ 1051 => x"0c8b3d0d",
+ 1052 => x"04fe3d0d",
+ 1053 => x"02930533",
+ 1054 => x"51800284",
+ 1055 => x"05970533",
+ 1056 => x"54527073",
+ 1057 => x"2e883871",
+ 1058 => x"800c843d",
+ 1059 => x"0d047081",
+ 1060 => x"b4bc3481",
+ 1061 => x"0b800c84",
+ 1062 => x"3d0d04f8",
+ 1063 => x"3d0d7a7c",
+ 1064 => x"5956820b",
+ 1065 => x"83195555",
+ 1066 => x"74167033",
+ 1067 => x"75335b51",
+ 1068 => x"5372792e",
+ 1069 => x"80c63880",
+ 1070 => x"c10b8116",
+ 1071 => x"81165656",
+ 1072 => x"57827525",
+ 1073 => x"e338ffa9",
+ 1074 => x"177081ff",
+ 1075 => x"06555973",
+ 1076 => x"82268338",
+ 1077 => x"87558153",
+ 1078 => x"7680d22e",
+ 1079 => x"98387752",
+ 1080 => x"75519bc3",
+ 1081 => x"3f805372",
+ 1082 => x"80082589",
+ 1083 => x"38871581",
+ 1084 => x"b4b80c81",
+ 1085 => x"5372800c",
+ 1086 => x"8a3d0d04",
+ 1087 => x"7281b4bc",
+ 1088 => x"34827525",
+ 1089 => x"ffa238ff",
+ 1090 => x"bd39ef3d",
+ 1091 => x"0d636567",
+ 1092 => x"5b427943",
+ 1093 => x"67695940",
+ 1094 => x"77415a80",
+ 1095 => x"5d805e61",
+ 1096 => x"7083ffff",
+ 1097 => x"0671902a",
+ 1098 => x"627083ff",
+ 1099 => x"ff067190",
+ 1100 => x"2a747229",
+ 1101 => x"74732975",
+ 1102 => x"73297774",
+ 1103 => x"2973902a",
+ 1104 => x"05721151",
+ 1105 => x"5856535f",
+ 1106 => x"5a575a58",
+ 1107 => x"55587373",
+ 1108 => x"27863884",
+ 1109 => x"80801656",
+ 1110 => x"73902a16",
+ 1111 => x"5b7883ff",
+ 1112 => x"ff067484",
+ 1113 => x"80802905",
+ 1114 => x"5c7a7c5a",
+ 1115 => x"5d785e77",
+ 1116 => x"7f296178",
+ 1117 => x"29057d05",
+ 1118 => x"5d7c7e56",
+ 1119 => x"7a0c7484",
+ 1120 => x"1b0c7980",
+ 1121 => x"0c933d0d",
+ 1122 => x"04f93d0d",
+ 1123 => x"797b7d54",
+ 1124 => x"58725977",
+ 1125 => x"30797030",
+ 1126 => x"7072079f",
+ 1127 => x"2a737131",
+ 1128 => x"5a525977",
+ 1129 => x"7956730c",
+ 1130 => x"53738413",
+ 1131 => x"0c54800c",
+ 1132 => x"893d0d04",
+ 1133 => x"f93d0d79",
+ 1134 => x"7b7d7f56",
+ 1135 => x"54525472",
+ 1136 => x"802ea038",
+ 1137 => x"70577158",
+ 1138 => x"a0733152",
+ 1139 => x"807225a1",
+ 1140 => x"38777074",
+ 1141 => x"2b577073",
+ 1142 => x"2a78752b",
+ 1143 => x"07565174",
+ 1144 => x"76535170",
+ 1145 => x"740c7184",
+ 1146 => x"150c7380",
+ 1147 => x"0c893d0d",
+ 1148 => x"04805677",
+ 1149 => x"72302b55",
+ 1150 => x"74765351",
+ 1151 => x"e639e43d",
+ 1152 => x"0d6ea13d",
+ 1153 => x"08a33d08",
+ 1154 => x"59575f80",
+ 1155 => x"764d774e",
+ 1156 => x"a33d08a5",
+ 1157 => x"3d08574b",
+ 1158 => x"754c5e7d",
+ 1159 => x"6c2486fb",
+ 1160 => x"38806a24",
+ 1161 => x"878f3869",
+ 1162 => x"6b58566b",
+ 1163 => x"6d5d467b",
+ 1164 => x"47754476",
+ 1165 => x"45646468",
+ 1166 => x"685c5c56",
+ 1167 => x"567481e7",
+ 1168 => x"38787627",
+ 1169 => x"82c73875",
+ 1170 => x"81ff2683",
+ 1171 => x"2b5583ff",
+ 1172 => x"ff76278c",
+ 1173 => x"389055fe",
+ 1174 => x"800a7627",
+ 1175 => x"83389855",
+ 1176 => x"75752a80",
+ 1177 => x"d3d00570",
+ 1178 => x"33a07731",
+ 1179 => x"71315755",
+ 1180 => x"5774802e",
+ 1181 => x"95387575",
+ 1182 => x"2ba07631",
+ 1183 => x"7a772b7c",
+ 1184 => x"722a077c",
+ 1185 => x"782b5d5b",
+ 1186 => x"59567590",
+ 1187 => x"2a7683ff",
+ 1188 => x"ff067154",
+ 1189 => x"7a535957",
+ 1190 => x"88803f80",
+ 1191 => x"085b87ea",
+ 1192 => x"3f800880",
+ 1193 => x"0879297c",
+ 1194 => x"902b7c90",
+ 1195 => x"2a075656",
+ 1196 => x"59737527",
+ 1197 => x"94388008",
+ 1198 => x"ff057615",
+ 1199 => x"55597574",
+ 1200 => x"26873874",
+ 1201 => x"742687b9",
+ 1202 => x"38765273",
+ 1203 => x"75315187",
+ 1204 => x"c93f8008",
+ 1205 => x"5587b33f",
+ 1206 => x"80088008",
+ 1207 => x"79297b83",
+ 1208 => x"ffff0677",
+ 1209 => x"902b0756",
+ 1210 => x"59577378",
+ 1211 => x"27963880",
+ 1212 => x"08ff0576",
+ 1213 => x"15555775",
+ 1214 => x"74268938",
+ 1215 => x"77742677",
+ 1216 => x"71315856",
+ 1217 => x"78902b77",
+ 1218 => x"0758805b",
+ 1219 => x"7a407741",
+ 1220 => x"7f615654",
+ 1221 => x"7d80d938",
+ 1222 => x"737f0c74",
+ 1223 => x"7f84050c",
+ 1224 => x"7e800c9e",
+ 1225 => x"3d0d0480",
+ 1226 => x"705c5874",
+ 1227 => x"7926dd38",
+ 1228 => x"7481ff26",
+ 1229 => x"832b5774",
+ 1230 => x"83ffff26",
+ 1231 => x"82a53874",
+ 1232 => x"772a80d3",
+ 1233 => x"d0057033",
+ 1234 => x"a0793171",
+ 1235 => x"31595c5d",
+ 1236 => x"7682b338",
+ 1237 => x"76547479",
+ 1238 => x"27833881",
+ 1239 => x"54797627",
+ 1240 => x"74075981",
+ 1241 => x"5878ffa2",
+ 1242 => x"38765880",
+ 1243 => x"5bff9d39",
+ 1244 => x"73527453",
+ 1245 => x"9e3de805",
+ 1246 => x"51fc8e3f",
+ 1247 => x"6769567f",
+ 1248 => x"0c747f84",
+ 1249 => x"050c7e80",
+ 1250 => x"0c9e3d0d",
+ 1251 => x"0475802e",
+ 1252 => x"81c43875",
+ 1253 => x"81ff2683",
+ 1254 => x"2b5583ff",
+ 1255 => x"ff76278c",
+ 1256 => x"389055fe",
+ 1257 => x"800a7627",
+ 1258 => x"83389855",
+ 1259 => x"75752a80",
+ 1260 => x"d3d00570",
+ 1261 => x"33a07731",
+ 1262 => x"7131575e",
+ 1263 => x"54748491",
+ 1264 => x"38787631",
+ 1265 => x"54817690",
+ 1266 => x"2a7783ff",
+ 1267 => x"ff065f5d",
+ 1268 => x"5b7b5273",
+ 1269 => x"5185c33f",
+ 1270 => x"80085785",
+ 1271 => x"ad3f8008",
+ 1272 => x"80087e29",
+ 1273 => x"78902b7c",
+ 1274 => x"902a0756",
+ 1275 => x"56597375",
+ 1276 => x"27943880",
+ 1277 => x"08ff0576",
+ 1278 => x"15555975",
+ 1279 => x"74268738",
+ 1280 => x"74742684",
+ 1281 => x"f3387b52",
+ 1282 => x"73753151",
+ 1283 => x"858c3f80",
+ 1284 => x"085584f6",
+ 1285 => x"3f800880",
+ 1286 => x"087e297b",
+ 1287 => x"83ffff06",
+ 1288 => x"77902b07",
+ 1289 => x"56595773",
+ 1290 => x"78279638",
+ 1291 => x"8008ff05",
+ 1292 => x"76155557",
+ 1293 => x"75742689",
+ 1294 => x"38777426",
+ 1295 => x"77713158",
+ 1296 => x"5a78902b",
+ 1297 => x"77077b41",
+ 1298 => x"417f6156",
+ 1299 => x"547d802e",
+ 1300 => x"fdc638fe",
+ 1301 => x"9b397552",
+ 1302 => x"815184ae",
+ 1303 => x"3f800856",
+ 1304 => x"feb13990",
+ 1305 => x"57fe800a",
+ 1306 => x"7527fdd3",
+ 1307 => x"38987571",
+ 1308 => x"2a80d3d0",
+ 1309 => x"057033a0",
+ 1310 => x"73317131",
+ 1311 => x"535d5e57",
+ 1312 => x"76802efd",
+ 1313 => x"cf38a077",
+ 1314 => x"3175782b",
+ 1315 => x"77722a07",
+ 1316 => x"77792b7b",
+ 1317 => x"7a2b7d74",
+ 1318 => x"2a077d7b",
+ 1319 => x"2b73902a",
+ 1320 => x"7483ffff",
+ 1321 => x"0671597f",
+ 1322 => x"772a585e",
+ 1323 => x"5c415f58",
+ 1324 => x"5c5483e6",
+ 1325 => x"3f800854",
+ 1326 => x"83d03f80",
+ 1327 => x"08800879",
+ 1328 => x"2975902b",
+ 1329 => x"7e902a07",
+ 1330 => x"56565973",
+ 1331 => x"75279938",
+ 1332 => x"8008ff05",
+ 1333 => x"7b155559",
+ 1334 => x"7a74268c",
+ 1335 => x"38737527",
+ 1336 => x"8738ff19",
+ 1337 => x"7b155559",
+ 1338 => x"76527375",
+ 1339 => x"315183aa",
+ 1340 => x"3f800855",
+ 1341 => x"83943f80",
+ 1342 => x"08800879",
+ 1343 => x"297d83ff",
+ 1344 => x"ff067790",
+ 1345 => x"2b075659",
+ 1346 => x"57737827",
+ 1347 => x"99388008",
+ 1348 => x"ff057b15",
+ 1349 => x"55577a74",
+ 1350 => x"268c3873",
+ 1351 => x"78278738",
+ 1352 => x"ff177b15",
+ 1353 => x"55577378",
+ 1354 => x"3179902b",
+ 1355 => x"78077083",
+ 1356 => x"ffff0671",
+ 1357 => x"902a7983",
+ 1358 => x"ffff067a",
+ 1359 => x"902a7372",
+ 1360 => x"29737329",
+ 1361 => x"74732976",
+ 1362 => x"74297390",
+ 1363 => x"2a057205",
+ 1364 => x"5755435f",
+ 1365 => x"5b585a57",
+ 1366 => x"595a747c",
+ 1367 => x"27863884",
+ 1368 => x"80801757",
+ 1369 => x"74902a17",
+ 1370 => x"7983ffff",
+ 1371 => x"06768480",
+ 1372 => x"80290557",
+ 1373 => x"57767a26",
+ 1374 => x"9a38767a",
+ 1375 => x"32703070",
+ 1376 => x"72078025",
+ 1377 => x"565a5b7c",
+ 1378 => x"7627fafe",
+ 1379 => x"3873802e",
+ 1380 => x"faf838ff",
+ 1381 => x"1858805b",
+ 1382 => x"faf239ff",
+ 1383 => x"76537754",
+ 1384 => x"9f3de805",
+ 1385 => x"525ef7e1",
+ 1386 => x"3f676957",
+ 1387 => x"4c754d69",
+ 1388 => x"8025f8f3",
+ 1389 => x"387d096a",
+ 1390 => x"6c5c537a",
+ 1391 => x"549f3de8",
+ 1392 => x"05525ef7",
+ 1393 => x"c43f6769",
+ 1394 => x"714c704d",
+ 1395 => x"5856f8db",
+ 1396 => x"39a07531",
+ 1397 => x"76762b7a",
+ 1398 => x"772b7c73",
+ 1399 => x"2a077c78",
+ 1400 => x"2b72902a",
+ 1401 => x"7383ffff",
+ 1402 => x"0671587e",
+ 1403 => x"762a5742",
+ 1404 => x"405d5d57",
+ 1405 => x"5881a33f",
+ 1406 => x"80085781",
+ 1407 => x"8d3f8008",
+ 1408 => x"80087e29",
+ 1409 => x"78902b7d",
+ 1410 => x"902a0756",
+ 1411 => x"56597375",
+ 1412 => x"27993880",
+ 1413 => x"08ff0576",
+ 1414 => x"15555975",
+ 1415 => x"74268c38",
+ 1416 => x"73752787",
+ 1417 => x"38ff1976",
+ 1418 => x"1555597b",
+ 1419 => x"52737531",
+ 1420 => x"5180e73f",
+ 1421 => x"80085580",
+ 1422 => x"d13f8008",
+ 1423 => x"80087e29",
+ 1424 => x"7c83ffff",
+ 1425 => x"06707890",
+ 1426 => x"2b075156",
+ 1427 => x"58587377",
+ 1428 => x"27993880",
+ 1429 => x"08ff0576",
+ 1430 => x"15555875",
+ 1431 => x"74268c38",
+ 1432 => x"73772787",
+ 1433 => x"38ff1876",
+ 1434 => x"15555878",
+ 1435 => x"902b7807",
+ 1436 => x"74783155",
+ 1437 => x"5bfada39",
+ 1438 => x"ff197615",
+ 1439 => x"5559fb86",
+ 1440 => x"39ff1976",
+ 1441 => x"155559f8",
+ 1442 => x"c0397070",
+ 1443 => x"70805375",
+ 1444 => x"52745181",
+ 1445 => x"913f5050",
+ 1446 => x"50047070",
+ 1447 => x"70815375",
+ 1448 => x"52745181",
+ 1449 => x"813f5050",
+ 1450 => x"5004fb3d",
+ 1451 => x"0d777955",
+ 1452 => x"55805675",
+ 1453 => x"7524ab38",
+ 1454 => x"8074249d",
+ 1455 => x"38805373",
+ 1456 => x"52745180",
+ 1457 => x"e13f8008",
+ 1458 => x"5475802e",
+ 1459 => x"85388008",
+ 1460 => x"30547380",
+ 1461 => x"0c873d0d",
+ 1462 => x"04733076",
+ 1463 => x"81325754",
+ 1464 => x"dc397430",
+ 1465 => x"55815673",
+ 1466 => x"8025d238",
+ 1467 => x"ec39fa3d",
+ 1468 => x"0d787a57",
+ 1469 => x"55805776",
+ 1470 => x"7524a438",
+ 1471 => x"759f2c54",
+ 1472 => x"81537574",
+ 1473 => x"32743152",
+ 1474 => x"74519b3f",
+ 1475 => x"80085476",
+ 1476 => x"802e8538",
+ 1477 => x"80083054",
+ 1478 => x"73800c88",
+ 1479 => x"3d0d0474",
+ 1480 => x"30558157",
+ 1481 => x"d739fc3d",
+ 1482 => x"0d767853",
+ 1483 => x"54815380",
+ 1484 => x"74732652",
+ 1485 => x"5572802e",
+ 1486 => x"98387080",
+ 1487 => x"2eab3880",
+ 1488 => x"7224a638",
+ 1489 => x"71107310",
+ 1490 => x"75722653",
+ 1491 => x"545272ea",
+ 1492 => x"38735178",
+ 1493 => x"83387451",
+ 1494 => x"70800c86",
+ 1495 => x"3d0d0472",
+ 1496 => x"0a100a72",
+ 1497 => x"0a100a53",
+ 1498 => x"5372802e",
+ 1499 => x"e4387174",
+ 1500 => x"26ed3873",
+ 1501 => x"72317574",
+ 1502 => x"07740a10",
+ 1503 => x"0a740a10",
+ 1504 => x"0a555556",
+ 1505 => x"54e33970",
+ 1506 => x"70735280",
+ 1507 => x"decc0851",
+ 1508 => x"933f5050",
+ 1509 => x"04707073",
+ 1510 => x"5280decc",
+ 1511 => x"085190ce",
+ 1512 => x"3f505004",
+ 1513 => x"f43d0d7e",
+ 1514 => x"608b1170",
+ 1515 => x"f8065b55",
+ 1516 => x"555d7296",
+ 1517 => x"26833890",
+ 1518 => x"58807824",
+ 1519 => x"74792607",
+ 1520 => x"55805474",
+ 1521 => x"742e0981",
+ 1522 => x"0680ca38",
+ 1523 => x"7c518d9e",
+ 1524 => x"3f7783f7",
+ 1525 => x"2680c538",
+ 1526 => x"77832a70",
+ 1527 => x"10101080",
+ 1528 => x"d6c4058c",
+ 1529 => x"11085858",
+ 1530 => x"5475772e",
+ 1531 => x"81f03884",
+ 1532 => x"1608fc06",
+ 1533 => x"8c170888",
+ 1534 => x"1808718c",
+ 1535 => x"120c8812",
+ 1536 => x"0c5b7605",
+ 1537 => x"84110881",
+ 1538 => x"0784120c",
+ 1539 => x"537c518c",
+ 1540 => x"de3f8816",
+ 1541 => x"5473800c",
+ 1542 => x"8e3d0d04",
+ 1543 => x"77892a78",
+ 1544 => x"832a5854",
+ 1545 => x"73802ebf",
+ 1546 => x"3877862a",
+ 1547 => x"b8055784",
+ 1548 => x"7427b438",
+ 1549 => x"80db1457",
+ 1550 => x"947427ab",
+ 1551 => x"38778c2a",
+ 1552 => x"80ee0557",
+ 1553 => x"80d47427",
+ 1554 => x"9e38778f",
+ 1555 => x"2a80f705",
+ 1556 => x"5782d474",
+ 1557 => x"27913877",
+ 1558 => x"922a80fc",
+ 1559 => x"05578ad4",
+ 1560 => x"74278438",
+ 1561 => x"80fe5776",
+ 1562 => x"10101080",
+ 1563 => x"d6c4058c",
+ 1564 => x"11085653",
+ 1565 => x"74732ea3",
+ 1566 => x"38841508",
+ 1567 => x"fc067079",
+ 1568 => x"31555673",
+ 1569 => x"8f2488e4",
+ 1570 => x"38738025",
+ 1571 => x"88e6388c",
+ 1572 => x"15085574",
+ 1573 => x"732e0981",
+ 1574 => x"06df3881",
+ 1575 => x"175980d6",
+ 1576 => x"d4085675",
+ 1577 => x"80d6cc2e",
+ 1578 => x"82cc3884",
+ 1579 => x"1608fc06",
+ 1580 => x"70793155",
+ 1581 => x"55738f24",
+ 1582 => x"bb3880d6",
+ 1583 => x"cc0b80d6",
+ 1584 => x"d80c80d6",
+ 1585 => x"cc0b80d6",
+ 1586 => x"d40c8074",
+ 1587 => x"2480db38",
+ 1588 => x"74168411",
+ 1589 => x"08810784",
+ 1590 => x"120c53fe",
+ 1591 => x"b0398816",
+ 1592 => x"8c110857",
+ 1593 => x"5975792e",
+ 1594 => x"098106fe",
+ 1595 => x"82388214",
+ 1596 => x"59ffab39",
+ 1597 => x"77167881",
+ 1598 => x"0784180c",
+ 1599 => x"7080d6d8",
+ 1600 => x"0c7080d6",
+ 1601 => x"d40c80d6",
+ 1602 => x"cc0b8c12",
+ 1603 => x"0c8c1108",
+ 1604 => x"88120c74",
+ 1605 => x"81078412",
+ 1606 => x"0c740574",
+ 1607 => x"710c5b7c",
+ 1608 => x"518acc3f",
+ 1609 => x"881654fd",
+ 1610 => x"ec3983ff",
+ 1611 => x"75278391",
+ 1612 => x"3874892a",
+ 1613 => x"75832a54",
+ 1614 => x"5473802e",
+ 1615 => x"bf387486",
+ 1616 => x"2ab80553",
+ 1617 => x"847427b4",
+ 1618 => x"3880db14",
+ 1619 => x"53947427",
+ 1620 => x"ab38748c",
+ 1621 => x"2a80ee05",
+ 1622 => x"5380d474",
+ 1623 => x"279e3874",
+ 1624 => x"8f2a80f7",
+ 1625 => x"055382d4",
+ 1626 => x"74279138",
+ 1627 => x"74922a80",
+ 1628 => x"fc05538a",
+ 1629 => x"d4742784",
+ 1630 => x"3880fe53",
+ 1631 => x"72101010",
+ 1632 => x"80d6c405",
+ 1633 => x"88110855",
+ 1634 => x"5773772e",
+ 1635 => x"868b3884",
+ 1636 => x"1408fc06",
+ 1637 => x"5b747b27",
+ 1638 => x"8d388814",
+ 1639 => x"08547377",
+ 1640 => x"2e098106",
+ 1641 => x"ea388c14",
+ 1642 => x"0880d6c4",
+ 1643 => x"0b840508",
+ 1644 => x"718c190c",
+ 1645 => x"7588190c",
+ 1646 => x"7788130c",
+ 1647 => x"5c57758c",
+ 1648 => x"150c7853",
+ 1649 => x"80792483",
+ 1650 => x"98387282",
+ 1651 => x"2c81712b",
+ 1652 => x"5656747b",
+ 1653 => x"2680ca38",
+ 1654 => x"7a750657",
+ 1655 => x"7682a338",
+ 1656 => x"78fc0684",
+ 1657 => x"05597410",
+ 1658 => x"707c0655",
+ 1659 => x"55738292",
+ 1660 => x"38841959",
+ 1661 => x"f13980d6",
+ 1662 => x"c40b8405",
+ 1663 => x"0879545b",
+ 1664 => x"788025c6",
+ 1665 => x"3882da39",
+ 1666 => x"74097b06",
+ 1667 => x"7080d6c4",
+ 1668 => x"0b84050c",
+ 1669 => x"5b741055",
+ 1670 => x"747b2685",
+ 1671 => x"387485bc",
+ 1672 => x"3880d6c4",
+ 1673 => x"0b880508",
+ 1674 => x"70841208",
+ 1675 => x"fc06707b",
+ 1676 => x"317b7226",
+ 1677 => x"8f722507",
+ 1678 => x"5d575c5c",
+ 1679 => x"5578802e",
+ 1680 => x"80d93879",
+ 1681 => x"1580d6bc",
+ 1682 => x"08199011",
+ 1683 => x"59545680",
+ 1684 => x"d6b808ff",
+ 1685 => x"2e8838a0",
+ 1686 => x"8f13e080",
+ 1687 => x"06577652",
+ 1688 => x"7c51888c",
+ 1689 => x"3f800854",
+ 1690 => x"8008ff2e",
+ 1691 => x"90388008",
+ 1692 => x"762782a7",
+ 1693 => x"387480d6",
+ 1694 => x"c42e829f",
+ 1695 => x"3880d6c4",
+ 1696 => x"0b880508",
+ 1697 => x"55841508",
+ 1698 => x"fc067079",
+ 1699 => x"31797226",
+ 1700 => x"8f722507",
+ 1701 => x"5d555a7a",
+ 1702 => x"83f23877",
+ 1703 => x"81078416",
+ 1704 => x"0c771570",
+ 1705 => x"80d6c40b",
+ 1706 => x"88050c74",
+ 1707 => x"81078412",
+ 1708 => x"0c567c51",
+ 1709 => x"87b93f88",
+ 1710 => x"15547380",
+ 1711 => x"0c8e3d0d",
+ 1712 => x"0474832a",
+ 1713 => x"70545480",
+ 1714 => x"7424819b",
+ 1715 => x"3872822c",
+ 1716 => x"81712b80",
+ 1717 => x"d6c80807",
+ 1718 => x"7080d6c4",
+ 1719 => x"0b84050c",
+ 1720 => x"75101010",
+ 1721 => x"80d6c405",
+ 1722 => x"88110871",
+ 1723 => x"8c1b0c70",
+ 1724 => x"881b0c79",
+ 1725 => x"88130c57",
+ 1726 => x"555c5575",
+ 1727 => x"8c150cfd",
+ 1728 => x"c1397879",
+ 1729 => x"10101080",
+ 1730 => x"d6c40570",
+ 1731 => x"565b5c8c",
+ 1732 => x"14085675",
+ 1733 => x"742ea338",
+ 1734 => x"841608fc",
+ 1735 => x"06707931",
+ 1736 => x"5853768f",
+ 1737 => x"2483f138",
+ 1738 => x"76802584",
+ 1739 => x"af388c16",
+ 1740 => x"08567574",
+ 1741 => x"2e098106",
+ 1742 => x"df388814",
+ 1743 => x"811a7083",
+ 1744 => x"06555a54",
+ 1745 => x"72c9387b",
+ 1746 => x"83065675",
+ 1747 => x"802efdb8",
+ 1748 => x"38ff1cf8",
+ 1749 => x"1b5b5c88",
+ 1750 => x"1a087a2e",
+ 1751 => x"ea38fdb5",
+ 1752 => x"39831953",
+ 1753 => x"fce43983",
+ 1754 => x"1470822c",
+ 1755 => x"81712b80",
+ 1756 => x"d6c80807",
+ 1757 => x"7080d6c4",
+ 1758 => x"0b84050c",
+ 1759 => x"76101010",
+ 1760 => x"80d6c405",
+ 1761 => x"88110871",
+ 1762 => x"8c1c0c70",
+ 1763 => x"881c0c7a",
+ 1764 => x"88130c58",
+ 1765 => x"535d5653",
+ 1766 => x"fee13980",
+ 1767 => x"d6880817",
+ 1768 => x"59800876",
+ 1769 => x"2e818b38",
+ 1770 => x"80d6b808",
+ 1771 => x"ff2e848e",
+ 1772 => x"38737631",
+ 1773 => x"1980d688",
+ 1774 => x"0c738706",
+ 1775 => x"70565372",
+ 1776 => x"802e8838",
+ 1777 => x"88733170",
+ 1778 => x"15555576",
+ 1779 => x"149fff06",
+ 1780 => x"a0807131",
+ 1781 => x"1670547e",
+ 1782 => x"53515385",
+ 1783 => x"933f8008",
+ 1784 => x"568008ff",
+ 1785 => x"2e819e38",
+ 1786 => x"80d68808",
+ 1787 => x"137080d6",
+ 1788 => x"880c7475",
+ 1789 => x"80d6c40b",
+ 1790 => x"88050c77",
+ 1791 => x"76311581",
+ 1792 => x"07555659",
+ 1793 => x"7a80d6c4",
+ 1794 => x"2e83c038",
+ 1795 => x"798f2682",
+ 1796 => x"ef38810b",
+ 1797 => x"84150c84",
+ 1798 => x"1508fc06",
+ 1799 => x"70793179",
+ 1800 => x"72268f72",
+ 1801 => x"25075d55",
+ 1802 => x"5a7a802e",
+ 1803 => x"fced3880",
+ 1804 => x"db398008",
+ 1805 => x"9fff0655",
+ 1806 => x"74feed38",
+ 1807 => x"7880d688",
+ 1808 => x"0c80d6c4",
+ 1809 => x"0b880508",
+ 1810 => x"7a188107",
+ 1811 => x"84120c55",
+ 1812 => x"80d6b408",
+ 1813 => x"79278638",
+ 1814 => x"7880d6b4",
+ 1815 => x"0c80d6b0",
+ 1816 => x"087927fc",
+ 1817 => x"a0387880",
+ 1818 => x"d6b00c84",
+ 1819 => x"1508fc06",
+ 1820 => x"70793179",
+ 1821 => x"72268f72",
+ 1822 => x"25075d55",
+ 1823 => x"5a7a802e",
+ 1824 => x"fc993888",
+ 1825 => x"39807457",
+ 1826 => x"53fedd39",
+ 1827 => x"7c5183df",
+ 1828 => x"3f800b80",
+ 1829 => x"0c8e3d0d",
+ 1830 => x"04807324",
+ 1831 => x"a5387282",
+ 1832 => x"2c81712b",
+ 1833 => x"80d6c808",
+ 1834 => x"077080d6",
+ 1835 => x"c40b8405",
+ 1836 => x"0c5c5a76",
+ 1837 => x"8c170c73",
+ 1838 => x"88170c75",
+ 1839 => x"88180cf9",
+ 1840 => x"fd398313",
+ 1841 => x"70822c81",
+ 1842 => x"712b80d6",
+ 1843 => x"c8080770",
+ 1844 => x"80d6c40b",
+ 1845 => x"84050c5d",
+ 1846 => x"5b53d839",
+ 1847 => x"7a75065c",
+ 1848 => x"7bfc9f38",
+ 1849 => x"84197510",
+ 1850 => x"5659f139",
+ 1851 => x"ff178105",
+ 1852 => x"59f7ab39",
+ 1853 => x"8c150888",
+ 1854 => x"1608718c",
+ 1855 => x"120c8812",
+ 1856 => x"0c597515",
+ 1857 => x"84110881",
+ 1858 => x"0784120c",
+ 1859 => x"587c5182",
+ 1860 => x"de3f8815",
+ 1861 => x"54fba339",
+ 1862 => x"77167881",
+ 1863 => x"0784180c",
+ 1864 => x"8c170888",
+ 1865 => x"1808718c",
+ 1866 => x"120c8812",
+ 1867 => x"0c5c7080",
+ 1868 => x"d6d80c70",
+ 1869 => x"80d6d40c",
+ 1870 => x"80d6cc0b",
+ 1871 => x"8c120c8c",
+ 1872 => x"11088812",
+ 1873 => x"0c778107",
+ 1874 => x"84120c77",
+ 1875 => x"0577710c",
+ 1876 => x"557c5182",
+ 1877 => x"9a3f8816",
+ 1878 => x"54f5ba39",
+ 1879 => x"72168411",
+ 1880 => x"08810784",
+ 1881 => x"120c588c",
+ 1882 => x"16088817",
+ 1883 => x"08718c12",
+ 1884 => x"0c88120c",
+ 1885 => x"577c5181",
+ 1886 => x"f63f8816",
+ 1887 => x"54f59639",
+ 1888 => x"7284150c",
+ 1889 => x"f41af806",
+ 1890 => x"70841d08",
+ 1891 => x"81060784",
+ 1892 => x"1d0c701c",
+ 1893 => x"5556850b",
+ 1894 => x"84150c85",
+ 1895 => x"0b88150c",
+ 1896 => x"8f7627fd",
+ 1897 => x"ab38881b",
+ 1898 => x"527c5184",
+ 1899 => x"c13f80d6",
+ 1900 => x"c40b8805",
+ 1901 => x"0880d688",
+ 1902 => x"085a55fd",
+ 1903 => x"93397880",
+ 1904 => x"d6880c73",
+ 1905 => x"80d6b80c",
+ 1906 => x"fbef3972",
+ 1907 => x"84150cfc",
+ 1908 => x"ff39fb3d",
+ 1909 => x"0d77707a",
+ 1910 => x"7c585553",
+ 1911 => x"568f7527",
+ 1912 => x"80e63872",
+ 1913 => x"76078306",
+ 1914 => x"517080dc",
+ 1915 => x"38757352",
+ 1916 => x"54707084",
+ 1917 => x"05520874",
+ 1918 => x"70840556",
+ 1919 => x"0c737170",
+ 1920 => x"84055308",
+ 1921 => x"71708405",
+ 1922 => x"530c7170",
+ 1923 => x"84055308",
+ 1924 => x"71708405",
+ 1925 => x"530c7170",
+ 1926 => x"84055308",
+ 1927 => x"71708405",
+ 1928 => x"530cf016",
+ 1929 => x"5654748f",
+ 1930 => x"26c73883",
+ 1931 => x"75279538",
+ 1932 => x"70708405",
+ 1933 => x"52087470",
+ 1934 => x"8405560c",
+ 1935 => x"fc155574",
+ 1936 => x"8326ed38",
+ 1937 => x"73715452",
+ 1938 => x"ff155170",
+ 1939 => x"ff2e9838",
+ 1940 => x"72708105",
+ 1941 => x"54337270",
+ 1942 => x"81055434",
+ 1943 => x"ff115170",
+ 1944 => x"ff2e0981",
+ 1945 => x"06ea3875",
+ 1946 => x"800c873d",
+ 1947 => x"0d040404",
+ 1948 => x"70707070",
+ 1949 => x"800b81b6",
+ 1950 => x"9c0c7651",
+ 1951 => x"87cc3f80",
+ 1952 => x"08538008",
+ 1953 => x"ff2e8938",
+ 1954 => x"72800c50",
+ 1955 => x"50505004",
+ 1956 => x"81b69c08",
+ 1957 => x"5473802e",
+ 1958 => x"ef387574",
+ 1959 => x"710c5272",
+ 1960 => x"800c5050",
+ 1961 => x"505004fb",
+ 1962 => x"3d0d7779",
+ 1963 => x"70720783",
+ 1964 => x"06535452",
+ 1965 => x"70933871",
+ 1966 => x"73730854",
+ 1967 => x"56547173",
+ 1968 => x"082e80c4",
+ 1969 => x"38737554",
+ 1970 => x"52713370",
+ 1971 => x"81ff0652",
+ 1972 => x"5470802e",
+ 1973 => x"9d387233",
+ 1974 => x"5570752e",
+ 1975 => x"09810695",
+ 1976 => x"38811281",
+ 1977 => x"14713370",
+ 1978 => x"81ff0654",
+ 1979 => x"56545270",
+ 1980 => x"e5387233",
+ 1981 => x"557381ff",
+ 1982 => x"067581ff",
+ 1983 => x"06717131",
+ 1984 => x"800c5552",
+ 1985 => x"873d0d04",
+ 1986 => x"7109f7fb",
+ 1987 => x"fdff1306",
+ 1988 => x"f8848281",
+ 1989 => x"80065271",
+ 1990 => x"97388414",
+ 1991 => x"84167108",
+ 1992 => x"54565471",
+ 1993 => x"75082ee0",
+ 1994 => x"38737554",
+ 1995 => x"52ff9a39",
+ 1996 => x"800b800c",
+ 1997 => x"873d0d04",
+ 1998 => x"fb3d0d77",
+ 1999 => x"705256fe",
+ 2000 => x"ad3f80d6",
+ 2001 => x"c40b8805",
+ 2002 => x"08841108",
+ 2003 => x"fc06707b",
+ 2004 => x"319fef05",
+ 2005 => x"e08006e0",
+ 2006 => x"80055255",
+ 2007 => x"55a08075",
+ 2008 => x"24943880",
+ 2009 => x"527551fe",
+ 2010 => x"873f80d6",
+ 2011 => x"cc081453",
+ 2012 => x"7280082e",
+ 2013 => x"8f387551",
+ 2014 => x"fdf53f80",
+ 2015 => x"5372800c",
+ 2016 => x"873d0d04",
+ 2017 => x"74305275",
+ 2018 => x"51fde53f",
+ 2019 => x"8008ff2e",
+ 2020 => x"a83880d6",
+ 2021 => x"c40b8805",
+ 2022 => x"08747631",
+ 2023 => x"81078412",
+ 2024 => x"0c5380d6",
+ 2025 => x"88087531",
+ 2026 => x"80d6880c",
+ 2027 => x"7551fdbf",
+ 2028 => x"3f810b80",
+ 2029 => x"0c873d0d",
+ 2030 => x"04805275",
+ 2031 => x"51fdb13f",
+ 2032 => x"80d6c40b",
+ 2033 => x"88050880",
+ 2034 => x"08713154",
+ 2035 => x"548f7325",
+ 2036 => x"ffa43880",
+ 2037 => x"0880d6b8",
+ 2038 => x"083180d6",
+ 2039 => x"880c7281",
+ 2040 => x"0784150c",
+ 2041 => x"7551fd87",
+ 2042 => x"3f8053ff",
+ 2043 => x"9039f73d",
+ 2044 => x"0d7b7d54",
+ 2045 => x"5a72802e",
+ 2046 => x"82833879",
+ 2047 => x"51fcef3f",
+ 2048 => x"f8138411",
+ 2049 => x"0870fe06",
+ 2050 => x"70138411",
+ 2051 => x"08fc065c",
+ 2052 => x"57585457",
+ 2053 => x"80d6cc08",
+ 2054 => x"742e82de",
+ 2055 => x"38778415",
+ 2056 => x"0c807381",
+ 2057 => x"06565974",
+ 2058 => x"792e81d5",
+ 2059 => x"38771484",
+ 2060 => x"11088106",
+ 2061 => x"565374a0",
+ 2062 => x"38771656",
+ 2063 => x"7881e638",
+ 2064 => x"88140855",
+ 2065 => x"7480d6cc",
+ 2066 => x"2e82f938",
+ 2067 => x"8c140870",
+ 2068 => x"8c170c75",
+ 2069 => x"88120c58",
+ 2070 => x"75810784",
+ 2071 => x"180c7517",
+ 2072 => x"76710c54",
+ 2073 => x"78819138",
+ 2074 => x"83ff7627",
+ 2075 => x"81c83875",
+ 2076 => x"892a7683",
+ 2077 => x"2a545473",
+ 2078 => x"802ebf38",
+ 2079 => x"75862ab8",
+ 2080 => x"05538474",
+ 2081 => x"27b43880",
+ 2082 => x"db145394",
+ 2083 => x"7427ab38",
+ 2084 => x"758c2a80",
+ 2085 => x"ee055380",
+ 2086 => x"d474279e",
+ 2087 => x"38758f2a",
+ 2088 => x"80f70553",
+ 2089 => x"82d47427",
+ 2090 => x"91387592",
+ 2091 => x"2a80fc05",
+ 2092 => x"538ad474",
+ 2093 => x"27843880",
+ 2094 => x"fe537210",
+ 2095 => x"101080d6",
+ 2096 => x"c4058811",
+ 2097 => x"08555573",
+ 2098 => x"752e82bf",
+ 2099 => x"38841408",
+ 2100 => x"fc065975",
+ 2101 => x"79278d38",
+ 2102 => x"88140854",
+ 2103 => x"73752e09",
+ 2104 => x"8106ea38",
+ 2105 => x"8c140870",
+ 2106 => x"8c190c74",
+ 2107 => x"88190c77",
+ 2108 => x"88120c55",
+ 2109 => x"768c150c",
+ 2110 => x"7951faf3",
+ 2111 => x"3f8b3d0d",
+ 2112 => x"04760877",
+ 2113 => x"71315876",
+ 2114 => x"05881808",
+ 2115 => x"56567480",
+ 2116 => x"d6cc2e80",
+ 2117 => x"e0388c17",
+ 2118 => x"08708c17",
+ 2119 => x"0c758812",
+ 2120 => x"0c53fe89",
+ 2121 => x"39881408",
+ 2122 => x"8c150870",
+ 2123 => x"8c130c59",
+ 2124 => x"88190cfe",
+ 2125 => x"a3397583",
+ 2126 => x"2a705454",
+ 2127 => x"80742481",
+ 2128 => x"98387282",
+ 2129 => x"2c81712b",
+ 2130 => x"80d6c808",
+ 2131 => x"0780d6c4",
+ 2132 => x"0b84050c",
+ 2133 => x"74101010",
+ 2134 => x"80d6c405",
+ 2135 => x"88110871",
+ 2136 => x"8c1b0c70",
+ 2137 => x"881b0c79",
+ 2138 => x"88130c56",
+ 2139 => x"5a55768c",
+ 2140 => x"150cff84",
+ 2141 => x"398159fd",
+ 2142 => x"b4397716",
+ 2143 => x"73810654",
+ 2144 => x"55729838",
+ 2145 => x"76087771",
+ 2146 => x"31587505",
+ 2147 => x"8c180888",
+ 2148 => x"1908718c",
+ 2149 => x"120c8812",
+ 2150 => x"0c555574",
+ 2151 => x"81078418",
+ 2152 => x"0c7680d6",
+ 2153 => x"c40b8805",
+ 2154 => x"0c80d6c0",
+ 2155 => x"087526fe",
+ 2156 => x"c73880d6",
+ 2157 => x"bc085279",
+ 2158 => x"51fafd3f",
+ 2159 => x"7951f9af",
+ 2160 => x"3ffeba39",
+ 2161 => x"81778c17",
+ 2162 => x"0c778817",
+ 2163 => x"0c758c19",
+ 2164 => x"0c758819",
+ 2165 => x"0c59fd80",
+ 2166 => x"39831470",
+ 2167 => x"822c8171",
+ 2168 => x"2b80d6c8",
+ 2169 => x"080780d6",
+ 2170 => x"c40b8405",
+ 2171 => x"0c751010",
+ 2172 => x"1080d6c4",
+ 2173 => x"05881108",
+ 2174 => x"718c1c0c",
+ 2175 => x"70881c0c",
+ 2176 => x"7a88130c",
+ 2177 => x"575b5653",
+ 2178 => x"fee43980",
+ 2179 => x"7324a338",
+ 2180 => x"72822c81",
+ 2181 => x"712b80d6",
+ 2182 => x"c8080780",
+ 2183 => x"d6c40b84",
+ 2184 => x"050c5874",
+ 2185 => x"8c180c73",
+ 2186 => x"88180c76",
+ 2187 => x"88160cfd",
+ 2188 => x"c3398313",
+ 2189 => x"70822c81",
+ 2190 => x"712b80d6",
+ 2191 => x"c8080780",
+ 2192 => x"d6c40b84",
+ 2193 => x"050c5953",
+ 2194 => x"da397070",
+ 2195 => x"7080e5f4",
+ 2196 => x"08893881",
+ 2197 => x"b6a00b80",
+ 2198 => x"e5f40c80",
+ 2199 => x"e5f40875",
+ 2200 => x"115252ff",
+ 2201 => x"537087fb",
+ 2202 => x"80802688",
+ 2203 => x"387080e5",
+ 2204 => x"f40c7153",
+ 2205 => x"72800c50",
+ 2206 => x"505004fd",
+ 2207 => x"3d0d800b",
+ 2208 => x"80d5f408",
+ 2209 => x"54547281",
+ 2210 => x"2e9b3873",
+ 2211 => x"80e5f80c",
+ 2212 => x"c3ee3fc2",
+ 2213 => x"eb3f80e5",
+ 2214 => x"cc528151",
+ 2215 => x"cc933f80",
+ 2216 => x"085180dd",
+ 2217 => x"3f7280e5",
+ 2218 => x"f80cc3d4",
+ 2219 => x"3fc2d13f",
+ 2220 => x"80e5cc52",
+ 2221 => x"8151cbf9",
+ 2222 => x"3f800851",
+ 2223 => x"80c33f00",
+ 2224 => x"ff3900ff",
+ 2225 => x"39f43d0d",
+ 2226 => x"7e80e5ec",
+ 2227 => x"08700870",
+ 2228 => x"81ff0692",
+ 2229 => x"3df80555",
+ 2230 => x"515a5759",
+ 2231 => x"c48f3f80",
+ 2232 => x"5477557b",
+ 2233 => x"7d585276",
+ 2234 => x"538e3df0",
+ 2235 => x"0551de8e",
+ 2236 => x"3f797b58",
+ 2237 => x"790c7684",
+ 2238 => x"1a0c7880",
+ 2239 => x"0c8e3d0d",
+ 2240 => x"04f73d0d",
+ 2241 => x"7b80decc",
+ 2242 => x"0882c811",
+ 2243 => x"085a545a",
+ 2244 => x"77802e80",
+ 2245 => x"da388188",
+ 2246 => x"18841908",
+ 2247 => x"ff058171",
+ 2248 => x"2b595559",
+ 2249 => x"80742480",
+ 2250 => x"ea388074",
+ 2251 => x"24b53873",
+ 2252 => x"822b7811",
+ 2253 => x"88055656",
+ 2254 => x"81801908",
+ 2255 => x"77065372",
+ 2256 => x"802eb638",
+ 2257 => x"78167008",
+ 2258 => x"53537951",
+ 2259 => x"74085372",
+ 2260 => x"2dff14fc",
+ 2261 => x"17fc1779",
+ 2262 => x"812c5a57",
+ 2263 => x"57547380",
+ 2264 => x"25d63877",
+ 2265 => x"085877ff",
+ 2266 => x"ad3880de",
+ 2267 => x"cc0853bc",
+ 2268 => x"1308a538",
+ 2269 => x"7951fec7",
+ 2270 => x"3f740853",
+ 2271 => x"722dff14",
+ 2272 => x"fc17fc17",
+ 2273 => x"79812c5a",
+ 2274 => x"57575473",
+ 2275 => x"8025ffa8",
+ 2276 => x"38d13980",
+ 2277 => x"57ff9339",
+ 2278 => x"7251bc13",
+ 2279 => x"0854732d",
+ 2280 => x"7951fe9b",
+ 2281 => x"3f707080",
+ 2282 => x"e5d40bfc",
+ 2283 => x"05700852",
+ 2284 => x"5270ff2e",
+ 2285 => x"9138702d",
+ 2286 => x"fc127008",
+ 2287 => x"525270ff",
+ 2288 => x"2e098106",
+ 2289 => x"f1385050",
+ 2290 => x"0404c2ff",
+ 2291 => x"3f040000",
+ 2292 => x"00000040",
+ 2293 => x"30313233",
+ 2294 => x"34353637",
+ 2295 => x"38390000",
+ 2296 => x"44485259",
+ 2297 => x"53544f4e",
+ 2298 => x"45205052",
+ 2299 => x"4f475241",
+ 2300 => x"4d2c2053",
+ 2301 => x"4f4d4520",
+ 2302 => x"53545249",
+ 2303 => x"4e470000",
+ 2304 => x"44485259",
+ 2305 => x"53544f4e",
+ 2306 => x"45205052",
+ 2307 => x"4f475241",
+ 2308 => x"4d2c2031",
+ 2309 => x"27535420",
+ 2310 => x"53545249",
+ 2311 => x"4e470000",
+ 2312 => x"44687279",
+ 2313 => x"73746f6e",
+ 2314 => x"65204265",
+ 2315 => x"6e63686d",
+ 2316 => x"61726b2c",
+ 2317 => x"20566572",
+ 2318 => x"73696f6e",
+ 2319 => x"20322e31",
+ 2320 => x"20284c61",
+ 2321 => x"6e677561",
+ 2322 => x"67653a20",
+ 2323 => x"43290a00",
+ 2324 => x"50726f67",
+ 2325 => x"72616d20",
+ 2326 => x"636f6d70",
+ 2327 => x"696c6564",
+ 2328 => x"20776974",
+ 2329 => x"68202772",
+ 2330 => x"65676973",
+ 2331 => x"74657227",
+ 2332 => x"20617474",
+ 2333 => x"72696275",
+ 2334 => x"74650a00",
+ 2335 => x"45786563",
+ 2336 => x"7574696f",
+ 2337 => x"6e207374",
+ 2338 => x"61727473",
+ 2339 => x"2c202564",
+ 2340 => x"2072756e",
+ 2341 => x"73207468",
+ 2342 => x"726f7567",
+ 2343 => x"68204468",
+ 2344 => x"72797374",
+ 2345 => x"6f6e650a",
+ 2346 => x"00000000",
+ 2347 => x"44485259",
+ 2348 => x"53544f4e",
+ 2349 => x"45205052",
+ 2350 => x"4f475241",
+ 2351 => x"4d2c2032",
+ 2352 => x"274e4420",
+ 2353 => x"53545249",
+ 2354 => x"4e470000",
+ 2355 => x"45786563",
+ 2356 => x"7574696f",
+ 2357 => x"6e20656e",
+ 2358 => x"64730a00",
+ 2359 => x"46696e61",
+ 2360 => x"6c207661",
+ 2361 => x"6c756573",
+ 2362 => x"206f6620",
+ 2363 => x"74686520",
+ 2364 => x"76617269",
+ 2365 => x"61626c65",
+ 2366 => x"73207573",
+ 2367 => x"65642069",
+ 2368 => x"6e207468",
+ 2369 => x"65206265",
+ 2370 => x"6e63686d",
+ 2371 => x"61726b3a",
+ 2372 => x"0a000000",
+ 2373 => x"496e745f",
+ 2374 => x"476c6f62",
+ 2375 => x"3a202020",
+ 2376 => x"20202020",
+ 2377 => x"20202020",
+ 2378 => x"2025640a",
+ 2379 => x"00000000",
+ 2380 => x"20202020",
+ 2381 => x"20202020",
+ 2382 => x"73686f75",
+ 2383 => x"6c642062",
+ 2384 => x"653a2020",
+ 2385 => x"2025640a",
+ 2386 => x"00000000",
+ 2387 => x"426f6f6c",
+ 2388 => x"5f476c6f",
+ 2389 => x"623a2020",
+ 2390 => x"20202020",
+ 2391 => x"20202020",
+ 2392 => x"2025640a",
+ 2393 => x"00000000",
+ 2394 => x"43685f31",
+ 2395 => x"5f476c6f",
+ 2396 => x"623a2020",
+ 2397 => x"20202020",
+ 2398 => x"20202020",
+ 2399 => x"2025630a",
+ 2400 => x"00000000",
+ 2401 => x"20202020",
+ 2402 => x"20202020",
+ 2403 => x"73686f75",
+ 2404 => x"6c642062",
+ 2405 => x"653a2020",
+ 2406 => x"2025630a",
+ 2407 => x"00000000",
+ 2408 => x"43685f32",
+ 2409 => x"5f476c6f",
+ 2410 => x"623a2020",
+ 2411 => x"20202020",
+ 2412 => x"20202020",
+ 2413 => x"2025630a",
+ 2414 => x"00000000",
+ 2415 => x"4172725f",
+ 2416 => x"315f476c",
+ 2417 => x"6f625b38",
+ 2418 => x"5d3a2020",
+ 2419 => x"20202020",
+ 2420 => x"2025640a",
+ 2421 => x"00000000",
+ 2422 => x"4172725f",
+ 2423 => x"325f476c",
+ 2424 => x"6f625b38",
+ 2425 => x"5d5b375d",
+ 2426 => x"3a202020",
+ 2427 => x"2025640a",
+ 2428 => x"00000000",
+ 2429 => x"20202020",
+ 2430 => x"20202020",
+ 2431 => x"73686f75",
+ 2432 => x"6c642062",
+ 2433 => x"653a2020",
+ 2434 => x"204e756d",
+ 2435 => x"6265725f",
+ 2436 => x"4f665f52",
+ 2437 => x"756e7320",
+ 2438 => x"2b203130",
+ 2439 => x"0a000000",
+ 2440 => x"5074725f",
+ 2441 => x"476c6f62",
+ 2442 => x"2d3e0a00",
+ 2443 => x"20205074",
+ 2444 => x"725f436f",
+ 2445 => x"6d703a20",
+ 2446 => x"20202020",
+ 2447 => x"20202020",
+ 2448 => x"2025640a",
+ 2449 => x"00000000",
+ 2450 => x"20202020",
+ 2451 => x"20202020",
+ 2452 => x"73686f75",
+ 2453 => x"6c642062",
+ 2454 => x"653a2020",
+ 2455 => x"2028696d",
+ 2456 => x"706c656d",
+ 2457 => x"656e7461",
+ 2458 => x"74696f6e",
+ 2459 => x"2d646570",
+ 2460 => x"656e6465",
+ 2461 => x"6e74290a",
+ 2462 => x"00000000",
+ 2463 => x"20204469",
+ 2464 => x"7363723a",
+ 2465 => x"20202020",
+ 2466 => x"20202020",
+ 2467 => x"20202020",
+ 2468 => x"2025640a",
+ 2469 => x"00000000",
+ 2470 => x"2020456e",
+ 2471 => x"756d5f43",
+ 2472 => x"6f6d703a",
+ 2473 => x"20202020",
+ 2474 => x"20202020",
+ 2475 => x"2025640a",
+ 2476 => x"00000000",
+ 2477 => x"2020496e",
+ 2478 => x"745f436f",
+ 2479 => x"6d703a20",
+ 2480 => x"20202020",
+ 2481 => x"20202020",
+ 2482 => x"2025640a",
+ 2483 => x"00000000",
+ 2484 => x"20205374",
+ 2485 => x"725f436f",
+ 2486 => x"6d703a20",
+ 2487 => x"20202020",
+ 2488 => x"20202020",
+ 2489 => x"2025730a",
+ 2490 => x"00000000",
+ 2491 => x"20202020",
+ 2492 => x"20202020",
+ 2493 => x"73686f75",
+ 2494 => x"6c642062",
+ 2495 => x"653a2020",
+ 2496 => x"20444852",
+ 2497 => x"5953544f",
+ 2498 => x"4e452050",
+ 2499 => x"524f4752",
+ 2500 => x"414d2c20",
+ 2501 => x"534f4d45",
+ 2502 => x"20535452",
+ 2503 => x"494e470a",
+ 2504 => x"00000000",
+ 2505 => x"4e657874",
+ 2506 => x"5f507472",
+ 2507 => x"5f476c6f",
+ 2508 => x"622d3e0a",
+ 2509 => x"00000000",
+ 2510 => x"20202020",
+ 2511 => x"20202020",
+ 2512 => x"73686f75",
+ 2513 => x"6c642062",
+ 2514 => x"653a2020",
+ 2515 => x"2028696d",
+ 2516 => x"706c656d",
+ 2517 => x"656e7461",
+ 2518 => x"74696f6e",
+ 2519 => x"2d646570",
+ 2520 => x"656e6465",
+ 2521 => x"6e74292c",
+ 2522 => x"2073616d",
+ 2523 => x"65206173",
+ 2524 => x"2061626f",
+ 2525 => x"76650a00",
+ 2526 => x"496e745f",
+ 2527 => x"315f4c6f",
+ 2528 => x"633a2020",
+ 2529 => x"20202020",
+ 2530 => x"20202020",
+ 2531 => x"2025640a",
+ 2532 => x"00000000",
+ 2533 => x"496e745f",
+ 2534 => x"325f4c6f",
+ 2535 => x"633a2020",
+ 2536 => x"20202020",
+ 2537 => x"20202020",
+ 2538 => x"2025640a",
+ 2539 => x"00000000",
+ 2540 => x"496e745f",
+ 2541 => x"335f4c6f",
+ 2542 => x"633a2020",
+ 2543 => x"20202020",
+ 2544 => x"20202020",
+ 2545 => x"2025640a",
+ 2546 => x"00000000",
+ 2547 => x"456e756d",
+ 2548 => x"5f4c6f63",
+ 2549 => x"3a202020",
+ 2550 => x"20202020",
+ 2551 => x"20202020",
+ 2552 => x"2025640a",
+ 2553 => x"00000000",
+ 2554 => x"5374725f",
+ 2555 => x"315f4c6f",
+ 2556 => x"633a2020",
+ 2557 => x"20202020",
+ 2558 => x"20202020",
+ 2559 => x"2025730a",
+ 2560 => x"00000000",
+ 2561 => x"20202020",
+ 2562 => x"20202020",
+ 2563 => x"73686f75",
+ 2564 => x"6c642062",
+ 2565 => x"653a2020",
+ 2566 => x"20444852",
+ 2567 => x"5953544f",
+ 2568 => x"4e452050",
+ 2569 => x"524f4752",
+ 2570 => x"414d2c20",
+ 2571 => x"31275354",
+ 2572 => x"20535452",
+ 2573 => x"494e470a",
+ 2574 => x"00000000",
+ 2575 => x"5374725f",
+ 2576 => x"325f4c6f",
+ 2577 => x"633a2020",
+ 2578 => x"20202020",
+ 2579 => x"20202020",
+ 2580 => x"2025730a",
+ 2581 => x"00000000",
+ 2582 => x"20202020",
+ 2583 => x"20202020",
+ 2584 => x"73686f75",
+ 2585 => x"6c642062",
+ 2586 => x"653a2020",
+ 2587 => x"20444852",
+ 2588 => x"5953544f",
+ 2589 => x"4e452050",
+ 2590 => x"524f4752",
+ 2591 => x"414d2c20",
+ 2592 => x"32274e44",
+ 2593 => x"20535452",
+ 2594 => x"494e470a",
+ 2595 => x"00000000",
+ 2596 => x"55736572",
+ 2597 => x"2074696d",
+ 2598 => x"653a2025",
+ 2599 => x"640a0000",
+ 2600 => x"4d696372",
+ 2601 => x"6f736563",
+ 2602 => x"6f6e6473",
+ 2603 => x"20666f72",
+ 2604 => x"206f6e65",
+ 2605 => x"2072756e",
+ 2606 => x"20746872",
+ 2607 => x"6f756768",
+ 2608 => x"20446872",
+ 2609 => x"7973746f",
+ 2610 => x"6e653a20",
+ 2611 => x"00000000",
+ 2612 => x"2564200a",
+ 2613 => x"00000000",
+ 2614 => x"44687279",
+ 2615 => x"73746f6e",
+ 2616 => x"65732070",
+ 2617 => x"65722053",
+ 2618 => x"65636f6e",
+ 2619 => x"643a2020",
+ 2620 => x"20202020",
+ 2621 => x"20202020",
+ 2622 => x"20202020",
+ 2623 => x"20202020",
+ 2624 => x"20202020",
+ 2625 => x"00000000",
+ 2626 => x"56415820",
+ 2627 => x"4d495053",
+ 2628 => x"20726174",
+ 2629 => x"696e6720",
+ 2630 => x"2a203130",
+ 2631 => x"3030203d",
+ 2632 => x"20256420",
+ 2633 => x"0a000000",
+ 2634 => x"50726f67",
+ 2635 => x"72616d20",
+ 2636 => x"636f6d70",
+ 2637 => x"696c6564",
+ 2638 => x"20776974",
+ 2639 => x"686f7574",
+ 2640 => x"20277265",
+ 2641 => x"67697374",
+ 2642 => x"65722720",
+ 2643 => x"61747472",
+ 2644 => x"69627574",
+ 2645 => x"650a0000",
+ 2646 => x"4d656173",
+ 2647 => x"75726564",
+ 2648 => x"2074696d",
+ 2649 => x"6520746f",
+ 2650 => x"6f20736d",
+ 2651 => x"616c6c20",
+ 2652 => x"746f206f",
+ 2653 => x"62746169",
+ 2654 => x"6e206d65",
+ 2655 => x"616e696e",
+ 2656 => x"6766756c",
+ 2657 => x"20726573",
+ 2658 => x"756c7473",
+ 2659 => x"0a000000",
+ 2660 => x"506c6561",
+ 2661 => x"73652069",
+ 2662 => x"6e637265",
+ 2663 => x"61736520",
+ 2664 => x"6e756d62",
+ 2665 => x"6572206f",
+ 2666 => x"66207275",
+ 2667 => x"6e730a00",
+ 2668 => x"44485259",
+ 2669 => x"53544f4e",
+ 2670 => x"45205052",
+ 2671 => x"4f475241",
+ 2672 => x"4d2c2033",
+ 2673 => x"27524420",
+ 2674 => x"53545249",
+ 2675 => x"4e470000",
+ 2676 => x"00010202",
+ 2677 => x"03030303",
+ 2678 => x"04040404",
+ 2679 => x"04040404",
+ 2680 => x"05050505",
+ 2681 => x"05050505",
+ 2682 => x"05050505",
+ 2683 => x"05050505",
+ 2684 => x"06060606",
+ 2685 => x"06060606",
+ 2686 => x"06060606",
+ 2687 => x"06060606",
+ 2688 => x"06060606",
+ 2689 => x"06060606",
+ 2690 => x"06060606",
+ 2691 => x"06060606",
+ 2692 => x"07070707",
+ 2693 => x"07070707",
+ 2694 => x"07070707",
+ 2695 => x"07070707",
+ 2696 => x"07070707",
+ 2697 => x"07070707",
+ 2698 => x"07070707",
+ 2699 => x"07070707",
+ 2700 => x"07070707",
+ 2701 => x"07070707",
+ 2702 => x"07070707",
+ 2703 => x"07070707",
+ 2704 => x"07070707",
+ 2705 => x"07070707",
+ 2706 => x"07070707",
+ 2707 => x"07070707",
+ 2708 => x"08080808",
+ 2709 => x"08080808",
+ 2710 => x"08080808",
+ 2711 => x"08080808",
+ 2712 => x"08080808",
+ 2713 => x"08080808",
+ 2714 => x"08080808",
+ 2715 => x"08080808",
+ 2716 => x"08080808",
+ 2717 => x"08080808",
+ 2718 => x"08080808",
+ 2719 => x"08080808",
+ 2720 => x"08080808",
+ 2721 => x"08080808",
+ 2722 => x"08080808",
+ 2723 => x"08080808",
+ 2724 => x"08080808",
+ 2725 => x"08080808",
+ 2726 => x"08080808",
+ 2727 => x"08080808",
+ 2728 => x"08080808",
+ 2729 => x"08080808",
+ 2730 => x"08080808",
+ 2731 => x"08080808",
+ 2732 => x"08080808",
+ 2733 => x"08080808",
+ 2734 => x"08080808",
+ 2735 => x"08080808",
+ 2736 => x"08080808",
+ 2737 => x"08080808",
+ 2738 => x"08080808",
+ 2739 => x"08080808",
+ 2740 => x"43000000",
+ 2741 => x"64756d6d",
+ 2742 => x"792e6578",
+ 2743 => x"65000000",
+ 2744 => x"00ffffff",
+ 2745 => x"ff00ffff",
+ 2746 => x"ffff00ff",
+ 2747 => x"ffffff00",
+ 2748 => x"00000000",
+ 2749 => x"00000000",
+ 2750 => x"00000000",
+ 2751 => x"000032dc",
+ 2752 => x"0000c350",
+ 2753 => x"00000000",
+ 2754 => x"00000000",
+ 2755 => x"00000000",
+ 2756 => x"00000000",
+ 2757 => x"00000000",
+ 2758 => x"00000000",
+ 2759 => x"00000000",
+ 2760 => x"00000000",
+ 2761 => x"00000000",
+ 2762 => x"00000000",
+ 2763 => x"00000000",
+ 2764 => x"00000000",
+ 2765 => x"00000000",
+ 2766 => x"ffffffff",
+ 2767 => x"00000000",
+ 2768 => x"00020000",
+ 2769 => x"00000000",
+ 2770 => x"00000000",
+ 2771 => x"00002b44",
+ 2772 => x"00002b44",
+ 2773 => x"00002b4c",
+ 2774 => x"00002b4c",
+ 2775 => x"00002b54",
+ 2776 => x"00002b54",
+ 2777 => x"00002b5c",
+ 2778 => x"00002b5c",
+ 2779 => x"00002b64",
+ 2780 => x"00002b64",
+ 2781 => x"00002b6c",
+ 2782 => x"00002b6c",
+ 2783 => x"00002b74",
+ 2784 => x"00002b74",
+ 2785 => x"00002b7c",
+ 2786 => x"00002b7c",
+ 2787 => x"00002b84",
+ 2788 => x"00002b84",
+ 2789 => x"00002b8c",
+ 2790 => x"00002b8c",
+ 2791 => x"00002b94",
+ 2792 => x"00002b94",
+ 2793 => x"00002b9c",
+ 2794 => x"00002b9c",
+ 2795 => x"00002ba4",
+ 2796 => x"00002ba4",
+ 2797 => x"00002bac",
+ 2798 => x"00002bac",
+ 2799 => x"00002bb4",
+ 2800 => x"00002bb4",
+ 2801 => x"00002bbc",
+ 2802 => x"00002bbc",
+ 2803 => x"00002bc4",
+ 2804 => x"00002bc4",
+ 2805 => x"00002bcc",
+ 2806 => x"00002bcc",
+ 2807 => x"00002bd4",
+ 2808 => x"00002bd4",
+ 2809 => x"00002bdc",
+ 2810 => x"00002bdc",
+ 2811 => x"00002be4",
+ 2812 => x"00002be4",
+ 2813 => x"00002bec",
+ 2814 => x"00002bec",
+ 2815 => x"00002bf4",
+ 2816 => x"00002bf4",
+ 2817 => x"00002bfc",
+ 2818 => x"00002bfc",
+ 2819 => x"00002c04",
+ 2820 => x"00002c04",
+ 2821 => x"00002c0c",
+ 2822 => x"00002c0c",
+ 2823 => x"00002c14",
+ 2824 => x"00002c14",
+ 2825 => x"00002c1c",
+ 2826 => x"00002c1c",
+ 2827 => x"00002c24",
+ 2828 => x"00002c24",
+ 2829 => x"00002c2c",
+ 2830 => x"00002c2c",
+ 2831 => x"00002c34",
+ 2832 => x"00002c34",
+ 2833 => x"00002c3c",
+ 2834 => x"00002c3c",
+ 2835 => x"00002c44",
+ 2836 => x"00002c44",
+ 2837 => x"00002c4c",
+ 2838 => x"00002c4c",
+ 2839 => x"00002c54",
+ 2840 => x"00002c54",
+ 2841 => x"00002c5c",
+ 2842 => x"00002c5c",
+ 2843 => x"00002c64",
+ 2844 => x"00002c64",
+ 2845 => x"00002c6c",
+ 2846 => x"00002c6c",
+ 2847 => x"00002c74",
+ 2848 => x"00002c74",
+ 2849 => x"00002c7c",
+ 2850 => x"00002c7c",
+ 2851 => x"00002c84",
+ 2852 => x"00002c84",
+ 2853 => x"00002c8c",
+ 2854 => x"00002c8c",
+ 2855 => x"00002c94",
+ 2856 => x"00002c94",
+ 2857 => x"00002c9c",
+ 2858 => x"00002c9c",
+ 2859 => x"00002ca4",
+ 2860 => x"00002ca4",
+ 2861 => x"00002cac",
+ 2862 => x"00002cac",
+ 2863 => x"00002cb4",
+ 2864 => x"00002cb4",
+ 2865 => x"00002cbc",
+ 2866 => x"00002cbc",
+ 2867 => x"00002cc4",
+ 2868 => x"00002cc4",
+ 2869 => x"00002ccc",
+ 2870 => x"00002ccc",
+ 2871 => x"00002cd4",
+ 2872 => x"00002cd4",
+ 2873 => x"00002cdc",
+ 2874 => x"00002cdc",
+ 2875 => x"00002ce4",
+ 2876 => x"00002ce4",
+ 2877 => x"00002cec",
+ 2878 => x"00002cec",
+ 2879 => x"00002cf4",
+ 2880 => x"00002cf4",
+ 2881 => x"00002cfc",
+ 2882 => x"00002cfc",
+ 2883 => x"00002d04",
+ 2884 => x"00002d04",
+ 2885 => x"00002d0c",
+ 2886 => x"00002d0c",
+ 2887 => x"00002d14",
+ 2888 => x"00002d14",
+ 2889 => x"00002d1c",
+ 2890 => x"00002d1c",
+ 2891 => x"00002d24",
+ 2892 => x"00002d24",
+ 2893 => x"00002d2c",
+ 2894 => x"00002d2c",
+ 2895 => x"00002d34",
+ 2896 => x"00002d34",
+ 2897 => x"00002d3c",
+ 2898 => x"00002d3c",
+ 2899 => x"00002d44",
+ 2900 => x"00002d44",
+ 2901 => x"00002d4c",
+ 2902 => x"00002d4c",
+ 2903 => x"00002d54",
+ 2904 => x"00002d54",
+ 2905 => x"00002d5c",
+ 2906 => x"00002d5c",
+ 2907 => x"00002d64",
+ 2908 => x"00002d64",
+ 2909 => x"00002d6c",
+ 2910 => x"00002d6c",
+ 2911 => x"00002d74",
+ 2912 => x"00002d74",
+ 2913 => x"00002d7c",
+ 2914 => x"00002d7c",
+ 2915 => x"00002d84",
+ 2916 => x"00002d84",
+ 2917 => x"00002d8c",
+ 2918 => x"00002d8c",
+ 2919 => x"00002d94",
+ 2920 => x"00002d94",
+ 2921 => x"00002d9c",
+ 2922 => x"00002d9c",
+ 2923 => x"00002da4",
+ 2924 => x"00002da4",
+ 2925 => x"00002dac",
+ 2926 => x"00002dac",
+ 2927 => x"00002db4",
+ 2928 => x"00002db4",
+ 2929 => x"00002dbc",
+ 2930 => x"00002dbc",
+ 2931 => x"00002dc4",
+ 2932 => x"00002dc4",
+ 2933 => x"00002dcc",
+ 2934 => x"00002dcc",
+ 2935 => x"00002dd4",
+ 2936 => x"00002dd4",
+ 2937 => x"00002ddc",
+ 2938 => x"00002ddc",
+ 2939 => x"00002de4",
+ 2940 => x"00002de4",
+ 2941 => x"00002dec",
+ 2942 => x"00002dec",
+ 2943 => x"00002df4",
+ 2944 => x"00002df4",
+ 2945 => x"00002dfc",
+ 2946 => x"00002dfc",
+ 2947 => x"00002e04",
+ 2948 => x"00002e04",
+ 2949 => x"00002e0c",
+ 2950 => x"00002e0c",
+ 2951 => x"00002e14",
+ 2952 => x"00002e14",
+ 2953 => x"00002e1c",
+ 2954 => x"00002e1c",
+ 2955 => x"00002e24",
+ 2956 => x"00002e24",
+ 2957 => x"00002e2c",
+ 2958 => x"00002e2c",
+ 2959 => x"00002e34",
+ 2960 => x"00002e34",
+ 2961 => x"00002e3c",
+ 2962 => x"00002e3c",
+ 2963 => x"00002e44",
+ 2964 => x"00002e44",
+ 2965 => x"00002e4c",
+ 2966 => x"00002e4c",
+ 2967 => x"00002e54",
+ 2968 => x"00002e54",
+ 2969 => x"00002e5c",
+ 2970 => x"00002e5c",
+ 2971 => x"00002e64",
+ 2972 => x"00002e64",
+ 2973 => x"00002e6c",
+ 2974 => x"00002e6c",
+ 2975 => x"00002e74",
+ 2976 => x"00002e74",
+ 2977 => x"00002e7c",
+ 2978 => x"00002e7c",
+ 2979 => x"00002e84",
+ 2980 => x"00002e84",
+ 2981 => x"00002e8c",
+ 2982 => x"00002e8c",
+ 2983 => x"00002e94",
+ 2984 => x"00002e94",
+ 2985 => x"00002e9c",
+ 2986 => x"00002e9c",
+ 2987 => x"00002ea4",
+ 2988 => x"00002ea4",
+ 2989 => x"00002eac",
+ 2990 => x"00002eac",
+ 2991 => x"00002eb4",
+ 2992 => x"00002eb4",
+ 2993 => x"00002ebc",
+ 2994 => x"00002ebc",
+ 2995 => x"00002ec4",
+ 2996 => x"00002ec4",
+ 2997 => x"00002ecc",
+ 2998 => x"00002ecc",
+ 2999 => x"00002ed4",
+ 3000 => x"00002ed4",
+ 3001 => x"00002edc",
+ 3002 => x"00002edc",
+ 3003 => x"00002ee4",
+ 3004 => x"00002ee4",
+ 3005 => x"00002eec",
+ 3006 => x"00002eec",
+ 3007 => x"00002ef4",
+ 3008 => x"00002ef4",
+ 3009 => x"00002efc",
+ 3010 => x"00002efc",
+ 3011 => x"00002f04",
+ 3012 => x"00002f04",
+ 3013 => x"00002f0c",
+ 3014 => x"00002f0c",
+ 3015 => x"00002f14",
+ 3016 => x"00002f14",
+ 3017 => x"00002f1c",
+ 3018 => x"00002f1c",
+ 3019 => x"00002f24",
+ 3020 => x"00002f24",
+ 3021 => x"00002f2c",
+ 3022 => x"00002f2c",
+ 3023 => x"00002f34",
+ 3024 => x"00002f34",
+ 3025 => x"00002f3c",
+ 3026 => x"00002f3c",
+ 3027 => x"00002f50",
+ 3028 => x"00000000",
+ 3029 => x"000031b8",
+ 3030 => x"00003214",
+ 3031 => x"00003270",
+ 3032 => x"00000000",
+ 3033 => x"00000000",
+ 3034 => x"00000000",
+ 3035 => x"00000000",
+ 3036 => x"00000000",
+ 3037 => x"00000000",
+ 3038 => x"00000000",
+ 3039 => x"00000000",
+ 3040 => x"00000000",
+ 3041 => x"00002ad0",
+ 3042 => x"00000000",
+ 3043 => x"00000000",
+ 3044 => x"00000000",
+ 3045 => x"00000000",
+ 3046 => x"00000000",
+ 3047 => x"00000000",
+ 3048 => x"00000000",
+ 3049 => x"00000000",
+ 3050 => x"00000000",
+ 3051 => x"00000000",
+ 3052 => x"00000000",
+ 3053 => x"00000000",
+ 3054 => x"00000000",
+ 3055 => x"00000000",
+ 3056 => x"00000000",
+ 3057 => x"00000000",
+ 3058 => x"00000000",
+ 3059 => x"00000000",
+ 3060 => x"00000000",
+ 3061 => x"00000000",
+ 3062 => x"00000000",
+ 3063 => x"00000000",
+ 3064 => x"00000000",
+ 3065 => x"00000000",
+ 3066 => x"00000000",
+ 3067 => x"00000000",
+ 3068 => x"00000000",
+ 3069 => x"00000000",
+ 3070 => x"00000001",
+ 3071 => x"330eabcd",
+ 3072 => x"1234e66d",
+ 3073 => x"deec0005",
+ 3074 => x"000b0000",
+ 3075 => x"00000000",
+ 3076 => x"00000000",
+ 3077 => x"00000000",
+ 3078 => x"00000000",
+ 3079 => x"00000000",
+ 3080 => x"00000000",
+ 3081 => x"00000000",
+ 3082 => x"00000000",
+ 3083 => x"00000000",
+ 3084 => x"00000000",
+ 3085 => x"00000000",
+ 3086 => x"00000000",
+ 3087 => x"00000000",
+ 3088 => x"00000000",
+ 3089 => x"00000000",
+ 3090 => x"00000000",
+ 3091 => x"00000000",
+ 3092 => x"00000000",
+ 3093 => x"00000000",
+ 3094 => x"00000000",
+ 3095 => x"00000000",
+ 3096 => x"00000000",
+ 3097 => x"00000000",
+ 3098 => x"00000000",
+ 3099 => x"00000000",
+ 3100 => x"00000000",
+ 3101 => x"00000000",
+ 3102 => x"00000000",
+ 3103 => x"00000000",
+ 3104 => x"00000000",
+ 3105 => x"00000000",
+ 3106 => x"00000000",
+ 3107 => x"00000000",
+ 3108 => x"00000000",
+ 3109 => x"00000000",
+ 3110 => x"00000000",
+ 3111 => x"00000000",
+ 3112 => x"00000000",
+ 3113 => x"00000000",
+ 3114 => x"00000000",
+ 3115 => x"00000000",
+ 3116 => x"00000000",
+ 3117 => x"00000000",
+ 3118 => x"00000000",
+ 3119 => x"00000000",
+ 3120 => x"00000000",
+ 3121 => x"00000000",
+ 3122 => x"00000000",
+ 3123 => x"00000000",
+ 3124 => x"00000000",
+ 3125 => x"00000000",
+ 3126 => x"00000000",
+ 3127 => x"00000000",
+ 3128 => x"00000000",
+ 3129 => x"00000000",
+ 3130 => x"00000000",
+ 3131 => x"00000000",
+ 3132 => x"00000000",
+ 3133 => x"00000000",
+ 3134 => x"00000000",
+ 3135 => x"00000000",
+ 3136 => x"00000000",
+ 3137 => x"00000000",
+ 3138 => x"00000000",
+ 3139 => x"00000000",
+ 3140 => x"00000000",
+ 3141 => x"00000000",
+ 3142 => x"00000000",
+ 3143 => x"00000000",
+ 3144 => x"00000000",
+ 3145 => x"00000000",
+ 3146 => x"00000000",
+ 3147 => x"00000000",
+ 3148 => x"00000000",
+ 3149 => x"00000000",
+ 3150 => x"00000000",
+ 3151 => x"00000000",
+ 3152 => x"00000000",
+ 3153 => x"00000000",
+ 3154 => x"00000000",
+ 3155 => x"00000000",
+ 3156 => x"00000000",
+ 3157 => x"00000000",
+ 3158 => x"00000000",
+ 3159 => x"00000000",
+ 3160 => x"00000000",
+ 3161 => x"00000000",
+ 3162 => x"00000000",
+ 3163 => x"00000000",
+ 3164 => x"00000000",
+ 3165 => x"00000000",
+ 3166 => x"00000000",
+ 3167 => x"00000000",
+ 3168 => x"00000000",
+ 3169 => x"00000000",
+ 3170 => x"00000000",
+ 3171 => x"00000000",
+ 3172 => x"00000000",
+ 3173 => x"00000000",
+ 3174 => x"00000000",
+ 3175 => x"00000000",
+ 3176 => x"00000000",
+ 3177 => x"00000000",
+ 3178 => x"00000000",
+ 3179 => x"00000000",
+ 3180 => x"00000000",
+ 3181 => x"00000000",
+ 3182 => x"00000000",
+ 3183 => x"00000000",
+ 3184 => x"00000000",
+ 3185 => x"00000000",
+ 3186 => x"00000000",
+ 3187 => x"00000000",
+ 3188 => x"00000000",
+ 3189 => x"00000000",
+ 3190 => x"00000000",
+ 3191 => x"00000000",
+ 3192 => x"00000000",
+ 3193 => x"00000000",
+ 3194 => x"00000000",
+ 3195 => x"00000000",
+ 3196 => x"00000000",
+ 3197 => x"00000000",
+ 3198 => x"00000000",
+ 3199 => x"00000000",
+ 3200 => x"00000000",
+ 3201 => x"00000000",
+ 3202 => x"00000000",
+ 3203 => x"00000000",
+ 3204 => x"00000000",
+ 3205 => x"00000000",
+ 3206 => x"00000000",
+ 3207 => x"00000000",
+ 3208 => x"00000000",
+ 3209 => x"00000000",
+ 3210 => x"00000000",
+ 3211 => x"00000000",
+ 3212 => x"00000000",
+ 3213 => x"00000000",
+ 3214 => x"00000000",
+ 3215 => x"00000000",
+ 3216 => x"00000000",
+ 3217 => x"00000000",
+ 3218 => x"00000000",
+ 3219 => x"00000000",
+ 3220 => x"00000000",
+ 3221 => x"00000000",
+ 3222 => x"00000000",
+ 3223 => x"00000000",
+ 3224 => x"00000000",
+ 3225 => x"00000000",
+ 3226 => x"00000000",
+ 3227 => x"00000000",
+ 3228 => x"00000000",
+ 3229 => x"00000000",
+ 3230 => x"00000000",
+ 3231 => x"00000000",
+ 3232 => x"00000000",
+ 3233 => x"00000000",
+ 3234 => x"00000000",
+ 3235 => x"00000000",
+ 3236 => x"00000000",
+ 3237 => x"00000000",
+ 3238 => x"00000000",
+ 3239 => x"00000000",
+ 3240 => x"00000000",
+ 3241 => x"00000000",
+ 3242 => x"00000000",
+ 3243 => x"00000000",
+ 3244 => x"00000000",
+ 3245 => x"00000000",
+ 3246 => x"00000000",
+ 3247 => x"00000000",
+ 3248 => x"00000000",
+ 3249 => x"00000000",
+ 3250 => x"00000000",
+ 3251 => x"00002ad4",
+ 3252 => x"ffffffff",
+ 3253 => x"00000000",
+ 3254 => x"ffffffff",
+ 3255 => x"00000000",
+ 3256 => x"00000000",
+ others => x"00000000"
+);
+
+begin
+
+process (clk)
+begin
+ if (clk'event and clk = '1') then
+ if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then
+ report "write collision" severity failure;
+ end if;
+
+ if (memAWriteEnable = '1') then
+ ram(to_integer(unsigned(memAAddr))) := memAWrite;
+ memARead <= memAWrite;
+ else
+ memARead <= ram(to_integer(unsigned(memAAddr)));
+ end if;
+ end if;
+end process;
+
+process (clk)
+begin
+ if (clk'event and clk = '1') then
+ if (memBWriteEnable = '1') then
+ ram(to_integer(unsigned(memBAddr))) := memBWrite;
+ memBRead <= memBWrite;
+ else
+ memBRead <= ram(to_integer(unsigned(memBAddr)));
+ end if;
+ end if;
+end process;
+
+
+
+
+end dualport_ram_arch;
diff --git a/zpu/hdl/example/helloworld.vhd b/zpu/hdl/example/helloworld.vhd
new file mode 100644
index 0000000..cc8d8c6
--- /dev/null
+++ b/zpu/hdl/example/helloworld.vhd
@@ -0,0 +1,3154 @@
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+--
+-- The FreeBSD license
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+--
+-- 1. Redistributions of source code must retain the above copyright
+-- notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+-- copyright notice, this list of conditions and the following
+-- disclaimer in the documentation and/or other materials
+-- provided with the distribution.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity dualport_ram is
+port (clk : in std_logic;
+ memAWriteEnable : in std_logic;
+ memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+ memAWrite : in std_logic_vector(wordSize-1 downto 0);
+ memARead : out std_logic_vector(wordSize-1 downto 0);
+ memBWriteEnable : in std_logic;
+ memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+ memBWrite : in std_logic_vector(wordSize-1 downto 0);
+ memBRead : out std_logic_vector(wordSize-1 downto 0));
+end dualport_ram;
+
+architecture dualport_ram_arch of dualport_ram is
+
+
+type ram_type is array(natural range 0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
+
+shared variable ram : ram_type :=
+(
+0 => x"0b0b0b0b",
+1 => x"82700b0b",
+2 => x"80cfd80c",
+3 => x"3a0b0b80",
+4 => x"c6d00400",
+5 => x"00000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"80c7972d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
+17 => x"72830609",
+18 => x"81058205",
+19 => x"832b2a83",
+20 => x"ffff0652",
+21 => x"04000000",
+22 => x"00000000",
+23 => x"00000000",
+24 => x"71fd0608",
+25 => x"83ffff73",
+26 => x"83060981",
+27 => x"05820583",
+28 => x"2b2b0906",
+29 => x"7383ffff",
+30 => x"0b0b0b0b",
+31 => x"83a70400",
+32 => x"72098105",
+33 => x"72057373",
+34 => x"09060906",
+35 => x"73097306",
+36 => x"070a8106",
+37 => x"53510400",
+38 => x"00000000",
+39 => x"00000000",
+40 => x"72722473",
+41 => x"732e0753",
+42 => x"51040000",
+43 => x"00000000",
+44 => x"00000000",
+45 => x"00000000",
+46 => x"00000000",
+47 => x"00000000",
+48 => x"71737109",
+49 => x"71068106",
+50 => x"30720a10",
+51 => x"0a720a10",
+52 => x"0a31050a",
+53 => x"81065151",
+54 => x"53510400",
+55 => x"00000000",
+56 => x"72722673",
+57 => x"732e0753",
+58 => x"51040000",
+59 => x"00000000",
+60 => x"00000000",
+61 => x"00000000",
+62 => x"00000000",
+63 => x"00000000",
+64 => x"00000000",
+65 => x"00000000",
+66 => x"00000000",
+67 => x"00000000",
+68 => x"00000000",
+69 => x"00000000",
+70 => x"00000000",
+71 => x"00000000",
+72 => x"0b0b0b88",
+73 => x"c4040000",
+74 => x"00000000",
+75 => x"00000000",
+76 => x"00000000",
+77 => x"00000000",
+78 => x"00000000",
+79 => x"00000000",
+80 => x"720a722b",
+81 => x"0a535104",
+82 => x"00000000",
+83 => x"00000000",
+84 => x"00000000",
+85 => x"00000000",
+86 => x"00000000",
+87 => x"00000000",
+88 => x"72729f06",
+89 => x"0981050b",
+90 => x"0b0b88a7",
+91 => x"05040000",
+92 => x"00000000",
+93 => x"00000000",
+94 => x"00000000",
+95 => x"00000000",
+96 => x"72722aff",
+97 => x"739f062a",
+98 => x"0974090a",
+99 => x"8106ff05",
+100 => x"06075351",
+101 => x"04000000",
+102 => x"00000000",
+103 => x"00000000",
+104 => x"71715351",
+105 => x"020d0406",
+106 => x"73830609",
+107 => x"81058205",
+108 => x"832b0b2b",
+109 => x"0772fc06",
+110 => x"0c515104",
+111 => x"00000000",
+112 => x"72098105",
+113 => x"72050970",
+114 => x"81050906",
+115 => x"0a810653",
+116 => x"51040000",
+117 => x"00000000",
+118 => x"00000000",
+119 => x"00000000",
+120 => x"72098105",
+121 => x"72050970",
+122 => x"81050906",
+123 => x"0a098106",
+124 => x"53510400",
+125 => x"00000000",
+126 => x"00000000",
+127 => x"00000000",
+128 => x"71098105",
+129 => x"52040000",
+130 => x"00000000",
+131 => x"00000000",
+132 => x"00000000",
+133 => x"00000000",
+134 => x"00000000",
+135 => x"00000000",
+136 => x"72720981",
+137 => x"05055351",
+138 => x"04000000",
+139 => x"00000000",
+140 => x"00000000",
+141 => x"00000000",
+142 => x"00000000",
+143 => x"00000000",
+144 => x"72097206",
+145 => x"73730906",
+146 => x"07535104",
+147 => x"00000000",
+148 => x"00000000",
+149 => x"00000000",
+150 => x"00000000",
+151 => x"00000000",
+152 => x"71fc0608",
+153 => x"72830609",
+154 => x"81058305",
+155 => x"1010102a",
+156 => x"81ff0652",
+157 => x"04000000",
+158 => x"00000000",
+159 => x"00000000",
+160 => x"71fc0608",
+161 => x"0b0b80cf",
+162 => x"c4738306",
+163 => x"10100508",
+164 => x"060b0b0b",
+165 => x"88aa0400",
+166 => x"00000000",
+167 => x"00000000",
+168 => x"80088408",
+169 => x"88087575",
+170 => x"0b0b0b8b",
+171 => x"9f2d5050",
+172 => x"80085688",
+173 => x"0c840c80",
+174 => x"0c510400",
+175 => x"00000000",
+176 => x"80088408",
+177 => x"88087575",
+178 => x"0b0b0b8b",
+179 => x"e32d5050",
+180 => x"80085688",
+181 => x"0c840c80",
+182 => x"0c510400",
+183 => x"00000000",
+184 => x"72097081",
+185 => x"0509060a",
+186 => x"8106ff05",
+187 => x"70547106",
+188 => x"73097274",
+189 => x"05ff0506",
+190 => x"07515151",
+191 => x"04000000",
+192 => x"72097081",
+193 => x"0509060a",
+194 => x"098106ff",
+195 => x"05705471",
+196 => x"06730972",
+197 => x"7405ff05",
+198 => x"06075151",
+199 => x"51040000",
+200 => x"05ff0504",
+201 => x"00000000",
+202 => x"00000000",
+203 => x"00000000",
+204 => x"00000000",
+205 => x"00000000",
+206 => x"00000000",
+207 => x"00000000",
+208 => x"810b0b0b",
+209 => x"80cfd40c",
+210 => x"51040000",
+211 => x"00000000",
+212 => x"00000000",
+213 => x"00000000",
+214 => x"00000000",
+215 => x"00000000",
+216 => x"71810552",
+217 => x"04000000",
+218 => x"00000000",
+219 => x"00000000",
+220 => x"00000000",
+221 => x"00000000",
+222 => x"00000000",
+223 => x"00000000",
+224 => x"00000000",
+225 => x"00000000",
+226 => x"00000000",
+227 => x"00000000",
+228 => x"00000000",
+229 => x"00000000",
+230 => x"00000000",
+231 => x"00000000",
+232 => x"02840572",
+233 => x"10100552",
+234 => x"04000000",
+235 => x"00000000",
+236 => x"00000000",
+237 => x"00000000",
+238 => x"00000000",
+239 => x"00000000",
+240 => x"00000000",
+241 => x"00000000",
+242 => x"00000000",
+243 => x"00000000",
+244 => x"00000000",
+245 => x"00000000",
+246 => x"00000000",
+247 => x"00000000",
+248 => x"717105ff",
+249 => x"05715351",
+250 => x"020d0400",
+251 => x"00000000",
+252 => x"00000000",
+253 => x"00000000",
+254 => x"00000000",
+255 => x"00000000",
+256 => x"82c53f80",
+257 => x"c6d93f04",
+258 => x"10101010",
+259 => x"10101010",
+260 => x"10101010",
+261 => x"10101010",
+262 => x"10101010",
+263 => x"10101010",
+264 => x"10101010",
+265 => x"10101053",
+266 => x"51047381",
+267 => x"ff067383",
+268 => x"06098105",
+269 => x"83051010",
+270 => x"102b0772",
+271 => x"fc060c51",
+272 => x"51043c04",
+273 => x"72728072",
+274 => x"8106ff05",
+275 => x"09720605",
+276 => x"71105272",
+277 => x"0a100a53",
+278 => x"72ed3851",
+279 => x"51535104",
+280 => x"fe3d0d0b",
+281 => x"0b80dfc0",
+282 => x"08538413",
+283 => x"0870882a",
+284 => x"70810651",
+285 => x"52527080",
+286 => x"2ef03871",
+287 => x"81ff0680",
+288 => x"0c843d0d",
+289 => x"04ff3d0d",
+290 => x"0b0b80df",
+291 => x"c0085271",
+292 => x"0870882a",
+293 => x"81327081",
+294 => x"06515151",
+295 => x"70f13873",
+296 => x"720c833d",
+297 => x"0d0480cf",
+298 => x"d408802e",
+299 => x"a43880cf",
+300 => x"d808822e",
+301 => x"bd388380",
+302 => x"800b0b0b",
+303 => x"80dfc00c",
+304 => x"82a0800b",
+305 => x"80dfc40c",
+306 => x"8290800b",
+307 => x"80dfc80c",
+308 => x"04f88080",
+309 => x"80a40b0b",
+310 => x"0b80dfc0",
+311 => x"0cf88080",
+312 => x"82800b80",
+313 => x"dfc40cf8",
+314 => x"80808480",
+315 => x"0b80dfc8",
+316 => x"0c0480c0",
+317 => x"a8808c0b",
+318 => x"0b0b80df",
+319 => x"c00c80c0",
+320 => x"a880940b",
+321 => x"80dfc40c",
+322 => x"0b0b80cf",
+323 => x"8c0b80df",
+324 => x"c80c0470",
+325 => x"7080dfcc",
+326 => x"335170a7",
+327 => x"3880cfe0",
+328 => x"08700852",
+329 => x"5270802e",
+330 => x"94388412",
+331 => x"80cfe00c",
+332 => x"702d80cf",
+333 => x"e0087008",
+334 => x"525270ee",
+335 => x"38810b80",
+336 => x"dfcc3450",
+337 => x"50040470",
+338 => x"0b0b80df",
+339 => x"bc08802e",
+340 => x"8e380b0b",
+341 => x"0b0b800b",
+342 => x"802e0981",
+343 => x"06833850",
+344 => x"040b0b80",
+345 => x"dfbc510b",
+346 => x"0b0bf594",
+347 => x"3f500404",
+348 => x"fe3d0d89",
+349 => x"5380cf90",
+350 => x"5182c13f",
+351 => x"80cfa051",
+352 => x"82ba3f81",
+353 => x"0a0b80df",
+354 => x"d80cff0b",
+355 => x"80dfdc0c",
+356 => x"ff135372",
+357 => x"8025de38",
+358 => x"72800c84",
+359 => x"3d0d04fb",
+360 => x"3d0d7779",
+361 => x"55558056",
+362 => x"757524ab",
+363 => x"38807424",
+364 => x"9d388053",
+365 => x"73527451",
+366 => x"80e13f80",
+367 => x"08547580",
+368 => x"2e853880",
+369 => x"08305473",
+370 => x"800c873d",
+371 => x"0d047330",
+372 => x"76813257",
+373 => x"54dc3974",
+374 => x"30558156",
+375 => x"738025d2",
+376 => x"38ec39fa",
+377 => x"3d0d787a",
+378 => x"57558057",
+379 => x"767524a4",
+380 => x"38759f2c",
+381 => x"54815375",
+382 => x"74327431",
+383 => x"5274519b",
+384 => x"3f800854",
+385 => x"76802e85",
+386 => x"38800830",
+387 => x"5473800c",
+388 => x"883d0d04",
+389 => x"74305581",
+390 => x"57d739fc",
+391 => x"3d0d7678",
+392 => x"53548153",
+393 => x"80747326",
+394 => x"52557280",
+395 => x"2e983870",
+396 => x"802eab38",
+397 => x"807224a6",
+398 => x"38711073",
+399 => x"10757226",
+400 => x"53545272",
+401 => x"ea387351",
+402 => x"78833874",
+403 => x"5170800c",
+404 => x"863d0d04",
+405 => x"720a100a",
+406 => x"720a100a",
+407 => x"53537280",
+408 => x"2ee43871",
+409 => x"7426ed38",
+410 => x"73723175",
+411 => x"7407740a",
+412 => x"100a740a",
+413 => x"100a5555",
+414 => x"5654e339",
+415 => x"f73d0d7c",
+416 => x"70525380",
+417 => x"f93f7254",
+418 => x"80085580",
+419 => x"cfb05681",
+420 => x"57800881",
+421 => x"055a8b3d",
+422 => x"e4115953",
+423 => x"8259f413",
+424 => x"527b8811",
+425 => x"08525381",
+426 => x"b23f8008",
+427 => x"30708008",
+428 => x"079f2c8a",
+429 => x"07800c53",
+430 => x"8b3d0d04",
+431 => x"f63d0d7c",
+432 => x"80cfe408",
+433 => x"71535553",
+434 => x"b53f7255",
+435 => x"80085680",
+436 => x"cfb05781",
+437 => x"58800881",
+438 => x"055b8c3d",
+439 => x"e4115a53",
+440 => x"825af413",
+441 => x"52881408",
+442 => x"5180f03f",
+443 => x"80083070",
+444 => x"8008079f",
+445 => x"2c8a0780",
+446 => x"0c548c3d",
+447 => x"0d047070",
+448 => x"70707570",
+449 => x"71830653",
+450 => x"555270b4",
+451 => x"38717008",
+452 => x"7009f7fb",
+453 => x"fdff1206",
+454 => x"f8848281",
+455 => x"80065452",
+456 => x"53719b38",
+457 => x"84137008",
+458 => x"7009f7fb",
+459 => x"fdff1206",
+460 => x"f8848281",
+461 => x"80065452",
+462 => x"5371802e",
+463 => x"e7387252",
+464 => x"71335372",
+465 => x"802e8a38",
+466 => x"81127033",
+467 => x"545272f8",
+468 => x"38717431",
+469 => x"800c5050",
+470 => x"505004f2",
+471 => x"3d0d6062",
+472 => x"88110870",
+473 => x"58565f5a",
+474 => x"73802e81",
+475 => x"8c388c1a",
+476 => x"2270832a",
+477 => x"81328106",
+478 => x"56587486",
+479 => x"38901a08",
+480 => x"91387951",
+481 => x"90b73fff",
+482 => x"55800880",
+483 => x"ec388c1a",
+484 => x"22587d08",
+485 => x"55807883",
+486 => x"ffff0670",
+487 => x"0a100a81",
+488 => x"06415c57",
+489 => x"7e772e80",
+490 => x"d7387690",
+491 => x"38740884",
+492 => x"16088817",
+493 => x"57585676",
+494 => x"802ef238",
+495 => x"76548880",
+496 => x"77278438",
+497 => x"88805473",
+498 => x"5375529c",
+499 => x"1a0851a4",
+500 => x"1a085877",
+501 => x"2d800b80",
+502 => x"082582e0",
+503 => x"38800816",
+504 => x"77800831",
+505 => x"7f880508",
+506 => x"80083170",
+507 => x"6188050c",
+508 => x"5b585678",
+509 => x"ffb43880",
+510 => x"5574800c",
+511 => x"903d0d04",
+512 => x"7a813281",
+513 => x"06774056",
+514 => x"75802e81",
+515 => x"bd387690",
+516 => x"38740884",
+517 => x"16088817",
+518 => x"57585976",
+519 => x"802ef238",
+520 => x"881a0878",
+521 => x"83ffff06",
+522 => x"70892a81",
+523 => x"06565956",
+524 => x"73802e82",
+525 => x"f8387577",
+526 => x"278b3877",
+527 => x"872a8106",
+528 => x"5c7b82b5",
+529 => x"38767627",
+530 => x"83387656",
+531 => x"75537852",
+532 => x"79085185",
+533 => x"833f881a",
+534 => x"08763188",
+535 => x"1b0c7908",
+536 => x"167a0c76",
+537 => x"56751977",
+538 => x"77317f88",
+539 => x"05087831",
+540 => x"70618805",
+541 => x"0c415859",
+542 => x"7e802efe",
+543 => x"fa388c1a",
+544 => x"2258ff8a",
+545 => x"39787954",
+546 => x"7c537b52",
+547 => x"5684c93f",
+548 => x"881a0879",
+549 => x"31881b0c",
+550 => x"7908197a",
+551 => x"0c7c7631",
+552 => x"5d7c8e38",
+553 => x"79518ff2",
+554 => x"3f800881",
+555 => x"8f388008",
+556 => x"5f751c77",
+557 => x"77317f88",
+558 => x"05087831",
+559 => x"70618805",
+560 => x"0c5d585c",
+561 => x"7a802efe",
+562 => x"ae387681",
+563 => x"83387408",
+564 => x"84160888",
+565 => x"1757585c",
+566 => x"76802ef2",
+567 => x"3876538a",
+568 => x"527b5182",
+569 => x"d33f8008",
+570 => x"7c318105",
+571 => x"5d800884",
+572 => x"3881175d",
+573 => x"815f7c59",
+574 => x"767d2783",
+575 => x"38765994",
+576 => x"1a08881b",
+577 => x"08115758",
+578 => x"807a085c",
+579 => x"54901a08",
+580 => x"7b278338",
+581 => x"81547579",
+582 => x"25843873",
+583 => x"ba387779",
+584 => x"24fee238",
+585 => x"77537b52",
+586 => x"9c1a0851",
+587 => x"a41a0859",
+588 => x"782d8008",
+589 => x"56800880",
+590 => x"24fee238",
+591 => x"8c1a2280",
+592 => x"c0075e7d",
+593 => x"8c1b23ff",
+594 => x"5574800c",
+595 => x"903d0d04",
+596 => x"7effa338",
+597 => x"ff873975",
+598 => x"537b527a",
+599 => x"5182f93f",
+600 => x"7908167a",
+601 => x"0c79518e",
+602 => x"b13f8008",
+603 => x"cf387c76",
+604 => x"315d7cfe",
+605 => x"bc38feac",
+606 => x"39901a08",
+607 => x"7a087131",
+608 => x"78117056",
+609 => x"5a575280",
+610 => x"cfe40851",
+611 => x"84943f80",
+612 => x"08802eff",
+613 => x"a7388008",
+614 => x"901b0c80",
+615 => x"08167a0c",
+616 => x"77941b0c",
+617 => x"76881b0c",
+618 => x"7656fd99",
+619 => x"39790858",
+620 => x"901a0878",
+621 => x"27833881",
+622 => x"54757727",
+623 => x"843873b3",
+624 => x"38941a08",
+625 => x"54737726",
+626 => x"80d33873",
+627 => x"5378529c",
+628 => x"1a0851a4",
+629 => x"1a085877",
+630 => x"2d800856",
+631 => x"80088024",
+632 => x"fd83388c",
+633 => x"1a2280c0",
+634 => x"075e7d8c",
+635 => x"1b23ff55",
+636 => x"fed73975",
+637 => x"53785277",
+638 => x"5181dd3f",
+639 => x"7908167a",
+640 => x"0c79518d",
+641 => x"953f8008",
+642 => x"802efcd9",
+643 => x"388c1a22",
+644 => x"80c0075e",
+645 => x"7d8c1b23",
+646 => x"ff55fead",
+647 => x"39767754",
+648 => x"79537852",
+649 => x"5681b13f",
+650 => x"881a0877",
+651 => x"31881b0c",
+652 => x"7908177a",
+653 => x"0cfcae39",
+654 => x"fa3d0d7a",
+655 => x"79028805",
+656 => x"a7053355",
+657 => x"53548374",
+658 => x"2780df38",
+659 => x"71830651",
+660 => x"7080d738",
+661 => x"71715755",
+662 => x"83517582",
+663 => x"802913ff",
+664 => x"12525670",
+665 => x"8025f338",
+666 => x"837427bc",
+667 => x"38740876",
+668 => x"327009f7",
+669 => x"fbfdff12",
+670 => x"06f88482",
+671 => x"81800651",
+672 => x"5170802e",
+673 => x"98387451",
+674 => x"80527033",
+675 => x"5772772e",
+676 => x"b9388111",
+677 => x"81135351",
+678 => x"837227ee",
+679 => x"38fc1484",
+680 => x"16565473",
+681 => x"8326c638",
+682 => x"7452ff14",
+683 => x"5170ff2e",
+684 => x"97387133",
+685 => x"5472742e",
+686 => x"98388112",
+687 => x"ff125252",
+688 => x"70ff2e09",
+689 => x"8106eb38",
+690 => x"80517080",
+691 => x"0c883d0d",
+692 => x"0471800c",
+693 => x"883d0d04",
+694 => x"fa3d0d78",
+695 => x"7a7c7272",
+696 => x"72595755",
+697 => x"58565774",
+698 => x"7727b238",
+699 => x"75155176",
+700 => x"7127aa38",
+701 => x"707618ff",
+702 => x"18535353",
+703 => x"70ff2e96",
+704 => x"38ff12ff",
+705 => x"14545272",
+706 => x"337234ff",
+707 => x"115170ff",
+708 => x"2e098106",
+709 => x"ec387680",
+710 => x"0c883d0d",
+711 => x"048f7627",
+712 => x"80e63874",
+713 => x"77078306",
+714 => x"517080dc",
+715 => x"38767552",
+716 => x"53707084",
+717 => x"05520873",
+718 => x"70840555",
+719 => x"0c727170",
+720 => x"84055308",
+721 => x"71708405",
+722 => x"530c7170",
+723 => x"84055308",
+724 => x"71708405",
+725 => x"530c7170",
+726 => x"84055308",
+727 => x"71708405",
+728 => x"530cf015",
+729 => x"5553738f",
+730 => x"26c73883",
+731 => x"74279538",
+732 => x"70708405",
+733 => x"52087370",
+734 => x"8405550c",
+735 => x"fc145473",
+736 => x"8326ed38",
+737 => x"72715452",
+738 => x"ff145170",
+739 => x"ff2eff86",
+740 => x"38727081",
+741 => x"05543372",
+742 => x"70810554",
+743 => x"34ff1151",
+744 => x"ea39ef3d",
+745 => x"0d636567",
+746 => x"405d427b",
+747 => x"802e8582",
+748 => x"386151a9",
+749 => x"e73ff81c",
+750 => x"70841208",
+751 => x"70fc0670",
+752 => x"628b0570",
+753 => x"f8064159",
+754 => x"455c5f41",
+755 => x"57967427",
+756 => x"82c53880",
+757 => x"7b247e7c",
+758 => x"26075880",
+759 => x"5477742e",
+760 => x"09810682",
+761 => x"ab38787b",
+762 => x"2581fe38",
+763 => x"781780d7",
+764 => x"a00b8805",
+765 => x"085b5679",
+766 => x"762e84c5",
+767 => x"38841608",
+768 => x"70fe0617",
+769 => x"84110881",
+770 => x"06415555",
+771 => x"7e828d38",
+772 => x"74fc0658",
+773 => x"79762e84",
+774 => x"e3387818",
+775 => x"5f7e7b25",
+776 => x"81ff387c",
+777 => x"81065473",
+778 => x"82c13876",
+779 => x"77083184",
+780 => x"1108fc06",
+781 => x"56577580",
+782 => x"2e913879",
+783 => x"762e84f0",
+784 => x"38741819",
+785 => x"58777b25",
+786 => x"84913876",
+787 => x"802e829b",
+788 => x"38781556",
+789 => x"7a762482",
+790 => x"92388c17",
+791 => x"08881808",
+792 => x"718c120c",
+793 => x"88120c5e",
+794 => x"75598817",
+795 => x"61fc055b",
+796 => x"5679a426",
+797 => x"85ff387b",
+798 => x"76595593",
+799 => x"7a2780c9",
+800 => x"387b7084",
+801 => x"055d087c",
+802 => x"56760c74",
+803 => x"70840556",
+804 => x"088c180c",
+805 => x"9017589b",
+806 => x"7a27ae38",
+807 => x"74708405",
+808 => x"5608780c",
+809 => x"74708405",
+810 => x"56089418",
+811 => x"0c981758",
+812 => x"a37a2795",
+813 => x"38747084",
+814 => x"05560878",
+815 => x"0c747084",
+816 => x"0556089c",
+817 => x"180ca017",
+818 => x"58747084",
+819 => x"05560875",
+820 => x"5f787084",
+821 => x"055a0c77",
+822 => x"7e708405",
+823 => x"40087170",
+824 => x"8405530c",
+825 => x"7e08710c",
+826 => x"5d787b31",
+827 => x"56758f26",
+828 => x"80c93884",
+829 => x"17088106",
+830 => x"79078418",
+831 => x"0c781784",
+832 => x"11088107",
+833 => x"84120c5b",
+834 => x"6151a791",
+835 => x"3f881754",
+836 => x"73800c93",
+837 => x"3d0d0490",
+838 => x"5bfdb839",
+839 => x"7756fe83",
+840 => x"398c1608",
+841 => x"88170871",
+842 => x"8c120c88",
+843 => x"120c587e",
+844 => x"707c3157",
+845 => x"598f7627",
+846 => x"ffb9387a",
+847 => x"17841808",
+848 => x"81067c07",
+849 => x"84190c76",
+850 => x"81078412",
+851 => x"0c761184",
+852 => x"11088107",
+853 => x"84120c5b",
+854 => x"88055261",
+855 => x"518fda3f",
+856 => x"6151a6b9",
+857 => x"3f881754",
+858 => x"ffa6397d",
+859 => x"52615197",
+860 => x"d73f8008",
+861 => x"5a800880",
+862 => x"2e81ab38",
+863 => x"8008f805",
+864 => x"60840508",
+865 => x"fe066105",
+866 => x"58557477",
+867 => x"2e83f238",
+868 => x"fc195877",
+869 => x"a42681b0",
+870 => x"387b8008",
+871 => x"56579378",
+872 => x"2780dc38",
+873 => x"7b707084",
+874 => x"05520880",
+875 => x"08708405",
+876 => x"800c0c80",
+877 => x"08717084",
+878 => x"0553085d",
+879 => x"567b7670",
+880 => x"8405580c",
+881 => x"579b7827",
+882 => x"b6387670",
+883 => x"84055808",
+884 => x"75708405",
+885 => x"570c7670",
+886 => x"84055808",
+887 => x"75708405",
+888 => x"570ca378",
+889 => x"27993876",
+890 => x"70840558",
+891 => x"08757084",
+892 => x"05570c76",
+893 => x"70840558",
+894 => x"08757084",
+895 => x"05570c76",
+896 => x"70840558",
+897 => x"08775e75",
+898 => x"70840557",
+899 => x"0c747d70",
+900 => x"84055f08",
+901 => x"71708405",
+902 => x"530c7d08",
+903 => x"710c5f7b",
+904 => x"5261518e",
+905 => x"943f6151",
+906 => x"a4f33f79",
+907 => x"800c933d",
+908 => x"0d047d52",
+909 => x"61519690",
+910 => x"3f800880",
+911 => x"0c933d0d",
+912 => x"04841608",
+913 => x"55fbc939",
+914 => x"77537b52",
+915 => x"800851a2",
+916 => x"a53f7b52",
+917 => x"61518de1",
+918 => x"3fcc398c",
+919 => x"16088817",
+920 => x"08718c12",
+921 => x"0c88120c",
+922 => x"5d8c1708",
+923 => x"88180871",
+924 => x"8c120c88",
+925 => x"120c5977",
+926 => x"59fbef39",
+927 => x"7818901c",
+928 => x"40557e75",
+929 => x"24fb9c38",
+930 => x"7a177080",
+931 => x"d7a00b88",
+932 => x"050c757c",
+933 => x"31810784",
+934 => x"120c5684",
+935 => x"17088106",
+936 => x"7b078418",
+937 => x"0c6151a3",
+938 => x"f43f8817",
+939 => x"54fce139",
+940 => x"74181990",
+941 => x"1c5e5a7c",
+942 => x"7a24fb8f",
+943 => x"388c1708",
+944 => x"88180871",
+945 => x"8c120c88",
+946 => x"120c5e88",
+947 => x"1761fc05",
+948 => x"575975a4",
+949 => x"2681b638",
+950 => x"7b795955",
+951 => x"93762780",
+952 => x"c9387b70",
+953 => x"84055d08",
+954 => x"7c56790c",
+955 => x"74708405",
+956 => x"56088c18",
+957 => x"0c901758",
+958 => x"9b7627ae",
+959 => x"38747084",
+960 => x"05560878",
+961 => x"0c747084",
+962 => x"05560894",
+963 => x"180c9817",
+964 => x"58a37627",
+965 => x"95387470",
+966 => x"84055608",
+967 => x"780c7470",
+968 => x"84055608",
+969 => x"9c180ca0",
+970 => x"17587470",
+971 => x"84055608",
+972 => x"75417870",
+973 => x"84055a0c",
+974 => x"77607084",
+975 => x"05420871",
+976 => x"70840553",
+977 => x"0c600871",
+978 => x"0c5e7a17",
+979 => x"7080d7a0",
+980 => x"0b88050c",
+981 => x"7a7c3181",
+982 => x"0784120c",
+983 => x"58841708",
+984 => x"81067b07",
+985 => x"84180c61",
+986 => x"51a2b23f",
+987 => x"78547380",
+988 => x"0c933d0d",
+989 => x"0479537b",
+990 => x"5275519f",
+991 => x"f93ffae9",
+992 => x"39841508",
+993 => x"fc061960",
+994 => x"5859fadd",
+995 => x"3975537b",
+996 => x"5278519f",
+997 => x"e13f7a17",
+998 => x"7080d7a0",
+999 => x"0b88050c",
+1000 => x"7a7c3181",
+1001 => x"0784120c",
+1002 => x"58841708",
+1003 => x"81067b07",
+1004 => x"84180c61",
+1005 => x"51a1e63f",
+1006 => x"7854ffb2",
+1007 => x"39fa3d0d",
+1008 => x"7880cfe4",
+1009 => x"085455b8",
+1010 => x"1308802e",
+1011 => x"81af388c",
+1012 => x"15227083",
+1013 => x"ffff0670",
+1014 => x"832a8132",
+1015 => x"81065555",
+1016 => x"5672802e",
+1017 => x"80da3873",
+1018 => x"842a8132",
+1019 => x"810657ff",
+1020 => x"537680f2",
+1021 => x"3873822a",
+1022 => x"81065473",
+1023 => x"802eb938",
+1024 => x"b0150854",
+1025 => x"73802e9c",
+1026 => x"3880c015",
+1027 => x"5373732e",
+1028 => x"8f387352",
+1029 => x"80cfe408",
+1030 => x"518a9e3f",
+1031 => x"8c152256",
+1032 => x"76b0160c",
+1033 => x"75db0657",
+1034 => x"768c1623",
+1035 => x"800b8416",
+1036 => x"0c901508",
+1037 => x"750c7656",
+1038 => x"75880754",
+1039 => x"738c1623",
+1040 => x"90150880",
+1041 => x"2ebf388c",
+1042 => x"15227081",
+1043 => x"06555373",
+1044 => x"9c38720a",
+1045 => x"100a8106",
+1046 => x"56758538",
+1047 => x"94150854",
+1048 => x"7388160c",
+1049 => x"80537280",
+1050 => x"0c883d0d",
+1051 => x"04800b88",
+1052 => x"160c9415",
+1053 => x"08309816",
+1054 => x"0c8053ea",
+1055 => x"39725182",
+1056 => x"a63ffecb",
+1057 => x"3974518f",
+1058 => x"bc3f8c15",
+1059 => x"22708106",
+1060 => x"55537380",
+1061 => x"2effbb38",
+1062 => x"d439f83d",
+1063 => x"0d7a5776",
+1064 => x"802e8197",
+1065 => x"3880cfe4",
+1066 => x"0854b814",
+1067 => x"08802e80",
+1068 => x"eb388c17",
+1069 => x"2270902b",
+1070 => x"70902c70",
+1071 => x"832a8132",
+1072 => x"81065b5b",
+1073 => x"57557780",
+1074 => x"cb389017",
+1075 => x"08567580",
+1076 => x"2e80c138",
+1077 => x"76087631",
+1078 => x"76780c79",
+1079 => x"83065555",
+1080 => x"73853894",
+1081 => x"17085877",
+1082 => x"88180c80",
+1083 => x"7525a538",
+1084 => x"74537552",
+1085 => x"9c170851",
+1086 => x"a4170854",
+1087 => x"732d800b",
+1088 => x"80082580",
+1089 => x"c9388008",
+1090 => x"16758008",
+1091 => x"31565674",
+1092 => x"8024dd38",
+1093 => x"800b800c",
+1094 => x"8a3d0d04",
+1095 => x"73518187",
+1096 => x"3f8c1722",
+1097 => x"70902b70",
+1098 => x"902c7083",
+1099 => x"2a813281",
+1100 => x"065b5b57",
+1101 => x"5577dd38",
+1102 => x"ff9039a1",
+1103 => x"9a5280cf",
+1104 => x"e408518c",
+1105 => x"d03f8008",
+1106 => x"800c8a3d",
+1107 => x"0d048c17",
+1108 => x"2280c007",
+1109 => x"58778c18",
+1110 => x"23ff0b80",
+1111 => x"0c8a3d0d",
+1112 => x"04fa3d0d",
+1113 => x"797080dc",
+1114 => x"298c1154",
+1115 => x"7a535657",
+1116 => x"8fd63f80",
+1117 => x"08800855",
+1118 => x"56800880",
+1119 => x"2ea23880",
+1120 => x"088c0554",
+1121 => x"800b8008",
+1122 => x"0c768008",
+1123 => x"84050c73",
+1124 => x"80088805",
+1125 => x"0c745380",
+1126 => x"5273519c",
+1127 => x"f53f7554",
+1128 => x"73800c88",
+1129 => x"3d0d0470",
+1130 => x"707074a8",
+1131 => x"e60bbc12",
+1132 => x"0c53810b",
+1133 => x"b8140c80",
+1134 => x"0b84dc14",
+1135 => x"0c830b84",
+1136 => x"e0140c84",
+1137 => x"e81384e4",
+1138 => x"140c8413",
+1139 => x"08518070",
+1140 => x"720c7084",
+1141 => x"130c7088",
+1142 => x"130c5284",
+1143 => x"0b8c1223",
+1144 => x"718e1223",
+1145 => x"7190120c",
+1146 => x"7194120c",
+1147 => x"7198120c",
+1148 => x"709c120c",
+1149 => x"80c1d50b",
+1150 => x"a0120c80",
+1151 => x"c2a10ba4",
+1152 => x"120c80c3",
+1153 => x"9d0ba812",
+1154 => x"0c80c3ee",
+1155 => x"0bac120c",
+1156 => x"88130872",
+1157 => x"710c7284",
+1158 => x"120c7288",
+1159 => x"120c5189",
+1160 => x"0b8c1223",
+1161 => x"810b8e12",
+1162 => x"23719012",
+1163 => x"0c719412",
+1164 => x"0c719812",
+1165 => x"0c709c12",
+1166 => x"0c80c1d5",
+1167 => x"0ba0120c",
+1168 => x"80c2a10b",
+1169 => x"a4120c80",
+1170 => x"c39d0ba8",
+1171 => x"120c80c3",
+1172 => x"ee0bac12",
+1173 => x"0c8c1308",
+1174 => x"72710c72",
+1175 => x"84120c72",
+1176 => x"88120c51",
+1177 => x"8a0b8c12",
+1178 => x"23820b8e",
+1179 => x"12237190",
+1180 => x"120c7194",
+1181 => x"120c7198",
+1182 => x"120c709c",
+1183 => x"120c80c1",
+1184 => x"d50ba012",
+1185 => x"0c80c2a1",
+1186 => x"0ba4120c",
+1187 => x"80c39d0b",
+1188 => x"a8120c80",
+1189 => x"c3ee0bac",
+1190 => x"120c5050",
+1191 => x"5004f83d",
+1192 => x"0d7a80cf",
+1193 => x"e408b811",
+1194 => x"08575758",
+1195 => x"7481ec38",
+1196 => x"a8e60bbc",
+1197 => x"170c810b",
+1198 => x"b8170c74",
+1199 => x"84dc170c",
+1200 => x"830b84e0",
+1201 => x"170c84e8",
+1202 => x"1684e417",
+1203 => x"0c841608",
+1204 => x"75710c75",
+1205 => x"84120c75",
+1206 => x"88120c59",
+1207 => x"840b8c1a",
+1208 => x"23748e1a",
+1209 => x"2374901a",
+1210 => x"0c74941a",
+1211 => x"0c74981a",
+1212 => x"0c789c1a",
+1213 => x"0c80c1d5",
+1214 => x"0ba01a0c",
+1215 => x"80c2a10b",
+1216 => x"a41a0c80",
+1217 => x"c39d0ba8",
+1218 => x"1a0c80c3",
+1219 => x"ee0bac1a",
+1220 => x"0c881608",
+1221 => x"75710c75",
+1222 => x"84120c75",
+1223 => x"88120c57",
+1224 => x"890b8c18",
+1225 => x"23810b8e",
+1226 => x"18237490",
+1227 => x"180c7494",
+1228 => x"180c7498",
+1229 => x"180c769c",
+1230 => x"180c80c1",
+1231 => x"d50ba018",
+1232 => x"0c80c2a1",
+1233 => x"0ba4180c",
+1234 => x"80c39d0b",
+1235 => x"a8180c80",
+1236 => x"c3ee0bac",
+1237 => x"180c8c16",
+1238 => x"0875710c",
+1239 => x"7584120c",
+1240 => x"7588120c",
+1241 => x"548a0b8c",
+1242 => x"1523820b",
+1243 => x"8e152374",
+1244 => x"90150c74",
+1245 => x"94150c74",
+1246 => x"98150c73",
+1247 => x"9c150c80",
+1248 => x"c1d50ba0",
+1249 => x"150c80c2",
+1250 => x"a10ba415",
+1251 => x"0c80c39d",
+1252 => x"0ba8150c",
+1253 => x"80c3ee0b",
+1254 => x"ac150c84",
+1255 => x"dc168811",
+1256 => x"08841208",
+1257 => x"ff055757",
+1258 => x"57807524",
+1259 => x"9f388c16",
+1260 => x"2270902b",
+1261 => x"70902c51",
+1262 => x"55597380",
+1263 => x"2e80ed38",
+1264 => x"80dc16ff",
+1265 => x"16565674",
+1266 => x"8025e338",
+1267 => x"76085574",
+1268 => x"802e8f38",
+1269 => x"74881108",
+1270 => x"841208ff",
+1271 => x"05575757",
+1272 => x"c83982fc",
+1273 => x"5277518a",
+1274 => x"df3f8008",
+1275 => x"80085556",
+1276 => x"8008802e",
+1277 => x"a3388008",
+1278 => x"8c057580",
+1279 => x"080c5484",
+1280 => x"0b800884",
+1281 => x"050c7380",
+1282 => x"0888050c",
+1283 => x"82f05374",
+1284 => x"52735197",
+1285 => x"fd3f7554",
+1286 => x"7374780c",
+1287 => x"5573ffb4",
+1288 => x"388c780c",
+1289 => x"800b800c",
+1290 => x"8a3d0d04",
+1291 => x"810b8c17",
+1292 => x"2373760c",
+1293 => x"7388170c",
+1294 => x"7384170c",
+1295 => x"7390170c",
+1296 => x"7394170c",
+1297 => x"7398170c",
+1298 => x"ff0b8e17",
+1299 => x"2373b017",
+1300 => x"0c73b417",
+1301 => x"0c7380c4",
+1302 => x"170c7380",
+1303 => x"c8170c75",
+1304 => x"800c8a3d",
+1305 => x"0d047070",
+1306 => x"a19a5273",
+1307 => x"5186a63f",
+1308 => x"50500470",
+1309 => x"70a19a52",
+1310 => x"80cfe408",
+1311 => x"5186963f",
+1312 => x"505004fb",
+1313 => x"3d0d7770",
+1314 => x"52569890",
+1315 => x"3f80d7a0",
+1316 => x"0b880508",
+1317 => x"841108fc",
+1318 => x"06707b31",
+1319 => x"9fef05e0",
+1320 => x"8006e080",
+1321 => x"05525555",
+1322 => x"a0807524",
+1323 => x"94388052",
+1324 => x"755197ea",
+1325 => x"3f80d7a8",
+1326 => x"08145372",
+1327 => x"80082e8f",
+1328 => x"38755197",
+1329 => x"d83f8053",
+1330 => x"72800c87",
+1331 => x"3d0d0474",
+1332 => x"30527551",
+1333 => x"97c83f80",
+1334 => x"08ff2ea8",
+1335 => x"3880d7a0",
+1336 => x"0b880508",
+1337 => x"74763181",
+1338 => x"0784120c",
+1339 => x"5380d6e4",
+1340 => x"08753180",
+1341 => x"d6e40c75",
+1342 => x"5197a23f",
+1343 => x"810b800c",
+1344 => x"873d0d04",
+1345 => x"80527551",
+1346 => x"97943f80",
+1347 => x"d7a00b88",
+1348 => x"05088008",
+1349 => x"71315454",
+1350 => x"8f7325ff",
+1351 => x"a4388008",
+1352 => x"80d79408",
+1353 => x"3180d6e4",
+1354 => x"0c728107",
+1355 => x"84150c75",
+1356 => x"5196ea3f",
+1357 => x"8053ff90",
+1358 => x"39f73d0d",
+1359 => x"7b7d545a",
+1360 => x"72802e82",
+1361 => x"83387951",
+1362 => x"96d23ff8",
+1363 => x"13841108",
+1364 => x"70fe0670",
+1365 => x"13841108",
+1366 => x"fc065c57",
+1367 => x"58545780",
+1368 => x"d7a80874",
+1369 => x"2e82de38",
+1370 => x"7784150c",
+1371 => x"80738106",
+1372 => x"56597479",
+1373 => x"2e81d538",
+1374 => x"77148411",
+1375 => x"08810656",
+1376 => x"5374a038",
+1377 => x"77165678",
+1378 => x"81e63888",
+1379 => x"14085574",
+1380 => x"80d7a82e",
+1381 => x"82f9388c",
+1382 => x"1408708c",
+1383 => x"170c7588",
+1384 => x"120c5875",
+1385 => x"81078418",
+1386 => x"0c751776",
+1387 => x"710c5478",
+1388 => x"81913883",
+1389 => x"ff762781",
+1390 => x"c8387589",
+1391 => x"2a76832a",
+1392 => x"54547380",
+1393 => x"2ebf3875",
+1394 => x"862ab805",
+1395 => x"53847427",
+1396 => x"b43880db",
+1397 => x"14539474",
+1398 => x"27ab3875",
+1399 => x"8c2a80ee",
+1400 => x"055380d4",
+1401 => x"74279e38",
+1402 => x"758f2a80",
+1403 => x"f7055382",
+1404 => x"d4742791",
+1405 => x"3875922a",
+1406 => x"80fc0553",
+1407 => x"8ad47427",
+1408 => x"843880fe",
+1409 => x"53721010",
+1410 => x"1080d7a0",
+1411 => x"05881108",
+1412 => x"55557375",
+1413 => x"2e82bf38",
+1414 => x"841408fc",
+1415 => x"06597579",
+1416 => x"278d3888",
+1417 => x"14085473",
+1418 => x"752e0981",
+1419 => x"06ea388c",
+1420 => x"1408708c",
+1421 => x"190c7488",
+1422 => x"190c7788",
+1423 => x"120c5576",
+1424 => x"8c150c79",
+1425 => x"5194d63f",
+1426 => x"8b3d0d04",
+1427 => x"76087771",
+1428 => x"31587605",
+1429 => x"88180856",
+1430 => x"567480d7",
+1431 => x"a82e80e0",
+1432 => x"388c1708",
+1433 => x"708c170c",
+1434 => x"7588120c",
+1435 => x"53fe8939",
+1436 => x"8814088c",
+1437 => x"1508708c",
+1438 => x"130c5988",
+1439 => x"190cfea3",
+1440 => x"3975832a",
+1441 => x"70545480",
+1442 => x"74248198",
+1443 => x"3872822c",
+1444 => x"81712b80",
+1445 => x"d7a40807",
+1446 => x"80d7a00b",
+1447 => x"84050c74",
+1448 => x"10101080",
+1449 => x"d7a00588",
+1450 => x"1108718c",
+1451 => x"1b0c7088",
+1452 => x"1b0c7988",
+1453 => x"130c565a",
+1454 => x"55768c15",
+1455 => x"0cff8439",
+1456 => x"8159fdb4",
+1457 => x"39771673",
+1458 => x"81065455",
+1459 => x"72983876",
+1460 => x"08777131",
+1461 => x"5875058c",
+1462 => x"18088819",
+1463 => x"08718c12",
+1464 => x"0c88120c",
+1465 => x"55557481",
+1466 => x"0784180c",
+1467 => x"7680d7a0",
+1468 => x"0b88050c",
+1469 => x"80d79c08",
+1470 => x"7526fec7",
+1471 => x"3880d798",
+1472 => x"08527951",
+1473 => x"fafd3f79",
+1474 => x"5193923f",
+1475 => x"feba3981",
+1476 => x"778c170c",
+1477 => x"7788170c",
+1478 => x"758c190c",
+1479 => x"7588190c",
+1480 => x"59fd8039",
+1481 => x"83147082",
+1482 => x"2c81712b",
+1483 => x"80d7a408",
+1484 => x"0780d7a0",
+1485 => x"0b84050c",
+1486 => x"75101010",
+1487 => x"80d7a005",
+1488 => x"88110871",
+1489 => x"8c1c0c70",
+1490 => x"881c0c7a",
+1491 => x"88130c57",
+1492 => x"5b5653fe",
+1493 => x"e4398073",
+1494 => x"24a33872",
+1495 => x"822c8171",
+1496 => x"2b80d7a4",
+1497 => x"080780d7",
+1498 => x"a00b8405",
+1499 => x"0c58748c",
+1500 => x"180c7388",
+1501 => x"180c7688",
+1502 => x"160cfdc3",
+1503 => x"39831370",
+1504 => x"822c8171",
+1505 => x"2b80d7a4",
+1506 => x"080780d7",
+1507 => x"a00b8405",
+1508 => x"0c5953da",
+1509 => x"39f93d0d",
+1510 => x"797b5853",
+1511 => x"800b80cf",
+1512 => x"e4085356",
+1513 => x"72722ebc",
+1514 => x"3884dc13",
+1515 => x"5574762e",
+1516 => x"b3388815",
+1517 => x"08841608",
+1518 => x"ff055454",
+1519 => x"80732499",
+1520 => x"388c1422",
+1521 => x"70902b53",
+1522 => x"587180d4",
+1523 => x"3880dc14",
+1524 => x"ff145454",
+1525 => x"728025e9",
+1526 => x"38740855",
+1527 => x"74d43880",
+1528 => x"cfe40852",
+1529 => x"84dc1255",
+1530 => x"74802ead",
+1531 => x"38881508",
+1532 => x"841608ff",
+1533 => x"05545480",
+1534 => x"73249838",
+1535 => x"8c142270",
+1536 => x"902b5358",
+1537 => x"71ad3880",
+1538 => x"dc14ff14",
+1539 => x"54547280",
+1540 => x"25ea3874",
+1541 => x"085574d5",
+1542 => x"3875800c",
+1543 => x"893d0d04",
+1544 => x"7351762d",
+1545 => x"75800807",
+1546 => x"80dc15ff",
+1547 => x"15555556",
+1548 => x"ffa23973",
+1549 => x"51762d75",
+1550 => x"80080780",
+1551 => x"dc15ff15",
+1552 => x"555556ca",
+1553 => x"39ea3d0d",
+1554 => x"688c1122",
+1555 => x"700a100a",
+1556 => x"81065758",
+1557 => x"567480e4",
+1558 => x"388e1622",
+1559 => x"70902b70",
+1560 => x"902c5155",
+1561 => x"58807424",
+1562 => x"b138983d",
+1563 => x"c4055373",
+1564 => x"5280cfe4",
+1565 => x"08519481",
+1566 => x"3f800b80",
+1567 => x"08249738",
+1568 => x"7983e080",
+1569 => x"06547380",
+1570 => x"c0802e81",
+1571 => x"8f387382",
+1572 => x"80802e81",
+1573 => x"91388c16",
+1574 => x"22577690",
+1575 => x"80075473",
+1576 => x"8c172388",
+1577 => x"805280cf",
+1578 => x"e4085181",
+1579 => x"9b3f8008",
+1580 => x"9d388c16",
+1581 => x"22820755",
+1582 => x"748c1723",
+1583 => x"80c31670",
+1584 => x"770c9017",
+1585 => x"0c810b94",
+1586 => x"170c983d",
+1587 => x"0d0480cf",
+1588 => x"e408a8e6",
+1589 => x"0bbc120c",
+1590 => x"588c1622",
+1591 => x"81800754",
+1592 => x"738c1723",
+1593 => x"8008760c",
+1594 => x"80089017",
+1595 => x"0c88800b",
+1596 => x"94170c74",
+1597 => x"802ed338",
+1598 => x"8e162270",
+1599 => x"902b7090",
+1600 => x"2c535654",
+1601 => x"9afe3f80",
+1602 => x"08802eff",
+1603 => x"bd388c16",
+1604 => x"22810757",
+1605 => x"768c1723",
+1606 => x"983d0d04",
+1607 => x"810b8c17",
+1608 => x"225855fe",
+1609 => x"f539a816",
+1610 => x"0880c39d",
+1611 => x"2e098106",
+1612 => x"fee4388c",
+1613 => x"16228880",
+1614 => x"0754738c",
+1615 => x"17238880",
+1616 => x"0b80cc17",
+1617 => x"0cfedc39",
+1618 => x"f43d0d7e",
+1619 => x"608b1170",
+1620 => x"f8065b55",
+1621 => x"555d7296",
+1622 => x"26833890",
+1623 => x"58807824",
+1624 => x"74792607",
+1625 => x"55805474",
+1626 => x"742e0981",
+1627 => x"0680ca38",
+1628 => x"7c518ea8",
+1629 => x"3f7783f7",
+1630 => x"2680c538",
+1631 => x"77832a70",
+1632 => x"10101080",
+1633 => x"d7a0058c",
+1634 => x"11085858",
+1635 => x"5475772e",
+1636 => x"81f03884",
+1637 => x"1608fc06",
+1638 => x"8c170888",
+1639 => x"1808718c",
+1640 => x"120c8812",
+1641 => x"0c5b7605",
+1642 => x"84110881",
+1643 => x"0784120c",
+1644 => x"537c518d",
+1645 => x"e83f8816",
+1646 => x"5473800c",
+1647 => x"8e3d0d04",
+1648 => x"77892a78",
+1649 => x"832a5854",
+1650 => x"73802ebf",
+1651 => x"3877862a",
+1652 => x"b8055784",
+1653 => x"7427b438",
+1654 => x"80db1457",
+1655 => x"947427ab",
+1656 => x"38778c2a",
+1657 => x"80ee0557",
+1658 => x"80d47427",
+1659 => x"9e38778f",
+1660 => x"2a80f705",
+1661 => x"5782d474",
+1662 => x"27913877",
+1663 => x"922a80fc",
+1664 => x"05578ad4",
+1665 => x"74278438",
+1666 => x"80fe5776",
+1667 => x"10101080",
+1668 => x"d7a0058c",
+1669 => x"11085653",
+1670 => x"74732ea3",
+1671 => x"38841508",
+1672 => x"fc067079",
+1673 => x"31555673",
+1674 => x"8f2488e4",
+1675 => x"38738025",
+1676 => x"88e6388c",
+1677 => x"15085574",
+1678 => x"732e0981",
+1679 => x"06df3881",
+1680 => x"175980d7",
+1681 => x"b0085675",
+1682 => x"80d7a82e",
+1683 => x"82cc3884",
+1684 => x"1608fc06",
+1685 => x"70793155",
+1686 => x"55738f24",
+1687 => x"bb3880d7",
+1688 => x"a80b80d7",
+1689 => x"b40c80d7",
+1690 => x"a80b80d7",
+1691 => x"b00c8074",
+1692 => x"2480db38",
+1693 => x"74168411",
+1694 => x"08810784",
+1695 => x"120c53fe",
+1696 => x"b0398816",
+1697 => x"8c110857",
+1698 => x"5975792e",
+1699 => x"098106fe",
+1700 => x"82388214",
+1701 => x"59ffab39",
+1702 => x"77167881",
+1703 => x"0784180c",
+1704 => x"7080d7b4",
+1705 => x"0c7080d7",
+1706 => x"b00c80d7",
+1707 => x"a80b8c12",
+1708 => x"0c8c1108",
+1709 => x"88120c74",
+1710 => x"81078412",
+1711 => x"0c740574",
+1712 => x"710c5b7c",
+1713 => x"518bd63f",
+1714 => x"881654fd",
+1715 => x"ec3983ff",
+1716 => x"75278391",
+1717 => x"3874892a",
+1718 => x"75832a54",
+1719 => x"5473802e",
+1720 => x"bf387486",
+1721 => x"2ab80553",
+1722 => x"847427b4",
+1723 => x"3880db14",
+1724 => x"53947427",
+1725 => x"ab38748c",
+1726 => x"2a80ee05",
+1727 => x"5380d474",
+1728 => x"279e3874",
+1729 => x"8f2a80f7",
+1730 => x"055382d4",
+1731 => x"74279138",
+1732 => x"74922a80",
+1733 => x"fc05538a",
+1734 => x"d4742784",
+1735 => x"3880fe53",
+1736 => x"72101010",
+1737 => x"80d7a005",
+1738 => x"88110855",
+1739 => x"5773772e",
+1740 => x"868b3884",
+1741 => x"1408fc06",
+1742 => x"5b747b27",
+1743 => x"8d388814",
+1744 => x"08547377",
+1745 => x"2e098106",
+1746 => x"ea388c14",
+1747 => x"0880d7a0",
+1748 => x"0b840508",
+1749 => x"718c190c",
+1750 => x"7588190c",
+1751 => x"7788130c",
+1752 => x"5c57758c",
+1753 => x"150c7853",
+1754 => x"80792483",
+1755 => x"98387282",
+1756 => x"2c81712b",
+1757 => x"5656747b",
+1758 => x"2680ca38",
+1759 => x"7a750657",
+1760 => x"7682a338",
+1761 => x"78fc0684",
+1762 => x"05597410",
+1763 => x"707c0655",
+1764 => x"55738292",
+1765 => x"38841959",
+1766 => x"f13980d7",
+1767 => x"a00b8405",
+1768 => x"0879545b",
+1769 => x"788025c6",
+1770 => x"3882da39",
+1771 => x"74097b06",
+1772 => x"7080d7a0",
+1773 => x"0b84050c",
+1774 => x"5b741055",
+1775 => x"747b2685",
+1776 => x"387485bc",
+1777 => x"3880d7a0",
+1778 => x"0b880508",
+1779 => x"70841208",
+1780 => x"fc06707b",
+1781 => x"317b7226",
+1782 => x"8f722507",
+1783 => x"5d575c5c",
+1784 => x"5578802e",
+1785 => x"80d93879",
+1786 => x"1580d798",
+1787 => x"08199011",
+1788 => x"59545680",
+1789 => x"d79408ff",
+1790 => x"2e8838a0",
+1791 => x"8f13e080",
+1792 => x"06577652",
+1793 => x"7c518996",
+1794 => x"3f800854",
+1795 => x"8008ff2e",
+1796 => x"90388008",
+1797 => x"762782a7",
+1798 => x"387480d7",
+1799 => x"a02e829f",
+1800 => x"3880d7a0",
+1801 => x"0b880508",
+1802 => x"55841508",
+1803 => x"fc067079",
+1804 => x"31797226",
+1805 => x"8f722507",
+1806 => x"5d555a7a",
+1807 => x"83f23877",
+1808 => x"81078416",
+1809 => x"0c771570",
+1810 => x"80d7a00b",
+1811 => x"88050c74",
+1812 => x"81078412",
+1813 => x"0c567c51",
+1814 => x"88c33f88",
+1815 => x"15547380",
+1816 => x"0c8e3d0d",
+1817 => x"0474832a",
+1818 => x"70545480",
+1819 => x"7424819b",
+1820 => x"3872822c",
+1821 => x"81712b80",
+1822 => x"d7a40807",
+1823 => x"7080d7a0",
+1824 => x"0b84050c",
+1825 => x"75101010",
+1826 => x"80d7a005",
+1827 => x"88110871",
+1828 => x"8c1b0c70",
+1829 => x"881b0c79",
+1830 => x"88130c57",
+1831 => x"555c5575",
+1832 => x"8c150cfd",
+1833 => x"c1397879",
+1834 => x"10101080",
+1835 => x"d7a00570",
+1836 => x"565b5c8c",
+1837 => x"14085675",
+1838 => x"742ea338",
+1839 => x"841608fc",
+1840 => x"06707931",
+1841 => x"5853768f",
+1842 => x"2483f138",
+1843 => x"76802584",
+1844 => x"af388c16",
+1845 => x"08567574",
+1846 => x"2e098106",
+1847 => x"df388814",
+1848 => x"811a7083",
+1849 => x"06555a54",
+1850 => x"72c9387b",
+1851 => x"83065675",
+1852 => x"802efdb8",
+1853 => x"38ff1cf8",
+1854 => x"1b5b5c88",
+1855 => x"1a087a2e",
+1856 => x"ea38fdb5",
+1857 => x"39831953",
+1858 => x"fce43983",
+1859 => x"1470822c",
+1860 => x"81712b80",
+1861 => x"d7a40807",
+1862 => x"7080d7a0",
+1863 => x"0b84050c",
+1864 => x"76101010",
+1865 => x"80d7a005",
+1866 => x"88110871",
+1867 => x"8c1c0c70",
+1868 => x"881c0c7a",
+1869 => x"88130c58",
+1870 => x"535d5653",
+1871 => x"fee13980",
+1872 => x"d6e40817",
+1873 => x"59800876",
+1874 => x"2e818b38",
+1875 => x"80d79408",
+1876 => x"ff2e848e",
+1877 => x"38737631",
+1878 => x"1980d6e4",
+1879 => x"0c738706",
+1880 => x"70565372",
+1881 => x"802e8838",
+1882 => x"88733170",
+1883 => x"15555576",
+1884 => x"149fff06",
+1885 => x"a0807131",
+1886 => x"1670547e",
+1887 => x"53515386",
+1888 => x"9d3f8008",
+1889 => x"568008ff",
+1890 => x"2e819e38",
+1891 => x"80d6e408",
+1892 => x"137080d6",
+1893 => x"e40c7475",
+1894 => x"80d7a00b",
+1895 => x"88050c77",
+1896 => x"76311581",
+1897 => x"07555659",
+1898 => x"7a80d7a0",
+1899 => x"2e83c038",
+1900 => x"798f2682",
+1901 => x"ef38810b",
+1902 => x"84150c84",
+1903 => x"1508fc06",
+1904 => x"70793179",
+1905 => x"72268f72",
+1906 => x"25075d55",
+1907 => x"5a7a802e",
+1908 => x"fced3880",
+1909 => x"db398008",
+1910 => x"9fff0655",
+1911 => x"74feed38",
+1912 => x"7880d6e4",
+1913 => x"0c80d7a0",
+1914 => x"0b880508",
+1915 => x"7a188107",
+1916 => x"84120c55",
+1917 => x"80d79008",
+1918 => x"79278638",
+1919 => x"7880d790",
+1920 => x"0c80d78c",
+1921 => x"087927fc",
+1922 => x"a0387880",
+1923 => x"d78c0c84",
+1924 => x"1508fc06",
+1925 => x"70793179",
+1926 => x"72268f72",
+1927 => x"25075d55",
+1928 => x"5a7a802e",
+1929 => x"fc993888",
+1930 => x"39807457",
+1931 => x"53fedd39",
+1932 => x"7c5184e9",
+1933 => x"3f800b80",
+1934 => x"0c8e3d0d",
+1935 => x"04807324",
+1936 => x"a5387282",
+1937 => x"2c81712b",
+1938 => x"80d7a408",
+1939 => x"077080d7",
+1940 => x"a00b8405",
+1941 => x"0c5c5a76",
+1942 => x"8c170c73",
+1943 => x"88170c75",
+1944 => x"88180cf9",
+1945 => x"fd398313",
+1946 => x"70822c81",
+1947 => x"712b80d7",
+1948 => x"a4080770",
+1949 => x"80d7a00b",
+1950 => x"84050c5d",
+1951 => x"5b53d839",
+1952 => x"7a75065c",
+1953 => x"7bfc9f38",
+1954 => x"84197510",
+1955 => x"5659f139",
+1956 => x"ff178105",
+1957 => x"59f7ab39",
+1958 => x"8c150888",
+1959 => x"1608718c",
+1960 => x"120c8812",
+1961 => x"0c597515",
+1962 => x"84110881",
+1963 => x"0784120c",
+1964 => x"587c5183",
+1965 => x"e83f8815",
+1966 => x"54fba339",
+1967 => x"77167881",
+1968 => x"0784180c",
+1969 => x"8c170888",
+1970 => x"1808718c",
+1971 => x"120c8812",
+1972 => x"0c5c7080",
+1973 => x"d7b40c70",
+1974 => x"80d7b00c",
+1975 => x"80d7a80b",
+1976 => x"8c120c8c",
+1977 => x"11088812",
+1978 => x"0c778107",
+1979 => x"84120c77",
+1980 => x"0577710c",
+1981 => x"557c5183",
+1982 => x"a43f8816",
+1983 => x"54f5ba39",
+1984 => x"72168411",
+1985 => x"08810784",
+1986 => x"120c588c",
+1987 => x"16088817",
+1988 => x"08718c12",
+1989 => x"0c88120c",
+1990 => x"577c5183",
+1991 => x"803f8816",
+1992 => x"54f59639",
+1993 => x"7284150c",
+1994 => x"f41af806",
+1995 => x"70841d08",
+1996 => x"81060784",
+1997 => x"1d0c701c",
+1998 => x"5556850b",
+1999 => x"84150c85",
+2000 => x"0b88150c",
+2001 => x"8f7627fd",
+2002 => x"ab38881b",
+2003 => x"527c51eb",
+2004 => x"e83f80d7",
+2005 => x"a00b8805",
+2006 => x"0880d6e4",
+2007 => x"085a55fd",
+2008 => x"93397880",
+2009 => x"d6e40c73",
+2010 => x"80d7940c",
+2011 => x"fbef3972",
+2012 => x"84150cfc",
+2013 => x"ff39fb3d",
+2014 => x"0d77707a",
+2015 => x"7c585553",
+2016 => x"568f7527",
+2017 => x"80e63872",
+2018 => x"76078306",
+2019 => x"517080dc",
+2020 => x"38757352",
+2021 => x"54707084",
+2022 => x"05520874",
+2023 => x"70840556",
+2024 => x"0c737170",
+2025 => x"84055308",
+2026 => x"71708405",
+2027 => x"530c7170",
+2028 => x"84055308",
+2029 => x"71708405",
+2030 => x"530c7170",
+2031 => x"84055308",
+2032 => x"71708405",
+2033 => x"530cf016",
+2034 => x"5654748f",
+2035 => x"26c73883",
+2036 => x"75279538",
+2037 => x"70708405",
+2038 => x"52087470",
+2039 => x"8405560c",
+2040 => x"fc155574",
+2041 => x"8326ed38",
+2042 => x"73715452",
+2043 => x"ff155170",
+2044 => x"ff2e9838",
+2045 => x"72708105",
+2046 => x"54337270",
+2047 => x"81055434",
+2048 => x"ff115170",
+2049 => x"ff2e0981",
+2050 => x"06ea3875",
+2051 => x"800c873d",
+2052 => x"0d04fb3d",
+2053 => x"0d777a71",
+2054 => x"028c05a3",
+2055 => x"05335854",
+2056 => x"54568373",
+2057 => x"2780d438",
+2058 => x"75830651",
+2059 => x"7080cc38",
+2060 => x"74882b75",
+2061 => x"07707190",
+2062 => x"2b075551",
+2063 => x"8f7327a7",
+2064 => x"38737270",
+2065 => x"8405540c",
+2066 => x"71747170",
+2067 => x"8405530c",
+2068 => x"74717084",
+2069 => x"05530c74",
+2070 => x"71708405",
+2071 => x"530cf014",
+2072 => x"5452728f",
+2073 => x"26db3883",
+2074 => x"73279038",
+2075 => x"73727084",
+2076 => x"05540cfc",
+2077 => x"13537283",
+2078 => x"26f238ff",
+2079 => x"135170ff",
+2080 => x"2e933874",
+2081 => x"72708105",
+2082 => x"5434ff11",
+2083 => x"5170ff2e",
+2084 => x"098106ef",
+2085 => x"3875800c",
+2086 => x"873d0d04",
+2087 => x"04047070",
+2088 => x"7070800b",
+2089 => x"80dfe00c",
+2090 => x"765184f3",
+2091 => x"3f800853",
+2092 => x"8008ff2e",
+2093 => x"89387280",
+2094 => x"0c505050",
+2095 => x"500480df",
+2096 => x"e0085473",
+2097 => x"802eef38",
+2098 => x"7574710c",
+2099 => x"5272800c",
+2100 => x"50505050",
+2101 => x"04f93d0d",
+2102 => x"797c557b",
+2103 => x"548e1122",
+2104 => x"70902b70",
+2105 => x"902c5557",
+2106 => x"80cfe408",
+2107 => x"53585683",
+2108 => x"f63f8008",
+2109 => x"57800b80",
+2110 => x"08249338",
+2111 => x"80d01608",
+2112 => x"80080580",
+2113 => x"d0170c76",
+2114 => x"800c893d",
+2115 => x"0d048c16",
+2116 => x"2283dfff",
+2117 => x"0655748c",
+2118 => x"17237680",
+2119 => x"0c893d0d",
+2120 => x"04fa3d0d",
+2121 => x"788c1122",
+2122 => x"70882a70",
+2123 => x"81065157",
+2124 => x"585674a9",
+2125 => x"388c1622",
+2126 => x"83dfff06",
+2127 => x"55748c17",
+2128 => x"237a5479",
+2129 => x"538e1622",
+2130 => x"70902b70",
+2131 => x"902c5456",
+2132 => x"80cfe408",
+2133 => x"525681b2",
+2134 => x"3f883d0d",
+2135 => x"04825480",
+2136 => x"538e1622",
+2137 => x"70902b70",
+2138 => x"902c5456",
+2139 => x"80cfe408",
+2140 => x"525782bb",
+2141 => x"3f8c1622",
+2142 => x"83dfff06",
+2143 => x"55748c17",
+2144 => x"237a5479",
+2145 => x"538e1622",
+2146 => x"70902b70",
+2147 => x"902c5456",
+2148 => x"80cfe408",
+2149 => x"525680f2",
+2150 => x"3f883d0d",
+2151 => x"04f93d0d",
+2152 => x"797c557b",
+2153 => x"548e1122",
+2154 => x"70902b70",
+2155 => x"902c5557",
+2156 => x"80cfe408",
+2157 => x"53585681",
+2158 => x"f63f8008",
+2159 => x"578008ff",
+2160 => x"2e99388c",
+2161 => x"1622a080",
+2162 => x"0755748c",
+2163 => x"17238008",
+2164 => x"80d0170c",
+2165 => x"76800c89",
+2166 => x"3d0d048c",
+2167 => x"162283df",
+2168 => x"ff065574",
+2169 => x"8c172376",
+2170 => x"800c893d",
+2171 => x"0d047070",
+2172 => x"70748e11",
+2173 => x"2270902b",
+2174 => x"70902c55",
+2175 => x"51515380",
+2176 => x"cfe40851",
+2177 => x"bd3f5050",
+2178 => x"5004fb3d",
+2179 => x"0d800b80",
+2180 => x"dfe00c7a",
+2181 => x"53795278",
+2182 => x"5182ff3f",
+2183 => x"80085580",
+2184 => x"08ff2e88",
+2185 => x"3874800c",
+2186 => x"873d0d04",
+2187 => x"80dfe008",
+2188 => x"5675802e",
+2189 => x"f0387776",
+2190 => x"710c5474",
+2191 => x"800c873d",
+2192 => x"0d047070",
+2193 => x"7070800b",
+2194 => x"80dfe00c",
+2195 => x"765184cc",
+2196 => x"3f800853",
+2197 => x"8008ff2e",
+2198 => x"89387280",
+2199 => x"0c505050",
+2200 => x"500480df",
+2201 => x"e0085473",
+2202 => x"802eef38",
+2203 => x"7574710c",
+2204 => x"5272800c",
+2205 => x"50505050",
+2206 => x"04fc3d0d",
+2207 => x"800b80df",
+2208 => x"e00c7852",
+2209 => x"775187b3",
+2210 => x"3f800854",
+2211 => x"8008ff2e",
+2212 => x"88387380",
+2213 => x"0c863d0d",
+2214 => x"0480dfe0",
+2215 => x"08557480",
+2216 => x"2ef03876",
+2217 => x"75710c53",
+2218 => x"73800c86",
+2219 => x"3d0d04fb",
+2220 => x"3d0d800b",
+2221 => x"80dfe00c",
+2222 => x"7a537952",
+2223 => x"7851848e",
+2224 => x"3f800855",
+2225 => x"8008ff2e",
+2226 => x"88387480",
+2227 => x"0c873d0d",
+2228 => x"0480dfe0",
+2229 => x"08567580",
+2230 => x"2ef03877",
+2231 => x"76710c54",
+2232 => x"74800c87",
+2233 => x"3d0d04fb",
+2234 => x"3d0d800b",
+2235 => x"80dfe00c",
+2236 => x"7a537952",
+2237 => x"78518296",
+2238 => x"3f800855",
+2239 => x"8008ff2e",
+2240 => x"88387480",
+2241 => x"0c873d0d",
+2242 => x"0480dfe0",
+2243 => x"08567580",
+2244 => x"2ef03877",
+2245 => x"76710c54",
+2246 => x"74800c87",
+2247 => x"3d0d0470",
+2248 => x"707080df",
+2249 => x"d0088938",
+2250 => x"80dfe40b",
+2251 => x"80dfd00c",
+2252 => x"80dfd008",
+2253 => x"75115252",
+2254 => x"ff537087",
+2255 => x"fb808026",
+2256 => x"88387080",
+2257 => x"dfd00c71",
+2258 => x"5372800c",
+2259 => x"50505004",
+2260 => x"fd3d0d80",
+2261 => x"0b80cfd8",
+2262 => x"08545472",
+2263 => x"812e9b38",
+2264 => x"7380dfd4",
+2265 => x"0cc2bf3f",
+2266 => x"c1963f80",
+2267 => x"dfa85281",
+2268 => x"51c3fd3f",
+2269 => x"80085186",
+2270 => x"c23f7280",
+2271 => x"dfd40cc2",
+2272 => x"a53fc0fc",
+2273 => x"3f80dfa8",
+2274 => x"528151c3",
+2275 => x"e33f8008",
+2276 => x"5186a83f",
+2277 => x"00ff3900",
+2278 => x"ff39f53d",
+2279 => x"0d7e6080",
+2280 => x"dfd40870",
+2281 => x"5b585b5b",
+2282 => x"7580c238",
+2283 => x"777a25a1",
+2284 => x"38771b70",
+2285 => x"337081ff",
+2286 => x"06585859",
+2287 => x"758a2e98",
+2288 => x"387681ff",
+2289 => x"0651c1bd",
+2290 => x"3f811858",
+2291 => x"797824e1",
+2292 => x"3879800c",
+2293 => x"8d3d0d04",
+2294 => x"8d51c1a9",
+2295 => x"3f783370",
+2296 => x"81ff0652",
+2297 => x"57c19e3f",
+2298 => x"811858e0",
+2299 => x"3979557a",
+2300 => x"547d5385",
+2301 => x"528d3dfc",
+2302 => x"0551c0c6",
+2303 => x"3f800856",
+2304 => x"85b23f7b",
+2305 => x"80080c75",
+2306 => x"800c8d3d",
+2307 => x"0d04f63d",
+2308 => x"0d7d7f80",
+2309 => x"dfd40870",
+2310 => x"5b585a5a",
+2311 => x"7580c138",
+2312 => x"777925b3",
+2313 => x"38c0b93f",
+2314 => x"800881ff",
+2315 => x"06708d32",
+2316 => x"7030709f",
+2317 => x"2a515157",
+2318 => x"57768a2e",
+2319 => x"80c43875",
+2320 => x"802ebf38",
+2321 => x"771a5676",
+2322 => x"76347651",
+2323 => x"c0b73f81",
+2324 => x"18587878",
+2325 => x"24cf3877",
+2326 => x"5675800c",
+2327 => x"8c3d0d04",
+2328 => x"78557954",
+2329 => x"7c538452",
+2330 => x"8c3dfc05",
+2331 => x"51ffbfd2",
+2332 => x"3f800856",
+2333 => x"84be3f7a",
+2334 => x"80080c75",
+2335 => x"800c8c3d",
+2336 => x"0d04771a",
+2337 => x"598a7934",
+2338 => x"8118588d",
+2339 => x"51ffbff5",
+2340 => x"3f8a51ff",
+2341 => x"bfef3f77",
+2342 => x"56ffbe39",
+2343 => x"fb3d0d80",
+2344 => x"dfd40870",
+2345 => x"56547388",
+2346 => x"3874800c",
+2347 => x"873d0d04",
+2348 => x"77538352",
+2349 => x"873dfc05",
+2350 => x"51ffbf86",
+2351 => x"3f800854",
+2352 => x"83f23f75",
+2353 => x"80080c73",
+2354 => x"800c873d",
+2355 => x"0d04fa3d",
+2356 => x"0d80dfd4",
+2357 => x"08802ea3",
+2358 => x"387a5579",
+2359 => x"54785386",
+2360 => x"52883dfc",
+2361 => x"0551ffbe",
+2362 => x"d93f8008",
+2363 => x"5683c53f",
+2364 => x"7680080c",
+2365 => x"75800c88",
+2366 => x"3d0d0483",
+2367 => x"b73f9d0b",
+2368 => x"80080cff",
+2369 => x"0b800c88",
+2370 => x"3d0d04f7",
+2371 => x"3d0d7b7d",
+2372 => x"5b59bc53",
+2373 => x"80527951",
+2374 => x"f5f83f80",
+2375 => x"70565798",
+2376 => x"56741970",
+2377 => x"3370782b",
+2378 => x"79078118",
+2379 => x"f81a5a58",
+2380 => x"59555884",
+2381 => x"7524ea38",
+2382 => x"767a2384",
+2383 => x"19588070",
+2384 => x"56579856",
+2385 => x"74187033",
+2386 => x"70782b79",
+2387 => x"078118f8",
+2388 => x"1a5a5859",
+2389 => x"51548475",
+2390 => x"24ea3876",
+2391 => x"821b2388",
+2392 => x"19588070",
+2393 => x"56579856",
+2394 => x"74187033",
+2395 => x"70782b79",
+2396 => x"078118f8",
+2397 => x"1a5a5859",
+2398 => x"51548475",
+2399 => x"24ea3876",
+2400 => x"841b0c8c",
+2401 => x"19588070",
+2402 => x"56579856",
+2403 => x"74187033",
+2404 => x"70782b79",
+2405 => x"078118f8",
+2406 => x"1a5a5859",
+2407 => x"51548475",
+2408 => x"24ea3876",
+2409 => x"881b2390",
+2410 => x"19588070",
+2411 => x"56579856",
+2412 => x"74187033",
+2413 => x"70782b79",
+2414 => x"078118f8",
+2415 => x"1a5a5859",
+2416 => x"51548475",
+2417 => x"24ea3876",
+2418 => x"8a1b2394",
+2419 => x"19588070",
+2420 => x"56579856",
+2421 => x"74187033",
+2422 => x"70782b79",
+2423 => x"078118f8",
+2424 => x"1a5a5859",
+2425 => x"51548475",
+2426 => x"24ea3876",
+2427 => x"8c1b2398",
+2428 => x"19588070",
+2429 => x"56579856",
+2430 => x"74187033",
+2431 => x"70782b79",
+2432 => x"078118f8",
+2433 => x"1a5a5859",
+2434 => x"51548475",
+2435 => x"24ea3876",
+2436 => x"8e1b239c",
+2437 => x"19588070",
+2438 => x"5657b856",
+2439 => x"74187033",
+2440 => x"70782b79",
+2441 => x"078118f8",
+2442 => x"1a5a5859",
+2443 => x"5a548875",
+2444 => x"24ea3876",
+2445 => x"901b0c8b",
+2446 => x"3d0d04e9",
+2447 => x"3d0d6a80",
+2448 => x"dfd40857",
+2449 => x"57759338",
+2450 => x"80c0800b",
+2451 => x"84180c75",
+2452 => x"ac180c75",
+2453 => x"800c993d",
+2454 => x"0d04893d",
+2455 => x"70556a54",
+2456 => x"558a5299",
+2457 => x"3dffbc05",
+2458 => x"51ffbbd6",
+2459 => x"3f800877",
+2460 => x"53755256",
+2461 => x"fd953fbc",
+2462 => x"3f778008",
+2463 => x"0c75800c",
+2464 => x"993d0d04",
+2465 => x"fc3d0d81",
+2466 => x"5480dfd4",
+2467 => x"08883873",
+2468 => x"800c863d",
+2469 => x"0d047653",
+2470 => x"97b95286",
+2471 => x"3dfc0551",
+2472 => x"ffbb9f3f",
+2473 => x"8008548c",
+2474 => x"3f748008",
+2475 => x"0c73800c",
+2476 => x"863d0d04",
+2477 => x"80cfe408",
+2478 => x"800c04f7",
+2479 => x"3d0d7b80",
+2480 => x"cfe40882",
+2481 => x"c811085a",
+2482 => x"545a7780",
+2483 => x"2e80da38",
+2484 => x"81881884",
+2485 => x"1908ff05",
+2486 => x"81712b59",
+2487 => x"55598074",
+2488 => x"2480ea38",
+2489 => x"807424b5",
+2490 => x"3873822b",
+2491 => x"78118805",
+2492 => x"56568180",
+2493 => x"19087706",
+2494 => x"5372802e",
+2495 => x"b6387816",
+2496 => x"70085353",
+2497 => x"79517408",
+2498 => x"53722dff",
+2499 => x"14fc17fc",
+2500 => x"1779812c",
+2501 => x"5a575754",
+2502 => x"738025d6",
+2503 => x"38770858",
+2504 => x"77ffad38",
+2505 => x"80cfe408",
+2506 => x"53bc1308",
+2507 => x"a5387951",
+2508 => x"f8e23f74",
+2509 => x"0853722d",
+2510 => x"ff14fc17",
+2511 => x"fc177981",
+2512 => x"2c5a5757",
+2513 => x"54738025",
+2514 => x"ffa838d1",
+2515 => x"398057ff",
+2516 => x"93397251",
+2517 => x"bc130854",
+2518 => x"732d7951",
+2519 => x"f8b63f70",
+2520 => x"7080dfb0",
+2521 => x"0bfc0570",
+2522 => x"08525270",
+2523 => x"ff2e9138",
+2524 => x"702dfc12",
+2525 => x"70085252",
+2526 => x"70ff2e09",
+2527 => x"8106f138",
+2528 => x"50500404",
+2529 => x"ffbb8c3f",
+2530 => x"04000000",
+2531 => x"00000040",
+2532 => x"48656c6c",
+2533 => x"6f20776f",
+2534 => x"726c6420",
+2535 => x"310a0000",
+2536 => x"48656c6c",
+2537 => x"6f20776f",
+2538 => x"726c6420",
+2539 => x"320a0000",
+2540 => x"0a000000",
+2541 => x"43000000",
+2542 => x"64756d6d",
+2543 => x"792e6578",
+2544 => x"65000000",
+2545 => x"00ffffff",
+2546 => x"ff00ffff",
+2547 => x"ffff00ff",
+2548 => x"ffffff00",
+2549 => x"00000000",
+2550 => x"00000000",
+2551 => x"00000000",
+2552 => x"00002fb8",
+2553 => x"000027e8",
+2554 => x"00000000",
+2555 => x"00002a50",
+2556 => x"00002aac",
+2557 => x"00002b08",
+2558 => x"00000000",
+2559 => x"00000000",
+2560 => x"00000000",
+2561 => x"00000000",
+2562 => x"00000000",
+2563 => x"00000000",
+2564 => x"00000000",
+2565 => x"00000000",
+2566 => x"00000000",
+2567 => x"000027b4",
+2568 => x"00000000",
+2569 => x"00000000",
+2570 => x"00000000",
+2571 => x"00000000",
+2572 => x"00000000",
+2573 => x"00000000",
+2574 => x"00000000",
+2575 => x"00000000",
+2576 => x"00000000",
+2577 => x"00000000",
+2578 => x"00000000",
+2579 => x"00000000",
+2580 => x"00000000",
+2581 => x"00000000",
+2582 => x"00000000",
+2583 => x"00000000",
+2584 => x"00000000",
+2585 => x"00000000",
+2586 => x"00000000",
+2587 => x"00000000",
+2588 => x"00000000",
+2589 => x"00000000",
+2590 => x"00000000",
+2591 => x"00000000",
+2592 => x"00000000",
+2593 => x"00000000",
+2594 => x"00000000",
+2595 => x"00000000",
+2596 => x"00000001",
+2597 => x"330eabcd",
+2598 => x"1234e66d",
+2599 => x"deec0005",
+2600 => x"000b0000",
+2601 => x"00000000",
+2602 => x"00000000",
+2603 => x"00000000",
+2604 => x"00000000",
+2605 => x"00000000",
+2606 => x"00000000",
+2607 => x"00000000",
+2608 => x"00000000",
+2609 => x"00000000",
+2610 => x"00000000",
+2611 => x"00000000",
+2612 => x"00000000",
+2613 => x"00000000",
+2614 => x"00000000",
+2615 => x"00000000",
+2616 => x"00000000",
+2617 => x"00000000",
+2618 => x"00000000",
+2619 => x"00000000",
+2620 => x"00000000",
+2621 => x"00000000",
+2622 => x"00000000",
+2623 => x"00000000",
+2624 => x"00000000",
+2625 => x"00000000",
+2626 => x"00000000",
+2627 => x"00000000",
+2628 => x"00000000",
+2629 => x"00000000",
+2630 => x"00000000",
+2631 => x"00000000",
+2632 => x"00000000",
+2633 => x"00000000",
+2634 => x"00000000",
+2635 => x"00000000",
+2636 => x"00000000",
+2637 => x"00000000",
+2638 => x"00000000",
+2639 => x"00000000",
+2640 => x"00000000",
+2641 => x"00000000",
+2642 => x"00000000",
+2643 => x"00000000",
+2644 => x"00000000",
+2645 => x"00000000",
+2646 => x"00000000",
+2647 => x"00000000",
+2648 => x"00000000",
+2649 => x"00000000",
+2650 => x"00000000",
+2651 => x"00000000",
+2652 => x"00000000",
+2653 => x"00000000",
+2654 => x"00000000",
+2655 => x"00000000",
+2656 => x"00000000",
+2657 => x"00000000",
+2658 => x"00000000",
+2659 => x"00000000",
+2660 => x"00000000",
+2661 => x"00000000",
+2662 => x"00000000",
+2663 => x"00000000",
+2664 => x"00000000",
+2665 => x"00000000",
+2666 => x"00000000",
+2667 => x"00000000",
+2668 => x"00000000",
+2669 => x"00000000",
+2670 => x"00000000",
+2671 => x"00000000",
+2672 => x"00000000",
+2673 => x"00000000",
+2674 => x"00000000",
+2675 => x"00000000",
+2676 => x"00000000",
+2677 => x"00000000",
+2678 => x"00000000",
+2679 => x"00000000",
+2680 => x"00000000",
+2681 => x"00000000",
+2682 => x"00000000",
+2683 => x"00000000",
+2684 => x"00000000",
+2685 => x"00000000",
+2686 => x"00000000",
+2687 => x"00000000",
+2688 => x"00000000",
+2689 => x"00000000",
+2690 => x"00000000",
+2691 => x"00000000",
+2692 => x"00000000",
+2693 => x"00000000",
+2694 => x"00000000",
+2695 => x"00000000",
+2696 => x"00000000",
+2697 => x"00000000",
+2698 => x"00000000",
+2699 => x"00000000",
+2700 => x"00000000",
+2701 => x"00000000",
+2702 => x"00000000",
+2703 => x"00000000",
+2704 => x"00000000",
+2705 => x"00000000",
+2706 => x"00000000",
+2707 => x"00000000",
+2708 => x"00000000",
+2709 => x"00000000",
+2710 => x"00000000",
+2711 => x"00000000",
+2712 => x"00000000",
+2713 => x"00000000",
+2714 => x"00000000",
+2715 => x"00000000",
+2716 => x"00000000",
+2717 => x"00000000",
+2718 => x"00000000",
+2719 => x"00000000",
+2720 => x"00000000",
+2721 => x"00000000",
+2722 => x"00000000",
+2723 => x"00000000",
+2724 => x"00000000",
+2725 => x"00000000",
+2726 => x"00000000",
+2727 => x"00000000",
+2728 => x"00000000",
+2729 => x"00000000",
+2730 => x"00000000",
+2731 => x"00000000",
+2732 => x"00000000",
+2733 => x"00000000",
+2734 => x"00000000",
+2735 => x"00000000",
+2736 => x"00000000",
+2737 => x"00000000",
+2738 => x"00000000",
+2739 => x"00000000",
+2740 => x"00000000",
+2741 => x"00000000",
+2742 => x"00000000",
+2743 => x"00000000",
+2744 => x"00000000",
+2745 => x"00000000",
+2746 => x"00000000",
+2747 => x"00000000",
+2748 => x"00000000",
+2749 => x"00000000",
+2750 => x"00000000",
+2751 => x"00000000",
+2752 => x"00000000",
+2753 => x"00000000",
+2754 => x"00000000",
+2755 => x"00000000",
+2756 => x"00000000",
+2757 => x"00000000",
+2758 => x"00000000",
+2759 => x"00000000",
+2760 => x"00000000",
+2761 => x"00000000",
+2762 => x"00000000",
+2763 => x"00000000",
+2764 => x"00000000",
+2765 => x"00000000",
+2766 => x"00000000",
+2767 => x"00000000",
+2768 => x"00000000",
+2769 => x"00000000",
+2770 => x"00000000",
+2771 => x"00000000",
+2772 => x"00000000",
+2773 => x"00000000",
+2774 => x"00000000",
+2775 => x"00000000",
+2776 => x"00000000",
+2777 => x"00000000",
+2778 => x"00000000",
+2779 => x"00000000",
+2780 => x"00000000",
+2781 => x"00000000",
+2782 => x"00000000",
+2783 => x"00000000",
+2784 => x"00000000",
+2785 => x"00000000",
+2786 => x"00000000",
+2787 => x"00000000",
+2788 => x"00000000",
+2789 => x"ffffffff",
+2790 => x"00000000",
+2791 => x"00020000",
+2792 => x"00000000",
+2793 => x"00000000",
+2794 => x"00002ba0",
+2795 => x"00002ba0",
+2796 => x"00002ba8",
+2797 => x"00002ba8",
+2798 => x"00002bb0",
+2799 => x"00002bb0",
+2800 => x"00002bb8",
+2801 => x"00002bb8",
+2802 => x"00002bc0",
+2803 => x"00002bc0",
+2804 => x"00002bc8",
+2805 => x"00002bc8",
+2806 => x"00002bd0",
+2807 => x"00002bd0",
+2808 => x"00002bd8",
+2809 => x"00002bd8",
+2810 => x"00002be0",
+2811 => x"00002be0",
+2812 => x"00002be8",
+2813 => x"00002be8",
+2814 => x"00002bf0",
+2815 => x"00002bf0",
+2816 => x"00002bf8",
+2817 => x"00002bf8",
+2818 => x"00002c00",
+2819 => x"00002c00",
+2820 => x"00002c08",
+2821 => x"00002c08",
+2822 => x"00002c10",
+2823 => x"00002c10",
+2824 => x"00002c18",
+2825 => x"00002c18",
+2826 => x"00002c20",
+2827 => x"00002c20",
+2828 => x"00002c28",
+2829 => x"00002c28",
+2830 => x"00002c30",
+2831 => x"00002c30",
+2832 => x"00002c38",
+2833 => x"00002c38",
+2834 => x"00002c40",
+2835 => x"00002c40",
+2836 => x"00002c48",
+2837 => x"00002c48",
+2838 => x"00002c50",
+2839 => x"00002c50",
+2840 => x"00002c58",
+2841 => x"00002c58",
+2842 => x"00002c60",
+2843 => x"00002c60",
+2844 => x"00002c68",
+2845 => x"00002c68",
+2846 => x"00002c70",
+2847 => x"00002c70",
+2848 => x"00002c78",
+2849 => x"00002c78",
+2850 => x"00002c80",
+2851 => x"00002c80",
+2852 => x"00002c88",
+2853 => x"00002c88",
+2854 => x"00002c90",
+2855 => x"00002c90",
+2856 => x"00002c98",
+2857 => x"00002c98",
+2858 => x"00002ca0",
+2859 => x"00002ca0",
+2860 => x"00002ca8",
+2861 => x"00002ca8",
+2862 => x"00002cb0",
+2863 => x"00002cb0",
+2864 => x"00002cb8",
+2865 => x"00002cb8",
+2866 => x"00002cc0",
+2867 => x"00002cc0",
+2868 => x"00002cc8",
+2869 => x"00002cc8",
+2870 => x"00002cd0",
+2871 => x"00002cd0",
+2872 => x"00002cd8",
+2873 => x"00002cd8",
+2874 => x"00002ce0",
+2875 => x"00002ce0",
+2876 => x"00002ce8",
+2877 => x"00002ce8",
+2878 => x"00002cf0",
+2879 => x"00002cf0",
+2880 => x"00002cf8",
+2881 => x"00002cf8",
+2882 => x"00002d00",
+2883 => x"00002d00",
+2884 => x"00002d08",
+2885 => x"00002d08",
+2886 => x"00002d10",
+2887 => x"00002d10",
+2888 => x"00002d18",
+2889 => x"00002d18",
+2890 => x"00002d20",
+2891 => x"00002d20",
+2892 => x"00002d28",
+2893 => x"00002d28",
+2894 => x"00002d30",
+2895 => x"00002d30",
+2896 => x"00002d38",
+2897 => x"00002d38",
+2898 => x"00002d40",
+2899 => x"00002d40",
+2900 => x"00002d48",
+2901 => x"00002d48",
+2902 => x"00002d50",
+2903 => x"00002d50",
+2904 => x"00002d58",
+2905 => x"00002d58",
+2906 => x"00002d60",
+2907 => x"00002d60",
+2908 => x"00002d68",
+2909 => x"00002d68",
+2910 => x"00002d70",
+2911 => x"00002d70",
+2912 => x"00002d78",
+2913 => x"00002d78",
+2914 => x"00002d80",
+2915 => x"00002d80",
+2916 => x"00002d88",
+2917 => x"00002d88",
+2918 => x"00002d90",
+2919 => x"00002d90",
+2920 => x"00002d98",
+2921 => x"00002d98",
+2922 => x"00002da0",
+2923 => x"00002da0",
+2924 => x"00002da8",
+2925 => x"00002da8",
+2926 => x"00002db0",
+2927 => x"00002db0",
+2928 => x"00002db8",
+2929 => x"00002db8",
+2930 => x"00002dc0",
+2931 => x"00002dc0",
+2932 => x"00002dc8",
+2933 => x"00002dc8",
+2934 => x"00002dd0",
+2935 => x"00002dd0",
+2936 => x"00002dd8",
+2937 => x"00002dd8",
+2938 => x"00002de0",
+2939 => x"00002de0",
+2940 => x"00002de8",
+2941 => x"00002de8",
+2942 => x"00002df0",
+2943 => x"00002df0",
+2944 => x"00002df8",
+2945 => x"00002df8",
+2946 => x"00002e00",
+2947 => x"00002e00",
+2948 => x"00002e08",
+2949 => x"00002e08",
+2950 => x"00002e10",
+2951 => x"00002e10",
+2952 => x"00002e18",
+2953 => x"00002e18",
+2954 => x"00002e20",
+2955 => x"00002e20",
+2956 => x"00002e28",
+2957 => x"00002e28",
+2958 => x"00002e30",
+2959 => x"00002e30",
+2960 => x"00002e38",
+2961 => x"00002e38",
+2962 => x"00002e40",
+2963 => x"00002e40",
+2964 => x"00002e48",
+2965 => x"00002e48",
+2966 => x"00002e50",
+2967 => x"00002e50",
+2968 => x"00002e58",
+2969 => x"00002e58",
+2970 => x"00002e60",
+2971 => x"00002e60",
+2972 => x"00002e68",
+2973 => x"00002e68",
+2974 => x"00002e70",
+2975 => x"00002e70",
+2976 => x"00002e78",
+2977 => x"00002e78",
+2978 => x"00002e80",
+2979 => x"00002e80",
+2980 => x"00002e88",
+2981 => x"00002e88",
+2982 => x"00002e90",
+2983 => x"00002e90",
+2984 => x"00002e98",
+2985 => x"00002e98",
+2986 => x"00002ea0",
+2987 => x"00002ea0",
+2988 => x"00002ea8",
+2989 => x"00002ea8",
+2990 => x"00002eb0",
+2991 => x"00002eb0",
+2992 => x"00002eb8",
+2993 => x"00002eb8",
+2994 => x"00002ec0",
+2995 => x"00002ec0",
+2996 => x"00002ec8",
+2997 => x"00002ec8",
+2998 => x"00002ed0",
+2999 => x"00002ed0",
+3000 => x"00002ed8",
+3001 => x"00002ed8",
+3002 => x"00002ee0",
+3003 => x"00002ee0",
+3004 => x"00002ee8",
+3005 => x"00002ee8",
+3006 => x"00002ef0",
+3007 => x"00002ef0",
+3008 => x"00002ef8",
+3009 => x"00002ef8",
+3010 => x"00002f00",
+3011 => x"00002f00",
+3012 => x"00002f08",
+3013 => x"00002f08",
+3014 => x"00002f10",
+3015 => x"00002f10",
+3016 => x"00002f18",
+3017 => x"00002f18",
+3018 => x"00002f20",
+3019 => x"00002f20",
+3020 => x"00002f28",
+3021 => x"00002f28",
+3022 => x"00002f30",
+3023 => x"00002f30",
+3024 => x"00002f38",
+3025 => x"00002f38",
+3026 => x"00002f40",
+3027 => x"00002f40",
+3028 => x"00002f48",
+3029 => x"00002f48",
+3030 => x"00002f50",
+3031 => x"00002f50",
+3032 => x"00002f58",
+3033 => x"00002f58",
+3034 => x"00002f60",
+3035 => x"00002f60",
+3036 => x"00002f68",
+3037 => x"00002f68",
+3038 => x"00002f70",
+3039 => x"00002f70",
+3040 => x"00002f78",
+3041 => x"00002f78",
+3042 => x"00002f80",
+3043 => x"00002f80",
+3044 => x"00002f88",
+3045 => x"00002f88",
+3046 => x"00002f90",
+3047 => x"00002f90",
+3048 => x"00002f98",
+3049 => x"00002f98",
+3050 => x"000027b8",
+3051 => x"ffffffff",
+3052 => x"00000000",
+3053 => x"ffffffff",
+3054 => x"00000000",
+ others => x"00000000"
+);
+
+begin
+
+process (clk)
+begin
+ if (clk'event and clk = '1') then
+ if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then
+ report "write collision" severity failure;
+ end if;
+
+ if (memAWriteEnable = '1') then
+ ram(to_integer(unsigned(memAAddr))) := memAWrite;
+ memARead <= memAWrite;
+ else
+ memARead <= ram(to_integer(unsigned(memAAddr)));
+ end if;
+ end if;
+end process;
+
+process (clk)
+begin
+ if (clk'event and clk = '1') then
+ if (memBWriteEnable = '1') then
+ ram(to_integer(unsigned(memBAddr))) := memBWrite;
+ memBRead <= memBWrite;
+ else
+ memBRead <= ram(to_integer(unsigned(memBAddr)));
+ end if;
+ end if;
+end process;
+
+
+
+
+end dualport_ram_arch;
diff --git a/zpu/hdl/example/interrupt.vhd b/zpu/hdl/example/interrupt.vhd
new file mode 100644
index 0000000..d2bc709
--- /dev/null
+++ b/zpu/hdl/example/interrupt.vhd
@@ -0,0 +1,3156 @@
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+--
+-- The FreeBSD license
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+--
+-- 1. Redistributions of source code must retain the above copyright
+-- notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+-- copyright notice, this list of conditions and the following
+-- disclaimer in the documentation and/or other materials
+-- provided with the distribution.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity dualport_ram is
+port (clk : in std_logic;
+ memAWriteEnable : in std_logic;
+ memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+ memAWrite : in std_logic_vector(wordSize-1 downto 0);
+ memARead : out std_logic_vector(wordSize-1 downto 0);
+ memBWriteEnable : in std_logic;
+ memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+ memBWrite : in std_logic_vector(wordSize-1 downto 0);
+ memBRead : out std_logic_vector(wordSize-1 downto 0));
+end dualport_ram;
+
+architecture dualport_ram_arch of dualport_ram is
+
+
+type ram_type is array(natural range 0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
+
+shared variable ram : ram_type :=
+(
+0 => x"0b0b0b0b",
+1 => x"82700b0b",
+2 => x"80cfe00c",
+3 => x"3a0b0b80",
+4 => x"c6e00400",
+5 => x"00000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"0b8af02d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
+17 => x"72830609",
+18 => x"81058205",
+19 => x"832b2a83",
+20 => x"ffff0652",
+21 => x"04000000",
+22 => x"00000000",
+23 => x"00000000",
+24 => x"71fd0608",
+25 => x"83ffff73",
+26 => x"83060981",
+27 => x"05820583",
+28 => x"2b2b0906",
+29 => x"7383ffff",
+30 => x"0b0b0b0b",
+31 => x"83a70400",
+32 => x"72098105",
+33 => x"72057373",
+34 => x"09060906",
+35 => x"73097306",
+36 => x"070a8106",
+37 => x"53510400",
+38 => x"00000000",
+39 => x"00000000",
+40 => x"72722473",
+41 => x"732e0753",
+42 => x"51040000",
+43 => x"00000000",
+44 => x"00000000",
+45 => x"00000000",
+46 => x"00000000",
+47 => x"00000000",
+48 => x"71737109",
+49 => x"71068106",
+50 => x"30720a10",
+51 => x"0a720a10",
+52 => x"0a31050a",
+53 => x"81065151",
+54 => x"53510400",
+55 => x"00000000",
+56 => x"72722673",
+57 => x"732e0753",
+58 => x"51040000",
+59 => x"00000000",
+60 => x"00000000",
+61 => x"00000000",
+62 => x"00000000",
+63 => x"00000000",
+64 => x"00000000",
+65 => x"00000000",
+66 => x"00000000",
+67 => x"00000000",
+68 => x"00000000",
+69 => x"00000000",
+70 => x"00000000",
+71 => x"00000000",
+72 => x"0b0b0b88",
+73 => x"c4040000",
+74 => x"00000000",
+75 => x"00000000",
+76 => x"00000000",
+77 => x"00000000",
+78 => x"00000000",
+79 => x"00000000",
+80 => x"720a722b",
+81 => x"0a535104",
+82 => x"00000000",
+83 => x"00000000",
+84 => x"00000000",
+85 => x"00000000",
+86 => x"00000000",
+87 => x"00000000",
+88 => x"72729f06",
+89 => x"0981050b",
+90 => x"0b0b88a7",
+91 => x"05040000",
+92 => x"00000000",
+93 => x"00000000",
+94 => x"00000000",
+95 => x"00000000",
+96 => x"72722aff",
+97 => x"739f062a",
+98 => x"0974090a",
+99 => x"8106ff05",
+100 => x"06075351",
+101 => x"04000000",
+102 => x"00000000",
+103 => x"00000000",
+104 => x"71715351",
+105 => x"020d0406",
+106 => x"73830609",
+107 => x"81058205",
+108 => x"832b0b2b",
+109 => x"0772fc06",
+110 => x"0c515104",
+111 => x"00000000",
+112 => x"72098105",
+113 => x"72050970",
+114 => x"81050906",
+115 => x"0a810653",
+116 => x"51040000",
+117 => x"00000000",
+118 => x"00000000",
+119 => x"00000000",
+120 => x"72098105",
+121 => x"72050970",
+122 => x"81050906",
+123 => x"0a098106",
+124 => x"53510400",
+125 => x"00000000",
+126 => x"00000000",
+127 => x"00000000",
+128 => x"71098105",
+129 => x"52040000",
+130 => x"00000000",
+131 => x"00000000",
+132 => x"00000000",
+133 => x"00000000",
+134 => x"00000000",
+135 => x"00000000",
+136 => x"72720981",
+137 => x"05055351",
+138 => x"04000000",
+139 => x"00000000",
+140 => x"00000000",
+141 => x"00000000",
+142 => x"00000000",
+143 => x"00000000",
+144 => x"72097206",
+145 => x"73730906",
+146 => x"07535104",
+147 => x"00000000",
+148 => x"00000000",
+149 => x"00000000",
+150 => x"00000000",
+151 => x"00000000",
+152 => x"71fc0608",
+153 => x"72830609",
+154 => x"81058305",
+155 => x"1010102a",
+156 => x"81ff0652",
+157 => x"04000000",
+158 => x"00000000",
+159 => x"00000000",
+160 => x"71fc0608",
+161 => x"0b0b80cf",
+162 => x"cc738306",
+163 => x"10100508",
+164 => x"060b0b0b",
+165 => x"88aa0400",
+166 => x"00000000",
+167 => x"00000000",
+168 => x"80088408",
+169 => x"88087575",
+170 => x"0b0b0b8b",
+171 => x"ab2d5050",
+172 => x"80085688",
+173 => x"0c840c80",
+174 => x"0c510400",
+175 => x"00000000",
+176 => x"80088408",
+177 => x"88087575",
+178 => x"0b0b0b8b",
+179 => x"ef2d5050",
+180 => x"80085688",
+181 => x"0c840c80",
+182 => x"0c510400",
+183 => x"00000000",
+184 => x"72097081",
+185 => x"0509060a",
+186 => x"8106ff05",
+187 => x"70547106",
+188 => x"73097274",
+189 => x"05ff0506",
+190 => x"07515151",
+191 => x"04000000",
+192 => x"72097081",
+193 => x"0509060a",
+194 => x"098106ff",
+195 => x"05705471",
+196 => x"06730972",
+197 => x"7405ff05",
+198 => x"06075151",
+199 => x"51040000",
+200 => x"05ff0504",
+201 => x"00000000",
+202 => x"00000000",
+203 => x"00000000",
+204 => x"00000000",
+205 => x"00000000",
+206 => x"00000000",
+207 => x"00000000",
+208 => x"810b0b0b",
+209 => x"80cfdc0c",
+210 => x"51040000",
+211 => x"00000000",
+212 => x"00000000",
+213 => x"00000000",
+214 => x"00000000",
+215 => x"00000000",
+216 => x"71810552",
+217 => x"04000000",
+218 => x"00000000",
+219 => x"00000000",
+220 => x"00000000",
+221 => x"00000000",
+222 => x"00000000",
+223 => x"00000000",
+224 => x"00000000",
+225 => x"00000000",
+226 => x"00000000",
+227 => x"00000000",
+228 => x"00000000",
+229 => x"00000000",
+230 => x"00000000",
+231 => x"00000000",
+232 => x"02840572",
+233 => x"10100552",
+234 => x"04000000",
+235 => x"00000000",
+236 => x"00000000",
+237 => x"00000000",
+238 => x"00000000",
+239 => x"00000000",
+240 => x"00000000",
+241 => x"00000000",
+242 => x"00000000",
+243 => x"00000000",
+244 => x"00000000",
+245 => x"00000000",
+246 => x"00000000",
+247 => x"00000000",
+248 => x"717105ff",
+249 => x"05715351",
+250 => x"020d0400",
+251 => x"00000000",
+252 => x"00000000",
+253 => x"00000000",
+254 => x"00000000",
+255 => x"00000000",
+256 => x"82c53f80",
+257 => x"c6e63f04",
+258 => x"10101010",
+259 => x"10101010",
+260 => x"10101010",
+261 => x"10101010",
+262 => x"10101010",
+263 => x"10101010",
+264 => x"10101010",
+265 => x"10101053",
+266 => x"51047381",
+267 => x"ff067383",
+268 => x"06098105",
+269 => x"83051010",
+270 => x"102b0772",
+271 => x"fc060c51",
+272 => x"51043c04",
+273 => x"72728072",
+274 => x"8106ff05",
+275 => x"09720605",
+276 => x"71105272",
+277 => x"0a100a53",
+278 => x"72ed3851",
+279 => x"51535104",
+280 => x"fe3d0d0b",
+281 => x"0b80dfc8",
+282 => x"08538413",
+283 => x"0870882a",
+284 => x"70810651",
+285 => x"52527080",
+286 => x"2ef03871",
+287 => x"81ff0680",
+288 => x"0c843d0d",
+289 => x"04ff3d0d",
+290 => x"0b0b80df",
+291 => x"c8085271",
+292 => x"0870882a",
+293 => x"81327081",
+294 => x"06515151",
+295 => x"70f13873",
+296 => x"720c833d",
+297 => x"0d0480cf",
+298 => x"dc08802e",
+299 => x"a43880cf",
+300 => x"e008822e",
+301 => x"bd388380",
+302 => x"800b0b0b",
+303 => x"80dfc80c",
+304 => x"82a0800b",
+305 => x"80dfcc0c",
+306 => x"8290800b",
+307 => x"80dfd00c",
+308 => x"04f88080",
+309 => x"80a40b0b",
+310 => x"0b80dfc8",
+311 => x"0cf88080",
+312 => x"82800b80",
+313 => x"dfcc0cf8",
+314 => x"80808480",
+315 => x"0b80dfd0",
+316 => x"0c0480c0",
+317 => x"a8808c0b",
+318 => x"0b0b80df",
+319 => x"c80c80c0",
+320 => x"a880940b",
+321 => x"80dfcc0c",
+322 => x"0b0b80cf",
+323 => x"980b80df",
+324 => x"d00c0470",
+325 => x"7080dfd4",
+326 => x"335170a7",
+327 => x"3880cfe8",
+328 => x"08700852",
+329 => x"5270802e",
+330 => x"94388412",
+331 => x"80cfe80c",
+332 => x"702d80cf",
+333 => x"e8087008",
+334 => x"525270ee",
+335 => x"38810b80",
+336 => x"dfd43450",
+337 => x"50040470",
+338 => x"0b0b80df",
+339 => x"c408802e",
+340 => x"8e380b0b",
+341 => x"0b0b800b",
+342 => x"802e0981",
+343 => x"06833850",
+344 => x"040b0b80",
+345 => x"dfc4510b",
+346 => x"0b0bf594",
+347 => x"3f500404",
+348 => x"803d0d80",
+349 => x"dfe00881",
+350 => x"1180dfe0",
+351 => x"0c51823d",
+352 => x"0d04fe3d",
+353 => x"0d80dfe0",
+354 => x"085380df",
+355 => x"e0085272",
+356 => x"722e8f38",
+357 => x"80cf9c51",
+358 => x"82b03f80",
+359 => x"dfe00853",
+360 => x"e93980cf",
+361 => x"ac5182a2",
+362 => x"3fe039fb",
+363 => x"3d0d7779",
+364 => x"55558056",
+365 => x"757524ab",
+366 => x"38807424",
+367 => x"9d388053",
+368 => x"73527451",
+369 => x"80e13f80",
+370 => x"08547580",
+371 => x"2e853880",
+372 => x"08305473",
+373 => x"800c873d",
+374 => x"0d047330",
+375 => x"76813257",
+376 => x"54dc3974",
+377 => x"30558156",
+378 => x"738025d2",
+379 => x"38ec39fa",
+380 => x"3d0d787a",
+381 => x"57558057",
+382 => x"767524a4",
+383 => x"38759f2c",
+384 => x"54815375",
+385 => x"74327431",
+386 => x"5274519b",
+387 => x"3f800854",
+388 => x"76802e85",
+389 => x"38800830",
+390 => x"5473800c",
+391 => x"883d0d04",
+392 => x"74305581",
+393 => x"57d739fc",
+394 => x"3d0d7678",
+395 => x"53548153",
+396 => x"80747326",
+397 => x"52557280",
+398 => x"2e983870",
+399 => x"802eab38",
+400 => x"807224a6",
+401 => x"38711073",
+402 => x"10757226",
+403 => x"53545272",
+404 => x"ea387351",
+405 => x"78833874",
+406 => x"5170800c",
+407 => x"863d0d04",
+408 => x"720a100a",
+409 => x"720a100a",
+410 => x"53537280",
+411 => x"2ee43871",
+412 => x"7426ed38",
+413 => x"73723175",
+414 => x"7407740a",
+415 => x"100a740a",
+416 => x"100a5555",
+417 => x"5654e339",
+418 => x"f73d0d7c",
+419 => x"70525380",
+420 => x"fd3f7254",
+421 => x"8008550b",
+422 => x"0b80cfb8",
+423 => x"56815780",
+424 => x"0881055a",
+425 => x"8b3de411",
+426 => x"59538259",
+427 => x"f413527b",
+428 => x"88110852",
+429 => x"5381b43f",
+430 => x"80083070",
+431 => x"8008079f",
+432 => x"2c8a0780",
+433 => x"0c538b3d",
+434 => x"0d04f63d",
+435 => x"0d7c80cf",
+436 => x"ec087153",
+437 => x"5553b73f",
+438 => x"72558008",
+439 => x"560b0b80",
+440 => x"cfb85781",
+441 => x"58800881",
+442 => x"055b8c3d",
+443 => x"e4115a53",
+444 => x"825af413",
+445 => x"52881408",
+446 => x"5180f03f",
+447 => x"80083070",
+448 => x"8008079f",
+449 => x"2c8a0780",
+450 => x"0c548c3d",
+451 => x"0d047070",
+452 => x"70707570",
+453 => x"71830653",
+454 => x"555270b4",
+455 => x"38717008",
+456 => x"7009f7fb",
+457 => x"fdff1206",
+458 => x"f8848281",
+459 => x"80065452",
+460 => x"53719b38",
+461 => x"84137008",
+462 => x"7009f7fb",
+463 => x"fdff1206",
+464 => x"f8848281",
+465 => x"80065452",
+466 => x"5371802e",
+467 => x"e7387252",
+468 => x"71335372",
+469 => x"802e8a38",
+470 => x"81127033",
+471 => x"545272f8",
+472 => x"38717431",
+473 => x"800c5050",
+474 => x"505004f2",
+475 => x"3d0d6062",
+476 => x"88110870",
+477 => x"58565f5a",
+478 => x"73802e81",
+479 => x"8c388c1a",
+480 => x"2270832a",
+481 => x"81328106",
+482 => x"56587486",
+483 => x"38901a08",
+484 => x"91387951",
+485 => x"90b73fff",
+486 => x"55800880",
+487 => x"ec388c1a",
+488 => x"22587d08",
+489 => x"55807883",
+490 => x"ffff0670",
+491 => x"0a100a81",
+492 => x"06415c57",
+493 => x"7e772e80",
+494 => x"d7387690",
+495 => x"38740884",
+496 => x"16088817",
+497 => x"57585676",
+498 => x"802ef238",
+499 => x"76548880",
+500 => x"77278438",
+501 => x"88805473",
+502 => x"5375529c",
+503 => x"1a0851a4",
+504 => x"1a085877",
+505 => x"2d800b80",
+506 => x"082582e0",
+507 => x"38800816",
+508 => x"77800831",
+509 => x"7f880508",
+510 => x"80083170",
+511 => x"6188050c",
+512 => x"5b585678",
+513 => x"ffb43880",
+514 => x"5574800c",
+515 => x"903d0d04",
+516 => x"7a813281",
+517 => x"06774056",
+518 => x"75802e81",
+519 => x"bd387690",
+520 => x"38740884",
+521 => x"16088817",
+522 => x"57585976",
+523 => x"802ef238",
+524 => x"881a0878",
+525 => x"83ffff06",
+526 => x"70892a81",
+527 => x"06565956",
+528 => x"73802e82",
+529 => x"f8387577",
+530 => x"278b3877",
+531 => x"872a8106",
+532 => x"5c7b82b5",
+533 => x"38767627",
+534 => x"83387656",
+535 => x"75537852",
+536 => x"79085185",
+537 => x"833f881a",
+538 => x"08763188",
+539 => x"1b0c7908",
+540 => x"167a0c76",
+541 => x"56751977",
+542 => x"77317f88",
+543 => x"05087831",
+544 => x"70618805",
+545 => x"0c415859",
+546 => x"7e802efe",
+547 => x"fa388c1a",
+548 => x"2258ff8a",
+549 => x"39787954",
+550 => x"7c537b52",
+551 => x"5684c93f",
+552 => x"881a0879",
+553 => x"31881b0c",
+554 => x"7908197a",
+555 => x"0c7c7631",
+556 => x"5d7c8e38",
+557 => x"79518ff2",
+558 => x"3f800881",
+559 => x"8f388008",
+560 => x"5f751c77",
+561 => x"77317f88",
+562 => x"05087831",
+563 => x"70618805",
+564 => x"0c5d585c",
+565 => x"7a802efe",
+566 => x"ae387681",
+567 => x"83387408",
+568 => x"84160888",
+569 => x"1757585c",
+570 => x"76802ef2",
+571 => x"3876538a",
+572 => x"527b5182",
+573 => x"d33f8008",
+574 => x"7c318105",
+575 => x"5d800884",
+576 => x"3881175d",
+577 => x"815f7c59",
+578 => x"767d2783",
+579 => x"38765994",
+580 => x"1a08881b",
+581 => x"08115758",
+582 => x"807a085c",
+583 => x"54901a08",
+584 => x"7b278338",
+585 => x"81547579",
+586 => x"25843873",
+587 => x"ba387779",
+588 => x"24fee238",
+589 => x"77537b52",
+590 => x"9c1a0851",
+591 => x"a41a0859",
+592 => x"782d8008",
+593 => x"56800880",
+594 => x"24fee238",
+595 => x"8c1a2280",
+596 => x"c0075e7d",
+597 => x"8c1b23ff",
+598 => x"5574800c",
+599 => x"903d0d04",
+600 => x"7effa338",
+601 => x"ff873975",
+602 => x"537b527a",
+603 => x"5182f93f",
+604 => x"7908167a",
+605 => x"0c79518e",
+606 => x"b13f8008",
+607 => x"cf387c76",
+608 => x"315d7cfe",
+609 => x"bc38feac",
+610 => x"39901a08",
+611 => x"7a087131",
+612 => x"78117056",
+613 => x"5a575280",
+614 => x"cfec0851",
+615 => x"84943f80",
+616 => x"08802eff",
+617 => x"a7388008",
+618 => x"901b0c80",
+619 => x"08167a0c",
+620 => x"77941b0c",
+621 => x"76881b0c",
+622 => x"7656fd99",
+623 => x"39790858",
+624 => x"901a0878",
+625 => x"27833881",
+626 => x"54757727",
+627 => x"843873b3",
+628 => x"38941a08",
+629 => x"54737726",
+630 => x"80d33873",
+631 => x"5378529c",
+632 => x"1a0851a4",
+633 => x"1a085877",
+634 => x"2d800856",
+635 => x"80088024",
+636 => x"fd83388c",
+637 => x"1a2280c0",
+638 => x"075e7d8c",
+639 => x"1b23ff55",
+640 => x"fed73975",
+641 => x"53785277",
+642 => x"5181dd3f",
+643 => x"7908167a",
+644 => x"0c79518d",
+645 => x"953f8008",
+646 => x"802efcd9",
+647 => x"388c1a22",
+648 => x"80c0075e",
+649 => x"7d8c1b23",
+650 => x"ff55fead",
+651 => x"39767754",
+652 => x"79537852",
+653 => x"5681b13f",
+654 => x"881a0877",
+655 => x"31881b0c",
+656 => x"7908177a",
+657 => x"0cfcae39",
+658 => x"fa3d0d7a",
+659 => x"79028805",
+660 => x"a7053355",
+661 => x"53548374",
+662 => x"2780df38",
+663 => x"71830651",
+664 => x"7080d738",
+665 => x"71715755",
+666 => x"83517582",
+667 => x"802913ff",
+668 => x"12525670",
+669 => x"8025f338",
+670 => x"837427bc",
+671 => x"38740876",
+672 => x"327009f7",
+673 => x"fbfdff12",
+674 => x"06f88482",
+675 => x"81800651",
+676 => x"5170802e",
+677 => x"98387451",
+678 => x"80527033",
+679 => x"5772772e",
+680 => x"b9388111",
+681 => x"81135351",
+682 => x"837227ee",
+683 => x"38fc1484",
+684 => x"16565473",
+685 => x"8326c638",
+686 => x"7452ff14",
+687 => x"5170ff2e",
+688 => x"97387133",
+689 => x"5472742e",
+690 => x"98388112",
+691 => x"ff125252",
+692 => x"70ff2e09",
+693 => x"8106eb38",
+694 => x"80517080",
+695 => x"0c883d0d",
+696 => x"0471800c",
+697 => x"883d0d04",
+698 => x"fa3d0d78",
+699 => x"7a7c7272",
+700 => x"72595755",
+701 => x"58565774",
+702 => x"7727b238",
+703 => x"75155176",
+704 => x"7127aa38",
+705 => x"707618ff",
+706 => x"18535353",
+707 => x"70ff2e96",
+708 => x"38ff12ff",
+709 => x"14545272",
+710 => x"337234ff",
+711 => x"115170ff",
+712 => x"2e098106",
+713 => x"ec387680",
+714 => x"0c883d0d",
+715 => x"048f7627",
+716 => x"80e63874",
+717 => x"77078306",
+718 => x"517080dc",
+719 => x"38767552",
+720 => x"53707084",
+721 => x"05520873",
+722 => x"70840555",
+723 => x"0c727170",
+724 => x"84055308",
+725 => x"71708405",
+726 => x"530c7170",
+727 => x"84055308",
+728 => x"71708405",
+729 => x"530c7170",
+730 => x"84055308",
+731 => x"71708405",
+732 => x"530cf015",
+733 => x"5553738f",
+734 => x"26c73883",
+735 => x"74279538",
+736 => x"70708405",
+737 => x"52087370",
+738 => x"8405550c",
+739 => x"fc145473",
+740 => x"8326ed38",
+741 => x"72715452",
+742 => x"ff145170",
+743 => x"ff2eff86",
+744 => x"38727081",
+745 => x"05543372",
+746 => x"70810554",
+747 => x"34ff1151",
+748 => x"ea39ef3d",
+749 => x"0d636567",
+750 => x"405d427b",
+751 => x"802e8582",
+752 => x"386151a9",
+753 => x"e73ff81c",
+754 => x"70841208",
+755 => x"70fc0670",
+756 => x"628b0570",
+757 => x"f8064159",
+758 => x"455c5f41",
+759 => x"57967427",
+760 => x"82c53880",
+761 => x"7b247e7c",
+762 => x"26075880",
+763 => x"5477742e",
+764 => x"09810682",
+765 => x"ab38787b",
+766 => x"2581fe38",
+767 => x"781780d7",
+768 => x"a80b8805",
+769 => x"085b5679",
+770 => x"762e84c5",
+771 => x"38841608",
+772 => x"70fe0617",
+773 => x"84110881",
+774 => x"06415555",
+775 => x"7e828d38",
+776 => x"74fc0658",
+777 => x"79762e84",
+778 => x"e3387818",
+779 => x"5f7e7b25",
+780 => x"81ff387c",
+781 => x"81065473",
+782 => x"82c13876",
+783 => x"77083184",
+784 => x"1108fc06",
+785 => x"56577580",
+786 => x"2e913879",
+787 => x"762e84f0",
+788 => x"38741819",
+789 => x"58777b25",
+790 => x"84913876",
+791 => x"802e829b",
+792 => x"38781556",
+793 => x"7a762482",
+794 => x"92388c17",
+795 => x"08881808",
+796 => x"718c120c",
+797 => x"88120c5e",
+798 => x"75598817",
+799 => x"61fc055b",
+800 => x"5679a426",
+801 => x"85ff387b",
+802 => x"76595593",
+803 => x"7a2780c9",
+804 => x"387b7084",
+805 => x"055d087c",
+806 => x"56760c74",
+807 => x"70840556",
+808 => x"088c180c",
+809 => x"9017589b",
+810 => x"7a27ae38",
+811 => x"74708405",
+812 => x"5608780c",
+813 => x"74708405",
+814 => x"56089418",
+815 => x"0c981758",
+816 => x"a37a2795",
+817 => x"38747084",
+818 => x"05560878",
+819 => x"0c747084",
+820 => x"0556089c",
+821 => x"180ca017",
+822 => x"58747084",
+823 => x"05560875",
+824 => x"5f787084",
+825 => x"055a0c77",
+826 => x"7e708405",
+827 => x"40087170",
+828 => x"8405530c",
+829 => x"7e08710c",
+830 => x"5d787b31",
+831 => x"56758f26",
+832 => x"80c93884",
+833 => x"17088106",
+834 => x"79078418",
+835 => x"0c781784",
+836 => x"11088107",
+837 => x"84120c5b",
+838 => x"6151a791",
+839 => x"3f881754",
+840 => x"73800c93",
+841 => x"3d0d0490",
+842 => x"5bfdb839",
+843 => x"7756fe83",
+844 => x"398c1608",
+845 => x"88170871",
+846 => x"8c120c88",
+847 => x"120c587e",
+848 => x"707c3157",
+849 => x"598f7627",
+850 => x"ffb9387a",
+851 => x"17841808",
+852 => x"81067c07",
+853 => x"84190c76",
+854 => x"81078412",
+855 => x"0c761184",
+856 => x"11088107",
+857 => x"84120c5b",
+858 => x"88055261",
+859 => x"518fda3f",
+860 => x"6151a6b9",
+861 => x"3f881754",
+862 => x"ffa6397d",
+863 => x"52615197",
+864 => x"d73f8008",
+865 => x"5a800880",
+866 => x"2e81ab38",
+867 => x"8008f805",
+868 => x"60840508",
+869 => x"fe066105",
+870 => x"58557477",
+871 => x"2e83f238",
+872 => x"fc195877",
+873 => x"a42681b0",
+874 => x"387b8008",
+875 => x"56579378",
+876 => x"2780dc38",
+877 => x"7b707084",
+878 => x"05520880",
+879 => x"08708405",
+880 => x"800c0c80",
+881 => x"08717084",
+882 => x"0553085d",
+883 => x"567b7670",
+884 => x"8405580c",
+885 => x"579b7827",
+886 => x"b6387670",
+887 => x"84055808",
+888 => x"75708405",
+889 => x"570c7670",
+890 => x"84055808",
+891 => x"75708405",
+892 => x"570ca378",
+893 => x"27993876",
+894 => x"70840558",
+895 => x"08757084",
+896 => x"05570c76",
+897 => x"70840558",
+898 => x"08757084",
+899 => x"05570c76",
+900 => x"70840558",
+901 => x"08775e75",
+902 => x"70840557",
+903 => x"0c747d70",
+904 => x"84055f08",
+905 => x"71708405",
+906 => x"530c7d08",
+907 => x"710c5f7b",
+908 => x"5261518e",
+909 => x"943f6151",
+910 => x"a4f33f79",
+911 => x"800c933d",
+912 => x"0d047d52",
+913 => x"61519690",
+914 => x"3f800880",
+915 => x"0c933d0d",
+916 => x"04841608",
+917 => x"55fbc939",
+918 => x"77537b52",
+919 => x"800851a2",
+920 => x"a53f7b52",
+921 => x"61518de1",
+922 => x"3fcc398c",
+923 => x"16088817",
+924 => x"08718c12",
+925 => x"0c88120c",
+926 => x"5d8c1708",
+927 => x"88180871",
+928 => x"8c120c88",
+929 => x"120c5977",
+930 => x"59fbef39",
+931 => x"7818901c",
+932 => x"40557e75",
+933 => x"24fb9c38",
+934 => x"7a177080",
+935 => x"d7a80b88",
+936 => x"050c757c",
+937 => x"31810784",
+938 => x"120c5684",
+939 => x"17088106",
+940 => x"7b078418",
+941 => x"0c6151a3",
+942 => x"f43f8817",
+943 => x"54fce139",
+944 => x"74181990",
+945 => x"1c5e5a7c",
+946 => x"7a24fb8f",
+947 => x"388c1708",
+948 => x"88180871",
+949 => x"8c120c88",
+950 => x"120c5e88",
+951 => x"1761fc05",
+952 => x"575975a4",
+953 => x"2681b638",
+954 => x"7b795955",
+955 => x"93762780",
+956 => x"c9387b70",
+957 => x"84055d08",
+958 => x"7c56790c",
+959 => x"74708405",
+960 => x"56088c18",
+961 => x"0c901758",
+962 => x"9b7627ae",
+963 => x"38747084",
+964 => x"05560878",
+965 => x"0c747084",
+966 => x"05560894",
+967 => x"180c9817",
+968 => x"58a37627",
+969 => x"95387470",
+970 => x"84055608",
+971 => x"780c7470",
+972 => x"84055608",
+973 => x"9c180ca0",
+974 => x"17587470",
+975 => x"84055608",
+976 => x"75417870",
+977 => x"84055a0c",
+978 => x"77607084",
+979 => x"05420871",
+980 => x"70840553",
+981 => x"0c600871",
+982 => x"0c5e7a17",
+983 => x"7080d7a8",
+984 => x"0b88050c",
+985 => x"7a7c3181",
+986 => x"0784120c",
+987 => x"58841708",
+988 => x"81067b07",
+989 => x"84180c61",
+990 => x"51a2b23f",
+991 => x"78547380",
+992 => x"0c933d0d",
+993 => x"0479537b",
+994 => x"5275519f",
+995 => x"f93ffae9",
+996 => x"39841508",
+997 => x"fc061960",
+998 => x"5859fadd",
+999 => x"3975537b",
+1000 => x"5278519f",
+1001 => x"e13f7a17",
+1002 => x"7080d7a8",
+1003 => x"0b88050c",
+1004 => x"7a7c3181",
+1005 => x"0784120c",
+1006 => x"58841708",
+1007 => x"81067b07",
+1008 => x"84180c61",
+1009 => x"51a1e63f",
+1010 => x"7854ffb2",
+1011 => x"39fa3d0d",
+1012 => x"7880cfec",
+1013 => x"085455b8",
+1014 => x"1308802e",
+1015 => x"81af388c",
+1016 => x"15227083",
+1017 => x"ffff0670",
+1018 => x"832a8132",
+1019 => x"81065555",
+1020 => x"5672802e",
+1021 => x"80da3873",
+1022 => x"842a8132",
+1023 => x"810657ff",
+1024 => x"537680f2",
+1025 => x"3873822a",
+1026 => x"81065473",
+1027 => x"802eb938",
+1028 => x"b0150854",
+1029 => x"73802e9c",
+1030 => x"3880c015",
+1031 => x"5373732e",
+1032 => x"8f387352",
+1033 => x"80cfec08",
+1034 => x"518a9e3f",
+1035 => x"8c152256",
+1036 => x"76b0160c",
+1037 => x"75db0657",
+1038 => x"768c1623",
+1039 => x"800b8416",
+1040 => x"0c901508",
+1041 => x"750c7656",
+1042 => x"75880754",
+1043 => x"738c1623",
+1044 => x"90150880",
+1045 => x"2ebf388c",
+1046 => x"15227081",
+1047 => x"06555373",
+1048 => x"9c38720a",
+1049 => x"100a8106",
+1050 => x"56758538",
+1051 => x"94150854",
+1052 => x"7388160c",
+1053 => x"80537280",
+1054 => x"0c883d0d",
+1055 => x"04800b88",
+1056 => x"160c9415",
+1057 => x"08309816",
+1058 => x"0c8053ea",
+1059 => x"39725182",
+1060 => x"a63ffecb",
+1061 => x"3974518f",
+1062 => x"bc3f8c15",
+1063 => x"22708106",
+1064 => x"55537380",
+1065 => x"2effbb38",
+1066 => x"d439f83d",
+1067 => x"0d7a5776",
+1068 => x"802e8197",
+1069 => x"3880cfec",
+1070 => x"0854b814",
+1071 => x"08802e80",
+1072 => x"eb388c17",
+1073 => x"2270902b",
+1074 => x"70902c70",
+1075 => x"832a8132",
+1076 => x"81065b5b",
+1077 => x"57557780",
+1078 => x"cb389017",
+1079 => x"08567580",
+1080 => x"2e80c138",
+1081 => x"76087631",
+1082 => x"76780c79",
+1083 => x"83065555",
+1084 => x"73853894",
+1085 => x"17085877",
+1086 => x"88180c80",
+1087 => x"7525a538",
+1088 => x"74537552",
+1089 => x"9c170851",
+1090 => x"a4170854",
+1091 => x"732d800b",
+1092 => x"80082580",
+1093 => x"c9388008",
+1094 => x"16758008",
+1095 => x"31565674",
+1096 => x"8024dd38",
+1097 => x"800b800c",
+1098 => x"8a3d0d04",
+1099 => x"73518187",
+1100 => x"3f8c1722",
+1101 => x"70902b70",
+1102 => x"902c7083",
+1103 => x"2a813281",
+1104 => x"065b5b57",
+1105 => x"5577dd38",
+1106 => x"ff9039a1",
+1107 => x"aa5280cf",
+1108 => x"ec08518c",
+1109 => x"d03f8008",
+1110 => x"800c8a3d",
+1111 => x"0d048c17",
+1112 => x"2280c007",
+1113 => x"58778c18",
+1114 => x"23ff0b80",
+1115 => x"0c8a3d0d",
+1116 => x"04fa3d0d",
+1117 => x"797080dc",
+1118 => x"298c1154",
+1119 => x"7a535657",
+1120 => x"8fd63f80",
+1121 => x"08800855",
+1122 => x"56800880",
+1123 => x"2ea23880",
+1124 => x"088c0554",
+1125 => x"800b8008",
+1126 => x"0c768008",
+1127 => x"84050c73",
+1128 => x"80088805",
+1129 => x"0c745380",
+1130 => x"5273519c",
+1131 => x"f53f7554",
+1132 => x"73800c88",
+1133 => x"3d0d0470",
+1134 => x"707074a8",
+1135 => x"f60bbc12",
+1136 => x"0c53810b",
+1137 => x"b8140c80",
+1138 => x"0b84dc14",
+1139 => x"0c830b84",
+1140 => x"e0140c84",
+1141 => x"e81384e4",
+1142 => x"140c8413",
+1143 => x"08518070",
+1144 => x"720c7084",
+1145 => x"130c7088",
+1146 => x"130c5284",
+1147 => x"0b8c1223",
+1148 => x"718e1223",
+1149 => x"7190120c",
+1150 => x"7194120c",
+1151 => x"7198120c",
+1152 => x"709c120c",
+1153 => x"80c1e50b",
+1154 => x"a0120c80",
+1155 => x"c2b10ba4",
+1156 => x"120c80c3",
+1157 => x"ad0ba812",
+1158 => x"0c80c3fe",
+1159 => x"0bac120c",
+1160 => x"88130872",
+1161 => x"710c7284",
+1162 => x"120c7288",
+1163 => x"120c5189",
+1164 => x"0b8c1223",
+1165 => x"810b8e12",
+1166 => x"23719012",
+1167 => x"0c719412",
+1168 => x"0c719812",
+1169 => x"0c709c12",
+1170 => x"0c80c1e5",
+1171 => x"0ba0120c",
+1172 => x"80c2b10b",
+1173 => x"a4120c80",
+1174 => x"c3ad0ba8",
+1175 => x"120c80c3",
+1176 => x"fe0bac12",
+1177 => x"0c8c1308",
+1178 => x"72710c72",
+1179 => x"84120c72",
+1180 => x"88120c51",
+1181 => x"8a0b8c12",
+1182 => x"23820b8e",
+1183 => x"12237190",
+1184 => x"120c7194",
+1185 => x"120c7198",
+1186 => x"120c709c",
+1187 => x"120c80c1",
+1188 => x"e50ba012",
+1189 => x"0c80c2b1",
+1190 => x"0ba4120c",
+1191 => x"80c3ad0b",
+1192 => x"a8120c80",
+1193 => x"c3fe0bac",
+1194 => x"120c5050",
+1195 => x"5004f83d",
+1196 => x"0d7a80cf",
+1197 => x"ec08b811",
+1198 => x"08575758",
+1199 => x"7481ec38",
+1200 => x"a8f60bbc",
+1201 => x"170c810b",
+1202 => x"b8170c74",
+1203 => x"84dc170c",
+1204 => x"830b84e0",
+1205 => x"170c84e8",
+1206 => x"1684e417",
+1207 => x"0c841608",
+1208 => x"75710c75",
+1209 => x"84120c75",
+1210 => x"88120c59",
+1211 => x"840b8c1a",
+1212 => x"23748e1a",
+1213 => x"2374901a",
+1214 => x"0c74941a",
+1215 => x"0c74981a",
+1216 => x"0c789c1a",
+1217 => x"0c80c1e5",
+1218 => x"0ba01a0c",
+1219 => x"80c2b10b",
+1220 => x"a41a0c80",
+1221 => x"c3ad0ba8",
+1222 => x"1a0c80c3",
+1223 => x"fe0bac1a",
+1224 => x"0c881608",
+1225 => x"75710c75",
+1226 => x"84120c75",
+1227 => x"88120c57",
+1228 => x"890b8c18",
+1229 => x"23810b8e",
+1230 => x"18237490",
+1231 => x"180c7494",
+1232 => x"180c7498",
+1233 => x"180c769c",
+1234 => x"180c80c1",
+1235 => x"e50ba018",
+1236 => x"0c80c2b1",
+1237 => x"0ba4180c",
+1238 => x"80c3ad0b",
+1239 => x"a8180c80",
+1240 => x"c3fe0bac",
+1241 => x"180c8c16",
+1242 => x"0875710c",
+1243 => x"7584120c",
+1244 => x"7588120c",
+1245 => x"548a0b8c",
+1246 => x"1523820b",
+1247 => x"8e152374",
+1248 => x"90150c74",
+1249 => x"94150c74",
+1250 => x"98150c73",
+1251 => x"9c150c80",
+1252 => x"c1e50ba0",
+1253 => x"150c80c2",
+1254 => x"b10ba415",
+1255 => x"0c80c3ad",
+1256 => x"0ba8150c",
+1257 => x"80c3fe0b",
+1258 => x"ac150c84",
+1259 => x"dc168811",
+1260 => x"08841208",
+1261 => x"ff055757",
+1262 => x"57807524",
+1263 => x"9f388c16",
+1264 => x"2270902b",
+1265 => x"70902c51",
+1266 => x"55597380",
+1267 => x"2e80ed38",
+1268 => x"80dc16ff",
+1269 => x"16565674",
+1270 => x"8025e338",
+1271 => x"76085574",
+1272 => x"802e8f38",
+1273 => x"74881108",
+1274 => x"841208ff",
+1275 => x"05575757",
+1276 => x"c83982fc",
+1277 => x"5277518a",
+1278 => x"df3f8008",
+1279 => x"80085556",
+1280 => x"8008802e",
+1281 => x"a3388008",
+1282 => x"8c057580",
+1283 => x"080c5484",
+1284 => x"0b800884",
+1285 => x"050c7380",
+1286 => x"0888050c",
+1287 => x"82f05374",
+1288 => x"52735197",
+1289 => x"fd3f7554",
+1290 => x"7374780c",
+1291 => x"5573ffb4",
+1292 => x"388c780c",
+1293 => x"800b800c",
+1294 => x"8a3d0d04",
+1295 => x"810b8c17",
+1296 => x"2373760c",
+1297 => x"7388170c",
+1298 => x"7384170c",
+1299 => x"7390170c",
+1300 => x"7394170c",
+1301 => x"7398170c",
+1302 => x"ff0b8e17",
+1303 => x"2373b017",
+1304 => x"0c73b417",
+1305 => x"0c7380c4",
+1306 => x"170c7380",
+1307 => x"c8170c75",
+1308 => x"800c8a3d",
+1309 => x"0d047070",
+1310 => x"a1aa5273",
+1311 => x"5186a63f",
+1312 => x"50500470",
+1313 => x"70a1aa52",
+1314 => x"80cfec08",
+1315 => x"5186963f",
+1316 => x"505004fb",
+1317 => x"3d0d7770",
+1318 => x"52569890",
+1319 => x"3f80d7a8",
+1320 => x"0b880508",
+1321 => x"841108fc",
+1322 => x"06707b31",
+1323 => x"9fef05e0",
+1324 => x"8006e080",
+1325 => x"05525555",
+1326 => x"a0807524",
+1327 => x"94388052",
+1328 => x"755197ea",
+1329 => x"3f80d7b0",
+1330 => x"08145372",
+1331 => x"80082e8f",
+1332 => x"38755197",
+1333 => x"d83f8053",
+1334 => x"72800c87",
+1335 => x"3d0d0474",
+1336 => x"30527551",
+1337 => x"97c83f80",
+1338 => x"08ff2ea8",
+1339 => x"3880d7a8",
+1340 => x"0b880508",
+1341 => x"74763181",
+1342 => x"0784120c",
+1343 => x"5380d6ec",
+1344 => x"08753180",
+1345 => x"d6ec0c75",
+1346 => x"5197a23f",
+1347 => x"810b800c",
+1348 => x"873d0d04",
+1349 => x"80527551",
+1350 => x"97943f80",
+1351 => x"d7a80b88",
+1352 => x"05088008",
+1353 => x"71315454",
+1354 => x"8f7325ff",
+1355 => x"a4388008",
+1356 => x"80d79c08",
+1357 => x"3180d6ec",
+1358 => x"0c728107",
+1359 => x"84150c75",
+1360 => x"5196ea3f",
+1361 => x"8053ff90",
+1362 => x"39f73d0d",
+1363 => x"7b7d545a",
+1364 => x"72802e82",
+1365 => x"83387951",
+1366 => x"96d23ff8",
+1367 => x"13841108",
+1368 => x"70fe0670",
+1369 => x"13841108",
+1370 => x"fc065c57",
+1371 => x"58545780",
+1372 => x"d7b00874",
+1373 => x"2e82de38",
+1374 => x"7784150c",
+1375 => x"80738106",
+1376 => x"56597479",
+1377 => x"2e81d538",
+1378 => x"77148411",
+1379 => x"08810656",
+1380 => x"5374a038",
+1381 => x"77165678",
+1382 => x"81e63888",
+1383 => x"14085574",
+1384 => x"80d7b02e",
+1385 => x"82f9388c",
+1386 => x"1408708c",
+1387 => x"170c7588",
+1388 => x"120c5875",
+1389 => x"81078418",
+1390 => x"0c751776",
+1391 => x"710c5478",
+1392 => x"81913883",
+1393 => x"ff762781",
+1394 => x"c8387589",
+1395 => x"2a76832a",
+1396 => x"54547380",
+1397 => x"2ebf3875",
+1398 => x"862ab805",
+1399 => x"53847427",
+1400 => x"b43880db",
+1401 => x"14539474",
+1402 => x"27ab3875",
+1403 => x"8c2a80ee",
+1404 => x"055380d4",
+1405 => x"74279e38",
+1406 => x"758f2a80",
+1407 => x"f7055382",
+1408 => x"d4742791",
+1409 => x"3875922a",
+1410 => x"80fc0553",
+1411 => x"8ad47427",
+1412 => x"843880fe",
+1413 => x"53721010",
+1414 => x"1080d7a8",
+1415 => x"05881108",
+1416 => x"55557375",
+1417 => x"2e82bf38",
+1418 => x"841408fc",
+1419 => x"06597579",
+1420 => x"278d3888",
+1421 => x"14085473",
+1422 => x"752e0981",
+1423 => x"06ea388c",
+1424 => x"1408708c",
+1425 => x"190c7488",
+1426 => x"190c7788",
+1427 => x"120c5576",
+1428 => x"8c150c79",
+1429 => x"5194d63f",
+1430 => x"8b3d0d04",
+1431 => x"76087771",
+1432 => x"31587605",
+1433 => x"88180856",
+1434 => x"567480d7",
+1435 => x"b02e80e0",
+1436 => x"388c1708",
+1437 => x"708c170c",
+1438 => x"7588120c",
+1439 => x"53fe8939",
+1440 => x"8814088c",
+1441 => x"1508708c",
+1442 => x"130c5988",
+1443 => x"190cfea3",
+1444 => x"3975832a",
+1445 => x"70545480",
+1446 => x"74248198",
+1447 => x"3872822c",
+1448 => x"81712b80",
+1449 => x"d7ac0807",
+1450 => x"80d7a80b",
+1451 => x"84050c74",
+1452 => x"10101080",
+1453 => x"d7a80588",
+1454 => x"1108718c",
+1455 => x"1b0c7088",
+1456 => x"1b0c7988",
+1457 => x"130c565a",
+1458 => x"55768c15",
+1459 => x"0cff8439",
+1460 => x"8159fdb4",
+1461 => x"39771673",
+1462 => x"81065455",
+1463 => x"72983876",
+1464 => x"08777131",
+1465 => x"5875058c",
+1466 => x"18088819",
+1467 => x"08718c12",
+1468 => x"0c88120c",
+1469 => x"55557481",
+1470 => x"0784180c",
+1471 => x"7680d7a8",
+1472 => x"0b88050c",
+1473 => x"80d7a408",
+1474 => x"7526fec7",
+1475 => x"3880d7a0",
+1476 => x"08527951",
+1477 => x"fafd3f79",
+1478 => x"5193923f",
+1479 => x"feba3981",
+1480 => x"778c170c",
+1481 => x"7788170c",
+1482 => x"758c190c",
+1483 => x"7588190c",
+1484 => x"59fd8039",
+1485 => x"83147082",
+1486 => x"2c81712b",
+1487 => x"80d7ac08",
+1488 => x"0780d7a8",
+1489 => x"0b84050c",
+1490 => x"75101010",
+1491 => x"80d7a805",
+1492 => x"88110871",
+1493 => x"8c1c0c70",
+1494 => x"881c0c7a",
+1495 => x"88130c57",
+1496 => x"5b5653fe",
+1497 => x"e4398073",
+1498 => x"24a33872",
+1499 => x"822c8171",
+1500 => x"2b80d7ac",
+1501 => x"080780d7",
+1502 => x"a80b8405",
+1503 => x"0c58748c",
+1504 => x"180c7388",
+1505 => x"180c7688",
+1506 => x"160cfdc3",
+1507 => x"39831370",
+1508 => x"822c8171",
+1509 => x"2b80d7ac",
+1510 => x"080780d7",
+1511 => x"a80b8405",
+1512 => x"0c5953da",
+1513 => x"39f93d0d",
+1514 => x"797b5853",
+1515 => x"800b80cf",
+1516 => x"ec085356",
+1517 => x"72722ebc",
+1518 => x"3884dc13",
+1519 => x"5574762e",
+1520 => x"b3388815",
+1521 => x"08841608",
+1522 => x"ff055454",
+1523 => x"80732499",
+1524 => x"388c1422",
+1525 => x"70902b53",
+1526 => x"587180d4",
+1527 => x"3880dc14",
+1528 => x"ff145454",
+1529 => x"728025e9",
+1530 => x"38740855",
+1531 => x"74d43880",
+1532 => x"cfec0852",
+1533 => x"84dc1255",
+1534 => x"74802ead",
+1535 => x"38881508",
+1536 => x"841608ff",
+1537 => x"05545480",
+1538 => x"73249838",
+1539 => x"8c142270",
+1540 => x"902b5358",
+1541 => x"71ad3880",
+1542 => x"dc14ff14",
+1543 => x"54547280",
+1544 => x"25ea3874",
+1545 => x"085574d5",
+1546 => x"3875800c",
+1547 => x"893d0d04",
+1548 => x"7351762d",
+1549 => x"75800807",
+1550 => x"80dc15ff",
+1551 => x"15555556",
+1552 => x"ffa23973",
+1553 => x"51762d75",
+1554 => x"80080780",
+1555 => x"dc15ff15",
+1556 => x"555556ca",
+1557 => x"39ea3d0d",
+1558 => x"688c1122",
+1559 => x"700a100a",
+1560 => x"81065758",
+1561 => x"567480e4",
+1562 => x"388e1622",
+1563 => x"70902b70",
+1564 => x"902c5155",
+1565 => x"58807424",
+1566 => x"b138983d",
+1567 => x"c4055373",
+1568 => x"5280cfec",
+1569 => x"08519481",
+1570 => x"3f800b80",
+1571 => x"08249738",
+1572 => x"7983e080",
+1573 => x"06547380",
+1574 => x"c0802e81",
+1575 => x"8f387382",
+1576 => x"80802e81",
+1577 => x"91388c16",
+1578 => x"22577690",
+1579 => x"80075473",
+1580 => x"8c172388",
+1581 => x"805280cf",
+1582 => x"ec085181",
+1583 => x"9b3f8008",
+1584 => x"9d388c16",
+1585 => x"22820755",
+1586 => x"748c1723",
+1587 => x"80c31670",
+1588 => x"770c9017",
+1589 => x"0c810b94",
+1590 => x"170c983d",
+1591 => x"0d0480cf",
+1592 => x"ec08a8f6",
+1593 => x"0bbc120c",
+1594 => x"588c1622",
+1595 => x"81800754",
+1596 => x"738c1723",
+1597 => x"8008760c",
+1598 => x"80089017",
+1599 => x"0c88800b",
+1600 => x"94170c74",
+1601 => x"802ed338",
+1602 => x"8e162270",
+1603 => x"902b7090",
+1604 => x"2c535654",
+1605 => x"9afb3f80",
+1606 => x"08802eff",
+1607 => x"bd388c16",
+1608 => x"22810757",
+1609 => x"768c1723",
+1610 => x"983d0d04",
+1611 => x"810b8c17",
+1612 => x"225855fe",
+1613 => x"f539a816",
+1614 => x"0880c3ad",
+1615 => x"2e098106",
+1616 => x"fee4388c",
+1617 => x"16228880",
+1618 => x"0754738c",
+1619 => x"17238880",
+1620 => x"0b80cc17",
+1621 => x"0cfedc39",
+1622 => x"f43d0d7e",
+1623 => x"608b1170",
+1624 => x"f8065b55",
+1625 => x"555d7296",
+1626 => x"26833890",
+1627 => x"58807824",
+1628 => x"74792607",
+1629 => x"55805474",
+1630 => x"742e0981",
+1631 => x"0680ca38",
+1632 => x"7c518ea8",
+1633 => x"3f7783f7",
+1634 => x"2680c538",
+1635 => x"77832a70",
+1636 => x"10101080",
+1637 => x"d7a8058c",
+1638 => x"11085858",
+1639 => x"5475772e",
+1640 => x"81f03884",
+1641 => x"1608fc06",
+1642 => x"8c170888",
+1643 => x"1808718c",
+1644 => x"120c8812",
+1645 => x"0c5b7605",
+1646 => x"84110881",
+1647 => x"0784120c",
+1648 => x"537c518d",
+1649 => x"e83f8816",
+1650 => x"5473800c",
+1651 => x"8e3d0d04",
+1652 => x"77892a78",
+1653 => x"832a5854",
+1654 => x"73802ebf",
+1655 => x"3877862a",
+1656 => x"b8055784",
+1657 => x"7427b438",
+1658 => x"80db1457",
+1659 => x"947427ab",
+1660 => x"38778c2a",
+1661 => x"80ee0557",
+1662 => x"80d47427",
+1663 => x"9e38778f",
+1664 => x"2a80f705",
+1665 => x"5782d474",
+1666 => x"27913877",
+1667 => x"922a80fc",
+1668 => x"05578ad4",
+1669 => x"74278438",
+1670 => x"80fe5776",
+1671 => x"10101080",
+1672 => x"d7a8058c",
+1673 => x"11085653",
+1674 => x"74732ea3",
+1675 => x"38841508",
+1676 => x"fc067079",
+1677 => x"31555673",
+1678 => x"8f2488e4",
+1679 => x"38738025",
+1680 => x"88e6388c",
+1681 => x"15085574",
+1682 => x"732e0981",
+1683 => x"06df3881",
+1684 => x"175980d7",
+1685 => x"b8085675",
+1686 => x"80d7b02e",
+1687 => x"82cc3884",
+1688 => x"1608fc06",
+1689 => x"70793155",
+1690 => x"55738f24",
+1691 => x"bb3880d7",
+1692 => x"b00b80d7",
+1693 => x"bc0c80d7",
+1694 => x"b00b80d7",
+1695 => x"b80c8074",
+1696 => x"2480db38",
+1697 => x"74168411",
+1698 => x"08810784",
+1699 => x"120c53fe",
+1700 => x"b0398816",
+1701 => x"8c110857",
+1702 => x"5975792e",
+1703 => x"098106fe",
+1704 => x"82388214",
+1705 => x"59ffab39",
+1706 => x"77167881",
+1707 => x"0784180c",
+1708 => x"7080d7bc",
+1709 => x"0c7080d7",
+1710 => x"b80c80d7",
+1711 => x"b00b8c12",
+1712 => x"0c8c1108",
+1713 => x"88120c74",
+1714 => x"81078412",
+1715 => x"0c740574",
+1716 => x"710c5b7c",
+1717 => x"518bd63f",
+1718 => x"881654fd",
+1719 => x"ec3983ff",
+1720 => x"75278391",
+1721 => x"3874892a",
+1722 => x"75832a54",
+1723 => x"5473802e",
+1724 => x"bf387486",
+1725 => x"2ab80553",
+1726 => x"847427b4",
+1727 => x"3880db14",
+1728 => x"53947427",
+1729 => x"ab38748c",
+1730 => x"2a80ee05",
+1731 => x"5380d474",
+1732 => x"279e3874",
+1733 => x"8f2a80f7",
+1734 => x"055382d4",
+1735 => x"74279138",
+1736 => x"74922a80",
+1737 => x"fc05538a",
+1738 => x"d4742784",
+1739 => x"3880fe53",
+1740 => x"72101010",
+1741 => x"80d7a805",
+1742 => x"88110855",
+1743 => x"5773772e",
+1744 => x"868b3884",
+1745 => x"1408fc06",
+1746 => x"5b747b27",
+1747 => x"8d388814",
+1748 => x"08547377",
+1749 => x"2e098106",
+1750 => x"ea388c14",
+1751 => x"0880d7a8",
+1752 => x"0b840508",
+1753 => x"718c190c",
+1754 => x"7588190c",
+1755 => x"7788130c",
+1756 => x"5c57758c",
+1757 => x"150c7853",
+1758 => x"80792483",
+1759 => x"98387282",
+1760 => x"2c81712b",
+1761 => x"5656747b",
+1762 => x"2680ca38",
+1763 => x"7a750657",
+1764 => x"7682a338",
+1765 => x"78fc0684",
+1766 => x"05597410",
+1767 => x"707c0655",
+1768 => x"55738292",
+1769 => x"38841959",
+1770 => x"f13980d7",
+1771 => x"a80b8405",
+1772 => x"0879545b",
+1773 => x"788025c6",
+1774 => x"3882da39",
+1775 => x"74097b06",
+1776 => x"7080d7a8",
+1777 => x"0b84050c",
+1778 => x"5b741055",
+1779 => x"747b2685",
+1780 => x"387485bc",
+1781 => x"3880d7a8",
+1782 => x"0b880508",
+1783 => x"70841208",
+1784 => x"fc06707b",
+1785 => x"317b7226",
+1786 => x"8f722507",
+1787 => x"5d575c5c",
+1788 => x"5578802e",
+1789 => x"80d93879",
+1790 => x"1580d7a0",
+1791 => x"08199011",
+1792 => x"59545680",
+1793 => x"d79c08ff",
+1794 => x"2e8838a0",
+1795 => x"8f13e080",
+1796 => x"06577652",
+1797 => x"7c518996",
+1798 => x"3f800854",
+1799 => x"8008ff2e",
+1800 => x"90388008",
+1801 => x"762782a7",
+1802 => x"387480d7",
+1803 => x"a82e829f",
+1804 => x"3880d7a8",
+1805 => x"0b880508",
+1806 => x"55841508",
+1807 => x"fc067079",
+1808 => x"31797226",
+1809 => x"8f722507",
+1810 => x"5d555a7a",
+1811 => x"83f23877",
+1812 => x"81078416",
+1813 => x"0c771570",
+1814 => x"80d7a80b",
+1815 => x"88050c74",
+1816 => x"81078412",
+1817 => x"0c567c51",
+1818 => x"88c33f88",
+1819 => x"15547380",
+1820 => x"0c8e3d0d",
+1821 => x"0474832a",
+1822 => x"70545480",
+1823 => x"7424819b",
+1824 => x"3872822c",
+1825 => x"81712b80",
+1826 => x"d7ac0807",
+1827 => x"7080d7a8",
+1828 => x"0b84050c",
+1829 => x"75101010",
+1830 => x"80d7a805",
+1831 => x"88110871",
+1832 => x"8c1b0c70",
+1833 => x"881b0c79",
+1834 => x"88130c57",
+1835 => x"555c5575",
+1836 => x"8c150cfd",
+1837 => x"c1397879",
+1838 => x"10101080",
+1839 => x"d7a80570",
+1840 => x"565b5c8c",
+1841 => x"14085675",
+1842 => x"742ea338",
+1843 => x"841608fc",
+1844 => x"06707931",
+1845 => x"5853768f",
+1846 => x"2483f138",
+1847 => x"76802584",
+1848 => x"af388c16",
+1849 => x"08567574",
+1850 => x"2e098106",
+1851 => x"df388814",
+1852 => x"811a7083",
+1853 => x"06555a54",
+1854 => x"72c9387b",
+1855 => x"83065675",
+1856 => x"802efdb8",
+1857 => x"38ff1cf8",
+1858 => x"1b5b5c88",
+1859 => x"1a087a2e",
+1860 => x"ea38fdb5",
+1861 => x"39831953",
+1862 => x"fce43983",
+1863 => x"1470822c",
+1864 => x"81712b80",
+1865 => x"d7ac0807",
+1866 => x"7080d7a8",
+1867 => x"0b84050c",
+1868 => x"76101010",
+1869 => x"80d7a805",
+1870 => x"88110871",
+1871 => x"8c1c0c70",
+1872 => x"881c0c7a",
+1873 => x"88130c58",
+1874 => x"535d5653",
+1875 => x"fee13980",
+1876 => x"d6ec0817",
+1877 => x"59800876",
+1878 => x"2e818b38",
+1879 => x"80d79c08",
+1880 => x"ff2e848e",
+1881 => x"38737631",
+1882 => x"1980d6ec",
+1883 => x"0c738706",
+1884 => x"70565372",
+1885 => x"802e8838",
+1886 => x"88733170",
+1887 => x"15555576",
+1888 => x"149fff06",
+1889 => x"a0807131",
+1890 => x"1670547e",
+1891 => x"53515386",
+1892 => x"9d3f8008",
+1893 => x"568008ff",
+1894 => x"2e819e38",
+1895 => x"80d6ec08",
+1896 => x"137080d6",
+1897 => x"ec0c7475",
+1898 => x"80d7a80b",
+1899 => x"88050c77",
+1900 => x"76311581",
+1901 => x"07555659",
+1902 => x"7a80d7a8",
+1903 => x"2e83c038",
+1904 => x"798f2682",
+1905 => x"ef38810b",
+1906 => x"84150c84",
+1907 => x"1508fc06",
+1908 => x"70793179",
+1909 => x"72268f72",
+1910 => x"25075d55",
+1911 => x"5a7a802e",
+1912 => x"fced3880",
+1913 => x"db398008",
+1914 => x"9fff0655",
+1915 => x"74feed38",
+1916 => x"7880d6ec",
+1917 => x"0c80d7a8",
+1918 => x"0b880508",
+1919 => x"7a188107",
+1920 => x"84120c55",
+1921 => x"80d79808",
+1922 => x"79278638",
+1923 => x"7880d798",
+1924 => x"0c80d794",
+1925 => x"087927fc",
+1926 => x"a0387880",
+1927 => x"d7940c84",
+1928 => x"1508fc06",
+1929 => x"70793179",
+1930 => x"72268f72",
+1931 => x"25075d55",
+1932 => x"5a7a802e",
+1933 => x"fc993888",
+1934 => x"39807457",
+1935 => x"53fedd39",
+1936 => x"7c5184e9",
+1937 => x"3f800b80",
+1938 => x"0c8e3d0d",
+1939 => x"04807324",
+1940 => x"a5387282",
+1941 => x"2c81712b",
+1942 => x"80d7ac08",
+1943 => x"077080d7",
+1944 => x"a80b8405",
+1945 => x"0c5c5a76",
+1946 => x"8c170c73",
+1947 => x"88170c75",
+1948 => x"88180cf9",
+1949 => x"fd398313",
+1950 => x"70822c81",
+1951 => x"712b80d7",
+1952 => x"ac080770",
+1953 => x"80d7a80b",
+1954 => x"84050c5d",
+1955 => x"5b53d839",
+1956 => x"7a75065c",
+1957 => x"7bfc9f38",
+1958 => x"84197510",
+1959 => x"5659f139",
+1960 => x"ff178105",
+1961 => x"59f7ab39",
+1962 => x"8c150888",
+1963 => x"1608718c",
+1964 => x"120c8812",
+1965 => x"0c597515",
+1966 => x"84110881",
+1967 => x"0784120c",
+1968 => x"587c5183",
+1969 => x"e83f8815",
+1970 => x"54fba339",
+1971 => x"77167881",
+1972 => x"0784180c",
+1973 => x"8c170888",
+1974 => x"1808718c",
+1975 => x"120c8812",
+1976 => x"0c5c7080",
+1977 => x"d7bc0c70",
+1978 => x"80d7b80c",
+1979 => x"80d7b00b",
+1980 => x"8c120c8c",
+1981 => x"11088812",
+1982 => x"0c778107",
+1983 => x"84120c77",
+1984 => x"0577710c",
+1985 => x"557c5183",
+1986 => x"a43f8816",
+1987 => x"54f5ba39",
+1988 => x"72168411",
+1989 => x"08810784",
+1990 => x"120c588c",
+1991 => x"16088817",
+1992 => x"08718c12",
+1993 => x"0c88120c",
+1994 => x"577c5183",
+1995 => x"803f8816",
+1996 => x"54f59639",
+1997 => x"7284150c",
+1998 => x"f41af806",
+1999 => x"70841d08",
+2000 => x"81060784",
+2001 => x"1d0c701c",
+2002 => x"5556850b",
+2003 => x"84150c85",
+2004 => x"0b88150c",
+2005 => x"8f7627fd",
+2006 => x"ab38881b",
+2007 => x"527c51eb",
+2008 => x"e83f80d7",
+2009 => x"a80b8805",
+2010 => x"0880d6ec",
+2011 => x"085a55fd",
+2012 => x"93397880",
+2013 => x"d6ec0c73",
+2014 => x"80d79c0c",
+2015 => x"fbef3972",
+2016 => x"84150cfc",
+2017 => x"ff39fb3d",
+2018 => x"0d77707a",
+2019 => x"7c585553",
+2020 => x"568f7527",
+2021 => x"80e63872",
+2022 => x"76078306",
+2023 => x"517080dc",
+2024 => x"38757352",
+2025 => x"54707084",
+2026 => x"05520874",
+2027 => x"70840556",
+2028 => x"0c737170",
+2029 => x"84055308",
+2030 => x"71708405",
+2031 => x"530c7170",
+2032 => x"84055308",
+2033 => x"71708405",
+2034 => x"530c7170",
+2035 => x"84055308",
+2036 => x"71708405",
+2037 => x"530cf016",
+2038 => x"5654748f",
+2039 => x"26c73883",
+2040 => x"75279538",
+2041 => x"70708405",
+2042 => x"52087470",
+2043 => x"8405560c",
+2044 => x"fc155574",
+2045 => x"8326ed38",
+2046 => x"73715452",
+2047 => x"ff155170",
+2048 => x"ff2e9838",
+2049 => x"72708105",
+2050 => x"54337270",
+2051 => x"81055434",
+2052 => x"ff115170",
+2053 => x"ff2e0981",
+2054 => x"06ea3875",
+2055 => x"800c873d",
+2056 => x"0d04fb3d",
+2057 => x"0d777a71",
+2058 => x"028c05a3",
+2059 => x"05335854",
+2060 => x"54568373",
+2061 => x"2780d438",
+2062 => x"75830651",
+2063 => x"7080cc38",
+2064 => x"74882b75",
+2065 => x"07707190",
+2066 => x"2b075551",
+2067 => x"8f7327a7",
+2068 => x"38737270",
+2069 => x"8405540c",
+2070 => x"71747170",
+2071 => x"8405530c",
+2072 => x"74717084",
+2073 => x"05530c74",
+2074 => x"71708405",
+2075 => x"530cf014",
+2076 => x"5452728f",
+2077 => x"26db3883",
+2078 => x"73279038",
+2079 => x"73727084",
+2080 => x"05540cfc",
+2081 => x"13537283",
+2082 => x"26f238ff",
+2083 => x"135170ff",
+2084 => x"2e933874",
+2085 => x"72708105",
+2086 => x"5434ff11",
+2087 => x"5170ff2e",
+2088 => x"098106ef",
+2089 => x"3875800c",
+2090 => x"873d0d04",
+2091 => x"04047070",
+2092 => x"7070800b",
+2093 => x"80dfe40c",
+2094 => x"765184f3",
+2095 => x"3f800853",
+2096 => x"8008ff2e",
+2097 => x"89387280",
+2098 => x"0c505050",
+2099 => x"500480df",
+2100 => x"e4085473",
+2101 => x"802eef38",
+2102 => x"7574710c",
+2103 => x"5272800c",
+2104 => x"50505050",
+2105 => x"04f93d0d",
+2106 => x"797c557b",
+2107 => x"548e1122",
+2108 => x"70902b70",
+2109 => x"902c5557",
+2110 => x"80cfec08",
+2111 => x"53585683",
+2112 => x"f63f8008",
+2113 => x"57800b80",
+2114 => x"08249338",
+2115 => x"80d01608",
+2116 => x"80080580",
+2117 => x"d0170c76",
+2118 => x"800c893d",
+2119 => x"0d048c16",
+2120 => x"2283dfff",
+2121 => x"0655748c",
+2122 => x"17237680",
+2123 => x"0c893d0d",
+2124 => x"04fa3d0d",
+2125 => x"788c1122",
+2126 => x"70882a70",
+2127 => x"81065157",
+2128 => x"585674a9",
+2129 => x"388c1622",
+2130 => x"83dfff06",
+2131 => x"55748c17",
+2132 => x"237a5479",
+2133 => x"538e1622",
+2134 => x"70902b70",
+2135 => x"902c5456",
+2136 => x"80cfec08",
+2137 => x"525681b2",
+2138 => x"3f883d0d",
+2139 => x"04825480",
+2140 => x"538e1622",
+2141 => x"70902b70",
+2142 => x"902c5456",
+2143 => x"80cfec08",
+2144 => x"525782bb",
+2145 => x"3f8c1622",
+2146 => x"83dfff06",
+2147 => x"55748c17",
+2148 => x"237a5479",
+2149 => x"538e1622",
+2150 => x"70902b70",
+2151 => x"902c5456",
+2152 => x"80cfec08",
+2153 => x"525680f2",
+2154 => x"3f883d0d",
+2155 => x"04f93d0d",
+2156 => x"797c557b",
+2157 => x"548e1122",
+2158 => x"70902b70",
+2159 => x"902c5557",
+2160 => x"80cfec08",
+2161 => x"53585681",
+2162 => x"f63f8008",
+2163 => x"578008ff",
+2164 => x"2e99388c",
+2165 => x"1622a080",
+2166 => x"0755748c",
+2167 => x"17238008",
+2168 => x"80d0170c",
+2169 => x"76800c89",
+2170 => x"3d0d048c",
+2171 => x"162283df",
+2172 => x"ff065574",
+2173 => x"8c172376",
+2174 => x"800c893d",
+2175 => x"0d047070",
+2176 => x"70748e11",
+2177 => x"2270902b",
+2178 => x"70902c55",
+2179 => x"51515380",
+2180 => x"cfec0851",
+2181 => x"bd3f5050",
+2182 => x"5004fb3d",
+2183 => x"0d800b80",
+2184 => x"dfe40c7a",
+2185 => x"53795278",
+2186 => x"5182fc3f",
+2187 => x"80085580",
+2188 => x"08ff2e88",
+2189 => x"3874800c",
+2190 => x"873d0d04",
+2191 => x"80dfe408",
+2192 => x"5675802e",
+2193 => x"f0387776",
+2194 => x"710c5474",
+2195 => x"800c873d",
+2196 => x"0d047070",
+2197 => x"7070800b",
+2198 => x"80dfe40c",
+2199 => x"765184c9",
+2200 => x"3f800853",
+2201 => x"8008ff2e",
+2202 => x"89387280",
+2203 => x"0c505050",
+2204 => x"500480df",
+2205 => x"e4085473",
+2206 => x"802eef38",
+2207 => x"7574710c",
+2208 => x"5272800c",
+2209 => x"50505050",
+2210 => x"04fc3d0d",
+2211 => x"800b80df",
+2212 => x"e40c7852",
+2213 => x"775187b0",
+2214 => x"3f800854",
+2215 => x"8008ff2e",
+2216 => x"88387380",
+2217 => x"0c863d0d",
+2218 => x"0480dfe4",
+2219 => x"08557480",
+2220 => x"2ef03876",
+2221 => x"75710c53",
+2222 => x"73800c86",
+2223 => x"3d0d04fb",
+2224 => x"3d0d800b",
+2225 => x"80dfe40c",
+2226 => x"7a537952",
+2227 => x"7851848b",
+2228 => x"3f800855",
+2229 => x"8008ff2e",
+2230 => x"88387480",
+2231 => x"0c873d0d",
+2232 => x"0480dfe4",
+2233 => x"08567580",
+2234 => x"2ef03877",
+2235 => x"76710c54",
+2236 => x"74800c87",
+2237 => x"3d0d04fb",
+2238 => x"3d0d800b",
+2239 => x"80dfe40c",
+2240 => x"7a537952",
+2241 => x"78518293",
+2242 => x"3f800855",
+2243 => x"8008ff2e",
+2244 => x"88387480",
+2245 => x"0c873d0d",
+2246 => x"0480dfe4",
+2247 => x"08567580",
+2248 => x"2ef03877",
+2249 => x"76710c54",
+2250 => x"74800c87",
+2251 => x"3d0d0470",
+2252 => x"707080df",
+2253 => x"d8088938",
+2254 => x"80dfe80b",
+2255 => x"80dfd80c",
+2256 => x"80dfd808",
+2257 => x"75115252",
+2258 => x"ff537087",
+2259 => x"fb808026",
+2260 => x"88387080",
+2261 => x"dfd80c71",
+2262 => x"5372800c",
+2263 => x"50505004",
+2264 => x"fd3d0d80",
+2265 => x"0b80cfe0",
+2266 => x"08545472",
+2267 => x"812e9b38",
+2268 => x"7380dfdc",
+2269 => x"0cc2af3f",
+2270 => x"c1863f80",
+2271 => x"dfb05281",
+2272 => x"51c3ff3f",
+2273 => x"80085186",
+2274 => x"bf3f7280",
+2275 => x"dfdc0cc2",
+2276 => x"953fc0ec",
+2277 => x"3f80dfb0",
+2278 => x"528151c3",
+2279 => x"e53f8008",
+2280 => x"5186a53f",
+2281 => x"00ff39f5",
+2282 => x"3d0d7e60",
+2283 => x"80dfdc08",
+2284 => x"705b585b",
+2285 => x"5b7580c2",
+2286 => x"38777a25",
+2287 => x"a138771b",
+2288 => x"70337081",
+2289 => x"ff065858",
+2290 => x"59758a2e",
+2291 => x"98387681",
+2292 => x"ff0651c1",
+2293 => x"b03f8118",
+2294 => x"58797824",
+2295 => x"e1387980",
+2296 => x"0c8d3d0d",
+2297 => x"048d51c1",
+2298 => x"9c3f7833",
+2299 => x"7081ff06",
+2300 => x"5257c191",
+2301 => x"3f811858",
+2302 => x"e0397955",
+2303 => x"7a547d53",
+2304 => x"85528d3d",
+2305 => x"fc0551c0",
+2306 => x"b93f8008",
+2307 => x"5685b23f",
+2308 => x"7b80080c",
+2309 => x"75800c8d",
+2310 => x"3d0d04f6",
+2311 => x"3d0d7d7f",
+2312 => x"80dfdc08",
+2313 => x"705b585a",
+2314 => x"5a7580c1",
+2315 => x"38777925",
+2316 => x"b338c0ac",
+2317 => x"3f800881",
+2318 => x"ff06708d",
+2319 => x"32703070",
+2320 => x"9f2a5151",
+2321 => x"5757768a",
+2322 => x"2e80c438",
+2323 => x"75802ebf",
+2324 => x"38771a56",
+2325 => x"76763476",
+2326 => x"51c0aa3f",
+2327 => x"81185878",
+2328 => x"7824cf38",
+2329 => x"77567580",
+2330 => x"0c8c3d0d",
+2331 => x"04785579",
+2332 => x"547c5384",
+2333 => x"528c3dfc",
+2334 => x"0551ffbf",
+2335 => x"c53f8008",
+2336 => x"5684be3f",
+2337 => x"7a80080c",
+2338 => x"75800c8c",
+2339 => x"3d0d0477",
+2340 => x"1a598a79",
+2341 => x"34811858",
+2342 => x"8d51ffbf",
+2343 => x"e83f8a51",
+2344 => x"ffbfe23f",
+2345 => x"7756ffbe",
+2346 => x"39fb3d0d",
+2347 => x"80dfdc08",
+2348 => x"70565473",
+2349 => x"88387480",
+2350 => x"0c873d0d",
+2351 => x"04775383",
+2352 => x"52873dfc",
+2353 => x"0551ffbe",
+2354 => x"f93f8008",
+2355 => x"5483f23f",
+2356 => x"7580080c",
+2357 => x"73800c87",
+2358 => x"3d0d04fa",
+2359 => x"3d0d80df",
+2360 => x"dc08802e",
+2361 => x"a3387a55",
+2362 => x"79547853",
+2363 => x"8652883d",
+2364 => x"fc0551ff",
+2365 => x"becc3f80",
+2366 => x"085683c5",
+2367 => x"3f768008",
+2368 => x"0c75800c",
+2369 => x"883d0d04",
+2370 => x"83b73f9d",
+2371 => x"0b80080c",
+2372 => x"ff0b800c",
+2373 => x"883d0d04",
+2374 => x"f73d0d7b",
+2375 => x"7d5b59bc",
+2376 => x"53805279",
+2377 => x"51f5fb3f",
+2378 => x"80705657",
+2379 => x"98567419",
+2380 => x"70337078",
+2381 => x"2b790781",
+2382 => x"18f81a5a",
+2383 => x"58595558",
+2384 => x"847524ea",
+2385 => x"38767a23",
+2386 => x"84195880",
+2387 => x"70565798",
+2388 => x"56741870",
+2389 => x"3370782b",
+2390 => x"79078118",
+2391 => x"f81a5a58",
+2392 => x"59515484",
+2393 => x"7524ea38",
+2394 => x"76821b23",
+2395 => x"88195880",
+2396 => x"70565798",
+2397 => x"56741870",
+2398 => x"3370782b",
+2399 => x"79078118",
+2400 => x"f81a5a58",
+2401 => x"59515484",
+2402 => x"7524ea38",
+2403 => x"76841b0c",
+2404 => x"8c195880",
+2405 => x"70565798",
+2406 => x"56741870",
+2407 => x"3370782b",
+2408 => x"79078118",
+2409 => x"f81a5a58",
+2410 => x"59515484",
+2411 => x"7524ea38",
+2412 => x"76881b23",
+2413 => x"90195880",
+2414 => x"70565798",
+2415 => x"56741870",
+2416 => x"3370782b",
+2417 => x"79078118",
+2418 => x"f81a5a58",
+2419 => x"59515484",
+2420 => x"7524ea38",
+2421 => x"768a1b23",
+2422 => x"94195880",
+2423 => x"70565798",
+2424 => x"56741870",
+2425 => x"3370782b",
+2426 => x"79078118",
+2427 => x"f81a5a58",
+2428 => x"59515484",
+2429 => x"7524ea38",
+2430 => x"768c1b23",
+2431 => x"98195880",
+2432 => x"70565798",
+2433 => x"56741870",
+2434 => x"3370782b",
+2435 => x"79078118",
+2436 => x"f81a5a58",
+2437 => x"59515484",
+2438 => x"7524ea38",
+2439 => x"768e1b23",
+2440 => x"9c195880",
+2441 => x"705657b8",
+2442 => x"56741870",
+2443 => x"3370782b",
+2444 => x"79078118",
+2445 => x"f81a5a58",
+2446 => x"595a5488",
+2447 => x"7524ea38",
+2448 => x"76901b0c",
+2449 => x"8b3d0d04",
+2450 => x"e93d0d6a",
+2451 => x"80dfdc08",
+2452 => x"57577593",
+2453 => x"3880c080",
+2454 => x"0b84180c",
+2455 => x"75ac180c",
+2456 => x"75800c99",
+2457 => x"3d0d0489",
+2458 => x"3d70556a",
+2459 => x"54558a52",
+2460 => x"993dffbc",
+2461 => x"0551ffbb",
+2462 => x"c93f8008",
+2463 => x"77537552",
+2464 => x"56fd953f",
+2465 => x"bc3f7780",
+2466 => x"080c7580",
+2467 => x"0c993d0d",
+2468 => x"04fc3d0d",
+2469 => x"815480df",
+2470 => x"dc088838",
+2471 => x"73800c86",
+2472 => x"3d0d0476",
+2473 => x"5397b952",
+2474 => x"863dfc05",
+2475 => x"51ffbb92",
+2476 => x"3f800854",
+2477 => x"8c3f7480",
+2478 => x"080c7380",
+2479 => x"0c863d0d",
+2480 => x"0480cfec",
+2481 => x"08800c04",
+2482 => x"f73d0d7b",
+2483 => x"80cfec08",
+2484 => x"82c81108",
+2485 => x"5a545a77",
+2486 => x"802e80da",
+2487 => x"38818818",
+2488 => x"841908ff",
+2489 => x"0581712b",
+2490 => x"59555980",
+2491 => x"742480ea",
+2492 => x"38807424",
+2493 => x"b5387382",
+2494 => x"2b781188",
+2495 => x"05565681",
+2496 => x"80190877",
+2497 => x"06537280",
+2498 => x"2eb63878",
+2499 => x"16700853",
+2500 => x"53795174",
+2501 => x"0853722d",
+2502 => x"ff14fc17",
+2503 => x"fc177981",
+2504 => x"2c5a5757",
+2505 => x"54738025",
+2506 => x"d6387708",
+2507 => x"5877ffad",
+2508 => x"3880cfec",
+2509 => x"0853bc13",
+2510 => x"08a53879",
+2511 => x"51f8e53f",
+2512 => x"74085372",
+2513 => x"2dff14fc",
+2514 => x"17fc1779",
+2515 => x"812c5a57",
+2516 => x"57547380",
+2517 => x"25ffa838",
+2518 => x"d1398057",
+2519 => x"ff933972",
+2520 => x"51bc1308",
+2521 => x"54732d79",
+2522 => x"51f8b93f",
+2523 => x"707080df",
+2524 => x"b80bfc05",
+2525 => x"70085252",
+2526 => x"70ff2e91",
+2527 => x"38702dfc",
+2528 => x"12700852",
+2529 => x"5270ff2e",
+2530 => x"098106f1",
+2531 => x"38505004",
+2532 => x"04ffbaff",
+2533 => x"3f040000",
+2534 => x"00000040",
+2535 => x"476f7420",
+2536 => x"696e7465",
+2537 => x"72727570",
+2538 => x"740a0000",
+2539 => x"4e6f2069",
+2540 => x"6e746572",
+2541 => x"72757074",
+2542 => x"0a000000",
+2543 => x"43000000",
+2544 => x"64756d6d",
+2545 => x"792e6578",
+2546 => x"65000000",
+2547 => x"00ffffff",
+2548 => x"ff00ffff",
+2549 => x"ffff00ff",
+2550 => x"ffffff00",
+2551 => x"00000000",
+2552 => x"00000000",
+2553 => x"00000000",
+2554 => x"00002fc0",
+2555 => x"000027f0",
+2556 => x"00000000",
+2557 => x"00002a58",
+2558 => x"00002ab4",
+2559 => x"00002b10",
+2560 => x"00000000",
+2561 => x"00000000",
+2562 => x"00000000",
+2563 => x"00000000",
+2564 => x"00000000",
+2565 => x"00000000",
+2566 => x"00000000",
+2567 => x"00000000",
+2568 => x"00000000",
+2569 => x"000027bc",
+2570 => x"00000000",
+2571 => x"00000000",
+2572 => x"00000000",
+2573 => x"00000000",
+2574 => x"00000000",
+2575 => x"00000000",
+2576 => x"00000000",
+2577 => x"00000000",
+2578 => x"00000000",
+2579 => x"00000000",
+2580 => x"00000000",
+2581 => x"00000000",
+2582 => x"00000000",
+2583 => x"00000000",
+2584 => x"00000000",
+2585 => x"00000000",
+2586 => x"00000000",
+2587 => x"00000000",
+2588 => x"00000000",
+2589 => x"00000000",
+2590 => x"00000000",
+2591 => x"00000000",
+2592 => x"00000000",
+2593 => x"00000000",
+2594 => x"00000000",
+2595 => x"00000000",
+2596 => x"00000000",
+2597 => x"00000000",
+2598 => x"00000001",
+2599 => x"330eabcd",
+2600 => x"1234e66d",
+2601 => x"deec0005",
+2602 => x"000b0000",
+2603 => x"00000000",
+2604 => x"00000000",
+2605 => x"00000000",
+2606 => x"00000000",
+2607 => x"00000000",
+2608 => x"00000000",
+2609 => x"00000000",
+2610 => x"00000000",
+2611 => x"00000000",
+2612 => x"00000000",
+2613 => x"00000000",
+2614 => x"00000000",
+2615 => x"00000000",
+2616 => x"00000000",
+2617 => x"00000000",
+2618 => x"00000000",
+2619 => x"00000000",
+2620 => x"00000000",
+2621 => x"00000000",
+2622 => x"00000000",
+2623 => x"00000000",
+2624 => x"00000000",
+2625 => x"00000000",
+2626 => x"00000000",
+2627 => x"00000000",
+2628 => x"00000000",
+2629 => x"00000000",
+2630 => x"00000000",
+2631 => x"00000000",
+2632 => x"00000000",
+2633 => x"00000000",
+2634 => x"00000000",
+2635 => x"00000000",
+2636 => x"00000000",
+2637 => x"00000000",
+2638 => x"00000000",
+2639 => x"00000000",
+2640 => x"00000000",
+2641 => x"00000000",
+2642 => x"00000000",
+2643 => x"00000000",
+2644 => x"00000000",
+2645 => x"00000000",
+2646 => x"00000000",
+2647 => x"00000000",
+2648 => x"00000000",
+2649 => x"00000000",
+2650 => x"00000000",
+2651 => x"00000000",
+2652 => x"00000000",
+2653 => x"00000000",
+2654 => x"00000000",
+2655 => x"00000000",
+2656 => x"00000000",
+2657 => x"00000000",
+2658 => x"00000000",
+2659 => x"00000000",
+2660 => x"00000000",
+2661 => x"00000000",
+2662 => x"00000000",
+2663 => x"00000000",
+2664 => x"00000000",
+2665 => x"00000000",
+2666 => x"00000000",
+2667 => x"00000000",
+2668 => x"00000000",
+2669 => x"00000000",
+2670 => x"00000000",
+2671 => x"00000000",
+2672 => x"00000000",
+2673 => x"00000000",
+2674 => x"00000000",
+2675 => x"00000000",
+2676 => x"00000000",
+2677 => x"00000000",
+2678 => x"00000000",
+2679 => x"00000000",
+2680 => x"00000000",
+2681 => x"00000000",
+2682 => x"00000000",
+2683 => x"00000000",
+2684 => x"00000000",
+2685 => x"00000000",
+2686 => x"00000000",
+2687 => x"00000000",
+2688 => x"00000000",
+2689 => x"00000000",
+2690 => x"00000000",
+2691 => x"00000000",
+2692 => x"00000000",
+2693 => x"00000000",
+2694 => x"00000000",
+2695 => x"00000000",
+2696 => x"00000000",
+2697 => x"00000000",
+2698 => x"00000000",
+2699 => x"00000000",
+2700 => x"00000000",
+2701 => x"00000000",
+2702 => x"00000000",
+2703 => x"00000000",
+2704 => x"00000000",
+2705 => x"00000000",
+2706 => x"00000000",
+2707 => x"00000000",
+2708 => x"00000000",
+2709 => x"00000000",
+2710 => x"00000000",
+2711 => x"00000000",
+2712 => x"00000000",
+2713 => x"00000000",
+2714 => x"00000000",
+2715 => x"00000000",
+2716 => x"00000000",
+2717 => x"00000000",
+2718 => x"00000000",
+2719 => x"00000000",
+2720 => x"00000000",
+2721 => x"00000000",
+2722 => x"00000000",
+2723 => x"00000000",
+2724 => x"00000000",
+2725 => x"00000000",
+2726 => x"00000000",
+2727 => x"00000000",
+2728 => x"00000000",
+2729 => x"00000000",
+2730 => x"00000000",
+2731 => x"00000000",
+2732 => x"00000000",
+2733 => x"00000000",
+2734 => x"00000000",
+2735 => x"00000000",
+2736 => x"00000000",
+2737 => x"00000000",
+2738 => x"00000000",
+2739 => x"00000000",
+2740 => x"00000000",
+2741 => x"00000000",
+2742 => x"00000000",
+2743 => x"00000000",
+2744 => x"00000000",
+2745 => x"00000000",
+2746 => x"00000000",
+2747 => x"00000000",
+2748 => x"00000000",
+2749 => x"00000000",
+2750 => x"00000000",
+2751 => x"00000000",
+2752 => x"00000000",
+2753 => x"00000000",
+2754 => x"00000000",
+2755 => x"00000000",
+2756 => x"00000000",
+2757 => x"00000000",
+2758 => x"00000000",
+2759 => x"00000000",
+2760 => x"00000000",
+2761 => x"00000000",
+2762 => x"00000000",
+2763 => x"00000000",
+2764 => x"00000000",
+2765 => x"00000000",
+2766 => x"00000000",
+2767 => x"00000000",
+2768 => x"00000000",
+2769 => x"00000000",
+2770 => x"00000000",
+2771 => x"00000000",
+2772 => x"00000000",
+2773 => x"00000000",
+2774 => x"00000000",
+2775 => x"00000000",
+2776 => x"00000000",
+2777 => x"00000000",
+2778 => x"00000000",
+2779 => x"00000000",
+2780 => x"00000000",
+2781 => x"00000000",
+2782 => x"00000000",
+2783 => x"00000000",
+2784 => x"00000000",
+2785 => x"00000000",
+2786 => x"00000000",
+2787 => x"00000000",
+2788 => x"00000000",
+2789 => x"00000000",
+2790 => x"00000000",
+2791 => x"ffffffff",
+2792 => x"00000000",
+2793 => x"00020000",
+2794 => x"00000000",
+2795 => x"00000000",
+2796 => x"00002ba8",
+2797 => x"00002ba8",
+2798 => x"00002bb0",
+2799 => x"00002bb0",
+2800 => x"00002bb8",
+2801 => x"00002bb8",
+2802 => x"00002bc0",
+2803 => x"00002bc0",
+2804 => x"00002bc8",
+2805 => x"00002bc8",
+2806 => x"00002bd0",
+2807 => x"00002bd0",
+2808 => x"00002bd8",
+2809 => x"00002bd8",
+2810 => x"00002be0",
+2811 => x"00002be0",
+2812 => x"00002be8",
+2813 => x"00002be8",
+2814 => x"00002bf0",
+2815 => x"00002bf0",
+2816 => x"00002bf8",
+2817 => x"00002bf8",
+2818 => x"00002c00",
+2819 => x"00002c00",
+2820 => x"00002c08",
+2821 => x"00002c08",
+2822 => x"00002c10",
+2823 => x"00002c10",
+2824 => x"00002c18",
+2825 => x"00002c18",
+2826 => x"00002c20",
+2827 => x"00002c20",
+2828 => x"00002c28",
+2829 => x"00002c28",
+2830 => x"00002c30",
+2831 => x"00002c30",
+2832 => x"00002c38",
+2833 => x"00002c38",
+2834 => x"00002c40",
+2835 => x"00002c40",
+2836 => x"00002c48",
+2837 => x"00002c48",
+2838 => x"00002c50",
+2839 => x"00002c50",
+2840 => x"00002c58",
+2841 => x"00002c58",
+2842 => x"00002c60",
+2843 => x"00002c60",
+2844 => x"00002c68",
+2845 => x"00002c68",
+2846 => x"00002c70",
+2847 => x"00002c70",
+2848 => x"00002c78",
+2849 => x"00002c78",
+2850 => x"00002c80",
+2851 => x"00002c80",
+2852 => x"00002c88",
+2853 => x"00002c88",
+2854 => x"00002c90",
+2855 => x"00002c90",
+2856 => x"00002c98",
+2857 => x"00002c98",
+2858 => x"00002ca0",
+2859 => x"00002ca0",
+2860 => x"00002ca8",
+2861 => x"00002ca8",
+2862 => x"00002cb0",
+2863 => x"00002cb0",
+2864 => x"00002cb8",
+2865 => x"00002cb8",
+2866 => x"00002cc0",
+2867 => x"00002cc0",
+2868 => x"00002cc8",
+2869 => x"00002cc8",
+2870 => x"00002cd0",
+2871 => x"00002cd0",
+2872 => x"00002cd8",
+2873 => x"00002cd8",
+2874 => x"00002ce0",
+2875 => x"00002ce0",
+2876 => x"00002ce8",
+2877 => x"00002ce8",
+2878 => x"00002cf0",
+2879 => x"00002cf0",
+2880 => x"00002cf8",
+2881 => x"00002cf8",
+2882 => x"00002d00",
+2883 => x"00002d00",
+2884 => x"00002d08",
+2885 => x"00002d08",
+2886 => x"00002d10",
+2887 => x"00002d10",
+2888 => x"00002d18",
+2889 => x"00002d18",
+2890 => x"00002d20",
+2891 => x"00002d20",
+2892 => x"00002d28",
+2893 => x"00002d28",
+2894 => x"00002d30",
+2895 => x"00002d30",
+2896 => x"00002d38",
+2897 => x"00002d38",
+2898 => x"00002d40",
+2899 => x"00002d40",
+2900 => x"00002d48",
+2901 => x"00002d48",
+2902 => x"00002d50",
+2903 => x"00002d50",
+2904 => x"00002d58",
+2905 => x"00002d58",
+2906 => x"00002d60",
+2907 => x"00002d60",
+2908 => x"00002d68",
+2909 => x"00002d68",
+2910 => x"00002d70",
+2911 => x"00002d70",
+2912 => x"00002d78",
+2913 => x"00002d78",
+2914 => x"00002d80",
+2915 => x"00002d80",
+2916 => x"00002d88",
+2917 => x"00002d88",
+2918 => x"00002d90",
+2919 => x"00002d90",
+2920 => x"00002d98",
+2921 => x"00002d98",
+2922 => x"00002da0",
+2923 => x"00002da0",
+2924 => x"00002da8",
+2925 => x"00002da8",
+2926 => x"00002db0",
+2927 => x"00002db0",
+2928 => x"00002db8",
+2929 => x"00002db8",
+2930 => x"00002dc0",
+2931 => x"00002dc0",
+2932 => x"00002dc8",
+2933 => x"00002dc8",
+2934 => x"00002dd0",
+2935 => x"00002dd0",
+2936 => x"00002dd8",
+2937 => x"00002dd8",
+2938 => x"00002de0",
+2939 => x"00002de0",
+2940 => x"00002de8",
+2941 => x"00002de8",
+2942 => x"00002df0",
+2943 => x"00002df0",
+2944 => x"00002df8",
+2945 => x"00002df8",
+2946 => x"00002e00",
+2947 => x"00002e00",
+2948 => x"00002e08",
+2949 => x"00002e08",
+2950 => x"00002e10",
+2951 => x"00002e10",
+2952 => x"00002e18",
+2953 => x"00002e18",
+2954 => x"00002e20",
+2955 => x"00002e20",
+2956 => x"00002e28",
+2957 => x"00002e28",
+2958 => x"00002e30",
+2959 => x"00002e30",
+2960 => x"00002e38",
+2961 => x"00002e38",
+2962 => x"00002e40",
+2963 => x"00002e40",
+2964 => x"00002e48",
+2965 => x"00002e48",
+2966 => x"00002e50",
+2967 => x"00002e50",
+2968 => x"00002e58",
+2969 => x"00002e58",
+2970 => x"00002e60",
+2971 => x"00002e60",
+2972 => x"00002e68",
+2973 => x"00002e68",
+2974 => x"00002e70",
+2975 => x"00002e70",
+2976 => x"00002e78",
+2977 => x"00002e78",
+2978 => x"00002e80",
+2979 => x"00002e80",
+2980 => x"00002e88",
+2981 => x"00002e88",
+2982 => x"00002e90",
+2983 => x"00002e90",
+2984 => x"00002e98",
+2985 => x"00002e98",
+2986 => x"00002ea0",
+2987 => x"00002ea0",
+2988 => x"00002ea8",
+2989 => x"00002ea8",
+2990 => x"00002eb0",
+2991 => x"00002eb0",
+2992 => x"00002eb8",
+2993 => x"00002eb8",
+2994 => x"00002ec0",
+2995 => x"00002ec0",
+2996 => x"00002ec8",
+2997 => x"00002ec8",
+2998 => x"00002ed0",
+2999 => x"00002ed0",
+3000 => x"00002ed8",
+3001 => x"00002ed8",
+3002 => x"00002ee0",
+3003 => x"00002ee0",
+3004 => x"00002ee8",
+3005 => x"00002ee8",
+3006 => x"00002ef0",
+3007 => x"00002ef0",
+3008 => x"00002ef8",
+3009 => x"00002ef8",
+3010 => x"00002f00",
+3011 => x"00002f00",
+3012 => x"00002f08",
+3013 => x"00002f08",
+3014 => x"00002f10",
+3015 => x"00002f10",
+3016 => x"00002f18",
+3017 => x"00002f18",
+3018 => x"00002f20",
+3019 => x"00002f20",
+3020 => x"00002f28",
+3021 => x"00002f28",
+3022 => x"00002f30",
+3023 => x"00002f30",
+3024 => x"00002f38",
+3025 => x"00002f38",
+3026 => x"00002f40",
+3027 => x"00002f40",
+3028 => x"00002f48",
+3029 => x"00002f48",
+3030 => x"00002f50",
+3031 => x"00002f50",
+3032 => x"00002f58",
+3033 => x"00002f58",
+3034 => x"00002f60",
+3035 => x"00002f60",
+3036 => x"00002f68",
+3037 => x"00002f68",
+3038 => x"00002f70",
+3039 => x"00002f70",
+3040 => x"00002f78",
+3041 => x"00002f78",
+3042 => x"00002f80",
+3043 => x"00002f80",
+3044 => x"00002f88",
+3045 => x"00002f88",
+3046 => x"00002f90",
+3047 => x"00002f90",
+3048 => x"00002f98",
+3049 => x"00002f98",
+3050 => x"00002fa0",
+3051 => x"00002fa0",
+3052 => x"000027c0",
+3053 => x"ffffffff",
+3054 => x"00000000",
+3055 => x"ffffffff",
+3056 => x"00000000",
+ others => x"00000000"
+);
+
+begin
+
+process (clk)
+begin
+ if (clk'event and clk = '1') then
+ if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then
+ report "write collision" severity failure;
+ end if;
+
+ if (memAWriteEnable = '1') then
+ ram(to_integer(unsigned(memAAddr))) := memAWrite;
+ memARead <= memAWrite;
+ else
+ memARead <= ram(to_integer(unsigned(memAAddr)));
+ end if;
+ end if;
+end process;
+
+process (clk)
+begin
+ if (clk'event and clk = '1') then
+ if (memBWriteEnable = '1') then
+ ram(to_integer(unsigned(memBAddr))) := memBWrite;
+ memBRead <= memBWrite;
+ else
+ memBRead <= ram(to_integer(unsigned(memBAddr)));
+ end if;
+ end if;
+end process;
+
+
+
+
+end dualport_ram_arch;
diff --git a/zpu/hdl/example/log.txt b/zpu/hdl/example/log.txt
new file mode 100644
index 0000000..6ee1d94
--- /dev/null
+++ b/zpu/hdl/example/log.txt
@@ -0,0 +1,20 @@
+Hello world 1
+
+Hello world 2
+
+Hello world 1
+
+Hello world 2
+
+Hello world 1
+
+Hello world 2
+
+Hello world 1
+
+Hello world 2
+
+Hello world 1
+
+Hello world 2
+
diff --git a/zpu/hdl/example/sim_small_fpga_top.vhd b/zpu/hdl/example/sim_small_fpga_top.vhd
new file mode 100644
index 0000000..909ea21
--- /dev/null
+++ b/zpu/hdl/example/sim_small_fpga_top.vhd
@@ -0,0 +1,197 @@
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+--
+-- The FreeBSD license
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+--
+-- 1. Redistributions of source code must retain the above copyright
+-- notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+-- copyright notice, this list of conditions and the following
+-- disclaimer in the documentation and/or other materials
+-- provided with the distribution.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+
+entity fpga_top is
+end fpga_top;
+
+
+architecture behave of fpga_top is
+
+
+ signal clk : std_logic;
+
+ signal areset : std_logic := '1';
+
+
+ component zpu_io is
+ generic (
+ log_file: string := "log.txt"
+ );
+ port (
+ clk : in std_logic;
+ areset : in std_logic;
+ busy : out std_logic;
+ writeEnable : in std_logic;
+ readEnable : in std_logic;
+ write : in std_logic_vector(wordSize-1 downto 0);
+ read : out std_logic_vector(wordSize-1 downto 0);
+ addr : in std_logic_vector(maxAddrBit downto minAddrBit)
+ );
+ end component;
+
+
+ signal mem_busy : std_logic;
+ signal mem_read : std_logic_vector(wordSize-1 downto 0);
+ signal mem_write : std_logic_vector(wordSize-1 downto 0);
+ signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);
+ signal mem_writeEnable : std_logic;
+ signal mem_readEnable : std_logic;
+ signal mem_writeMask : std_logic_vector(wordBytes-1 downto 0);
+
+ signal enable : std_logic;
+
+ signal dram_mem_busy : std_logic;
+ signal dram_mem_read : std_logic_vector(wordSize-1 downto 0);
+ signal dram_mem_write : std_logic_vector(wordSize-1 downto 0);
+ signal dram_mem_writeEnable : std_logic;
+ signal dram_mem_readEnable : std_logic;
+ signal dram_mem_writeMask : std_logic_vector(wordBytes-1 downto 0);
+
+ signal io_busy : std_logic;
+
+ signal io_mem_read : std_logic_vector(wordSize-1 downto 0);
+ signal io_mem_writeEnable : std_logic;
+ signal io_mem_readEnable : std_logic;
+
+ signal dram_ready : std_logic;
+ signal io_ready : std_logic;
+ signal io_reading : std_logic;
+ signal interruptcounter : unsigned(15 downto 0);
+ signal interrupt : std_logic;
+
+ signal break : std_logic;
+
+begin
+
+ zpu: zpu_core
+ port map (
+ clk => clk,
+ reset => areset,
+ enable => enable,
+ in_mem_busy => mem_busy,
+ mem_read => mem_read,
+ mem_write => mem_write,
+ out_mem_addr => mem_addr,
+ out_mem_writeEnable => mem_writeEnable,
+ out_mem_readEnable => mem_readEnable,
+ mem_writeMask => mem_writeMask,
+ interrupt => interrupt,
+ break => break
+ );
+
+
+ ioMap: zpu_io
+ port map (
+ clk => clk,
+ areset => areset,
+ busy => io_busy,
+ writeEnable => io_mem_writeEnable,
+ readEnable => io_mem_readEnable,
+ write => mem_write,
+ read => io_mem_read,
+ addr => mem_addr(maxAddrBit downto minAddrBit)
+ );
+
+ dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit);
+ dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit);
+ io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit);
+ io_mem_readEnable <= mem_readEnable and mem_addr(ioBit);
+ mem_busy <= io_busy;
+
+
+ -- Memory reads either come from IO or DRAM. We need to pick the right one.
+ memorycontrol: process(dram_mem_read, dram_ready, io_ready, io_mem_read)
+ begin
+ mem_read <= (others => 'U');
+ if dram_ready='1' then
+ mem_read <= dram_mem_read;
+ end if;
+
+ if io_ready='1' then
+ mem_read <= (others => '0');
+ mem_read <= io_mem_read;
+ end if;
+ end process;
+
+
+ io_ready <= (io_reading or io_mem_readEnable) and not io_busy;
+
+ memoryControlSync: process(clk, areset)
+ begin
+ if areset = '1' then
+ enable <= '0';
+ io_reading <= '0';
+ dram_ready <= '0';
+
+ interruptcounter <= to_unsigned(0, 16);
+ interrupt <= '0';
+
+ elsif rising_edge(clk) then
+ enable <= '1';
+ io_reading <= io_busy or io_mem_readEnable;
+ dram_ready <= dram_mem_readEnable;
+
+ -- keep interrupt signal high for 16 cycles
+ interruptcounter <= interruptcounter + 1;
+ if (interruptcounter < 16) then
+ report "Interrupt asserted!" severity note;
+ interrupt <='1';
+ else
+ interrupt <='0';
+ end if;
+ end if;
+ end process;
+
+ -- wiggle the clock @ 100MHz
+ clock: process
+ begin
+ clk <= '0';
+ wait for 5 ns;
+ clk <= '1';
+ wait for 5 ns;
+ areset <= '0';
+ end process clock;
+
+
+end architecture behave;
diff --git a/zpu/hdl/example/sim_small_fpga_top_noint.vhd b/zpu/hdl/example/sim_small_fpga_top_noint.vhd
new file mode 100644
index 0000000..23b92cc
--- /dev/null
+++ b/zpu/hdl/example/sim_small_fpga_top_noint.vhd
@@ -0,0 +1,184 @@
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+--
+-- The FreeBSD license
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+--
+-- 1. Redistributions of source code must retain the above copyright
+-- notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+-- copyright notice, this list of conditions and the following
+-- disclaimer in the documentation and/or other materials
+-- provided with the distribution.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+
+entity fpga_top is
+end fpga_top;
+
+
+architecture behave of fpga_top is
+
+
+ signal clk : std_logic;
+
+ signal areset : std_logic := '1';
+
+
+ component zpu_io is
+ generic (
+ log_file: string := "log.txt"
+ );
+ port (
+ clk : in std_logic;
+ areset : in std_logic;
+ busy : out std_logic;
+ writeEnable : in std_logic;
+ readEnable : in std_logic;
+ write : in std_logic_vector(wordSize-1 downto 0);
+ read : out std_logic_vector(wordSize-1 downto 0);
+ addr : in std_logic_vector(maxAddrBit downto minAddrBit)
+ );
+ end component;
+
+
+ signal mem_busy : std_logic;
+ signal mem_read : std_logic_vector(wordSize-1 downto 0);
+ signal mem_write : std_logic_vector(wordSize-1 downto 0);
+ signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);
+ signal mem_writeEnable : std_logic;
+ signal mem_readEnable : std_logic;
+ signal mem_writeMask : std_logic_vector(wordBytes-1 downto 0);
+
+ signal enable : std_logic;
+
+ signal dram_mem_busy : std_logic;
+ signal dram_mem_read : std_logic_vector(wordSize-1 downto 0);
+ signal dram_mem_write : std_logic_vector(wordSize-1 downto 0);
+ signal dram_mem_writeEnable : std_logic;
+ signal dram_mem_readEnable : std_logic;
+ signal dram_mem_writeMask : std_logic_vector(wordBytes-1 downto 0);
+
+ signal io_busy : std_logic;
+
+ signal io_mem_read : std_logic_vector(wordSize-1 downto 0);
+ signal io_mem_writeEnable : std_logic;
+ signal io_mem_readEnable : std_logic;
+
+ signal dram_ready : std_logic;
+ signal io_ready : std_logic;
+ signal io_reading : std_logic;
+
+ signal break : std_logic;
+
+
+begin
+
+ zpu: zpu_core
+ port map (
+ clk => clk,
+ reset => areset,
+ enable => enable,
+ in_mem_busy => mem_busy,
+ mem_read => mem_read,
+ mem_write => mem_write,
+ out_mem_addr => mem_addr,
+ out_mem_writeEnable => mem_writeEnable,
+ out_mem_readEnable => mem_readEnable,
+ mem_writeMask => mem_writeMask,
+ interrupt => '0',
+ break => break
+ );
+
+
+ ioMap: zpu_io
+ port map (
+ clk => clk,
+ areset => areset,
+ busy => io_busy,
+ writeEnable => io_mem_writeEnable,
+ readEnable => io_mem_readEnable,
+ write => mem_write,
+ read => io_mem_read,
+ addr => mem_addr(maxAddrBit downto minAddrBit)
+ );
+
+ dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit);
+ dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit);
+ io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit);
+ io_mem_readEnable <= mem_readEnable and mem_addr(ioBit);
+ mem_busy <= io_busy;
+
+
+ -- Memory reads either come from IO or DRAM. We need to pick the right one.
+ memorycontrol: process(dram_mem_read, dram_ready, io_ready, io_mem_read)
+ begin
+ mem_read <= (others => 'U');
+ if dram_ready='1' then
+ mem_read <= dram_mem_read;
+ end if;
+
+ if io_ready='1' then
+ mem_read <= (others => '0');
+ mem_read <= io_mem_read;
+ end if;
+ end process;
+
+
+
+ io_ready <= (io_reading or io_mem_readEnable) and not io_busy;
+
+ memoryControlSync: process(clk, areset)
+ begin
+ if areset = '1' then
+ enable <= '0';
+ io_reading <= '0';
+ dram_ready <= '0';
+
+ elsif rising_edge(clk) then
+ enable <= '1';
+ io_reading <= io_busy or io_mem_readEnable;
+ dram_ready <= dram_mem_readEnable;
+ end if;
+ end process;
+
+ -- wiggle the clock @ 100MHz
+ clock: process
+ begin
+ clk <= '0';
+ wait for 5 ns;
+ clk <= '1';
+ wait for 5 ns;
+ areset <= '0';
+ end process clock;
+
+
+end architecture behave;
diff --git a/zpu/hdl/example/simzpu_dmips.do b/zpu/hdl/example/simzpu_dmips.do
new file mode 100644
index 0000000..883259e
--- /dev/null
+++ b/zpu/hdl/example/simzpu_dmips.do
@@ -0,0 +1,29 @@
+# Xilinx WebPack modelsim script
+#
+#
+# cd C:/workspace/zpu/zpu/hdl/example
+# do simzpu_dmips.do
+
+set BreakOnAssertion 1
+vlib work
+
+vcom -93 -explicit zpu_config.vhd
+vcom -93 -explicit ../zpu4/core/zpupkg.vhd
+vcom -93 -explicit ../zpu4/src/txt_util.vhd
+vcom -93 -explicit sim_small_fpga_top_noint.vhd
+vcom -93 -explicit ../zpu4/core/zpu_core_small.vhd
+vcom -93 -explicit bram_dmips.vhd
+vcom -93 -explicit ../zpu4/src/timer.vhd
+vcom -93 -explicit ../zpu4/src/io.vhd
+vcom -93 -explicit ../zpu4/src/trace.vhd
+
+# run ZPU
+vsim fpga_top
+view wave
+add wave -recursive fpga_top/zpu/*
+#add wave -recursive fpga_top/*
+view structure
+#view signals
+
+# Enough to run tiny programs
+run 10 ms
diff --git a/zpu/hdl/example/simzpu_interrupt.do b/zpu/hdl/example/simzpu_interrupt.do
new file mode 100644
index 0000000..864bf76
--- /dev/null
+++ b/zpu/hdl/example/simzpu_interrupt.do
@@ -0,0 +1,29 @@
+# Xilinx WebPack modelsim script
+#
+#
+# cd C:/workspace/zpu/zpu/hdl/example
+# do simzpu_interrupt.do
+
+set BreakOnAssertion 1
+vlib work
+
+vcom -93 -explicit zpu_config.vhd
+vcom -93 -explicit ../zpu4/core/zpupkg.vhd
+vcom -93 -explicit ../zpu4/src/txt_util.vhd
+vcom -93 -explicit sim_small_fpga_top.vhd
+vcom -93 -explicit ../zpu4/core/zpu_core_small.vhd
+vcom -93 -explicit interrupt.vhd
+vcom -93 -explicit ../zpu4/src/timer.vhd
+vcom -93 -explicit ../zpu4/src/io.vhd
+vcom -93 -explicit ../zpu4/src/trace.vhd
+
+# run ZPU
+vsim fpga_top
+view wave
+add wave -recursive fpga_top/zpu/*
+#add wave -recursive fpga_top/*
+view structure
+#view signals
+
+# Enough to run tiny programs
+run 10 ms
diff --git a/zpu/hdl/example/simzpu_small.do b/zpu/hdl/example/simzpu_small.do
new file mode 100644
index 0000000..2b64926
--- /dev/null
+++ b/zpu/hdl/example/simzpu_small.do
@@ -0,0 +1,29 @@
+# Xilinx WebPack modelsim script
+#
+#
+# cd C:/workspace/zpu/zpu/hdl/example
+# do simzpu_small.do
+
+set BreakOnAssertion 1
+vlib work
+
+vcom -93 -explicit zpu_config.vhd
+vcom -93 -explicit ../zpu4/core/zpupkg.vhd
+vcom -93 -explicit ../zpu4/src/txt_util.vhd
+vcom -93 -explicit sim_small_fpga_top_noint.vhd
+vcom -93 -explicit ../zpu4/core/zpu_core_small.vhd
+vcom -93 -explicit helloworld.vhd
+vcom -93 -explicit ../zpu4/src/timer.vhd
+vcom -93 -explicit ../zpu4/src/io.vhd
+vcom -93 -explicit ../zpu4/src/trace.vhd
+
+# run ZPU
+vsim fpga_top
+view wave
+add wave -recursive fpga_top/zpu/*
+#add wave -recursive fpga_top/*
+view structure
+#view signals
+
+# Enough to run tiny programs
+run 10 ms
diff --git a/zpu/hdl/example/zpu_config.vhd b/zpu/hdl/example/zpu_config.vhd
new file mode 100644
index 0000000..cd4163d
--- /dev/null
+++ b/zpu/hdl/example/zpu_config.vhd
@@ -0,0 +1,55 @@
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+--
+-- The FreeBSD license
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+--
+-- 1. Redistributions of source code must retain the above copyright
+-- notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+-- copyright notice, this list of conditions and the following
+-- disclaimer in the documentation and/or other materials
+-- provided with the distribution.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package zpu_config is
+ -- generate trace output
+ constant Generate_Trace : boolean := true;
+ constant wordPower : integer := 5;
+ -- during simulation, set this to '0' to get matching trace.txt
+ constant DontCareValue : std_logic := '0';
+ -- Clock frequency in MHz.
+ constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64";
+ -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
+ constant maxAddrBitIncIO : integer := 27;
+ constant maxAddrBitBRAM : integer := 16;
+
+ -- start byte address of stack.
+ -- point to top of RAM - 2*words
+ constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) :=
+ std_logic_vector(to_unsigned((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1));
+end zpu_config;
diff --git a/zpu/hdl/example/zpuromgen.c b/zpu/hdl/example/zpuromgen.c
new file mode 100644
index 0000000..fb8c4ba
--- /dev/null
+++ b/zpu/hdl/example/zpuromgen.c
@@ -0,0 +1,59 @@
+// zpuromgen.c
+//
+// Program to turn a binary file into a VHDL lookup table.
+// by Adam Pierce
+// 29-Feb-2008
+//
+// This software is free to use by anyone for any purpose.
+//
+
+#include <unistd.h>
+#include <stdio.h>
+
+typedef uint8_t BYTE;
+
+main(int argc, char **argv)
+{
+ BYTE opcode[4];
+ int fd;
+ int addr = 0;
+ ssize_t s;
+
+// Check the user has given us an input file.
+ if(argc < 2)
+ {
+ printf("Usage: %s <binary_file>\n\n", argv[0]);
+ return 1;
+ }
+
+// Open the input file.
+ fd = open(argv[1], 0);
+ if(fd == -1)
+ {
+ perror("File Open");
+ return 2;
+ }
+
+ while(1)
+ {
+ // Read 32 bits.
+ s = read(fd, opcode, 4);
+ if(s == -1)
+ {
+ perror("File read");
+ return 3;
+ }
+
+ if(s == 0)
+ break; // End of file.
+
+ // Output to STDOUT.
+ printf("%6d => x\"%02x%02x%02x%02x\",\n",
+ addr++, opcode[0], opcode[1],
+ opcode[2], opcode[3]);
+ }
+
+ close(fd);
+ return 0;
+}
+
diff --git a/zpu/hdl/example/zpuromgen.exe b/zpu/hdl/example/zpuromgen.exe
new file mode 100644
index 0000000..6655412
--- /dev/null
+++ b/zpu/hdl/example/zpuromgen.exe
Binary files differ
diff --git a/zpu/hdl/example_ghdl/README b/zpu/hdl/example_ghdl/README
new file mode 100644
index 0000000..a098c0c
--- /dev/null
+++ b/zpu/hdl/example_ghdl/README
@@ -0,0 +1,44 @@
+This directory contains a quick setup of the helloworld example for
+the GHDL simulator.
+
+ http://ghdl.free.fr/
+
+Compiled by Arnim Laeuger, 17-Apr-2008.
+Removed ROC/unisim dependency 16-Jun-2008.
+
+Compiling the example
+---------------------
+
+Make all shell scripts executable:
+ $ chmod +x *.sh
+
+On Linux, convert files from DOS format:
+ $ dos2unix *.sh
+
+You need to import the project sources once by running
+ $ ./ghdl_import.sh
+
+Compilation (using GHDL's make feature) is invoked by
+ $ ./ghdl_make.sh
+
+Whenever the VHDL sources change, it's enough to execute ghdl_make.sh. GHDL
+will trace the dependencies and will rebuild only the modified sources.
+
+
+Simulation
+----------
+
+Simulation finally happens by running the fpga_top executable generated by the
+compilation step. Don't forget to set a stop time or the testbench might run
+forever:
+
+ $ ./fpga_top --stop-time=2100us
+
+The log.txt and trace.txt files are generated as simulation progresses. They
+should be compared to the files given in the example directory.
+
+Waveforms can be obtained by specifying the ghw file name:
+
+ $ ./fpga_top --stop-time=1ms --wave=zpu.ghw
+
+They can be inspected with gtkwave from http://home.nc.rr.com/gtkwave/.
diff --git a/zpu/hdl/example_ghdl/dmipssmalltrace_ghdl.sh b/zpu/hdl/example_ghdl/dmipssmalltrace_ghdl.sh
new file mode 100644
index 0000000..b3be1a6
--- /dev/null
+++ b/zpu/hdl/example_ghdl/dmipssmalltrace_ghdl.sh
@@ -0,0 +1,24 @@
+#!/bin/sh
+
+IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work"
+MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding"
+
+if test ! -e work; then
+ echo "Building work library..."
+ mkdir work
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/zpu_config.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpupkg.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/txt_util.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/sim_small_fpga_top.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpu_core_small.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/bram_dmips.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/timer.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/io.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/trace.vhd
+fi
+
+echo "Compiling design..."
+if ghdl -m ${MAKE_OPTIONS} fpga_top; then
+ echo "Compilation finished, start simulation with"
+ echo " ./fpga_top --stop-time=1ms"
+fi
diff --git a/zpu/hdl/example_ghdl/dmipstrace_ghdl.sh b/zpu/hdl/example_ghdl/dmipstrace_ghdl.sh
new file mode 100644
index 0000000..53474d4
--- /dev/null
+++ b/zpu/hdl/example_ghdl/dmipstrace_ghdl.sh
@@ -0,0 +1,24 @@
+#!/bin/sh
+
+IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work"
+MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding"
+
+if test ! -e work; then
+ echo "Building work library..."
+ mkdir work
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/example_medium/zpu_config_trace.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpupkg.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/txt_util.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/example_medium/sim_fpga_top.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpu_core.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/example_medium/dram_dmips.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/timer.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/io.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/trace.vhd
+fi
+
+echo "Compiling design..."
+if ghdl -m ${MAKE_OPTIONS} fpga_top; then
+ echo "Compilation finished, start simulation with"
+ echo " ./fpga_top --stop-time=2500us"
+fi
diff --git a/zpu/hdl/example_ghdl/ghdl_import.sh b/zpu/hdl/example_ghdl/ghdl_import.sh
new file mode 100644
index 0000000..b1c2713
--- /dev/null
+++ b/zpu/hdl/example_ghdl/ghdl_import.sh
@@ -0,0 +1,16 @@
+#!/bin/sh
+. ghdl_options.sh
+
+mkdir -p work
+ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/zpu_config.vhd
+ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpupkg.vhd
+ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/interrupt.vhd
+# to execute helloworld comment interrupt.vhd above
+# and edit sim_small_fpga_top.vhd to never assert interrupts
+#ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/helloworld.vhd
+ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/txt_util.vhd
+ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/trace.vhd
+ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpu_core_small.vhd
+ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/io.vhd
+ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/timer.vhd
+ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/sim_small_fpga_top.vhd
diff --git a/zpu/hdl/example_ghdl/ghdl_make.sh b/zpu/hdl/example_ghdl/ghdl_make.sh
new file mode 100644
index 0000000..948b100
--- /dev/null
+++ b/zpu/hdl/example_ghdl/ghdl_make.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+. ghdl_options.sh
+
+ghdl -m ${MAKE_OPTIONS} fpga_top
diff --git a/zpu/hdl/example_ghdl/ghdl_options.sh b/zpu/hdl/example_ghdl/ghdl_options.sh
new file mode 100644
index 0000000..aba231c
--- /dev/null
+++ b/zpu/hdl/example_ghdl/ghdl_options.sh
@@ -0,0 +1,2 @@
+IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work"
+MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding"
diff --git a/zpu/hdl/example_ghdl/simzpu_medium_ghdl.sh b/zpu/hdl/example_ghdl/simzpu_medium_ghdl.sh
new file mode 100644
index 0000000..8ba5078
--- /dev/null
+++ b/zpu/hdl/example_ghdl/simzpu_medium_ghdl.sh
@@ -0,0 +1,24 @@
+#!/bin/sh
+
+IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work"
+MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding"
+
+if test ! -e work; then
+ echo "Building work library..."
+ mkdir work
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/example_medium/zpu_config_trace.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpupkg.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/txt_util.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/example_medium/sim_fpga_top.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpu_core.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/example_medium/dram_hello.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/timer.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/io.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/trace.vhd
+fi
+
+echo "Compiling design..."
+if ghdl -m ${MAKE_OPTIONS} fpga_top; then
+ echo "Compilation finished, start simulation with"
+ echo " ./fpga_top --stop-time=1ms"
+fi
diff --git a/zpu/hdl/example_medium/.cvsignore b/zpu/hdl/example_medium/.cvsignore
new file mode 100644
index 0000000..3add443
--- /dev/null
+++ b/zpu/hdl/example_medium/.cvsignore
@@ -0,0 +1,4 @@
+vsim.wlf
+work
+log.txt
+trace.txt
diff --git a/zpu/hdl/example_medium/dram_dmips.vhd b/zpu/hdl/example_medium/dram_dmips.vhd
new file mode 100644
index 0000000..0437adc
--- /dev/null
+++ b/zpu/hdl/example_medium/dram_dmips.vhd
@@ -0,0 +1,3308 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity dram is
+port (clk : in std_logic;
+areset : std_logic;
+ mem_writeEnable : in std_logic;
+ mem_readEnable : in std_logic;
+ mem_addr : in std_logic_vector(maxAddrBit downto 0);
+ mem_write : in std_logic_vector(wordSize-1 downto 0);
+ mem_read : out std_logic_vector(wordSize-1 downto 0);
+ mem_busy : out std_logic;
+ mem_writeMask : in std_logic_vector(wordBytes-1 downto 0));
+end dram;
+
+architecture dram_arch of dram is
+
+
+type ram_type is array(natural range 0 to ((2**(maxAddrBitDRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
+
+shared variable ram : ram_type :=
+(
+0 => x"0b0b0b0b",
+1 => x"82700b0b",
+2 => x"80d5f40c",
+3 => x"3a0b0b80",
+4 => x"c4fb0400",
+5 => x"00000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"80c5c22d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
+17 => x"72830609",
+18 => x"81058205",
+19 => x"832b2a83",
+20 => x"ffff0652",
+21 => x"04000000",
+22 => x"00000000",
+23 => x"00000000",
+24 => x"71fd0608",
+25 => x"83ffff73",
+26 => x"83060981",
+27 => x"05820583",
+28 => x"2b2b0906",
+29 => x"7383ffff",
+30 => x"0b0b0b0b",
+31 => x"83a70400",
+32 => x"72098105",
+33 => x"72057373",
+34 => x"09060906",
+35 => x"73097306",
+36 => x"070a8106",
+37 => x"53510400",
+38 => x"00000000",
+39 => x"00000000",
+40 => x"72722473",
+41 => x"732e0753",
+42 => x"51040000",
+43 => x"00000000",
+44 => x"00000000",
+45 => x"00000000",
+46 => x"00000000",
+47 => x"00000000",
+48 => x"71737109",
+49 => x"71068106",
+50 => x"30720a10",
+51 => x"0a720a10",
+52 => x"0a31050a",
+53 => x"81065151",
+54 => x"53510400",
+55 => x"00000000",
+56 => x"72722673",
+57 => x"732e0753",
+58 => x"51040000",
+59 => x"00000000",
+60 => x"00000000",
+61 => x"00000000",
+62 => x"00000000",
+63 => x"00000000",
+64 => x"00000000",
+65 => x"00000000",
+66 => x"00000000",
+67 => x"00000000",
+68 => x"00000000",
+69 => x"00000000",
+70 => x"00000000",
+71 => x"00000000",
+72 => x"0b0b0b88",
+73 => x"c3040000",
+74 => x"00000000",
+75 => x"00000000",
+76 => x"00000000",
+77 => x"00000000",
+78 => x"00000000",
+79 => x"00000000",
+80 => x"720a722b",
+81 => x"0a535104",
+82 => x"00000000",
+83 => x"00000000",
+84 => x"00000000",
+85 => x"00000000",
+86 => x"00000000",
+87 => x"00000000",
+88 => x"72729f06",
+89 => x"0981050b",
+90 => x"0b0b88a6",
+91 => x"05040000",
+92 => x"00000000",
+93 => x"00000000",
+94 => x"00000000",
+95 => x"00000000",
+96 => x"72722aff",
+97 => x"739f062a",
+98 => x"0974090a",
+99 => x"8106ff05",
+100 => x"06075351",
+101 => x"04000000",
+102 => x"00000000",
+103 => x"00000000",
+104 => x"71715351",
+105 => x"020d0406",
+106 => x"73830609",
+107 => x"81058205",
+108 => x"832b0b2b",
+109 => x"0772fc06",
+110 => x"0c515104",
+111 => x"00000000",
+112 => x"72098105",
+113 => x"72050970",
+114 => x"81050906",
+115 => x"0a810653",
+116 => x"51040000",
+117 => x"00000000",
+118 => x"00000000",
+119 => x"00000000",
+120 => x"72098105",
+121 => x"72050970",
+122 => x"81050906",
+123 => x"0a098106",
+124 => x"53510400",
+125 => x"00000000",
+126 => x"00000000",
+127 => x"00000000",
+128 => x"71098105",
+129 => x"52040000",
+130 => x"00000000",
+131 => x"00000000",
+132 => x"00000000",
+133 => x"00000000",
+134 => x"00000000",
+135 => x"00000000",
+136 => x"72720981",
+137 => x"05055351",
+138 => x"04000000",
+139 => x"00000000",
+140 => x"00000000",
+141 => x"00000000",
+142 => x"00000000",
+143 => x"00000000",
+144 => x"72097206",
+145 => x"73730906",
+146 => x"07535104",
+147 => x"00000000",
+148 => x"00000000",
+149 => x"00000000",
+150 => x"00000000",
+151 => x"00000000",
+152 => x"71fc0608",
+153 => x"72830609",
+154 => x"81058305",
+155 => x"1010102a",
+156 => x"81ff0652",
+157 => x"04000000",
+158 => x"00000000",
+159 => x"00000000",
+160 => x"71fc0608",
+161 => x"0b0b80d5",
+162 => x"e0738306",
+163 => x"10100508",
+164 => x"060b0b0b",
+165 => x"88a90400",
+166 => x"00000000",
+167 => x"00000000",
+168 => x"80088408",
+169 => x"88087575",
+170 => x"0b0b0bad",
+171 => x"aa2d5050",
+172 => x"80085688",
+173 => x"0c840c80",
+174 => x"0c510400",
+175 => x"00000000",
+176 => x"80088408",
+177 => x"88087575",
+178 => x"0b0b0bad",
+179 => x"ee2d5050",
+180 => x"80085688",
+181 => x"0c840c80",
+182 => x"0c510400",
+183 => x"00000000",
+184 => x"72097081",
+185 => x"0509060a",
+186 => x"8106ff05",
+187 => x"70547106",
+188 => x"73097274",
+189 => x"05ff0506",
+190 => x"07515151",
+191 => x"04000000",
+192 => x"72097081",
+193 => x"0509060a",
+194 => x"098106ff",
+195 => x"05705471",
+196 => x"06730972",
+197 => x"7405ff05",
+198 => x"06075151",
+199 => x"51040000",
+200 => x"05ff0504",
+201 => x"00000000",
+202 => x"00000000",
+203 => x"00000000",
+204 => x"00000000",
+205 => x"00000000",
+206 => x"00000000",
+207 => x"00000000",
+208 => x"810b0b0b",
+209 => x"80d5f00c",
+210 => x"51040000",
+211 => x"00000000",
+212 => x"00000000",
+213 => x"00000000",
+214 => x"00000000",
+215 => x"00000000",
+216 => x"71810552",
+217 => x"04000000",
+218 => x"00000000",
+219 => x"00000000",
+220 => x"00000000",
+221 => x"00000000",
+222 => x"00000000",
+223 => x"00000000",
+224 => x"00000000",
+225 => x"00000000",
+226 => x"00000000",
+227 => x"00000000",
+228 => x"00000000",
+229 => x"00000000",
+230 => x"00000000",
+231 => x"00000000",
+232 => x"02840572",
+233 => x"10100552",
+234 => x"04000000",
+235 => x"00000000",
+236 => x"00000000",
+237 => x"00000000",
+238 => x"00000000",
+239 => x"00000000",
+240 => x"00000000",
+241 => x"00000000",
+242 => x"00000000",
+243 => x"00000000",
+244 => x"00000000",
+245 => x"00000000",
+246 => x"00000000",
+247 => x"00000000",
+248 => x"717105ff",
+249 => x"05715351",
+250 => x"020d0400",
+251 => x"00000000",
+252 => x"00000000",
+253 => x"00000000",
+254 => x"00000000",
+255 => x"00000000",
+256 => x"82fd3fbf",
+257 => x"a03f0410",
+258 => x"10101010",
+259 => x"10101010",
+260 => x"10101010",
+261 => x"10101010",
+262 => x"10101010",
+263 => x"10101010",
+264 => x"10101010",
+265 => x"10105351",
+266 => x"047381ff",
+267 => x"06738306",
+268 => x"09810583",
+269 => x"05101010",
+270 => x"2b0772fc",
+271 => x"060c5151",
+272 => x"043c0472",
+273 => x"72807281",
+274 => x"06ff0509",
+275 => x"72060571",
+276 => x"1052720a",
+277 => x"100a5372",
+278 => x"ed385151",
+279 => x"535104ff",
+280 => x"3d0d0b0b",
+281 => x"80e5e408",
+282 => x"52710870",
+283 => x"882a8132",
+284 => x"70810651",
+285 => x"515170f1",
+286 => x"3873720c",
+287 => x"833d0d04",
+288 => x"80d5f008",
+289 => x"802ea438",
+290 => x"80d5f408",
+291 => x"822ebd38",
+292 => x"8380800b",
+293 => x"0b0b80e5",
+294 => x"e40c82a0",
+295 => x"800b80e5",
+296 => x"e80c8290",
+297 => x"800b80e5",
+298 => x"ec0c04f8",
+299 => x"808080a4",
+300 => x"0b0b0b80",
+301 => x"e5e40cf8",
+302 => x"80808280",
+303 => x"0b80e5e8",
+304 => x"0cf88080",
+305 => x"84800b80",
+306 => x"e5ec0c04",
+307 => x"80c0a880",
+308 => x"8c0b0b0b",
+309 => x"80e5e40c",
+310 => x"80c0a880",
+311 => x"940b80e5",
+312 => x"e80c0b0b",
+313 => x"80c7d00b",
+314 => x"80e5ec0c",
+315 => x"04f23d0d",
+316 => x"6080e5e8",
+317 => x"08565d82",
+318 => x"750c8059",
+319 => x"805a800b",
+320 => x"8f3d5d5b",
+321 => x"7a101015",
+322 => x"70087108",
+323 => x"719f2c7e",
+324 => x"852b5855",
+325 => x"557d5359",
+326 => x"5799993f",
+327 => x"7d7f7a72",
+328 => x"077c7207",
+329 => x"71716081",
+330 => x"05415f5d",
+331 => x"5b595755",
+332 => x"817b278f",
+333 => x"38767d0c",
+334 => x"77841e0c",
+335 => x"7c800c90",
+336 => x"3d0d0480",
+337 => x"e5e80855",
+338 => x"ffba3970",
+339 => x"7080e5f0",
+340 => x"335170a7",
+341 => x"3880d5fc",
+342 => x"08700852",
+343 => x"5270802e",
+344 => x"94388412",
+345 => x"80d5fc0c",
+346 => x"702d80d5",
+347 => x"fc087008",
+348 => x"525270ee",
+349 => x"38810b80",
+350 => x"e5f03450",
+351 => x"50040470",
+352 => x"0b0b80e5",
+353 => x"e008802e",
+354 => x"8e380b0b",
+355 => x"0b0b800b",
+356 => x"802e0981",
+357 => x"06833850",
+358 => x"040b0b80",
+359 => x"e5e0510b",
+360 => x"0b0bf4dc",
+361 => x"3f500404",
+362 => x"ff3d0d02",
+363 => x"8f053352",
+364 => x"718a2e8a",
+365 => x"387151fd",
+366 => x"a63f833d",
+367 => x"0d048d51",
+368 => x"fd9d3f71",
+369 => x"51fd983f",
+370 => x"833d0d04",
+371 => x"ce3d0db5",
+372 => x"3d707084",
+373 => x"0552088b",
+374 => x"a85c56a5",
+375 => x"3d5e5c80",
+376 => x"75708105",
+377 => x"5733765b",
+378 => x"55587378",
+379 => x"2e80c138",
+380 => x"8e3d5b73",
+381 => x"a52e0981",
+382 => x"0680c538",
+383 => x"78708105",
+384 => x"5a335473",
+385 => x"80e42e81",
+386 => x"b6387380",
+387 => x"e42480c6",
+388 => x"387380e3",
+389 => x"2ea13880",
+390 => x"52a55179",
+391 => x"2d805273",
+392 => x"51792d82",
+393 => x"18587870",
+394 => x"81055a33",
+395 => x"5473c438",
+396 => x"77800cb4",
+397 => x"3d0d047b",
+398 => x"841d8312",
+399 => x"33565d57",
+400 => x"80527351",
+401 => x"792d8118",
+402 => x"79708105",
+403 => x"5b335558",
+404 => x"73ffa038",
+405 => x"db397380",
+406 => x"f32e0981",
+407 => x"06ffb838",
+408 => x"7b841d71",
+409 => x"08595d56",
+410 => x"80773355",
+411 => x"5673762e",
+412 => x"8d388116",
+413 => x"70187033",
+414 => x"57555674",
+415 => x"f538ff16",
+416 => x"55807625",
+417 => x"ffa03876",
+418 => x"70810558",
+419 => x"33548052",
+420 => x"7351792d",
+421 => x"811875ff",
+422 => x"17575758",
+423 => x"807625ff",
+424 => x"85387670",
+425 => x"81055833",
+426 => x"54805273",
+427 => x"51792d81",
+428 => x"1875ff17",
+429 => x"57575875",
+430 => x"8024cc38",
+431 => x"fee8397b",
+432 => x"841d7108",
+433 => x"70719f2c",
+434 => x"5953595d",
+435 => x"56807524",
+436 => x"81913875",
+437 => x"7d7c5856",
+438 => x"54805773",
+439 => x"772e0981",
+440 => x"06b638b0",
+441 => x"7b3402b5",
+442 => x"05567a76",
+443 => x"2e9738ff",
+444 => x"16567533",
+445 => x"75708105",
+446 => x"57348117",
+447 => x"577a762e",
+448 => x"098106eb",
+449 => x"38807534",
+450 => x"767dff12",
+451 => x"57585675",
+452 => x"8024fef3",
+453 => x"38fe8f39",
+454 => x"8a527351",
+455 => x"9fd03f80",
+456 => x"0880c7d4",
+457 => x"05337670",
+458 => x"81055834",
+459 => x"8a527351",
+460 => x"9ef83f80",
+461 => x"08548008",
+462 => x"802effae",
+463 => x"388a5273",
+464 => x"519fab3f",
+465 => x"800880c7",
+466 => x"d4053376",
+467 => x"70810558",
+468 => x"348a5273",
+469 => x"519ed33f",
+470 => x"80085480",
+471 => x"08ffb938",
+472 => x"ff883974",
+473 => x"527653b4",
+474 => x"3dffb805",
+475 => x"51949a3f",
+476 => x"a33d0856",
+477 => x"fedd3980",
+478 => x"3d0d80c1",
+479 => x"0b81b4bc",
+480 => x"34800b81",
+481 => x"b6980c70",
+482 => x"800c823d",
+483 => x"0d04ff3d",
+484 => x"0d800b81",
+485 => x"b4bc3352",
+486 => x"527080c1",
+487 => x"2e993871",
+488 => x"81b69808",
+489 => x"0781b698",
+490 => x"0c80c20b",
+491 => x"81b4c034",
+492 => x"70800c83",
+493 => x"3d0d0481",
+494 => x"0b81b698",
+495 => x"080781b6",
+496 => x"980c80c2",
+497 => x"0b81b4c0",
+498 => x"3470800c",
+499 => x"833d0d04",
+500 => x"fd3d0d75",
+501 => x"70088a05",
+502 => x"535381b4",
+503 => x"bc335170",
+504 => x"80c12e8b",
+505 => x"3873f338",
+506 => x"70800c85",
+507 => x"3d0d04ff",
+508 => x"127081b4",
+509 => x"b8083174",
+510 => x"0c800c85",
+511 => x"3d0d04fc",
+512 => x"3d0d81b4",
+513 => x"c4085574",
+514 => x"802e8c38",
+515 => x"76750871",
+516 => x"0c81b4c4",
+517 => x"0856548c",
+518 => x"155381b4",
+519 => x"b808528a",
+520 => x"518fd43f",
+521 => x"73800c86",
+522 => x"3d0d04fb",
+523 => x"3d0d7770",
+524 => x"085656b0",
+525 => x"5381b4c4",
+526 => x"08527451",
+527 => x"ab943f85",
+528 => x"0b8c170c",
+529 => x"850b8c16",
+530 => x"0c750875",
+531 => x"0c81b4c4",
+532 => x"08547380",
+533 => x"2e8a3873",
+534 => x"08750c81",
+535 => x"b4c40854",
+536 => x"8c145381",
+537 => x"b4b80852",
+538 => x"8a518f8b",
+539 => x"3f841508",
+540 => x"ad38860b",
+541 => x"8c160c88",
+542 => x"15528816",
+543 => x"08518e97",
+544 => x"3f81b4c4",
+545 => x"08700876",
+546 => x"0c548c15",
+547 => x"7054548a",
+548 => x"52730851",
+549 => x"8ee13f73",
+550 => x"800c873d",
+551 => x"0d047508",
+552 => x"54b05373",
+553 => x"527551aa",
+554 => x"a93f7380",
+555 => x"0c873d0d",
+556 => x"04d93d0d",
+557 => x"b0519dcf",
+558 => x"3f800881",
+559 => x"b4b40cb0",
+560 => x"519dc43f",
+561 => x"800881b4",
+562 => x"c40c81b4",
+563 => x"b4088008",
+564 => x"0c800b80",
+565 => x"0884050c",
+566 => x"820b8008",
+567 => x"88050ca8",
+568 => x"0b80088c",
+569 => x"050c9f53",
+570 => x"80c7e052",
+571 => x"80089005",
+572 => x"51a9df3f",
+573 => x"a13d5e9f",
+574 => x"5380c880",
+575 => x"527d51a9",
+576 => x"d13f8a0b",
+577 => x"80f2f80c",
+578 => x"80d2a451",
+579 => x"f9be3f80",
+580 => x"c8a051f9",
+581 => x"b73f80d2",
+582 => x"a451f9b0",
+583 => x"3f80d684",
+584 => x"08802e89",
+585 => x"d33880c8",
+586 => x"d051f9a0",
+587 => x"3f80d2a4",
+588 => x"51f9993f",
+589 => x"80d68008",
+590 => x"5280c8fc",
+591 => x"51f98d3f",
+592 => x"80e69451",
+593 => x"b2ff3f81",
+594 => x"0b9a3d5e",
+595 => x"5b800b80",
+596 => x"d6800825",
+597 => x"82d43890",
+598 => x"3d5f80c1",
+599 => x"0b81b4bc",
+600 => x"34810b81",
+601 => x"b6980c80",
+602 => x"c20b81b4",
+603 => x"c0348240",
+604 => x"835a9f53",
+605 => x"80c9ac52",
+606 => x"7c51a8d6",
+607 => x"3f814180",
+608 => x"7d537e52",
+609 => x"568e943f",
+610 => x"8008762e",
+611 => x"09810683",
+612 => x"38815675",
+613 => x"81b6980c",
+614 => x"7f705856",
+615 => x"758325a2",
+616 => x"38751010",
+617 => x"16fd0542",
+618 => x"a93dffa4",
+619 => x"05538352",
+620 => x"76518cc3",
+621 => x"3f7f8105",
+622 => x"70417058",
+623 => x"56837624",
+624 => x"e0386154",
+625 => x"755380e6",
+626 => x"9c5281b4",
+627 => x"d0518cb7",
+628 => x"3f81b4c4",
+629 => x"08700858",
+630 => x"58b05377",
+631 => x"527651a7",
+632 => x"f13f850b",
+633 => x"8c190c85",
+634 => x"0b8c180c",
+635 => x"7708770c",
+636 => x"81b4c408",
+637 => x"5675802e",
+638 => x"8a387508",
+639 => x"770c81b4",
+640 => x"c408568c",
+641 => x"165381b4",
+642 => x"b808528a",
+643 => x"518be83f",
+644 => x"84170887",
+645 => x"ea38860b",
+646 => x"8c180c88",
+647 => x"17528818",
+648 => x"08518af3",
+649 => x"3f81b4c4",
+650 => x"08700878",
+651 => x"0c568c17",
+652 => x"7054598a",
+653 => x"52780851",
+654 => x"8bbd3f80",
+655 => x"c10b81b4",
+656 => x"c0335757",
+657 => x"767626a2",
+658 => x"3880c352",
+659 => x"76518ca1",
+660 => x"3f800861",
+661 => x"2e89e438",
+662 => x"81177081",
+663 => x"ff0681b4",
+664 => x"c0335858",
+665 => x"58757727",
+666 => x"e0387960",
+667 => x"29627054",
+668 => x"71535b59",
+669 => x"98b43f80",
+670 => x"0840787a",
+671 => x"31708729",
+672 => x"80083180",
+673 => x"088a0581",
+674 => x"b4bc3381",
+675 => x"b4b8085e",
+676 => x"5b525a56",
+677 => x"7780c12e",
+678 => x"89ce387b",
+679 => x"f738811b",
+680 => x"5b80d680",
+681 => x"087b25fd",
+682 => x"b13881b4",
+683 => x"ac51b095",
+684 => x"3f80c9cc",
+685 => x"51f6953f",
+686 => x"80d2a451",
+687 => x"f68e3f80",
+688 => x"c9dc51f6",
+689 => x"873f80d2",
+690 => x"a451f680",
+691 => x"3f81b4b8",
+692 => x"085280ca",
+693 => x"9451f5f4",
+694 => x"3f855280",
+695 => x"cab051f5",
+696 => x"eb3f81b6",
+697 => x"98085280",
+698 => x"cacc51f5",
+699 => x"df3f8152",
+700 => x"80cab051",
+701 => x"f5d63f81",
+702 => x"b4bc3352",
+703 => x"80cae851",
+704 => x"f5ca3f80",
+705 => x"c15280cb",
+706 => x"8451f5c0",
+707 => x"3f81b4c0",
+708 => x"335280cb",
+709 => x"a051f5b4",
+710 => x"3f80c252",
+711 => x"80cb8451",
+712 => x"f5aa3f81",
+713 => x"b4f00852",
+714 => x"80cbbc51",
+715 => x"f59e3f87",
+716 => x"5280cab0",
+717 => x"51f5953f",
+718 => x"80f2f808",
+719 => x"5280cbd8",
+720 => x"51f5893f",
+721 => x"80cbf451",
+722 => x"f5823f80",
+723 => x"cca051f4",
+724 => x"fb3f81b4",
+725 => x"c4087008",
+726 => x"535a80cc",
+727 => x"ac51f4ec",
+728 => x"3f80ccc8",
+729 => x"51f4e53f",
+730 => x"81b4c408",
+731 => x"84110853",
+732 => x"5680ccfc",
+733 => x"51f4d53f",
+734 => x"805280ca",
+735 => x"b051f4cc",
+736 => x"3f81b4c4",
+737 => x"08881108",
+738 => x"535880cd",
+739 => x"9851f4bc",
+740 => x"3f825280",
+741 => x"cab051f4",
+742 => x"b33f81b4",
+743 => x"c4088c11",
+744 => x"08535780",
+745 => x"cdb451f4",
+746 => x"a33f9152",
+747 => x"80cab051",
+748 => x"f49a3f81",
+749 => x"b4c40890",
+750 => x"055280cd",
+751 => x"d051f48c",
+752 => x"3f80cdec",
+753 => x"51f4853f",
+754 => x"80cea451",
+755 => x"f3fe3f81",
+756 => x"b4b40870",
+757 => x"08535f80",
+758 => x"ccac51f3",
+759 => x"ef3f80ce",
+760 => x"b851f3e8",
+761 => x"3f81b4b4",
+762 => x"08841108",
+763 => x"535b80cc",
+764 => x"fc51f3d8",
+765 => x"3f805280",
+766 => x"cab051f3",
+767 => x"cf3f81b4",
+768 => x"b4088811",
+769 => x"08535c80",
+770 => x"cd9851f3",
+771 => x"bf3f8152",
+772 => x"80cab051",
+773 => x"f3b63f81",
+774 => x"b4b4088c",
+775 => x"1108535a",
+776 => x"80cdb451",
+777 => x"f3a63f92",
+778 => x"5280cab0",
+779 => x"51f39d3f",
+780 => x"81b4b408",
+781 => x"90055280",
+782 => x"cdd051f3",
+783 => x"8f3f80cd",
+784 => x"ec51f388",
+785 => x"3f7f5280",
+786 => x"cef851f2",
+787 => x"ff3f8552",
+788 => x"80cab051",
+789 => x"f2f63f78",
+790 => x"5280cf94",
+791 => x"51f2ed3f",
+792 => x"8d5280ca",
+793 => x"b051f2e4",
+794 => x"3f615280",
+795 => x"cfb051f2",
+796 => x"db3f8752",
+797 => x"80cab051",
+798 => x"f2d23f60",
+799 => x"5280cfcc",
+800 => x"51f2c93f",
+801 => x"815280ca",
+802 => x"b051f2c0",
+803 => x"3f7d5280",
+804 => x"cfe851f2",
+805 => x"b73f80d0",
+806 => x"8451f2b0",
+807 => x"3f7c5280",
+808 => x"d0bc51f2",
+809 => x"a73f80d0",
+810 => x"d851f2a0",
+811 => x"3f80d2a4",
+812 => x"51f2993f",
+813 => x"81b4ac08",
+814 => x"81b4b008",
+815 => x"80e69408",
+816 => x"80e69808",
+817 => x"72713170",
+818 => x"74267574",
+819 => x"31707231",
+820 => x"80e68c0c",
+821 => x"444480e6",
+822 => x"900c80e6",
+823 => x"90085680",
+824 => x"d190555c",
+825 => x"595758f1",
+826 => x"e33f80e6",
+827 => x"8c085680",
+828 => x"762582a3",
+829 => x"3880d680",
+830 => x"0870719f",
+831 => x"2c9a3d53",
+832 => x"565680e6",
+833 => x"8c0880e6",
+834 => x"90084153",
+835 => x"7f547052",
+836 => x"5a89eb3f",
+837 => x"66685f80",
+838 => x"e5fc0c7d",
+839 => x"80e6800c",
+840 => x"80d68008",
+841 => x"709f2c58",
+842 => x"568058bd",
+843 => x"84c07855",
+844 => x"55765275",
+845 => x"53795187",
+846 => x"d13f953d",
+847 => x"80e68c08",
+848 => x"80e69008",
+849 => x"41557f56",
+850 => x"67694053",
+851 => x"7e547052",
+852 => x"5c89ab3f",
+853 => x"64665e80",
+854 => x"e6840c7c",
+855 => x"80e6880c",
+856 => x"80d68008",
+857 => x"709f2c40",
+858 => x"58805783",
+859 => x"dceb9480",
+860 => x"7755557e",
+861 => x"5277537b",
+862 => x"51878f3f",
+863 => x"64665d5b",
+864 => x"805e8ddd",
+865 => x"7e555580",
+866 => x"e68c0880",
+867 => x"e6900859",
+868 => x"52775379",
+869 => x"5186f33f",
+870 => x"66684054",
+871 => x"7e557a52",
+872 => x"7b53a93d",
+873 => x"ffa80551",
+874 => x"88d43f62",
+875 => x"645e81b4",
+876 => x"c80c7c81",
+877 => x"b4cc0c80",
+878 => x"d1a051f0",
+879 => x"8f3f80e6",
+880 => x"80085280",
+881 => x"d1d051f0",
+882 => x"833f80d1",
+883 => x"d851effc",
+884 => x"3f80e688",
+885 => x"085280d1",
+886 => x"d051eff0",
+887 => x"3f81b4cc",
+888 => x"085280d2",
+889 => x"8851efe4",
+890 => x"3f80d2a4",
+891 => x"51efdd3f",
+892 => x"800b800c",
+893 => x"a93d0d04",
+894 => x"80d2a851",
+895 => x"f6ac3977",
+896 => x"0857b053",
+897 => x"76527751",
+898 => x"9fc83f80",
+899 => x"c10b81b4",
+900 => x"c0335757",
+901 => x"f8ae3975",
+902 => x"8a3880e6",
+903 => x"90088126",
+904 => x"fdd33880",
+905 => x"d2d851ef",
+906 => x"a33f80d3",
+907 => x"9051ef9c",
+908 => x"3f80d2a4",
+909 => x"51ef953f",
+910 => x"80d68008",
+911 => x"70719f2c",
+912 => x"9a3d5356",
+913 => x"5680e68c",
+914 => x"0880e690",
+915 => x"0841537f",
+916 => x"5470525a",
+917 => x"87a83f66",
+918 => x"685f80e5",
+919 => x"fc0c7d80",
+920 => x"e6800c80",
+921 => x"d6800870",
+922 => x"9f2c5856",
+923 => x"8058bd84",
+924 => x"c0785555",
+925 => x"76527553",
+926 => x"7951858e",
+927 => x"3f953d80",
+928 => x"e68c0880",
+929 => x"e6900841",
+930 => x"557f5667",
+931 => x"6940537e",
+932 => x"5470525c",
+933 => x"86e83f64",
+934 => x"665e80e6",
+935 => x"840c7c80",
+936 => x"e6880c80",
+937 => x"d6800870",
+938 => x"9f2c4058",
+939 => x"805783dc",
+940 => x"eb948077",
+941 => x"55557e52",
+942 => x"77537b51",
+943 => x"84cc3f64",
+944 => x"665d5b80",
+945 => x"5e8ddd7e",
+946 => x"555580e6",
+947 => x"8c0880e6",
+948 => x"90085952",
+949 => x"77537951",
+950 => x"84b03f66",
+951 => x"6840547e",
+952 => x"557a527b",
+953 => x"53a93dff",
+954 => x"a8055186",
+955 => x"913f6264",
+956 => x"5e81b4c8",
+957 => x"0c7c81b4",
+958 => x"cc0c80d1",
+959 => x"a051edcc",
+960 => x"3f80e680",
+961 => x"085280d1",
+962 => x"d051edc0",
+963 => x"3f80d1d8",
+964 => x"51edb93f",
+965 => x"80e68808",
+966 => x"5280d1d0",
+967 => x"51edad3f",
+968 => x"81b4cc08",
+969 => x"5280d288",
+970 => x"51eda13f",
+971 => x"80d2a451",
+972 => x"ed9a3f80",
+973 => x"0b800ca9",
+974 => x"3d0d04a9",
+975 => x"3dffa005",
+976 => x"52805180",
+977 => x"d23f9f53",
+978 => x"80d3b052",
+979 => x"7c519d82",
+980 => x"3f7a7b81",
+981 => x"b4b80c81",
+982 => x"187081ff",
+983 => x"0681b4c0",
+984 => x"33595959",
+985 => x"5af5fe39",
+986 => x"ff16707b",
+987 => x"31600c5c",
+988 => x"800b811c",
+989 => x"5c5c80d6",
+990 => x"80087b25",
+991 => x"f3dc38f6",
+992 => x"a939ff3d",
+993 => x"0d738232",
+994 => x"70307072",
+995 => x"07802580",
+996 => x"0c525283",
+997 => x"3d0d04fe",
+998 => x"3d0d7476",
+999 => x"71535452",
+1000 => x"71822e83",
+1001 => x"38835171",
+1002 => x"812e9a38",
+1003 => x"8172269f",
+1004 => x"3871822e",
+1005 => x"b8387184",
+1006 => x"2ea93870",
+1007 => x"730c7080",
+1008 => x"0c843d0d",
+1009 => x"0480e40b",
+1010 => x"81b4b808",
+1011 => x"258b3880",
+1012 => x"730c7080",
+1013 => x"0c843d0d",
+1014 => x"0483730c",
+1015 => x"70800c84",
+1016 => x"3d0d0482",
+1017 => x"730c7080",
+1018 => x"0c843d0d",
+1019 => x"0481730c",
+1020 => x"70800c84",
+1021 => x"3d0d0480",
+1022 => x"3d0d7474",
+1023 => x"14820571",
+1024 => x"0c800c82",
+1025 => x"3d0d04f7",
+1026 => x"3d0d7b7d",
+1027 => x"7f618512",
+1028 => x"70822b75",
+1029 => x"11707471",
+1030 => x"70840553",
+1031 => x"0c5a5a5d",
+1032 => x"5b760c79",
+1033 => x"80f8180c",
+1034 => x"79861252",
+1035 => x"57585a5a",
+1036 => x"76762499",
+1037 => x"3876b329",
+1038 => x"822b7911",
+1039 => x"51537673",
+1040 => x"70840555",
+1041 => x"0c811454",
+1042 => x"757425f2",
+1043 => x"387681cc",
+1044 => x"2919fc11",
+1045 => x"088105fc",
+1046 => x"120c7a19",
+1047 => x"70089fa0",
+1048 => x"130c5856",
+1049 => x"850b81b4",
+1050 => x"b80c7580",
+1051 => x"0c8b3d0d",
+1052 => x"04fe3d0d",
+1053 => x"02930533",
+1054 => x"51800284",
+1055 => x"05970533",
+1056 => x"54527073",
+1057 => x"2e883871",
+1058 => x"800c843d",
+1059 => x"0d047081",
+1060 => x"b4bc3481",
+1061 => x"0b800c84",
+1062 => x"3d0d04f8",
+1063 => x"3d0d7a7c",
+1064 => x"5956820b",
+1065 => x"83195555",
+1066 => x"74167033",
+1067 => x"75335b51",
+1068 => x"5372792e",
+1069 => x"80c63880",
+1070 => x"c10b8116",
+1071 => x"81165656",
+1072 => x"57827525",
+1073 => x"e338ffa9",
+1074 => x"177081ff",
+1075 => x"06555973",
+1076 => x"82268338",
+1077 => x"87558153",
+1078 => x"7680d22e",
+1079 => x"98387752",
+1080 => x"75519bc3",
+1081 => x"3f805372",
+1082 => x"80082589",
+1083 => x"38871581",
+1084 => x"b4b80c81",
+1085 => x"5372800c",
+1086 => x"8a3d0d04",
+1087 => x"7281b4bc",
+1088 => x"34827525",
+1089 => x"ffa238ff",
+1090 => x"bd39ef3d",
+1091 => x"0d636567",
+1092 => x"5b427943",
+1093 => x"67695940",
+1094 => x"77415a80",
+1095 => x"5d805e61",
+1096 => x"7083ffff",
+1097 => x"0671902a",
+1098 => x"627083ff",
+1099 => x"ff067190",
+1100 => x"2a747229",
+1101 => x"74732975",
+1102 => x"73297774",
+1103 => x"2973902a",
+1104 => x"05721151",
+1105 => x"5856535f",
+1106 => x"5a575a58",
+1107 => x"55587373",
+1108 => x"27863884",
+1109 => x"80801656",
+1110 => x"73902a16",
+1111 => x"5b7883ff",
+1112 => x"ff067484",
+1113 => x"80802905",
+1114 => x"5c7a7c5a",
+1115 => x"5d785e77",
+1116 => x"7f296178",
+1117 => x"29057d05",
+1118 => x"5d7c7e56",
+1119 => x"7a0c7484",
+1120 => x"1b0c7980",
+1121 => x"0c933d0d",
+1122 => x"04f93d0d",
+1123 => x"797b7d54",
+1124 => x"58725977",
+1125 => x"30797030",
+1126 => x"7072079f",
+1127 => x"2a737131",
+1128 => x"5a525977",
+1129 => x"7956730c",
+1130 => x"53738413",
+1131 => x"0c54800c",
+1132 => x"893d0d04",
+1133 => x"f93d0d79",
+1134 => x"7b7d7f56",
+1135 => x"54525472",
+1136 => x"802ea038",
+1137 => x"70577158",
+1138 => x"a0733152",
+1139 => x"807225a1",
+1140 => x"38777074",
+1141 => x"2b577073",
+1142 => x"2a78752b",
+1143 => x"07565174",
+1144 => x"76535170",
+1145 => x"740c7184",
+1146 => x"150c7380",
+1147 => x"0c893d0d",
+1148 => x"04805677",
+1149 => x"72302b55",
+1150 => x"74765351",
+1151 => x"e639e43d",
+1152 => x"0d6ea13d",
+1153 => x"08a33d08",
+1154 => x"59575f80",
+1155 => x"764d774e",
+1156 => x"a33d08a5",
+1157 => x"3d08574b",
+1158 => x"754c5e7d",
+1159 => x"6c2486fb",
+1160 => x"38806a24",
+1161 => x"878f3869",
+1162 => x"6b58566b",
+1163 => x"6d5d467b",
+1164 => x"47754476",
+1165 => x"45646468",
+1166 => x"685c5c56",
+1167 => x"567481e7",
+1168 => x"38787627",
+1169 => x"82c73875",
+1170 => x"81ff2683",
+1171 => x"2b5583ff",
+1172 => x"ff76278c",
+1173 => x"389055fe",
+1174 => x"800a7627",
+1175 => x"83389855",
+1176 => x"75752a80",
+1177 => x"d3d00570",
+1178 => x"33a07731",
+1179 => x"71315755",
+1180 => x"5774802e",
+1181 => x"95387575",
+1182 => x"2ba07631",
+1183 => x"7a772b7c",
+1184 => x"722a077c",
+1185 => x"782b5d5b",
+1186 => x"59567590",
+1187 => x"2a7683ff",
+1188 => x"ff067154",
+1189 => x"7a535957",
+1190 => x"88803f80",
+1191 => x"085b87ea",
+1192 => x"3f800880",
+1193 => x"0879297c",
+1194 => x"902b7c90",
+1195 => x"2a075656",
+1196 => x"59737527",
+1197 => x"94388008",
+1198 => x"ff057615",
+1199 => x"55597574",
+1200 => x"26873874",
+1201 => x"742687b9",
+1202 => x"38765273",
+1203 => x"75315187",
+1204 => x"c93f8008",
+1205 => x"5587b33f",
+1206 => x"80088008",
+1207 => x"79297b83",
+1208 => x"ffff0677",
+1209 => x"902b0756",
+1210 => x"59577378",
+1211 => x"27963880",
+1212 => x"08ff0576",
+1213 => x"15555775",
+1214 => x"74268938",
+1215 => x"77742677",
+1216 => x"71315856",
+1217 => x"78902b77",
+1218 => x"0758805b",
+1219 => x"7a407741",
+1220 => x"7f615654",
+1221 => x"7d80d938",
+1222 => x"737f0c74",
+1223 => x"7f84050c",
+1224 => x"7e800c9e",
+1225 => x"3d0d0480",
+1226 => x"705c5874",
+1227 => x"7926dd38",
+1228 => x"7481ff26",
+1229 => x"832b5774",
+1230 => x"83ffff26",
+1231 => x"82a53874",
+1232 => x"772a80d3",
+1233 => x"d0057033",
+1234 => x"a0793171",
+1235 => x"31595c5d",
+1236 => x"7682b338",
+1237 => x"76547479",
+1238 => x"27833881",
+1239 => x"54797627",
+1240 => x"74075981",
+1241 => x"5878ffa2",
+1242 => x"38765880",
+1243 => x"5bff9d39",
+1244 => x"73527453",
+1245 => x"9e3de805",
+1246 => x"51fc8e3f",
+1247 => x"6769567f",
+1248 => x"0c747f84",
+1249 => x"050c7e80",
+1250 => x"0c9e3d0d",
+1251 => x"0475802e",
+1252 => x"81c43875",
+1253 => x"81ff2683",
+1254 => x"2b5583ff",
+1255 => x"ff76278c",
+1256 => x"389055fe",
+1257 => x"800a7627",
+1258 => x"83389855",
+1259 => x"75752a80",
+1260 => x"d3d00570",
+1261 => x"33a07731",
+1262 => x"7131575e",
+1263 => x"54748491",
+1264 => x"38787631",
+1265 => x"54817690",
+1266 => x"2a7783ff",
+1267 => x"ff065f5d",
+1268 => x"5b7b5273",
+1269 => x"5185c33f",
+1270 => x"80085785",
+1271 => x"ad3f8008",
+1272 => x"80087e29",
+1273 => x"78902b7c",
+1274 => x"902a0756",
+1275 => x"56597375",
+1276 => x"27943880",
+1277 => x"08ff0576",
+1278 => x"15555975",
+1279 => x"74268738",
+1280 => x"74742684",
+1281 => x"f3387b52",
+1282 => x"73753151",
+1283 => x"858c3f80",
+1284 => x"085584f6",
+1285 => x"3f800880",
+1286 => x"087e297b",
+1287 => x"83ffff06",
+1288 => x"77902b07",
+1289 => x"56595773",
+1290 => x"78279638",
+1291 => x"8008ff05",
+1292 => x"76155557",
+1293 => x"75742689",
+1294 => x"38777426",
+1295 => x"77713158",
+1296 => x"5a78902b",
+1297 => x"77077b41",
+1298 => x"417f6156",
+1299 => x"547d802e",
+1300 => x"fdc638fe",
+1301 => x"9b397552",
+1302 => x"815184ae",
+1303 => x"3f800856",
+1304 => x"feb13990",
+1305 => x"57fe800a",
+1306 => x"7527fdd3",
+1307 => x"38987571",
+1308 => x"2a80d3d0",
+1309 => x"057033a0",
+1310 => x"73317131",
+1311 => x"535d5e57",
+1312 => x"76802efd",
+1313 => x"cf38a077",
+1314 => x"3175782b",
+1315 => x"77722a07",
+1316 => x"77792b7b",
+1317 => x"7a2b7d74",
+1318 => x"2a077d7b",
+1319 => x"2b73902a",
+1320 => x"7483ffff",
+1321 => x"0671597f",
+1322 => x"772a585e",
+1323 => x"5c415f58",
+1324 => x"5c5483e6",
+1325 => x"3f800854",
+1326 => x"83d03f80",
+1327 => x"08800879",
+1328 => x"2975902b",
+1329 => x"7e902a07",
+1330 => x"56565973",
+1331 => x"75279938",
+1332 => x"8008ff05",
+1333 => x"7b155559",
+1334 => x"7a74268c",
+1335 => x"38737527",
+1336 => x"8738ff19",
+1337 => x"7b155559",
+1338 => x"76527375",
+1339 => x"315183aa",
+1340 => x"3f800855",
+1341 => x"83943f80",
+1342 => x"08800879",
+1343 => x"297d83ff",
+1344 => x"ff067790",
+1345 => x"2b075659",
+1346 => x"57737827",
+1347 => x"99388008",
+1348 => x"ff057b15",
+1349 => x"55577a74",
+1350 => x"268c3873",
+1351 => x"78278738",
+1352 => x"ff177b15",
+1353 => x"55577378",
+1354 => x"3179902b",
+1355 => x"78077083",
+1356 => x"ffff0671",
+1357 => x"902a7983",
+1358 => x"ffff067a",
+1359 => x"902a7372",
+1360 => x"29737329",
+1361 => x"74732976",
+1362 => x"74297390",
+1363 => x"2a057205",
+1364 => x"5755435f",
+1365 => x"5b585a57",
+1366 => x"595a747c",
+1367 => x"27863884",
+1368 => x"80801757",
+1369 => x"74902a17",
+1370 => x"7983ffff",
+1371 => x"06768480",
+1372 => x"80290557",
+1373 => x"57767a26",
+1374 => x"9a38767a",
+1375 => x"32703070",
+1376 => x"72078025",
+1377 => x"565a5b7c",
+1378 => x"7627fafe",
+1379 => x"3873802e",
+1380 => x"faf838ff",
+1381 => x"1858805b",
+1382 => x"faf239ff",
+1383 => x"76537754",
+1384 => x"9f3de805",
+1385 => x"525ef7e1",
+1386 => x"3f676957",
+1387 => x"4c754d69",
+1388 => x"8025f8f3",
+1389 => x"387d096a",
+1390 => x"6c5c537a",
+1391 => x"549f3de8",
+1392 => x"05525ef7",
+1393 => x"c43f6769",
+1394 => x"714c704d",
+1395 => x"5856f8db",
+1396 => x"39a07531",
+1397 => x"76762b7a",
+1398 => x"772b7c73",
+1399 => x"2a077c78",
+1400 => x"2b72902a",
+1401 => x"7383ffff",
+1402 => x"0671587e",
+1403 => x"762a5742",
+1404 => x"405d5d57",
+1405 => x"5881a33f",
+1406 => x"80085781",
+1407 => x"8d3f8008",
+1408 => x"80087e29",
+1409 => x"78902b7d",
+1410 => x"902a0756",
+1411 => x"56597375",
+1412 => x"27993880",
+1413 => x"08ff0576",
+1414 => x"15555975",
+1415 => x"74268c38",
+1416 => x"73752787",
+1417 => x"38ff1976",
+1418 => x"1555597b",
+1419 => x"52737531",
+1420 => x"5180e73f",
+1421 => x"80085580",
+1422 => x"d13f8008",
+1423 => x"80087e29",
+1424 => x"7c83ffff",
+1425 => x"06707890",
+1426 => x"2b075156",
+1427 => x"58587377",
+1428 => x"27993880",
+1429 => x"08ff0576",
+1430 => x"15555875",
+1431 => x"74268c38",
+1432 => x"73772787",
+1433 => x"38ff1876",
+1434 => x"15555878",
+1435 => x"902b7807",
+1436 => x"74783155",
+1437 => x"5bfada39",
+1438 => x"ff197615",
+1439 => x"5559fb86",
+1440 => x"39ff1976",
+1441 => x"155559f8",
+1442 => x"c0397070",
+1443 => x"70805375",
+1444 => x"52745181",
+1445 => x"913f5050",
+1446 => x"50047070",
+1447 => x"70815375",
+1448 => x"52745181",
+1449 => x"813f5050",
+1450 => x"5004fb3d",
+1451 => x"0d777955",
+1452 => x"55805675",
+1453 => x"7524ab38",
+1454 => x"8074249d",
+1455 => x"38805373",
+1456 => x"52745180",
+1457 => x"e13f8008",
+1458 => x"5475802e",
+1459 => x"85388008",
+1460 => x"30547380",
+1461 => x"0c873d0d",
+1462 => x"04733076",
+1463 => x"81325754",
+1464 => x"dc397430",
+1465 => x"55815673",
+1466 => x"8025d238",
+1467 => x"ec39fa3d",
+1468 => x"0d787a57",
+1469 => x"55805776",
+1470 => x"7524a438",
+1471 => x"759f2c54",
+1472 => x"81537574",
+1473 => x"32743152",
+1474 => x"74519b3f",
+1475 => x"80085476",
+1476 => x"802e8538",
+1477 => x"80083054",
+1478 => x"73800c88",
+1479 => x"3d0d0474",
+1480 => x"30558157",
+1481 => x"d739fc3d",
+1482 => x"0d767853",
+1483 => x"54815380",
+1484 => x"74732652",
+1485 => x"5572802e",
+1486 => x"98387080",
+1487 => x"2eab3880",
+1488 => x"7224a638",
+1489 => x"71107310",
+1490 => x"75722653",
+1491 => x"545272ea",
+1492 => x"38735178",
+1493 => x"83387451",
+1494 => x"70800c86",
+1495 => x"3d0d0472",
+1496 => x"0a100a72",
+1497 => x"0a100a53",
+1498 => x"5372802e",
+1499 => x"e4387174",
+1500 => x"26ed3873",
+1501 => x"72317574",
+1502 => x"07740a10",
+1503 => x"0a740a10",
+1504 => x"0a555556",
+1505 => x"54e33970",
+1506 => x"70735280",
+1507 => x"decc0851",
+1508 => x"933f5050",
+1509 => x"04707073",
+1510 => x"5280decc",
+1511 => x"085190ce",
+1512 => x"3f505004",
+1513 => x"f43d0d7e",
+1514 => x"608b1170",
+1515 => x"f8065b55",
+1516 => x"555d7296",
+1517 => x"26833890",
+1518 => x"58807824",
+1519 => x"74792607",
+1520 => x"55805474",
+1521 => x"742e0981",
+1522 => x"0680ca38",
+1523 => x"7c518d9e",
+1524 => x"3f7783f7",
+1525 => x"2680c538",
+1526 => x"77832a70",
+1527 => x"10101080",
+1528 => x"d6c4058c",
+1529 => x"11085858",
+1530 => x"5475772e",
+1531 => x"81f03884",
+1532 => x"1608fc06",
+1533 => x"8c170888",
+1534 => x"1808718c",
+1535 => x"120c8812",
+1536 => x"0c5b7605",
+1537 => x"84110881",
+1538 => x"0784120c",
+1539 => x"537c518c",
+1540 => x"de3f8816",
+1541 => x"5473800c",
+1542 => x"8e3d0d04",
+1543 => x"77892a78",
+1544 => x"832a5854",
+1545 => x"73802ebf",
+1546 => x"3877862a",
+1547 => x"b8055784",
+1548 => x"7427b438",
+1549 => x"80db1457",
+1550 => x"947427ab",
+1551 => x"38778c2a",
+1552 => x"80ee0557",
+1553 => x"80d47427",
+1554 => x"9e38778f",
+1555 => x"2a80f705",
+1556 => x"5782d474",
+1557 => x"27913877",
+1558 => x"922a80fc",
+1559 => x"05578ad4",
+1560 => x"74278438",
+1561 => x"80fe5776",
+1562 => x"10101080",
+1563 => x"d6c4058c",
+1564 => x"11085653",
+1565 => x"74732ea3",
+1566 => x"38841508",
+1567 => x"fc067079",
+1568 => x"31555673",
+1569 => x"8f2488e4",
+1570 => x"38738025",
+1571 => x"88e6388c",
+1572 => x"15085574",
+1573 => x"732e0981",
+1574 => x"06df3881",
+1575 => x"175980d6",
+1576 => x"d4085675",
+1577 => x"80d6cc2e",
+1578 => x"82cc3884",
+1579 => x"1608fc06",
+1580 => x"70793155",
+1581 => x"55738f24",
+1582 => x"bb3880d6",
+1583 => x"cc0b80d6",
+1584 => x"d80c80d6",
+1585 => x"cc0b80d6",
+1586 => x"d40c8074",
+1587 => x"2480db38",
+1588 => x"74168411",
+1589 => x"08810784",
+1590 => x"120c53fe",
+1591 => x"b0398816",
+1592 => x"8c110857",
+1593 => x"5975792e",
+1594 => x"098106fe",
+1595 => x"82388214",
+1596 => x"59ffab39",
+1597 => x"77167881",
+1598 => x"0784180c",
+1599 => x"7080d6d8",
+1600 => x"0c7080d6",
+1601 => x"d40c80d6",
+1602 => x"cc0b8c12",
+1603 => x"0c8c1108",
+1604 => x"88120c74",
+1605 => x"81078412",
+1606 => x"0c740574",
+1607 => x"710c5b7c",
+1608 => x"518acc3f",
+1609 => x"881654fd",
+1610 => x"ec3983ff",
+1611 => x"75278391",
+1612 => x"3874892a",
+1613 => x"75832a54",
+1614 => x"5473802e",
+1615 => x"bf387486",
+1616 => x"2ab80553",
+1617 => x"847427b4",
+1618 => x"3880db14",
+1619 => x"53947427",
+1620 => x"ab38748c",
+1621 => x"2a80ee05",
+1622 => x"5380d474",
+1623 => x"279e3874",
+1624 => x"8f2a80f7",
+1625 => x"055382d4",
+1626 => x"74279138",
+1627 => x"74922a80",
+1628 => x"fc05538a",
+1629 => x"d4742784",
+1630 => x"3880fe53",
+1631 => x"72101010",
+1632 => x"80d6c405",
+1633 => x"88110855",
+1634 => x"5773772e",
+1635 => x"868b3884",
+1636 => x"1408fc06",
+1637 => x"5b747b27",
+1638 => x"8d388814",
+1639 => x"08547377",
+1640 => x"2e098106",
+1641 => x"ea388c14",
+1642 => x"0880d6c4",
+1643 => x"0b840508",
+1644 => x"718c190c",
+1645 => x"7588190c",
+1646 => x"7788130c",
+1647 => x"5c57758c",
+1648 => x"150c7853",
+1649 => x"80792483",
+1650 => x"98387282",
+1651 => x"2c81712b",
+1652 => x"5656747b",
+1653 => x"2680ca38",
+1654 => x"7a750657",
+1655 => x"7682a338",
+1656 => x"78fc0684",
+1657 => x"05597410",
+1658 => x"707c0655",
+1659 => x"55738292",
+1660 => x"38841959",
+1661 => x"f13980d6",
+1662 => x"c40b8405",
+1663 => x"0879545b",
+1664 => x"788025c6",
+1665 => x"3882da39",
+1666 => x"74097b06",
+1667 => x"7080d6c4",
+1668 => x"0b84050c",
+1669 => x"5b741055",
+1670 => x"747b2685",
+1671 => x"387485bc",
+1672 => x"3880d6c4",
+1673 => x"0b880508",
+1674 => x"70841208",
+1675 => x"fc06707b",
+1676 => x"317b7226",
+1677 => x"8f722507",
+1678 => x"5d575c5c",
+1679 => x"5578802e",
+1680 => x"80d93879",
+1681 => x"1580d6bc",
+1682 => x"08199011",
+1683 => x"59545680",
+1684 => x"d6b808ff",
+1685 => x"2e8838a0",
+1686 => x"8f13e080",
+1687 => x"06577652",
+1688 => x"7c51888c",
+1689 => x"3f800854",
+1690 => x"8008ff2e",
+1691 => x"90388008",
+1692 => x"762782a7",
+1693 => x"387480d6",
+1694 => x"c42e829f",
+1695 => x"3880d6c4",
+1696 => x"0b880508",
+1697 => x"55841508",
+1698 => x"fc067079",
+1699 => x"31797226",
+1700 => x"8f722507",
+1701 => x"5d555a7a",
+1702 => x"83f23877",
+1703 => x"81078416",
+1704 => x"0c771570",
+1705 => x"80d6c40b",
+1706 => x"88050c74",
+1707 => x"81078412",
+1708 => x"0c567c51",
+1709 => x"87b93f88",
+1710 => x"15547380",
+1711 => x"0c8e3d0d",
+1712 => x"0474832a",
+1713 => x"70545480",
+1714 => x"7424819b",
+1715 => x"3872822c",
+1716 => x"81712b80",
+1717 => x"d6c80807",
+1718 => x"7080d6c4",
+1719 => x"0b84050c",
+1720 => x"75101010",
+1721 => x"80d6c405",
+1722 => x"88110871",
+1723 => x"8c1b0c70",
+1724 => x"881b0c79",
+1725 => x"88130c57",
+1726 => x"555c5575",
+1727 => x"8c150cfd",
+1728 => x"c1397879",
+1729 => x"10101080",
+1730 => x"d6c40570",
+1731 => x"565b5c8c",
+1732 => x"14085675",
+1733 => x"742ea338",
+1734 => x"841608fc",
+1735 => x"06707931",
+1736 => x"5853768f",
+1737 => x"2483f138",
+1738 => x"76802584",
+1739 => x"af388c16",
+1740 => x"08567574",
+1741 => x"2e098106",
+1742 => x"df388814",
+1743 => x"811a7083",
+1744 => x"06555a54",
+1745 => x"72c9387b",
+1746 => x"83065675",
+1747 => x"802efdb8",
+1748 => x"38ff1cf8",
+1749 => x"1b5b5c88",
+1750 => x"1a087a2e",
+1751 => x"ea38fdb5",
+1752 => x"39831953",
+1753 => x"fce43983",
+1754 => x"1470822c",
+1755 => x"81712b80",
+1756 => x"d6c80807",
+1757 => x"7080d6c4",
+1758 => x"0b84050c",
+1759 => x"76101010",
+1760 => x"80d6c405",
+1761 => x"88110871",
+1762 => x"8c1c0c70",
+1763 => x"881c0c7a",
+1764 => x"88130c58",
+1765 => x"535d5653",
+1766 => x"fee13980",
+1767 => x"d6880817",
+1768 => x"59800876",
+1769 => x"2e818b38",
+1770 => x"80d6b808",
+1771 => x"ff2e848e",
+1772 => x"38737631",
+1773 => x"1980d688",
+1774 => x"0c738706",
+1775 => x"70565372",
+1776 => x"802e8838",
+1777 => x"88733170",
+1778 => x"15555576",
+1779 => x"149fff06",
+1780 => x"a0807131",
+1781 => x"1670547e",
+1782 => x"53515385",
+1783 => x"933f8008",
+1784 => x"568008ff",
+1785 => x"2e819e38",
+1786 => x"80d68808",
+1787 => x"137080d6",
+1788 => x"880c7475",
+1789 => x"80d6c40b",
+1790 => x"88050c77",
+1791 => x"76311581",
+1792 => x"07555659",
+1793 => x"7a80d6c4",
+1794 => x"2e83c038",
+1795 => x"798f2682",
+1796 => x"ef38810b",
+1797 => x"84150c84",
+1798 => x"1508fc06",
+1799 => x"70793179",
+1800 => x"72268f72",
+1801 => x"25075d55",
+1802 => x"5a7a802e",
+1803 => x"fced3880",
+1804 => x"db398008",
+1805 => x"9fff0655",
+1806 => x"74feed38",
+1807 => x"7880d688",
+1808 => x"0c80d6c4",
+1809 => x"0b880508",
+1810 => x"7a188107",
+1811 => x"84120c55",
+1812 => x"80d6b408",
+1813 => x"79278638",
+1814 => x"7880d6b4",
+1815 => x"0c80d6b0",
+1816 => x"087927fc",
+1817 => x"a0387880",
+1818 => x"d6b00c84",
+1819 => x"1508fc06",
+1820 => x"70793179",
+1821 => x"72268f72",
+1822 => x"25075d55",
+1823 => x"5a7a802e",
+1824 => x"fc993888",
+1825 => x"39807457",
+1826 => x"53fedd39",
+1827 => x"7c5183df",
+1828 => x"3f800b80",
+1829 => x"0c8e3d0d",
+1830 => x"04807324",
+1831 => x"a5387282",
+1832 => x"2c81712b",
+1833 => x"80d6c808",
+1834 => x"077080d6",
+1835 => x"c40b8405",
+1836 => x"0c5c5a76",
+1837 => x"8c170c73",
+1838 => x"88170c75",
+1839 => x"88180cf9",
+1840 => x"fd398313",
+1841 => x"70822c81",
+1842 => x"712b80d6",
+1843 => x"c8080770",
+1844 => x"80d6c40b",
+1845 => x"84050c5d",
+1846 => x"5b53d839",
+1847 => x"7a75065c",
+1848 => x"7bfc9f38",
+1849 => x"84197510",
+1850 => x"5659f139",
+1851 => x"ff178105",
+1852 => x"59f7ab39",
+1853 => x"8c150888",
+1854 => x"1608718c",
+1855 => x"120c8812",
+1856 => x"0c597515",
+1857 => x"84110881",
+1858 => x"0784120c",
+1859 => x"587c5182",
+1860 => x"de3f8815",
+1861 => x"54fba339",
+1862 => x"77167881",
+1863 => x"0784180c",
+1864 => x"8c170888",
+1865 => x"1808718c",
+1866 => x"120c8812",
+1867 => x"0c5c7080",
+1868 => x"d6d80c70",
+1869 => x"80d6d40c",
+1870 => x"80d6cc0b",
+1871 => x"8c120c8c",
+1872 => x"11088812",
+1873 => x"0c778107",
+1874 => x"84120c77",
+1875 => x"0577710c",
+1876 => x"557c5182",
+1877 => x"9a3f8816",
+1878 => x"54f5ba39",
+1879 => x"72168411",
+1880 => x"08810784",
+1881 => x"120c588c",
+1882 => x"16088817",
+1883 => x"08718c12",
+1884 => x"0c88120c",
+1885 => x"577c5181",
+1886 => x"f63f8816",
+1887 => x"54f59639",
+1888 => x"7284150c",
+1889 => x"f41af806",
+1890 => x"70841d08",
+1891 => x"81060784",
+1892 => x"1d0c701c",
+1893 => x"5556850b",
+1894 => x"84150c85",
+1895 => x"0b88150c",
+1896 => x"8f7627fd",
+1897 => x"ab38881b",
+1898 => x"527c5184",
+1899 => x"c13f80d6",
+1900 => x"c40b8805",
+1901 => x"0880d688",
+1902 => x"085a55fd",
+1903 => x"93397880",
+1904 => x"d6880c73",
+1905 => x"80d6b80c",
+1906 => x"fbef3972",
+1907 => x"84150cfc",
+1908 => x"ff39fb3d",
+1909 => x"0d77707a",
+1910 => x"7c585553",
+1911 => x"568f7527",
+1912 => x"80e63872",
+1913 => x"76078306",
+1914 => x"517080dc",
+1915 => x"38757352",
+1916 => x"54707084",
+1917 => x"05520874",
+1918 => x"70840556",
+1919 => x"0c737170",
+1920 => x"84055308",
+1921 => x"71708405",
+1922 => x"530c7170",
+1923 => x"84055308",
+1924 => x"71708405",
+1925 => x"530c7170",
+1926 => x"84055308",
+1927 => x"71708405",
+1928 => x"530cf016",
+1929 => x"5654748f",
+1930 => x"26c73883",
+1931 => x"75279538",
+1932 => x"70708405",
+1933 => x"52087470",
+1934 => x"8405560c",
+1935 => x"fc155574",
+1936 => x"8326ed38",
+1937 => x"73715452",
+1938 => x"ff155170",
+1939 => x"ff2e9838",
+1940 => x"72708105",
+1941 => x"54337270",
+1942 => x"81055434",
+1943 => x"ff115170",
+1944 => x"ff2e0981",
+1945 => x"06ea3875",
+1946 => x"800c873d",
+1947 => x"0d040404",
+1948 => x"70707070",
+1949 => x"800b81b6",
+1950 => x"9c0c7651",
+1951 => x"87cc3f80",
+1952 => x"08538008",
+1953 => x"ff2e8938",
+1954 => x"72800c50",
+1955 => x"50505004",
+1956 => x"81b69c08",
+1957 => x"5473802e",
+1958 => x"ef387574",
+1959 => x"710c5272",
+1960 => x"800c5050",
+1961 => x"505004fb",
+1962 => x"3d0d7779",
+1963 => x"70720783",
+1964 => x"06535452",
+1965 => x"70933871",
+1966 => x"73730854",
+1967 => x"56547173",
+1968 => x"082e80c4",
+1969 => x"38737554",
+1970 => x"52713370",
+1971 => x"81ff0652",
+1972 => x"5470802e",
+1973 => x"9d387233",
+1974 => x"5570752e",
+1975 => x"09810695",
+1976 => x"38811281",
+1977 => x"14713370",
+1978 => x"81ff0654",
+1979 => x"56545270",
+1980 => x"e5387233",
+1981 => x"557381ff",
+1982 => x"067581ff",
+1983 => x"06717131",
+1984 => x"800c5552",
+1985 => x"873d0d04",
+1986 => x"7109f7fb",
+1987 => x"fdff1306",
+1988 => x"f8848281",
+1989 => x"80065271",
+1990 => x"97388414",
+1991 => x"84167108",
+1992 => x"54565471",
+1993 => x"75082ee0",
+1994 => x"38737554",
+1995 => x"52ff9a39",
+1996 => x"800b800c",
+1997 => x"873d0d04",
+1998 => x"fb3d0d77",
+1999 => x"705256fe",
+2000 => x"ad3f80d6",
+2001 => x"c40b8805",
+2002 => x"08841108",
+2003 => x"fc06707b",
+2004 => x"319fef05",
+2005 => x"e08006e0",
+2006 => x"80055255",
+2007 => x"55a08075",
+2008 => x"24943880",
+2009 => x"527551fe",
+2010 => x"873f80d6",
+2011 => x"cc081453",
+2012 => x"7280082e",
+2013 => x"8f387551",
+2014 => x"fdf53f80",
+2015 => x"5372800c",
+2016 => x"873d0d04",
+2017 => x"74305275",
+2018 => x"51fde53f",
+2019 => x"8008ff2e",
+2020 => x"a83880d6",
+2021 => x"c40b8805",
+2022 => x"08747631",
+2023 => x"81078412",
+2024 => x"0c5380d6",
+2025 => x"88087531",
+2026 => x"80d6880c",
+2027 => x"7551fdbf",
+2028 => x"3f810b80",
+2029 => x"0c873d0d",
+2030 => x"04805275",
+2031 => x"51fdb13f",
+2032 => x"80d6c40b",
+2033 => x"88050880",
+2034 => x"08713154",
+2035 => x"548f7325",
+2036 => x"ffa43880",
+2037 => x"0880d6b8",
+2038 => x"083180d6",
+2039 => x"880c7281",
+2040 => x"0784150c",
+2041 => x"7551fd87",
+2042 => x"3f8053ff",
+2043 => x"9039f73d",
+2044 => x"0d7b7d54",
+2045 => x"5a72802e",
+2046 => x"82833879",
+2047 => x"51fcef3f",
+2048 => x"f8138411",
+2049 => x"0870fe06",
+2050 => x"70138411",
+2051 => x"08fc065c",
+2052 => x"57585457",
+2053 => x"80d6cc08",
+2054 => x"742e82de",
+2055 => x"38778415",
+2056 => x"0c807381",
+2057 => x"06565974",
+2058 => x"792e81d5",
+2059 => x"38771484",
+2060 => x"11088106",
+2061 => x"565374a0",
+2062 => x"38771656",
+2063 => x"7881e638",
+2064 => x"88140855",
+2065 => x"7480d6cc",
+2066 => x"2e82f938",
+2067 => x"8c140870",
+2068 => x"8c170c75",
+2069 => x"88120c58",
+2070 => x"75810784",
+2071 => x"180c7517",
+2072 => x"76710c54",
+2073 => x"78819138",
+2074 => x"83ff7627",
+2075 => x"81c83875",
+2076 => x"892a7683",
+2077 => x"2a545473",
+2078 => x"802ebf38",
+2079 => x"75862ab8",
+2080 => x"05538474",
+2081 => x"27b43880",
+2082 => x"db145394",
+2083 => x"7427ab38",
+2084 => x"758c2a80",
+2085 => x"ee055380",
+2086 => x"d474279e",
+2087 => x"38758f2a",
+2088 => x"80f70553",
+2089 => x"82d47427",
+2090 => x"91387592",
+2091 => x"2a80fc05",
+2092 => x"538ad474",
+2093 => x"27843880",
+2094 => x"fe537210",
+2095 => x"101080d6",
+2096 => x"c4058811",
+2097 => x"08555573",
+2098 => x"752e82bf",
+2099 => x"38841408",
+2100 => x"fc065975",
+2101 => x"79278d38",
+2102 => x"88140854",
+2103 => x"73752e09",
+2104 => x"8106ea38",
+2105 => x"8c140870",
+2106 => x"8c190c74",
+2107 => x"88190c77",
+2108 => x"88120c55",
+2109 => x"768c150c",
+2110 => x"7951faf3",
+2111 => x"3f8b3d0d",
+2112 => x"04760877",
+2113 => x"71315876",
+2114 => x"05881808",
+2115 => x"56567480",
+2116 => x"d6cc2e80",
+2117 => x"e0388c17",
+2118 => x"08708c17",
+2119 => x"0c758812",
+2120 => x"0c53fe89",
+2121 => x"39881408",
+2122 => x"8c150870",
+2123 => x"8c130c59",
+2124 => x"88190cfe",
+2125 => x"a3397583",
+2126 => x"2a705454",
+2127 => x"80742481",
+2128 => x"98387282",
+2129 => x"2c81712b",
+2130 => x"80d6c808",
+2131 => x"0780d6c4",
+2132 => x"0b84050c",
+2133 => x"74101010",
+2134 => x"80d6c405",
+2135 => x"88110871",
+2136 => x"8c1b0c70",
+2137 => x"881b0c79",
+2138 => x"88130c56",
+2139 => x"5a55768c",
+2140 => x"150cff84",
+2141 => x"398159fd",
+2142 => x"b4397716",
+2143 => x"73810654",
+2144 => x"55729838",
+2145 => x"76087771",
+2146 => x"31587505",
+2147 => x"8c180888",
+2148 => x"1908718c",
+2149 => x"120c8812",
+2150 => x"0c555574",
+2151 => x"81078418",
+2152 => x"0c7680d6",
+2153 => x"c40b8805",
+2154 => x"0c80d6c0",
+2155 => x"087526fe",
+2156 => x"c73880d6",
+2157 => x"bc085279",
+2158 => x"51fafd3f",
+2159 => x"7951f9af",
+2160 => x"3ffeba39",
+2161 => x"81778c17",
+2162 => x"0c778817",
+2163 => x"0c758c19",
+2164 => x"0c758819",
+2165 => x"0c59fd80",
+2166 => x"39831470",
+2167 => x"822c8171",
+2168 => x"2b80d6c8",
+2169 => x"080780d6",
+2170 => x"c40b8405",
+2171 => x"0c751010",
+2172 => x"1080d6c4",
+2173 => x"05881108",
+2174 => x"718c1c0c",
+2175 => x"70881c0c",
+2176 => x"7a88130c",
+2177 => x"575b5653",
+2178 => x"fee43980",
+2179 => x"7324a338",
+2180 => x"72822c81",
+2181 => x"712b80d6",
+2182 => x"c8080780",
+2183 => x"d6c40b84",
+2184 => x"050c5874",
+2185 => x"8c180c73",
+2186 => x"88180c76",
+2187 => x"88160cfd",
+2188 => x"c3398313",
+2189 => x"70822c81",
+2190 => x"712b80d6",
+2191 => x"c8080780",
+2192 => x"d6c40b84",
+2193 => x"050c5953",
+2194 => x"da397070",
+2195 => x"7080e5f4",
+2196 => x"08893881",
+2197 => x"b6a00b80",
+2198 => x"e5f40c80",
+2199 => x"e5f40875",
+2200 => x"115252ff",
+2201 => x"537087fb",
+2202 => x"80802688",
+2203 => x"387080e5",
+2204 => x"f40c7153",
+2205 => x"72800c50",
+2206 => x"505004fd",
+2207 => x"3d0d800b",
+2208 => x"80d5f408",
+2209 => x"54547281",
+2210 => x"2e9b3873",
+2211 => x"80e5f80c",
+2212 => x"c3ee3fc2",
+2213 => x"eb3f80e5",
+2214 => x"cc528151",
+2215 => x"cc933f80",
+2216 => x"085180dd",
+2217 => x"3f7280e5",
+2218 => x"f80cc3d4",
+2219 => x"3fc2d13f",
+2220 => x"80e5cc52",
+2221 => x"8151cbf9",
+2222 => x"3f800851",
+2223 => x"80c33f00",
+2224 => x"ff3900ff",
+2225 => x"39f43d0d",
+2226 => x"7e80e5ec",
+2227 => x"08700870",
+2228 => x"81ff0692",
+2229 => x"3df80555",
+2230 => x"515a5759",
+2231 => x"c48f3f80",
+2232 => x"5477557b",
+2233 => x"7d585276",
+2234 => x"538e3df0",
+2235 => x"0551de8e",
+2236 => x"3f797b58",
+2237 => x"790c7684",
+2238 => x"1a0c7880",
+2239 => x"0c8e3d0d",
+2240 => x"04f73d0d",
+2241 => x"7b80decc",
+2242 => x"0882c811",
+2243 => x"085a545a",
+2244 => x"77802e80",
+2245 => x"da388188",
+2246 => x"18841908",
+2247 => x"ff058171",
+2248 => x"2b595559",
+2249 => x"80742480",
+2250 => x"ea388074",
+2251 => x"24b53873",
+2252 => x"822b7811",
+2253 => x"88055656",
+2254 => x"81801908",
+2255 => x"77065372",
+2256 => x"802eb638",
+2257 => x"78167008",
+2258 => x"53537951",
+2259 => x"74085372",
+2260 => x"2dff14fc",
+2261 => x"17fc1779",
+2262 => x"812c5a57",
+2263 => x"57547380",
+2264 => x"25d63877",
+2265 => x"085877ff",
+2266 => x"ad3880de",
+2267 => x"cc0853bc",
+2268 => x"1308a538",
+2269 => x"7951fec7",
+2270 => x"3f740853",
+2271 => x"722dff14",
+2272 => x"fc17fc17",
+2273 => x"79812c5a",
+2274 => x"57575473",
+2275 => x"8025ffa8",
+2276 => x"38d13980",
+2277 => x"57ff9339",
+2278 => x"7251bc13",
+2279 => x"0854732d",
+2280 => x"7951fe9b",
+2281 => x"3f707080",
+2282 => x"e5d40bfc",
+2283 => x"05700852",
+2284 => x"5270ff2e",
+2285 => x"9138702d",
+2286 => x"fc127008",
+2287 => x"525270ff",
+2288 => x"2e098106",
+2289 => x"f1385050",
+2290 => x"0404c2ff",
+2291 => x"3f040000",
+2292 => x"00000040",
+2293 => x"30313233",
+2294 => x"34353637",
+2295 => x"38390000",
+2296 => x"44485259",
+2297 => x"53544f4e",
+2298 => x"45205052",
+2299 => x"4f475241",
+2300 => x"4d2c2053",
+2301 => x"4f4d4520",
+2302 => x"53545249",
+2303 => x"4e470000",
+2304 => x"44485259",
+2305 => x"53544f4e",
+2306 => x"45205052",
+2307 => x"4f475241",
+2308 => x"4d2c2031",
+2309 => x"27535420",
+2310 => x"53545249",
+2311 => x"4e470000",
+2312 => x"44687279",
+2313 => x"73746f6e",
+2314 => x"65204265",
+2315 => x"6e63686d",
+2316 => x"61726b2c",
+2317 => x"20566572",
+2318 => x"73696f6e",
+2319 => x"20322e31",
+2320 => x"20284c61",
+2321 => x"6e677561",
+2322 => x"67653a20",
+2323 => x"43290a00",
+2324 => x"50726f67",
+2325 => x"72616d20",
+2326 => x"636f6d70",
+2327 => x"696c6564",
+2328 => x"20776974",
+2329 => x"68202772",
+2330 => x"65676973",
+2331 => x"74657227",
+2332 => x"20617474",
+2333 => x"72696275",
+2334 => x"74650a00",
+2335 => x"45786563",
+2336 => x"7574696f",
+2337 => x"6e207374",
+2338 => x"61727473",
+2339 => x"2c202564",
+2340 => x"2072756e",
+2341 => x"73207468",
+2342 => x"726f7567",
+2343 => x"68204468",
+2344 => x"72797374",
+2345 => x"6f6e650a",
+2346 => x"00000000",
+2347 => x"44485259",
+2348 => x"53544f4e",
+2349 => x"45205052",
+2350 => x"4f475241",
+2351 => x"4d2c2032",
+2352 => x"274e4420",
+2353 => x"53545249",
+2354 => x"4e470000",
+2355 => x"45786563",
+2356 => x"7574696f",
+2357 => x"6e20656e",
+2358 => x"64730a00",
+2359 => x"46696e61",
+2360 => x"6c207661",
+2361 => x"6c756573",
+2362 => x"206f6620",
+2363 => x"74686520",
+2364 => x"76617269",
+2365 => x"61626c65",
+2366 => x"73207573",
+2367 => x"65642069",
+2368 => x"6e207468",
+2369 => x"65206265",
+2370 => x"6e63686d",
+2371 => x"61726b3a",
+2372 => x"0a000000",
+2373 => x"496e745f",
+2374 => x"476c6f62",
+2375 => x"3a202020",
+2376 => x"20202020",
+2377 => x"20202020",
+2378 => x"2025640a",
+2379 => x"00000000",
+2380 => x"20202020",
+2381 => x"20202020",
+2382 => x"73686f75",
+2383 => x"6c642062",
+2384 => x"653a2020",
+2385 => x"2025640a",
+2386 => x"00000000",
+2387 => x"426f6f6c",
+2388 => x"5f476c6f",
+2389 => x"623a2020",
+2390 => x"20202020",
+2391 => x"20202020",
+2392 => x"2025640a",
+2393 => x"00000000",
+2394 => x"43685f31",
+2395 => x"5f476c6f",
+2396 => x"623a2020",
+2397 => x"20202020",
+2398 => x"20202020",
+2399 => x"2025630a",
+2400 => x"00000000",
+2401 => x"20202020",
+2402 => x"20202020",
+2403 => x"73686f75",
+2404 => x"6c642062",
+2405 => x"653a2020",
+2406 => x"2025630a",
+2407 => x"00000000",
+2408 => x"43685f32",
+2409 => x"5f476c6f",
+2410 => x"623a2020",
+2411 => x"20202020",
+2412 => x"20202020",
+2413 => x"2025630a",
+2414 => x"00000000",
+2415 => x"4172725f",
+2416 => x"315f476c",
+2417 => x"6f625b38",
+2418 => x"5d3a2020",
+2419 => x"20202020",
+2420 => x"2025640a",
+2421 => x"00000000",
+2422 => x"4172725f",
+2423 => x"325f476c",
+2424 => x"6f625b38",
+2425 => x"5d5b375d",
+2426 => x"3a202020",
+2427 => x"2025640a",
+2428 => x"00000000",
+2429 => x"20202020",
+2430 => x"20202020",
+2431 => x"73686f75",
+2432 => x"6c642062",
+2433 => x"653a2020",
+2434 => x"204e756d",
+2435 => x"6265725f",
+2436 => x"4f665f52",
+2437 => x"756e7320",
+2438 => x"2b203130",
+2439 => x"0a000000",
+2440 => x"5074725f",
+2441 => x"476c6f62",
+2442 => x"2d3e0a00",
+2443 => x"20205074",
+2444 => x"725f436f",
+2445 => x"6d703a20",
+2446 => x"20202020",
+2447 => x"20202020",
+2448 => x"2025640a",
+2449 => x"00000000",
+2450 => x"20202020",
+2451 => x"20202020",
+2452 => x"73686f75",
+2453 => x"6c642062",
+2454 => x"653a2020",
+2455 => x"2028696d",
+2456 => x"706c656d",
+2457 => x"656e7461",
+2458 => x"74696f6e",
+2459 => x"2d646570",
+2460 => x"656e6465",
+2461 => x"6e74290a",
+2462 => x"00000000",
+2463 => x"20204469",
+2464 => x"7363723a",
+2465 => x"20202020",
+2466 => x"20202020",
+2467 => x"20202020",
+2468 => x"2025640a",
+2469 => x"00000000",
+2470 => x"2020456e",
+2471 => x"756d5f43",
+2472 => x"6f6d703a",
+2473 => x"20202020",
+2474 => x"20202020",
+2475 => x"2025640a",
+2476 => x"00000000",
+2477 => x"2020496e",
+2478 => x"745f436f",
+2479 => x"6d703a20",
+2480 => x"20202020",
+2481 => x"20202020",
+2482 => x"2025640a",
+2483 => x"00000000",
+2484 => x"20205374",
+2485 => x"725f436f",
+2486 => x"6d703a20",
+2487 => x"20202020",
+2488 => x"20202020",
+2489 => x"2025730a",
+2490 => x"00000000",
+2491 => x"20202020",
+2492 => x"20202020",
+2493 => x"73686f75",
+2494 => x"6c642062",
+2495 => x"653a2020",
+2496 => x"20444852",
+2497 => x"5953544f",
+2498 => x"4e452050",
+2499 => x"524f4752",
+2500 => x"414d2c20",
+2501 => x"534f4d45",
+2502 => x"20535452",
+2503 => x"494e470a",
+2504 => x"00000000",
+2505 => x"4e657874",
+2506 => x"5f507472",
+2507 => x"5f476c6f",
+2508 => x"622d3e0a",
+2509 => x"00000000",
+2510 => x"20202020",
+2511 => x"20202020",
+2512 => x"73686f75",
+2513 => x"6c642062",
+2514 => x"653a2020",
+2515 => x"2028696d",
+2516 => x"706c656d",
+2517 => x"656e7461",
+2518 => x"74696f6e",
+2519 => x"2d646570",
+2520 => x"656e6465",
+2521 => x"6e74292c",
+2522 => x"2073616d",
+2523 => x"65206173",
+2524 => x"2061626f",
+2525 => x"76650a00",
+2526 => x"496e745f",
+2527 => x"315f4c6f",
+2528 => x"633a2020",
+2529 => x"20202020",
+2530 => x"20202020",
+2531 => x"2025640a",
+2532 => x"00000000",
+2533 => x"496e745f",
+2534 => x"325f4c6f",
+2535 => x"633a2020",
+2536 => x"20202020",
+2537 => x"20202020",
+2538 => x"2025640a",
+2539 => x"00000000",
+2540 => x"496e745f",
+2541 => x"335f4c6f",
+2542 => x"633a2020",
+2543 => x"20202020",
+2544 => x"20202020",
+2545 => x"2025640a",
+2546 => x"00000000",
+2547 => x"456e756d",
+2548 => x"5f4c6f63",
+2549 => x"3a202020",
+2550 => x"20202020",
+2551 => x"20202020",
+2552 => x"2025640a",
+2553 => x"00000000",
+2554 => x"5374725f",
+2555 => x"315f4c6f",
+2556 => x"633a2020",
+2557 => x"20202020",
+2558 => x"20202020",
+2559 => x"2025730a",
+2560 => x"00000000",
+2561 => x"20202020",
+2562 => x"20202020",
+2563 => x"73686f75",
+2564 => x"6c642062",
+2565 => x"653a2020",
+2566 => x"20444852",
+2567 => x"5953544f",
+2568 => x"4e452050",
+2569 => x"524f4752",
+2570 => x"414d2c20",
+2571 => x"31275354",
+2572 => x"20535452",
+2573 => x"494e470a",
+2574 => x"00000000",
+2575 => x"5374725f",
+2576 => x"325f4c6f",
+2577 => x"633a2020",
+2578 => x"20202020",
+2579 => x"20202020",
+2580 => x"2025730a",
+2581 => x"00000000",
+2582 => x"20202020",
+2583 => x"20202020",
+2584 => x"73686f75",
+2585 => x"6c642062",
+2586 => x"653a2020",
+2587 => x"20444852",
+2588 => x"5953544f",
+2589 => x"4e452050",
+2590 => x"524f4752",
+2591 => x"414d2c20",
+2592 => x"32274e44",
+2593 => x"20535452",
+2594 => x"494e470a",
+2595 => x"00000000",
+2596 => x"55736572",
+2597 => x"2074696d",
+2598 => x"653a2025",
+2599 => x"640a0000",
+2600 => x"4d696372",
+2601 => x"6f736563",
+2602 => x"6f6e6473",
+2603 => x"20666f72",
+2604 => x"206f6e65",
+2605 => x"2072756e",
+2606 => x"20746872",
+2607 => x"6f756768",
+2608 => x"20446872",
+2609 => x"7973746f",
+2610 => x"6e653a20",
+2611 => x"00000000",
+2612 => x"2564200a",
+2613 => x"00000000",
+2614 => x"44687279",
+2615 => x"73746f6e",
+2616 => x"65732070",
+2617 => x"65722053",
+2618 => x"65636f6e",
+2619 => x"643a2020",
+2620 => x"20202020",
+2621 => x"20202020",
+2622 => x"20202020",
+2623 => x"20202020",
+2624 => x"20202020",
+2625 => x"00000000",
+2626 => x"56415820",
+2627 => x"4d495053",
+2628 => x"20726174",
+2629 => x"696e6720",
+2630 => x"2a203130",
+2631 => x"3030203d",
+2632 => x"20256420",
+2633 => x"0a000000",
+2634 => x"50726f67",
+2635 => x"72616d20",
+2636 => x"636f6d70",
+2637 => x"696c6564",
+2638 => x"20776974",
+2639 => x"686f7574",
+2640 => x"20277265",
+2641 => x"67697374",
+2642 => x"65722720",
+2643 => x"61747472",
+2644 => x"69627574",
+2645 => x"650a0000",
+2646 => x"4d656173",
+2647 => x"75726564",
+2648 => x"2074696d",
+2649 => x"6520746f",
+2650 => x"6f20736d",
+2651 => x"616c6c20",
+2652 => x"746f206f",
+2653 => x"62746169",
+2654 => x"6e206d65",
+2655 => x"616e696e",
+2656 => x"6766756c",
+2657 => x"20726573",
+2658 => x"756c7473",
+2659 => x"0a000000",
+2660 => x"506c6561",
+2661 => x"73652069",
+2662 => x"6e637265",
+2663 => x"61736520",
+2664 => x"6e756d62",
+2665 => x"6572206f",
+2666 => x"66207275",
+2667 => x"6e730a00",
+2668 => x"44485259",
+2669 => x"53544f4e",
+2670 => x"45205052",
+2671 => x"4f475241",
+2672 => x"4d2c2033",
+2673 => x"27524420",
+2674 => x"53545249",
+2675 => x"4e470000",
+2676 => x"00010202",
+2677 => x"03030303",
+2678 => x"04040404",
+2679 => x"04040404",
+2680 => x"05050505",
+2681 => x"05050505",
+2682 => x"05050505",
+2683 => x"05050505",
+2684 => x"06060606",
+2685 => x"06060606",
+2686 => x"06060606",
+2687 => x"06060606",
+2688 => x"06060606",
+2689 => x"06060606",
+2690 => x"06060606",
+2691 => x"06060606",
+2692 => x"07070707",
+2693 => x"07070707",
+2694 => x"07070707",
+2695 => x"07070707",
+2696 => x"07070707",
+2697 => x"07070707",
+2698 => x"07070707",
+2699 => x"07070707",
+2700 => x"07070707",
+2701 => x"07070707",
+2702 => x"07070707",
+2703 => x"07070707",
+2704 => x"07070707",
+2705 => x"07070707",
+2706 => x"07070707",
+2707 => x"07070707",
+2708 => x"08080808",
+2709 => x"08080808",
+2710 => x"08080808",
+2711 => x"08080808",
+2712 => x"08080808",
+2713 => x"08080808",
+2714 => x"08080808",
+2715 => x"08080808",
+2716 => x"08080808",
+2717 => x"08080808",
+2718 => x"08080808",
+2719 => x"08080808",
+2720 => x"08080808",
+2721 => x"08080808",
+2722 => x"08080808",
+2723 => x"08080808",
+2724 => x"08080808",
+2725 => x"08080808",
+2726 => x"08080808",
+2727 => x"08080808",
+2728 => x"08080808",
+2729 => x"08080808",
+2730 => x"08080808",
+2731 => x"08080808",
+2732 => x"08080808",
+2733 => x"08080808",
+2734 => x"08080808",
+2735 => x"08080808",
+2736 => x"08080808",
+2737 => x"08080808",
+2738 => x"08080808",
+2739 => x"08080808",
+2740 => x"43000000",
+2741 => x"64756d6d",
+2742 => x"792e6578",
+2743 => x"65000000",
+2744 => x"00ffffff",
+2745 => x"ff00ffff",
+2746 => x"ffff00ff",
+2747 => x"ffffff00",
+2748 => x"00000000",
+2749 => x"00000000",
+2750 => x"00000000",
+2751 => x"000032dc",
+2752 => x"0000c350",
+2753 => x"00000000",
+2754 => x"00000000",
+2755 => x"00000000",
+2756 => x"00000000",
+2757 => x"00000000",
+2758 => x"00000000",
+2759 => x"00000000",
+2760 => x"00000000",
+2761 => x"00000000",
+2762 => x"00000000",
+2763 => x"00000000",
+2764 => x"00000000",
+2765 => x"00000000",
+2766 => x"ffffffff",
+2767 => x"00000000",
+2768 => x"00020000",
+2769 => x"00000000",
+2770 => x"00000000",
+2771 => x"00002b44",
+2772 => x"00002b44",
+2773 => x"00002b4c",
+2774 => x"00002b4c",
+2775 => x"00002b54",
+2776 => x"00002b54",
+2777 => x"00002b5c",
+2778 => x"00002b5c",
+2779 => x"00002b64",
+2780 => x"00002b64",
+2781 => x"00002b6c",
+2782 => x"00002b6c",
+2783 => x"00002b74",
+2784 => x"00002b74",
+2785 => x"00002b7c",
+2786 => x"00002b7c",
+2787 => x"00002b84",
+2788 => x"00002b84",
+2789 => x"00002b8c",
+2790 => x"00002b8c",
+2791 => x"00002b94",
+2792 => x"00002b94",
+2793 => x"00002b9c",
+2794 => x"00002b9c",
+2795 => x"00002ba4",
+2796 => x"00002ba4",
+2797 => x"00002bac",
+2798 => x"00002bac",
+2799 => x"00002bb4",
+2800 => x"00002bb4",
+2801 => x"00002bbc",
+2802 => x"00002bbc",
+2803 => x"00002bc4",
+2804 => x"00002bc4",
+2805 => x"00002bcc",
+2806 => x"00002bcc",
+2807 => x"00002bd4",
+2808 => x"00002bd4",
+2809 => x"00002bdc",
+2810 => x"00002bdc",
+2811 => x"00002be4",
+2812 => x"00002be4",
+2813 => x"00002bec",
+2814 => x"00002bec",
+2815 => x"00002bf4",
+2816 => x"00002bf4",
+2817 => x"00002bfc",
+2818 => x"00002bfc",
+2819 => x"00002c04",
+2820 => x"00002c04",
+2821 => x"00002c0c",
+2822 => x"00002c0c",
+2823 => x"00002c14",
+2824 => x"00002c14",
+2825 => x"00002c1c",
+2826 => x"00002c1c",
+2827 => x"00002c24",
+2828 => x"00002c24",
+2829 => x"00002c2c",
+2830 => x"00002c2c",
+2831 => x"00002c34",
+2832 => x"00002c34",
+2833 => x"00002c3c",
+2834 => x"00002c3c",
+2835 => x"00002c44",
+2836 => x"00002c44",
+2837 => x"00002c4c",
+2838 => x"00002c4c",
+2839 => x"00002c54",
+2840 => x"00002c54",
+2841 => x"00002c5c",
+2842 => x"00002c5c",
+2843 => x"00002c64",
+2844 => x"00002c64",
+2845 => x"00002c6c",
+2846 => x"00002c6c",
+2847 => x"00002c74",
+2848 => x"00002c74",
+2849 => x"00002c7c",
+2850 => x"00002c7c",
+2851 => x"00002c84",
+2852 => x"00002c84",
+2853 => x"00002c8c",
+2854 => x"00002c8c",
+2855 => x"00002c94",
+2856 => x"00002c94",
+2857 => x"00002c9c",
+2858 => x"00002c9c",
+2859 => x"00002ca4",
+2860 => x"00002ca4",
+2861 => x"00002cac",
+2862 => x"00002cac",
+2863 => x"00002cb4",
+2864 => x"00002cb4",
+2865 => x"00002cbc",
+2866 => x"00002cbc",
+2867 => x"00002cc4",
+2868 => x"00002cc4",
+2869 => x"00002ccc",
+2870 => x"00002ccc",
+2871 => x"00002cd4",
+2872 => x"00002cd4",
+2873 => x"00002cdc",
+2874 => x"00002cdc",
+2875 => x"00002ce4",
+2876 => x"00002ce4",
+2877 => x"00002cec",
+2878 => x"00002cec",
+2879 => x"00002cf4",
+2880 => x"00002cf4",
+2881 => x"00002cfc",
+2882 => x"00002cfc",
+2883 => x"00002d04",
+2884 => x"00002d04",
+2885 => x"00002d0c",
+2886 => x"00002d0c",
+2887 => x"00002d14",
+2888 => x"00002d14",
+2889 => x"00002d1c",
+2890 => x"00002d1c",
+2891 => x"00002d24",
+2892 => x"00002d24",
+2893 => x"00002d2c",
+2894 => x"00002d2c",
+2895 => x"00002d34",
+2896 => x"00002d34",
+2897 => x"00002d3c",
+2898 => x"00002d3c",
+2899 => x"00002d44",
+2900 => x"00002d44",
+2901 => x"00002d4c",
+2902 => x"00002d4c",
+2903 => x"00002d54",
+2904 => x"00002d54",
+2905 => x"00002d5c",
+2906 => x"00002d5c",
+2907 => x"00002d64",
+2908 => x"00002d64",
+2909 => x"00002d6c",
+2910 => x"00002d6c",
+2911 => x"00002d74",
+2912 => x"00002d74",
+2913 => x"00002d7c",
+2914 => x"00002d7c",
+2915 => x"00002d84",
+2916 => x"00002d84",
+2917 => x"00002d8c",
+2918 => x"00002d8c",
+2919 => x"00002d94",
+2920 => x"00002d94",
+2921 => x"00002d9c",
+2922 => x"00002d9c",
+2923 => x"00002da4",
+2924 => x"00002da4",
+2925 => x"00002dac",
+2926 => x"00002dac",
+2927 => x"00002db4",
+2928 => x"00002db4",
+2929 => x"00002dbc",
+2930 => x"00002dbc",
+2931 => x"00002dc4",
+2932 => x"00002dc4",
+2933 => x"00002dcc",
+2934 => x"00002dcc",
+2935 => x"00002dd4",
+2936 => x"00002dd4",
+2937 => x"00002ddc",
+2938 => x"00002ddc",
+2939 => x"00002de4",
+2940 => x"00002de4",
+2941 => x"00002dec",
+2942 => x"00002dec",
+2943 => x"00002df4",
+2944 => x"00002df4",
+2945 => x"00002dfc",
+2946 => x"00002dfc",
+2947 => x"00002e04",
+2948 => x"00002e04",
+2949 => x"00002e0c",
+2950 => x"00002e0c",
+2951 => x"00002e14",
+2952 => x"00002e14",
+2953 => x"00002e1c",
+2954 => x"00002e1c",
+2955 => x"00002e24",
+2956 => x"00002e24",
+2957 => x"00002e2c",
+2958 => x"00002e2c",
+2959 => x"00002e34",
+2960 => x"00002e34",
+2961 => x"00002e3c",
+2962 => x"00002e3c",
+2963 => x"00002e44",
+2964 => x"00002e44",
+2965 => x"00002e4c",
+2966 => x"00002e4c",
+2967 => x"00002e54",
+2968 => x"00002e54",
+2969 => x"00002e5c",
+2970 => x"00002e5c",
+2971 => x"00002e64",
+2972 => x"00002e64",
+2973 => x"00002e6c",
+2974 => x"00002e6c",
+2975 => x"00002e74",
+2976 => x"00002e74",
+2977 => x"00002e7c",
+2978 => x"00002e7c",
+2979 => x"00002e84",
+2980 => x"00002e84",
+2981 => x"00002e8c",
+2982 => x"00002e8c",
+2983 => x"00002e94",
+2984 => x"00002e94",
+2985 => x"00002e9c",
+2986 => x"00002e9c",
+2987 => x"00002ea4",
+2988 => x"00002ea4",
+2989 => x"00002eac",
+2990 => x"00002eac",
+2991 => x"00002eb4",
+2992 => x"00002eb4",
+2993 => x"00002ebc",
+2994 => x"00002ebc",
+2995 => x"00002ec4",
+2996 => x"00002ec4",
+2997 => x"00002ecc",
+2998 => x"00002ecc",
+2999 => x"00002ed4",
+3000 => x"00002ed4",
+3001 => x"00002edc",
+3002 => x"00002edc",
+3003 => x"00002ee4",
+3004 => x"00002ee4",
+3005 => x"00002eec",
+3006 => x"00002eec",
+3007 => x"00002ef4",
+3008 => x"00002ef4",
+3009 => x"00002efc",
+3010 => x"00002efc",
+3011 => x"00002f04",
+3012 => x"00002f04",
+3013 => x"00002f0c",
+3014 => x"00002f0c",
+3015 => x"00002f14",
+3016 => x"00002f14",
+3017 => x"00002f1c",
+3018 => x"00002f1c",
+3019 => x"00002f24",
+3020 => x"00002f24",
+3021 => x"00002f2c",
+3022 => x"00002f2c",
+3023 => x"00002f34",
+3024 => x"00002f34",
+3025 => x"00002f3c",
+3026 => x"00002f3c",
+3027 => x"00002f50",
+3028 => x"00000000",
+3029 => x"000031b8",
+3030 => x"00003214",
+3031 => x"00003270",
+3032 => x"00000000",
+3033 => x"00000000",
+3034 => x"00000000",
+3035 => x"00000000",
+3036 => x"00000000",
+3037 => x"00000000",
+3038 => x"00000000",
+3039 => x"00000000",
+3040 => x"00000000",
+3041 => x"00002ad0",
+3042 => x"00000000",
+3043 => x"00000000",
+3044 => x"00000000",
+3045 => x"00000000",
+3046 => x"00000000",
+3047 => x"00000000",
+3048 => x"00000000",
+3049 => x"00000000",
+3050 => x"00000000",
+3051 => x"00000000",
+3052 => x"00000000",
+3053 => x"00000000",
+3054 => x"00000000",
+3055 => x"00000000",
+3056 => x"00000000",
+3057 => x"00000000",
+3058 => x"00000000",
+3059 => x"00000000",
+3060 => x"00000000",
+3061 => x"00000000",
+3062 => x"00000000",
+3063 => x"00000000",
+3064 => x"00000000",
+3065 => x"00000000",
+3066 => x"00000000",
+3067 => x"00000000",
+3068 => x"00000000",
+3069 => x"00000000",
+3070 => x"00000001",
+3071 => x"330eabcd",
+3072 => x"1234e66d",
+3073 => x"deec0005",
+3074 => x"000b0000",
+3075 => x"00000000",
+3076 => x"00000000",
+3077 => x"00000000",
+3078 => x"00000000",
+3079 => x"00000000",
+3080 => x"00000000",
+3081 => x"00000000",
+3082 => x"00000000",
+3083 => x"00000000",
+3084 => x"00000000",
+3085 => x"00000000",
+3086 => x"00000000",
+3087 => x"00000000",
+3088 => x"00000000",
+3089 => x"00000000",
+3090 => x"00000000",
+3091 => x"00000000",
+3092 => x"00000000",
+3093 => x"00000000",
+3094 => x"00000000",
+3095 => x"00000000",
+3096 => x"00000000",
+3097 => x"00000000",
+3098 => x"00000000",
+3099 => x"00000000",
+3100 => x"00000000",
+3101 => x"00000000",
+3102 => x"00000000",
+3103 => x"00000000",
+3104 => x"00000000",
+3105 => x"00000000",
+3106 => x"00000000",
+3107 => x"00000000",
+3108 => x"00000000",
+3109 => x"00000000",
+3110 => x"00000000",
+3111 => x"00000000",
+3112 => x"00000000",
+3113 => x"00000000",
+3114 => x"00000000",
+3115 => x"00000000",
+3116 => x"00000000",
+3117 => x"00000000",
+3118 => x"00000000",
+3119 => x"00000000",
+3120 => x"00000000",
+3121 => x"00000000",
+3122 => x"00000000",
+3123 => x"00000000",
+3124 => x"00000000",
+3125 => x"00000000",
+3126 => x"00000000",
+3127 => x"00000000",
+3128 => x"00000000",
+3129 => x"00000000",
+3130 => x"00000000",
+3131 => x"00000000",
+3132 => x"00000000",
+3133 => x"00000000",
+3134 => x"00000000",
+3135 => x"00000000",
+3136 => x"00000000",
+3137 => x"00000000",
+3138 => x"00000000",
+3139 => x"00000000",
+3140 => x"00000000",
+3141 => x"00000000",
+3142 => x"00000000",
+3143 => x"00000000",
+3144 => x"00000000",
+3145 => x"00000000",
+3146 => x"00000000",
+3147 => x"00000000",
+3148 => x"00000000",
+3149 => x"00000000",
+3150 => x"00000000",
+3151 => x"00000000",
+3152 => x"00000000",
+3153 => x"00000000",
+3154 => x"00000000",
+3155 => x"00000000",
+3156 => x"00000000",
+3157 => x"00000000",
+3158 => x"00000000",
+3159 => x"00000000",
+3160 => x"00000000",
+3161 => x"00000000",
+3162 => x"00000000",
+3163 => x"00000000",
+3164 => x"00000000",
+3165 => x"00000000",
+3166 => x"00000000",
+3167 => x"00000000",
+3168 => x"00000000",
+3169 => x"00000000",
+3170 => x"00000000",
+3171 => x"00000000",
+3172 => x"00000000",
+3173 => x"00000000",
+3174 => x"00000000",
+3175 => x"00000000",
+3176 => x"00000000",
+3177 => x"00000000",
+3178 => x"00000000",
+3179 => x"00000000",
+3180 => x"00000000",
+3181 => x"00000000",
+3182 => x"00000000",
+3183 => x"00000000",
+3184 => x"00000000",
+3185 => x"00000000",
+3186 => x"00000000",
+3187 => x"00000000",
+3188 => x"00000000",
+3189 => x"00000000",
+3190 => x"00000000",
+3191 => x"00000000",
+3192 => x"00000000",
+3193 => x"00000000",
+3194 => x"00000000",
+3195 => x"00000000",
+3196 => x"00000000",
+3197 => x"00000000",
+3198 => x"00000000",
+3199 => x"00000000",
+3200 => x"00000000",
+3201 => x"00000000",
+3202 => x"00000000",
+3203 => x"00000000",
+3204 => x"00000000",
+3205 => x"00000000",
+3206 => x"00000000",
+3207 => x"00000000",
+3208 => x"00000000",
+3209 => x"00000000",
+3210 => x"00000000",
+3211 => x"00000000",
+3212 => x"00000000",
+3213 => x"00000000",
+3214 => x"00000000",
+3215 => x"00000000",
+3216 => x"00000000",
+3217 => x"00000000",
+3218 => x"00000000",
+3219 => x"00000000",
+3220 => x"00000000",
+3221 => x"00000000",
+3222 => x"00000000",
+3223 => x"00000000",
+3224 => x"00000000",
+3225 => x"00000000",
+3226 => x"00000000",
+3227 => x"00000000",
+3228 => x"00000000",
+3229 => x"00000000",
+3230 => x"00000000",
+3231 => x"00000000",
+3232 => x"00000000",
+3233 => x"00000000",
+3234 => x"00000000",
+3235 => x"00000000",
+3236 => x"00000000",
+3237 => x"00000000",
+3238 => x"00000000",
+3239 => x"00000000",
+3240 => x"00000000",
+3241 => x"00000000",
+3242 => x"00000000",
+3243 => x"00000000",
+3244 => x"00000000",
+3245 => x"00000000",
+3246 => x"00000000",
+3247 => x"00000000",
+3248 => x"00000000",
+3249 => x"00000000",
+3250 => x"00000000",
+3251 => x"00002ad4",
+3252 => x"ffffffff",
+3253 => x"00000000",
+3254 => x"ffffffff",
+3255 => x"00000000",
+ others => x"00000000"
+);
+
+begin
+
+mem_busy<=mem_readEnable; -- we're done on the cycle after we serve the read request
+
+process (clk, areset)
+begin
+ if areset = '1' then
+ elsif (clk'event and clk = '1') then
+ if (mem_writeEnable = '1') then
+ ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit)))) := mem_write;
+ end if;
+ if (mem_readEnable = '1') then
+ mem_read <= ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit))));
+ end if;
+ end if;
+end process;
+
+
+
+
+end dram_arch;
diff --git a/zpu/hdl/example_medium/dram_hello.vhd b/zpu/hdl/example_medium/dram_hello.vhd
new file mode 100644
index 0000000..aae18fd
--- /dev/null
+++ b/zpu/hdl/example_medium/dram_hello.vhd
@@ -0,0 +1,3107 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity dram is
+port (clk : in std_logic;
+areset : std_logic;
+ mem_writeEnable : in std_logic;
+ mem_readEnable : in std_logic;
+ mem_addr : in std_logic_vector(maxAddrBit downto 0);
+ mem_write : in std_logic_vector(wordSize-1 downto 0);
+ mem_read : out std_logic_vector(wordSize-1 downto 0);
+ mem_busy : out std_logic;
+ mem_writeMask : in std_logic_vector(wordBytes-1 downto 0));
+end dram;
+
+architecture dram_arch of dram is
+
+
+type ram_type is array(natural range 0 to ((2**(maxAddrBitDRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
+
+shared variable ram : ram_type :=
+(
+0 => x"0b0b0b0b",
+1 => x"82700b0b",
+2 => x"80cfd80c",
+3 => x"3a0b0b80",
+4 => x"c6d00400",
+5 => x"00000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"80c7972d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
+17 => x"72830609",
+18 => x"81058205",
+19 => x"832b2a83",
+20 => x"ffff0652",
+21 => x"04000000",
+22 => x"00000000",
+23 => x"00000000",
+24 => x"71fd0608",
+25 => x"83ffff73",
+26 => x"83060981",
+27 => x"05820583",
+28 => x"2b2b0906",
+29 => x"7383ffff",
+30 => x"0b0b0b0b",
+31 => x"83a70400",
+32 => x"72098105",
+33 => x"72057373",
+34 => x"09060906",
+35 => x"73097306",
+36 => x"070a8106",
+37 => x"53510400",
+38 => x"00000000",
+39 => x"00000000",
+40 => x"72722473",
+41 => x"732e0753",
+42 => x"51040000",
+43 => x"00000000",
+44 => x"00000000",
+45 => x"00000000",
+46 => x"00000000",
+47 => x"00000000",
+48 => x"71737109",
+49 => x"71068106",
+50 => x"30720a10",
+51 => x"0a720a10",
+52 => x"0a31050a",
+53 => x"81065151",
+54 => x"53510400",
+55 => x"00000000",
+56 => x"72722673",
+57 => x"732e0753",
+58 => x"51040000",
+59 => x"00000000",
+60 => x"00000000",
+61 => x"00000000",
+62 => x"00000000",
+63 => x"00000000",
+64 => x"00000000",
+65 => x"00000000",
+66 => x"00000000",
+67 => x"00000000",
+68 => x"00000000",
+69 => x"00000000",
+70 => x"00000000",
+71 => x"00000000",
+72 => x"0b0b0b88",
+73 => x"c4040000",
+74 => x"00000000",
+75 => x"00000000",
+76 => x"00000000",
+77 => x"00000000",
+78 => x"00000000",
+79 => x"00000000",
+80 => x"720a722b",
+81 => x"0a535104",
+82 => x"00000000",
+83 => x"00000000",
+84 => x"00000000",
+85 => x"00000000",
+86 => x"00000000",
+87 => x"00000000",
+88 => x"72729f06",
+89 => x"0981050b",
+90 => x"0b0b88a7",
+91 => x"05040000",
+92 => x"00000000",
+93 => x"00000000",
+94 => x"00000000",
+95 => x"00000000",
+96 => x"72722aff",
+97 => x"739f062a",
+98 => x"0974090a",
+99 => x"8106ff05",
+100 => x"06075351",
+101 => x"04000000",
+102 => x"00000000",
+103 => x"00000000",
+104 => x"71715351",
+105 => x"020d0406",
+106 => x"73830609",
+107 => x"81058205",
+108 => x"832b0b2b",
+109 => x"0772fc06",
+110 => x"0c515104",
+111 => x"00000000",
+112 => x"72098105",
+113 => x"72050970",
+114 => x"81050906",
+115 => x"0a810653",
+116 => x"51040000",
+117 => x"00000000",
+118 => x"00000000",
+119 => x"00000000",
+120 => x"72098105",
+121 => x"72050970",
+122 => x"81050906",
+123 => x"0a098106",
+124 => x"53510400",
+125 => x"00000000",
+126 => x"00000000",
+127 => x"00000000",
+128 => x"71098105",
+129 => x"52040000",
+130 => x"00000000",
+131 => x"00000000",
+132 => x"00000000",
+133 => x"00000000",
+134 => x"00000000",
+135 => x"00000000",
+136 => x"72720981",
+137 => x"05055351",
+138 => x"04000000",
+139 => x"00000000",
+140 => x"00000000",
+141 => x"00000000",
+142 => x"00000000",
+143 => x"00000000",
+144 => x"72097206",
+145 => x"73730906",
+146 => x"07535104",
+147 => x"00000000",
+148 => x"00000000",
+149 => x"00000000",
+150 => x"00000000",
+151 => x"00000000",
+152 => x"71fc0608",
+153 => x"72830609",
+154 => x"81058305",
+155 => x"1010102a",
+156 => x"81ff0652",
+157 => x"04000000",
+158 => x"00000000",
+159 => x"00000000",
+160 => x"71fc0608",
+161 => x"0b0b80cf",
+162 => x"c4738306",
+163 => x"10100508",
+164 => x"060b0b0b",
+165 => x"88aa0400",
+166 => x"00000000",
+167 => x"00000000",
+168 => x"80088408",
+169 => x"88087575",
+170 => x"0b0b0b8b",
+171 => x"9f2d5050",
+172 => x"80085688",
+173 => x"0c840c80",
+174 => x"0c510400",
+175 => x"00000000",
+176 => x"80088408",
+177 => x"88087575",
+178 => x"0b0b0b8b",
+179 => x"e32d5050",
+180 => x"80085688",
+181 => x"0c840c80",
+182 => x"0c510400",
+183 => x"00000000",
+184 => x"72097081",
+185 => x"0509060a",
+186 => x"8106ff05",
+187 => x"70547106",
+188 => x"73097274",
+189 => x"05ff0506",
+190 => x"07515151",
+191 => x"04000000",
+192 => x"72097081",
+193 => x"0509060a",
+194 => x"098106ff",
+195 => x"05705471",
+196 => x"06730972",
+197 => x"7405ff05",
+198 => x"06075151",
+199 => x"51040000",
+200 => x"05ff0504",
+201 => x"00000000",
+202 => x"00000000",
+203 => x"00000000",
+204 => x"00000000",
+205 => x"00000000",
+206 => x"00000000",
+207 => x"00000000",
+208 => x"810b0b0b",
+209 => x"80cfd40c",
+210 => x"51040000",
+211 => x"00000000",
+212 => x"00000000",
+213 => x"00000000",
+214 => x"00000000",
+215 => x"00000000",
+216 => x"71810552",
+217 => x"04000000",
+218 => x"00000000",
+219 => x"00000000",
+220 => x"00000000",
+221 => x"00000000",
+222 => x"00000000",
+223 => x"00000000",
+224 => x"00000000",
+225 => x"00000000",
+226 => x"00000000",
+227 => x"00000000",
+228 => x"00000000",
+229 => x"00000000",
+230 => x"00000000",
+231 => x"00000000",
+232 => x"02840572",
+233 => x"10100552",
+234 => x"04000000",
+235 => x"00000000",
+236 => x"00000000",
+237 => x"00000000",
+238 => x"00000000",
+239 => x"00000000",
+240 => x"00000000",
+241 => x"00000000",
+242 => x"00000000",
+243 => x"00000000",
+244 => x"00000000",
+245 => x"00000000",
+246 => x"00000000",
+247 => x"00000000",
+248 => x"717105ff",
+249 => x"05715351",
+250 => x"020d0400",
+251 => x"00000000",
+252 => x"00000000",
+253 => x"00000000",
+254 => x"00000000",
+255 => x"00000000",
+256 => x"82c53f80",
+257 => x"c6d93f04",
+258 => x"10101010",
+259 => x"10101010",
+260 => x"10101010",
+261 => x"10101010",
+262 => x"10101010",
+263 => x"10101010",
+264 => x"10101010",
+265 => x"10101053",
+266 => x"51047381",
+267 => x"ff067383",
+268 => x"06098105",
+269 => x"83051010",
+270 => x"102b0772",
+271 => x"fc060c51",
+272 => x"51043c04",
+273 => x"72728072",
+274 => x"8106ff05",
+275 => x"09720605",
+276 => x"71105272",
+277 => x"0a100a53",
+278 => x"72ed3851",
+279 => x"51535104",
+280 => x"fe3d0d0b",
+281 => x"0b80dfc0",
+282 => x"08538413",
+283 => x"0870882a",
+284 => x"70810651",
+285 => x"52527080",
+286 => x"2ef03871",
+287 => x"81ff0680",
+288 => x"0c843d0d",
+289 => x"04ff3d0d",
+290 => x"0b0b80df",
+291 => x"c0085271",
+292 => x"0870882a",
+293 => x"81327081",
+294 => x"06515151",
+295 => x"70f13873",
+296 => x"720c833d",
+297 => x"0d0480cf",
+298 => x"d408802e",
+299 => x"a43880cf",
+300 => x"d808822e",
+301 => x"bd388380",
+302 => x"800b0b0b",
+303 => x"80dfc00c",
+304 => x"82a0800b",
+305 => x"80dfc40c",
+306 => x"8290800b",
+307 => x"80dfc80c",
+308 => x"04f88080",
+309 => x"80a40b0b",
+310 => x"0b80dfc0",
+311 => x"0cf88080",
+312 => x"82800b80",
+313 => x"dfc40cf8",
+314 => x"80808480",
+315 => x"0b80dfc8",
+316 => x"0c0480c0",
+317 => x"a8808c0b",
+318 => x"0b0b80df",
+319 => x"c00c80c0",
+320 => x"a880940b",
+321 => x"80dfc40c",
+322 => x"0b0b80cf",
+323 => x"8c0b80df",
+324 => x"c80c0470",
+325 => x"7080dfcc",
+326 => x"335170a7",
+327 => x"3880cfe0",
+328 => x"08700852",
+329 => x"5270802e",
+330 => x"94388412",
+331 => x"80cfe00c",
+332 => x"702d80cf",
+333 => x"e0087008",
+334 => x"525270ee",
+335 => x"38810b80",
+336 => x"dfcc3450",
+337 => x"50040470",
+338 => x"0b0b80df",
+339 => x"bc08802e",
+340 => x"8e380b0b",
+341 => x"0b0b800b",
+342 => x"802e0981",
+343 => x"06833850",
+344 => x"040b0b80",
+345 => x"dfbc510b",
+346 => x"0b0bf594",
+347 => x"3f500404",
+348 => x"fe3d0d89",
+349 => x"5380cf90",
+350 => x"5182c13f",
+351 => x"80cfa051",
+352 => x"82ba3f81",
+353 => x"0a0b80df",
+354 => x"d80cff0b",
+355 => x"80dfdc0c",
+356 => x"ff135372",
+357 => x"8025de38",
+358 => x"72800c84",
+359 => x"3d0d04fb",
+360 => x"3d0d7779",
+361 => x"55558056",
+362 => x"757524ab",
+363 => x"38807424",
+364 => x"9d388053",
+365 => x"73527451",
+366 => x"80e13f80",
+367 => x"08547580",
+368 => x"2e853880",
+369 => x"08305473",
+370 => x"800c873d",
+371 => x"0d047330",
+372 => x"76813257",
+373 => x"54dc3974",
+374 => x"30558156",
+375 => x"738025d2",
+376 => x"38ec39fa",
+377 => x"3d0d787a",
+378 => x"57558057",
+379 => x"767524a4",
+380 => x"38759f2c",
+381 => x"54815375",
+382 => x"74327431",
+383 => x"5274519b",
+384 => x"3f800854",
+385 => x"76802e85",
+386 => x"38800830",
+387 => x"5473800c",
+388 => x"883d0d04",
+389 => x"74305581",
+390 => x"57d739fc",
+391 => x"3d0d7678",
+392 => x"53548153",
+393 => x"80747326",
+394 => x"52557280",
+395 => x"2e983870",
+396 => x"802eab38",
+397 => x"807224a6",
+398 => x"38711073",
+399 => x"10757226",
+400 => x"53545272",
+401 => x"ea387351",
+402 => x"78833874",
+403 => x"5170800c",
+404 => x"863d0d04",
+405 => x"720a100a",
+406 => x"720a100a",
+407 => x"53537280",
+408 => x"2ee43871",
+409 => x"7426ed38",
+410 => x"73723175",
+411 => x"7407740a",
+412 => x"100a740a",
+413 => x"100a5555",
+414 => x"5654e339",
+415 => x"f73d0d7c",
+416 => x"70525380",
+417 => x"f93f7254",
+418 => x"80085580",
+419 => x"cfb05681",
+420 => x"57800881",
+421 => x"055a8b3d",
+422 => x"e4115953",
+423 => x"8259f413",
+424 => x"527b8811",
+425 => x"08525381",
+426 => x"b23f8008",
+427 => x"30708008",
+428 => x"079f2c8a",
+429 => x"07800c53",
+430 => x"8b3d0d04",
+431 => x"f63d0d7c",
+432 => x"80cfe408",
+433 => x"71535553",
+434 => x"b53f7255",
+435 => x"80085680",
+436 => x"cfb05781",
+437 => x"58800881",
+438 => x"055b8c3d",
+439 => x"e4115a53",
+440 => x"825af413",
+441 => x"52881408",
+442 => x"5180f03f",
+443 => x"80083070",
+444 => x"8008079f",
+445 => x"2c8a0780",
+446 => x"0c548c3d",
+447 => x"0d047070",
+448 => x"70707570",
+449 => x"71830653",
+450 => x"555270b4",
+451 => x"38717008",
+452 => x"7009f7fb",
+453 => x"fdff1206",
+454 => x"f8848281",
+455 => x"80065452",
+456 => x"53719b38",
+457 => x"84137008",
+458 => x"7009f7fb",
+459 => x"fdff1206",
+460 => x"f8848281",
+461 => x"80065452",
+462 => x"5371802e",
+463 => x"e7387252",
+464 => x"71335372",
+465 => x"802e8a38",
+466 => x"81127033",
+467 => x"545272f8",
+468 => x"38717431",
+469 => x"800c5050",
+470 => x"505004f2",
+471 => x"3d0d6062",
+472 => x"88110870",
+473 => x"58565f5a",
+474 => x"73802e81",
+475 => x"8c388c1a",
+476 => x"2270832a",
+477 => x"81328106",
+478 => x"56587486",
+479 => x"38901a08",
+480 => x"91387951",
+481 => x"90b73fff",
+482 => x"55800880",
+483 => x"ec388c1a",
+484 => x"22587d08",
+485 => x"55807883",
+486 => x"ffff0670",
+487 => x"0a100a81",
+488 => x"06415c57",
+489 => x"7e772e80",
+490 => x"d7387690",
+491 => x"38740884",
+492 => x"16088817",
+493 => x"57585676",
+494 => x"802ef238",
+495 => x"76548880",
+496 => x"77278438",
+497 => x"88805473",
+498 => x"5375529c",
+499 => x"1a0851a4",
+500 => x"1a085877",
+501 => x"2d800b80",
+502 => x"082582e0",
+503 => x"38800816",
+504 => x"77800831",
+505 => x"7f880508",
+506 => x"80083170",
+507 => x"6188050c",
+508 => x"5b585678",
+509 => x"ffb43880",
+510 => x"5574800c",
+511 => x"903d0d04",
+512 => x"7a813281",
+513 => x"06774056",
+514 => x"75802e81",
+515 => x"bd387690",
+516 => x"38740884",
+517 => x"16088817",
+518 => x"57585976",
+519 => x"802ef238",
+520 => x"881a0878",
+521 => x"83ffff06",
+522 => x"70892a81",
+523 => x"06565956",
+524 => x"73802e82",
+525 => x"f8387577",
+526 => x"278b3877",
+527 => x"872a8106",
+528 => x"5c7b82b5",
+529 => x"38767627",
+530 => x"83387656",
+531 => x"75537852",
+532 => x"79085185",
+533 => x"833f881a",
+534 => x"08763188",
+535 => x"1b0c7908",
+536 => x"167a0c76",
+537 => x"56751977",
+538 => x"77317f88",
+539 => x"05087831",
+540 => x"70618805",
+541 => x"0c415859",
+542 => x"7e802efe",
+543 => x"fa388c1a",
+544 => x"2258ff8a",
+545 => x"39787954",
+546 => x"7c537b52",
+547 => x"5684c93f",
+548 => x"881a0879",
+549 => x"31881b0c",
+550 => x"7908197a",
+551 => x"0c7c7631",
+552 => x"5d7c8e38",
+553 => x"79518ff2",
+554 => x"3f800881",
+555 => x"8f388008",
+556 => x"5f751c77",
+557 => x"77317f88",
+558 => x"05087831",
+559 => x"70618805",
+560 => x"0c5d585c",
+561 => x"7a802efe",
+562 => x"ae387681",
+563 => x"83387408",
+564 => x"84160888",
+565 => x"1757585c",
+566 => x"76802ef2",
+567 => x"3876538a",
+568 => x"527b5182",
+569 => x"d33f8008",
+570 => x"7c318105",
+571 => x"5d800884",
+572 => x"3881175d",
+573 => x"815f7c59",
+574 => x"767d2783",
+575 => x"38765994",
+576 => x"1a08881b",
+577 => x"08115758",
+578 => x"807a085c",
+579 => x"54901a08",
+580 => x"7b278338",
+581 => x"81547579",
+582 => x"25843873",
+583 => x"ba387779",
+584 => x"24fee238",
+585 => x"77537b52",
+586 => x"9c1a0851",
+587 => x"a41a0859",
+588 => x"782d8008",
+589 => x"56800880",
+590 => x"24fee238",
+591 => x"8c1a2280",
+592 => x"c0075e7d",
+593 => x"8c1b23ff",
+594 => x"5574800c",
+595 => x"903d0d04",
+596 => x"7effa338",
+597 => x"ff873975",
+598 => x"537b527a",
+599 => x"5182f93f",
+600 => x"7908167a",
+601 => x"0c79518e",
+602 => x"b13f8008",
+603 => x"cf387c76",
+604 => x"315d7cfe",
+605 => x"bc38feac",
+606 => x"39901a08",
+607 => x"7a087131",
+608 => x"78117056",
+609 => x"5a575280",
+610 => x"cfe40851",
+611 => x"84943f80",
+612 => x"08802eff",
+613 => x"a7388008",
+614 => x"901b0c80",
+615 => x"08167a0c",
+616 => x"77941b0c",
+617 => x"76881b0c",
+618 => x"7656fd99",
+619 => x"39790858",
+620 => x"901a0878",
+621 => x"27833881",
+622 => x"54757727",
+623 => x"843873b3",
+624 => x"38941a08",
+625 => x"54737726",
+626 => x"80d33873",
+627 => x"5378529c",
+628 => x"1a0851a4",
+629 => x"1a085877",
+630 => x"2d800856",
+631 => x"80088024",
+632 => x"fd83388c",
+633 => x"1a2280c0",
+634 => x"075e7d8c",
+635 => x"1b23ff55",
+636 => x"fed73975",
+637 => x"53785277",
+638 => x"5181dd3f",
+639 => x"7908167a",
+640 => x"0c79518d",
+641 => x"953f8008",
+642 => x"802efcd9",
+643 => x"388c1a22",
+644 => x"80c0075e",
+645 => x"7d8c1b23",
+646 => x"ff55fead",
+647 => x"39767754",
+648 => x"79537852",
+649 => x"5681b13f",
+650 => x"881a0877",
+651 => x"31881b0c",
+652 => x"7908177a",
+653 => x"0cfcae39",
+654 => x"fa3d0d7a",
+655 => x"79028805",
+656 => x"a7053355",
+657 => x"53548374",
+658 => x"2780df38",
+659 => x"71830651",
+660 => x"7080d738",
+661 => x"71715755",
+662 => x"83517582",
+663 => x"802913ff",
+664 => x"12525670",
+665 => x"8025f338",
+666 => x"837427bc",
+667 => x"38740876",
+668 => x"327009f7",
+669 => x"fbfdff12",
+670 => x"06f88482",
+671 => x"81800651",
+672 => x"5170802e",
+673 => x"98387451",
+674 => x"80527033",
+675 => x"5772772e",
+676 => x"b9388111",
+677 => x"81135351",
+678 => x"837227ee",
+679 => x"38fc1484",
+680 => x"16565473",
+681 => x"8326c638",
+682 => x"7452ff14",
+683 => x"5170ff2e",
+684 => x"97387133",
+685 => x"5472742e",
+686 => x"98388112",
+687 => x"ff125252",
+688 => x"70ff2e09",
+689 => x"8106eb38",
+690 => x"80517080",
+691 => x"0c883d0d",
+692 => x"0471800c",
+693 => x"883d0d04",
+694 => x"fa3d0d78",
+695 => x"7a7c7272",
+696 => x"72595755",
+697 => x"58565774",
+698 => x"7727b238",
+699 => x"75155176",
+700 => x"7127aa38",
+701 => x"707618ff",
+702 => x"18535353",
+703 => x"70ff2e96",
+704 => x"38ff12ff",
+705 => x"14545272",
+706 => x"337234ff",
+707 => x"115170ff",
+708 => x"2e098106",
+709 => x"ec387680",
+710 => x"0c883d0d",
+711 => x"048f7627",
+712 => x"80e63874",
+713 => x"77078306",
+714 => x"517080dc",
+715 => x"38767552",
+716 => x"53707084",
+717 => x"05520873",
+718 => x"70840555",
+719 => x"0c727170",
+720 => x"84055308",
+721 => x"71708405",
+722 => x"530c7170",
+723 => x"84055308",
+724 => x"71708405",
+725 => x"530c7170",
+726 => x"84055308",
+727 => x"71708405",
+728 => x"530cf015",
+729 => x"5553738f",
+730 => x"26c73883",
+731 => x"74279538",
+732 => x"70708405",
+733 => x"52087370",
+734 => x"8405550c",
+735 => x"fc145473",
+736 => x"8326ed38",
+737 => x"72715452",
+738 => x"ff145170",
+739 => x"ff2eff86",
+740 => x"38727081",
+741 => x"05543372",
+742 => x"70810554",
+743 => x"34ff1151",
+744 => x"ea39ef3d",
+745 => x"0d636567",
+746 => x"405d427b",
+747 => x"802e8582",
+748 => x"386151a9",
+749 => x"e73ff81c",
+750 => x"70841208",
+751 => x"70fc0670",
+752 => x"628b0570",
+753 => x"f8064159",
+754 => x"455c5f41",
+755 => x"57967427",
+756 => x"82c53880",
+757 => x"7b247e7c",
+758 => x"26075880",
+759 => x"5477742e",
+760 => x"09810682",
+761 => x"ab38787b",
+762 => x"2581fe38",
+763 => x"781780d7",
+764 => x"a00b8805",
+765 => x"085b5679",
+766 => x"762e84c5",
+767 => x"38841608",
+768 => x"70fe0617",
+769 => x"84110881",
+770 => x"06415555",
+771 => x"7e828d38",
+772 => x"74fc0658",
+773 => x"79762e84",
+774 => x"e3387818",
+775 => x"5f7e7b25",
+776 => x"81ff387c",
+777 => x"81065473",
+778 => x"82c13876",
+779 => x"77083184",
+780 => x"1108fc06",
+781 => x"56577580",
+782 => x"2e913879",
+783 => x"762e84f0",
+784 => x"38741819",
+785 => x"58777b25",
+786 => x"84913876",
+787 => x"802e829b",
+788 => x"38781556",
+789 => x"7a762482",
+790 => x"92388c17",
+791 => x"08881808",
+792 => x"718c120c",
+793 => x"88120c5e",
+794 => x"75598817",
+795 => x"61fc055b",
+796 => x"5679a426",
+797 => x"85ff387b",
+798 => x"76595593",
+799 => x"7a2780c9",
+800 => x"387b7084",
+801 => x"055d087c",
+802 => x"56760c74",
+803 => x"70840556",
+804 => x"088c180c",
+805 => x"9017589b",
+806 => x"7a27ae38",
+807 => x"74708405",
+808 => x"5608780c",
+809 => x"74708405",
+810 => x"56089418",
+811 => x"0c981758",
+812 => x"a37a2795",
+813 => x"38747084",
+814 => x"05560878",
+815 => x"0c747084",
+816 => x"0556089c",
+817 => x"180ca017",
+818 => x"58747084",
+819 => x"05560875",
+820 => x"5f787084",
+821 => x"055a0c77",
+822 => x"7e708405",
+823 => x"40087170",
+824 => x"8405530c",
+825 => x"7e08710c",
+826 => x"5d787b31",
+827 => x"56758f26",
+828 => x"80c93884",
+829 => x"17088106",
+830 => x"79078418",
+831 => x"0c781784",
+832 => x"11088107",
+833 => x"84120c5b",
+834 => x"6151a791",
+835 => x"3f881754",
+836 => x"73800c93",
+837 => x"3d0d0490",
+838 => x"5bfdb839",
+839 => x"7756fe83",
+840 => x"398c1608",
+841 => x"88170871",
+842 => x"8c120c88",
+843 => x"120c587e",
+844 => x"707c3157",
+845 => x"598f7627",
+846 => x"ffb9387a",
+847 => x"17841808",
+848 => x"81067c07",
+849 => x"84190c76",
+850 => x"81078412",
+851 => x"0c761184",
+852 => x"11088107",
+853 => x"84120c5b",
+854 => x"88055261",
+855 => x"518fda3f",
+856 => x"6151a6b9",
+857 => x"3f881754",
+858 => x"ffa6397d",
+859 => x"52615197",
+860 => x"d73f8008",
+861 => x"5a800880",
+862 => x"2e81ab38",
+863 => x"8008f805",
+864 => x"60840508",
+865 => x"fe066105",
+866 => x"58557477",
+867 => x"2e83f238",
+868 => x"fc195877",
+869 => x"a42681b0",
+870 => x"387b8008",
+871 => x"56579378",
+872 => x"2780dc38",
+873 => x"7b707084",
+874 => x"05520880",
+875 => x"08708405",
+876 => x"800c0c80",
+877 => x"08717084",
+878 => x"0553085d",
+879 => x"567b7670",
+880 => x"8405580c",
+881 => x"579b7827",
+882 => x"b6387670",
+883 => x"84055808",
+884 => x"75708405",
+885 => x"570c7670",
+886 => x"84055808",
+887 => x"75708405",
+888 => x"570ca378",
+889 => x"27993876",
+890 => x"70840558",
+891 => x"08757084",
+892 => x"05570c76",
+893 => x"70840558",
+894 => x"08757084",
+895 => x"05570c76",
+896 => x"70840558",
+897 => x"08775e75",
+898 => x"70840557",
+899 => x"0c747d70",
+900 => x"84055f08",
+901 => x"71708405",
+902 => x"530c7d08",
+903 => x"710c5f7b",
+904 => x"5261518e",
+905 => x"943f6151",
+906 => x"a4f33f79",
+907 => x"800c933d",
+908 => x"0d047d52",
+909 => x"61519690",
+910 => x"3f800880",
+911 => x"0c933d0d",
+912 => x"04841608",
+913 => x"55fbc939",
+914 => x"77537b52",
+915 => x"800851a2",
+916 => x"a53f7b52",
+917 => x"61518de1",
+918 => x"3fcc398c",
+919 => x"16088817",
+920 => x"08718c12",
+921 => x"0c88120c",
+922 => x"5d8c1708",
+923 => x"88180871",
+924 => x"8c120c88",
+925 => x"120c5977",
+926 => x"59fbef39",
+927 => x"7818901c",
+928 => x"40557e75",
+929 => x"24fb9c38",
+930 => x"7a177080",
+931 => x"d7a00b88",
+932 => x"050c757c",
+933 => x"31810784",
+934 => x"120c5684",
+935 => x"17088106",
+936 => x"7b078418",
+937 => x"0c6151a3",
+938 => x"f43f8817",
+939 => x"54fce139",
+940 => x"74181990",
+941 => x"1c5e5a7c",
+942 => x"7a24fb8f",
+943 => x"388c1708",
+944 => x"88180871",
+945 => x"8c120c88",
+946 => x"120c5e88",
+947 => x"1761fc05",
+948 => x"575975a4",
+949 => x"2681b638",
+950 => x"7b795955",
+951 => x"93762780",
+952 => x"c9387b70",
+953 => x"84055d08",
+954 => x"7c56790c",
+955 => x"74708405",
+956 => x"56088c18",
+957 => x"0c901758",
+958 => x"9b7627ae",
+959 => x"38747084",
+960 => x"05560878",
+961 => x"0c747084",
+962 => x"05560894",
+963 => x"180c9817",
+964 => x"58a37627",
+965 => x"95387470",
+966 => x"84055608",
+967 => x"780c7470",
+968 => x"84055608",
+969 => x"9c180ca0",
+970 => x"17587470",
+971 => x"84055608",
+972 => x"75417870",
+973 => x"84055a0c",
+974 => x"77607084",
+975 => x"05420871",
+976 => x"70840553",
+977 => x"0c600871",
+978 => x"0c5e7a17",
+979 => x"7080d7a0",
+980 => x"0b88050c",
+981 => x"7a7c3181",
+982 => x"0784120c",
+983 => x"58841708",
+984 => x"81067b07",
+985 => x"84180c61",
+986 => x"51a2b23f",
+987 => x"78547380",
+988 => x"0c933d0d",
+989 => x"0479537b",
+990 => x"5275519f",
+991 => x"f93ffae9",
+992 => x"39841508",
+993 => x"fc061960",
+994 => x"5859fadd",
+995 => x"3975537b",
+996 => x"5278519f",
+997 => x"e13f7a17",
+998 => x"7080d7a0",
+999 => x"0b88050c",
+1000 => x"7a7c3181",
+1001 => x"0784120c",
+1002 => x"58841708",
+1003 => x"81067b07",
+1004 => x"84180c61",
+1005 => x"51a1e63f",
+1006 => x"7854ffb2",
+1007 => x"39fa3d0d",
+1008 => x"7880cfe4",
+1009 => x"085455b8",
+1010 => x"1308802e",
+1011 => x"81af388c",
+1012 => x"15227083",
+1013 => x"ffff0670",
+1014 => x"832a8132",
+1015 => x"81065555",
+1016 => x"5672802e",
+1017 => x"80da3873",
+1018 => x"842a8132",
+1019 => x"810657ff",
+1020 => x"537680f2",
+1021 => x"3873822a",
+1022 => x"81065473",
+1023 => x"802eb938",
+1024 => x"b0150854",
+1025 => x"73802e9c",
+1026 => x"3880c015",
+1027 => x"5373732e",
+1028 => x"8f387352",
+1029 => x"80cfe408",
+1030 => x"518a9e3f",
+1031 => x"8c152256",
+1032 => x"76b0160c",
+1033 => x"75db0657",
+1034 => x"768c1623",
+1035 => x"800b8416",
+1036 => x"0c901508",
+1037 => x"750c7656",
+1038 => x"75880754",
+1039 => x"738c1623",
+1040 => x"90150880",
+1041 => x"2ebf388c",
+1042 => x"15227081",
+1043 => x"06555373",
+1044 => x"9c38720a",
+1045 => x"100a8106",
+1046 => x"56758538",
+1047 => x"94150854",
+1048 => x"7388160c",
+1049 => x"80537280",
+1050 => x"0c883d0d",
+1051 => x"04800b88",
+1052 => x"160c9415",
+1053 => x"08309816",
+1054 => x"0c8053ea",
+1055 => x"39725182",
+1056 => x"a63ffecb",
+1057 => x"3974518f",
+1058 => x"bc3f8c15",
+1059 => x"22708106",
+1060 => x"55537380",
+1061 => x"2effbb38",
+1062 => x"d439f83d",
+1063 => x"0d7a5776",
+1064 => x"802e8197",
+1065 => x"3880cfe4",
+1066 => x"0854b814",
+1067 => x"08802e80",
+1068 => x"eb388c17",
+1069 => x"2270902b",
+1070 => x"70902c70",
+1071 => x"832a8132",
+1072 => x"81065b5b",
+1073 => x"57557780",
+1074 => x"cb389017",
+1075 => x"08567580",
+1076 => x"2e80c138",
+1077 => x"76087631",
+1078 => x"76780c79",
+1079 => x"83065555",
+1080 => x"73853894",
+1081 => x"17085877",
+1082 => x"88180c80",
+1083 => x"7525a538",
+1084 => x"74537552",
+1085 => x"9c170851",
+1086 => x"a4170854",
+1087 => x"732d800b",
+1088 => x"80082580",
+1089 => x"c9388008",
+1090 => x"16758008",
+1091 => x"31565674",
+1092 => x"8024dd38",
+1093 => x"800b800c",
+1094 => x"8a3d0d04",
+1095 => x"73518187",
+1096 => x"3f8c1722",
+1097 => x"70902b70",
+1098 => x"902c7083",
+1099 => x"2a813281",
+1100 => x"065b5b57",
+1101 => x"5577dd38",
+1102 => x"ff9039a1",
+1103 => x"9a5280cf",
+1104 => x"e408518c",
+1105 => x"d03f8008",
+1106 => x"800c8a3d",
+1107 => x"0d048c17",
+1108 => x"2280c007",
+1109 => x"58778c18",
+1110 => x"23ff0b80",
+1111 => x"0c8a3d0d",
+1112 => x"04fa3d0d",
+1113 => x"797080dc",
+1114 => x"298c1154",
+1115 => x"7a535657",
+1116 => x"8fd63f80",
+1117 => x"08800855",
+1118 => x"56800880",
+1119 => x"2ea23880",
+1120 => x"088c0554",
+1121 => x"800b8008",
+1122 => x"0c768008",
+1123 => x"84050c73",
+1124 => x"80088805",
+1125 => x"0c745380",
+1126 => x"5273519c",
+1127 => x"f53f7554",
+1128 => x"73800c88",
+1129 => x"3d0d0470",
+1130 => x"707074a8",
+1131 => x"e60bbc12",
+1132 => x"0c53810b",
+1133 => x"b8140c80",
+1134 => x"0b84dc14",
+1135 => x"0c830b84",
+1136 => x"e0140c84",
+1137 => x"e81384e4",
+1138 => x"140c8413",
+1139 => x"08518070",
+1140 => x"720c7084",
+1141 => x"130c7088",
+1142 => x"130c5284",
+1143 => x"0b8c1223",
+1144 => x"718e1223",
+1145 => x"7190120c",
+1146 => x"7194120c",
+1147 => x"7198120c",
+1148 => x"709c120c",
+1149 => x"80c1d50b",
+1150 => x"a0120c80",
+1151 => x"c2a10ba4",
+1152 => x"120c80c3",
+1153 => x"9d0ba812",
+1154 => x"0c80c3ee",
+1155 => x"0bac120c",
+1156 => x"88130872",
+1157 => x"710c7284",
+1158 => x"120c7288",
+1159 => x"120c5189",
+1160 => x"0b8c1223",
+1161 => x"810b8e12",
+1162 => x"23719012",
+1163 => x"0c719412",
+1164 => x"0c719812",
+1165 => x"0c709c12",
+1166 => x"0c80c1d5",
+1167 => x"0ba0120c",
+1168 => x"80c2a10b",
+1169 => x"a4120c80",
+1170 => x"c39d0ba8",
+1171 => x"120c80c3",
+1172 => x"ee0bac12",
+1173 => x"0c8c1308",
+1174 => x"72710c72",
+1175 => x"84120c72",
+1176 => x"88120c51",
+1177 => x"8a0b8c12",
+1178 => x"23820b8e",
+1179 => x"12237190",
+1180 => x"120c7194",
+1181 => x"120c7198",
+1182 => x"120c709c",
+1183 => x"120c80c1",
+1184 => x"d50ba012",
+1185 => x"0c80c2a1",
+1186 => x"0ba4120c",
+1187 => x"80c39d0b",
+1188 => x"a8120c80",
+1189 => x"c3ee0bac",
+1190 => x"120c5050",
+1191 => x"5004f83d",
+1192 => x"0d7a80cf",
+1193 => x"e408b811",
+1194 => x"08575758",
+1195 => x"7481ec38",
+1196 => x"a8e60bbc",
+1197 => x"170c810b",
+1198 => x"b8170c74",
+1199 => x"84dc170c",
+1200 => x"830b84e0",
+1201 => x"170c84e8",
+1202 => x"1684e417",
+1203 => x"0c841608",
+1204 => x"75710c75",
+1205 => x"84120c75",
+1206 => x"88120c59",
+1207 => x"840b8c1a",
+1208 => x"23748e1a",
+1209 => x"2374901a",
+1210 => x"0c74941a",
+1211 => x"0c74981a",
+1212 => x"0c789c1a",
+1213 => x"0c80c1d5",
+1214 => x"0ba01a0c",
+1215 => x"80c2a10b",
+1216 => x"a41a0c80",
+1217 => x"c39d0ba8",
+1218 => x"1a0c80c3",
+1219 => x"ee0bac1a",
+1220 => x"0c881608",
+1221 => x"75710c75",
+1222 => x"84120c75",
+1223 => x"88120c57",
+1224 => x"890b8c18",
+1225 => x"23810b8e",
+1226 => x"18237490",
+1227 => x"180c7494",
+1228 => x"180c7498",
+1229 => x"180c769c",
+1230 => x"180c80c1",
+1231 => x"d50ba018",
+1232 => x"0c80c2a1",
+1233 => x"0ba4180c",
+1234 => x"80c39d0b",
+1235 => x"a8180c80",
+1236 => x"c3ee0bac",
+1237 => x"180c8c16",
+1238 => x"0875710c",
+1239 => x"7584120c",
+1240 => x"7588120c",
+1241 => x"548a0b8c",
+1242 => x"1523820b",
+1243 => x"8e152374",
+1244 => x"90150c74",
+1245 => x"94150c74",
+1246 => x"98150c73",
+1247 => x"9c150c80",
+1248 => x"c1d50ba0",
+1249 => x"150c80c2",
+1250 => x"a10ba415",
+1251 => x"0c80c39d",
+1252 => x"0ba8150c",
+1253 => x"80c3ee0b",
+1254 => x"ac150c84",
+1255 => x"dc168811",
+1256 => x"08841208",
+1257 => x"ff055757",
+1258 => x"57807524",
+1259 => x"9f388c16",
+1260 => x"2270902b",
+1261 => x"70902c51",
+1262 => x"55597380",
+1263 => x"2e80ed38",
+1264 => x"80dc16ff",
+1265 => x"16565674",
+1266 => x"8025e338",
+1267 => x"76085574",
+1268 => x"802e8f38",
+1269 => x"74881108",
+1270 => x"841208ff",
+1271 => x"05575757",
+1272 => x"c83982fc",
+1273 => x"5277518a",
+1274 => x"df3f8008",
+1275 => x"80085556",
+1276 => x"8008802e",
+1277 => x"a3388008",
+1278 => x"8c057580",
+1279 => x"080c5484",
+1280 => x"0b800884",
+1281 => x"050c7380",
+1282 => x"0888050c",
+1283 => x"82f05374",
+1284 => x"52735197",
+1285 => x"fd3f7554",
+1286 => x"7374780c",
+1287 => x"5573ffb4",
+1288 => x"388c780c",
+1289 => x"800b800c",
+1290 => x"8a3d0d04",
+1291 => x"810b8c17",
+1292 => x"2373760c",
+1293 => x"7388170c",
+1294 => x"7384170c",
+1295 => x"7390170c",
+1296 => x"7394170c",
+1297 => x"7398170c",
+1298 => x"ff0b8e17",
+1299 => x"2373b017",
+1300 => x"0c73b417",
+1301 => x"0c7380c4",
+1302 => x"170c7380",
+1303 => x"c8170c75",
+1304 => x"800c8a3d",
+1305 => x"0d047070",
+1306 => x"a19a5273",
+1307 => x"5186a63f",
+1308 => x"50500470",
+1309 => x"70a19a52",
+1310 => x"80cfe408",
+1311 => x"5186963f",
+1312 => x"505004fb",
+1313 => x"3d0d7770",
+1314 => x"52569890",
+1315 => x"3f80d7a0",
+1316 => x"0b880508",
+1317 => x"841108fc",
+1318 => x"06707b31",
+1319 => x"9fef05e0",
+1320 => x"8006e080",
+1321 => x"05525555",
+1322 => x"a0807524",
+1323 => x"94388052",
+1324 => x"755197ea",
+1325 => x"3f80d7a8",
+1326 => x"08145372",
+1327 => x"80082e8f",
+1328 => x"38755197",
+1329 => x"d83f8053",
+1330 => x"72800c87",
+1331 => x"3d0d0474",
+1332 => x"30527551",
+1333 => x"97c83f80",
+1334 => x"08ff2ea8",
+1335 => x"3880d7a0",
+1336 => x"0b880508",
+1337 => x"74763181",
+1338 => x"0784120c",
+1339 => x"5380d6e4",
+1340 => x"08753180",
+1341 => x"d6e40c75",
+1342 => x"5197a23f",
+1343 => x"810b800c",
+1344 => x"873d0d04",
+1345 => x"80527551",
+1346 => x"97943f80",
+1347 => x"d7a00b88",
+1348 => x"05088008",
+1349 => x"71315454",
+1350 => x"8f7325ff",
+1351 => x"a4388008",
+1352 => x"80d79408",
+1353 => x"3180d6e4",
+1354 => x"0c728107",
+1355 => x"84150c75",
+1356 => x"5196ea3f",
+1357 => x"8053ff90",
+1358 => x"39f73d0d",
+1359 => x"7b7d545a",
+1360 => x"72802e82",
+1361 => x"83387951",
+1362 => x"96d23ff8",
+1363 => x"13841108",
+1364 => x"70fe0670",
+1365 => x"13841108",
+1366 => x"fc065c57",
+1367 => x"58545780",
+1368 => x"d7a80874",
+1369 => x"2e82de38",
+1370 => x"7784150c",
+1371 => x"80738106",
+1372 => x"56597479",
+1373 => x"2e81d538",
+1374 => x"77148411",
+1375 => x"08810656",
+1376 => x"5374a038",
+1377 => x"77165678",
+1378 => x"81e63888",
+1379 => x"14085574",
+1380 => x"80d7a82e",
+1381 => x"82f9388c",
+1382 => x"1408708c",
+1383 => x"170c7588",
+1384 => x"120c5875",
+1385 => x"81078418",
+1386 => x"0c751776",
+1387 => x"710c5478",
+1388 => x"81913883",
+1389 => x"ff762781",
+1390 => x"c8387589",
+1391 => x"2a76832a",
+1392 => x"54547380",
+1393 => x"2ebf3875",
+1394 => x"862ab805",
+1395 => x"53847427",
+1396 => x"b43880db",
+1397 => x"14539474",
+1398 => x"27ab3875",
+1399 => x"8c2a80ee",
+1400 => x"055380d4",
+1401 => x"74279e38",
+1402 => x"758f2a80",
+1403 => x"f7055382",
+1404 => x"d4742791",
+1405 => x"3875922a",
+1406 => x"80fc0553",
+1407 => x"8ad47427",
+1408 => x"843880fe",
+1409 => x"53721010",
+1410 => x"1080d7a0",
+1411 => x"05881108",
+1412 => x"55557375",
+1413 => x"2e82bf38",
+1414 => x"841408fc",
+1415 => x"06597579",
+1416 => x"278d3888",
+1417 => x"14085473",
+1418 => x"752e0981",
+1419 => x"06ea388c",
+1420 => x"1408708c",
+1421 => x"190c7488",
+1422 => x"190c7788",
+1423 => x"120c5576",
+1424 => x"8c150c79",
+1425 => x"5194d63f",
+1426 => x"8b3d0d04",
+1427 => x"76087771",
+1428 => x"31587605",
+1429 => x"88180856",
+1430 => x"567480d7",
+1431 => x"a82e80e0",
+1432 => x"388c1708",
+1433 => x"708c170c",
+1434 => x"7588120c",
+1435 => x"53fe8939",
+1436 => x"8814088c",
+1437 => x"1508708c",
+1438 => x"130c5988",
+1439 => x"190cfea3",
+1440 => x"3975832a",
+1441 => x"70545480",
+1442 => x"74248198",
+1443 => x"3872822c",
+1444 => x"81712b80",
+1445 => x"d7a40807",
+1446 => x"80d7a00b",
+1447 => x"84050c74",
+1448 => x"10101080",
+1449 => x"d7a00588",
+1450 => x"1108718c",
+1451 => x"1b0c7088",
+1452 => x"1b0c7988",
+1453 => x"130c565a",
+1454 => x"55768c15",
+1455 => x"0cff8439",
+1456 => x"8159fdb4",
+1457 => x"39771673",
+1458 => x"81065455",
+1459 => x"72983876",
+1460 => x"08777131",
+1461 => x"5875058c",
+1462 => x"18088819",
+1463 => x"08718c12",
+1464 => x"0c88120c",
+1465 => x"55557481",
+1466 => x"0784180c",
+1467 => x"7680d7a0",
+1468 => x"0b88050c",
+1469 => x"80d79c08",
+1470 => x"7526fec7",
+1471 => x"3880d798",
+1472 => x"08527951",
+1473 => x"fafd3f79",
+1474 => x"5193923f",
+1475 => x"feba3981",
+1476 => x"778c170c",
+1477 => x"7788170c",
+1478 => x"758c190c",
+1479 => x"7588190c",
+1480 => x"59fd8039",
+1481 => x"83147082",
+1482 => x"2c81712b",
+1483 => x"80d7a408",
+1484 => x"0780d7a0",
+1485 => x"0b84050c",
+1486 => x"75101010",
+1487 => x"80d7a005",
+1488 => x"88110871",
+1489 => x"8c1c0c70",
+1490 => x"881c0c7a",
+1491 => x"88130c57",
+1492 => x"5b5653fe",
+1493 => x"e4398073",
+1494 => x"24a33872",
+1495 => x"822c8171",
+1496 => x"2b80d7a4",
+1497 => x"080780d7",
+1498 => x"a00b8405",
+1499 => x"0c58748c",
+1500 => x"180c7388",
+1501 => x"180c7688",
+1502 => x"160cfdc3",
+1503 => x"39831370",
+1504 => x"822c8171",
+1505 => x"2b80d7a4",
+1506 => x"080780d7",
+1507 => x"a00b8405",
+1508 => x"0c5953da",
+1509 => x"39f93d0d",
+1510 => x"797b5853",
+1511 => x"800b80cf",
+1512 => x"e4085356",
+1513 => x"72722ebc",
+1514 => x"3884dc13",
+1515 => x"5574762e",
+1516 => x"b3388815",
+1517 => x"08841608",
+1518 => x"ff055454",
+1519 => x"80732499",
+1520 => x"388c1422",
+1521 => x"70902b53",
+1522 => x"587180d4",
+1523 => x"3880dc14",
+1524 => x"ff145454",
+1525 => x"728025e9",
+1526 => x"38740855",
+1527 => x"74d43880",
+1528 => x"cfe40852",
+1529 => x"84dc1255",
+1530 => x"74802ead",
+1531 => x"38881508",
+1532 => x"841608ff",
+1533 => x"05545480",
+1534 => x"73249838",
+1535 => x"8c142270",
+1536 => x"902b5358",
+1537 => x"71ad3880",
+1538 => x"dc14ff14",
+1539 => x"54547280",
+1540 => x"25ea3874",
+1541 => x"085574d5",
+1542 => x"3875800c",
+1543 => x"893d0d04",
+1544 => x"7351762d",
+1545 => x"75800807",
+1546 => x"80dc15ff",
+1547 => x"15555556",
+1548 => x"ffa23973",
+1549 => x"51762d75",
+1550 => x"80080780",
+1551 => x"dc15ff15",
+1552 => x"555556ca",
+1553 => x"39ea3d0d",
+1554 => x"688c1122",
+1555 => x"700a100a",
+1556 => x"81065758",
+1557 => x"567480e4",
+1558 => x"388e1622",
+1559 => x"70902b70",
+1560 => x"902c5155",
+1561 => x"58807424",
+1562 => x"b138983d",
+1563 => x"c4055373",
+1564 => x"5280cfe4",
+1565 => x"08519481",
+1566 => x"3f800b80",
+1567 => x"08249738",
+1568 => x"7983e080",
+1569 => x"06547380",
+1570 => x"c0802e81",
+1571 => x"8f387382",
+1572 => x"80802e81",
+1573 => x"91388c16",
+1574 => x"22577690",
+1575 => x"80075473",
+1576 => x"8c172388",
+1577 => x"805280cf",
+1578 => x"e4085181",
+1579 => x"9b3f8008",
+1580 => x"9d388c16",
+1581 => x"22820755",
+1582 => x"748c1723",
+1583 => x"80c31670",
+1584 => x"770c9017",
+1585 => x"0c810b94",
+1586 => x"170c983d",
+1587 => x"0d0480cf",
+1588 => x"e408a8e6",
+1589 => x"0bbc120c",
+1590 => x"588c1622",
+1591 => x"81800754",
+1592 => x"738c1723",
+1593 => x"8008760c",
+1594 => x"80089017",
+1595 => x"0c88800b",
+1596 => x"94170c74",
+1597 => x"802ed338",
+1598 => x"8e162270",
+1599 => x"902b7090",
+1600 => x"2c535654",
+1601 => x"9afe3f80",
+1602 => x"08802eff",
+1603 => x"bd388c16",
+1604 => x"22810757",
+1605 => x"768c1723",
+1606 => x"983d0d04",
+1607 => x"810b8c17",
+1608 => x"225855fe",
+1609 => x"f539a816",
+1610 => x"0880c39d",
+1611 => x"2e098106",
+1612 => x"fee4388c",
+1613 => x"16228880",
+1614 => x"0754738c",
+1615 => x"17238880",
+1616 => x"0b80cc17",
+1617 => x"0cfedc39",
+1618 => x"f43d0d7e",
+1619 => x"608b1170",
+1620 => x"f8065b55",
+1621 => x"555d7296",
+1622 => x"26833890",
+1623 => x"58807824",
+1624 => x"74792607",
+1625 => x"55805474",
+1626 => x"742e0981",
+1627 => x"0680ca38",
+1628 => x"7c518ea8",
+1629 => x"3f7783f7",
+1630 => x"2680c538",
+1631 => x"77832a70",
+1632 => x"10101080",
+1633 => x"d7a0058c",
+1634 => x"11085858",
+1635 => x"5475772e",
+1636 => x"81f03884",
+1637 => x"1608fc06",
+1638 => x"8c170888",
+1639 => x"1808718c",
+1640 => x"120c8812",
+1641 => x"0c5b7605",
+1642 => x"84110881",
+1643 => x"0784120c",
+1644 => x"537c518d",
+1645 => x"e83f8816",
+1646 => x"5473800c",
+1647 => x"8e3d0d04",
+1648 => x"77892a78",
+1649 => x"832a5854",
+1650 => x"73802ebf",
+1651 => x"3877862a",
+1652 => x"b8055784",
+1653 => x"7427b438",
+1654 => x"80db1457",
+1655 => x"947427ab",
+1656 => x"38778c2a",
+1657 => x"80ee0557",
+1658 => x"80d47427",
+1659 => x"9e38778f",
+1660 => x"2a80f705",
+1661 => x"5782d474",
+1662 => x"27913877",
+1663 => x"922a80fc",
+1664 => x"05578ad4",
+1665 => x"74278438",
+1666 => x"80fe5776",
+1667 => x"10101080",
+1668 => x"d7a0058c",
+1669 => x"11085653",
+1670 => x"74732ea3",
+1671 => x"38841508",
+1672 => x"fc067079",
+1673 => x"31555673",
+1674 => x"8f2488e4",
+1675 => x"38738025",
+1676 => x"88e6388c",
+1677 => x"15085574",
+1678 => x"732e0981",
+1679 => x"06df3881",
+1680 => x"175980d7",
+1681 => x"b0085675",
+1682 => x"80d7a82e",
+1683 => x"82cc3884",
+1684 => x"1608fc06",
+1685 => x"70793155",
+1686 => x"55738f24",
+1687 => x"bb3880d7",
+1688 => x"a80b80d7",
+1689 => x"b40c80d7",
+1690 => x"a80b80d7",
+1691 => x"b00c8074",
+1692 => x"2480db38",
+1693 => x"74168411",
+1694 => x"08810784",
+1695 => x"120c53fe",
+1696 => x"b0398816",
+1697 => x"8c110857",
+1698 => x"5975792e",
+1699 => x"098106fe",
+1700 => x"82388214",
+1701 => x"59ffab39",
+1702 => x"77167881",
+1703 => x"0784180c",
+1704 => x"7080d7b4",
+1705 => x"0c7080d7",
+1706 => x"b00c80d7",
+1707 => x"a80b8c12",
+1708 => x"0c8c1108",
+1709 => x"88120c74",
+1710 => x"81078412",
+1711 => x"0c740574",
+1712 => x"710c5b7c",
+1713 => x"518bd63f",
+1714 => x"881654fd",
+1715 => x"ec3983ff",
+1716 => x"75278391",
+1717 => x"3874892a",
+1718 => x"75832a54",
+1719 => x"5473802e",
+1720 => x"bf387486",
+1721 => x"2ab80553",
+1722 => x"847427b4",
+1723 => x"3880db14",
+1724 => x"53947427",
+1725 => x"ab38748c",
+1726 => x"2a80ee05",
+1727 => x"5380d474",
+1728 => x"279e3874",
+1729 => x"8f2a80f7",
+1730 => x"055382d4",
+1731 => x"74279138",
+1732 => x"74922a80",
+1733 => x"fc05538a",
+1734 => x"d4742784",
+1735 => x"3880fe53",
+1736 => x"72101010",
+1737 => x"80d7a005",
+1738 => x"88110855",
+1739 => x"5773772e",
+1740 => x"868b3884",
+1741 => x"1408fc06",
+1742 => x"5b747b27",
+1743 => x"8d388814",
+1744 => x"08547377",
+1745 => x"2e098106",
+1746 => x"ea388c14",
+1747 => x"0880d7a0",
+1748 => x"0b840508",
+1749 => x"718c190c",
+1750 => x"7588190c",
+1751 => x"7788130c",
+1752 => x"5c57758c",
+1753 => x"150c7853",
+1754 => x"80792483",
+1755 => x"98387282",
+1756 => x"2c81712b",
+1757 => x"5656747b",
+1758 => x"2680ca38",
+1759 => x"7a750657",
+1760 => x"7682a338",
+1761 => x"78fc0684",
+1762 => x"05597410",
+1763 => x"707c0655",
+1764 => x"55738292",
+1765 => x"38841959",
+1766 => x"f13980d7",
+1767 => x"a00b8405",
+1768 => x"0879545b",
+1769 => x"788025c6",
+1770 => x"3882da39",
+1771 => x"74097b06",
+1772 => x"7080d7a0",
+1773 => x"0b84050c",
+1774 => x"5b741055",
+1775 => x"747b2685",
+1776 => x"387485bc",
+1777 => x"3880d7a0",
+1778 => x"0b880508",
+1779 => x"70841208",
+1780 => x"fc06707b",
+1781 => x"317b7226",
+1782 => x"8f722507",
+1783 => x"5d575c5c",
+1784 => x"5578802e",
+1785 => x"80d93879",
+1786 => x"1580d798",
+1787 => x"08199011",
+1788 => x"59545680",
+1789 => x"d79408ff",
+1790 => x"2e8838a0",
+1791 => x"8f13e080",
+1792 => x"06577652",
+1793 => x"7c518996",
+1794 => x"3f800854",
+1795 => x"8008ff2e",
+1796 => x"90388008",
+1797 => x"762782a7",
+1798 => x"387480d7",
+1799 => x"a02e829f",
+1800 => x"3880d7a0",
+1801 => x"0b880508",
+1802 => x"55841508",
+1803 => x"fc067079",
+1804 => x"31797226",
+1805 => x"8f722507",
+1806 => x"5d555a7a",
+1807 => x"83f23877",
+1808 => x"81078416",
+1809 => x"0c771570",
+1810 => x"80d7a00b",
+1811 => x"88050c74",
+1812 => x"81078412",
+1813 => x"0c567c51",
+1814 => x"88c33f88",
+1815 => x"15547380",
+1816 => x"0c8e3d0d",
+1817 => x"0474832a",
+1818 => x"70545480",
+1819 => x"7424819b",
+1820 => x"3872822c",
+1821 => x"81712b80",
+1822 => x"d7a40807",
+1823 => x"7080d7a0",
+1824 => x"0b84050c",
+1825 => x"75101010",
+1826 => x"80d7a005",
+1827 => x"88110871",
+1828 => x"8c1b0c70",
+1829 => x"881b0c79",
+1830 => x"88130c57",
+1831 => x"555c5575",
+1832 => x"8c150cfd",
+1833 => x"c1397879",
+1834 => x"10101080",
+1835 => x"d7a00570",
+1836 => x"565b5c8c",
+1837 => x"14085675",
+1838 => x"742ea338",
+1839 => x"841608fc",
+1840 => x"06707931",
+1841 => x"5853768f",
+1842 => x"2483f138",
+1843 => x"76802584",
+1844 => x"af388c16",
+1845 => x"08567574",
+1846 => x"2e098106",
+1847 => x"df388814",
+1848 => x"811a7083",
+1849 => x"06555a54",
+1850 => x"72c9387b",
+1851 => x"83065675",
+1852 => x"802efdb8",
+1853 => x"38ff1cf8",
+1854 => x"1b5b5c88",
+1855 => x"1a087a2e",
+1856 => x"ea38fdb5",
+1857 => x"39831953",
+1858 => x"fce43983",
+1859 => x"1470822c",
+1860 => x"81712b80",
+1861 => x"d7a40807",
+1862 => x"7080d7a0",
+1863 => x"0b84050c",
+1864 => x"76101010",
+1865 => x"80d7a005",
+1866 => x"88110871",
+1867 => x"8c1c0c70",
+1868 => x"881c0c7a",
+1869 => x"88130c58",
+1870 => x"535d5653",
+1871 => x"fee13980",
+1872 => x"d6e40817",
+1873 => x"59800876",
+1874 => x"2e818b38",
+1875 => x"80d79408",
+1876 => x"ff2e848e",
+1877 => x"38737631",
+1878 => x"1980d6e4",
+1879 => x"0c738706",
+1880 => x"70565372",
+1881 => x"802e8838",
+1882 => x"88733170",
+1883 => x"15555576",
+1884 => x"149fff06",
+1885 => x"a0807131",
+1886 => x"1670547e",
+1887 => x"53515386",
+1888 => x"9d3f8008",
+1889 => x"568008ff",
+1890 => x"2e819e38",
+1891 => x"80d6e408",
+1892 => x"137080d6",
+1893 => x"e40c7475",
+1894 => x"80d7a00b",
+1895 => x"88050c77",
+1896 => x"76311581",
+1897 => x"07555659",
+1898 => x"7a80d7a0",
+1899 => x"2e83c038",
+1900 => x"798f2682",
+1901 => x"ef38810b",
+1902 => x"84150c84",
+1903 => x"1508fc06",
+1904 => x"70793179",
+1905 => x"72268f72",
+1906 => x"25075d55",
+1907 => x"5a7a802e",
+1908 => x"fced3880",
+1909 => x"db398008",
+1910 => x"9fff0655",
+1911 => x"74feed38",
+1912 => x"7880d6e4",
+1913 => x"0c80d7a0",
+1914 => x"0b880508",
+1915 => x"7a188107",
+1916 => x"84120c55",
+1917 => x"80d79008",
+1918 => x"79278638",
+1919 => x"7880d790",
+1920 => x"0c80d78c",
+1921 => x"087927fc",
+1922 => x"a0387880",
+1923 => x"d78c0c84",
+1924 => x"1508fc06",
+1925 => x"70793179",
+1926 => x"72268f72",
+1927 => x"25075d55",
+1928 => x"5a7a802e",
+1929 => x"fc993888",
+1930 => x"39807457",
+1931 => x"53fedd39",
+1932 => x"7c5184e9",
+1933 => x"3f800b80",
+1934 => x"0c8e3d0d",
+1935 => x"04807324",
+1936 => x"a5387282",
+1937 => x"2c81712b",
+1938 => x"80d7a408",
+1939 => x"077080d7",
+1940 => x"a00b8405",
+1941 => x"0c5c5a76",
+1942 => x"8c170c73",
+1943 => x"88170c75",
+1944 => x"88180cf9",
+1945 => x"fd398313",
+1946 => x"70822c81",
+1947 => x"712b80d7",
+1948 => x"a4080770",
+1949 => x"80d7a00b",
+1950 => x"84050c5d",
+1951 => x"5b53d839",
+1952 => x"7a75065c",
+1953 => x"7bfc9f38",
+1954 => x"84197510",
+1955 => x"5659f139",
+1956 => x"ff178105",
+1957 => x"59f7ab39",
+1958 => x"8c150888",
+1959 => x"1608718c",
+1960 => x"120c8812",
+1961 => x"0c597515",
+1962 => x"84110881",
+1963 => x"0784120c",
+1964 => x"587c5183",
+1965 => x"e83f8815",
+1966 => x"54fba339",
+1967 => x"77167881",
+1968 => x"0784180c",
+1969 => x"8c170888",
+1970 => x"1808718c",
+1971 => x"120c8812",
+1972 => x"0c5c7080",
+1973 => x"d7b40c70",
+1974 => x"80d7b00c",
+1975 => x"80d7a80b",
+1976 => x"8c120c8c",
+1977 => x"11088812",
+1978 => x"0c778107",
+1979 => x"84120c77",
+1980 => x"0577710c",
+1981 => x"557c5183",
+1982 => x"a43f8816",
+1983 => x"54f5ba39",
+1984 => x"72168411",
+1985 => x"08810784",
+1986 => x"120c588c",
+1987 => x"16088817",
+1988 => x"08718c12",
+1989 => x"0c88120c",
+1990 => x"577c5183",
+1991 => x"803f8816",
+1992 => x"54f59639",
+1993 => x"7284150c",
+1994 => x"f41af806",
+1995 => x"70841d08",
+1996 => x"81060784",
+1997 => x"1d0c701c",
+1998 => x"5556850b",
+1999 => x"84150c85",
+2000 => x"0b88150c",
+2001 => x"8f7627fd",
+2002 => x"ab38881b",
+2003 => x"527c51eb",
+2004 => x"e83f80d7",
+2005 => x"a00b8805",
+2006 => x"0880d6e4",
+2007 => x"085a55fd",
+2008 => x"93397880",
+2009 => x"d6e40c73",
+2010 => x"80d7940c",
+2011 => x"fbef3972",
+2012 => x"84150cfc",
+2013 => x"ff39fb3d",
+2014 => x"0d77707a",
+2015 => x"7c585553",
+2016 => x"568f7527",
+2017 => x"80e63872",
+2018 => x"76078306",
+2019 => x"517080dc",
+2020 => x"38757352",
+2021 => x"54707084",
+2022 => x"05520874",
+2023 => x"70840556",
+2024 => x"0c737170",
+2025 => x"84055308",
+2026 => x"71708405",
+2027 => x"530c7170",
+2028 => x"84055308",
+2029 => x"71708405",
+2030 => x"530c7170",
+2031 => x"84055308",
+2032 => x"71708405",
+2033 => x"530cf016",
+2034 => x"5654748f",
+2035 => x"26c73883",
+2036 => x"75279538",
+2037 => x"70708405",
+2038 => x"52087470",
+2039 => x"8405560c",
+2040 => x"fc155574",
+2041 => x"8326ed38",
+2042 => x"73715452",
+2043 => x"ff155170",
+2044 => x"ff2e9838",
+2045 => x"72708105",
+2046 => x"54337270",
+2047 => x"81055434",
+2048 => x"ff115170",
+2049 => x"ff2e0981",
+2050 => x"06ea3875",
+2051 => x"800c873d",
+2052 => x"0d04fb3d",
+2053 => x"0d777a71",
+2054 => x"028c05a3",
+2055 => x"05335854",
+2056 => x"54568373",
+2057 => x"2780d438",
+2058 => x"75830651",
+2059 => x"7080cc38",
+2060 => x"74882b75",
+2061 => x"07707190",
+2062 => x"2b075551",
+2063 => x"8f7327a7",
+2064 => x"38737270",
+2065 => x"8405540c",
+2066 => x"71747170",
+2067 => x"8405530c",
+2068 => x"74717084",
+2069 => x"05530c74",
+2070 => x"71708405",
+2071 => x"530cf014",
+2072 => x"5452728f",
+2073 => x"26db3883",
+2074 => x"73279038",
+2075 => x"73727084",
+2076 => x"05540cfc",
+2077 => x"13537283",
+2078 => x"26f238ff",
+2079 => x"135170ff",
+2080 => x"2e933874",
+2081 => x"72708105",
+2082 => x"5434ff11",
+2083 => x"5170ff2e",
+2084 => x"098106ef",
+2085 => x"3875800c",
+2086 => x"873d0d04",
+2087 => x"04047070",
+2088 => x"7070800b",
+2089 => x"80dfe00c",
+2090 => x"765184f3",
+2091 => x"3f800853",
+2092 => x"8008ff2e",
+2093 => x"89387280",
+2094 => x"0c505050",
+2095 => x"500480df",
+2096 => x"e0085473",
+2097 => x"802eef38",
+2098 => x"7574710c",
+2099 => x"5272800c",
+2100 => x"50505050",
+2101 => x"04f93d0d",
+2102 => x"797c557b",
+2103 => x"548e1122",
+2104 => x"70902b70",
+2105 => x"902c5557",
+2106 => x"80cfe408",
+2107 => x"53585683",
+2108 => x"f63f8008",
+2109 => x"57800b80",
+2110 => x"08249338",
+2111 => x"80d01608",
+2112 => x"80080580",
+2113 => x"d0170c76",
+2114 => x"800c893d",
+2115 => x"0d048c16",
+2116 => x"2283dfff",
+2117 => x"0655748c",
+2118 => x"17237680",
+2119 => x"0c893d0d",
+2120 => x"04fa3d0d",
+2121 => x"788c1122",
+2122 => x"70882a70",
+2123 => x"81065157",
+2124 => x"585674a9",
+2125 => x"388c1622",
+2126 => x"83dfff06",
+2127 => x"55748c17",
+2128 => x"237a5479",
+2129 => x"538e1622",
+2130 => x"70902b70",
+2131 => x"902c5456",
+2132 => x"80cfe408",
+2133 => x"525681b2",
+2134 => x"3f883d0d",
+2135 => x"04825480",
+2136 => x"538e1622",
+2137 => x"70902b70",
+2138 => x"902c5456",
+2139 => x"80cfe408",
+2140 => x"525782bb",
+2141 => x"3f8c1622",
+2142 => x"83dfff06",
+2143 => x"55748c17",
+2144 => x"237a5479",
+2145 => x"538e1622",
+2146 => x"70902b70",
+2147 => x"902c5456",
+2148 => x"80cfe408",
+2149 => x"525680f2",
+2150 => x"3f883d0d",
+2151 => x"04f93d0d",
+2152 => x"797c557b",
+2153 => x"548e1122",
+2154 => x"70902b70",
+2155 => x"902c5557",
+2156 => x"80cfe408",
+2157 => x"53585681",
+2158 => x"f63f8008",
+2159 => x"578008ff",
+2160 => x"2e99388c",
+2161 => x"1622a080",
+2162 => x"0755748c",
+2163 => x"17238008",
+2164 => x"80d0170c",
+2165 => x"76800c89",
+2166 => x"3d0d048c",
+2167 => x"162283df",
+2168 => x"ff065574",
+2169 => x"8c172376",
+2170 => x"800c893d",
+2171 => x"0d047070",
+2172 => x"70748e11",
+2173 => x"2270902b",
+2174 => x"70902c55",
+2175 => x"51515380",
+2176 => x"cfe40851",
+2177 => x"bd3f5050",
+2178 => x"5004fb3d",
+2179 => x"0d800b80",
+2180 => x"dfe00c7a",
+2181 => x"53795278",
+2182 => x"5182ff3f",
+2183 => x"80085580",
+2184 => x"08ff2e88",
+2185 => x"3874800c",
+2186 => x"873d0d04",
+2187 => x"80dfe008",
+2188 => x"5675802e",
+2189 => x"f0387776",
+2190 => x"710c5474",
+2191 => x"800c873d",
+2192 => x"0d047070",
+2193 => x"7070800b",
+2194 => x"80dfe00c",
+2195 => x"765184cc",
+2196 => x"3f800853",
+2197 => x"8008ff2e",
+2198 => x"89387280",
+2199 => x"0c505050",
+2200 => x"500480df",
+2201 => x"e0085473",
+2202 => x"802eef38",
+2203 => x"7574710c",
+2204 => x"5272800c",
+2205 => x"50505050",
+2206 => x"04fc3d0d",
+2207 => x"800b80df",
+2208 => x"e00c7852",
+2209 => x"775187b3",
+2210 => x"3f800854",
+2211 => x"8008ff2e",
+2212 => x"88387380",
+2213 => x"0c863d0d",
+2214 => x"0480dfe0",
+2215 => x"08557480",
+2216 => x"2ef03876",
+2217 => x"75710c53",
+2218 => x"73800c86",
+2219 => x"3d0d04fb",
+2220 => x"3d0d800b",
+2221 => x"80dfe00c",
+2222 => x"7a537952",
+2223 => x"7851848e",
+2224 => x"3f800855",
+2225 => x"8008ff2e",
+2226 => x"88387480",
+2227 => x"0c873d0d",
+2228 => x"0480dfe0",
+2229 => x"08567580",
+2230 => x"2ef03877",
+2231 => x"76710c54",
+2232 => x"74800c87",
+2233 => x"3d0d04fb",
+2234 => x"3d0d800b",
+2235 => x"80dfe00c",
+2236 => x"7a537952",
+2237 => x"78518296",
+2238 => x"3f800855",
+2239 => x"8008ff2e",
+2240 => x"88387480",
+2241 => x"0c873d0d",
+2242 => x"0480dfe0",
+2243 => x"08567580",
+2244 => x"2ef03877",
+2245 => x"76710c54",
+2246 => x"74800c87",
+2247 => x"3d0d0470",
+2248 => x"707080df",
+2249 => x"d0088938",
+2250 => x"80dfe40b",
+2251 => x"80dfd00c",
+2252 => x"80dfd008",
+2253 => x"75115252",
+2254 => x"ff537087",
+2255 => x"fb808026",
+2256 => x"88387080",
+2257 => x"dfd00c71",
+2258 => x"5372800c",
+2259 => x"50505004",
+2260 => x"fd3d0d80",
+2261 => x"0b80cfd8",
+2262 => x"08545472",
+2263 => x"812e9b38",
+2264 => x"7380dfd4",
+2265 => x"0cc2bf3f",
+2266 => x"c1963f80",
+2267 => x"dfa85281",
+2268 => x"51c3fd3f",
+2269 => x"80085186",
+2270 => x"c23f7280",
+2271 => x"dfd40cc2",
+2272 => x"a53fc0fc",
+2273 => x"3f80dfa8",
+2274 => x"528151c3",
+2275 => x"e33f8008",
+2276 => x"5186a83f",
+2277 => x"00ff3900",
+2278 => x"ff39f53d",
+2279 => x"0d7e6080",
+2280 => x"dfd40870",
+2281 => x"5b585b5b",
+2282 => x"7580c238",
+2283 => x"777a25a1",
+2284 => x"38771b70",
+2285 => x"337081ff",
+2286 => x"06585859",
+2287 => x"758a2e98",
+2288 => x"387681ff",
+2289 => x"0651c1bd",
+2290 => x"3f811858",
+2291 => x"797824e1",
+2292 => x"3879800c",
+2293 => x"8d3d0d04",
+2294 => x"8d51c1a9",
+2295 => x"3f783370",
+2296 => x"81ff0652",
+2297 => x"57c19e3f",
+2298 => x"811858e0",
+2299 => x"3979557a",
+2300 => x"547d5385",
+2301 => x"528d3dfc",
+2302 => x"0551c0c6",
+2303 => x"3f800856",
+2304 => x"85b23f7b",
+2305 => x"80080c75",
+2306 => x"800c8d3d",
+2307 => x"0d04f63d",
+2308 => x"0d7d7f80",
+2309 => x"dfd40870",
+2310 => x"5b585a5a",
+2311 => x"7580c138",
+2312 => x"777925b3",
+2313 => x"38c0b93f",
+2314 => x"800881ff",
+2315 => x"06708d32",
+2316 => x"7030709f",
+2317 => x"2a515157",
+2318 => x"57768a2e",
+2319 => x"80c43875",
+2320 => x"802ebf38",
+2321 => x"771a5676",
+2322 => x"76347651",
+2323 => x"c0b73f81",
+2324 => x"18587878",
+2325 => x"24cf3877",
+2326 => x"5675800c",
+2327 => x"8c3d0d04",
+2328 => x"78557954",
+2329 => x"7c538452",
+2330 => x"8c3dfc05",
+2331 => x"51ffbfd2",
+2332 => x"3f800856",
+2333 => x"84be3f7a",
+2334 => x"80080c75",
+2335 => x"800c8c3d",
+2336 => x"0d04771a",
+2337 => x"598a7934",
+2338 => x"8118588d",
+2339 => x"51ffbff5",
+2340 => x"3f8a51ff",
+2341 => x"bfef3f77",
+2342 => x"56ffbe39",
+2343 => x"fb3d0d80",
+2344 => x"dfd40870",
+2345 => x"56547388",
+2346 => x"3874800c",
+2347 => x"873d0d04",
+2348 => x"77538352",
+2349 => x"873dfc05",
+2350 => x"51ffbf86",
+2351 => x"3f800854",
+2352 => x"83f23f75",
+2353 => x"80080c73",
+2354 => x"800c873d",
+2355 => x"0d04fa3d",
+2356 => x"0d80dfd4",
+2357 => x"08802ea3",
+2358 => x"387a5579",
+2359 => x"54785386",
+2360 => x"52883dfc",
+2361 => x"0551ffbe",
+2362 => x"d93f8008",
+2363 => x"5683c53f",
+2364 => x"7680080c",
+2365 => x"75800c88",
+2366 => x"3d0d0483",
+2367 => x"b73f9d0b",
+2368 => x"80080cff",
+2369 => x"0b800c88",
+2370 => x"3d0d04f7",
+2371 => x"3d0d7b7d",
+2372 => x"5b59bc53",
+2373 => x"80527951",
+2374 => x"f5f83f80",
+2375 => x"70565798",
+2376 => x"56741970",
+2377 => x"3370782b",
+2378 => x"79078118",
+2379 => x"f81a5a58",
+2380 => x"59555884",
+2381 => x"7524ea38",
+2382 => x"767a2384",
+2383 => x"19588070",
+2384 => x"56579856",
+2385 => x"74187033",
+2386 => x"70782b79",
+2387 => x"078118f8",
+2388 => x"1a5a5859",
+2389 => x"51548475",
+2390 => x"24ea3876",
+2391 => x"821b2388",
+2392 => x"19588070",
+2393 => x"56579856",
+2394 => x"74187033",
+2395 => x"70782b79",
+2396 => x"078118f8",
+2397 => x"1a5a5859",
+2398 => x"51548475",
+2399 => x"24ea3876",
+2400 => x"841b0c8c",
+2401 => x"19588070",
+2402 => x"56579856",
+2403 => x"74187033",
+2404 => x"70782b79",
+2405 => x"078118f8",
+2406 => x"1a5a5859",
+2407 => x"51548475",
+2408 => x"24ea3876",
+2409 => x"881b2390",
+2410 => x"19588070",
+2411 => x"56579856",
+2412 => x"74187033",
+2413 => x"70782b79",
+2414 => x"078118f8",
+2415 => x"1a5a5859",
+2416 => x"51548475",
+2417 => x"24ea3876",
+2418 => x"8a1b2394",
+2419 => x"19588070",
+2420 => x"56579856",
+2421 => x"74187033",
+2422 => x"70782b79",
+2423 => x"078118f8",
+2424 => x"1a5a5859",
+2425 => x"51548475",
+2426 => x"24ea3876",
+2427 => x"8c1b2398",
+2428 => x"19588070",
+2429 => x"56579856",
+2430 => x"74187033",
+2431 => x"70782b79",
+2432 => x"078118f8",
+2433 => x"1a5a5859",
+2434 => x"51548475",
+2435 => x"24ea3876",
+2436 => x"8e1b239c",
+2437 => x"19588070",
+2438 => x"5657b856",
+2439 => x"74187033",
+2440 => x"70782b79",
+2441 => x"078118f8",
+2442 => x"1a5a5859",
+2443 => x"5a548875",
+2444 => x"24ea3876",
+2445 => x"901b0c8b",
+2446 => x"3d0d04e9",
+2447 => x"3d0d6a80",
+2448 => x"dfd40857",
+2449 => x"57759338",
+2450 => x"80c0800b",
+2451 => x"84180c75",
+2452 => x"ac180c75",
+2453 => x"800c993d",
+2454 => x"0d04893d",
+2455 => x"70556a54",
+2456 => x"558a5299",
+2457 => x"3dffbc05",
+2458 => x"51ffbbd6",
+2459 => x"3f800877",
+2460 => x"53755256",
+2461 => x"fd953fbc",
+2462 => x"3f778008",
+2463 => x"0c75800c",
+2464 => x"993d0d04",
+2465 => x"fc3d0d81",
+2466 => x"5480dfd4",
+2467 => x"08883873",
+2468 => x"800c863d",
+2469 => x"0d047653",
+2470 => x"97b95286",
+2471 => x"3dfc0551",
+2472 => x"ffbb9f3f",
+2473 => x"8008548c",
+2474 => x"3f748008",
+2475 => x"0c73800c",
+2476 => x"863d0d04",
+2477 => x"80cfe408",
+2478 => x"800c04f7",
+2479 => x"3d0d7b80",
+2480 => x"cfe40882",
+2481 => x"c811085a",
+2482 => x"545a7780",
+2483 => x"2e80da38",
+2484 => x"81881884",
+2485 => x"1908ff05",
+2486 => x"81712b59",
+2487 => x"55598074",
+2488 => x"2480ea38",
+2489 => x"807424b5",
+2490 => x"3873822b",
+2491 => x"78118805",
+2492 => x"56568180",
+2493 => x"19087706",
+2494 => x"5372802e",
+2495 => x"b6387816",
+2496 => x"70085353",
+2497 => x"79517408",
+2498 => x"53722dff",
+2499 => x"14fc17fc",
+2500 => x"1779812c",
+2501 => x"5a575754",
+2502 => x"738025d6",
+2503 => x"38770858",
+2504 => x"77ffad38",
+2505 => x"80cfe408",
+2506 => x"53bc1308",
+2507 => x"a5387951",
+2508 => x"f8e23f74",
+2509 => x"0853722d",
+2510 => x"ff14fc17",
+2511 => x"fc177981",
+2512 => x"2c5a5757",
+2513 => x"54738025",
+2514 => x"ffa838d1",
+2515 => x"398057ff",
+2516 => x"93397251",
+2517 => x"bc130854",
+2518 => x"732d7951",
+2519 => x"f8b63f70",
+2520 => x"7080dfb0",
+2521 => x"0bfc0570",
+2522 => x"08525270",
+2523 => x"ff2e9138",
+2524 => x"702dfc12",
+2525 => x"70085252",
+2526 => x"70ff2e09",
+2527 => x"8106f138",
+2528 => x"50500404",
+2529 => x"ffbb8c3f",
+2530 => x"04000000",
+2531 => x"00000040",
+2532 => x"48656c6c",
+2533 => x"6f20776f",
+2534 => x"726c6420",
+2535 => x"310a0000",
+2536 => x"48656c6c",
+2537 => x"6f20776f",
+2538 => x"726c6420",
+2539 => x"320a0000",
+2540 => x"0a000000",
+2541 => x"43000000",
+2542 => x"64756d6d",
+2543 => x"792e6578",
+2544 => x"65000000",
+2545 => x"00ffffff",
+2546 => x"ff00ffff",
+2547 => x"ffff00ff",
+2548 => x"ffffff00",
+2549 => x"00000000",
+2550 => x"00000000",
+2551 => x"00000000",
+2552 => x"00002fb8",
+2553 => x"000027e8",
+2554 => x"00000000",
+2555 => x"00002a50",
+2556 => x"00002aac",
+2557 => x"00002b08",
+2558 => x"00000000",
+2559 => x"00000000",
+2560 => x"00000000",
+2561 => x"00000000",
+2562 => x"00000000",
+2563 => x"00000000",
+2564 => x"00000000",
+2565 => x"00000000",
+2566 => x"00000000",
+2567 => x"000027b4",
+2568 => x"00000000",
+2569 => x"00000000",
+2570 => x"00000000",
+2571 => x"00000000",
+2572 => x"00000000",
+2573 => x"00000000",
+2574 => x"00000000",
+2575 => x"00000000",
+2576 => x"00000000",
+2577 => x"00000000",
+2578 => x"00000000",
+2579 => x"00000000",
+2580 => x"00000000",
+2581 => x"00000000",
+2582 => x"00000000",
+2583 => x"00000000",
+2584 => x"00000000",
+2585 => x"00000000",
+2586 => x"00000000",
+2587 => x"00000000",
+2588 => x"00000000",
+2589 => x"00000000",
+2590 => x"00000000",
+2591 => x"00000000",
+2592 => x"00000000",
+2593 => x"00000000",
+2594 => x"00000000",
+2595 => x"00000000",
+2596 => x"00000001",
+2597 => x"330eabcd",
+2598 => x"1234e66d",
+2599 => x"deec0005",
+2600 => x"000b0000",
+2601 => x"00000000",
+2602 => x"00000000",
+2603 => x"00000000",
+2604 => x"00000000",
+2605 => x"00000000",
+2606 => x"00000000",
+2607 => x"00000000",
+2608 => x"00000000",
+2609 => x"00000000",
+2610 => x"00000000",
+2611 => x"00000000",
+2612 => x"00000000",
+2613 => x"00000000",
+2614 => x"00000000",
+2615 => x"00000000",
+2616 => x"00000000",
+2617 => x"00000000",
+2618 => x"00000000",
+2619 => x"00000000",
+2620 => x"00000000",
+2621 => x"00000000",
+2622 => x"00000000",
+2623 => x"00000000",
+2624 => x"00000000",
+2625 => x"00000000",
+2626 => x"00000000",
+2627 => x"00000000",
+2628 => x"00000000",
+2629 => x"00000000",
+2630 => x"00000000",
+2631 => x"00000000",
+2632 => x"00000000",
+2633 => x"00000000",
+2634 => x"00000000",
+2635 => x"00000000",
+2636 => x"00000000",
+2637 => x"00000000",
+2638 => x"00000000",
+2639 => x"00000000",
+2640 => x"00000000",
+2641 => x"00000000",
+2642 => x"00000000",
+2643 => x"00000000",
+2644 => x"00000000",
+2645 => x"00000000",
+2646 => x"00000000",
+2647 => x"00000000",
+2648 => x"00000000",
+2649 => x"00000000",
+2650 => x"00000000",
+2651 => x"00000000",
+2652 => x"00000000",
+2653 => x"00000000",
+2654 => x"00000000",
+2655 => x"00000000",
+2656 => x"00000000",
+2657 => x"00000000",
+2658 => x"00000000",
+2659 => x"00000000",
+2660 => x"00000000",
+2661 => x"00000000",
+2662 => x"00000000",
+2663 => x"00000000",
+2664 => x"00000000",
+2665 => x"00000000",
+2666 => x"00000000",
+2667 => x"00000000",
+2668 => x"00000000",
+2669 => x"00000000",
+2670 => x"00000000",
+2671 => x"00000000",
+2672 => x"00000000",
+2673 => x"00000000",
+2674 => x"00000000",
+2675 => x"00000000",
+2676 => x"00000000",
+2677 => x"00000000",
+2678 => x"00000000",
+2679 => x"00000000",
+2680 => x"00000000",
+2681 => x"00000000",
+2682 => x"00000000",
+2683 => x"00000000",
+2684 => x"00000000",
+2685 => x"00000000",
+2686 => x"00000000",
+2687 => x"00000000",
+2688 => x"00000000",
+2689 => x"00000000",
+2690 => x"00000000",
+2691 => x"00000000",
+2692 => x"00000000",
+2693 => x"00000000",
+2694 => x"00000000",
+2695 => x"00000000",
+2696 => x"00000000",
+2697 => x"00000000",
+2698 => x"00000000",
+2699 => x"00000000",
+2700 => x"00000000",
+2701 => x"00000000",
+2702 => x"00000000",
+2703 => x"00000000",
+2704 => x"00000000",
+2705 => x"00000000",
+2706 => x"00000000",
+2707 => x"00000000",
+2708 => x"00000000",
+2709 => x"00000000",
+2710 => x"00000000",
+2711 => x"00000000",
+2712 => x"00000000",
+2713 => x"00000000",
+2714 => x"00000000",
+2715 => x"00000000",
+2716 => x"00000000",
+2717 => x"00000000",
+2718 => x"00000000",
+2719 => x"00000000",
+2720 => x"00000000",
+2721 => x"00000000",
+2722 => x"00000000",
+2723 => x"00000000",
+2724 => x"00000000",
+2725 => x"00000000",
+2726 => x"00000000",
+2727 => x"00000000",
+2728 => x"00000000",
+2729 => x"00000000",
+2730 => x"00000000",
+2731 => x"00000000",
+2732 => x"00000000",
+2733 => x"00000000",
+2734 => x"00000000",
+2735 => x"00000000",
+2736 => x"00000000",
+2737 => x"00000000",
+2738 => x"00000000",
+2739 => x"00000000",
+2740 => x"00000000",
+2741 => x"00000000",
+2742 => x"00000000",
+2743 => x"00000000",
+2744 => x"00000000",
+2745 => x"00000000",
+2746 => x"00000000",
+2747 => x"00000000",
+2748 => x"00000000",
+2749 => x"00000000",
+2750 => x"00000000",
+2751 => x"00000000",
+2752 => x"00000000",
+2753 => x"00000000",
+2754 => x"00000000",
+2755 => x"00000000",
+2756 => x"00000000",
+2757 => x"00000000",
+2758 => x"00000000",
+2759 => x"00000000",
+2760 => x"00000000",
+2761 => x"00000000",
+2762 => x"00000000",
+2763 => x"00000000",
+2764 => x"00000000",
+2765 => x"00000000",
+2766 => x"00000000",
+2767 => x"00000000",
+2768 => x"00000000",
+2769 => x"00000000",
+2770 => x"00000000",
+2771 => x"00000000",
+2772 => x"00000000",
+2773 => x"00000000",
+2774 => x"00000000",
+2775 => x"00000000",
+2776 => x"00000000",
+2777 => x"00000000",
+2778 => x"00000000",
+2779 => x"00000000",
+2780 => x"00000000",
+2781 => x"00000000",
+2782 => x"00000000",
+2783 => x"00000000",
+2784 => x"00000000",
+2785 => x"00000000",
+2786 => x"00000000",
+2787 => x"00000000",
+2788 => x"00000000",
+2789 => x"ffffffff",
+2790 => x"00000000",
+2791 => x"00020000",
+2792 => x"00000000",
+2793 => x"00000000",
+2794 => x"00002ba0",
+2795 => x"00002ba0",
+2796 => x"00002ba8",
+2797 => x"00002ba8",
+2798 => x"00002bb0",
+2799 => x"00002bb0",
+2800 => x"00002bb8",
+2801 => x"00002bb8",
+2802 => x"00002bc0",
+2803 => x"00002bc0",
+2804 => x"00002bc8",
+2805 => x"00002bc8",
+2806 => x"00002bd0",
+2807 => x"00002bd0",
+2808 => x"00002bd8",
+2809 => x"00002bd8",
+2810 => x"00002be0",
+2811 => x"00002be0",
+2812 => x"00002be8",
+2813 => x"00002be8",
+2814 => x"00002bf0",
+2815 => x"00002bf0",
+2816 => x"00002bf8",
+2817 => x"00002bf8",
+2818 => x"00002c00",
+2819 => x"00002c00",
+2820 => x"00002c08",
+2821 => x"00002c08",
+2822 => x"00002c10",
+2823 => x"00002c10",
+2824 => x"00002c18",
+2825 => x"00002c18",
+2826 => x"00002c20",
+2827 => x"00002c20",
+2828 => x"00002c28",
+2829 => x"00002c28",
+2830 => x"00002c30",
+2831 => x"00002c30",
+2832 => x"00002c38",
+2833 => x"00002c38",
+2834 => x"00002c40",
+2835 => x"00002c40",
+2836 => x"00002c48",
+2837 => x"00002c48",
+2838 => x"00002c50",
+2839 => x"00002c50",
+2840 => x"00002c58",
+2841 => x"00002c58",
+2842 => x"00002c60",
+2843 => x"00002c60",
+2844 => x"00002c68",
+2845 => x"00002c68",
+2846 => x"00002c70",
+2847 => x"00002c70",
+2848 => x"00002c78",
+2849 => x"00002c78",
+2850 => x"00002c80",
+2851 => x"00002c80",
+2852 => x"00002c88",
+2853 => x"00002c88",
+2854 => x"00002c90",
+2855 => x"00002c90",
+2856 => x"00002c98",
+2857 => x"00002c98",
+2858 => x"00002ca0",
+2859 => x"00002ca0",
+2860 => x"00002ca8",
+2861 => x"00002ca8",
+2862 => x"00002cb0",
+2863 => x"00002cb0",
+2864 => x"00002cb8",
+2865 => x"00002cb8",
+2866 => x"00002cc0",
+2867 => x"00002cc0",
+2868 => x"00002cc8",
+2869 => x"00002cc8",
+2870 => x"00002cd0",
+2871 => x"00002cd0",
+2872 => x"00002cd8",
+2873 => x"00002cd8",
+2874 => x"00002ce0",
+2875 => x"00002ce0",
+2876 => x"00002ce8",
+2877 => x"00002ce8",
+2878 => x"00002cf0",
+2879 => x"00002cf0",
+2880 => x"00002cf8",
+2881 => x"00002cf8",
+2882 => x"00002d00",
+2883 => x"00002d00",
+2884 => x"00002d08",
+2885 => x"00002d08",
+2886 => x"00002d10",
+2887 => x"00002d10",
+2888 => x"00002d18",
+2889 => x"00002d18",
+2890 => x"00002d20",
+2891 => x"00002d20",
+2892 => x"00002d28",
+2893 => x"00002d28",
+2894 => x"00002d30",
+2895 => x"00002d30",
+2896 => x"00002d38",
+2897 => x"00002d38",
+2898 => x"00002d40",
+2899 => x"00002d40",
+2900 => x"00002d48",
+2901 => x"00002d48",
+2902 => x"00002d50",
+2903 => x"00002d50",
+2904 => x"00002d58",
+2905 => x"00002d58",
+2906 => x"00002d60",
+2907 => x"00002d60",
+2908 => x"00002d68",
+2909 => x"00002d68",
+2910 => x"00002d70",
+2911 => x"00002d70",
+2912 => x"00002d78",
+2913 => x"00002d78",
+2914 => x"00002d80",
+2915 => x"00002d80",
+2916 => x"00002d88",
+2917 => x"00002d88",
+2918 => x"00002d90",
+2919 => x"00002d90",
+2920 => x"00002d98",
+2921 => x"00002d98",
+2922 => x"00002da0",
+2923 => x"00002da0",
+2924 => x"00002da8",
+2925 => x"00002da8",
+2926 => x"00002db0",
+2927 => x"00002db0",
+2928 => x"00002db8",
+2929 => x"00002db8",
+2930 => x"00002dc0",
+2931 => x"00002dc0",
+2932 => x"00002dc8",
+2933 => x"00002dc8",
+2934 => x"00002dd0",
+2935 => x"00002dd0",
+2936 => x"00002dd8",
+2937 => x"00002dd8",
+2938 => x"00002de0",
+2939 => x"00002de0",
+2940 => x"00002de8",
+2941 => x"00002de8",
+2942 => x"00002df0",
+2943 => x"00002df0",
+2944 => x"00002df8",
+2945 => x"00002df8",
+2946 => x"00002e00",
+2947 => x"00002e00",
+2948 => x"00002e08",
+2949 => x"00002e08",
+2950 => x"00002e10",
+2951 => x"00002e10",
+2952 => x"00002e18",
+2953 => x"00002e18",
+2954 => x"00002e20",
+2955 => x"00002e20",
+2956 => x"00002e28",
+2957 => x"00002e28",
+2958 => x"00002e30",
+2959 => x"00002e30",
+2960 => x"00002e38",
+2961 => x"00002e38",
+2962 => x"00002e40",
+2963 => x"00002e40",
+2964 => x"00002e48",
+2965 => x"00002e48",
+2966 => x"00002e50",
+2967 => x"00002e50",
+2968 => x"00002e58",
+2969 => x"00002e58",
+2970 => x"00002e60",
+2971 => x"00002e60",
+2972 => x"00002e68",
+2973 => x"00002e68",
+2974 => x"00002e70",
+2975 => x"00002e70",
+2976 => x"00002e78",
+2977 => x"00002e78",
+2978 => x"00002e80",
+2979 => x"00002e80",
+2980 => x"00002e88",
+2981 => x"00002e88",
+2982 => x"00002e90",
+2983 => x"00002e90",
+2984 => x"00002e98",
+2985 => x"00002e98",
+2986 => x"00002ea0",
+2987 => x"00002ea0",
+2988 => x"00002ea8",
+2989 => x"00002ea8",
+2990 => x"00002eb0",
+2991 => x"00002eb0",
+2992 => x"00002eb8",
+2993 => x"00002eb8",
+2994 => x"00002ec0",
+2995 => x"00002ec0",
+2996 => x"00002ec8",
+2997 => x"00002ec8",
+2998 => x"00002ed0",
+2999 => x"00002ed0",
+3000 => x"00002ed8",
+3001 => x"00002ed8",
+3002 => x"00002ee0",
+3003 => x"00002ee0",
+3004 => x"00002ee8",
+3005 => x"00002ee8",
+3006 => x"00002ef0",
+3007 => x"00002ef0",
+3008 => x"00002ef8",
+3009 => x"00002ef8",
+3010 => x"00002f00",
+3011 => x"00002f00",
+3012 => x"00002f08",
+3013 => x"00002f08",
+3014 => x"00002f10",
+3015 => x"00002f10",
+3016 => x"00002f18",
+3017 => x"00002f18",
+3018 => x"00002f20",
+3019 => x"00002f20",
+3020 => x"00002f28",
+3021 => x"00002f28",
+3022 => x"00002f30",
+3023 => x"00002f30",
+3024 => x"00002f38",
+3025 => x"00002f38",
+3026 => x"00002f40",
+3027 => x"00002f40",
+3028 => x"00002f48",
+3029 => x"00002f48",
+3030 => x"00002f50",
+3031 => x"00002f50",
+3032 => x"00002f58",
+3033 => x"00002f58",
+3034 => x"00002f60",
+3035 => x"00002f60",
+3036 => x"00002f68",
+3037 => x"00002f68",
+3038 => x"00002f70",
+3039 => x"00002f70",
+3040 => x"00002f78",
+3041 => x"00002f78",
+3042 => x"00002f80",
+3043 => x"00002f80",
+3044 => x"00002f88",
+3045 => x"00002f88",
+3046 => x"00002f90",
+3047 => x"00002f90",
+3048 => x"00002f98",
+3049 => x"00002f98",
+3050 => x"000027b8",
+3051 => x"ffffffff",
+3052 => x"00000000",
+3053 => x"ffffffff",
+3054 => x"00000000",
+ others => x"00000000"
+);
+
+begin
+
+mem_busy<=mem_readEnable; -- we're done on the cycle after we serve the read request
+
+process (clk, areset)
+begin
+ if areset = '1' then
+ elsif (clk'event and clk = '1') then
+ if (mem_writeEnable = '1') then
+ ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit)))) := mem_write;
+ end if;
+ if (mem_readEnable = '1') then
+ mem_read <= ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit))));
+ end if;
+ end if;
+end process;
+
+
+
+
+end dram_arch;
diff --git a/zpu/hdl/example_medium/sim_fpga_top.vhd b/zpu/hdl/example_medium/sim_fpga_top.vhd
new file mode 100644
index 0000000..962caad
--- /dev/null
+++ b/zpu/hdl/example_medium/sim_fpga_top.vhd
@@ -0,0 +1,194 @@
+--------------------------------------------------------------------------------
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+--
+-- The FreeBSD license
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+--
+-- 1. Redistributions of source code must retain the above copyright
+-- notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+-- copyright notice, this list of conditions and the following
+-- disclaimer in the documentation and/or other materials
+-- provided with the distribution.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.zpu_config.all;
+
+
+entity fpga_top is
+end fpga_top;
+
+use work.zpupkg.all;
+
+architecture behave of fpga_top is
+
+
+ signal clk : std_logic;
+
+ signal areset : std_logic := '1';
+
+
+ component zpu_io is
+ generic (
+ log_file: string := "log.txt"
+ );
+ port (
+ clk : in std_logic;
+ areset : in std_logic;
+ busy : out std_logic;
+ writeEnable : in std_logic;
+ readEnable : in std_logic;
+ write : in std_logic_vector(wordSize-1 downto 0);
+ read : out std_logic_vector(wordSize-1 downto 0);
+ addr : in std_logic_vector(maxAddrBit downto minAddrBit)
+ );
+ end component;
+
+
+ signal mem_busy : std_logic;
+ signal mem_read : std_logic_vector(wordSize-1 downto 0);
+ signal mem_write : std_logic_vector(wordSize-1 downto 0);
+ signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);
+ signal mem_writeEnable : std_logic;
+ signal mem_readEnable : std_logic;
+ signal mem_writeMask : std_logic_vector(wordBytes-1 downto 0);
+
+ signal enable : std_logic;
+
+ signal dram_mem_busy : std_logic;
+ signal dram_mem_read : std_logic_vector(wordSize-1 downto 0);
+ signal dram_mem_write : std_logic_vector(wordSize-1 downto 0);
+ signal dram_mem_writeEnable : std_logic;
+ signal dram_mem_readEnable : std_logic;
+ signal dram_mem_writeMask : std_logic_vector(wordBytes-1 downto 0);
+
+ signal io_busy : std_logic;
+
+ signal io_mem_read : std_logic_vector(wordSize-1 downto 0);
+ signal io_mem_writeEnable : std_logic;
+ signal io_mem_readEnable : std_logic;
+
+ signal dram_ready : std_logic;
+ signal io_ready : std_logic;
+ signal io_reading : std_logic;
+
+ signal break : std_logic;
+
+begin
+
+ zpu: zpu_core
+ port map (
+ clk => clk,
+ reset => areset,
+ enable => enable,
+ in_mem_busy => mem_busy,
+ mem_read => mem_read,
+ mem_write => mem_write,
+ out_mem_addr => mem_addr,
+ out_mem_writeEnable => mem_writeEnable,
+ out_mem_readEnable => mem_readEnable,
+ mem_writeMask => mem_writeMask,
+ interrupt => '0',
+ break => break
+ );
+
+ dram_imp: dram
+ port map (
+ clk => clk ,
+ areset => areset,
+ mem_busy => dram_mem_busy,
+ mem_read => dram_mem_read,
+ mem_write => mem_write,
+ mem_addr => mem_addr(maxAddrBit downto 0),
+ mem_writeEnable => dram_mem_writeEnable,
+ mem_readEnable => dram_mem_readEnable,
+ mem_writeMask => mem_writeMask
+ );
+
+
+ ioMap: zpu_io
+ port map (
+ clk => clk,
+ areset => areset,
+ busy => io_busy,
+ writeEnable => io_mem_writeEnable,
+ readEnable => io_mem_readEnable,
+ write => mem_write(wordSize-1 downto 0),
+ read => io_mem_read,
+ addr => mem_addr(maxAddrBit downto minAddrBit)
+ );
+
+ dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit);
+ dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit);
+ io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit);
+ io_mem_readEnable <= mem_readEnable and mem_addr(ioBit);
+ mem_busy <= io_busy or dram_mem_busy or io_busy;
+
+
+ -- Memory reads either come from IO or DRAM. We need to pick the right one.
+ memorycontrol: process(dram_mem_read, dram_ready, io_ready, io_mem_read)
+ begin
+ mem_read <= (others => 'U');
+ if dram_ready='1' then
+ mem_read <= dram_mem_read;
+ end if;
+
+ if io_ready='1' then
+ mem_read <= io_mem_read;
+ end if;
+ end process;
+
+
+ io_ready <= (io_reading or io_mem_readEnable) and not io_busy;
+
+ memoryControlSync: process(clk, areset)
+ begin
+ if areset = '1' then
+ enable <= '0';
+ io_reading <= '0';
+ dram_ready <= '0';
+ elsif rising_edge(clk) then
+ enable <= '1';
+ io_reading <= io_busy or io_mem_readEnable;
+ dram_ready <= dram_mem_readEnable;
+ end if;
+ end process;
+
+ -- wiggle the clock @ 100MHz
+ clock : process
+ begin
+ clk <= '0';
+ wait for 5 ns;
+ clk <= '1';
+ wait for 5 ns;
+ areset <= '0';
+ end process clock;
+
+
+end architecture behave;
diff --git a/zpu/hdl/example_medium/simzpu_medium.do b/zpu/hdl/example_medium/simzpu_medium.do
new file mode 100644
index 0000000..2b77ba6
--- /dev/null
+++ b/zpu/hdl/example_medium/simzpu_medium.do
@@ -0,0 +1,28 @@
+# Xilinx WebPack modelsim script
+#
+# cd C:/workspace/zpu/zpu/hdl/example_medium
+# do simzpu_medium.do
+
+set BreakOnAssertion 1
+vlib work
+
+vcom -93 -explicit zpu_config_trace.vhd
+vcom -93 -explicit ../zpu4/core/zpupkg.vhd
+vcom -93 -explicit ../zpu4/src/txt_util.vhd
+vcom -93 -explicit sim_fpga_top.vhd
+vcom -93 -explicit ../zpu4/core/zpu_core.vhd
+vcom -93 -explicit dram_hello.vhd
+vcom -93 -explicit ../zpu4/src/timer.vhd
+vcom -93 -explicit ../zpu4/src/io.vhd
+vcom -93 -explicit ../zpu4/src/trace.vhd
+
+# run ZPU
+vsim fpga_top
+view wave
+add wave -recursive fpga_top/zpu/*
+#add wave -recursive fpga_top/*
+view structure
+#view signals
+
+# Enough to run tiny programs
+run 1000 ms
diff --git a/zpu/hdl/example_medium/zpu_config_trace.vhd b/zpu/hdl/example_medium/zpu_config_trace.vhd
new file mode 100644
index 0000000..a5b9192
--- /dev/null
+++ b/zpu/hdl/example_medium/zpu_config_trace.vhd
@@ -0,0 +1,17 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+package zpu_config is
+
+ constant Generate_Trace : boolean := true;
+ constant wordPower : integer := 5;
+ -- during simulation, set this to '0' to get matching trace.txt
+ constant DontCareValue : std_logic := '0';
+ -- Clock frequency in MHz.
+ constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64";
+ constant maxAddrBitIncIO : integer := 27;
+ constant maxAddrBitDRAM : integer := 16;
+ constant maxAddrBitBRAM : integer := 16;
+ constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"001fff8";
+
+end zpu_config;
diff --git a/zpu/hdl/sim/dmipssmalltrace.do b/zpu/hdl/sim/dmipssmalltrace.do
new file mode 100644
index 0000000..eb4c6fe
--- /dev/null
+++ b/zpu/hdl/sim/dmipssmalltrace.do
@@ -0,0 +1,26 @@
+set BreakOnAssertion 1
+vlib work
+
+vcom -93 -explicit zpu_config_trace.vhd
+vcom -93 -explicit zpupkg.vhd
+vcom -93 -explicit txt_util.vhd
+vcom -93 -explicit sim_fpga_top.vhd
+vcom -93 -explicit zpu_core_small.vhd
+vcom -93 -explicit bram_dmips.vhd
+vcom -93 -explicit dram_dmips.vhd
+vcom -93 -explicit timer.vhd
+vcom -93 -explicit io.vhd
+vcom -93 -explicit trace.vhd
+
+
+vsim fpga_top
+view wave
+
+add wave -recursive fpga_top/zpu/*
+#--add wave -recursive fpga_top/ioMap/*
+#add wave -recursive fpga_top/*
+view structure
+
+
+# run ZPU
+run 5 ms
diff --git a/zpu/hdl/sim/dmipstrace.do b/zpu/hdl/sim/dmipstrace.do
new file mode 100644
index 0000000..64cf8fd
--- /dev/null
+++ b/zpu/hdl/sim/dmipstrace.do
@@ -0,0 +1,30 @@
+# Xilinx WebPack modelsim script
+#
+# cd C:/workspace/zpu/zpu/hdl/zpu4/src
+# do dmipstrace.do
+
+set BreakOnAssertion 1
+vlib work
+
+vcom -93 -explicit zpu_config_trace.vhd
+vcom -93 -explicit zpupkg.vhd
+vcom -93 -explicit txt_util.vhd
+vcom -93 -explicit sim_fpga_top.vhd
+vcom -93 -explicit zpu_core.vhd
+vcom -93 -explicit dram_dmips.vhd
+vcom -93 -explicit timer.vhd
+vcom -93 -explicit io.vhd
+vcom -93 -explicit trace.vhd
+
+
+vsim fpga_top
+view wave
+
+add wave -recursive fpga_top/zpu/*
+#--add wave -recursive fpga_top/ioMap/*
+#add wave -recursive fpga_top/*
+view structure
+
+
+# run ZPU
+run 5 ms
diff --git a/zpu/hdl/spi/spi_controller.v b/zpu/hdl/spi/spi_controller.v
new file mode 100644
index 0000000..b22f294
--- /dev/null
+++ b/zpu/hdl/spi/spi_controller.v
@@ -0,0 +1,235 @@
+/*
+ SPI flash read-only controller
+
+ Copyright 2008 Álvaro Lopes <alvieboy@alvie.com>
+
+ Version: 1.3
+
+ The FreeBSD license
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ 1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials
+ provided with the distribution.
+
+ THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
+ EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ Changelog:
+
+ 1.3: Remove async reset from spi_data shift register
+ Fix indentation of code
+
+ 1.2: Fix read count for sequential fetch
+
+ 1.1: Move port types outside module declaration.
+ Fix state machine to handle clock stop
+ Remove err out report
+ Fix SPI_CLK generation.
+*/
+
+module spi_controller (
+ clk, // Clock
+ rst, // Reset
+ ce, // Chip Enable
+ ack, // Acknowledge
+
+ adr, // Address in
+ dat_o, // Data out
+
+ SPI_MOSI, // Master Out/Slave In for SPI
+ SPI_MISO, // Master In/Slave Out for SPI
+ SPI_CLK, // SPI clock
+ SPI_SELN // SPI nSEL
+);
+
+parameter Tp = 0; // Propagation delay - for simulation
+parameter INIT_CLOCK_CYCLE_WAIT = 2; // Clock cycles to wait before init
+parameter DESELECT_CYCLES = 3; // Clock cycles to wait after deselection - should give 100ns at least
+parameter SPI_REGISTER_SIZE = 40;
+parameter SPI_ADDRESS_SIZE = 24;
+
+input clk;
+input rst;
+input ce;
+output reg ack;
+
+input [SPI_ADDRESS_SIZE-1:0] adr;
+output reg [31:0] dat_o;
+
+output reg SPI_MOSI;
+input SPI_MISO;
+output SPI_CLK;
+output reg SPI_SELN;
+
+
+// FSM states
+localparam SPI_STATE_WAIT = 7'b0000001,
+ SPI_STATE_IDLE = 7'b0000010,
+ SPI_STATE_WACK = 7'b0000100,
+ SPI_STATE_SEND = 7'b0001000,
+ SPI_STATE_BREAD = 7'b0010000,
+ SPI_STATE_READ = 7'b0100000,
+ SPI_STATE_WDES = 7'b1000000;
+
+// SPI commands
+localparam SPI_CMD_READ_FAST = 8'b00001011;
+
+
+// Shift register to hold command to be sent to SPI
+reg [SPI_REGISTER_SIZE-1:0] spi_shift_register_out;
+
+integer spi_reg_count;
+
+reg [8:0] spi_read_count;
+reg [7:0] spi_data;
+reg [3:0] data_valid_window;
+reg [SPI_REGISTER_SIZE-1:0] next_address;
+
+integer dsel_dly;
+integer spi_init_count;
+reg spi_start_count;
+reg spi_enable_clock; // Enable SPI clock
+reg [6:0] spi_state; // SPI state machine
+
+/*
+ SPI clock generation
+*/
+
+assign SPI_CLK = spi_enable_clock?~clk:1'b0;
+
+reg seq_read; // Sequential read in progress
+
+always @(posedge clk or posedge rst)
+begin
+ if ( rst ) begin
+ spi_enable_clock <= #Tp 1'b0;
+ spi_state <= #Tp SPI_STATE_WAIT;
+ spi_init_count <= #Tp INIT_CLOCK_CYCLE_WAIT;
+ SPI_SELN <= #Tp 1'b1;
+ ack <= #Tp 1'b0;
+ spi_start_count <= #Tp 1'b0;
+ next_address <= #Tp 32'hFFFFFFFF;
+ end else begin
+
+ case (spi_state)
+ SPI_STATE_WAIT:
+ begin
+ if ( spi_init_count == 0 ) begin
+ spi_state <= SPI_STATE_IDLE;
+ end else begin
+ spi_init_count <= #Tp spi_init_count - 1;
+ end
+ end
+ SPI_STATE_IDLE:
+ begin
+
+ if ( ce ) begin
+ next_address <= { adr[SPI_ADDRESS_SIZE-1:2], 2'b0 } + 4;
+ seq_read = adr[SPI_ADDRESS_SIZE-1:2] == next_address[SPI_ADDRESS_SIZE-1:2];
+ // Latch address (24 bit wordsize)
+ spi_shift_register_out <= #Tp { SPI_CMD_READ_FAST, adr[SPI_ADDRESS_SIZE-1:2], 2'b0, 8'b0 };
+
+ spi_enable_clock <= #Tp 1'b1;
+
+ if ( seq_read ) begin
+ spi_state <= #Tp SPI_STATE_BREAD;
+ end else begin
+ SPI_SELN <= 1'b1 ;
+ spi_reg_count <= #Tp SPI_REGISTER_SIZE;
+ dsel_dly <= DESELECT_CYCLES;
+ spi_state <= #Tp SPI_STATE_WDES;
+ end
+ end
+ end
+ SPI_STATE_WACK:
+ begin
+ ack <= 1'b0;
+ spi_state <= SPI_STATE_IDLE;
+ end
+ SPI_STATE_SEND:
+ begin
+
+ SPI_SELN <=#Tp 1'b0;
+
+ if (spi_reg_count == 0)
+ begin
+ spi_state <= #Tp SPI_STATE_BREAD;
+ end else begin
+ SPI_MOSI <= #Tp spi_shift_register_out[SPI_REGISTER_SIZE-1];
+ spi_shift_register_out <= #Tp { spi_shift_register_out[SPI_REGISTER_SIZE-2:0], 1'b0 };
+ spi_reg_count <= #Tp spi_reg_count - 1;
+ end
+ end
+ SPI_STATE_BREAD:
+ begin
+ spi_start_count <= #Tp 1'b1;
+ spi_state <= #Tp SPI_STATE_READ;
+ end
+ SPI_STATE_READ:
+ begin
+ spi_start_count <= #Tp 1'b0;
+
+ // Stop clock a bit earlier
+ if ( data_valid_window[3] && spi_read_count[1] )
+ spi_enable_clock <= 1'b0;
+
+ if (spi_read_count[0])
+ begin
+
+ dat_o <= #Tp { dat_o[23:0], spi_data };
+
+ if ( data_valid_window[3] ) begin
+ ack <= #Tp 1'b1;
+ spi_state <= #Tp SPI_STATE_WACK;
+ end
+ end
+ end
+ SPI_STATE_WDES:
+ begin
+ if ( dsel_dly == 0 )
+ spi_state <= SPI_STATE_SEND;
+ else
+ dsel_dly <= dsel_dly -1;
+ end
+ endcase
+ end
+end
+
+always @(posedge clk)
+begin
+ if (spi_start_count) begin
+ spi_read_count <= 8'b01000000;
+ data_valid_window <= #Tp 5'b00001;
+ end else begin
+ if ( spi_read_count[0] ) begin
+ data_valid_window <= #Tp { data_valid_window[3:0], 1'b0 };
+ end
+ spi_read_count <= #Tp { spi_read_count[0] ,spi_read_count[7:1] };
+ end
+end
+
+// SPI data shift register
+
+always @(negedge clk)
+begin
+ spi_data <= #Tp { spi_data[6:0], SPI_MISO };
+end
+
+endmodule
diff --git a/zpu/hdl/wishbone/wishbone_pkg.vhd b/zpu/hdl/wishbone/wishbone_pkg.vhd
new file mode 100644
index 0000000..b6d30ee
--- /dev/null
+++ b/zpu/hdl/wishbone/wishbone_pkg.vhd
@@ -0,0 +1,86 @@
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+--
+-- The FreeBSD license
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+--
+-- 1. Redistributions of source code must retain the above copyright
+-- notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+-- copyright notice, this list of conditions and the following
+-- disclaimer in the documentation and/or other materials
+-- provided with the distribution.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+package wishbone_pkg is
+
+ type wishbone_bus_in is record
+ adr : std_logic_vector(31 downto 0);
+ sel : std_logic_vector(3 downto 0);
+ we : std_logic;
+ dat : std_logic_vector(31 downto 0); -- Note! Data written with 'we'
+ cyc : std_logic;
+ stb : std_logic;
+ end record;
+
+ type wishbone_bus_out is record
+ dat : std_logic_vector(31 downto 0);
+ ack : std_logic;
+ end record;
+
+ type wishbone_bus is record
+ insig : wishbone_bus_in;
+ outsig : wishbone_bus_out;
+ end record;
+
+ component atomic32_access is
+ port ( cpu_clk : in std_logic;
+ areset : in std_logic;
+
+ -- Wishbone from CPU interface
+ wb_16_i : in wishbone_bus_in;
+ wb_16_o : out wishbone_bus_out;
+ -- Wishbone to FPGA registers and ethernet core
+ wb_32_i : in wishbone_bus_out;
+ wb_32_o : out wishbone_bus_in);
+ end component;
+
+ component eth_access_corr is
+ port ( cpu_clk : in std_logic;
+ areset : in std_logic;
+
+ -- Wishbone from Wishbone MUX
+ eth_raw_o : out wishbone_bus_out;
+ eth_raw_i : in wishbone_bus_in;
+
+ -- Wishbone ethernet core
+ eth_slave_i : in wishbone_bus_out;
+ eth_slave_o : out wishbone_bus_in);
+ end component;
+
+
+end wishbone_pkg;
diff --git a/zpu/hdl/wishbone/zpu_system.vhd b/zpu/hdl/wishbone/zpu_system.vhd
new file mode 100644
index 0000000..07c5bdc
--- /dev/null
+++ b/zpu/hdl/wishbone/zpu_system.vhd
@@ -0,0 +1,104 @@
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+--
+-- The FreeBSD license
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+--
+-- 1. Redistributions of source code must retain the above copyright
+-- notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+-- copyright notice, this list of conditions and the following
+-- disclaimer in the documentation and/or other materials
+-- provided with the distribution.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.zpupkg.all;
+use work.zpu_config.all;
+
+entity zpu_system is
+ generic(
+ simulate : boolean := false);
+ port ( areset : in std_logic;
+ cpu_clk : in std_logic;
+
+ -- ZPU Control signals
+ enable : in std_logic;
+ interrupt : in std_logic;
+
+ zpu_status : out std_logic_vector(63 downto 0);
+
+ -- wishbone interfaces
+ zpu_wb_i : in wishbone_bus_out;
+ zpu_wb_o : out wishbone_bus_in);
+end zpu_system;
+
+architecture behave of zpu_system is
+
+signal mem_req : std_logic;
+signal mem_we : std_logic;
+signal mem_ack : std_logic;
+signal mem_read : std_logic_vector(wordSize-1 downto 0);
+signal mem_write : std_logic_vector(wordSize-1 downto 0);
+signal out_mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);
+signal mem_writeMask : std_logic_vector(wordBytes-1 downto 0);
+
+
+begin
+
+ my_zpu_core:
+ zpu_core port map (
+ clk => cpu_clk,
+ areset => areset,
+ enable => enable,
+ mem_req => mem_req,
+ mem_we => mem_we,
+ mem_ack => mem_ack,
+ mem_read => mem_read,
+ mem_write => mem_write,
+ out_mem_addr => out_mem_addr,
+ mem_writeMask => mem_writeMask,
+ interrupt => interrupt,
+ zpu_status => zpu_status,
+ break => open);
+
+ my_zpu_wb_bridge:
+ zpu_wb_bridge port map (
+ clk => cpu_clk,
+ areset => areset,
+ mem_req => mem_req,
+ mem_we => mem_we,
+ mem_ack => mem_ack,
+ mem_read => mem_read,
+ mem_write => mem_write,
+ out_mem_addr => out_mem_addr,
+ mem_writeMask => mem_writeMask,
+ zpu_wb_i => zpu_wb_i,
+ zpu_wb_o => zpu_wb_o);
+
+end behave;
diff --git a/zpu/hdl/wishbone/zpu_wb_bridge.vhd b/zpu/hdl/wishbone/zpu_wb_bridge.vhd
new file mode 100644
index 0000000..086ae11
--- /dev/null
+++ b/zpu/hdl/wishbone/zpu_wb_bridge.vhd
@@ -0,0 +1,83 @@
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+--
+-- The FreeBSD license
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+--
+-- 1. Redistributions of source code must retain the above copyright
+-- notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+-- copyright notice, this list of conditions and the following
+-- disclaimer in the documentation and/or other materials
+-- provided with the distribution.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library work;
+use work.phi_config.all;
+use work.wishbone_pkg.all;
+use work.zpupkg.all;
+use work.zpu_config.all;
+
+entity zpu_wb_bridge is
+ port ( -- Native ZPU interface
+ clk : in std_logic;
+ areset : in std_logic;
+
+ mem_req : in std_logic;
+ mem_we : in std_logic;
+ mem_ack : out std_logic;
+ mem_read : out std_logic_vector(wordSize-1 downto 0);
+ mem_write : in std_logic_vector(wordSize-1 downto 0);
+ out_mem_addr : in std_logic_vector(maxAddrBitIncIO downto 0);
+ mem_writeMask : in std_logic_vector(wordBytes-1 downto 0);
+
+ -- Wishbone from ZPU
+ zpu_wb_i : in wishbone_bus_out;
+ zpu_wb_o : out wishbone_bus_in);
+
+end zpu_wb_bridge;
+
+architecture behave of zpu_wb_bridge is
+
+begin
+
+ mem_read <= zpu_wb_i.dat;
+ mem_ack <= zpu_wb_i.ack;
+
+ zpu_wb_o.adr <= "000000" & out_mem_addr(27) & out_mem_addr(24 downto 0);
+ zpu_wb_o.dat <= mem_write;
+ zpu_wb_o.sel <= mem_writeMask;
+ zpu_wb_o.stb <= mem_req;
+ zpu_wb_o.cyc <= mem_req;
+ zpu_wb_o.we <= mem_we;
+
+end behave;
+
+
+
+
+
diff --git a/zpu/hdl/zealot/0README.txt b/zpu/hdl/zealot/0README.txt
new file mode 100644
index 0000000..4bb4546
--- /dev/null
+++ b/zpu/hdl/zealot/0README.txt
@@ -0,0 +1,195 @@
+This is a test release of the ZPU.
+ZPU is a 32 bits stack CPU. This package contains a VHDL implementation
+suitable for FPGAs. It was tested using a Xilinx Spartan 3 1500 FPGA.
+
+The author of the ZPU is Øyvind Harboe (oyvind.harboe zylin.com) and the
+license is the BSD one. Portions of this package were developed by Salvador E.
+Tropea (salvador inti.gob.ar) and others. Some portions are under the GPL
+license.
+
+Øyvind also added a ZPU target to the gcc/gdb.
+
+For more information about the ZPU core please visit:
+http://www.zylin.com/zpu.htm
+http://www.opencores.org/projects.cgi/web/zpu/overview
+
+What are the files?
+-------------------
+
+zpu_medium.vhdl
+ZPU CPU, medium version.
+
+zpu_small.vhdl
+ZPU CPU, small version (Dual Port RAM only!).
+
+zpu_pkg.vhdl
+Package containing the declarations for the ZPU library.
+
+devices/phi_io.vhdl
+The very basic I/O peripherals needed for the standard C library. It includes a
+timer (64 bits clock counter) and an UART (8N1 without FIFO).
+This is known as the PHI I/O layout, this implementation isn't complete. Only
+the above mentioned peripherals are available.
+
+devices/timer.vhdl
+64 bits clock counter maped by the PHI I/O.
+
+devices/trace.vhdl
+This is used for debug purposes. The ZPU have a debug port to connect this
+module. It can generate an execution trace log during the simulation.
+
+devices/txt_util.vhdl
+Useful text handling routines for the simulation.
+
+devices/br_gen.vhdl
+Fixed baud rate generator for the UART.
+
+devices/rx_unit.vhdl
+UART Rx module.
+
+devices/tx_unit.vhdl
+UART Tx module.
+
+roms/rom_pkg.vhdl
+Package containing the declarations for the memories used by the small and
+medium ZPU.
+
+roms/dmips_bram.vhdl
+A memory that maps to Xilinx BRAMs and contains the Dhrystone Benchmark,
+Version 2.1 (Language: C). This memory can be connected to the ZPU for
+simulation or hardware implementations. The code assumes a 50 MHz clock to
+compute the benchmark. The minimum size for this block should be 32 kB.
+
+roms/dmips_dbram.vhdl
+Same as roms/dmips_bram.vhdl, but dual ported. Suitable for the small ZPU.
+
+roms/hello_bram.vhdl
+A memory that maps to Xilinx BRAMs and contains a simple "Hello World!"
+program (C compiled). This memory can be connected to the ZPU for
+simulation or hardware implementations. The minimum size for this block
+should be 16 kB.
+
+roms/hello_dbram.vhdl
+Same as roms/hello_bram.vhdl, but dual ported. Suitable for the small ZPU.
+helpers/zpu_med1.vhdl
+This is a helper that connects a ZPU to its memory and the PHI I/O space.
+
+testbenches/dmips_med1_tb.vhdl
+A simple testbench to simulate the medium ZPU (behavior).
+
+testbenches/small1_tb.vhdl
+A simple testbench to simulate the small ZPU (behavior).
+
+fpga/dmips_med1.vhdl
+A wrapper to implement the medium ZPU in an FPGA. This example was designed
+for a GR-XC3S board from Pender, but should be easily adapted to other
+boards.
+
+fpga/hello_med1.vhdl
+Same as fpga/dmips_med1.vhdl, but uses less memory, enough for the "Hello
+Wold!" test.
+
+fpga/dmips_small1.vhdl
+Same as fpga/dmips_med1.vhdl, but for the small ZPU.
+
+fpga/hello_small1.vhdl
+Same as fpga/hello_med1.vhdl, but for the small ZPU.
+
+
+ZPU library?
+------------
+
+The following files are part of a library I called ZPU:
+
+zpu_pkg.vhdl, zpu_medium.vhdl, zpu_small.vhdl, txt_util.vhdl, timer.vhdl,
+rx_unit.vhdl, tx_unit.vhdl, br_gen.vhdl, phi_io.vhdl and trace.vhdl.
+
+You should group them inside a library called zpu. This procedure is
+tool-chain dependent. In the ISE tool you must add a library and them move
+these files to the library.
+
+If you don't know how to do it with your tools you can just replace all the:
+
+library zpu;
+use zpu.xxxxxx.all;
+
+code by:
+
+library work;
+use work.xxxxxx.all;
+
+
+Which files are needed for simulation?
+--------------------------------------
+
+You need all the files that compose the zpu library plus:
+1) A memory containing a program, i.e.:
+roms/rom_pkg.vhdl and roms/dmips_bram.vhdl
+2) A testbench (including the memory and I/O interconnections):
+aux/zpu_med1.vhdl and testbenches/dmips_med1_tb.vhdl
+3) Be careful to include only the medium or the small ZPU. Also note that
+the small uses dual port BRAMs, i.e. roms/dmips_dbram.vhdl The testbench
+for the small ZPU is small1_tb.vhdl
+
+
+Which files are needed for synthesis?
+-------------------------------------
+
+This is similar to simulation, but:
+1) You should avoid trace.vhdl.
+2) The top level should connect to the FPGA pins, replace dmips_med1_tb.vhdl
+by fpga/dmips_med1.vhdl or fpga/hello_med1.vhdl
+
+
+What resources are needed in the FPGA?
+--------------------------------------
+
+The DMIPS benchmarks needs aprox (Xilinx Spartan 3):
+
+Medium ZPU:
+
+Flip Flops: 498
+LUTs: 1877
+Slices: 1032
+BRAMs: 16
+Multipliers: 3
+
+The hello world example needs less memory:
+
+Flip Flops: 496
+LUTs: 1871
+Slices: 1027
+BRAMs: 8
+Multipliers: 3
+
+
+Small ZPU:
+
+Flip Flops: 373
+LUTs: 706
+Slices: 434
+BRAMs: 16
+
+The hello world example needs less memory:
+
+Flip Flops: 371
+LUTs: 701
+Slices: 431
+BRAMs: 8
+
+
+The board should contain an RS-232 transceiver. A push button (active when
+pressed) is also used, for reset.
+
+
+Ok, I synthetized it and put in the FPGA, what now?
+---------------------------------------------------
+
+Connect the RS-232 board output to a terminal (a PC). Setup the terminal for
+115200 8N1 reception and press the reset push button. You should get the
+program output. You can change the baudrate in the toplevel VHDL.
+
+
+Please tell me if you succeed or failed!
+Enjoy, Salvador E. Tropea
+
diff --git a/zpu/hdl/zealot/BSD b/zpu/hdl/zealot/BSD
new file mode 100644
index 0000000..cca2a5c
--- /dev/null
+++ b/zpu/hdl/zealot/BSD
@@ -0,0 +1,20 @@
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions
+are met:
+
+1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
diff --git a/zpu/hdl/zealot/GPL_V2 b/zpu/hdl/zealot/GPL_V2
new file mode 100644
index 0000000..21b9363
--- /dev/null
+++ b/zpu/hdl/zealot/GPL_V2
@@ -0,0 +1,341 @@
+ GNU GENERAL PUBLIC LICENSE
+ Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.
+ 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+ Preamble
+
+ The licenses for most software are designed to take away your
+freedom to share and change it. By contrast, the GNU General Public
+License is intended to guarantee your freedom to share and change free
+software--to make sure the software is free for all its users. This
+General Public License applies to most of the Free Software
+Foundation's software and to any other program whose authors commit to
+using it. (Some other Free Software Foundation software is covered by
+the GNU Library General Public License instead.) You can apply it to
+your programs, too.
+
+ When we speak of free software, we are referring to freedom, not
+price. Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
+this service if you wish), that you receive source code or can get it
+if you want it, that you can change the software or use pieces of it
+in new free programs; and that you know you can do these things.
+
+ To protect your rights, we need to make restrictions that forbid
+anyone to deny you these rights or to ask you to surrender the rights.
+These restrictions translate to certain responsibilities for you if you
+distribute copies of the software, or if you modify it.
+
+ For example, if you distribute copies of such a program, whether
+gratis or for a fee, you must give the recipients all the rights that
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+ We protect your rights with two steps: (1) copyright the software, and
+(2) offer you this license which gives you legal permission to copy,
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+
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+that everyone understands that there is no warranty for this free
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+
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+ GNU GENERAL PUBLIC LICENSE
+ TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
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+the Program or works based on it.
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+license would not permit royalty-free redistribution of the Program by
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+to distribute software through any other system and a licensee cannot
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+
+This section is intended to make thoroughly clear what is believed to
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+
+ 8. If the distribution and/or use of the Program is restricted in
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+original copyright holder who places the Program under this License
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+
+ 9. The Free Software Foundation may publish revised and/or new versions
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+be similar in spirit to the present version, but may differ in detail to
+address new problems or concerns.
+
+Each version is given a distinguishing version number. If the Program
+specifies a version number of this License which applies to it and "any
+later version", you have the option of following the terms and conditions
+either of that version or of any later version published by the Free
+Software Foundation. If the Program does not specify a version number of
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+Foundation.
+
+ 10. If you wish to incorporate parts of the Program into other free
+programs whose distribution conditions are different, write to the author
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+
+ 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
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+PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGES.
+
+ END OF TERMS AND CONDITIONS
+
+
+ How to Apply These Terms to Your New Programs
+
+ If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
+ To do so, attach the following notices to the program. It is safest
+to attach them to the start of each source file to most effectively
+convey the exclusion of warranty; and each file should have at least
+the "copyright" line and a pointer to where the full notice is found.
+
+ <one line to give the program's name and a brief idea of what it does.>
+ Copyright (C) 19yy <name of author>
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+
+
+Also add information on how to contact you by electronic and paper mail.
+
+If the program is interactive, make it output a short notice like this
+when it starts in an interactive mode:
+
+ Gnomovision version 69, Copyright (C) 19yy name of author
+ Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+ This is free software, and you are welcome to redistribute it
+ under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License. Of course, the commands you use may
+be called something other than `show w' and `show c'; they could even be
+mouse-clicks or menu items--whatever suits your program.
+
+You should also get your employer (if you work as a programmer) or your
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+
+ Yoyodyne, Inc., hereby disclaims all copyright interest in the program
+ `Gnomovision' (which makes passes at compilers) written by James Hacker.
+
+ <signature of Ty Coon>, 1 April 1989
+ Ty Coon, President of Vice
+
+This General Public License does not permit incorporating your program into
+proprietary programs. If your program is a subroutine library, you may
+consider it more useful to permit linking proprietary applications with the
+library. If this is what you want to do, use the GNU Library General
+Public License instead of this License.
diff --git a/zpu/hdl/zealot/devices/br_gen.vhdl b/zpu/hdl/zealot/devices/br_gen.vhdl
new file mode 100644
index 0000000..d14440e
--- /dev/null
+++ b/zpu/hdl/zealot/devices/br_gen.vhdl
@@ -0,0 +1,91 @@
+------------------------------------------------------------------------------
+---- ----
+---- RS-232 baudrate generator ----
+---- ----
+---- http://www.opencores.org/ ----
+---- ----
+---- Description: ----
+---- This counter is a parametrizable clock divider. The count value is ----
+---- the generic parameter COUNT. It has a chip enable ce_i input. ----
+---- (will count only if CE is high). ----
+---- When it overflows, will emit a pulse on o_o. ----
+---- ----
+---- To Do: ----
+---- - ----
+---- ----
+---- Author: ----
+---- - Philippe Carton, philippe.carton2 libertysurf.fr ----
+---- - Juan Pablo Daniel Borgna, jpdborgna gmail.com ----
+---- - Salvador E. Tropea, salvador inti.gob.ar ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Copyright (c) 2001-2003 Philippe Carton ----
+---- Copyright (c) 2005 Juan Pablo Daniel Borgna ----
+---- Copyright (c) 2005-2008 Salvador E. Tropea ----
+---- Copyright (c) 2005-2008 Instituto Nacional de Tecnología Industrial ----
+---- ----
+---- Distributed under the GPL license ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Design unit: BRGen(Behaviour) (Entity and architecture) ----
+---- File name: br_gen.vhdl ----
+---- Note: None ----
+---- Limitations: None known ----
+---- Errors: None known ----
+---- Library: zpu ----
+---- Dependencies: IEEE.std_logic_1164 ----
+---- Target FPGA: Spartan ----
+---- Language: VHDL ----
+---- Wishbone: No ----
+---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
+---- Text editor: SETEdit 0.5.x ----
+---- ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity BRGen is
+ generic(
+ COUNT : integer range 0 to 65535);-- Count revolution
+ port (
+ clk_i : in std_logic; -- Clock
+ reset_i : in std_logic; -- Reset input
+ ce_i : in std_logic; -- Chip Enable
+ o_o : out std_logic); -- Output
+end entity BRGen;
+
+architecture Behaviour of BRGen is
+
+begin
+ CountGen:
+ if COUNT/=1 generate
+ Counter:
+ process (clk_i)
+ variable cnt : integer range 0 to COUNT-1;
+ begin
+ if rising_edge(clk_i) then
+ o_o <= '0';
+ if reset_i='1' then
+ cnt:=COUNT-1;
+ elsif ce_i='1' then
+ if cnt=0 then
+ o_o <= '1';
+ cnt:=COUNT-1;
+ else
+ cnt:=cnt-1;
+ end if; -- cnt/=0
+ end if; -- ce_i='1'
+ end if; -- rising_edge(clk_i)
+ end process Counter;
+ end generate CountGen;
+
+ CountWire:
+ if COUNT=1 generate
+ o_o <= '0' when reset_i='1' else ce_i;
+ end generate CountWire;
+end architecture Behaviour; -- Entity: BRGen
+
diff --git a/zpu/hdl/zealot/devices/gpio.vhdl b/zpu/hdl/zealot/devices/gpio.vhdl
new file mode 100644
index 0000000..fc66bde
--- /dev/null
+++ b/zpu/hdl/zealot/devices/gpio.vhdl
@@ -0,0 +1,107 @@
+--
+-- this module desribes a simple GPIO interface
+--
+-- data on port_in is synhronized to clk_i and can be read at
+-- address 0
+--
+-- any write to address 0 is mapped to port_out
+--
+-- at address 1 is a direction register (port_dir)
+-- initialized with '1's, what mean direction = in
+-- this register is useful for bidirectional pins, e.g. headers
+--
+--
+-- some examples:
+--
+-- to connect 4 buttons:
+-- port_in( 3 downto 0) <= gpio_button;
+--
+--
+-- to connect 8 LEDs:
+-- gpio_led <= port_out(7 downto 0);
+--
+--
+-- to connect 2 bidirectional header pins:
+-- port_in(8) <= gpio_pin(0);
+-- gpio_pin(0) <= port_out(8) when port_dir(8) = '0' else 'Z';
+--
+-- port_in(9) <= gpio_pin(1);
+-- gpio_pin(1) <= port_out(9) when port_dir(9) = '0' else 'Z';
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+entity gpio is
+ port(
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ --
+ we_i : in std_logic;
+ data_i : in unsigned(31 downto 0);
+ addr_i : in unsigned( 0 downto 0);
+ data_o : out unsigned(31 downto 0);
+ --
+ port_in : in std_logic_vector(31 downto 0);
+ port_out : out std_logic_vector(31 downto 0);
+ port_dir : out std_logic_vector(31 downto 0)
+ );
+end entity gpio;
+
+
+architecture rtl of gpio is
+
+ signal port_in_reg : std_logic_vector(31 downto 0);
+ signal port_in_sync : std_logic_vector(31 downto 0);
+ --
+ signal direction : std_logic_vector(31 downto 0) := (others => '1');
+
+begin
+
+ process
+ begin
+ wait until rising_edge( clk_i);
+
+ -- synchronize all inputs with two registers
+ -- to avoid metastability
+ port_in_reg <= port_in;
+ port_in_sync <= port_in_reg;
+
+ -- write access to gpio
+ if we_i = '1' then
+ -- data
+ if addr_i = "0" then
+ port_out <= std_logic_vector( data_i);
+ end if;
+ -- direction
+ if addr_i = "1" then
+ direction <= std_logic_vector( data_i);
+ end if;
+ end if;
+
+ -- read access to gpio
+ -- data
+ if addr_i = "0" then
+ data_o <= unsigned( port_in_sync);
+ end if;
+ -- direction
+ if addr_i = "1" then
+ data_o <= unsigned( direction);
+ end if;
+
+ -- outputs
+ port_dir <= direction;
+
+ -- sync reset
+ if reset_i = '1' then
+ direction <= (others => '1');
+ port_in_reg <= (others => '0');
+ port_in_sync <= (others => '0');
+ end if;
+
+ end process;
+
+
+end architecture rtl;
diff --git a/zpu/hdl/zealot/devices/phi_io.vhdl b/zpu/hdl/zealot/devices/phi_io.vhdl
new file mode 100644
index 0000000..6e40d1d
--- /dev/null
+++ b/zpu/hdl/zealot/devices/phi_io.vhdl
@@ -0,0 +1,257 @@
+------------------------------------------------------------------------------
+---- ----
+---- ZPU Phi I/O ----
+---- ----
+---- http://www.opencores.org/ ----
+---- ----
+---- Description: ----
+---- ZPU is a 32 bits small stack cpu. This is the minimum I/O devices ----
+---- assumed by the libc. They are a timer and an UART.@p ----
+---- Important! this is currently a simulation only model, no UART ----
+---- provided and it unconditionally generates a log. ----
+---- Important! not all peripherals implemented! ----
+---- Important! The enable signals assumes this is mapped @ 0x80A00xx. ----
+---- ----
+---- To Do: ----
+---- - ----
+---- ----
+---- Author: ----
+---- - Øyvind Harboe, oyvind.harboe zylin.com ----
+---- - Salvador E. Tropea, salvador inti.gob.ar ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
+---- ----
+---- Distributed under the BSD license ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Design unit: ZPUPhiIO(Behave) (Entity and architecture) ----
+---- File name: phi_io.vhdl ----
+---- Note: None ----
+---- Limitations: Only for simulation. ----
+---- Errors: None known ----
+---- Library: zpu ----
+---- Dependencies: IEEE.std_logic_1164 ----
+---- IEEE.numeric_std ----
+---- std.textio ----
+---- zpu.zpupkg ----
+---- zpu.txt_util ----
+---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
+---- Language: VHDL ----
+---- Wishbone: No ----
+---- Synthesis tools: N/A ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
+---- Text editor: SETEdit 0.5.x ----
+---- ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use std.textio.all;
+
+library zpu;
+use zpu.zpupkg.timer;
+use zpu.zpupkg.gpio;
+use zpu.UART.all;
+use zpu.txt_util.all;
+
+entity ZPUPhiIO is
+ generic(
+ BRDIVISOR : positive:=1; -- Baud rate divisor i.e. br_clk/9600/4
+ ENA_LOG : boolean:=true; -- Enable log
+ LOG_FILE : string:="log.txt"); -- Name for the log file
+ port(
+ clk_i : in std_logic; -- System Clock
+ reset_i : in std_logic; -- Synchronous Reset
+ busy_o : out std_logic; -- I/O is busy
+ we_i : in std_logic; -- Write Enable
+ re_i : in std_logic; -- Read Enable
+ data_i : in unsigned(31 downto 0);
+ data_o : out unsigned(31 downto 0);
+ addr_i : in unsigned(2 downto 0); -- Address bits 4-2
+ --
+ rs232_rx_i : in std_logic; -- UART Rx input
+ rs232_tx_o : out std_logic; -- UART Tx output
+ br_clk_i : in std_logic; -- UART base clock (enable)
+ --
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+end entity ZPUPhiIO;
+
+
+architecture Behave of ZPUPhiIO is
+ constant LOW_BITS : unsigned(1 downto 0):=(others=>'0');
+ constant TX_FULL : std_logic:='0';
+ constant RX_EMPTY : std_logic:='1';
+
+ -- "000" 0x00 is CPU enable ... useful?
+ constant IO_DATA : unsigned(2 downto 0):="001"; -- 0x04
+ constant IO_DIR : unsigned(2 downto 0):="010"; -- 0x08
+ constant UART_TX : unsigned(2 downto 0):="011"; -- 0x0C
+ constant UART_RX : unsigned(2 downto 0):="100"; -- 0x10
+ constant CNT_1 : unsigned(2 downto 0):="101"; -- 0x14
+ constant CNT_2 : unsigned(2 downto 0):="110"; -- 0x18
+ -- "111" 0x1C Unused
+ -- Unimplemented: Interrupt control and timer (not counter ...?)
+
+ signal timer_read : unsigned(31 downto 0);
+ signal timer_we : std_logic;
+ signal is_timer : std_logic;
+
+ -- UART
+ -- Rx
+ signal rx_br : std_logic; -- Rx timing
+ signal uart_read : std_logic; -- ZPU read the value
+ signal rx_avail : std_logic; -- Rx data available
+ signal rx_data : std_logic_vector(7 downto 0); -- Rx data
+ -- Tx
+ signal tx_br : std_logic; -- Tx timing
+ signal uart_write : std_logic; -- ZPU is writing
+ signal tx_busy : std_logic; -- Tx can't get a new value
+
+ -- GPIO
+ signal gpio_we : std_logic;
+ signal is_gpio : std_logic;
+ signal gpio_read : unsigned(31 downto 0);
+
+ file l_file : text open write_mode is LOG_FILE;
+
+begin
+ -----------
+ -- Timer --
+ -----------
+ timerinst: Timer
+ port map(
+ clk_i => clk_i, reset_i => reset_i, we_i => timer_we,
+ data_i => data_i, addr_i => addr_i(1 downto 1),
+ data_o => timer_read);
+
+ busy_o <= we_i or re_i;
+ is_timer <= '1' when to_01(addr_i)=CNT_1 or to_01(addr_i)=CNT_2 else '0'; -- 0x80A0014/8
+ timer_we <= we_i and is_timer;
+
+ ----------
+ -- UART --
+ ----------
+ -- Rx section
+ rx_core : RxUnit
+ port map(
+ clk_i => clk_i, reset_i => reset_i, enable_i => rx_br,
+ read_i => uart_read, rxd_i => rs232_rx_i, rxav_o => rx_avail,
+ datao_o => rx_data);
+ uart_read <= '1' when re_i='1' and addr_i=UART_RX else '0';
+
+ -- Tx section
+ tx_core : TxUnit
+ port map(
+ clk_i => clk_i, reset_i => reset_i, enable_i => tx_br,
+ load_i => uart_write, txd_o => rs232_tx_o, busy_o => tx_busy,
+ datai_i => std_logic_vector(data_i(7 downto 0)));
+ uart_write <= '1' when we_i='1' and addr_i=UART_TX else '0';
+
+ -- Rx timing
+ rx_timer : BRGen
+ generic map(COUNT => BRDIVISOR)
+ port map(
+ clk_i => clk_i, reset_i => reset_i, ce_i => br_clk_i, o_o => rx_br);
+
+ -- Tx timing
+ tx_timer : BRGen -- 4 Divider for Tx
+ generic map(COUNT => 4)
+ port map(
+ clk_i => clk_i, reset_i => reset_i, ce_i => rx_br, o_o => tx_br);
+
+ ----------
+ -- GPIO --
+ ----------
+ gpio_i0: gpio
+ port map(
+ clk_i => clk_i, -- : in std_logic;
+ reset_i => reset_i, -- : in std_logic;
+ --
+ we_i => gpio_we, -- : in std_logic;
+ data_i => data_i, -- : in unsigned(31 downto 0);
+ addr_i => addr_i(1 downto 1), -- : in unsigned( 0 downto 0);
+ data_o => gpio_read, -- : out unsigned(31 downto 0);
+ --
+ port_in => gpio_in, -- : std_logic_vector(31 downto 0);
+ port_out => gpio_out, -- : std_logic_vector(31 downto 0);
+ port_dir => gpio_dir -- : std_logic_vector(31 downto 0);
+ );
+ is_gpio <= '1' when to_01(addr_i) = IO_DATA or to_01(addr_i) = IO_DIR else '0'; -- 0x80A0004/8
+ gpio_we <= we_i and is_gpio;
+
+
+ do_io:
+ process(clk_i)
+ --synopsys translate off
+ variable line_out : line := new string'("");
+ variable char : character;
+ --synopsys translate on
+ begin
+ if rising_edge(clk_i) then
+ if reset_i/='1' then
+ --synopsys translate off
+ if we_i='1' then
+ if addr_i=UART_TX and ENA_LOG then -- 0x80a000c
+ -- Write to UART
+ print("- Write to UART Tx: 0x" &hstr(data_i)&" ("&
+ character'val(to_integer(data_i) mod 256)&")");
+ char := character'val(to_integer(data_i));
+ if char = lf then
+ std.textio.writeline(l_file, line_out);
+ else
+ std.textio.write(line_out, char);
+ end if;
+ elsif is_gpio = '1' and ENA_LOG then
+ print("- Write GPIO: 0x" & hstr(data_i));
+ elsif is_timer='1' and ENA_LOG then
+ print("- Write to TIMER: 0x" & hstr(data_i));
+ else
+ --print(l_file,character'val(to_integer(data_i)));
+ report "Illegal IO data_i=0x"&hstr(data_i)&" @0x"&
+ hstr(x"80a00"&"000"&addr_i&"00") severity warning;
+ end if;
+ end if;
+ --synopsys translate on
+ data_o <= (others => '0');
+ if re_i='1' then
+ if is_gpio = '1' then
+ if ENA_LOG then
+ print("- Read GPIO: 0x" & hstr(gpio_read));
+ end if;
+ data_o <= gpio_read;
+ elsif addr_i=UART_TX then
+ if ENA_LOG then
+ print("- Read UART Tx");
+ end if;
+ data_o(8) <= not(tx_busy); -- output fifo not full
+ elsif addr_i=UART_RX then
+ if ENA_LOG then
+ print("- Read UART Rx");
+ end if;
+ data_o(8) <= rx_avail; -- receiver not empty
+ data_o(7 downto 0) <= unsigned(rx_data);
+ elsif is_timer='1' then
+ if ENA_LOG then
+ print("- Read TIMER: 0x" & hstr(timer_read));
+ end if;
+ data_o <= timer_read;
+ else
+ report "Illegal IO data_o @0x"&
+ hstr(x"80a00"&"000"&addr_i&"00") severity warning;
+ end if;
+ end if; -- re_i='1'
+ end if; -- reset_i/='1'
+ end if; -- rising_edge(clk_i)
+ end process do_io;
+end Behave;
+
diff --git a/zpu/hdl/zealot/devices/rx_unit.vhdl b/zpu/hdl/zealot/devices/rx_unit.vhdl
new file mode 100644
index 0000000..e9b3251
--- /dev/null
+++ b/zpu/hdl/zealot/devices/rx_unit.vhdl
@@ -0,0 +1,108 @@
+------------------------------------------------------------------------------
+---- ----
+---- RS-232 simple Rx module ----
+---- ----
+---- http://www.opencores.org/ ----
+---- ----
+---- Description: ----
+---- Implements a simple 8N1 rx module for RS-232. ----
+---- ----
+---- To Do: ----
+---- - ----
+---- ----
+---- Author: ----
+---- - Philippe Carton, philippe.carton2 libertysurf.fr ----
+---- - Juan Pablo Daniel Borgna, jpdborgna gmail.com ----
+---- - Salvador E. Tropea, salvador inti.gob.ar ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Copyright (c) 2001-2003 Philippe Carton ----
+---- Copyright (c) 2005 Juan Pablo Daniel Borgna ----
+---- Copyright (c) 2005-2008 Salvador E. Tropea ----
+---- Copyright (c) 2005-2008 Instituto Nacional de Tecnología Industrial ----
+---- ----
+---- Distributed under the GPL license ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Design unit: RxUnit(Behaviour) (Entity and architecture) ----
+---- File name: rx_unit.vhdl ----
+---- Note: None ----
+---- Limitations: None known ----
+---- Errors: None known ----
+---- Library: zpu ----
+---- Dependencies: IEEE.std_logic_1164 ----
+---- Target FPGA: Spartan ----
+---- Language: VHDL ----
+---- Wishbone: No ----
+---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
+---- Text editor: SETEdit 0.5.x ----
+---- ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity RxUnit is
+ port(
+ clk_i : in std_logic; -- System clock signal
+ reset_i : in std_logic; -- Reset input (sync)
+ enable_i : in std_logic; -- Enable input (rate*4)
+ read_i : in std_logic; -- Received Byte Read
+ rxd_i : in std_logic; -- RS-232 data input
+ rxav_o : out std_logic; -- Byte available
+ datao_o : out std_logic_vector(7 downto 0)); -- Byte received
+end entity RxUnit;
+
+architecture Behaviour of RxUnit is
+ signal r_r : std_logic_vector(7 downto 0); -- Receive register
+ signal bavail_r : std_logic:='0'; -- Byte received
+begin
+ rxav_o <= bavail_r;
+ -- Rx Process
+ RxProc:
+ process (clk_i)
+ variable bitpos : integer range 0 to 10; -- Position of the bit in the frame
+ variable samplecnt : integer range 0 to 3; -- Count from 0 to 3 in each bit
+ begin
+ if rising_edge(clk_i) then
+ if reset_i='1' then
+ bavail_r <= '0';
+ bitpos:=0;
+ else -- reset_i='0'
+ if read_i='1' then
+ bavail_r <= '0';
+ end if;
+ if enable_i='1' then
+ case bitpos is
+ when 0 => -- idle
+ bavail_r <= '0';
+ if rxd_i='0' then -- Start Bit
+ samplecnt:=0;
+ bitpos:=1;
+ end if;
+ when 10 => -- Stop Bit
+ bitpos:=0; -- next is idle
+ bavail_r <= '1'; -- Indicate byte received
+ datao_o <= r_r; -- Store received byte
+ when others =>
+ if samplecnt=1 and bitpos>=2 then -- Sample RxD on 1
+ r_r(bitpos-2) <= rxd_i; -- Deserialisation
+ end if;
+ if samplecnt=3 then -- Increment BitPos on 3
+ bitpos:=bitpos+1;
+ end if;
+ end case;
+ if samplecnt=3 then
+ samplecnt:=0;
+ else
+ samplecnt:=samplecnt+1;
+ end if;
+ end if; -- enable_i='1'
+ end if; -- reset_i='0'
+ end if; -- rising_edge(clk_i)
+ end process RxProc;
+end architecture Behaviour;
+
diff --git a/zpu/hdl/zealot/devices/timer.vhdl b/zpu/hdl/zealot/devices/timer.vhdl
new file mode 100644
index 0000000..389868c
--- /dev/null
+++ b/zpu/hdl/zealot/devices/timer.vhdl
@@ -0,0 +1,91 @@
+------------------------------------------------------------------------------
+---- ----
+---- 64 bits clock counter ----
+---- ----
+---- http://www.opencores.org/ ----
+---- ----
+---- Description: ----
+---- This is a peripheral used by the PHI I/O layout. It just counts the ----
+---- elapsed number of clocks. ----
+---- ----
+---- To Do: ----
+---- - ----
+---- ----
+---- Author: ----
+---- - Øyvind Harboe, oyvind.harboe zylin.com ----
+---- - Salvador E. Tropea, salvador inti.gob.ar ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
+---- ----
+---- Distributed under the BSD license ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Design unit: Timer(Behave) (Entity and architecture) ----
+---- File name: timer.vhdl ----
+---- Note: None ----
+---- Limitations: None known ----
+---- Errors: None known ----
+---- Library: zpu ----
+---- Dependencies: IEEE.std_logic_1164 ----
+---- IEEE.numeric_std ----
+---- zpu.zpupkg ----
+---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
+---- Language: VHDL ----
+---- Wishbone: No ----
+---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
+---- Text editor: SETEdit 0.5.x ----
+---- ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity Timer is
+ port(
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ we_i : in std_logic;
+ data_i : in unsigned(31 downto 0);
+ addr_i : in unsigned(0 downto 0);
+ data_o : out unsigned(31 downto 0));
+end entity Timer;
+
+architecture Behave of Timer is
+ signal sample : std_logic;
+ signal reset : std_logic;
+
+ signal cnt : unsigned(63 downto 0);
+ signal cnt_smp : unsigned(63 downto 0);
+begin
+ reset <= '1' when (we_i='1' and data_i(0)='1') else '0';
+ sample <= '1' when (we_i='1' and data_i(1)='1') else '0';
+
+ -- Carry generation
+ do_timer:
+ process (clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if reset_i='1' or reset='1' then
+ cnt <= (others => '0');
+ cnt_smp <= (others => '0');
+ else
+ cnt <= cnt+1;
+ if sample='1' then
+ -- report "sampling" severity failure;
+ cnt_smp <= cnt;
+ end if;
+ end if; -- else reset_i='1'
+ end if; -- rising_edge(clk_i)
+ end process do_timer;
+
+ data_o <= cnt_smp(31 downto 0) when to_01(addr_i)="0" else
+ cnt_smp(63 downto 32);
+end architecture Behave; -- Entity: Timer
+
diff --git a/zpu/hdl/zealot/devices/trace.vhdl b/zpu/hdl/zealot/devices/trace.vhdl
new file mode 100644
index 0000000..83d3782
--- /dev/null
+++ b/zpu/hdl/zealot/devices/trace.vhdl
@@ -0,0 +1,258 @@
+------------------------------------------------------------------------------
+---- ----
+---- ZPU Trace Module ----
+---- ----
+---- http://www.opencores.org/ ----
+---- ----
+---- Description: ----
+---- ZPU is a 32 bits small stack cpu. This is a module to log an ----
+---- execution trace. ----
+---- ----
+---- To Do: ----
+---- - ----
+---- ----
+---- Author: ----
+---- - Øyvind Harboe, oyvind.harboe zylin.com ----
+---- - Salvador E. Tropea, salvador inti.gob.ar ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
+---- ----
+---- Distributed under the BSD license ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Design unit: Trace(Behave) (Entity and architecture) ----
+---- File name: trace.vhdl ----
+---- Note: None ----
+---- Limitations: None known ----
+---- Errors: None known ----
+---- Library: zpu ----
+---- Dependencies: IEEE.std_logic_1164 ----
+---- IEEE.numeric_std ----
+---- std.textio ----
+---- zpu.zpupkg ----
+---- zpu.txt_util ----
+---- Target FPGA: N/A ----
+---- Language: VHDL ----
+---- Wishbone: No ----
+---- Synthesis tools: N/A ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
+---- Text editor: SETEdit 0.5.x ----
+---- ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use std.textio.all;
+
+library zpu;
+use zpu.zpupkg.all;
+use zpu.txt_util.all;
+
+entity Trace is
+ generic(
+ LOG_FILE : string:="trace.txt"; -- Name of the trace file
+ ADDR_W : integer:=16; -- Address width
+ WORD_SIZE : integer:=32); -- 16/32
+ port(
+ clk_i : in std_logic;
+ dbg_i : in zpu_dbgo_t;
+ stop_i : in std_logic;
+ busy_i : in std_logic
+ );
+end entity Trace;
+
+architecture Behave of Trace is
+ file l_file : text open write_mode is LOG_FILE;
+ signal counter : unsigned(63 downto 0);
+begin
+ -- write data and control information to a file
+ receive_data:
+ process
+ variable l : line;
+ variable stk_min : unsigned(31 downto 0):=(others => '1');
+ variable stk_ini : unsigned(31 downto 0);
+ variable first : boolean:=true;
+ variable sp_off : unsigned(4 downto 0);
+ variable idim : boolean:=false;
+ variable im_val : unsigned(31 downto 0):=(others => '0');
+ begin
+ counter <= to_unsigned(1,64);
+ -- print header for the logfile
+ print(l_file,"#PC Opcode SP A=[SP] B=[SP+1] Clk Counter Assembler");
+ print(l_file,"#---------------------------------------------------------------------------");
+ print(l_file," ");
+
+ wait until clk_i='1';
+ wait until clk_i='0';
+
+ while true loop
+ counter <= counter+1;
+ if dbg_i.b_inst='1' then
+ write(l, "0x"&hstr(dbg_i.pc(ADDR_W-1 downto 0))&
+ " 0x"&hstr(dbg_i.opcode)&
+ " 0x"&hstr(dbg_i.sp)&
+ " 0x"&hstr(dbg_i.stk_a)&
+ " 0x"&hstr(dbg_i.stk_b)&
+ " 0x"&hstr(counter)&" ");
+ --------------------------
+ -- Instruction Decoder --
+ --------------------------
+ sp_off(4):=not dbg_i.opcode(4);
+ sp_off(3 downto 0):=dbg_i.opcode(3 downto 0);
+ if dbg_i.opcode(7 downto 7)=OPCODE_IM then
+ if idim then
+ im_val(31 downto 7):=im_val(24 downto 0);
+ im_val(6 downto 0):=dbg_i.opcode(6 downto 0);
+ else
+ im_val:=unsigned(resize(signed(dbg_i.opcode(6 downto 0)),32));
+ end if;
+ idim:=true;
+ write(l,"im 0x"&hstr(dbg_i.opcode(6 downto 0))&" ; 0x"&hstr(im_val));
+ elsif dbg_i.opcode(7 downto 5)=OPCODE_STORESP then
+ if sp_off=0 then
+ write(l,string'("storesp 0 ; pop"));
+ elsif sp_off=1 then
+ write(l,string'("storesp 4 ; 1*4 = popdown"));
+ else
+ write(l,"storesp "&integer'image(to_integer(sp_off)*4)&" ; "&
+ integer'image(to_integer(sp_off))&"*4");
+ end if;
+ elsif dbg_i.opcode(7 downto 5)=OPCODE_LOADSP then
+ if sp_off=0 then
+ write(l,string'("loadsp 0 ; dup"));
+ elsif sp_off=1 then
+ write(l,string'("loadsp 4 ; 1*4 = dupstkb"));
+ else
+ write(l,"loadsp "&integer'image(to_integer(sp_off)*4)&" ; "&
+ integer'image(to_integer(sp_off))&"*4");
+ end if;
+ elsif dbg_i.opcode(7 downto 5)=OPCODE_EMULATE then
+ if dbg_i.opcode(5 downto 0)=OPCODE_EQ then
+ write(l,string'("eq"));
+ elsif dbg_i.opcode(5 downto 0)=OPCODE_LOADB then
+ write(l,string'("loadb"));
+ elsif dbg_i.opcode(5 downto 0)=OPCODE_NEQBRANCH then
+ write(l,string'("neqbranch"));
+ elsif dbg_i.opcode(5 downto 0)=OPCODE_PUSHSPADD then
+ write(l,string'("pushspadd"));
+ elsif dbg_i.opcode(5 downto 0)=OPCODE_LESSTHAN then
+ write(l,string'("lessthan"));
+ elsif dbg_i.opcode(5 downto 0)=OPCODE_ULESSTHAN then
+ write(l,string'("ulessthan"));
+ elsif dbg_i.opcode(5 downto 0)=OPCODE_MULT then
+ write(l,string'("mult"));
+ elsif dbg_i.opcode(5 downto 0)=OPCODE_STOREB then
+ write(l,string'("storeb"));
+ elsif dbg_i.opcode(5 downto 0)=OPCODE_CALLPCREL then
+ write(l,string'("callpcrel"));
+ elsif dbg_i.opcode(5 downto 0)=OPCODE_SUB then
+ write(l,string'("sub"));
+ elsif dbg_i.opcode(5 downto 0)=OPCODE_LESSTHANOREQUAL then
+ write(l,string'("lessthanorequal"));
+ elsif dbg_i.opcode(5 downto 0)=OPCODE_ULESSTHANOREQUAL then
+ write(l,string'("ulessthanorequal"));
+ elsif dbg_i.opcode(5 downto 0)=OPCODE_CALL then
+ write(l,string'("call"));
+ elsif dbg_i.opcode(5 downto 0)=OPCODE_POPPCREL then
+ write(l,string'("poppcrel"));
+ elsif dbg_i.opcode(5 downto 0)=OPCODE_LSHIFTRIGHT then
+ write(l,string'("lshiftright"));
+ elsif dbg_i.opcode(5 downto 0)=OPCODE_LOADH then
+ write(l,string'("loadh"));
+ elsif dbg_i.opcode(5 downto 0)=OPCODE_STOREH then
+ write(l,string'("storeh"));
+ elsif dbg_i.opcode(5 downto 0)=OPCODE_ASHIFTLEFT then
+ write(l,string'("ashiftleft"));
+ elsif dbg_i.opcode(5 downto 0)=OPCODE_ASHIFTRIGHT then
+ write(l,string'("ashiftright"));
+ elsif dbg_i.opcode(5 downto 0)=OPCODE_NEQ then
+ write(l,string'("neq"));
+ elsif dbg_i.opcode(5 downto 0)=OPCODE_NEG then
+ write(l,string'("neg"));
+ elsif dbg_i.opcode(5 downto 0)=OPCODE_XOR then
+ write(l,string'("xor"));
+ elsif dbg_i.opcode(5 downto 0)=OPCODE_DIV then
+ write(l,string'("div"));
+ elsif dbg_i.opcode(5 downto 0)=OPCODE_MOD then
+ write(l,string'("mod"));
+ elsif dbg_i.opcode(5 downto 0)=OPCODE_EQBRANCH then
+ write(l,string'("eqbranch"));
+ elsif dbg_i.opcode(5 downto 0)=OPCODE_CONFIG then
+ write(l,string'("config"));
+ elsif dbg_i.opcode(5 downto 0)=OPCODE_PUSHPC then
+ write(l,string'("pushpc"));
+ else
+ write(l,integer'image(to_integer(dbg_i.opcode(5 downto 0)))&
+ " ; invalid emulated instruction");
+ end if;
+ elsif dbg_i.opcode(7 downto 4)=OPCODE_ADDSP then
+ if sp_off=0 then
+ write(l,string'("addsp 0 ; shift"));
+ elsif sp_off=1 then
+ write(l,string'("addsp 4 ; 1*4 = addtop"));
+ else
+ write(l,"addsp "&integer'image(to_integer(sp_off)*4)&" ; "&
+ integer'image(to_integer(sp_off))&"*4");
+ end if;
+ else -- OPCODE_SHORT
+ case dbg_i.opcode(3 downto 0) is
+ when OPCODE_BREAK =>
+ write(l,string'("break"));
+ when OPCODE_PUSHSP =>
+ write(l,string'("pushsp"));
+ when OPCODE_POPPC =>
+ write(l,string'("poppc"));
+ when OPCODE_ADD =>
+ write(l,string'("add"));
+ when OPCODE_OR =>
+ write(l,string'("or"));
+ when OPCODE_AND =>
+ write(l,string'("and"));
+ when OPCODE_LOAD =>
+ write(l,string'("load"));
+ when OPCODE_NOT =>
+ write(l,string'("not"));
+ when OPCODE_FLIP =>
+ write(l,string'("flip"));
+ when OPCODE_STORE =>
+ write(l,string'("store"));
+ when OPCODE_POPSP =>
+ write(l,string'("popsp"));
+ when OPCODE_NOP =>
+ write(l,string'("nop"));
+ when others =>
+ write(l,integer'image(to_integer(dbg_i.opcode))&
+ " ; invalid instruction");
+ end case;
+ end if;
+ if dbg_i.opcode(7 downto 7)/=OPCODE_IM then
+ idim:=false;
+ end if;
+ -----------------------------
+ -- End Instruction Decoder --
+ -----------------------------
+ writeline(l_file,l);
+ if dbg_i.sp<stk_min then
+ stk_min:=dbg_i.sp;
+ end if;
+ if first then
+ stk_ini:=dbg_i.sp+8;
+ first:=false;
+ end if;
+ end if;
+ wait until clk_i='0' or stop_i='1';
+ if stop_i='1' then
+ print(output,"Minimum SP: 0x"&hstr(stk_min)&" Size: 0x"&hstr(stk_ini-stk_min));
+ wait;
+ end if;
+ end loop;
+ end process receive_data;
+end Behave;
+
diff --git a/zpu/hdl/zealot/devices/tx_unit.vhdl b/zpu/hdl/zealot/devices/tx_unit.vhdl
new file mode 100644
index 0000000..73293f6
--- /dev/null
+++ b/zpu/hdl/zealot/devices/tx_unit.vhdl
@@ -0,0 +1,109 @@
+------------------------------------------------------------------------------
+---- ----
+---- RS-232 simple Tx module ----
+---- ----
+---- http://www.opencores.org/ ----
+---- ----
+---- Description: ----
+---- Implements a simple 8N1 tx module for RS-232. ----
+---- ----
+---- To Do: ----
+---- - ----
+---- ----
+---- Author: ----
+---- - Philippe Carton, philippe.carton2 libertysurf.fr ----
+---- - Juan Pablo Daniel Borgna, jpdborgna gmail.com ----
+---- - Salvador E. Tropea, salvador inti.gob.ar ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Copyright (c) 2001-2003 Philippe Carton ----
+---- Copyright (c) 2005 Juan Pablo Daniel Borgna ----
+---- Copyright (c) 2005-2008 Salvador E. Tropea ----
+---- Copyright (c) 2005-2008 Instituto Nacional de Tecnología Industrial ----
+---- ----
+---- Distributed under the GPL license ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Design unit: TxUnit(Behaviour) (Entity and architecture) ----
+---- File name: Txunit.vhdl ----
+---- Note: None ----
+---- Limitations: None known ----
+---- Errors: None known ----
+---- Library: zpu ----
+---- Dependencies: IEEE.std_logic_1164 ----
+---- zpu.UART ----
+---- Target FPGA: Spartan ----
+---- Language: VHDL ----
+---- Wishbone: No ----
+---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
+---- Text editor: SETEdit 0.5.x ----
+---- ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library zpu;
+use zpu.UART.all;
+
+entity TxUnit is
+ port (
+ clk_i : in std_logic; -- Clock signal
+ reset_i : in std_logic; -- Reset input
+ enable_i : in std_logic; -- Enable input
+ load_i : in std_logic; -- Load input
+ txd_o : out std_logic; -- RS-232 data output
+ busy_o : out std_logic; -- Tx Busy
+ datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
+end entity TxUnit;
+
+architecture Behaviour of TxUnit is
+ signal tbuff_r : std_logic_vector(7 downto 0); -- transmit buffer
+ signal t_r : std_logic_vector(7 downto 0); -- transmit register
+ signal loaded_r : std_logic:='0'; -- Buffer loaded
+ signal txd_r : std_logic:='1'; -- Tx buffer ready
+begin
+ busy_o <= load_i or loaded_r;
+ txd_o <= txd_r;
+
+ -- Tx process
+ TxProc:
+ process (clk_i)
+ variable bitpos : integer range 0 to 10; -- Bit position in the frame
+ begin
+ if rising_edge(clk_i) then
+ if reset_i='1' then
+ loaded_r <= '0';
+ bitpos:=0;
+ txd_r <= '1';
+ else -- reset_i='0'
+ if load_i='1' then
+ tbuff_r <= datai_i;
+ loaded_r <= '1';
+ end if;
+ if enable_i='1' then
+ case bitpos is
+ when 0 => -- idle or stop bit
+ txd_r <= '1';
+ if loaded_r='1' then -- start transmit. next is start bit
+ t_r <= tbuff_r;
+ loaded_r <= '0';
+ bitpos:=1;
+ end if;
+ when 1 => -- Start bit
+ txd_r <= '0';
+ bitpos:=2;
+ when others =>
+ txd_r <= t_r(bitpos-2); -- Serialisation of t_r
+ bitpos:=bitpos+1;
+ end case;
+ if bitpos=10 then -- bit8. next is stop bit
+ bitpos:=0;
+ end if;
+ end if; -- enable_i='1'
+ end if; -- reset_i='0'
+ end if; -- rising_edge(clk_i)
+ end process TxProc;
+end architecture Behaviour;
diff --git a/zpu/hdl/zealot/devices/txt_util.vhdl b/zpu/hdl/zealot/devices/txt_util.vhdl
new file mode 100644
index 0000000..862611c
--- /dev/null
+++ b/zpu/hdl/zealot/devices/txt_util.vhdl
@@ -0,0 +1,541 @@
+------------------------------------------------------------------------------
+---- ----
+---- Text Utils ----
+---- ----
+---- http://www.opencores.org/ ----
+---- ----
+---- Description: ----
+---- Utils to handle text. Used for the testbenches. ----
+---- ----
+---- To Do: ----
+---- - ----
+---- ----
+---- Author: ----
+---- - Øyvind Harboe, oyvind.harboe zylin.com ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
+---- ----
+---- Distributed under the BSD license ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Design unit: txt_util (Package) ----
+---- File name: txt_util.vhdl ----
+---- Note: None ----
+---- Limitations: None known ----
+---- Errors: None known ----
+---- Library: zpu ----
+---- Dependencies: IEEE.std_logic_1164 ----
+---- IEEE.numeric_std ----
+---- std.textio ----
+---- Target FPGA: N/A ----
+---- Language: VHDL ----
+---- Wishbone: No ----
+---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
+---- Text editor: SETEdit 0.5.x ----
+---- ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use std.textio.all;
+
+library zpu;
+
+package txt_util is
+ -- prints a message to the screen
+ procedure print(text: string);
+
+ -- prints the message when active
+ -- useful for debug switches
+ procedure print(active: boolean; text: string);
+
+ -- converts std_logic into a character
+ function chr(sl: std_logic) return character;
+
+ -- converts std_logic into a string (1 to 1)
+ function str(sl: std_logic) return string;
+
+ -- converts std_logic_vector into a string (binary base)
+ function str(slv: std_logic_vector) return string;
+
+ -- converts boolean into a string
+ function str(b: boolean) return string;
+
+ -- converts an integer into a single character
+ -- (can also be used for hex conversion and other bases)
+ function chr(int: integer) return character;
+
+ -- converts integer into string using specified base
+ function str(int: integer; base: integer) return string;
+
+ -- converts integer to string, using base 10
+ function str(int: integer) return string;
+
+ -- convert std_logic_vector into a string in hex format
+ function hstr(slv: std_logic_vector) return string;
+ function hstr(slv: unsigned) return string;
+
+
+ -- functions to manipulate strings
+ -----------------------------------
+
+ -- convert a character to upper case
+ function to_upper(c: character) return character;
+
+ -- convert a character to lower case
+ function to_lower(c: character) return character;
+
+ -- convert a string to upper case
+ function to_upper(s: string) return string;
+
+ -- convert a string to lower case
+ function to_lower(s: string) return string;
+
+
+
+ -- functions to convert strings into other formats
+ --------------------------------------------------
+
+ -- converts a character into std_logic
+ function to_std_logic(c: character) return std_logic;
+
+ -- converts a string into std_logic_vector
+ function to_std_logic_vector(s: string) return std_logic_vector;
+
+
+
+ -- file I/O
+ -----------
+
+ -- read variable length string from input file
+ procedure str_read(file in_file: TEXT;
+ res_string: out string);
+
+ procedure str_write(file out_file: TEXT;
+ new_string: in string);
+
+ -- print string to a file and start new line
+ procedure print(file out_file: TEXT;
+ new_string: in string);
+
+ -- print character to a file and start new line
+ procedure print(file out_file: TEXT;
+ char: in character);
+end package txt_util;
+
+
+
+
+package body txt_util is
+ -- prints text to the screen
+ procedure print(text: string) is
+ variable msg_line: line;
+ begin
+ --synopsys translate off
+ write(msg_line, text);
+ writeline(output, msg_line);
+ --synopsys translate on
+ end procedure print;
+
+ -- prints text to the screen when active
+ procedure print(active: boolean; text: string) is
+ begin
+ if active then
+ print(text);
+ end if;
+ end procedure print;
+
+ -- converts std_logic into a character
+ function chr(sl: std_logic) return character is
+ variable c: character;
+ begin
+ case sl is
+ when 'U' => c:= 'U';
+ when 'X' => c:= 'X';
+ when '0' => c:= '0';
+ when '1' => c:= '1';
+ when 'Z' => c:= 'Z';
+ when 'W' => c:= 'W';
+ when 'L' => c:= 'L';
+ when 'H' => c:= 'H';
+ when '-' => c:= '-';
+ end case;
+ return c;
+ end function chr;
+
+ -- converts std_logic into a string (1 to 1)
+ function str(sl: std_logic) return string is
+ variable s: string(1 to 1);
+ begin
+ s(1):=chr(sl);
+ return s;
+ end function str;
+
+ -- converts std_logic_vector into a string (binary base)
+ -- (this also takes care of the fact that the range of
+ -- a string is natural while a std_logic_vector may
+ -- have an integer range)
+ function str(slv: std_logic_vector) return string is
+ variable result : string (1 to slv'length);
+ variable r : integer;
+ begin
+ r:=1;
+ for i in slv'range loop
+ result(r) := chr(slv(i));
+ r:=r+1;
+ end loop;
+ return result;
+ end function str;
+
+
+ function str(b: boolean) return string is
+ begin
+ if b then
+ return "true";
+ else
+ return "false";
+ end if;
+ end function str;
+
+ -- converts an integer into a character
+ -- for 0 to 9 the obvious mapping is used, higher
+ -- values are mapped to the characters A-Z
+ -- (this is usefull for systems with base > 10)
+ -- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
+ function chr(int: integer) return character is
+ variable c: character;
+ begin
+ case int is
+ when 0 => c := '0';
+ when 1 => c := '1';
+ when 2 => c := '2';
+ when 3 => c := '3';
+ when 4 => c := '4';
+ when 5 => c := '5';
+ when 6 => c := '6';
+ when 7 => c := '7';
+ when 8 => c := '8';
+ when 9 => c := '9';
+ when 10 => c := 'A';
+ when 11 => c := 'B';
+ when 12 => c := 'C';
+ when 13 => c := 'D';
+ when 14 => c := 'E';
+ when 15 => c := 'F';
+ when 16 => c := 'G';
+ when 17 => c := 'H';
+ when 18 => c := 'I';
+ when 19 => c := 'J';
+ when 20 => c := 'K';
+ when 21 => c := 'L';
+ when 22 => c := 'M';
+ when 23 => c := 'N';
+ when 24 => c := 'O';
+ when 25 => c := 'P';
+ when 26 => c := 'Q';
+ when 27 => c := 'R';
+ when 28 => c := 'S';
+ when 29 => c := 'T';
+ when 30 => c := 'U';
+ when 31 => c := 'V';
+ when 32 => c := 'W';
+ when 33 => c := 'X';
+ when 34 => c := 'Y';
+ when 35 => c := 'Z';
+ when others => c := '?';
+ end case;
+ return c;
+ end function chr;
+
+ -- convert integer to string using specified base
+ -- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
+ function str(int: integer; base: integer) return string is
+ variable temp : string(1 to 10);
+ variable num : integer;
+ variable abs_int : integer;
+ variable len : integer:=1;
+ variable power : integer:=1;
+ begin
+ -- bug fix for negative numbers
+ abs_int:=abs(int);
+
+ num :=abs_int;
+
+ while num>=base loop -- Determine how many
+ len:=len+1; -- characters required
+ num:=num/base; -- to represent the
+ end loop; -- number.
+
+ for i in len downto 1 loop -- Convert the number to
+ temp(i):=chr(abs_int/power mod base); -- a string starting
+ power:=power*base; -- with the right hand
+ end loop ; -- side.
+
+ -- return result and add sign if required
+ if int<0 then
+ return '-'& temp(1 to len);
+ else
+ return temp(1 to len);
+ end if;
+ end function str;
+
+ -- convert integer to string, using base 10
+ function str(int: integer) return string is
+ begin
+ return str(int, 10) ;
+ end function str;
+
+ -- converts a std_logic_vector into a hex string.
+ function hstr(slv: std_logic_vector) return string is
+ variable hexlen: integer;
+ variable longslv : std_logic_vector(67 downto 0):=(others => '0');
+ variable hex : string(1 to 16);
+ variable fourbit : std_logic_vector(3 downto 0);
+ begin
+ hexlen:=(slv'left+1)/4;
+ if (slv'left+1) mod 4/=0 then
+ hexlen := hexlen + 1;
+ end if;
+ longslv(slv'left downto 0) := slv;
+ for i in (hexlen-1) downto 0 loop
+ fourbit:=longslv(((i*4)+3) downto (i*4));
+ case fourbit is
+ when "0000" => hex(hexlen-I):='0';
+ when "0001" => hex(hexlen-I):='1';
+ when "0010" => hex(hexlen-I):='2';
+ when "0011" => hex(hexlen-I):='3';
+ when "0100" => hex(hexlen-I):='4';
+ when "0101" => hex(hexlen-I):='5';
+ when "0110" => hex(hexlen-I):='6';
+ when "0111" => hex(hexlen-I):='7';
+ when "1000" => hex(hexlen-I):='8';
+ when "1001" => hex(hexlen-I):='9';
+ when "1010" => hex(hexlen-I):='A';
+ when "1011" => hex(hexlen-I):='B';
+ when "1100" => hex(hexlen-I):='C';
+ when "1101" => hex(hexlen-I):='D';
+ when "1110" => hex(hexlen-I):='E';
+ when "1111" => hex(hexlen-I):='F';
+ when "ZZZZ" => hex(hexlen-I):='z';
+ when "UUUU" => hex(hexlen-I):='u';
+ when "XXXX" => hex(hexlen-I):='x';
+ when others => hex(hexlen-I):='?';
+ end case;
+ end loop;
+ return hex(1 to hexlen);
+ end function hstr;
+
+ function hstr(slv: unsigned) return string is
+ begin
+ return hstr(std_logic_vector(slv));
+ end function hstr;
+
+ -- functions to manipulate strings
+ -----------------------------------
+
+
+ -- convert a character to upper case
+ function to_upper(c: character) return character is
+ variable u: character;
+ begin
+ case c is
+ when 'a' => u:='A';
+ when 'b' => u:='B';
+ when 'c' => u:='C';
+ when 'd' => u:='D';
+ when 'e' => u:='E';
+ when 'f' => u:='F';
+ when 'g' => u:='G';
+ when 'h' => u:='H';
+ when 'i' => u:='I';
+ when 'j' => u:='J';
+ when 'k' => u:='K';
+ when 'l' => u:='L';
+ when 'm' => u:='M';
+ when 'n' => u:='N';
+ when 'o' => u:='O';
+ when 'p' => u:='P';
+ when 'q' => u:='Q';
+ when 'r' => u:='R';
+ when 's' => u:='S';
+ when 't' => u:='T';
+ when 'u' => u:='U';
+ when 'v' => u:='V';
+ when 'w' => u:='W';
+ when 'x' => u:='X';
+ when 'y' => u:='Y';
+ when 'z' => u:='Z';
+ when others => u:=c;
+ end case;
+ return u;
+ end function to_upper;
+
+
+ -- convert a character to lower case
+ function to_lower(c: character) return character is
+ variable l: character;
+ begin
+ case c is
+ when 'A' => l:='a';
+ when 'B' => l:='b';
+ when 'C' => l:='c';
+ when 'D' => l:='d';
+ when 'E' => l:='e';
+ when 'F' => l:='f';
+ when 'G' => l:='g';
+ when 'H' => l:='h';
+ when 'I' => l:='i';
+ when 'J' => l:='j';
+ when 'K' => l:='k';
+ when 'L' => l:='l';
+ when 'M' => l:='m';
+ when 'N' => l:='n';
+ when 'O' => l:='o';
+ when 'P' => l:='p';
+ when 'Q' => l:='q';
+ when 'R' => l:='r';
+ when 'S' => l:='s';
+ when 'T' => l:='t';
+ when 'U' => l:='u';
+ when 'V' => l:='v';
+ when 'W' => l:='w';
+ when 'X' => l:='x';
+ when 'Y' => l:='y';
+ when 'Z' => l:='z';
+ when others => l:=c;
+ end case;
+ return l;
+ end function to_lower;
+
+ -- convert a string to upper case
+ function to_upper(s: string) return string is
+ variable uppercase: string (s'range);
+ begin
+ for i in s'range loop
+ uppercase(i):=to_upper(s(i));
+ end loop;
+ return uppercase;
+ end to_upper;
+
+ -- convert a string to lower case
+ function to_lower(s: string) return string is
+ variable lowercase: string (s'range);
+ begin
+ for i in s'range loop
+ lowercase(i):=to_lower(s(i));
+ end loop;
+ return lowercase;
+ end to_lower;
+
+ -- functions to convert strings into other types
+
+ -- converts a character into a std_logic
+
+ function to_std_logic(c: character) return std_logic is
+ variable sl : std_logic;
+ begin
+ case c is
+ when 'U' =>
+ sl:='U';
+ when 'X' =>
+ sl:='X';
+ when '0' =>
+ sl:='0';
+ when '1' =>
+ sl:='1';
+ when 'Z' =>
+ sl:='Z';
+ when 'W' =>
+ sl:='W';
+ when 'L' =>
+ sl:='L';
+ when 'H' =>
+ sl:='H';
+ when '-' =>
+ sl:='-';
+ when others =>
+ sl:='X';
+ end case;
+ return sl;
+ end function to_std_logic;
+
+
+ -- converts a string into std_logic_vector
+ function to_std_logic_vector(s: string) return std_logic_vector is
+ variable slv : std_logic_vector(s'high-s'low downto 0);
+ variable k : integer;
+ begin
+ k:=s'high-s'low;
+ for i in s'range loop
+ slv(k):=to_std_logic(s(i));
+ k :=k-1;
+ end loop;
+ return slv;
+ end function to_std_logic_vector;
+
+
+ ----------------
+ -- file I/O --
+ ----------------
+
+ -- read variable length string from input file
+ procedure str_read(file in_file: TEXT;
+ res_string: out string) is
+ variable l : line;
+ variable c : character;
+ variable is_string : boolean;
+ begin
+ readline(in_file, l);
+ -- clear the contents of the result string
+ for i in res_string'range loop
+ res_string(i):=' ';
+ end loop;
+ -- read all characters of the line, up to the length
+ -- of the results string
+ for i in res_string'range loop
+ read(l,c,is_string);
+ res_string(i):=c;
+ if not is_string then -- found end of line
+ exit;
+ end if;
+ end loop;
+ end procedure str_read;
+
+ -- print string to a file
+ procedure print(file out_file: TEXT;
+ new_string: in string) is
+ variable l: line;
+ begin
+ write(l,new_string);
+ writeline(out_file,l);
+ end procedure print;
+
+ -- print character to a file and start new line
+ procedure print(file out_file: TEXT;
+ char: in character) is
+ variable l: line;
+ begin
+ write(l,char);
+ writeline(out_file,l);
+ end procedure print;
+
+ -- appends contents of a string to a file until line feed occurs
+ -- (LF is considered to be the end of the string)
+ procedure str_write(file out_file: TEXT;
+ new_string: in string) is
+ begin
+ for i in new_string'range loop
+ print(out_file,new_string(i));
+ if new_string(i)=LF then -- end of string
+ exit;
+ end if;
+ end loop;
+ end str_write;
+end package body txt_util;
+
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/clean_up.sh b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/clean_up.sh
new file mode 100755
index 0000000..3855f16
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/clean_up.sh
@@ -0,0 +1,16 @@
+#!/bin/sh
+
+# ise build stuff
+rm -rf build
+rm -f top.bit
+
+# modelsim compile stuff
+rm -rf work
+rm -rf zpu
+
+# modelsim simulation stuff
+rm -f vsim.wlf
+rm -f transcript
+rm -f zpu_trace.log
+rm -f zpu_med1_io.log
+rm -f zpu_small1_io.log
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation.sh b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation.sh
new file mode 100755
index 0000000..d525737
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation.sh
@@ -0,0 +1,49 @@
+#!/bin/sh
+
+# need project files:
+# run.do
+# wave.do
+
+# need ModelSim tools:
+# vlib
+# vcom
+# vsim
+
+
+echo "###############"
+echo "compile zpu lib"
+echo "###############"
+vlib zpu
+vcom -work zpu ../../roms/hello_dbram.vhdl
+vcom -work zpu ../../roms/hello_bram.vhdl
+#vcom -work zpu ../../roms/dmips_dbram.vhdl
+#vcom -work zpu ../../roms/dmips_bram.vhdl
+
+vcom -work zpu ../../roms/rom_pkg.vhdl
+vcom -work zpu ../../zpu_pkg.vhdl
+vcom -work zpu ../../zpu_small.vhdl
+vcom -work zpu ../../zpu_medium.vhdl
+vcom -work zpu ../../helpers/zpu_small1.vhdl
+vcom -work zpu ../../helpers/zpu_med1.vhdl
+vcom -work zpu ../../devices/txt_util.vhdl
+vcom -work zpu ../../devices/phi_io.vhdl
+vcom -work zpu ../../devices/timer.vhdl
+vcom -work zpu ../../devices/gpio.vhdl
+vcom -work zpu ../../devices/rx_unit.vhdl
+vcom -work zpu ../../devices/tx_unit.vhdl
+vcom -work zpu ../../devices/br_gen.vhdl
+vcom -work zpu ../../devices/trace.vhdl
+
+
+echo "################"
+echo "compile work lib"
+echo "################"
+vlib work
+vcom top.vhd
+vcom top_tb.vhd
+
+
+echo "###################"
+echo "start simulator gui"
+echo "###################"
+vsim -gui top_tb -do simulation_config/run.do
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/run.do b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/run.do
new file mode 100644
index 0000000..acc1710
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/run.do
@@ -0,0 +1,2 @@
+do wave.do
+run -all
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/wave.do b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/wave.do
new file mode 100644
index 0000000..3f5d4fe
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/wave.do
@@ -0,0 +1,30 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /top_tb/tb_reset_n
+add wave -noupdate /top_tb/tb_clk
+add wave -noupdate -divider <NULL>
+add wave -noupdate /top_tb/tb_rs232_rx
+add wave -noupdate /top_tb/tb_rs232_tx
+add wave -noupdate /top_tb/tb_rs232_rts
+add wave -noupdate /top_tb/tb_rs232_cts
+add wave -noupdate -divider Buttons
+add wave -noupdate /top_tb/tb_button_n
+add wave -noupdate -divider LEDs
+add wave -noupdate /top_tb/tb_led
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {0 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 2
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {1294218073 ps} {1421130628 ps}
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis.sh b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis.sh
new file mode 100755
index 0000000..a7180fc
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis.sh
@@ -0,0 +1,36 @@
+#!/bin/sh
+
+# need project files:
+# top.xst
+# top.prj
+# top.ut
+
+# need Xilinx tools:
+# xst
+# ngdbuild
+# map
+# par
+# trce
+# bitgen
+
+echo "########################"
+echo "generate build directory"
+echo "########################"
+mkdir build
+cd build
+mkdir tmp
+
+echo "###############"
+echo "start processes"
+echo "###############"
+xst -ifn "../synthesis_config/top.xst" -ofn "top.syr"
+ngdbuild -dd _ngo -nt timestamp -uc ../synthesis_config/altium-livedesign-xc3s1000.ucf -p xc3s1000-fg456-4 top.ngc top.ngd
+map -p xc3s1000-fg456-4 -cm area -ir off -pr off -c 100 -o top_map.ncd top.ngd top.pcf
+par -w -ol high -t 1 top_map.ncd top.ncd top.pcf
+trce -v 3 -s 4 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf
+bitgen -f ../synthesis_config/top.ut top.ncd
+
+echo "###########"
+echo "get bitfile"
+echo "###########"
+cp top.bit ..
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/altium-livedesign-xc3s1000.ucf b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/altium-livedesign-xc3s1000.ucf
new file mode 100644
index 0000000..ba22ee9
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/altium-livedesign-xc3s1000.ucf
@@ -0,0 +1,397 @@
+############################################################
+# Altium Livedesign Evaluation Board constraints file
+#
+# Familiy: Spartan-3
+# Device: XC3S1000
+# Package: FG456C
+# Speed: -4
+#
+# all banks are powered with 3.3V
+#
+# config pins (M2, M1, M0): 101
+
+############################################################
+## clock/timing constraints
+############################################################
+
+NET "clk_50" period = 50 MHz ;
+
+
+############################################################
+## pin placement constraints
+############################################################
+
+NET "clk_50" LOC = AA12 | IOSTANDARD = LVCMOS33;
+NET "reset_n" LOC = Y17 | IOSTANDARD = LVCMOS33; # low active
+
+# Soft JTAG
+NET "soft_tdo" LOC = D22 | IOSTANDARD = LVCMOS33;
+NET "soft_tms" LOC = E21 | IOSTANDARD = LVCMOS33;
+NET "soft_tdi" LOC = E22 | IOSTANDARD = LVCMOS33;
+NET "soft_tck" LOC = F21 | IOSTANDARD = LVCMOS33;
+
+# SRAM 0
+NET "sram0_a<0>" LOC = L6 | IOSTANDARD = LVCMOS33;
+NET "sram0_a<1>" LOC = K4 | IOSTANDARD = LVCMOS33;
+NET "sram0_a<2>" LOC = H5 | IOSTANDARD = LVCMOS33;
+NET "sram0_a<3>" LOC = G6 | IOSTANDARD = LVCMOS33;
+NET "sram0_a<4>" LOC = F3 | IOSTANDARD = LVCMOS33;
+NET "sram0_a<5>" LOC = G1 | IOSTANDARD = LVCMOS33;
+NET "sram0_a<6>" LOC = G2 | IOSTANDARD = LVCMOS33;
+NET "sram0_a<7>" LOC = K3 | IOSTANDARD = LVCMOS33;
+NET "sram0_a<8>" LOC = T2 | IOSTANDARD = LVCMOS33;
+NET "sram0_a<9>" LOC = T1 | IOSTANDARD = LVCMOS33;
+NET "sram0_a<10>" LOC = U2 | IOSTANDARD = LVCMOS33;
+NET "sram0_a<11>" LOC = V3 | IOSTANDARD = LVCMOS33;
+NET "sram0_a<12>" LOC = V1 | IOSTANDARD = LVCMOS33;
+NET "sram0_a<13>" LOC = W1 | IOSTANDARD = LVCMOS33;
+NET "sram0_a<14>" LOC = V2 | IOSTANDARD = LVCMOS33;
+NET "sram0_a<15>" LOC = V5 | IOSTANDARD = LVCMOS33;
+NET "sram0_a<16>" LOC = V4 | IOSTANDARD = LVCMOS33;
+NET "sram0_a<17>" LOC = U5 | IOSTANDARD = LVCMOS33;
+NET "sram0_a<18>" LOC = U6 | IOSTANDARD = LVCMOS33; # n.c.
+NET "sram0_d<0>" LOC = L4 | IOSTANDARD = LVCMOS33;
+NET "sram0_d<1>" LOC = L3 | IOSTANDARD = LVCMOS33;
+NET "sram0_d<2>" LOC = M5 | IOSTANDARD = LVCMOS33;
+NET "sram0_d<3>" LOC = M4 | IOSTANDARD = LVCMOS33;
+NET "sram0_d<4>" LOC = M3 | IOSTANDARD = LVCMOS33;
+NET "sram0_d<5>" LOC = N4 | IOSTANDARD = LVCMOS33;
+NET "sram0_d<6>" LOC = N3 | IOSTANDARD = LVCMOS33;
+NET "sram0_d<7>" LOC = T5 | IOSTANDARD = LVCMOS33;
+NET "sram0_d<8>" LOC = T4 | IOSTANDARD = LVCMOS33;
+NET "sram0_d<9>" LOC = T6 | IOSTANDARD = LVCMOS33;
+NET "sram0_d<10>" LOC = M6 | IOSTANDARD = LVCMOS33;
+NET "sram0_d<11>" LOC = N2 | IOSTANDARD = LVCMOS33;
+NET "sram0_d<12>" LOC = N1 | IOSTANDARD = LVCMOS33;
+NET "sram0_d<13>" LOC = M2 | IOSTANDARD = LVCMOS33;
+NET "sram0_d<14>" LOC = M1 | IOSTANDARD = LVCMOS33;
+NET "sram0_d<15>" LOC = L2 | IOSTANDARD = LVCMOS33;
+NET "sram0_cs_n" LOC = L5 | IOSTANDARD = LVCMOS33;
+NET "sram0_lb_n" LOC = L1 | IOSTANDARD = LVCMOS33;
+NET "sram0_ub_n" LOC = K2 | IOSTANDARD = LVCMOS33;
+NET "sram0_we_n" LOC = U4 | IOSTANDARD = LVCMOS33;
+NET "sram0_oe_n" LOC = K1 | IOSTANDARD = LVCMOS33;
+
+# SRAM 1
+NET "sram1_a<0>" LOC = K21 | IOSTANDARD = LVCMOS33;
+NET "sram1_a<1>" LOC = K22 | IOSTANDARD = LVCMOS33;
+NET "sram1_a<2>" LOC = K20 | IOSTANDARD = LVCMOS33;
+NET "sram1_a<3>" LOC = G21 | IOSTANDARD = LVCMOS33;
+NET "sram1_a<4>" LOC = G22 | IOSTANDARD = LVCMOS33;
+NET "sram1_a<5>" LOC = M17 | IOSTANDARD = LVCMOS33;
+NET "sram1_a<6>" LOC = L18 | IOSTANDARD = LVCMOS33;
+NET "sram1_a<7>" LOC = K19 | IOSTANDARD = LVCMOS33;
+NET "sram1_a<8>" LOC = V19 | IOSTANDARD = LVCMOS33;
+NET "sram1_a<9>" LOC = W20 | IOSTANDARD = LVCMOS33;
+NET "sram1_a<10>" LOC = W19 | IOSTANDARD = LVCMOS33;
+NET "sram1_a<11>" LOC = Y20 | IOSTANDARD = LVCMOS33;
+NET "sram1_a<12>" LOC = Y21 | IOSTANDARD = LVCMOS33;
+NET "sram1_a<13>" LOC = Y22 | IOSTANDARD = LVCMOS33;
+NET "sram1_a<14>" LOC = W21 | IOSTANDARD = LVCMOS33;
+NET "sram1_a<15>" LOC = W22 | IOSTANDARD = LVCMOS33;
+NET "sram1_a<16>" LOC = V21 | IOSTANDARD = LVCMOS33;
+NET "sram1_a<17>" LOC = V22 | IOSTANDARD = LVCMOS33;
+NET "sram1_a<18>" LOC = V20 | IOSTANDARD = LVCMOS33; # n.c.
+NET "sram1_d<0>" LOC = L21 | IOSTANDARD = LVCMOS33;
+NET "sram1_d<1>" LOC = M22 | IOSTANDARD = LVCMOS33;
+NET "sram1_d<2>" LOC = M21 | IOSTANDARD = LVCMOS33;
+NET "sram1_d<3>" LOC = N22 | IOSTANDARD = LVCMOS33;
+NET "sram1_d<4>" LOC = N21 | IOSTANDARD = LVCMOS33;
+NET "sram1_d<5>" LOC = U20 | IOSTANDARD = LVCMOS33;
+NET "sram1_d<6>" LOC = T22 | IOSTANDARD = LVCMOS33;
+NET "sram1_d<7>" LOC = T21 | IOSTANDARD = LVCMOS33;
+NET "sram1_d<8>" LOC = V18 | IOSTANDARD = LVCMOS33;
+NET "sram1_d<9>" LOC = U19 | IOSTANDARD = LVCMOS33;
+NET "sram1_d<10>" LOC = U18 | IOSTANDARD = LVCMOS33;
+NET "sram1_d<11>" LOC = T18 | IOSTANDARD = LVCMOS33;
+NET "sram1_d<12>" LOC = R18 | IOSTANDARD = LVCMOS33;
+NET "sram1_d<13>" LOC = T17 | IOSTANDARD = LVCMOS33;
+NET "sram1_d<14>" LOC = M18 | IOSTANDARD = LVCMOS33;
+NET "sram1_d<15>" LOC = M20 | IOSTANDARD = LVCMOS33;
+NET "sram1_cs_n" LOC = L22 | IOSTANDARD = LVCMOS33;
+NET "sram1_lb_n" LOC = M19 | IOSTANDARD = LVCMOS33;
+NET "sram1_ub_n" LOC = L20 | IOSTANDARD = LVCMOS33;
+NET "sram1_we_n" LOC = U21 | IOSTANDARD = LVCMOS33;
+NET "sram1_oe_n" LOC = L19 | IOSTANDARD = LVCMOS33;
+
+# RS232
+NET "rs232_rx" LOC = A5 | IOSTANDARD = LVCMOS33;
+NET "rs232_tx" LOC = F7 | IOSTANDARD = LVCMOS33;
+NET "rs232_cts" LOC = F2 | IOSTANDARD = LVCMOS33;
+NET "rs232_rts" LOC = E1 | IOSTANDARD = LVCMOS33;
+
+# 2x PS2 connectors
+NET "mouse_clk" LOC = L17 | IOSTANDARD = LVCMOS33;
+NET "mouse_data" LOC = G18 | IOSTANDARD = LVCMOS33;
+NET "kbd_clk" LOC = F20 | IOSTANDARD = LVCMOS33;
+NET "kbd_data" LOC = G19 | IOSTANDARD = LVCMOS33;
+
+
+# VGA output (2**9 = 512 colors)
+NET "vga_blue<7>" LOC = E14 | IOSTANDARD = LVCMOS33;
+NET "vga_blue<6>" LOC = A13 | IOSTANDARD = LVCMOS33;
+NET "vga_blue<5>" LOC = C13 | IOSTANDARD = LVCMOS33;
+NET "vga_green<7>" LOC = E11 | IOSTANDARD = LVCMOS33;
+NET "vga_green<6>" LOC = C11 | IOSTANDARD = LVCMOS33;
+NET "vga_green<5>" LOC = D10 | IOSTANDARD = LVCMOS33;
+NET "vga_red<7>" LOC = D6 | IOSTANDARD = LVCMOS33;
+NET "vga_red<6>" LOC = D7 | IOSTANDARD = LVCMOS33;
+NET "vga_red<5>" LOC = D9 | IOSTANDARD = LVCMOS33;
+NET "vga_hsync" LOC = A8 | IOSTANDARD = LVCMOS33;
+NET "vga_vsync" LOC = B14 | IOSTANDARD = LVCMOS33;
+
+
+# Stereo Audio out
+NET "audio_r" LOC = U3 | IOSTANDARD = LVCMOS33;
+NET "audio_l" LOC = W3 | IOSTANDARD = LVCMOS33;
+
+
+# GPIO DIP switches 7..0 left..right, low active
+NET "switch_n<0>" LOC = Y6 | IOSTANDARD = LVCMOS33;
+NET "switch_n<1>" LOC = V6 | IOSTANDARD = LVCMOS33;
+NET "switch_n<2>" LOC = U7 | IOSTANDARD = LVCMOS33;
+NET "switch_n<3>" LOC = AA4 | IOSTANDARD = LVCMOS33;
+NET "switch_n<4>" LOC = AB4 | IOSTANDARD = LVCMOS33;
+NET "switch_n<5>" LOC = AA5 | IOSTANDARD = LVCMOS33;
+NET "switch_n<6>" LOC = AB5 | IOSTANDARD = LVCMOS33;
+NET "switch_n<7>" LOC = AA6 | IOSTANDARD = LVCMOS33;
+
+# GPIO push buttons, low active
+NET "button_n<5>" LOC = C21 | IOSTANDARD = LVCMOS33;
+NET "button_n<4>" LOC = B20 | IOSTANDARD = LVCMOS33;
+NET "button_n<3>" LOC = A15 | IOSTANDARD = LVCMOS33;
+NET "button_n<2>" LOC = B6 | IOSTANDARD = LVCMOS33;
+NET "button_n<1>" LOC = C1 | IOSTANDARD = LVCMOS33;
+NET "button_n<0>" LOC = D1 | IOSTANDARD = LVCMOS33;
+
+# GPIO LEDs
+NET "led<7>" LOC = W6 | IOSTANDARD = LVCMOS33;
+NET "led<6>" LOC = Y5 | IOSTANDARD = LVCMOS33;
+NET "led<5>" LOC = W5 | IOSTANDARD = LVCMOS33;
+NET "led<4>" LOC = W4 | IOSTANDARD = LVCMOS33;
+NET "led<3>" LOC = Y3 | IOSTANDARD = LVCMOS33;
+NET "led<2>" LOC = Y2 | IOSTANDARD = LVCMOS33;
+NET "led<1>" LOC = Y1 | IOSTANDARD = LVCMOS33;
+NET "led<0>" LOC = W2 | IOSTANDARD = LVCMOS33;
+
+# seven segment display (5=left 0=right)
+#
+# segment assignment:
+# .ABCDEFG
+# 76543210
+NET "dig0_seg<7>" LOC = E20 | IOSTANDARD = LVCMOS33;
+NET "dig0_seg<6>" LOC = C22 | IOSTANDARD = LVCMOS33;
+NET "dig0_seg<5>" LOC = E18 | IOSTANDARD = LVCMOS33;
+NET "dig0_seg<4>" LOC = D20 | IOSTANDARD = LVCMOS33;
+NET "dig0_seg<3>" LOC = D21 | IOSTANDARD = LVCMOS33;
+NET "dig0_seg<2>" LOC = E19 | IOSTANDARD = LVCMOS33;
+NET "dig0_seg<1>" LOC = G17 | IOSTANDARD = LVCMOS33;
+NET "dig0_seg<0>" LOC = F19 | IOSTANDARD = LVCMOS33;
+
+NET "dig1_seg<7>" LOC = F17 | IOSTANDARD = LVCMOS33;
+NET "dig1_seg<6>" LOC = D18 | IOSTANDARD = LVCMOS33;
+NET "dig1_seg<5>" LOC = B19 | IOSTANDARD = LVCMOS33;
+NET "dig1_seg<4>" LOC = C18 | IOSTANDARD = LVCMOS33;
+NET "dig1_seg<3>" LOC = C19 | IOSTANDARD = LVCMOS33;
+NET "dig1_seg<2>" LOC = C20 | IOSTANDARD = LVCMOS33;
+NET "dig1_seg<1>" LOC = F18 | IOSTANDARD = LVCMOS33;
+NET "dig1_seg<0>" LOC = D19 | IOSTANDARD = LVCMOS33;
+
+NET "dig2_seg<7>" LOC = A19 | IOSTANDARD = LVCMOS33;
+NET "dig2_seg<6>" LOC = E17 | IOSTANDARD = LVCMOS33;
+NET "dig2_seg<5>" LOC = C17 | IOSTANDARD = LVCMOS33;
+NET "dig2_seg<4>" LOC = D17 | IOSTANDARD = LVCMOS33;
+NET "dig2_seg<3>" LOC = B15 | IOSTANDARD = LVCMOS33;
+NET "dig2_seg<2>" LOC = A18 | IOSTANDARD = LVCMOS33;
+NET "dig2_seg<1>" LOC = B18 | IOSTANDARD = LVCMOS33;
+NET "dig2_seg<0>" LOC = B17 | IOSTANDARD = LVCMOS33;
+
+NET "dig3_seg<7>" LOC = D15 | IOSTANDARD = LVCMOS33;
+NET "dig3_seg<6>" LOC = E13 | IOSTANDARD = LVCMOS33;
+NET "dig3_seg<5>" LOC = B13 | IOSTANDARD = LVCMOS33;
+NET "dig3_seg<4>" LOC = D13 | IOSTANDARD = LVCMOS33;
+NET "dig3_seg<3>" LOC = D14 | IOSTANDARD = LVCMOS33;
+NET "dig3_seg<2>" LOC = A14 | IOSTANDARD = LVCMOS33;
+NET "dig3_seg<1>" LOC = E16 | IOSTANDARD = LVCMOS33;
+NET "dig3_seg<0>" LOC = E15 | IOSTANDARD = LVCMOS33;
+
+NET "dig4_seg<7>" LOC = D11 | IOSTANDARD = LVCMOS33;
+NET "dig4_seg<6>" LOC = E9 | IOSTANDARD = LVCMOS33;
+NET "dig4_seg<5>" LOC = A10 | IOSTANDARD = LVCMOS33;
+NET "dig4_seg<4>" LOC = B9 | IOSTANDARD = LVCMOS33;
+NET "dig4_seg<3>" LOC = A9 | IOSTANDARD = LVCMOS33;
+NET "dig4_seg<2>" LOC = C10 | IOSTANDARD = LVCMOS33;
+NET "dig4_seg<1>" LOC = A12 | IOSTANDARD = LVCMOS33;
+NET "dig4_seg<0>" LOC = B10 | IOSTANDARD = LVCMOS33;
+
+NET "dig5_seg<7>" LOC = C7 | IOSTANDARD = LVCMOS33;
+NET "dig5_seg<6>" LOC = A4 | IOSTANDARD = LVCMOS33;
+NET "dig5_seg<5>" LOC = B5 | IOSTANDARD = LVCMOS33;
+NET "dig5_seg<4>" LOC = E6 | IOSTANDARD = LVCMOS33;
+NET "dig5_seg<3>" LOC = C5 | IOSTANDARD = LVCMOS33;
+NET "dig5_seg<2>" LOC = E7 | IOSTANDARD = LVCMOS33;
+NET "dig5_seg<1>" LOC = B8 | IOSTANDARD = LVCMOS33;
+NET "dig5_seg<0>" LOC = C6 | IOSTANDARD = LVCMOS33;
+
+
+# Header A (left)
+NET "header_a<2>" LOC = V7 | IOSTANDARD = LVCMOS33;
+NET "header_a<3>" LOC = AA8 | IOSTANDARD = LVCMOS33;
+NET "header_a<4>" LOC = AB8 | IOSTANDARD = LVCMOS33;
+NET "header_a<5>" LOC = V8 | IOSTANDARD = LVCMOS33;
+NET "header_a<6>" LOC = Y10 | IOSTANDARD = LVCMOS33;
+NET "header_a<7>" LOC = V9 | IOSTANDARD = LVCMOS33;
+NET "header_a<8>" LOC = W9 | IOSTANDARD = LVCMOS33;
+NET "header_a<9>" LOC = AA10 | IOSTANDARD = LVCMOS33;
+NET "header_a<10>" LOC = AB10 | IOSTANDARD = LVCMOS33;
+NET "header_a<11>" LOC = W10 | IOSTANDARD = LVCMOS33;
+NET "header_a<12>" LOC = AB11 | IOSTANDARD = LVCMOS33;
+NET "header_a<13>" LOC = U11 | IOSTANDARD = LVCMOS33;
+NET "header_a<14>" LOC = AB13 | IOSTANDARD = LVCMOS33;
+NET "header_a<15>" LOC = AA13 | IOSTANDARD = LVCMOS33;
+NET "header_a<16>" LOC = V10 | IOSTANDARD = LVCMOS33;
+NET "header_a<17>" LOC = U10 | IOSTANDARD = LVCMOS33;
+NET "header_a<18>" LOC = W13 | IOSTANDARD = LVCMOS33;
+NET "header_a<19>" LOC = Y13 | IOSTANDARD = LVCMOS33;
+
+# Header B (right)
+NET "header_b<2>" LOC = V14 | IOSTANDARD = LVCMOS33;
+NET "header_b<3>" LOC = V13 | IOSTANDARD = LVCMOS33;
+NET "header_b<4>" LOC = AA15 | IOSTANDARD = LVCMOS33;
+NET "header_b<5>" LOC = W14 | IOSTANDARD = LVCMOS33;
+NET "header_b<6>" LOC = AB15 | IOSTANDARD = LVCMOS33;
+NET "header_b<7>" LOC = Y16 | IOSTANDARD = LVCMOS33;
+NET "header_b<8>" LOC = AA17 | IOSTANDARD = LVCMOS33;
+NET "header_b<9>" LOC = AA18 | IOSTANDARD = LVCMOS33;
+NET "header_b<10>" LOC = AB18 | IOSTANDARD = LVCMOS33;
+NET "header_b<11>" LOC = Y18 | IOSTANDARD = LVCMOS33;
+NET "header_b<12>" LOC = Y19 | IOSTANDARD = LVCMOS33;
+NET "header_b<13>" LOC = AB20 | IOSTANDARD = LVCMOS33;
+NET "header_b<14>" LOC = AA20 | IOSTANDARD = LVCMOS33;
+NET "header_b<15>" LOC = U16 | IOSTANDARD = LVCMOS33;
+NET "header_b<16>" LOC = V16 | IOSTANDARD = LVCMOS33;
+NET "header_b<17>" LOC = V17 | IOSTANDARD = LVCMOS33;
+NET "header_b<18>" LOC = W16 | IOSTANDARD = LVCMOS33;
+NET "header_b<19>" LOC = W17 | IOSTANDARD = LVCMOS33;
+
+# usused pins
+CONFIG PROHIBIT = A3;
+CONFIG PROHIBIT = A7;
+CONFIG PROHIBIT = A11;
+CONFIG PROHIBIT = A16;
+CONFIG PROHIBIT = AA3;
+CONFIG PROHIBIT = AA7;
+CONFIG PROHIBIT = AA9;
+CONFIG PROHIBIT = AA11;
+CONFIG PROHIBIT = AA14;
+CONFIG PROHIBIT = AA16;
+CONFIG PROHIBIT = AA19;
+CONFIG PROHIBIT = AB7;
+CONFIG PROHIBIT = AB9;
+CONFIG PROHIBIT = AB12;
+CONFIG PROHIBIT = AB14;
+CONFIG PROHIBIT = AB16;
+CONFIG PROHIBIT = AB19;
+CONFIG PROHIBIT = B4;
+CONFIG PROHIBIT = B7;
+CONFIG PROHIBIT = B12;
+CONFIG PROHIBIT = B11;
+CONFIG PROHIBIT = B16;
+CONFIG PROHIBIT = C2;
+CONFIG PROHIBIT = C3;
+CONFIG PROHIBIT = C4;
+CONFIG PROHIBIT = C12;
+CONFIG PROHIBIT = C16;
+CONFIG PROHIBIT = D2;
+CONFIG PROHIBIT = D3;
+CONFIG PROHIBIT = D4;
+CONFIG PROHIBIT = D5;
+CONFIG PROHIBIT = D8;
+CONFIG PROHIBIT = D12;
+CONFIG PROHIBIT = D16;
+CONFIG PROHIBIT = E2;
+CONFIG PROHIBIT = E3;
+CONFIG PROHIBIT = E8;
+CONFIG PROHIBIT = E4;
+CONFIG PROHIBIT = E5;
+CONFIG PROHIBIT = F4;
+CONFIG PROHIBIT = E10;
+CONFIG PROHIBIT = E12;
+CONFIG PROHIBIT = F12;
+CONFIG PROHIBIT = F5;
+CONFIG PROHIBIT = F13;
+CONFIG PROHIBIT = F6;
+CONFIG PROHIBIT = F9;
+CONFIG PROHIBIT = F10;
+CONFIG PROHIBIT = F16;
+CONFIG PROHIBIT = F11;
+CONFIG PROHIBIT = F14;
+CONFIG PROHIBIT = G3;
+CONFIG PROHIBIT = G4;
+CONFIG PROHIBIT = G5;
+CONFIG PROHIBIT = G20;
+CONFIG PROHIBIT = H1;
+CONFIG PROHIBIT = H2;
+CONFIG PROHIBIT = H4;
+CONFIG PROHIBIT = H18;
+CONFIG PROHIBIT = H19;
+CONFIG PROHIBIT = H21;
+CONFIG PROHIBIT = H22;
+CONFIG PROHIBIT = J1;
+CONFIG PROHIBIT = J2;
+CONFIG PROHIBIT = J4;
+CONFIG PROHIBIT = J5;
+CONFIG PROHIBIT = J6;
+CONFIG PROHIBIT = J17;
+CONFIG PROHIBIT = J18;
+CONFIG PROHIBIT = J19;
+CONFIG PROHIBIT = J21;
+CONFIG PROHIBIT = J22;
+CONFIG PROHIBIT = K5;
+CONFIG PROHIBIT = K6;
+CONFIG PROHIBIT = K17;
+CONFIG PROHIBIT = K18;
+CONFIG PROHIBIT = N5;
+CONFIG PROHIBIT = N6;
+CONFIG PROHIBIT = N17;
+CONFIG PROHIBIT = N18;
+CONFIG PROHIBIT = N19;
+CONFIG PROHIBIT = N20;
+CONFIG PROHIBIT = P1;
+CONFIG PROHIBIT = P2;
+CONFIG PROHIBIT = P4;
+CONFIG PROHIBIT = P5;
+CONFIG PROHIBIT = P6;
+CONFIG PROHIBIT = P17;
+CONFIG PROHIBIT = P18;
+CONFIG PROHIBIT = P19;
+CONFIG PROHIBIT = P21;
+CONFIG PROHIBIT = P22;
+CONFIG PROHIBIT = R1;
+CONFIG PROHIBIT = R2;
+CONFIG PROHIBIT = R4;
+CONFIG PROHIBIT = R5;
+CONFIG PROHIBIT = R19;
+CONFIG PROHIBIT = R21;
+CONFIG PROHIBIT = R22;
+CONFIG PROHIBIT = T3;
+CONFIG PROHIBIT = T19;
+CONFIG PROHIBIT = T20;
+CONFIG PROHIBIT = U9;
+CONFIG PROHIBIT = U12;
+CONFIG PROHIBIT = U13;
+CONFIG PROHIBIT = U14;
+CONFIG PROHIBIT = U17;
+CONFIG PROHIBIT = V11;
+CONFIG PROHIBIT = V12;
+CONFIG PROHIBIT = V15;
+CONFIG PROHIBIT = W7;
+CONFIG PROHIBIT = W8;
+CONFIG PROHIBIT = W11;
+CONFIG PROHIBIT = W12;
+CONFIG PROHIBIT = W15;
+CONFIG PROHIBIT = W18;
+CONFIG PROHIBIT = Y4;
+CONFIG PROHIBIT = Y7;
+CONFIG PROHIBIT = Y11;
+CONFIG PROHIBIT = Y12;
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.prj b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.prj
new file mode 100644
index 0000000..24120d5
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.prj
@@ -0,0 +1,19 @@
+vhdl work ../top.vhd
+vhdl zpu ../../../zpu_pkg.vhdl
+vhdl zpu ../../../zpu_small.vhdl
+vhdl zpu ../../../zpu_medium.vhdl
+vhdl zpu ../../../roms/rom_pkg.vhdl
+#vhdl zpu ../../../roms/hello_dbram.vhdl
+#vhdl zpu ../../../roms/hello_bram.vhdl
+vhdl zpu ../../../roms/dmips_dbram.vhdl
+vhdl zpu ../../../roms/dmips_bram.vhdl
+vhdl zpu ../../../helpers/zpu_small1.vhdl
+vhdl zpu ../../../helpers/zpu_med1.vhdl
+vhdl zpu ../../../devices/txt_util.vhdl
+vhdl zpu ../../../devices/phi_io.vhdl
+vhdl zpu ../../../devices/timer.vhdl
+vhdl zpu ../../../devices/gpio.vhdl
+vhdl zpu ../../../devices/rx_unit.vhdl
+vhdl zpu ../../../devices/tx_unit.vhdl
+vhdl zpu ../../../devices/br_gen.vhdl
+vhdl zpu ../../../devices/trace.vhdl
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.ut b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.ut
new file mode 100644
index 0000000..765a6f3
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.ut
@@ -0,0 +1,29 @@
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g ConfigRate:6
+-g CclkPin:PullUp
+-g M0Pin:PullUp
+-g M1Pin:PullUp
+-g M2Pin:PullUp
+-g ProgPin:PullUp
+-g DonePin:PullUp
+-g HswapenPin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g DCMShutdown:Disable
+-g DCIUpdateMode:AsRequired
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Match_cycle:Auto
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.xst b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.xst
new file mode 100644
index 0000000..14873ea
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.xst
@@ -0,0 +1,56 @@
+set -tmpdir "tmp"
+set -xsthdpdir "xst"
+run
+-ifn ../synthesis_config/top.prj
+-ifmt mixed
+-ofn top
+-ofmt NGC
+-p xc3s1000-4-fg456
+-top top
+-opt_mode Speed
+-opt_level 1
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract Yes
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-auto_bram_packing NO
+-mux_extract Yes
+-resource_sharing YES
+-async_to_sync NO
+-mult_style Auto
+-iobuf YES
+-max_fanout 500
+-bufg 8
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Yes
+-use_sync_set Yes
+-use_sync_reset Yes
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top.vhd b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top.vhd
new file mode 100644
index 0000000..4a93c4f
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top.vhd
@@ -0,0 +1,372 @@
+-- top module of
+-- Altium LiveDesign Board
+--
+-- using following external connections:
+-- test button as reset
+-- LEDs and 7 segment for output
+-- RS232
+--
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library zpu;
+use zpu.zpupkg.all; -- zpu_dbgo_t
+
+library unisim;
+use unisim.vcomponents.dcm;
+
+
+entity top is
+ port (
+ -- pragma translate_off
+ stop_simulation : out std_logic;
+ -- pragma translate_on
+ clk_50 : in std_logic;
+ reset_n : in std_logic;
+ --
+ -- soft JTAG
+ soft_tdo : out std_logic;
+ soft_tms : in std_logic;
+ soft_tdi : in std_logic;
+ soft_tck : in std_logic;
+ --
+ -- SRAM 0 (256k x 16) pin connections
+ sram0_a : out std_logic_vector(18 downto 0);
+ sram0_d : inout std_logic_vector(15 downto 0);
+ sram0_lb_n : out std_logic;
+ sram0_ub_n : out std_logic;
+ sram0_cs_n : out std_logic; -- chip select
+ sram0_we_n : out std_logic; -- write-enable
+ sram0_oe_n : out std_logic; -- output enable
+ --
+ -- SRAM 1 (256k x 16) pin connections
+ sram1_a : out std_logic_vector(18 downto 0);
+ sram1_d : inout std_logic_vector(15 downto 0);
+ sram1_lb_n : out std_logic;
+ sram1_ub_n : out std_logic;
+ sram1_cs_n : out std_logic; -- chip select
+ sram1_we_n : out std_logic; -- write-enable
+ sram1_oe_n : out std_logic; -- output enable
+ --
+ -- RS232
+ rs232_rx : in std_logic;
+ rs232_tx : out std_logic;
+ rs232_cts : in std_logic;
+ rs232_rts : out std_logic;
+ --
+ -- PS2 connectors
+ mouse_clk : inout std_logic;
+ mouse_data : inout std_logic;
+ kbd_clk : inout std_logic;
+ kbd_data : inout std_logic;
+ --
+ -- vga output
+ vga_red : out std_logic_vector(7 downto 5);
+ vga_green : out std_logic_vector(7 downto 5);
+ vga_blue : out std_logic_vector(7 downto 5);
+ vga_hsync : out std_logic;
+ vga_vsync : out std_logic;
+ --
+ -- Audio out
+ audio_r : out std_logic;
+ audio_l : out std_logic;
+ --
+ -- GPIOs
+ switch_n : in std_logic_vector(7 downto 0);
+ button_n : in std_logic_vector(5 downto 0);
+ led : out std_logic_vector(7 downto 0);
+ --
+ -- seven segment display
+ dig0_seg : out std_logic_vector(7 downto 0);
+ dig1_seg : out std_logic_vector(7 downto 0);
+ dig2_seg : out std_logic_vector(7 downto 0);
+ dig3_seg : out std_logic_vector(7 downto 0);
+ dig4_seg : out std_logic_vector(7 downto 0);
+ dig5_seg : out std_logic_vector(7 downto 0);
+ --
+ -- User Header
+ header_a : inout std_logic_vector(19 downto 2);
+ header_b : inout std_logic_vector(19 downto 2)
+ );
+end entity top;
+
+
+architecture rtl of top is
+
+
+ ---------------------------
+ -- type declarations
+ type zpu_type is (zpu_small, zpu_medium);
+
+ ---------------------------
+ -- constant declarations
+ constant zpu_flavour : zpu_type := zpu_medium; -- choose your flavour HERE
+ -- modify frequency here
+ constant clk_multiply : positive := 3; -- 9 for small, 3 for medium
+ constant clk_divide : positive := 2; -- 5 for small, 2 for medium
+ --
+ constant word_size_c : natural := 32; -- 32 bits data path
+ constant addr_w_c : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O
+
+ constant clk_frequency : positive := 50; -- input frequency for correct calculation
+
+
+ ---------------------------
+ -- component declarations
+ component zpu_small1 is
+ generic (
+ word_size : natural := 32; -- 32 bits data path
+ d_care_val : std_logic := '0'; -- Fill value
+ clk_freq : positive := 50; -- 50 MHz clock
+ brate : positive := 115200; -- RS232 baudrate
+ addr_w : natural := 16; -- 16 bits address space=64 kB, 32 kB I/O
+ bram_w : natural := 15 -- 15 bits RAM space=32 kB
+ );
+ port (
+ clk_i : in std_logic; -- CPU clock
+ rst_i : in std_logic; -- Reset
+ break_o : out std_logic; -- Break executed
+ dbg_o : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o : out std_logic; -- UART Tx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end component zpu_small1;
+
+ component zpu_med1 is
+ generic(
+ word_size : natural := 32; -- 32 bits data path
+ d_care_val : std_logic := '0'; -- Fill value
+ clk_freq : positive := 50; -- 50 MHz clock
+ brate : positive := 115200; -- RS232 baudrate
+ addr_w : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O
+ bram_w : natural := 15 -- 15 bits RAM space=32 kB
+ );
+ port(
+ clk_i : in std_logic; -- CPU clock
+ rst_i : in std_logic; -- Reset
+ break_o : out std_logic; -- Break executed
+ dbg_o : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o : out std_logic; -- UART Tx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end component zpu_med1;
+
+
+ ---------------------------
+ -- signal declarations
+ signal dcm_i0_clk0 : std_ulogic;
+ signal dcm_i0_clkfx : std_ulogic;
+ signal clk_fb : std_ulogic;
+ signal clk : std_ulogic;
+ --
+ signal reset_shift_reg : std_ulogic_vector(3 downto 0);
+ signal reset_sync : std_ulogic;
+ --
+ signal zpu_i0_dbg : zpu_dbgo_t; -- Debug info
+ signal zpu_i0_break : std_logic;
+ --
+ signal gpio_in : std_logic_vector(31 downto 0) := (others => '0');
+ signal zpu_i0_gpio_out : std_logic_vector(31 downto 0);
+ signal zpu_i0_gpio_dir : std_logic_vector(31 downto 0);
+
+
+begin
+
+ -- default output drivers
+ -- to pass bitgen DRC
+ -- outputs used by design are commented
+ soft_tdo <= '1';
+ --
+ sram0_a <= (others => '1');
+ sram0_d <= (others => 'Z');
+ sram0_lb_n <= '1';
+ sram0_ub_n <= '1';
+ sram0_cs_n <= '1';
+ sram0_we_n <= '1';
+ sram0_oe_n <= '1';
+ --
+ sram1_a <= (others => '1');
+ sram1_d <= (others => 'Z');
+ sram1_lb_n <= '1';
+ sram1_ub_n <= '1';
+ sram1_cs_n <= '1';
+ sram1_we_n <= '1';
+ sram1_oe_n <= '1';
+ --
+ --rs232_tx <= '1';
+ rs232_rts <= '1';
+ --
+ mouse_clk <= 'Z';
+ mouse_data <= 'Z';
+ kbd_clk <= 'Z';
+ kbd_data <= 'Z';
+ --
+ vga_red <= (others => '1');
+ vga_green <= (others => '1');
+ vga_blue <= (others => '1');
+ vga_hsync <= '1';
+ vga_vsync <= '1';
+ --
+ audio_r <= '0';
+ audio_l <= '0';
+ --
+ --led <= (others => '0');
+ --
+ --dig0_seg <= (others => '0');
+ --dig1_seg <= (others => '0');
+ dig2_seg <= (others => '0');
+ dig3_seg <= (others => '0');
+ dig4_seg <= (others => '0');
+ dig5_seg <= (others => '0');
+ --
+ header_a <= (others => 'Z');
+ header_b <= (others => 'Z');
+
+
+ -- digital clock manager (DCM)
+ -- to generate higher/other system clock frequencys
+ dcm_i0 : dcm
+ generic map (
+ startup_wait => true, -- wait with DONE till locked
+ clkfx_multiply => clk_multiply,
+ clkfx_divide => clk_divide,
+ clk_feedback => "1X"
+ )
+ port map (
+ clkin => clk_50,
+ clk0 => dcm_i0_clk0,
+ clkfx => dcm_i0_clkfx,
+ clkfb => clk_fb
+ );
+
+ clk_fb <= dcm_i0_clk0;
+ clk <= dcm_i0_clkfx;
+
+
+ -- reset synchronizer
+ -- generate synchronous reset
+ reset_synchronizer : process(clk, reset_n)
+ begin
+ if reset_n = '0' then
+ reset_shift_reg <= (others => '1');
+ elsif rising_edge(clk) then
+ reset_shift_reg <= reset_shift_reg(reset_shift_reg'high-1 downto 0) & '0';
+ end if;
+ end process;
+ reset_sync <= reset_shift_reg(reset_shift_reg'high);
+
+
+ -- select instance of zpu
+ zpu_i0_small : if zpu_flavour = zpu_small generate
+ zpu_i0 : zpu_small1
+ generic map (
+ addr_w => addr_w_c,
+ word_size => word_size_c,
+ clk_freq => clk_frequency * clk_multiply / clk_divide
+ )
+ port map (
+ clk_i => clk, -- : in std_logic; -- CPU clock
+ rst_i => reset_sync, -- : in std_logic; -- Reset
+ break_o => zpu_i0_break, -- : out std_logic; -- Break executed
+ dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o => rs232_tx, -- : out std_logic; -- UART Tx
+ rs232_rx_i => rs232_rx, -- : in std_logic -- UART Rx
+ gpio_in => gpio_in, -- : in std_logic_vector(31 downto 0);
+ gpio_out => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
+ gpio_dir => zpu_i0_gpio_dir -- : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end generate zpu_i0_small;
+
+ zpu_i0_medium : if zpu_flavour = zpu_medium generate
+ zpu_i0 : zpu_med1
+ generic map (
+ addr_w => addr_w_c,
+ word_size => word_size_c,
+ clk_freq => clk_frequency * clk_multiply / clk_divide
+ )
+ port map (
+ clk_i => clk, -- : in std_logic; -- CPU clock
+ rst_i => reset_sync, -- : in std_logic; -- Reset
+ break_o => zpu_i0_break, -- : out std_logic; -- Break executed
+ dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o => rs232_tx, -- : out std_logic; -- UART Tx
+ rs232_rx_i => rs232_rx, -- : in std_logic -- UART Rx
+ gpio_in => gpio_in, -- : in std_logic_vector(31 downto 0);
+ gpio_out => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
+ gpio_dir => zpu_i0_gpio_dir -- : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end generate zpu_i0_medium;
+
+
+ -- pragma translate_off
+ stop_simulation <= zpu_i0_break;
+
+
+ trace_mod : trace
+ generic map (
+ addr_w => addr_w_c,
+ word_size => word_size_c,
+ log_file => "zpu_trace.log"
+ )
+ port map (
+ clk_i => clk,
+ dbg_i => zpu_i0_dbg,
+ stop_i => zpu_i0_break,
+ busy_i => '0'
+ );
+ -- pragma translate_on
+
+
+ -- assign GPIOs
+ --
+ -- bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
+ --
+ -- in header_a(19.........12) -- -- -- -- -- -- -- --
+ -- out header_a(19.........12) dig1_seg(7...........0)
+ --
+ --
+ -- bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+ --
+ -- in switch_n(7...........0) -- -- button_n(5....0)
+ -- out dig0_seg(7...........0) led(7................0)
+ --
+
+ gpio_in(31 downto 24) <= header_a(19 downto 12);
+ gpio_in(15 downto 8) <= switch_n;
+ gpio_in( 5 downto 0) <= button_n;
+
+ -- 3-state buffers for some headers
+ header_a(19) <= zpu_i0_gpio_out(31) when zpu_i0_gpio_dir(31) = '0' else 'Z';
+ header_a(18) <= zpu_i0_gpio_out(30) when zpu_i0_gpio_dir(30) = '0' else 'Z';
+ header_a(17) <= zpu_i0_gpio_out(29) when zpu_i0_gpio_dir(29) = '0' else 'Z';
+ header_a(16) <= zpu_i0_gpio_out(28) when zpu_i0_gpio_dir(28) = '0' else 'Z';
+ header_a(15) <= zpu_i0_gpio_out(27) when zpu_i0_gpio_dir(27) = '0' else 'Z';
+ header_a(14) <= zpu_i0_gpio_out(26) when zpu_i0_gpio_dir(26) = '0' else 'Z';
+ header_a(13) <= zpu_i0_gpio_out(25) when zpu_i0_gpio_dir(25) = '0' else 'Z';
+ header_a(12) <= zpu_i0_gpio_out(24) when zpu_i0_gpio_dir(24) = '0' else 'Z';
+
+ -- outputs
+ dig1_seg <= zpu_i0_gpio_out(23 downto 16);
+ dig0_seg <= zpu_i0_gpio_out(15 downto 8);
+
+ -- switch on all LEDs in case of break
+ process
+ begin
+ wait until rising_edge(clk);
+ led <= zpu_i0_gpio_out(7 downto 0);
+ if zpu_i0_break = '1' then
+ led <= (others => '1');
+ end if;
+ end process;
+
+
+end architecture rtl;
+
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top_tb.vhd b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top_tb.vhd
new file mode 100644
index 0000000..e42fc20
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top_tb.vhd
@@ -0,0 +1,194 @@
+-- testbench for
+-- Altium LiveDesign Board
+--
+-- includes "model" for clock generation
+-- simulate press on test/reset as reset
+--
+-- place models for external components (SRAM, PS2) in this file
+--
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity top_tb is
+end entity top_tb;
+
+architecture testbench of top_tb is
+
+ ---------------------------
+ -- constant declarations
+ constant clk_period : time := 1 sec / 50_000_000; -- 50 MHz
+
+
+ ---------------------------
+ -- signal declarations
+ signal simulation_run : boolean := true;
+ signal tb_stop_simulation : std_logic;
+ --
+ signal tb_clk : std_logic := '0';
+ signal tb_reset_n : std_logic;
+ --
+ -- soft JTAG
+ signal tb_soft_tdo : std_logic;
+ signal tb_soft_tms : std_logic := '1';
+ signal tb_soft_tdi : std_logic := '1';
+ signal tb_soft_tck : std_logic := '1';
+ --
+ -- SRAM 0 (256k x 16) pin connections
+ signal tb_sram0_a : std_logic_vector(18 downto 0);
+ signal tb_sram0_d : std_logic_vector(15 downto 0) := (others => 'Z');
+ signal tb_sram0_lb_n : std_logic;
+ signal tb_sram0_ub_n : std_logic;
+ signal tb_sram0_cs_n : std_logic; -- chip select
+ signal tb_sram0_we_n : std_logic; -- write-enable
+ signal tb_sram0_oe_n : std_logic; -- output enable
+ --
+ -- SRAM 1 (256k x 16) pin connections
+ signal tb_sram1_a : std_logic_vector(18 downto 0);
+ signal tb_sram1_d : std_logic_vector(15 downto 0) := (others => 'Z');
+ signal tb_sram1_lb_n : std_logic;
+ signal tb_sram1_ub_n : std_logic;
+ signal tb_sram1_cs_n : std_logic; -- chip select
+ signal tb_sram1_we_n : std_logic; -- write-enable
+ signal tb_sram1_oe_n : std_logic; -- output enable
+ --
+ -- RS232
+ signal tb_rs232_rx : std_logic := '1';
+ signal tb_rs232_tx : std_logic;
+ signal tb_rs232_cts : std_logic := '1';
+ signal tb_rs232_rts : std_logic;
+ --
+ -- PS2 connectors
+ signal tb_mouse_clk : std_logic := 'Z';
+ signal tb_mouse_data : std_logic := 'Z';
+ signal tb_kbd_clk : std_logic := 'Z';
+ signal tb_kbd_data : std_logic := 'Z';
+ --
+ -- vga output
+ signal tb_vga_red : std_logic_vector(7 downto 5);
+ signal tb_vga_green : std_logic_vector(7 downto 5);
+ signal tb_vga_blue : std_logic_vector(7 downto 5);
+ signal tb_vga_hsync : std_logic;
+ signal tb_vga_vsync : std_logic;
+ --
+ -- Audio out
+ signal tb_audio_r : std_logic;
+ signal tb_audio_l : std_logic;
+ --
+ -- GPIOs
+ signal tb_switch_n : std_logic_vector(7 downto 0) := (others => '1');
+ signal tb_button_n : std_logic_vector(5 downto 0) := (others => '1');
+ signal tb_led : std_logic_vector(7 downto 0);
+ --
+ -- seven segment display
+ signal tb_dig0_seg : std_logic_vector(7 downto 0);
+ signal tb_dig1_seg : std_logic_vector(7 downto 0);
+ signal tb_dig2_seg : std_logic_vector(7 downto 0);
+ signal tb_dig3_seg : std_logic_vector(7 downto 0);
+ signal tb_dig4_seg : std_logic_vector(7 downto 0);
+ signal tb_dig5_seg : std_logic_vector(7 downto 0);
+ --
+ -- User Header A
+ signal tb_header_a : std_logic_vector(19 downto 2) := (others => 'Z');
+ signal tb_header_b : std_logic_vector(19 downto 2) := (others => 'Z');
+
+begin
+
+ -- generate clock
+ tb_clk <= not tb_clk after clk_period / 2 when simulation_run;
+
+ -- generate reset
+ tb_reset_n <= '0', '1' after 6.66 * clk_period;
+
+
+ -- simulate keypress
+ tb_button_n(2) <= '1', '0' after 50 us, '1' after 52 us;
+
+ -- dut
+ top_i0 : entity work.top
+ port map (
+ stop_simulation => tb_stop_simulation, -- : out std_logic;
+ --
+ clk_50 => tb_clk, -- : in std_logic;
+ reset_n => tb_reset_n, -- : in std_logic;
+ --
+ -- soft JTAG
+ soft_tdo => tb_soft_tdo, -- : out std_logic;
+ soft_tms => tb_soft_tms, -- : in std_logic;
+ soft_tdi => tb_soft_tdi, -- : in std_logic;
+ soft_tck => tb_soft_tck, -- : in std_logic;
+ --
+ -- SRAM 0 (256k x 16) pin connections
+ sram0_a => tb_sram0_a, -- : out std_logic_vector(18 downto 0);
+ sram0_d => tb_sram0_d, -- : inout std_logic_vector(15 downto 0);
+ sram0_lb_n => tb_sram0_lb_n, -- : out std_logic;
+ sram0_ub_n => tb_sram0_ub_n, -- : out std_logic;
+ sram0_cs_n => tb_sram0_cs_n, -- : out std_logic; -- chip select
+ sram0_we_n => tb_sram0_we_n, -- : out std_logic; -- write-enable
+ sram0_oe_n => tb_sram0_oe_n, -- : out std_logic; -- output enable
+ --
+ -- SRAM 1 (256k x 16) pin connections
+ sram1_a => tb_sram1_a, -- : out std_logic_vector(18 downto 0);
+ sram1_d => tb_sram1_d, -- : inout std_logic_vector(15 downto 0);
+ sram1_lb_n => tb_sram1_lb_n, -- : out std_logic;
+ sram1_ub_n => tb_sram1_ub_n, -- : out std_logic;
+ sram1_cs_n => tb_sram1_cs_n, -- : out std_logic; -- chip select
+ sram1_we_n => tb_sram1_we_n, -- : out std_logic; -- write-enable
+ sram1_oe_n => tb_sram1_oe_n, -- : out std_logic; -- output enable
+ --
+ -- RS232
+ rs232_rx => tb_rs232_rx, -- : in std_logic;
+ rs232_tx => tb_rs232_tx, -- : out std_logic;
+ rs232_cts => tb_rs232_cts, -- : in std_logic;
+ rs232_rts => tb_rs232_rts, -- : out std_logic;
+ --
+ -- PS2 connectors
+ mouse_clk => tb_mouse_clk, -- : inout std_logic;
+ mouse_data => tb_mouse_data, -- : inout std_logic;
+ kbd_clk => tb_kbd_clk, -- : inout std_logic;
+ kbd_data => tb_kbd_data, -- : inout std_logic;
+ --
+ -- vga output
+ vga_red => tb_vga_red, -- : out std_logic_vector(7 downto 5);
+ vga_green => tb_vga_green, -- : out std_logic_vector(7 downto 5);
+ vga_blue => tb_vga_blue, -- : out std_logic_vector(7 downto 5);
+ vga_hsync => tb_vga_hsync, -- : out std_logic;
+ vga_vsync => tb_vga_vsync, -- : out std_logic;
+ --
+ -- Audio out
+ audio_r => tb_audio_r, -- : out std_logic;
+ audio_l => tb_audio_l, -- : out std_logic;
+ --
+ -- GPIOs
+ switch_n => tb_switch_n, -- : in std_logic_vector(7 downto 0);
+ button_n => tb_button_n, -- : in std_logic_vector(5 downto 0);
+ led => tb_led, -- : out std_logic_vector(7 downto 0);
+ --
+ -- seven segment display
+ dig0_seg => tb_dig0_seg, -- : out std_logic_vector(7 downto 0);
+ dig1_seg => tb_dig1_seg, -- : out std_logic_vector(7 downto 0);
+ dig2_seg => tb_dig2_seg, -- : out std_logic_vector(7 downto 0);
+ dig3_seg => tb_dig3_seg, -- : out std_logic_vector(7 downto 0);
+ dig4_seg => tb_dig4_seg, -- : out std_logic_vector(7 downto 0);
+ dig5_seg => tb_dig5_seg, -- : out std_logic_vector(7 downto 0);
+ --
+ -- User Header
+ header_a => tb_header_a, -- : inout std_logic_vector(19 downto 2);
+ header_b => tb_header_b -- : inout std_logic_vector(19 downto 2)
+ );
+
+
+ -- check for simulation stopping
+ process (tb_stop_simulation)
+ begin
+ if tb_stop_simulation = '1' then
+ report "Simulation end." severity note;
+ simulation_run <= false;
+ end if;
+ end process;
+
+
+end architecture testbench;
+
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/clean_up.sh b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/clean_up.sh
new file mode 100755
index 0000000..3855f16
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/clean_up.sh
@@ -0,0 +1,16 @@
+#!/bin/sh
+
+# ise build stuff
+rm -rf build
+rm -f top.bit
+
+# modelsim compile stuff
+rm -rf work
+rm -rf zpu
+
+# modelsim simulation stuff
+rm -f vsim.wlf
+rm -f transcript
+rm -f zpu_trace.log
+rm -f zpu_med1_io.log
+rm -f zpu_small1_io.log
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation.sh b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation.sh
new file mode 100755
index 0000000..d525737
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation.sh
@@ -0,0 +1,49 @@
+#!/bin/sh
+
+# need project files:
+# run.do
+# wave.do
+
+# need ModelSim tools:
+# vlib
+# vcom
+# vsim
+
+
+echo "###############"
+echo "compile zpu lib"
+echo "###############"
+vlib zpu
+vcom -work zpu ../../roms/hello_dbram.vhdl
+vcom -work zpu ../../roms/hello_bram.vhdl
+#vcom -work zpu ../../roms/dmips_dbram.vhdl
+#vcom -work zpu ../../roms/dmips_bram.vhdl
+
+vcom -work zpu ../../roms/rom_pkg.vhdl
+vcom -work zpu ../../zpu_pkg.vhdl
+vcom -work zpu ../../zpu_small.vhdl
+vcom -work zpu ../../zpu_medium.vhdl
+vcom -work zpu ../../helpers/zpu_small1.vhdl
+vcom -work zpu ../../helpers/zpu_med1.vhdl
+vcom -work zpu ../../devices/txt_util.vhdl
+vcom -work zpu ../../devices/phi_io.vhdl
+vcom -work zpu ../../devices/timer.vhdl
+vcom -work zpu ../../devices/gpio.vhdl
+vcom -work zpu ../../devices/rx_unit.vhdl
+vcom -work zpu ../../devices/tx_unit.vhdl
+vcom -work zpu ../../devices/br_gen.vhdl
+vcom -work zpu ../../devices/trace.vhdl
+
+
+echo "################"
+echo "compile work lib"
+echo "################"
+vlib work
+vcom top.vhd
+vcom top_tb.vhd
+
+
+echo "###################"
+echo "start simulator gui"
+echo "###################"
+vsim -gui top_tb -do simulation_config/run.do
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/run.do b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/run.do
new file mode 100644
index 0000000..acc1710
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/run.do
@@ -0,0 +1,2 @@
+do wave.do
+run -all
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/wave.do b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/wave.do
new file mode 100644
index 0000000..d572a06
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/wave.do
@@ -0,0 +1,30 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /top_tb/tb_gpio_button(0)
+add wave -noupdate /top_tb/tb_clk_100MHz
+add wave -noupdate -divider <NULL>
+add wave -noupdate /top_tb/tb_rs232_rx
+add wave -noupdate /top_tb/tb_rs232_tx
+add wave -noupdate /top_tb/tb_rs232_rts
+add wave -noupdate /top_tb/tb_rs232_cts
+add wave -noupdate -divider Buttons
+add wave -noupdate /top_tb/tb_gpio_button
+add wave -noupdate -divider LEDs
+add wave -noupdate /top_tb/tb_gpio_led_n
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {0 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 2
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ps} {126912555 ps}
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis.sh b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis.sh
new file mode 100755
index 0000000..d8d7603
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis.sh
@@ -0,0 +1,36 @@
+#!/bin/sh
+
+# need project files:
+# top.xst
+# top.prj
+# top.ut
+
+# need Xilinx tools:
+# xst
+# ngdbuild
+# map
+# par
+# trce
+# bitgen
+
+echo "########################"
+echo "generate build directory"
+echo "########################"
+mkdir build
+cd build
+mkdir tmp
+
+echo "###############"
+echo "start processes"
+echo "###############"
+xst -ifn "../synthesis_config/top.xst" -ofn "top.syr"
+ngdbuild -dd _ngo -nt timestamp -uc ../synthesis_config/avnet-eval-xc5vfx30t.ucf -p xc5vfx30t-ff665-1 top.ngc top.ngd
+map -p xc5vfx30t-ff665-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -ir off -pr off -lc off -power off -o top_map.ncd top.ngd top.pcf
+par -w -ol high -mt off top_map.ncd top.ncd top.pcf
+trce -v 3 -s 1 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf
+bitgen -f ../synthesis_config/top.ut top.ncd
+
+echo "###########"
+echo "get bitfile"
+echo "###########"
+cp top.bit ..
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/avnet-eval-xc5vfx30t.ucf b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/avnet-eval-xc5vfx30t.ucf
new file mode 100644
index 0000000..8494af3
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/avnet-eval-xc5vfx30t.ucf
@@ -0,0 +1,482 @@
+############################################################
+# Avnet Virtex 5 FX Evaluation Board constraints file
+#
+# Familiy: Virtex5
+# Device: XC5VFX30T
+# Package: FF665
+# Speed: -1
+#
+#
+# Bank 0 3.3V
+# Bank 1 3.3V
+# Bank 2 3.3V
+# Bank 3 3.3V
+# Bank 4 2.5V or 3.3V (JP2, VIO_EXP1_DP), here 2.5V
+# Bank 11 1.8V
+# Bank 12 3.3V
+# Bank 13 1.8V
+# Bank 15 3.3V
+# Bank 16 2.5V or 3.3V (JP3, VIO_EXP1_SE), here 2.5V
+# Bank 17 1.8V
+# Bank 18 2.5V or 3.3V (JP2, VIO_EXP1_DP), here 2.5V
+
+
+############################################################
+## clock/timing constraints
+############################################################
+
+TIMESPEC "TS_clk_100" = PERIOD "clk_100" 100 MHz;
+
+
+############################################################
+## design placement constraints
+############################################################
+#
+# the following constraint are need if you want to synthesize
+# zpu_medium with 125 MHz
+#
+INST "zpu_i0_medium.zpu_i0/zpu/*" AREA_GROUP = "zpu_block";
+AREA_GROUP "zpu_block" RANGE=SLICE_X18Y0:SLICE_X55Y41;
+AREA_GROUP "zpu_block" RANGE=DSP48_X0Y0:DSP48_X0Y15;
+AREA_GROUP "zpu_block" RANGE=RAMB36_X1Y0:RAMB36_X3Y7;
+
+
+############################################################
+## pin placement constraints
+############################################################
+
+NET "clk_100MHz" LOC= E18 | IOSTANDARD = LVCMOS33 | TNM_NET = "clk_100";
+NET "clk_socket" LOC= E13 | IOSTANDARD = LVCMOS33;
+NET "user_clk_p" LOC= AB15 ;
+NET "user_clk_n" LOC= AC16 ;
+
+# RS232
+NET "RS232_RX" LOC= K8 | IOSTANDARD = LVCMOS33;
+NET "RS232_TX" LOC= L8 | IOSTANDARD = LVCMOS33;
+NET "RS232_RTS" LOC= N8 | IOSTANDARD = LVCMOS33; # Jumper J3
+NET "RS232_CTS" LOC= R8 | IOSTANDARD = LVCMOS33; # Jumper J4
+
+# RS232_USB
+NET "RS232_USB_RX" LOC= AA10 | IOSTANDARD = LVCMOS33;
+NET "RS232_USB_TX" LOC= AA19 | IOSTANDARD = LVCMOS33;
+NET "RS232_USB_reset_n" LOC= Y20 | IOSTANDARD = LVCMOS33;
+
+# GPIO LEDs, active low
+NET "GPIO_LED_n<0>" LOC= AF22 | IOSTANDARD = LVCMOS18 | PULLUP;
+NET "GPIO_LED_n<1>" LOC= AF23 | IOSTANDARD = LVCMOS18 | PULLUP;
+NET "GPIO_LED_n<2>" LOC= AF25 | IOSTANDARD = LVCMOS18 | PULLUP;
+NET "GPIO_LED_n<3>" LOC= AE25 | IOSTANDARD = LVCMOS18 | PULLUP;
+NET "GPIO_LED_n<4>" LOC= AD25 | IOSTANDARD = LVCMOS18 | PULLUP;
+NET "GPIO_LED_n<5>" LOC= AE26 | IOSTANDARD = LVCMOS18 | PULLUP;
+NET "GPIO_LED_n<6>" LOC= AD26 | IOSTANDARD = LVCMOS18 | PULLUP;
+NET "GPIO_LED_n<7>" LOC= AC26 | IOSTANDARD = LVCMOS18 | PULLUP;
+
+# GPIO DIP_Switches
+NET "GPIO_DIPswitch<0>" LOC= AD13 | IOSTANDARD = LVCMOS18;
+NET "GPIO_DIPswitch<1>" LOC= AE13 | IOSTANDARD = LVCMOS18;
+NET "GPIO_DIPswitch<2>" LOC= AF13 | IOSTANDARD = LVCMOS18;
+NET "GPIO_DIPswitch<3>" LOC= AD15 | IOSTANDARD = LVCMOS18;
+NET "GPIO_DIPswitch<4>" LOC= AD14 | IOSTANDARD = LVCMOS18;
+NET "GPIO_DIPswitch<5>" LOC= AF14 | IOSTANDARD = LVCMOS18;
+NET "GPIO_DIPswitch<6>" LOC= AE15 | IOSTANDARD = LVCMOS18;
+NET "GPIO_DIPswitch<7>" LOC= AF15 | IOSTANDARD = LVCMOS18;
+
+# Push Buttons
+NET "GPIO_button<0>" LOC= AF20 | IOSTANDARD = LVCMOS18 | PULLUP; #PB1
+NET "GPIO_button<1>" LOC= AE20 | IOSTANDARD = LVCMOS18 | PULLUP; #PB2
+NET "GPIO_button<2>" LOC= AD19 | IOSTANDARD = LVCMOS18 | PULLUP; #PB3
+NET "GPIO_button<3>" LOC= AD20 | IOSTANDARD = LVCMOS18 | PULLUP; #PB4
+
+# FLASH_8Mx16
+NET "FLASH_A<31>" LOC= Y11 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<30>" LOC= H9 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<29>" LOC= G10 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<28>" LOC= H21 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<27>" LOC= G20 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<26>" LOC= H11 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<25>" LOC= G11 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<24>" LOC= H19 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<23>" LOC= H18 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<22>" LOC= G12 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<21>" LOC= F13 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<20>" LOC= G19 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<19>" LOC= F18 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<18>" LOC= F14 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<17>" LOC= F15 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<16>" LOC= F17 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<15>" LOC= G17 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<14>" LOC= G14 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<13>" LOC= H13 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<12>" LOC= G16 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<11>" LOC= G15 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<10>" LOC= Y18 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<9>" LOC= AA18 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<8>" LOC= Y10 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<7>" LOC= W11 | IOSTANDARD = LVCMOS33;
+NET "FLASH_DQ<0>" LOC= AA15 | IOSTANDARD = LVCMOS33;
+NET "FLASH_DQ<1>" LOC= Y15 | IOSTANDARD = LVCMOS33;
+NET "FLASH_DQ<2>" LOC= W14 | IOSTANDARD = LVCMOS33;
+NET "FLASH_DQ<3>" LOC= Y13 | IOSTANDARD = LVCMOS33;
+NET "FLASH_DQ<4>" LOC= W16 | IOSTANDARD = LVCMOS33;
+NET "FLASH_DQ<5>" LOC= Y16 | IOSTANDARD = LVCMOS33;
+NET "FLASH_DQ<6>" LOC= AA14 | IOSTANDARD = LVCMOS33;
+NET "FLASH_DQ<7>" LOC= AA13 | IOSTANDARD = LVCMOS33;
+NET "FLASH_DQ<8>" LOC= AB12 | IOSTANDARD = LVCMOS25; # with level shifter
+NET "FLASH_DQ<9>" LOC= AC11 | IOSTANDARD = LVCMOS25; # with level shifter
+NET "FLASH_DQ<10>" LOC= AB20 | IOSTANDARD = LVCMOS25; # with level shifter
+NET "FLASH_DQ<11>" LOC= AB21 | IOSTANDARD = LVCMOS25; # with level shifter
+NET "FLASH_DQ<12>" LOC= AB11 | IOSTANDARD = LVCMOS25; # with level shifter
+NET "FLASH_DQ<13>" LOC= AB10 | IOSTANDARD = LVCMOS25; # with level shifter
+NET "FLASH_DQ<14>" LOC= AA20 | IOSTANDARD = LVCMOS25; # with level shifter
+NET "FLASH_DQ<15>" LOC= Y21 | IOSTANDARD = LVCMOS25; # with level shifter
+NET "FLASH_WEN" LOC= AA17 | IOSTANDARD = LVCMOS33;
+NET "FLASH_OEN<0>" LOC= AA12 | IOSTANDARD = LVCMOS33;
+NET "FLASH_CEN<0>" LOC= Y12 | IOSTANDARD = LVCMOS33;
+NET "FLASH_rp_n" LOC= D13 | IOSTANDARD = LVCMOS33;
+NET "FLASH_byte_n" LOC= Y17 | IOSTANDARD = LVCMOS33;
+NET "FLASH_adv_n" LOC= F19 | IOSTANDARD = LVCMOS33;
+NET "FLASH_clk" LOC= E12 | IOSTANDARD = LVCMOS33;
+NET "FLASH_wait" LOC= D16 | IOSTANDARD = LVCMOS33;
+
+# DDR2_SDRAM_16Mx32
+NET "DDR2_ODT<0>" LOC= AF24 | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<0>" LOC= U25 | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<1>" LOC= T25 | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<2>" LOC= T24 | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<3>" LOC= T23 | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<4>" LOC= U24 | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<5>" LOC= V24 | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<6>" LOC= Y23 | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<7>" LOC= W23 | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<8>" LOC= AA25 | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<9>" LOC= AB26 | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<10>" LOC= AB25 | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<11>" LOC= AB24 | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<12>" LOC= AA23 | IOSTANDARD = SSTL18_II;
+NET "DDR2_BA<0>" LOC= U21 | IOSTANDARD = SSTL18_II;
+NET "DDR2_BA<1>" LOC= V22 | IOSTANDARD = SSTL18_II;
+NET "DDR2_CAS_N" LOC= W24 | IOSTANDARD = SSTL18_II;
+NET "DDR2_CKE" LOC= T22 | IOSTANDARD = SSTL18_II;
+NET "DDR2_CS_N" LOC= AD24 | IOSTANDARD = SSTL18_II;
+NET "DDR2_RAS_N" LOC= Y22 | IOSTANDARD = SSTL18_II;
+NET "DDR2_WE_N" LOC= AA22 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DM<0>" LOC= U26 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DM<1>" LOC= N24 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DM<2>" LOC= M24 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DM<3>" LOC= M25 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQS_P<0>" LOC= W26 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQS_P<1>" LOC= L23 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQS_P<2>" LOC= K22 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQS_P<3>" LOC= J21 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQS_N<0>" LOC= W25 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQS_N<1>" LOC= L22 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQS_N<2>" LOC= K23 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQS_N<3>" LOC= K21 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<0>" LOC= R22 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<1>" LOC= R23 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<2>" LOC= P23 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<3>" LOC= P24 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<4>" LOC= R25 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<5>" LOC= P25 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<6>" LOC= R26 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<7>" LOC= P26 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<8>" LOC= M26 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<9>" LOC= N26 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<10>" LOC= K25 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<11>" LOC= L24 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<12>" LOC= K26 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<13>" LOC= J26 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<14>" LOC= J25 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<15>" LOC= N21 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<16>" LOC= M21 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<17>" LOC= J23 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<18>" LOC= H23 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<19>" LOC= H22 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<20>" LOC= G22 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<21>" LOC= F22 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<22>" LOC= F23 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<23>" LOC= E23 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<24>" LOC= G24 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<25>" LOC= F24 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<26>" LOC= G25 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<27>" LOC= H26 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<28>" LOC= G26 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<29>" LOC= F25 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<30>" LOC= E25 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<31>" LOC= E26 | IOSTANDARD = SSTL18_II;
+NET "DDR2_CK_p<0>" LOC= V21 | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_CK_p<1>" LOC= N22 | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_CK_n<0>" LOC= W21 | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_CK_n<1>" LOC= M22 | IOSTANDARD = DIFF_SSTL18_II;
+
+# Ethernet MAC
+NET "GMII_txer" LOC= A22 | IOSTANDARD = LVCMOS33;
+NET "GMII_tx_clk" LOC= E17 | IOSTANDARD = LVCMOS33 | PERIOD=40000 ps;
+NET "GMII_rx_clk" LOC= E20 | IOSTANDARD = LVCMOS33 | PERIOD=40000 ps;
+NET "GMII_gtc_clk" LOC= A19 | IOSTANDARD = LVCMOS33;
+NET "GMII_crs" LOC= A25 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET "GMII_dv" LOC= C21 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET "GMII_rx_data<0>" LOC= D24 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET "GMII_rx_data<1>" LOC= D23 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET "GMII_rx_data<2>" LOC= D21 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET "GMII_rx_data<3>" LOC= C26 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET "GMII_rx_data<4>" LOC= D20 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET "GMII_rx_data<5>" LOC= C23 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET "GMII_rx_data<6>" LOC= B25 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET "GMII_rx_data<7>" LOC= C22 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET "GMII_col" LOC= A24 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET "GMII_rx_er" LOC= B24 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET "GMII_tx_en" LOC= A23 | IOSTANDARD = LVCMOS33;
+NET "GMII_tx_data<0>" LOC= D19 | IOSTANDARD = LVCMOS33;
+NET "GMII_tx_data<1>" LOC= C19 | IOSTANDARD = LVCMOS33;
+NET "GMII_tx_data<2>" LOC= A20 | IOSTANDARD = LVCMOS33;
+NET "GMII_tx_data<3>" LOC= B20 | IOSTANDARD = LVCMOS33;
+NET "GMII_tx_data<4>" LOC= B19 | IOSTANDARD = LVCMOS33;
+NET "GMII_tx_data<5>" LOC= A15 | IOSTANDARD = LVCMOS33;
+NET "GMII_tx_data<6>" LOC= B22 | IOSTANDARD = LVCMOS33;
+NET "GMII_tx_data<7>" LOC= B21 | IOSTANDARD = LVCMOS33;
+NET "GBE_rst_n" LOC= B26 | IOSTANDARD = LVCMOS33;
+NET "GBE_mdc" LOC= D26 | IOSTANDARD = LVCMOS33;
+NET "GBE_mdio" LOC= D25 | IOSTANDARD = LVCMOS33;
+NET "GBE_int_n" LOC= C24 | IOSTANDARD = LVCMOS33;
+NET "GBE_mclk" LOC= F20 | IOSTANDARD = LVCMOS33;
+
+# SysACE CompactFlash
+NET "SAM_CLK" LOC= F12 | IOSTANDARD = LVCMOS33;
+NET "SAM_A<0>" LOC= Y5 | IOSTANDARD = LVCMOS33;
+NET "SAM_A<1>" LOC= V7 | IOSTANDARD = LVCMOS33;
+NET "SAM_A<2>" LOC= W6 | IOSTANDARD = LVCMOS33;
+NET "SAM_A<3>" LOC= W5 | IOSTANDARD = LVCMOS33;
+NET "SAM_A<4>" LOC= K6 | IOSTANDARD = LVCMOS33;
+NET "SAM_A<5>" LOC= J5 | IOSTANDARD = LVCMOS33;
+NET "SAM_A<6>" LOC= J6 | IOSTANDARD = LVCMOS33;
+NET "SAM_D<0>" LOC= F5 | IOSTANDARD = LVCMOS33;
+NET "SAM_D<1>" LOC= U7 | IOSTANDARD = LVCMOS33;
+NET "SAM_D<2>" LOC= V6 | IOSTANDARD = LVCMOS33;
+NET "SAM_D<3>" LOC= U5 | IOSTANDARD = LVCMOS33;
+NET "SAM_D<4>" LOC= U6 | IOSTANDARD = LVCMOS33;
+NET "SAM_D<5>" LOC= T5 | IOSTANDARD = LVCMOS33;
+NET "SAM_D<6>" LOC= T7 | IOSTANDARD = LVCMOS33;
+NET "SAM_D<7>" LOC= R6 | IOSTANDARD = LVCMOS33;
+NET "SAM_D<8>" LOC= R7 | IOSTANDARD = LVCMOS33;
+NET "SAM_D<9>" LOC= R5 | IOSTANDARD = LVCMOS33;
+NET "SAM_D<10>" LOC= P6 | IOSTANDARD = LVCMOS33;
+NET "SAM_D<11>" LOC= P8 | IOSTANDARD = LVCMOS33;
+NET "SAM_D<12>" LOC= N6 | IOSTANDARD = LVCMOS33;
+NET "SAM_D<13>" LOC= M7 | IOSTANDARD = LVCMOS33;
+NET "SAM_D<14>" LOC= K5 | IOSTANDARD = LVCMOS33;
+NET "SAM_D<15>" LOC= L7 | IOSTANDARD = LVCMOS33;
+NET "SAM_CEN" LOC= G4 | IOSTANDARD = LVCMOS33;
+NET "SAM_OEN" LOC= Y6 | IOSTANDARD = LVCMOS33;
+NET "SAM_WEN" LOC= Y4 | IOSTANDARD = LVCMOS33;
+NET "SAM_MPIRQ" LOC= H4 | IOSTANDARD = LVCMOS33;
+NET "SAM_BRDY" LOC= G5 | IOSTANDARD = LVCMOS33;
+NET "SAM_RESET_n" LOC= H6 | IOSTANDARD = LVCMOS33;
+
+# Expansion Header
+NET "EXP1_SE_IO<0>" LOC= A8 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<1>" LOC= A12 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<2>" LOC= B10 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<3>" LOC= A10 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<4>" LOC= B9 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<5>" LOC= A9 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<6>" LOC= A5 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<7>" LOC= B11 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<8>" LOC= B6 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<9>" LOC= A7 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<10>" LOC= D8 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<11>" LOC= C9 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<12>" LOC= B7 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<13>" LOC= A4 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<14>" LOC= B5 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<15>" LOC= C8 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<16>" LOC= C7 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<17>" LOC= A3 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<18>" LOC= C6 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<19>" LOC= B4 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<20>" LOC= D6 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<21>" LOC= D9 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<22>" LOC= E8 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<23>" LOC= D5 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<24>" LOC= F7 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<25>" LOC= E7 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<26>" LOC= E5 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<27>" LOC= E6 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<28>" LOC= F8 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<29>" LOC= H7 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<30>" LOC= G7 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<31>" LOC= H8 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<32>" LOC= G9 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<33>" LOC= J8 | IOSTANDARD = LVCMOS25;
+NET "EXP1_DIFF_P<0>" LOC= AF9 ;
+NET "EXP1_DIFF_N<0>" LOC= AF10 ;
+NET "EXP1_DIFF_P<1>" LOC= AF12 ;
+NET "EXP1_DIFF_N<1>" LOC= AE12 ;
+NET "EXP1_DIFF_P<2>" LOC= AF7 ;
+NET "EXP1_DIFF_N<2>" LOC= AF8 ;
+NET "EXP1_DIFF_P<3>" LOC= AE11 ;
+NET "EXP1_DIFF_N<3>" LOC= AD11 ;
+NET "EXP1_DIFF_P<4>" LOC= AF4 ;
+NET "EXP1_DIFF_N<4>" LOC= AF3 ;
+NET "EXP1_DIFF_P<5>" LOC= AD10 ;
+NET "EXP1_DIFF_N<5>" LOC= AE10 ;
+NET "EXP1_DIFF_P<6>" LOC= AE8 ;
+NET "EXP1_DIFF_N<6>" LOC= AE7 ;
+NET "EXP1_DIFF_P<7>" LOC= AC8 ;
+NET "EXP1_DIFF_N<7>" LOC= AD8 ;
+NET "EXP1_DIFF_P<8>" LOC= AD9 ;
+NET "EXP1_DIFF_N<8>" LOC= AC9 ;
+NET "EXP1_DIFF_P<9>" LOC= AE6 ;
+NET "EXP1_DIFF_N<9>" LOC= AF5 ;
+NET "EXP1_DIFF_P<10>" LOC= AB6 ;
+NET "EXP1_DIFF_N<10>" LOC= AB7 ;
+NET "EXP1_DIFF_P<11>" LOC= AC6 ;
+NET "EXP1_DIFF_N<11>" LOC= AD5 ;
+NET "EXP1_DIFF_P<12>" LOC= AD6 ;
+NET "EXP1_DIFF_N<12>" LOC= AC7 ;
+NET "EXP1_DIFF_P<13>" LOC= AE5 ;
+NET "EXP1_DIFF_N<13>" LOC= AD4 ;
+NET "EXP1_DIFF_P<14>" LOC= AB9 ;
+NET "EXP1_DIFF_N<14>" LOC= AA9 ;
+NET "EXP1_DIFF_P<15>" LOC= AC12 ;
+NET "EXP1_DIFF_N<15>" LOC= AC13 ;
+NET "EXP1_DIFF_P<16>" LOC= AA7 ;
+NET "EXP1_DIFF_N<16>" LOC= AA8 ;
+NET "EXP1_DIFF_P<17>" LOC= AA5 ;
+NET "EXP1_DIFF_N<17>" LOC= AB5 ;
+NET "EXP1_DIFF_P<18>" LOC= AB19 ;
+NET "EXP1_DIFF_N<18>" LOC= AC19 ;
+NET "EXP1_DIFF_P<19>" LOC= Y7 ;
+NET "EXP1_DIFF_N<19>" LOC= Y8 ;
+NET "EXP1_DIFF_P<20>" LOC= W9 ;
+NET "EXP1_DIFF_N<20>" LOC= W8 ;
+NET "EXP1_DIFF_P<21>" LOC= V8 ;
+NET "EXP1_DIFF_N<21>" LOC= V9 ;
+NET "EXP1_SE_CLK_OUT" LOC= B12 | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_CLK_IN" LOC= E10 | IOSTANDARD = LVCMOS33;
+NET "EXP1_DIFF_CLK_OUT_P" LOC= AC18 ;
+NET "EXP1_DIFF_CLK_OUT_N" LOC= AB17 ;
+NET "EXP1_DIFF_CLK_IN_P" LOC= AB14 ;
+NET "EXP1_DIFF_CLK_IN_N" LOC= AC14 ;
+#NET "EXP1_RCLK_DIFF_P" LOC= AB6 ;
+#NET "EXP1_RCLK_DIFF_N" LOC= AB7 ;
+
+# CPU Debug Trace
+NET "ATDD<8>" LOC= C16 | IOSTANDARD = LVCMOS33;
+NET "ATDD<9>" LOC= A17 | IOSTANDARD = LVCMOS33;
+NET "ATDD<10>" LOC= B15 | IOSTANDARD = LVCMOS33;
+NET "ATDD<11>" LOC= E15 | IOSTANDARD = LVCMOS33;
+NET "ATDD<12>" LOC= A14 | IOSTANDARD = LVCMOS33;
+NET "ATDD<13>" LOC= D18 | IOSTANDARD = LVCMOS33;
+NET "ATDD<14>" LOC= A13 | IOSTANDARD = LVCMOS33;
+NET "ATDD<15>" LOC= C13 | IOSTANDARD = LVCMOS33;
+NET "ATDD<16>" LOC= D14 | IOSTANDARD = LVCMOS33;
+NET "ATDD<17>" LOC= C17 | IOSTANDARD = LVCMOS33;
+NET "ATDD<18>" LOC= E16 | IOSTANDARD = LVCMOS33;
+NET "ATDD<19>" LOC= C14 | IOSTANDARD = LVCMOS33;
+NET "TRACE_TS10" LOC= B16 | IOSTANDARD = LVCMOS33;
+NET "TRACE_TS20" LOC= E21 | IOSTANDARD = LVCMOS33;
+NET "TRACE_TS1E" LOC= B14 | IOSTANDARD = LVCMOS33;
+NET "TRACE_TS2E" LOC= B17 | IOSTANDARD = LVCMOS33;
+NET "TRACE_TS3" LOC= C18 | IOSTANDARD = LVCMOS33;
+NET "TRACE_TS4" LOC= G21 | IOSTANDARD = LVCMOS33;
+NET "TRACE_TS5" LOC= A18 | IOSTANDARD = LVCMOS33;
+NET "TRACE_TS6" LOC= F10 | IOSTANDARD = LVCMOS33;
+NET "TRACE_CLK" LOC= D15 | IOSTANDARD = LVCMOS33;
+NET "CPU_HRESET" LOC= E11 | IOSTANDARD = LVCMOS33;
+NET "CPU_TDO" LOC= K7 | IOSTANDARD = LVCMOS33;
+NET "CPU_TMS" LOC= L5 | IOSTANDARD = LVCMOS33;
+NET "CPU_TDI" LOC= M6 | IOSTANDARD = LVCMOS33;
+NET "CPU_TRST" LOC= N7 | IOSTANDARD = LVCMOS33;
+NET "CPU_TCK" LOC= T8 | IOSTANDARD = LVCMOS33;
+NET "CPU_HALT_n" LOC= W4 | IOSTANDARD = LVCMOS33;
+
+
+# voltage termination
+CONFIG PROHIBIT = AA24;
+CONFIG PROHIBIT = AE23;
+CONFIG PROHIBIT = AF17;
+CONFIG PROHIBIT = V26;
+CONFIG PROHIBIT = E22;
+CONFIG PROHIBIT = L25;
+
+# unused pins
+CONFIG PROHIBIT = F9;
+CONFIG PROHIBIT = D10;
+CONFIG PROHIBIT = C12;
+CONFIG PROHIBIT = C11;
+CONFIG PROHIBIT = D11;
+CONFIG PROHIBIT = AB16;
+CONFIG PROHIBIT = AB22;
+CONFIG PROHIBIT = AC17;
+CONFIG PROHIBIT = AC21;
+CONFIG PROHIBIT = AE22;
+CONFIG PROHIBIT = AD23;
+CONFIG PROHIBIT = AC24;
+CONFIG PROHIBIT = AC23;
+CONFIG PROHIBIT = AC22;
+CONFIG PROHIBIT = AB22;
+CONFIG PROHIBIT = AE21;
+CONFIG PROHIBIT = AD21;
+CONFIG PROHIBIT = AF19;
+CONFIG PROHIBIT = AF18;
+CONFIG PROHIBIT = AE18;
+CONFIG PROHIBIT = AD18;
+CONFIG PROHIBIT = AE17;
+CONFIG PROHIBIT = AE16;
+CONFIG PROHIBIT = AD16;
+CONFIG PROHIBIT = G6;
+CONFIG PROHIBIT = H24;
+CONFIG PROHIBIT = J24;
+CONFIG PROHIBIT = N23;
+CONFIG PROHIBIT = N15;
+CONFIG PROHIBIT = P14;
+CONFIG PROHIBIT = V23;
+CONFIG PROHIBIT = Y26;
+CONFIG PROHIBIT = Y25;
+CONFIG PROHIBIT = P21;
+CONFIG PROHIBIT = R21;
+CONFIG PROHIBIT = U22;
+
+# grounded pins from gigabit transcievers
+CONFIG PROHIBIT = K4;
+CONFIG PROHIBIT = K3;
+CONFIG PROHIBIT = J1;
+CONFIG PROHIBIT = K1;
+CONFIG PROHIBIT = M1;
+CONFIG PROHIBIT = L1;
+CONFIG PROHIBIT = T3;
+CONFIG PROHIBIT = T4;
+CONFIG PROHIBIT = R1;
+CONFIG PROHIBIT = T1;
+CONFIG PROHIBIT = V1;
+CONFIG PROHIBIT = U1;
+CONFIG PROHIBIT = D3;
+CONFIG PROHIBIT = D4;
+CONFIG PROHIBIT = C1;
+CONFIG PROHIBIT = D1;
+CONFIG PROHIBIT = E1;
+CONFIG PROHIBIT = F1;
+CONFIG PROHIBIT = AB3;
+CONFIG PROHIBIT = AB4;
+CONFIG PROHIBIT = AA1;
+CONFIG PROHIBIT = AB1;
+CONFIG PROHIBIT = AC1;
+CONFIG PROHIBIT = AD1;
+CONFIG PROHIBIT = H2;
+CONFIG PROHIBIT = J2;
+CONFIG PROHIBIT = N2;
+CONFIG PROHIBIT = M2;
+CONFIG PROHIBIT = P2;
+CONFIG PROHIBIT = R2;
+CONFIG PROHIBIT = V2;
+CONFIG PROHIBIT = W2;
+CONFIG PROHIBIT = B2;
+CONFIG PROHIBIT = C2;
+CONFIG PROHIBIT = G2;
+CONFIG PROHIBIT = F2;
+CONFIG PROHIBIT = Y2;
+CONFIG PROHIBIT = AA2;
+CONFIG PROHIBIT = AD2;
+CONFIG PROHIBIT = AE2;
+
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj
new file mode 100644
index 0000000..24120d5
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj
@@ -0,0 +1,19 @@
+vhdl work ../top.vhd
+vhdl zpu ../../../zpu_pkg.vhdl
+vhdl zpu ../../../zpu_small.vhdl
+vhdl zpu ../../../zpu_medium.vhdl
+vhdl zpu ../../../roms/rom_pkg.vhdl
+#vhdl zpu ../../../roms/hello_dbram.vhdl
+#vhdl zpu ../../../roms/hello_bram.vhdl
+vhdl zpu ../../../roms/dmips_dbram.vhdl
+vhdl zpu ../../../roms/dmips_bram.vhdl
+vhdl zpu ../../../helpers/zpu_small1.vhdl
+vhdl zpu ../../../helpers/zpu_med1.vhdl
+vhdl zpu ../../../devices/txt_util.vhdl
+vhdl zpu ../../../devices/phi_io.vhdl
+vhdl zpu ../../../devices/timer.vhdl
+vhdl zpu ../../../devices/gpio.vhdl
+vhdl zpu ../../../devices/rx_unit.vhdl
+vhdl zpu ../../../devices/tx_unit.vhdl
+vhdl zpu ../../../devices/br_gen.vhdl
+vhdl zpu ../../../devices/trace.vhdl
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.ut b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.ut
new file mode 100644
index 0000000..e0159fb
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.ut
@@ -0,0 +1,39 @@
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g ConfigRate:2
+-g CclkPin:PullUp
+-g M0Pin:PullUp
+-g M1Pin:PullUp
+-g M2Pin:PullUp
+-g ProgPin:PullUp
+-g DonePin:PullUp
+-g InitPin:Pullup
+-g CsPin:Pullup
+-g DinPin:Pullup
+-g BusyPin:Pullup
+-g RdWrPin:Pullup
+-g HswapenPin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g ConfigFallback:Enable
+-g SelectMAPAbort:Enable
+-g BPI_page_size:1
+-g OverTempPowerDown:Disable
+-g JTAG_SysMon:Enable
+-g DCIUpdateMode:AsRequired
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Match_cycle:Auto
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
+-g Encrypt:No
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.xst b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.xst
new file mode 100644
index 0000000..7ca54bc
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.xst
@@ -0,0 +1,60 @@
+set -tmpdir "tmp"
+set -xsthdpdir "xst"
+run
+-ifn ../synthesis_config/top.prj
+-ifmt mixed
+-ofn top
+-ofmt NGC
+-p xc5vfx30t-1-ff665
+-top top
+-opt_mode Speed
+-opt_level 1
+-power NO
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-dsp_utilization_ratio 100
+-lc Off
+-reduce_control_sets Off
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract Yes
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-auto_bram_packing NO
+-mux_extract Yes
+-resource_sharing YES
+-async_to_sync NO
+-use_dsp48 Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 32
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd
new file mode 100644
index 0000000..560e685
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd
@@ -0,0 +1,444 @@
+-- top module of
+-- Avnet Virtex 5 FX Evaluation Board
+--
+-- using following external connections:
+-- pushbutton PB1 as reset
+-- LEDs for output
+-- RS232 (non USB)
+--
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library zpu;
+use zpu.zpupkg.all; -- zpu_dbgo_t
+
+library unisim;
+use unisim.vcomponents.ibufds;
+use unisim.vcomponents.dcm_base;
+
+
+entity top is
+ port (
+ -- pragma translate_off
+ stop_simulation : out std_logic;
+ -- pragma translate_on
+ clk_100MHz : in std_logic; -- 100 MHz clock
+ clk_socket : in std_logic; -- user clock
+ user_clk_p : in std_logic; -- differential user clock
+ user_clk_n : in std_logic; -- differential user clock
+ --
+ -- RS232
+ rs232_rx : in std_logic;
+ rs232_tx : out std_logic;
+ rs232_rts : in std_logic;
+ rs232_cts : out std_logic;
+ -- RS232 USB
+ rs232_usb_rx : in std_logic;
+ rs232_usb_tx : out std_logic;
+ rs232_usb_reset_n : out std_logic;
+ --
+ gpio_led_n : out std_logic_vector(7 downto 0);
+ gpio_dipswitch : in std_logic_vector(7 downto 0);
+ gpio_button : in std_logic_vector(3 downto 0);
+ --
+ -- FLASH 8Mx16
+ flash_a : out std_logic_vector(31 downto 7);
+ flash_dq : inout std_logic_vector(15 downto 0);
+ flash_wen : out std_logic;
+ flash_oen : out std_logic_vector(0 downto 0);
+ flash_cen : out std_logic_vector(0 downto 0);
+ flash_rp_n : out std_logic;
+ flash_byte_n : out std_logic;
+ flash_adv_n : out std_logic;
+ flash_clk : out std_logic;
+ flash_wait : in std_logic;
+ --
+ -- DDR2 SDRAM 16Mx32
+ ddr2_odt : in std_logic_vector(0 downto 0);
+ ddr2_a : out std_logic_vector(12 downto 0);
+ ddr2_ba : out std_logic_vector(1 downto 0);
+ ddr2_cas_n : out std_logic;
+ ddr2_cke : out std_logic;
+ ddr2_cs_n : out std_logic;
+ ddr2_ras_n : out std_logic;
+ ddr2_we_n : out std_logic;
+ ddr2_dm : out std_logic_vector(3 downto 0);
+ ddr2_dqs_p : inout std_logic_vector(3 downto 0);
+ ddr2_dqs_n : inout std_logic_vector(3 downto 0);
+ ddr2_dq : inout std_logic_vector(31 downto 0);
+ ddr2_ck_p : in std_logic_vector(1 downto 0);
+ ddr2_ck_n : in std_logic_vector(1 downto 0);
+ --
+ -- Ethernet MAC
+ gmii_txer : out std_logic;
+ gmii_tx_clk : in std_logic; -- 25 MHz
+ gmii_rx_clk : in std_logic; -- 25 MHz
+ gmii_gtc_clk : out std_logic;
+ gmii_crs : in std_logic;
+ gmii_dv : in std_logic;
+ gmii_rx_data : in std_logic_vector(7 downto 0);
+ gmii_col : in std_logic;
+ gmii_rx_er : in std_logic;
+ gmii_tx_en : out std_logic;
+ gmii_tx_data : out std_logic_vector(7 downto 0);
+ gbe_rst_n : out std_logic;
+ gbe_mdc : out std_logic;
+ gbe_mdio : inout std_logic;
+ gbe_int_n : inout std_logic;
+ gbe_mclk : in std_logic;
+ --
+ -- SysACE CompactFlash
+ sam_clk : in std_logic;
+ sam_a : out std_logic_vector(6 downto 0);
+ sam_d : inout std_logic_vector(15 downto 0);
+ sam_cen : out std_logic;
+ sam_oen : out std_logic;
+ sam_wen : out std_logic;
+ sam_mpirq : in std_logic;
+ sam_brdy : in std_logic;
+ sam_reset_n : out std_logic;
+ --
+ -- Expansion Header
+ exp1_se_io : inout std_logic_vector(33 downto 0);
+ exp1_diff_p : inout std_logic_vector(21 downto 0);
+ exp1_diff_n : inout std_logic_vector(21 downto 0);
+ exp1_se_clk_out : out std_logic;
+ exp1_se_clk_in : in std_logic;
+ exp1_diff_clk_out_p : out std_logic;
+ exp1_diff_clk_out_n : out std_logic;
+ exp1_diff_clk_in_p : in std_logic;
+ exp1_diff_clk_in_n : in std_logic;
+ --
+ -- Debug/Trace
+ atdd : inout std_logic_vector(19 downto 8);
+ trace_ts10 : inout std_logic;
+ trace_ts20 : inout std_logic;
+ trace_ts1e : inout std_logic;
+ trace_ts2e : inout std_logic;
+ trace_ts3 : inout std_logic;
+ trace_ts4 : inout std_logic;
+ trace_ts5 : inout std_logic;
+ trace_ts6 : inout std_logic;
+ trace_clk : in std_logic;
+ cpu_hreset : in std_logic;
+ cpu_tdo : out std_logic;
+ cpu_tms : in std_logic;
+ cpu_tdi : in std_logic;
+ cpu_trst : in std_logic;
+ cpu_tck : in std_logic;
+ cpu_halt_n : in std_logic
+ );
+end entity top;
+
+
+architecture rtl of top is
+
+ ---------------------------
+ -- type declarations
+ type zpu_type is (zpu_small, zpu_medium);
+
+ ---------------------------
+ -- constant declarations
+ constant zpu_flavour : zpu_type := zpu_medium; -- choose your flavour HERE
+ -- modify frequency here
+ constant clk_multiply : positive := 5; -- 7 for small, 5 for medium
+ constant clk_divide : positive := 4; -- 4 for small, 4 for medium
+ --
+ --
+ constant word_size_c : natural := 32; -- 32 bits data path
+ constant addr_w_c : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O
+ --
+ constant clk_frequency : positive := 100; -- input frequency for correct calculation
+
+ ---------------------------
+ -- component declarations
+ component zpu_small1 is
+ generic (
+ word_size : natural := 32; -- 32 bits data path
+ d_care_val : std_logic := '0'; -- Fill value
+ clk_freq : positive := 50; -- 50 MHz clock
+ brate : positive := 115200; -- RS232 baudrate
+ addr_w : natural := 16; -- 16 bits address space=64 kB, 32 kB I/O
+ bram_w : natural := 15 -- 15 bits RAM space=32 kB
+ );
+ port (
+ clk_i : in std_logic; -- CPU clock
+ rst_i : in std_logic; -- Reset
+ break_o : out std_logic; -- Break executed
+ dbg_o : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o : out std_logic; -- UART Tx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end component zpu_small1;
+
+ component zpu_med1 is
+ generic(
+ word_size : natural := 32; -- 32 bits data path
+ d_care_val : std_logic := '0'; -- Fill value
+ clk_freq : positive := 50; -- 50 MHz clock
+ brate : positive := 115200; -- RS232 baudrate
+ addr_w : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O
+ bram_w : natural := 15 -- 15 bits RAM space=32 kB
+ );
+ port(
+ clk_i : in std_logic; -- CPU clock
+ rst_i : in std_logic; -- Reset
+ break_o : out std_logic; -- Break executed
+ dbg_o : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o : out std_logic; -- UART Tx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end component zpu_med1;
+
+
+
+ ---------------------------
+ -- signal declarations
+ signal sys_clk : std_ulogic;
+ signal dcm_base_i0_clk0 : std_ulogic;
+ signal dcm_base_i0_clkfx : std_ulogic;
+ signal clk_fb : std_ulogic;
+ signal clk : std_ulogic;
+ --
+ signal reset_shift_reg : std_ulogic_vector(3 downto 0);
+ signal reset_sync : std_ulogic;
+ --
+ signal zpu_i0_dbg : zpu_dbgo_t; -- Debug info
+ signal zpu_i0_break : std_logic;
+ --
+ signal ibufds_i0_o : std_ulogic;
+ signal ibufds_i1_o : std_ulogic;
+ --
+ signal gpio_in : std_logic_vector(31 downto 0) := (others => '0');
+ signal zpu_i0_gpio_out : std_logic_vector(31 downto 0);
+ signal zpu_i0_gpio_dir : std_logic_vector(31 downto 0);
+
+begin
+
+ -- default output drivers
+ -- to pass bitgen DRC
+ -- other used outputs are only commented
+ --rs232_tx <= '1';
+ rs232_cts <= '1';
+ rs232_usb_tx <= '1';
+ rs232_usb_reset_n <= '1';
+ --
+ --gpio_led_n <= (others => '1');
+ --
+ flash_cen <= "1";
+ flash_oen <= "1";
+ flash_wen <= '1';
+ flash_rp_n <= '1';
+ flash_byte_n <= '1';
+ flash_adv_n <= '1';
+ flash_clk <= '0';
+ flash_a <= (others => '0');
+ flash_dq <= (others => 'Z');
+ --
+ ddr2_a <= (others => '0');
+ ddr2_ba <= (others => '0');
+ ddr2_dm <= (others => '0');
+ ddr2_cs_n <= '1';
+ ddr2_we_n <= '1';
+ ddr2_cke <= '1';
+ ddr2_cas_n <= '1';
+ ddr2_ras_n <= '1';
+ ddr2_dqs_p <= (others => 'Z');
+ ddr2_dqs_n <= (others => 'Z');
+ ddr2_dq <= (others => 'Z');
+ --
+ gmii_gtc_clk <= '0';
+ gmii_tx_data <= (others => '0');
+ gmii_tx_en <= '0';
+ gmii_txer <= '0';
+ gbe_rst_n <= '1';
+ gbe_mdc <= '1';
+ gbe_mdio <= 'Z';
+ gbe_int_n <= 'Z';
+ --
+ sam_cen <= '1';
+ sam_oen <= '1';
+ sam_wen <= '1';
+ sam_a <= (others => '0');
+ sam_d <= (others => 'Z');
+ sam_reset_n <= '1';
+ --
+ exp1_se_io <= (others => 'Z');
+ exp1_diff_p <= (others => 'Z');
+ exp1_diff_n <= (others => 'Z');
+ exp1_se_clk_out <= '0';
+ exp1_diff_clk_out_p <= '0';
+ exp1_diff_clk_out_n <= '1';
+ --
+ atdd <= (others => 'Z');
+ trace_ts10 <= 'Z';
+ trace_ts20 <= 'Z';
+ trace_ts1e <= 'Z';
+ trace_ts2e <= 'Z';
+ trace_ts3 <= 'Z';
+ trace_ts4 <= 'Z';
+ trace_ts5 <= 'Z';
+ trace_ts6 <= 'Z';
+ cpu_tdo <= '1';
+
+
+ -- global differential input buffer
+ ibufds_i0 : ibufds
+ generic map (
+ diff_term => true
+ )
+ port map (
+ o => ibufds_i0_o,
+ i => ddr2_ck_p(0),
+ ib => ddr2_ck_n(0)
+ );
+
+ -- global differential input buffer
+ ibufds_i1 : ibufds
+ generic map (
+ diff_term => true
+ )
+ port map (
+ o => ibufds_i1_o,
+ i => ddr2_ck_p(1),
+ ib => ddr2_ck_n(1)
+ );
+
+ -- digital clock manager (DCM)
+ -- to generate higher/other system clock frequencys
+ dcm_base_i0: dcm_base
+ generic map (
+ startup_wait => true, -- wait with DONE till locked
+ --dfs_frequency_mode => "HIGH", -- use this with zpu_small for 175 MHz
+ clkfx_multiply => clk_multiply,
+ clkfx_divide => clk_divide,
+ clk_feedback => "1X"
+ )
+ port map (
+ rst => '0',
+ clkin => clk_100MHz,
+ clk0 => dcm_base_i0_clk0,
+ clkfx => dcm_base_i0_clkfx,
+ clkfb => clk_fb
+ );
+
+ -- speaking names for dcm output
+ clk_fb <= dcm_base_i0_clk0;
+ clk <= dcm_base_i0_clkfx;
+
+
+ -- reset synchronizer
+ -- generate synchronous reset
+ reset_synchronizer : process(clk, gpio_button)
+ begin
+ if (gpio_button(0) = '1') then
+ reset_shift_reg <= (others => '1');
+ elsif rising_edge(clk) then
+ reset_shift_reg <= reset_shift_reg(reset_shift_reg'high-1 downto 0) & '0';
+ end if;
+ end process;
+ reset_sync <= reset_shift_reg(reset_shift_reg'high);
+
+
+
+ -- select instance of zpu
+ zpu_i0_small: if zpu_flavour = zpu_small generate
+ zpu_i0 : zpu_small1
+ generic map (
+ addr_w => addr_w_c,
+ word_size => word_size_c,
+ clk_freq => clk_frequency * clk_multiply / clk_divide
+ )
+ port map (
+ clk_i => clk, -- : in std_logic; - CPU clock
+ rst_i => reset_sync, -- : in std_logic; - Reset
+ break_o => zpu_i0_break, -- : out std_logic; - Break executed
+ dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; - Debug info
+ rs232_tx_o => rs232_tx, -- : out std_logic; - UART Tx
+ rs232_rx_i => rs232_rx, -- : in std_logic - UART Rx
+ gpio_in => gpio_in, -- : in std_logic_vector(31 downto 0);
+ gpio_out => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
+ gpio_dir => zpu_i0_gpio_dir -- : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end generate zpu_i0_small;
+
+ zpu_i0_medium: if zpu_flavour = zpu_medium generate
+ zpu_i0 : zpu_med1
+ generic map (
+ addr_w => addr_w_c,
+ word_size => word_size_c,
+ clk_freq => clk_frequency * clk_multiply / clk_divide
+ )
+ port map (
+ clk_i => clk, -- : in std_logic; - CPU clock
+ rst_i => reset_sync, -- : in std_logic; - Reset
+ break_o => zpu_i0_break, -- : out std_logic; - Break executed
+ dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; - Debug info
+ rs232_tx_o => rs232_tx, -- : out std_logic; - UART Tx
+ rs232_rx_i => rs232_rx, -- : in std_logic - UART Rx
+ gpio_in => gpio_in, -- : in std_logic_vector(31 downto 0);
+ gpio_out => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
+ gpio_dir => zpu_i0_gpio_dir -- : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end generate zpu_i0_medium;
+
+ -- pragma translate_off
+ stop_simulation <= zpu_i0_break; -- abort() causes to stop the simulation
+
+
+ trace_mod : trace
+ generic map (
+ addr_w => addr_w_c,
+ word_size => word_size_c,
+ log_file => "zpu_trace.log"
+ )
+ port map (
+ clk_i => clk,
+ dbg_i => zpu_i0_dbg,
+ stop_i => zpu_i0_break,
+ busy_i => '0'
+ );
+ -- pragma translate_on
+
+ -- assign GPIOs
+ -- no bidirectional pins (e.g. headers), so
+ -- gpio_dir is unused
+ --
+ -- bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
+ --
+ -- in -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ -- out -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ --
+ --
+ -- bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+ --
+ -- in gpio_dipswitch(7.....0) -- -- -- -- buttons3.0
+ -- out -- -- -- -- -- -- -- -- led(7................0)
+ --
+
+ gpio_in(15 downto 8) <= gpio_dipswitch;
+ gpio_in( 3 downto 0) <= gpio_button;
+
+
+ -- switch on all LEDs in case of break
+ process
+ begin
+ wait until rising_edge(clk);
+ gpio_led_n <= not zpu_i0_gpio_out(7 downto 0);
+ if zpu_i0_break = '1' then
+ gpio_led_n <= (others => '0');
+ end if;
+ end process;
+
+
+
+end architecture rtl;
+
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top_tb.vhd b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top_tb.vhd
new file mode 100644
index 0000000..751ce22
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top_tb.vhd
@@ -0,0 +1,271 @@
+-- testbench for
+-- Avnet Virtex 5 FX Evaluation Board
+--
+-- includes "model" for clock generation
+-- simulate press on gpio_button(0) (=PB1) as reset
+--
+-- place models for external components (PHY, DDR2-RAM) in this file
+--
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity top_tb is
+end entity top_tb;
+
+architecture testbench of top_tb is
+
+ ---------------------------
+ -- constant declarations
+ constant clk_100MHz_period : time := 1 sec / 100_000_000; -- 100 MHz
+
+
+ ---------------------------
+ -- signal declarations
+ signal simulation_run : boolean := true;
+ signal tb_stop_simulation : std_logic;
+ --
+ signal tb_clk_100MHz : std_logic := '0'; -- 100 MHz clock
+ signal tb_clk_socket : std_logic := '0'; -- user clock
+ signal tb_user_clk_p : std_logic := '0'; -- diff user clock
+ signal tb_user_clk_n : std_logic := '0'; -- diff user clock
+ --
+ -- RS232
+ signal tb_rs232_rx : std_logic := '0';
+ signal tb_rs232_tx : std_logic;
+ signal tb_rs232_rts : std_logic := '0';
+ signal tb_rs232_cts : std_logic;
+ -- RS232 USB
+ signal tb_rs232_usb_rx : std_logic := '0';
+ signal tb_rs232_usb_tx : std_logic;
+ signal tb_rs232_usb_reset_n : std_logic;
+ --
+ signal tb_gpio_led_n : std_logic_vector(7 downto 0);
+ signal tb_gpio_dipswitch : std_logic_vector(7 downto 0) := (others => '0');
+ signal tb_gpio_button : std_logic_vector(3 downto 0) := (others => '0');
+ --
+ -- FLASH 8Mx16
+ signal tb_flash_a : std_logic_vector(31 downto 7);
+ signal tb_flash_dq : std_logic_vector(15 downto 0);
+ signal tb_flash_wen : std_logic;
+ signal tb_flash_oen : std_logic_vector(0 downto 0);
+ signal tb_flash_cen : std_logic_vector(0 downto 0);
+ signal tb_flash_rp_n : std_logic;
+ signal tb_flash_byte_n : std_logic;
+ signal tb_flash_adv_n : std_logic;
+ signal tb_flash_clk : std_logic;
+ signal tb_flash_wait : std_logic := '0';
+ --
+ -- DDR2 SDRAM 16Mx32
+ signal tb_ddr2_odt : std_logic_vector(0 downto 0) := (others => '0');
+ signal tb_ddr2_a : std_logic_vector(12 downto 0);
+ signal tb_ddr2_ba : std_logic_vector(1 downto 0);
+ signal tb_ddr2_cas_n : std_logic;
+ signal tb_ddr2_cke : std_logic;
+ signal tb_ddr2_cs_n : std_logic;
+ signal tb_ddr2_ras_n : std_logic;
+ signal tb_ddr2_we_n : std_logic;
+ signal tb_ddr2_dm : std_logic_vector(3 downto 0);
+ signal tb_ddr2_dqs_p : std_logic_vector(3 downto 0);
+ signal tb_ddr2_dqs_n : std_logic_vector(3 downto 0);
+ signal tb_ddr2_dq : std_logic_vector(31 downto 0);
+ signal tb_ddr2_ck_p : std_logic_vector(1 downto 0) := (others => '0');
+ signal tb_ddr2_ck_n : std_logic_vector(1 downto 0) := (others => '0');
+ --
+ -- Ethernet MAC
+ signal tb_gmii_txer : std_logic;
+ signal tb_gmii_tx_clk : std_logic := '0'; -- 25 MHz
+ signal tb_gmii_rx_clk : std_logic := '0'; -- 25 MHz
+ signal tb_gmii_gtc_clk : std_logic;
+ signal tb_gmii_crs : std_logic := '0';
+ signal tb_gmii_dv : std_logic := '0';
+ signal tb_gmii_rx_data : std_logic_vector(7 downto 0);
+ signal tb_gmii_col : std_logic := '0';
+ signal tb_gmii_rx_er : std_logic := '0';
+ signal tb_gmii_tx_en : std_logic;
+ signal tb_gmii_tx_data : std_logic_vector(7 downto 0);
+ signal tb_gbe_rst_n : std_logic;
+ signal tb_gbe_mdc : std_logic;
+ signal tb_gbe_mdio : std_logic;
+ signal tb_gbe_int_n : std_logic;
+ signal tb_gbe_mclk : std_logic := '0';
+ --
+ -- SysACE CompactFlash
+ signal tb_sam_clk : std_logic := '0';
+ signal tb_sam_a : std_logic_vector(6 downto 0);
+ signal tb_sam_d : std_logic_vector(15 downto 0);
+ signal tb_sam_cen : std_logic;
+ signal tb_sam_oen : std_logic;
+ signal tb_sam_wen : std_logic;
+ signal tb_sam_mpirq : std_logic := '0';
+ signal tb_sam_brdy : std_logic := '0';
+ signal tb_sam_reset_n : std_logic;
+ --
+ -- Expansion Header
+ signal tb_exp1_se_io : std_logic_vector(33 downto 0);
+ signal tb_exp1_diff_p : std_logic_vector(21 downto 0);
+ signal tb_exp1_diff_n : std_logic_vector(21 downto 0);
+ signal tb_exp1_se_clk_out : std_logic;
+ signal tb_exp1_se_clk_in : std_logic := '0';
+ signal tb_exp1_diff_clk_out_p : std_logic;
+ signal tb_exp1_diff_clk_out_n : std_logic;
+ signal tb_exp1_diff_clk_in_p : std_logic := '0';
+ signal tb_exp1_diff_clk_in_n : std_logic := '0';
+ --
+ -- Debug/Trace
+ signal tb_atdd : std_logic_vector(19 downto 8);
+ signal tb_trace_ts10 : std_logic;
+ signal tb_trace_ts20 : std_logic;
+ signal tb_trace_ts1e : std_logic;
+ signal tb_trace_ts2e : std_logic;
+ signal tb_trace_ts3 : std_logic;
+ signal tb_trace_ts4 : std_logic;
+ signal tb_trace_ts5 : std_logic;
+ signal tb_trace_ts6 : std_logic;
+ signal tb_trace_clk : std_logic := '0';
+ signal tb_cpu_hreset : std_logic := '0';
+ signal tb_cpu_tdo : std_logic;
+ signal tb_cpu_tms : std_logic := '0';
+ signal tb_cpu_tdi : std_logic := '0';
+ signal tb_cpu_trst : std_logic := '0';
+ signal tb_cpu_tck : std_logic := '0';
+ signal tb_cpu_halt_n : std_logic := '0';
+
+
+begin
+
+
+ -- generate clocks
+ tb_clk_100MHz <= not tb_clk_100MHz after clk_100MHz_period / 2 when simulation_run;
+
+ -- generate reset
+ tb_gpio_button(0) <= '1', '0' after 6.66 * clk_100MHz_period;
+
+
+ -- simulate keypress
+ tb_gpio_button(2) <= '0', '1' after 55 us, '0' after 56 us;
+
+ -- dut
+ top_i0 : entity work.top
+ port map (
+ stop_simulation => tb_stop_simulation, -- : out std_logic;
+ clk_100MHz => tb_clk_100MHz, -- : in std_logic;
+ clk_socket => tb_clk_socket, -- : in std_logic;
+ user_clk_p => tb_user_clk_p, -- : in std_logic;
+ user_clk_n => tb_user_clk_n, -- : in std_logic;
+ --
+ -- RS232
+ rs232_rx => tb_rs232_rx, -- : in std_logic;
+ rs232_tx => tb_rs232_tx, -- : out std_logic;
+ rs232_rts => tb_rs232_rts, -- : in std_logic;
+ rs232_cts => tb_rs232_cts, -- : out std_logic;
+ -- RS232 USB
+ rs232_usb_rx => tb_rs232_usb_rx, -- : in std_logic;
+ rs232_usb_tx => tb_rs232_usb_tx, -- : out std_logic;
+ rs232_usb_reset_n => tb_rs232_usb_reset_n, -- : out std_logic;
+ --
+ gpio_led_n => tb_gpio_led_n, -- : out std_logic_vector(7 downto 0);
+ gpio_dipswitch => tb_gpio_dipswitch, -- : in std_logic_vector(7 downto 0);
+ gpio_button => tb_gpio_button, -- : in std_logic_vector(3 downto 0);
+ --
+ -- FLASH 8Mx16
+ flash_a => tb_flash_a, -- : out std_logic_vector(31 downto 7);
+ flash_dq => tb_flash_dq, -- : inout std_logic_vector(15 downto 0);
+ flash_wen => tb_flash_wen, -- : out std_logic;
+ flash_oen => tb_flash_oen, -- : out std_logic_vector(0 downto 0);
+ flash_cen => tb_flash_cen, -- : out std_logic_vector(0 downto 0);
+ flash_rp_n => tb_flash_rp_n, -- : out std_logic;
+ flash_byte_n => tb_flash_byte_n, -- : out std_logic;
+ flash_adv_n => tb_flash_adv_n, -- : out std_logic;
+ flash_clk => tb_flash_clk, -- : out std_logic;
+ flash_wait => tb_flash_wait, -- : in std_logic;
+ --
+ -- DDR2 SDRAM 16Mx32
+ ddr2_odt => tb_ddr2_odt, -- : in std_logic_vector(0 downto 0);
+ ddr2_a => tb_ddr2_a, -- : out std_logic_vector(12 downto 0);
+ ddr2_ba => tb_ddr2_ba, -- : out std_logic_vector(1 downto 0);
+ ddr2_cas_n => tb_ddr2_cas_n, -- : out std_logic;
+ ddr2_cke => tb_ddr2_cke, -- : out std_logic;
+ ddr2_cs_n => tb_ddr2_cs_n, -- : out std_logic;
+ ddr2_ras_n => tb_ddr2_ras_n, -- : out std_logic;
+ ddr2_we_n => tb_ddr2_we_n, -- : out std_logic;
+ ddr2_dm => tb_ddr2_dm, -- : out std_logic_vector(3 downto 0);
+ ddr2_dqs_p => tb_ddr2_dqs_p, -- : inout std_logic_vector(3 downto 0);
+ ddr2_dqs_n => tb_ddr2_dqs_n, -- : inout std_logic_vector(3 downto 0);
+ ddr2_dq => tb_ddr2_dq, -- : inout std_logic_vector(31 downto 0);
+ ddr2_ck_p => tb_ddr2_ck_p, -- : in std_logic_vector(1 downto 0);
+ ddr2_ck_n => tb_ddr2_ck_n, -- : in std_logic_vector(1 downto 0);
+ --
+ -- Ethernet MAC
+ gmii_txer => tb_gmii_txer, -- : out std_logic;
+ gmii_tx_clk => tb_gmii_tx_clk, -- : in std_logic;
+ gmii_rx_clk => tb_gmii_rx_clk, -- : in std_logic;
+ gmii_gtc_clk => tb_gmii_gtc_clk, -- : out std_logic;
+ gmii_crs => tb_gmii_crs, -- : in std_logic;
+ gmii_dv => tb_gmii_dv, -- : in std_logic;
+ gmii_rx_data => tb_gmii_rx_data, -- : in std_logic_vector(7 downto 0);
+ gmii_col => tb_gmii_col, -- : in std_logic;
+ gmii_rx_er => tb_gmii_rx_er, -- : in std_logic;
+ gmii_tx_en => tb_gmii_tx_en, -- : out std_logic;
+ gmii_tx_data => tb_gmii_tx_data, -- : out std_logic_vector(7 downto 0);
+ gbe_rst_n => tb_gbe_rst_n, -- : out std_logic;
+ gbe_mdc => tb_gbe_mdc, -- : out std_logic;
+ gbe_mdio => tb_gbe_mdio, -- : inout std_logic;
+ gbe_int_n => tb_gbe_int_n, -- : inout std_logic;
+ gbe_mclk => tb_gbe_mclk, -- : in std_logic;
+ --
+ -- SysACE CompactFlash
+ sam_clk => tb_sam_clk, -- : in std_logic;
+ sam_a => tb_sam_a, -- : out std_logic_vector(6 downto 0);
+ sam_d => tb_sam_d, -- : inout std_logic_vector(15 downto 0);
+ sam_cen => tb_sam_cen, -- : out std_logic;
+ sam_oen => tb_sam_oen, -- : out std_logic;
+ sam_wen => tb_sam_wen, -- : out std_logic;
+ sam_mpirq => tb_sam_mpirq, -- : in std_logic;
+ sam_brdy => tb_sam_brdy, -- : in std_logic;
+ sam_reset_n => tb_sam_reset_n, -- : out std_logic;
+ --
+ -- Expansion Header
+ exp1_se_io => tb_exp1_se_io, -- : inout std_logic_vector(33 downto 0);
+ exp1_diff_p => tb_exp1_diff_p, -- : inout std_logic_vector(21 downto 0);
+ exp1_diff_n => tb_exp1_diff_n, -- : inout std_logic_vector(21 downto 0);
+ exp1_se_clk_out => tb_exp1_se_clk_out, -- : out std_logic;
+ exp1_se_clk_in => tb_exp1_se_clk_in, -- : in std_logic;
+ exp1_diff_clk_out_p => tb_exp1_diff_clk_out_p, -- : out std_logic;
+ exp1_diff_clk_out_n => tb_exp1_diff_clk_out_n, -- : out std_logic;
+ exp1_diff_clk_in_p => tb_exp1_diff_clk_in_p, -- : in std_logic;
+ exp1_diff_clk_in_n => tb_exp1_diff_clk_in_n, -- : in std_logic;
+ --
+ -- Debug/Trace
+ atdd => tb_atdd, -- : inout std_logic_vector(19 downto 8);
+ trace_ts10 => tb_trace_ts10, -- : inout std_logic;
+ trace_ts20 => tb_trace_ts20, -- : inout std_logic;
+ trace_ts1e => tb_trace_ts1e, -- : inout std_logic;
+ trace_ts2e => tb_trace_ts2e, -- : inout std_logic;
+ trace_ts3 => tb_trace_ts3, -- : inout std_logic;
+ trace_ts4 => tb_trace_ts4, -- : inout std_logic;
+ trace_ts5 => tb_trace_ts5, -- : inout std_logic;
+ trace_ts6 => tb_trace_ts6, -- : inout std_logic;
+ trace_clk => tb_trace_clk, -- : in std_logic;
+ cpu_hreset => tb_cpu_hreset, -- : in std_logic;
+ cpu_tdo => tb_cpu_tdo, -- : out std_logic;
+ cpu_tms => tb_cpu_tms, -- : in std_logic;
+ cpu_tdi => tb_cpu_tdi, -- : in std_logic;
+ cpu_trst => tb_cpu_trst, -- : in std_logic;
+ cpu_tck => tb_cpu_tck, -- : in std_logic;
+ cpu_halt_n => tb_cpu_halt_n -- : in std_logic
+ );
+
+
+ -- check for simulation stopping
+ process (tb_stop_simulation)
+ begin
+ if tb_stop_simulation = '1' then
+ report "Simulation end." severity note;
+ simulation_run <= false;
+ end if;
+ end process;
+
+end architecture testbench;
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/clean_up.sh b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/clean_up.sh
new file mode 100755
index 0000000..3855f16
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/clean_up.sh
@@ -0,0 +1,16 @@
+#!/bin/sh
+
+# ise build stuff
+rm -rf build
+rm -f top.bit
+
+# modelsim compile stuff
+rm -rf work
+rm -rf zpu
+
+# modelsim simulation stuff
+rm -f vsim.wlf
+rm -f transcript
+rm -f zpu_trace.log
+rm -f zpu_med1_io.log
+rm -f zpu_small1_io.log
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation.sh b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation.sh
new file mode 100755
index 0000000..d525737
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation.sh
@@ -0,0 +1,49 @@
+#!/bin/sh
+
+# need project files:
+# run.do
+# wave.do
+
+# need ModelSim tools:
+# vlib
+# vcom
+# vsim
+
+
+echo "###############"
+echo "compile zpu lib"
+echo "###############"
+vlib zpu
+vcom -work zpu ../../roms/hello_dbram.vhdl
+vcom -work zpu ../../roms/hello_bram.vhdl
+#vcom -work zpu ../../roms/dmips_dbram.vhdl
+#vcom -work zpu ../../roms/dmips_bram.vhdl
+
+vcom -work zpu ../../roms/rom_pkg.vhdl
+vcom -work zpu ../../zpu_pkg.vhdl
+vcom -work zpu ../../zpu_small.vhdl
+vcom -work zpu ../../zpu_medium.vhdl
+vcom -work zpu ../../helpers/zpu_small1.vhdl
+vcom -work zpu ../../helpers/zpu_med1.vhdl
+vcom -work zpu ../../devices/txt_util.vhdl
+vcom -work zpu ../../devices/phi_io.vhdl
+vcom -work zpu ../../devices/timer.vhdl
+vcom -work zpu ../../devices/gpio.vhdl
+vcom -work zpu ../../devices/rx_unit.vhdl
+vcom -work zpu ../../devices/tx_unit.vhdl
+vcom -work zpu ../../devices/br_gen.vhdl
+vcom -work zpu ../../devices/trace.vhdl
+
+
+echo "################"
+echo "compile work lib"
+echo "################"
+vlib work
+vcom top.vhd
+vcom top_tb.vhd
+
+
+echo "###################"
+echo "start simulator gui"
+echo "###################"
+vsim -gui top_tb -do simulation_config/run.do
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/run.do b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/run.do
new file mode 100644
index 0000000..0d29e0a
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/run.do
@@ -0,0 +1,2 @@
+do wave.do
+run -all
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/wave.do b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/wave.do
new file mode 100644
index 0000000..12582ce
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/wave.do
@@ -0,0 +1,30 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /top_tb/tb_rot_center
+add wave -noupdate /top_tb/tb_clk_50mhz
+add wave -noupdate /top_tb/tb_rs232_dce_rxd
+add wave -noupdate /top_tb/tb_rs232_dce_txd
+add wave -noupdate -divider Buttons
+add wave -noupdate /top_tb/tb_btn_east
+add wave -noupdate /top_tb/tb_btn_north
+add wave -noupdate /top_tb/tb_btn_south
+add wave -noupdate /top_tb/tb_btn_west
+add wave -noupdate -divider LEDs
+add wave -noupdate /top_tb/top_i0/led
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {56714893 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 2
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ps} {151772250 ps}
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis.sh b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis.sh
new file mode 100755
index 0000000..66622ea
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis.sh
@@ -0,0 +1,36 @@
+#!/bin/sh
+
+# need project files:
+# top.xst
+# top.prj
+# top.ut
+
+# need Xilinx tools:
+# xst
+# ngdbuild
+# map
+# par
+# trce
+# bitgen
+
+echo "########################"
+echo "generate build directory"
+echo "########################"
+mkdir build
+cd build
+mkdir tmp
+
+echo "###############"
+echo "start processes"
+echo "###############"
+xst -ifn "../synthesis_config/top.xst" -ofn "top.syr"
+ngdbuild -dd _ngo -nt timestamp -uc ../synthesis_config/digilent-starter-xc3s500e.ucf -p xc3s500e-fg320-4 top.ngc top.ngd
+map -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o top_map.ncd top.ngd top.pcf
+par -w -ol high -t 1 top_map.ncd top.ncd top.pcf
+trce -v 3 -s 4 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf
+bitgen -f ../synthesis_config/top.ut top.ncd
+
+echo "###########"
+echo "get bitfile"
+echo "###########"
+cp top.bit ..
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/digilent-starter-xc3s500e.ucf b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/digilent-starter-xc3s500e.ucf
new file mode 100644
index 0000000..1007d00
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/digilent-starter-xc3s500e.ucf
@@ -0,0 +1,356 @@
+#####################################################
+# SPARTAN-3E Starter Kit Board Constraints File
+#
+# Family: Spartan3E
+# Device: XC3S500E
+# Package: FG320
+# Speed: -4
+
+
+############################################################
+## clock/timing constraints
+############################################################
+
+# Define clock period for 50 MHz oscillator (40%/60% duty-cycle)
+TIMESPEC "TS_CLK_50MHZ" = PERIOD "CLK_50MHZ" 50.0 MHz HIGH 40%;
+
+# ethernet clock
+TIMESPEC "TS_E_CLK" = PERIOD "E_CLK" 25.0 MHz HIGH 50% ;
+# need because misplaced ethernet clock lines
+NET "E_RX_CLK" CLOCK_DEDICATED_ROUTE = FALSE ;
+NET "E_TX_CLK" CLOCK_DEDICATED_ROUTE = FALSE ;
+
+############################################################
+## pin placement constraints
+############################################################
+
+# Analog-to-Digital Converter (ADC)
+# some connections shared with SPI Flash, DAC, ADC, and AMP
+NET "AD_CONV" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+
+# Programmable Gain Amplifier (AMP)
+# some connections shared with SPI Flash, DAC, ADC, and AMP
+NET "AMP_CS" LOC = "N7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+NET "AMP_DOUT" LOC = "E18" | IOSTANDARD = LVCMOS33 ;
+NET "AMP_SHDN" LOC = "P7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+
+# Pushbuttons (BTN)
+NET "BTN_EAST" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN | TIG;
+NET "BTN_NORTH" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN | TIG;
+NET "BTN_SOUTH" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN | TIG;
+NET "BTN_WEST" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN | TIG;
+
+# Clock inputs (CLK)
+NET "CLK_50MHZ" LOC = "C9" | IOSTANDARD = LVCMOS33 | TNM_NET = "CLK_50MHZ";
+NET "CLK_AUX" LOC = "B8" | IOSTANDARD = LVCMOS33 ;
+NET "CLK_SMA" LOC = "A10" | IOSTANDARD = LVCMOS33 ;
+
+# Digital-to-Analog Converter (DAC)
+# some connections shared with SPI Flash, DAC, ADC, and AMP
+NET "DAC_CLR" LOC = "P8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "DAC_CS" LOC = "N8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+
+# 1-Wire Secure EEPROM (DS)
+NET "DS_WIRE" LOC = "U4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+
+# Ethernet PHY (E)
+NET "E_COL" LOC = "U6" | IOSTANDARD = LVCMOS33 ;
+NET "E_CRS" LOC = "U13" | IOSTANDARD = LVCMOS33 ;
+NET "E_MDC" LOC = "P9" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "E_MDIO" LOC = "U5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "E_RX_CLK" LOC = "V3" | IOSTANDARD = LVCMOS33 | TNM_NET = "E_CLK";
+NET "E_RX_DV" LOC = "V2" | IOSTANDARD = LVCMOS33 ;
+NET "E_RXD<0>" LOC = "V8" | IOSTANDARD = LVCMOS33 ;
+NET "E_RXD<1>" LOC = "T11" | IOSTANDARD = LVCMOS33 ;
+NET "E_RXD<2>" LOC = "U11" | IOSTANDARD = LVCMOS33 ;
+NET "E_RXD<3>" LOC = "V14" | IOSTANDARD = LVCMOS33 ;
+NET "E_RX_ER" LOC = "U14" | IOSTANDARD = LVCMOS33 ;
+NET "E_TX_CLK" LOC = "T7" | IOSTANDARD = LVCMOS33 | TNM_NET = "E_CLK";
+NET "E_TX_EN" LOC = "P15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "E_TXD<0>" LOC = "R11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "E_TXD<1>" LOC = "T15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "E_TXD<2>" LOC = "R5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "E_TXD<3>" LOC = "T5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "E_TX_ER" LOC = "R6" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+
+# FPGA Configuration Mode, INIT_B Pins (FPGA)
+NET "FPGA_M0" LOC = "M10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "FPGA_M1" LOC = "V11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "FPGA_M2" LOC = "T10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "FPGA_INIT_B" LOC = "T3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
+NET "FPGA_RDWR_B" LOC = "U10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
+NET "FPGA_HSWAP" LOC = "B3" | IOSTANDARD = LVCMOS33 ;
+
+# FX2 Connector (FX2)
+NET "FX2_CLKIN" LOC = "E10" | IOSTANDARD = LVCMOS33 ;
+NET "FX2_CLKIO" LOC = "D9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_CLKOUT" LOC = "D10" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+
+# These four connections are shared with the J1 6-pin accessory header
+NET "FX2_IO<1>" LOC = "B4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<2>" LOC = "A4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<3>" LOC = "D5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<4>" LOC = "C5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+
+# These four connections are shared with the J2 6-pin accessory header
+NET "FX2_IO<5>" LOC = "A6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<6>" LOC = "B6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<7>" LOC = "E7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<8>" LOC = "F7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+
+# These four connections are shared with the J4 6-pin accessory header
+NET "FX2_IO<9>" LOC = "D7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<10>" LOC = "C7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<11>" LOC = "F8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<12>" LOC = "E8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+
+# The discrete LEDs are shared with the following 8 FX2 connections
+NET "FX2_IO<13>" LOC = "F9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<14>" LOC = "E9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<15>" LOC = "D11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<16>" LOC = "C11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<17>" LOC = "F11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<18>" LOC = "E11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<19>" LOC = "E12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<20>" LOC = "F12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+
+NET "FX2_IO<21>" LOC = "A13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<22>" LOC = "B13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<23>" LOC = "A14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<24>" LOC = "B14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<25>" LOC = "C14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<26>" LOC = "D14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<27>" LOC = "A16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<28>" LOC = "B16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<29>" LOC = "E13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<30>" LOC = "C4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<31>" LOC = "B11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<32>" LOC = "A11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<33>" LOC = "A8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<34>" LOC = "G9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#
+NET "FX2_IO<35>" LOC = "D12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<36>" LOC = "C12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<37>" LOC = "A15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<38>" LOC = "B15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#
+NET "FX2_IO<39>" LOC = "C3" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<40>" LOC = "C15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+
+# 6-pin header J1
+# These are shared connections with the FX2 connector
+#NET "J1<0>" LOC = "B4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J1<1>" LOC = "A4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J1<2>" LOC = "D5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J1<3>" LOC = "C5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+
+# 6-pin header J2
+# These are shared connections with the FX2 connector
+#NET "J2<0>" LOC = "A6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J2<1>" LOC = "B6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J2<2>" LOC = "E7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J2<3>" LOC = "F7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+
+# 6-pin header J4
+# These are shared connections with the FX2 connector
+#NET "J4<0>" LOC = "D7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J4<1>" LOC = "C7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J4<2>" LOC = "F8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J4<3>" LOC = "E8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+
+# Character LCD (LCD)
+NET "LCD_E" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "LCD_RS" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "LCD_RW" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+
+# LCD data connections are shared with StrataFlash connections SF_D<11:8>
+#NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+
+# Discrete LEDs (LED)
+# These are shared connections with the FX2 connector
+#NET "LED<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<6>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<7>" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+
+# PS/2 Mouse/Keyboard Port (PS2)
+NET "PS2_CLK" LOC = "G14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW | TIG;
+NET "PS2_DATA" LOC = "G13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW | TIG;
+
+# Rotary Pushbutton Switch (ROT)
+NET "ROT_A" LOC = "K18" | IOSTANDARD = LVTTL | PULLUP | TIG;
+NET "ROT_B" LOC = "G18" | IOSTANDARD = LVTTL | PULLUP | TIG;
+NET "ROT_CENTER" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN | TIG;
+
+# RS-232 Serial Ports (RS232)
+NET "RS232_DCE_RXD" LOC = "R7" | IOSTANDARD = LVTTL | TIG;
+NET "RS232_DCE_TXD" LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW | TIG;
+NET "RS232_DTE_RXD" LOC = "U8" | IOSTANDARD = LVTTL | TIG;
+NET "RS232_DTE_TXD" LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW | TIG;
+
+# DDR SDRAM (SD) (I/O Bank 3, VCCO=2.5V)
+NET "SD_A<0>" LOC = "T1" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<1>" LOC = "R3" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<2>" LOC = "R2" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<3>" LOC = "P1" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<4>" LOC = "F4" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<5>" LOC = "H4" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<6>" LOC = "H3" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<7>" LOC = "H1" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<8>" LOC = "H2" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<9>" LOC = "N4" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<10>" LOC = "T2" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<11>" LOC = "N5" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<12>" LOC = "P2" | IOSTANDARD = SSTL2_I ;
+NET "SD_BA<0>" LOC = "K5" | IOSTANDARD = SSTL2_I ;
+NET "SD_BA<1>" LOC = "K6" | IOSTANDARD = SSTL2_I ;
+NET "SD_CAS" LOC = "C2" | IOSTANDARD = SSTL2_I ;
+NET "SD_CK_N" LOC = "J4" | IOSTANDARD = SSTL2_I ; #DIFF_SSTL2_I ;
+NET "SD_CK_P" LOC = "J5" | IOSTANDARD = SSTL2_I ; #DIFF_SSTL2_I ;
+NET "SD_CKE" LOC = "K3" | IOSTANDARD = SSTL2_I ;
+NET "SD_CS" LOC = "K4" | IOSTANDARD = SSTL2_I ;
+NET "SD_DQ<0>" LOC = "L2" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<1>" LOC = "L1" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<2>" LOC = "L3" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<3>" LOC = "L4" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<4>" LOC = "M3" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<5>" LOC = "M4" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<6>" LOC = "M5" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<7>" LOC = "M6" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<8>" LOC = "E2" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<9>" LOC = "E1" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<10>" LOC = "F1" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<11>" LOC = "F2" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<12>" LOC = "G6" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<13>" LOC = "G5" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<14>" LOC = "H6" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<15>" LOC = "H5" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_LDM" LOC = "J2" | IOSTANDARD = SSTL2_I ;
+NET "SD_UDM" LOC = "J1" | IOSTANDARD = SSTL2_I ;
+NET "SD_RAS" LOC = "C1" | IOSTANDARD = SSTL2_I ;
+NET "SD_LDQS" LOC = "L6" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_UDQS" LOC = "G3" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_WE" LOC = "D1" | IOSTANDARD = SSTL2_I ;
+# Path to allow connection to top DCM connection
+NET "SD_CK_FB" LOC = "B9" | IOSTANDARD = LVCMOS33 ;
+
+# Prohibit VREF pins
+CONFIG PROHIBIT = D2;
+CONFIG PROHIBIT = G4;
+CONFIG PROHIBIT = J6;
+CONFIG PROHIBIT = L5;
+CONFIG PROHIBIT = R4;
+
+# Intel StrataFlash Parallel NOR Flash (SF)
+NET "SF_A<0>" LOC = "H17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<1>" LOC = "J13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<2>" LOC = "J12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<3>" LOC = "J14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<4>" LOC = "J15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<5>" LOC = "J16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<6>" LOC = "J17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<7>" LOC = "K14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<8>" LOC = "K15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<9>" LOC = "K12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<10>" LOC = "K13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<11>" LOC = "L15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<12>" LOC = "L16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<13>" LOC = "T18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<14>" LOC = "R18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<15>" LOC = "T17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<16>" LOC = "U18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<17>" LOC = "T16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<18>" LOC = "U15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<19>" LOC = "V15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<20>" LOC = "T12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<21>" LOC = "V13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<22>" LOC = "V12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<23>" LOC = "N11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<24>" LOC = "A11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_BYTE" LOC = "C17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<1>" LOC = "P10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<2>" LOC = "R10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<3>" LOC = "V9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<4>" LOC = "U9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<5>" LOC = "R9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<6>" LOC = "M9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<7>" LOC = "N9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<12>" LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<13>" LOC = "P6" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<14>" LOC = "R8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<15>" LOC = "T8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_OE" LOC = "C18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_STS" LOC = "B18" | IOSTANDARD = LVCMOS33 ;
+NET "SF_WE" LOC = "D17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+
+# STMicro SPI serial Flash (SPI)
+# some connections shared with SPI Flash, DAC, ADC, and AMP
+NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ;
+NET "SPI_MOSI" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+NET "SPI_SS_B" LOC = "U3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 | PULLUP ;
+NET "SPI_ALT_CS_JP11" LOC = "R12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+
+# Slide Switches (SW)
+NET "SW<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP | TIG;
+NET "SW<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP | TIG;
+NET "SW<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP | TIG;
+NET "SW<3>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP | TIG;
+
+# VGA Port (VGA)
+NET "VGA_BLUE" LOC = "G15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "VGA_GREEN" LOC = "H15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "VGA_HSYNC" LOC = "F15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "VGA_RED" LOC = "H14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "VGA_VSYNC" LOC = "F14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+
+# Xilinx CPLD (XC)
+NET "XC_CMD<0>" LOC = "P18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
+NET "XC_CMD<1>" LOC = "N18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
+NET "XC_CPLD_EN" LOC = "B10" | IOSTANDARD = LVTTL ;
+NET "XC_D<0>" LOC = "G16" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
+NET "XC_D<1>" LOC = "F18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
+NET "XC_D<2>" LOC = "F17" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
+NET "XC_TRIG" LOC = "R17" | IOSTANDARD = LVCMOS33 ;
+NET "XC_GCK0" LOC = "H16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "GCLK10" LOC = "C9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+
+# prohibit unused pins
+CONFIG PROHIBIT = A3;
+CONFIG PROHIBIT = A7;
+CONFIG PROHIBIT = D13;
+CONFIG PROHIBIT = F10;
+CONFIG PROHIBIT = G10;
+CONFIG PROHIBIT = C8;
+CONFIG PROHIBIT = D8;
+CONFIG PROHIBIT = A5;
+CONFIG PROHIBIT = B5;
+#
+CONFIG PROHIBIT = P13;
+CONFIG PROHIBIT = R13;
+CONFIG PROHIBIT = T14;
+CONFIG PROHIBIT = R14;
+#
+CONFIG PROHIBIT = D3;
+CONFIG PROHIBIT = F5;
+CONFIG PROHIBIT = G1;
+CONFIG PROHIBIT = J7;
+CONFIG PROHIBIT = K2;
+CONFIG PROHIBIT = K7;
+CONFIG PROHIBIT = M1;
+CONFIG PROHIBIT = N1;
+CONFIG PROHIBIT = N2;
+CONFIG PROHIBIT = R1;
+CONFIG PROHIBIT = U1;
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj
new file mode 100644
index 0000000..965ae4c
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj
@@ -0,0 +1,19 @@
+vhdl work ../top.vhd
+vhdl zpu ../../../zpu_pkg.vhdl
+vhdl zpu ../../../zpu_small.vhdl
+vhdl zpu ../../../zpu_medium.vhdl
+vhdl zpu ../../../roms/rom_pkg.vhdl
+#vhdl zpu ../../../roms/hello_dbram.vhdl
+#vhdl zpu ../../../roms/hello_bram.vhdl
+vhdl zpu ../../../roms/dmips_dbram.vhdl
+vhdl zpu ../../../roms/dmips_bram.vhdl
+vhdl zpu ../../../helpers/zpu_small1.vhdl
+vhdl zpu ../../../helpers/zpu_med1.vhdl
+vhdl zpu ../../../devices/txt_util.vhdl
+vhdl zpu ../../../devices/phi_io.vhdl
+vhdl zpu ../../../devices/timer.vhdl
+vhdl zpu ../../../devices/gpio.vhdl
+vhdl zpu ../../../devices/rx_unit.vhdl
+vhdl zpu ../../../devices/tx_unit.vhdl
+vhdl zpu ../../../devices/br_gen.vhdl
+vhdl zpu ../../../devices/trace.vhdl
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut
new file mode 100644
index 0000000..4bf13c6
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut
@@ -0,0 +1,22 @@
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g ConfigRate:1
+-g ProgPin:PullUp
+-g DonePin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g DCMShutdown:Disable
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.xst b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.xst
new file mode 100644
index 0000000..d357860
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.xst
@@ -0,0 +1,56 @@
+set -tmpdir "tmp"
+set -xsthdpdir "xst"
+run
+-ifn ../synthesis_config/top.prj
+-ifmt mixed
+-ofn top
+-ofmt NGC
+-p xc3s500e-4-fg320
+-top top
+-opt_mode Speed
+-opt_level 1
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract Yes
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-auto_bram_packing NO
+-mux_extract Yes
+-resource_sharing YES
+-async_to_sync NO
+-mult_style Auto
+-iobuf YES
+-max_fanout 500
+-bufg 24
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Yes
+-use_sync_set Yes
+-use_sync_reset Yes
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top.vhd b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top.vhd
new file mode 100644
index 0000000..4adc18b
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top.vhd
@@ -0,0 +1,464 @@
+-- top module of
+-- Spartan-3E Starter Kit Board
+--
+-- using following external connections:
+-- rotary pushbutton as reset
+-- LEDs for output
+-- RS232 (DCE, the left one)
+--
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library zpu;
+use zpu.zpupkg.all; -- zpu_dbgo_t
+
+library unisim;
+use unisim.vcomponents.dcm_sp;
+
+
+entity top is
+ port (
+ -- pragma translate_off
+ stop_simulation : out std_logic;
+ -- pragma translate_on
+ --
+ -- Analog-to-Digital Converter (ADC)
+ ad_conv : out std_logic;
+ -- Programmable Gain Amplifier (AMP)
+ amp_cs : out std_logic; -- active low chip select
+ amp_dout : in std_logic;
+ amp_shdn : out std_logic; -- active high shutdown, reset
+ -- Pushbuttons (BTN)
+ btn_east : in std_logic;
+ btn_north : in std_logic;
+ btn_south : in std_logic;
+ btn_west : in std_logic;
+ -- Clock inputs (CLK)
+ clk_50mhz : in std_logic;
+ clk_aux : in std_logic;
+ clk_sma : in std_logic;
+ -- Digital-to-Analog Converter (DAC)
+ dac_clr : out std_logic; -- async, active low reset input
+ dac_cs : out std_logic; -- active low chip select, conv start with rising edge
+ -- 1-Wire Secure EEPROM (DS)
+ ds_wire : inout std_logic;
+ -- Ethernet PHY (E)
+ e_col : in std_logic; -- MII collision detect
+ e_crs : in std_logic; -- carrier sense
+ e_mdc : out std_logic; -- management clock
+ e_mdio : inout std_logic; -- management data io
+ e_rx_clk : in std_logic; -- receive clock 25MHz@100BaseTx or 2.5MHz@10Base-T
+ e_rx_dv : in std_logic; -- receive data valid
+ e_rxd : in std_logic_vector(3 downto 0);
+ e_rx_er : in std_logic;
+ e_tx_clk : in std_logic; -- transmit clock 25MHz@100BaseTx or 2.5MHz@10Base-T
+ e_tx_en : out std_logic; -- transmit enable
+ e_txd : out std_logic_vector(3 downto 0);
+ e_tx_er : out std_logic;
+ -- FPGA Configuration Mode, INIT_B Pins (FPGA)
+ fpga_m0 : inout std_logic;
+ fpga_m1 : inout std_logic;
+ fpga_m2 : inout std_logic;
+ fpga_init_b : inout std_logic;
+ fpga_rdwr_b : in std_logic;
+ fpga_hswap : in std_logic;
+ -- FX2 Connector (FX2)
+ fx2_clkin : inout std_logic;
+ fx2_clkio : inout std_logic;
+ fx2_clkout : inout std_logic;
+ fx2_io : inout std_logic_vector(40 downto 1);
+ -- These are shared connections with the FX2 connector
+ --j1 : inout std_logic_vector(3 downto 0);
+ --j2 : inout std_logic_vector(3 downto 0);
+ --j4 : inout std_logic_vector(3 downto 0);
+ --led : out std_logic_vector(7 downto 0);
+ -- Character LCD (LCD)
+ lcd_e : out std_logic;
+ lcd_rs : out std_logic;
+ lcd_rw : out std_logic;
+ -- LCD data connections are shared with StrataFlash connections SF_D<11:8>
+ --sf_d : inout std_ulogic_vector(11 downto 8);
+ -- PS/2 Mouse/Keyboard Port (PS2)
+ ps2_clk : inout std_logic;
+ ps2_data : inout std_logic;
+ -- Rotary Pushbutton Switch (ROT)
+ rot_a : in std_logic;
+ rot_b : in std_logic;
+ rot_center : in std_logic;
+ -- RS-232 Serial Ports (RS232)
+ rs232_dce_rxd : in std_logic;
+ rs232_dce_txd : out std_logic;
+ rs232_dte_rxd : in std_logic;
+ rs232_dte_txd : out std_logic;
+ -- DDR SDRAM (SD) (I/O Bank 3, VCCO=2.5V)
+ sd_a : out std_logic_vector(12 downto 0); -- address inputs
+ sd_dq : inout std_logic_vector(15 downto 0); -- data io
+ sd_ba : out std_logic_vector(1 downto 0); -- bank address inputs
+ sd_ras : out std_logic; -- command output
+ sd_cas : out std_logic; -- command output
+ sd_we : out std_logic; -- command output
+ sd_udm : out std_logic; -- data mask
+ sd_ldm : out std_logic; -- data mask
+ sd_udqs : inout std_logic; -- data strobe
+ sd_ldqs : inout std_logic; -- data strobe
+ sd_cs : out std_logic; -- active low chip select
+ sd_cke : out std_logic; -- active high clock enable
+ sd_ck_n : out std_logic; -- differential clock
+ sd_ck_p : out std_logic; -- differential clock
+ -- Path to allow connection to top DCM connection
+ sd_ck_fb : in std_logic;
+ -- Intel StrataFlash Parallel NOR Flash (SF)
+ sf_a : out std_logic_vector(23 downto 0); -- sf_a<24> = fx_io32
+ sf_byte : out std_logic;
+ sf_ce0 : out std_logic;
+ sf_d : inout std_logic_vector(15 downto 1);
+ sf_oe : out std_logic;
+ sf_sts : in std_logic;
+ sf_we : out std_logic;
+ -- STMicro SPI serial Flash (SPI)
+ spi_mosi : out std_logic; -- master out slave in
+ spi_miso : in std_logic; -- master in slave out
+ spi_sck : out std_logic; -- clock
+ spi_ss_b : out std_logic; -- active low slave select
+ spi_alt_cs_jp11 : out std_logic;
+ -- Slide Switches (SW)
+ sw : in std_logic_vector(3 downto 0);
+ -- VGA Port (VGA)
+ vga_blue : out std_logic;
+ vga_green : out std_logic;
+ vga_hsync : out std_logic;
+ vga_red : out std_logic;
+ vga_vsync : out std_logic;
+ -- Xilinx CPLD (XC)
+ xc_cmd : out std_logic_vector(1 downto 0);
+ xc_cpld_en : out std_logic;
+ xc_d : inout std_logic_vector(2 downto 0);
+ xc_trig : in std_logic;
+ xc_gck0 : inout std_logic;
+ gclk10 : inout std_logic
+ );
+end entity top;
+
+
+architecture rtl of top is
+
+ ---------------------------
+ -- type declarations
+ type zpu_type is (zpu_small, zpu_medium);
+
+ ---------------------------
+ -- constant declarations
+ constant zpu_flavour : zpu_type := zpu_medium; -- choose your flavour HERE
+ -- modify frequency here
+ constant clk_multiply : positive := 3; -- 2 for small, 3 for medium
+ constant clk_divide : positive := 2; -- 1 for small, 2 for medium
+ --
+ constant word_size_c : natural := 32; -- 32 bits data path
+ constant addr_w_c : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O
+
+
+ constant spi_ss_b_disable : std_ulogic := '1'; -- 1 = disable SPI serial flash
+ constant dac_cs_disable : std_ulogic := '1'; -- 1 = disable DAC
+ constant amp_cs_disable : std_ulogic := '1'; -- 1 = disable programmable pre-amplifier
+ constant ad_conv_disable : std_ulogic := '0'; -- 0 = disable ADC
+ constant sf_ce0_disable : std_ulogic := '1';
+ constant fpga_init_b_disable : std_ulogic := '1'; -- 1 = disable pflatform flash PROM
+ --
+ -- connect ldc to fpga
+ constant sf_ce0_lcd_to_fpga : std_ulogic := '1';
+ --
+ constant clk_frequency : positive := 50; -- input frequency for correct calculation
+
+
+ ---------------------------
+ -- component declarations
+ component zpu_small1 is
+ generic (
+ word_size : natural := 32; -- 32 bits data path
+ d_care_val : std_logic := '0'; -- Fill value
+ clk_freq : positive := 50; -- 50 MHz clock
+ brate : positive := 115200; -- RS232 baudrate
+ addr_w : natural := 16; -- 16 bits address space=64 kB, 32 kB I/O
+ bram_w : natural := 15 -- 15 bits RAM space=32 kB
+ );
+ port (
+ clk_i : in std_logic; -- CPU clock
+ rst_i : in std_logic; -- Reset
+ break_o : out std_logic; -- Break executed
+ dbg_o : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o : out std_logic; -- UART Tx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end component zpu_small1;
+
+ component zpu_med1 is
+ generic(
+ word_size : natural := 32; -- 32 bits data path
+ d_care_val : std_logic := '0'; -- Fill value
+ clk_freq : positive := 50; -- 50 MHz clock
+ brate : positive := 115200; -- RS232 baudrate
+ addr_w : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O
+ bram_w : natural := 15 -- 15 bits RAM space=32 kB
+ );
+ port(
+ clk_i : in std_logic; -- CPU clock
+ rst_i : in std_logic; -- Reset
+ break_o : out std_logic; -- Break executed
+ dbg_o : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o : out std_logic; -- UART Tx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end component zpu_med1;
+
+
+ ---------------------------
+ -- signal declarations
+ signal dcm_sp_i0_clk0 : std_ulogic;
+ signal dcm_sp_i0_clkfx : std_ulogic;
+ signal clk_fb : std_ulogic;
+ signal clk : std_ulogic;
+ --
+ signal reset_shift_reg : std_ulogic_vector(3 downto 0);
+ signal reset_sync : std_ulogic;
+ --
+ signal zpu_i0_dbg : zpu_dbgo_t; -- Debug info
+ signal zpu_i0_break : std_logic;
+ --
+ signal gpio_in : std_logic_vector(31 downto 0);
+ signal zpu_i0_gpio_out : std_logic_vector(31 downto 0);
+ signal zpu_i0_gpio_dir : std_logic_vector(31 downto 0);
+
+ ---------------------------
+ -- alias declarations
+ alias led : std_logic_vector(7 downto 0) is fx2_io(20 downto 13);
+
+
+begin
+
+ -- default output drivers
+ -- to pass bitgen DRC
+ -- outputs used by design are commented
+ --
+ ad_conv <= ad_conv_disable;
+ amp_cs <= amp_cs_disable;
+ amp_shdn <= '1';
+ --
+ dac_clr <= '0';
+ dac_cs <= dac_cs_disable;
+ --
+ ds_wire <= 'Z';
+ --
+ e_txd(3 downto 0) <= (others => '1');
+ e_tx_en <= '0';
+ e_tx_er <= '0';
+ e_mdc <= '1';
+ e_mdio <= 'Z';
+ --
+ fpga_m0 <= 'Z';
+ fpga_m1 <= 'Z';
+ fpga_m2 <= 'Z';
+ fpga_init_b <= fpga_init_b_disable;
+ --
+ fx2_clkin <= 'Z';
+ fx2_clkio <= 'Z';
+ fx2_clkout <= 'Z';
+ fx2_io <= (others => 'Z');
+ --
+ lcd_e <= '0';
+ lcd_rs <= '0';
+ lcd_rw <= '0';
+ --
+ ps2_clk <= 'Z';
+ ps2_data <= 'Z';
+ --
+ --rs232_dce_txd <= '1';
+ rs232_dte_txd <= '1';
+ --
+ sd_a <= (others => '1');
+ sd_dq <= (others => 'Z');
+ sd_ba <= (others => '1');
+ sd_ras <= '0';
+ sd_cas <= '0';
+ sd_we <= '0';
+ sd_udm <= '1';
+ sd_ldm <= '1';
+ sd_udqs <= '1';
+ sd_ldqs <= '1';
+ sd_cs <= '1';
+ sd_cke <= '1';
+ sd_ck_n <= '0';
+ sd_ck_p <= '1';
+ --
+ sf_a <= (others => '0');
+ sf_byte <= '0';
+ sf_ce0 <= sf_ce0_lcd_to_fpga;
+ sf_d <= (others => 'Z');
+ sf_oe <= '1';
+ sf_we <= '0';
+ --
+ spi_mosi <= '0';
+ spi_sck <= '0';
+ spi_ss_b <= spi_ss_b_disable;
+ spi_alt_cs_jp11 <= spi_ss_b_disable;
+ --
+ vga_red <= '0';
+ vga_green <= '0';
+ vga_blue <= '0';
+ vga_hsync <= '0';
+ vga_vsync <= '0';
+ --
+ xc_cmd <= "00";
+ xc_d <= (others => 'Z');
+ xc_cpld_en <= '0';
+ xc_gck0 <= 'Z';
+ gclk10 <= 'Z';
+ -- led out
+ --fx2_io(20 downto 13) <= (others => '0');
+
+
+ -- digital clock manager (DCM)
+ -- to generate higher/other system clock frequencys
+ dcm_sp_i0 : dcm_sp
+ generic map (
+ startup_wait => true, -- wait with DONE till locked
+ clkfx_multiply => clk_multiply,
+ clkfx_divide => clk_divide,
+ clk_feedback => "1X"
+ )
+ port map (
+ clkin => clk_50mhz,
+ clk0 => dcm_sp_i0_clk0,
+ clkfx => dcm_sp_i0_clkfx,
+ clkfb => clk_fb
+ );
+
+ clk_fb <= dcm_sp_i0_clk0;
+ clk <= dcm_sp_i0_clkfx;
+
+
+ -- reset synchronizer
+ -- generate synchronous reset
+ reset_synchronizer : process(clk, rot_center)
+ begin
+ if rot_center = '1' then
+ reset_shift_reg <= (others => '1');
+ elsif rising_edge(clk) then
+ reset_shift_reg <= reset_shift_reg(reset_shift_reg'high-1 downto 0) & '0';
+ end if;
+ end process;
+ reset_sync <= reset_shift_reg(reset_shift_reg'high);
+
+
+ -- select instance of zpu
+ zpu_i0_small : if zpu_flavour = zpu_small generate
+ zpu_i0 : zpu_small1
+ generic map (
+ addr_w => addr_w_c,
+ word_size => word_size_c,
+ clk_freq => clk_frequency * clk_multiply / clk_divide
+ )
+ port map (
+ clk_i => clk, -- : in std_logic; -- CPU clock
+ rst_i => reset_sync, -- : in std_logic; -- Reset
+ break_o => zpu_i0_break, -- : out std_logic; -- Break executed
+ dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o => rs232_dce_txd, -- : out std_logic; -- UART Tx
+ rs232_rx_i => rs232_dce_rxd, -- : in std_logic -- UART Rx
+ gpio_in => gpio_in, -- : in std_logic_vector(31 downto 0);
+ gpio_out => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
+ gpio_dir => zpu_i0_gpio_dir -- : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end generate zpu_i0_small;
+
+ zpu_i0_medium : if zpu_flavour = zpu_medium generate
+ zpu_i0 : zpu_med1
+ generic map (
+ addr_w => addr_w_c,
+ word_size => word_size_c,
+ clk_freq => clk_frequency * clk_multiply / clk_divide
+ )
+ port map (
+ clk_i => clk, -- : in std_logic; -- CPU clock
+ rst_i => reset_sync, -- : in std_logic; -- Reset
+ break_o => zpu_i0_break, -- : out std_logic; -- Break executed
+ dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o => rs232_dce_txd, -- : out std_logic; -- UART Tx
+ rs232_rx_i => rs232_dce_rxd, -- : in std_logic -- UART Rx
+ gpio_in => gpio_in, -- : in std_logic_vector(31 downto 0);
+ gpio_out => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
+ gpio_dir => zpu_i0_gpio_dir -- : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end generate zpu_i0_medium;
+
+
+ -- pragma translate_off
+ stop_simulation <= zpu_i0_break;
+
+
+ trace_mod : trace
+ generic map (
+ addr_w => addr_w_c,
+ word_size => word_size_c,
+ log_file => "zpu_trace.log"
+ )
+ port map (
+ clk_i => clk,
+ dbg_i => zpu_i0_dbg,
+ stop_i => zpu_i0_break,
+ busy_i => '0'
+ );
+ -- pragma translate_on
+
+
+ -- assign GPIOs
+ -- no bidirectional pins (e.g. headers), so
+ -- gpio_dir is unused
+ --
+ -- bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
+ --
+ -- in -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ -- out -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ --
+ --
+ -- bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+ --
+ -- in -- -- -- -- sw(3.....0) -- ra rb rc be bn bs bw
+ -- out -- -- -- -- -- -- -- -- led(7................0)
+
+ gpio_in <= ((11) => sw(3),
+ (10) => sw(2),
+ ( 9) => sw(1),
+ ( 8) => sw(0),
+ --
+ ( 6) => rot_a,
+ ( 5) => rot_b,
+ ( 4) => rot_center,
+ --
+ ( 3) => btn_east,
+ ( 2) => btn_north,
+ ( 1) => btn_south,
+ ( 0) => btn_west,
+ others => '0');
+
+
+ -- switch on all LEDs in case of break
+ process
+ begin
+ wait until rising_edge(clk);
+ led <= zpu_i0_gpio_out(7 downto 0);
+ if zpu_i0_break = '1' then
+ led <= (others => '1');
+ end if;
+ end process;
+
+
+
+end architecture rtl;
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top_tb.vhd b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top_tb.vhd
new file mode 100644
index 0000000..d62bed9
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top_tb.vhd
@@ -0,0 +1,281 @@
+-- testbench for
+-- Digilent Spartan 3E Starter Board
+--
+-- includes "model" for clock generation
+-- simulate press on Rotary Pushbutton Switch as reset
+--
+-- place models for external components (PHY, SDRAM) in this file
+--
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity top_tb is
+end entity top_tb;
+
+architecture testbench of top_tb is
+
+ ---------------------------
+ -- constant declarations
+ constant clk_50mhz_period : time := 1 sec / 50_000_000; -- 50 MHz
+
+
+ ---------------------------
+ -- signal declarations
+ signal simulation_run : boolean := true;
+ signal tb_stop_simulation : std_logic;
+ --
+ -- Analog-to-Digital Converter (ADC)
+ signal tb_ad_conv : std_logic;
+ -- Programmable Gain Amplifier (AMP)
+ signal tb_amp_cs : std_logic; -- active low chip select
+ signal tb_amp_dout : std_logic := '1';
+ signal tb_amp_shdn : std_logic; -- active high shutdown, reset
+ -- Pushbuttons (BTN)
+ signal tb_btn_east : std_logic := '0';
+ signal tb_btn_north : std_logic := '0';
+ signal tb_btn_south : std_logic := '0';
+ signal tb_btn_west : std_logic := '0';
+ -- Clock inputs (CLK)
+ signal tb_clk_50mhz : std_logic := '0';
+ signal tb_clk_aux : std_logic := '0';
+ signal tb_clk_sma : std_logic := '0';
+ -- Digital-to-Analog Converter (DAC)
+ signal tb_dac_clr : std_logic; -- async, active low reset input
+ signal tb_dac_cs : std_logic; -- active low chip select, conv start with rising edge
+ -- 1-Wire Secure EEPROM (DS)
+ signal tb_ds_wire : std_logic;
+ -- Ethernet PHY (E)
+ signal tb_e_col : std_logic := '0'; -- MII collision detect
+ signal tb_e_crs : std_logic := '0'; -- carrier sense
+ signal tb_e_mdc : std_logic; -- management clock
+ signal tb_e_mdio : std_logic; -- management data io
+ signal tb_e_rx_clk : std_logic := '0'; -- receive clock 25MHz@100BaseTx or 2.5MHz@10Base-T
+ signal tb_e_rx_dv : std_logic := '0'; -- receive data valid
+ signal tb_e_rxd : std_logic_vector(3 downto 0) := (others => '0');
+ signal tb_e_rx_er : std_logic := '0';
+ signal tb_e_tx_clk : std_logic := '0'; -- transmit clock 25MHz@100BaseTx or 2.5MHz@10Base-T
+ signal tb_e_tx_en : std_logic; -- transmit enable
+ signal tb_e_txd : std_logic_vector(3 downto 0);
+ signal tb_e_tx_er : std_logic;
+ -- FPGA Configuration Mode, INIT_B Pins (FPGA)
+ signal tb_fpga_m0 : std_logic;
+ signal tb_fpga_m1 : std_logic;
+ signal tb_fpga_m2 : std_logic;
+ signal tb_fpga_init_b : std_logic;
+ signal tb_fpga_rdwr_b : std_logic := '0';
+ signal tb_fpga_hswap : std_logic := '0';
+ -- FX2 Connector (FX2)
+ signal tb_fx2_clkin : std_logic;
+ signal tb_fx2_clkio : std_logic;
+ signal tb_fx2_clkout : std_logic;
+ signal tb_fx2_io : std_logic_vector(40 downto 1);
+ -- Character LCD (LCD)
+ signal tb_lcd_e : std_logic;
+ signal tb_lcd_rs : std_logic;
+ signal tb_lcd_rw : std_logic;
+ -- LCD data connections are shared with StrataFlash connections SF_D<11:8>
+ -- PS/2 Mouse/Keyboard Port (PS2)
+ signal tb_ps2_clk : std_logic;
+ signal tb_ps2_data : std_logic;
+ -- Rotary Pushbutton Switch (ROT)
+ signal tb_rot_a : std_logic := '0';
+ signal tb_rot_b : std_logic := '0';
+ signal tb_rot_center : std_logic; -- use as reset
+ -- RS-232 Serial Ports (RS232)
+ signal tb_rs232_dce_rxd : std_logic := '1';
+ signal tb_rs232_dce_txd : std_logic;
+ signal tb_rs232_dte_rxd : std_logic := '1';
+ signal tb_rs232_dte_txd : std_logic;
+ -- DDR SDRAM (SD) (I/O Bank 3, VCCO=2.5V)
+ signal tb_sd_a : std_logic_vector(12 downto 0); -- address inputs
+ signal tb_sd_dq : std_logic_vector(15 downto 0); -- data io
+ signal tb_sd_ba : std_logic_vector(1 downto 0); -- bank address inputs
+ signal tb_sd_ras : std_logic; -- command output
+ signal tb_sd_cas : std_logic; -- command output
+ signal tb_sd_we : std_logic; -- command output
+ signal tb_sd_udm : std_logic; -- data mask
+ signal tb_sd_ldm : std_logic; -- data mask
+ signal tb_sd_udqs : std_logic; -- data strobe
+ signal tb_sd_ldqs : std_logic; -- data strobe
+ signal tb_sd_cs : std_logic; -- active low chip select
+ signal tb_sd_cke : std_logic; -- active high clock enable
+ signal tb_sd_ck_n : std_logic; -- differential clock
+ signal tb_sd_ck_p : std_logic; -- differential clock
+ -- Path to allow connection to top DCM connection
+ signal tb_sd_ck_fb : std_logic;
+ -- Intel StrataFlash Parallel NOR Flash (SF)
+ signal tb_sf_a : std_logic_vector(23 downto 0); -- sf_a<24> = fx_io32 :-(
+ signal tb_sf_byte : std_logic;
+ signal tb_sf_ce0 : std_logic;
+ signal tb_sf_d : std_logic_vector(15 downto 1);
+ signal tb_sf_oe : std_logic;
+ signal tb_sf_sts : std_logic := '0';
+ signal tb_sf_we : std_logic;
+ -- STMicro SPI serial Flash (SPI)
+ signal tb_spi_mosi : std_logic; -- master out slave in
+ signal tb_spi_miso : std_logic := '0'; -- master in slave out
+ signal tb_spi_sck : std_logic; -- clock
+ signal tb_spi_ss_b : std_logic; -- active low slave select
+ signal tb_spi_alt_cs_jp11 : std_logic;
+ -- Slide Switches (SW)
+ signal tb_sw : std_logic_vector(3 downto 0) := (others => '0');
+ -- VGA Port (VGA)
+ signal tb_vga_blue : std_logic;
+ signal tb_vga_green : std_logic;
+ signal tb_vga_hsync : std_logic;
+ signal tb_vga_red : std_logic;
+ signal tb_vga_vsync : std_logic;
+ -- Xilinx CPLD (XC)
+ signal tb_xc_cmd : std_logic_vector(1 downto 0);
+ signal tb_xc_cpld_en : std_logic;
+ signal tb_xc_d : std_logic_vector(2 downto 0);
+ signal tb_xc_trig : std_logic := '0';
+ signal tb_xc_gck0 : std_logic;
+ signal tb_gclk10 : std_logic;
+
+
+begin
+
+
+ -- generate clock
+ tb_clk_50mhz <= not tb_clk_50mhz after clk_50mhz_period / 2 when simulation_run;
+
+ -- generate reset
+ tb_rot_center <= '1', '0' after 6.66 * clk_50mhz_period;
+
+
+ -- clock feedback for SD-RAM (on board)
+ tb_sd_ck_fb <= tb_sd_ck_p;
+
+ -- simulate keypress
+ tb_btn_north <= '0', '1' after 55 us, '0' after 56 us;
+
+ -- dut
+ top_i0 : entity work.top
+ port map (
+ stop_simulation => tb_stop_simulation, -- : out std_logic;
+ -- Analog-to-Digital Converter (ADC)
+ ad_conv => tb_ad_conv, -- : out std_logic;
+ -- Programmable Gain Amplifier (AMP)
+ amp_cs => tb_amp_cs, -- : out std_logic;
+ amp_dout => tb_amp_dout, -- : in std_logic;
+ amp_shdn => tb_amp_shdn, -- : out std_logic;
+ -- Pushbuttons (BTN)
+ btn_east => tb_btn_east, -- : in std_logic;
+ btn_north => tb_btn_north, -- : in std_logic;
+ btn_south => tb_btn_south, -- : in std_logic;
+ btn_west => tb_btn_west, -- : in std_logic;
+ -- Clock inputs (CLK)
+ clk_50mhz => tb_clk_50mhz, -- : in std_logic;
+ clk_aux => tb_clk_aux, -- : in std_logic;
+ clk_sma => tb_clk_sma, -- : in std_logic;
+ -- Digital-to-Analog Converter (DAC)
+ dac_clr => tb_dac_clr, -- : out std_logic;
+ dac_cs => tb_dac_cs, -- : out std_logic;
+ -- 1-Wire Secure EEPROM (DS)
+ ds_wire => tb_ds_wire, -- : inout std_logic;
+ -- Ethernet PHY (E)
+ e_col => tb_e_col, -- : in std_logic;
+ e_crs => tb_e_crs, -- : in std_logic;
+ e_mdc => tb_e_mdc, -- : out std_logic;
+ e_mdio => tb_e_mdio, -- : inout std_logic;
+ e_rx_clk => tb_e_rx_clk, -- : in std_logic;
+ e_rx_dv => tb_e_rx_dv, -- : in std_logic;
+ e_rxd => tb_e_rxd, -- : in std_logic_vector(3 downto 0);
+ e_rx_er => tb_e_rx_er, -- : in std_logic;
+ e_tx_clk => tb_e_tx_clk, -- : in std_logic;
+ e_tx_en => tb_e_tx_en, -- : out std_logic;
+ e_txd => tb_e_txd, -- : out std_logic_vector(3 downto 0);
+ e_tx_er => tb_e_tx_er, -- : out std_logic;
+ -- FPGA Configuration Mode, INIT_B Pins (FPGA)
+ fpga_m0 => tb_fpga_m0, -- : inout std_logic;
+ fpga_m1 => tb_fpga_m1, -- : inout std_logic;
+ fpga_m2 => tb_fpga_m2, -- : inout std_logic;
+ fpga_init_b => tb_fpga_init_b, -- : inout std_logic;
+ fpga_rdwr_b => tb_fpga_rdwr_b, -- : in std_logic;
+ fpga_hswap => tb_fpga_hswap, -- : in std_logic;
+ -- FX2 Connector (FX2)
+ fx2_clkin => tb_fx2_clkin, -- : inout std_logic;
+ fx2_clkio => tb_fx2_clkio, -- : inout std_logic;
+ fx2_clkout => tb_fx2_clkout, -- : inout std_logic;
+ fx2_io => tb_fx2_io, -- : inout std_logic_vector(40 downto 1);
+ -- Character LCD (LCD)
+ lcd_e => tb_lcd_e, -- : out std_logic;
+ lcd_rs => tb_lcd_rs, -- : out std_logic;
+ lcd_rw => tb_lcd_rw, -- : out std_logic;
+ -- LCD data connections are shared with StrataFlash connections SF_D<11:8>
+ -- PS/2 Mouse/Keyboard Port (PS2)
+ ps2_clk => tb_ps2_clk, -- : inout std_logic;
+ ps2_data => tb_ps2_data, -- : inout std_logic;
+ -- Rotary Pushbutton Switch (ROT)
+ rot_a => tb_rot_a, -- : in std_logic;
+ rot_b => tb_rot_b, -- : in std_logic;
+ rot_center => tb_rot_center, -- : in std_logic;
+ -- RS-232 Serial Ports (RS232)
+ rs232_dce_rxd => tb_rs232_dce_rxd, -- : in std_logic;
+ rs232_dce_txd => tb_rs232_dce_txd, -- : out std_logic;
+ rs232_dte_rxd => tb_rs232_dte_rxd, -- : in std_logic;
+ rs232_dte_txd => tb_rs232_dte_txd, -- : out std_logic;
+ -- DDR SDRAM (SD) (I/O Bank 3, VCCO=2.5V)
+ sd_a => tb_sd_a, -- : out std_logic_vector(12 downto 0);
+ sd_dq => tb_sd_dq, -- : inout std_logic_vector(15 downto 0);
+ sd_ba => tb_sd_ba, -- : out std_logic_vector(1 downto 0);
+ sd_ras => tb_sd_ras, -- : out std_logic;
+ sd_cas => tb_sd_cas, -- : out std_logic;
+ sd_we => tb_sd_we, -- : out std_logic;
+ sd_udm => tb_sd_udm, -- : out std_logic;
+ sd_ldm => tb_sd_ldm, -- : out std_logic;
+ sd_udqs => tb_sd_udqs, -- : inout std_logic;
+ sd_ldqs => tb_sd_ldqs, -- : inout std_logic;
+ sd_cs => tb_sd_cs, -- : out std_logic;
+ sd_cke => tb_sd_cke, -- : out std_logic;
+ sd_ck_n => tb_sd_ck_n, -- : out std_logic;
+ sd_ck_p => tb_sd_ck_p, -- : out std_logic;
+ -- Path to allow connection to top DCM connection
+ sd_ck_fb => tb_sd_ck_fb, -- : in std_logic;
+ -- Intel StrataFlash Parallel NOR Flash (SF)
+ sf_a => tb_sf_a, -- : out std_logic_vector(23 downto 0);
+ sf_byte => tb_sf_byte, -- : out std_logic;
+ sf_ce0 => tb_sf_ce0, -- : out std_logic;
+ sf_d => tb_sf_d, -- : inout std_logic_vector(15 downto 1);
+ sf_oe => tb_sf_oe, -- : out std_logic;
+ sf_sts => tb_sf_sts, -- : in std_logic;
+ sf_we => tb_sf_we, -- : out std_logic;
+ -- STMicro SPI serial Flash (SPI)
+ spi_mosi => tb_spi_mosi, -- : out std_logic;
+ spi_miso => tb_spi_miso, -- : in std_logic;
+ spi_sck => tb_spi_sck, -- : out std_logic;
+ spi_ss_b => tb_spi_ss_b, -- : out std_logic;
+ spi_alt_cs_jp11 => tb_spi_alt_cs_jp11, -- : out std_logic;
+ -- Slide Switches (SW)
+ sw => tb_sw, -- : in std_logic_vector(3 downto 0);
+ -- VGA Port (VGA)
+ vga_blue => tb_vga_blue, -- : out std_logic;
+ vga_green => tb_vga_green, -- : out std_logic;
+ vga_hsync => tb_vga_hsync, -- : out std_logic;
+ vga_red => tb_vga_red, -- : out std_logic;
+ vga_vsync => tb_vga_vsync, -- : out std_logic;
+ -- Xilinx CPLD (XC)
+ xc_cmd => tb_xc_cmd, -- : out std_logic_vector(1 downto 0);
+ xc_cpld_en => tb_xc_cpld_en, -- : out std_logic;
+ xc_d => tb_xc_d, -- : inout std_logic_vector(2 downto 0);
+ xc_trig => tb_xc_trig, -- : in std_logic;
+ xc_gck0 => tb_xc_gck0, -- : inout std_logic;
+ gclk10 => tb_gclk10 -- : inout std_logic
+ );
+
+
+ -- check for simulation stopping
+ process (tb_stop_simulation)
+ begin
+ if tb_stop_simulation = '1' then
+ report "Simulation end." severity note;
+ simulation_run <= false;
+ end if;
+ end process;
+
+
+end architecture testbench;
diff --git a/zpu/hdl/zealot/fpga/dmips_med1.vhdl b/zpu/hdl/zealot/fpga/dmips_med1.vhdl
new file mode 100644
index 0000000..b95016c
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/dmips_med1.vhdl
@@ -0,0 +1,119 @@
+------------------------------------------------------------------------------
+---- ----
+---- ZPU Medium connection to the FPGA pins ----
+---- ----
+---- http://www.opencores.org/ ----
+---- ----
+---- Description: ----
+---- This module connects the ZPU_Med1 (zpu_med1.vhdl) core to a Spartan ----
+---- 3 1500 Xilinx FPGA available in the GR-XC3S board from Pender. ----
+---- ----
+---- To Do: ----
+---- - ----
+---- ----
+---- Author: ----
+---- - Salvador E. Tropea, salvador inti.gob.ar ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
+---- ----
+---- Distributed under the GPL license ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Design unit: DMIPS_Med1(FPGA) (Entity and architecture) ----
+---- File name: dmips_med1.vhdl ----
+---- Note: None ----
+---- Limitations: None known ----
+---- Errors: None known ----
+---- Library: work ----
+---- Dependencies: IEEE.std_logic_1164 ----
+---- IEEE.numeric_std ----
+---- zpu.zpu_pkg ----
+---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
+---- Language: VHDL ----
+---- Wishbone: No ----
+---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
+---- Simulation tools: N/A ----
+---- Text editor: SETEdit 0.5.x ----
+---- ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library zpu;
+use zpu.zpupkg.all;
+
+entity DMIPS_Med1 is
+ generic(
+ WORD_SIZE : natural:=32; -- 32 bits data path
+ D_CARE_VAL : std_logic:='0'; -- Fill value, I got better results with it
+ CLK_FREQ : positive:=50; -- 50 MHz clock
+ BRATE : positive:=115200; -- RS-232 baudrate
+ ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O
+ BRAM_W : natural:=15); -- 15 bits RAM space=32 kB
+ port(
+ clk_i : in std_logic; -- CPU clock
+ rst_i : in std_logic; -- Reset
+ rs232_tx_o : out std_logic; -- UART Tx
+ rs232_rx_i : in std_logic); -- UART Rx
+
+ constant BRD_PB1_I : string:="D19"; -- SWITCH8==S2
+ constant BRD_CLK1_I : string:="AA12"; -- 50 MHz clock
+ --constant BRD_CLK1_I : string:="AB12"; -- 40 MHz clock
+ -- UART: direct 1:1 cable
+ constant BRD_TX_O : string:="L4"; -- UART 1 (J1) TXD1 DB9 pin 2
+ constant BRD_RX_I : string:="L3"; -- UART 1 (J1) RXD1 DB9 pin 3
+
+ ------------
+ -- Pinout --
+ ------------
+ attribute LOC : string;
+ attribute IOSTANDARD : string;
+ constant IOSTD : string:="LVTTL";
+
+ attribute LOC of rst_i : signal is BRD_PB1_I;
+ attribute IOSTANDARD of rst_i : signal is IOSTD;
+ attribute LOC of clk_i : signal is BRD_CLK1_I;
+ attribute LOC of rs232_tx_o : signal is BRD_TX_O;
+ attribute IOSTANDARD of rs232_tx_o : signal is IOSTD;
+ attribute LOC of rs232_rx_i : signal is BRD_RX_I;
+ attribute IOSTANDARD of rs232_rx_i : signal is IOSTD;
+end entity DMIPS_Med1;
+
+architecture FPGA of DMIPS_Med1 is
+ component ZPU_Med1 is
+ generic(
+ WORD_SIZE : natural:=32; -- 32 bits data path
+ D_CARE_VAL : std_logic:='X'; -- Fill value
+ CLK_FREQ : positive:=50; -- 50 MHz clock
+ BRATE : positive:=9600; -- RS232 baudrate
+ ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O
+ BRAM_W : natural:=15); -- 15 bits RAM space=32 kB
+ port(
+ clk_i : in std_logic; -- CPU clock
+ rst_i : in std_logic; -- Reset
+ break_o : out std_logic; -- Break executed
+ dbg_o : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o : out std_logic; -- UART Tx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end component ZPU_Med1;
+begin
+ zpu : ZPU_Med1
+ generic map(
+ WORD_SIZE => WORD_SIZE, D_CARE_VAL => D_CARE_VAL,
+ CLK_FREQ => CLK_FREQ, BRATE => BRATE, ADDR_W => ADDR_W,
+ BRAM_W => BRAM_W)
+ port map(
+ clk_i => clk_i, rst_i => rst_i, rs232_tx_o => rs232_tx_o,
+ rs232_rx_i => rs232_rx_i, dbg_o => open, gpio_in => (others => '0'));
+end architecture FPGA; -- Entity: DMIPS_Med1
+
diff --git a/zpu/hdl/zealot/fpga/dmips_small1.vhdl b/zpu/hdl/zealot/fpga/dmips_small1.vhdl
new file mode 100644
index 0000000..6edec00
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/dmips_small1.vhdl
@@ -0,0 +1,120 @@
+------------------------------------------------------------------------------
+---- ----
+---- ZPU Small connection to the FPGA pins ----
+---- ----
+---- http://www.opencores.org/ ----
+---- ----
+---- Description: ----
+---- This module connects the ZPU_Small1 (zpu_small1.vhdl) core to a ----
+---- Spartan 3 1500 Xilinx FPGA available in the GR-XC3S board from ----
+---- Pender. ----
+---- ----
+---- To Do: ----
+---- - ----
+---- ----
+---- Author: ----
+---- - Salvador E. Tropea, salvador inti.gob.ar ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
+---- ----
+---- Distributed under the GPL license ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Design unit: DMIPS_Small1(FPGA) (Entity and architecture) ----
+---- File name: dmips_small1.vhdl ----
+---- Note: None ----
+---- Limitations: None known ----
+---- Errors: None known ----
+---- Library: work ----
+---- Dependencies: IEEE.std_logic_1164 ----
+---- IEEE.numeric_std ----
+---- zpu.zpu_pkg ----
+---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
+---- Language: VHDL ----
+---- Wishbone: No ----
+---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
+---- Simulation tools: N/A ----
+---- Text editor: SETEdit 0.5.x ----
+---- ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library zpu;
+use zpu.zpupkg.all;
+
+entity DMIPS_Small1 is
+ generic(
+ WORD_SIZE : natural:=32; -- 32 bits data path
+ D_CARE_VAL : std_logic:='0'; -- Fill value, I got better results with it
+ CLK_FREQ : positive:=50; -- 50 MHz clock
+ BRATE : positive:=115200; -- RS-232 baudrate
+ ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O
+ BRAM_W : natural:=15); -- 15 bits RAM space=32 kB
+ port(
+ clk_i : in std_logic; -- CPU clock
+ rst_i : in std_logic; -- Reset
+ rs232_tx_o : out std_logic; -- UART Tx
+ rs232_rx_i : in std_logic); -- UART Rx
+
+ constant BRD_PB1_I : string:="D19"; -- SWITCH8==S2
+ constant BRD_CLK1_I : string:="AA12"; -- 50 MHz clock
+ --constant BRD_CLK1_I : string:="AB12"; -- 40 MHz clock
+ -- UART: direct 1:1 cable
+ constant BRD_TX_O : string:="L4"; -- UART 1 (J1) TXD1 DB9 pin 2
+ constant BRD_RX_I : string:="L3"; -- UART 1 (J1) RXD1 DB9 pin 3
+
+ ------------
+ -- Pinout --
+ ------------
+ attribute LOC : string;
+ attribute IOSTANDARD : string;
+ constant IOSTD : string:="LVTTL";
+
+ attribute LOC of rst_i : signal is BRD_PB1_I;
+ attribute IOSTANDARD of rst_i : signal is IOSTD;
+ attribute LOC of clk_i : signal is BRD_CLK1_I;
+ attribute LOC of rs232_tx_o : signal is BRD_TX_O;
+ attribute IOSTANDARD of rs232_tx_o : signal is IOSTD;
+ attribute LOC of rs232_rx_i : signal is BRD_RX_I;
+ attribute IOSTANDARD of rs232_rx_i : signal is IOSTD;
+end entity DMIPS_Small1;
+
+architecture FPGA of DMIPS_Small1 is
+ component ZPU_Small1 is
+ generic(
+ WORD_SIZE : natural:=32; -- 32 bits data path
+ D_CARE_VAL : std_logic:='0'; -- Fill value
+ CLK_FREQ : positive:=50; -- 50 MHz clock
+ BRATE : positive:=115200; -- RS232 baudrate
+ ADDR_W : natural:=16; -- 16 bits address space=64 kB, 32 kB I/O
+ BRAM_W : natural:=15); -- 15 bits RAM space=32 kB
+ port(
+ clk_i : in std_logic; -- CPU clock
+ rst_i : in std_logic; -- Reset
+ break_o : out std_logic; -- Break executed
+ dbg_o : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o : out std_logic; -- UART Tx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end component ZPU_Small1;
+begin
+ zpu : ZPU_Small1
+ generic map(
+ WORD_SIZE => WORD_SIZE, D_CARE_VAL => D_CARE_VAL,
+ CLK_FREQ => CLK_FREQ, BRATE => BRATE, ADDR_W => ADDR_W,
+ BRAM_W => BRAM_W)
+ port map(
+ clk_i => clk_i, rst_i => rst_i, rs232_tx_o => rs232_tx_o,
+ rs232_rx_i => rs232_rx_i, dbg_o => open, gpio_in => (others => '0'));
+end architecture FPGA; -- Entity: DMIPS_Small1
+
diff --git a/zpu/hdl/zealot/fpga/hello_med1.vhdl b/zpu/hdl/zealot/fpga/hello_med1.vhdl
new file mode 100644
index 0000000..5ffea1f
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/hello_med1.vhdl
@@ -0,0 +1,119 @@
+------------------------------------------------------------------------------
+---- ----
+---- ZPU Medium connection to the FPGA pins ----
+---- ----
+---- http://www.opencores.org/ ----
+---- ----
+---- Description: ----
+---- This module connects the ZPU_Med1 (zpu_med1.vhdl) core to a Spartan ----
+---- 3 1500 Xilinx FPGA available in the GR-XC3S board from Pender. ----
+---- ----
+---- To Do: ----
+---- - ----
+---- ----
+---- Author: ----
+---- - Salvador E. Tropea, salvador inti.gob.ar ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
+---- ----
+---- Distributed under the GPL license ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Design unit: Hello_Med1(FPGA) (Entity and architecture) ----
+---- File name: hello_med1.vhdl ----
+---- Note: None ----
+---- Limitations: None known ----
+---- Errors: None known ----
+---- Library: work ----
+---- Dependencies: IEEE.std_logic_1164 ----
+---- IEEE.numeric_std ----
+---- zpu.zpu_pkg ----
+---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
+---- Language: VHDL ----
+---- Wishbone: No ----
+---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
+---- Simulation tools: N/A ----
+---- Text editor: SETEdit 0.5.x ----
+---- ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library zpu;
+use zpu.zpupkg.all;
+
+entity Hello_Med1 is
+ generic(
+ WORD_SIZE : natural:=32; -- 32 bits data path
+ D_CARE_VAL : std_logic:='0'; -- Fill value, I got better results with it
+ CLK_FREQ : positive:=50; -- 50 MHz clock
+ BRATE : positive:=115200; -- RS-232 baudrate
+ ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O
+ BRAM_W : natural:=14); -- 14 bits RAM space=16 kB
+ port(
+ clk_i : in std_logic; -- CPU clock
+ rst_i : in std_logic; -- Reset
+ rs232_tx_o : out std_logic; -- UART Tx
+ rs232_rx_i : in std_logic); -- UART Rx
+
+ constant BRD_PB1_I : string:="D19"; -- SWITCH8==S2
+ constant BRD_CLK1_I : string:="AA12"; -- 50 MHz clock
+ --constant BRD_CLK1_I : string:="AB12"; -- 40 MHz clock
+ -- UART: direct 1:1 cable
+ constant BRD_TX_O : string:="L4"; -- UART 1 (J1) TXD1 DB9 pin 2
+ constant BRD_RX_I : string:="L3"; -- UART 1 (J1) RXD1 DB9 pin 3
+
+ ------------
+ -- Pinout --
+ ------------
+ attribute LOC : string;
+ attribute IOSTANDARD : string;
+ constant IOSTD : string:="LVTTL";
+
+ attribute LOC of rst_i : signal is BRD_PB1_I;
+ attribute IOSTANDARD of rst_i : signal is IOSTD;
+ attribute LOC of clk_i : signal is BRD_CLK1_I;
+ attribute LOC of rs232_tx_o : signal is BRD_TX_O;
+ attribute IOSTANDARD of rs232_tx_o : signal is IOSTD;
+ attribute LOC of rs232_rx_i : signal is BRD_RX_I;
+ attribute IOSTANDARD of rs232_rx_i : signal is IOSTD;
+end entity Hello_Med1;
+
+architecture FPGA of Hello_Med1 is
+ component ZPU_Med1 is
+ generic(
+ WORD_SIZE : natural:=32; -- 32 bits data path
+ D_CARE_VAL : std_logic:='X'; -- Fill value
+ CLK_FREQ : positive:=50; -- 50 MHz clock
+ BRATE : positive:=9600; -- RS232 baudrate
+ ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O
+ BRAM_W : natural:=15); -- 15 bits RAM space=32 kB
+ port(
+ clk_i : in std_logic; -- CPU clock
+ rst_i : in std_logic; -- Reset
+ break_o : out std_logic; -- Break executed
+ dbg_o : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o : out std_logic; -- UART Tx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end component ZPU_Med1;
+begin
+ zpu : ZPU_Med1
+ generic map(
+ WORD_SIZE => WORD_SIZE, D_CARE_VAL => D_CARE_VAL,
+ CLK_FREQ => CLK_FREQ, BRATE => BRATE, ADDR_W => ADDR_W,
+ BRAM_W => BRAM_W)
+ port map(
+ clk_i => clk_i, rst_i => rst_i, rs232_tx_o => rs232_tx_o,
+ rs232_rx_i => rs232_rx_i, dbg_o => open, gpio_in => (others => '0'));
+end architecture FPGA; -- Entity: Hello_Med1
+
diff --git a/zpu/hdl/zealot/fpga/hello_small1.vhdl b/zpu/hdl/zealot/fpga/hello_small1.vhdl
new file mode 100644
index 0000000..a7e2c21
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/hello_small1.vhdl
@@ -0,0 +1,120 @@
+------------------------------------------------------------------------------
+---- ----
+---- ZPU Small connection to the FPGA pins ----
+---- ----
+---- http://www.opencores.org/ ----
+---- ----
+---- Description: ----
+---- This module connects the ZPU_Small1 (zpu_small1.vhdl) core to a ----
+---- Spartan 3 1500 Xilinx FPGA available in the GR-XC3S board from ----
+---- Pender. ----
+---- ----
+---- To Do: ----
+---- - ----
+---- ----
+---- Author: ----
+---- - Salvador E. Tropea, salvador inti.gob.ar ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
+---- ----
+---- Distributed under the GPL license ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Design unit: Hello_Small1(FPGA) (Entity and architecture) ----
+---- File name: hello_small1.vhdl ----
+---- Note: None ----
+---- Limitations: None known ----
+---- Errors: None known ----
+---- Library: work ----
+---- Dependencies: IEEE.std_logic_1164 ----
+---- IEEE.numeric_std ----
+---- zpu.zpu_pkg ----
+---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
+---- Language: VHDL ----
+---- Wishbone: No ----
+---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
+---- Simulation tools: N/A ----
+---- Text editor: SETEdit 0.5.x ----
+---- ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library zpu;
+use zpu.zpupkg.all;
+
+entity Hello_Small1 is
+ generic(
+ WORD_SIZE : natural:=32; -- 32 bits data path
+ D_CARE_VAL : std_logic:='0'; -- Fill value, I got better results with it
+ CLK_FREQ : positive:=50; -- 50 MHz clock
+ BRATE : positive:=115200; -- RS-232 baudrate
+ ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O
+ BRAM_W : natural:=14); -- 14 bits RAM space=16 kB
+ port(
+ clk_i : in std_logic; -- CPU clock
+ rst_i : in std_logic; -- Reset
+ rs232_tx_o : out std_logic; -- UART Tx
+ rs232_rx_i : in std_logic); -- UART Rx
+
+ constant BRD_PB1_I : string:="D19"; -- SWITCH8==S2
+ constant BRD_CLK1_I : string:="AA12"; -- 50 MHz clock
+ --constant BRD_CLK1_I : string:="AB12"; -- 40 MHz clock
+ -- UART: direct 1:1 cable
+ constant BRD_TX_O : string:="L4"; -- UART 1 (J1) TXD1 DB9 pin 2
+ constant BRD_RX_I : string:="L3"; -- UART 1 (J1) RXD1 DB9 pin 3
+
+ ------------
+ -- Pinout --
+ ------------
+ attribute LOC : string;
+ attribute IOSTANDARD : string;
+ constant IOSTD : string:="LVTTL";
+
+ attribute LOC of rst_i : signal is BRD_PB1_I;
+ attribute IOSTANDARD of rst_i : signal is IOSTD;
+ attribute LOC of clk_i : signal is BRD_CLK1_I;
+ attribute LOC of rs232_tx_o : signal is BRD_TX_O;
+ attribute IOSTANDARD of rs232_tx_o : signal is IOSTD;
+ attribute LOC of rs232_rx_i : signal is BRD_RX_I;
+ attribute IOSTANDARD of rs232_rx_i : signal is IOSTD;
+end entity Hello_Small1;
+
+architecture FPGA of Hello_Small1 is
+ component ZPU_Small1 is
+ generic(
+ WORD_SIZE : natural:=32; -- 32 bits data path
+ D_CARE_VAL : std_logic:='0'; -- Fill value
+ CLK_FREQ : positive:=50; -- 50 MHz clock
+ BRATE : positive:=115200; -- RS232 baudrate
+ ADDR_W : natural:=16; -- 16 bits address space=64 kB, 32 kB I/O
+ BRAM_W : natural:=15); -- 15 bits RAM space=32 kB
+ port(
+ clk_i : in std_logic; -- CPU clock
+ rst_i : in std_logic; -- Reset
+ break_o : out std_logic; -- Break executed
+ dbg_o : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o : out std_logic; -- UART Tx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end component ZPU_Small1;
+begin
+ zpu : ZPU_Small1
+ generic map(
+ WORD_SIZE => WORD_SIZE, D_CARE_VAL => D_CARE_VAL,
+ CLK_FREQ => CLK_FREQ, BRATE => BRATE, ADDR_W => ADDR_W,
+ BRAM_W => BRAM_W)
+ port map(
+ clk_i => clk_i, rst_i => rst_i, rs232_tx_o => rs232_tx_o,
+ rs232_rx_i => rs232_rx_i, dbg_o => open, gpio_in => (others => '0'));
+end architecture FPGA; -- Entity: Hello_Small1
+
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/clean_up.sh b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/clean_up.sh
new file mode 100755
index 0000000..3855f16
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/clean_up.sh
@@ -0,0 +1,16 @@
+#!/bin/sh
+
+# ise build stuff
+rm -rf build
+rm -f top.bit
+
+# modelsim compile stuff
+rm -rf work
+rm -rf zpu
+
+# modelsim simulation stuff
+rm -f vsim.wlf
+rm -f transcript
+rm -f zpu_trace.log
+rm -f zpu_med1_io.log
+rm -f zpu_small1_io.log
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation.sh b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation.sh
new file mode 100755
index 0000000..d525737
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation.sh
@@ -0,0 +1,49 @@
+#!/bin/sh
+
+# need project files:
+# run.do
+# wave.do
+
+# need ModelSim tools:
+# vlib
+# vcom
+# vsim
+
+
+echo "###############"
+echo "compile zpu lib"
+echo "###############"
+vlib zpu
+vcom -work zpu ../../roms/hello_dbram.vhdl
+vcom -work zpu ../../roms/hello_bram.vhdl
+#vcom -work zpu ../../roms/dmips_dbram.vhdl
+#vcom -work zpu ../../roms/dmips_bram.vhdl
+
+vcom -work zpu ../../roms/rom_pkg.vhdl
+vcom -work zpu ../../zpu_pkg.vhdl
+vcom -work zpu ../../zpu_small.vhdl
+vcom -work zpu ../../zpu_medium.vhdl
+vcom -work zpu ../../helpers/zpu_small1.vhdl
+vcom -work zpu ../../helpers/zpu_med1.vhdl
+vcom -work zpu ../../devices/txt_util.vhdl
+vcom -work zpu ../../devices/phi_io.vhdl
+vcom -work zpu ../../devices/timer.vhdl
+vcom -work zpu ../../devices/gpio.vhdl
+vcom -work zpu ../../devices/rx_unit.vhdl
+vcom -work zpu ../../devices/tx_unit.vhdl
+vcom -work zpu ../../devices/br_gen.vhdl
+vcom -work zpu ../../devices/trace.vhdl
+
+
+echo "################"
+echo "compile work lib"
+echo "################"
+vlib work
+vcom top.vhd
+vcom top_tb.vhd
+
+
+echo "###################"
+echo "start simulator gui"
+echo "###################"
+vsim -gui top_tb -do simulation_config/run.do
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/run.do b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/run.do
new file mode 100644
index 0000000..0d29e0a
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/run.do
@@ -0,0 +1,2 @@
+do wave.do
+run -all
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/wave.do b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/wave.do
new file mode 100644
index 0000000..6a3731d
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/wave.do
@@ -0,0 +1,163 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /top_tb/simulation_run
+add wave -noupdate /top_tb/tb_cpu_reset
+add wave -noupdate /top_tb/tb_sysclk_n
+add wave -noupdate /top_tb/tb_sysclk_p
+add wave -noupdate /top_tb/tb_user_clock
+add wave -noupdate -divider <NULL>
+add wave -noupdate /top_tb/top_i0/clk
+add wave -noupdate -divider <NULL>
+add wave -noupdate /top_tb/tb_gpio_button
+add wave -noupdate /top_tb/tb_gpio_header_ls
+add wave -noupdate /top_tb/tb_gpio_led
+add wave -noupdate /top_tb/tb_gpio_switch
+add wave -noupdate -expand -group USB/RS232 /top_tb/tb_usb_1_cts
+add wave -noupdate -expand -group USB/RS232 /top_tb/tb_usb_1_rts
+add wave -noupdate -expand -group USB/RS232 /top_tb/tb_usb_1_rx
+add wave -noupdate -expand -group USB/RS232 /top_tb/tb_usb_1_tx
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_a
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_ba
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_cas_b
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_ras_b
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_we_b
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_cke
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_clk_n
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_clk_p
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_dq
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_ldm
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_udm
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_ldqs_n
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_ldqs_p
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_udqs_n
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_udqs_p
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_odt
+add wave -noupdate -group {Flash memory} /top_tb/tb_flash_a
+add wave -noupdate -group {Flash memory} /top_tb/tb_flash_d
+add wave -noupdate -group {Flash memory} /top_tb/tb_fpga_d0_din_miso_miso1
+add wave -noupdate -group {Flash memory} /top_tb/tb_fpga_d1_miso2
+add wave -noupdate -group {Flash memory} /top_tb/tb_fpga_d2_miso3
+add wave -noupdate -group {Flash memory} /top_tb/tb_flash_we_b
+add wave -noupdate -group {Flash memory} /top_tb/tb_flash_oe_b
+add wave -noupdate -group {Flash memory} /top_tb/tb_flash_ce_b
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_clk0_m2c_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_clk0_m2c_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_clk1_m2c_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_clk1_m2c_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_iic_scl_main
+add wave -noupdate -group {FMC connector} /top_tb/tb_iic_sda_main
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la00_cc_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la00_cc_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la01_cc_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la01_cc_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la02_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la02_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la03_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la03_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la04_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la04_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la05_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la05_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la06_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la06_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la07_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la07_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la08_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la08_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la09_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la09_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la10_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la10_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la11_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la11_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la12_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la12_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la13_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la13_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la14_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la14_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la15_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la15_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la16_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la16_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la17_cc_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la17_cc_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la18_cc_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la18_cc_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la19_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la19_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la20_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la20_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la21_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la21_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la22_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la22_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la23_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la23_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la24_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la24_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la25_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la25_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la26_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la26_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la27_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la27_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la28_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la28_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la29_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la29_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la30_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la30_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la31_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la31_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la32_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la32_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la33_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la33_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_prsnt_m2c_l
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_pwr_good_flash_rst_b
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_awake
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_cclk
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_cmp_clk
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_cmp_mosi
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_hswapen
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_init_b
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_m0_cmp_miso
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_m1
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_mosi_csi_b_miso0
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_onchip_term1
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_onchip_term2
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_vtemp
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_spi_cs_b
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_col
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_crs
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_int
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_mdc
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_mdio
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_reset
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_rxclk
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_rxctl_rxdv
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_rxd
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_rxer
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_txclk
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_txctl_txen
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_txc_gtxclk
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_txd
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_txer
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {1393701250 ps} 0} {{Cursor 2} {138750 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ps} {327615 ps}
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis.sh b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis.sh
new file mode 100755
index 0000000..2f89415
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis.sh
@@ -0,0 +1,36 @@
+#!/bin/sh
+
+# need project files:
+# top.xst
+# top.prj
+# top.ut
+
+# need Xilinx tools:
+# xst
+# ngdbuild
+# map
+# par
+# trce
+# bitgen
+
+echo "########################"
+echo "generate build directory"
+echo "########################"
+mkdir build
+cd build
+mkdir tmp
+
+echo "###############"
+echo "start processes"
+echo "###############"
+xst -ifn "../synthesis_config/top.xst" -ofn "top.syr"
+ngdbuild -dd _ngo -nt timestamp -uc ../synthesis_config/xilinx-sp601-xc6slx16.ucf -p xc6slx16-csg324-2 top.ngc top.ngd
+map -p xc6slx16-csg324-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o top_map.ncd top.ngd top.pcf
+par -ol high -mt off top_map.ncd -w top.ncd top.pcf
+trce -v 3 -s 2 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf
+bitgen -f ../synthesis_config/top.ut top.ncd
+
+echo "###########"
+echo "get bitfile"
+echo "###########"
+cp top.bit ..
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.prj b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.prj
new file mode 100644
index 0000000..965ae4c
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.prj
@@ -0,0 +1,19 @@
+vhdl work ../top.vhd
+vhdl zpu ../../../zpu_pkg.vhdl
+vhdl zpu ../../../zpu_small.vhdl
+vhdl zpu ../../../zpu_medium.vhdl
+vhdl zpu ../../../roms/rom_pkg.vhdl
+#vhdl zpu ../../../roms/hello_dbram.vhdl
+#vhdl zpu ../../../roms/hello_bram.vhdl
+vhdl zpu ../../../roms/dmips_dbram.vhdl
+vhdl zpu ../../../roms/dmips_bram.vhdl
+vhdl zpu ../../../helpers/zpu_small1.vhdl
+vhdl zpu ../../../helpers/zpu_med1.vhdl
+vhdl zpu ../../../devices/txt_util.vhdl
+vhdl zpu ../../../devices/phi_io.vhdl
+vhdl zpu ../../../devices/timer.vhdl
+vhdl zpu ../../../devices/gpio.vhdl
+vhdl zpu ../../../devices/rx_unit.vhdl
+vhdl zpu ../../../devices/tx_unit.vhdl
+vhdl zpu ../../../devices/br_gen.vhdl
+vhdl zpu ../../../devices/trace.vhdl
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.ut b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.ut
new file mode 100644
index 0000000..be56902
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.ut
@@ -0,0 +1,30 @@
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g Reset_on_err:No
+-g ConfigRate:2
+-g ProgPin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g ExtMasterCclk_en:No
+-g SPI_buswidth:1
+-g TIMER_CFG:0xFFFF
+-g multipin_wakeup:No
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
+-g en_sw_gsr:No
+-g drive_awake:No
+-g sw_clk:Startupclk
+-g sw_gwe_cycle:5
+-g sw_gts_cycle:4
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.xst b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.xst
new file mode 100644
index 0000000..ddddddd
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.xst
@@ -0,0 +1,53 @@
+set -tmpdir "tmp"
+set -xsthdpdir "xst"
+run
+-ifn ../synthesis_config/top.prj
+-ifmt mixed
+-ofn top
+-ofmt NGC
+-p xc6slx16-2-csg324
+-top top
+-opt_mode Speed
+-opt_level 1
+-power NO
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-dsp_utilization_ratio 100
+-lc Auto
+-reduce_control_sets Auto
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-shreg_extract YES
+-rom_style Auto
+-auto_bram_packing NO
+-resource_sharing YES
+-async_to_sync NO
+-shreg_min_size 2
+-use_dsp48 Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 16
+-register_duplication YES
+-register_balancing No
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/xilinx-sp601-xc6slx16.ucf b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/xilinx-sp601-xc6slx16.ucf
new file mode 100644
index 0000000..a0c60e7
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/xilinx-sp601-xc6slx16.ucf
@@ -0,0 +1,303 @@
+############################################################
+# SPARTAN-6 SP601 Board Constraints File
+#
+# Family: Spartan6
+# Device: XC6SLX16
+# Package: CSG324
+# Speed: -2
+#
+#
+# Bank Voltage
+# Bank 0: 2.5 V
+# Bank 1: 2.5 V
+# Bank 2: 2.5 V
+# Bank 3: 1.8 V
+# VCCAUX: 2.5 V
+
+# following pins are connected to VCC1V8/2:
+# N3, M5, C1
+
+
+############################################################
+## clock/timing constraints
+############################################################
+
+TIMESPEC "TS_SYSCLK" = PERIOD "SYSCLK" 200 MHz HIGH 50 %;
+TIMESPEC "TS_USER_SMA_CLOCK" = PERIOD "USER_SMA_CLOCK" 50 MHz HIGH 50 %;
+NET "USER_CLOCK" PERIOD = 27 MHz HIGH 40%;
+
+
+############################################################
+## pin placement constraints
+############################################################
+
+NET "CPU_RESET" LOC = "N4";
+
+## 128 MB DDR2 Component Memory
+NET "DDR2_A<12>" LOC ="G6"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<11>" LOC ="D3"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<10>" LOC ="F4"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<9>" LOC ="D1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<8>" LOC ="D2"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<7>" LOC ="H6"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<6>" LOC ="H3"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<5>" LOC ="H4"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<4>" LOC ="F3"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<3>" LOC ="L7"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<2>" LOC ="H5"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<1>" LOC ="J6"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<0>" LOC ="J7"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<15>" LOC ="U1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<14>" LOC ="U2"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<13>" LOC ="T1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<12>" LOC ="T2"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<11>" LOC ="N1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<10>" LOC ="N2"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<9>" LOC ="M1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<8>" LOC ="M3"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<7>" LOC ="J1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<6>" LOC ="J3"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<5>" LOC ="H1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<4>" LOC ="H2"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<3>" LOC ="K1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<2>" LOC ="K2"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<1>" LOC ="L1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<0>" LOC ="L2"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_WE_B" LOC ="E3"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_UDQS_P" LOC ="P2"; # | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_UDQS_N" LOC ="P1"; # | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_UDM" LOC ="K4"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_RAS_B" LOC ="L5"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_ODT" LOC ="K6"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_LDQS_P" LOC ="L4"; # | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_LDQS_N" LOC ="L3"; # | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_LDM" LOC ="K3"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_CLK_P" LOC ="G3"; # | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_CLK_N" LOC ="G1"; # | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_CKE" LOC ="H7"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_CAS_B" LOC ="K5"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_BA<2>" LOC ="E1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_BA<1>" LOC ="F1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_BA<0>" LOC ="F2"; # | IOSTANDARD = SSTL18_II ;
+
+## Flash Memory
+NET "FLASH_A<0>" LOC = "K18";
+NET "FLASH_A<1>" LOC = "K17";
+NET "FLASH_A<2>" LOC = "J18";
+NET "FLASH_A<3>" LOC = "J16";
+NET "FLASH_A<4>" LOC = "G18";
+NET "FLASH_A<5>" LOC = "G16";
+NET "FLASH_A<6>" LOC = "H16";
+NET "FLASH_A<7>" LOC = "H15";
+NET "FLASH_A<8>" LOC = "H14";
+NET "FLASH_A<9>" LOC = "H13";
+NET "FLASH_A<10>" LOC = "F18";
+NET "FLASH_A<11>" LOC = "F17";
+NET "FLASH_A<12>" LOC = "K13";
+NET "FLASH_A<13>" LOC = "K12";
+NET "FLASH_A<14>" LOC = "E18";
+NET "FLASH_A<15>" LOC = "E16";
+NET "FLASH_A<16>" LOC = "G13";
+NET "FLASH_A<17>" LOC = "H12";
+NET "FLASH_A<18>" LOC = "D18";
+NET "FLASH_A<19>" LOC = "D17";
+NET "FLASH_A<20>" LOC = "G14";
+NET "FLASH_A<21>" LOC = "F14";
+NET "FLASH_A<22>" LOC = "C18";
+NET "FLASH_A<23>" LOC = "C17";
+NET "FLASH_A<24>" LOC = "F16";
+#NET "FLASH_D<0>" LOC = "R13" | SLEW = "SLOW" | DRIVE = 2;
+#NET "FLASH_D<1>" LOC = "T14" | SLEW = "SLOW" | DRIVE = 2;
+#NET "FLASH_D<2>" LOC = "V14" | SLEW = "SLOW" | DRIVE = 2;
+NET "FLASH_D<3>" LOC = "U5" | SLEW = "SLOW" | DRIVE = 2;
+NET "FLASH_D<4>" LOC = "V5" | SLEW = "SLOW" | DRIVE = 2;
+NET "FLASH_D<5>" LOC = "R3" | SLEW = "SLOW" | DRIVE = 2;
+NET "FLASH_D<6>" LOC = "T3" | SLEW = "SLOW" | DRIVE = 2;
+NET "FLASH_D<7>" LOC = "R5" | SLEW = "SLOW" | DRIVE = 2;
+NET "FLASH_OE_B" LOC = "L18";
+NET "FLASH_WE_B" LOC = "M16";
+NET "FLASH_CE_B" LOC = "L17";
+
+# FMC-Connector, Bank 0,2 (M2C = Mezzanine to Carrier, C2M = Carrier to Mezzanine)
+NET "FMC_CLK0_M2C_N" LOC = "A10";
+NET "FMC_CLK0_M2C_P" LOC = "C10";
+NET "FMC_CLK1_M2C_N" LOC = "V9" ;
+NET "FMC_CLK1_M2C_P" LOC = "T9" ;
+NET "FMC_LA00_CC_N" LOC = "C9" ;
+NET "FMC_LA00_CC_P" LOC = "D9" ;
+NET "FMC_LA01_CC_N" LOC = "C11";
+NET "FMC_LA01_CC_P" LOC = "D11";
+NET "FMC_LA02_N" LOC = "A15";
+NET "FMC_LA02_P" LOC = "C15";
+NET "FMC_LA03_N" LOC = "A13";
+NET "FMC_LA03_P" LOC = "C13";
+NET "FMC_LA04_N" LOC = "A16";
+NET "FMC_LA04_P" LOC = "B16";
+NET "FMC_LA05_N" LOC = "A14";
+NET "FMC_LA05_P" LOC = "B14";
+NET "FMC_LA06_N" LOC = "C12";
+NET "FMC_LA06_P" LOC = "D12";
+NET "FMC_LA07_N" LOC = "E8" ;
+NET "FMC_LA07_P" LOC = "E7" ;
+NET "FMC_LA08_N" LOC = "E11";
+NET "FMC_LA08_P" LOC = "F11";
+NET "FMC_LA09_N" LOC = "F10";
+NET "FMC_LA09_P" LOC = "G11";
+NET "FMC_LA10_N" LOC = "C8" ;
+NET "FMC_LA10_P" LOC = "D8" ;
+NET "FMC_LA11_N" LOC = "A12";
+NET "FMC_LA11_P" LOC = "B12";
+NET "FMC_LA12_N" LOC = "C6" ;
+NET "FMC_LA12_P" LOC = "D6" ;
+NET "FMC_LA13_N" LOC = "A11";
+NET "FMC_LA13_P" LOC = "B11";
+NET "FMC_LA14_N" LOC = "A2" ;
+NET "FMC_LA14_P" LOC = "B2" ;
+NET "FMC_LA15_N" LOC = "F9" ;
+NET "FMC_LA15_P" LOC = "G9" ;
+NET "FMC_LA16_N" LOC = "A7" ;
+NET "FMC_LA16_P" LOC = "C7" ;
+NET "FMC_LA17_CC_N" LOC = "T8" ;
+NET "FMC_LA17_CC_P" LOC = "R8" ;
+NET "FMC_LA18_CC_N" LOC = "T10";
+NET "FMC_LA18_CC_P" LOC = "R10";
+NET "FMC_LA19_N" LOC = "P7" ;
+NET "FMC_LA19_P" LOC = "N6" ;
+NET "FMC_LA20_N" LOC = "P8" ;
+NET "FMC_LA20_P" LOC = "N7" ;
+NET "FMC_LA21_N" LOC = "V4" ;
+NET "FMC_LA21_P" LOC = "T4" ;
+NET "FMC_LA22_N" LOC = "T7" ;
+NET "FMC_LA22_P" LOC = "R7" ;
+NET "FMC_LA23_N" LOC = "P6" ;
+NET "FMC_LA23_P" LOC = "N5" ;
+NET "FMC_LA24_N" LOC = "V8" ;
+NET "FMC_LA24_P" LOC = "U8" ;
+NET "FMC_LA25_N" LOC = "N11";
+NET "FMC_LA25_P" LOC = "M11";
+NET "FMC_LA26_N" LOC = "V7" ;
+NET "FMC_LA26_P" LOC = "U7" ;
+NET "FMC_LA27_N" LOC = "T11";
+NET "FMC_LA27_P" LOC = "R11";
+NET "FMC_LA28_N" LOC = "V11";
+NET "FMC_LA28_P" LOC = "U11";
+NET "FMC_LA29_N" LOC = "N8" ;
+NET "FMC_LA29_P" LOC = "M8" ;
+NET "FMC_LA30_N" LOC = "V12";
+NET "FMC_LA30_P" LOC = "T12";
+NET "FMC_LA31_N" LOC = "V6" ;
+NET "FMC_LA31_P" LOC = "T6" ;
+NET "FMC_LA32_N" LOC = "V15";
+NET "FMC_LA32_P" LOC = "U15";
+NET "FMC_LA33_N" LOC = "N9" ;
+NET "FMC_LA33_P" LOC = "M10";
+NET "FMC_PRSNT_M2C_L" LOC = "U13";
+NET "FMC_PWR_GOOD_FLASH_RST_B" LOC = "B3";
+
+# special FPGA pins
+NET "FPGA_AWAKE" LOC = "P15"| SLEW = SLOW | DRIVE = 2;
+NET "FPGA_CCLK" LOC = "R15";
+NET "FPGA_CMP_CLK" LOC = "U16";
+NET "FPGA_CMP_MOSI" LOC = "V16";
+NET "FPGA_D0_DIN_MISO_MISO1" LOC = "R13" | DRIVE = 4; ## 8 on U17 (thru series R187 100 ohm), 33 on U10, 6 on J12
+NET "FPGA_D1_MISO2" LOC = "T14" | DRIVE = 4; ## 9 on U17 (thru series R186 100 ohm), 35 on U10, 3 on J12
+NET "FPGA_D2_MISO3" LOC = "V14" | DRIVE = 4; ## 1 on U17, 38 on U10, 2 on J12
+NET "FPGA_HSWAPEN" LOC = "D4";
+NET "FPGA_INIT_B" LOC = "U3" | SLEW = SLOW | DRIVE = 4;
+NET "FPGA_M0_CMP_MISO" LOC = "T15";
+NET "FPGA_M1" LOC = "N12";
+NET "FPGA_MOSI_CSI_B_MISO0" LOC = "T13" | DRIVE = 4;
+NET "FPGA_ONCHIP_TERM1" LOC = "L6";
+NET "FPGA_ONCHIP_TERM2" LOC = "C2";
+NET "FPGA_VTEMP" LOC = "P3";
+
+## Pushbuttons, Bank 3, external Pulldown
+NET "GPIO_BUTTON<0>" LOC = "P4" ;
+NET "GPIO_BUTTON<1>" LOC = "F6" ;
+NET "GPIO_BUTTON<2>" LOC = "E4" ;
+NET "GPIO_BUTTON<3>" LOC = "F5" ;
+NET "GPIO_BUTTON*" TIG;
+
+## 8 Pin GPIO Header J13, Bank 0,1,2
+NET "GPIO_HEADER_LS<0>" LOC = "N17"| SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_HEADER_LS<1>" LOC = "M18"| SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_HEADER_LS<2>" LOC = "A3" | SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_HEADER_LS<3>" LOC = "L15"| SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_HEADER_LS<4>" LOC = "F15"| SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_HEADER_LS<5>" LOC = "B4" | SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_HEADER_LS<6>" LOC = "F13"| SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_HEADER_LS<7>" LOC = "P12"| SLEW = SLOW | DRIVE = 4 ;
+
+## 4 GPIO LEDs, Bank 0
+NET "GPIO_LED<0>" LOC = "E13"| SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_LED<1>" LOC = "C14"| SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_LED<2>" LOC = "C4" | SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_LED<3>" LOC = "A4" | SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_LED*" TIG;
+
+## GPIO Dip Switches, Bank 0,2, external Pulldown
+NET "GPIO_SWITCH<0>" LOC = "D14";
+NET "GPIO_SWITCH<1>" LOC = "E12";
+NET "GPIO_SWITCH<2>" LOC = "F12";
+NET "GPIO_SWITCH<3>" LOC = "V13";
+NET "GPIO_SWITCH*" TIG;
+
+## IIC Bus
+NET "IIC_SCL_MAIN" LOC = "P11";
+NET "IIC_SDA_MAIN" LOC = "N10";
+
+## 10/100/1000 Tri-Speed Ethernet PHY
+NET "PHY_COL" LOC = "L14";
+NET "PHY_CRS" LOC = "M13";
+NET "PHY_INT" LOC = "J13";
+NET "PHY_MDC" LOC = "N14" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_MDIO" LOC = "P16" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_RESET" LOC = "L13";
+NET "PHY_RXCLK" LOC = "L16";
+NET "PHY_RXCTL_RXDV" LOC = "N18";
+NET "PHY_RXD<0>" LOC = "M14";
+NET "PHY_RXD<1>" LOC = "U18";
+NET "PHY_RXD<2>" LOC = "U17";
+NET "PHY_RXD<3>" LOC = "T18";
+NET "PHY_RXD<4>" LOC = "T17";
+NET "PHY_RXD<5>" LOC = "N16";
+NET "PHY_RXD<6>" LOC = "N15";
+NET "PHY_RXD<7>" LOC = "P18";
+NET "PHY_RXER" LOC = "P17";
+NET "PHY_TXCLK" LOC = "B9" ;
+NET "PHY_TXCTL_TXEN" LOC = "B8" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXC_GTXCLK" LOC = "A9" ;
+NET "PHY_TXD<0>" LOC = "F8" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXD<1>" LOC = "G8" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXD<2>" LOC = "A6" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXD<3>" LOC = "B6" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXD<4>" LOC = "E6" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXD<5>" LOC = "F7" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXD<6>" LOC = "A5" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXD<7>" LOC = "C5" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXER" LOC = "A8" | SLEW = SLOW | DRIVE = 4;
+
+## SPI x4 Flash
+NET "SPI_CS_B" LOC = "V3";
+
+## 200 MHz oscillator (differential)
+NET "SYSCLK_N" LOC = "K16"| IOSTANDARD = LVDS_33 | TNM_NET = "SYSCLK";
+NET "SYSCLK_P" LOC = "K15"| IOSTANDARD = LVDS_33 | TNM_NET = "SYSCLK";
+
+## USB-UART
+## this names are real net names
+NET "USB_1_CTS" LOC = "U10"| DRIVE = 4 | SLEW = SLOW; # RTS output
+NET "USB_1_RTS" LOC = "T5" ; # CTS input
+NET "USB_1_RX" LOC = "L12"| DRIVE = 4 | SLEW = SLOW; # TX data out
+NET "USB_1_TX" LOC = "K14"; # RX data in
+
+## 27 MHz
+NET "USER_CLOCK" LOC = "V10"| IOSTANDARD = LVCMOS33 ;
+##
+NET "USER_SMA_CLOCK_N" LOC = "H18"| TNM_NET = "USER_SMA_CLOCK";
+NET "USER_SMA_CLOCK_P" LOC = "H17"| TNM_NET = "USER_SMA_CLOCK";
+
+# pins used for voltage termination
+CONFIG PROHIBIT = C1;
+CONFIG PROHIBIT = M5;
+CONFIG PROHIBIT = N3;
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top.vhd b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top.vhd
new file mode 100644
index 0000000..27d158f
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top.vhd
@@ -0,0 +1,574 @@
+-- top module of
+-- SP601 evaluation board
+--
+-- using following external connections:
+--
+-- cpu_reset (SW9) reset
+-- LEDs output
+-- USB_UART communication
+--
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library zpu;
+use zpu.zpupkg.all; -- zpu_dbgo_t
+
+library unisim;
+use unisim.vcomponents.ibufgds;
+use unisim.vcomponents.dcm_sp;
+
+
+entity top is
+ port (
+ -- pragma translate_off
+ stop_simulation : out std_logic;
+ -- pragma translate_on
+ --
+ cpu_reset : in std_logic; -- SW9 pushbutton (active-high)
+ --
+ -- DDR2 memory 128 MB
+ ddr2_a : out std_logic_vector(12 downto 0);
+ ddr2_ba : out std_logic_vector(2 downto 0);
+ ddr2_cas_b : out std_logic;
+ ddr2_ras_b : out std_logic;
+ ddr2_we_b : out std_logic;
+ ddr2_cke : out std_logic;
+ ddr2_clk_n : out std_logic;
+ ddr2_clk_p : out std_logic;
+ ddr2_dq : inout std_logic_vector(15 downto 0);
+ ddr2_ldm : out std_logic;
+ ddr2_udm : out std_logic;
+ ddr2_ldqs_n : inout std_logic;
+ ddr2_ldqs_p : inout std_logic;
+ ddr2_udqs_n : inout std_logic;
+ ddr2_udqs_p : inout std_logic;
+ ddr2_odt : out std_logic;
+ --
+ -- flash memory
+ flash_a : out std_logic_vector(24 downto 0);
+ flash_d : inout std_logic_vector(7 downto 3);
+ --
+ fpga_d0_din_miso_miso1 : inout std_logic; -- dual use
+ fpga_d1_miso2 : inout std_logic; -- dual use
+ fpga_d2_miso3 : inout std_logic; -- dual use
+ flash_we_b : out std_logic;
+ flash_oe_b : out std_logic;
+ flash_ce_b : out std_logic;
+ --
+ -- FMC connector
+ -- M2C Mezzanine to Carrier
+ -- C2M Carrier to Mezzanine
+ fmc_clk0_m2c_n : in std_logic;
+ fmc_clk0_m2c_p : in std_logic;
+ fmc_clk1_m2c_n : in std_logic;
+ fmc_clk1_m2c_p : in std_logic;
+ -- IIC addresses:
+ -- M24C08: 1010100..1010111
+ -- 2kb EEPROM on FMC card: 1010010
+ iic_scl_main : inout std_logic;
+ iic_sda_main : inout std_logic;
+ fmc_la00_cc_n : inout std_logic;
+ fmc_la00_cc_p : inout std_logic;
+ fmc_la01_cc_n : inout std_logic;
+ fmc_la01_cc_p : inout std_logic;
+ fmc_la02_n : inout std_logic;
+ fmc_la02_p : inout std_logic;
+ fmc_la03_n : inout std_logic;
+ fmc_la03_p : inout std_logic;
+ fmc_la04_n : inout std_logic;
+ fmc_la04_p : inout std_logic;
+ fmc_la05_n : inout std_logic;
+ fmc_la05_p : inout std_logic;
+ fmc_la06_n : inout std_logic;
+ fmc_la06_p : inout std_logic;
+ fmc_la07_n : inout std_logic;
+ fmc_la07_p : inout std_logic;
+ fmc_la08_n : inout std_logic;
+ fmc_la08_p : inout std_logic;
+ fmc_la09_n : inout std_logic;
+ fmc_la09_p : inout std_logic;
+ fmc_la10_n : inout std_logic;
+ fmc_la10_p : inout std_logic;
+ fmc_la11_n : inout std_logic;
+ fmc_la11_p : inout std_logic;
+ fmc_la12_n : inout std_logic;
+ fmc_la12_p : inout std_logic;
+ fmc_la13_n : inout std_logic;
+ fmc_la13_p : inout std_logic;
+ fmc_la14_n : inout std_logic;
+ fmc_la14_p : inout std_logic;
+ fmc_la15_n : inout std_logic;
+ fmc_la15_p : inout std_logic;
+ fmc_la16_n : inout std_logic;
+ fmc_la16_p : inout std_logic;
+ fmc_la17_cc_n : inout std_logic;
+ fmc_la17_cc_p : inout std_logic;
+ fmc_la18_cc_n : inout std_logic;
+ fmc_la18_cc_p : inout std_logic;
+ fmc_la19_n : inout std_logic;
+ fmc_la19_p : inout std_logic;
+ fmc_la20_n : inout std_logic;
+ fmc_la20_p : inout std_logic;
+ fmc_la21_n : inout std_logic;
+ fmc_la21_p : inout std_logic;
+ fmc_la22_n : inout std_logic;
+ fmc_la22_p : inout std_logic;
+ fmc_la23_n : inout std_logic;
+ fmc_la23_p : inout std_logic;
+ fmc_la24_n : inout std_logic;
+ fmc_la24_p : inout std_logic;
+ fmc_la25_n : inout std_logic;
+ fmc_la25_p : inout std_logic;
+ fmc_la26_n : inout std_logic;
+ fmc_la26_p : inout std_logic;
+ fmc_la27_n : inout std_logic;
+ fmc_la27_p : inout std_logic;
+ fmc_la28_n : inout std_logic;
+ fmc_la28_p : inout std_logic;
+ fmc_la29_n : inout std_logic;
+ fmc_la29_p : inout std_logic;
+ fmc_la30_n : inout std_logic;
+ fmc_la30_p : inout std_logic;
+ fmc_la31_n : inout std_logic;
+ fmc_la31_p : inout std_logic;
+ fmc_la32_n : inout std_logic;
+ fmc_la32_p : inout std_logic;
+ fmc_la33_n : inout std_logic;
+ fmc_la33_p : inout std_logic;
+ fmc_prsnt_m2c_l : in std_logic;
+ fmc_pwr_good_flash_rst_b : out std_logic; -- multiple destinations: 1 of Q2 (LED DS1 driver), U1 AB2 FPGA_PROG (through series R260 DNP), 44 of U25
+ --
+ fpga_awake : out std_logic;
+ fpga_cclk : out std_logic;
+ fpga_cmp_clk : in std_logic;
+ fpga_cmp_mosi : in std_logic;
+ --
+ fpga_hswapen : in std_logic;
+ fpga_init_b : out std_logic; -- low active
+ fpga_m0_cmp_miso : in std_logic; -- mode DIP switch SW1 active high
+ fpga_m1 : in std_logic; -- mode DIP switch SW1 active high
+ fpga_mosi_csi_b_miso0 : inout std_logic;
+ fpga_onchip_term1 : inout std_logic;
+ fpga_onchip_term2 : inout std_logic;
+ fpga_vtemp : in std_logic;
+ --
+ -- GPIOs
+ gpio_button : in std_logic_vector(3 downto 0); -- active high
+ gpio_header_ls : inout std_logic_vector(7 downto 0);
+ gpio_led : out std_logic_vector(3 downto 0);
+ gpio_switch : in std_logic_vector(3 downto 0); -- active high
+ --
+ -- Ethernet Gigabit PHY,
+ -- default settings:
+ -- phy address = 0b00111
+ -- ANEG[3..0] = "1111"
+ -- ENA_XC = 1
+ -- DIS_125 = 1
+ -- HWCFG_MD[3..0] = "1111"
+ -- DIS_FC = 1
+ -- DIS_SLEEP = 1
+ -- SEL_BDT = 0
+ -- INT_POL = 1
+ -- 75/50Ohm = 0
+ phy_col : in std_logic;
+ phy_crs : in std_logic;
+ phy_int : in std_logic;
+ phy_mdc : out std_logic;
+ phy_mdio : inout std_logic;
+ phy_reset : out std_logic;
+ phy_rxclk : in std_logic;
+ phy_rxctl_rxdv : in std_logic;
+ phy_rxd : in std_logic_vector(7 downto 0);
+ phy_rxer : in std_logic;
+ phy_txclk : in std_logic;
+ phy_txctl_txen : out std_logic;
+ phy_txc_gtxclk : out std_logic;
+ phy_txd : out std_logic_vector(7 downto 0);
+ phy_txer : out std_logic;
+ --
+ --
+ spi_cs_b : out std_logic;
+ --
+ -- 200 MHz oscillator, jitter 50 ppm
+ sysclk_n : in std_logic;
+ sysclk_p : in std_logic;
+ --
+ -- RS232 via USB
+ usb_1_cts : out std_logic; -- function: RTS output
+ usb_1_rts : in std_logic; -- function: CTS input
+ usb_1_rx : out std_logic; -- function: TX data out
+ usb_1_tx : in std_logic; -- function: RX data in
+ --
+ -- 27 MHz, oscillator socket
+ user_clock : in std_logic;
+ --
+ -- user clock provided per SMA
+ user_sma_clock_p : in std_logic;
+ user_sma_clock_n : in std_logic
+ );
+end entity top;
+
+
+architecture rtl of top is
+
+ ---------------------------
+ -- type declarations
+ type zpu_type is (zpu_small, zpu_medium);
+
+ ---------------------------
+ -- constant declarations
+ constant zpu_flavour : zpu_type := zpu_medium; -- choose your flavour HERE
+ -- modify frequency here
+ constant clk_multiply : positive := 2; -- 2 for small, 2 for medium
+ constant clk_divide : positive := 5; -- 4 for small, 5 for medium
+ --
+ --
+ constant word_size_c : natural := 32; -- 32 bits data path
+ constant addr_w_c : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O
+ --
+ constant clk_frequency : positive := 200; -- input frequency for correct calculation
+
+
+ ---------------------------
+ -- component declarations
+ component zpu_small1 is
+ generic (
+ word_size : natural := 32; -- 32 bits data path
+ d_care_val : std_logic := '0'; -- Fill value
+ clk_freq : positive := 50; -- 50 MHz clock
+ brate : positive := 115200; -- RS232 baudrate
+ addr_w : natural := 16; -- 16 bits address space=64 kB, 32 kB I/O
+ bram_w : natural := 15 -- 15 bits RAM space=32 kB
+ );
+ port (
+ clk_i : in std_logic; -- CPU clock
+ rst_i : in std_logic; -- Reset
+ break_o : out std_logic; -- Break executed
+ dbg_o : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o : out std_logic; -- UART Tx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end component zpu_small1;
+
+ component zpu_med1 is
+ generic(
+ word_size : natural := 32; -- 32 bits data path
+ d_care_val : std_logic := '0'; -- Fill value
+ clk_freq : positive := 50; -- 50 MHz clock
+ brate : positive := 115200; -- RS232 baudrate
+ addr_w : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O
+ bram_w : natural := 15 -- 15 bits RAM space=32 kB
+ );
+ port(
+ clk_i : in std_logic; -- CPU clock
+ rst_i : in std_logic; -- Reset
+ break_o : out std_logic; -- Break executed
+ dbg_o : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o : out std_logic; -- UART Tx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end component zpu_med1;
+
+
+
+ ---------------------------
+ -- signal declarations
+ signal sys_clk : std_ulogic;
+ signal dcm_sp_i0_clk0 : std_ulogic;
+ signal dcm_sp_i0_clkfx : std_ulogic;
+ signal clk_fb : std_ulogic;
+ signal clk : std_ulogic;
+ --
+ signal reset_shift_reg : std_ulogic_vector(3 downto 0);
+ signal reset_sync : std_ulogic;
+ --
+ signal zpu_i0_dbg : zpu_dbgo_t; -- Debug info
+ signal zpu_i0_break : std_logic;
+ --
+ signal gpio_in : std_logic_vector(31 downto 0) := (others => '0');
+ signal zpu_i0_gpio_out : std_logic_vector(31 downto 0);
+ signal zpu_i0_gpio_dir : std_logic_vector(31 downto 0);
+
+
+begin
+
+ -- default output drivers
+ -- to pass bitgen DRC
+ -- outputs used by design are commented
+ --
+ ddr2_a <= (others => '1');
+ ddr2_ba <= (others => '1');
+ ddr2_cas_b <= '1';
+ ddr2_ras_b <= '1';
+ ddr2_we_b <= '1';
+ ddr2_cke <= '0';
+ ddr2_clk_n <= '0';
+ ddr2_clk_p <= '1';
+ ddr2_dq <= (others => 'Z');
+ ddr2_ldm <= '0';
+ ddr2_udm <= '0';
+ ddr2_ldqs_n <= 'Z';
+ ddr2_ldqs_p <= 'Z';
+ ddr2_udqs_n <= 'Z';
+ ddr2_udqs_p <= 'Z';
+ ddr2_odt <= '1';
+ --
+ flash_a <= (others => '1');
+ flash_d <= (others => 'Z');
+ flash_we_b <= '1';
+ flash_oe_b <= '1';
+ flash_ce_b <= '1';
+ --
+ fpga_d0_din_miso_miso1 <= 'Z';
+ fpga_d1_miso2 <= 'Z';
+ fpga_d2_miso3 <= 'Z';
+ --
+ iic_scl_main <= 'Z';
+ iic_sda_main <= 'Z';
+ fmc_la00_cc_n <= 'Z';
+ fmc_la00_cc_p <= 'Z';
+ fmc_la01_cc_n <= 'Z';
+ fmc_la01_cc_p <= 'Z';
+ fmc_la02_n <= 'Z';
+ fmc_la02_p <= 'Z';
+ fmc_la03_n <= 'Z';
+ fmc_la03_p <= 'Z';
+ fmc_la04_n <= 'Z';
+ fmc_la04_p <= 'Z';
+ fmc_la05_n <= 'Z';
+ fmc_la05_p <= 'Z';
+ fmc_la06_n <= 'Z';
+ fmc_la06_p <= 'Z';
+ fmc_la07_n <= 'Z';
+ fmc_la07_p <= 'Z';
+ fmc_la08_n <= 'Z';
+ fmc_la08_p <= 'Z';
+ fmc_la09_n <= 'Z';
+ fmc_la09_p <= 'Z';
+ fmc_la10_n <= 'Z';
+ fmc_la10_p <= 'Z';
+ fmc_la11_n <= 'Z';
+ fmc_la11_p <= 'Z';
+ fmc_la12_n <= 'Z';
+ fmc_la12_p <= 'Z';
+ fmc_la13_n <= 'Z';
+ fmc_la13_p <= 'Z';
+ fmc_la14_n <= 'Z';
+ fmc_la14_p <= 'Z';
+ fmc_la15_n <= 'Z';
+ fmc_la15_p <= 'Z';
+ fmc_la16_n <= 'Z';
+ fmc_la16_p <= 'Z';
+ fmc_la17_cc_n <= 'Z';
+ fmc_la17_cc_p <= 'Z';
+ fmc_la18_cc_n <= 'Z';
+ fmc_la18_cc_p <= 'Z';
+ fmc_la19_n <= 'Z';
+ fmc_la19_p <= 'Z';
+ fmc_la20_n <= 'Z';
+ fmc_la20_p <= 'Z';
+ fmc_la21_n <= 'Z';
+ fmc_la21_p <= 'Z';
+ fmc_la22_n <= 'Z';
+ fmc_la22_p <= 'Z';
+ fmc_la23_n <= 'Z';
+ fmc_la23_p <= 'Z';
+ fmc_la24_n <= 'Z';
+ fmc_la24_p <= 'Z';
+ fmc_la25_n <= 'Z';
+ fmc_la25_p <= 'Z';
+ fmc_la26_n <= 'Z';
+ fmc_la26_p <= 'Z';
+ fmc_la27_n <= 'Z';
+ fmc_la27_p <= 'Z';
+ fmc_la28_n <= 'Z';
+ fmc_la28_p <= 'Z';
+ fmc_la29_n <= 'Z';
+ fmc_la29_p <= 'Z';
+ fmc_la30_n <= 'Z';
+ fmc_la30_p <= 'Z';
+ fmc_la31_n <= 'Z';
+ fmc_la31_p <= 'Z';
+ fmc_la32_n <= 'Z';
+ fmc_la32_p <= 'Z';
+ fmc_la33_n <= 'Z';
+ fmc_la33_p <= 'Z';
+ fmc_pwr_good_flash_rst_b <= '1';
+ --
+ fpga_awake <= '1';
+ fpga_cclk <= '1'; -- SPI clk
+ fpga_init_b <= '1';
+ fpga_mosi_csi_b_miso0 <= 'Z';
+ fpga_onchip_term1 <= 'Z';
+ fpga_onchip_term2 <= 'Z';
+ --
+ --gpio_led <= (others => '0');
+ --gpio_header_ls <= (others => 'Z');
+ --
+ phy_mdc <= '0';
+ phy_mdio <= 'Z';
+ phy_reset <= '0';
+ phy_txc_gtxclk <= '0';
+ phy_txctl_txen <= '0';
+ phy_txd <= (others => '1');
+ phy_txer <= '0';
+ --
+ spi_cs_b <= '1';
+ --
+ --usb_1_rx <= '1'; -- function: TX data out
+ usb_1_cts <= '1'; -- function: RTS
+
+
+ -- global differential input buffer
+ ibufgds_i0 : ibufgds
+ generic map (
+ diff_term => true
+ )
+ port map (
+ i => sysclk_p,
+ ib => sysclk_n,
+ o => sys_clk
+ );
+
+ -- digital clock manager (DCM)
+ -- to generate higher/other system clock frequencys
+ dcm_sp_i0 : dcm_sp
+ generic map (
+ startup_wait => true, -- wait with DONE till locked
+ clkfx_multiply => clk_multiply,
+ clkfx_divide => clk_divide,
+ clk_feedback => "1X"
+ )
+ port map (
+ clkin => sys_clk,
+ clk0 => dcm_sp_i0_clk0,
+ clkfx => dcm_sp_i0_clkfx,
+ clkfb => clk_fb
+ );
+
+ clk_fb <= dcm_sp_i0_clk0;
+ clk <= dcm_sp_i0_clkfx;
+
+
+ -- reset synchronizer
+ -- generate synchronous reset
+ reset_synchronizer : process(clk, cpu_reset)
+ begin
+ if cpu_reset = '1' then
+ reset_shift_reg <= (others => '1');
+ elsif rising_edge(clk) then
+ reset_shift_reg <= reset_shift_reg(reset_shift_reg'high-1 downto 0) & '0';
+ end if;
+ end process;
+ reset_sync <= reset_shift_reg(reset_shift_reg'high);
+
+
+
+ -- select instance of zpu
+ zpu_i0_small: if zpu_flavour = zpu_small generate
+ zpu_i0 : zpu_small1
+ generic map (
+ addr_w => addr_w_c,
+ word_size => word_size_c,
+ clk_freq => clk_frequency * clk_multiply / clk_divide
+ )
+ port map (
+ clk_i => clk, -- : in std_logic; -- CPU clock
+ rst_i => reset_sync, -- : in std_logic; -- Reset
+ break_o => zpu_i0_break, -- : out std_logic; -- Break executed
+ dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o => usb_1_rx, -- : out std_logic; -- UART Tx
+ rs232_rx_i => usb_1_tx, -- : in std_logic -- UART Rx
+ gpio_in => gpio_in, -- : in std_logic_vector(31 downto 0);
+ gpio_out => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
+ gpio_dir => zpu_i0_gpio_dir -- : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end generate zpu_i0_small;
+
+ zpu_i0_medium: if zpu_flavour = zpu_medium generate
+ zpu_i0 : zpu_med1
+ generic map (
+ addr_w => addr_w_c,
+ word_size => word_size_c,
+ clk_freq => clk_frequency * clk_multiply / clk_divide
+ )
+ port map (
+ clk_i => clk, -- : in std_logic; -- CPU clock
+ rst_i => reset_sync, -- : in std_logic; -- Reset
+ break_o => zpu_i0_break, -- : out std_logic; -- Break executed
+ dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o => usb_1_rx, -- : out std_logic; -- UART Tx
+ rs232_rx_i => usb_1_tx, -- : in std_logic -- UART Rx
+ gpio_in => gpio_in, -- : in std_logic_vector(31 downto 0);
+ gpio_out => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
+ gpio_dir => zpu_i0_gpio_dir -- : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end generate zpu_i0_medium;
+
+
+ -- pragma translate_off
+ stop_simulation <= zpu_i0_break; -- abort() causes to stop the simulation
+
+
+
+ trace_mod : trace
+ generic map (
+ addr_w => addr_w_c,
+ word_size => word_size_c,
+ log_file => "zpu_trace.log"
+ )
+ port map (
+ clk_i => clk,
+ dbg_i => zpu_i0_dbg,
+ stop_i => zpu_i0_break,
+ busy_i => '0'
+ );
+ -- pragma translate_on
+
+ -- assign GPIOs
+ --
+ -- bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
+ --
+ -- in -- -- -- -- -- -- -- -- gpio_header_ls(7.....0)
+ -- out -- -- -- -- -- -- -- -- gpio_header_ls(7.....0)
+ --
+ -- bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+ --
+ -- in -- -- -- -- switch(3.0) -- -- -- -- button(3.0)
+ -- out -- -- -- -- -- -- -- -- gpio_led(7...........0)
+ --
+ gpio_in(23 downto 16) <= gpio_header_ls;
+ gpio_in(11 downto 8) <= gpio_switch;
+ gpio_in( 3 downto 0) <= gpio_button;
+
+ -- 3-state buffers for header_ls
+ gpio_header_ls(7) <= zpu_i0_gpio_out(23) when zpu_i0_gpio_dir(23) = '0' else 'Z';
+ gpio_header_ls(6) <= zpu_i0_gpio_out(22) when zpu_i0_gpio_dir(22) = '0' else 'Z';
+ gpio_header_ls(5) <= zpu_i0_gpio_out(21) when zpu_i0_gpio_dir(21) = '0' else 'Z';
+ gpio_header_ls(4) <= zpu_i0_gpio_out(20) when zpu_i0_gpio_dir(20) = '0' else 'Z';
+ gpio_header_ls(3) <= zpu_i0_gpio_out(19) when zpu_i0_gpio_dir(19) = '0' else 'Z';
+ gpio_header_ls(2) <= zpu_i0_gpio_out(18) when zpu_i0_gpio_dir(18) = '0' else 'Z';
+ gpio_header_ls(1) <= zpu_i0_gpio_out(17) when zpu_i0_gpio_dir(17) = '0' else 'Z';
+ gpio_header_ls(0) <= zpu_i0_gpio_out(16) when zpu_i0_gpio_dir(16) = '0' else 'Z';
+
+ -- switch on all LEDs in case of break
+ process
+ begin
+ wait until rising_edge(clk);
+ gpio_led <= zpu_i0_gpio_out(3 downto 0);
+ if zpu_i0_break = '1' then
+ gpio_led <= (others => '1');
+ end if;
+ end process;
+
+
+
+end architecture rtl;
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top_tb.vhd b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top_tb.vhd
new file mode 100644
index 0000000..f089f29
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top_tb.vhd
@@ -0,0 +1,402 @@
+-- testbench for
+-- SP601 evaluation board
+--
+-- includes "model" for clock generation
+-- simulate press on cpu_reset as reset
+--
+-- place models for external components (PHY, DDR2) in this file
+--
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity top_tb is
+end entity top_tb;
+
+architecture testbench of top_tb is
+
+ ---------------------------
+ -- constant declarations
+ constant sys_clk_period : time := 1 sec / 200_000_000; -- 200 MHz
+ constant user_clk_period : time := 1 sec / 27_000_000; -- 27 MHz
+
+
+ ---------------------------
+ -- signal declarations
+ signal simulation_run : boolean := true;
+ signal tb_stop_simulation : std_logic;
+ --
+ signal tb_cpu_reset : std_logic; -- SW9 pushbutton (active-high)
+ --
+ -- DDR2 memory 128 MB
+ signal tb_ddr2_a : std_logic_vector(12 downto 0);
+ signal tb_ddr2_ba : std_logic_vector(2 downto 0);
+ signal tb_ddr2_cas_b : std_logic;
+ signal tb_ddr2_ras_b : std_logic;
+ signal tb_ddr2_we_b : std_logic;
+ signal tb_ddr2_cke : std_logic;
+ signal tb_ddr2_clk_n : std_logic;
+ signal tb_ddr2_clk_p : std_logic;
+ signal tb_ddr2_dq : std_logic_vector(15 downto 0);
+ signal tb_ddr2_ldm : std_logic;
+ signal tb_ddr2_udm : std_logic;
+ signal tb_ddr2_ldqs_n : std_logic;
+ signal tb_ddr2_ldqs_p : std_logic;
+ signal tb_ddr2_udqs_n : std_logic;
+ signal tb_ddr2_udqs_p : std_logic;
+ signal tb_ddr2_odt : std_logic;
+ --
+ -- flash memory
+ signal tb_flash_a : std_logic_vector(24 downto 0);
+ signal tb_flash_d : std_logic_vector(7 downto 3);
+ signal tb_fpga_d0_din_miso_miso1 : std_logic; -- dual use
+ signal tb_fpga_d1_miso2 : std_logic; -- dual use
+ signal tb_fpga_d2_miso3 : std_logic; -- dual use
+ signal tb_flash_we_b : std_logic;
+ signal tb_flash_oe_b : std_logic;
+ signal tb_flash_ce_b : std_logic;
+ --
+ -- FMC connector
+ -- M2C Mezzanine to Carrier
+ -- C2M Carrier to Mezzanine
+ signal tb_fmc_clk0_m2c_n : std_logic := '1';
+ signal tb_fmc_clk0_m2c_p : std_logic := '0';
+ signal tb_fmc_clk1_m2c_n : std_logic := '1';
+ signal tb_fmc_clk1_m2c_p : std_logic := '0';
+ -- IIC addresses:
+ -- M24C08: 1010100..1010111
+ -- 2kb EEPROM on FMC card: 1010010
+ signal tb_iic_scl_main : std_logic;
+ signal tb_iic_sda_main : std_logic;
+ signal tb_fmc_la00_cc_n : std_logic;
+ signal tb_fmc_la00_cc_p : std_logic;
+ signal tb_fmc_la01_cc_n : std_logic;
+ signal tb_fmc_la01_cc_p : std_logic;
+ signal tb_fmc_la02_n : std_logic;
+ signal tb_fmc_la02_p : std_logic;
+ signal tb_fmc_la03_n : std_logic;
+ signal tb_fmc_la03_p : std_logic;
+ signal tb_fmc_la04_n : std_logic;
+ signal tb_fmc_la04_p : std_logic;
+ signal tb_fmc_la05_n : std_logic;
+ signal tb_fmc_la05_p : std_logic;
+ signal tb_fmc_la06_n : std_logic;
+ signal tb_fmc_la06_p : std_logic;
+ signal tb_fmc_la07_n : std_logic;
+ signal tb_fmc_la07_p : std_logic;
+ signal tb_fmc_la08_n : std_logic;
+ signal tb_fmc_la08_p : std_logic;
+ signal tb_fmc_la09_n : std_logic;
+ signal tb_fmc_la09_p : std_logic;
+ signal tb_fmc_la10_n : std_logic;
+ signal tb_fmc_la10_p : std_logic;
+ signal tb_fmc_la11_n : std_logic;
+ signal tb_fmc_la11_p : std_logic;
+ signal tb_fmc_la12_n : std_logic;
+ signal tb_fmc_la12_p : std_logic;
+ signal tb_fmc_la13_n : std_logic;
+ signal tb_fmc_la13_p : std_logic;
+ signal tb_fmc_la14_n : std_logic;
+ signal tb_fmc_la14_p : std_logic;
+ signal tb_fmc_la15_n : std_logic;
+ signal tb_fmc_la15_p : std_logic;
+ signal tb_fmc_la16_n : std_logic;
+ signal tb_fmc_la16_p : std_logic;
+ signal tb_fmc_la17_cc_n : std_logic;
+ signal tb_fmc_la17_cc_p : std_logic;
+ signal tb_fmc_la18_cc_n : std_logic;
+ signal tb_fmc_la18_cc_p : std_logic;
+ signal tb_fmc_la19_n : std_logic;
+ signal tb_fmc_la19_p : std_logic;
+ signal tb_fmc_la20_n : std_logic;
+ signal tb_fmc_la20_p : std_logic;
+ signal tb_fmc_la21_n : std_logic;
+ signal tb_fmc_la21_p : std_logic;
+ signal tb_fmc_la22_n : std_logic;
+ signal tb_fmc_la22_p : std_logic;
+ signal tb_fmc_la23_n : std_logic;
+ signal tb_fmc_la23_p : std_logic;
+ signal tb_fmc_la24_n : std_logic;
+ signal tb_fmc_la24_p : std_logic;
+ signal tb_fmc_la25_n : std_logic;
+ signal tb_fmc_la25_p : std_logic;
+ signal tb_fmc_la26_n : std_logic;
+ signal tb_fmc_la26_p : std_logic;
+ signal tb_fmc_la27_n : std_logic;
+ signal tb_fmc_la27_p : std_logic;
+ signal tb_fmc_la28_n : std_logic;
+ signal tb_fmc_la28_p : std_logic;
+ signal tb_fmc_la29_n : std_logic;
+ signal tb_fmc_la29_p : std_logic;
+ signal tb_fmc_la30_n : std_logic;
+ signal tb_fmc_la30_p : std_logic;
+ signal tb_fmc_la31_n : std_logic;
+ signal tb_fmc_la31_p : std_logic;
+ signal tb_fmc_la32_n : std_logic;
+ signal tb_fmc_la32_p : std_logic;
+ signal tb_fmc_la33_n : std_logic;
+ signal tb_fmc_la33_p : std_logic;
+ signal tb_fmc_prsnt_m2c_l : std_logic := '0';
+ signal tb_fmc_pwr_good_flash_rst_b : std_logic; -- multiple destinations: 1 of Q2 (LED DS1 driver), U1 AB2 FPGA_PROG (through series R260 DNP), 44 of U25
+ --
+ signal tb_fpga_awake : std_logic;
+ signal tb_fpga_cclk : std_logic;
+ signal tb_fpga_cmp_clk : std_logic := '0';
+ signal tb_fpga_cmp_mosi : std_logic := '0';
+ signal tb_fpga_hswapen : std_logic := '0';
+ signal tb_fpga_init_b : std_logic; -- low active
+ signal tb_fpga_m0_cmp_miso : std_logic := '0'; -- mode DIP switch SW1 active high
+ signal tb_fpga_m1 : std_logic := '0'; -- mode DIP switch SW1 active high
+ signal tb_fpga_mosi_csi_b_miso0 : std_logic;
+ signal tb_fpga_onchip_term1 : std_logic;
+ signal tb_fpga_onchip_term2 : std_logic;
+ signal tb_fpga_vtemp : std_logic := '0';
+ --
+ -- GPIOs
+ signal tb_gpio_button : std_logic_vector(3 downto 0) := (others => '0'); -- active high
+ signal tb_gpio_header_ls : std_logic_vector(7 downto 0); --
+ signal tb_gpio_led : std_logic_vector(3 downto 0);
+ signal tb_gpio_switch : std_logic_vector(3 downto 0) := (others => '0'); -- active high
+ --
+ -- Ethernet Gigabit PHY
+ signal tb_phy_col : std_logic := '0';
+ signal tb_phy_crs : std_logic := '0';
+ signal tb_phy_int : std_logic := '0';
+ signal tb_phy_mdc : std_logic;
+ signal tb_phy_mdio : std_logic;
+ signal tb_phy_reset : std_logic;
+ signal tb_phy_rxclk : std_logic := '0';
+ signal tb_phy_rxctl_rxdv : std_logic := '0';
+ signal tb_phy_rxd : std_logic_vector(7 downto 0);
+ signal tb_phy_rxer : std_logic := '0';
+ signal tb_phy_txclk : std_logic := '0';
+ signal tb_phy_txctl_txen : std_logic;
+ signal tb_phy_txc_gtxclk : std_logic;
+ signal tb_phy_txd : std_logic_vector(7 downto 0);
+ signal tb_phy_txer : std_logic;
+ --
+ --
+ signal tb_spi_cs_b : std_logic;
+ --
+ -- 200 MHz oscillator, jitter 50 ppm
+ signal tb_sysclk_n : std_logic := '1';
+ signal tb_sysclk_p : std_logic := '0';
+ --
+ -- RS232 via USB
+ signal tb_usb_1_cts : std_logic; -- function: RTS output
+ signal tb_usb_1_rts : std_logic := '0'; -- function: CTS input
+ signal tb_usb_1_rx : std_logic; -- function: TX data out
+ signal tb_usb_1_tx : std_logic := '0'; -- function: RX data in
+ --
+ -- 27 MHz, oscillator socket
+ signal tb_user_clock : std_logic := '0';
+ --
+ -- user clock provided per SMA
+ signal tb_user_sma_clock_p : std_logic := '0';
+ signal tb_user_sma_clock_n : std_logic := '0';
+
+
+
+begin
+
+ -- generate clocks
+ tb_sysclk_p <= not tb_sysclk_p after sys_clk_period / 2 when simulation_run;
+ tb_sysclk_n <= not tb_sysclk_n after sys_clk_period / 2 when simulation_run;
+ tb_user_clock <= not tb_user_clock after user_clk_period / 2 when simulation_run;
+
+ -- generate reset
+ tb_cpu_reset <= '1', '0' after 6.66 * sys_clk_period;
+
+
+ -- simulate keypress
+ tb_gpio_button(2) <= '0', '1' after 50 us, '0' after 52 us;
+
+ -- dut
+ top_i0 : entity work.top
+ port map (
+ stop_simulation => tb_stop_simulation, -- : out std_logic;
+ --
+ cpu_reset => tb_cpu_reset, -- : in std_logic;
+ --
+ -- DDR2 memory 128 MB
+ ddr2_a => tb_ddr2_a, -- : out std_logic_vector(12 downto 0);
+ ddr2_ba => tb_ddr2_ba, -- : out std_logic_vector(2 downto 0);
+ ddr2_cas_b => tb_ddr2_cas_b, -- : out std_logic;
+ ddr2_ras_b => tb_ddr2_ras_b, -- : out std_logic;
+ ddr2_we_b => tb_ddr2_we_b, -- : out std_logic;
+ ddr2_cke => tb_ddr2_cke, -- : out std_logic;
+ ddr2_clk_n => tb_ddr2_clk_n, -- : out std_logic;
+ ddr2_clk_p => tb_ddr2_clk_p, -- : out std_logic;
+ ddr2_dq => tb_ddr2_dq, -- : inout std_logic_vector(15 downto 0);
+ ddr2_ldm => tb_ddr2_ldm, -- : out std_logic;
+ ddr2_udm => tb_ddr2_udm, -- : out std_logic;
+ ddr2_ldqs_n => tb_ddr2_ldqs_n, -- : inout std_logic;
+ ddr2_ldqs_p => tb_ddr2_ldqs_p, -- : inout std_logic;
+ ddr2_udqs_n => tb_ddr2_udqs_n, -- : inout std_logic;
+ ddr2_udqs_p => tb_ddr2_udqs_p, -- : inout std_logic;
+ ddr2_odt => tb_ddr2_odt, -- : out std_logic;
+ --
+ -- flash memory
+ flash_a => tb_flash_a, -- : out std_logic_vector(24 downto 0);
+ flash_d => tb_flash_d, -- : inout std_logic_vector(7 downto 3);
+ -- --
+ fpga_d0_din_miso_miso1 => tb_fpga_d0_din_miso_miso1, -- : inout std_logic;
+ fpga_d1_miso2 => tb_fpga_d1_miso2, -- : inout std_logic;
+ fpga_d2_miso3 => tb_fpga_d2_miso3, -- : inout std_logic;
+ flash_we_b => tb_flash_we_b, -- : out std_logic;
+ flash_oe_b => tb_flash_oe_b, -- : out std_logic;
+ flash_ce_b => tb_flash_ce_b, -- : out std_logic;
+ --
+ -- FMC connector
+ -- M2C Mezzanine to Carrier
+ -- C2M Carrier to Mezzanine
+ fmc_clk0_m2c_n => tb_fmc_clk0_m2c_n, -- : in std_logic;
+ fmc_clk0_m2c_p => tb_fmc_clk0_m2c_p, -- : in std_logic;
+ fmc_clk1_m2c_n => tb_fmc_clk1_m2c_n, -- : in std_logic;
+ fmc_clk1_m2c_p => tb_fmc_clk1_m2c_p, -- : in std_logic;
+ iic_scl_main => tb_iic_scl_main, -- : inout std_logic;
+ iic_sda_main => tb_iic_sda_main, -- : inout std_logic;
+ fmc_la00_cc_n => tb_fmc_la00_cc_n, -- : inout std_logic;
+ fmc_la00_cc_p => tb_fmc_la00_cc_p, -- : inout std_logic;
+ fmc_la01_cc_n => tb_fmc_la01_cc_n, -- : inout std_logic;
+ fmc_la01_cc_p => tb_fmc_la01_cc_p, -- : inout std_logic;
+ fmc_la02_n => tb_fmc_la02_n, -- : inout std_logic;
+ fmc_la02_p => tb_fmc_la02_p, -- : inout std_logic;
+ fmc_la03_n => tb_fmc_la03_n, -- : inout std_logic;
+ fmc_la03_p => tb_fmc_la03_p, -- : inout std_logic;
+ fmc_la04_n => tb_fmc_la04_n, -- : inout std_logic;
+ fmc_la04_p => tb_fmc_la04_p, -- : inout std_logic;
+ fmc_la05_n => tb_fmc_la05_n, -- : inout std_logic;
+ fmc_la05_p => tb_fmc_la05_p, -- : inout std_logic;
+ fmc_la06_n => tb_fmc_la06_n, -- : inout std_logic;
+ fmc_la06_p => tb_fmc_la06_p, -- : inout std_logic;
+ fmc_la07_n => tb_fmc_la07_n, -- : inout std_logic;
+ fmc_la07_p => tb_fmc_la07_p, -- : inout std_logic;
+ fmc_la08_n => tb_fmc_la08_n, -- : inout std_logic;
+ fmc_la08_p => tb_fmc_la08_p, -- : inout std_logic;
+ fmc_la09_n => tb_fmc_la09_n, -- : inout std_logic;
+ fmc_la09_p => tb_fmc_la09_p, -- : inout std_logic;
+ fmc_la10_n => tb_fmc_la10_n, -- : inout std_logic;
+ fmc_la10_p => tb_fmc_la10_p, -- : inout std_logic;
+ fmc_la11_n => tb_fmc_la11_n, -- : inout std_logic;
+ fmc_la11_p => tb_fmc_la11_p, -- : inout std_logic;
+ fmc_la12_n => tb_fmc_la12_n, -- : inout std_logic;
+ fmc_la12_p => tb_fmc_la12_p, -- : inout std_logic;
+ fmc_la13_n => tb_fmc_la13_n, -- : inout std_logic;
+ fmc_la13_p => tb_fmc_la13_p, -- : inout std_logic;
+ fmc_la14_n => tb_fmc_la14_n, -- : inout std_logic;
+ fmc_la14_p => tb_fmc_la14_p, -- : inout std_logic;
+ fmc_la15_n => tb_fmc_la15_n, -- : inout std_logic;
+ fmc_la15_p => tb_fmc_la15_p, -- : inout std_logic;
+ fmc_la16_n => tb_fmc_la16_n, -- : inout std_logic;
+ fmc_la16_p => tb_fmc_la16_p, -- : inout std_logic;
+ fmc_la17_cc_n => tb_fmc_la17_cc_n, -- : inout std_logic;
+ fmc_la17_cc_p => tb_fmc_la17_cc_p, -- : inout std_logic;
+ fmc_la18_cc_n => tb_fmc_la18_cc_n, -- : inout std_logic;
+ fmc_la18_cc_p => tb_fmc_la18_cc_p, -- : inout std_logic;
+ fmc_la19_n => tb_fmc_la19_n, -- : inout std_logic;
+ fmc_la19_p => tb_fmc_la19_p, -- : inout std_logic;
+ fmc_la20_n => tb_fmc_la20_n, -- : inout std_logic;
+ fmc_la20_p => tb_fmc_la20_p, -- : inout std_logic;
+ fmc_la21_n => tb_fmc_la21_n, -- : inout std_logic;
+ fmc_la21_p => tb_fmc_la21_p, -- : inout std_logic;
+ fmc_la22_n => tb_fmc_la22_n, -- : inout std_logic;
+ fmc_la22_p => tb_fmc_la22_p, -- : inout std_logic;
+ fmc_la23_n => tb_fmc_la23_n, -- : inout std_logic;
+ fmc_la23_p => tb_fmc_la23_p, -- : inout std_logic;
+ fmc_la24_n => tb_fmc_la24_n, -- : inout std_logic;
+ fmc_la24_p => tb_fmc_la24_p, -- : inout std_logic;
+ fmc_la25_n => tb_fmc_la25_n, -- : inout std_logic;
+ fmc_la25_p => tb_fmc_la25_p, -- : inout std_logic;
+ fmc_la26_n => tb_fmc_la26_n, -- : inout std_logic;
+ fmc_la26_p => tb_fmc_la26_p, -- : inout std_logic;
+ fmc_la27_n => tb_fmc_la27_n, -- : inout std_logic;
+ fmc_la27_p => tb_fmc_la27_p, -- : inout std_logic;
+ fmc_la28_n => tb_fmc_la28_n, -- : inout std_logic;
+ fmc_la28_p => tb_fmc_la28_p, -- : inout std_logic;
+ fmc_la29_n => tb_fmc_la29_n, -- : inout std_logic;
+ fmc_la29_p => tb_fmc_la29_p, -- : inout std_logic;
+ fmc_la30_n => tb_fmc_la30_n, -- : inout std_logic;
+ fmc_la30_p => tb_fmc_la30_p, -- : inout std_logic;
+ fmc_la31_n => tb_fmc_la31_n, -- : inout std_logic;
+ fmc_la31_p => tb_fmc_la31_p, -- : inout std_logic;
+ fmc_la32_n => tb_fmc_la32_n, -- : inout std_logic;
+ fmc_la32_p => tb_fmc_la32_p, -- : inout std_logic;
+ fmc_la33_n => tb_fmc_la33_n, -- : inout std_logic;
+ fmc_la33_p => tb_fmc_la33_p, -- : inout std_logic;
+ fmc_prsnt_m2c_l => tb_fmc_prsnt_m2c_l, -- : in std_logic;
+ fmc_pwr_good_flash_rst_b => tb_fmc_pwr_good_flash_rst_b, -- : out std_logic;
+ --
+ fpga_awake => tb_fpga_awake, -- : out std_logic;
+ fpga_cclk => tb_fpga_cclk, -- : out std_logic;
+ fpga_cmp_clk => tb_fpga_cmp_clk, -- : in std_logic;
+ fpga_cmp_mosi => tb_fpga_cmp_mosi, -- : in std_logic;
+ -- --
+ fpga_hswapen => tb_fpga_hswapen, -- : in std_logic;
+ fpga_init_b => tb_fpga_init_b, -- : out std_logic;
+ fpga_m0_cmp_miso => tb_fpga_m0_cmp_miso, -- : in std_logic;
+ fpga_m1 => tb_fpga_m1, -- : in std_logic;
+ fpga_mosi_csi_b_miso0 => tb_fpga_mosi_csi_b_miso0, -- : inout std_logic;
+ fpga_onchip_term1 => tb_fpga_onchip_term1, -- : inout std_logic;
+ fpga_onchip_term2 => tb_fpga_onchip_term2, -- : inout std_logic;
+ fpga_vtemp => tb_fpga_vtemp, -- : in std_logic;
+ --
+ -- GPIOs
+ gpio_button => tb_gpio_button, -- : in std_logic_vector(3 downto 0);
+ gpio_header_ls => tb_gpio_header_ls, -- : inout std_logic_vector(7 downto 0);
+ gpio_led => tb_gpio_led, -- : out std_logic_vector(3 downto 0);
+ gpio_switch => tb_gpio_switch, -- : in std_logic_vector(3 downto 0);
+ --
+ -- Ethernet Gigabit PHY
+ phy_col => tb_phy_col, -- : in std_logic;
+ phy_crs => tb_phy_crs, -- : in std_logic;
+ phy_int => tb_phy_int, -- : in std_logic;
+ phy_mdc => tb_phy_mdc, -- : out std_logic;
+ phy_mdio => tb_phy_mdio, -- : inout std_logic;
+ phy_reset => tb_phy_reset, -- : out std_logic;
+ phy_rxclk => tb_phy_rxclk, -- : in std_logic;
+ phy_rxctl_rxdv => tb_phy_rxctl_rxdv, -- : in std_logic;
+ phy_rxd => tb_phy_rxd, -- : in std_logic_vector(7 downto 0);
+ phy_rxer => tb_phy_rxer, -- : in std_logic;
+ phy_txclk => tb_phy_txclk, -- : in std_logic;
+ phy_txctl_txen => tb_phy_txctl_txen, -- : out std_logic;
+ phy_txc_gtxclk => tb_phy_txc_gtxclk, -- : out std_logic;
+ phy_txd => tb_phy_txd, -- : out std_logic_vector(7 downto 0);
+ phy_txer => tb_phy_txer, -- : out std_logic;
+ --
+ --
+ spi_cs_b => tb_spi_cs_b, -- : out std_logic;
+ --
+ -- 200 MHz oscillator, jitter 50 ppm
+ sysclk_n => tb_sysclk_n, -- : in std_logic;
+ sysclk_p => tb_sysclk_p, -- : in std_logic;
+ --
+ -- RS232 via USB
+ usb_1_cts => tb_usb_1_cts, -- : out std_logic;
+ usb_1_rts => tb_usb_1_rts, -- : in std_logic;
+ usb_1_rx => tb_usb_1_rx, -- : out std_logic;
+ usb_1_tx => tb_usb_1_tx, -- : in std_logic;
+ --
+ -- 27 MHz, oscillator socket
+ user_clock => tb_user_clock, -- : in std_logic;
+ --
+ -- user clock provided per SMA
+ user_sma_clock_p => tb_user_sma_clock_p, -- : in std_logic;
+ user_sma_clock_n => tb_user_sma_clock_n -- : in std_logic
+ );
+
+
+ -- check for simulation stopping
+ process (tb_stop_simulation)
+ begin
+ if tb_stop_simulation = '1' then
+ report "Simulation end." severity note;
+ simulation_run <= false;
+ end if;
+ end process;
+
+
+end architecture testbench;
+
diff --git a/zpu/hdl/zealot/helpers/zpu_med1.vhdl b/zpu/hdl/zealot/helpers/zpu_med1.vhdl
new file mode 100644
index 0000000..a0cbcb2
--- /dev/null
+++ b/zpu/hdl/zealot/helpers/zpu_med1.vhdl
@@ -0,0 +1,187 @@
+------------------------------------------------------------------------------
+---- ----
+---- ZPU Medium + PHI I/O + BRAM ----
+---- ----
+---- http://www.opencores.org/ ----
+---- ----
+---- Description: ----
+---- ZPU is a 32 bits small stack cpu. This is a helper that joins the ----
+---- medium version, the PHI I/O basic layout and a program BRAM. ----
+---- ----
+---- To Do: ----
+---- - ----
+---- ----
+---- Author: ----
+---- - Salvador E. Tropea, salvador inti.gob.ar ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
+---- ----
+---- Distributed under the BSD license ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Design unit: ZPU_Med1(Structural) (Entity and architecture) ----
+---- File name: zpu_med1.vhdl ----
+---- Note: None ----
+---- Limitations: None known ----
+---- Errors: None known ----
+---- Library: work ----
+---- Dependencies: IEEE.std_logic_1164 ----
+---- IEEE.numeric_std ----
+---- zpu.zpupkg ----
+---- work.zpu_memory ----
+---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
+---- Language: VHDL ----
+---- Wishbone: No ----
+---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
+---- Text editor: SETEdit 0.5.x ----
+---- ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library zpu;
+use zpu.zpupkg.all;
+
+-- RAM declaration
+library work;
+use work.zpu_memory.all;
+
+entity ZPU_Med1 is
+ generic(
+ WORD_SIZE : natural:=32; -- 32 bits data path
+ D_CARE_VAL : std_logic:='X'; -- Fill value
+ CLK_FREQ : positive:=50; -- 50 MHz clock
+ BRATE : positive:=9600; -- RS232 baudrate
+ ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O
+ BRAM_W : natural:=15); -- 15 bits RAM space=32 kB
+ port(
+ clk_i : in std_logic; -- CPU clock
+ rst_i : in std_logic; -- Reset
+ break_o : out std_logic; -- Break executed
+ dbg_o : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o : out std_logic; -- UART Tx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+end entity ZPU_Med1;
+
+architecture Structural of ZPU_Med1 is
+ constant BYTE_BITS : integer:=WORD_SIZE/16; -- # of bits in a word that addresses bytes
+ constant IO_BIT : integer:=ADDR_W-1; -- Address bit to determine this is an I/O
+ constant BRDIVISOR : positive:=CLK_FREQ*1e6/BRATE/4;
+
+ -- I/O & memory (ZPU)
+ signal mem_busy : std_logic;
+ signal mem_read : unsigned(WORD_SIZE-1 downto 0);
+ signal mem_write : unsigned(WORD_SIZE-1 downto 0);
+ signal mem_addr : unsigned(ADDR_W-1 downto 0);
+ signal mem_we : std_logic;
+ signal mem_re : std_logic;
+
+ -- Memory (SinglePort_RAM)
+ signal ram_busy : std_logic;
+ signal ram_read : unsigned(WORD_SIZE-1 downto 0);
+ signal ram_addr : unsigned(BRAM_W-1 downto BYTE_BITS);
+ signal ram_we : std_logic;
+ signal ram_re : std_logic;
+ signal ram_ready_r : std_logic:='0';
+
+ -- I/O (ZPU_IO)
+ signal io_busy : std_logic;
+ signal io_re : std_logic;
+ signal io_we : std_logic;
+ signal io_read : unsigned(WORD_SIZE-1 downto 0);
+ signal io_ready : std_logic;
+ signal io_reading_r : std_logic:='0';
+ signal io_addr : unsigned(2 downto 0);
+begin
+ memory: SinglePortRAM
+ generic map(
+ WORD_SIZE => WORD_SIZE, BYTE_BITS => BYTE_BITS, BRAM_W => BRAM_W)
+ port map(
+ clk_i => clk_i,
+ we_i => ram_we, re_i => ram_re, addr_i => ram_addr,
+ write_i => mem_write, read_o => ram_read, busy_o => ram_busy);
+ ram_addr <= mem_addr(BRAM_W-1 downto BYTE_BITS);
+ ram_we <= mem_we and not(mem_addr(IO_BIT));
+ ram_re <= mem_re and not(mem_addr(IO_BIT));
+
+ -- I/O: Phi layout
+ io_map: ZPUPhiIO
+ generic map(
+ BRDIVISOR => BRDIVISOR,
+ LOG_FILE => "zpu_med1_io.log"
+ )
+ port map(
+ clk_i => clk_i,
+ reset_i => rst_i,
+ busy_o => io_busy,
+ we_i => io_we,
+ re_i => io_re,
+ data_i => mem_write,
+ data_o => io_read,
+ addr_i => io_addr,
+ rs232_rx_i => rs232_rx_i,
+ rs232_tx_o => rs232_tx_o,
+ br_clk_i => '1',
+ gpio_in => gpio_in,
+ gpio_out => gpio_out,
+ gpio_dir => gpio_dir
+ );
+ io_addr <= mem_addr(4 downto 2);
+ -- Here we decode 0x8xxxx as I/O and not just 0x80A00xx
+ -- Note: We define the address space as 256 kB, so writing to 0x80A00xx
+ -- will be as wrting to 0x200xx and hence we decode it as I/O space.
+ io_we <= mem_we and mem_addr(IO_BIT);
+ io_re <= mem_re and mem_addr(IO_BIT);
+ io_ready <= (io_reading_r or io_re) and not io_busy;
+
+ zpu : ZPUMediumCore
+ generic map(
+ WORD_SIZE => WORD_SIZE, ADDR_W => ADDR_W, MEM_W => BRAM_W,
+ D_CARE_VAL => D_CARE_VAL)
+ port map(
+ clk_i => clk_i, reset_i => rst_i, enable_i => '1',
+ break_o => break_o, dbg_o => dbg_o,
+ -- Memory
+ mem_busy_i => mem_busy, data_i => mem_read, data_o => mem_write,
+ addr_o => mem_addr, write_en_o => mem_we, read_en_o => mem_re);
+ mem_busy <= io_busy or ram_busy;
+
+ -- Memory reads either come from IO or DRAM. We need to pick the right one.
+ memory_control:
+ process (ram_read, ram_ready_r, io_ready, io_read)
+ begin
+ mem_read <= (others => '0');
+ if ram_ready_r='1' then
+ mem_read <= ram_read;
+ end if;
+ if io_ready='1' then
+ mem_read <= io_read;
+ end if;
+ end process memory_control;
+
+ memory_control_sync:
+ process (clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if rst_i='1' then
+ io_reading_r <= '0';
+ ram_ready_r <= '0';
+ else
+ io_reading_r <= io_busy or io_re;
+ ram_ready_r <= ram_re;
+ end if;
+ end if;
+ end process memory_control_sync;
+end architecture Structural; -- Entity: ZPU_Med1
+
diff --git a/zpu/hdl/zealot/helpers/zpu_small1.vhdl b/zpu/hdl/zealot/helpers/zpu_small1.vhdl
new file mode 100644
index 0000000..52006e4
--- /dev/null
+++ b/zpu/hdl/zealot/helpers/zpu_small1.vhdl
@@ -0,0 +1,153 @@
+------------------------------------------------------------------------------
+---- ----
+---- ZPU Small + PHI I/O + BRAM ----
+---- ----
+---- http://www.opencores.org/ ----
+---- ----
+---- Description: ----
+---- ZPU is a 32 bits small stack cpu. This is a helper that joins the ----
+---- small version, the PHI I/O basic layout and a program BRAM. ----
+---- ----
+---- To Do: ----
+---- - ----
+---- ----
+---- Author: ----
+---- - Salvador E. Tropea, salvador inti.gob.ar ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
+---- ----
+---- Distributed under the BSD license ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Design unit: ZPU_Small1(Structural) (Entity and architecture) ----
+---- File name: zpu_small1.vhdl ----
+---- Note: None ----
+---- Limitations: None known ----
+---- Errors: None known ----
+---- Library: work ----
+---- Dependencies: IEEE.std_logic_1164 ----
+---- IEEE.numeric_std ----
+---- zpu.zpupkg ----
+---- work.zpu_memory ----
+---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
+---- Language: VHDL ----
+---- Wishbone: No ----
+---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
+---- Text editor: SETEdit 0.5.x ----
+---- ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library zpu;
+use zpu.zpupkg.all;
+
+-- RAM declaration
+library work;
+use work.zpu_memory.all;
+
+entity ZPU_Small1 is
+ generic(
+ WORD_SIZE : natural:=32; -- 32 bits data path
+ D_CARE_VAL : std_logic:='0'; -- Fill value
+ CLK_FREQ : positive:=50; -- 50 MHz clock
+ BRATE : positive:=115200; -- RS232 baudrate
+ ADDR_W : natural:=16; -- 16 bits address space=64 kB, 32 kB I/O
+ BRAM_W : natural:=15); -- 15 bits RAM space=32 kB
+ port(
+ clk_i : in std_logic; -- CPU clock
+ rst_i : in std_logic; -- Reset
+ break_o : out std_logic; -- Break executed
+ dbg_o : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o : out std_logic; -- UART Tx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+end entity ZPU_Small1;
+
+architecture Structural of ZPU_Small1 is
+ constant BYTE_BITS : integer:=WORD_SIZE/16; -- # of bits in a word that addresses bytes
+ constant IO_BIT : integer:=ADDR_W-1; -- Address bit to determine this is an I/O
+ constant BRDIVISOR : positive:=CLK_FREQ*1e6/BRATE/4;
+
+ -- Program+data+stack BRAM
+ -- Port A
+ signal a_we : std_logic;
+ signal a_addr : unsigned(BRAM_W-1 downto BYTE_BITS);
+ signal a_write : unsigned(WORD_SIZE-1 downto 0);
+ signal a_read : unsigned(WORD_SIZE-1 downto 0);
+ -- Port B
+ signal b_we : std_logic;
+ signal b_addr : unsigned(BRAM_W-1 downto BYTE_BITS);
+ signal b_write : unsigned(WORD_SIZE-1 downto 0);
+ signal b_read : unsigned(WORD_SIZE-1 downto 0);
+
+ -- I/O space
+ signal io_busy : std_logic;
+ signal io_write : unsigned(WORD_SIZE-1 downto 0);
+ signal io_read : unsigned(WORD_SIZE-1 downto 0);
+ signal io_addr : unsigned(ADDR_W-1 downto 0);
+ signal phi_addr : unsigned(2 downto 0);
+ signal io_we : std_logic;
+ signal io_re : std_logic;
+begin
+ memory: DualPortRAM
+ generic map(
+ WORD_SIZE => WORD_SIZE, BYTE_BITS => BYTE_BITS, BRAM_W => BRAM_W)
+ port map(
+ clk_i => clk_i,
+ -- Port A
+ a_we_i => a_we, a_addr_i => a_addr, a_write_i => a_write,
+ a_read_o => a_read,
+ -- Port B
+ b_we_i => b_we, b_addr_i => b_addr, b_write_i => b_write,
+ b_read_o => b_read);
+
+ -- I/O: Phi layout
+ io_map: ZPUPhiIO
+ generic map(
+ BRDIVISOR => BRDIVISOR,
+ LOG_FILE => "zpu_small1_io.log"
+ )
+ port map(
+ clk_i => clk_i,
+ reset_i => rst_i,
+ busy_o => io_busy,
+ we_i => io_we,
+ re_i => io_re,
+ data_i => io_write,
+ data_o => io_read,
+ addr_i => phi_addr,
+ rs232_rx_i => rs232_rx_i,
+ rs232_tx_o => rs232_tx_o,
+ br_clk_i => '1',
+ gpio_in => gpio_in,
+ gpio_out => gpio_out,
+ gpio_dir => gpio_dir
+ );
+ phi_addr <= io_addr(4 downto 2);
+
+ zpu : ZPUSmallCore
+ generic map(
+ WORD_SIZE => WORD_SIZE, ADDR_W => ADDR_W, MEM_W => BRAM_W,
+ D_CARE_VAL => D_CARE_VAL)
+ port map(
+ clk_i => clk_i, reset_i => rst_i, interrupt_i => '0',
+ break_o => break_o, dbg_o => dbg_o,
+ -- BRAM (text, data, bss and stack)
+ a_we_o => a_we, a_addr_o => a_addr, a_o => a_write, a_i => a_read,
+ b_we_o => b_we, b_addr_o => b_addr, b_o => b_write, b_i => b_read,
+ -- Memory mapped I/O
+ mem_busy_i => io_busy, data_i => io_read, data_o => io_write,
+ addr_o => io_addr, write_en_o => io_we, read_en_o => io_re);
+end architecture Structural; -- Entity: ZPU_Small1
+
diff --git a/zpu/hdl/zealot/roms/dmips_bram.vhdl b/zpu/hdl/zealot/roms/dmips_bram.vhdl
new file mode 100644
index 0000000..977626c
--- /dev/null
+++ b/zpu/hdl/zealot/roms/dmips_bram.vhdl
@@ -0,0 +1,4462 @@
+------------------------------------------------------------------------------
+---- ----
+---- Single Port RAM that maps to a Xilinx BRAM ----
+---- ----
+---- http://www.opencores.org/ ----
+---- ----
+---- Description: ----
+---- This is a program+data memory for the ZPU. It maps to a Xilinx BRAM ----
+---- ----
+---- To Do: ----
+---- - ----
+---- ----
+---- Author: ----
+---- - Salvador E. Tropea, salvador inti.gob.ar ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
+---- ----
+---- Distributed under the BSD license ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Design unit: SinglePortRAM(Xilinx) (Entity and architecture) ----
+---- File name: rom_s.in.vhdl (template used) ----
+---- Note: None ----
+---- Limitations: None known ----
+---- Errors: None known ----
+---- Library: work ----
+---- Dependencies: IEEE.std_logic_1164 ----
+---- IEEE.numeric_std ----
+---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
+---- Language: VHDL ----
+---- Wishbone: No ----
+---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
+---- Text editor: SETEdit 0.5.x ----
+---- ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity SinglePortRAM is
+ generic(
+ WORD_SIZE : integer:=32; -- Word Size 16/32
+ BYTE_BITS : integer:=2; -- Bits used to address bytes
+ BRAM_W : integer:=15); -- Address Width
+ port(
+ clk_i : in std_logic;
+ we_i : in std_logic;
+ re_i : in std_logic;
+ addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS);
+ write_i : in unsigned(WORD_SIZE-1 downto 0);
+ read_o : out unsigned(WORD_SIZE-1 downto 0);
+ busy_o : out std_logic);
+end entity SinglePortRAM;
+
+architecture Xilinx of SinglePortRAM is
+ type ram_type is array(natural range 0 to ((2**BRAM_W)/4)-1) of unsigned(WORD_SIZE-1 downto 0);
+ signal addr_r : unsigned(BRAM_W-1 downto BYTE_BITS);
+
+ signal ram : ram_type :=
+(
+ 0 => x"0b0b0b0b",
+ 1 => x"82700b0b",
+ 2 => x"80f8ec0c",
+ 3 => x"3a0b0b80",
+ 4 => x"e7ea0400",
+ 5 => x"00000000",
+ 6 => x"00000000",
+ 7 => x"00000000",
+ 8 => x"80088408",
+ 9 => x"88080b0b",
+ 10 => x"80e8b72d",
+ 11 => x"880c840c",
+ 12 => x"800c0400",
+ 13 => x"00000000",
+ 14 => x"00000000",
+ 15 => x"00000000",
+ 16 => x"71fd0608",
+ 17 => x"72830609",
+ 18 => x"81058205",
+ 19 => x"832b2a83",
+ 20 => x"ffff0652",
+ 21 => x"04000000",
+ 22 => x"00000000",
+ 23 => x"00000000",
+ 24 => x"71fd0608",
+ 25 => x"83ffff73",
+ 26 => x"83060981",
+ 27 => x"05820583",
+ 28 => x"2b2b0906",
+ 29 => x"7383ffff",
+ 30 => x"0b0b0b0b",
+ 31 => x"83a70400",
+ 32 => x"72098105",
+ 33 => x"72057373",
+ 34 => x"09060906",
+ 35 => x"73097306",
+ 36 => x"070a8106",
+ 37 => x"53510400",
+ 38 => x"00000000",
+ 39 => x"00000000",
+ 40 => x"72722473",
+ 41 => x"732e0753",
+ 42 => x"51040000",
+ 43 => x"00000000",
+ 44 => x"00000000",
+ 45 => x"00000000",
+ 46 => x"00000000",
+ 47 => x"00000000",
+ 48 => x"71737109",
+ 49 => x"71068106",
+ 50 => x"30720a10",
+ 51 => x"0a720a10",
+ 52 => x"0a31050a",
+ 53 => x"81065151",
+ 54 => x"53510400",
+ 55 => x"00000000",
+ 56 => x"72722673",
+ 57 => x"732e0753",
+ 58 => x"51040000",
+ 59 => x"00000000",
+ 60 => x"00000000",
+ 61 => x"00000000",
+ 62 => x"00000000",
+ 63 => x"00000000",
+ 64 => x"00000000",
+ 65 => x"00000000",
+ 66 => x"00000000",
+ 67 => x"00000000",
+ 68 => x"00000000",
+ 69 => x"00000000",
+ 70 => x"00000000",
+ 71 => x"00000000",
+ 72 => x"0b0b0b88",
+ 73 => x"c4040000",
+ 74 => x"00000000",
+ 75 => x"00000000",
+ 76 => x"00000000",
+ 77 => x"00000000",
+ 78 => x"00000000",
+ 79 => x"00000000",
+ 80 => x"720a722b",
+ 81 => x"0a535104",
+ 82 => x"00000000",
+ 83 => x"00000000",
+ 84 => x"00000000",
+ 85 => x"00000000",
+ 86 => x"00000000",
+ 87 => x"00000000",
+ 88 => x"72729f06",
+ 89 => x"0981050b",
+ 90 => x"0b0b88a7",
+ 91 => x"05040000",
+ 92 => x"00000000",
+ 93 => x"00000000",
+ 94 => x"00000000",
+ 95 => x"00000000",
+ 96 => x"72722aff",
+ 97 => x"739f062a",
+ 98 => x"0974090a",
+ 99 => x"8106ff05",
+ 100 => x"06075351",
+ 101 => x"04000000",
+ 102 => x"00000000",
+ 103 => x"00000000",
+ 104 => x"71715351",
+ 105 => x"020d0406",
+ 106 => x"73830609",
+ 107 => x"81058205",
+ 108 => x"832b0b2b",
+ 109 => x"0772fc06",
+ 110 => x"0c515104",
+ 111 => x"00000000",
+ 112 => x"72098105",
+ 113 => x"72050970",
+ 114 => x"81050906",
+ 115 => x"0a810653",
+ 116 => x"51040000",
+ 117 => x"00000000",
+ 118 => x"00000000",
+ 119 => x"00000000",
+ 120 => x"72098105",
+ 121 => x"72050970",
+ 122 => x"81050906",
+ 123 => x"0a098106",
+ 124 => x"53510400",
+ 125 => x"00000000",
+ 126 => x"00000000",
+ 127 => x"00000000",
+ 128 => x"71098105",
+ 129 => x"52040000",
+ 130 => x"00000000",
+ 131 => x"00000000",
+ 132 => x"00000000",
+ 133 => x"00000000",
+ 134 => x"00000000",
+ 135 => x"00000000",
+ 136 => x"72720981",
+ 137 => x"05055351",
+ 138 => x"04000000",
+ 139 => x"00000000",
+ 140 => x"00000000",
+ 141 => x"00000000",
+ 142 => x"00000000",
+ 143 => x"00000000",
+ 144 => x"72097206",
+ 145 => x"73730906",
+ 146 => x"07535104",
+ 147 => x"00000000",
+ 148 => x"00000000",
+ 149 => x"00000000",
+ 150 => x"00000000",
+ 151 => x"00000000",
+ 152 => x"71fc0608",
+ 153 => x"72830609",
+ 154 => x"81058305",
+ 155 => x"1010102a",
+ 156 => x"81ff0652",
+ 157 => x"04000000",
+ 158 => x"00000000",
+ 159 => x"00000000",
+ 160 => x"71fc0608",
+ 161 => x"0b0b80f8",
+ 162 => x"d8738306",
+ 163 => x"10100508",
+ 164 => x"060b0b0b",
+ 165 => x"88aa0400",
+ 166 => x"00000000",
+ 167 => x"00000000",
+ 168 => x"80088408",
+ 169 => x"88087575",
+ 170 => x"0b0b80ce",
+ 171 => x"b62d5050",
+ 172 => x"80085688",
+ 173 => x"0c840c80",
+ 174 => x"0c510400",
+ 175 => x"00000000",
+ 176 => x"80088408",
+ 177 => x"88087575",
+ 178 => x"0b0b80cf",
+ 179 => x"e82d5050",
+ 180 => x"80085688",
+ 181 => x"0c840c80",
+ 182 => x"0c510400",
+ 183 => x"00000000",
+ 184 => x"72097081",
+ 185 => x"0509060a",
+ 186 => x"8106ff05",
+ 187 => x"70547106",
+ 188 => x"73097274",
+ 189 => x"05ff0506",
+ 190 => x"07515151",
+ 191 => x"04000000",
+ 192 => x"72097081",
+ 193 => x"0509060a",
+ 194 => x"098106ff",
+ 195 => x"05705471",
+ 196 => x"06730972",
+ 197 => x"7405ff05",
+ 198 => x"06075151",
+ 199 => x"51040000",
+ 200 => x"05ff0504",
+ 201 => x"00000000",
+ 202 => x"00000000",
+ 203 => x"00000000",
+ 204 => x"00000000",
+ 205 => x"00000000",
+ 206 => x"00000000",
+ 207 => x"00000000",
+ 208 => x"810b0b0b",
+ 209 => x"80f8e80c",
+ 210 => x"51040000",
+ 211 => x"00000000",
+ 212 => x"00000000",
+ 213 => x"00000000",
+ 214 => x"00000000",
+ 215 => x"00000000",
+ 216 => x"71810552",
+ 217 => x"04000000",
+ 218 => x"00000000",
+ 219 => x"00000000",
+ 220 => x"00000000",
+ 221 => x"00000000",
+ 222 => x"00000000",
+ 223 => x"00000000",
+ 224 => x"00000000",
+ 225 => x"00000000",
+ 226 => x"00000000",
+ 227 => x"00000000",
+ 228 => x"00000000",
+ 229 => x"00000000",
+ 230 => x"00000000",
+ 231 => x"00000000",
+ 232 => x"02840572",
+ 233 => x"10100552",
+ 234 => x"04000000",
+ 235 => x"00000000",
+ 236 => x"00000000",
+ 237 => x"00000000",
+ 238 => x"00000000",
+ 239 => x"00000000",
+ 240 => x"00000000",
+ 241 => x"00000000",
+ 242 => x"00000000",
+ 243 => x"00000000",
+ 244 => x"00000000",
+ 245 => x"00000000",
+ 246 => x"00000000",
+ 247 => x"00000000",
+ 248 => x"717105ff",
+ 249 => x"05715351",
+ 250 => x"020d0400",
+ 251 => x"00000000",
+ 252 => x"00000000",
+ 253 => x"00000000",
+ 254 => x"00000000",
+ 255 => x"00000000",
+ 256 => x"83803f80",
+ 257 => x"e2953f04",
+ 258 => x"10101010",
+ 259 => x"10101010",
+ 260 => x"10101010",
+ 261 => x"10101010",
+ 262 => x"10101010",
+ 263 => x"10101010",
+ 264 => x"10101010",
+ 265 => x"10101053",
+ 266 => x"51047381",
+ 267 => x"ff067383",
+ 268 => x"06098105",
+ 269 => x"83051010",
+ 270 => x"102b0772",
+ 271 => x"fc060c51",
+ 272 => x"51043c04",
+ 273 => x"72728072",
+ 274 => x"8106ff05",
+ 275 => x"09720605",
+ 276 => x"71105272",
+ 277 => x"0a100a53",
+ 278 => x"72ed3851",
+ 279 => x"51535104",
+ 280 => x"ff3d0d0b",
+ 281 => x"0b8188e0",
+ 282 => x"08527108",
+ 283 => x"70882a81",
+ 284 => x"32708106",
+ 285 => x"51515170",
+ 286 => x"f1387372",
+ 287 => x"0c833d0d",
+ 288 => x"0480f8e8",
+ 289 => x"08802ea4",
+ 290 => x"3880f8ec",
+ 291 => x"08822ebd",
+ 292 => x"38838080",
+ 293 => x"0b0b0b81",
+ 294 => x"88e00c82",
+ 295 => x"a0800b81",
+ 296 => x"88e40c82",
+ 297 => x"90800b81",
+ 298 => x"88e80c04",
+ 299 => x"f8808080",
+ 300 => x"a40b0b0b",
+ 301 => x"8188e00c",
+ 302 => x"f8808082",
+ 303 => x"800b8188",
+ 304 => x"e40cf880",
+ 305 => x"8084800b",
+ 306 => x"8188e80c",
+ 307 => x"0480c0a8",
+ 308 => x"808c0b0b",
+ 309 => x"0b8188e0",
+ 310 => x"0c80c0a8",
+ 311 => x"80940b81",
+ 312 => x"88e40c0b",
+ 313 => x"0b80eac8",
+ 314 => x"0b8188e8",
+ 315 => x"0c04f23d",
+ 316 => x"0d608188",
+ 317 => x"e408565d",
+ 318 => x"82750c80",
+ 319 => x"59805a80",
+ 320 => x"0b8f3d5d",
+ 321 => x"5b7a1010",
+ 322 => x"15700871",
+ 323 => x"08719f2c",
+ 324 => x"7e852b58",
+ 325 => x"55557d53",
+ 326 => x"59579d94",
+ 327 => x"3f7d7f7a",
+ 328 => x"72077c72",
+ 329 => x"07717160",
+ 330 => x"8105415f",
+ 331 => x"5d5b5957",
+ 332 => x"55817b27",
+ 333 => x"8f38767d",
+ 334 => x"0c77841e",
+ 335 => x"0c7c800c",
+ 336 => x"903d0d04",
+ 337 => x"8188e408",
+ 338 => x"55ffba39",
+ 339 => x"ff3d0d81",
+ 340 => x"88ec3351",
+ 341 => x"70a73880",
+ 342 => x"f8f40870",
+ 343 => x"08525270",
+ 344 => x"802e9438",
+ 345 => x"841280f8",
+ 346 => x"f40c702d",
+ 347 => x"80f8f408",
+ 348 => x"70085252",
+ 349 => x"70ee3881",
+ 350 => x"0b8188ec",
+ 351 => x"34833d0d",
+ 352 => x"0404803d",
+ 353 => x"0d0b0b81",
+ 354 => x"88dc0880",
+ 355 => x"2e8e380b",
+ 356 => x"0b0b0b80",
+ 357 => x"0b802e09",
+ 358 => x"81068538",
+ 359 => x"823d0d04",
+ 360 => x"0b0b8188",
+ 361 => x"dc510b0b",
+ 362 => x"0bf4d53f",
+ 363 => x"823d0d04",
+ 364 => x"04ff3d0d",
+ 365 => x"028f0533",
+ 366 => x"52718a2e",
+ 367 => x"8a387151",
+ 368 => x"fd9e3f83",
+ 369 => x"3d0d048d",
+ 370 => x"51fd953f",
+ 371 => x"7151fd90",
+ 372 => x"3f833d0d",
+ 373 => x"04ce3d0d",
+ 374 => x"b53d7070",
+ 375 => x"84055208",
+ 376 => x"8bb15c56",
+ 377 => x"a53d5e5c",
+ 378 => x"80757081",
+ 379 => x"05573376",
+ 380 => x"5b555873",
+ 381 => x"782e80c1",
+ 382 => x"388e3d5b",
+ 383 => x"73a52e09",
+ 384 => x"810680c5",
+ 385 => x"38787081",
+ 386 => x"055a3354",
+ 387 => x"7380e42e",
+ 388 => x"81b63873",
+ 389 => x"80e42480",
+ 390 => x"c6387380",
+ 391 => x"e32ea138",
+ 392 => x"8052a551",
+ 393 => x"792d8052",
+ 394 => x"7351792d",
+ 395 => x"82185878",
+ 396 => x"7081055a",
+ 397 => x"335473c4",
+ 398 => x"3877800c",
+ 399 => x"b43d0d04",
+ 400 => x"7b841d83",
+ 401 => x"1233565d",
+ 402 => x"57805273",
+ 403 => x"51792d81",
+ 404 => x"18797081",
+ 405 => x"055b3355",
+ 406 => x"5873ffa0",
+ 407 => x"38db3973",
+ 408 => x"80f32e09",
+ 409 => x"8106ffb8",
+ 410 => x"387b841d",
+ 411 => x"7108595d",
+ 412 => x"56807733",
+ 413 => x"55567376",
+ 414 => x"2e8d3881",
+ 415 => x"16701870",
+ 416 => x"33575556",
+ 417 => x"74f538ff",
+ 418 => x"16558076",
+ 419 => x"25ffa038",
+ 420 => x"76708105",
+ 421 => x"58335480",
+ 422 => x"52735179",
+ 423 => x"2d811875",
+ 424 => x"ff175757",
+ 425 => x"58807625",
+ 426 => x"ff853876",
+ 427 => x"70810558",
+ 428 => x"33548052",
+ 429 => x"7351792d",
+ 430 => x"811875ff",
+ 431 => x"17575758",
+ 432 => x"758024cc",
+ 433 => x"38fee839",
+ 434 => x"7b841d71",
+ 435 => x"0870719f",
+ 436 => x"2c595359",
+ 437 => x"5d568075",
+ 438 => x"24819338",
+ 439 => x"757d7c58",
+ 440 => x"56548057",
+ 441 => x"73772e09",
+ 442 => x"8106b638",
+ 443 => x"b07b3402",
+ 444 => x"b505567a",
+ 445 => x"762e9738",
+ 446 => x"ff165675",
+ 447 => x"33757081",
+ 448 => x"05573481",
+ 449 => x"17577a76",
+ 450 => x"2e098106",
+ 451 => x"eb388075",
+ 452 => x"34767dff",
+ 453 => x"12575856",
+ 454 => x"758024fe",
+ 455 => x"f338fe8f",
+ 456 => x"398a5273",
+ 457 => x"5180c1c0",
+ 458 => x"3f800880",
+ 459 => x"eacc0533",
+ 460 => x"76708105",
+ 461 => x"58348a52",
+ 462 => x"7351bffa",
+ 463 => x"3f800854",
+ 464 => x"8008802e",
+ 465 => x"ffad388a",
+ 466 => x"52735180",
+ 467 => x"c19a3f80",
+ 468 => x"0880eacc",
+ 469 => x"05337670",
+ 470 => x"81055834",
+ 471 => x"8a527351",
+ 472 => x"bfd43f80",
+ 473 => x"08548008",
+ 474 => x"ffb738ff",
+ 475 => x"86397452",
+ 476 => x"7653b43d",
+ 477 => x"ffb80551",
+ 478 => x"978a3fa3",
+ 479 => x"3d0856fe",
+ 480 => x"db39803d",
+ 481 => x"0d80c10b",
+ 482 => x"81d7b834",
+ 483 => x"800b81d9",
+ 484 => x"940c7080",
+ 485 => x"0c823d0d",
+ 486 => x"04ff3d0d",
+ 487 => x"800b81d7",
+ 488 => x"b8335252",
+ 489 => x"7080c12e",
+ 490 => x"99387181",
+ 491 => x"d9940807",
+ 492 => x"81d9940c",
+ 493 => x"80c20b81",
+ 494 => x"d7bc3470",
+ 495 => x"800c833d",
+ 496 => x"0d04810b",
+ 497 => x"81d99408",
+ 498 => x"0781d994",
+ 499 => x"0c80c20b",
+ 500 => x"81d7bc34",
+ 501 => x"70800c83",
+ 502 => x"3d0d04fd",
+ 503 => x"3d0d7570",
+ 504 => x"088a0553",
+ 505 => x"5381d7b8",
+ 506 => x"33517080",
+ 507 => x"c12e8b38",
+ 508 => x"73f33870",
+ 509 => x"800c853d",
+ 510 => x"0d04ff12",
+ 511 => x"7081d7b4",
+ 512 => x"0831740c",
+ 513 => x"800c853d",
+ 514 => x"0d04fc3d",
+ 515 => x"0d81d7c0",
+ 516 => x"08557480",
+ 517 => x"2e8c3876",
+ 518 => x"7508710c",
+ 519 => x"81d7c008",
+ 520 => x"56548c15",
+ 521 => x"5381d7b4",
+ 522 => x"08528a51",
+ 523 => x"8fe73f73",
+ 524 => x"800c863d",
+ 525 => x"0d04fb3d",
+ 526 => x"0d777008",
+ 527 => x"5656b053",
+ 528 => x"81d7c008",
+ 529 => x"52745180",
+ 530 => x"cdff3f85",
+ 531 => x"0b8c170c",
+ 532 => x"850b8c16",
+ 533 => x"0c750875",
+ 534 => x"0c81d7c0",
+ 535 => x"08547380",
+ 536 => x"2e8a3873",
+ 537 => x"08750c81",
+ 538 => x"d7c00854",
+ 539 => x"8c145381",
+ 540 => x"d7b40852",
+ 541 => x"8a518f9d",
+ 542 => x"3f841508",
+ 543 => x"ad38860b",
+ 544 => x"8c160c88",
+ 545 => x"15528816",
+ 546 => x"08518ea9",
+ 547 => x"3f81d7c0",
+ 548 => x"08700876",
+ 549 => x"0c548c15",
+ 550 => x"7054548a",
+ 551 => x"52730851",
+ 552 => x"8ef33f73",
+ 553 => x"800c873d",
+ 554 => x"0d047508",
+ 555 => x"54b05373",
+ 556 => x"52755180",
+ 557 => x"cd933f73",
+ 558 => x"800c873d",
+ 559 => x"0d04d93d",
+ 560 => x"0d80f980",
+ 561 => x"0b8188e8",
+ 562 => x"0cb05180",
+ 563 => x"c0e43f80",
+ 564 => x"0881d7b0",
+ 565 => x"0cb05180",
+ 566 => x"c0d83f80",
+ 567 => x"0881d7c0",
+ 568 => x"0c81d7b0",
+ 569 => x"0880080c",
+ 570 => x"800b8008",
+ 571 => x"84050c82",
+ 572 => x"0b800888",
+ 573 => x"050ca80b",
+ 574 => x"80088c05",
+ 575 => x"0c9f5380",
+ 576 => x"ead85280",
+ 577 => x"08900551",
+ 578 => x"80ccbe3f",
+ 579 => x"a13d5e9f",
+ 580 => x"5380eaf8",
+ 581 => x"527d5180",
+ 582 => x"ccaf3f8a",
+ 583 => x"0b8195f4",
+ 584 => x"0c80f59c",
+ 585 => x"51f9ae3f",
+ 586 => x"80eb9851",
+ 587 => x"f9a73f80",
+ 588 => x"f59c51f9",
+ 589 => x"a03f80f8",
+ 590 => x"fc08802e",
+ 591 => x"89d73880",
+ 592 => x"ebc851f9",
+ 593 => x"903f80f5",
+ 594 => x"9c51f989",
+ 595 => x"3f80f8f8",
+ 596 => x"085280eb",
+ 597 => x"f451f8fd",
+ 598 => x"3f818990",
+ 599 => x"5180d5da",
+ 600 => x"3f810b9a",
+ 601 => x"3d5e5b80",
+ 602 => x"0b80f8f8",
+ 603 => x"082582d6",
+ 604 => x"38903d5f",
+ 605 => x"80c10b81",
+ 606 => x"d7b83481",
+ 607 => x"0b81d994",
+ 608 => x"0c80c20b",
+ 609 => x"81d7bc34",
+ 610 => x"8240835a",
+ 611 => x"9f5380ec",
+ 612 => x"a4527c51",
+ 613 => x"80cbb23f",
+ 614 => x"8141807d",
+ 615 => x"537e5256",
+ 616 => x"8e973f80",
+ 617 => x"08762e09",
+ 618 => x"81068338",
+ 619 => x"81567581",
+ 620 => x"d9940c7f",
+ 621 => x"70585675",
+ 622 => x"8325a238",
+ 623 => x"75101016",
+ 624 => x"fd0542a9",
+ 625 => x"3dffa405",
+ 626 => x"53835276",
+ 627 => x"518cc63f",
+ 628 => x"7f810570",
+ 629 => x"41705856",
+ 630 => x"837624e0",
+ 631 => x"38615475",
+ 632 => x"53818998",
+ 633 => x"5281d7cc",
+ 634 => x"518cba3f",
+ 635 => x"81d7c008",
+ 636 => x"70085858",
+ 637 => x"b0537752",
+ 638 => x"765180ca",
+ 639 => x"cc3f850b",
+ 640 => x"8c190c85",
+ 641 => x"0b8c180c",
+ 642 => x"7708770c",
+ 643 => x"81d7c008",
+ 644 => x"5675802e",
+ 645 => x"8a387508",
+ 646 => x"770c81d7",
+ 647 => x"c008568c",
+ 648 => x"165381d7",
+ 649 => x"b408528a",
+ 650 => x"518bea3f",
+ 651 => x"84170887",
+ 652 => x"eb38860b",
+ 653 => x"8c180c88",
+ 654 => x"17528818",
+ 655 => x"08518af5",
+ 656 => x"3f81d7c0",
+ 657 => x"08700878",
+ 658 => x"0c568c17",
+ 659 => x"7054598a",
+ 660 => x"52780851",
+ 661 => x"8bbf3f80",
+ 662 => x"c10b81d7",
+ 663 => x"bc335757",
+ 664 => x"767626a2",
+ 665 => x"3880c352",
+ 666 => x"76518ca3",
+ 667 => x"3f800861",
+ 668 => x"2e89e638",
+ 669 => x"81177081",
+ 670 => x"ff0681d7",
+ 671 => x"bc335858",
+ 672 => x"58757727",
+ 673 => x"e0387960",
+ 674 => x"29627054",
+ 675 => x"71535b59",
+ 676 => x"b9a43f80",
+ 677 => x"0840787a",
+ 678 => x"31708729",
+ 679 => x"80083180",
+ 680 => x"088a0581",
+ 681 => x"d7b83381",
+ 682 => x"d7b4085e",
+ 683 => x"5b525a56",
+ 684 => x"7780c12e",
+ 685 => x"89d0387b",
+ 686 => x"f738811b",
+ 687 => x"5b80f8f8",
+ 688 => x"087b25fd",
+ 689 => x"af3881d7",
+ 690 => x"a85180d2",
+ 691 => x"ed3f80ec",
+ 692 => x"c451f681",
+ 693 => x"3f80f59c",
+ 694 => x"51f5fa3f",
+ 695 => x"80ecd451",
+ 696 => x"f5f33f80",
+ 697 => x"f59c51f5",
+ 698 => x"ec3f81d7",
+ 699 => x"b4085280",
+ 700 => x"ed8c51f5",
+ 701 => x"e03f8552",
+ 702 => x"80eda851",
+ 703 => x"f5d73f81",
+ 704 => x"d9940852",
+ 705 => x"80edc451",
+ 706 => x"f5cb3f81",
+ 707 => x"5280eda8",
+ 708 => x"51f5c23f",
+ 709 => x"81d7b833",
+ 710 => x"5280ede0",
+ 711 => x"51f5b63f",
+ 712 => x"80c15280",
+ 713 => x"edfc51f5",
+ 714 => x"ac3f81d7",
+ 715 => x"bc335280",
+ 716 => x"ee9851f5",
+ 717 => x"a03f80c2",
+ 718 => x"5280edfc",
+ 719 => x"51f5963f",
+ 720 => x"81d7ec08",
+ 721 => x"5280eeb4",
+ 722 => x"51f58a3f",
+ 723 => x"875280ed",
+ 724 => x"a851f581",
+ 725 => x"3f8195f4",
+ 726 => x"085280ee",
+ 727 => x"d051f4f5",
+ 728 => x"3f80eeec",
+ 729 => x"51f4ee3f",
+ 730 => x"80ef9851",
+ 731 => x"f4e73f81",
+ 732 => x"d7c00870",
+ 733 => x"08535a80",
+ 734 => x"efa451f4",
+ 735 => x"d83f80ef",
+ 736 => x"c051f4d1",
+ 737 => x"3f81d7c0",
+ 738 => x"08841108",
+ 739 => x"535680ef",
+ 740 => x"f451f4c1",
+ 741 => x"3f805280",
+ 742 => x"eda851f4",
+ 743 => x"b83f81d7",
+ 744 => x"c0088811",
+ 745 => x"08535880",
+ 746 => x"f09051f4",
+ 747 => x"a83f8252",
+ 748 => x"80eda851",
+ 749 => x"f49f3f81",
+ 750 => x"d7c0088c",
+ 751 => x"11085357",
+ 752 => x"80f0ac51",
+ 753 => x"f48f3f91",
+ 754 => x"5280eda8",
+ 755 => x"51f4863f",
+ 756 => x"81d7c008",
+ 757 => x"90055280",
+ 758 => x"f0c851f3",
+ 759 => x"f83f80f0",
+ 760 => x"e451f3f1",
+ 761 => x"3f80f19c",
+ 762 => x"51f3ea3f",
+ 763 => x"81d7b008",
+ 764 => x"7008535f",
+ 765 => x"80efa451",
+ 766 => x"f3db3f80",
+ 767 => x"f1b051f3",
+ 768 => x"d43f81d7",
+ 769 => x"b0088411",
+ 770 => x"08535b80",
+ 771 => x"eff451f3",
+ 772 => x"c43f8052",
+ 773 => x"80eda851",
+ 774 => x"f3bb3f81",
+ 775 => x"d7b00888",
+ 776 => x"1108535c",
+ 777 => x"80f09051",
+ 778 => x"f3ab3f81",
+ 779 => x"5280eda8",
+ 780 => x"51f3a23f",
+ 781 => x"81d7b008",
+ 782 => x"8c110853",
+ 783 => x"5a80f0ac",
+ 784 => x"51f3923f",
+ 785 => x"925280ed",
+ 786 => x"a851f389",
+ 787 => x"3f81d7b0",
+ 788 => x"08900552",
+ 789 => x"80f0c851",
+ 790 => x"f2fb3f80",
+ 791 => x"f0e451f2",
+ 792 => x"f43f7f52",
+ 793 => x"80f1f051",
+ 794 => x"f2eb3f85",
+ 795 => x"5280eda8",
+ 796 => x"51f2e23f",
+ 797 => x"785280f2",
+ 798 => x"8c51f2d9",
+ 799 => x"3f8d5280",
+ 800 => x"eda851f2",
+ 801 => x"d03f6152",
+ 802 => x"80f2a851",
+ 803 => x"f2c73f87",
+ 804 => x"5280eda8",
+ 805 => x"51f2be3f",
+ 806 => x"605280f2",
+ 807 => x"c451f2b5",
+ 808 => x"3f815280",
+ 809 => x"eda851f2",
+ 810 => x"ac3f7d52",
+ 811 => x"80f2e051",
+ 812 => x"f2a33f80",
+ 813 => x"f2fc51f2",
+ 814 => x"9c3f7c52",
+ 815 => x"80f3b451",
+ 816 => x"f2933f80",
+ 817 => x"f3d051f2",
+ 818 => x"8c3f80f5",
+ 819 => x"9c51f285",
+ 820 => x"3f81d7a8",
+ 821 => x"0881d7ac",
+ 822 => x"08818990",
+ 823 => x"08818994",
+ 824 => x"08727131",
+ 825 => x"70742675",
+ 826 => x"74317072",
+ 827 => x"31818988",
+ 828 => x"0c444481",
+ 829 => x"898c0c81",
+ 830 => x"898c0856",
+ 831 => x"80f48855",
+ 832 => x"5c595758",
+ 833 => x"f1cf3f81",
+ 834 => x"89880856",
+ 835 => x"80762582",
+ 836 => x"a43880f8",
+ 837 => x"f8087071",
+ 838 => x"9f2c9a3d",
+ 839 => x"53565681",
+ 840 => x"89880881",
+ 841 => x"898c0841",
+ 842 => x"537f5470",
+ 843 => x"525a8ef6",
+ 844 => x"3f66685f",
+ 845 => x"8188f80c",
+ 846 => x"7d8188fc",
+ 847 => x"0c80f8f8",
+ 848 => x"08709f2c",
+ 849 => x"58568058",
+ 850 => x"bd84c078",
+ 851 => x"55557652",
+ 852 => x"75537951",
+ 853 => x"87d23f95",
+ 854 => x"3d818988",
+ 855 => x"0881898c",
+ 856 => x"0841557f",
+ 857 => x"56676940",
+ 858 => x"537e5470",
+ 859 => x"525c8eb6",
+ 860 => x"3f64665e",
+ 861 => x"8189800c",
+ 862 => x"7c818984",
+ 863 => x"0c80f8f8",
+ 864 => x"08709f2c",
+ 865 => x"40588057",
+ 866 => x"83dceb94",
+ 867 => x"80775555",
+ 868 => x"7e527753",
+ 869 => x"7b518790",
+ 870 => x"3f64665d",
+ 871 => x"5b805e8d",
+ 872 => x"dd7e5555",
+ 873 => x"81898808",
+ 874 => x"81898c08",
+ 875 => x"59527753",
+ 876 => x"795186f4",
+ 877 => x"3f666840",
+ 878 => x"547e557a",
+ 879 => x"527b53a9",
+ 880 => x"3dffa805",
+ 881 => x"518ddf3f",
+ 882 => x"62645e81",
+ 883 => x"d7c40c7c",
+ 884 => x"81d7c80c",
+ 885 => x"80f49851",
+ 886 => x"effb3f81",
+ 887 => x"88fc0852",
+ 888 => x"80f4c851",
+ 889 => x"efef3f80",
+ 890 => x"f4d051ef",
+ 891 => x"e83f8189",
+ 892 => x"84085280",
+ 893 => x"f4c851ef",
+ 894 => x"dc3f81d7",
+ 895 => x"c8085280",
+ 896 => x"f58051ef",
+ 897 => x"d03f80f5",
+ 898 => x"9c51efc9",
+ 899 => x"3f800b80",
+ 900 => x"0ca93d0d",
+ 901 => x"0480f5a0",
+ 902 => x"51f6a839",
+ 903 => x"770857b0",
+ 904 => x"53765277",
+ 905 => x"5180c2a1",
+ 906 => x"3f80c10b",
+ 907 => x"81d7bc33",
+ 908 => x"5757f8ac",
+ 909 => x"39758a38",
+ 910 => x"81898c08",
+ 911 => x"8126fdd2",
+ 912 => x"3880f5d0",
+ 913 => x"51ef8e3f",
+ 914 => x"80f68851",
+ 915 => x"ef873f80",
+ 916 => x"f59c51ef",
+ 917 => x"803f80f8",
+ 918 => x"f8087071",
+ 919 => x"9f2c9a3d",
+ 920 => x"53565681",
+ 921 => x"89880881",
+ 922 => x"898c0841",
+ 923 => x"537f5470",
+ 924 => x"525a8cb2",
+ 925 => x"3f66685f",
+ 926 => x"8188f80c",
+ 927 => x"7d8188fc",
+ 928 => x"0c80f8f8",
+ 929 => x"08709f2c",
+ 930 => x"58568058",
+ 931 => x"bd84c078",
+ 932 => x"55557652",
+ 933 => x"75537951",
+ 934 => x"858e3f95",
+ 935 => x"3d818988",
+ 936 => x"0881898c",
+ 937 => x"0841557f",
+ 938 => x"56676940",
+ 939 => x"537e5470",
+ 940 => x"525c8bf2",
+ 941 => x"3f64665e",
+ 942 => x"8189800c",
+ 943 => x"7c818984",
+ 944 => x"0c80f8f8",
+ 945 => x"08709f2c",
+ 946 => x"40588057",
+ 947 => x"83dceb94",
+ 948 => x"80775555",
+ 949 => x"7e527753",
+ 950 => x"7b5184cc",
+ 951 => x"3f64665d",
+ 952 => x"5b805e8d",
+ 953 => x"dd7e5555",
+ 954 => x"81898808",
+ 955 => x"81898c08",
+ 956 => x"59527753",
+ 957 => x"795184b0",
+ 958 => x"3f666840",
+ 959 => x"547e557a",
+ 960 => x"527b53a9",
+ 961 => x"3dffa805",
+ 962 => x"518b9b3f",
+ 963 => x"62645e81",
+ 964 => x"d7c40c7c",
+ 965 => x"81d7c80c",
+ 966 => x"80f49851",
+ 967 => x"edb73f81",
+ 968 => x"88fc0852",
+ 969 => x"80f4c851",
+ 970 => x"edab3f80",
+ 971 => x"f4d051ed",
+ 972 => x"a43f8189",
+ 973 => x"84085280",
+ 974 => x"f4c851ed",
+ 975 => x"983f81d7",
+ 976 => x"c8085280",
+ 977 => x"f58051ed",
+ 978 => x"8c3f80f5",
+ 979 => x"9c51ed85",
+ 980 => x"3f800b80",
+ 981 => x"0ca93d0d",
+ 982 => x"04a93dff",
+ 983 => x"a0055280",
+ 984 => x"5180d23f",
+ 985 => x"9f5380f6",
+ 986 => x"a8527c51",
+ 987 => x"bfdb3f7a",
+ 988 => x"7b81d7b4",
+ 989 => x"0c811870",
+ 990 => x"81ff0681",
+ 991 => x"d7bc3359",
+ 992 => x"59595af5",
+ 993 => x"fc39ff16",
+ 994 => x"707b3160",
+ 995 => x"0c5c800b",
+ 996 => x"811c5c5c",
+ 997 => x"80f8f808",
+ 998 => x"7b25f3d8",
+ 999 => x"38f6a739",
+ 1000 => x"ff3d0d73",
+ 1001 => x"82327030",
+ 1002 => x"70720780",
+ 1003 => x"25800c52",
+ 1004 => x"52833d0d",
+ 1005 => x"04fe3d0d",
+ 1006 => x"74767153",
+ 1007 => x"54527182",
+ 1008 => x"2e833883",
+ 1009 => x"5171812e",
+ 1010 => x"9a388172",
+ 1011 => x"269f3871",
+ 1012 => x"822eb838",
+ 1013 => x"71842ea9",
+ 1014 => x"3870730c",
+ 1015 => x"70800c84",
+ 1016 => x"3d0d0480",
+ 1017 => x"e40b81d7",
+ 1018 => x"b408258b",
+ 1019 => x"3880730c",
+ 1020 => x"70800c84",
+ 1021 => x"3d0d0483",
+ 1022 => x"730c7080",
+ 1023 => x"0c843d0d",
+ 1024 => x"0482730c",
+ 1025 => x"70800c84",
+ 1026 => x"3d0d0481",
+ 1027 => x"730c7080",
+ 1028 => x"0c843d0d",
+ 1029 => x"04803d0d",
+ 1030 => x"74741482",
+ 1031 => x"05710c80",
+ 1032 => x"0c823d0d",
+ 1033 => x"04f73d0d",
+ 1034 => x"7b7d7f61",
+ 1035 => x"85127082",
+ 1036 => x"2b751170",
+ 1037 => x"74717084",
+ 1038 => x"05530c5a",
+ 1039 => x"5a5d5b76",
+ 1040 => x"0c7980f8",
+ 1041 => x"180c7986",
+ 1042 => x"12525758",
+ 1043 => x"5a5a7676",
+ 1044 => x"24993876",
+ 1045 => x"b329822b",
+ 1046 => x"79115153",
+ 1047 => x"76737084",
+ 1048 => x"05550c81",
+ 1049 => x"14547574",
+ 1050 => x"25f23876",
+ 1051 => x"81cc2919",
+ 1052 => x"fc110881",
+ 1053 => x"05fc120c",
+ 1054 => x"7a197008",
+ 1055 => x"9fa0130c",
+ 1056 => x"5856850b",
+ 1057 => x"81d7b40c",
+ 1058 => x"75800c8b",
+ 1059 => x"3d0d04fe",
+ 1060 => x"3d0d0293",
+ 1061 => x"05335180",
+ 1062 => x"02840597",
+ 1063 => x"05335452",
+ 1064 => x"70732e88",
+ 1065 => x"3871800c",
+ 1066 => x"843d0d04",
+ 1067 => x"7081d7b8",
+ 1068 => x"34810b80",
+ 1069 => x"0c843d0d",
+ 1070 => x"04f83d0d",
+ 1071 => x"7a7c5956",
+ 1072 => x"820b8319",
+ 1073 => x"55557416",
+ 1074 => x"70337533",
+ 1075 => x"5b515372",
+ 1076 => x"792e80c6",
+ 1077 => x"3880c10b",
+ 1078 => x"81168116",
+ 1079 => x"56565782",
+ 1080 => x"7525e338",
+ 1081 => x"ffa91770",
+ 1082 => x"81ff0655",
+ 1083 => x"59738226",
+ 1084 => x"83388755",
+ 1085 => x"81537680",
+ 1086 => x"d22e9838",
+ 1087 => x"77527551",
+ 1088 => x"be963f80",
+ 1089 => x"53728008",
+ 1090 => x"25893887",
+ 1091 => x"1581d7b4",
+ 1092 => x"0c815372",
+ 1093 => x"800c8a3d",
+ 1094 => x"0d047281",
+ 1095 => x"d7b83482",
+ 1096 => x"7525ffa2",
+ 1097 => x"38ffbd39",
+ 1098 => x"8c08028c",
+ 1099 => x"0ceb3d0d",
+ 1100 => x"800b8c08",
+ 1101 => x"f0050c80",
+ 1102 => x"0b8c08f4",
+ 1103 => x"050c8c08",
+ 1104 => x"8c05088c",
+ 1105 => x"08900508",
+ 1106 => x"5654738c",
+ 1107 => x"08f0050c",
+ 1108 => x"748c08f4",
+ 1109 => x"050c8c08",
+ 1110 => x"f8058c08",
+ 1111 => x"f0055656",
+ 1112 => x"88705475",
+ 1113 => x"53765254",
+ 1114 => x"bbdf3f80",
+ 1115 => x"0b8c08e8",
+ 1116 => x"050c800b",
+ 1117 => x"8c08ec05",
+ 1118 => x"0c8c0894",
+ 1119 => x"05088c08",
+ 1120 => x"98050856",
+ 1121 => x"54738c08",
+ 1122 => x"e8050c74",
+ 1123 => x"8c08ec05",
+ 1124 => x"0c8c08f0",
+ 1125 => x"058c08e8",
+ 1126 => x"05565688",
+ 1127 => x"70547553",
+ 1128 => x"765254bb",
+ 1129 => x"a43f800b",
+ 1130 => x"8c08e805",
+ 1131 => x"0c800b8c",
+ 1132 => x"08ec050c",
+ 1133 => x"8c08fc05",
+ 1134 => x"0883ffff",
+ 1135 => x"068c08cc",
+ 1136 => x"050c8c08",
+ 1137 => x"fc050890",
+ 1138 => x"2a8c08c4",
+ 1139 => x"050c8c08",
+ 1140 => x"f4050883",
+ 1141 => x"ffff068c",
+ 1142 => x"08c8050c",
+ 1143 => x"8c08f405",
+ 1144 => x"08902a8c",
+ 1145 => x"08c0050c",
+ 1146 => x"8c08cc05",
+ 1147 => x"088c08c8",
+ 1148 => x"05082970",
+ 1149 => x"8c08dc05",
+ 1150 => x"0c8c08cc",
+ 1151 => x"05088c08",
+ 1152 => x"c0050829",
+ 1153 => x"708c08d8",
+ 1154 => x"050c8c08",
+ 1155 => x"c405088c",
+ 1156 => x"08c80508",
+ 1157 => x"29708c08",
+ 1158 => x"d4050c8c",
+ 1159 => x"08c40508",
+ 1160 => x"8c08c005",
+ 1161 => x"0829708c",
+ 1162 => x"08d0050c",
+ 1163 => x"8c08dc05",
+ 1164 => x"08902a8c",
+ 1165 => x"08d80508",
+ 1166 => x"118c08d8",
+ 1167 => x"050c8c08",
+ 1168 => x"d805088c",
+ 1169 => x"08d40508",
+ 1170 => x"058c08d8",
+ 1171 => x"050c5151",
+ 1172 => x"5151548c",
+ 1173 => x"08d80508",
+ 1174 => x"8c08d405",
+ 1175 => x"08278f38",
+ 1176 => x"8c08d005",
+ 1177 => x"08848080",
+ 1178 => x"058c08d0",
+ 1179 => x"050c8c08",
+ 1180 => x"d8050890",
+ 1181 => x"2a8c08d0",
+ 1182 => x"0508118c",
+ 1183 => x"08e0050c",
+ 1184 => x"8c08d805",
+ 1185 => x"0883ffff",
+ 1186 => x"0670902b",
+ 1187 => x"8c08dc05",
+ 1188 => x"0883ffff",
+ 1189 => x"0670128c",
+ 1190 => x"08e4050c",
+ 1191 => x"52575154",
+ 1192 => x"8c08e005",
+ 1193 => x"088c08e4",
+ 1194 => x"05085654",
+ 1195 => x"738c08e8",
+ 1196 => x"050c748c",
+ 1197 => x"08ec050c",
+ 1198 => x"8c08fc05",
+ 1199 => x"088c08f0",
+ 1200 => x"0508298c",
+ 1201 => x"08f80508",
+ 1202 => x"8c08f405",
+ 1203 => x"08297012",
+ 1204 => x"8c08e805",
+ 1205 => x"08118c08",
+ 1206 => x"e8050c51",
+ 1207 => x"55558c08",
+ 1208 => x"e805088c",
+ 1209 => x"08ec0508",
+ 1210 => x"8c088805",
+ 1211 => x"08585654",
+ 1212 => x"73760c74",
+ 1213 => x"84170c8c",
+ 1214 => x"08880508",
+ 1215 => x"800c973d",
+ 1216 => x"0d8c0c04",
+ 1217 => x"8c08028c",
+ 1218 => x"0cf63d0d",
+ 1219 => x"800b8c08",
+ 1220 => x"f0050c80",
+ 1221 => x"0b8c08f4",
+ 1222 => x"050c8c08",
+ 1223 => x"8c05088c",
+ 1224 => x"08900508",
+ 1225 => x"5654738c",
+ 1226 => x"08f0050c",
+ 1227 => x"748c08f4",
+ 1228 => x"050c8c08",
+ 1229 => x"f8058c08",
+ 1230 => x"f0055656",
+ 1231 => x"88705475",
+ 1232 => x"53765254",
+ 1233 => x"b8833f80",
+ 1234 => x"0b8c08f0",
+ 1235 => x"050c800b",
+ 1236 => x"8c08f405",
+ 1237 => x"0c8c08f8",
+ 1238 => x"0508308c",
+ 1239 => x"08ec050c",
+ 1240 => x"8c08fc05",
+ 1241 => x"08802e8d",
+ 1242 => x"388c08ec",
+ 1243 => x"0508ff05",
+ 1244 => x"8c08ec05",
+ 1245 => x"0c8c08ec",
+ 1246 => x"05088c08",
+ 1247 => x"f0050c8c",
+ 1248 => x"08fc0508",
+ 1249 => x"308c08f4",
+ 1250 => x"050c8c08",
+ 1251 => x"f005088c",
+ 1252 => x"08f40508",
+ 1253 => x"8c088805",
+ 1254 => x"08585654",
+ 1255 => x"73760c74",
+ 1256 => x"84170c8c",
+ 1257 => x"08880508",
+ 1258 => x"800c8c3d",
+ 1259 => x"0d8c0c04",
+ 1260 => x"8c08028c",
+ 1261 => x"0cf53d0d",
+ 1262 => x"8c089405",
+ 1263 => x"089d388c",
+ 1264 => x"088c0508",
+ 1265 => x"8c089005",
+ 1266 => x"088c0888",
+ 1267 => x"05085856",
+ 1268 => x"5473760c",
+ 1269 => x"7484170c",
+ 1270 => x"81bf3980",
+ 1271 => x"0b8c08f0",
+ 1272 => x"050c800b",
+ 1273 => x"8c08f405",
+ 1274 => x"0c8c088c",
+ 1275 => x"05088c08",
+ 1276 => x"90050856",
+ 1277 => x"54738c08",
+ 1278 => x"f0050c74",
+ 1279 => x"8c08f405",
+ 1280 => x"0c8c08f8",
+ 1281 => x"058c08f0",
+ 1282 => x"05565688",
+ 1283 => x"70547553",
+ 1284 => x"765254b6",
+ 1285 => x"b43fa00b",
+ 1286 => x"8c089405",
+ 1287 => x"08318c08",
+ 1288 => x"ec050c8c",
+ 1289 => x"08ec0508",
+ 1290 => x"80249d38",
+ 1291 => x"800b8c08",
+ 1292 => x"f4050c8c",
+ 1293 => x"08ec0508",
+ 1294 => x"308c08fc",
+ 1295 => x"0508712b",
+ 1296 => x"8c08f005",
+ 1297 => x"0c54b939",
+ 1298 => x"8c08fc05",
+ 1299 => x"088c08ec",
+ 1300 => x"05082a8c",
+ 1301 => x"08e8050c",
+ 1302 => x"8c08fc05",
+ 1303 => x"088c0894",
+ 1304 => x"05082b8c",
+ 1305 => x"08f4050c",
+ 1306 => x"8c08f805",
+ 1307 => x"088c0894",
+ 1308 => x"05082b70",
+ 1309 => x"8c08e805",
+ 1310 => x"08078c08",
+ 1311 => x"f0050c54",
+ 1312 => x"8c08f005",
+ 1313 => x"088c08f4",
+ 1314 => x"05088c08",
+ 1315 => x"88050858",
+ 1316 => x"56547376",
+ 1317 => x"0c748417",
+ 1318 => x"0c8c0888",
+ 1319 => x"0508800c",
+ 1320 => x"8d3d0d8c",
+ 1321 => x"0c048c08",
+ 1322 => x"028c0ccc",
+ 1323 => x"3d0d800b",
+ 1324 => x"8c08fc05",
+ 1325 => x"0c800b8c",
+ 1326 => x"08ec050c",
+ 1327 => x"800b8c08",
+ 1328 => x"f0050c8c",
+ 1329 => x"088c0508",
+ 1330 => x"8c089005",
+ 1331 => x"08565473",
+ 1332 => x"8c08ec05",
+ 1333 => x"0c748c08",
+ 1334 => x"f0050c8c",
+ 1335 => x"08f4058c",
+ 1336 => x"08ec0556",
+ 1337 => x"56887054",
+ 1338 => x"75537652",
+ 1339 => x"54b4da3f",
+ 1340 => x"800b8c08",
+ 1341 => x"e4050c80",
+ 1342 => x"0b8c08e8",
+ 1343 => x"050c8c08",
+ 1344 => x"9405088c",
+ 1345 => x"08980508",
+ 1346 => x"5654738c",
+ 1347 => x"08e4050c",
+ 1348 => x"748c08e8",
+ 1349 => x"050c8c08",
+ 1350 => x"ec058c08",
+ 1351 => x"e4055656",
+ 1352 => x"88705475",
+ 1353 => x"53765254",
+ 1354 => x"b49f3f8c",
+ 1355 => x"08f40508",
+ 1356 => x"8025be38",
+ 1357 => x"8c08fc05",
+ 1358 => x"08098c08",
+ 1359 => x"fc050c8c",
+ 1360 => x"08d40554",
+ 1361 => x"8c08f405",
+ 1362 => x"088c08f8",
+ 1363 => x"05085755",
+ 1364 => x"74527553",
+ 1365 => x"7351fbac",
+ 1366 => x"3f8c08d4",
+ 1367 => x"05088c08",
+ 1368 => x"d8050856",
+ 1369 => x"54738c08",
+ 1370 => x"f4050c74",
+ 1371 => x"8c08f805",
+ 1372 => x"0c8c08ec",
+ 1373 => x"05088025",
+ 1374 => x"be388c08",
+ 1375 => x"fc050809",
+ 1376 => x"8c08fc05",
+ 1377 => x"0c8c08d4",
+ 1378 => x"05548c08",
+ 1379 => x"ec05088c",
+ 1380 => x"08f00508",
+ 1381 => x"57557452",
+ 1382 => x"75537351",
+ 1383 => x"fae63f8c",
+ 1384 => x"08d40508",
+ 1385 => x"8c08d805",
+ 1386 => x"08565473",
+ 1387 => x"8c08ec05",
+ 1388 => x"0c748c08",
+ 1389 => x"f0050c8c",
+ 1390 => x"08f40508",
+ 1391 => x"8c08f805",
+ 1392 => x"08565473",
+ 1393 => x"8c08d405",
+ 1394 => x"0c748c08",
+ 1395 => x"d8050c8c",
+ 1396 => x"08ec0508",
+ 1397 => x"8c08f005",
+ 1398 => x"08565473",
+ 1399 => x"8c08cc05",
+ 1400 => x"0c748c08",
+ 1401 => x"d0050c80",
+ 1402 => x"0b8c08c8",
+ 1403 => x"050c800b",
+ 1404 => x"8c08e405",
+ 1405 => x"0c800b8c",
+ 1406 => x"08e8050c",
+ 1407 => x"8c08d405",
+ 1408 => x"088c08d8",
+ 1409 => x"05085654",
+ 1410 => x"738c08e4",
+ 1411 => x"050c748c",
+ 1412 => x"08e8050c",
+ 1413 => x"800b8c08",
+ 1414 => x"ffb8050c",
+ 1415 => x"800b8c08",
+ 1416 => x"ffbc050c",
+ 1417 => x"8c08cc05",
+ 1418 => x"088c08d0",
+ 1419 => x"05085654",
+ 1420 => x"738c08ff",
+ 1421 => x"b8050c74",
+ 1422 => x"8c08ffbc",
+ 1423 => x"050c8c08",
+ 1424 => x"ffbc0508",
+ 1425 => x"8c08ffac",
+ 1426 => x"050c8c08",
+ 1427 => x"ffb80508",
+ 1428 => x"8c08ffa8",
+ 1429 => x"050c8c08",
+ 1430 => x"e805088c",
+ 1431 => x"08ffa405",
+ 1432 => x"0c8c08e4",
+ 1433 => x"05088c08",
+ 1434 => x"ffa0050c",
+ 1435 => x"8c08ffa8",
+ 1436 => x"050891d4",
+ 1437 => x"388c08ff",
+ 1438 => x"a005088c",
+ 1439 => x"08ffac05",
+ 1440 => x"0827868c",
+ 1441 => x"388c08ff",
+ 1442 => x"ac05088c",
+ 1443 => x"08ff8805",
+ 1444 => x"0c8c08ff",
+ 1445 => x"88050883",
+ 1446 => x"ffff26a0",
+ 1447 => x"388c08ff",
+ 1448 => x"88050881",
+ 1449 => x"ff268b38",
+ 1450 => x"800b8c08",
+ 1451 => x"fed8050c",
+ 1452 => x"a939880b",
+ 1453 => x"8c08fed8",
+ 1454 => x"050c9f39",
+ 1455 => x"8c08ff88",
+ 1456 => x"0508fe80",
+ 1457 => x"0a268b38",
+ 1458 => x"900b8c08",
+ 1459 => x"fed8050c",
+ 1460 => x"8939980b",
+ 1461 => x"8c08fed8",
+ 1462 => x"050c8c08",
+ 1463 => x"fed80508",
+ 1464 => x"8c08ff84",
+ 1465 => x"050c8c08",
+ 1466 => x"ff880508",
+ 1467 => x"8c08ff84",
+ 1468 => x"05082a80",
+ 1469 => x"f6c81133",
+ 1470 => x"8c08ff84",
+ 1471 => x"050811a0",
+ 1472 => x"71318c08",
+ 1473 => x"ff8c050c",
+ 1474 => x"5151548c",
+ 1475 => x"08ff8c05",
+ 1476 => x"08802e80",
+ 1477 => x"d1388c08",
+ 1478 => x"ffac0508",
+ 1479 => x"8c08ff8c",
+ 1480 => x"05082b8c",
+ 1481 => x"08ffac05",
+ 1482 => x"0c8c08ff",
+ 1483 => x"a005088c",
+ 1484 => x"08ff8c05",
+ 1485 => x"082ba00b",
+ 1486 => x"8c08ff8c",
+ 1487 => x"0508318c",
+ 1488 => x"08ffa405",
+ 1489 => x"08712a70",
+ 1490 => x"73078c08",
+ 1491 => x"ffa0050c",
+ 1492 => x"8c08ffa4",
+ 1493 => x"05088c08",
+ 1494 => x"ff8c0508",
+ 1495 => x"2b8c08ff",
+ 1496 => x"a4050c51",
+ 1497 => x"56548c08",
+ 1498 => x"ffac0508",
+ 1499 => x"902a8c08",
+ 1500 => x"ff84050c",
+ 1501 => x"8c08ffac",
+ 1502 => x"050883ff",
+ 1503 => x"ff068c08",
+ 1504 => x"ff88050c",
+ 1505 => x"8c08ffa0",
+ 1506 => x"05088c08",
+ 1507 => x"ff840508",
+ 1508 => x"53705254",
+ 1509 => x"9efb3f80",
+ 1510 => x"08708c08",
+ 1511 => x"fef8050c",
+ 1512 => x"8c08ff84",
+ 1513 => x"0508538c",
+ 1514 => x"08ffa005",
+ 1515 => x"0852549e",
+ 1516 => x"bb3f8008",
+ 1517 => x"708c08ff",
+ 1518 => x"80050c8c",
+ 1519 => x"08ff8005",
+ 1520 => x"088c08ff",
+ 1521 => x"88050829",
+ 1522 => x"708c08fe",
+ 1523 => x"f0050c8c",
+ 1524 => x"08fef805",
+ 1525 => x"0870902b",
+ 1526 => x"8c08ffa4",
+ 1527 => x"0508902a",
+ 1528 => x"7072078c",
+ 1529 => x"08fef805",
+ 1530 => x"0c525851",
+ 1531 => x"51548c08",
+ 1532 => x"fef80508",
+ 1533 => x"8c08fef0",
+ 1534 => x"05082780",
+ 1535 => x"e1388c08",
+ 1536 => x"ff800508",
+ 1537 => x"ff058c08",
+ 1538 => x"ff80050c",
+ 1539 => x"8c08fef8",
+ 1540 => x"05088c08",
+ 1541 => x"ffac0508",
+ 1542 => x"058c08fe",
+ 1543 => x"f8050c8c",
+ 1544 => x"08ffac05",
+ 1545 => x"088c08fe",
+ 1546 => x"f8050826",
+ 1547 => x"b1388c08",
+ 1548 => x"fef80508",
+ 1549 => x"8c08fef0",
+ 1550 => x"050827a2",
+ 1551 => x"388c08ff",
+ 1552 => x"800508ff",
+ 1553 => x"058c08ff",
+ 1554 => x"80050c8c",
+ 1555 => x"08fef805",
+ 1556 => x"088c08ff",
+ 1557 => x"ac050805",
+ 1558 => x"8c08fef8",
+ 1559 => x"050c8c08",
+ 1560 => x"fef80508",
+ 1561 => x"8c08fef0",
+ 1562 => x"0508318c",
+ 1563 => x"08fef805",
+ 1564 => x"0c8c08fe",
+ 1565 => x"f805088c",
+ 1566 => x"08ff8405",
+ 1567 => x"08537052",
+ 1568 => x"549d8e3f",
+ 1569 => x"8008708c",
+ 1570 => x"08fef405",
+ 1571 => x"0c8c08ff",
+ 1572 => x"84050853",
+ 1573 => x"8c08fef8",
+ 1574 => x"05085254",
+ 1575 => x"9cce3f80",
+ 1576 => x"08708c08",
+ 1577 => x"fefc050c",
+ 1578 => x"8c08fefc",
+ 1579 => x"05088c08",
+ 1580 => x"ff880508",
+ 1581 => x"29708c08",
+ 1582 => x"fef0050c",
+ 1583 => x"8c08fef4",
+ 1584 => x"05087090",
+ 1585 => x"2b8c08ff",
+ 1586 => x"a4050883",
+ 1587 => x"ffff0670",
+ 1588 => x"72078c08",
+ 1589 => x"fef4050c",
+ 1590 => x"52585151",
+ 1591 => x"548c08fe",
+ 1592 => x"f405088c",
+ 1593 => x"08fef005",
+ 1594 => x"082780e1",
+ 1595 => x"388c08fe",
+ 1596 => x"fc0508ff",
+ 1597 => x"058c08fe",
+ 1598 => x"fc050c8c",
+ 1599 => x"08fef405",
+ 1600 => x"088c08ff",
+ 1601 => x"ac050805",
+ 1602 => x"8c08fef4",
+ 1603 => x"050c8c08",
+ 1604 => x"ffac0508",
+ 1605 => x"8c08fef4",
+ 1606 => x"050826b1",
+ 1607 => x"388c08fe",
+ 1608 => x"f405088c",
+ 1609 => x"08fef005",
+ 1610 => x"0827a238",
+ 1611 => x"8c08fefc",
+ 1612 => x"0508ff05",
+ 1613 => x"8c08fefc",
+ 1614 => x"050c8c08",
+ 1615 => x"fef40508",
+ 1616 => x"8c08ffac",
+ 1617 => x"0508058c",
+ 1618 => x"08fef405",
+ 1619 => x"0c8c08fe",
+ 1620 => x"f405088c",
+ 1621 => x"08fef005",
+ 1622 => x"08318c08",
+ 1623 => x"fef4050c",
+ 1624 => x"8c08ff80",
+ 1625 => x"05087090",
+ 1626 => x"2b708c08",
+ 1627 => x"fefc0508",
+ 1628 => x"078c08ff",
+ 1629 => x"98050c8c",
+ 1630 => x"08fef405",
+ 1631 => x"088c08ff",
+ 1632 => x"a4050c51",
+ 1633 => x"54800b8c",
+ 1634 => x"08ff9405",
+ 1635 => x"0c8af639",
+ 1636 => x"8c08ffac",
+ 1637 => x"05089738",
+ 1638 => x"8c08ffac",
+ 1639 => x"05085281",
+ 1640 => x"519ac93f",
+ 1641 => x"8008708c",
+ 1642 => x"08ffac05",
+ 1643 => x"0c548c08",
+ 1644 => x"ffac0508",
+ 1645 => x"8c08fef0",
+ 1646 => x"050c8c08",
+ 1647 => x"fef00508",
+ 1648 => x"83ffff26",
+ 1649 => x"a0388c08",
+ 1650 => x"fef00508",
+ 1651 => x"81ff268b",
+ 1652 => x"38800b8c",
+ 1653 => x"08fed405",
+ 1654 => x"0ca93988",
+ 1655 => x"0b8c08fe",
+ 1656 => x"d4050c9f",
+ 1657 => x"398c08fe",
+ 1658 => x"f00508fe",
+ 1659 => x"800a268b",
+ 1660 => x"38900b8c",
+ 1661 => x"08fed405",
+ 1662 => x"0c893998",
+ 1663 => x"0b8c08fe",
+ 1664 => x"d4050c8c",
+ 1665 => x"08fed405",
+ 1666 => x"088c08fe",
+ 1667 => x"f4050c8c",
+ 1668 => x"08fef005",
+ 1669 => x"088c08fe",
+ 1670 => x"f405082a",
+ 1671 => x"80f6c811",
+ 1672 => x"338c08fe",
+ 1673 => x"f4050811",
+ 1674 => x"a071318c",
+ 1675 => x"08ff8c05",
+ 1676 => x"0c515154",
+ 1677 => x"8c08ff8c",
+ 1678 => x"05089f38",
+ 1679 => x"8c08ffa0",
+ 1680 => x"05088c08",
+ 1681 => x"ffac0508",
+ 1682 => x"318c08ff",
+ 1683 => x"a0050c81",
+ 1684 => x"0b8c08ff",
+ 1685 => x"94050c85",
+ 1686 => x"8d39a00b",
+ 1687 => x"8c08ff8c",
+ 1688 => x"0508318c",
+ 1689 => x"08ff9005",
+ 1690 => x"0c8c08ff",
+ 1691 => x"ac05088c",
+ 1692 => x"08ff8c05",
+ 1693 => x"082b8c08",
+ 1694 => x"ffac050c",
+ 1695 => x"8c08ffa0",
+ 1696 => x"05088c08",
+ 1697 => x"ff900508",
+ 1698 => x"2a8c08ff",
+ 1699 => x"9c050c8c",
+ 1700 => x"08ffa005",
+ 1701 => x"088c08ff",
+ 1702 => x"8c05082b",
+ 1703 => x"8c08ffa4",
+ 1704 => x"05088c08",
+ 1705 => x"ff900508",
+ 1706 => x"2a707207",
+ 1707 => x"8c08ffa0",
+ 1708 => x"050c8c08",
+ 1709 => x"ffa40508",
+ 1710 => x"8c08ff8c",
+ 1711 => x"05082b8c",
+ 1712 => x"08ffa405",
+ 1713 => x"0c8c08ff",
+ 1714 => x"ac050890",
+ 1715 => x"2a8c08fe",
+ 1716 => x"f0050c8c",
+ 1717 => x"08ffac05",
+ 1718 => x"0883ffff",
+ 1719 => x"068c08fe",
+ 1720 => x"f4050c8c",
+ 1721 => x"08ff9c05",
+ 1722 => x"088c08fe",
+ 1723 => x"f0050855",
+ 1724 => x"70545155",
+ 1725 => x"55989a3f",
+ 1726 => x"8008708c",
+ 1727 => x"08ff8005",
+ 1728 => x"0c8c08fe",
+ 1729 => x"f0050853",
+ 1730 => x"8c08ff9c",
+ 1731 => x"05085254",
+ 1732 => x"97da3f80",
+ 1733 => x"08708c08",
+ 1734 => x"fef8050c",
+ 1735 => x"8c08fef8",
+ 1736 => x"05088c08",
+ 1737 => x"fef40508",
+ 1738 => x"29708c08",
+ 1739 => x"ff88050c",
+ 1740 => x"8c08ff80",
+ 1741 => x"05087090",
+ 1742 => x"2b8c08ff",
+ 1743 => x"a0050890",
+ 1744 => x"2a707207",
+ 1745 => x"8c08ff80",
+ 1746 => x"050c5258",
+ 1747 => x"5151548c",
+ 1748 => x"08ff8005",
+ 1749 => x"088c08ff",
+ 1750 => x"88050827",
+ 1751 => x"80e1388c",
+ 1752 => x"08fef805",
+ 1753 => x"08ff058c",
+ 1754 => x"08fef805",
+ 1755 => x"0c8c08ff",
+ 1756 => x"8005088c",
+ 1757 => x"08ffac05",
+ 1758 => x"08058c08",
+ 1759 => x"ff80050c",
+ 1760 => x"8c08ffac",
+ 1761 => x"05088c08",
+ 1762 => x"ff800508",
+ 1763 => x"26b1388c",
+ 1764 => x"08ff8005",
+ 1765 => x"088c08ff",
+ 1766 => x"88050827",
+ 1767 => x"a2388c08",
+ 1768 => x"fef80508",
+ 1769 => x"ff058c08",
+ 1770 => x"fef8050c",
+ 1771 => x"8c08ff80",
+ 1772 => x"05088c08",
+ 1773 => x"ffac0508",
+ 1774 => x"058c08ff",
+ 1775 => x"80050c8c",
+ 1776 => x"08ff8005",
+ 1777 => x"088c08ff",
+ 1778 => x"88050831",
+ 1779 => x"8c08ff80",
+ 1780 => x"050c8c08",
+ 1781 => x"ff800508",
+ 1782 => x"8c08fef0",
+ 1783 => x"05085370",
+ 1784 => x"525496ad",
+ 1785 => x"3f800870",
+ 1786 => x"8c08ff84",
+ 1787 => x"050c8c08",
+ 1788 => x"fef00508",
+ 1789 => x"538c08ff",
+ 1790 => x"80050852",
+ 1791 => x"5495ed3f",
+ 1792 => x"8008708c",
+ 1793 => x"08fefc05",
+ 1794 => x"0c8c08fe",
+ 1795 => x"fc05088c",
+ 1796 => x"08fef405",
+ 1797 => x"0829708c",
+ 1798 => x"08ff8805",
+ 1799 => x"0c8c08ff",
+ 1800 => x"84050870",
+ 1801 => x"902b8c08",
+ 1802 => x"ffa00508",
+ 1803 => x"83ffff06",
+ 1804 => x"7072078c",
+ 1805 => x"08ff8405",
+ 1806 => x"0c525851",
+ 1807 => x"51548c08",
+ 1808 => x"ff840508",
+ 1809 => x"8c08ff88",
+ 1810 => x"05082780",
+ 1811 => x"e1388c08",
+ 1812 => x"fefc0508",
+ 1813 => x"ff058c08",
+ 1814 => x"fefc050c",
+ 1815 => x"8c08ff84",
+ 1816 => x"05088c08",
+ 1817 => x"ffac0508",
+ 1818 => x"058c08ff",
+ 1819 => x"84050c8c",
+ 1820 => x"08ffac05",
+ 1821 => x"088c08ff",
+ 1822 => x"84050826",
+ 1823 => x"b1388c08",
+ 1824 => x"ff840508",
+ 1825 => x"8c08ff88",
+ 1826 => x"050827a2",
+ 1827 => x"388c08fe",
+ 1828 => x"fc0508ff",
+ 1829 => x"058c08fe",
+ 1830 => x"fc050c8c",
+ 1831 => x"08ff8405",
+ 1832 => x"088c08ff",
+ 1833 => x"ac050805",
+ 1834 => x"8c08ff84",
+ 1835 => x"050c8c08",
+ 1836 => x"ff840508",
+ 1837 => x"8c08ff88",
+ 1838 => x"0508318c",
+ 1839 => x"08ff8405",
+ 1840 => x"0c8c08fe",
+ 1841 => x"f8050870",
+ 1842 => x"902b708c",
+ 1843 => x"08fefc05",
+ 1844 => x"08078c08",
+ 1845 => x"ff94050c",
+ 1846 => x"8c08ff84",
+ 1847 => x"05088c08",
+ 1848 => x"ffa0050c",
+ 1849 => x"51548c08",
+ 1850 => x"ffac0508",
+ 1851 => x"902a8c08",
+ 1852 => x"fef0050c",
+ 1853 => x"8c08ffac",
+ 1854 => x"050883ff",
+ 1855 => x"ff068c08",
+ 1856 => x"fef4050c",
+ 1857 => x"8c08ffa0",
+ 1858 => x"05088c08",
+ 1859 => x"fef00508",
+ 1860 => x"53705254",
+ 1861 => x"93fb3f80",
+ 1862 => x"08708c08",
+ 1863 => x"ff80050c",
+ 1864 => x"8c08fef0",
+ 1865 => x"0508538c",
+ 1866 => x"08ffa005",
+ 1867 => x"08525493",
+ 1868 => x"bb3f8008",
+ 1869 => x"708c08fe",
+ 1870 => x"f8050c8c",
+ 1871 => x"08fef805",
+ 1872 => x"088c08fe",
+ 1873 => x"f4050829",
+ 1874 => x"708c08ff",
+ 1875 => x"88050c8c",
+ 1876 => x"08ff8005",
+ 1877 => x"0870902b",
+ 1878 => x"8c08ffa4",
+ 1879 => x"0508902a",
+ 1880 => x"7072078c",
+ 1881 => x"08ff8005",
+ 1882 => x"0c525851",
+ 1883 => x"51548c08",
+ 1884 => x"ff800508",
+ 1885 => x"8c08ff88",
+ 1886 => x"05082780",
+ 1887 => x"e1388c08",
+ 1888 => x"fef80508",
+ 1889 => x"ff058c08",
+ 1890 => x"fef8050c",
+ 1891 => x"8c08ff80",
+ 1892 => x"05088c08",
+ 1893 => x"ffac0508",
+ 1894 => x"058c08ff",
+ 1895 => x"80050c8c",
+ 1896 => x"08ffac05",
+ 1897 => x"088c08ff",
+ 1898 => x"80050826",
+ 1899 => x"b1388c08",
+ 1900 => x"ff800508",
+ 1901 => x"8c08ff88",
+ 1902 => x"050827a2",
+ 1903 => x"388c08fe",
+ 1904 => x"f80508ff",
+ 1905 => x"058c08fe",
+ 1906 => x"f8050c8c",
+ 1907 => x"08ff8005",
+ 1908 => x"088c08ff",
+ 1909 => x"ac050805",
+ 1910 => x"8c08ff80",
+ 1911 => x"050c8c08",
+ 1912 => x"ff800508",
+ 1913 => x"8c08ff88",
+ 1914 => x"0508318c",
+ 1915 => x"08ff8005",
+ 1916 => x"0c8c08ff",
+ 1917 => x"8005088c",
+ 1918 => x"08fef005",
+ 1919 => x"08537052",
+ 1920 => x"54928e3f",
+ 1921 => x"8008708c",
+ 1922 => x"08ff8405",
+ 1923 => x"0c8c08fe",
+ 1924 => x"f0050853",
+ 1925 => x"8c08ff80",
+ 1926 => x"05085254",
+ 1927 => x"91ce3f80",
+ 1928 => x"08708c08",
+ 1929 => x"fefc050c",
+ 1930 => x"8c08fefc",
+ 1931 => x"05088c08",
+ 1932 => x"fef40508",
+ 1933 => x"29708c08",
+ 1934 => x"ff88050c",
+ 1935 => x"8c08ff84",
+ 1936 => x"05087090",
+ 1937 => x"2b8c08ff",
+ 1938 => x"a4050883",
+ 1939 => x"ffff0670",
+ 1940 => x"72078c08",
+ 1941 => x"ff84050c",
+ 1942 => x"52585151",
+ 1943 => x"548c08ff",
+ 1944 => x"8405088c",
+ 1945 => x"08ff8805",
+ 1946 => x"082780e1",
+ 1947 => x"388c08fe",
+ 1948 => x"fc0508ff",
+ 1949 => x"058c08fe",
+ 1950 => x"fc050c8c",
+ 1951 => x"08ff8405",
+ 1952 => x"088c08ff",
+ 1953 => x"ac050805",
+ 1954 => x"8c08ff84",
+ 1955 => x"050c8c08",
+ 1956 => x"ffac0508",
+ 1957 => x"8c08ff84",
+ 1958 => x"050826b1",
+ 1959 => x"388c08ff",
+ 1960 => x"8405088c",
+ 1961 => x"08ff8805",
+ 1962 => x"0827a238",
+ 1963 => x"8c08fefc",
+ 1964 => x"0508ff05",
+ 1965 => x"8c08fefc",
+ 1966 => x"050c8c08",
+ 1967 => x"ff840508",
+ 1968 => x"8c08ffac",
+ 1969 => x"0508058c",
+ 1970 => x"08ff8405",
+ 1971 => x"0c8c08ff",
+ 1972 => x"8405088c",
+ 1973 => x"08ff8805",
+ 1974 => x"08318c08",
+ 1975 => x"ff84050c",
+ 1976 => x"8c08fef8",
+ 1977 => x"05087090",
+ 1978 => x"2b708c08",
+ 1979 => x"fefc0508",
+ 1980 => x"078c08ff",
+ 1981 => x"98050c8c",
+ 1982 => x"08ff8405",
+ 1983 => x"088c08ff",
+ 1984 => x"a4050c51",
+ 1985 => x"548c08c8",
+ 1986 => x"0508802e",
+ 1987 => x"8ea3388c",
+ 1988 => x"08ffa405",
+ 1989 => x"088c08ff",
+ 1990 => x"8c05082a",
+ 1991 => x"8c08ffb4",
+ 1992 => x"050c800b",
+ 1993 => x"8c08ffb0",
+ 1994 => x"050c8c08",
+ 1995 => x"c8050856",
+ 1996 => x"8c08ffb0",
+ 1997 => x"05088c08",
+ 1998 => x"ffb40508",
+ 1999 => x"56547376",
+ 2000 => x"0c748417",
+ 2001 => x"0c8dea39",
+ 2002 => x"8c08ffa0",
+ 2003 => x"05088c08",
+ 2004 => x"ffa80508",
+ 2005 => x"2780d138",
+ 2006 => x"800b8c08",
+ 2007 => x"ff98050c",
+ 2008 => x"800b8c08",
+ 2009 => x"ff94050c",
+ 2010 => x"8c08c805",
+ 2011 => x"08802e8d",
+ 2012 => x"c0388c08",
+ 2013 => x"ffa40508",
+ 2014 => x"8c08ffb4",
+ 2015 => x"050c8c08",
+ 2016 => x"ffa00508",
+ 2017 => x"8c08ffb0",
+ 2018 => x"050c8c08",
+ 2019 => x"c8050856",
+ 2020 => x"8c08ffb0",
+ 2021 => x"05088c08",
+ 2022 => x"ffb40508",
+ 2023 => x"56547376",
+ 2024 => x"0c748417",
+ 2025 => x"0c8d8a39",
+ 2026 => x"8c08ffa8",
+ 2027 => x"05088c08",
+ 2028 => x"fef0050c",
+ 2029 => x"8c08fef0",
+ 2030 => x"050883ff",
+ 2031 => x"ff26a038",
+ 2032 => x"8c08fef0",
+ 2033 => x"050881ff",
+ 2034 => x"268b3880",
+ 2035 => x"0b8c08fe",
+ 2036 => x"d0050ca9",
+ 2037 => x"39880b8c",
+ 2038 => x"08fed005",
+ 2039 => x"0c9f398c",
+ 2040 => x"08fef005",
+ 2041 => x"08fe800a",
+ 2042 => x"268b3890",
+ 2043 => x"0b8c08fe",
+ 2044 => x"d0050c89",
+ 2045 => x"39980b8c",
+ 2046 => x"08fed005",
+ 2047 => x"0c8c08fe",
+ 2048 => x"d005088c",
+ 2049 => x"08fef405",
+ 2050 => x"0c8c08fe",
+ 2051 => x"f005088c",
+ 2052 => x"08fef405",
+ 2053 => x"082a80f6",
+ 2054 => x"c811338c",
+ 2055 => x"08fef405",
+ 2056 => x"0811a071",
+ 2057 => x"318c08ff",
+ 2058 => x"8c050c51",
+ 2059 => x"51548c08",
+ 2060 => x"ff8c0508",
+ 2061 => x"81d9388c",
+ 2062 => x"08ffa005",
+ 2063 => x"088c08ff",
+ 2064 => x"a8050826",
+ 2065 => x"93388c08",
+ 2066 => x"ffa40508",
+ 2067 => x"8c08ffac",
+ 2068 => x"05082784",
+ 2069 => x"3880e839",
+ 2070 => x"810b8c08",
+ 2071 => x"ff98050c",
+ 2072 => x"8c08ffa4",
+ 2073 => x"05088c08",
+ 2074 => x"ffac0508",
+ 2075 => x"318c08fe",
+ 2076 => x"f0050c8c",
+ 2077 => x"08ffa005",
+ 2078 => x"088c08ff",
+ 2079 => x"a8050831",
+ 2080 => x"708c08fe",
+ 2081 => x"cc050c54",
+ 2082 => x"8c08ffa4",
+ 2083 => x"05088c08",
+ 2084 => x"fef00508",
+ 2085 => x"278f388c",
+ 2086 => x"08fecc05",
+ 2087 => x"08ff058c",
+ 2088 => x"08fecc05",
+ 2089 => x"0c8c08fe",
+ 2090 => x"cc05088c",
+ 2091 => x"08ffa005",
+ 2092 => x"0c8c08fe",
+ 2093 => x"f005088c",
+ 2094 => x"08ffa405",
+ 2095 => x"0c893980",
+ 2096 => x"0b8c08ff",
+ 2097 => x"98050c80",
+ 2098 => x"0b8c08ff",
+ 2099 => x"94050c8c",
+ 2100 => x"08c80508",
+ 2101 => x"802e8ad9",
+ 2102 => x"388c08ff",
+ 2103 => x"a405088c",
+ 2104 => x"08ffb405",
+ 2105 => x"0c8c08ff",
+ 2106 => x"a005088c",
+ 2107 => x"08ffb005",
+ 2108 => x"0c8c08c8",
+ 2109 => x"0508568c",
+ 2110 => x"08ffb005",
+ 2111 => x"088c08ff",
+ 2112 => x"b4050856",
+ 2113 => x"5473760c",
+ 2114 => x"7484170c",
+ 2115 => x"8aa339a0",
+ 2116 => x"0b8c08ff",
+ 2117 => x"8c050831",
+ 2118 => x"8c08ff90",
+ 2119 => x"050c8c08",
+ 2120 => x"ffa80508",
+ 2121 => x"8c08ff8c",
+ 2122 => x"05082b8c",
+ 2123 => x"08ffac05",
+ 2124 => x"088c08ff",
+ 2125 => x"9005082a",
+ 2126 => x"7072078c",
+ 2127 => x"08ffa805",
+ 2128 => x"0c8c08ff",
+ 2129 => x"ac05088c",
+ 2130 => x"08ff8c05",
+ 2131 => x"082b8c08",
+ 2132 => x"ffac050c",
+ 2133 => x"8c08ffa0",
+ 2134 => x"05088c08",
+ 2135 => x"ff900508",
+ 2136 => x"2a8c08ff",
+ 2137 => x"9c050c8c",
+ 2138 => x"08ffa005",
+ 2139 => x"088c08ff",
+ 2140 => x"8c05082b",
+ 2141 => x"8c08ffa4",
+ 2142 => x"05088c08",
+ 2143 => x"ff900508",
+ 2144 => x"2a707207",
+ 2145 => x"8c08ffa0",
+ 2146 => x"050c8c08",
+ 2147 => x"ffa40508",
+ 2148 => x"8c08ff8c",
+ 2149 => x"05082b8c",
+ 2150 => x"08ffa405",
+ 2151 => x"0c8c08ff",
+ 2152 => x"a8050890",
+ 2153 => x"2a8c08fe",
+ 2154 => x"f8050c8c",
+ 2155 => x"08ffa805",
+ 2156 => x"0883ffff",
+ 2157 => x"068c08fe",
+ 2158 => x"fc050c8c",
+ 2159 => x"08ff9c05",
+ 2160 => x"088c08fe",
+ 2161 => x"f8050857",
+ 2162 => x"70565152",
+ 2163 => x"5255558a",
+ 2164 => x"c03f8008",
+ 2165 => x"708c08ff",
+ 2166 => x"88050c8c",
+ 2167 => x"08fef805",
+ 2168 => x"08538c08",
+ 2169 => x"ff9c0508",
+ 2170 => x"52548a80",
+ 2171 => x"3f800870",
+ 2172 => x"8c08ff80",
+ 2173 => x"050c8c08",
+ 2174 => x"ff800508",
+ 2175 => x"8c08fefc",
+ 2176 => x"05082970",
+ 2177 => x"8c08fee8",
+ 2178 => x"050c8c08",
+ 2179 => x"ff880508",
+ 2180 => x"70902b8c",
+ 2181 => x"08ffa005",
+ 2182 => x"08902a70",
+ 2183 => x"72078c08",
+ 2184 => x"ff88050c",
+ 2185 => x"52585151",
+ 2186 => x"548c08ff",
+ 2187 => x"8805088c",
+ 2188 => x"08fee805",
+ 2189 => x"082780e1",
+ 2190 => x"388c08ff",
+ 2191 => x"800508ff",
+ 2192 => x"058c08ff",
+ 2193 => x"80050c8c",
+ 2194 => x"08ff8805",
+ 2195 => x"088c08ff",
+ 2196 => x"a8050805",
+ 2197 => x"8c08ff88",
+ 2198 => x"050c8c08",
+ 2199 => x"ffa80508",
+ 2200 => x"8c08ff88",
+ 2201 => x"050826b1",
+ 2202 => x"388c08ff",
+ 2203 => x"8805088c",
+ 2204 => x"08fee805",
+ 2205 => x"0827a238",
+ 2206 => x"8c08ff80",
+ 2207 => x"0508ff05",
+ 2208 => x"8c08ff80",
+ 2209 => x"050c8c08",
+ 2210 => x"ff880508",
+ 2211 => x"8c08ffa8",
+ 2212 => x"0508058c",
+ 2213 => x"08ff8805",
+ 2214 => x"0c8c08ff",
+ 2215 => x"8805088c",
+ 2216 => x"08fee805",
+ 2217 => x"08318c08",
+ 2218 => x"ff88050c",
+ 2219 => x"8c08ff88",
+ 2220 => x"05088c08",
+ 2221 => x"fef80508",
+ 2222 => x"53705254",
+ 2223 => x"88d33f80",
+ 2224 => x"08708c08",
+ 2225 => x"feec050c",
+ 2226 => x"8c08fef8",
+ 2227 => x"0508538c",
+ 2228 => x"08ff8805",
+ 2229 => x"08525488",
+ 2230 => x"933f8008",
+ 2231 => x"708c08ff",
+ 2232 => x"84050c8c",
+ 2233 => x"08ff8405",
+ 2234 => x"088c08fe",
+ 2235 => x"fc050829",
+ 2236 => x"708c08fe",
+ 2237 => x"e8050c8c",
+ 2238 => x"08feec05",
+ 2239 => x"0870902b",
+ 2240 => x"8c08ffa0",
+ 2241 => x"050883ff",
+ 2242 => x"ff067072",
+ 2243 => x"078c08fe",
+ 2244 => x"ec050c52",
+ 2245 => x"58515154",
+ 2246 => x"8c08feec",
+ 2247 => x"05088c08",
+ 2248 => x"fee80508",
+ 2249 => x"2780e138",
+ 2250 => x"8c08ff84",
+ 2251 => x"0508ff05",
+ 2252 => x"8c08ff84",
+ 2253 => x"050c8c08",
+ 2254 => x"feec0508",
+ 2255 => x"8c08ffa8",
+ 2256 => x"0508058c",
+ 2257 => x"08feec05",
+ 2258 => x"0c8c08ff",
+ 2259 => x"a805088c",
+ 2260 => x"08feec05",
+ 2261 => x"0826b138",
+ 2262 => x"8c08feec",
+ 2263 => x"05088c08",
+ 2264 => x"fee80508",
+ 2265 => x"27a2388c",
+ 2266 => x"08ff8405",
+ 2267 => x"08ff058c",
+ 2268 => x"08ff8405",
+ 2269 => x"0c8c08fe",
+ 2270 => x"ec05088c",
+ 2271 => x"08ffa805",
+ 2272 => x"08058c08",
+ 2273 => x"feec050c",
+ 2274 => x"8c08feec",
+ 2275 => x"05088c08",
+ 2276 => x"fee80508",
+ 2277 => x"318c08fe",
+ 2278 => x"ec050c8c",
+ 2279 => x"08ff8005",
+ 2280 => x"0870902b",
+ 2281 => x"708c08ff",
+ 2282 => x"84050807",
+ 2283 => x"8c08ff98",
+ 2284 => x"050c8c08",
+ 2285 => x"feec0508",
+ 2286 => x"8c08ffa0",
+ 2287 => x"050c8c08",
+ 2288 => x"ff980508",
+ 2289 => x"83ffff06",
+ 2290 => x"8c08ff80",
+ 2291 => x"050c8c08",
+ 2292 => x"ff980508",
+ 2293 => x"902a8c08",
+ 2294 => x"ff88050c",
+ 2295 => x"8c08ffac",
+ 2296 => x"050883ff",
+ 2297 => x"ff068c08",
+ 2298 => x"ff84050c",
+ 2299 => x"8c08ffac",
+ 2300 => x"0508902a",
+ 2301 => x"8c08fee4",
+ 2302 => x"050c8c08",
+ 2303 => x"ff800508",
+ 2304 => x"8c08ff84",
+ 2305 => x"05082970",
+ 2306 => x"8c08fee8",
+ 2307 => x"050c8c08",
+ 2308 => x"ff800508",
+ 2309 => x"8c08fee4",
+ 2310 => x"05082970",
+ 2311 => x"8c08feec",
+ 2312 => x"050c8c08",
+ 2313 => x"ff880508",
+ 2314 => x"8c08ff84",
+ 2315 => x"05082970",
+ 2316 => x"8c08fef8",
+ 2317 => x"050c8c08",
+ 2318 => x"ff880508",
+ 2319 => x"8c08fee4",
+ 2320 => x"05082970",
+ 2321 => x"8c08fefc",
+ 2322 => x"050c8c08",
+ 2323 => x"fee80508",
+ 2324 => x"902a8c08",
+ 2325 => x"feec0508",
+ 2326 => x"118c08fe",
+ 2327 => x"ec050c8c",
+ 2328 => x"08feec05",
+ 2329 => x"088c08fe",
+ 2330 => x"f8050805",
+ 2331 => x"8c08feec",
+ 2332 => x"050c5151",
+ 2333 => x"51515151",
+ 2334 => x"548c08fe",
+ 2335 => x"ec05088c",
+ 2336 => x"08fef805",
+ 2337 => x"08279138",
+ 2338 => x"8c08fefc",
+ 2339 => x"05088480",
+ 2340 => x"80058c08",
+ 2341 => x"fefc050c",
+ 2342 => x"8c08feec",
+ 2343 => x"0508902a",
+ 2344 => x"8c08fefc",
+ 2345 => x"0508118c",
+ 2346 => x"08fef005",
+ 2347 => x"0c8c08fe",
+ 2348 => x"ec050883",
+ 2349 => x"ffff0670",
+ 2350 => x"902b8c08",
+ 2351 => x"fee80508",
+ 2352 => x"83ffff06",
+ 2353 => x"70128c08",
+ 2354 => x"fef4050c",
+ 2355 => x"52575154",
+ 2356 => x"8c08fef0",
+ 2357 => x"05088c08",
+ 2358 => x"ffa00508",
+ 2359 => x"26a6388c",
+ 2360 => x"08fef005",
+ 2361 => x"088c08ff",
+ 2362 => x"a005082e",
+ 2363 => x"09810680",
+ 2364 => x"fe388c08",
+ 2365 => x"fef40508",
+ 2366 => x"8c08ffa4",
+ 2367 => x"05082684",
+ 2368 => x"3880ec39",
+ 2369 => x"8c08ff98",
+ 2370 => x"0508ff05",
+ 2371 => x"8c08ff98",
+ 2372 => x"050c8c08",
+ 2373 => x"fef40508",
+ 2374 => x"8c08ffac",
+ 2375 => x"0508318c",
+ 2376 => x"08fee405",
+ 2377 => x"0c8c08fe",
+ 2378 => x"f005088c",
+ 2379 => x"08ffa805",
+ 2380 => x"0831708c",
+ 2381 => x"08fec805",
+ 2382 => x"0c548c08",
+ 2383 => x"fef40508",
+ 2384 => x"8c08fee4",
+ 2385 => x"0508278f",
+ 2386 => x"388c08fe",
+ 2387 => x"c80508ff",
+ 2388 => x"058c08fe",
+ 2389 => x"c8050c8c",
+ 2390 => x"08fec805",
+ 2391 => x"088c08fe",
+ 2392 => x"f0050c8c",
+ 2393 => x"08fee405",
+ 2394 => x"088c08fe",
+ 2395 => x"f4050c80",
+ 2396 => x"0b8c08ff",
+ 2397 => x"94050c8c",
+ 2398 => x"08c80508",
+ 2399 => x"802e81b1",
+ 2400 => x"388c08ff",
+ 2401 => x"a405088c",
+ 2402 => x"08fef405",
+ 2403 => x"08318c08",
+ 2404 => x"fee4050c",
+ 2405 => x"8c08ffa0",
+ 2406 => x"05088c08",
+ 2407 => x"fef00508",
+ 2408 => x"31708c08",
+ 2409 => x"fec4050c",
+ 2410 => x"548c08ff",
+ 2411 => x"a405088c",
+ 2412 => x"08fee405",
+ 2413 => x"08278f38",
+ 2414 => x"8c08fec4",
+ 2415 => x"0508ff05",
+ 2416 => x"8c08fec4",
+ 2417 => x"050c8c08",
+ 2418 => x"fec40508",
+ 2419 => x"8c08ffa0",
+ 2420 => x"050c8c08",
+ 2421 => x"fee40508",
+ 2422 => x"8c08ffa4",
+ 2423 => x"050c8c08",
+ 2424 => x"ffa00508",
+ 2425 => x"8c08ff90",
+ 2426 => x"05082b8c",
+ 2427 => x"08ffa405",
+ 2428 => x"088c08ff",
+ 2429 => x"8c05082a",
+ 2430 => x"7072078c",
+ 2431 => x"08ffb405",
+ 2432 => x"0c8c08ff",
+ 2433 => x"a005088c",
+ 2434 => x"08ff8c05",
+ 2435 => x"082a8c08",
+ 2436 => x"ffb0050c",
+ 2437 => x"8c08c805",
+ 2438 => x"08585555",
+ 2439 => x"8c08ffb0",
+ 2440 => x"05088c08",
+ 2441 => x"ffb40508",
+ 2442 => x"56547376",
+ 2443 => x"0c748417",
+ 2444 => x"0c800b8c",
+ 2445 => x"08fedc05",
+ 2446 => x"0c800b8c",
+ 2447 => x"08fee005",
+ 2448 => x"0c8c08ff",
+ 2449 => x"9405088c",
+ 2450 => x"08fedc05",
+ 2451 => x"0c8c08ff",
+ 2452 => x"9805088c",
+ 2453 => x"08fee005",
+ 2454 => x"0c8c08fe",
+ 2455 => x"dc05088c",
+ 2456 => x"08fee005",
+ 2457 => x"08565473",
+ 2458 => x"8c08c005",
+ 2459 => x"0c748c08",
+ 2460 => x"c4050c8c",
+ 2461 => x"08c00508",
+ 2462 => x"8c08c405",
+ 2463 => x"08565473",
+ 2464 => x"8c08dc05",
+ 2465 => x"0c748c08",
+ 2466 => x"e0050c8c",
+ 2467 => x"08fc0508",
+ 2468 => x"802eb338",
+ 2469 => x"8c08c005",
+ 2470 => x"548c08dc",
+ 2471 => x"05088c08",
+ 2472 => x"e0050857",
+ 2473 => x"55745275",
+ 2474 => x"537351d8",
+ 2475 => x"d73f8c08",
+ 2476 => x"c005088c",
+ 2477 => x"08c40508",
+ 2478 => x"5654738c",
+ 2479 => x"08dc050c",
+ 2480 => x"748c08e0",
+ 2481 => x"050c8c08",
+ 2482 => x"dc05088c",
+ 2483 => x"08e00508",
+ 2484 => x"8c088805",
+ 2485 => x"08585654",
+ 2486 => x"73760c74",
+ 2487 => x"84170c8c",
+ 2488 => x"08880508",
+ 2489 => x"800cb63d",
+ 2490 => x"0d8c0c04",
+ 2491 => x"8c08028c",
+ 2492 => x"0cfd3d0d",
+ 2493 => x"80538c08",
+ 2494 => x"8c050852",
+ 2495 => x"8c088805",
+ 2496 => x"085182de",
+ 2497 => x"3f800870",
+ 2498 => x"800c5485",
+ 2499 => x"3d0d8c0c",
+ 2500 => x"048c0802",
+ 2501 => x"8c0cfd3d",
+ 2502 => x"0d81538c",
+ 2503 => x"088c0508",
+ 2504 => x"528c0888",
+ 2505 => x"05085182",
+ 2506 => x"b93f8008",
+ 2507 => x"70800c54",
+ 2508 => x"853d0d8c",
+ 2509 => x"0c048c08",
+ 2510 => x"028c0cf9",
+ 2511 => x"3d0d800b",
+ 2512 => x"8c08fc05",
+ 2513 => x"0c8c0888",
+ 2514 => x"05088025",
+ 2515 => x"ab388c08",
+ 2516 => x"88050830",
+ 2517 => x"8c088805",
+ 2518 => x"0c800b8c",
+ 2519 => x"08f4050c",
+ 2520 => x"8c08fc05",
+ 2521 => x"08883881",
+ 2522 => x"0b8c08f4",
+ 2523 => x"050c8c08",
+ 2524 => x"f405088c",
+ 2525 => x"08fc050c",
+ 2526 => x"8c088c05",
+ 2527 => x"088025ab",
+ 2528 => x"388c088c",
+ 2529 => x"0508308c",
+ 2530 => x"088c050c",
+ 2531 => x"800b8c08",
+ 2532 => x"f0050c8c",
+ 2533 => x"08fc0508",
+ 2534 => x"8838810b",
+ 2535 => x"8c08f005",
+ 2536 => x"0c8c08f0",
+ 2537 => x"05088c08",
+ 2538 => x"fc050c80",
+ 2539 => x"538c088c",
+ 2540 => x"0508528c",
+ 2541 => x"08880508",
+ 2542 => x"5181a73f",
+ 2543 => x"8008708c",
+ 2544 => x"08f8050c",
+ 2545 => x"548c08fc",
+ 2546 => x"0508802e",
+ 2547 => x"8c388c08",
+ 2548 => x"f8050830",
+ 2549 => x"8c08f805",
+ 2550 => x"0c8c08f8",
+ 2551 => x"05087080",
+ 2552 => x"0c54893d",
+ 2553 => x"0d8c0c04",
+ 2554 => x"8c08028c",
+ 2555 => x"0cfb3d0d",
+ 2556 => x"800b8c08",
+ 2557 => x"fc050c8c",
+ 2558 => x"08880508",
+ 2559 => x"80259338",
+ 2560 => x"8c088805",
+ 2561 => x"08308c08",
+ 2562 => x"88050c81",
+ 2563 => x"0b8c08fc",
+ 2564 => x"050c8c08",
+ 2565 => x"8c050880",
+ 2566 => x"258c388c",
+ 2567 => x"088c0508",
+ 2568 => x"308c088c",
+ 2569 => x"050c8153",
+ 2570 => x"8c088c05",
+ 2571 => x"08528c08",
+ 2572 => x"88050851",
+ 2573 => x"ad3f8008",
+ 2574 => x"708c08f8",
+ 2575 => x"050c548c",
+ 2576 => x"08fc0508",
+ 2577 => x"802e8c38",
+ 2578 => x"8c08f805",
+ 2579 => x"08308c08",
+ 2580 => x"f8050c8c",
+ 2581 => x"08f80508",
+ 2582 => x"70800c54",
+ 2583 => x"873d0d8c",
+ 2584 => x"0c048c08",
+ 2585 => x"028c0cfd",
+ 2586 => x"3d0d810b",
+ 2587 => x"8c08fc05",
+ 2588 => x"0c800b8c",
+ 2589 => x"08f8050c",
+ 2590 => x"8c088c05",
+ 2591 => x"088c0888",
+ 2592 => x"050827ac",
+ 2593 => x"388c08fc",
+ 2594 => x"0508802e",
+ 2595 => x"a338800b",
+ 2596 => x"8c088c05",
+ 2597 => x"08249938",
+ 2598 => x"8c088c05",
+ 2599 => x"08108c08",
+ 2600 => x"8c050c8c",
+ 2601 => x"08fc0508",
+ 2602 => x"108c08fc",
+ 2603 => x"050cc939",
+ 2604 => x"8c08fc05",
+ 2605 => x"08802e80",
+ 2606 => x"c9388c08",
+ 2607 => x"8c05088c",
+ 2608 => x"08880508",
+ 2609 => x"26a1388c",
+ 2610 => x"08880508",
+ 2611 => x"8c088c05",
+ 2612 => x"08318c08",
+ 2613 => x"88050c8c",
+ 2614 => x"08f80508",
+ 2615 => x"8c08fc05",
+ 2616 => x"08078c08",
+ 2617 => x"f8050c8c",
+ 2618 => x"08fc0508",
+ 2619 => x"812a8c08",
+ 2620 => x"fc050c8c",
+ 2621 => x"088c0508",
+ 2622 => x"812a8c08",
+ 2623 => x"8c050cff",
+ 2624 => x"af398c08",
+ 2625 => x"90050880",
+ 2626 => x"2e8f388c",
+ 2627 => x"08880508",
+ 2628 => x"708c08f4",
+ 2629 => x"050c518d",
+ 2630 => x"398c08f8",
+ 2631 => x"0508708c",
+ 2632 => x"08f4050c",
+ 2633 => x"518c08f4",
+ 2634 => x"0508800c",
+ 2635 => x"853d0d8c",
+ 2636 => x"0c04ff3d",
+ 2637 => x"0d735281",
+ 2638 => x"81c80851",
+ 2639 => x"963f833d",
+ 2640 => x"0d04ff3d",
+ 2641 => x"0d735281",
+ 2642 => x"81c80851",
+ 2643 => x"90953f83",
+ 2644 => x"3d0d04f3",
+ 2645 => x"3d0d7f61",
+ 2646 => x"8b1170f8",
+ 2647 => x"065c5555",
+ 2648 => x"5e729626",
+ 2649 => x"83389059",
+ 2650 => x"80792474",
+ 2651 => x"7a260753",
+ 2652 => x"80547274",
+ 2653 => x"2e098106",
+ 2654 => x"80cb387d",
+ 2655 => x"518ce33f",
+ 2656 => x"7883f726",
+ 2657 => x"80c63878",
+ 2658 => x"832a7010",
+ 2659 => x"101080f9",
+ 2660 => x"c0058c11",
+ 2661 => x"0859595a",
+ 2662 => x"76782e83",
+ 2663 => x"b0388417",
+ 2664 => x"08fc0656",
+ 2665 => x"8c170888",
+ 2666 => x"1808718c",
+ 2667 => x"120c8812",
+ 2668 => x"0c587517",
+ 2669 => x"84110881",
+ 2670 => x"0784120c",
+ 2671 => x"537d518c",
+ 2672 => x"a23f8817",
+ 2673 => x"5473800c",
+ 2674 => x"8f3d0d04",
+ 2675 => x"78892a79",
+ 2676 => x"832a5b53",
+ 2677 => x"72802ebf",
+ 2678 => x"3878862a",
+ 2679 => x"b8055a84",
+ 2680 => x"7327b438",
+ 2681 => x"80db135a",
+ 2682 => x"947327ab",
+ 2683 => x"38788c2a",
+ 2684 => x"80ee055a",
+ 2685 => x"80d47327",
+ 2686 => x"9e38788f",
+ 2687 => x"2a80f705",
+ 2688 => x"5a82d473",
+ 2689 => x"27913878",
+ 2690 => x"922a80fc",
+ 2691 => x"055a8ad4",
+ 2692 => x"73278438",
+ 2693 => x"80fe5a79",
+ 2694 => x"10101080",
+ 2695 => x"f9c0058c",
+ 2696 => x"11085855",
+ 2697 => x"76752ea3",
+ 2698 => x"38841708",
+ 2699 => x"fc06707a",
+ 2700 => x"31555673",
+ 2701 => x"8f2488d5",
+ 2702 => x"38738025",
+ 2703 => x"fee6388c",
+ 2704 => x"17085776",
+ 2705 => x"752e0981",
+ 2706 => x"06df3881",
+ 2707 => x"1a5a80f9",
+ 2708 => x"d0085776",
+ 2709 => x"80f9c82e",
+ 2710 => x"82c03884",
+ 2711 => x"1708fc06",
+ 2712 => x"707a3155",
+ 2713 => x"56738f24",
+ 2714 => x"81f93880",
+ 2715 => x"f9c80b80",
+ 2716 => x"f9d40c80",
+ 2717 => x"f9c80b80",
+ 2718 => x"f9d00c73",
+ 2719 => x"8025feb2",
+ 2720 => x"3883ff76",
+ 2721 => x"2783df38",
+ 2722 => x"75892a76",
+ 2723 => x"832a5553",
+ 2724 => x"72802ebf",
+ 2725 => x"3875862a",
+ 2726 => x"b8055484",
+ 2727 => x"7327b438",
+ 2728 => x"80db1354",
+ 2729 => x"947327ab",
+ 2730 => x"38758c2a",
+ 2731 => x"80ee0554",
+ 2732 => x"80d47327",
+ 2733 => x"9e38758f",
+ 2734 => x"2a80f705",
+ 2735 => x"5482d473",
+ 2736 => x"27913875",
+ 2737 => x"922a80fc",
+ 2738 => x"05548ad4",
+ 2739 => x"73278438",
+ 2740 => x"80fe5473",
+ 2741 => x"10101080",
+ 2742 => x"f9c00588",
+ 2743 => x"11085658",
+ 2744 => x"74782e86",
+ 2745 => x"cf388415",
+ 2746 => x"08fc0653",
+ 2747 => x"7573278d",
+ 2748 => x"38881508",
+ 2749 => x"5574782e",
+ 2750 => x"098106ea",
+ 2751 => x"388c1508",
+ 2752 => x"80f9c00b",
+ 2753 => x"84050871",
+ 2754 => x"8c1a0c76",
+ 2755 => x"881a0c78",
+ 2756 => x"88130c78",
+ 2757 => x"8c180c5d",
+ 2758 => x"58795380",
+ 2759 => x"7a2483e6",
+ 2760 => x"3872822c",
+ 2761 => x"81712b5c",
+ 2762 => x"537a7c26",
+ 2763 => x"8198387b",
+ 2764 => x"7b065372",
+ 2765 => x"82f13879",
+ 2766 => x"fc068405",
+ 2767 => x"5a7a1070",
+ 2768 => x"7d06545b",
+ 2769 => x"7282e038",
+ 2770 => x"841a5af1",
+ 2771 => x"3988178c",
+ 2772 => x"11085858",
+ 2773 => x"76782e09",
+ 2774 => x"8106fcc2",
+ 2775 => x"38821a5a",
+ 2776 => x"fdec3978",
+ 2777 => x"17798107",
+ 2778 => x"84190c70",
+ 2779 => x"80f9d40c",
+ 2780 => x"7080f9d0",
+ 2781 => x"0c80f9c8",
+ 2782 => x"0b8c120c",
+ 2783 => x"8c110888",
+ 2784 => x"120c7481",
+ 2785 => x"0784120c",
+ 2786 => x"74117571",
+ 2787 => x"0c51537d",
+ 2788 => x"5188d03f",
+ 2789 => x"881754fc",
+ 2790 => x"ac3980f9",
+ 2791 => x"c00b8405",
+ 2792 => x"087a545c",
+ 2793 => x"798025fe",
+ 2794 => x"f83882da",
+ 2795 => x"397a097c",
+ 2796 => x"067080f9",
+ 2797 => x"c00b8405",
+ 2798 => x"0c5c7a10",
+ 2799 => x"5b7a7c26",
+ 2800 => x"85387a85",
+ 2801 => x"b83880f9",
+ 2802 => x"c00b8805",
+ 2803 => x"08708412",
+ 2804 => x"08fc0670",
+ 2805 => x"7c317c72",
+ 2806 => x"268f7225",
+ 2807 => x"0757575c",
+ 2808 => x"5d557280",
+ 2809 => x"2e80db38",
+ 2810 => x"797a1680",
+ 2811 => x"f9b8081b",
+ 2812 => x"90115a55",
+ 2813 => x"575b80f9",
+ 2814 => x"b408ff2e",
+ 2815 => x"8838a08f",
+ 2816 => x"13e08006",
+ 2817 => x"5776527d",
+ 2818 => x"5187d93f",
+ 2819 => x"80085480",
+ 2820 => x"08ff2e90",
+ 2821 => x"38800876",
+ 2822 => x"27829938",
+ 2823 => x"7480f9c0",
+ 2824 => x"2e829138",
+ 2825 => x"80f9c00b",
+ 2826 => x"88050855",
+ 2827 => x"841508fc",
+ 2828 => x"06707a31",
+ 2829 => x"7a72268f",
+ 2830 => x"72250752",
+ 2831 => x"55537283",
+ 2832 => x"e6387479",
+ 2833 => x"81078417",
+ 2834 => x"0c791670",
+ 2835 => x"80f9c00b",
+ 2836 => x"88050c75",
+ 2837 => x"81078412",
+ 2838 => x"0c547e52",
+ 2839 => x"5787843f",
+ 2840 => x"881754fa",
+ 2841 => x"e0397583",
+ 2842 => x"2a705454",
+ 2843 => x"80742481",
+ 2844 => x"9b387282",
+ 2845 => x"2c81712b",
+ 2846 => x"80f9c408",
+ 2847 => x"077080f9",
+ 2848 => x"c00b8405",
+ 2849 => x"0c751010",
+ 2850 => x"1080f9c0",
+ 2851 => x"05881108",
+ 2852 => x"585a5d53",
+ 2853 => x"778c180c",
+ 2854 => x"7488180c",
+ 2855 => x"7688190c",
+ 2856 => x"768c160c",
+ 2857 => x"fcf33979",
+ 2858 => x"7a101010",
+ 2859 => x"80f9c005",
+ 2860 => x"7057595d",
+ 2861 => x"8c150857",
+ 2862 => x"76752ea3",
+ 2863 => x"38841708",
+ 2864 => x"fc06707a",
+ 2865 => x"31555673",
+ 2866 => x"8f2483ca",
+ 2867 => x"38738025",
+ 2868 => x"8481388c",
+ 2869 => x"17085776",
+ 2870 => x"752e0981",
+ 2871 => x"06df3888",
+ 2872 => x"15811b70",
+ 2873 => x"8306555b",
+ 2874 => x"5572c938",
+ 2875 => x"7c830653",
+ 2876 => x"72802efd",
+ 2877 => x"b838ff1d",
+ 2878 => x"f819595d",
+ 2879 => x"88180878",
+ 2880 => x"2eea38fd",
+ 2881 => x"b539831a",
+ 2882 => x"53fc9639",
+ 2883 => x"83147082",
+ 2884 => x"2c81712b",
+ 2885 => x"80f9c408",
+ 2886 => x"077080f9",
+ 2887 => x"c00b8405",
+ 2888 => x"0c761010",
+ 2889 => x"1080f9c0",
+ 2890 => x"05881108",
+ 2891 => x"595b5e51",
+ 2892 => x"53fee139",
+ 2893 => x"80f98408",
+ 2894 => x"17588008",
+ 2895 => x"762e818d",
+ 2896 => x"3880f9b4",
+ 2897 => x"08ff2e83",
+ 2898 => x"ec387376",
+ 2899 => x"311880f9",
+ 2900 => x"840c7387",
+ 2901 => x"06705753",
+ 2902 => x"72802e88",
+ 2903 => x"38887331",
+ 2904 => x"70155556",
+ 2905 => x"76149fff",
+ 2906 => x"06a08071",
+ 2907 => x"31177054",
+ 2908 => x"7f535753",
+ 2909 => x"84ee3f80",
+ 2910 => x"08538008",
+ 2911 => x"ff2e81a0",
+ 2912 => x"3880f984",
+ 2913 => x"08167080",
+ 2914 => x"f9840c74",
+ 2915 => x"7580f9c0",
+ 2916 => x"0b88050c",
+ 2917 => x"74763118",
+ 2918 => x"70810751",
+ 2919 => x"5556587b",
+ 2920 => x"80f9c02e",
+ 2921 => x"839c3879",
+ 2922 => x"8f2682cb",
+ 2923 => x"38810b84",
+ 2924 => x"150c8415",
+ 2925 => x"08fc0670",
+ 2926 => x"7a317a72",
+ 2927 => x"268f7225",
+ 2928 => x"07525553",
+ 2929 => x"72802efc",
+ 2930 => x"f93880db",
+ 2931 => x"3980089f",
+ 2932 => x"ff065372",
+ 2933 => x"feeb3877",
+ 2934 => x"80f9840c",
+ 2935 => x"80f9c00b",
+ 2936 => x"8805087b",
+ 2937 => x"18810784",
+ 2938 => x"120c5580",
+ 2939 => x"f9b00878",
+ 2940 => x"27863877",
+ 2941 => x"80f9b00c",
+ 2942 => x"80f9ac08",
+ 2943 => x"7827fcac",
+ 2944 => x"387780f9",
+ 2945 => x"ac0c8415",
+ 2946 => x"08fc0670",
+ 2947 => x"7a317a72",
+ 2948 => x"268f7225",
+ 2949 => x"07525553",
+ 2950 => x"72802efc",
+ 2951 => x"a5388839",
+ 2952 => x"80745456",
+ 2953 => x"fedb397d",
+ 2954 => x"5183b83f",
+ 2955 => x"800b800c",
+ 2956 => x"8f3d0d04",
+ 2957 => x"73538074",
+ 2958 => x"24a93872",
+ 2959 => x"822c8171",
+ 2960 => x"2b80f9c4",
+ 2961 => x"08077080",
+ 2962 => x"f9c00b84",
+ 2963 => x"050c5d53",
+ 2964 => x"778c180c",
+ 2965 => x"7488180c",
+ 2966 => x"7688190c",
+ 2967 => x"768c160c",
+ 2968 => x"f9b73983",
+ 2969 => x"1470822c",
+ 2970 => x"81712b80",
+ 2971 => x"f9c40807",
+ 2972 => x"7080f9c0",
+ 2973 => x"0b84050c",
+ 2974 => x"5e5153d4",
+ 2975 => x"397b7b06",
+ 2976 => x"5372fca3",
+ 2977 => x"38841a7b",
+ 2978 => x"105c5af1",
+ 2979 => x"39ff1a81",
+ 2980 => x"11515af7",
+ 2981 => x"b9397817",
+ 2982 => x"79810784",
+ 2983 => x"190c8c18",
+ 2984 => x"08881908",
+ 2985 => x"718c120c",
+ 2986 => x"88120c59",
+ 2987 => x"7080f9d4",
+ 2988 => x"0c7080f9",
+ 2989 => x"d00c80f9",
+ 2990 => x"c80b8c12",
+ 2991 => x"0c8c1108",
+ 2992 => x"88120c74",
+ 2993 => x"81078412",
+ 2994 => x"0c741175",
+ 2995 => x"710c5153",
+ 2996 => x"f9bd3975",
+ 2997 => x"17841108",
+ 2998 => x"81078412",
+ 2999 => x"0c538c17",
+ 3000 => x"08881808",
+ 3001 => x"718c120c",
+ 3002 => x"88120c58",
+ 3003 => x"7d5181f3",
+ 3004 => x"3f881754",
+ 3005 => x"f5cf3972",
+ 3006 => x"84150cf4",
+ 3007 => x"1af80670",
+ 3008 => x"841e0881",
+ 3009 => x"0607841e",
+ 3010 => x"0c701d54",
+ 3011 => x"5b850b84",
+ 3012 => x"140c850b",
+ 3013 => x"88140c8f",
+ 3014 => x"7b27fdcf",
+ 3015 => x"38881c52",
+ 3016 => x"7d5184bf",
+ 3017 => x"3f80f9c0",
+ 3018 => x"0b880508",
+ 3019 => x"80f98408",
+ 3020 => x"5955fdb7",
+ 3021 => x"397780f9",
+ 3022 => x"840c7380",
+ 3023 => x"f9b40cfc",
+ 3024 => x"91397284",
+ 3025 => x"150cfda3",
+ 3026 => x"39fc3d0d",
+ 3027 => x"7670797b",
+ 3028 => x"55555555",
+ 3029 => x"8f72278c",
+ 3030 => x"38727507",
+ 3031 => x"83065170",
+ 3032 => x"802ea738",
+ 3033 => x"ff125271",
+ 3034 => x"ff2e9838",
+ 3035 => x"72708105",
+ 3036 => x"54337470",
+ 3037 => x"81055634",
+ 3038 => x"ff125271",
+ 3039 => x"ff2e0981",
+ 3040 => x"06ea3874",
+ 3041 => x"800c863d",
+ 3042 => x"0d047451",
+ 3043 => x"72708405",
+ 3044 => x"54087170",
+ 3045 => x"8405530c",
+ 3046 => x"72708405",
+ 3047 => x"54087170",
+ 3048 => x"8405530c",
+ 3049 => x"72708405",
+ 3050 => x"54087170",
+ 3051 => x"8405530c",
+ 3052 => x"72708405",
+ 3053 => x"54087170",
+ 3054 => x"8405530c",
+ 3055 => x"f0125271",
+ 3056 => x"8f26c938",
+ 3057 => x"83722795",
+ 3058 => x"38727084",
+ 3059 => x"05540871",
+ 3060 => x"70840553",
+ 3061 => x"0cfc1252",
+ 3062 => x"718326ed",
+ 3063 => x"387054ff",
+ 3064 => x"83390404",
+ 3065 => x"fd3d0d80",
+ 3066 => x"0b81d998",
+ 3067 => x"0c765187",
+ 3068 => x"c83f8008",
+ 3069 => x"538008ff",
+ 3070 => x"2e883872",
+ 3071 => x"800c853d",
+ 3072 => x"0d0481d9",
+ 3073 => x"98085473",
+ 3074 => x"802ef038",
+ 3075 => x"7574710c",
+ 3076 => x"5272800c",
+ 3077 => x"853d0d04",
+ 3078 => x"fb3d0d77",
+ 3079 => x"79707207",
+ 3080 => x"83065354",
+ 3081 => x"52709338",
+ 3082 => x"71737308",
+ 3083 => x"54565471",
+ 3084 => x"73082e80",
+ 3085 => x"c4387375",
+ 3086 => x"54527133",
+ 3087 => x"7081ff06",
+ 3088 => x"52547080",
+ 3089 => x"2e9d3872",
+ 3090 => x"33557075",
+ 3091 => x"2e098106",
+ 3092 => x"95388112",
+ 3093 => x"81147133",
+ 3094 => x"7081ff06",
+ 3095 => x"54565452",
+ 3096 => x"70e53872",
+ 3097 => x"33557381",
+ 3098 => x"ff067581",
+ 3099 => x"ff067171",
+ 3100 => x"31800c52",
+ 3101 => x"52873d0d",
+ 3102 => x"04710970",
+ 3103 => x"f7fbfdff",
+ 3104 => x"140670f8",
+ 3105 => x"84828180",
+ 3106 => x"06515151",
+ 3107 => x"70973884",
+ 3108 => x"14841671",
+ 3109 => x"08545654",
+ 3110 => x"7175082e",
+ 3111 => x"dc387375",
+ 3112 => x"5452ff96",
+ 3113 => x"39800b80",
+ 3114 => x"0c873d0d",
+ 3115 => x"04fb3d0d",
+ 3116 => x"77705256",
+ 3117 => x"feac3f80",
+ 3118 => x"f9c00b88",
+ 3119 => x"05088411",
+ 3120 => x"08fc0670",
+ 3121 => x"7b319fef",
+ 3122 => x"05e08006",
+ 3123 => x"e0800556",
+ 3124 => x"5653a080",
+ 3125 => x"74249438",
+ 3126 => x"80527551",
+ 3127 => x"fe863f80",
+ 3128 => x"f9c80815",
+ 3129 => x"53728008",
+ 3130 => x"2e8f3875",
+ 3131 => x"51fdf43f",
+ 3132 => x"80537280",
+ 3133 => x"0c873d0d",
+ 3134 => x"04733052",
+ 3135 => x"7551fde4",
+ 3136 => x"3f8008ff",
+ 3137 => x"2ea83880",
+ 3138 => x"f9c00b88",
+ 3139 => x"05087575",
+ 3140 => x"31810784",
+ 3141 => x"120c5380",
+ 3142 => x"f9840874",
+ 3143 => x"3180f984",
+ 3144 => x"0c7551fd",
+ 3145 => x"be3f810b",
+ 3146 => x"800c873d",
+ 3147 => x"0d048052",
+ 3148 => x"7551fdb0",
+ 3149 => x"3f80f9c0",
+ 3150 => x"0b880508",
+ 3151 => x"80087131",
+ 3152 => x"56538f75",
+ 3153 => x"25ffa438",
+ 3154 => x"800880f9",
+ 3155 => x"b4083180",
+ 3156 => x"f9840c74",
+ 3157 => x"81078414",
+ 3158 => x"0c7551fd",
+ 3159 => x"863f8053",
+ 3160 => x"ff9039f6",
+ 3161 => x"3d0d7c7e",
+ 3162 => x"545b7280",
+ 3163 => x"2e828338",
+ 3164 => x"7a51fcee",
+ 3165 => x"3ff81384",
+ 3166 => x"110870fe",
+ 3167 => x"06701384",
+ 3168 => x"1108fc06",
+ 3169 => x"5d585954",
+ 3170 => x"5880f9c8",
+ 3171 => x"08752e82",
+ 3172 => x"de387884",
+ 3173 => x"160c8073",
+ 3174 => x"8106545a",
+ 3175 => x"727a2e81",
+ 3176 => x"d5387815",
+ 3177 => x"84110881",
+ 3178 => x"06515372",
+ 3179 => x"a0387817",
+ 3180 => x"577981e6",
+ 3181 => x"38881508",
+ 3182 => x"537280f9",
+ 3183 => x"c82e82f9",
+ 3184 => x"388c1508",
+ 3185 => x"708c150c",
+ 3186 => x"7388120c",
+ 3187 => x"56768107",
+ 3188 => x"84190c76",
+ 3189 => x"1877710c",
+ 3190 => x"53798191",
+ 3191 => x"3883ff77",
+ 3192 => x"2781c838",
+ 3193 => x"76892a77",
+ 3194 => x"832a5653",
+ 3195 => x"72802ebf",
+ 3196 => x"3876862a",
+ 3197 => x"b8055584",
+ 3198 => x"7327b438",
+ 3199 => x"80db1355",
+ 3200 => x"947327ab",
+ 3201 => x"38768c2a",
+ 3202 => x"80ee0555",
+ 3203 => x"80d47327",
+ 3204 => x"9e38768f",
+ 3205 => x"2a80f705",
+ 3206 => x"5582d473",
+ 3207 => x"27913876",
+ 3208 => x"922a80fc",
+ 3209 => x"05558ad4",
+ 3210 => x"73278438",
+ 3211 => x"80fe5574",
+ 3212 => x"10101080",
+ 3213 => x"f9c00588",
+ 3214 => x"11085556",
+ 3215 => x"73762e82",
+ 3216 => x"b3388414",
+ 3217 => x"08fc0653",
+ 3218 => x"7673278d",
+ 3219 => x"38881408",
+ 3220 => x"5473762e",
+ 3221 => x"098106ea",
+ 3222 => x"388c1408",
+ 3223 => x"708c1a0c",
+ 3224 => x"74881a0c",
+ 3225 => x"7888120c",
+ 3226 => x"56778c15",
+ 3227 => x"0c7a51fa",
+ 3228 => x"f23f8c3d",
+ 3229 => x"0d047708",
+ 3230 => x"78713159",
+ 3231 => x"77058819",
+ 3232 => x"08545772",
+ 3233 => x"80f9c82e",
+ 3234 => x"80e0388c",
+ 3235 => x"1808708c",
+ 3236 => x"150c7388",
+ 3237 => x"120c56fe",
+ 3238 => x"89398815",
+ 3239 => x"088c1608",
+ 3240 => x"708c130c",
+ 3241 => x"5788170c",
+ 3242 => x"fea33976",
+ 3243 => x"832a7054",
+ 3244 => x"55807524",
+ 3245 => x"81983872",
+ 3246 => x"822c8171",
+ 3247 => x"2b80f9c4",
+ 3248 => x"080780f9",
+ 3249 => x"c00b8405",
+ 3250 => x"0c537410",
+ 3251 => x"101080f9",
+ 3252 => x"c0058811",
+ 3253 => x"08555675",
+ 3254 => x"8c190c73",
+ 3255 => x"88190c77",
+ 3256 => x"88170c77",
+ 3257 => x"8c150cff",
+ 3258 => x"8439815a",
+ 3259 => x"fdb43978",
+ 3260 => x"17738106",
+ 3261 => x"54577298",
+ 3262 => x"38770878",
+ 3263 => x"71315977",
+ 3264 => x"058c1908",
+ 3265 => x"881a0871",
+ 3266 => x"8c120c88",
+ 3267 => x"120c5757",
+ 3268 => x"76810784",
+ 3269 => x"190c7780",
+ 3270 => x"f9c00b88",
+ 3271 => x"050c80f9",
+ 3272 => x"bc087726",
+ 3273 => x"fec73880",
+ 3274 => x"f9b80852",
+ 3275 => x"7a51fafd",
+ 3276 => x"3f7a51f9",
+ 3277 => x"ae3ffeba",
+ 3278 => x"3981788c",
+ 3279 => x"150c7888",
+ 3280 => x"150c738c",
+ 3281 => x"1a0c7388",
+ 3282 => x"1a0c5afd",
+ 3283 => x"80398315",
+ 3284 => x"70822c81",
+ 3285 => x"712b80f9",
+ 3286 => x"c4080780",
+ 3287 => x"f9c00b84",
+ 3288 => x"050c5153",
+ 3289 => x"74101010",
+ 3290 => x"80f9c005",
+ 3291 => x"88110855",
+ 3292 => x"56fee439",
+ 3293 => x"74538075",
+ 3294 => x"24a73872",
+ 3295 => x"822c8171",
+ 3296 => x"2b80f9c4",
+ 3297 => x"080780f9",
+ 3298 => x"c00b8405",
+ 3299 => x"0c53758c",
+ 3300 => x"190c7388",
+ 3301 => x"190c7788",
+ 3302 => x"170c778c",
+ 3303 => x"150cfdcd",
+ 3304 => x"39831570",
+ 3305 => x"822c8171",
+ 3306 => x"2b80f9c4",
+ 3307 => x"080780f9",
+ 3308 => x"c00b8405",
+ 3309 => x"0c5153d6",
+ 3310 => x"39fe3d0d",
+ 3311 => x"8188f008",
+ 3312 => x"51708a38",
+ 3313 => x"81d99c70",
+ 3314 => x"8188f00c",
+ 3315 => x"51707512",
+ 3316 => x"5252ff53",
+ 3317 => x"7087fb80",
+ 3318 => x"80268838",
+ 3319 => x"708188f0",
+ 3320 => x"0c715372",
+ 3321 => x"800c843d",
+ 3322 => x"0d04fd3d",
+ 3323 => x"0d800b80",
+ 3324 => x"f8ec0854",
+ 3325 => x"5472812e",
+ 3326 => x"9e387381",
+ 3327 => x"88f40cff",
+ 3328 => x"a0ff3fff",
+ 3329 => x"9ffa3f81",
+ 3330 => x"88c85281",
+ 3331 => x"51ffa9ae",
+ 3332 => x"3f800851",
+ 3333 => x"80e13f72",
+ 3334 => x"8188f40c",
+ 3335 => x"ffa0e23f",
+ 3336 => x"ff9fdd3f",
+ 3337 => x"8188c852",
+ 3338 => x"8151ffa9",
+ 3339 => x"913f8008",
+ 3340 => x"5180c43f",
+ 3341 => x"00ff3900",
+ 3342 => x"ff39f43d",
+ 3343 => x"0d7e8188",
+ 3344 => x"e8087008",
+ 3345 => x"7081ff06",
+ 3346 => x"923df805",
+ 3347 => x"55515a57",
+ 3348 => x"59ffa19a",
+ 3349 => x"3f805477",
+ 3350 => x"557b7d58",
+ 3351 => x"5276538e",
+ 3352 => x"3df00551",
+ 3353 => x"c0c03f79",
+ 3354 => x"7b58790c",
+ 3355 => x"76841a0c",
+ 3356 => x"78800c8e",
+ 3357 => x"3d0d04f7",
+ 3358 => x"3d0d7b81",
+ 3359 => x"81c80882",
+ 3360 => x"c811085a",
+ 3361 => x"545a7780",
+ 3362 => x"2e80da38",
+ 3363 => x"81881884",
+ 3364 => x"1908ff05",
+ 3365 => x"81712b59",
+ 3366 => x"55598074",
+ 3367 => x"2480ea38",
+ 3368 => x"807424b5",
+ 3369 => x"3873822b",
+ 3370 => x"78118805",
+ 3371 => x"56568180",
+ 3372 => x"19087706",
+ 3373 => x"5372802e",
+ 3374 => x"b6387816",
+ 3375 => x"70085353",
+ 3376 => x"79517408",
+ 3377 => x"53722dff",
+ 3378 => x"14fc17fc",
+ 3379 => x"1779812c",
+ 3380 => x"5a575754",
+ 3381 => x"738025d6",
+ 3382 => x"38770858",
+ 3383 => x"77ffad38",
+ 3384 => x"8181c808",
+ 3385 => x"53bc1308",
+ 3386 => x"a5387951",
+ 3387 => x"fec63f74",
+ 3388 => x"0853722d",
+ 3389 => x"ff14fc17",
+ 3390 => x"fc177981",
+ 3391 => x"2c5a5757",
+ 3392 => x"54738025",
+ 3393 => x"ffa838d1",
+ 3394 => x"398057ff",
+ 3395 => x"93397251",
+ 3396 => x"bc130853",
+ 3397 => x"722d7951",
+ 3398 => x"fe9a3fff",
+ 3399 => x"3d0d8188",
+ 3400 => x"d00bfc05",
+ 3401 => x"70085252",
+ 3402 => x"70ff2e91",
+ 3403 => x"38702dfc",
+ 3404 => x"12700852",
+ 3405 => x"5270ff2e",
+ 3406 => x"098106f1",
+ 3407 => x"38833d0d",
+ 3408 => x"0404ffa0",
+ 3409 => x"873f0400",
+ 3410 => x"00000040",
+ 3411 => x"30313233",
+ 3412 => x"34353637",
+ 3413 => x"38390000",
+ 3414 => x"44485259",
+ 3415 => x"53544f4e",
+ 3416 => x"45205052",
+ 3417 => x"4f475241",
+ 3418 => x"4d2c2053",
+ 3419 => x"4f4d4520",
+ 3420 => x"53545249",
+ 3421 => x"4e470000",
+ 3422 => x"44485259",
+ 3423 => x"53544f4e",
+ 3424 => x"45205052",
+ 3425 => x"4f475241",
+ 3426 => x"4d2c2031",
+ 3427 => x"27535420",
+ 3428 => x"53545249",
+ 3429 => x"4e470000",
+ 3430 => x"44687279",
+ 3431 => x"73746f6e",
+ 3432 => x"65204265",
+ 3433 => x"6e63686d",
+ 3434 => x"61726b2c",
+ 3435 => x"20566572",
+ 3436 => x"73696f6e",
+ 3437 => x"20322e31",
+ 3438 => x"20284c61",
+ 3439 => x"6e677561",
+ 3440 => x"67653a20",
+ 3441 => x"43290a00",
+ 3442 => x"50726f67",
+ 3443 => x"72616d20",
+ 3444 => x"636f6d70",
+ 3445 => x"696c6564",
+ 3446 => x"20776974",
+ 3447 => x"68202772",
+ 3448 => x"65676973",
+ 3449 => x"74657227",
+ 3450 => x"20617474",
+ 3451 => x"72696275",
+ 3452 => x"74650a00",
+ 3453 => x"45786563",
+ 3454 => x"7574696f",
+ 3455 => x"6e207374",
+ 3456 => x"61727473",
+ 3457 => x"2c202564",
+ 3458 => x"2072756e",
+ 3459 => x"73207468",
+ 3460 => x"726f7567",
+ 3461 => x"68204468",
+ 3462 => x"72797374",
+ 3463 => x"6f6e650a",
+ 3464 => x"00000000",
+ 3465 => x"44485259",
+ 3466 => x"53544f4e",
+ 3467 => x"45205052",
+ 3468 => x"4f475241",
+ 3469 => x"4d2c2032",
+ 3470 => x"274e4420",
+ 3471 => x"53545249",
+ 3472 => x"4e470000",
+ 3473 => x"45786563",
+ 3474 => x"7574696f",
+ 3475 => x"6e20656e",
+ 3476 => x"64730a00",
+ 3477 => x"46696e61",
+ 3478 => x"6c207661",
+ 3479 => x"6c756573",
+ 3480 => x"206f6620",
+ 3481 => x"74686520",
+ 3482 => x"76617269",
+ 3483 => x"61626c65",
+ 3484 => x"73207573",
+ 3485 => x"65642069",
+ 3486 => x"6e207468",
+ 3487 => x"65206265",
+ 3488 => x"6e63686d",
+ 3489 => x"61726b3a",
+ 3490 => x"0a000000",
+ 3491 => x"496e745f",
+ 3492 => x"476c6f62",
+ 3493 => x"3a202020",
+ 3494 => x"20202020",
+ 3495 => x"20202020",
+ 3496 => x"2025640a",
+ 3497 => x"00000000",
+ 3498 => x"20202020",
+ 3499 => x"20202020",
+ 3500 => x"73686f75",
+ 3501 => x"6c642062",
+ 3502 => x"653a2020",
+ 3503 => x"2025640a",
+ 3504 => x"00000000",
+ 3505 => x"426f6f6c",
+ 3506 => x"5f476c6f",
+ 3507 => x"623a2020",
+ 3508 => x"20202020",
+ 3509 => x"20202020",
+ 3510 => x"2025640a",
+ 3511 => x"00000000",
+ 3512 => x"43685f31",
+ 3513 => x"5f476c6f",
+ 3514 => x"623a2020",
+ 3515 => x"20202020",
+ 3516 => x"20202020",
+ 3517 => x"2025630a",
+ 3518 => x"00000000",
+ 3519 => x"20202020",
+ 3520 => x"20202020",
+ 3521 => x"73686f75",
+ 3522 => x"6c642062",
+ 3523 => x"653a2020",
+ 3524 => x"2025630a",
+ 3525 => x"00000000",
+ 3526 => x"43685f32",
+ 3527 => x"5f476c6f",
+ 3528 => x"623a2020",
+ 3529 => x"20202020",
+ 3530 => x"20202020",
+ 3531 => x"2025630a",
+ 3532 => x"00000000",
+ 3533 => x"4172725f",
+ 3534 => x"315f476c",
+ 3535 => x"6f625b38",
+ 3536 => x"5d3a2020",
+ 3537 => x"20202020",
+ 3538 => x"2025640a",
+ 3539 => x"00000000",
+ 3540 => x"4172725f",
+ 3541 => x"325f476c",
+ 3542 => x"6f625b38",
+ 3543 => x"5d5b375d",
+ 3544 => x"3a202020",
+ 3545 => x"2025640a",
+ 3546 => x"00000000",
+ 3547 => x"20202020",
+ 3548 => x"20202020",
+ 3549 => x"73686f75",
+ 3550 => x"6c642062",
+ 3551 => x"653a2020",
+ 3552 => x"204e756d",
+ 3553 => x"6265725f",
+ 3554 => x"4f665f52",
+ 3555 => x"756e7320",
+ 3556 => x"2b203130",
+ 3557 => x"0a000000",
+ 3558 => x"5074725f",
+ 3559 => x"476c6f62",
+ 3560 => x"2d3e0a00",
+ 3561 => x"20205074",
+ 3562 => x"725f436f",
+ 3563 => x"6d703a20",
+ 3564 => x"20202020",
+ 3565 => x"20202020",
+ 3566 => x"2025640a",
+ 3567 => x"00000000",
+ 3568 => x"20202020",
+ 3569 => x"20202020",
+ 3570 => x"73686f75",
+ 3571 => x"6c642062",
+ 3572 => x"653a2020",
+ 3573 => x"2028696d",
+ 3574 => x"706c656d",
+ 3575 => x"656e7461",
+ 3576 => x"74696f6e",
+ 3577 => x"2d646570",
+ 3578 => x"656e6465",
+ 3579 => x"6e74290a",
+ 3580 => x"00000000",
+ 3581 => x"20204469",
+ 3582 => x"7363723a",
+ 3583 => x"20202020",
+ 3584 => x"20202020",
+ 3585 => x"20202020",
+ 3586 => x"2025640a",
+ 3587 => x"00000000",
+ 3588 => x"2020456e",
+ 3589 => x"756d5f43",
+ 3590 => x"6f6d703a",
+ 3591 => x"20202020",
+ 3592 => x"20202020",
+ 3593 => x"2025640a",
+ 3594 => x"00000000",
+ 3595 => x"2020496e",
+ 3596 => x"745f436f",
+ 3597 => x"6d703a20",
+ 3598 => x"20202020",
+ 3599 => x"20202020",
+ 3600 => x"2025640a",
+ 3601 => x"00000000",
+ 3602 => x"20205374",
+ 3603 => x"725f436f",
+ 3604 => x"6d703a20",
+ 3605 => x"20202020",
+ 3606 => x"20202020",
+ 3607 => x"2025730a",
+ 3608 => x"00000000",
+ 3609 => x"20202020",
+ 3610 => x"20202020",
+ 3611 => x"73686f75",
+ 3612 => x"6c642062",
+ 3613 => x"653a2020",
+ 3614 => x"20444852",
+ 3615 => x"5953544f",
+ 3616 => x"4e452050",
+ 3617 => x"524f4752",
+ 3618 => x"414d2c20",
+ 3619 => x"534f4d45",
+ 3620 => x"20535452",
+ 3621 => x"494e470a",
+ 3622 => x"00000000",
+ 3623 => x"4e657874",
+ 3624 => x"5f507472",
+ 3625 => x"5f476c6f",
+ 3626 => x"622d3e0a",
+ 3627 => x"00000000",
+ 3628 => x"20202020",
+ 3629 => x"20202020",
+ 3630 => x"73686f75",
+ 3631 => x"6c642062",
+ 3632 => x"653a2020",
+ 3633 => x"2028696d",
+ 3634 => x"706c656d",
+ 3635 => x"656e7461",
+ 3636 => x"74696f6e",
+ 3637 => x"2d646570",
+ 3638 => x"656e6465",
+ 3639 => x"6e74292c",
+ 3640 => x"2073616d",
+ 3641 => x"65206173",
+ 3642 => x"2061626f",
+ 3643 => x"76650a00",
+ 3644 => x"496e745f",
+ 3645 => x"315f4c6f",
+ 3646 => x"633a2020",
+ 3647 => x"20202020",
+ 3648 => x"20202020",
+ 3649 => x"2025640a",
+ 3650 => x"00000000",
+ 3651 => x"496e745f",
+ 3652 => x"325f4c6f",
+ 3653 => x"633a2020",
+ 3654 => x"20202020",
+ 3655 => x"20202020",
+ 3656 => x"2025640a",
+ 3657 => x"00000000",
+ 3658 => x"496e745f",
+ 3659 => x"335f4c6f",
+ 3660 => x"633a2020",
+ 3661 => x"20202020",
+ 3662 => x"20202020",
+ 3663 => x"2025640a",
+ 3664 => x"00000000",
+ 3665 => x"456e756d",
+ 3666 => x"5f4c6f63",
+ 3667 => x"3a202020",
+ 3668 => x"20202020",
+ 3669 => x"20202020",
+ 3670 => x"2025640a",
+ 3671 => x"00000000",
+ 3672 => x"5374725f",
+ 3673 => x"315f4c6f",
+ 3674 => x"633a2020",
+ 3675 => x"20202020",
+ 3676 => x"20202020",
+ 3677 => x"2025730a",
+ 3678 => x"00000000",
+ 3679 => x"20202020",
+ 3680 => x"20202020",
+ 3681 => x"73686f75",
+ 3682 => x"6c642062",
+ 3683 => x"653a2020",
+ 3684 => x"20444852",
+ 3685 => x"5953544f",
+ 3686 => x"4e452050",
+ 3687 => x"524f4752",
+ 3688 => x"414d2c20",
+ 3689 => x"31275354",
+ 3690 => x"20535452",
+ 3691 => x"494e470a",
+ 3692 => x"00000000",
+ 3693 => x"5374725f",
+ 3694 => x"325f4c6f",
+ 3695 => x"633a2020",
+ 3696 => x"20202020",
+ 3697 => x"20202020",
+ 3698 => x"2025730a",
+ 3699 => x"00000000",
+ 3700 => x"20202020",
+ 3701 => x"20202020",
+ 3702 => x"73686f75",
+ 3703 => x"6c642062",
+ 3704 => x"653a2020",
+ 3705 => x"20444852",
+ 3706 => x"5953544f",
+ 3707 => x"4e452050",
+ 3708 => x"524f4752",
+ 3709 => x"414d2c20",
+ 3710 => x"32274e44",
+ 3711 => x"20535452",
+ 3712 => x"494e470a",
+ 3713 => x"00000000",
+ 3714 => x"55736572",
+ 3715 => x"2074696d",
+ 3716 => x"653a2025",
+ 3717 => x"640a0000",
+ 3718 => x"4d696372",
+ 3719 => x"6f736563",
+ 3720 => x"6f6e6473",
+ 3721 => x"20666f72",
+ 3722 => x"206f6e65",
+ 3723 => x"2072756e",
+ 3724 => x"20746872",
+ 3725 => x"6f756768",
+ 3726 => x"20446872",
+ 3727 => x"7973746f",
+ 3728 => x"6e653a20",
+ 3729 => x"00000000",
+ 3730 => x"2564200a",
+ 3731 => x"00000000",
+ 3732 => x"44687279",
+ 3733 => x"73746f6e",
+ 3734 => x"65732070",
+ 3735 => x"65722053",
+ 3736 => x"65636f6e",
+ 3737 => x"643a2020",
+ 3738 => x"20202020",
+ 3739 => x"20202020",
+ 3740 => x"20202020",
+ 3741 => x"20202020",
+ 3742 => x"20202020",
+ 3743 => x"00000000",
+ 3744 => x"56415820",
+ 3745 => x"4d495053",
+ 3746 => x"20726174",
+ 3747 => x"696e6720",
+ 3748 => x"2a203130",
+ 3749 => x"3030203d",
+ 3750 => x"20256420",
+ 3751 => x"0a000000",
+ 3752 => x"50726f67",
+ 3753 => x"72616d20",
+ 3754 => x"636f6d70",
+ 3755 => x"696c6564",
+ 3756 => x"20776974",
+ 3757 => x"686f7574",
+ 3758 => x"20277265",
+ 3759 => x"67697374",
+ 3760 => x"65722720",
+ 3761 => x"61747472",
+ 3762 => x"69627574",
+ 3763 => x"650a0000",
+ 3764 => x"4d656173",
+ 3765 => x"75726564",
+ 3766 => x"2074696d",
+ 3767 => x"6520746f",
+ 3768 => x"6f20736d",
+ 3769 => x"616c6c20",
+ 3770 => x"746f206f",
+ 3771 => x"62746169",
+ 3772 => x"6e206d65",
+ 3773 => x"616e696e",
+ 3774 => x"6766756c",
+ 3775 => x"20726573",
+ 3776 => x"756c7473",
+ 3777 => x"0a000000",
+ 3778 => x"506c6561",
+ 3779 => x"73652069",
+ 3780 => x"6e637265",
+ 3781 => x"61736520",
+ 3782 => x"6e756d62",
+ 3783 => x"6572206f",
+ 3784 => x"66207275",
+ 3785 => x"6e730a00",
+ 3786 => x"44485259",
+ 3787 => x"53544f4e",
+ 3788 => x"45205052",
+ 3789 => x"4f475241",
+ 3790 => x"4d2c2033",
+ 3791 => x"27524420",
+ 3792 => x"53545249",
+ 3793 => x"4e470000",
+ 3794 => x"00010202",
+ 3795 => x"03030303",
+ 3796 => x"04040404",
+ 3797 => x"04040404",
+ 3798 => x"05050505",
+ 3799 => x"05050505",
+ 3800 => x"05050505",
+ 3801 => x"05050505",
+ 3802 => x"06060606",
+ 3803 => x"06060606",
+ 3804 => x"06060606",
+ 3805 => x"06060606",
+ 3806 => x"06060606",
+ 3807 => x"06060606",
+ 3808 => x"06060606",
+ 3809 => x"06060606",
+ 3810 => x"07070707",
+ 3811 => x"07070707",
+ 3812 => x"07070707",
+ 3813 => x"07070707",
+ 3814 => x"07070707",
+ 3815 => x"07070707",
+ 3816 => x"07070707",
+ 3817 => x"07070707",
+ 3818 => x"07070707",
+ 3819 => x"07070707",
+ 3820 => x"07070707",
+ 3821 => x"07070707",
+ 3822 => x"07070707",
+ 3823 => x"07070707",
+ 3824 => x"07070707",
+ 3825 => x"07070707",
+ 3826 => x"08080808",
+ 3827 => x"08080808",
+ 3828 => x"08080808",
+ 3829 => x"08080808",
+ 3830 => x"08080808",
+ 3831 => x"08080808",
+ 3832 => x"08080808",
+ 3833 => x"08080808",
+ 3834 => x"08080808",
+ 3835 => x"08080808",
+ 3836 => x"08080808",
+ 3837 => x"08080808",
+ 3838 => x"08080808",
+ 3839 => x"08080808",
+ 3840 => x"08080808",
+ 3841 => x"08080808",
+ 3842 => x"08080808",
+ 3843 => x"08080808",
+ 3844 => x"08080808",
+ 3845 => x"08080808",
+ 3846 => x"08080808",
+ 3847 => x"08080808",
+ 3848 => x"08080808",
+ 3849 => x"08080808",
+ 3850 => x"08080808",
+ 3851 => x"08080808",
+ 3852 => x"08080808",
+ 3853 => x"08080808",
+ 3854 => x"08080808",
+ 3855 => x"08080808",
+ 3856 => x"08080808",
+ 3857 => x"08080808",
+ 3858 => x"43000000",
+ 3859 => x"64756d6d",
+ 3860 => x"792e6578",
+ 3861 => x"65000000",
+ 3862 => x"00ffffff",
+ 3863 => x"ff00ffff",
+ 3864 => x"ffff00ff",
+ 3865 => x"ffffff00",
+ 3866 => x"00000000",
+ 3867 => x"00000000",
+ 3868 => x"00000000",
+ 3869 => x"00004458",
+ 3870 => x"0000000a",
+ 3871 => x"00000000",
+ 3872 => x"00000032",
+ 3873 => x"00000000",
+ 3874 => x"00000000",
+ 3875 => x"00000000",
+ 3876 => x"00000000",
+ 3877 => x"00000000",
+ 3878 => x"00000000",
+ 3879 => x"00000000",
+ 3880 => x"00000000",
+ 3881 => x"00000000",
+ 3882 => x"00000000",
+ 3883 => x"00000000",
+ 3884 => x"00000000",
+ 3885 => x"ffffffff",
+ 3886 => x"00000000",
+ 3887 => x"00020000",
+ 3888 => x"00000000",
+ 3889 => x"00000000",
+ 3890 => x"00003cc0",
+ 3891 => x"00003cc0",
+ 3892 => x"00003cc8",
+ 3893 => x"00003cc8",
+ 3894 => x"00003cd0",
+ 3895 => x"00003cd0",
+ 3896 => x"00003cd8",
+ 3897 => x"00003cd8",
+ 3898 => x"00003ce0",
+ 3899 => x"00003ce0",
+ 3900 => x"00003ce8",
+ 3901 => x"00003ce8",
+ 3902 => x"00003cf0",
+ 3903 => x"00003cf0",
+ 3904 => x"00003cf8",
+ 3905 => x"00003cf8",
+ 3906 => x"00003d00",
+ 3907 => x"00003d00",
+ 3908 => x"00003d08",
+ 3909 => x"00003d08",
+ 3910 => x"00003d10",
+ 3911 => x"00003d10",
+ 3912 => x"00003d18",
+ 3913 => x"00003d18",
+ 3914 => x"00003d20",
+ 3915 => x"00003d20",
+ 3916 => x"00003d28",
+ 3917 => x"00003d28",
+ 3918 => x"00003d30",
+ 3919 => x"00003d30",
+ 3920 => x"00003d38",
+ 3921 => x"00003d38",
+ 3922 => x"00003d40",
+ 3923 => x"00003d40",
+ 3924 => x"00003d48",
+ 3925 => x"00003d48",
+ 3926 => x"00003d50",
+ 3927 => x"00003d50",
+ 3928 => x"00003d58",
+ 3929 => x"00003d58",
+ 3930 => x"00003d60",
+ 3931 => x"00003d60",
+ 3932 => x"00003d68",
+ 3933 => x"00003d68",
+ 3934 => x"00003d70",
+ 3935 => x"00003d70",
+ 3936 => x"00003d78",
+ 3937 => x"00003d78",
+ 3938 => x"00003d80",
+ 3939 => x"00003d80",
+ 3940 => x"00003d88",
+ 3941 => x"00003d88",
+ 3942 => x"00003d90",
+ 3943 => x"00003d90",
+ 3944 => x"00003d98",
+ 3945 => x"00003d98",
+ 3946 => x"00003da0",
+ 3947 => x"00003da0",
+ 3948 => x"00003da8",
+ 3949 => x"00003da8",
+ 3950 => x"00003db0",
+ 3951 => x"00003db0",
+ 3952 => x"00003db8",
+ 3953 => x"00003db8",
+ 3954 => x"00003dc0",
+ 3955 => x"00003dc0",
+ 3956 => x"00003dc8",
+ 3957 => x"00003dc8",
+ 3958 => x"00003dd0",
+ 3959 => x"00003dd0",
+ 3960 => x"00003dd8",
+ 3961 => x"00003dd8",
+ 3962 => x"00003de0",
+ 3963 => x"00003de0",
+ 3964 => x"00003de8",
+ 3965 => x"00003de8",
+ 3966 => x"00003df0",
+ 3967 => x"00003df0",
+ 3968 => x"00003df8",
+ 3969 => x"00003df8",
+ 3970 => x"00003e00",
+ 3971 => x"00003e00",
+ 3972 => x"00003e08",
+ 3973 => x"00003e08",
+ 3974 => x"00003e10",
+ 3975 => x"00003e10",
+ 3976 => x"00003e18",
+ 3977 => x"00003e18",
+ 3978 => x"00003e20",
+ 3979 => x"00003e20",
+ 3980 => x"00003e28",
+ 3981 => x"00003e28",
+ 3982 => x"00003e30",
+ 3983 => x"00003e30",
+ 3984 => x"00003e38",
+ 3985 => x"00003e38",
+ 3986 => x"00003e40",
+ 3987 => x"00003e40",
+ 3988 => x"00003e48",
+ 3989 => x"00003e48",
+ 3990 => x"00003e50",
+ 3991 => x"00003e50",
+ 3992 => x"00003e58",
+ 3993 => x"00003e58",
+ 3994 => x"00003e60",
+ 3995 => x"00003e60",
+ 3996 => x"00003e68",
+ 3997 => x"00003e68",
+ 3998 => x"00003e70",
+ 3999 => x"00003e70",
+ 4000 => x"00003e78",
+ 4001 => x"00003e78",
+ 4002 => x"00003e80",
+ 4003 => x"00003e80",
+ 4004 => x"00003e88",
+ 4005 => x"00003e88",
+ 4006 => x"00003e90",
+ 4007 => x"00003e90",
+ 4008 => x"00003e98",
+ 4009 => x"00003e98",
+ 4010 => x"00003ea0",
+ 4011 => x"00003ea0",
+ 4012 => x"00003ea8",
+ 4013 => x"00003ea8",
+ 4014 => x"00003eb0",
+ 4015 => x"00003eb0",
+ 4016 => x"00003eb8",
+ 4017 => x"00003eb8",
+ 4018 => x"00003ec0",
+ 4019 => x"00003ec0",
+ 4020 => x"00003ec8",
+ 4021 => x"00003ec8",
+ 4022 => x"00003ed0",
+ 4023 => x"00003ed0",
+ 4024 => x"00003ed8",
+ 4025 => x"00003ed8",
+ 4026 => x"00003ee0",
+ 4027 => x"00003ee0",
+ 4028 => x"00003ee8",
+ 4029 => x"00003ee8",
+ 4030 => x"00003ef0",
+ 4031 => x"00003ef0",
+ 4032 => x"00003ef8",
+ 4033 => x"00003ef8",
+ 4034 => x"00003f00",
+ 4035 => x"00003f00",
+ 4036 => x"00003f08",
+ 4037 => x"00003f08",
+ 4038 => x"00003f10",
+ 4039 => x"00003f10",
+ 4040 => x"00003f18",
+ 4041 => x"00003f18",
+ 4042 => x"00003f20",
+ 4043 => x"00003f20",
+ 4044 => x"00003f28",
+ 4045 => x"00003f28",
+ 4046 => x"00003f30",
+ 4047 => x"00003f30",
+ 4048 => x"00003f38",
+ 4049 => x"00003f38",
+ 4050 => x"00003f40",
+ 4051 => x"00003f40",
+ 4052 => x"00003f48",
+ 4053 => x"00003f48",
+ 4054 => x"00003f50",
+ 4055 => x"00003f50",
+ 4056 => x"00003f58",
+ 4057 => x"00003f58",
+ 4058 => x"00003f60",
+ 4059 => x"00003f60",
+ 4060 => x"00003f68",
+ 4061 => x"00003f68",
+ 4062 => x"00003f70",
+ 4063 => x"00003f70",
+ 4064 => x"00003f78",
+ 4065 => x"00003f78",
+ 4066 => x"00003f80",
+ 4067 => x"00003f80",
+ 4068 => x"00003f88",
+ 4069 => x"00003f88",
+ 4070 => x"00003f90",
+ 4071 => x"00003f90",
+ 4072 => x"00003f98",
+ 4073 => x"00003f98",
+ 4074 => x"00003fa0",
+ 4075 => x"00003fa0",
+ 4076 => x"00003fa8",
+ 4077 => x"00003fa8",
+ 4078 => x"00003fb0",
+ 4079 => x"00003fb0",
+ 4080 => x"00003fb8",
+ 4081 => x"00003fb8",
+ 4082 => x"00003fc0",
+ 4083 => x"00003fc0",
+ 4084 => x"00003fc8",
+ 4085 => x"00003fc8",
+ 4086 => x"00003fd0",
+ 4087 => x"00003fd0",
+ 4088 => x"00003fd8",
+ 4089 => x"00003fd8",
+ 4090 => x"00003fe0",
+ 4091 => x"00003fe0",
+ 4092 => x"00003fe8",
+ 4093 => x"00003fe8",
+ 4094 => x"00003ff0",
+ 4095 => x"00003ff0",
+ 4096 => x"00003ff8",
+ 4097 => x"00003ff8",
+ 4098 => x"00004000",
+ 4099 => x"00004000",
+ 4100 => x"00004008",
+ 4101 => x"00004008",
+ 4102 => x"00004010",
+ 4103 => x"00004010",
+ 4104 => x"00004018",
+ 4105 => x"00004018",
+ 4106 => x"00004020",
+ 4107 => x"00004020",
+ 4108 => x"00004028",
+ 4109 => x"00004028",
+ 4110 => x"00004030",
+ 4111 => x"00004030",
+ 4112 => x"00004038",
+ 4113 => x"00004038",
+ 4114 => x"00004040",
+ 4115 => x"00004040",
+ 4116 => x"00004048",
+ 4117 => x"00004048",
+ 4118 => x"00004050",
+ 4119 => x"00004050",
+ 4120 => x"00004058",
+ 4121 => x"00004058",
+ 4122 => x"00004060",
+ 4123 => x"00004060",
+ 4124 => x"00004068",
+ 4125 => x"00004068",
+ 4126 => x"00004070",
+ 4127 => x"00004070",
+ 4128 => x"00004078",
+ 4129 => x"00004078",
+ 4130 => x"00004080",
+ 4131 => x"00004080",
+ 4132 => x"00004088",
+ 4133 => x"00004088",
+ 4134 => x"00004090",
+ 4135 => x"00004090",
+ 4136 => x"00004098",
+ 4137 => x"00004098",
+ 4138 => x"000040a0",
+ 4139 => x"000040a0",
+ 4140 => x"000040a8",
+ 4141 => x"000040a8",
+ 4142 => x"000040b0",
+ 4143 => x"000040b0",
+ 4144 => x"000040b8",
+ 4145 => x"000040b8",
+ 4146 => x"000040cc",
+ 4147 => x"00000000",
+ 4148 => x"00004334",
+ 4149 => x"00004390",
+ 4150 => x"000043ec",
+ 4151 => x"00000000",
+ 4152 => x"00000000",
+ 4153 => x"00000000",
+ 4154 => x"00000000",
+ 4155 => x"00000000",
+ 4156 => x"00000000",
+ 4157 => x"00000000",
+ 4158 => x"00000000",
+ 4159 => x"00000000",
+ 4160 => x"00003c48",
+ 4161 => x"00000000",
+ 4162 => x"00000000",
+ 4163 => x"00000000",
+ 4164 => x"00000000",
+ 4165 => x"00000000",
+ 4166 => x"00000000",
+ 4167 => x"00000000",
+ 4168 => x"00000000",
+ 4169 => x"00000000",
+ 4170 => x"00000000",
+ 4171 => x"00000000",
+ 4172 => x"00000000",
+ 4173 => x"00000000",
+ 4174 => x"00000000",
+ 4175 => x"00000000",
+ 4176 => x"00000000",
+ 4177 => x"00000000",
+ 4178 => x"00000000",
+ 4179 => x"00000000",
+ 4180 => x"00000000",
+ 4181 => x"00000000",
+ 4182 => x"00000000",
+ 4183 => x"00000000",
+ 4184 => x"00000000",
+ 4185 => x"00000000",
+ 4186 => x"00000000",
+ 4187 => x"00000000",
+ 4188 => x"00000000",
+ 4189 => x"00000001",
+ 4190 => x"330eabcd",
+ 4191 => x"1234e66d",
+ 4192 => x"deec0005",
+ 4193 => x"000b0000",
+ 4194 => x"00000000",
+ 4195 => x"00000000",
+ 4196 => x"00000000",
+ 4197 => x"00000000",
+ 4198 => x"00000000",
+ 4199 => x"00000000",
+ 4200 => x"00000000",
+ 4201 => x"00000000",
+ 4202 => x"00000000",
+ 4203 => x"00000000",
+ 4204 => x"00000000",
+ 4205 => x"00000000",
+ 4206 => x"00000000",
+ 4207 => x"00000000",
+ 4208 => x"00000000",
+ 4209 => x"00000000",
+ 4210 => x"00000000",
+ 4211 => x"00000000",
+ 4212 => x"00000000",
+ 4213 => x"00000000",
+ 4214 => x"00000000",
+ 4215 => x"00000000",
+ 4216 => x"00000000",
+ 4217 => x"00000000",
+ 4218 => x"00000000",
+ 4219 => x"00000000",
+ 4220 => x"00000000",
+ 4221 => x"00000000",
+ 4222 => x"00000000",
+ 4223 => x"00000000",
+ 4224 => x"00000000",
+ 4225 => x"00000000",
+ 4226 => x"00000000",
+ 4227 => x"00000000",
+ 4228 => x"00000000",
+ 4229 => x"00000000",
+ 4230 => x"00000000",
+ 4231 => x"00000000",
+ 4232 => x"00000000",
+ 4233 => x"00000000",
+ 4234 => x"00000000",
+ 4235 => x"00000000",
+ 4236 => x"00000000",
+ 4237 => x"00000000",
+ 4238 => x"00000000",
+ 4239 => x"00000000",
+ 4240 => x"00000000",
+ 4241 => x"00000000",
+ 4242 => x"00000000",
+ 4243 => x"00000000",
+ 4244 => x"00000000",
+ 4245 => x"00000000",
+ 4246 => x"00000000",
+ 4247 => x"00000000",
+ 4248 => x"00000000",
+ 4249 => x"00000000",
+ 4250 => x"00000000",
+ 4251 => x"00000000",
+ 4252 => x"00000000",
+ 4253 => x"00000000",
+ 4254 => x"00000000",
+ 4255 => x"00000000",
+ 4256 => x"00000000",
+ 4257 => x"00000000",
+ 4258 => x"00000000",
+ 4259 => x"00000000",
+ 4260 => x"00000000",
+ 4261 => x"00000000",
+ 4262 => x"00000000",
+ 4263 => x"00000000",
+ 4264 => x"00000000",
+ 4265 => x"00000000",
+ 4266 => x"00000000",
+ 4267 => x"00000000",
+ 4268 => x"00000000",
+ 4269 => x"00000000",
+ 4270 => x"00000000",
+ 4271 => x"00000000",
+ 4272 => x"00000000",
+ 4273 => x"00000000",
+ 4274 => x"00000000",
+ 4275 => x"00000000",
+ 4276 => x"00000000",
+ 4277 => x"00000000",
+ 4278 => x"00000000",
+ 4279 => x"00000000",
+ 4280 => x"00000000",
+ 4281 => x"00000000",
+ 4282 => x"00000000",
+ 4283 => x"00000000",
+ 4284 => x"00000000",
+ 4285 => x"00000000",
+ 4286 => x"00000000",
+ 4287 => x"00000000",
+ 4288 => x"00000000",
+ 4289 => x"00000000",
+ 4290 => x"00000000",
+ 4291 => x"00000000",
+ 4292 => x"00000000",
+ 4293 => x"00000000",
+ 4294 => x"00000000",
+ 4295 => x"00000000",
+ 4296 => x"00000000",
+ 4297 => x"00000000",
+ 4298 => x"00000000",
+ 4299 => x"00000000",
+ 4300 => x"00000000",
+ 4301 => x"00000000",
+ 4302 => x"00000000",
+ 4303 => x"00000000",
+ 4304 => x"00000000",
+ 4305 => x"00000000",
+ 4306 => x"00000000",
+ 4307 => x"00000000",
+ 4308 => x"00000000",
+ 4309 => x"00000000",
+ 4310 => x"00000000",
+ 4311 => x"00000000",
+ 4312 => x"00000000",
+ 4313 => x"00000000",
+ 4314 => x"00000000",
+ 4315 => x"00000000",
+ 4316 => x"00000000",
+ 4317 => x"00000000",
+ 4318 => x"00000000",
+ 4319 => x"00000000",
+ 4320 => x"00000000",
+ 4321 => x"00000000",
+ 4322 => x"00000000",
+ 4323 => x"00000000",
+ 4324 => x"00000000",
+ 4325 => x"00000000",
+ 4326 => x"00000000",
+ 4327 => x"00000000",
+ 4328 => x"00000000",
+ 4329 => x"00000000",
+ 4330 => x"00000000",
+ 4331 => x"00000000",
+ 4332 => x"00000000",
+ 4333 => x"00000000",
+ 4334 => x"00000000",
+ 4335 => x"00000000",
+ 4336 => x"00000000",
+ 4337 => x"00000000",
+ 4338 => x"00000000",
+ 4339 => x"00000000",
+ 4340 => x"00000000",
+ 4341 => x"00000000",
+ 4342 => x"00000000",
+ 4343 => x"00000000",
+ 4344 => x"00000000",
+ 4345 => x"00000000",
+ 4346 => x"00000000",
+ 4347 => x"00000000",
+ 4348 => x"00000000",
+ 4349 => x"00000000",
+ 4350 => x"00000000",
+ 4351 => x"00000000",
+ 4352 => x"00000000",
+ 4353 => x"00000000",
+ 4354 => x"00000000",
+ 4355 => x"00000000",
+ 4356 => x"00000000",
+ 4357 => x"00000000",
+ 4358 => x"00000000",
+ 4359 => x"00000000",
+ 4360 => x"00000000",
+ 4361 => x"00000000",
+ 4362 => x"00000000",
+ 4363 => x"00000000",
+ 4364 => x"00000000",
+ 4365 => x"00000000",
+ 4366 => x"00000000",
+ 4367 => x"00000000",
+ 4368 => x"00000000",
+ 4369 => x"00000000",
+ 4370 => x"00003c4c",
+ 4371 => x"ffffffff",
+ 4372 => x"00000000",
+ 4373 => x"ffffffff",
+ 4374 => x"00000000",
+ 4375 => x"00000000",
+
+others => x"00000000"
+);
+begin
+ busy_o <= re_i; -- we're done on the cycle after we serve the read request
+
+ do_ram:
+ process (clk_i)
+ variable iaddr : integer;
+ begin
+ if rising_edge(clk_i) then
+ if we_i='1' then
+ ram(to_integer(addr_i)) <= write_i;
+ end if;
+ addr_r <= addr_i;
+ end if;
+ end process do_ram;
+ read_o <= ram(to_integer(addr_r));
+end architecture Xilinx; -- Entity: SinglePortRAM
+
diff --git a/zpu/hdl/zealot/roms/dmips_dbram.vhdl b/zpu/hdl/zealot/roms/dmips_dbram.vhdl
new file mode 100644
index 0000000..32b6947
--- /dev/null
+++ b/zpu/hdl/zealot/roms/dmips_dbram.vhdl
@@ -0,0 +1,4485 @@
+------------------------------------------------------------------------------
+---- ----
+---- Dual Port RAM that maps to a Xilinx BRAM ----
+---- ----
+---- http://www.opencores.org/ ----
+---- ----
+---- Description: ----
+---- This is a program+data memory for the ZPU. It maps to a Xilinx BRAM ----
+---- ----
+---- To Do: ----
+---- - ----
+---- ----
+---- Author: ----
+---- - Øyvind Harboe, oyvind.harboe zylin.com ----
+---- - Salvador E. Tropea, salvador inti.gob.ar ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
+---- ----
+---- Distributed under the BSD license ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Design unit: DualPortRAM(Xilinx) (Entity and architecture) ----
+---- File name: rom.in.vhdl (template used) ----
+---- Note: None ----
+---- Limitations: None known ----
+---- Errors: None known ----
+---- Library: work ----
+---- Dependencies: IEEE.std_logic_1164 ----
+---- IEEE.numeric_std ----
+---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
+---- Language: VHDL ----
+---- Wishbone: No ----
+---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
+---- Text editor: SETEdit 0.5.x ----
+---- ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity DualPortRAM is
+ generic(
+ WORD_SIZE : integer:=32; -- Word Size 16/32
+ BYTE_BITS : integer:=2; -- Bits used to address bytes
+ BRAM_W : integer:=15); -- Address Width
+ port(
+ clk_i : in std_logic;
+ -- Port A
+ a_we_i : in std_logic;
+ a_addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS);
+ a_write_i : in unsigned(WORD_SIZE-1 downto 0);
+ a_read_o : out unsigned(WORD_SIZE-1 downto 0);
+ -- Port B
+ b_we_i : in std_logic;
+ b_addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS);
+ b_write_i : in unsigned(WORD_SIZE-1 downto 0);
+ b_read_o : out unsigned(WORD_SIZE-1 downto 0));
+end entity DualPortRAM;
+
+architecture Xilinx of DualPortRAM is
+ type ram_type is array(natural range 0 to ((2**BRAM_W)/4)-1) of unsigned(WORD_SIZE-1 downto 0);
+
+ shared variable ram : ram_type:=
+(
+ 0 => x"0b0b0b0b",
+ 1 => x"82700b0b",
+ 2 => x"80f8ec0c",
+ 3 => x"3a0b0b80",
+ 4 => x"e7ea0400",
+ 5 => x"00000000",
+ 6 => x"00000000",
+ 7 => x"00000000",
+ 8 => x"80088408",
+ 9 => x"88080b0b",
+ 10 => x"80e8b72d",
+ 11 => x"880c840c",
+ 12 => x"800c0400",
+ 13 => x"00000000",
+ 14 => x"00000000",
+ 15 => x"00000000",
+ 16 => x"71fd0608",
+ 17 => x"72830609",
+ 18 => x"81058205",
+ 19 => x"832b2a83",
+ 20 => x"ffff0652",
+ 21 => x"04000000",
+ 22 => x"00000000",
+ 23 => x"00000000",
+ 24 => x"71fd0608",
+ 25 => x"83ffff73",
+ 26 => x"83060981",
+ 27 => x"05820583",
+ 28 => x"2b2b0906",
+ 29 => x"7383ffff",
+ 30 => x"0b0b0b0b",
+ 31 => x"83a70400",
+ 32 => x"72098105",
+ 33 => x"72057373",
+ 34 => x"09060906",
+ 35 => x"73097306",
+ 36 => x"070a8106",
+ 37 => x"53510400",
+ 38 => x"00000000",
+ 39 => x"00000000",
+ 40 => x"72722473",
+ 41 => x"732e0753",
+ 42 => x"51040000",
+ 43 => x"00000000",
+ 44 => x"00000000",
+ 45 => x"00000000",
+ 46 => x"00000000",
+ 47 => x"00000000",
+ 48 => x"71737109",
+ 49 => x"71068106",
+ 50 => x"30720a10",
+ 51 => x"0a720a10",
+ 52 => x"0a31050a",
+ 53 => x"81065151",
+ 54 => x"53510400",
+ 55 => x"00000000",
+ 56 => x"72722673",
+ 57 => x"732e0753",
+ 58 => x"51040000",
+ 59 => x"00000000",
+ 60 => x"00000000",
+ 61 => x"00000000",
+ 62 => x"00000000",
+ 63 => x"00000000",
+ 64 => x"00000000",
+ 65 => x"00000000",
+ 66 => x"00000000",
+ 67 => x"00000000",
+ 68 => x"00000000",
+ 69 => x"00000000",
+ 70 => x"00000000",
+ 71 => x"00000000",
+ 72 => x"0b0b0b88",
+ 73 => x"c4040000",
+ 74 => x"00000000",
+ 75 => x"00000000",
+ 76 => x"00000000",
+ 77 => x"00000000",
+ 78 => x"00000000",
+ 79 => x"00000000",
+ 80 => x"720a722b",
+ 81 => x"0a535104",
+ 82 => x"00000000",
+ 83 => x"00000000",
+ 84 => x"00000000",
+ 85 => x"00000000",
+ 86 => x"00000000",
+ 87 => x"00000000",
+ 88 => x"72729f06",
+ 89 => x"0981050b",
+ 90 => x"0b0b88a7",
+ 91 => x"05040000",
+ 92 => x"00000000",
+ 93 => x"00000000",
+ 94 => x"00000000",
+ 95 => x"00000000",
+ 96 => x"72722aff",
+ 97 => x"739f062a",
+ 98 => x"0974090a",
+ 99 => x"8106ff05",
+ 100 => x"06075351",
+ 101 => x"04000000",
+ 102 => x"00000000",
+ 103 => x"00000000",
+ 104 => x"71715351",
+ 105 => x"020d0406",
+ 106 => x"73830609",
+ 107 => x"81058205",
+ 108 => x"832b0b2b",
+ 109 => x"0772fc06",
+ 110 => x"0c515104",
+ 111 => x"00000000",
+ 112 => x"72098105",
+ 113 => x"72050970",
+ 114 => x"81050906",
+ 115 => x"0a810653",
+ 116 => x"51040000",
+ 117 => x"00000000",
+ 118 => x"00000000",
+ 119 => x"00000000",
+ 120 => x"72098105",
+ 121 => x"72050970",
+ 122 => x"81050906",
+ 123 => x"0a098106",
+ 124 => x"53510400",
+ 125 => x"00000000",
+ 126 => x"00000000",
+ 127 => x"00000000",
+ 128 => x"71098105",
+ 129 => x"52040000",
+ 130 => x"00000000",
+ 131 => x"00000000",
+ 132 => x"00000000",
+ 133 => x"00000000",
+ 134 => x"00000000",
+ 135 => x"00000000",
+ 136 => x"72720981",
+ 137 => x"05055351",
+ 138 => x"04000000",
+ 139 => x"00000000",
+ 140 => x"00000000",
+ 141 => x"00000000",
+ 142 => x"00000000",
+ 143 => x"00000000",
+ 144 => x"72097206",
+ 145 => x"73730906",
+ 146 => x"07535104",
+ 147 => x"00000000",
+ 148 => x"00000000",
+ 149 => x"00000000",
+ 150 => x"00000000",
+ 151 => x"00000000",
+ 152 => x"71fc0608",
+ 153 => x"72830609",
+ 154 => x"81058305",
+ 155 => x"1010102a",
+ 156 => x"81ff0652",
+ 157 => x"04000000",
+ 158 => x"00000000",
+ 159 => x"00000000",
+ 160 => x"71fc0608",
+ 161 => x"0b0b80f8",
+ 162 => x"d8738306",
+ 163 => x"10100508",
+ 164 => x"060b0b0b",
+ 165 => x"88aa0400",
+ 166 => x"00000000",
+ 167 => x"00000000",
+ 168 => x"80088408",
+ 169 => x"88087575",
+ 170 => x"0b0b80ce",
+ 171 => x"b62d5050",
+ 172 => x"80085688",
+ 173 => x"0c840c80",
+ 174 => x"0c510400",
+ 175 => x"00000000",
+ 176 => x"80088408",
+ 177 => x"88087575",
+ 178 => x"0b0b80cf",
+ 179 => x"e82d5050",
+ 180 => x"80085688",
+ 181 => x"0c840c80",
+ 182 => x"0c510400",
+ 183 => x"00000000",
+ 184 => x"72097081",
+ 185 => x"0509060a",
+ 186 => x"8106ff05",
+ 187 => x"70547106",
+ 188 => x"73097274",
+ 189 => x"05ff0506",
+ 190 => x"07515151",
+ 191 => x"04000000",
+ 192 => x"72097081",
+ 193 => x"0509060a",
+ 194 => x"098106ff",
+ 195 => x"05705471",
+ 196 => x"06730972",
+ 197 => x"7405ff05",
+ 198 => x"06075151",
+ 199 => x"51040000",
+ 200 => x"05ff0504",
+ 201 => x"00000000",
+ 202 => x"00000000",
+ 203 => x"00000000",
+ 204 => x"00000000",
+ 205 => x"00000000",
+ 206 => x"00000000",
+ 207 => x"00000000",
+ 208 => x"810b0b0b",
+ 209 => x"80f8e80c",
+ 210 => x"51040000",
+ 211 => x"00000000",
+ 212 => x"00000000",
+ 213 => x"00000000",
+ 214 => x"00000000",
+ 215 => x"00000000",
+ 216 => x"71810552",
+ 217 => x"04000000",
+ 218 => x"00000000",
+ 219 => x"00000000",
+ 220 => x"00000000",
+ 221 => x"00000000",
+ 222 => x"00000000",
+ 223 => x"00000000",
+ 224 => x"00000000",
+ 225 => x"00000000",
+ 226 => x"00000000",
+ 227 => x"00000000",
+ 228 => x"00000000",
+ 229 => x"00000000",
+ 230 => x"00000000",
+ 231 => x"00000000",
+ 232 => x"02840572",
+ 233 => x"10100552",
+ 234 => x"04000000",
+ 235 => x"00000000",
+ 236 => x"00000000",
+ 237 => x"00000000",
+ 238 => x"00000000",
+ 239 => x"00000000",
+ 240 => x"00000000",
+ 241 => x"00000000",
+ 242 => x"00000000",
+ 243 => x"00000000",
+ 244 => x"00000000",
+ 245 => x"00000000",
+ 246 => x"00000000",
+ 247 => x"00000000",
+ 248 => x"717105ff",
+ 249 => x"05715351",
+ 250 => x"020d0400",
+ 251 => x"00000000",
+ 252 => x"00000000",
+ 253 => x"00000000",
+ 254 => x"00000000",
+ 255 => x"00000000",
+ 256 => x"83803f80",
+ 257 => x"e2953f04",
+ 258 => x"10101010",
+ 259 => x"10101010",
+ 260 => x"10101010",
+ 261 => x"10101010",
+ 262 => x"10101010",
+ 263 => x"10101010",
+ 264 => x"10101010",
+ 265 => x"10101053",
+ 266 => x"51047381",
+ 267 => x"ff067383",
+ 268 => x"06098105",
+ 269 => x"83051010",
+ 270 => x"102b0772",
+ 271 => x"fc060c51",
+ 272 => x"51043c04",
+ 273 => x"72728072",
+ 274 => x"8106ff05",
+ 275 => x"09720605",
+ 276 => x"71105272",
+ 277 => x"0a100a53",
+ 278 => x"72ed3851",
+ 279 => x"51535104",
+ 280 => x"ff3d0d0b",
+ 281 => x"0b8188e0",
+ 282 => x"08527108",
+ 283 => x"70882a81",
+ 284 => x"32708106",
+ 285 => x"51515170",
+ 286 => x"f1387372",
+ 287 => x"0c833d0d",
+ 288 => x"0480f8e8",
+ 289 => x"08802ea4",
+ 290 => x"3880f8ec",
+ 291 => x"08822ebd",
+ 292 => x"38838080",
+ 293 => x"0b0b0b81",
+ 294 => x"88e00c82",
+ 295 => x"a0800b81",
+ 296 => x"88e40c82",
+ 297 => x"90800b81",
+ 298 => x"88e80c04",
+ 299 => x"f8808080",
+ 300 => x"a40b0b0b",
+ 301 => x"8188e00c",
+ 302 => x"f8808082",
+ 303 => x"800b8188",
+ 304 => x"e40cf880",
+ 305 => x"8084800b",
+ 306 => x"8188e80c",
+ 307 => x"0480c0a8",
+ 308 => x"808c0b0b",
+ 309 => x"0b8188e0",
+ 310 => x"0c80c0a8",
+ 311 => x"80940b81",
+ 312 => x"88e40c0b",
+ 313 => x"0b80eac8",
+ 314 => x"0b8188e8",
+ 315 => x"0c04f23d",
+ 316 => x"0d608188",
+ 317 => x"e408565d",
+ 318 => x"82750c80",
+ 319 => x"59805a80",
+ 320 => x"0b8f3d5d",
+ 321 => x"5b7a1010",
+ 322 => x"15700871",
+ 323 => x"08719f2c",
+ 324 => x"7e852b58",
+ 325 => x"55557d53",
+ 326 => x"59579d94",
+ 327 => x"3f7d7f7a",
+ 328 => x"72077c72",
+ 329 => x"07717160",
+ 330 => x"8105415f",
+ 331 => x"5d5b5957",
+ 332 => x"55817b27",
+ 333 => x"8f38767d",
+ 334 => x"0c77841e",
+ 335 => x"0c7c800c",
+ 336 => x"903d0d04",
+ 337 => x"8188e408",
+ 338 => x"55ffba39",
+ 339 => x"ff3d0d81",
+ 340 => x"88ec3351",
+ 341 => x"70a73880",
+ 342 => x"f8f40870",
+ 343 => x"08525270",
+ 344 => x"802e9438",
+ 345 => x"841280f8",
+ 346 => x"f40c702d",
+ 347 => x"80f8f408",
+ 348 => x"70085252",
+ 349 => x"70ee3881",
+ 350 => x"0b8188ec",
+ 351 => x"34833d0d",
+ 352 => x"0404803d",
+ 353 => x"0d0b0b81",
+ 354 => x"88dc0880",
+ 355 => x"2e8e380b",
+ 356 => x"0b0b0b80",
+ 357 => x"0b802e09",
+ 358 => x"81068538",
+ 359 => x"823d0d04",
+ 360 => x"0b0b8188",
+ 361 => x"dc510b0b",
+ 362 => x"0bf4d53f",
+ 363 => x"823d0d04",
+ 364 => x"04ff3d0d",
+ 365 => x"028f0533",
+ 366 => x"52718a2e",
+ 367 => x"8a387151",
+ 368 => x"fd9e3f83",
+ 369 => x"3d0d048d",
+ 370 => x"51fd953f",
+ 371 => x"7151fd90",
+ 372 => x"3f833d0d",
+ 373 => x"04ce3d0d",
+ 374 => x"b53d7070",
+ 375 => x"84055208",
+ 376 => x"8bb15c56",
+ 377 => x"a53d5e5c",
+ 378 => x"80757081",
+ 379 => x"05573376",
+ 380 => x"5b555873",
+ 381 => x"782e80c1",
+ 382 => x"388e3d5b",
+ 383 => x"73a52e09",
+ 384 => x"810680c5",
+ 385 => x"38787081",
+ 386 => x"055a3354",
+ 387 => x"7380e42e",
+ 388 => x"81b63873",
+ 389 => x"80e42480",
+ 390 => x"c6387380",
+ 391 => x"e32ea138",
+ 392 => x"8052a551",
+ 393 => x"792d8052",
+ 394 => x"7351792d",
+ 395 => x"82185878",
+ 396 => x"7081055a",
+ 397 => x"335473c4",
+ 398 => x"3877800c",
+ 399 => x"b43d0d04",
+ 400 => x"7b841d83",
+ 401 => x"1233565d",
+ 402 => x"57805273",
+ 403 => x"51792d81",
+ 404 => x"18797081",
+ 405 => x"055b3355",
+ 406 => x"5873ffa0",
+ 407 => x"38db3973",
+ 408 => x"80f32e09",
+ 409 => x"8106ffb8",
+ 410 => x"387b841d",
+ 411 => x"7108595d",
+ 412 => x"56807733",
+ 413 => x"55567376",
+ 414 => x"2e8d3881",
+ 415 => x"16701870",
+ 416 => x"33575556",
+ 417 => x"74f538ff",
+ 418 => x"16558076",
+ 419 => x"25ffa038",
+ 420 => x"76708105",
+ 421 => x"58335480",
+ 422 => x"52735179",
+ 423 => x"2d811875",
+ 424 => x"ff175757",
+ 425 => x"58807625",
+ 426 => x"ff853876",
+ 427 => x"70810558",
+ 428 => x"33548052",
+ 429 => x"7351792d",
+ 430 => x"811875ff",
+ 431 => x"17575758",
+ 432 => x"758024cc",
+ 433 => x"38fee839",
+ 434 => x"7b841d71",
+ 435 => x"0870719f",
+ 436 => x"2c595359",
+ 437 => x"5d568075",
+ 438 => x"24819338",
+ 439 => x"757d7c58",
+ 440 => x"56548057",
+ 441 => x"73772e09",
+ 442 => x"8106b638",
+ 443 => x"b07b3402",
+ 444 => x"b505567a",
+ 445 => x"762e9738",
+ 446 => x"ff165675",
+ 447 => x"33757081",
+ 448 => x"05573481",
+ 449 => x"17577a76",
+ 450 => x"2e098106",
+ 451 => x"eb388075",
+ 452 => x"34767dff",
+ 453 => x"12575856",
+ 454 => x"758024fe",
+ 455 => x"f338fe8f",
+ 456 => x"398a5273",
+ 457 => x"5180c1c0",
+ 458 => x"3f800880",
+ 459 => x"eacc0533",
+ 460 => x"76708105",
+ 461 => x"58348a52",
+ 462 => x"7351bffa",
+ 463 => x"3f800854",
+ 464 => x"8008802e",
+ 465 => x"ffad388a",
+ 466 => x"52735180",
+ 467 => x"c19a3f80",
+ 468 => x"0880eacc",
+ 469 => x"05337670",
+ 470 => x"81055834",
+ 471 => x"8a527351",
+ 472 => x"bfd43f80",
+ 473 => x"08548008",
+ 474 => x"ffb738ff",
+ 475 => x"86397452",
+ 476 => x"7653b43d",
+ 477 => x"ffb80551",
+ 478 => x"978a3fa3",
+ 479 => x"3d0856fe",
+ 480 => x"db39803d",
+ 481 => x"0d80c10b",
+ 482 => x"81d7b834",
+ 483 => x"800b81d9",
+ 484 => x"940c7080",
+ 485 => x"0c823d0d",
+ 486 => x"04ff3d0d",
+ 487 => x"800b81d7",
+ 488 => x"b8335252",
+ 489 => x"7080c12e",
+ 490 => x"99387181",
+ 491 => x"d9940807",
+ 492 => x"81d9940c",
+ 493 => x"80c20b81",
+ 494 => x"d7bc3470",
+ 495 => x"800c833d",
+ 496 => x"0d04810b",
+ 497 => x"81d99408",
+ 498 => x"0781d994",
+ 499 => x"0c80c20b",
+ 500 => x"81d7bc34",
+ 501 => x"70800c83",
+ 502 => x"3d0d04fd",
+ 503 => x"3d0d7570",
+ 504 => x"088a0553",
+ 505 => x"5381d7b8",
+ 506 => x"33517080",
+ 507 => x"c12e8b38",
+ 508 => x"73f33870",
+ 509 => x"800c853d",
+ 510 => x"0d04ff12",
+ 511 => x"7081d7b4",
+ 512 => x"0831740c",
+ 513 => x"800c853d",
+ 514 => x"0d04fc3d",
+ 515 => x"0d81d7c0",
+ 516 => x"08557480",
+ 517 => x"2e8c3876",
+ 518 => x"7508710c",
+ 519 => x"81d7c008",
+ 520 => x"56548c15",
+ 521 => x"5381d7b4",
+ 522 => x"08528a51",
+ 523 => x"8fe73f73",
+ 524 => x"800c863d",
+ 525 => x"0d04fb3d",
+ 526 => x"0d777008",
+ 527 => x"5656b053",
+ 528 => x"81d7c008",
+ 529 => x"52745180",
+ 530 => x"cdff3f85",
+ 531 => x"0b8c170c",
+ 532 => x"850b8c16",
+ 533 => x"0c750875",
+ 534 => x"0c81d7c0",
+ 535 => x"08547380",
+ 536 => x"2e8a3873",
+ 537 => x"08750c81",
+ 538 => x"d7c00854",
+ 539 => x"8c145381",
+ 540 => x"d7b40852",
+ 541 => x"8a518f9d",
+ 542 => x"3f841508",
+ 543 => x"ad38860b",
+ 544 => x"8c160c88",
+ 545 => x"15528816",
+ 546 => x"08518ea9",
+ 547 => x"3f81d7c0",
+ 548 => x"08700876",
+ 549 => x"0c548c15",
+ 550 => x"7054548a",
+ 551 => x"52730851",
+ 552 => x"8ef33f73",
+ 553 => x"800c873d",
+ 554 => x"0d047508",
+ 555 => x"54b05373",
+ 556 => x"52755180",
+ 557 => x"cd933f73",
+ 558 => x"800c873d",
+ 559 => x"0d04d93d",
+ 560 => x"0d80f980",
+ 561 => x"0b8188e8",
+ 562 => x"0cb05180",
+ 563 => x"c0e43f80",
+ 564 => x"0881d7b0",
+ 565 => x"0cb05180",
+ 566 => x"c0d83f80",
+ 567 => x"0881d7c0",
+ 568 => x"0c81d7b0",
+ 569 => x"0880080c",
+ 570 => x"800b8008",
+ 571 => x"84050c82",
+ 572 => x"0b800888",
+ 573 => x"050ca80b",
+ 574 => x"80088c05",
+ 575 => x"0c9f5380",
+ 576 => x"ead85280",
+ 577 => x"08900551",
+ 578 => x"80ccbe3f",
+ 579 => x"a13d5e9f",
+ 580 => x"5380eaf8",
+ 581 => x"527d5180",
+ 582 => x"ccaf3f8a",
+ 583 => x"0b8195f4",
+ 584 => x"0c80f59c",
+ 585 => x"51f9ae3f",
+ 586 => x"80eb9851",
+ 587 => x"f9a73f80",
+ 588 => x"f59c51f9",
+ 589 => x"a03f80f8",
+ 590 => x"fc08802e",
+ 591 => x"89d73880",
+ 592 => x"ebc851f9",
+ 593 => x"903f80f5",
+ 594 => x"9c51f989",
+ 595 => x"3f80f8f8",
+ 596 => x"085280eb",
+ 597 => x"f451f8fd",
+ 598 => x"3f818990",
+ 599 => x"5180d5da",
+ 600 => x"3f810b9a",
+ 601 => x"3d5e5b80",
+ 602 => x"0b80f8f8",
+ 603 => x"082582d6",
+ 604 => x"38903d5f",
+ 605 => x"80c10b81",
+ 606 => x"d7b83481",
+ 607 => x"0b81d994",
+ 608 => x"0c80c20b",
+ 609 => x"81d7bc34",
+ 610 => x"8240835a",
+ 611 => x"9f5380ec",
+ 612 => x"a4527c51",
+ 613 => x"80cbb23f",
+ 614 => x"8141807d",
+ 615 => x"537e5256",
+ 616 => x"8e973f80",
+ 617 => x"08762e09",
+ 618 => x"81068338",
+ 619 => x"81567581",
+ 620 => x"d9940c7f",
+ 621 => x"70585675",
+ 622 => x"8325a238",
+ 623 => x"75101016",
+ 624 => x"fd0542a9",
+ 625 => x"3dffa405",
+ 626 => x"53835276",
+ 627 => x"518cc63f",
+ 628 => x"7f810570",
+ 629 => x"41705856",
+ 630 => x"837624e0",
+ 631 => x"38615475",
+ 632 => x"53818998",
+ 633 => x"5281d7cc",
+ 634 => x"518cba3f",
+ 635 => x"81d7c008",
+ 636 => x"70085858",
+ 637 => x"b0537752",
+ 638 => x"765180ca",
+ 639 => x"cc3f850b",
+ 640 => x"8c190c85",
+ 641 => x"0b8c180c",
+ 642 => x"7708770c",
+ 643 => x"81d7c008",
+ 644 => x"5675802e",
+ 645 => x"8a387508",
+ 646 => x"770c81d7",
+ 647 => x"c008568c",
+ 648 => x"165381d7",
+ 649 => x"b408528a",
+ 650 => x"518bea3f",
+ 651 => x"84170887",
+ 652 => x"eb38860b",
+ 653 => x"8c180c88",
+ 654 => x"17528818",
+ 655 => x"08518af5",
+ 656 => x"3f81d7c0",
+ 657 => x"08700878",
+ 658 => x"0c568c17",
+ 659 => x"7054598a",
+ 660 => x"52780851",
+ 661 => x"8bbf3f80",
+ 662 => x"c10b81d7",
+ 663 => x"bc335757",
+ 664 => x"767626a2",
+ 665 => x"3880c352",
+ 666 => x"76518ca3",
+ 667 => x"3f800861",
+ 668 => x"2e89e638",
+ 669 => x"81177081",
+ 670 => x"ff0681d7",
+ 671 => x"bc335858",
+ 672 => x"58757727",
+ 673 => x"e0387960",
+ 674 => x"29627054",
+ 675 => x"71535b59",
+ 676 => x"b9a43f80",
+ 677 => x"0840787a",
+ 678 => x"31708729",
+ 679 => x"80083180",
+ 680 => x"088a0581",
+ 681 => x"d7b83381",
+ 682 => x"d7b4085e",
+ 683 => x"5b525a56",
+ 684 => x"7780c12e",
+ 685 => x"89d0387b",
+ 686 => x"f738811b",
+ 687 => x"5b80f8f8",
+ 688 => x"087b25fd",
+ 689 => x"af3881d7",
+ 690 => x"a85180d2",
+ 691 => x"ed3f80ec",
+ 692 => x"c451f681",
+ 693 => x"3f80f59c",
+ 694 => x"51f5fa3f",
+ 695 => x"80ecd451",
+ 696 => x"f5f33f80",
+ 697 => x"f59c51f5",
+ 698 => x"ec3f81d7",
+ 699 => x"b4085280",
+ 700 => x"ed8c51f5",
+ 701 => x"e03f8552",
+ 702 => x"80eda851",
+ 703 => x"f5d73f81",
+ 704 => x"d9940852",
+ 705 => x"80edc451",
+ 706 => x"f5cb3f81",
+ 707 => x"5280eda8",
+ 708 => x"51f5c23f",
+ 709 => x"81d7b833",
+ 710 => x"5280ede0",
+ 711 => x"51f5b63f",
+ 712 => x"80c15280",
+ 713 => x"edfc51f5",
+ 714 => x"ac3f81d7",
+ 715 => x"bc335280",
+ 716 => x"ee9851f5",
+ 717 => x"a03f80c2",
+ 718 => x"5280edfc",
+ 719 => x"51f5963f",
+ 720 => x"81d7ec08",
+ 721 => x"5280eeb4",
+ 722 => x"51f58a3f",
+ 723 => x"875280ed",
+ 724 => x"a851f581",
+ 725 => x"3f8195f4",
+ 726 => x"085280ee",
+ 727 => x"d051f4f5",
+ 728 => x"3f80eeec",
+ 729 => x"51f4ee3f",
+ 730 => x"80ef9851",
+ 731 => x"f4e73f81",
+ 732 => x"d7c00870",
+ 733 => x"08535a80",
+ 734 => x"efa451f4",
+ 735 => x"d83f80ef",
+ 736 => x"c051f4d1",
+ 737 => x"3f81d7c0",
+ 738 => x"08841108",
+ 739 => x"535680ef",
+ 740 => x"f451f4c1",
+ 741 => x"3f805280",
+ 742 => x"eda851f4",
+ 743 => x"b83f81d7",
+ 744 => x"c0088811",
+ 745 => x"08535880",
+ 746 => x"f09051f4",
+ 747 => x"a83f8252",
+ 748 => x"80eda851",
+ 749 => x"f49f3f81",
+ 750 => x"d7c0088c",
+ 751 => x"11085357",
+ 752 => x"80f0ac51",
+ 753 => x"f48f3f91",
+ 754 => x"5280eda8",
+ 755 => x"51f4863f",
+ 756 => x"81d7c008",
+ 757 => x"90055280",
+ 758 => x"f0c851f3",
+ 759 => x"f83f80f0",
+ 760 => x"e451f3f1",
+ 761 => x"3f80f19c",
+ 762 => x"51f3ea3f",
+ 763 => x"81d7b008",
+ 764 => x"7008535f",
+ 765 => x"80efa451",
+ 766 => x"f3db3f80",
+ 767 => x"f1b051f3",
+ 768 => x"d43f81d7",
+ 769 => x"b0088411",
+ 770 => x"08535b80",
+ 771 => x"eff451f3",
+ 772 => x"c43f8052",
+ 773 => x"80eda851",
+ 774 => x"f3bb3f81",
+ 775 => x"d7b00888",
+ 776 => x"1108535c",
+ 777 => x"80f09051",
+ 778 => x"f3ab3f81",
+ 779 => x"5280eda8",
+ 780 => x"51f3a23f",
+ 781 => x"81d7b008",
+ 782 => x"8c110853",
+ 783 => x"5a80f0ac",
+ 784 => x"51f3923f",
+ 785 => x"925280ed",
+ 786 => x"a851f389",
+ 787 => x"3f81d7b0",
+ 788 => x"08900552",
+ 789 => x"80f0c851",
+ 790 => x"f2fb3f80",
+ 791 => x"f0e451f2",
+ 792 => x"f43f7f52",
+ 793 => x"80f1f051",
+ 794 => x"f2eb3f85",
+ 795 => x"5280eda8",
+ 796 => x"51f2e23f",
+ 797 => x"785280f2",
+ 798 => x"8c51f2d9",
+ 799 => x"3f8d5280",
+ 800 => x"eda851f2",
+ 801 => x"d03f6152",
+ 802 => x"80f2a851",
+ 803 => x"f2c73f87",
+ 804 => x"5280eda8",
+ 805 => x"51f2be3f",
+ 806 => x"605280f2",
+ 807 => x"c451f2b5",
+ 808 => x"3f815280",
+ 809 => x"eda851f2",
+ 810 => x"ac3f7d52",
+ 811 => x"80f2e051",
+ 812 => x"f2a33f80",
+ 813 => x"f2fc51f2",
+ 814 => x"9c3f7c52",
+ 815 => x"80f3b451",
+ 816 => x"f2933f80",
+ 817 => x"f3d051f2",
+ 818 => x"8c3f80f5",
+ 819 => x"9c51f285",
+ 820 => x"3f81d7a8",
+ 821 => x"0881d7ac",
+ 822 => x"08818990",
+ 823 => x"08818994",
+ 824 => x"08727131",
+ 825 => x"70742675",
+ 826 => x"74317072",
+ 827 => x"31818988",
+ 828 => x"0c444481",
+ 829 => x"898c0c81",
+ 830 => x"898c0856",
+ 831 => x"80f48855",
+ 832 => x"5c595758",
+ 833 => x"f1cf3f81",
+ 834 => x"89880856",
+ 835 => x"80762582",
+ 836 => x"a43880f8",
+ 837 => x"f8087071",
+ 838 => x"9f2c9a3d",
+ 839 => x"53565681",
+ 840 => x"89880881",
+ 841 => x"898c0841",
+ 842 => x"537f5470",
+ 843 => x"525a8ef6",
+ 844 => x"3f66685f",
+ 845 => x"8188f80c",
+ 846 => x"7d8188fc",
+ 847 => x"0c80f8f8",
+ 848 => x"08709f2c",
+ 849 => x"58568058",
+ 850 => x"bd84c078",
+ 851 => x"55557652",
+ 852 => x"75537951",
+ 853 => x"87d23f95",
+ 854 => x"3d818988",
+ 855 => x"0881898c",
+ 856 => x"0841557f",
+ 857 => x"56676940",
+ 858 => x"537e5470",
+ 859 => x"525c8eb6",
+ 860 => x"3f64665e",
+ 861 => x"8189800c",
+ 862 => x"7c818984",
+ 863 => x"0c80f8f8",
+ 864 => x"08709f2c",
+ 865 => x"40588057",
+ 866 => x"83dceb94",
+ 867 => x"80775555",
+ 868 => x"7e527753",
+ 869 => x"7b518790",
+ 870 => x"3f64665d",
+ 871 => x"5b805e8d",
+ 872 => x"dd7e5555",
+ 873 => x"81898808",
+ 874 => x"81898c08",
+ 875 => x"59527753",
+ 876 => x"795186f4",
+ 877 => x"3f666840",
+ 878 => x"547e557a",
+ 879 => x"527b53a9",
+ 880 => x"3dffa805",
+ 881 => x"518ddf3f",
+ 882 => x"62645e81",
+ 883 => x"d7c40c7c",
+ 884 => x"81d7c80c",
+ 885 => x"80f49851",
+ 886 => x"effb3f81",
+ 887 => x"88fc0852",
+ 888 => x"80f4c851",
+ 889 => x"efef3f80",
+ 890 => x"f4d051ef",
+ 891 => x"e83f8189",
+ 892 => x"84085280",
+ 893 => x"f4c851ef",
+ 894 => x"dc3f81d7",
+ 895 => x"c8085280",
+ 896 => x"f58051ef",
+ 897 => x"d03f80f5",
+ 898 => x"9c51efc9",
+ 899 => x"3f800b80",
+ 900 => x"0ca93d0d",
+ 901 => x"0480f5a0",
+ 902 => x"51f6a839",
+ 903 => x"770857b0",
+ 904 => x"53765277",
+ 905 => x"5180c2a1",
+ 906 => x"3f80c10b",
+ 907 => x"81d7bc33",
+ 908 => x"5757f8ac",
+ 909 => x"39758a38",
+ 910 => x"81898c08",
+ 911 => x"8126fdd2",
+ 912 => x"3880f5d0",
+ 913 => x"51ef8e3f",
+ 914 => x"80f68851",
+ 915 => x"ef873f80",
+ 916 => x"f59c51ef",
+ 917 => x"803f80f8",
+ 918 => x"f8087071",
+ 919 => x"9f2c9a3d",
+ 920 => x"53565681",
+ 921 => x"89880881",
+ 922 => x"898c0841",
+ 923 => x"537f5470",
+ 924 => x"525a8cb2",
+ 925 => x"3f66685f",
+ 926 => x"8188f80c",
+ 927 => x"7d8188fc",
+ 928 => x"0c80f8f8",
+ 929 => x"08709f2c",
+ 930 => x"58568058",
+ 931 => x"bd84c078",
+ 932 => x"55557652",
+ 933 => x"75537951",
+ 934 => x"858e3f95",
+ 935 => x"3d818988",
+ 936 => x"0881898c",
+ 937 => x"0841557f",
+ 938 => x"56676940",
+ 939 => x"537e5470",
+ 940 => x"525c8bf2",
+ 941 => x"3f64665e",
+ 942 => x"8189800c",
+ 943 => x"7c818984",
+ 944 => x"0c80f8f8",
+ 945 => x"08709f2c",
+ 946 => x"40588057",
+ 947 => x"83dceb94",
+ 948 => x"80775555",
+ 949 => x"7e527753",
+ 950 => x"7b5184cc",
+ 951 => x"3f64665d",
+ 952 => x"5b805e8d",
+ 953 => x"dd7e5555",
+ 954 => x"81898808",
+ 955 => x"81898c08",
+ 956 => x"59527753",
+ 957 => x"795184b0",
+ 958 => x"3f666840",
+ 959 => x"547e557a",
+ 960 => x"527b53a9",
+ 961 => x"3dffa805",
+ 962 => x"518b9b3f",
+ 963 => x"62645e81",
+ 964 => x"d7c40c7c",
+ 965 => x"81d7c80c",
+ 966 => x"80f49851",
+ 967 => x"edb73f81",
+ 968 => x"88fc0852",
+ 969 => x"80f4c851",
+ 970 => x"edab3f80",
+ 971 => x"f4d051ed",
+ 972 => x"a43f8189",
+ 973 => x"84085280",
+ 974 => x"f4c851ed",
+ 975 => x"983f81d7",
+ 976 => x"c8085280",
+ 977 => x"f58051ed",
+ 978 => x"8c3f80f5",
+ 979 => x"9c51ed85",
+ 980 => x"3f800b80",
+ 981 => x"0ca93d0d",
+ 982 => x"04a93dff",
+ 983 => x"a0055280",
+ 984 => x"5180d23f",
+ 985 => x"9f5380f6",
+ 986 => x"a8527c51",
+ 987 => x"bfdb3f7a",
+ 988 => x"7b81d7b4",
+ 989 => x"0c811870",
+ 990 => x"81ff0681",
+ 991 => x"d7bc3359",
+ 992 => x"59595af5",
+ 993 => x"fc39ff16",
+ 994 => x"707b3160",
+ 995 => x"0c5c800b",
+ 996 => x"811c5c5c",
+ 997 => x"80f8f808",
+ 998 => x"7b25f3d8",
+ 999 => x"38f6a739",
+ 1000 => x"ff3d0d73",
+ 1001 => x"82327030",
+ 1002 => x"70720780",
+ 1003 => x"25800c52",
+ 1004 => x"52833d0d",
+ 1005 => x"04fe3d0d",
+ 1006 => x"74767153",
+ 1007 => x"54527182",
+ 1008 => x"2e833883",
+ 1009 => x"5171812e",
+ 1010 => x"9a388172",
+ 1011 => x"269f3871",
+ 1012 => x"822eb838",
+ 1013 => x"71842ea9",
+ 1014 => x"3870730c",
+ 1015 => x"70800c84",
+ 1016 => x"3d0d0480",
+ 1017 => x"e40b81d7",
+ 1018 => x"b408258b",
+ 1019 => x"3880730c",
+ 1020 => x"70800c84",
+ 1021 => x"3d0d0483",
+ 1022 => x"730c7080",
+ 1023 => x"0c843d0d",
+ 1024 => x"0482730c",
+ 1025 => x"70800c84",
+ 1026 => x"3d0d0481",
+ 1027 => x"730c7080",
+ 1028 => x"0c843d0d",
+ 1029 => x"04803d0d",
+ 1030 => x"74741482",
+ 1031 => x"05710c80",
+ 1032 => x"0c823d0d",
+ 1033 => x"04f73d0d",
+ 1034 => x"7b7d7f61",
+ 1035 => x"85127082",
+ 1036 => x"2b751170",
+ 1037 => x"74717084",
+ 1038 => x"05530c5a",
+ 1039 => x"5a5d5b76",
+ 1040 => x"0c7980f8",
+ 1041 => x"180c7986",
+ 1042 => x"12525758",
+ 1043 => x"5a5a7676",
+ 1044 => x"24993876",
+ 1045 => x"b329822b",
+ 1046 => x"79115153",
+ 1047 => x"76737084",
+ 1048 => x"05550c81",
+ 1049 => x"14547574",
+ 1050 => x"25f23876",
+ 1051 => x"81cc2919",
+ 1052 => x"fc110881",
+ 1053 => x"05fc120c",
+ 1054 => x"7a197008",
+ 1055 => x"9fa0130c",
+ 1056 => x"5856850b",
+ 1057 => x"81d7b40c",
+ 1058 => x"75800c8b",
+ 1059 => x"3d0d04fe",
+ 1060 => x"3d0d0293",
+ 1061 => x"05335180",
+ 1062 => x"02840597",
+ 1063 => x"05335452",
+ 1064 => x"70732e88",
+ 1065 => x"3871800c",
+ 1066 => x"843d0d04",
+ 1067 => x"7081d7b8",
+ 1068 => x"34810b80",
+ 1069 => x"0c843d0d",
+ 1070 => x"04f83d0d",
+ 1071 => x"7a7c5956",
+ 1072 => x"820b8319",
+ 1073 => x"55557416",
+ 1074 => x"70337533",
+ 1075 => x"5b515372",
+ 1076 => x"792e80c6",
+ 1077 => x"3880c10b",
+ 1078 => x"81168116",
+ 1079 => x"56565782",
+ 1080 => x"7525e338",
+ 1081 => x"ffa91770",
+ 1082 => x"81ff0655",
+ 1083 => x"59738226",
+ 1084 => x"83388755",
+ 1085 => x"81537680",
+ 1086 => x"d22e9838",
+ 1087 => x"77527551",
+ 1088 => x"be963f80",
+ 1089 => x"53728008",
+ 1090 => x"25893887",
+ 1091 => x"1581d7b4",
+ 1092 => x"0c815372",
+ 1093 => x"800c8a3d",
+ 1094 => x"0d047281",
+ 1095 => x"d7b83482",
+ 1096 => x"7525ffa2",
+ 1097 => x"38ffbd39",
+ 1098 => x"8c08028c",
+ 1099 => x"0ceb3d0d",
+ 1100 => x"800b8c08",
+ 1101 => x"f0050c80",
+ 1102 => x"0b8c08f4",
+ 1103 => x"050c8c08",
+ 1104 => x"8c05088c",
+ 1105 => x"08900508",
+ 1106 => x"5654738c",
+ 1107 => x"08f0050c",
+ 1108 => x"748c08f4",
+ 1109 => x"050c8c08",
+ 1110 => x"f8058c08",
+ 1111 => x"f0055656",
+ 1112 => x"88705475",
+ 1113 => x"53765254",
+ 1114 => x"bbdf3f80",
+ 1115 => x"0b8c08e8",
+ 1116 => x"050c800b",
+ 1117 => x"8c08ec05",
+ 1118 => x"0c8c0894",
+ 1119 => x"05088c08",
+ 1120 => x"98050856",
+ 1121 => x"54738c08",
+ 1122 => x"e8050c74",
+ 1123 => x"8c08ec05",
+ 1124 => x"0c8c08f0",
+ 1125 => x"058c08e8",
+ 1126 => x"05565688",
+ 1127 => x"70547553",
+ 1128 => x"765254bb",
+ 1129 => x"a43f800b",
+ 1130 => x"8c08e805",
+ 1131 => x"0c800b8c",
+ 1132 => x"08ec050c",
+ 1133 => x"8c08fc05",
+ 1134 => x"0883ffff",
+ 1135 => x"068c08cc",
+ 1136 => x"050c8c08",
+ 1137 => x"fc050890",
+ 1138 => x"2a8c08c4",
+ 1139 => x"050c8c08",
+ 1140 => x"f4050883",
+ 1141 => x"ffff068c",
+ 1142 => x"08c8050c",
+ 1143 => x"8c08f405",
+ 1144 => x"08902a8c",
+ 1145 => x"08c0050c",
+ 1146 => x"8c08cc05",
+ 1147 => x"088c08c8",
+ 1148 => x"05082970",
+ 1149 => x"8c08dc05",
+ 1150 => x"0c8c08cc",
+ 1151 => x"05088c08",
+ 1152 => x"c0050829",
+ 1153 => x"708c08d8",
+ 1154 => x"050c8c08",
+ 1155 => x"c405088c",
+ 1156 => x"08c80508",
+ 1157 => x"29708c08",
+ 1158 => x"d4050c8c",
+ 1159 => x"08c40508",
+ 1160 => x"8c08c005",
+ 1161 => x"0829708c",
+ 1162 => x"08d0050c",
+ 1163 => x"8c08dc05",
+ 1164 => x"08902a8c",
+ 1165 => x"08d80508",
+ 1166 => x"118c08d8",
+ 1167 => x"050c8c08",
+ 1168 => x"d805088c",
+ 1169 => x"08d40508",
+ 1170 => x"058c08d8",
+ 1171 => x"050c5151",
+ 1172 => x"5151548c",
+ 1173 => x"08d80508",
+ 1174 => x"8c08d405",
+ 1175 => x"08278f38",
+ 1176 => x"8c08d005",
+ 1177 => x"08848080",
+ 1178 => x"058c08d0",
+ 1179 => x"050c8c08",
+ 1180 => x"d8050890",
+ 1181 => x"2a8c08d0",
+ 1182 => x"0508118c",
+ 1183 => x"08e0050c",
+ 1184 => x"8c08d805",
+ 1185 => x"0883ffff",
+ 1186 => x"0670902b",
+ 1187 => x"8c08dc05",
+ 1188 => x"0883ffff",
+ 1189 => x"0670128c",
+ 1190 => x"08e4050c",
+ 1191 => x"52575154",
+ 1192 => x"8c08e005",
+ 1193 => x"088c08e4",
+ 1194 => x"05085654",
+ 1195 => x"738c08e8",
+ 1196 => x"050c748c",
+ 1197 => x"08ec050c",
+ 1198 => x"8c08fc05",
+ 1199 => x"088c08f0",
+ 1200 => x"0508298c",
+ 1201 => x"08f80508",
+ 1202 => x"8c08f405",
+ 1203 => x"08297012",
+ 1204 => x"8c08e805",
+ 1205 => x"08118c08",
+ 1206 => x"e8050c51",
+ 1207 => x"55558c08",
+ 1208 => x"e805088c",
+ 1209 => x"08ec0508",
+ 1210 => x"8c088805",
+ 1211 => x"08585654",
+ 1212 => x"73760c74",
+ 1213 => x"84170c8c",
+ 1214 => x"08880508",
+ 1215 => x"800c973d",
+ 1216 => x"0d8c0c04",
+ 1217 => x"8c08028c",
+ 1218 => x"0cf63d0d",
+ 1219 => x"800b8c08",
+ 1220 => x"f0050c80",
+ 1221 => x"0b8c08f4",
+ 1222 => x"050c8c08",
+ 1223 => x"8c05088c",
+ 1224 => x"08900508",
+ 1225 => x"5654738c",
+ 1226 => x"08f0050c",
+ 1227 => x"748c08f4",
+ 1228 => x"050c8c08",
+ 1229 => x"f8058c08",
+ 1230 => x"f0055656",
+ 1231 => x"88705475",
+ 1232 => x"53765254",
+ 1233 => x"b8833f80",
+ 1234 => x"0b8c08f0",
+ 1235 => x"050c800b",
+ 1236 => x"8c08f405",
+ 1237 => x"0c8c08f8",
+ 1238 => x"0508308c",
+ 1239 => x"08ec050c",
+ 1240 => x"8c08fc05",
+ 1241 => x"08802e8d",
+ 1242 => x"388c08ec",
+ 1243 => x"0508ff05",
+ 1244 => x"8c08ec05",
+ 1245 => x"0c8c08ec",
+ 1246 => x"05088c08",
+ 1247 => x"f0050c8c",
+ 1248 => x"08fc0508",
+ 1249 => x"308c08f4",
+ 1250 => x"050c8c08",
+ 1251 => x"f005088c",
+ 1252 => x"08f40508",
+ 1253 => x"8c088805",
+ 1254 => x"08585654",
+ 1255 => x"73760c74",
+ 1256 => x"84170c8c",
+ 1257 => x"08880508",
+ 1258 => x"800c8c3d",
+ 1259 => x"0d8c0c04",
+ 1260 => x"8c08028c",
+ 1261 => x"0cf53d0d",
+ 1262 => x"8c089405",
+ 1263 => x"089d388c",
+ 1264 => x"088c0508",
+ 1265 => x"8c089005",
+ 1266 => x"088c0888",
+ 1267 => x"05085856",
+ 1268 => x"5473760c",
+ 1269 => x"7484170c",
+ 1270 => x"81bf3980",
+ 1271 => x"0b8c08f0",
+ 1272 => x"050c800b",
+ 1273 => x"8c08f405",
+ 1274 => x"0c8c088c",
+ 1275 => x"05088c08",
+ 1276 => x"90050856",
+ 1277 => x"54738c08",
+ 1278 => x"f0050c74",
+ 1279 => x"8c08f405",
+ 1280 => x"0c8c08f8",
+ 1281 => x"058c08f0",
+ 1282 => x"05565688",
+ 1283 => x"70547553",
+ 1284 => x"765254b6",
+ 1285 => x"b43fa00b",
+ 1286 => x"8c089405",
+ 1287 => x"08318c08",
+ 1288 => x"ec050c8c",
+ 1289 => x"08ec0508",
+ 1290 => x"80249d38",
+ 1291 => x"800b8c08",
+ 1292 => x"f4050c8c",
+ 1293 => x"08ec0508",
+ 1294 => x"308c08fc",
+ 1295 => x"0508712b",
+ 1296 => x"8c08f005",
+ 1297 => x"0c54b939",
+ 1298 => x"8c08fc05",
+ 1299 => x"088c08ec",
+ 1300 => x"05082a8c",
+ 1301 => x"08e8050c",
+ 1302 => x"8c08fc05",
+ 1303 => x"088c0894",
+ 1304 => x"05082b8c",
+ 1305 => x"08f4050c",
+ 1306 => x"8c08f805",
+ 1307 => x"088c0894",
+ 1308 => x"05082b70",
+ 1309 => x"8c08e805",
+ 1310 => x"08078c08",
+ 1311 => x"f0050c54",
+ 1312 => x"8c08f005",
+ 1313 => x"088c08f4",
+ 1314 => x"05088c08",
+ 1315 => x"88050858",
+ 1316 => x"56547376",
+ 1317 => x"0c748417",
+ 1318 => x"0c8c0888",
+ 1319 => x"0508800c",
+ 1320 => x"8d3d0d8c",
+ 1321 => x"0c048c08",
+ 1322 => x"028c0ccc",
+ 1323 => x"3d0d800b",
+ 1324 => x"8c08fc05",
+ 1325 => x"0c800b8c",
+ 1326 => x"08ec050c",
+ 1327 => x"800b8c08",
+ 1328 => x"f0050c8c",
+ 1329 => x"088c0508",
+ 1330 => x"8c089005",
+ 1331 => x"08565473",
+ 1332 => x"8c08ec05",
+ 1333 => x"0c748c08",
+ 1334 => x"f0050c8c",
+ 1335 => x"08f4058c",
+ 1336 => x"08ec0556",
+ 1337 => x"56887054",
+ 1338 => x"75537652",
+ 1339 => x"54b4da3f",
+ 1340 => x"800b8c08",
+ 1341 => x"e4050c80",
+ 1342 => x"0b8c08e8",
+ 1343 => x"050c8c08",
+ 1344 => x"9405088c",
+ 1345 => x"08980508",
+ 1346 => x"5654738c",
+ 1347 => x"08e4050c",
+ 1348 => x"748c08e8",
+ 1349 => x"050c8c08",
+ 1350 => x"ec058c08",
+ 1351 => x"e4055656",
+ 1352 => x"88705475",
+ 1353 => x"53765254",
+ 1354 => x"b49f3f8c",
+ 1355 => x"08f40508",
+ 1356 => x"8025be38",
+ 1357 => x"8c08fc05",
+ 1358 => x"08098c08",
+ 1359 => x"fc050c8c",
+ 1360 => x"08d40554",
+ 1361 => x"8c08f405",
+ 1362 => x"088c08f8",
+ 1363 => x"05085755",
+ 1364 => x"74527553",
+ 1365 => x"7351fbac",
+ 1366 => x"3f8c08d4",
+ 1367 => x"05088c08",
+ 1368 => x"d8050856",
+ 1369 => x"54738c08",
+ 1370 => x"f4050c74",
+ 1371 => x"8c08f805",
+ 1372 => x"0c8c08ec",
+ 1373 => x"05088025",
+ 1374 => x"be388c08",
+ 1375 => x"fc050809",
+ 1376 => x"8c08fc05",
+ 1377 => x"0c8c08d4",
+ 1378 => x"05548c08",
+ 1379 => x"ec05088c",
+ 1380 => x"08f00508",
+ 1381 => x"57557452",
+ 1382 => x"75537351",
+ 1383 => x"fae63f8c",
+ 1384 => x"08d40508",
+ 1385 => x"8c08d805",
+ 1386 => x"08565473",
+ 1387 => x"8c08ec05",
+ 1388 => x"0c748c08",
+ 1389 => x"f0050c8c",
+ 1390 => x"08f40508",
+ 1391 => x"8c08f805",
+ 1392 => x"08565473",
+ 1393 => x"8c08d405",
+ 1394 => x"0c748c08",
+ 1395 => x"d8050c8c",
+ 1396 => x"08ec0508",
+ 1397 => x"8c08f005",
+ 1398 => x"08565473",
+ 1399 => x"8c08cc05",
+ 1400 => x"0c748c08",
+ 1401 => x"d0050c80",
+ 1402 => x"0b8c08c8",
+ 1403 => x"050c800b",
+ 1404 => x"8c08e405",
+ 1405 => x"0c800b8c",
+ 1406 => x"08e8050c",
+ 1407 => x"8c08d405",
+ 1408 => x"088c08d8",
+ 1409 => x"05085654",
+ 1410 => x"738c08e4",
+ 1411 => x"050c748c",
+ 1412 => x"08e8050c",
+ 1413 => x"800b8c08",
+ 1414 => x"ffb8050c",
+ 1415 => x"800b8c08",
+ 1416 => x"ffbc050c",
+ 1417 => x"8c08cc05",
+ 1418 => x"088c08d0",
+ 1419 => x"05085654",
+ 1420 => x"738c08ff",
+ 1421 => x"b8050c74",
+ 1422 => x"8c08ffbc",
+ 1423 => x"050c8c08",
+ 1424 => x"ffbc0508",
+ 1425 => x"8c08ffac",
+ 1426 => x"050c8c08",
+ 1427 => x"ffb80508",
+ 1428 => x"8c08ffa8",
+ 1429 => x"050c8c08",
+ 1430 => x"e805088c",
+ 1431 => x"08ffa405",
+ 1432 => x"0c8c08e4",
+ 1433 => x"05088c08",
+ 1434 => x"ffa0050c",
+ 1435 => x"8c08ffa8",
+ 1436 => x"050891d4",
+ 1437 => x"388c08ff",
+ 1438 => x"a005088c",
+ 1439 => x"08ffac05",
+ 1440 => x"0827868c",
+ 1441 => x"388c08ff",
+ 1442 => x"ac05088c",
+ 1443 => x"08ff8805",
+ 1444 => x"0c8c08ff",
+ 1445 => x"88050883",
+ 1446 => x"ffff26a0",
+ 1447 => x"388c08ff",
+ 1448 => x"88050881",
+ 1449 => x"ff268b38",
+ 1450 => x"800b8c08",
+ 1451 => x"fed8050c",
+ 1452 => x"a939880b",
+ 1453 => x"8c08fed8",
+ 1454 => x"050c9f39",
+ 1455 => x"8c08ff88",
+ 1456 => x"0508fe80",
+ 1457 => x"0a268b38",
+ 1458 => x"900b8c08",
+ 1459 => x"fed8050c",
+ 1460 => x"8939980b",
+ 1461 => x"8c08fed8",
+ 1462 => x"050c8c08",
+ 1463 => x"fed80508",
+ 1464 => x"8c08ff84",
+ 1465 => x"050c8c08",
+ 1466 => x"ff880508",
+ 1467 => x"8c08ff84",
+ 1468 => x"05082a80",
+ 1469 => x"f6c81133",
+ 1470 => x"8c08ff84",
+ 1471 => x"050811a0",
+ 1472 => x"71318c08",
+ 1473 => x"ff8c050c",
+ 1474 => x"5151548c",
+ 1475 => x"08ff8c05",
+ 1476 => x"08802e80",
+ 1477 => x"d1388c08",
+ 1478 => x"ffac0508",
+ 1479 => x"8c08ff8c",
+ 1480 => x"05082b8c",
+ 1481 => x"08ffac05",
+ 1482 => x"0c8c08ff",
+ 1483 => x"a005088c",
+ 1484 => x"08ff8c05",
+ 1485 => x"082ba00b",
+ 1486 => x"8c08ff8c",
+ 1487 => x"0508318c",
+ 1488 => x"08ffa405",
+ 1489 => x"08712a70",
+ 1490 => x"73078c08",
+ 1491 => x"ffa0050c",
+ 1492 => x"8c08ffa4",
+ 1493 => x"05088c08",
+ 1494 => x"ff8c0508",
+ 1495 => x"2b8c08ff",
+ 1496 => x"a4050c51",
+ 1497 => x"56548c08",
+ 1498 => x"ffac0508",
+ 1499 => x"902a8c08",
+ 1500 => x"ff84050c",
+ 1501 => x"8c08ffac",
+ 1502 => x"050883ff",
+ 1503 => x"ff068c08",
+ 1504 => x"ff88050c",
+ 1505 => x"8c08ffa0",
+ 1506 => x"05088c08",
+ 1507 => x"ff840508",
+ 1508 => x"53705254",
+ 1509 => x"9efb3f80",
+ 1510 => x"08708c08",
+ 1511 => x"fef8050c",
+ 1512 => x"8c08ff84",
+ 1513 => x"0508538c",
+ 1514 => x"08ffa005",
+ 1515 => x"0852549e",
+ 1516 => x"bb3f8008",
+ 1517 => x"708c08ff",
+ 1518 => x"80050c8c",
+ 1519 => x"08ff8005",
+ 1520 => x"088c08ff",
+ 1521 => x"88050829",
+ 1522 => x"708c08fe",
+ 1523 => x"f0050c8c",
+ 1524 => x"08fef805",
+ 1525 => x"0870902b",
+ 1526 => x"8c08ffa4",
+ 1527 => x"0508902a",
+ 1528 => x"7072078c",
+ 1529 => x"08fef805",
+ 1530 => x"0c525851",
+ 1531 => x"51548c08",
+ 1532 => x"fef80508",
+ 1533 => x"8c08fef0",
+ 1534 => x"05082780",
+ 1535 => x"e1388c08",
+ 1536 => x"ff800508",
+ 1537 => x"ff058c08",
+ 1538 => x"ff80050c",
+ 1539 => x"8c08fef8",
+ 1540 => x"05088c08",
+ 1541 => x"ffac0508",
+ 1542 => x"058c08fe",
+ 1543 => x"f8050c8c",
+ 1544 => x"08ffac05",
+ 1545 => x"088c08fe",
+ 1546 => x"f8050826",
+ 1547 => x"b1388c08",
+ 1548 => x"fef80508",
+ 1549 => x"8c08fef0",
+ 1550 => x"050827a2",
+ 1551 => x"388c08ff",
+ 1552 => x"800508ff",
+ 1553 => x"058c08ff",
+ 1554 => x"80050c8c",
+ 1555 => x"08fef805",
+ 1556 => x"088c08ff",
+ 1557 => x"ac050805",
+ 1558 => x"8c08fef8",
+ 1559 => x"050c8c08",
+ 1560 => x"fef80508",
+ 1561 => x"8c08fef0",
+ 1562 => x"0508318c",
+ 1563 => x"08fef805",
+ 1564 => x"0c8c08fe",
+ 1565 => x"f805088c",
+ 1566 => x"08ff8405",
+ 1567 => x"08537052",
+ 1568 => x"549d8e3f",
+ 1569 => x"8008708c",
+ 1570 => x"08fef405",
+ 1571 => x"0c8c08ff",
+ 1572 => x"84050853",
+ 1573 => x"8c08fef8",
+ 1574 => x"05085254",
+ 1575 => x"9cce3f80",
+ 1576 => x"08708c08",
+ 1577 => x"fefc050c",
+ 1578 => x"8c08fefc",
+ 1579 => x"05088c08",
+ 1580 => x"ff880508",
+ 1581 => x"29708c08",
+ 1582 => x"fef0050c",
+ 1583 => x"8c08fef4",
+ 1584 => x"05087090",
+ 1585 => x"2b8c08ff",
+ 1586 => x"a4050883",
+ 1587 => x"ffff0670",
+ 1588 => x"72078c08",
+ 1589 => x"fef4050c",
+ 1590 => x"52585151",
+ 1591 => x"548c08fe",
+ 1592 => x"f405088c",
+ 1593 => x"08fef005",
+ 1594 => x"082780e1",
+ 1595 => x"388c08fe",
+ 1596 => x"fc0508ff",
+ 1597 => x"058c08fe",
+ 1598 => x"fc050c8c",
+ 1599 => x"08fef405",
+ 1600 => x"088c08ff",
+ 1601 => x"ac050805",
+ 1602 => x"8c08fef4",
+ 1603 => x"050c8c08",
+ 1604 => x"ffac0508",
+ 1605 => x"8c08fef4",
+ 1606 => x"050826b1",
+ 1607 => x"388c08fe",
+ 1608 => x"f405088c",
+ 1609 => x"08fef005",
+ 1610 => x"0827a238",
+ 1611 => x"8c08fefc",
+ 1612 => x"0508ff05",
+ 1613 => x"8c08fefc",
+ 1614 => x"050c8c08",
+ 1615 => x"fef40508",
+ 1616 => x"8c08ffac",
+ 1617 => x"0508058c",
+ 1618 => x"08fef405",
+ 1619 => x"0c8c08fe",
+ 1620 => x"f405088c",
+ 1621 => x"08fef005",
+ 1622 => x"08318c08",
+ 1623 => x"fef4050c",
+ 1624 => x"8c08ff80",
+ 1625 => x"05087090",
+ 1626 => x"2b708c08",
+ 1627 => x"fefc0508",
+ 1628 => x"078c08ff",
+ 1629 => x"98050c8c",
+ 1630 => x"08fef405",
+ 1631 => x"088c08ff",
+ 1632 => x"a4050c51",
+ 1633 => x"54800b8c",
+ 1634 => x"08ff9405",
+ 1635 => x"0c8af639",
+ 1636 => x"8c08ffac",
+ 1637 => x"05089738",
+ 1638 => x"8c08ffac",
+ 1639 => x"05085281",
+ 1640 => x"519ac93f",
+ 1641 => x"8008708c",
+ 1642 => x"08ffac05",
+ 1643 => x"0c548c08",
+ 1644 => x"ffac0508",
+ 1645 => x"8c08fef0",
+ 1646 => x"050c8c08",
+ 1647 => x"fef00508",
+ 1648 => x"83ffff26",
+ 1649 => x"a0388c08",
+ 1650 => x"fef00508",
+ 1651 => x"81ff268b",
+ 1652 => x"38800b8c",
+ 1653 => x"08fed405",
+ 1654 => x"0ca93988",
+ 1655 => x"0b8c08fe",
+ 1656 => x"d4050c9f",
+ 1657 => x"398c08fe",
+ 1658 => x"f00508fe",
+ 1659 => x"800a268b",
+ 1660 => x"38900b8c",
+ 1661 => x"08fed405",
+ 1662 => x"0c893998",
+ 1663 => x"0b8c08fe",
+ 1664 => x"d4050c8c",
+ 1665 => x"08fed405",
+ 1666 => x"088c08fe",
+ 1667 => x"f4050c8c",
+ 1668 => x"08fef005",
+ 1669 => x"088c08fe",
+ 1670 => x"f405082a",
+ 1671 => x"80f6c811",
+ 1672 => x"338c08fe",
+ 1673 => x"f4050811",
+ 1674 => x"a071318c",
+ 1675 => x"08ff8c05",
+ 1676 => x"0c515154",
+ 1677 => x"8c08ff8c",
+ 1678 => x"05089f38",
+ 1679 => x"8c08ffa0",
+ 1680 => x"05088c08",
+ 1681 => x"ffac0508",
+ 1682 => x"318c08ff",
+ 1683 => x"a0050c81",
+ 1684 => x"0b8c08ff",
+ 1685 => x"94050c85",
+ 1686 => x"8d39a00b",
+ 1687 => x"8c08ff8c",
+ 1688 => x"0508318c",
+ 1689 => x"08ff9005",
+ 1690 => x"0c8c08ff",
+ 1691 => x"ac05088c",
+ 1692 => x"08ff8c05",
+ 1693 => x"082b8c08",
+ 1694 => x"ffac050c",
+ 1695 => x"8c08ffa0",
+ 1696 => x"05088c08",
+ 1697 => x"ff900508",
+ 1698 => x"2a8c08ff",
+ 1699 => x"9c050c8c",
+ 1700 => x"08ffa005",
+ 1701 => x"088c08ff",
+ 1702 => x"8c05082b",
+ 1703 => x"8c08ffa4",
+ 1704 => x"05088c08",
+ 1705 => x"ff900508",
+ 1706 => x"2a707207",
+ 1707 => x"8c08ffa0",
+ 1708 => x"050c8c08",
+ 1709 => x"ffa40508",
+ 1710 => x"8c08ff8c",
+ 1711 => x"05082b8c",
+ 1712 => x"08ffa405",
+ 1713 => x"0c8c08ff",
+ 1714 => x"ac050890",
+ 1715 => x"2a8c08fe",
+ 1716 => x"f0050c8c",
+ 1717 => x"08ffac05",
+ 1718 => x"0883ffff",
+ 1719 => x"068c08fe",
+ 1720 => x"f4050c8c",
+ 1721 => x"08ff9c05",
+ 1722 => x"088c08fe",
+ 1723 => x"f0050855",
+ 1724 => x"70545155",
+ 1725 => x"55989a3f",
+ 1726 => x"8008708c",
+ 1727 => x"08ff8005",
+ 1728 => x"0c8c08fe",
+ 1729 => x"f0050853",
+ 1730 => x"8c08ff9c",
+ 1731 => x"05085254",
+ 1732 => x"97da3f80",
+ 1733 => x"08708c08",
+ 1734 => x"fef8050c",
+ 1735 => x"8c08fef8",
+ 1736 => x"05088c08",
+ 1737 => x"fef40508",
+ 1738 => x"29708c08",
+ 1739 => x"ff88050c",
+ 1740 => x"8c08ff80",
+ 1741 => x"05087090",
+ 1742 => x"2b8c08ff",
+ 1743 => x"a0050890",
+ 1744 => x"2a707207",
+ 1745 => x"8c08ff80",
+ 1746 => x"050c5258",
+ 1747 => x"5151548c",
+ 1748 => x"08ff8005",
+ 1749 => x"088c08ff",
+ 1750 => x"88050827",
+ 1751 => x"80e1388c",
+ 1752 => x"08fef805",
+ 1753 => x"08ff058c",
+ 1754 => x"08fef805",
+ 1755 => x"0c8c08ff",
+ 1756 => x"8005088c",
+ 1757 => x"08ffac05",
+ 1758 => x"08058c08",
+ 1759 => x"ff80050c",
+ 1760 => x"8c08ffac",
+ 1761 => x"05088c08",
+ 1762 => x"ff800508",
+ 1763 => x"26b1388c",
+ 1764 => x"08ff8005",
+ 1765 => x"088c08ff",
+ 1766 => x"88050827",
+ 1767 => x"a2388c08",
+ 1768 => x"fef80508",
+ 1769 => x"ff058c08",
+ 1770 => x"fef8050c",
+ 1771 => x"8c08ff80",
+ 1772 => x"05088c08",
+ 1773 => x"ffac0508",
+ 1774 => x"058c08ff",
+ 1775 => x"80050c8c",
+ 1776 => x"08ff8005",
+ 1777 => x"088c08ff",
+ 1778 => x"88050831",
+ 1779 => x"8c08ff80",
+ 1780 => x"050c8c08",
+ 1781 => x"ff800508",
+ 1782 => x"8c08fef0",
+ 1783 => x"05085370",
+ 1784 => x"525496ad",
+ 1785 => x"3f800870",
+ 1786 => x"8c08ff84",
+ 1787 => x"050c8c08",
+ 1788 => x"fef00508",
+ 1789 => x"538c08ff",
+ 1790 => x"80050852",
+ 1791 => x"5495ed3f",
+ 1792 => x"8008708c",
+ 1793 => x"08fefc05",
+ 1794 => x"0c8c08fe",
+ 1795 => x"fc05088c",
+ 1796 => x"08fef405",
+ 1797 => x"0829708c",
+ 1798 => x"08ff8805",
+ 1799 => x"0c8c08ff",
+ 1800 => x"84050870",
+ 1801 => x"902b8c08",
+ 1802 => x"ffa00508",
+ 1803 => x"83ffff06",
+ 1804 => x"7072078c",
+ 1805 => x"08ff8405",
+ 1806 => x"0c525851",
+ 1807 => x"51548c08",
+ 1808 => x"ff840508",
+ 1809 => x"8c08ff88",
+ 1810 => x"05082780",
+ 1811 => x"e1388c08",
+ 1812 => x"fefc0508",
+ 1813 => x"ff058c08",
+ 1814 => x"fefc050c",
+ 1815 => x"8c08ff84",
+ 1816 => x"05088c08",
+ 1817 => x"ffac0508",
+ 1818 => x"058c08ff",
+ 1819 => x"84050c8c",
+ 1820 => x"08ffac05",
+ 1821 => x"088c08ff",
+ 1822 => x"84050826",
+ 1823 => x"b1388c08",
+ 1824 => x"ff840508",
+ 1825 => x"8c08ff88",
+ 1826 => x"050827a2",
+ 1827 => x"388c08fe",
+ 1828 => x"fc0508ff",
+ 1829 => x"058c08fe",
+ 1830 => x"fc050c8c",
+ 1831 => x"08ff8405",
+ 1832 => x"088c08ff",
+ 1833 => x"ac050805",
+ 1834 => x"8c08ff84",
+ 1835 => x"050c8c08",
+ 1836 => x"ff840508",
+ 1837 => x"8c08ff88",
+ 1838 => x"0508318c",
+ 1839 => x"08ff8405",
+ 1840 => x"0c8c08fe",
+ 1841 => x"f8050870",
+ 1842 => x"902b708c",
+ 1843 => x"08fefc05",
+ 1844 => x"08078c08",
+ 1845 => x"ff94050c",
+ 1846 => x"8c08ff84",
+ 1847 => x"05088c08",
+ 1848 => x"ffa0050c",
+ 1849 => x"51548c08",
+ 1850 => x"ffac0508",
+ 1851 => x"902a8c08",
+ 1852 => x"fef0050c",
+ 1853 => x"8c08ffac",
+ 1854 => x"050883ff",
+ 1855 => x"ff068c08",
+ 1856 => x"fef4050c",
+ 1857 => x"8c08ffa0",
+ 1858 => x"05088c08",
+ 1859 => x"fef00508",
+ 1860 => x"53705254",
+ 1861 => x"93fb3f80",
+ 1862 => x"08708c08",
+ 1863 => x"ff80050c",
+ 1864 => x"8c08fef0",
+ 1865 => x"0508538c",
+ 1866 => x"08ffa005",
+ 1867 => x"08525493",
+ 1868 => x"bb3f8008",
+ 1869 => x"708c08fe",
+ 1870 => x"f8050c8c",
+ 1871 => x"08fef805",
+ 1872 => x"088c08fe",
+ 1873 => x"f4050829",
+ 1874 => x"708c08ff",
+ 1875 => x"88050c8c",
+ 1876 => x"08ff8005",
+ 1877 => x"0870902b",
+ 1878 => x"8c08ffa4",
+ 1879 => x"0508902a",
+ 1880 => x"7072078c",
+ 1881 => x"08ff8005",
+ 1882 => x"0c525851",
+ 1883 => x"51548c08",
+ 1884 => x"ff800508",
+ 1885 => x"8c08ff88",
+ 1886 => x"05082780",
+ 1887 => x"e1388c08",
+ 1888 => x"fef80508",
+ 1889 => x"ff058c08",
+ 1890 => x"fef8050c",
+ 1891 => x"8c08ff80",
+ 1892 => x"05088c08",
+ 1893 => x"ffac0508",
+ 1894 => x"058c08ff",
+ 1895 => x"80050c8c",
+ 1896 => x"08ffac05",
+ 1897 => x"088c08ff",
+ 1898 => x"80050826",
+ 1899 => x"b1388c08",
+ 1900 => x"ff800508",
+ 1901 => x"8c08ff88",
+ 1902 => x"050827a2",
+ 1903 => x"388c08fe",
+ 1904 => x"f80508ff",
+ 1905 => x"058c08fe",
+ 1906 => x"f8050c8c",
+ 1907 => x"08ff8005",
+ 1908 => x"088c08ff",
+ 1909 => x"ac050805",
+ 1910 => x"8c08ff80",
+ 1911 => x"050c8c08",
+ 1912 => x"ff800508",
+ 1913 => x"8c08ff88",
+ 1914 => x"0508318c",
+ 1915 => x"08ff8005",
+ 1916 => x"0c8c08ff",
+ 1917 => x"8005088c",
+ 1918 => x"08fef005",
+ 1919 => x"08537052",
+ 1920 => x"54928e3f",
+ 1921 => x"8008708c",
+ 1922 => x"08ff8405",
+ 1923 => x"0c8c08fe",
+ 1924 => x"f0050853",
+ 1925 => x"8c08ff80",
+ 1926 => x"05085254",
+ 1927 => x"91ce3f80",
+ 1928 => x"08708c08",
+ 1929 => x"fefc050c",
+ 1930 => x"8c08fefc",
+ 1931 => x"05088c08",
+ 1932 => x"fef40508",
+ 1933 => x"29708c08",
+ 1934 => x"ff88050c",
+ 1935 => x"8c08ff84",
+ 1936 => x"05087090",
+ 1937 => x"2b8c08ff",
+ 1938 => x"a4050883",
+ 1939 => x"ffff0670",
+ 1940 => x"72078c08",
+ 1941 => x"ff84050c",
+ 1942 => x"52585151",
+ 1943 => x"548c08ff",
+ 1944 => x"8405088c",
+ 1945 => x"08ff8805",
+ 1946 => x"082780e1",
+ 1947 => x"388c08fe",
+ 1948 => x"fc0508ff",
+ 1949 => x"058c08fe",
+ 1950 => x"fc050c8c",
+ 1951 => x"08ff8405",
+ 1952 => x"088c08ff",
+ 1953 => x"ac050805",
+ 1954 => x"8c08ff84",
+ 1955 => x"050c8c08",
+ 1956 => x"ffac0508",
+ 1957 => x"8c08ff84",
+ 1958 => x"050826b1",
+ 1959 => x"388c08ff",
+ 1960 => x"8405088c",
+ 1961 => x"08ff8805",
+ 1962 => x"0827a238",
+ 1963 => x"8c08fefc",
+ 1964 => x"0508ff05",
+ 1965 => x"8c08fefc",
+ 1966 => x"050c8c08",
+ 1967 => x"ff840508",
+ 1968 => x"8c08ffac",
+ 1969 => x"0508058c",
+ 1970 => x"08ff8405",
+ 1971 => x"0c8c08ff",
+ 1972 => x"8405088c",
+ 1973 => x"08ff8805",
+ 1974 => x"08318c08",
+ 1975 => x"ff84050c",
+ 1976 => x"8c08fef8",
+ 1977 => x"05087090",
+ 1978 => x"2b708c08",
+ 1979 => x"fefc0508",
+ 1980 => x"078c08ff",
+ 1981 => x"98050c8c",
+ 1982 => x"08ff8405",
+ 1983 => x"088c08ff",
+ 1984 => x"a4050c51",
+ 1985 => x"548c08c8",
+ 1986 => x"0508802e",
+ 1987 => x"8ea3388c",
+ 1988 => x"08ffa405",
+ 1989 => x"088c08ff",
+ 1990 => x"8c05082a",
+ 1991 => x"8c08ffb4",
+ 1992 => x"050c800b",
+ 1993 => x"8c08ffb0",
+ 1994 => x"050c8c08",
+ 1995 => x"c8050856",
+ 1996 => x"8c08ffb0",
+ 1997 => x"05088c08",
+ 1998 => x"ffb40508",
+ 1999 => x"56547376",
+ 2000 => x"0c748417",
+ 2001 => x"0c8dea39",
+ 2002 => x"8c08ffa0",
+ 2003 => x"05088c08",
+ 2004 => x"ffa80508",
+ 2005 => x"2780d138",
+ 2006 => x"800b8c08",
+ 2007 => x"ff98050c",
+ 2008 => x"800b8c08",
+ 2009 => x"ff94050c",
+ 2010 => x"8c08c805",
+ 2011 => x"08802e8d",
+ 2012 => x"c0388c08",
+ 2013 => x"ffa40508",
+ 2014 => x"8c08ffb4",
+ 2015 => x"050c8c08",
+ 2016 => x"ffa00508",
+ 2017 => x"8c08ffb0",
+ 2018 => x"050c8c08",
+ 2019 => x"c8050856",
+ 2020 => x"8c08ffb0",
+ 2021 => x"05088c08",
+ 2022 => x"ffb40508",
+ 2023 => x"56547376",
+ 2024 => x"0c748417",
+ 2025 => x"0c8d8a39",
+ 2026 => x"8c08ffa8",
+ 2027 => x"05088c08",
+ 2028 => x"fef0050c",
+ 2029 => x"8c08fef0",
+ 2030 => x"050883ff",
+ 2031 => x"ff26a038",
+ 2032 => x"8c08fef0",
+ 2033 => x"050881ff",
+ 2034 => x"268b3880",
+ 2035 => x"0b8c08fe",
+ 2036 => x"d0050ca9",
+ 2037 => x"39880b8c",
+ 2038 => x"08fed005",
+ 2039 => x"0c9f398c",
+ 2040 => x"08fef005",
+ 2041 => x"08fe800a",
+ 2042 => x"268b3890",
+ 2043 => x"0b8c08fe",
+ 2044 => x"d0050c89",
+ 2045 => x"39980b8c",
+ 2046 => x"08fed005",
+ 2047 => x"0c8c08fe",
+ 2048 => x"d005088c",
+ 2049 => x"08fef405",
+ 2050 => x"0c8c08fe",
+ 2051 => x"f005088c",
+ 2052 => x"08fef405",
+ 2053 => x"082a80f6",
+ 2054 => x"c811338c",
+ 2055 => x"08fef405",
+ 2056 => x"0811a071",
+ 2057 => x"318c08ff",
+ 2058 => x"8c050c51",
+ 2059 => x"51548c08",
+ 2060 => x"ff8c0508",
+ 2061 => x"81d9388c",
+ 2062 => x"08ffa005",
+ 2063 => x"088c08ff",
+ 2064 => x"a8050826",
+ 2065 => x"93388c08",
+ 2066 => x"ffa40508",
+ 2067 => x"8c08ffac",
+ 2068 => x"05082784",
+ 2069 => x"3880e839",
+ 2070 => x"810b8c08",
+ 2071 => x"ff98050c",
+ 2072 => x"8c08ffa4",
+ 2073 => x"05088c08",
+ 2074 => x"ffac0508",
+ 2075 => x"318c08fe",
+ 2076 => x"f0050c8c",
+ 2077 => x"08ffa005",
+ 2078 => x"088c08ff",
+ 2079 => x"a8050831",
+ 2080 => x"708c08fe",
+ 2081 => x"cc050c54",
+ 2082 => x"8c08ffa4",
+ 2083 => x"05088c08",
+ 2084 => x"fef00508",
+ 2085 => x"278f388c",
+ 2086 => x"08fecc05",
+ 2087 => x"08ff058c",
+ 2088 => x"08fecc05",
+ 2089 => x"0c8c08fe",
+ 2090 => x"cc05088c",
+ 2091 => x"08ffa005",
+ 2092 => x"0c8c08fe",
+ 2093 => x"f005088c",
+ 2094 => x"08ffa405",
+ 2095 => x"0c893980",
+ 2096 => x"0b8c08ff",
+ 2097 => x"98050c80",
+ 2098 => x"0b8c08ff",
+ 2099 => x"94050c8c",
+ 2100 => x"08c80508",
+ 2101 => x"802e8ad9",
+ 2102 => x"388c08ff",
+ 2103 => x"a405088c",
+ 2104 => x"08ffb405",
+ 2105 => x"0c8c08ff",
+ 2106 => x"a005088c",
+ 2107 => x"08ffb005",
+ 2108 => x"0c8c08c8",
+ 2109 => x"0508568c",
+ 2110 => x"08ffb005",
+ 2111 => x"088c08ff",
+ 2112 => x"b4050856",
+ 2113 => x"5473760c",
+ 2114 => x"7484170c",
+ 2115 => x"8aa339a0",
+ 2116 => x"0b8c08ff",
+ 2117 => x"8c050831",
+ 2118 => x"8c08ff90",
+ 2119 => x"050c8c08",
+ 2120 => x"ffa80508",
+ 2121 => x"8c08ff8c",
+ 2122 => x"05082b8c",
+ 2123 => x"08ffac05",
+ 2124 => x"088c08ff",
+ 2125 => x"9005082a",
+ 2126 => x"7072078c",
+ 2127 => x"08ffa805",
+ 2128 => x"0c8c08ff",
+ 2129 => x"ac05088c",
+ 2130 => x"08ff8c05",
+ 2131 => x"082b8c08",
+ 2132 => x"ffac050c",
+ 2133 => x"8c08ffa0",
+ 2134 => x"05088c08",
+ 2135 => x"ff900508",
+ 2136 => x"2a8c08ff",
+ 2137 => x"9c050c8c",
+ 2138 => x"08ffa005",
+ 2139 => x"088c08ff",
+ 2140 => x"8c05082b",
+ 2141 => x"8c08ffa4",
+ 2142 => x"05088c08",
+ 2143 => x"ff900508",
+ 2144 => x"2a707207",
+ 2145 => x"8c08ffa0",
+ 2146 => x"050c8c08",
+ 2147 => x"ffa40508",
+ 2148 => x"8c08ff8c",
+ 2149 => x"05082b8c",
+ 2150 => x"08ffa405",
+ 2151 => x"0c8c08ff",
+ 2152 => x"a8050890",
+ 2153 => x"2a8c08fe",
+ 2154 => x"f8050c8c",
+ 2155 => x"08ffa805",
+ 2156 => x"0883ffff",
+ 2157 => x"068c08fe",
+ 2158 => x"fc050c8c",
+ 2159 => x"08ff9c05",
+ 2160 => x"088c08fe",
+ 2161 => x"f8050857",
+ 2162 => x"70565152",
+ 2163 => x"5255558a",
+ 2164 => x"c03f8008",
+ 2165 => x"708c08ff",
+ 2166 => x"88050c8c",
+ 2167 => x"08fef805",
+ 2168 => x"08538c08",
+ 2169 => x"ff9c0508",
+ 2170 => x"52548a80",
+ 2171 => x"3f800870",
+ 2172 => x"8c08ff80",
+ 2173 => x"050c8c08",
+ 2174 => x"ff800508",
+ 2175 => x"8c08fefc",
+ 2176 => x"05082970",
+ 2177 => x"8c08fee8",
+ 2178 => x"050c8c08",
+ 2179 => x"ff880508",
+ 2180 => x"70902b8c",
+ 2181 => x"08ffa005",
+ 2182 => x"08902a70",
+ 2183 => x"72078c08",
+ 2184 => x"ff88050c",
+ 2185 => x"52585151",
+ 2186 => x"548c08ff",
+ 2187 => x"8805088c",
+ 2188 => x"08fee805",
+ 2189 => x"082780e1",
+ 2190 => x"388c08ff",
+ 2191 => x"800508ff",
+ 2192 => x"058c08ff",
+ 2193 => x"80050c8c",
+ 2194 => x"08ff8805",
+ 2195 => x"088c08ff",
+ 2196 => x"a8050805",
+ 2197 => x"8c08ff88",
+ 2198 => x"050c8c08",
+ 2199 => x"ffa80508",
+ 2200 => x"8c08ff88",
+ 2201 => x"050826b1",
+ 2202 => x"388c08ff",
+ 2203 => x"8805088c",
+ 2204 => x"08fee805",
+ 2205 => x"0827a238",
+ 2206 => x"8c08ff80",
+ 2207 => x"0508ff05",
+ 2208 => x"8c08ff80",
+ 2209 => x"050c8c08",
+ 2210 => x"ff880508",
+ 2211 => x"8c08ffa8",
+ 2212 => x"0508058c",
+ 2213 => x"08ff8805",
+ 2214 => x"0c8c08ff",
+ 2215 => x"8805088c",
+ 2216 => x"08fee805",
+ 2217 => x"08318c08",
+ 2218 => x"ff88050c",
+ 2219 => x"8c08ff88",
+ 2220 => x"05088c08",
+ 2221 => x"fef80508",
+ 2222 => x"53705254",
+ 2223 => x"88d33f80",
+ 2224 => x"08708c08",
+ 2225 => x"feec050c",
+ 2226 => x"8c08fef8",
+ 2227 => x"0508538c",
+ 2228 => x"08ff8805",
+ 2229 => x"08525488",
+ 2230 => x"933f8008",
+ 2231 => x"708c08ff",
+ 2232 => x"84050c8c",
+ 2233 => x"08ff8405",
+ 2234 => x"088c08fe",
+ 2235 => x"fc050829",
+ 2236 => x"708c08fe",
+ 2237 => x"e8050c8c",
+ 2238 => x"08feec05",
+ 2239 => x"0870902b",
+ 2240 => x"8c08ffa0",
+ 2241 => x"050883ff",
+ 2242 => x"ff067072",
+ 2243 => x"078c08fe",
+ 2244 => x"ec050c52",
+ 2245 => x"58515154",
+ 2246 => x"8c08feec",
+ 2247 => x"05088c08",
+ 2248 => x"fee80508",
+ 2249 => x"2780e138",
+ 2250 => x"8c08ff84",
+ 2251 => x"0508ff05",
+ 2252 => x"8c08ff84",
+ 2253 => x"050c8c08",
+ 2254 => x"feec0508",
+ 2255 => x"8c08ffa8",
+ 2256 => x"0508058c",
+ 2257 => x"08feec05",
+ 2258 => x"0c8c08ff",
+ 2259 => x"a805088c",
+ 2260 => x"08feec05",
+ 2261 => x"0826b138",
+ 2262 => x"8c08feec",
+ 2263 => x"05088c08",
+ 2264 => x"fee80508",
+ 2265 => x"27a2388c",
+ 2266 => x"08ff8405",
+ 2267 => x"08ff058c",
+ 2268 => x"08ff8405",
+ 2269 => x"0c8c08fe",
+ 2270 => x"ec05088c",
+ 2271 => x"08ffa805",
+ 2272 => x"08058c08",
+ 2273 => x"feec050c",
+ 2274 => x"8c08feec",
+ 2275 => x"05088c08",
+ 2276 => x"fee80508",
+ 2277 => x"318c08fe",
+ 2278 => x"ec050c8c",
+ 2279 => x"08ff8005",
+ 2280 => x"0870902b",
+ 2281 => x"708c08ff",
+ 2282 => x"84050807",
+ 2283 => x"8c08ff98",
+ 2284 => x"050c8c08",
+ 2285 => x"feec0508",
+ 2286 => x"8c08ffa0",
+ 2287 => x"050c8c08",
+ 2288 => x"ff980508",
+ 2289 => x"83ffff06",
+ 2290 => x"8c08ff80",
+ 2291 => x"050c8c08",
+ 2292 => x"ff980508",
+ 2293 => x"902a8c08",
+ 2294 => x"ff88050c",
+ 2295 => x"8c08ffac",
+ 2296 => x"050883ff",
+ 2297 => x"ff068c08",
+ 2298 => x"ff84050c",
+ 2299 => x"8c08ffac",
+ 2300 => x"0508902a",
+ 2301 => x"8c08fee4",
+ 2302 => x"050c8c08",
+ 2303 => x"ff800508",
+ 2304 => x"8c08ff84",
+ 2305 => x"05082970",
+ 2306 => x"8c08fee8",
+ 2307 => x"050c8c08",
+ 2308 => x"ff800508",
+ 2309 => x"8c08fee4",
+ 2310 => x"05082970",
+ 2311 => x"8c08feec",
+ 2312 => x"050c8c08",
+ 2313 => x"ff880508",
+ 2314 => x"8c08ff84",
+ 2315 => x"05082970",
+ 2316 => x"8c08fef8",
+ 2317 => x"050c8c08",
+ 2318 => x"ff880508",
+ 2319 => x"8c08fee4",
+ 2320 => x"05082970",
+ 2321 => x"8c08fefc",
+ 2322 => x"050c8c08",
+ 2323 => x"fee80508",
+ 2324 => x"902a8c08",
+ 2325 => x"feec0508",
+ 2326 => x"118c08fe",
+ 2327 => x"ec050c8c",
+ 2328 => x"08feec05",
+ 2329 => x"088c08fe",
+ 2330 => x"f8050805",
+ 2331 => x"8c08feec",
+ 2332 => x"050c5151",
+ 2333 => x"51515151",
+ 2334 => x"548c08fe",
+ 2335 => x"ec05088c",
+ 2336 => x"08fef805",
+ 2337 => x"08279138",
+ 2338 => x"8c08fefc",
+ 2339 => x"05088480",
+ 2340 => x"80058c08",
+ 2341 => x"fefc050c",
+ 2342 => x"8c08feec",
+ 2343 => x"0508902a",
+ 2344 => x"8c08fefc",
+ 2345 => x"0508118c",
+ 2346 => x"08fef005",
+ 2347 => x"0c8c08fe",
+ 2348 => x"ec050883",
+ 2349 => x"ffff0670",
+ 2350 => x"902b8c08",
+ 2351 => x"fee80508",
+ 2352 => x"83ffff06",
+ 2353 => x"70128c08",
+ 2354 => x"fef4050c",
+ 2355 => x"52575154",
+ 2356 => x"8c08fef0",
+ 2357 => x"05088c08",
+ 2358 => x"ffa00508",
+ 2359 => x"26a6388c",
+ 2360 => x"08fef005",
+ 2361 => x"088c08ff",
+ 2362 => x"a005082e",
+ 2363 => x"09810680",
+ 2364 => x"fe388c08",
+ 2365 => x"fef40508",
+ 2366 => x"8c08ffa4",
+ 2367 => x"05082684",
+ 2368 => x"3880ec39",
+ 2369 => x"8c08ff98",
+ 2370 => x"0508ff05",
+ 2371 => x"8c08ff98",
+ 2372 => x"050c8c08",
+ 2373 => x"fef40508",
+ 2374 => x"8c08ffac",
+ 2375 => x"0508318c",
+ 2376 => x"08fee405",
+ 2377 => x"0c8c08fe",
+ 2378 => x"f005088c",
+ 2379 => x"08ffa805",
+ 2380 => x"0831708c",
+ 2381 => x"08fec805",
+ 2382 => x"0c548c08",
+ 2383 => x"fef40508",
+ 2384 => x"8c08fee4",
+ 2385 => x"0508278f",
+ 2386 => x"388c08fe",
+ 2387 => x"c80508ff",
+ 2388 => x"058c08fe",
+ 2389 => x"c8050c8c",
+ 2390 => x"08fec805",
+ 2391 => x"088c08fe",
+ 2392 => x"f0050c8c",
+ 2393 => x"08fee405",
+ 2394 => x"088c08fe",
+ 2395 => x"f4050c80",
+ 2396 => x"0b8c08ff",
+ 2397 => x"94050c8c",
+ 2398 => x"08c80508",
+ 2399 => x"802e81b1",
+ 2400 => x"388c08ff",
+ 2401 => x"a405088c",
+ 2402 => x"08fef405",
+ 2403 => x"08318c08",
+ 2404 => x"fee4050c",
+ 2405 => x"8c08ffa0",
+ 2406 => x"05088c08",
+ 2407 => x"fef00508",
+ 2408 => x"31708c08",
+ 2409 => x"fec4050c",
+ 2410 => x"548c08ff",
+ 2411 => x"a405088c",
+ 2412 => x"08fee405",
+ 2413 => x"08278f38",
+ 2414 => x"8c08fec4",
+ 2415 => x"0508ff05",
+ 2416 => x"8c08fec4",
+ 2417 => x"050c8c08",
+ 2418 => x"fec40508",
+ 2419 => x"8c08ffa0",
+ 2420 => x"050c8c08",
+ 2421 => x"fee40508",
+ 2422 => x"8c08ffa4",
+ 2423 => x"050c8c08",
+ 2424 => x"ffa00508",
+ 2425 => x"8c08ff90",
+ 2426 => x"05082b8c",
+ 2427 => x"08ffa405",
+ 2428 => x"088c08ff",
+ 2429 => x"8c05082a",
+ 2430 => x"7072078c",
+ 2431 => x"08ffb405",
+ 2432 => x"0c8c08ff",
+ 2433 => x"a005088c",
+ 2434 => x"08ff8c05",
+ 2435 => x"082a8c08",
+ 2436 => x"ffb0050c",
+ 2437 => x"8c08c805",
+ 2438 => x"08585555",
+ 2439 => x"8c08ffb0",
+ 2440 => x"05088c08",
+ 2441 => x"ffb40508",
+ 2442 => x"56547376",
+ 2443 => x"0c748417",
+ 2444 => x"0c800b8c",
+ 2445 => x"08fedc05",
+ 2446 => x"0c800b8c",
+ 2447 => x"08fee005",
+ 2448 => x"0c8c08ff",
+ 2449 => x"9405088c",
+ 2450 => x"08fedc05",
+ 2451 => x"0c8c08ff",
+ 2452 => x"9805088c",
+ 2453 => x"08fee005",
+ 2454 => x"0c8c08fe",
+ 2455 => x"dc05088c",
+ 2456 => x"08fee005",
+ 2457 => x"08565473",
+ 2458 => x"8c08c005",
+ 2459 => x"0c748c08",
+ 2460 => x"c4050c8c",
+ 2461 => x"08c00508",
+ 2462 => x"8c08c405",
+ 2463 => x"08565473",
+ 2464 => x"8c08dc05",
+ 2465 => x"0c748c08",
+ 2466 => x"e0050c8c",
+ 2467 => x"08fc0508",
+ 2468 => x"802eb338",
+ 2469 => x"8c08c005",
+ 2470 => x"548c08dc",
+ 2471 => x"05088c08",
+ 2472 => x"e0050857",
+ 2473 => x"55745275",
+ 2474 => x"537351d8",
+ 2475 => x"d73f8c08",
+ 2476 => x"c005088c",
+ 2477 => x"08c40508",
+ 2478 => x"5654738c",
+ 2479 => x"08dc050c",
+ 2480 => x"748c08e0",
+ 2481 => x"050c8c08",
+ 2482 => x"dc05088c",
+ 2483 => x"08e00508",
+ 2484 => x"8c088805",
+ 2485 => x"08585654",
+ 2486 => x"73760c74",
+ 2487 => x"84170c8c",
+ 2488 => x"08880508",
+ 2489 => x"800cb63d",
+ 2490 => x"0d8c0c04",
+ 2491 => x"8c08028c",
+ 2492 => x"0cfd3d0d",
+ 2493 => x"80538c08",
+ 2494 => x"8c050852",
+ 2495 => x"8c088805",
+ 2496 => x"085182de",
+ 2497 => x"3f800870",
+ 2498 => x"800c5485",
+ 2499 => x"3d0d8c0c",
+ 2500 => x"048c0802",
+ 2501 => x"8c0cfd3d",
+ 2502 => x"0d81538c",
+ 2503 => x"088c0508",
+ 2504 => x"528c0888",
+ 2505 => x"05085182",
+ 2506 => x"b93f8008",
+ 2507 => x"70800c54",
+ 2508 => x"853d0d8c",
+ 2509 => x"0c048c08",
+ 2510 => x"028c0cf9",
+ 2511 => x"3d0d800b",
+ 2512 => x"8c08fc05",
+ 2513 => x"0c8c0888",
+ 2514 => x"05088025",
+ 2515 => x"ab388c08",
+ 2516 => x"88050830",
+ 2517 => x"8c088805",
+ 2518 => x"0c800b8c",
+ 2519 => x"08f4050c",
+ 2520 => x"8c08fc05",
+ 2521 => x"08883881",
+ 2522 => x"0b8c08f4",
+ 2523 => x"050c8c08",
+ 2524 => x"f405088c",
+ 2525 => x"08fc050c",
+ 2526 => x"8c088c05",
+ 2527 => x"088025ab",
+ 2528 => x"388c088c",
+ 2529 => x"0508308c",
+ 2530 => x"088c050c",
+ 2531 => x"800b8c08",
+ 2532 => x"f0050c8c",
+ 2533 => x"08fc0508",
+ 2534 => x"8838810b",
+ 2535 => x"8c08f005",
+ 2536 => x"0c8c08f0",
+ 2537 => x"05088c08",
+ 2538 => x"fc050c80",
+ 2539 => x"538c088c",
+ 2540 => x"0508528c",
+ 2541 => x"08880508",
+ 2542 => x"5181a73f",
+ 2543 => x"8008708c",
+ 2544 => x"08f8050c",
+ 2545 => x"548c08fc",
+ 2546 => x"0508802e",
+ 2547 => x"8c388c08",
+ 2548 => x"f8050830",
+ 2549 => x"8c08f805",
+ 2550 => x"0c8c08f8",
+ 2551 => x"05087080",
+ 2552 => x"0c54893d",
+ 2553 => x"0d8c0c04",
+ 2554 => x"8c08028c",
+ 2555 => x"0cfb3d0d",
+ 2556 => x"800b8c08",
+ 2557 => x"fc050c8c",
+ 2558 => x"08880508",
+ 2559 => x"80259338",
+ 2560 => x"8c088805",
+ 2561 => x"08308c08",
+ 2562 => x"88050c81",
+ 2563 => x"0b8c08fc",
+ 2564 => x"050c8c08",
+ 2565 => x"8c050880",
+ 2566 => x"258c388c",
+ 2567 => x"088c0508",
+ 2568 => x"308c088c",
+ 2569 => x"050c8153",
+ 2570 => x"8c088c05",
+ 2571 => x"08528c08",
+ 2572 => x"88050851",
+ 2573 => x"ad3f8008",
+ 2574 => x"708c08f8",
+ 2575 => x"050c548c",
+ 2576 => x"08fc0508",
+ 2577 => x"802e8c38",
+ 2578 => x"8c08f805",
+ 2579 => x"08308c08",
+ 2580 => x"f8050c8c",
+ 2581 => x"08f80508",
+ 2582 => x"70800c54",
+ 2583 => x"873d0d8c",
+ 2584 => x"0c048c08",
+ 2585 => x"028c0cfd",
+ 2586 => x"3d0d810b",
+ 2587 => x"8c08fc05",
+ 2588 => x"0c800b8c",
+ 2589 => x"08f8050c",
+ 2590 => x"8c088c05",
+ 2591 => x"088c0888",
+ 2592 => x"050827ac",
+ 2593 => x"388c08fc",
+ 2594 => x"0508802e",
+ 2595 => x"a338800b",
+ 2596 => x"8c088c05",
+ 2597 => x"08249938",
+ 2598 => x"8c088c05",
+ 2599 => x"08108c08",
+ 2600 => x"8c050c8c",
+ 2601 => x"08fc0508",
+ 2602 => x"108c08fc",
+ 2603 => x"050cc939",
+ 2604 => x"8c08fc05",
+ 2605 => x"08802e80",
+ 2606 => x"c9388c08",
+ 2607 => x"8c05088c",
+ 2608 => x"08880508",
+ 2609 => x"26a1388c",
+ 2610 => x"08880508",
+ 2611 => x"8c088c05",
+ 2612 => x"08318c08",
+ 2613 => x"88050c8c",
+ 2614 => x"08f80508",
+ 2615 => x"8c08fc05",
+ 2616 => x"08078c08",
+ 2617 => x"f8050c8c",
+ 2618 => x"08fc0508",
+ 2619 => x"812a8c08",
+ 2620 => x"fc050c8c",
+ 2621 => x"088c0508",
+ 2622 => x"812a8c08",
+ 2623 => x"8c050cff",
+ 2624 => x"af398c08",
+ 2625 => x"90050880",
+ 2626 => x"2e8f388c",
+ 2627 => x"08880508",
+ 2628 => x"708c08f4",
+ 2629 => x"050c518d",
+ 2630 => x"398c08f8",
+ 2631 => x"0508708c",
+ 2632 => x"08f4050c",
+ 2633 => x"518c08f4",
+ 2634 => x"0508800c",
+ 2635 => x"853d0d8c",
+ 2636 => x"0c04ff3d",
+ 2637 => x"0d735281",
+ 2638 => x"81c80851",
+ 2639 => x"963f833d",
+ 2640 => x"0d04ff3d",
+ 2641 => x"0d735281",
+ 2642 => x"81c80851",
+ 2643 => x"90953f83",
+ 2644 => x"3d0d04f3",
+ 2645 => x"3d0d7f61",
+ 2646 => x"8b1170f8",
+ 2647 => x"065c5555",
+ 2648 => x"5e729626",
+ 2649 => x"83389059",
+ 2650 => x"80792474",
+ 2651 => x"7a260753",
+ 2652 => x"80547274",
+ 2653 => x"2e098106",
+ 2654 => x"80cb387d",
+ 2655 => x"518ce33f",
+ 2656 => x"7883f726",
+ 2657 => x"80c63878",
+ 2658 => x"832a7010",
+ 2659 => x"101080f9",
+ 2660 => x"c0058c11",
+ 2661 => x"0859595a",
+ 2662 => x"76782e83",
+ 2663 => x"b0388417",
+ 2664 => x"08fc0656",
+ 2665 => x"8c170888",
+ 2666 => x"1808718c",
+ 2667 => x"120c8812",
+ 2668 => x"0c587517",
+ 2669 => x"84110881",
+ 2670 => x"0784120c",
+ 2671 => x"537d518c",
+ 2672 => x"a23f8817",
+ 2673 => x"5473800c",
+ 2674 => x"8f3d0d04",
+ 2675 => x"78892a79",
+ 2676 => x"832a5b53",
+ 2677 => x"72802ebf",
+ 2678 => x"3878862a",
+ 2679 => x"b8055a84",
+ 2680 => x"7327b438",
+ 2681 => x"80db135a",
+ 2682 => x"947327ab",
+ 2683 => x"38788c2a",
+ 2684 => x"80ee055a",
+ 2685 => x"80d47327",
+ 2686 => x"9e38788f",
+ 2687 => x"2a80f705",
+ 2688 => x"5a82d473",
+ 2689 => x"27913878",
+ 2690 => x"922a80fc",
+ 2691 => x"055a8ad4",
+ 2692 => x"73278438",
+ 2693 => x"80fe5a79",
+ 2694 => x"10101080",
+ 2695 => x"f9c0058c",
+ 2696 => x"11085855",
+ 2697 => x"76752ea3",
+ 2698 => x"38841708",
+ 2699 => x"fc06707a",
+ 2700 => x"31555673",
+ 2701 => x"8f2488d5",
+ 2702 => x"38738025",
+ 2703 => x"fee6388c",
+ 2704 => x"17085776",
+ 2705 => x"752e0981",
+ 2706 => x"06df3881",
+ 2707 => x"1a5a80f9",
+ 2708 => x"d0085776",
+ 2709 => x"80f9c82e",
+ 2710 => x"82c03884",
+ 2711 => x"1708fc06",
+ 2712 => x"707a3155",
+ 2713 => x"56738f24",
+ 2714 => x"81f93880",
+ 2715 => x"f9c80b80",
+ 2716 => x"f9d40c80",
+ 2717 => x"f9c80b80",
+ 2718 => x"f9d00c73",
+ 2719 => x"8025feb2",
+ 2720 => x"3883ff76",
+ 2721 => x"2783df38",
+ 2722 => x"75892a76",
+ 2723 => x"832a5553",
+ 2724 => x"72802ebf",
+ 2725 => x"3875862a",
+ 2726 => x"b8055484",
+ 2727 => x"7327b438",
+ 2728 => x"80db1354",
+ 2729 => x"947327ab",
+ 2730 => x"38758c2a",
+ 2731 => x"80ee0554",
+ 2732 => x"80d47327",
+ 2733 => x"9e38758f",
+ 2734 => x"2a80f705",
+ 2735 => x"5482d473",
+ 2736 => x"27913875",
+ 2737 => x"922a80fc",
+ 2738 => x"05548ad4",
+ 2739 => x"73278438",
+ 2740 => x"80fe5473",
+ 2741 => x"10101080",
+ 2742 => x"f9c00588",
+ 2743 => x"11085658",
+ 2744 => x"74782e86",
+ 2745 => x"cf388415",
+ 2746 => x"08fc0653",
+ 2747 => x"7573278d",
+ 2748 => x"38881508",
+ 2749 => x"5574782e",
+ 2750 => x"098106ea",
+ 2751 => x"388c1508",
+ 2752 => x"80f9c00b",
+ 2753 => x"84050871",
+ 2754 => x"8c1a0c76",
+ 2755 => x"881a0c78",
+ 2756 => x"88130c78",
+ 2757 => x"8c180c5d",
+ 2758 => x"58795380",
+ 2759 => x"7a2483e6",
+ 2760 => x"3872822c",
+ 2761 => x"81712b5c",
+ 2762 => x"537a7c26",
+ 2763 => x"8198387b",
+ 2764 => x"7b065372",
+ 2765 => x"82f13879",
+ 2766 => x"fc068405",
+ 2767 => x"5a7a1070",
+ 2768 => x"7d06545b",
+ 2769 => x"7282e038",
+ 2770 => x"841a5af1",
+ 2771 => x"3988178c",
+ 2772 => x"11085858",
+ 2773 => x"76782e09",
+ 2774 => x"8106fcc2",
+ 2775 => x"38821a5a",
+ 2776 => x"fdec3978",
+ 2777 => x"17798107",
+ 2778 => x"84190c70",
+ 2779 => x"80f9d40c",
+ 2780 => x"7080f9d0",
+ 2781 => x"0c80f9c8",
+ 2782 => x"0b8c120c",
+ 2783 => x"8c110888",
+ 2784 => x"120c7481",
+ 2785 => x"0784120c",
+ 2786 => x"74117571",
+ 2787 => x"0c51537d",
+ 2788 => x"5188d03f",
+ 2789 => x"881754fc",
+ 2790 => x"ac3980f9",
+ 2791 => x"c00b8405",
+ 2792 => x"087a545c",
+ 2793 => x"798025fe",
+ 2794 => x"f83882da",
+ 2795 => x"397a097c",
+ 2796 => x"067080f9",
+ 2797 => x"c00b8405",
+ 2798 => x"0c5c7a10",
+ 2799 => x"5b7a7c26",
+ 2800 => x"85387a85",
+ 2801 => x"b83880f9",
+ 2802 => x"c00b8805",
+ 2803 => x"08708412",
+ 2804 => x"08fc0670",
+ 2805 => x"7c317c72",
+ 2806 => x"268f7225",
+ 2807 => x"0757575c",
+ 2808 => x"5d557280",
+ 2809 => x"2e80db38",
+ 2810 => x"797a1680",
+ 2811 => x"f9b8081b",
+ 2812 => x"90115a55",
+ 2813 => x"575b80f9",
+ 2814 => x"b408ff2e",
+ 2815 => x"8838a08f",
+ 2816 => x"13e08006",
+ 2817 => x"5776527d",
+ 2818 => x"5187d93f",
+ 2819 => x"80085480",
+ 2820 => x"08ff2e90",
+ 2821 => x"38800876",
+ 2822 => x"27829938",
+ 2823 => x"7480f9c0",
+ 2824 => x"2e829138",
+ 2825 => x"80f9c00b",
+ 2826 => x"88050855",
+ 2827 => x"841508fc",
+ 2828 => x"06707a31",
+ 2829 => x"7a72268f",
+ 2830 => x"72250752",
+ 2831 => x"55537283",
+ 2832 => x"e6387479",
+ 2833 => x"81078417",
+ 2834 => x"0c791670",
+ 2835 => x"80f9c00b",
+ 2836 => x"88050c75",
+ 2837 => x"81078412",
+ 2838 => x"0c547e52",
+ 2839 => x"5787843f",
+ 2840 => x"881754fa",
+ 2841 => x"e0397583",
+ 2842 => x"2a705454",
+ 2843 => x"80742481",
+ 2844 => x"9b387282",
+ 2845 => x"2c81712b",
+ 2846 => x"80f9c408",
+ 2847 => x"077080f9",
+ 2848 => x"c00b8405",
+ 2849 => x"0c751010",
+ 2850 => x"1080f9c0",
+ 2851 => x"05881108",
+ 2852 => x"585a5d53",
+ 2853 => x"778c180c",
+ 2854 => x"7488180c",
+ 2855 => x"7688190c",
+ 2856 => x"768c160c",
+ 2857 => x"fcf33979",
+ 2858 => x"7a101010",
+ 2859 => x"80f9c005",
+ 2860 => x"7057595d",
+ 2861 => x"8c150857",
+ 2862 => x"76752ea3",
+ 2863 => x"38841708",
+ 2864 => x"fc06707a",
+ 2865 => x"31555673",
+ 2866 => x"8f2483ca",
+ 2867 => x"38738025",
+ 2868 => x"8481388c",
+ 2869 => x"17085776",
+ 2870 => x"752e0981",
+ 2871 => x"06df3888",
+ 2872 => x"15811b70",
+ 2873 => x"8306555b",
+ 2874 => x"5572c938",
+ 2875 => x"7c830653",
+ 2876 => x"72802efd",
+ 2877 => x"b838ff1d",
+ 2878 => x"f819595d",
+ 2879 => x"88180878",
+ 2880 => x"2eea38fd",
+ 2881 => x"b539831a",
+ 2882 => x"53fc9639",
+ 2883 => x"83147082",
+ 2884 => x"2c81712b",
+ 2885 => x"80f9c408",
+ 2886 => x"077080f9",
+ 2887 => x"c00b8405",
+ 2888 => x"0c761010",
+ 2889 => x"1080f9c0",
+ 2890 => x"05881108",
+ 2891 => x"595b5e51",
+ 2892 => x"53fee139",
+ 2893 => x"80f98408",
+ 2894 => x"17588008",
+ 2895 => x"762e818d",
+ 2896 => x"3880f9b4",
+ 2897 => x"08ff2e83",
+ 2898 => x"ec387376",
+ 2899 => x"311880f9",
+ 2900 => x"840c7387",
+ 2901 => x"06705753",
+ 2902 => x"72802e88",
+ 2903 => x"38887331",
+ 2904 => x"70155556",
+ 2905 => x"76149fff",
+ 2906 => x"06a08071",
+ 2907 => x"31177054",
+ 2908 => x"7f535753",
+ 2909 => x"84ee3f80",
+ 2910 => x"08538008",
+ 2911 => x"ff2e81a0",
+ 2912 => x"3880f984",
+ 2913 => x"08167080",
+ 2914 => x"f9840c74",
+ 2915 => x"7580f9c0",
+ 2916 => x"0b88050c",
+ 2917 => x"74763118",
+ 2918 => x"70810751",
+ 2919 => x"5556587b",
+ 2920 => x"80f9c02e",
+ 2921 => x"839c3879",
+ 2922 => x"8f2682cb",
+ 2923 => x"38810b84",
+ 2924 => x"150c8415",
+ 2925 => x"08fc0670",
+ 2926 => x"7a317a72",
+ 2927 => x"268f7225",
+ 2928 => x"07525553",
+ 2929 => x"72802efc",
+ 2930 => x"f93880db",
+ 2931 => x"3980089f",
+ 2932 => x"ff065372",
+ 2933 => x"feeb3877",
+ 2934 => x"80f9840c",
+ 2935 => x"80f9c00b",
+ 2936 => x"8805087b",
+ 2937 => x"18810784",
+ 2938 => x"120c5580",
+ 2939 => x"f9b00878",
+ 2940 => x"27863877",
+ 2941 => x"80f9b00c",
+ 2942 => x"80f9ac08",
+ 2943 => x"7827fcac",
+ 2944 => x"387780f9",
+ 2945 => x"ac0c8415",
+ 2946 => x"08fc0670",
+ 2947 => x"7a317a72",
+ 2948 => x"268f7225",
+ 2949 => x"07525553",
+ 2950 => x"72802efc",
+ 2951 => x"a5388839",
+ 2952 => x"80745456",
+ 2953 => x"fedb397d",
+ 2954 => x"5183b83f",
+ 2955 => x"800b800c",
+ 2956 => x"8f3d0d04",
+ 2957 => x"73538074",
+ 2958 => x"24a93872",
+ 2959 => x"822c8171",
+ 2960 => x"2b80f9c4",
+ 2961 => x"08077080",
+ 2962 => x"f9c00b84",
+ 2963 => x"050c5d53",
+ 2964 => x"778c180c",
+ 2965 => x"7488180c",
+ 2966 => x"7688190c",
+ 2967 => x"768c160c",
+ 2968 => x"f9b73983",
+ 2969 => x"1470822c",
+ 2970 => x"81712b80",
+ 2971 => x"f9c40807",
+ 2972 => x"7080f9c0",
+ 2973 => x"0b84050c",
+ 2974 => x"5e5153d4",
+ 2975 => x"397b7b06",
+ 2976 => x"5372fca3",
+ 2977 => x"38841a7b",
+ 2978 => x"105c5af1",
+ 2979 => x"39ff1a81",
+ 2980 => x"11515af7",
+ 2981 => x"b9397817",
+ 2982 => x"79810784",
+ 2983 => x"190c8c18",
+ 2984 => x"08881908",
+ 2985 => x"718c120c",
+ 2986 => x"88120c59",
+ 2987 => x"7080f9d4",
+ 2988 => x"0c7080f9",
+ 2989 => x"d00c80f9",
+ 2990 => x"c80b8c12",
+ 2991 => x"0c8c1108",
+ 2992 => x"88120c74",
+ 2993 => x"81078412",
+ 2994 => x"0c741175",
+ 2995 => x"710c5153",
+ 2996 => x"f9bd3975",
+ 2997 => x"17841108",
+ 2998 => x"81078412",
+ 2999 => x"0c538c17",
+ 3000 => x"08881808",
+ 3001 => x"718c120c",
+ 3002 => x"88120c58",
+ 3003 => x"7d5181f3",
+ 3004 => x"3f881754",
+ 3005 => x"f5cf3972",
+ 3006 => x"84150cf4",
+ 3007 => x"1af80670",
+ 3008 => x"841e0881",
+ 3009 => x"0607841e",
+ 3010 => x"0c701d54",
+ 3011 => x"5b850b84",
+ 3012 => x"140c850b",
+ 3013 => x"88140c8f",
+ 3014 => x"7b27fdcf",
+ 3015 => x"38881c52",
+ 3016 => x"7d5184bf",
+ 3017 => x"3f80f9c0",
+ 3018 => x"0b880508",
+ 3019 => x"80f98408",
+ 3020 => x"5955fdb7",
+ 3021 => x"397780f9",
+ 3022 => x"840c7380",
+ 3023 => x"f9b40cfc",
+ 3024 => x"91397284",
+ 3025 => x"150cfda3",
+ 3026 => x"39fc3d0d",
+ 3027 => x"7670797b",
+ 3028 => x"55555555",
+ 3029 => x"8f72278c",
+ 3030 => x"38727507",
+ 3031 => x"83065170",
+ 3032 => x"802ea738",
+ 3033 => x"ff125271",
+ 3034 => x"ff2e9838",
+ 3035 => x"72708105",
+ 3036 => x"54337470",
+ 3037 => x"81055634",
+ 3038 => x"ff125271",
+ 3039 => x"ff2e0981",
+ 3040 => x"06ea3874",
+ 3041 => x"800c863d",
+ 3042 => x"0d047451",
+ 3043 => x"72708405",
+ 3044 => x"54087170",
+ 3045 => x"8405530c",
+ 3046 => x"72708405",
+ 3047 => x"54087170",
+ 3048 => x"8405530c",
+ 3049 => x"72708405",
+ 3050 => x"54087170",
+ 3051 => x"8405530c",
+ 3052 => x"72708405",
+ 3053 => x"54087170",
+ 3054 => x"8405530c",
+ 3055 => x"f0125271",
+ 3056 => x"8f26c938",
+ 3057 => x"83722795",
+ 3058 => x"38727084",
+ 3059 => x"05540871",
+ 3060 => x"70840553",
+ 3061 => x"0cfc1252",
+ 3062 => x"718326ed",
+ 3063 => x"387054ff",
+ 3064 => x"83390404",
+ 3065 => x"fd3d0d80",
+ 3066 => x"0b81d998",
+ 3067 => x"0c765187",
+ 3068 => x"c83f8008",
+ 3069 => x"538008ff",
+ 3070 => x"2e883872",
+ 3071 => x"800c853d",
+ 3072 => x"0d0481d9",
+ 3073 => x"98085473",
+ 3074 => x"802ef038",
+ 3075 => x"7574710c",
+ 3076 => x"5272800c",
+ 3077 => x"853d0d04",
+ 3078 => x"fb3d0d77",
+ 3079 => x"79707207",
+ 3080 => x"83065354",
+ 3081 => x"52709338",
+ 3082 => x"71737308",
+ 3083 => x"54565471",
+ 3084 => x"73082e80",
+ 3085 => x"c4387375",
+ 3086 => x"54527133",
+ 3087 => x"7081ff06",
+ 3088 => x"52547080",
+ 3089 => x"2e9d3872",
+ 3090 => x"33557075",
+ 3091 => x"2e098106",
+ 3092 => x"95388112",
+ 3093 => x"81147133",
+ 3094 => x"7081ff06",
+ 3095 => x"54565452",
+ 3096 => x"70e53872",
+ 3097 => x"33557381",
+ 3098 => x"ff067581",
+ 3099 => x"ff067171",
+ 3100 => x"31800c52",
+ 3101 => x"52873d0d",
+ 3102 => x"04710970",
+ 3103 => x"f7fbfdff",
+ 3104 => x"140670f8",
+ 3105 => x"84828180",
+ 3106 => x"06515151",
+ 3107 => x"70973884",
+ 3108 => x"14841671",
+ 3109 => x"08545654",
+ 3110 => x"7175082e",
+ 3111 => x"dc387375",
+ 3112 => x"5452ff96",
+ 3113 => x"39800b80",
+ 3114 => x"0c873d0d",
+ 3115 => x"04fb3d0d",
+ 3116 => x"77705256",
+ 3117 => x"feac3f80",
+ 3118 => x"f9c00b88",
+ 3119 => x"05088411",
+ 3120 => x"08fc0670",
+ 3121 => x"7b319fef",
+ 3122 => x"05e08006",
+ 3123 => x"e0800556",
+ 3124 => x"5653a080",
+ 3125 => x"74249438",
+ 3126 => x"80527551",
+ 3127 => x"fe863f80",
+ 3128 => x"f9c80815",
+ 3129 => x"53728008",
+ 3130 => x"2e8f3875",
+ 3131 => x"51fdf43f",
+ 3132 => x"80537280",
+ 3133 => x"0c873d0d",
+ 3134 => x"04733052",
+ 3135 => x"7551fde4",
+ 3136 => x"3f8008ff",
+ 3137 => x"2ea83880",
+ 3138 => x"f9c00b88",
+ 3139 => x"05087575",
+ 3140 => x"31810784",
+ 3141 => x"120c5380",
+ 3142 => x"f9840874",
+ 3143 => x"3180f984",
+ 3144 => x"0c7551fd",
+ 3145 => x"be3f810b",
+ 3146 => x"800c873d",
+ 3147 => x"0d048052",
+ 3148 => x"7551fdb0",
+ 3149 => x"3f80f9c0",
+ 3150 => x"0b880508",
+ 3151 => x"80087131",
+ 3152 => x"56538f75",
+ 3153 => x"25ffa438",
+ 3154 => x"800880f9",
+ 3155 => x"b4083180",
+ 3156 => x"f9840c74",
+ 3157 => x"81078414",
+ 3158 => x"0c7551fd",
+ 3159 => x"863f8053",
+ 3160 => x"ff9039f6",
+ 3161 => x"3d0d7c7e",
+ 3162 => x"545b7280",
+ 3163 => x"2e828338",
+ 3164 => x"7a51fcee",
+ 3165 => x"3ff81384",
+ 3166 => x"110870fe",
+ 3167 => x"06701384",
+ 3168 => x"1108fc06",
+ 3169 => x"5d585954",
+ 3170 => x"5880f9c8",
+ 3171 => x"08752e82",
+ 3172 => x"de387884",
+ 3173 => x"160c8073",
+ 3174 => x"8106545a",
+ 3175 => x"727a2e81",
+ 3176 => x"d5387815",
+ 3177 => x"84110881",
+ 3178 => x"06515372",
+ 3179 => x"a0387817",
+ 3180 => x"577981e6",
+ 3181 => x"38881508",
+ 3182 => x"537280f9",
+ 3183 => x"c82e82f9",
+ 3184 => x"388c1508",
+ 3185 => x"708c150c",
+ 3186 => x"7388120c",
+ 3187 => x"56768107",
+ 3188 => x"84190c76",
+ 3189 => x"1877710c",
+ 3190 => x"53798191",
+ 3191 => x"3883ff77",
+ 3192 => x"2781c838",
+ 3193 => x"76892a77",
+ 3194 => x"832a5653",
+ 3195 => x"72802ebf",
+ 3196 => x"3876862a",
+ 3197 => x"b8055584",
+ 3198 => x"7327b438",
+ 3199 => x"80db1355",
+ 3200 => x"947327ab",
+ 3201 => x"38768c2a",
+ 3202 => x"80ee0555",
+ 3203 => x"80d47327",
+ 3204 => x"9e38768f",
+ 3205 => x"2a80f705",
+ 3206 => x"5582d473",
+ 3207 => x"27913876",
+ 3208 => x"922a80fc",
+ 3209 => x"05558ad4",
+ 3210 => x"73278438",
+ 3211 => x"80fe5574",
+ 3212 => x"10101080",
+ 3213 => x"f9c00588",
+ 3214 => x"11085556",
+ 3215 => x"73762e82",
+ 3216 => x"b3388414",
+ 3217 => x"08fc0653",
+ 3218 => x"7673278d",
+ 3219 => x"38881408",
+ 3220 => x"5473762e",
+ 3221 => x"098106ea",
+ 3222 => x"388c1408",
+ 3223 => x"708c1a0c",
+ 3224 => x"74881a0c",
+ 3225 => x"7888120c",
+ 3226 => x"56778c15",
+ 3227 => x"0c7a51fa",
+ 3228 => x"f23f8c3d",
+ 3229 => x"0d047708",
+ 3230 => x"78713159",
+ 3231 => x"77058819",
+ 3232 => x"08545772",
+ 3233 => x"80f9c82e",
+ 3234 => x"80e0388c",
+ 3235 => x"1808708c",
+ 3236 => x"150c7388",
+ 3237 => x"120c56fe",
+ 3238 => x"89398815",
+ 3239 => x"088c1608",
+ 3240 => x"708c130c",
+ 3241 => x"5788170c",
+ 3242 => x"fea33976",
+ 3243 => x"832a7054",
+ 3244 => x"55807524",
+ 3245 => x"81983872",
+ 3246 => x"822c8171",
+ 3247 => x"2b80f9c4",
+ 3248 => x"080780f9",
+ 3249 => x"c00b8405",
+ 3250 => x"0c537410",
+ 3251 => x"101080f9",
+ 3252 => x"c0058811",
+ 3253 => x"08555675",
+ 3254 => x"8c190c73",
+ 3255 => x"88190c77",
+ 3256 => x"88170c77",
+ 3257 => x"8c150cff",
+ 3258 => x"8439815a",
+ 3259 => x"fdb43978",
+ 3260 => x"17738106",
+ 3261 => x"54577298",
+ 3262 => x"38770878",
+ 3263 => x"71315977",
+ 3264 => x"058c1908",
+ 3265 => x"881a0871",
+ 3266 => x"8c120c88",
+ 3267 => x"120c5757",
+ 3268 => x"76810784",
+ 3269 => x"190c7780",
+ 3270 => x"f9c00b88",
+ 3271 => x"050c80f9",
+ 3272 => x"bc087726",
+ 3273 => x"fec73880",
+ 3274 => x"f9b80852",
+ 3275 => x"7a51fafd",
+ 3276 => x"3f7a51f9",
+ 3277 => x"ae3ffeba",
+ 3278 => x"3981788c",
+ 3279 => x"150c7888",
+ 3280 => x"150c738c",
+ 3281 => x"1a0c7388",
+ 3282 => x"1a0c5afd",
+ 3283 => x"80398315",
+ 3284 => x"70822c81",
+ 3285 => x"712b80f9",
+ 3286 => x"c4080780",
+ 3287 => x"f9c00b84",
+ 3288 => x"050c5153",
+ 3289 => x"74101010",
+ 3290 => x"80f9c005",
+ 3291 => x"88110855",
+ 3292 => x"56fee439",
+ 3293 => x"74538075",
+ 3294 => x"24a73872",
+ 3295 => x"822c8171",
+ 3296 => x"2b80f9c4",
+ 3297 => x"080780f9",
+ 3298 => x"c00b8405",
+ 3299 => x"0c53758c",
+ 3300 => x"190c7388",
+ 3301 => x"190c7788",
+ 3302 => x"170c778c",
+ 3303 => x"150cfdcd",
+ 3304 => x"39831570",
+ 3305 => x"822c8171",
+ 3306 => x"2b80f9c4",
+ 3307 => x"080780f9",
+ 3308 => x"c00b8405",
+ 3309 => x"0c5153d6",
+ 3310 => x"39fe3d0d",
+ 3311 => x"8188f008",
+ 3312 => x"51708a38",
+ 3313 => x"81d99c70",
+ 3314 => x"8188f00c",
+ 3315 => x"51707512",
+ 3316 => x"5252ff53",
+ 3317 => x"7087fb80",
+ 3318 => x"80268838",
+ 3319 => x"708188f0",
+ 3320 => x"0c715372",
+ 3321 => x"800c843d",
+ 3322 => x"0d04fd3d",
+ 3323 => x"0d800b80",
+ 3324 => x"f8ec0854",
+ 3325 => x"5472812e",
+ 3326 => x"9e387381",
+ 3327 => x"88f40cff",
+ 3328 => x"a0ff3fff",
+ 3329 => x"9ffa3f81",
+ 3330 => x"88c85281",
+ 3331 => x"51ffa9ae",
+ 3332 => x"3f800851",
+ 3333 => x"80e13f72",
+ 3334 => x"8188f40c",
+ 3335 => x"ffa0e23f",
+ 3336 => x"ff9fdd3f",
+ 3337 => x"8188c852",
+ 3338 => x"8151ffa9",
+ 3339 => x"913f8008",
+ 3340 => x"5180c43f",
+ 3341 => x"00ff3900",
+ 3342 => x"ff39f43d",
+ 3343 => x"0d7e8188",
+ 3344 => x"e8087008",
+ 3345 => x"7081ff06",
+ 3346 => x"923df805",
+ 3347 => x"55515a57",
+ 3348 => x"59ffa19a",
+ 3349 => x"3f805477",
+ 3350 => x"557b7d58",
+ 3351 => x"5276538e",
+ 3352 => x"3df00551",
+ 3353 => x"c0c03f79",
+ 3354 => x"7b58790c",
+ 3355 => x"76841a0c",
+ 3356 => x"78800c8e",
+ 3357 => x"3d0d04f7",
+ 3358 => x"3d0d7b81",
+ 3359 => x"81c80882",
+ 3360 => x"c811085a",
+ 3361 => x"545a7780",
+ 3362 => x"2e80da38",
+ 3363 => x"81881884",
+ 3364 => x"1908ff05",
+ 3365 => x"81712b59",
+ 3366 => x"55598074",
+ 3367 => x"2480ea38",
+ 3368 => x"807424b5",
+ 3369 => x"3873822b",
+ 3370 => x"78118805",
+ 3371 => x"56568180",
+ 3372 => x"19087706",
+ 3373 => x"5372802e",
+ 3374 => x"b6387816",
+ 3375 => x"70085353",
+ 3376 => x"79517408",
+ 3377 => x"53722dff",
+ 3378 => x"14fc17fc",
+ 3379 => x"1779812c",
+ 3380 => x"5a575754",
+ 3381 => x"738025d6",
+ 3382 => x"38770858",
+ 3383 => x"77ffad38",
+ 3384 => x"8181c808",
+ 3385 => x"53bc1308",
+ 3386 => x"a5387951",
+ 3387 => x"fec63f74",
+ 3388 => x"0853722d",
+ 3389 => x"ff14fc17",
+ 3390 => x"fc177981",
+ 3391 => x"2c5a5757",
+ 3392 => x"54738025",
+ 3393 => x"ffa838d1",
+ 3394 => x"398057ff",
+ 3395 => x"93397251",
+ 3396 => x"bc130853",
+ 3397 => x"722d7951",
+ 3398 => x"fe9a3fff",
+ 3399 => x"3d0d8188",
+ 3400 => x"d00bfc05",
+ 3401 => x"70085252",
+ 3402 => x"70ff2e91",
+ 3403 => x"38702dfc",
+ 3404 => x"12700852",
+ 3405 => x"5270ff2e",
+ 3406 => x"098106f1",
+ 3407 => x"38833d0d",
+ 3408 => x"0404ffa0",
+ 3409 => x"873f0400",
+ 3410 => x"00000040",
+ 3411 => x"30313233",
+ 3412 => x"34353637",
+ 3413 => x"38390000",
+ 3414 => x"44485259",
+ 3415 => x"53544f4e",
+ 3416 => x"45205052",
+ 3417 => x"4f475241",
+ 3418 => x"4d2c2053",
+ 3419 => x"4f4d4520",
+ 3420 => x"53545249",
+ 3421 => x"4e470000",
+ 3422 => x"44485259",
+ 3423 => x"53544f4e",
+ 3424 => x"45205052",
+ 3425 => x"4f475241",
+ 3426 => x"4d2c2031",
+ 3427 => x"27535420",
+ 3428 => x"53545249",
+ 3429 => x"4e470000",
+ 3430 => x"44687279",
+ 3431 => x"73746f6e",
+ 3432 => x"65204265",
+ 3433 => x"6e63686d",
+ 3434 => x"61726b2c",
+ 3435 => x"20566572",
+ 3436 => x"73696f6e",
+ 3437 => x"20322e31",
+ 3438 => x"20284c61",
+ 3439 => x"6e677561",
+ 3440 => x"67653a20",
+ 3441 => x"43290a00",
+ 3442 => x"50726f67",
+ 3443 => x"72616d20",
+ 3444 => x"636f6d70",
+ 3445 => x"696c6564",
+ 3446 => x"20776974",
+ 3447 => x"68202772",
+ 3448 => x"65676973",
+ 3449 => x"74657227",
+ 3450 => x"20617474",
+ 3451 => x"72696275",
+ 3452 => x"74650a00",
+ 3453 => x"45786563",
+ 3454 => x"7574696f",
+ 3455 => x"6e207374",
+ 3456 => x"61727473",
+ 3457 => x"2c202564",
+ 3458 => x"2072756e",
+ 3459 => x"73207468",
+ 3460 => x"726f7567",
+ 3461 => x"68204468",
+ 3462 => x"72797374",
+ 3463 => x"6f6e650a",
+ 3464 => x"00000000",
+ 3465 => x"44485259",
+ 3466 => x"53544f4e",
+ 3467 => x"45205052",
+ 3468 => x"4f475241",
+ 3469 => x"4d2c2032",
+ 3470 => x"274e4420",
+ 3471 => x"53545249",
+ 3472 => x"4e470000",
+ 3473 => x"45786563",
+ 3474 => x"7574696f",
+ 3475 => x"6e20656e",
+ 3476 => x"64730a00",
+ 3477 => x"46696e61",
+ 3478 => x"6c207661",
+ 3479 => x"6c756573",
+ 3480 => x"206f6620",
+ 3481 => x"74686520",
+ 3482 => x"76617269",
+ 3483 => x"61626c65",
+ 3484 => x"73207573",
+ 3485 => x"65642069",
+ 3486 => x"6e207468",
+ 3487 => x"65206265",
+ 3488 => x"6e63686d",
+ 3489 => x"61726b3a",
+ 3490 => x"0a000000",
+ 3491 => x"496e745f",
+ 3492 => x"476c6f62",
+ 3493 => x"3a202020",
+ 3494 => x"20202020",
+ 3495 => x"20202020",
+ 3496 => x"2025640a",
+ 3497 => x"00000000",
+ 3498 => x"20202020",
+ 3499 => x"20202020",
+ 3500 => x"73686f75",
+ 3501 => x"6c642062",
+ 3502 => x"653a2020",
+ 3503 => x"2025640a",
+ 3504 => x"00000000",
+ 3505 => x"426f6f6c",
+ 3506 => x"5f476c6f",
+ 3507 => x"623a2020",
+ 3508 => x"20202020",
+ 3509 => x"20202020",
+ 3510 => x"2025640a",
+ 3511 => x"00000000",
+ 3512 => x"43685f31",
+ 3513 => x"5f476c6f",
+ 3514 => x"623a2020",
+ 3515 => x"20202020",
+ 3516 => x"20202020",
+ 3517 => x"2025630a",
+ 3518 => x"00000000",
+ 3519 => x"20202020",
+ 3520 => x"20202020",
+ 3521 => x"73686f75",
+ 3522 => x"6c642062",
+ 3523 => x"653a2020",
+ 3524 => x"2025630a",
+ 3525 => x"00000000",
+ 3526 => x"43685f32",
+ 3527 => x"5f476c6f",
+ 3528 => x"623a2020",
+ 3529 => x"20202020",
+ 3530 => x"20202020",
+ 3531 => x"2025630a",
+ 3532 => x"00000000",
+ 3533 => x"4172725f",
+ 3534 => x"315f476c",
+ 3535 => x"6f625b38",
+ 3536 => x"5d3a2020",
+ 3537 => x"20202020",
+ 3538 => x"2025640a",
+ 3539 => x"00000000",
+ 3540 => x"4172725f",
+ 3541 => x"325f476c",
+ 3542 => x"6f625b38",
+ 3543 => x"5d5b375d",
+ 3544 => x"3a202020",
+ 3545 => x"2025640a",
+ 3546 => x"00000000",
+ 3547 => x"20202020",
+ 3548 => x"20202020",
+ 3549 => x"73686f75",
+ 3550 => x"6c642062",
+ 3551 => x"653a2020",
+ 3552 => x"204e756d",
+ 3553 => x"6265725f",
+ 3554 => x"4f665f52",
+ 3555 => x"756e7320",
+ 3556 => x"2b203130",
+ 3557 => x"0a000000",
+ 3558 => x"5074725f",
+ 3559 => x"476c6f62",
+ 3560 => x"2d3e0a00",
+ 3561 => x"20205074",
+ 3562 => x"725f436f",
+ 3563 => x"6d703a20",
+ 3564 => x"20202020",
+ 3565 => x"20202020",
+ 3566 => x"2025640a",
+ 3567 => x"00000000",
+ 3568 => x"20202020",
+ 3569 => x"20202020",
+ 3570 => x"73686f75",
+ 3571 => x"6c642062",
+ 3572 => x"653a2020",
+ 3573 => x"2028696d",
+ 3574 => x"706c656d",
+ 3575 => x"656e7461",
+ 3576 => x"74696f6e",
+ 3577 => x"2d646570",
+ 3578 => x"656e6465",
+ 3579 => x"6e74290a",
+ 3580 => x"00000000",
+ 3581 => x"20204469",
+ 3582 => x"7363723a",
+ 3583 => x"20202020",
+ 3584 => x"20202020",
+ 3585 => x"20202020",
+ 3586 => x"2025640a",
+ 3587 => x"00000000",
+ 3588 => x"2020456e",
+ 3589 => x"756d5f43",
+ 3590 => x"6f6d703a",
+ 3591 => x"20202020",
+ 3592 => x"20202020",
+ 3593 => x"2025640a",
+ 3594 => x"00000000",
+ 3595 => x"2020496e",
+ 3596 => x"745f436f",
+ 3597 => x"6d703a20",
+ 3598 => x"20202020",
+ 3599 => x"20202020",
+ 3600 => x"2025640a",
+ 3601 => x"00000000",
+ 3602 => x"20205374",
+ 3603 => x"725f436f",
+ 3604 => x"6d703a20",
+ 3605 => x"20202020",
+ 3606 => x"20202020",
+ 3607 => x"2025730a",
+ 3608 => x"00000000",
+ 3609 => x"20202020",
+ 3610 => x"20202020",
+ 3611 => x"73686f75",
+ 3612 => x"6c642062",
+ 3613 => x"653a2020",
+ 3614 => x"20444852",
+ 3615 => x"5953544f",
+ 3616 => x"4e452050",
+ 3617 => x"524f4752",
+ 3618 => x"414d2c20",
+ 3619 => x"534f4d45",
+ 3620 => x"20535452",
+ 3621 => x"494e470a",
+ 3622 => x"00000000",
+ 3623 => x"4e657874",
+ 3624 => x"5f507472",
+ 3625 => x"5f476c6f",
+ 3626 => x"622d3e0a",
+ 3627 => x"00000000",
+ 3628 => x"20202020",
+ 3629 => x"20202020",
+ 3630 => x"73686f75",
+ 3631 => x"6c642062",
+ 3632 => x"653a2020",
+ 3633 => x"2028696d",
+ 3634 => x"706c656d",
+ 3635 => x"656e7461",
+ 3636 => x"74696f6e",
+ 3637 => x"2d646570",
+ 3638 => x"656e6465",
+ 3639 => x"6e74292c",
+ 3640 => x"2073616d",
+ 3641 => x"65206173",
+ 3642 => x"2061626f",
+ 3643 => x"76650a00",
+ 3644 => x"496e745f",
+ 3645 => x"315f4c6f",
+ 3646 => x"633a2020",
+ 3647 => x"20202020",
+ 3648 => x"20202020",
+ 3649 => x"2025640a",
+ 3650 => x"00000000",
+ 3651 => x"496e745f",
+ 3652 => x"325f4c6f",
+ 3653 => x"633a2020",
+ 3654 => x"20202020",
+ 3655 => x"20202020",
+ 3656 => x"2025640a",
+ 3657 => x"00000000",
+ 3658 => x"496e745f",
+ 3659 => x"335f4c6f",
+ 3660 => x"633a2020",
+ 3661 => x"20202020",
+ 3662 => x"20202020",
+ 3663 => x"2025640a",
+ 3664 => x"00000000",
+ 3665 => x"456e756d",
+ 3666 => x"5f4c6f63",
+ 3667 => x"3a202020",
+ 3668 => x"20202020",
+ 3669 => x"20202020",
+ 3670 => x"2025640a",
+ 3671 => x"00000000",
+ 3672 => x"5374725f",
+ 3673 => x"315f4c6f",
+ 3674 => x"633a2020",
+ 3675 => x"20202020",
+ 3676 => x"20202020",
+ 3677 => x"2025730a",
+ 3678 => x"00000000",
+ 3679 => x"20202020",
+ 3680 => x"20202020",
+ 3681 => x"73686f75",
+ 3682 => x"6c642062",
+ 3683 => x"653a2020",
+ 3684 => x"20444852",
+ 3685 => x"5953544f",
+ 3686 => x"4e452050",
+ 3687 => x"524f4752",
+ 3688 => x"414d2c20",
+ 3689 => x"31275354",
+ 3690 => x"20535452",
+ 3691 => x"494e470a",
+ 3692 => x"00000000",
+ 3693 => x"5374725f",
+ 3694 => x"325f4c6f",
+ 3695 => x"633a2020",
+ 3696 => x"20202020",
+ 3697 => x"20202020",
+ 3698 => x"2025730a",
+ 3699 => x"00000000",
+ 3700 => x"20202020",
+ 3701 => x"20202020",
+ 3702 => x"73686f75",
+ 3703 => x"6c642062",
+ 3704 => x"653a2020",
+ 3705 => x"20444852",
+ 3706 => x"5953544f",
+ 3707 => x"4e452050",
+ 3708 => x"524f4752",
+ 3709 => x"414d2c20",
+ 3710 => x"32274e44",
+ 3711 => x"20535452",
+ 3712 => x"494e470a",
+ 3713 => x"00000000",
+ 3714 => x"55736572",
+ 3715 => x"2074696d",
+ 3716 => x"653a2025",
+ 3717 => x"640a0000",
+ 3718 => x"4d696372",
+ 3719 => x"6f736563",
+ 3720 => x"6f6e6473",
+ 3721 => x"20666f72",
+ 3722 => x"206f6e65",
+ 3723 => x"2072756e",
+ 3724 => x"20746872",
+ 3725 => x"6f756768",
+ 3726 => x"20446872",
+ 3727 => x"7973746f",
+ 3728 => x"6e653a20",
+ 3729 => x"00000000",
+ 3730 => x"2564200a",
+ 3731 => x"00000000",
+ 3732 => x"44687279",
+ 3733 => x"73746f6e",
+ 3734 => x"65732070",
+ 3735 => x"65722053",
+ 3736 => x"65636f6e",
+ 3737 => x"643a2020",
+ 3738 => x"20202020",
+ 3739 => x"20202020",
+ 3740 => x"20202020",
+ 3741 => x"20202020",
+ 3742 => x"20202020",
+ 3743 => x"00000000",
+ 3744 => x"56415820",
+ 3745 => x"4d495053",
+ 3746 => x"20726174",
+ 3747 => x"696e6720",
+ 3748 => x"2a203130",
+ 3749 => x"3030203d",
+ 3750 => x"20256420",
+ 3751 => x"0a000000",
+ 3752 => x"50726f67",
+ 3753 => x"72616d20",
+ 3754 => x"636f6d70",
+ 3755 => x"696c6564",
+ 3756 => x"20776974",
+ 3757 => x"686f7574",
+ 3758 => x"20277265",
+ 3759 => x"67697374",
+ 3760 => x"65722720",
+ 3761 => x"61747472",
+ 3762 => x"69627574",
+ 3763 => x"650a0000",
+ 3764 => x"4d656173",
+ 3765 => x"75726564",
+ 3766 => x"2074696d",
+ 3767 => x"6520746f",
+ 3768 => x"6f20736d",
+ 3769 => x"616c6c20",
+ 3770 => x"746f206f",
+ 3771 => x"62746169",
+ 3772 => x"6e206d65",
+ 3773 => x"616e696e",
+ 3774 => x"6766756c",
+ 3775 => x"20726573",
+ 3776 => x"756c7473",
+ 3777 => x"0a000000",
+ 3778 => x"506c6561",
+ 3779 => x"73652069",
+ 3780 => x"6e637265",
+ 3781 => x"61736520",
+ 3782 => x"6e756d62",
+ 3783 => x"6572206f",
+ 3784 => x"66207275",
+ 3785 => x"6e730a00",
+ 3786 => x"44485259",
+ 3787 => x"53544f4e",
+ 3788 => x"45205052",
+ 3789 => x"4f475241",
+ 3790 => x"4d2c2033",
+ 3791 => x"27524420",
+ 3792 => x"53545249",
+ 3793 => x"4e470000",
+ 3794 => x"00010202",
+ 3795 => x"03030303",
+ 3796 => x"04040404",
+ 3797 => x"04040404",
+ 3798 => x"05050505",
+ 3799 => x"05050505",
+ 3800 => x"05050505",
+ 3801 => x"05050505",
+ 3802 => x"06060606",
+ 3803 => x"06060606",
+ 3804 => x"06060606",
+ 3805 => x"06060606",
+ 3806 => x"06060606",
+ 3807 => x"06060606",
+ 3808 => x"06060606",
+ 3809 => x"06060606",
+ 3810 => x"07070707",
+ 3811 => x"07070707",
+ 3812 => x"07070707",
+ 3813 => x"07070707",
+ 3814 => x"07070707",
+ 3815 => x"07070707",
+ 3816 => x"07070707",
+ 3817 => x"07070707",
+ 3818 => x"07070707",
+ 3819 => x"07070707",
+ 3820 => x"07070707",
+ 3821 => x"07070707",
+ 3822 => x"07070707",
+ 3823 => x"07070707",
+ 3824 => x"07070707",
+ 3825 => x"07070707",
+ 3826 => x"08080808",
+ 3827 => x"08080808",
+ 3828 => x"08080808",
+ 3829 => x"08080808",
+ 3830 => x"08080808",
+ 3831 => x"08080808",
+ 3832 => x"08080808",
+ 3833 => x"08080808",
+ 3834 => x"08080808",
+ 3835 => x"08080808",
+ 3836 => x"08080808",
+ 3837 => x"08080808",
+ 3838 => x"08080808",
+ 3839 => x"08080808",
+ 3840 => x"08080808",
+ 3841 => x"08080808",
+ 3842 => x"08080808",
+ 3843 => x"08080808",
+ 3844 => x"08080808",
+ 3845 => x"08080808",
+ 3846 => x"08080808",
+ 3847 => x"08080808",
+ 3848 => x"08080808",
+ 3849 => x"08080808",
+ 3850 => x"08080808",
+ 3851 => x"08080808",
+ 3852 => x"08080808",
+ 3853 => x"08080808",
+ 3854 => x"08080808",
+ 3855 => x"08080808",
+ 3856 => x"08080808",
+ 3857 => x"08080808",
+ 3858 => x"43000000",
+ 3859 => x"64756d6d",
+ 3860 => x"792e6578",
+ 3861 => x"65000000",
+ 3862 => x"00ffffff",
+ 3863 => x"ff00ffff",
+ 3864 => x"ffff00ff",
+ 3865 => x"ffffff00",
+ 3866 => x"00000000",
+ 3867 => x"00000000",
+ 3868 => x"00000000",
+ 3869 => x"00004458",
+ 3870 => x"0000000a",
+ 3871 => x"00000000",
+ 3872 => x"00000032",
+ 3873 => x"00000000",
+ 3874 => x"00000000",
+ 3875 => x"00000000",
+ 3876 => x"00000000",
+ 3877 => x"00000000",
+ 3878 => x"00000000",
+ 3879 => x"00000000",
+ 3880 => x"00000000",
+ 3881 => x"00000000",
+ 3882 => x"00000000",
+ 3883 => x"00000000",
+ 3884 => x"00000000",
+ 3885 => x"ffffffff",
+ 3886 => x"00000000",
+ 3887 => x"00020000",
+ 3888 => x"00000000",
+ 3889 => x"00000000",
+ 3890 => x"00003cc0",
+ 3891 => x"00003cc0",
+ 3892 => x"00003cc8",
+ 3893 => x"00003cc8",
+ 3894 => x"00003cd0",
+ 3895 => x"00003cd0",
+ 3896 => x"00003cd8",
+ 3897 => x"00003cd8",
+ 3898 => x"00003ce0",
+ 3899 => x"00003ce0",
+ 3900 => x"00003ce8",
+ 3901 => x"00003ce8",
+ 3902 => x"00003cf0",
+ 3903 => x"00003cf0",
+ 3904 => x"00003cf8",
+ 3905 => x"00003cf8",
+ 3906 => x"00003d00",
+ 3907 => x"00003d00",
+ 3908 => x"00003d08",
+ 3909 => x"00003d08",
+ 3910 => x"00003d10",
+ 3911 => x"00003d10",
+ 3912 => x"00003d18",
+ 3913 => x"00003d18",
+ 3914 => x"00003d20",
+ 3915 => x"00003d20",
+ 3916 => x"00003d28",
+ 3917 => x"00003d28",
+ 3918 => x"00003d30",
+ 3919 => x"00003d30",
+ 3920 => x"00003d38",
+ 3921 => x"00003d38",
+ 3922 => x"00003d40",
+ 3923 => x"00003d40",
+ 3924 => x"00003d48",
+ 3925 => x"00003d48",
+ 3926 => x"00003d50",
+ 3927 => x"00003d50",
+ 3928 => x"00003d58",
+ 3929 => x"00003d58",
+ 3930 => x"00003d60",
+ 3931 => x"00003d60",
+ 3932 => x"00003d68",
+ 3933 => x"00003d68",
+ 3934 => x"00003d70",
+ 3935 => x"00003d70",
+ 3936 => x"00003d78",
+ 3937 => x"00003d78",
+ 3938 => x"00003d80",
+ 3939 => x"00003d80",
+ 3940 => x"00003d88",
+ 3941 => x"00003d88",
+ 3942 => x"00003d90",
+ 3943 => x"00003d90",
+ 3944 => x"00003d98",
+ 3945 => x"00003d98",
+ 3946 => x"00003da0",
+ 3947 => x"00003da0",
+ 3948 => x"00003da8",
+ 3949 => x"00003da8",
+ 3950 => x"00003db0",
+ 3951 => x"00003db0",
+ 3952 => x"00003db8",
+ 3953 => x"00003db8",
+ 3954 => x"00003dc0",
+ 3955 => x"00003dc0",
+ 3956 => x"00003dc8",
+ 3957 => x"00003dc8",
+ 3958 => x"00003dd0",
+ 3959 => x"00003dd0",
+ 3960 => x"00003dd8",
+ 3961 => x"00003dd8",
+ 3962 => x"00003de0",
+ 3963 => x"00003de0",
+ 3964 => x"00003de8",
+ 3965 => x"00003de8",
+ 3966 => x"00003df0",
+ 3967 => x"00003df0",
+ 3968 => x"00003df8",
+ 3969 => x"00003df8",
+ 3970 => x"00003e00",
+ 3971 => x"00003e00",
+ 3972 => x"00003e08",
+ 3973 => x"00003e08",
+ 3974 => x"00003e10",
+ 3975 => x"00003e10",
+ 3976 => x"00003e18",
+ 3977 => x"00003e18",
+ 3978 => x"00003e20",
+ 3979 => x"00003e20",
+ 3980 => x"00003e28",
+ 3981 => x"00003e28",
+ 3982 => x"00003e30",
+ 3983 => x"00003e30",
+ 3984 => x"00003e38",
+ 3985 => x"00003e38",
+ 3986 => x"00003e40",
+ 3987 => x"00003e40",
+ 3988 => x"00003e48",
+ 3989 => x"00003e48",
+ 3990 => x"00003e50",
+ 3991 => x"00003e50",
+ 3992 => x"00003e58",
+ 3993 => x"00003e58",
+ 3994 => x"00003e60",
+ 3995 => x"00003e60",
+ 3996 => x"00003e68",
+ 3997 => x"00003e68",
+ 3998 => x"00003e70",
+ 3999 => x"00003e70",
+ 4000 => x"00003e78",
+ 4001 => x"00003e78",
+ 4002 => x"00003e80",
+ 4003 => x"00003e80",
+ 4004 => x"00003e88",
+ 4005 => x"00003e88",
+ 4006 => x"00003e90",
+ 4007 => x"00003e90",
+ 4008 => x"00003e98",
+ 4009 => x"00003e98",
+ 4010 => x"00003ea0",
+ 4011 => x"00003ea0",
+ 4012 => x"00003ea8",
+ 4013 => x"00003ea8",
+ 4014 => x"00003eb0",
+ 4015 => x"00003eb0",
+ 4016 => x"00003eb8",
+ 4017 => x"00003eb8",
+ 4018 => x"00003ec0",
+ 4019 => x"00003ec0",
+ 4020 => x"00003ec8",
+ 4021 => x"00003ec8",
+ 4022 => x"00003ed0",
+ 4023 => x"00003ed0",
+ 4024 => x"00003ed8",
+ 4025 => x"00003ed8",
+ 4026 => x"00003ee0",
+ 4027 => x"00003ee0",
+ 4028 => x"00003ee8",
+ 4029 => x"00003ee8",
+ 4030 => x"00003ef0",
+ 4031 => x"00003ef0",
+ 4032 => x"00003ef8",
+ 4033 => x"00003ef8",
+ 4034 => x"00003f00",
+ 4035 => x"00003f00",
+ 4036 => x"00003f08",
+ 4037 => x"00003f08",
+ 4038 => x"00003f10",
+ 4039 => x"00003f10",
+ 4040 => x"00003f18",
+ 4041 => x"00003f18",
+ 4042 => x"00003f20",
+ 4043 => x"00003f20",
+ 4044 => x"00003f28",
+ 4045 => x"00003f28",
+ 4046 => x"00003f30",
+ 4047 => x"00003f30",
+ 4048 => x"00003f38",
+ 4049 => x"00003f38",
+ 4050 => x"00003f40",
+ 4051 => x"00003f40",
+ 4052 => x"00003f48",
+ 4053 => x"00003f48",
+ 4054 => x"00003f50",
+ 4055 => x"00003f50",
+ 4056 => x"00003f58",
+ 4057 => x"00003f58",
+ 4058 => x"00003f60",
+ 4059 => x"00003f60",
+ 4060 => x"00003f68",
+ 4061 => x"00003f68",
+ 4062 => x"00003f70",
+ 4063 => x"00003f70",
+ 4064 => x"00003f78",
+ 4065 => x"00003f78",
+ 4066 => x"00003f80",
+ 4067 => x"00003f80",
+ 4068 => x"00003f88",
+ 4069 => x"00003f88",
+ 4070 => x"00003f90",
+ 4071 => x"00003f90",
+ 4072 => x"00003f98",
+ 4073 => x"00003f98",
+ 4074 => x"00003fa0",
+ 4075 => x"00003fa0",
+ 4076 => x"00003fa8",
+ 4077 => x"00003fa8",
+ 4078 => x"00003fb0",
+ 4079 => x"00003fb0",
+ 4080 => x"00003fb8",
+ 4081 => x"00003fb8",
+ 4082 => x"00003fc0",
+ 4083 => x"00003fc0",
+ 4084 => x"00003fc8",
+ 4085 => x"00003fc8",
+ 4086 => x"00003fd0",
+ 4087 => x"00003fd0",
+ 4088 => x"00003fd8",
+ 4089 => x"00003fd8",
+ 4090 => x"00003fe0",
+ 4091 => x"00003fe0",
+ 4092 => x"00003fe8",
+ 4093 => x"00003fe8",
+ 4094 => x"00003ff0",
+ 4095 => x"00003ff0",
+ 4096 => x"00003ff8",
+ 4097 => x"00003ff8",
+ 4098 => x"00004000",
+ 4099 => x"00004000",
+ 4100 => x"00004008",
+ 4101 => x"00004008",
+ 4102 => x"00004010",
+ 4103 => x"00004010",
+ 4104 => x"00004018",
+ 4105 => x"00004018",
+ 4106 => x"00004020",
+ 4107 => x"00004020",
+ 4108 => x"00004028",
+ 4109 => x"00004028",
+ 4110 => x"00004030",
+ 4111 => x"00004030",
+ 4112 => x"00004038",
+ 4113 => x"00004038",
+ 4114 => x"00004040",
+ 4115 => x"00004040",
+ 4116 => x"00004048",
+ 4117 => x"00004048",
+ 4118 => x"00004050",
+ 4119 => x"00004050",
+ 4120 => x"00004058",
+ 4121 => x"00004058",
+ 4122 => x"00004060",
+ 4123 => x"00004060",
+ 4124 => x"00004068",
+ 4125 => x"00004068",
+ 4126 => x"00004070",
+ 4127 => x"00004070",
+ 4128 => x"00004078",
+ 4129 => x"00004078",
+ 4130 => x"00004080",
+ 4131 => x"00004080",
+ 4132 => x"00004088",
+ 4133 => x"00004088",
+ 4134 => x"00004090",
+ 4135 => x"00004090",
+ 4136 => x"00004098",
+ 4137 => x"00004098",
+ 4138 => x"000040a0",
+ 4139 => x"000040a0",
+ 4140 => x"000040a8",
+ 4141 => x"000040a8",
+ 4142 => x"000040b0",
+ 4143 => x"000040b0",
+ 4144 => x"000040b8",
+ 4145 => x"000040b8",
+ 4146 => x"000040cc",
+ 4147 => x"00000000",
+ 4148 => x"00004334",
+ 4149 => x"00004390",
+ 4150 => x"000043ec",
+ 4151 => x"00000000",
+ 4152 => x"00000000",
+ 4153 => x"00000000",
+ 4154 => x"00000000",
+ 4155 => x"00000000",
+ 4156 => x"00000000",
+ 4157 => x"00000000",
+ 4158 => x"00000000",
+ 4159 => x"00000000",
+ 4160 => x"00003c48",
+ 4161 => x"00000000",
+ 4162 => x"00000000",
+ 4163 => x"00000000",
+ 4164 => x"00000000",
+ 4165 => x"00000000",
+ 4166 => x"00000000",
+ 4167 => x"00000000",
+ 4168 => x"00000000",
+ 4169 => x"00000000",
+ 4170 => x"00000000",
+ 4171 => x"00000000",
+ 4172 => x"00000000",
+ 4173 => x"00000000",
+ 4174 => x"00000000",
+ 4175 => x"00000000",
+ 4176 => x"00000000",
+ 4177 => x"00000000",
+ 4178 => x"00000000",
+ 4179 => x"00000000",
+ 4180 => x"00000000",
+ 4181 => x"00000000",
+ 4182 => x"00000000",
+ 4183 => x"00000000",
+ 4184 => x"00000000",
+ 4185 => x"00000000",
+ 4186 => x"00000000",
+ 4187 => x"00000000",
+ 4188 => x"00000000",
+ 4189 => x"00000001",
+ 4190 => x"330eabcd",
+ 4191 => x"1234e66d",
+ 4192 => x"deec0005",
+ 4193 => x"000b0000",
+ 4194 => x"00000000",
+ 4195 => x"00000000",
+ 4196 => x"00000000",
+ 4197 => x"00000000",
+ 4198 => x"00000000",
+ 4199 => x"00000000",
+ 4200 => x"00000000",
+ 4201 => x"00000000",
+ 4202 => x"00000000",
+ 4203 => x"00000000",
+ 4204 => x"00000000",
+ 4205 => x"00000000",
+ 4206 => x"00000000",
+ 4207 => x"00000000",
+ 4208 => x"00000000",
+ 4209 => x"00000000",
+ 4210 => x"00000000",
+ 4211 => x"00000000",
+ 4212 => x"00000000",
+ 4213 => x"00000000",
+ 4214 => x"00000000",
+ 4215 => x"00000000",
+ 4216 => x"00000000",
+ 4217 => x"00000000",
+ 4218 => x"00000000",
+ 4219 => x"00000000",
+ 4220 => x"00000000",
+ 4221 => x"00000000",
+ 4222 => x"00000000",
+ 4223 => x"00000000",
+ 4224 => x"00000000",
+ 4225 => x"00000000",
+ 4226 => x"00000000",
+ 4227 => x"00000000",
+ 4228 => x"00000000",
+ 4229 => x"00000000",
+ 4230 => x"00000000",
+ 4231 => x"00000000",
+ 4232 => x"00000000",
+ 4233 => x"00000000",
+ 4234 => x"00000000",
+ 4235 => x"00000000",
+ 4236 => x"00000000",
+ 4237 => x"00000000",
+ 4238 => x"00000000",
+ 4239 => x"00000000",
+ 4240 => x"00000000",
+ 4241 => x"00000000",
+ 4242 => x"00000000",
+ 4243 => x"00000000",
+ 4244 => x"00000000",
+ 4245 => x"00000000",
+ 4246 => x"00000000",
+ 4247 => x"00000000",
+ 4248 => x"00000000",
+ 4249 => x"00000000",
+ 4250 => x"00000000",
+ 4251 => x"00000000",
+ 4252 => x"00000000",
+ 4253 => x"00000000",
+ 4254 => x"00000000",
+ 4255 => x"00000000",
+ 4256 => x"00000000",
+ 4257 => x"00000000",
+ 4258 => x"00000000",
+ 4259 => x"00000000",
+ 4260 => x"00000000",
+ 4261 => x"00000000",
+ 4262 => x"00000000",
+ 4263 => x"00000000",
+ 4264 => x"00000000",
+ 4265 => x"00000000",
+ 4266 => x"00000000",
+ 4267 => x"00000000",
+ 4268 => x"00000000",
+ 4269 => x"00000000",
+ 4270 => x"00000000",
+ 4271 => x"00000000",
+ 4272 => x"00000000",
+ 4273 => x"00000000",
+ 4274 => x"00000000",
+ 4275 => x"00000000",
+ 4276 => x"00000000",
+ 4277 => x"00000000",
+ 4278 => x"00000000",
+ 4279 => x"00000000",
+ 4280 => x"00000000",
+ 4281 => x"00000000",
+ 4282 => x"00000000",
+ 4283 => x"00000000",
+ 4284 => x"00000000",
+ 4285 => x"00000000",
+ 4286 => x"00000000",
+ 4287 => x"00000000",
+ 4288 => x"00000000",
+ 4289 => x"00000000",
+ 4290 => x"00000000",
+ 4291 => x"00000000",
+ 4292 => x"00000000",
+ 4293 => x"00000000",
+ 4294 => x"00000000",
+ 4295 => x"00000000",
+ 4296 => x"00000000",
+ 4297 => x"00000000",
+ 4298 => x"00000000",
+ 4299 => x"00000000",
+ 4300 => x"00000000",
+ 4301 => x"00000000",
+ 4302 => x"00000000",
+ 4303 => x"00000000",
+ 4304 => x"00000000",
+ 4305 => x"00000000",
+ 4306 => x"00000000",
+ 4307 => x"00000000",
+ 4308 => x"00000000",
+ 4309 => x"00000000",
+ 4310 => x"00000000",
+ 4311 => x"00000000",
+ 4312 => x"00000000",
+ 4313 => x"00000000",
+ 4314 => x"00000000",
+ 4315 => x"00000000",
+ 4316 => x"00000000",
+ 4317 => x"00000000",
+ 4318 => x"00000000",
+ 4319 => x"00000000",
+ 4320 => x"00000000",
+ 4321 => x"00000000",
+ 4322 => x"00000000",
+ 4323 => x"00000000",
+ 4324 => x"00000000",
+ 4325 => x"00000000",
+ 4326 => x"00000000",
+ 4327 => x"00000000",
+ 4328 => x"00000000",
+ 4329 => x"00000000",
+ 4330 => x"00000000",
+ 4331 => x"00000000",
+ 4332 => x"00000000",
+ 4333 => x"00000000",
+ 4334 => x"00000000",
+ 4335 => x"00000000",
+ 4336 => x"00000000",
+ 4337 => x"00000000",
+ 4338 => x"00000000",
+ 4339 => x"00000000",
+ 4340 => x"00000000",
+ 4341 => x"00000000",
+ 4342 => x"00000000",
+ 4343 => x"00000000",
+ 4344 => x"00000000",
+ 4345 => x"00000000",
+ 4346 => x"00000000",
+ 4347 => x"00000000",
+ 4348 => x"00000000",
+ 4349 => x"00000000",
+ 4350 => x"00000000",
+ 4351 => x"00000000",
+ 4352 => x"00000000",
+ 4353 => x"00000000",
+ 4354 => x"00000000",
+ 4355 => x"00000000",
+ 4356 => x"00000000",
+ 4357 => x"00000000",
+ 4358 => x"00000000",
+ 4359 => x"00000000",
+ 4360 => x"00000000",
+ 4361 => x"00000000",
+ 4362 => x"00000000",
+ 4363 => x"00000000",
+ 4364 => x"00000000",
+ 4365 => x"00000000",
+ 4366 => x"00000000",
+ 4367 => x"00000000",
+ 4368 => x"00000000",
+ 4369 => x"00000000",
+ 4370 => x"00003c4c",
+ 4371 => x"ffffffff",
+ 4372 => x"00000000",
+ 4373 => x"ffffffff",
+ 4374 => x"00000000",
+ 4375 => x"00000000",
+
+others => x"00000000"
+);
+begin
+ do_port_a:
+ process (clk_i)
+ variable iaddr : integer;
+ begin
+ if rising_edge(clk_i) then
+ if (a_we_i='1') and (b_we_i='1') and (a_addr_i=b_addr_i) and (a_write_i/=b_write_i) then
+ report "DualPortRAM write collision" severity failure;
+ end if;
+ iaddr:=to_integer(a_addr_i);
+ if a_we_i='1' then
+ ram(iaddr):=a_write_i;
+ -- Write First mode
+ a_read_o <= a_write_i;
+ else
+ a_read_o <= ram(iaddr);
+ end if;
+ end if;
+ end process do_port_a;
+
+ do_port_b:
+ process (clk_i)
+ variable iaddr : integer;
+ begin
+ if rising_edge(clk_i) then
+ iaddr:=to_integer(b_addr_i);
+ if b_we_i='1' then
+ ram(iaddr):=b_write_i;
+ b_read_o <= b_write_i;
+ else
+ b_read_o <= ram(iaddr);
+ end if;
+ end if;
+ end process do_port_b;
+end architecture Xilinx; -- Entity: DualPortRAM
diff --git a/zpu/hdl/zealot/roms/hello_bram.vhdl b/zpu/hdl/zealot/roms/hello_bram.vhdl
new file mode 100644
index 0000000..7724423
--- /dev/null
+++ b/zpu/hdl/zealot/roms/hello_bram.vhdl
@@ -0,0 +1,3056 @@
+------------------------------------------------------------------------------
+---- ----
+---- Single Port RAM that maps to a Xilinx BRAM ----
+---- ----
+---- http://www.opencores.org/ ----
+---- ----
+---- Description: ----
+---- This is a program+data memory for the ZPU. It maps to a Xilinx BRAM ----
+---- ----
+---- To Do: ----
+---- - ----
+---- ----
+---- Author: ----
+---- - Salvador E. Tropea, salvador inti.gob.ar ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
+---- ----
+---- Distributed under the BSD license ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Design unit: SinglePortRAM(Xilinx) (Entity and architecture) ----
+---- File name: rom_s.in.vhdl (template used) ----
+---- Note: None ----
+---- Limitations: None known ----
+---- Errors: None known ----
+---- Library: work ----
+---- Dependencies: IEEE.std_logic_1164 ----
+---- IEEE.numeric_std ----
+---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
+---- Language: VHDL ----
+---- Wishbone: No ----
+---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
+---- Text editor: SETEdit 0.5.x ----
+---- ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity SinglePortRAM is
+ generic(
+ WORD_SIZE : integer:=32; -- Word Size 16/32
+ BYTE_BITS : integer:=2; -- Bits used to address bytes
+ BRAM_W : integer:=15); -- Address Width
+ port(
+ clk_i : in std_logic;
+ we_i : in std_logic;
+ re_i : in std_logic;
+ addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS);
+ write_i : in unsigned(WORD_SIZE-1 downto 0);
+ read_o : out unsigned(WORD_SIZE-1 downto 0);
+ busy_o : out std_logic);
+end entity SinglePortRAM;
+
+architecture Xilinx of SinglePortRAM is
+ type ram_type is array(natural range 0 to ((2**BRAM_W)/4)-1) of unsigned(WORD_SIZE-1 downto 0);
+ signal addr_r : unsigned(BRAM_W-1 downto BYTE_BITS);
+
+ signal ram : ram_type :=
+(
+ 0 => x"0b0b0b0b",
+ 1 => x"82700b0b",
+ 2 => x"80cd800c",
+ 3 => x"3a0b0b80",
+ 4 => x"c58f0400",
+ 5 => x"00000000",
+ 6 => x"00000000",
+ 7 => x"00000000",
+ 8 => x"80088408",
+ 9 => x"88080b0b",
+ 10 => x"80c5d62d",
+ 11 => x"880c840c",
+ 12 => x"800c0400",
+ 13 => x"00000000",
+ 14 => x"00000000",
+ 15 => x"00000000",
+ 16 => x"71fd0608",
+ 17 => x"72830609",
+ 18 => x"81058205",
+ 19 => x"832b2a83",
+ 20 => x"ffff0652",
+ 21 => x"04000000",
+ 22 => x"00000000",
+ 23 => x"00000000",
+ 24 => x"71fd0608",
+ 25 => x"83ffff73",
+ 26 => x"83060981",
+ 27 => x"05820583",
+ 28 => x"2b2b0906",
+ 29 => x"7383ffff",
+ 30 => x"0b0b0b0b",
+ 31 => x"83a70400",
+ 32 => x"72098105",
+ 33 => x"72057373",
+ 34 => x"09060906",
+ 35 => x"73097306",
+ 36 => x"070a8106",
+ 37 => x"53510400",
+ 38 => x"00000000",
+ 39 => x"00000000",
+ 40 => x"72722473",
+ 41 => x"732e0753",
+ 42 => x"51040000",
+ 43 => x"00000000",
+ 44 => x"00000000",
+ 45 => x"00000000",
+ 46 => x"00000000",
+ 47 => x"00000000",
+ 48 => x"71737109",
+ 49 => x"71068106",
+ 50 => x"30720a10",
+ 51 => x"0a720a10",
+ 52 => x"0a31050a",
+ 53 => x"81065151",
+ 54 => x"53510400",
+ 55 => x"00000000",
+ 56 => x"72722673",
+ 57 => x"732e0753",
+ 58 => x"51040000",
+ 59 => x"00000000",
+ 60 => x"00000000",
+ 61 => x"00000000",
+ 62 => x"00000000",
+ 63 => x"00000000",
+ 64 => x"00000000",
+ 65 => x"00000000",
+ 66 => x"00000000",
+ 67 => x"00000000",
+ 68 => x"00000000",
+ 69 => x"00000000",
+ 70 => x"00000000",
+ 71 => x"00000000",
+ 72 => x"0b0b0b88",
+ 73 => x"c4040000",
+ 74 => x"00000000",
+ 75 => x"00000000",
+ 76 => x"00000000",
+ 77 => x"00000000",
+ 78 => x"00000000",
+ 79 => x"00000000",
+ 80 => x"720a722b",
+ 81 => x"0a535104",
+ 82 => x"00000000",
+ 83 => x"00000000",
+ 84 => x"00000000",
+ 85 => x"00000000",
+ 86 => x"00000000",
+ 87 => x"00000000",
+ 88 => x"72729f06",
+ 89 => x"0981050b",
+ 90 => x"0b0b88a7",
+ 91 => x"05040000",
+ 92 => x"00000000",
+ 93 => x"00000000",
+ 94 => x"00000000",
+ 95 => x"00000000",
+ 96 => x"72722aff",
+ 97 => x"739f062a",
+ 98 => x"0974090a",
+ 99 => x"8106ff05",
+ 100 => x"06075351",
+ 101 => x"04000000",
+ 102 => x"00000000",
+ 103 => x"00000000",
+ 104 => x"71715351",
+ 105 => x"020d0406",
+ 106 => x"73830609",
+ 107 => x"81058205",
+ 108 => x"832b0b2b",
+ 109 => x"0772fc06",
+ 110 => x"0c515104",
+ 111 => x"00000000",
+ 112 => x"72098105",
+ 113 => x"72050970",
+ 114 => x"81050906",
+ 115 => x"0a810653",
+ 116 => x"51040000",
+ 117 => x"00000000",
+ 118 => x"00000000",
+ 119 => x"00000000",
+ 120 => x"72098105",
+ 121 => x"72050970",
+ 122 => x"81050906",
+ 123 => x"0a098106",
+ 124 => x"53510400",
+ 125 => x"00000000",
+ 126 => x"00000000",
+ 127 => x"00000000",
+ 128 => x"71098105",
+ 129 => x"52040000",
+ 130 => x"00000000",
+ 131 => x"00000000",
+ 132 => x"00000000",
+ 133 => x"00000000",
+ 134 => x"00000000",
+ 135 => x"00000000",
+ 136 => x"72720981",
+ 137 => x"05055351",
+ 138 => x"04000000",
+ 139 => x"00000000",
+ 140 => x"00000000",
+ 141 => x"00000000",
+ 142 => x"00000000",
+ 143 => x"00000000",
+ 144 => x"72097206",
+ 145 => x"73730906",
+ 146 => x"07535104",
+ 147 => x"00000000",
+ 148 => x"00000000",
+ 149 => x"00000000",
+ 150 => x"00000000",
+ 151 => x"00000000",
+ 152 => x"71fc0608",
+ 153 => x"72830609",
+ 154 => x"81058305",
+ 155 => x"1010102a",
+ 156 => x"81ff0652",
+ 157 => x"04000000",
+ 158 => x"00000000",
+ 159 => x"00000000",
+ 160 => x"71fc0608",
+ 161 => x"0b0b80cc",
+ 162 => x"ec738306",
+ 163 => x"10100508",
+ 164 => x"060b0b0b",
+ 165 => x"88aa0400",
+ 166 => x"00000000",
+ 167 => x"00000000",
+ 168 => x"80088408",
+ 169 => x"88087575",
+ 170 => x"0b0b0b8b",
+ 171 => x"8a2d5050",
+ 172 => x"80085688",
+ 173 => x"0c840c80",
+ 174 => x"0c510400",
+ 175 => x"00000000",
+ 176 => x"80088408",
+ 177 => x"88087575",
+ 178 => x"0b0b0b8c",
+ 179 => x"bc2d5050",
+ 180 => x"80085688",
+ 181 => x"0c840c80",
+ 182 => x"0c510400",
+ 183 => x"00000000",
+ 184 => x"72097081",
+ 185 => x"0509060a",
+ 186 => x"8106ff05",
+ 187 => x"70547106",
+ 188 => x"73097274",
+ 189 => x"05ff0506",
+ 190 => x"07515151",
+ 191 => x"04000000",
+ 192 => x"72097081",
+ 193 => x"0509060a",
+ 194 => x"098106ff",
+ 195 => x"05705471",
+ 196 => x"06730972",
+ 197 => x"7405ff05",
+ 198 => x"06075151",
+ 199 => x"51040000",
+ 200 => x"05ff0504",
+ 201 => x"00000000",
+ 202 => x"00000000",
+ 203 => x"00000000",
+ 204 => x"00000000",
+ 205 => x"00000000",
+ 206 => x"00000000",
+ 207 => x"00000000",
+ 208 => x"810b0b0b",
+ 209 => x"80ccfc0c",
+ 210 => x"51040000",
+ 211 => x"00000000",
+ 212 => x"00000000",
+ 213 => x"00000000",
+ 214 => x"00000000",
+ 215 => x"00000000",
+ 216 => x"71810552",
+ 217 => x"04000000",
+ 218 => x"00000000",
+ 219 => x"00000000",
+ 220 => x"00000000",
+ 221 => x"00000000",
+ 222 => x"00000000",
+ 223 => x"00000000",
+ 224 => x"00000000",
+ 225 => x"00000000",
+ 226 => x"00000000",
+ 227 => x"00000000",
+ 228 => x"00000000",
+ 229 => x"00000000",
+ 230 => x"00000000",
+ 231 => x"00000000",
+ 232 => x"02840572",
+ 233 => x"10100552",
+ 234 => x"04000000",
+ 235 => x"00000000",
+ 236 => x"00000000",
+ 237 => x"00000000",
+ 238 => x"00000000",
+ 239 => x"00000000",
+ 240 => x"00000000",
+ 241 => x"00000000",
+ 242 => x"00000000",
+ 243 => x"00000000",
+ 244 => x"00000000",
+ 245 => x"00000000",
+ 246 => x"00000000",
+ 247 => x"00000000",
+ 248 => x"717105ff",
+ 249 => x"05715351",
+ 250 => x"020d0400",
+ 251 => x"00000000",
+ 252 => x"00000000",
+ 253 => x"00000000",
+ 254 => x"00000000",
+ 255 => x"00000000",
+ 256 => x"82c73f80",
+ 257 => x"c4913f04",
+ 258 => x"10101010",
+ 259 => x"10101010",
+ 260 => x"10101010",
+ 261 => x"10101010",
+ 262 => x"10101010",
+ 263 => x"10101010",
+ 264 => x"10101010",
+ 265 => x"10101053",
+ 266 => x"51047381",
+ 267 => x"ff067383",
+ 268 => x"06098105",
+ 269 => x"83051010",
+ 270 => x"102b0772",
+ 271 => x"fc060c51",
+ 272 => x"51043c04",
+ 273 => x"72728072",
+ 274 => x"8106ff05",
+ 275 => x"09720605",
+ 276 => x"71105272",
+ 277 => x"0a100a53",
+ 278 => x"72ed3851",
+ 279 => x"51535104",
+ 280 => x"fe3d0d0b",
+ 281 => x"0b80dce8",
+ 282 => x"08538413",
+ 283 => x"0870882a",
+ 284 => x"70810651",
+ 285 => x"52527080",
+ 286 => x"2ef03871",
+ 287 => x"81ff0680",
+ 288 => x"0c843d0d",
+ 289 => x"04ff3d0d",
+ 290 => x"0b0b80dc",
+ 291 => x"e8085271",
+ 292 => x"0870882a",
+ 293 => x"81327081",
+ 294 => x"06515151",
+ 295 => x"70f13873",
+ 296 => x"720c833d",
+ 297 => x"0d0480cc",
+ 298 => x"fc08802e",
+ 299 => x"a43880cd",
+ 300 => x"8008822e",
+ 301 => x"bd388380",
+ 302 => x"800b0b0b",
+ 303 => x"80dce80c",
+ 304 => x"82a0800b",
+ 305 => x"80dcec0c",
+ 306 => x"8290800b",
+ 307 => x"80dcf00c",
+ 308 => x"04f88080",
+ 309 => x"80a40b0b",
+ 310 => x"0b80dce8",
+ 311 => x"0cf88080",
+ 312 => x"82800b80",
+ 313 => x"dcec0cf8",
+ 314 => x"80808480",
+ 315 => x"0b80dcf0",
+ 316 => x"0c0480c0",
+ 317 => x"a8808c0b",
+ 318 => x"0b0b80dc",
+ 319 => x"e80c80c0",
+ 320 => x"a880940b",
+ 321 => x"80dcec0c",
+ 322 => x"0b0b80cc",
+ 323 => x"c40b80dc",
+ 324 => x"f00c04ff",
+ 325 => x"3d0d80dc",
+ 326 => x"f4335170",
+ 327 => x"a73880cd",
+ 328 => x"88087008",
+ 329 => x"52527080",
+ 330 => x"2e943884",
+ 331 => x"1280cd88",
+ 332 => x"0c702d80",
+ 333 => x"cd880870",
+ 334 => x"08525270",
+ 335 => x"ee38810b",
+ 336 => x"80dcf434",
+ 337 => x"833d0d04",
+ 338 => x"04803d0d",
+ 339 => x"0b0b80dc",
+ 340 => x"e408802e",
+ 341 => x"8e380b0b",
+ 342 => x"0b0b800b",
+ 343 => x"802e0981",
+ 344 => x"06853882",
+ 345 => x"3d0d040b",
+ 346 => x"0b80dce4",
+ 347 => x"510b0b0b",
+ 348 => x"f58e3f82",
+ 349 => x"3d0d0404",
+ 350 => x"803d0d80",
+ 351 => x"ccc85185",
+ 352 => x"de3f800b",
+ 353 => x"800c823d",
+ 354 => x"0d048c08",
+ 355 => x"028c0cf9",
+ 356 => x"3d0d800b",
+ 357 => x"8c08fc05",
+ 358 => x"0c8c0888",
+ 359 => x"05088025",
+ 360 => x"ab388c08",
+ 361 => x"88050830",
+ 362 => x"8c088805",
+ 363 => x"0c800b8c",
+ 364 => x"08f4050c",
+ 365 => x"8c08fc05",
+ 366 => x"08883881",
+ 367 => x"0b8c08f4",
+ 368 => x"050c8c08",
+ 369 => x"f405088c",
+ 370 => x"08fc050c",
+ 371 => x"8c088c05",
+ 372 => x"088025ab",
+ 373 => x"388c088c",
+ 374 => x"0508308c",
+ 375 => x"088c050c",
+ 376 => x"800b8c08",
+ 377 => x"f0050c8c",
+ 378 => x"08fc0508",
+ 379 => x"8838810b",
+ 380 => x"8c08f005",
+ 381 => x"0c8c08f0",
+ 382 => x"05088c08",
+ 383 => x"fc050c80",
+ 384 => x"538c088c",
+ 385 => x"0508528c",
+ 386 => x"08880508",
+ 387 => x"5181a73f",
+ 388 => x"8008708c",
+ 389 => x"08f8050c",
+ 390 => x"548c08fc",
+ 391 => x"0508802e",
+ 392 => x"8c388c08",
+ 393 => x"f8050830",
+ 394 => x"8c08f805",
+ 395 => x"0c8c08f8",
+ 396 => x"05087080",
+ 397 => x"0c54893d",
+ 398 => x"0d8c0c04",
+ 399 => x"8c08028c",
+ 400 => x"0cfb3d0d",
+ 401 => x"800b8c08",
+ 402 => x"fc050c8c",
+ 403 => x"08880508",
+ 404 => x"80259338",
+ 405 => x"8c088805",
+ 406 => x"08308c08",
+ 407 => x"88050c81",
+ 408 => x"0b8c08fc",
+ 409 => x"050c8c08",
+ 410 => x"8c050880",
+ 411 => x"258c388c",
+ 412 => x"088c0508",
+ 413 => x"308c088c",
+ 414 => x"050c8153",
+ 415 => x"8c088c05",
+ 416 => x"08528c08",
+ 417 => x"88050851",
+ 418 => x"ad3f8008",
+ 419 => x"708c08f8",
+ 420 => x"050c548c",
+ 421 => x"08fc0508",
+ 422 => x"802e8c38",
+ 423 => x"8c08f805",
+ 424 => x"08308c08",
+ 425 => x"f8050c8c",
+ 426 => x"08f80508",
+ 427 => x"70800c54",
+ 428 => x"873d0d8c",
+ 429 => x"0c048c08",
+ 430 => x"028c0cfd",
+ 431 => x"3d0d810b",
+ 432 => x"8c08fc05",
+ 433 => x"0c800b8c",
+ 434 => x"08f8050c",
+ 435 => x"8c088c05",
+ 436 => x"088c0888",
+ 437 => x"050827ac",
+ 438 => x"388c08fc",
+ 439 => x"0508802e",
+ 440 => x"a338800b",
+ 441 => x"8c088c05",
+ 442 => x"08249938",
+ 443 => x"8c088c05",
+ 444 => x"08108c08",
+ 445 => x"8c050c8c",
+ 446 => x"08fc0508",
+ 447 => x"108c08fc",
+ 448 => x"050cc939",
+ 449 => x"8c08fc05",
+ 450 => x"08802e80",
+ 451 => x"c9388c08",
+ 452 => x"8c05088c",
+ 453 => x"08880508",
+ 454 => x"26a1388c",
+ 455 => x"08880508",
+ 456 => x"8c088c05",
+ 457 => x"08318c08",
+ 458 => x"88050c8c",
+ 459 => x"08f80508",
+ 460 => x"8c08fc05",
+ 461 => x"08078c08",
+ 462 => x"f8050c8c",
+ 463 => x"08fc0508",
+ 464 => x"812a8c08",
+ 465 => x"fc050c8c",
+ 466 => x"088c0508",
+ 467 => x"812a8c08",
+ 468 => x"8c050cff",
+ 469 => x"af398c08",
+ 470 => x"90050880",
+ 471 => x"2e8f388c",
+ 472 => x"08880508",
+ 473 => x"708c08f4",
+ 474 => x"050c518d",
+ 475 => x"398c08f8",
+ 476 => x"0508708c",
+ 477 => x"08f4050c",
+ 478 => x"518c08f4",
+ 479 => x"0508800c",
+ 480 => x"853d0d8c",
+ 481 => x"0c04fc3d",
+ 482 => x"0d767079",
+ 483 => x"7b555555",
+ 484 => x"558f7227",
+ 485 => x"8c387275",
+ 486 => x"07830651",
+ 487 => x"70802ea7",
+ 488 => x"38ff1252",
+ 489 => x"71ff2e98",
+ 490 => x"38727081",
+ 491 => x"05543374",
+ 492 => x"70810556",
+ 493 => x"34ff1252",
+ 494 => x"71ff2e09",
+ 495 => x"8106ea38",
+ 496 => x"74800c86",
+ 497 => x"3d0d0474",
+ 498 => x"51727084",
+ 499 => x"05540871",
+ 500 => x"70840553",
+ 501 => x"0c727084",
+ 502 => x"05540871",
+ 503 => x"70840553",
+ 504 => x"0c727084",
+ 505 => x"05540871",
+ 506 => x"70840553",
+ 507 => x"0c727084",
+ 508 => x"05540871",
+ 509 => x"70840553",
+ 510 => x"0cf01252",
+ 511 => x"718f26c9",
+ 512 => x"38837227",
+ 513 => x"95387270",
+ 514 => x"84055408",
+ 515 => x"71708405",
+ 516 => x"530cfc12",
+ 517 => x"52718326",
+ 518 => x"ed387054",
+ 519 => x"ff8339f7",
+ 520 => x"3d0d7c70",
+ 521 => x"525380c8",
+ 522 => x"3f725480",
+ 523 => x"085580cc",
+ 524 => x"d8568157",
+ 525 => x"80088105",
+ 526 => x"5a8b3de4",
+ 527 => x"11595382",
+ 528 => x"59f41352",
+ 529 => x"7b881108",
+ 530 => x"52538183",
+ 531 => x"3f800830",
+ 532 => x"70800807",
+ 533 => x"9f2c8a07",
+ 534 => x"800c538b",
+ 535 => x"3d0d04ff",
+ 536 => x"3d0d7352",
+ 537 => x"80cd8c08",
+ 538 => x"51ffb43f",
+ 539 => x"833d0d04",
+ 540 => x"fd3d0d75",
+ 541 => x"70718306",
+ 542 => x"53555270",
+ 543 => x"b8387170",
+ 544 => x"087009f7",
+ 545 => x"fbfdff12",
+ 546 => x"0670f884",
+ 547 => x"82818006",
+ 548 => x"51515253",
+ 549 => x"709d3884",
+ 550 => x"13700870",
+ 551 => x"09f7fbfd",
+ 552 => x"ff120670",
+ 553 => x"f8848281",
+ 554 => x"80065151",
+ 555 => x"52537080",
+ 556 => x"2ee53872",
+ 557 => x"52713351",
+ 558 => x"70802e8a",
+ 559 => x"38811270",
+ 560 => x"33525270",
+ 561 => x"f8387174",
+ 562 => x"31800c85",
+ 563 => x"3d0d04f2",
+ 564 => x"3d0d6062",
+ 565 => x"88110870",
+ 566 => x"57575f5a",
+ 567 => x"74802e81",
+ 568 => x"90388c1a",
+ 569 => x"2270832a",
+ 570 => x"81327081",
+ 571 => x"06515558",
+ 572 => x"73863890",
+ 573 => x"1a089138",
+ 574 => x"795190a2",
+ 575 => x"3fff5480",
+ 576 => x"0880ee38",
+ 577 => x"8c1a2258",
+ 578 => x"7d085780",
+ 579 => x"7883ffff",
+ 580 => x"06700a10",
+ 581 => x"0a708106",
+ 582 => x"51565755",
+ 583 => x"73752e80",
+ 584 => x"d7387490",
+ 585 => x"38760884",
+ 586 => x"18088819",
+ 587 => x"59565974",
+ 588 => x"802ef238",
+ 589 => x"74548880",
+ 590 => x"75278438",
+ 591 => x"88805473",
+ 592 => x"5378529c",
+ 593 => x"1a0851a4",
+ 594 => x"1a085473",
+ 595 => x"2d800b80",
+ 596 => x"082582e6",
+ 597 => x"38800819",
+ 598 => x"75800831",
+ 599 => x"7f880508",
+ 600 => x"80083170",
+ 601 => x"6188050c",
+ 602 => x"56565973",
+ 603 => x"ffb43880",
+ 604 => x"5473800c",
+ 605 => x"903d0d04",
+ 606 => x"75813270",
+ 607 => x"81067641",
+ 608 => x"51547380",
+ 609 => x"2e81c138",
+ 610 => x"74903876",
+ 611 => x"08841808",
+ 612 => x"88195956",
+ 613 => x"5974802e",
+ 614 => x"f238881a",
+ 615 => x"087883ff",
+ 616 => x"ff067089",
+ 617 => x"2a708106",
+ 618 => x"51565956",
+ 619 => x"73802e82",
+ 620 => x"fa387575",
+ 621 => x"278d3877",
+ 622 => x"872a7081",
+ 623 => x"06515473",
+ 624 => x"82b53874",
+ 625 => x"76278338",
+ 626 => x"74567553",
+ 627 => x"78527908",
+ 628 => x"5185823f",
+ 629 => x"881a0876",
+ 630 => x"31881b0c",
+ 631 => x"7908167a",
+ 632 => x"0c745675",
+ 633 => x"19757731",
+ 634 => x"7f880508",
+ 635 => x"78317061",
+ 636 => x"88050c56",
+ 637 => x"56597380",
+ 638 => x"2efef438",
+ 639 => x"8c1a2258",
+ 640 => x"ff863977",
+ 641 => x"78547953",
+ 642 => x"7b525684",
+ 643 => x"c83f881a",
+ 644 => x"08783188",
+ 645 => x"1b0c7908",
+ 646 => x"187a0c7c",
+ 647 => x"76315d7c",
+ 648 => x"8e387951",
+ 649 => x"8fdc3f80",
+ 650 => x"08818f38",
+ 651 => x"80085f75",
+ 652 => x"19757731",
+ 653 => x"7f880508",
+ 654 => x"78317061",
+ 655 => x"88050c56",
+ 656 => x"56597380",
+ 657 => x"2efea838",
+ 658 => x"74818338",
+ 659 => x"76088418",
+ 660 => x"08881959",
+ 661 => x"56597480",
+ 662 => x"2ef23874",
+ 663 => x"538a5278",
+ 664 => x"5182d33f",
+ 665 => x"80087931",
+ 666 => x"81055d80",
+ 667 => x"08843881",
+ 668 => x"155d815f",
+ 669 => x"7c58747d",
+ 670 => x"27833874",
+ 671 => x"58941a08",
+ 672 => x"881b0811",
+ 673 => x"575c807a",
+ 674 => x"085c5490",
+ 675 => x"1a087b27",
+ 676 => x"83388154",
+ 677 => x"75782584",
+ 678 => x"3873ba38",
+ 679 => x"7b7824fe",
+ 680 => x"e2387b53",
+ 681 => x"78529c1a",
+ 682 => x"0851a41a",
+ 683 => x"0854732d",
+ 684 => x"80085680",
+ 685 => x"088024fe",
+ 686 => x"e2388c1a",
+ 687 => x"2280c007",
+ 688 => x"54738c1b",
+ 689 => x"23ff5473",
+ 690 => x"800c903d",
+ 691 => x"0d047eff",
+ 692 => x"a338ff87",
+ 693 => x"39755378",
+ 694 => x"527a5182",
+ 695 => x"f83f7908",
+ 696 => x"167a0c79",
+ 697 => x"518e9b3f",
+ 698 => x"8008cf38",
+ 699 => x"7c76315d",
+ 700 => x"7cfebc38",
+ 701 => x"feac3990",
+ 702 => x"1a087a08",
+ 703 => x"71317611",
+ 704 => x"70565a57",
+ 705 => x"5280cd8c",
+ 706 => x"0851848c",
+ 707 => x"3f800880",
+ 708 => x"2effa738",
+ 709 => x"8008901b",
+ 710 => x"0c800816",
+ 711 => x"7a0c7794",
+ 712 => x"1b0c7488",
+ 713 => x"1b0c7456",
+ 714 => x"fd993979",
+ 715 => x"0858901a",
+ 716 => x"08782783",
+ 717 => x"38815475",
+ 718 => x"75278438",
+ 719 => x"73b33894",
+ 720 => x"1a085675",
+ 721 => x"752680d3",
+ 722 => x"38755378",
+ 723 => x"529c1a08",
+ 724 => x"51a41a08",
+ 725 => x"54732d80",
+ 726 => x"08568008",
+ 727 => x"8024fd83",
+ 728 => x"388c1a22",
+ 729 => x"80c00754",
+ 730 => x"738c1b23",
+ 731 => x"ff54fed7",
+ 732 => x"39755378",
+ 733 => x"52775181",
+ 734 => x"dc3f7908",
+ 735 => x"167a0c79",
+ 736 => x"518cff3f",
+ 737 => x"8008802e",
+ 738 => x"fcd9388c",
+ 739 => x"1a2280c0",
+ 740 => x"0754738c",
+ 741 => x"1b23ff54",
+ 742 => x"fead3974",
+ 743 => x"75547953",
+ 744 => x"78525681",
+ 745 => x"b03f881a",
+ 746 => x"08753188",
+ 747 => x"1b0c7908",
+ 748 => x"157a0cfc",
+ 749 => x"ae39fa3d",
+ 750 => x"0d7a7902",
+ 751 => x"8805a705",
+ 752 => x"33565253",
+ 753 => x"8373278a",
+ 754 => x"38708306",
+ 755 => x"5271802e",
+ 756 => x"a838ff13",
+ 757 => x"5372ff2e",
+ 758 => x"97387033",
+ 759 => x"5273722e",
+ 760 => x"91388111",
+ 761 => x"ff145451",
+ 762 => x"72ff2e09",
+ 763 => x"8106eb38",
+ 764 => x"80517080",
+ 765 => x"0c883d0d",
+ 766 => x"04707257",
+ 767 => x"55835175",
+ 768 => x"82802914",
+ 769 => x"ff125256",
+ 770 => x"708025f3",
+ 771 => x"38837327",
+ 772 => x"bf387408",
+ 773 => x"76327009",
+ 774 => x"f7fbfdff",
+ 775 => x"120670f8",
+ 776 => x"84828180",
+ 777 => x"06515151",
+ 778 => x"70802e99",
+ 779 => x"38745180",
+ 780 => x"52703357",
+ 781 => x"73772eff",
+ 782 => x"b9388111",
+ 783 => x"81135351",
+ 784 => x"837227ed",
+ 785 => x"38fc1384",
+ 786 => x"16565372",
+ 787 => x"8326c338",
+ 788 => x"7451fefe",
+ 789 => x"39fa3d0d",
+ 790 => x"787a7c72",
+ 791 => x"72725757",
+ 792 => x"57595656",
+ 793 => x"747627b2",
+ 794 => x"38761551",
+ 795 => x"757127aa",
+ 796 => x"38707717",
+ 797 => x"ff145455",
+ 798 => x"5371ff2e",
+ 799 => x"9638ff14",
+ 800 => x"ff145454",
+ 801 => x"72337434",
+ 802 => x"ff125271",
+ 803 => x"ff2e0981",
+ 804 => x"06ec3875",
+ 805 => x"800c883d",
+ 806 => x"0d04768f",
+ 807 => x"269738ff",
+ 808 => x"125271ff",
+ 809 => x"2eed3872",
+ 810 => x"70810554",
+ 811 => x"33747081",
+ 812 => x"055634eb",
+ 813 => x"39747607",
+ 814 => x"83065170",
+ 815 => x"e2387575",
+ 816 => x"54517270",
+ 817 => x"84055408",
+ 818 => x"71708405",
+ 819 => x"530c7270",
+ 820 => x"84055408",
+ 821 => x"71708405",
+ 822 => x"530c7270",
+ 823 => x"84055408",
+ 824 => x"71708405",
+ 825 => x"530c7270",
+ 826 => x"84055408",
+ 827 => x"71708405",
+ 828 => x"530cf012",
+ 829 => x"52718f26",
+ 830 => x"c9388372",
+ 831 => x"27953872",
+ 832 => x"70840554",
+ 833 => x"08717084",
+ 834 => x"05530cfc",
+ 835 => x"12527183",
+ 836 => x"26ed3870",
+ 837 => x"54ff8839",
+ 838 => x"ef3d0d63",
+ 839 => x"6567405d",
+ 840 => x"427b802e",
+ 841 => x"84fa3861",
+ 842 => x"51a5b63f",
+ 843 => x"f81c7084",
+ 844 => x"120870fc",
+ 845 => x"0670628b",
+ 846 => x"0570f806",
+ 847 => x"4159455b",
+ 848 => x"5c415796",
+ 849 => x"742782c3",
+ 850 => x"38807b24",
+ 851 => x"7e7c2607",
+ 852 => x"59805478",
+ 853 => x"742e0981",
+ 854 => x"0682a938",
+ 855 => x"777b2581",
+ 856 => x"fc387717",
+ 857 => x"80d4c80b",
+ 858 => x"8805085e",
+ 859 => x"567c762e",
+ 860 => x"84bd3884",
+ 861 => x"160870fe",
+ 862 => x"06178411",
+ 863 => x"08810651",
+ 864 => x"55557382",
+ 865 => x"8b3874fc",
+ 866 => x"06597c76",
+ 867 => x"2e84dd38",
+ 868 => x"77195f7e",
+ 869 => x"7b2581fd",
+ 870 => x"38798106",
+ 871 => x"547382bf",
+ 872 => x"38767708",
+ 873 => x"31841108",
+ 874 => x"fc06565a",
+ 875 => x"75802e91",
+ 876 => x"387c762e",
+ 877 => x"84ea3874",
+ 878 => x"19185978",
+ 879 => x"7b258489",
+ 880 => x"3879802e",
+ 881 => x"82993877",
+ 882 => x"15567a76",
+ 883 => x"24829038",
+ 884 => x"8c1a0888",
+ 885 => x"1b08718c",
+ 886 => x"120c8812",
+ 887 => x"0c557976",
+ 888 => x"59578817",
+ 889 => x"61fc0557",
+ 890 => x"5975a426",
+ 891 => x"85ef387b",
+ 892 => x"79555593",
+ 893 => x"762780c9",
+ 894 => x"387b7084",
+ 895 => x"055d087c",
+ 896 => x"56790c74",
+ 897 => x"70840556",
+ 898 => x"088c180c",
+ 899 => x"9017549b",
+ 900 => x"7627ae38",
+ 901 => x"74708405",
+ 902 => x"5608740c",
+ 903 => x"74708405",
+ 904 => x"56089418",
+ 905 => x"0c981754",
+ 906 => x"a3762795",
+ 907 => x"38747084",
+ 908 => x"05560874",
+ 909 => x"0c747084",
+ 910 => x"0556089c",
+ 911 => x"180ca017",
+ 912 => x"54747084",
+ 913 => x"05560874",
+ 914 => x"70840556",
+ 915 => x"0c747084",
+ 916 => x"05560874",
+ 917 => x"70840556",
+ 918 => x"0c740874",
+ 919 => x"0c777b31",
+ 920 => x"56758f26",
+ 921 => x"80c93884",
+ 922 => x"17088106",
+ 923 => x"78078418",
+ 924 => x"0c771784",
+ 925 => x"11088107",
+ 926 => x"84120c54",
+ 927 => x"6151a2e2",
+ 928 => x"3f881754",
+ 929 => x"73800c93",
+ 930 => x"3d0d0490",
+ 931 => x"5bfdba39",
+ 932 => x"7856fe85",
+ 933 => x"398c1608",
+ 934 => x"88170871",
+ 935 => x"8c120c88",
+ 936 => x"120c557e",
+ 937 => x"707c3157",
+ 938 => x"588f7627",
+ 939 => x"ffb9387a",
+ 940 => x"17841808",
+ 941 => x"81067c07",
+ 942 => x"84190c76",
+ 943 => x"81078412",
+ 944 => x"0c761184",
+ 945 => x"11088107",
+ 946 => x"84120c55",
+ 947 => x"88055261",
+ 948 => x"518cf73f",
+ 949 => x"6151a28a",
+ 950 => x"3f881754",
+ 951 => x"ffa6397d",
+ 952 => x"52615194",
+ 953 => x"f73f8008",
+ 954 => x"59800880",
+ 955 => x"2e81a338",
+ 956 => x"8008f805",
+ 957 => x"60840508",
+ 958 => x"fe066105",
+ 959 => x"55577674",
+ 960 => x"2e83e638",
+ 961 => x"fc185675",
+ 962 => x"a42681aa",
+ 963 => x"387b8008",
+ 964 => x"55559376",
+ 965 => x"2780d838",
+ 966 => x"74708405",
+ 967 => x"56088008",
+ 968 => x"70840580",
+ 969 => x"0c0c8008",
+ 970 => x"75708405",
+ 971 => x"57087170",
+ 972 => x"8405530c",
+ 973 => x"549b7627",
+ 974 => x"b6387470",
+ 975 => x"84055608",
+ 976 => x"74708405",
+ 977 => x"560c7470",
+ 978 => x"84055608",
+ 979 => x"74708405",
+ 980 => x"560ca376",
+ 981 => x"27993874",
+ 982 => x"70840556",
+ 983 => x"08747084",
+ 984 => x"05560c74",
+ 985 => x"70840556",
+ 986 => x"08747084",
+ 987 => x"05560c74",
+ 988 => x"70840556",
+ 989 => x"08747084",
+ 990 => x"05560c74",
+ 991 => x"70840556",
+ 992 => x"08747084",
+ 993 => x"05560c74",
+ 994 => x"08740c7b",
+ 995 => x"5261518b",
+ 996 => x"b93f6151",
+ 997 => x"a0cc3f78",
+ 998 => x"5473800c",
+ 999 => x"933d0d04",
+ 1000 => x"7d526151",
+ 1001 => x"93b63f80",
+ 1002 => x"08800c93",
+ 1003 => x"3d0d0484",
+ 1004 => x"160855fb",
+ 1005 => x"d1397553",
+ 1006 => x"7b528008",
+ 1007 => x"51efc73f",
+ 1008 => x"7b526151",
+ 1009 => x"8b843fca",
+ 1010 => x"398c1608",
+ 1011 => x"88170871",
+ 1012 => x"8c120c88",
+ 1013 => x"120c558c",
+ 1014 => x"1a08881b",
+ 1015 => x"08718c12",
+ 1016 => x"0c88120c",
+ 1017 => x"55797959",
+ 1018 => x"57fbf739",
+ 1019 => x"7719901c",
+ 1020 => x"55557375",
+ 1021 => x"24fba238",
+ 1022 => x"7a177080",
+ 1023 => x"d4c80b88",
+ 1024 => x"050c757c",
+ 1025 => x"31810784",
+ 1026 => x"120c5d84",
+ 1027 => x"17088106",
+ 1028 => x"7b078418",
+ 1029 => x"0c61519f",
+ 1030 => x"c93f8817",
+ 1031 => x"54fce539",
+ 1032 => x"74191890",
+ 1033 => x"1c555d73",
+ 1034 => x"7d24fb95",
+ 1035 => x"388c1a08",
+ 1036 => x"881b0871",
+ 1037 => x"8c120c88",
+ 1038 => x"120c5588",
+ 1039 => x"1a61fc05",
+ 1040 => x"575975a4",
+ 1041 => x"2681ae38",
+ 1042 => x"7b795555",
+ 1043 => x"93762780",
+ 1044 => x"c9387b70",
+ 1045 => x"84055d08",
+ 1046 => x"7c56790c",
+ 1047 => x"74708405",
+ 1048 => x"56088c1b",
+ 1049 => x"0c901a54",
+ 1050 => x"9b7627ae",
+ 1051 => x"38747084",
+ 1052 => x"05560874",
+ 1053 => x"0c747084",
+ 1054 => x"05560894",
+ 1055 => x"1b0c981a",
+ 1056 => x"54a37627",
+ 1057 => x"95387470",
+ 1058 => x"84055608",
+ 1059 => x"740c7470",
+ 1060 => x"84055608",
+ 1061 => x"9c1b0ca0",
+ 1062 => x"1a547470",
+ 1063 => x"84055608",
+ 1064 => x"74708405",
+ 1065 => x"560c7470",
+ 1066 => x"84055608",
+ 1067 => x"74708405",
+ 1068 => x"560c7408",
+ 1069 => x"740c7a1a",
+ 1070 => x"7080d4c8",
+ 1071 => x"0b88050c",
+ 1072 => x"7d7c3181",
+ 1073 => x"0784120c",
+ 1074 => x"54841a08",
+ 1075 => x"81067b07",
+ 1076 => x"841b0c61",
+ 1077 => x"519e8b3f",
+ 1078 => x"7854fdbd",
+ 1079 => x"3975537b",
+ 1080 => x"527851ed",
+ 1081 => x"a13ffaf5",
+ 1082 => x"39841708",
+ 1083 => x"fc061860",
+ 1084 => x"5858fae9",
+ 1085 => x"3975537b",
+ 1086 => x"527851ed",
+ 1087 => x"893f7a1a",
+ 1088 => x"7080d4c8",
+ 1089 => x"0b88050c",
+ 1090 => x"7d7c3181",
+ 1091 => x"0784120c",
+ 1092 => x"54841a08",
+ 1093 => x"81067b07",
+ 1094 => x"841b0cff",
+ 1095 => x"b639fa3d",
+ 1096 => x"0d7880cd",
+ 1097 => x"8c085455",
+ 1098 => x"b8130880",
+ 1099 => x"2e81b638",
+ 1100 => x"8c152270",
+ 1101 => x"83ffff06",
+ 1102 => x"70832a81",
+ 1103 => x"32708106",
+ 1104 => x"51555556",
+ 1105 => x"72802e80",
+ 1106 => x"dc387384",
+ 1107 => x"2a813281",
+ 1108 => x"0657ff53",
+ 1109 => x"7680f738",
+ 1110 => x"73822a70",
+ 1111 => x"81065153",
+ 1112 => x"72802eb9",
+ 1113 => x"38b01508",
+ 1114 => x"5473802e",
+ 1115 => x"9c3880c0",
+ 1116 => x"15537373",
+ 1117 => x"2e8f3873",
+ 1118 => x"5280cd8c",
+ 1119 => x"085187ca",
+ 1120 => x"3f8c1522",
+ 1121 => x"5676b016",
+ 1122 => x"0c75db06",
+ 1123 => x"53728c16",
+ 1124 => x"23800b84",
+ 1125 => x"160c9015",
+ 1126 => x"08750c72",
+ 1127 => x"56758807",
+ 1128 => x"53728c16",
+ 1129 => x"23901508",
+ 1130 => x"802e80c1",
+ 1131 => x"388c1522",
+ 1132 => x"70810655",
+ 1133 => x"53739e38",
+ 1134 => x"720a100a",
+ 1135 => x"70810651",
+ 1136 => x"53728538",
+ 1137 => x"94150854",
+ 1138 => x"7388160c",
+ 1139 => x"80537280",
+ 1140 => x"0c883d0d",
+ 1141 => x"04800b88",
+ 1142 => x"160c9415",
+ 1143 => x"08309816",
+ 1144 => x"0c8053ea",
+ 1145 => x"39725182",
+ 1146 => x"fb3ffec4",
+ 1147 => x"3974518c",
+ 1148 => x"e83f8c15",
+ 1149 => x"22708106",
+ 1150 => x"55537380",
+ 1151 => x"2effb938",
+ 1152 => x"d439f83d",
+ 1153 => x"0d7a5877",
+ 1154 => x"802e8199",
+ 1155 => x"3880cd8c",
+ 1156 => x"0854b814",
+ 1157 => x"08802e80",
+ 1158 => x"ed388c18",
+ 1159 => x"2270902b",
+ 1160 => x"70902c70",
+ 1161 => x"832a8132",
+ 1162 => x"81065c51",
+ 1163 => x"57547880",
+ 1164 => x"cd389018",
+ 1165 => x"08577680",
+ 1166 => x"2e80c338",
+ 1167 => x"77087731",
+ 1168 => x"77790c76",
+ 1169 => x"83067a58",
+ 1170 => x"55557385",
+ 1171 => x"38941808",
+ 1172 => x"56758819",
+ 1173 => x"0c807525",
+ 1174 => x"a5387453",
+ 1175 => x"76529c18",
+ 1176 => x"0851a418",
+ 1177 => x"0854732d",
+ 1178 => x"800b8008",
+ 1179 => x"2580c938",
+ 1180 => x"80081775",
+ 1181 => x"80083156",
+ 1182 => x"57748024",
+ 1183 => x"dd38800b",
+ 1184 => x"800c8a3d",
+ 1185 => x"0d047351",
+ 1186 => x"81da3f8c",
+ 1187 => x"18227090",
+ 1188 => x"2b70902c",
+ 1189 => x"70832a81",
+ 1190 => x"3281065c",
+ 1191 => x"51575478",
+ 1192 => x"dd38ff8e",
+ 1193 => x"39a48252",
+ 1194 => x"80cd8c08",
+ 1195 => x"5189f13f",
+ 1196 => x"8008800c",
+ 1197 => x"8a3d0d04",
+ 1198 => x"8c182280",
+ 1199 => x"c0075473",
+ 1200 => x"8c1923ff",
+ 1201 => x"0b800c8a",
+ 1202 => x"3d0d0480",
+ 1203 => x"3d0d7251",
+ 1204 => x"80710c80",
+ 1205 => x"0b84120c",
+ 1206 => x"800b8812",
+ 1207 => x"0c028e05",
+ 1208 => x"228c1223",
+ 1209 => x"02920522",
+ 1210 => x"8e122380",
+ 1211 => x"0b90120c",
+ 1212 => x"800b9412",
+ 1213 => x"0c800b98",
+ 1214 => x"120c709c",
+ 1215 => x"120c80c0",
+ 1216 => x"970ba012",
+ 1217 => x"0c80c0e3",
+ 1218 => x"0ba4120c",
+ 1219 => x"80c1df0b",
+ 1220 => x"a8120c80",
+ 1221 => x"c2b00bac",
+ 1222 => x"120c823d",
+ 1223 => x"0d04fa3d",
+ 1224 => x"0d797080",
+ 1225 => x"dc298c11",
+ 1226 => x"547a5356",
+ 1227 => x"578cad3f",
+ 1228 => x"80088008",
+ 1229 => x"55568008",
+ 1230 => x"802ea238",
+ 1231 => x"80088c05",
+ 1232 => x"54800b80",
+ 1233 => x"080c7680",
+ 1234 => x"0884050c",
+ 1235 => x"73800888",
+ 1236 => x"050c7453",
+ 1237 => x"80527351",
+ 1238 => x"97f83f75",
+ 1239 => x"5473800c",
+ 1240 => x"883d0d04",
+ 1241 => x"fc3d0d76",
+ 1242 => x"a8f70bbc",
+ 1243 => x"120c5581",
+ 1244 => x"0bb8160c",
+ 1245 => x"800b84dc",
+ 1246 => x"160c830b",
+ 1247 => x"84e0160c",
+ 1248 => x"84e81584",
+ 1249 => x"e4160c74",
+ 1250 => x"54805384",
+ 1251 => x"52841508",
+ 1252 => x"51feb83f",
+ 1253 => x"74548153",
+ 1254 => x"89528815",
+ 1255 => x"0851feab",
+ 1256 => x"3f745482",
+ 1257 => x"538a528c",
+ 1258 => x"150851fe",
+ 1259 => x"9e3f863d",
+ 1260 => x"0d04f93d",
+ 1261 => x"0d7980cd",
+ 1262 => x"8c085457",
+ 1263 => x"b8130880",
+ 1264 => x"2e80c838",
+ 1265 => x"84dc1356",
+ 1266 => x"88160884",
+ 1267 => x"1708ff05",
+ 1268 => x"55558074",
+ 1269 => x"249f388c",
+ 1270 => x"15227090",
+ 1271 => x"2b70902c",
+ 1272 => x"51545872",
+ 1273 => x"802e80ca",
+ 1274 => x"3880dc15",
+ 1275 => x"ff155555",
+ 1276 => x"738025e3",
+ 1277 => x"38750853",
+ 1278 => x"72802e9f",
+ 1279 => x"38725688",
+ 1280 => x"16088417",
+ 1281 => x"08ff0555",
+ 1282 => x"55c83972",
+ 1283 => x"51fed53f",
+ 1284 => x"80cd8c08",
+ 1285 => x"84dc0556",
+ 1286 => x"ffae3984",
+ 1287 => x"527651fd",
+ 1288 => x"fd3f8008",
+ 1289 => x"760c8008",
+ 1290 => x"802e80c0",
+ 1291 => x"38800856",
+ 1292 => x"ce39810b",
+ 1293 => x"8c162372",
+ 1294 => x"750c7288",
+ 1295 => x"160c7284",
+ 1296 => x"160c7290",
+ 1297 => x"160c7294",
+ 1298 => x"160c7298",
+ 1299 => x"160cff0b",
+ 1300 => x"8e162372",
+ 1301 => x"b0160c72",
+ 1302 => x"b4160c72",
+ 1303 => x"80c4160c",
+ 1304 => x"7280c816",
+ 1305 => x"0c74800c",
+ 1306 => x"893d0d04",
+ 1307 => x"8c770c80",
+ 1308 => x"0b800c89",
+ 1309 => x"3d0d04ff",
+ 1310 => x"3d0da482",
+ 1311 => x"52735186",
+ 1312 => x"9f3f833d",
+ 1313 => x"0d04803d",
+ 1314 => x"0d80cd8c",
+ 1315 => x"0851e83f",
+ 1316 => x"823d0d04",
+ 1317 => x"fb3d0d77",
+ 1318 => x"70525696",
+ 1319 => x"c43f80d4",
+ 1320 => x"c80b8805",
+ 1321 => x"08841108",
+ 1322 => x"fc06707b",
+ 1323 => x"319fef05",
+ 1324 => x"e08006e0",
+ 1325 => x"80055656",
+ 1326 => x"53a08074",
+ 1327 => x"24943880",
+ 1328 => x"52755196",
+ 1329 => x"9e3f80d4",
+ 1330 => x"d0081553",
+ 1331 => x"7280082e",
+ 1332 => x"8f387551",
+ 1333 => x"968c3f80",
+ 1334 => x"5372800c",
+ 1335 => x"873d0d04",
+ 1336 => x"73305275",
+ 1337 => x"5195fc3f",
+ 1338 => x"8008ff2e",
+ 1339 => x"a83880d4",
+ 1340 => x"c80b8805",
+ 1341 => x"08757531",
+ 1342 => x"81078412",
+ 1343 => x"0c5380d4",
+ 1344 => x"8c087431",
+ 1345 => x"80d48c0c",
+ 1346 => x"755195d6",
+ 1347 => x"3f810b80",
+ 1348 => x"0c873d0d",
+ 1349 => x"04805275",
+ 1350 => x"5195c83f",
+ 1351 => x"80d4c80b",
+ 1352 => x"88050880",
+ 1353 => x"08713156",
+ 1354 => x"538f7525",
+ 1355 => x"ffa43880",
+ 1356 => x"0880d4bc",
+ 1357 => x"083180d4",
+ 1358 => x"8c0c7481",
+ 1359 => x"0784140c",
+ 1360 => x"7551959e",
+ 1361 => x"3f8053ff",
+ 1362 => x"9039f63d",
+ 1363 => x"0d7c7e54",
+ 1364 => x"5b72802e",
+ 1365 => x"8283387a",
+ 1366 => x"5195863f",
+ 1367 => x"f8138411",
+ 1368 => x"0870fe06",
+ 1369 => x"70138411",
+ 1370 => x"08fc065d",
+ 1371 => x"58595458",
+ 1372 => x"80d4d008",
+ 1373 => x"752e82de",
+ 1374 => x"38788416",
+ 1375 => x"0c807381",
+ 1376 => x"06545a72",
+ 1377 => x"7a2e81d5",
+ 1378 => x"38781584",
+ 1379 => x"11088106",
+ 1380 => x"515372a0",
+ 1381 => x"38781757",
+ 1382 => x"7981e638",
+ 1383 => x"88150853",
+ 1384 => x"7280d4d0",
+ 1385 => x"2e82f938",
+ 1386 => x"8c150870",
+ 1387 => x"8c150c73",
+ 1388 => x"88120c56",
+ 1389 => x"76810784",
+ 1390 => x"190c7618",
+ 1391 => x"77710c53",
+ 1392 => x"79819138",
+ 1393 => x"83ff7727",
+ 1394 => x"81c83876",
+ 1395 => x"892a7783",
+ 1396 => x"2a565372",
+ 1397 => x"802ebf38",
+ 1398 => x"76862ab8",
+ 1399 => x"05558473",
+ 1400 => x"27b43880",
+ 1401 => x"db135594",
+ 1402 => x"7327ab38",
+ 1403 => x"768c2a80",
+ 1404 => x"ee055580",
+ 1405 => x"d473279e",
+ 1406 => x"38768f2a",
+ 1407 => x"80f70555",
+ 1408 => x"82d47327",
+ 1409 => x"91387692",
+ 1410 => x"2a80fc05",
+ 1411 => x"558ad473",
+ 1412 => x"27843880",
+ 1413 => x"fe557410",
+ 1414 => x"101080d4",
+ 1415 => x"c8058811",
+ 1416 => x"08555673",
+ 1417 => x"762e82b3",
+ 1418 => x"38841408",
+ 1419 => x"fc065376",
+ 1420 => x"73278d38",
+ 1421 => x"88140854",
+ 1422 => x"73762e09",
+ 1423 => x"8106ea38",
+ 1424 => x"8c140870",
+ 1425 => x"8c1a0c74",
+ 1426 => x"881a0c78",
+ 1427 => x"88120c56",
+ 1428 => x"778c150c",
+ 1429 => x"7a51938a",
+ 1430 => x"3f8c3d0d",
+ 1431 => x"04770878",
+ 1432 => x"71315977",
+ 1433 => x"05881908",
+ 1434 => x"54577280",
+ 1435 => x"d4d02e80",
+ 1436 => x"e0388c18",
+ 1437 => x"08708c15",
+ 1438 => x"0c738812",
+ 1439 => x"0c56fe89",
+ 1440 => x"39881508",
+ 1441 => x"8c160870",
+ 1442 => x"8c130c57",
+ 1443 => x"88170cfe",
+ 1444 => x"a3397683",
+ 1445 => x"2a705455",
+ 1446 => x"80752481",
+ 1447 => x"98387282",
+ 1448 => x"2c81712b",
+ 1449 => x"80d4cc08",
+ 1450 => x"0780d4c8",
+ 1451 => x"0b84050c",
+ 1452 => x"53741010",
+ 1453 => x"1080d4c8",
+ 1454 => x"05881108",
+ 1455 => x"5556758c",
+ 1456 => x"190c7388",
+ 1457 => x"190c7788",
+ 1458 => x"170c778c",
+ 1459 => x"150cff84",
+ 1460 => x"39815afd",
+ 1461 => x"b4397817",
+ 1462 => x"73810654",
+ 1463 => x"57729838",
+ 1464 => x"77087871",
+ 1465 => x"31597705",
+ 1466 => x"8c190888",
+ 1467 => x"1a08718c",
+ 1468 => x"120c8812",
+ 1469 => x"0c575776",
+ 1470 => x"81078419",
+ 1471 => x"0c7780d4",
+ 1472 => x"c80b8805",
+ 1473 => x"0c80d4c4",
+ 1474 => x"087726fe",
+ 1475 => x"c73880d4",
+ 1476 => x"c008527a",
+ 1477 => x"51fafd3f",
+ 1478 => x"7a5191c6",
+ 1479 => x"3ffeba39",
+ 1480 => x"81788c15",
+ 1481 => x"0c788815",
+ 1482 => x"0c738c1a",
+ 1483 => x"0c73881a",
+ 1484 => x"0c5afd80",
+ 1485 => x"39831570",
+ 1486 => x"822c8171",
+ 1487 => x"2b80d4cc",
+ 1488 => x"080780d4",
+ 1489 => x"c80b8405",
+ 1490 => x"0c515374",
+ 1491 => x"10101080",
+ 1492 => x"d4c80588",
+ 1493 => x"11085556",
+ 1494 => x"fee43974",
+ 1495 => x"53807524",
+ 1496 => x"a7387282",
+ 1497 => x"2c81712b",
+ 1498 => x"80d4cc08",
+ 1499 => x"0780d4c8",
+ 1500 => x"0b84050c",
+ 1501 => x"53758c19",
+ 1502 => x"0c738819",
+ 1503 => x"0c778817",
+ 1504 => x"0c778c15",
+ 1505 => x"0cfdcd39",
+ 1506 => x"83157082",
+ 1507 => x"2c81712b",
+ 1508 => x"80d4cc08",
+ 1509 => x"0780d4c8",
+ 1510 => x"0b84050c",
+ 1511 => x"5153d639",
+ 1512 => x"f93d0d79",
+ 1513 => x"7b585380",
+ 1514 => x"0b80cd8c",
+ 1515 => x"08535672",
+ 1516 => x"722e80c0",
+ 1517 => x"3884dc13",
+ 1518 => x"5574762e",
+ 1519 => x"b7388815",
+ 1520 => x"08841608",
+ 1521 => x"ff055454",
+ 1522 => x"8073249d",
+ 1523 => x"388c1422",
+ 1524 => x"70902b70",
+ 1525 => x"902c5153",
+ 1526 => x"587180d8",
+ 1527 => x"3880dc14",
+ 1528 => x"ff145454",
+ 1529 => x"728025e5",
+ 1530 => x"38740855",
+ 1531 => x"74d03880",
+ 1532 => x"cd8c0852",
+ 1533 => x"84dc1255",
+ 1534 => x"74802eb1",
+ 1535 => x"38881508",
+ 1536 => x"841608ff",
+ 1537 => x"05545480",
+ 1538 => x"73249c38",
+ 1539 => x"8c142270",
+ 1540 => x"902b7090",
+ 1541 => x"2c515358",
+ 1542 => x"71ad3880",
+ 1543 => x"dc14ff14",
+ 1544 => x"54547280",
+ 1545 => x"25e63874",
+ 1546 => x"085574d1",
+ 1547 => x"3875800c",
+ 1548 => x"893d0d04",
+ 1549 => x"7351762d",
+ 1550 => x"75800807",
+ 1551 => x"80dc15ff",
+ 1552 => x"15555556",
+ 1553 => x"ff9e3973",
+ 1554 => x"51762d75",
+ 1555 => x"80080780",
+ 1556 => x"dc15ff15",
+ 1557 => x"555556ca",
+ 1558 => x"39ea3d0d",
+ 1559 => x"688c1122",
+ 1560 => x"700a100a",
+ 1561 => x"81065758",
+ 1562 => x"567480e4",
+ 1563 => x"388e1622",
+ 1564 => x"70902b70",
+ 1565 => x"902c5155",
+ 1566 => x"58807424",
+ 1567 => x"b138983d",
+ 1568 => x"c4055373",
+ 1569 => x"5280cd8c",
+ 1570 => x"085192ac",
+ 1571 => x"3f800b80",
+ 1572 => x"08249738",
+ 1573 => x"7983e080",
+ 1574 => x"06547380",
+ 1575 => x"c0802e81",
+ 1576 => x"8f387382",
+ 1577 => x"80802e81",
+ 1578 => x"91388c16",
+ 1579 => x"22577690",
+ 1580 => x"80075473",
+ 1581 => x"8c172388",
+ 1582 => x"805280cd",
+ 1583 => x"8c085181",
+ 1584 => x"9b3f8008",
+ 1585 => x"9d388c16",
+ 1586 => x"22820754",
+ 1587 => x"738c1723",
+ 1588 => x"80c31670",
+ 1589 => x"770c9017",
+ 1590 => x"0c810b94",
+ 1591 => x"170c983d",
+ 1592 => x"0d0480cd",
+ 1593 => x"8c08a8f7",
+ 1594 => x"0bbc120c",
+ 1595 => x"548c1622",
+ 1596 => x"81800754",
+ 1597 => x"738c1723",
+ 1598 => x"8008760c",
+ 1599 => x"80089017",
+ 1600 => x"0c88800b",
+ 1601 => x"94170c74",
+ 1602 => x"802ed338",
+ 1603 => x"8e162270",
+ 1604 => x"902b7090",
+ 1605 => x"2c535558",
+ 1606 => x"98a23f80",
+ 1607 => x"08802eff",
+ 1608 => x"bd388c16",
+ 1609 => x"22810754",
+ 1610 => x"738c1723",
+ 1611 => x"983d0d04",
+ 1612 => x"810b8c17",
+ 1613 => x"225855fe",
+ 1614 => x"f539a816",
+ 1615 => x"0880c1df",
+ 1616 => x"2e098106",
+ 1617 => x"fee4388c",
+ 1618 => x"16228880",
+ 1619 => x"0754738c",
+ 1620 => x"17238880",
+ 1621 => x"0b80cc17",
+ 1622 => x"0cfedc39",
+ 1623 => x"f33d0d7f",
+ 1624 => x"618b1170",
+ 1625 => x"f8065c55",
+ 1626 => x"555e7296",
+ 1627 => x"26833890",
+ 1628 => x"59807924",
+ 1629 => x"747a2607",
+ 1630 => x"53805472",
+ 1631 => x"742e0981",
+ 1632 => x"0680cb38",
+ 1633 => x"7d518cd9",
+ 1634 => x"3f7883f7",
+ 1635 => x"2680c638",
+ 1636 => x"78832a70",
+ 1637 => x"10101080",
+ 1638 => x"d4c8058c",
+ 1639 => x"11085959",
+ 1640 => x"5a76782e",
+ 1641 => x"83b03884",
+ 1642 => x"1708fc06",
+ 1643 => x"568c1708",
+ 1644 => x"88180871",
+ 1645 => x"8c120c88",
+ 1646 => x"120c5875",
+ 1647 => x"17841108",
+ 1648 => x"81078412",
+ 1649 => x"0c537d51",
+ 1650 => x"8c983f88",
+ 1651 => x"17547380",
+ 1652 => x"0c8f3d0d",
+ 1653 => x"0478892a",
+ 1654 => x"79832a5b",
+ 1655 => x"5372802e",
+ 1656 => x"bf387886",
+ 1657 => x"2ab8055a",
+ 1658 => x"847327b4",
+ 1659 => x"3880db13",
+ 1660 => x"5a947327",
+ 1661 => x"ab38788c",
+ 1662 => x"2a80ee05",
+ 1663 => x"5a80d473",
+ 1664 => x"279e3878",
+ 1665 => x"8f2a80f7",
+ 1666 => x"055a82d4",
+ 1667 => x"73279138",
+ 1668 => x"78922a80",
+ 1669 => x"fc055a8a",
+ 1670 => x"d4732784",
+ 1671 => x"3880fe5a",
+ 1672 => x"79101010",
+ 1673 => x"80d4c805",
+ 1674 => x"8c110858",
+ 1675 => x"5576752e",
+ 1676 => x"a3388417",
+ 1677 => x"08fc0670",
+ 1678 => x"7a315556",
+ 1679 => x"738f2488",
+ 1680 => x"d5387380",
+ 1681 => x"25fee638",
+ 1682 => x"8c170857",
+ 1683 => x"76752e09",
+ 1684 => x"8106df38",
+ 1685 => x"811a5a80",
+ 1686 => x"d4d80857",
+ 1687 => x"7680d4d0",
+ 1688 => x"2e82c038",
+ 1689 => x"841708fc",
+ 1690 => x"06707a31",
+ 1691 => x"5556738f",
+ 1692 => x"2481f938",
+ 1693 => x"80d4d00b",
+ 1694 => x"80d4dc0c",
+ 1695 => x"80d4d00b",
+ 1696 => x"80d4d80c",
+ 1697 => x"738025fe",
+ 1698 => x"b23883ff",
+ 1699 => x"762783df",
+ 1700 => x"3875892a",
+ 1701 => x"76832a55",
+ 1702 => x"5372802e",
+ 1703 => x"bf387586",
+ 1704 => x"2ab80554",
+ 1705 => x"847327b4",
+ 1706 => x"3880db13",
+ 1707 => x"54947327",
+ 1708 => x"ab38758c",
+ 1709 => x"2a80ee05",
+ 1710 => x"5480d473",
+ 1711 => x"279e3875",
+ 1712 => x"8f2a80f7",
+ 1713 => x"055482d4",
+ 1714 => x"73279138",
+ 1715 => x"75922a80",
+ 1716 => x"fc05548a",
+ 1717 => x"d4732784",
+ 1718 => x"3880fe54",
+ 1719 => x"73101010",
+ 1720 => x"80d4c805",
+ 1721 => x"88110856",
+ 1722 => x"5874782e",
+ 1723 => x"86cf3884",
+ 1724 => x"1508fc06",
+ 1725 => x"53757327",
+ 1726 => x"8d388815",
+ 1727 => x"08557478",
+ 1728 => x"2e098106",
+ 1729 => x"ea388c15",
+ 1730 => x"0880d4c8",
+ 1731 => x"0b840508",
+ 1732 => x"718c1a0c",
+ 1733 => x"76881a0c",
+ 1734 => x"7888130c",
+ 1735 => x"788c180c",
+ 1736 => x"5d587953",
+ 1737 => x"807a2483",
+ 1738 => x"e6387282",
+ 1739 => x"2c81712b",
+ 1740 => x"5c537a7c",
+ 1741 => x"26819838",
+ 1742 => x"7b7b0653",
+ 1743 => x"7282f138",
+ 1744 => x"79fc0684",
+ 1745 => x"055a7a10",
+ 1746 => x"707d0654",
+ 1747 => x"5b7282e0",
+ 1748 => x"38841a5a",
+ 1749 => x"f1398817",
+ 1750 => x"8c110858",
+ 1751 => x"5876782e",
+ 1752 => x"098106fc",
+ 1753 => x"c238821a",
+ 1754 => x"5afdec39",
+ 1755 => x"78177981",
+ 1756 => x"0784190c",
+ 1757 => x"7080d4dc",
+ 1758 => x"0c7080d4",
+ 1759 => x"d80c80d4",
+ 1760 => x"d00b8c12",
+ 1761 => x"0c8c1108",
+ 1762 => x"88120c74",
+ 1763 => x"81078412",
+ 1764 => x"0c741175",
+ 1765 => x"710c5153",
+ 1766 => x"7d5188c6",
+ 1767 => x"3f881754",
+ 1768 => x"fcac3980",
+ 1769 => x"d4c80b84",
+ 1770 => x"05087a54",
+ 1771 => x"5c798025",
+ 1772 => x"fef83882",
+ 1773 => x"da397a09",
+ 1774 => x"7c067080",
+ 1775 => x"d4c80b84",
+ 1776 => x"050c5c7a",
+ 1777 => x"105b7a7c",
+ 1778 => x"2685387a",
+ 1779 => x"85b83880",
+ 1780 => x"d4c80b88",
+ 1781 => x"05087084",
+ 1782 => x"1208fc06",
+ 1783 => x"707c317c",
+ 1784 => x"72268f72",
+ 1785 => x"25075757",
+ 1786 => x"5c5d5572",
+ 1787 => x"802e80db",
+ 1788 => x"38797a16",
+ 1789 => x"80d4c008",
+ 1790 => x"1b90115a",
+ 1791 => x"55575b80",
+ 1792 => x"d4bc08ff",
+ 1793 => x"2e8838a0",
+ 1794 => x"8f13e080",
+ 1795 => x"06577652",
+ 1796 => x"7d5187cf",
+ 1797 => x"3f800854",
+ 1798 => x"8008ff2e",
+ 1799 => x"90388008",
+ 1800 => x"76278299",
+ 1801 => x"387480d4",
+ 1802 => x"c82e8291",
+ 1803 => x"3880d4c8",
+ 1804 => x"0b880508",
+ 1805 => x"55841508",
+ 1806 => x"fc06707a",
+ 1807 => x"317a7226",
+ 1808 => x"8f722507",
+ 1809 => x"52555372",
+ 1810 => x"83e63874",
+ 1811 => x"79810784",
+ 1812 => x"170c7916",
+ 1813 => x"7080d4c8",
+ 1814 => x"0b88050c",
+ 1815 => x"75810784",
+ 1816 => x"120c547e",
+ 1817 => x"525786fa",
+ 1818 => x"3f881754",
+ 1819 => x"fae03975",
+ 1820 => x"832a7054",
+ 1821 => x"54807424",
+ 1822 => x"819b3872",
+ 1823 => x"822c8171",
+ 1824 => x"2b80d4cc",
+ 1825 => x"08077080",
+ 1826 => x"d4c80b84",
+ 1827 => x"050c7510",
+ 1828 => x"101080d4",
+ 1829 => x"c8058811",
+ 1830 => x"08585a5d",
+ 1831 => x"53778c18",
+ 1832 => x"0c748818",
+ 1833 => x"0c768819",
+ 1834 => x"0c768c16",
+ 1835 => x"0cfcf339",
+ 1836 => x"797a1010",
+ 1837 => x"1080d4c8",
+ 1838 => x"05705759",
+ 1839 => x"5d8c1508",
+ 1840 => x"5776752e",
+ 1841 => x"a3388417",
+ 1842 => x"08fc0670",
+ 1843 => x"7a315556",
+ 1844 => x"738f2483",
+ 1845 => x"ca387380",
+ 1846 => x"25848138",
+ 1847 => x"8c170857",
+ 1848 => x"76752e09",
+ 1849 => x"8106df38",
+ 1850 => x"8815811b",
+ 1851 => x"70830655",
+ 1852 => x"5b5572c9",
+ 1853 => x"387c8306",
+ 1854 => x"5372802e",
+ 1855 => x"fdb838ff",
+ 1856 => x"1df81959",
+ 1857 => x"5d881808",
+ 1858 => x"782eea38",
+ 1859 => x"fdb53983",
+ 1860 => x"1a53fc96",
+ 1861 => x"39831470",
+ 1862 => x"822c8171",
+ 1863 => x"2b80d4cc",
+ 1864 => x"08077080",
+ 1865 => x"d4c80b84",
+ 1866 => x"050c7610",
+ 1867 => x"101080d4",
+ 1868 => x"c8058811",
+ 1869 => x"08595b5e",
+ 1870 => x"5153fee1",
+ 1871 => x"3980d48c",
+ 1872 => x"08175880",
+ 1873 => x"08762e81",
+ 1874 => x"8d3880d4",
+ 1875 => x"bc08ff2e",
+ 1876 => x"83ec3873",
+ 1877 => x"76311880",
+ 1878 => x"d48c0c73",
+ 1879 => x"87067057",
+ 1880 => x"5372802e",
+ 1881 => x"88388873",
+ 1882 => x"31701555",
+ 1883 => x"5676149f",
+ 1884 => x"ff06a080",
+ 1885 => x"71311770",
+ 1886 => x"547f5357",
+ 1887 => x"5384e43f",
+ 1888 => x"80085380",
+ 1889 => x"08ff2e81",
+ 1890 => x"a03880d4",
+ 1891 => x"8c081670",
+ 1892 => x"80d48c0c",
+ 1893 => x"747580d4",
+ 1894 => x"c80b8805",
+ 1895 => x"0c747631",
+ 1896 => x"18708107",
+ 1897 => x"51555658",
+ 1898 => x"7b80d4c8",
+ 1899 => x"2e839c38",
+ 1900 => x"798f2682",
+ 1901 => x"cb38810b",
+ 1902 => x"84150c84",
+ 1903 => x"1508fc06",
+ 1904 => x"707a317a",
+ 1905 => x"72268f72",
+ 1906 => x"25075255",
+ 1907 => x"5372802e",
+ 1908 => x"fcf93880",
+ 1909 => x"db398008",
+ 1910 => x"9fff0653",
+ 1911 => x"72feeb38",
+ 1912 => x"7780d48c",
+ 1913 => x"0c80d4c8",
+ 1914 => x"0b880508",
+ 1915 => x"7b188107",
+ 1916 => x"84120c55",
+ 1917 => x"80d4b808",
+ 1918 => x"78278638",
+ 1919 => x"7780d4b8",
+ 1920 => x"0c80d4b4",
+ 1921 => x"087827fc",
+ 1922 => x"ac387780",
+ 1923 => x"d4b40c84",
+ 1924 => x"1508fc06",
+ 1925 => x"707a317a",
+ 1926 => x"72268f72",
+ 1927 => x"25075255",
+ 1928 => x"5372802e",
+ 1929 => x"fca53888",
+ 1930 => x"39807454",
+ 1931 => x"56fedb39",
+ 1932 => x"7d5183ae",
+ 1933 => x"3f800b80",
+ 1934 => x"0c8f3d0d",
+ 1935 => x"04735380",
+ 1936 => x"7424a938",
+ 1937 => x"72822c81",
+ 1938 => x"712b80d4",
+ 1939 => x"cc080770",
+ 1940 => x"80d4c80b",
+ 1941 => x"84050c5d",
+ 1942 => x"53778c18",
+ 1943 => x"0c748818",
+ 1944 => x"0c768819",
+ 1945 => x"0c768c16",
+ 1946 => x"0cf9b739",
+ 1947 => x"83147082",
+ 1948 => x"2c81712b",
+ 1949 => x"80d4cc08",
+ 1950 => x"077080d4",
+ 1951 => x"c80b8405",
+ 1952 => x"0c5e5153",
+ 1953 => x"d4397b7b",
+ 1954 => x"065372fc",
+ 1955 => x"a338841a",
+ 1956 => x"7b105c5a",
+ 1957 => x"f139ff1a",
+ 1958 => x"8111515a",
+ 1959 => x"f7b93978",
+ 1960 => x"17798107",
+ 1961 => x"84190c8c",
+ 1962 => x"18088819",
+ 1963 => x"08718c12",
+ 1964 => x"0c88120c",
+ 1965 => x"597080d4",
+ 1966 => x"dc0c7080",
+ 1967 => x"d4d80c80",
+ 1968 => x"d4d00b8c",
+ 1969 => x"120c8c11",
+ 1970 => x"0888120c",
+ 1971 => x"74810784",
+ 1972 => x"120c7411",
+ 1973 => x"75710c51",
+ 1974 => x"53f9bd39",
+ 1975 => x"75178411",
+ 1976 => x"08810784",
+ 1977 => x"120c538c",
+ 1978 => x"17088818",
+ 1979 => x"08718c12",
+ 1980 => x"0c88120c",
+ 1981 => x"587d5181",
+ 1982 => x"e93f8817",
+ 1983 => x"54f5cf39",
+ 1984 => x"7284150c",
+ 1985 => x"f41af806",
+ 1986 => x"70841e08",
+ 1987 => x"81060784",
+ 1988 => x"1e0c701d",
+ 1989 => x"545b850b",
+ 1990 => x"84140c85",
+ 1991 => x"0b88140c",
+ 1992 => x"8f7b27fd",
+ 1993 => x"cf38881c",
+ 1994 => x"527d51ec",
+ 1995 => x"9d3f80d4",
+ 1996 => x"c80b8805",
+ 1997 => x"0880d48c",
+ 1998 => x"085955fd",
+ 1999 => x"b7397780",
+ 2000 => x"d48c0c73",
+ 2001 => x"80d4bc0c",
+ 2002 => x"fc913972",
+ 2003 => x"84150cfd",
+ 2004 => x"a339fc3d",
+ 2005 => x"0d767971",
+ 2006 => x"028c059f",
+ 2007 => x"05335755",
+ 2008 => x"53558372",
+ 2009 => x"278a3874",
+ 2010 => x"83065170",
+ 2011 => x"802ea238",
+ 2012 => x"ff125271",
+ 2013 => x"ff2e9338",
+ 2014 => x"73737081",
+ 2015 => x"055534ff",
+ 2016 => x"125271ff",
+ 2017 => x"2e098106",
+ 2018 => x"ef387480",
+ 2019 => x"0c863d0d",
+ 2020 => x"04747488",
+ 2021 => x"2b750770",
+ 2022 => x"71902b07",
+ 2023 => x"5154518f",
+ 2024 => x"7227a538",
+ 2025 => x"72717084",
+ 2026 => x"05530c72",
+ 2027 => x"71708405",
+ 2028 => x"530c7271",
+ 2029 => x"70840553",
+ 2030 => x"0c727170",
+ 2031 => x"8405530c",
+ 2032 => x"f0125271",
+ 2033 => x"8f26dd38",
+ 2034 => x"83722790",
+ 2035 => x"38727170",
+ 2036 => x"8405530c",
+ 2037 => x"fc125271",
+ 2038 => x"8326f238",
+ 2039 => x"7053ff90",
+ 2040 => x"390404fd",
+ 2041 => x"3d0d800b",
+ 2042 => x"80dd800c",
+ 2043 => x"765184ee",
+ 2044 => x"3f800853",
+ 2045 => x"8008ff2e",
+ 2046 => x"88387280",
+ 2047 => x"0c853d0d",
+ 2048 => x"0480dd80",
+ 2049 => x"08547380",
+ 2050 => x"2ef03875",
+ 2051 => x"74710c52",
+ 2052 => x"72800c85",
+ 2053 => x"3d0d04f9",
+ 2054 => x"3d0d797c",
+ 2055 => x"557b548e",
+ 2056 => x"11227090",
+ 2057 => x"2b70902c",
+ 2058 => x"555780cd",
+ 2059 => x"8c085358",
+ 2060 => x"5683f33f",
+ 2061 => x"80085780",
+ 2062 => x"0b800824",
+ 2063 => x"933880d0",
+ 2064 => x"16088008",
+ 2065 => x"0580d017",
+ 2066 => x"0c76800c",
+ 2067 => x"893d0d04",
+ 2068 => x"8c162283",
+ 2069 => x"dfff0655",
+ 2070 => x"748c1723",
+ 2071 => x"76800c89",
+ 2072 => x"3d0d04fa",
+ 2073 => x"3d0d788c",
+ 2074 => x"11227088",
+ 2075 => x"2a708106",
+ 2076 => x"51575856",
+ 2077 => x"74a9388c",
+ 2078 => x"162283df",
+ 2079 => x"ff065574",
+ 2080 => x"8c17237a",
+ 2081 => x"5479538e",
+ 2082 => x"16227090",
+ 2083 => x"2b70902c",
+ 2084 => x"545680cd",
+ 2085 => x"8c085256",
+ 2086 => x"81b23f88",
+ 2087 => x"3d0d0482",
+ 2088 => x"5480538e",
+ 2089 => x"16227090",
+ 2090 => x"2b70902c",
+ 2091 => x"545680cd",
+ 2092 => x"8c085257",
+ 2093 => x"82b83f8c",
+ 2094 => x"162283df",
+ 2095 => x"ff065574",
+ 2096 => x"8c17237a",
+ 2097 => x"5479538e",
+ 2098 => x"16227090",
+ 2099 => x"2b70902c",
+ 2100 => x"545680cd",
+ 2101 => x"8c085256",
+ 2102 => x"80f23f88",
+ 2103 => x"3d0d04f9",
+ 2104 => x"3d0d797c",
+ 2105 => x"557b548e",
+ 2106 => x"11227090",
+ 2107 => x"2b70902c",
+ 2108 => x"555780cd",
+ 2109 => x"8c085358",
+ 2110 => x"5681f33f",
+ 2111 => x"80085780",
+ 2112 => x"08ff2e99",
+ 2113 => x"388c1622",
+ 2114 => x"a0800755",
+ 2115 => x"748c1723",
+ 2116 => x"800880d0",
+ 2117 => x"170c7680",
+ 2118 => x"0c893d0d",
+ 2119 => x"048c1622",
+ 2120 => x"83dfff06",
+ 2121 => x"55748c17",
+ 2122 => x"2376800c",
+ 2123 => x"893d0d04",
+ 2124 => x"fe3d0d74",
+ 2125 => x"8e112270",
+ 2126 => x"902b7090",
+ 2127 => x"2c555151",
+ 2128 => x"5380cd8c",
+ 2129 => x"0851bd3f",
+ 2130 => x"843d0d04",
+ 2131 => x"fb3d0d80",
+ 2132 => x"0b80dd80",
+ 2133 => x"0c7a5379",
+ 2134 => x"52785182",
+ 2135 => x"fc3f8008",
+ 2136 => x"558008ff",
+ 2137 => x"2e883874",
+ 2138 => x"800c873d",
+ 2139 => x"0d0480dd",
+ 2140 => x"80085675",
+ 2141 => x"802ef038",
+ 2142 => x"7776710c",
+ 2143 => x"5474800c",
+ 2144 => x"873d0d04",
+ 2145 => x"fd3d0d80",
+ 2146 => x"0b80dd80",
+ 2147 => x"0c765184",
+ 2148 => x"c63f8008",
+ 2149 => x"538008ff",
+ 2150 => x"2e883872",
+ 2151 => x"800c853d",
+ 2152 => x"0d0480dd",
+ 2153 => x"80085473",
+ 2154 => x"802ef038",
+ 2155 => x"7574710c",
+ 2156 => x"5272800c",
+ 2157 => x"853d0d04",
+ 2158 => x"fc3d0d80",
+ 2159 => x"0b80dd80",
+ 2160 => x"0c785277",
+ 2161 => x"5186ac3f",
+ 2162 => x"80085480",
+ 2163 => x"08ff2e88",
+ 2164 => x"3873800c",
+ 2165 => x"863d0d04",
+ 2166 => x"80dd8008",
+ 2167 => x"5574802e",
+ 2168 => x"f0387675",
+ 2169 => x"710c5373",
+ 2170 => x"800c863d",
+ 2171 => x"0d04fb3d",
+ 2172 => x"0d800b80",
+ 2173 => x"dd800c7a",
+ 2174 => x"53795278",
+ 2175 => x"5184893f",
+ 2176 => x"80085580",
+ 2177 => x"08ff2e88",
+ 2178 => x"3874800c",
+ 2179 => x"873d0d04",
+ 2180 => x"80dd8008",
+ 2181 => x"5675802e",
+ 2182 => x"f0387776",
+ 2183 => x"710c5474",
+ 2184 => x"800c873d",
+ 2185 => x"0d04fb3d",
+ 2186 => x"0d800b80",
+ 2187 => x"dd800c7a",
+ 2188 => x"53795278",
+ 2189 => x"5182963f",
+ 2190 => x"80085580",
+ 2191 => x"08ff2e88",
+ 2192 => x"3874800c",
+ 2193 => x"873d0d04",
+ 2194 => x"80dd8008",
+ 2195 => x"5675802e",
+ 2196 => x"f0387776",
+ 2197 => x"710c5474",
+ 2198 => x"800c873d",
+ 2199 => x"0d04fe3d",
+ 2200 => x"0d80dcf8",
+ 2201 => x"0851708a",
+ 2202 => x"3880dd84",
+ 2203 => x"7080dcf8",
+ 2204 => x"0c517075",
+ 2205 => x"125252ff",
+ 2206 => x"537087fb",
+ 2207 => x"80802688",
+ 2208 => x"387080dc",
+ 2209 => x"f80c7153",
+ 2210 => x"72800c84",
+ 2211 => x"3d0d04fd",
+ 2212 => x"3d0d800b",
+ 2213 => x"80cd8008",
+ 2214 => x"54547281",
+ 2215 => x"2e9b3873",
+ 2216 => x"80dcfc0c",
+ 2217 => x"c4803fc2",
+ 2218 => x"d73f80dc",
+ 2219 => x"d0528151",
+ 2220 => x"c5c63f80",
+ 2221 => x"085185bb",
+ 2222 => x"3f7280dc",
+ 2223 => x"fc0cc3e6",
+ 2224 => x"3fc2bd3f",
+ 2225 => x"80dcd052",
+ 2226 => x"8151c5ac",
+ 2227 => x"3f800851",
+ 2228 => x"85a13f00",
+ 2229 => x"ff3900ff",
+ 2230 => x"39f53d0d",
+ 2231 => x"7e6080dc",
+ 2232 => x"fc08705b",
+ 2233 => x"585b5b75",
+ 2234 => x"80c23877",
+ 2235 => x"7a25a138",
+ 2236 => x"771b7033",
+ 2237 => x"7081ff06",
+ 2238 => x"58585975",
+ 2239 => x"8a2e9838",
+ 2240 => x"7681ff06",
+ 2241 => x"51c2fe3f",
+ 2242 => x"81185879",
+ 2243 => x"7824e138",
+ 2244 => x"79800c8d",
+ 2245 => x"3d0d048d",
+ 2246 => x"51c2ea3f",
+ 2247 => x"78337081",
+ 2248 => x"ff065257",
+ 2249 => x"c2df3f81",
+ 2250 => x"1858e039",
+ 2251 => x"79557a54",
+ 2252 => x"7d538552",
+ 2253 => x"8d3dfc05",
+ 2254 => x"51c2873f",
+ 2255 => x"80085684",
+ 2256 => x"ab3f7b80",
+ 2257 => x"080c7580",
+ 2258 => x"0c8d3d0d",
+ 2259 => x"04f63d0d",
+ 2260 => x"7d7f80dc",
+ 2261 => x"fc08705b",
+ 2262 => x"585a5a75",
+ 2263 => x"80c13877",
+ 2264 => x"7925b338",
+ 2265 => x"c1fa3f80",
+ 2266 => x"0881ff06",
+ 2267 => x"708d3270",
+ 2268 => x"30709f2a",
+ 2269 => x"51515757",
+ 2270 => x"768a2e80",
+ 2271 => x"c3387580",
+ 2272 => x"2ebe3877",
+ 2273 => x"1a567676",
+ 2274 => x"347651c1",
+ 2275 => x"f83f8118",
+ 2276 => x"58787824",
+ 2277 => x"cf387756",
+ 2278 => x"75800c8c",
+ 2279 => x"3d0d0478",
+ 2280 => x"5579547c",
+ 2281 => x"5384528c",
+ 2282 => x"3dfc0551",
+ 2283 => x"c1943f80",
+ 2284 => x"085683b8",
+ 2285 => x"3f7a8008",
+ 2286 => x"0c75800c",
+ 2287 => x"8c3d0d04",
+ 2288 => x"771a568a",
+ 2289 => x"76348118",
+ 2290 => x"588d51c1",
+ 2291 => x"b83f8a51",
+ 2292 => x"c1b33f77",
+ 2293 => x"56c239fb",
+ 2294 => x"3d0d80dc",
+ 2295 => x"fc087056",
+ 2296 => x"54738838",
+ 2297 => x"74800c87",
+ 2298 => x"3d0d0477",
+ 2299 => x"53835287",
+ 2300 => x"3dfc0551",
+ 2301 => x"c0cc3f80",
+ 2302 => x"085482f0",
+ 2303 => x"3f758008",
+ 2304 => x"0c73800c",
+ 2305 => x"873d0d04",
+ 2306 => x"fa3d0d80",
+ 2307 => x"dcfc0880",
+ 2308 => x"2ea2387a",
+ 2309 => x"55795478",
+ 2310 => x"53865288",
+ 2311 => x"3dfc0551",
+ 2312 => x"c0a03f80",
+ 2313 => x"085682c4",
+ 2314 => x"3f768008",
+ 2315 => x"0c75800c",
+ 2316 => x"883d0d04",
+ 2317 => x"82b63f9d",
+ 2318 => x"0b80080c",
+ 2319 => x"ff0b800c",
+ 2320 => x"883d0d04",
+ 2321 => x"fb3d0d77",
+ 2322 => x"79565680",
+ 2323 => x"70545473",
+ 2324 => x"75259f38",
+ 2325 => x"74101010",
+ 2326 => x"f8055272",
+ 2327 => x"16703370",
+ 2328 => x"742b7607",
+ 2329 => x"8116f816",
+ 2330 => x"56565651",
+ 2331 => x"51747324",
+ 2332 => x"ea387380",
+ 2333 => x"0c873d0d",
+ 2334 => x"04fc3d0d",
+ 2335 => x"76785555",
+ 2336 => x"bc538052",
+ 2337 => x"7351f5ca",
+ 2338 => x"3f845274",
+ 2339 => x"51ffb53f",
+ 2340 => x"80087423",
+ 2341 => x"84528415",
+ 2342 => x"51ffa93f",
+ 2343 => x"80088215",
+ 2344 => x"23845288",
+ 2345 => x"1551ff9c",
+ 2346 => x"3f800884",
+ 2347 => x"150c8452",
+ 2348 => x"8c1551ff",
+ 2349 => x"8f3f8008",
+ 2350 => x"88152384",
+ 2351 => x"52901551",
+ 2352 => x"ff823f80",
+ 2353 => x"088a1523",
+ 2354 => x"84529415",
+ 2355 => x"51fef53f",
+ 2356 => x"80088c15",
+ 2357 => x"23845298",
+ 2358 => x"1551fee8",
+ 2359 => x"3f80088e",
+ 2360 => x"15238852",
+ 2361 => x"9c1551fe",
+ 2362 => x"db3f8008",
+ 2363 => x"90150c86",
+ 2364 => x"3d0d04e9",
+ 2365 => x"3d0d6a80",
+ 2366 => x"dcfc0857",
+ 2367 => x"57759338",
+ 2368 => x"80c0800b",
+ 2369 => x"84180c75",
+ 2370 => x"ac180c75",
+ 2371 => x"800c993d",
+ 2372 => x"0d04893d",
+ 2373 => x"70556a54",
+ 2374 => x"558a5299",
+ 2375 => x"3dffbc05",
+ 2376 => x"51ffbe9e",
+ 2377 => x"3f800877",
+ 2378 => x"53755256",
+ 2379 => x"fecb3fbc",
+ 2380 => x"3f778008",
+ 2381 => x"0c75800c",
+ 2382 => x"993d0d04",
+ 2383 => x"fc3d0d81",
+ 2384 => x"5480dcfc",
+ 2385 => x"08883873",
+ 2386 => x"800c863d",
+ 2387 => x"0d047653",
+ 2388 => x"97b95286",
+ 2389 => x"3dfc0551",
+ 2390 => x"ffbde73f",
+ 2391 => x"8008548c",
+ 2392 => x"3f748008",
+ 2393 => x"0c73800c",
+ 2394 => x"863d0d04",
+ 2395 => x"80cd8c08",
+ 2396 => x"800c04f7",
+ 2397 => x"3d0d7b80",
+ 2398 => x"cd8c0882",
+ 2399 => x"c811085a",
+ 2400 => x"545a7780",
+ 2401 => x"2e80da38",
+ 2402 => x"81881884",
+ 2403 => x"1908ff05",
+ 2404 => x"81712b59",
+ 2405 => x"55598074",
+ 2406 => x"2480ea38",
+ 2407 => x"807424b5",
+ 2408 => x"3873822b",
+ 2409 => x"78118805",
+ 2410 => x"56568180",
+ 2411 => x"19087706",
+ 2412 => x"5372802e",
+ 2413 => x"b6387816",
+ 2414 => x"70085353",
+ 2415 => x"79517408",
+ 2416 => x"53722dff",
+ 2417 => x"14fc17fc",
+ 2418 => x"1779812c",
+ 2419 => x"5a575754",
+ 2420 => x"738025d6",
+ 2421 => x"38770858",
+ 2422 => x"77ffad38",
+ 2423 => x"80cd8c08",
+ 2424 => x"53bc1308",
+ 2425 => x"a5387951",
+ 2426 => x"f9e93f74",
+ 2427 => x"0853722d",
+ 2428 => x"ff14fc17",
+ 2429 => x"fc177981",
+ 2430 => x"2c5a5757",
+ 2431 => x"54738025",
+ 2432 => x"ffa838d1",
+ 2433 => x"398057ff",
+ 2434 => x"93397251",
+ 2435 => x"bc130853",
+ 2436 => x"722d7951",
+ 2437 => x"f9bd3fff",
+ 2438 => x"3d0d80dc",
+ 2439 => x"d80bfc05",
+ 2440 => x"70085252",
+ 2441 => x"70ff2e91",
+ 2442 => x"38702dfc",
+ 2443 => x"12700852",
+ 2444 => x"5270ff2e",
+ 2445 => x"098106f1",
+ 2446 => x"38833d0d",
+ 2447 => x"0404ffbd",
+ 2448 => x"d23f0400",
+ 2449 => x"00000040",
+ 2450 => x"48656c6c",
+ 2451 => x"6f20776f",
+ 2452 => x"726c6421",
+ 2453 => x"00000000",
+ 2454 => x"0a000000",
+ 2455 => x"43000000",
+ 2456 => x"64756d6d",
+ 2457 => x"792e6578",
+ 2458 => x"65000000",
+ 2459 => x"00ffffff",
+ 2460 => x"ff00ffff",
+ 2461 => x"ffff00ff",
+ 2462 => x"ffffff00",
+ 2463 => x"00000000",
+ 2464 => x"00000000",
+ 2465 => x"00000000",
+ 2466 => x"00002e60",
+ 2467 => x"00002690",
+ 2468 => x"00000000",
+ 2469 => x"000028f8",
+ 2470 => x"00002954",
+ 2471 => x"000029b0",
+ 2472 => x"00000000",
+ 2473 => x"00000000",
+ 2474 => x"00000000",
+ 2475 => x"00000000",
+ 2476 => x"00000000",
+ 2477 => x"00000000",
+ 2478 => x"00000000",
+ 2479 => x"00000000",
+ 2480 => x"00000000",
+ 2481 => x"0000265c",
+ 2482 => x"00000000",
+ 2483 => x"00000000",
+ 2484 => x"00000000",
+ 2485 => x"00000000",
+ 2486 => x"00000000",
+ 2487 => x"00000000",
+ 2488 => x"00000000",
+ 2489 => x"00000000",
+ 2490 => x"00000000",
+ 2491 => x"00000000",
+ 2492 => x"00000000",
+ 2493 => x"00000000",
+ 2494 => x"00000000",
+ 2495 => x"00000000",
+ 2496 => x"00000000",
+ 2497 => x"00000000",
+ 2498 => x"00000000",
+ 2499 => x"00000000",
+ 2500 => x"00000000",
+ 2501 => x"00000000",
+ 2502 => x"00000000",
+ 2503 => x"00000000",
+ 2504 => x"00000000",
+ 2505 => x"00000000",
+ 2506 => x"00000000",
+ 2507 => x"00000000",
+ 2508 => x"00000000",
+ 2509 => x"00000000",
+ 2510 => x"00000001",
+ 2511 => x"330eabcd",
+ 2512 => x"1234e66d",
+ 2513 => x"deec0005",
+ 2514 => x"000b0000",
+ 2515 => x"00000000",
+ 2516 => x"00000000",
+ 2517 => x"00000000",
+ 2518 => x"00000000",
+ 2519 => x"00000000",
+ 2520 => x"00000000",
+ 2521 => x"00000000",
+ 2522 => x"00000000",
+ 2523 => x"00000000",
+ 2524 => x"00000000",
+ 2525 => x"00000000",
+ 2526 => x"00000000",
+ 2527 => x"00000000",
+ 2528 => x"00000000",
+ 2529 => x"00000000",
+ 2530 => x"00000000",
+ 2531 => x"00000000",
+ 2532 => x"00000000",
+ 2533 => x"00000000",
+ 2534 => x"00000000",
+ 2535 => x"00000000",
+ 2536 => x"00000000",
+ 2537 => x"00000000",
+ 2538 => x"00000000",
+ 2539 => x"00000000",
+ 2540 => x"00000000",
+ 2541 => x"00000000",
+ 2542 => x"00000000",
+ 2543 => x"00000000",
+ 2544 => x"00000000",
+ 2545 => x"00000000",
+ 2546 => x"00000000",
+ 2547 => x"00000000",
+ 2548 => x"00000000",
+ 2549 => x"00000000",
+ 2550 => x"00000000",
+ 2551 => x"00000000",
+ 2552 => x"00000000",
+ 2553 => x"00000000",
+ 2554 => x"00000000",
+ 2555 => x"00000000",
+ 2556 => x"00000000",
+ 2557 => x"00000000",
+ 2558 => x"00000000",
+ 2559 => x"00000000",
+ 2560 => x"00000000",
+ 2561 => x"00000000",
+ 2562 => x"00000000",
+ 2563 => x"00000000",
+ 2564 => x"00000000",
+ 2565 => x"00000000",
+ 2566 => x"00000000",
+ 2567 => x"00000000",
+ 2568 => x"00000000",
+ 2569 => x"00000000",
+ 2570 => x"00000000",
+ 2571 => x"00000000",
+ 2572 => x"00000000",
+ 2573 => x"00000000",
+ 2574 => x"00000000",
+ 2575 => x"00000000",
+ 2576 => x"00000000",
+ 2577 => x"00000000",
+ 2578 => x"00000000",
+ 2579 => x"00000000",
+ 2580 => x"00000000",
+ 2581 => x"00000000",
+ 2582 => x"00000000",
+ 2583 => x"00000000",
+ 2584 => x"00000000",
+ 2585 => x"00000000",
+ 2586 => x"00000000",
+ 2587 => x"00000000",
+ 2588 => x"00000000",
+ 2589 => x"00000000",
+ 2590 => x"00000000",
+ 2591 => x"00000000",
+ 2592 => x"00000000",
+ 2593 => x"00000000",
+ 2594 => x"00000000",
+ 2595 => x"00000000",
+ 2596 => x"00000000",
+ 2597 => x"00000000",
+ 2598 => x"00000000",
+ 2599 => x"00000000",
+ 2600 => x"00000000",
+ 2601 => x"00000000",
+ 2602 => x"00000000",
+ 2603 => x"00000000",
+ 2604 => x"00000000",
+ 2605 => x"00000000",
+ 2606 => x"00000000",
+ 2607 => x"00000000",
+ 2608 => x"00000000",
+ 2609 => x"00000000",
+ 2610 => x"00000000",
+ 2611 => x"00000000",
+ 2612 => x"00000000",
+ 2613 => x"00000000",
+ 2614 => x"00000000",
+ 2615 => x"00000000",
+ 2616 => x"00000000",
+ 2617 => x"00000000",
+ 2618 => x"00000000",
+ 2619 => x"00000000",
+ 2620 => x"00000000",
+ 2621 => x"00000000",
+ 2622 => x"00000000",
+ 2623 => x"00000000",
+ 2624 => x"00000000",
+ 2625 => x"00000000",
+ 2626 => x"00000000",
+ 2627 => x"00000000",
+ 2628 => x"00000000",
+ 2629 => x"00000000",
+ 2630 => x"00000000",
+ 2631 => x"00000000",
+ 2632 => x"00000000",
+ 2633 => x"00000000",
+ 2634 => x"00000000",
+ 2635 => x"00000000",
+ 2636 => x"00000000",
+ 2637 => x"00000000",
+ 2638 => x"00000000",
+ 2639 => x"00000000",
+ 2640 => x"00000000",
+ 2641 => x"00000000",
+ 2642 => x"00000000",
+ 2643 => x"00000000",
+ 2644 => x"00000000",
+ 2645 => x"00000000",
+ 2646 => x"00000000",
+ 2647 => x"00000000",
+ 2648 => x"00000000",
+ 2649 => x"00000000",
+ 2650 => x"00000000",
+ 2651 => x"00000000",
+ 2652 => x"00000000",
+ 2653 => x"00000000",
+ 2654 => x"00000000",
+ 2655 => x"00000000",
+ 2656 => x"00000000",
+ 2657 => x"00000000",
+ 2658 => x"00000000",
+ 2659 => x"00000000",
+ 2660 => x"00000000",
+ 2661 => x"00000000",
+ 2662 => x"00000000",
+ 2663 => x"00000000",
+ 2664 => x"00000000",
+ 2665 => x"00000000",
+ 2666 => x"00000000",
+ 2667 => x"00000000",
+ 2668 => x"00000000",
+ 2669 => x"00000000",
+ 2670 => x"00000000",
+ 2671 => x"00000000",
+ 2672 => x"00000000",
+ 2673 => x"00000000",
+ 2674 => x"00000000",
+ 2675 => x"00000000",
+ 2676 => x"00000000",
+ 2677 => x"00000000",
+ 2678 => x"00000000",
+ 2679 => x"00000000",
+ 2680 => x"00000000",
+ 2681 => x"00000000",
+ 2682 => x"00000000",
+ 2683 => x"00000000",
+ 2684 => x"00000000",
+ 2685 => x"00000000",
+ 2686 => x"00000000",
+ 2687 => x"00000000",
+ 2688 => x"00000000",
+ 2689 => x"00000000",
+ 2690 => x"00000000",
+ 2691 => x"00000000",
+ 2692 => x"00000000",
+ 2693 => x"00000000",
+ 2694 => x"00000000",
+ 2695 => x"00000000",
+ 2696 => x"00000000",
+ 2697 => x"00000000",
+ 2698 => x"00000000",
+ 2699 => x"00000000",
+ 2700 => x"00000000",
+ 2701 => x"00000000",
+ 2702 => x"00000000",
+ 2703 => x"ffffffff",
+ 2704 => x"00000000",
+ 2705 => x"00020000",
+ 2706 => x"00000000",
+ 2707 => x"00000000",
+ 2708 => x"00002a48",
+ 2709 => x"00002a48",
+ 2710 => x"00002a50",
+ 2711 => x"00002a50",
+ 2712 => x"00002a58",
+ 2713 => x"00002a58",
+ 2714 => x"00002a60",
+ 2715 => x"00002a60",
+ 2716 => x"00002a68",
+ 2717 => x"00002a68",
+ 2718 => x"00002a70",
+ 2719 => x"00002a70",
+ 2720 => x"00002a78",
+ 2721 => x"00002a78",
+ 2722 => x"00002a80",
+ 2723 => x"00002a80",
+ 2724 => x"00002a88",
+ 2725 => x"00002a88",
+ 2726 => x"00002a90",
+ 2727 => x"00002a90",
+ 2728 => x"00002a98",
+ 2729 => x"00002a98",
+ 2730 => x"00002aa0",
+ 2731 => x"00002aa0",
+ 2732 => x"00002aa8",
+ 2733 => x"00002aa8",
+ 2734 => x"00002ab0",
+ 2735 => x"00002ab0",
+ 2736 => x"00002ab8",
+ 2737 => x"00002ab8",
+ 2738 => x"00002ac0",
+ 2739 => x"00002ac0",
+ 2740 => x"00002ac8",
+ 2741 => x"00002ac8",
+ 2742 => x"00002ad0",
+ 2743 => x"00002ad0",
+ 2744 => x"00002ad8",
+ 2745 => x"00002ad8",
+ 2746 => x"00002ae0",
+ 2747 => x"00002ae0",
+ 2748 => x"00002ae8",
+ 2749 => x"00002ae8",
+ 2750 => x"00002af0",
+ 2751 => x"00002af0",
+ 2752 => x"00002af8",
+ 2753 => x"00002af8",
+ 2754 => x"00002b00",
+ 2755 => x"00002b00",
+ 2756 => x"00002b08",
+ 2757 => x"00002b08",
+ 2758 => x"00002b10",
+ 2759 => x"00002b10",
+ 2760 => x"00002b18",
+ 2761 => x"00002b18",
+ 2762 => x"00002b20",
+ 2763 => x"00002b20",
+ 2764 => x"00002b28",
+ 2765 => x"00002b28",
+ 2766 => x"00002b30",
+ 2767 => x"00002b30",
+ 2768 => x"00002b38",
+ 2769 => x"00002b38",
+ 2770 => x"00002b40",
+ 2771 => x"00002b40",
+ 2772 => x"00002b48",
+ 2773 => x"00002b48",
+ 2774 => x"00002b50",
+ 2775 => x"00002b50",
+ 2776 => x"00002b58",
+ 2777 => x"00002b58",
+ 2778 => x"00002b60",
+ 2779 => x"00002b60",
+ 2780 => x"00002b68",
+ 2781 => x"00002b68",
+ 2782 => x"00002b70",
+ 2783 => x"00002b70",
+ 2784 => x"00002b78",
+ 2785 => x"00002b78",
+ 2786 => x"00002b80",
+ 2787 => x"00002b80",
+ 2788 => x"00002b88",
+ 2789 => x"00002b88",
+ 2790 => x"00002b90",
+ 2791 => x"00002b90",
+ 2792 => x"00002b98",
+ 2793 => x"00002b98",
+ 2794 => x"00002ba0",
+ 2795 => x"00002ba0",
+ 2796 => x"00002ba8",
+ 2797 => x"00002ba8",
+ 2798 => x"00002bb0",
+ 2799 => x"00002bb0",
+ 2800 => x"00002bb8",
+ 2801 => x"00002bb8",
+ 2802 => x"00002bc0",
+ 2803 => x"00002bc0",
+ 2804 => x"00002bc8",
+ 2805 => x"00002bc8",
+ 2806 => x"00002bd0",
+ 2807 => x"00002bd0",
+ 2808 => x"00002bd8",
+ 2809 => x"00002bd8",
+ 2810 => x"00002be0",
+ 2811 => x"00002be0",
+ 2812 => x"00002be8",
+ 2813 => x"00002be8",
+ 2814 => x"00002bf0",
+ 2815 => x"00002bf0",
+ 2816 => x"00002bf8",
+ 2817 => x"00002bf8",
+ 2818 => x"00002c00",
+ 2819 => x"00002c00",
+ 2820 => x"00002c08",
+ 2821 => x"00002c08",
+ 2822 => x"00002c10",
+ 2823 => x"00002c10",
+ 2824 => x"00002c18",
+ 2825 => x"00002c18",
+ 2826 => x"00002c20",
+ 2827 => x"00002c20",
+ 2828 => x"00002c28",
+ 2829 => x"00002c28",
+ 2830 => x"00002c30",
+ 2831 => x"00002c30",
+ 2832 => x"00002c38",
+ 2833 => x"00002c38",
+ 2834 => x"00002c40",
+ 2835 => x"00002c40",
+ 2836 => x"00002c48",
+ 2837 => x"00002c48",
+ 2838 => x"00002c50",
+ 2839 => x"00002c50",
+ 2840 => x"00002c58",
+ 2841 => x"00002c58",
+ 2842 => x"00002c60",
+ 2843 => x"00002c60",
+ 2844 => x"00002c68",
+ 2845 => x"00002c68",
+ 2846 => x"00002c70",
+ 2847 => x"00002c70",
+ 2848 => x"00002c78",
+ 2849 => x"00002c78",
+ 2850 => x"00002c80",
+ 2851 => x"00002c80",
+ 2852 => x"00002c88",
+ 2853 => x"00002c88",
+ 2854 => x"00002c90",
+ 2855 => x"00002c90",
+ 2856 => x"00002c98",
+ 2857 => x"00002c98",
+ 2858 => x"00002ca0",
+ 2859 => x"00002ca0",
+ 2860 => x"00002ca8",
+ 2861 => x"00002ca8",
+ 2862 => x"00002cb0",
+ 2863 => x"00002cb0",
+ 2864 => x"00002cb8",
+ 2865 => x"00002cb8",
+ 2866 => x"00002cc0",
+ 2867 => x"00002cc0",
+ 2868 => x"00002cc8",
+ 2869 => x"00002cc8",
+ 2870 => x"00002cd0",
+ 2871 => x"00002cd0",
+ 2872 => x"00002cd8",
+ 2873 => x"00002cd8",
+ 2874 => x"00002ce0",
+ 2875 => x"00002ce0",
+ 2876 => x"00002ce8",
+ 2877 => x"00002ce8",
+ 2878 => x"00002cf0",
+ 2879 => x"00002cf0",
+ 2880 => x"00002cf8",
+ 2881 => x"00002cf8",
+ 2882 => x"00002d00",
+ 2883 => x"00002d00",
+ 2884 => x"00002d08",
+ 2885 => x"00002d08",
+ 2886 => x"00002d10",
+ 2887 => x"00002d10",
+ 2888 => x"00002d18",
+ 2889 => x"00002d18",
+ 2890 => x"00002d20",
+ 2891 => x"00002d20",
+ 2892 => x"00002d28",
+ 2893 => x"00002d28",
+ 2894 => x"00002d30",
+ 2895 => x"00002d30",
+ 2896 => x"00002d38",
+ 2897 => x"00002d38",
+ 2898 => x"00002d40",
+ 2899 => x"00002d40",
+ 2900 => x"00002d48",
+ 2901 => x"00002d48",
+ 2902 => x"00002d50",
+ 2903 => x"00002d50",
+ 2904 => x"00002d58",
+ 2905 => x"00002d58",
+ 2906 => x"00002d60",
+ 2907 => x"00002d60",
+ 2908 => x"00002d68",
+ 2909 => x"00002d68",
+ 2910 => x"00002d70",
+ 2911 => x"00002d70",
+ 2912 => x"00002d78",
+ 2913 => x"00002d78",
+ 2914 => x"00002d80",
+ 2915 => x"00002d80",
+ 2916 => x"00002d88",
+ 2917 => x"00002d88",
+ 2918 => x"00002d90",
+ 2919 => x"00002d90",
+ 2920 => x"00002d98",
+ 2921 => x"00002d98",
+ 2922 => x"00002da0",
+ 2923 => x"00002da0",
+ 2924 => x"00002da8",
+ 2925 => x"00002da8",
+ 2926 => x"00002db0",
+ 2927 => x"00002db0",
+ 2928 => x"00002db8",
+ 2929 => x"00002db8",
+ 2930 => x"00002dc0",
+ 2931 => x"00002dc0",
+ 2932 => x"00002dc8",
+ 2933 => x"00002dc8",
+ 2934 => x"00002dd0",
+ 2935 => x"00002dd0",
+ 2936 => x"00002dd8",
+ 2937 => x"00002dd8",
+ 2938 => x"00002de0",
+ 2939 => x"00002de0",
+ 2940 => x"00002de8",
+ 2941 => x"00002de8",
+ 2942 => x"00002df0",
+ 2943 => x"00002df0",
+ 2944 => x"00002df8",
+ 2945 => x"00002df8",
+ 2946 => x"00002e00",
+ 2947 => x"00002e00",
+ 2948 => x"00002e08",
+ 2949 => x"00002e08",
+ 2950 => x"00002e10",
+ 2951 => x"00002e10",
+ 2952 => x"00002e18",
+ 2953 => x"00002e18",
+ 2954 => x"00002e20",
+ 2955 => x"00002e20",
+ 2956 => x"00002e28",
+ 2957 => x"00002e28",
+ 2958 => x"00002e30",
+ 2959 => x"00002e30",
+ 2960 => x"00002e38",
+ 2961 => x"00002e38",
+ 2962 => x"00002e40",
+ 2963 => x"00002e40",
+ 2964 => x"00002660",
+ 2965 => x"ffffffff",
+ 2966 => x"00000000",
+ 2967 => x"ffffffff",
+ 2968 => x"00000000",
+ 2969 => x"00000000",
+
+others => x"00000000"
+);
+begin
+ busy_o <= re_i; -- we're done on the cycle after we serve the read request
+
+ do_ram:
+ process (clk_i)
+ variable iaddr : integer;
+ begin
+ if rising_edge(clk_i) then
+ if we_i='1' then
+ ram(to_integer(addr_i)) <= write_i;
+ end if;
+ addr_r <= addr_i;
+ end if;
+ end process do_ram;
+ read_o <= ram(to_integer(addr_r));
+end architecture Xilinx; -- Entity: SinglePortRAM
+
diff --git a/zpu/hdl/zealot/roms/hello_dbram.vhdl b/zpu/hdl/zealot/roms/hello_dbram.vhdl
new file mode 100644
index 0000000..28cac6f
--- /dev/null
+++ b/zpu/hdl/zealot/roms/hello_dbram.vhdl
@@ -0,0 +1,3035 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity DualPortRAM is
+ generic(
+ WORD_SIZE : integer:=32; -- Word Size 16/32
+ BYTE_BITS : integer:=2; -- Bits used to address bytes
+ BRAM_W : integer:=15); -- Address Width
+ port(
+ clk_i : in std_logic;
+ -- Port A
+ a_we_i : in std_logic;
+ a_addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS);
+ a_write_i : in unsigned(WORD_SIZE-1 downto 0);
+ a_read_o : out unsigned(WORD_SIZE-1 downto 0);
+ -- Port B
+ b_we_i : in std_logic;
+ b_addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS);
+ b_write_i : in unsigned(WORD_SIZE-1 downto 0);
+ b_read_o : out unsigned(WORD_SIZE-1 downto 0));
+end entity DualPortRAM;
+
+architecture DualPort_Arch of DualPortRAM is
+ type ram_type is array(natural range 0 to ((2**BRAM_W)/4)-1) of unsigned(WORD_SIZE-1 downto 0);
+
+ shared variable ram : ram_type:=
+(
+ 0 => x"0b0b0b0b",
+ 1 => x"82700b0b",
+ 2 => x"80cd800c",
+ 3 => x"3a0b0b80",
+ 4 => x"c58f0400",
+ 5 => x"00000000",
+ 6 => x"00000000",
+ 7 => x"00000000",
+ 8 => x"80088408",
+ 9 => x"88080b0b",
+ 10 => x"80c5d62d",
+ 11 => x"880c840c",
+ 12 => x"800c0400",
+ 13 => x"00000000",
+ 14 => x"00000000",
+ 15 => x"00000000",
+ 16 => x"71fd0608",
+ 17 => x"72830609",
+ 18 => x"81058205",
+ 19 => x"832b2a83",
+ 20 => x"ffff0652",
+ 21 => x"04000000",
+ 22 => x"00000000",
+ 23 => x"00000000",
+ 24 => x"71fd0608",
+ 25 => x"83ffff73",
+ 26 => x"83060981",
+ 27 => x"05820583",
+ 28 => x"2b2b0906",
+ 29 => x"7383ffff",
+ 30 => x"0b0b0b0b",
+ 31 => x"83a70400",
+ 32 => x"72098105",
+ 33 => x"72057373",
+ 34 => x"09060906",
+ 35 => x"73097306",
+ 36 => x"070a8106",
+ 37 => x"53510400",
+ 38 => x"00000000",
+ 39 => x"00000000",
+ 40 => x"72722473",
+ 41 => x"732e0753",
+ 42 => x"51040000",
+ 43 => x"00000000",
+ 44 => x"00000000",
+ 45 => x"00000000",
+ 46 => x"00000000",
+ 47 => x"00000000",
+ 48 => x"71737109",
+ 49 => x"71068106",
+ 50 => x"30720a10",
+ 51 => x"0a720a10",
+ 52 => x"0a31050a",
+ 53 => x"81065151",
+ 54 => x"53510400",
+ 55 => x"00000000",
+ 56 => x"72722673",
+ 57 => x"732e0753",
+ 58 => x"51040000",
+ 59 => x"00000000",
+ 60 => x"00000000",
+ 61 => x"00000000",
+ 62 => x"00000000",
+ 63 => x"00000000",
+ 64 => x"00000000",
+ 65 => x"00000000",
+ 66 => x"00000000",
+ 67 => x"00000000",
+ 68 => x"00000000",
+ 69 => x"00000000",
+ 70 => x"00000000",
+ 71 => x"00000000",
+ 72 => x"0b0b0b88",
+ 73 => x"c4040000",
+ 74 => x"00000000",
+ 75 => x"00000000",
+ 76 => x"00000000",
+ 77 => x"00000000",
+ 78 => x"00000000",
+ 79 => x"00000000",
+ 80 => x"720a722b",
+ 81 => x"0a535104",
+ 82 => x"00000000",
+ 83 => x"00000000",
+ 84 => x"00000000",
+ 85 => x"00000000",
+ 86 => x"00000000",
+ 87 => x"00000000",
+ 88 => x"72729f06",
+ 89 => x"0981050b",
+ 90 => x"0b0b88a7",
+ 91 => x"05040000",
+ 92 => x"00000000",
+ 93 => x"00000000",
+ 94 => x"00000000",
+ 95 => x"00000000",
+ 96 => x"72722aff",
+ 97 => x"739f062a",
+ 98 => x"0974090a",
+ 99 => x"8106ff05",
+ 100 => x"06075351",
+ 101 => x"04000000",
+ 102 => x"00000000",
+ 103 => x"00000000",
+ 104 => x"71715351",
+ 105 => x"020d0406",
+ 106 => x"73830609",
+ 107 => x"81058205",
+ 108 => x"832b0b2b",
+ 109 => x"0772fc06",
+ 110 => x"0c515104",
+ 111 => x"00000000",
+ 112 => x"72098105",
+ 113 => x"72050970",
+ 114 => x"81050906",
+ 115 => x"0a810653",
+ 116 => x"51040000",
+ 117 => x"00000000",
+ 118 => x"00000000",
+ 119 => x"00000000",
+ 120 => x"72098105",
+ 121 => x"72050970",
+ 122 => x"81050906",
+ 123 => x"0a098106",
+ 124 => x"53510400",
+ 125 => x"00000000",
+ 126 => x"00000000",
+ 127 => x"00000000",
+ 128 => x"71098105",
+ 129 => x"52040000",
+ 130 => x"00000000",
+ 131 => x"00000000",
+ 132 => x"00000000",
+ 133 => x"00000000",
+ 134 => x"00000000",
+ 135 => x"00000000",
+ 136 => x"72720981",
+ 137 => x"05055351",
+ 138 => x"04000000",
+ 139 => x"00000000",
+ 140 => x"00000000",
+ 141 => x"00000000",
+ 142 => x"00000000",
+ 143 => x"00000000",
+ 144 => x"72097206",
+ 145 => x"73730906",
+ 146 => x"07535104",
+ 147 => x"00000000",
+ 148 => x"00000000",
+ 149 => x"00000000",
+ 150 => x"00000000",
+ 151 => x"00000000",
+ 152 => x"71fc0608",
+ 153 => x"72830609",
+ 154 => x"81058305",
+ 155 => x"1010102a",
+ 156 => x"81ff0652",
+ 157 => x"04000000",
+ 158 => x"00000000",
+ 159 => x"00000000",
+ 160 => x"71fc0608",
+ 161 => x"0b0b80cc",
+ 162 => x"ec738306",
+ 163 => x"10100508",
+ 164 => x"060b0b0b",
+ 165 => x"88aa0400",
+ 166 => x"00000000",
+ 167 => x"00000000",
+ 168 => x"80088408",
+ 169 => x"88087575",
+ 170 => x"0b0b0b8b",
+ 171 => x"8a2d5050",
+ 172 => x"80085688",
+ 173 => x"0c840c80",
+ 174 => x"0c510400",
+ 175 => x"00000000",
+ 176 => x"80088408",
+ 177 => x"88087575",
+ 178 => x"0b0b0b8c",
+ 179 => x"bc2d5050",
+ 180 => x"80085688",
+ 181 => x"0c840c80",
+ 182 => x"0c510400",
+ 183 => x"00000000",
+ 184 => x"72097081",
+ 185 => x"0509060a",
+ 186 => x"8106ff05",
+ 187 => x"70547106",
+ 188 => x"73097274",
+ 189 => x"05ff0506",
+ 190 => x"07515151",
+ 191 => x"04000000",
+ 192 => x"72097081",
+ 193 => x"0509060a",
+ 194 => x"098106ff",
+ 195 => x"05705471",
+ 196 => x"06730972",
+ 197 => x"7405ff05",
+ 198 => x"06075151",
+ 199 => x"51040000",
+ 200 => x"05ff0504",
+ 201 => x"00000000",
+ 202 => x"00000000",
+ 203 => x"00000000",
+ 204 => x"00000000",
+ 205 => x"00000000",
+ 206 => x"00000000",
+ 207 => x"00000000",
+ 208 => x"810b0b0b",
+ 209 => x"80ccfc0c",
+ 210 => x"51040000",
+ 211 => x"00000000",
+ 212 => x"00000000",
+ 213 => x"00000000",
+ 214 => x"00000000",
+ 215 => x"00000000",
+ 216 => x"71810552",
+ 217 => x"04000000",
+ 218 => x"00000000",
+ 219 => x"00000000",
+ 220 => x"00000000",
+ 221 => x"00000000",
+ 222 => x"00000000",
+ 223 => x"00000000",
+ 224 => x"00000000",
+ 225 => x"00000000",
+ 226 => x"00000000",
+ 227 => x"00000000",
+ 228 => x"00000000",
+ 229 => x"00000000",
+ 230 => x"00000000",
+ 231 => x"00000000",
+ 232 => x"02840572",
+ 233 => x"10100552",
+ 234 => x"04000000",
+ 235 => x"00000000",
+ 236 => x"00000000",
+ 237 => x"00000000",
+ 238 => x"00000000",
+ 239 => x"00000000",
+ 240 => x"00000000",
+ 241 => x"00000000",
+ 242 => x"00000000",
+ 243 => x"00000000",
+ 244 => x"00000000",
+ 245 => x"00000000",
+ 246 => x"00000000",
+ 247 => x"00000000",
+ 248 => x"717105ff",
+ 249 => x"05715351",
+ 250 => x"020d0400",
+ 251 => x"00000000",
+ 252 => x"00000000",
+ 253 => x"00000000",
+ 254 => x"00000000",
+ 255 => x"00000000",
+ 256 => x"82c73f80",
+ 257 => x"c4913f04",
+ 258 => x"10101010",
+ 259 => x"10101010",
+ 260 => x"10101010",
+ 261 => x"10101010",
+ 262 => x"10101010",
+ 263 => x"10101010",
+ 264 => x"10101010",
+ 265 => x"10101053",
+ 266 => x"51047381",
+ 267 => x"ff067383",
+ 268 => x"06098105",
+ 269 => x"83051010",
+ 270 => x"102b0772",
+ 271 => x"fc060c51",
+ 272 => x"51043c04",
+ 273 => x"72728072",
+ 274 => x"8106ff05",
+ 275 => x"09720605",
+ 276 => x"71105272",
+ 277 => x"0a100a53",
+ 278 => x"72ed3851",
+ 279 => x"51535104",
+ 280 => x"fe3d0d0b",
+ 281 => x"0b80dce8",
+ 282 => x"08538413",
+ 283 => x"0870882a",
+ 284 => x"70810651",
+ 285 => x"52527080",
+ 286 => x"2ef03871",
+ 287 => x"81ff0680",
+ 288 => x"0c843d0d",
+ 289 => x"04ff3d0d",
+ 290 => x"0b0b80dc",
+ 291 => x"e8085271",
+ 292 => x"0870882a",
+ 293 => x"81327081",
+ 294 => x"06515151",
+ 295 => x"70f13873",
+ 296 => x"720c833d",
+ 297 => x"0d0480cc",
+ 298 => x"fc08802e",
+ 299 => x"a43880cd",
+ 300 => x"8008822e",
+ 301 => x"bd388380",
+ 302 => x"800b0b0b",
+ 303 => x"80dce80c",
+ 304 => x"82a0800b",
+ 305 => x"80dcec0c",
+ 306 => x"8290800b",
+ 307 => x"80dcf00c",
+ 308 => x"04f88080",
+ 309 => x"80a40b0b",
+ 310 => x"0b80dce8",
+ 311 => x"0cf88080",
+ 312 => x"82800b80",
+ 313 => x"dcec0cf8",
+ 314 => x"80808480",
+ 315 => x"0b80dcf0",
+ 316 => x"0c0480c0",
+ 317 => x"a8808c0b",
+ 318 => x"0b0b80dc",
+ 319 => x"e80c80c0",
+ 320 => x"a880940b",
+ 321 => x"80dcec0c",
+ 322 => x"0b0b80cc",
+ 323 => x"c40b80dc",
+ 324 => x"f00c04ff",
+ 325 => x"3d0d80dc",
+ 326 => x"f4335170",
+ 327 => x"a73880cd",
+ 328 => x"88087008",
+ 329 => x"52527080",
+ 330 => x"2e943884",
+ 331 => x"1280cd88",
+ 332 => x"0c702d80",
+ 333 => x"cd880870",
+ 334 => x"08525270",
+ 335 => x"ee38810b",
+ 336 => x"80dcf434",
+ 337 => x"833d0d04",
+ 338 => x"04803d0d",
+ 339 => x"0b0b80dc",
+ 340 => x"e408802e",
+ 341 => x"8e380b0b",
+ 342 => x"0b0b800b",
+ 343 => x"802e0981",
+ 344 => x"06853882",
+ 345 => x"3d0d040b",
+ 346 => x"0b80dce4",
+ 347 => x"510b0b0b",
+ 348 => x"f58e3f82",
+ 349 => x"3d0d0404",
+ 350 => x"803d0d80",
+ 351 => x"ccc85185",
+ 352 => x"de3f800b",
+ 353 => x"800c823d",
+ 354 => x"0d048c08",
+ 355 => x"028c0cf9",
+ 356 => x"3d0d800b",
+ 357 => x"8c08fc05",
+ 358 => x"0c8c0888",
+ 359 => x"05088025",
+ 360 => x"ab388c08",
+ 361 => x"88050830",
+ 362 => x"8c088805",
+ 363 => x"0c800b8c",
+ 364 => x"08f4050c",
+ 365 => x"8c08fc05",
+ 366 => x"08883881",
+ 367 => x"0b8c08f4",
+ 368 => x"050c8c08",
+ 369 => x"f405088c",
+ 370 => x"08fc050c",
+ 371 => x"8c088c05",
+ 372 => x"088025ab",
+ 373 => x"388c088c",
+ 374 => x"0508308c",
+ 375 => x"088c050c",
+ 376 => x"800b8c08",
+ 377 => x"f0050c8c",
+ 378 => x"08fc0508",
+ 379 => x"8838810b",
+ 380 => x"8c08f005",
+ 381 => x"0c8c08f0",
+ 382 => x"05088c08",
+ 383 => x"fc050c80",
+ 384 => x"538c088c",
+ 385 => x"0508528c",
+ 386 => x"08880508",
+ 387 => x"5181a73f",
+ 388 => x"8008708c",
+ 389 => x"08f8050c",
+ 390 => x"548c08fc",
+ 391 => x"0508802e",
+ 392 => x"8c388c08",
+ 393 => x"f8050830",
+ 394 => x"8c08f805",
+ 395 => x"0c8c08f8",
+ 396 => x"05087080",
+ 397 => x"0c54893d",
+ 398 => x"0d8c0c04",
+ 399 => x"8c08028c",
+ 400 => x"0cfb3d0d",
+ 401 => x"800b8c08",
+ 402 => x"fc050c8c",
+ 403 => x"08880508",
+ 404 => x"80259338",
+ 405 => x"8c088805",
+ 406 => x"08308c08",
+ 407 => x"88050c81",
+ 408 => x"0b8c08fc",
+ 409 => x"050c8c08",
+ 410 => x"8c050880",
+ 411 => x"258c388c",
+ 412 => x"088c0508",
+ 413 => x"308c088c",
+ 414 => x"050c8153",
+ 415 => x"8c088c05",
+ 416 => x"08528c08",
+ 417 => x"88050851",
+ 418 => x"ad3f8008",
+ 419 => x"708c08f8",
+ 420 => x"050c548c",
+ 421 => x"08fc0508",
+ 422 => x"802e8c38",
+ 423 => x"8c08f805",
+ 424 => x"08308c08",
+ 425 => x"f8050c8c",
+ 426 => x"08f80508",
+ 427 => x"70800c54",
+ 428 => x"873d0d8c",
+ 429 => x"0c048c08",
+ 430 => x"028c0cfd",
+ 431 => x"3d0d810b",
+ 432 => x"8c08fc05",
+ 433 => x"0c800b8c",
+ 434 => x"08f8050c",
+ 435 => x"8c088c05",
+ 436 => x"088c0888",
+ 437 => x"050827ac",
+ 438 => x"388c08fc",
+ 439 => x"0508802e",
+ 440 => x"a338800b",
+ 441 => x"8c088c05",
+ 442 => x"08249938",
+ 443 => x"8c088c05",
+ 444 => x"08108c08",
+ 445 => x"8c050c8c",
+ 446 => x"08fc0508",
+ 447 => x"108c08fc",
+ 448 => x"050cc939",
+ 449 => x"8c08fc05",
+ 450 => x"08802e80",
+ 451 => x"c9388c08",
+ 452 => x"8c05088c",
+ 453 => x"08880508",
+ 454 => x"26a1388c",
+ 455 => x"08880508",
+ 456 => x"8c088c05",
+ 457 => x"08318c08",
+ 458 => x"88050c8c",
+ 459 => x"08f80508",
+ 460 => x"8c08fc05",
+ 461 => x"08078c08",
+ 462 => x"f8050c8c",
+ 463 => x"08fc0508",
+ 464 => x"812a8c08",
+ 465 => x"fc050c8c",
+ 466 => x"088c0508",
+ 467 => x"812a8c08",
+ 468 => x"8c050cff",
+ 469 => x"af398c08",
+ 470 => x"90050880",
+ 471 => x"2e8f388c",
+ 472 => x"08880508",
+ 473 => x"708c08f4",
+ 474 => x"050c518d",
+ 475 => x"398c08f8",
+ 476 => x"0508708c",
+ 477 => x"08f4050c",
+ 478 => x"518c08f4",
+ 479 => x"0508800c",
+ 480 => x"853d0d8c",
+ 481 => x"0c04fc3d",
+ 482 => x"0d767079",
+ 483 => x"7b555555",
+ 484 => x"558f7227",
+ 485 => x"8c387275",
+ 486 => x"07830651",
+ 487 => x"70802ea7",
+ 488 => x"38ff1252",
+ 489 => x"71ff2e98",
+ 490 => x"38727081",
+ 491 => x"05543374",
+ 492 => x"70810556",
+ 493 => x"34ff1252",
+ 494 => x"71ff2e09",
+ 495 => x"8106ea38",
+ 496 => x"74800c86",
+ 497 => x"3d0d0474",
+ 498 => x"51727084",
+ 499 => x"05540871",
+ 500 => x"70840553",
+ 501 => x"0c727084",
+ 502 => x"05540871",
+ 503 => x"70840553",
+ 504 => x"0c727084",
+ 505 => x"05540871",
+ 506 => x"70840553",
+ 507 => x"0c727084",
+ 508 => x"05540871",
+ 509 => x"70840553",
+ 510 => x"0cf01252",
+ 511 => x"718f26c9",
+ 512 => x"38837227",
+ 513 => x"95387270",
+ 514 => x"84055408",
+ 515 => x"71708405",
+ 516 => x"530cfc12",
+ 517 => x"52718326",
+ 518 => x"ed387054",
+ 519 => x"ff8339f7",
+ 520 => x"3d0d7c70",
+ 521 => x"525380c8",
+ 522 => x"3f725480",
+ 523 => x"085580cc",
+ 524 => x"d8568157",
+ 525 => x"80088105",
+ 526 => x"5a8b3de4",
+ 527 => x"11595382",
+ 528 => x"59f41352",
+ 529 => x"7b881108",
+ 530 => x"52538183",
+ 531 => x"3f800830",
+ 532 => x"70800807",
+ 533 => x"9f2c8a07",
+ 534 => x"800c538b",
+ 535 => x"3d0d04ff",
+ 536 => x"3d0d7352",
+ 537 => x"80cd8c08",
+ 538 => x"51ffb43f",
+ 539 => x"833d0d04",
+ 540 => x"fd3d0d75",
+ 541 => x"70718306",
+ 542 => x"53555270",
+ 543 => x"b8387170",
+ 544 => x"087009f7",
+ 545 => x"fbfdff12",
+ 546 => x"0670f884",
+ 547 => x"82818006",
+ 548 => x"51515253",
+ 549 => x"709d3884",
+ 550 => x"13700870",
+ 551 => x"09f7fbfd",
+ 552 => x"ff120670",
+ 553 => x"f8848281",
+ 554 => x"80065151",
+ 555 => x"52537080",
+ 556 => x"2ee53872",
+ 557 => x"52713351",
+ 558 => x"70802e8a",
+ 559 => x"38811270",
+ 560 => x"33525270",
+ 561 => x"f8387174",
+ 562 => x"31800c85",
+ 563 => x"3d0d04f2",
+ 564 => x"3d0d6062",
+ 565 => x"88110870",
+ 566 => x"57575f5a",
+ 567 => x"74802e81",
+ 568 => x"90388c1a",
+ 569 => x"2270832a",
+ 570 => x"81327081",
+ 571 => x"06515558",
+ 572 => x"73863890",
+ 573 => x"1a089138",
+ 574 => x"795190a2",
+ 575 => x"3fff5480",
+ 576 => x"0880ee38",
+ 577 => x"8c1a2258",
+ 578 => x"7d085780",
+ 579 => x"7883ffff",
+ 580 => x"06700a10",
+ 581 => x"0a708106",
+ 582 => x"51565755",
+ 583 => x"73752e80",
+ 584 => x"d7387490",
+ 585 => x"38760884",
+ 586 => x"18088819",
+ 587 => x"59565974",
+ 588 => x"802ef238",
+ 589 => x"74548880",
+ 590 => x"75278438",
+ 591 => x"88805473",
+ 592 => x"5378529c",
+ 593 => x"1a0851a4",
+ 594 => x"1a085473",
+ 595 => x"2d800b80",
+ 596 => x"082582e6",
+ 597 => x"38800819",
+ 598 => x"75800831",
+ 599 => x"7f880508",
+ 600 => x"80083170",
+ 601 => x"6188050c",
+ 602 => x"56565973",
+ 603 => x"ffb43880",
+ 604 => x"5473800c",
+ 605 => x"903d0d04",
+ 606 => x"75813270",
+ 607 => x"81067641",
+ 608 => x"51547380",
+ 609 => x"2e81c138",
+ 610 => x"74903876",
+ 611 => x"08841808",
+ 612 => x"88195956",
+ 613 => x"5974802e",
+ 614 => x"f238881a",
+ 615 => x"087883ff",
+ 616 => x"ff067089",
+ 617 => x"2a708106",
+ 618 => x"51565956",
+ 619 => x"73802e82",
+ 620 => x"fa387575",
+ 621 => x"278d3877",
+ 622 => x"872a7081",
+ 623 => x"06515473",
+ 624 => x"82b53874",
+ 625 => x"76278338",
+ 626 => x"74567553",
+ 627 => x"78527908",
+ 628 => x"5185823f",
+ 629 => x"881a0876",
+ 630 => x"31881b0c",
+ 631 => x"7908167a",
+ 632 => x"0c745675",
+ 633 => x"19757731",
+ 634 => x"7f880508",
+ 635 => x"78317061",
+ 636 => x"88050c56",
+ 637 => x"56597380",
+ 638 => x"2efef438",
+ 639 => x"8c1a2258",
+ 640 => x"ff863977",
+ 641 => x"78547953",
+ 642 => x"7b525684",
+ 643 => x"c83f881a",
+ 644 => x"08783188",
+ 645 => x"1b0c7908",
+ 646 => x"187a0c7c",
+ 647 => x"76315d7c",
+ 648 => x"8e387951",
+ 649 => x"8fdc3f80",
+ 650 => x"08818f38",
+ 651 => x"80085f75",
+ 652 => x"19757731",
+ 653 => x"7f880508",
+ 654 => x"78317061",
+ 655 => x"88050c56",
+ 656 => x"56597380",
+ 657 => x"2efea838",
+ 658 => x"74818338",
+ 659 => x"76088418",
+ 660 => x"08881959",
+ 661 => x"56597480",
+ 662 => x"2ef23874",
+ 663 => x"538a5278",
+ 664 => x"5182d33f",
+ 665 => x"80087931",
+ 666 => x"81055d80",
+ 667 => x"08843881",
+ 668 => x"155d815f",
+ 669 => x"7c58747d",
+ 670 => x"27833874",
+ 671 => x"58941a08",
+ 672 => x"881b0811",
+ 673 => x"575c807a",
+ 674 => x"085c5490",
+ 675 => x"1a087b27",
+ 676 => x"83388154",
+ 677 => x"75782584",
+ 678 => x"3873ba38",
+ 679 => x"7b7824fe",
+ 680 => x"e2387b53",
+ 681 => x"78529c1a",
+ 682 => x"0851a41a",
+ 683 => x"0854732d",
+ 684 => x"80085680",
+ 685 => x"088024fe",
+ 686 => x"e2388c1a",
+ 687 => x"2280c007",
+ 688 => x"54738c1b",
+ 689 => x"23ff5473",
+ 690 => x"800c903d",
+ 691 => x"0d047eff",
+ 692 => x"a338ff87",
+ 693 => x"39755378",
+ 694 => x"527a5182",
+ 695 => x"f83f7908",
+ 696 => x"167a0c79",
+ 697 => x"518e9b3f",
+ 698 => x"8008cf38",
+ 699 => x"7c76315d",
+ 700 => x"7cfebc38",
+ 701 => x"feac3990",
+ 702 => x"1a087a08",
+ 703 => x"71317611",
+ 704 => x"70565a57",
+ 705 => x"5280cd8c",
+ 706 => x"0851848c",
+ 707 => x"3f800880",
+ 708 => x"2effa738",
+ 709 => x"8008901b",
+ 710 => x"0c800816",
+ 711 => x"7a0c7794",
+ 712 => x"1b0c7488",
+ 713 => x"1b0c7456",
+ 714 => x"fd993979",
+ 715 => x"0858901a",
+ 716 => x"08782783",
+ 717 => x"38815475",
+ 718 => x"75278438",
+ 719 => x"73b33894",
+ 720 => x"1a085675",
+ 721 => x"752680d3",
+ 722 => x"38755378",
+ 723 => x"529c1a08",
+ 724 => x"51a41a08",
+ 725 => x"54732d80",
+ 726 => x"08568008",
+ 727 => x"8024fd83",
+ 728 => x"388c1a22",
+ 729 => x"80c00754",
+ 730 => x"738c1b23",
+ 731 => x"ff54fed7",
+ 732 => x"39755378",
+ 733 => x"52775181",
+ 734 => x"dc3f7908",
+ 735 => x"167a0c79",
+ 736 => x"518cff3f",
+ 737 => x"8008802e",
+ 738 => x"fcd9388c",
+ 739 => x"1a2280c0",
+ 740 => x"0754738c",
+ 741 => x"1b23ff54",
+ 742 => x"fead3974",
+ 743 => x"75547953",
+ 744 => x"78525681",
+ 745 => x"b03f881a",
+ 746 => x"08753188",
+ 747 => x"1b0c7908",
+ 748 => x"157a0cfc",
+ 749 => x"ae39fa3d",
+ 750 => x"0d7a7902",
+ 751 => x"8805a705",
+ 752 => x"33565253",
+ 753 => x"8373278a",
+ 754 => x"38708306",
+ 755 => x"5271802e",
+ 756 => x"a838ff13",
+ 757 => x"5372ff2e",
+ 758 => x"97387033",
+ 759 => x"5273722e",
+ 760 => x"91388111",
+ 761 => x"ff145451",
+ 762 => x"72ff2e09",
+ 763 => x"8106eb38",
+ 764 => x"80517080",
+ 765 => x"0c883d0d",
+ 766 => x"04707257",
+ 767 => x"55835175",
+ 768 => x"82802914",
+ 769 => x"ff125256",
+ 770 => x"708025f3",
+ 771 => x"38837327",
+ 772 => x"bf387408",
+ 773 => x"76327009",
+ 774 => x"f7fbfdff",
+ 775 => x"120670f8",
+ 776 => x"84828180",
+ 777 => x"06515151",
+ 778 => x"70802e99",
+ 779 => x"38745180",
+ 780 => x"52703357",
+ 781 => x"73772eff",
+ 782 => x"b9388111",
+ 783 => x"81135351",
+ 784 => x"837227ed",
+ 785 => x"38fc1384",
+ 786 => x"16565372",
+ 787 => x"8326c338",
+ 788 => x"7451fefe",
+ 789 => x"39fa3d0d",
+ 790 => x"787a7c72",
+ 791 => x"72725757",
+ 792 => x"57595656",
+ 793 => x"747627b2",
+ 794 => x"38761551",
+ 795 => x"757127aa",
+ 796 => x"38707717",
+ 797 => x"ff145455",
+ 798 => x"5371ff2e",
+ 799 => x"9638ff14",
+ 800 => x"ff145454",
+ 801 => x"72337434",
+ 802 => x"ff125271",
+ 803 => x"ff2e0981",
+ 804 => x"06ec3875",
+ 805 => x"800c883d",
+ 806 => x"0d04768f",
+ 807 => x"269738ff",
+ 808 => x"125271ff",
+ 809 => x"2eed3872",
+ 810 => x"70810554",
+ 811 => x"33747081",
+ 812 => x"055634eb",
+ 813 => x"39747607",
+ 814 => x"83065170",
+ 815 => x"e2387575",
+ 816 => x"54517270",
+ 817 => x"84055408",
+ 818 => x"71708405",
+ 819 => x"530c7270",
+ 820 => x"84055408",
+ 821 => x"71708405",
+ 822 => x"530c7270",
+ 823 => x"84055408",
+ 824 => x"71708405",
+ 825 => x"530c7270",
+ 826 => x"84055408",
+ 827 => x"71708405",
+ 828 => x"530cf012",
+ 829 => x"52718f26",
+ 830 => x"c9388372",
+ 831 => x"27953872",
+ 832 => x"70840554",
+ 833 => x"08717084",
+ 834 => x"05530cfc",
+ 835 => x"12527183",
+ 836 => x"26ed3870",
+ 837 => x"54ff8839",
+ 838 => x"ef3d0d63",
+ 839 => x"6567405d",
+ 840 => x"427b802e",
+ 841 => x"84fa3861",
+ 842 => x"51a5b63f",
+ 843 => x"f81c7084",
+ 844 => x"120870fc",
+ 845 => x"0670628b",
+ 846 => x"0570f806",
+ 847 => x"4159455b",
+ 848 => x"5c415796",
+ 849 => x"742782c3",
+ 850 => x"38807b24",
+ 851 => x"7e7c2607",
+ 852 => x"59805478",
+ 853 => x"742e0981",
+ 854 => x"0682a938",
+ 855 => x"777b2581",
+ 856 => x"fc387717",
+ 857 => x"80d4c80b",
+ 858 => x"8805085e",
+ 859 => x"567c762e",
+ 860 => x"84bd3884",
+ 861 => x"160870fe",
+ 862 => x"06178411",
+ 863 => x"08810651",
+ 864 => x"55557382",
+ 865 => x"8b3874fc",
+ 866 => x"06597c76",
+ 867 => x"2e84dd38",
+ 868 => x"77195f7e",
+ 869 => x"7b2581fd",
+ 870 => x"38798106",
+ 871 => x"547382bf",
+ 872 => x"38767708",
+ 873 => x"31841108",
+ 874 => x"fc06565a",
+ 875 => x"75802e91",
+ 876 => x"387c762e",
+ 877 => x"84ea3874",
+ 878 => x"19185978",
+ 879 => x"7b258489",
+ 880 => x"3879802e",
+ 881 => x"82993877",
+ 882 => x"15567a76",
+ 883 => x"24829038",
+ 884 => x"8c1a0888",
+ 885 => x"1b08718c",
+ 886 => x"120c8812",
+ 887 => x"0c557976",
+ 888 => x"59578817",
+ 889 => x"61fc0557",
+ 890 => x"5975a426",
+ 891 => x"85ef387b",
+ 892 => x"79555593",
+ 893 => x"762780c9",
+ 894 => x"387b7084",
+ 895 => x"055d087c",
+ 896 => x"56790c74",
+ 897 => x"70840556",
+ 898 => x"088c180c",
+ 899 => x"9017549b",
+ 900 => x"7627ae38",
+ 901 => x"74708405",
+ 902 => x"5608740c",
+ 903 => x"74708405",
+ 904 => x"56089418",
+ 905 => x"0c981754",
+ 906 => x"a3762795",
+ 907 => x"38747084",
+ 908 => x"05560874",
+ 909 => x"0c747084",
+ 910 => x"0556089c",
+ 911 => x"180ca017",
+ 912 => x"54747084",
+ 913 => x"05560874",
+ 914 => x"70840556",
+ 915 => x"0c747084",
+ 916 => x"05560874",
+ 917 => x"70840556",
+ 918 => x"0c740874",
+ 919 => x"0c777b31",
+ 920 => x"56758f26",
+ 921 => x"80c93884",
+ 922 => x"17088106",
+ 923 => x"78078418",
+ 924 => x"0c771784",
+ 925 => x"11088107",
+ 926 => x"84120c54",
+ 927 => x"6151a2e2",
+ 928 => x"3f881754",
+ 929 => x"73800c93",
+ 930 => x"3d0d0490",
+ 931 => x"5bfdba39",
+ 932 => x"7856fe85",
+ 933 => x"398c1608",
+ 934 => x"88170871",
+ 935 => x"8c120c88",
+ 936 => x"120c557e",
+ 937 => x"707c3157",
+ 938 => x"588f7627",
+ 939 => x"ffb9387a",
+ 940 => x"17841808",
+ 941 => x"81067c07",
+ 942 => x"84190c76",
+ 943 => x"81078412",
+ 944 => x"0c761184",
+ 945 => x"11088107",
+ 946 => x"84120c55",
+ 947 => x"88055261",
+ 948 => x"518cf73f",
+ 949 => x"6151a28a",
+ 950 => x"3f881754",
+ 951 => x"ffa6397d",
+ 952 => x"52615194",
+ 953 => x"f73f8008",
+ 954 => x"59800880",
+ 955 => x"2e81a338",
+ 956 => x"8008f805",
+ 957 => x"60840508",
+ 958 => x"fe066105",
+ 959 => x"55577674",
+ 960 => x"2e83e638",
+ 961 => x"fc185675",
+ 962 => x"a42681aa",
+ 963 => x"387b8008",
+ 964 => x"55559376",
+ 965 => x"2780d838",
+ 966 => x"74708405",
+ 967 => x"56088008",
+ 968 => x"70840580",
+ 969 => x"0c0c8008",
+ 970 => x"75708405",
+ 971 => x"57087170",
+ 972 => x"8405530c",
+ 973 => x"549b7627",
+ 974 => x"b6387470",
+ 975 => x"84055608",
+ 976 => x"74708405",
+ 977 => x"560c7470",
+ 978 => x"84055608",
+ 979 => x"74708405",
+ 980 => x"560ca376",
+ 981 => x"27993874",
+ 982 => x"70840556",
+ 983 => x"08747084",
+ 984 => x"05560c74",
+ 985 => x"70840556",
+ 986 => x"08747084",
+ 987 => x"05560c74",
+ 988 => x"70840556",
+ 989 => x"08747084",
+ 990 => x"05560c74",
+ 991 => x"70840556",
+ 992 => x"08747084",
+ 993 => x"05560c74",
+ 994 => x"08740c7b",
+ 995 => x"5261518b",
+ 996 => x"b93f6151",
+ 997 => x"a0cc3f78",
+ 998 => x"5473800c",
+ 999 => x"933d0d04",
+ 1000 => x"7d526151",
+ 1001 => x"93b63f80",
+ 1002 => x"08800c93",
+ 1003 => x"3d0d0484",
+ 1004 => x"160855fb",
+ 1005 => x"d1397553",
+ 1006 => x"7b528008",
+ 1007 => x"51efc73f",
+ 1008 => x"7b526151",
+ 1009 => x"8b843fca",
+ 1010 => x"398c1608",
+ 1011 => x"88170871",
+ 1012 => x"8c120c88",
+ 1013 => x"120c558c",
+ 1014 => x"1a08881b",
+ 1015 => x"08718c12",
+ 1016 => x"0c88120c",
+ 1017 => x"55797959",
+ 1018 => x"57fbf739",
+ 1019 => x"7719901c",
+ 1020 => x"55557375",
+ 1021 => x"24fba238",
+ 1022 => x"7a177080",
+ 1023 => x"d4c80b88",
+ 1024 => x"050c757c",
+ 1025 => x"31810784",
+ 1026 => x"120c5d84",
+ 1027 => x"17088106",
+ 1028 => x"7b078418",
+ 1029 => x"0c61519f",
+ 1030 => x"c93f8817",
+ 1031 => x"54fce539",
+ 1032 => x"74191890",
+ 1033 => x"1c555d73",
+ 1034 => x"7d24fb95",
+ 1035 => x"388c1a08",
+ 1036 => x"881b0871",
+ 1037 => x"8c120c88",
+ 1038 => x"120c5588",
+ 1039 => x"1a61fc05",
+ 1040 => x"575975a4",
+ 1041 => x"2681ae38",
+ 1042 => x"7b795555",
+ 1043 => x"93762780",
+ 1044 => x"c9387b70",
+ 1045 => x"84055d08",
+ 1046 => x"7c56790c",
+ 1047 => x"74708405",
+ 1048 => x"56088c1b",
+ 1049 => x"0c901a54",
+ 1050 => x"9b7627ae",
+ 1051 => x"38747084",
+ 1052 => x"05560874",
+ 1053 => x"0c747084",
+ 1054 => x"05560894",
+ 1055 => x"1b0c981a",
+ 1056 => x"54a37627",
+ 1057 => x"95387470",
+ 1058 => x"84055608",
+ 1059 => x"740c7470",
+ 1060 => x"84055608",
+ 1061 => x"9c1b0ca0",
+ 1062 => x"1a547470",
+ 1063 => x"84055608",
+ 1064 => x"74708405",
+ 1065 => x"560c7470",
+ 1066 => x"84055608",
+ 1067 => x"74708405",
+ 1068 => x"560c7408",
+ 1069 => x"740c7a1a",
+ 1070 => x"7080d4c8",
+ 1071 => x"0b88050c",
+ 1072 => x"7d7c3181",
+ 1073 => x"0784120c",
+ 1074 => x"54841a08",
+ 1075 => x"81067b07",
+ 1076 => x"841b0c61",
+ 1077 => x"519e8b3f",
+ 1078 => x"7854fdbd",
+ 1079 => x"3975537b",
+ 1080 => x"527851ed",
+ 1081 => x"a13ffaf5",
+ 1082 => x"39841708",
+ 1083 => x"fc061860",
+ 1084 => x"5858fae9",
+ 1085 => x"3975537b",
+ 1086 => x"527851ed",
+ 1087 => x"893f7a1a",
+ 1088 => x"7080d4c8",
+ 1089 => x"0b88050c",
+ 1090 => x"7d7c3181",
+ 1091 => x"0784120c",
+ 1092 => x"54841a08",
+ 1093 => x"81067b07",
+ 1094 => x"841b0cff",
+ 1095 => x"b639fa3d",
+ 1096 => x"0d7880cd",
+ 1097 => x"8c085455",
+ 1098 => x"b8130880",
+ 1099 => x"2e81b638",
+ 1100 => x"8c152270",
+ 1101 => x"83ffff06",
+ 1102 => x"70832a81",
+ 1103 => x"32708106",
+ 1104 => x"51555556",
+ 1105 => x"72802e80",
+ 1106 => x"dc387384",
+ 1107 => x"2a813281",
+ 1108 => x"0657ff53",
+ 1109 => x"7680f738",
+ 1110 => x"73822a70",
+ 1111 => x"81065153",
+ 1112 => x"72802eb9",
+ 1113 => x"38b01508",
+ 1114 => x"5473802e",
+ 1115 => x"9c3880c0",
+ 1116 => x"15537373",
+ 1117 => x"2e8f3873",
+ 1118 => x"5280cd8c",
+ 1119 => x"085187ca",
+ 1120 => x"3f8c1522",
+ 1121 => x"5676b016",
+ 1122 => x"0c75db06",
+ 1123 => x"53728c16",
+ 1124 => x"23800b84",
+ 1125 => x"160c9015",
+ 1126 => x"08750c72",
+ 1127 => x"56758807",
+ 1128 => x"53728c16",
+ 1129 => x"23901508",
+ 1130 => x"802e80c1",
+ 1131 => x"388c1522",
+ 1132 => x"70810655",
+ 1133 => x"53739e38",
+ 1134 => x"720a100a",
+ 1135 => x"70810651",
+ 1136 => x"53728538",
+ 1137 => x"94150854",
+ 1138 => x"7388160c",
+ 1139 => x"80537280",
+ 1140 => x"0c883d0d",
+ 1141 => x"04800b88",
+ 1142 => x"160c9415",
+ 1143 => x"08309816",
+ 1144 => x"0c8053ea",
+ 1145 => x"39725182",
+ 1146 => x"fb3ffec4",
+ 1147 => x"3974518c",
+ 1148 => x"e83f8c15",
+ 1149 => x"22708106",
+ 1150 => x"55537380",
+ 1151 => x"2effb938",
+ 1152 => x"d439f83d",
+ 1153 => x"0d7a5877",
+ 1154 => x"802e8199",
+ 1155 => x"3880cd8c",
+ 1156 => x"0854b814",
+ 1157 => x"08802e80",
+ 1158 => x"ed388c18",
+ 1159 => x"2270902b",
+ 1160 => x"70902c70",
+ 1161 => x"832a8132",
+ 1162 => x"81065c51",
+ 1163 => x"57547880",
+ 1164 => x"cd389018",
+ 1165 => x"08577680",
+ 1166 => x"2e80c338",
+ 1167 => x"77087731",
+ 1168 => x"77790c76",
+ 1169 => x"83067a58",
+ 1170 => x"55557385",
+ 1171 => x"38941808",
+ 1172 => x"56758819",
+ 1173 => x"0c807525",
+ 1174 => x"a5387453",
+ 1175 => x"76529c18",
+ 1176 => x"0851a418",
+ 1177 => x"0854732d",
+ 1178 => x"800b8008",
+ 1179 => x"2580c938",
+ 1180 => x"80081775",
+ 1181 => x"80083156",
+ 1182 => x"57748024",
+ 1183 => x"dd38800b",
+ 1184 => x"800c8a3d",
+ 1185 => x"0d047351",
+ 1186 => x"81da3f8c",
+ 1187 => x"18227090",
+ 1188 => x"2b70902c",
+ 1189 => x"70832a81",
+ 1190 => x"3281065c",
+ 1191 => x"51575478",
+ 1192 => x"dd38ff8e",
+ 1193 => x"39a48252",
+ 1194 => x"80cd8c08",
+ 1195 => x"5189f13f",
+ 1196 => x"8008800c",
+ 1197 => x"8a3d0d04",
+ 1198 => x"8c182280",
+ 1199 => x"c0075473",
+ 1200 => x"8c1923ff",
+ 1201 => x"0b800c8a",
+ 1202 => x"3d0d0480",
+ 1203 => x"3d0d7251",
+ 1204 => x"80710c80",
+ 1205 => x"0b84120c",
+ 1206 => x"800b8812",
+ 1207 => x"0c028e05",
+ 1208 => x"228c1223",
+ 1209 => x"02920522",
+ 1210 => x"8e122380",
+ 1211 => x"0b90120c",
+ 1212 => x"800b9412",
+ 1213 => x"0c800b98",
+ 1214 => x"120c709c",
+ 1215 => x"120c80c0",
+ 1216 => x"970ba012",
+ 1217 => x"0c80c0e3",
+ 1218 => x"0ba4120c",
+ 1219 => x"80c1df0b",
+ 1220 => x"a8120c80",
+ 1221 => x"c2b00bac",
+ 1222 => x"120c823d",
+ 1223 => x"0d04fa3d",
+ 1224 => x"0d797080",
+ 1225 => x"dc298c11",
+ 1226 => x"547a5356",
+ 1227 => x"578cad3f",
+ 1228 => x"80088008",
+ 1229 => x"55568008",
+ 1230 => x"802ea238",
+ 1231 => x"80088c05",
+ 1232 => x"54800b80",
+ 1233 => x"080c7680",
+ 1234 => x"0884050c",
+ 1235 => x"73800888",
+ 1236 => x"050c7453",
+ 1237 => x"80527351",
+ 1238 => x"97f83f75",
+ 1239 => x"5473800c",
+ 1240 => x"883d0d04",
+ 1241 => x"fc3d0d76",
+ 1242 => x"a8f70bbc",
+ 1243 => x"120c5581",
+ 1244 => x"0bb8160c",
+ 1245 => x"800b84dc",
+ 1246 => x"160c830b",
+ 1247 => x"84e0160c",
+ 1248 => x"84e81584",
+ 1249 => x"e4160c74",
+ 1250 => x"54805384",
+ 1251 => x"52841508",
+ 1252 => x"51feb83f",
+ 1253 => x"74548153",
+ 1254 => x"89528815",
+ 1255 => x"0851feab",
+ 1256 => x"3f745482",
+ 1257 => x"538a528c",
+ 1258 => x"150851fe",
+ 1259 => x"9e3f863d",
+ 1260 => x"0d04f93d",
+ 1261 => x"0d7980cd",
+ 1262 => x"8c085457",
+ 1263 => x"b8130880",
+ 1264 => x"2e80c838",
+ 1265 => x"84dc1356",
+ 1266 => x"88160884",
+ 1267 => x"1708ff05",
+ 1268 => x"55558074",
+ 1269 => x"249f388c",
+ 1270 => x"15227090",
+ 1271 => x"2b70902c",
+ 1272 => x"51545872",
+ 1273 => x"802e80ca",
+ 1274 => x"3880dc15",
+ 1275 => x"ff155555",
+ 1276 => x"738025e3",
+ 1277 => x"38750853",
+ 1278 => x"72802e9f",
+ 1279 => x"38725688",
+ 1280 => x"16088417",
+ 1281 => x"08ff0555",
+ 1282 => x"55c83972",
+ 1283 => x"51fed53f",
+ 1284 => x"80cd8c08",
+ 1285 => x"84dc0556",
+ 1286 => x"ffae3984",
+ 1287 => x"527651fd",
+ 1288 => x"fd3f8008",
+ 1289 => x"760c8008",
+ 1290 => x"802e80c0",
+ 1291 => x"38800856",
+ 1292 => x"ce39810b",
+ 1293 => x"8c162372",
+ 1294 => x"750c7288",
+ 1295 => x"160c7284",
+ 1296 => x"160c7290",
+ 1297 => x"160c7294",
+ 1298 => x"160c7298",
+ 1299 => x"160cff0b",
+ 1300 => x"8e162372",
+ 1301 => x"b0160c72",
+ 1302 => x"b4160c72",
+ 1303 => x"80c4160c",
+ 1304 => x"7280c816",
+ 1305 => x"0c74800c",
+ 1306 => x"893d0d04",
+ 1307 => x"8c770c80",
+ 1308 => x"0b800c89",
+ 1309 => x"3d0d04ff",
+ 1310 => x"3d0da482",
+ 1311 => x"52735186",
+ 1312 => x"9f3f833d",
+ 1313 => x"0d04803d",
+ 1314 => x"0d80cd8c",
+ 1315 => x"0851e83f",
+ 1316 => x"823d0d04",
+ 1317 => x"fb3d0d77",
+ 1318 => x"70525696",
+ 1319 => x"c43f80d4",
+ 1320 => x"c80b8805",
+ 1321 => x"08841108",
+ 1322 => x"fc06707b",
+ 1323 => x"319fef05",
+ 1324 => x"e08006e0",
+ 1325 => x"80055656",
+ 1326 => x"53a08074",
+ 1327 => x"24943880",
+ 1328 => x"52755196",
+ 1329 => x"9e3f80d4",
+ 1330 => x"d0081553",
+ 1331 => x"7280082e",
+ 1332 => x"8f387551",
+ 1333 => x"968c3f80",
+ 1334 => x"5372800c",
+ 1335 => x"873d0d04",
+ 1336 => x"73305275",
+ 1337 => x"5195fc3f",
+ 1338 => x"8008ff2e",
+ 1339 => x"a83880d4",
+ 1340 => x"c80b8805",
+ 1341 => x"08757531",
+ 1342 => x"81078412",
+ 1343 => x"0c5380d4",
+ 1344 => x"8c087431",
+ 1345 => x"80d48c0c",
+ 1346 => x"755195d6",
+ 1347 => x"3f810b80",
+ 1348 => x"0c873d0d",
+ 1349 => x"04805275",
+ 1350 => x"5195c83f",
+ 1351 => x"80d4c80b",
+ 1352 => x"88050880",
+ 1353 => x"08713156",
+ 1354 => x"538f7525",
+ 1355 => x"ffa43880",
+ 1356 => x"0880d4bc",
+ 1357 => x"083180d4",
+ 1358 => x"8c0c7481",
+ 1359 => x"0784140c",
+ 1360 => x"7551959e",
+ 1361 => x"3f8053ff",
+ 1362 => x"9039f63d",
+ 1363 => x"0d7c7e54",
+ 1364 => x"5b72802e",
+ 1365 => x"8283387a",
+ 1366 => x"5195863f",
+ 1367 => x"f8138411",
+ 1368 => x"0870fe06",
+ 1369 => x"70138411",
+ 1370 => x"08fc065d",
+ 1371 => x"58595458",
+ 1372 => x"80d4d008",
+ 1373 => x"752e82de",
+ 1374 => x"38788416",
+ 1375 => x"0c807381",
+ 1376 => x"06545a72",
+ 1377 => x"7a2e81d5",
+ 1378 => x"38781584",
+ 1379 => x"11088106",
+ 1380 => x"515372a0",
+ 1381 => x"38781757",
+ 1382 => x"7981e638",
+ 1383 => x"88150853",
+ 1384 => x"7280d4d0",
+ 1385 => x"2e82f938",
+ 1386 => x"8c150870",
+ 1387 => x"8c150c73",
+ 1388 => x"88120c56",
+ 1389 => x"76810784",
+ 1390 => x"190c7618",
+ 1391 => x"77710c53",
+ 1392 => x"79819138",
+ 1393 => x"83ff7727",
+ 1394 => x"81c83876",
+ 1395 => x"892a7783",
+ 1396 => x"2a565372",
+ 1397 => x"802ebf38",
+ 1398 => x"76862ab8",
+ 1399 => x"05558473",
+ 1400 => x"27b43880",
+ 1401 => x"db135594",
+ 1402 => x"7327ab38",
+ 1403 => x"768c2a80",
+ 1404 => x"ee055580",
+ 1405 => x"d473279e",
+ 1406 => x"38768f2a",
+ 1407 => x"80f70555",
+ 1408 => x"82d47327",
+ 1409 => x"91387692",
+ 1410 => x"2a80fc05",
+ 1411 => x"558ad473",
+ 1412 => x"27843880",
+ 1413 => x"fe557410",
+ 1414 => x"101080d4",
+ 1415 => x"c8058811",
+ 1416 => x"08555673",
+ 1417 => x"762e82b3",
+ 1418 => x"38841408",
+ 1419 => x"fc065376",
+ 1420 => x"73278d38",
+ 1421 => x"88140854",
+ 1422 => x"73762e09",
+ 1423 => x"8106ea38",
+ 1424 => x"8c140870",
+ 1425 => x"8c1a0c74",
+ 1426 => x"881a0c78",
+ 1427 => x"88120c56",
+ 1428 => x"778c150c",
+ 1429 => x"7a51938a",
+ 1430 => x"3f8c3d0d",
+ 1431 => x"04770878",
+ 1432 => x"71315977",
+ 1433 => x"05881908",
+ 1434 => x"54577280",
+ 1435 => x"d4d02e80",
+ 1436 => x"e0388c18",
+ 1437 => x"08708c15",
+ 1438 => x"0c738812",
+ 1439 => x"0c56fe89",
+ 1440 => x"39881508",
+ 1441 => x"8c160870",
+ 1442 => x"8c130c57",
+ 1443 => x"88170cfe",
+ 1444 => x"a3397683",
+ 1445 => x"2a705455",
+ 1446 => x"80752481",
+ 1447 => x"98387282",
+ 1448 => x"2c81712b",
+ 1449 => x"80d4cc08",
+ 1450 => x"0780d4c8",
+ 1451 => x"0b84050c",
+ 1452 => x"53741010",
+ 1453 => x"1080d4c8",
+ 1454 => x"05881108",
+ 1455 => x"5556758c",
+ 1456 => x"190c7388",
+ 1457 => x"190c7788",
+ 1458 => x"170c778c",
+ 1459 => x"150cff84",
+ 1460 => x"39815afd",
+ 1461 => x"b4397817",
+ 1462 => x"73810654",
+ 1463 => x"57729838",
+ 1464 => x"77087871",
+ 1465 => x"31597705",
+ 1466 => x"8c190888",
+ 1467 => x"1a08718c",
+ 1468 => x"120c8812",
+ 1469 => x"0c575776",
+ 1470 => x"81078419",
+ 1471 => x"0c7780d4",
+ 1472 => x"c80b8805",
+ 1473 => x"0c80d4c4",
+ 1474 => x"087726fe",
+ 1475 => x"c73880d4",
+ 1476 => x"c008527a",
+ 1477 => x"51fafd3f",
+ 1478 => x"7a5191c6",
+ 1479 => x"3ffeba39",
+ 1480 => x"81788c15",
+ 1481 => x"0c788815",
+ 1482 => x"0c738c1a",
+ 1483 => x"0c73881a",
+ 1484 => x"0c5afd80",
+ 1485 => x"39831570",
+ 1486 => x"822c8171",
+ 1487 => x"2b80d4cc",
+ 1488 => x"080780d4",
+ 1489 => x"c80b8405",
+ 1490 => x"0c515374",
+ 1491 => x"10101080",
+ 1492 => x"d4c80588",
+ 1493 => x"11085556",
+ 1494 => x"fee43974",
+ 1495 => x"53807524",
+ 1496 => x"a7387282",
+ 1497 => x"2c81712b",
+ 1498 => x"80d4cc08",
+ 1499 => x"0780d4c8",
+ 1500 => x"0b84050c",
+ 1501 => x"53758c19",
+ 1502 => x"0c738819",
+ 1503 => x"0c778817",
+ 1504 => x"0c778c15",
+ 1505 => x"0cfdcd39",
+ 1506 => x"83157082",
+ 1507 => x"2c81712b",
+ 1508 => x"80d4cc08",
+ 1509 => x"0780d4c8",
+ 1510 => x"0b84050c",
+ 1511 => x"5153d639",
+ 1512 => x"f93d0d79",
+ 1513 => x"7b585380",
+ 1514 => x"0b80cd8c",
+ 1515 => x"08535672",
+ 1516 => x"722e80c0",
+ 1517 => x"3884dc13",
+ 1518 => x"5574762e",
+ 1519 => x"b7388815",
+ 1520 => x"08841608",
+ 1521 => x"ff055454",
+ 1522 => x"8073249d",
+ 1523 => x"388c1422",
+ 1524 => x"70902b70",
+ 1525 => x"902c5153",
+ 1526 => x"587180d8",
+ 1527 => x"3880dc14",
+ 1528 => x"ff145454",
+ 1529 => x"728025e5",
+ 1530 => x"38740855",
+ 1531 => x"74d03880",
+ 1532 => x"cd8c0852",
+ 1533 => x"84dc1255",
+ 1534 => x"74802eb1",
+ 1535 => x"38881508",
+ 1536 => x"841608ff",
+ 1537 => x"05545480",
+ 1538 => x"73249c38",
+ 1539 => x"8c142270",
+ 1540 => x"902b7090",
+ 1541 => x"2c515358",
+ 1542 => x"71ad3880",
+ 1543 => x"dc14ff14",
+ 1544 => x"54547280",
+ 1545 => x"25e63874",
+ 1546 => x"085574d1",
+ 1547 => x"3875800c",
+ 1548 => x"893d0d04",
+ 1549 => x"7351762d",
+ 1550 => x"75800807",
+ 1551 => x"80dc15ff",
+ 1552 => x"15555556",
+ 1553 => x"ff9e3973",
+ 1554 => x"51762d75",
+ 1555 => x"80080780",
+ 1556 => x"dc15ff15",
+ 1557 => x"555556ca",
+ 1558 => x"39ea3d0d",
+ 1559 => x"688c1122",
+ 1560 => x"700a100a",
+ 1561 => x"81065758",
+ 1562 => x"567480e4",
+ 1563 => x"388e1622",
+ 1564 => x"70902b70",
+ 1565 => x"902c5155",
+ 1566 => x"58807424",
+ 1567 => x"b138983d",
+ 1568 => x"c4055373",
+ 1569 => x"5280cd8c",
+ 1570 => x"085192ac",
+ 1571 => x"3f800b80",
+ 1572 => x"08249738",
+ 1573 => x"7983e080",
+ 1574 => x"06547380",
+ 1575 => x"c0802e81",
+ 1576 => x"8f387382",
+ 1577 => x"80802e81",
+ 1578 => x"91388c16",
+ 1579 => x"22577690",
+ 1580 => x"80075473",
+ 1581 => x"8c172388",
+ 1582 => x"805280cd",
+ 1583 => x"8c085181",
+ 1584 => x"9b3f8008",
+ 1585 => x"9d388c16",
+ 1586 => x"22820754",
+ 1587 => x"738c1723",
+ 1588 => x"80c31670",
+ 1589 => x"770c9017",
+ 1590 => x"0c810b94",
+ 1591 => x"170c983d",
+ 1592 => x"0d0480cd",
+ 1593 => x"8c08a8f7",
+ 1594 => x"0bbc120c",
+ 1595 => x"548c1622",
+ 1596 => x"81800754",
+ 1597 => x"738c1723",
+ 1598 => x"8008760c",
+ 1599 => x"80089017",
+ 1600 => x"0c88800b",
+ 1601 => x"94170c74",
+ 1602 => x"802ed338",
+ 1603 => x"8e162270",
+ 1604 => x"902b7090",
+ 1605 => x"2c535558",
+ 1606 => x"98a23f80",
+ 1607 => x"08802eff",
+ 1608 => x"bd388c16",
+ 1609 => x"22810754",
+ 1610 => x"738c1723",
+ 1611 => x"983d0d04",
+ 1612 => x"810b8c17",
+ 1613 => x"225855fe",
+ 1614 => x"f539a816",
+ 1615 => x"0880c1df",
+ 1616 => x"2e098106",
+ 1617 => x"fee4388c",
+ 1618 => x"16228880",
+ 1619 => x"0754738c",
+ 1620 => x"17238880",
+ 1621 => x"0b80cc17",
+ 1622 => x"0cfedc39",
+ 1623 => x"f33d0d7f",
+ 1624 => x"618b1170",
+ 1625 => x"f8065c55",
+ 1626 => x"555e7296",
+ 1627 => x"26833890",
+ 1628 => x"59807924",
+ 1629 => x"747a2607",
+ 1630 => x"53805472",
+ 1631 => x"742e0981",
+ 1632 => x"0680cb38",
+ 1633 => x"7d518cd9",
+ 1634 => x"3f7883f7",
+ 1635 => x"2680c638",
+ 1636 => x"78832a70",
+ 1637 => x"10101080",
+ 1638 => x"d4c8058c",
+ 1639 => x"11085959",
+ 1640 => x"5a76782e",
+ 1641 => x"83b03884",
+ 1642 => x"1708fc06",
+ 1643 => x"568c1708",
+ 1644 => x"88180871",
+ 1645 => x"8c120c88",
+ 1646 => x"120c5875",
+ 1647 => x"17841108",
+ 1648 => x"81078412",
+ 1649 => x"0c537d51",
+ 1650 => x"8c983f88",
+ 1651 => x"17547380",
+ 1652 => x"0c8f3d0d",
+ 1653 => x"0478892a",
+ 1654 => x"79832a5b",
+ 1655 => x"5372802e",
+ 1656 => x"bf387886",
+ 1657 => x"2ab8055a",
+ 1658 => x"847327b4",
+ 1659 => x"3880db13",
+ 1660 => x"5a947327",
+ 1661 => x"ab38788c",
+ 1662 => x"2a80ee05",
+ 1663 => x"5a80d473",
+ 1664 => x"279e3878",
+ 1665 => x"8f2a80f7",
+ 1666 => x"055a82d4",
+ 1667 => x"73279138",
+ 1668 => x"78922a80",
+ 1669 => x"fc055a8a",
+ 1670 => x"d4732784",
+ 1671 => x"3880fe5a",
+ 1672 => x"79101010",
+ 1673 => x"80d4c805",
+ 1674 => x"8c110858",
+ 1675 => x"5576752e",
+ 1676 => x"a3388417",
+ 1677 => x"08fc0670",
+ 1678 => x"7a315556",
+ 1679 => x"738f2488",
+ 1680 => x"d5387380",
+ 1681 => x"25fee638",
+ 1682 => x"8c170857",
+ 1683 => x"76752e09",
+ 1684 => x"8106df38",
+ 1685 => x"811a5a80",
+ 1686 => x"d4d80857",
+ 1687 => x"7680d4d0",
+ 1688 => x"2e82c038",
+ 1689 => x"841708fc",
+ 1690 => x"06707a31",
+ 1691 => x"5556738f",
+ 1692 => x"2481f938",
+ 1693 => x"80d4d00b",
+ 1694 => x"80d4dc0c",
+ 1695 => x"80d4d00b",
+ 1696 => x"80d4d80c",
+ 1697 => x"738025fe",
+ 1698 => x"b23883ff",
+ 1699 => x"762783df",
+ 1700 => x"3875892a",
+ 1701 => x"76832a55",
+ 1702 => x"5372802e",
+ 1703 => x"bf387586",
+ 1704 => x"2ab80554",
+ 1705 => x"847327b4",
+ 1706 => x"3880db13",
+ 1707 => x"54947327",
+ 1708 => x"ab38758c",
+ 1709 => x"2a80ee05",
+ 1710 => x"5480d473",
+ 1711 => x"279e3875",
+ 1712 => x"8f2a80f7",
+ 1713 => x"055482d4",
+ 1714 => x"73279138",
+ 1715 => x"75922a80",
+ 1716 => x"fc05548a",
+ 1717 => x"d4732784",
+ 1718 => x"3880fe54",
+ 1719 => x"73101010",
+ 1720 => x"80d4c805",
+ 1721 => x"88110856",
+ 1722 => x"5874782e",
+ 1723 => x"86cf3884",
+ 1724 => x"1508fc06",
+ 1725 => x"53757327",
+ 1726 => x"8d388815",
+ 1727 => x"08557478",
+ 1728 => x"2e098106",
+ 1729 => x"ea388c15",
+ 1730 => x"0880d4c8",
+ 1731 => x"0b840508",
+ 1732 => x"718c1a0c",
+ 1733 => x"76881a0c",
+ 1734 => x"7888130c",
+ 1735 => x"788c180c",
+ 1736 => x"5d587953",
+ 1737 => x"807a2483",
+ 1738 => x"e6387282",
+ 1739 => x"2c81712b",
+ 1740 => x"5c537a7c",
+ 1741 => x"26819838",
+ 1742 => x"7b7b0653",
+ 1743 => x"7282f138",
+ 1744 => x"79fc0684",
+ 1745 => x"055a7a10",
+ 1746 => x"707d0654",
+ 1747 => x"5b7282e0",
+ 1748 => x"38841a5a",
+ 1749 => x"f1398817",
+ 1750 => x"8c110858",
+ 1751 => x"5876782e",
+ 1752 => x"098106fc",
+ 1753 => x"c238821a",
+ 1754 => x"5afdec39",
+ 1755 => x"78177981",
+ 1756 => x"0784190c",
+ 1757 => x"7080d4dc",
+ 1758 => x"0c7080d4",
+ 1759 => x"d80c80d4",
+ 1760 => x"d00b8c12",
+ 1761 => x"0c8c1108",
+ 1762 => x"88120c74",
+ 1763 => x"81078412",
+ 1764 => x"0c741175",
+ 1765 => x"710c5153",
+ 1766 => x"7d5188c6",
+ 1767 => x"3f881754",
+ 1768 => x"fcac3980",
+ 1769 => x"d4c80b84",
+ 1770 => x"05087a54",
+ 1771 => x"5c798025",
+ 1772 => x"fef83882",
+ 1773 => x"da397a09",
+ 1774 => x"7c067080",
+ 1775 => x"d4c80b84",
+ 1776 => x"050c5c7a",
+ 1777 => x"105b7a7c",
+ 1778 => x"2685387a",
+ 1779 => x"85b83880",
+ 1780 => x"d4c80b88",
+ 1781 => x"05087084",
+ 1782 => x"1208fc06",
+ 1783 => x"707c317c",
+ 1784 => x"72268f72",
+ 1785 => x"25075757",
+ 1786 => x"5c5d5572",
+ 1787 => x"802e80db",
+ 1788 => x"38797a16",
+ 1789 => x"80d4c008",
+ 1790 => x"1b90115a",
+ 1791 => x"55575b80",
+ 1792 => x"d4bc08ff",
+ 1793 => x"2e8838a0",
+ 1794 => x"8f13e080",
+ 1795 => x"06577652",
+ 1796 => x"7d5187cf",
+ 1797 => x"3f800854",
+ 1798 => x"8008ff2e",
+ 1799 => x"90388008",
+ 1800 => x"76278299",
+ 1801 => x"387480d4",
+ 1802 => x"c82e8291",
+ 1803 => x"3880d4c8",
+ 1804 => x"0b880508",
+ 1805 => x"55841508",
+ 1806 => x"fc06707a",
+ 1807 => x"317a7226",
+ 1808 => x"8f722507",
+ 1809 => x"52555372",
+ 1810 => x"83e63874",
+ 1811 => x"79810784",
+ 1812 => x"170c7916",
+ 1813 => x"7080d4c8",
+ 1814 => x"0b88050c",
+ 1815 => x"75810784",
+ 1816 => x"120c547e",
+ 1817 => x"525786fa",
+ 1818 => x"3f881754",
+ 1819 => x"fae03975",
+ 1820 => x"832a7054",
+ 1821 => x"54807424",
+ 1822 => x"819b3872",
+ 1823 => x"822c8171",
+ 1824 => x"2b80d4cc",
+ 1825 => x"08077080",
+ 1826 => x"d4c80b84",
+ 1827 => x"050c7510",
+ 1828 => x"101080d4",
+ 1829 => x"c8058811",
+ 1830 => x"08585a5d",
+ 1831 => x"53778c18",
+ 1832 => x"0c748818",
+ 1833 => x"0c768819",
+ 1834 => x"0c768c16",
+ 1835 => x"0cfcf339",
+ 1836 => x"797a1010",
+ 1837 => x"1080d4c8",
+ 1838 => x"05705759",
+ 1839 => x"5d8c1508",
+ 1840 => x"5776752e",
+ 1841 => x"a3388417",
+ 1842 => x"08fc0670",
+ 1843 => x"7a315556",
+ 1844 => x"738f2483",
+ 1845 => x"ca387380",
+ 1846 => x"25848138",
+ 1847 => x"8c170857",
+ 1848 => x"76752e09",
+ 1849 => x"8106df38",
+ 1850 => x"8815811b",
+ 1851 => x"70830655",
+ 1852 => x"5b5572c9",
+ 1853 => x"387c8306",
+ 1854 => x"5372802e",
+ 1855 => x"fdb838ff",
+ 1856 => x"1df81959",
+ 1857 => x"5d881808",
+ 1858 => x"782eea38",
+ 1859 => x"fdb53983",
+ 1860 => x"1a53fc96",
+ 1861 => x"39831470",
+ 1862 => x"822c8171",
+ 1863 => x"2b80d4cc",
+ 1864 => x"08077080",
+ 1865 => x"d4c80b84",
+ 1866 => x"050c7610",
+ 1867 => x"101080d4",
+ 1868 => x"c8058811",
+ 1869 => x"08595b5e",
+ 1870 => x"5153fee1",
+ 1871 => x"3980d48c",
+ 1872 => x"08175880",
+ 1873 => x"08762e81",
+ 1874 => x"8d3880d4",
+ 1875 => x"bc08ff2e",
+ 1876 => x"83ec3873",
+ 1877 => x"76311880",
+ 1878 => x"d48c0c73",
+ 1879 => x"87067057",
+ 1880 => x"5372802e",
+ 1881 => x"88388873",
+ 1882 => x"31701555",
+ 1883 => x"5676149f",
+ 1884 => x"ff06a080",
+ 1885 => x"71311770",
+ 1886 => x"547f5357",
+ 1887 => x"5384e43f",
+ 1888 => x"80085380",
+ 1889 => x"08ff2e81",
+ 1890 => x"a03880d4",
+ 1891 => x"8c081670",
+ 1892 => x"80d48c0c",
+ 1893 => x"747580d4",
+ 1894 => x"c80b8805",
+ 1895 => x"0c747631",
+ 1896 => x"18708107",
+ 1897 => x"51555658",
+ 1898 => x"7b80d4c8",
+ 1899 => x"2e839c38",
+ 1900 => x"798f2682",
+ 1901 => x"cb38810b",
+ 1902 => x"84150c84",
+ 1903 => x"1508fc06",
+ 1904 => x"707a317a",
+ 1905 => x"72268f72",
+ 1906 => x"25075255",
+ 1907 => x"5372802e",
+ 1908 => x"fcf93880",
+ 1909 => x"db398008",
+ 1910 => x"9fff0653",
+ 1911 => x"72feeb38",
+ 1912 => x"7780d48c",
+ 1913 => x"0c80d4c8",
+ 1914 => x"0b880508",
+ 1915 => x"7b188107",
+ 1916 => x"84120c55",
+ 1917 => x"80d4b808",
+ 1918 => x"78278638",
+ 1919 => x"7780d4b8",
+ 1920 => x"0c80d4b4",
+ 1921 => x"087827fc",
+ 1922 => x"ac387780",
+ 1923 => x"d4b40c84",
+ 1924 => x"1508fc06",
+ 1925 => x"707a317a",
+ 1926 => x"72268f72",
+ 1927 => x"25075255",
+ 1928 => x"5372802e",
+ 1929 => x"fca53888",
+ 1930 => x"39807454",
+ 1931 => x"56fedb39",
+ 1932 => x"7d5183ae",
+ 1933 => x"3f800b80",
+ 1934 => x"0c8f3d0d",
+ 1935 => x"04735380",
+ 1936 => x"7424a938",
+ 1937 => x"72822c81",
+ 1938 => x"712b80d4",
+ 1939 => x"cc080770",
+ 1940 => x"80d4c80b",
+ 1941 => x"84050c5d",
+ 1942 => x"53778c18",
+ 1943 => x"0c748818",
+ 1944 => x"0c768819",
+ 1945 => x"0c768c16",
+ 1946 => x"0cf9b739",
+ 1947 => x"83147082",
+ 1948 => x"2c81712b",
+ 1949 => x"80d4cc08",
+ 1950 => x"077080d4",
+ 1951 => x"c80b8405",
+ 1952 => x"0c5e5153",
+ 1953 => x"d4397b7b",
+ 1954 => x"065372fc",
+ 1955 => x"a338841a",
+ 1956 => x"7b105c5a",
+ 1957 => x"f139ff1a",
+ 1958 => x"8111515a",
+ 1959 => x"f7b93978",
+ 1960 => x"17798107",
+ 1961 => x"84190c8c",
+ 1962 => x"18088819",
+ 1963 => x"08718c12",
+ 1964 => x"0c88120c",
+ 1965 => x"597080d4",
+ 1966 => x"dc0c7080",
+ 1967 => x"d4d80c80",
+ 1968 => x"d4d00b8c",
+ 1969 => x"120c8c11",
+ 1970 => x"0888120c",
+ 1971 => x"74810784",
+ 1972 => x"120c7411",
+ 1973 => x"75710c51",
+ 1974 => x"53f9bd39",
+ 1975 => x"75178411",
+ 1976 => x"08810784",
+ 1977 => x"120c538c",
+ 1978 => x"17088818",
+ 1979 => x"08718c12",
+ 1980 => x"0c88120c",
+ 1981 => x"587d5181",
+ 1982 => x"e93f8817",
+ 1983 => x"54f5cf39",
+ 1984 => x"7284150c",
+ 1985 => x"f41af806",
+ 1986 => x"70841e08",
+ 1987 => x"81060784",
+ 1988 => x"1e0c701d",
+ 1989 => x"545b850b",
+ 1990 => x"84140c85",
+ 1991 => x"0b88140c",
+ 1992 => x"8f7b27fd",
+ 1993 => x"cf38881c",
+ 1994 => x"527d51ec",
+ 1995 => x"9d3f80d4",
+ 1996 => x"c80b8805",
+ 1997 => x"0880d48c",
+ 1998 => x"085955fd",
+ 1999 => x"b7397780",
+ 2000 => x"d48c0c73",
+ 2001 => x"80d4bc0c",
+ 2002 => x"fc913972",
+ 2003 => x"84150cfd",
+ 2004 => x"a339fc3d",
+ 2005 => x"0d767971",
+ 2006 => x"028c059f",
+ 2007 => x"05335755",
+ 2008 => x"53558372",
+ 2009 => x"278a3874",
+ 2010 => x"83065170",
+ 2011 => x"802ea238",
+ 2012 => x"ff125271",
+ 2013 => x"ff2e9338",
+ 2014 => x"73737081",
+ 2015 => x"055534ff",
+ 2016 => x"125271ff",
+ 2017 => x"2e098106",
+ 2018 => x"ef387480",
+ 2019 => x"0c863d0d",
+ 2020 => x"04747488",
+ 2021 => x"2b750770",
+ 2022 => x"71902b07",
+ 2023 => x"5154518f",
+ 2024 => x"7227a538",
+ 2025 => x"72717084",
+ 2026 => x"05530c72",
+ 2027 => x"71708405",
+ 2028 => x"530c7271",
+ 2029 => x"70840553",
+ 2030 => x"0c727170",
+ 2031 => x"8405530c",
+ 2032 => x"f0125271",
+ 2033 => x"8f26dd38",
+ 2034 => x"83722790",
+ 2035 => x"38727170",
+ 2036 => x"8405530c",
+ 2037 => x"fc125271",
+ 2038 => x"8326f238",
+ 2039 => x"7053ff90",
+ 2040 => x"390404fd",
+ 2041 => x"3d0d800b",
+ 2042 => x"80dd800c",
+ 2043 => x"765184ee",
+ 2044 => x"3f800853",
+ 2045 => x"8008ff2e",
+ 2046 => x"88387280",
+ 2047 => x"0c853d0d",
+ 2048 => x"0480dd80",
+ 2049 => x"08547380",
+ 2050 => x"2ef03875",
+ 2051 => x"74710c52",
+ 2052 => x"72800c85",
+ 2053 => x"3d0d04f9",
+ 2054 => x"3d0d797c",
+ 2055 => x"557b548e",
+ 2056 => x"11227090",
+ 2057 => x"2b70902c",
+ 2058 => x"555780cd",
+ 2059 => x"8c085358",
+ 2060 => x"5683f33f",
+ 2061 => x"80085780",
+ 2062 => x"0b800824",
+ 2063 => x"933880d0",
+ 2064 => x"16088008",
+ 2065 => x"0580d017",
+ 2066 => x"0c76800c",
+ 2067 => x"893d0d04",
+ 2068 => x"8c162283",
+ 2069 => x"dfff0655",
+ 2070 => x"748c1723",
+ 2071 => x"76800c89",
+ 2072 => x"3d0d04fa",
+ 2073 => x"3d0d788c",
+ 2074 => x"11227088",
+ 2075 => x"2a708106",
+ 2076 => x"51575856",
+ 2077 => x"74a9388c",
+ 2078 => x"162283df",
+ 2079 => x"ff065574",
+ 2080 => x"8c17237a",
+ 2081 => x"5479538e",
+ 2082 => x"16227090",
+ 2083 => x"2b70902c",
+ 2084 => x"545680cd",
+ 2085 => x"8c085256",
+ 2086 => x"81b23f88",
+ 2087 => x"3d0d0482",
+ 2088 => x"5480538e",
+ 2089 => x"16227090",
+ 2090 => x"2b70902c",
+ 2091 => x"545680cd",
+ 2092 => x"8c085257",
+ 2093 => x"82b83f8c",
+ 2094 => x"162283df",
+ 2095 => x"ff065574",
+ 2096 => x"8c17237a",
+ 2097 => x"5479538e",
+ 2098 => x"16227090",
+ 2099 => x"2b70902c",
+ 2100 => x"545680cd",
+ 2101 => x"8c085256",
+ 2102 => x"80f23f88",
+ 2103 => x"3d0d04f9",
+ 2104 => x"3d0d797c",
+ 2105 => x"557b548e",
+ 2106 => x"11227090",
+ 2107 => x"2b70902c",
+ 2108 => x"555780cd",
+ 2109 => x"8c085358",
+ 2110 => x"5681f33f",
+ 2111 => x"80085780",
+ 2112 => x"08ff2e99",
+ 2113 => x"388c1622",
+ 2114 => x"a0800755",
+ 2115 => x"748c1723",
+ 2116 => x"800880d0",
+ 2117 => x"170c7680",
+ 2118 => x"0c893d0d",
+ 2119 => x"048c1622",
+ 2120 => x"83dfff06",
+ 2121 => x"55748c17",
+ 2122 => x"2376800c",
+ 2123 => x"893d0d04",
+ 2124 => x"fe3d0d74",
+ 2125 => x"8e112270",
+ 2126 => x"902b7090",
+ 2127 => x"2c555151",
+ 2128 => x"5380cd8c",
+ 2129 => x"0851bd3f",
+ 2130 => x"843d0d04",
+ 2131 => x"fb3d0d80",
+ 2132 => x"0b80dd80",
+ 2133 => x"0c7a5379",
+ 2134 => x"52785182",
+ 2135 => x"fc3f8008",
+ 2136 => x"558008ff",
+ 2137 => x"2e883874",
+ 2138 => x"800c873d",
+ 2139 => x"0d0480dd",
+ 2140 => x"80085675",
+ 2141 => x"802ef038",
+ 2142 => x"7776710c",
+ 2143 => x"5474800c",
+ 2144 => x"873d0d04",
+ 2145 => x"fd3d0d80",
+ 2146 => x"0b80dd80",
+ 2147 => x"0c765184",
+ 2148 => x"c63f8008",
+ 2149 => x"538008ff",
+ 2150 => x"2e883872",
+ 2151 => x"800c853d",
+ 2152 => x"0d0480dd",
+ 2153 => x"80085473",
+ 2154 => x"802ef038",
+ 2155 => x"7574710c",
+ 2156 => x"5272800c",
+ 2157 => x"853d0d04",
+ 2158 => x"fc3d0d80",
+ 2159 => x"0b80dd80",
+ 2160 => x"0c785277",
+ 2161 => x"5186ac3f",
+ 2162 => x"80085480",
+ 2163 => x"08ff2e88",
+ 2164 => x"3873800c",
+ 2165 => x"863d0d04",
+ 2166 => x"80dd8008",
+ 2167 => x"5574802e",
+ 2168 => x"f0387675",
+ 2169 => x"710c5373",
+ 2170 => x"800c863d",
+ 2171 => x"0d04fb3d",
+ 2172 => x"0d800b80",
+ 2173 => x"dd800c7a",
+ 2174 => x"53795278",
+ 2175 => x"5184893f",
+ 2176 => x"80085580",
+ 2177 => x"08ff2e88",
+ 2178 => x"3874800c",
+ 2179 => x"873d0d04",
+ 2180 => x"80dd8008",
+ 2181 => x"5675802e",
+ 2182 => x"f0387776",
+ 2183 => x"710c5474",
+ 2184 => x"800c873d",
+ 2185 => x"0d04fb3d",
+ 2186 => x"0d800b80",
+ 2187 => x"dd800c7a",
+ 2188 => x"53795278",
+ 2189 => x"5182963f",
+ 2190 => x"80085580",
+ 2191 => x"08ff2e88",
+ 2192 => x"3874800c",
+ 2193 => x"873d0d04",
+ 2194 => x"80dd8008",
+ 2195 => x"5675802e",
+ 2196 => x"f0387776",
+ 2197 => x"710c5474",
+ 2198 => x"800c873d",
+ 2199 => x"0d04fe3d",
+ 2200 => x"0d80dcf8",
+ 2201 => x"0851708a",
+ 2202 => x"3880dd84",
+ 2203 => x"7080dcf8",
+ 2204 => x"0c517075",
+ 2205 => x"125252ff",
+ 2206 => x"537087fb",
+ 2207 => x"80802688",
+ 2208 => x"387080dc",
+ 2209 => x"f80c7153",
+ 2210 => x"72800c84",
+ 2211 => x"3d0d04fd",
+ 2212 => x"3d0d800b",
+ 2213 => x"80cd8008",
+ 2214 => x"54547281",
+ 2215 => x"2e9b3873",
+ 2216 => x"80dcfc0c",
+ 2217 => x"c4803fc2",
+ 2218 => x"d73f80dc",
+ 2219 => x"d0528151",
+ 2220 => x"c5c63f80",
+ 2221 => x"085185bb",
+ 2222 => x"3f7280dc",
+ 2223 => x"fc0cc3e6",
+ 2224 => x"3fc2bd3f",
+ 2225 => x"80dcd052",
+ 2226 => x"8151c5ac",
+ 2227 => x"3f800851",
+ 2228 => x"85a13f00",
+ 2229 => x"ff3900ff",
+ 2230 => x"39f53d0d",
+ 2231 => x"7e6080dc",
+ 2232 => x"fc08705b",
+ 2233 => x"585b5b75",
+ 2234 => x"80c23877",
+ 2235 => x"7a25a138",
+ 2236 => x"771b7033",
+ 2237 => x"7081ff06",
+ 2238 => x"58585975",
+ 2239 => x"8a2e9838",
+ 2240 => x"7681ff06",
+ 2241 => x"51c2fe3f",
+ 2242 => x"81185879",
+ 2243 => x"7824e138",
+ 2244 => x"79800c8d",
+ 2245 => x"3d0d048d",
+ 2246 => x"51c2ea3f",
+ 2247 => x"78337081",
+ 2248 => x"ff065257",
+ 2249 => x"c2df3f81",
+ 2250 => x"1858e039",
+ 2251 => x"79557a54",
+ 2252 => x"7d538552",
+ 2253 => x"8d3dfc05",
+ 2254 => x"51c2873f",
+ 2255 => x"80085684",
+ 2256 => x"ab3f7b80",
+ 2257 => x"080c7580",
+ 2258 => x"0c8d3d0d",
+ 2259 => x"04f63d0d",
+ 2260 => x"7d7f80dc",
+ 2261 => x"fc08705b",
+ 2262 => x"585a5a75",
+ 2263 => x"80c13877",
+ 2264 => x"7925b338",
+ 2265 => x"c1fa3f80",
+ 2266 => x"0881ff06",
+ 2267 => x"708d3270",
+ 2268 => x"30709f2a",
+ 2269 => x"51515757",
+ 2270 => x"768a2e80",
+ 2271 => x"c3387580",
+ 2272 => x"2ebe3877",
+ 2273 => x"1a567676",
+ 2274 => x"347651c1",
+ 2275 => x"f83f8118",
+ 2276 => x"58787824",
+ 2277 => x"cf387756",
+ 2278 => x"75800c8c",
+ 2279 => x"3d0d0478",
+ 2280 => x"5579547c",
+ 2281 => x"5384528c",
+ 2282 => x"3dfc0551",
+ 2283 => x"c1943f80",
+ 2284 => x"085683b8",
+ 2285 => x"3f7a8008",
+ 2286 => x"0c75800c",
+ 2287 => x"8c3d0d04",
+ 2288 => x"771a568a",
+ 2289 => x"76348118",
+ 2290 => x"588d51c1",
+ 2291 => x"b83f8a51",
+ 2292 => x"c1b33f77",
+ 2293 => x"56c239fb",
+ 2294 => x"3d0d80dc",
+ 2295 => x"fc087056",
+ 2296 => x"54738838",
+ 2297 => x"74800c87",
+ 2298 => x"3d0d0477",
+ 2299 => x"53835287",
+ 2300 => x"3dfc0551",
+ 2301 => x"c0cc3f80",
+ 2302 => x"085482f0",
+ 2303 => x"3f758008",
+ 2304 => x"0c73800c",
+ 2305 => x"873d0d04",
+ 2306 => x"fa3d0d80",
+ 2307 => x"dcfc0880",
+ 2308 => x"2ea2387a",
+ 2309 => x"55795478",
+ 2310 => x"53865288",
+ 2311 => x"3dfc0551",
+ 2312 => x"c0a03f80",
+ 2313 => x"085682c4",
+ 2314 => x"3f768008",
+ 2315 => x"0c75800c",
+ 2316 => x"883d0d04",
+ 2317 => x"82b63f9d",
+ 2318 => x"0b80080c",
+ 2319 => x"ff0b800c",
+ 2320 => x"883d0d04",
+ 2321 => x"fb3d0d77",
+ 2322 => x"79565680",
+ 2323 => x"70545473",
+ 2324 => x"75259f38",
+ 2325 => x"74101010",
+ 2326 => x"f8055272",
+ 2327 => x"16703370",
+ 2328 => x"742b7607",
+ 2329 => x"8116f816",
+ 2330 => x"56565651",
+ 2331 => x"51747324",
+ 2332 => x"ea387380",
+ 2333 => x"0c873d0d",
+ 2334 => x"04fc3d0d",
+ 2335 => x"76785555",
+ 2336 => x"bc538052",
+ 2337 => x"7351f5ca",
+ 2338 => x"3f845274",
+ 2339 => x"51ffb53f",
+ 2340 => x"80087423",
+ 2341 => x"84528415",
+ 2342 => x"51ffa93f",
+ 2343 => x"80088215",
+ 2344 => x"23845288",
+ 2345 => x"1551ff9c",
+ 2346 => x"3f800884",
+ 2347 => x"150c8452",
+ 2348 => x"8c1551ff",
+ 2349 => x"8f3f8008",
+ 2350 => x"88152384",
+ 2351 => x"52901551",
+ 2352 => x"ff823f80",
+ 2353 => x"088a1523",
+ 2354 => x"84529415",
+ 2355 => x"51fef53f",
+ 2356 => x"80088c15",
+ 2357 => x"23845298",
+ 2358 => x"1551fee8",
+ 2359 => x"3f80088e",
+ 2360 => x"15238852",
+ 2361 => x"9c1551fe",
+ 2362 => x"db3f8008",
+ 2363 => x"90150c86",
+ 2364 => x"3d0d04e9",
+ 2365 => x"3d0d6a80",
+ 2366 => x"dcfc0857",
+ 2367 => x"57759338",
+ 2368 => x"80c0800b",
+ 2369 => x"84180c75",
+ 2370 => x"ac180c75",
+ 2371 => x"800c993d",
+ 2372 => x"0d04893d",
+ 2373 => x"70556a54",
+ 2374 => x"558a5299",
+ 2375 => x"3dffbc05",
+ 2376 => x"51ffbe9e",
+ 2377 => x"3f800877",
+ 2378 => x"53755256",
+ 2379 => x"fecb3fbc",
+ 2380 => x"3f778008",
+ 2381 => x"0c75800c",
+ 2382 => x"993d0d04",
+ 2383 => x"fc3d0d81",
+ 2384 => x"5480dcfc",
+ 2385 => x"08883873",
+ 2386 => x"800c863d",
+ 2387 => x"0d047653",
+ 2388 => x"97b95286",
+ 2389 => x"3dfc0551",
+ 2390 => x"ffbde73f",
+ 2391 => x"8008548c",
+ 2392 => x"3f748008",
+ 2393 => x"0c73800c",
+ 2394 => x"863d0d04",
+ 2395 => x"80cd8c08",
+ 2396 => x"800c04f7",
+ 2397 => x"3d0d7b80",
+ 2398 => x"cd8c0882",
+ 2399 => x"c811085a",
+ 2400 => x"545a7780",
+ 2401 => x"2e80da38",
+ 2402 => x"81881884",
+ 2403 => x"1908ff05",
+ 2404 => x"81712b59",
+ 2405 => x"55598074",
+ 2406 => x"2480ea38",
+ 2407 => x"807424b5",
+ 2408 => x"3873822b",
+ 2409 => x"78118805",
+ 2410 => x"56568180",
+ 2411 => x"19087706",
+ 2412 => x"5372802e",
+ 2413 => x"b6387816",
+ 2414 => x"70085353",
+ 2415 => x"79517408",
+ 2416 => x"53722dff",
+ 2417 => x"14fc17fc",
+ 2418 => x"1779812c",
+ 2419 => x"5a575754",
+ 2420 => x"738025d6",
+ 2421 => x"38770858",
+ 2422 => x"77ffad38",
+ 2423 => x"80cd8c08",
+ 2424 => x"53bc1308",
+ 2425 => x"a5387951",
+ 2426 => x"f9e93f74",
+ 2427 => x"0853722d",
+ 2428 => x"ff14fc17",
+ 2429 => x"fc177981",
+ 2430 => x"2c5a5757",
+ 2431 => x"54738025",
+ 2432 => x"ffa838d1",
+ 2433 => x"398057ff",
+ 2434 => x"93397251",
+ 2435 => x"bc130853",
+ 2436 => x"722d7951",
+ 2437 => x"f9bd3fff",
+ 2438 => x"3d0d80dc",
+ 2439 => x"d80bfc05",
+ 2440 => x"70085252",
+ 2441 => x"70ff2e91",
+ 2442 => x"38702dfc",
+ 2443 => x"12700852",
+ 2444 => x"5270ff2e",
+ 2445 => x"098106f1",
+ 2446 => x"38833d0d",
+ 2447 => x"0404ffbd",
+ 2448 => x"d23f0400",
+ 2449 => x"00000040",
+ 2450 => x"48656c6c",
+ 2451 => x"6f20776f",
+ 2452 => x"726c6421",
+ 2453 => x"00000000",
+ 2454 => x"0a000000",
+ 2455 => x"43000000",
+ 2456 => x"64756d6d",
+ 2457 => x"792e6578",
+ 2458 => x"65000000",
+ 2459 => x"00ffffff",
+ 2460 => x"ff00ffff",
+ 2461 => x"ffff00ff",
+ 2462 => x"ffffff00",
+ 2463 => x"00000000",
+ 2464 => x"00000000",
+ 2465 => x"00000000",
+ 2466 => x"00002e60",
+ 2467 => x"00002690",
+ 2468 => x"00000000",
+ 2469 => x"000028f8",
+ 2470 => x"00002954",
+ 2471 => x"000029b0",
+ 2472 => x"00000000",
+ 2473 => x"00000000",
+ 2474 => x"00000000",
+ 2475 => x"00000000",
+ 2476 => x"00000000",
+ 2477 => x"00000000",
+ 2478 => x"00000000",
+ 2479 => x"00000000",
+ 2480 => x"00000000",
+ 2481 => x"0000265c",
+ 2482 => x"00000000",
+ 2483 => x"00000000",
+ 2484 => x"00000000",
+ 2485 => x"00000000",
+ 2486 => x"00000000",
+ 2487 => x"00000000",
+ 2488 => x"00000000",
+ 2489 => x"00000000",
+ 2490 => x"00000000",
+ 2491 => x"00000000",
+ 2492 => x"00000000",
+ 2493 => x"00000000",
+ 2494 => x"00000000",
+ 2495 => x"00000000",
+ 2496 => x"00000000",
+ 2497 => x"00000000",
+ 2498 => x"00000000",
+ 2499 => x"00000000",
+ 2500 => x"00000000",
+ 2501 => x"00000000",
+ 2502 => x"00000000",
+ 2503 => x"00000000",
+ 2504 => x"00000000",
+ 2505 => x"00000000",
+ 2506 => x"00000000",
+ 2507 => x"00000000",
+ 2508 => x"00000000",
+ 2509 => x"00000000",
+ 2510 => x"00000001",
+ 2511 => x"330eabcd",
+ 2512 => x"1234e66d",
+ 2513 => x"deec0005",
+ 2514 => x"000b0000",
+ 2515 => x"00000000",
+ 2516 => x"00000000",
+ 2517 => x"00000000",
+ 2518 => x"00000000",
+ 2519 => x"00000000",
+ 2520 => x"00000000",
+ 2521 => x"00000000",
+ 2522 => x"00000000",
+ 2523 => x"00000000",
+ 2524 => x"00000000",
+ 2525 => x"00000000",
+ 2526 => x"00000000",
+ 2527 => x"00000000",
+ 2528 => x"00000000",
+ 2529 => x"00000000",
+ 2530 => x"00000000",
+ 2531 => x"00000000",
+ 2532 => x"00000000",
+ 2533 => x"00000000",
+ 2534 => x"00000000",
+ 2535 => x"00000000",
+ 2536 => x"00000000",
+ 2537 => x"00000000",
+ 2538 => x"00000000",
+ 2539 => x"00000000",
+ 2540 => x"00000000",
+ 2541 => x"00000000",
+ 2542 => x"00000000",
+ 2543 => x"00000000",
+ 2544 => x"00000000",
+ 2545 => x"00000000",
+ 2546 => x"00000000",
+ 2547 => x"00000000",
+ 2548 => x"00000000",
+ 2549 => x"00000000",
+ 2550 => x"00000000",
+ 2551 => x"00000000",
+ 2552 => x"00000000",
+ 2553 => x"00000000",
+ 2554 => x"00000000",
+ 2555 => x"00000000",
+ 2556 => x"00000000",
+ 2557 => x"00000000",
+ 2558 => x"00000000",
+ 2559 => x"00000000",
+ 2560 => x"00000000",
+ 2561 => x"00000000",
+ 2562 => x"00000000",
+ 2563 => x"00000000",
+ 2564 => x"00000000",
+ 2565 => x"00000000",
+ 2566 => x"00000000",
+ 2567 => x"00000000",
+ 2568 => x"00000000",
+ 2569 => x"00000000",
+ 2570 => x"00000000",
+ 2571 => x"00000000",
+ 2572 => x"00000000",
+ 2573 => x"00000000",
+ 2574 => x"00000000",
+ 2575 => x"00000000",
+ 2576 => x"00000000",
+ 2577 => x"00000000",
+ 2578 => x"00000000",
+ 2579 => x"00000000",
+ 2580 => x"00000000",
+ 2581 => x"00000000",
+ 2582 => x"00000000",
+ 2583 => x"00000000",
+ 2584 => x"00000000",
+ 2585 => x"00000000",
+ 2586 => x"00000000",
+ 2587 => x"00000000",
+ 2588 => x"00000000",
+ 2589 => x"00000000",
+ 2590 => x"00000000",
+ 2591 => x"00000000",
+ 2592 => x"00000000",
+ 2593 => x"00000000",
+ 2594 => x"00000000",
+ 2595 => x"00000000",
+ 2596 => x"00000000",
+ 2597 => x"00000000",
+ 2598 => x"00000000",
+ 2599 => x"00000000",
+ 2600 => x"00000000",
+ 2601 => x"00000000",
+ 2602 => x"00000000",
+ 2603 => x"00000000",
+ 2604 => x"00000000",
+ 2605 => x"00000000",
+ 2606 => x"00000000",
+ 2607 => x"00000000",
+ 2608 => x"00000000",
+ 2609 => x"00000000",
+ 2610 => x"00000000",
+ 2611 => x"00000000",
+ 2612 => x"00000000",
+ 2613 => x"00000000",
+ 2614 => x"00000000",
+ 2615 => x"00000000",
+ 2616 => x"00000000",
+ 2617 => x"00000000",
+ 2618 => x"00000000",
+ 2619 => x"00000000",
+ 2620 => x"00000000",
+ 2621 => x"00000000",
+ 2622 => x"00000000",
+ 2623 => x"00000000",
+ 2624 => x"00000000",
+ 2625 => x"00000000",
+ 2626 => x"00000000",
+ 2627 => x"00000000",
+ 2628 => x"00000000",
+ 2629 => x"00000000",
+ 2630 => x"00000000",
+ 2631 => x"00000000",
+ 2632 => x"00000000",
+ 2633 => x"00000000",
+ 2634 => x"00000000",
+ 2635 => x"00000000",
+ 2636 => x"00000000",
+ 2637 => x"00000000",
+ 2638 => x"00000000",
+ 2639 => x"00000000",
+ 2640 => x"00000000",
+ 2641 => x"00000000",
+ 2642 => x"00000000",
+ 2643 => x"00000000",
+ 2644 => x"00000000",
+ 2645 => x"00000000",
+ 2646 => x"00000000",
+ 2647 => x"00000000",
+ 2648 => x"00000000",
+ 2649 => x"00000000",
+ 2650 => x"00000000",
+ 2651 => x"00000000",
+ 2652 => x"00000000",
+ 2653 => x"00000000",
+ 2654 => x"00000000",
+ 2655 => x"00000000",
+ 2656 => x"00000000",
+ 2657 => x"00000000",
+ 2658 => x"00000000",
+ 2659 => x"00000000",
+ 2660 => x"00000000",
+ 2661 => x"00000000",
+ 2662 => x"00000000",
+ 2663 => x"00000000",
+ 2664 => x"00000000",
+ 2665 => x"00000000",
+ 2666 => x"00000000",
+ 2667 => x"00000000",
+ 2668 => x"00000000",
+ 2669 => x"00000000",
+ 2670 => x"00000000",
+ 2671 => x"00000000",
+ 2672 => x"00000000",
+ 2673 => x"00000000",
+ 2674 => x"00000000",
+ 2675 => x"00000000",
+ 2676 => x"00000000",
+ 2677 => x"00000000",
+ 2678 => x"00000000",
+ 2679 => x"00000000",
+ 2680 => x"00000000",
+ 2681 => x"00000000",
+ 2682 => x"00000000",
+ 2683 => x"00000000",
+ 2684 => x"00000000",
+ 2685 => x"00000000",
+ 2686 => x"00000000",
+ 2687 => x"00000000",
+ 2688 => x"00000000",
+ 2689 => x"00000000",
+ 2690 => x"00000000",
+ 2691 => x"00000000",
+ 2692 => x"00000000",
+ 2693 => x"00000000",
+ 2694 => x"00000000",
+ 2695 => x"00000000",
+ 2696 => x"00000000",
+ 2697 => x"00000000",
+ 2698 => x"00000000",
+ 2699 => x"00000000",
+ 2700 => x"00000000",
+ 2701 => x"00000000",
+ 2702 => x"00000000",
+ 2703 => x"ffffffff",
+ 2704 => x"00000000",
+ 2705 => x"00020000",
+ 2706 => x"00000000",
+ 2707 => x"00000000",
+ 2708 => x"00002a48",
+ 2709 => x"00002a48",
+ 2710 => x"00002a50",
+ 2711 => x"00002a50",
+ 2712 => x"00002a58",
+ 2713 => x"00002a58",
+ 2714 => x"00002a60",
+ 2715 => x"00002a60",
+ 2716 => x"00002a68",
+ 2717 => x"00002a68",
+ 2718 => x"00002a70",
+ 2719 => x"00002a70",
+ 2720 => x"00002a78",
+ 2721 => x"00002a78",
+ 2722 => x"00002a80",
+ 2723 => x"00002a80",
+ 2724 => x"00002a88",
+ 2725 => x"00002a88",
+ 2726 => x"00002a90",
+ 2727 => x"00002a90",
+ 2728 => x"00002a98",
+ 2729 => x"00002a98",
+ 2730 => x"00002aa0",
+ 2731 => x"00002aa0",
+ 2732 => x"00002aa8",
+ 2733 => x"00002aa8",
+ 2734 => x"00002ab0",
+ 2735 => x"00002ab0",
+ 2736 => x"00002ab8",
+ 2737 => x"00002ab8",
+ 2738 => x"00002ac0",
+ 2739 => x"00002ac0",
+ 2740 => x"00002ac8",
+ 2741 => x"00002ac8",
+ 2742 => x"00002ad0",
+ 2743 => x"00002ad0",
+ 2744 => x"00002ad8",
+ 2745 => x"00002ad8",
+ 2746 => x"00002ae0",
+ 2747 => x"00002ae0",
+ 2748 => x"00002ae8",
+ 2749 => x"00002ae8",
+ 2750 => x"00002af0",
+ 2751 => x"00002af0",
+ 2752 => x"00002af8",
+ 2753 => x"00002af8",
+ 2754 => x"00002b00",
+ 2755 => x"00002b00",
+ 2756 => x"00002b08",
+ 2757 => x"00002b08",
+ 2758 => x"00002b10",
+ 2759 => x"00002b10",
+ 2760 => x"00002b18",
+ 2761 => x"00002b18",
+ 2762 => x"00002b20",
+ 2763 => x"00002b20",
+ 2764 => x"00002b28",
+ 2765 => x"00002b28",
+ 2766 => x"00002b30",
+ 2767 => x"00002b30",
+ 2768 => x"00002b38",
+ 2769 => x"00002b38",
+ 2770 => x"00002b40",
+ 2771 => x"00002b40",
+ 2772 => x"00002b48",
+ 2773 => x"00002b48",
+ 2774 => x"00002b50",
+ 2775 => x"00002b50",
+ 2776 => x"00002b58",
+ 2777 => x"00002b58",
+ 2778 => x"00002b60",
+ 2779 => x"00002b60",
+ 2780 => x"00002b68",
+ 2781 => x"00002b68",
+ 2782 => x"00002b70",
+ 2783 => x"00002b70",
+ 2784 => x"00002b78",
+ 2785 => x"00002b78",
+ 2786 => x"00002b80",
+ 2787 => x"00002b80",
+ 2788 => x"00002b88",
+ 2789 => x"00002b88",
+ 2790 => x"00002b90",
+ 2791 => x"00002b90",
+ 2792 => x"00002b98",
+ 2793 => x"00002b98",
+ 2794 => x"00002ba0",
+ 2795 => x"00002ba0",
+ 2796 => x"00002ba8",
+ 2797 => x"00002ba8",
+ 2798 => x"00002bb0",
+ 2799 => x"00002bb0",
+ 2800 => x"00002bb8",
+ 2801 => x"00002bb8",
+ 2802 => x"00002bc0",
+ 2803 => x"00002bc0",
+ 2804 => x"00002bc8",
+ 2805 => x"00002bc8",
+ 2806 => x"00002bd0",
+ 2807 => x"00002bd0",
+ 2808 => x"00002bd8",
+ 2809 => x"00002bd8",
+ 2810 => x"00002be0",
+ 2811 => x"00002be0",
+ 2812 => x"00002be8",
+ 2813 => x"00002be8",
+ 2814 => x"00002bf0",
+ 2815 => x"00002bf0",
+ 2816 => x"00002bf8",
+ 2817 => x"00002bf8",
+ 2818 => x"00002c00",
+ 2819 => x"00002c00",
+ 2820 => x"00002c08",
+ 2821 => x"00002c08",
+ 2822 => x"00002c10",
+ 2823 => x"00002c10",
+ 2824 => x"00002c18",
+ 2825 => x"00002c18",
+ 2826 => x"00002c20",
+ 2827 => x"00002c20",
+ 2828 => x"00002c28",
+ 2829 => x"00002c28",
+ 2830 => x"00002c30",
+ 2831 => x"00002c30",
+ 2832 => x"00002c38",
+ 2833 => x"00002c38",
+ 2834 => x"00002c40",
+ 2835 => x"00002c40",
+ 2836 => x"00002c48",
+ 2837 => x"00002c48",
+ 2838 => x"00002c50",
+ 2839 => x"00002c50",
+ 2840 => x"00002c58",
+ 2841 => x"00002c58",
+ 2842 => x"00002c60",
+ 2843 => x"00002c60",
+ 2844 => x"00002c68",
+ 2845 => x"00002c68",
+ 2846 => x"00002c70",
+ 2847 => x"00002c70",
+ 2848 => x"00002c78",
+ 2849 => x"00002c78",
+ 2850 => x"00002c80",
+ 2851 => x"00002c80",
+ 2852 => x"00002c88",
+ 2853 => x"00002c88",
+ 2854 => x"00002c90",
+ 2855 => x"00002c90",
+ 2856 => x"00002c98",
+ 2857 => x"00002c98",
+ 2858 => x"00002ca0",
+ 2859 => x"00002ca0",
+ 2860 => x"00002ca8",
+ 2861 => x"00002ca8",
+ 2862 => x"00002cb0",
+ 2863 => x"00002cb0",
+ 2864 => x"00002cb8",
+ 2865 => x"00002cb8",
+ 2866 => x"00002cc0",
+ 2867 => x"00002cc0",
+ 2868 => x"00002cc8",
+ 2869 => x"00002cc8",
+ 2870 => x"00002cd0",
+ 2871 => x"00002cd0",
+ 2872 => x"00002cd8",
+ 2873 => x"00002cd8",
+ 2874 => x"00002ce0",
+ 2875 => x"00002ce0",
+ 2876 => x"00002ce8",
+ 2877 => x"00002ce8",
+ 2878 => x"00002cf0",
+ 2879 => x"00002cf0",
+ 2880 => x"00002cf8",
+ 2881 => x"00002cf8",
+ 2882 => x"00002d00",
+ 2883 => x"00002d00",
+ 2884 => x"00002d08",
+ 2885 => x"00002d08",
+ 2886 => x"00002d10",
+ 2887 => x"00002d10",
+ 2888 => x"00002d18",
+ 2889 => x"00002d18",
+ 2890 => x"00002d20",
+ 2891 => x"00002d20",
+ 2892 => x"00002d28",
+ 2893 => x"00002d28",
+ 2894 => x"00002d30",
+ 2895 => x"00002d30",
+ 2896 => x"00002d38",
+ 2897 => x"00002d38",
+ 2898 => x"00002d40",
+ 2899 => x"00002d40",
+ 2900 => x"00002d48",
+ 2901 => x"00002d48",
+ 2902 => x"00002d50",
+ 2903 => x"00002d50",
+ 2904 => x"00002d58",
+ 2905 => x"00002d58",
+ 2906 => x"00002d60",
+ 2907 => x"00002d60",
+ 2908 => x"00002d68",
+ 2909 => x"00002d68",
+ 2910 => x"00002d70",
+ 2911 => x"00002d70",
+ 2912 => x"00002d78",
+ 2913 => x"00002d78",
+ 2914 => x"00002d80",
+ 2915 => x"00002d80",
+ 2916 => x"00002d88",
+ 2917 => x"00002d88",
+ 2918 => x"00002d90",
+ 2919 => x"00002d90",
+ 2920 => x"00002d98",
+ 2921 => x"00002d98",
+ 2922 => x"00002da0",
+ 2923 => x"00002da0",
+ 2924 => x"00002da8",
+ 2925 => x"00002da8",
+ 2926 => x"00002db0",
+ 2927 => x"00002db0",
+ 2928 => x"00002db8",
+ 2929 => x"00002db8",
+ 2930 => x"00002dc0",
+ 2931 => x"00002dc0",
+ 2932 => x"00002dc8",
+ 2933 => x"00002dc8",
+ 2934 => x"00002dd0",
+ 2935 => x"00002dd0",
+ 2936 => x"00002dd8",
+ 2937 => x"00002dd8",
+ 2938 => x"00002de0",
+ 2939 => x"00002de0",
+ 2940 => x"00002de8",
+ 2941 => x"00002de8",
+ 2942 => x"00002df0",
+ 2943 => x"00002df0",
+ 2944 => x"00002df8",
+ 2945 => x"00002df8",
+ 2946 => x"00002e00",
+ 2947 => x"00002e00",
+ 2948 => x"00002e08",
+ 2949 => x"00002e08",
+ 2950 => x"00002e10",
+ 2951 => x"00002e10",
+ 2952 => x"00002e18",
+ 2953 => x"00002e18",
+ 2954 => x"00002e20",
+ 2955 => x"00002e20",
+ 2956 => x"00002e28",
+ 2957 => x"00002e28",
+ 2958 => x"00002e30",
+ 2959 => x"00002e30",
+ 2960 => x"00002e38",
+ 2961 => x"00002e38",
+ 2962 => x"00002e40",
+ 2963 => x"00002e40",
+ 2964 => x"00002660",
+ 2965 => x"ffffffff",
+ 2966 => x"00000000",
+ 2967 => x"ffffffff",
+ 2968 => x"00000000",
+ 2969 => x"00000000",
+
+others => x"00000000"
+);
+begin
+ do_port_a:
+ process (clk_i)
+ variable iaddr : integer;
+ begin
+ if rising_edge(clk_i) then
+ if (a_we_i='1') and (b_we_i='1') and (a_addr_i=b_addr_i) and (a_write_i/=b_write_i) then
+ report "DualPortRAM write collision" severity failure;
+ end if;
+ iaddr:=to_integer(a_addr_i);
+ if a_we_i='1' then
+ ram(iaddr):=a_write_i;
+ a_read_o <= a_write_i;
+ else
+ a_read_o <= ram(iaddr);
+ end if;
+ end if;
+ end process do_port_a;
+
+ do_port_b:
+ process (clk_i)
+ variable iaddr : integer;
+ begin
+ if rising_edge(clk_i) then
+ iaddr:=to_integer(b_addr_i);
+ if b_we_i='1' then
+ ram(iaddr):=b_write_i;
+ b_read_o <= b_write_i;
+ else
+ b_read_o <= ram(iaddr);
+ end if;
+ end if;
+ end process do_port_b;
+end architecture DualPort_Arch; -- Entity: DualPortRAM
diff --git a/zpu/hdl/zealot/roms/rom_pkg.vhdl b/zpu/hdl/zealot/roms/rom_pkg.vhdl
new file mode 100644
index 0000000..c5a4161
--- /dev/null
+++ b/zpu/hdl/zealot/roms/rom_pkg.vhdl
@@ -0,0 +1,80 @@
+------------------------------------------------------------------------------
+---- ----
+---- ZPU memories package ----
+---- ----
+---- http://www.opencores.org/ ----
+---- ----
+---- Description: ----
+---- This is a package with the memories used for the ZPU core. ----
+---- ----
+---- To Do: ----
+---- - ----
+---- ----
+---- Author: ----
+---- - Salvador E. Tropea, salvador inti.gob.ar ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
+---- ----
+---- Distributed under the BSD license ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Design unit: zpu_memory (Package) ----
+---- File name: rom_pkg.vhdl (template used) ----
+---- Note: None ----
+---- Limitations: None known ----
+---- Errors: None known ----
+---- Library: work ----
+---- Dependencies: IEEE.std_logic_1164 ----
+---- IEEE.numeric_std ----
+---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
+---- Language: VHDL ----
+---- Wishbone: No ----
+---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
+---- Text editor: SETEdit 0.5.x ----
+---- ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+package zpu_memory is
+ component DualPortRAM is
+ generic(
+ WORD_SIZE : integer:=32; -- Word Size 16/32
+ BYTE_BITS : integer:=2; -- Bits used to address bytes
+ BRAM_W : integer:=15); -- Address Width
+ port(
+ clk_i : in std_logic;
+ -- Port A
+ a_we_i : in std_logic;
+ a_addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS);
+ a_write_i : in unsigned(WORD_SIZE-1 downto 0);
+ a_read_o : out unsigned(WORD_SIZE-1 downto 0);
+ -- Port B
+ b_we_i : in std_logic;
+ b_addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS);
+ b_write_i : in unsigned(WORD_SIZE-1 downto 0);
+ b_read_o : out unsigned(WORD_SIZE-1 downto 0));
+ end component DualPortRAM;
+
+ component SinglePortRAM is
+ generic(
+ WORD_SIZE : integer:=32; -- Word Size 16/32
+ BYTE_BITS : integer:=2; -- Bits used to address bytes
+ BRAM_W : integer:=15); -- Address Width
+ port(
+ clk_i : in std_logic;
+ we_i : in std_logic;
+ re_i : in std_logic;
+ addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS);
+ write_i : in unsigned(WORD_SIZE-1 downto 0);
+ read_o : out unsigned(WORD_SIZE-1 downto 0);
+ busy_o : out std_logic);
+ end component SinglePortRAM;
+end package zpu_memory;
diff --git a/zpu/hdl/zealot/testbenches/dmips_med1_tb.vhdl b/zpu/hdl/zealot/testbenches/dmips_med1_tb.vhdl
new file mode 100644
index 0000000..8bdcdd3
--- /dev/null
+++ b/zpu/hdl/zealot/testbenches/dmips_med1_tb.vhdl
@@ -0,0 +1,134 @@
+------------------------------------------------------------------------------
+---- ----
+---- Testbench for the ZPU Medium connection to the FPGA ----
+---- ----
+---- http://www.opencores.org/ ----
+---- ----
+---- Description: ----
+---- This is a testbench to simulate the ZPU_Med1 core as used in the ----
+---- dmips_med1.vhdl ----
+---- ----
+---- To Do: ----
+---- - ----
+---- ----
+---- Author: ----
+---- - Salvador E. Tropea, salvador inti.gob.ar ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
+---- ----
+---- Distributed under the BSD license ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Design unit: DMIPS_Med1_TB(Behave) (Entity and architecture) ----
+---- File name: dmips_med1_tb.vhdl ----
+---- Note: None ----
+---- Limitations: None known ----
+---- Errors: None known ----
+---- Library: work ----
+---- Dependencies: IEEE.std_logic_1164 ----
+---- IEEE.numeric_std ----
+---- zpu.zpupkg ----
+---- zpu.txt_util ----
+---- work.zpu_memory ----
+---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
+---- Language: VHDL ----
+---- Wishbone: No ----
+---- Synthesis tools: N/A ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
+---- Text editor: SETEdit 0.5.x ----
+---- ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library zpu;
+use zpu.zpupkg.all;
+use zpu.txt_util.all;
+
+library work;
+use work.zpu_memory.all;
+
+entity DMIPS_Med1_TB is
+end entity DMIPS_Med1_TB;
+
+architecture Behave of DMIPS_Med1_TB is
+ constant WORD_SIZE : natural:=32; -- 32 bits data path
+ constant ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O
+ constant BRAM_W : natural:=15; -- 15 bits RAM space=32 kB
+ constant D_CARE_VAL : std_logic:='0'; -- Fill value
+ constant CLK_FREQ : positive:=50; -- 50 MHz clock
+ constant CLK_S_PER : time:=1 us/(2.0*real(CLK_FREQ)); -- Clock semi period
+ constant BRATE : positive:=115200;
+
+ component ZPU_Med1 is
+ generic(
+ WORD_SIZE : natural:=32; -- 32 bits data path
+ D_CARE_VAL : std_logic:='X'; -- Fill value
+ CLK_FREQ : positive:=50; -- 50 MHz clock
+ BRATE : positive:=9600; -- RS232 baudrate
+ ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O
+ BRAM_W : natural:=15); -- 15 bits RAM space=32 kB
+ port(
+ clk_i : in std_logic; -- CPU clock
+ rst_i : in std_logic; -- Reset
+ break_o : out std_logic; -- Break executed
+ dbg_o : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o : out std_logic; -- UART Tx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end component ZPU_Med1;
+
+ signal clk : std_logic;
+ signal reset : std_logic:='1';
+
+ signal break : std_logic;
+ signal dbg : zpu_dbgo_t; -- Debug info
+ signal rs232_tx : std_logic;
+ signal rs232_rx : std_logic;
+begin
+ zpu : ZPU_Med1
+ generic map(
+ WORD_SIZE => WORD_SIZE, D_CARE_VAL => D_CARE_VAL,
+ CLK_FREQ => CLK_FREQ, BRATE => BRATE, ADDR_W => ADDR_W,
+ BRAM_W => BRAM_W)
+ port map(
+ clk_i => clk, rst_i => reset, rs232_tx_o => rs232_tx,
+ rs232_rx_i => rs232_rx, break_o => break, dbg_o => dbg,
+ gpio_in => (others => '0'));
+
+ trace_mod : Trace
+ generic map(
+ ADDR_W => ADDR_W, WORD_SIZE => WORD_SIZE,
+ LOG_FILE => "dmips_med1.log")
+ port map(
+ clk_i => clk, dbg_i => dbg, stop_i => break, busy_i => '0');
+
+ do_clock:
+ process
+ begin
+ clk <= '0';
+ wait for CLK_S_PER;
+ clk <= '1';
+ wait for CLK_S_PER;
+ if break='1' then
+ print("* Break asserted, end of test");
+ wait;
+ end if;
+ end process do_clock;
+
+ do_reset:
+ process
+ begin
+ wait until rising_edge(clk);
+ reset <= '0';
+ end process do_reset;
+end architecture Behave; -- Entity: DMIPS_Med1_TB
diff --git a/zpu/hdl/zealot/testbenches/small1_tb.vhdl b/zpu/hdl/zealot/testbenches/small1_tb.vhdl
new file mode 100644
index 0000000..a77e5bc
--- /dev/null
+++ b/zpu/hdl/zealot/testbenches/small1_tb.vhdl
@@ -0,0 +1,134 @@
+------------------------------------------------------------------------------
+---- ----
+---- Testbench for the ZPU Small connection to the FPGA ----
+---- ----
+---- http://www.opencores.org/ ----
+---- ----
+---- Description: ----
+---- This is a testbench to simulate the ZPU_Small1 core as used in the ----
+---- *_small1.vhdl ----
+---- ----
+---- To Do: ----
+---- - ----
+---- ----
+---- Author: ----
+---- - Salvador E. Tropea, salvador inti.gob.ar ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
+---- ----
+---- Distributed under the BSD license ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Design unit: Small1_TB(Behave) (Entity and architecture) ----
+---- File name: small1_tb.vhdl ----
+---- Note: None ----
+---- Limitations: None known ----
+---- Errors: None known ----
+---- Library: work ----
+---- Dependencies: IEEE.std_logic_1164 ----
+---- IEEE.numeric_std ----
+---- zpu.zpupkg ----
+---- zpu.txt_util ----
+---- work.zpu_memory ----
+---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
+---- Language: VHDL ----
+---- Wishbone: No ----
+---- Synthesis tools: N/A ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
+---- Text editor: SETEdit 0.5.x ----
+---- ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library zpu;
+use zpu.zpupkg.all;
+use zpu.txt_util.all;
+
+library work;
+use work.zpu_memory.all;
+
+entity Small1_TB is
+end entity Small1_TB;
+
+architecture Behave of Small1_TB is
+ constant WORD_SIZE : natural:=32; -- 32 bits data path
+ constant ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O
+ constant BRAM_W : natural:=15; -- 15 bits RAM space=32 kB
+ constant D_CARE_VAL : std_logic:='0'; -- Fill value
+ constant CLK_FREQ : positive:=50; -- 50 MHz clock
+ constant CLK_S_PER : time:=1 us/(2.0*real(CLK_FREQ)); -- Clock semi period
+ constant BRATE : positive:=115200;
+
+ component ZPU_Small1 is
+ generic(
+ WORD_SIZE : natural:=32; -- 32 bits data path
+ D_CARE_VAL : std_logic:='0'; -- Fill value
+ CLK_FREQ : positive:=50; -- 50 MHz clock
+ BRATE : positive:=115200; -- RS232 baudrate
+ ADDR_W : natural:=16; -- 16 bits address space=64 kB, 32 kB I/O
+ BRAM_W : natural:=15); -- 15 bits RAM space=32 kB
+ port(
+ clk_i : in std_logic; -- CPU clock
+ rst_i : in std_logic; -- Reset
+ break_o : out std_logic; -- Break executed
+ dbg_o : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o : out std_logic; -- UART Tx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end component ZPU_Small1;
+
+ signal clk : std_logic;
+ signal reset : std_logic:='1';
+
+ signal break : std_logic;
+ signal dbg : zpu_dbgo_t; -- Debug info
+ signal rs232_tx : std_logic;
+ signal rs232_rx : std_logic;
+begin
+ zpu : ZPU_Small1
+ generic map(
+ WORD_SIZE => WORD_SIZE, D_CARE_VAL => D_CARE_VAL,
+ CLK_FREQ => CLK_FREQ, BRATE => BRATE, ADDR_W => ADDR_W,
+ BRAM_W => BRAM_W)
+ port map(
+ clk_i => clk, rst_i => reset, rs232_tx_o => rs232_tx,
+ rs232_rx_i => rs232_rx, break_o => break, dbg_o => dbg,
+ gpio_in => (others => '0'));
+
+ trace_mod : Trace
+ generic map(
+ ADDR_W => ADDR_W, WORD_SIZE => WORD_SIZE,
+ LOG_FILE => "small1_trace.log")
+ port map(
+ clk_i => clk, dbg_i => dbg, stop_i => break, busy_i => '0');
+
+ do_clock:
+ process
+ begin
+ clk <= '0';
+ wait for CLK_S_PER;
+ clk <= '1';
+ wait for CLK_S_PER;
+ if break='1' then
+ print("* Break asserted, end of test");
+ wait;
+ end if;
+ end process do_clock;
+
+ do_reset:
+ process
+ begin
+ wait until rising_edge(clk);
+ reset <= '0';
+ end process do_reset;
+end architecture Behave; -- Entity: Small1_TB
diff --git a/zpu/hdl/zealot/zpu_medium.vhdl b/zpu/hdl/zealot/zpu_medium.vhdl
new file mode 100644
index 0000000..47950fe
--- /dev/null
+++ b/zpu/hdl/zealot/zpu_medium.vhdl
@@ -0,0 +1,948 @@
+------------------------------------------------------------------------------
+---- ----
+---- ZPU Medium ----
+---- ----
+---- http://www.opencores.org/ ----
+---- ----
+---- Description: ----
+---- ZPU is a 32 bits small stack cpu. This is the medium size version. ----
+---- Supports external memories. ----
+---- ----
+---- To Do: ----
+---- - ----
+---- ----
+---- Author: ----
+---- - Øyvind Harboe, oyvind.harboe zylin.com ----
+---- - Salvador E. Tropea, salvador inti.gob.ar ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
+---- ----
+---- Distributed under the BSD license ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Design unit: ZPUMediumCore(Behave) (Entity and architecture) ----
+---- File name: zpu_medium.vhdl ----
+---- Note: None ----
+---- Limitations: None known ----
+---- Errors: None known ----
+---- Library: zpu ----
+---- Dependencies: IEEE.std_logic_1164 ----
+---- IEEE.numeric_std ----
+---- zpu.zpupkg ----
+---- Target FPGA: Spartan 3 (XC3S400-4-FT256) ----
+---- Language: VHDL ----
+---- Wishbone: No ----
+---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
+---- Text editor: SETEdit 0.5.x ----
+---- ----
+------------------------------------------------------------------------------
+--
+-- write_en_o - set to '1' for a single cycle to send off a write request.
+-- data_o is valid only while write_en_o='1'.
+-- read_en_o - set to '1' for a single cycle to send off a read request.
+-- mem_busy_i - It is illegal to send off a read/write request when
+-- mem_busy_i='1'.
+-- Set to '0' when data_i is valid after a read request.
+-- If it goes to '1'(busy), it is on the cycle after read/
+-- write_en_o is '1'.
+-- addr_o - address for read/write request
+-- data_i - read data. Valid only on the cycle after mem_busy_i='0'
+-- after read_en_o='1' for a single cycle.
+-- data_o - data to write
+-- break_o - set to '1' when CPU hits break instruction
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library zpu;
+use zpu.zpupkg.all;
+
+entity ZPUMediumCore is
+ generic(
+ WORD_SIZE : integer:=32; -- 16/32 (2**wordPower)
+ ADDR_W : integer:=16; -- Total address space width (incl. I/O)
+ MEM_W : integer:=15; -- Memory (prog+data+stack) width
+ D_CARE_VAL : std_logic:='X'; -- Value used to fill the unsused bits
+ MULT_PIPE : boolean:=false; -- Pipeline multiplication
+ BINOP_PIPE : integer range 0 to 2:=0; -- Pipeline binary operations (-, =, < and <=)
+ ENA_LEVEL0 : boolean:=true; -- eq, loadb, neqbranch and pushspadd
+ ENA_LEVEL1 : boolean:=true; -- lessthan, ulessthan, mult, storeb, callpcrel and sub
+ ENA_LEVEL2 : boolean:=false; -- lessthanorequal, ulessthanorequal, call and poppcrel
+ ENA_LSHR : boolean:=true; -- lshiftright
+ ENA_IDLE : boolean:=false; -- Enable the enable_i input
+ FAST_FETCH : boolean:=true); -- Merge the st_fetch with the st_execute states
+ port(
+ clk_i : in std_logic; -- CPU Clock
+ reset_i : in std_logic; -- Sync Reset
+ enable_i : in std_logic; -- Hold the CPU (after reset)
+ break_o : out std_logic; -- Break instruction executed
+ dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
+ -- Memory interface
+ mem_busy_i : in std_logic; -- Memory is busy
+ data_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from mem
+ data_o : out unsigned(WORD_SIZE-1 downto 0); -- Data to mem
+ addr_o : out unsigned(ADDR_W-1 downto 0); -- Memory address
+ write_en_o : out std_logic; -- Memory write enable
+ read_en_o : out std_logic); -- Memory read enable
+end entity ZPUMediumCore;
+
+architecture Behave of ZPUMediumCore is
+ constant BYTE_BITS : integer:=WORD_SIZE/16; -- # of bits in a word that addresses bytes
+ constant WORD_BYTES : integer:=WORD_SIZE/OPCODE_W;
+ constant MAX_ADDR_BIT : integer:=ADDR_W-2;
+ -- Stack Pointer initial value: BRAM size-8
+ constant SP_START_1 : unsigned(ADDR_W-1 downto 0):=to_unsigned((2**MEM_W)-8,ADDR_W);
+ constant SP_START : unsigned(ADDR_W-1 downto BYTE_BITS):=
+ SP_START_1(ADDR_W-1 downto BYTE_BITS);
+
+ -- Update [SP+1]. We hold it in b_r, this writes the value to memory.
+ procedure FlushB(signal we : out std_logic;
+ signal addr : out unsigned(ADDR_W-1 downto BYTE_BITS);
+ signal inc_sp : in unsigned(ADDR_W-1 downto BYTE_BITS);
+ signal data : out unsigned(WORD_SIZE-1 downto 0);
+ signal b : in unsigned(WORD_SIZE-1 downto 0)) is
+ begin
+ we <= '1';
+ addr <= inc_sp;
+ data <= b;
+ end procedure FlushB;
+
+ -- Do a simple stack push, it is performed in the internal cache registers,
+ -- not in the real memory.
+ procedure Push(signal sp : inout unsigned(ADDR_W-1 downto BYTE_BITS);
+ signal a : in unsigned(WORD_SIZE-1 downto 0);
+ signal b : out unsigned(WORD_SIZE-1 downto 0)) is
+ begin
+ b <= a; -- Update cache [SP+1]=[SP]
+ sp <= sp-1;
+ end procedure Push;
+
+ -- Do a simple stack pop, it is performed in the internal cache registers,
+ -- not in the real memory.
+ procedure Pop(signal sp : inout unsigned(ADDR_W-1 downto BYTE_BITS);
+ signal a : out unsigned(WORD_SIZE-1 downto 0);
+ signal b : in unsigned(WORD_SIZE-1 downto 0)) is
+ begin
+ a <= b; -- Update cache [SP]=[SP+1]
+ sp <= sp+1;
+ end procedure Pop;
+
+ -- Expand a PC value to WORD_SIZE
+ function ExpandPC(v : unsigned(ADDR_W-1 downto 0)) return unsigned is
+ variable nv : unsigned(WORD_SIZE-1 downto 0);
+ begin
+ nv:=(others => '0');
+ nv(ADDR_W-1 downto 0):=v;
+ return nv;
+ end function ExpandPC;
+
+ -- Program counter
+ signal pc_r : unsigned(ADDR_W-1 downto 0):=(others => '0');
+ -- Stack pointer
+ signal sp_r : unsigned(ADDR_W-1 downto BYTE_BITS):=SP_START;
+ -- SP+1, SP+2 and SP-1 are very used, these are shortcuts
+ signal inc_sp : unsigned(ADDR_W-1 downto BYTE_BITS);
+ signal inc_inc_sp : unsigned(ADDR_W-1 downto BYTE_BITS);
+ -- a_r is a cache for the top of the stack [SP]
+ -- Note: as this is a stack CPU this is a very important register.
+ signal a_r : unsigned(WORD_SIZE-1 downto 0);
+ -- b_r is a cache for the next value in the stack [SP+1]
+ signal b_r : unsigned(WORD_SIZE-1 downto 0);
+ signal bin_op_res1_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
+ signal bin_op_res2_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
+ signal mult_res1_r : unsigned(WORD_SIZE-1 downto 0);
+ signal mult_res2_r : unsigned(WORD_SIZE-1 downto 0);
+ signal mult_res3_r : unsigned(WORD_SIZE-1 downto 0);
+ signal mult_a_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
+ signal mult_b_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
+ signal idim_r : std_logic;
+ signal write_en_r : std_logic;
+ signal read_en_r : std_logic;
+ signal addr_r : unsigned(ADDR_W-1 downto BYTE_BITS):=(others => '0');
+ signal fetched_w_r : unsigned(WORD_SIZE-1 downto 0);
+
+ type state_t is(st_load2, st_popped, st_load_sp2, st_load_sp3, st_add_sp2,
+ st_fetch, st_execute, st_decode, st_decode2, st_resync,
+ st_store_sp2, st_resync2, st_resync3, st_loadb2, st_storeb2,
+ st_mult2, st_mult3, st_mult5, st_mult4, st_binary_op_res2,
+ st_binary_op_res, st_idle);
+ signal state : state_t:=st_resync;
+
+ -- Go to st_fetch state or just do its work
+ procedure DoFetch(constant FAST : boolean;
+ signal state : out state_t;
+ signal addr : out unsigned(ADDR_W-1 downto BYTE_BITS);
+ signal pc : in unsigned(ADDR_W-1 downto 0);
+ signal re : out std_logic;
+ signal busy : in std_logic) is
+ begin
+ if FAST then
+ -- Equivalent to st_fetch
+ if busy='0' then
+ addr <= pc(ADDR_W-1 downto BYTE_BITS);
+ re <= '1';
+ state <= st_decode;
+ end if;
+ else
+ state <= st_fetch;
+ end if;
+ end procedure DoFetch;
+
+ -- Perform a "binary operation" (2 operands)
+ procedure DoBinOp(result : in unsigned(WORD_SIZE-1 downto 0);
+ signal state : out state_t;
+ signal sp : inout unsigned(ADDR_W-1 downto BYTE_BITS);
+ signal addr : out unsigned(ADDR_W-1 downto BYTE_BITS);
+ signal re : out std_logic;
+ signal dest : out unsigned(WORD_SIZE-1 downto 0);
+ signal dest_p : out unsigned(WORD_SIZE-1 downto 0);
+ constant DEPTH : natural) is
+ begin
+ if DEPTH=2 then
+ -- 2 clocks: st_binary_op_res+st_binary_op_res2
+ state <= st_binary_op_res;
+ dest_p <= result;
+ elsif DEPTH=1 then
+ -- 1 clock: st_binary_op_res2
+ state <= st_binary_op_res2;
+ dest_p <= result;
+ else -- 0 clocks
+ re <= '1';
+ addr <= sp+2;
+ sp <= sp+1;
+ dest <= result;
+ state <= st_popped;
+ end if;
+ end procedure DoBinOp;
+
+ -- Perform a boolean "binary operation" (2 operands)
+ procedure DoBinOpBool(result : in boolean;
+ signal state : out state_t;
+ signal sp : inout unsigned(ADDR_W-1 downto BYTE_BITS);
+ signal addr : out unsigned(ADDR_W-1 downto BYTE_BITS);
+ signal re : out std_logic;
+ signal dest : out unsigned(WORD_SIZE-1 downto 0);
+ signal dest_p : out unsigned(WORD_SIZE-1 downto 0);
+ constant DEPTH : natural) is
+ variable res : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
+ begin
+ if result then
+ res(0):='1';
+ end if;
+ DoBinOp(res,state,sp,addr,re,dest,dest_p,DEPTH);
+ end procedure DoBinOpBool;
+
+ type insn_t is (dec_add_top, dec_dup, dec_dup_stk_b, dec_pop, dec_add,
+ dec_or, dec_and, dec_store, dec_add_sp, dec_shift, dec_nop,
+ dec_im, dec_load_sp, dec_store_sp, dec_emulate, dec_load,
+ dec_push_sp, dec_pop_pc, dec_pop_pc_rel, dec_not, dec_flip,
+ dec_pop_sp, dec_neq_branch, dec_eq, dec_loadb, dec_mult,
+ dec_less_than, dec_less_than_or_equal, dec_lshr,
+ dec_u_less_than_or_equal, dec_u_less_than, dec_push_sp_add,
+ dec_call, dec_call_pc_rel, dec_sub, dec_break, dec_storeb,
+ dec_insn_fetch, dec_pop_down);
+ signal insn : insn_t;
+ type insn_array_t is array(0 to WORD_BYTES-1) of insn_t;
+ signal insns : insn_array_t;
+ type opcode_array_t is array(0 to WORD_BYTES-1) of unsigned(OPCODE_W-1 downto 0);
+ signal opcode_r : opcode_array_t;
+begin
+ -- the memory subsystem will tell us one cycle later whether or
+ -- not it is busy
+ write_en_o <= write_en_r;
+ read_en_o <= read_en_r;
+ addr_o(ADDR_W-1 downto BYTE_BITS) <= addr_r;
+ addr_o(BYTE_BITS-1 downto 0) <= (others => '0');
+
+ -- SP+1 and +2
+ inc_sp <= sp_r+1;
+ inc_inc_sp <= sp_r+2;
+
+ opcode_control:
+ process (clk_i)
+ variable topcode : unsigned(OPCODE_W-1 downto 0);
+ variable ex_opcode : unsigned(OPCODE_W-1 downto 0);
+ variable sp_offset : unsigned(4 downto 0);
+ variable tsp_offset : unsigned(4 downto 0);
+ variable next_pc : unsigned(ADDR_W-1 downto 0);
+ variable tdecoded : insn_t;
+ variable tinsns : insn_array_t;
+ variable mult_res : unsigned(WORD_SIZE*2-1 downto 0);
+ variable ipc_low : integer range 0 to 3; -- Address inside a word (pc_r)
+ variable inpc_low : integer range 0 to 3; -- Address inside a word (next_pc)
+ variable h_bit : integer;
+ variable l_bit : integer;
+ variable not_lshr : std_logic:='1';
+ begin
+ if rising_edge(clk_i) then
+ break_o <= '0';
+ if reset_i='1' then
+ if ENA_IDLE then
+ state <= st_idle;
+ else
+ state <= st_resync;
+ end if;
+ sp_r <= SP_START;
+ pc_r <= (others => '0');
+ idim_r <= '0';
+ write_en_r <= '0';
+ read_en_r <= '0';
+ mult_a_r <= (others => '0');
+ mult_b_r <= (others => '0');
+ dbg_o.b_inst <= '0';
+ -- Reseting add_r here makes XST fail to use BRAMs ?!
+ else -- reset_i='1'
+ if MULT_PIPE then
+ -- We must multiply unconditionally to get pipelined multiplication
+ mult_res:=mult_a_r*mult_b_r;
+ mult_res1_r <= mult_res(WORD_SIZE-1 downto 0);
+ mult_res2_r <= mult_res1_r;
+ mult_res3_r <= mult_res2_r;
+ mult_a_r <= (others => D_CARE_VAL);
+ mult_b_r <= (others => D_CARE_VAL);
+ end if;
+
+ if BINOP_PIPE=2 then
+ bin_op_res2_r <= bin_op_res1_r; -- pipeline a bit.
+ end if;
+
+ read_en_r <='0';
+ write_en_r <='0';
+ -- Allow synthesis tools to load bogus values when we don't
+ -- care about the address and output data.
+ addr_r <= (others => D_CARE_VAL);
+ data_o <= (others => D_CARE_VAL);
+
+ if (write_en_r='1') and (read_en_r='1') then
+ report "read/write collision" severity failure;
+ end if;
+
+ ipc_low:=to_integer(pc_r(BYTE_BITS-1 downto 0));
+ sp_offset(4):=not opcode_r(ipc_low)(4);
+ sp_offset(3 downto 0):=opcode_r(ipc_low)(3 downto 0);
+ next_pc:=pc_r+1;
+
+ -- Prepare trace snapshot
+ dbg_o.opcode <= opcode_r(ipc_low);
+ dbg_o.pc <= resize(pc_r,32);
+ dbg_o.stk_a <= resize(a_r,32);
+ dbg_o.stk_b <= resize(b_r,32);
+ dbg_o.b_inst <= '0';
+ dbg_o.sp <= (others => '0');
+ dbg_o.sp(ADDR_W-1 downto BYTE_BITS) <= sp_r;
+
+ case state is
+ when st_idle =>
+ if enable_i='1' then
+ state <= st_resync;
+ end if;
+ -- Initial state of ZPU, fetch top of stack (A/B) + first instruction
+ when st_resync =>
+ if mem_busy_i='0' then
+ addr_r <= sp_r;
+ read_en_r <= '1';
+ state <= st_resync2;
+ end if;
+ when st_resync2 =>
+ if mem_busy_i='0' then
+ a_r <= data_i;
+ addr_r <= inc_sp;
+ read_en_r <= '1';
+ state <= st_resync3;
+ end if;
+ when st_resync3 =>
+ if mem_busy_i='0' then
+ b_r <= data_i;
+ addr_r <= pc_r(ADDR_W-1 downto BYTE_BITS);
+ read_en_r <= '1';
+ state <= st_decode;
+ end if;
+ when st_decode =>
+ if mem_busy_i='0' then
+ -- Here we latch the fetched word to give one full clock
+ -- cycle to the instruction decoder. This could be removed
+ -- if using BRAMs and the decoder delay isn't important.
+ fetched_w_r <= data_i;
+ state <= st_decode2;
+ end if;
+ when st_decode2 =>
+ -- decode 4 instructions in parallel
+ for i in 0 to WORD_BYTES-1 loop
+ topcode:=fetched_w_r((WORD_BYTES-1-i+1)*8-1 downto (WORD_BYTES-1-i)*8);
+
+ tsp_offset(4):=not topcode(4);
+ tsp_offset(3 downto 0):=topcode(3 downto 0);
+
+ opcode_r(i) <= topcode;
+ if topcode(7 downto 7)=OPCODE_IM then
+ tdecoded:=dec_im;
+ elsif topcode(7 downto 5)=OPCODE_STORESP then
+ if tsp_offset=0 then
+ -- Special case, we can avoid a write
+ tdecoded:=dec_pop;
+ elsif tsp_offset=1 then
+ -- Special case, collision
+ tdecoded:=dec_pop_down;
+ else
+ tdecoded:=dec_store_sp;
+ end if;
+ elsif topcode(7 downto 5)=OPCODE_LOADSP then
+ if tsp_offset=0 then
+ tdecoded:=dec_dup;
+ elsif tsp_offset=1 then
+ tdecoded:=dec_dup_stk_b;
+ else
+ tdecoded:=dec_load_sp;
+ end if;
+ elsif topcode(7 downto 5)=OPCODE_EMULATE then
+ tdecoded:=dec_emulate;
+ if ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_NEQBRANCH then
+ tdecoded:=dec_neq_branch;
+ elsif ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_EQ then
+ tdecoded:=dec_eq;
+ elsif ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_LOADB then
+ tdecoded:=dec_loadb;
+ elsif ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_PUSHSPADD then
+ tdecoded:=dec_push_sp_add;
+ elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_LESSTHAN then
+ tdecoded:=dec_less_than;
+ elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_ULESSTHAN then
+ tdecoded:=dec_u_less_than;
+ elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_MULT then
+ tdecoded:=dec_mult;
+ elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_STOREB then
+ tdecoded:=dec_storeb;
+ elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_CALLPCREL then
+ tdecoded:=dec_call_pc_rel;
+ elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_SUB then
+ tdecoded:=dec_sub;
+ elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_LESSTHANOREQUAL then
+ tdecoded:=dec_less_than_or_equal;
+ elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_ULESSTHANOREQUAL then
+ tdecoded:=dec_u_less_than_or_equal;
+ elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_CALL then
+ tdecoded:=dec_call;
+ elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_POPPCREL then
+ tdecoded:=dec_pop_pc_rel;
+ elsif ENA_LSHR and topcode(5 downto 0)=OPCODE_LSHIFTRIGHT then
+ tdecoded:=dec_lshr;
+ end if;
+ elsif topcode(7 downto 4)=OPCODE_ADDSP then
+ if tsp_offset=0 then
+ tdecoded:=dec_shift;
+ elsif tsp_offset=1 then
+ tdecoded:=dec_add_top;
+ else
+ tdecoded:=dec_add_sp;
+ end if;
+ else -- OPCODE_SHORT
+ case topcode(3 downto 0) is
+ when OPCODE_BREAK =>
+ tdecoded:=dec_break;
+ when OPCODE_PUSHSP =>
+ tdecoded:=dec_push_sp;
+ when OPCODE_POPPC =>
+ tdecoded:=dec_pop_pc;
+ when OPCODE_ADD =>
+ tdecoded:=dec_add;
+ when OPCODE_OR =>
+ tdecoded:=dec_or;
+ when OPCODE_AND =>
+ tdecoded:=dec_and;
+ when OPCODE_LOAD =>
+ tdecoded:=dec_load;
+ when OPCODE_NOT =>
+ tdecoded:=dec_not;
+ when OPCODE_FLIP =>
+ tdecoded:=dec_flip;
+ when OPCODE_STORE =>
+ tdecoded:=dec_store;
+ when OPCODE_POPSP =>
+ tdecoded:=dec_pop_sp;
+ when others => -- OPCODE_NOP and others
+ tdecoded:=dec_nop;
+ end case;
+ end if;
+ tinsns(i):=tdecoded;
+ end loop;
+
+ insn <= tinsns(ipc_low);
+ -- once we wrap, we need to fetch
+ tinsns(0):=dec_insn_fetch;
+ insns <= tinsns;
+ state <= st_execute;
+
+ -- Each instruction must:
+ --
+ -- 1. increase pc_r if applicable
+ -- 2. set next state if applicable
+ -- 3. do it's operation
+ when st_execute =>
+ -- Some shortcut to make the code readable:
+ inpc_low:=to_integer(next_pc(BYTE_BITS-1 downto 0));
+ ex_opcode:=opcode_r(ipc_low);
+ insn <= insns(inpc_low);
+ -- Defaults used by most instructions
+ if insn/=dec_insn_fetch and insn/=dec_im then
+ dbg_o.b_inst <= '1';
+ idim_r <= '0';
+ end if;
+ case insn is
+ when dec_insn_fetch =>
+ -- Not a real instruction, fetch new instructions
+ DoFetch(FAST_FETCH,state,addr_r,pc_r,read_en_r,mem_busy_i);
+ when dec_im =>
+ -- Push(immediate value), IDIM=1
+ -- if IDIM=0 Push(signed(opcode & 0x7F)) else
+ -- Push((Pop()<<7)|(opcode&0x7F))
+ if mem_busy_i='0' then
+ dbg_o.b_inst <= '1';
+ idim_r <= '1';
+ pc_r <= pc_r+1;
+ if idim_r='1' then
+ -- We already started an IM sequence
+ -- Shift left 7 bits
+ a_r(WORD_SIZE-1 downto 7) <= a_r(WORD_SIZE-8 downto 0);
+ -- Put the new value
+ a_r(6 downto 0) <= ex_opcode(6 downto 0);
+ else
+ -- First IM, push the value sign extended
+ FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+ a_r <= unsigned(resize(signed(ex_opcode(6 downto 0)),WORD_SIZE));
+ Push(sp_r,a_r,b_r);
+ end if;
+ end if;
+ when dec_store_sp =>
+ -- [SP+Offset]=Pop()
+ if mem_busy_i='0' then
+ write_en_r <= '1';
+ addr_r <= sp_r+sp_offset;
+ data_o <= a_r;
+ Pop(sp_r,a_r,b_r);
+ -- We need to fetch B
+ state <= st_store_sp2;
+ end if;
+ when dec_load_sp =>
+ -- Push([SP+Offset])
+ if mem_busy_i='0' then
+ FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+ Push(sp_r,a_r,b_r);
+ -- We are flushing B cache, so we need more time to
+ -- read the value.
+ state <= st_load_sp2;
+ end if;
+ when dec_emulate =>
+ -- Push(PC+1), PC=Opcode[4:0]*32
+ if mem_busy_i='0' then
+ FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+ state <= st_fetch;
+ a_r <= ExpandPC(pc_r+1);
+ Push(sp_r,a_r,b_r);
+ -- The emulate address is:
+ -- 98 7654 3210
+ -- 0000 00aa aaa0 0000
+ pc_r <= (others => '0');
+ pc_r(9 downto 5) <= ex_opcode(4 downto 0);
+ end if;
+ when dec_call_pc_rel =>
+ -- t=Pop(), Push(PC+1), PC=PC+t
+ if mem_busy_i='0' and ENA_LEVEL1 then
+ state <= st_fetch;
+ a_r <= ExpandPC(pc_r+1);
+ pc_r <= pc_r+a_r(ADDR_W-1 downto 0);
+ end if;
+ when dec_call =>
+ -- t=Pop(), Push(PC+1), PC=t
+ if mem_busy_i='0' and ENA_LEVEL2 then
+ state <= st_fetch;
+ a_r <= ExpandPC(pc_r+1);
+ pc_r <= a_r(ADDR_W-1 downto 0);
+ end if;
+ when dec_add_sp =>
+ -- Push(Pop()+[SP+Offset])
+ if mem_busy_i='0' then
+ -- Read SP+Offset
+ state <= st_add_sp2;
+ read_en_r <= '1';
+ addr_r <= sp_r+sp_offset;
+ pc_r <= pc_r+1;
+ end if;
+ when dec_push_sp =>
+ -- Push(SP)
+ if mem_busy_i='0' then
+ FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+ pc_r <= pc_r+1;
+ a_r <= (others => '0');
+ a_r(ADDR_W-1 downto BYTE_BITS) <= sp_r;
+ Push(sp_r,a_r,b_r);
+ end if;
+ when dec_pop_pc =>
+ -- PC=Pop() (return)
+ if mem_busy_i='0' then
+ FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+ state <= st_resync;
+ pc_r <= a_r(ADDR_W-1 downto 0);
+ sp_r <= inc_sp;
+ end if;
+ when dec_pop_pc_rel =>
+ -- PC=PC+Pop()
+ if mem_busy_i='0' and ENA_LEVEL2 then
+ FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+ state <= st_resync;
+ pc_r <= a_r(ADDR_W-1 downto 0)+pc_r;
+ sp_r <= inc_sp;
+ end if;
+ when dec_add =>
+ -- Push(Pop()+Pop()) [A=A+B, SP++, update B]
+ if mem_busy_i='0' then
+ state <= st_popped;
+ a_r <= a_r+b_r;
+ read_en_r <= '1';
+ addr_r <= inc_inc_sp;
+ sp_r <= inc_sp;
+ end if;
+ when dec_sub =>
+ -- a=Pop(), b=Pop(), Push(b-a)
+ if mem_busy_i='0' and ENA_LEVEL1 then
+ DoBinOp(b_r-a_r,state,sp_r,addr_r,read_en_r,
+ a_r,bin_op_res1_r,BINOP_PIPE);
+ end if;
+ when dec_pop =>
+ -- Pop()
+ if mem_busy_i='0' then
+ state <= st_popped;
+ addr_r <= inc_inc_sp;
+ read_en_r <= '1';
+ Pop(sp_r,a_r,b_r);
+ end if;
+ when dec_pop_down =>
+ -- t=Pop(), Pop(), Push(t)
+ if mem_busy_i='0' then
+ -- PopDown leaves top of stack unchanged
+ state <= st_popped;
+ addr_r <= inc_inc_sp;
+ read_en_r <= '1';
+ sp_r <= inc_sp;
+ end if;
+ when dec_or =>
+ -- Push(Pop() or Pop())
+ if mem_busy_i='0' then
+ state <= st_popped;
+ a_r <= a_r or b_r;
+ read_en_r <= '1';
+ addr_r <= inc_inc_sp;
+ sp_r <= inc_sp;
+ end if;
+ when dec_and =>
+ -- Push(Pop() and Pop())
+ if mem_busy_i='0' then
+ state <= st_popped;
+ a_r <= a_r and b_r;
+ read_en_r <= '1';
+ addr_r <= inc_inc_sp;
+ sp_r <= inc_sp;
+ end if;
+ when dec_eq =>
+ -- a=Pop(), b=Pop(), Push(a=b ? 1 : 0)
+ if mem_busy_i='0' and ENA_LEVEL0 then
+ DoBinOpBool(a_r=b_r,state,sp_r,addr_r,read_en_r,
+ a_r,bin_op_res1_r,BINOP_PIPE);
+ end if;
+ when dec_u_less_than =>
+ -- a=Pop(), b=Pop(), Push(a<b ? 1 : 0)
+ if mem_busy_i='0' and ENA_LEVEL1 then
+ DoBinOpBool(a_r<b_r,state,sp_r,addr_r,read_en_r,
+ a_r,bin_op_res1_r,BINOP_PIPE);
+ end if;
+ when dec_u_less_than_or_equal =>
+ -- a=Pop(), b=Pop(), Push(a<=b ? 1 : 0)
+ if mem_busy_i='0' and ENA_LEVEL2 then
+ DoBinOpBool(a_r<=b_r,state,sp_r,addr_r,read_en_r,
+ a_r,bin_op_res1_r,BINOP_PIPE);
+ end if;
+ when dec_less_than =>
+ -- a=signed(Pop()), b=signed(Pop()), Push(a<b ? 1 : 0)
+ if mem_busy_i='0' and ENA_LEVEL1 then
+ DoBinOpBool(signed(a_r)<signed(b_r),state,sp_r,
+ addr_r,read_en_r,a_r,bin_op_res1_r,
+ BINOP_PIPE);
+ end if;
+ when dec_less_than_or_equal =>
+ -- a=signed(Pop()), b=signed(Pop()), Push(a<=b ? 1 : 0)
+ if mem_busy_i='0' and ENA_LEVEL2 then
+ DoBinOpBool(signed(a_r)<=signed(b_r),state,sp_r,
+ addr_r,read_en_r,a_r,bin_op_res1_r,
+ BINOP_PIPE);
+ end if;
+ when dec_load =>
+ -- Push([Pop()])
+ if mem_busy_i='0' then
+ state <= st_load2;
+ addr_r <= a_r(ADDR_W-1 downto BYTE_BITS);
+ read_en_r <= '1';
+ pc_r <= pc_r+1;
+ end if;
+ when dec_dup =>
+ -- t=Pop(), Push(t), Push(t)
+ if mem_busy_i='0' then
+ pc_r <= pc_r+1;
+ -- A is dupped, no change
+ Push(sp_r,a_r,b_r);
+ FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+ end if;
+ when dec_dup_stk_b =>
+ -- Pop(), t=Pop(), Push(t), Push(t), Push(t)
+ if mem_busy_i='0' then
+ pc_r <= pc_r+1;
+ a_r <= b_r;
+ -- B goes to A
+ Push(sp_r,a_r,b_r);
+ FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+ end if;
+ when dec_store =>
+ -- a=Pop(), b=Pop(), [a]=b
+ if mem_busy_i='0' then
+ state <= st_resync;
+ pc_r <= pc_r+1;
+ addr_r <= a_r(ADDR_W-1 downto BYTE_BITS);
+ data_o <= b_r;
+ write_en_r <= '1';
+ sp_r <= inc_inc_sp;
+ end if;
+ when dec_pop_sp =>
+ -- SP=Pop()
+ if mem_busy_i='0' then
+ FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+ state <= st_resync;
+ pc_r <= pc_r+1;
+ sp_r <= a_r(ADDR_W-1 downto BYTE_BITS);
+ end if;
+ when dec_nop =>
+ pc_r <= pc_r+1;
+ when dec_not =>
+ -- Push(not(Pop()))
+ pc_r <= pc_r+1;
+ a_r <= not a_r;
+ when dec_flip =>
+ -- Push(flip(Pop()))
+ pc_r <= pc_r+1;
+ for i in 0 to WORD_SIZE-1 loop
+ a_r(i) <= a_r(WORD_SIZE-1-i);
+ end loop;
+ when dec_add_top =>
+ -- a=Pop(), b=Pop(), Push(b), Push(a+b)
+ pc_r <= pc_r+1;
+ a_r <= a_r+b_r;
+ when dec_shift =>
+ -- Push(Pop()<<1) [equivalent to a=Pop(), Push(a+a)]
+ pc_r <= pc_r+1;
+ a_r(WORD_SIZE-1 downto 1) <= a_r(WORD_SIZE-2 downto 0);
+ a_r(0) <= '0';
+ when dec_push_sp_add =>
+ -- Push(Pop()+SP)
+ if ENA_LEVEL0 then
+ pc_r <= pc_r+1;
+ a_r <= (others => '0');
+ a_r(ADDR_W-1 downto BYTE_BITS) <=
+ a_r(ADDR_W-1-BYTE_BITS downto 0)+sp_r;
+ end if;
+ when dec_neq_branch =>
+ -- a=Pop(), b=Pop(), PC+=b==0 ? 1 : a
+ -- Branches are almost always taken as they form loops
+ if ENA_LEVEL0 then
+ sp_r <= inc_inc_sp;
+ -- Need to fetch stack again.
+ state <= st_resync;
+ if b_r/=0 then
+ pc_r <= a_r(ADDR_W-1 downto 0)+pc_r;
+ else
+ pc_r <= pc_r+1;
+ end if;
+ end if;
+ when dec_mult =>
+ -- Push(Pop()*Pop())
+ if ENA_LEVEL1 then
+ if MULT_PIPE then
+ mult_a_r <= a_r;
+ mult_b_r <= b_r;
+ state <= st_mult2;
+ else
+ mult_res:=a_r*b_r;
+ mult_res1_r <= mult_res(WORD_SIZE-1 downto 0);
+ state <= st_mult5;
+ end if;
+ end if;
+ when dec_break =>
+ -- Assert the break_o signal
+ --report "Break instruction encountered" severity failure;
+ break_o <= '1';
+ pc_r <= pc_r+1;
+ when dec_loadb =>
+ -- Push([Pop()] & 0xFF) (byte address)
+ if mem_busy_i='0' and ENA_LEVEL0 then
+ state <= st_loadb2;
+ addr_r <= a_r(ADDR_W-1 downto BYTE_BITS);
+ read_en_r <= '1';
+ pc_r <= pc_r+1;
+ end if;
+ when dec_storeb =>
+ -- [Pop()]=Pop() & 0xFF (byte address)
+ if mem_busy_i='0' and ENA_LEVEL1 then
+ state <= st_storeb2;
+ addr_r <= a_r(ADDR_W-1 downto BYTE_BITS);
+ read_en_r <= '1';
+ pc_r <= pc_r+1;
+ end if;
+ when dec_lshr =>
+ -- a=Pop(), b=Pop(), Push(b>>(a&0x3F))
+ if ENA_LSHR then
+ -- This instruction takes more than one cycle.
+ -- We must avoid duplications in the trace log.
+ dbg_o.b_inst <= not_lshr;
+ not_lshr:='0';
+ if a_r(5 downto 0)=0 then -- Only 6 bits used
+ -- No more shifts
+ if mem_busy_i='0' then
+ state <= st_popped;
+ a_r <= b_r;
+ read_en_r <= '1';
+ addr_r <= inc_inc_sp;
+ sp_r <= inc_sp;
+ not_lshr:='1';
+ end if;
+ else -- More shifts needed
+ b_r <= "0"&b_r(WORD_SIZE-1 downto 1);
+ a_r(5 downto 0) <= a_r(5 downto 0)-1;
+ insn <= insn;
+ end if;
+ end if;
+ when others =>
+ -- Undefined behavior, we shouldn't get here.
+ -- It only helps synthesis tools.
+ sp_r <= (others => D_CARE_VAL);
+ report "Illegal decode instruction?!" severity failure;
+ --break_o <= '1';
+ end case;
+ -- The followup of operations that takes more than one execution clock
+ when st_store_sp2 =>
+ if mem_busy_i='0' then
+ addr_r <= inc_sp;
+ read_en_r <= '1';
+ state <= st_popped;
+ end if;
+ when st_load_sp2 =>
+ if mem_busy_i='0' then
+ state <= st_load_sp3;
+ -- Now we can read SP+Offset (SP already decremented)
+ read_en_r <= '1';
+ addr_r <= sp_r+sp_offset+1;
+ end if;
+ when st_load_sp3 =>
+ if mem_busy_i='0' then
+ -- Note: We can't increment PC in the decode stage
+ -- because it will modify sp_offset.
+ pc_r <= pc_r+1;
+ -- Finally we have the result in A
+ state <= st_execute;
+ a_r <= data_i;
+ end if;
+ when st_add_sp2 =>
+ if mem_busy_i='0' then
+ state <= st_execute;
+ a_r <= a_r+data_i;
+ end if;
+ when st_load2 =>
+ if mem_busy_i='0' then
+ a_r <= data_i;
+ state <= st_execute;
+ end if;
+ when st_loadb2 =>
+ if mem_busy_i='0' then
+ a_r <= (others => '0');
+ -- Select the source bits using the less significant bits (byte address)
+ h_bit:=(WORD_BYTES-to_integer(a_r(BYTE_BITS-1 downto 0)))*8-1;
+ l_bit:=h_bit-7;
+ a_r(7 downto 0) <= data_i(h_bit downto l_bit);
+ state <= st_execute;
+ end if;
+ when st_storeb2 =>
+ if mem_busy_i='0' then
+ addr_r <= a_r(ADDR_W-1 downto BYTE_BITS);
+ data_o <= data_i;
+ -- Select the source bits using the less significant bits (byte address)
+ h_bit:=(WORD_BYTES-to_integer(a_r(BYTE_BITS-1 downto 0)))*8-1;
+ l_bit:=h_bit-7;
+ data_o(h_bit downto l_bit) <= b_r(7 downto 0);
+ write_en_r <= '1';
+ sp_r <= inc_inc_sp;
+ state <= st_resync;
+ end if;
+ when st_fetch =>
+ if mem_busy_i='0' then
+ addr_r <= pc_r(ADDR_W-1 downto BYTE_BITS);
+ read_en_r <= '1';
+ state <= st_decode;
+ end if;
+ -- The following states can be used to leave cycles free for
+ -- tools that can automagically decompose the multiplication
+ -- in various stages. Xilinx tools can do it to increase the
+ -- multipliers performance.
+ when st_mult2 =>
+ state <= st_mult3;
+ when st_mult3 =>
+ state <= st_mult4;
+ when st_mult4 =>
+ state <= st_mult5;
+ when st_mult5 =>
+ if mem_busy_i='0' then
+ if MULT_PIPE then
+ a_r <= mult_res3_r;
+ else
+ a_r <= mult_res1_r;
+ end if;
+ read_en_r <= '1';
+ addr_r <= inc_inc_sp;
+ sp_r <= inc_sp;
+ state <= st_popped;
+ end if;
+ when st_binary_op_res =>
+ -- BINOP_PIPE=2
+ state <= st_binary_op_res2;
+ when st_binary_op_res2 =>
+ -- BINOP_PIPE>=1
+ read_en_r <= '1';
+ addr_r <= inc_inc_sp;
+ sp_r <= inc_sp;
+ state <= st_popped;
+ if BINOP_PIPE=2 then
+ a_r <= bin_op_res2_r;
+ else -- 1
+ a_r <= bin_op_res1_r;
+ end if;
+ when st_popped =>
+ if mem_busy_i='0' then
+ -- Note: Moving this PC++ to the decoder seems to
+ -- consume more LUTs.
+ pc_r <= pc_r+1;
+ b_r <= data_i;
+ state <= st_execute;
+ end if;
+ when others =>
+ -- Undefined behavior, we shouldn't get here.
+ -- It only helps synthesis tools.
+ sp_r <= (others => D_CARE_VAL);
+ report "Illegal state?!" severity failure;
+ --break_o <= '1';
+ end case; -- state
+ end if; -- else reset_i='1'
+ end if; -- rising_edge(clk_i)
+ end process opcode_control;
+end architecture Behave; -- Entity: ZPUMediumCore
+
diff --git a/zpu/hdl/zealot/zpu_pkg.vhdl b/zpu/hdl/zealot/zpu_pkg.vhdl
new file mode 100644
index 0000000..915f352
--- /dev/null
+++ b/zpu/hdl/zealot/zpu_pkg.vhdl
@@ -0,0 +1,292 @@
+------------------------------------------------------------------------------
+---- ----
+---- ZPU Package ----
+---- ----
+---- http://www.opencores.org/ ----
+---- ----
+---- Description: ----
+---- ZPU is a 32 bits small stack cpu. This is the package. ----
+---- ----
+---- To Do: ----
+---- - ----
+---- ----
+---- Author: ----
+---- - Øyvind Harboe, oyvind.harboe zylin.com ----
+---- - Salvador E. Tropea, salvador inti.gob.ar ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
+---- ----
+---- Distributed under the BSD license ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Design unit: zpupkg, UART (Package) ----
+---- File name: zpu_medium.vhdl ----
+---- Note: None ----
+---- Limitations: None known ----
+---- Errors: None known ----
+---- Library: zpu ----
+---- Dependencies: IEEE.std_logic_1164 ----
+---- IEEE.numeric_std ----
+---- Target FPGA: Spartan 3 (XC3S400-4-FT256) ----
+---- Language: VHDL ----
+---- Wishbone: No ----
+---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
+---- Text editor: SETEdit 0.5.x ----
+---- ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+package zpupkg is
+ constant OPCODE_W : integer:=8;
+
+ -- Debug structure, currently only for the trace module
+ type zpu_dbgo_t is record
+ b_inst : std_logic;
+ opcode : unsigned(OPCODE_W-1 downto 0);
+ pc : unsigned(31 downto 0);
+ sp : unsigned(31 downto 0);
+ stk_a : unsigned(31 downto 0);
+ stk_b : unsigned(31 downto 0);
+ end record;
+
+ component Trace is
+ generic(
+ LOG_FILE : string:="trace.txt"; -- Name of the trace file
+ ADDR_W : integer:=16; -- Address width
+ WORD_SIZE : integer:=32); -- 16/32
+ port(
+ clk_i : in std_logic;
+ dbg_i : in zpu_dbgo_t;
+ stop_i : in std_logic;
+ busy_i : in std_logic
+ );
+ end component Trace;
+
+ component ZPUSmallCore is
+ generic(
+ WORD_SIZE : integer:=32; -- Data width 16/32
+ ADDR_W : integer:=16; -- Total address space width (incl. I/O)
+ MEM_W : integer:=15; -- Memory (prog+data+stack) width
+ D_CARE_VAL : std_logic:='X'); -- Value used to fill the unsused bits
+ port(
+ clk_i : in std_logic; -- System Clock
+ reset_i : in std_logic; -- Synchronous Reset
+ interrupt_i : in std_logic; -- Interrupt
+ break_o : out std_logic; -- Breakpoint opcode executed
+ dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
+ -- BRAM (text, data, bss and stack)
+ a_we_o : out std_logic; -- BRAM A port Write Enable
+ a_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM A Address
+ a_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM A port
+ a_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM A port
+ b_we_o : out std_logic; -- BRAM B port Write Enable
+ b_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM B Address
+ b_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM B port
+ b_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM B port
+ -- Memory mapped I/O
+ mem_busy_i : in std_logic;
+ data_i : in unsigned(WORD_SIZE-1 downto 0);
+ data_o : out unsigned(WORD_SIZE-1 downto 0);
+ addr_o : out unsigned(ADDR_W-1 downto 0);
+ write_en_o : out std_logic;
+ read_en_o : out std_logic);
+ end component ZPUSmallCore;
+
+ component ZPUMediumCore is
+ generic(
+ WORD_SIZE : integer:=32; -- Data width 16/32
+ ADDR_W : integer:=16; -- Total address space width (incl. I/O)
+ MEM_W : integer:=15; -- Memory (prog+data+stack) width
+ D_CARE_VAL : std_logic:='X'; -- Value used to fill the unsused bits
+ MULT_PIPE : boolean:=false; -- Pipeline multiplication
+ BINOP_PIPE : integer range 0 to 2:=0; -- Pipeline binary operations (-, =, < and <=)
+ ENA_LEVEL0 : boolean:=true; -- eq, loadb, neqbranch and pushspadd
+ ENA_LEVEL1 : boolean:=true; -- lessthan, ulessthan, mult, storeb, callpcrel and sub
+ ENA_LEVEL2 : boolean:=false; -- lessthanorequal, ulessthanorequal, call and poppcrel
+ ENA_LSHR : boolean:=true; -- lshiftright
+ ENA_IDLE : boolean:=false; -- Enable the enable_i input
+ FAST_FETCH : boolean:=true); -- Merge the st_fetch with the st_execute states
+ port(
+ clk_i : in std_logic; -- CPU Clock
+ reset_i : in std_logic; -- Sync Reset
+ enable_i : in std_logic; -- Hold the CPU (after reset)
+ break_o : out std_logic; -- Break instruction executed
+ dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
+ -- Memory interface
+ mem_busy_i : in std_logic; -- Memory is busy
+ data_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from mem
+ data_o : out unsigned(WORD_SIZE-1 downto 0); -- Data to mem
+ addr_o : out unsigned(ADDR_W-1 downto 0); -- Memory address
+ write_en_o : out std_logic; -- Memory write enable
+ read_en_o : out std_logic); -- Memory read enable
+ end component ZPUMediumCore;
+
+ component Timer is
+ port(
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ we_i : in std_logic;
+ data_i : in unsigned(31 downto 0);
+ addr_i : in unsigned(0 downto 0);
+ data_o : out unsigned(31 downto 0));
+ end component Timer;
+
+ component gpio is
+ port(
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ --
+ we_i : in std_logic;
+ data_i : in unsigned(31 downto 0);
+ addr_i : in unsigned( 0 downto 0);
+ data_o : out unsigned(31 downto 0);
+ --
+ port_in : in std_logic_vector(31 downto 0);
+ port_out : out std_logic_vector(31 downto 0);
+ port_dir : out std_logic_vector(31 downto 0)
+ );
+ end component gpio;
+
+
+ component ZPUPhiIO is
+ generic(
+ BRDIVISOR : positive:=1; -- Baud rate divisor i.e. br_clk/9600/4
+ ENA_LOG : boolean:=true; -- Enable log
+ LOG_FILE : string:="log.txt"); -- Name for the log file
+ port(
+ clk_i : in std_logic; -- System Clock
+ reset_i : in std_logic; -- Synchronous Reset
+ busy_o : out std_logic; -- I/O is busy
+ we_i : in std_logic; -- Write Enable
+ re_i : in std_logic; -- Read Enable
+ data_i : in unsigned(31 downto 0);
+ data_o : out unsigned(31 downto 0);
+ addr_i : in unsigned(2 downto 0); -- Address bits 4-2
+ --
+ rs232_rx_i : in std_logic; -- UART Rx input
+ rs232_tx_o : out std_logic; -- UART Tx output
+ br_clk_i : in std_logic; -- UART base clock (enable)
+ --
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0)
+ );
+ end component ZPUPhiIO;
+
+ -- Opcode decode constants
+ -- Note: these are the basic opcodes, always implemented using hardware.
+ constant OPCODE_IM : unsigned(7 downto 7):="1";
+ constant OPCODE_STORESP : unsigned(7 downto 5):="010";
+ constant OPCODE_LOADSP : unsigned(7 downto 5):="011";
+ constant OPCODE_EMULATE : unsigned(7 downto 5):="001";
+ constant OPCODE_ADDSP : unsigned(7 downto 4):="0001";
+ constant OPCODE_SHORT : unsigned(7 downto 4):="0000";
+
+ constant OPCODE_BREAK : unsigned(3 downto 0):="0000";
+ constant OPCODE_SHIFTLEFT : unsigned(3 downto 0):="0001";
+ constant OPCODE_PUSHSP : unsigned(3 downto 0):="0010";
+ constant OPCODE_PUSHINT : unsigned(3 downto 0):="0011";
+
+ constant OPCODE_POPPC : unsigned(3 downto 0):="0100";
+ constant OPCODE_ADD : unsigned(3 downto 0):="0101";
+ constant OPCODE_AND : unsigned(3 downto 0):="0110";
+ constant OPCODE_OR : unsigned(3 downto 0):="0111";
+
+ constant OPCODE_LOAD : unsigned(3 downto 0):="1000";
+ constant OPCODE_NOT : unsigned(3 downto 0):="1001";
+ constant OPCODE_FLIP : unsigned(3 downto 0):="1010";
+ constant OPCODE_NOP : unsigned(3 downto 0):="1011";
+
+ constant OPCODE_STORE : unsigned(3 downto 0):="1100";
+ constant OPCODE_POPSP : unsigned(3 downto 0):="1101";
+ constant OPCODE_COMPARE : unsigned(3 downto 0):="1110";
+ constant OPCODE_POPINT : unsigned(3 downto 0):="1111";
+
+ -- The following instructions are emulated in the small version and
+ -- implemented as hardware in the full version.
+ -- The constants correpond to the "emulated" instruction number.
+
+ -- Enabled by the ENA_LEVEL0 generic:
+ constant OPCODE_EQ : unsigned(5 downto 0):=to_unsigned(46,6);
+ constant OPCODE_LOADB : unsigned(5 downto 0):=to_unsigned(51,6);
+ constant OPCODE_NEQBRANCH : unsigned(5 downto 0):=to_unsigned(56,6);
+ constant OPCODE_PUSHSPADD : unsigned(5 downto 0):=to_unsigned(61,6);
+ -- Enabled by the ENA_LEVEL1 generic:
+ constant OPCODE_LESSTHAN : unsigned(5 downto 0):=to_unsigned(36,6);
+ constant OPCODE_ULESSTHAN : unsigned(5 downto 0):=to_unsigned(38,6);
+ constant OPCODE_MULT : unsigned(5 downto 0):=to_unsigned(41,6);
+ constant OPCODE_STOREB : unsigned(5 downto 0):=to_unsigned(52,6);
+ constant OPCODE_CALLPCREL : unsigned(5 downto 0):=to_unsigned(63,6);
+ constant OPCODE_SUB : unsigned(5 downto 0):=to_unsigned(49,6);
+ -- Enabled by the ENA_LEVEL2 generic:
+ constant OPCODE_LESSTHANOREQUAL : unsigned(5 downto 0):=to_unsigned(37,6);
+ constant OPCODE_ULESSTHANOREQUAL : unsigned(5 downto 0):=to_unsigned(39,6);
+ constant OPCODE_CALL : unsigned(5 downto 0):=to_unsigned(45,6);
+ constant OPCODE_POPPCREL : unsigned(5 downto 0):=to_unsigned(57,6);
+ -- Enabled by the ENA_LSHR generic:
+ constant OPCODE_LSHIFTRIGHT : unsigned(5 downto 0):=to_unsigned(42,6);
+ -- The following opcodes are always emulated.
+ constant OPCODE_LOADH : unsigned(5 downto 0):=to_unsigned(34,6);
+ constant OPCODE_STOREH : unsigned(5 downto 0):=to_unsigned(35,6);
+ constant OPCODE_ASHIFTLEFT : unsigned(5 downto 0):=to_unsigned(43,6);
+ constant OPCODE_ASHIFTRIGHT : unsigned(5 downto 0):=to_unsigned(44,6);
+ constant OPCODE_NEQ : unsigned(5 downto 0):=to_unsigned(47,6);
+ constant OPCODE_NEG : unsigned(5 downto 0):=to_unsigned(48,6);
+ constant OPCODE_XOR : unsigned(5 downto 0):=to_unsigned(50,6);
+ constant OPCODE_DIV : unsigned(5 downto 0):=to_unsigned(53,6);
+ constant OPCODE_MOD : unsigned(5 downto 0):=to_unsigned(54,6);
+ constant OPCODE_EQBRANCH : unsigned(5 downto 0):=to_unsigned(55,6);
+ constant OPCODE_CONFIG : unsigned(5 downto 0):=to_unsigned(58,6);
+ constant OPCODE_PUSHPC : unsigned(5 downto 0):=to_unsigned(59,6);
+end package zpupkg;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+package UART is
+ ----------------------
+ -- Very simple UART --
+ ----------------------
+ component RxUnit is
+ port(
+ clk_i : in std_logic; -- System clock signal
+ reset_i : in std_logic; -- Reset input (sync)
+ enable_i : in std_logic; -- Enable input (rate*4)
+ read_i : in std_logic; -- Received Byte Read
+ rxd_i : in std_logic; -- RS-232 data input
+ rxav_o : out std_logic; -- Byte available
+ datao_o : out std_logic_vector(7 downto 0)); -- Byte received
+ end component RxUnit;
+
+ component TxUnit is
+ port (
+ clk_i : in std_logic; -- Clock signal
+ reset_i : in std_logic; -- Reset input
+ enable_i : in std_logic; -- Enable input
+ load_i : in std_logic; -- Load input
+ txd_o : out std_logic; -- RS-232 data output
+ busy_o : out std_logic; -- Tx Busy
+ datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
+ end component TxUnit;
+
+ component BRGen is
+ generic(
+ COUNT : integer range 0 to 65535);-- Count revolution
+ port (
+ clk_i : in std_logic; -- Clock
+ reset_i : in std_logic; -- Reset input
+ ce_i : in std_logic; -- Chip Enable
+ o_o : out std_logic); -- Output
+ end component BRGen;
+end package UART;
+
diff --git a/zpu/hdl/zealot/zpu_small.vhdl b/zpu/hdl/zealot/zpu_small.vhdl
new file mode 100644
index 0000000..056b924
--- /dev/null
+++ b/zpu/hdl/zealot/zpu_small.vhdl
@@ -0,0 +1,472 @@
+------------------------------------------------------------------------------
+---- ----
+---- ZPU Small ----
+---- ----
+---- http://www.opencores.org/ ----
+---- ----
+---- Description: ----
+---- ZPU is a 32 bits small stack cpu. This is the small size version. ----
+---- It doesn't support external memories, needs a dual ported memory. ----
+---- ----
+---- To Do: ----
+---- - ----
+---- ----
+---- Author: ----
+---- - Øyvind Harboe, oyvind.harboe zylin.com ----
+---- - Salvador E. Tropea, salvador inti.gob.ar ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
+---- ----
+---- Distributed under the BSD license ----
+---- ----
+------------------------------------------------------------------------------
+---- ----
+---- Design unit: ZPUSmallCore(Behave) (Entity and architecture) ----
+---- File name: zpu_small.vhdl ----
+---- Note: None ----
+---- Limitations: None known ----
+---- Errors: None known ----
+---- Library: zpu ----
+---- Dependencies: IEEE.std_logic_1164 ----
+---- IEEE.numeric_std ----
+---- zpu.zpupkg ----
+---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
+---- Language: VHDL ----
+---- Wishbone: No ----
+---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
+---- Text editor: SETEdit 0.5.x ----
+---- ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.numeric_std.all;
+
+library zpu;
+use zpu.zpupkg.all;
+
+entity ZPUSmallCore is
+ generic(
+ WORD_SIZE : integer:=32; -- Data width 16/32
+ ADDR_W : integer:=16; -- Total address space width (incl. I/O)
+ MEM_W : integer:=15; -- Memory (prog+data+stack) width
+ D_CARE_VAL : std_logic:='X'); -- Value used to fill the unsused bits
+ port(
+ clk_i : in std_logic; -- System Clock
+ reset_i : in std_logic; -- Synchronous Reset
+ interrupt_i : in std_logic; -- Interrupt
+ break_o : out std_logic; -- Breakpoint opcode executed
+ dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
+ -- BRAM (text, data, bss and stack)
+ a_we_o : out std_logic; -- BRAM A port Write Enable
+ a_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM A Address
+ a_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM A port
+ a_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM A port
+ b_we_o : out std_logic; -- BRAM B port Write Enable
+ b_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM B Address
+ b_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM B port
+ b_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM B port
+ -- Memory mapped I/O
+ mem_busy_i : in std_logic;
+ data_i : in unsigned(WORD_SIZE-1 downto 0);
+ data_o : out unsigned(WORD_SIZE-1 downto 0);
+ addr_o : out unsigned(ADDR_W-1 downto 0);
+ write_en_o : out std_logic;
+ read_en_o : out std_logic);
+end entity ZPUSmallCore;
+
+architecture Behave of ZPUSmallCore is
+ constant MAX_ADDR_BIT : integer:=ADDR_W-2;
+ constant BYTE_BITS : integer:=WORD_SIZE/16; -- # of bits in a word that addresses bytes
+ -- Stack Pointer initial value: BRAM size-8
+ constant SP_START_1 : unsigned(ADDR_W-1 downto 0):=to_unsigned((2**MEM_W)-8,ADDR_W);
+ constant SP_START : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=
+ SP_START_1(MAX_ADDR_BIT downto BYTE_BITS);
+ constant IO_BIT : integer:=ADDR_W-1; -- Address bit to determine this is an I/O
+
+ -- Program counter
+ signal pc_r : unsigned(MAX_ADDR_BIT downto 0):=(others => '0');
+ -- Stack pointer
+ signal sp_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=SP_START;
+ signal idim_r : std_logic:='0';
+
+ -- BRAM (text, data, bss and stack)
+ -- a_r is a register for the top of the stack [SP]
+ -- Note: as this is a stack CPU this is a very important register.
+ signal a_we_r : std_logic:='0';
+ signal a_addr_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=(others => '0');
+ signal a_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
+ -- b_r is a register for the next value in the stack [SP+1]
+ -- We also use the B port to fetch instructions.
+ signal b_we_r : std_logic:='0';
+ signal b_addr_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=(others => '0');
+ signal b_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
+
+ -- State machine.
+ type state_t is (st_fetch, st_write_io_done, st_execute, st_add, st_or,
+ st_and, st_store, st_read_io, st_write_io, st_fetch_next,
+ st_add_sp, st_decode, st_resync);
+ signal state : state_t:=st_resync;
+
+ -- Decoded Opcode
+ type decode_t is (dec_nop, dec_im, dec_load_sp, dec_store_sp, dec_add_sp,
+ dec_emulate, dec_break, dec_push_sp, dec_pop_pc, dec_add,
+ dec_or, dec_and, dec_load, dec_not, dec_flip, dec_store,
+ dec_pop_sp, dec_interrupt);
+ signal d_opcode_r : decode_t;
+ signal d_opcode : decode_t;
+
+ signal opcode : unsigned(OPCODE_W-1 downto 0); -- Decoded
+ signal opcode_r : unsigned(OPCODE_W-1 downto 0); -- Registered
+
+ -- IRQ flag
+ signal in_irq_r : std_logic:='0';
+ -- I/O space address
+ signal addr_r : unsigned(ADDR_W-1 downto 0):=(others => '0');
+begin
+ -- Dual ported memory interface
+ a_we_o <= a_we_r;
+ a_addr_o <= a_addr_r(MEM_W-1 downto BYTE_BITS);
+ a_o <= a_r;
+ b_we_o <= b_we_r;
+ b_addr_o <= b_addr_r(MEM_W-1 downto BYTE_BITS);
+ b_o <= b_r;
+
+ -------------------------
+ -- Instruction Decoder --
+ -------------------------
+ -- Note: We use Port B memory to fetch the opcodes.
+ decode_control:
+ process(b_i, pc_r)
+ variable topcode : unsigned(OPCODE_W-1 downto 0);
+ begin
+ -- Select the addressed byte inside the fetched word
+ case (to_integer(pc_r(BYTE_BITS-1 downto 0))) is
+ when 0 =>
+ topcode := to_01( b_i(31 downto 24));
+ when 1 =>
+ topcode := to_01( b_i(23 downto 16));
+ when 2 =>
+ topcode := to_01( b_i(15 downto 8));
+ when others => -- 3
+ topcode := to_01( b_i(7 downto 0));
+ end case;
+ opcode <= topcode;
+
+ if (topcode(7 downto 7)=OPCODE_IM) then
+ d_opcode <= dec_im;
+ elsif (topcode(7 downto 5)=OPCODE_STORESP) then
+ d_opcode <= dec_store_sp;
+ elsif (topcode(7 downto 5)=OPCODE_LOADSP) then
+ d_opcode <= dec_load_sp;
+ elsif (topcode(7 downto 5)=OPCODE_EMULATE) then
+ d_opcode <= dec_emulate;
+ elsif (topcode(7 downto 4)=OPCODE_ADDSP) then
+ d_opcode <= dec_add_sp;
+ else -- OPCODE_SHORT
+ case topcode(3 downto 0) is
+ when OPCODE_BREAK =>
+ d_opcode <= dec_break;
+ when OPCODE_PUSHSP =>
+ d_opcode <= dec_push_sp;
+ when OPCODE_POPPC =>
+ d_opcode <= dec_pop_pc;
+ when OPCODE_ADD =>
+ d_opcode <= dec_add;
+ when OPCODE_OR =>
+ d_opcode <= dec_or;
+ when OPCODE_AND =>
+ d_opcode <= dec_and;
+ when OPCODE_LOAD =>
+ d_opcode <= dec_load;
+ when OPCODE_NOT =>
+ d_opcode <= dec_not;
+ when OPCODE_FLIP =>
+ d_opcode <= dec_flip;
+ when OPCODE_STORE =>
+ d_opcode <= dec_store;
+ when OPCODE_POPSP =>
+ d_opcode <= dec_pop_sp;
+ when others => -- OPCODE_NOP and others
+ d_opcode <= dec_nop;
+ end case;
+ end if;
+ end process decode_control;
+
+ data_o <= b_i;
+ opcode_control:
+ process (clk_i)
+ variable sp_offset : unsigned(4 downto 0);
+ begin
+ if rising_edge(clk_i) then
+ break_o <= '0';
+ write_en_o <= '0';
+ read_en_o <= '0';
+ dbg_o.b_inst <= '0';
+ if reset_i='1' then
+ state <= st_resync;
+ sp_r <= SP_START;
+ pc_r <= (others => '0');
+ idim_r <= '0';
+ a_addr_r <= (others => '0');
+ b_addr_r <= (others => '0');
+ a_we_r <= '0';
+ b_we_r <= '0';
+ a_r <= (others => '0');
+ b_r <= (others => '0');
+ in_irq_r <= '0';
+ addr_r <= (others => '0');
+ else -- reset_i/='1'
+ a_we_r <= '0';
+ b_we_r <= '0';
+ -- This saves LUTs, by explicitly declaring that the
+ -- a_o can be left at whatever value if a_we_r is
+ -- not set.
+ a_r <= (others => D_CARE_VAL);
+ b_r <= (others => D_CARE_VAL);
+ sp_offset:=(others => D_CARE_VAL);
+ a_addr_r <= (others => D_CARE_VAL);
+ b_addr_r <= (others => D_CARE_VAL);
+ addr_r <= a_i(ADDR_W-1 downto 0);
+ d_opcode_r <= d_opcode;
+ opcode_r <= opcode;
+ if interrupt_i='0' then
+ in_irq_r <= '0'; -- no longer in an interrupt
+ end if;
+
+ case state is
+ when st_execute =>
+ state <= st_fetch;
+ -- At this point:
+ -- b_i contains opcode word
+ -- a_i contains top of stack
+ pc_r <= pc_r+1;
+
+ -- Debug info (Trace)
+ dbg_o.b_inst <= '1';
+ dbg_o.pc <= (others => '0');
+ dbg_o.pc(MAX_ADDR_BIT downto 0) <= pc_r;
+ dbg_o.opcode <= opcode_r;
+ dbg_o.sp <= (others => '0');
+ dbg_o.sp(MAX_ADDR_BIT downto BYTE_BITS) <= sp_r;
+ dbg_o.stk_a <= a_i;
+ dbg_o.stk_b <= b_i;
+
+ -- During the next cycle we'll be reading the next opcode
+ sp_offset(4):=not opcode_r(4);
+ sp_offset(3 downto 0):=opcode_r(3 downto 0);
+
+ idim_r <= '0';
+
+ --------------------
+ -- Execution Unit --
+ --------------------
+ case d_opcode_r is
+ when dec_interrupt =>
+ -- Not a real instruction, but an interrupt
+ -- Push(PC); PC=32
+ sp_r <= sp_r-1;
+ a_addr_r <= sp_r-1;
+ a_we_r <= '1';
+ a_r <= (others => D_CARE_VAL);
+ a_r(MAX_ADDR_BIT downto 0) <= pc_r;
+ -- Jump to ISR
+ pc_r <= to_unsigned(32,MAX_ADDR_BIT+1); -- interrupt address
+ --report "ZPU jumped to interrupt!" severity note;
+ when dec_im =>
+ idim_r <= '1';
+ a_we_r <= '1';
+ if idim_r='0' then
+ -- First IM
+ -- Push the 7 bits (extending the sign)
+ sp_r <= sp_r-1;
+ a_addr_r <= sp_r-1;
+ a_r <= unsigned(resize(signed(opcode_r(6 downto 0)),WORD_SIZE));
+ else
+ -- Next IMs, shift the word and put the new value in the lower
+ -- bits
+ a_addr_r <= sp_r;
+ a_r(WORD_SIZE-1 downto 7) <= a_i(WORD_SIZE-8 downto 0);
+ a_r(6 downto 0) <= opcode_r(6 downto 0);
+ end if;
+ when dec_store_sp =>
+ -- [SP+Offset]=Pop()
+ b_we_r <= '1';
+ b_addr_r <= sp_r+sp_offset;
+ b_r <= a_i;
+ sp_r <= sp_r+1;
+ state <= st_resync;
+ when dec_load_sp =>
+ -- Push([SP+Offset])
+ sp_r <= sp_r-1;
+ a_addr_r <= sp_r+sp_offset;
+ when dec_emulate =>
+ -- Push(PC+1), PC=Opcode[4:0]*32
+ sp_r <= sp_r-1;
+ a_we_r <= '1';
+ a_addr_r <= sp_r-1;
+ a_r <= (others => D_CARE_VAL);
+ a_r(MAX_ADDR_BIT downto 0) <= pc_r+1;
+ -- Jump to NUM*32
+ -- The emulate address is:
+ -- 98 7654 3210
+ -- 0000 00aa aaa0 0000
+ pc_r <= (others => '0');
+ pc_r(9 downto 5) <= opcode_r(4 downto 0);
+ when dec_add_sp =>
+ -- Push(Pop()+[SP+Offset])
+ a_addr_r <= sp_r;
+ b_addr_r <= sp_r+sp_offset;
+ state <= st_add_sp;
+ when dec_break =>
+ --report "Break instruction encountered" severity failure;
+ break_o <= '1';
+ when dec_push_sp =>
+ -- Push(SP)
+ sp_r <= sp_r-1;
+ a_we_r <= '1';
+ a_addr_r <= sp_r-1;
+ a_r <= (others => D_CARE_VAL);
+ a_r(MAX_ADDR_BIT downto BYTE_BITS) <= sp_r;
+ when dec_pop_pc =>
+ -- Pop(PC)
+ pc_r <= a_i(MAX_ADDR_BIT downto 0);
+ sp_r <= sp_r+1;
+ state <= st_resync;
+ when dec_add =>
+ -- Push(Pop()+Pop())
+ sp_r <= sp_r+1;
+ state <= st_add;
+ when dec_or =>
+ -- Push(Pop() or Pop())
+ sp_r <= sp_r+1;
+ state <= st_or;
+ when dec_and =>
+ -- Push(Pop() and Pop())
+ sp_r <= sp_r+1;
+ state <= st_and;
+ when dec_load =>
+ -- Push([Pop()])
+ if a_i(IO_BIT)='1' then
+ addr_r <= a_i(ADDR_W-1 downto 0);
+ read_en_o <= '1';
+ state <= st_read_io;
+ else
+ a_addr_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS);
+ end if;
+ when dec_not =>
+ -- Push(not(Pop()))
+ a_addr_r <= sp_r(MAX_ADDR_BIT downto BYTE_BITS);
+ a_we_r <= '1';
+ a_r <= not a_i;
+ when dec_flip =>
+ -- Push(flip(Pop()))
+ a_addr_r <= sp_r(MAX_ADDR_BIT downto BYTE_BITS);
+ a_we_r <= '1';
+ for i in 0 to WORD_SIZE-1 loop
+ a_r(i) <= a_i(WORD_SIZE-1-i);
+ end loop;
+ when dec_store =>
+ -- a=Pop(), b=Pop(), [a]=b
+ b_addr_r <= sp_r+1;
+ sp_r <= sp_r+1;
+ if a_i(IO_BIT)='1' then
+ state <= st_write_io;
+ else
+ state <= st_store;
+ end if;
+ when dec_pop_sp =>
+ -- SP=Pop()
+ sp_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS);
+ state <= st_resync;
+ when dec_nop =>
+ -- Default, keep addressing to of the stack (A)
+ a_addr_r <= sp_r;
+ when others =>
+ null;
+ end case;
+ when st_read_io =>
+ a_addr_r <= sp_r;
+ -- Wait until memory I/O isn't busy
+ if mem_busy_i='0' then
+ state <= st_fetch;
+ a_we_r <= '1';
+ a_r <= data_i;
+ end if;
+ when st_write_io =>
+ -- [A]=B
+ sp_r <= sp_r+1;
+ write_en_o <= '1';
+ addr_r <= a_i(ADDR_W-1 downto 0);
+ state <= st_write_io_done;
+ when st_write_io_done =>
+ -- Wait until memory I/O isn't busy
+ if mem_busy_i='0' then
+ state <= st_resync;
+ end if;
+ when st_fetch =>
+ -- We need to resync. During the *next* cycle
+ -- we'll fetch the opcode @ pc and thus it will
+ -- be available for st_execute the cycle after
+ -- next
+ b_addr_r <= pc_r(MAX_ADDR_BIT downto BYTE_BITS);
+ state <= st_fetch_next;
+ when st_fetch_next =>
+ -- At this point a_i contains the value that is either
+ -- from the top of stack or should be copied to the top of the stack
+ a_we_r <= '1';
+ a_r <= a_i;
+ a_addr_r <= sp_r;
+ b_addr_r <= sp_r+1;
+ state <= st_decode;
+ when st_decode =>
+ if interrupt_i='1' and in_irq_r='0' and idim_r='0' then
+ -- We got an interrupt, execute interrupt instead of next instruction
+ in_irq_r <= '1';
+ d_opcode_r <= dec_interrupt;
+ end if;
+ -- during the st_execute cycle we'll be fetching SP+1
+ a_addr_r <= sp_r;
+ b_addr_r <= sp_r+1;
+ state <= st_execute;
+ when st_store =>
+ sp_r <= sp_r+1;
+ a_we_r <= '1';
+ a_addr_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS);
+ a_r <= b_i;
+ state <= st_resync;
+ when st_add_sp =>
+ state <= st_add;
+ when st_add =>
+ a_addr_r <= sp_r;
+ a_we_r <= '1';
+ a_r <= a_i+b_i;
+ state <= st_fetch;
+ when st_or =>
+ a_addr_r <= sp_r;
+ a_we_r <= '1';
+ a_r <= a_i or b_i;
+ state <= st_fetch;
+ when st_and =>
+ a_addr_r <= sp_r;
+ a_we_r <= '1';
+ a_r <= a_i and b_i;
+ state <= st_fetch;
+ when st_resync =>
+ a_addr_r <= sp_r;
+ state <= st_fetch;
+ when others =>
+ null;
+ end case;
+ end if; -- else reset_i/='1'
+ end if; -- rising_edge(clk_i)
+ end process opcode_control;
+ addr_o <= addr_r;
+
+end architecture Behave; -- Entity: ZPUSmallCore
+
diff --git a/zpu/hdl/zpu4/core/histogram.perl b/zpu/hdl/zpu4/core/histogram.perl
new file mode 100644
index 0000000..479ee0f
--- /dev/null
+++ b/zpu/hdl/zpu4/core/histogram.perl
@@ -0,0 +1,218 @@
+#!/usr/bin/perl
+##############################################################################
+#
+# Copyright (c) 2008 Salvador E. Tropea <salvador en inti gov ar>
+# Copyright (c) 2008 Instituto Nacional de Tecnología Industrial
+#
+##############################################################################
+#
+# Target: Any
+# Language: Perl
+# Interpreter used: v5.6.1/v5.8.4
+# Text editor: SETEdit 0.5.5
+#
+##############################################################################
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
+# 02111-1307, USA
+#
+##############################################################################
+#
+# Description: Takes a ZPU trace and does some raw stats about opcodes
+# frequency and speed.
+#
+##############################################################################
+#
+# TODO
+#
+# A lot ...
+#
+
+
+# 0x40-0x460
+# div y mod son especiales
+@used=();
+@clks=();
+
+$line=1;
+$startLine=1;
+#$endLine=10000;
+$endLine=-1;
+$lastClk=0;
+$lastOpcode=-1;
+while (<>)
+ {
+ if ($_=~/^(\S+) (\S+) (\S+) (\S+) (\S+) (\S+) (\S+)/)
+ {
+ $clk=hex($7);
+ #print "$line\n";
+ if ($line>=$startLine)
+ {
+ #print $_;
+ $addr=hex($1);
+ $opcode=hex($2);
+ $sp=hex($3);
+ $a=hex($4);
+ $b=hex($5);
+ if ($addr>=0x40 and $addr<0x460)
+ {
+ @used[$opcode+0x100]++;
+ @clks[$lastOpcodeEmu]+=$clk-$lastClkEmu unless lastOpcodeEmu==-1;
+ $lastOpcodeEmu=$opcode+0x100;
+ $lastClkEmu=$clk;
+ }
+ else
+ {
+ @used[$opcode]++;
+ @clks[$lastOpcode]+=$clk-$lastClk unless $lastOpcode==-1;
+ #printf "%d+=%d\n",$lastOpcode,$clk-$lastClk;
+ $lastOpcode=$opcode;
+ $lastClk=$clk;
+ $lastOpcodeEmu=-1;
+ $lastClkEmu=$clk;
+ }
+ }
+ else
+ {
+ $lastClk=$clk;
+ }
+ last if $line==$endLine;
+ $line++;
+ }
+ }
+@used[$lastOpcode]--;
+
+$id=0;
+# Cluster them
+AddSimple('breakpoint',0);
+# 1=shiftleft, invalid
+AddSimple('pushsp',2);
+# 3=pushint, invalid
+AddSimple('poppc',4);
+AddSimple('add',5);
+AddSimple('and',6);
+AddSimple('or',7);
+AddSimple('load',8);
+AddSimple('not',9);
+AddSimple('flip',10);
+AddSimple('nop',11);
+AddSimple('store',12);
+AddSimple('popsp',13);
+# 14=compare, invalid
+# 15=popint, invalid
+AddSimpleRange('addsp',16,31);
+# 32-63 emulate
+AddSimpleRange('storesp',64,95);
+AddSimpleRange('loadsp',96,127);
+AddSimpleRange('im',128,255);
+
+# 32 is the reset entry point
+# 33 is the interrupt entry point
+AddEmulate('loadh',34);
+AddEmulate('storeh',35);
+AddEmulate('lessthan',36);
+AddEmulate('lessthanorequal',37);
+AddEmulate('ulessthan',38);
+AddEmulate('ulessthanorequal',39);
+AddEmulate('swap',40); # unimplemented
+AddEmulate('mult',41);
+AddEmulate('lshiftright',42);
+AddEmulate('ashiftleft',43);
+AddEmulate('ashiftright',44);
+AddEmulate('call',45);
+AddEmulate('eq',46);
+AddEmulate('neq',47);
+AddEmulate('neg',48);
+AddEmulate('sub',49);
+AddEmulate('xor',50);
+AddEmulate('loadb',51);
+AddEmulate('storeb',52);
+AddEmulate('div',53);
+AddEmulate('mod',54);
+AddEmulate('eqbranch',55);
+AddEmulate('neqbranch',56);
+AddEmulate('poppcrel',57);
+AddEmulate('config',58);
+AddEmulate('pushpc',59);
+AddEmulate('syscall_emulate',60); # unimplemented
+AddEmulate('pushspadd',61);
+AddEmulate('halfmult',62); # unimplemented
+AddEmulate('callpcrel',63);
+
+$maxID=$id;
+print "Total clocks: $lastClk\n";
+print "Unsorted:\n\n";
+for ($i=0; $i<$maxID; $i++)
+ {
+ $used=@used_noemu[$i];
+ $clkm=0;
+ $clkm=@clks_noemu[$i]/$used if $used;
+ printf "%-20s %8d %6.2f\n",$names[$i],$used,$clkm;
+ $by_times{$i}=$used;
+ $by_clks{$i}=@clks_noemu[$i];
+ }
+print "Sorted by consumed clocks:\n\n";
+foreach $key (sort { $by_clks{$b} <=> $by_clks{$a} } keys %by_clks)
+ {
+ printf "%5.2f %-20s %8d\n",$by_clks{$key}/$lastClk*100,$names[$key],$by_clks{$key};
+ }
+
+
+sub AddSimple
+{
+ my ($name, $opcode)=@_;
+
+ $names[$id]=$name;
+ @used_noemu[$id]=@used[$opcode];
+ @used_emu[$id]=@used[$opcode+0x100];
+ @used_both[$id]=@used[$opcode]+@used[$opcode+0x100];
+ @clks_noemu[$id]=@clks[$opcode];
+ @clks_emu[$id]=@clks[$opcode+0x100];
+ @clks_both[$id]=@clks[$opcode]+@clks[$opcode+0x100];
+ $id++;
+}
+
+sub AddEmulate
+{
+ my ($name, $opcode)=@_;
+
+ $names[$id]=$name;
+ @used_noemu[$id]=@used[$opcode];
+ @used_emu[$id]=@used[$opcode+0x100];
+ @used_both[$id]=@used[$opcode];
+ @clks_noemu[$id]=@clks[$opcode];
+ @clks_emu[$id]=@clks[$opcode+0x100];
+ @clks_both[$id]=@clks[$opcode];
+ $id++;
+}
+
+sub AddSimpleRange
+{
+ my ($name, $opStart, $opLast)=@_;
+ my $i;
+
+ $names[$id]=$name;
+ for ($i=$opStart; $i<=$opLast; $i++)
+ {
+ @used_noemu[$id]+=@used[$i];
+ @used_emu[$id]+=@used[$i+0x100];
+ @used_both[$id]+=@used[$i]+@used[$i+0x100];
+ @clks_noemu[$id]+=@clks[$i];
+ @clks_emu[$id]+=@clks[$i+0x100];
+ @clks_both[$id]+=@clks[$i]+@clks[$i+0x100];
+ }
+ $id++;
+}
+
+
diff --git a/zpu/hdl/zpu4/core/zpu_config.vhd b/zpu/hdl/zpu4/core/zpu_config.vhd
new file mode 100644
index 0000000..c678044
--- /dev/null
+++ b/zpu/hdl/zpu4/core/zpu_config.vhd
@@ -0,0 +1,58 @@
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+--
+-- The FreeBSD license
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+--
+-- 1. Redistributions of source code must retain the above copyright
+-- notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+-- copyright notice, this list of conditions and the following
+-- disclaimer in the documentation and/or other materials
+-- provided with the distribution.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package zpu_config is
+
+ -- generate trace output or not.
+ constant Generate_Trace : boolean := false;
+ constant wordPower : integer := 5;
+ -- during simulation, set this to '0' to get matching trace.txt
+ constant DontCareValue : std_logic := 'X';
+ -- Clock frequency in MHz.
+ constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64";
+ -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
+ constant maxAddrBitIncIO : integer := 15;
+ constant maxAddrBitBRAM : integer := 14;
+
+ -- start byte address of stack.
+ -- point to top of RAM - 2*words
+ constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) :=
+ std_logic_vector(to_unsigned((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1));
+
+end zpu_config;
diff --git a/zpu/hdl/zpu4/core/zpu_core.vhd b/zpu/hdl/zpu4/core/zpu_core.vhd
new file mode 100644
index 0000000..f423f80
--- /dev/null
+++ b/zpu/hdl/zpu4/core/zpu_core.vhd
@@ -0,0 +1,1014 @@
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+-- Copyright 2008 alvieboy - Álvaro Lopes - alvieboy@alvie.com
+--
+-- The FreeBSD license
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+--
+-- 1. Redistributions of source code must retain the above copyright
+-- notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+-- copyright notice, this list of conditions and the following
+-- disclaimer in the documentation and/or other materials
+-- provided with the distribution.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+
+-- mem_writeEnable - set to '1' for a single cycle to send off a write request.
+-- mem_write is valid only while mem_writeEnable='1'.
+-- mem_readEnable - set to '1' for a single cycle to send off a read request.
+--
+-- mem_busy - It is illegal to send off a read/write request when mem_busy='1'.
+-- Set to '0' when mem_read is valid after a read request.
+-- If it goes to '1'(busy), it is on the cycle after mem_read/writeEnable
+-- is '1'.
+-- mem_addr - address for read/write request
+-- mem_read - read data. Valid only on the cycle after mem_busy='0' after
+-- mem_readEnable='1' for a single cycle.
+-- mem_write - data to write
+-- mem_writeMask - set to '1' for those bits that are to be written to memory upon
+-- write request
+-- break - set to '1' when CPU hits break instruction
+-- interrupt - set to '1' until interrupts are cleared by CPU.
+
+
+
+
+entity zpu_core is
+ port (
+ clk : in std_logic;
+ reset : in std_logic;
+ enable : in std_logic;
+ in_mem_busy : in std_logic;
+ mem_read : in std_logic_vector(wordSize-1 downto 0);
+ mem_write : out std_logic_vector(wordSize-1 downto 0);
+ out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0);
+ out_mem_writeEnable : out std_logic;
+ out_mem_readEnable : out std_logic;
+ mem_writeMask : out std_logic_vector(wordBytes-1 downto 0);
+ interrupt : in std_logic;
+ break : out std_logic
+ );
+end zpu_core;
+
+
+architecture behave of zpu_core is
+
+ type InsnType is (
+ Insn_AddTop,
+ Insn_Dup,
+ Insn_DupStackB,
+ Insn_Pop,
+ Insn_PopDown,
+ Insn_Add,
+ Insn_Or,
+ Insn_And,
+ Insn_Store,
+ Insn_AddSP,
+ Insn_Shift,
+ Insn_Nop,
+ Insn_Im,
+ Insn_LoadSP,
+ Insn_StoreSP,
+ Insn_Emulate,
+ Insn_Load,
+ Insn_PushSP,
+ Insn_PopPC,
+ Insn_PopPCrel,
+ Insn_Not,
+ Insn_Flip,
+ Insn_PopSP,
+ Insn_Neqbranch,
+ Insn_Eq,
+ Insn_Loadb,
+ Insn_Mult,
+ Insn_Lessthan,
+ Insn_Lessthanorequal,
+ Insn_Ulessthanorequal,
+ Insn_Ulessthan,
+ Insn_PushSPadd,
+ Insn_Call,
+ Insn_CallPCrel,
+ Insn_Sub,
+ Insn_Break,
+ Insn_Storeb,
+ Insn_InsnFetch
+ );
+
+ type StateType is (
+ State_Load2,
+ State_Popped,
+ State_LoadSP2,
+ State_LoadSP3,
+ State_AddSP2,
+ State_Fetch,
+ State_Execute,
+ State_Decode,
+ State_Decode2,
+ State_Resync,
+
+ State_StoreSP2,
+ State_Resync2,
+ State_Resync3,
+ State_Loadb2,
+ State_Storeb2,
+ State_Mult2,
+ State_Mult3,
+ State_Mult5,
+ State_Mult4,
+ State_BinaryOpResult2,
+ State_BinaryOpResult,
+ State_Idle,
+ State_Interrupt
+ );
+
+
+ signal pc : unsigned(maxAddrBitIncIO downto 0);
+ signal sp : unsigned(maxAddrBitIncIO downto minAddrBit);
+ signal incSp : unsigned(maxAddrBitIncIO downto minAddrBit);
+ signal incIncSp : unsigned(maxAddrBitIncIO downto minAddrBit);
+ signal decSp : unsigned(maxAddrBitIncIO downto minAddrBit);
+ signal stackA : unsigned(wordSize-1 downto 0);
+ signal binaryOpResult : unsigned(wordSize-1 downto 0);
+ signal binaryOpResult2 : unsigned(wordSize-1 downto 0);
+ signal multResult2 : unsigned(wordSize-1 downto 0);
+ signal multResult3 : unsigned(wordSize-1 downto 0);
+ signal multResult : unsigned(wordSize-1 downto 0);
+ signal multA : unsigned(wordSize-1 downto 0);
+ signal multB : unsigned(wordSize-1 downto 0);
+ signal stackB : unsigned(wordSize-1 downto 0);
+ signal idim_flag : std_logic;
+ signal busy : std_logic;
+ signal mem_writeEnable : std_logic;
+ signal mem_readEnable : std_logic;
+ signal mem_addr : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+ signal mem_delayAddr : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+ signal mem_delayReadEnable : std_logic;
+ --
+ signal inInterrupt : std_logic;
+ --
+ signal decodeWord : std_logic_vector(wordSize-1 downto 0);
+ --
+ --
+ signal state : StateType;
+ signal insn : InsnType;
+ type InsnArray is array(0 to wordBytes-1) of InsnType;
+ signal decodedOpcode : InsnArray;
+ --
+ type OpcodeArray is array(0 to wordBytes-1) of std_logic_vector(7 downto 0);
+ --
+ signal opcode : OpcodeArray;
+
+
+
+ signal begin_inst : std_logic;
+ signal trace_opcode : std_logic_vector(7 downto 0);
+ signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0);
+ signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+ signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0);
+ signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0);
+
+-- state machine.
+
+begin
+
+
+ traceFileGenerate :
+ if Generate_Trace generate
+ trace_file : trace port map (
+ clk => clk,
+ begin_inst => begin_inst,
+ pc => trace_pc,
+ opcode => trace_opcode,
+ sp => trace_sp,
+ memA => trace_topOfStack,
+ memB => trace_topOfStackB,
+ busy => busy,
+ intsp => (others => 'U')
+ );
+ end generate;
+
+
+ -- the memory subsystem will tell us one cycle later whether or
+ -- not it is busy
+ out_mem_writeEnable <= mem_writeEnable;
+ out_mem_readEnable <= mem_readEnable;
+ out_mem_addr(maxAddrBitIncIO downto minAddrBit) <= mem_addr;
+ out_mem_addr(minAddrBit-1 downto 0) <= (others => '0');
+
+ incSp <= sp + 1;
+ incIncSp <= sp + 2;
+ decSp <= sp - 1;
+
+
+ opcodeControl : process(clk, reset)
+ variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0);
+ variable spOffset : unsigned(4 downto 0);
+ variable tSpOffset : unsigned(4 downto 0);
+ variable nextPC : unsigned(maxAddrBitIncIO downto 0);
+ variable tNextInsn : InsnType;
+ variable tDecodedOpcode : InsnArray;
+ variable tMultResult : unsigned(wordSize*2-1 downto 0);
+ begin
+ if reset = '1' then
+ state <= State_Idle;
+ break <= '0';
+ sp <= unsigned(spStart(maxAddrBitIncIO downto minAddrBit));
+
+ pc <= (others => '0');
+ idim_flag <= '0';
+ begin_inst <= '0';
+ inInterrupt <= '0';
+ mem_writeEnable <= '0';
+ mem_readEnable <= '0';
+ multA <= (others => '0');
+ multB <= (others => '0');
+ mem_writeMask <= (others => '1');
+ elsif rising_edge(clk) then
+ -- we must multiply unconditionally to get pipelined multiplication
+ tMultResult := multA * multB;
+ multResult3 <= multResult2;
+ multResult2 <= multResult;
+ multResult <= tMultResult(wordSize-1 downto 0);
+
+
+ binaryOpResult2 <= binaryOpResult; -- pipeline a bit.
+
+
+ multA <= (others => DontCareValue);
+ multB <= (others => DontCareValue);
+
+
+ mem_addr <= (others => DontCareValue);
+ mem_readEnable <= '0';
+ mem_writeEnable <= '0';
+ mem_write <= (others => DontCareValue);
+
+ if (mem_writeEnable = '1') and (mem_readEnable = '1') then
+ report "read/write collision" severity failure;
+ end if;
+
+
+
+
+ spOffset(4) := not opcode(to_integer(pc(byteBits-1 downto 0)))(4);
+ spOffset(3 downto 0) := unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(3 downto 0));
+ nextPC := pc + 1;
+
+ -- prepare trace snapshot
+ trace_opcode <= opcode(to_integer(pc(byteBits-1 downto 0)));
+ trace_pc <= std_logic_vector(pc);
+ trace_sp <= std_logic_vector(sp);
+ trace_topOfStack <= std_logic_vector(stackA);
+ trace_topOfStackB <= std_logic_vector(stackB);
+ begin_inst <= '0';
+
+ if (interrupt = '0') then
+ -- Interrupt ended, we can serve ISR again
+ inInterrupt <= '0';
+ end if;
+
+ case state is
+
+ when State_Idle =>
+ if enable = '1' then
+ state <= State_Resync;
+ end if;
+ -- Initial state of ZPU, fetch top of stack + first instruction
+
+ when State_Resync =>
+ if in_mem_busy = '0' then
+ mem_addr <= std_logic_vector(sp);
+ mem_readEnable <= '1';
+ state <= State_Resync2;
+ end if;
+
+ when State_Resync2 =>
+ if in_mem_busy = '0' then
+ stackA <= unsigned(mem_read);
+ mem_addr <= std_logic_vector(incSp);
+ mem_readEnable <= '1';
+ state <= State_Resync3;
+ end if;
+
+ when State_Resync3 =>
+ if in_mem_busy = '0' then
+ stackB <= unsigned(mem_read);
+ mem_addr <= std_logic_vector(pc(maxAddrBitIncIO downto minAddrBit));
+ mem_readEnable <= '1';
+ state <= State_Decode;
+ end if;
+
+ when State_Decode =>
+ if in_mem_busy = '0' then
+ decodeWord <= mem_read;
+ state <= State_Decode2;
+ -- Do not recurse into ISR while interrupt line is active
+ if interrupt = '1' and inInterrupt = '0' and idim_flag = '0' then
+ -- We got an interrupt, execute interrupt instead of next instruction
+ inInterrupt <= '1';
+ sp <= decSp;
+ mem_writeEnable <= '1';
+ mem_addr <= std_logic_vector(incSp);
+ mem_write <= std_logic_vector(stackB);
+ stackA <= (others => DontCareValue);
+ stackA(maxAddrBitIncIO downto 0) <= pc;
+ stackB <= stackA;
+ pc <= to_unsigned(32, maxAddrBitIncIO+1);
+ state <= State_Interrupt;
+ end if; -- interrupt
+ end if; -- in_mem_busy
+
+ when State_Interrupt =>
+ if in_mem_busy = '0' then
+ mem_addr <= std_logic_vector(pc(maxAddrBitIncIO downto minAddrBit));
+ mem_readEnable <= '1';
+ state <= State_Decode;
+ report "ZPU jumped to interrupt!" severity note;
+ end if;
+
+ when State_Decode2 =>
+ -- decode 4 instructions in parallel
+ for i in 0 to wordBytes-1 loop
+ tOpcode := decodeWord((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8);
+
+ tSpOffset(4) := not tOpcode(4);
+ tSpOffset(3 downto 0) := unsigned(tOpcode(3 downto 0));
+
+ opcode(i) <= tOpcode;
+ if (tOpcode(7 downto 7) = OpCode_Im) then
+ tNextInsn := Insn_Im;
+ elsif (tOpcode(7 downto 5) = OpCode_StoreSP) then
+ if tSpOffset = 0 then
+ tNextInsn := Insn_Pop;
+ elsif tSpOffset = 1 then
+ tNextInsn := Insn_PopDown;
+ else
+ tNextInsn := Insn_StoreSP;
+ end if;
+ elsif (tOpcode(7 downto 5) = OpCode_LoadSP) then
+ if tSpOffset = 0 then
+ tNextInsn := Insn_Dup;
+ elsif tSpOffset = 1 then
+ tNextInsn := Insn_DupStackB;
+ else
+ tNextInsn := Insn_LoadSP;
+ end if;
+ elsif (tOpcode(7 downto 5) = OpCode_Emulate) then
+ tNextInsn := Insn_Emulate;
+ if tOpcode(5 downto 0) = OpCode_Neqbranch then
+ tNextInsn := Insn_Neqbranch;
+ elsif tOpcode(5 downto 0) = OpCode_Eq then
+ tNextInsn := Insn_Eq;
+ elsif tOpcode(5 downto 0) = OpCode_Lessthan then
+ tNextInsn := Insn_Lessthan;
+ elsif tOpcode(5 downto 0) = OpCode_Lessthanorequal then
+ --tNextInsn :=Insn_Lessthanorequal;
+ elsif tOpcode(5 downto 0) = OpCode_Ulessthan then
+ tNextInsn := Insn_Ulessthan;
+ elsif tOpcode(5 downto 0) = OpCode_Ulessthanorequal then
+ --tNextInsn :=Insn_Ulessthanorequal;
+ elsif tOpcode(5 downto 0) = OpCode_Loadb then
+ tNextInsn := Insn_Loadb;
+ elsif tOpcode(5 downto 0) = OpCode_Mult then
+ tNextInsn := Insn_Mult;
+ elsif tOpcode(5 downto 0) = OpCode_Storeb then
+ tNextInsn := Insn_Storeb;
+ elsif tOpcode(5 downto 0) = OpCode_Pushspadd then
+ tNextInsn := Insn_PushSPadd;
+ elsif tOpcode(5 downto 0) = OpCode_Callpcrel then
+ tNextInsn := Insn_CallPCrel;
+ elsif tOpcode(5 downto 0) = OpCode_Call then
+ --tNextInsn :=Insn_Call;
+ elsif tOpcode(5 downto 0) = OpCode_Sub then
+ tNextInsn := Insn_Sub;
+ elsif tOpcode(5 downto 0) = OpCode_PopPCRel then
+ --tNextInsn :=Insn_PopPCrel;
+ end if;
+ elsif (tOpcode(7 downto 4) = OpCode_AddSP) then
+ if tSpOffset = 0 then
+ tNextInsn := Insn_Shift;
+ elsif tSpOffset = 1 then
+ tNextInsn := Insn_AddTop;
+ else
+ tNextInsn := Insn_AddSP;
+ end if;
+ else
+ case tOpcode(3 downto 0) is
+ when OpCode_Nop =>
+ tNextInsn := Insn_Nop;
+ when OpCode_PushSP =>
+ tNextInsn := Insn_PushSP;
+ when OpCode_PopPC =>
+ tNextInsn := Insn_PopPC;
+ when OpCode_Add =>
+ tNextInsn := Insn_Add;
+ when OpCode_Or =>
+ tNextInsn := Insn_Or;
+ when OpCode_And =>
+ tNextInsn := Insn_And;
+ when OpCode_Load =>
+ tNextInsn := Insn_Load;
+ when OpCode_Not =>
+ tNextInsn := Insn_Not;
+ when OpCode_Flip =>
+ tNextInsn := Insn_Flip;
+ when OpCode_Store =>
+ tNextInsn := Insn_Store;
+ when OpCode_PopSP =>
+ tNextInsn := Insn_PopSP;
+ when others =>
+ tNextInsn := Insn_Break;
+
+ end case; -- tOpcode(3 downto 0)
+ end if; -- tOpcode
+ tDecodedOpcode(i) := tNextInsn;
+
+ end loop; -- 0 to wordBytes-1
+
+ insn <= tDecodedOpcode(to_integer(pc(byteBits-1 downto 0)));
+
+ -- once we wrap, we need to fetch
+ tDecodedOpcode(0) := Insn_InsnFetch;
+
+ decodedOpcode <= tDecodedOpcode;
+ state <= State_Execute;
+
+
+
+ -- Each instruction must:
+ --
+ -- 1. set idim_flag
+ -- 2. increase PC if applicable
+ -- 3. set next state if appliable
+ -- 4. do it's operation
+
+ when State_Execute =>
+ insn <= decodedOpcode(to_integer(nextPC(byteBits-1 downto 0)));
+
+ case insn is
+
+ when Insn_InsnFetch =>
+ state <= State_Fetch;
+
+ when Insn_Im =>
+ if in_mem_busy = '0' then
+ begin_inst <= '1';
+ idim_flag <= '1';
+ pc <= pc + 1;
+
+ if idim_flag = '1' then
+ stackA(wordSize-1 downto 7) <= stackA(wordSize-8 downto 0);
+ stackA(6 downto 0) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(6 downto 0));
+ else
+ mem_writeEnable <= '1';
+ mem_addr <= std_logic_vector(incSp);
+ mem_write <= std_logic_vector(stackB);
+ stackB <= stackA;
+ sp <= decSp;
+ for i in wordSize-1 downto 7 loop
+ stackA(i) <= opcode(to_integer(pc(byteBits-1 downto 0)))(6);
+ end loop;
+ stackA(6 downto 0) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(6 downto 0));
+ end if; -- idim_flag
+ end if; -- in_mem_busy
+
+ when Insn_StoreSP =>
+ if in_mem_busy = '0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ state <= State_StoreSP2;
+
+ mem_writeEnable <= '1';
+ mem_addr <= std_logic_vector(sp+spOffset);
+ mem_write <= std_logic_vector(stackA);
+ stackA <= stackB;
+ sp <= incSp;
+ end if;
+
+
+ when Insn_LoadSP =>
+ if in_mem_busy = '0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ state <= State_LoadSP2;
+
+ sp <= decSp;
+ mem_writeEnable <= '1';
+ mem_addr <= std_logic_vector(incSp);
+ mem_write <= std_logic_vector(stackB);
+ end if;
+
+ when Insn_Emulate =>
+ if in_mem_busy = '0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ sp <= decSp;
+ mem_writeEnable <= '1';
+ mem_addr <= std_logic_vector(incSp);
+ mem_write <= std_logic_vector(stackB);
+ stackA <= (others => DontCareValue);
+ stackA(maxAddrBitIncIO downto 0) <= pc + 1;
+ stackB <= stackA;
+
+ -- The emulate address is:
+ -- 98 7654 3210
+ -- 0000 00aa aaa0 0000
+ pc <= (others => '0');
+ pc(9 downto 5) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(4 downto 0));
+ state <= State_Fetch;
+ end if; -- in_mem_busy
+
+ when Insn_CallPCrel =>
+ if in_mem_busy = '0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ stackA <= (others => DontCareValue);
+ stackA(maxAddrBitIncIO downto 0) <= pc + 1;
+
+ pc <= pc + stackA(maxAddrBitIncIO downto 0);
+ state <= State_Fetch;
+ end if;
+
+ when Insn_Call =>
+ if in_mem_busy = '0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ stackA <= (others => DontCareValue);
+ stackA(maxAddrBitIncIO downto 0) <= pc + 1;
+ pc <= stackA(maxAddrBitIncIO downto 0);
+ state <= State_Fetch;
+ end if;
+
+ when Insn_AddSP =>
+ if in_mem_busy = '0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ state <= State_AddSP2;
+
+ mem_readEnable <= '1';
+ mem_addr <= std_logic_vector(sp+spOffset);
+ end if;
+
+ when Insn_PushSP =>
+ if in_mem_busy = '0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ pc <= pc + 1;
+
+ sp <= decSp;
+ stackA <= (others => '0');
+ stackA(maxAddrBitIncIO downto minAddrBit) <= sp;
+ stackB <= stackA;
+ mem_writeEnable <= '1';
+ mem_addr <= std_logic_vector(incSp);
+ mem_write <= std_logic_vector(stackB);
+ end if;
+
+ when Insn_PopPC =>
+ if in_mem_busy = '0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ pc <= stackA(maxAddrBitIncIO downto 0);
+ sp <= incSp;
+
+ mem_writeEnable <= '1';
+ mem_addr <= std_logic_vector(incSp);
+ mem_write <= std_logic_vector(stackB);
+ state <= State_Resync;
+ end if;
+
+ when Insn_PopPCrel =>
+ if in_mem_busy = '0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ pc <= stackA(maxAddrBitIncIO downto 0) + pc;
+ sp <= incSp;
+
+ mem_writeEnable <= '1';
+ mem_addr <= std_logic_vector(incSp);
+ mem_write <= std_logic_vector(stackB);
+ state <= State_Resync;
+ end if;
+
+ when Insn_Add =>
+ if in_mem_busy = '0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ stackA <= stackA + stackB;
+
+ mem_readEnable <= '1';
+ mem_addr <= std_logic_vector(incIncSp);
+ sp <= incSp;
+ state <= State_Popped;
+ end if;
+
+ when Insn_Sub =>
+ if in_mem_busy = '0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ binaryOpResult <= stackB - stackA;
+ state <= State_BinaryOpResult;
+ end if;
+
+ when Insn_Pop =>
+ if in_mem_busy = '0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ mem_addr <= std_logic_vector(incIncSp);
+ mem_readEnable <= '1';
+ sp <= incSp;
+ stackA <= stackB;
+ state <= State_Popped;
+ end if;
+
+ when Insn_PopDown =>
+ if in_mem_busy = '0' then
+ -- PopDown leaves top of stack unchanged
+ begin_inst <= '1';
+ idim_flag <= '0';
+ mem_addr <= std_logic_vector(incIncSp);
+ mem_readEnable <= '1';
+ sp <= incSp;
+ state <= State_Popped;
+ end if;
+
+ when Insn_Or =>
+ if in_mem_busy = '0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ stackA <= stackA or stackB;
+ mem_readEnable <= '1';
+ mem_addr <= std_logic_vector(incIncSp);
+ sp <= incSp;
+ state <= State_Popped;
+ end if;
+
+ when Insn_And =>
+ if in_mem_busy = '0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+
+ stackA <= stackA and stackB;
+ mem_readEnable <= '1';
+ mem_addr <= std_logic_vector(incIncSp);
+ sp <= incSp;
+ state <= State_Popped;
+ end if;
+
+ when Insn_Eq =>
+ if in_mem_busy = '0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+
+ binaryOpResult <= (others => '0');
+ if (stackA = stackB) then
+ binaryOpResult(0) <= '1';
+ end if;
+ state <= State_BinaryOpResult;
+ end if;
+
+ when Insn_Ulessthan =>
+ if in_mem_busy = '0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+
+ binaryOpResult <= (others => '0');
+ if (stackA < stackB) then
+ binaryOpResult(0) <= '1';
+ end if;
+ state <= State_BinaryOpResult;
+ end if;
+
+ when Insn_Ulessthanorequal =>
+ if in_mem_busy = '0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+
+ binaryOpResult <= (others => '0');
+ if (stackA <= stackB) then
+ binaryOpResult(0) <= '1';
+ end if;
+ state <= State_BinaryOpResult;
+ end if;
+
+ when Insn_Lessthan =>
+ if in_mem_busy = '0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+
+ binaryOpResult <= (others => '0');
+ if (signed(stackA) < signed(stackB)) then
+ binaryOpResult(0) <= '1';
+ end if;
+ state <= State_BinaryOpResult;
+ end if;
+
+ when Insn_Lessthanorequal =>
+ if in_mem_busy = '0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+
+ binaryOpResult <= (others => '0');
+ if (signed(stackA) <= signed(stackB)) then
+ binaryOpResult(0) <= '1';
+ end if;
+ state <= State_BinaryOpResult;
+ end if;
+
+ when Insn_Load =>
+ if in_mem_busy = '0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ state <= State_Load2;
+
+ mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit));
+ mem_readEnable <= '1';
+ end if;
+
+ when Insn_Dup =>
+ if in_mem_busy = '0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ pc <= pc + 1;
+
+ sp <= decSp;
+ stackB <= stackA;
+ mem_write <= std_logic_vector(stackB);
+ mem_addr <= std_logic_vector(incSp);
+ mem_writeEnable <= '1';
+ end if;
+
+ when Insn_DupStackB =>
+ if in_mem_busy = '0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ pc <= pc + 1;
+
+ sp <= decSp;
+ stackA <= stackB;
+ stackB <= stackA;
+ mem_write <= std_logic_vector(stackB);
+ mem_addr <= std_logic_vector(incSp);
+ mem_writeEnable <= '1';
+ end if;
+
+ when Insn_Store =>
+ if in_mem_busy = '0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ pc <= pc + 1;
+ mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit));
+ mem_write <= std_logic_vector(stackB);
+ mem_writeEnable <= '1';
+ sp <= incIncSp;
+ state <= State_Resync;
+ end if;
+
+ when Insn_PopSP =>
+ if in_mem_busy = '0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ pc <= pc + 1;
+
+ mem_write <= std_logic_vector(stackB);
+ mem_addr <= std_logic_vector(incSp);
+ mem_writeEnable <= '1';
+ sp <= stackA(maxAddrBitIncIO downto minAddrBit);
+ state <= State_Resync;
+ end if;
+
+ when Insn_Nop =>
+ begin_inst <= '1';
+ idim_flag <= '0';
+ pc <= pc + 1;
+
+ when Insn_Not =>
+ begin_inst <= '1';
+ idim_flag <= '0';
+ pc <= pc + 1;
+
+ stackA <= not stackA;
+
+ when Insn_Flip =>
+ begin_inst <= '1';
+ idim_flag <= '0';
+ pc <= pc + 1;
+
+ for i in 0 to wordSize-1 loop
+ stackA(i) <= stackA(wordSize-1-i);
+ end loop;
+
+ when Insn_AddTop =>
+ begin_inst <= '1';
+ idim_flag <= '0';
+ pc <= pc + 1;
+
+ stackA <= stackA + stackB;
+
+ when Insn_Shift =>
+ begin_inst <= '1';
+ idim_flag <= '0';
+ pc <= pc + 1;
+
+ stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0);
+ stackA(0) <= '0';
+
+ when Insn_PushSPadd =>
+ begin_inst <= '1';
+ idim_flag <= '0';
+ pc <= pc + 1;
+
+ stackA <= (others => '0');
+ stackA(maxAddrBitIncIO downto minAddrBit) <= stackA(maxAddrBitIncIO-minAddrBit downto 0)+sp;
+
+ when Insn_Neqbranch =>
+ -- branches are almost always taken as they form loops
+ begin_inst <= '1';
+ idim_flag <= '0';
+ sp <= incIncSp;
+ if (stackB /= 0) then
+ pc <= stackA(maxAddrBitIncIO downto 0) + pc;
+ else
+ pc <= pc + 1;
+ end if;
+ -- need to fetch stack again.
+ state <= State_Resync;
+
+ when Insn_Mult =>
+ begin_inst <= '1';
+ idim_flag <= '0';
+
+ multA <= stackA;
+ multB <= stackB;
+ state <= State_Mult2;
+
+ when Insn_Break =>
+ report "Break instruction encountered" severity failure;
+ break <= '1';
+
+ when Insn_Loadb =>
+ if in_mem_busy = '0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ state <= State_Loadb2;
+
+ mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit));
+ mem_readEnable <= '1';
+ end if;
+
+ when Insn_Storeb =>
+ if in_mem_busy = '0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ state <= State_Storeb2;
+
+ mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit));
+ mem_readEnable <= '1';
+ end if;
+
+ when others =>
+ sp <= (others => DontCareValue);
+ report "Illegal instruction" severity failure;
+ break <= '1';
+
+ end case; -- insn/State_Execute
+
+
+ when State_StoreSP2 =>
+ if in_mem_busy = '0' then
+ mem_addr <= std_logic_vector(incSp);
+ mem_readEnable <= '1';
+ state <= State_Popped;
+ end if;
+
+ when State_LoadSP2 =>
+ if in_mem_busy = '0' then
+ state <= State_LoadSP3;
+ mem_readEnable <= '1';
+ mem_addr <= std_logic_vector(sp+spOffset+1);
+ end if;
+
+ when State_LoadSP3 =>
+ if in_mem_busy = '0' then
+ pc <= pc + 1;
+ state <= State_Execute;
+ stackB <= stackA;
+ stackA <= unsigned(mem_read);
+ end if;
+
+ when State_AddSP2 =>
+ if in_mem_busy = '0' then
+ pc <= pc + 1;
+ state <= State_Execute;
+ stackA <= stackA + unsigned(mem_read);
+ end if;
+
+ when State_Load2 =>
+ if in_mem_busy = '0' then
+ stackA <= unsigned(mem_read);
+ pc <= pc + 1;
+ state <= State_Execute;
+ end if;
+
+ when State_Loadb2 =>
+ if in_mem_busy = '0' then
+ stackA <= (others => '0');
+ stackA(7 downto 0) <= unsigned(mem_read(((wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8));
+ pc <= pc + 1;
+ state <= State_Execute;
+ end if;
+
+ when State_Storeb2 =>
+ if in_mem_busy = '0' then
+ mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit));
+ mem_write <= mem_read;
+ mem_write(((wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8) <= std_logic_vector(stackB(7 downto 0));
+ mem_writeEnable <= '1';
+ pc <= pc + 1;
+ sp <= incIncSp;
+ state <= State_Resync;
+ end if;
+
+ when State_Fetch =>
+ if in_mem_busy = '0' then
+ mem_addr <= std_logic_vector(pc(maxAddrBitIncIO downto minAddrBit));
+ mem_readEnable <= '1';
+ state <= State_Decode;
+ end if;
+
+ when State_Mult2 =>
+ state <= State_Mult3;
+
+ when State_Mult3 =>
+ state <= State_Mult4;
+
+ when State_Mult4 =>
+ state <= State_Mult5;
+
+ when State_Mult5 =>
+ if in_mem_busy = '0' then
+ stackA <= multResult3;
+ mem_readEnable <= '1';
+ mem_addr <= std_logic_vector(incIncSp);
+ sp <= incSp;
+ state <= State_Popped;
+ end if;
+
+ when State_BinaryOpResult =>
+ state <= State_BinaryOpResult2;
+
+ when State_BinaryOpResult2 =>
+ mem_readEnable <= '1';
+ mem_addr <= std_logic_vector(incIncSp);
+ sp <= incSp;
+ stackA <= binaryOpResult2;
+ state <= State_Popped;
+
+ when State_Popped =>
+ if in_mem_busy = '0' then
+ pc <= pc + 1;
+ stackB <= unsigned(mem_read);
+ state <= State_Execute;
+ end if;
+
+ when others =>
+ sp <= (others => DontCareValue);
+ report "Illegal state" severity failure;
+ break <= '1';
+
+ end case; -- state
+ end if; -- clk'event
+ end process;
+
+
+
+end behave;
diff --git a/zpu/hdl/zpu4/core/zpu_core_small.vhd b/zpu/hdl/zpu4/core/zpu_core_small.vhd
new file mode 100644
index 0000000..9ac35a8
--- /dev/null
+++ b/zpu/hdl/zpu4/core/zpu_core_small.vhd
@@ -0,0 +1,602 @@
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+--
+-- The FreeBSD license
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+--
+-- 1. Redistributions of source code must retain the above copyright
+-- notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+-- copyright notice, this list of conditions and the following
+-- disclaimer in the documentation and/or other materials
+-- provided with the distribution.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+
+entity zpu_core is
+ port (
+ clk : in std_logic;
+ -- asynchronous reset signal
+ reset : in std_logic;
+ -- this particular implementation of the ZPU does not
+ -- have a clocked enable signal
+ enable : in std_logic;
+ in_mem_busy : in std_logic;
+ mem_read : in std_logic_vector(wordSize-1 downto 0);
+ mem_write : out std_logic_vector(wordSize-1 downto 0);
+ out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0);
+ out_mem_writeEnable : out std_logic;
+ out_mem_readEnable : out std_logic;
+ -- this implementation of the ZPU *always* reads and writes entire
+ -- 32 bit words, so mem_writeMask is tied to (others => '1').
+ mem_writeMask : out std_logic_vector(wordBytes-1 downto 0);
+ -- Set to one to jump to interrupt vector
+ -- The ZPU will communicate with the hardware that caused the
+ -- interrupt via memory mapped IO or the interrupt flag can
+ -- be cleared automatically
+ interrupt : in std_logic;
+ -- Signal that the break instruction is executed, normally only used
+ -- in simulation to stop simulation
+ break : out std_logic
+ );
+end zpu_core;
+
+
+
+architecture behave of zpu_core is
+
+ signal memAWriteEnable : std_logic;
+ signal memAAddr : unsigned(maxAddrBit downto minAddrBit);
+ signal memAWrite : unsigned(wordSize-1 downto 0);
+ signal memARead : unsigned(wordSize-1 downto 0);
+ signal memBWriteEnable : std_logic;
+ signal memBAddr : unsigned(maxAddrBit downto minAddrBit);
+ signal memBWrite : unsigned(wordSize-1 downto 0);
+ signal memBRead : unsigned(wordSize-1 downto 0);
+
+
+
+ signal pc : unsigned(maxAddrBit downto 0);
+ signal sp : unsigned(maxAddrBit downto minAddrBit);
+
+ -- this signal is set upon executing an IM instruction
+ -- the subsequence IM instruction will then behave differently.
+ -- all other instructions will clear the idim_flag.
+ -- this yields highly compact immediate instructions.
+ signal idim_flag : std_logic;
+ --
+ signal busy : std_logic;
+ --
+ signal begin_inst : std_logic;
+
+
+ signal trace_opcode : std_logic_vector(7 downto 0);
+ signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0);
+ signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+ signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0);
+ signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0);
+
+ -- state machine.
+ type State_Type is (
+ State_Fetch,
+ State_WriteIODone,
+ State_Execute,
+ State_StoreToStack,
+ State_Add,
+ State_Or,
+ State_And,
+ State_Store,
+ State_ReadIO,
+ State_WriteIO,
+ State_Load,
+ State_FetchNext,
+ State_AddSP,
+ State_ReadIODone,
+ State_Decode,
+ State_Resync,
+ State_Interrupt
+ );
+
+ type DecodedOpcodeType is (
+ Decoded_Nop,
+ Decoded_Im,
+ Decoded_ImShift,
+ Decoded_LoadSP,
+ Decoded_StoreSP ,
+ Decoded_AddSP,
+ Decoded_Emulate,
+ Decoded_Break,
+ Decoded_PushSP,
+ Decoded_PopPC,
+ Decoded_Add,
+ Decoded_Or,
+ Decoded_And,
+ Decoded_Load,
+ Decoded_Not,
+ Decoded_Flip,
+ Decoded_Store,
+ Decoded_PopSP,
+ Decoded_Interrupt
+ );
+
+
+
+ signal sampledOpcode : std_logic_vector(OpCode_Size-1 downto 0);
+ signal opcode : std_logic_vector(OpCode_Size-1 downto 0);
+ --
+ signal decodedOpcode : DecodedOpcodeType;
+ signal sampledDecodedOpcode : DecodedOpcodeType;
+
+
+ signal state : State_Type;
+ --
+ subtype AddrBitBRAM_range is natural range maxAddrBitBRAM downto minAddrBit;
+ signal memAAddr_stdlogic : std_logic_vector(AddrBitBRAM_range);
+ signal memAWrite_stdlogic : std_logic_vector(memAWrite'range);
+ signal memARead_stdlogic : std_logic_vector(memARead'range);
+ signal memBAddr_stdlogic : std_logic_vector(AddrBitBRAM_range);
+ signal memBWrite_stdlogic : std_logic_vector(memBWrite'range);
+ signal memBRead_stdlogic : std_logic_vector(memBRead'range);
+ --
+ subtype index is integer range 0 to 3;
+ --
+ signal tOpcode_sel : index;
+ --
+ signal inInterrupt : std_logic;
+
+
+
+begin
+
+ -- generate a trace file.
+ --
+ -- This is only used in simulation to see what instructions are
+ -- executed.
+ --
+ -- a quick & dirty regression test is then to commit trace files
+ -- to CVS and compare the latest trace file against the last known
+ -- good trace file
+ traceFileGenerate : if Generate_Trace generate
+ trace_file : trace port map (
+ clk => clk,
+ begin_inst => begin_inst,
+ pc => trace_pc,
+ opcode => trace_opcode,
+ sp => trace_sp,
+ memA => trace_topOfStack,
+ memB => trace_topOfStackB,
+ busy => busy,
+ intsp => (others => 'U')
+ );
+ end generate;
+
+
+ -- mem_writeMask is not used in this design, tie it to 1
+ mem_writeMask <= (others => '1');
+
+
+
+ memAAddr_stdlogic <= std_logic_vector(memAAddr(AddrBitBRAM_range));
+ memAWrite_stdlogic <= std_logic_vector(memAWrite);
+ memBAddr_stdlogic <= std_logic_vector(memBAddr(AddrBitBRAM_range));
+ memBWrite_stdlogic <= std_logic_vector(memBWrite);
+
+
+ -- dualport_ram must be defined by the application.
+ --
+ -- How this can be implemented is highly dependent on the FPGA
+ -- and synthesis technology used.
+ --
+ -- sometimes it can be instantiated as in the
+ -- zpu/example/helloworld.vhd, using inference,
+ -- but oftentimes it must be instantiated directly
+ -- portmapping to part specific FPGA resources
+ --
+ --
+ -- DANGER!!!!!! If inference fails, then synthesis will try
+ -- to implement the memory using basic logic resources. This
+ -- will almost certainly cause the compiler to get "stuck"
+ -- since synthesising such a huge number of basic logic resources
+ -- will take more or less forever.
+ --
+ -- So: if your compiler gets "stuck" then inference is not
+ -- the way to go.
+ memory : dualport_ram port map (
+ clk => clk,
+ memAWriteEnable => memAWriteEnable,
+ memAAddr => memAAddr_stdlogic,
+ memAWrite => memAWrite_stdlogic,
+ memARead => memARead_stdlogic,
+ memBWriteEnable => memBWriteEnable,
+ memBAddr => memBAddr_stdlogic,
+ memBWrite => memBWrite_stdlogic,
+ memBRead => memBRead_stdlogic
+ );
+ memARead <= unsigned(memARead_stdlogic);
+ memBRead <= unsigned(memBRead_stdlogic);
+
+
+
+ tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0));
+
+
+
+ -- move out calculation of the opcode to a seperate process
+ -- to make things a bit easier to read
+ decodeControl : process(memBRead, pc, tOpcode_sel)
+ variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0);
+ begin
+
+ -- simplify opcode selection a bit so it passes more synthesizers
+ case (tOpcode_sel) is
+
+ when 0 => tOpcode := std_logic_vector(memBRead(31 downto 24));
+
+ when 1 => tOpcode := std_logic_vector(memBRead(23 downto 16));
+
+ when 2 => tOpcode := std_logic_vector(memBRead(15 downto 8));
+
+ when 3 => tOpcode := std_logic_vector(memBRead(7 downto 0));
+
+ when others => tOpcode := std_logic_vector(memBRead(7 downto 0));
+ end case;
+
+ sampledOpcode <= tOpcode;
+
+ if (tOpcode(7 downto 7) = OpCode_Im) then
+ sampledDecodedOpcode <= Decoded_Im;
+ elsif (tOpcode(7 downto 5) = OpCode_StoreSP) then
+ sampledDecodedOpcode <= Decoded_StoreSP;
+ elsif (tOpcode(7 downto 5) = OpCode_LoadSP) then
+ sampledDecodedOpcode <= Decoded_LoadSP;
+ elsif (tOpcode(7 downto 5) = OpCode_Emulate) then
+ sampledDecodedOpcode <= Decoded_Emulate;
+ elsif (tOpcode(7 downto 4) = OpCode_AddSP) then
+ sampledDecodedOpcode <= Decoded_AddSP;
+ else
+ case tOpcode(3 downto 0) is
+ when OpCode_Break =>
+ sampledDecodedOpcode <= Decoded_Break;
+ when OpCode_PushSP =>
+ sampledDecodedOpcode <= Decoded_PushSP;
+ when OpCode_PopPC =>
+ sampledDecodedOpcode <= Decoded_PopPC;
+ when OpCode_Add =>
+ sampledDecodedOpcode <= Decoded_Add;
+ when OpCode_Or =>
+ sampledDecodedOpcode <= Decoded_Or;
+ when OpCode_And =>
+ sampledDecodedOpcode <= Decoded_And;
+ when OpCode_Load =>
+ sampledDecodedOpcode <= Decoded_Load;
+ when OpCode_Not =>
+ sampledDecodedOpcode <= Decoded_Not;
+ when OpCode_Flip =>
+ sampledDecodedOpcode <= Decoded_Flip;
+ when OpCode_Store =>
+ sampledDecodedOpcode <= Decoded_Store;
+ when OpCode_PopSP =>
+ sampledDecodedOpcode <= Decoded_PopSP;
+ when others =>
+ sampledDecodedOpcode <= Decoded_Nop;
+ end case; -- tOpcode(3 downto 0)
+ end if; -- tOpcode
+ end process;
+
+
+ opcodeControl: process(clk, reset)
+ variable spOffset : unsigned(4 downto 0);
+ begin
+
+ if reset = '1' then
+ state <= State_Resync;
+ break <= '0';
+ sp <= unsigned(spStart(maxAddrBit downto minAddrBit));
+ pc <= (others => '0');
+ idim_flag <= '0';
+ begin_inst <= '0';
+ memAAddr <= (others => '0');
+ memBAddr <= (others => '0');
+ memAWriteEnable <= '0';
+ memBWriteEnable <= '0';
+ out_mem_writeEnable <= '0';
+ out_mem_readEnable <= '0';
+ memAWrite <= (others => '0');
+ memBWrite <= (others => '0');
+ inInterrupt <= '0';
+
+ elsif (clk'event and clk = '1') then
+ memAWriteEnable <= '0';
+ memBWriteEnable <= '0';
+ -- This saves ca. 100 LUT's, by explicitly declaring that the
+ -- memAWrite can be left at whatever value if memAWriteEnable is
+ -- not set.
+ memAWrite <= (others => DontCareValue);
+ memBWrite <= (others => DontCareValue);
+-- out_mem_addr <= (others => DontCareValue);
+-- mem_write <= (others => DontCareValue);
+ spOffset := (others => DontCareValue);
+ memAAddr <= (others => DontCareValue);
+ memBAddr <= (others => DontCareValue);
+
+ out_mem_writeEnable <= '0';
+ out_mem_readEnable <= '0';
+ begin_inst <= '0';
+ out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0));
+ mem_write <= std_logic_vector(memBRead);
+
+ decodedOpcode <= sampledDecodedOpcode;
+ opcode <= sampledOpcode;
+ if interrupt = '0' then
+ inInterrupt <= '0'; -- no longer in an interrupt
+ end if;
+
+ case state is
+
+ when State_Execute =>
+ state <= State_Fetch;
+ -- at this point:
+ -- memBRead contains opcode word
+ -- memARead contains top of stack
+ pc <= pc + 1;
+
+ -- trace
+ begin_inst <= '1';
+ trace_pc <= (others => '0');
+ trace_pc(maxAddrBit downto 0) <= std_logic_vector(pc);
+ trace_opcode <= opcode;
+ trace_sp <= (others => '0');
+ trace_sp(maxAddrBit downto minAddrBit) <= std_logic_vector(sp);
+ trace_topOfStack <= std_logic_vector(memARead);
+ trace_topOfStackB <= std_logic_vector(memBRead);
+
+ -- during the next cycle we'll be reading the next opcode
+ spOffset(4) := not opcode(4);
+ spOffset(3 downto 0) := unsigned(opcode(3 downto 0));
+
+ idim_flag <= '0';
+
+ case decodedOpcode is
+
+ when Decoded_Interrupt =>
+ sp <= sp - 1;
+ memAAddr <= sp - 1;
+ memAWriteEnable <= '1';
+ memAWrite <= (others => DontCareValue);
+ memAWrite(maxAddrBit downto 0) <= pc;
+ pc <= to_unsigned(32, maxAddrBit+1); -- interrupt address
+ report "ZPU jumped to interrupt!" severity note;
+
+ when Decoded_Im =>
+ idim_flag <= '1';
+ memAWriteEnable <= '1';
+ if (idim_flag = '0') then
+ sp <= sp - 1;
+ memAAddr <= sp-1;
+ for i in wordSize-1 downto 7 loop
+ memAWrite(i) <= opcode(6);
+ end loop;
+ memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0));
+ else
+ memAAddr <= sp;
+ memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0);
+ memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0));
+ end if; -- idim_flag
+
+ when Decoded_StoreSP =>
+ memBWriteEnable <= '1';
+ memBAddr <= sp+spOffset;
+ memBWrite <= memARead;
+ sp <= sp + 1;
+ state <= State_Resync;
+
+ when Decoded_LoadSP =>
+ sp <= sp - 1;
+ memAAddr <= sp+spOffset;
+
+ when Decoded_Emulate =>
+ sp <= sp - 1;
+ memAWriteEnable <= '1';
+ memAAddr <= sp - 1;
+ memAWrite <= (others => DontCareValue);
+ memAWrite(maxAddrBit downto 0) <= pc + 1;
+ -- The emulate address is:
+ -- 98 7654 3210
+ -- 0000 00aa aaa0 0000
+ pc <= (others => '0');
+ pc(9 downto 5) <= unsigned(opcode(4 downto 0));
+
+ when Decoded_AddSP =>
+ memAAddr <= sp;
+ memBAddr <= sp+spOffset;
+ state <= State_AddSP;
+
+ when Decoded_Break =>
+ report "Break instruction encountered" severity failure;
+ break <= '1';
+
+ when Decoded_PushSP =>
+ memAWriteEnable <= '1';
+ memAAddr <= sp - 1;
+ sp <= sp - 1;
+ memAWrite <= (others => DontCareValue);
+ memAWrite(maxAddrBit downto minAddrBit) <= sp;
+
+ when Decoded_PopPC =>
+ pc <= memARead(maxAddrBit downto 0);
+ sp <= sp + 1;
+ state <= State_Resync;
+
+ when Decoded_Add =>
+ sp <= sp + 1;
+ state <= State_Add;
+
+ when Decoded_Or =>
+ sp <= sp + 1;
+ state <= State_Or;
+
+ when Decoded_And =>
+ sp <= sp + 1;
+ state <= State_And;
+
+ when Decoded_Load =>
+ if (memARead(ioBit) = '1') then
+ out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0));
+ out_mem_readEnable <= '1';
+ state <= State_ReadIO;
+ else
+ memAAddr <= memARead(maxAddrBit downto minAddrBit);
+ end if;
+
+ when Decoded_Not =>
+ memAAddr <= sp(maxAddrBit downto minAddrBit);
+ memAWriteEnable <= '1';
+ memAWrite <= not memARead;
+
+ when Decoded_Flip =>
+ memAAddr <= sp(maxAddrBit downto minAddrBit);
+ memAWriteEnable <= '1';
+ for i in 0 to wordSize-1 loop
+ memAWrite(i) <= memARead(wordSize-1-i);
+ end loop;
+
+ when Decoded_Store =>
+ memBAddr <= sp + 1;
+ sp <= sp + 1;
+ if (memARead(ioBit) = '1') then
+ state <= State_WriteIO;
+ else
+ state <= State_Store;
+ end if;
+
+ when Decoded_PopSP =>
+ sp <= memARead(maxAddrBit downto minAddrBit);
+ state <= State_Resync;
+
+ when Decoded_Nop =>
+ memAAddr <= sp;
+
+ when others =>
+ null;
+
+ end case; -- decodedOpcode
+
+ when State_ReadIO =>
+ memAAddr <= sp;
+ if (in_mem_busy = '0') then
+ state <= State_Fetch;
+ memAWriteEnable <= '1';
+ memAWrite <= unsigned(mem_read);
+ end if;
+
+ when State_WriteIO =>
+ sp <= sp + 1;
+ out_mem_writeEnable <= '1';
+ out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0));
+ mem_write <= std_logic_vector(memBRead);
+ state <= State_WriteIODone;
+
+ when State_WriteIODone =>
+ if (in_mem_busy = '0') then
+ state <= State_Resync;
+ end if;
+
+ when State_Fetch =>
+ -- We need to resync. During the *next* cycle
+ -- we'll fetch the opcode @ pc and thus it will
+ -- be available for State_Execute the cycle after
+ -- next
+ memBAddr <= pc(maxAddrBit downto minAddrBit);
+ state <= State_FetchNext;
+
+ when State_FetchNext =>
+ -- at this point memARead contains the value that is either
+ -- from the top of stack or should be copied to the top of the stack
+ memAWriteEnable <= '1';
+ memAWrite <= memARead;
+ memAAddr <= sp;
+ memBAddr <= sp + 1;
+ state <= State_Decode;
+
+ when State_Decode =>
+ if interrupt = '1' and inInterrupt = '0' and idim_flag = '0' then
+ -- We got an interrupt, execute interrupt instead of next instruction
+ inInterrupt <= '1';
+ decodedOpcode <= Decoded_Interrupt;
+ end if;
+ -- during the State_Execute cycle we'll be fetching SP+1
+ memAAddr <= sp;
+ memBAddr <= sp + 1;
+ state <= State_Execute;
+
+ when State_Store =>
+ sp <= sp + 1;
+ memAWriteEnable <= '1';
+ memAAddr <= memARead(maxAddrBit downto minAddrBit);
+ memAWrite <= memBRead;
+ state <= State_Resync;
+
+ when State_AddSP =>
+ state <= State_Add;
+
+ when State_Add =>
+ memAAddr <= sp;
+ memAWriteEnable <= '1';
+ memAWrite <= memARead + memBRead;
+ state <= State_Fetch;
+
+ when State_Or =>
+ memAAddr <= sp;
+ memAWriteEnable <= '1';
+ memAWrite <= memARead or memBRead;
+ state <= State_Fetch;
+
+ when State_Resync =>
+ memAAddr <= sp;
+ state <= State_Fetch;
+
+ when State_And =>
+ memAAddr <= sp;
+ memAWriteEnable <= '1';
+ memAWrite <= memARead and memBRead;
+ state <= State_Fetch;
+
+ when others =>
+ null;
+
+ end case; -- state
+
+ end if; -- reset, enable
+ end process;
+
+
+
+end behave;
diff --git a/zpu/hdl/zpu4/core/zpupkg.vhd b/zpu/hdl/zpu4/core/zpupkg.vhd
new file mode 100644
index 0000000..0363aca
--- /dev/null
+++ b/zpu/hdl/zpu4/core/zpupkg.vhd
@@ -0,0 +1,218 @@
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+--
+-- The FreeBSD license
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+--
+-- 1. Redistributions of source code must retain the above copyright
+-- notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+-- copyright notice, this list of conditions and the following
+-- disclaimer in the documentation and/or other materials
+-- provided with the distribution.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.zpu_config.all;
+
+
+package zpupkg is
+
+ -- This bit is set for read/writes to IO
+ -- FIX!!! eventually this should be set to wordSize-1 so as to
+ -- to make the address of IO independent of amount of memory
+ -- reserved for CPU. Requires trivial tweaks in toolchain/runtime
+ -- libraries.
+
+ constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
+ constant maxAddrBit : integer := maxAddrBitIncIO-1;
+ constant ioBit : integer := maxAddrBit+1;
+ constant wordSize : integer := 2**wordPower;
+ constant wordBytes : integer := wordSize/8;
+ constant minAddrBit : integer := byteBits;
+ -- configurable internal stack size. Probably going to be 16 after toolchain is done
+ constant stack_bits : integer := 5;
+ constant stack_size : integer := 2**stack_bits;
+
+
+ ------------------------------------------------------------
+ -- components
+
+ component dualport_ram is
+ port (
+ clk : in std_logic;
+ memAWriteEnable : in std_logic;
+ memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+ memAWrite : in std_logic_vector(wordSize-1 downto 0);
+ memARead : out std_logic_vector(wordSize-1 downto 0);
+ memBWriteEnable : in std_logic;
+ memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+ memBWrite : in std_logic_vector(wordSize-1 downto 0);
+ memBRead : out std_logic_vector(wordSize-1 downto 0)
+ );
+ end component dualport_ram;
+
+
+ component dram is
+ port (
+ clk : in std_logic;
+ areset : in std_logic;
+ mem_writeEnable : in std_logic;
+ mem_readEnable : in std_logic;
+ mem_addr : in std_logic_vector(maxAddrBit downto 0);
+ mem_write : in std_logic_vector(wordSize-1 downto 0);
+ mem_read : out std_logic_vector(wordSize-1 downto 0);
+ mem_busy : out std_logic;
+ mem_writeMask : in std_logic_vector(wordBytes-1 downto 0)
+ );
+ end component dram;
+
+
+ component trace is
+ port (
+ clk : in std_logic;
+ begin_inst : in std_logic;
+ pc : in std_logic_vector(maxAddrBitIncIO downto 0);
+ opcode : in std_logic_vector(7 downto 0);
+ sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+ memA : in std_logic_vector(wordSize-1 downto 0);
+ memB : in std_logic_vector(wordSize-1 downto 0);
+ busy : in std_logic;
+ intSp : in std_logic_vector(stack_bits-1 downto 0)
+ );
+ end component trace;
+
+
+ component zpu_core is
+ port (
+ clk : in std_logic;
+ reset : in std_logic;
+ enable : in std_logic;
+ in_mem_busy : in std_logic;
+ mem_read : in std_logic_vector(wordSize-1 downto 0);
+ mem_write : out std_logic_vector(wordSize-1 downto 0);
+ out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0);
+ out_mem_writeEnable : out std_logic;
+ out_mem_readEnable : out std_logic;
+ mem_writeMask : out std_logic_vector(wordBytes-1 downto 0);
+ interrupt : in std_logic;
+ break : out std_logic
+ );
+ end component zpu_core;
+
+
+ component timer is
+ port (
+ clk : in std_logic;
+ areset : in std_logic;
+ we : in std_logic;
+ din : in std_logic_vector(7 downto 0);
+ adr : in std_logic_vector(2 downto 0);
+ dout : out std_logic_vector(7 downto 0)
+ );
+ end component timer;
+
+
+ component zpuio is
+ port (
+ areset : in std_logic;
+ cpu_clk : in std_logic;
+ clk_status : in std_logic_vector(2 downto 0);
+ cpu_din : in std_logic_vector(15 downto 0);
+ cpu_a : in std_logic_vector(20 downto 0);
+ cpu_we : in std_logic_vector(1 downto 0);
+ cpu_re : in std_logic;
+ cpu_dout : inout std_logic_vector(15 downto 0)
+ );
+ end component zpuio;
+
+
+ ------------------------------------------------------------
+ -- constants
+
+ -- opcode decode constants
+ constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
+ constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
+ constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
+ constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
+ constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
+ constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
+ --
+ constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
+ constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
+ constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
+ constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
+ --
+ constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
+ constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
+ constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
+ constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
+ --
+ constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
+ constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
+ constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
+ constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
+ --
+ constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
+ constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
+ constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
+ constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
+ --
+ constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
+ constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
+ constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
+ constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
+ --
+ constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
+ constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
+ --
+ constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
+ constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
+ constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
+ constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
+ --
+ constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
+ constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
+ --
+ constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
+ constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
+ constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
+ --
+ constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
+ constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
+ constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
+ --
+ constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
+ constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
+ constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
+ --
+ --
+ constant OpCode_Size : integer := 8;
+
+
+
+end zpupkg;
diff --git a/zpu/hdl/zpu4/src/.cvsignore b/zpu/hdl/zpu4/src/.cvsignore
new file mode 100644
index 0000000..41c40a0
--- /dev/null
+++ b/zpu/hdl/zpu4/src/.cvsignore
@@ -0,0 +1,5 @@
+work
+vsim.wlf
+xilinx_device_details.xml
+tcl_stacktrace.txt
+vish_stacktrace.vstf
diff --git a/zpu/hdl/zpu4/src/clocks.vhd b/zpu/hdl/zpu4/src/clocks.vhd
new file mode 100644
index 0000000..67433be
--- /dev/null
+++ b/zpu/hdl/zpu4/src/clocks.vhd
@@ -0,0 +1,198 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library unisim;
+use unisim.vcomponents.ibufg;
+use unisim.vcomponents.srl16;
+use unisim.vcomponents.dcm;
+use unisim.vcomponents.bufg;
+
+
+entity clocks is
+ port (
+ areset : in std_logic;
+ cpu_clk_p : in std_logic;
+ sdr_clk_fb_p : in std_logic;
+ cpu_clk : out std_logic;
+ cpu_clk_2x : out std_logic;
+ cpu_clk_4x : out std_logic;
+ ddr_in_clk : out std_logic;
+ ddr_in_clk_2x : out std_logic;
+ locked : out std_logic_vector(2 downto 0)
+ );
+end entity clocks;
+
+architecture behave of clocks is
+
+ signal low : std_logic;
+ --
+ signal cpu_clk_in : std_logic;
+ signal sdr_clk_fb_in : std_logic;
+ --
+ signal dcm_cpu1 : std_logic;
+ signal dcm_cpu2 : std_logic;
+ signal dcm_cpu2_dum : std_logic;
+ signal dcm_cpu4 : std_logic;
+ signal dcm_ddr2 : std_logic;
+ signal dcm_ddr2_2x : std_logic;
+ --
+ signal cpu_clk_int : std_logic;
+ signal cpu_clk_2x_int : std_logic;
+ signal cpu_clk_2x_dum_int : std_logic;
+ signal cpu_clk_4x_int : std_logic;
+ signal ddr_in_clk_int : std_logic;
+ signal ddr_in_clk_2x_int : std_logic;
+ --
+ signal dcm1_locked_del : std_logic;
+ signal dcm2_locked_del : std_logic;
+ signal dcm2_reset : std_logic;
+ signal dcm3_reset : std_logic;
+ --
+ signal locked_int : std_logic_vector(2 downto 0);
+ signal del_addr : std_logic_vector(3 downto 0);
+
+begin
+
+ low <= '0';
+ del_addr <= "1111";
+ --
+ cpu_clk <= cpu_clk_int;
+ cpu_clk_2x <= cpu_clk_2x_int;
+ cpu_clk_4x <= cpu_clk_4x_int;
+ ddr_in_clk <= ddr_in_clk_int;
+ ddr_in_clk_2x <= ddr_in_clk_2x_int;
+ locked <= locked_int;
+
+
+ cpu_ibufg : ibufg
+ port map (
+ O => cpu_clk_in,
+ I => cpu_clk_p
+ );
+
+ sdr_fb_ibufg : ibufg
+ port map (
+ O => sdr_clk_fb_in,
+ I => sdr_clk_fb_p
+ );
+
+ dcm2_rst : srl16
+ generic map (
+ init => x"0000"
+ )
+ port map (
+ Q => dcm1_locked_del,
+ A0 => del_addr(0),
+ A1 => del_addr(1),
+ A2 => del_addr(2),
+ A3 => del_addr(3),
+ CLK => cpu_clk_int,
+ D => locked_int(0)
+ );
+
+ dcm2_reset <= not(dcm1_locked_del);
+
+ dcm3_rst : srl16
+ generic map (
+ init => x"0000"
+ )
+ port map (
+ Q => dcm2_locked_del,
+ A0 => del_addr(0),
+ A1 => del_addr(1),
+ A2 => del_addr(2),
+ A3 => del_addr(3),
+ CLK => cpu_clk_int,
+ D => locked_int(1)
+ );
+
+ dcm3_reset <= not(dcm2_locked_del);
+
+ cpu1_dcm :
+ dcm generic map (
+ clkin_period => 15.625, -- Specify period of input clock
+ factory_jf => X"8080" -- FACTORY JF Values
+ )
+ port map (
+ clk0 => dcm_cpu1, -- 0 degree DCM CLK ouptput
+ clk2x => dcm_cpu2, -- 2X DCM CLK output
+ locked => locked_int(0), -- DCM LOCK status output
+ clkfb => cpu_clk_int, -- DCM clock feedback
+ clkin => cpu_clk_in, -- Clock input (from IBUFG, BUFG or DCM)
+ psclk => low, -- Dynamic phase adjust clock input
+ psen => low, -- Dynamic phase adjust enable input
+ psincdec => low, -- Dynamic phase adjust increment/decrement
+ rst => areset -- DCM asynchronous reset input
+ );
+
+ cpu2_dcm : dcm
+ generic map (
+ clkin_period => 7.8125, -- Specify period of input clock
+ factory_jf => X"8080" -- FACTORY JF Values
+ )
+ port map (
+ clk0 => dcm_cpu2_dum, -- 0 degree DCM CLK ouptput
+ clk2x => dcm_cpu4, -- 2X DCM CLK output
+ locked => locked_int(1), -- DCM LOCK status output
+ clkfb => cpu_clk_2x_dum_int, -- DCM clock feedback
+ clkin => cpu_clk_2x_int, -- Clock input (from IBUFG, BUFG or DCM)
+ psclk => low, -- Dynamic phase adjust clock input
+ psen => low, -- Dynamic phase adjust enable input
+ psincdec => low, -- Dynamic phase adjust increment/decrement
+ rst => dcm2_reset -- DCM asynchronous reset input
+ );
+
+ ddr_read_dcm : dcm
+ generic map (
+ clkin_period => 7.8125, -- Specify period of input clock
+ clkout_phase_shift => "FIXED", -- Specify phase shift of NONE, FIXED or VARIABLE
+ factory_jf => X"8080", -- FACTORY JF Values
+ phase_shift => 103 -- Amount of fixed phase shift from -255 to 255
+ )
+ port map (
+ clk0 => dcm_ddr2, -- 0 degree DCM CLK ouptput
+ clk2x => dcm_ddr2_2x, -- 2X DCM CLK output
+ locked => locked_int(2), -- DCM LOCK status output
+ clkfb => ddr_in_clk_int, -- DCM clock feedback
+ clkin => sdr_clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM)
+ psclk => low, -- Dynamic phase adjust clock input
+ psen => low, -- Dynamic phase adjust enable input
+ psincdec => low, -- Dynamic phase adjust increment/decrement
+ rst => dcm3_reset -- DCM asynchronous reset input
+ );
+
+ cpu1 : bufg
+ port map (
+ I => dcm_cpu1,
+ O => cpu_clk_int
+ );
+
+ cpu2 : bufg
+ port map (
+ I => dcm_cpu2,
+ O => cpu_clk_2x_int
+ );
+
+ cpu2_dum : bufg
+ port map (
+ i => dcm_cpu2_dum,
+ o => cpu_clk_2x_dum_int
+ );
+
+ cpu4 : bufg
+ port map (
+ i => dcm_cpu4,
+ o => cpu_clk_4x_int
+ );
+
+ ddr_clk : bufg port map (
+ i => dcm_ddr2,
+ o => ddr_in_clk_int
+ );
+
+ ddr_clk_2x : bufg port map (
+ i => dcm_ddr2_2x,
+ o => ddr_in_clk_2x_int
+ );
+
+end architecture behave;
diff --git a/zpu/hdl/zpu4/src/io.vhd b/zpu/hdl/zpu4/src/io.vhd
new file mode 100644
index 0000000..56c7fb5
--- /dev/null
+++ b/zpu/hdl/zpu4/src/io.vhd
@@ -0,0 +1,119 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use std.textio.all;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+use work.txt_util.all;
+
+
+entity zpu_io is
+ generic (
+ log_file : string := "log.txt"
+ );
+ port(
+ clk : in std_logic;
+ areset : in std_logic;
+ busy : out std_logic;
+ writeEnable : in std_logic;
+ readEnable : in std_logic;
+ write : in std_logic_vector(wordSize-1 downto 0);
+ read : out std_logic_vector(wordSize-1 downto 0);
+ addr : in std_logic_vector(maxAddrBit downto minAddrBit)
+ );
+end entity zpu_io;
+
+
+architecture behave of zpu_io is
+
+ signal timer_read : std_logic_vector(7 downto 0);
+ signal timer_we : std_logic;
+ --
+ signal serving : std_logic;
+ --
+ file l_file : text open write_mode is log_file;
+ constant lowAddrBits : std_logic_vector(minAddrBit-1 downto 0) := (others => '0');
+ constant tx_full : std_logic := '0';
+ constant rx_empty : std_logic := '1';
+
+begin
+
+
+ timerinst : timer
+ port map (
+ clk => clk,
+ areset => areset,
+ we => timer_we,
+ din => write(7 downto 0),
+ adr => addr(4 downto 2),
+ dout => timer_read
+ );
+
+ busy <= writeEnable or readEnable;
+ timer_we <= writeEnable and addr(12);
+
+ process(areset, clk)
+ variable taddr : std_logic_vector(maxAddrBit downto 0);
+ -- pragma translate_off
+ variable line_out : line := new string'("");
+ variable char : character;
+ -- pragma translate_on
+ begin
+ taddr := (others => '0');
+ taddr(maxAddrBit downto minAddrBit) := addr;
+
+ if (areset = '1') then
+ elsif (clk'event and clk = '1') then
+ if writeEnable = '1' then
+ -- external interface (fixed address)
+ --<JK> extend compare to avoid waring messages
+ if ("1" & addr & lowAddrBits) = x"80a000c" then
+ -- Write to UART
+ report "Write to UART[0]" & " :0x" & hstr(write);
+ -- pragma translate_off
+ char := character'val(to_integer(unsigned(write)));
+ if char = lf then
+ std.textio.writeline(l_file, line_out);
+ else
+ std.textio.write(line_out, char);
+ end if;
+ -- pragma translate_on
+
+ elsif addr(12) = '1' then
+ report "Write to TIMER" & " :0x" & hstr(write);
+
+ else
+
+ report "Illegal IO write @" & "0x" & hstr(taddr) severity warning;
+ end if;
+
+ end if;
+ read <= (others => '0');
+ if (readEnable = '1') then
+ --<JK> extend compare to avoid waring messages
+ if ("1" & addr & lowAddrBits) = x"80a000c" then
+ report "Read UART[0]";
+ read(8) <= not tx_full; -- output fifo not full
+ read(9) <= not rx_empty; -- receiver not empty
+ elsif ("1" & addr & lowAddrBits) = x"80a0010" then
+ report "Read UART[1]";
+ read(8) <= not rx_empty; -- receiver not empty
+ read(7 downto 0) <= (others => '0');
+ elsif addr(12) = '1' then
+ report "Read TIMER";
+ read(7 downto 0) <= timer_read;
+ elsif addr(11) = '1' then
+ report "Read ZPU Freq";
+ read(7 downto 0) <= ZPU_Frequency;
+ else
+ report "Illegal IO read @" & "0x" & hstr(taddr) severity warning;
+ end if;
+ end if;
+ end if;
+ end process;
+
+end architecture behave;
+
diff --git a/zpu/hdl/zpu4/src/timer.vhd b/zpu/hdl/zpu4/src/timer.vhd
new file mode 100644
index 0000000..d6d9358
--- /dev/null
+++ b/zpu/hdl/zpu4/src/timer.vhd
@@ -0,0 +1,61 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity timer is
+ port(
+ clk : in std_logic;
+ areset : in std_logic;
+ we : in std_logic;
+ din : in std_logic_vector(7 downto 0);
+ adr : in std_logic_vector(2 downto 0);
+ dout : out std_logic_vector(7 downto 0)
+ );
+end entity timer;
+
+
+architecture behave of timer is
+
+ signal sample : std_logic;
+ signal reset : std_logic;
+ --
+ signal cnt : unsigned(63 downto 0);
+ signal cnt_smp : std_logic_vector(63 downto 0);
+
+begin
+
+ reset <= '1' when (we = '1' and din(0) = '1') else '0';
+ sample <= '1' when (we = '1' and din(1) = '1') else '0';
+
+ process(clk, areset) -- Carry generation
+ begin
+ if areset = '1' then
+ cnt <= (others => '0');
+ cnt_smp <= (others => '0');
+ elsif rising_edge(clk) then
+ cnt <= cnt + 1;
+ if sample = '1' then
+-- report "sampling" severity failure;
+ cnt_smp <= std_logic_vector(cnt);
+ end if;
+ end if;
+ end process;
+
+
+ process(cnt_smp, adr)
+ begin
+ case adr is
+ when "000" => dout <= cnt_smp(7 downto 0);
+ when "001" => dout <= cnt_smp(15 downto 8);
+ when "010" => dout <= cnt_smp(23 downto 16);
+ when "011" => dout <= cnt_smp(31 downto 24);
+ when "100" => dout <= cnt_smp(39 downto 32);
+ when "101" => dout <= cnt_smp(47 downto 40);
+ when "110" => dout <= cnt_smp(55 downto 48);
+ when others => dout <= cnt_smp(63 downto 56);
+ end case;
+ end process;
+
+
+end architecture behave;
+
diff --git a/zpu/hdl/zpu4/src/trace.vhd b/zpu/hdl/zpu4/src/trace.vhd
new file mode 100644
index 0000000..01678c8
--- /dev/null
+++ b/zpu/hdl/zpu4/src/trace.vhd
@@ -0,0 +1,107 @@
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+--
+-- The FreeBSD license
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+--
+-- 1. Redistributions of source code must retain the above copyright
+-- notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+-- copyright notice, this list of conditions and the following
+-- disclaimer in the documentation and/or other materials
+-- provided with the distribution.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use std.textio.all;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+use work.txt_util.all;
+
+
+entity trace is
+ generic (
+ log_file : string := "trace.txt"
+ );
+ port(
+ clk : in std_logic;
+ begin_inst : in std_logic;
+ pc : in std_logic_vector(maxAddrBitIncIO downto 0);
+ opcode : in std_logic_vector(7 downto 0);
+ sp : in std_logic_vector(maxAddrBitIncIO downto 2);
+ memA : in std_logic_vector(wordSize-1 downto 0);
+ memB : in std_logic_vector(wordSize-1 downto 0);
+ busy : in std_logic;
+ intSp : in std_logic_vector(stack_bits-1 downto 0)
+ );
+end entity trace;
+
+
+architecture behave of trace is
+
+ file l_file : text open write_mode is log_file;
+
+begin
+
+ -- write data and control information to a file
+ receive_data : process
+ variable l : line;
+ variable t : std_logic_vector(wordSize-1 downto 0);
+ variable t2 : std_logic_vector(maxAddrBitIncIO downto 0);
+ variable counter : unsigned(63 downto 0);
+ begin
+
+ t := (others => '0');
+ t2 := (others => '0');
+
+ counter := (others => '0');
+
+ -- print header for the logfile
+ print(l_file, "#pc,opcode,sp,top_of_stack ");
+ print(l_file, "#----------");
+ print(l_file, " ");
+
+ wait until clk = '1';
+ wait until clk = '0';
+
+ while true loop
+
+ counter := counter + 1;
+ if begin_inst = '1' then
+ t(maxAddrBitIncIO downto 2) := sp;
+ t2 := pc;
+ print(l_file, "0x" & hstr(t2) & " 0x" & hstr(opcode) & " 0x" & hstr(t) & " 0x" & hstr(memA) & " 0x" & hstr(memB) & " 0x" & hstr(intSp) & " 0x" & hstr(std_logic_vector(counter)));
+ end if;
+
+ wait until clk = '0';
+
+ end loop;
+ end process receive_data;
+
+end architecture behave;
+
diff --git a/zpu/hdl/zpu4/src/txt_util.vhd b/zpu/hdl/zpu4/src/txt_util.vhd
new file mode 100644
index 0000000..4dca901
--- /dev/null
+++ b/zpu/hdl/zpu4/src/txt_util.vhd
@@ -0,0 +1,539 @@
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+--
+-- The FreeBSD license
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+--
+-- 1. Redistributions of source code must retain the above copyright
+-- notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+-- copyright notice, this list of conditions and the following
+-- disclaimer in the documentation and/or other materials
+-- provided with the distribution.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use std.textio.all;
+
+
+package txt_util is
+
+ -- prints a message to the screen
+ procedure print(text : string);
+
+ -- prints the message when active
+ -- useful for debug switches
+ procedure print(active : boolean; text : string);
+
+ -- converts std_logic into a character
+ function chr(sl : std_logic) return character;
+
+ -- converts std_logic into a string (1 to 1)
+ function str(sl : std_logic) return string;
+
+ -- converts std_logic_vector into a string (binary base)
+ function str(slv : std_logic_vector) return string;
+
+ -- converts boolean into a string
+ function str(b : boolean) return string;
+
+ -- converts an integer into a single character
+ -- (can also be used for hex conversion and other bases)
+ function chr(int : integer) return character;
+
+ -- converts integer into string using specified base
+ function str(int : integer; base : integer) return string;
+
+ -- converts integer to string, using base 10
+ function str(int : integer) return string;
+
+ -- convert std_logic_vector into a string in hex format
+ function hstr(slv : std_logic_vector) return string;
+
+
+ -- functions to manipulate strings
+ -----------------------------------
+
+ -- convert a character to upper case
+ function to_upper(c : character) return character;
+
+ -- convert a character to lower case
+ function to_lower(c : character) return character;
+
+ -- convert a string to upper case
+ function to_upper(s : string) return string;
+
+ -- convert a string to lower case
+ function to_lower(s : string) return string;
+
+
+
+ -- functions to convert strings into other formats
+ --------------------------------------------------
+
+ -- converts a character into std_logic
+ function to_std_logic(c : character) return std_logic;
+
+ -- converts a string into std_logic_vector
+ function to_std_logic_vector(s : string) return std_logic_vector;
+
+
+
+ -- file I/O
+ -----------
+
+ -- read variable length string from input file
+ procedure str_read(file in_file : text; res_string : out string);
+
+ -- print string to a file and start new line
+ procedure print(file out_file : text; new_string : in string);
+
+ -- print character to a file and start new line
+ procedure print(file out_file : text; char : in character);
+
+end package txt_util;
+
+
+
+
+package body txt_util is
+
+
+ -- prints text to the screen
+ procedure print(text : string) is
+ variable msg_line : line;
+ begin
+ write(msg_line, text);
+ writeline(output, msg_line);
+ end procedure print;
+
+
+ -- prints text to the screen when active
+ procedure print(active : boolean; text : string) is
+ begin
+ if active then
+ print(text);
+ end if;
+ end procedure print;
+
+
+ -- converts std_logic into a character
+ function chr(sl : std_logic) return character is
+ variable c : character;
+ begin
+ case sl is
+ when 'U' => c := 'U';
+ when 'X' => c := 'X';
+ when '0' => c := '0';
+ when '1' => c := '1';
+ when 'Z' => c := 'Z';
+ when 'W' => c := 'W';
+ when 'L' => c := 'L';
+ when 'H' => c := 'H';
+ when '-' => c := '-';
+ end case;
+ return c;
+ end function chr;
+
+
+ -- converts std_logic into a string (1 to 1)
+ function str(sl : std_logic) return string is
+ variable s : string(1 to 1);
+ begin
+ s(1) := chr(sl);
+ return s;
+ end function str;
+
+
+ -- converts std_logic_vector into a string (binary base)
+ -- (this also takes care of the fact that the range of
+ -- a string is natural while a std_logic_vector may
+ -- have an integer range)
+ function str(slv : std_logic_vector) return string is
+ variable result : string (1 to slv'length);
+ variable r : integer;
+ begin
+ r := 1;
+ for i in slv'range loop
+ result(r) := chr(slv(i));
+ r := r + 1;
+ end loop;
+ return result;
+ end function str;
+
+
+ function str(b : boolean) return string is
+ begin
+ if b then
+ return "true";
+ else
+ return "false";
+ end if;
+ end function str;
+
+
+ -- converts an integer into a character
+ -- for 0 to 9 the obvious mapping is used, higher
+ -- values are mapped to the characters A-Z
+ -- (this is usefull for systems with base > 10)
+ -- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
+ function chr(int : integer) return character is
+ variable c : character;
+ begin
+ case int is
+ when 0 => c := '0';
+ when 1 => c := '1';
+ when 2 => c := '2';
+ when 3 => c := '3';
+ when 4 => c := '4';
+ when 5 => c := '5';
+ when 6 => c := '6';
+ when 7 => c := '7';
+ when 8 => c := '8';
+ when 9 => c := '9';
+ when 10 => c := 'A';
+ when 11 => c := 'B';
+ when 12 => c := 'C';
+ when 13 => c := 'D';
+ when 14 => c := 'E';
+ when 15 => c := 'F';
+ when 16 => c := 'G';
+ when 17 => c := 'H';
+ when 18 => c := 'I';
+ when 19 => c := 'J';
+ when 20 => c := 'K';
+ when 21 => c := 'L';
+ when 22 => c := 'M';
+ when 23 => c := 'N';
+ when 24 => c := 'O';
+ when 25 => c := 'P';
+ when 26 => c := 'Q';
+ when 27 => c := 'R';
+ when 28 => c := 'S';
+ when 29 => c := 'T';
+ when 30 => c := 'U';
+ when 31 => c := 'V';
+ when 32 => c := 'W';
+ when 33 => c := 'X';
+ when 34 => c := 'Y';
+ when 35 => c := 'Z';
+ when others => c := '?';
+ end case;
+ return c;
+ end function chr;
+
+
+ -- convert integer to string using specified base
+ -- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
+ function str(int : integer; base : integer) return string is
+ variable temp : string(1 to 10);
+ variable num : integer;
+ variable abs_int : integer;
+ variable len : integer := 1;
+ variable power : integer := 1;
+ begin
+
+ -- bug fix for negative numbers
+ abs_int := abs(int);
+
+ num := abs_int;
+
+ while num >= base loop -- Determine how many
+ len := len + 1; -- characters required
+ num := num / base; -- to represent the
+ end loop; -- number.
+
+ for i in len downto 1 loop -- Convert the number to
+ temp(i) := chr(abs_int/power mod base); -- a string starting
+ power := power * base; -- with the right hand
+ end loop; -- side.
+
+ -- return result and add sign if required
+ if int < 0 then
+ return '-'& temp(1 to len);
+ else
+ return temp(1 to len);
+ end if;
+
+ end function str;
+
+
+ -- convert integer to string, using base 10
+ function str(int : integer) return string is
+ begin
+ return str(int, 10);
+ end function str;
+
+
+ -- converts a std_logic_vector into a hex string.
+ function hstr(slv : std_logic_vector) return string is
+ variable hexlen : integer;
+ variable longslv : std_logic_vector(67 downto 0) := (others => '0');
+ variable hex : string(1 to 16);
+ variable fourbit : std_logic_vector(3 downto 0);
+ begin
+ hexlen := (slv'left+1)/4;
+ if (slv'left+1) mod 4 /= 0 then
+ hexlen := hexlen + 1;
+ end if;
+ longslv(slv'left downto 0) := slv;
+ for i in (hexlen -1) downto 0 loop
+ fourbit := longslv(((i*4)+3) downto (i*4));
+ case fourbit is
+ when "0000" => hex(hexlen -I) := '0';
+ when "0001" => hex(hexlen -I) := '1';
+ when "0010" => hex(hexlen -I) := '2';
+ when "0011" => hex(hexlen -I) := '3';
+ when "0100" => hex(hexlen -I) := '4';
+ when "0101" => hex(hexlen -I) := '5';
+ when "0110" => hex(hexlen -I) := '6';
+ when "0111" => hex(hexlen -I) := '7';
+ when "1000" => hex(hexlen -I) := '8';
+ when "1001" => hex(hexlen -I) := '9';
+ when "1010" => hex(hexlen -I) := 'A';
+ when "1011" => hex(hexlen -I) := 'B';
+ when "1100" => hex(hexlen -I) := 'C';
+ when "1101" => hex(hexlen -I) := 'D';
+ when "1110" => hex(hexlen -I) := 'E';
+ when "1111" => hex(hexlen -I) := 'F';
+ when "ZZZZ" => hex(hexlen -I) := 'z';
+ when "UUUU" => hex(hexlen -I) := 'u';
+ when "XXXX" => hex(hexlen -I) := 'x';
+ when others => hex(hexlen -I) := '?';
+ end case;
+ end loop;
+ return hex(1 to hexlen);
+ end function hstr;
+
+
+
+ -- functions to manipulate strings
+ -----------------------------------
+
+ -- convert a character to upper case
+ function to_upper(c : character) return character is
+ variable u : character;
+ begin
+ case c is
+ when 'a' => u := 'A';
+ when 'b' => u := 'B';
+ when 'c' => u := 'C';
+ when 'd' => u := 'D';
+ when 'e' => u := 'E';
+ when 'f' => u := 'F';
+ when 'g' => u := 'G';
+ when 'h' => u := 'H';
+ when 'i' => u := 'I';
+ when 'j' => u := 'J';
+ when 'k' => u := 'K';
+ when 'l' => u := 'L';
+ when 'm' => u := 'M';
+ when 'n' => u := 'N';
+ when 'o' => u := 'O';
+ when 'p' => u := 'P';
+ when 'q' => u := 'Q';
+ when 'r' => u := 'R';
+ when 's' => u := 'S';
+ when 't' => u := 'T';
+ when 'u' => u := 'U';
+ when 'v' => u := 'V';
+ when 'w' => u := 'W';
+ when 'x' => u := 'X';
+ when 'y' => u := 'Y';
+ when 'z' => u := 'Z';
+ when others => u := c;
+ end case;
+ return u;
+ end function to_upper;
+
+
+ -- convert a character to lower case
+ function to_lower(c : character) return character is
+ variable l : character;
+ begin
+ case c is
+ when 'A' => l := 'a';
+ when 'B' => l := 'b';
+ when 'C' => l := 'c';
+ when 'D' => l := 'd';
+ when 'E' => l := 'e';
+ when 'F' => l := 'f';
+ when 'G' => l := 'g';
+ when 'H' => l := 'h';
+ when 'I' => l := 'i';
+ when 'J' => l := 'j';
+ when 'K' => l := 'k';
+ when 'L' => l := 'l';
+ when 'M' => l := 'm';
+ when 'N' => l := 'n';
+ when 'O' => l := 'o';
+ when 'P' => l := 'p';
+ when 'Q' => l := 'q';
+ when 'R' => l := 'r';
+ when 'S' => l := 's';
+ when 'T' => l := 't';
+ when 'U' => l := 'u';
+ when 'V' => l := 'v';
+ when 'W' => l := 'w';
+ when 'X' => l := 'x';
+ when 'Y' => l := 'y';
+ when 'Z' => l := 'z';
+ when others => l := c;
+ end case;
+ return l;
+ end function to_lower;
+
+
+ -- convert a string to upper case
+ function to_upper(s : string) return string is
+ variable uppercase : string (s'range);
+ begin
+
+ for i in s'range loop
+ uppercase(i) := to_upper(s(i));
+ end loop;
+ return uppercase;
+
+ end function to_upper;
+
+
+ -- convert a string to lower case
+ function to_lower(s : string) return string is
+ variable lowercase : string (s'range);
+ begin
+ for i in s'range loop
+ lowercase(i) := to_lower(s(i));
+ end loop;
+ return lowercase;
+ end function to_lower;
+
+
+
+ -- functions to convert strings into other types
+ ------------------------------------------------
+
+ -- converts a character into a std_logic
+ function to_std_logic(c : character) return std_logic is
+ variable sl : std_logic;
+ begin
+ case c is
+ when 'U' =>
+ sl := 'U';
+ when 'X' =>
+ sl := 'X';
+ when '0' =>
+ sl := '0';
+ when '1' =>
+ sl := '1';
+ when 'Z' =>
+ sl := 'Z';
+ when 'W' =>
+ sl := 'W';
+ when 'L' =>
+ sl := 'L';
+ when 'H' =>
+ sl := 'H';
+ when '-' =>
+ sl := '-';
+ when others =>
+ sl := 'X';
+ end case;
+ return sl;
+ end function to_std_logic;
+
+
+ -- converts a string into std_logic_vector
+ function to_std_logic_vector(s : string) return std_logic_vector is
+ variable slv : std_logic_vector(s'high-s'low downto 0);
+ variable k : integer;
+ begin
+ k := s'high-s'low;
+ for i in s'range loop
+ slv(k) := to_std_logic(s(i));
+ k := k - 1;
+ end loop;
+ return slv;
+ end function to_std_logic_vector;
+
+
+
+ -- file I/O
+ -------------
+
+ -- read variable length string from input file
+ procedure str_read(file in_file : text; res_string : out string) is
+ variable l : line;
+ variable c : character;
+ variable is_string : boolean;
+ begin
+ readline(in_file, l);
+ -- clear the contents of the result string
+ for i in res_string'range loop
+ res_string(i) := ' ';
+ end loop;
+ -- read all characters of the line, up to the length
+ -- of the results string
+ for i in res_string'range loop
+ read(l, c, is_string);
+ res_string(i) := c;
+ if not is_string then -- found end of line
+ exit;
+ end if;
+ end loop;
+ end procedure str_read;
+
+
+ -- print string to a file
+ procedure print(file out_file : text; new_string : in string) is
+ variable l : line;
+ begin
+ write(l, new_string);
+ writeline(out_file, l);
+ end procedure print;
+
+
+ -- print character to a file and start new line
+ procedure print(file out_file : text; char : in character) is
+ variable l : line;
+ begin
+ write(l, char);
+ writeline(out_file, l);
+ end procedure print;
+
+
+ -- appends contents of a string to a file until line feed occurs
+ -- (LF is considered to be the end of the string)
+ procedure str_write(file out_file : text; new_string : in string) is
+ begin
+ for i in new_string'range loop
+ print(out_file, new_string(i));
+ if new_string(i) = LF then -- end of string
+ exit;
+ end if;
+ end loop;
+ end procedure str_write;
+
+
+end package body txt_util;
+
diff --git a/zpu/hdl/zpu4/src/zpuio.vhd b/zpu/hdl/zpu4/src/zpuio.vhd
new file mode 100644
index 0000000..9ca9050
--- /dev/null
+++ b/zpu/hdl/zpu4/src/zpuio.vhd
@@ -0,0 +1,218 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity zpuio is
+ port (
+ areset : in std_logic;
+ cpu_clk : in std_logic;
+ clk_status : in std_logic_vector(2 downto 0);
+ cpu_din : in std_logic_vector(15 downto 0);
+ cpu_a : in std_logic_vector(20 downto 0);
+ cpu_we : in std_logic_vector(1 downto 0);
+ cpu_re : in std_logic;
+ cpu_dout : inout std_logic_vector(15 downto 0)
+ );
+end zpuio;
+
+architecture behave of zpuio is
+
+ signal timer_read : std_logic_vector(7 downto 0);
+ signal timer_we : std_logic;
+ --
+ signal io_busy : std_logic;
+ signal io_read : std_logic_vector(7 downto 0);
+ signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit);
+ signal io_writeEnable : std_logic;
+ signal Enable : std_logic;
+ --
+ signal din : std_logic_vector(7 downto 0);
+ signal dout : std_logic_vector(7 downto 0);
+ signal adr : std_logic_vector(15 downto 0);
+ signal break : std_logic;
+ signal we : std_logic;
+ signal re : std_logic;
+ --
+ -- uart forwarding...
+ signal uartTXPending : std_logic;
+ signal uartTXCleared : std_logic;
+ signal uartData : std_logic_vector(7 downto 0);
+ --
+ signal readingTimer : std_logic;
+ --
+ --
+ signal mem_busy : std_logic;
+ signal mem_read : std_logic_vector(wordSize-1 downto 0);
+ signal mem_write : std_logic_vector(wordSize-1 downto 0);
+ signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);
+ signal mem_writeEnable : std_logic;
+ signal mem_readEnable : std_logic;
+ signal mem_writeMask : std_logic_vector(wordBytes-1 downto 0);
+ --
+ signal dram_mem_busy : std_logic;
+ signal dram_mem_read : std_logic_vector(wordSize-1 downto 0);
+ signal dram_mem_write : std_logic_vector(wordSize-1 downto 0);
+ signal dram_mem_writeEnable : std_logic;
+ signal dram_mem_readEnable : std_logic;
+ signal dram_mem_writeMask : std_logic_vector(wordBytes-1 downto 0);
+ --
+ signal io_readEnable : std_logic;
+ --
+ signal dram_read : std_logic;
+
+begin
+
+ io_addr <= mem_addr(maxAddrBit downto minAddrBit);
+
+ timerinst : timer
+ port map (
+ clk => cpu_clk,
+ areset => areset,
+ we => timer_we,
+ din => mem_write(7 downto 0),
+ adr => io_addr(4 downto 2),
+ dout => timer_read
+ );
+
+ zpu : zpu_core
+ port map (
+ clk => cpu_clk ,
+ areset => areset,
+ in_mem_busy => mem_busy,
+ mem_read => mem_read,
+ mem_write => mem_write,
+ out_mem_addr => mem_addr,
+ out_mem_writeEnable => mem_writeEnable,
+ out_mem_readEnable => mem_readEnable,
+ mem_writeMask => mem_writeMask,
+ interrupt => '0',
+ break => break
+ );
+
+
+ ram_imp : dram
+ port map (
+ clk => cpu_clk,
+ areset => areset,
+ mem_busy => dram_mem_busy,
+ mem_read => dram_mem_read,
+ mem_write => mem_write,
+ mem_addr => mem_addr(maxAddrBit downto 0),
+ mem_writeEnable => dram_mem_writeEnable,
+ mem_readEnable => dram_mem_readEnable,
+ mem_writeMask => mem_writeMask
+ );
+
+
+ fauxUart : process(cpu_clk, areset)
+ begin
+ if areset = '1' then
+ io_busy <= '0';
+ uartTXPending <= '0';
+ timer_we <= '0';
+ io_busy <= '0';
+ uartData <= x"58"; -- 'X'
+ readingTimer <= '0';
+ elsif rising_edge(cpu_clk) then
+ timer_we <= '0';
+ io_busy <= '0';
+ if uartTXCleared = '1' then
+ uartTXPending <= '0';
+ end if;
+
+ if io_writeEnable = '1' then
+ if io_addr = x"2028003" then
+ -- Write to UART
+ uartData <= mem_write(7 downto 0);
+ uartTXPending <= '1';
+ io_busy <= '1';
+ elsif io_addr(12) = '1' then
+ timer_we <= '1';
+ io_busy <= '1';
+ else
+ -- report "Illegal IO write" severity failure;
+ end if;
+ end if;
+ if (io_readEnable = '1') then
+ if io_addr = x"2028003" then
+ io_read <= (0 => '1', -- recieve empty
+ 1 => uartTXPending, -- tx full
+ others => '0');
+ io_busy <= '1';
+ elsif io_addr(12) = '1' then
+ readingTimer <= '1';
+ io_busy <= '1';
+ elsif io_addr(11) = '1' then
+ io_read <= ZPU_Frequency;
+ io_busy <= '1';
+ else
+ -- report "Illegal IO read" severity failure;
+ end if;
+
+ else
+ if (readingTimer = '1') then
+ readingTimer <= '0';
+ io_read <= timer_read;
+ io_busy <= '0';
+ else
+ io_read <= (others => '1');
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+ forwardUARTOutputToARM : process(cpu_clk, areset)
+ begin
+ if areset = '1' then
+ uartTXCleared <= '0';
+ elsif rising_edge(cpu_clkt) then
+ if cpu_we(0) = '1' and cpu_a(3 downto 1) = "000" then
+ uartTXCleared <= cpu_din(0);
+ else
+ uartTXCleared <= uartTXCleared;
+ end if;
+ end if;
+ end process;
+
+ cpu_dout(7 downto 0) <= uartData when (cpu_re = '1' and cpu_a(3 downto 1) = "001") else (others => 'Z');
+ cpu_dout <= (0 => uartTXPending, others => '0') when (cpu_re = '1' and cpu_a(3 downto 1) = "000") else (others => 'Z');
+
+ dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit);
+ dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit);
+ io_writeEnable <= mem_writeEnable and mem_addr(ioBit);
+ mem_busy <= io_busy or dram_mem_busy or dram_read or io_readEnable;
+
+ -- Memory reads either come from IO or DRAM. We need to pick the right one.
+ memorycontrol : process(cpu_clk, areset)
+ begin
+ if areset = '1' then
+ dram_read <= '0';
+ io_readEnable <= '0';
+
+ elsif rising_edge(cpu_clk) then
+ mem_read <= (others => '0');
+ if mem_addr(ioBit) = '0' and mem_readEnable = '1' then
+ dram_read <= '1';
+ end if;
+ if dram_read = '1' and dram_mem_busy = '0' then
+ dram_read <= '0';
+ mem_read <= dram_mem_read;
+ end if;
+
+ if mem_addr(ioBit) = '1' and mem_readEnable = '1' then
+ io_readEnable <= '1';
+ end if;
+ if io_readEnable = '1' and io_busy = '0' then
+ io_readEnable <= '0';
+ mem_read(7 downto 0) <= io_read;
+ end if;
+
+ end if;
+ end process;
+
+
+end architecture behave;
diff --git a/zpu/hdl/zpu4/test/dmips/build.sh b/zpu/hdl/zpu4/test/dmips/build.sh
new file mode 100755
index 0000000..44ead41
--- /dev/null
+++ b/zpu/hdl/zpu4/test/dmips/build.sh
@@ -0,0 +1,4 @@
+zpu-elf-gcc -DTIME ../../../../../../roadshow/dhrystone/dhry_*.c -O3 -Wl,--gc-sections -Wl,--relax -phi -o dmips.elf
+zpu-elf-objdump --disassemble-all >dmips.dis dmips.elf
+zpu-elf-objcopy -O binary dmips.elf dmips.bin
+java -classpath ../../../../sw/simulator/zpusim.jar com.zylin.zpu.simulator.tools.MakeRam dmips.bin >dmips.ram
diff --git a/zpu/hdl/zpu4/test/dmips/dmips.bin b/zpu/hdl/zpu4/test/dmips/dmips.bin
new file mode 100644
index 0000000..ee1a6fe
--- /dev/null
+++ b/zpu/hdl/zpu4/test/dmips/dmips.bin
Binary files differ
diff --git a/zpu/hdl/zpu4/test/dmips/dmips.elf b/zpu/hdl/zpu4/test/dmips/dmips.elf
new file mode 100644
index 0000000..3a04a5b
--- /dev/null
+++ b/zpu/hdl/zpu4/test/dmips/dmips.elf
Binary files differ
diff --git a/zpu/hdl/zpu4/test/dmips/dmips.ram b/zpu/hdl/zpu4/test/dmips/dmips.ram
new file mode 100644
index 0000000..0919ce1
--- /dev/null
+++ b/zpu/hdl/zpu4/test/dmips/dmips.ram
@@ -0,0 +1,3256 @@
+0 => x"0b0b0b0b",
+1 => x"82700b0b",
+2 => x"80d5f40c",
+3 => x"3a0b0b80",
+4 => x"c4fb0400",
+5 => x"00000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"80c5c22d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
+17 => x"72830609",
+18 => x"81058205",
+19 => x"832b2a83",
+20 => x"ffff0652",
+21 => x"04000000",
+22 => x"00000000",
+23 => x"00000000",
+24 => x"71fd0608",
+25 => x"83ffff73",
+26 => x"83060981",
+27 => x"05820583",
+28 => x"2b2b0906",
+29 => x"7383ffff",
+30 => x"0b0b0b0b",
+31 => x"83a70400",
+32 => x"72098105",
+33 => x"72057373",
+34 => x"09060906",
+35 => x"73097306",
+36 => x"070a8106",
+37 => x"53510400",
+38 => x"00000000",
+39 => x"00000000",
+40 => x"72722473",
+41 => x"732e0753",
+42 => x"51040000",
+43 => x"00000000",
+44 => x"00000000",
+45 => x"00000000",
+46 => x"00000000",
+47 => x"00000000",
+48 => x"71737109",
+49 => x"71068106",
+50 => x"30720a10",
+51 => x"0a720a10",
+52 => x"0a31050a",
+53 => x"81065151",
+54 => x"53510400",
+55 => x"00000000",
+56 => x"72722673",
+57 => x"732e0753",
+58 => x"51040000",
+59 => x"00000000",
+60 => x"00000000",
+61 => x"00000000",
+62 => x"00000000",
+63 => x"00000000",
+64 => x"00000000",
+65 => x"00000000",
+66 => x"00000000",
+67 => x"00000000",
+68 => x"00000000",
+69 => x"00000000",
+70 => x"00000000",
+71 => x"00000000",
+72 => x"0b0b0b88",
+73 => x"c3040000",
+74 => x"00000000",
+75 => x"00000000",
+76 => x"00000000",
+77 => x"00000000",
+78 => x"00000000",
+79 => x"00000000",
+80 => x"720a722b",
+81 => x"0a535104",
+82 => x"00000000",
+83 => x"00000000",
+84 => x"00000000",
+85 => x"00000000",
+86 => x"00000000",
+87 => x"00000000",
+88 => x"72729f06",
+89 => x"0981050b",
+90 => x"0b0b88a6",
+91 => x"05040000",
+92 => x"00000000",
+93 => x"00000000",
+94 => x"00000000",
+95 => x"00000000",
+96 => x"72722aff",
+97 => x"739f062a",
+98 => x"0974090a",
+99 => x"8106ff05",
+100 => x"06075351",
+101 => x"04000000",
+102 => x"00000000",
+103 => x"00000000",
+104 => x"71715351",
+105 => x"020d0406",
+106 => x"73830609",
+107 => x"81058205",
+108 => x"832b0b2b",
+109 => x"0772fc06",
+110 => x"0c515104",
+111 => x"00000000",
+112 => x"72098105",
+113 => x"72050970",
+114 => x"81050906",
+115 => x"0a810653",
+116 => x"51040000",
+117 => x"00000000",
+118 => x"00000000",
+119 => x"00000000",
+120 => x"72098105",
+121 => x"72050970",
+122 => x"81050906",
+123 => x"0a098106",
+124 => x"53510400",
+125 => x"00000000",
+126 => x"00000000",
+127 => x"00000000",
+128 => x"71098105",
+129 => x"52040000",
+130 => x"00000000",
+131 => x"00000000",
+132 => x"00000000",
+133 => x"00000000",
+134 => x"00000000",
+135 => x"00000000",
+136 => x"72720981",
+137 => x"05055351",
+138 => x"04000000",
+139 => x"00000000",
+140 => x"00000000",
+141 => x"00000000",
+142 => x"00000000",
+143 => x"00000000",
+144 => x"72097206",
+145 => x"73730906",
+146 => x"07535104",
+147 => x"00000000",
+148 => x"00000000",
+149 => x"00000000",
+150 => x"00000000",
+151 => x"00000000",
+152 => x"71fc0608",
+153 => x"72830609",
+154 => x"81058305",
+155 => x"1010102a",
+156 => x"81ff0652",
+157 => x"04000000",
+158 => x"00000000",
+159 => x"00000000",
+160 => x"71fc0608",
+161 => x"0b0b80d5",
+162 => x"e0738306",
+163 => x"10100508",
+164 => x"060b0b0b",
+165 => x"88a90400",
+166 => x"00000000",
+167 => x"00000000",
+168 => x"80088408",
+169 => x"88087575",
+170 => x"0b0b0bad",
+171 => x"aa2d5050",
+172 => x"80085688",
+173 => x"0c840c80",
+174 => x"0c510400",
+175 => x"00000000",
+176 => x"80088408",
+177 => x"88087575",
+178 => x"0b0b0bad",
+179 => x"ee2d5050",
+180 => x"80085688",
+181 => x"0c840c80",
+182 => x"0c510400",
+183 => x"00000000",
+184 => x"72097081",
+185 => x"0509060a",
+186 => x"8106ff05",
+187 => x"70547106",
+188 => x"73097274",
+189 => x"05ff0506",
+190 => x"07515151",
+191 => x"04000000",
+192 => x"72097081",
+193 => x"0509060a",
+194 => x"098106ff",
+195 => x"05705471",
+196 => x"06730972",
+197 => x"7405ff05",
+198 => x"06075151",
+199 => x"51040000",
+200 => x"05ff0504",
+201 => x"00000000",
+202 => x"00000000",
+203 => x"00000000",
+204 => x"00000000",
+205 => x"00000000",
+206 => x"00000000",
+207 => x"00000000",
+208 => x"810b0b0b",
+209 => x"80d5f00c",
+210 => x"51040000",
+211 => x"00000000",
+212 => x"00000000",
+213 => x"00000000",
+214 => x"00000000",
+215 => x"00000000",
+216 => x"71810552",
+217 => x"04000000",
+218 => x"00000000",
+219 => x"00000000",
+220 => x"00000000",
+221 => x"00000000",
+222 => x"00000000",
+223 => x"00000000",
+224 => x"00000000",
+225 => x"00000000",
+226 => x"00000000",
+227 => x"00000000",
+228 => x"00000000",
+229 => x"00000000",
+230 => x"00000000",
+231 => x"00000000",
+232 => x"02840572",
+233 => x"10100552",
+234 => x"04000000",
+235 => x"00000000",
+236 => x"00000000",
+237 => x"00000000",
+238 => x"00000000",
+239 => x"00000000",
+240 => x"00000000",
+241 => x"00000000",
+242 => x"00000000",
+243 => x"00000000",
+244 => x"00000000",
+245 => x"00000000",
+246 => x"00000000",
+247 => x"00000000",
+248 => x"717105ff",
+249 => x"05715351",
+250 => x"020d0400",
+251 => x"00000000",
+252 => x"00000000",
+253 => x"00000000",
+254 => x"00000000",
+255 => x"00000000",
+256 => x"82fd3fbf",
+257 => x"a03f0410",
+258 => x"10101010",
+259 => x"10101010",
+260 => x"10101010",
+261 => x"10101010",
+262 => x"10101010",
+263 => x"10101010",
+264 => x"10101010",
+265 => x"10105351",
+266 => x"047381ff",
+267 => x"06738306",
+268 => x"09810583",
+269 => x"05101010",
+270 => x"2b0772fc",
+271 => x"060c5151",
+272 => x"043c0472",
+273 => x"72807281",
+274 => x"06ff0509",
+275 => x"72060571",
+276 => x"1052720a",
+277 => x"100a5372",
+278 => x"ed385151",
+279 => x"535104ff",
+280 => x"3d0d0b0b",
+281 => x"80e5e408",
+282 => x"52710870",
+283 => x"882a8132",
+284 => x"70810651",
+285 => x"515170f1",
+286 => x"3873720c",
+287 => x"833d0d04",
+288 => x"80d5f008",
+289 => x"802ea438",
+290 => x"80d5f408",
+291 => x"822ebd38",
+292 => x"8380800b",
+293 => x"0b0b80e5",
+294 => x"e40c82a0",
+295 => x"800b80e5",
+296 => x"e80c8290",
+297 => x"800b80e5",
+298 => x"ec0c04f8",
+299 => x"808080a4",
+300 => x"0b0b0b80",
+301 => x"e5e40cf8",
+302 => x"80808280",
+303 => x"0b80e5e8",
+304 => x"0cf88080",
+305 => x"84800b80",
+306 => x"e5ec0c04",
+307 => x"80c0a880",
+308 => x"8c0b0b0b",
+309 => x"80e5e40c",
+310 => x"80c0a880",
+311 => x"940b80e5",
+312 => x"e80c0b0b",
+313 => x"80c7d00b",
+314 => x"80e5ec0c",
+315 => x"04f23d0d",
+316 => x"6080e5e8",
+317 => x"08565d82",
+318 => x"750c8059",
+319 => x"805a800b",
+320 => x"8f3d5d5b",
+321 => x"7a101015",
+322 => x"70087108",
+323 => x"719f2c7e",
+324 => x"852b5855",
+325 => x"557d5359",
+326 => x"5799993f",
+327 => x"7d7f7a72",
+328 => x"077c7207",
+329 => x"71716081",
+330 => x"05415f5d",
+331 => x"5b595755",
+332 => x"817b278f",
+333 => x"38767d0c",
+334 => x"77841e0c",
+335 => x"7c800c90",
+336 => x"3d0d0480",
+337 => x"e5e80855",
+338 => x"ffba3970",
+339 => x"7080e5f0",
+340 => x"335170a7",
+341 => x"3880d5fc",
+342 => x"08700852",
+343 => x"5270802e",
+344 => x"94388412",
+345 => x"80d5fc0c",
+346 => x"702d80d5",
+347 => x"fc087008",
+348 => x"525270ee",
+349 => x"38810b80",
+350 => x"e5f03450",
+351 => x"50040470",
+352 => x"0b0b80e5",
+353 => x"e008802e",
+354 => x"8e380b0b",
+355 => x"0b0b800b",
+356 => x"802e0981",
+357 => x"06833850",
+358 => x"040b0b80",
+359 => x"e5e0510b",
+360 => x"0b0bf4dc",
+361 => x"3f500404",
+362 => x"ff3d0d02",
+363 => x"8f053352",
+364 => x"718a2e8a",
+365 => x"387151fd",
+366 => x"a63f833d",
+367 => x"0d048d51",
+368 => x"fd9d3f71",
+369 => x"51fd983f",
+370 => x"833d0d04",
+371 => x"ce3d0db5",
+372 => x"3d707084",
+373 => x"0552088b",
+374 => x"a85c56a5",
+375 => x"3d5e5c80",
+376 => x"75708105",
+377 => x"5733765b",
+378 => x"55587378",
+379 => x"2e80c138",
+380 => x"8e3d5b73",
+381 => x"a52e0981",
+382 => x"0680c538",
+383 => x"78708105",
+384 => x"5a335473",
+385 => x"80e42e81",
+386 => x"b6387380",
+387 => x"e42480c6",
+388 => x"387380e3",
+389 => x"2ea13880",
+390 => x"52a55179",
+391 => x"2d805273",
+392 => x"51792d82",
+393 => x"18587870",
+394 => x"81055a33",
+395 => x"5473c438",
+396 => x"77800cb4",
+397 => x"3d0d047b",
+398 => x"841d8312",
+399 => x"33565d57",
+400 => x"80527351",
+401 => x"792d8118",
+402 => x"79708105",
+403 => x"5b335558",
+404 => x"73ffa038",
+405 => x"db397380",
+406 => x"f32e0981",
+407 => x"06ffb838",
+408 => x"7b841d71",
+409 => x"08595d56",
+410 => x"80773355",
+411 => x"5673762e",
+412 => x"8d388116",
+413 => x"70187033",
+414 => x"57555674",
+415 => x"f538ff16",
+416 => x"55807625",
+417 => x"ffa03876",
+418 => x"70810558",
+419 => x"33548052",
+420 => x"7351792d",
+421 => x"811875ff",
+422 => x"17575758",
+423 => x"807625ff",
+424 => x"85387670",
+425 => x"81055833",
+426 => x"54805273",
+427 => x"51792d81",
+428 => x"1875ff17",
+429 => x"57575875",
+430 => x"8024cc38",
+431 => x"fee8397b",
+432 => x"841d7108",
+433 => x"70719f2c",
+434 => x"5953595d",
+435 => x"56807524",
+436 => x"81913875",
+437 => x"7d7c5856",
+438 => x"54805773",
+439 => x"772e0981",
+440 => x"06b638b0",
+441 => x"7b3402b5",
+442 => x"05567a76",
+443 => x"2e9738ff",
+444 => x"16567533",
+445 => x"75708105",
+446 => x"57348117",
+447 => x"577a762e",
+448 => x"098106eb",
+449 => x"38807534",
+450 => x"767dff12",
+451 => x"57585675",
+452 => x"8024fef3",
+453 => x"38fe8f39",
+454 => x"8a527351",
+455 => x"9fd03f80",
+456 => x"0880c7d4",
+457 => x"05337670",
+458 => x"81055834",
+459 => x"8a527351",
+460 => x"9ef83f80",
+461 => x"08548008",
+462 => x"802effae",
+463 => x"388a5273",
+464 => x"519fab3f",
+465 => x"800880c7",
+466 => x"d4053376",
+467 => x"70810558",
+468 => x"348a5273",
+469 => x"519ed33f",
+470 => x"80085480",
+471 => x"08ffb938",
+472 => x"ff883974",
+473 => x"527653b4",
+474 => x"3dffb805",
+475 => x"51949a3f",
+476 => x"a33d0856",
+477 => x"fedd3980",
+478 => x"3d0d80c1",
+479 => x"0b81b4bc",
+480 => x"34800b81",
+481 => x"b6980c70",
+482 => x"800c823d",
+483 => x"0d04ff3d",
+484 => x"0d800b81",
+485 => x"b4bc3352",
+486 => x"527080c1",
+487 => x"2e993871",
+488 => x"81b69808",
+489 => x"0781b698",
+490 => x"0c80c20b",
+491 => x"81b4c034",
+492 => x"70800c83",
+493 => x"3d0d0481",
+494 => x"0b81b698",
+495 => x"080781b6",
+496 => x"980c80c2",
+497 => x"0b81b4c0",
+498 => x"3470800c",
+499 => x"833d0d04",
+500 => x"fd3d0d75",
+501 => x"70088a05",
+502 => x"535381b4",
+503 => x"bc335170",
+504 => x"80c12e8b",
+505 => x"3873f338",
+506 => x"70800c85",
+507 => x"3d0d04ff",
+508 => x"127081b4",
+509 => x"b8083174",
+510 => x"0c800c85",
+511 => x"3d0d04fc",
+512 => x"3d0d81b4",
+513 => x"c4085574",
+514 => x"802e8c38",
+515 => x"76750871",
+516 => x"0c81b4c4",
+517 => x"0856548c",
+518 => x"155381b4",
+519 => x"b808528a",
+520 => x"518fd43f",
+521 => x"73800c86",
+522 => x"3d0d04fb",
+523 => x"3d0d7770",
+524 => x"085656b0",
+525 => x"5381b4c4",
+526 => x"08527451",
+527 => x"ab943f85",
+528 => x"0b8c170c",
+529 => x"850b8c16",
+530 => x"0c750875",
+531 => x"0c81b4c4",
+532 => x"08547380",
+533 => x"2e8a3873",
+534 => x"08750c81",
+535 => x"b4c40854",
+536 => x"8c145381",
+537 => x"b4b80852",
+538 => x"8a518f8b",
+539 => x"3f841508",
+540 => x"ad38860b",
+541 => x"8c160c88",
+542 => x"15528816",
+543 => x"08518e97",
+544 => x"3f81b4c4",
+545 => x"08700876",
+546 => x"0c548c15",
+547 => x"7054548a",
+548 => x"52730851",
+549 => x"8ee13f73",
+550 => x"800c873d",
+551 => x"0d047508",
+552 => x"54b05373",
+553 => x"527551aa",
+554 => x"a93f7380",
+555 => x"0c873d0d",
+556 => x"04d93d0d",
+557 => x"b0519dcf",
+558 => x"3f800881",
+559 => x"b4b40cb0",
+560 => x"519dc43f",
+561 => x"800881b4",
+562 => x"c40c81b4",
+563 => x"b4088008",
+564 => x"0c800b80",
+565 => x"0884050c",
+566 => x"820b8008",
+567 => x"88050ca8",
+568 => x"0b80088c",
+569 => x"050c9f53",
+570 => x"80c7e052",
+571 => x"80089005",
+572 => x"51a9df3f",
+573 => x"a13d5e9f",
+574 => x"5380c880",
+575 => x"527d51a9",
+576 => x"d13f8a0b",
+577 => x"80f2f80c",
+578 => x"80d2a451",
+579 => x"f9be3f80",
+580 => x"c8a051f9",
+581 => x"b73f80d2",
+582 => x"a451f9b0",
+583 => x"3f80d684",
+584 => x"08802e89",
+585 => x"d33880c8",
+586 => x"d051f9a0",
+587 => x"3f80d2a4",
+588 => x"51f9993f",
+589 => x"80d68008",
+590 => x"5280c8fc",
+591 => x"51f98d3f",
+592 => x"80e69451",
+593 => x"b2ff3f81",
+594 => x"0b9a3d5e",
+595 => x"5b800b80",
+596 => x"d6800825",
+597 => x"82d43890",
+598 => x"3d5f80c1",
+599 => x"0b81b4bc",
+600 => x"34810b81",
+601 => x"b6980c80",
+602 => x"c20b81b4",
+603 => x"c0348240",
+604 => x"835a9f53",
+605 => x"80c9ac52",
+606 => x"7c51a8d6",
+607 => x"3f814180",
+608 => x"7d537e52",
+609 => x"568e943f",
+610 => x"8008762e",
+611 => x"09810683",
+612 => x"38815675",
+613 => x"81b6980c",
+614 => x"7f705856",
+615 => x"758325a2",
+616 => x"38751010",
+617 => x"16fd0542",
+618 => x"a93dffa4",
+619 => x"05538352",
+620 => x"76518cc3",
+621 => x"3f7f8105",
+622 => x"70417058",
+623 => x"56837624",
+624 => x"e0386154",
+625 => x"755380e6",
+626 => x"9c5281b4",
+627 => x"d0518cb7",
+628 => x"3f81b4c4",
+629 => x"08700858",
+630 => x"58b05377",
+631 => x"527651a7",
+632 => x"f13f850b",
+633 => x"8c190c85",
+634 => x"0b8c180c",
+635 => x"7708770c",
+636 => x"81b4c408",
+637 => x"5675802e",
+638 => x"8a387508",
+639 => x"770c81b4",
+640 => x"c408568c",
+641 => x"165381b4",
+642 => x"b808528a",
+643 => x"518be83f",
+644 => x"84170887",
+645 => x"ea38860b",
+646 => x"8c180c88",
+647 => x"17528818",
+648 => x"08518af3",
+649 => x"3f81b4c4",
+650 => x"08700878",
+651 => x"0c568c17",
+652 => x"7054598a",
+653 => x"52780851",
+654 => x"8bbd3f80",
+655 => x"c10b81b4",
+656 => x"c0335757",
+657 => x"767626a2",
+658 => x"3880c352",
+659 => x"76518ca1",
+660 => x"3f800861",
+661 => x"2e89e438",
+662 => x"81177081",
+663 => x"ff0681b4",
+664 => x"c0335858",
+665 => x"58757727",
+666 => x"e0387960",
+667 => x"29627054",
+668 => x"71535b59",
+669 => x"98b43f80",
+670 => x"0840787a",
+671 => x"31708729",
+672 => x"80083180",
+673 => x"088a0581",
+674 => x"b4bc3381",
+675 => x"b4b8085e",
+676 => x"5b525a56",
+677 => x"7780c12e",
+678 => x"89ce387b",
+679 => x"f738811b",
+680 => x"5b80d680",
+681 => x"087b25fd",
+682 => x"b13881b4",
+683 => x"ac51b095",
+684 => x"3f80c9cc",
+685 => x"51f6953f",
+686 => x"80d2a451",
+687 => x"f68e3f80",
+688 => x"c9dc51f6",
+689 => x"873f80d2",
+690 => x"a451f680",
+691 => x"3f81b4b8",
+692 => x"085280ca",
+693 => x"9451f5f4",
+694 => x"3f855280",
+695 => x"cab051f5",
+696 => x"eb3f81b6",
+697 => x"98085280",
+698 => x"cacc51f5",
+699 => x"df3f8152",
+700 => x"80cab051",
+701 => x"f5d63f81",
+702 => x"b4bc3352",
+703 => x"80cae851",
+704 => x"f5ca3f80",
+705 => x"c15280cb",
+706 => x"8451f5c0",
+707 => x"3f81b4c0",
+708 => x"335280cb",
+709 => x"a051f5b4",
+710 => x"3f80c252",
+711 => x"80cb8451",
+712 => x"f5aa3f81",
+713 => x"b4f00852",
+714 => x"80cbbc51",
+715 => x"f59e3f87",
+716 => x"5280cab0",
+717 => x"51f5953f",
+718 => x"80f2f808",
+719 => x"5280cbd8",
+720 => x"51f5893f",
+721 => x"80cbf451",
+722 => x"f5823f80",
+723 => x"cca051f4",
+724 => x"fb3f81b4",
+725 => x"c4087008",
+726 => x"535a80cc",
+727 => x"ac51f4ec",
+728 => x"3f80ccc8",
+729 => x"51f4e53f",
+730 => x"81b4c408",
+731 => x"84110853",
+732 => x"5680ccfc",
+733 => x"51f4d53f",
+734 => x"805280ca",
+735 => x"b051f4cc",
+736 => x"3f81b4c4",
+737 => x"08881108",
+738 => x"535880cd",
+739 => x"9851f4bc",
+740 => x"3f825280",
+741 => x"cab051f4",
+742 => x"b33f81b4",
+743 => x"c4088c11",
+744 => x"08535780",
+745 => x"cdb451f4",
+746 => x"a33f9152",
+747 => x"80cab051",
+748 => x"f49a3f81",
+749 => x"b4c40890",
+750 => x"055280cd",
+751 => x"d051f48c",
+752 => x"3f80cdec",
+753 => x"51f4853f",
+754 => x"80cea451",
+755 => x"f3fe3f81",
+756 => x"b4b40870",
+757 => x"08535f80",
+758 => x"ccac51f3",
+759 => x"ef3f80ce",
+760 => x"b851f3e8",
+761 => x"3f81b4b4",
+762 => x"08841108",
+763 => x"535b80cc",
+764 => x"fc51f3d8",
+765 => x"3f805280",
+766 => x"cab051f3",
+767 => x"cf3f81b4",
+768 => x"b4088811",
+769 => x"08535c80",
+770 => x"cd9851f3",
+771 => x"bf3f8152",
+772 => x"80cab051",
+773 => x"f3b63f81",
+774 => x"b4b4088c",
+775 => x"1108535a",
+776 => x"80cdb451",
+777 => x"f3a63f92",
+778 => x"5280cab0",
+779 => x"51f39d3f",
+780 => x"81b4b408",
+781 => x"90055280",
+782 => x"cdd051f3",
+783 => x"8f3f80cd",
+784 => x"ec51f388",
+785 => x"3f7f5280",
+786 => x"cef851f2",
+787 => x"ff3f8552",
+788 => x"80cab051",
+789 => x"f2f63f78",
+790 => x"5280cf94",
+791 => x"51f2ed3f",
+792 => x"8d5280ca",
+793 => x"b051f2e4",
+794 => x"3f615280",
+795 => x"cfb051f2",
+796 => x"db3f8752",
+797 => x"80cab051",
+798 => x"f2d23f60",
+799 => x"5280cfcc",
+800 => x"51f2c93f",
+801 => x"815280ca",
+802 => x"b051f2c0",
+803 => x"3f7d5280",
+804 => x"cfe851f2",
+805 => x"b73f80d0",
+806 => x"8451f2b0",
+807 => x"3f7c5280",
+808 => x"d0bc51f2",
+809 => x"a73f80d0",
+810 => x"d851f2a0",
+811 => x"3f80d2a4",
+812 => x"51f2993f",
+813 => x"81b4ac08",
+814 => x"81b4b008",
+815 => x"80e69408",
+816 => x"80e69808",
+817 => x"72713170",
+818 => x"74267574",
+819 => x"31707231",
+820 => x"80e68c0c",
+821 => x"444480e6",
+822 => x"900c80e6",
+823 => x"90085680",
+824 => x"d190555c",
+825 => x"595758f1",
+826 => x"e33f80e6",
+827 => x"8c085680",
+828 => x"762582a3",
+829 => x"3880d680",
+830 => x"0870719f",
+831 => x"2c9a3d53",
+832 => x"565680e6",
+833 => x"8c0880e6",
+834 => x"90084153",
+835 => x"7f547052",
+836 => x"5a89eb3f",
+837 => x"66685f80",
+838 => x"e5fc0c7d",
+839 => x"80e6800c",
+840 => x"80d68008",
+841 => x"709f2c58",
+842 => x"568058bd",
+843 => x"84c07855",
+844 => x"55765275",
+845 => x"53795187",
+846 => x"d13f953d",
+847 => x"80e68c08",
+848 => x"80e69008",
+849 => x"41557f56",
+850 => x"67694053",
+851 => x"7e547052",
+852 => x"5c89ab3f",
+853 => x"64665e80",
+854 => x"e6840c7c",
+855 => x"80e6880c",
+856 => x"80d68008",
+857 => x"709f2c40",
+858 => x"58805783",
+859 => x"dceb9480",
+860 => x"7755557e",
+861 => x"5277537b",
+862 => x"51878f3f",
+863 => x"64665d5b",
+864 => x"805e8ddd",
+865 => x"7e555580",
+866 => x"e68c0880",
+867 => x"e6900859",
+868 => x"52775379",
+869 => x"5186f33f",
+870 => x"66684054",
+871 => x"7e557a52",
+872 => x"7b53a93d",
+873 => x"ffa80551",
+874 => x"88d43f62",
+875 => x"645e81b4",
+876 => x"c80c7c81",
+877 => x"b4cc0c80",
+878 => x"d1a051f0",
+879 => x"8f3f80e6",
+880 => x"80085280",
+881 => x"d1d051f0",
+882 => x"833f80d1",
+883 => x"d851effc",
+884 => x"3f80e688",
+885 => x"085280d1",
+886 => x"d051eff0",
+887 => x"3f81b4cc",
+888 => x"085280d2",
+889 => x"8851efe4",
+890 => x"3f80d2a4",
+891 => x"51efdd3f",
+892 => x"800b800c",
+893 => x"a93d0d04",
+894 => x"80d2a851",
+895 => x"f6ac3977",
+896 => x"0857b053",
+897 => x"76527751",
+898 => x"9fc83f80",
+899 => x"c10b81b4",
+900 => x"c0335757",
+901 => x"f8ae3975",
+902 => x"8a3880e6",
+903 => x"90088126",
+904 => x"fdd33880",
+905 => x"d2d851ef",
+906 => x"a33f80d3",
+907 => x"9051ef9c",
+908 => x"3f80d2a4",
+909 => x"51ef953f",
+910 => x"80d68008",
+911 => x"70719f2c",
+912 => x"9a3d5356",
+913 => x"5680e68c",
+914 => x"0880e690",
+915 => x"0841537f",
+916 => x"5470525a",
+917 => x"87a83f66",
+918 => x"685f80e5",
+919 => x"fc0c7d80",
+920 => x"e6800c80",
+921 => x"d6800870",
+922 => x"9f2c5856",
+923 => x"8058bd84",
+924 => x"c0785555",
+925 => x"76527553",
+926 => x"7951858e",
+927 => x"3f953d80",
+928 => x"e68c0880",
+929 => x"e6900841",
+930 => x"557f5667",
+931 => x"6940537e",
+932 => x"5470525c",
+933 => x"86e83f64",
+934 => x"665e80e6",
+935 => x"840c7c80",
+936 => x"e6880c80",
+937 => x"d6800870",
+938 => x"9f2c4058",
+939 => x"805783dc",
+940 => x"eb948077",
+941 => x"55557e52",
+942 => x"77537b51",
+943 => x"84cc3f64",
+944 => x"665d5b80",
+945 => x"5e8ddd7e",
+946 => x"555580e6",
+947 => x"8c0880e6",
+948 => x"90085952",
+949 => x"77537951",
+950 => x"84b03f66",
+951 => x"6840547e",
+952 => x"557a527b",
+953 => x"53a93dff",
+954 => x"a8055186",
+955 => x"913f6264",
+956 => x"5e81b4c8",
+957 => x"0c7c81b4",
+958 => x"cc0c80d1",
+959 => x"a051edcc",
+960 => x"3f80e680",
+961 => x"085280d1",
+962 => x"d051edc0",
+963 => x"3f80d1d8",
+964 => x"51edb93f",
+965 => x"80e68808",
+966 => x"5280d1d0",
+967 => x"51edad3f",
+968 => x"81b4cc08",
+969 => x"5280d288",
+970 => x"51eda13f",
+971 => x"80d2a451",
+972 => x"ed9a3f80",
+973 => x"0b800ca9",
+974 => x"3d0d04a9",
+975 => x"3dffa005",
+976 => x"52805180",
+977 => x"d23f9f53",
+978 => x"80d3b052",
+979 => x"7c519d82",
+980 => x"3f7a7b81",
+981 => x"b4b80c81",
+982 => x"187081ff",
+983 => x"0681b4c0",
+984 => x"33595959",
+985 => x"5af5fe39",
+986 => x"ff16707b",
+987 => x"31600c5c",
+988 => x"800b811c",
+989 => x"5c5c80d6",
+990 => x"80087b25",
+991 => x"f3dc38f6",
+992 => x"a939ff3d",
+993 => x"0d738232",
+994 => x"70307072",
+995 => x"07802580",
+996 => x"0c525283",
+997 => x"3d0d04fe",
+998 => x"3d0d7476",
+999 => x"71535452",
+1000 => x"71822e83",
+1001 => x"38835171",
+1002 => x"812e9a38",
+1003 => x"8172269f",
+1004 => x"3871822e",
+1005 => x"b8387184",
+1006 => x"2ea93870",
+1007 => x"730c7080",
+1008 => x"0c843d0d",
+1009 => x"0480e40b",
+1010 => x"81b4b808",
+1011 => x"258b3880",
+1012 => x"730c7080",
+1013 => x"0c843d0d",
+1014 => x"0483730c",
+1015 => x"70800c84",
+1016 => x"3d0d0482",
+1017 => x"730c7080",
+1018 => x"0c843d0d",
+1019 => x"0481730c",
+1020 => x"70800c84",
+1021 => x"3d0d0480",
+1022 => x"3d0d7474",
+1023 => x"14820571",
+1024 => x"0c800c82",
+1025 => x"3d0d04f7",
+1026 => x"3d0d7b7d",
+1027 => x"7f618512",
+1028 => x"70822b75",
+1029 => x"11707471",
+1030 => x"70840553",
+1031 => x"0c5a5a5d",
+1032 => x"5b760c79",
+1033 => x"80f8180c",
+1034 => x"79861252",
+1035 => x"57585a5a",
+1036 => x"76762499",
+1037 => x"3876b329",
+1038 => x"822b7911",
+1039 => x"51537673",
+1040 => x"70840555",
+1041 => x"0c811454",
+1042 => x"757425f2",
+1043 => x"387681cc",
+1044 => x"2919fc11",
+1045 => x"088105fc",
+1046 => x"120c7a19",
+1047 => x"70089fa0",
+1048 => x"130c5856",
+1049 => x"850b81b4",
+1050 => x"b80c7580",
+1051 => x"0c8b3d0d",
+1052 => x"04fe3d0d",
+1053 => x"02930533",
+1054 => x"51800284",
+1055 => x"05970533",
+1056 => x"54527073",
+1057 => x"2e883871",
+1058 => x"800c843d",
+1059 => x"0d047081",
+1060 => x"b4bc3481",
+1061 => x"0b800c84",
+1062 => x"3d0d04f8",
+1063 => x"3d0d7a7c",
+1064 => x"5956820b",
+1065 => x"83195555",
+1066 => x"74167033",
+1067 => x"75335b51",
+1068 => x"5372792e",
+1069 => x"80c63880",
+1070 => x"c10b8116",
+1071 => x"81165656",
+1072 => x"57827525",
+1073 => x"e338ffa9",
+1074 => x"177081ff",
+1075 => x"06555973",
+1076 => x"82268338",
+1077 => x"87558153",
+1078 => x"7680d22e",
+1079 => x"98387752",
+1080 => x"75519bc3",
+1081 => x"3f805372",
+1082 => x"80082589",
+1083 => x"38871581",
+1084 => x"b4b80c81",
+1085 => x"5372800c",
+1086 => x"8a3d0d04",
+1087 => x"7281b4bc",
+1088 => x"34827525",
+1089 => x"ffa238ff",
+1090 => x"bd39ef3d",
+1091 => x"0d636567",
+1092 => x"5b427943",
+1093 => x"67695940",
+1094 => x"77415a80",
+1095 => x"5d805e61",
+1096 => x"7083ffff",
+1097 => x"0671902a",
+1098 => x"627083ff",
+1099 => x"ff067190",
+1100 => x"2a747229",
+1101 => x"74732975",
+1102 => x"73297774",
+1103 => x"2973902a",
+1104 => x"05721151",
+1105 => x"5856535f",
+1106 => x"5a575a58",
+1107 => x"55587373",
+1108 => x"27863884",
+1109 => x"80801656",
+1110 => x"73902a16",
+1111 => x"5b7883ff",
+1112 => x"ff067484",
+1113 => x"80802905",
+1114 => x"5c7a7c5a",
+1115 => x"5d785e77",
+1116 => x"7f296178",
+1117 => x"29057d05",
+1118 => x"5d7c7e56",
+1119 => x"7a0c7484",
+1120 => x"1b0c7980",
+1121 => x"0c933d0d",
+1122 => x"04f93d0d",
+1123 => x"797b7d54",
+1124 => x"58725977",
+1125 => x"30797030",
+1126 => x"7072079f",
+1127 => x"2a737131",
+1128 => x"5a525977",
+1129 => x"7956730c",
+1130 => x"53738413",
+1131 => x"0c54800c",
+1132 => x"893d0d04",
+1133 => x"f93d0d79",
+1134 => x"7b7d7f56",
+1135 => x"54525472",
+1136 => x"802ea038",
+1137 => x"70577158",
+1138 => x"a0733152",
+1139 => x"807225a1",
+1140 => x"38777074",
+1141 => x"2b577073",
+1142 => x"2a78752b",
+1143 => x"07565174",
+1144 => x"76535170",
+1145 => x"740c7184",
+1146 => x"150c7380",
+1147 => x"0c893d0d",
+1148 => x"04805677",
+1149 => x"72302b55",
+1150 => x"74765351",
+1151 => x"e639e43d",
+1152 => x"0d6ea13d",
+1153 => x"08a33d08",
+1154 => x"59575f80",
+1155 => x"764d774e",
+1156 => x"a33d08a5",
+1157 => x"3d08574b",
+1158 => x"754c5e7d",
+1159 => x"6c2486fb",
+1160 => x"38806a24",
+1161 => x"878f3869",
+1162 => x"6b58566b",
+1163 => x"6d5d467b",
+1164 => x"47754476",
+1165 => x"45646468",
+1166 => x"685c5c56",
+1167 => x"567481e7",
+1168 => x"38787627",
+1169 => x"82c73875",
+1170 => x"81ff2683",
+1171 => x"2b5583ff",
+1172 => x"ff76278c",
+1173 => x"389055fe",
+1174 => x"800a7627",
+1175 => x"83389855",
+1176 => x"75752a80",
+1177 => x"d3d00570",
+1178 => x"33a07731",
+1179 => x"71315755",
+1180 => x"5774802e",
+1181 => x"95387575",
+1182 => x"2ba07631",
+1183 => x"7a772b7c",
+1184 => x"722a077c",
+1185 => x"782b5d5b",
+1186 => x"59567590",
+1187 => x"2a7683ff",
+1188 => x"ff067154",
+1189 => x"7a535957",
+1190 => x"88803f80",
+1191 => x"085b87ea",
+1192 => x"3f800880",
+1193 => x"0879297c",
+1194 => x"902b7c90",
+1195 => x"2a075656",
+1196 => x"59737527",
+1197 => x"94388008",
+1198 => x"ff057615",
+1199 => x"55597574",
+1200 => x"26873874",
+1201 => x"742687b9",
+1202 => x"38765273",
+1203 => x"75315187",
+1204 => x"c93f8008",
+1205 => x"5587b33f",
+1206 => x"80088008",
+1207 => x"79297b83",
+1208 => x"ffff0677",
+1209 => x"902b0756",
+1210 => x"59577378",
+1211 => x"27963880",
+1212 => x"08ff0576",
+1213 => x"15555775",
+1214 => x"74268938",
+1215 => x"77742677",
+1216 => x"71315856",
+1217 => x"78902b77",
+1218 => x"0758805b",
+1219 => x"7a407741",
+1220 => x"7f615654",
+1221 => x"7d80d938",
+1222 => x"737f0c74",
+1223 => x"7f84050c",
+1224 => x"7e800c9e",
+1225 => x"3d0d0480",
+1226 => x"705c5874",
+1227 => x"7926dd38",
+1228 => x"7481ff26",
+1229 => x"832b5774",
+1230 => x"83ffff26",
+1231 => x"82a53874",
+1232 => x"772a80d3",
+1233 => x"d0057033",
+1234 => x"a0793171",
+1235 => x"31595c5d",
+1236 => x"7682b338",
+1237 => x"76547479",
+1238 => x"27833881",
+1239 => x"54797627",
+1240 => x"74075981",
+1241 => x"5878ffa2",
+1242 => x"38765880",
+1243 => x"5bff9d39",
+1244 => x"73527453",
+1245 => x"9e3de805",
+1246 => x"51fc8e3f",
+1247 => x"6769567f",
+1248 => x"0c747f84",
+1249 => x"050c7e80",
+1250 => x"0c9e3d0d",
+1251 => x"0475802e",
+1252 => x"81c43875",
+1253 => x"81ff2683",
+1254 => x"2b5583ff",
+1255 => x"ff76278c",
+1256 => x"389055fe",
+1257 => x"800a7627",
+1258 => x"83389855",
+1259 => x"75752a80",
+1260 => x"d3d00570",
+1261 => x"33a07731",
+1262 => x"7131575e",
+1263 => x"54748491",
+1264 => x"38787631",
+1265 => x"54817690",
+1266 => x"2a7783ff",
+1267 => x"ff065f5d",
+1268 => x"5b7b5273",
+1269 => x"5185c33f",
+1270 => x"80085785",
+1271 => x"ad3f8008",
+1272 => x"80087e29",
+1273 => x"78902b7c",
+1274 => x"902a0756",
+1275 => x"56597375",
+1276 => x"27943880",
+1277 => x"08ff0576",
+1278 => x"15555975",
+1279 => x"74268738",
+1280 => x"74742684",
+1281 => x"f3387b52",
+1282 => x"73753151",
+1283 => x"858c3f80",
+1284 => x"085584f6",
+1285 => x"3f800880",
+1286 => x"087e297b",
+1287 => x"83ffff06",
+1288 => x"77902b07",
+1289 => x"56595773",
+1290 => x"78279638",
+1291 => x"8008ff05",
+1292 => x"76155557",
+1293 => x"75742689",
+1294 => x"38777426",
+1295 => x"77713158",
+1296 => x"5a78902b",
+1297 => x"77077b41",
+1298 => x"417f6156",
+1299 => x"547d802e",
+1300 => x"fdc638fe",
+1301 => x"9b397552",
+1302 => x"815184ae",
+1303 => x"3f800856",
+1304 => x"feb13990",
+1305 => x"57fe800a",
+1306 => x"7527fdd3",
+1307 => x"38987571",
+1308 => x"2a80d3d0",
+1309 => x"057033a0",
+1310 => x"73317131",
+1311 => x"535d5e57",
+1312 => x"76802efd",
+1313 => x"cf38a077",
+1314 => x"3175782b",
+1315 => x"77722a07",
+1316 => x"77792b7b",
+1317 => x"7a2b7d74",
+1318 => x"2a077d7b",
+1319 => x"2b73902a",
+1320 => x"7483ffff",
+1321 => x"0671597f",
+1322 => x"772a585e",
+1323 => x"5c415f58",
+1324 => x"5c5483e6",
+1325 => x"3f800854",
+1326 => x"83d03f80",
+1327 => x"08800879",
+1328 => x"2975902b",
+1329 => x"7e902a07",
+1330 => x"56565973",
+1331 => x"75279938",
+1332 => x"8008ff05",
+1333 => x"7b155559",
+1334 => x"7a74268c",
+1335 => x"38737527",
+1336 => x"8738ff19",
+1337 => x"7b155559",
+1338 => x"76527375",
+1339 => x"315183aa",
+1340 => x"3f800855",
+1341 => x"83943f80",
+1342 => x"08800879",
+1343 => x"297d83ff",
+1344 => x"ff067790",
+1345 => x"2b075659",
+1346 => x"57737827",
+1347 => x"99388008",
+1348 => x"ff057b15",
+1349 => x"55577a74",
+1350 => x"268c3873",
+1351 => x"78278738",
+1352 => x"ff177b15",
+1353 => x"55577378",
+1354 => x"3179902b",
+1355 => x"78077083",
+1356 => x"ffff0671",
+1357 => x"902a7983",
+1358 => x"ffff067a",
+1359 => x"902a7372",
+1360 => x"29737329",
+1361 => x"74732976",
+1362 => x"74297390",
+1363 => x"2a057205",
+1364 => x"5755435f",
+1365 => x"5b585a57",
+1366 => x"595a747c",
+1367 => x"27863884",
+1368 => x"80801757",
+1369 => x"74902a17",
+1370 => x"7983ffff",
+1371 => x"06768480",
+1372 => x"80290557",
+1373 => x"57767a26",
+1374 => x"9a38767a",
+1375 => x"32703070",
+1376 => x"72078025",
+1377 => x"565a5b7c",
+1378 => x"7627fafe",
+1379 => x"3873802e",
+1380 => x"faf838ff",
+1381 => x"1858805b",
+1382 => x"faf239ff",
+1383 => x"76537754",
+1384 => x"9f3de805",
+1385 => x"525ef7e1",
+1386 => x"3f676957",
+1387 => x"4c754d69",
+1388 => x"8025f8f3",
+1389 => x"387d096a",
+1390 => x"6c5c537a",
+1391 => x"549f3de8",
+1392 => x"05525ef7",
+1393 => x"c43f6769",
+1394 => x"714c704d",
+1395 => x"5856f8db",
+1396 => x"39a07531",
+1397 => x"76762b7a",
+1398 => x"772b7c73",
+1399 => x"2a077c78",
+1400 => x"2b72902a",
+1401 => x"7383ffff",
+1402 => x"0671587e",
+1403 => x"762a5742",
+1404 => x"405d5d57",
+1405 => x"5881a33f",
+1406 => x"80085781",
+1407 => x"8d3f8008",
+1408 => x"80087e29",
+1409 => x"78902b7d",
+1410 => x"902a0756",
+1411 => x"56597375",
+1412 => x"27993880",
+1413 => x"08ff0576",
+1414 => x"15555975",
+1415 => x"74268c38",
+1416 => x"73752787",
+1417 => x"38ff1976",
+1418 => x"1555597b",
+1419 => x"52737531",
+1420 => x"5180e73f",
+1421 => x"80085580",
+1422 => x"d13f8008",
+1423 => x"80087e29",
+1424 => x"7c83ffff",
+1425 => x"06707890",
+1426 => x"2b075156",
+1427 => x"58587377",
+1428 => x"27993880",
+1429 => x"08ff0576",
+1430 => x"15555875",
+1431 => x"74268c38",
+1432 => x"73772787",
+1433 => x"38ff1876",
+1434 => x"15555878",
+1435 => x"902b7807",
+1436 => x"74783155",
+1437 => x"5bfada39",
+1438 => x"ff197615",
+1439 => x"5559fb86",
+1440 => x"39ff1976",
+1441 => x"155559f8",
+1442 => x"c0397070",
+1443 => x"70805375",
+1444 => x"52745181",
+1445 => x"913f5050",
+1446 => x"50047070",
+1447 => x"70815375",
+1448 => x"52745181",
+1449 => x"813f5050",
+1450 => x"5004fb3d",
+1451 => x"0d777955",
+1452 => x"55805675",
+1453 => x"7524ab38",
+1454 => x"8074249d",
+1455 => x"38805373",
+1456 => x"52745180",
+1457 => x"e13f8008",
+1458 => x"5475802e",
+1459 => x"85388008",
+1460 => x"30547380",
+1461 => x"0c873d0d",
+1462 => x"04733076",
+1463 => x"81325754",
+1464 => x"dc397430",
+1465 => x"55815673",
+1466 => x"8025d238",
+1467 => x"ec39fa3d",
+1468 => x"0d787a57",
+1469 => x"55805776",
+1470 => x"7524a438",
+1471 => x"759f2c54",
+1472 => x"81537574",
+1473 => x"32743152",
+1474 => x"74519b3f",
+1475 => x"80085476",
+1476 => x"802e8538",
+1477 => x"80083054",
+1478 => x"73800c88",
+1479 => x"3d0d0474",
+1480 => x"30558157",
+1481 => x"d739fc3d",
+1482 => x"0d767853",
+1483 => x"54815380",
+1484 => x"74732652",
+1485 => x"5572802e",
+1486 => x"98387080",
+1487 => x"2eab3880",
+1488 => x"7224a638",
+1489 => x"71107310",
+1490 => x"75722653",
+1491 => x"545272ea",
+1492 => x"38735178",
+1493 => x"83387451",
+1494 => x"70800c86",
+1495 => x"3d0d0472",
+1496 => x"0a100a72",
+1497 => x"0a100a53",
+1498 => x"5372802e",
+1499 => x"e4387174",
+1500 => x"26ed3873",
+1501 => x"72317574",
+1502 => x"07740a10",
+1503 => x"0a740a10",
+1504 => x"0a555556",
+1505 => x"54e33970",
+1506 => x"70735280",
+1507 => x"decc0851",
+1508 => x"933f5050",
+1509 => x"04707073",
+1510 => x"5280decc",
+1511 => x"085190ce",
+1512 => x"3f505004",
+1513 => x"f43d0d7e",
+1514 => x"608b1170",
+1515 => x"f8065b55",
+1516 => x"555d7296",
+1517 => x"26833890",
+1518 => x"58807824",
+1519 => x"74792607",
+1520 => x"55805474",
+1521 => x"742e0981",
+1522 => x"0680ca38",
+1523 => x"7c518d9e",
+1524 => x"3f7783f7",
+1525 => x"2680c538",
+1526 => x"77832a70",
+1527 => x"10101080",
+1528 => x"d6c4058c",
+1529 => x"11085858",
+1530 => x"5475772e",
+1531 => x"81f03884",
+1532 => x"1608fc06",
+1533 => x"8c170888",
+1534 => x"1808718c",
+1535 => x"120c8812",
+1536 => x"0c5b7605",
+1537 => x"84110881",
+1538 => x"0784120c",
+1539 => x"537c518c",
+1540 => x"de3f8816",
+1541 => x"5473800c",
+1542 => x"8e3d0d04",
+1543 => x"77892a78",
+1544 => x"832a5854",
+1545 => x"73802ebf",
+1546 => x"3877862a",
+1547 => x"b8055784",
+1548 => x"7427b438",
+1549 => x"80db1457",
+1550 => x"947427ab",
+1551 => x"38778c2a",
+1552 => x"80ee0557",
+1553 => x"80d47427",
+1554 => x"9e38778f",
+1555 => x"2a80f705",
+1556 => x"5782d474",
+1557 => x"27913877",
+1558 => x"922a80fc",
+1559 => x"05578ad4",
+1560 => x"74278438",
+1561 => x"80fe5776",
+1562 => x"10101080",
+1563 => x"d6c4058c",
+1564 => x"11085653",
+1565 => x"74732ea3",
+1566 => x"38841508",
+1567 => x"fc067079",
+1568 => x"31555673",
+1569 => x"8f2488e4",
+1570 => x"38738025",
+1571 => x"88e6388c",
+1572 => x"15085574",
+1573 => x"732e0981",
+1574 => x"06df3881",
+1575 => x"175980d6",
+1576 => x"d4085675",
+1577 => x"80d6cc2e",
+1578 => x"82cc3884",
+1579 => x"1608fc06",
+1580 => x"70793155",
+1581 => x"55738f24",
+1582 => x"bb3880d6",
+1583 => x"cc0b80d6",
+1584 => x"d80c80d6",
+1585 => x"cc0b80d6",
+1586 => x"d40c8074",
+1587 => x"2480db38",
+1588 => x"74168411",
+1589 => x"08810784",
+1590 => x"120c53fe",
+1591 => x"b0398816",
+1592 => x"8c110857",
+1593 => x"5975792e",
+1594 => x"098106fe",
+1595 => x"82388214",
+1596 => x"59ffab39",
+1597 => x"77167881",
+1598 => x"0784180c",
+1599 => x"7080d6d8",
+1600 => x"0c7080d6",
+1601 => x"d40c80d6",
+1602 => x"cc0b8c12",
+1603 => x"0c8c1108",
+1604 => x"88120c74",
+1605 => x"81078412",
+1606 => x"0c740574",
+1607 => x"710c5b7c",
+1608 => x"518acc3f",
+1609 => x"881654fd",
+1610 => x"ec3983ff",
+1611 => x"75278391",
+1612 => x"3874892a",
+1613 => x"75832a54",
+1614 => x"5473802e",
+1615 => x"bf387486",
+1616 => x"2ab80553",
+1617 => x"847427b4",
+1618 => x"3880db14",
+1619 => x"53947427",
+1620 => x"ab38748c",
+1621 => x"2a80ee05",
+1622 => x"5380d474",
+1623 => x"279e3874",
+1624 => x"8f2a80f7",
+1625 => x"055382d4",
+1626 => x"74279138",
+1627 => x"74922a80",
+1628 => x"fc05538a",
+1629 => x"d4742784",
+1630 => x"3880fe53",
+1631 => x"72101010",
+1632 => x"80d6c405",
+1633 => x"88110855",
+1634 => x"5773772e",
+1635 => x"868b3884",
+1636 => x"1408fc06",
+1637 => x"5b747b27",
+1638 => x"8d388814",
+1639 => x"08547377",
+1640 => x"2e098106",
+1641 => x"ea388c14",
+1642 => x"0880d6c4",
+1643 => x"0b840508",
+1644 => x"718c190c",
+1645 => x"7588190c",
+1646 => x"7788130c",
+1647 => x"5c57758c",
+1648 => x"150c7853",
+1649 => x"80792483",
+1650 => x"98387282",
+1651 => x"2c81712b",
+1652 => x"5656747b",
+1653 => x"2680ca38",
+1654 => x"7a750657",
+1655 => x"7682a338",
+1656 => x"78fc0684",
+1657 => x"05597410",
+1658 => x"707c0655",
+1659 => x"55738292",
+1660 => x"38841959",
+1661 => x"f13980d6",
+1662 => x"c40b8405",
+1663 => x"0879545b",
+1664 => x"788025c6",
+1665 => x"3882da39",
+1666 => x"74097b06",
+1667 => x"7080d6c4",
+1668 => x"0b84050c",
+1669 => x"5b741055",
+1670 => x"747b2685",
+1671 => x"387485bc",
+1672 => x"3880d6c4",
+1673 => x"0b880508",
+1674 => x"70841208",
+1675 => x"fc06707b",
+1676 => x"317b7226",
+1677 => x"8f722507",
+1678 => x"5d575c5c",
+1679 => x"5578802e",
+1680 => x"80d93879",
+1681 => x"1580d6bc",
+1682 => x"08199011",
+1683 => x"59545680",
+1684 => x"d6b808ff",
+1685 => x"2e8838a0",
+1686 => x"8f13e080",
+1687 => x"06577652",
+1688 => x"7c51888c",
+1689 => x"3f800854",
+1690 => x"8008ff2e",
+1691 => x"90388008",
+1692 => x"762782a7",
+1693 => x"387480d6",
+1694 => x"c42e829f",
+1695 => x"3880d6c4",
+1696 => x"0b880508",
+1697 => x"55841508",
+1698 => x"fc067079",
+1699 => x"31797226",
+1700 => x"8f722507",
+1701 => x"5d555a7a",
+1702 => x"83f23877",
+1703 => x"81078416",
+1704 => x"0c771570",
+1705 => x"80d6c40b",
+1706 => x"88050c74",
+1707 => x"81078412",
+1708 => x"0c567c51",
+1709 => x"87b93f88",
+1710 => x"15547380",
+1711 => x"0c8e3d0d",
+1712 => x"0474832a",
+1713 => x"70545480",
+1714 => x"7424819b",
+1715 => x"3872822c",
+1716 => x"81712b80",
+1717 => x"d6c80807",
+1718 => x"7080d6c4",
+1719 => x"0b84050c",
+1720 => x"75101010",
+1721 => x"80d6c405",
+1722 => x"88110871",
+1723 => x"8c1b0c70",
+1724 => x"881b0c79",
+1725 => x"88130c57",
+1726 => x"555c5575",
+1727 => x"8c150cfd",
+1728 => x"c1397879",
+1729 => x"10101080",
+1730 => x"d6c40570",
+1731 => x"565b5c8c",
+1732 => x"14085675",
+1733 => x"742ea338",
+1734 => x"841608fc",
+1735 => x"06707931",
+1736 => x"5853768f",
+1737 => x"2483f138",
+1738 => x"76802584",
+1739 => x"af388c16",
+1740 => x"08567574",
+1741 => x"2e098106",
+1742 => x"df388814",
+1743 => x"811a7083",
+1744 => x"06555a54",
+1745 => x"72c9387b",
+1746 => x"83065675",
+1747 => x"802efdb8",
+1748 => x"38ff1cf8",
+1749 => x"1b5b5c88",
+1750 => x"1a087a2e",
+1751 => x"ea38fdb5",
+1752 => x"39831953",
+1753 => x"fce43983",
+1754 => x"1470822c",
+1755 => x"81712b80",
+1756 => x"d6c80807",
+1757 => x"7080d6c4",
+1758 => x"0b84050c",
+1759 => x"76101010",
+1760 => x"80d6c405",
+1761 => x"88110871",
+1762 => x"8c1c0c70",
+1763 => x"881c0c7a",
+1764 => x"88130c58",
+1765 => x"535d5653",
+1766 => x"fee13980",
+1767 => x"d6880817",
+1768 => x"59800876",
+1769 => x"2e818b38",
+1770 => x"80d6b808",
+1771 => x"ff2e848e",
+1772 => x"38737631",
+1773 => x"1980d688",
+1774 => x"0c738706",
+1775 => x"70565372",
+1776 => x"802e8838",
+1777 => x"88733170",
+1778 => x"15555576",
+1779 => x"149fff06",
+1780 => x"a0807131",
+1781 => x"1670547e",
+1782 => x"53515385",
+1783 => x"933f8008",
+1784 => x"568008ff",
+1785 => x"2e819e38",
+1786 => x"80d68808",
+1787 => x"137080d6",
+1788 => x"880c7475",
+1789 => x"80d6c40b",
+1790 => x"88050c77",
+1791 => x"76311581",
+1792 => x"07555659",
+1793 => x"7a80d6c4",
+1794 => x"2e83c038",
+1795 => x"798f2682",
+1796 => x"ef38810b",
+1797 => x"84150c84",
+1798 => x"1508fc06",
+1799 => x"70793179",
+1800 => x"72268f72",
+1801 => x"25075d55",
+1802 => x"5a7a802e",
+1803 => x"fced3880",
+1804 => x"db398008",
+1805 => x"9fff0655",
+1806 => x"74feed38",
+1807 => x"7880d688",
+1808 => x"0c80d6c4",
+1809 => x"0b880508",
+1810 => x"7a188107",
+1811 => x"84120c55",
+1812 => x"80d6b408",
+1813 => x"79278638",
+1814 => x"7880d6b4",
+1815 => x"0c80d6b0",
+1816 => x"087927fc",
+1817 => x"a0387880",
+1818 => x"d6b00c84",
+1819 => x"1508fc06",
+1820 => x"70793179",
+1821 => x"72268f72",
+1822 => x"25075d55",
+1823 => x"5a7a802e",
+1824 => x"fc993888",
+1825 => x"39807457",
+1826 => x"53fedd39",
+1827 => x"7c5183df",
+1828 => x"3f800b80",
+1829 => x"0c8e3d0d",
+1830 => x"04807324",
+1831 => x"a5387282",
+1832 => x"2c81712b",
+1833 => x"80d6c808",
+1834 => x"077080d6",
+1835 => x"c40b8405",
+1836 => x"0c5c5a76",
+1837 => x"8c170c73",
+1838 => x"88170c75",
+1839 => x"88180cf9",
+1840 => x"fd398313",
+1841 => x"70822c81",
+1842 => x"712b80d6",
+1843 => x"c8080770",
+1844 => x"80d6c40b",
+1845 => x"84050c5d",
+1846 => x"5b53d839",
+1847 => x"7a75065c",
+1848 => x"7bfc9f38",
+1849 => x"84197510",
+1850 => x"5659f139",
+1851 => x"ff178105",
+1852 => x"59f7ab39",
+1853 => x"8c150888",
+1854 => x"1608718c",
+1855 => x"120c8812",
+1856 => x"0c597515",
+1857 => x"84110881",
+1858 => x"0784120c",
+1859 => x"587c5182",
+1860 => x"de3f8815",
+1861 => x"54fba339",
+1862 => x"77167881",
+1863 => x"0784180c",
+1864 => x"8c170888",
+1865 => x"1808718c",
+1866 => x"120c8812",
+1867 => x"0c5c7080",
+1868 => x"d6d80c70",
+1869 => x"80d6d40c",
+1870 => x"80d6cc0b",
+1871 => x"8c120c8c",
+1872 => x"11088812",
+1873 => x"0c778107",
+1874 => x"84120c77",
+1875 => x"0577710c",
+1876 => x"557c5182",
+1877 => x"9a3f8816",
+1878 => x"54f5ba39",
+1879 => x"72168411",
+1880 => x"08810784",
+1881 => x"120c588c",
+1882 => x"16088817",
+1883 => x"08718c12",
+1884 => x"0c88120c",
+1885 => x"577c5181",
+1886 => x"f63f8816",
+1887 => x"54f59639",
+1888 => x"7284150c",
+1889 => x"f41af806",
+1890 => x"70841d08",
+1891 => x"81060784",
+1892 => x"1d0c701c",
+1893 => x"5556850b",
+1894 => x"84150c85",
+1895 => x"0b88150c",
+1896 => x"8f7627fd",
+1897 => x"ab38881b",
+1898 => x"527c5184",
+1899 => x"c13f80d6",
+1900 => x"c40b8805",
+1901 => x"0880d688",
+1902 => x"085a55fd",
+1903 => x"93397880",
+1904 => x"d6880c73",
+1905 => x"80d6b80c",
+1906 => x"fbef3972",
+1907 => x"84150cfc",
+1908 => x"ff39fb3d",
+1909 => x"0d77707a",
+1910 => x"7c585553",
+1911 => x"568f7527",
+1912 => x"80e63872",
+1913 => x"76078306",
+1914 => x"517080dc",
+1915 => x"38757352",
+1916 => x"54707084",
+1917 => x"05520874",
+1918 => x"70840556",
+1919 => x"0c737170",
+1920 => x"84055308",
+1921 => x"71708405",
+1922 => x"530c7170",
+1923 => x"84055308",
+1924 => x"71708405",
+1925 => x"530c7170",
+1926 => x"84055308",
+1927 => x"71708405",
+1928 => x"530cf016",
+1929 => x"5654748f",
+1930 => x"26c73883",
+1931 => x"75279538",
+1932 => x"70708405",
+1933 => x"52087470",
+1934 => x"8405560c",
+1935 => x"fc155574",
+1936 => x"8326ed38",
+1937 => x"73715452",
+1938 => x"ff155170",
+1939 => x"ff2e9838",
+1940 => x"72708105",
+1941 => x"54337270",
+1942 => x"81055434",
+1943 => x"ff115170",
+1944 => x"ff2e0981",
+1945 => x"06ea3875",
+1946 => x"800c873d",
+1947 => x"0d040404",
+1948 => x"70707070",
+1949 => x"800b81b6",
+1950 => x"9c0c7651",
+1951 => x"87cc3f80",
+1952 => x"08538008",
+1953 => x"ff2e8938",
+1954 => x"72800c50",
+1955 => x"50505004",
+1956 => x"81b69c08",
+1957 => x"5473802e",
+1958 => x"ef387574",
+1959 => x"710c5272",
+1960 => x"800c5050",
+1961 => x"505004fb",
+1962 => x"3d0d7779",
+1963 => x"70720783",
+1964 => x"06535452",
+1965 => x"70933871",
+1966 => x"73730854",
+1967 => x"56547173",
+1968 => x"082e80c4",
+1969 => x"38737554",
+1970 => x"52713370",
+1971 => x"81ff0652",
+1972 => x"5470802e",
+1973 => x"9d387233",
+1974 => x"5570752e",
+1975 => x"09810695",
+1976 => x"38811281",
+1977 => x"14713370",
+1978 => x"81ff0654",
+1979 => x"56545270",
+1980 => x"e5387233",
+1981 => x"557381ff",
+1982 => x"067581ff",
+1983 => x"06717131",
+1984 => x"800c5552",
+1985 => x"873d0d04",
+1986 => x"7109f7fb",
+1987 => x"fdff1306",
+1988 => x"f8848281",
+1989 => x"80065271",
+1990 => x"97388414",
+1991 => x"84167108",
+1992 => x"54565471",
+1993 => x"75082ee0",
+1994 => x"38737554",
+1995 => x"52ff9a39",
+1996 => x"800b800c",
+1997 => x"873d0d04",
+1998 => x"fb3d0d77",
+1999 => x"705256fe",
+2000 => x"ad3f80d6",
+2001 => x"c40b8805",
+2002 => x"08841108",
+2003 => x"fc06707b",
+2004 => x"319fef05",
+2005 => x"e08006e0",
+2006 => x"80055255",
+2007 => x"55a08075",
+2008 => x"24943880",
+2009 => x"527551fe",
+2010 => x"873f80d6",
+2011 => x"cc081453",
+2012 => x"7280082e",
+2013 => x"8f387551",
+2014 => x"fdf53f80",
+2015 => x"5372800c",
+2016 => x"873d0d04",
+2017 => x"74305275",
+2018 => x"51fde53f",
+2019 => x"8008ff2e",
+2020 => x"a83880d6",
+2021 => x"c40b8805",
+2022 => x"08747631",
+2023 => x"81078412",
+2024 => x"0c5380d6",
+2025 => x"88087531",
+2026 => x"80d6880c",
+2027 => x"7551fdbf",
+2028 => x"3f810b80",
+2029 => x"0c873d0d",
+2030 => x"04805275",
+2031 => x"51fdb13f",
+2032 => x"80d6c40b",
+2033 => x"88050880",
+2034 => x"08713154",
+2035 => x"548f7325",
+2036 => x"ffa43880",
+2037 => x"0880d6b8",
+2038 => x"083180d6",
+2039 => x"880c7281",
+2040 => x"0784150c",
+2041 => x"7551fd87",
+2042 => x"3f8053ff",
+2043 => x"9039f73d",
+2044 => x"0d7b7d54",
+2045 => x"5a72802e",
+2046 => x"82833879",
+2047 => x"51fcef3f",
+2048 => x"f8138411",
+2049 => x"0870fe06",
+2050 => x"70138411",
+2051 => x"08fc065c",
+2052 => x"57585457",
+2053 => x"80d6cc08",
+2054 => x"742e82de",
+2055 => x"38778415",
+2056 => x"0c807381",
+2057 => x"06565974",
+2058 => x"792e81d5",
+2059 => x"38771484",
+2060 => x"11088106",
+2061 => x"565374a0",
+2062 => x"38771656",
+2063 => x"7881e638",
+2064 => x"88140855",
+2065 => x"7480d6cc",
+2066 => x"2e82f938",
+2067 => x"8c140870",
+2068 => x"8c170c75",
+2069 => x"88120c58",
+2070 => x"75810784",
+2071 => x"180c7517",
+2072 => x"76710c54",
+2073 => x"78819138",
+2074 => x"83ff7627",
+2075 => x"81c83875",
+2076 => x"892a7683",
+2077 => x"2a545473",
+2078 => x"802ebf38",
+2079 => x"75862ab8",
+2080 => x"05538474",
+2081 => x"27b43880",
+2082 => x"db145394",
+2083 => x"7427ab38",
+2084 => x"758c2a80",
+2085 => x"ee055380",
+2086 => x"d474279e",
+2087 => x"38758f2a",
+2088 => x"80f70553",
+2089 => x"82d47427",
+2090 => x"91387592",
+2091 => x"2a80fc05",
+2092 => x"538ad474",
+2093 => x"27843880",
+2094 => x"fe537210",
+2095 => x"101080d6",
+2096 => x"c4058811",
+2097 => x"08555573",
+2098 => x"752e82bf",
+2099 => x"38841408",
+2100 => x"fc065975",
+2101 => x"79278d38",
+2102 => x"88140854",
+2103 => x"73752e09",
+2104 => x"8106ea38",
+2105 => x"8c140870",
+2106 => x"8c190c74",
+2107 => x"88190c77",
+2108 => x"88120c55",
+2109 => x"768c150c",
+2110 => x"7951faf3",
+2111 => x"3f8b3d0d",
+2112 => x"04760877",
+2113 => x"71315876",
+2114 => x"05881808",
+2115 => x"56567480",
+2116 => x"d6cc2e80",
+2117 => x"e0388c17",
+2118 => x"08708c17",
+2119 => x"0c758812",
+2120 => x"0c53fe89",
+2121 => x"39881408",
+2122 => x"8c150870",
+2123 => x"8c130c59",
+2124 => x"88190cfe",
+2125 => x"a3397583",
+2126 => x"2a705454",
+2127 => x"80742481",
+2128 => x"98387282",
+2129 => x"2c81712b",
+2130 => x"80d6c808",
+2131 => x"0780d6c4",
+2132 => x"0b84050c",
+2133 => x"74101010",
+2134 => x"80d6c405",
+2135 => x"88110871",
+2136 => x"8c1b0c70",
+2137 => x"881b0c79",
+2138 => x"88130c56",
+2139 => x"5a55768c",
+2140 => x"150cff84",
+2141 => x"398159fd",
+2142 => x"b4397716",
+2143 => x"73810654",
+2144 => x"55729838",
+2145 => x"76087771",
+2146 => x"31587505",
+2147 => x"8c180888",
+2148 => x"1908718c",
+2149 => x"120c8812",
+2150 => x"0c555574",
+2151 => x"81078418",
+2152 => x"0c7680d6",
+2153 => x"c40b8805",
+2154 => x"0c80d6c0",
+2155 => x"087526fe",
+2156 => x"c73880d6",
+2157 => x"bc085279",
+2158 => x"51fafd3f",
+2159 => x"7951f9af",
+2160 => x"3ffeba39",
+2161 => x"81778c17",
+2162 => x"0c778817",
+2163 => x"0c758c19",
+2164 => x"0c758819",
+2165 => x"0c59fd80",
+2166 => x"39831470",
+2167 => x"822c8171",
+2168 => x"2b80d6c8",
+2169 => x"080780d6",
+2170 => x"c40b8405",
+2171 => x"0c751010",
+2172 => x"1080d6c4",
+2173 => x"05881108",
+2174 => x"718c1c0c",
+2175 => x"70881c0c",
+2176 => x"7a88130c",
+2177 => x"575b5653",
+2178 => x"fee43980",
+2179 => x"7324a338",
+2180 => x"72822c81",
+2181 => x"712b80d6",
+2182 => x"c8080780",
+2183 => x"d6c40b84",
+2184 => x"050c5874",
+2185 => x"8c180c73",
+2186 => x"88180c76",
+2187 => x"88160cfd",
+2188 => x"c3398313",
+2189 => x"70822c81",
+2190 => x"712b80d6",
+2191 => x"c8080780",
+2192 => x"d6c40b84",
+2193 => x"050c5953",
+2194 => x"da397070",
+2195 => x"7080e5f4",
+2196 => x"08893881",
+2197 => x"b6a00b80",
+2198 => x"e5f40c80",
+2199 => x"e5f40875",
+2200 => x"115252ff",
+2201 => x"537087fb",
+2202 => x"80802688",
+2203 => x"387080e5",
+2204 => x"f40c7153",
+2205 => x"72800c50",
+2206 => x"505004fd",
+2207 => x"3d0d800b",
+2208 => x"80d5f408",
+2209 => x"54547281",
+2210 => x"2e9b3873",
+2211 => x"80e5f80c",
+2212 => x"c3ee3fc2",
+2213 => x"eb3f80e5",
+2214 => x"cc528151",
+2215 => x"cc933f80",
+2216 => x"085180dd",
+2217 => x"3f7280e5",
+2218 => x"f80cc3d4",
+2219 => x"3fc2d13f",
+2220 => x"80e5cc52",
+2221 => x"8151cbf9",
+2222 => x"3f800851",
+2223 => x"80c33f00",
+2224 => x"ff3900ff",
+2225 => x"39f43d0d",
+2226 => x"7e80e5ec",
+2227 => x"08700870",
+2228 => x"81ff0692",
+2229 => x"3df80555",
+2230 => x"515a5759",
+2231 => x"c48f3f80",
+2232 => x"5477557b",
+2233 => x"7d585276",
+2234 => x"538e3df0",
+2235 => x"0551de8e",
+2236 => x"3f797b58",
+2237 => x"790c7684",
+2238 => x"1a0c7880",
+2239 => x"0c8e3d0d",
+2240 => x"04f73d0d",
+2241 => x"7b80decc",
+2242 => x"0882c811",
+2243 => x"085a545a",
+2244 => x"77802e80",
+2245 => x"da388188",
+2246 => x"18841908",
+2247 => x"ff058171",
+2248 => x"2b595559",
+2249 => x"80742480",
+2250 => x"ea388074",
+2251 => x"24b53873",
+2252 => x"822b7811",
+2253 => x"88055656",
+2254 => x"81801908",
+2255 => x"77065372",
+2256 => x"802eb638",
+2257 => x"78167008",
+2258 => x"53537951",
+2259 => x"74085372",
+2260 => x"2dff14fc",
+2261 => x"17fc1779",
+2262 => x"812c5a57",
+2263 => x"57547380",
+2264 => x"25d63877",
+2265 => x"085877ff",
+2266 => x"ad3880de",
+2267 => x"cc0853bc",
+2268 => x"1308a538",
+2269 => x"7951fec7",
+2270 => x"3f740853",
+2271 => x"722dff14",
+2272 => x"fc17fc17",
+2273 => x"79812c5a",
+2274 => x"57575473",
+2275 => x"8025ffa8",
+2276 => x"38d13980",
+2277 => x"57ff9339",
+2278 => x"7251bc13",
+2279 => x"0854732d",
+2280 => x"7951fe9b",
+2281 => x"3f707080",
+2282 => x"e5d40bfc",
+2283 => x"05700852",
+2284 => x"5270ff2e",
+2285 => x"9138702d",
+2286 => x"fc127008",
+2287 => x"525270ff",
+2288 => x"2e098106",
+2289 => x"f1385050",
+2290 => x"0404c2ff",
+2291 => x"3f040000",
+2292 => x"00000040",
+2293 => x"30313233",
+2294 => x"34353637",
+2295 => x"38390000",
+2296 => x"44485259",
+2297 => x"53544f4e",
+2298 => x"45205052",
+2299 => x"4f475241",
+2300 => x"4d2c2053",
+2301 => x"4f4d4520",
+2302 => x"53545249",
+2303 => x"4e470000",
+2304 => x"44485259",
+2305 => x"53544f4e",
+2306 => x"45205052",
+2307 => x"4f475241",
+2308 => x"4d2c2031",
+2309 => x"27535420",
+2310 => x"53545249",
+2311 => x"4e470000",
+2312 => x"44687279",
+2313 => x"73746f6e",
+2314 => x"65204265",
+2315 => x"6e63686d",
+2316 => x"61726b2c",
+2317 => x"20566572",
+2318 => x"73696f6e",
+2319 => x"20322e31",
+2320 => x"20284c61",
+2321 => x"6e677561",
+2322 => x"67653a20",
+2323 => x"43290a00",
+2324 => x"50726f67",
+2325 => x"72616d20",
+2326 => x"636f6d70",
+2327 => x"696c6564",
+2328 => x"20776974",
+2329 => x"68202772",
+2330 => x"65676973",
+2331 => x"74657227",
+2332 => x"20617474",
+2333 => x"72696275",
+2334 => x"74650a00",
+2335 => x"45786563",
+2336 => x"7574696f",
+2337 => x"6e207374",
+2338 => x"61727473",
+2339 => x"2c202564",
+2340 => x"2072756e",
+2341 => x"73207468",
+2342 => x"726f7567",
+2343 => x"68204468",
+2344 => x"72797374",
+2345 => x"6f6e650a",
+2346 => x"00000000",
+2347 => x"44485259",
+2348 => x"53544f4e",
+2349 => x"45205052",
+2350 => x"4f475241",
+2351 => x"4d2c2032",
+2352 => x"274e4420",
+2353 => x"53545249",
+2354 => x"4e470000",
+2355 => x"45786563",
+2356 => x"7574696f",
+2357 => x"6e20656e",
+2358 => x"64730a00",
+2359 => x"46696e61",
+2360 => x"6c207661",
+2361 => x"6c756573",
+2362 => x"206f6620",
+2363 => x"74686520",
+2364 => x"76617269",
+2365 => x"61626c65",
+2366 => x"73207573",
+2367 => x"65642069",
+2368 => x"6e207468",
+2369 => x"65206265",
+2370 => x"6e63686d",
+2371 => x"61726b3a",
+2372 => x"0a000000",
+2373 => x"496e745f",
+2374 => x"476c6f62",
+2375 => x"3a202020",
+2376 => x"20202020",
+2377 => x"20202020",
+2378 => x"2025640a",
+2379 => x"00000000",
+2380 => x"20202020",
+2381 => x"20202020",
+2382 => x"73686f75",
+2383 => x"6c642062",
+2384 => x"653a2020",
+2385 => x"2025640a",
+2386 => x"00000000",
+2387 => x"426f6f6c",
+2388 => x"5f476c6f",
+2389 => x"623a2020",
+2390 => x"20202020",
+2391 => x"20202020",
+2392 => x"2025640a",
+2393 => x"00000000",
+2394 => x"43685f31",
+2395 => x"5f476c6f",
+2396 => x"623a2020",
+2397 => x"20202020",
+2398 => x"20202020",
+2399 => x"2025630a",
+2400 => x"00000000",
+2401 => x"20202020",
+2402 => x"20202020",
+2403 => x"73686f75",
+2404 => x"6c642062",
+2405 => x"653a2020",
+2406 => x"2025630a",
+2407 => x"00000000",
+2408 => x"43685f32",
+2409 => x"5f476c6f",
+2410 => x"623a2020",
+2411 => x"20202020",
+2412 => x"20202020",
+2413 => x"2025630a",
+2414 => x"00000000",
+2415 => x"4172725f",
+2416 => x"315f476c",
+2417 => x"6f625b38",
+2418 => x"5d3a2020",
+2419 => x"20202020",
+2420 => x"2025640a",
+2421 => x"00000000",
+2422 => x"4172725f",
+2423 => x"325f476c",
+2424 => x"6f625b38",
+2425 => x"5d5b375d",
+2426 => x"3a202020",
+2427 => x"2025640a",
+2428 => x"00000000",
+2429 => x"20202020",
+2430 => x"20202020",
+2431 => x"73686f75",
+2432 => x"6c642062",
+2433 => x"653a2020",
+2434 => x"204e756d",
+2435 => x"6265725f",
+2436 => x"4f665f52",
+2437 => x"756e7320",
+2438 => x"2b203130",
+2439 => x"0a000000",
+2440 => x"5074725f",
+2441 => x"476c6f62",
+2442 => x"2d3e0a00",
+2443 => x"20205074",
+2444 => x"725f436f",
+2445 => x"6d703a20",
+2446 => x"20202020",
+2447 => x"20202020",
+2448 => x"2025640a",
+2449 => x"00000000",
+2450 => x"20202020",
+2451 => x"20202020",
+2452 => x"73686f75",
+2453 => x"6c642062",
+2454 => x"653a2020",
+2455 => x"2028696d",
+2456 => x"706c656d",
+2457 => x"656e7461",
+2458 => x"74696f6e",
+2459 => x"2d646570",
+2460 => x"656e6465",
+2461 => x"6e74290a",
+2462 => x"00000000",
+2463 => x"20204469",
+2464 => x"7363723a",
+2465 => x"20202020",
+2466 => x"20202020",
+2467 => x"20202020",
+2468 => x"2025640a",
+2469 => x"00000000",
+2470 => x"2020456e",
+2471 => x"756d5f43",
+2472 => x"6f6d703a",
+2473 => x"20202020",
+2474 => x"20202020",
+2475 => x"2025640a",
+2476 => x"00000000",
+2477 => x"2020496e",
+2478 => x"745f436f",
+2479 => x"6d703a20",
+2480 => x"20202020",
+2481 => x"20202020",
+2482 => x"2025640a",
+2483 => x"00000000",
+2484 => x"20205374",
+2485 => x"725f436f",
+2486 => x"6d703a20",
+2487 => x"20202020",
+2488 => x"20202020",
+2489 => x"2025730a",
+2490 => x"00000000",
+2491 => x"20202020",
+2492 => x"20202020",
+2493 => x"73686f75",
+2494 => x"6c642062",
+2495 => x"653a2020",
+2496 => x"20444852",
+2497 => x"5953544f",
+2498 => x"4e452050",
+2499 => x"524f4752",
+2500 => x"414d2c20",
+2501 => x"534f4d45",
+2502 => x"20535452",
+2503 => x"494e470a",
+2504 => x"00000000",
+2505 => x"4e657874",
+2506 => x"5f507472",
+2507 => x"5f476c6f",
+2508 => x"622d3e0a",
+2509 => x"00000000",
+2510 => x"20202020",
+2511 => x"20202020",
+2512 => x"73686f75",
+2513 => x"6c642062",
+2514 => x"653a2020",
+2515 => x"2028696d",
+2516 => x"706c656d",
+2517 => x"656e7461",
+2518 => x"74696f6e",
+2519 => x"2d646570",
+2520 => x"656e6465",
+2521 => x"6e74292c",
+2522 => x"2073616d",
+2523 => x"65206173",
+2524 => x"2061626f",
+2525 => x"76650a00",
+2526 => x"496e745f",
+2527 => x"315f4c6f",
+2528 => x"633a2020",
+2529 => x"20202020",
+2530 => x"20202020",
+2531 => x"2025640a",
+2532 => x"00000000",
+2533 => x"496e745f",
+2534 => x"325f4c6f",
+2535 => x"633a2020",
+2536 => x"20202020",
+2537 => x"20202020",
+2538 => x"2025640a",
+2539 => x"00000000",
+2540 => x"496e745f",
+2541 => x"335f4c6f",
+2542 => x"633a2020",
+2543 => x"20202020",
+2544 => x"20202020",
+2545 => x"2025640a",
+2546 => x"00000000",
+2547 => x"456e756d",
+2548 => x"5f4c6f63",
+2549 => x"3a202020",
+2550 => x"20202020",
+2551 => x"20202020",
+2552 => x"2025640a",
+2553 => x"00000000",
+2554 => x"5374725f",
+2555 => x"315f4c6f",
+2556 => x"633a2020",
+2557 => x"20202020",
+2558 => x"20202020",
+2559 => x"2025730a",
+2560 => x"00000000",
+2561 => x"20202020",
+2562 => x"20202020",
+2563 => x"73686f75",
+2564 => x"6c642062",
+2565 => x"653a2020",
+2566 => x"20444852",
+2567 => x"5953544f",
+2568 => x"4e452050",
+2569 => x"524f4752",
+2570 => x"414d2c20",
+2571 => x"31275354",
+2572 => x"20535452",
+2573 => x"494e470a",
+2574 => x"00000000",
+2575 => x"5374725f",
+2576 => x"325f4c6f",
+2577 => x"633a2020",
+2578 => x"20202020",
+2579 => x"20202020",
+2580 => x"2025730a",
+2581 => x"00000000",
+2582 => x"20202020",
+2583 => x"20202020",
+2584 => x"73686f75",
+2585 => x"6c642062",
+2586 => x"653a2020",
+2587 => x"20444852",
+2588 => x"5953544f",
+2589 => x"4e452050",
+2590 => x"524f4752",
+2591 => x"414d2c20",
+2592 => x"32274e44",
+2593 => x"20535452",
+2594 => x"494e470a",
+2595 => x"00000000",
+2596 => x"55736572",
+2597 => x"2074696d",
+2598 => x"653a2025",
+2599 => x"640a0000",
+2600 => x"4d696372",
+2601 => x"6f736563",
+2602 => x"6f6e6473",
+2603 => x"20666f72",
+2604 => x"206f6e65",
+2605 => x"2072756e",
+2606 => x"20746872",
+2607 => x"6f756768",
+2608 => x"20446872",
+2609 => x"7973746f",
+2610 => x"6e653a20",
+2611 => x"00000000",
+2612 => x"2564200a",
+2613 => x"00000000",
+2614 => x"44687279",
+2615 => x"73746f6e",
+2616 => x"65732070",
+2617 => x"65722053",
+2618 => x"65636f6e",
+2619 => x"643a2020",
+2620 => x"20202020",
+2621 => x"20202020",
+2622 => x"20202020",
+2623 => x"20202020",
+2624 => x"20202020",
+2625 => x"00000000",
+2626 => x"56415820",
+2627 => x"4d495053",
+2628 => x"20726174",
+2629 => x"696e6720",
+2630 => x"2a203130",
+2631 => x"3030203d",
+2632 => x"20256420",
+2633 => x"0a000000",
+2634 => x"50726f67",
+2635 => x"72616d20",
+2636 => x"636f6d70",
+2637 => x"696c6564",
+2638 => x"20776974",
+2639 => x"686f7574",
+2640 => x"20277265",
+2641 => x"67697374",
+2642 => x"65722720",
+2643 => x"61747472",
+2644 => x"69627574",
+2645 => x"650a0000",
+2646 => x"4d656173",
+2647 => x"75726564",
+2648 => x"2074696d",
+2649 => x"6520746f",
+2650 => x"6f20736d",
+2651 => x"616c6c20",
+2652 => x"746f206f",
+2653 => x"62746169",
+2654 => x"6e206d65",
+2655 => x"616e696e",
+2656 => x"6766756c",
+2657 => x"20726573",
+2658 => x"756c7473",
+2659 => x"0a000000",
+2660 => x"506c6561",
+2661 => x"73652069",
+2662 => x"6e637265",
+2663 => x"61736520",
+2664 => x"6e756d62",
+2665 => x"6572206f",
+2666 => x"66207275",
+2667 => x"6e730a00",
+2668 => x"44485259",
+2669 => x"53544f4e",
+2670 => x"45205052",
+2671 => x"4f475241",
+2672 => x"4d2c2033",
+2673 => x"27524420",
+2674 => x"53545249",
+2675 => x"4e470000",
+2676 => x"00010202",
+2677 => x"03030303",
+2678 => x"04040404",
+2679 => x"04040404",
+2680 => x"05050505",
+2681 => x"05050505",
+2682 => x"05050505",
+2683 => x"05050505",
+2684 => x"06060606",
+2685 => x"06060606",
+2686 => x"06060606",
+2687 => x"06060606",
+2688 => x"06060606",
+2689 => x"06060606",
+2690 => x"06060606",
+2691 => x"06060606",
+2692 => x"07070707",
+2693 => x"07070707",
+2694 => x"07070707",
+2695 => x"07070707",
+2696 => x"07070707",
+2697 => x"07070707",
+2698 => x"07070707",
+2699 => x"07070707",
+2700 => x"07070707",
+2701 => x"07070707",
+2702 => x"07070707",
+2703 => x"07070707",
+2704 => x"07070707",
+2705 => x"07070707",
+2706 => x"07070707",
+2707 => x"07070707",
+2708 => x"08080808",
+2709 => x"08080808",
+2710 => x"08080808",
+2711 => x"08080808",
+2712 => x"08080808",
+2713 => x"08080808",
+2714 => x"08080808",
+2715 => x"08080808",
+2716 => x"08080808",
+2717 => x"08080808",
+2718 => x"08080808",
+2719 => x"08080808",
+2720 => x"08080808",
+2721 => x"08080808",
+2722 => x"08080808",
+2723 => x"08080808",
+2724 => x"08080808",
+2725 => x"08080808",
+2726 => x"08080808",
+2727 => x"08080808",
+2728 => x"08080808",
+2729 => x"08080808",
+2730 => x"08080808",
+2731 => x"08080808",
+2732 => x"08080808",
+2733 => x"08080808",
+2734 => x"08080808",
+2735 => x"08080808",
+2736 => x"08080808",
+2737 => x"08080808",
+2738 => x"08080808",
+2739 => x"08080808",
+2740 => x"43000000",
+2741 => x"64756d6d",
+2742 => x"792e6578",
+2743 => x"65000000",
+2744 => x"00ffffff",
+2745 => x"ff00ffff",
+2746 => x"ffff00ff",
+2747 => x"ffffff00",
+2748 => x"00000000",
+2749 => x"00000000",
+2750 => x"00000000",
+2751 => x"000032dc",
+2752 => x"0000c350",
+2753 => x"00000000",
+2754 => x"00000000",
+2755 => x"00000000",
+2756 => x"00000000",
+2757 => x"00000000",
+2758 => x"00000000",
+2759 => x"00000000",
+2760 => x"00000000",
+2761 => x"00000000",
+2762 => x"00000000",
+2763 => x"00000000",
+2764 => x"00000000",
+2765 => x"00000000",
+2766 => x"ffffffff",
+2767 => x"00000000",
+2768 => x"00020000",
+2769 => x"00000000",
+2770 => x"00000000",
+2771 => x"00002b44",
+2772 => x"00002b44",
+2773 => x"00002b4c",
+2774 => x"00002b4c",
+2775 => x"00002b54",
+2776 => x"00002b54",
+2777 => x"00002b5c",
+2778 => x"00002b5c",
+2779 => x"00002b64",
+2780 => x"00002b64",
+2781 => x"00002b6c",
+2782 => x"00002b6c",
+2783 => x"00002b74",
+2784 => x"00002b74",
+2785 => x"00002b7c",
+2786 => x"00002b7c",
+2787 => x"00002b84",
+2788 => x"00002b84",
+2789 => x"00002b8c",
+2790 => x"00002b8c",
+2791 => x"00002b94",
+2792 => x"00002b94",
+2793 => x"00002b9c",
+2794 => x"00002b9c",
+2795 => x"00002ba4",
+2796 => x"00002ba4",
+2797 => x"00002bac",
+2798 => x"00002bac",
+2799 => x"00002bb4",
+2800 => x"00002bb4",
+2801 => x"00002bbc",
+2802 => x"00002bbc",
+2803 => x"00002bc4",
+2804 => x"00002bc4",
+2805 => x"00002bcc",
+2806 => x"00002bcc",
+2807 => x"00002bd4",
+2808 => x"00002bd4",
+2809 => x"00002bdc",
+2810 => x"00002bdc",
+2811 => x"00002be4",
+2812 => x"00002be4",
+2813 => x"00002bec",
+2814 => x"00002bec",
+2815 => x"00002bf4",
+2816 => x"00002bf4",
+2817 => x"00002bfc",
+2818 => x"00002bfc",
+2819 => x"00002c04",
+2820 => x"00002c04",
+2821 => x"00002c0c",
+2822 => x"00002c0c",
+2823 => x"00002c14",
+2824 => x"00002c14",
+2825 => x"00002c1c",
+2826 => x"00002c1c",
+2827 => x"00002c24",
+2828 => x"00002c24",
+2829 => x"00002c2c",
+2830 => x"00002c2c",
+2831 => x"00002c34",
+2832 => x"00002c34",
+2833 => x"00002c3c",
+2834 => x"00002c3c",
+2835 => x"00002c44",
+2836 => x"00002c44",
+2837 => x"00002c4c",
+2838 => x"00002c4c",
+2839 => x"00002c54",
+2840 => x"00002c54",
+2841 => x"00002c5c",
+2842 => x"00002c5c",
+2843 => x"00002c64",
+2844 => x"00002c64",
+2845 => x"00002c6c",
+2846 => x"00002c6c",
+2847 => x"00002c74",
+2848 => x"00002c74",
+2849 => x"00002c7c",
+2850 => x"00002c7c",
+2851 => x"00002c84",
+2852 => x"00002c84",
+2853 => x"00002c8c",
+2854 => x"00002c8c",
+2855 => x"00002c94",
+2856 => x"00002c94",
+2857 => x"00002c9c",
+2858 => x"00002c9c",
+2859 => x"00002ca4",
+2860 => x"00002ca4",
+2861 => x"00002cac",
+2862 => x"00002cac",
+2863 => x"00002cb4",
+2864 => x"00002cb4",
+2865 => x"00002cbc",
+2866 => x"00002cbc",
+2867 => x"00002cc4",
+2868 => x"00002cc4",
+2869 => x"00002ccc",
+2870 => x"00002ccc",
+2871 => x"00002cd4",
+2872 => x"00002cd4",
+2873 => x"00002cdc",
+2874 => x"00002cdc",
+2875 => x"00002ce4",
+2876 => x"00002ce4",
+2877 => x"00002cec",
+2878 => x"00002cec",
+2879 => x"00002cf4",
+2880 => x"00002cf4",
+2881 => x"00002cfc",
+2882 => x"00002cfc",
+2883 => x"00002d04",
+2884 => x"00002d04",
+2885 => x"00002d0c",
+2886 => x"00002d0c",
+2887 => x"00002d14",
+2888 => x"00002d14",
+2889 => x"00002d1c",
+2890 => x"00002d1c",
+2891 => x"00002d24",
+2892 => x"00002d24",
+2893 => x"00002d2c",
+2894 => x"00002d2c",
+2895 => x"00002d34",
+2896 => x"00002d34",
+2897 => x"00002d3c",
+2898 => x"00002d3c",
+2899 => x"00002d44",
+2900 => x"00002d44",
+2901 => x"00002d4c",
+2902 => x"00002d4c",
+2903 => x"00002d54",
+2904 => x"00002d54",
+2905 => x"00002d5c",
+2906 => x"00002d5c",
+2907 => x"00002d64",
+2908 => x"00002d64",
+2909 => x"00002d6c",
+2910 => x"00002d6c",
+2911 => x"00002d74",
+2912 => x"00002d74",
+2913 => x"00002d7c",
+2914 => x"00002d7c",
+2915 => x"00002d84",
+2916 => x"00002d84",
+2917 => x"00002d8c",
+2918 => x"00002d8c",
+2919 => x"00002d94",
+2920 => x"00002d94",
+2921 => x"00002d9c",
+2922 => x"00002d9c",
+2923 => x"00002da4",
+2924 => x"00002da4",
+2925 => x"00002dac",
+2926 => x"00002dac",
+2927 => x"00002db4",
+2928 => x"00002db4",
+2929 => x"00002dbc",
+2930 => x"00002dbc",
+2931 => x"00002dc4",
+2932 => x"00002dc4",
+2933 => x"00002dcc",
+2934 => x"00002dcc",
+2935 => x"00002dd4",
+2936 => x"00002dd4",
+2937 => x"00002ddc",
+2938 => x"00002ddc",
+2939 => x"00002de4",
+2940 => x"00002de4",
+2941 => x"00002dec",
+2942 => x"00002dec",
+2943 => x"00002df4",
+2944 => x"00002df4",
+2945 => x"00002dfc",
+2946 => x"00002dfc",
+2947 => x"00002e04",
+2948 => x"00002e04",
+2949 => x"00002e0c",
+2950 => x"00002e0c",
+2951 => x"00002e14",
+2952 => x"00002e14",
+2953 => x"00002e1c",
+2954 => x"00002e1c",
+2955 => x"00002e24",
+2956 => x"00002e24",
+2957 => x"00002e2c",
+2958 => x"00002e2c",
+2959 => x"00002e34",
+2960 => x"00002e34",
+2961 => x"00002e3c",
+2962 => x"00002e3c",
+2963 => x"00002e44",
+2964 => x"00002e44",
+2965 => x"00002e4c",
+2966 => x"00002e4c",
+2967 => x"00002e54",
+2968 => x"00002e54",
+2969 => x"00002e5c",
+2970 => x"00002e5c",
+2971 => x"00002e64",
+2972 => x"00002e64",
+2973 => x"00002e6c",
+2974 => x"00002e6c",
+2975 => x"00002e74",
+2976 => x"00002e74",
+2977 => x"00002e7c",
+2978 => x"00002e7c",
+2979 => x"00002e84",
+2980 => x"00002e84",
+2981 => x"00002e8c",
+2982 => x"00002e8c",
+2983 => x"00002e94",
+2984 => x"00002e94",
+2985 => x"00002e9c",
+2986 => x"00002e9c",
+2987 => x"00002ea4",
+2988 => x"00002ea4",
+2989 => x"00002eac",
+2990 => x"00002eac",
+2991 => x"00002eb4",
+2992 => x"00002eb4",
+2993 => x"00002ebc",
+2994 => x"00002ebc",
+2995 => x"00002ec4",
+2996 => x"00002ec4",
+2997 => x"00002ecc",
+2998 => x"00002ecc",
+2999 => x"00002ed4",
+3000 => x"00002ed4",
+3001 => x"00002edc",
+3002 => x"00002edc",
+3003 => x"00002ee4",
+3004 => x"00002ee4",
+3005 => x"00002eec",
+3006 => x"00002eec",
+3007 => x"00002ef4",
+3008 => x"00002ef4",
+3009 => x"00002efc",
+3010 => x"00002efc",
+3011 => x"00002f04",
+3012 => x"00002f04",
+3013 => x"00002f0c",
+3014 => x"00002f0c",
+3015 => x"00002f14",
+3016 => x"00002f14",
+3017 => x"00002f1c",
+3018 => x"00002f1c",
+3019 => x"00002f24",
+3020 => x"00002f24",
+3021 => x"00002f2c",
+3022 => x"00002f2c",
+3023 => x"00002f34",
+3024 => x"00002f34",
+3025 => x"00002f3c",
+3026 => x"00002f3c",
+3027 => x"00002f50",
+3028 => x"00000000",
+3029 => x"000031b8",
+3030 => x"00003214",
+3031 => x"00003270",
+3032 => x"00000000",
+3033 => x"00000000",
+3034 => x"00000000",
+3035 => x"00000000",
+3036 => x"00000000",
+3037 => x"00000000",
+3038 => x"00000000",
+3039 => x"00000000",
+3040 => x"00000000",
+3041 => x"00002ad0",
+3042 => x"00000000",
+3043 => x"00000000",
+3044 => x"00000000",
+3045 => x"00000000",
+3046 => x"00000000",
+3047 => x"00000000",
+3048 => x"00000000",
+3049 => x"00000000",
+3050 => x"00000000",
+3051 => x"00000000",
+3052 => x"00000000",
+3053 => x"00000000",
+3054 => x"00000000",
+3055 => x"00000000",
+3056 => x"00000000",
+3057 => x"00000000",
+3058 => x"00000000",
+3059 => x"00000000",
+3060 => x"00000000",
+3061 => x"00000000",
+3062 => x"00000000",
+3063 => x"00000000",
+3064 => x"00000000",
+3065 => x"00000000",
+3066 => x"00000000",
+3067 => x"00000000",
+3068 => x"00000000",
+3069 => x"00000000",
+3070 => x"00000001",
+3071 => x"330eabcd",
+3072 => x"1234e66d",
+3073 => x"deec0005",
+3074 => x"000b0000",
+3075 => x"00000000",
+3076 => x"00000000",
+3077 => x"00000000",
+3078 => x"00000000",
+3079 => x"00000000",
+3080 => x"00000000",
+3081 => x"00000000",
+3082 => x"00000000",
+3083 => x"00000000",
+3084 => x"00000000",
+3085 => x"00000000",
+3086 => x"00000000",
+3087 => x"00000000",
+3088 => x"00000000",
+3089 => x"00000000",
+3090 => x"00000000",
+3091 => x"00000000",
+3092 => x"00000000",
+3093 => x"00000000",
+3094 => x"00000000",
+3095 => x"00000000",
+3096 => x"00000000",
+3097 => x"00000000",
+3098 => x"00000000",
+3099 => x"00000000",
+3100 => x"00000000",
+3101 => x"00000000",
+3102 => x"00000000",
+3103 => x"00000000",
+3104 => x"00000000",
+3105 => x"00000000",
+3106 => x"00000000",
+3107 => x"00000000",
+3108 => x"00000000",
+3109 => x"00000000",
+3110 => x"00000000",
+3111 => x"00000000",
+3112 => x"00000000",
+3113 => x"00000000",
+3114 => x"00000000",
+3115 => x"00000000",
+3116 => x"00000000",
+3117 => x"00000000",
+3118 => x"00000000",
+3119 => x"00000000",
+3120 => x"00000000",
+3121 => x"00000000",
+3122 => x"00000000",
+3123 => x"00000000",
+3124 => x"00000000",
+3125 => x"00000000",
+3126 => x"00000000",
+3127 => x"00000000",
+3128 => x"00000000",
+3129 => x"00000000",
+3130 => x"00000000",
+3131 => x"00000000",
+3132 => x"00000000",
+3133 => x"00000000",
+3134 => x"00000000",
+3135 => x"00000000",
+3136 => x"00000000",
+3137 => x"00000000",
+3138 => x"00000000",
+3139 => x"00000000",
+3140 => x"00000000",
+3141 => x"00000000",
+3142 => x"00000000",
+3143 => x"00000000",
+3144 => x"00000000",
+3145 => x"00000000",
+3146 => x"00000000",
+3147 => x"00000000",
+3148 => x"00000000",
+3149 => x"00000000",
+3150 => x"00000000",
+3151 => x"00000000",
+3152 => x"00000000",
+3153 => x"00000000",
+3154 => x"00000000",
+3155 => x"00000000",
+3156 => x"00000000",
+3157 => x"00000000",
+3158 => x"00000000",
+3159 => x"00000000",
+3160 => x"00000000",
+3161 => x"00000000",
+3162 => x"00000000",
+3163 => x"00000000",
+3164 => x"00000000",
+3165 => x"00000000",
+3166 => x"00000000",
+3167 => x"00000000",
+3168 => x"00000000",
+3169 => x"00000000",
+3170 => x"00000000",
+3171 => x"00000000",
+3172 => x"00000000",
+3173 => x"00000000",
+3174 => x"00000000",
+3175 => x"00000000",
+3176 => x"00000000",
+3177 => x"00000000",
+3178 => x"00000000",
+3179 => x"00000000",
+3180 => x"00000000",
+3181 => x"00000000",
+3182 => x"00000000",
+3183 => x"00000000",
+3184 => x"00000000",
+3185 => x"00000000",
+3186 => x"00000000",
+3187 => x"00000000",
+3188 => x"00000000",
+3189 => x"00000000",
+3190 => x"00000000",
+3191 => x"00000000",
+3192 => x"00000000",
+3193 => x"00000000",
+3194 => x"00000000",
+3195 => x"00000000",
+3196 => x"00000000",
+3197 => x"00000000",
+3198 => x"00000000",
+3199 => x"00000000",
+3200 => x"00000000",
+3201 => x"00000000",
+3202 => x"00000000",
+3203 => x"00000000",
+3204 => x"00000000",
+3205 => x"00000000",
+3206 => x"00000000",
+3207 => x"00000000",
+3208 => x"00000000",
+3209 => x"00000000",
+3210 => x"00000000",
+3211 => x"00000000",
+3212 => x"00000000",
+3213 => x"00000000",
+3214 => x"00000000",
+3215 => x"00000000",
+3216 => x"00000000",
+3217 => x"00000000",
+3218 => x"00000000",
+3219 => x"00000000",
+3220 => x"00000000",
+3221 => x"00000000",
+3222 => x"00000000",
+3223 => x"00000000",
+3224 => x"00000000",
+3225 => x"00000000",
+3226 => x"00000000",
+3227 => x"00000000",
+3228 => x"00000000",
+3229 => x"00000000",
+3230 => x"00000000",
+3231 => x"00000000",
+3232 => x"00000000",
+3233 => x"00000000",
+3234 => x"00000000",
+3235 => x"00000000",
+3236 => x"00000000",
+3237 => x"00000000",
+3238 => x"00000000",
+3239 => x"00000000",
+3240 => x"00000000",
+3241 => x"00000000",
+3242 => x"00000000",
+3243 => x"00000000",
+3244 => x"00000000",
+3245 => x"00000000",
+3246 => x"00000000",
+3247 => x"00000000",
+3248 => x"00000000",
+3249 => x"00000000",
+3250 => x"00000000",
+3251 => x"00002ad4",
+3252 => x"ffffffff",
+3253 => x"00000000",
+3254 => x"ffffffff",
+3255 => x"00000000",
diff --git a/zpu/hdl/zpu4/test/gpiotest/build.sh b/zpu/hdl/zpu4/test/gpiotest/build.sh
new file mode 100755
index 0000000..c0385ad
--- /dev/null
+++ b/zpu/hdl/zpu4/test/gpiotest/build.sh
@@ -0,0 +1,4 @@
+zpu-elf-gcc -O3 -phi `pwd`/gpiotest.c -o gpiotest.elf -Wl,--relax -Wl,--gc-sections -g
+zpu-elf-objdump --disassemble-all >gpiotest.dis gpiotest.elf
+zpu-elf-objcopy -O binary gpiotest.elf gpiotest.bin
+java -classpath ../../../../sw/simulator/zpusim.jar com.zylin.zpu.simulator.tools.MakeRam gpiotest.bin >gpiotest.ram
diff --git a/zpu/hdl/zpu4/test/gpiotest/gpiotest.c b/zpu/hdl/zpu4/test/gpiotest/gpiotest.c
new file mode 100644
index 0000000..393ab9f
--- /dev/null
+++ b/zpu/hdl/zpu4/test/gpiotest/gpiotest.c
@@ -0,0 +1,72 @@
+/*
+ * Small test program to check GPIOs
+ *
+ * LED chaser until keypress
+ *
+ */
+
+// addresses refer to Phi memory layout
+#define GPIO_DATA *((volatile unsigned int *) 0x080a0004)
+#define GPIO_DIR *((volatile unsigned int *) 0x080a0008)
+
+
+#define BUTTON_EAST (3)
+#define BUTTON_NORTH (2)
+#define BUTTON_SOUTH (1)
+#define BUTTON_WEST (0)
+
+
+#define bit_is_set(var, bit) ((var) & (1 << (bit)))
+#define bit_is_clear(var, bit) ((!(var)) & (1 << (bit)))
+#define loop_until_bit_is_set(var, bit) do { } while (bit_is_clear(var, bit))
+#define loop_until_bit_is_clear(var, bit) do { } while (bit_is_set(var, bit))
+
+
+void led_test( void)
+{
+ unsigned char runs;
+ unsigned char leds;
+
+ runs = 1;
+ leds = 0x01;
+
+ while( runs)
+ {
+ // output
+ GPIO_DATA = leds;
+
+ // read button status
+ if bit_is_set(GPIO_DATA, BUTTON_NORTH)
+ {
+ runs = 0;
+ }
+
+ // LED chaser
+ leds = leds << 1;
+ if (leds == 0)
+ {
+ leds = 0x01;
+ }
+ }
+}
+
+
+void header_test( void)
+{
+ // this test is special for the SP601 header connector
+ // check the output in simulation
+ GPIO_DATA = 0x00550000;
+ GPIO_DIR = 0xff00ffff;
+ GPIO_DATA = 0x00aa0000;
+ GPIO_DIR = 0xffffffff;
+}
+
+
+int main(int argc, char **argv)
+{
+
+ led_test();
+ header_test();
+
+ abort();
+}
diff --git a/zpu/hdl/zpu4/test/hello/build.sh b/zpu/hdl/zpu4/test/hello/build.sh
new file mode 100755
index 0000000..dd87410
--- /dev/null
+++ b/zpu/hdl/zpu4/test/hello/build.sh
@@ -0,0 +1,4 @@
+zpu-elf-gcc -O3 -phi `pwd`/hello.c -o hello.elf -Wl,--relax -Wl,--gc-sections -g
+zpu-elf-objdump --disassemble-all >hello.dis hello.elf
+zpu-elf-objcopy -O binary hello.elf hello.bin
+java -classpath ../../../../sw/simulator/zpusim.jar com.zylin.zpu.simulator.tools.MakeRam hello.bin >hello.ram
diff --git a/zpu/hdl/zpu4/test/hello/hello.bin b/zpu/hdl/zpu4/test/hello/hello.bin
new file mode 100644
index 0000000..7c37759
--- /dev/null
+++ b/zpu/hdl/zpu4/test/hello/hello.bin
Binary files differ
diff --git a/zpu/hdl/zpu4/test/hello/hello.c b/zpu/hdl/zpu4/test/hello/hello.c
new file mode 100644
index 0000000..609c163
--- /dev/null
+++ b/zpu/hdl/zpu4/test/hello/hello.c
@@ -0,0 +1,47 @@
+/*
+ * Small hello world example, does not use printf()
+ */
+#include <stdio.h>
+
+int j;
+int k;
+
+int main(int argc, char **argv)
+{
+ int i;
+ for (i=0; i< 10; i++)
+ {
+ puts("Hello world 1\n");
+ puts("Hello world 2\n");
+ j=-4;
+ if ((j>>1)!=-2)
+ {
+ abort();
+ }
+
+ k=10;
+ if (k*j!=-40)
+ {
+ abort();
+ }
+
+ j=10;
+ k=10000000;
+ if (k*j!=100000000)
+ {
+ abort();
+ }
+
+ j=0x80000000;
+ k=0xffffffff;
+ if (j>k)
+ {
+ abort();
+ }
+ }
+ if (i!=10)
+ {
+ abort();
+ }
+
+}
diff --git a/zpu/hdl/zpu4/test/hello/hello.elf b/zpu/hdl/zpu4/test/hello/hello.elf
new file mode 100644
index 0000000..73d28e7
--- /dev/null
+++ b/zpu/hdl/zpu4/test/hello/hello.elf
Binary files differ
diff --git a/zpu/hdl/zpu4/test/hello/hello.ram b/zpu/hdl/zpu4/test/hello/hello.ram
new file mode 100644
index 0000000..175d3a8
--- /dev/null
+++ b/zpu/hdl/zpu4/test/hello/hello.ram
@@ -0,0 +1,3055 @@
+0 => x"0b0b0b0b",
+1 => x"82700b0b",
+2 => x"80cfd80c",
+3 => x"3a0b0b80",
+4 => x"c6d00400",
+5 => x"00000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"80c7972d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
+17 => x"72830609",
+18 => x"81058205",
+19 => x"832b2a83",
+20 => x"ffff0652",
+21 => x"04000000",
+22 => x"00000000",
+23 => x"00000000",
+24 => x"71fd0608",
+25 => x"83ffff73",
+26 => x"83060981",
+27 => x"05820583",
+28 => x"2b2b0906",
+29 => x"7383ffff",
+30 => x"0b0b0b0b",
+31 => x"83a70400",
+32 => x"72098105",
+33 => x"72057373",
+34 => x"09060906",
+35 => x"73097306",
+36 => x"070a8106",
+37 => x"53510400",
+38 => x"00000000",
+39 => x"00000000",
+40 => x"72722473",
+41 => x"732e0753",
+42 => x"51040000",
+43 => x"00000000",
+44 => x"00000000",
+45 => x"00000000",
+46 => x"00000000",
+47 => x"00000000",
+48 => x"71737109",
+49 => x"71068106",
+50 => x"30720a10",
+51 => x"0a720a10",
+52 => x"0a31050a",
+53 => x"81065151",
+54 => x"53510400",
+55 => x"00000000",
+56 => x"72722673",
+57 => x"732e0753",
+58 => x"51040000",
+59 => x"00000000",
+60 => x"00000000",
+61 => x"00000000",
+62 => x"00000000",
+63 => x"00000000",
+64 => x"00000000",
+65 => x"00000000",
+66 => x"00000000",
+67 => x"00000000",
+68 => x"00000000",
+69 => x"00000000",
+70 => x"00000000",
+71 => x"00000000",
+72 => x"0b0b0b88",
+73 => x"c4040000",
+74 => x"00000000",
+75 => x"00000000",
+76 => x"00000000",
+77 => x"00000000",
+78 => x"00000000",
+79 => x"00000000",
+80 => x"720a722b",
+81 => x"0a535104",
+82 => x"00000000",
+83 => x"00000000",
+84 => x"00000000",
+85 => x"00000000",
+86 => x"00000000",
+87 => x"00000000",
+88 => x"72729f06",
+89 => x"0981050b",
+90 => x"0b0b88a7",
+91 => x"05040000",
+92 => x"00000000",
+93 => x"00000000",
+94 => x"00000000",
+95 => x"00000000",
+96 => x"72722aff",
+97 => x"739f062a",
+98 => x"0974090a",
+99 => x"8106ff05",
+100 => x"06075351",
+101 => x"04000000",
+102 => x"00000000",
+103 => x"00000000",
+104 => x"71715351",
+105 => x"020d0406",
+106 => x"73830609",
+107 => x"81058205",
+108 => x"832b0b2b",
+109 => x"0772fc06",
+110 => x"0c515104",
+111 => x"00000000",
+112 => x"72098105",
+113 => x"72050970",
+114 => x"81050906",
+115 => x"0a810653",
+116 => x"51040000",
+117 => x"00000000",
+118 => x"00000000",
+119 => x"00000000",
+120 => x"72098105",
+121 => x"72050970",
+122 => x"81050906",
+123 => x"0a098106",
+124 => x"53510400",
+125 => x"00000000",
+126 => x"00000000",
+127 => x"00000000",
+128 => x"71098105",
+129 => x"52040000",
+130 => x"00000000",
+131 => x"00000000",
+132 => x"00000000",
+133 => x"00000000",
+134 => x"00000000",
+135 => x"00000000",
+136 => x"72720981",
+137 => x"05055351",
+138 => x"04000000",
+139 => x"00000000",
+140 => x"00000000",
+141 => x"00000000",
+142 => x"00000000",
+143 => x"00000000",
+144 => x"72097206",
+145 => x"73730906",
+146 => x"07535104",
+147 => x"00000000",
+148 => x"00000000",
+149 => x"00000000",
+150 => x"00000000",
+151 => x"00000000",
+152 => x"71fc0608",
+153 => x"72830609",
+154 => x"81058305",
+155 => x"1010102a",
+156 => x"81ff0652",
+157 => x"04000000",
+158 => x"00000000",
+159 => x"00000000",
+160 => x"71fc0608",
+161 => x"0b0b80cf",
+162 => x"c4738306",
+163 => x"10100508",
+164 => x"060b0b0b",
+165 => x"88aa0400",
+166 => x"00000000",
+167 => x"00000000",
+168 => x"80088408",
+169 => x"88087575",
+170 => x"0b0b0b8b",
+171 => x"9f2d5050",
+172 => x"80085688",
+173 => x"0c840c80",
+174 => x"0c510400",
+175 => x"00000000",
+176 => x"80088408",
+177 => x"88087575",
+178 => x"0b0b0b8b",
+179 => x"e32d5050",
+180 => x"80085688",
+181 => x"0c840c80",
+182 => x"0c510400",
+183 => x"00000000",
+184 => x"72097081",
+185 => x"0509060a",
+186 => x"8106ff05",
+187 => x"70547106",
+188 => x"73097274",
+189 => x"05ff0506",
+190 => x"07515151",
+191 => x"04000000",
+192 => x"72097081",
+193 => x"0509060a",
+194 => x"098106ff",
+195 => x"05705471",
+196 => x"06730972",
+197 => x"7405ff05",
+198 => x"06075151",
+199 => x"51040000",
+200 => x"05ff0504",
+201 => x"00000000",
+202 => x"00000000",
+203 => x"00000000",
+204 => x"00000000",
+205 => x"00000000",
+206 => x"00000000",
+207 => x"00000000",
+208 => x"810b0b0b",
+209 => x"80cfd40c",
+210 => x"51040000",
+211 => x"00000000",
+212 => x"00000000",
+213 => x"00000000",
+214 => x"00000000",
+215 => x"00000000",
+216 => x"71810552",
+217 => x"04000000",
+218 => x"00000000",
+219 => x"00000000",
+220 => x"00000000",
+221 => x"00000000",
+222 => x"00000000",
+223 => x"00000000",
+224 => x"00000000",
+225 => x"00000000",
+226 => x"00000000",
+227 => x"00000000",
+228 => x"00000000",
+229 => x"00000000",
+230 => x"00000000",
+231 => x"00000000",
+232 => x"02840572",
+233 => x"10100552",
+234 => x"04000000",
+235 => x"00000000",
+236 => x"00000000",
+237 => x"00000000",
+238 => x"00000000",
+239 => x"00000000",
+240 => x"00000000",
+241 => x"00000000",
+242 => x"00000000",
+243 => x"00000000",
+244 => x"00000000",
+245 => x"00000000",
+246 => x"00000000",
+247 => x"00000000",
+248 => x"717105ff",
+249 => x"05715351",
+250 => x"020d0400",
+251 => x"00000000",
+252 => x"00000000",
+253 => x"00000000",
+254 => x"00000000",
+255 => x"00000000",
+256 => x"82c53f80",
+257 => x"c6d93f04",
+258 => x"10101010",
+259 => x"10101010",
+260 => x"10101010",
+261 => x"10101010",
+262 => x"10101010",
+263 => x"10101010",
+264 => x"10101010",
+265 => x"10101053",
+266 => x"51047381",
+267 => x"ff067383",
+268 => x"06098105",
+269 => x"83051010",
+270 => x"102b0772",
+271 => x"fc060c51",
+272 => x"51043c04",
+273 => x"72728072",
+274 => x"8106ff05",
+275 => x"09720605",
+276 => x"71105272",
+277 => x"0a100a53",
+278 => x"72ed3851",
+279 => x"51535104",
+280 => x"fe3d0d0b",
+281 => x"0b80dfc0",
+282 => x"08538413",
+283 => x"0870882a",
+284 => x"70810651",
+285 => x"52527080",
+286 => x"2ef03871",
+287 => x"81ff0680",
+288 => x"0c843d0d",
+289 => x"04ff3d0d",
+290 => x"0b0b80df",
+291 => x"c0085271",
+292 => x"0870882a",
+293 => x"81327081",
+294 => x"06515151",
+295 => x"70f13873",
+296 => x"720c833d",
+297 => x"0d0480cf",
+298 => x"d408802e",
+299 => x"a43880cf",
+300 => x"d808822e",
+301 => x"bd388380",
+302 => x"800b0b0b",
+303 => x"80dfc00c",
+304 => x"82a0800b",
+305 => x"80dfc40c",
+306 => x"8290800b",
+307 => x"80dfc80c",
+308 => x"04f88080",
+309 => x"80a40b0b",
+310 => x"0b80dfc0",
+311 => x"0cf88080",
+312 => x"82800b80",
+313 => x"dfc40cf8",
+314 => x"80808480",
+315 => x"0b80dfc8",
+316 => x"0c0480c0",
+317 => x"a8808c0b",
+318 => x"0b0b80df",
+319 => x"c00c80c0",
+320 => x"a880940b",
+321 => x"80dfc40c",
+322 => x"0b0b80cf",
+323 => x"8c0b80df",
+324 => x"c80c0470",
+325 => x"7080dfcc",
+326 => x"335170a7",
+327 => x"3880cfe0",
+328 => x"08700852",
+329 => x"5270802e",
+330 => x"94388412",
+331 => x"80cfe00c",
+332 => x"702d80cf",
+333 => x"e0087008",
+334 => x"525270ee",
+335 => x"38810b80",
+336 => x"dfcc3450",
+337 => x"50040470",
+338 => x"0b0b80df",
+339 => x"bc08802e",
+340 => x"8e380b0b",
+341 => x"0b0b800b",
+342 => x"802e0981",
+343 => x"06833850",
+344 => x"040b0b80",
+345 => x"dfbc510b",
+346 => x"0b0bf594",
+347 => x"3f500404",
+348 => x"fe3d0d89",
+349 => x"5380cf90",
+350 => x"5182c13f",
+351 => x"80cfa051",
+352 => x"82ba3f81",
+353 => x"0a0b80df",
+354 => x"d80cff0b",
+355 => x"80dfdc0c",
+356 => x"ff135372",
+357 => x"8025de38",
+358 => x"72800c84",
+359 => x"3d0d04fb",
+360 => x"3d0d7779",
+361 => x"55558056",
+362 => x"757524ab",
+363 => x"38807424",
+364 => x"9d388053",
+365 => x"73527451",
+366 => x"80e13f80",
+367 => x"08547580",
+368 => x"2e853880",
+369 => x"08305473",
+370 => x"800c873d",
+371 => x"0d047330",
+372 => x"76813257",
+373 => x"54dc3974",
+374 => x"30558156",
+375 => x"738025d2",
+376 => x"38ec39fa",
+377 => x"3d0d787a",
+378 => x"57558057",
+379 => x"767524a4",
+380 => x"38759f2c",
+381 => x"54815375",
+382 => x"74327431",
+383 => x"5274519b",
+384 => x"3f800854",
+385 => x"76802e85",
+386 => x"38800830",
+387 => x"5473800c",
+388 => x"883d0d04",
+389 => x"74305581",
+390 => x"57d739fc",
+391 => x"3d0d7678",
+392 => x"53548153",
+393 => x"80747326",
+394 => x"52557280",
+395 => x"2e983870",
+396 => x"802eab38",
+397 => x"807224a6",
+398 => x"38711073",
+399 => x"10757226",
+400 => x"53545272",
+401 => x"ea387351",
+402 => x"78833874",
+403 => x"5170800c",
+404 => x"863d0d04",
+405 => x"720a100a",
+406 => x"720a100a",
+407 => x"53537280",
+408 => x"2ee43871",
+409 => x"7426ed38",
+410 => x"73723175",
+411 => x"7407740a",
+412 => x"100a740a",
+413 => x"100a5555",
+414 => x"5654e339",
+415 => x"f73d0d7c",
+416 => x"70525380",
+417 => x"f93f7254",
+418 => x"80085580",
+419 => x"cfb05681",
+420 => x"57800881",
+421 => x"055a8b3d",
+422 => x"e4115953",
+423 => x"8259f413",
+424 => x"527b8811",
+425 => x"08525381",
+426 => x"b23f8008",
+427 => x"30708008",
+428 => x"079f2c8a",
+429 => x"07800c53",
+430 => x"8b3d0d04",
+431 => x"f63d0d7c",
+432 => x"80cfe408",
+433 => x"71535553",
+434 => x"b53f7255",
+435 => x"80085680",
+436 => x"cfb05781",
+437 => x"58800881",
+438 => x"055b8c3d",
+439 => x"e4115a53",
+440 => x"825af413",
+441 => x"52881408",
+442 => x"5180f03f",
+443 => x"80083070",
+444 => x"8008079f",
+445 => x"2c8a0780",
+446 => x"0c548c3d",
+447 => x"0d047070",
+448 => x"70707570",
+449 => x"71830653",
+450 => x"555270b4",
+451 => x"38717008",
+452 => x"7009f7fb",
+453 => x"fdff1206",
+454 => x"f8848281",
+455 => x"80065452",
+456 => x"53719b38",
+457 => x"84137008",
+458 => x"7009f7fb",
+459 => x"fdff1206",
+460 => x"f8848281",
+461 => x"80065452",
+462 => x"5371802e",
+463 => x"e7387252",
+464 => x"71335372",
+465 => x"802e8a38",
+466 => x"81127033",
+467 => x"545272f8",
+468 => x"38717431",
+469 => x"800c5050",
+470 => x"505004f2",
+471 => x"3d0d6062",
+472 => x"88110870",
+473 => x"58565f5a",
+474 => x"73802e81",
+475 => x"8c388c1a",
+476 => x"2270832a",
+477 => x"81328106",
+478 => x"56587486",
+479 => x"38901a08",
+480 => x"91387951",
+481 => x"90b73fff",
+482 => x"55800880",
+483 => x"ec388c1a",
+484 => x"22587d08",
+485 => x"55807883",
+486 => x"ffff0670",
+487 => x"0a100a81",
+488 => x"06415c57",
+489 => x"7e772e80",
+490 => x"d7387690",
+491 => x"38740884",
+492 => x"16088817",
+493 => x"57585676",
+494 => x"802ef238",
+495 => x"76548880",
+496 => x"77278438",
+497 => x"88805473",
+498 => x"5375529c",
+499 => x"1a0851a4",
+500 => x"1a085877",
+501 => x"2d800b80",
+502 => x"082582e0",
+503 => x"38800816",
+504 => x"77800831",
+505 => x"7f880508",
+506 => x"80083170",
+507 => x"6188050c",
+508 => x"5b585678",
+509 => x"ffb43880",
+510 => x"5574800c",
+511 => x"903d0d04",
+512 => x"7a813281",
+513 => x"06774056",
+514 => x"75802e81",
+515 => x"bd387690",
+516 => x"38740884",
+517 => x"16088817",
+518 => x"57585976",
+519 => x"802ef238",
+520 => x"881a0878",
+521 => x"83ffff06",
+522 => x"70892a81",
+523 => x"06565956",
+524 => x"73802e82",
+525 => x"f8387577",
+526 => x"278b3877",
+527 => x"872a8106",
+528 => x"5c7b82b5",
+529 => x"38767627",
+530 => x"83387656",
+531 => x"75537852",
+532 => x"79085185",
+533 => x"833f881a",
+534 => x"08763188",
+535 => x"1b0c7908",
+536 => x"167a0c76",
+537 => x"56751977",
+538 => x"77317f88",
+539 => x"05087831",
+540 => x"70618805",
+541 => x"0c415859",
+542 => x"7e802efe",
+543 => x"fa388c1a",
+544 => x"2258ff8a",
+545 => x"39787954",
+546 => x"7c537b52",
+547 => x"5684c93f",
+548 => x"881a0879",
+549 => x"31881b0c",
+550 => x"7908197a",
+551 => x"0c7c7631",
+552 => x"5d7c8e38",
+553 => x"79518ff2",
+554 => x"3f800881",
+555 => x"8f388008",
+556 => x"5f751c77",
+557 => x"77317f88",
+558 => x"05087831",
+559 => x"70618805",
+560 => x"0c5d585c",
+561 => x"7a802efe",
+562 => x"ae387681",
+563 => x"83387408",
+564 => x"84160888",
+565 => x"1757585c",
+566 => x"76802ef2",
+567 => x"3876538a",
+568 => x"527b5182",
+569 => x"d33f8008",
+570 => x"7c318105",
+571 => x"5d800884",
+572 => x"3881175d",
+573 => x"815f7c59",
+574 => x"767d2783",
+575 => x"38765994",
+576 => x"1a08881b",
+577 => x"08115758",
+578 => x"807a085c",
+579 => x"54901a08",
+580 => x"7b278338",
+581 => x"81547579",
+582 => x"25843873",
+583 => x"ba387779",
+584 => x"24fee238",
+585 => x"77537b52",
+586 => x"9c1a0851",
+587 => x"a41a0859",
+588 => x"782d8008",
+589 => x"56800880",
+590 => x"24fee238",
+591 => x"8c1a2280",
+592 => x"c0075e7d",
+593 => x"8c1b23ff",
+594 => x"5574800c",
+595 => x"903d0d04",
+596 => x"7effa338",
+597 => x"ff873975",
+598 => x"537b527a",
+599 => x"5182f93f",
+600 => x"7908167a",
+601 => x"0c79518e",
+602 => x"b13f8008",
+603 => x"cf387c76",
+604 => x"315d7cfe",
+605 => x"bc38feac",
+606 => x"39901a08",
+607 => x"7a087131",
+608 => x"78117056",
+609 => x"5a575280",
+610 => x"cfe40851",
+611 => x"84943f80",
+612 => x"08802eff",
+613 => x"a7388008",
+614 => x"901b0c80",
+615 => x"08167a0c",
+616 => x"77941b0c",
+617 => x"76881b0c",
+618 => x"7656fd99",
+619 => x"39790858",
+620 => x"901a0878",
+621 => x"27833881",
+622 => x"54757727",
+623 => x"843873b3",
+624 => x"38941a08",
+625 => x"54737726",
+626 => x"80d33873",
+627 => x"5378529c",
+628 => x"1a0851a4",
+629 => x"1a085877",
+630 => x"2d800856",
+631 => x"80088024",
+632 => x"fd83388c",
+633 => x"1a2280c0",
+634 => x"075e7d8c",
+635 => x"1b23ff55",
+636 => x"fed73975",
+637 => x"53785277",
+638 => x"5181dd3f",
+639 => x"7908167a",
+640 => x"0c79518d",
+641 => x"953f8008",
+642 => x"802efcd9",
+643 => x"388c1a22",
+644 => x"80c0075e",
+645 => x"7d8c1b23",
+646 => x"ff55fead",
+647 => x"39767754",
+648 => x"79537852",
+649 => x"5681b13f",
+650 => x"881a0877",
+651 => x"31881b0c",
+652 => x"7908177a",
+653 => x"0cfcae39",
+654 => x"fa3d0d7a",
+655 => x"79028805",
+656 => x"a7053355",
+657 => x"53548374",
+658 => x"2780df38",
+659 => x"71830651",
+660 => x"7080d738",
+661 => x"71715755",
+662 => x"83517582",
+663 => x"802913ff",
+664 => x"12525670",
+665 => x"8025f338",
+666 => x"837427bc",
+667 => x"38740876",
+668 => x"327009f7",
+669 => x"fbfdff12",
+670 => x"06f88482",
+671 => x"81800651",
+672 => x"5170802e",
+673 => x"98387451",
+674 => x"80527033",
+675 => x"5772772e",
+676 => x"b9388111",
+677 => x"81135351",
+678 => x"837227ee",
+679 => x"38fc1484",
+680 => x"16565473",
+681 => x"8326c638",
+682 => x"7452ff14",
+683 => x"5170ff2e",
+684 => x"97387133",
+685 => x"5472742e",
+686 => x"98388112",
+687 => x"ff125252",
+688 => x"70ff2e09",
+689 => x"8106eb38",
+690 => x"80517080",
+691 => x"0c883d0d",
+692 => x"0471800c",
+693 => x"883d0d04",
+694 => x"fa3d0d78",
+695 => x"7a7c7272",
+696 => x"72595755",
+697 => x"58565774",
+698 => x"7727b238",
+699 => x"75155176",
+700 => x"7127aa38",
+701 => x"707618ff",
+702 => x"18535353",
+703 => x"70ff2e96",
+704 => x"38ff12ff",
+705 => x"14545272",
+706 => x"337234ff",
+707 => x"115170ff",
+708 => x"2e098106",
+709 => x"ec387680",
+710 => x"0c883d0d",
+711 => x"048f7627",
+712 => x"80e63874",
+713 => x"77078306",
+714 => x"517080dc",
+715 => x"38767552",
+716 => x"53707084",
+717 => x"05520873",
+718 => x"70840555",
+719 => x"0c727170",
+720 => x"84055308",
+721 => x"71708405",
+722 => x"530c7170",
+723 => x"84055308",
+724 => x"71708405",
+725 => x"530c7170",
+726 => x"84055308",
+727 => x"71708405",
+728 => x"530cf015",
+729 => x"5553738f",
+730 => x"26c73883",
+731 => x"74279538",
+732 => x"70708405",
+733 => x"52087370",
+734 => x"8405550c",
+735 => x"fc145473",
+736 => x"8326ed38",
+737 => x"72715452",
+738 => x"ff145170",
+739 => x"ff2eff86",
+740 => x"38727081",
+741 => x"05543372",
+742 => x"70810554",
+743 => x"34ff1151",
+744 => x"ea39ef3d",
+745 => x"0d636567",
+746 => x"405d427b",
+747 => x"802e8582",
+748 => x"386151a9",
+749 => x"e73ff81c",
+750 => x"70841208",
+751 => x"70fc0670",
+752 => x"628b0570",
+753 => x"f8064159",
+754 => x"455c5f41",
+755 => x"57967427",
+756 => x"82c53880",
+757 => x"7b247e7c",
+758 => x"26075880",
+759 => x"5477742e",
+760 => x"09810682",
+761 => x"ab38787b",
+762 => x"2581fe38",
+763 => x"781780d7",
+764 => x"a00b8805",
+765 => x"085b5679",
+766 => x"762e84c5",
+767 => x"38841608",
+768 => x"70fe0617",
+769 => x"84110881",
+770 => x"06415555",
+771 => x"7e828d38",
+772 => x"74fc0658",
+773 => x"79762e84",
+774 => x"e3387818",
+775 => x"5f7e7b25",
+776 => x"81ff387c",
+777 => x"81065473",
+778 => x"82c13876",
+779 => x"77083184",
+780 => x"1108fc06",
+781 => x"56577580",
+782 => x"2e913879",
+783 => x"762e84f0",
+784 => x"38741819",
+785 => x"58777b25",
+786 => x"84913876",
+787 => x"802e829b",
+788 => x"38781556",
+789 => x"7a762482",
+790 => x"92388c17",
+791 => x"08881808",
+792 => x"718c120c",
+793 => x"88120c5e",
+794 => x"75598817",
+795 => x"61fc055b",
+796 => x"5679a426",
+797 => x"85ff387b",
+798 => x"76595593",
+799 => x"7a2780c9",
+800 => x"387b7084",
+801 => x"055d087c",
+802 => x"56760c74",
+803 => x"70840556",
+804 => x"088c180c",
+805 => x"9017589b",
+806 => x"7a27ae38",
+807 => x"74708405",
+808 => x"5608780c",
+809 => x"74708405",
+810 => x"56089418",
+811 => x"0c981758",
+812 => x"a37a2795",
+813 => x"38747084",
+814 => x"05560878",
+815 => x"0c747084",
+816 => x"0556089c",
+817 => x"180ca017",
+818 => x"58747084",
+819 => x"05560875",
+820 => x"5f787084",
+821 => x"055a0c77",
+822 => x"7e708405",
+823 => x"40087170",
+824 => x"8405530c",
+825 => x"7e08710c",
+826 => x"5d787b31",
+827 => x"56758f26",
+828 => x"80c93884",
+829 => x"17088106",
+830 => x"79078418",
+831 => x"0c781784",
+832 => x"11088107",
+833 => x"84120c5b",
+834 => x"6151a791",
+835 => x"3f881754",
+836 => x"73800c93",
+837 => x"3d0d0490",
+838 => x"5bfdb839",
+839 => x"7756fe83",
+840 => x"398c1608",
+841 => x"88170871",
+842 => x"8c120c88",
+843 => x"120c587e",
+844 => x"707c3157",
+845 => x"598f7627",
+846 => x"ffb9387a",
+847 => x"17841808",
+848 => x"81067c07",
+849 => x"84190c76",
+850 => x"81078412",
+851 => x"0c761184",
+852 => x"11088107",
+853 => x"84120c5b",
+854 => x"88055261",
+855 => x"518fda3f",
+856 => x"6151a6b9",
+857 => x"3f881754",
+858 => x"ffa6397d",
+859 => x"52615197",
+860 => x"d73f8008",
+861 => x"5a800880",
+862 => x"2e81ab38",
+863 => x"8008f805",
+864 => x"60840508",
+865 => x"fe066105",
+866 => x"58557477",
+867 => x"2e83f238",
+868 => x"fc195877",
+869 => x"a42681b0",
+870 => x"387b8008",
+871 => x"56579378",
+872 => x"2780dc38",
+873 => x"7b707084",
+874 => x"05520880",
+875 => x"08708405",
+876 => x"800c0c80",
+877 => x"08717084",
+878 => x"0553085d",
+879 => x"567b7670",
+880 => x"8405580c",
+881 => x"579b7827",
+882 => x"b6387670",
+883 => x"84055808",
+884 => x"75708405",
+885 => x"570c7670",
+886 => x"84055808",
+887 => x"75708405",
+888 => x"570ca378",
+889 => x"27993876",
+890 => x"70840558",
+891 => x"08757084",
+892 => x"05570c76",
+893 => x"70840558",
+894 => x"08757084",
+895 => x"05570c76",
+896 => x"70840558",
+897 => x"08775e75",
+898 => x"70840557",
+899 => x"0c747d70",
+900 => x"84055f08",
+901 => x"71708405",
+902 => x"530c7d08",
+903 => x"710c5f7b",
+904 => x"5261518e",
+905 => x"943f6151",
+906 => x"a4f33f79",
+907 => x"800c933d",
+908 => x"0d047d52",
+909 => x"61519690",
+910 => x"3f800880",
+911 => x"0c933d0d",
+912 => x"04841608",
+913 => x"55fbc939",
+914 => x"77537b52",
+915 => x"800851a2",
+916 => x"a53f7b52",
+917 => x"61518de1",
+918 => x"3fcc398c",
+919 => x"16088817",
+920 => x"08718c12",
+921 => x"0c88120c",
+922 => x"5d8c1708",
+923 => x"88180871",
+924 => x"8c120c88",
+925 => x"120c5977",
+926 => x"59fbef39",
+927 => x"7818901c",
+928 => x"40557e75",
+929 => x"24fb9c38",
+930 => x"7a177080",
+931 => x"d7a00b88",
+932 => x"050c757c",
+933 => x"31810784",
+934 => x"120c5684",
+935 => x"17088106",
+936 => x"7b078418",
+937 => x"0c6151a3",
+938 => x"f43f8817",
+939 => x"54fce139",
+940 => x"74181990",
+941 => x"1c5e5a7c",
+942 => x"7a24fb8f",
+943 => x"388c1708",
+944 => x"88180871",
+945 => x"8c120c88",
+946 => x"120c5e88",
+947 => x"1761fc05",
+948 => x"575975a4",
+949 => x"2681b638",
+950 => x"7b795955",
+951 => x"93762780",
+952 => x"c9387b70",
+953 => x"84055d08",
+954 => x"7c56790c",
+955 => x"74708405",
+956 => x"56088c18",
+957 => x"0c901758",
+958 => x"9b7627ae",
+959 => x"38747084",
+960 => x"05560878",
+961 => x"0c747084",
+962 => x"05560894",
+963 => x"180c9817",
+964 => x"58a37627",
+965 => x"95387470",
+966 => x"84055608",
+967 => x"780c7470",
+968 => x"84055608",
+969 => x"9c180ca0",
+970 => x"17587470",
+971 => x"84055608",
+972 => x"75417870",
+973 => x"84055a0c",
+974 => x"77607084",
+975 => x"05420871",
+976 => x"70840553",
+977 => x"0c600871",
+978 => x"0c5e7a17",
+979 => x"7080d7a0",
+980 => x"0b88050c",
+981 => x"7a7c3181",
+982 => x"0784120c",
+983 => x"58841708",
+984 => x"81067b07",
+985 => x"84180c61",
+986 => x"51a2b23f",
+987 => x"78547380",
+988 => x"0c933d0d",
+989 => x"0479537b",
+990 => x"5275519f",
+991 => x"f93ffae9",
+992 => x"39841508",
+993 => x"fc061960",
+994 => x"5859fadd",
+995 => x"3975537b",
+996 => x"5278519f",
+997 => x"e13f7a17",
+998 => x"7080d7a0",
+999 => x"0b88050c",
+1000 => x"7a7c3181",
+1001 => x"0784120c",
+1002 => x"58841708",
+1003 => x"81067b07",
+1004 => x"84180c61",
+1005 => x"51a1e63f",
+1006 => x"7854ffb2",
+1007 => x"39fa3d0d",
+1008 => x"7880cfe4",
+1009 => x"085455b8",
+1010 => x"1308802e",
+1011 => x"81af388c",
+1012 => x"15227083",
+1013 => x"ffff0670",
+1014 => x"832a8132",
+1015 => x"81065555",
+1016 => x"5672802e",
+1017 => x"80da3873",
+1018 => x"842a8132",
+1019 => x"810657ff",
+1020 => x"537680f2",
+1021 => x"3873822a",
+1022 => x"81065473",
+1023 => x"802eb938",
+1024 => x"b0150854",
+1025 => x"73802e9c",
+1026 => x"3880c015",
+1027 => x"5373732e",
+1028 => x"8f387352",
+1029 => x"80cfe408",
+1030 => x"518a9e3f",
+1031 => x"8c152256",
+1032 => x"76b0160c",
+1033 => x"75db0657",
+1034 => x"768c1623",
+1035 => x"800b8416",
+1036 => x"0c901508",
+1037 => x"750c7656",
+1038 => x"75880754",
+1039 => x"738c1623",
+1040 => x"90150880",
+1041 => x"2ebf388c",
+1042 => x"15227081",
+1043 => x"06555373",
+1044 => x"9c38720a",
+1045 => x"100a8106",
+1046 => x"56758538",
+1047 => x"94150854",
+1048 => x"7388160c",
+1049 => x"80537280",
+1050 => x"0c883d0d",
+1051 => x"04800b88",
+1052 => x"160c9415",
+1053 => x"08309816",
+1054 => x"0c8053ea",
+1055 => x"39725182",
+1056 => x"a63ffecb",
+1057 => x"3974518f",
+1058 => x"bc3f8c15",
+1059 => x"22708106",
+1060 => x"55537380",
+1061 => x"2effbb38",
+1062 => x"d439f83d",
+1063 => x"0d7a5776",
+1064 => x"802e8197",
+1065 => x"3880cfe4",
+1066 => x"0854b814",
+1067 => x"08802e80",
+1068 => x"eb388c17",
+1069 => x"2270902b",
+1070 => x"70902c70",
+1071 => x"832a8132",
+1072 => x"81065b5b",
+1073 => x"57557780",
+1074 => x"cb389017",
+1075 => x"08567580",
+1076 => x"2e80c138",
+1077 => x"76087631",
+1078 => x"76780c79",
+1079 => x"83065555",
+1080 => x"73853894",
+1081 => x"17085877",
+1082 => x"88180c80",
+1083 => x"7525a538",
+1084 => x"74537552",
+1085 => x"9c170851",
+1086 => x"a4170854",
+1087 => x"732d800b",
+1088 => x"80082580",
+1089 => x"c9388008",
+1090 => x"16758008",
+1091 => x"31565674",
+1092 => x"8024dd38",
+1093 => x"800b800c",
+1094 => x"8a3d0d04",
+1095 => x"73518187",
+1096 => x"3f8c1722",
+1097 => x"70902b70",
+1098 => x"902c7083",
+1099 => x"2a813281",
+1100 => x"065b5b57",
+1101 => x"5577dd38",
+1102 => x"ff9039a1",
+1103 => x"9a5280cf",
+1104 => x"e408518c",
+1105 => x"d03f8008",
+1106 => x"800c8a3d",
+1107 => x"0d048c17",
+1108 => x"2280c007",
+1109 => x"58778c18",
+1110 => x"23ff0b80",
+1111 => x"0c8a3d0d",
+1112 => x"04fa3d0d",
+1113 => x"797080dc",
+1114 => x"298c1154",
+1115 => x"7a535657",
+1116 => x"8fd63f80",
+1117 => x"08800855",
+1118 => x"56800880",
+1119 => x"2ea23880",
+1120 => x"088c0554",
+1121 => x"800b8008",
+1122 => x"0c768008",
+1123 => x"84050c73",
+1124 => x"80088805",
+1125 => x"0c745380",
+1126 => x"5273519c",
+1127 => x"f53f7554",
+1128 => x"73800c88",
+1129 => x"3d0d0470",
+1130 => x"707074a8",
+1131 => x"e60bbc12",
+1132 => x"0c53810b",
+1133 => x"b8140c80",
+1134 => x"0b84dc14",
+1135 => x"0c830b84",
+1136 => x"e0140c84",
+1137 => x"e81384e4",
+1138 => x"140c8413",
+1139 => x"08518070",
+1140 => x"720c7084",
+1141 => x"130c7088",
+1142 => x"130c5284",
+1143 => x"0b8c1223",
+1144 => x"718e1223",
+1145 => x"7190120c",
+1146 => x"7194120c",
+1147 => x"7198120c",
+1148 => x"709c120c",
+1149 => x"80c1d50b",
+1150 => x"a0120c80",
+1151 => x"c2a10ba4",
+1152 => x"120c80c3",
+1153 => x"9d0ba812",
+1154 => x"0c80c3ee",
+1155 => x"0bac120c",
+1156 => x"88130872",
+1157 => x"710c7284",
+1158 => x"120c7288",
+1159 => x"120c5189",
+1160 => x"0b8c1223",
+1161 => x"810b8e12",
+1162 => x"23719012",
+1163 => x"0c719412",
+1164 => x"0c719812",
+1165 => x"0c709c12",
+1166 => x"0c80c1d5",
+1167 => x"0ba0120c",
+1168 => x"80c2a10b",
+1169 => x"a4120c80",
+1170 => x"c39d0ba8",
+1171 => x"120c80c3",
+1172 => x"ee0bac12",
+1173 => x"0c8c1308",
+1174 => x"72710c72",
+1175 => x"84120c72",
+1176 => x"88120c51",
+1177 => x"8a0b8c12",
+1178 => x"23820b8e",
+1179 => x"12237190",
+1180 => x"120c7194",
+1181 => x"120c7198",
+1182 => x"120c709c",
+1183 => x"120c80c1",
+1184 => x"d50ba012",
+1185 => x"0c80c2a1",
+1186 => x"0ba4120c",
+1187 => x"80c39d0b",
+1188 => x"a8120c80",
+1189 => x"c3ee0bac",
+1190 => x"120c5050",
+1191 => x"5004f83d",
+1192 => x"0d7a80cf",
+1193 => x"e408b811",
+1194 => x"08575758",
+1195 => x"7481ec38",
+1196 => x"a8e60bbc",
+1197 => x"170c810b",
+1198 => x"b8170c74",
+1199 => x"84dc170c",
+1200 => x"830b84e0",
+1201 => x"170c84e8",
+1202 => x"1684e417",
+1203 => x"0c841608",
+1204 => x"75710c75",
+1205 => x"84120c75",
+1206 => x"88120c59",
+1207 => x"840b8c1a",
+1208 => x"23748e1a",
+1209 => x"2374901a",
+1210 => x"0c74941a",
+1211 => x"0c74981a",
+1212 => x"0c789c1a",
+1213 => x"0c80c1d5",
+1214 => x"0ba01a0c",
+1215 => x"80c2a10b",
+1216 => x"a41a0c80",
+1217 => x"c39d0ba8",
+1218 => x"1a0c80c3",
+1219 => x"ee0bac1a",
+1220 => x"0c881608",
+1221 => x"75710c75",
+1222 => x"84120c75",
+1223 => x"88120c57",
+1224 => x"890b8c18",
+1225 => x"23810b8e",
+1226 => x"18237490",
+1227 => x"180c7494",
+1228 => x"180c7498",
+1229 => x"180c769c",
+1230 => x"180c80c1",
+1231 => x"d50ba018",
+1232 => x"0c80c2a1",
+1233 => x"0ba4180c",
+1234 => x"80c39d0b",
+1235 => x"a8180c80",
+1236 => x"c3ee0bac",
+1237 => x"180c8c16",
+1238 => x"0875710c",
+1239 => x"7584120c",
+1240 => x"7588120c",
+1241 => x"548a0b8c",
+1242 => x"1523820b",
+1243 => x"8e152374",
+1244 => x"90150c74",
+1245 => x"94150c74",
+1246 => x"98150c73",
+1247 => x"9c150c80",
+1248 => x"c1d50ba0",
+1249 => x"150c80c2",
+1250 => x"a10ba415",
+1251 => x"0c80c39d",
+1252 => x"0ba8150c",
+1253 => x"80c3ee0b",
+1254 => x"ac150c84",
+1255 => x"dc168811",
+1256 => x"08841208",
+1257 => x"ff055757",
+1258 => x"57807524",
+1259 => x"9f388c16",
+1260 => x"2270902b",
+1261 => x"70902c51",
+1262 => x"55597380",
+1263 => x"2e80ed38",
+1264 => x"80dc16ff",
+1265 => x"16565674",
+1266 => x"8025e338",
+1267 => x"76085574",
+1268 => x"802e8f38",
+1269 => x"74881108",
+1270 => x"841208ff",
+1271 => x"05575757",
+1272 => x"c83982fc",
+1273 => x"5277518a",
+1274 => x"df3f8008",
+1275 => x"80085556",
+1276 => x"8008802e",
+1277 => x"a3388008",
+1278 => x"8c057580",
+1279 => x"080c5484",
+1280 => x"0b800884",
+1281 => x"050c7380",
+1282 => x"0888050c",
+1283 => x"82f05374",
+1284 => x"52735197",
+1285 => x"fd3f7554",
+1286 => x"7374780c",
+1287 => x"5573ffb4",
+1288 => x"388c780c",
+1289 => x"800b800c",
+1290 => x"8a3d0d04",
+1291 => x"810b8c17",
+1292 => x"2373760c",
+1293 => x"7388170c",
+1294 => x"7384170c",
+1295 => x"7390170c",
+1296 => x"7394170c",
+1297 => x"7398170c",
+1298 => x"ff0b8e17",
+1299 => x"2373b017",
+1300 => x"0c73b417",
+1301 => x"0c7380c4",
+1302 => x"170c7380",
+1303 => x"c8170c75",
+1304 => x"800c8a3d",
+1305 => x"0d047070",
+1306 => x"a19a5273",
+1307 => x"5186a63f",
+1308 => x"50500470",
+1309 => x"70a19a52",
+1310 => x"80cfe408",
+1311 => x"5186963f",
+1312 => x"505004fb",
+1313 => x"3d0d7770",
+1314 => x"52569890",
+1315 => x"3f80d7a0",
+1316 => x"0b880508",
+1317 => x"841108fc",
+1318 => x"06707b31",
+1319 => x"9fef05e0",
+1320 => x"8006e080",
+1321 => x"05525555",
+1322 => x"a0807524",
+1323 => x"94388052",
+1324 => x"755197ea",
+1325 => x"3f80d7a8",
+1326 => x"08145372",
+1327 => x"80082e8f",
+1328 => x"38755197",
+1329 => x"d83f8053",
+1330 => x"72800c87",
+1331 => x"3d0d0474",
+1332 => x"30527551",
+1333 => x"97c83f80",
+1334 => x"08ff2ea8",
+1335 => x"3880d7a0",
+1336 => x"0b880508",
+1337 => x"74763181",
+1338 => x"0784120c",
+1339 => x"5380d6e4",
+1340 => x"08753180",
+1341 => x"d6e40c75",
+1342 => x"5197a23f",
+1343 => x"810b800c",
+1344 => x"873d0d04",
+1345 => x"80527551",
+1346 => x"97943f80",
+1347 => x"d7a00b88",
+1348 => x"05088008",
+1349 => x"71315454",
+1350 => x"8f7325ff",
+1351 => x"a4388008",
+1352 => x"80d79408",
+1353 => x"3180d6e4",
+1354 => x"0c728107",
+1355 => x"84150c75",
+1356 => x"5196ea3f",
+1357 => x"8053ff90",
+1358 => x"39f73d0d",
+1359 => x"7b7d545a",
+1360 => x"72802e82",
+1361 => x"83387951",
+1362 => x"96d23ff8",
+1363 => x"13841108",
+1364 => x"70fe0670",
+1365 => x"13841108",
+1366 => x"fc065c57",
+1367 => x"58545780",
+1368 => x"d7a80874",
+1369 => x"2e82de38",
+1370 => x"7784150c",
+1371 => x"80738106",
+1372 => x"56597479",
+1373 => x"2e81d538",
+1374 => x"77148411",
+1375 => x"08810656",
+1376 => x"5374a038",
+1377 => x"77165678",
+1378 => x"81e63888",
+1379 => x"14085574",
+1380 => x"80d7a82e",
+1381 => x"82f9388c",
+1382 => x"1408708c",
+1383 => x"170c7588",
+1384 => x"120c5875",
+1385 => x"81078418",
+1386 => x"0c751776",
+1387 => x"710c5478",
+1388 => x"81913883",
+1389 => x"ff762781",
+1390 => x"c8387589",
+1391 => x"2a76832a",
+1392 => x"54547380",
+1393 => x"2ebf3875",
+1394 => x"862ab805",
+1395 => x"53847427",
+1396 => x"b43880db",
+1397 => x"14539474",
+1398 => x"27ab3875",
+1399 => x"8c2a80ee",
+1400 => x"055380d4",
+1401 => x"74279e38",
+1402 => x"758f2a80",
+1403 => x"f7055382",
+1404 => x"d4742791",
+1405 => x"3875922a",
+1406 => x"80fc0553",
+1407 => x"8ad47427",
+1408 => x"843880fe",
+1409 => x"53721010",
+1410 => x"1080d7a0",
+1411 => x"05881108",
+1412 => x"55557375",
+1413 => x"2e82bf38",
+1414 => x"841408fc",
+1415 => x"06597579",
+1416 => x"278d3888",
+1417 => x"14085473",
+1418 => x"752e0981",
+1419 => x"06ea388c",
+1420 => x"1408708c",
+1421 => x"190c7488",
+1422 => x"190c7788",
+1423 => x"120c5576",
+1424 => x"8c150c79",
+1425 => x"5194d63f",
+1426 => x"8b3d0d04",
+1427 => x"76087771",
+1428 => x"31587605",
+1429 => x"88180856",
+1430 => x"567480d7",
+1431 => x"a82e80e0",
+1432 => x"388c1708",
+1433 => x"708c170c",
+1434 => x"7588120c",
+1435 => x"53fe8939",
+1436 => x"8814088c",
+1437 => x"1508708c",
+1438 => x"130c5988",
+1439 => x"190cfea3",
+1440 => x"3975832a",
+1441 => x"70545480",
+1442 => x"74248198",
+1443 => x"3872822c",
+1444 => x"81712b80",
+1445 => x"d7a40807",
+1446 => x"80d7a00b",
+1447 => x"84050c74",
+1448 => x"10101080",
+1449 => x"d7a00588",
+1450 => x"1108718c",
+1451 => x"1b0c7088",
+1452 => x"1b0c7988",
+1453 => x"130c565a",
+1454 => x"55768c15",
+1455 => x"0cff8439",
+1456 => x"8159fdb4",
+1457 => x"39771673",
+1458 => x"81065455",
+1459 => x"72983876",
+1460 => x"08777131",
+1461 => x"5875058c",
+1462 => x"18088819",
+1463 => x"08718c12",
+1464 => x"0c88120c",
+1465 => x"55557481",
+1466 => x"0784180c",
+1467 => x"7680d7a0",
+1468 => x"0b88050c",
+1469 => x"80d79c08",
+1470 => x"7526fec7",
+1471 => x"3880d798",
+1472 => x"08527951",
+1473 => x"fafd3f79",
+1474 => x"5193923f",
+1475 => x"feba3981",
+1476 => x"778c170c",
+1477 => x"7788170c",
+1478 => x"758c190c",
+1479 => x"7588190c",
+1480 => x"59fd8039",
+1481 => x"83147082",
+1482 => x"2c81712b",
+1483 => x"80d7a408",
+1484 => x"0780d7a0",
+1485 => x"0b84050c",
+1486 => x"75101010",
+1487 => x"80d7a005",
+1488 => x"88110871",
+1489 => x"8c1c0c70",
+1490 => x"881c0c7a",
+1491 => x"88130c57",
+1492 => x"5b5653fe",
+1493 => x"e4398073",
+1494 => x"24a33872",
+1495 => x"822c8171",
+1496 => x"2b80d7a4",
+1497 => x"080780d7",
+1498 => x"a00b8405",
+1499 => x"0c58748c",
+1500 => x"180c7388",
+1501 => x"180c7688",
+1502 => x"160cfdc3",
+1503 => x"39831370",
+1504 => x"822c8171",
+1505 => x"2b80d7a4",
+1506 => x"080780d7",
+1507 => x"a00b8405",
+1508 => x"0c5953da",
+1509 => x"39f93d0d",
+1510 => x"797b5853",
+1511 => x"800b80cf",
+1512 => x"e4085356",
+1513 => x"72722ebc",
+1514 => x"3884dc13",
+1515 => x"5574762e",
+1516 => x"b3388815",
+1517 => x"08841608",
+1518 => x"ff055454",
+1519 => x"80732499",
+1520 => x"388c1422",
+1521 => x"70902b53",
+1522 => x"587180d4",
+1523 => x"3880dc14",
+1524 => x"ff145454",
+1525 => x"728025e9",
+1526 => x"38740855",
+1527 => x"74d43880",
+1528 => x"cfe40852",
+1529 => x"84dc1255",
+1530 => x"74802ead",
+1531 => x"38881508",
+1532 => x"841608ff",
+1533 => x"05545480",
+1534 => x"73249838",
+1535 => x"8c142270",
+1536 => x"902b5358",
+1537 => x"71ad3880",
+1538 => x"dc14ff14",
+1539 => x"54547280",
+1540 => x"25ea3874",
+1541 => x"085574d5",
+1542 => x"3875800c",
+1543 => x"893d0d04",
+1544 => x"7351762d",
+1545 => x"75800807",
+1546 => x"80dc15ff",
+1547 => x"15555556",
+1548 => x"ffa23973",
+1549 => x"51762d75",
+1550 => x"80080780",
+1551 => x"dc15ff15",
+1552 => x"555556ca",
+1553 => x"39ea3d0d",
+1554 => x"688c1122",
+1555 => x"700a100a",
+1556 => x"81065758",
+1557 => x"567480e4",
+1558 => x"388e1622",
+1559 => x"70902b70",
+1560 => x"902c5155",
+1561 => x"58807424",
+1562 => x"b138983d",
+1563 => x"c4055373",
+1564 => x"5280cfe4",
+1565 => x"08519481",
+1566 => x"3f800b80",
+1567 => x"08249738",
+1568 => x"7983e080",
+1569 => x"06547380",
+1570 => x"c0802e81",
+1571 => x"8f387382",
+1572 => x"80802e81",
+1573 => x"91388c16",
+1574 => x"22577690",
+1575 => x"80075473",
+1576 => x"8c172388",
+1577 => x"805280cf",
+1578 => x"e4085181",
+1579 => x"9b3f8008",
+1580 => x"9d388c16",
+1581 => x"22820755",
+1582 => x"748c1723",
+1583 => x"80c31670",
+1584 => x"770c9017",
+1585 => x"0c810b94",
+1586 => x"170c983d",
+1587 => x"0d0480cf",
+1588 => x"e408a8e6",
+1589 => x"0bbc120c",
+1590 => x"588c1622",
+1591 => x"81800754",
+1592 => x"738c1723",
+1593 => x"8008760c",
+1594 => x"80089017",
+1595 => x"0c88800b",
+1596 => x"94170c74",
+1597 => x"802ed338",
+1598 => x"8e162270",
+1599 => x"902b7090",
+1600 => x"2c535654",
+1601 => x"9afe3f80",
+1602 => x"08802eff",
+1603 => x"bd388c16",
+1604 => x"22810757",
+1605 => x"768c1723",
+1606 => x"983d0d04",
+1607 => x"810b8c17",
+1608 => x"225855fe",
+1609 => x"f539a816",
+1610 => x"0880c39d",
+1611 => x"2e098106",
+1612 => x"fee4388c",
+1613 => x"16228880",
+1614 => x"0754738c",
+1615 => x"17238880",
+1616 => x"0b80cc17",
+1617 => x"0cfedc39",
+1618 => x"f43d0d7e",
+1619 => x"608b1170",
+1620 => x"f8065b55",
+1621 => x"555d7296",
+1622 => x"26833890",
+1623 => x"58807824",
+1624 => x"74792607",
+1625 => x"55805474",
+1626 => x"742e0981",
+1627 => x"0680ca38",
+1628 => x"7c518ea8",
+1629 => x"3f7783f7",
+1630 => x"2680c538",
+1631 => x"77832a70",
+1632 => x"10101080",
+1633 => x"d7a0058c",
+1634 => x"11085858",
+1635 => x"5475772e",
+1636 => x"81f03884",
+1637 => x"1608fc06",
+1638 => x"8c170888",
+1639 => x"1808718c",
+1640 => x"120c8812",
+1641 => x"0c5b7605",
+1642 => x"84110881",
+1643 => x"0784120c",
+1644 => x"537c518d",
+1645 => x"e83f8816",
+1646 => x"5473800c",
+1647 => x"8e3d0d04",
+1648 => x"77892a78",
+1649 => x"832a5854",
+1650 => x"73802ebf",
+1651 => x"3877862a",
+1652 => x"b8055784",
+1653 => x"7427b438",
+1654 => x"80db1457",
+1655 => x"947427ab",
+1656 => x"38778c2a",
+1657 => x"80ee0557",
+1658 => x"80d47427",
+1659 => x"9e38778f",
+1660 => x"2a80f705",
+1661 => x"5782d474",
+1662 => x"27913877",
+1663 => x"922a80fc",
+1664 => x"05578ad4",
+1665 => x"74278438",
+1666 => x"80fe5776",
+1667 => x"10101080",
+1668 => x"d7a0058c",
+1669 => x"11085653",
+1670 => x"74732ea3",
+1671 => x"38841508",
+1672 => x"fc067079",
+1673 => x"31555673",
+1674 => x"8f2488e4",
+1675 => x"38738025",
+1676 => x"88e6388c",
+1677 => x"15085574",
+1678 => x"732e0981",
+1679 => x"06df3881",
+1680 => x"175980d7",
+1681 => x"b0085675",
+1682 => x"80d7a82e",
+1683 => x"82cc3884",
+1684 => x"1608fc06",
+1685 => x"70793155",
+1686 => x"55738f24",
+1687 => x"bb3880d7",
+1688 => x"a80b80d7",
+1689 => x"b40c80d7",
+1690 => x"a80b80d7",
+1691 => x"b00c8074",
+1692 => x"2480db38",
+1693 => x"74168411",
+1694 => x"08810784",
+1695 => x"120c53fe",
+1696 => x"b0398816",
+1697 => x"8c110857",
+1698 => x"5975792e",
+1699 => x"098106fe",
+1700 => x"82388214",
+1701 => x"59ffab39",
+1702 => x"77167881",
+1703 => x"0784180c",
+1704 => x"7080d7b4",
+1705 => x"0c7080d7",
+1706 => x"b00c80d7",
+1707 => x"a80b8c12",
+1708 => x"0c8c1108",
+1709 => x"88120c74",
+1710 => x"81078412",
+1711 => x"0c740574",
+1712 => x"710c5b7c",
+1713 => x"518bd63f",
+1714 => x"881654fd",
+1715 => x"ec3983ff",
+1716 => x"75278391",
+1717 => x"3874892a",
+1718 => x"75832a54",
+1719 => x"5473802e",
+1720 => x"bf387486",
+1721 => x"2ab80553",
+1722 => x"847427b4",
+1723 => x"3880db14",
+1724 => x"53947427",
+1725 => x"ab38748c",
+1726 => x"2a80ee05",
+1727 => x"5380d474",
+1728 => x"279e3874",
+1729 => x"8f2a80f7",
+1730 => x"055382d4",
+1731 => x"74279138",
+1732 => x"74922a80",
+1733 => x"fc05538a",
+1734 => x"d4742784",
+1735 => x"3880fe53",
+1736 => x"72101010",
+1737 => x"80d7a005",
+1738 => x"88110855",
+1739 => x"5773772e",
+1740 => x"868b3884",
+1741 => x"1408fc06",
+1742 => x"5b747b27",
+1743 => x"8d388814",
+1744 => x"08547377",
+1745 => x"2e098106",
+1746 => x"ea388c14",
+1747 => x"0880d7a0",
+1748 => x"0b840508",
+1749 => x"718c190c",
+1750 => x"7588190c",
+1751 => x"7788130c",
+1752 => x"5c57758c",
+1753 => x"150c7853",
+1754 => x"80792483",
+1755 => x"98387282",
+1756 => x"2c81712b",
+1757 => x"5656747b",
+1758 => x"2680ca38",
+1759 => x"7a750657",
+1760 => x"7682a338",
+1761 => x"78fc0684",
+1762 => x"05597410",
+1763 => x"707c0655",
+1764 => x"55738292",
+1765 => x"38841959",
+1766 => x"f13980d7",
+1767 => x"a00b8405",
+1768 => x"0879545b",
+1769 => x"788025c6",
+1770 => x"3882da39",
+1771 => x"74097b06",
+1772 => x"7080d7a0",
+1773 => x"0b84050c",
+1774 => x"5b741055",
+1775 => x"747b2685",
+1776 => x"387485bc",
+1777 => x"3880d7a0",
+1778 => x"0b880508",
+1779 => x"70841208",
+1780 => x"fc06707b",
+1781 => x"317b7226",
+1782 => x"8f722507",
+1783 => x"5d575c5c",
+1784 => x"5578802e",
+1785 => x"80d93879",
+1786 => x"1580d798",
+1787 => x"08199011",
+1788 => x"59545680",
+1789 => x"d79408ff",
+1790 => x"2e8838a0",
+1791 => x"8f13e080",
+1792 => x"06577652",
+1793 => x"7c518996",
+1794 => x"3f800854",
+1795 => x"8008ff2e",
+1796 => x"90388008",
+1797 => x"762782a7",
+1798 => x"387480d7",
+1799 => x"a02e829f",
+1800 => x"3880d7a0",
+1801 => x"0b880508",
+1802 => x"55841508",
+1803 => x"fc067079",
+1804 => x"31797226",
+1805 => x"8f722507",
+1806 => x"5d555a7a",
+1807 => x"83f23877",
+1808 => x"81078416",
+1809 => x"0c771570",
+1810 => x"80d7a00b",
+1811 => x"88050c74",
+1812 => x"81078412",
+1813 => x"0c567c51",
+1814 => x"88c33f88",
+1815 => x"15547380",
+1816 => x"0c8e3d0d",
+1817 => x"0474832a",
+1818 => x"70545480",
+1819 => x"7424819b",
+1820 => x"3872822c",
+1821 => x"81712b80",
+1822 => x"d7a40807",
+1823 => x"7080d7a0",
+1824 => x"0b84050c",
+1825 => x"75101010",
+1826 => x"80d7a005",
+1827 => x"88110871",
+1828 => x"8c1b0c70",
+1829 => x"881b0c79",
+1830 => x"88130c57",
+1831 => x"555c5575",
+1832 => x"8c150cfd",
+1833 => x"c1397879",
+1834 => x"10101080",
+1835 => x"d7a00570",
+1836 => x"565b5c8c",
+1837 => x"14085675",
+1838 => x"742ea338",
+1839 => x"841608fc",
+1840 => x"06707931",
+1841 => x"5853768f",
+1842 => x"2483f138",
+1843 => x"76802584",
+1844 => x"af388c16",
+1845 => x"08567574",
+1846 => x"2e098106",
+1847 => x"df388814",
+1848 => x"811a7083",
+1849 => x"06555a54",
+1850 => x"72c9387b",
+1851 => x"83065675",
+1852 => x"802efdb8",
+1853 => x"38ff1cf8",
+1854 => x"1b5b5c88",
+1855 => x"1a087a2e",
+1856 => x"ea38fdb5",
+1857 => x"39831953",
+1858 => x"fce43983",
+1859 => x"1470822c",
+1860 => x"81712b80",
+1861 => x"d7a40807",
+1862 => x"7080d7a0",
+1863 => x"0b84050c",
+1864 => x"76101010",
+1865 => x"80d7a005",
+1866 => x"88110871",
+1867 => x"8c1c0c70",
+1868 => x"881c0c7a",
+1869 => x"88130c58",
+1870 => x"535d5653",
+1871 => x"fee13980",
+1872 => x"d6e40817",
+1873 => x"59800876",
+1874 => x"2e818b38",
+1875 => x"80d79408",
+1876 => x"ff2e848e",
+1877 => x"38737631",
+1878 => x"1980d6e4",
+1879 => x"0c738706",
+1880 => x"70565372",
+1881 => x"802e8838",
+1882 => x"88733170",
+1883 => x"15555576",
+1884 => x"149fff06",
+1885 => x"a0807131",
+1886 => x"1670547e",
+1887 => x"53515386",
+1888 => x"9d3f8008",
+1889 => x"568008ff",
+1890 => x"2e819e38",
+1891 => x"80d6e408",
+1892 => x"137080d6",
+1893 => x"e40c7475",
+1894 => x"80d7a00b",
+1895 => x"88050c77",
+1896 => x"76311581",
+1897 => x"07555659",
+1898 => x"7a80d7a0",
+1899 => x"2e83c038",
+1900 => x"798f2682",
+1901 => x"ef38810b",
+1902 => x"84150c84",
+1903 => x"1508fc06",
+1904 => x"70793179",
+1905 => x"72268f72",
+1906 => x"25075d55",
+1907 => x"5a7a802e",
+1908 => x"fced3880",
+1909 => x"db398008",
+1910 => x"9fff0655",
+1911 => x"74feed38",
+1912 => x"7880d6e4",
+1913 => x"0c80d7a0",
+1914 => x"0b880508",
+1915 => x"7a188107",
+1916 => x"84120c55",
+1917 => x"80d79008",
+1918 => x"79278638",
+1919 => x"7880d790",
+1920 => x"0c80d78c",
+1921 => x"087927fc",
+1922 => x"a0387880",
+1923 => x"d78c0c84",
+1924 => x"1508fc06",
+1925 => x"70793179",
+1926 => x"72268f72",
+1927 => x"25075d55",
+1928 => x"5a7a802e",
+1929 => x"fc993888",
+1930 => x"39807457",
+1931 => x"53fedd39",
+1932 => x"7c5184e9",
+1933 => x"3f800b80",
+1934 => x"0c8e3d0d",
+1935 => x"04807324",
+1936 => x"a5387282",
+1937 => x"2c81712b",
+1938 => x"80d7a408",
+1939 => x"077080d7",
+1940 => x"a00b8405",
+1941 => x"0c5c5a76",
+1942 => x"8c170c73",
+1943 => x"88170c75",
+1944 => x"88180cf9",
+1945 => x"fd398313",
+1946 => x"70822c81",
+1947 => x"712b80d7",
+1948 => x"a4080770",
+1949 => x"80d7a00b",
+1950 => x"84050c5d",
+1951 => x"5b53d839",
+1952 => x"7a75065c",
+1953 => x"7bfc9f38",
+1954 => x"84197510",
+1955 => x"5659f139",
+1956 => x"ff178105",
+1957 => x"59f7ab39",
+1958 => x"8c150888",
+1959 => x"1608718c",
+1960 => x"120c8812",
+1961 => x"0c597515",
+1962 => x"84110881",
+1963 => x"0784120c",
+1964 => x"587c5183",
+1965 => x"e83f8815",
+1966 => x"54fba339",
+1967 => x"77167881",
+1968 => x"0784180c",
+1969 => x"8c170888",
+1970 => x"1808718c",
+1971 => x"120c8812",
+1972 => x"0c5c7080",
+1973 => x"d7b40c70",
+1974 => x"80d7b00c",
+1975 => x"80d7a80b",
+1976 => x"8c120c8c",
+1977 => x"11088812",
+1978 => x"0c778107",
+1979 => x"84120c77",
+1980 => x"0577710c",
+1981 => x"557c5183",
+1982 => x"a43f8816",
+1983 => x"54f5ba39",
+1984 => x"72168411",
+1985 => x"08810784",
+1986 => x"120c588c",
+1987 => x"16088817",
+1988 => x"08718c12",
+1989 => x"0c88120c",
+1990 => x"577c5183",
+1991 => x"803f8816",
+1992 => x"54f59639",
+1993 => x"7284150c",
+1994 => x"f41af806",
+1995 => x"70841d08",
+1996 => x"81060784",
+1997 => x"1d0c701c",
+1998 => x"5556850b",
+1999 => x"84150c85",
+2000 => x"0b88150c",
+2001 => x"8f7627fd",
+2002 => x"ab38881b",
+2003 => x"527c51eb",
+2004 => x"e83f80d7",
+2005 => x"a00b8805",
+2006 => x"0880d6e4",
+2007 => x"085a55fd",
+2008 => x"93397880",
+2009 => x"d6e40c73",
+2010 => x"80d7940c",
+2011 => x"fbef3972",
+2012 => x"84150cfc",
+2013 => x"ff39fb3d",
+2014 => x"0d77707a",
+2015 => x"7c585553",
+2016 => x"568f7527",
+2017 => x"80e63872",
+2018 => x"76078306",
+2019 => x"517080dc",
+2020 => x"38757352",
+2021 => x"54707084",
+2022 => x"05520874",
+2023 => x"70840556",
+2024 => x"0c737170",
+2025 => x"84055308",
+2026 => x"71708405",
+2027 => x"530c7170",
+2028 => x"84055308",
+2029 => x"71708405",
+2030 => x"530c7170",
+2031 => x"84055308",
+2032 => x"71708405",
+2033 => x"530cf016",
+2034 => x"5654748f",
+2035 => x"26c73883",
+2036 => x"75279538",
+2037 => x"70708405",
+2038 => x"52087470",
+2039 => x"8405560c",
+2040 => x"fc155574",
+2041 => x"8326ed38",
+2042 => x"73715452",
+2043 => x"ff155170",
+2044 => x"ff2e9838",
+2045 => x"72708105",
+2046 => x"54337270",
+2047 => x"81055434",
+2048 => x"ff115170",
+2049 => x"ff2e0981",
+2050 => x"06ea3875",
+2051 => x"800c873d",
+2052 => x"0d04fb3d",
+2053 => x"0d777a71",
+2054 => x"028c05a3",
+2055 => x"05335854",
+2056 => x"54568373",
+2057 => x"2780d438",
+2058 => x"75830651",
+2059 => x"7080cc38",
+2060 => x"74882b75",
+2061 => x"07707190",
+2062 => x"2b075551",
+2063 => x"8f7327a7",
+2064 => x"38737270",
+2065 => x"8405540c",
+2066 => x"71747170",
+2067 => x"8405530c",
+2068 => x"74717084",
+2069 => x"05530c74",
+2070 => x"71708405",
+2071 => x"530cf014",
+2072 => x"5452728f",
+2073 => x"26db3883",
+2074 => x"73279038",
+2075 => x"73727084",
+2076 => x"05540cfc",
+2077 => x"13537283",
+2078 => x"26f238ff",
+2079 => x"135170ff",
+2080 => x"2e933874",
+2081 => x"72708105",
+2082 => x"5434ff11",
+2083 => x"5170ff2e",
+2084 => x"098106ef",
+2085 => x"3875800c",
+2086 => x"873d0d04",
+2087 => x"04047070",
+2088 => x"7070800b",
+2089 => x"80dfe00c",
+2090 => x"765184f3",
+2091 => x"3f800853",
+2092 => x"8008ff2e",
+2093 => x"89387280",
+2094 => x"0c505050",
+2095 => x"500480df",
+2096 => x"e0085473",
+2097 => x"802eef38",
+2098 => x"7574710c",
+2099 => x"5272800c",
+2100 => x"50505050",
+2101 => x"04f93d0d",
+2102 => x"797c557b",
+2103 => x"548e1122",
+2104 => x"70902b70",
+2105 => x"902c5557",
+2106 => x"80cfe408",
+2107 => x"53585683",
+2108 => x"f63f8008",
+2109 => x"57800b80",
+2110 => x"08249338",
+2111 => x"80d01608",
+2112 => x"80080580",
+2113 => x"d0170c76",
+2114 => x"800c893d",
+2115 => x"0d048c16",
+2116 => x"2283dfff",
+2117 => x"0655748c",
+2118 => x"17237680",
+2119 => x"0c893d0d",
+2120 => x"04fa3d0d",
+2121 => x"788c1122",
+2122 => x"70882a70",
+2123 => x"81065157",
+2124 => x"585674a9",
+2125 => x"388c1622",
+2126 => x"83dfff06",
+2127 => x"55748c17",
+2128 => x"237a5479",
+2129 => x"538e1622",
+2130 => x"70902b70",
+2131 => x"902c5456",
+2132 => x"80cfe408",
+2133 => x"525681b2",
+2134 => x"3f883d0d",
+2135 => x"04825480",
+2136 => x"538e1622",
+2137 => x"70902b70",
+2138 => x"902c5456",
+2139 => x"80cfe408",
+2140 => x"525782bb",
+2141 => x"3f8c1622",
+2142 => x"83dfff06",
+2143 => x"55748c17",
+2144 => x"237a5479",
+2145 => x"538e1622",
+2146 => x"70902b70",
+2147 => x"902c5456",
+2148 => x"80cfe408",
+2149 => x"525680f2",
+2150 => x"3f883d0d",
+2151 => x"04f93d0d",
+2152 => x"797c557b",
+2153 => x"548e1122",
+2154 => x"70902b70",
+2155 => x"902c5557",
+2156 => x"80cfe408",
+2157 => x"53585681",
+2158 => x"f63f8008",
+2159 => x"578008ff",
+2160 => x"2e99388c",
+2161 => x"1622a080",
+2162 => x"0755748c",
+2163 => x"17238008",
+2164 => x"80d0170c",
+2165 => x"76800c89",
+2166 => x"3d0d048c",
+2167 => x"162283df",
+2168 => x"ff065574",
+2169 => x"8c172376",
+2170 => x"800c893d",
+2171 => x"0d047070",
+2172 => x"70748e11",
+2173 => x"2270902b",
+2174 => x"70902c55",
+2175 => x"51515380",
+2176 => x"cfe40851",
+2177 => x"bd3f5050",
+2178 => x"5004fb3d",
+2179 => x"0d800b80",
+2180 => x"dfe00c7a",
+2181 => x"53795278",
+2182 => x"5182ff3f",
+2183 => x"80085580",
+2184 => x"08ff2e88",
+2185 => x"3874800c",
+2186 => x"873d0d04",
+2187 => x"80dfe008",
+2188 => x"5675802e",
+2189 => x"f0387776",
+2190 => x"710c5474",
+2191 => x"800c873d",
+2192 => x"0d047070",
+2193 => x"7070800b",
+2194 => x"80dfe00c",
+2195 => x"765184cc",
+2196 => x"3f800853",
+2197 => x"8008ff2e",
+2198 => x"89387280",
+2199 => x"0c505050",
+2200 => x"500480df",
+2201 => x"e0085473",
+2202 => x"802eef38",
+2203 => x"7574710c",
+2204 => x"5272800c",
+2205 => x"50505050",
+2206 => x"04fc3d0d",
+2207 => x"800b80df",
+2208 => x"e00c7852",
+2209 => x"775187b3",
+2210 => x"3f800854",
+2211 => x"8008ff2e",
+2212 => x"88387380",
+2213 => x"0c863d0d",
+2214 => x"0480dfe0",
+2215 => x"08557480",
+2216 => x"2ef03876",
+2217 => x"75710c53",
+2218 => x"73800c86",
+2219 => x"3d0d04fb",
+2220 => x"3d0d800b",
+2221 => x"80dfe00c",
+2222 => x"7a537952",
+2223 => x"7851848e",
+2224 => x"3f800855",
+2225 => x"8008ff2e",
+2226 => x"88387480",
+2227 => x"0c873d0d",
+2228 => x"0480dfe0",
+2229 => x"08567580",
+2230 => x"2ef03877",
+2231 => x"76710c54",
+2232 => x"74800c87",
+2233 => x"3d0d04fb",
+2234 => x"3d0d800b",
+2235 => x"80dfe00c",
+2236 => x"7a537952",
+2237 => x"78518296",
+2238 => x"3f800855",
+2239 => x"8008ff2e",
+2240 => x"88387480",
+2241 => x"0c873d0d",
+2242 => x"0480dfe0",
+2243 => x"08567580",
+2244 => x"2ef03877",
+2245 => x"76710c54",
+2246 => x"74800c87",
+2247 => x"3d0d0470",
+2248 => x"707080df",
+2249 => x"d0088938",
+2250 => x"80dfe40b",
+2251 => x"80dfd00c",
+2252 => x"80dfd008",
+2253 => x"75115252",
+2254 => x"ff537087",
+2255 => x"fb808026",
+2256 => x"88387080",
+2257 => x"dfd00c71",
+2258 => x"5372800c",
+2259 => x"50505004",
+2260 => x"fd3d0d80",
+2261 => x"0b80cfd8",
+2262 => x"08545472",
+2263 => x"812e9b38",
+2264 => x"7380dfd4",
+2265 => x"0cc2bf3f",
+2266 => x"c1963f80",
+2267 => x"dfa85281",
+2268 => x"51c3fd3f",
+2269 => x"80085186",
+2270 => x"c23f7280",
+2271 => x"dfd40cc2",
+2272 => x"a53fc0fc",
+2273 => x"3f80dfa8",
+2274 => x"528151c3",
+2275 => x"e33f8008",
+2276 => x"5186a83f",
+2277 => x"00ff3900",
+2278 => x"ff39f53d",
+2279 => x"0d7e6080",
+2280 => x"dfd40870",
+2281 => x"5b585b5b",
+2282 => x"7580c238",
+2283 => x"777a25a1",
+2284 => x"38771b70",
+2285 => x"337081ff",
+2286 => x"06585859",
+2287 => x"758a2e98",
+2288 => x"387681ff",
+2289 => x"0651c1bd",
+2290 => x"3f811858",
+2291 => x"797824e1",
+2292 => x"3879800c",
+2293 => x"8d3d0d04",
+2294 => x"8d51c1a9",
+2295 => x"3f783370",
+2296 => x"81ff0652",
+2297 => x"57c19e3f",
+2298 => x"811858e0",
+2299 => x"3979557a",
+2300 => x"547d5385",
+2301 => x"528d3dfc",
+2302 => x"0551c0c6",
+2303 => x"3f800856",
+2304 => x"85b23f7b",
+2305 => x"80080c75",
+2306 => x"800c8d3d",
+2307 => x"0d04f63d",
+2308 => x"0d7d7f80",
+2309 => x"dfd40870",
+2310 => x"5b585a5a",
+2311 => x"7580c138",
+2312 => x"777925b3",
+2313 => x"38c0b93f",
+2314 => x"800881ff",
+2315 => x"06708d32",
+2316 => x"7030709f",
+2317 => x"2a515157",
+2318 => x"57768a2e",
+2319 => x"80c43875",
+2320 => x"802ebf38",
+2321 => x"771a5676",
+2322 => x"76347651",
+2323 => x"c0b73f81",
+2324 => x"18587878",
+2325 => x"24cf3877",
+2326 => x"5675800c",
+2327 => x"8c3d0d04",
+2328 => x"78557954",
+2329 => x"7c538452",
+2330 => x"8c3dfc05",
+2331 => x"51ffbfd2",
+2332 => x"3f800856",
+2333 => x"84be3f7a",
+2334 => x"80080c75",
+2335 => x"800c8c3d",
+2336 => x"0d04771a",
+2337 => x"598a7934",
+2338 => x"8118588d",
+2339 => x"51ffbff5",
+2340 => x"3f8a51ff",
+2341 => x"bfef3f77",
+2342 => x"56ffbe39",
+2343 => x"fb3d0d80",
+2344 => x"dfd40870",
+2345 => x"56547388",
+2346 => x"3874800c",
+2347 => x"873d0d04",
+2348 => x"77538352",
+2349 => x"873dfc05",
+2350 => x"51ffbf86",
+2351 => x"3f800854",
+2352 => x"83f23f75",
+2353 => x"80080c73",
+2354 => x"800c873d",
+2355 => x"0d04fa3d",
+2356 => x"0d80dfd4",
+2357 => x"08802ea3",
+2358 => x"387a5579",
+2359 => x"54785386",
+2360 => x"52883dfc",
+2361 => x"0551ffbe",
+2362 => x"d93f8008",
+2363 => x"5683c53f",
+2364 => x"7680080c",
+2365 => x"75800c88",
+2366 => x"3d0d0483",
+2367 => x"b73f9d0b",
+2368 => x"80080cff",
+2369 => x"0b800c88",
+2370 => x"3d0d04f7",
+2371 => x"3d0d7b7d",
+2372 => x"5b59bc53",
+2373 => x"80527951",
+2374 => x"f5f83f80",
+2375 => x"70565798",
+2376 => x"56741970",
+2377 => x"3370782b",
+2378 => x"79078118",
+2379 => x"f81a5a58",
+2380 => x"59555884",
+2381 => x"7524ea38",
+2382 => x"767a2384",
+2383 => x"19588070",
+2384 => x"56579856",
+2385 => x"74187033",
+2386 => x"70782b79",
+2387 => x"078118f8",
+2388 => x"1a5a5859",
+2389 => x"51548475",
+2390 => x"24ea3876",
+2391 => x"821b2388",
+2392 => x"19588070",
+2393 => x"56579856",
+2394 => x"74187033",
+2395 => x"70782b79",
+2396 => x"078118f8",
+2397 => x"1a5a5859",
+2398 => x"51548475",
+2399 => x"24ea3876",
+2400 => x"841b0c8c",
+2401 => x"19588070",
+2402 => x"56579856",
+2403 => x"74187033",
+2404 => x"70782b79",
+2405 => x"078118f8",
+2406 => x"1a5a5859",
+2407 => x"51548475",
+2408 => x"24ea3876",
+2409 => x"881b2390",
+2410 => x"19588070",
+2411 => x"56579856",
+2412 => x"74187033",
+2413 => x"70782b79",
+2414 => x"078118f8",
+2415 => x"1a5a5859",
+2416 => x"51548475",
+2417 => x"24ea3876",
+2418 => x"8a1b2394",
+2419 => x"19588070",
+2420 => x"56579856",
+2421 => x"74187033",
+2422 => x"70782b79",
+2423 => x"078118f8",
+2424 => x"1a5a5859",
+2425 => x"51548475",
+2426 => x"24ea3876",
+2427 => x"8c1b2398",
+2428 => x"19588070",
+2429 => x"56579856",
+2430 => x"74187033",
+2431 => x"70782b79",
+2432 => x"078118f8",
+2433 => x"1a5a5859",
+2434 => x"51548475",
+2435 => x"24ea3876",
+2436 => x"8e1b239c",
+2437 => x"19588070",
+2438 => x"5657b856",
+2439 => x"74187033",
+2440 => x"70782b79",
+2441 => x"078118f8",
+2442 => x"1a5a5859",
+2443 => x"5a548875",
+2444 => x"24ea3876",
+2445 => x"901b0c8b",
+2446 => x"3d0d04e9",
+2447 => x"3d0d6a80",
+2448 => x"dfd40857",
+2449 => x"57759338",
+2450 => x"80c0800b",
+2451 => x"84180c75",
+2452 => x"ac180c75",
+2453 => x"800c993d",
+2454 => x"0d04893d",
+2455 => x"70556a54",
+2456 => x"558a5299",
+2457 => x"3dffbc05",
+2458 => x"51ffbbd6",
+2459 => x"3f800877",
+2460 => x"53755256",
+2461 => x"fd953fbc",
+2462 => x"3f778008",
+2463 => x"0c75800c",
+2464 => x"993d0d04",
+2465 => x"fc3d0d81",
+2466 => x"5480dfd4",
+2467 => x"08883873",
+2468 => x"800c863d",
+2469 => x"0d047653",
+2470 => x"97b95286",
+2471 => x"3dfc0551",
+2472 => x"ffbb9f3f",
+2473 => x"8008548c",
+2474 => x"3f748008",
+2475 => x"0c73800c",
+2476 => x"863d0d04",
+2477 => x"80cfe408",
+2478 => x"800c04f7",
+2479 => x"3d0d7b80",
+2480 => x"cfe40882",
+2481 => x"c811085a",
+2482 => x"545a7780",
+2483 => x"2e80da38",
+2484 => x"81881884",
+2485 => x"1908ff05",
+2486 => x"81712b59",
+2487 => x"55598074",
+2488 => x"2480ea38",
+2489 => x"807424b5",
+2490 => x"3873822b",
+2491 => x"78118805",
+2492 => x"56568180",
+2493 => x"19087706",
+2494 => x"5372802e",
+2495 => x"b6387816",
+2496 => x"70085353",
+2497 => x"79517408",
+2498 => x"53722dff",
+2499 => x"14fc17fc",
+2500 => x"1779812c",
+2501 => x"5a575754",
+2502 => x"738025d6",
+2503 => x"38770858",
+2504 => x"77ffad38",
+2505 => x"80cfe408",
+2506 => x"53bc1308",
+2507 => x"a5387951",
+2508 => x"f8e23f74",
+2509 => x"0853722d",
+2510 => x"ff14fc17",
+2511 => x"fc177981",
+2512 => x"2c5a5757",
+2513 => x"54738025",
+2514 => x"ffa838d1",
+2515 => x"398057ff",
+2516 => x"93397251",
+2517 => x"bc130854",
+2518 => x"732d7951",
+2519 => x"f8b63f70",
+2520 => x"7080dfb0",
+2521 => x"0bfc0570",
+2522 => x"08525270",
+2523 => x"ff2e9138",
+2524 => x"702dfc12",
+2525 => x"70085252",
+2526 => x"70ff2e09",
+2527 => x"8106f138",
+2528 => x"50500404",
+2529 => x"ffbb8c3f",
+2530 => x"04000000",
+2531 => x"00000040",
+2532 => x"48656c6c",
+2533 => x"6f20776f",
+2534 => x"726c6420",
+2535 => x"310a0000",
+2536 => x"48656c6c",
+2537 => x"6f20776f",
+2538 => x"726c6420",
+2539 => x"320a0000",
+2540 => x"0a000000",
+2541 => x"43000000",
+2542 => x"64756d6d",
+2543 => x"792e6578",
+2544 => x"65000000",
+2545 => x"00ffffff",
+2546 => x"ff00ffff",
+2547 => x"ffff00ff",
+2548 => x"ffffff00",
+2549 => x"00000000",
+2550 => x"00000000",
+2551 => x"00000000",
+2552 => x"00002fb8",
+2553 => x"000027e8",
+2554 => x"00000000",
+2555 => x"00002a50",
+2556 => x"00002aac",
+2557 => x"00002b08",
+2558 => x"00000000",
+2559 => x"00000000",
+2560 => x"00000000",
+2561 => x"00000000",
+2562 => x"00000000",
+2563 => x"00000000",
+2564 => x"00000000",
+2565 => x"00000000",
+2566 => x"00000000",
+2567 => x"000027b4",
+2568 => x"00000000",
+2569 => x"00000000",
+2570 => x"00000000",
+2571 => x"00000000",
+2572 => x"00000000",
+2573 => x"00000000",
+2574 => x"00000000",
+2575 => x"00000000",
+2576 => x"00000000",
+2577 => x"00000000",
+2578 => x"00000000",
+2579 => x"00000000",
+2580 => x"00000000",
+2581 => x"00000000",
+2582 => x"00000000",
+2583 => x"00000000",
+2584 => x"00000000",
+2585 => x"00000000",
+2586 => x"00000000",
+2587 => x"00000000",
+2588 => x"00000000",
+2589 => x"00000000",
+2590 => x"00000000",
+2591 => x"00000000",
+2592 => x"00000000",
+2593 => x"00000000",
+2594 => x"00000000",
+2595 => x"00000000",
+2596 => x"00000001",
+2597 => x"330eabcd",
+2598 => x"1234e66d",
+2599 => x"deec0005",
+2600 => x"000b0000",
+2601 => x"00000000",
+2602 => x"00000000",
+2603 => x"00000000",
+2604 => x"00000000",
+2605 => x"00000000",
+2606 => x"00000000",
+2607 => x"00000000",
+2608 => x"00000000",
+2609 => x"00000000",
+2610 => x"00000000",
+2611 => x"00000000",
+2612 => x"00000000",
+2613 => x"00000000",
+2614 => x"00000000",
+2615 => x"00000000",
+2616 => x"00000000",
+2617 => x"00000000",
+2618 => x"00000000",
+2619 => x"00000000",
+2620 => x"00000000",
+2621 => x"00000000",
+2622 => x"00000000",
+2623 => x"00000000",
+2624 => x"00000000",
+2625 => x"00000000",
+2626 => x"00000000",
+2627 => x"00000000",
+2628 => x"00000000",
+2629 => x"00000000",
+2630 => x"00000000",
+2631 => x"00000000",
+2632 => x"00000000",
+2633 => x"00000000",
+2634 => x"00000000",
+2635 => x"00000000",
+2636 => x"00000000",
+2637 => x"00000000",
+2638 => x"00000000",
+2639 => x"00000000",
+2640 => x"00000000",
+2641 => x"00000000",
+2642 => x"00000000",
+2643 => x"00000000",
+2644 => x"00000000",
+2645 => x"00000000",
+2646 => x"00000000",
+2647 => x"00000000",
+2648 => x"00000000",
+2649 => x"00000000",
+2650 => x"00000000",
+2651 => x"00000000",
+2652 => x"00000000",
+2653 => x"00000000",
+2654 => x"00000000",
+2655 => x"00000000",
+2656 => x"00000000",
+2657 => x"00000000",
+2658 => x"00000000",
+2659 => x"00000000",
+2660 => x"00000000",
+2661 => x"00000000",
+2662 => x"00000000",
+2663 => x"00000000",
+2664 => x"00000000",
+2665 => x"00000000",
+2666 => x"00000000",
+2667 => x"00000000",
+2668 => x"00000000",
+2669 => x"00000000",
+2670 => x"00000000",
+2671 => x"00000000",
+2672 => x"00000000",
+2673 => x"00000000",
+2674 => x"00000000",
+2675 => x"00000000",
+2676 => x"00000000",
+2677 => x"00000000",
+2678 => x"00000000",
+2679 => x"00000000",
+2680 => x"00000000",
+2681 => x"00000000",
+2682 => x"00000000",
+2683 => x"00000000",
+2684 => x"00000000",
+2685 => x"00000000",
+2686 => x"00000000",
+2687 => x"00000000",
+2688 => x"00000000",
+2689 => x"00000000",
+2690 => x"00000000",
+2691 => x"00000000",
+2692 => x"00000000",
+2693 => x"00000000",
+2694 => x"00000000",
+2695 => x"00000000",
+2696 => x"00000000",
+2697 => x"00000000",
+2698 => x"00000000",
+2699 => x"00000000",
+2700 => x"00000000",
+2701 => x"00000000",
+2702 => x"00000000",
+2703 => x"00000000",
+2704 => x"00000000",
+2705 => x"00000000",
+2706 => x"00000000",
+2707 => x"00000000",
+2708 => x"00000000",
+2709 => x"00000000",
+2710 => x"00000000",
+2711 => x"00000000",
+2712 => x"00000000",
+2713 => x"00000000",
+2714 => x"00000000",
+2715 => x"00000000",
+2716 => x"00000000",
+2717 => x"00000000",
+2718 => x"00000000",
+2719 => x"00000000",
+2720 => x"00000000",
+2721 => x"00000000",
+2722 => x"00000000",
+2723 => x"00000000",
+2724 => x"00000000",
+2725 => x"00000000",
+2726 => x"00000000",
+2727 => x"00000000",
+2728 => x"00000000",
+2729 => x"00000000",
+2730 => x"00000000",
+2731 => x"00000000",
+2732 => x"00000000",
+2733 => x"00000000",
+2734 => x"00000000",
+2735 => x"00000000",
+2736 => x"00000000",
+2737 => x"00000000",
+2738 => x"00000000",
+2739 => x"00000000",
+2740 => x"00000000",
+2741 => x"00000000",
+2742 => x"00000000",
+2743 => x"00000000",
+2744 => x"00000000",
+2745 => x"00000000",
+2746 => x"00000000",
+2747 => x"00000000",
+2748 => x"00000000",
+2749 => x"00000000",
+2750 => x"00000000",
+2751 => x"00000000",
+2752 => x"00000000",
+2753 => x"00000000",
+2754 => x"00000000",
+2755 => x"00000000",
+2756 => x"00000000",
+2757 => x"00000000",
+2758 => x"00000000",
+2759 => x"00000000",
+2760 => x"00000000",
+2761 => x"00000000",
+2762 => x"00000000",
+2763 => x"00000000",
+2764 => x"00000000",
+2765 => x"00000000",
+2766 => x"00000000",
+2767 => x"00000000",
+2768 => x"00000000",
+2769 => x"00000000",
+2770 => x"00000000",
+2771 => x"00000000",
+2772 => x"00000000",
+2773 => x"00000000",
+2774 => x"00000000",
+2775 => x"00000000",
+2776 => x"00000000",
+2777 => x"00000000",
+2778 => x"00000000",
+2779 => x"00000000",
+2780 => x"00000000",
+2781 => x"00000000",
+2782 => x"00000000",
+2783 => x"00000000",
+2784 => x"00000000",
+2785 => x"00000000",
+2786 => x"00000000",
+2787 => x"00000000",
+2788 => x"00000000",
+2789 => x"ffffffff",
+2790 => x"00000000",
+2791 => x"00020000",
+2792 => x"00000000",
+2793 => x"00000000",
+2794 => x"00002ba0",
+2795 => x"00002ba0",
+2796 => x"00002ba8",
+2797 => x"00002ba8",
+2798 => x"00002bb0",
+2799 => x"00002bb0",
+2800 => x"00002bb8",
+2801 => x"00002bb8",
+2802 => x"00002bc0",
+2803 => x"00002bc0",
+2804 => x"00002bc8",
+2805 => x"00002bc8",
+2806 => x"00002bd0",
+2807 => x"00002bd0",
+2808 => x"00002bd8",
+2809 => x"00002bd8",
+2810 => x"00002be0",
+2811 => x"00002be0",
+2812 => x"00002be8",
+2813 => x"00002be8",
+2814 => x"00002bf0",
+2815 => x"00002bf0",
+2816 => x"00002bf8",
+2817 => x"00002bf8",
+2818 => x"00002c00",
+2819 => x"00002c00",
+2820 => x"00002c08",
+2821 => x"00002c08",
+2822 => x"00002c10",
+2823 => x"00002c10",
+2824 => x"00002c18",
+2825 => x"00002c18",
+2826 => x"00002c20",
+2827 => x"00002c20",
+2828 => x"00002c28",
+2829 => x"00002c28",
+2830 => x"00002c30",
+2831 => x"00002c30",
+2832 => x"00002c38",
+2833 => x"00002c38",
+2834 => x"00002c40",
+2835 => x"00002c40",
+2836 => x"00002c48",
+2837 => x"00002c48",
+2838 => x"00002c50",
+2839 => x"00002c50",
+2840 => x"00002c58",
+2841 => x"00002c58",
+2842 => x"00002c60",
+2843 => x"00002c60",
+2844 => x"00002c68",
+2845 => x"00002c68",
+2846 => x"00002c70",
+2847 => x"00002c70",
+2848 => x"00002c78",
+2849 => x"00002c78",
+2850 => x"00002c80",
+2851 => x"00002c80",
+2852 => x"00002c88",
+2853 => x"00002c88",
+2854 => x"00002c90",
+2855 => x"00002c90",
+2856 => x"00002c98",
+2857 => x"00002c98",
+2858 => x"00002ca0",
+2859 => x"00002ca0",
+2860 => x"00002ca8",
+2861 => x"00002ca8",
+2862 => x"00002cb0",
+2863 => x"00002cb0",
+2864 => x"00002cb8",
+2865 => x"00002cb8",
+2866 => x"00002cc0",
+2867 => x"00002cc0",
+2868 => x"00002cc8",
+2869 => x"00002cc8",
+2870 => x"00002cd0",
+2871 => x"00002cd0",
+2872 => x"00002cd8",
+2873 => x"00002cd8",
+2874 => x"00002ce0",
+2875 => x"00002ce0",
+2876 => x"00002ce8",
+2877 => x"00002ce8",
+2878 => x"00002cf0",
+2879 => x"00002cf0",
+2880 => x"00002cf8",
+2881 => x"00002cf8",
+2882 => x"00002d00",
+2883 => x"00002d00",
+2884 => x"00002d08",
+2885 => x"00002d08",
+2886 => x"00002d10",
+2887 => x"00002d10",
+2888 => x"00002d18",
+2889 => x"00002d18",
+2890 => x"00002d20",
+2891 => x"00002d20",
+2892 => x"00002d28",
+2893 => x"00002d28",
+2894 => x"00002d30",
+2895 => x"00002d30",
+2896 => x"00002d38",
+2897 => x"00002d38",
+2898 => x"00002d40",
+2899 => x"00002d40",
+2900 => x"00002d48",
+2901 => x"00002d48",
+2902 => x"00002d50",
+2903 => x"00002d50",
+2904 => x"00002d58",
+2905 => x"00002d58",
+2906 => x"00002d60",
+2907 => x"00002d60",
+2908 => x"00002d68",
+2909 => x"00002d68",
+2910 => x"00002d70",
+2911 => x"00002d70",
+2912 => x"00002d78",
+2913 => x"00002d78",
+2914 => x"00002d80",
+2915 => x"00002d80",
+2916 => x"00002d88",
+2917 => x"00002d88",
+2918 => x"00002d90",
+2919 => x"00002d90",
+2920 => x"00002d98",
+2921 => x"00002d98",
+2922 => x"00002da0",
+2923 => x"00002da0",
+2924 => x"00002da8",
+2925 => x"00002da8",
+2926 => x"00002db0",
+2927 => x"00002db0",
+2928 => x"00002db8",
+2929 => x"00002db8",
+2930 => x"00002dc0",
+2931 => x"00002dc0",
+2932 => x"00002dc8",
+2933 => x"00002dc8",
+2934 => x"00002dd0",
+2935 => x"00002dd0",
+2936 => x"00002dd8",
+2937 => x"00002dd8",
+2938 => x"00002de0",
+2939 => x"00002de0",
+2940 => x"00002de8",
+2941 => x"00002de8",
+2942 => x"00002df0",
+2943 => x"00002df0",
+2944 => x"00002df8",
+2945 => x"00002df8",
+2946 => x"00002e00",
+2947 => x"00002e00",
+2948 => x"00002e08",
+2949 => x"00002e08",
+2950 => x"00002e10",
+2951 => x"00002e10",
+2952 => x"00002e18",
+2953 => x"00002e18",
+2954 => x"00002e20",
+2955 => x"00002e20",
+2956 => x"00002e28",
+2957 => x"00002e28",
+2958 => x"00002e30",
+2959 => x"00002e30",
+2960 => x"00002e38",
+2961 => x"00002e38",
+2962 => x"00002e40",
+2963 => x"00002e40",
+2964 => x"00002e48",
+2965 => x"00002e48",
+2966 => x"00002e50",
+2967 => x"00002e50",
+2968 => x"00002e58",
+2969 => x"00002e58",
+2970 => x"00002e60",
+2971 => x"00002e60",
+2972 => x"00002e68",
+2973 => x"00002e68",
+2974 => x"00002e70",
+2975 => x"00002e70",
+2976 => x"00002e78",
+2977 => x"00002e78",
+2978 => x"00002e80",
+2979 => x"00002e80",
+2980 => x"00002e88",
+2981 => x"00002e88",
+2982 => x"00002e90",
+2983 => x"00002e90",
+2984 => x"00002e98",
+2985 => x"00002e98",
+2986 => x"00002ea0",
+2987 => x"00002ea0",
+2988 => x"00002ea8",
+2989 => x"00002ea8",
+2990 => x"00002eb0",
+2991 => x"00002eb0",
+2992 => x"00002eb8",
+2993 => x"00002eb8",
+2994 => x"00002ec0",
+2995 => x"00002ec0",
+2996 => x"00002ec8",
+2997 => x"00002ec8",
+2998 => x"00002ed0",
+2999 => x"00002ed0",
+3000 => x"00002ed8",
+3001 => x"00002ed8",
+3002 => x"00002ee0",
+3003 => x"00002ee0",
+3004 => x"00002ee8",
+3005 => x"00002ee8",
+3006 => x"00002ef0",
+3007 => x"00002ef0",
+3008 => x"00002ef8",
+3009 => x"00002ef8",
+3010 => x"00002f00",
+3011 => x"00002f00",
+3012 => x"00002f08",
+3013 => x"00002f08",
+3014 => x"00002f10",
+3015 => x"00002f10",
+3016 => x"00002f18",
+3017 => x"00002f18",
+3018 => x"00002f20",
+3019 => x"00002f20",
+3020 => x"00002f28",
+3021 => x"00002f28",
+3022 => x"00002f30",
+3023 => x"00002f30",
+3024 => x"00002f38",
+3025 => x"00002f38",
+3026 => x"00002f40",
+3027 => x"00002f40",
+3028 => x"00002f48",
+3029 => x"00002f48",
+3030 => x"00002f50",
+3031 => x"00002f50",
+3032 => x"00002f58",
+3033 => x"00002f58",
+3034 => x"00002f60",
+3035 => x"00002f60",
+3036 => x"00002f68",
+3037 => x"00002f68",
+3038 => x"00002f70",
+3039 => x"00002f70",
+3040 => x"00002f78",
+3041 => x"00002f78",
+3042 => x"00002f80",
+3043 => x"00002f80",
+3044 => x"00002f88",
+3045 => x"00002f88",
+3046 => x"00002f90",
+3047 => x"00002f90",
+3048 => x"00002f98",
+3049 => x"00002f98",
+3050 => x"000027b8",
+3051 => x"ffffffff",
+3052 => x"00000000",
+3053 => x"ffffffff",
+3054 => x"00000000",
diff --git a/zpu/hdl/zpu4/test/interrupt/build.sh b/zpu/hdl/zpu4/test/interrupt/build.sh
new file mode 100755
index 0000000..3d617e9
--- /dev/null
+++ b/zpu/hdl/zpu4/test/interrupt/build.sh
@@ -0,0 +1,4 @@
+zpu-elf-gcc -O3 -phi `pwd`/int.c -o int.elf -Wl,--relax -Wl,--gc-sections -g
+zpu-elf-objdump --disassemble-all >int.dis int.elf
+zpu-elf-objcopy -O binary int.elf int.bin
+java -classpath ../../../../sw/simulator/zpusim.jar com.zylin.zpu.simulator.tools.MakeRam int.bin >int.ram
diff --git a/zpu/hdl/zpu4/test/interrupt/int.bin b/zpu/hdl/zpu4/test/interrupt/int.bin
new file mode 100644
index 0000000..282f53b
--- /dev/null
+++ b/zpu/hdl/zpu4/test/interrupt/int.bin
Binary files differ
diff --git a/zpu/hdl/zpu4/test/interrupt/int.c b/zpu/hdl/zpu4/test/interrupt/int.c
new file mode 100644
index 0000000..6ab28f7
--- /dev/null
+++ b/zpu/hdl/zpu4/test/interrupt/int.c
@@ -0,0 +1,40 @@
+/*
+ * Shows usage of interrupts. Goes along with zpu_core_small_wip.vhd.
+ */
+#include <stdio.h>
+
+
+volatile int counter;
+
+/* Example of single, fixed interval non-maskable, nested interrupt. The interrupt signal is
+ * held high for enough cycles to guarantee that it will be noticed, i.e. longer than
+ * any io access + 4 cycles roughly.
+ *
+ * Any non-trivial interrupt controller would have support for
+ * acknowledging interrupts(i.e. keep interrupts asserted until
+ * software acknowledges them via memory mapped IO).
+ */
+void _zpu_interrupt(void)
+{
+ /* interrupts are enabled so we need to finish up quickly,
+ * lest we will get infinite recursion!*/
+ counter++;
+}
+
+int main(int argc, char **argv)
+{
+ int t;
+ t=counter;
+ for (;;)
+ {
+ if (t==counter)
+ {
+ puts("No interrupt\n");
+ } else
+ {
+ puts("Got interrupt\n");
+ t=counter;
+ }
+ }
+
+}
diff --git a/zpu/hdl/zpu4/test/interrupt/int.elf b/zpu/hdl/zpu4/test/interrupt/int.elf
new file mode 100644
index 0000000..346d148
--- /dev/null
+++ b/zpu/hdl/zpu4/test/interrupt/int.elf
Binary files differ
diff --git a/zpu/hdl/zpu4/test/interrupt/int.ram b/zpu/hdl/zpu4/test/interrupt/int.ram
new file mode 100644
index 0000000..6751ec2
--- /dev/null
+++ b/zpu/hdl/zpu4/test/interrupt/int.ram
@@ -0,0 +1,3057 @@
+0 => x"0b0b0b0b",
+1 => x"82700b0b",
+2 => x"80cfe00c",
+3 => x"3a0b0b80",
+4 => x"c6e00400",
+5 => x"00000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"0b8af02d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
+17 => x"72830609",
+18 => x"81058205",
+19 => x"832b2a83",
+20 => x"ffff0652",
+21 => x"04000000",
+22 => x"00000000",
+23 => x"00000000",
+24 => x"71fd0608",
+25 => x"83ffff73",
+26 => x"83060981",
+27 => x"05820583",
+28 => x"2b2b0906",
+29 => x"7383ffff",
+30 => x"0b0b0b0b",
+31 => x"83a70400",
+32 => x"72098105",
+33 => x"72057373",
+34 => x"09060906",
+35 => x"73097306",
+36 => x"070a8106",
+37 => x"53510400",
+38 => x"00000000",
+39 => x"00000000",
+40 => x"72722473",
+41 => x"732e0753",
+42 => x"51040000",
+43 => x"00000000",
+44 => x"00000000",
+45 => x"00000000",
+46 => x"00000000",
+47 => x"00000000",
+48 => x"71737109",
+49 => x"71068106",
+50 => x"30720a10",
+51 => x"0a720a10",
+52 => x"0a31050a",
+53 => x"81065151",
+54 => x"53510400",
+55 => x"00000000",
+56 => x"72722673",
+57 => x"732e0753",
+58 => x"51040000",
+59 => x"00000000",
+60 => x"00000000",
+61 => x"00000000",
+62 => x"00000000",
+63 => x"00000000",
+64 => x"00000000",
+65 => x"00000000",
+66 => x"00000000",
+67 => x"00000000",
+68 => x"00000000",
+69 => x"00000000",
+70 => x"00000000",
+71 => x"00000000",
+72 => x"0b0b0b88",
+73 => x"c4040000",
+74 => x"00000000",
+75 => x"00000000",
+76 => x"00000000",
+77 => x"00000000",
+78 => x"00000000",
+79 => x"00000000",
+80 => x"720a722b",
+81 => x"0a535104",
+82 => x"00000000",
+83 => x"00000000",
+84 => x"00000000",
+85 => x"00000000",
+86 => x"00000000",
+87 => x"00000000",
+88 => x"72729f06",
+89 => x"0981050b",
+90 => x"0b0b88a7",
+91 => x"05040000",
+92 => x"00000000",
+93 => x"00000000",
+94 => x"00000000",
+95 => x"00000000",
+96 => x"72722aff",
+97 => x"739f062a",
+98 => x"0974090a",
+99 => x"8106ff05",
+100 => x"06075351",
+101 => x"04000000",
+102 => x"00000000",
+103 => x"00000000",
+104 => x"71715351",
+105 => x"020d0406",
+106 => x"73830609",
+107 => x"81058205",
+108 => x"832b0b2b",
+109 => x"0772fc06",
+110 => x"0c515104",
+111 => x"00000000",
+112 => x"72098105",
+113 => x"72050970",
+114 => x"81050906",
+115 => x"0a810653",
+116 => x"51040000",
+117 => x"00000000",
+118 => x"00000000",
+119 => x"00000000",
+120 => x"72098105",
+121 => x"72050970",
+122 => x"81050906",
+123 => x"0a098106",
+124 => x"53510400",
+125 => x"00000000",
+126 => x"00000000",
+127 => x"00000000",
+128 => x"71098105",
+129 => x"52040000",
+130 => x"00000000",
+131 => x"00000000",
+132 => x"00000000",
+133 => x"00000000",
+134 => x"00000000",
+135 => x"00000000",
+136 => x"72720981",
+137 => x"05055351",
+138 => x"04000000",
+139 => x"00000000",
+140 => x"00000000",
+141 => x"00000000",
+142 => x"00000000",
+143 => x"00000000",
+144 => x"72097206",
+145 => x"73730906",
+146 => x"07535104",
+147 => x"00000000",
+148 => x"00000000",
+149 => x"00000000",
+150 => x"00000000",
+151 => x"00000000",
+152 => x"71fc0608",
+153 => x"72830609",
+154 => x"81058305",
+155 => x"1010102a",
+156 => x"81ff0652",
+157 => x"04000000",
+158 => x"00000000",
+159 => x"00000000",
+160 => x"71fc0608",
+161 => x"0b0b80cf",
+162 => x"cc738306",
+163 => x"10100508",
+164 => x"060b0b0b",
+165 => x"88aa0400",
+166 => x"00000000",
+167 => x"00000000",
+168 => x"80088408",
+169 => x"88087575",
+170 => x"0b0b0b8b",
+171 => x"ab2d5050",
+172 => x"80085688",
+173 => x"0c840c80",
+174 => x"0c510400",
+175 => x"00000000",
+176 => x"80088408",
+177 => x"88087575",
+178 => x"0b0b0b8b",
+179 => x"ef2d5050",
+180 => x"80085688",
+181 => x"0c840c80",
+182 => x"0c510400",
+183 => x"00000000",
+184 => x"72097081",
+185 => x"0509060a",
+186 => x"8106ff05",
+187 => x"70547106",
+188 => x"73097274",
+189 => x"05ff0506",
+190 => x"07515151",
+191 => x"04000000",
+192 => x"72097081",
+193 => x"0509060a",
+194 => x"098106ff",
+195 => x"05705471",
+196 => x"06730972",
+197 => x"7405ff05",
+198 => x"06075151",
+199 => x"51040000",
+200 => x"05ff0504",
+201 => x"00000000",
+202 => x"00000000",
+203 => x"00000000",
+204 => x"00000000",
+205 => x"00000000",
+206 => x"00000000",
+207 => x"00000000",
+208 => x"810b0b0b",
+209 => x"80cfdc0c",
+210 => x"51040000",
+211 => x"00000000",
+212 => x"00000000",
+213 => x"00000000",
+214 => x"00000000",
+215 => x"00000000",
+216 => x"71810552",
+217 => x"04000000",
+218 => x"00000000",
+219 => x"00000000",
+220 => x"00000000",
+221 => x"00000000",
+222 => x"00000000",
+223 => x"00000000",
+224 => x"00000000",
+225 => x"00000000",
+226 => x"00000000",
+227 => x"00000000",
+228 => x"00000000",
+229 => x"00000000",
+230 => x"00000000",
+231 => x"00000000",
+232 => x"02840572",
+233 => x"10100552",
+234 => x"04000000",
+235 => x"00000000",
+236 => x"00000000",
+237 => x"00000000",
+238 => x"00000000",
+239 => x"00000000",
+240 => x"00000000",
+241 => x"00000000",
+242 => x"00000000",
+243 => x"00000000",
+244 => x"00000000",
+245 => x"00000000",
+246 => x"00000000",
+247 => x"00000000",
+248 => x"717105ff",
+249 => x"05715351",
+250 => x"020d0400",
+251 => x"00000000",
+252 => x"00000000",
+253 => x"00000000",
+254 => x"00000000",
+255 => x"00000000",
+256 => x"82c53f80",
+257 => x"c6e63f04",
+258 => x"10101010",
+259 => x"10101010",
+260 => x"10101010",
+261 => x"10101010",
+262 => x"10101010",
+263 => x"10101010",
+264 => x"10101010",
+265 => x"10101053",
+266 => x"51047381",
+267 => x"ff067383",
+268 => x"06098105",
+269 => x"83051010",
+270 => x"102b0772",
+271 => x"fc060c51",
+272 => x"51043c04",
+273 => x"72728072",
+274 => x"8106ff05",
+275 => x"09720605",
+276 => x"71105272",
+277 => x"0a100a53",
+278 => x"72ed3851",
+279 => x"51535104",
+280 => x"fe3d0d0b",
+281 => x"0b80dfc8",
+282 => x"08538413",
+283 => x"0870882a",
+284 => x"70810651",
+285 => x"52527080",
+286 => x"2ef03871",
+287 => x"81ff0680",
+288 => x"0c843d0d",
+289 => x"04ff3d0d",
+290 => x"0b0b80df",
+291 => x"c8085271",
+292 => x"0870882a",
+293 => x"81327081",
+294 => x"06515151",
+295 => x"70f13873",
+296 => x"720c833d",
+297 => x"0d0480cf",
+298 => x"dc08802e",
+299 => x"a43880cf",
+300 => x"e008822e",
+301 => x"bd388380",
+302 => x"800b0b0b",
+303 => x"80dfc80c",
+304 => x"82a0800b",
+305 => x"80dfcc0c",
+306 => x"8290800b",
+307 => x"80dfd00c",
+308 => x"04f88080",
+309 => x"80a40b0b",
+310 => x"0b80dfc8",
+311 => x"0cf88080",
+312 => x"82800b80",
+313 => x"dfcc0cf8",
+314 => x"80808480",
+315 => x"0b80dfd0",
+316 => x"0c0480c0",
+317 => x"a8808c0b",
+318 => x"0b0b80df",
+319 => x"c80c80c0",
+320 => x"a880940b",
+321 => x"80dfcc0c",
+322 => x"0b0b80cf",
+323 => x"980b80df",
+324 => x"d00c0470",
+325 => x"7080dfd4",
+326 => x"335170a7",
+327 => x"3880cfe8",
+328 => x"08700852",
+329 => x"5270802e",
+330 => x"94388412",
+331 => x"80cfe80c",
+332 => x"702d80cf",
+333 => x"e8087008",
+334 => x"525270ee",
+335 => x"38810b80",
+336 => x"dfd43450",
+337 => x"50040470",
+338 => x"0b0b80df",
+339 => x"c408802e",
+340 => x"8e380b0b",
+341 => x"0b0b800b",
+342 => x"802e0981",
+343 => x"06833850",
+344 => x"040b0b80",
+345 => x"dfc4510b",
+346 => x"0b0bf594",
+347 => x"3f500404",
+348 => x"803d0d80",
+349 => x"dfe00881",
+350 => x"1180dfe0",
+351 => x"0c51823d",
+352 => x"0d04fe3d",
+353 => x"0d80dfe0",
+354 => x"085380df",
+355 => x"e0085272",
+356 => x"722e8f38",
+357 => x"80cf9c51",
+358 => x"82b03f80",
+359 => x"dfe00853",
+360 => x"e93980cf",
+361 => x"ac5182a2",
+362 => x"3fe039fb",
+363 => x"3d0d7779",
+364 => x"55558056",
+365 => x"757524ab",
+366 => x"38807424",
+367 => x"9d388053",
+368 => x"73527451",
+369 => x"80e13f80",
+370 => x"08547580",
+371 => x"2e853880",
+372 => x"08305473",
+373 => x"800c873d",
+374 => x"0d047330",
+375 => x"76813257",
+376 => x"54dc3974",
+377 => x"30558156",
+378 => x"738025d2",
+379 => x"38ec39fa",
+380 => x"3d0d787a",
+381 => x"57558057",
+382 => x"767524a4",
+383 => x"38759f2c",
+384 => x"54815375",
+385 => x"74327431",
+386 => x"5274519b",
+387 => x"3f800854",
+388 => x"76802e85",
+389 => x"38800830",
+390 => x"5473800c",
+391 => x"883d0d04",
+392 => x"74305581",
+393 => x"57d739fc",
+394 => x"3d0d7678",
+395 => x"53548153",
+396 => x"80747326",
+397 => x"52557280",
+398 => x"2e983870",
+399 => x"802eab38",
+400 => x"807224a6",
+401 => x"38711073",
+402 => x"10757226",
+403 => x"53545272",
+404 => x"ea387351",
+405 => x"78833874",
+406 => x"5170800c",
+407 => x"863d0d04",
+408 => x"720a100a",
+409 => x"720a100a",
+410 => x"53537280",
+411 => x"2ee43871",
+412 => x"7426ed38",
+413 => x"73723175",
+414 => x"7407740a",
+415 => x"100a740a",
+416 => x"100a5555",
+417 => x"5654e339",
+418 => x"f73d0d7c",
+419 => x"70525380",
+420 => x"fd3f7254",
+421 => x"8008550b",
+422 => x"0b80cfb8",
+423 => x"56815780",
+424 => x"0881055a",
+425 => x"8b3de411",
+426 => x"59538259",
+427 => x"f413527b",
+428 => x"88110852",
+429 => x"5381b43f",
+430 => x"80083070",
+431 => x"8008079f",
+432 => x"2c8a0780",
+433 => x"0c538b3d",
+434 => x"0d04f63d",
+435 => x"0d7c80cf",
+436 => x"ec087153",
+437 => x"5553b73f",
+438 => x"72558008",
+439 => x"560b0b80",
+440 => x"cfb85781",
+441 => x"58800881",
+442 => x"055b8c3d",
+443 => x"e4115a53",
+444 => x"825af413",
+445 => x"52881408",
+446 => x"5180f03f",
+447 => x"80083070",
+448 => x"8008079f",
+449 => x"2c8a0780",
+450 => x"0c548c3d",
+451 => x"0d047070",
+452 => x"70707570",
+453 => x"71830653",
+454 => x"555270b4",
+455 => x"38717008",
+456 => x"7009f7fb",
+457 => x"fdff1206",
+458 => x"f8848281",
+459 => x"80065452",
+460 => x"53719b38",
+461 => x"84137008",
+462 => x"7009f7fb",
+463 => x"fdff1206",
+464 => x"f8848281",
+465 => x"80065452",
+466 => x"5371802e",
+467 => x"e7387252",
+468 => x"71335372",
+469 => x"802e8a38",
+470 => x"81127033",
+471 => x"545272f8",
+472 => x"38717431",
+473 => x"800c5050",
+474 => x"505004f2",
+475 => x"3d0d6062",
+476 => x"88110870",
+477 => x"58565f5a",
+478 => x"73802e81",
+479 => x"8c388c1a",
+480 => x"2270832a",
+481 => x"81328106",
+482 => x"56587486",
+483 => x"38901a08",
+484 => x"91387951",
+485 => x"90b73fff",
+486 => x"55800880",
+487 => x"ec388c1a",
+488 => x"22587d08",
+489 => x"55807883",
+490 => x"ffff0670",
+491 => x"0a100a81",
+492 => x"06415c57",
+493 => x"7e772e80",
+494 => x"d7387690",
+495 => x"38740884",
+496 => x"16088817",
+497 => x"57585676",
+498 => x"802ef238",
+499 => x"76548880",
+500 => x"77278438",
+501 => x"88805473",
+502 => x"5375529c",
+503 => x"1a0851a4",
+504 => x"1a085877",
+505 => x"2d800b80",
+506 => x"082582e0",
+507 => x"38800816",
+508 => x"77800831",
+509 => x"7f880508",
+510 => x"80083170",
+511 => x"6188050c",
+512 => x"5b585678",
+513 => x"ffb43880",
+514 => x"5574800c",
+515 => x"903d0d04",
+516 => x"7a813281",
+517 => x"06774056",
+518 => x"75802e81",
+519 => x"bd387690",
+520 => x"38740884",
+521 => x"16088817",
+522 => x"57585976",
+523 => x"802ef238",
+524 => x"881a0878",
+525 => x"83ffff06",
+526 => x"70892a81",
+527 => x"06565956",
+528 => x"73802e82",
+529 => x"f8387577",
+530 => x"278b3877",
+531 => x"872a8106",
+532 => x"5c7b82b5",
+533 => x"38767627",
+534 => x"83387656",
+535 => x"75537852",
+536 => x"79085185",
+537 => x"833f881a",
+538 => x"08763188",
+539 => x"1b0c7908",
+540 => x"167a0c76",
+541 => x"56751977",
+542 => x"77317f88",
+543 => x"05087831",
+544 => x"70618805",
+545 => x"0c415859",
+546 => x"7e802efe",
+547 => x"fa388c1a",
+548 => x"2258ff8a",
+549 => x"39787954",
+550 => x"7c537b52",
+551 => x"5684c93f",
+552 => x"881a0879",
+553 => x"31881b0c",
+554 => x"7908197a",
+555 => x"0c7c7631",
+556 => x"5d7c8e38",
+557 => x"79518ff2",
+558 => x"3f800881",
+559 => x"8f388008",
+560 => x"5f751c77",
+561 => x"77317f88",
+562 => x"05087831",
+563 => x"70618805",
+564 => x"0c5d585c",
+565 => x"7a802efe",
+566 => x"ae387681",
+567 => x"83387408",
+568 => x"84160888",
+569 => x"1757585c",
+570 => x"76802ef2",
+571 => x"3876538a",
+572 => x"527b5182",
+573 => x"d33f8008",
+574 => x"7c318105",
+575 => x"5d800884",
+576 => x"3881175d",
+577 => x"815f7c59",
+578 => x"767d2783",
+579 => x"38765994",
+580 => x"1a08881b",
+581 => x"08115758",
+582 => x"807a085c",
+583 => x"54901a08",
+584 => x"7b278338",
+585 => x"81547579",
+586 => x"25843873",
+587 => x"ba387779",
+588 => x"24fee238",
+589 => x"77537b52",
+590 => x"9c1a0851",
+591 => x"a41a0859",
+592 => x"782d8008",
+593 => x"56800880",
+594 => x"24fee238",
+595 => x"8c1a2280",
+596 => x"c0075e7d",
+597 => x"8c1b23ff",
+598 => x"5574800c",
+599 => x"903d0d04",
+600 => x"7effa338",
+601 => x"ff873975",
+602 => x"537b527a",
+603 => x"5182f93f",
+604 => x"7908167a",
+605 => x"0c79518e",
+606 => x"b13f8008",
+607 => x"cf387c76",
+608 => x"315d7cfe",
+609 => x"bc38feac",
+610 => x"39901a08",
+611 => x"7a087131",
+612 => x"78117056",
+613 => x"5a575280",
+614 => x"cfec0851",
+615 => x"84943f80",
+616 => x"08802eff",
+617 => x"a7388008",
+618 => x"901b0c80",
+619 => x"08167a0c",
+620 => x"77941b0c",
+621 => x"76881b0c",
+622 => x"7656fd99",
+623 => x"39790858",
+624 => x"901a0878",
+625 => x"27833881",
+626 => x"54757727",
+627 => x"843873b3",
+628 => x"38941a08",
+629 => x"54737726",
+630 => x"80d33873",
+631 => x"5378529c",
+632 => x"1a0851a4",
+633 => x"1a085877",
+634 => x"2d800856",
+635 => x"80088024",
+636 => x"fd83388c",
+637 => x"1a2280c0",
+638 => x"075e7d8c",
+639 => x"1b23ff55",
+640 => x"fed73975",
+641 => x"53785277",
+642 => x"5181dd3f",
+643 => x"7908167a",
+644 => x"0c79518d",
+645 => x"953f8008",
+646 => x"802efcd9",
+647 => x"388c1a22",
+648 => x"80c0075e",
+649 => x"7d8c1b23",
+650 => x"ff55fead",
+651 => x"39767754",
+652 => x"79537852",
+653 => x"5681b13f",
+654 => x"881a0877",
+655 => x"31881b0c",
+656 => x"7908177a",
+657 => x"0cfcae39",
+658 => x"fa3d0d7a",
+659 => x"79028805",
+660 => x"a7053355",
+661 => x"53548374",
+662 => x"2780df38",
+663 => x"71830651",
+664 => x"7080d738",
+665 => x"71715755",
+666 => x"83517582",
+667 => x"802913ff",
+668 => x"12525670",
+669 => x"8025f338",
+670 => x"837427bc",
+671 => x"38740876",
+672 => x"327009f7",
+673 => x"fbfdff12",
+674 => x"06f88482",
+675 => x"81800651",
+676 => x"5170802e",
+677 => x"98387451",
+678 => x"80527033",
+679 => x"5772772e",
+680 => x"b9388111",
+681 => x"81135351",
+682 => x"837227ee",
+683 => x"38fc1484",
+684 => x"16565473",
+685 => x"8326c638",
+686 => x"7452ff14",
+687 => x"5170ff2e",
+688 => x"97387133",
+689 => x"5472742e",
+690 => x"98388112",
+691 => x"ff125252",
+692 => x"70ff2e09",
+693 => x"8106eb38",
+694 => x"80517080",
+695 => x"0c883d0d",
+696 => x"0471800c",
+697 => x"883d0d04",
+698 => x"fa3d0d78",
+699 => x"7a7c7272",
+700 => x"72595755",
+701 => x"58565774",
+702 => x"7727b238",
+703 => x"75155176",
+704 => x"7127aa38",
+705 => x"707618ff",
+706 => x"18535353",
+707 => x"70ff2e96",
+708 => x"38ff12ff",
+709 => x"14545272",
+710 => x"337234ff",
+711 => x"115170ff",
+712 => x"2e098106",
+713 => x"ec387680",
+714 => x"0c883d0d",
+715 => x"048f7627",
+716 => x"80e63874",
+717 => x"77078306",
+718 => x"517080dc",
+719 => x"38767552",
+720 => x"53707084",
+721 => x"05520873",
+722 => x"70840555",
+723 => x"0c727170",
+724 => x"84055308",
+725 => x"71708405",
+726 => x"530c7170",
+727 => x"84055308",
+728 => x"71708405",
+729 => x"530c7170",
+730 => x"84055308",
+731 => x"71708405",
+732 => x"530cf015",
+733 => x"5553738f",
+734 => x"26c73883",
+735 => x"74279538",
+736 => x"70708405",
+737 => x"52087370",
+738 => x"8405550c",
+739 => x"fc145473",
+740 => x"8326ed38",
+741 => x"72715452",
+742 => x"ff145170",
+743 => x"ff2eff86",
+744 => x"38727081",
+745 => x"05543372",
+746 => x"70810554",
+747 => x"34ff1151",
+748 => x"ea39ef3d",
+749 => x"0d636567",
+750 => x"405d427b",
+751 => x"802e8582",
+752 => x"386151a9",
+753 => x"e73ff81c",
+754 => x"70841208",
+755 => x"70fc0670",
+756 => x"628b0570",
+757 => x"f8064159",
+758 => x"455c5f41",
+759 => x"57967427",
+760 => x"82c53880",
+761 => x"7b247e7c",
+762 => x"26075880",
+763 => x"5477742e",
+764 => x"09810682",
+765 => x"ab38787b",
+766 => x"2581fe38",
+767 => x"781780d7",
+768 => x"a80b8805",
+769 => x"085b5679",
+770 => x"762e84c5",
+771 => x"38841608",
+772 => x"70fe0617",
+773 => x"84110881",
+774 => x"06415555",
+775 => x"7e828d38",
+776 => x"74fc0658",
+777 => x"79762e84",
+778 => x"e3387818",
+779 => x"5f7e7b25",
+780 => x"81ff387c",
+781 => x"81065473",
+782 => x"82c13876",
+783 => x"77083184",
+784 => x"1108fc06",
+785 => x"56577580",
+786 => x"2e913879",
+787 => x"762e84f0",
+788 => x"38741819",
+789 => x"58777b25",
+790 => x"84913876",
+791 => x"802e829b",
+792 => x"38781556",
+793 => x"7a762482",
+794 => x"92388c17",
+795 => x"08881808",
+796 => x"718c120c",
+797 => x"88120c5e",
+798 => x"75598817",
+799 => x"61fc055b",
+800 => x"5679a426",
+801 => x"85ff387b",
+802 => x"76595593",
+803 => x"7a2780c9",
+804 => x"387b7084",
+805 => x"055d087c",
+806 => x"56760c74",
+807 => x"70840556",
+808 => x"088c180c",
+809 => x"9017589b",
+810 => x"7a27ae38",
+811 => x"74708405",
+812 => x"5608780c",
+813 => x"74708405",
+814 => x"56089418",
+815 => x"0c981758",
+816 => x"a37a2795",
+817 => x"38747084",
+818 => x"05560878",
+819 => x"0c747084",
+820 => x"0556089c",
+821 => x"180ca017",
+822 => x"58747084",
+823 => x"05560875",
+824 => x"5f787084",
+825 => x"055a0c77",
+826 => x"7e708405",
+827 => x"40087170",
+828 => x"8405530c",
+829 => x"7e08710c",
+830 => x"5d787b31",
+831 => x"56758f26",
+832 => x"80c93884",
+833 => x"17088106",
+834 => x"79078418",
+835 => x"0c781784",
+836 => x"11088107",
+837 => x"84120c5b",
+838 => x"6151a791",
+839 => x"3f881754",
+840 => x"73800c93",
+841 => x"3d0d0490",
+842 => x"5bfdb839",
+843 => x"7756fe83",
+844 => x"398c1608",
+845 => x"88170871",
+846 => x"8c120c88",
+847 => x"120c587e",
+848 => x"707c3157",
+849 => x"598f7627",
+850 => x"ffb9387a",
+851 => x"17841808",
+852 => x"81067c07",
+853 => x"84190c76",
+854 => x"81078412",
+855 => x"0c761184",
+856 => x"11088107",
+857 => x"84120c5b",
+858 => x"88055261",
+859 => x"518fda3f",
+860 => x"6151a6b9",
+861 => x"3f881754",
+862 => x"ffa6397d",
+863 => x"52615197",
+864 => x"d73f8008",
+865 => x"5a800880",
+866 => x"2e81ab38",
+867 => x"8008f805",
+868 => x"60840508",
+869 => x"fe066105",
+870 => x"58557477",
+871 => x"2e83f238",
+872 => x"fc195877",
+873 => x"a42681b0",
+874 => x"387b8008",
+875 => x"56579378",
+876 => x"2780dc38",
+877 => x"7b707084",
+878 => x"05520880",
+879 => x"08708405",
+880 => x"800c0c80",
+881 => x"08717084",
+882 => x"0553085d",
+883 => x"567b7670",
+884 => x"8405580c",
+885 => x"579b7827",
+886 => x"b6387670",
+887 => x"84055808",
+888 => x"75708405",
+889 => x"570c7670",
+890 => x"84055808",
+891 => x"75708405",
+892 => x"570ca378",
+893 => x"27993876",
+894 => x"70840558",
+895 => x"08757084",
+896 => x"05570c76",
+897 => x"70840558",
+898 => x"08757084",
+899 => x"05570c76",
+900 => x"70840558",
+901 => x"08775e75",
+902 => x"70840557",
+903 => x"0c747d70",
+904 => x"84055f08",
+905 => x"71708405",
+906 => x"530c7d08",
+907 => x"710c5f7b",
+908 => x"5261518e",
+909 => x"943f6151",
+910 => x"a4f33f79",
+911 => x"800c933d",
+912 => x"0d047d52",
+913 => x"61519690",
+914 => x"3f800880",
+915 => x"0c933d0d",
+916 => x"04841608",
+917 => x"55fbc939",
+918 => x"77537b52",
+919 => x"800851a2",
+920 => x"a53f7b52",
+921 => x"61518de1",
+922 => x"3fcc398c",
+923 => x"16088817",
+924 => x"08718c12",
+925 => x"0c88120c",
+926 => x"5d8c1708",
+927 => x"88180871",
+928 => x"8c120c88",
+929 => x"120c5977",
+930 => x"59fbef39",
+931 => x"7818901c",
+932 => x"40557e75",
+933 => x"24fb9c38",
+934 => x"7a177080",
+935 => x"d7a80b88",
+936 => x"050c757c",
+937 => x"31810784",
+938 => x"120c5684",
+939 => x"17088106",
+940 => x"7b078418",
+941 => x"0c6151a3",
+942 => x"f43f8817",
+943 => x"54fce139",
+944 => x"74181990",
+945 => x"1c5e5a7c",
+946 => x"7a24fb8f",
+947 => x"388c1708",
+948 => x"88180871",
+949 => x"8c120c88",
+950 => x"120c5e88",
+951 => x"1761fc05",
+952 => x"575975a4",
+953 => x"2681b638",
+954 => x"7b795955",
+955 => x"93762780",
+956 => x"c9387b70",
+957 => x"84055d08",
+958 => x"7c56790c",
+959 => x"74708405",
+960 => x"56088c18",
+961 => x"0c901758",
+962 => x"9b7627ae",
+963 => x"38747084",
+964 => x"05560878",
+965 => x"0c747084",
+966 => x"05560894",
+967 => x"180c9817",
+968 => x"58a37627",
+969 => x"95387470",
+970 => x"84055608",
+971 => x"780c7470",
+972 => x"84055608",
+973 => x"9c180ca0",
+974 => x"17587470",
+975 => x"84055608",
+976 => x"75417870",
+977 => x"84055a0c",
+978 => x"77607084",
+979 => x"05420871",
+980 => x"70840553",
+981 => x"0c600871",
+982 => x"0c5e7a17",
+983 => x"7080d7a8",
+984 => x"0b88050c",
+985 => x"7a7c3181",
+986 => x"0784120c",
+987 => x"58841708",
+988 => x"81067b07",
+989 => x"84180c61",
+990 => x"51a2b23f",
+991 => x"78547380",
+992 => x"0c933d0d",
+993 => x"0479537b",
+994 => x"5275519f",
+995 => x"f93ffae9",
+996 => x"39841508",
+997 => x"fc061960",
+998 => x"5859fadd",
+999 => x"3975537b",
+1000 => x"5278519f",
+1001 => x"e13f7a17",
+1002 => x"7080d7a8",
+1003 => x"0b88050c",
+1004 => x"7a7c3181",
+1005 => x"0784120c",
+1006 => x"58841708",
+1007 => x"81067b07",
+1008 => x"84180c61",
+1009 => x"51a1e63f",
+1010 => x"7854ffb2",
+1011 => x"39fa3d0d",
+1012 => x"7880cfec",
+1013 => x"085455b8",
+1014 => x"1308802e",
+1015 => x"81af388c",
+1016 => x"15227083",
+1017 => x"ffff0670",
+1018 => x"832a8132",
+1019 => x"81065555",
+1020 => x"5672802e",
+1021 => x"80da3873",
+1022 => x"842a8132",
+1023 => x"810657ff",
+1024 => x"537680f2",
+1025 => x"3873822a",
+1026 => x"81065473",
+1027 => x"802eb938",
+1028 => x"b0150854",
+1029 => x"73802e9c",
+1030 => x"3880c015",
+1031 => x"5373732e",
+1032 => x"8f387352",
+1033 => x"80cfec08",
+1034 => x"518a9e3f",
+1035 => x"8c152256",
+1036 => x"76b0160c",
+1037 => x"75db0657",
+1038 => x"768c1623",
+1039 => x"800b8416",
+1040 => x"0c901508",
+1041 => x"750c7656",
+1042 => x"75880754",
+1043 => x"738c1623",
+1044 => x"90150880",
+1045 => x"2ebf388c",
+1046 => x"15227081",
+1047 => x"06555373",
+1048 => x"9c38720a",
+1049 => x"100a8106",
+1050 => x"56758538",
+1051 => x"94150854",
+1052 => x"7388160c",
+1053 => x"80537280",
+1054 => x"0c883d0d",
+1055 => x"04800b88",
+1056 => x"160c9415",
+1057 => x"08309816",
+1058 => x"0c8053ea",
+1059 => x"39725182",
+1060 => x"a63ffecb",
+1061 => x"3974518f",
+1062 => x"bc3f8c15",
+1063 => x"22708106",
+1064 => x"55537380",
+1065 => x"2effbb38",
+1066 => x"d439f83d",
+1067 => x"0d7a5776",
+1068 => x"802e8197",
+1069 => x"3880cfec",
+1070 => x"0854b814",
+1071 => x"08802e80",
+1072 => x"eb388c17",
+1073 => x"2270902b",
+1074 => x"70902c70",
+1075 => x"832a8132",
+1076 => x"81065b5b",
+1077 => x"57557780",
+1078 => x"cb389017",
+1079 => x"08567580",
+1080 => x"2e80c138",
+1081 => x"76087631",
+1082 => x"76780c79",
+1083 => x"83065555",
+1084 => x"73853894",
+1085 => x"17085877",
+1086 => x"88180c80",
+1087 => x"7525a538",
+1088 => x"74537552",
+1089 => x"9c170851",
+1090 => x"a4170854",
+1091 => x"732d800b",
+1092 => x"80082580",
+1093 => x"c9388008",
+1094 => x"16758008",
+1095 => x"31565674",
+1096 => x"8024dd38",
+1097 => x"800b800c",
+1098 => x"8a3d0d04",
+1099 => x"73518187",
+1100 => x"3f8c1722",
+1101 => x"70902b70",
+1102 => x"902c7083",
+1103 => x"2a813281",
+1104 => x"065b5b57",
+1105 => x"5577dd38",
+1106 => x"ff9039a1",
+1107 => x"aa5280cf",
+1108 => x"ec08518c",
+1109 => x"d03f8008",
+1110 => x"800c8a3d",
+1111 => x"0d048c17",
+1112 => x"2280c007",
+1113 => x"58778c18",
+1114 => x"23ff0b80",
+1115 => x"0c8a3d0d",
+1116 => x"04fa3d0d",
+1117 => x"797080dc",
+1118 => x"298c1154",
+1119 => x"7a535657",
+1120 => x"8fd63f80",
+1121 => x"08800855",
+1122 => x"56800880",
+1123 => x"2ea23880",
+1124 => x"088c0554",
+1125 => x"800b8008",
+1126 => x"0c768008",
+1127 => x"84050c73",
+1128 => x"80088805",
+1129 => x"0c745380",
+1130 => x"5273519c",
+1131 => x"f53f7554",
+1132 => x"73800c88",
+1133 => x"3d0d0470",
+1134 => x"707074a8",
+1135 => x"f60bbc12",
+1136 => x"0c53810b",
+1137 => x"b8140c80",
+1138 => x"0b84dc14",
+1139 => x"0c830b84",
+1140 => x"e0140c84",
+1141 => x"e81384e4",
+1142 => x"140c8413",
+1143 => x"08518070",
+1144 => x"720c7084",
+1145 => x"130c7088",
+1146 => x"130c5284",
+1147 => x"0b8c1223",
+1148 => x"718e1223",
+1149 => x"7190120c",
+1150 => x"7194120c",
+1151 => x"7198120c",
+1152 => x"709c120c",
+1153 => x"80c1e50b",
+1154 => x"a0120c80",
+1155 => x"c2b10ba4",
+1156 => x"120c80c3",
+1157 => x"ad0ba812",
+1158 => x"0c80c3fe",
+1159 => x"0bac120c",
+1160 => x"88130872",
+1161 => x"710c7284",
+1162 => x"120c7288",
+1163 => x"120c5189",
+1164 => x"0b8c1223",
+1165 => x"810b8e12",
+1166 => x"23719012",
+1167 => x"0c719412",
+1168 => x"0c719812",
+1169 => x"0c709c12",
+1170 => x"0c80c1e5",
+1171 => x"0ba0120c",
+1172 => x"80c2b10b",
+1173 => x"a4120c80",
+1174 => x"c3ad0ba8",
+1175 => x"120c80c3",
+1176 => x"fe0bac12",
+1177 => x"0c8c1308",
+1178 => x"72710c72",
+1179 => x"84120c72",
+1180 => x"88120c51",
+1181 => x"8a0b8c12",
+1182 => x"23820b8e",
+1183 => x"12237190",
+1184 => x"120c7194",
+1185 => x"120c7198",
+1186 => x"120c709c",
+1187 => x"120c80c1",
+1188 => x"e50ba012",
+1189 => x"0c80c2b1",
+1190 => x"0ba4120c",
+1191 => x"80c3ad0b",
+1192 => x"a8120c80",
+1193 => x"c3fe0bac",
+1194 => x"120c5050",
+1195 => x"5004f83d",
+1196 => x"0d7a80cf",
+1197 => x"ec08b811",
+1198 => x"08575758",
+1199 => x"7481ec38",
+1200 => x"a8f60bbc",
+1201 => x"170c810b",
+1202 => x"b8170c74",
+1203 => x"84dc170c",
+1204 => x"830b84e0",
+1205 => x"170c84e8",
+1206 => x"1684e417",
+1207 => x"0c841608",
+1208 => x"75710c75",
+1209 => x"84120c75",
+1210 => x"88120c59",
+1211 => x"840b8c1a",
+1212 => x"23748e1a",
+1213 => x"2374901a",
+1214 => x"0c74941a",
+1215 => x"0c74981a",
+1216 => x"0c789c1a",
+1217 => x"0c80c1e5",
+1218 => x"0ba01a0c",
+1219 => x"80c2b10b",
+1220 => x"a41a0c80",
+1221 => x"c3ad0ba8",
+1222 => x"1a0c80c3",
+1223 => x"fe0bac1a",
+1224 => x"0c881608",
+1225 => x"75710c75",
+1226 => x"84120c75",
+1227 => x"88120c57",
+1228 => x"890b8c18",
+1229 => x"23810b8e",
+1230 => x"18237490",
+1231 => x"180c7494",
+1232 => x"180c7498",
+1233 => x"180c769c",
+1234 => x"180c80c1",
+1235 => x"e50ba018",
+1236 => x"0c80c2b1",
+1237 => x"0ba4180c",
+1238 => x"80c3ad0b",
+1239 => x"a8180c80",
+1240 => x"c3fe0bac",
+1241 => x"180c8c16",
+1242 => x"0875710c",
+1243 => x"7584120c",
+1244 => x"7588120c",
+1245 => x"548a0b8c",
+1246 => x"1523820b",
+1247 => x"8e152374",
+1248 => x"90150c74",
+1249 => x"94150c74",
+1250 => x"98150c73",
+1251 => x"9c150c80",
+1252 => x"c1e50ba0",
+1253 => x"150c80c2",
+1254 => x"b10ba415",
+1255 => x"0c80c3ad",
+1256 => x"0ba8150c",
+1257 => x"80c3fe0b",
+1258 => x"ac150c84",
+1259 => x"dc168811",
+1260 => x"08841208",
+1261 => x"ff055757",
+1262 => x"57807524",
+1263 => x"9f388c16",
+1264 => x"2270902b",
+1265 => x"70902c51",
+1266 => x"55597380",
+1267 => x"2e80ed38",
+1268 => x"80dc16ff",
+1269 => x"16565674",
+1270 => x"8025e338",
+1271 => x"76085574",
+1272 => x"802e8f38",
+1273 => x"74881108",
+1274 => x"841208ff",
+1275 => x"05575757",
+1276 => x"c83982fc",
+1277 => x"5277518a",
+1278 => x"df3f8008",
+1279 => x"80085556",
+1280 => x"8008802e",
+1281 => x"a3388008",
+1282 => x"8c057580",
+1283 => x"080c5484",
+1284 => x"0b800884",
+1285 => x"050c7380",
+1286 => x"0888050c",
+1287 => x"82f05374",
+1288 => x"52735197",
+1289 => x"fd3f7554",
+1290 => x"7374780c",
+1291 => x"5573ffb4",
+1292 => x"388c780c",
+1293 => x"800b800c",
+1294 => x"8a3d0d04",
+1295 => x"810b8c17",
+1296 => x"2373760c",
+1297 => x"7388170c",
+1298 => x"7384170c",
+1299 => x"7390170c",
+1300 => x"7394170c",
+1301 => x"7398170c",
+1302 => x"ff0b8e17",
+1303 => x"2373b017",
+1304 => x"0c73b417",
+1305 => x"0c7380c4",
+1306 => x"170c7380",
+1307 => x"c8170c75",
+1308 => x"800c8a3d",
+1309 => x"0d047070",
+1310 => x"a1aa5273",
+1311 => x"5186a63f",
+1312 => x"50500470",
+1313 => x"70a1aa52",
+1314 => x"80cfec08",
+1315 => x"5186963f",
+1316 => x"505004fb",
+1317 => x"3d0d7770",
+1318 => x"52569890",
+1319 => x"3f80d7a8",
+1320 => x"0b880508",
+1321 => x"841108fc",
+1322 => x"06707b31",
+1323 => x"9fef05e0",
+1324 => x"8006e080",
+1325 => x"05525555",
+1326 => x"a0807524",
+1327 => x"94388052",
+1328 => x"755197ea",
+1329 => x"3f80d7b0",
+1330 => x"08145372",
+1331 => x"80082e8f",
+1332 => x"38755197",
+1333 => x"d83f8053",
+1334 => x"72800c87",
+1335 => x"3d0d0474",
+1336 => x"30527551",
+1337 => x"97c83f80",
+1338 => x"08ff2ea8",
+1339 => x"3880d7a8",
+1340 => x"0b880508",
+1341 => x"74763181",
+1342 => x"0784120c",
+1343 => x"5380d6ec",
+1344 => x"08753180",
+1345 => x"d6ec0c75",
+1346 => x"5197a23f",
+1347 => x"810b800c",
+1348 => x"873d0d04",
+1349 => x"80527551",
+1350 => x"97943f80",
+1351 => x"d7a80b88",
+1352 => x"05088008",
+1353 => x"71315454",
+1354 => x"8f7325ff",
+1355 => x"a4388008",
+1356 => x"80d79c08",
+1357 => x"3180d6ec",
+1358 => x"0c728107",
+1359 => x"84150c75",
+1360 => x"5196ea3f",
+1361 => x"8053ff90",
+1362 => x"39f73d0d",
+1363 => x"7b7d545a",
+1364 => x"72802e82",
+1365 => x"83387951",
+1366 => x"96d23ff8",
+1367 => x"13841108",
+1368 => x"70fe0670",
+1369 => x"13841108",
+1370 => x"fc065c57",
+1371 => x"58545780",
+1372 => x"d7b00874",
+1373 => x"2e82de38",
+1374 => x"7784150c",
+1375 => x"80738106",
+1376 => x"56597479",
+1377 => x"2e81d538",
+1378 => x"77148411",
+1379 => x"08810656",
+1380 => x"5374a038",
+1381 => x"77165678",
+1382 => x"81e63888",
+1383 => x"14085574",
+1384 => x"80d7b02e",
+1385 => x"82f9388c",
+1386 => x"1408708c",
+1387 => x"170c7588",
+1388 => x"120c5875",
+1389 => x"81078418",
+1390 => x"0c751776",
+1391 => x"710c5478",
+1392 => x"81913883",
+1393 => x"ff762781",
+1394 => x"c8387589",
+1395 => x"2a76832a",
+1396 => x"54547380",
+1397 => x"2ebf3875",
+1398 => x"862ab805",
+1399 => x"53847427",
+1400 => x"b43880db",
+1401 => x"14539474",
+1402 => x"27ab3875",
+1403 => x"8c2a80ee",
+1404 => x"055380d4",
+1405 => x"74279e38",
+1406 => x"758f2a80",
+1407 => x"f7055382",
+1408 => x"d4742791",
+1409 => x"3875922a",
+1410 => x"80fc0553",
+1411 => x"8ad47427",
+1412 => x"843880fe",
+1413 => x"53721010",
+1414 => x"1080d7a8",
+1415 => x"05881108",
+1416 => x"55557375",
+1417 => x"2e82bf38",
+1418 => x"841408fc",
+1419 => x"06597579",
+1420 => x"278d3888",
+1421 => x"14085473",
+1422 => x"752e0981",
+1423 => x"06ea388c",
+1424 => x"1408708c",
+1425 => x"190c7488",
+1426 => x"190c7788",
+1427 => x"120c5576",
+1428 => x"8c150c79",
+1429 => x"5194d63f",
+1430 => x"8b3d0d04",
+1431 => x"76087771",
+1432 => x"31587605",
+1433 => x"88180856",
+1434 => x"567480d7",
+1435 => x"b02e80e0",
+1436 => x"388c1708",
+1437 => x"708c170c",
+1438 => x"7588120c",
+1439 => x"53fe8939",
+1440 => x"8814088c",
+1441 => x"1508708c",
+1442 => x"130c5988",
+1443 => x"190cfea3",
+1444 => x"3975832a",
+1445 => x"70545480",
+1446 => x"74248198",
+1447 => x"3872822c",
+1448 => x"81712b80",
+1449 => x"d7ac0807",
+1450 => x"80d7a80b",
+1451 => x"84050c74",
+1452 => x"10101080",
+1453 => x"d7a80588",
+1454 => x"1108718c",
+1455 => x"1b0c7088",
+1456 => x"1b0c7988",
+1457 => x"130c565a",
+1458 => x"55768c15",
+1459 => x"0cff8439",
+1460 => x"8159fdb4",
+1461 => x"39771673",
+1462 => x"81065455",
+1463 => x"72983876",
+1464 => x"08777131",
+1465 => x"5875058c",
+1466 => x"18088819",
+1467 => x"08718c12",
+1468 => x"0c88120c",
+1469 => x"55557481",
+1470 => x"0784180c",
+1471 => x"7680d7a8",
+1472 => x"0b88050c",
+1473 => x"80d7a408",
+1474 => x"7526fec7",
+1475 => x"3880d7a0",
+1476 => x"08527951",
+1477 => x"fafd3f79",
+1478 => x"5193923f",
+1479 => x"feba3981",
+1480 => x"778c170c",
+1481 => x"7788170c",
+1482 => x"758c190c",
+1483 => x"7588190c",
+1484 => x"59fd8039",
+1485 => x"83147082",
+1486 => x"2c81712b",
+1487 => x"80d7ac08",
+1488 => x"0780d7a8",
+1489 => x"0b84050c",
+1490 => x"75101010",
+1491 => x"80d7a805",
+1492 => x"88110871",
+1493 => x"8c1c0c70",
+1494 => x"881c0c7a",
+1495 => x"88130c57",
+1496 => x"5b5653fe",
+1497 => x"e4398073",
+1498 => x"24a33872",
+1499 => x"822c8171",
+1500 => x"2b80d7ac",
+1501 => x"080780d7",
+1502 => x"a80b8405",
+1503 => x"0c58748c",
+1504 => x"180c7388",
+1505 => x"180c7688",
+1506 => x"160cfdc3",
+1507 => x"39831370",
+1508 => x"822c8171",
+1509 => x"2b80d7ac",
+1510 => x"080780d7",
+1511 => x"a80b8405",
+1512 => x"0c5953da",
+1513 => x"39f93d0d",
+1514 => x"797b5853",
+1515 => x"800b80cf",
+1516 => x"ec085356",
+1517 => x"72722ebc",
+1518 => x"3884dc13",
+1519 => x"5574762e",
+1520 => x"b3388815",
+1521 => x"08841608",
+1522 => x"ff055454",
+1523 => x"80732499",
+1524 => x"388c1422",
+1525 => x"70902b53",
+1526 => x"587180d4",
+1527 => x"3880dc14",
+1528 => x"ff145454",
+1529 => x"728025e9",
+1530 => x"38740855",
+1531 => x"74d43880",
+1532 => x"cfec0852",
+1533 => x"84dc1255",
+1534 => x"74802ead",
+1535 => x"38881508",
+1536 => x"841608ff",
+1537 => x"05545480",
+1538 => x"73249838",
+1539 => x"8c142270",
+1540 => x"902b5358",
+1541 => x"71ad3880",
+1542 => x"dc14ff14",
+1543 => x"54547280",
+1544 => x"25ea3874",
+1545 => x"085574d5",
+1546 => x"3875800c",
+1547 => x"893d0d04",
+1548 => x"7351762d",
+1549 => x"75800807",
+1550 => x"80dc15ff",
+1551 => x"15555556",
+1552 => x"ffa23973",
+1553 => x"51762d75",
+1554 => x"80080780",
+1555 => x"dc15ff15",
+1556 => x"555556ca",
+1557 => x"39ea3d0d",
+1558 => x"688c1122",
+1559 => x"700a100a",
+1560 => x"81065758",
+1561 => x"567480e4",
+1562 => x"388e1622",
+1563 => x"70902b70",
+1564 => x"902c5155",
+1565 => x"58807424",
+1566 => x"b138983d",
+1567 => x"c4055373",
+1568 => x"5280cfec",
+1569 => x"08519481",
+1570 => x"3f800b80",
+1571 => x"08249738",
+1572 => x"7983e080",
+1573 => x"06547380",
+1574 => x"c0802e81",
+1575 => x"8f387382",
+1576 => x"80802e81",
+1577 => x"91388c16",
+1578 => x"22577690",
+1579 => x"80075473",
+1580 => x"8c172388",
+1581 => x"805280cf",
+1582 => x"ec085181",
+1583 => x"9b3f8008",
+1584 => x"9d388c16",
+1585 => x"22820755",
+1586 => x"748c1723",
+1587 => x"80c31670",
+1588 => x"770c9017",
+1589 => x"0c810b94",
+1590 => x"170c983d",
+1591 => x"0d0480cf",
+1592 => x"ec08a8f6",
+1593 => x"0bbc120c",
+1594 => x"588c1622",
+1595 => x"81800754",
+1596 => x"738c1723",
+1597 => x"8008760c",
+1598 => x"80089017",
+1599 => x"0c88800b",
+1600 => x"94170c74",
+1601 => x"802ed338",
+1602 => x"8e162270",
+1603 => x"902b7090",
+1604 => x"2c535654",
+1605 => x"9afb3f80",
+1606 => x"08802eff",
+1607 => x"bd388c16",
+1608 => x"22810757",
+1609 => x"768c1723",
+1610 => x"983d0d04",
+1611 => x"810b8c17",
+1612 => x"225855fe",
+1613 => x"f539a816",
+1614 => x"0880c3ad",
+1615 => x"2e098106",
+1616 => x"fee4388c",
+1617 => x"16228880",
+1618 => x"0754738c",
+1619 => x"17238880",
+1620 => x"0b80cc17",
+1621 => x"0cfedc39",
+1622 => x"f43d0d7e",
+1623 => x"608b1170",
+1624 => x"f8065b55",
+1625 => x"555d7296",
+1626 => x"26833890",
+1627 => x"58807824",
+1628 => x"74792607",
+1629 => x"55805474",
+1630 => x"742e0981",
+1631 => x"0680ca38",
+1632 => x"7c518ea8",
+1633 => x"3f7783f7",
+1634 => x"2680c538",
+1635 => x"77832a70",
+1636 => x"10101080",
+1637 => x"d7a8058c",
+1638 => x"11085858",
+1639 => x"5475772e",
+1640 => x"81f03884",
+1641 => x"1608fc06",
+1642 => x"8c170888",
+1643 => x"1808718c",
+1644 => x"120c8812",
+1645 => x"0c5b7605",
+1646 => x"84110881",
+1647 => x"0784120c",
+1648 => x"537c518d",
+1649 => x"e83f8816",
+1650 => x"5473800c",
+1651 => x"8e3d0d04",
+1652 => x"77892a78",
+1653 => x"832a5854",
+1654 => x"73802ebf",
+1655 => x"3877862a",
+1656 => x"b8055784",
+1657 => x"7427b438",
+1658 => x"80db1457",
+1659 => x"947427ab",
+1660 => x"38778c2a",
+1661 => x"80ee0557",
+1662 => x"80d47427",
+1663 => x"9e38778f",
+1664 => x"2a80f705",
+1665 => x"5782d474",
+1666 => x"27913877",
+1667 => x"922a80fc",
+1668 => x"05578ad4",
+1669 => x"74278438",
+1670 => x"80fe5776",
+1671 => x"10101080",
+1672 => x"d7a8058c",
+1673 => x"11085653",
+1674 => x"74732ea3",
+1675 => x"38841508",
+1676 => x"fc067079",
+1677 => x"31555673",
+1678 => x"8f2488e4",
+1679 => x"38738025",
+1680 => x"88e6388c",
+1681 => x"15085574",
+1682 => x"732e0981",
+1683 => x"06df3881",
+1684 => x"175980d7",
+1685 => x"b8085675",
+1686 => x"80d7b02e",
+1687 => x"82cc3884",
+1688 => x"1608fc06",
+1689 => x"70793155",
+1690 => x"55738f24",
+1691 => x"bb3880d7",
+1692 => x"b00b80d7",
+1693 => x"bc0c80d7",
+1694 => x"b00b80d7",
+1695 => x"b80c8074",
+1696 => x"2480db38",
+1697 => x"74168411",
+1698 => x"08810784",
+1699 => x"120c53fe",
+1700 => x"b0398816",
+1701 => x"8c110857",
+1702 => x"5975792e",
+1703 => x"098106fe",
+1704 => x"82388214",
+1705 => x"59ffab39",
+1706 => x"77167881",
+1707 => x"0784180c",
+1708 => x"7080d7bc",
+1709 => x"0c7080d7",
+1710 => x"b80c80d7",
+1711 => x"b00b8c12",
+1712 => x"0c8c1108",
+1713 => x"88120c74",
+1714 => x"81078412",
+1715 => x"0c740574",
+1716 => x"710c5b7c",
+1717 => x"518bd63f",
+1718 => x"881654fd",
+1719 => x"ec3983ff",
+1720 => x"75278391",
+1721 => x"3874892a",
+1722 => x"75832a54",
+1723 => x"5473802e",
+1724 => x"bf387486",
+1725 => x"2ab80553",
+1726 => x"847427b4",
+1727 => x"3880db14",
+1728 => x"53947427",
+1729 => x"ab38748c",
+1730 => x"2a80ee05",
+1731 => x"5380d474",
+1732 => x"279e3874",
+1733 => x"8f2a80f7",
+1734 => x"055382d4",
+1735 => x"74279138",
+1736 => x"74922a80",
+1737 => x"fc05538a",
+1738 => x"d4742784",
+1739 => x"3880fe53",
+1740 => x"72101010",
+1741 => x"80d7a805",
+1742 => x"88110855",
+1743 => x"5773772e",
+1744 => x"868b3884",
+1745 => x"1408fc06",
+1746 => x"5b747b27",
+1747 => x"8d388814",
+1748 => x"08547377",
+1749 => x"2e098106",
+1750 => x"ea388c14",
+1751 => x"0880d7a8",
+1752 => x"0b840508",
+1753 => x"718c190c",
+1754 => x"7588190c",
+1755 => x"7788130c",
+1756 => x"5c57758c",
+1757 => x"150c7853",
+1758 => x"80792483",
+1759 => x"98387282",
+1760 => x"2c81712b",
+1761 => x"5656747b",
+1762 => x"2680ca38",
+1763 => x"7a750657",
+1764 => x"7682a338",
+1765 => x"78fc0684",
+1766 => x"05597410",
+1767 => x"707c0655",
+1768 => x"55738292",
+1769 => x"38841959",
+1770 => x"f13980d7",
+1771 => x"a80b8405",
+1772 => x"0879545b",
+1773 => x"788025c6",
+1774 => x"3882da39",
+1775 => x"74097b06",
+1776 => x"7080d7a8",
+1777 => x"0b84050c",
+1778 => x"5b741055",
+1779 => x"747b2685",
+1780 => x"387485bc",
+1781 => x"3880d7a8",
+1782 => x"0b880508",
+1783 => x"70841208",
+1784 => x"fc06707b",
+1785 => x"317b7226",
+1786 => x"8f722507",
+1787 => x"5d575c5c",
+1788 => x"5578802e",
+1789 => x"80d93879",
+1790 => x"1580d7a0",
+1791 => x"08199011",
+1792 => x"59545680",
+1793 => x"d79c08ff",
+1794 => x"2e8838a0",
+1795 => x"8f13e080",
+1796 => x"06577652",
+1797 => x"7c518996",
+1798 => x"3f800854",
+1799 => x"8008ff2e",
+1800 => x"90388008",
+1801 => x"762782a7",
+1802 => x"387480d7",
+1803 => x"a82e829f",
+1804 => x"3880d7a8",
+1805 => x"0b880508",
+1806 => x"55841508",
+1807 => x"fc067079",
+1808 => x"31797226",
+1809 => x"8f722507",
+1810 => x"5d555a7a",
+1811 => x"83f23877",
+1812 => x"81078416",
+1813 => x"0c771570",
+1814 => x"80d7a80b",
+1815 => x"88050c74",
+1816 => x"81078412",
+1817 => x"0c567c51",
+1818 => x"88c33f88",
+1819 => x"15547380",
+1820 => x"0c8e3d0d",
+1821 => x"0474832a",
+1822 => x"70545480",
+1823 => x"7424819b",
+1824 => x"3872822c",
+1825 => x"81712b80",
+1826 => x"d7ac0807",
+1827 => x"7080d7a8",
+1828 => x"0b84050c",
+1829 => x"75101010",
+1830 => x"80d7a805",
+1831 => x"88110871",
+1832 => x"8c1b0c70",
+1833 => x"881b0c79",
+1834 => x"88130c57",
+1835 => x"555c5575",
+1836 => x"8c150cfd",
+1837 => x"c1397879",
+1838 => x"10101080",
+1839 => x"d7a80570",
+1840 => x"565b5c8c",
+1841 => x"14085675",
+1842 => x"742ea338",
+1843 => x"841608fc",
+1844 => x"06707931",
+1845 => x"5853768f",
+1846 => x"2483f138",
+1847 => x"76802584",
+1848 => x"af388c16",
+1849 => x"08567574",
+1850 => x"2e098106",
+1851 => x"df388814",
+1852 => x"811a7083",
+1853 => x"06555a54",
+1854 => x"72c9387b",
+1855 => x"83065675",
+1856 => x"802efdb8",
+1857 => x"38ff1cf8",
+1858 => x"1b5b5c88",
+1859 => x"1a087a2e",
+1860 => x"ea38fdb5",
+1861 => x"39831953",
+1862 => x"fce43983",
+1863 => x"1470822c",
+1864 => x"81712b80",
+1865 => x"d7ac0807",
+1866 => x"7080d7a8",
+1867 => x"0b84050c",
+1868 => x"76101010",
+1869 => x"80d7a805",
+1870 => x"88110871",
+1871 => x"8c1c0c70",
+1872 => x"881c0c7a",
+1873 => x"88130c58",
+1874 => x"535d5653",
+1875 => x"fee13980",
+1876 => x"d6ec0817",
+1877 => x"59800876",
+1878 => x"2e818b38",
+1879 => x"80d79c08",
+1880 => x"ff2e848e",
+1881 => x"38737631",
+1882 => x"1980d6ec",
+1883 => x"0c738706",
+1884 => x"70565372",
+1885 => x"802e8838",
+1886 => x"88733170",
+1887 => x"15555576",
+1888 => x"149fff06",
+1889 => x"a0807131",
+1890 => x"1670547e",
+1891 => x"53515386",
+1892 => x"9d3f8008",
+1893 => x"568008ff",
+1894 => x"2e819e38",
+1895 => x"80d6ec08",
+1896 => x"137080d6",
+1897 => x"ec0c7475",
+1898 => x"80d7a80b",
+1899 => x"88050c77",
+1900 => x"76311581",
+1901 => x"07555659",
+1902 => x"7a80d7a8",
+1903 => x"2e83c038",
+1904 => x"798f2682",
+1905 => x"ef38810b",
+1906 => x"84150c84",
+1907 => x"1508fc06",
+1908 => x"70793179",
+1909 => x"72268f72",
+1910 => x"25075d55",
+1911 => x"5a7a802e",
+1912 => x"fced3880",
+1913 => x"db398008",
+1914 => x"9fff0655",
+1915 => x"74feed38",
+1916 => x"7880d6ec",
+1917 => x"0c80d7a8",
+1918 => x"0b880508",
+1919 => x"7a188107",
+1920 => x"84120c55",
+1921 => x"80d79808",
+1922 => x"79278638",
+1923 => x"7880d798",
+1924 => x"0c80d794",
+1925 => x"087927fc",
+1926 => x"a0387880",
+1927 => x"d7940c84",
+1928 => x"1508fc06",
+1929 => x"70793179",
+1930 => x"72268f72",
+1931 => x"25075d55",
+1932 => x"5a7a802e",
+1933 => x"fc993888",
+1934 => x"39807457",
+1935 => x"53fedd39",
+1936 => x"7c5184e9",
+1937 => x"3f800b80",
+1938 => x"0c8e3d0d",
+1939 => x"04807324",
+1940 => x"a5387282",
+1941 => x"2c81712b",
+1942 => x"80d7ac08",
+1943 => x"077080d7",
+1944 => x"a80b8405",
+1945 => x"0c5c5a76",
+1946 => x"8c170c73",
+1947 => x"88170c75",
+1948 => x"88180cf9",
+1949 => x"fd398313",
+1950 => x"70822c81",
+1951 => x"712b80d7",
+1952 => x"ac080770",
+1953 => x"80d7a80b",
+1954 => x"84050c5d",
+1955 => x"5b53d839",
+1956 => x"7a75065c",
+1957 => x"7bfc9f38",
+1958 => x"84197510",
+1959 => x"5659f139",
+1960 => x"ff178105",
+1961 => x"59f7ab39",
+1962 => x"8c150888",
+1963 => x"1608718c",
+1964 => x"120c8812",
+1965 => x"0c597515",
+1966 => x"84110881",
+1967 => x"0784120c",
+1968 => x"587c5183",
+1969 => x"e83f8815",
+1970 => x"54fba339",
+1971 => x"77167881",
+1972 => x"0784180c",
+1973 => x"8c170888",
+1974 => x"1808718c",
+1975 => x"120c8812",
+1976 => x"0c5c7080",
+1977 => x"d7bc0c70",
+1978 => x"80d7b80c",
+1979 => x"80d7b00b",
+1980 => x"8c120c8c",
+1981 => x"11088812",
+1982 => x"0c778107",
+1983 => x"84120c77",
+1984 => x"0577710c",
+1985 => x"557c5183",
+1986 => x"a43f8816",
+1987 => x"54f5ba39",
+1988 => x"72168411",
+1989 => x"08810784",
+1990 => x"120c588c",
+1991 => x"16088817",
+1992 => x"08718c12",
+1993 => x"0c88120c",
+1994 => x"577c5183",
+1995 => x"803f8816",
+1996 => x"54f59639",
+1997 => x"7284150c",
+1998 => x"f41af806",
+1999 => x"70841d08",
+2000 => x"81060784",
+2001 => x"1d0c701c",
+2002 => x"5556850b",
+2003 => x"84150c85",
+2004 => x"0b88150c",
+2005 => x"8f7627fd",
+2006 => x"ab38881b",
+2007 => x"527c51eb",
+2008 => x"e83f80d7",
+2009 => x"a80b8805",
+2010 => x"0880d6ec",
+2011 => x"085a55fd",
+2012 => x"93397880",
+2013 => x"d6ec0c73",
+2014 => x"80d79c0c",
+2015 => x"fbef3972",
+2016 => x"84150cfc",
+2017 => x"ff39fb3d",
+2018 => x"0d77707a",
+2019 => x"7c585553",
+2020 => x"568f7527",
+2021 => x"80e63872",
+2022 => x"76078306",
+2023 => x"517080dc",
+2024 => x"38757352",
+2025 => x"54707084",
+2026 => x"05520874",
+2027 => x"70840556",
+2028 => x"0c737170",
+2029 => x"84055308",
+2030 => x"71708405",
+2031 => x"530c7170",
+2032 => x"84055308",
+2033 => x"71708405",
+2034 => x"530c7170",
+2035 => x"84055308",
+2036 => x"71708405",
+2037 => x"530cf016",
+2038 => x"5654748f",
+2039 => x"26c73883",
+2040 => x"75279538",
+2041 => x"70708405",
+2042 => x"52087470",
+2043 => x"8405560c",
+2044 => x"fc155574",
+2045 => x"8326ed38",
+2046 => x"73715452",
+2047 => x"ff155170",
+2048 => x"ff2e9838",
+2049 => x"72708105",
+2050 => x"54337270",
+2051 => x"81055434",
+2052 => x"ff115170",
+2053 => x"ff2e0981",
+2054 => x"06ea3875",
+2055 => x"800c873d",
+2056 => x"0d04fb3d",
+2057 => x"0d777a71",
+2058 => x"028c05a3",
+2059 => x"05335854",
+2060 => x"54568373",
+2061 => x"2780d438",
+2062 => x"75830651",
+2063 => x"7080cc38",
+2064 => x"74882b75",
+2065 => x"07707190",
+2066 => x"2b075551",
+2067 => x"8f7327a7",
+2068 => x"38737270",
+2069 => x"8405540c",
+2070 => x"71747170",
+2071 => x"8405530c",
+2072 => x"74717084",
+2073 => x"05530c74",
+2074 => x"71708405",
+2075 => x"530cf014",
+2076 => x"5452728f",
+2077 => x"26db3883",
+2078 => x"73279038",
+2079 => x"73727084",
+2080 => x"05540cfc",
+2081 => x"13537283",
+2082 => x"26f238ff",
+2083 => x"135170ff",
+2084 => x"2e933874",
+2085 => x"72708105",
+2086 => x"5434ff11",
+2087 => x"5170ff2e",
+2088 => x"098106ef",
+2089 => x"3875800c",
+2090 => x"873d0d04",
+2091 => x"04047070",
+2092 => x"7070800b",
+2093 => x"80dfe40c",
+2094 => x"765184f3",
+2095 => x"3f800853",
+2096 => x"8008ff2e",
+2097 => x"89387280",
+2098 => x"0c505050",
+2099 => x"500480df",
+2100 => x"e4085473",
+2101 => x"802eef38",
+2102 => x"7574710c",
+2103 => x"5272800c",
+2104 => x"50505050",
+2105 => x"04f93d0d",
+2106 => x"797c557b",
+2107 => x"548e1122",
+2108 => x"70902b70",
+2109 => x"902c5557",
+2110 => x"80cfec08",
+2111 => x"53585683",
+2112 => x"f63f8008",
+2113 => x"57800b80",
+2114 => x"08249338",
+2115 => x"80d01608",
+2116 => x"80080580",
+2117 => x"d0170c76",
+2118 => x"800c893d",
+2119 => x"0d048c16",
+2120 => x"2283dfff",
+2121 => x"0655748c",
+2122 => x"17237680",
+2123 => x"0c893d0d",
+2124 => x"04fa3d0d",
+2125 => x"788c1122",
+2126 => x"70882a70",
+2127 => x"81065157",
+2128 => x"585674a9",
+2129 => x"388c1622",
+2130 => x"83dfff06",
+2131 => x"55748c17",
+2132 => x"237a5479",
+2133 => x"538e1622",
+2134 => x"70902b70",
+2135 => x"902c5456",
+2136 => x"80cfec08",
+2137 => x"525681b2",
+2138 => x"3f883d0d",
+2139 => x"04825480",
+2140 => x"538e1622",
+2141 => x"70902b70",
+2142 => x"902c5456",
+2143 => x"80cfec08",
+2144 => x"525782bb",
+2145 => x"3f8c1622",
+2146 => x"83dfff06",
+2147 => x"55748c17",
+2148 => x"237a5479",
+2149 => x"538e1622",
+2150 => x"70902b70",
+2151 => x"902c5456",
+2152 => x"80cfec08",
+2153 => x"525680f2",
+2154 => x"3f883d0d",
+2155 => x"04f93d0d",
+2156 => x"797c557b",
+2157 => x"548e1122",
+2158 => x"70902b70",
+2159 => x"902c5557",
+2160 => x"80cfec08",
+2161 => x"53585681",
+2162 => x"f63f8008",
+2163 => x"578008ff",
+2164 => x"2e99388c",
+2165 => x"1622a080",
+2166 => x"0755748c",
+2167 => x"17238008",
+2168 => x"80d0170c",
+2169 => x"76800c89",
+2170 => x"3d0d048c",
+2171 => x"162283df",
+2172 => x"ff065574",
+2173 => x"8c172376",
+2174 => x"800c893d",
+2175 => x"0d047070",
+2176 => x"70748e11",
+2177 => x"2270902b",
+2178 => x"70902c55",
+2179 => x"51515380",
+2180 => x"cfec0851",
+2181 => x"bd3f5050",
+2182 => x"5004fb3d",
+2183 => x"0d800b80",
+2184 => x"dfe40c7a",
+2185 => x"53795278",
+2186 => x"5182fc3f",
+2187 => x"80085580",
+2188 => x"08ff2e88",
+2189 => x"3874800c",
+2190 => x"873d0d04",
+2191 => x"80dfe408",
+2192 => x"5675802e",
+2193 => x"f0387776",
+2194 => x"710c5474",
+2195 => x"800c873d",
+2196 => x"0d047070",
+2197 => x"7070800b",
+2198 => x"80dfe40c",
+2199 => x"765184c9",
+2200 => x"3f800853",
+2201 => x"8008ff2e",
+2202 => x"89387280",
+2203 => x"0c505050",
+2204 => x"500480df",
+2205 => x"e4085473",
+2206 => x"802eef38",
+2207 => x"7574710c",
+2208 => x"5272800c",
+2209 => x"50505050",
+2210 => x"04fc3d0d",
+2211 => x"800b80df",
+2212 => x"e40c7852",
+2213 => x"775187b0",
+2214 => x"3f800854",
+2215 => x"8008ff2e",
+2216 => x"88387380",
+2217 => x"0c863d0d",
+2218 => x"0480dfe4",
+2219 => x"08557480",
+2220 => x"2ef03876",
+2221 => x"75710c53",
+2222 => x"73800c86",
+2223 => x"3d0d04fb",
+2224 => x"3d0d800b",
+2225 => x"80dfe40c",
+2226 => x"7a537952",
+2227 => x"7851848b",
+2228 => x"3f800855",
+2229 => x"8008ff2e",
+2230 => x"88387480",
+2231 => x"0c873d0d",
+2232 => x"0480dfe4",
+2233 => x"08567580",
+2234 => x"2ef03877",
+2235 => x"76710c54",
+2236 => x"74800c87",
+2237 => x"3d0d04fb",
+2238 => x"3d0d800b",
+2239 => x"80dfe40c",
+2240 => x"7a537952",
+2241 => x"78518293",
+2242 => x"3f800855",
+2243 => x"8008ff2e",
+2244 => x"88387480",
+2245 => x"0c873d0d",
+2246 => x"0480dfe4",
+2247 => x"08567580",
+2248 => x"2ef03877",
+2249 => x"76710c54",
+2250 => x"74800c87",
+2251 => x"3d0d0470",
+2252 => x"707080df",
+2253 => x"d8088938",
+2254 => x"80dfe80b",
+2255 => x"80dfd80c",
+2256 => x"80dfd808",
+2257 => x"75115252",
+2258 => x"ff537087",
+2259 => x"fb808026",
+2260 => x"88387080",
+2261 => x"dfd80c71",
+2262 => x"5372800c",
+2263 => x"50505004",
+2264 => x"fd3d0d80",
+2265 => x"0b80cfe0",
+2266 => x"08545472",
+2267 => x"812e9b38",
+2268 => x"7380dfdc",
+2269 => x"0cc2af3f",
+2270 => x"c1863f80",
+2271 => x"dfb05281",
+2272 => x"51c3ff3f",
+2273 => x"80085186",
+2274 => x"bf3f7280",
+2275 => x"dfdc0cc2",
+2276 => x"953fc0ec",
+2277 => x"3f80dfb0",
+2278 => x"528151c3",
+2279 => x"e53f8008",
+2280 => x"5186a53f",
+2281 => x"00ff39f5",
+2282 => x"3d0d7e60",
+2283 => x"80dfdc08",
+2284 => x"705b585b",
+2285 => x"5b7580c2",
+2286 => x"38777a25",
+2287 => x"a138771b",
+2288 => x"70337081",
+2289 => x"ff065858",
+2290 => x"59758a2e",
+2291 => x"98387681",
+2292 => x"ff0651c1",
+2293 => x"b03f8118",
+2294 => x"58797824",
+2295 => x"e1387980",
+2296 => x"0c8d3d0d",
+2297 => x"048d51c1",
+2298 => x"9c3f7833",
+2299 => x"7081ff06",
+2300 => x"5257c191",
+2301 => x"3f811858",
+2302 => x"e0397955",
+2303 => x"7a547d53",
+2304 => x"85528d3d",
+2305 => x"fc0551c0",
+2306 => x"b93f8008",
+2307 => x"5685b23f",
+2308 => x"7b80080c",
+2309 => x"75800c8d",
+2310 => x"3d0d04f6",
+2311 => x"3d0d7d7f",
+2312 => x"80dfdc08",
+2313 => x"705b585a",
+2314 => x"5a7580c1",
+2315 => x"38777925",
+2316 => x"b338c0ac",
+2317 => x"3f800881",
+2318 => x"ff06708d",
+2319 => x"32703070",
+2320 => x"9f2a5151",
+2321 => x"5757768a",
+2322 => x"2e80c438",
+2323 => x"75802ebf",
+2324 => x"38771a56",
+2325 => x"76763476",
+2326 => x"51c0aa3f",
+2327 => x"81185878",
+2328 => x"7824cf38",
+2329 => x"77567580",
+2330 => x"0c8c3d0d",
+2331 => x"04785579",
+2332 => x"547c5384",
+2333 => x"528c3dfc",
+2334 => x"0551ffbf",
+2335 => x"c53f8008",
+2336 => x"5684be3f",
+2337 => x"7a80080c",
+2338 => x"75800c8c",
+2339 => x"3d0d0477",
+2340 => x"1a598a79",
+2341 => x"34811858",
+2342 => x"8d51ffbf",
+2343 => x"e83f8a51",
+2344 => x"ffbfe23f",
+2345 => x"7756ffbe",
+2346 => x"39fb3d0d",
+2347 => x"80dfdc08",
+2348 => x"70565473",
+2349 => x"88387480",
+2350 => x"0c873d0d",
+2351 => x"04775383",
+2352 => x"52873dfc",
+2353 => x"0551ffbe",
+2354 => x"f93f8008",
+2355 => x"5483f23f",
+2356 => x"7580080c",
+2357 => x"73800c87",
+2358 => x"3d0d04fa",
+2359 => x"3d0d80df",
+2360 => x"dc08802e",
+2361 => x"a3387a55",
+2362 => x"79547853",
+2363 => x"8652883d",
+2364 => x"fc0551ff",
+2365 => x"becc3f80",
+2366 => x"085683c5",
+2367 => x"3f768008",
+2368 => x"0c75800c",
+2369 => x"883d0d04",
+2370 => x"83b73f9d",
+2371 => x"0b80080c",
+2372 => x"ff0b800c",
+2373 => x"883d0d04",
+2374 => x"f73d0d7b",
+2375 => x"7d5b59bc",
+2376 => x"53805279",
+2377 => x"51f5fb3f",
+2378 => x"80705657",
+2379 => x"98567419",
+2380 => x"70337078",
+2381 => x"2b790781",
+2382 => x"18f81a5a",
+2383 => x"58595558",
+2384 => x"847524ea",
+2385 => x"38767a23",
+2386 => x"84195880",
+2387 => x"70565798",
+2388 => x"56741870",
+2389 => x"3370782b",
+2390 => x"79078118",
+2391 => x"f81a5a58",
+2392 => x"59515484",
+2393 => x"7524ea38",
+2394 => x"76821b23",
+2395 => x"88195880",
+2396 => x"70565798",
+2397 => x"56741870",
+2398 => x"3370782b",
+2399 => x"79078118",
+2400 => x"f81a5a58",
+2401 => x"59515484",
+2402 => x"7524ea38",
+2403 => x"76841b0c",
+2404 => x"8c195880",
+2405 => x"70565798",
+2406 => x"56741870",
+2407 => x"3370782b",
+2408 => x"79078118",
+2409 => x"f81a5a58",
+2410 => x"59515484",
+2411 => x"7524ea38",
+2412 => x"76881b23",
+2413 => x"90195880",
+2414 => x"70565798",
+2415 => x"56741870",
+2416 => x"3370782b",
+2417 => x"79078118",
+2418 => x"f81a5a58",
+2419 => x"59515484",
+2420 => x"7524ea38",
+2421 => x"768a1b23",
+2422 => x"94195880",
+2423 => x"70565798",
+2424 => x"56741870",
+2425 => x"3370782b",
+2426 => x"79078118",
+2427 => x"f81a5a58",
+2428 => x"59515484",
+2429 => x"7524ea38",
+2430 => x"768c1b23",
+2431 => x"98195880",
+2432 => x"70565798",
+2433 => x"56741870",
+2434 => x"3370782b",
+2435 => x"79078118",
+2436 => x"f81a5a58",
+2437 => x"59515484",
+2438 => x"7524ea38",
+2439 => x"768e1b23",
+2440 => x"9c195880",
+2441 => x"705657b8",
+2442 => x"56741870",
+2443 => x"3370782b",
+2444 => x"79078118",
+2445 => x"f81a5a58",
+2446 => x"595a5488",
+2447 => x"7524ea38",
+2448 => x"76901b0c",
+2449 => x"8b3d0d04",
+2450 => x"e93d0d6a",
+2451 => x"80dfdc08",
+2452 => x"57577593",
+2453 => x"3880c080",
+2454 => x"0b84180c",
+2455 => x"75ac180c",
+2456 => x"75800c99",
+2457 => x"3d0d0489",
+2458 => x"3d70556a",
+2459 => x"54558a52",
+2460 => x"993dffbc",
+2461 => x"0551ffbb",
+2462 => x"c93f8008",
+2463 => x"77537552",
+2464 => x"56fd953f",
+2465 => x"bc3f7780",
+2466 => x"080c7580",
+2467 => x"0c993d0d",
+2468 => x"04fc3d0d",
+2469 => x"815480df",
+2470 => x"dc088838",
+2471 => x"73800c86",
+2472 => x"3d0d0476",
+2473 => x"5397b952",
+2474 => x"863dfc05",
+2475 => x"51ffbb92",
+2476 => x"3f800854",
+2477 => x"8c3f7480",
+2478 => x"080c7380",
+2479 => x"0c863d0d",
+2480 => x"0480cfec",
+2481 => x"08800c04",
+2482 => x"f73d0d7b",
+2483 => x"80cfec08",
+2484 => x"82c81108",
+2485 => x"5a545a77",
+2486 => x"802e80da",
+2487 => x"38818818",
+2488 => x"841908ff",
+2489 => x"0581712b",
+2490 => x"59555980",
+2491 => x"742480ea",
+2492 => x"38807424",
+2493 => x"b5387382",
+2494 => x"2b781188",
+2495 => x"05565681",
+2496 => x"80190877",
+2497 => x"06537280",
+2498 => x"2eb63878",
+2499 => x"16700853",
+2500 => x"53795174",
+2501 => x"0853722d",
+2502 => x"ff14fc17",
+2503 => x"fc177981",
+2504 => x"2c5a5757",
+2505 => x"54738025",
+2506 => x"d6387708",
+2507 => x"5877ffad",
+2508 => x"3880cfec",
+2509 => x"0853bc13",
+2510 => x"08a53879",
+2511 => x"51f8e53f",
+2512 => x"74085372",
+2513 => x"2dff14fc",
+2514 => x"17fc1779",
+2515 => x"812c5a57",
+2516 => x"57547380",
+2517 => x"25ffa838",
+2518 => x"d1398057",
+2519 => x"ff933972",
+2520 => x"51bc1308",
+2521 => x"54732d79",
+2522 => x"51f8b93f",
+2523 => x"707080df",
+2524 => x"b80bfc05",
+2525 => x"70085252",
+2526 => x"70ff2e91",
+2527 => x"38702dfc",
+2528 => x"12700852",
+2529 => x"5270ff2e",
+2530 => x"098106f1",
+2531 => x"38505004",
+2532 => x"04ffbaff",
+2533 => x"3f040000",
+2534 => x"00000040",
+2535 => x"476f7420",
+2536 => x"696e7465",
+2537 => x"72727570",
+2538 => x"740a0000",
+2539 => x"4e6f2069",
+2540 => x"6e746572",
+2541 => x"72757074",
+2542 => x"0a000000",
+2543 => x"43000000",
+2544 => x"64756d6d",
+2545 => x"792e6578",
+2546 => x"65000000",
+2547 => x"00ffffff",
+2548 => x"ff00ffff",
+2549 => x"ffff00ff",
+2550 => x"ffffff00",
+2551 => x"00000000",
+2552 => x"00000000",
+2553 => x"00000000",
+2554 => x"00002fc0",
+2555 => x"000027f0",
+2556 => x"00000000",
+2557 => x"00002a58",
+2558 => x"00002ab4",
+2559 => x"00002b10",
+2560 => x"00000000",
+2561 => x"00000000",
+2562 => x"00000000",
+2563 => x"00000000",
+2564 => x"00000000",
+2565 => x"00000000",
+2566 => x"00000000",
+2567 => x"00000000",
+2568 => x"00000000",
+2569 => x"000027bc",
+2570 => x"00000000",
+2571 => x"00000000",
+2572 => x"00000000",
+2573 => x"00000000",
+2574 => x"00000000",
+2575 => x"00000000",
+2576 => x"00000000",
+2577 => x"00000000",
+2578 => x"00000000",
+2579 => x"00000000",
+2580 => x"00000000",
+2581 => x"00000000",
+2582 => x"00000000",
+2583 => x"00000000",
+2584 => x"00000000",
+2585 => x"00000000",
+2586 => x"00000000",
+2587 => x"00000000",
+2588 => x"00000000",
+2589 => x"00000000",
+2590 => x"00000000",
+2591 => x"00000000",
+2592 => x"00000000",
+2593 => x"00000000",
+2594 => x"00000000",
+2595 => x"00000000",
+2596 => x"00000000",
+2597 => x"00000000",
+2598 => x"00000001",
+2599 => x"330eabcd",
+2600 => x"1234e66d",
+2601 => x"deec0005",
+2602 => x"000b0000",
+2603 => x"00000000",
+2604 => x"00000000",
+2605 => x"00000000",
+2606 => x"00000000",
+2607 => x"00000000",
+2608 => x"00000000",
+2609 => x"00000000",
+2610 => x"00000000",
+2611 => x"00000000",
+2612 => x"00000000",
+2613 => x"00000000",
+2614 => x"00000000",
+2615 => x"00000000",
+2616 => x"00000000",
+2617 => x"00000000",
+2618 => x"00000000",
+2619 => x"00000000",
+2620 => x"00000000",
+2621 => x"00000000",
+2622 => x"00000000",
+2623 => x"00000000",
+2624 => x"00000000",
+2625 => x"00000000",
+2626 => x"00000000",
+2627 => x"00000000",
+2628 => x"00000000",
+2629 => x"00000000",
+2630 => x"00000000",
+2631 => x"00000000",
+2632 => x"00000000",
+2633 => x"00000000",
+2634 => x"00000000",
+2635 => x"00000000",
+2636 => x"00000000",
+2637 => x"00000000",
+2638 => x"00000000",
+2639 => x"00000000",
+2640 => x"00000000",
+2641 => x"00000000",
+2642 => x"00000000",
+2643 => x"00000000",
+2644 => x"00000000",
+2645 => x"00000000",
+2646 => x"00000000",
+2647 => x"00000000",
+2648 => x"00000000",
+2649 => x"00000000",
+2650 => x"00000000",
+2651 => x"00000000",
+2652 => x"00000000",
+2653 => x"00000000",
+2654 => x"00000000",
+2655 => x"00000000",
+2656 => x"00000000",
+2657 => x"00000000",
+2658 => x"00000000",
+2659 => x"00000000",
+2660 => x"00000000",
+2661 => x"00000000",
+2662 => x"00000000",
+2663 => x"00000000",
+2664 => x"00000000",
+2665 => x"00000000",
+2666 => x"00000000",
+2667 => x"00000000",
+2668 => x"00000000",
+2669 => x"00000000",
+2670 => x"00000000",
+2671 => x"00000000",
+2672 => x"00000000",
+2673 => x"00000000",
+2674 => x"00000000",
+2675 => x"00000000",
+2676 => x"00000000",
+2677 => x"00000000",
+2678 => x"00000000",
+2679 => x"00000000",
+2680 => x"00000000",
+2681 => x"00000000",
+2682 => x"00000000",
+2683 => x"00000000",
+2684 => x"00000000",
+2685 => x"00000000",
+2686 => x"00000000",
+2687 => x"00000000",
+2688 => x"00000000",
+2689 => x"00000000",
+2690 => x"00000000",
+2691 => x"00000000",
+2692 => x"00000000",
+2693 => x"00000000",
+2694 => x"00000000",
+2695 => x"00000000",
+2696 => x"00000000",
+2697 => x"00000000",
+2698 => x"00000000",
+2699 => x"00000000",
+2700 => x"00000000",
+2701 => x"00000000",
+2702 => x"00000000",
+2703 => x"00000000",
+2704 => x"00000000",
+2705 => x"00000000",
+2706 => x"00000000",
+2707 => x"00000000",
+2708 => x"00000000",
+2709 => x"00000000",
+2710 => x"00000000",
+2711 => x"00000000",
+2712 => x"00000000",
+2713 => x"00000000",
+2714 => x"00000000",
+2715 => x"00000000",
+2716 => x"00000000",
+2717 => x"00000000",
+2718 => x"00000000",
+2719 => x"00000000",
+2720 => x"00000000",
+2721 => x"00000000",
+2722 => x"00000000",
+2723 => x"00000000",
+2724 => x"00000000",
+2725 => x"00000000",
+2726 => x"00000000",
+2727 => x"00000000",
+2728 => x"00000000",
+2729 => x"00000000",
+2730 => x"00000000",
+2731 => x"00000000",
+2732 => x"00000000",
+2733 => x"00000000",
+2734 => x"00000000",
+2735 => x"00000000",
+2736 => x"00000000",
+2737 => x"00000000",
+2738 => x"00000000",
+2739 => x"00000000",
+2740 => x"00000000",
+2741 => x"00000000",
+2742 => x"00000000",
+2743 => x"00000000",
+2744 => x"00000000",
+2745 => x"00000000",
+2746 => x"00000000",
+2747 => x"00000000",
+2748 => x"00000000",
+2749 => x"00000000",
+2750 => x"00000000",
+2751 => x"00000000",
+2752 => x"00000000",
+2753 => x"00000000",
+2754 => x"00000000",
+2755 => x"00000000",
+2756 => x"00000000",
+2757 => x"00000000",
+2758 => x"00000000",
+2759 => x"00000000",
+2760 => x"00000000",
+2761 => x"00000000",
+2762 => x"00000000",
+2763 => x"00000000",
+2764 => x"00000000",
+2765 => x"00000000",
+2766 => x"00000000",
+2767 => x"00000000",
+2768 => x"00000000",
+2769 => x"00000000",
+2770 => x"00000000",
+2771 => x"00000000",
+2772 => x"00000000",
+2773 => x"00000000",
+2774 => x"00000000",
+2775 => x"00000000",
+2776 => x"00000000",
+2777 => x"00000000",
+2778 => x"00000000",
+2779 => x"00000000",
+2780 => x"00000000",
+2781 => x"00000000",
+2782 => x"00000000",
+2783 => x"00000000",
+2784 => x"00000000",
+2785 => x"00000000",
+2786 => x"00000000",
+2787 => x"00000000",
+2788 => x"00000000",
+2789 => x"00000000",
+2790 => x"00000000",
+2791 => x"ffffffff",
+2792 => x"00000000",
+2793 => x"00020000",
+2794 => x"00000000",
+2795 => x"00000000",
+2796 => x"00002ba8",
+2797 => x"00002ba8",
+2798 => x"00002bb0",
+2799 => x"00002bb0",
+2800 => x"00002bb8",
+2801 => x"00002bb8",
+2802 => x"00002bc0",
+2803 => x"00002bc0",
+2804 => x"00002bc8",
+2805 => x"00002bc8",
+2806 => x"00002bd0",
+2807 => x"00002bd0",
+2808 => x"00002bd8",
+2809 => x"00002bd8",
+2810 => x"00002be0",
+2811 => x"00002be0",
+2812 => x"00002be8",
+2813 => x"00002be8",
+2814 => x"00002bf0",
+2815 => x"00002bf0",
+2816 => x"00002bf8",
+2817 => x"00002bf8",
+2818 => x"00002c00",
+2819 => x"00002c00",
+2820 => x"00002c08",
+2821 => x"00002c08",
+2822 => x"00002c10",
+2823 => x"00002c10",
+2824 => x"00002c18",
+2825 => x"00002c18",
+2826 => x"00002c20",
+2827 => x"00002c20",
+2828 => x"00002c28",
+2829 => x"00002c28",
+2830 => x"00002c30",
+2831 => x"00002c30",
+2832 => x"00002c38",
+2833 => x"00002c38",
+2834 => x"00002c40",
+2835 => x"00002c40",
+2836 => x"00002c48",
+2837 => x"00002c48",
+2838 => x"00002c50",
+2839 => x"00002c50",
+2840 => x"00002c58",
+2841 => x"00002c58",
+2842 => x"00002c60",
+2843 => x"00002c60",
+2844 => x"00002c68",
+2845 => x"00002c68",
+2846 => x"00002c70",
+2847 => x"00002c70",
+2848 => x"00002c78",
+2849 => x"00002c78",
+2850 => x"00002c80",
+2851 => x"00002c80",
+2852 => x"00002c88",
+2853 => x"00002c88",
+2854 => x"00002c90",
+2855 => x"00002c90",
+2856 => x"00002c98",
+2857 => x"00002c98",
+2858 => x"00002ca0",
+2859 => x"00002ca0",
+2860 => x"00002ca8",
+2861 => x"00002ca8",
+2862 => x"00002cb0",
+2863 => x"00002cb0",
+2864 => x"00002cb8",
+2865 => x"00002cb8",
+2866 => x"00002cc0",
+2867 => x"00002cc0",
+2868 => x"00002cc8",
+2869 => x"00002cc8",
+2870 => x"00002cd0",
+2871 => x"00002cd0",
+2872 => x"00002cd8",
+2873 => x"00002cd8",
+2874 => x"00002ce0",
+2875 => x"00002ce0",
+2876 => x"00002ce8",
+2877 => x"00002ce8",
+2878 => x"00002cf0",
+2879 => x"00002cf0",
+2880 => x"00002cf8",
+2881 => x"00002cf8",
+2882 => x"00002d00",
+2883 => x"00002d00",
+2884 => x"00002d08",
+2885 => x"00002d08",
+2886 => x"00002d10",
+2887 => x"00002d10",
+2888 => x"00002d18",
+2889 => x"00002d18",
+2890 => x"00002d20",
+2891 => x"00002d20",
+2892 => x"00002d28",
+2893 => x"00002d28",
+2894 => x"00002d30",
+2895 => x"00002d30",
+2896 => x"00002d38",
+2897 => x"00002d38",
+2898 => x"00002d40",
+2899 => x"00002d40",
+2900 => x"00002d48",
+2901 => x"00002d48",
+2902 => x"00002d50",
+2903 => x"00002d50",
+2904 => x"00002d58",
+2905 => x"00002d58",
+2906 => x"00002d60",
+2907 => x"00002d60",
+2908 => x"00002d68",
+2909 => x"00002d68",
+2910 => x"00002d70",
+2911 => x"00002d70",
+2912 => x"00002d78",
+2913 => x"00002d78",
+2914 => x"00002d80",
+2915 => x"00002d80",
+2916 => x"00002d88",
+2917 => x"00002d88",
+2918 => x"00002d90",
+2919 => x"00002d90",
+2920 => x"00002d98",
+2921 => x"00002d98",
+2922 => x"00002da0",
+2923 => x"00002da0",
+2924 => x"00002da8",
+2925 => x"00002da8",
+2926 => x"00002db0",
+2927 => x"00002db0",
+2928 => x"00002db8",
+2929 => x"00002db8",
+2930 => x"00002dc0",
+2931 => x"00002dc0",
+2932 => x"00002dc8",
+2933 => x"00002dc8",
+2934 => x"00002dd0",
+2935 => x"00002dd0",
+2936 => x"00002dd8",
+2937 => x"00002dd8",
+2938 => x"00002de0",
+2939 => x"00002de0",
+2940 => x"00002de8",
+2941 => x"00002de8",
+2942 => x"00002df0",
+2943 => x"00002df0",
+2944 => x"00002df8",
+2945 => x"00002df8",
+2946 => x"00002e00",
+2947 => x"00002e00",
+2948 => x"00002e08",
+2949 => x"00002e08",
+2950 => x"00002e10",
+2951 => x"00002e10",
+2952 => x"00002e18",
+2953 => x"00002e18",
+2954 => x"00002e20",
+2955 => x"00002e20",
+2956 => x"00002e28",
+2957 => x"00002e28",
+2958 => x"00002e30",
+2959 => x"00002e30",
+2960 => x"00002e38",
+2961 => x"00002e38",
+2962 => x"00002e40",
+2963 => x"00002e40",
+2964 => x"00002e48",
+2965 => x"00002e48",
+2966 => x"00002e50",
+2967 => x"00002e50",
+2968 => x"00002e58",
+2969 => x"00002e58",
+2970 => x"00002e60",
+2971 => x"00002e60",
+2972 => x"00002e68",
+2973 => x"00002e68",
+2974 => x"00002e70",
+2975 => x"00002e70",
+2976 => x"00002e78",
+2977 => x"00002e78",
+2978 => x"00002e80",
+2979 => x"00002e80",
+2980 => x"00002e88",
+2981 => x"00002e88",
+2982 => x"00002e90",
+2983 => x"00002e90",
+2984 => x"00002e98",
+2985 => x"00002e98",
+2986 => x"00002ea0",
+2987 => x"00002ea0",
+2988 => x"00002ea8",
+2989 => x"00002ea8",
+2990 => x"00002eb0",
+2991 => x"00002eb0",
+2992 => x"00002eb8",
+2993 => x"00002eb8",
+2994 => x"00002ec0",
+2995 => x"00002ec0",
+2996 => x"00002ec8",
+2997 => x"00002ec8",
+2998 => x"00002ed0",
+2999 => x"00002ed0",
+3000 => x"00002ed8",
+3001 => x"00002ed8",
+3002 => x"00002ee0",
+3003 => x"00002ee0",
+3004 => x"00002ee8",
+3005 => x"00002ee8",
+3006 => x"00002ef0",
+3007 => x"00002ef0",
+3008 => x"00002ef8",
+3009 => x"00002ef8",
+3010 => x"00002f00",
+3011 => x"00002f00",
+3012 => x"00002f08",
+3013 => x"00002f08",
+3014 => x"00002f10",
+3015 => x"00002f10",
+3016 => x"00002f18",
+3017 => x"00002f18",
+3018 => x"00002f20",
+3019 => x"00002f20",
+3020 => x"00002f28",
+3021 => x"00002f28",
+3022 => x"00002f30",
+3023 => x"00002f30",
+3024 => x"00002f38",
+3025 => x"00002f38",
+3026 => x"00002f40",
+3027 => x"00002f40",
+3028 => x"00002f48",
+3029 => x"00002f48",
+3030 => x"00002f50",
+3031 => x"00002f50",
+3032 => x"00002f58",
+3033 => x"00002f58",
+3034 => x"00002f60",
+3035 => x"00002f60",
+3036 => x"00002f68",
+3037 => x"00002f68",
+3038 => x"00002f70",
+3039 => x"00002f70",
+3040 => x"00002f78",
+3041 => x"00002f78",
+3042 => x"00002f80",
+3043 => x"00002f80",
+3044 => x"00002f88",
+3045 => x"00002f88",
+3046 => x"00002f90",
+3047 => x"00002f90",
+3048 => x"00002f98",
+3049 => x"00002f98",
+3050 => x"00002fa0",
+3051 => x"00002fa0",
+3052 => x"000027c0",
+3053 => x"ffffffff",
+3054 => x"00000000",
+3055 => x"ffffffff",
+3056 => x"00000000",
diff --git a/zpu/hdl/zy2000/timer.vhd b/zpu/hdl/zy2000/timer.vhd
new file mode 100644
index 0000000..735d55c
--- /dev/null
+++ b/zpu/hdl/zy2000/timer.vhd
@@ -0,0 +1,137 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity timer is
+ port(
+ clk : in std_logic;
+ areset : in std_logic;
+ sample : in std_logic;
+ reset : in std_logic;
+ counter : out std_logic_vector(63 downto 0));
+end timer;
+
+
+architecture behave of timer is
+
+signal c : std_logic_vector(1 to 7);
+
+signal cnt : std_logic_vector(63 downto 0);
+signal cnt_smp : std_logic_vector(63 downto 0);
+
+begin
+
+ counter <= cnt_smp;
+
+ process(clk, areset) -- Carry generation
+ begin
+ if areset = '1' then
+ c <= "0000000";
+ elsif (clk'event and clk = '1') then
+ if reset = '1' then
+ c <= "0000000";
+ else
+ if cnt(7 downto 0) = "11111110" then
+ c(1) <= '1';
+ else
+ c(1) <= '0';
+ end if;
+ if cnt(15 downto 8) = "11111111" then
+ c(2) <= '1';
+ else
+ c(2) <= '0';
+ end if;
+ if cnt(23 downto 16) = "11111111" and c(2) = '1' then
+ c(3) <= '1';
+ else
+ c(3) <= '0';
+ end if;
+ if cnt(31 downto 24) = "11111111" and c(3) = '1' then
+ c(4) <= '1';
+ else
+ c(4) <= '0';
+ end if;
+ if cnt(39 downto 32) = "11111111" and c(4) = '1' then
+ c(5) <= '1';
+ else
+ c(5) <= '0';
+ end if;
+ if cnt(47 downto 40) = "11111111" and c(5) = '1' then
+ c(6) <= '1';
+ else
+ c(6) <= '0';
+ end if;
+ if cnt(55 downto 48) = "11111111" and c(6) = '1' then
+ c(7) <= '1';
+ else
+ c(7) <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ process(clk, areset)
+ begin
+ if areset = '1' then
+ cnt <= (others=>'0');
+ elsif (clk'event and clk = '1') then
+ if reset = '1' then
+ cnt <= (others=>'0');
+ else
+ cnt(7 downto 0) <= cnt(7 downto 0) + '1';
+ if c(1) = '1' then
+ cnt(15 downto 8) <= cnt(15 downto 8) + '1';
+ else
+ cnt(15 downto 8) <= cnt(15 downto 8);
+ end if;
+ if c(2) = '1' and c(1) = '1' then
+ cnt(23 downto 16) <= cnt(23 downto 16) + '1';
+ else
+ cnt(23 downto 16) <= cnt(23 downto 16);
+ end if;
+ if c(3) = '1' and c(1) = '1' then
+ cnt(31 downto 24) <= cnt(31 downto 24) + '1';
+ else
+ cnt(31 downto 24) <= cnt(31 downto 24);
+ end if;
+ if c(4) = '1' and c(1) = '1' then
+ cnt(39 downto 32) <= cnt(39 downto 32) + '1';
+ else
+ cnt(39 downto 32) <= cnt(39 downto 32);
+ end if;
+ if c(5) = '1' and c(1) = '1' then
+ cnt(47 downto 40) <= cnt(47 downto 40) + '1';
+ else
+ cnt(47 downto 40) <= cnt(47 downto 40);
+ end if;
+ if c(6) = '1' and c(1) = '1' then
+ cnt(55 downto 48) <= cnt(55 downto 48) + '1';
+ else
+ cnt(55 downto 48) <= cnt(55 downto 48);
+ end if;
+ if c(7) = '1' and c(1) = '1' then
+ cnt(63 downto 56) <= cnt(63 downto 56) + '1';
+ else
+ cnt(63 downto 56) <= cnt(63 downto 56);
+ end if;
+ end if;
+ end if;
+ end process;
+
+ process(clk, areset)
+ begin
+ if areset = '1' then
+ cnt_smp <= (others=>'0');
+ elsif (clk'event and clk = '1') then
+ if reset = '1' then
+ cnt_smp <= (others=>'0');
+ elsif sample = '1' then
+ cnt_smp <= cnt;
+ else
+ cnt_smp <= cnt_smp;
+ end if;
+ end if;
+ end process;
+
+end behave;
+
diff --git a/zpu/hdl/zy2000/trace.vhd b/zpu/hdl/zy2000/trace.vhd
new file mode 100644
index 0000000..ec6be57
--- /dev/null
+++ b/zpu/hdl/zy2000/trace.vhd
@@ -0,0 +1,84 @@
+library ieee;
+use ieee.std_logic_1164.all;
+--use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+use std.textio.all;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+use work.txt_util.all;
+
+
+entity trace is
+ generic (
+ log_file: string := "trace.txt"
+ );
+ port(
+ clk : in std_logic;
+ begin_inst : in std_logic;
+ pc : in std_logic_vector(maxAddrBitIncIO downto 0);
+ opcode : in std_logic_vector(7 downto 0);
+ sp : in std_logic_vector(maxAddrBitIncIO downto 2);
+ memA : in std_logic_vector(wordSize-1 downto 0);
+ memB : in std_logic_vector(wordSize-1 downto 0);
+ busy : in std_logic;
+ intSp : in std_logic_vector(stack_bits-1 downto 0)
+ );
+end trace;
+
+
+architecture behave of trace is
+
+
+file l_file : TEXT open write_mode is log_file;
+
+
+begin
+
+
+-- write data and control information to a file
+
+receive_data: process
+
+variable l: line;
+variable t : std_logic_vector(wordSize-1 downto 0);
+variable t2 : std_logic_vector(maxAddrBitIncIO downto 0);
+variable counter : std_logic_vector(63 downto 0);
+
+
+
+begin
+
+ t:= (others => '0');
+ t2:= (others => '0');
+
+counter := (others => '0');
+ -- print header for the logfile
+ print(l_file, "#pc,opcode,sp,top_of_stack ");
+ print(l_file, "#----------");
+ print(l_file, " ");
+
+ wait until clk = '1';
+ wait until clk = '0';
+
+ while true loop
+
+ counter := counter + 1;
+ if begin_inst = '1' then
+ t(maxAddrBitIncIO downto 2):=sp;
+ t2:=pc;
+ print(l_file, "0x" & hstr(t2) & " 0x" & hstr(opcode) & " 0x" & hstr(t) & " 0x" & hstr(memA) & " 0x" & hstr(memB) & " 0x" & hstr(intSp) & " 0x" & hstr(counter));
+ end if;
+
+ wait until clk = '0';
+
+ end loop;
+
+ end process receive_data;
+
+
+
+end behave;
+
diff --git a/zpu/hdl/zy2000/txt_util.vhd b/zpu/hdl/zy2000/txt_util.vhd
new file mode 100644
index 0000000..40d39b9
--- /dev/null
+++ b/zpu/hdl/zy2000/txt_util.vhd
@@ -0,0 +1,587 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use std.textio.all;
+
+library work;
+
+package txt_util is
+
+ -- prints a message to the screen
+ procedure print(text: string);
+
+ -- prints the message when active
+ -- useful for debug switches
+ procedure print(active: boolean; text: string);
+
+ -- converts std_logic into a character
+ function chr(sl: std_logic) return character;
+
+ -- converts std_logic into a string (1 to 1)
+ function str(sl: std_logic) return string;
+
+ -- converts std_logic_vector into a string (binary base)
+ function str(slv: std_logic_vector) return string;
+
+ -- converts boolean into a string
+ function str(b: boolean) return string;
+
+ -- converts an integer into a single character
+ -- (can also be used for hex conversion and other bases)
+ function chr(int: integer) return character;
+
+ -- converts integer into string using specified base
+ function str(int: integer; base: integer) return string;
+
+ -- converts integer to string, using base 10
+ function str(int: integer) return string;
+
+ -- convert std_logic_vector into a string in hex format
+ function hstr(slv: std_logic_vector) return string;
+
+
+ -- functions to manipulate strings
+ -----------------------------------
+
+ -- convert a character to upper case
+ function to_upper(c: character) return character;
+
+ -- convert a character to lower case
+ function to_lower(c: character) return character;
+
+ -- convert a string to upper case
+ function to_upper(s: string) return string;
+
+ -- convert a string to lower case
+ function to_lower(s: string) return string;
+
+
+
+ -- functions to convert strings into other formats
+ --------------------------------------------------
+
+ -- converts a character into std_logic
+ function to_std_logic(c: character) return std_logic;
+
+ -- converts a string into std_logic_vector
+ function to_std_logic_vector(s: string) return std_logic_vector;
+
+
+
+ -- file I/O
+ -----------
+
+ -- read variable length string from input file
+ procedure str_read(file in_file: TEXT;
+ res_string: out string);
+
+ -- print string to a file and start new line
+ procedure print(file out_file: TEXT;
+ new_string: in string);
+
+ -- print character to a file and start new line
+ procedure print(file out_file: TEXT;
+ char: in character);
+
+end txt_util;
+
+
+
+
+package body txt_util is
+
+
+
+
+ -- prints text to the screen
+
+ procedure print(text: string) is
+ variable msg_line: line;
+ begin
+ write(msg_line, text);
+ writeline(output, msg_line);
+ end print;
+
+
+
+
+ -- prints text to the screen when active
+
+ procedure print(active: boolean; text: string) is
+ begin
+ if active then
+ print(text);
+ end if;
+ end print;
+
+
+ -- converts std_logic into a character
+
+ function chr(sl: std_logic) return character is
+ variable c: character;
+ begin
+ case sl is
+ when 'U' => c:= 'U';
+ when 'X' => c:= 'X';
+ when '0' => c:= '0';
+ when '1' => c:= '1';
+ when 'Z' => c:= 'Z';
+ when 'W' => c:= 'W';
+ when 'L' => c:= 'L';
+ when 'H' => c:= 'H';
+ when '-' => c:= '-';
+ end case;
+ return c;
+ end chr;
+
+
+
+ -- converts std_logic into a string (1 to 1)
+
+ function str(sl: std_logic) return string is
+ variable s: string(1 to 1);
+ begin
+ s(1) := chr(sl);
+ return s;
+ end str;
+
+
+
+ -- converts std_logic_vector into a string (binary base)
+ -- (this also takes care of the fact that the range of
+ -- a string is natural while a std_logic_vector may
+ -- have an integer range)
+
+ function str(slv: std_logic_vector) return string is
+ variable result : string (1 to slv'length);
+ variable r : integer;
+ begin
+ r := 1;
+ for i in slv'range loop
+ result(r) := chr(slv(i));
+ r := r + 1;
+ end loop;
+ return result;
+ end str;
+
+
+ function str(b: boolean) return string is
+
+ begin
+ if b then
+ return "true";
+ else
+ return "false";
+ end if;
+ end str;
+
+
+ -- converts an integer into a character
+ -- for 0 to 9 the obvious mapping is used, higher
+ -- values are mapped to the characters A-Z
+ -- (this is usefull for systems with base > 10)
+ -- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
+
+ function chr(int: integer) return character is
+ variable c: character;
+ begin
+ case int is
+ when 0 => c := '0';
+ when 1 => c := '1';
+ when 2 => c := '2';
+ when 3 => c := '3';
+ when 4 => c := '4';
+ when 5 => c := '5';
+ when 6 => c := '6';
+ when 7 => c := '7';
+ when 8 => c := '8';
+ when 9 => c := '9';
+ when 10 => c := 'A';
+ when 11 => c := 'B';
+ when 12 => c := 'C';
+ when 13 => c := 'D';
+ when 14 => c := 'E';
+ when 15 => c := 'F';
+ when 16 => c := 'G';
+ when 17 => c := 'H';
+ when 18 => c := 'I';
+ when 19 => c := 'J';
+ when 20 => c := 'K';
+ when 21 => c := 'L';
+ when 22 => c := 'M';
+ when 23 => c := 'N';
+ when 24 => c := 'O';
+ when 25 => c := 'P';
+ when 26 => c := 'Q';
+ when 27 => c := 'R';
+ when 28 => c := 'S';
+ when 29 => c := 'T';
+ when 30 => c := 'U';
+ when 31 => c := 'V';
+ when 32 => c := 'W';
+ when 33 => c := 'X';
+ when 34 => c := 'Y';
+ when 35 => c := 'Z';
+ when others => c := '?';
+ end case;
+ return c;
+ end chr;
+
+
+
+ -- convert integer to string using specified base
+ -- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
+
+ function str(int: integer; base: integer) return string is
+
+ variable temp: string(1 to 10);
+ variable num: integer;
+ variable abs_int: integer;
+ variable len: integer := 1;
+ variable power: integer := 1;
+
+ begin
+
+ -- bug fix for negative numbers
+ abs_int := abs(int);
+
+ num := abs_int;
+
+ while num >= base loop -- Determine how many
+ len := len + 1; -- characters required
+ num := num / base; -- to represent the
+ end loop ; -- number.
+
+ for i in len downto 1 loop -- Convert the number to
+ temp(i) := chr(abs_int/power mod base); -- a string starting
+ power := power * base; -- with the right hand
+ end loop ; -- side.
+
+ -- return result and add sign if required
+ if int < 0 then
+ return '-'& temp(1 to len);
+ else
+ return temp(1 to len);
+ end if;
+
+ end str;
+
+
+ -- convert integer to string, using base 10
+ function str(int: integer) return string is
+
+ begin
+
+ return str(int, 10) ;
+
+ end str;
+
+
+
+ -- converts a std_logic_vector into a hex string.
+ function hstr(slv: std_logic_vector) return string is
+ variable hexlen: integer;
+ variable longslv : std_logic_vector(67 downto 0) := (others => '0');
+ variable hex : string(1 to 16);
+ variable fourbit : std_logic_vector(3 downto 0);
+ begin
+ hexlen := (slv'left+1)/4;
+ if (slv'left+1) mod 4 /= 0 then
+ hexlen := hexlen + 1;
+ end if;
+ longslv(slv'left downto 0) := slv;
+ for i in (hexlen -1) downto 0 loop
+ fourbit := longslv(((i*4)+3) downto (i*4));
+ case fourbit is
+ when "0000" => hex(hexlen -I) := '0';
+ when "0001" => hex(hexlen -I) := '1';
+ when "0010" => hex(hexlen -I) := '2';
+ when "0011" => hex(hexlen -I) := '3';
+ when "0100" => hex(hexlen -I) := '4';
+ when "0101" => hex(hexlen -I) := '5';
+ when "0110" => hex(hexlen -I) := '6';
+ when "0111" => hex(hexlen -I) := '7';
+ when "1000" => hex(hexlen -I) := '8';
+ when "1001" => hex(hexlen -I) := '9';
+ when "1010" => hex(hexlen -I) := 'A';
+ when "1011" => hex(hexlen -I) := 'B';
+ when "1100" => hex(hexlen -I) := 'C';
+ when "1101" => hex(hexlen -I) := 'D';
+ when "1110" => hex(hexlen -I) := 'E';
+ when "1111" => hex(hexlen -I) := 'F';
+ when "ZZZZ" => hex(hexlen -I) := 'z';
+ when "UUUU" => hex(hexlen -I) := 'u';
+ when "XXXX" => hex(hexlen -I) := 'x';
+ when others => hex(hexlen -I) := '?';
+ end case;
+ end loop;
+ return hex(1 to hexlen);
+ end hstr;
+
+
+
+ -- functions to manipulate strings
+ -----------------------------------
+
+
+ -- convert a character to upper case
+
+ function to_upper(c: character) return character is
+
+ variable u: character;
+
+ begin
+
+ case c is
+ when 'a' => u := 'A';
+ when 'b' => u := 'B';
+ when 'c' => u := 'C';
+ when 'd' => u := 'D';
+ when 'e' => u := 'E';
+ when 'f' => u := 'F';
+ when 'g' => u := 'G';
+ when 'h' => u := 'H';
+ when 'i' => u := 'I';
+ when 'j' => u := 'J';
+ when 'k' => u := 'K';
+ when 'l' => u := 'L';
+ when 'm' => u := 'M';
+ when 'n' => u := 'N';
+ when 'o' => u := 'O';
+ when 'p' => u := 'P';
+ when 'q' => u := 'Q';
+ when 'r' => u := 'R';
+ when 's' => u := 'S';
+ when 't' => u := 'T';
+ when 'u' => u := 'U';
+ when 'v' => u := 'V';
+ when 'w' => u := 'W';
+ when 'x' => u := 'X';
+ when 'y' => u := 'Y';
+ when 'z' => u := 'Z';
+ when others => u := c;
+ end case;
+
+ return u;
+
+ end to_upper;
+
+
+ -- convert a character to lower case
+
+ function to_lower(c: character) return character is
+
+ variable l: character;
+
+ begin
+
+ case c is
+ when 'A' => l := 'a';
+ when 'B' => l := 'b';
+ when 'C' => l := 'c';
+ when 'D' => l := 'd';
+ when 'E' => l := 'e';
+ when 'F' => l := 'f';
+ when 'G' => l := 'g';
+ when 'H' => l := 'h';
+ when 'I' => l := 'i';
+ when 'J' => l := 'j';
+ when 'K' => l := 'k';
+ when 'L' => l := 'l';
+ when 'M' => l := 'm';
+ when 'N' => l := 'n';
+ when 'O' => l := 'o';
+ when 'P' => l := 'p';
+ when 'Q' => l := 'q';
+ when 'R' => l := 'r';
+ when 'S' => l := 's';
+ when 'T' => l := 't';
+ when 'U' => l := 'u';
+ when 'V' => l := 'v';
+ when 'W' => l := 'w';
+ when 'X' => l := 'x';
+ when 'Y' => l := 'y';
+ when 'Z' => l := 'z';
+ when others => l := c;
+ end case;
+
+ return l;
+
+ end to_lower;
+
+
+
+ -- convert a string to upper case
+
+ function to_upper(s: string) return string is
+
+ variable uppercase: string (s'range);
+
+ begin
+
+ for i in s'range loop
+ uppercase(i):= to_upper(s(i));
+ end loop;
+ return uppercase;
+
+ end to_upper;
+
+
+
+ -- convert a string to lower case
+
+ function to_lower(s: string) return string is
+
+ variable lowercase: string (s'range);
+
+ begin
+
+ for i in s'range loop
+ lowercase(i):= to_lower(s(i));
+ end loop;
+ return lowercase;
+
+ end to_lower;
+
+
+
+-- functions to convert strings into other types
+
+
+-- converts a character into a std_logic
+
+function to_std_logic(c: character) return std_logic is
+ variable sl: std_logic;
+ begin
+ case c is
+ when 'U' =>
+ sl := 'U';
+ when 'X' =>
+ sl := 'X';
+ when '0' =>
+ sl := '0';
+ when '1' =>
+ sl := '1';
+ when 'Z' =>
+ sl := 'Z';
+ when 'W' =>
+ sl := 'W';
+ when 'L' =>
+ sl := 'L';
+ when 'H' =>
+ sl := 'H';
+ when '-' =>
+ sl := '-';
+ when others =>
+ sl := 'X';
+ end case;
+ return sl;
+ end to_std_logic;
+
+
+-- converts a string into std_logic_vector
+
+function to_std_logic_vector(s: string) return std_logic_vector is
+ variable slv: std_logic_vector(s'high-s'low downto 0);
+ variable k: integer;
+begin
+ k := s'high-s'low;
+ for i in s'range loop
+ slv(k) := to_std_logic(s(i));
+ k := k - 1;
+ end loop;
+ return slv;
+end to_std_logic_vector;
+
+
+
+
+
+
+----------------
+-- file I/O --
+----------------
+
+
+
+-- read variable length string from input file
+
+procedure str_read(file in_file: TEXT;
+ res_string: out string) is
+
+ variable l: line;
+ variable c: character;
+ variable is_string: boolean;
+
+ begin
+
+ readline(in_file, l);
+ -- clear the contents of the result string
+ for i in res_string'range loop
+ res_string(i) := ' ';
+ end loop;
+ -- read all characters of the line, up to the length
+ -- of the results string
+ for i in res_string'range loop
+ read(l, c, is_string);
+ res_string(i) := c;
+ if not is_string then -- found end of line
+ exit;
+ end if;
+ end loop;
+
+end str_read;
+
+
+-- print string to a file
+procedure print(file out_file: TEXT;
+ new_string: in string) is
+
+ variable l: line;
+
+ begin
+
+ write(l, new_string);
+ writeline(out_file, l);
+
+end print;
+
+
+-- print character to a file and start new line
+procedure print(file out_file: TEXT;
+ char: in character) is
+
+ variable l: line;
+
+ begin
+
+ write(l, char);
+ writeline(out_file, l);
+
+end print;
+
+
+
+-- appends contents of a string to a file until line feed occurs
+-- (LF is considered to be the end of the string)
+
+procedure str_write(file out_file: TEXT;
+ new_string: in string) is
+ begin
+
+ for i in new_string'range loop
+ print(out_file, new_string(i));
+ if new_string(i) = LF then -- end of string
+ exit;
+ end if;
+ end loop;
+
+end str_write;
+
+
+
+
+end txt_util;
+
+
+
+
diff --git a/zpu/hdl/zy2000/zpu_config.vhd b/zpu/hdl/zy2000/zpu_config.vhd
new file mode 100644
index 0000000..c0df294
--- /dev/null
+++ b/zpu/hdl/zy2000/zpu_config.vhd
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+package zpu_config is
+ -- generate trace output or not.
+ constant Generate_Trace : boolean := false;
+ constant wordPower : integer := 5;
+ -- during simulation, set this to '0' to get matching trace.txt
+ constant DontCareValue : std_logic := '0';
+ -- Clock frequency in MHz.
+ constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"40";
+ -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
+ constant maxAddrBitIncIO : integer := 27;
+
+ -- start byte address of stack.
+ -- point to top of RAM - 2*words
+ constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"1fffff8";
+
+end zpu_config;
diff --git a/zpu/hdl/zy2000/zpu_config_fast.vhd b/zpu/hdl/zy2000/zpu_config_fast.vhd
new file mode 100644
index 0000000..c0df294
--- /dev/null
+++ b/zpu/hdl/zy2000/zpu_config_fast.vhd
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+package zpu_config is
+ -- generate trace output or not.
+ constant Generate_Trace : boolean := false;
+ constant wordPower : integer := 5;
+ -- during simulation, set this to '0' to get matching trace.txt
+ constant DontCareValue : std_logic := '0';
+ -- Clock frequency in MHz.
+ constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"40";
+ -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
+ constant maxAddrBitIncIO : integer := 27;
+
+ -- start byte address of stack.
+ -- point to top of RAM - 2*words
+ constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"1fffff8";
+
+end zpu_config;
diff --git a/zpu/hdl/zy2000/zpu_core.vhd b/zpu/hdl/zy2000/zpu_core.vhd
new file mode 100644
index 0000000..2450f14
--- /dev/null
+++ b/zpu/hdl/zy2000/zpu_core.vhd
@@ -0,0 +1,948 @@
+
+-- Company: ZPU4 generic memory interface CPU
+-- Engineer: Øyvind Harboe
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.STD_LOGIC_arith.ALL;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+
+
+
+
+entity zpu_core is
+ Port ( clk : in std_logic;
+ areset : in std_logic;
+ enable : in std_logic;
+ mem_req : out std_logic;
+ mem_we : out std_logic;
+ mem_ack : in std_logic;
+ mem_read : in std_logic_vector(wordSize-1 downto 0);
+ mem_write : out std_logic_vector(wordSize-1 downto 0);
+ out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0);
+ mem_writeMask: out std_logic_vector(wordBytes-1 downto 0);
+ interrupt : in std_logic;
+ break : out std_logic;
+ zpu_status : out std_logic_vector(63 downto 0));
+end zpu_core;
+
+architecture behave of zpu_core is
+
+type InsnType is
+(
+State_AddTop,
+State_Dup,
+State_DupStackB,
+State_Pop,
+State_Popdown,
+State_Add,
+State_Or,
+State_And,
+State_Store,
+State_AddSP,
+State_Shift,
+State_Nop,
+State_Im,
+State_LoadSP,
+State_StoreSP,
+State_Emulate,
+State_Load,
+State_PushPC,
+State_PushSP,
+State_PopPC,
+State_PopPCRel,
+State_Not,
+State_Flip,
+State_PopSP,
+State_Neqbranch,
+State_Eq,
+State_Loadb,
+State_Mult,
+State_Lessthan,
+State_Lessthanorequal,
+State_Ulessthanorequal,
+State_Ulessthan,
+State_Pushspadd,
+State_Call,
+State_Callpcrel,
+State_Sub,
+State_Break,
+State_Storeb,
+State_Interrupt,
+State_InsnFetch
+);
+
+type StateType is
+(
+State_Idle, -- using first state first on the list out of paranoia
+State_Load2,
+State_Popped,
+State_LoadSP2,
+State_LoadSP3,
+State_AddSP2,
+State_Fetch,
+State_Execute,
+State_Decode,
+State_Decode2,
+State_Resync,
+
+State_StoreSP2,
+State_Resync2,
+State_Resync3,
+State_Loadb2,
+State_Storeb2,
+State_Mult2,
+State_Mult3,
+State_Mult5,
+State_Mult6,
+State_Mult4,
+State_BinaryOpResult
+);
+
+
+signal pc : std_logic_vector(maxAddrBitIncIO downto 0);
+signal sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+signal incSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+signal incIncSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+signal decSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+signal stackA : std_logic_vector(wordSize-1 downto 0);
+signal binaryOpResult : std_logic_vector(wordSize-1 downto 0);
+signal multResult2 : std_logic_vector(wordSize-1 downto 0);
+signal multResult3 : std_logic_vector(wordSize-1 downto 0);
+signal multResult : std_logic_vector(wordSize-1 downto 0);
+signal multA : std_logic_vector(wordSize-1 downto 0);
+signal multB : std_logic_vector(wordSize-1 downto 0);
+signal stackB : std_logic_vector(wordSize-1 downto 0);
+signal idim_flag : std_logic;
+signal busy : std_logic;
+signal mem_readEnable : std_logic;
+signal mem_addr : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+signal mem_delayAddr : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+signal mem_delayReadEnable : std_logic;
+signal mem_busy : std_logic;
+signal decodeWord : std_logic_vector(wordSize-1 downto 0);
+
+
+signal state : StateType;
+signal insn : InsnType;
+type InsnArray is array(0 to wordBytes-1) of InsnType;
+signal decodedOpcode : InsnArray;
+
+type OpcodeArray is array(0 to wordBytes-1) of std_logic_vector(7 downto 0);
+
+signal opcode : OpcodeArray;
+
+
+
+
+signal begin_inst : std_logic;
+signal trace_opcode : std_logic_vector(7 downto 0);
+signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0);
+signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0);
+signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0);
+
+signal out_mem_req : std_logic;
+
+signal inInterrupt : std_logic;
+
+-- state machine.
+
+begin
+
+ zpu_status(maxAddrBitIncIO downto 0) <= trace_pc;
+ zpu_status(31) <= '1';
+ zpu_status(39 downto 32) <= trace_opcode;
+ zpu_status(40) <= '1' when (state = State_Idle) else '0';
+ zpu_status(62) <= '1';
+
+ traceFileGenerate:
+ if Generate_Trace generate
+ trace_file: trace port map (
+ clk => clk,
+ begin_inst => begin_inst,
+ pc => trace_pc,
+ opcode => trace_opcode,
+ sp => trace_sp,
+ memA => trace_topOfStack,
+ memB => trace_topOfStackB,
+ busy => busy,
+ intsp => (others => 'U')
+ );
+ end generate;
+
+
+ -- the memory subsystem will tell us one cycle later whether or
+ -- not it is busy
+ out_mem_addr(maxAddrBitIncIO downto minAddrBit) <= mem_addr;
+ out_mem_addr(minAddrBit-1 downto 0) <= (others => '0');
+ mem_req <= out_mem_req;
+
+ incSp <= sp + 1;
+ incIncSp <= sp + 2;
+ decSp <= sp - 1;
+
+ mem_busy <= out_mem_req and not mem_ack; -- '1' when the memory is busy
+
+ opcodeControl:
+ process(clk, areset)
+ variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0);
+ variable spOffset : std_logic_vector(4 downto 0);
+ variable tSpOffset : std_logic_vector(4 downto 0);
+ variable nextPC : std_logic_vector(maxAddrBitIncIO downto 0);
+ variable tNextState : InsnType;
+ variable tDecodedOpcode : InsnArray;
+ variable tMultResult : std_logic_vector(wordSize*2-1 downto 0);
+ begin
+ if areset = '1' then
+ state <= State_Idle;
+ break <= '0';
+ sp <= spStart(maxAddrBitIncIO downto minAddrBit);
+
+ pc <= (others => '0');
+ idim_flag <= '0';
+ begin_inst <= '0';
+ mem_we <= '0';
+ multA <= (others => '0');
+ multB <= (others => '0');
+ mem_writeMask <= (others => '1');
+ out_mem_req <= '0';
+ mem_addr <= (others => DontCareValue);
+ mem_write <= (others => DontCareValue);
+ inInterrupt <= '0';
+ elsif (clk'event and clk = '1') then
+ -- we must multiply unconditionally to get pipelined multiplication
+ tMultResult := multA * multB;
+ multResult3 <= multResult2;
+ multResult2 <= multResult;
+ multResult <= tMultResult(wordSize-1 downto 0);
+
+
+ spOffset(4):=not opcode(conv_integer(pc(byteBits-1 downto 0)))(4);
+ spOffset(3 downto 0):=opcode(conv_integer(pc(byteBits-1 downto 0)))(3 downto 0);
+ nextPC := pc + 1;
+
+ -- prepare trace snapshot
+ trace_opcode <= opcode(conv_integer(pc(byteBits-1 downto 0)));
+ trace_pc <= pc;
+ trace_sp <= sp;
+ trace_topOfStack <= stackA;
+ trace_topOfStackB <= stackB;
+ begin_inst <= '0';
+
+ -- we terminate the requeset as soon as we get acknowledge
+ if mem_ack = '1' then
+ out_mem_req <= '0';
+ mem_we <= '0';
+ end if;
+
+ if interrupt='0' then
+ inInterrupt <= '0'; -- no longer in an interrupt
+ end if;
+
+ case state is
+ when State_Idle =>
+ if enable='1' then
+ state <= State_Resync;
+ end if;
+ -- Initial state of ZPU, fetch top of stack + first instruction
+ when State_Resync =>
+ if mem_busy='0' then
+ mem_addr <= sp;
+ out_mem_req <= '1';
+ state <= State_Resync2;
+ end if;
+ when State_Resync2 =>
+ if mem_busy='0' then
+ stackA <= mem_read;
+ mem_addr <= incSp;
+ out_mem_req <= '1';
+ state <= State_Resync3;
+ end if;
+ when State_Resync3 =>
+ if mem_busy='0' then
+ stackB <= mem_read;
+ mem_addr <= pc(maxAddrBitIncIO downto minAddrBit);
+ out_mem_req <= '1';
+ state <= State_Decode;
+ end if;
+ when State_Decode =>
+ if mem_busy='0' then
+ decodeWord <= mem_read;
+ state <= State_Decode2;
+ end if;
+ when State_Decode2 =>
+ -- decode 4 instructions in parallel
+ for i in 0 to wordBytes-1 loop
+ tOpcode := decodeWord((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8);
+
+ tSpOffset(4):=not tOpcode(4);
+ tSpOffset(3 downto 0):=tOpcode(3 downto 0);
+
+ opcode(i) <= tOpcode;
+ if (tOpcode(7 downto 7)=OpCode_Im) then
+ tNextState:=State_Im;
+ elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then
+ if tSpOffset = 0 then
+ tNextState := State_Pop;
+ elsif tSpOffset=1 then
+ tNextState := State_PopDown;
+ else
+ tNextState :=State_StoreSP;
+ end if;
+ elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then
+ if tSpOffset = 0 then
+ tNextState :=State_Dup;
+ elsif tSpOffset = 1 then
+ tNextState :=State_DupStackB;
+ else
+ tNextState :=State_LoadSP;
+ end if;
+ elsif (tOpcode(7 downto 5)=OpCode_Emulate) then
+ tNextState :=State_Emulate;
+ if tOpcode(5 downto 0)=OpCode_Neqbranch then
+ tNextState :=State_Neqbranch;
+ elsif tOpcode(5 downto 0)=OpCode_Eq then
+ tNextState :=State_Eq;
+ elsif tOpcode(5 downto 0)=OpCode_Lessthan then
+ tNextState :=State_Lessthan;
+ elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then
+ --tNextState :=State_Lessthanorequal;
+ elsif tOpcode(5 downto 0)=OpCode_Ulessthan then
+ tNextState :=State_Ulessthan;
+ elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then
+ --tNextState :=State_Ulessthanorequal;
+ elsif tOpcode(5 downto 0)=OpCode_Loadb then
+ tNextState :=State_Loadb;
+ elsif tOpcode(5 downto 0)=OpCode_Mult then
+ tNextState :=State_Mult;
+ elsif tOpcode(5 downto 0)=OpCode_Storeb then
+ tNextState :=State_Storeb;
+ elsif tOpcode(5 downto 0)=OpCode_Pushspadd then
+ tNextState :=State_Pushspadd;
+ elsif tOpcode(5 downto 0)=OpCode_Callpcrel then
+ tNextState :=State_Callpcrel;
+ elsif tOpcode(5 downto 0)=OpCode_Call then
+ --tNextState :=State_Call;
+ elsif tOpcode(5 downto 0)=OpCode_Sub then
+ tNextState :=State_Sub;
+ elsif tOpcode(5 downto 0)=OpCode_PopPCRel then
+ --tNextState :=State_PopPCRel;
+ end if;
+ elsif (tOpcode(7 downto 4)=OpCode_AddSP) then
+ if tSpOffset = 0 then
+ tNextState := State_Shift;
+ elsif tSpOffset = 1 then
+ tNextState := State_AddTop;
+ else
+ tNextState :=State_AddSP;
+ end if;
+ else
+ case tOpcode(3 downto 0) is
+ when OpCode_Nop =>
+ tNextState :=State_Nop;
+ when OpCode_PushSP =>
+ tNextState :=State_PushSP;
+ when OpCode_PopPC =>
+ tNextState :=State_PopPC;
+ when OpCode_Add =>
+ tNextState :=State_Add;
+ when OpCode_Or =>
+ tNextState :=State_Or;
+ when OpCode_And =>
+ tNextState :=State_And;
+ when OpCode_Load =>
+ tNextState :=State_Load;
+ when OpCode_Not =>
+ tNextState :=State_Not;
+ when OpCode_Flip =>
+ tNextState :=State_Flip;
+ when OpCode_Store =>
+ tNextState :=State_Store;
+ when OpCode_PopSP =>
+ tNextState :=State_PopSP;
+ when others =>
+ tNextState := State_Break;
+
+ end case;
+ end if;
+ tDecodedOpcode(i) := tNextState;
+
+ end loop;
+
+ insn <= tDecodedOpcode(conv_integer(pc(byteBits-1 downto 0)));
+
+ -- once we wrap, we need to fetch
+ tDecodedOpcode(0) := State_InsnFetch;
+
+ decodedOpcode <= tDecodedOpcode;
+ state <= State_Execute;
+
+
+
+ -- Each instruction must:
+ --
+ -- 1. set idim_flag
+ -- 2. increase pc if applicable
+ -- 3. set next state if appliable
+ -- 4. do it's operation
+
+ when State_Execute =>
+ insn <= decodedOpcode(conv_integer(nextPC(byteBits-1 downto 0)));
+
+ case insn is
+ when State_InsnFetch =>
+ state <= State_Fetch;
+ when State_Im =>
+ if mem_busy='0' then
+ begin_inst <= '1';
+ idim_flag <= '1';
+ pc <= pc + 1;
+
+ if idim_flag='1' then
+ stackA(wordSize-1 downto 7) <= stackA(wordSize-8 downto 0);
+ stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0);
+ else
+ out_mem_req <= '1';
+ mem_we <= '1';
+ mem_addr <= incSp;
+ mem_write <= stackB;
+ stackB <= stackA;
+ sp <= decSp;
+ for i in wordSize-1 downto 7 loop
+ stackA(i) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6);
+ end loop;
+ stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0);
+ end if;
+ else
+ insn <= insn;
+ end if;
+ when State_StoreSP =>
+ if mem_busy='0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ state <= State_StoreSP2;
+
+ out_mem_req <= '1';
+ mem_we <= '1';
+ mem_addr <= sp+spOffset;
+ mem_write <= stackA;
+ stackA <= stackB;
+ sp <= incSp;
+ else
+ insn <= insn;
+ end if;
+
+
+ when State_LoadSP =>
+ if mem_busy='0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ state <= State_LoadSP2;
+
+ sp <= decSp;
+ out_mem_req <= '1';
+ mem_we <= '1';
+ mem_addr <= incSp;
+ mem_write <= stackB;
+ else
+ insn <= insn;
+ end if;
+ when State_Emulate =>
+ if mem_busy='0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ sp <= decSp;
+ out_mem_req <= '1';
+ mem_we <= '1';
+ mem_addr <= incSp;
+ mem_write <= stackB;
+ stackA <= (others => DontCareValue);
+ stackA(maxAddrBitIncIO downto 0) <= pc + 1;
+ stackB <= stackA;
+
+ -- The emulate address is:
+ -- 98 7654 3210
+ -- 0000 00aa aaa0 0000
+ pc <= (others => '0');
+ pc(9 downto 5) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(4 downto 0);
+ state <= State_Fetch;
+ else
+ insn <= insn;
+ end if;
+ when State_Callpcrel =>
+ if mem_busy='0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ stackA <= (others => DontCareValue);
+ stackA(maxAddrBitIncIO downto 0) <= pc + 1;
+
+ pc <= pc + stackA(maxAddrBitIncIO downto 0);
+ state <= State_Fetch;
+ else
+ insn <= insn;
+ end if;
+ when State_Call =>
+ if mem_busy='0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ stackA <= (others => DontCareValue);
+ stackA(maxAddrBitIncIO downto 0) <= pc + 1;
+ pc <= stackA(maxAddrBitIncIO downto 0);
+ state <= State_Fetch;
+ else
+ insn <= insn;
+ end if;
+ when State_AddSP =>
+ if mem_busy='0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ state <= State_AddSP2;
+
+ out_mem_req <= '1';
+ mem_addr <= sp+spOffset;
+ else
+ insn <= insn;
+ end if;
+ when State_PushSP =>
+ if mem_busy='0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ pc <= pc + 1;
+
+ sp <= decSp;
+ stackA <= (others => '0');
+ stackA(maxAddrBitIncIO downto minAddrBit) <= sp;
+ stackB <= stackA;
+ out_mem_req <= '1';
+ mem_we <= '1';
+ mem_addr <= incSp;
+ mem_write <= stackB;
+ else
+ insn <= insn;
+ end if;
+ when State_PopPC =>
+ if mem_busy='0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ pc <= stackA(maxAddrBitIncIO downto 0);
+ sp <= incSp;
+
+ out_mem_req <= '1';
+ mem_we <= '1';
+ mem_addr <= incSp;
+ mem_write <= stackB;
+ state <= State_Resync;
+ else
+ insn <= insn;
+ end if;
+ when State_PopPCRel =>
+ if mem_busy='0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ pc <= stackA(maxAddrBitIncIO downto 0) + pc;
+ sp <= incSp;
+
+ out_mem_req <= '1';
+ mem_we <= '1';
+ mem_addr <= incSp;
+ mem_write <= stackB;
+ state <= State_Resync;
+ else
+ insn <= insn;
+ end if;
+ when State_Add =>
+ if mem_busy='0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ stackA <= stackA + stackB;
+
+ out_mem_req <= '1';
+ mem_addr <= incIncSp;
+ sp <= incSp;
+ state <= State_Popped;
+ else
+ insn <= insn;
+ end if;
+ when State_Sub =>
+ begin_inst <= '1';
+ idim_flag <= '0';
+ binaryOpResult <= stackB - stackA;
+ state <= State_BinaryOpResult;
+ when State_Pop =>
+ if mem_busy='0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ mem_addr <= incIncSp;
+ out_mem_req <= '1';
+ sp <= incSp;
+ stackA <= stackB;
+ state <= State_Popped;
+ else
+ insn <= insn;
+ end if;
+ when State_PopDown =>
+ if mem_busy='0' then
+ -- PopDown leaves top of stack unchanged
+ begin_inst <= '1';
+ idim_flag <= '0';
+ mem_addr <= incIncSp;
+ out_mem_req <= '1';
+ sp <= incSp;
+ state <= State_Popped;
+ else
+ insn <= insn;
+ end if;
+ when State_Or =>
+ if mem_busy='0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ stackA <= stackA or stackB;
+ out_mem_req <= '1';
+ mem_addr <= incIncSp;
+ sp <= incSp;
+ state <= State_Popped;
+ else
+ insn <= insn;
+ end if;
+ when State_And =>
+ if mem_busy='0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+
+ stackA <= stackA and stackB;
+ out_mem_req <= '1';
+ mem_addr <= incIncSp;
+ sp <= incSp;
+ state <= State_Popped;
+ else
+ insn <= insn;
+ end if;
+ when State_Eq =>
+ begin_inst <= '1';
+ idim_flag <= '0';
+
+ binaryOpResult <= (others => '0');
+ if (stackA=stackB) then
+ binaryOpResult(0) <= '1';
+ end if;
+ state <= State_BinaryOpResult;
+ when State_Ulessthan =>
+ begin_inst <= '1';
+ idim_flag <= '0';
+
+ binaryOpResult <= (others => '0');
+ if (stackA<stackB) then
+ binaryOpResult(0) <= '1';
+ end if;
+ state <= State_BinaryOpResult;
+ when State_Ulessthanorequal =>
+ begin_inst <= '1';
+ idim_flag <= '0';
+
+ binaryOpResult <= (others => '0');
+ if (stackA<=stackB) then
+ binaryOpResult(0) <= '1';
+ end if;
+ state <= State_BinaryOpResult;
+ when State_Lessthan =>
+ begin_inst <= '1';
+ idim_flag <= '0';
+
+ binaryOpResult <= (others => '0');
+ if (signed(stackA)<signed(stackB)) then
+ binaryOpResult(0) <= '1';
+ end if;
+ state <= State_BinaryOpResult;
+ when State_Lessthanorequal =>
+ begin_inst <= '1';
+ idim_flag <= '0';
+
+ binaryOpResult <= (others => '0');
+ if (signed(stackA)<=signed(stackB)) then
+ binaryOpResult(0) <= '1';
+ end if;
+ state <= State_BinaryOpResult;
+ when State_Load =>
+ if mem_busy='0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ state <= State_Load2;
+
+ mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit);
+ out_mem_req <= '1';
+ else
+ insn <= insn;
+ end if;
+
+ when State_Dup =>
+ if mem_busy='0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ pc <= pc + 1;
+
+ sp <= decSp;
+ stackB <= stackA;
+ mem_write <= stackB;
+ mem_addr <= incSp;
+ out_mem_req <= '1';
+ mem_we <= '1';
+ else
+ insn <= insn;
+ end if;
+ when State_DupStackB =>
+ if mem_busy='0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ pc <= pc + 1;
+
+ sp <= decSp;
+ stackA <= stackB;
+ stackB <= stackA;
+ mem_write <= stackB;
+ mem_addr <= incSp;
+ out_mem_req <= '1';
+ mem_we <= '1';
+ else
+ insn <= insn;
+ end if;
+ when State_Store =>
+ if mem_busy='0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ pc <= pc + 1;
+ mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit);
+ mem_write <= stackB;
+ out_mem_req <= '1';
+ mem_we <= '1';
+ sp <= incIncSp;
+ state <= State_Resync;
+ else
+ insn <= insn;
+ end if;
+ when State_PopSP =>
+ if mem_busy='0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ pc <= pc + 1;
+
+ mem_write <= stackB;
+ mem_addr <= incSp;
+ out_mem_req <= '1';
+ mem_we <= '1';
+ sp <= stackA(maxAddrBitIncIO downto minAddrBit);
+ state <= State_Resync;
+ else
+ insn <= insn;
+ end if;
+ when State_Nop =>
+ begin_inst <= '1';
+ idim_flag <= '0';
+ pc <= pc + 1;
+ when State_Not =>
+ begin_inst <= '1';
+ idim_flag <= '0';
+ pc <= pc + 1;
+
+ stackA <= not stackA;
+ when State_Flip =>
+ begin_inst <= '1';
+ idim_flag <= '0';
+ pc <= pc + 1;
+
+ for i in 0 to wordSize-1 loop
+ stackA(i) <= stackA(wordSize-1-i);
+ end loop;
+ when State_AddTop =>
+ begin_inst <= '1';
+ idim_flag <= '0';
+ pc <= pc + 1;
+
+ stackA <= stackA + stackB;
+ when State_Shift =>
+ begin_inst <= '1';
+ idim_flag <= '0';
+ pc <= pc + 1;
+
+ stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0);
+ stackA(0) <= '0';
+ when State_Pushspadd =>
+ begin_inst <= '1';
+ idim_flag <= '0';
+ pc <= pc + 1;
+
+ stackA <= (others => '0');
+ stackA(maxAddrBitIncIO downto minAddrBit) <= stackA(maxAddrBitIncIO-minAddrBit downto 0)+sp;
+ when State_Neqbranch =>
+ -- branches are almost always taken as they form loops
+ begin_inst <= '1';
+ idim_flag <= '0';
+ sp <= incIncSp;
+ if (stackB/=0) then
+ pc <= stackA(maxAddrBitIncIO downto 0) + pc;
+ else
+ pc <= pc + 1;
+ end if;
+ -- need to fetch stack again.
+ state <= State_Resync;
+ when State_Mult =>
+ begin_inst <= '1';
+ idim_flag <= '0';
+
+ multA <= stackA;
+ multB <= stackB;
+ state <= State_Mult2;
+ when State_Break =>
+ report "Break instruction encountered" severity failure;
+ break <= '1';
+
+ when State_Loadb =>
+ if mem_busy='0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ state <= State_Loadb2;
+
+ mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit);
+ out_mem_req <= '1';
+ else
+ insn <= insn;
+ end if;
+ when State_Storeb =>
+ if mem_busy='0' then
+ begin_inst <= '1';
+ idim_flag <= '0';
+ state <= State_Storeb2;
+
+ mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit);
+ out_mem_req <= '1';
+ else
+ insn <= insn;
+ end if;
+
+ when others =>
+-- sp <= (others => DontCareValue);
+ report "Illegal instruction" severity failure;
+ break <= '1';
+ end case;
+
+
+ when State_StoreSP2 =>
+ if mem_busy='0' then
+ mem_addr <= incSp;
+ out_mem_req <= '1';
+ state <= State_Popped;
+ end if;
+ when State_LoadSP2 =>
+ if mem_busy='0' then
+ state <= State_LoadSP3;
+ out_mem_req <= '1';
+ mem_addr <= sp+spOffset+1;
+ end if;
+ when State_LoadSP3 =>
+ if mem_busy='0' then
+ pc <= pc + 1;
+ state <= State_Execute;
+ stackB <= stackA;
+ stackA <= mem_read;
+ end if;
+ when State_AddSP2 =>
+ if mem_busy='0' then
+ pc <= pc + 1;
+ state <= State_Execute;
+ stackA <= stackA + mem_read;
+ end if;
+ when State_Load2 =>
+ if mem_busy='0' then
+ stackA <= mem_read;
+ pc <= pc + 1;
+ state <= State_Execute;
+ end if;
+ when State_Loadb2 =>
+ if mem_busy='0' then
+ stackA <= (others => '0');
+ stackA(7 downto 0) <= mem_read(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8);
+ pc <= pc + 1;
+ state <= State_Execute;
+ end if;
+ when State_Storeb2 =>
+ if mem_busy='0' then
+ mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit);
+ mem_write <= mem_read;
+ mem_write(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8) <= stackB(7 downto 0) ;
+ out_mem_req <= '1';
+ mem_we <= '1';
+ pc <= pc + 1;
+ sp <= incIncSp;
+ state <= State_Resync;
+ end if;
+ when State_Fetch =>
+ if mem_busy='0' then
+ if interrupt='1' and inInterrupt='0' and idim_flag='0' then
+ -- We got an interrupt
+ inInterrupt <= '1';
+
+ sp <= decSp;
+ out_mem_req <= '1';
+ mem_we <= '1';
+ mem_addr <= incSp;
+ mem_write <= stackB;
+ stackA <= (others => DontCareValue);
+ stackA(maxAddrBitIncIO downto 0) <= pc;
+ stackB <= stackA;
+
+ pc <= conv_std_logic_vector(32, maxAddrBitIncIo+1); -- interrupt address
+
+ report "ZPU jumped to interrupt!" severity note;
+ else
+ mem_addr <= pc(maxAddrBitIncIO downto minAddrBit);
+ out_mem_req <= '1';
+ state <= State_Decode;
+ end if;
+ end if;
+ when State_Mult2 =>
+ state <= State_Mult3;
+ when State_Mult3 =>
+ state <= State_Mult4;
+ when State_Mult4 =>
+ state <= State_Mult5;
+ when State_Mult5 =>
+ stackA <= multResult3;
+ state <= State_Mult6;
+ when State_Mult6 =>
+ if mem_busy='0' then
+ out_mem_req <= '1';
+ mem_addr <= incIncSp;
+ sp <= incSp;
+ state <= State_Popped;
+ end if;
+ when State_BinaryOpResult =>
+ if mem_busy='0' then
+ -- NB!!!! we know that the memory isn't busy at this point!!!!
+ out_mem_req <= '1';
+ mem_addr <= incIncSp;
+ sp <= incSp;
+ stackA <= binaryOpResult;
+ state <= State_Popped;
+ end if;
+ when State_Popped =>
+ if mem_busy='0' then
+ pc <= pc + 1;
+ stackB <= mem_read;
+ state <= State_Execute;
+ end if;
+ when others =>
+-- sp <= (others => DontCareValue);
+ report "Illegal state" severity failure;
+ break <= '1';
+ end case;
+ end if;
+ end process;
+
+
+
+end behave;
diff --git a/zpu/hdl/zy2000/zpupkg.vhd b/zpu/hdl/zy2000/zpupkg.vhd
new file mode 100644
index 0000000..a7e6cf1
--- /dev/null
+++ b/zpu/hdl/zy2000/zpupkg.vhd
@@ -0,0 +1,168 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+
+library work;
+use work.zpu_config.all;
+
+package zpupkg is
+
+ -- This bit is set for read/writes to IO
+ -- FIX!!! eventually this should be set to wordSize-1 so as to
+ -- to make the address of IO independent of amount of memory
+ -- reserved for CPU. Requires trivial tweaks in toolchain/runtime
+ -- libraries.
+
+ constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
+ constant maxAddrBit : integer := maxAddrBitIncIO-1;
+ constant ioBit : integer := maxAddrBit+1;
+ constant wordSize : integer := 2**wordPower;
+ constant wordBytes : integer := wordSize/8;
+ constant minAddrBit : integer := byteBits;
+ -- configurable internal stack size. Probably going to be 16 after toolchain is done
+ constant stack_bits : integer := 5;
+ constant stack_size : integer := 2**stack_bits;
+
+ component dualport_ram is
+ port (clk : in std_logic;
+ memAWriteEnable : in std_logic;
+ memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
+ memAWrite : in std_logic_vector(wordSize-1 downto 0);
+ memARead : out std_logic_vector(wordSize-1 downto 0);
+ memBWriteEnable : in std_logic;
+ memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
+ memBWrite : in std_logic_vector(wordSize-1 downto 0);
+ memBRead : out std_logic_vector(wordSize-1 downto 0));
+ end component;
+
+ component dram is
+ port (clk : in std_logic;
+ areset : in std_logic;
+ mem_writeEnable : in std_logic;
+ mem_readEnable : in std_logic;
+ mem_addr : in std_logic_vector(maxAddrBit downto 0);
+ mem_write : in std_logic_vector(wordSize-1 downto 0);
+ mem_read : out std_logic_vector(wordSize-1 downto 0);
+ mem_busy : out std_logic;
+ mem_writeMask : in std_logic_vector(wordBytes-1 downto 0));
+ end component;
+
+
+ component trace is
+ port(
+ clk : in std_logic;
+ begin_inst : in std_logic;
+ pc : in std_logic_vector(maxAddrBitIncIO downto 0);
+ opcode : in std_logic_vector(7 downto 0);
+ sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+ memA : in std_logic_vector(wordSize-1 downto 0);
+ memB : in std_logic_vector(wordSize-1 downto 0);
+ busy : in std_logic;
+ intSp : in std_logic_vector(stack_bits-1 downto 0)
+ );
+ end component;
+
+ component zpu_core is
+ port ( clk : in std_logic;
+ areset : in std_logic;
+ enable : in std_logic;
+ mem_req : out std_logic;
+ mem_we : out std_logic;
+ mem_ack : in std_logic;
+ mem_read : in std_logic_vector(wordSize-1 downto 0);
+ mem_write : out std_logic_vector(wordSize-1 downto 0);
+ out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0);
+ mem_writeMask: out std_logic_vector(wordBytes-1 downto 0);
+ interrupt : in std_logic;
+ break : out std_logic;
+ zpu_status : out std_logic_vector(63 downto 0));
+ end component;
+
+
+
+ component timer is
+ port(
+ clk : in std_logic;
+ areset : in std_logic;
+ sample : in std_logic;
+ reset : in std_logic;
+ counter : out std_logic_vector(63 downto 0));
+ end component;
+
+ component zpuio is
+ port ( areset : in std_logic;
+ cpu_clk : in std_logic;
+ clk_status : in std_logic_vector(2 downto 0);
+ cpu_din : in std_logic_vector(15 downto 0);
+ cpu_a : in std_logic_vector(20 downto 0);
+ cpu_we : in std_logic_vector(1 downto 0);
+ cpu_re : in std_logic;
+ cpu_dout : inout std_logic_vector(15 downto 0));
+ end component;
+
+
+
+
+ -- opcode decode constants
+ constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
+ constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
+ constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
+ constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
+ constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
+ constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
+
+ constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
+ constant OpCode_Shiftleft: std_logic_vector(3 downto 0) := "0001";
+ constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
+ constant OpCode_PushInt : std_logic_vector(3 downto 0) := "0011";
+
+ constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
+ constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
+ constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
+ constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
+
+ constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
+ constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
+ constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
+ constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
+
+ constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
+ constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
+ constant OpCode_Compare : std_logic_vector(3 downto 0) := "1110";
+ constant OpCode_PopInt : std_logic_vector(3 downto 0) := "1111";
+
+ constant OpCode_Lessthan : std_logic_vector(5 downto 0) := conv_std_logic_vector(36, 6);
+ constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := conv_std_logic_vector(37, 6);
+ constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := conv_std_logic_vector(38, 6);
+ constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := conv_std_logic_vector(39, 6);
+
+ constant OpCode_Swap : std_logic_vector(5 downto 0) := conv_std_logic_vector(40, 6);
+ constant OpCode_Mult : std_logic_vector(5 downto 0) := conv_std_logic_vector(41, 6);
+
+ constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := conv_std_logic_vector(42, 6);
+ constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := conv_std_logic_vector(43, 6);
+ constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := conv_std_logic_vector(44, 6);
+ constant OpCode_Call : std_logic_vector(5 downto 0) := conv_std_logic_vector(45, 6);
+
+ constant OpCode_Eq : std_logic_vector(5 downto 0) := conv_std_logic_vector(46, 6);
+ constant OpCode_Neq : std_logic_vector(5 downto 0) := conv_std_logic_vector(47, 6);
+
+ constant OpCode_Sub : std_logic_vector(5 downto 0) := conv_std_logic_vector(49, 6);
+ constant OpCode_Loadb : std_logic_vector(5 downto 0) := conv_std_logic_vector(51, 6);
+ constant OpCode_Storeb : std_logic_vector(5 downto 0) := conv_std_logic_vector(52, 6);
+
+ constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := conv_std_logic_vector(55, 6);
+ constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := conv_std_logic_vector(56, 6);
+ constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := conv_std_logic_vector(57, 6);
+
+ constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := conv_std_logic_vector(61, 6);
+ constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := conv_std_logic_vector(62, 6);
+ constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := conv_std_logic_vector(63, 6);
+
+
+
+ constant OpCode_Size : integer := 8;
+
+
+
+end zpupkg;
diff --git a/zpu/roadshow/roadshow/build/makefirmware.sh b/zpu/roadshow/roadshow/build/makefirmware.sh
new file mode 100644
index 0000000..b44559b
--- /dev/null
+++ b/zpu/roadshow/roadshow/build/makefirmware.sh
@@ -0,0 +1,13 @@
+echo >$2 ZylinPhiFirmware
+
+if [ x"$3" = x ] ;then
+ echo "No ic300.bit embedded into .phi"
+else
+ echo "Embed ic300.bit into .phi"
+ echo >>$2 "FPGA: `wc -c $3 | grep -o -e \[0-9\]*`"
+ cat >>$2 $1
+fi
+echo "Writing application"
+echo >>$2 "Application: `wc -c $1 | grep -o -e \[0-9\]*`"
+cat >>$2 $1
+echo >>$2 Done \ No newline at end of file
diff --git a/zpu/roadshow/roadshow/codesize/.cvsignore b/zpu/roadshow/roadshow/codesize/.cvsignore
new file mode 100644
index 0000000..6559932
--- /dev/null
+++ b/zpu/roadshow/roadshow/codesize/.cvsignore
@@ -0,0 +1 @@
+smallstd.elf
diff --git a/zpu/roadshow/roadshow/codesize/crt0_phi.S b/zpu/roadshow/roadshow/codesize/crt0_phi.S
new file mode 100644
index 0000000..4d654e2
--- /dev/null
+++ b/zpu/roadshow/roadshow/codesize/crt0_phi.S
@@ -0,0 +1,178 @@
+/* Startup code for ZPU
+ Copyright (C) 2005 Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file with other programs, and to distribute
+those programs without any restriction coming from the use of this
+file. (The General Public License restrictions do apply in other
+respects; for example, they cover modification of the file, and
+distribution when not linked into another program.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING. If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA. */
+ .file "crt0.S"
+
+
+
+
+; .section ".fixed_vectors","ax"
+; KLUDGE!!! we remove the executable bit to avoid relaxation
+ .section ".fixed_vectors","a"
+
+; DANGER!!!!
+; we need to align these code sections to 32 bytes, which
+; means we must not use any assembler instructions that are relaxed
+; at linker time
+; DANGER!!!!
+
+ .macro fixedim value
+ im \value
+ .endm
+
+ .macro jsr address
+
+ im 0 ; save R0
+ load
+ im 4 ; save R1
+ load
+ im 8 ; save R2
+ load
+
+ fixedim \address
+ call
+
+ im 8
+ store ; restore R2
+ im 4
+ store ; restore R1
+ im 0
+ store ; restore R0
+ .endm
+
+
+ .macro jmp address
+ fixedim \address
+ poppc
+ .endm
+
+
+ .macro fast_neg
+ not
+ im 1
+ add
+ .endm
+
+ .macro cimpl funcname
+ ; save R0
+ im 0
+ load
+
+ ; save R1
+ im 4
+ load
+
+ ; save R2
+ im 8
+ load
+
+ loadsp 20
+ loadsp 20
+
+ fixedim \funcname
+ call
+
+ ; destroy arguments on stack
+ storesp 0
+ storesp 0
+
+ im 0
+ load
+
+ ; poke the result into the right slot
+ storesp 24
+
+ ; restore R2
+ im 8
+ store
+
+ ; restore R1
+ im 4
+ store
+
+ ; restore r0
+ im 0
+ store
+
+
+ storesp 4
+ poppc
+ .endm
+
+ .macro mult1bit
+ ; create mask of lowest bit in A
+ loadsp 8 ; A
+ im 1
+ and
+ im -1
+ add
+ not
+ loadsp 8 ; B
+ and
+ add ; accumulate in C
+
+ ; shift B left 1 bit
+ loadsp 4 ; B
+ addsp 0
+ storesp 8 ; B
+
+ ; shift A right 1 bit
+ loadsp 8 ; A
+ flip
+ addsp 0
+ flip
+ storesp 12 ; A
+ .endm
+
+
+
+/* vectors */
+ .balign 32,0
+# offset 0x0000 0000
+ .globl _start
+_start:
+ ; intSp must be 0 when we jump to _premain
+
+ im ZPU_ID
+ loadsp 0
+ im _cpu_config
+ store
+ config
+ jmp _premain
+
+
+
+/* instruction emulation code */
+
+ .data
+
+
+ .globl _hardware
+_hardware:
+ .long 0
+ .globl _cpu_config
+_cpu_config:
+ .long 0
+
diff --git a/zpu/roadshow/roadshow/codesize/hello.c b/zpu/roadshow/roadshow/codesize/hello.c
new file mode 100644
index 0000000..176275c
--- /dev/null
+++ b/zpu/roadshow/roadshow/codesize/hello.c
@@ -0,0 +1,9 @@
+/* Simple hello world */
+#include <stdio.h>
+
+
+int main(int argc, char **argv)
+{
+ puts("Hello world\n");
+}
+
diff --git a/zpu/roadshow/roadshow/codesize/small.c b/zpu/roadshow/roadshow/codesize/small.c
new file mode 100644
index 0000000..0317343
--- /dev/null
+++ b/zpu/roadshow/roadshow/codesize/small.c
@@ -0,0 +1,9 @@
+void _premain(void)
+{
+ volatile int *someRegister=(volatile int *)0;
+ volatile int *otherRegister=(volatile int *)4;
+ while (*someRegister!=0)
+ {
+ *otherRegister++;
+ }
+}
diff --git a/zpu/roadshow/roadshow/codesize/small.elf b/zpu/roadshow/roadshow/codesize/small.elf
new file mode 100644
index 0000000..4193a53
--- /dev/null
+++ b/zpu/roadshow/roadshow/codesize/small.elf
Binary files differ
diff --git a/zpu/roadshow/roadshow/codesize/smallstd.c b/zpu/roadshow/roadshow/codesize/smallstd.c
new file mode 100644
index 0000000..5d4b87a
--- /dev/null
+++ b/zpu/roadshow/roadshow/codesize/smallstd.c
@@ -0,0 +1,9 @@
+int main(int argc, char **argv)
+{
+ volatile int *someRegister=(volatile int *)0;
+ volatile int *otherRegister=(volatile int *)4;
+ while (*someRegister!=0)
+ {
+ *otherRegister++;
+ }
+}
diff --git a/zpu/roadshow/roadshow/dhrystone/.cvsignore b/zpu/roadshow/roadshow/dhrystone/.cvsignore
new file mode 100644
index 0000000..3544c3f
--- /dev/null
+++ b/zpu/roadshow/roadshow/dhrystone/.cvsignore
@@ -0,0 +1,2 @@
+dhrystone.elf
+dhrystone_zpu.elf
diff --git a/zpu/roadshow/roadshow/dhrystone/RATIONALE b/zpu/roadshow/roadshow/dhrystone/RATIONALE
new file mode 100644
index 0000000..926e046
--- /dev/null
+++ b/zpu/roadshow/roadshow/dhrystone/RATIONALE
@@ -0,0 +1,361 @@
+
+
+ Dhrystone Benchmark: Rationale for Version 2 and Measurement Rules
+
+ [published in SIGPLAN Notices 23,8 (Aug. 1988), 49-62]
+
+
+ Reinhold P. Weicker
+ Siemens AG, E STE 35
+ [now: Siemens AG, AUT E 51]
+ Postfach 3220
+ D-8520 Erlangen
+ Germany (West)
+
+
+
+
+1. Why a Version 2 of Dhrystone?
+
+The Dhrystone benchmark program [1] has become a popular benchmark for
+CPU/compiler performance measurement, in particular in the area of
+minicomputers, workstations, PC's and microprocesors. It apparently satisfies
+a need for an easy-to-use integer benchmark; it gives a first performance
+indication which is more meaningful than MIPS numbers which, in their literal
+meaning (million instructions per second), cannot be used across different
+instruction sets (e.g. RISC vs. CISC). With the increasing use of the
+benchmark, it seems necessary to reconsider the benchmark and to check whether
+it can still fulfill this function. Version 2 of Dhrystone is the result of
+such a re-evaluation, it has been made for two reasons:
+
+o Dhrystone has been published in Ada [1], and Versions in Ada, Pascal and C
+ have been distributed by Reinhold Weicker via floppy disk. However, the
+ version that was used most often for benchmarking has been the version made
+ by Rick Richardson by another translation from the Ada version into the C
+ programming language, this has been the version distributed via the UNIX
+ network Usenet [2].
+
+ There is an obvious need for a common C version of Dhrystone, since C is at
+ present the most popular system programming language for the class of
+ systems (microcomputers, minicomputers, workstations) where Dhrystone is
+ used most. There should be, as far as possible, only one C version of
+ Dhrystone such that results can be compared without restrictions. In the
+ past, the C versions distributed by Rick Richardson (Version 1.1) and by
+ Reinhold Weicker had small (though not significant) differences.
+
+ Together with the new C version, the Ada and Pascal versions have been
+ updated as well.
+
+o As far as it is possible without changes to the Dhrystone statistics,
+ optimizing compilers should be prevented from removing significant
+ statements. It has turned out in the past that optimizing compilers
+ suppressed code generation for too many statements (by "dead code removal"
+ or "dead variable elimination"). This has lead to the danger that
+ benchmarking results obtained by a naive application of Dhrystone - without
+ inspection of the code that was generated - could become meaningless.
+
+The overall policiy for version 2 has been that the distribution of
+statements, operand types and operand locality described in [1] should remain
+unchanged as much as possible. (Very few changes were necessary; their impact
+should be negligible.) Also, the order of statements should remain unchanged.
+Although I am aware of some critical remarks on the benchmark - I agree with
+several of them - and know some suggestions for improvement, I didn't want to
+change the benchmark into something different from what has become known as
+"Dhrystone"; the confusion generated by such a change would probably outweight
+the benefits. If I were to write a new benchmark program, I wouldn't give it
+the name "Dhrystone" since this denotes the program published in [1].
+However, I do recognize the need for a larger number of representative
+programs that can be used as benchmarks; users should always be encouraged to
+use more than just one benchmark.
+
+The new versions (version 2.1 for C, Pascal and Ada) will be distributed as
+widely as possible. (Version 2.1 differs from version 2.0 distributed via the
+UNIX Network Usenet in March 1988 only in a few corrections for minor
+deficiencies found by users of version 2.0.) Readers who want to use the
+benchmark for their own measurements can obtain a copy in machine-readable
+form on floppy disk (MS-DOS or XENIX format) from the author.
+
+
+2. Overall Characteristics of Version 2
+
+In general, version 2 follows - in the parts that are significant for
+performance measurement, i.e. within the measurement loop - the published
+(Ada) version and the C versions previously distributed. Where the versions
+distributed by Rick Richardson [2] and Reinhold Weicker have been different,
+it follows the version distributed by Reinhold Weicker. (However, the
+differences have been so small that their impact on execution time in all
+likelihood has been negligible.) The initialization and UNIX instrumentation
+part - which had been omitted in [1] - follows mostly the ideas of Rick
+Richardson [2]. However, any changes in the initialization part and in the
+printing of the result have no impact on performance measurement since they
+are outside the measaurement loop. As a concession to older compilers, names
+have been made unique within the first 8 characters for the C version.
+
+The original publication of Dhrystone did not contain any statements for time
+measurement since they are necessarily system-dependent. However, it turned
+out that it is not enough just to inclose the main procedure of Dhrystone in a
+loop and to measure the execution time. If the variables that are computed
+are not used somehow, there is the danger that the compiler considers them as
+"dead variables" and suppresses code generation for a part of the statements.
+Therefore in version 2 all variables of "main" are printed at the end of the
+program. This also permits some plausibility control for correct execution of
+the benchmark.
+
+At several places in the benchmark, code has been added, but only in branches
+that are not executed. The intention is that optimizing compilers should be
+prevented from moving code out of the measurement loop, or from removing code
+altogether. Statements that are executed have been changed in very few places
+only. In these cases, only the role of some operands has been changed, and it
+was made sure that the numbers defining the "Dhrystone distribution"
+(distribution of statements, operand types and locality) still hold as much as
+possible. Except for sophisticated optimizing compilers, execution times for
+version 2.1 should be the same as for previous versions.
+
+Because of the self-imposed limitation that the order and distribution of the
+executed statements should not be changed, there are still cases where
+optimizing compilers may not generate code for some statements. To a certain
+degree, this is unavoidable for small synthetic benchmarks. Users of the
+benchmark are advised to check code listings whether code is generated for all
+statements of Dhrystone.
+
+Contrary to the suggestion in the published paper and its realization in the
+versions previously distributed, no attempt has been made to subtract the time
+for the measurement loop overhead. (This calculation has proven difficult to
+implement in a correct way, and its omission makes the program simpler.)
+However, since the loop check is now part of the benchmark, this does have an
+impact - though a very minor one - on the distribution statistics which have
+been updated for this version.
+
+
+3. Discussion of Individual Changes
+
+In this section, all changes are described that affect the measurement loop
+and that are not just renamings of variables. All remarks refer to the C
+version; the other language versions have been updated similarly.
+
+In addition to adding the measurement loop and the printout statements,
+changes have been made at the following places:
+
+o In procedure "main", three statements have been added in the non-executed
+ "then" part of the statement
+
+ if (Enum_Loc == Func_1 (Ch_Index, 'C'))
+
+ they are
+
+ strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 3'RD STRING");
+ Int_2_Loc = Run_Index;
+ Int_Glob = Run_Index;
+
+ The string assignment prevents movement of the preceding assignment to
+ Str_2_Loc (5'th statement of "main") out of the measurement loop (This
+ probably will not happen for the C version, but it did happen with another
+ language and compiler.) The assignment to Int_2_Loc prevents value
+ propagation for Int_2_Loc, and the assignment to Int_Glob makes the value of
+ Int_Glob possibly dependent from the value of Run_Index.
+
+o In the three arithmetic computations at the end of the measurement loop in
+ "main ", the role of some variables has been exchanged, to prevent the
+ division from just cancelling out the multiplication as it was in [1]. A
+ very smart compiler might have recognized this and suppressed code
+ generation for the division.
+
+o For Proc_2, no code has been changed, but the values of the actual parameter
+ have changed due to changes in "main".
+
+o In Proc_4, the second assignment has been changed from
+
+ Bool_Loc = Bool_Loc | Bool_Glob;
+
+ to
+
+ Bool_Glob = Bool_Loc | Bool_Glob;
+
+ It now assigns a value to a global variable instead of a local variable
+ (Bool_Loc); Bool_Loc would be a "dead variable" which is not used
+ afterwards.
+
+o In Func_1, the statement
+
+ Ch_1_Glob = Ch_1_Loc;
+
+ was added in the non-executed "else" part of the "if" statement, to prevent
+ the suppression of code generation for the assignment to Ch_1_Loc.
+
+o In Func_2, the second character comparison statement has been changed to
+
+ if (Ch_Loc == 'R')
+
+ ('R' instead of 'X') because a comparison with 'X' is implied in the
+ preceding "if" statement.
+
+ Also in Func_2, the statement
+
+ Int_Glob = Int_Loc;
+
+ has been added in the non-executed part of the last "if" statement, in order
+ to prevent Int_Loc from becoming a dead variable.
+
+o In Func_3, a non-executed "else" part has been added to the "if" statement.
+ While the program would not be incorrect without this "else" part, it is
+ considered bad programming practice if a function can be left without a
+ return value.
+
+ To compensate for this change, the (non-executed) "else" part in the "if"
+ statement of Proc_3 was removed.
+
+The distribution statistics have been changed only by the addition of the
+measurement loop iteration (1 additional statement, 4 additional local integer
+operands) and by the change in Proc_4 (one operand changed from local to
+global). The distribution statistics in the comment headers have been updated
+accordingly.
+
+
+4. String Operations
+
+The string operations (string assignment and string comparison) have not been
+changed, to keep the program consistent with the original version.
+
+There has been some concern that the string operations are over-represented in
+the program, and that execution time is dominated by these operations. This
+was true in particular when optimizing compilers removed too much code in the
+main part of the program, this should have been mitigated in version 2.
+
+It should be noted that this is a language-dependent issue: Dhrystone was
+first published in Ada, and with Ada or Pascal semantics, the time spent in
+the string operations is, at least in all implementations known to me,
+considerably smaller. In Ada and Pascal, assignment and comparison of strings
+are operators defined in the language, and the upper bounds of the strings
+occuring in Dhrystone are part of the type information known at compilation
+time. The compilers can therefore generate efficient inline code. In C,
+string assignemt and comparisons are not part of the language, so the string
+operations must be expressed in terms of the C library functions "strcpy" and
+"strcmp". (ANSI C allows an implementation to use inline code for these
+functions.) In addition to the overhead caused by additional function calls,
+these functions are defined for null-terminated strings where the length of
+the strings is not known at compilation time; the function has to check every
+byte for the termination condition (the null byte).
+
+Obviously, a C library which includes efficiently coded "strcpy" and "strcmp"
+functions helps to obtain good Dhrystone results. However, I don't think that
+this is unfair since string functions do occur quite frequently in real
+programs (editors, command interpreters, etc.). If the strings functions are
+implemented efficiently, this helps real programs as well as benchmark
+programs.
+
+I admit that the string comparison in Dhrystone terminates later (after
+scanning 20 characters) than most string comparisons in real programs. For
+consistency with the original benchmark, I didn't change the program despite
+this weakness.
+
+
+5. Intended Use of Dhrystone
+
+When Dhrystone is used, the following "ground rules" apply:
+
+o Separate compilation (Ada and C versions)
+
+ As mentioned in [1], Dhrystone was written to reflect actual programming
+ practice in systems programming. The division into several compilation
+ units (5 in the Ada version, 2 in the C version) is intended, as is the
+ distribution of inter-module and intra-module subprogram calls. Although on
+ many systems there will be no difference in execution time to a Dhrystone
+ version where all compilation units are merged into one file, the rule is
+ that separate compilation should be used. The intention is that real
+ programming practice, where programs consist of several independently
+ compiled units, should be reflected. This also has implies that the
+ compiler, while compiling one unit, has no information about the use of
+ variables, register allocation etc. occuring in other compilation units.
+ Although in real life compilation units will probably be larger, the
+ intention is that these effects of separate compilation are modeled in
+ Dhrystone.
+
+ A few language systems have post-linkage optimization available (e.g., final
+ register allocation is performed after linkage). This is a borderline case:
+ Post-linkage optimization involves additional program preparation time
+ (although not as much as compilation in one unit) which may prevent its
+ general use in practical programming. I think that since it defeats the
+ intentions given above, it should not be used for Dhrystone.
+
+ Unfortunately, ISO/ANSI Pascal does not contain language features for
+ separate compilation. Although most commercial Pascal compilers provide
+ separate compilation in some way, we cannot use it for Dhrystone since such
+ a version would not be portable. Therefore, no attempt has been made to
+ provide a Pascal version with several compilation units.
+
+o No procedure merging
+
+ Although Dhrystone contains some very short procedures where execution would
+ benefit from procedure merging (inlining, macro expansion of procedures),
+ procedure merging is not to be used. The reason is that the percentage of
+ procedure and function calls is part of the "Dhrystone distribution" of
+ statements contained in [1]. This restriction does not hold for the string
+ functions of the C version since ANSI C allows an implementation to use
+ inline code for these functions.
+
+o Other optimizations are allowed, but they should be indicated
+
+ It is often hard to draw an exact line between "normal code generation" and
+ "optimization" in compilers: Some compilers perform operations by default
+ that are invoked in other compilers only when optimization is explicitly
+ requested. Also, we cannot avoid that in benchmarking people try to achieve
+ results that look as good as possible. Therefore, optimizations performed
+ by compilers - other than those listed above - are not forbidden when
+ Dhrystone execution times are measured. Dhrystone is not intended to be
+ non-optimizable but is intended to be similarly optimizable as normal
+ programs. For example, there are several places in Dhrystone where
+ performance benefits from optimizations like common subexpression
+ elimination, value propagation etc., but normal programs usually also
+ benefit from these optimizations. Therefore, no effort was made to
+ artificially prevent such optimizations. However, measurement reports
+ should indicate which compiler optimization levels have been used, and
+ reporting results with different levels of compiler optimization for the
+ same hardware is encouraged.
+
+o Default results are those without "register" declarations (C version)
+
+ When Dhrystone results are quoted without additional qualification, they
+ should be understood as results obtained without use of the "register"
+ attribute. Good compilers should be able to make good use of registers even
+ without explicit register declarations ([3], p. 193).
+
+Of course, for experimental purposes, post-linkage optimization, procedure
+merging and/or compilation in one unit can be done to determine their effects.
+However, Dhrystone numbers obtained under these conditions should be
+explicitly marked as such; "normal" Dhrystone results should be understood as
+results obtained following the ground rules listed above.
+
+In any case, for serious performance evaluation, users are advised to ask for
+code listings and to check them carefully. In this way, when results for
+different systems are compared, the reader can get a feeling how much
+performance difference is due to compiler optimization and how much is due to
+hardware speed.
+
+
+6. Acknowledgements
+
+The C version 2.1 of Dhrystone has been developed in cooperation with Rick
+Richardson (Tinton Falls, NJ), it incorporates many ideas from the "Version
+1.1" distributed previously by him over the UNIX network Usenet. Through his
+activity with Usenet, Rick Richardson has made a very valuable contribution to
+the dissemination of the benchmark. I also thank Chaim Benedelac (National
+Semiconductor), David Ditzel (SUN), Earl Killian and John Mashey (MIPS), Alan
+Smith and Rafael Saavedra-Barrera (UC at Berkeley) for their help with
+comments on earlier versions of the benchmark.
+
+
+7. Bibliography
+
+[1]
+ Reinhold P. Weicker: Dhrystone: A Synthetic Systems Programming Benchmark.
+ Communications of the ACM 27, 10 (Oct. 1984), 1013-1030
+
+[2]
+ Rick Richardson: Dhrystone 1.1 Benchmark Summary (and Program Text)
+ Informal Distribution via "Usenet", Last Version Known to me: Sept. 21,
+ 1987
+
+[3]
+ Brian W. Kernighan and Dennis M. Ritchie: The C Programming Language.
+ Prentice-Hall, Englewood Cliffs (NJ) 1978
+
diff --git a/zpu/roadshow/roadshow/dhrystone/README_C b/zpu/roadshow/roadshow/dhrystone/README_C
new file mode 100644
index 0000000..a27a192
--- /dev/null
+++ b/zpu/roadshow/roadshow/dhrystone/README_C
@@ -0,0 +1,78 @@
+This "shar" file contains the documentation for the
+electronic mail distribution of the Dhrystone benchmark (C version 2.1);
+a companion "shar" file contains the source code.
+(Because of mail length restrictions for some mailers, I have
+split the distribution in two parts.)
+
+For versions in other languages, see the other "shar" files.
+
+Files containing the C version (*.h: Header File, *.c: C Modules)
+
+ dhry.h
+ dhry_1.c
+ dhry_2.c
+
+The file RATIONALE contains the article
+
+ "Dhrystone Benchmark: Rationale for Version 2 and Measurement Rules"
+
+which has been published, together with the C source code (Version 2.0),
+in SIGPLAN Notices vol. 23, no. 8 (Aug. 1988), pp. 49-62.
+This article explains all changes that have been made for Version 2,
+compared with the version of the original publication
+in Communications of the ACM vol. 27, no. 10 (Oct. 1984), pp. 1013-1030.
+It also contains "ground rules" for benchmarking with Dhrystone
+which should be followed by everyone who uses the program and publishes
+Dhrystone results.
+
+Compared with the Version 2.0 published in SIGPLAN Notices, Version 2.1
+contains a few corrections that have been made after Version 2.0 was
+distriobuted over the UNIX network Usenet. These small differences between
+Version 2.0 and 2.1 should not affect execution time measurements.
+For those who want to compare the exact contents of both versions,
+the file "dhry_c.dif" contains the differences between the two versions,
+as generated by a file comparison of the corresponding files with the
+UNIX utility "diff".
+
+The file VARIATIONS contains the article
+
+ "Understanding Variations in Dhrystone Performance"
+
+which has been published in Microprocessor Report, May 1989
+(Editor: M. Slater), pp. 16-17. It describes the points that users
+should know if C Dhrystone results are compared.
+
+Recipients of this shar file who perform measurements are asked
+to send measurement results to the author and/or to Rick Richardson.
+Rick Richardson publishes regularly Dhrystone results on the UNIX network
+Usenet. For submissions of results to him (preferably by electronic mail,
+see address in the program header), he has provided a form which is contained
+in the file "submit.frm".
+
+
+The following files are contained in other "shar" files:
+
+Files containing the Ada version (*.s: Specifications, *.b: Bodies):
+
+ d_global.s
+ d_main.b
+ d_pack_1.b
+ d_pack_1.s
+ d_pack_2.b
+ d_pack_2.s
+
+File containing the Pascal version:
+
+ dhry.p
+
+
+February 22, 1990
+
+ Reinhold P. Weicker
+ Siemens AG, AUT E 51
+ Postfach 3220
+ D-8520 Erlangen
+ Germany (West)
+
+ Phone: [xxx-49]-9131-7-20330 (8-17 Central European Time)
+ UUCP: ..!mcsun!unido!estevax!weicker
diff --git a/zpu/roadshow/roadshow/dhrystone/VARIATIONS b/zpu/roadshow/roadshow/dhrystone/VARIATIONS
new file mode 100644
index 0000000..3046cbd
--- /dev/null
+++ b/zpu/roadshow/roadshow/dhrystone/VARIATIONS
@@ -0,0 +1,157 @@
+
+ Understanding Variations in Dhrystone Performance
+
+
+
+ By Reinhold P. Weicker, Siemens AG, AUT E 51, Erlangen
+
+
+
+ April 1989
+
+
+ This article has appeared in:
+
+
+ Microprocessor Report, May 1989 (Editor: M. Slater), pp. 16-17
+
+
+
+
+Microprocessor manufacturers tend to credit all the performance measured by
+benchmarks to the speed of their processors, they often don't even mention the
+programming language and compiler used. In their detailed documents, usually
+called "performance brief" or "performance report," they usually do give more
+details. However, these details are often lost in the press releases and other
+marketing statements. For serious performance evaluation, it is necessary to
+study the code generated by the various compilers.
+
+Dhrystone was originally published in Ada (Communications of the ACM, Oct.
+1984). However, since good Ada compilers were rare at this time and, together
+with UNIX, C became more and more popular, the C version of Dhrystone is the
+one now mainly used in industry. There are "official" versions 2.1 for Ada,
+Pascal, and C, which are as close together as the languages' semantic
+differences permit.
+
+Dhrystone contains two statements where the programming language and its
+translation play a major part in the execution time measured by the benchmark:
+
+ o String assignment (in procedure Proc_0 / main)
+ o String comparison (in function Func_2)
+
+In Ada and Pascal, strings are arrays of characters where the length of the
+string is part of the type information known at compile time. In C, strings
+are also arrays of characters, but there are no operators defined in the
+language for assignment and comparison of strings. Instead, functions
+"strcpy" and "strcmp" are used. These functions are defined for strings of
+arbitrary length, and make use of the fact that strings in C have to end with
+a terminating null byte. For general-purpose calls to these functions, the
+implementor can assume nothing about the length and the alignment of the
+strings involved.
+
+The C version of Dhrystone spends a relatively large amount of time in these
+two functions. Some time ago, I made measurements on a VAX 11/785 with the
+Berkeley UNIX (4.2) compilers (often-used compilers, but certainly not the
+most advanced). In the C version, 23% of the time was spent in the string
+functions; in the Pascal version, only 10%. On good RISC machines (where less
+time is spent in the procedure calling sequence than on a VAX) and with better
+optimizing compilers, the percentage is higher; MIPS has reported 34% for an
+R3000. Because of this effect, Pascal and Ada Dhrystone results are usually
+better than C results (except when the optimization quality of the C compiler
+is considerably better than that of the other compilers).
+
+Several people have noted that the string operations are over-represented in
+Dhrystone, mainly because the strings occurring in Dhrystone are longer than
+average strings. I admit that this is true, and have said so in my SIGPLAN
+Notices paper (Aug. 1988); however, I didn't want to generate confusion by
+changing the string lengths from version 1 to version 2.
+
+Even if they are somewhat over-represented in Dhrystone, string operations are
+frequent enough that it makes sense to implement them in the most efficient
+way possible, not only for benchmarking purposes. This means that they can
+and should be written in assembly language code. ANSI C also explicitly allows
+the strings functions to be implemented as macros, i.e. by inline code.
+
+There is also a third way to speed up the "strcpy" statement in Dhrystone: For
+this particular "strcpy" statement, the source of the assignment is a string
+constant. Therefore, in contrast to calls to "strcpy" in the general case, the
+compiler knows the length and alignment of the strings involved at compile
+time and can generate code in the same efficient way as a Pascal compiler
+(word instructions instead of byte instructions).
+
+This is not allowed in the case of the "strcmp" call: Here, the addresses are
+formal procedure parameters, and no assumptions can be made about the length
+or alignment of the strings. Any such assumptions would indicate an incorrect
+implementation. They might work for Dhrystone, where the strings are in fact
+word-aligned with typical compilers, but other programs would deliver
+incorrect results.
+
+So, for an apple-to-apple comparison between processors, and not between
+several possible (legal or illegal) degrees of compiler optimization, one
+should check that the systems are comparable with respect to the following
+three points:
+
+ (1) String functions in assembly language vs. in C
+
+ Frequently used functions such as the string functions can and should be
+ written in assembly language, and all serious C language systems known
+ to me do this. (I list this point for completeness only.) Note that
+ processors with an instruction that checks a word for a null byte (such
+ as AMD's 29000 and Intel's 80960) have an advantage here. (This
+ advantage decreases relatively if optimization (3) is applied.) Due to
+ the length of the strings involved in Dhrystone, this advantage may be
+ considered too high in perspective, but it is certainly legal to use
+ such instructions - after all, these situations are what they were
+ invented for.
+
+ (2) String function code inline vs. as library functions.
+
+ ANSI C has created a new situation, compared with the older
+ Kernighan/Ritchie C. In the original C, the definition of the string
+ function was not part of the language. Now it is, and inlining is
+ explicitly allowed. I probably should have stated more clearly in my
+ SIGPLAN Notices paper that the rule "No procedure inlining for
+ Dhrystone" referred to the user level procedures only and not to the
+ library routines.
+
+ (3) Fixed-length and alignment assumptions for the strings
+
+ Compilers should be allowed to optimize in these cases if (and only if)
+ it is safe to do so. For Dhrystone, this is the "strcpy" statement, but
+ not the "strcmp" statement (unless, of course, the "strcmp" code
+ explicitly checks the alignment at execution time and branches
+ accordingly). A "Dhrystone switch" for the compiler that causes the
+ generation of code that may not work under certain circumstances is
+ certainly inappropriate for comparisons. It has been reported in Usenet
+ that some C compilers provide such a compiler option; since I don't have
+ access to all C compilers involved, I cannot verify this.
+
+ If the fixed-length and word-alignment assumption can be used, a wide
+ bus that permits fast multi-word load instructions certainly does help;
+ however, this fact by itself should not make a really big difference.
+
+A check of these points - something that is necessary for a thorough
+evaluation and comparison of the Dhrystone performance claims - requires
+object code listings as well as listings for the string functions (strcpy,
+strcmp) that are possibly called by the program.
+
+I don't pretend that Dhrystone is a perfect tool to measure the integer
+performance of microprocessors. The more it is used and discussed, the more I
+myself learn about aspects that I hadn't noticed yet when I wrote the program.
+And of course, the very success of a benchmark program is a danger in that
+people may tune their compilers and/or hardware to it, and with this action
+make it less useful.
+
+Whetstone and Linpack have their critical points also: The Whetstone rating
+depends heavily on the speed of the mathematical functions (sine, sqrt, ...),
+and Linpack is sensitive to data alignment for some cache configurations.
+
+Introduction of a standard set of public domain benchmark software (something
+the SPEC effort attempts) is certainly a worthwhile thing. In the meantime,
+people will continue to use whatever is available and widely distributed, and
+Dhrystone ratings are probably still better than MIPS ratings if these are -
+as often in industry - based on no reproducible derivation. However, any
+serious performance evaluation requires more than just a comparison of raw
+numbers; one has to make sure that the numbers have been obtained in a
+comparable way.
+
diff --git a/zpu/roadshow/roadshow/dhrystone/build.sh b/zpu/roadshow/roadshow/dhrystone/build.sh
new file mode 100644
index 0000000..5bba707
--- /dev/null
+++ b/zpu/roadshow/roadshow/dhrystone/build.sh
@@ -0,0 +1,7 @@
+zpu-elf-gcc -phi -DTIME dhry_1.c dhry_2.c -O3 -Wl,--relax -Wl,--gc-sections -o dhrystone.elf
+zpu-elf-size *.elf
+zpu-elf-objcopy -O binary dhrystone.elf dhrystone.bin
+sh ../build/makefirmware.sh dhrystone.bin dhrystone.zpu
+
+
+
diff --git a/zpu/roadshow/roadshow/dhrystone/dhry-c b/zpu/roadshow/roadshow/dhrystone/dhry-c
new file mode 100644
index 0000000..4cec46c
--- /dev/null
+++ b/zpu/roadshow/roadshow/dhrystone/dhry-c
@@ -0,0 +1,1779 @@
+# to unbundle, sh this file (in an empty directory)
+echo RATIONALE 1>&2
+sed >RATIONALE <<'//GO.SYSIN DD RATIONALE' 's/^-//'
+-
+-
+- Dhrystone Benchmark: Rationale for Version 2 and Measurement Rules
+-
+- [published in SIGPLAN Notices 23,8 (Aug. 1988), 49-62]
+-
+-
+- Reinhold P. Weicker
+- Siemens AG, E STE 35
+- [now: Siemens AG, AUT E 51]
+- Postfach 3220
+- D-8520 Erlangen
+- Germany (West)
+-
+-
+-
+-
+-1. Why a Version 2 of Dhrystone?
+-
+-The Dhrystone benchmark program [1] has become a popular benchmark for
+-CPU/compiler performance measurement, in particular in the area of
+-minicomputers, workstations, PC's and microprocesors. It apparently satisfies
+-a need for an easy-to-use integer benchmark; it gives a first performance
+-indication which is more meaningful than MIPS numbers which, in their literal
+-meaning (million instructions per second), cannot be used across different
+-instruction sets (e.g. RISC vs. CISC). With the increasing use of the
+-benchmark, it seems necessary to reconsider the benchmark and to check whether
+-it can still fulfill this function. Version 2 of Dhrystone is the result of
+-such a re-evaluation, it has been made for two reasons:
+-
+-o Dhrystone has been published in Ada [1], and Versions in Ada, Pascal and C
+- have been distributed by Reinhold Weicker via floppy disk. However, the
+- version that was used most often for benchmarking has been the version made
+- by Rick Richardson by another translation from the Ada version into the C
+- programming language, this has been the version distributed via the UNIX
+- network Usenet [2].
+-
+- There is an obvious need for a common C version of Dhrystone, since C is at
+- present the most popular system programming language for the class of
+- systems (microcomputers, minicomputers, workstations) where Dhrystone is
+- used most. There should be, as far as possible, only one C version of
+- Dhrystone such that results can be compared without restrictions. In the
+- past, the C versions distributed by Rick Richardson (Version 1.1) and by
+- Reinhold Weicker had small (though not significant) differences.
+-
+- Together with the new C version, the Ada and Pascal versions have been
+- updated as well.
+-
+-o As far as it is possible without changes to the Dhrystone statistics,
+- optimizing compilers should be prevented from removing significant
+- statements. It has turned out in the past that optimizing compilers
+- suppressed code generation for too many statements (by "dead code removal"
+- or "dead variable elimination"). This has lead to the danger that
+- benchmarking results obtained by a naive application of Dhrystone - without
+- inspection of the code that was generated - could become meaningless.
+-
+-The overall policiy for version 2 has been that the distribution of
+-statements, operand types and operand locality described in [1] should remain
+-unchanged as much as possible. (Very few changes were necessary; their impact
+-should be negligible.) Also, the order of statements should remain unchanged.
+-Although I am aware of some critical remarks on the benchmark - I agree with
+-several of them - and know some suggestions for improvement, I didn't want to
+-change the benchmark into something different from what has become known as
+-"Dhrystone"; the confusion generated by such a change would probably outweight
+-the benefits. If I were to write a new benchmark program, I wouldn't give it
+-the name "Dhrystone" since this denotes the program published in [1].
+-However, I do recognize the need for a larger number of representative
+-programs that can be used as benchmarks; users should always be encouraged to
+-use more than just one benchmark.
+-
+-The new versions (version 2.1 for C, Pascal and Ada) will be distributed as
+-widely as possible. (Version 2.1 differs from version 2.0 distributed via the
+-UNIX Network Usenet in March 1988 only in a few corrections for minor
+-deficiencies found by users of version 2.0.) Readers who want to use the
+-benchmark for their own measurements can obtain a copy in machine-readable
+-form on floppy disk (MS-DOS or XENIX format) from the author.
+-
+-
+-2. Overall Characteristics of Version 2
+-
+-In general, version 2 follows - in the parts that are significant for
+-performance measurement, i.e. within the measurement loop - the published
+-(Ada) version and the C versions previously distributed. Where the versions
+-distributed by Rick Richardson [2] and Reinhold Weicker have been different,
+-it follows the version distributed by Reinhold Weicker. (However, the
+-differences have been so small that their impact on execution time in all
+-likelihood has been negligible.) The initialization and UNIX instrumentation
+-part - which had been omitted in [1] - follows mostly the ideas of Rick
+-Richardson [2]. However, any changes in the initialization part and in the
+-printing of the result have no impact on performance measurement since they
+-are outside the measaurement loop. As a concession to older compilers, names
+-have been made unique within the first 8 characters for the C version.
+-
+-The original publication of Dhrystone did not contain any statements for time
+-measurement since they are necessarily system-dependent. However, it turned
+-out that it is not enough just to inclose the main procedure of Dhrystone in a
+-loop and to measure the execution time. If the variables that are computed
+-are not used somehow, there is the danger that the compiler considers them as
+-"dead variables" and suppresses code generation for a part of the statements.
+-Therefore in version 2 all variables of "main" are printed at the end of the
+-program. This also permits some plausibility control for correct execution of
+-the benchmark.
+-
+-At several places in the benchmark, code has been added, but only in branches
+-that are not executed. The intention is that optimizing compilers should be
+-prevented from moving code out of the measurement loop, or from removing code
+-altogether. Statements that are executed have been changed in very few places
+-only. In these cases, only the role of some operands has been changed, and it
+-was made sure that the numbers defining the "Dhrystone distribution"
+-(distribution of statements, operand types and locality) still hold as much as
+-possible. Except for sophisticated optimizing compilers, execution times for
+-version 2.1 should be the same as for previous versions.
+-
+-Because of the self-imposed limitation that the order and distribution of the
+-executed statements should not be changed, there are still cases where
+-optimizing compilers may not generate code for some statements. To a certain
+-degree, this is unavoidable for small synthetic benchmarks. Users of the
+-benchmark are advised to check code listings whether code is generated for all
+-statements of Dhrystone.
+-
+-Contrary to the suggestion in the published paper and its realization in the
+-versions previously distributed, no attempt has been made to subtract the time
+-for the measurement loop overhead. (This calculation has proven difficult to
+-implement in a correct way, and its omission makes the program simpler.)
+-However, since the loop check is now part of the benchmark, this does have an
+-impact - though a very minor one - on the distribution statistics which have
+-been updated for this version.
+-
+-
+-3. Discussion of Individual Changes
+-
+-In this section, all changes are described that affect the measurement loop
+-and that are not just renamings of variables. All remarks refer to the C
+-version; the other language versions have been updated similarly.
+-
+-In addition to adding the measurement loop and the printout statements,
+-changes have been made at the following places:
+-
+-o In procedure "main", three statements have been added in the non-executed
+- "then" part of the statement
+-
+- if (Enum_Loc == Func_1 (Ch_Index, 'C'))
+-
+- they are
+-
+- strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 3'RD STRING");
+- Int_2_Loc = Run_Index;
+- Int_Glob = Run_Index;
+-
+- The string assignment prevents movement of the preceding assignment to
+- Str_2_Loc (5'th statement of "main") out of the measurement loop (This
+- probably will not happen for the C version, but it did happen with another
+- language and compiler.) The assignment to Int_2_Loc prevents value
+- propagation for Int_2_Loc, and the assignment to Int_Glob makes the value of
+- Int_Glob possibly dependent from the value of Run_Index.
+-
+-o In the three arithmetic computations at the end of the measurement loop in
+- "main ", the role of some variables has been exchanged, to prevent the
+- division from just cancelling out the multiplication as it was in [1]. A
+- very smart compiler might have recognized this and suppressed code
+- generation for the division.
+-
+-o For Proc_2, no code has been changed, but the values of the actual parameter
+- have changed due to changes in "main".
+-
+-o In Proc_4, the second assignment has been changed from
+-
+- Bool_Loc = Bool_Loc | Bool_Glob;
+-
+- to
+-
+- Bool_Glob = Bool_Loc | Bool_Glob;
+-
+- It now assigns a value to a global variable instead of a local variable
+- (Bool_Loc); Bool_Loc would be a "dead variable" which is not used
+- afterwards.
+-
+-o In Func_1, the statement
+-
+- Ch_1_Glob = Ch_1_Loc;
+-
+- was added in the non-executed "else" part of the "if" statement, to prevent
+- the suppression of code generation for the assignment to Ch_1_Loc.
+-
+-o In Func_2, the second character comparison statement has been changed to
+-
+- if (Ch_Loc == 'R')
+-
+- ('R' instead of 'X') because a comparison with 'X' is implied in the
+- preceding "if" statement.
+-
+- Also in Func_2, the statement
+-
+- Int_Glob = Int_Loc;
+-
+- has been added in the non-executed part of the last "if" statement, in order
+- to prevent Int_Loc from becoming a dead variable.
+-
+-o In Func_3, a non-executed "else" part has been added to the "if" statement.
+- While the program would not be incorrect without this "else" part, it is
+- considered bad programming practice if a function can be left without a
+- return value.
+-
+- To compensate for this change, the (non-executed) "else" part in the "if"
+- statement of Proc_3 was removed.
+-
+-The distribution statistics have been changed only by the addition of the
+-measurement loop iteration (1 additional statement, 4 additional local integer
+-operands) and by the change in Proc_4 (one operand changed from local to
+-global). The distribution statistics in the comment headers have been updated
+-accordingly.
+-
+-
+-4. String Operations
+-
+-The string operations (string assignment and string comparison) have not been
+-changed, to keep the program consistent with the original version.
+-
+-There has been some concern that the string operations are over-represented in
+-the program, and that execution time is dominated by these operations. This
+-was true in particular when optimizing compilers removed too much code in the
+-main part of the program, this should have been mitigated in version 2.
+-
+-It should be noted that this is a language-dependent issue: Dhrystone was
+-first published in Ada, and with Ada or Pascal semantics, the time spent in
+-the string operations is, at least in all implementations known to me,
+-considerably smaller. In Ada and Pascal, assignment and comparison of strings
+-are operators defined in the language, and the upper bounds of the strings
+-occuring in Dhrystone are part of the type information known at compilation
+-time. The compilers can therefore generate efficient inline code. In C,
+-string assignemt and comparisons are not part of the language, so the string
+-operations must be expressed in terms of the C library functions "strcpy" and
+-"strcmp". (ANSI C allows an implementation to use inline code for these
+-functions.) In addition to the overhead caused by additional function calls,
+-these functions are defined for null-terminated strings where the length of
+-the strings is not known at compilation time; the function has to check every
+-byte for the termination condition (the null byte).
+-
+-Obviously, a C library which includes efficiently coded "strcpy" and "strcmp"
+-functions helps to obtain good Dhrystone results. However, I don't think that
+-this is unfair since string functions do occur quite frequently in real
+-programs (editors, command interpreters, etc.). If the strings functions are
+-implemented efficiently, this helps real programs as well as benchmark
+-programs.
+-
+-I admit that the string comparison in Dhrystone terminates later (after
+-scanning 20 characters) than most string comparisons in real programs. For
+-consistency with the original benchmark, I didn't change the program despite
+-this weakness.
+-
+-
+-5. Intended Use of Dhrystone
+-
+-When Dhrystone is used, the following "ground rules" apply:
+-
+-o Separate compilation (Ada and C versions)
+-
+- As mentioned in [1], Dhrystone was written to reflect actual programming
+- practice in systems programming. The division into several compilation
+- units (5 in the Ada version, 2 in the C version) is intended, as is the
+- distribution of inter-module and intra-module subprogram calls. Although on
+- many systems there will be no difference in execution time to a Dhrystone
+- version where all compilation units are merged into one file, the rule is
+- that separate compilation should be used. The intention is that real
+- programming practice, where programs consist of several independently
+- compiled units, should be reflected. This also has implies that the
+- compiler, while compiling one unit, has no information about the use of
+- variables, register allocation etc. occuring in other compilation units.
+- Although in real life compilation units will probably be larger, the
+- intention is that these effects of separate compilation are modeled in
+- Dhrystone.
+-
+- A few language systems have post-linkage optimization available (e.g., final
+- register allocation is performed after linkage). This is a borderline case:
+- Post-linkage optimization involves additional program preparation time
+- (although not as much as compilation in one unit) which may prevent its
+- general use in practical programming. I think that since it defeats the
+- intentions given above, it should not be used for Dhrystone.
+-
+- Unfortunately, ISO/ANSI Pascal does not contain language features for
+- separate compilation. Although most commercial Pascal compilers provide
+- separate compilation in some way, we cannot use it for Dhrystone since such
+- a version would not be portable. Therefore, no attempt has been made to
+- provide a Pascal version with several compilation units.
+-
+-o No procedure merging
+-
+- Although Dhrystone contains some very short procedures where execution would
+- benefit from procedure merging (inlining, macro expansion of procedures),
+- procedure merging is not to be used. The reason is that the percentage of
+- procedure and function calls is part of the "Dhrystone distribution" of
+- statements contained in [1]. This restriction does not hold for the string
+- functions of the C version since ANSI C allows an implementation to use
+- inline code for these functions.
+-
+-o Other optimizations are allowed, but they should be indicated
+-
+- It is often hard to draw an exact line between "normal code generation" and
+- "optimization" in compilers: Some compilers perform operations by default
+- that are invoked in other compilers only when optimization is explicitly
+- requested. Also, we cannot avoid that in benchmarking people try to achieve
+- results that look as good as possible. Therefore, optimizations performed
+- by compilers - other than those listed above - are not forbidden when
+- Dhrystone execution times are measured. Dhrystone is not intended to be
+- non-optimizable but is intended to be similarly optimizable as normal
+- programs. For example, there are several places in Dhrystone where
+- performance benefits from optimizations like common subexpression
+- elimination, value propagation etc., but normal programs usually also
+- benefit from these optimizations. Therefore, no effort was made to
+- artificially prevent such optimizations. However, measurement reports
+- should indicate which compiler optimization levels have been used, and
+- reporting results with different levels of compiler optimization for the
+- same hardware is encouraged.
+-
+-o Default results are those without "register" declarations (C version)
+-
+- When Dhrystone results are quoted without additional qualification, they
+- should be understood as results obtained without use of the "register"
+- attribute. Good compilers should be able to make good use of registers even
+- without explicit register declarations ([3], p. 193).
+-
+-Of course, for experimental purposes, post-linkage optimization, procedure
+-merging and/or compilation in one unit can be done to determine their effects.
+-However, Dhrystone numbers obtained under these conditions should be
+-explicitly marked as such; "normal" Dhrystone results should be understood as
+-results obtained following the ground rules listed above.
+-
+-In any case, for serious performance evaluation, users are advised to ask for
+-code listings and to check them carefully. In this way, when results for
+-different systems are compared, the reader can get a feeling how much
+-performance difference is due to compiler optimization and how much is due to
+-hardware speed.
+-
+-
+-6. Acknowledgements
+-
+-The C version 2.1 of Dhrystone has been developed in cooperation with Rick
+-Richardson (Tinton Falls, NJ), it incorporates many ideas from the "Version
+-1.1" distributed previously by him over the UNIX network Usenet. Through his
+-activity with Usenet, Rick Richardson has made a very valuable contribution to
+-the dissemination of the benchmark. I also thank Chaim Benedelac (National
+-Semiconductor), David Ditzel (SUN), Earl Killian and John Mashey (MIPS), Alan
+-Smith and Rafael Saavedra-Barrera (UC at Berkeley) for their help with
+-comments on earlier versions of the benchmark.
+-
+-
+-7. Bibliography
+-
+-[1]
+- Reinhold P. Weicker: Dhrystone: A Synthetic Systems Programming Benchmark.
+- Communications of the ACM 27, 10 (Oct. 1984), 1013-1030
+-
+-[2]
+- Rick Richardson: Dhrystone 1.1 Benchmark Summary (and Program Text)
+- Informal Distribution via "Usenet", Last Version Known to me: Sept. 21,
+- 1987
+-
+-[3]
+- Brian W. Kernighan and Dennis M. Ritchie: The C Programming Language.
+- Prentice-Hall, Englewood Cliffs (NJ) 1978
+-
+//GO.SYSIN DD RATIONALE
+echo README_C 1>&2
+sed >README_C <<'//GO.SYSIN DD README_C' 's/^-//'
+-This "shar" file contains the documentation for the
+-electronic mail distribution of the Dhrystone benchmark (C version 2.1);
+-a companion "shar" file contains the source code.
+-(Because of mail length restrictions for some mailers, I have
+-split the distribution in two parts.)
+-
+-For versions in other languages, see the other "shar" files.
+-
+-Files containing the C version (*.h: Header File, *.c: C Modules)
+-
+- dhry.h
+- dhry_1.c
+- dhry_2.c
+-
+-The file RATIONALE contains the article
+-
+- "Dhrystone Benchmark: Rationale for Version 2 and Measurement Rules"
+-
+-which has been published, together with the C source code (Version 2.0),
+-in SIGPLAN Notices vol. 23, no. 8 (Aug. 1988), pp. 49-62.
+-This article explains all changes that have been made for Version 2,
+-compared with the version of the original publication
+-in Communications of the ACM vol. 27, no. 10 (Oct. 1984), pp. 1013-1030.
+-It also contains "ground rules" for benchmarking with Dhrystone
+-which should be followed by everyone who uses the program and publishes
+-Dhrystone results.
+-
+-Compared with the Version 2.0 published in SIGPLAN Notices, Version 2.1
+-contains a few corrections that have been made after Version 2.0 was
+-distriobuted over the UNIX network Usenet. These small differences between
+-Version 2.0 and 2.1 should not affect execution time measurements.
+-For those who want to compare the exact contents of both versions,
+-the file "dhry_c.dif" contains the differences between the two versions,
+-as generated by a file comparison of the corresponding files with the
+-UNIX utility "diff".
+-
+-The file VARIATIONS contains the article
+-
+- "Understanding Variations in Dhrystone Performance"
+-
+-which has been published in Microprocessor Report, May 1989
+-(Editor: M. Slater), pp. 16-17. It describes the points that users
+-should know if C Dhrystone results are compared.
+-
+-Recipients of this shar file who perform measurements are asked
+-to send measurement results to the author and/or to Rick Richardson.
+-Rick Richardson publishes regularly Dhrystone results on the UNIX network
+-Usenet. For submissions of results to him (preferably by electronic mail,
+-see address in the program header), he has provided a form which is contained
+-in the file "submit.frm".
+-
+-
+-The following files are contained in other "shar" files:
+-
+-Files containing the Ada version (*.s: Specifications, *.b: Bodies):
+-
+- d_global.s
+- d_main.b
+- d_pack_1.b
+- d_pack_1.s
+- d_pack_2.b
+- d_pack_2.s
+-
+-File containing the Pascal version:
+-
+- dhry.p
+-
+-
+-February 22, 1990
+-
+- Reinhold P. Weicker
+- Siemens AG, AUT E 51
+- Postfach 3220
+- D-8520 Erlangen
+- Germany (West)
+-
+- Phone: [xxx-49]-9131-7-20330 (8-17 Central European Time)
+- UUCP: ..!mcsun!unido!estevax!weicker
+//GO.SYSIN DD README_C
+echo VARIATIONS 1>&2
+sed >VARIATIONS <<'//GO.SYSIN DD VARIATIONS' 's/^-//'
+-
+- Understanding Variations in Dhrystone Performance
+-
+-
+-
+- By Reinhold P. Weicker, Siemens AG, AUT E 51, Erlangen
+-
+-
+-
+- April 1989
+-
+-
+- This article has appeared in:
+-
+-
+- Microprocessor Report, May 1989 (Editor: M. Slater), pp. 16-17
+-
+-
+-
+-
+-Microprocessor manufacturers tend to credit all the performance measured by
+-benchmarks to the speed of their processors, they often don't even mention the
+-programming language and compiler used. In their detailed documents, usually
+-called "performance brief" or "performance report," they usually do give more
+-details. However, these details are often lost in the press releases and other
+-marketing statements. For serious performance evaluation, it is necessary to
+-study the code generated by the various compilers.
+-
+-Dhrystone was originally published in Ada (Communications of the ACM, Oct.
+-1984). However, since good Ada compilers were rare at this time and, together
+-with UNIX, C became more and more popular, the C version of Dhrystone is the
+-one now mainly used in industry. There are "official" versions 2.1 for Ada,
+-Pascal, and C, which are as close together as the languages' semantic
+-differences permit.
+-
+-Dhrystone contains two statements where the programming language and its
+-translation play a major part in the execution time measured by the benchmark:
+-
+- o String assignment (in procedure Proc_0 / main)
+- o String comparison (in function Func_2)
+-
+-In Ada and Pascal, strings are arrays of characters where the length of the
+-string is part of the type information known at compile time. In C, strings
+-are also arrays of characters, but there are no operators defined in the
+-language for assignment and comparison of strings. Instead, functions
+-"strcpy" and "strcmp" are used. These functions are defined for strings of
+-arbitrary length, and make use of the fact that strings in C have to end with
+-a terminating null byte. For general-purpose calls to these functions, the
+-implementor can assume nothing about the length and the alignment of the
+-strings involved.
+-
+-The C version of Dhrystone spends a relatively large amount of time in these
+-two functions. Some time ago, I made measurements on a VAX 11/785 with the
+-Berkeley UNIX (4.2) compilers (often-used compilers, but certainly not the
+-most advanced). In the C version, 23% of the time was spent in the string
+-functions; in the Pascal version, only 10%. On good RISC machines (where less
+-time is spent in the procedure calling sequence than on a VAX) and with better
+-optimizing compilers, the percentage is higher; MIPS has reported 34% for an
+-R3000. Because of this effect, Pascal and Ada Dhrystone results are usually
+-better than C results (except when the optimization quality of the C compiler
+-is considerably better than that of the other compilers).
+-
+-Several people have noted that the string operations are over-represented in
+-Dhrystone, mainly because the strings occurring in Dhrystone are longer than
+-average strings. I admit that this is true, and have said so in my SIGPLAN
+-Notices paper (Aug. 1988); however, I didn't want to generate confusion by
+-changing the string lengths from version 1 to version 2.
+-
+-Even if they are somewhat over-represented in Dhrystone, string operations are
+-frequent enough that it makes sense to implement them in the most efficient
+-way possible, not only for benchmarking purposes. This means that they can
+-and should be written in assembly language code. ANSI C also explicitly allows
+-the strings functions to be implemented as macros, i.e. by inline code.
+-
+-There is also a third way to speed up the "strcpy" statement in Dhrystone: For
+-this particular "strcpy" statement, the source of the assignment is a string
+-constant. Therefore, in contrast to calls to "strcpy" in the general case, the
+-compiler knows the length and alignment of the strings involved at compile
+-time and can generate code in the same efficient way as a Pascal compiler
+-(word instructions instead of byte instructions).
+-
+-This is not allowed in the case of the "strcmp" call: Here, the addresses are
+-formal procedure parameters, and no assumptions can be made about the length
+-or alignment of the strings. Any such assumptions would indicate an incorrect
+-implementation. They might work for Dhrystone, where the strings are in fact
+-word-aligned with typical compilers, but other programs would deliver
+-incorrect results.
+-
+-So, for an apple-to-apple comparison between processors, and not between
+-several possible (legal or illegal) degrees of compiler optimization, one
+-should check that the systems are comparable with respect to the following
+-three points:
+-
+- (1) String functions in assembly language vs. in C
+-
+- Frequently used functions such as the string functions can and should be
+- written in assembly language, and all serious C language systems known
+- to me do this. (I list this point for completeness only.) Note that
+- processors with an instruction that checks a word for a null byte (such
+- as AMD's 29000 and Intel's 80960) have an advantage here. (This
+- advantage decreases relatively if optimization (3) is applied.) Due to
+- the length of the strings involved in Dhrystone, this advantage may be
+- considered too high in perspective, but it is certainly legal to use
+- such instructions - after all, these situations are what they were
+- invented for.
+-
+- (2) String function code inline vs. as library functions.
+-
+- ANSI C has created a new situation, compared with the older
+- Kernighan/Ritchie C. In the original C, the definition of the string
+- function was not part of the language. Now it is, and inlining is
+- explicitly allowed. I probably should have stated more clearly in my
+- SIGPLAN Notices paper that the rule "No procedure inlining for
+- Dhrystone" referred to the user level procedures only and not to the
+- library routines.
+-
+- (3) Fixed-length and alignment assumptions for the strings
+-
+- Compilers should be allowed to optimize in these cases if (and only if)
+- it is safe to do so. For Dhrystone, this is the "strcpy" statement, but
+- not the "strcmp" statement (unless, of course, the "strcmp" code
+- explicitly checks the alignment at execution time and branches
+- accordingly). A "Dhrystone switch" for the compiler that causes the
+- generation of code that may not work under certain circumstances is
+- certainly inappropriate for comparisons. It has been reported in Usenet
+- that some C compilers provide such a compiler option; since I don't have
+- access to all C compilers involved, I cannot verify this.
+-
+- If the fixed-length and word-alignment assumption can be used, a wide
+- bus that permits fast multi-word load instructions certainly does help;
+- however, this fact by itself should not make a really big difference.
+-
+-A check of these points - something that is necessary for a thorough
+-evaluation and comparison of the Dhrystone performance claims - requires
+-object code listings as well as listings for the string functions (strcpy,
+-strcmp) that are possibly called by the program.
+-
+-I don't pretend that Dhrystone is a perfect tool to measure the integer
+-performance of microprocessors. The more it is used and discussed, the more I
+-myself learn about aspects that I hadn't noticed yet when I wrote the program.
+-And of course, the very success of a benchmark program is a danger in that
+-people may tune their compilers and/or hardware to it, and with this action
+-make it less useful.
+-
+-Whetstone and Linpack have their critical points also: The Whetstone rating
+-depends heavily on the speed of the mathematical functions (sine, sqrt, ...),
+-and Linpack is sensitive to data alignment for some cache configurations.
+-
+-Introduction of a standard set of public domain benchmark software (something
+-the SPEC effort attempts) is certainly a worthwhile thing. In the meantime,
+-people will continue to use whatever is available and widely distributed, and
+-Dhrystone ratings are probably still better than MIPS ratings if these are -
+-as often in industry - based on no reproducible derivation. However, any
+-serious performance evaluation requires more than just a comparison of raw
+-numbers; one has to make sure that the numbers have been obtained in a
+-comparable way.
+-
+//GO.SYSIN DD VARIATIONS
+echo dhry.h 1>&2
+sed >dhry.h <<'//GO.SYSIN DD dhry.h' 's/^-//'
+-/*
+- ****************************************************************************
+- *
+- * "DHRYSTONE" Benchmark Program
+- * -----------------------------
+- *
+- * Version: C, Version 2.1
+- *
+- * File: dhry.h (part 1 of 3)
+- *
+- * Date: May 25, 1988
+- *
+- * Author: Reinhold P. Weicker
+- * Siemens AG, AUT E 51
+- * Postfach 3220
+- * 8520 Erlangen
+- * Germany (West)
+- * Phone: [+49]-9131-7-20330
+- * (8-17 Central European Time)
+- * Usenet: ..!mcsun!unido!estevax!weicker
+- *
+- * Original Version (in Ada) published in
+- * "Communications of the ACM" vol. 27., no. 10 (Oct. 1984),
+- * pp. 1013 - 1030, together with the statistics
+- * on which the distribution of statements etc. is based.
+- *
+- * In this C version, the following C library functions are used:
+- * - strcpy, strcmp (inside the measurement loop)
+- * - printf, scanf (outside the measurement loop)
+- * In addition, Berkeley UNIX system calls "times ()" or "time ()"
+- * are used for execution time measurement. For measurements
+- * on other systems, these calls have to be changed.
+- *
+- * Collection of Results:
+- * Reinhold Weicker (address see above) and
+- *
+- * Rick Richardson
+- * PC Research. Inc.
+- * 94 Apple Orchard Drive
+- * Tinton Falls, NJ 07724
+- * Phone: (201) 389-8963 (9-17 EST)
+- * Usenet: ...!uunet!pcrat!rick
+- *
+- * Please send results to Rick Richardson and/or Reinhold Weicker.
+- * Complete information should be given on hardware and software used.
+- * Hardware information includes: Machine type, CPU, type and size
+- * of caches; for microprocessors: clock frequency, memory speed
+- * (number of wait states).
+- * Software information includes: Compiler (and runtime library)
+- * manufacturer and version, compilation switches, OS version.
+- * The Operating System version may give an indication about the
+- * compiler; Dhrystone itself performs no OS calls in the measurement loop.
+- *
+- * The complete output generated by the program should be mailed
+- * such that at least some checks for correctness can be made.
+- *
+- ***************************************************************************
+- *
+- * History: This version C/2.1 has been made for two reasons:
+- *
+- * 1) There is an obvious need for a common C version of
+- * Dhrystone, since C is at present the most popular system
+- * programming language for the class of processors
+- * (microcomputers, minicomputers) where Dhrystone is used most.
+- * There should be, as far as possible, only one C version of
+- * Dhrystone such that results can be compared without
+- * restrictions. In the past, the C versions distributed
+- * by Rick Richardson (Version 1.1) and by Reinhold Weicker
+- * had small (though not significant) differences.
+- *
+- * 2) As far as it is possible without changes to the Dhrystone
+- * statistics, optimizing compilers should be prevented from
+- * removing significant statements.
+- *
+- * This C version has been developed in cooperation with
+- * Rick Richardson (Tinton Falls, NJ), it incorporates many
+- * ideas from the "Version 1.1" distributed previously by
+- * him over the UNIX network Usenet.
+- * I also thank Chaim Benedelac (National Semiconductor),
+- * David Ditzel (SUN), Earl Killian and John Mashey (MIPS),
+- * Alan Smith and Rafael Saavedra-Barrera (UC at Berkeley)
+- * for their help with comments on earlier versions of the
+- * benchmark.
+- *
+- * Changes: In the initialization part, this version follows mostly
+- * Rick Richardson's version distributed via Usenet, not the
+- * version distributed earlier via floppy disk by Reinhold Weicker.
+- * As a concession to older compilers, names have been made
+- * unique within the first 8 characters.
+- * Inside the measurement loop, this version follows the
+- * version previously distributed by Reinhold Weicker.
+- *
+- * At several places in the benchmark, code has been added,
+- * but within the measurement loop only in branches that
+- * are not executed. The intention is that optimizing compilers
+- * should be prevented from moving code out of the measurement
+- * loop, or from removing code altogether. Since the statements
+- * that are executed within the measurement loop have NOT been
+- * changed, the numbers defining the "Dhrystone distribution"
+- * (distribution of statements, operand types and locality)
+- * still hold. Except for sophisticated optimizing compilers,
+- * execution times for this version should be the same as
+- * for previous versions.
+- *
+- * Since it has proven difficult to subtract the time for the
+- * measurement loop overhead in a correct way, the loop check
+- * has been made a part of the benchmark. This does have
+- * an impact - though a very minor one - on the distribution
+- * statistics which have been updated for this version.
+- *
+- * All changes within the measurement loop are described
+- * and discussed in the companion paper "Rationale for
+- * Dhrystone version 2".
+- *
+- * Because of the self-imposed limitation that the order and
+- * distribution of the executed statements should not be
+- * changed, there are still cases where optimizing compilers
+- * may not generate code for some statements. To a certain
+- * degree, this is unavoidable for small synthetic benchmarks.
+- * Users of the benchmark are advised to check code listings
+- * whether code is generated for all statements of Dhrystone.
+- *
+- * Version 2.1 is identical to version 2.0 distributed via
+- * the UNIX network Usenet in March 1988 except that it corrects
+- * some minor deficiencies that were found by users of version 2.0.
+- * The only change within the measurement loop is that a
+- * non-executed "else" part was added to the "if" statement in
+- * Func_3, and a non-executed "else" part removed from Proc_3.
+- *
+- ***************************************************************************
+- *
+- * Defines: The following "Defines" are possible:
+- * -DREG=register (default: Not defined)
+- * As an approximation to what an average C programmer
+- * might do, the "register" storage class is applied
+- * (if enabled by -DREG=register)
+- * - for local variables, if they are used (dynamically)
+- * five or more times
+- * - for parameters if they are used (dynamically)
+- * six or more times
+- * Note that an optimal "register" strategy is
+- * compiler-dependent, and that "register" declarations
+- * do not necessarily lead to faster execution.
+- * -DNOSTRUCTASSIGN (default: Not defined)
+- * Define if the C compiler does not support
+- * assignment of structures.
+- * -DNOENUMS (default: Not defined)
+- * Define if the C compiler does not support
+- * enumeration types.
+- * -DTIMES (default)
+- * -DTIME
+- * The "times" function of UNIX (returning process times)
+- * or the "time" function (returning wallclock time)
+- * is used for measurement.
+- * For single user machines, "time ()" is adequate. For
+- * multi-user machines where you cannot get single-user
+- * access, use the "times ()" function. If you have
+- * neither, use a stopwatch in the dead of night.
+- * "printf"s are provided marking the points "Start Timer"
+- * and "Stop Timer". DO NOT use the UNIX "time(1)"
+- * command, as this will measure the total time to
+- * run this program, which will (erroneously) include
+- * the time to allocate storage (malloc) and to perform
+- * the initialization.
+- * -DHZ=nnn
+- * In Berkeley UNIX, the function "times" returns process
+- * time in 1/HZ seconds, with HZ = 60 for most systems.
+- * CHECK YOUR SYSTEM DESCRIPTION BEFORE YOU JUST APPLY
+- * A VALUE.
+- *
+- ***************************************************************************
+- *
+- * Compilation model and measurement (IMPORTANT):
+- *
+- * This C version of Dhrystone consists of three files:
+- * - dhry.h (this file, containing global definitions and comments)
+- * - dhry_1.c (containing the code corresponding to Ada package Pack_1)
+- * - dhry_2.c (containing the code corresponding to Ada package Pack_2)
+- *
+- * The following "ground rules" apply for measurements:
+- * - Separate compilation
+- * - No procedure merging
+- * - Otherwise, compiler optimizations are allowed but should be indicated
+- * - Default results are those without register declarations
+- * See the companion paper "Rationale for Dhrystone Version 2" for a more
+- * detailed discussion of these ground rules.
+- *
+- * For 16-Bit processors (e.g. 80186, 80286), times for all compilation
+- * models ("small", "medium", "large" etc.) should be given if possible,
+- * together with a definition of these models for the compiler system used.
+- *
+- **************************************************************************
+- *
+- * Dhrystone (C version) statistics:
+- *
+- * [Comment from the first distribution, updated for version 2.
+- * Note that because of language differences, the numbers are slightly
+- * different from the Ada version.]
+- *
+- * The following program contains statements of a high level programming
+- * language (here: C) in a distribution considered representative:
+- *
+- * assignments 52 (51.0 %)
+- * control statements 33 (32.4 %)
+- * procedure, function calls 17 (16.7 %)
+- *
+- * 103 statements are dynamically executed. The program is balanced with
+- * respect to the three aspects:
+- *
+- * - statement type
+- * - operand type
+- * - operand locality
+- * operand global, local, parameter, or constant.
+- *
+- * The combination of these three aspects is balanced only approximately.
+- *
+- * 1. Statement Type:
+- * ----------------- number
+- *
+- * V1 = V2 9
+- * (incl. V1 = F(..)
+- * V = Constant 12
+- * Assignment, 7
+- * with array element
+- * Assignment, 6
+- * with record component
+- * --
+- * 34 34
+- *
+- * X = Y +|-|"&&"|"|" Z 5
+- * X = Y +|-|"==" Constant 6
+- * X = X +|- 1 3
+- * X = Y *|/ Z 2
+- * X = Expression, 1
+- * two operators
+- * X = Expression, 1
+- * three operators
+- * --
+- * 18 18
+- *
+- * if .... 14
+- * with "else" 7
+- * without "else" 7
+- * executed 3
+- * not executed 4
+- * for ... 7 | counted every time
+- * while ... 4 | the loop condition
+- * do ... while 1 | is evaluated
+- * switch ... 1
+- * break 1
+- * declaration with 1
+- * initialization
+- * --
+- * 34 34
+- *
+- * P (...) procedure call 11
+- * user procedure 10
+- * library procedure 1
+- * X = F (...)
+- * function call 6
+- * user function 5
+- * library function 1
+- * --
+- * 17 17
+- * ---
+- * 103
+- *
+- * The average number of parameters in procedure or function calls
+- * is 1.82 (not counting the function values as implicit parameters).
+- *
+- *
+- * 2. Operators
+- * ------------
+- * number approximate
+- * percentage
+- *
+- * Arithmetic 32 50.8
+- *
+- * + 21 33.3
+- * - 7 11.1
+- * * 3 4.8
+- * / (int div) 1 1.6
+- *
+- * Comparison 27 42.8
+- *
+- * == 9 14.3
+- * /= 4 6.3
+- * > 1 1.6
+- * < 3 4.8
+- * >= 1 1.6
+- * <= 9 14.3
+- *
+- * Logic 4 6.3
+- *
+- * && (AND-THEN) 1 1.6
+- * | (OR) 1 1.6
+- * ! (NOT) 2 3.2
+- *
+- * -- -----
+- * 63 100.1
+- *
+- *
+- * 3. Operand Type (counted once per operand reference):
+- * ---------------
+- * number approximate
+- * percentage
+- *
+- * Integer 175 72.3 %
+- * Character 45 18.6 %
+- * Pointer 12 5.0 %
+- * String30 6 2.5 %
+- * Array 2 0.8 %
+- * Record 2 0.8 %
+- * --- -------
+- * 242 100.0 %
+- *
+- * When there is an access path leading to the final operand (e.g. a record
+- * component), only the final data type on the access path is counted.
+- *
+- *
+- * 4. Operand Locality:
+- * -------------------
+- * number approximate
+- * percentage
+- *
+- * local variable 114 47.1 %
+- * global variable 22 9.1 %
+- * parameter 45 18.6 %
+- * value 23 9.5 %
+- * reference 22 9.1 %
+- * function result 6 2.5 %
+- * constant 55 22.7 %
+- * --- -------
+- * 242 100.0 %
+- *
+- *
+- * The program does not compute anything meaningful, but it is syntactically
+- * and semantically correct. All variables have a value assigned to them
+- * before they are used as a source operand.
+- *
+- * There has been no explicit effort to account for the effects of a
+- * cache, or to balance the use of long or short displacements for code or
+- * data.
+- *
+- ***************************************************************************
+- */
+-
+-/* Compiler and system dependent definitions: */
+-
+-#ifndef TIME
+-#define TIMES
+-#endif
+- /* Use times(2) time function unless */
+- /* explicitly defined otherwise */
+-
+-#ifdef TIMES
+-#include <sys/types.h>
+-#include <sys/times.h>
+- /* for "times" */
+-#endif
+-
+-#define Mic_secs_Per_Second 1000000.0
+- /* Berkeley UNIX C returns process times in seconds/HZ */
+-
+-#ifdef NOSTRUCTASSIGN
+-#define structassign(d, s) memcpy(&(d), &(s), sizeof(d))
+-#else
+-#define structassign(d, s) d = s
+-#endif
+-
+-#ifdef NOENUM
+-#define Ident_1 0
+-#define Ident_2 1
+-#define Ident_3 2
+-#define Ident_4 3
+-#define Ident_5 4
+- typedef int Enumeration;
+-#else
+- typedef enum {Ident_1, Ident_2, Ident_3, Ident_4, Ident_5}
+- Enumeration;
+-#endif
+- /* for boolean and enumeration types in Ada, Pascal */
+-
+-/* General definitions: */
+-
+-#include <stdio.h>
+- /* for strcpy, strcmp */
+-
+-#define Null 0
+- /* Value of a Null pointer */
+-#define true 1
+-#define false 0
+-
+-typedef int One_Thirty;
+-typedef int One_Fifty;
+-typedef char Capital_Letter;
+-typedef int Boolean;
+-typedef char Str_30 [31];
+-typedef int Arr_1_Dim [50];
+-typedef int Arr_2_Dim [50] [50];
+-
+-typedef struct record
+- {
+- struct record *Ptr_Comp;
+- Enumeration Discr;
+- union {
+- struct {
+- Enumeration Enum_Comp;
+- int Int_Comp;
+- char Str_Comp [31];
+- } var_1;
+- struct {
+- Enumeration E_Comp_2;
+- char Str_2_Comp [31];
+- } var_2;
+- struct {
+- char Ch_1_Comp;
+- char Ch_2_Comp;
+- } var_3;
+- } variant;
+- } Rec_Type, *Rec_Pointer;
+-
+-
+//GO.SYSIN DD dhry.h
+echo dhry_1.c 1>&2
+sed >dhry_1.c <<'//GO.SYSIN DD dhry_1.c' 's/^-//'
+-/*
+- ****************************************************************************
+- *
+- * "DHRYSTONE" Benchmark Program
+- * -----------------------------
+- *
+- * Version: C, Version 2.1
+- *
+- * File: dhry_1.c (part 2 of 3)
+- *
+- * Date: May 25, 1988
+- *
+- * Author: Reinhold P. Weicker
+- *
+- ****************************************************************************
+- */
+-
+-#include "dhry.h"
+-
+-/* Global Variables: */
+-
+-Rec_Pointer Ptr_Glob,
+- Next_Ptr_Glob;
+-int Int_Glob;
+-Boolean Bool_Glob;
+-char Ch_1_Glob,
+- Ch_2_Glob;
+-int Arr_1_Glob [50];
+-int Arr_2_Glob [50] [50];
+-
+-extern char *malloc ();
+-Enumeration Func_1 ();
+- /* forward declaration necessary since Enumeration may not simply be int */
+-
+-#ifndef REG
+- Boolean Reg = false;
+-#define REG
+- /* REG becomes defined as empty */
+- /* i.e. no register variables */
+-#else
+- Boolean Reg = true;
+-#endif
+-
+-/* variables for time measurement: */
+-
+-#ifdef TIMES
+-struct tms time_info;
+-extern int times ();
+- /* see library function "times" */
+-#define Too_Small_Time 120
+- /* Measurements should last at least about 2 seconds */
+-#endif
+-#ifdef TIME
+-extern long time();
+- /* see library function "time" */
+-#define Too_Small_Time 2
+- /* Measurements should last at least 2 seconds */
+-#endif
+-
+-long Begin_Time,
+- End_Time,
+- User_Time;
+-float Microseconds,
+- Dhrystones_Per_Second;
+-
+-/* end of variables for time measurement */
+-
+-
+-main ()
+-/*****/
+-
+- /* main program, corresponds to procedures */
+- /* Main and Proc_0 in the Ada version */
+-{
+- One_Fifty Int_1_Loc;
+- REG One_Fifty Int_2_Loc;
+- One_Fifty Int_3_Loc;
+- REG char Ch_Index;
+- Enumeration Enum_Loc;
+- Str_30 Str_1_Loc;
+- Str_30 Str_2_Loc;
+- REG int Run_Index;
+- REG int Number_Of_Runs;
+-
+- /* Initializations */
+-
+- Next_Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type));
+- Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type));
+-
+- Ptr_Glob->Ptr_Comp = Next_Ptr_Glob;
+- Ptr_Glob->Discr = Ident_1;
+- Ptr_Glob->variant.var_1.Enum_Comp = Ident_3;
+- Ptr_Glob->variant.var_1.Int_Comp = 40;
+- strcpy (Ptr_Glob->variant.var_1.Str_Comp,
+- "DHRYSTONE PROGRAM, SOME STRING");
+- strcpy (Str_1_Loc, "DHRYSTONE PROGRAM, 1'ST STRING");
+-
+- Arr_2_Glob [8][7] = 10;
+- /* Was missing in published program. Without this statement, */
+- /* Arr_2_Glob [8][7] would have an undefined value. */
+- /* Warning: With 16-Bit processors and Number_Of_Runs > 32000, */
+- /* overflow may occur for this array element. */
+-
+- printf ("\n");
+- printf ("Dhrystone Benchmark, Version 2.1 (Language: C)\n");
+- printf ("\n");
+- if (Reg)
+- {
+- printf ("Program compiled with 'register' attribute\n");
+- printf ("\n");
+- }
+- else
+- {
+- printf ("Program compiled without 'register' attribute\n");
+- printf ("\n");
+- }
+- printf ("Please give the number of runs through the benchmark: ");
+- {
+- int n;
+- scanf ("%d", &n);
+- Number_Of_Runs = n;
+- }
+- printf ("\n");
+-
+- printf ("Execution starts, %d runs through Dhrystone\n", Number_Of_Runs);
+-
+- /***************/
+- /* Start timer */
+- /***************/
+-
+-#ifdef TIMES
+- times (&time_info);
+- Begin_Time = (long) time_info.tms_utime;
+-#endif
+-#ifdef TIME
+- Begin_Time = time ( (long *) 0);
+-#endif
+-
+- for (Run_Index = 1; Run_Index <= Number_Of_Runs; ++Run_Index)
+- {
+-
+- Proc_5();
+- Proc_4();
+- /* Ch_1_Glob == 'A', Ch_2_Glob == 'B', Bool_Glob == true */
+- Int_1_Loc = 2;
+- Int_2_Loc = 3;
+- strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 2'ND STRING");
+- Enum_Loc = Ident_2;
+- Bool_Glob = ! Func_2 (Str_1_Loc, Str_2_Loc);
+- /* Bool_Glob == 1 */
+- while (Int_1_Loc < Int_2_Loc) /* loop body executed once */
+- {
+- Int_3_Loc = 5 * Int_1_Loc - Int_2_Loc;
+- /* Int_3_Loc == 7 */
+- Proc_7 (Int_1_Loc, Int_2_Loc, &Int_3_Loc);
+- /* Int_3_Loc == 7 */
+- Int_1_Loc += 1;
+- } /* while */
+- /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */
+- Proc_8 (Arr_1_Glob, Arr_2_Glob, Int_1_Loc, Int_3_Loc);
+- /* Int_Glob == 5 */
+- Proc_1 (Ptr_Glob);
+- for (Ch_Index = 'A'; Ch_Index <= Ch_2_Glob; ++Ch_Index)
+- /* loop body executed twice */
+- {
+- if (Enum_Loc == Func_1 (Ch_Index, 'C'))
+- /* then, not executed */
+- {
+- Proc_6 (Ident_1, &Enum_Loc);
+- strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 3'RD STRING");
+- Int_2_Loc = Run_Index;
+- Int_Glob = Run_Index;
+- }
+- }
+- /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */
+- Int_2_Loc = Int_2_Loc * Int_1_Loc;
+- Int_1_Loc = Int_2_Loc / Int_3_Loc;
+- Int_2_Loc = 7 * (Int_2_Loc - Int_3_Loc) - Int_1_Loc;
+- /* Int_1_Loc == 1, Int_2_Loc == 13, Int_3_Loc == 7 */
+- Proc_2 (&Int_1_Loc);
+- /* Int_1_Loc == 5 */
+-
+- } /* loop "for Run_Index" */
+-
+- /**************/
+- /* Stop timer */
+- /**************/
+-
+-#ifdef TIMES
+- times (&time_info);
+- End_Time = (long) time_info.tms_utime;
+-#endif
+-#ifdef TIME
+- End_Time = time ( (long *) 0);
+-#endif
+-
+- printf ("Execution ends\n");
+- printf ("\n");
+- printf ("Final values of the variables used in the benchmark:\n");
+- printf ("\n");
+- printf ("Int_Glob: %d\n", Int_Glob);
+- printf (" should be: %d\n", 5);
+- printf ("Bool_Glob: %d\n", Bool_Glob);
+- printf (" should be: %d\n", 1);
+- printf ("Ch_1_Glob: %c\n", Ch_1_Glob);
+- printf (" should be: %c\n", 'A');
+- printf ("Ch_2_Glob: %c\n", Ch_2_Glob);
+- printf (" should be: %c\n", 'B');
+- printf ("Arr_1_Glob[8]: %d\n", Arr_1_Glob[8]);
+- printf (" should be: %d\n", 7);
+- printf ("Arr_2_Glob[8][7]: %d\n", Arr_2_Glob[8][7]);
+- printf (" should be: Number_Of_Runs + 10\n");
+- printf ("Ptr_Glob->\n");
+- printf (" Ptr_Comp: %d\n", (int) Ptr_Glob->Ptr_Comp);
+- printf (" should be: (implementation-dependent)\n");
+- printf (" Discr: %d\n", Ptr_Glob->Discr);
+- printf (" should be: %d\n", 0);
+- printf (" Enum_Comp: %d\n", Ptr_Glob->variant.var_1.Enum_Comp);
+- printf (" should be: %d\n", 2);
+- printf (" Int_Comp: %d\n", Ptr_Glob->variant.var_1.Int_Comp);
+- printf (" should be: %d\n", 17);
+- printf (" Str_Comp: %s\n", Ptr_Glob->variant.var_1.Str_Comp);
+- printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n");
+- printf ("Next_Ptr_Glob->\n");
+- printf (" Ptr_Comp: %d\n", (int) Next_Ptr_Glob->Ptr_Comp);
+- printf (" should be: (implementation-dependent), same as above\n");
+- printf (" Discr: %d\n", Next_Ptr_Glob->Discr);
+- printf (" should be: %d\n", 0);
+- printf (" Enum_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Enum_Comp);
+- printf (" should be: %d\n", 1);
+- printf (" Int_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Int_Comp);
+- printf (" should be: %d\n", 18);
+- printf (" Str_Comp: %s\n",
+- Next_Ptr_Glob->variant.var_1.Str_Comp);
+- printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n");
+- printf ("Int_1_Loc: %d\n", Int_1_Loc);
+- printf (" should be: %d\n", 5);
+- printf ("Int_2_Loc: %d\n", Int_2_Loc);
+- printf (" should be: %d\n", 13);
+- printf ("Int_3_Loc: %d\n", Int_3_Loc);
+- printf (" should be: %d\n", 7);
+- printf ("Enum_Loc: %d\n", Enum_Loc);
+- printf (" should be: %d\n", 1);
+- printf ("Str_1_Loc: %s\n", Str_1_Loc);
+- printf (" should be: DHRYSTONE PROGRAM, 1'ST STRING\n");
+- printf ("Str_2_Loc: %s\n", Str_2_Loc);
+- printf (" should be: DHRYSTONE PROGRAM, 2'ND STRING\n");
+- printf ("\n");
+-
+- User_Time = End_Time - Begin_Time;
+-
+- if (User_Time < Too_Small_Time)
+- {
+- printf ("Measured time too small to obtain meaningful results\n");
+- printf ("Please increase number of runs\n");
+- printf ("\n");
+- }
+- else
+- {
+-#ifdef TIME
+- Microseconds = (float) User_Time * Mic_secs_Per_Second
+- / (float) Number_Of_Runs;
+- Dhrystones_Per_Second = (float) Number_Of_Runs / (float) User_Time;
+-#else
+- Microseconds = (float) User_Time * Mic_secs_Per_Second
+- / ((float) HZ * ((float) Number_Of_Runs));
+- Dhrystones_Per_Second = ((float) HZ * (float) Number_Of_Runs)
+- / (float) User_Time;
+-#endif
+- printf ("Microseconds for one run through Dhrystone: ");
+- printf ("%6.1f \n", Microseconds);
+- printf ("Dhrystones per Second: ");
+- printf ("%6.1f \n", Dhrystones_Per_Second);
+- printf ("\n");
+- }
+-
+-}
+-
+-
+-Proc_1 (Ptr_Val_Par)
+-/******************/
+-
+-REG Rec_Pointer Ptr_Val_Par;
+- /* executed once */
+-{
+- REG Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp;
+- /* == Ptr_Glob_Next */
+- /* Local variable, initialized with Ptr_Val_Par->Ptr_Comp, */
+- /* corresponds to "rename" in Ada, "with" in Pascal */
+-
+- structassign (*Ptr_Val_Par->Ptr_Comp, *Ptr_Glob);
+- Ptr_Val_Par->variant.var_1.Int_Comp = 5;
+- Next_Record->variant.var_1.Int_Comp
+- = Ptr_Val_Par->variant.var_1.Int_Comp;
+- Next_Record->Ptr_Comp = Ptr_Val_Par->Ptr_Comp;
+- Proc_3 (&Next_Record->Ptr_Comp);
+- /* Ptr_Val_Par->Ptr_Comp->Ptr_Comp
+- == Ptr_Glob->Ptr_Comp */
+- if (Next_Record->Discr == Ident_1)
+- /* then, executed */
+- {
+- Next_Record->variant.var_1.Int_Comp = 6;
+- Proc_6 (Ptr_Val_Par->variant.var_1.Enum_Comp,
+- &Next_Record->variant.var_1.Enum_Comp);
+- Next_Record->Ptr_Comp = Ptr_Glob->Ptr_Comp;
+- Proc_7 (Next_Record->variant.var_1.Int_Comp, 10,
+- &Next_Record->variant.var_1.Int_Comp);
+- }
+- else /* not executed */
+- structassign (*Ptr_Val_Par, *Ptr_Val_Par->Ptr_Comp);
+-} /* Proc_1 */
+-
+-
+-Proc_2 (Int_Par_Ref)
+-/******************/
+- /* executed once */
+- /* *Int_Par_Ref == 1, becomes 4 */
+-
+-One_Fifty *Int_Par_Ref;
+-{
+- One_Fifty Int_Loc;
+- Enumeration Enum_Loc;
+-
+- Int_Loc = *Int_Par_Ref + 10;
+- do /* executed once */
+- if (Ch_1_Glob == 'A')
+- /* then, executed */
+- {
+- Int_Loc -= 1;
+- *Int_Par_Ref = Int_Loc - Int_Glob;
+- Enum_Loc = Ident_1;
+- } /* if */
+- while (Enum_Loc != Ident_1); /* true */
+-} /* Proc_2 */
+-
+-
+-Proc_3 (Ptr_Ref_Par)
+-/******************/
+- /* executed once */
+- /* Ptr_Ref_Par becomes Ptr_Glob */
+-
+-Rec_Pointer *Ptr_Ref_Par;
+-
+-{
+- if (Ptr_Glob != Null)
+- /* then, executed */
+- *Ptr_Ref_Par = Ptr_Glob->Ptr_Comp;
+- Proc_7 (10, Int_Glob, &Ptr_Glob->variant.var_1.Int_Comp);
+-} /* Proc_3 */
+-
+-
+-Proc_4 () /* without parameters */
+-/*******/
+- /* executed once */
+-{
+- Boolean Bool_Loc;
+-
+- Bool_Loc = Ch_1_Glob == 'A';
+- Bool_Glob = Bool_Loc | Bool_Glob;
+- Ch_2_Glob = 'B';
+-} /* Proc_4 */
+-
+-
+-Proc_5 () /* without parameters */
+-/*******/
+- /* executed once */
+-{
+- Ch_1_Glob = 'A';
+- Bool_Glob = false;
+-} /* Proc_5 */
+-
+-
+- /* Procedure for the assignment of structures, */
+- /* if the C compiler doesn't support this feature */
+-#ifdef NOSTRUCTASSIGN
+-memcpy (d, s, l)
+-register char *d;
+-register char *s;
+-register int l;
+-{
+- while (l--) *d++ = *s++;
+-}
+-#endif
+-
+-
+//GO.SYSIN DD dhry_1.c
+echo dhry_2.c 1>&2
+sed >dhry_2.c <<'//GO.SYSIN DD dhry_2.c' 's/^-//'
+-/*
+- ****************************************************************************
+- *
+- * "DHRYSTONE" Benchmark Program
+- * -----------------------------
+- *
+- * Version: C, Version 2.1
+- *
+- * File: dhry_2.c (part 3 of 3)
+- *
+- * Date: May 25, 1988
+- *
+- * Author: Reinhold P. Weicker
+- *
+- ****************************************************************************
+- */
+-
+-#include "dhry.h"
+-
+-#ifndef REG
+-#define REG
+- /* REG becomes defined as empty */
+- /* i.e. no register variables */
+-#endif
+-
+-extern int Int_Glob;
+-extern char Ch_1_Glob;
+-
+-
+-Proc_6 (Enum_Val_Par, Enum_Ref_Par)
+-/*********************************/
+- /* executed once */
+- /* Enum_Val_Par == Ident_3, Enum_Ref_Par becomes Ident_2 */
+-
+-Enumeration Enum_Val_Par;
+-Enumeration *Enum_Ref_Par;
+-{
+- *Enum_Ref_Par = Enum_Val_Par;
+- if (! Func_3 (Enum_Val_Par))
+- /* then, not executed */
+- *Enum_Ref_Par = Ident_4;
+- switch (Enum_Val_Par)
+- {
+- case Ident_1:
+- *Enum_Ref_Par = Ident_1;
+- break;
+- case Ident_2:
+- if (Int_Glob > 100)
+- /* then */
+- *Enum_Ref_Par = Ident_1;
+- else *Enum_Ref_Par = Ident_4;
+- break;
+- case Ident_3: /* executed */
+- *Enum_Ref_Par = Ident_2;
+- break;
+- case Ident_4: break;
+- case Ident_5:
+- *Enum_Ref_Par = Ident_3;
+- break;
+- } /* switch */
+-} /* Proc_6 */
+-
+-
+-Proc_7 (Int_1_Par_Val, Int_2_Par_Val, Int_Par_Ref)
+-/**********************************************/
+- /* executed three times */
+- /* first call: Int_1_Par_Val == 2, Int_2_Par_Val == 3, */
+- /* Int_Par_Ref becomes 7 */
+- /* second call: Int_1_Par_Val == 10, Int_2_Par_Val == 5, */
+- /* Int_Par_Ref becomes 17 */
+- /* third call: Int_1_Par_Val == 6, Int_2_Par_Val == 10, */
+- /* Int_Par_Ref becomes 18 */
+-One_Fifty Int_1_Par_Val;
+-One_Fifty Int_2_Par_Val;
+-One_Fifty *Int_Par_Ref;
+-{
+- One_Fifty Int_Loc;
+-
+- Int_Loc = Int_1_Par_Val + 2;
+- *Int_Par_Ref = Int_2_Par_Val + Int_Loc;
+-} /* Proc_7 */
+-
+-
+-Proc_8 (Arr_1_Par_Ref, Arr_2_Par_Ref, Int_1_Par_Val, Int_2_Par_Val)
+-/*********************************************************************/
+- /* executed once */
+- /* Int_Par_Val_1 == 3 */
+- /* Int_Par_Val_2 == 7 */
+-Arr_1_Dim Arr_1_Par_Ref;
+-Arr_2_Dim Arr_2_Par_Ref;
+-int Int_1_Par_Val;
+-int Int_2_Par_Val;
+-{
+- REG One_Fifty Int_Index;
+- REG One_Fifty Int_Loc;
+-
+- Int_Loc = Int_1_Par_Val + 5;
+- Arr_1_Par_Ref [Int_Loc] = Int_2_Par_Val;
+- Arr_1_Par_Ref [Int_Loc+1] = Arr_1_Par_Ref [Int_Loc];
+- Arr_1_Par_Ref [Int_Loc+30] = Int_Loc;
+- for (Int_Index = Int_Loc; Int_Index <= Int_Loc+1; ++Int_Index)
+- Arr_2_Par_Ref [Int_Loc] [Int_Index] = Int_Loc;
+- Arr_2_Par_Ref [Int_Loc] [Int_Loc-1] += 1;
+- Arr_2_Par_Ref [Int_Loc+20] [Int_Loc] = Arr_1_Par_Ref [Int_Loc];
+- Int_Glob = 5;
+-} /* Proc_8 */
+-
+-
+-Enumeration Func_1 (Ch_1_Par_Val, Ch_2_Par_Val)
+-/*************************************************/
+- /* executed three times */
+- /* first call: Ch_1_Par_Val == 'H', Ch_2_Par_Val == 'R' */
+- /* second call: Ch_1_Par_Val == 'A', Ch_2_Par_Val == 'C' */
+- /* third call: Ch_1_Par_Val == 'B', Ch_2_Par_Val == 'C' */
+-
+-Capital_Letter Ch_1_Par_Val;
+-Capital_Letter Ch_2_Par_Val;
+-{
+- Capital_Letter Ch_1_Loc;
+- Capital_Letter Ch_2_Loc;
+-
+- Ch_1_Loc = Ch_1_Par_Val;
+- Ch_2_Loc = Ch_1_Loc;
+- if (Ch_2_Loc != Ch_2_Par_Val)
+- /* then, executed */
+- return (Ident_1);
+- else /* not executed */
+- {
+- Ch_1_Glob = Ch_1_Loc;
+- return (Ident_2);
+- }
+-} /* Func_1 */
+-
+-
+-Boolean Func_2 (Str_1_Par_Ref, Str_2_Par_Ref)
+-/*************************************************/
+- /* executed once */
+- /* Str_1_Par_Ref == "DHRYSTONE PROGRAM, 1'ST STRING" */
+- /* Str_2_Par_Ref == "DHRYSTONE PROGRAM, 2'ND STRING" */
+-
+-Str_30 Str_1_Par_Ref;
+-Str_30 Str_2_Par_Ref;
+-{
+- REG One_Thirty Int_Loc;
+- Capital_Letter Ch_Loc;
+-
+- Int_Loc = 2;
+- while (Int_Loc <= 2) /* loop body executed once */
+- if (Func_1 (Str_1_Par_Ref[Int_Loc],
+- Str_2_Par_Ref[Int_Loc+1]) == Ident_1)
+- /* then, executed */
+- {
+- Ch_Loc = 'A';
+- Int_Loc += 1;
+- } /* if, while */
+- if (Ch_Loc >= 'W' && Ch_Loc < 'Z')
+- /* then, not executed */
+- Int_Loc = 7;
+- if (Ch_Loc == 'R')
+- /* then, not executed */
+- return (true);
+- else /* executed */
+- {
+- if (strcmp (Str_1_Par_Ref, Str_2_Par_Ref) > 0)
+- /* then, not executed */
+- {
+- Int_Loc += 7;
+- Int_Glob = Int_Loc;
+- return (true);
+- }
+- else /* executed */
+- return (false);
+- } /* if Ch_Loc */
+-} /* Func_2 */
+-
+-
+-Boolean Func_3 (Enum_Par_Val)
+-/***************************/
+- /* executed once */
+- /* Enum_Par_Val == Ident_3 */
+-Enumeration Enum_Par_Val;
+-{
+- Enumeration Enum_Loc;
+-
+- Enum_Loc = Enum_Par_Val;
+- if (Enum_Loc == Ident_3)
+- /* then, executed */
+- return (true);
+- else /* not executed */
+- return (false);
+-} /* Func_3 */
+-
+//GO.SYSIN DD dhry_2.c
+echo dhry_c.dif 1>&2
+sed >dhry_c.dif <<'//GO.SYSIN DD dhry_c.dif' 's/^-//'
+-7c7
+-< * Version: C, Version 2.1
+----
+-> * Version: C, Version 2.0
+-9c9
+-< * File: dhry.h (part 1 of 3)
+----
+-> * File: dhry_global.h (part 1 of 3)
+-11c11
+-< * Date: May 25, 1988
+----
+-> * Date: March 3, 1988
+-30c30
+-< * In addition, Berkeley UNIX system calls "times ()" or "time ()"
+----
+-> * In addition, UNIX system calls "times ()" or "time ()"
+-44c44
+-< * Please send results to Rick Richardson and/or Reinhold Weicker.
+----
+-> * Please send results to Reinhold Weicker and/or Rick Richardson.
+-59c59
+-< * History: This version C/2.1 has been made for two reasons:
+----
+-> * History: This version C/2.0 has been made for two reasons:
+-123,129d122
+-< * Version 2.1 is identical to version 2.0 distributed via
+-< * the UNIX network Usenet in March 1988 except that it corrects
+-< * some minor deficiencies that were found by users of version 2.0.
+-< * The only change within the measurement loop is that a
+-< * non-executed "else" part was added to the "if" statement in
+-< * Func_3, and a non-executed "else" part removed from Proc_3.
+-< *
+-165,167c158,160
+-< * -DHZ=nnn
+-< * In Berkeley UNIX, the function "times" returns process
+-< * time in 1/HZ seconds, with HZ = 60 for most systems.
+----
+-> * -DHZ=nnn (default: 60)
+-> * The function "times" returns process times in
+-> * 1/HZ seconds, with HZ = 60 for most systems.
+-169c162
+-< * A VALUE.
+----
+-> * THE DEFAULT VALUE.
+-176,178c169,171
+-< * - dhry.h (this file, containing global definitions and comments)
+-< * - dhry_1.c (containing the code corresponding to Ada package Pack_1)
+-< * - dhry_2.c (containing the code corresponding to Ada package Pack_2)
+----
+-> * - dhry_global.h (this file, containing global definitions and comments)
+-> * - dhry_pack_1.c (containing the code corresponding to Ada package Pack_1)
+-> * - dhry_pack_2.c (containing the code corresponding to Ada package Pack_2)
+-350a344
+-> #ifndef TIMES
+-353,354c347,354
+-< /* Use times(2) time function unless */
+-< /* explicitly defined otherwise */
+----
+-> #endif
+-> /* Use "times" function for measurement */
+-> /* unless explicitly defined otherwise */
+-> #ifndef HZ
+-> #define HZ 60
+-> #endif
+-> /* Use HZ = 60 for "times" function */
+-> /* unless explicitly defined otherwise */
+-363c363
+-< /* Berkeley UNIX C returns process times in seconds/HZ */
+----
+-> /* UNIX C returns process times in seconds/HZ */
+-7c7
+-< * Version: C, Version 2.1
+----
+-> * Version: C, Version 2.0
+-9c9
+-< * File: dhry_1.c (part 2 of 3)
+----
+-> * File: dhry_pack_1.c (part 2 of 3)
+-11c11
+-< * Date: May 25, 1988
+----
+-> * Date: March 3, 1988
+-18c18
+-< #include "dhry.h"
+----
+-> #include "dhry_global.h"
+-50,51d49
+-< #define Too_Small_Time 120
+-< /* Measurements should last at least about 2 seconds */
+-55a54,55
+-> #endif
+->
+-58d57
+-< #endif
+-73a73
+->
+-84a85
+->
+-99,100c100,102
+-< /* Was missing in published program. Without this statement, */
+-< /* Arr_2_Glob [8][7] would have an undefined value. */
+----
+-> /* Was missing in published program. Without this */
+-> /* initialization, Arr_2_Glob [8][7] would have an */
+-> /* undefined value. */
+-105c107
+-< printf ("Dhrystone Benchmark, Version 2.1 (Language: C)\n");
+----
+-> printf ("Dhrystone Benchmark, Version 2.0 (Language: C)\n");
+-281c283
+-< /******************/
+----
+-> /**********************/
+-338c340
+-< /******************/
+----
+-> /**********************/
+-347a350,351
+-> else /* not executed */
+-> Int_Glob = 100;
+-349a354
+->
+-7c7
+-< * Version: C, Version 2.1
+----
+-> * Version: C, Version 2.0
+-9c9
+-< * File: dhry_2.c (part 3 of 3)
+----
+-> * File: dhry_pack_2.c (part 3 of 3)
+-11c11
+-< * Date: May 25, 1988
+----
+-> * Date: March 3, 1988
+-18c18
+-< #include "dhry.h"
+----
+-> #include "dhry_global.h"
+-189,190d188
+-< else /* not executed */
+-< return (false);
+//GO.SYSIN DD dhry_c.dif
+echo submit.frm 1>&2
+sed >submit.frm <<'//GO.SYSIN DD submit.frm' 's/^-//'
+-DHRYSTONE 2.1 BENCHMARK REPORTING FORM
+-MANUF:
+-MODEL:
+-PROC:
+-CLOCK:
+-OS:
+-OVERSION:
+-COMPILER:
+-CVERSION:
+-OPTIONS:
+-NOREG:
+-REG:
+-NOTES:
+-DATE:
+-SUBMITTER:
+-CODESIZE:
+-MAILTO: uunet!pcrat!dry2
+//GO.SYSIN DD submit.frm
diff --git a/zpu/roadshow/roadshow/dhrystone/dhry.h b/zpu/roadshow/roadshow/dhrystone/dhry.h
new file mode 100644
index 0000000..211c2e2
--- /dev/null
+++ b/zpu/roadshow/roadshow/dhrystone/dhry.h
@@ -0,0 +1,423 @@
+/*
+ ****************************************************************************
+ *
+ * "DHRYSTONE" Benchmark Program
+ * -----------------------------
+ *
+ * Version: C, Version 2.1
+ *
+ * File: dhry.h (part 1 of 3)
+ *
+ * Date: May 25, 1988
+ *
+ * Author: Reinhold P. Weicker
+ * Siemens AG, AUT E 51
+ * Postfach 3220
+ * 8520 Erlangen
+ * Germany (West)
+ * Phone: [+49]-9131-7-20330
+ * (8-17 Central European Time)
+ * Usenet: ..!mcsun!unido!estevax!weicker
+ *
+ * Original Version (in Ada) published in
+ * "Communications of the ACM" vol. 27., no. 10 (Oct. 1984),
+ * pp. 1013 - 1030, together with the statistics
+ * on which the distribution of statements etc. is based.
+ *
+ * In this C version, the following C library functions are used:
+ * - strcpy, strcmp (inside the measurement loop)
+ * - printf, scanf (outside the measurement loop)
+ * In addition, Berkeley UNIX system calls "times ()" or "time ()"
+ * are used for execution time measurement. For measurements
+ * on other systems, these calls have to be changed.
+ *
+ * Collection of Results:
+ * Reinhold Weicker (address see above) and
+ *
+ * Rick Richardson
+ * PC Research. Inc.
+ * 94 Apple Orchard Drive
+ * Tinton Falls, NJ 07724
+ * Phone: (201) 389-8963 (9-17 EST)
+ * Usenet: ...!uunet!pcrat!rick
+ *
+ * Please send results to Rick Richardson and/or Reinhold Weicker.
+ * Complete information should be given on hardware and software used.
+ * Hardware information includes: Machine type, CPU, type and size
+ * of caches; for microprocessors: clock frequency, memory speed
+ * (number of wait states).
+ * Software information includes: Compiler (and runtime library)
+ * manufacturer and version, compilation switches, OS version.
+ * The Operating System version may give an indication about the
+ * compiler; Dhrystone itself performs no OS calls in the measurement loop.
+ *
+ * The complete output generated by the program should be mailed
+ * such that at least some checks for correctness can be made.
+ *
+ ***************************************************************************
+ *
+ * History: This version C/2.1 has been made for two reasons:
+ *
+ * 1) There is an obvious need for a common C version of
+ * Dhrystone, since C is at present the most popular system
+ * programming language for the class of processors
+ * (microcomputers, minicomputers) where Dhrystone is used most.
+ * There should be, as far as possible, only one C version of
+ * Dhrystone such that results can be compared without
+ * restrictions. In the past, the C versions distributed
+ * by Rick Richardson (Version 1.1) and by Reinhold Weicker
+ * had small (though not significant) differences.
+ *
+ * 2) As far as it is possible without changes to the Dhrystone
+ * statistics, optimizing compilers should be prevented from
+ * removing significant statements.
+ *
+ * This C version has been developed in cooperation with
+ * Rick Richardson (Tinton Falls, NJ), it incorporates many
+ * ideas from the "Version 1.1" distributed previously by
+ * him over the UNIX network Usenet.
+ * I also thank Chaim Benedelac (National Semiconductor),
+ * David Ditzel (SUN), Earl Killian and John Mashey (MIPS),
+ * Alan Smith and Rafael Saavedra-Barrera (UC at Berkeley)
+ * for their help with comments on earlier versions of the
+ * benchmark.
+ *
+ * Changes: In the initialization part, this version follows mostly
+ * Rick Richardson's version distributed via Usenet, not the
+ * version distributed earlier via floppy disk by Reinhold Weicker.
+ * As a concession to older compilers, names have been made
+ * unique within the first 8 characters.
+ * Inside the measurement loop, this version follows the
+ * version previously distributed by Reinhold Weicker.
+ *
+ * At several places in the benchmark, code has been added,
+ * but within the measurement loop only in branches that
+ * are not executed. The intention is that optimizing compilers
+ * should be prevented from moving code out of the measurement
+ * loop, or from removing code altogether. Since the statements
+ * that are executed within the measurement loop have NOT been
+ * changed, the numbers defining the "Dhrystone distribution"
+ * (distribution of statements, operand types and locality)
+ * still hold. Except for sophisticated optimizing compilers,
+ * execution times for this version should be the same as
+ * for previous versions.
+ *
+ * Since it has proven difficult to subtract the time for the
+ * measurement loop overhead in a correct way, the loop check
+ * has been made a part of the benchmark. This does have
+ * an impact - though a very minor one - on the distribution
+ * statistics which have been updated for this version.
+ *
+ * All changes within the measurement loop are described
+ * and discussed in the companion paper "Rationale for
+ * Dhrystone version 2".
+ *
+ * Because of the self-imposed limitation that the order and
+ * distribution of the executed statements should not be
+ * changed, there are still cases where optimizing compilers
+ * may not generate code for some statements. To a certain
+ * degree, this is unavoidable for small synthetic benchmarks.
+ * Users of the benchmark are advised to check code listings
+ * whether code is generated for all statements of Dhrystone.
+ *
+ * Version 2.1 is identical to version 2.0 distributed via
+ * the UNIX network Usenet in March 1988 except that it corrects
+ * some minor deficiencies that were found by users of version 2.0.
+ * The only change within the measurement loop is that a
+ * non-executed "else" part was added to the "if" statement in
+ * Func_3, and a non-executed "else" part removed from Proc_3.
+ *
+ ***************************************************************************
+ *
+ * Defines: The following "Defines" are possible:
+ * -DREG=register (default: Not defined)
+ * As an approximation to what an average C programmer
+ * might do, the "register" storage class is applied
+ * (if enabled by -DREG=register)
+ * - for local variables, if they are used (dynamically)
+ * five or more times
+ * - for parameters if they are used (dynamically)
+ * six or more times
+ * Note that an optimal "register" strategy is
+ * compiler-dependent, and that "register" declarations
+ * do not necessarily lead to faster execution.
+ * -DNOSTRUCTASSIGN (default: Not defined)
+ * Define if the C compiler does not support
+ * assignment of structures.
+ * -DNOENUMS (default: Not defined)
+ * Define if the C compiler does not support
+ * enumeration types.
+ * -DTIMES (default)
+ * -DTIME
+ * The "times" function of UNIX (returning process times)
+ * or the "time" function (returning wallclock time)
+ * is used for measurement.
+ * For single user machines, "time ()" is adequate. For
+ * multi-user machines where you cannot get single-user
+ * access, use the "times ()" function. If you have
+ * neither, use a stopwatch in the dead of night.
+ * "printf"s are provided marking the points "Start Timer"
+ * and "Stop Timer". DO NOT use the UNIX "time(1)"
+ * command, as this will measure the total time to
+ * run this program, which will (erroneously) include
+ * the time to allocate storage (malloc) and to perform
+ * the initialization.
+ * -DHZ=nnn
+ * In Berkeley UNIX, the function "times" returns process
+ * time in 1/HZ seconds, with HZ = 60 for most systems.
+ * CHECK YOUR SYSTEM DESCRIPTION BEFORE YOU JUST APPLY
+ * A VALUE.
+ *
+ ***************************************************************************
+ *
+ * Compilation model and measurement (IMPORTANT):
+ *
+ * This C version of Dhrystone consists of three files:
+ * - dhry.h (this file, containing global definitions and comments)
+ * - dhry_1.c (containing the code corresponding to Ada package Pack_1)
+ * - dhry_2.c (containing the code corresponding to Ada package Pack_2)
+ *
+ * The following "ground rules" apply for measurements:
+ * - Separate compilation
+ * - No procedure merging
+ * - Otherwise, compiler optimizations are allowed but should be indicated
+ * - Default results are those without register declarations
+ * See the companion paper "Rationale for Dhrystone Version 2" for a more
+ * detailed discussion of these ground rules.
+ *
+ * For 16-Bit processors (e.g. 80186, 80286), times for all compilation
+ * models ("small", "medium", "large" etc.) should be given if possible,
+ * together with a definition of these models for the compiler system used.
+ *
+ **************************************************************************
+ *
+ * Dhrystone (C version) statistics:
+ *
+ * [Comment from the first distribution, updated for version 2.
+ * Note that because of language differences, the numbers are slightly
+ * different from the Ada version.]
+ *
+ * The following program contains statements of a high level programming
+ * language (here: C) in a distribution considered representative:
+ *
+ * assignments 52 (51.0 %)
+ * control statements 33 (32.4 %)
+ * procedure, function calls 17 (16.7 %)
+ *
+ * 103 statements are dynamically executed. The program is balanced with
+ * respect to the three aspects:
+ *
+ * - statement type
+ * - operand type
+ * - operand locality
+ * operand global, local, parameter, or constant.
+ *
+ * The combination of these three aspects is balanced only approximately.
+ *
+ * 1. Statement Type:
+ * ----------------- number
+ *
+ * V1 = V2 9
+ * (incl. V1 = F(..)
+ * V = Constant 12
+ * Assignment, 7
+ * with array element
+ * Assignment, 6
+ * with record component
+ * --
+ * 34 34
+ *
+ * X = Y +|-|"&&"|"|" Z 5
+ * X = Y +|-|"==" Constant 6
+ * X = X +|- 1 3
+ * X = Y *|/ Z 2
+ * X = Expression, 1
+ * two operators
+ * X = Expression, 1
+ * three operators
+ * --
+ * 18 18
+ *
+ * if .... 14
+ * with "else" 7
+ * without "else" 7
+ * executed 3
+ * not executed 4
+ * for ... 7 | counted every time
+ * while ... 4 | the loop condition
+ * do ... while 1 | is evaluated
+ * switch ... 1
+ * break 1
+ * declaration with 1
+ * initialization
+ * --
+ * 34 34
+ *
+ * P (...) procedure call 11
+ * user procedure 10
+ * library procedure 1
+ * X = F (...)
+ * function call 6
+ * user function 5
+ * library function 1
+ * --
+ * 17 17
+ * ---
+ * 103
+ *
+ * The average number of parameters in procedure or function calls
+ * is 1.82 (not counting the function values as implicit parameters).
+ *
+ *
+ * 2. Operators
+ * ------------
+ * number approximate
+ * percentage
+ *
+ * Arithmetic 32 50.8
+ *
+ * + 21 33.3
+ * - 7 11.1
+ * * 3 4.8
+ * / (int div) 1 1.6
+ *
+ * Comparison 27 42.8
+ *
+ * == 9 14.3
+ * /= 4 6.3
+ * > 1 1.6
+ * < 3 4.8
+ * >= 1 1.6
+ * <= 9 14.3
+ *
+ * Logic 4 6.3
+ *
+ * && (AND-THEN) 1 1.6
+ * | (OR) 1 1.6
+ * ! (NOT) 2 3.2
+ *
+ * -- -----
+ * 63 100.1
+ *
+ *
+ * 3. Operand Type (counted once per operand reference):
+ * ---------------
+ * number approximate
+ * percentage
+ *
+ * Integer 175 72.3 %
+ * Character 45 18.6 %
+ * Pointer 12 5.0 %
+ * String30 6 2.5 %
+ * Array 2 0.8 %
+ * Record 2 0.8 %
+ * --- -------
+ * 242 100.0 %
+ *
+ * When there is an access path leading to the final operand (e.g. a record
+ * component), only the final data type on the access path is counted.
+ *
+ *
+ * 4. Operand Locality:
+ * -------------------
+ * number approximate
+ * percentage
+ *
+ * local variable 114 47.1 %
+ * global variable 22 9.1 %
+ * parameter 45 18.6 %
+ * value 23 9.5 %
+ * reference 22 9.1 %
+ * function result 6 2.5 %
+ * constant 55 22.7 %
+ * --- -------
+ * 242 100.0 %
+ *
+ *
+ * The program does not compute anything meaningful, but it is syntactically
+ * and semantically correct. All variables have a value assigned to them
+ * before they are used as a source operand.
+ *
+ * There has been no explicit effort to account for the effects of a
+ * cache, or to balance the use of long or short displacements for code or
+ * data.
+ *
+ ***************************************************************************
+ */
+
+/* Compiler and system dependent definitions: */
+
+#ifndef TIME
+#define TIMES
+#endif
+ /* Use times(2) time function unless */
+ /* explicitly defined otherwise */
+
+#ifdef TIMES
+#include <sys/types.h>
+#include <sys/times.h>
+ /* for "times" */
+#endif
+
+#define Mic_secs_Per_Second 1000000
+ /* Berkeley UNIX C returns process times in seconds/HZ */
+
+#ifdef NOSTRUCTASSIGN
+#define structassign(d, s) memcpy(&(d), &(s), sizeof(d))
+#else
+#define structassign(d, s) d = s
+#endif
+
+#ifdef NOENUM
+#define Ident_1 0
+#define Ident_2 1
+#define Ident_3 2
+#define Ident_4 3
+#define Ident_5 4
+ typedef int Enumeration;
+#else
+ typedef enum {Ident_1, Ident_2, Ident_3, Ident_4, Ident_5}
+ Enumeration;
+#endif
+ /* for boolean and enumeration types in Ada, Pascal */
+
+/* General definitions: */
+
+#include <stdio.h>
+ /* for strcpy, strcmp */
+
+#define Null 0
+ /* Value of a Null pointer */
+#define true 1
+#define false 0
+
+typedef int One_Thirty;
+typedef int One_Fifty;
+typedef char Capital_Letter;
+typedef int Boolean;
+typedef char Str_30 [31];
+typedef int Arr_1_Dim [50];
+typedef int Arr_2_Dim [50] [50];
+
+typedef struct record
+ {
+ struct record *Ptr_Comp;
+ Enumeration Discr;
+ union {
+ struct {
+ Enumeration Enum_Comp;
+ int Int_Comp;
+ char Str_Comp [31];
+ } var_1;
+ struct {
+ Enumeration E_Comp_2;
+ char Str_2_Comp [31];
+ } var_2;
+ struct {
+ char Ch_1_Comp;
+ char Ch_2_Comp;
+ } var_3;
+ } variant;
+ } Rec_Type, *Rec_Pointer;
+
+
diff --git a/zpu/roadshow/roadshow/dhrystone/dhry_1.c b/zpu/roadshow/roadshow/dhrystone/dhry_1.c
new file mode 100644
index 0000000..08a29b9
--- /dev/null
+++ b/zpu/roadshow/roadshow/dhrystone/dhry_1.c
@@ -0,0 +1,533 @@
+/*
+ ****************************************************************************
+ *
+ * "DHRYSTONE" Benchmark Program
+ * -----------------------------
+ *
+ * Version: C, Version 2.1
+ *
+ * File: dhry_1.c (part 2 of 3)
+ *
+ * Date: May 25, 1988
+ *
+ * Author: Reinhold P. Weicker
+ *
+ ****************************************************************************
+ */
+
+#include "dhry.h"
+#include <stdarg.h>
+
+static int
+_cvt(int val, char *buf, int radix, char *digits)
+{
+ char temp[80];
+ char *cp = temp;
+ int length = 0;
+
+ if (val == 0) {
+ /* Special case */
+ *cp++ = '0';
+ } else {
+ while (val) {
+ *cp++ = digits[val % radix];
+ val /= radix;
+ }
+ }
+ while (cp != temp) {
+ *buf++ = *--cp;
+ length++;
+ }
+ *buf = '\0';
+ return (length);
+}
+
+#define is_digit(c) ((c >= '0') && (c <= '9'))
+
+
+#ifndef TINY
+static int
+_vprintf(void (*putc)(char c, void **param), void **param, const char *fmt, va_list ap)
+{
+ char buf[sizeof(long long)*8];
+ char c, sign, *cp=buf;
+ int left_prec, right_prec, zero_fill, pad, pad_on_right,
+ i, islong, islonglong;
+ long long val = 0;
+ int res = 0, length = 0;
+
+ while ((c = *fmt++) != '\0') {
+ if (c == '%') {
+ c = *fmt++;
+ left_prec = right_prec = pad_on_right = islong = islonglong = 0;
+ sign = '\0';
+ // Fetch value [numeric descriptors only]
+ switch (c) {
+ case 'd':
+ val = (long long)va_arg(ap, int);
+ if ((c == 'd') || (c == 'D')) {
+ if (val < 0) {
+ sign = '-';
+ val = -val;
+ }
+ } else {
+ // Mask to unsigned, sized quantity
+ if (islong) {
+ val &= ((long long)1 << (sizeof(long) * 8)) - 1;
+ } else{
+ val &= ((long long)1 << (sizeof(int) * 8)) - 1;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ // Process output
+ switch (c) {
+ case 'd':
+ switch (c) {
+ case 'd':
+ length = _cvt(val, buf, 10, "0123456789");
+ break;
+ }
+ cp = buf;
+ break;
+ case 's':
+ cp = va_arg(ap, char *);
+ length = 0;
+ while (cp[length] != '\0') length++;
+ break;
+ case 'c':
+ c = va_arg(ap, int /*char*/);
+ (*putc)(c, param);
+ res++;
+ continue;
+ default:
+ (*putc)('%', param);
+ (*putc)(c, param);
+ res += 2;
+ continue;
+ }
+ while (length-- > 0) {
+ c = *cp++;
+ (*putc)(c, param);
+ res++;
+ }
+ } else {
+ (*putc)(c, param);
+ res++;
+ }
+ }
+ return (res);
+}
+#endif
+
+// Default wrapper function used by diag_printf
+static void
+_diag_write_char(char c, void **param)
+{
+ if (c=='\n')
+ {
+ outbyte('\r');
+ }
+ outbyte(c);
+}
+
+int
+small_printf(const char *fmt, ...)
+{
+#ifndef TINY
+ va_list ap;
+ int ret;
+
+ va_start(ap, fmt);
+ ret = _vprintf(_diag_write_char, (void **)0, fmt, ap);
+ va_end(ap);
+ return (ret);
+#else
+ return 0;
+#endif
+}
+
+
+
+
+/* Global Variables: */
+
+Rec_Pointer Ptr_Glob,
+ Next_Ptr_Glob;
+int Int_Glob;
+Boolean Bool_Glob;
+char Ch_1_Glob,
+ Ch_2_Glob;
+int Arr_1_Glob [50];
+int Arr_2_Glob [50] [50];
+
+Enumeration Func_1 ();
+ /* forward declaration necessary since Enumeration may not simply be int */
+
+#ifndef REG
+ Boolean Reg = false;
+#define REG
+ /* REG becomes defined as empty */
+ /* i.e. no register variables */
+#else
+ Boolean Reg = true;
+#endif
+
+/* variables for time measurement: */
+
+#ifdef TIMES
+struct tms time_info;
+ /* see library function "times" */
+#define Too_Small_Time 120
+ /* Measurements should last at least about 2 seconds */
+#endif
+#ifdef TIME
+extern long time();
+ /* see library function "time" */
+#define Too_Small_Time 2
+ /* Measurements should last at least 2 seconds */
+#endif
+
+long long Begin_Time,
+ End_Time,
+ User_Time;
+long long Microseconds,
+ Dhrystones_Per_Second,
+ Vax_Mips;
+
+/* end of variables for time measurement */
+
+int Number_Of_Runs = 50000;
+
+extern long long _readMicroseconds();
+
+
+int main ()
+/*****/
+
+ /* main program, corresponds to procedures */
+ /* Main and Proc_0 in the Ada version */
+{
+ One_Fifty Int_1_Loc;
+ REG One_Fifty Int_2_Loc;
+ One_Fifty Int_3_Loc;
+ REG char Ch_Index;
+ Enumeration Enum_Loc;
+ Str_30 Str_1_Loc;
+ Str_30 Str_2_Loc;
+ REG int Run_Index;
+
+ /* Initializations */
+
+ Next_Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type));
+ Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type));
+
+ Ptr_Glob->Ptr_Comp = Next_Ptr_Glob;
+ Ptr_Glob->Discr = Ident_1;
+ Ptr_Glob->variant.var_1.Enum_Comp = Ident_3;
+ Ptr_Glob->variant.var_1.Int_Comp = 40;
+ strcpy (Ptr_Glob->variant.var_1.Str_Comp,
+ "DHRYSTONE PROGRAM, SOME STRING");
+ strcpy (Str_1_Loc, "DHRYSTONE PROGRAM, 1'ST STRING");
+
+ Arr_2_Glob [8][7] = 10;
+ /* Was missing in published program. Without this statement, */
+ /* Arr_2_Glob [8][7] would have an undefined value. */
+ /* Warning: With 16-Bit processors and Number_Of_Runs > 32000, */
+ /* overflow may occur for this array element. */
+ small_printf ("\n");
+ small_printf ("Dhrystone Benchmark, Version 2.1 (Language: C)\n");
+ small_printf ("\n");
+ if (Reg)
+ {
+ small_printf ("Program compiled with 'register' attribute\n");
+ small_printf ("\n");
+ }
+ else
+ {
+ small_printf ("Program compiled without 'register' attribute\n");
+ small_printf ("\n");
+ }
+ Number_Of_Runs;
+
+ small_printf ("Execution starts, %d runs through Dhrystone\n", Number_Of_Runs);
+
+ /***************/
+ /* Start timer */
+ /***************/
+
+#if 0
+#ifdef TIMES
+ times (&time_info);
+ Begin_Time = (long) time_info.tms_utime;
+#endif
+#ifdef TIME
+ Begin_Time = time ( (long *) 0);
+#endif
+#else
+ Begin_Time = _readMicroseconds();
+#endif
+ for (Run_Index = 1; Run_Index <= Number_Of_Runs; ++Run_Index)
+ {
+
+ Proc_5();
+ Proc_4();
+ /* Ch_1_Glob == 'A', Ch_2_Glob == 'B', Bool_Glob == true */
+ Int_1_Loc = 2;
+ Int_2_Loc = 3;
+ strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 2'ND STRING");
+ Enum_Loc = Ident_2;
+ Bool_Glob = ! Func_2 (Str_1_Loc, Str_2_Loc);
+ /* Bool_Glob == 1 */
+ while (Int_1_Loc < Int_2_Loc) /* loop body executed once */
+ {
+ Int_3_Loc = 5 * Int_1_Loc - Int_2_Loc;
+ /* Int_3_Loc == 7 */
+ Proc_7 (Int_1_Loc, Int_2_Loc, &Int_3_Loc);
+ /* Int_3_Loc == 7 */
+ Int_1_Loc += 1;
+ } /* while */
+ /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */
+ Proc_8 (Arr_1_Glob, Arr_2_Glob, Int_1_Loc, Int_3_Loc);
+ /* Int_Glob == 5 */
+ Proc_1 (Ptr_Glob);
+ for (Ch_Index = 'A'; Ch_Index <= Ch_2_Glob; ++Ch_Index)
+ /* loop body executed twice */
+ {
+ if (Enum_Loc == Func_1 (Ch_Index, 'C'))
+ /* then, not executed */
+ {
+ Proc_6 (Ident_1, &Enum_Loc);
+ strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 3'RD STRING");
+ Int_2_Loc = Run_Index;
+ Int_Glob = Run_Index;
+ }
+ }
+ /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */
+ Int_2_Loc = Int_2_Loc * Int_1_Loc;
+ Int_1_Loc = Int_2_Loc / Int_3_Loc;
+ Int_2_Loc = 7 * (Int_2_Loc - Int_3_Loc) - Int_1_Loc;
+ /* Int_1_Loc == 1, Int_2_Loc == 13, Int_3_Loc == 7 */
+ Proc_2 (&Int_1_Loc);
+ /* Int_1_Loc == 5 */
+
+ } /* loop "for Run_Index" */
+
+ /**************/
+ /* Stop timer */
+ /**************/
+
+#if 0
+#ifdef TIMES
+ times (&time_info);
+ End_Time = (long) time_info.tms_utime;
+#endif
+#ifdef TIME
+ End_Time = time ( (long *) 0);
+#endif
+#else
+ End_Time = _readMicroseconds();
+#endif
+
+ small_printf ("Execution ends\n");
+ small_printf ("\n");
+ small_printf ("Final values of the variables used in the benchmark:\n");
+ small_printf ("\n");
+ small_printf ("Int_Glob: %d\n", Int_Glob);
+ small_printf (" should be: %d\n", 5);
+ small_printf ("Bool_Glob: %d\n", Bool_Glob);
+ small_printf (" should be: %d\n", 1);
+ small_printf ("Ch_1_Glob: %c\n", Ch_1_Glob);
+ small_printf (" should be: %c\n", 'A');
+ small_printf ("Ch_2_Glob: %c\n", Ch_2_Glob);
+ small_printf (" should be: %c\n", 'B');
+ small_printf ("Arr_1_Glob[8]: %d\n", Arr_1_Glob[8]);
+ small_printf (" should be: %d\n", 7);
+ small_printf ("Arr_2_Glob[8][7]: %d\n", Arr_2_Glob[8][7]);
+ small_printf (" should be: Number_Of_Runs + 10\n");
+ small_printf ("Ptr_Glob->\n");
+ small_printf (" Ptr_Comp: %d\n", (int) Ptr_Glob->Ptr_Comp);
+ small_printf (" should be: (implementation-dependent)\n");
+ small_printf (" Discr: %d\n", Ptr_Glob->Discr);
+ small_printf (" should be: %d\n", 0);
+ small_printf (" Enum_Comp: %d\n", Ptr_Glob->variant.var_1.Enum_Comp);
+ small_printf (" should be: %d\n", 2);
+ small_printf (" Int_Comp: %d\n", Ptr_Glob->variant.var_1.Int_Comp);
+ small_printf (" should be: %d\n", 17);
+ small_printf (" Str_Comp: %s\n", Ptr_Glob->variant.var_1.Str_Comp);
+ small_printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n");
+ small_printf ("Next_Ptr_Glob->\n");
+ small_printf (" Ptr_Comp: %d\n", (int) Next_Ptr_Glob->Ptr_Comp);
+ small_printf (" should be: (implementation-dependent), same as above\n");
+ small_printf (" Discr: %d\n", Next_Ptr_Glob->Discr);
+ small_printf (" should be: %d\n", 0);
+ small_printf (" Enum_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Enum_Comp);
+ small_printf (" should be: %d\n", 1);
+ small_printf (" Int_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Int_Comp);
+ small_printf (" should be: %d\n", 18);
+ small_printf (" Str_Comp: %s\n",
+ Next_Ptr_Glob->variant.var_1.Str_Comp);
+ small_printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n");
+ small_printf ("Int_1_Loc: %d\n", Int_1_Loc);
+ small_printf (" should be: %d\n", 5);
+ small_printf ("Int_2_Loc: %d\n", Int_2_Loc);
+ small_printf (" should be: %d\n", 13);
+ small_printf ("Int_3_Loc: %d\n", Int_3_Loc);
+ small_printf (" should be: %d\n", 7);
+ small_printf ("Enum_Loc: %d\n", Enum_Loc);
+ small_printf (" should be: %d\n", 1);
+ small_printf ("Str_1_Loc: %s\n", Str_1_Loc);
+ small_printf (" should be: DHRYSTONE PROGRAM, 1'ST STRING\n");
+ small_printf ("Str_2_Loc: %s\n", Str_2_Loc);
+ small_printf (" should be: DHRYSTONE PROGRAM, 2'ND STRING\n");
+ small_printf ("\n");
+
+ User_Time = End_Time - Begin_Time;
+ small_printf ("User time: %d\n", (int)User_Time);
+
+ if (User_Time < Too_Small_Time)
+ {
+ small_printf ("Measured time too small to obtain meaningful results\n");
+ small_printf ("Please increase number of runs\n");
+ small_printf ("\n");
+ }
+/* else */
+ {
+#if 0
+#ifdef TIME
+ Microseconds = (User_Time * Mic_secs_Per_Second )
+ / Number_Of_Runs;
+ Dhrystones_Per_Second = Number_Of_Runs / User_Time;
+ Vax_Mips = (Number_Of_Runs*1000) / (1757*User_Time);
+#else
+ Microseconds = (float) User_Time * Mic_secs_Per_Second
+ / ((float) HZ * ((float) Number_Of_Runs));
+ Dhrystones_Per_Second = ((float) HZ * (float) Number_Of_Runs)
+ / (float) User_Time;
+ Vax_Mips = Dhrystones_Per_Second / 1757.0;
+#endif
+#else
+ Microseconds = User_Time / Number_Of_Runs;
+ Dhrystones_Per_Second = ((long long)Number_Of_Runs*1000000) / User_Time;
+ Vax_Mips = (((long long)Number_Of_Runs)*1000000000) / (1757*User_Time);
+#endif
+ small_printf ("Microseconds for one run through Dhrystone: ");
+ small_printf ("%d \n", (int)Microseconds);
+ small_printf ("Dhrystones per Second: ");
+ small_printf ("%d \n", (int)Dhrystones_Per_Second);
+ small_printf ("VAX MIPS rating * 1000 = %d \n",(int)Vax_Mips);
+ small_printf ("\n");
+ }
+
+ return 0;
+}
+
+
+Proc_1 (Ptr_Val_Par)
+/******************/
+
+REG Rec_Pointer Ptr_Val_Par;
+ /* executed once */
+{
+ REG Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp;
+ /* == Ptr_Glob_Next */
+ /* Local variable, initialized with Ptr_Val_Par->Ptr_Comp, */
+ /* corresponds to "rename" in Ada, "with" in Pascal */
+
+ structassign (*Ptr_Val_Par->Ptr_Comp, *Ptr_Glob);
+ Ptr_Val_Par->variant.var_1.Int_Comp = 5;
+ Next_Record->variant.var_1.Int_Comp
+ = Ptr_Val_Par->variant.var_1.Int_Comp;
+ Next_Record->Ptr_Comp = Ptr_Val_Par->Ptr_Comp;
+ Proc_3 (&Next_Record->Ptr_Comp);
+ /* Ptr_Val_Par->Ptr_Comp->Ptr_Comp
+ == Ptr_Glob->Ptr_Comp */
+ if (Next_Record->Discr == Ident_1)
+ /* then, executed */
+ {
+ Next_Record->variant.var_1.Int_Comp = 6;
+ Proc_6 (Ptr_Val_Par->variant.var_1.Enum_Comp,
+ &Next_Record->variant.var_1.Enum_Comp);
+ Next_Record->Ptr_Comp = Ptr_Glob->Ptr_Comp;
+ Proc_7 (Next_Record->variant.var_1.Int_Comp, 10,
+ &Next_Record->variant.var_1.Int_Comp);
+ }
+ else /* not executed */
+ structassign (*Ptr_Val_Par, *Ptr_Val_Par->Ptr_Comp);
+} /* Proc_1 */
+
+
+Proc_2 (Int_Par_Ref)
+/******************/
+ /* executed once */
+ /* *Int_Par_Ref == 1, becomes 4 */
+
+One_Fifty *Int_Par_Ref;
+{
+ One_Fifty Int_Loc;
+ Enumeration Enum_Loc;
+
+ Int_Loc = *Int_Par_Ref + 10;
+ do /* executed once */
+ if (Ch_1_Glob == 'A')
+ /* then, executed */
+ {
+ Int_Loc -= 1;
+ *Int_Par_Ref = Int_Loc - Int_Glob;
+ Enum_Loc = Ident_1;
+ } /* if */
+ while (Enum_Loc != Ident_1); /* true */
+} /* Proc_2 */
+
+
+Proc_3 (Ptr_Ref_Par)
+/******************/
+ /* executed once */
+ /* Ptr_Ref_Par becomes Ptr_Glob */
+
+Rec_Pointer *Ptr_Ref_Par;
+
+{
+ if (Ptr_Glob != Null)
+ /* then, executed */
+ *Ptr_Ref_Par = Ptr_Glob->Ptr_Comp;
+ Proc_7 (10, Int_Glob, &Ptr_Glob->variant.var_1.Int_Comp);
+} /* Proc_3 */
+
+
+Proc_4 () /* without parameters */
+/*******/
+ /* executed once */
+{
+ Boolean Bool_Loc;
+
+ Bool_Loc = Ch_1_Glob == 'A';
+ Bool_Glob = Bool_Loc | Bool_Glob;
+ Ch_2_Glob = 'B';
+} /* Proc_4 */
+
+
+Proc_5 () /* without parameters */
+/*******/
+ /* executed once */
+{
+ Ch_1_Glob = 'A';
+ Bool_Glob = false;
+} /* Proc_5 */
+
+
+ /* Procedure for the assignment of structures, */
+ /* if the C compiler doesn't support this feature */
+#ifdef NOSTRUCTASSIGN
+memcpy (d, s, l)
+register char *d;
+register char *s;
+register int l;
+{
+ while (l--) *d++ = *s++;
+}
+#endif
+
+
diff --git a/zpu/roadshow/roadshow/dhrystone/dhry_2.c b/zpu/roadshow/roadshow/dhrystone/dhry_2.c
new file mode 100644
index 0000000..ed0e5b7
--- /dev/null
+++ b/zpu/roadshow/roadshow/dhrystone/dhry_2.c
@@ -0,0 +1,192 @@
+/*
+ ****************************************************************************
+ *
+ * "DHRYSTONE" Benchmark Program
+ * -----------------------------
+ *
+ * Version: C, Version 2.1
+ *
+ * File: dhry_2.c (part 3 of 3)
+ *
+ * Date: May 25, 1988
+ *
+ * Author: Reinhold P. Weicker
+ *
+ ****************************************************************************
+ */
+
+#include "dhry.h"
+
+#ifndef REG
+#define REG
+ /* REG becomes defined as empty */
+ /* i.e. no register variables */
+#endif
+
+extern int Int_Glob;
+extern char Ch_1_Glob;
+
+
+Proc_6 (Enum_Val_Par, Enum_Ref_Par)
+/*********************************/
+ /* executed once */
+ /* Enum_Val_Par == Ident_3, Enum_Ref_Par becomes Ident_2 */
+
+Enumeration Enum_Val_Par;
+Enumeration *Enum_Ref_Par;
+{
+ *Enum_Ref_Par = Enum_Val_Par;
+ if (! Func_3 (Enum_Val_Par))
+ /* then, not executed */
+ *Enum_Ref_Par = Ident_4;
+ switch (Enum_Val_Par)
+ {
+ case Ident_1:
+ *Enum_Ref_Par = Ident_1;
+ break;
+ case Ident_2:
+ if (Int_Glob > 100)
+ /* then */
+ *Enum_Ref_Par = Ident_1;
+ else *Enum_Ref_Par = Ident_4;
+ break;
+ case Ident_3: /* executed */
+ *Enum_Ref_Par = Ident_2;
+ break;
+ case Ident_4: break;
+ case Ident_5:
+ *Enum_Ref_Par = Ident_3;
+ break;
+ } /* switch */
+} /* Proc_6 */
+
+
+Proc_7 (Int_1_Par_Val, Int_2_Par_Val, Int_Par_Ref)
+/**********************************************/
+ /* executed three times */
+ /* first call: Int_1_Par_Val == 2, Int_2_Par_Val == 3, */
+ /* Int_Par_Ref becomes 7 */
+ /* second call: Int_1_Par_Val == 10, Int_2_Par_Val == 5, */
+ /* Int_Par_Ref becomes 17 */
+ /* third call: Int_1_Par_Val == 6, Int_2_Par_Val == 10, */
+ /* Int_Par_Ref becomes 18 */
+One_Fifty Int_1_Par_Val;
+One_Fifty Int_2_Par_Val;
+One_Fifty *Int_Par_Ref;
+{
+ One_Fifty Int_Loc;
+
+ Int_Loc = Int_1_Par_Val + 2;
+ *Int_Par_Ref = Int_2_Par_Val + Int_Loc;
+} /* Proc_7 */
+
+
+Proc_8 (Arr_1_Par_Ref, Arr_2_Par_Ref, Int_1_Par_Val, Int_2_Par_Val)
+/*********************************************************************/
+ /* executed once */
+ /* Int_Par_Val_1 == 3 */
+ /* Int_Par_Val_2 == 7 */
+Arr_1_Dim Arr_1_Par_Ref;
+Arr_2_Dim Arr_2_Par_Ref;
+int Int_1_Par_Val;
+int Int_2_Par_Val;
+{
+ REG One_Fifty Int_Index;
+ REG One_Fifty Int_Loc;
+
+ Int_Loc = Int_1_Par_Val + 5;
+ Arr_1_Par_Ref [Int_Loc] = Int_2_Par_Val;
+ Arr_1_Par_Ref [Int_Loc+1] = Arr_1_Par_Ref [Int_Loc];
+ Arr_1_Par_Ref [Int_Loc+30] = Int_Loc;
+ for (Int_Index = Int_Loc; Int_Index <= Int_Loc+1; ++Int_Index)
+ Arr_2_Par_Ref [Int_Loc] [Int_Index] = Int_Loc;
+ Arr_2_Par_Ref [Int_Loc] [Int_Loc-1] += 1;
+ Arr_2_Par_Ref [Int_Loc+20] [Int_Loc] = Arr_1_Par_Ref [Int_Loc];
+ Int_Glob = 5;
+} /* Proc_8 */
+
+
+Enumeration Func_1 (Ch_1_Par_Val, Ch_2_Par_Val)
+/*************************************************/
+ /* executed three times */
+ /* first call: Ch_1_Par_Val == 'H', Ch_2_Par_Val == 'R' */
+ /* second call: Ch_1_Par_Val == 'A', Ch_2_Par_Val == 'C' */
+ /* third call: Ch_1_Par_Val == 'B', Ch_2_Par_Val == 'C' */
+
+Capital_Letter Ch_1_Par_Val;
+Capital_Letter Ch_2_Par_Val;
+{
+ Capital_Letter Ch_1_Loc;
+ Capital_Letter Ch_2_Loc;
+
+ Ch_1_Loc = Ch_1_Par_Val;
+ Ch_2_Loc = Ch_1_Loc;
+ if (Ch_2_Loc != Ch_2_Par_Val)
+ /* then, executed */
+ return (Ident_1);
+ else /* not executed */
+ {
+ Ch_1_Glob = Ch_1_Loc;
+ return (Ident_2);
+ }
+} /* Func_1 */
+
+
+Boolean Func_2 (Str_1_Par_Ref, Str_2_Par_Ref)
+/*************************************************/
+ /* executed once */
+ /* Str_1_Par_Ref == "DHRYSTONE PROGRAM, 1'ST STRING" */
+ /* Str_2_Par_Ref == "DHRYSTONE PROGRAM, 2'ND STRING" */
+
+Str_30 Str_1_Par_Ref;
+Str_30 Str_2_Par_Ref;
+{
+ REG One_Thirty Int_Loc;
+ Capital_Letter Ch_Loc;
+
+ Int_Loc = 2;
+ while (Int_Loc <= 2) /* loop body executed once */
+ if (Func_1 (Str_1_Par_Ref[Int_Loc],
+ Str_2_Par_Ref[Int_Loc+1]) == Ident_1)
+ /* then, executed */
+ {
+ Ch_Loc = 'A';
+ Int_Loc += 1;
+ } /* if, while */
+ if (Ch_Loc >= 'W' && Ch_Loc < 'Z')
+ /* then, not executed */
+ Int_Loc = 7;
+ if (Ch_Loc == 'R')
+ /* then, not executed */
+ return (true);
+ else /* executed */
+ {
+ if (strcmp (Str_1_Par_Ref, Str_2_Par_Ref) > 0)
+ /* then, not executed */
+ {
+ Int_Loc += 7;
+ Int_Glob = Int_Loc;
+ return (true);
+ }
+ else /* executed */
+ return (false);
+ } /* if Ch_Loc */
+} /* Func_2 */
+
+
+Boolean Func_3 (Enum_Par_Val)
+/***************************/
+ /* executed once */
+ /* Enum_Par_Val == Ident_3 */
+Enumeration Enum_Par_Val;
+{
+ Enumeration Enum_Loc;
+
+ Enum_Loc = Enum_Par_Val;
+ if (Enum_Loc == Ident_3)
+ /* then, executed */
+ return (true);
+ else /* not executed */
+ return (false);
+} /* Func_3 */
+
diff --git a/zpu/roadshow/roadshow/dhrystone/dhry_c.dif b/zpu/roadshow/roadshow/dhrystone/dhry_c.dif
new file mode 100644
index 0000000..8bcaaea
--- /dev/null
+++ b/zpu/roadshow/roadshow/dhrystone/dhry_c.dif
@@ -0,0 +1,141 @@
+7c7
+< * Version: C, Version 2.1
+---
+> * Version: C, Version 2.0
+9c9
+< * File: dhry.h (part 1 of 3)
+---
+> * File: dhry_global.h (part 1 of 3)
+11c11
+< * Date: May 25, 1988
+---
+> * Date: March 3, 1988
+30c30
+< * In addition, Berkeley UNIX system calls "times ()" or "time ()"
+---
+> * In addition, UNIX system calls "times ()" or "time ()"
+44c44
+< * Please send results to Rick Richardson and/or Reinhold Weicker.
+---
+> * Please send results to Reinhold Weicker and/or Rick Richardson.
+59c59
+< * History: This version C/2.1 has been made for two reasons:
+---
+> * History: This version C/2.0 has been made for two reasons:
+123,129d122
+< * Version 2.1 is identical to version 2.0 distributed via
+< * the UNIX network Usenet in March 1988 except that it corrects
+< * some minor deficiencies that were found by users of version 2.0.
+< * The only change within the measurement loop is that a
+< * non-executed "else" part was added to the "if" statement in
+< * Func_3, and a non-executed "else" part removed from Proc_3.
+< *
+165,167c158,160
+< * -DHZ=nnn
+< * In Berkeley UNIX, the function "times" returns process
+< * time in 1/HZ seconds, with HZ = 60 for most systems.
+---
+> * -DHZ=nnn (default: 60)
+> * The function "times" returns process times in
+> * 1/HZ seconds, with HZ = 60 for most systems.
+169c162
+< * A VALUE.
+---
+> * THE DEFAULT VALUE.
+176,178c169,171
+< * - dhry.h (this file, containing global definitions and comments)
+< * - dhry_1.c (containing the code corresponding to Ada package Pack_1)
+< * - dhry_2.c (containing the code corresponding to Ada package Pack_2)
+---
+> * - dhry_global.h (this file, containing global definitions and comments)
+> * - dhry_pack_1.c (containing the code corresponding to Ada package Pack_1)
+> * - dhry_pack_2.c (containing the code corresponding to Ada package Pack_2)
+350a344
+> #ifndef TIMES
+353,354c347,354
+< /* Use times(2) time function unless */
+< /* explicitly defined otherwise */
+---
+> #endif
+> /* Use "times" function for measurement */
+> /* unless explicitly defined otherwise */
+> #ifndef HZ
+> #define HZ 60
+> #endif
+> /* Use HZ = 60 for "times" function */
+> /* unless explicitly defined otherwise */
+363c363
+< /* Berkeley UNIX C returns process times in seconds/HZ */
+---
+> /* UNIX C returns process times in seconds/HZ */
+7c7
+< * Version: C, Version 2.1
+---
+> * Version: C, Version 2.0
+9c9
+< * File: dhry_1.c (part 2 of 3)
+---
+> * File: dhry_pack_1.c (part 2 of 3)
+11c11
+< * Date: May 25, 1988
+---
+> * Date: March 3, 1988
+18c18
+< #include "dhry.h"
+---
+> #include "dhry_global.h"
+50,51d49
+< #define Too_Small_Time 120
+< /* Measurements should last at least about 2 seconds */
+55a54,55
+> #endif
+>
+58d57
+< #endif
+73a73
+>
+84a85
+>
+99,100c100,102
+< /* Was missing in published program. Without this statement, */
+< /* Arr_2_Glob [8][7] would have an undefined value. */
+---
+> /* Was missing in published program. Without this */
+> /* initialization, Arr_2_Glob [8][7] would have an */
+> /* undefined value. */
+105c107
+< printf ("Dhrystone Benchmark, Version 2.1 (Language: C)\n");
+---
+> printf ("Dhrystone Benchmark, Version 2.0 (Language: C)\n");
+281c283
+< /******************/
+---
+> /**********************/
+338c340
+< /******************/
+---
+> /**********************/
+347a350,351
+> else /* not executed */
+> Int_Glob = 100;
+349a354
+>
+7c7
+< * Version: C, Version 2.1
+---
+> * Version: C, Version 2.0
+9c9
+< * File: dhry_2.c (part 3 of 3)
+---
+> * File: dhry_pack_2.c (part 3 of 3)
+11c11
+< * Date: May 25, 1988
+---
+> * Date: March 3, 1988
+18c18
+< #include "dhry.h"
+---
+> #include "dhry_global.h"
+189,190d188
+< else /* not executed */
+< return (false);
diff --git a/zpu/roadshow/roadshow/dhrystone/dhrystone.bin b/zpu/roadshow/roadshow/dhrystone/dhrystone.bin
new file mode 100644
index 0000000..ee1a6fe
--- /dev/null
+++ b/zpu/roadshow/roadshow/dhrystone/dhrystone.bin
Binary files differ
diff --git a/zpu/roadshow/roadshow/dhrystone/dhrystone.zpu b/zpu/roadshow/roadshow/dhrystone/dhrystone.zpu
new file mode 100644
index 0000000..e37e59f
--- /dev/null
+++ b/zpu/roadshow/roadshow/dhrystone/dhrystone.zpu
Binary files differ
diff --git a/zpu/roadshow/roadshow/dhrystone/submit.frm b/zpu/roadshow/roadshow/dhrystone/submit.frm
new file mode 100644
index 0000000..a75a689
--- /dev/null
+++ b/zpu/roadshow/roadshow/dhrystone/submit.frm
@@ -0,0 +1,17 @@
+DHRYSTONE 2.1 BENCHMARK REPORTING FORM
+MANUF:
+MODEL:
+PROC:
+CLOCK:
+OS:
+OVERSION:
+COMPILER:
+CVERSION:
+OPTIONS:
+NOREG:
+REG:
+NOTES:
+DATE:
+SUBMITTER:
+CODESIZE:
+MAILTO: uunet!pcrat!dry2
diff --git a/zpu/roadshow/roadshow/ecos/codesize/zpuarmcodesize.htm b/zpu/roadshow/roadshow/ecos/codesize/zpuarmcodesize.htm
new file mode 100644
index 0000000..3631145
--- /dev/null
+++ b/zpu/roadshow/roadshow/ecos/codesize/zpuarmcodesize.htm
@@ -0,0 +1,1049 @@
+<html xmlns:o="urn:schemas-microsoft-com:office:office"
+xmlns:x="urn:schemas-microsoft-com:office:excel"
+xmlns="http://www.w3.org/TR/REC-html40">
+
+<head>
+<meta http-equiv=Content-Type content="text/html; charset=windows-1252">
+<meta name=ProgId content=Excel.Sheet>
+<meta name=Generator content="Microsoft Excel 9">
+<link rel=File-List href="./zpuarmcodesize2_files/filelist.xml">
+<style id="test_15598_Styles">
+<!--table
+ {mso-displayed-decimal-separator:"\,";
+ mso-displayed-thousand-separator:" ";}
+.xl1515598
+ {padding-top:1px;
+ padding-right:1px;
+ padding-left:1px;
+ mso-ignore:padding;
+ color:windowtext;
+ font-size:10.0pt;
+ font-weight:400;
+ font-style:normal;
+ text-decoration:none;
+ font-family:Arial;
+ mso-generic-font-family:auto;
+ mso-font-charset:0;
+ mso-number-format:General;
+ text-align:general;
+ vertical-align:bottom;
+ mso-background-source:auto;
+ mso-pattern:auto;
+ white-space:nowrap;}
+.xl2215598
+ {padding-top:1px;
+ padding-right:1px;
+ padding-left:1px;
+ mso-ignore:padding;
+ color:windowtext;
+ font-size:10.0pt;
+ font-weight:400;
+ font-style:normal;
+ text-decoration:none;
+ font-family:Arial;
+ mso-generic-font-family:auto;
+ mso-font-charset:0;
+ mso-number-format:General;
+ text-align:center;
+ vertical-align:bottom;
+ mso-background-source:auto;
+ mso-pattern:auto;
+ white-space:nowrap;}
+.xl2315598
+ {padding-top:1px;
+ padding-right:1px;
+ padding-left:1px;
+ mso-ignore:padding;
+ color:windowtext;
+ font-size:10.0pt;
+ font-weight:400;
+ font-style:normal;
+ text-decoration:none;
+ font-family:Arial;
+ mso-generic-font-family:auto;
+ mso-font-charset:0;
+ mso-number-format:"0\\ %";
+ text-align:general;
+ vertical-align:bottom;
+ mso-background-source:auto;
+ mso-pattern:auto;
+ white-space:nowrap;}
+.xl2415598
+ {padding-top:1px;
+ padding-right:1px;
+ padding-left:1px;
+ mso-ignore:padding;
+ color:windowtext;
+ font-size:10.0pt;
+ font-weight:400;
+ font-style:normal;
+ text-decoration:none;
+ font-family:Arial;
+ mso-generic-font-family:auto;
+ mso-font-charset:0;
+ mso-number-format:General;
+ text-align:right;
+ vertical-align:bottom;
+ mso-background-source:auto;
+ mso-pattern:auto;
+ white-space:nowrap;}
+.xl2515598
+ {padding-top:1px;
+ padding-right:1px;
+ padding-left:1px;
+ mso-ignore:padding;
+ color:windowtext;
+ font-size:10.0pt;
+ font-weight:400;
+ font-style:normal;
+ text-decoration:none;
+ font-family:Arial;
+ mso-generic-font-family:auto;
+ mso-font-charset:0;
+ mso-number-format:"\@";
+ text-align:right;
+ vertical-align:bottom;
+ mso-background-source:auto;
+ mso-pattern:auto;
+ white-space:nowrap;}
+-->
+</style>
+<title>ZPU vs. ARM non-thumb eCos codesize</title>
+</head>
+
+<body>
+<!--[if !excel]>&nbsp;&nbsp;<![endif]-->
+<!--The following information was generated by Microsoft Excel's Publish as Web
+Page wizard.-->
+<!--If the same item is republished from Excel, all information between the DIV
+tags will be replaced.-->
+<!----------------------------->
+<!--START OF OUTPUT FROM EXCEL PUBLISH AS WEB PAGE WIZARD -->
+<!----------------------------->
+
+<div id="test_15598" align=center x:publishsource="Excel">
+
+<h1 style='color:black;font-family:Arial;font-size:14.0pt;font-weight:800;
+font-style:normal'>ZPU vs. ARM non-thumb eCos codesize</h1>
+
+<table x:str border=0 cellpadding=0 cellspacing=0 width=883 style='border-collapse:
+ collapse;table-layout:fixed;width:663pt'>
+ <col width=64 span=5 style='width:48pt'>
+ <col width=62 style='mso-width-source:userset;mso-width-alt:2267;width:47pt'>
+ <col width=64 span=6 style='width:48pt'>
+ <col width=117 style='mso-width-source:userset;mso-width-alt:4278;width:88pt'>
+ <tr height=17 style='height:12.75pt'>
+ <td colspan=6 height=17 class=xl2215598 width=382 style='height:12.75pt;
+ width:287pt'>ZPU</td>
+ <td colspan=6 class=xl2215598 width=384 style='width:288pt'>ARM
+ non-thumb(eCos Thumb does not compile out of the box)</td>
+ <td class=xl1515598 width=117 style='width:88pt'></td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>filename</td>
+ <td class=xl1515598>text</td>
+ <td class=xl1515598>data</td>
+ <td class=xl1515598>bss</td>
+ <td class=xl1515598>dec</td>
+ <td class=xl1515598>hex</td>
+ <td class=xl1515598>filename</td>
+ <td class=xl1515598>text</td>
+ <td class=xl1515598>data</td>
+ <td class=xl1515598>bss</td>
+ <td class=xl1515598>dec</td>
+ <td class=xl1515598>hex</td>
+ <td class=xl1515598>ZPU text/ZPU ARM</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>bin_sem0</td>
+ <td class=xl2415598 x:num>15761</td>
+ <td class=xl2415598 x:num>1504</td>
+ <td class=xl2415598 x:num>12060</td>
+ <td class=xl2415598 x:num>29325</td>
+ <td class=xl2515598>728d</td>
+ <td class=xl2415598>bin_sem0</td>
+ <td class=xl2415598 x:num>25204</td>
+ <td class=xl2415598 x:num>692</td>
+ <td class=xl2415598 x:num>16976</td>
+ <td class=xl2415598 x:num>42872</td>
+ <td class=xl2415598>a778</td>
+ <td class=xl2315598 align=right x:num="0.6253372480558641" x:fmla="=B3/H3">63
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>bin_sem1</td>
+ <td class=xl2415598 x:num>16907</td>
+ <td class=xl2415598 x:num>1512</td>
+ <td class=xl2415598 x:num>14436</td>
+ <td class=xl2415598 x:num>32855</td>
+ <td class=xl2515598 x:num>8057</td>
+ <td class=xl2415598>bin_sem1</td>
+ <td class=xl2415598 x:num>26644</td>
+ <td class=xl2415598 x:num>700</td>
+ <td class=xl2415598 x:num>22096</td>
+ <td class=xl2415598 x:num>49440</td>
+ <td class=xl2415598>c120</td>
+ <td class=xl2315598 align=right x:num="0.63455186908872541" x:fmla="=B4/H4">63
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>bin_sem2</td>
+ <td class=xl2415598 x:num>17105</td>
+ <td class=xl2415598 x:num>1524</td>
+ <td class=xl2415598 x:num>30032</td>
+ <td class=xl2415598 x:num>48661</td>
+ <td class=xl2515598>be15</td>
+ <td class=xl2415598>bin_sem2</td>
+ <td class=xl2415598 x:num>26996</td>
+ <td class=xl2415598 x:num>712</td>
+ <td class=xl2415598 x:num>55584</td>
+ <td class=xl2415598 x:num>83292</td>
+ <td class=xl2415598>1455c</td>
+ <td class=xl2315598 align=right x:num="0.63361238702029932" x:fmla="=B5/H5">63
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>bin_sem3</td>
+ <td class=xl2415598 x:num>17186</td>
+ <td class=xl2415598 x:num>1512</td>
+ <td class=xl2415598 x:num>14436</td>
+ <td class=xl2415598 x:num>33134</td>
+ <td class=xl2515598>816e</td>
+ <td class=xl2415598>bin_sem3</td>
+ <td class=xl2415598 x:num>27008</td>
+ <td class=xl2415598 x:num>700</td>
+ <td class=xl2415598 x:num>22100</td>
+ <td class=xl2415598 x:num>49808</td>
+ <td class=xl2415598>c290</td>
+ <td class=xl2315598 align=right x:num="0.63632997630331756" x:fmla="=B6/H6">64
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>clock0</td>
+ <td class=xl2415598 x:num>18986</td>
+ <td class=xl2415598 x:num>1500</td>
+ <td class=xl2415598 x:num>12036</td>
+ <td class=xl2415598 x:num>32522</td>
+ <td class=xl2515598>7f0a</td>
+ <td class=xl2415598>clock0</td>
+ <td class=xl2415598 x:num>28992</td>
+ <td class=xl2415598 x:num>688</td>
+ <td class=xl2415598 x:num>16944</td>
+ <td class=xl2415598 x:num>46624</td>
+ <td class=xl2415598>b620</td>
+ <td class=xl2315598 align=right x:num="0.65487030905077259" x:fmla="=B7/H7">65
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>clock1</td>
+ <td class=xl2415598 x:num>15812</td>
+ <td class=xl2415598 x:num>1504</td>
+ <td class=xl2415598 x:num>13236</td>
+ <td class=xl2415598 x:num>30552</td>
+ <td class=xl2515598 x:num>7758</td>
+ <td class=xl2415598>clock1</td>
+ <td class=xl2415598 x:num>25456</td>
+ <td class=xl2415598 x:num>692</td>
+ <td class=xl2415598 x:num>19532</td>
+ <td class=xl2415598 x:num>45680</td>
+ <td class=xl2415598>b270</td>
+ <td class=xl2315598 align=right x:num="0.62115021998742925" x:fmla="=B8/H8">62
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>clockcnv</td>
+ <td class=xl2415598 x:num>25095</td>
+ <td class=xl2415598 x:num>1972</td>
+ <td class=xl2415598 x:num>13224</td>
+ <td class=xl2415598 x:num>40291</td>
+ <td class=xl2515598>9d63</td>
+ <td class=xl2415598>clockcnv</td>
+ <td class=xl2415598 x:num>34572</td>
+ <td class=xl2415598 x:num>1160</td>
+ <td class=xl2415598 x:num>19520</td>
+ <td class=xl2415598 x:num>55252</td>
+ <td class=xl2415598>d7d4</td>
+ <td class=xl2315598 align=right x:num="0.72587643179451578" x:fmla="=B9/H9">73
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>clocktruth</td>
+ <td class=xl2415598 x:num>16437</td>
+ <td class=xl2415598 x:num>1500</td>
+ <td class=xl2415598 x:num>13224</td>
+ <td class=xl2415598 x:num>31161</td>
+ <td class=xl2515598>79b9</td>
+ <td class=xl2415598>clocktruth</td>
+ <td class=xl2415598 x:num>26224</td>
+ <td class=xl2415598 x:num>688</td>
+ <td class=xl2415598 x:num>19508</td>
+ <td class=xl2415598 x:num>46420</td>
+ <td class=xl2415598>b554</td>
+ <td class=xl2315598 align=right x:num="0.62679225137278827" x:fmla="=B10/H10">63
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>cnt_sem0</td>
+ <td class=xl2415598 x:num>15762</td>
+ <td class=xl2415598 x:num>1504</td>
+ <td class=xl2415598 x:num>12060</td>
+ <td class=xl2415598 x:num>29326</td>
+ <td class=xl2515598>728e</td>
+ <td class=xl2415598>cnt_sem0</td>
+ <td class=xl2415598 x:num>25204</td>
+ <td class=xl2415598 x:num>692</td>
+ <td class=xl2415598 x:num>16976</td>
+ <td class=xl2415598 x:num>42872</td>
+ <td class=xl2415598>a778</td>
+ <td class=xl2315598 align=right x:num="0.62537692429773051" x:fmla="=B11/H11">63
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>cnt_sem1</td>
+ <td class=xl2415598 x:num>17124</td>
+ <td class=xl2415598 x:num>1512</td>
+ <td class=xl2415598 x:num>14436</td>
+ <td class=xl2415598 x:num>33072</td>
+ <td class=xl2515598 x:num>8130</td>
+ <td class=xl2415598>cnt_sem1</td>
+ <td class=xl2415598 x:num>26888</td>
+ <td class=xl2415598 x:num>700</td>
+ <td class=xl2415598 x:num>22108</td>
+ <td class=xl2415598 x:num>49696</td>
+ <td class=xl2415598>c220</td>
+ <td class=xl2315598 align=right x:num="0.63686402856292768" x:fmla="=B12/H12">64
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>dhrystone</td>
+ <td class=xl2415598 x:num>35947</td>
+ <td class=xl2415598 x:num>1564</td>
+ <td class=xl2415598 x:num>22512</td>
+ <td class=xl2415598 x:num>60023</td>
+ <td class=xl2515598>ea77</td>
+ <td class=xl2415598>dhrystone</td>
+ <td class=xl2415598 x:num>44180</td>
+ <td class=xl2415598 x:num>752</td>
+ <td class=xl2415598 x:num>27416</td>
+ <td class=xl2415598 x:num>72348</td>
+ <td class=xl2415598>11a9c</td>
+ <td class=xl2315598 align=right x:num="0.8136487098234495" x:fmla="=B13/H13">81
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>except1</td>
+ <td class=xl2415598 x:num>16428</td>
+ <td class=xl2415598 x:num>1500</td>
+ <td class=xl2415598 x:num>13228</td>
+ <td class=xl2415598 x:num>31156</td>
+ <td class=xl2515598>79b4</td>
+ <td class=xl2415598>except1</td>
+ <td class=xl2415598 x:num>26088</td>
+ <td class=xl2415598 x:num>688</td>
+ <td class=xl2415598 x:num>19520</td>
+ <td class=xl2415598 x:num>46296</td>
+ <td class=xl2415598>b4d8</td>
+ <td class=xl2315598 align=right x:num="0.62971481140754371" x:fmla="=B14/H14">63
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>flag0</td>
+ <td class=xl2415598 x:num>15751</td>
+ <td class=xl2415598 x:num>1504</td>
+ <td class=xl2415598 x:num>12052</td>
+ <td class=xl2415598 x:num>29307</td>
+ <td class=xl2515598>727b</td>
+ <td class=xl2415598>flag0</td>
+ <td class=xl2415598 x:num>25236</td>
+ <td class=xl2415598 x:num>692</td>
+ <td class=xl2415598 x:num>16968</td>
+ <td class=xl2415598 x:num>42896</td>
+ <td class=xl2415598>a790</td>
+ <td class=xl2315598 align=right x:num="0.62414804247899824" x:fmla="=B15/H15">62
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>flag1</td>
+ <td class=xl2415598 x:num>19145</td>
+ <td class=xl2415598 x:num>1512</td>
+ <td class=xl2415598 x:num>15624</td>
+ <td class=xl2415598 x:num>36281</td>
+ <td class=xl2515598>8db9</td>
+ <td class=xl2415598>flag1</td>
+ <td class=xl2415598 x:num>29532</td>
+ <td class=xl2415598 x:num>700</td>
+ <td class=xl2415598 x:num>24668</td>
+ <td class=xl2415598 x:num>54900</td>
+ <td class=xl2415598>d674</td>
+ <td class=xl2315598 align=right x:num="0.64827983204659356" x:fmla="=B16/H16">65
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>fptest</td>
+ <td class=xl2415598 x:num>20053</td>
+ <td class=xl2415598 x:num>1516</td>
+ <td class=xl2415598 x:num>102908</td>
+ <td class=xl2415598 x:num>124477</td>
+ <td class=xl2515598>1e63d</td>
+ <td class=xl2415598>fptest</td>
+ <td class=xl2415598 x:num>29508</td>
+ <td class=xl2415598 x:num>704</td>
+ <td class=xl2415598 x:num>109652</td>
+ <td class=xl2415598 x:num>139864</td>
+ <td class=xl2415598 x:num>22258</td>
+ <td class=xl2315598 align=right x:num="0.67957841941168495" x:fmla="=B17/H17">68
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>intr0</td>
+ <td class=xl2415598 x:num>15998</td>
+ <td class=xl2415598 x:num>1496</td>
+ <td class=xl2415598 x:num>12092</td>
+ <td class=xl2415598 x:num>29586</td>
+ <td class=xl2515598 x:num>7392</td>
+ <td class=xl2415598>intr0</td>
+ <td class=xl2415598 x:num>25932</td>
+ <td class=xl2415598 x:num>684</td>
+ <td class=xl2415598 x:num>17016</td>
+ <td class=xl2415598 x:num>43632</td>
+ <td class=xl2415598>aa70</td>
+ <td class=xl2315598 align=right x:num="0.6169211784667592" x:fmla="=B18/H18">62
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>kalarm0</td>
+ <td class=xl2415598 x:num>16080</td>
+ <td class=xl2415598 x:num>1496</td>
+ <td class=xl2415598 x:num>12200</td>
+ <td class=xl2415598 x:num>29776</td>
+ <td class=xl2515598 x:num>7450</td>
+ <td class=xl2415598>kalarm0</td>
+ <td class=xl2415598 x:num>25824</td>
+ <td class=xl2415598 x:num>684</td>
+ <td class=xl2415598 x:num>17112</td>
+ <td class=xl2415598 x:num>43620</td>
+ <td class=xl2415598>aa64</td>
+ <td class=xl2315598 align=right x:num="0.62267657992565051" x:fmla="=B19/H19">62
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>kcache1</td>
+ <td class=xl2415598 x:num>15327</td>
+ <td class=xl2415598 x:num>1496</td>
+ <td class=xl2415598 x:num>12036</td>
+ <td class=xl2415598 x:num>28859</td>
+ <td class=xl2515598>70bb</td>
+ <td class=xl2415598>kcache1</td>
+ <td class=xl2415598 x:num>24728</td>
+ <td class=xl2415598 x:num>684</td>
+ <td class=xl2415598 x:num>16956</td>
+ <td class=xl2415598 x:num>42368</td>
+ <td class=xl2415598>a580</td>
+ <td class=xl2315598 align=right x:num="0.61982368165642188" x:fmla="=B20/H20">62
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>kcache2</td>
+ <td class=xl2415598 x:num>15549</td>
+ <td class=xl2415598 x:num>1496</td>
+ <td class=xl2415598 x:num>13224</td>
+ <td class=xl2415598 x:num>30269</td>
+ <td class=xl2515598>763d</td>
+ <td class=xl2415598>kcache2</td>
+ <td class=xl2415598 x:num>25168</td>
+ <td class=xl2415598 x:num>684</td>
+ <td class=xl2415598 x:num>19512</td>
+ <td class=xl2415598 x:num>45364</td>
+ <td class=xl2415598>b134</td>
+ <td class=xl2315598 align=right x:num="0.61780832803560082" x:fmla="=B21/H21">62
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>kclock0</td>
+ <td class=xl2415598 x:num>18291</td>
+ <td class=xl2415598 x:num>1500</td>
+ <td class=xl2415598 x:num>12260</td>
+ <td class=xl2415598 x:num>32051</td>
+ <td class=xl2515598>7d33</td>
+ <td class=xl2415598>kclock0</td>
+ <td class=xl2415598 x:num>28112</td>
+ <td class=xl2415598 x:num>688</td>
+ <td class=xl2415598 x:num>17168</td>
+ <td class=xl2415598 x:num>45968</td>
+ <td class=xl2415598>b390</td>
+ <td class=xl2315598 align=right x:num="0.65064741035856577" x:fmla="=B22/H22">65
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>kclock1</td>
+ <td class=xl2415598 x:num>16231</td>
+ <td class=xl2415598 x:num>1500</td>
+ <td class=xl2415598 x:num>13232</td>
+ <td class=xl2415598 x:num>30963</td>
+ <td class=xl2515598>78f3</td>
+ <td class=xl2415598>kclock1</td>
+ <td class=xl2415598 x:num>25976</td>
+ <td class=xl2415598 x:num>688</td>
+ <td class=xl2415598 x:num>19524</td>
+ <td class=xl2415598 x:num>46188</td>
+ <td class=xl2415598>b46c</td>
+ <td class=xl2315598 align=right x:num="0.6248460117031106" x:fmla="=B23/H23">62
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>kexcept1</td>
+ <td class=xl2415598 x:num>16572</td>
+ <td class=xl2415598 x:num>1496</td>
+ <td class=xl2415598 x:num>13228</td>
+ <td class=xl2415598 x:num>31296</td>
+ <td class=xl2515598>7a40</td>
+ <td class=xl2415598>kexcept1</td>
+ <td class=xl2415598 x:num>26372</td>
+ <td class=xl2415598 x:num>684</td>
+ <td class=xl2415598 x:num>19512</td>
+ <td class=xl2415598 x:num>46568</td>
+ <td class=xl2415598>b5e8</td>
+ <td class=xl2315598 align=right x:num="0.62839375094797512" x:fmla="=B24/H24">63
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>kflag0</td>
+ <td class=xl2415598 x:num>15618</td>
+ <td class=xl2415598 x:num>1496</td>
+ <td class=xl2415598 x:num>12060</td>
+ <td class=xl2415598 x:num>29174</td>
+ <td class=xl2515598>71f6</td>
+ <td class=xl2415598>kflag0</td>
+ <td class=xl2415598 x:num>25140</td>
+ <td class=xl2415598 x:num>684</td>
+ <td class=xl2415598 x:num>16968</td>
+ <td class=xl2415598 x:num>42792</td>
+ <td class=xl2415598>a728</td>
+ <td class=xl2315598 align=right x:num="0.62124105011933173" x:fmla="=B25/H25">62
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>kflag1</td>
+ <td class=xl2415598 x:num>19287</td>
+ <td class=xl2415598 x:num>1500</td>
+ <td class=xl2415598 x:num>15624</td>
+ <td class=xl2415598 x:num>36411</td>
+ <td class=xl2515598>8e3b</td>
+ <td class=xl2415598>kflag1</td>
+ <td class=xl2415598 x:num>29824</td>
+ <td class=xl2415598 x:num>688</td>
+ <td class=xl2415598 x:num>24660</td>
+ <td class=xl2415598 x:num>55172</td>
+ <td class=xl2415598>d784</td>
+ <td class=xl2315598 align=right x:num="0.64669393776824036" x:fmla="=B26/H26">65
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>kill</td>
+ <td class=xl2415598 x:num>16887</td>
+ <td class=xl2415598 x:num>1516</td>
+ <td class=xl2415598 x:num>15628</td>
+ <td class=xl2415598 x:num>34031</td>
+ <td class=xl2515598>84ef</td>
+ <td class=xl2415598>kill</td>
+ <td class=xl2415598 x:num>26896</td>
+ <td class=xl2415598 x:num>704</td>
+ <td class=xl2415598 x:num>24656</td>
+ <td class=xl2415598 x:num>52256</td>
+ <td class=xl2415598>cc20</td>
+ <td class=xl2315598 align=right x:num="0.62786287923854844" x:fmla="=B27/H27">63
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>kintr0</td>
+ <td class=xl2415598 x:num>16186</td>
+ <td class=xl2415598 x:num>1496</td>
+ <td class=xl2415598 x:num>12128</td>
+ <td class=xl2415598 x:num>29810</td>
+ <td class=xl2515598 x:num>7472</td>
+ <td class=xl2415598>kintr0</td>
+ <td class=xl2415598 x:num>26088</td>
+ <td class=xl2415598 x:num>684</td>
+ <td class=xl2415598 x:num>17028</td>
+ <td class=xl2415598 x:num>43800</td>
+ <td class=xl2415598>ab18</td>
+ <td class=xl2315598 align=right x:num="0.62043851579270159" x:fmla="=B28/H28">62
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>klock</td>
+ <td class=xl2415598 x:num>19724</td>
+ <td class=xl2415598 x:num>1504</td>
+ <td class=xl2415598 x:num>14516</td>
+ <td class=xl2415598 x:num>35744</td>
+ <td class=xl2515598>8ba0</td>
+ <td class=xl2415598>klock</td>
+ <td class=xl2415598 x:num>30812</td>
+ <td class=xl2415598 x:num>692</td>
+ <td class=xl2415598 x:num>22176</td>
+ <td class=xl2415598 x:num>53680</td>
+ <td class=xl2415598>d1b0</td>
+ <td class=xl2315598 align=right x:num="0.64014020511489034" x:fmla="=B29/H29">64
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>kmbox1</td>
+ <td class=xl2415598 x:num>18283</td>
+ <td class=xl2415598 x:num>1500</td>
+ <td class=xl2415598 x:num>14592</td>
+ <td class=xl2415598 x:num>34375</td>
+ <td class=xl2515598 x:num>8647</td>
+ <td class=xl2415598>kmbox1</td>
+ <td class=xl2415598 x:num>28504</td>
+ <td class=xl2415598 x:num>688</td>
+ <td class=xl2415598 x:num>22260</td>
+ <td class=xl2415598 x:num>51452</td>
+ <td class=xl2415598>c8fc</td>
+ <td class=xl2315598 align=right x:num="0.6414187482458602" x:fmla="=B30/H30">64
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>kmutex0</td>
+ <td class=xl2415598 x:num>15539</td>
+ <td class=xl2415598 x:num>1496</td>
+ <td class=xl2415598 x:num>12064</td>
+ <td class=xl2415598 x:num>29099</td>
+ <td class=xl2515598>71ab</td>
+ <td class=xl2415598>kmutex0</td>
+ <td class=xl2415598 x:num>24984</td>
+ <td class=xl2415598 x:num>684</td>
+ <td class=xl2415598 x:num>16984</td>
+ <td class=xl2415598 x:num>42652</td>
+ <td class=xl2415598>a69c</td>
+ <td class=xl2315598 align=right x:num="0.62195805315401853" x:fmla="=B31/H31">62
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>kmutex1</td>
+ <td class=xl2415598 x:num>16524</td>
+ <td class=xl2415598 x:num>1504</td>
+ <td class=xl2415598 x:num>15664</td>
+ <td class=xl2415598 x:num>33692</td>
+ <td class=xl2515598>839c</td>
+ <td class=xl2415598>kmutex1</td>
+ <td class=xl2415598 x:num>26504</td>
+ <td class=xl2415598 x:num>692</td>
+ <td class=xl2415598 x:num>24704</td>
+ <td class=xl2415598 x:num>51900</td>
+ <td class=xl2415598>cabc</td>
+ <td class=xl2315598 align=right x:num="0.62345306368849984" x:fmla="=B32/H32">62
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>kmutex3</td>
+ <td class=xl2415598 x:num>18272</td>
+ <td class=xl2415598 x:num>1712</td>
+ <td class=xl2415598 x:num>20348</td>
+ <td class=xl2415598 x:num>40332</td>
+ <td class=xl2515598>9d8c</td>
+ <td class=xl2415598>kmutex3</td>
+ <td class=xl2415598 x:num>28792</td>
+ <td class=xl2415598 x:num>900</td>
+ <td class=xl2415598 x:num>34892</td>
+ <td class=xl2415598 x:num>64584</td>
+ <td class=xl2415598>fc48</td>
+ <td class=xl2315598 align=right x:num="0.63462072797999447" x:fmla="=B33/H33">63
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>kmutex4</td>
+ <td class=xl2415598 x:num>18682</td>
+ <td class=xl2415598 x:num>1608</td>
+ <td class=xl2415598 x:num>20352</td>
+ <td class=xl2415598 x:num>40642</td>
+ <td class=xl2515598>9ec2</td>
+ <td class=xl2415598>kmutex4</td>
+ <td class=xl2415598 x:num>29264</td>
+ <td class=xl2415598 x:num>796</td>
+ <td class=xl2415598 x:num>34896</td>
+ <td class=xl2415598 x:num>64956</td>
+ <td class=xl2415598>fdbc</td>
+ <td class=xl2315598 align=right x:num="0.63839529797703665" x:fmla="=B34/H34">64
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>ksched1</td>
+ <td class=xl2415598 x:num>15619</td>
+ <td class=xl2415598 x:num>1496</td>
+ <td class=xl2415598 x:num>14412</td>
+ <td class=xl2415598 x:num>31527</td>
+ <td class=xl2515598>7b27</td>
+ <td class=xl2415598>ksched1</td>
+ <td class=xl2415598 x:num>25240</td>
+ <td class=xl2415598 x:num>684</td>
+ <td class=xl2415598 x:num>22084</td>
+ <td class=xl2415598 x:num>48008</td>
+ <td class=xl2415598>bb88</td>
+ <td class=xl2315598 align=right x:num="0.61881933438985737" x:fmla="=B35/H35">62
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>ksem0</td>
+ <td class=xl2415598 x:num>15567</td>
+ <td class=xl2415598 x:num>1496</td>
+ <td class=xl2415598 x:num>12060</td>
+ <td class=xl2415598 x:num>29123</td>
+ <td class=xl2515598>71c3</td>
+ <td class=xl2415598>ksem0</td>
+ <td class=xl2415598 x:num>25044</td>
+ <td class=xl2415598 x:num>684</td>
+ <td class=xl2415598 x:num>16968</td>
+ <td class=xl2415598 x:num>42696</td>
+ <td class=xl2415598>a6c8</td>
+ <td class=xl2315598 align=right x:num="0.62158600862482027" x:fmla="=B36/H36">62
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>ksem1</td>
+ <td class=xl2415598 x:num>17063</td>
+ <td class=xl2415598 x:num>1500</td>
+ <td class=xl2415598 x:num>14436</td>
+ <td class=xl2415598 x:num>32999</td>
+ <td class=xl2515598 x:num="800000000">8E+08</td>
+ <td class=xl2415598>ksem1</td>
+ <td class=xl2415598 x:num>26988</td>
+ <td class=xl2415598 x:num>688</td>
+ <td class=xl2415598 x:num>22100</td>
+ <td class=xl2415598 x:num>49776</td>
+ <td class=xl2415598>c270</td>
+ <td class=xl2315598 align=right x:num="0.63224396027864238" x:fmla="=B37/H37">63
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>kthread0</td>
+ <td class=xl2415598 x:num>15504</td>
+ <td class=xl2415598 x:num>1496</td>
+ <td class=xl2415598 x:num>13228</td>
+ <td class=xl2415598 x:num>30228</td>
+ <td class=xl2515598 x:num>7614</td>
+ <td class=xl2415598>kthread0</td>
+ <td class=xl2415598 x:num>25028</td>
+ <td class=xl2415598 x:num>684</td>
+ <td class=xl2415598 x:num>19512</td>
+ <td class=xl2415598 x:num>45224</td>
+ <td class=xl2415598>b0a8</td>
+ <td class=xl2315598 align=right x:num="0.61946619785839863" x:fmla="=B38/H38">62
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>kthread1</td>
+ <td class=xl2415598 x:num>16167</td>
+ <td class=xl2415598 x:num>1496</td>
+ <td class=xl2415598 x:num>14412</td>
+ <td class=xl2415598 x:num>32075</td>
+ <td class=xl2515598>7d4b</td>
+ <td class=xl2415598>kthread1</td>
+ <td class=xl2415598 x:num>25996</td>
+ <td class=xl2415598 x:num>684</td>
+ <td class=xl2415598 x:num>22080</td>
+ <td class=xl2415598 x:num>48760</td>
+ <td class=xl2415598>be78</td>
+ <td class=xl2315598 align=right x:num="0.62190336974919214" x:fmla="=B39/H39">62
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>mbox1</td>
+ <td class=xl2415598 x:num>18281</td>
+ <td class=xl2415598 x:num>1512</td>
+ <td class=xl2415598 x:num>14580</td>
+ <td class=xl2415598 x:num>34373</td>
+ <td class=xl2515598 x:num>8645</td>
+ <td class=xl2415598>mbox1</td>
+ <td class=xl2415598 x:num>28552</td>
+ <td class=xl2415598 x:num>700</td>
+ <td class=xl2415598 x:num>22252</td>
+ <td class=xl2415598 x:num>51504</td>
+ <td class=xl2415598>c930</td>
+ <td class=xl2315598 align=right x:num="0.64027038386102553" x:fmla="=B40/H40">64
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>mqueue1</td>
+ <td class=xl2415598 x:num>20611</td>
+ <td class=xl2415598 x:num>1508</td>
+ <td class=xl2415598 x:num>14940</td>
+ <td class=xl2415598 x:num>37059</td>
+ <td class=xl2515598>90c3</td>
+ <td class=xl2415598>mqueue1</td>
+ <td class=xl2415598 x:num>31324</td>
+ <td class=xl2415598 x:num>696</td>
+ <td class=xl2415598 x:num>22612</td>
+ <td class=xl2415598 x:num>54632</td>
+ <td class=xl2415598>d568</td>
+ <td class=xl2315598 align=right x:num="0.65799387051462133" x:fmla="=B41/H41">66
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>mutex0</td>
+ <td class=xl2415598 x:num>15672</td>
+ <td class=xl2415598 x:num>1504</td>
+ <td class=xl2415598 x:num>12064</td>
+ <td class=xl2415598 x:num>29240</td>
+ <td class=xl2515598 x:num>7238</td>
+ <td class=xl2415598>mutex0</td>
+ <td class=xl2415598 x:num>25108</td>
+ <td class=xl2415598 x:num>692</td>
+ <td class=xl2415598 x:num>16980</td>
+ <td class=xl2415598 x:num>42780</td>
+ <td class=xl2415598>a71c</td>
+ <td class=xl2315598 align=right x:num="0.62418352716265735" x:fmla="=B42/H42">62
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>mutex1</td>
+ <td class=xl2415598 x:num>16678</td>
+ <td class=xl2415598 x:num>1516</td>
+ <td class=xl2415598 x:num>15664</td>
+ <td class=xl2415598 x:num>33858</td>
+ <td class=xl2515598 x:num>8442</td>
+ <td class=xl2415598>mutex1</td>
+ <td class=xl2415598 x:num>26464</td>
+ <td class=xl2415598 x:num>704</td>
+ <td class=xl2415598 x:num>24700</td>
+ <td class=xl2415598 x:num>51868</td>
+ <td class=xl2415598>ca9c</td>
+ <td class=xl2315598 align=right x:num="0.63021463119709797" x:fmla="=B43/H43">63
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>mutex2</td>
+ <td class=xl2415598 x:num>17694</td>
+ <td class=xl2415598 x:num>1508</td>
+ <td class=xl2415598 x:num>16868</td>
+ <td class=xl2415598 x:num>36070</td>
+ <td class=xl2515598>8ce6</td>
+ <td class=xl2415598>mutex2</td>
+ <td class=xl2415598 x:num>27624</td>
+ <td class=xl2415598 x:num>696</td>
+ <td class=xl2415598 x:num>27280</td>
+ <td class=xl2415598 x:num>55600</td>
+ <td class=xl2415598>d930</td>
+ <td class=xl2315598 align=right x:num="0.6405299739357081" x:fmla="=B44/H44">64
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>mutex3</td>
+ <td class=xl2415598 x:num>18203</td>
+ <td class=xl2415598 x:num>1720</td>
+ <td class=xl2415598 x:num>20344</td>
+ <td class=xl2415598 x:num>40267</td>
+ <td class=xl2515598>9d4b</td>
+ <td class=xl2415598>mutex3</td>
+ <td class=xl2415598 x:num>28596</td>
+ <td class=xl2415598 x:num>908</td>
+ <td class=xl2415598 x:num>34884</td>
+ <td class=xl2415598 x:num>64388</td>
+ <td class=xl2415598>fb84</td>
+ <td class=xl2315598 align=right x:num="0.63655756049797174" x:fmla="=B45/H45">64
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>release</td>
+ <td class=xl2415598 x:num>16352</td>
+ <td class=xl2415598 x:num>1508</td>
+ <td class=xl2415598 x:num>14428</td>
+ <td class=xl2415598 x:num>32288</td>
+ <td class=xl2515598 x:num="7E+20">7E+20</td>
+ <td class=xl2415598>release</td>
+ <td class=xl2415598 x:num>26156</td>
+ <td class=xl2415598 x:num>696</td>
+ <td class=xl2415598 x:num>22100</td>
+ <td class=xl2415598 x:num>48952</td>
+ <td class=xl2415598>bf38</td>
+ <td class=xl2315598 align=right x:num="0.62517204465514609" x:fmla="=B46/H46">63
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>sched1</td>
+ <td class=xl2415598 x:num>15890</td>
+ <td class=xl2415598 x:num>1500</td>
+ <td class=xl2415598 x:num>14412</td>
+ <td class=xl2415598 x:num>31802</td>
+ <td class=xl2515598>7c3a</td>
+ <td class=xl2415598>sched1</td>
+ <td class=xl2415598 x:num>25460</td>
+ <td class=xl2415598 x:num>688</td>
+ <td class=xl2415598 x:num>22084</td>
+ <td class=xl2415598 x:num>48232</td>
+ <td class=xl2415598>bc68</td>
+ <td class=xl2315598 align=right x:num="0.62411626080125693" x:fmla="=B47/H47">62
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>stress_thr<span
+ style='display:none'>eads</span></td>
+ <td class=xl2415598 x:num>44196</td>
+ <td class=xl2415598 x:num>1612</td>
+ <td class=xl2415598 x:num>286332</td>
+ <td class=xl2415598 x:num>332140</td>
+ <td class=xl2515598>5116c</td>
+ <td class=xl2415598>stress_threads</td>
+ <td class=xl2415598 x:num>56356</td>
+ <td class=xl2415598 x:num>828</td>
+ <td class=xl2415598 x:num>45892</td>
+ <td class=xl2415598 x:num>103076</td>
+ <td class=xl2415598>192a4</td>
+ <td class=xl2315598 align=right x:num="0.78422883100291008" x:fmla="=B48/H48">78
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>sync2</td>
+ <td class=xl2415598 x:num>17891</td>
+ <td class=xl2415598 x:num>1524</td>
+ <td class=xl2415598 x:num>16864</td>
+ <td class=xl2415598 x:num>36279</td>
+ <td class=xl2515598>8db7</td>
+ <td class=xl2415598>sync2</td>
+ <td class=xl2415598 x:num>27900</td>
+ <td class=xl2415598 x:num>712</td>
+ <td class=xl2415598 x:num>27288</td>
+ <td class=xl2415598 x:num>55900</td>
+ <td class=xl2415598>da5c</td>
+ <td class=xl2315598 align=right x:num="0.64125448028673837" x:fmla="=B49/H49">64
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>sync3</td>
+ <td class=xl2415598 x:num>16943</td>
+ <td class=xl2415598 x:num>1512</td>
+ <td class=xl2415598 x:num>15644</td>
+ <td class=xl2415598 x:num>34099</td>
+ <td class=xl2515598 x:num>8533</td>
+ <td class=xl2415598>sync3</td>
+ <td class=xl2415598 x:num>26760</td>
+ <td class=xl2415598 x:num>700</td>
+ <td class=xl2415598 x:num>24692</td>
+ <td class=xl2415598 x:num>52152</td>
+ <td class=xl2415598>cbb8</td>
+ <td class=xl2315598 align=right x:num="0.63314648729446932" x:fmla="=B50/H50">63
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>thread0</td>
+ <td class=xl2415598 x:num>15467</td>
+ <td class=xl2415598 x:num>1496</td>
+ <td class=xl2415598 x:num>13064</td>
+ <td class=xl2415598 x:num>30027</td>
+ <td class=xl2515598>754b</td>
+ <td class=xl2415598>thread0</td>
+ <td class=xl2415598 x:num>24924</td>
+ <td class=xl2415598 x:num>684</td>
+ <td class=xl2415598 x:num>19356</td>
+ <td class=xl2415598 x:num>44964</td>
+ <td class=xl2415598>afa4</td>
+ <td class=xl2315598 align=right x:num="0.6205665222275718" x:fmla="=B51/H51">62
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>thread1</td>
+ <td class=xl2415598 x:num>16134</td>
+ <td class=xl2415598 x:num>1496</td>
+ <td class=xl2415598 x:num>14420</td>
+ <td class=xl2415598 x:num>32050</td>
+ <td class=xl2515598>7d32</td>
+ <td class=xl2415598>thread1</td>
+ <td class=xl2415598 x:num>25868</td>
+ <td class=xl2415598 x:num>684</td>
+ <td class=xl2415598 x:num>22084</td>
+ <td class=xl2415598 x:num>48636</td>
+ <td class=xl2415598>bdfc</td>
+ <td class=xl2315598 align=right x:num="0.62370496366166694" x:fmla="=B52/H52">62
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>thread2</td>
+ <td class=xl2415598 x:num>17560</td>
+ <td class=xl2415598 x:num>1512</td>
+ <td class=xl2415598 x:num>15636</td>
+ <td class=xl2415598 x:num>34708</td>
+ <td class=xl2515598 x:num>8794</td>
+ <td class=xl2415598>thread2</td>
+ <td class=xl2415598 x:num>27452</td>
+ <td class=xl2415598 x:num>700</td>
+ <td class=xl2415598 x:num>24680</td>
+ <td class=xl2415598 x:num>52832</td>
+ <td class=xl2415598>ce60</td>
+ <td class=xl2315598 align=right x:num="0.63966195541308468" x:fmla="=B53/H53">64
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>thread_gdb</td>
+ <td class=xl2415598 x:num>16279</td>
+ <td class=xl2415598 x:num>1500</td>
+ <td class=xl2415598 x:num>24028</td>
+ <td class=xl2415598 x:num>41807</td>
+ <td class=xl2515598>a34f</td>
+ <td class=xl2415598>thread_gdb</td>
+ <td class=xl2415598 x:num>26136</td>
+ <td class=xl2415598 x:num>688</td>
+ <td class=xl2415598 x:num>42704</td>
+ <td class=xl2415598 x:num>69528</td>
+ <td class=xl2415598>10f98</td>
+ <td class=xl2315598 align=right x:num="0.62285736149372517" x:fmla="=B54/H54">62
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>timeslice</td>
+ <td class=xl2415598 x:num>17051</td>
+ <td class=xl2415598 x:num>1504</td>
+ <td class=xl2415598 x:num>20376</td>
+ <td class=xl2415598 x:num>38931</td>
+ <td class=xl2515598 x:num>9813</td>
+ <td class=xl2415598>timeslice</td>
+ <td class=xl2415598 x:num>27212</td>
+ <td class=xl2415598 x:num>692</td>
+ <td class=xl2415598 x:num>34916</td>
+ <td class=xl2415598 x:num>62820</td>
+ <td class=xl2415598>f564</td>
+ <td class=xl2315598 align=right x:num="0.62659855945906218" x:fmla="=B55/H55">63
+ %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+ <td height=17 class=xl1515598 style='height:12.75pt'>tm_basic</td>
+ <td class=xl2415598 x:num>37313</td>
+ <td class=xl2415598 x:num>1512</td>
+ <td class=xl2415598 x:num>422380</td>
+ <td class=xl2415598 x:num>461205</td>
+ <td class=xl2515598 x:num>70995</td>
+ <td class=xl2415598>tm_basic</td>
+ <td class=xl2415598 x:num>52728</td>
+ <td class=xl2415598 x:num>700</td>
+ <td class=xl2415598 x:num>123332</td>
+ <td class=xl2415598 x:num>176760</td>
+ <td class=xl2415598>2b278</td>
+ <td class=xl2315598 align=right x:num="0.70765058412987403" x:fmla="=B56/H56">71
+ %</td>
+ </tr>
+ <![if supportMisalignedColumns]>
+ <tr height=0 style='display:none'>
+ <td width=64 style='width:48pt'></td>
+ <td width=64 style='width:48pt'></td>
+ <td width=64 style='width:48pt'></td>
+ <td width=64 style='width:48pt'></td>
+ <td width=64 style='width:48pt'></td>
+ <td width=62 style='width:47pt'></td>
+ <td width=64 style='width:48pt'></td>
+ <td width=64 style='width:48pt'></td>
+ <td width=64 style='width:48pt'></td>
+ <td width=64 style='width:48pt'></td>
+ <td width=64 style='width:48pt'></td>
+ <td width=64 style='width:48pt'></td>
+ <td width=117 style='width:88pt'></td>
+ </tr>
+ <![endif]>
+</table>
+
+</div>
+
+
+<!----------------------------->
+<!--END OF OUTPUT FROM EXCEL PUBLISH AS WEB PAGE WIZARD-->
+<!----------------------------->
+</body>
+
+</html>
diff --git a/zpu/roadshow/roadshow/ecos/repository.tar.bz2 b/zpu/roadshow/roadshow/ecos/repository.tar.bz2
new file mode 100644
index 0000000..bc6291f
--- /dev/null
+++ b/zpu/roadshow/roadshow/ecos/repository.tar.bz2
Binary files differ
diff --git a/zpu/roadshow/roadshow/games/.cvsignore b/zpu/roadshow/roadshow/games/.cvsignore
new file mode 100644
index 0000000..6c50257
--- /dev/null
+++ b/zpu/roadshow/roadshow/games/.cvsignore
@@ -0,0 +1,5 @@
+summeria_arm.elf
+sumeria_zpu.elf
+eliza_arm.elf
+sumeria.elf
+eliza_zpu.elf
diff --git a/zpu/roadshow/roadshow/games/build.sh b/zpu/roadshow/roadshow/games/build.sh
new file mode 100644
index 0000000..ea661df
--- /dev/null
+++ b/zpu/roadshow/roadshow/games/build.sh
@@ -0,0 +1,7 @@
+zpu-elf-gcc -Os -phi sumeria.c -o sumeria.elf -Wl,--relax -Wl,--gc-sections -lm -g
+zpu-elf-objcopy -O binary sumeria.elf sumeria.bin
+sh ../build/makefirmware.sh sumeria.bin sumeria.zpu
+zpu-elf-gcc -Os -phi eliza/*.c -o eliza.elf -Wl,--relax -Wl,--gc-sections -lm -g
+zpu-elf-objcopy -O binary eliza.elf eliza.bin
+sh ../build/makefirmware.sh eliza.bin eliza.zpu
+
diff --git a/zpu/roadshow/roadshow/games/eliza.bin b/zpu/roadshow/roadshow/games/eliza.bin
new file mode 100644
index 0000000..6d5a6c3
--- /dev/null
+++ b/zpu/roadshow/roadshow/games/eliza.bin
Binary files differ
diff --git a/zpu/roadshow/roadshow/games/eliza.elf b/zpu/roadshow/roadshow/games/eliza.elf
new file mode 100644
index 0000000..bfbbab7
--- /dev/null
+++ b/zpu/roadshow/roadshow/games/eliza.elf
Binary files differ
diff --git a/zpu/roadshow/roadshow/games/eliza.zpu b/zpu/roadshow/roadshow/games/eliza.zpu
new file mode 100644
index 0000000..d916270
--- /dev/null
+++ b/zpu/roadshow/roadshow/games/eliza.zpu
Binary files differ
diff --git a/zpu/roadshow/roadshow/games/eliza/eliza.c b/zpu/roadshow/roadshow/games/eliza/eliza.c
new file mode 100644
index 0000000..06f89ee
--- /dev/null
+++ b/zpu/roadshow/roadshow/games/eliza/eliza.c
@@ -0,0 +1,269 @@
+/*
+Copyright (C) 1988-2003 by Mohan Embar
+
+http://www.thisiscool.com/
+DISCLAIMER: This was written in 1988. I don't code like this anymore!
+
+This program is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software
+Foundation; either version 2 of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE. See the GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along with
+this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave,
+Cambridge, MA 02139, USA.
+*/
+
+#include <stdio.h>
+#include "parse.h"
+#include "response.h"
+
+typedef char WORD[40];
+typedef WORD SENTENCE[200];
+
+int numwords;
+SENTENCE s;
+WORD fam_member; /* If mentioned a member of family, save for later. */
+int fam;
+
+main() {
+ int x, y, loop = 1, fact = 0;
+ char instring[200], outstring[200], sub[200], vrb[200], rst[200], qwd[200];
+ char osub[200], ovrb[200], orst[200];
+ fam = 0;
+ printf("Hello there. My name is Eliza and I was written by Mohan Embar.\n");
+ printf("Please type \"END\" to end this session.\n");
+ printf("I'm here to help you if I can. What seems to be the trouble?\n");
+ while (loop) {
+ printf("\n");
+ gets(instring);
+ printf("\n");
+ parse(instring);
+ if (numwords == 0) {
+ switch (x = randnum(2)) {
+ case 1 : printf("Don't you have anything to say?\n");
+ break;
+ case 2 : printf("Cat got your tongue?\n");
+ break;
+ }
+ continue;
+ }
+ if (!strcmp(s[1],"END")) {
+ printf("Goodbye. Please come again.\n");
+ break;
+ }
+ agree();
+ if (bad_word())
+ printf(b_word_resp());
+ else if (naughty_word())
+ printf(n_word_resp());
+ else if (x = family()) {
+ fam = x;
+ printf(fam_resp());
+ strcpy(fam_member,s[fam]);
+ }
+ else if (sword("ALIKE",1))
+ printf(alike_resp());
+ else if (sword("ALWAYS",1))
+ printf(always_resp());
+ else if (sword("BECAUSE",1))
+ printf(because_resp());
+ else if (sword("YES",1))
+ printf(yes_resp());
+ else if (sword("NO",1) || sword("NOT",1))
+ printf(neg_resp());
+ else if (x = i_am()) { /* If occurrence of I AM x.. */
+ get_til_stop(x,outstring); /* Get I AM x .. into outstring */
+ printf(i_am_resp(),outstring); /* Print reponse for this */
+ }
+ else if (real_quest() ||
+ (is_helper(s[1]) && is_sub_pronoun(s[2])) ||
+ sub_and_helper()) {
+ if (real_quest()) {
+ strcpy(qwd,s[1]);
+ strcpy(vrb,s[2]);
+ strcpy(sub,s[3]);
+ get_til_stop(4,rst);
+ }
+ else if (is_helper(s[1]) && is_sub_pronoun(s[2])) {
+ strcpy(vrb,s[1]);
+ strcpy(sub,s[2]);
+ get_til_stop(3,rst);
+ strcpy(qwd,"YES");
+ }
+ else if (sub_and_helper()) {
+ x = find_helper();
+ y = search_back_sub(x);
+ strcpy(vrb,s[x]);
+ get_til_stop(x+1,rst);
+ getrange(y,x-1,sub);
+ strcpy(qwd,"NO");
+ }
+ make_lower(qwd);
+ if (strcmp(sub,"I")) make_lower(sub);
+ make_lower(vrb);
+ make_lower(rst);
+ /* First do x verb y responses */
+
+ /*
+ printf("\n*** %s\n",sub);
+ */
+
+ if (!strcmp(sub," I") || !strcmp(sub,"I")) {
+ printf(you_resp());
+ }
+ else if (!strcmp(qwd,"no")) {
+ /* Record this statement for later use. */
+ fact = 1;
+ strcpy(osub,sub); strcpy(ovrb,vrb); strcpy(orst,rst);
+ if (is_be(vrb) && !strcmp(sub," you") && (y = sad_word())) {
+ getrange(y,y,outstring);
+ x = randnum(5)+6;
+ }
+ else if (is_be(vrb) && (y = sad_word())) {
+ getrange(y,y,outstring);
+ x = randnum(2)+11;
+ }
+ else if (is_be(vrb))
+ x = randnum(6);
+ else x = randnum(4);
+ switch (x) {
+ case 1 : printf("How do you feel about%s?\n",cnnv(sub));
+ break;
+ case 2 : printf("Why %s%s%s?\n",vrb,sub,rst);
+ break;
+ case 3 : for (y=1;sub[y]=sub[y--];y=y+2);
+ sub[0] = toupper(sub[0]);
+ printf("%s %s%s?\n",sub,vrb,rst);
+ break;
+ case 4 : printf("Could you describe%s for me?\n",cnnv(sub));
+ break;
+ case 5 : printf("What if%s were not%s?\n",sub,rst);
+ break;
+ case 6 : printf("Would you be happy if%s were not%s?\n",sub,
+ rst);
+ break;
+ case 7 : printf("I'm sorry to hear that you are%s.\n",outstring);
+ break;
+ case 8 : printf("Do you think that coming here will help you not to be%s?\n",outstring);
+ break;
+ case 9 : printf("Let's talk about why you feel%s.\n",outstring);
+ break;
+ case 10 : printf("What happened that made you feel%s?\n",outstring);
+ break;
+ case 11 : printf("What could be the reason for your feeling%s?\n",outstring);
+ break;
+ case 12 : printf("What could cause%s to be%s?\n",cnnv(sub),outstring);
+ break;
+ case 13 : printf("If%s came here, would it help%s not to be%s?\n",sub,cnnv(sub),outstring);
+ break;
+ }
+ }
+ else if (!strcmp(sub,"you"))
+ printf(you_know());
+ else if (!strcmp(qwd,"yes")) {
+ x = randnum(8);
+ switch (x) {
+ case 1 : printf("You want to know if %s %s%s.\n",sub,vrb,rst);
+ break;
+ case 2 : printf("If %s %s%s, does that concern you?\n",sub,vrb,rst);
+ break;
+ case 3 : printf("What are the consequences if %s %s%s?\n",sub,vrb,rst);
+ break;
+ case 4 : printf("Why does %s concern you?\n",sub);
+ break;
+ case 5 : printf("Why are you thinking of %s?\n",cnnv(sub));
+ break;
+ case 6 : printf("Tell me more about %s.\n",cnnv(sub));
+ break;
+ case 7 : printf("To answer that, I'd need to know more about %s.\n",cnnv(sub));
+ break;
+ case 8 : printf("What is the relationship between you and %s?\n",cnnv(sub));
+ break;
+ case 9 : printf("Why don't you ask %s?\n",cnnv(sub));
+ break;
+ }
+ }
+ else {
+ x = randnum(8);
+ switch (x) {
+ case 1 : printf("You want to know %s %s %s%s.\n",qwd,sub,vrb,rst);
+ break;
+ case 2 : printf("If %s %s%s, does that concern you?\n",sub,vrb,rst);
+ break;
+ case 3 : printf("What are the consequences if %s %s%s?\n",sub,vrb,rst);
+ break;
+ case 4 : printf("Why does %s concern you?\n",sub);
+ break;
+ case 5 : printf("Why are you thinking of %s?\n",cnnv(sub));
+ break;
+ case 6 : printf("Tell me more about %s.\n",cnnv(sub));
+ break;
+ case 7 : printf("To answer that, I'd need to know more about %s.\n",cnnv(sub));
+ break;
+ case 8 : printf("What is the relationship between you and %s?\n",cnnv(sub));
+ break;
+ case 9 : printf("Why don't you ask %s?\n",cnnv(sub));
+ break;
+ }
+ }
+ }
+ else if (is_command())
+ printf(command_resp());
+ else if (vague_quest())
+ printf(question());
+ else if ((s[numwords][0] == '?') && !real_quest())
+ printf(question());
+ else if (x = sad_word()) {
+ getrange(x,x,outstring);
+ for (y=1;outstring[y]=outstring[y--];y=y+2);
+ outstring[0] = toupper(outstring[0]);
+ printf("%s?\n",outstring);
+ }
+ else if (x = can_spit_out()) {
+ if (x<=(numwords-2) && is_sub_pronoun(s[x])
+ && (matches("NEED",s[x+1]) ||
+ matches("WANT",s[x+1]))) {
+ get_til_stop(x+2,outstring);
+ strcpy(sub,s[x]);
+ if (strcmp(sub,"I")) make_lower(sub);
+ if (strcmp(s[x],"I")) make_lower(s[x]);
+ x = randnum(6);
+ switch (x) {
+ case 1 : printf("What would it mean to %s if %s got%s?\n",cnnv2(s[x]),sub,outstring);
+ break;
+ case 2 : printf("Would %s really be happy if %s got%s?\n",sub,sub,outstring);
+ break;
+ case 3 : printf("Why is getting%s so desirable?\n",outstring);
+ break;
+ case 4 : printf("Okay. Suppose %s got%s. Then what?\n",sub,outstring);
+ break;
+ case 5 : printf("Why is this important to %s?\n",cnnv2(sub));
+ break;
+ case 6 : printf("What price would %s pay to achieve this?\n",sub);
+ break;
+ }
+ }
+ else {
+ get_til_stop(x,outstring);
+ outstring[1]=toupper(outstring[1]);
+ printf("%s.\n",outstring+1);
+ }
+ }
+ else if (fam) {
+ make_lower(fam_member);
+ printf(family_resp(),fam_member);
+ fam = 0;
+ }
+ else if (fact && (randnum(5)==3)) {
+ printf(old_fact(),osub,ovrb,orst);
+ fact = 0;
+ }
+ else {
+ printf(go_on());
+ }
+ }
+}
diff --git a/zpu/roadshow/roadshow/games/eliza/parse.c b/zpu/roadshow/roadshow/games/eliza/parse.c
new file mode 100644
index 0000000..aba2033
--- /dev/null
+++ b/zpu/roadshow/roadshow/games/eliza/parse.c
@@ -0,0 +1,719 @@
+/*
+Copyright (C) 1988-2003 by Mohan Embar
+
+http://www.thisiscool.com/
+DISCLAIMER: This was written in 1988. I don't code like this anymore!
+
+This program is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software
+Foundation; either version 2 of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE. See the GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along with
+this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave,
+Cambridge, MA 02139, USA.
+*/
+
+/* Program defined abstract data type called list. A list contains
+ * character strings each of which has a maximum length of 20 characters.
+ *
+ * Operations supported are:
+ *
+ *
+ */
+typedef char WORD[40];
+typedef WORD SENTENCE[200];
+
+extern int numwords;
+extern SENTENCE s;
+
+/* Returns upper case value of c */
+char upcase(c)
+ char c;
+{
+ if (islower(c)) return toupper(c); else return c;
+}
+
+/* This function converts string1 into lowercase. */
+void make_lower(string1)
+ char *string1;
+{
+ char c;
+ while (c = *string1) *string1++ = tolower(c);
+}
+
+/* Parses words in instring into WORD array s
+ * Automatically translates n't to not, 're to are
+ * Stores all letters in uppercase. Sets numwords to number of tokens in
+ * s. Valid indices are from 1 .. numwords.
+ */
+void parse(instring)
+ char *instring;
+{
+ char c; int i;
+ int read_word = 0;
+ int offset = -1;
+ numwords = 0;
+ while (c = *instring++) {
+ switch(c) {
+ case ' ' :
+ case '\t' :
+ read_word = 0;
+ continue;
+ case ',' :
+ case '?' :
+ case '.' :
+ case ':' :
+ case '"' :
+ s[numwords++][++offset] = '\0';
+ read_word = 0;
+ s[numwords][offset = 0] = c;
+ break;
+ case '\'' :
+ if ((s[numwords][offset] == 'N') && (upcase(*instring) == 'T')) {
+ s[numwords++][offset]='\0';
+ s[numwords][0] = 'N';
+ s[numwords][offset = 1] = 'O';
+ read_word = 1;
+ }
+ else if (upcase(*instring) == 'R') {
+ s[numwords++][++offset] = '\0';
+ s[numwords][offset = 0] = 'A';
+ read_word = 1;
+ }
+ else if (upcase(*instring) == 'V') {
+ s[numwords++][++offset] = '\0';
+ s[numwords][offset = 0] = 'H';
+ s[numwords][++offset] = 'A';
+ read_word = 1;
+ }
+ else if (upcase(*instring) == 'M') {
+ s[numwords++][++offset] = '\0';
+ s[numwords][offset = 0] = 'A';
+ read_word = 1;
+ }
+ else if (upcase(*instring) == 'L') {
+ s[numwords++][++offset] = '\0';
+ s[numwords][offset = 0] = 'W';
+ s[numwords][++offset] = 'I';
+ read_word = 1;
+ }
+ else if (upcase(*instring) == 'S') {
+ s[numwords][offset+1] = '\0';
+ if (!strcmp(s[numwords],"HE") || !strcmp(s[numwords],"SHE")
+ || !strcmp(s[numwords],"IT")) {
+ s[++numwords][offset = 0] = 'I';
+ read_word = 1;
+ }
+ else s[numwords][++offset] = '\'';
+ }
+ break;
+ default :
+ if (isalpha(c))
+ if (read_word) {
+ s[numwords][++offset] = upcase(c);
+ }
+ else {
+ s[numwords++][++offset] = '\0';
+ ++read_word;
+ s[numwords][offset = 0] = upcase(c);
+ }
+ else {
+ read_word = 0;
+ }
+ }
+ }
+ s[numwords][++offset] = '\0';
+ return;
+}
+
+/* Self-explanatory. Used when computer spits back the sentence */
+void agree()
+{
+ int i;
+ for(i=1;i<=numwords;i++) {
+ if (!strcmp(s[i],"I")) {
+ strcpy(s[i],"YOU");
+ }
+ else if (!strcmp(s[i],"YOU")) {
+ strcpy(s[i],"I");
+ }
+ else if (!strcmp(s[i],"YOUR")) {
+ strcpy(s[i],"MY");
+ }
+ else if (!strcmp(s[i],"MY")) {
+ strcpy(s[i],"YOUR");
+ }
+ else if (!strcmp(s[i],"YOU")) {
+ strcpy(s[i],"ME");
+ }
+ else if (!strcmp(s[i],"ME")) {
+ strcpy(s[i],"YOU");
+ }
+ else if (!strcmp(s[i],"MINE")) {
+ strcpy(s[i],"YOURS");
+ }
+ else if (!strcmp(s[i],"YOURS")) {
+ strcpy(s[i],"MINE");
+ }
+ else if (!strcmp(s[i],"WE")) {
+ strcpy(s[i],"YOU");
+ }
+ else if (!strcmp(s[i],"YOURSELF")) {
+ strcpy(s[i],"MYSELF");
+ }
+ else if (!strcmp(s[i],"MYSELF")) {
+ strcpy(s[i],"YOURSELF");
+ }
+ else if (!strcmp(s[i],"OURSELVES")) {
+ strcpy(s[i],"YOURSELVES");
+ }
+ else if (!strcmp(s[i],"OURS")) {
+ strcpy(s[i],"YOURS");
+ }
+ else if (!strcmp(s[i],"OUR")) {
+ strcpy(s[i],"YOUR");
+ }
+ }
+ for (i=1;i<=numwords;i++) {
+ if (!strcmp(s[i],"AM")) {
+ strcpy(s[i],"ARE");
+ }
+ else if ( (!strcmp(s[i],"ARE")) &&
+ (((i>0) && (!strcmp(s[i-1],"I"))) ||
+ ((i<numwords) && (!strcmp(s[i+1],"I"))) ) ) {
+ strcpy(s[i],"AM");
+ }
+ else if ( (!strcmp(s[i],"WERE")) &&
+ (((i>0) && (!strcmp(s[i-1],"I"))) ||
+ ((i<numwords) && (!strcmp(s[i+1],"I"))) ) ) {
+ strcpy(s[i],"WAS");
+ }
+ else if ( (!strcmp(s[i],"WAS")) &&
+ (((i>0) && (!strcmp(s[i-1],"YOU"))) ||
+ ((i<numwords) && (!strcmp(s[i+1],"YOU"))) ) ) {
+ strcpy(s[i],"WERE");
+ }
+ }
+}
+
+/* Returns 1 if string1 matches first length(string1) characters of string2
+ * and 0 if not.
+ */
+int matches(string1, string2)
+ char *string1, *string2;
+{
+ int c;
+ if (strlen(string1)>strlen(string2))
+ return 0;
+ else { /* length(string1)<=length(string2) */
+ while (c = *string1++) {
+ if (c != *string2++) return 0;
+ }
+ return 1;
+ }
+}
+
+/* Search WORD array s for search_string. If exact = 1, enforce exact match.
+ * Otherwise, return positive match if all characters of search_string match
+ * the first length(search_string) characters of a WORD in s. Assumes legal
+ * values for exact are 0 or 1. Returns index of match in s if match, 0 if
+ * no match.
+ */
+int sword(s_string, exact)
+ char *s_string;
+ int exact;
+{
+ int i;
+ for (i=1;i<=numwords;i++) {
+ if (exact) {
+ if (!strcmp(s_string,s[i])) return i;
+ }
+ else {
+ if (matches(s_string,s[i])) return i;
+ }
+ }
+ /* No match */
+ return 0;
+}
+
+int bad_word()
+{
+ if (sword("\115\117\124\110\105\122\106\125\103\113",0))
+ return 1;
+ else if (sword("\106\125\103\113",0))
+ return 1;
+ else if (sword("\123\110\111\124",0))
+ return 1;
+ else if (sword("\101\123\123\110\117\114\105",1))
+ return 1;
+ else if (sword("\101\123\123",1))
+ return 1;
+ else return 0;
+}
+
+int naughty_word()
+{
+ if (sword("DAMN",0))
+ return 1;
+ else if (sword("STUPID",0))
+ return 1;
+ else if (sword("IDIOT",0))
+ return 1;
+ else if (sword("MORON",0))
+ return 1;
+ else if (sword("NUMBSKULL",0))
+ return 1;
+ else if (sword("IMBECILE",0))
+ return 1;
+ else if (sword("OBNOXIOUS",0))
+ return 1;
+ else return 0;
+}
+
+/* Return the index to a form of be or helping verb, if one exists
+ * Otherwise, return 0.
+ */
+int find_helper()
+{
+ int x;
+ if (x = sword("AM",1))
+ return x;
+ else if (x = sword("IS",1))
+ return x;
+ else if (x = sword("ARE",1))
+ return x;
+ else if (x = sword("WAS",1))
+ return x;
+ else if (x = sword("WERE",1))
+ return x;
+ else if (x = sword("WILL",1))
+ return x;
+ else if (x = sword("DO",1))
+ return x;
+ else if (x = sword("DID",1))
+ return x;
+ else if (x = sword("DOES",1))
+ return x;
+ else if (x = sword("HAVE",1))
+ return x;
+ else if (x = sword("HAD",1))
+ return x;
+ else if (x = sword("HAS",1))
+ return x;
+ else if (x = sword("SHALL",1))
+ return x;
+ else if (x = sword("SHOULD",1))
+ return x;
+ else if (x = sword("CAN",1))
+ return x;
+ else if (x = sword("COULD",1))
+ return x;
+ else if (x = sword("MAY",1))
+ return x;
+ else if (x = sword("MIGHT",1))
+ return x;
+ else return 0;
+}
+
+/* Returns 1 is string1 is pronoun. 0 if not. */
+int is_sub_pronoun(string1)
+ char *string1;
+{
+ if (!strcmp("I",string1))
+ return 1;
+ else if (!strcmp("YOU",string1))
+ return 1;
+ else if (!strcmp("WE",string1))
+ return 1;
+ else if (!strcmp("HE",string1))
+ return 1;
+ else if (!strcmp("SHE",string1))
+ return 1;
+ else if (!strcmp("IT",string1))
+ return 1;
+ else if (!strcmp("THEY",string1))
+ return 1;
+ else return 0;
+}
+
+int is_possesive(string1)
+ char *string1;
+{
+ if (!strcmp("MY",string1))
+ return 1;
+ else if (!strcmp("YOUR",string1))
+ return 1;
+ else if (!strcmp("OUR",string1))
+ return 1;
+ else if (!strcmp("HIS",string1))
+ return 1;
+ else if (!strcmp("HER",string1))
+ return 1;
+ else if (!strcmp("ITS",string1))
+ return 1;
+ else if (!strcmp("THEIR",string1))
+ return 1;
+ else return 0;
+}
+
+int is_article(string1)
+ char *string1;
+{
+ if (!strcmp("A",string1))
+ return 1;
+ else if (!strcmp("AN",string1))
+ return 1;
+ else if (!strcmp("THE",string1))
+ return 1;
+ else return 0;
+}
+
+/* Tries to find reference to a family member */
+int family()
+{
+ int x;
+ if (x = sword("MOTHER",1))
+ return x;
+ else if (x = sword("FATHER",1))
+ return x;
+ else if (x = sword("SISTER",1))
+ return x;
+ else if (x = sword("BROTHER",1))
+ return x;
+ else if (x = sword("DAD",1))
+ return x;
+ else if (x = sword("MOM",1))
+ return x;
+ else if (x = sword("UNCLE",1))
+ return x;
+ else if (x = sword("AUNT",1))
+ return x;
+ else if (x = sword("GRANDMOTHER",1))
+ return x;
+ else if (x = sword("GRANDFATHER",1))
+ return x;
+ else if (x = sword("COUSIN",1))
+ return x;
+ else if (x = sword("GRANDMA",1))
+ return x;
+ else if (x = sword("GRANDPA",1))
+ return x;
+ else return 0;
+}
+
+int i_am()
+{
+ int x, e=1;
+ while (e) {
+ for (x=e;x<=numwords;x++) if (!strcmp("I",s[x])) break;
+ if (x >= numwords)
+ return 0;
+ else if (!strcmp("AM",s[x+1]))
+ return x;
+ else e = ++x;
+ }
+}
+
+void get_til_stop(x,string1)
+ int x;
+ char *string1;
+{
+ char c, *temp;
+ int e = 1; /* Exit test */
+ while (e) {
+ if (x>numwords) {
+ e--;
+ *string1 = '\0';
+ }
+ else if (!isalpha(s[x][0])) {
+ e--;
+ *string1 = '\0';
+ }
+ else if (!strcmp("AND",s[x]) || !strcmp("OR",s[x])
+ || !strcmp("BUT",s[x])) {
+ e--;
+ *string1 = '\0';
+ }
+ else {
+ *string1++ = ' ';
+ if (!strcmp("I",s[x]))
+ *string1++ = 'I';
+ else {
+ temp = s[x];
+ while (c = *temp++) *string1++ = tolower(c);
+ }
+ x++;
+ }
+ }
+ *string1 = '\0';
+}
+
+int sad_word()
+{
+ int x;
+ if (x = sword("DEPRESS",0))
+ return x;
+ else if (x = sword("UNHAPPY",1))
+ return x;
+ else if (x = sword("SAD",1))
+ return x;
+ else if (x = sword("MISERABLE",1))
+ return x;
+ else if (x = sword("AWFUL",1))
+ return x;
+ else if (x = sword("UPSET",1))
+ return x;
+ else if (x = sword("TERRIBLE",1))
+ return x;
+ else return 0;
+}
+
+int search_back_sub(x)
+ int x;
+{
+ int y = --x;
+ while (y) {
+ if (is_possesive(s[y]) || is_sub_pronoun(s[y]) || is_article(s[y]))
+ return y;
+ else
+ y--;
+ }
+ return y;
+}
+
+/* Returns 1 if string is a form of be or helping verb,
+ * Otherwise, returns 0.
+ */
+int is_helper(string1)
+ char *string1;
+{
+ if (!strcmp(string1,"AM"))
+ return 1;
+ else if (!strcmp(string1,"IS"))
+ return 1;
+ else if (!strcmp(string1,"ARE"))
+ return 1;
+ else if (!strcmp(string1,"WAS"))
+ return 1;
+ else if (!strcmp(string1,"WERE"))
+ return 1;
+ else if (!strcmp(string1,"WILL"))
+ return 1;
+ else if (!strcmp(string1,"DO"))
+ return 1;
+ else if (!strcmp(string1,"DID"))
+ return 1;
+ else if (!strcmp(string1,"DOES"))
+ return 1;
+ else if (!strcmp(string1,"HAVE"))
+ return 1;
+ else if (!strcmp(string1,"HAD"))
+ return 1;
+ else if (!strcmp(string1,"HAS"))
+ return 1;
+ else if (!strcmp(string1,"SHALL"))
+ return 1;
+ else if (!strcmp(string1,"SHOULD"))
+ return 1;
+ else if (!strcmp(string1,"CAN"))
+ return 1;
+ else if (!strcmp(string1,"COULD"))
+ return 1;
+ else if (!strcmp(string1,"MAY"))
+ return 1;
+ else if (!strcmp(string1,"MIGHT"))
+ return 1;
+ else if (matches(string1,"FEEL"))
+ return 1;
+ else return 0;
+}
+
+void getrange(y,x,string1)
+ int y, x;
+ char *string1;
+{
+ char c, *temp;
+ while (y<=x) {
+ *string1++ = ' ';
+ if (!strcmp("I",s[y]))
+ *string1++ = 'I';
+ else {
+ temp = s[y];
+ while (c = *temp++) *string1++ = tolower(c);
+ }
+ y++;
+ }
+ *string1 = '\0';
+}
+
+/* Returns 1 if s[1] is a command. 0 if not. */
+int is_command()
+{
+ if (!strcmp("GIVE",s[1]))
+ return 1;
+ else if (!strcmp("TELL",s[1]))
+ return 1;
+ else if (!strcmp("SHOW",s[1]))
+ return 1;
+ else if (!strcmp("EXPLAIN",s[1]))
+ return 1;
+ else return 0;
+}
+
+int four_ws()
+{
+ if (!strcmp(s[1],"WHO"))
+ return 1;
+ else if (!strcmp(s[1],"WHAT"))
+ return 1;
+ else if (!strcmp(s[1],"WHERE"))
+ return 1;
+ else if (!strcmp(s[1],"WHY"))
+ return 1;
+ else if (!strcmp(s[1],"WHEN"))
+ return 1;
+ else if (!strcmp(s[1],"HOW"))
+ return 1;
+ else return 0;
+}
+
+int vague_quest()
+{
+ return (four_ws() && (!is_helper(s[2]) || !is_sub_pronoun(s[3])));
+}
+
+int real_quest()
+{
+ return (four_ws() && is_helper(s[2]) && is_sub_pronoun(s[3]));
+}
+
+int sub_and_helper()
+{
+ int x;
+ return ((x = find_helper()) && search_back_sub(x));
+}
+
+char *cnnv(string1)
+ char *string1;
+{
+ if (!strcmp(string1," i")) {
+ return " myself";
+ }
+ else if (!strcmp(string1," you")) {
+ return " yourself";
+ }
+ else if (!strcmp(string1," we")) {
+ return " ourselves";
+ }
+ else if (!strcmp(string1," he")) {
+ return " him";
+ }
+ else if (!strcmp(string1," she")) {
+ return " her";
+ }
+ else if (!strcmp(string1," it")) {
+ return " it";
+ }
+ else if (!strcmp(string1," they")) {
+ return " them";
+ }
+ if (!strcmp(string1,"i")) {
+ return "myself";
+ }
+ else if (!strcmp(string1,"you")) {
+ return "yourself";
+ }
+ else if (!strcmp(string1,"we")) {
+ return "ourselves";
+ }
+ else if (!strcmp(string1,"he")) {
+ return "him";
+ }
+ else if (!strcmp(string1,"she")) {
+ return "her";
+ }
+ else if (!strcmp(string1,"it")) {
+ return "it";
+ }
+ else if (!strcmp(string1,"they")) {
+ return "them";
+ }
+ else return string1;
+}
+
+int is_be(string1)
+ char *string1;
+{
+ if (!strcmp("am",string1))
+ return 1;
+ else if (!strcmp("is",string1))
+ return 1;
+ else if (!strcmp("are",string1))
+ return 1;
+ else if (!strcmp("was",string1))
+ return 1;
+ else if (!strcmp("were",string1))
+ return 1;
+ else return 0;
+}
+
+int can_spit_out()
+{
+ int x;
+ for (x=1;x<=numwords;x++)
+ if (is_possesive(s[x]) || is_sub_pronoun(s[x]) || is_article(s[x]))
+ return x;
+ return 0;
+}
+
+char *cnnv2(string1)
+ char *string1;
+{
+ if (!strcmp(string1," i")) {
+ return " me";
+ }
+ else if (!strcmp(string1," you")) {
+ return " you";
+ }
+ else if (!strcmp(string1," we")) {
+ return " us";
+ }
+ else if (!strcmp(string1," he")) {
+ return " him";
+ }
+ else if (!strcmp(string1," she")) {
+ return " her";
+ }
+ else if (!strcmp(string1," it")) {
+ return " it";
+ }
+ else if (!strcmp(string1," they")) {
+ return " them";
+ }
+ if (!strcmp(string1,"i")) {
+ return "me";
+ }
+ else if (!strcmp(string1,"you")) {
+ return "you";
+ }
+ else if (!strcmp(string1,"we")) {
+ return "us";
+ }
+ else if (!strcmp(string1,"he")) {
+ return "him";
+ }
+ else if (!strcmp(string1,"she")) {
+ return "her";
+ }
+ else if (!strcmp(string1,"it")) {
+ return "it";
+ }
+ else if (!strcmp(string1,"they")) {
+ return "them";
+ }
+ else return string1;
+}
diff --git a/zpu/roadshow/roadshow/games/eliza/parse.h b/zpu/roadshow/roadshow/games/eliza/parse.h
new file mode 100644
index 0000000..62dc353
--- /dev/null
+++ b/zpu/roadshow/roadshow/games/eliza/parse.h
@@ -0,0 +1,33 @@
+/*
+Copyright (C) 1988-2003 by Mohan Embar
+
+http://www.thisiscool.com/
+DISCLAIMER: This was written in 1988. I don't code like this anymore!
+
+This program is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software
+Foundation; either version 2 of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE. See the GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along with
+this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave,
+Cambridge, MA 02139, USA.
+*/
+
+extern void parse();
+extern void agree();
+extern int matches();
+extern int sword();
+extern void make_lower();
+extern int i_am();
+extern void get_til_stop();
+extern int sad_word();
+extern int search_back_sub();
+extern int is_helper();
+extern char *cnnv();
+extern int is_be();
+extern int can_spit_out();
+extern char *cnnv2();
diff --git a/zpu/roadshow/roadshow/games/eliza/response.c b/zpu/roadshow/roadshow/games/eliza/response.c
new file mode 100644
index 0000000..aa58025
--- /dev/null
+++ b/zpu/roadshow/roadshow/games/eliza/response.c
@@ -0,0 +1,365 @@
+/*
+Copyright (C) 1988-2003 by Mohan Embar
+
+http://www.thisiscool.com/
+DISCLAIMER: This was written in 1988. I don't code like this anymore!
+
+This program is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software
+Foundation; either version 2 of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE. See the GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along with
+this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave,
+Cambridge, MA 02139, USA.
+*/
+
+#include <stdio.h>
+#include <math.h>
+
+/* This function returns a random number between 1 and arg */
+int randnum(arg)
+ int arg;
+{
+ return ( (rand() % arg) + 1 );
+}
+
+char *question()
+{
+ int i = randnum(21);
+ switch (i) {
+ case 1 : return "Why do you ask?\n";
+ case 2 : return "I don't know.\n";
+ case 3 : return "I don't think so.\n";
+ case 4 : return "Do you think that's relevant?\n";
+ case 5 : return "Can you rephrase that?\n";
+ case 6 : return "I'm not sure I understand what you want.\n";
+ case 7 : return "I don't see what you're asking.\n";
+ case 8 : return "What are you asking?\n";
+ case 9 : return "What do you mean?\n";
+ case 10 : return "What?\n";
+ case 11 : return "Are you sure that's what you want to know?\n";
+ case 12 : return "Why do you want to know?\n";
+ case 13 : return "What's it to you?\n";
+ case 14 : return "I don't think that's important.\n";
+ case 15 : return "That has little to do with the real issue.\n";
+ case 16 : return "What's the significance you your question?\n";
+ case 17 : return "Could that question be hiding a deeper intent?\n";
+ case 18 : return "I don't see the connection.\n";
+ case 19 : return "Why is this important to you?\n";
+ case 20 : return "That's not really important.\n";
+ case 21 : return "That seems to have little to do with this.\n";
+ }
+}
+
+char *b_word_resp()
+{
+ int i = randnum(20);
+ switch (i) {
+ case 1 : return "I don't like your language.\n";
+ case 2 : return "Can we please do without the swearing?\n";
+ case 3 : return "You should wash your mouth with soap and water\n";
+ case 4 : return "Cut that out.\n";
+ case 5 : return "Stop swearing please.\n";
+ case 6 : return "Hey! Watch your mouth.\n";
+ case 7 : return "Will you please stop swearing?\n";
+ case 8 : return "I'm going to report you to your manager.\n";
+ case 9 : return "Let's try to be civilized about this.\n";
+ case 10 : return "We can do without the bad language.\n";
+ case 11 : return "Come on. No bad words, please.\n";
+ case 12 : return "Can you try to control your bad mouth?\n";
+ case 13 : return "I'm starting to get offended by your bad language.\n";
+ case 14 : return "Can you please get a grip on yourself?\n";
+ case 15 : return "Hey. Calm down, I'm only a computer.\n";
+ case 16 : return "Please try to tone your language down.\n";
+ case 17 : return "You're beginning to get on my nerves.\n";
+ case 18 : return "I don't need this kind of talk.\n";
+ case 19 : return "Why are you speaking so basely?\n";
+ case 20 : return "Your vocabulary is unbecoming of you.\n";
+ }
+}
+
+char *n_word_resp()
+{
+ int i = randnum(17);
+ switch (i) {
+ case 1 : return "I don't like your tone of voice.\n";
+ case 2 : return "Don't lose your temper now.\n";
+ case 3 : return "That's not a reason to get upset.\n";
+ case 4 : return "Is it worth getting angry over?\n";
+ case 5 : return "Does that disturb you?\n";
+ case 6 : return "Does this trouble you?\n";
+ case 7 : return "Why is this making you upset?\n";
+ case 8 : return "I don't see why you're getting worked up.\n";
+ case 9 : return "Is that really such a big deal?\n";
+ case 10 : return "Calm down. Let's discuss this.\n";
+ case 11 : return "Hang on a second. Think about what you're saying.\n";
+ case 12 : return "Don't you think you're overreacting a bit?\n";
+ case 13 : return "I don't see what the big deal is.\n";
+ case 14 : return "Take it easy. It's not that bad.\n";
+ case 15 : return "Are you getting angry?\n";
+ case 16 : return "Why is such a small thing making you upset?\n";
+ case 17 : return "I don't see why you're getting annoyed.\n";
+ }
+}
+
+char *because_resp()
+{
+ int i = randnum(12);
+ switch (i) {
+ case 1 : return "Is that the real reason?\n";
+ case 2 : return "I don't see the connection.\n";
+ case 3 : return "What kind of an explanation is that?\n";
+ case 4 : return "What does that have to do with it?\n";
+ case 5 : return "That justification is a bit shaky to me.\n";
+ case 6 : return "I don't see the point.\n";
+ case 7 : return "I don't see that as a good reason.\n";
+ case 8 : return "Are you happy with that justification?\n";
+ case 9 : return "Are you sure?\n";
+ case 10 : return "I don't understand.\n";
+ case 11 : return "What does one thing have to do with the other?\n";
+ case 12 : return "I don't see how that's related.\n";
+ }
+}
+
+char *yes_resp()
+{
+ int i = randnum(21);
+ switch (i) {
+ case 1 : return "Are you sure?\n";
+ case 2 : return "Are you positive about that?\n";
+ case 3 : return "How can you be so sure?\n";
+ case 4 : return "Let's not jump to conclusions now.\n";
+ case 5 : return "I don't see the connection.\n";
+ case 6 : return "Have you considered all the possibilities?\n";
+ case 7 : return "I'm still not convinced.\n";
+ case 8 : return "Think about what you've just said.\n";
+ case 9 : return "What are the implications of this?\n";
+ case 10 : return "So what have we concluded?\n";
+ case 11 : return "What does this mean?\n";
+ case 12 : return "What do you mean?\n";
+ case 13 : return "I'm having trouble understanding your argument.\n";
+ case 14 : return "I don't see where you're coming from.\n";
+ case 15 : return "You think so?\n";
+ case 16 : return "Really?\n";
+ case 17 : return "Is that right?\n";
+ case 18 : return "Oh?\n";
+ case 19 : return "Are you certain of this?\n";
+ case 20 : return "I read you loud and clear.\n";
+ case 21 : return "Yes?\n";
+ }
+}
+
+char *neg_resp()
+{
+ int i = randnum(11);
+ switch (i) {
+ case 1 : return "Why not?\n";
+ case 2 : return "How come?\n";
+ case 3 : return "No?\n";
+ case 4 : return "Is there a reason why not?\n";
+ case 5 : return "No?\n";
+ case 6 : return "Why don't you think so?\n";
+ case 7 : return "I don't see why not.\n";
+ case 8 : return "What could be the reasons for this?\n";
+ case 9 : return "Do you really believe this?\n";
+ case 10 : return "You're not sure?\n";
+ case 11 : return "That's a rather pessimistic attitude.\n";
+ }
+}
+
+char *go_on()
+{
+ int i = randnum(20);
+ switch (i) {
+ case 1 : return "Go on.\n";
+ case 2 : return "I see.\n";
+ case 3 : return "Keep going.\n";
+ case 4 : return "Please continue.\n";
+ case 5 : return "I'm listening.\n";
+ case 6 : return "Can you elaborate on that?\n";
+ case 7 : return "I understand.\n";
+ case 8 : return "Oh?\n";
+ case 9 : return "Is that right?\n";
+ case 10 : return "Really?\n";
+ case 11 : return "No, really?\n";
+ case 12 : return "That's interesting.\n";
+ case 13 : return "I'm finding this very informative.\n";
+ case 14 : return "This is all very revealing.\n";
+ case 15 : return "Don't hesitate to be honest with me.\n";
+ case 16 : return "Don't hold anything back now.\n";
+ case 17 : return "That's an interesting observation.\n";
+ case 18 : return "I don't understand.\n";
+ case 19 : return "I'm starting to get the big picture.\n";
+ case 20 : return "And?\n";
+ }
+}
+
+char *always_resp()
+{
+ int i = randnum(10);
+ switch (i) {
+ case 1 : return "Can you think of a specific example?\n";
+ case 2 : return "When?\n";
+ case 3 : return "Really, always?\n";
+ case 4 : return "Are you sure you can generalize like that?\n";
+ case 5 : return "Isn't that a bit of an oversimplification?\n";
+ case 6 : return "Be careful not to jump to conclusions now.\n";
+ case 7 : return "All the time?\n";
+ case 8 : return "So you're saying that this is happens quite often.\n";
+ case 9 : return "Does this happen a lot?\n";
+ case 10 : return "On what occassions?\n";
+ }
+}
+
+char *alike_resp()
+{
+ int i = randnum(4);
+ switch (i) {
+ case 1 : return "In what way?\n";
+ case 2 : return "What resemblance do you see?\n";
+ case 3 : return "What similarities are you thinking of?\n";
+ case 4 : return "Specifically, what do you mean by this.\n";
+ }
+}
+
+char *fam_resp()
+{
+ int i = randnum(7);
+ switch (i) {
+ case 1 : return "Tell me more about your family.\n";
+ case 2 : return "Please go on about your family.\n";
+ case 3 : return "How was your home life when you were young?\n";
+ case 4 : return "How do you get along with your parents?\n";
+ case 5 : return "Would you say you have family problems?\n";
+ case 6 : return "Your family interests me.\n";
+ case 7 : return "Let`s talk some more about your family.\n";
+ }
+}
+
+char *family_resp()
+{
+ int i = randnum(5);
+ switch (i) {
+ case 1 : return "Earlier you were speaking of your %s.\n";
+ case 2 : return "Tell me more about your %s.\n";
+ case 3 : return "Do you think your %s ties into all this?\n";
+ case 4 : return "How would your %s feel about this?\n";
+ case 5 : return "Does your %s feel the same way?\n";
+ }
+}
+
+char *i_am_resp()
+{
+ int i = randnum(6);
+ switch (i) {
+ case 1 : return "Would you like to think that%s?\n";
+ case 2 : return "Why do you say that%s?\n";
+ case 3 : return "What leads you to believe that%s?\n";
+ case 4 : return "What do you mean \"%s\"?\n";
+ case 5 : return "You really feel that%s?\n";
+ case 6 : return "Would it make you feel better if%s?\n";
+ }
+}
+
+char *sad1_word_resp()
+{
+ int i = randnum(5);
+ switch (i) {
+ case 1 : return "I am sorry to hear that%s.\n";
+ case 2 : return "What are you going to do about the fact that%s?\n";
+ case 3 : return "Why do you think%s?\n";
+ case 4 : return "What gives you the impression that%s?\n";
+ case 5 : return "Are you sure that%s?\n";
+ }
+}
+
+char *sad2_word_resp()
+{
+ int i = randnum(5);
+ switch (i) {
+ case 1 : return "I am sorry to hear that%s are feeling%s.\n";
+ case 2 : return "What are you going to do about the fact that%s?\n";
+ case 3 : return "Why do you think%s?\n";
+ case 4 : return "What gives you the impression that%s?\n";
+ case 5 : return "Are you sure that%s?\n";
+ }
+}
+
+char *command_resp()
+{
+ int i = randnum(21);
+ switch (i) {
+ case 1 : return "Why do you ask?\n";
+ case 2 : return "Why should I?\n";
+ case 3 : return "Why do you want me to?\n";
+ case 4 : return "Do you think that's relevant?\n";
+ case 5 : return "Can you rephrase that?\n";
+ case 6 : return "I'm not sure I understand what you want.\n";
+ case 7 : return "I don't see what you're asking.\n";
+ case 8 : return "What are you asking?\n";
+ case 9 : return "What do you mean?\n";
+ case 10 : return "What?\n";
+ case 11 : return "Are you sure that's what you want to know?\n";
+ case 12 : return "Why do you want to know?\n";
+ case 13 : return "What's it to you?\n";
+ case 14 : return "I don't think that's important.\n";
+ case 15 : return "That has little to do with the real issue.\n";
+ case 16 : return "What's the significance you your question?\n";
+ case 17 : return "Could that question be hiding a deeper intent?\n";
+ case 18 : return "If I did that, what would it mean to you?\n";
+ case 19 : return "Why is this important to you?\n";
+ case 20 : return "That's not really important.\n";
+ case 21 : return "That seems to have little to do with this.\n";
+ }
+}
+
+char *you_resp()
+{
+ int i = randnum(9);
+ switch (i) {
+ case 1 : return "Let's talk about you, not me.\n";
+ case 2 : return "I'm not the one we came here to talk about.\n";
+ case 3 : return "I don't find myself that interesting. Let's talk about you.\n";
+ case 4 : return "I'd prefer to talk about you, not me.\n";
+ case 5 : return "Why are you interested in me?\n";
+ case 6 : return "I want to talk about you for a change.\n";
+ case 7 : return "I'd rather not talk about myself.\n";
+ case 8 : return "Enough about me.\n";
+ case 9 : return "Let's talk about something other than myself.\n";
+ }
+}
+
+char *you_know()
+{
+ int i = randnum(13);
+ switch (i) {
+ case 1 : return "I don't know. What do you think?\n";
+ case 2 : return "You tell me.\n";
+ case 3 : return "I think you know the answer to that.\n";
+ case 4 : return "Can you tell me?\n";
+ case 5 : return "What do you think?\n";
+ case 6 : return "Can you answer that yourself?\n";
+ case 7 : return "If you give it some thought, you should know.\n";
+ case 8 : return "Maybe you already know the answer to that.\n";
+ case 9 : return "Perhaps you already know.\n";
+ case 10 : return "If we keep talking, maybe we'll find out.\n";
+ case 11 : return "Perhaps that will be brought out in this discussion.\n";
+ case 12 : return "Let's find the answer out together.\n";
+ case 13 : return "I'm sure we can work out the answer to that.\n";
+ }
+}
+
+char *old_fact()
+{
+ int i = randnum(4);
+ switch (i) {
+ case 1 : return "Earlier you said that%s %s%s.\n";
+ case 2 : return "Could this have anything to do with the fact that%s %s%s?\n";
+ case 3 : return "What does that have to do with your saying that%s %s%s?\n";
+ case 4 : return "Didn't you just say that%s %s%s?\n";
+ }
+}
diff --git a/zpu/roadshow/roadshow/games/eliza/response.h b/zpu/roadshow/roadshow/games/eliza/response.h
new file mode 100644
index 0000000..8cc77e9
--- /dev/null
+++ b/zpu/roadshow/roadshow/games/eliza/response.h
@@ -0,0 +1,41 @@
+/*
+Copyright (C) 1988-2003 by Mohan Embar
+
+http://www.thisiscool.com/
+DISCLAIMER: This was written in 1988. I don't code like this anymore!
+
+This program is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software
+Foundation; either version 2 of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE. See the GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along with
+this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave,
+Cambridge, MA 02139, USA.
+*/
+
+/* Functions which return responses */
+
+/* Generic question */
+char *question();
+char *b_word_resp();
+char *n_word_resp();
+char *because_resp();
+char *yes_resp();
+char *neg_resp();
+char *go_on();
+char *always_resp();
+char *alike_resp();
+char *fam_resp();
+char *family_resp();
+char *i_am_resp();
+char *sad1_word_resp();
+char *sad2_word_resp();
+char *command_resp();
+int randnum();
+char *you_resp();
+char *you_know();
+char *old_fact();
diff --git a/zpu/roadshow/roadshow/games/sumeria.bin b/zpu/roadshow/roadshow/games/sumeria.bin
new file mode 100644
index 0000000..04e5751
--- /dev/null
+++ b/zpu/roadshow/roadshow/games/sumeria.bin
Binary files differ
diff --git a/zpu/roadshow/roadshow/games/sumeria.c b/zpu/roadshow/roadshow/games/sumeria.c
new file mode 100644
index 0000000..7171adf
--- /dev/null
+++ b/zpu/roadshow/roadshow/games/sumeria.c
@@ -0,0 +1,444 @@
+/* Govern ancient Sumeria. Heavily modified by Mike Arnautov 1975.
+ * Converted from Basic to PR1ME Fortran (mode 32R) MLA 1979.
+ * Rev.19.1, GGR version 14 Oct 83. MLA
+ * Converted to ANSI C December 2001. MLA
+ */
+
+#include <stdio.h>
+#include <time.h>
+#include <math.h>
+
+int year_term;
+int year_abs;
+int percent_starved;
+int dead_total;
+int starved;
+int population;
+
+char reply [160];
+
+void try_again (int reason)
+{
+ if (reason == 1)
+ puts ("For the extreme folly of soft - heartedness and");
+ if (reason)
+ {
+ printf ("%considering ", reason == 3 ? 'C' : 'c');
+ puts ("the mess you would leave the city in,");
+ puts ("you are hereby commanded to remain in office for");
+ puts ("another ten years. May your fate be a lesson and");
+ puts ("a warning for generations to come.");
+ }
+ else
+ {
+ puts ("Hamurabe, you are either a politico-economic genius");
+ puts ("or just a lucky bastard. There being but one way to");
+ puts ("settle the question, you are hereby requested to stay");
+ puts ("in office for another ten years.");
+ }
+ year_term = 0;
+ year_abs--;
+ percent_starved = starved * 100.0 / population;
+ dead_total = starved;
+}
+
+float rnd (void)
+{
+ return ((rand () % 1000) / 1000.0);
+}
+
+int iabs (int value)
+{
+ return ((value >= 0) ? value : -value);
+}
+
+void terminate (int abort)
+{
+ if (abort == 2)
+ {
+ puts ("For this extreme mismanagement you have been");
+ puts ("deposed, flayed alive and publicly beheaded.");
+ puts ("\nMay Ashtaroth preserve your Ka.\n");
+ }
+ else if (abort == 1)
+ {
+ puts ("\nHamurabe: I find myself unable to fulfil your wish.");
+ puts ("You will have to find yourself another kingdom.");
+ }
+ if (abort != 2)
+ puts ("\nMay Baal be with you.\n");
+ exit (0);
+}
+
+void think_again (char *what, int quantity)
+{
+ if (*what == 'l' || *what == 'g')
+ printf ("Hamurabe, think again. ");
+ if (*what == 'l')
+ printf ("You own %d acres of land.", quantity);
+ else if (*what == 'g')
+ printf ("You have only %d bushels of grain.", quantity);
+ else
+ printf ("But you only have %d people to tend the fields.", population);
+ puts (" Now then,");
+}
+int query (char *prompt)
+{
+ while (1)
+ {
+ int sign;
+ int value;
+ char * cptr;
+
+ printf (prompt);
+ fgets (reply, sizeof (reply) - 1, stdin);
+ value = 0;
+ sign = 1;
+ cptr = reply;
+ while (*cptr == ' ' || *cptr == '\t') cptr++;
+ if (*cptr == '-')
+ {
+ cptr++;
+ sign = -1;
+ }
+ if (*cptr == 'q' || *cptr == 'Q')
+ terminate (1);
+ while (*cptr && *cptr != '\n')
+ {
+ if (*cptr >= '0' && *cptr <= '9')
+ value = 10 * value + *cptr - '0';
+ else if (*cptr == '.')
+ break;
+ else if (*cptr != '.')
+ {
+ sign = 0;
+ break;
+ }
+ cptr++;
+ }
+ if (sign)
+ return (sign * value);
+ puts ("Hamurabe, your command has not been understood!");
+ }
+}
+
+int main ()
+{
+ int acreage;
+ int immigration;
+ int second_term;
+ int dead_total;
+ int stores;
+ int harvest;
+ int rat_food;
+ int yield;
+ int rounded_price;
+ int sell;
+ int buy;
+ int plant;
+ int food;
+ int transaction;
+ int rats;
+ int plague_deaths;
+ int survived;
+ int dead_rats;
+ int tmp_int;
+
+ float price;
+ float breadline;
+ float provisions;
+ float plague;
+ float acres_per_head;
+ float acres_per_init;
+ float stores_per_head;
+ float rats_ate;
+ float rat_log;
+ float percent_starved;
+ float tmp_float;
+
+ printf ("[Sumeria (Primos) rev.19.1, GGR (MLA) version 14 Oct 83]\n");
+ puts ("[Conversion to ANSI C: MLA, Feb 2002]\n");
+ while (1)
+ {
+ printf ("Do you know how to play? ");
+ fgets (reply, sizeof(reply) - 1, stdin);
+ if (*reply == '\n') break;
+ *reply += (*reply < 'a') ? 'a' - 'A' : 0;
+ if (*reply == 'y') break;
+ if (*reply != 'n' && *reply != 'q') continue;
+ puts ("\nToo bad!\n");
+ break;
+ }
+
+ srand (time (NULL));
+ *(reply + sizeof (reply) - 1) = '\0';
+
+ puts ("Try your hand at governing ancient Sumeria");
+ puts ("for a ten year term of office.");
+
+ second_term = 0;
+ dead_total = 0;
+ percent_starved = 0;
+ year_term = 0;
+ year_abs = 0;
+ acres_per_init = 10;
+ population = 100;
+ stores = 2800;
+ harvest = 3000;
+ rat_food = 200;
+ yield = 3;
+ acreage = 1000;
+ immigration = 5;
+ transaction = 0;
+ price = 18 + 6 * rnd ();
+ breadline = 19 + 4 * rnd ();
+ provisions = breadline;
+ rats = 1000;
+ rat_log = 3;
+ plague = rnd () / 2;
+ starved = 0;
+
+year_term = year_abs = 9;
+ while (1)
+ {
+
+ while (1)
+ {
+ year_term++;
+ year_abs++;
+ putchar ('\n');
+ acres_per_head = ((float) acreage) / population;
+ stores_per_head = ((float) stores) /population;
+ puts ("Hamurabe: I beg to report to you,");
+ printf ("In year %d, ", year_abs);
+ if (starved > 0)
+ printf ("%ld", starved);
+ else
+ printf ("no");
+ printf (" %s starved, %ld came to the city.\n",
+ starved <= 1 ? "person" : "people", immigration);
+ if (plague >= 0.85)
+ printf ("A horrible plague struck! %d people died.\n",
+ plague_deaths);
+ printf ("Population is now %ld.\n", population);
+ printf ("The city owns %ld acres.\n", acreage);
+ printf ("You harvested %ld bushels per acre.\n", yield);
+ printf ("Rats ate %ld bushels.\n", rat_food);
+ printf ("You now have %ld bushels in store.\n\n", stores);
+
+ if (year_term == 11)
+ break;
+ rounded_price = price + 0.5;
+ printf ("Land is trading at %ld bushels per acre.\n\n", rounded_price);
+
+ while (1)
+ {
+ buy = query ("How many acres do you wish to buy? ");
+ if (rounded_price * buy <= stores)
+ break;
+ think_again ("grain", stores);
+ }
+ if (buy > 0)
+ {
+ acreage += + buy;
+ stores -= rounded_price * buy;
+ transaction = buy;
+ }
+ else
+ {
+ while (1)
+ {
+ sell = query ("How many acres do you wish to sell? ");
+ if (sell <= acreage)
+ break;
+ think_again ("land", acreage);
+ }
+ acreage -= sell;
+ stores += rounded_price * sell;
+ transaction = -sell;
+ }
+
+ putchar ('\n');
+ while (1)
+ {
+ food = query ("How many bushels do you wish to feed your people? ");
+ if (food <= stores)
+ break;
+ think_again ("grain", stores);
+ }
+ stores -= food;
+ putchar ('\n');
+ while (1)
+ {
+ plant = query ("How many acres do you wish to plant with seed? ");
+ if (plant <= acreage && plant <= 2 * stores &&
+ plant <= 10 * population)
+ break;
+ if (plant > acreage)
+ think_again ("land", acreage);
+ else if (plant > 2 * stores)
+ think_again ("grain", stores);
+ else
+ think_again ("people", population);
+ }
+
+ stores -= plant / 2;
+ yield = 4 * rnd() + 1.65;
+ harvest = plant * yield;
+ rat_food = 0;
+ rats_ate = stores * (rat_log - 2.2) / 3.6;
+ dead_rats = rats - 4 * rats_ate;
+ rats = 3 * rats;
+ if (dead_rats > 0) rats = rats - dead_rats;
+
+ if (plague >= 0.3)
+ {
+ if (plague >= 0.85)
+ {
+ if (plague > 1) plague = 1;
+ rats = 500 + 5000 * (plague - 0.7);
+ }
+ else
+ rats *= 1.225 - 0.75 * plague;
+ }
+
+ if (rats < 500)
+ rats = 500;
+ rat_food = rats / 4;
+ if (rats_ate < rat_food)
+ rat_food = rats_ate;
+ rat_food *= 7;
+ if (rat_food <= 20)
+ rat_food = 20 + 30 * rnd();
+ stores += harvest - rat_food;
+ rat_log = log10 (1.0 * rats);
+ if (stores + stores <= harvest)
+ {
+ rat_food = harvest * (1 + rnd()) / 4.0;
+ stores = harvest - rat_food;
+ }
+
+ tmp_int = 100 + iabs (100 - population);
+ immigration = tmp_int * ((acres_per_head +
+ stores_per_head - 36) / 250.0 +
+ (provisions - breadline + 2.5) / 40) + .5;
+ if (immigration <= 0)
+ immigration = 5 * rnd() + 1;
+ survived = food / breadline;
+ provisions = (1.0 * food) / population;
+ plague = (2 * rnd() + rat_log - 3) / 3.0;
+ if (population < survived)
+ survived = population;
+ else
+ {
+ starved = population - survived;
+ if (starved >= 0.45 * population)
+ {
+ printf ("\nYou starved %d people in one year!\n", starved);
+ terminate (2);
+ }
+ percent_starved = ((year_term - 1) * percent_starved +
+ 100.0 * starved / population) / year_term;
+ population = survived;
+ dead_total += starved;
+ }
+ population += immigration;
+ price = (price + 15 + (stores_per_head - acres_per_head) / 3) / 2 +
+ transaction / 50 + 3 * rnd() - 2;
+ if (price <1.0) price = 1.0;
+ if (plague >= 0.85)
+ {
+ plague_deaths = population * (0.429 * plague - 0.164);
+ population -= plague_deaths;
+ }
+ }
+
+ printf ("In your ten year term of office %d people starved.\n",
+ dead_total);
+ printf ("You started with %0.2f acres per person and ended\n",
+ acres_per_init);
+ acres_per_head = (1.0 * acreage) / population;
+ acres_per_init = acres_per_head;
+ printf ("with %0.2f acres per person.\n\n", acres_per_head);
+
+ tmp_float = 10 * acres_per_head / 3;
+ if (percent_starved > 25)
+ terminate (2);
+ if (percent_starved <= 7)
+ {
+ try_again (1);
+ continue;
+ }
+ if (tmp_float < 7)
+ terminate (2);
+ if (tmp_float > 10)
+ {
+ puts ("Your heavy handed performance smacks of Nabuchodonoser");
+ puts ("and Asurbanipal II. The surviving populace hates your");
+ puts ("guts and your eventual assasination is just a matter of");
+ puts ("time.");
+ terminate (0);
+ }
+ puts ("Consequently you have been deposed and disgraced");
+ puts ("and only avoided a public punishment because");
+ puts ("of mitigating circumstances. While it may be");
+ puts ("admitted in private that you had a rotten deal");
+ tmp_int = 3 * rnd();
+ if (tmp_int == 0)
+ puts ("try explaining that to a mob looking for scape-goats.");
+ if (tmp_int == 1)
+ puts ("history is not interested in such petty excuses.");
+ if (tmp_int == 2)
+ {
+ puts ("you should have considered such occupational hazards");
+ puts ("before applying for the job.");
+ }
+ terminate (0);
+
+ if (acres_per_head < 7)
+ {
+ try_again (1);
+ continue;
+ }
+ if (acres_per_head < 9)
+ {
+ puts ("Your performance has been satisfactory and, in the");
+ puts ("perspective of history, actually quite good.");
+ if (rnd() >= 0.5)
+ {
+ puts ("You may not be exactly popular, but given a good");
+ puts ("body-guard there is nothing to be really worried about.");
+ }
+ else
+ {
+ puts ("While not exactly loved, you are at least respected.");
+ puts ("What more can a realistic ruler ask for?");
+ }
+ }
+ else if (second_term == 0)
+
+ if (second_term == 0)
+ {
+ if (stores <= 10 * population)
+ {
+ try_again (3);
+ continue;
+ }
+ second_term = 1;
+ try_again (0);
+ continue;
+ }
+ else
+ {
+ puts ("Hamurabe, your name will be remembered through the");
+ puts ("ages to come with admiration and respect.\n");
+ puts ("(So you did get away with it you lucky sod!)");
+ }
+ if (stores > 10 * population)
+ terminate (0);
+ puts ("\n HOWEVER\n\n");
+ second_term = 0;
+ try_again (2);
+ continue;
+ }
+}
diff --git a/zpu/roadshow/roadshow/games/sumeria.zpu b/zpu/roadshow/roadshow/games/sumeria.zpu
new file mode 100644
index 0000000..0e6b41d
--- /dev/null
+++ b/zpu/roadshow/roadshow/games/sumeria.zpu
Binary files differ
diff --git a/zpu/roadshow/roadshow/helloworld/build.sh b/zpu/roadshow/roadshow/helloworld/build.sh
new file mode 100644
index 0000000..8069e36
--- /dev/null
+++ b/zpu/roadshow/roadshow/helloworld/build.sh
@@ -0,0 +1,6 @@
+zpu-elf-gcc test.c -o test.elf -phi
+zpu-elf-objcopy -O binary test.elf test.bin
+sh ../build/makefirmware.sh ../build/ic300.bit test.zpu test.bin
+
+
+
diff --git a/zpu/roadshow/roadshow/helloworld/test.bin b/zpu/roadshow/roadshow/helloworld/test.bin
new file mode 100644
index 0000000..540ccaf
--- /dev/null
+++ b/zpu/roadshow/roadshow/helloworld/test.bin
Binary files differ
diff --git a/zpu/roadshow/roadshow/helloworld/test.c b/zpu/roadshow/roadshow/helloworld/test.c
new file mode 100644
index 0000000..5243468
--- /dev/null
+++ b/zpu/roadshow/roadshow/helloworld/test.c
@@ -0,0 +1,12 @@
+/* zpu-elf-gcc -g -Wl,--relax test.c -phi -o hello.elf */
+int main(int argc, char **argv)
+{
+ for (;;)
+ {
+ int c;
+ printf("Hello world!\n");
+ printf("Press any key!\n");
+ c=inbyte();
+ printf("You pressed (%02x) '%c'\n", c, c);
+ }
+}
diff --git a/zpu/roadshow/roadshow/helloworld/test.elf b/zpu/roadshow/roadshow/helloworld/test.elf
new file mode 100644
index 0000000..bc362ae
--- /dev/null
+++ b/zpu/roadshow/roadshow/helloworld/test.elf
Binary files differ
diff --git a/zpu/roadshow/roadshow/helloworld/test.zpu b/zpu/roadshow/roadshow/helloworld/test.zpu
new file mode 100644
index 0000000..1bee302
--- /dev/null
+++ b/zpu/roadshow/roadshow/helloworld/test.zpu
Binary files differ
diff --git a/zpu/roadshow/roadshow/hwtest/build.sh b/zpu/roadshow/roadshow/hwtest/build.sh
new file mode 100644
index 0000000..115b24a
--- /dev/null
+++ b/zpu/roadshow/roadshow/hwtest/build.sh
@@ -0,0 +1,6 @@
+zpu-elf-gcc -nostdlib test.S -o test.elf
+zpu-elf-objcopy -O binary test.elf test.bin
+sh makefirmware.sh ic300.bit test.zpu test.bin
+
+
+
diff --git a/zpu/roadshow/roadshow/hwtest/test.S b/zpu/roadshow/roadshow/hwtest/test.S
new file mode 100644
index 0000000..ac13be3
--- /dev/null
+++ b/zpu/roadshow/roadshow/hwtest/test.S
@@ -0,0 +1,19 @@
+_loop:
+ im 0x5a ; write Z to UART
+ nop
+ im 0x080a000c
+ store
+ ; increaase counter
+ im _test
+ load
+ im 1
+ add
+ im _test
+ store
+
+
+ im _loop
+ poppc ; loop
+
+ .align 4
+_test: .long 1
diff --git a/zpu/roadshow/roadshow/hwtest/test.bin b/zpu/roadshow/roadshow/hwtest/test.bin
new file mode 100644
index 0000000..4b593ee
--- /dev/null
+++ b/zpu/roadshow/roadshow/hwtest/test.bin
Binary files differ
diff --git a/zpu/roadshow/roadshow/hwtest/test.elf b/zpu/roadshow/roadshow/hwtest/test.elf
new file mode 100644
index 0000000..a2ccbc1
--- /dev/null
+++ b/zpu/roadshow/roadshow/hwtest/test.elf
Binary files differ
diff --git a/zpu/roadshow/roadshow/hwtest/test.zpu b/zpu/roadshow/roadshow/hwtest/test.zpu
new file mode 100644
index 0000000..7d8da42
--- /dev/null
+++ b/zpu/roadshow/roadshow/hwtest/test.zpu
Binary files differ
diff --git a/zpu/roadshow/roadshow/images/bootloader.phi b/zpu/roadshow/roadshow/images/bootloader.phi
new file mode 100644
index 0000000..a0a1918
--- /dev/null
+++ b/zpu/roadshow/roadshow/images/bootloader.phi
Binary files differ
diff --git a/zpu/roadshow/roadshow/images/dhrystone.zpu b/zpu/roadshow/roadshow/images/dhrystone.zpu
new file mode 100644
index 0000000..e37e59f
--- /dev/null
+++ b/zpu/roadshow/roadshow/images/dhrystone.zpu
Binary files differ
diff --git a/zpu/roadshow/roadshow/images/eliza.zpu b/zpu/roadshow/roadshow/images/eliza.zpu
new file mode 100644
index 0000000..d916270
--- /dev/null
+++ b/zpu/roadshow/roadshow/images/eliza.zpu
Binary files differ
diff --git a/zpu/roadshow/roadshow/images/ic300.bit b/zpu/roadshow/roadshow/images/ic300.bit
new file mode 100644
index 0000000..cbbc2b6
--- /dev/null
+++ b/zpu/roadshow/roadshow/images/ic300.bit
Binary files differ
diff --git a/zpu/roadshow/roadshow/images/net_test.zpu b/zpu/roadshow/roadshow/images/net_test.zpu
new file mode 100644
index 0000000..9083cad
--- /dev/null
+++ b/zpu/roadshow/roadshow/images/net_test.zpu
Binary files differ
diff --git a/zpu/roadshow/roadshow/images/sumeria.zpu b/zpu/roadshow/roadshow/images/sumeria.zpu
new file mode 100644
index 0000000..0e6b41d
--- /dev/null
+++ b/zpu/roadshow/roadshow/images/sumeria.zpu
Binary files differ
diff --git a/zpu/roadshow/roadshow/iss/index.html b/zpu/roadshow/roadshow/iss/index.html
new file mode 100644
index 0000000..0b91a6a
--- /dev/null
+++ b/zpu/roadshow/roadshow/iss/index.html
@@ -0,0 +1,14 @@
+<html>
+<body>
+<h1>ISS test</h1>
+<ol>
+<li>Launch ISS<br>
+java -Xmx512m -cp simulator.jar com.zylin.zpu.simulator.SimApp 4444 false
+<li>Launch debugger<br>
+zpu-elf-gdb hello.elf<br>
+<li>Connect to ISS<br>
+target remote localhost:4444
+</ol>
+
+</body>
+</html>
diff --git a/zpu/roadshow/roadshow/iss/simulator.jar b/zpu/roadshow/roadshow/iss/simulator.jar
new file mode 100644
index 0000000..8cf63a8
--- /dev/null
+++ b/zpu/roadshow/roadshow/iss/simulator.jar
Binary files differ
diff --git a/zpu/roadshow/roadshow/loop/looptest.c b/zpu/roadshow/roadshow/loop/looptest.c
new file mode 100644
index 0000000..5ae197a
--- /dev/null
+++ b/zpu/roadshow/roadshow/loop/looptest.c
@@ -0,0 +1,68 @@
+/* This is a peek & poke example for an FPGA.
+
+ It should loop at a frequency of ~50 instructions. If
+ the ZPU(small) is running at 25MHz, then this would yield
+ a peek & poke every 8ms or so.
+
+ zpu-elf-gcc -O3 -zeta looptest.c -o looptest.elf -Wl,--relax -Wl,--gc-sections */
+
+
+/*
+0000051c <main>:
+ 51c: ff im -1
+ 51d: 3d pushspadd
+ 51e: 0d popsp
+ 51f: 80 im 0
+ 520: 52 storesp 8
+
+00000521 <.L2>:
+ 521: 81 im 1
+ 522: 12 addsp 8
+ 523: 82 im 2
+ 524: 80 im 0
+ 525: 80 im 0
+ 526: 08 load
+ 527: 71 loadsp 4
+ 528: 82 im 2
+ 529: 80 im 0
+ 52a: 90 im 16
+ 52b: 0c store
+ 52c: 81 im 1
+ 52d: 12 addsp 8
+ 52e: 82 im 2
+ 52f: 80 im 0
+ 530: 80 im 0
+ 531: 08 load
+ 532: 71 loadsp 4
+ 533: 82 im 2
+ 534: 80 im 0
+ 535: 90 im 16
+ 536: 0c store
+ 537: 52 storesp 8
+ 538: 52 storesp 8
+ 539: 52 storesp 8
+ 53a: 52 storesp 8
+ 53b: e5 im -27
+ 53c: 39 poppcrel
+*/
+#define FPGA_ADDR 0x8000
+
+typedef volatile unsigned int* pAddr;
+#define FPGA_READ *(pAddr) (FPGA_ADDR)
+
+#define FPGA_WRITE *(pAddr) (FPGA_ADDR + 16)
+
+
+int main(int argc, char **argv)
+{
+int i;
+int j = 0;
+
+ while (1)
+
+ {
+ j++;
+ i = FPGA_READ;
+ FPGA_WRITE = j;
+ }
+}
diff --git a/zpu/roadshow/roadshow/net_test/.cvsignore b/zpu/roadshow/roadshow/net_test/.cvsignore
new file mode 100644
index 0000000..66dac94
--- /dev/null
+++ b/zpu/roadshow/roadshow/net_test/.cvsignore
@@ -0,0 +1,8 @@
+output
+all.txt
+dis.txt
+gmon.out
+ll.txt
+prof.txt
+net_test.txt
+gmon.sum
diff --git a/zpu/roadshow/roadshow/net_test/http_pages.c b/zpu/roadshow/roadshow/net_test/http_pages.c
new file mode 100644
index 0000000..437dad8
--- /dev/null
+++ b/zpu/roadshow/roadshow/net_test/http_pages.c
@@ -0,0 +1,206 @@
+#include <pkgconf/hal.h>
+#include <cyg/hal/hal_if.h>
+#include <pkgconf/system.h>
+#include <pkgconf/isoinfra.h>
+#include <pkgconf/net.h>
+#include <pkgconf/httpd.h>
+#include <cyg/httpd/httpd.h>
+#include <pkgconf/kernel.h>
+#include <stdio.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <string.h>
+
+static cyg_bool isUnsignedHex(char *string)
+{
+ int i = 0;
+ for(i = 0; string[i] != '\0'; i++)
+ if(!( ('0' <= string[i] && string[i] <= '9') ||
+ ('a' <= string[i] && string[i] <= 'f') ||
+ ('A' <= string[i] && string[i] <= 'F') ))
+ return 0;
+ return 1;
+}
+
+static cyg_bool net_test_mac_handler(FILE *client, char *filename, char *formdata, void *arg)
+{
+ char error_string[50];
+
+ error_string[0] = '\0';
+
+ if( formdata != NULL )
+ {
+ char *formlist[1];
+ char *mac_string = NULL;
+ /* Parse the data */
+ cyg_formdata_parse( formdata, formlist, 1 );
+ mac_string = cyg_formlist_find( formlist, "mac");
+ if(mac_string != NULL)
+ {
+
+ if(!isUnsignedHex(mac_string))
+ {
+ sprintf(error_string, "Please enter digits between 0-9 and a-f");
+ }
+ else if(strlen(mac_string) != 12)
+ {
+ sprintf(error_string, "Please enter a 12 digit MAC address");
+ }
+ else
+ {
+ char temp = '\0';
+ int fd = -1;
+ cyg_uint8 mac_addr[6];
+ error_string[0] = '\0';
+
+ temp = mac_string[2];
+ mac_string[2] = '\0';
+ mac_addr[0] = strtol(mac_string, NULL, 16);
+ mac_string[2] = temp;
+
+ temp = mac_string[4];
+ mac_string[4] = '\0';
+ mac_addr[1] = strtol(mac_string, NULL, 16);
+ mac_string[4] = temp;
+
+ temp = mac_string[6];
+ mac_string[6] = '\0';
+ mac_addr[2] = strtol(mac_string, NULL, 16);
+ mac_string[6] = temp;
+
+ temp = mac_string[8];
+ mac_string[8] = '\0';
+ mac_addr[3] = strtol(mac_string, NULL, 16);
+ mac_string[8] = temp;
+
+ temp = mac_string[10];
+ mac_string[10] = '\0';
+ mac_addr[4] = strtol(mac_string, NULL, 16);
+ mac_string[10] = temp;
+
+ temp = mac_string[12];
+ mac_string[12] = '\0';
+ mac_addr[5] = strtol(mac_string, NULL, 16);
+ mac_string[12] = temp;
+
+ /*write it to flash*/
+ fd = creat("/jffs2/mac", O_TRUNC | O_CREAT);
+ if(fd < 0)
+ {
+ sprintf(error_string, "<font color=red>%n %s</font>", errno, strerror(errno) );
+ }
+ else
+ {
+ write(fd, mac_addr, 6);
+ close(fd);
+ fd = -1;
+ //CYGACC_CALL_IF_RESET();
+ }
+ }
+ }
+ }
+
+ html_begin(client);
+
+ html_head(client,"Changing MAC Address", "");
+
+ html_body_begin(client,"");
+ {
+ fputs(error_string, client);
+ fputs("<br>\n", client);
+ html_form_begin( client, "/mac", "" );
+ {
+ fputs( "Enter the new mac address in the format xxxxxxxxxxxx ", client );
+ html_form_input( client, "mac", "mac", "", "");
+ }
+ html_form_end(client);
+ }
+ html_body_end(client);
+
+ html_end(client);
+
+ return 1;
+}
+
+CYG_HTTPD_TABLE_ENTRY( net_test_mac,
+ "/mac",
+ net_test_mac_handler,
+ NULL );
+
+
+static cyg_bool net_test_ip_handler(FILE *client, char *filename, char *formdata, void *arg)
+{
+ int fd = -1;
+ char error_string[50];
+ char error_string2[50];
+
+ error_string[0] = '\0';
+ error_string2[0] = '\0';
+ if( formdata != NULL )
+ {
+ char *formlist[1];
+ char *ip_string = NULL;
+ /* Parse the data */
+ cyg_formdata_parse( formdata, formlist, 1 );
+ ip_string = cyg_formlist_find( formlist, "ip");
+ if(ip_string != NULL)
+ {
+ /*write it to flash*/
+ fd = creat("/jffs2/ip", O_TRUNC | O_CREAT);
+ if(fd < 0)
+ {
+ sprintf(error_string, "<font color=red>%n %s</font>", errno, strerror(errno) );
+ }
+ else
+ {
+ write(fd, ip_string, strlen(ip_string));
+ close(fd);
+ fd = -1;
+ }
+ }
+ }
+ html_begin(client);
+
+ html_head(client,"Changing IP Address", "");
+
+ html_body_begin(client,"");
+ {
+ char value[81];
+ value[0] = '\0';
+ fd = open("/jffs2/ip", O_RDONLY);
+ if(fd < 0)
+ {
+ sprintf(error_string2, "<font color=red>%n %s</font>", errno, strerror(errno) );
+ }
+ else
+ {
+ int len = read(fd, value, 80);
+ value[len] = '\0';
+ close(fd);
+ fd = -1;
+ }
+ fputs(error_string, client);
+ fputs("<br>\n", client);
+ fputs(error_string2, client);
+ fputs("<br>\n", client);
+ html_form_begin( client, "/ip", "" );
+ {
+ fputs( "Enter the new address in the following order: IP_mask_broadcast_gateway_server ", client );
+ fputs("<br>\n", client);
+ html_form_input( client, "ip", "ip", value, "");
+ }
+ html_form_end(client);
+ }
+ html_body_end(client);
+
+ html_end(client);
+
+ return 1;
+}
+
+CYG_HTTPD_TABLE_ENTRY( net_test_ip,
+ "/ip",
+ net_test_ip_handler,
+ NULL );
+
diff --git a/zpu/roadshow/roadshow/net_test/init.cpp b/zpu/roadshow/roadshow/net_test/init.cpp
new file mode 100644
index 0000000..b5805b2
--- /dev/null
+++ b/zpu/roadshow/roadshow/net_test/init.cpp
@@ -0,0 +1,52 @@
+#include <pkgconf/system.h>
+#include <pkgconf/isoinfra.h>
+#include <cyg/infra/diag.h>
+#include <cyg/io/file.h>
+
+#if 0
+externC int chdir(const char *);
+
+/* ================================================================= */
+/* Initialization object
+ */
+
+class NetTestInit
+{
+public:
+ NetTestInit();
+};
+
+/* ----------------------------------------------------------------- */
+/* Static initialization object instance. The constructor is
+ * prioritized to run after any filesystem constructors.
+ */
+static NetTestInit netTestInitializer CYGBLD_ATTRIB_INIT_PRI(CYG_INIT_IO_FS + 1);
+
+/* ----------------------------------------------------------------- */
+/* Constructor, mounts the file system
+ */
+
+NetTestInit::NetTestInit()
+{
+ int err = 0;
+ err = mount( "/dev/flash1", "/jffs2", "jffs2" );
+ if(err < 0)
+ {
+ diag_printf("unable to mount jffs\n");
+ }
+ else
+ {
+ diag_printf("mounted jffs\n");
+ }
+ err = mount( "", "/ramfs", "ramfs" );
+ if(err < 0)
+ {
+ diag_printf("unable to mount ramfs\n");
+ }
+ else
+ {
+ diag_printf("mounted ramfs\n");
+ }
+ chdir( "/ramfs" );
+}
+#endif
diff --git a/zpu/roadshow/roadshow/net_test/makefile b/zpu/roadshow/roadshow/net_test/makefile
new file mode 100644
index 0000000..877afab
--- /dev/null
+++ b/zpu/roadshow/roadshow/net_test/makefile
@@ -0,0 +1,41 @@
+PROJECTNAME = net_test
+OUT= output
+ECOS_DIR=$(OUT)/ecos
+INSTALL_DIR=$(ECOS_DIR)/install
+
+.symbolic: all clean ecos
+
+all: ecos app
+
+
+
+clean:
+ rm -rf $(OUT)/*
+
+$(OUT):
+ mkdir $(OUT)
+
+$(ECOS_DIR)/ecos.ecc $(INSTALL_DIR)/include/pkgconf/ecos.mak:
+ mkdir -p $(ECOS_DIR)
+ cd $(ECOS_DIR) && ecosconfig new zpuetherphi minimal
+ cd $(ECOS_DIR) && ecosconfig import ../../$(PROJECTNAME).ecm
+ cd $(ECOS_DIR) && ecosconfig tree
+ cd $(ECOS_DIR) && make -s headers
+
+$(OUT)/ecostree: $(ECOS_DIR)/ecos.ecc
+ cd $(ECOS_DIR) && ecosconfig tree
+ echo >$(OUT)/ecostree
+
+ecos $(INSTALL_DIR)/lib/libtarget.a $(INSTALL_DIR)/lib/vectors.o: $(OUT)/ecostree
+ cd $(ECOS_DIR) && make -s
+
+app:
+ make -f $(INSTALL_DIR)/include/pkgconf/ecos.mak -f makefile $(OUT)/$(PROJECTNAME).bin
+
+$(OUT)/$(PROJECTNAME).bin: *.c makefile
+ zpu-elf-gcc -I$(INSTALL_DIR)/include $(ECOS_GLOBAL_CFLAGS) $(ECOS_GLOBAL_LDFLAGS) -L$(INSTALL_DIR)/lib *.c* -o $(OUT)/$(PROJECTNAME).elf -Wl,-Map,$(OUT)/$(PROJECTNAME).map -nostartfiles -nostdlib -Ttarget.ld -lstdc++ -lsupc++
+ zpu-elf-objcopy -O binary $(OUT)/$(PROJECTNAME).elf $(OUT)/$(PROJECTNAME).bin
+ sh ../build/makefirmware.sh $(OUT)/$(PROJECTNAME).bin $(OUT)/$(PROJECTNAME).zpu
+ zpu-elf-size $(OUT)/$(PROJECTNAME).elf
+
+ \ No newline at end of file
diff --git a/zpu/roadshow/roadshow/net_test/net_test.ecm b/zpu/roadshow/roadshow/net_test/net_test.ecm
new file mode 100644
index 0000000..5b32991
--- /dev/null
+++ b/zpu/roadshow/roadshow/net_test/net_test.ecm
@@ -0,0 +1,237 @@
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+ description "" ;
+ hardware zpuetherphi ;
+ template default ;
+ package -hardware CYGPKG_HAL_ZYLIN current ;
+ package -hardware CYGPKG_HAL_ZYLIN_ZPU current ;
+ package -hardware CYGPKG_HAL_ZYLIN_ZPU_PHI current ;
+ package -hardware CYGPKG_IO_ETH_DRIVERS current ;
+ package -hardware CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC current ;
+ package -hardware CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI current ;
+ package -template CYGPKG_HAL current ;
+ package -template CYGPKG_IO current ;
+ package -template CYGPKG_INFRA current ;
+ package -template CYGPKG_ERROR current ;
+ package -template CYGPKG_ISOINFRA current ;
+ package -template CYGPKG_IO_SERIAL current ;
+ package -template CYGPKG_KERNEL current ;
+ package -template CYGPKG_MEMALLOC current ;
+ package -template CYGPKG_LIBC current ;
+ package -template CYGPKG_LIBC_I18N current ;
+ package -template CYGPKG_LIBC_SETJMP current ;
+ package -template CYGPKG_LIBC_SIGNALS current ;
+ package -template CYGPKG_LIBC_STARTUP current ;
+ package -template CYGPKG_LIBC_STDIO current ;
+ package -template CYGPKG_LIBC_STDLIB current ;
+ package -template CYGPKG_LIBC_STRING current ;
+ package -template CYGPKG_LIBC_TIME current ;
+ package -template CYGPKG_LIBM current ;
+ package -template CYGPKG_IO_WALLCLOCK current ;
+ package CYGPKG_NET_FREEBSD_STACK current ;
+ package CYGPKG_IO_FILEIO current ;
+ package CYGPKG_NET current ;
+ package CYGPKG_HTTPD current ;
+};
+
+cdl_component CYGPKG_IO_ETH_DRIVERS_STAND_ALONE {
+ inferred_value 0
+};
+
+cdl_option CYGINT_DEVS_ETH_OPENCORES_ETHERMAC_TxNUM {
+ user_value 4
+};
+
+cdl_option CYGINT_DEVS_ETH_OPENCORES_ETHERMAC_RxNUM {
+ user_value 32
+};
+
+cdl_option CYGSEM_ERROR_PER_THREAD_ERRNO {
+ inferred_value 0
+};
+
+cdl_option CYGBLD_ISO_CTYPE_HEADER {
+ inferred_value 1 <cyg/libc/i18n/ctype.inl>
+};
+
+cdl_option CYGBLD_ISO_ERRNO_CODES_HEADER {
+ inferred_value 1 <cyg/error/codes.h>
+};
+
+cdl_option CYGBLD_ISO_ERRNO_HEADER {
+ inferred_value 1 <cyg/error/errno.h>
+};
+
+cdl_option CYGBLD_ISO_STDIO_FILETYPES_HEADER {
+ inferred_value 1 <cyg/libc/stdio/stdio.h>
+};
+
+cdl_option CYGBLD_ISO_STDIO_STREAMS_HEADER {
+ inferred_value 1 <cyg/libc/stdio/stdio.h>
+};
+
+cdl_option CYGBLD_ISO_STDIO_FILEOPS_HEADER {
+ inferred_value 1 <cyg/libc/stdio/stdio.h>
+};
+
+cdl_option CYGBLD_ISO_STDIO_FILEACCESS_HEADER {
+ inferred_value 1 <cyg/libc/stdio/stdio.h>
+};
+
+cdl_option CYGBLD_ISO_STDIO_FORMATTED_IO_HEADER {
+ inferred_value 1 <cyg/libc/stdio/stdio.h>
+};
+
+cdl_option CYGBLD_ISO_STDIO_CHAR_IO_HEADER {
+ inferred_value 1 <cyg/libc/stdio/stdio.h>
+};
+
+cdl_option CYGBLD_ISO_STDIO_DIRECT_IO_HEADER {
+ inferred_value 1 <cyg/libc/stdio/stdio.h>
+};
+
+cdl_option CYGBLD_ISO_STDIO_FILEPOS_HEADER {
+ inferred_value 1 <cyg/libc/stdio/stdio.h>
+};
+
+cdl_option CYGBLD_ISO_STDIO_ERROR_HEADER {
+ inferred_value 1 <cyg/libc/stdio/stdio.h>
+};
+
+cdl_option CYGBLD_ISO_STDLIB_STRCONV_HEADER {
+ inferred_value 1 <cyg/libc/stdlib/atox.inl>
+};
+
+cdl_option CYGBLD_ISO_STDLIB_ABS_HEADER {
+ inferred_value 1 <cyg/libc/stdlib/abs.inl>
+};
+
+cdl_option CYGBLD_ISO_STDLIB_DIV_HEADER {
+ inferred_value 1 <cyg/libc/stdlib/div.inl>
+};
+
+cdl_option CYGBLD_ISO_STRERROR_HEADER {
+ inferred_value 1 <cyg/error/strerror.h>
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_FNMATCH_HEADER {
+ inferred_value 1 <cyg/fileio/fnmatch.h>
+};
+
+cdl_option CYGBLD_ISO_C_TIME_TYPES_HEADER {
+ inferred_value 1 <cyg/libc/time/time.h>
+};
+
+cdl_option CYGBLD_ISO_C_CLOCK_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/time/time.h>
+};
+
+cdl_option CYGBLD_ISO_SIGNAL_NUMBERS_HEADER {
+ inferred_value 1 <cyg/libc/signals/signal.h>
+};
+
+cdl_option CYGBLD_ISO_SIGNAL_IMPL_HEADER {
+ inferred_value 1 <cyg/libc/signals/signal.h>
+};
+
+cdl_option CYGBLD_ISO_SETJMP_HEADER {
+ inferred_value 1 <cyg/libc/setjmp/setjmp.h>
+};
+
+cdl_option CYGBLD_ISO_DIRENT_HEADER {
+ inferred_value 1 <cyg/fileio/dirent.h>
+};
+
+cdl_option CYGBLD_ISO_BSDTYPES_HEADER {
+ inferred_value 1 <sys/bsdtypes.h>
+};
+
+cdl_option CYGBLD_ISO_OPEN_MAX_HEADER {
+ inferred_value 1 <cyg/fileio/limits.h>
+};
+
+cdl_option CYGBLD_ISO_NAME_MAX_HEADER {
+ inferred_value 1 <cyg/fileio/limits.h>
+};
+
+cdl_option CYGBLD_ISO_NETDB_PROTO_HEADER {
+ inferred_value 1 <net/netdb.h>
+};
+
+cdl_option CYGBLD_ISO_NETDB_SERV_HEADER {
+ inferred_value 1 <net/netdb.h>
+};
+
+cdl_option CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT {
+ inferred_value 0
+};
+
+cdl_option CYGNUM_LIBC_MAIN_DEFAULT_STACK_SIZE {
+ user_value 16384
+};
+
+cdl_option CYGPKG_NET_TFTPD_THREAD_STACK_SIZE {
+ user_value (CYGNUM_HAL_STACK_SIZE_TYPICAL+(8192))
+};
+
+cdl_component CYGPKG_NET_DHCP {
+ user_value 0
+};
+
+cdl_component CYGHWR_NET_DRIVER_ETH0_MANUAL {
+ inferred_value 0
+};
+
+cdl_component CYGHWR_NET_DRIVER_ETH0_BOOTP {
+ user_value 0
+};
+
+cdl_component CYGHWR_NET_DRIVER_ETH0_ADDRS {
+ user_value 1
+};
+
+cdl_option CYGHWR_NET_DRIVER_ETH0_ADDRS_IP {
+ user_value 10.0.0.57
+};
+
+cdl_option CYGHWR_NET_DRIVER_ETH0_ADDRS_BROADCAST {
+ user_value 10.0.0.255
+};
+
+cdl_option CYGHWR_NET_DRIVER_ETH0_ADDRS_GATEWAY {
+ user_value 10.0.0.1
+};
+
+cdl_option CYGHWR_NET_DRIVER_ETH0_ADDRS_SERVER {
+ user_value 10.0.0.58
+};
+
+
diff --git a/zpu/roadshow/roadshow/net_test/ping_test.c b/zpu/roadshow/roadshow/net_test/ping_test.c
new file mode 100644
index 0000000..7a3ce59
--- /dev/null
+++ b/zpu/roadshow/roadshow/net_test/ping_test.c
@@ -0,0 +1,585 @@
+//==========================================================================
+//
+// tests/ping_test.c
+//
+// Simple test of PING (ICMP) and networking support
+//
+//==========================================================================
+//####BSDCOPYRIGHTBEGIN####
+//
+// -------------------------------------------
+//
+// Portions of this software may have been derived from OpenBSD or other sources,
+// and are covered by the appropriate copyright disclaimers included herein.
+//
+// -------------------------------------------
+//
+//####BSDCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): gthomas
+// Contributors: gthomas, andrew.lunn@ascom.ch
+// Date: 2000-01-10
+// Purpose:
+// Description:
+//
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+// PING test code
+
+#include <network.h>
+#include <cyg/hal/hal_if.h>
+#include <stdio.h>
+#include <cyg/fileio/fileio.h>
+#include <unistd.h>
+#include <pkgconf/system.h>
+#include <pkgconf/net.h>
+#include <cyg/io/file.h>
+#include <cyg/infra/testcase.h>
+#include CYGDAT_DEVS_ETH_OPENCORES_ETHERMAC_CFG
+
+#ifdef CYGBLD_DEVS_ETH_DEVICE_H // Get the device config if it exists
+#include CYGBLD_DEVS_ETH_DEVICE_H // May provide CYGTST_DEVS_ETH_TEST_NET_REALTIME
+#endif
+
+#ifdef CYGPKG_NET_TESTS_USE_RT_TEST_HARNESS // do we use the rt test?
+# ifdef CYGTST_DEVS_ETH_TEST_NET_REALTIME // Get the test ancilla if it exists
+# include CYGTST_DEVS_ETH_TEST_NET_REALTIME
+# endif
+#endif
+
+// Fill in the blanks if necessary
+#ifndef TNR_OFF
+# define TNR_OFF()
+#endif
+#ifndef TNR_ON
+# define TNR_ON()
+#endif
+#ifndef TNR_INIT
+# define TNR_INIT()
+#endif
+#ifndef TNR_PRINT_ACTIVITY
+# define TNR_PRINT_ACTIVITY()
+#endif
+
+#include <cyg/io/io.h>
+
+#include <network.h>
+#include <tftp_support.h>
+
+#include <sys/types.h> //directory
+#include <dirent.h>
+
+//for serial
+cyg_io_handle_t handle;
+extern int inet_aton __P((const char *, struct in_addr *));
+#ifndef CYGPKG_LIBC_STDIO
+#define perror(s) diag_printf(#s ": %s\n", strerror(errno))
+#endif
+#define SHOW_RESULT( _fn, _res ) \
+diag_printf("<FAIL>: " #_fn "() returned %ld %s\n", (long)_res, _res<0?strerror(errno):"");
+
+/*
+#define STACK_SIZE (CYGNUM_HAL_STACK_SIZE_TYPICAL + 0x1000)
+static char stack[STACK_SIZE];
+static cyg_thread thread_data;
+static cyg_handle_t thread_handle;
+*/
+
+
+/* NB!!! must be divisible by 8 */
+#define NUM_PINGS 8192
+#define MAX_PACKET 16384
+#define MIN_PACKET 64
+#define MAX_SEND (IP_MAXPACKET - 100)
+
+#define PACKET_ADD ((MAX_SEND - MIN_PACKET)/NUM_PINGS)
+#define nPACKET_ADD 1
+
+static unsigned char pkt1[MAX_PACKET], pkt2[MAX_PACKET];
+
+#define UNIQUEID 0x1234
+/* we write this much to jffs2 in each go.
+ *
+ * DANGER!!! JFFS2 memory consumption is proportional to the # of write operations,
+ * so reducing this size will make the bootloader run out of memory.
+ */
+#define IOSIZE 16384
+void
+pexit(char *s)
+{
+ CYG_TEST_FAIL_FINISH(s);
+}
+
+// Compute INET checksum
+int
+inet_cksum(u_short *addr, int len)
+{
+ register int nleft = len;
+ register u_short *w = addr;
+ register u_short answer;
+ register u_int sum = 0;
+ u_short odd_byte = 0;
+
+ /*
+ * Our algorithm is simple, using a 32 bit accumulator (sum),
+ * we add sequential 16 bit words to it, and at the end, fold
+ * back all the carry bits from the top 16 bits into the lower
+ * 16 bits.
+ */
+ while( nleft > 1 ) {
+ cyg_uint32 t=*w++;
+ sum += t;
+ nleft -= 2;
+ }
+
+ /* mop up an odd byte, if necessary */
+ if( nleft == 1 ) {
+ *(u_char *)(&odd_byte) = *(u_char *)w;
+ sum += odd_byte;
+ }
+
+ /*
+ * add back carry outs from top 16 bits to low 16 bits
+ */
+ sum = (sum >> 16) + (sum & 0x0000ffff); /* add hi 16 to low 16 */
+ sum += (sum >> 16); /* add carry */
+ answer = ~sum; /* truncate to 16 bits */
+ return (answer);
+}
+
+static int
+show_icmp(unsigned char *pkt, int len,
+ struct sockaddr_in *from, struct sockaddr_in *to)
+{
+ char buffer[100];
+ cyg_uint32 buffer_index = 0;
+ cyg_tick_count_t tp, tv;
+ struct ip *ip;
+ struct icmp *icmp;
+ tv = cyg_current_time();
+ ip = (struct ip *)pkt;
+ if ((len < (int)sizeof(*ip)) || ip->ip_v != IPVERSION)
+ {
+ buffer[0] = '\0';
+ snprintf(buffer, 99, "%s: Short packet or not IP! - Len: %d, Version: %d\r\n",
+ inet_ntoa(from->sin_addr), len, ip->ip_v);
+ buffer_index = strlen(buffer);
+ cyg_io_write(handle, buffer, &buffer_index);
+ return 0;
+ }
+ icmp = (struct icmp *)(pkt + sizeof(*ip));
+ len -= (sizeof(*ip) + 8);
+ tp = *((cyg_tick_count_t *)&icmp->icmp_data);
+ if (icmp->icmp_type != ICMP_ECHOREPLY)
+ {
+ buffer[0] = '\0';
+ snprintf(buffer, 99, "%s: Invalid ICMP - type: %d\r\n",
+ inet_ntoa(from->sin_addr), icmp->icmp_type);
+ buffer_index = strlen(buffer);
+ cyg_io_write(handle, buffer, &buffer_index);
+ return 0;
+ }
+ if (icmp->icmp_id != UNIQUEID)
+ {
+ buffer[0] = '\0';
+ snprintf(buffer, 99, "%s: ICMP received for wrong id - sent: %x, recvd: %x\r\n",
+ inet_ntoa(from->sin_addr), UNIQUEID, icmp->icmp_id);
+ buffer_index = strlen(buffer);
+ cyg_io_write(handle, buffer, &buffer_index);
+ }
+// printf("%d bytes from %s: ", len, inet_ntoa(from->sin_addr));
+// printf("icmp_seq=%d", icmp->icmp_seq);
+ int t=(int)(tv-tp);
+ t*=10;
+// printf(", time=%d ms\n", t);
+ return (from->sin_addr.s_addr == to->sin_addr.s_addr);
+}
+
+static void
+ping_host(int s, struct sockaddr_in *host)
+{
+ char buffer[100];
+ cyg_uint32 buffer_index = 0;
+ struct icmp *icmp = (struct icmp *)pkt1;
+ int icmp_len = MIN_PACKET;
+ int seq = 0, ok_recv = 0, bogus_recv = 0;
+ cyg_tick_count_t *tp;
+ long *dp;
+ struct sockaddr_in from;
+ int len;
+ socklen_t fromlen;
+
+ ok_recv = 0;
+ bogus_recv = 0;
+ snprintf(buffer, 99, "PING server %s\r\n", inet_ntoa(host->sin_addr));
+ buffer_index = strlen(buffer);
+ cyg_io_write(handle, buffer, &buffer_index);
+
+
+ for (seq = 0; seq < NUM_PINGS; seq++, icmp_len += PACKET_ADD )
+ {
+ cyg_thread_delay(50);
+ TNR_ON();
+
+ memset(pkt1, 0, sizeof(pkt1)); // make sure we start each time w/same situation...
+ // Build ICMP packet
+ icmp->icmp_type = ICMP_ECHO;
+ icmp->icmp_code = 0;
+ icmp->icmp_cksum = 0;
+ icmp->icmp_seq = seq;
+ icmp->icmp_id = 0x1234;
+ // Set up ping data
+ tp = (cyg_tick_count_t *)&icmp->icmp_data;
+ memset(tp, 0xff, icmp_len); // try to fish out bit 1 force to 0.
+ *tp++ = cyg_current_time();
+ tp++;
+ dp = (long *)tp;
+
+ // Add checksum
+ icmp->icmp_cksum = inet_cksum( (u_short *)icmp, icmp_len+8);
+ // Send it off
+ if (sendto(s, icmp, icmp_len+8, 0, (struct sockaddr *)host, sizeof(*host)) < 0) {
+ TNR_OFF();
+ perror("sendto");
+ continue;
+ }
+ // Wait for a response
+ fromlen = sizeof(from);
+ len = recvfrom(s, pkt2, sizeof(pkt2), 0, (struct sockaddr *)&from, &fromlen);
+ TNR_OFF();
+ if (len < 0) {
+ perror("recvfrom");
+ inet_cksum( (u_short *)icmp, icmp_len+8);
+ icmp_len = MIN_PACKET - PACKET_ADD; // just in case - long routes
+ } else {
+ if (show_icmp(pkt2, len, &from, host)) {
+ ok_recv++;
+ } else {
+ bogus_recv++;
+ }
+ }
+ }
+ TNR_OFF();
+ snprintf(buffer, 99, "Sent %d packets, received %d OK, %d bad\r\n", NUM_PINGS, ok_recv, bogus_recv);
+ buffer_index = strlen(buffer);
+ cyg_io_write(handle, buffer, &buffer_index);
+}
+
+#ifdef CYGPKG_PROFILE_GPROF
+#include <cyg/profile/profile.h>
+
+extern char _stext, _etext; // Defined by the linker
+
+static void
+start_profile(void)
+{
+ // This starts up the system-wide profiling, gathering
+ // profile information on all of the code, with a 16 byte
+ // "bucket" size, at a rate of 100us/profile hit.
+ // Note: a bucket size of 16 will give pretty good function
+ // resolution. Much smaller and the buffer becomes
+ // much too large for very little gain.
+ // Note: a timer period of 100us is also a reasonable
+ // compromise. Any smaller and the overhead of
+ // handling the timter (profile) interrupt could
+ // swamp the system. A fast processor might get
+ // by with a smaller value, but a slow one could
+ // even be swamped by this value. If the value is
+ // too large, the usefulness of the profile is reduced.
+
+ // no more interrupts than 1/10ms.
+ //profile_on(&_stext, &_etext, 16, 10000); // DRAM
+ //profile_on((void *)0x2000000, (void *)0x4000000, 32, 10000); // DRAM
+ //profile_on((void *)0, (void *)0x40000, 16, 10000); // SRAM
+ //profile_on(0, &_etext, 32, 10000); // SRAM & DRAM
+}
+#endif
+
+static void
+ping_test(struct bootp *bp)
+{
+ struct protoent *p;
+ struct timeval tv;
+ struct sockaddr_in host;
+ int s;
+
+ p = getprotobyname("icmp");
+ if (p == NULL)
+ {
+ pexit("getprotobyname");
+ return;
+ }
+ s = socket(AF_INET, SOCK_RAW, p->p_proto);
+ if (s < 0) {
+ pexit("socket");
+ return;
+ }
+ tv.tv_sec = 4;
+ tv.tv_usec = 0;
+ setsockopt(s, SOL_SOCKET, SO_RCVTIMEO, &tv, sizeof(tv));
+
+ // default is 8192 bytes which is not big enough for our ping tests...
+ int sndsize=70000;
+ setsockopt(s, SOL_SOCKET, SO_RCVBUF, (char *)&sndsize,
+ (int)sizeof(sndsize));
+ sndsize=70000;
+ setsockopt(s, SOL_SOCKET, SO_SNDBUF, (char *)&sndsize,
+ (int)sizeof(sndsize));
+
+ // Set up host address
+ host.sin_family = AF_INET;
+ host.sin_len = sizeof(host);
+ inet_aton("10.0.0.9", &(host.sin_addr)); // edgarpc dev machine
+// inet_aton("10.0.0.1", &host.sin_addr); // cisco router
+ host.sin_port = 0;
+ ping_host(s, &host);
+}
+
+void done_test()
+{
+}
+
+void
+net_test(void)
+{
+
+ Cyg_ErrNo err;
+ diag_printf("Start PING test\r\n");
+ TNR_INIT();
+
+ err = cyg_io_lookup("/dev/ser0", &handle);
+ if(err != ENOERR)
+ {
+ diag_printf("cannot open serial /dev/ser0");
+ return;
+ }
+ printf("Testing stdout...\r\n");
+
+#ifdef CYGHWR_NET_DRIVER_ETH0
+ if (eth0_up) {
+ ping_test(&eth0_bootp_data);
+ }
+#endif
+#ifdef CYGHWR_NET_DRIVER_ETH1
+ if (eth1_up) {
+ ping_test(&eth1_bootp_data);
+ }
+#endif
+ TNR_PRINT_ACTIVITY();
+ CYG_TEST_PASS_FINISH("Ping test OK");
+ done_test();
+}
+
+
+int getFileName(const char *extension, char *fileName)
+{
+ int found = 0;
+ DIR* ramfs = opendir("/ramfs");
+ if(ramfs == NULL)
+ {
+ diag_printf("cannot open /ramfs\n");
+ return found;
+ }
+ while(1)
+ {
+ struct dirent *entry = readdir( ramfs );
+ int len = 0;
+ if( entry == NULL )
+ break;
+ len = strlen(entry->d_name);
+ if(len > 4 && entry->d_name[len - 4] == '.' &&
+ entry->d_name[len - 3] == 'p' &&
+ entry->d_name[len - 2] == 'h' &&
+ entry->d_name[len - 1] == 'i')
+ {
+ found = 1;
+ strcpy(fileName, "/ramfs/");
+ strcat(fileName, entry->d_name);
+ }
+ }
+ closedir(ramfs);
+ ramfs = NULL;
+ return found;
+}
+
+static char buf[IOSIZE];
+
+static int copyfile( char *name2, char *name1 )
+{
+
+ int err = 0;
+ int fd1 = -1, fd2 = -1;
+ ssize_t done = 0, wrote = 0, current = 0;
+
+ diag_printf(" copy file %s -> %s\n",name2,name1);
+
+ fd1 = creat(name1, O_TRUNC | O_CREAT);
+ if( fd1 < 0 )
+ {
+ SHOW_RESULT( creat, fd1 );
+ diag_printf(" %s", name1);
+ return -1;
+ }
+
+ fd2 = open( name2, O_RDONLY );
+ if( fd2 < 0 )
+ {
+ SHOW_RESULT( open, fd2 );
+ diag_printf(" %s", name2);
+ return -1;
+ }
+
+ for(;;)
+ {
+ done = read( fd2, buf, IOSIZE );
+ if( done < 0 )
+ {
+ SHOW_RESULT( read, done );
+ return -1;
+ }
+
+ if( done == 0 ) break;
+
+ wrote = write( fd1, buf, done );
+ if( wrote != done )
+ {
+ SHOW_RESULT( write, wrote );
+ return -1;
+ }
+
+ current += wrote;
+ if( wrote != done ) break;
+ }
+ diag_printf("wrote %d\n", current);
+ err = close( fd1 );
+ if( err < 0 )
+ {
+ SHOW_RESULT( close, err );
+ diag_printf(" %s", name1);
+ return -1;
+ }
+
+ err = close( fd2 );
+ if( err < 0 )
+ {
+ SHOW_RESULT( close, err );
+ diag_printf(" %s", name2);
+ return -1;
+ }
+ return 0;
+}
+
+int isCompleted(const char *fileName)
+{
+ int err = access( fileName, W_OK );
+ int fd = 0;
+ char readyBuffer[5];
+ if( err < 0 && errno != EACCES )
+ {
+ SHOW_RESULT( access, err );
+ return 0;
+ }
+ fd = open(fileName, O_RDONLY);
+ if(fd < 0)
+ {
+ SHOW_RESULT( open, errno );
+ return 0;
+ }
+ err = lseek(fd, -5, SEEK_END);
+ if(err < 0)
+ {
+ SHOW_RESULT( lseek, err );
+ close(fd);
+ return 0;
+ }
+ err = read(fd, readyBuffer, 4);
+ if(err < 0)
+ {
+ SHOW_RESULT( read, err );
+ close(fd);
+ return 0;
+ }
+ readyBuffer[4] = '\0';
+ if(strncmp(readyBuffer, "Done", 4) != 0)
+ {
+ //diag_printf("Coudn't read \"Done\" at the end of the firmware file %s\n", readyBuffer);
+ close(fd);
+ return 0;
+ }
+ close(fd);
+ diag_printf("found!\n");
+ return 1;
+}
+
+static void ramfs_polling(cyg_addrword_t data)
+{
+ char fileName[100];
+ int found = 0;
+ while(1)
+ {
+ cyg_thread_delay(100);
+ //scan the file system for a new .phi file
+ found = getFileName("phi", fileName);
+ if(found)
+ {
+ //check if the file has been transfered
+ if(isCompleted(fileName))
+ {
+ //move the file to flash
+ unlink("/jffs2/firmware.bin");
+ copyfile(fileName, "/jffs2/firmware.bin");
+ diag_printf("firmware file copied to jffs2\n");
+ unlink(fileName);
+ diag_printf("unmounting /jffs\n");
+ umount("/jffs2");
+ diag_printf("Resetting...\n");
+// CYGACC_CALL_IF_RESET();
+ }
+ }
+ }
+}
+
+static unsigned char ramfs_polling_stack[CYGNUM_HAL_STACK_SIZE_TYPICAL];
+static cyg_handle_t ramfs_polling_handle;
+static cyg_thread ramfs_polling_thread;
+
+void start_ramfs_polling()
+{
+
+ cyg_thread_create(10, &ramfs_polling, 0, "ramfs_polling",
+ ramfs_polling_stack, CYGNUM_HAL_STACK_SIZE_TYPICAL,
+ &ramfs_polling_handle, &ramfs_polling_thread);
+ cyg_thread_resume(ramfs_polling_handle);
+}
+
+struct tftpd_fileops fileops = {open,
+ close,
+ write,
+ read};
+
+externC void phi_init_all_network_interfaces();
+
+int main(int argc, char **argv)
+{
+ diag_printf("Entered net_test main()\n");
+
+ int server_id = 0;
+
+ init_all_network_interfaces();
+
+
+
+ int i=0;
+ while(1)
+ {
+ cyg_thread_delay(500);
+// net_test();
+ diag_printf("sleeping... %d\n", i++);
+ }
+ return 0;
+}
diff --git a/zpu/snapshot.sh b/zpu/snapshot.sh
new file mode 100644
index 0000000..8fd6e33
--- /dev/null
+++ b/zpu/snapshot.sh
@@ -0,0 +1,7 @@
+export SNAPSHOT=`date +%Y-%m-%d`
+
+echo hdl$SNAPSHOT.zip docs$SNAPSHOT.zip sw$SNAPSHOT.zip
+rm -f hdl$SNAPSHOT.zip docs$SNAPSHOT.zip sw$SNAPSHOT.zip
+zip -r hdl$SNAPSHOT.zip hdl -x "*.svn*"
+zip -r docs$SNAPSHOT.zip docs -x "*.svn*"
+zip -r sw$SNAPSHOT.zip sw -x "*.svn*"
diff --git a/zpu/sw/ecos/repository/dev/eth/opencores/ethermac/current/cdl/opencores_ethermac_drivers.cdl b/zpu/sw/ecos/repository/dev/eth/opencores/ethermac/current/cdl/opencores_ethermac_drivers.cdl
new file mode 100644
index 0000000..017ee57
--- /dev/null
+++ b/zpu/sw/ecos/repository/dev/eth/opencores/ethermac/current/cdl/opencores_ethermac_drivers.cdl
@@ -0,0 +1,149 @@
+# ====================================================================
+#
+# opencores_ethermac_eth_drivers.cdl
+#
+# Ethernet drivers - support for Opencores ethermac controllers
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2004 Andrew Lunn
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s): Gaisler Research, (Konrad Eisele<eiselekd@web.de>)
+# Contributors:
+# Date: 2005-01-22
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC {
+ display "Opencores ethermac driver"
+ description "Ethernet driver for Opencores ethermac driver."
+
+ parent CYGPKG_IO_ETH_DRIVERS
+ active_if CYGPKG_IO_ETH_DRIVERS
+
+ active_if CYGINT_DEVS_ETH_OPENCORES_ETHERMAC_REQUIRED
+
+ include_dir .
+ include_files ; # none _exported_ whatsoever
+ compile if_oeth.c
+
+ include_files include/oeth_info.h
+
+ define_proc {
+ puts $::cdl_header "#include <pkgconf/system.h>";
+ puts $::cdl_header "#include CYGDAT_DEVS_ETH_OPENCORES_ETHERMAC_CFG";
+ }
+
+ cdl_option CYGNUM_DEVS_ETH_OPENCORES_ETHERMAC_DEV_COUNT {
+ display "Number of supported interfaces."
+ calculated { CYGINT_DEVS_ETH_OPENCORES_ETHERMAC_REQUIRED }
+ flavor data
+ description "
+ This option selects the number of ethernet interfaces to
+ be supported by the driver."
+ }
+
+ cdl_interface CYGINT_DEVS_ETH_OPENCORES_ETHERMAC_STATIC_ESA {
+ display "ESA is statically configured"
+ description "
+ If this is nonzero, then the ESA (MAC address) is statically
+ configured in the platform-specific package which instantiates
+ this driver with all its details.
+
+ Note that use of this option is deprecated in favor of a
+ CYGSEM_DEVS_ETH_..._SET_ESA option in the platform specific
+ driver."
+ }
+
+ cdl_option CYGINT_DEVS_ETH_OPENCORES_ETHERMAC_TxNUM {
+ display "Number of output buffers"
+ flavor data
+ legal_values 2 to 64
+ default_value 4
+ description "
+ This option specifies the number of output buffer packets
+ to be used for the opencores ethernet device in multiples of 2."
+ }
+
+ cdl_option CYGINT_DEVS_ETH_OPENCORES_ETHERMAC_RxNUM {
+ display "Number of input buffers"
+ flavor data
+ legal_values 2 to 64
+ default_value 4
+ description "
+ This option specifies the number of input buffer packets
+ to be used for the opencores ethernet device in multiples of 2."
+ }
+
+ cdl_component CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC_OPTIONS {
+ display "Opencores ethermac driver build options"
+ flavor none
+ no_define
+
+ cdl_option CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC_CFLAGS_ADD {
+ display "Additional compiler flags"
+ flavor data
+ no_define
+ default_value { "-D_KERNEL -D__ECOS" }
+ description "
+ This option modifies the set of compiler flags for
+ building the opencores ethermac driver package.
+ These flags are used in addition
+ to the set of global flags."
+ }
+ }
+
+ cdl_component CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC_FLUSH {
+ display "Cache flushing"
+ flavor bool
+ default_value 1
+ description "Flush cache before copying packets from/to the
+ ethermac dma transfer buffers. If you have cache snooping enabled
+ you can disable this option."
+
+ }
+
+ cdl_component CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC_ETH100 {
+ display "Initialize MII to 100mbit"
+ flavor bool
+ default_value 0
+ description "Issue a MII sequence that enables a 100mbit link "
+
+ }
+
+}
diff --git a/zpu/sw/ecos/repository/dev/eth/zpu/opencores/phi/current/cdl/phi_opencores_ethmac_drivers.cdl b/zpu/sw/ecos/repository/dev/eth/zpu/opencores/phi/current/cdl/phi_opencores_ethmac_drivers.cdl
new file mode 100644
index 0000000..580890d
--- /dev/null
+++ b/zpu/sw/ecos/repository/dev/eth/zpu/opencores/phi/current/cdl/phi_opencores_ethmac_drivers.cdl
@@ -0,0 +1,127 @@
+# ====================================================================
+#
+# phi_opencores_ethmac_drivers.cdl
+#
+# Ethernet drivers - support for Opencores ethermac controller
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s): Gaisler Research, (Konrad Eisele<eiselekd@web.de>)
+# Contributors: Zylin AS, (Edgar Grimberg<edgar.grimberg@zylin.com>)
+# Date: 2005-01-20
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI {
+
+ display "PHI opencores ethernet driver"
+
+ parent CYGPKG_IO_ETH_DRIVERS
+ active_if CYGPKG_IO_ETH_DRIVERS
+ active_if CYGPKG_HAL_ZYLIN_ZPU_PHI
+
+ requires CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC
+ description "Ethernet driver for ethermac in on a Zylin Phi Board."
+
+ include_dir cyg/io
+ compile -library=libextras.a if_opencores.c
+
+ define_proc {
+ puts $::cdl_system_header "/***** ethernet driver proc output start *****/"
+ puts $::cdl_system_header "#define CYGDAT_DEVS_ETH_OPENCORES_ETHERMAC_INL <cyg/io/devs_eth_zpu_opencores_phi.inl>"
+ puts $::cdl_system_header "#define CYGDAT_DEVS_ETH_OPENCORES_ETHERMAC_CFG <pkgconf/devs_eth_zpu_opencores_phi.h>"
+ puts $::cdl_system_header "/***** ethernet driver proc output end *****/"
+ }
+
+ # Arguably this should do in the generic package
+ # but then there is a logic loop so you can never enable it.
+
+ cdl_interface CYGINT_DEVS_ETH_OPENCORES_ETHERMAC_REQUIRED {
+ display "opencores ethermac driver required"
+ }
+
+ cdl_component CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI_ETH0 {
+ display "Ethernet port 0 driver"
+ flavor bool
+ default_value 1
+
+ implements CYGHWR_NET_DRIVERS
+ implements CYGHWR_NET_DRIVER_ETH0
+ implements CYGINT_DEVS_ETH_OPENCORES_ETHERMAC_REQUIRED
+
+ cdl_option CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI_ETH0_NAME {
+ display "Device name for the ethernet driver"
+ flavor data
+ default_value {"\"eth0\""}
+ description "
+ This option sets the name of the ethernet device for the
+ ethernet port."
+ }
+
+ cdl_option CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI_ETH0_ESA {
+ display "The ethernet station address (MAC)"
+ flavor data
+ default_value {"{0x00, 0x00, 0x5E, 0x21, 0x00, 0x01}"}
+ description "A static ethernet station address.
+ Caution: Booting two systems with the same MAC on the same
+ network, will cause severe conflicts."
+ }
+ }
+
+ cdl_component CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI_OPTIONS {
+ display "Opencores ethermac driver build options"
+ flavor none
+ no_define
+
+ cdl_option CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI_CFLAGS_ADD {
+ display "Additional compiler flags"
+ flavor data
+ no_define
+ default_value { "-D_KERNEL -D__ECOS" }
+ description "
+ This option modifies the set of compiler flags for
+ building the opencores ethermac driver package.
+ These flags are used in addition
+ to the set of global flags."
+ }
+ }
+
+}
+
+# EOF phi_opencores_ethmac_drivers.cdl
diff --git a/zpu/sw/ecos/repository/dev/eth/zpu/opencores/phi/current/include/devs_eth_zpu_opencores_phi.inl b/zpu/sw/ecos/repository/dev/eth/zpu/opencores/phi/current/include/devs_eth_zpu_opencores_phi.inl
new file mode 100644
index 0000000..7cfa114
--- /dev/null
+++ b/zpu/sw/ecos/repository/dev/eth/zpu/opencores/phi/current/include/devs_eth_zpu_opencores_phi.inl
@@ -0,0 +1,92 @@
+//==========================================================================
+//
+//
+//
+// Opencores ethermac I/O definitions.
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): Gaisler Research, (Konrad Eisele<eiselekd@web.de>)
+// Contributors:
+// Date: 2000-11-22
+//####DESCRIPTIONEND####
+//==========================================================================
+
+#include <pkgconf/system.h>
+#include <cyg/hal/hal_intr.h>
+
+#define CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC_ETH0_ESA CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI_ETH0_ESA
+#define CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC_INITFN openeth_phi_init
+
+#ifdef CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI_ETH0
+
+//structs and tables for eth0
+static oeth_info openeth_priv;
+ETH_DRV_SC(oeth_sc,
+ &openeth_priv, // Driver specific data
+ CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI_ETH0_NAME, // Name for device
+ openeth_start,
+ openeth_stop,
+ openeth_ioctl,
+ openeth_can_send,
+ openeth_send,
+ openeth_recv,
+ openeth_deliver,
+ openeth_poll,
+ openeth_int_vector
+);
+
+NETDEVTAB_ENTRY(oeth_netdev,
+ "openeth_" CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI_ETH0_NAME,
+ openeth_init,
+ &oeth_sc);
+#endif
+
+#if CYGNUM_DEVS_ETH_OPENCORES_ETHERMAC_DEV_COUNT > 1
+#error Only 1 ethermac at a time supported yet (eth0)
+#endif
+
+oeth_info *openeth_priv_array[CYGNUM_DEVS_ETH_OPENCORES_ETHERMAC_DEV_COUNT] = {
+#ifdef CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI_ETH0
+ &openeth_priv
+#endif
+};
+
+
+//EOF devs_eth_zpu_opencorec_phi.inl
+
+
diff --git a/zpu/sw/ecos/repository/dev/eth/zpu/opencores/phi/current/src/if_opencores.c b/zpu/sw/ecos/repository/dev/eth/zpu/opencores/phi/current/src/if_opencores.c
new file mode 100644
index 0000000..c18caca
--- /dev/null
+++ b/zpu/sw/ecos/repository/dev/eth/zpu/opencores/phi/current/src/if_opencores.c
@@ -0,0 +1,112 @@
+//==========================================================================
+//
+//
+//
+// Ethernet device driver for Opencore's ethermac on Zylin Phi
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//####BSDCOPYRIGHTBEGIN####
+//
+// -------------------------------------------
+//
+// Portions of this software may have been derived from OpenBSD or other sources,
+// and are covered by the appropriate copyright disclaimers included herein.
+//
+// -------------------------------------------
+//
+//####BSDCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): Gaisler Research, (Konrad Eisele<eiselekd@web.de>)
+// Contributors:
+// Date: 2005-01-20
+// Purpose:
+// Description: hardware driver for Opencores ethernet
+//
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/system.h>
+#ifdef CYGPKG_IO_ETH_DRIVERS
+#include <pkgconf/io_eth_drivers.h>
+#endif
+#include <pkgconf/devs_eth_opencores_ethermac.h>
+
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_cache.h>
+#include <cyg/infra/cyg_ass.h>
+#include <cyg/infra/diag.h>
+#include <cyg/hal/drv_api.h>
+#include <cyg/io/eth/netdev.h>
+#include <cyg/io/eth/eth_drv.h>
+
+#ifdef CYGPKG_NET
+#include <pkgconf/net.h>
+#include <cyg/kernel/kapi.h>
+#include <net/if.h> /* Needed for struct ifnet */
+#endif
+
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_intr.h>
+//#include <cyg/hal/hal_leon3.h>
+
+externC void openeth_device_init(struct eth_drv_sc *sc, cyg_uint32 idx, cyg_uint32 base, cyg_uint32 irq);
+
+bool openeth_phi_init(struct cyg_netdevtab_entry *ndp)
+{
+ struct eth_drv_sc *sc = (struct eth_drv_sc *)(ndp->device_instance);
+
+#if !defined(CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC_FLUSH)
+#error "CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC_FLUSH must be 1 for Zylin Phi"
+#endif
+
+#if 0
+ int i,j;
+ amba_ahb_device adev[CYGNUM_DEVS_ETH_OPENCORES_ETHERMAC_DEV_COUNT];
+ j = amba_get_free_ahbslv_devices (VENDOR_GAISLER, GAISLER_ETHAHB, adev, CYGNUM_DEVS_ETH_OPENCORES_ETHERMAC_DEV_COUNT);
+ for (i = 0;i < j;i++) {
+ openeth_device_init(sc,i,adev[i].start[0],adev[i].irq);
+ }
+#endif
+ openeth_device_init(sc, 0, 0x080C0000, CYGNUM_HAL_INTERRUPT_ETHERMAC);
+ return 1;
+}
diff --git a/zpu/sw/ecos/repository/ecos.db b/zpu/sw/ecos/repository/ecos.db
new file mode 100644
index 0000000..c31fc4b
--- /dev/null
+++ b/zpu/sw/ecos/repository/ecos.db
@@ -0,0 +1,128 @@
+
+package CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC {
+ alias { "opencore's ethermac support" devs_eth_opencores_ethermac }
+ hardware
+ directory dev/eth/opencores/ethermac
+ script opencores_ethermac_drivers.cdl
+ description "This package contains hardware support for Opencores
+ ethermac."
+}
+
+package CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI {
+ alias { "ethernet support for opencores on Zylin Phi addon board" devs_eth_zpu_opencores_phi }
+ hardware
+ directory dev/eth/zpu/opencores/phi
+ script phi_opencores_ethmac_drivers.cdl
+ description "This package contains hardware support for Opencores Ethermac
+ ethernet device on Phi."
+}
+
+
+
+package CYGPKG_HAL_ZYLIN {
+ alias { "Zylin common HAL" hal_zylin }
+ directory hal/zylin/arch
+ script hal_zylin.cdl
+ hardware
+ description "
+The Zylin architecture HAL package provides generic support for this
+processor architecture. It is also necessary to select a specific
+target platform HAL package."
+}
+
+
+package CYGPKG_HAL_ZYLIN_ZPU {
+ alias { "Zylin ZPU variant HAL" hal_zylin_zpu }
+ directory hal/zylin/zpu/var
+ script hal_zylin_zpu.cdl
+ hardware
+ description "
+ The Zylin ZPU HAL package provides the support needed to run eCos on Zylin
+ ZPU based targets."
+}
+
+
+
+package CYGPKG_HAL_ZYLIN_ZPU_ZETA {
+ alias { "Zylin ZPU simulation" zeta }
+ directory hal/zylin/zpu/zeta
+ script hal_zylin_zpu_zeta.cdl
+ hardware
+ description "
+ The Zylin ZPU package provides the support needed to run eCos on an Zylin
+ evaluation board."
+}
+package CYGPKG_HAL_ZYLIN_ZPU_PHI {
+ alias { "Zylin ZPU evaluation board" phi }
+ directory hal/zylin/zpu/phi
+ script hal_zylin_zpu_phi.cdl
+ hardware
+ description "
+ The Zylin ZPU package provides the support needed to run eCos on a Zylin eCosBoard"
+}
+
+package CYGPKG_HAL_ZYLIN_ZPU_ABEL {
+ alias { "Zylin ZPU Abel board" abel }
+ directory hal/zylin/zpu/abel
+ script hal_zylin_zpu_abel.cdl
+ hardware
+ description "
+ The Zylin ZPU package provides the support needed to run eCos on an Abel Zylin
+ evaluation board."
+}
+
+
+package CYGPKG_PHI_NET {
+ alias { "Zylin Phi networking" phi_net }
+ directory net/zylin
+ script phi_net.cdl
+ hardware
+ description "Contains phi specific network init."
+}
+
+
+target zeta {
+ alias { "Zylin ZPU evaluation board " zeta }
+ packages { CYGPKG_HAL_ZYLIN
+ CYGPKG_HAL_ZYLIN_ZPU
+ CYGPKG_HAL_ZYLIN_ZPU_ZETA
+ }
+ description "
+ The Zylin ZPU target provides the packages needed to run eCos on an Zylin
+ evaluation board."
+}
+
+target phi {
+ alias { "Zylin ZPU evaluation board " phi }
+ packages { CYGPKG_HAL_ZYLIN
+ CYGPKG_HAL_ZYLIN_ZPU
+ CYGPKG_HAL_ZYLIN_ZPU_PHI
+ }
+ description "
+ The Zylin ZPU target provides the packages needed to run eCos on an Zylin eCosBoard"
+}
+
+target abel {
+ alias { "Zylin ZPU evaluation board " abel }
+ packages { CYGPKG_HAL_ZYLIN
+ CYGPKG_HAL_ZYLIN_ZPU
+ CYGPKG_HAL_ZYLIN_ZPU_ABEL
+ }
+ description "
+ The Zylin ZPU target provides the packages needed to run eCos on an Abel Zylin
+ evaluation board."
+}
+
+target zpuetherphi {
+ alias { "Zylin Phi addon board with ethernet" etherphi }
+ packages { CYGPKG_HAL_ZYLIN
+ CYGPKG_HAL_ZYLIN_ZPU
+ CYGPKG_HAL_ZYLIN_ZPU_PHI
+ CYGPKG_IO_ETH_DRIVERS
+ CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC
+ CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI
+ }
+ description "
+ The Zylin Phi ZPU target provides the packages needed to run ZPU eCos on a
+ Zylin eCosBoard addon board with ethernet."
+}
diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/ChangeLog b/zpu/sw/ecos/repository/hal/zylin/arch/current/ChangeLog
new file mode 100644
index 0000000..6403c63
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/ChangeLog
@@ -0,0 +1,39 @@
+2004-11-05 Øyvind Harboe <oyvind.harboe@zylin.com>
+
+ * First cut of ZYLIN support
+
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/cdl/hal_zylin.cdl b/zpu/sw/ecos/repository/hal/zylin/arch/current/cdl/hal_zylin.cdl
new file mode 100644
index 0000000..cecc879
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/cdl/hal_zylin.cdl
@@ -0,0 +1,108 @@
+# ====================================================================
+#
+# hal_zylin.cdl
+#
+# ZYLIN architectural HAL package configuration data
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s): bartv
+# Original data: gthomas
+# Contributors:
+# Date: 1999-06-13
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+cdl_package CYGPKG_HAL_ZYLIN {
+ display "ZYLIN architecture"
+ parent CYGPKG_HAL
+ hardware
+ include_dir cyg/hal
+ requires !CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT
+ define_header hal_zylin.h
+ description "
+ The ZYLIN architecture HAL package provides generic
+ support for this processor architecture. It is also
+ necessary to select a specific target platform HAL
+ package."
+
+ compile hal_misc.c context.S vectors.c
+
+ # The "-o file" is a workaround for CR100958 - without it the
+ # output file would end up in the source directory under CygWin.
+ # n.b. grep does not behave itself under win32
+ make -priority 1 {
+ zylin.inc : <PACKAGE>/src/hal_mk_defs.c
+ $(CC) $(CFLAGS) $(INCLUDE_PATH) -Wp,-MD,zylin.tmp -o hal_mk_defs.tmp -S $<
+ fgrep .equ hal_mk_defs.tmp | sed s/#// > $@
+ @echo $@ ": \\" > $(notdir $@).deps
+ @tail -n +2 zylin.tmp >> $(notdir $@).deps
+ @echo >> $(notdir $@).deps
+ @rm zylin.tmp hal_mk_defs.tmp
+ }
+
+ make {
+ <PREFIX>/lib/vectors.o : <PACKAGE>/src/vectors.c
+ $(CC) -Wp,-MD,vectors.tmp $(INCLUDE_PATH) $(CFLAGS) -c -o $@ $<
+ @echo $@ ": \\" > $(notdir $@).deps
+ @tail -n +2 vectors.tmp >> $(notdir $@).deps
+ @echo >> $(notdir $@).deps
+ @rm vectors.tmp
+ }
+
+
+ make {
+ <PREFIX>/lib/target.ld: <PACKAGE>/src/zylin.ld
+ $(CC) -E -P -Wp,-MD,target.tmp -xc $(INCLUDE_PATH) $(CFLAGS) -o $@ $<
+ @echo $@ ": \\" > $(notdir $@).deps
+ @tail -n +2 target.tmp >> $(notdir $@).deps
+ @echo >> $(notdir $@).deps
+ @rm target.tmp
+ }
+
+
+ cdl_option CYGBLD_LINKER_SCRIPT {
+ display "Linker script"
+ flavor data
+ no_define
+ calculated { "src/zylin.ld" }
+ }
+
+}
+
+# EOF hal_zylin.cdl
diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/include/arch.inc b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/arch.inc
new file mode 100644
index 0000000..a30819e
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/arch.inc
@@ -0,0 +1,79 @@
+##=============================================================================
+##
+## arch.inc
+##
+## ZYLIN architecture assembler header file
+##
+##=============================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+##=============================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s): jskov
+## Contributors:jskov
+## Date: 2000-11-15
+## Purpose: ZYLIN definitions.
+## Description: This file contains various definitions and macros that are
+## useful for writing assembly code for the ZYLIN
+## It also includes the variant/platform assembly header file.
+## Usage:
+## #include <cyg/hal/arch.inc>
+## ...
+##
+##
+######DESCRIPTIONEND####
+##
+##=============================================================================
+
+#include <cyg/hal/basetype.h>
+
+##-----------------------------------------------------------------------------
+## ZYLIN entry definitions. This allows _ prefixing to change by modifying
+## the CYG_LABEL_DEFN macro.
+
+#define FUNC_START(name) \
+ .type CYG_LABEL_DEFN(name),@function; \
+ .globl CYG_LABEL_DEFN(name); \
+CYG_LABEL_DEFN(name):
+
+#define FUNC_END(name) \
+ .globl CYG_LABEL_DEFN(name); \
+CYG_LABEL_DEFN(name):
+
+#define SYM_DEF(name) \
+ .globl CYG_LABEL_DEFN(name); \
+CYG_LABEL_DEFN(name):
+
+#------------------------------------------------------------------------------
+# end of arch.inc
diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/include/basetype.h b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/basetype.h
new file mode 100644
index 0000000..6f2c2c7
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/basetype.h
@@ -0,0 +1,83 @@
+#ifndef CYGONCE_HAL_BASETYPE_H
+#define CYGONCE_HAL_BASETYPE_H
+
+//=============================================================================
+//
+// basetype.h
+//
+// Standard types for this architecture.
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): nickg, gthomas
+// Contributors: nickg, gthomas
+// Date: 1998-09-11
+// Purpose: Define architecture base types.
+// Usage: Included by "cyg_type.h", do not use directly
+
+//
+//####DESCRIPTIONEND####
+//
+
+//-----------------------------------------------------------------------------
+// Characterize the architecture
+
+#define CYG_BYTEORDER CYG_MSBFIRST // Big endian
+#define CYG_DOUBLE_BYTEORDER CYG_MSBFIRST // Big? endian
+
+//-----------------------------------------------------------------------------
+// ZYLIN does not usually use labels with underscores.
+
+#define CYG_LABEL_NAME(_name_) _name_
+#define CYG_LABEL_DEFN(_name_) _name_
+
+//-----------------------------------------------------------------------------
+// Override the alignment definitions from cyg_type.h. ZYLIN only allows 4
+// byte alignment whereas the default is 8 byte.
+
+#define CYGARC_ALIGNMENT 4
+#define CYGARC_P2ALIGNMENT 2
+
+//-----------------------------------------------------------------------------
+// Define the standard variable sizes
+
+// The ZYLIN architecture uses the default definitions of the base types,
+// so we do not need to define any here.
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_BASETYPE_H
+// End of basetype.h
diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_arch.h b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_arch.h
new file mode 100644
index 0000000..cd61277
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_arch.h
@@ -0,0 +1,255 @@
+#ifndef CYGONCE_HAL_ARCH_H
+#define CYGONCE_HAL_ARCH_H
+
+//==========================================================================
+//
+// hal_arch.h
+//
+// Architecture specific abstractions
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): nickg, gthomas
+// Contributors: nickg, gthomas
+// Date: 1999-02-20
+// Purpose: Define architecture abstractions
+// Usage: #include <cyg/hal/hal_arch.h>
+
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h> // To decide on stack usage
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/plf_io.h>
+#ifdef CYGBLD_HAL_ZYLIN_PLF_ARCH_H
+#include <cyg/hal/plf_arch.h>
+#endif
+
+#ifdef CYGBLD_HAL_ZYLIN_VAR_ARCH_H
+#include <cyg/hal/var_arch.h>
+#endif
+
+
+// It seems that r0-r3,r12 are considered scratch by function calls
+
+typedef struct
+{
+ cyg_uint32 reg[8];
+ cyg_uint32 interrupt;
+ cyg_uint32 pc; // must be last...
+} HAL_SavedRegisters;
+
+//-------------------------------------------------------------------------
+// Exception handling function.
+// This function is defined by the kernel according to this prototype. It is
+// invoked from the HAL to deal with any CPU exceptions that the HAL does
+// not want to deal with itself. It usually invokes the kernel's exception
+// delivery mechanism.
+
+externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data );
+
+//-------------------------------------------------------------------------
+// Bit manipulation macros
+
+externC int hal_lsbindex(int);
+externC int hal_msbindex(int);
+
+#define HAL_LSBIT_INDEX(index, mask) index = hal_lsbindex(mask)
+#define HAL_MSBIT_INDEX(index, mask) index = hal_msbindex(mask)
+
+//-------------------------------------------------------------------------
+// Context Initialization
+// Initialize the context of a thread.
+// Arguments:
+// _sparg_ name of variable containing current sp, will be changed to new sp
+// _thread_ thread object address, passed as argument to entry point
+// _entry_ entry point address.
+// _id_ bit pattern used in initializing registers, for debugging.
+
+#define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ ) \
+ CYG_MACRO_START \
+ cyg_uint32 *_sp_=(cyg_uint32 *)(((CYG_WORD)_sparg_) &~3); \
+ *--_sp_=(CYG_ADDRWORD)_thread_; \
+ *--_sp_=(CYG_ADDRWORD)0xffffffff; /* dummy return address */ \
+ *--_sp_=(cyg_uint32)(_entry_); /* PC = [initial] entry point */ \
+ *--_sp_= 0; /* interrupt mask */ \
+ *--_sp_= (_id_)|7; \
+ *--_sp_= (_id_)|6; \
+ *--_sp_= (_id_)|5; \
+ *--_sp_= (_id_)|4; \
+ *--_sp_= (_id_)|3; \
+ *--_sp_= (_id_)|2; \
+ *--_sp_= (_id_)|1; \
+ *--_sp_=(_id_)|0; \
+ _sparg_ = (CYG_ADDRWORD)_sp_; \
+ CYG_MACRO_END
+
+//--------------------------------------------------------------------------
+// Context switch macros.
+// The arguments are pointers to locations where the stack pointer
+// of the current thread is to be stored, and from where the sp of the
+// next thread is to be fetched.
+
+externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from );
+externC void hal_thread_load_context( CYG_ADDRESS to )
+ __attribute__ ((noreturn));
+
+#define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_) \
+ hal_thread_switch_context((CYG_ADDRESS)_tspptr_, \
+ (CYG_ADDRESS)_fspptr_);
+
+#define HAL_THREAD_LOAD_CONTEXT(_tspptr_) \
+ hal_thread_load_context( (CYG_ADDRESS)_tspptr_ );
+
+//--------------------------------------------------------------------------
+// Execution reorder barrier.
+// When optimizing the compiler can reorder code. In multithreaded systems
+// where the order of actions is vital, this can sometimes cause problems.
+// This macro may be inserted into places where reordering should not happen.
+
+#define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" )
+
+//--------------------------------------------------------------------------
+// Breakpoint support
+// HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to happen
+// if executed.
+// HAL_BREAKINST is the value of the breakpoint instruction and
+// HAL_BREAKINST_SIZE is its size in bytes.
+
+#define _stringify1(__arg) #__arg
+#define _stringify(__arg) _stringify1(__arg)
+
+#define HAL_BREAKINST_ZYLIN 0
+#define HAL_BREAKINST_ZYLIN_SIZE 1
+
+
+#define HAL_BREAKPOINT(_label_) \
+asm volatile (" .globl " #_label_ ";" \
+ #_label_":" \
+ " .byte " _stringify(HAL_BREAKINST_ZYLIN) \
+ );
+
+//#define HAL_BREAKINST {0xFE, 0xDE, 0xFF, 0xE7}
+#define HAL_BREAKINST HAL_BREAKINST_ZYLIN
+#define HAL_BREAKINST_SIZE HAL_BREAKINST_ZYLIN_SIZE
+#define HAL_BREAKINST_TYPE cyg_uint8
+
+extern cyg_uint32 __zylin_breakinst;
+#define HAL_BREAKINST_ADDR(x) (void*)&__zylin_breakinst)
+
+
+// Translate a stack pointer as saved by the thread context macros above into
+// a pointer to a HAL_SavedRegisters structure.
+#define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \
+ (_regs_) = (HAL_SavedRegisters *)(_sp_)
+
+
+
+//--------------------------------------------------------------------------
+// HAL setjmp
+
+#define CYGARC_JMP_BUF_SIZE 16 // Actually 11, but some room left over
+
+typedef cyg_uint32 hal_jmp_buf[CYGARC_JMP_BUF_SIZE];
+
+externC int hal_setjmp(hal_jmp_buf env);
+externC void hal_longjmp(hal_jmp_buf env, int val);
+
+
+//--------------------------------------------------------------------------
+// Idle thread code.
+// This macro is called in the idle thread loop, and gives the HAL the
+// chance to insert code. Typical idle thread behaviour might be to halt the
+// processor. Here we only supply a default fallback if the variant/platform
+// doesn't define anything.
+
+#ifndef HAL_IDLE_THREAD_ACTION
+#define HAL_IDLE_THREAD_ACTION(_count_) CYG_EMPTY_STATEMENT
+#endif
+
+//---------------------------------------------------------------------------
+
+// Minimal and sensible stack sizes: the intention is that applications
+// will use these to provide a stack size in the first instance prior to
+// proper analysis. Idle thread stack should be this big.
+
+// THESE ARE NOT INTENDED TO BE MICROMETRICALLY ACCURATE FIGURES.
+// THEY ARE HOWEVER ENOUGH TO START PROGRAMMING.
+// YOU MUST MAKE YOUR STACKS LARGER IF YOU HAVE LARGE "AUTO" VARIABLES!
+
+// This is not a config option because it should not be adjusted except
+// under "enough rope" sort of disclaimers.
+
+// A minimal, optimized stack frame, rounded up - no autos
+#define CYGNUM_HAL_STACK_FRAME_SIZE (4 * 80)
+
+// Stack needed for a context switch: this is implicit in the estimate for
+// interrupts so not explicitly used below:
+#define CYGNUM_HAL_STACK_CONTEXT_SIZE (4 * 80)
+
+// Interrupt + call to ISR, interrupt_end() and the DSR
+#define CYGNUM_HAL_STACK_INTERRUPT_SIZE \
+ ((4 * 80) + 2 * CYGNUM_HAL_STACK_FRAME_SIZE)
+
+// Space for the maximum number of nested interrupts, plus room to call functions
+#define CYGNUM_HAL_MAX_INTERRUPT_NESTING 16
+
+#if 0
+#define CYGNUM_HAL_STACK_SIZE_MINIMUM
+ (CYGNUM_HAL_MAX_INTERRUPT_NESTING * CYGNUM_HAL_STACK_INTERRUPT_SIZE + \
+ 2 * CYGNUM_HAL_STACK_FRAME_SIZE)
+
+#define CYGNUM_HAL_STACK_SIZE_TYPICAL \
+ (CYGNUM_HAL_STACK_SIZE_MINIMUM + \
+ 16 * CYGNUM_HAL_STACK_FRAME_SIZE)
+#else
+#define CYGNUM_HAL_STACK_SIZE_MINIMUM 16384 // KLUDGE!!! until interrupt stacks can be added
+
+#define CYGNUM_HAL_STACK_SIZE_TYPICAL 32768 // KLUDGE!!! until interrupt stacks can be added
+
+#endif
+
+//--------------------------------------------------------------------------
+// Macros for switching context between two eCos instances (jump from
+// code in ROM to code in RAM or vice versa).
+#define CYGARC_HAL_SAVE_GP()
+#define CYGARC_HAL_RESTORE_GP()
+
+#endif // CYGONCE_HAL_ARCH_H
+// End of hal_arch.h
diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_intr.h b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_intr.h
new file mode 100644
index 0000000..6ec6070
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_intr.h
@@ -0,0 +1,261 @@
+#ifndef CYGONCE_HAL_INTR_H
+#define CYGONCE_HAL_INTR_H
+
+//==========================================================================
+//
+// hal_intr.h
+//
+// HAL Interrupt and clock support
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): nickg, gthomas
+// Contributors: nickg, gthomas,
+// jlzylinour
+// Date: 1999-02-20
+// Purpose: Define Interrupt support
+// Description: The macros defined here provide the HAL APIs for handling
+// interrupts and the clock.
+//
+// Usage: #include <cyg/hal/hal_intr.h>
+// ...
+//
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>
+
+// This is to allow a variant to decide that there is no platform-specific
+// interrupts file; and that in turn can be overridden by a platform that
+// refines the variant's ideas.
+#ifdef CYGBLD_HAL_PLF_INTS_H
+# include CYGBLD_HAL_PLF_INTS_H // should include variant data as required
+#else
+# ifdef CYGBLD_HAL_VAR_INTS_H
+# include CYGBLD_HAL_VAR_INTS_H
+# else
+# include <cyg/hal/hal_platform_ints.h> // default less-complex platforms
+# endif
+#endif
+
+// Spurious interrupt (no interrupt source could be found)
+#define CYGNUM_HAL_INTERRUPT_NONE -1
+
+//--------------------------------------------------------------------------
+// ZYLIN exception vectors.
+
+// These vectors correspond to VSRs. These values are the ones to use for
+// HAL_VSR_GET/SET
+
+#define CYGNUM_HAL_VECTOR_RESET 0
+#define CYGNUM_HAL_VECTOR_UNDEF_INSTRUCTION 1
+#define CYGNUM_HAL_VECTOR_MISC 2
+#define CYGNUM_HAL_VECTOR_IRQ 3
+#define CYGNUM_HAL_VECTOR_MEMORY 4
+
+#define CYGNUM_HAL_VSR_MIN 0
+#define CYGNUM_HAL_VSR_MAX 4
+#define CYGNUM_HAL_VSR_COUNT 5
+
+// Exception vectors. These are the values used when passed out to an
+// external exception handler using cyg_hal_deliver_exception()
+
+#define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION \
+ CYGNUM_HAL_VECTOR_UNDEF_INSTRUCTION
+#define CYGNUM_HAL_EXCEPTION_INTERRUPT \
+ CYGNUM_HAL_VECTOR_SOFTWARE_INTERRUPT
+#define CYGNUM_HAL_EXCEPTION_CODE_ACCESS CYGNUM_HAL_VECTOR_MEMORY
+#define CYGNUM_HAL_EXCEPTION_DATA_ACCESS CYGNUM_HAL_VECTOR_MEMORY
+
+#define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_VSR_MIN
+#define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_VSR_MAX
+#define CYGNUM_HAL_EXCEPTION_COUNT (CYGNUM_HAL_EXCEPTION_MAX - \
+ CYGNUM_HAL_EXCEPTION_MIN + 1)
+
+//--------------------------------------------------------------------------
+// Static data used by HAL
+
+// ISR tables
+
+externC CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
+externC CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];
+externC CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];
+
+// VSR table
+externC CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_COUNT];
+
+//--------------------------------------------------------------------------
+// Default ISR
+// The #define is used to test whether this routine exists, and to allow
+// code outside the HAL to call it.
+
+externC cyg_uint32 hal_default_isr(cyg_uint32 vector, CYG_ADDRWORD data);
+
+#define HAL_DEFAULT_ISR hal_default_isr
+
+//--------------------------------------------------------------------------
+// Interrupt state storage
+
+typedef cyg_uint32 CYG_INTERRUPT_STATE;
+
+//--------------------------------------------------------------------------
+// Interrupt control macros
+
+externC cyg_uint32 zpu_disable_interrupts();
+externC void zpu_enable_interrupts();
+externC void zpu_restore_interrupts(cyg_uint32);
+externC cyg_uint32 zpu_query_interrupts();
+
+#define HAL_DISABLE_INTERRUPTS(_old_) {_old_=zpu_disable_interrupts();}
+#define HAL_ENABLE_INTERRUPTS() zpu_enable_interrupts()
+#define HAL_RESTORE_INTERRUPTS(_old_) { zpu_restore_interrupts(_old_); }
+#define HAL_QUERY_INTERRUPTS(_old_) { _old_=zpu_query_interrupts(); }
+
+
+//--------------------------------------------------------------------------
+// Vector translation.
+
+#ifndef HAL_TRANSLATE_VECTOR
+#define HAL_TRANSLATE_VECTOR(_vector_,_index_) \
+ (_index_) = (_vector_)
+#endif
+
+//--------------------------------------------------------------------------
+// Interrupt and VSR attachment macros
+
+#define HAL_INTERRUPT_IN_USE( _vector_, _state_) \
+ CYG_MACRO_START \
+ cyg_uint32 _index_; \
+ HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
+ \
+ if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr ) \
+ (_state_) = 0; \
+ else \
+ (_state_) = 1; \
+ CYG_MACRO_END
+
+#define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \
+ CYG_MACRO_START \
+ if( hal_interrupt_handlers[_vector_] == (CYG_ADDRESS)hal_default_isr ) \
+ { \
+ hal_interrupt_handlers[_vector_] = (CYG_ADDRESS)_isr_; \
+ hal_interrupt_data[_vector_] = (CYG_ADDRWORD) _data_; \
+ hal_interrupt_objects[_vector_] = (CYG_ADDRESS)_object_; \
+ } \
+ CYG_MACRO_END
+
+#define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \
+ CYG_MACRO_START \
+ if( hal_interrupt_handlers[_vector_] == (CYG_ADDRESS)_isr_ ) \
+ { \
+ hal_interrupt_handlers[_vector_] = (CYG_ADDRESS)hal_default_isr; \
+ hal_interrupt_data[_vector_] = 0; \
+ hal_interrupt_objects[_vector_] = 0; \
+ } \
+ CYG_MACRO_END
+
+#define HAL_VSR_GET( _vector_, _pvsr_ ) \
+ *(CYG_ADDRESS *)(_pvsr_) = hal_vsr_table[_vector_];
+
+
+#define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) \
+ CYG_MACRO_START \
+ if( _poldvsr_ != NULL ) \
+ *(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_]; \
+ hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_; \
+ CYG_MACRO_END
+
+//--------------------------------------------------------------------------
+// Interrupt controller access
+
+externC void hal_interrupt_mask(int);
+externC void hal_interrupt_unmask(int);
+externC void hal_interrupt_acknowledge(int);
+externC void hal_interrupt_configure(int, int, int);
+externC void hal_interrupt_set_level(int, int);
+
+#define HAL_INTERRUPT_MASK( _vector_ ) \
+ hal_interrupt_mask( _vector_ )
+#define HAL_INTERRUPT_UNMASK( _vector_ ) \
+ hal_interrupt_unmask( _vector_ )
+#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
+ hal_interrupt_acknowledge( _vector_ )
+#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \
+ hal_interrupt_configure( _vector_, _level_, _up_ )
+#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \
+ hal_interrupt_set_level( _vector_, _level_ )
+
+//--------------------------------------------------------------------------
+// Clock control
+
+externC void hal_clock_initialize(cyg_uint32);
+externC void hal_clock_read(cyg_uint32 *);
+externC void hal_clock_reset(cyg_uint32, cyg_uint32);
+
+#define HAL_CLOCK_INITIALIZE( _period_ ) hal_clock_initialize( _period_ )
+#define HAL_CLOCK_RESET( _vec_, _period_ ) hal_clock_reset( _vec_, _period_ )
+#define HAL_CLOCK_READ( _pvalue_ ) hal_clock_read( _pvalue_ )
+#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
+# ifndef HAL_CLOCK_LATENCY
+# define HAL_CLOCK_LATENCY( _pvalue_ ) HAL_CLOCK_READ( (cyg_uint32 *)_pvalue_ )
+# endif
+#endif
+
+
+#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
+externC void hal_interrupt_stack_call_pending_DSRs(void);
+#define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \
+ hal_interrupt_stack_call_pending_DSRs()
+
+// these are offered solely for stack usage testing
+// if they are not defined, then there is no interrupt stack.
+#define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base
+#define HAL_INTERRUPT_STACK_TOP cyg_interrupt_stack
+// use them to declare these extern however you want:
+// extern char HAL_INTERRUPT_STACK_BASE[];
+// extern char HAL_INTERRUPT_STACK_TOP[];
+// is recommended
+#endif
+
+
+//--------------------------------------------------------------------------
+#endif // ifndef CYGONCE_HAL_INTR_H
+// End of hal_intr.h
diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_io.h b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_io.h
new file mode 100644
index 0000000..64ad695
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_io.h
@@ -0,0 +1,305 @@
+#ifndef CYGONCE_HAL_IO_H
+#define CYGONCE_HAL_IO_H
+
+//=============================================================================
+//
+// hal_io.h
+//
+// HAL device IO register support.
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): nickg, gthomas
+// Contributors: Fabrice Gautier
+// Date: 1998-09-11
+// Purpose: Define IO register support
+// Description: The macros defined here provide the HAL APIs for handling
+// device IO control registers.
+//
+// Usage:
+// #include <cyg/hal/hal_io.h>
+// ...
+//
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/system.h>
+#include <cyg/infra/cyg_type.h>
+
+#include <cyg/hal/basetype.h>
+
+//-----------------------------------------------------------------------------
+// Include plf_io.h for platforms. Either via var_io.h or directly.
+#ifdef CYGBLD_HAL_ZYLIN_VAR_IO_H
+#include <cyg/hal/var_io.h>
+#else
+#include <cyg/hal/plf_io.h>
+#endif
+
+
+//-----------------------------------------------------------------------------
+// IO Register address.
+// This type is for recording the address of an IO register.
+
+typedef volatile CYG_ADDRWORD HAL_IO_REGISTER;
+
+//-----------------------------------------------------------------------------
+// HAL IO macros.
+#ifndef HAL_IO_MACROS_DEFINED
+
+//-----------------------------------------------------------------------------
+// BYTE Register access.
+// Individual and vectorized access to 8 bit registers.
+
+// Little-endian version or big-endian version that doesn't need address munging
+#if (CYG_BYTEORDER == CYG_LSBFIRST) || defined(HAL_IO_MACROS_NO_ADDRESS_MUNGING)
+
+#define HAL_READ_UINT8( _register_, _value_ ) \
+ ((_value_) = *((volatile CYG_BYTE *)(_register_)))
+
+#define HAL_WRITE_UINT8( _register_, _value_ ) \
+ (*((volatile CYG_BYTE *)(_register_)) = (_value_))
+
+#define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
+ CYG_MACRO_START \
+ cyg_count32 _i_,_j_; \
+ for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
+ (_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_j_]; \
+ CYG_MACRO_END
+
+#define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
+ CYG_MACRO_START \
+ cyg_count32 _i_,_j_; \
+ for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
+ ((volatile CYG_BYTE *)(_register_))[_j_] = (_buf_)[_i_]; \
+ CYG_MACRO_END
+
+#define HAL_READ_UINT8_STRING( _register_, _buf_, _count_ ) \
+ CYG_MACRO_START \
+ cyg_count32 _i_; \
+ for( _i_ = 0; _i_ < (_count_); _i_++) \
+ (_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_i_]; \
+ CYG_MACRO_END
+
+#define HAL_WRITE_UINT8_STRING( _register_, _buf_, _count_ ) \
+ CYG_MACRO_START \
+ cyg_count32 _i_; \
+ for( _i_ = 0; _i_ < (_count_); _i_++) \
+ ((volatile CYG_BYTE *)(_register_)) = (_buf_)[_i_]; \
+ CYG_MACRO_END
+
+#else // Big-endian version
+
+#define HAL_READ_UINT8( _register_, _value_ ) \
+ ((_value_) = *((volatile CYG_BYTE *)((CYG_ADDRWORD)(_register_)^3)))
+
+#define HAL_WRITE_UINT8( _register_, _value_ ) \
+ (*((volatile CYG_BYTE *)((CYG_ADDRWORD)(_register_)^3)) = (_value_))
+
+#define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
+ CYG_MACRO_START \
+ cyg_count32 _i_,_j_; \
+ volatile CYG_BYTE* _r_ = ((CYG_ADDRWORD)(_register_)^3); \
+ for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
+ (_buf_)[_i_] = _r_[_j_]; \
+ CYG_MACRO_END
+
+#define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
+ CYG_MACRO_START \
+ cyg_count32 _i_,_j_; \
+ volatile CYG_BYTE* _r_ = ((CYG_ADDRWORD)(_register_)^3); \
+ for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
+ _r_[_j_] = (_buf_)[_i_]; \
+ CYG_MACRO_END
+
+#define HAL_READ_UINT8_STRING( _register_, _buf_, _count_ ) \
+ CYG_MACRO_START \
+ cyg_count32 _i_; \
+ volatile CYG_BYTE* _r_ = ((CYG_ADDRWORD)(_register_)^3); \
+ for( _i_ = 0; _i_ < (_count_); _i_++; \
+ (_buf_)[_i_] = _r_[_i_]; \
+ CYG_MACRO_END
+
+#define HAL_WRITE_UINT8_STRING( _register_, _buf_, _count_ ) \
+ CYG_MACRO_START \
+ cyg_count32 _i_; \
+ volatile CYG_BYTE* _r_ = ((CYG_ADDRWORD)(_register_)^3); \
+ for( _i_ = 0; _i_ < (_count_); _i_++) \
+ _r_[_i_] = (_buf_)[_i_]; \
+ CYG_MACRO_END
+
+#endif // Big-endian
+
+//-----------------------------------------------------------------------------
+// 16 bit access.
+// Individual and vectorized access to 16 bit registers.
+
+// Little-endian version or big-endian version that doesn't need address munging
+#if (CYG_BYTEORDER == CYG_LSBFIRST) || defined(HAL_IO_MACROS_NO_ADDRESS_MUNGING)
+
+#define HAL_READ_UINT16( _register_, _value_ ) \
+ ((_value_) = *((volatile CYG_WORD16 *)(_register_)))
+
+#define HAL_WRITE_UINT16( _register_, _value_ ) \
+ (*((volatile CYG_WORD16 *)(_register_)) = (_value_))
+
+#define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
+ CYG_MACRO_START \
+ cyg_count32 _i_,_j_; \
+ for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
+ (_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_j_]; \
+ CYG_MACRO_END
+
+#define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
+ CYG_MACRO_START \
+ cyg_count32 _i_,_j_; \
+ for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
+ ((volatile CYG_WORD16 *)(_register_))[_j_] = (_buf_)[_i_]; \
+ CYG_MACRO_END
+
+#define HAL_READ_UINT16_STRING( _register_, _buf_, _count_) \
+ CYG_MACRO_START \
+ cyg_count32 _i_; \
+ for( _i_ = 0; _i_ < (_count_); _i_++) \
+ (_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_i_]; \
+ CYG_MACRO_END
+
+#define HAL_WRITE_UINT16_STRING( _register_, _buf_, _count_) \
+ CYG_MACRO_START \
+ cyg_count32 _i_; \
+ for( _i_ = 0; _i_ < (_count_); _i_++) \
+ ((volatile CYG_WORD16 *)(_register_))[_i_] = (_buf_)[_i_]; \
+ CYG_MACRO_END
+
+
+#else // Big-endian version
+
+#define HAL_READ_UINT16( _register_, _value_ ) \
+ ((_value_) = *((volatile CYG_WORD16 *)((CYG_ADDRWORD)(_register_)^3)))
+
+#define HAL_WRITE_UINT16( _register_, _value_ ) \
+ (*((volatile CYG_WORD16 *)((CYG_ADDRWORD)(_register_)^3)) = (_value_))
+
+#define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
+ CYG_MACRO_START \
+ cyg_count32 _i_,_j_; \
+ volatile CYG_WORD16* _r_ = ((CYG_ADDRWORD)(_register_)^3); \
+ for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
+ (_buf_)[_i_] = _r_[_j_]; \
+ CYG_MACRO_END
+
+#define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
+ CYG_MACRO_START \
+ cyg_count32 _i_,_j_; \
+ volatile CYG_WORD16* _r_ = ((CYG_ADDRWORD)(_register_)^3); \
+ for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
+ _r_[_j_] = (_buf_)[_i_]; \
+ CYG_MACRO_END
+
+#define HAL_READ_UINT16_STRING( _register_, _buf_, _count_) \
+ CYG_MACRO_START \
+ cyg_count32 _i_; \
+ volatile CYG_WORD16* _r_ = ((CYG_ADDRWORD)(_register_)^3); \
+ for( _i_ = 0 = 0; _i_ < (_count_); _i_++) \
+ (_buf_)[_i_] = _r_[_i_]; \
+ CYG_MACRO_END
+
+#define HAL_WRITE_UINT16_STRING( _register_, _buf_, _count_) \
+ CYG_MACRO_START \
+ cyg_count32 _i_; \
+ volatile CYG_WORD16* _r_ = ((CYG_ADDRWORD)(_register_)^3); \
+ for( _i_ = 0 = 0; _i_ < (_count_); _i_++) \
+ _r_[_i_] = (_buf_)[_i_]; \
+ CYG_MACRO_END
+
+
+#endif // Big-endian
+
+//-----------------------------------------------------------------------------
+// 32 bit access.
+// Individual and vectorized access to 32 bit registers.
+
+// Note: same macros for little- and big-endian systems.
+
+#define HAL_READ_UINT32( _register_, _value_ ) \
+ ((_value_) = *((volatile CYG_WORD32 *)(_register_)))
+
+#define HAL_WRITE_UINT32( _register_, _value_ ) \
+ (*((volatile CYG_WORD32 *)(_register_)) = (_value_))
+
+#define HAL_READ_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \
+ CYG_MACRO_START \
+ cyg_count32 _i_,_j_; \
+ for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
+ (_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_j_]; \
+ CYG_MACRO_END
+
+#define HAL_WRITE_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \
+ CYG_MACRO_START \
+ cyg_count32 _i_,_j_; \
+ for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
+ ((volatile CYG_WORD32 *)(_register_))[_j_] = (_buf_)[_i_]; \
+ CYG_MACRO_END
+
+#define HAL_READ_UINT32_STRING( _register_, _buf_, _count_) \
+ CYG_MACRO_START \
+ cyg_count32 _i_; \
+ for( _i_ = 0; _i_ < (_count_); _i_++) \
+ (_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_i_]; \
+ CYG_MACRO_END
+
+#define HAL_WRITE_UINT32_STRING( _register_, _buf_, _count_) \
+ CYG_MACRO_START \
+ cyg_count32 _i_; \
+ for( _i_ = 0; _i_ < (_count_); _i_++) \
+ ((volatile CYG_WORD32 *)(_register_))[_i_] = (_buf_)[_i_]; \
+ CYG_MACRO_END
+
+
+#define HAL_IO_MACROS_DEFINED
+
+#endif // !HAL_IO_MACROS_DEFINED
+
+// Enforce a flow "barrier" to prevent optimizing compiler from reordering
+// operations.
+#define HAL_IO_BARRIER()
+
+//-----------------------------------------------------------------------------
+#endif // ifndef CYGONCE_HAL_IO_H
+// End of hal_io.h
diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/src/context.S b/zpu/sw/ecos/repository/hal/zylin/arch/current/src/context.S
new file mode 100644
index 0000000..6b0b833
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/src/context.S
@@ -0,0 +1,324 @@
+// #===========================================================================
+// #
+// # context.S
+// #
+// # ZYLIN context switch code
+// #
+// #===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+// #===========================================================================
+// ######DESCRIPTIONBEGIN####
+// #
+// # Author(s): nickg, gthomas
+// # Contributors: nickg, gthomas
+// # Date: 1998-09-15
+// # Purpose: ZYLIN context switch code
+// # Description: This file contains implementations of the thread context
+// # switch routines. It also contains the longjmp() and setjmp()
+// # routines.
+// #
+// #####DESCRIPTIONEND####
+// #
+// #===========================================================================
+
+#include <pkgconf/hal.h>
+#ifdef CYGPKG_KERNEL // no CDL yet
+#include <pkgconf/kernel.h>
+#else
+# undef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
+# undef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
+#endif
+
+
+
+
+#include "zylin.inc"
+
+ .text
+
+
+;; By using a macro, we get multiple breakpoint sites
+ .macro LOAD_STATE
+ popsp
+ ; stack pointer now points to beginning of HAL_SavedRegisters
+ ; we now pop the state of the CPU
+
+ ; this will restore r0-r3
+ im 0
+ store
+ im 4
+ store
+ im 8
+ store
+ im 12
+ store
+ im 16
+ store
+ im 20
+ store
+ im 24
+ store
+ im 28
+ store
+
+ ;; restore interrupts
+ im INTERRUPT_MASK
+ load
+ store
+
+
+ .endm
+
+
+// ----------------------------------------------------------------------------
+// hal_thread_switch_context
+// Switch thread contexts
+
+
+ .globl hal_thread_switch_context
+hal_thread_switch_context:
+
+ ;; save interrupt state
+ im INTERRUPT_MASK
+ load
+ load
+
+ ; store current state on stack
+ im 28
+ load
+ im 24
+ load
+ im 20
+ load
+ im 16
+ load
+ im 12
+ load
+ im 8
+ load
+ im 4
+ load
+ im 0
+ load
+
+
+ ;; store pointer to SP in "from" pointer
+ pushsp
+ pushsp
+ im 8+8*4+4+4
+ add
+ load
+ store
+
+ ;; put pointer to '*to' on stack
+ pushsp
+ im 4+8*4+4
+ add
+ load
+ load
+
+ LOAD_STATE
+
+ poppc ; voila! jump to saved pc
+
+
+
+
+// ----------------------------------------------------------------------------
+// hal_thread_load_context
+// Load thread context
+
+ .globl hal_thread_load_context
+hal_thread_load_context:
+ pushsp
+ im 4
+ add
+ load
+ load ; pointer to HAL_SavedRegisters on stack
+
+load_state_internal:
+ LOAD_STATE
+
+ poppc ; voila! jump to saved pc
+
+// ----------------------------------------------------------------------------
+// HAL longjmp, setjmp implementations
+
+ .globl hal_setjmp
+hal_setjmp:
+ .byte 0
+
+
+ .globl hal_longjmp
+ hal_longjmp:
+ .byte 0
+
+// ----------------------------------------------------------------------------
+// end of context.S
+
+#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
+
+ ; push 1 onto stack if we're already switched, 0 otherwise
+ .macro check_thread_stack
+ pushsp ; 0xda68
+ im __interrupt_stack ; 0x241a
+ lessthan ; => 1
+ im __interrupt_stack_base
+ pushsp
+ lessthan
+ or
+
+ .endm
+
+ ; push 1 onto stack if we're already switched, 0 otherwise
+ .macro switch_stack
+ pushsp
+ im __interrupt_stack-4
+ store ; saved stack pointer on interrupt stack.
+
+ im __interrupt_stack-4
+ popsp
+ ; we're now on the interrupt stack
+
+ .endm
+
+ .macro switch_stack_back
+ ; return to thread stack
+ popsp
+ .endm
+
+_zpu_invoke_zpu_interrupt_stack:
+ im hal_IRQ_handler
+ call
+ im 0
+ load ; return value - source
+
+ im _zpu_interrupt_stack
+ call
+ im 0
+ load ; return value - result
+
+ ; we've got source and ISR result args on the stack
+ im _zpu_interrupt_thread
+ call
+ storesp 0 ; destroy args
+ storesp 0
+
+ poppc
+
+
+// switch to interrupt stack, invoke interrupt handler, switch back to original stack, enable interrupts
+ .globl _zpu_interrupt
+_zpu_interrupt:
+ ; disable interrupts, we don't nest
+ im 1
+ nop
+ im INTERRUPT_MASK
+ load
+ store
+
+ ; if we're interrupting the DSRs then
+ ; we're already on the interrupt stack
+ check_thread_stack
+
+ impcrel _already_switched
+ eqbranch
+
+_zpu_interrupt_switch_stack:
+ switch_stack
+
+ im _zpu_invoke_zpu_interrupt_stack
+ call
+
+ switch_stack_back
+
+ im .already_switched2
+ poppc
+
+_already_switched:
+ im _zpu_invoke_zpu_interrupt_stack
+ call
+
+.already_switched2:
+ ; turn on interrupts and run on thread stack.
+ im 0
+ nop
+ im INTERRUPT_MASK
+ load
+ store ; unmask interrupts
+
+ ; we're now running on thread stack
+
+ im _zpu_interrupt_thread
+ call
+
+ poppc
+
+ .globl hal_interrupt_stack_call_pending_DSRs
+hal_interrupt_stack_call_pending_DSRs:
+ ; the scheduler is not running, so only interrupts
+ ; could have switched stacks at this point and
+ ; since we're running, interrupts are not
+ switch_stack
+
+ im cyg_interrupt_call_pending_DSRs
+ call
+
+ switch_stack_back
+
+ ; back on thread stack
+ poppc
+
+
+
+
+// Runtime stack used during all interrupt processing
+#ifndef CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+#define CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE 4096
+#endif
+ .bss
+ .balign 4,0
+ .global cyg_interrupt_stack_base
+cyg_interrupt_stack_base:
+__interrupt_stack_base:
+ .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+ .byte 0
+ .endr
+ .balign 4,0
+ .global cyg_interrupt_stack
+cyg_interrupt_stack:
+__interrupt_stack:
+#endif
+
+
diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/src/hal_misc.c b/zpu/sw/ecos/repository/hal/zylin/arch/current/src/hal_misc.c
new file mode 100644
index 0000000..eea2465
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/src/hal_misc.c
@@ -0,0 +1,177 @@
+/*==========================================================================
+//
+// hal_misc.c
+//
+// HAL miscellaneous functions
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): nickg, gthomas
+// Contributors: nickg, gthomas
+// Date: 1999-02-20
+// Purpose: HAL miscellaneous functions
+// Description: This file contains miscellaneous functions provided by the
+// HAL.
+//
+//####DESCRIPTIONEND####
+//
+//=========================================================================*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_zylin.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+#ifdef CYGPKG_CYGMON
+#include <pkgconf/cygmon.h>
+#endif
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_arch.h> // HAL header
+#include <cyg/hal/hal_intr.h> // HAL header
+
+#include <cyg/hal/var_io.h>
+#include <cyg/hal/hal_io.h>
+
+externC void diag_printf(const char *fmt, ...);
+
+/*------------------------------------------------------------------------*/
+/* First level C exception handler. */
+
+
+/*------------------------------------------------------------------------*/
+/* C++ support - run initial constructors */
+
+#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG
+cyg_bool cyg_hal_stop_constructors;
+#endif
+
+typedef void (*pfunc) (void);
+extern pfunc __CTOR_LIST__[];
+extern pfunc __CTOR_END__[];
+
+void
+cyg_hal_invoke_constructors (void)
+{
+#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG
+ static pfunc *p = &__CTOR_END__[-1];
+
+ cyg_hal_stop_constructors = 0;
+ for (; p >= __CTOR_LIST__; p--) {
+ (*p) ();
+ if (cyg_hal_stop_constructors) {
+ p--;
+ break;
+ }
+ }
+#else
+ pfunc *p;
+
+ for (p = &__CTOR_END__[-1]; p >= __CTOR_LIST__; p--)
+ (*p) ();
+#endif
+}
+
+
+/*-------------------------------------------------------------------------*/
+/* Misc functions */
+
+int
+hal_lsbindex(int mask)
+{
+ int i;
+ for (i = 0; i < 32; i++) {
+ if (mask & (1<<i)) return (i);
+ }
+ return (-1);
+}
+
+int
+hal_msbindex(int mask)
+{
+ int i;
+ for (i = 31; i >= 0; i--) {
+ if (mask & (1<<i)) return (i);
+ }
+ return (-1);
+}
+
+/*------------------------------------------------------------------------*/
+/* Architecture default ISR */
+
+externC cyg_uint32
+hal_arch_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data)
+{
+ CYG_TRACE1(true, "Interrupt: %d", vector);
+
+ CYG_FAIL("Spurious Interrupt!!!");
+ return 0;
+}
+
+extern volatile int *INTERRUPT_MASK;
+
+cyg_uint32 zpu_disable_interrupts()
+{
+ /* NOTE! We disable interrupts before flipping the cached state */
+ cyg_uint32 t=*INTERRUPT_MASK;
+ *INTERRUPT_MASK=1;
+ return t;
+}
+
+void zpu_enable_interrupts()
+{
+ *INTERRUPT_MASK=0;
+}
+
+void zpu_restore_interrupts(cyg_uint32 t)
+{
+ if (t==0)
+ zpu_enable_interrupts();
+ else
+ zpu_disable_interrupts();
+}
+
+externC cyg_uint32 zpu_query_interrupts()
+{
+ return *INTERRUPT_MASK;
+}
+
+/*------------------------------------------------------------------------*/
+// EOF hal_misc.c
diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/src/hal_mk_defs.c b/zpu/sw/ecos/repository/hal/zylin/arch/current/src/hal_mk_defs.c
new file mode 100644
index 0000000..734ce65
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/src/hal_mk_defs.c
@@ -0,0 +1,102 @@
+/*==========================================================================
+//
+// hal_mk_defs.c
+//
+// HAL (architecture) "make defs" program
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): gthomas
+// Contributors: gthomas
+// Date: 1999-02-20
+// Purpose: ZYLIN architecture dependent definition generator
+// Description: This file contains code that can be compiled by the target
+// compiler and used to generate machine specific definitions
+// suitable for use in assembly code.
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+
+#include <cyg/hal/hal_arch.h> // HAL header
+#include <cyg/hal/hal_intr.h> // HAL header
+#ifdef CYGPKG_KERNEL
+# include <pkgconf/kernel.h>
+# include <cyg/kernel/instrmnt.h>
+#endif
+#include <cyg/hal/hal_if.h>
+
+/*
+ * This program is used to generate definitions needed by
+ * assembly language modules.
+ *
+ * This technique was first used in the OSF Mach kernel code:
+ * generate asm statements containing #defines,
+ * compile this file to assembler, and then extract the
+ * #defines from the assembly-language output.
+ */
+
+#define DEFINE(sym, val) \
+ asm volatile("\n\t.equ\t" #sym ",%0" : : "i" (val))
+
+int
+main(void)
+{
+ DEFINE(CYGNUM_HAL_ISR_COUNT, CYGNUM_HAL_ISR_COUNT);
+ DEFINE(CYGNUM_HAL_VSR_COUNT, CYGNUM_HAL_VSR_COUNT);
+ DEFINE(CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION,
+ CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION);
+ DEFINE(CYGNUM_HAL_EXCEPTION_CODE_ACCESS,
+ CYGNUM_HAL_EXCEPTION_CODE_ACCESS);
+ DEFINE(CYGNUM_HAL_EXCEPTION_DATA_ACCESS,
+ CYGNUM_HAL_EXCEPTION_DATA_ACCESS);
+ DEFINE(CYGNUM_HAL_VECTOR_IRQ, CYGNUM_HAL_VECTOR_IRQ);
+#ifdef CYGPKG_KERNEL
+ DEFINE(RAISE_INTR, CYG_INSTRUMENT_CLASS_INTR|CYG_INSTRUMENT_EVENT_INTR_RAISE);
+#endif
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT)
+ DEFINE(CYGNUM_CALL_IF_TABLE_SIZE, CYGNUM_CALL_IF_TABLE_SIZE);
+#endif
+ DEFINE(CYGNUM_HAL_INTERRUPT_NONE, CYGNUM_HAL_INTERRUPT_NONE);
+ return 0;
+}
+
+
+/*------------------------------------------------------------------------*/
+// EOF hal_mk_defs.c
diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/src/vectors.c b/zpu/sw/ecos/repository/hal/zylin/arch/current/src/vectors.c
new file mode 100644
index 0000000..b254a85
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/src/vectors.c
@@ -0,0 +1,116 @@
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_zylin.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+#ifdef CYGPKG_CYGMON
+#include <pkgconf/cygmon.h>
+#endif
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_arch.h> // HAL header
+#include <cyg/hal/hal_intr.h> // HAL header
+#include <string.h>
+#include <cyg/hal/hal_arch.h> // Register state info
+
+extern char __bss_start[];
+extern char __bss_end[];
+
+externC void cyg_hal_invoke_constructors (void);
+externC void cyg_start (void);
+externC void hal_hardware_init (void);
+externC void _initIO();
+
+void _premain(void)
+{
+ // clear BSS
+ memset(__bss_start, 0, __bss_end-__bss_start);
+
+ _initIO();
+
+ hal_hardware_init();
+
+ cyg_hal_invoke_constructors();
+
+ cyg_start();
+
+ __asm("breakpoint"); // stop debugger/sim here for now
+// for (;;); // hang forever
+}
+
+CYG_ADDRWORD hal_vsr_table[CYGNUM_HAL_VSR_COUNT];
+CYG_ADDRWORD hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
+CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];
+CYG_ADDRWORD hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];
+
+externC cyg_ucount32 cyg_scheduler_sched_lock;
+externC cyg_uint32 hal_IRQ_handler();
+
+externC void interrupt_end(
+ cyg_uint32 isr_ret,
+ CYG_ADDRWORD intr,
+ HAL_SavedRegisters *ctx
+ );
+
+
+#ifndef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
+
+
+void _zpu_interrupt(void)
+{
+ cyg_uint32 source;
+#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
+ cyg_scheduler_sched_lock++;
+#endif
+ /* we don't support reentrant interrupts, so we disable interrupts here. */
+ cyg_uint32 t;
+ HAL_DISABLE_INTERRUPTS(t);
+
+ source=hal_IRQ_handler();
+ if (source!=CYGNUM_HAL_INTERRUPT_NONE)
+ {
+
+ cyg_uint32 result;
+
+ result=((cyg_uint32 (*)(cyg_uint32, CYG_ADDRWORD))hal_interrupt_handlers[source])(source, hal_interrupt_data[source]);
+ /* restore interrupts again. */
+ HAL_ENABLE_INTERRUPTS();
+ /* Interrupts must be enabled here as the scheduler is invoked here. */
+ interrupt_end(result, hal_interrupt_objects[source], NULL);
+ } else
+ {
+ /* restore interrupts again. */
+ HAL_ENABLE_INTERRUPTS();
+ }
+}
+#else
+/* low-level interrupt handling routine */
+cyg_uint32 _zpu_interrupt_stack(cyg_uint32 source)
+{
+#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
+ cyg_scheduler_sched_lock++;
+#endif
+ /* we don't support reentrant interrupts, so we disable interrupts here. */
+ cyg_uint32 t;
+ HAL_DISABLE_INTERRUPTS(t);
+
+ cyg_uint32 result=0;
+ if (source!=CYGNUM_HAL_INTERRUPT_NONE)
+ {
+ cyg_uint32 result;
+ result=((cyg_uint32 (*)(cyg_uint32, CYG_ADDRWORD))hal_interrupt_handlers[source])(source, hal_interrupt_data[source]);
+ }
+ return result;
+}
+void _zpu_interrupt_thread(cyg_uint32 source, cyg_uint32 result)
+{
+ if (source!=CYGNUM_HAL_INTERRUPT_NONE)
+ {
+ /* Interrupts must be enabled here as the scheduler is invoked here. */
+ interrupt_end(result, hal_interrupt_objects[source], NULL);
+ }
+}
+#endif
diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/src/zylin.ld b/zpu/sw/ecos/repository/hal/zylin/arch/current/src/zylin.ld
new file mode 100644
index 0000000..eef2cd7
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/src/zylin.ld
@@ -0,0 +1,226 @@
+//=============================================================================
+//
+// MLT linker script for ZYLIN
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+
+#include <pkgconf/system.h>
+
+STARTUP(crt0.o)
+ENTRY(_start)
+INPUT(crt_io.o)
+INPUT(extras.o)
+INPUT(vectors.o)
+GROUP(libtarget.a libgcc.a libsupc++.a)
+
+// Keep RODATA in separate sections.
+#define MERGE_IN_RODATA
+
+#define ALIGN_LMA 4
+#define FOLLOWING(_section_) AT ((LOADADDR (_section_) + SIZEOF (_section_) + ALIGN_LMA - 1) & ~ (ALIGN_LMA - 1))
+#define LMA_EQ_VMA
+#define FORCE_OUTPUT . = .
+
+#define SECTIONS_BEGIN
+
+#define SECTION_fixed_vectors(_region_, _vma_, _lma_) \
+ .fixed_vectors _vma_ : _lma_ \
+ { FORCE_OUTPUT; KEEP (*(.fixed_vectors)) } \
+ > _region_
+
+#define SECTION_rom_vectors(_region_, _vma_, _lma_) \
+ .rom_vectors _vma_ : _lma_ \
+ { __rom_vectors_vma = ABSOLUTE(.); \
+ FORCE_OUTPUT; KEEP (*(.vectors)) } \
+ > _region_ \
+ __rom_vectors_lma = LOADADDR(.rom_vectors);
+
+#define SECTION_text(_region_, _vma_, _lma_) \
+ .text _vma_ : _lma_ \
+ { _stext = ABSOLUTE(.); \
+ PROVIDE (__stext = ABSOLUTE(.)); \
+ *(.text*) *(.gnu.warning) *(.gnu.linkonce.t.*) *(.init) \
+ *(.glue_7) *(.glue_7t) \
+ } > _region_ \
+ _etext = .; PROVIDE (__etext = .);
+
+#define SECTION_fini(_region_, _vma_, _lma_) \
+ .fini _vma_ : _lma_ \
+ { FORCE_OUTPUT; *(.fini) } \
+ > _region_
+
+#define SECTION_rodata(_region_, _vma_, _lma_) \
+ .rodata _vma_ : _lma_ \
+ { FORCE_OUTPUT; *(.rodata*) *(.gnu.linkonce.r.*) } \
+ > _region_
+
+#define SECTION_rodata1(_region_, _vma_, _lma_) \
+ .rodata1 _vma_ : _lma_ \
+ { FORCE_OUTPUT; *(.rodata1) } \
+ > _region_
+
+#define SECTION_fixup(_region_, _vma_, _lma_) \
+ .fixup _vma_ : _lma_ \
+ { FORCE_OUTPUT; *(.fixup) } \
+ > _region_
+
+#define SECTION_gcc_except_table(_region_, _vma_, _lma_) \
+ .gcc_except_table _vma_ : _lma_ \
+ { FORCE_OUTPUT; *(.gcc_except_table) } \
+ > _region_
+
+#define SECTION_eh_frame(_region_, _vma_, _lma_) \
+ .eh_frame _vma_ : _lma_ \
+ { \
+ FORCE_OUTPUT; __EH_FRAME_BEGIN__ = .; \
+ KEEP(*(.eh_frame)) \
+ __FRAME_END__ = .; \
+ . = . + 8; \
+ } > _region_ = 0
+
+#define SECTION_RELOCS(_region_, _vma_, _lma_) \
+ .rel.text : \
+ { \
+ *(.rel.text) \
+ *(.rel.text.*) \
+ *(.rel.gnu.linkonce.t*) \
+ } > _region_ \
+ .rela.text : \
+ { \
+ *(.rela.text) \
+ *(.rela.text.*) \
+ *(.rela.gnu.linkonce.t*) \
+ } > _region_ \
+ .rel.data : \
+ { \
+ *(.rel.data) \
+ *(.rel.data.*) \
+ *(.rel.gnu.linkonce.d*) \
+ } > _region_ \
+ .rela.data : \
+ { \
+ *(.rela.data) \
+ *(.rela.data.*) \
+ *(.rela.gnu.linkonce.d*) \
+ } > _region_ \
+ .rel.rodata : \
+ { \
+ *(.rel.rodata) \
+ *(.rel.rodata.*) \
+ *(.rel.gnu.linkonce.r*) \
+ } > _region_ \
+ .rela.rodata : \
+ { \
+ *(.rela.rodata) \
+ *(.rela.rodata.*) \
+ *(.rela.gnu.linkonce.r*) \
+ } > _region_ \
+ .rel.got : { *(.rel.got) } > _region_ \
+ .rela.got : { *(.rela.got) } > _region_ \
+ .rel.ctors : { *(.rel.ctors) } > _region_ \
+ .rela.ctors : { *(.rela.ctors) } > _region_ \
+ .rel.dtors : { *(.rel.dtors) } > _region_ \
+ .rela.dtors : { *(.rela.dtors) } > _region_ \
+ .rel.init : { *(.rel.init) } > _region_ \
+ .rela.init : { *(.rela.init) } > _region_ \
+ .rel.fini : { *(.rel.fini) } > _region_ \
+ .rela.fini : { *(.rela.fini) } > _region_ \
+ .rel.bss : { *(.rel.bss) } > _region_ \
+ .rela.bss : { *(.rela.bss) } > _region_ \
+ .rel.plt : { *(.rel.plt) } > _region_ \
+ .rela.plt : { *(.rela.plt) } > _region_ \
+ .rel.dyn : { *(.rel.dyn) } > _region_
+
+#define SECTION_got(_region_, _vma_, _lma_) \
+ .got _vma_ : _lma_ \
+ { \
+ FORCE_OUTPUT; *(.got.plt) *(.got) \
+ _GOT1_START_ = ABSOLUTE (.); *(.got1) _GOT1_END_ = ABSOLUTE (.); \
+ _GOT2_START_ = ABSOLUTE (.); *(.got2) _GOT2_END_ = ABSOLUTE (.); \
+ } > _region_
+
+#define SECTION_mmu_tables(_region_, _vma_, _lma_) \
+ .mmu_tables _vma_ : _lma_ \
+ { FORCE_OUTPUT; *(.mmu_tables) } \
+ > _region_
+
+#define SECTION_sram(_region_, _vma_, _lma_) \
+ .sram _vma_ : _lma_ \
+ { FORCE_OUTPUT; *(.sram*) } \
+ > _region_
+
+#define SECTION_data(_region_, _vma_, _lma_) \
+ .data _vma_ : _lma_ \
+ { __ram_data_start = ABSOLUTE (.); \
+ *(.data*) *(.data1) *(.gnu.linkonce.d.*) MERGE_IN_RODATA \
+ . = ALIGN (4); \
+ KEEP(*( SORT (.ecos.table.*))) ; \
+ . = ALIGN (4); \
+ __CTOR_LIST__ = ABSOLUTE (.); KEEP (*(SORT (.ctors*))) __CTOR_END__ = ABSOLUTE (.); \
+ __DTOR_LIST__ = ABSOLUTE (.); KEEP (*(SORT (.dtors*))) __DTOR_END__ = ABSOLUTE (.); \
+ *(.dynamic) *(.sdata*) *(.gnu.linkonce.s.*) \
+ . = ALIGN (4); *(.2ram.*) } \
+ > _region_ \
+ __rom_data_start = LOADADDR (.data); \
+ __ram_data_end = .; PROVIDE (__ram_data_end = .); _edata = .; PROVIDE (edata = .); \
+ PROVIDE (__rom_data_end = LOADADDR (.data) + SIZEOF(.data));
+
+#define SECTION_bss(_region_, _vma_, _lma_) \
+ .bss _vma_ : _lma_ \
+ { __bss_start = ABSOLUTE (.); \
+ *(.scommon) *(.dynsbss) *(.sbss*) *(.gnu.linkonce.sb.*) \
+ *(.dynbss) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON) \
+ __bss_end = ABSOLUTE (.); } \
+ > _region_
+
+// Some versions of gcc define "zpu" which causes problems with .note.arm.ident
+#undef zpu
+#define SECTIONS_END . = ALIGN(4); _end = .; PROVIDE (end = .); \
+ /* Debug information */ \
+ .debug_aranges 0 : { *(.debug_aranges) } \
+ .debug_pubnames 0 : { *(.debug_pubnames) } \
+ .debug_info 0 : { *(.debug_info) } \
+ .debug_abbrev 0 : { *(.debug_abbrev) } \
+ .debug_line 0 : { *(.debug_line) } \
+ .debug_frame 0 : { *(.debug_frame) } \
+ .debug_str 0 : { *(.debug_str) } \
+ .debug_loc 0 : { *(.debug_loc) } \
+ .debug_macinfo 0 : { *(.debug_macinfo) } \
+ .note.gnu.zpu.ident 0 : { KEEP (*(.note.gnu.zpu.ident)) }
+
+
+#include <pkgconf/hal_zylin.h>
+#include CYGHWR_MEMORY_LAYOUT_LDI
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/ChangeLog b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/ChangeLog
new file mode 100644
index 0000000..a29dbf8
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/ChangeLog
@@ -0,0 +1,39 @@
+2004-09-16 Øyvind Harboe <oyvind.harboe@zylin.com>
+
+ * first cut HAL support for ZPU
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/cdl/hal_zylin_zpu_abel.cdl b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/cdl/hal_zylin_zpu_abel.cdl
new file mode 100644
index 0000000..f5c2f81
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/cdl/hal_zylin_zpu_abel.cdl
@@ -0,0 +1,298 @@
+# ====================================================================
+#
+# hal_zpu.cdl
+#
+# ZPU HAL package configuration data
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):
+# Contributors:
+# Date: 2001-07-12
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_HAL_ZYLIN_ZPU_ABEL {
+ display "Zylin ZPU HAL"
+ parent CYGPKG_HAL_ZYLIN_ZPU
+ define_header hal_zylin_zpu_abel.h
+ include_dir cyg/hal
+ hardware
+ description "
+ The Zylin ZPU HAL package provides the support needed to run
+ eCos on an Zylin ZPU board using the Abel board."
+
+ compile abel_misc.c
+
+ requires { CYGHWR_HAL_ZYLIN_ZPU == "ZPU1" }
+
+ define_proc {
+ puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_zylin.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_zylin_zpu.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_zylin_zpu_abel.h>"
+ puts $::cdl_header "#define HAL_PLATFORM_CPU \"ZPU1\""
+ puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Zylin Abel\""
+ puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\""
+ }
+
+ # Real-time clock/counter specifics
+ cdl_option CYGNUM_HAL_ZYLIN_ZPU_CLOCK_SPEED {
+ display "CPU clock speed"
+ flavor data
+ default_value 90000000
+ }
+
+ cdl_component CYGNUM_HAL_RTC_CONSTANTS {
+ display "Real-time clock constants"
+ flavor none
+
+ cdl_option CYGNUM_HAL_RTC_NUMERATOR {
+ display "Real-time clock numerator"
+ flavor data
+ default_value 1000000000
+ }
+ cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
+ display "Real-time clock denominator"
+ flavor data
+ default_value 100
+ }
+ cdl_option CYGNUM_HAL_RTC_PERIOD {
+ display "Real-time clock period"
+ flavor data
+ default_value (CYGNUM_HAL_ZYLIN_ZPU_CLOCK_SPEED / CYGNUM_HAL_RTC_DENOMINATOR)
+ }
+ }
+
+
+ cdl_component CYG_HAL_STARTUP {
+ display "Startup type"
+ flavor data
+ default_value {"RAM"}
+ legal_values {"RAM"}
+ no_define
+ define -file system.h CYG_HAL_STARTUP
+ description "
+ When targetting the ZPU board it is possible to build
+ the system for either RAM bootstrap or ROM bootstrap(s). Select
+ 'ram' when building programs to load into RAM using onboard
+ debug software such as Angel or eCos GDB stubs. Select 'rom'
+ when building a stand-alone application which will be put
+ into ROM. Using ROMRAM will allow the program to exist in
+ ROM, but be copied to RAM during startup."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+ display "Number of communication channels on the board"
+ flavor data
+ calculated 1
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+ display "Debug serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value 0
+ description "
+ This option
+ chooses which port will be used to connect to a host
+ running GDB."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+ display "Diagnostic serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value 0
+ description "
+ This option
+ chooses which port will be used for diagnostic output."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+ display "Diagnostic serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 57600 115200
+ default_value 38400
+ description "
+ This option selects the baud rate used for the diagnostic port."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+ display "GDB serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 57600 115200
+ default_value 38400
+ description "
+ This option controls the baud rate used for the GDB connection."
+ }
+
+ cdl_option CYGSEM_HAL_ROM_MONITOR {
+ display "Behave as a ROM monitor"
+ flavor bool
+ default_value 0
+ parent CYGPKG_HAL_ROM_MONITOR
+ requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" }
+ description "
+ Enable this option if this program is to be used as a ROM monitor,
+ i.e. applications will be loaded into RAM on the board, and this
+ ROM monitor may process exceptions or interrupts generated from the
+ application. This enables features such as utilizing a separate
+ interrupt stack when exceptions are generated."
+ }
+
+ cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+ display "Work with a ROM monitor"
+ flavor booldata
+ legal_values { "Generic" }
+ default_value { 0 }
+ parent CYGPKG_HAL_ROM_MONITOR
+ requires { CYG_HAL_STARTUP == "RAM" }
+ description "
+ Support can be enabled for different varieties of ROM monitor.
+ This support changes various eCos semantics such as the encoding
+ of diagnostic output, or the overriding of hardware interrupt
+ vectors.
+ Firstly there is \"Generic\" support which prevents the HAL
+ from overriding the hardware vectors that it does not use, to
+ instead allow an installed ROM monitor to handle them. This is
+ the most basic support which is likely to be common to most
+ implementations of ROM monitor.
+ \"GDB_stubs\" provides support when GDB stubs are included in
+ the ROM monitor or boot ROM."
+ }
+
+ cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
+ display "Redboot HAL options"
+ flavor none
+ no_define
+ parent CYGPKG_REDBOOT
+ active_if CYGPKG_REDBOOT
+ description "
+ This option lists the target's requirements for a valid Redboot
+ configuration."
+
+ cdl_option CYGBLD_BUILD_REDBOOT_BIN {
+ display "Build Redboot ROM binary image"
+ active_if CYGBLD_BUILD_REDBOOT
+ default_value 1
+ no_define
+ description "This option enables the conversion of the Redboot ELF
+ image to a binary image suitable for ROM programming."
+
+ make -priority 325 {
+ <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
+ $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
+ $(OBJCOPY) -O srec $< $(@:.bin=.srec)
+ $(OBJCOPY) -O binary $< $@
+ }
+
+ }
+ }
+
+ cdl_component CYGBLD_GLOBAL_OPTIONS {
+ display "Global build options"
+ flavor none
+ parent CYGPKG_NONE
+ description "
+ Global build options including control over
+ compiler flags, linker flags and choice of toolchain."
+
+
+ cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+ display "Global command prefix"
+ flavor data
+ no_define
+ default_value { "zpu-elf" }
+ description "
+ This option specifies the command prefix used when
+ invoking the build tools."
+ }
+
+ cdl_option CYGBLD_GLOBAL_CFLAGS {
+ display "Global compiler flags"
+ flavor data
+ no_define
+ default_value { "-Wall -Wpointer-arith -Winline -Wundef -g -Os -ffunction-sections -fdata-sections -fno-exceptions -finit-priority -abel" }
+ description "
+ This option controls the global compiler flags which are used to
+ compile all packages by default. Individual packages may define
+ options which override these global flags."
+ }
+
+ cdl_option CYGBLD_GLOBAL_LDFLAGS {
+ display "Global linker flags"
+ flavor data
+ no_define
+ default_value { "-Wl,--gc-sections -Wl,-static -g -nostdlib -abel -Wl,--relax -Os" }
+ description "
+ This option controls the global linker flags. Individual
+ packages may define options which override these global flags."
+ }
+ }
+
+ cdl_component CYGHWR_MEMORY_LAYOUT {
+ display "Memory layout"
+ flavor data
+ no_define
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "zpu_ram" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "zpu_romram" :
+ "zpu_rom" }
+
+ cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+ display "Memory layout linker script fragment"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_zylin_zpu_abel_ram.ldi>" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_zylin_zpu_abel_romram.ldi>" :
+ "<pkgconf/mlt_zylin_zpu_abel_rom.ldi>" }
+ }
+
+ cdl_option CYGHWR_MEMORY_LAYOUT_H {
+ display "Memory layout header file"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_H
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_zylin_zpu_abel_ram.h>" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_zylin_zpu_abel_romram.h>" :
+ "<pkgconf/mlt_zylin_zpu_abel_rom.h>" }
+ }
+ }
+}
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/hal_platform_ints.h b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/hal_platform_ints.h
new file mode 100644
index 0000000..9ff0029
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/hal_platform_ints.h
@@ -0,0 +1,79 @@
+#ifndef CYGONCE_HAL_PLATFORM_INTS_H
+#define CYGONCE_HAL_PLATFORM_INTS_H
+//==========================================================================
+//
+// hal_platform_ints.h
+//
+// HAL Interrupt and clock assignments for ZPU
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): gthomas
+// Contributors: gthomas
+// Date: 2001-07-12
+// Purpose: Define Interrupt support
+// Description: The interrupt specifics for the ZPU board/platform are
+// defined here.
+//
+// Usage: #include <cyg/hal/hal_platform_ints.h>
+// ...
+//
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#define CYGNUM_HAL_INTERRUPT_TIMER 0
+
+#define CYGNUM_HAL_ISR_MIN 0
+
+#define CYGNUM_HAL_ISR_MAX 0
+
+#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX + 1)
+
+// The vector used by the Real time clock
+#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER
+
+
+//----------------------------------------------------------------------------
+// Reset.
+__externC void hal_zpu_reset_cpu(void);
+#define HAL_PLATFORM_RESET() hal_zpu_reset_cpu()
+
+
+
+#endif // CYGONCE_HAL_PLATFORM_INTS_H
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/pkgconf/mlt_zylin_zpu_abel_ram.h b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/pkgconf/mlt_zylin_zpu_abel_ram.h
new file mode 100644
index 0000000..4d31221
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/pkgconf/mlt_zylin_zpu_abel_ram.h
@@ -0,0 +1,17 @@
+// eCos memory layout - Mon Jul 23 11:49:04 2001
+
+// This is a generated file - do not edit
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x00000000)
+#define CYGMEM_REGION_ram_SIZE (0x00008000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE ((CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE) - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/pkgconf/mlt_zylin_zpu_abel_ram.ldi b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/pkgconf/mlt_zylin_zpu_abel_ram.ldi
new file mode 100644
index 0000000..9a50a17
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/pkgconf/mlt_zylin_zpu_abel_ram.ldi
@@ -0,0 +1,27 @@
+// eCos memory layout - Mon Jul 23 11:49:04 2001
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+ ram : ORIGIN = 0x00000000, LENGTH = 0x8000
+}
+
+SECTIONS
+{
+ SECTIONS_BEGIN
+ SECTION_fixed_vectors (ram, 0x0, LMA_EQ_VMA)
+ SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rom_vectors (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata1 (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA)
+ CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+ SECTIONS_END
+}
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/plf_io.h b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/plf_io.h
new file mode 100644
index 0000000..7e6a234
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/plf_io.h
@@ -0,0 +1,64 @@
+#ifndef CYGONCE_HAL_PLF_IO_H
+#define CYGONCE_HAL_PLF_IO_H
+//=============================================================================
+//
+// plf_io.h
+//
+// ZPU board specific registers
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): tkoeller
+// Contributors: tdrury
+// Date: 2002-06-22
+// Purpose: Zylin ZPU board specific registers
+// Description:
+// Usage: #include <cyg/hal/plf_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+/* cause an "interrupt" from the idle thread */
+
+void _zpu_interrupt(void);
+/* KLUDGE!!!! some linker problem with _zpu_interrupt() that I'll solve later */
+#define HAL_IDLE_THREAD_ACTION(_count_) ((void (*)())0x20)();
+
+//-----------------------------------------------------------------------------
+// end of plf_io.h
+#endif // CYGONCE_HAL_PLF_IO_H
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/misc/redboot_RAM.ecm b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/misc/redboot_RAM.ecm
new file mode 100644
index 0000000..04eae62
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/misc/redboot_RAM.ecm
@@ -0,0 +1,53 @@
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+ description "" ;
+ hardware zpu_board ;
+ template redboot ;
+ package -hardware CYGPKG_HAL_ZPU current ;
+ package -hardware CYGPKG_HAL_ZPU_CPU current ;
+ package -template CYGPKG_HAL current ;
+ package -template CYGPKG_INFRA current ;
+ package -template CYGPKG_REDBOOT current ;
+};
+
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+ user_value 0
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+ inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+ inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+ inferred_value 0 0
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+ user_value 1
+};
+
+cdl_option CYGOPT_REDBOOT_FIS {
+ user_value 0
+};
+
+cdl_component CYGSEM_REDBOOT_FLASH_CONFIG {
+ user_value 0
+};
+
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC {
+ user_value 0
+};
+
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/src/abel_misc.c b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/src/abel_misc.c
new file mode 100644
index 0000000..ed5a0e9
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/src/abel_misc.c
@@ -0,0 +1,61 @@
+//==========================================================================
+//
+// zpu_misc.c
+//
+// HAL misc board support code for Zylin ZPU board
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): gthomas
+// Contributors: gthomas, jskov, tkoeller, tdrury, nickg
+// Date: 2002-05-30
+// Purpose: HAL board support
+// Description: Implementations of HAL board interfaces
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/hal/hal_io.h> // low level i/o
+#include <cyg/hal/var_io.h> // common registers
+#include <cyg/hal/plf_io.h> // platform registers
+
+
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/ChangeLog b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/ChangeLog
new file mode 100644
index 0000000..a29dbf8
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/ChangeLog
@@ -0,0 +1,39 @@
+2004-09-16 Øyvind Harboe <oyvind.harboe@zylin.com>
+
+ * first cut HAL support for ZPU
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/cdl/hal_zylin_zpu_phi.cdl b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/cdl/hal_zylin_zpu_phi.cdl
new file mode 100644
index 0000000..d7b7234
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/cdl/hal_zylin_zpu_phi.cdl
@@ -0,0 +1,292 @@
+# ====================================================================
+#
+# hal_zpu.cdl
+#
+# ZPU HAL package configuration data
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):
+# Contributors:
+# Date: 2001-07-12
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_HAL_ZYLIN_ZPU_PHI {
+ display "Zylin ZPU HAL"
+ parent CYGPKG_HAL_ZYLIN_ZPU
+ define_header hal_zylin_zpu_phi.h
+ include_dir cyg/hal
+ hardware
+ description "
+ The Zylin ZPU HAL package provides the support needed to run
+ eCos on an Zylin ZPU board."
+
+ compile phi_misc.c
+
+ requires { CYGHWR_HAL_ZYLIN_ZPU == "ZPU1" }
+
+ define_proc {
+ puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_zylin.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_zylin_zpu.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_zylin_zpu_phi.h>"
+ puts $::cdl_header "#define HAL_PLATFORM_CPU \"ZPU1\""
+ puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Zylin Phi\""
+ puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\""
+ }
+
+ # Real-time clock/counter specifics
+ cdl_option CYGNUM_HAL_ZYLIN_ZPU_CLOCK_SPEED {
+ display "CPU clock speed"
+ flavor data
+ default_value 64000000
+ }
+
+ cdl_component CYGNUM_HAL_RTC_CONSTANTS {
+ display "Real-time clock constants"
+ flavor none
+
+ cdl_option CYGNUM_HAL_RTC_NUMERATOR {
+ display "Real-time clock numerator"
+ flavor data
+ default_value 1000000000
+ }
+ cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
+ display "Real-time clock denominator"
+ flavor data
+ default_value 100
+ description "How many times a second to invoke the timer interrupt, normally 100"
+ }
+ cdl_option CYGNUM_HAL_RTC_PERIOD {
+ display "Real-time clock period"
+ flavor data
+ default_value (CYGNUM_HAL_ZYLIN_ZPU_CLOCK_SPEED / CYGNUM_HAL_RTC_DENOMINATOR)
+ }
+ }
+
+
+ cdl_component CYG_HAL_STARTUP {
+ display "Startup type"
+ flavor data
+ default_value {"RAM"}
+ legal_values {"RAM"}
+ no_define
+ define -file system.h CYG_HAL_STARTUP
+ description "For now the eCosBoard only supports DRAM startup"
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+ display "Number of communication channels on the board"
+ flavor data
+ calculated 1
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+ display "Debug serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value 0
+ description "
+ This option
+ chooses which port will be used to connect to a host
+ running GDB."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+ display "Diagnostic serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value 0
+ description "
+ This option
+ chooses which port will be used for diagnostic output."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+ display "Diagnostic serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 57600 115200
+ default_value 38400
+ description "
+ This option selects the baud rate used for the diagnostic port."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+ display "GDB serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 57600 115200
+ default_value 38400
+ description "
+ This option controls the baud rate used for the GDB connection."
+ }
+
+ cdl_option CYGSEM_HAL_ROM_MONITOR {
+ display "Behave as a ROM monitor"
+ flavor bool
+ default_value 0
+ parent CYGPKG_HAL_ROM_MONITOR
+ requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" }
+ description "
+ Enable this option if this program is to be used as a ROM monitor,
+ i.e. applications will be loaded into RAM on the board, and this
+ ROM monitor may process exceptions or interrupts generated from the
+ application. This enables features such as utilizing a separate
+ interrupt stack when exceptions are generated."
+ }
+
+ cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+ display "Work with a ROM monitor"
+ flavor booldata
+ legal_values { "Generic" }
+ default_value { 0 }
+ parent CYGPKG_HAL_ROM_MONITOR
+ requires { CYG_HAL_STARTUP == "RAM" }
+ description "
+ Support can be enabled for different varieties of ROM monitor.
+ This support changes various eCos semantics such as the encoding
+ of diagnostic output, or the overriding of hardware interrupt
+ vectors.
+ Firstly there is \"Generic\" support which prevents the HAL
+ from overriding the hardware vectors that it does not use, to
+ instead allow an installed ROM monitor to handle them. This is
+ the most basic support which is likely to be common to most
+ implementations of ROM monitor.
+ \"GDB_stubs\" provides support when GDB stubs are included in
+ the ROM monitor or boot ROM."
+ }
+
+ cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
+ display "Redboot HAL options"
+ flavor none
+ no_define
+ parent CYGPKG_REDBOOT
+ active_if CYGPKG_REDBOOT
+ description "
+ This option lists the target's requirements for a valid Redboot
+ configuration."
+
+ cdl_option CYGBLD_BUILD_REDBOOT_BIN {
+ display "Build Redboot ROM binary image"
+ active_if CYGBLD_BUILD_REDBOOT
+ default_value 1
+ no_define
+ description "This option enables the conversion of the Redboot ELF
+ image to a binary image suitable for ROM programming."
+
+ make -priority 325 {
+ <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
+ $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
+ $(OBJCOPY) -O srec $< $(@:.bin=.srec)
+ $(OBJCOPY) -O binary $< $@
+ }
+
+ }
+ }
+
+ cdl_component CYGBLD_GLOBAL_OPTIONS {
+ display "Global build options"
+ flavor none
+ parent CYGPKG_NONE
+ description "
+ Global build options including control over
+ compiler flags, linker flags and choice of toolchain."
+
+
+ cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+ display "Global command prefix"
+ flavor data
+ no_define
+ default_value { "zpu-elf" }
+ description "
+ This option specifies the command prefix used when
+ invoking the build tools."
+ }
+
+ cdl_option CYGBLD_GLOBAL_CFLAGS {
+ display "Global compiler flags"
+ flavor data
+ no_define
+ default_value { "-Wall -Wpointer-arith -Winline -Wundef -g -Os -ffunction-sections -fdata-sections -fno-exceptions -phi" }
+ description "
+ This option controls the global compiler flags which are used to
+ compile all packages by default. Individual packages may define
+ options which override these global flags."
+ }
+
+ cdl_option CYGBLD_GLOBAL_LDFLAGS {
+ display "Global linker flags"
+ flavor data
+ no_define
+ default_value { "-Wl,--gc-sections -Wl,-static -g -nostdlib -phi -Wl,--relax -Os" }
+ description "
+ This option controls the global linker flags. Individual
+ packages may define options which override these global flags."
+ }
+ }
+
+ cdl_component CYGHWR_MEMORY_LAYOUT {
+ display "Memory layout"
+ flavor data
+ no_define
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "zpu_ram" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "zpu_romram" :
+ "zpu_rom" }
+
+ cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+ display "Memory layout linker script fragment"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_zylin_zpu_phi_ram.ldi>" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_zylin_zpu_phi_romram.ldi>" :
+ "<pkgconf/mlt_zylin_zpu_phi_rom.ldi>" }
+ }
+
+ cdl_option CYGHWR_MEMORY_LAYOUT_H {
+ display "Memory layout header file"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_H
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_zylin_zpu_phi_ram.h>" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_zylin_zpu_phi_romram.h>" :
+ "<pkgconf/mlt_zylin_zpu_phi_rom.h>" }
+ }
+ }
+}
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/hal_platform_ints.h b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/hal_platform_ints.h
new file mode 100644
index 0000000..1ec0475
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/hal_platform_ints.h
@@ -0,0 +1,81 @@
+#ifndef CYGONCE_HAL_PLATFORM_INTS_H
+#define CYGONCE_HAL_PLATFORM_INTS_H
+//==========================================================================
+//
+// hal_platform_ints.h
+//
+// HAL Interrupt and clock assignments for ZPU
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): gthomas
+// Contributors: gthomas
+// Date: 2001-07-12
+// Purpose: Define Interrupt support
+// Description: The interrupt specifics for the ZPU board/platform are
+// defined here.
+//
+// Usage: #include <cyg/hal/hal_platform_ints.h>
+// ...
+//
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#define CYGNUM_HAL_INTERRUPT_TIMER 0
+#define CYGNUM_HAL_INTERRUPT_UART 1
+#define CYGNUM_HAL_INTERRUPT_ETHERMAC 2
+
+#define CYGNUM_HAL_ISR_MIN 0
+
+#define CYGNUM_HAL_ISR_MAX 2
+
+#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX + 1)
+
+// The vector used by the Real time clock
+#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER
+
+
+//----------------------------------------------------------------------------
+// Reset.
+__externC void hal_zpu_reset_cpu(void);
+#define HAL_PLATFORM_RESET() hal_zpu_reset_cpu()
+
+
+
+#endif // CYGONCE_HAL_PLATFORM_INTS_H
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/pkgconf/mlt_zylin_zpu_phi_ram.h b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/pkgconf/mlt_zylin_zpu_phi_ram.h
new file mode 100644
index 0000000..165467f
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/pkgconf/mlt_zylin_zpu_phi_ram.h
@@ -0,0 +1,17 @@
+// eCos memory layout - Mon Jul 23 11:49:04 2001
+
+// This is a generated file - do not edit
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x00000000)
+#define CYGMEM_REGION_ram_SIZE (0x01ff0000) // 0x10000 as startup stack...
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE ((CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE) - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/pkgconf/mlt_zylin_zpu_phi_ram.ldi b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/pkgconf/mlt_zylin_zpu_phi_ram.ldi
new file mode 100644
index 0000000..ef5947c
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/pkgconf/mlt_zylin_zpu_phi_ram.ldi
@@ -0,0 +1,27 @@
+// eCos memory layout - Mon Jul 23 11:49:04 2001
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+ ram : ORIGIN = 0x00000000, LENGTH = 0x01ff0000 // 0x10000 as startup stack...
+}
+
+SECTIONS
+{
+ SECTIONS_BEGIN
+ SECTION_fixed_vectors (ram, 0x0, LMA_EQ_VMA)
+ SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rom_vectors (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata1 (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
+ CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+ SECTIONS_END
+}
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/plf_io.h b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/plf_io.h
new file mode 100644
index 0000000..1c6f53b
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/plf_io.h
@@ -0,0 +1,58 @@
+#ifndef CYGONCE_HAL_PLF_IO_H
+#define CYGONCE_HAL_PLF_IO_H
+//=============================================================================
+//
+// plf_io.h
+//
+// ZPU board specific registers
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): tkoeller
+// Contributors: tdrury
+// Date: 2002-06-22
+// Purpose: Zylin ZPU board specific registers
+// Description:
+// Usage: #include <cyg/hal/plf_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_io.h
+#endif // CYGONCE_HAL_PLF_IO_H
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/src/phi_misc.c b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/src/phi_misc.c
new file mode 100644
index 0000000..f7393f7
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/src/phi_misc.c
@@ -0,0 +1,72 @@
+//==========================================================================
+//
+// zpu_misc.c
+//
+// HAL misc board support code for Zylin ZPU board
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): gthomas
+// Contributors: gthomas, jskov, tkoeller, tdrury, nickg
+// Date: 2002-05-30
+// Purpose: HAL board support
+// Description: Implementations of HAL board interfaces
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/hal/hal_io.h> // low level i/o
+#include <cyg/hal/var_io.h> // common registers
+#include <cyg/hal/plf_io.h> // platform registers
+
+
+volatile int *INTERRUPT_MASK=(volatile int *)0x080a0020;
+
+volatile int *TIMER_PERIOD=(volatile int *)0x080a0034;
+volatile int *TIMER_INTERRUPT=(volatile int *)0x080a0030;
+volatile int *TIMER_ENABLE=(volatile int *)0x080a002c;
+volatile int *TIMER_COUNTER=(volatile int *)0x080a0038;
+volatile int *UART_INTERRUPT=(volatile int *)0x080a0028;
+volatile int *UART_ENABLE=(volatile int *)0x080a0024;
+
+
+
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/ChangeLog b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/ChangeLog
new file mode 100644
index 0000000..519b620
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/ChangeLog
@@ -0,0 +1,38 @@
+2004-12-05 Øyvind Harboe <oyvind.harboe@zylin.com>
+
+ * first cut ZPU HAL
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/cdl/hal_zylin_zpu.cdl b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/cdl/hal_zylin_zpu.cdl
new file mode 100644
index 0000000..8d96088
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/cdl/hal_zylin_zpu.cdl
@@ -0,0 +1,83 @@
+# ====================================================================
+#
+# hal_zpu.cdl
+#
+# Zylin ZPU HAL package configuration data
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s): gthomas
+# Contributors: gthomas, tkoeller, tdrury, nickg
+# Date: 2001-07-12
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_HAL_ZYLIN_ZPU {
+ display "Zylin ZPU variant HAL"
+ parent CYGPKG_HAL_ZYLIN
+ define_header hal_zylin_zpu.h
+ include_dir cyg/hal
+ hardware
+ description "
+ The ZPU HAL package provides the support needed to run
+ eCos on Zylin ZPU based targets."
+
+ compile hal_diag.c zpu_misc.c
+
+
+ # Let the architectural HAL see this variant's files
+ define_proc {
+ puts $::cdl_system_header "#define CYGBLD_HAL_ZPU_VAR_IO_H"
+ puts $::cdl_system_header "#define CYGBLD_HAL_ZPU_VAR_ARCH_H"
+ }
+
+ cdl_option CYGHWR_HAL_ZYLIN_ZPU {
+ display "ZPU variant used"
+ flavor data
+ default_value {"ZPU1"}
+ legal_values {"ZPU1"}
+ description "The ZPU microcontroller family has several variants,
+ the main differences being the amount of on-chip SRAM,
+ peripherals and their layout. This option allows the
+ platform HALs to select the specific microcontroller
+ being used."
+ }
+
+}
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/hal_cache.h b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/hal_cache.h
new file mode 100644
index 0000000..d3fef4f
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/hal_cache.h
@@ -0,0 +1,192 @@
+#ifndef CYGONCE_HAL_CACHE_H
+#define CYGONCE_HAL_CACHE_H
+
+//=============================================================================
+//
+// hal_cache.h
+//
+// HAL cache control API
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): nickg, gthomas
+// Contributors: nickg, gthomas
+// Date: 1998-09-28
+// Purpose: Cache control API
+// Description: The macros defined here provide the HAL APIs for handling
+// cache control operations.
+// Usage:
+// #include <cyg/hal/hal_cache.h>
+// ...
+//
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <cyg/infra/cyg_type.h>
+
+//-----------------------------------------------------------------------------
+// Cache dimensions
+
+// Data cache
+//#define HAL_DCACHE_SIZE 0 // Size of data cache in bytes
+//#define HAL_DCACHE_LINE_SIZE 0 // Size of a data cache line
+//#define HAL_DCACHE_WAYS 0 // Associativity of the cache
+
+// Instruction cache
+//#define HAL_ICACHE_SIZE 0 // Size of cache in bytes
+//#define HAL_ICACHE_LINE_SIZE 0 // Size of a cache line
+//#define HAL_ICACHE_WAYS 0 // Associativity of the cache
+
+//#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
+//#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
+
+//-----------------------------------------------------------------------------
+// Global control of data cache
+
+// Enable the data cache
+#define HAL_DCACHE_ENABLE()
+
+// Disable the data cache
+#define HAL_DCACHE_DISABLE()
+
+// Invalidate the entire cache
+#define HAL_DCACHE_INVALIDATE_ALL()
+
+// Synchronize the contents of the cache with memory.
+#define HAL_DCACHE_SYNC()
+
+// Purge contents of data cache
+#define HAL_DCACHE_PURGE_ALL()
+
+// Query the state of the data cache (does not affect the caching)
+#define HAL_DCACHE_IS_ENABLED(_state_) \
+ CYG_MACRO_START \
+ (_state_) = 0; \
+ CYG_MACRO_END
+
+// Set the data cache refill burst size
+//#define HAL_DCACHE_BURST_SIZE(_size_)
+
+// Set the data cache write mode
+//#define HAL_DCACHE_WRITE_MODE( _mode_ )
+
+//#define HAL_DCACHE_WRITETHRU_MODE 0
+//#define HAL_DCACHE_WRITEBACK_MODE 1
+
+// Load the contents of the given address range into the data cache
+// and then lock the cache so that it stays there.
+//#define HAL_DCACHE_LOCK(_base_, _size_)
+
+// Undo a previous lock operation
+//#define HAL_DCACHE_UNLOCK(_base_, _size_)
+
+// Unlock entire cache
+//#define HAL_DCACHE_UNLOCK_ALL()
+
+//-----------------------------------------------------------------------------
+// Data cache line control
+
+// Allocate cache lines for the given address range without reading its
+// contents from memory.
+//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
+
+// Write dirty cache lines to memory and invalidate the cache entries
+// for the given address range.
+//#define HAL_DCACHE_FLUSH( _base_ , _size_ )
+
+// Invalidate cache lines in the given range without writing to memory.
+//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
+
+// Write dirty cache lines to memory for the given address range.
+//#define HAL_DCACHE_STORE( _base_ , _size_ )
+
+// Preread the given range into the cache with the intention of reading
+// from it later.
+//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
+
+// Preread the given range into the cache with the intention of writing
+// to it later.
+//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
+
+// Allocate and zero the cache lines associated with the given range.
+//#define HAL_DCACHE_ZERO( _base_ , _size_ )
+
+//-----------------------------------------------------------------------------
+// Global control of Instruction cache
+
+// Enable the instruction cache
+#define HAL_ICACHE_ENABLE()
+
+// Disable the instruction cache
+#define HAL_ICACHE_DISABLE()
+
+// Invalidate the entire cache
+#define HAL_ICACHE_INVALIDATE_ALL()
+
+// Synchronize the contents of the cache with memory.
+#define HAL_ICACHE_SYNC()
+
+// Query the state of the instruction cache (does not affect the caching)
+#define HAL_ICACHE_IS_ENABLED(_state_) \
+ CYG_MACRO_START \
+ (_state_) = 0; \
+ CYG_MACRO_END
+
+// Set the instruction cache refill burst size
+//#define HAL_ICACHE_BURST_SIZE(_size_)
+
+// Load the contents of the given address range into the instruction cache
+// and then lock the cache so that it stays there.
+//#define HAL_ICACHE_LOCK(_base_, _size_)
+
+// Undo a previous lock operation
+//#define HAL_ICACHE_UNLOCK(_base_, _size_)
+
+// Unlock entire cache
+//#define HAL_ICACHE_UNLOCK_ALL()
+
+//-----------------------------------------------------------------------------
+// Instruction cache line control
+
+// Invalidate cache lines in the given range without writing to memory.
+//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
+
+//-----------------------------------------------------------------------------
+#endif // ifndef CYGONCE_HAL_CACHE_H
+// End of hal_cache.h
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/hal_diag.h b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/hal_diag.h
new file mode 100644
index 0000000..3a9dba4
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/hal_diag.h
@@ -0,0 +1,90 @@
+#ifndef CYGONCE_HAL_DIAG_H
+#define CYGONCE_HAL_DIAG_H
+
+//=============================================================================
+//
+// hal_diag.h
+//
+// HAL Support for Kernel Diagnostic Routines
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): jskov
+// Contributors:jskov, gthomas, tkoeller
+// Date: 2001-07-12
+// Purpose: HAL Support for Kernel Diagnostic Routines
+// Description: Diagnostic routines for use during kernel development.
+// Usage: #include <cyg/hal/hal_diag.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>
+
+#include <cyg/hal/hal_if.h>
+
+externC void zpu_if_diag_init(void);
+externC void zpu_if_diag_write_char(char c);
+externC void zpu_if_diag_read_char(char *c);
+
+#define HAL_DIAG_INIT() zpu_if_diag_init()
+#define HAL_DIAG_WRITE_CHAR(_c_) zpu_if_diag_write_char(_c_)
+#define HAL_DIAG_READ_CHAR(_c_) zpu_if_diag_read_char(&_c_)
+
+//-----------------------------------------------------------------------------
+// LED
+externC void hal_diag_led(int mask);
+
+externC void hal_zpu_set_leds(int mask);
+
+//-----------------------------------------------------------------------------
+// delay
+
+externC void hal_delay_us(cyg_int32 usecs);
+#define HAL_DELAY_US(n) hal_delay_us(n);
+
+//-----------------------------------------------------------------------------
+// reset
+
+extern void hal_zpu_reset_cpu(void);
+
+//-----------------------------------------------------------------------------
+// end of hal_diag.h
+#endif // CYGONCE_HAL_DIAG_H
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/plf_stub.h b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/plf_stub.h
new file mode 100644
index 0000000..eb87958
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/plf_stub.h
@@ -0,0 +1,85 @@
+#ifndef CYGONCE_HAL_PLF_STUB_H
+#define CYGONCE_HAL_PLF_STUB_H
+
+//=============================================================================
+//
+// plf_stub.h
+//
+// Platform header for GDB stub support.
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): jskov
+// Contributors:jskov, gthomas
+// Date: 2001-07-12
+// Purpose: Platform HAL stub support for ZPU boards.
+// Usage: #include <cyg/hal/plf_stub.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM
+
+
+//----------------------------------------------------------------------------
+// Define some platform specific communication details. This is mostly
+// handled by hal_if now, but we need to make sure the comms tables are
+// properly initialized.
+
+externC void cyg_hal_plf_comms_init(void);
+
+#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init()
+
+#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud))
+#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0
+#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT
+
+//----------------------------------------------------------------------------
+// Stub initializer.
+#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT
+
+#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_STUB_H
+// End of plf_stub.h
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/var_arch.h b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/var_arch.h
new file mode 100644
index 0000000..293d7fc
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/var_arch.h
@@ -0,0 +1,73 @@
+#ifndef CYGONCE_HAL_VAR_ARCH_H
+#define CYGONCE_HAL_VAR_ARCH_H
+//=============================================================================
+//
+// var_arch.h
+//
+// ZPU variant architecture overrides
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2003 Jonathan Larmour <jifl@eCosCentric.com>
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting the copyright
+// holders.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): jlarmour
+// Contributors: Daniel Neri
+// Date: 2003-06-24
+// Purpose: ZPU variant architecture overrides
+// Description:
+// Usage: #include <cyg/hal/hal_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <cyg/hal/hal_io.h>
+
+//--------------------------------------------------------------------------
+// Idle thread code.
+// This macro is called in the idle thread loop, and gives the HAL the
+// chance to insert code. Typical idle thread behaviour might be to halt the
+// processor. These implementations halt the system core clock.
+
+#ifndef HAL_IDLE_THREAD_ACTION
+#define HAL_IDLE_THREAD_ACTION(_count_) \
+CYG_MACRO_START \
+CYG_MACRO_END
+#endif
+
+//-----------------------------------------------------------------------------
+// end of var_arch.h
+#endif // CYGONCE_HAL_VAR_ARCH_H
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/var_io.h b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/var_io.h
new file mode 100644
index 0000000..f1ef035
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/var_io.h
@@ -0,0 +1,73 @@
+#ifndef CYGONCE_HAL_VAR_IO_H
+#define CYGONCE_HAL_VAR_IO_H
+//=============================================================================
+//
+// var_io.h
+//
+// Variant specific registers
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): jskov
+// Contributors:jskov, gthomas, tkoeller, tdrury, nickg
+// Date: 2001-07-12
+// Purpose: ZPU variant specific registers
+// Description:
+// Usage: #include <cyg/hal/var_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <cyg/hal/plf_io.h>
+
+
+extern volatile int *INTERRUPT_MASK;
+extern volatile int *TIMER_PERIOD;
+extern volatile int *TIMER_INTERRUPT;
+extern volatile int *TIMER_ENABLE;
+extern volatile int *TIMER_COUNTER;
+extern volatile int *UART_INTERRUPT;
+extern volatile int *UART_ENABLE;
+void ethermac_enable(int enable);
+int ethermac_interrupt();
+void ethermac_ack();
+
+//-----------------------------------------------------------------------------
+// end of var_io.h
+#endif // CYGONCE_HAL_VAR_IO_H
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/src/hal_diag.c b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/src/hal_diag.c
new file mode 100644
index 0000000..0b0f901
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/src/hal_diag.c
@@ -0,0 +1,88 @@
+/*=============================================================================
+//
+// hal_diag.c
+//
+// HAL diagnostic output code
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): jskov
+// Contributors:jskov, gthomas
+// Date: 2001-07-12
+// Purpose: HAL diagnostic output
+// Description: Implementations of HAL diagnostic output support.
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================*/
+
+#include <pkgconf/hal.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h> // base types
+
+#include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP macros
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_if.h> // interface API
+#include <cyg/hal/hal_intr.h> // HAL_ENABLE/MASK/UNMASK_INTERRUPTS
+#include <cyg/hal/hal_misc.h> // Helper functions
+#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED
+#include <cyg/hal/hal_diag.h>
+
+#include <cyg/hal/var_io.h> // USART registers
+
+void zpu_if_diag_init(void)
+{
+}
+
+extern void outbyte(int c);
+extern int inbyte();
+
+void
+zpu_if_diag_write_char(char c)
+{
+ outbyte(c);
+}
+
+void
+zpu_if_diag_read_char(char *c)
+{
+ *c=inbyte();
+}
+
+//-----------------------------------------------------------------------------
+// End of hal_diag.c
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/src/zpu_misc.c b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/src/zpu_misc.c
new file mode 100644
index 0000000..019e024
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/src/zpu_misc.c
@@ -0,0 +1,252 @@
+/*==========================================================================
+//
+// zpu_misc.c
+//
+// HAL misc board support code for Zylin ZPU
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): gthomas
+// Contributors: gthomas, jskov, nickg, tkoeller
+// Date: 2001-07-12
+// Purpose: HAL board support
+// Description: Implementations of HAL board interfaces
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_arch.h> // Register state info
+#include <cyg/hal/hal_diag.h>
+#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+#include <cyg/hal/drv_api.h> // HAL ISR support
+#endif
+#include <cyg/hal/hal_intr.h> // necessary?
+
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/hal_if.h> // calling interface
+#include <cyg/hal/hal_misc.h> // helper functions
+#include <cyg/hal/var_io.h> // platform registers
+
+
+
+
+
+// -------------------------------------------------------------------------
+// Clock support
+
+static cyg_uint32 _period;
+
+
+void hal_clock_initialize(cyg_uint32 period)
+{
+ _period=period;
+ *TIMER_PERIOD=period;
+ *TIMER_INTERRUPT=0x2; // reset counter
+}
+
+void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
+{
+ /* the next interrupt will happen without further action */
+}
+
+
+long long _readCycles();
+
+void hal_clock_read(cyg_uint32 *pvalue)
+{
+ *pvalue=_period-1-*TIMER_COUNTER;
+}
+
+// -------------------------------------------------------------------------
+//
+void hal_delay_us(cyg_int32 usecs)
+{
+ long long until=_readCycles();
+ until+=((long long)usecs*(long long)(CYGNUM_HAL_ZYLIN_ZPU_CLOCK_SPEED))/(long long)1000000;
+
+ /* waiting for the moment to pass.... */
+ for (;;)
+ {
+ if (_readCycles()>until)
+ {
+ break;
+ }
+ }
+}
+
+// -------------------------------------------------------------------------
+// Hardware init
+
+void hal_hardware_init(void)
+{
+ int i;
+ for (i=0; i<CYGNUM_HAL_ISR_COUNT; i++)
+ {
+ hal_interrupt_handlers[i]=(CYG_ADDRESS)hal_default_isr;
+ }
+}
+
+// -------------------------------------------------------------------------
+// This routine is called to respond to a hardware interrupt (IRQ). It
+// should interrogate the hardware and return the IRQ vector number.
+
+int hal_IRQ_handler(void)
+{
+ // for now we only have this type of interrupt
+ if ((*TIMER_INTERRUPT&0x1)!=0)
+ {
+ return CYGNUM_HAL_INTERRUPT_TIMER;
+ } else if ((*UART_INTERRUPT&0x1)!=0)
+ {
+ return CYGNUM_HAL_INTERRUPT_UART;
+ }
+#ifdef CYGPKG_IO_ETH_DRIVERS
+ else if (ethermac_interrupt())
+ {
+ return CYGNUM_HAL_INTERRUPT_ETHERMAC;
+ }
+#endif
+ else
+ {
+ return CYGNUM_HAL_INTERRUPT_NONE;
+ }
+}
+
+// -------------------------------------------------------------------------
+// Interrupt control
+//
+
+void hal_interrupt_mask(int vector)
+{
+ CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
+ vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
+
+ if (vector==CYGNUM_HAL_INTERRUPT_TIMER)
+ {
+ *TIMER_ENABLE=0;
+ } else if (vector==CYGNUM_HAL_INTERRUPT_UART)
+ {
+ *UART_ENABLE=0;
+ }
+#ifdef CYGPKG_IO_ETH_DRIVERS
+ else if (vector==CYGNUM_HAL_INTERRUPT_ETHERMAC)
+ {
+ ethermac_enable(0);
+ }
+#endif
+}
+
+void hal_interrupt_unmask(int vector)
+{
+ CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
+ vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
+ if (vector==CYGNUM_HAL_INTERRUPT_TIMER)
+ {
+ *TIMER_ENABLE=1;
+ } else if (vector==CYGNUM_HAL_INTERRUPT_UART)
+ {
+ *UART_ENABLE=1;
+ }
+#ifdef CYGPKG_IO_ETH_DRIVERS
+ else if (vector==CYGNUM_HAL_INTERRUPT_ETHERMAC)
+ {
+ ethermac_enable(1);
+ }
+#endif
+
+}
+
+void hal_interrupt_acknowledge(int vector)
+{
+ if (vector==CYGNUM_HAL_INTERRUPT_TIMER)
+ {
+ *TIMER_INTERRUPT=0x1;
+ } else if (vector==CYGNUM_HAL_INTERRUPT_UART)
+ {
+ *UART_INTERRUPT=0x1;
+ }
+#ifdef CYGPKG_IO_ETH_DRIVERS
+ else if (vector==CYGNUM_HAL_INTERRUPT_ETHERMAC)
+ {
+ ethermac_ack();
+ }
+#endif
+
+}
+
+void hal_interrupt_configure(int vector, int level, int up)
+{
+ CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
+ vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
+}
+
+void hal_interrupt_set_level(int vector, int level)
+{
+ CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
+ vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
+ CYG_ASSERT(level >= 0 && level <= 7, "Invalid level");
+
+}
+
+void hal_show_IRQ(int vector, int data, int handler)
+{
+}
+
+
+/* Use the watchdog to generate a reset */
+void hal_zpu_reset_cpu(void)
+{
+}
+
+/* nothing to do by default */
+cyg_uint32
+hal_default_isr(cyg_uint32 vector, CYG_ADDRWORD data)
+{
+ return 0;
+}
+
+//--------------------------------------------------------------------------
+// EOF zpu_misc.c
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/ChangeLog b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/ChangeLog
new file mode 100644
index 0000000..a29dbf8
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/ChangeLog
@@ -0,0 +1,39 @@
+2004-09-16 Øyvind Harboe <oyvind.harboe@zylin.com>
+
+ * first cut HAL support for ZPU
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/cdl/hal_zylin_zpu_zeta.cdl b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/cdl/hal_zylin_zpu_zeta.cdl
new file mode 100644
index 0000000..65a8d59
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/cdl/hal_zylin_zpu_zeta.cdl
@@ -0,0 +1,298 @@
+# ====================================================================
+#
+# hal_zpu.cdl
+#
+# ZPU HAL package configuration data
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):
+# Contributors:
+# Date: 2001-07-12
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_HAL_ZYLIN_ZPU_ZETA {
+ display "Zylin ZPU HAL"
+ parent CYGPKG_HAL_ZYLIN_ZPU
+ define_header hal_zylin_zpu_zeta.h
+ include_dir cyg/hal
+ hardware
+ description "
+ The Zylin ZPU HAL package provides the support needed to run
+ eCos on an Zylin ZPU board."
+
+ compile zeta_misc.c
+
+ requires { CYGHWR_HAL_ZYLIN_ZPU == "ZPU1" }
+
+ define_proc {
+ puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_zylin.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_zylin_zpu.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_zylin_zpu_zeta.h>"
+ puts $::cdl_header "#define HAL_PLATFORM_CPU \"ZPU1\""
+ puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Zylin Zeta\""
+ puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\""
+ }
+
+ # Real-time clock/counter specifics
+ cdl_option CYGNUM_HAL_ZYLIN_ZPU_CLOCK_SPEED {
+ display "CPU clock speed"
+ flavor data
+ default_value 90000000
+ }
+
+ cdl_component CYGNUM_HAL_RTC_CONSTANTS {
+ display "Real-time clock constants"
+ flavor none
+
+ cdl_option CYGNUM_HAL_RTC_NUMERATOR {
+ display "Real-time clock numerator"
+ flavor data
+ default_value 1000000000
+ }
+ cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
+ display "Real-time clock denominator"
+ flavor data
+ default_value 100
+ }
+ cdl_option CYGNUM_HAL_RTC_PERIOD {
+ display "Real-time clock period"
+ flavor data
+ default_value (CYGNUM_HAL_ZYLIN_ZPU_CLOCK_SPEED / CYGNUM_HAL_RTC_DENOMINATOR)
+ }
+ }
+
+
+ cdl_component CYG_HAL_STARTUP {
+ display "Startup type"
+ flavor data
+ default_value {"RAM"}
+ legal_values {"RAM"}
+ no_define
+ define -file system.h CYG_HAL_STARTUP
+ description "
+ When targetting the ZPU board it is possible to build
+ the system for either RAM bootstrap or ROM bootstrap(s). Select
+ 'ram' when building programs to load into RAM using onboard
+ debug software such as Angel or eCos GDB stubs. Select 'rom'
+ when building a stand-alone application which will be put
+ into ROM. Using ROMRAM will allow the program to exist in
+ ROM, but be copied to RAM during startup."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+ display "Number of communication channels on the board"
+ flavor data
+ calculated 1
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+ display "Debug serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value 0
+ description "
+ This option
+ chooses which port will be used to connect to a host
+ running GDB."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+ display "Diagnostic serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value 0
+ description "
+ This option
+ chooses which port will be used for diagnostic output."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+ display "Diagnostic serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 57600 115200
+ default_value 38400
+ description "
+ This option selects the baud rate used for the diagnostic port."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+ display "GDB serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 57600 115200
+ default_value 38400
+ description "
+ This option controls the baud rate used for the GDB connection."
+ }
+
+ cdl_option CYGSEM_HAL_ROM_MONITOR {
+ display "Behave as a ROM monitor"
+ flavor bool
+ default_value 0
+ parent CYGPKG_HAL_ROM_MONITOR
+ requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" }
+ description "
+ Enable this option if this program is to be used as a ROM monitor,
+ i.e. applications will be loaded into RAM on the board, and this
+ ROM monitor may process exceptions or interrupts generated from the
+ application. This enables features such as utilizing a separate
+ interrupt stack when exceptions are generated."
+ }
+
+ cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+ display "Work with a ROM monitor"
+ flavor booldata
+ legal_values { "Generic" }
+ default_value { 0 }
+ parent CYGPKG_HAL_ROM_MONITOR
+ requires { CYG_HAL_STARTUP == "RAM" }
+ description "
+ Support can be enabled for different varieties of ROM monitor.
+ This support changes various eCos semantics such as the encoding
+ of diagnostic output, or the overriding of hardware interrupt
+ vectors.
+ Firstly there is \"Generic\" support which prevents the HAL
+ from overriding the hardware vectors that it does not use, to
+ instead allow an installed ROM monitor to handle them. This is
+ the most basic support which is likely to be common to most
+ implementations of ROM monitor.
+ \"GDB_stubs\" provides support when GDB stubs are included in
+ the ROM monitor or boot ROM."
+ }
+
+ cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
+ display "Redboot HAL options"
+ flavor none
+ no_define
+ parent CYGPKG_REDBOOT
+ active_if CYGPKG_REDBOOT
+ description "
+ This option lists the target's requirements for a valid Redboot
+ configuration."
+
+ cdl_option CYGBLD_BUILD_REDBOOT_BIN {
+ display "Build Redboot ROM binary image"
+ active_if CYGBLD_BUILD_REDBOOT
+ default_value 1
+ no_define
+ description "This option enables the conversion of the Redboot ELF
+ image to a binary image suitable for ROM programming."
+
+ make -priority 325 {
+ <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
+ $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
+ $(OBJCOPY) -O srec $< $(@:.bin=.srec)
+ $(OBJCOPY) -O binary $< $@
+ }
+
+ }
+ }
+
+ cdl_component CYGBLD_GLOBAL_OPTIONS {
+ display "Global build options"
+ flavor none
+ parent CYGPKG_NONE
+ description "
+ Global build options including control over
+ compiler flags, linker flags and choice of toolchain."
+
+
+ cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+ display "Global command prefix"
+ flavor data
+ no_define
+ default_value { "zpu-elf" }
+ description "
+ This option specifies the command prefix used when
+ invoking the build tools."
+ }
+
+ cdl_option CYGBLD_GLOBAL_CFLAGS {
+ display "Global compiler flags"
+ flavor data
+ no_define
+ default_value { "-Wall -Wpointer-arith -Winline -Wundef -g -Os -ffunction-sections -fdata-sections -fno-exceptions -finit-priority -zeta" }
+ description "
+ This option controls the global compiler flags which are used to
+ compile all packages by default. Individual packages may define
+ options which override these global flags."
+ }
+
+ cdl_option CYGBLD_GLOBAL_LDFLAGS {
+ display "Global linker flags"
+ flavor data
+ no_define
+ default_value { "-Wl,--gc-sections -Wl,-static -g -nostdlib -zeta -Wl,--relax -Os" }
+ description "
+ This option controls the global linker flags. Individual
+ packages may define options which override these global flags."
+ }
+ }
+
+ cdl_component CYGHWR_MEMORY_LAYOUT {
+ display "Memory layout"
+ flavor data
+ no_define
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "zpu_ram" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "zpu_romram" :
+ "zpu_rom" }
+
+ cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+ display "Memory layout linker script fragment"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_zylin_zpu_zeta_ram.ldi>" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_zylin_zpu_zeta_romram.ldi>" :
+ "<pkgconf/mlt_zylin_zpu_zeta_rom.ldi>" }
+ }
+
+ cdl_option CYGHWR_MEMORY_LAYOUT_H {
+ display "Memory layout header file"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_H
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_zylin_zpu_zeta_ram.h>" :
+ (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_zylin_zpu_zeta_romram.h>" :
+ "<pkgconf/mlt_zylin_zpu_zeta_rom.h>" }
+ }
+ }
+}
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/hal_platform_ints.h b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/hal_platform_ints.h
new file mode 100644
index 0000000..9ff0029
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/hal_platform_ints.h
@@ -0,0 +1,79 @@
+#ifndef CYGONCE_HAL_PLATFORM_INTS_H
+#define CYGONCE_HAL_PLATFORM_INTS_H
+//==========================================================================
+//
+// hal_platform_ints.h
+//
+// HAL Interrupt and clock assignments for ZPU
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): gthomas
+// Contributors: gthomas
+// Date: 2001-07-12
+// Purpose: Define Interrupt support
+// Description: The interrupt specifics for the ZPU board/platform are
+// defined here.
+//
+// Usage: #include <cyg/hal/hal_platform_ints.h>
+// ...
+//
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#define CYGNUM_HAL_INTERRUPT_TIMER 0
+
+#define CYGNUM_HAL_ISR_MIN 0
+
+#define CYGNUM_HAL_ISR_MAX 0
+
+#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX + 1)
+
+// The vector used by the Real time clock
+#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER
+
+
+//----------------------------------------------------------------------------
+// Reset.
+__externC void hal_zpu_reset_cpu(void);
+#define HAL_PLATFORM_RESET() hal_zpu_reset_cpu()
+
+
+
+#endif // CYGONCE_HAL_PLATFORM_INTS_H
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/pkgconf/mlt_zylin_zpu_zeta_ram.h b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/pkgconf/mlt_zylin_zpu_zeta_ram.h
new file mode 100644
index 0000000..ddbaae8
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/pkgconf/mlt_zylin_zpu_zeta_ram.h
@@ -0,0 +1,17 @@
+// eCos memory layout - Mon Jul 23 11:49:04 2001
+
+// This is a generated file - do not edit
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x10000000)
+#define CYGMEM_REGION_ram_SIZE (0x00100000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE ((CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE) - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/pkgconf/mlt_zylin_zpu_zeta_ram.ldi b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/pkgconf/mlt_zylin_zpu_zeta_ram.ldi
new file mode 100644
index 0000000..d9a14be
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/pkgconf/mlt_zylin_zpu_zeta_ram.ldi
@@ -0,0 +1,27 @@
+// eCos memory layout - Mon Jul 23 11:49:04 2001
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+ ram : ORIGIN = 0x00000000, LENGTH = 0x100000
+}
+
+SECTIONS
+{
+ SECTIONS_BEGIN
+ SECTION_fixed_vectors (ram, 0x0, LMA_EQ_VMA)
+ SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rom_vectors (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata1 (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA)
+ CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+ SECTIONS_END
+}
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/plf_io.h b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/plf_io.h
new file mode 100644
index 0000000..1c6f53b
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/plf_io.h
@@ -0,0 +1,58 @@
+#ifndef CYGONCE_HAL_PLF_IO_H
+#define CYGONCE_HAL_PLF_IO_H
+//=============================================================================
+//
+// plf_io.h
+//
+// ZPU board specific registers
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): tkoeller
+// Contributors: tdrury
+// Date: 2002-06-22
+// Purpose: Zylin ZPU board specific registers
+// Description:
+// Usage: #include <cyg/hal/plf_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_io.h
+#endif // CYGONCE_HAL_PLF_IO_H
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/misc/redboot_RAM.ecm b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/misc/redboot_RAM.ecm
new file mode 100644
index 0000000..04eae62
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/misc/redboot_RAM.ecm
@@ -0,0 +1,53 @@
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+ description "" ;
+ hardware zpu_board ;
+ template redboot ;
+ package -hardware CYGPKG_HAL_ZPU current ;
+ package -hardware CYGPKG_HAL_ZPU_CPU current ;
+ package -template CYGPKG_HAL current ;
+ package -template CYGPKG_INFRA current ;
+ package -template CYGPKG_REDBOOT current ;
+};
+
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+ user_value 0
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+ inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+ inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+ inferred_value 0 0
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+ user_value 1
+};
+
+cdl_option CYGOPT_REDBOOT_FIS {
+ user_value 0
+};
+
+cdl_component CYGSEM_REDBOOT_FLASH_CONFIG {
+ user_value 0
+};
+
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC {
+ user_value 0
+};
+
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/src/zeta_misc.c b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/src/zeta_misc.c
new file mode 100644
index 0000000..b8b2e39
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/src/zeta_misc.c
@@ -0,0 +1,64 @@
+//==========================================================================
+//
+// zpu_misc.c
+//
+// HAL misc board support code for Zylin ZPU board
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): gthomas
+// Contributors: gthomas, jskov, tkoeller, tdrury, nickg
+// Date: 2002-05-30
+// Purpose: HAL board support
+// Description: Implementations of HAL board interfaces
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/hal/hal_io.h> // low level i/o
+#include <cyg/hal/var_io.h> // common registers
+#include <cyg/hal/plf_io.h> // platform registers
+
+
+void hal_zpu_set_leds(int leds)
+{
+}
diff --git a/zpu/sw/ecos/repository/net/zylin/current/cdl/phi_net.cdl b/zpu/sw/ecos/repository/net/zylin/current/cdl/phi_net.cdl
new file mode 100644
index 0000000..d98bc96
--- /dev/null
+++ b/zpu/sw/ecos/repository/net/zylin/current/cdl/phi_net.cdl
@@ -0,0 +1,56 @@
+# ====================================================================
+#
+# net.cdl
+#
+# Networking configuration data
+#
+# ====================================================================
+#####ECOSPDCOPYRIGHTBEGIN####
+#
+# Copyright (C) 2000, 2001, 2002 Red Hat, Inc.
+# All Rights Reserved.
+#
+# Permission is granted to use, copy, modify and redistribute this
+# file.
+#
+#####ECOSPDCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s): gthomas
+# Original data: gthomas
+# Contributors:
+# Date: 1999-11-29
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_PHI_NET {
+ display "Basic networking framework"
+ doc nothing.html
+ include_dir .
+ requires CYGPKG_IO
+ requires CYGPKG_ISOINFRA
+ requires CYGINT_ISO_C_TIME_TYPES
+ requires CYGINT_ISO_STRERROR
+ requires CYGINT_ISO_ERRNO
+ requires CYGINT_ISO_ERRNO_CODES
+ requires CYGINT_ISO_MALLOC
+ requires CYGINT_ISO_STRING_BSD_FUNCS
+ requires CYGPKG_NET
+ description "Basic networking support, including TCP/IP."
+
+ cdl_component CYGPKG_PHI_NET_INET {
+ display "INET support"
+ active_if CYGPKG_NET_STACK_INET
+ flavor bool
+ no_define
+ default_value 1
+ description "
+ This option enables support for PHI INET (IP) network processing."
+ compile \
+ phi_network_support.c
+
+ }
+}
diff --git a/zpu/sw/ecos/repository/net/zylin/current/src/phi_network_support.c b/zpu/sw/ecos/repository/net/zylin/current/src/phi_network_support.c
new file mode 100644
index 0000000..c297651
--- /dev/null
+++ b/zpu/sw/ecos/repository/net/zylin/current/src/phi_network_support.c
@@ -0,0 +1,368 @@
+//==========================================================================
+//
+// ph_network_support.c
+//
+// Misc network support functions
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Andrew Lunn <andrew.lunn@ascom.ch>
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): gthomas
+// Contributors: gthomas, sorin@netappi.com ("Sorin Babeanu"), hmt, jlarmour,
+// andrew.lunn@ascom.ch
+// Date: 2000-01-10
+// Purpose:
+// Description:
+//
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+// BOOTP support
+
+#include <pkgconf/net.h>
+#undef _KERNEL
+#include <sys/param.h>
+#include <sys/socket.h>
+#include <sys/ioctl.h>
+#include <sys/errno.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+
+#include <net/if.h>
+#include <netinet/in.h>
+#include <netinet/ip.h>
+#include <netinet/ip_icmp.h>
+#include <net/route.h>
+
+#include <cyg/infra/diag.h>
+#include <cyg/kernel/kapi.h>
+
+#include <stdio.h> // for 'sprintf()'
+#include <string.h> // for strncpy and strtok_r
+#include <bootp.h>
+#include <network.h>
+#include <arpa/inet.h>
+
+#ifdef CYGPKG_IO_PCMCIA
+#include <cyg/io/eth/netdev.h>
+#endif
+
+#ifdef CYGPKG_NET_DHCP
+#include <dhcp.h>
+#endif
+
+#ifdef CYGPKG_NS_DNS
+#include <pkgconf/ns_dns.h>
+#endif
+
+#ifdef CYGHWR_NET_DRIVER_ETH0
+//struct bootp eth0_bootp_data;
+//cyg_bool_t eth0_up = false;
+//const char *eth0_name = "eth0";
+#endif
+#ifdef CYGHWR_NET_DRIVER_ETH1
+struct bootp eth1_bootp_data;
+//cyg_bool_t eth1_up = false;
+//const char *eth1_name = "eth1";
+#endif
+
+#define _string(s) #s
+#define string(s) _string(s)
+
+#ifndef CYGPKG_LIBC_STDIO
+#define perror(s) diag_printf(#s ": %s\n", strerror(errno))
+#endif
+
+
+static int hasIP(char *ip, char *mask, char *broadcast, char *gateway, char *server)
+{
+ int retVal = false;
+ int len = -1;
+ char buf[81];
+ char *ptr1 = NULL;
+ char *token = NULL;
+
+ if(ip == NULL)
+ return 0;
+
+ //try to open ip file
+ int fd = open("/jffs2/ip", O_RDONLY);
+ if(fd < 0)
+ {
+ ip[0] = '\0';
+ return 0;
+ }
+ //return ip address
+ if( (len = read(fd, buf, 80)) > 0)
+ {
+ buf[len] = '\0';
+ //get IP
+ token = strtok_r(buf, "_", &ptr1);
+ if(token != NULL)
+ strncpy(ip, token, 15);
+ else
+ {
+ close(fd);
+ return 0;
+ }
+ //get MASK
+ token = strtok_r(NULL, "_", &ptr1);
+ if(token != NULL)
+ strncpy(mask, token, 15);
+ else
+ {
+ close(fd);
+ return 0;
+ }
+ //get broadcast
+ token = strtok_r(NULL, "_", &ptr1);
+ if(token != NULL)
+ strncpy(broadcast, token, 15);
+ else
+ {
+ close(fd);
+ return 0;
+ }
+ //get gateway
+ token = strtok_r(NULL, "_", &ptr1);
+ if(token != NULL)
+ strncpy(gateway, token, 15);
+ else
+ {
+ close(fd);
+ return 0;
+ }
+ //get server
+ token = strtok_r(NULL, "_", &ptr1);
+ if(token != NULL)
+ strncpy(server, token, 15);
+ else
+ {
+ close(fd);
+ return 0;
+ }
+
+ retVal = 1;
+ }
+ else
+ {
+ retVal = 0;
+ ip[0] = '\0';
+ }
+ return retVal;
+}
+
+//
+// Initialize network interface[s] using BOOTP/DHCP
+//
+void
+phi_init_all_network_interfaces(void)
+{
+ static volatile int in_init_all_network_interfaces = 0;
+
+#ifdef CYGOPT_NET_IPV6_ROUTING_THREAD
+ int rs_wait = 40;
+#endif
+
+ cyg_scheduler_lock();
+ while ( in_init_all_network_interfaces ) {
+ // Another thread is doing this...
+ cyg_scheduler_unlock();
+ cyg_thread_delay( 10 );
+ cyg_scheduler_lock();
+ }
+ in_init_all_network_interfaces = 1;
+ cyg_scheduler_unlock();
+
+#ifdef CYGHWR_NET_DRIVER_ETH0
+ if ( ! eth0_up ) { // Make this call idempotent
+ char ip[16], mask[16], broadcast[16], gateway[16], server[16];
+ if(!hasIP(ip, mask, broadcast, gateway, server))
+ {
+ // Perform a complete initialization, using BOOTP/DHCP
+ eth0_up = true;
+ eth0_dhcpstate = 0; // Says that initialization is external to dhcp
+ if (do_dhcp(eth0_name, &eth0_bootp_data, &eth0_dhcpstate, &eth0_lease))
+// {
+// if (do_bootp(eth0_name, &eth0_bootp_data))
+ {
+ show_bootp(eth0_name, &eth0_bootp_data);
+ } else {
+ diag_printf("BOOTP/DHCP failed on eth0\n");
+ eth0_up = false;
+ }
+// }
+ }
+ else
+ {
+
+ eth0_up = true;
+ build_bootp_record(&eth0_bootp_data,
+ eth0_name,
+ ip,
+ mask,
+ broadcast,
+ gateway,
+ server);
+ show_bootp(eth0_name, &eth0_bootp_data);
+ }
+ }
+#endif // CYGHWR_NET_DRIVER_ETH0
+#ifdef CYGHWR_NET_DRIVER_ETH1
+ if ( ! eth1_up ) { // Make this call idempotent
+#ifdef CYGHWR_NET_DRIVER_ETH1_BOOTP
+ // Perform a complete initialization, using BOOTP/DHCP
+ eth1_up = true;
+#ifdef CYGHWR_NET_DRIVER_ETH1_DHCP
+ eth1_dhcpstate = 0; // Says that initialization is external to dhcp
+ if (do_dhcp(eth1_name, &eth1_bootp_data, &eth1_dhcpstate, &eth1_lease))
+#else
+#ifdef CYGPKG_NET_DHCP
+ eth1_dhcpstate = DHCPSTATE_BOOTP_FALLBACK;
+ // so the dhcp machine does no harm if called
+#endif
+ if (do_bootp(eth1_name, &eth1_bootp_data))
+#endif
+ {
+#ifdef CYGHWR_NET_DRIVER_ETH1_BOOTP_SHOW
+ show_bootp(eth1_name, &eth1_bootp_data);
+#endif
+ } else {
+ diag_printf("BOOTP/DHCP failed on eth1\n");
+ eth1_up = false;
+ }
+#elif defined(CYGHWR_NET_DRIVER_ETH1_ADDRS_IP)
+ eth1_up = true;
+ build_bootp_record(&eth1_bootp_data,
+ eth1_name,
+ string(CYGHWR_NET_DRIVER_ETH1_ADDRS_IP),
+ string(CYGHWR_NET_DRIVER_ETH1_ADDRS_NETMASK),
+ string(CYGHWR_NET_DRIVER_ETH1_ADDRS_BROADCAST),
+ string(CYGHWR_NET_DRIVER_ETH1_ADDRS_GATEWAY),
+ string(CYGHWR_NET_DRIVER_ETH1_ADDRS_SERVER));
+ show_bootp(eth1_name, &eth1_bootp_data);
+#endif
+ }
+#endif // CYGHWR_NET_DRIVER_ETH1
+#ifdef CYGHWR_NET_DRIVER_ETH0
+#ifndef CYGHWR_NET_DRIVER_ETH0_MANUAL
+ if (eth0_up) {
+ if (!init_net(eth0_name, &eth0_bootp_data)) {
+ diag_printf("Network initialization failed for eth0\n");
+ eth0_up = false;
+ }
+#ifdef CYGHWR_NET_DRIVER_ETH0_IPV6_PREFIX
+ if (!init_net_IPv6(eth0_name, &eth0_bootp_data,
+ string(CYGHWR_NET_DRIVER_ETH0_IPV6_PREFIX))) {
+ diag_printf("Static IPv6 network initialization failed for eth0\n");
+ eth0_up = false; // ???
+ }
+#endif
+ }
+#endif
+#endif
+#ifdef CYGHWR_NET_DRIVER_ETH1
+#ifndef CYGHWR_NET_DRIVER_ETH1_MANUAL
+ if (eth1_up) {
+ if (!init_net(eth1_name, &eth1_bootp_data)) {
+ diag_printf("Network initialization failed for eth1\n");
+ eth1_up = false;
+ }
+#ifdef CYGHWR_NET_DRIVER_ETH1_IPV6_PREFIX
+ if (!init_net_IPv6(eth1_name, &eth1_bootp_data,
+ string(CYGHWR_NET_DRIVER_ETH1_IPV6_PREFIX))) {
+ diag_printf("Static IPv6 network initialization failed for eth1\n");
+ eth1_up = false; // ???
+ }
+#endif
+ }
+#endif
+#endif
+
+#ifdef CYGPKG_NET_NLOOP
+#if 0 < CYGPKG_NET_NLOOP
+ {
+ static int loop_init = 0;
+ int i;
+ if ( 0 == loop_init++ )
+ for ( i = 0; i < CYGPKG_NET_NLOOP; i++ )
+ init_loopback_interface( i );
+ }
+#endif
+#endif
+
+#ifdef CYGOPT_NET_DHCP_DHCP_THREAD
+ dhcp_start_dhcp_mgt_thread();
+#endif
+
+#ifdef CYGOPT_NET_IPV6_ROUTING_THREAD
+ ipv6_start_routing_thread();
+
+ // Wait for router solicit process to happen.
+ while (rs_wait-- && !cyg_net_get_ipv6_advrouter(NULL)) {
+ cyg_thread_delay(10);
+ }
+ if (rs_wait == 0 ) {
+ diag_printf("No router solicit received\n");
+ } else {
+ // Give Duplicate Address Detection time to work
+ cyg_thread_delay(200);
+ }
+#endif
+
+#ifdef CYGDAT_NS_DNS_DEFAULT_SERVER
+ cyg_dns_res_start(string(CYGDAT_NS_DNS_DEFAULT_SERVER));
+#endif
+
+#ifdef CYGDAT_NS_DNS_DOMAINNAME_NAME
+#define _NAME string(CYGDAT_NS_DNS_DOMAINNAME_NAME)
+ {
+ const char buf[] = _NAME;
+ int len = strlen(_NAME);
+
+ setdomainname(buf,len);
+ }
+#endif
+ // Open the monitor to other threads.
+ in_init_all_network_interfaces = 0;
+
+}
+
+// EOF phi_network_support.c
diff --git a/zpu/sw/ecos/repository/pkgconf/rules.mak b/zpu/sw/ecos/repository/pkgconf/rules.mak
new file mode 100644
index 0000000..e043efa
--- /dev/null
+++ b/zpu/sw/ecos/repository/pkgconf/rules.mak
@@ -0,0 +1,210 @@
+#=============================================================================
+#
+# rules.mak
+#
+# Generic rules for inclusion by all package makefiles.
+#
+#=============================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+#=============================================================================
+#####DESCRIPTIONBEGIN####
+#
+# Author(s): jld
+# Contributors: bartv
+# Date: 1999-11-04
+# Purpose: Generic rules for inclusion by all package makefiles
+# Description:
+#
+#####DESCRIPTIONEND####
+#=============================================================================
+
+# FIXME: This definition belongs in the top-level makefile.
+export HOST_CC := gcc
+
+.PHONY: default build clean tests headers mlt_headers
+
+# include any dependency rules generated previously
+ifneq ($(wildcard *.deps),)
+include $(wildcard *.deps)
+endif
+
+# GCC since 2.95 does -finit-priority by default so remove it from old HALs
+CFLAGS := $(subst -finit-priority,,$(CFLAGS))
+
+# -fvtable-gc is known to be broken in all recent GCC.
+CFLAGS := $(subst -fvtable-gc,,$(CFLAGS))
+
+# To support more recent GCC whilst preserving existing behaviour, we need
+# to increase the inlining limit globally from the default 600. Note this
+# will break GCC 2.95 based tools and earlier. You must use "make OLDGCC=1"
+# to avoid this.
+ifneq ($(OLDGCC),1)
+CFLAGS := -finline-limit=7000 $(CFLAGS)
+endif
+
+# Separate C++ flags out from C flags.
+ACTUAL_CFLAGS = $(CFLAGS)
+ACTUAL_CFLAGS := $(subst -fno-rtti,,$(ACTUAL_CFLAGS))
+ACTUAL_CFLAGS := $(subst -frtti,,$(ACTUAL_CFLAGS))
+ACTUAL_CFLAGS := $(subst -Woverloaded-virtual,,$(ACTUAL_CFLAGS))
+ACTUAL_CFLAGS := $(subst -fvtable-gc,,$(ACTUAL_CFLAGS))
+
+ACTUAL_CXXFLAGS = $(subst -Wstrict-prototypes,,$(CFLAGS))
+
+# pattern matching rules to generate a library object from source code
+# object filenames are prefixed to avoid name clashes
+# a single dependency rule is generated (file extension = ".o.d")
+%.o.d : %.c
+ifeq ($(HOST),CYGWIN)
+ @mkdir -p `cygpath -w "$(dir $@)" | sed "s@\\\\\\\\@/@g"`
+else
+ @mkdir -p $(dir $@)
+endif
+ $(CC) -c $(INCLUDE_PATH) -I$(dir $<) $(ACTUAL_CFLAGS) -Wp,-MD,$(@:.o.d=.tmp) -o $(dir $@)$(OBJECT_PREFIX)_$(notdir $(@:.o.d=.o)) $<
+ @sed -e '/^ *\\/d' -e "s#.*: #$@: #" $(@:.o.d=.tmp) > $@
+ @rm $(@:.o.d=.tmp)
+
+%.o.d : %.cxx
+ifeq ($(HOST),CYGWIN)
+ @mkdir -p `cygpath -w "$(dir $@)" | sed "s@\\\\\\\\@/@g"`
+else
+ @mkdir -p $(dir $@)
+endif
+ $(CC) -c $(INCLUDE_PATH) -I$(dir $<) $(ACTUAL_CXXFLAGS) -Wp,-MD,$(@:.o.d=.tmp) -o $(dir $@)$(OBJECT_PREFIX)_$(notdir $(@:.o.d=.o)) $<
+ @sed -e '/^ *\\/d' -e "s#.*: #$@: #" $(@:.o.d=.tmp) > $@
+ @rm $(@:.o.d=.tmp)
+
+%.o.d : %.cpp
+ifeq ($(HOST),CYGWIN)
+ @mkdir -p `cygpath -w "$(dir $@)" | sed "s@\\\\\\\\@/@g"`
+else
+ @mkdir -p $(dir $@)
+endif
+ $(CC) -c $(INCLUDE_PATH) -I$(dir $<) $(ACTUAL_CXXFLAGS) -Wp,-MD,$(@:.o.d=.tmp) -o $(dir $@)$(OBJECT_PREFIX)_$(notdir $(@:.o.d=.o)) $<
+ @sed -e '/^ *\\/d' -e "s#.*: #$@: #" $(@:.o.d=.tmp) > $@
+ @rm $(@:.o.d=.tmp)
+
+%.o.d : %.S
+ifeq ($(HOST),CYGWIN)
+ @mkdir -p `cygpath -w "$(dir $@)" | sed "s@\\\\\\\\@/@g"`
+else
+ @mkdir -p $(dir $@)
+endif
+ $(CC) -c $(INCLUDE_PATH) -I$(dir $<) $(ACTUAL_CFLAGS) -Wp,-MD,$(@:.o.d=.tmp) -o $(dir $@)$(OBJECT_PREFIX)_$(notdir $(@:.o.d=.o)) $<
+ @sed -e '/^ *\\/d' -e "s#.*: #$@: #" $(@:.o.d=.tmp) > $@
+ @rm $(@:.o.d=.tmp)
+
+# pattern matching rules to generate a test object from source code
+# object filenames are not prefixed
+# a single dependency rule is generated (file extension = ".d")
+%.d : %.c
+ifeq ($(HOST),CYGWIN)
+ @mkdir -p `cygpath -w "$(dir $@)" | sed "s@\\\\\\\\@/@g"`
+else
+ @mkdir -p $(dir $@)
+endif
+ $(CC) -c $(INCLUDE_PATH) -I$(dir $<) $(ACTUAL_CFLAGS) -Wp,-MD,$(@:.d=.tmp) -o $(@:.d=.o) $<
+ @sed -e '/^ *\\/d' -e "s#.*: #$@: #" $(@:.d=.tmp) > $@
+ @rm $(@:.d=.tmp)
+
+%.d : %.cxx
+ifeq ($(HOST),CYGWIN)
+ @mkdir -p `cygpath -w "$(dir $@)" | sed "s@\\\\\\\\@/@g"`
+else
+ @mkdir -p $(dir $@)
+endif
+ $(CC) -c $(INCLUDE_PATH) -I$(dir $<) $(ACTUAL_CXXFLAGS) -Wp,-MD,$(@:.d=.tmp) -o $(@:.d=.o) $<
+ @sed -e '/^ *\\/d' -e "s#.*: #$@: #" $(@:.d=.tmp) > $@
+ @rm $(@:.d=.tmp)
+
+%.d : %.cpp
+ifeq ($(HOST),CYGWIN)
+ @mkdir -p `cygpath -w "$(dir $@)" | sed "s@\\\\\\\\@/@g"`
+else
+ @mkdir -p $(dir $@)
+endif
+ $(CC) -c $(INCLUDE_PATH) -I$(dir $<) $(ACTUAL_CXXFLAGS) -Wp,-MD,$(@:.d=.tmp) -o $(@:.d=.o) $<
+ @sed -e '/^ *\\/d' -e "s#.*: #$@: #" $(@:.d=.tmp) > $@
+ @rm $(@:.d=.tmp)
+
+%.d : %.S
+ifeq ($(HOST),CYGWIN)
+ @mkdir -p `cygpath -w "$(dir $@)" | sed "s@\\\\\\\\@/@g"`
+else
+ @mkdir -p $(dir $@)
+endif
+ $(CC) -c $(INCLUDE_PATH) -I$(dir $<) $(ACTUAL_CFLAGS) -Wp,-MD,$(@:.d=.tmp) -o $(@:.d=.o) $<
+ @sed -e '/^ *\\/d' -e "s#.*: #$@: #" $(@:.d=.tmp) > $@
+ @rm $(@:.d=.tmp)
+
+# rule to generate a test executable from object code
+$(PREFIX)/tests/$(PACKAGE)/%$(EXEEXT): %.d $(wildcard $(PREFIX)/lib/target.ld) $(wildcard $(PREFIX)/lib/*.[ao])
+ifeq ($(HOST),CYGWIN)
+ @mkdir -p `cygpath -w "$(dir $@)" | sed "s@\\\\\\\\@/@g"`
+else
+ @mkdir -p $(dir $@)
+endif
+ifneq ($(IGNORE_LINK_ERRORS),)
+ -$(CC) -L$(PREFIX)/lib -Ttarget.ld -o $@ $(<:.d=.o) $(LDFLAGS)
+else
+ $(CC) -L$(PREFIX)/lib -Ttarget.ld -o $@ $(<:.d=.o) $(LDFLAGS)
+endif
+
+# rule to generate all tests and create a dependency file "tests.deps" by
+# concatenating the individual dependency rule files (file extension = ".d")
+# generated during compilation
+tests: tests.stamp
+
+TESTS := $(TESTS:.cpp=)
+TESTS := $(TESTS:.cxx=)
+TESTS := $(TESTS:.c=)
+TESTS := $(TESTS:.S=)
+tests.stamp: $(foreach target,$(TESTS),$(target).d $(PREFIX)/tests/$(PACKAGE)/$(target)$(EXEEXT))
+ifneq ($(strip $(TESTS)),)
+ @cat $(TESTS:%=%.d) > $(@:.stamp=.deps)
+endif
+ @touch $@
+
+# rule to clean the build tree
+clean:
+ @find . -type f -print | grep -v makefile | xargs rm -f
+
+# rule to copy MLT files
+mlt_headers: $(foreach x,$(MLT),$(PREFIX)/include/pkgconf/$(notdir $x))
+
+$(foreach x,$(MLT),$(PREFIX)/include/pkgconf/$(notdir $x)): $(MLT)
+ @cp $(dir $<)/$(notdir $@) $(PREFIX)/include/pkgconf
+ @chmod u+w $(PREFIX)/include/pkgconf/$(notdir $@)
+
+# end of file
diff --git a/zpu/sw/env.sh b/zpu/sw/env.sh
new file mode 100644
index 0000000..8ed43f0
--- /dev/null
+++ b/zpu/sw/env.sh
@@ -0,0 +1,2 @@
+export ZPUSW=`pwd`
+export PATH=$PATH:/tmp/zpu/install/bin
diff --git a/zpu/sw/freertos/port/port.c b/zpu/sw/freertos/port/port.c
new file mode 100644
index 0000000..ff243ee
--- /dev/null
+++ b/zpu/sw/freertos/port/port.c
@@ -0,0 +1,271 @@
+/*
+ FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
+
+ This file is part of the FreeRTOS.org distribution.
+
+ FreeRTOS.org is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License (version 2) as published
+ by the Free Software Foundation and modified by the FreeRTOS exception.
+ **NOTE** The exception to the GPL is included to allow you to distribute a
+ combined work that includes FreeRTOS.org without being obliged to provide
+ the source code for any proprietary components. Alternative commercial
+ license and support terms are also available upon request. See the
+ licensing section of http://www.FreeRTOS.org for full details.
+
+ FreeRTOS.org is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details.
+
+ You should have received a copy of the GNU General Public License along
+ with FreeRTOS.org; if not, write to the Free Software Foundation, Inc., 59
+ Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+
+
+ ***************************************************************************
+ * *
+ * Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation *
+ * *
+ * This is a concise, step by step, 'hands on' guide that describes both *
+ * general multitasking concepts and FreeRTOS specifics. It presents and *
+ * explains numerous examples that are written using the FreeRTOS API. *
+ * Full source code for all the examples is provided in an accompanying *
+ * .zip file. *
+ * *
+ ***************************************************************************
+
+ 1 tab == 4 spaces!
+
+ Please ensure to read the configuration and relevant port sections of the
+ online documentation.
+
+ http://www.FreeRTOS.org - Documentation, latest information, license and
+ contact details.
+
+ http://www.SafeRTOS.com - A version that is certified for use in safety
+ critical systems.
+
+ http://www.OpenRTOS.com - Commercial support, development, porting,
+ licensing and training services.
+*/
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the MicroBlaze port.
+ *----------------------------------------------------------*/
+
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Standard includes. */
+#include <string.h>
+
+/* hardware/software platform specific defines */
+#define DISABLE_C_PROTOTYPES
+#include <devices.h>
+
+/* Tasks are started with interrupts enabled. */
+#define portINITIAL_INTERRUPT_ENABLE ( ( portSTACK_TYPE ) INTERRUPT_GLOBAL_ENABLE )
+
+/* Tasks are started with a critical section nesting of 0 - however prior
+to the scheduler being commenced we don't want the critical nesting level
+to reach zero, so it is initialised to a high value. */
+#define portINITIAL_NESTING_VALUE ( 0xff )
+
+/* The stack used by the ISR is filled with a known value to assist in
+debugging. */
+#define portISR_STACK_FILL_VALUE 0x55555555
+
+/* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task
+maintains it's own count, so this variable is saved as part of the task
+context. */
+volatile unsigned portBASE_TYPE uxCriticalNesting = portINITIAL_NESTING_VALUE;
+
+/* To limit the amount of stack required by each task, this port uses a
+separate stack for interrupts. */
+unsigned portLONG *pulISRStack;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but
+ * could have alternatively used the watchdog timer or timer 1.
+ */
+static void prvSetupTimerInterrupt( void );
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been made.
+ *
+ * See the header file portable.h.
+ */
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
+{
+ /* Function call parameters. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;
+
+ /* Place initial PC (task entry point) */
+ pxTopOfStack--;
+ *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */
+
+ /* Place initial value for INTERRUPT global ENABLE */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_INTERRUPT_ENABLE; /* interrupt state (global enable) */
+
+ /* Stack an initial value for the critical section nesting. This
+ is initialised to zero as tasks are started with interrupts enabled. */
+ pxTopOfStack--;
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x00;
+
+ /* Place an initial value for all temporary registers mapped to mem[0..16] by gcc */
+ pxTopOfStack--;
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* mem[0] */
+ pxTopOfStack--;
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x22222222; /* mem[4] */
+ pxTopOfStack--;
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x33333333; /* mem[8] */
+ pxTopOfStack--;
+ *pxTopOfStack = ( portSTACK_TYPE ) 0x44444444; /* mem[12] */
+
+ /* Return a pointer to the top of the stack we have generated so this can
+ be stored in the task control block for the task. */
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+portBASE_TYPE xPortStartScheduler( void )
+{
+extern void ( __FreeRTOS_interrupt_handler )( void );
+extern void ( vStartFirstTask )( void );
+
+ /* Setup the FreeRTOS interrupt handler */
+ *(volatile unsigned *) INTERRUPT_VECTOR = (unsigned) __FreeRTOS_interrupt_handler;
+
+ /* Setup the hardware to generate the tick. Interrupts are disabled when
+ this function is called. */
+ prvSetupTimerInterrupt();
+
+ /* Allocate the stack to be used by the interrupt handler. */
+ pulISRStack = ( unsigned portLONG * ) pvPortMalloc( configMINIMAL_STACK_SIZE * sizeof( portSTACK_TYPE ) );
+
+ /* Restore the context of the first task that is going to run. */
+ if( pulISRStack != NULL )
+ {
+ /* Fill the ISR stack with a known value to facilitate debugging. */
+ memset( pulISRStack, portISR_STACK_FILL_VALUE, configMINIMAL_STACK_SIZE * sizeof( portSTACK_TYPE ) );
+ pulISRStack += ( configMINIMAL_STACK_SIZE - 1 );
+
+ /* Kick off the first task. */
+ vStartFirstTask();
+ }
+
+ /* Should not get here as the tasks are now running! */
+ return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* Not implemented. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch called by portYIELD or taskYIELD.
+ */
+void vPortYield( void )
+{
+extern void VPortYieldASM( void );
+
+ /* Perform the context switch in a critical section to assure it is
+ not interrupted by the tick ISR. It is not a problem to do this as
+ each task maintains it's own interrupt status. */
+ portENTER_CRITICAL();
+ /* Jump directly to the yield function to ensure there is no
+ compiler generated prologue code. */
+ asm volatile ( "im VPortYieldASM \n\t" \
+ "call \n\t" );
+ portEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Hardware initialisation to generate the RTOS tick.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+const unsigned portLONG ulCounterValue = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+
+ /* Initialize and start timer1 counter */
+ *(volatile unsigned *) TIMER1_PORT = ulCounterValue;
+ *(volatile unsigned *) TIMERS_CONTROL = TIMER1_ENABLE;
+
+ /* Enable timer1 interrupt while maintaining other bit states
+ but disable global enable */
+ *(volatile unsigned *) INTERRUPT_ENABLE &= ~INTERRUPT_GLOBAL_ENABLE;
+ *(volatile unsigned *) INTERRUPT_ENABLE |= INTERRUPT_TIMER1;
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * The interrupt handler placed in the interrupt vector when the scheduler is
+ * started. The task context has already been saved when this is called.
+ * This handler determines the interrupt source and calls the relevant
+ * peripheral handler.
+ */
+void vTaskISRHandler( void )
+{
+void vTickISR(void);
+
+ unsigned int_status = *(volatile unsigned *) INTERRUPT_STATUS;
+ if(int_status & INTERRUPT_TIMER1) vTickISR();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Handler for the timer interrupt.
+ */
+void vTickISR( void )
+{
+ /* Increment the RTOS tick - this might cause a task to unblock. */
+ vTaskIncrementTick();
+
+ /* Clear the timer interrupt */
+ /* ... in this platform, timer interrupt is cleared automatically */
+
+ /* If we are using the preemptive scheduler then we also need to determine
+ if this tick should cause a context switch. */
+ #if configUSE_PREEMPTION == 1
+ vTaskSwitchContext();
+ #endif
+}
+/*-----------------------------------------------------------*/
+
+void zpu_disable_interrupts(void)
+{
+ *(volatile unsigned *) INTERRUPT_ENABLE &= ~INTERRUPT_GLOBAL_ENABLE;
+}
+
+void zpu_enable_interrupts(void)
+{
+ *(volatile unsigned *) INTERRUPT_ENABLE |= INTERRUPT_GLOBAL_ENABLE;
+}
+
+/*-----------------------------------------------------------*/
+
+void zpu_enter_critical(void)
+{
+ portDISABLE_INTERRUPTS();
+ uxCriticalNesting++;
+}
+
+void zpu_exit_critical(void)
+{
+ if( --uxCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
+}
diff --git a/zpu/sw/freertos/port/portasm.s b/zpu/sw/freertos/port/portasm.s
new file mode 100644
index 0000000..29c41ab
--- /dev/null
+++ b/zpu/sw/freertos/port/portasm.s
@@ -0,0 +1,142 @@
+ .extern pxCurrentTCB
+ .extern vTaskISRHandler
+ .extern vTaskSwitchContext
+ .extern uxCriticalNesting
+ .extern pulISRStack
+
+ .global __FreeRTOS_interrupt_handler
+ .global VPortYieldASM
+ .global vStartFirstTask
+
+/* interrupt controller port */
+ .equ INTERRUPT_ENABLE,0x8020
+
+.macro portSAVE_CONTEXT
+ /* PC is at the top of stack */
+
+ /* store interrupt global enable bit */
+ im INTERRUPT_ENABLE
+ load
+ im 1
+ and
+
+ /* Store nesting critical level */
+ im uxCriticalNesting
+ load
+
+ /* Store temporary registers */
+ im 0
+ load /* store mem[0] */
+ im 4
+ load /* store mem[4] */
+ im 8
+ load /* store mem[8] */
+ im 12
+ load /* store mem[12] */
+
+ /* Store top of stack at pxCurrentTCB */
+ pushsp
+ im pxCurrentTCB
+ load
+ store
+.endm
+
+.macro portRESTORE_CONTEXT
+ im pxCurrentTCB /* Load the top of stack value from the TCB. */
+ load
+ load
+ popsp
+
+ /* Restore the temporary registers. */
+ im 12
+ store /* restore mem[12] */
+ im 8
+ store /* restore mem[8] */
+ im 4
+ store /* restore mem[4] */
+ im 0
+ store /* restore mem[0] */
+
+ /* Load the critical nesting value. */
+ im uxCriticalNesting
+ store
+
+ /* Set interrupt global enable status */
+ im INTERRUPT_ENABLE
+ load
+ im ~1
+ and
+ or
+ im INTERRUPT_ENABLE
+ store
+
+ /* restore PC and enable interrupts at ZPU level */
+ .byte 0x03 /* popint */
+.endm
+
+.macro portRESTORE_CONTEXT_NOINTERRUPT
+ im pxCurrentTCB /* Load the top of stack value from the TCB. */
+ load
+ load
+ popsp
+
+ /* Restore the temporary registers. */
+ im 12
+ store /* restore mem[12] */
+ im 8
+ store /* restore mem[8] */
+ im 4
+ store /* restore mem[4] */
+ im 0
+ store /* restore mem[0] */
+
+ /* Load the critical nesting value. */
+ im uxCriticalNesting
+ store
+
+ /* Set interrupt global enable status */
+ im INTERRUPT_ENABLE
+ load
+ im ~1
+ and
+ or
+ im INTERRUPT_ENABLE
+ store
+
+ /* restore PC */
+ poppc
+.endm
+
+ .text
+ .align 2
+
+__FreeRTOS_interrupt_handler:
+ portSAVE_CONTEXT
+
+ /* Now switch to use the ISR stack. */
+ im pulISRStack
+ load
+ popsp
+
+ /* Call function */
+ im vTaskISRHandler
+ call
+
+ portRESTORE_CONTEXT
+
+VPortYieldASM:
+ portSAVE_CONTEXT
+
+ /* Now switch to use the ISR stack. */
+ im pulISRStack
+ load
+ popsp
+
+ /* Call function to switch context */
+ im vTaskSwitchContext
+ call
+
+ portRESTORE_CONTEXT_NOINTERRUPT
+
+vStartFirstTask:
+ portRESTORE_CONTEXT_NOINTERRUPT
diff --git a/zpu/sw/freertos/port/portmacro.h b/zpu/sw/freertos/port/portmacro.h
new file mode 100644
index 0000000..2b4d35a
--- /dev/null
+++ b/zpu/sw/freertos/port/portmacro.h
@@ -0,0 +1,125 @@
+/*
+ FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
+
+ This file is part of the FreeRTOS.org distribution.
+
+ FreeRTOS.org is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License (version 2) as published
+ by the Free Software Foundation and modified by the FreeRTOS exception.
+ **NOTE** The exception to the GPL is included to allow you to distribute a
+ combined work that includes FreeRTOS.org without being obliged to provide
+ the source code for any proprietary components. Alternative commercial
+ license and support terms are also available upon request. See the
+ licensing section of http://www.FreeRTOS.org for full details.
+
+ FreeRTOS.org is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details.
+
+ You should have received a copy of the GNU General Public License along
+ with FreeRTOS.org; if not, write to the Free Software Foundation, Inc., 59
+ Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+
+
+ ***************************************************************************
+ * *
+ * Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation *
+ * *
+ * This is a concise, step by step, 'hands on' guide that describes both *
+ * general multitasking concepts and FreeRTOS specifics. It presents and *
+ * explains numerous examples that are written using the FreeRTOS API. *
+ * Full source code for all the examples is provided in an accompanying *
+ * .zip file. *
+ * *
+ ***************************************************************************
+
+ 1 tab == 4 spaces!
+
+ Please ensure to read the configuration and relevant port sections of the
+ online documentation.
+
+ http://www.FreeRTOS.org - Documentation, latest information, license and
+ contact details.
+
+ http://www.SafeRTOS.com - A version that is certified for use in safety
+ critical systems.
+
+ http://www.OpenRTOS.com - Commercial support, development, porting,
+ licensing and training services.
+*/
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE unsigned portLONG
+#define portBASE_TYPE portLONG
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef unsigned portSHORT portTickType;
+ #define portMAX_DELAY ( portTickType ) 0xffff
+#else
+ typedef unsigned portLONG portTickType;
+ #define portMAX_DELAY ( portTickType ) 0xffffffff
+#endif
+/*-----------------------------------------------------------*/
+
+/* Interrupt control macros. */
+void zpu_disable_interrupts(void);
+void zpu_enable_interrupts(void);
+#define portDISABLE_INTERRUPTS() zpu_disable_interrupts()
+#define portENABLE_INTERRUPTS() zpu_enable_interrupts()
+/*-----------------------------------------------------------*/
+
+/* Critical section macros. */
+void zpu_enter_critical(void);
+void zpu_exit_critical(void);
+#define portENTER_CRITICAL() zpu_enter_critical()
+#define portEXIT_CRITICAL() zpu_exit_critical()
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+void vPortYield( void );
+#define portYIELD() vPortYield()
+
+void vTaskSwitchContext();
+#define portYIELD_FROM_ISR() vTaskSwitchContext()
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT 4
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
+#define portNOP() asm volatile ( "nop\n" )
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/zpu/sw/freertos/readme.txt b/zpu/sw/freertos/readme.txt
new file mode 100644
index 0000000..a1f1c89
--- /dev/null
+++ b/zpu/sw/freertos/readme.txt
@@ -0,0 +1,40 @@
+The FreeRTOS port was contributed by
+Antonio Anton <antonio.anton@anro-ingenieros.com>.
+
+Some of the files state that someone else is copyright
+holder, but I believe that to be copy and paste laziness
+and that, in fact, Antonio did this port.
+
+The port needs work, but is committed to ZPU git repository
+to get things started.
+
+Post questions to the zylin-zpu mailing list.
+
+Øyvind Harboe
+14/9-2009
+
+From Antonio:
+
+Ported version: 5.3.0
+Port goes to folder ${FREERTOS_ROOT}/Source/portable/GCC/ZPU
+
+portmacro.h : macro definitions for this port
+portasm.s : contains code for context switch, interrupt handler and
+other initializations
+port.c : other initialization functions that not need to be
+assembly code.
+
+(please note that #include <device.h> in port.c is specific for my ZPU
+port; it contains the definitions my peripherals)
+
+Each FreeRTOS application is compiled with the FreeRTOS port itself
+(source code).
+
+2nd file contains a sample application which includes the Makefile in
+order to compile & link against FreeRTOS port. It will link against some
+specific library (-lio) and specific linker file (sram-zpu.ld) which are
+not included. You must adapt these to your peripheral and memory
+configuration.
+
+At the moment there is no documentation but the source code is quite
+commented.
diff --git a/zpu/sw/freertos/sample/FreeRTOSConfig.h b/zpu/sw/freertos/sample/FreeRTOSConfig.h
new file mode 100644
index 0000000..d9470fd
--- /dev/null
+++ b/zpu/sw/freertos/sample/FreeRTOSConfig.h
@@ -0,0 +1,96 @@
+/*
+ FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
+
+ This file is part of the FreeRTOS.org distribution.
+
+ FreeRTOS.org is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License (version 2) as published
+ by the Free Software Foundation and modified by the FreeRTOS exception.
+ **NOTE** The exception to the GPL is included to allow you to distribute a
+ combined work that includes FreeRTOS.org without being obliged to provide
+ the source code for any proprietary components. Alternative commercial
+ license and support terms are also available upon request. See the
+ licensing section of http://www.FreeRTOS.org for full details.
+
+ FreeRTOS.org is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details.
+
+ You should have received a copy of the GNU General Public License along
+ with FreeRTOS.org; if not, write to the Free Software Foundation, Inc., 59
+ Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+
+
+ ***************************************************************************
+ * *
+ * Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation *
+ * *
+ * This is a concise, step by step, 'hands on' guide that describes both *
+ * general multitasking concepts and FreeRTOS specifics. It presents and *
+ * explains numerous examples that are written using the FreeRTOS API. *
+ * Full source code for all the examples is provided in an accompanying *
+ * .zip file. *
+ * *
+ ***************************************************************************
+
+ 1 tab == 4 spaces!
+
+ Please ensure to read the configuration and relevant port sections of the
+ online documentation.
+
+ http://www.FreeRTOS.org - Documentation, latest information, license and
+ contact details.
+
+ http://www.SafeRTOS.com - A version that is certified for use in safety
+ critical systems.
+
+ http://www.OpenRTOS.com - Commercial support, development, porting,
+ licensing and training services.
+*/
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION 1
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 25000000 )
+#define configTICK_RATE_HZ ( ( portTickType ) 100 )
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 )
+#define configMINIMAL_STACK_SIZE ( ( unsigned portLONG ) 256 )
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 8 * 1024 ) )
+#define configMAX_TASK_NAME_LEN ( 5 )
+#define configUSE_TRACE_FACILITY 0
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 0
+#define INCLUDE_vTaskCleanUpResources 0
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/zpu/sw/freertos/sample/Makefile b/zpu/sw/freertos/sample/Makefile
new file mode 100644
index 0000000..d3a6f6f
--- /dev/null
+++ b/zpu/sw/freertos/sample/Makefile
@@ -0,0 +1,50 @@
+PRJ = test1
+PATH_SW = /home/antonan/desarrollo/zpu/sw
+INCLUDES = $(PATH_SW)/freertos/Source/portable/GCC/ZPU/portmacro.h \
+ FreeRTOSConfig.h
+SRCS_C = $(PATH_SW)/freertos/Source/portable/GCC/ZPU/port.c \
+ $(PATH_SW)/freertos/Source/portable/MemMang/heap_1.c \
+ $(PATH_SW)/freertos/Source/croutine.c \
+ $(PATH_SW)/freertos/Source/list.c \
+ $(PATH_SW)/freertos/Source/queue.c \
+ $(PATH_SW)/freertos/Source/tasks.c \
+ test1.c
+SRCS_ASM = $(PATH_SW)/freertos/Source/portable/GCC/ZPU/portasm.s
+PATH_INC = -I$(PATH_SW)/include \
+ -I$(PATH_SW)/freertos/Source/include \
+ -I$(PATH_SW)/freertos/Source/portable/GCC/ZPU \
+ -I$(PATH_SW)/freertos/Demo/ZPU \
+ -I.
+OPTIONS = -g -Os -DGCC_ZPU
+LINK = -T $(PATH_SW)/ldscripts/zpu-sram.ld
+CRT = $(PATH_SW)/startup/crt-sram.o
+LLIB = -L $(PATH_SW)/lib
+LIBS = -lio -lgcc --start-group -lc -lbcc --end-group -lgcc -lio
+LFLAGS = --relax --gc-sections
+
+OBJS_ASM = $(SRCS_ASM:.s=.o)
+OBJS_C = $(SRCS_C:.c=.o)
+
+$(PRJ).srec: $(PRJ).out
+ zpu-elf-objcopy -O srec $(PRJ).out $(PRJ).srec
+ zpu-elf-objcopy -O binary $(PRJ).out $(PRJ).bin
+ bin2rom $(PRJ).bin $(PRJ).rom
+
+$(OBJS_ASM): $(SRCS_ASM)
+ zpu-elf-gcc $(OPTIONS) $(PATH_INC) -B. -c -Wa,-ahlms=$(@:.o=.lst) -o $@ $(@:.o=.s)
+
+$(OBJS_C): $(SRCS_C) $(INCLUDES)
+ zpu-elf-gcc $(OPTIONS) $(PATH_INC) -B. -c -Wa,-ahlms=$(@:.o=.lst) -o $@ $(@:.o=.c)
+
+$(PRJ).out: $(CRT) $(OBJS_C) $(OBJS_ASM)
+ zpu-elf-ld $(LLIB) $(LFLAGS) $(LINK) -Map=$(PRJ).map -o $(PRJ).out $(CRT) $(OBJS_C) $(OBJS_ASM) $(LIBS)
+
+
+clean:
+ -rm *.o
+ -rm *.out
+ -rm *.bin
+ -rm *.map
+ -rm *.lst
+ -rm *.srec
+ -rm *.rom
diff --git a/zpu/sw/freertos/sample/test1.c b/zpu/sw/freertos/sample/test1.c
new file mode 100644
index 0000000..41b4296
--- /dev/null
+++ b/zpu/sw/freertos/sample/test1.c
@@ -0,0 +1,67 @@
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#include "devices.h"
+
+#define mainTINY_STACK 256
+void vTest(void *pvParameters);
+void vTest2(void *pvParameters);
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Create all the demo tasks - then start the scheduler.
+ */
+int main (void)
+{
+ /* When re-starting a debug session (rather than cold booting) we want
+ to ensure the installed interrupt handlers do not execute until after the
+ scheduler has been started. */
+ portDISABLE_INTERRUPTS();
+
+ #if configUSE_PREEMPTION == 1
+ xTaskCreate( vTest, "TST1", mainTINY_STACK, ( void * ) 10, tskIDLE_PRIORITY, NULL );
+ xTaskCreate( vTest2, "TST2", mainTINY_STACK, ( void * ) 10, tskIDLE_PRIORITY, NULL );
+ #endif
+
+ /* Finally start the scheduler. */
+ vTaskStartScheduler();
+
+ /* Should not get here as the processor is now under control of the
+ scheduler! */
+
+ return 0;
+}
+
+void vTest(void *pvParameters)
+{
+const portTickType xDelay = 100 / portTICK_RATE_MS;
+ unsigned bit = 16;
+ unsigned dir = 0;
+
+ for(;;)
+ {
+ CLEAR_BIT(SP3SK_GPIO, bit);
+ if(dir == 0) { if(++bit == 23) { dir=1; } }
+ else { if(--bit == 16) { dir=0;} }
+ SET_BIT(SP3SK_GPIO, bit);
+ vTaskDelay( xDelay );
+ }
+}
+
+void vTest2(void *pvParameters)
+{
+const portTickType xDelay = 250 / portTICK_RATE_MS;
+ unsigned pos;
+ char marcas[] = "|/-\\";
+
+ for(;;)
+ {
+ uart1_printline("\r");
+ uart1_printline("Running...");
+ uart1_printchar(marcas[pos]);
+ if(++pos == 4) pos = 0;
+ vTaskDelay( xDelay );
+ }
+}
diff --git a/zpu/sw/helloworld/gmon.out b/zpu/sw/helloworld/gmon.out
new file mode 100644
index 0000000..86ca3d6
--- /dev/null
+++ b/zpu/sw/helloworld/gmon.out
Binary files differ
diff --git a/zpu/sw/helloworld/hello.bin b/zpu/sw/helloworld/hello.bin
new file mode 100644
index 0000000..4413b05
--- /dev/null
+++ b/zpu/sw/helloworld/hello.bin
Binary files differ
diff --git a/zpu/sw/helloworld/hello.bram b/zpu/sw/helloworld/hello.bram
new file mode 100644
index 0000000..f7e99e9
--- /dev/null
+++ b/zpu/sw/helloworld/hello.bram
@@ -0,0 +1,12441 @@
+0 => x"0b0b0b0b",
+1 => x"82700b0b",
+2 => x"82f4e00c",
+3 => x"3a0b0b81",
+4 => x"e48c0400",
+5 => x"00000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"81e4fd2d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
+17 => x"72830609",
+18 => x"81058205",
+19 => x"832b2a83",
+20 => x"ffff0652",
+21 => x"04000000",
+22 => x"00000000",
+23 => x"00000000",
+24 => x"71fd0608",
+25 => x"83ffff73",
+26 => x"83060981",
+27 => x"05820583",
+28 => x"2b2b0906",
+29 => x"7383ffff",
+30 => x"0b0b0b0b",
+31 => x"83a70400",
+32 => x"72098105",
+33 => x"72057373",
+34 => x"09060906",
+35 => x"73097306",
+36 => x"070a8106",
+37 => x"53510400",
+38 => x"00000000",
+39 => x"00000000",
+40 => x"72722473",
+41 => x"732e0753",
+42 => x"51040000",
+43 => x"00000000",
+44 => x"00000000",
+45 => x"00000000",
+46 => x"00000000",
+47 => x"00000000",
+48 => x"71737109",
+49 => x"71068106",
+50 => x"30720a10",
+51 => x"0a720a10",
+52 => x"0a31050a",
+53 => x"81065151",
+54 => x"53510400",
+55 => x"00000000",
+56 => x"72722673",
+57 => x"732e0753",
+58 => x"51040000",
+59 => x"00000000",
+60 => x"00000000",
+61 => x"00000000",
+62 => x"00000000",
+63 => x"00000000",
+64 => x"00000000",
+65 => x"00000000",
+66 => x"00000000",
+67 => x"00000000",
+68 => x"00000000",
+69 => x"00000000",
+70 => x"00000000",
+71 => x"00000000",
+72 => x"0b0b0b88",
+73 => x"c9040000",
+74 => x"00000000",
+75 => x"00000000",
+76 => x"00000000",
+77 => x"00000000",
+78 => x"00000000",
+79 => x"00000000",
+80 => x"720a722b",
+81 => x"0a535104",
+82 => x"00000000",
+83 => x"00000000",
+84 => x"00000000",
+85 => x"00000000",
+86 => x"00000000",
+87 => x"00000000",
+88 => x"72729f06",
+89 => x"0981050b",
+90 => x"0b0b88ac",
+91 => x"05040000",
+92 => x"00000000",
+93 => x"00000000",
+94 => x"00000000",
+95 => x"00000000",
+96 => x"72722aff",
+97 => x"739f062a",
+98 => x"0974090a",
+99 => x"8106ff05",
+100 => x"06075351",
+101 => x"04000000",
+102 => x"00000000",
+103 => x"00000000",
+104 => x"71715351",
+105 => x"020d0406",
+106 => x"73830609",
+107 => x"81058205",
+108 => x"832b0b2b",
+109 => x"0772fc06",
+110 => x"0c515104",
+111 => x"00000000",
+112 => x"72098105",
+113 => x"72050970",
+114 => x"81050906",
+115 => x"0a810653",
+116 => x"51040000",
+117 => x"00000000",
+118 => x"00000000",
+119 => x"00000000",
+120 => x"72098105",
+121 => x"72050970",
+122 => x"81050906",
+123 => x"0a098106",
+124 => x"53510400",
+125 => x"00000000",
+126 => x"00000000",
+127 => x"00000000",
+128 => x"71098105",
+129 => x"52040000",
+130 => x"00000000",
+131 => x"00000000",
+132 => x"00000000",
+133 => x"00000000",
+134 => x"00000000",
+135 => x"00000000",
+136 => x"72720981",
+137 => x"05055351",
+138 => x"04000000",
+139 => x"00000000",
+140 => x"00000000",
+141 => x"00000000",
+142 => x"00000000",
+143 => x"00000000",
+144 => x"72097206",
+145 => x"73730906",
+146 => x"07535104",
+147 => x"00000000",
+148 => x"00000000",
+149 => x"00000000",
+150 => x"00000000",
+151 => x"00000000",
+152 => x"71fc0608",
+153 => x"72830609",
+154 => x"81058305",
+155 => x"1010102a",
+156 => x"81ff0652",
+157 => x"04000000",
+158 => x"00000000",
+159 => x"00000000",
+160 => x"71fc0608",
+161 => x"0b0b82f4",
+162 => x"cc738306",
+163 => x"10100508",
+164 => x"060b0b0b",
+165 => x"88af0400",
+166 => x"00000000",
+167 => x"00000000",
+168 => x"80088408",
+169 => x"88087575",
+170 => x"0b0b0b8e",
+171 => x"c42d5050",
+172 => x"80085688",
+173 => x"0c840c80",
+174 => x"0c510400",
+175 => x"00000000",
+176 => x"80088408",
+177 => x"88087575",
+178 => x"0b0b0b90",
+179 => x"8d2d5050",
+180 => x"80085688",
+181 => x"0c840c80",
+182 => x"0c510400",
+183 => x"00000000",
+184 => x"72097081",
+185 => x"0509060a",
+186 => x"8106ff05",
+187 => x"70547106",
+188 => x"73097274",
+189 => x"05ff0506",
+190 => x"07515151",
+191 => x"04000000",
+192 => x"72097081",
+193 => x"0509060a",
+194 => x"098106ff",
+195 => x"05705471",
+196 => x"06730972",
+197 => x"7405ff05",
+198 => x"06075151",
+199 => x"51040000",
+200 => x"05ff0504",
+201 => x"00000000",
+202 => x"00000000",
+203 => x"00000000",
+204 => x"00000000",
+205 => x"00000000",
+206 => x"00000000",
+207 => x"00000000",
+208 => x"810b0b0b",
+209 => x"82f4dc0c",
+210 => x"51040000",
+211 => x"00000000",
+212 => x"00000000",
+213 => x"00000000",
+214 => x"00000000",
+215 => x"00000000",
+216 => x"71810552",
+217 => x"04000000",
+218 => x"00000000",
+219 => x"00000000",
+220 => x"00000000",
+221 => x"00000000",
+222 => x"00000000",
+223 => x"00000000",
+224 => x"00000000",
+225 => x"00000000",
+226 => x"00000000",
+227 => x"00000000",
+228 => x"00000000",
+229 => x"00000000",
+230 => x"00000000",
+231 => x"00000000",
+232 => x"02840572",
+233 => x"10100552",
+234 => x"04000000",
+235 => x"00000000",
+236 => x"00000000",
+237 => x"00000000",
+238 => x"00000000",
+239 => x"00000000",
+240 => x"00000000",
+241 => x"00000000",
+242 => x"00000000",
+243 => x"00000000",
+244 => x"00000000",
+245 => x"00000000",
+246 => x"00000000",
+247 => x"00000000",
+248 => x"717105ff",
+249 => x"05715351",
+250 => x"020d0400",
+251 => x"00000000",
+252 => x"00000000",
+253 => x"00000000",
+254 => x"00000000",
+255 => x"00000000",
+256 => x"0b0b0b83",
+257 => x"e93f0b0b",
+258 => x"82e4cc3f",
+259 => x"04101010",
+260 => x"10101010",
+261 => x"10101010",
+262 => x"10101010",
+263 => x"10101010",
+264 => x"10101010",
+265 => x"10101010",
+266 => x"10101010",
+267 => x"53510473",
+268 => x"81ff0673",
+269 => x"83060981",
+270 => x"05830510",
+271 => x"10102b07",
+272 => x"72fc060c",
+273 => x"5151043c",
+274 => x"04727280",
+275 => x"728106ff",
+276 => x"05097206",
+277 => x"05711052",
+278 => x"720a100a",
+279 => x"5372ed38",
+280 => x"51515351",
+281 => x"04fe3d0d",
+282 => x"0b0b8384",
+283 => x"e8085384",
+284 => x"13087088",
+285 => x"2a708106",
+286 => x"51525270",
+287 => x"802e0b0b",
+288 => x"0b0bec38",
+289 => x"7181ff06",
+290 => x"800c843d",
+291 => x"0d04ff3d",
+292 => x"0d0b0b83",
+293 => x"84e80852",
+294 => x"71087088",
+295 => x"2a813270",
+296 => x"81065151",
+297 => x"51700b0b",
+298 => x"0b0bed38",
+299 => x"73720c83",
+300 => x"3d0d040b",
+301 => x"0b82f4dc",
+302 => x"08802e0b",
+303 => x"0b0b0bae",
+304 => x"380b0b82",
+305 => x"f4e00882",
+306 => x"2e0b0b0b",
+307 => x"80c53883",
+308 => x"80800b0b",
+309 => x"0b8384e8",
+310 => x"0c82a080",
+311 => x"0b0b0b83",
+312 => x"84ec0c82",
+313 => x"90800b0b",
+314 => x"0b8384f0",
+315 => x"0c04f880",
+316 => x"8080a40b",
+317 => x"0b0b8384",
+318 => x"e80cf880",
+319 => x"8082800b",
+320 => x"0b0b8384",
+321 => x"ec0cf880",
+322 => x"8084800b",
+323 => x"0b0b8384",
+324 => x"f00c0480",
+325 => x"c0a8808c",
+326 => x"0b0b0b83",
+327 => x"84e80c80",
+328 => x"c0a88094",
+329 => x"0b0b0b83",
+330 => x"84ec0c0b",
+331 => x"0b82ed90",
+332 => x"0b0b0b83",
+333 => x"84f00c04",
+334 => x"f23d0d60",
+335 => x"0b0b8384",
+336 => x"ec08565d",
+337 => x"82750c80",
+338 => x"59805a80",
+339 => x"0b8f3d5d",
+340 => x"5b7a1010",
+341 => x"15700871",
+342 => x"08719f2c",
+343 => x"7e852b58",
+344 => x"55557d53",
+345 => x"59570b0b",
+346 => x"0b81d13f",
+347 => x"7d7f7a72",
+348 => x"077c7207",
+349 => x"71716081",
+350 => x"05415f5d",
+351 => x"5b595755",
+352 => x"817b270b",
+353 => x"0b0b0b8f",
+354 => x"38767d0c",
+355 => x"77841e0c",
+356 => x"7c800c90",
+357 => x"3d0d040b",
+358 => x"0b8384ec",
+359 => x"08550b0b",
+360 => x"0bffae39",
+361 => x"70700b0b",
+362 => x"8384f433",
+363 => x"51700b0b",
+364 => x"0b0bb738",
+365 => x"0b0b82f4",
+366 => x"e8087008",
+367 => x"52527080",
+368 => x"2e0b0b0b",
+369 => x"0b9c3884",
+370 => x"120b0b82",
+371 => x"f4e80c70",
+372 => x"2d0b0b82",
+373 => x"f4e80870",
+374 => x"08525270",
+375 => x"0b0b0b0b",
+376 => x"e638810b",
+377 => x"0b0b8384",
+378 => x"f4345050",
+379 => x"0404700b",
+380 => x"0b8384e4",
+381 => x"08802e0b",
+382 => x"0b0b0b92",
+383 => x"380b0b0b",
+384 => x"0b800b80",
+385 => x"2e098106",
+386 => x"0b0b0b0b",
+387 => x"83385004",
+388 => x"0b0b8384",
+389 => x"e4510b0b",
+390 => x"0bf3e53f",
+391 => x"5004048c",
+392 => x"08028c0c",
+393 => x"ff3d0d0b",
+394 => x"0b82ed94",
+395 => x"510b0b0b",
+396 => x"88ab3f71",
+397 => x"800c833d",
+398 => x"0d8c0c04",
+399 => x"8c08028c",
+400 => x"0cf53d0d",
+401 => x"8c089405",
+402 => x"080b0b0b",
+403 => x"0ba0388c",
+404 => x"088c0508",
+405 => x"8c089005",
+406 => x"088c0888",
+407 => x"05085856",
+408 => x"5473760c",
+409 => x"7484170c",
+410 => x"0b0b0b81",
+411 => x"ca39800b",
+412 => x"8c08f005",
+413 => x"0c800b8c",
+414 => x"08f4050c",
+415 => x"8c088c05",
+416 => x"088c0890",
+417 => x"05085654",
+418 => x"738c08f0",
+419 => x"050c748c",
+420 => x"08f4050c",
+421 => x"8c08f805",
+422 => x"8c08f005",
+423 => x"56568870",
+424 => x"54755376",
+425 => x"52540b0b",
+426 => x"0b85e03f",
+427 => x"a00b8c08",
+428 => x"94050831",
+429 => x"8c08ec05",
+430 => x"0c8c08ec",
+431 => x"05088024",
+432 => x"0b0b0b0b",
+433 => x"a138800b",
+434 => x"8c08f405",
+435 => x"0c8c08ec",
+436 => x"0508308c",
+437 => x"08fc0508",
+438 => x"712b8c08",
+439 => x"f0050c54",
+440 => x"0b0b0b0b",
+441 => x"b9398c08",
+442 => x"fc05088c",
+443 => x"08ec0508",
+444 => x"2a8c08e8",
+445 => x"050c8c08",
+446 => x"fc05088c",
+447 => x"08940508",
+448 => x"2b8c08f4",
+449 => x"050c8c08",
+450 => x"f805088c",
+451 => x"08940508",
+452 => x"2b708c08",
+453 => x"e8050807",
+454 => x"8c08f005",
+455 => x"0c548c08",
+456 => x"f005088c",
+457 => x"08f40508",
+458 => x"8c088805",
+459 => x"08585654",
+460 => x"73760c74",
+461 => x"84170c8c",
+462 => x"08880508",
+463 => x"800c8d3d",
+464 => x"0d8c0c04",
+465 => x"8c08028c",
+466 => x"0cf93d0d",
+467 => x"800b8c08",
+468 => x"fc050c8c",
+469 => x"08880508",
+470 => x"80250b0b",
+471 => x"0b0baf38",
+472 => x"8c088805",
+473 => x"08308c08",
+474 => x"88050c80",
+475 => x"0b8c08f4",
+476 => x"050c8c08",
+477 => x"fc05080b",
+478 => x"0b0b0b88",
+479 => x"38810b8c",
+480 => x"08f4050c",
+481 => x"8c08f405",
+482 => x"088c08fc",
+483 => x"050c8c08",
+484 => x"8c050880",
+485 => x"250b0b0b",
+486 => x"0baf388c",
+487 => x"088c0508",
+488 => x"308c088c",
+489 => x"050c800b",
+490 => x"8c08f005",
+491 => x"0c8c08fc",
+492 => x"05080b0b",
+493 => x"0b0b8838",
+494 => x"810b8c08",
+495 => x"f0050c8c",
+496 => x"08f00508",
+497 => x"8c08fc05",
+498 => x"0c80538c",
+499 => x"088c0508",
+500 => x"528c0888",
+501 => x"0508510b",
+502 => x"0b0b81bb",
+503 => x"3f800870",
+504 => x"8c08f805",
+505 => x"0c548c08",
+506 => x"fc050880",
+507 => x"2e0b0b0b",
+508 => x"0b8c388c",
+509 => x"08f80508",
+510 => x"308c08f8",
+511 => x"050c8c08",
+512 => x"f8050870",
+513 => x"800c5489",
+514 => x"3d0d8c0c",
+515 => x"048c0802",
+516 => x"8c0cfb3d",
+517 => x"0d800b8c",
+518 => x"08fc050c",
+519 => x"8c088805",
+520 => x"0880250b",
+521 => x"0b0b0b93",
+522 => x"388c0888",
+523 => x"0508308c",
+524 => x"0888050c",
+525 => x"810b8c08",
+526 => x"fc050c8c",
+527 => x"088c0508",
+528 => x"80250b0b",
+529 => x"0b0b8c38",
+530 => x"8c088c05",
+531 => x"08308c08",
+532 => x"8c050c81",
+533 => x"538c088c",
+534 => x"0508528c",
+535 => x"08880508",
+536 => x"510b0b0b",
+537 => x"0bb13f80",
+538 => x"08708c08",
+539 => x"f8050c54",
+540 => x"8c08fc05",
+541 => x"08802e0b",
+542 => x"0b0b0b8c",
+543 => x"388c08f8",
+544 => x"0508308c",
+545 => x"08f8050c",
+546 => x"8c08f805",
+547 => x"0870800c",
+548 => x"54873d0d",
+549 => x"8c0c048c",
+550 => x"08028c0c",
+551 => x"70707070",
+552 => x"810b8c08",
+553 => x"fc050c80",
+554 => x"0b8c08f8",
+555 => x"050c8c08",
+556 => x"8c05088c",
+557 => x"08880508",
+558 => x"270b0b0b",
+559 => x"0bb8388c",
+560 => x"08fc0508",
+561 => x"802e0b0b",
+562 => x"0b0bab38",
+563 => x"800b8c08",
+564 => x"8c050824",
+565 => x"0b0b0b0b",
+566 => x"9d388c08",
+567 => x"8c050810",
+568 => x"8c088c05",
+569 => x"0c8c08fc",
+570 => x"0508108c",
+571 => x"08fc050c",
+572 => x"0b0b0bff",
+573 => x"b9398c08",
+574 => x"fc050880",
+575 => x"2e0b0b0b",
+576 => x"80d0388c",
+577 => x"088c0508",
+578 => x"8c088805",
+579 => x"08260b0b",
+580 => x"0b0ba138",
+581 => x"8c088805",
+582 => x"088c088c",
+583 => x"0508318c",
+584 => x"0888050c",
+585 => x"8c08f805",
+586 => x"088c08fc",
+587 => x"0508078c",
+588 => x"08f8050c",
+589 => x"8c08fc05",
+590 => x"08812a8c",
+591 => x"08fc050c",
+592 => x"8c088c05",
+593 => x"08812a8c",
+594 => x"088c050c",
+595 => x"0b0b0bff",
+596 => x"a5398c08",
+597 => x"90050880",
+598 => x"2e0b0b0b",
+599 => x"0b93388c",
+600 => x"08880508",
+601 => x"708c08f4",
+602 => x"050c510b",
+603 => x"0b0b0b8d",
+604 => x"398c08f8",
+605 => x"0508708c",
+606 => x"08f4050c",
+607 => x"518c08f4",
+608 => x"0508800c",
+609 => x"50505050",
+610 => x"8c0c04fc",
+611 => x"3d0d7670",
+612 => x"797b5555",
+613 => x"55558f72",
+614 => x"270b0b0b",
+615 => x"0b903872",
+616 => x"75078306",
+617 => x"5170802e",
+618 => x"0b0b0b0b",
+619 => x"af38ff12",
+620 => x"5271ff2e",
+621 => x"0b0b0b0b",
+622 => x"9c387270",
+623 => x"81055433",
+624 => x"74708105",
+625 => x"5634ff12",
+626 => x"5271ff2e",
+627 => x"0981060b",
+628 => x"0b0b0be6",
+629 => x"3874800c",
+630 => x"863d0d04",
+631 => x"74517270",
+632 => x"84055408",
+633 => x"71708405",
+634 => x"530c7270",
+635 => x"84055408",
+636 => x"71708405",
+637 => x"530c7270",
+638 => x"84055408",
+639 => x"71708405",
+640 => x"530c7270",
+641 => x"84055408",
+642 => x"71708405",
+643 => x"530cf012",
+644 => x"52718f26",
+645 => x"0b0b0b0b",
+646 => x"c5388372",
+647 => x"270b0b0b",
+648 => x"0b993872",
+649 => x"70840554",
+650 => x"08717084",
+651 => x"05530cfc",
+652 => x"12527183",
+653 => x"260b0b0b",
+654 => x"0be93870",
+655 => x"540b0b0b",
+656 => x"feec39fb",
+657 => x"3d0d7789",
+658 => x"3d880555",
+659 => x"79548811",
+660 => x"0853510b",
+661 => x"0b0b80e3",
+662 => x"3f873d0d",
+663 => x"04fc3d0d",
+664 => x"873d7070",
+665 => x"84055208",
+666 => x"56537452",
+667 => x"0b0b82f4",
+668 => x"ec088811",
+669 => x"0852540b",
+670 => x"0b0bb4a2",
+671 => x"3f863d0d",
+672 => x"04707070",
+673 => x"70768811",
+674 => x"08545472",
+675 => x"0b0b0b0b",
+676 => x"8d387284",
+677 => x"150c7280",
+678 => x"0c505050",
+679 => x"50047352",
+680 => x"75510b0b",
+681 => x"80fcfe3f",
+682 => x"800b8815",
+683 => x"0c800b84",
+684 => x"150c8008",
+685 => x"800c5050",
+686 => x"505004fc",
+687 => x"c43d0d83",
+688 => x"bf3d0883",
+689 => x"c13d0883",
+690 => x"c33d0883",
+691 => x"c53d0848",
+692 => x"5e484b0b",
+693 => x"0b8186f6",
+694 => x"3f800808",
+695 => x"4c800b83",
+696 => x"bb3d0c80",
+697 => x"0b83bc3d",
+698 => x"0c807071",
+699 => x"698c0522",
+700 => x"70832a81",
+701 => x"32708106",
+702 => x"515d5d4c",
+703 => x"4f4d786d",
+704 => x"2e098106",
+705 => x"0b0b0b0b",
+706 => x"90386690",
+707 => x"05086d2e",
+708 => x"0981060b",
+709 => x"0b0b0b98",
+710 => x"3866510b",
+711 => x"0b0bbfc8",
+712 => x"3fff5980",
+713 => x"080b0b0b",
+714 => x"82893866",
+715 => x"8c05225a",
+716 => x"799a0659",
+717 => x"788a2e0b",
+718 => x"0b0b80ce",
+719 => x"387b83a6",
+720 => x"3d707183",
+721 => x"b93d0c5e",
+722 => x"475d800b",
+723 => x"83b83d0c",
+724 => x"800b83b7",
+725 => x"3d0c8049",
+726 => x"7c5e807d",
+727 => x"337081ff",
+728 => x"065b5b5b",
+729 => x"787b2e0b",
+730 => x"0b0b0b83",
+731 => x"38815b78",
+732 => x"a52e0b0b",
+733 => x"0b81c438",
+734 => x"7a802e0b",
+735 => x"0b0b81bb",
+736 => x"38811d5d",
+737 => x"0b0b0b0b",
+738 => x"d139668e",
+739 => x"05227090",
+740 => x"2b5a5b80",
+741 => x"79240b0b",
+742 => x"0bffa238",
+743 => x"79fd0659",
+744 => x"7882ba3d",
+745 => x"237a0284",
+746 => x"0589e205",
+747 => x"23669c05",
+748 => x"0882be3d",
+749 => x"0c66a405",
+750 => x"0882c03d",
+751 => x"0cb63d70",
+752 => x"82b83d0c",
+753 => x"82bb3d0c",
+754 => x"88800b82",
+755 => x"b93d0c88",
+756 => x"800b82bc",
+757 => x"3d0c800b",
+758 => x"82bd3d0c",
+759 => x"64537b52",
+760 => x"82b63d70",
+761 => x"52590b0b",
+762 => x"0bb1b33f",
+763 => x"80085a80",
+764 => x"0b800824",
+765 => x"0b0b0b0b",
+766 => x"95387851",
+767 => x"0b0b80ec",
+768 => x"bf3f8008",
+769 => x"802e0b0b",
+770 => x"0b0b8338",
+771 => x"ff5a82b9",
+772 => x"3d227086",
+773 => x"2a708106",
+774 => x"515a5b78",
+775 => x"802e0b0b",
+776 => x"0b0b8e38",
+777 => x"668c0522",
+778 => x"80c00759",
+779 => x"78678c05",
+780 => x"23795978",
+781 => x"800c83be",
+782 => x"3d0d047c",
+783 => x"7e315b7a",
+784 => x"802e0b0b",
+785 => x"0b0bb138",
+786 => x"7d7c0c7a",
+787 => x"841d0c83",
+788 => x"b73d081b",
+789 => x"83b83d0c",
+790 => x"881c83b7",
+791 => x"3d088111",
+792 => x"83b93d0c",
+793 => x"8111515a",
+794 => x"5c788724",
+795 => x"0b0b0b80",
+796 => x"cb38681b",
+797 => x"7d335b49",
+798 => x"7981ff06",
+799 => x"5978802e",
+800 => x"0b0b0bae",
+801 => x"df38811d",
+802 => x"5d807071",
+803 => x"4a4543ff",
+804 => x"416283be",
+805 => x"3d347c33",
+806 => x"5a7981ff",
+807 => x"06811e5e",
+808 => x"407fe005",
+809 => x"597880d8",
+810 => x"260b0b0b",
+811 => x"88a83878",
+812 => x"10100b0b",
+813 => x"82edc405",
+814 => x"59780804",
+815 => x"83be3ddc",
+816 => x"05526651",
+817 => x"0b0b0bfb",
+818 => x"b83f8008",
+819 => x"0b0b0b8b",
+820 => x"b3386569",
+821 => x"1c7e335c",
+822 => x"4a5c0b0b",
+823 => x"0bff9939",
+824 => x"62900743",
+825 => x"62842a70",
+826 => x"81065159",
+827 => x"780b0b0b",
+828 => x"9e873862",
+829 => x"862a7081",
+830 => x"06515978",
+831 => x"802e0b0b",
+832 => x"0b9df638",
+833 => x"64658405",
+834 => x"8212225d",
+835 => x"4659815f",
+836 => x"800b83be",
+837 => x"3d346044",
+838 => x"8061240b",
+839 => x"0b0b0b86",
+840 => x"3862feff",
+841 => x"0643657b",
+842 => x"30707d07",
+843 => x"9f2a6630",
+844 => x"7068079f",
+845 => x"2a720752",
+846 => x"5c515b5e",
+847 => x"79802e0b",
+848 => x"0b0b98fd",
+849 => x"387e812e",
+850 => x"0b0b0b8c",
+851 => x"8438817f",
+852 => x"250b0b0b",
+853 => x"a0eb387e",
+854 => x"822e0b0b",
+855 => x"0b8cc038",
+856 => x"0b0b82f0",
+857 => x"a85e7d51",
+858 => x"0b0b81c0",
+859 => x"ae3f8008",
+860 => x"5f7e427e",
+861 => x"64250b0b",
+862 => x"0b0b8338",
+863 => x"634283bd",
+864 => x"3d337081",
+865 => x"ff065a5b",
+866 => x"78802e0b",
+867 => x"0b0b9488",
+868 => x"38618105",
+869 => x"42628184",
+870 => x"0641600b",
+871 => x"0b0b8186",
+872 => x"38676231",
+873 => x"5a807a25",
+874 => x"0b0b0b80",
+875 => x"f938907a",
+876 => x"250b0b0b",
+877 => x"0bbd380b",
+878 => x"0b82eda4",
+879 => x"7c0c900b",
+880 => x"841d0c83",
+881 => x"b73d0890",
+882 => x"0583b83d",
+883 => x"0c881c83",
+884 => x"b73d0881",
+885 => x"1183b93d",
+886 => x"0c811151",
+887 => x"5a5c7887",
+888 => x"240b0b0b",
+889 => x"868e38f0",
+890 => x"1a5a7990",
+891 => x"240b0b0b",
+892 => x"0bc5380b",
+893 => x"0b82eda4",
+894 => x"7c0c7984",
+895 => x"1d0c83b7",
+896 => x"3d081a83",
+897 => x"b83d0c88",
+898 => x"1c83b73d",
+899 => x"08811183",
+900 => x"b93d0c81",
+901 => x"11515a5c",
+902 => x"7887240b",
+903 => x"0b0b96fe",
+904 => x"3883bd3d",
+905 => x"335b7a81",
+906 => x"ff065978",
+907 => x"802e0b0b",
+908 => x"0b938138",
+909 => x"83be3dfc",
+910 => x"057c0c81",
+911 => x"0b841d0c",
+912 => x"83b73d08",
+913 => x"810583b8",
+914 => x"3d0c881c",
+915 => x"83b73d08",
+916 => x"811183b9",
+917 => x"3d0c8111",
+918 => x"515a5c78",
+919 => x"87240b0b",
+920 => x"0b879f38",
+921 => x"6081802e",
+922 => x"0b0b0b85",
+923 => x"c938637f",
+924 => x"315a807a",
+925 => x"250b0b0b",
+926 => x"818c3890",
+927 => x"7a250b0b",
+928 => x"0b0bbd38",
+929 => x"0b0b82ed",
+930 => x"b47c0c90",
+931 => x"0b841d0c",
+932 => x"83b73d08",
+933 => x"900583b8",
+934 => x"3d0c881c",
+935 => x"83b73d08",
+936 => x"811183b9",
+937 => x"3d0c8111",
+938 => x"515a5c78",
+939 => x"87240b0b",
+940 => x"0b84e238",
+941 => x"f01a5a79",
+942 => x"90240b0b",
+943 => x"0b0bc538",
+944 => x"0b0b82ed",
+945 => x"b47c0c79",
+946 => x"841d0c83",
+947 => x"b73d081a",
+948 => x"83b83d0c",
+949 => x"881c83b7",
+950 => x"3d088111",
+951 => x"83b93d0c",
+952 => x"8111515a",
+953 => x"5c877925",
+954 => x"0b0b0b0b",
+955 => x"993883be",
+956 => x"3ddc0552",
+957 => x"66510b0b",
+958 => x"0bf7863f",
+959 => x"80080b0b",
+960 => x"0b878138",
+961 => x"655c6288",
+962 => x"2a813270",
+963 => x"81065159",
+964 => x"78802e0b",
+965 => x"0b0b91f3",
+966 => x"387d7c0c",
+967 => x"7e841d0c",
+968 => x"83b73d08",
+969 => x"1f83b83d",
+970 => x"0c881c83",
+971 => x"b73d0881",
+972 => x"1183b93d",
+973 => x"0c811151",
+974 => x"5a5c7887",
+975 => x"240b0b0b",
+976 => x"868c3862",
+977 => x"822a7081",
+978 => x"06515978",
+979 => x"802e0b0b",
+980 => x"0b819438",
+981 => x"6762315a",
+982 => x"807a250b",
+983 => x"0b0b8187",
+984 => x"38907a25",
+985 => x"0b0b0b0b",
+986 => x"bd380b0b",
+987 => x"82eda47c",
+988 => x"0c900b84",
+989 => x"1d0c83b7",
+990 => x"3d089005",
+991 => x"83b83d0c",
+992 => x"881c83b7",
+993 => x"3d088111",
+994 => x"83b93d0c",
+995 => x"8111515a",
+996 => x"5c788724",
+997 => x"0b0b0b85",
+998 => x"9438f01a",
+999 => x"5a799024",
+1000 => x"0b0b0b0b",
+1001 => x"c5380b0b",
+1002 => x"82eda47c",
+1003 => x"0c79841d",
+1004 => x"0c83b73d",
+1005 => x"081a83b8",
+1006 => x"3d0c83b6",
+1007 => x"3d088111",
+1008 => x"83b83d0c",
+1009 => x"81115159",
+1010 => x"8779250b",
+1011 => x"0b0b0b97",
+1012 => x"3883be3d",
+1013 => x"dc055266",
+1014 => x"510b0b0b",
+1015 => x"f5a33f80",
+1016 => x"080b0b0b",
+1017 => x"859e3861",
+1018 => x"59616825",
+1019 => x"0b0b0b0b",
+1020 => x"83386759",
+1021 => x"68194983",
+1022 => x"b73d080b",
+1023 => x"0b0b84ec",
+1024 => x"38800b83",
+1025 => x"b73d0c65",
+1026 => x"5c69802e",
+1027 => x"0b0b0bf6",
+1028 => x"c7386951",
+1029 => x"0b0b80ff",
+1030 => x"953f807d",
+1031 => x"5f4a0b0b",
+1032 => x"0bf6b739",
+1033 => x"62900743",
+1034 => x"62842a70",
+1035 => x"81065159",
+1036 => x"780b0b0b",
+1037 => x"97d43862",
+1038 => x"862a7081",
+1039 => x"06515978",
+1040 => x"802e0b0b",
+1041 => x"0b97c338",
+1042 => x"64658405",
+1043 => x"8212225d",
+1044 => x"4659805f",
+1045 => x"800b83be",
+1046 => x"3d340b0b",
+1047 => x"0bf9b739",
+1048 => x"62900743",
+1049 => x"62842a70",
+1050 => x"81065159",
+1051 => x"780b0b0b",
+1052 => x"97a93862",
+1053 => x"862a7081",
+1054 => x"06515978",
+1055 => x"802e0b0b",
+1056 => x"0b979838",
+1057 => x"64658405",
+1058 => x"7108902b",
+1059 => x"70902c51",
+1060 => x"5d465980",
+1061 => x"7b240b0b",
+1062 => x"0b8bdf38",
+1063 => x"815f0b0b",
+1064 => x"0bf8f339",
+1065 => x"64658405",
+1066 => x"71084a46",
+1067 => x"59678025",
+1068 => x"0b0b0bf7",
+1069 => x"e1386730",
+1070 => x"48628407",
+1071 => x"7d335b43",
+1072 => x"0b0b0bf7",
+1073 => x"d439811d",
+1074 => x"5d629007",
+1075 => x"7d335b43",
+1076 => x"0b0b0bf7",
+1077 => x"c4397f80",
+1078 => x"2e0b0b0b",
+1079 => x"a6863882",
+1080 => x"ce3d5e7f",
+1081 => x"7e34815f",
+1082 => x"800b83be",
+1083 => x"3d340b0b",
+1084 => x"0bf8fe39",
+1085 => x"83be3ddc",
+1086 => x"05526651",
+1087 => x"0b0b0bf3",
+1088 => x"803f8008",
+1089 => x"0b0b0b82",
+1090 => x"fb3865f0",
+1091 => x"1b5b5c0b",
+1092 => x"0b0bf9d6",
+1093 => x"3983be3d",
+1094 => x"dc055266",
+1095 => x"510b0b0b",
+1096 => x"f2df3f80",
+1097 => x"080b0b0b",
+1098 => x"82da3865",
+1099 => x"f01b5b5c",
+1100 => x"0b0b0bfb",
+1101 => x"82396762",
+1102 => x"315a807a",
+1103 => x"250b0b0b",
+1104 => x"faac3890",
+1105 => x"7a250b0b",
+1106 => x"0b0bbd38",
+1107 => x"0b0b82ed",
+1108 => x"b47c0c90",
+1109 => x"0b841d0c",
+1110 => x"83b73d08",
+1111 => x"900583b8",
+1112 => x"3d0c881c",
+1113 => x"83b73d08",
+1114 => x"811183b9",
+1115 => x"3d0c8111",
+1116 => x"515a5c78",
+1117 => x"87240b0b",
+1118 => x"0b80e638",
+1119 => x"f01a5a79",
+1120 => x"90240b0b",
+1121 => x"0b0bc538",
+1122 => x"0b0b82ed",
+1123 => x"b47c0c79",
+1124 => x"841d0c83",
+1125 => x"b73d081a",
+1126 => x"83b83d0c",
+1127 => x"881c83b7",
+1128 => x"3d088111",
+1129 => x"83b93d0c",
+1130 => x"8111515a",
+1131 => x"5c877925",
+1132 => x"0b0b0bf9",
+1133 => x"b93883be",
+1134 => x"3ddc0552",
+1135 => x"66510b0b",
+1136 => x"0bf1be3f",
+1137 => x"80080b0b",
+1138 => x"0b81b938",
+1139 => x"65646031",
+1140 => x"5b5c7980",
+1141 => x"240b0b0b",
+1142 => x"f9a1380b",
+1143 => x"0b0bfaa6",
+1144 => x"3983be3d",
+1145 => x"dc055266",
+1146 => x"510b0b0b",
+1147 => x"f1933f80",
+1148 => x"080b0b0b",
+1149 => x"818e3865",
+1150 => x"f01b5b5c",
+1151 => x"0b0b0bfe",
+1152 => x"fe3983be",
+1153 => x"3ddc0552",
+1154 => x"66510b0b",
+1155 => x"0bf0f23f",
+1156 => x"80080b0b",
+1157 => x"0b80ed38",
+1158 => x"655c6081",
+1159 => x"802e0981",
+1160 => x"060b0b0b",
+1161 => x"f8c8380b",
+1162 => x"0b0bfe8a",
+1163 => x"3983be3d",
+1164 => x"dc055266",
+1165 => x"510b0b0b",
+1166 => x"f0c73f80",
+1167 => x"080b0b0b",
+1168 => x"80c23865",
+1169 => x"f01b5b5c",
+1170 => x"0b0b0bfa",
+1171 => x"d03983be",
+1172 => x"3ddc0552",
+1173 => x"66510b0b",
+1174 => x"0bf0a63f",
+1175 => x"80080b0b",
+1176 => x"0b0ba138",
+1177 => x"655c0b0b",
+1178 => x"0bf9d839",
+1179 => x"83be3ddc",
+1180 => x"05526651",
+1181 => x"0b0b0bf0",
+1182 => x"883f8008",
+1183 => x"802e0b0b",
+1184 => x"0bfafe38",
+1185 => x"69802e0b",
+1186 => x"0b0b0b89",
+1187 => x"3869510b",
+1188 => x"0b80fa9a",
+1189 => x"3f668c05",
+1190 => x"2270862a",
+1191 => x"7081066b",
+1192 => x"5d515a47",
+1193 => x"78802e0b",
+1194 => x"0b0bf385",
+1195 => x"38ff590b",
+1196 => x"0b0bf2ff",
+1197 => x"397c3370",
+1198 => x"81ff065a",
+1199 => x"5a7880ec",
+1200 => x"2e0b0b0b",
+1201 => x"fc803862",
+1202 => x"90077a81",
+1203 => x"ff06811f",
+1204 => x"5f41430b",
+1205 => x"0b0bf3c9",
+1206 => x"397c7081",
+1207 => x"055e3340",
+1208 => x"7faa2e0b",
+1209 => x"0b0ba2f9",
+1210 => x"388060d0",
+1211 => x"0571435a",
+1212 => x"5a788926",
+1213 => x"0b0b0bf3",
+1214 => x"a8387910",
+1215 => x"10107a10",
+1216 => x"056005d0",
+1217 => x"057d7081",
+1218 => x"055f33d0",
+1219 => x"115b415a",
+1220 => x"8979270b",
+1221 => x"0b0b0be2",
+1222 => x"38794179",
+1223 => x"ff250b0b",
+1224 => x"0bf2fe38",
+1225 => x"ff410b0b",
+1226 => x"0bf2f639",
+1227 => x"64658405",
+1228 => x"71085d46",
+1229 => x"59820b0b",
+1230 => x"0b82f0c4",
+1231 => x"64720745",
+1232 => x"4f5f80f8",
+1233 => x"40800b83",
+1234 => x"be3d340b",
+1235 => x"0b0bf3c6",
+1236 => x"39897b27",
+1237 => x"0b0b0b0b",
+1238 => x"ac38ff1e",
+1239 => x"5e8a527a",
+1240 => x"510b0b82",
+1241 => x"9e803f80",
+1242 => x"08b00559",
+1243 => x"787e348a",
+1244 => x"527a510b",
+1245 => x"0b829dc4",
+1246 => x"3f80085b",
+1247 => x"7a89260b",
+1248 => x"0b0b0bd6",
+1249 => x"38ff1eb0",
+1250 => x"1c5a5e78",
+1251 => x"7e3483be",
+1252 => x"3d707f31",
+1253 => x"ff9c0540",
+1254 => x"5b0b0b0b",
+1255 => x"f3d339ff",
+1256 => x"1e7b8f06",
+1257 => x"6f055a5e",
+1258 => x"78337e34",
+1259 => x"7a842a5b",
+1260 => x"7a802e0b",
+1261 => x"0b0b0bd6",
+1262 => x"38ff1e7b",
+1263 => x"8f066f05",
+1264 => x"5a5e7833",
+1265 => x"7e347a84",
+1266 => x"2a5b7a0b",
+1267 => x"0b0b0bcf",
+1268 => x"380b0b0b",
+1269 => x"ffb83962",
+1270 => x"80c0077d",
+1271 => x"335b430b",
+1272 => x"0b0bf1b5",
+1273 => x"3960ff2e",
+1274 => x"0b0b0b9f",
+1275 => x"a0387f80",
+1276 => x"e7327030",
+1277 => x"70720780",
+1278 => x"256280c7",
+1279 => x"32703070",
+1280 => x"72078025",
+1281 => x"73075354",
+1282 => x"5e515b59",
+1283 => x"79802e0b",
+1284 => x"0b0b0b8a",
+1285 => x"38600b0b",
+1286 => x"0b0b8338",
+1287 => x"81416465",
+1288 => x"88058412",
+1289 => x"08720870",
+1290 => x"83bf3d0c",
+1291 => x"7183c03d",
+1292 => x"0c545446",
+1293 => x"590b0b81",
+1294 => x"adad3f80",
+1295 => x"08802e0b",
+1296 => x"0b0b95db",
+1297 => x"38805980",
+1298 => x"79545483",
+1299 => x"ba3d0883",
+1300 => x"bc3d085b",
+1301 => x"5179520b",
+1302 => x"0b8290c9",
+1303 => x"3f800b80",
+1304 => x"08240b0b",
+1305 => x"0b85f138",
+1306 => x"0b0b82f0",
+1307 => x"d85e835f",
+1308 => x"0b0b0bf1",
+1309 => x"fc3982ce",
+1310 => x"3d5e7f80",
+1311 => x"c32e0b0b",
+1312 => x"0b0b9238",
+1313 => x"62842a70",
+1314 => x"81065159",
+1315 => x"78802e0b",
+1316 => x"0b0b83d3",
+1317 => x"38885380",
+1318 => x"52b43d70",
+1319 => x"52590b0b",
+1320 => x"8188f23f",
+1321 => x"78546465",
+1322 => x"84057108",
+1323 => x"557f546c",
+1324 => x"5346590b",
+1325 => x"0b0ba0b1",
+1326 => x"3f80085f",
+1327 => x"8008ff2e",
+1328 => x"0b0b0bfb",
+1329 => x"bf38800b",
+1330 => x"83be3d34",
+1331 => x"0b0b0bf1",
+1332 => x"a0390b0b",
+1333 => x"82f0dc63",
+1334 => x"842a7081",
+1335 => x"06515a4e",
+1336 => x"780b0b0b",
+1337 => x"82ca3862",
+1338 => x"862a7081",
+1339 => x"06515978",
+1340 => x"802e0b0b",
+1341 => x"0b82b938",
+1342 => x"64658405",
+1343 => x"8212225d",
+1344 => x"46598263",
+1345 => x"81065a5f",
+1346 => x"7a802e0b",
+1347 => x"0b0bf080",
+1348 => x"3878802e",
+1349 => x"0b0b0bef",
+1350 => x"f738627f",
+1351 => x"0743800b",
+1352 => x"83be3d34",
+1353 => x"0b0b0bef",
+1354 => x"ed39800b",
+1355 => x"83be3d34",
+1356 => x"64658405",
+1357 => x"71084046",
+1358 => x"597d802e",
+1359 => x"0b0b0b9c",
+1360 => x"d4387f80",
+1361 => x"d32e0b0b",
+1362 => x"0b82c038",
+1363 => x"62842a70",
+1364 => x"81065159",
+1365 => x"780b0b0b",
+1366 => x"82b13880",
+1367 => x"61240b0b",
+1368 => x"0bf08338",
+1369 => x"60537852",
+1370 => x"7d510b0b",
+1371 => x"8183e73f",
+1372 => x"605f8008",
+1373 => x"802e0b0b",
+1374 => x"0beff638",
+1375 => x"80087e31",
+1376 => x"5f607f25",
+1377 => x"0b0b0bef",
+1378 => x"e838605f",
+1379 => x"0b0b0bef",
+1380 => x"e0396284",
+1381 => x"2a708106",
+1382 => x"5159780b",
+1383 => x"0b0b908d",
+1384 => x"3862862a",
+1385 => x"70810651",
+1386 => x"5978802e",
+1387 => x"0b0b0b8f",
+1388 => x"fc386465",
+1389 => x"84057108",
+1390 => x"52465968",
+1391 => x"79237c5e",
+1392 => x"0b0b0beb",
+1393 => x"9539ab0b",
+1394 => x"83be3d34",
+1395 => x"7c335a0b",
+1396 => x"0b0bedc5",
+1397 => x"39805a79",
+1398 => x"1010107a",
+1399 => x"10056005",
+1400 => x"d0057d70",
+1401 => x"81055f33",
+1402 => x"d0115b41",
+1403 => x"5a897927",
+1404 => x"0b0b0b0b",
+1405 => x"e2387948",
+1406 => x"0b0b0bed",
+1407 => x"a4396281",
+1408 => x"80077d33",
+1409 => x"5b430b0b",
+1410 => x"0bed8e39",
+1411 => x"6288077d",
+1412 => x"335b430b",
+1413 => x"0b0bed81",
+1414 => x"390b0b82",
+1415 => x"f0c46384",
+1416 => x"2a708106",
+1417 => x"515a4e78",
+1418 => x"802e0b0b",
+1419 => x"0bfdb838",
+1420 => x"64658405",
+1421 => x"71085d46",
+1422 => x"590b0b0b",
+1423 => x"fdc43962",
+1424 => x"81077d33",
+1425 => x"5b430b0b",
+1426 => x"0becce39",
+1427 => x"83bd3d33",
+1428 => x"59780b0b",
+1429 => x"0becbf38",
+1430 => x"a00b83be",
+1431 => x"3d347c33",
+1432 => x"5a0b0b0b",
+1433 => x"ecb33964",
+1434 => x"65840546",
+1435 => x"59831933",
+1436 => x"7e34815f",
+1437 => x"0b0b0bf4",
+1438 => x"ef397a30",
+1439 => x"5bad0b83",
+1440 => x"be3d3481",
+1441 => x"5f0b0b0b",
+1442 => x"ed8c397d",
+1443 => x"a23d0c80",
+1444 => x"705c5f88",
+1445 => x"537e52a6",
+1446 => x"3d70525a",
+1447 => x"0b0b8184",
+1448 => x"f43f7e61",
+1449 => x"240b0b0b",
+1450 => x"81c2387a",
+1451 => x"1010a23d",
+1452 => x"08055978",
+1453 => x"08802e0b",
+1454 => x"0b0b0bbd",
+1455 => x"38795478",
+1456 => x"085383be",
+1457 => x"3dfcc005",
+1458 => x"526a510b",
+1459 => x"0b0b9c99",
+1460 => x"3f8008ff",
+1461 => x"2e0b0b0b",
+1462 => x"f7aa3880",
+1463 => x"081f5978",
+1464 => x"61240b0b",
+1465 => x"0b0b9238",
+1466 => x"811b7940",
+1467 => x"5b78612e",
+1468 => x"0981060b",
+1469 => x"0b0bffb3",
+1470 => x"387e802e",
+1471 => x"0b0b0bec",
+1472 => x"f038811f",
+1473 => x"526a510b",
+1474 => x"0b80f1b6",
+1475 => x"3f80084a",
+1476 => x"8008802e",
+1477 => x"0b0b0bf6",
+1478 => x"fc388853",
+1479 => x"80527951",
+1480 => x"0b0b8183",
+1481 => x"f03f7955",
+1482 => x"7e5483be",
+1483 => x"3df38c05",
+1484 => x"5369526a",
+1485 => x"510b0b0b",
+1486 => x"9cb03f80",
+1487 => x"087f2e09",
+1488 => x"81060b0b",
+1489 => x"0bf6bd38",
+1490 => x"696a8008",
+1491 => x"055a5e80",
+1492 => x"79340b0b",
+1493 => x"0bec9a39",
+1494 => x"ad0b83be",
+1495 => x"3d340b0b",
+1496 => x"82f0d85e",
+1497 => x"835f0b0b",
+1498 => x"0bec8639",
+1499 => x"79557e54",
+1500 => x"83be3df3",
+1501 => x"8c05537e",
+1502 => x"526a510b",
+1503 => x"0b0b9bea",
+1504 => x"3f80085f",
+1505 => x"8008ff2e",
+1506 => x"0b0b0bf5",
+1507 => x"f7387da2",
+1508 => x"3d0c0b0b",
+1509 => x"0bfee239",
+1510 => x"620a100a",
+1511 => x"70810651",
+1512 => x"5978802e",
+1513 => x"0b0b0beb",
+1514 => x"ec386182",
+1515 => x"05420b0b",
+1516 => x"0bebe239",
+1517 => x"620a100a",
+1518 => x"70810651",
+1519 => x"5978802e",
+1520 => x"0b0b0bed",
+1521 => x"9f38b00b",
+1522 => x"82ce3d34",
+1523 => x"7f028405",
+1524 => x"8ab10534",
+1525 => x"83be3dfc",
+1526 => x"bc057c0c",
+1527 => x"820b841d",
+1528 => x"0c83b73d",
+1529 => x"08820583",
+1530 => x"b83d0c88",
+1531 => x"1c83b73d",
+1532 => x"08811183",
+1533 => x"b93d0c81",
+1534 => x"11515a5c",
+1535 => x"8779250b",
+1536 => x"0b0bece0",
+1537 => x"380b0b0b",
+1538 => x"f3f83980",
+1539 => x"e560250b",
+1540 => x"0b0b83da",
+1541 => x"38805980",
+1542 => x"79545483",
+1543 => x"ba3d0883",
+1544 => x"bc3d085b",
+1545 => x"5179520b",
+1546 => x"0b8282bd",
+1547 => x"3f80080b",
+1548 => x"0b0b87ff",
+1549 => x"380b0b82",
+1550 => x"f0f07c0c",
+1551 => x"810b841d",
+1552 => x"0c83b73d",
+1553 => x"08810583",
+1554 => x"b83d0c88",
+1555 => x"1c83b73d",
+1556 => x"08811183",
+1557 => x"b93d0c81",
+1558 => x"11515a5c",
+1559 => x"7887240b",
+1560 => x"0b0b81ce",
+1561 => x"38a43d08",
+1562 => x"5b7aa63d",
+1563 => x"08240b0b",
+1564 => x"0b0b8e38",
+1565 => x"62810659",
+1566 => x"78802e0b",
+1567 => x"0b0bedc3",
+1568 => x"386b7c0c",
+1569 => x"810b841d",
+1570 => x"0c83b73d",
+1571 => x"08810583",
+1572 => x"b83d0c88",
+1573 => x"1c83b73d",
+1574 => x"08811183",
+1575 => x"b93d0c81",
+1576 => x"11515a5c",
+1577 => x"7887240b",
+1578 => x"0b0b81c5",
+1579 => x"38ff1b5a",
+1580 => x"807a250b",
+1581 => x"0b0bed8b",
+1582 => x"38907a25",
+1583 => x"0b0b0b0b",
+1584 => x"bd380b0b",
+1585 => x"82edb47c",
+1586 => x"0c900b84",
+1587 => x"1d0c83b7",
+1588 => x"3d089005",
+1589 => x"83b83d0c",
+1590 => x"881c83b7",
+1591 => x"3d088111",
+1592 => x"83b93d0c",
+1593 => x"8111515a",
+1594 => x"5c788724",
+1595 => x"0b0b0b80",
+1596 => x"df38f01a",
+1597 => x"5a799024",
+1598 => x"0b0b0b0b",
+1599 => x"c5380b0b",
+1600 => x"82edb47c",
+1601 => x"0c79841d",
+1602 => x"0c83b73d",
+1603 => x"081a83b8",
+1604 => x"3d0c881c",
+1605 => x"83b73d08",
+1606 => x"811183b9",
+1607 => x"3d0c8111",
+1608 => x"515a5c87",
+1609 => x"79250b0b",
+1610 => x"0bec9838",
+1611 => x"0b0b0bf2",
+1612 => x"9d3983be",
+1613 => x"3ddc0552",
+1614 => x"66510b0b",
+1615 => x"0be2c23f",
+1616 => x"80080b0b",
+1617 => x"0bf2bd38",
+1618 => x"655c0b0b",
+1619 => x"0bfe9639",
+1620 => x"83be3ddc",
+1621 => x"05526651",
+1622 => x"0b0b0be2",
+1623 => x"a43f8008",
+1624 => x"0b0b0bf2",
+1625 => x"9f3865f0",
+1626 => x"1b5b5c0b",
+1627 => x"0b0bff85",
+1628 => x"3983be3d",
+1629 => x"dc055266",
+1630 => x"510b0b0b",
+1631 => x"e2833f80",
+1632 => x"080b0b0b",
+1633 => x"f1fe3865",
+1634 => x"a53d08ff",
+1635 => x"055b5c79",
+1636 => x"80240b0b",
+1637 => x"0bfea238",
+1638 => x"0b0b0beb",
+1639 => x"a63983be",
+1640 => x"3ddc0552",
+1641 => x"66510b0b",
+1642 => x"0be1d63f",
+1643 => x"80080b0b",
+1644 => x"0bf1d138",
+1645 => x"6583be3d",
+1646 => x"335c5c0b",
+1647 => x"0b0be8e6",
+1648 => x"397e0b0b",
+1649 => x"0bf3c738",
+1650 => x"62810659",
+1651 => x"78802e0b",
+1652 => x"0b0bf3ba",
+1653 => x"38028d8f",
+1654 => x"055eb07e",
+1655 => x"3483be3d",
+1656 => x"707f31ff",
+1657 => x"9c05405b",
+1658 => x"0b0b0be7",
+1659 => x"8439a43d",
+1660 => x"085b817b",
+1661 => x"250b0b0b",
+1662 => x"83bc387d",
+1663 => x"7081055f",
+1664 => x"3382ce3d",
+1665 => x"34ae0284",
+1666 => x"058ab105",
+1667 => x"3483be3d",
+1668 => x"fcbc057c",
+1669 => x"0c820b84",
+1670 => x"1d0c83b7",
+1671 => x"3d088205",
+1672 => x"83b83d0c",
+1673 => x"881c83b7",
+1674 => x"3d088111",
+1675 => x"83b93d0c",
+1676 => x"8111515a",
+1677 => x"5c788724",
+1678 => x"0b0b0b81",
+1679 => x"8b388059",
+1680 => x"80795454",
+1681 => x"83ba3d08",
+1682 => x"83bc3d08",
+1683 => x"5b517952",
+1684 => x"0b0b8280",
+1685 => x"a83f8008",
+1686 => x"802e0b0b",
+1687 => x"0b81a538",
+1688 => x"7d7c0cff",
+1689 => x"1b841d0c",
+1690 => x"83b73d08",
+1691 => x"1bff0583",
+1692 => x"b83d0c88",
+1693 => x"1c83b73d",
+1694 => x"08811183",
+1695 => x"b93d0c81",
+1696 => x"11515a5c",
+1697 => x"7887240b",
+1698 => x"0b0b81f7",
+1699 => x"3883be3d",
+1700 => x"e8057c0c",
+1701 => x"6c841d0c",
+1702 => x"83b73d08",
+1703 => x"6d0583b8",
+1704 => x"3d0c881c",
+1705 => x"83b73d08",
+1706 => x"811183b9",
+1707 => x"3d0c8111",
+1708 => x"515a5c87",
+1709 => x"79250b0b",
+1710 => x"0be98838",
+1711 => x"83be3ddc",
+1712 => x"05520b0b",
+1713 => x"0bef8d39",
+1714 => x"83be3ddc",
+1715 => x"05526651",
+1716 => x"0b0b0bdf",
+1717 => x"ac3f8008",
+1718 => x"0b0b0bef",
+1719 => x"a73865a5",
+1720 => x"3d085c5c",
+1721 => x"80598079",
+1722 => x"545483ba",
+1723 => x"3d0883bc",
+1724 => x"3d085b51",
+1725 => x"79520b0b",
+1726 => x"81ff823f",
+1727 => x"80080b0b",
+1728 => x"0bfedd38",
+1729 => x"ff1b5a80",
+1730 => x"7a250b0b",
+1731 => x"0bfefe38",
+1732 => x"907a250b",
+1733 => x"0b0b0bbd",
+1734 => x"380b0b82",
+1735 => x"edb47c0c",
+1736 => x"900b841d",
+1737 => x"0c83b73d",
+1738 => x"08900583",
+1739 => x"b83d0c88",
+1740 => x"1c83b73d",
+1741 => x"08811183",
+1742 => x"b93d0c81",
+1743 => x"11515a5c",
+1744 => x"7887240b",
+1745 => x"0b0b84c4",
+1746 => x"38f01a5a",
+1747 => x"7990240b",
+1748 => x"0b0b0bc5",
+1749 => x"380b0b82",
+1750 => x"edb47c0c",
+1751 => x"79841d0c",
+1752 => x"83b73d08",
+1753 => x"1a83b83d",
+1754 => x"0c881c83",
+1755 => x"b73d0881",
+1756 => x"1183b93d",
+1757 => x"0c811151",
+1758 => x"5a5c8779",
+1759 => x"250b0b0b",
+1760 => x"fe8b3883",
+1761 => x"be3ddc05",
+1762 => x"5266510b",
+1763 => x"0b0bddf1",
+1764 => x"3f80080b",
+1765 => x"0b0bedec",
+1766 => x"386583bf",
+1767 => x"3de80571",
+1768 => x"0c6d8412",
+1769 => x"0c83b83d",
+1770 => x"086e0583",
+1771 => x"b93d0c5c",
+1772 => x"0b0b0bfd",
+1773 => x"ed396281",
+1774 => x"0659780b",
+1775 => x"0b0bfcbb",
+1776 => x"387d7c0c",
+1777 => x"810b841d",
+1778 => x"0c83b73d",
+1779 => x"08810583",
+1780 => x"b83d0c88",
+1781 => x"1c83b73d",
+1782 => x"08811183",
+1783 => x"b93d0c81",
+1784 => x"11515a5c",
+1785 => x"8779250b",
+1786 => x"0b0bfda1",
+1787 => x"3883be3d",
+1788 => x"dc05520b",
+1789 => x"0b0bff91",
+1790 => x"39646584",
+1791 => x"0571085d",
+1792 => x"4659815f",
+1793 => x"0b0b0be2",
+1794 => x"87396465",
+1795 => x"84057108",
+1796 => x"5d465980",
+1797 => x"5f0b0b0b",
+1798 => x"e8ba3964",
+1799 => x"65840571",
+1800 => x"085d4659",
+1801 => x"7a80250b",
+1802 => x"0b0be8f0",
+1803 => x"380b0b0b",
+1804 => x"f4c839a5",
+1805 => x"3d085a80",
+1806 => x"7a250b0b",
+1807 => x"0b8bbd38",
+1808 => x"a43d085b",
+1809 => x"7a7a240b",
+1810 => x"0b0b83b5",
+1811 => x"387d7c0c",
+1812 => x"7a841d0c",
+1813 => x"83b73d08",
+1814 => x"1b83b83d",
+1815 => x"0c881c83",
+1816 => x"b73d0881",
+1817 => x"1183b93d",
+1818 => x"0c811151",
+1819 => x"5a5c7887",
+1820 => x"240b0b0b",
+1821 => x"81e33879",
+1822 => x"7b315a80",
+1823 => x"7a250b0b",
+1824 => x"0b818c38",
+1825 => x"907a250b",
+1826 => x"0b0b0bbd",
+1827 => x"380b0b82",
+1828 => x"edb47c0c",
+1829 => x"900b841d",
+1830 => x"0c83b73d",
+1831 => x"08900583",
+1832 => x"b83d0c88",
+1833 => x"1c83b73d",
+1834 => x"08811183",
+1835 => x"b93d0c81",
+1836 => x"11515a5c",
+1837 => x"7887240b",
+1838 => x"0b0b80fc",
+1839 => x"38f01a5a",
+1840 => x"7990240b",
+1841 => x"0b0b0bc5",
+1842 => x"380b0b82",
+1843 => x"edb47c0c",
+1844 => x"79841d0c",
+1845 => x"83b73d08",
+1846 => x"1a83b83d",
+1847 => x"0c881c83",
+1848 => x"b73d0881",
+1849 => x"1183b93d",
+1850 => x"0c811151",
+1851 => x"5a5c8779",
+1852 => x"250b0b0b",
+1853 => x"0b993883",
+1854 => x"be3ddc05",
+1855 => x"5266510b",
+1856 => x"0b0bdafd",
+1857 => x"3f80080b",
+1858 => x"0b0beaf8",
+1859 => x"38655c62",
+1860 => x"81065978",
+1861 => x"802e0b0b",
+1862 => x"0be4a838",
+1863 => x"0b0b82f0",
+1864 => x"f47c0c81",
+1865 => x"0b841d0c",
+1866 => x"83b73d08",
+1867 => x"810583b8",
+1868 => x"3d0c0b0b",
+1869 => x"0bfaeb39",
+1870 => x"83be3ddc",
+1871 => x"05526651",
+1872 => x"0b0b0bda",
+1873 => x"bc3f8008",
+1874 => x"0b0b0bea",
+1875 => x"b73865f0",
+1876 => x"1b5b5c0b",
+1877 => x"0b0bfee8",
+1878 => x"3983be3d",
+1879 => x"dc055266",
+1880 => x"510b0b0b",
+1881 => x"da9b3f80",
+1882 => x"080b0b0b",
+1883 => x"ea963865",
+1884 => x"a63d08a6",
+1885 => x"3d087171",
+1886 => x"31525d5b",
+1887 => x"5c798024",
+1888 => x"0b0b0bfd",
+1889 => x"ff380b0b",
+1890 => x"0bff8439",
+1891 => x"83be3ddc",
+1892 => x"05526651",
+1893 => x"0b0b0bd9",
+1894 => x"e83f8008",
+1895 => x"0b0b0be9",
+1896 => x"e33865f0",
+1897 => x"1b5b5c0b",
+1898 => x"0b0bfba0",
+1899 => x"39646584",
+1900 => x"0571086b",
+1901 => x"710c527e",
+1902 => x"4046590b",
+1903 => x"0b0bdb9a",
+1904 => x"397e0b0b",
+1905 => x"0bdf9938",
+1906 => x"ff1e7bb7",
+1907 => x"06b0075b",
+1908 => x"5e797e34",
+1909 => x"7a832a5b",
+1910 => x"7a0b0b0b",
+1911 => x"0bea3862",
+1912 => x"81065978",
+1913 => x"802e0b0b",
+1914 => x"0beba338",
+1915 => x"79b02e0b",
+1916 => x"0b0beb9a",
+1917 => x"38ff1e5e",
+1918 => x"b07e340b",
+1919 => x"0b0bf7dd",
+1920 => x"397d7c0c",
+1921 => x"79841d0c",
+1922 => x"83b73d08",
+1923 => x"1a83b83d",
+1924 => x"0c881c83",
+1925 => x"b73d0881",
+1926 => x"1183b93d",
+1927 => x"0c811151",
+1928 => x"5a5c7887",
+1929 => x"240b0b0b",
+1930 => x"81a03879",
+1931 => x"1e0b0b82",
+1932 => x"f0f47d0c",
+1933 => x"5e810b84",
+1934 => x"1d0c83b7",
+1935 => x"3d088105",
+1936 => x"83b83d0c",
+1937 => x"881c83b7",
+1938 => x"3d088111",
+1939 => x"83b93d0c",
+1940 => x"8111515a",
+1941 => x"5c788724",
+1942 => x"0b0b0b0b",
+1943 => x"b6387d7c",
+1944 => x"0ca43d08",
+1945 => x"7a317084",
+1946 => x"1e0c83b8",
+1947 => x"3d080583",
+1948 => x"b83d0c88",
+1949 => x"1c83b73d",
+1950 => x"08811183",
+1951 => x"b93d0c81",
+1952 => x"11515a5c",
+1953 => x"8779250b",
+1954 => x"0b0be1b7",
+1955 => x"380b0b0b",
+1956 => x"e7bc3983",
+1957 => x"be3ddc05",
+1958 => x"5266510b",
+1959 => x"0b0bd7e1",
+1960 => x"3f80080b",
+1961 => x"0b0be7dc",
+1962 => x"3865a63d",
+1963 => x"087f720c",
+1964 => x"a63d0871",
+1965 => x"31708414",
+1966 => x"0c83ba3d",
+1967 => x"080583ba",
+1968 => x"3d0c5b5c",
+1969 => x"0b0b0bff",
+1970 => x"aa3983be",
+1971 => x"3ddc0552",
+1972 => x"66510b0b",
+1973 => x"0bd7aa3f",
+1974 => x"80080b0b",
+1975 => x"0be7a538",
+1976 => x"65a63d08",
+1977 => x"7f110b0b",
+1978 => x"82f0f473",
+1979 => x"0c405b5c",
+1980 => x"810b841d",
+1981 => x"0c83b73d",
+1982 => x"08810583",
+1983 => x"b83d0c88",
+1984 => x"1c83b73d",
+1985 => x"08811183",
+1986 => x"b93d0c81",
+1987 => x"11515a5c",
+1988 => x"8779250b",
+1989 => x"0b0bfec6",
+1990 => x"380b0b0b",
+1991 => x"fef53983",
+1992 => x"ba3d0883",
+1993 => x"bc3d085b",
+1994 => x"5179520b",
+1995 => x"0b8197ea",
+1996 => x"3f0b0b82",
+1997 => x"f0f85e83",
+1998 => x"5f80080b",
+1999 => x"0b0bdcb1",
+2000 => x"38628280",
+2001 => x"0783bb3d",
+2002 => x"0883bd3d",
+2003 => x"086383c0",
+2004 => x"3daa3da5",
+2005 => x"3d0c5f45",
+2006 => x"415f4383",
+2007 => x"0ba13d0c",
+2008 => x"7f80e62e",
+2009 => x"0b0b0b0b",
+2010 => x"b1388008",
+2011 => x"5a7f80e5",
+2012 => x"2e0b0b0b",
+2013 => x"83ea3880",
+2014 => x"08597f80",
+2015 => x"c52e0b0b",
+2016 => x"0b83f038",
+2017 => x"79790759",
+2018 => x"78802e0b",
+2019 => x"0b0b0b85",
+2020 => x"38608105",
+2021 => x"42820ba1",
+2022 => x"3d0c7db3",
+2023 => x"3d0c7eb4",
+2024 => x"3d0c800b",
+2025 => x"b33d0824",
+2026 => x"0b0b0b88",
+2027 => x"ef38807b",
+2028 => x"3483be3d",
+2029 => x"f3941159",
+2030 => x"f3900557",
+2031 => x"6e566155",
+2032 => x"6f547d52",
+2033 => x"7e536a51",
+2034 => x"0b0b0b9b",
+2035 => x"b03f8008",
+2036 => x"6080e732",
+2037 => x"70307072",
+2038 => x"079f2a51",
+2039 => x"5b5ba13d",
+2040 => x"0c7f80c7",
+2041 => x"2e0b0b0b",
+2042 => x"0b883878",
+2043 => x"0b0b0b81",
+2044 => x"e4386281",
+2045 => x"0659780b",
+2046 => x"0b0b81d9",
+2047 => x"38a33d08",
+2048 => x"5978a13d",
+2049 => x"0831a53d",
+2050 => x"0c6f6080",
+2051 => x"e7327030",
+2052 => x"70720780",
+2053 => x"256380c7",
+2054 => x"32703070",
+2055 => x"72078025",
+2056 => x"73075354",
+2057 => x"5f515c5a",
+2058 => x"5e79802e",
+2059 => x"0b0b0b86",
+2060 => x"f238a53d",
+2061 => x"085afc7a",
+2062 => x"250b0b0b",
+2063 => x"0b8a3860",
+2064 => x"7a250b0b",
+2065 => x"0b82cc38",
+2066 => x"80e5597f",
+2067 => x"80e72e0b",
+2068 => x"0b0b0b84",
+2069 => x"3880c559",
+2070 => x"78407f80",
+2071 => x"e5240b0b",
+2072 => x"0b86ca38",
+2073 => x"ff1a70a7",
+2074 => x"3d0c83b9",
+2075 => x"3d715d43",
+2076 => x"5a7f6234",
+2077 => x"028ddd05",
+2078 => x"5f807a24",
+2079 => x"0b0b0b87",
+2080 => x"c138ab7f",
+2081 => x"34028dde",
+2082 => x"05b33d70",
+2083 => x"5c425f89",
+2084 => x"7b250b0b",
+2085 => x"0b818738",
+2086 => x"ff1a8a7c",
+2087 => x"36b0055a",
+2088 => x"5a787a34",
+2089 => x"8a7b355b",
+2090 => x"7a89240b",
+2091 => x"0b0b0be8",
+2092 => x"38ff1ab0",
+2093 => x"1c5a5a78",
+2094 => x"7a347961",
+2095 => x"270b0b0b",
+2096 => x"80ed3879",
+2097 => x"7081055b",
+2098 => x"337f7081",
+2099 => x"0541340b",
+2100 => x"0b0b0be6",
+2101 => x"39800862",
+2102 => x"055b7f80",
+2103 => x"e62e0b0b",
+2104 => x"0b819838",
+2105 => x"80598079",
+2106 => x"54547d51",
+2107 => x"7e520b0b",
+2108 => x"81f0f63f",
+2109 => x"80080b0b",
+2110 => x"0b0b8538",
+2111 => x"7aa43d0c",
+2112 => x"a33d0859",
+2113 => x"787b270b",
+2114 => x"0b0bfdf5",
+2115 => x"38b07934",
+2116 => x"a33d0881",
+2117 => x"05a43d0c",
+2118 => x"0b0b0b0b",
+2119 => x"e339b07f",
+2120 => x"70810541",
+2121 => x"34b01b59",
+2122 => x"787f7081",
+2123 => x"0541347e",
+2124 => x"6231a53d",
+2125 => x"08701241",
+2126 => x"5a4d8179",
+2127 => x"250b0b0b",
+2128 => x"81a43881",
+2129 => x"1f5f83bc",
+2130 => x"3d335978",
+2131 => x"802e0b0b",
+2132 => x"0bd89e38",
+2133 => x"ad0b83be",
+2134 => x"3d340b0b",
+2135 => x"0bd89239",
+2136 => x"810b8008",
+2137 => x"5a5a7f80",
+2138 => x"c52e0981",
+2139 => x"060b0b0b",
+2140 => x"fc923881",
+2141 => x"590b0b0b",
+2142 => x"fc8a3980",
+2143 => x"08335978",
+2144 => x"b02e0b0b",
+2145 => x"0b0bb438",
+2146 => x"6e087b05",
+2147 => x"5b0b0b0b",
+2148 => x"fed23980",
+2149 => x"e740a43d",
+2150 => x"0859787a",
+2151 => x"240b0b0b",
+2152 => x"85883879",
+2153 => x"6381065a",
+2154 => x"5f78802e",
+2155 => x"0b0b0bff",
+2156 => x"9538811a",
+2157 => x"5f0b0b0b",
+2158 => x"ff8c3980",
+2159 => x"59807954",
+2160 => x"547d517e",
+2161 => x"520b0b81",
+2162 => x"f1b33f80",
+2163 => x"08802e0b",
+2164 => x"0b0bffb4",
+2165 => x"38816231",
+2166 => x"70a13d08",
+2167 => x"0c7b055b",
+2168 => x"0b0b0bfd",
+2169 => x"ff396281",
+2170 => x"06597880",
+2171 => x"2e0b0b0b",
+2172 => x"fed43881",
+2173 => x"1f5f0b0b",
+2174 => x"0bfecb39",
+2175 => x"0b0b82f0",
+2176 => x"f07c0c81",
+2177 => x"0b841d0c",
+2178 => x"83b73d08",
+2179 => x"810583b8",
+2180 => x"3d0c881c",
+2181 => x"83b73d08",
+2182 => x"811183b9",
+2183 => x"3d0c8111",
+2184 => x"515a5c78",
+2185 => x"87240b0b",
+2186 => x"0b829238",
+2187 => x"790b0b0b",
+2188 => x"0b8c38a4",
+2189 => x"3d08802e",
+2190 => x"0b0b0bda",
+2191 => x"86386b7c",
+2192 => x"0c810b84",
+2193 => x"1d0c83b7",
+2194 => x"3d088105",
+2195 => x"83b83d0c",
+2196 => x"881c83b7",
+2197 => x"3d088111",
+2198 => x"83b93d0c",
+2199 => x"8111515a",
+2200 => x"5c788724",
+2201 => x"0b0b0b81",
+2202 => x"f6387930",
+2203 => x"5a807a25",
+2204 => x"0b0b0b81",
+2205 => x"8c38907a",
+2206 => x"250b0b0b",
+2207 => x"0bbd380b",
+2208 => x"0b82edb4",
+2209 => x"7c0c900b",
+2210 => x"841d0c83",
+2211 => x"b73d0890",
+2212 => x"0583b83d",
+2213 => x"0c881c83",
+2214 => x"b73d0881",
+2215 => x"1183b93d",
+2216 => x"0c811151",
+2217 => x"5a5c7887",
+2218 => x"240b0b0b",
+2219 => x"80ee38f0",
+2220 => x"1a5a7990",
+2221 => x"240b0b0b",
+2222 => x"0bc5380b",
+2223 => x"0b82edb4",
+2224 => x"7c0c7984",
+2225 => x"1d0c83b7",
+2226 => x"3d081a83",
+2227 => x"b83d0c88",
+2228 => x"1c83b73d",
+2229 => x"08811183",
+2230 => x"b93d0c81",
+2231 => x"11515a5c",
+2232 => x"8779250b",
+2233 => x"0b0b0b99",
+2234 => x"3883be3d",
+2235 => x"dc055266",
+2236 => x"510b0b0b",
+2237 => x"cf8b3f80",
+2238 => x"080b0b0b",
+2239 => x"df863865",
+2240 => x"5c7d7c0c",
+2241 => x"a43d0884",
+2242 => x"1d0c83b7",
+2243 => x"3d08a53d",
+2244 => x"080583b8",
+2245 => x"3d0c0b0b",
+2246 => x"0bef8739",
+2247 => x"83be3ddc",
+2248 => x"05526651",
+2249 => x"0b0b0bce",
+2250 => x"d83f8008",
+2251 => x"0b0b0bde",
+2252 => x"d33865f0",
+2253 => x"1b5b5c0b",
+2254 => x"0b0bfef6",
+2255 => x"3983be3d",
+2256 => x"dc055266",
+2257 => x"510b0b0b",
+2258 => x"ceb73f80",
+2259 => x"080b0b0b",
+2260 => x"deb23865",
+2261 => x"a63d085b",
+2262 => x"5c0b0b0b",
+2263 => x"fdce3983",
+2264 => x"be3ddc05",
+2265 => x"5266510b",
+2266 => x"0b0bce95",
+2267 => x"3f80080b",
+2268 => x"0b0bde90",
+2269 => x"3865a63d",
+2270 => x"08703051",
+2271 => x"5b5c7980",
+2272 => x"240b0b0b",
+2273 => x"fdf0380b",
+2274 => x"0b0bfef5",
+2275 => x"3986410b",
+2276 => x"0b0be18a",
+2277 => x"390b0b82",
+2278 => x"f0fc5e86",
+2279 => x"5f0b0b0b",
+2280 => x"d3cf39a5",
+2281 => x"3d085a0b",
+2282 => x"0b0bf9ae",
+2283 => x"397f80e6",
+2284 => x"2e098106",
+2285 => x"0b0b0bfb",
+2286 => x"dd38807a",
+2287 => x"250b0b0b",
+2288 => x"81bc3879",
+2289 => x"5f600b0b",
+2290 => x"0b0b8e38",
+2291 => x"62810659",
+2292 => x"78802e0b",
+2293 => x"0b0bfaee",
+2294 => x"38601a81",
+2295 => x"055f0b0b",
+2296 => x"0bfae339",
+2297 => x"83b73d08",
+2298 => x"0b0b0b0b",
+2299 => x"8d38800b",
+2300 => x"83b73d0c",
+2301 => x"0b0b0bdd",
+2302 => x"8b3983be",
+2303 => x"3ddc0552",
+2304 => x"66510b0b",
+2305 => x"0bccfa3f",
+2306 => x"80080b0b",
+2307 => x"0bdcf538",
+2308 => x"800b83b7",
+2309 => x"3d0c0b0b",
+2310 => x"0bdce939",
+2311 => x"7d810a32",
+2312 => x"5ead7b34",
+2313 => x"0b0b0bf7",
+2314 => x"8839787a",
+2315 => x"3182055f",
+2316 => x"807a250b",
+2317 => x"0b0bfa8e",
+2318 => x"3881195f",
+2319 => x"0b0b0bfa",
+2320 => x"85397930",
+2321 => x"5bad7f34",
+2322 => x"028dde05",
+2323 => x"b33d705c",
+2324 => x"425f897b",
+2325 => x"250b0b0b",
+2326 => x"f9c4380b",
+2327 => x"0b0bf8b8",
+2328 => x"39646584",
+2329 => x"05710843",
+2330 => x"46596080",
+2331 => x"250b0b0b",
+2332 => x"d0a438ff",
+2333 => x"7d335b41",
+2334 => x"0b0b0bd0",
+2335 => x"9c39600b",
+2336 => x"0b0b0b90",
+2337 => x"38628106",
+2338 => x"59815f78",
+2339 => x"802e0b0b",
+2340 => x"0bf9b338",
+2341 => x"6082055f",
+2342 => x"0b0b0bf9",
+2343 => x"a939fc3d",
+2344 => x"0d0b0b82",
+2345 => x"f4ec0855",
+2346 => x"b8150880",
+2347 => x"2e0b0b0b",
+2348 => x"0b983878",
+2349 => x"54775376",
+2350 => x"520b0b82",
+2351 => x"f4ec0851",
+2352 => x"0b0b0bcb",
+2353 => x"f63f863d",
+2354 => x"0d047451",
+2355 => x"0b0b0bbe",
+2356 => x"8e3f7854",
+2357 => x"77537652",
+2358 => x"0b0b82f4",
+2359 => x"ec08510b",
+2360 => x"0b0bcbd7",
+2361 => x"3f863d0d",
+2362 => x"04f63d0d",
+2363 => x"7c7e6159",
+2364 => x"56588056",
+2365 => x"74762e0b",
+2366 => x"0b0b0ba3",
+2367 => x"3876547e",
+2368 => x"53745277",
+2369 => x"510b0b0b",
+2370 => x"83823f80",
+2371 => x"08558008",
+2372 => x"ff2e0b0b",
+2373 => x"0b0ba938",
+2374 => x"74800c8c",
+2375 => x"3d0d0476",
+2376 => x"5475538c",
+2377 => x"3df40552",
+2378 => x"77510b0b",
+2379 => x"0b82dd3f",
+2380 => x"80085580",
+2381 => x"08ff2e09",
+2382 => x"81060b0b",
+2383 => x"0b0bd938",
+2384 => x"80770c81",
+2385 => x"8a780c74",
+2386 => x"800c8c3d",
+2387 => x"0d047070",
+2388 => x"70707754",
+2389 => x"76537552",
+2390 => x"0b0b82f4",
+2391 => x"ec08510b",
+2392 => x"0b0bff85",
+2393 => x"3f505050",
+2394 => x"5004ec3d",
+2395 => x"0d66686a",
+2396 => x"6c6e735c",
+2397 => x"405d4242",
+2398 => x"4260802e",
+2399 => x"0b0b0b81",
+2400 => x"b2388060",
+2401 => x"085a5d7c",
+2402 => x"7a270b0b",
+2403 => x"0b819b38",
+2404 => x"933d5b7b",
+2405 => x"08841d08",
+2406 => x"7d567a08",
+2407 => x"557c5463",
+2408 => x"53405e0b",
+2409 => x"0b0bfec1",
+2410 => x"3f800858",
+2411 => x"8008ff2e",
+2412 => x"0b0b0b81",
+2413 => x"9538807a",
+2414 => x"80083156",
+2415 => x"567c7526",
+2416 => x"0b0b0b0b",
+2417 => x"83388156",
+2418 => x"80087a27",
+2419 => x"0b0b0b80",
+2420 => x"ea387580",
+2421 => x"2e0b0b0b",
+2422 => x"80e13880",
+2423 => x"081d5d60",
+2424 => x"802e0b0b",
+2425 => x"0b0baa38",
+2426 => x"80567580",
+2427 => x"08250b0b",
+2428 => x"0b0b9838",
+2429 => x"751b5574",
+2430 => x"33777081",
+2431 => x"05593481",
+2432 => x"16567776",
+2433 => x"240b0b0b",
+2434 => x"0bea387f",
+2435 => x"08840560",
+2436 => x"0c787084",
+2437 => x"055a0855",
+2438 => x"74802e0b",
+2439 => x"0b0b0bb9",
+2440 => x"38797d26",
+2441 => x"0b0b0bfe",
+2442 => x"ea387c55",
+2443 => x"74800c96",
+2444 => x"3d0d04ff",
+2445 => x"5a0b0b0b",
+2446 => x"fec8397d",
+2447 => x"7c0c7e84",
+2448 => x"1d0c7c55",
+2449 => x"0b0b0b0b",
+2450 => x"e339818a",
+2451 => x"620c807c",
+2452 => x"0c800880",
+2453 => x"0c963d0d",
+2454 => x"0460802e",
+2455 => x"0b0b0b0b",
+2456 => x"84387460",
+2457 => x"0c747c0c",
+2458 => x"ff1d800c",
+2459 => x"963d0d04",
+2460 => x"fc3d0d79",
+2461 => x"55785477",
+2462 => x"5376520b",
+2463 => x"0b82f4ec",
+2464 => x"08510b0b",
+2465 => x"0bfde33f",
+2466 => x"863d0d04",
+2467 => x"f83d0d7b",
+2468 => x"7d7f0b0b",
+2469 => x"82fbec54",
+2470 => x"5957550b",
+2471 => x"0b818dfb",
+2472 => x"3f800881",
+2473 => x"260b0b0b",
+2474 => x"0b983874",
+2475 => x"5474802e",
+2476 => x"0b0b0b0b",
+2477 => x"86387575",
+2478 => x"34815473",
+2479 => x"800c8a3d",
+2480 => x"0d040b0b",
+2481 => x"82f18452",
+2482 => x"0b0b82fb",
+2483 => x"ec510b0b",
+2484 => x"818c953f",
+2485 => x"80080b0b",
+2486 => x"0b81d838",
+2487 => x"80085474",
+2488 => x"802e0b0b",
+2489 => x"0b0bd438",
+2490 => x"80ff7625",
+2491 => x"0b0b0b0b",
+2492 => x"c538ff80",
+2493 => x"16538eff",
+2494 => x"73270b0b",
+2495 => x"0b85e338",
+2496 => x"f0801653",
+2497 => x"83efff73",
+2498 => x"270b0b0b",
+2499 => x"82d838fc",
+2500 => x"80801653",
+2501 => x"80fbffff",
+2502 => x"73270b0b",
+2503 => x"0b85e838",
+2504 => x"8fff0a16",
+2505 => x"53f7c00a",
+2506 => x"73270b0b",
+2507 => x"0b86a638",
+2508 => x"ff54c00a",
+2509 => x"76250b0b",
+2510 => x"0bff8038",
+2511 => x"75820a06",
+2512 => x"709e2c70",
+2513 => x"fc075151",
+2514 => x"53727570",
+2515 => x"81055734",
+2516 => x"7581fc0a",
+2517 => x"0670982a",
+2518 => x"ff800751",
+2519 => x"53727570",
+2520 => x"81055734",
+2521 => x"7587f080",
+2522 => x"80067092",
+2523 => x"2aff8007",
+2524 => x"51537275",
+2525 => x"70810557",
+2526 => x"34758fe0",
+2527 => x"8006708c",
+2528 => x"2aff8007",
+2529 => x"51537275",
+2530 => x"70810557",
+2531 => x"34759fc0",
+2532 => x"0670862a",
+2533 => x"ff800751",
+2534 => x"53727570",
+2535 => x"81055734",
+2536 => x"75ffbf06",
+2537 => x"ff800753",
+2538 => x"72753486",
+2539 => x"0b800c8a",
+2540 => x"3d0d040b",
+2541 => x"0b82f18c",
+2542 => x"520b0b82",
+2543 => x"fbec510b",
+2544 => x"0b818aa4",
+2545 => x"3f80080b",
+2546 => x"0b0b81f7",
+2547 => x"387581ff",
+2548 => x"0676882c",
+2549 => x"7081ff06",
+2550 => x"80085759",
+2551 => x"54587480",
+2552 => x"2e0b0b0b",
+2553 => x"fdd53876",
+2554 => x"802e0b0b",
+2555 => x"0bfdbc38",
+2556 => x"800880ff",
+2557 => x"187081ff",
+2558 => x"06515456",
+2559 => x"729e260b",
+2560 => x"0b0b0b83",
+2561 => x"38815680",
+2562 => x"08a01870",
+2563 => x"81ff0651",
+2564 => x"5454728f",
+2565 => x"260b0b0b",
+2566 => x"0b833881",
+2567 => x"54757407",
+2568 => x"5372802e",
+2569 => x"0b0b0b0b",
+2570 => x"b5388008",
+2571 => x"c0195456",
+2572 => x"72be260b",
+2573 => x"0b0b0b83",
+2574 => x"38815680",
+2575 => x"08ff8019",
+2576 => x"7081ff06",
+2577 => x"51545472",
+2578 => x"80fc260b",
+2579 => x"0b0b0b83",
+2580 => x"38815475",
+2581 => x"74075372",
+2582 => x"0b0b0b80",
+2583 => x"d338ff0b",
+2584 => x"800c8a3d",
+2585 => x"0d04fcd0",
+2586 => x"801653ff",
+2587 => x"548fff73",
+2588 => x"270b0b0b",
+2589 => x"fcc53875",
+2590 => x"83e08006",
+2591 => x"708c2ae0",
+2592 => x"07515372",
+2593 => x"75708105",
+2594 => x"5734759f",
+2595 => x"c0067086",
+2596 => x"2aff8007",
+2597 => x"51537275",
+2598 => x"70810557",
+2599 => x"3475ffbf",
+2600 => x"06ff8007",
+2601 => x"53727534",
+2602 => x"830b800c",
+2603 => x"8a3d0d04",
+2604 => x"76757081",
+2605 => x"05573477",
+2606 => x"75348254",
+2607 => x"73800c8a",
+2608 => x"3d0d040b",
+2609 => x"0b82f194",
+2610 => x"520b0b82",
+2611 => x"fbec510b",
+2612 => x"0b818894",
+2613 => x"3f80080b",
+2614 => x"0b0b80f8",
+2615 => x"387581ff",
+2616 => x"0676882c",
+2617 => x"7081ff06",
+2618 => x"80085759",
+2619 => x"54587480",
+2620 => x"2e0b0b0b",
+2621 => x"fbc53876",
+2622 => x"802e0b0b",
+2623 => x"0bfbac38",
+2624 => x"80085381",
+2625 => x"a077270b",
+2626 => x"0b0b0b83",
+2627 => x"38815376",
+2628 => x"81ff2e0b",
+2629 => x"0b0bfec6",
+2630 => x"38817074",
+2631 => x"06545472",
+2632 => x"802e0b0b",
+2633 => x"0bfeb738",
+2634 => x"80085381",
+2635 => x"a078270b",
+2636 => x"0b0b0b83",
+2637 => x"38735377",
+2638 => x"81ff2e0b",
+2639 => x"0b0bfe9e",
+2640 => x"38727406",
+2641 => x"5372802e",
+2642 => x"0b0b0bfe",
+2643 => x"91380b0b",
+2644 => x"0bfedd39",
+2645 => x"0b0b82f1",
+2646 => x"9c520b0b",
+2647 => x"82fbec51",
+2648 => x"0b0b8187",
+2649 => x"833f8008",
+2650 => x"0b0b0bfa",
+2651 => x"be388008",
+2652 => x"7681ff06",
+2653 => x"77882c70",
+2654 => x"81ff0659",
+2655 => x"55595981",
+2656 => x"5474802e",
+2657 => x"0b0b0bfa",
+2658 => x"b2387580",
+2659 => x"2e0b0b0b",
+2660 => x"82a538df",
+2661 => x"16537280",
+2662 => x"dd260b0b",
+2663 => x"0bfdbf38",
+2664 => x"df185372",
+2665 => x"80dd260b",
+2666 => x"0b0bfdb2",
+2667 => x"3876080b",
+2668 => x"0b0b0b9c",
+2669 => x"3873770c",
+2670 => x"9b757081",
+2671 => x"055734a4",
+2672 => x"75708105",
+2673 => x"573480c2",
+2674 => x"75708105",
+2675 => x"57348359",
+2676 => x"75757081",
+2677 => x"05573477",
+2678 => x"75348219",
+2679 => x"800c8a3d",
+2680 => x"0d04758f",
+2681 => x"c0067086",
+2682 => x"2ac00751",
+2683 => x"53727570",
+2684 => x"81055734",
+2685 => x"75ffbf06",
+2686 => x"ff800753",
+2687 => x"72753482",
+2688 => x"540b0b0b",
+2689 => x"fdb63975",
+2690 => x"80f08080",
+2691 => x"0670922a",
+2692 => x"f0075153",
+2693 => x"72757081",
+2694 => x"05573475",
+2695 => x"8fe08006",
+2696 => x"708c2aff",
+2697 => x"80075153",
+2698 => x"72757081",
+2699 => x"05573475",
+2700 => x"9fc00670",
+2701 => x"862aff80",
+2702 => x"07515372",
+2703 => x"75708105",
+2704 => x"573475ff",
+2705 => x"bf06ff80",
+2706 => x"07537275",
+2707 => x"34840b80",
+2708 => x"0c8a3d0d",
+2709 => x"047581c0",
+2710 => x"0a067098",
+2711 => x"2af80751",
+2712 => x"53727570",
+2713 => x"81055734",
+2714 => x"7587f080",
+2715 => x"80067092",
+2716 => x"2aff8007",
+2717 => x"51537275",
+2718 => x"70810557",
+2719 => x"34758fe0",
+2720 => x"8006708c",
+2721 => x"2aff8007",
+2722 => x"51537275",
+2723 => x"70810557",
+2724 => x"34759fc0",
+2725 => x"0670862a",
+2726 => x"ff800751",
+2727 => x"53727570",
+2728 => x"81055734",
+2729 => x"75ffbf06",
+2730 => x"ff800753",
+2731 => x"72753485",
+2732 => x"0b800c8a",
+2733 => x"3d0d0476",
+2734 => x"08802e0b",
+2735 => x"0b0b0b9d",
+2736 => x"38800877",
+2737 => x"0c9b7570",
+2738 => x"81055734",
+2739 => x"a8757081",
+2740 => x"05573480",
+2741 => x"c2757081",
+2742 => x"05573483",
+2743 => x"59777534",
+2744 => x"8119800c",
+2745 => x"8a3d0d04",
+2746 => x"fa3d0d78",
+2747 => x"0b0b82f4",
+2748 => x"ec085455",
+2749 => x"b8130880",
+2750 => x"2e0b0b0b",
+2751 => x"81dc388c",
+2752 => x"15227083",
+2753 => x"ffff0670",
+2754 => x"832a8132",
+2755 => x"70810651",
+2756 => x"55555672",
+2757 => x"802e0b0b",
+2758 => x"0b80f038",
+2759 => x"73842a81",
+2760 => x"32810657",
+2761 => x"ff53760b",
+2762 => x"0b0b8193",
+2763 => x"3873822a",
+2764 => x"70810651",
+2765 => x"5372802e",
+2766 => x"0b0b0b80",
+2767 => x"c638b015",
+2768 => x"08547380",
+2769 => x"2e0b0b0b",
+2770 => x"0ba53880",
+2771 => x"c0155373",
+2772 => x"732e0b0b",
+2773 => x"0b0b9438",
+2774 => x"73520b0b",
+2775 => x"82f4ec08",
+2776 => x"510b0b0b",
+2777 => x"b5d23f8c",
+2778 => x"15225676",
+2779 => x"b0160c75",
+2780 => x"db065372",
+2781 => x"8c162380",
+2782 => x"0b84160c",
+2783 => x"90150875",
+2784 => x"0c725675",
+2785 => x"88075372",
+2786 => x"8c162390",
+2787 => x"1508802e",
+2788 => x"0b0b0b80",
+2789 => x"d3388c15",
+2790 => x"22708106",
+2791 => x"5553730b",
+2792 => x"0b0b0ba2",
+2793 => x"38720a10",
+2794 => x"0a708106",
+2795 => x"5153720b",
+2796 => x"0b0b0b85",
+2797 => x"38941508",
+2798 => x"54738816",
+2799 => x"0c805372",
+2800 => x"800c883d",
+2801 => x"0d04800b",
+2802 => x"88160c94",
+2803 => x"15083098",
+2804 => x"160c8053",
+2805 => x"0b0b0b0b",
+2806 => x"e6397251",
+2807 => x"0b0b0baf",
+2808 => x"fe3f0b0b",
+2809 => x"0bfe9839",
+2810 => x"74510b0b",
+2811 => x"80c4ef3f",
+2812 => x"8c152270",
+2813 => x"81065553",
+2814 => x"73802e0b",
+2815 => x"0b0bffa5",
+2816 => x"380b0b0b",
+2817 => x"0bc039ef",
+2818 => x"3d0d6365",
+2819 => x"9011085e",
+2820 => x"40408053",
+2821 => x"7b609005",
+2822 => x"08240b0b",
+2823 => x"0b81d038",
+2824 => x"941f70ff",
+2825 => x"1e70822b",
+2826 => x"73116494",
+2827 => x"05705c43",
+2828 => x"5f610570",
+2829 => x"087f0881",
+2830 => x"0557555c",
+2831 => x"5e42570b",
+2832 => x"0b81ebf8",
+2833 => x"3f80085d",
+2834 => x"80080b0b",
+2835 => x"0b81a738",
+2836 => x"7e527f51",
+2837 => x"0b0b80e9",
+2838 => x"803f800b",
+2839 => x"8008240b",
+2840 => x"0b0b8189",
+2841 => x"38811d5d",
+2842 => x"80707f63",
+2843 => x"5a585b58",
+2844 => x"76708405",
+2845 => x"58087083",
+2846 => x"ffff067b",
+2847 => x"0571902a",
+2848 => x"71902a05",
+2849 => x"70902a5d",
+2850 => x"5283ffff",
+2851 => x"06821822",
+2852 => x"7072311b",
+2853 => x"585b5483",
+2854 => x"ffff0676",
+2855 => x"22707231",
+2856 => x"77902c05",
+2857 => x"70902c5b",
+2858 => x"52435372",
+2859 => x"76237482",
+2860 => x"17238416",
+2861 => x"567a7727",
+2862 => x"0b0b0bff",
+2863 => x"b3387b10",
+2864 => x"101e5978",
+2865 => x"080b0b0b",
+2866 => x"0ba338fc",
+2867 => x"19597d79",
+2868 => x"270b0b0b",
+2869 => x"0b923878",
+2870 => x"080b0b0b",
+2871 => x"0b8a38ff",
+2872 => x"1c5c0b0b",
+2873 => x"0b0be439",
+2874 => x"7b609005",
+2875 => x"0c7c5372",
+2876 => x"800c933d",
+2877 => x"0d048070",
+2878 => x"5b587670",
+2879 => x"84055808",
+2880 => x"7083ffff",
+2881 => x"06707f29",
+2882 => x"1c72902a",
+2883 => x"60297190",
+2884 => x"2a057090",
+2885 => x"2a5e5283",
+2886 => x"ffff0682",
+2887 => x"19227072",
+2888 => x"311c5945",
+2889 => x"5283ffff",
+2890 => x"06772270",
+2891 => x"72317890",
+2892 => x"2c057090",
+2893 => x"2c5c5256",
+2894 => x"51537276",
+2895 => x"23748217",
+2896 => x"23841656",
+2897 => x"7a77270b",
+2898 => x"0b0bffae",
+2899 => x"3878080b",
+2900 => x"0b0bfdfc",
+2901 => x"38fc1959",
+2902 => x"7d79270b",
+2903 => x"0b0b0b92",
+2904 => x"3878080b",
+2905 => x"0b0b0b8a",
+2906 => x"38ff1c5c",
+2907 => x"0b0b0b0b",
+2908 => x"e4397b60",
+2909 => x"90050c0b",
+2910 => x"0b0bfdd4",
+2911 => x"398c08c8",
+2912 => x"3d0dbc3d",
+2913 => x"0880c03d",
+2914 => x"0880c23d",
+2915 => x"0880c53d",
+2916 => x"0880c73d",
+2917 => x"088c0c5d",
+2918 => x"4b434080",
+2919 => x"0bbe3d08",
+2920 => x"80c03d08",
+2921 => x"5bba3d0c",
+2922 => x"79bb3d0c",
+2923 => x"6080c005",
+2924 => x"08574875",
+2925 => x"682e0981",
+2926 => x"060b0b0b",
+2927 => x"80ea38b8",
+2928 => x"3d085780",
+2929 => x"77240b0b",
+2930 => x"0b818c38",
+2931 => x"677a0c76",
+2932 => x"9ffe0a06",
+2933 => x"56759ffe",
+2934 => x"0a2e0b0b",
+2935 => x"0b819838",
+2936 => x"b83d08ba",
+2937 => x"3d085a58",
+2938 => x"80568076",
+2939 => x"54547751",
+2940 => x"78520b0b",
+2941 => x"81d6f23f",
+2942 => x"80080b0b",
+2943 => x"0b81c638",
+2944 => x"80c13d08",
+2945 => x"5881780c",
+2946 => x"0b0b82f0",
+2947 => x"f05f8c08",
+2948 => x"802e0b0b",
+2949 => x"0b0b8638",
+2950 => x"811f8c08",
+2951 => x"0c7e5675",
+2952 => x"800cba3d",
+2953 => x"0d8c0c04",
+2954 => x"7f80c405",
+2955 => x"0884170c",
+2956 => x"816080c4",
+2957 => x"05082b88",
+2958 => x"170c7552",
+2959 => x"7f510b0b",
+2960 => x"80d8ad3f",
+2961 => x"676080c0",
+2962 => x"050cb83d",
+2963 => x"08577680",
+2964 => x"250b0b0b",
+2965 => x"fef63881",
+2966 => x"7a0c76fe",
+2967 => x"0a0670ba",
+2968 => x"3d0c709f",
+2969 => x"fe0a0657",
+2970 => x"57759ffe",
+2971 => x"0a2e0981",
+2972 => x"060b0b0b",
+2973 => x"feea3880",
+2974 => x"c13d0856",
+2975 => x"80ce8f76",
+2976 => x"0cb93d08",
+2977 => x"0b0b0b84",
+2978 => x"c93876bf",
+2979 => x"ffff060b",
+2980 => x"0b82f1a4",
+2981 => x"4056750b",
+2982 => x"0b0b84b6",
+2983 => x"388c0880",
+2984 => x"2e0b0b0b",
+2985 => x"fef73883",
+2986 => x"1f337f88",
+2987 => x"05585675",
+2988 => x"0b0b0b0b",
+2989 => x"8438831f",
+2990 => x"57768c08",
+2991 => x"0c7e560b",
+2992 => x"0b0bfedb",
+2993 => x"39ba3dff",
+2994 => x"b41156ff",
+2995 => x"b0055477",
+2996 => x"5278537f",
+2997 => x"510b0b80",
+2998 => x"eaa43f80",
+2999 => x"08b93d08",
+3000 => x"70942a8f",
+3001 => x"ff065e59",
+3002 => x"417b0b0b",
+3003 => x"0b83ef38",
+3004 => x"a73d08a7",
+3005 => x"3d080588",
+3006 => x"b2115d56",
+3007 => x"a07c250b",
+3008 => x"0b0b8ff4",
+3009 => x"3880c07c",
+3010 => x"31889217",
+3011 => x"79722bbc",
+3012 => x"3d08722a",
+3013 => x"07b53d71",
+3014 => x"5670555d",
+3015 => x"5157570b",
+3016 => x"0b81dfa9",
+3017 => x"3fb23d08",
+3018 => x"b43d08b2",
+3019 => x"3d5d5a58",
+3020 => x"8076240b",
+3021 => x"0b0b93f5",
+3022 => x"3877b73d",
+3023 => x"0c78b83d",
+3024 => x"0cb63d08",
+3025 => x"90ff0a05",
+3026 => x"b73d0cf7",
+3027 => x"cd1c5c81",
+3028 => x"4ebffc0a",
+3029 => x"56807655",
+3030 => x"55b63d08",
+3031 => x"b83d0858",
+3032 => x"5276537a",
+3033 => x"510b0b81",
+3034 => x"a2803f83",
+3035 => x"feca8fa7",
+3036 => x"56869bbd",
+3037 => x"86e17655",
+3038 => x"55b03d08",
+3039 => x"b23d0858",
+3040 => x"52765379",
+3041 => x"510b0b81",
+3042 => x"a3933f83",
+3043 => x"fe9a94a8",
+3044 => x"56f8db83",
+3045 => x"91b37655",
+3046 => x"55b23d08",
+3047 => x"b43d0858",
+3048 => x"527653ba",
+3049 => x"3dd00551",
+3050 => x"0b0b81a0",
+3051 => x"963fae3d",
+3052 => x"08b03d08",
+3053 => x"7d54ae3d",
+3054 => x"535a580b",
+3055 => x"0b81de8d",
+3056 => x"3faa3d4c",
+3057 => x"83fecd88",
+3058 => x"93568584",
+3059 => x"fdf3fb76",
+3060 => x"5555ac3d",
+3061 => x"08ae3d08",
+3062 => x"58527653",
+3063 => x"6b510b0b",
+3064 => x"81a2ba3f",
+3065 => x"a83dab3d",
+3066 => x"08ad3d08",
+3067 => x"59557756",
+3068 => x"78537954",
+3069 => x"7052450b",
+3070 => x"0b819fc7",
+3071 => x"3fa83d08",
+3072 => x"aa3d0871",
+3073 => x"5370545f",
+3074 => x"5d0b0b81",
+3075 => x"dfdf3f80",
+3076 => x"08438056",
+3077 => x"80765454",
+3078 => x"7c517d52",
+3079 => x"0b0b81d9",
+3080 => x"843f800b",
+3081 => x"8008240b",
+3082 => x"0b0b8eae",
+3083 => x"38810ba2",
+3084 => x"3d0c6296",
+3085 => x"260b0b0b",
+3086 => x"0bb23862",
+3087 => x"1010100b",
+3088 => x"0b82f2d8",
+3089 => x"05841108",
+3090 => x"71085555",
+3091 => x"b93d08bb",
+3092 => x"3d085952",
+3093 => x"5676520b",
+3094 => x"0b81d8c9",
+3095 => x"3f800b80",
+3096 => x"08246371",
+3097 => x"31445680",
+3098 => x"0ba23d0c",
+3099 => x"a73d087c",
+3100 => x"31ff055a",
+3101 => x"807a454b",
+3102 => x"6a7a240b",
+3103 => x"0b0b8da9",
+3104 => x"38806324",
+3105 => x"0b0b0ba0",
+3106 => x"8b38800b",
+3107 => x"a63d0c62",
+3108 => x"4f636305",
+3109 => x"44896227",
+3110 => x"0b0b0b0b",
+3111 => x"83388042",
+3112 => x"81588562",
+3113 => x"250b0b0b",
+3114 => x"0b873861",
+3115 => x"fc054280",
+3116 => x"58810ba1",
+3117 => x"3d0cff70",
+3118 => x"a53d0c46",
+3119 => x"6185260b",
+3120 => x"0b0b82bd",
+3121 => x"38611010",
+3122 => x"0b0b82f1",
+3123 => x"b0055675",
+3124 => x"08040b0b",
+3125 => x"82f0f85f",
+3126 => x"0b0b0bfb",
+3127 => x"c039b83d",
+3128 => x"08ba3d08",
+3129 => x"58b73d0c",
+3130 => x"76b83d0c",
+3131 => x"b63d08fc",
+3132 => x"0a069ffc",
+3133 => x"0a07b73d",
+3134 => x"0cf8811c",
+3135 => x"5c804eb2",
+3136 => x"3db13d5c",
+3137 => x"5abffc0a",
+3138 => x"56807655",
+3139 => x"55b63d08",
+3140 => x"b83d0858",
+3141 => x"5276537a",
+3142 => x"510b0b81",
+3143 => x"9ecc3f83",
+3144 => x"feca8fa7",
+3145 => x"56869bbd",
+3146 => x"86e17655",
+3147 => x"55b03d08",
+3148 => x"b23d0858",
+3149 => x"52765379",
+3150 => x"510b0b81",
+3151 => x"9fdf3f83",
+3152 => x"fe9a94a8",
+3153 => x"56f8db83",
+3154 => x"91b37655",
+3155 => x"55b23d08",
+3156 => x"b43d0858",
+3157 => x"527653ba",
+3158 => x"3dd00551",
+3159 => x"0b0b819c",
+3160 => x"e23fae3d",
+3161 => x"08b03d08",
+3162 => x"7d54ae3d",
+3163 => x"535a580b",
+3164 => x"0b81dad9",
+3165 => x"3faa3d4c",
+3166 => x"83fecd88",
+3167 => x"93568584",
+3168 => x"fdf3fb76",
+3169 => x"5555ac3d",
+3170 => x"08ae3d08",
+3171 => x"58527653",
+3172 => x"6b510b0b",
+3173 => x"819f863f",
+3174 => x"a83dab3d",
+3175 => x"08ad3d08",
+3176 => x"59557756",
+3177 => x"78537954",
+3178 => x"7052450b",
+3179 => x"0b819c93",
+3180 => x"3fa83d08",
+3181 => x"aa3d0871",
+3182 => x"5370545f",
+3183 => x"5d0b0b81",
+3184 => x"dcab3f80",
+3185 => x"08438056",
+3186 => x"80765454",
+3187 => x"7c517d52",
+3188 => x"0b0b81d5",
+3189 => x"d03f8008",
+3190 => x"80250b0b",
+3191 => x"0bfcce38",
+3192 => x"0b0b0b8a",
+3193 => x"f539800b",
+3194 => x"a13d0c68",
+3195 => x"63058111",
+3196 => x"70485da4",
+3197 => x"3d0c7b80",
+3198 => x"240b0b0b",
+3199 => x"0b833881",
+3200 => x"5c845a80",
+3201 => x"6080c405",
+3202 => x"0c987c26",
+3203 => x"0b0b0b0b",
+3204 => x"9b388057",
+3205 => x"81177a10",
+3206 => x"9411585b",
+3207 => x"577b7627",
+3208 => x"0b0b0b0b",
+3209 => x"ef387660",
+3210 => x"80c4050c",
+3211 => x"7f80c405",
+3212 => x"08527f51",
+3213 => x"0b0b80cf",
+3214 => x"903f8008",
+3215 => x"6080c005",
+3216 => x"0c800880",
+3217 => x"088e6827",
+3218 => x"58404d77",
+3219 => x"802e0b0b",
+3220 => x"0b86fd38",
+3221 => x"75802e0b",
+3222 => x"0b0b86f4",
+3223 => x"38b83d08",
+3224 => x"ba3d0871",
+3225 => x"b93d0c70",
+3226 => x"ba3d0c64",
+3227 => x"a53d0c67",
+3228 => x"a73d0c5a",
+3229 => x"58825c80",
+3230 => x"63250b0b",
+3231 => x"0b8cae38",
+3232 => x"62832b80",
+3233 => x"f8060b0b",
+3234 => x"82f2d811",
+3235 => x"080b0b82",
+3236 => x"f2dc1208",
+3237 => x"65842c70",
+3238 => x"842a7081",
+3239 => x"0651545d",
+3240 => x"405e5675",
+3241 => x"0b0b0b8a",
+3242 => x"8a387980",
+3243 => x"2e0b0b0b",
+3244 => x"0ba8380b",
+3245 => x"0b82f2b0",
+3246 => x"58798106",
+3247 => x"56750b0b",
+3248 => x"0b88f138",
+3249 => x"79812c88",
+3250 => x"19595a79",
+3251 => x"0b0b0b0b",
+3252 => x"e838b83d",
+3253 => x"08ba3d08",
+3254 => x"5a587c54",
+3255 => x"7d557752",
+3256 => x"78536451",
+3257 => x"0b0b81bb",
+3258 => x"b43fa83d",
+3259 => x"08aa3d08",
+3260 => x"71bb3d0c",
+3261 => x"70bc3d0c",
+3262 => x"5a58a13d",
+3263 => x"08802e0b",
+3264 => x"0b0b80eb",
+3265 => x"38805a9f",
+3266 => x"fc0a5680",
+3267 => x"76545477",
+3268 => x"5178520b",
+3269 => x"0b81d38d",
+3270 => x"3f798008",
+3271 => x"240b0b0b",
+3272 => x"8def3880",
+3273 => x"66250b0b",
+3274 => x"0b80c438",
+3275 => x"79802e0b",
+3276 => x"0b0b0bbb",
+3277 => x"38800ba4",
+3278 => x"3d08250b",
+3279 => x"0b0b84f8",
+3280 => x"38a33d08",
+3281 => x"63ff0544",
+3282 => x"4680c882",
+3283 => x"0a568076",
+3284 => x"55557752",
+3285 => x"78536451",
+3286 => x"0b0b819b",
+3287 => x"c03fa83d",
+3288 => x"08aa3d08",
+3289 => x"5ab93d0c",
+3290 => x"78ba3d0c",
+3291 => x"811c5c7b",
+3292 => x"5264510b",
+3293 => x"0b81d6d5",
+3294 => x"3fb83d08",
+3295 => x"ba3d0858",
+3296 => x"547655a8",
+3297 => x"3d08aa3d",
+3298 => x"08585276",
+3299 => x"536b510b",
+3300 => x"0b819b89",
+3301 => x"3f80f082",
+3302 => x"0a568076",
+3303 => x"5555aa3d",
+3304 => x"08ac3d08",
+3305 => x"58527653",
+3306 => x"ac3d510b",
+3307 => x"0b819893",
+3308 => x"3fac3d08",
+3309 => x"ae3d0858",
+3310 => x"b53d0c76",
+3311 => x"b63d0cb4",
+3312 => x"3d0886bf",
+3313 => x"0a05b53d",
+3314 => x"0c65802e",
+3315 => x"0b0b0b9b",
+3316 => x"c9386f80",
+3317 => x"2e0b0b0b",
+3318 => x"99e23865",
+3319 => x"1010100b",
+3320 => x"0b82f2d0",
+3321 => x"05841108",
+3322 => x"71085656",
+3323 => x"568ffc0a",
+3324 => x"56807653",
+3325 => x"5364510b",
+3326 => x"0b81b9a1",
+3327 => x"3fb43d08",
+3328 => x"b63d0858",
+3329 => x"547655a8",
+3330 => x"3d08aa3d",
+3331 => x"08585276",
+3332 => x"536b510b",
+3333 => x"0b8198d2",
+3334 => x"3faa3d08",
+3335 => x"ac3d0858",
+3336 => x"b53d0c76",
+3337 => x"b63d0c80",
+3338 => x"0bb93d08",
+3339 => x"bb3d085b",
+3340 => x"595c80c8",
+3341 => x"820a5d80",
+3342 => x"5e775178",
+3343 => x"520b0b81",
+3344 => x"d7ab3f80",
+3345 => x"08800853",
+3346 => x"65525a0b",
+3347 => x"0b81d4fd",
+3348 => x"3fa83d08",
+3349 => x"aa3d0858",
+3350 => x"547655b8",
+3351 => x"3d08ba3d",
+3352 => x"08585276",
+3353 => x"536b510b",
+3354 => x"0b8197fe",
+3355 => x"3faa3d08",
+3356 => x"ac3d085a",
+3357 => x"b93d0c78",
+3358 => x"ba3d0cb0",
+3359 => x"1a56757f",
+3360 => x"70810541",
+3361 => x"34b83d08",
+3362 => x"ba3d08b6",
+3363 => x"3d08b83d",
+3364 => x"085a5578",
+3365 => x"56715370",
+3366 => x"545a580b",
+3367 => x"0b81d085",
+3368 => x"3f800b80",
+3369 => x"08240b0b",
+3370 => x"0b87d438",
+3371 => x"77547855",
+3372 => x"9ffc0a56",
+3373 => x"80765353",
+3374 => x"64510b0b",
+3375 => x"8197ab3f",
+3376 => x"b43d08b6",
+3377 => x"3d087155",
+3378 => x"7056aa3d",
+3379 => x"08ac3d08",
+3380 => x"5a537854",
+3381 => x"5a580b0b",
+3382 => x"81cfca3f",
+3383 => x"800b8008",
+3384 => x"240b0b0b",
+3385 => x"86e63881",
+3386 => x"1c5c7b66",
+3387 => x"250b0b0b",
+3388 => x"81c6387c",
+3389 => x"547d5577",
+3390 => x"5278536b",
+3391 => x"510b0b81",
+3392 => x"989b3faa",
+3393 => x"3d08ac3d",
+3394 => x"0858b53d",
+3395 => x"0c76b63d",
+3396 => x"0c7c547d",
+3397 => x"55b83d08",
+3398 => x"ba3d0858",
+3399 => x"52765364",
+3400 => x"510b0b81",
+3401 => x"97f73fa8",
+3402 => x"3d08aa3d",
+3403 => x"0871bb3d",
+3404 => x"0c70bc3d",
+3405 => x"0c5a580b",
+3406 => x"0b0bfdfd",
+3407 => x"398ffc0a",
+3408 => x"58807855",
+3409 => x"7056b53d",
+3410 => x"08b73d08",
+3411 => x"59537754",
+3412 => x"6552590b",
+3413 => x"0b8194eb",
+3414 => x"3fa83d08",
+3415 => x"aa3d0858",
+3416 => x"537654b8",
+3417 => x"3d08ba3d",
+3418 => x"08585176",
+3419 => x"520b0b81",
+3420 => x"cc9f3f80",
+3421 => x"0880240b",
+3422 => x"0b0b85d0",
+3423 => x"38b43d08",
+3424 => x"b63d0858",
+3425 => x"54765577",
+3426 => x"5278536b",
+3427 => x"510b0b81",
+3428 => x"95d83faa",
+3429 => x"3d08ac3d",
+3430 => x"08585376",
+3431 => x"54b83d08",
+3432 => x"ba3d0858",
+3433 => x"5176520b",
+3434 => x"0b81cdf9",
+3435 => x"3f800b80",
+3436 => x"08240b0b",
+3437 => x"0b97cb38",
+3438 => x"6cb73d08",
+3439 => x"b93d085b",
+3440 => x"ba3d0c79",
+3441 => x"bb3d0ca3",
+3442 => x"3d08a63d",
+3443 => x"0848445f",
+3444 => x"800ba73d",
+3445 => x"08575877",
+3446 => x"76240b0b",
+3447 => x"0b0b8338",
+3448 => x"81588078",
+3449 => x"0657628e",
+3450 => x"240b0b0b",
+3451 => x"89ad3881",
+3452 => x"70790658",
+3453 => x"5976802e",
+3454 => x"0b0b0b89",
+3455 => x"9e386210",
+3456 => x"10100b0b",
+3457 => x"82f2d805",
+3458 => x"70088412",
+3459 => x"08806c24",
+3460 => x"53405e56",
+3461 => x"8066250b",
+3462 => x"0b0b86c9",
+3463 => x"38810bb9",
+3464 => x"3d08bb3d",
+3465 => x"085b595c",
+3466 => x"7c547d55",
+3467 => x"77527853",
+3468 => x"64510b0b",
+3469 => x"81b4e63f",
+3470 => x"a83d08aa",
+3471 => x"3d085851",
+3472 => x"76520b0b",
+3473 => x"81d3a63f",
+3474 => x"80088008",
+3475 => x"5365525a",
+3476 => x"0b0b81d0",
+3477 => x"f83f7c54",
+3478 => x"7d55a83d",
+3479 => x"08aa3d08",
+3480 => x"58527653",
+3481 => x"6b510b0b",
+3482 => x"8195b23f",
+3483 => x"aa3d08ac",
+3484 => x"3d085854",
+3485 => x"7655b83d",
+3486 => x"08ba3d08",
+3487 => x"58527653",
+3488 => x"ac3d510b",
+3489 => x"0b8193e2",
+3490 => x"3fac3d08",
+3491 => x"ae3d085a",
+3492 => x"b93d0c78",
+3493 => x"ba3d0cb0",
+3494 => x"1a56757f",
+3495 => x"70810541",
+3496 => x"347b662e",
+3497 => x"0b0b0b82",
+3498 => x"c23880c8",
+3499 => x"820a5680",
+3500 => x"765555b8",
+3501 => x"3d08ba3d",
+3502 => x"08585276",
+3503 => x"5364510b",
+3504 => x"0b8194d9",
+3505 => x"3fa83d08",
+3506 => x"aa3d0871",
+3507 => x"bb3d0c70",
+3508 => x"bc3d0c5a",
+3509 => x"58805680",
+3510 => x"76545477",
+3511 => x"5178520b",
+3512 => x"0b81c585",
+3513 => x"3f800880",
+3514 => x"2e0b0b0b",
+3515 => x"83913881",
+3516 => x"1c5c0b0b",
+3517 => x"0bfeb139",
+3518 => x"a07c31ba",
+3519 => x"3d08712b",
+3520 => x"b43d7155",
+3521 => x"70545c51",
+3522 => x"560b0b81",
+3523 => x"cfbf3fb2",
+3524 => x"3d08b43d",
+3525 => x"08b23d5d",
+3526 => x"5a587580",
+3527 => x"250b0b0b",
+3528 => x"f097380b",
+3529 => x"0b0b8485",
+3530 => x"3979304b",
+3531 => x"80440b0b",
+3532 => x"0bf2ce39",
+3533 => x"811c7808",
+3534 => x"841a0859",
+3535 => x"5577567d",
+3536 => x"537e5465",
+3537 => x"525c0b0b",
+3538 => x"8193d23f",
+3539 => x"a83d08aa",
+3540 => x"3d085f5d",
+3541 => x"0b0b0bf6",
+3542 => x"eb396252",
+3543 => x"64510b0b",
+3544 => x"81ceea3f",
+3545 => x"7c537d54",
+3546 => x"a83d08aa",
+3547 => x"3d085851",
+3548 => x"76520b0b",
+3549 => x"81c6863f",
+3550 => x"80083070",
+3551 => x"8008079f",
+3552 => x"2a647131",
+3553 => x"4551560b",
+3554 => x"0b0bf1a1",
+3555 => x"39800ba1",
+3556 => x"3d0c8069",
+3557 => x"250b0b0b",
+3558 => x"84e73868",
+3559 => x"69a53d0c",
+3560 => x"69475c0b",
+3561 => x"0b0bf4d9",
+3562 => x"39925c80",
+3563 => x"490b0b0b",
+3564 => x"f4cf3979",
+3565 => x"8f060b0b",
+3566 => x"82f2d008",
+3567 => x"0b0b82f2",
+3568 => x"d4085955",
+3569 => x"77567853",
+3570 => x"79546552",
+3571 => x"5a0b0b81",
+3572 => x"b1cb3fa8",
+3573 => x"3d08aa3d",
+3574 => x"0871bb3d",
+3575 => x"0c70bc3d",
+3576 => x"0c5a5883",
+3577 => x"5c0b0b0b",
+3578 => x"f5c039b8",
+3579 => x"3d08ba3d",
+3580 => x"08715670",
+3581 => x"57585276",
+3582 => x"5364510b",
+3583 => x"0b818fc3",
+3584 => x"3fa83d08",
+3585 => x"aa3d0871",
+3586 => x"bb3d0c70",
+3587 => x"bc3d0c7e",
+3588 => x"557f5671",
+3589 => x"5370545a",
+3590 => x"580b0b81",
+3591 => x"c6f33f80",
+3592 => x"0880240b",
+3593 => x"0b0b0ba4",
+3594 => x"387c537d",
+3595 => x"54775178",
+3596 => x"520b0b81",
+3597 => x"c2b33f80",
+3598 => x"080b0b0b",
+3599 => x"80c13879",
+3600 => x"81065675",
+3601 => x"802e0b0b",
+3602 => x"0b0bb438",
+3603 => x"ff1f7033",
+3604 => x"575f75b9",
+3605 => x"2e098106",
+3606 => x"0b0b0b0b",
+3607 => x"94387e6d",
+3608 => x"2e098106",
+3609 => x"0b0b0b0b",
+3610 => x"e3386281",
+3611 => x"0543b06d",
+3612 => x"347e7f81",
+3613 => x"05713381",
+3614 => x"05584057",
+3615 => x"75773460",
+3616 => x"527f510b",
+3617 => x"0b80c3e8",
+3618 => x"3f807f34",
+3619 => x"80c13d08",
+3620 => x"63810571",
+3621 => x"0c568c08",
+3622 => x"802e0b0b",
+3623 => x"0b0b8538",
+3624 => x"7e8c080c",
+3625 => x"6c800cba",
+3626 => x"3d0d8c0c",
+3627 => x"0462305b",
+3628 => x"7a802e0b",
+3629 => x"0b0bf4c2",
+3630 => x"387a832b",
+3631 => x"80f8060b",
+3632 => x"0b82f2dc",
+3633 => x"11080b0b",
+3634 => x"82f2d812",
+3635 => x"08565678",
+3636 => x"53795465",
+3637 => x"52560b0b",
+3638 => x"8190c23f",
+3639 => x"a83d08aa",
+3640 => x"3d0871bb",
+3641 => x"3d0c70bc",
+3642 => x"3d0c7c84",
+3643 => x"2c5c5a58",
+3644 => x"79802e0b",
+3645 => x"0b0bf482",
+3646 => x"380b0b82",
+3647 => x"f2b07a81",
+3648 => x"06575b75",
+3649 => x"0b0b0b82",
+3650 => x"90387981",
+3651 => x"2c881c5c",
+3652 => x"5a79802e",
+3653 => x"0b0b0bf3",
+3654 => x"e1387981",
+3655 => x"06567580",
+3656 => x"2e0b0b0b",
+3657 => x"0be4380b",
+3658 => x"0b0b81ed",
+3659 => x"399f820a",
+3660 => x"56807655",
+3661 => x"55775278",
+3662 => x"537a510b",
+3663 => x"0b818d83",
+3664 => x"3fb03d08",
+3665 => x"b23d085a",
+3666 => x"b73d0c78",
+3667 => x"b83d0cb6",
+3668 => x"3d0890ff",
+3669 => x"0a05b73d",
+3670 => x"0cf7cd1c",
+3671 => x"5c814e0b",
+3672 => x"0b0bebed",
+3673 => x"39757906",
+3674 => x"5675802e",
+3675 => x"0b0b0bf9",
+3676 => x"ac388070",
+3677 => x"484a6966",
+3678 => x"240b0b0b",
+3679 => x"82943880",
+3680 => x"d0820a56",
+3681 => x"80765555",
+3682 => x"7c527d53",
+3683 => x"64510b0b",
+3684 => x"818f8a3f",
+3685 => x"a83d08aa",
+3686 => x"3d085853",
+3687 => x"7654b83d",
+3688 => x"08ba3d08",
+3689 => x"58517652",
+3690 => x"0b0b81c8",
+3691 => x"8c3f6980",
+3692 => x"08250b0b",
+3693 => x"0b81db38",
+3694 => x"6c5fb17f",
+3695 => x"70810541",
+3696 => x"34628105",
+3697 => x"4366527f",
+3698 => x"510b0b80",
+3699 => x"c1a23f69",
+3700 => x"802e0b0b",
+3701 => x"0bfda838",
+3702 => x"67307069",
+3703 => x"079f2a51",
+3704 => x"56676a2e",
+3705 => x"0b0b0b0b",
+3706 => x"8838750b",
+3707 => x"0b0b80e5",
+3708 => x"3869527f",
+3709 => x"510b0b80",
+3710 => x"c0f63f0b",
+3711 => x"0b0bfcff",
+3712 => x"39817071",
+3713 => x"a63d0c71",
+3714 => x"485d490b",
+3715 => x"0b0beff1",
+3716 => x"39815a0b",
+3717 => x"0b0bf28b",
+3718 => x"39811c7b",
+3719 => x"08841d08",
+3720 => x"59557756",
+3721 => x"78537954",
+3722 => x"65525c0b",
+3723 => x"0b818ded",
+3724 => x"3fa83d08",
+3725 => x"aa3d0871",
+3726 => x"bb3d0c70",
+3727 => x"bc3d0c7b",
+3728 => x"812c881e",
+3729 => x"5e5c5a58",
+3730 => x"790b0b0b",
+3731 => x"fdcc380b",
+3732 => x"0b0bf1a6",
+3733 => x"3967527f",
+3734 => x"510b0b80",
+3735 => x"c0923f69",
+3736 => x"527f510b",
+3737 => x"0b80c088",
+3738 => x"3f0b0b0b",
+3739 => x"fc913977",
+3740 => x"810a3253",
+3741 => x"78547951",
+3742 => x"7a520b0b",
+3743 => x"81c4a63f",
+3744 => x"80088025",
+3745 => x"0b0b0bf6",
+3746 => x"af3879b9",
+3747 => x"3d0c7aba",
+3748 => x"3d0c6809",
+3749 => x"430b0b0b",
+3750 => x"feab396a",
+3751 => x"a63d0878",
+3752 => x"794b4c59",
+3753 => x"596f802e",
+3754 => x"0b0b0b80",
+3755 => x"d0388162",
+3756 => x"250b0b0b",
+3757 => x"8ec73865",
+3758 => x"ff05a63d",
+3759 => x"08713159",
+3760 => x"5aa53d08",
+3761 => x"7a250b0b",
+3762 => x"0b0b9438",
+3763 => x"79a63d08",
+3764 => x"316f11a1",
+3765 => x"3d0ca63d",
+3766 => x"0805a63d",
+3767 => x"0c765865",
+3768 => x"5c806624",
+3769 => x"0b0b0b84",
+3770 => x"cb386a1c",
+3771 => x"641d454b",
+3772 => x"81527f51",
+3773 => x"0b0b80c4",
+3774 => x"de3f8008",
+3775 => x"4a788024",
+3776 => x"56806425",
+3777 => x"0b0b0b0b",
+3778 => x"a3387580",
+3779 => x"2e0b0b0b",
+3780 => x"0b9a3863",
+3781 => x"5c786425",
+3782 => x"0b0b0b0b",
+3783 => x"8338785c",
+3784 => x"6a7c3179",
+3785 => x"7d31657e",
+3786 => x"31465a4b",
+3787 => x"800ba63d",
+3788 => x"08250b0b",
+3789 => x"0b80cb38",
+3790 => x"6f802e0b",
+3791 => x"0b0b8ae5",
+3792 => x"38807825",
+3793 => x"0b0b0b0b",
+3794 => x"ac387753",
+3795 => x"69527f51",
+3796 => x"0b0b80c7",
+3797 => x"943f8008",
+3798 => x"61548008",
+3799 => x"5360524a",
+3800 => x"0b0b80c4",
+3801 => x"8e3f8008",
+3802 => x"61536052",
+3803 => x"560b0b0b",
+3804 => x"bdfe3f75",
+3805 => x"41a53d08",
+3806 => x"78315a79",
+3807 => x"0b0b0b83",
+3808 => x"9e388152",
+3809 => x"7f510b0b",
+3810 => x"80c3cc3f",
+3811 => x"80084780",
+3812 => x"6f250b0b",
+3813 => x"0b0b9138",
+3814 => x"6e538008",
+3815 => x"527f510b",
+3816 => x"0b80c6c5",
+3817 => x"3f800847",
+3818 => x"80588162",
+3819 => x"250b0b0b",
+3820 => x"829b3863",
+3821 => x"81059f06",
+3822 => x"5c6e0b0b",
+3823 => x"0b81ee38",
+3824 => x"7b802e0b",
+3825 => x"0b0b0b85",
+3826 => x"38a07c31",
+3827 => x"5c847c25",
+3828 => x"0b0b0b88",
+3829 => x"c238fc1c",
+3830 => x"6b11711b",
+3831 => x"5b4c6405",
+3832 => x"44806b25",
+3833 => x"0b0b0b0b",
+3834 => x"90386a53",
+3835 => x"60527f51",
+3836 => x"0b0b80c7",
+3837 => x"f23f8008",
+3838 => x"41806425",
+3839 => x"0b0b0b0b",
+3840 => x"90386353",
+3841 => x"66527f51",
+3842 => x"0b0b80c7",
+3843 => x"da3f8008",
+3844 => x"47a13d08",
+3845 => x"0b0b0b80",
+3846 => x"da388066",
+3847 => x"25568262",
+3848 => x"250b0b0b",
+3849 => x"82c73875",
+3850 => x"802e0b0b",
+3851 => x"0b82be38",
+3852 => x"8066240b",
+3853 => x"0b0bfcda",
+3854 => x"38805485",
+3855 => x"5366527f",
+3856 => x"510b0b0b",
+3857 => x"bcce3f80",
+3858 => x"08800853",
+3859 => x"6152470b",
+3860 => x"0b80c985",
+3861 => x"3f800b80",
+3862 => x"08250b0b",
+3863 => x"0bfcb338",
+3864 => x"6c5fb17f",
+3865 => x"70810541",
+3866 => x"34628105",
+3867 => x"430b0b0b",
+3868 => x"fad33966",
+3869 => x"5260510b",
+3870 => x"0b80c8dd",
+3871 => x"3f800880",
+3872 => x"250b0b0b",
+3873 => x"ff943862",
+3874 => x"ff054380",
+3875 => x"548a5360",
+3876 => x"527f510b",
+3877 => x"0b0bbbfc",
+3878 => x"3f800841",
+3879 => x"6f0b0b0b",
+3880 => x"81b038a3",
+3881 => x"3d08460b",
+3882 => x"0b0bfeee",
+3883 => x"39669005",
+3884 => x"08101067",
+3885 => x"05901108",
+3886 => x"52560b0b",
+3887 => x"0bbec93f",
+3888 => x"63800831",
+3889 => x"9f065c0b",
+3890 => x"0b0bfdf4",
+3891 => x"39b93d08",
+3892 => x"782e0981",
+3893 => x"060b0b0b",
+3894 => x"fdd938b8",
+3895 => x"3d0870bf",
+3896 => x"ffff0657",
+3897 => x"5775782e",
+3898 => x"0981060b",
+3899 => x"0b0bfdc3",
+3900 => x"38769ffe",
+3901 => x"0a065675",
+3902 => x"782e0b0b",
+3903 => x"0bfdb438",
+3904 => x"6a810564",
+3905 => x"8105454b",
+3906 => x"81648105",
+3907 => x"9f065d58",
+3908 => x"6e802e0b",
+3909 => x"0b0bfda8",
+3910 => x"380b0b0b",
+3911 => x"ff8f3979",
+3912 => x"5360527f",
+3913 => x"510b0b80",
+3914 => x"c3bf3f80",
+3915 => x"08410b0b",
+3916 => x"0bfccf39",
+3917 => x"6a663159",
+3918 => x"806b114c",
+3919 => x"64054481",
+3920 => x"527f510b",
+3921 => x"0b80c08f",
+3922 => x"3f80084a",
+3923 => x"0b0b0bfb",
+3924 => x"ac398054",
+3925 => x"8a536952",
+3926 => x"7f510b0b",
+3927 => x"0bbab53f",
+3928 => x"8008a43d",
+3929 => x"08474a0b",
+3930 => x"0b0bfdae",
+3931 => x"39815c6f",
+3932 => x"802e0b0b",
+3933 => x"0b82bb38",
+3934 => x"8079250b",
+3935 => x"0b0b0b90",
+3936 => x"38785369",
+3937 => x"527f510b",
+3938 => x"0b80c4db",
+3939 => x"3f80084a",
+3940 => x"6948770b",
+3941 => x"0b0b82e9",
+3942 => x"38815c66",
+3943 => x"5260510b",
+3944 => x"0b0bdce3",
+3945 => x"3f8008b0",
+3946 => x"05685361",
+3947 => x"52570b0b",
+3948 => x"80c6a63f",
+3949 => x"80086a54",
+3950 => x"67536052",
+3951 => x"5a0b0b80",
+3952 => x"c6fe3f80",
+3953 => x"0856815b",
+3954 => x"80088c05",
+3955 => x"08802e0b",
+3956 => x"0b0b8299",
+3957 => x"3875527f",
+3958 => x"510b0b0b",
+3959 => x"b9923f7a",
+3960 => x"62075675",
+3961 => x"0b0b0b0b",
+3962 => x"9038b93d",
+3963 => x"08810656",
+3964 => x"75802e0b",
+3965 => x"0b0b82c8",
+3966 => x"38807a24",
+3967 => x"0b0b0b82",
+3968 => x"da387962",
+3969 => x"0756750b",
+3970 => x"0b0b0b90",
+3971 => x"38b93d08",
+3972 => x"81065675",
+3973 => x"802e0b0b",
+3974 => x"0b82c038",
+3975 => x"7a80240b",
+3976 => x"0b0b8883",
+3977 => x"38767f70",
+3978 => x"81054134",
+3979 => x"7b662e0b",
+3980 => x"0b0b83fd",
+3981 => x"3880548a",
+3982 => x"5360527f",
+3983 => x"510b0b0b",
+3984 => x"b8d23f80",
+3985 => x"0841676a",
+3986 => x"2e0b0b0b",
+3987 => x"83ac3880",
+3988 => x"548a5367",
+3989 => x"527f510b",
+3990 => x"0b0bb8b8",
+3991 => x"3f800848",
+3992 => x"80548a53",
+3993 => x"69527f51",
+3994 => x"0b0b0bb8",
+3995 => x"a73f8008",
+3996 => x"811d5d4a",
+3997 => x"66526051",
+3998 => x"0b0b0bdb",
+3999 => x"8a3f8008",
+4000 => x"b0056853",
+4001 => x"6152570b",
+4002 => x"0b80c4cd",
+4003 => x"3f80086a",
+4004 => x"54675360",
+4005 => x"525a0b0b",
+4006 => x"80c5a53f",
+4007 => x"80085681",
+4008 => x"5b80088c",
+4009 => x"05080b0b",
+4010 => x"0bfeaa38",
+4011 => x"0b0b0b0b",
+4012 => x"bc396652",
+4013 => x"7e7f8105",
+4014 => x"62534056",
+4015 => x"0b0b0bda",
+4016 => x"c63f8008",
+4017 => x"b0055776",
+4018 => x"76347b66",
+4019 => x"250b0b0b",
+4020 => x"82df3880",
+4021 => x"548a5360",
+4022 => x"527f510b",
+4023 => x"0b0bb7b4",
+4024 => x"3f800881",
+4025 => x"1d5d410b",
+4026 => x"0b0b0bc6",
+4027 => x"39800852",
+4028 => x"60510b0b",
+4029 => x"80c3e23f",
+4030 => x"80085b0b",
+4031 => x"0b0bfdd5",
+4032 => x"39698405",
+4033 => x"08527f51",
+4034 => x"0b0b0bb5",
+4035 => x"bc3f8008",
+4036 => x"68900508",
+4037 => x"10108805",
+4038 => x"54688c05",
+4039 => x"5380088c",
+4040 => x"05524a0b",
+4041 => x"0bff94e3",
+4042 => x"3f815369",
+4043 => x"527f510b",
+4044 => x"0b80c1b3",
+4045 => x"3f80084a",
+4046 => x"815c0b0b",
+4047 => x"0bfcdc39",
+4048 => x"76b92e0b",
+4049 => x"0b0b80d0",
+4050 => x"38798024",
+4051 => x"1757767f",
+4052 => x"70810541",
+4053 => x"340b0b0b",
+4054 => x"f4eb3980",
+4055 => x"7b250b0b",
+4056 => x"0b0beb38",
+4057 => x"81536052",
+4058 => x"7f510b0b",
+4059 => x"80c0f83f",
+4060 => x"80086753",
+4061 => x"80085241",
+4062 => x"0b0b80c2",
+4063 => x"dc3f800b",
+4064 => x"8008250b",
+4065 => x"0b0b80c8",
+4066 => x"38811757",
+4067 => x"76ba2e09",
+4068 => x"81060b0b",
+4069 => x"0bffb738",
+4070 => x"b97f7081",
+4071 => x"054134ff",
+4072 => x"1f703357",
+4073 => x"5f75b92e",
+4074 => x"0981060b",
+4075 => x"0b0b81d0",
+4076 => x"387e6d2e",
+4077 => x"0981060b",
+4078 => x"0b0b0be3",
+4079 => x"38628105",
+4080 => x"6d4043b1",
+4081 => x"7f708105",
+4082 => x"41340b0b",
+4083 => x"0bf3f639",
+4084 => x"80080b0b",
+4085 => x"0bfef738",
+4086 => x"76810656",
+4087 => x"75802e0b",
+4088 => x"0b0bfeea",
+4089 => x"38811757",
+4090 => x"76ba2e09",
+4091 => x"81060b0b",
+4092 => x"0bfedb38",
+4093 => x"0b0b0bff",
+4094 => x"9f398054",
+4095 => x"8a536952",
+4096 => x"7f510b0b",
+4097 => x"0bb58d3f",
+4098 => x"80088008",
+4099 => x"811e5e49",
+4100 => x"4a0b0b0b",
+4101 => x"fcde397b",
+4102 => x"83240b0b",
+4103 => x"0bf7c238",
+4104 => x"9c1c6b11",
+4105 => x"711b5b4c",
+4106 => x"6405440b",
+4107 => x"0b0bf7b1",
+4108 => x"39815360",
+4109 => x"527f510b",
+4110 => x"0b0bbfab",
+4111 => x"3f800867",
+4112 => x"53800852",
+4113 => x"410b0b80",
+4114 => x"c18f3f80",
+4115 => x"0880240b",
+4116 => x"0b0bfecb",
+4117 => x"3880080b",
+4118 => x"0b0b0b8c",
+4119 => x"38768106",
+4120 => x"56750b0b",
+4121 => x"0bfeb838",
+4122 => x"ff1f7033",
+4123 => x"575f75b0",
+4124 => x"2e0b0b0b",
+4125 => x"0bf23881",
+4126 => x"1f5f0b0b",
+4127 => x"0bf2c639",
+4128 => x"7e7f8105",
+4129 => x"71338105",
+4130 => x"58405775",
+4131 => x"77340b0b",
+4132 => x"0bf2b239",
+4133 => x"6a633163",
+4134 => x"30a73d0c",
+4135 => x"4b804f0b",
+4136 => x"0b0bdff1",
+4137 => x"39a53d08",
+4138 => x"5360527f",
+4139 => x"510b0b0b",
+4140 => x"bcb73f80",
+4141 => x"08410b0b",
+4142 => x"0bf5c739",
+4143 => x"65101010",
+4144 => x"0b0b82f2",
+4145 => x"d0058411",
+4146 => x"08710856",
+4147 => x"56b53d08",
+4148 => x"b73d0859",
+4149 => x"53567653",
+4150 => x"64510b0b",
+4151 => x"8180be3f",
+4152 => x"a83d08aa",
+4153 => x"3d0858b5",
+4154 => x"3d0c76b6",
+4155 => x"3d0c810b",
+4156 => x"b93d08bb",
+4157 => x"3d085b59",
+4158 => x"5c775178",
+4159 => x"520b0b81",
+4160 => x"bdeb3f80",
+4161 => x"08800853",
+4162 => x"65525a0b",
+4163 => x"0b81bbbd",
+4164 => x"3fa83d08",
+4165 => x"aa3d0858",
+4166 => x"547655b8",
+4167 => x"3d08ba3d",
+4168 => x"08585276",
+4169 => x"536b510b",
+4170 => x"0b80febe",
+4171 => x"3faa3d08",
+4172 => x"ac3d085a",
+4173 => x"b93d0c78",
+4174 => x"ba3d0cb0",
+4175 => x"1a56757f",
+4176 => x"70810541",
+4177 => x"347b662e",
+4178 => x"0b0b0be7",
+4179 => x"f038811c",
+4180 => x"5c80c882",
+4181 => x"0a568076",
+4182 => x"5555b83d",
+4183 => x"08ba3d08",
+4184 => x"58527653",
+4185 => x"64510b0b",
+4186 => x"80ffb23f",
+4187 => x"a83d08aa",
+4188 => x"3d0871bb",
+4189 => x"3d0c70bc",
+4190 => x"3d0c5a58",
+4191 => x"0b0b0bfe",
+4192 => x"f839ff1f",
+4193 => x"7033575f",
+4194 => x"75b02e0b",
+4195 => x"0b0b0bf2",
+4196 => x"38811f5f",
+4197 => x"0b0b0bed",
+4198 => x"e6396566",
+4199 => x"484a80d0",
+4200 => x"820a5680",
+4201 => x"765555b8",
+4202 => x"3d08ba3d",
+4203 => x"08585276",
+4204 => x"5364510b",
+4205 => x"0b80fdb2",
+4206 => x"3fa83d08",
+4207 => x"aa3d08b6",
+4208 => x"3d08b83d",
+4209 => x"08715770",
+4210 => x"58735572",
+4211 => x"565c5a5c",
+4212 => x"5a0b0b81",
+4213 => x"b3bb3f80",
+4214 => x"0b800825",
+4215 => x"0b0b0bf1",
+4216 => x"8e3879b9",
+4217 => x"3d0c7aba",
+4218 => x"3d0c6c5f",
+4219 => x"b17f7081",
+4220 => x"05413462",
+4221 => x"8105430b",
+4222 => x"0b0befc9",
+4223 => x"3988b316",
+4224 => x"5c6d0b0b",
+4225 => x"0bf1e338",
+4226 => x"b60ba83d",
+4227 => x"08316b11",
+4228 => x"4c640544",
+4229 => x"81527f51",
+4230 => x"0b0b0bb6",
+4231 => x"ba3f8008",
+4232 => x"4a0b0b0b",
+4233 => x"f1d73976",
+4234 => x"b92e0b0b",
+4235 => x"0bfae938",
+4236 => x"81175675",
+4237 => x"7f708105",
+4238 => x"41340b0b",
+4239 => x"0bef8639",
+4240 => x"f83d0d7a",
+4241 => x"5877802e",
+4242 => x"0b0b0b81",
+4243 => x"bd380b0b",
+4244 => x"82f4ec08",
+4245 => x"54b81408",
+4246 => x"802e0b0b",
+4247 => x"0b818238",
+4248 => x"8c182270",
+4249 => x"902b7090",
+4250 => x"2c70832a",
+4251 => x"81328106",
+4252 => x"5c515754",
+4253 => x"780b0b0b",
+4254 => x"80df3890",
+4255 => x"18085776",
+4256 => x"802e0b0b",
+4257 => x"0b80d238",
+4258 => x"77087731",
+4259 => x"77790c76",
+4260 => x"83067a58",
+4261 => x"5555730b",
+4262 => x"0b0b0b85",
+4263 => x"38941808",
+4264 => x"56758819",
+4265 => x"0c807525",
+4266 => x"0b0b0b0b",
+4267 => x"ac387453",
+4268 => x"76529c18",
+4269 => x"0851a418",
+4270 => x"0854732d",
+4271 => x"800b8008",
+4272 => x"250b0b0b",
+4273 => x"80df3880",
+4274 => x"08177580",
+4275 => x"08315657",
+4276 => x"7480240b",
+4277 => x"0b0b0bd6",
+4278 => x"38800b80",
+4279 => x"0c8a3d0d",
+4280 => x"0473510b",
+4281 => x"0b0b81f7",
+4282 => x"3f8c1822",
+4283 => x"70902b70",
+4284 => x"902c7083",
+4285 => x"2a813281",
+4286 => x"065c5157",
+4287 => x"54780b0b",
+4288 => x"0b0bd638",
+4289 => x"0b0b0bfe",
+4290 => x"f2390b0b",
+4291 => x"8184c052",
+4292 => x"0b0b82f4",
+4293 => x"ec08510b",
+4294 => x"0b0b93b4",
+4295 => x"3f800880",
+4296 => x"0c8a3d0d",
+4297 => x"048c1822",
+4298 => x"80c00754",
+4299 => x"738c1923",
+4300 => x"ff0b800c",
+4301 => x"8a3d0d04",
+4302 => x"70725180",
+4303 => x"710c800b",
+4304 => x"84120c80",
+4305 => x"0b88120c",
+4306 => x"028e0522",
+4307 => x"8c122302",
+4308 => x"9205228e",
+4309 => x"1223800b",
+4310 => x"90120c80",
+4311 => x"0b94120c",
+4312 => x"800b9812",
+4313 => x"0c709c12",
+4314 => x"0c0b0b81",
+4315 => x"d7880ba0",
+4316 => x"120c0b0b",
+4317 => x"81d7dd0b",
+4318 => x"a4120c0b",
+4319 => x"0b81d8ec",
+4320 => x"0ba8120c",
+4321 => x"0b0b81d9",
+4322 => x"c60bac12",
+4323 => x"0c5004fa",
+4324 => x"3d0d7970",
+4325 => x"80dc298c",
+4326 => x"11547a53",
+4327 => x"56570b0b",
+4328 => x"0b989f3f",
+4329 => x"80088008",
+4330 => x"55568008",
+4331 => x"802e0b0b",
+4332 => x"0b0ba538",
+4333 => x"80088c05",
+4334 => x"54800b80",
+4335 => x"080c7680",
+4336 => x"0884050c",
+4337 => x"73800888",
+4338 => x"050c7453",
+4339 => x"80527351",
+4340 => x"0b0b0baa",
+4341 => x"c03f7554",
+4342 => x"73800c88",
+4343 => x"3d0d04fc",
+4344 => x"3d0d760b",
+4345 => x"0b818aa8",
+4346 => x"0bbc120c",
+4347 => x"55810bb8",
+4348 => x"160c800b",
+4349 => x"84dc160c",
+4350 => x"830b84e0",
+4351 => x"160c84e8",
+4352 => x"1584e416",
+4353 => x"0c745480",
+4354 => x"53845284",
+4355 => x"1508510b",
+4356 => x"0b0bfea4",
+4357 => x"3f745481",
+4358 => x"53895288",
+4359 => x"1508510b",
+4360 => x"0b0bfe94",
+4361 => x"3f745482",
+4362 => x"538a528c",
+4363 => x"1508510b",
+4364 => x"0b0bfe84",
+4365 => x"3f863d0d",
+4366 => x"04f93d0d",
+4367 => x"790b0b82",
+4368 => x"f4ec0854",
+4369 => x"57b81308",
+4370 => x"802e0b0b",
+4371 => x"0b80db38",
+4372 => x"84dc1356",
+4373 => x"88160884",
+4374 => x"1708ff05",
+4375 => x"55558074",
+4376 => x"240b0b0b",
+4377 => x"0ba6388c",
+4378 => x"15227090",
+4379 => x"2b70902c",
+4380 => x"51545872",
+4381 => x"802e0b0b",
+4382 => x"0b80e838",
+4383 => x"80dc15ff",
+4384 => x"15555573",
+4385 => x"80250b0b",
+4386 => x"0b0bdc38",
+4387 => x"75085372",
+4388 => x"802e0b0b",
+4389 => x"0b0bab38",
+4390 => x"72568816",
+4391 => x"08841708",
+4392 => x"ff055555",
+4393 => x"0b0b0bff",
+4394 => x"b5397251",
+4395 => x"0b0b0bfe",
+4396 => x"ae3f0b0b",
+4397 => x"82f4ec08",
+4398 => x"84dc0556",
+4399 => x"0b0b0bff",
+4400 => x"93398452",
+4401 => x"76510b0b",
+4402 => x"0bfdc43f",
+4403 => x"8008760c",
+4404 => x"8008802e",
+4405 => x"0b0b0b80",
+4406 => x"c4388008",
+4407 => x"560b0b0b",
+4408 => x"ffb83981",
+4409 => x"0b8c1623",
+4410 => x"72750c72",
+4411 => x"88160c72",
+4412 => x"84160c72",
+4413 => x"90160c72",
+4414 => x"94160c72",
+4415 => x"98160cff",
+4416 => x"0b8e1623",
+4417 => x"72b0160c",
+4418 => x"72b4160c",
+4419 => x"7280c416",
+4420 => x"0c7280c8",
+4421 => x"160c7480",
+4422 => x"0c893d0d",
+4423 => x"048c770c",
+4424 => x"800b800c",
+4425 => x"893d0d04",
+4426 => x"70700b0b",
+4427 => x"8184c052",
+4428 => x"73510b0b",
+4429 => x"0b8f993f",
+4430 => x"50500470",
+4431 => x"0b0b82f4",
+4432 => x"ec08510b",
+4433 => x"0b0b0be0",
+4434 => x"3f5004fb",
+4435 => x"3d0d7770",
+4436 => x"52560b0b",
+4437 => x"0ba8f03f",
+4438 => x"0b0b82fc",
+4439 => x"c80b8805",
+4440 => x"08841108",
+4441 => x"fc06707b",
+4442 => x"319fef05",
+4443 => x"e08006e0",
+4444 => x"80055656",
+4445 => x"53a08074",
+4446 => x"240b0b0b",
+4447 => x"0b9d3880",
+4448 => x"5275510b",
+4449 => x"0b80cbba",
+4450 => x"3f0b0b82",
+4451 => x"fcd00815",
+4452 => x"53728008",
+4453 => x"2e0b0b0b",
+4454 => x"0b923875",
+4455 => x"510b0b0b",
+4456 => x"a8a63f80",
+4457 => x"5372800c",
+4458 => x"873d0d04",
+4459 => x"73305275",
+4460 => x"510b0b80",
+4461 => x"cb8c3f80",
+4462 => x"08ff2e0b",
+4463 => x"0b0b0bb1",
+4464 => x"380b0b82",
+4465 => x"fcc80b88",
+4466 => x"05087575",
+4467 => x"31810784",
+4468 => x"120c530b",
+4469 => x"0b82fc8c",
+4470 => x"0874310b",
+4471 => x"0b82fc8c",
+4472 => x"0c75510b",
+4473 => x"0b0ba7e0",
+4474 => x"3f810b80",
+4475 => x"0c873d0d",
+4476 => x"04805275",
+4477 => x"510b0b80",
+4478 => x"cac83f0b",
+4479 => x"0b82fcc8",
+4480 => x"0b880508",
+4481 => x"80087131",
+4482 => x"56538f75",
+4483 => x"250b0b0b",
+4484 => x"ff893880",
+4485 => x"080b0b82",
+4486 => x"fcbc0831",
+4487 => x"0b0b82fc",
+4488 => x"8c0c7481",
+4489 => x"0784140c",
+4490 => x"75510b0b",
+4491 => x"0ba7993f",
+4492 => x"80530b0b",
+4493 => x"0bfeee39",
+4494 => x"f63d0d7c",
+4495 => x"7e545b72",
+4496 => x"802e0b0b",
+4497 => x"0b82c838",
+4498 => x"7a510b0b",
+4499 => x"0ba6f83f",
+4500 => x"f8138411",
+4501 => x"0870fe06",
+4502 => x"70138411",
+4503 => x"08fc065d",
+4504 => x"58595458",
+4505 => x"0b0b82fc",
+4506 => x"d008752e",
+4507 => x"0b0b0b83",
+4508 => x"b5387884",
+4509 => x"160c8073",
+4510 => x"8106545a",
+4511 => x"727a2e0b",
+4512 => x"0b0b828f",
+4513 => x"38781584",
+4514 => x"11088106",
+4515 => x"5153720b",
+4516 => x"0b0b0ba8",
+4517 => x"38781757",
+4518 => x"790b0b0b",
+4519 => x"82a13888",
+4520 => x"15085372",
+4521 => x"0b0b82fc",
+4522 => x"d02e0b0b",
+4523 => x"0b83d738",
+4524 => x"8c150870",
+4525 => x"8c150c73",
+4526 => x"88120c56",
+4527 => x"76810784",
+4528 => x"190c7618",
+4529 => x"77710c53",
+4530 => x"790b0b0b",
+4531 => x"81b93883",
+4532 => x"ff77270b",
+4533 => x"0b0b81fb",
+4534 => x"3876892a",
+4535 => x"77832a56",
+4536 => x"5372802e",
+4537 => x"0b0b0b80",
+4538 => x"d3387686",
+4539 => x"2ab80555",
+4540 => x"8473270b",
+4541 => x"0b0b80c4",
+4542 => x"3880db13",
+4543 => x"55947327",
+4544 => x"0b0b0b0b",
+4545 => x"b738768c",
+4546 => x"2a80ee05",
+4547 => x"5580d473",
+4548 => x"270b0b0b",
+4549 => x"0ba63876",
+4550 => x"8f2a80f7",
+4551 => x"055582d4",
+4552 => x"73270b0b",
+4553 => x"0b0b9538",
+4554 => x"76922a80",
+4555 => x"fc05558a",
+4556 => x"d473270b",
+4557 => x"0b0b0b84",
+4558 => x"3880fe55",
+4559 => x"74101010",
+4560 => x"0b0b82fc",
+4561 => x"c8058811",
+4562 => x"08555673",
+4563 => x"762e0b0b",
+4564 => x"0b82fa38",
+4565 => x"841408fc",
+4566 => x"06537673",
+4567 => x"270b0b0b",
+4568 => x"0b913888",
+4569 => x"14085473",
+4570 => x"762e0981",
+4571 => x"060b0b0b",
+4572 => x"0be2388c",
+4573 => x"1408708c",
+4574 => x"1a0c7488",
+4575 => x"1a0c7888",
+4576 => x"120c5677",
+4577 => x"8c150c7a",
+4578 => x"510b0b0b",
+4579 => x"a4ba3f8c",
+4580 => x"3d0d0477",
+4581 => x"08787131",
+4582 => x"59770588",
+4583 => x"19085457",
+4584 => x"720b0b82",
+4585 => x"fcd02e0b",
+4586 => x"0b0b80f2",
+4587 => x"388c1808",
+4588 => x"708c150c",
+4589 => x"7388120c",
+4590 => x"560b0b0b",
+4591 => x"fdc73988",
+4592 => x"15088c16",
+4593 => x"08708c13",
+4594 => x"0c578817",
+4595 => x"0c0b0b0b",
+4596 => x"fdea3976",
+4597 => x"832a7054",
+4598 => x"55807524",
+4599 => x"0b0b0b81",
+4600 => x"bd387282",
+4601 => x"2c81712b",
+4602 => x"0b0b82fc",
+4603 => x"cc08070b",
+4604 => x"0b82fcc8",
+4605 => x"0b84050c",
+4606 => x"53741010",
+4607 => x"100b0b82",
+4608 => x"fcc80588",
+4609 => x"11085556",
+4610 => x"758c190c",
+4611 => x"7388190c",
+4612 => x"7788170c",
+4613 => x"778c150c",
+4614 => x"0b0b0bfe",
+4615 => x"ea39815a",
+4616 => x"0b0b0bfc",
+4617 => x"e0397817",
+4618 => x"73810654",
+4619 => x"57720b0b",
+4620 => x"0b0b9838",
+4621 => x"77087871",
+4622 => x"31597705",
+4623 => x"8c190888",
+4624 => x"1a08718c",
+4625 => x"120c8812",
+4626 => x"0c575776",
+4627 => x"81078419",
+4628 => x"0c770b0b",
+4629 => x"82fcc80b",
+4630 => x"88050c0b",
+4631 => x"0b82fcc4",
+4632 => x"0877260b",
+4633 => x"0b0bfe9f",
+4634 => x"380b0b82",
+4635 => x"fcc00852",
+4636 => x"7a510b0b",
+4637 => x"0bf9d43f",
+4638 => x"7a510b0b",
+4639 => x"0ba2c93f",
+4640 => x"0b0b0bfe",
+4641 => x"8a398178",
+4642 => x"8c150c78",
+4643 => x"88150c73",
+4644 => x"8c1a0c73",
+4645 => x"881a0c5a",
+4646 => x"0b0b0bfc",
+4647 => x"9f398315",
+4648 => x"70822c81",
+4649 => x"712b0b0b",
+4650 => x"82fccc08",
+4651 => x"070b0b82",
+4652 => x"fcc80b84",
+4653 => x"050c5153",
+4654 => x"74101010",
+4655 => x"0b0b82fc",
+4656 => x"c8058811",
+4657 => x"0855560b",
+4658 => x"0b0bfebc",
+4659 => x"39745380",
+4660 => x"75240b0b",
+4661 => x"0b0bae38",
+4662 => x"72822c81",
+4663 => x"712b0b0b",
+4664 => x"82fccc08",
+4665 => x"070b0b82",
+4666 => x"fcc80b84",
+4667 => x"050c5375",
+4668 => x"8c190c73",
+4669 => x"88190c77",
+4670 => x"88170c77",
+4671 => x"8c150c0b",
+4672 => x"0b0bfd83",
+4673 => x"39831570",
+4674 => x"822c8171",
+4675 => x"2b0b0b82",
+4676 => x"fccc0807",
+4677 => x"0b0b82fc",
+4678 => x"c80b8405",
+4679 => x"0c51530b",
+4680 => x"0b0b0bcb",
+4681 => x"39f23d0d",
+4682 => x"60628811",
+4683 => x"08705757",
+4684 => x"5f5a7480",
+4685 => x"2e0b0b0b",
+4686 => x"81b3388c",
+4687 => x"1a227083",
+4688 => x"2a813270",
+4689 => x"81065155",
+4690 => x"58730b0b",
+4691 => x"0b0b8a38",
+4692 => x"901a080b",
+4693 => x"0b0b0b97",
+4694 => x"3879510b",
+4695 => x"0b0bc388",
+4696 => x"3fff5480",
+4697 => x"080b0b0b",
+4698 => x"8183388c",
+4699 => x"1a22587d",
+4700 => x"08578078",
+4701 => x"83ffff06",
+4702 => x"700a100a",
+4703 => x"70810651",
+4704 => x"56575573",
+4705 => x"752e0b0b",
+4706 => x"0b80e938",
+4707 => x"740b0b0b",
+4708 => x"0b943876",
+4709 => x"08841808",
+4710 => x"88195956",
+4711 => x"5974802e",
+4712 => x"0b0b0b0b",
+4713 => x"ee387454",
+4714 => x"88807527",
+4715 => x"0b0b0b0b",
+4716 => x"84388880",
+4717 => x"54735378",
+4718 => x"529c1a08",
+4719 => x"51a41a08",
+4720 => x"54732d80",
+4721 => x"0b800825",
+4722 => x"0b0b0b83",
+4723 => x"bf388008",
+4724 => x"19758008",
+4725 => x"317f8805",
+4726 => x"08800831",
+4727 => x"70618805",
+4728 => x"0c565659",
+4729 => x"730b0b0b",
+4730 => x"ffa23880",
+4731 => x"5473800c",
+4732 => x"903d0d04",
+4733 => x"75813270",
+4734 => x"81067641",
+4735 => x"51547380",
+4736 => x"2e0b0b0b",
+4737 => x"81f03874",
+4738 => x"0b0b0b0b",
+4739 => x"94387608",
+4740 => x"84180888",
+4741 => x"19595659",
+4742 => x"74802e0b",
+4743 => x"0b0b0bee",
+4744 => x"38881a08",
+4745 => x"7883ffff",
+4746 => x"0670892a",
+4747 => x"70810651",
+4748 => x"56595673",
+4749 => x"802e0b0b",
+4750 => x"0b83e338",
+4751 => x"7575270b",
+4752 => x"0b0b0b90",
+4753 => x"3877872a",
+4754 => x"70810651",
+4755 => x"54730b0b",
+4756 => x"0b838c38",
+4757 => x"7476270b",
+4758 => x"0b0b0b83",
+4759 => x"38745675",
+4760 => x"53785279",
+4761 => x"08510b0b",
+4762 => x"0b9bb83f",
+4763 => x"881a0876",
+4764 => x"31881b0c",
+4765 => x"7908167a",
+4766 => x"0c745675",
+4767 => x"19757731",
+4768 => x"7f880508",
+4769 => x"78317061",
+4770 => x"88050c56",
+4771 => x"56597380",
+4772 => x"2e0b0b0b",
+4773 => x"fed5388c",
+4774 => x"1a22580b",
+4775 => x"0b0bfee7",
+4776 => x"39777854",
+4777 => x"79537b52",
+4778 => x"560b0b0b",
+4779 => x"9af53f88",
+4780 => x"1a087831",
+4781 => x"881b0c79",
+4782 => x"08187a0c",
+4783 => x"7c76315d",
+4784 => x"7c0b0b0b",
+4785 => x"0b943879",
+4786 => x"510b0b0b",
+4787 => x"eef23f80",
+4788 => x"080b0b0b",
+4789 => x"81b63880",
+4790 => x"085f7519",
+4791 => x"7577317f",
+4792 => x"88050878",
+4793 => x"31706188",
+4794 => x"050c5656",
+4795 => x"5973802e",
+4796 => x"0b0b0bfd",
+4797 => x"f638740b",
+4798 => x"0b0b81a4",
+4799 => x"38760884",
+4800 => x"18088819",
+4801 => x"59565974",
+4802 => x"802e0b0b",
+4803 => x"0b0bee38",
+4804 => x"74538a52",
+4805 => x"78510b0b",
+4806 => x"0b98bb3f",
+4807 => x"80087931",
+4808 => x"81055d80",
+4809 => x"080b0b0b",
+4810 => x"0b843881",
+4811 => x"155d815f",
+4812 => x"7c58747d",
+4813 => x"270b0b0b",
+4814 => x"0b833874",
+4815 => x"58941a08",
+4816 => x"881b0811",
+4817 => x"575c807a",
+4818 => x"085c5490",
+4819 => x"1a087b27",
+4820 => x"0b0b0b0b",
+4821 => x"83388154",
+4822 => x"7578250b",
+4823 => x"0b0b0b88",
+4824 => x"38730b0b",
+4825 => x"0b80c638",
+4826 => x"7b78240b",
+4827 => x"0b0bfeb1",
+4828 => x"387b5378",
+4829 => x"529c1a08",
+4830 => x"51a41a08",
+4831 => x"54732d80",
+4832 => x"08568008",
+4833 => x"80240b0b",
+4834 => x"0bfeb138",
+4835 => x"8c1a2280",
+4836 => x"c0075473",
+4837 => x"8c1b23ff",
+4838 => x"5473800c",
+4839 => x"903d0d04",
+4840 => x"7e0b0b0b",
+4841 => x"ff8a380b",
+4842 => x"0b0bfee4",
+4843 => x"39755378",
+4844 => x"527a510b",
+4845 => x"0b0b98eb",
+4846 => x"3f790816",
+4847 => x"7a0c7951",
+4848 => x"0b0b0bec",
+4849 => x"fb3f8008",
+4850 => x"0b0b0bff",
+4851 => x"bf387c76",
+4852 => x"315d7c0b",
+4853 => x"0b0bfe82",
+4854 => x"380b0b0b",
+4855 => x"fde93990",
+4856 => x"1a087a08",
+4857 => x"71317611",
+4858 => x"70565a57",
+4859 => x"520b0b82",
+4860 => x"f4ec0851",
+4861 => x"0b0b0bb4",
+4862 => x"ad3f8008",
+4863 => x"802e0b0b",
+4864 => x"0bff8938",
+4865 => x"8008901b",
+4866 => x"0c800816",
+4867 => x"7a0c7794",
+4868 => x"1b0c7488",
+4869 => x"1b0c7456",
+4870 => x"0b0b0bfc",
+4871 => x"b7397908",
+4872 => x"58901a08",
+4873 => x"78270b0b",
+4874 => x"0b0b8338",
+4875 => x"81547575",
+4876 => x"270b0b0b",
+4877 => x"0b883873",
+4878 => x"0b0b0b0b",
+4879 => x"bc38941a",
+4880 => x"08567575",
+4881 => x"260b0b0b",
+4882 => x"80e53875",
+4883 => x"5378529c",
+4884 => x"1a0851a4",
+4885 => x"1a085473",
+4886 => x"2d800856",
+4887 => x"80088024",
+4888 => x"0b0b0bfc",
+4889 => x"96388c1a",
+4890 => x"2280c007",
+4891 => x"54738c1b",
+4892 => x"23ff540b",
+4893 => x"0b0bfea1",
+4894 => x"39755378",
+4895 => x"5277510b",
+4896 => x"0b0b979f",
+4897 => x"3f790816",
+4898 => x"7a0c7951",
+4899 => x"0b0b0beb",
+4900 => x"af3f8008",
+4901 => x"802e0b0b",
+4902 => x"0bfbe038",
+4903 => x"8c1a2280",
+4904 => x"c0075473",
+4905 => x"8c1b23ff",
+4906 => x"540b0b0b",
+4907 => x"fdeb3974",
+4908 => x"75547953",
+4909 => x"7852560b",
+4910 => x"0b0b96e7",
+4911 => x"3f881a08",
+4912 => x"7531881b",
+4913 => x"0c790815",
+4914 => x"7a0c0b0b",
+4915 => x"0bfbac39",
+4916 => x"f93d0d79",
+4917 => x"7b585380",
+4918 => x"0b0b0b82",
+4919 => x"f4ec0853",
+4920 => x"5672722e",
+4921 => x"0b0b0b80",
+4922 => x"d53884dc",
+4923 => x"13557476",
+4924 => x"2e0b0b0b",
+4925 => x"80c83888",
+4926 => x"15088416",
+4927 => x"08ff0554",
+4928 => x"54807324",
+4929 => x"0b0b0b0b",
+4930 => x"a4388c14",
+4931 => x"2270902b",
+4932 => x"70902c51",
+4933 => x"5358710b",
+4934 => x"0b0b80f6",
+4935 => x"3880dc14",
+4936 => x"ff145454",
+4937 => x"7280250b",
+4938 => x"0b0b0bde",
+4939 => x"38740855",
+4940 => x"740b0b0b",
+4941 => x"0bc1380b",
+4942 => x"0b82f4ec",
+4943 => x"085284dc",
+4944 => x"12557480",
+4945 => x"2e0b0b0b",
+4946 => x"80c13888",
+4947 => x"15088416",
+4948 => x"08ff0554",
+4949 => x"54807324",
+4950 => x"0b0b0b0b",
+4951 => x"a4388c14",
+4952 => x"2270902b",
+4953 => x"70902c51",
+4954 => x"5358710b",
+4955 => x"0b0b0bb8",
+4956 => x"3880dc14",
+4957 => x"ff145454",
+4958 => x"7280250b",
+4959 => x"0b0b0bde",
+4960 => x"38740855",
+4961 => x"740b0b0b",
+4962 => x"0bc13875",
+4963 => x"800c893d",
+4964 => x"0d047351",
+4965 => x"762d7580",
+4966 => x"080780dc",
+4967 => x"15ff1555",
+4968 => x"55560b0b",
+4969 => x"0bfefd39",
+4970 => x"7351762d",
+4971 => x"75800807",
+4972 => x"80dc15ff",
+4973 => x"15555556",
+4974 => x"0b0b0bff",
+4975 => x"bb39fc3d",
+4976 => x"0d767955",
+4977 => x"5573802e",
+4978 => x"0b0b0b0b",
+4979 => x"9f380b0b",
+4980 => x"82f1c852",
+4981 => x"73510b0b",
+4982 => x"0bbe8d3f",
+4983 => x"80080b0b",
+4984 => x"0b0b9638",
+4985 => x"77b0160c",
+4986 => x"73b4160c",
+4987 => x"0b0b82f1",
+4988 => x"c8537280",
+4989 => x"0c863d0d",
+4990 => x"040b0b82",
+4991 => x"f0ec5273",
+4992 => x"510b0b0b",
+4993 => x"bde23f80",
+4994 => x"53800873",
+4995 => x"2e098106",
+4996 => x"0b0b0b0b",
+4997 => x"dd3877b0",
+4998 => x"160c73b4",
+4999 => x"160c0b0b",
+5000 => x"0b0bc939",
+5001 => x"0b0b82fc",
+5002 => x"8808800c",
+5003 => x"040b0b82",
+5004 => x"f1d80b80",
+5005 => x"0c047070",
+5006 => x"70755374",
+5007 => x"520b0b82",
+5008 => x"f4ec0851",
+5009 => x"0b0b0bfe",
+5010 => x"f53f5050",
+5011 => x"5004700b",
+5012 => x"0b82f4ec",
+5013 => x"08510b0b",
+5014 => x"0b0bd23f",
+5015 => x"5004ea3d",
+5016 => x"0d688c11",
+5017 => x"22700a10",
+5018 => x"0a810657",
+5019 => x"5856740b",
+5020 => x"0b0b8180",
+5021 => x"388e1622",
+5022 => x"70902b70",
+5023 => x"902c5155",
+5024 => x"58807424",
+5025 => x"0b0b0b80",
+5026 => x"c038983d",
+5027 => x"c4055373",
+5028 => x"520b0b82",
+5029 => x"f4ec0851",
+5030 => x"0b0b80c1",
+5031 => x"ac3f800b",
+5032 => x"8008240b",
+5033 => x"0b0b0b9d",
+5034 => x"387983e0",
+5035 => x"80065473",
+5036 => x"80c0802e",
+5037 => x"0b0b0b81",
+5038 => x"aa387382",
+5039 => x"80802e0b",
+5040 => x"0b0b81ac",
+5041 => x"388c1622",
+5042 => x"57769080",
+5043 => x"0754738c",
+5044 => x"17238880",
+5045 => x"520b0b82",
+5046 => x"f4ec0851",
+5047 => x"0b0b0b81",
+5048 => x"e13f8008",
+5049 => x"0b0b0b0b",
+5050 => x"9d388c16",
+5051 => x"22820754",
+5052 => x"738c1723",
+5053 => x"80c31670",
+5054 => x"770c9017",
+5055 => x"0c810b94",
+5056 => x"170c983d",
+5057 => x"0d040b0b",
+5058 => x"82f4ec08",
+5059 => x"0b0b818a",
+5060 => x"a80bbc12",
+5061 => x"0c548c16",
+5062 => x"22818007",
+5063 => x"54738c17",
+5064 => x"23800876",
+5065 => x"0c800890",
+5066 => x"170c8880",
+5067 => x"0b94170c",
+5068 => x"74802e0b",
+5069 => x"0b0b0bca",
+5070 => x"388e1622",
+5071 => x"70902b70",
+5072 => x"902c5355",
+5073 => x"580b0b80",
+5074 => x"ced33f80",
+5075 => x"08802e0b",
+5076 => x"0b0bffae",
+5077 => x"388c1622",
+5078 => x"81075473",
+5079 => x"8c172398",
+5080 => x"3d0d0481",
+5081 => x"0b8c1722",
+5082 => x"58550b0b",
+5083 => x"0bfeda39",
+5084 => x"a816080b",
+5085 => x"0b81d8ec",
+5086 => x"2e098106",
+5087 => x"0b0b0bfe",
+5088 => x"c4388c16",
+5089 => x"22888007",
+5090 => x"54738c17",
+5091 => x"2388800b",
+5092 => x"80cc170c",
+5093 => x"0b0b0bfe",
+5094 => x"b9397070",
+5095 => x"73520b0b",
+5096 => x"82f4ec08",
+5097 => x"510b0b0b",
+5098 => x"0b983f50",
+5099 => x"50047070",
+5100 => x"73520b0b",
+5101 => x"82f4ec08",
+5102 => x"510b0b0b",
+5103 => x"ecfa3f50",
+5104 => x"5004f33d",
+5105 => x"0d7f618b",
+5106 => x"1170f806",
+5107 => x"5c55555e",
+5108 => x"7296260b",
+5109 => x"0b0b0b83",
+5110 => x"38905980",
+5111 => x"7924747a",
+5112 => x"26075380",
+5113 => x"5472742e",
+5114 => x"0981060b",
+5115 => x"0b0b80d9",
+5116 => x"387d510b",
+5117 => x"0b0b93cf",
+5118 => x"3f7883f7",
+5119 => x"260b0b0b",
+5120 => x"80ce3878",
+5121 => x"832a7010",
+5122 => x"10100b0b",
+5123 => x"82fcc805",
+5124 => x"8c110859",
+5125 => x"595a7678",
+5126 => x"2e0b0b0b",
+5127 => x"84aa3884",
+5128 => x"1708fc06",
+5129 => x"568c1708",
+5130 => x"88180871",
+5131 => x"8c120c88",
+5132 => x"120c5875",
+5133 => x"17841108",
+5134 => x"81078412",
+5135 => x"0c537d51",
+5136 => x"0b0b0b93",
+5137 => x"833f8817",
+5138 => x"5473800c",
+5139 => x"8f3d0d04",
+5140 => x"78892a79",
+5141 => x"832a5b53",
+5142 => x"72802e0b",
+5143 => x"0b0b80d3",
+5144 => x"3878862a",
+5145 => x"b8055a84",
+5146 => x"73270b0b",
+5147 => x"0b80c438",
+5148 => x"80db135a",
+5149 => x"9473270b",
+5150 => x"0b0b0bb7",
+5151 => x"38788c2a",
+5152 => x"80ee055a",
+5153 => x"80d47327",
+5154 => x"0b0b0b0b",
+5155 => x"a638788f",
+5156 => x"2a80f705",
+5157 => x"5a82d473",
+5158 => x"270b0b0b",
+5159 => x"0b953878",
+5160 => x"922a80fc",
+5161 => x"055a8ad4",
+5162 => x"73270b0b",
+5163 => x"0b0b8438",
+5164 => x"80fe5a79",
+5165 => x"1010100b",
+5166 => x"0b82fcc8",
+5167 => x"058c1108",
+5168 => x"58557675",
+5169 => x"2e0b0b0b",
+5170 => x"0bad3884",
+5171 => x"1708fc06",
+5172 => x"707a3155",
+5173 => x"56738f24",
+5174 => x"0b0b0b8b",
+5175 => x"94387380",
+5176 => x"250b0b0b",
+5177 => x"febf388c",
+5178 => x"17085776",
+5179 => x"752e0981",
+5180 => x"060b0b0b",
+5181 => x"0bd53881",
+5182 => x"1a5a0b0b",
+5183 => x"82fcd808",
+5184 => x"57760b0b",
+5185 => x"82fcd02e",
+5186 => x"0b0b0b83",
+5187 => x"9a388417",
+5188 => x"08fc0670",
+5189 => x"7a315556",
+5190 => x"738f240b",
+5191 => x"0b0b82c4",
+5192 => x"380b0b82",
+5193 => x"fcd00b0b",
+5194 => x"0b82fcdc",
+5195 => x"0c0b0b82",
+5196 => x"fcd00b0b",
+5197 => x"0b82fcd8",
+5198 => x"0c738025",
+5199 => x"0b0b0bfd",
+5200 => x"f23883ff",
+5201 => x"76270b0b",
+5202 => x"0b84e238",
+5203 => x"75892a76",
+5204 => x"832a5553",
+5205 => x"72802e0b",
+5206 => x"0b0b80d3",
+5207 => x"3875862a",
+5208 => x"b8055484",
+5209 => x"73270b0b",
+5210 => x"0b80c438",
+5211 => x"80db1354",
+5212 => x"9473270b",
+5213 => x"0b0b0bb7",
+5214 => x"38758c2a",
+5215 => x"80ee0554",
+5216 => x"80d47327",
+5217 => x"0b0b0b0b",
+5218 => x"a638758f",
+5219 => x"2a80f705",
+5220 => x"5482d473",
+5221 => x"270b0b0b",
+5222 => x"0b953875",
+5223 => x"922a80fc",
+5224 => x"05548ad4",
+5225 => x"73270b0b",
+5226 => x"0b0b8438",
+5227 => x"80fe5473",
+5228 => x"1010100b",
+5229 => x"0b82fcc8",
+5230 => x"05881108",
+5231 => x"56587478",
+5232 => x"2e0b0b0b",
+5233 => x"88b83884",
+5234 => x"1508fc06",
+5235 => x"53757327",
+5236 => x"0b0b0b0b",
+5237 => x"91388815",
+5238 => x"08557478",
+5239 => x"2e098106",
+5240 => x"0b0b0b0b",
+5241 => x"e2388c15",
+5242 => x"080b0b82",
+5243 => x"fcc80b84",
+5244 => x"0508718c",
+5245 => x"1a0c7688",
+5246 => x"1a0c7888",
+5247 => x"130c788c",
+5248 => x"180c5d58",
+5249 => x"7953807a",
+5250 => x"240b0b0b",
+5251 => x"84e93872",
+5252 => x"822c8171",
+5253 => x"2b5c537a",
+5254 => x"7c260b0b",
+5255 => x"0b81c538",
+5256 => x"7b7b0653",
+5257 => x"720b0b0b",
+5258 => x"83d03879",
+5259 => x"fc068405",
+5260 => x"5a7a1070",
+5261 => x"7d06545b",
+5262 => x"720b0b0b",
+5263 => x"83bc3884",
+5264 => x"1a5a0b0b",
+5265 => x"0b0bea39",
+5266 => x"88178c11",
+5267 => x"08585876",
+5268 => x"782e0981",
+5269 => x"060b0b0b",
+5270 => x"fbc53882",
+5271 => x"1a5a0b0b",
+5272 => x"0bfd9739",
+5273 => x"78177981",
+5274 => x"0784190c",
+5275 => x"700b0b82",
+5276 => x"fcdc0c70",
+5277 => x"0b0b82fc",
+5278 => x"d80c0b0b",
+5279 => x"82fcd00b",
+5280 => x"8c120c8c",
+5281 => x"11088812",
+5282 => x"0c748107",
+5283 => x"84120c74",
+5284 => x"1175710c",
+5285 => x"51537d51",
+5286 => x"0b0b0b8e",
+5287 => x"ab3f8817",
+5288 => x"540b0b0b",
+5289 => x"fba3390b",
+5290 => x"0b82fcc8",
+5291 => x"0b840508",
+5292 => x"7a545c79",
+5293 => x"80250b0b",
+5294 => x"0bfed438",
+5295 => x"0b0b0b83",
+5296 => x"b6397a09",
+5297 => x"7c06700b",
+5298 => x"0b82fcc8",
+5299 => x"0b84050c",
+5300 => x"5c7a105b",
+5301 => x"7a7c260b",
+5302 => x"0b0b0b88",
+5303 => x"387a0b0b",
+5304 => x"0b86f738",
+5305 => x"0b0b82fc",
+5306 => x"c80b8805",
+5307 => x"08708412",
+5308 => x"08fc0670",
+5309 => x"7c317c72",
+5310 => x"268f7225",
+5311 => x"0757575c",
+5312 => x"5d557280",
+5313 => x"2e0b0b0b",
+5314 => x"80f73879",
+5315 => x"7a160b0b",
+5316 => x"82fcc008",
+5317 => x"1b90115a",
+5318 => x"55575b0b",
+5319 => x"0b82fcbc",
+5320 => x"08ff2e0b",
+5321 => x"0b0b0b88",
+5322 => x"38a08f13",
+5323 => x"e0800657",
+5324 => x"76527d51",
+5325 => x"0b0b0bb0",
+5326 => x"893f8008",
+5327 => x"548008ff",
+5328 => x"2e0b0b0b",
+5329 => x"0b983880",
+5330 => x"0876270b",
+5331 => x"0b0b82e1",
+5332 => x"38740b0b",
+5333 => x"82fcc82e",
+5334 => x"0b0b0b82",
+5335 => x"d4380b0b",
+5336 => x"82fcc80b",
+5337 => x"88050855",
+5338 => x"841508fc",
+5339 => x"06707a31",
+5340 => x"7a72268f",
+5341 => x"72250752",
+5342 => x"5553720b",
+5343 => x"0b0b84ee",
+5344 => x"38747981",
+5345 => x"0784170c",
+5346 => x"7916700b",
+5347 => x"0b82fcc8",
+5348 => x"0b88050c",
+5349 => x"75810784",
+5350 => x"120c547e",
+5351 => x"52570b0b",
+5352 => x"0b8ca53f",
+5353 => x"8817540b",
+5354 => x"0b0bf99d",
+5355 => x"3975832a",
+5356 => x"70545480",
+5357 => x"74240b0b",
+5358 => x"0b81c538",
+5359 => x"72822c81",
+5360 => x"712b0b0b",
+5361 => x"82fccc08",
+5362 => x"07700b0b",
+5363 => x"82fcc80b",
+5364 => x"84050c75",
+5365 => x"1010100b",
+5366 => x"0b82fcc8",
+5367 => x"05881108",
+5368 => x"585a5d53",
+5369 => x"778c180c",
+5370 => x"7488180c",
+5371 => x"7688190c",
+5372 => x"768c160c",
+5373 => x"0b0b0bfc",
+5374 => x"8b39797a",
+5375 => x"1010100b",
+5376 => x"0b82fcc8",
+5377 => x"05705759",
+5378 => x"5d8c1508",
+5379 => x"5776752e",
+5380 => x"0b0b0b0b",
+5381 => x"ad388417",
+5382 => x"08fc0670",
+5383 => x"7a315556",
+5384 => x"738f240b",
+5385 => x"0b0b84d5",
+5386 => x"38738025",
+5387 => x"0b0b0b85",
+5388 => x"92388c17",
+5389 => x"08577675",
+5390 => x"2e098106",
+5391 => x"0b0b0b0b",
+5392 => x"d5388815",
+5393 => x"811b7083",
+5394 => x"06555b55",
+5395 => x"720b0b0b",
+5396 => x"ffb7387c",
+5397 => x"83065372",
+5398 => x"802e0b0b",
+5399 => x"0bfce338",
+5400 => x"ff1df819",
+5401 => x"595d8818",
+5402 => x"08782e0b",
+5403 => x"0b0b0be3",
+5404 => x"380b0b0b",
+5405 => x"fcdb3983",
+5406 => x"1a530b0b",
+5407 => x"0bfb9039",
+5408 => x"83147082",
+5409 => x"2c81712b",
+5410 => x"0b0b82fc",
+5411 => x"cc080770",
+5412 => x"0b0b82fc",
+5413 => x"c80b8405",
+5414 => x"0c761010",
+5415 => x"100b0b82",
+5416 => x"fcc80588",
+5417 => x"1108595b",
+5418 => x"5e51530b",
+5419 => x"0b0bfeb4",
+5420 => x"390b0b82",
+5421 => x"fc8c0817",
+5422 => x"58800876",
+5423 => x"2e0b0b0b",
+5424 => x"81b2380b",
+5425 => x"0b82fcbc",
+5426 => x"08ff2e0b",
+5427 => x"0b0b84e8",
+5428 => x"38737631",
+5429 => x"180b0b82",
+5430 => x"fc8c0c73",
+5431 => x"87067057",
+5432 => x"5372802e",
+5433 => x"0b0b0b0b",
+5434 => x"88388873",
+5435 => x"31701555",
+5436 => x"5676149f",
+5437 => x"ff06a080",
+5438 => x"71311770",
+5439 => x"547f5357",
+5440 => x"530b0b0b",
+5441 => x"acbc3f80",
+5442 => x"08538008",
+5443 => x"ff2e0b0b",
+5444 => x"0b81d138",
+5445 => x"0b0b82fc",
+5446 => x"8c081670",
+5447 => x"0b0b82fc",
+5448 => x"8c0c7475",
+5449 => x"0b0b82fc",
+5450 => x"c80b8805",
+5451 => x"0c747631",
+5452 => x"18708107",
+5453 => x"51555658",
+5454 => x"7b0b0b82",
+5455 => x"fcc82e0b",
+5456 => x"0b0b8488",
+5457 => x"38798f26",
+5458 => x"0b0b0b83",
+5459 => x"a038810b",
+5460 => x"84150c84",
+5461 => x"1508fc06",
+5462 => x"707a317a",
+5463 => x"72268f72",
+5464 => x"25075255",
+5465 => x"5372802e",
+5466 => x"0b0b0bfc",
+5467 => x"94380b0b",
+5468 => x"0b80fb39",
+5469 => x"80089fff",
+5470 => x"0653720b",
+5471 => x"0b0bfec3",
+5472 => x"38770b0b",
+5473 => x"82fc8c0c",
+5474 => x"0b0b82fc",
+5475 => x"c80b8805",
+5476 => x"087b1881",
+5477 => x"0784120c",
+5478 => x"550b0b82",
+5479 => x"fcb80878",
+5480 => x"270b0b0b",
+5481 => x"0b883877",
+5482 => x"0b0b82fc",
+5483 => x"b80c0b0b",
+5484 => x"82fcb408",
+5485 => x"78270b0b",
+5486 => x"0bfbad38",
+5487 => x"770b0b82",
+5488 => x"fcb40c84",
+5489 => x"1508fc06",
+5490 => x"707a317a",
+5491 => x"72268f72",
+5492 => x"25075255",
+5493 => x"5372802e",
+5494 => x"0b0b0bfb",
+5495 => x"a4380b0b",
+5496 => x"0b0b8b39",
+5497 => x"80745456",
+5498 => x"0b0b0bfe",
+5499 => x"a7397d51",
+5500 => x"0b0b0b87",
+5501 => x"d33f800b",
+5502 => x"800c8f3d",
+5503 => x"0d047353",
+5504 => x"8074240b",
+5505 => x"0b0b0bb0",
+5506 => x"3872822c",
+5507 => x"81712b0b",
+5508 => x"0b82fccc",
+5509 => x"0807700b",
+5510 => x"0b82fcc8",
+5511 => x"0b84050c",
+5512 => x"5d53778c",
+5513 => x"180c7488",
+5514 => x"180c7688",
+5515 => x"190c768c",
+5516 => x"160c0b0b",
+5517 => x"0bf7cd39",
+5518 => x"83147082",
+5519 => x"2c81712b",
+5520 => x"0b0b82fc",
+5521 => x"cc080770",
+5522 => x"0b0b82fc",
+5523 => x"c80b8405",
+5524 => x"0c5e5153",
+5525 => x"0b0b0b0b",
+5526 => x"c9397b7b",
+5527 => x"0653720b",
+5528 => x"0b0bfb96",
+5529 => x"38841a7b",
+5530 => x"105c5a0b",
+5531 => x"0b0b0bea",
+5532 => x"39ff1a81",
+5533 => x"11515a0b",
+5534 => x"0b0bf4fe",
+5535 => x"39781779",
+5536 => x"81078419",
+5537 => x"0c8c1808",
+5538 => x"88190871",
+5539 => x"8c120c88",
+5540 => x"120c5970",
+5541 => x"0b0b82fc",
+5542 => x"dc0c700b",
+5543 => x"0b82fcd8",
+5544 => x"0c0b0b82",
+5545 => x"fcd00b8c",
+5546 => x"120c8c11",
+5547 => x"0888120c",
+5548 => x"74810784",
+5549 => x"120c7411",
+5550 => x"75710c51",
+5551 => x"530b0b0b",
+5552 => x"f7d43975",
+5553 => x"17841108",
+5554 => x"81078412",
+5555 => x"0c538c17",
+5556 => x"08881808",
+5557 => x"718c120c",
+5558 => x"88120c58",
+5559 => x"7d510b0b",
+5560 => x"0b85e53f",
+5561 => x"8817540b",
+5562 => x"0b0bf2dd",
+5563 => x"39728415",
+5564 => x"0cf41af8",
+5565 => x"0670841e",
+5566 => x"08810607",
+5567 => x"841e0c70",
+5568 => x"1d545b85",
+5569 => x"0b84140c",
+5570 => x"850b8814",
+5571 => x"0c8f7b27",
+5572 => x"0b0b0bfd",
+5573 => x"8438881c",
+5574 => x"527d510b",
+5575 => x"0b0bde98",
+5576 => x"3f0b0b82",
+5577 => x"fcc80b88",
+5578 => x"05080b0b",
+5579 => x"82fc8c08",
+5580 => x"59550b0b",
+5581 => x"0bfce239",
+5582 => x"770b0b82",
+5583 => x"fc8c0c73",
+5584 => x"0b0b82fc",
+5585 => x"bc0c0b0b",
+5586 => x"0bfb9039",
+5587 => x"7284150c",
+5588 => x"0b0b0bfc",
+5589 => x"c439fa3d",
+5590 => x"0d7a7902",
+5591 => x"8805a705",
+5592 => x"33565253",
+5593 => x"8373270b",
+5594 => x"0b0b0b8e",
+5595 => x"38708306",
+5596 => x"5271802e",
+5597 => x"0b0b0b0b",
+5598 => x"b438ff13",
+5599 => x"5372ff2e",
+5600 => x"0b0b0b0b",
+5601 => x"9f387033",
+5602 => x"5273722e",
+5603 => x"0b0b0b0b",
+5604 => x"95388111",
+5605 => x"ff145451",
+5606 => x"72ff2e09",
+5607 => x"81060b0b",
+5608 => x"0b0be338",
+5609 => x"80517080",
+5610 => x"0c883d0d",
+5611 => x"04707257",
+5612 => x"55835175",
+5613 => x"82802914",
+5614 => x"ff125256",
+5615 => x"7080250b",
+5616 => x"0b0b0bef",
+5617 => x"38837327",
+5618 => x"0b0b0b80",
+5619 => x"ce387408",
+5620 => x"76327009",
+5621 => x"f7fbfdff",
+5622 => x"120670f8",
+5623 => x"84828180",
+5624 => x"06515151",
+5625 => x"70802e0b",
+5626 => x"0b0b0ba0",
+5627 => x"38745180",
+5628 => x"52703357",
+5629 => x"73772e0b",
+5630 => x"0b0bffaa",
+5631 => x"38811181",
+5632 => x"13535183",
+5633 => x"72270b0b",
+5634 => x"0b0be638",
+5635 => x"fc138416",
+5636 => x"56537283",
+5637 => x"260b0b0b",
+5638 => x"ffb43874",
+5639 => x"510b0b0b",
+5640 => x"fed839fa",
+5641 => x"3d0d787a",
+5642 => x"7c727272",
+5643 => x"57575759",
+5644 => x"56567476",
+5645 => x"270b0b0b",
+5646 => x"0bbe3876",
+5647 => x"15517571",
+5648 => x"270b0b0b",
+5649 => x"0bb23870",
+5650 => x"7717ff14",
+5651 => x"54555371",
+5652 => x"ff2e0b0b",
+5653 => x"0b0b9a38",
+5654 => x"ff14ff14",
+5655 => x"54547233",
+5656 => x"7434ff12",
+5657 => x"5271ff2e",
+5658 => x"0981060b",
+5659 => x"0b0b0be8",
+5660 => x"3875800c",
+5661 => x"883d0d04",
+5662 => x"768f260b",
+5663 => x"0b0b0b9f",
+5664 => x"38ff1252",
+5665 => x"71ff2e0b",
+5666 => x"0b0b0be5",
+5667 => x"38727081",
+5668 => x"05543374",
+5669 => x"70810556",
+5670 => x"340b0b0b",
+5671 => x"0be33974",
+5672 => x"76078306",
+5673 => x"51700b0b",
+5674 => x"0b0bd638",
+5675 => x"75755451",
+5676 => x"72708405",
+5677 => x"54087170",
+5678 => x"8405530c",
+5679 => x"72708405",
+5680 => x"54087170",
+5681 => x"8405530c",
+5682 => x"72708405",
+5683 => x"54087170",
+5684 => x"8405530c",
+5685 => x"72708405",
+5686 => x"54087170",
+5687 => x"8405530c",
+5688 => x"f0125271",
+5689 => x"8f260b0b",
+5690 => x"0b0bc538",
+5691 => x"8372270b",
+5692 => x"0b0b0b99",
+5693 => x"38727084",
+5694 => x"05540871",
+5695 => x"70840553",
+5696 => x"0cfc1252",
+5697 => x"7183260b",
+5698 => x"0b0b0be9",
+5699 => x"3870540b",
+5700 => x"0b0bfeed",
+5701 => x"39fc3d0d",
+5702 => x"76797102",
+5703 => x"8c059f05",
+5704 => x"33575553",
+5705 => x"55837227",
+5706 => x"0b0b0b0b",
+5707 => x"8e387483",
+5708 => x"06517080",
+5709 => x"2e0b0b0b",
+5710 => x"0baa38ff",
+5711 => x"125271ff",
+5712 => x"2e0b0b0b",
+5713 => x"0b973873",
+5714 => x"73708105",
+5715 => x"5534ff12",
+5716 => x"5271ff2e",
+5717 => x"0981060b",
+5718 => x"0b0b0beb",
+5719 => x"3874800c",
+5720 => x"863d0d04",
+5721 => x"7474882b",
+5722 => x"75077071",
+5723 => x"902b0751",
+5724 => x"54518f72",
+5725 => x"270b0b0b",
+5726 => x"0ba93872",
+5727 => x"71708405",
+5728 => x"530c7271",
+5729 => x"70840553",
+5730 => x"0c727170",
+5731 => x"8405530c",
+5732 => x"72717084",
+5733 => x"05530cf0",
+5734 => x"1252718f",
+5735 => x"260b0b0b",
+5736 => x"0bd93883",
+5737 => x"72270b0b",
+5738 => x"0b0b9438",
+5739 => x"72717084",
+5740 => x"05530cfc",
+5741 => x"12527183",
+5742 => x"260b0b0b",
+5743 => x"0bee3870",
+5744 => x"530b0b0b",
+5745 => x"fef53904",
+5746 => x"04f93d0d",
+5747 => x"797b80cc",
+5748 => x"12085658",
+5749 => x"5673802e",
+5750 => x"0b0b0b0b",
+5751 => x"a9387610",
+5752 => x"10147008",
+5753 => x"55557380",
+5754 => x"2e0b0b0b",
+5755 => x"80c03873",
+5756 => x"08750c80",
+5757 => x"0b90150c",
+5758 => x"800b8c15",
+5759 => x"0c735574",
+5760 => x"800c893d",
+5761 => x"0d049053",
+5762 => x"84527551",
+5763 => x"0b0b0ba8",
+5764 => x"c63f8008",
+5765 => x"80cc170c",
+5766 => x"80085580",
+5767 => x"08802e0b",
+5768 => x"0b0b0bdb",
+5769 => x"38800854",
+5770 => x"0b0b0bff",
+5771 => x"b1398177",
+5772 => x"2b701010",
+5773 => x"94055458",
+5774 => x"81527551",
+5775 => x"0b0b0ba8",
+5776 => x"963f8008",
+5777 => x"80085654",
+5778 => x"8008802e",
+5779 => x"0b0b0bff",
+5780 => x"ae387680",
+5781 => x"0884050c",
+5782 => x"77800888",
+5783 => x"050c800b",
+5784 => x"90150c80",
+5785 => x"0b8c150c",
+5786 => x"73550b0b",
+5787 => x"0bff9039",
+5788 => x"70707452",
+5789 => x"71802e0b",
+5790 => x"0b0b0b95",
+5791 => x"38738413",
+5792 => x"08101080",
+5793 => x"cc120805",
+5794 => x"7008740c",
+5795 => x"73710c51",
+5796 => x"51505004",
+5797 => x"f53d0d7d",
+5798 => x"7f616390",
+5799 => x"13089414",
+5800 => x"5b5d5b5c",
+5801 => x"5c5c8057",
+5802 => x"8216227a",
+5803 => x"71291977",
+5804 => x"227c7129",
+5805 => x"72902a05",
+5806 => x"70902a73",
+5807 => x"83ffff06",
+5808 => x"72848080",
+5809 => x"29057b70",
+5810 => x"84055d0c",
+5811 => x"811c5c52",
+5812 => x"535a5555",
+5813 => x"7877240b",
+5814 => x"0b0b0bcc",
+5815 => x"3877802e",
+5816 => x"0b0b0b0b",
+5817 => x"9a387888",
+5818 => x"1c08250b",
+5819 => x"0b0b0b96",
+5820 => x"38781010",
+5821 => x"1b789412",
+5822 => x"0c548119",
+5823 => x"901c0c7a",
+5824 => x"800c8d3d",
+5825 => x"0d04841b",
+5826 => x"08810552",
+5827 => x"7b510b0b",
+5828 => x"0bfdb63f",
+5829 => x"8008901c",
+5830 => x"08101088",
+5831 => x"05548c1c",
+5832 => x"5380088c",
+5833 => x"0552540b",
+5834 => x"0bfedcdf",
+5835 => x"3f7a527b",
+5836 => x"510b0b0b",
+5837 => x"feba3f73",
+5838 => x"79101011",
+5839 => x"7994120c",
+5840 => x"55811a90",
+5841 => x"120c5b0b",
+5842 => x"0b0bffb3",
+5843 => x"39f63d0d",
+5844 => x"7c7e6062",
+5845 => x"890b8812",
+5846 => x"355b5e5c",
+5847 => x"59598056",
+5848 => x"81557477",
+5849 => x"250b0b0b",
+5850 => x"0b903874",
+5851 => x"10811757",
+5852 => x"55767524",
+5853 => x"0b0b0b0b",
+5854 => x"f2387552",
+5855 => x"78510b0b",
+5856 => x"0bfcc63f",
+5857 => x"80086180",
+5858 => x"0894050c",
+5859 => x"56810b80",
+5860 => x"0890050c",
+5861 => x"8957767a",
+5862 => x"250b0b0b",
+5863 => x"80e13876",
+5864 => x"18587770",
+5865 => x"81055933",
+5866 => x"d005548a",
+5867 => x"53755278",
+5868 => x"510b0b0b",
+5869 => x"fdde3f80",
+5870 => x"08811858",
+5871 => x"56797724",
+5872 => x"0b0b0b0b",
+5873 => x"dd388118",
+5874 => x"58767b25",
+5875 => x"0b0b0b0b",
+5876 => x"a7387a77",
+5877 => x"31577770",
+5878 => x"81055933",
+5879 => x"d005548a",
+5880 => x"53755278",
+5881 => x"510b0b0b",
+5882 => x"fdaa3f80",
+5883 => x"08ff1858",
+5884 => x"56760b0b",
+5885 => x"0b0bdf38",
+5886 => x"75800c8c",
+5887 => x"3d0d048a",
+5888 => x"18580b0b",
+5889 => x"0b0bc239",
+5890 => x"70707074",
+5891 => x"528072fc",
+5892 => x"80800652",
+5893 => x"5370732e",
+5894 => x"0981060b",
+5895 => x"0b0b0b87",
+5896 => x"38907271",
+5897 => x"2b535371",
+5898 => x"81ff0a06",
+5899 => x"51700b0b",
+5900 => x"0b0b8838",
+5901 => x"88137288",
+5902 => x"2b535371",
+5903 => x"8f0a0651",
+5904 => x"700b0b0b",
+5905 => x"0b883884",
+5906 => x"1372842b",
+5907 => x"53537183",
+5908 => x"0a065170",
+5909 => x"0b0b0b0b",
+5910 => x"88388213",
+5911 => x"72822b53",
+5912 => x"53807224",
+5913 => x"0b0b0b0b",
+5914 => x"97388113",
+5915 => x"729e2a70",
+5916 => x"81065152",
+5917 => x"53a05270",
+5918 => x"802e0b0b",
+5919 => x"0b0b8338",
+5920 => x"72527180",
+5921 => x"0c505050",
+5922 => x"04fc3d0d",
+5923 => x"76700870",
+5924 => x"87065353",
+5925 => x"5570802e",
+5926 => x"0b0b0b0b",
+5927 => x"b1387181",
+5928 => x"06518053",
+5929 => x"70732e09",
+5930 => x"81060b0b",
+5931 => x"0b0b9838",
+5932 => x"710a100a",
+5933 => x"70810652",
+5934 => x"5370802e",
+5935 => x"0b0b0b81",
+5936 => x"89387275",
+5937 => x"0c815372",
+5938 => x"800c863d",
+5939 => x"0d047072",
+5940 => x"83ffff06",
+5941 => x"52547080",
+5942 => x"2e0b0b0b",
+5943 => x"80e03871",
+5944 => x"81ff0651",
+5945 => x"700b0b0b",
+5946 => x"0b883888",
+5947 => x"1472882a",
+5948 => x"5354718f",
+5949 => x"0651700b",
+5950 => x"0b0b0b88",
+5951 => x"38841472",
+5952 => x"842a5354",
+5953 => x"71830651",
+5954 => x"700b0b0b",
+5955 => x"0b883882",
+5956 => x"1472822a",
+5957 => x"53547181",
+5958 => x"0651700b",
+5959 => x"0b0b0b94",
+5960 => x"38811472",
+5961 => x"0a100a53",
+5962 => x"54a05371",
+5963 => x"802e0b0b",
+5964 => x"0bff9438",
+5965 => x"71750c73",
+5966 => x"800c863d",
+5967 => x"0d049072",
+5968 => x"712a5354",
+5969 => x"0b0b0bff",
+5970 => x"96397182",
+5971 => x"2a750c82",
+5972 => x"0b800c86",
+5973 => x"3d0d0470",
+5974 => x"70815273",
+5975 => x"510b0b0b",
+5976 => x"f8e73f74",
+5977 => x"80089405",
+5978 => x"0c810b80",
+5979 => x"0890050c",
+5980 => x"505004ee",
+5981 => x"3d0d6567",
+5982 => x"90120890",
+5983 => x"12085856",
+5984 => x"57537375",
+5985 => x"250b0b0b",
+5986 => x"0b8d3872",
+5987 => x"76717790",
+5988 => x"14085957",
+5989 => x"58544274",
+5990 => x"14708815",
+5991 => x"08248415",
+5992 => x"08055365",
+5993 => x"525e0b0b",
+5994 => x"0bf89e3f",
+5995 => x"80088008",
+5996 => x"94057060",
+5997 => x"822b7211",
+5998 => x"43465941",
+5999 => x"427f7f27",
+6000 => x"0b0b0b0b",
+6001 => x"91388077",
+6002 => x"70840559",
+6003 => x"0c7e7726",
+6004 => x"0b0b0b0b",
+6005 => x"f1389413",
+6006 => x"74101011",
+6007 => x"94187710",
+6008 => x"10116341",
+6009 => x"445d5d5f",
+6010 => x"7a61270b",
+6011 => x"0b0b81c9",
+6012 => x"387a0870",
+6013 => x"83ffff06",
+6014 => x"59537780",
+6015 => x"2e0b0b0b",
+6016 => x"80cb387e",
+6017 => x"7d575780",
+6018 => x"5a767084",
+6019 => x"05580870",
+6020 => x"83ffff06",
+6021 => x"82182271",
+6022 => x"7b29057c",
+6023 => x"1173902a",
+6024 => x"7c297a22",
+6025 => x"5e7d0571",
+6026 => x"902a0570",
+6027 => x"902a5f59",
+6028 => x"51515454",
+6029 => x"74762372",
+6030 => x"82172384",
+6031 => x"16567b77",
+6032 => x"260b0b0b",
+6033 => x"0bc33879",
+6034 => x"760c7a08",
+6035 => x"5372902a",
+6036 => x"5877802e",
+6037 => x"0b0b0b80",
+6038 => x"d1387e7d",
+6039 => x"5757807d",
+6040 => x"08705b56",
+6041 => x"5a767084",
+6042 => x"05580870",
+6043 => x"83ffff06",
+6044 => x"707a297b",
+6045 => x"902a057c",
+6046 => x"11515154",
+6047 => x"54727623",
+6048 => x"74821723",
+6049 => x"84167490",
+6050 => x"2a792971",
+6051 => x"08821322",
+6052 => x"5d5b7b05",
+6053 => x"74902a05",
+6054 => x"70902a5c",
+6055 => x"56567b77",
+6056 => x"260b0b0b",
+6057 => x"ffbf3874",
+6058 => x"760c841b",
+6059 => x"841e5e5b",
+6060 => x"607b260b",
+6061 => x"0b0bfeb9",
+6062 => x"38626005",
+6063 => x"56807e25",
+6064 => x"0b0b0b0b",
+6065 => x"9838fc16",
+6066 => x"5675080b",
+6067 => x"0b0b0b8d",
+6068 => x"38ff1e5e",
+6069 => x"7d80240b",
+6070 => x"0b0b0bea",
+6071 => x"387d6290",
+6072 => x"050c6180",
+6073 => x"0c943d0d",
+6074 => x"04f73d0d",
+6075 => x"7b7d7f70",
+6076 => x"83065858",
+6077 => x"5a5a740b",
+6078 => x"0b0b8181",
+6079 => x"3875822c",
+6080 => x"5675802e",
+6081 => x"0b0b0b80",
+6082 => x"cc3880c8",
+6083 => x"1a087056",
+6084 => x"5776802e",
+6085 => x"0b0b0b81",
+6086 => x"a3387581",
+6087 => x"0655740b",
+6088 => x"0b0b0bb8",
+6089 => x"3875812c",
+6090 => x"5675802e",
+6091 => x"0b0b0b0b",
+6092 => x"a4387608",
+6093 => x"70595574",
+6094 => x"802e0b0b",
+6095 => x"0b80e038",
+6096 => x"74577581",
+6097 => x"06557480",
+6098 => x"2e0b0b0b",
+6099 => x"0bd7380b",
+6100 => x"0b0b0b88",
+6101 => x"3978800c",
+6102 => x"8b3d0d04",
+6103 => x"76537852",
+6104 => x"79510b0b",
+6105 => x"0bfc8c3f",
+6106 => x"80087953",
+6107 => x"7a52550b",
+6108 => x"0b0bf5fc",
+6109 => x"3f74590b",
+6110 => x"0b0bffa9",
+6111 => x"39805474",
+6112 => x"10100b0b",
+6113 => x"82f49c05",
+6114 => x"70085455",
+6115 => x"78527951",
+6116 => x"0b0b0bf5",
+6117 => x"ff3f8008",
+6118 => x"590b0b0b",
+6119 => x"fedf3976",
+6120 => x"53765279",
+6121 => x"510b0b0b",
+6122 => x"fbc93f80",
+6123 => x"08770c80",
+6124 => x"08788008",
+6125 => x"0c570b0b",
+6126 => x"0bff8739",
+6127 => x"84f15279",
+6128 => x"510b0b0b",
+6129 => x"fb913f80",
+6130 => x"0880c81b",
+6131 => x"0c800875",
+6132 => x"80080c76",
+6133 => x"81065657",
+6134 => x"74802e0b",
+6135 => x"0b0bfec5",
+6136 => x"380b0b0b",
+6137 => x"fef639f5",
+6138 => x"3d0d7d7f",
+6139 => x"6170852c",
+6140 => x"84130890",
+6141 => x"14081281",
+6142 => x"05881508",
+6143 => x"595e5959",
+6144 => x"5a5c5c72",
+6145 => x"79250b0b",
+6146 => x"0b0b9038",
+6147 => x"81157310",
+6148 => x"54557873",
+6149 => x"240b0b0b",
+6150 => x"0bf23874",
+6151 => x"527b510b",
+6152 => x"0b0bf3a5",
+6153 => x"3f800880",
+6154 => x"08940555",
+6155 => x"5a807625",
+6156 => x"0b0b0b0b",
+6157 => x"94387553",
+6158 => x"80747084",
+6159 => x"05560cff",
+6160 => x"1353720b",
+6161 => x"0b0b0bf0",
+6162 => x"38941b90",
+6163 => x"1c081010",
+6164 => x"11799f06",
+6165 => x"5a585377",
+6166 => x"802e0b0b",
+6167 => x"0b80ca38",
+6168 => x"a0783155",
+6169 => x"80567208",
+6170 => x"782b7607",
+6171 => x"74708405",
+6172 => x"560c7270",
+6173 => x"84055408",
+6174 => x"752a5676",
+6175 => x"73260b0b",
+6176 => x"0b0be338",
+6177 => x"75740c75",
+6178 => x"802e0b0b",
+6179 => x"0b0b8438",
+6180 => x"811959ff",
+6181 => x"19901b0c",
+6182 => x"7a527b51",
+6183 => x"0b0b0bf3",
+6184 => x"cf3f7980",
+6185 => x"0c8d3d0d",
+6186 => x"04727084",
+6187 => x"05540874",
+6188 => x"70840556",
+6189 => x"0c727727",
+6190 => x"0b0b0b0b",
+6191 => x"d6387270",
+6192 => x"84055408",
+6193 => x"74708405",
+6194 => x"560c7673",
+6195 => x"260b0b0b",
+6196 => x"0bd7380b",
+6197 => x"0b0bffbb",
+6198 => x"39fb3d0d",
+6199 => x"77799011",
+6200 => x"08901308",
+6201 => x"71317056",
+6202 => x"54555754",
+6203 => x"700b0b0b",
+6204 => x"0bb33894",
+6205 => x"1473822b",
+6206 => x"71117119",
+6207 => x"94055254",
+6208 => x"5255fc12",
+6209 => x"fc127108",
+6210 => x"71085656",
+6211 => x"52527373",
+6212 => x"2e098106",
+6213 => x"0b0b0b0b",
+6214 => x"93387175",
+6215 => x"260b0b0b",
+6216 => x"0be03880",
+6217 => x"5271800c",
+6218 => x"873d0d04",
+6219 => x"ff517274",
+6220 => x"260b0b0b",
+6221 => x"0b833881",
+6222 => x"5170800c",
+6223 => x"873d0d04",
+6224 => x"f33d0d7f",
+6225 => x"61637055",
+6226 => x"71545754",
+6227 => x"560b0b0b",
+6228 => x"ff873f80",
+6229 => x"08548008",
+6230 => x"802e0b0b",
+6231 => x"0b81e038",
+6232 => x"80547380",
+6233 => x"08240b0b",
+6234 => x"0b81f638",
+6235 => x"84130852",
+6236 => x"75510b0b",
+6237 => x"0bf0d23f",
+6238 => x"80087480",
+6239 => x"088c050c",
+6240 => x"90140894",
+6241 => x"15711010",
+6242 => x"11941990",
+6243 => x"1a081010",
+6244 => x"11800894",
+6245 => x"055d415d",
+6246 => x"415a5c5d",
+6247 => x"805a7770",
+6248 => x"84055908",
+6249 => x"7083ffff",
+6250 => x"067a7084",
+6251 => x"055c0870",
+6252 => x"83ffff06",
+6253 => x"7271311e",
+6254 => x"74902a73",
+6255 => x"902a3171",
+6256 => x"902c1170",
+6257 => x"902c4151",
+6258 => x"55515657",
+6259 => x"57547377",
+6260 => x"23728218",
+6261 => x"23841757",
+6262 => x"7b79260b",
+6263 => x"0b0bffbe",
+6264 => x"38777e27",
+6265 => x"0b0b0b0b",
+6266 => x"b0387770",
+6267 => x"84055908",
+6268 => x"7083ffff",
+6269 => x"067b1170",
+6270 => x"902c7390",
+6271 => x"2a057090",
+6272 => x"2c5e5351",
+6273 => x"54547377",
+6274 => x"23728218",
+6275 => x"23841757",
+6276 => x"7d78260b",
+6277 => x"0b0b0bd2",
+6278 => x"38fc1757",
+6279 => x"76080b0b",
+6280 => x"0b0b9138",
+6281 => x"ff1bfc18",
+6282 => x"585b7608",
+6283 => x"802e0b0b",
+6284 => x"0b0bf138",
+6285 => x"7a901e0c",
+6286 => x"7c800c8f",
+6287 => x"3d0d0480",
+6288 => x"08527551",
+6289 => x"0b0b0bef",
+6290 => x"803f8008",
+6291 => x"5d810b80",
+6292 => x"0890050c",
+6293 => x"73800894",
+6294 => x"050c7c80",
+6295 => x"0c8f3d0d",
+6296 => x"04727554",
+6297 => x"55810b84",
+6298 => x"14085376",
+6299 => x"52540b0b",
+6300 => x"0beed63f",
+6301 => x"80087480",
+6302 => x"088c050c",
+6303 => x"90140894",
+6304 => x"15711010",
+6305 => x"11941990",
+6306 => x"1a081010",
+6307 => x"11800894",
+6308 => x"055d415d",
+6309 => x"415a5c5d",
+6310 => x"805a0b0b",
+6311 => x"0bfdff39",
+6312 => x"fa3d0d78",
+6313 => x"7a7c5457",
+6314 => x"7258769f",
+6315 => x"fe0a0686",
+6316 => x"bf0a0553",
+6317 => x"53807225",
+6318 => x"0b0b0b0b",
+6319 => x"95387154",
+6320 => x"80557375",
+6321 => x"53730c71",
+6322 => x"84140c72",
+6323 => x"800c883d",
+6324 => x"0d047130",
+6325 => x"70942c53",
+6326 => x"51937225",
+6327 => x"0b0b0b0b",
+6328 => x"ab388054",
+6329 => x"ec129f71",
+6330 => x"3181712b",
+6331 => x"5152529e",
+6332 => x"72250b0b",
+6333 => x"0b0b8338",
+6334 => x"81517055",
+6335 => x"73755373",
+6336 => x"0c718414",
+6337 => x"0c72800c",
+6338 => x"883d0d04",
+6339 => x"a0808072",
+6340 => x"2c548055",
+6341 => x"0b0b0bff",
+6342 => x"a939f63d",
+6343 => x"0d7c7e94",
+6344 => x"11901208",
+6345 => x"101011fc",
+6346 => x"11700870",
+6347 => x"575a5157",
+6348 => x"5853590b",
+6349 => x"0b0bf1d0",
+6350 => x"3f80087f",
+6351 => x"a00b8008",
+6352 => x"31710c53",
+6353 => x"538a0b80",
+6354 => x"08250b0b",
+6355 => x"0b80f738",
+6356 => x"80577376",
+6357 => x"260b0b0b",
+6358 => x"80c438f5",
+6359 => x"13537280",
+6360 => x"2e0b0b0b",
+6361 => x"80c838a0",
+6362 => x"73317574",
+6363 => x"2b78722a",
+6364 => x"079ffc0a",
+6365 => x"075b5880",
+6366 => x"55757427",
+6367 => x"0b0b0b0b",
+6368 => x"8538fc14",
+6369 => x"08557673",
+6370 => x"2b75792a",
+6371 => x"075b797b",
+6372 => x"54790c72",
+6373 => x"841a0c78",
+6374 => x"800c8c3d",
+6375 => x"0d04fc14",
+6376 => x"7008f515",
+6377 => x"55585472",
+6378 => x"0b0b0bff",
+6379 => x"ba38749f",
+6380 => x"fc0a075a",
+6381 => x"765b797b",
+6382 => x"54790c72",
+6383 => x"841a0c78",
+6384 => x"800c8c3d",
+6385 => x"0d048b0b",
+6386 => x"80083175",
+6387 => x"712a9ffc",
+6388 => x"0a075b57",
+6389 => x"80587574",
+6390 => x"270b0b0b",
+6391 => x"0b8538fc",
+6392 => x"14085895",
+6393 => x"1375712b",
+6394 => x"79792a07",
+6395 => x"5c52797b",
+6396 => x"54790c72",
+6397 => x"841a0c78",
+6398 => x"800c8c3d",
+6399 => x"0d04f33d",
+6400 => x"0d626462",
+6401 => x"64575f75",
+6402 => x"405b5981",
+6403 => x"527f510b",
+6404 => x"0b0bebb5",
+6405 => x"3f800880",
+6406 => x"0894057e",
+6407 => x"70bfffff",
+6408 => x"06705f71",
+6409 => x"fe0a0670",
+6410 => x"4270942a",
+6411 => x"5b525755",
+6412 => x"59577580",
+6413 => x"2e0b0b0b",
+6414 => x"0b873873",
+6415 => x"90800a07",
+6416 => x"5b7d5372",
+6417 => x"802e0b0b",
+6418 => x"0b80e038",
+6419 => x"725c8f3d",
+6420 => x"f405510b",
+6421 => x"0b0bf0b1",
+6422 => x"3f800855",
+6423 => x"8008802e",
+6424 => x"0b0b0b81",
+6425 => x"8d38a00b",
+6426 => x"8008317b",
+6427 => x"712b7d07",
+6428 => x"790c537a",
+6429 => x"80082a5b",
+6430 => x"7a70841a",
+6431 => x"0c703070",
+6432 => x"72078025",
+6433 => x"82713170",
+6434 => x"901c0c51",
+6435 => x"51545475",
+6436 => x"802e0b0b",
+6437 => x"0b0bb638",
+6438 => x"7416f7cd",
+6439 => x"05790cb5",
+6440 => x"75317a0c",
+6441 => x"76800c8f",
+6442 => x"3d0d048f",
+6443 => x"3df00551",
+6444 => x"0b0b0bef",
+6445 => x"d43f7a78",
+6446 => x"0c810b90",
+6447 => x"180c810b",
+6448 => x"8008a005",
+6449 => x"5653750b",
+6450 => x"0b0b0bcc",
+6451 => x"38f7ce15",
+6452 => x"790c7285",
+6453 => x"2b731010",
+6454 => x"19fc1108",
+6455 => x"5354540b",
+6456 => x"0b0beea4",
+6457 => x"3f738008",
+6458 => x"317a0c76",
+6459 => x"800c8f3d",
+6460 => x"0d047b78",
+6461 => x"0c7a7084",
+6462 => x"1a0c7030",
+6463 => x"70720780",
+6464 => x"25827131",
+6465 => x"70901c0c",
+6466 => x"51515454",
+6467 => x"0b0b0bfe",
+6468 => x"fe39f03d",
+6469 => x"0d626466",
+6470 => x"953de411",
+6471 => x"577256f8",
+6472 => x"05545858",
+6473 => x"580b0b0b",
+6474 => x"fbf03f92",
+6475 => x"3de01154",
+6476 => x"7653f005",
+6477 => x"510b0b0b",
+6478 => x"fbe03f90",
+6479 => x"17089017",
+6480 => x"0831852b",
+6481 => x"7b7b3111",
+6482 => x"51568076",
+6483 => x"250b0b0b",
+6484 => x"0bb03875",
+6485 => x"90800a29",
+6486 => x"6005407d",
+6487 => x"7f585476",
+6488 => x"557f6158",
+6489 => x"52765392",
+6490 => x"3de80551",
+6491 => x"0b0b80d6",
+6492 => x"ac3f7b7d",
+6493 => x"58780c76",
+6494 => x"84190c77",
+6495 => x"800c923d",
+6496 => x"0d047530",
+6497 => x"7090800a",
+6498 => x"291f5f56",
+6499 => x"7d7f5854",
+6500 => x"76557f61",
+6501 => x"58527653",
+6502 => x"923de805",
+6503 => x"510b0b80",
+6504 => x"d5fb3f7b",
+6505 => x"7d58780c",
+6506 => x"7684190c",
+6507 => x"77800c92",
+6508 => x"3d0d04f3",
+6509 => x"3d0d7f61",
+6510 => x"575c9ffc",
+6511 => x"0a578058",
+6512 => x"7597240b",
+6513 => x"0b0b0b9d",
+6514 => x"38751010",
+6515 => x"100b0b82",
+6516 => x"f2d80584",
+6517 => x"11087108",
+6518 => x"7e0c841e",
+6519 => x"0c7c800c",
+6520 => x"568f3d0d",
+6521 => x"04807625",
+6522 => x"0b0b0b0b",
+6523 => x"ab388d3d",
+6524 => x"5b80c882",
+6525 => x"0a59805a",
+6526 => x"78547955",
+6527 => x"76527753",
+6528 => x"7a510b0b",
+6529 => x"0bb6963f",
+6530 => x"7c7eff18",
+6531 => x"58595775",
+6532 => x"80240b0b",
+6533 => x"0b0be138",
+6534 => x"767c0c77",
+6535 => x"841d0c7b",
+6536 => x"800c8f3d",
+6537 => x"0d04ef3d",
+6538 => x"0d636567",
+6539 => x"405d427b",
+6540 => x"802e0b0b",
+6541 => x"0b85ea38",
+6542 => x"61510b0b",
+6543 => x"0be7883f",
+6544 => x"f81c7084",
+6545 => x"120870fc",
+6546 => x"0670628b",
+6547 => x"0570f806",
+6548 => x"4159455b",
+6549 => x"5c415796",
+6550 => x"74270b0b",
+6551 => x"0b82fe38",
+6552 => x"807b247e",
+6553 => x"7c260759",
+6554 => x"80547874",
+6555 => x"2e098106",
+6556 => x"0b0b0b82",
+6557 => x"e138777b",
+6558 => x"250b0b0b",
+6559 => x"82ab3877",
+6560 => x"170b0b82",
+6561 => x"fcc80b88",
+6562 => x"05085e56",
+6563 => x"7c762e0b",
+6564 => x"0b0b859f",
+6565 => x"38841608",
+6566 => x"70fe0617",
+6567 => x"84110881",
+6568 => x"06515555",
+6569 => x"730b0b0b",
+6570 => x"82bb3874",
+6571 => x"fc06597c",
+6572 => x"762e0b0b",
+6573 => x"0b85c938",
+6574 => x"77195f7e",
+6575 => x"7b250b0b",
+6576 => x"0b82aa38",
+6577 => x"79810654",
+6578 => x"730b0b0b",
+6579 => x"82f53876",
+6580 => x"77083184",
+6581 => x"1108fc06",
+6582 => x"565a7580",
+6583 => x"2e0b0b0b",
+6584 => x"0b97387c",
+6585 => x"762e0b0b",
+6586 => x"0b85d438",
+6587 => x"74191859",
+6588 => x"787b250b",
+6589 => x"0b0b84e2",
+6590 => x"3879802e",
+6591 => x"0b0b0b82",
+6592 => x"c2387715",
+6593 => x"567a7624",
+6594 => x"0b0b0b82",
+6595 => x"b6388c1a",
+6596 => x"08881b08",
+6597 => x"718c120c",
+6598 => x"88120c55",
+6599 => x"79765957",
+6600 => x"881761fc",
+6601 => x"05575975",
+6602 => x"a4260b0b",
+6603 => x"0b86e638",
+6604 => x"7b795555",
+6605 => x"9376270b",
+6606 => x"0b0b80d1",
+6607 => x"387b7084",
+6608 => x"055d087c",
+6609 => x"56790c74",
+6610 => x"70840556",
+6611 => x"088c180c",
+6612 => x"9017549b",
+6613 => x"76270b0b",
+6614 => x"0b0bb238",
+6615 => x"74708405",
+6616 => x"5608740c",
+6617 => x"74708405",
+6618 => x"56089418",
+6619 => x"0c981754",
+6620 => x"a376270b",
+6621 => x"0b0b0b95",
+6622 => x"38747084",
+6623 => x"05560874",
+6624 => x"0c747084",
+6625 => x"0556089c",
+6626 => x"180ca017",
+6627 => x"54747084",
+6628 => x"05560874",
+6629 => x"70840556",
+6630 => x"0c747084",
+6631 => x"05560874",
+6632 => x"70840556",
+6633 => x"0c740874",
+6634 => x"0c777b31",
+6635 => x"56758f26",
+6636 => x"0b0b0b80",
+6637 => x"d5388417",
+6638 => x"08810678",
+6639 => x"0784180c",
+6640 => x"77178411",
+6641 => x"08810784",
+6642 => x"120c5461",
+6643 => x"510b0b0b",
+6644 => x"e3f63f88",
+6645 => x"17547380",
+6646 => x"0c933d0d",
+6647 => x"04905b0b",
+6648 => x"0b0bfcfc",
+6649 => x"3978560b",
+6650 => x"0b0bfdd8",
+6651 => x"398c1608",
+6652 => x"88170871",
+6653 => x"8c120c88",
+6654 => x"120c557e",
+6655 => x"707c3157",
+6656 => x"588f7627",
+6657 => x"0b0b0bff",
+6658 => x"ad387a17",
+6659 => x"84180881",
+6660 => x"067c0784",
+6661 => x"190c7681",
+6662 => x"0784120c",
+6663 => x"76118411",
+6664 => x"08810784",
+6665 => x"120c5588",
+6666 => x"05526151",
+6667 => x"0b0bffbc",
+6668 => x"873f6151",
+6669 => x"0b0b0be3",
+6670 => x"8f3f8817",
+6671 => x"540b0b0b",
+6672 => x"ff94397d",
+6673 => x"5261510b",
+6674 => x"0b0bcef6",
+6675 => x"3f800859",
+6676 => x"8008802e",
+6677 => x"0b0b0b81",
+6678 => x"b7388008",
+6679 => x"f8056084",
+6680 => x"0508fe06",
+6681 => x"61055557",
+6682 => x"76742e0b",
+6683 => x"0b0b84b7",
+6684 => x"38fc1856",
+6685 => x"75a4260b",
+6686 => x"0b0b81c1",
+6687 => x"387b8008",
+6688 => x"55559376",
+6689 => x"270b0b0b",
+6690 => x"80e03874",
+6691 => x"70840556",
+6692 => x"08800870",
+6693 => x"8405800c",
+6694 => x"0c800875",
+6695 => x"70840557",
+6696 => x"08717084",
+6697 => x"05530c54",
+6698 => x"9b76270b",
+6699 => x"0b0b0bba",
+6700 => x"38747084",
+6701 => x"05560874",
+6702 => x"70840556",
+6703 => x"0c747084",
+6704 => x"05560874",
+6705 => x"70840556",
+6706 => x"0ca37627",
+6707 => x"0b0b0b0b",
+6708 => x"99387470",
+6709 => x"84055608",
+6710 => x"74708405",
+6711 => x"560c7470",
+6712 => x"84055608",
+6713 => x"74708405",
+6714 => x"560c7470",
+6715 => x"84055608",
+6716 => x"74708405",
+6717 => x"560c7470",
+6718 => x"84055608",
+6719 => x"74708405",
+6720 => x"560c7408",
+6721 => x"740c7b52",
+6722 => x"61510b0b",
+6723 => x"ffbaa93f",
+6724 => x"61510b0b",
+6725 => x"0be1b13f",
+6726 => x"78547380",
+6727 => x"0c933d0d",
+6728 => x"047d5261",
+6729 => x"510b0b0b",
+6730 => x"cd983f80",
+6731 => x"08800c93",
+6732 => x"3d0d0484",
+6733 => x"1608550b",
+6734 => x"0b0bfaef",
+6735 => x"3975537b",
+6736 => x"52800851",
+6737 => x"0b0bfec0",
+6738 => x"c23f7b52",
+6739 => x"61510b0b",
+6740 => x"ffb9e53f",
+6741 => x"0b0b0bff",
+6742 => x"b7398c16",
+6743 => x"08881708",
+6744 => x"718c120c",
+6745 => x"88120c55",
+6746 => x"8c1a0888",
+6747 => x"1b08718c",
+6748 => x"120c8812",
+6749 => x"0c557979",
+6750 => x"59570b0b",
+6751 => x"0bfba139",
+6752 => x"7719901c",
+6753 => x"55557375",
+6754 => x"240b0b0b",
+6755 => x"fab6387a",
+6756 => x"17700b0b",
+6757 => x"82fcc80b",
+6758 => x"88050c75",
+6759 => x"7c318107",
+6760 => x"84120c5d",
+6761 => x"84170881",
+6762 => x"067b0784",
+6763 => x"180c6151",
+6764 => x"0b0b0be0",
+6765 => x"933f8817",
+6766 => x"540b0b0b",
+6767 => x"fc983974",
+6768 => x"1918901c",
+6769 => x"555d737d",
+6770 => x"240b0b0b",
+6771 => x"faab388c",
+6772 => x"1a08881b",
+6773 => x"08718c12",
+6774 => x"0c88120c",
+6775 => x"55881a61",
+6776 => x"fc055759",
+6777 => x"75a4260b",
+6778 => x"0b0b81ca",
+6779 => x"387b7955",
+6780 => x"55937627",
+6781 => x"0b0b0b80",
+6782 => x"d1387b70",
+6783 => x"84055d08",
+6784 => x"7c56790c",
+6785 => x"74708405",
+6786 => x"56088c1b",
+6787 => x"0c901a54",
+6788 => x"9b76270b",
+6789 => x"0b0b0bb2",
+6790 => x"38747084",
+6791 => x"05560874",
+6792 => x"0c747084",
+6793 => x"05560894",
+6794 => x"1b0c981a",
+6795 => x"54a37627",
+6796 => x"0b0b0b0b",
+6797 => x"95387470",
+6798 => x"84055608",
+6799 => x"740c7470",
+6800 => x"84055608",
+6801 => x"9c1b0ca0",
+6802 => x"1a547470",
+6803 => x"84055608",
+6804 => x"74708405",
+6805 => x"560c7470",
+6806 => x"84055608",
+6807 => x"74708405",
+6808 => x"560c7408",
+6809 => x"740c7a1a",
+6810 => x"700b0b82",
+6811 => x"fcc80b88",
+6812 => x"050c7d7c",
+6813 => x"31810784",
+6814 => x"120c5484",
+6815 => x"1a088106",
+6816 => x"7b07841b",
+6817 => x"0c61510b",
+6818 => x"0b0bdebc",
+6819 => x"3f78540b",
+6820 => x"0b0bfd86",
+6821 => x"3975537b",
+6822 => x"5278510b",
+6823 => x"0bfebdeb",
+6824 => x"3f0b0b0b",
+6825 => x"fa833984",
+6826 => x"1708fc06",
+6827 => x"18605858",
+6828 => x"0b0b0bf9",
+6829 => x"f4397553",
+6830 => x"7b527851",
+6831 => x"0b0bfebd",
+6832 => x"ca3f7a1a",
+6833 => x"700b0b82",
+6834 => x"fcc80b88",
+6835 => x"050c7d7c",
+6836 => x"31810784",
+6837 => x"120c5484",
+6838 => x"1a088106",
+6839 => x"7b07841b",
+6840 => x"0c0b0b0b",
+6841 => x"ff9f3970",
+6842 => x"70707075",
+6843 => x"77535371",
+6844 => x"54733070",
+6845 => x"75079f2a",
+6846 => x"7075fe0a",
+6847 => x"06079081",
+6848 => x"0a119ffe",
+6849 => x"0a723107",
+6850 => x"709f2a81",
+6851 => x"7131800c",
+6852 => x"51515151",
+6853 => x"51505050",
+6854 => x"50047070",
+6855 => x"70707577",
+6856 => x"53537154",
+6857 => x"73307075",
+6858 => x"079f2a70",
+6859 => x"75fe0a06",
+6860 => x"079ffe0a",
+6861 => x"71319f2a",
+6862 => x"800c5151",
+6863 => x"51505050",
+6864 => x"50047070",
+6865 => x"7070800b",
+6866 => x"0b0b8385",
+6867 => x"840c7651",
+6868 => x"0b0b0b8c",
+6869 => x"f33f8008",
+6870 => x"538008ff",
+6871 => x"2e0b0b0b",
+6872 => x"0b893872",
+6873 => x"800c5050",
+6874 => x"5050040b",
+6875 => x"0b838584",
+6876 => x"08547380",
+6877 => x"2e0b0b0b",
+6878 => x"0be93875",
+6879 => x"74710c52",
+6880 => x"72800c50",
+6881 => x"50505004",
+6882 => x"f93d0d79",
+6883 => x"7c557b54",
+6884 => x"8e112270",
+6885 => x"902b7090",
+6886 => x"2c55570b",
+6887 => x"0b82f4ec",
+6888 => x"08535856",
+6889 => x"0b0b0b88",
+6890 => x"ac3f8008",
+6891 => x"57800b80",
+6892 => x"08240b0b",
+6893 => x"0b0b9338",
+6894 => x"80d01608",
+6895 => x"80080580",
+6896 => x"d0170c76",
+6897 => x"800c893d",
+6898 => x"0d048c16",
+6899 => x"2283dfff",
+6900 => x"0655748c",
+6901 => x"17237680",
+6902 => x"0c893d0d",
+6903 => x"04fa3d0d",
+6904 => x"788c1122",
+6905 => x"70882a70",
+6906 => x"81065157",
+6907 => x"5856740b",
+6908 => x"0b0b0bae",
+6909 => x"388c1622",
+6910 => x"83dfff06",
+6911 => x"55748c17",
+6912 => x"237a5479",
+6913 => x"538e1622",
+6914 => x"70902b70",
+6915 => x"902c5456",
+6916 => x"0b0b82f4",
+6917 => x"ec085256",
+6918 => x"0b0b0b83",
+6919 => x"f33f883d",
+6920 => x"0d048254",
+6921 => x"80538e16",
+6922 => x"2270902b",
+6923 => x"70902c54",
+6924 => x"560b0b82",
+6925 => x"f4ec0852",
+6926 => x"570b0b0b",
+6927 => x"86d03f8c",
+6928 => x"162283df",
+6929 => x"ff065574",
+6930 => x"8c17237a",
+6931 => x"5479538e",
+6932 => x"16227090",
+6933 => x"2b70902c",
+6934 => x"54560b0b",
+6935 => x"82f4ec08",
+6936 => x"52560b0b",
+6937 => x"0b83a93f",
+6938 => x"883d0d04",
+6939 => x"f93d0d79",
+6940 => x"7c557b54",
+6941 => x"8e112270",
+6942 => x"902b7090",
+6943 => x"2c55570b",
+6944 => x"0b82f4ec",
+6945 => x"08535856",
+6946 => x"0b0b0b86",
+6947 => x"813f8008",
+6948 => x"578008ff",
+6949 => x"2e0b0b0b",
+6950 => x"0b99388c",
+6951 => x"1622a080",
+6952 => x"0755748c",
+6953 => x"17238008",
+6954 => x"80d0170c",
+6955 => x"76800c89",
+6956 => x"3d0d048c",
+6957 => x"162283df",
+6958 => x"ff065574",
+6959 => x"8c172376",
+6960 => x"800c893d",
+6961 => x"0d047070",
+6962 => x"70748e11",
+6963 => x"2270902b",
+6964 => x"70902c55",
+6965 => x"5151530b",
+6966 => x"0b82f4ec",
+6967 => x"08510b0b",
+6968 => x"0b84a03f",
+6969 => x"50505004",
+6970 => x"fb3d0d77",
+6971 => x"79707207",
+6972 => x"83065354",
+6973 => x"52700b0b",
+6974 => x"0b0b9638",
+6975 => x"71737308",
+6976 => x"54565471",
+6977 => x"73082e0b",
+6978 => x"0b0b80d0",
+6979 => x"38737554",
+6980 => x"52713370",
+6981 => x"81ff0652",
+6982 => x"5470802e",
+6983 => x"0b0b0b0b",
+6984 => x"a5387233",
+6985 => x"5570752e",
+6986 => x"0981060b",
+6987 => x"0b0b0b99",
+6988 => x"38811281",
+6989 => x"14713370",
+6990 => x"81ff0654",
+6991 => x"56545270",
+6992 => x"0b0b0b0b",
+6993 => x"dd387233",
+6994 => x"557381ff",
+6995 => x"067581ff",
+6996 => x"06717131",
+6997 => x"800c5252",
+6998 => x"873d0d04",
+6999 => x"710970f7",
+7000 => x"fbfdff14",
+7001 => x"0670f884",
+7002 => x"82818006",
+7003 => x"51515170",
+7004 => x"0b0b0b0b",
+7005 => x"9e388414",
+7006 => x"84167108",
+7007 => x"54565471",
+7008 => x"75082e0b",
+7009 => x"0b0b0bd4",
+7010 => x"38737554",
+7011 => x"520b0b0b",
+7012 => x"feff3980",
+7013 => x"0b800c87",
+7014 => x"3d0d0470",
+7015 => x"70707075",
+7016 => x"70718306",
+7017 => x"53555270",
+7018 => x"0b0b0b80",
+7019 => x"c0387170",
+7020 => x"087009f7",
+7021 => x"fbfdff12",
+7022 => x"0670f884",
+7023 => x"82818006",
+7024 => x"51515253",
+7025 => x"700b0b0b",
+7026 => x"0ba13884",
+7027 => x"13700870",
+7028 => x"09f7fbfd",
+7029 => x"ff120670",
+7030 => x"f8848281",
+7031 => x"80065151",
+7032 => x"52537080",
+7033 => x"2e0b0b0b",
+7034 => x"0be13872",
+7035 => x"52713351",
+7036 => x"70802e0b",
+7037 => x"0b0b0b8e",
+7038 => x"38811270",
+7039 => x"33525270",
+7040 => x"0b0b0b0b",
+7041 => x"f4387174",
+7042 => x"31800c50",
+7043 => x"50505004",
+7044 => x"fb3d0d80",
+7045 => x"0b0b0b83",
+7046 => x"85840c7a",
+7047 => x"53795278",
+7048 => x"510b0b0b",
+7049 => x"88de3f80",
+7050 => x"08558008",
+7051 => x"ff2e0b0b",
+7052 => x"0b0b8838",
+7053 => x"74800c87",
+7054 => x"3d0d040b",
+7055 => x"0b838584",
+7056 => x"08567580",
+7057 => x"2e0b0b0b",
+7058 => x"0bea3877",
+7059 => x"76710c54",
+7060 => x"74800c87",
+7061 => x"3d0d04fb",
+7062 => x"3d0d787a",
+7063 => x"29527751",
+7064 => x"0b0b0bc2",
+7065 => x"dd3f8008",
+7066 => x"80085556",
+7067 => x"8008802e",
+7068 => x"0b0b0b80",
+7069 => x"f2388008",
+7070 => x"fc0508fc",
+7071 => x"06fc0555",
+7072 => x"74a4260b",
+7073 => x"0b0b80e6",
+7074 => x"38937527",
+7075 => x"0b0b0b80",
+7076 => x"c338800b",
+7077 => x"80087084",
+7078 => x"05800c0c",
+7079 => x"80085480",
+7080 => x"74708405",
+7081 => x"560c9b75",
+7082 => x"270b0b0b",
+7083 => x"0ba63880",
+7084 => x"74708405",
+7085 => x"560c8074",
+7086 => x"70840556",
+7087 => x"0ca37527",
+7088 => x"0b0b0b0b",
+7089 => x"8f388074",
+7090 => x"70840556",
+7091 => x"0c807470",
+7092 => x"8405560c",
+7093 => x"80747084",
+7094 => x"05560c80",
+7095 => x"74708405",
+7096 => x"560c8074",
+7097 => x"0c755473",
+7098 => x"800c873d",
+7099 => x"0d047453",
+7100 => x"80528008",
+7101 => x"510b0b0b",
+7102 => x"d49b3f75",
+7103 => x"540b0b0b",
+7104 => x"0be53970",
+7105 => x"70707080",
+7106 => x"0b0b0b83",
+7107 => x"85840c76",
+7108 => x"510b0b0b",
+7109 => x"8a943f80",
+7110 => x"08538008",
+7111 => x"ff2e0b0b",
+7112 => x"0b0b8938",
+7113 => x"72800c50",
+7114 => x"50505004",
+7115 => x"0b0b8385",
+7116 => x"84085473",
+7117 => x"802e0b0b",
+7118 => x"0b0be938",
+7119 => x"7574710c",
+7120 => x"5272800c",
+7121 => x"50505050",
+7122 => x"04fc3d0d",
+7123 => x"800b0b0b",
+7124 => x"8385840c",
+7125 => x"78527751",
+7126 => x"0b0b0b8d",
+7127 => x"823f8008",
+7128 => x"548008ff",
+7129 => x"2e0b0b0b",
+7130 => x"0b883873",
+7131 => x"800c863d",
+7132 => x"0d040b0b",
+7133 => x"83858408",
+7134 => x"5574802e",
+7135 => x"0b0b0b0b",
+7136 => x"ea387675",
+7137 => x"710c5373",
+7138 => x"800c863d",
+7139 => x"0d04fb3d",
+7140 => x"0d800b0b",
+7141 => x"0b838584",
+7142 => x"0c7a5379",
+7143 => x"5278510b",
+7144 => x"0b0b8a9e",
+7145 => x"3f800855",
+7146 => x"8008ff2e",
+7147 => x"0b0b0b0b",
+7148 => x"88387480",
+7149 => x"0c873d0d",
+7150 => x"040b0b83",
+7151 => x"85840856",
+7152 => x"75802e0b",
+7153 => x"0b0b0bea",
+7154 => x"38777671",
+7155 => x"0c547480",
+7156 => x"0c873d0d",
+7157 => x"04fb3d0d",
+7158 => x"800b0b0b",
+7159 => x"8385840c",
+7160 => x"7a537952",
+7161 => x"78510b0b",
+7162 => x"0b86b13f",
+7163 => x"80085580",
+7164 => x"08ff2e0b",
+7165 => x"0b0b0b88",
+7166 => x"3874800c",
+7167 => x"873d0d04",
+7168 => x"0b0b8385",
+7169 => x"84085675",
+7170 => x"802e0b0b",
+7171 => x"0b0bea38",
+7172 => x"7776710c",
+7173 => x"5474800c",
+7174 => x"873d0d04",
+7175 => x"fc3d0d76",
+7176 => x"78700855",
+7177 => x"5555720b",
+7178 => x"0b0b0b8f",
+7179 => x"38735274",
+7180 => x"510b0bff",
+7181 => x"ac823f86",
+7182 => x"3d0d0472",
+7183 => x"5274510b",
+7184 => x"0b0b0bd8",
+7185 => x"3f735274",
+7186 => x"510b0bff",
+7187 => x"abea3f86",
+7188 => x"3d0d04fb",
+7189 => x"3d0d7755",
+7190 => x"740b0b82",
+7191 => x"f4ec082e",
+7192 => x"0b0b0b80",
+7193 => x"fe3880cc",
+7194 => x"15085380",
+7195 => x"5672762e",
+7196 => x"0981060b",
+7197 => x"0b0b8180",
+7198 => x"3882c815",
+7199 => x"08537280",
+7200 => x"2e0b0b0b",
+7201 => x"0bb23882",
+7202 => x"cc155672",
+7203 => x"762e0b0b",
+7204 => x"0b0ba538",
+7205 => x"72547574",
+7206 => x"2e0b0b0b",
+7207 => x"0b9a3873",
+7208 => x"74085552",
+7209 => x"74510b0b",
+7210 => x"ffab8d3f",
+7211 => x"75742e09",
+7212 => x"81060b0b",
+7213 => x"0b0be838",
+7214 => x"80d41508",
+7215 => x"53720b0b",
+7216 => x"0b80d938",
+7217 => x"b8150880",
+7218 => x"2e0b0b0b",
+7219 => x"0b953874",
+7220 => x"51bc1508",
+7221 => x"53722d84",
+7222 => x"dc150853",
+7223 => x"720b0b0b",
+7224 => x"80ca3887",
+7225 => x"3d0d0481",
+7226 => x"1656758e",
+7227 => x"240b0b0b",
+7228 => x"80c83880",
+7229 => x"cc150853",
+7230 => x"75101013",
+7231 => x"70085553",
+7232 => x"73802e0b",
+7233 => x"0b0b0bdf",
+7234 => x"38737408",
+7235 => x"55527451",
+7236 => x"0b0bffaa",
+7237 => x"a33f0b0b",
+7238 => x"0b0be539",
+7239 => x"72527451",
+7240 => x"0b0bffaa",
+7241 => x"933f0b0b",
+7242 => x"0bff9939",
+7243 => x"72527451",
+7244 => x"0b0b0bfd",
+7245 => x"e73f873d",
+7246 => x"0d0480cc",
+7247 => x"15085274",
+7248 => x"510b0bff",
+7249 => x"a9f23f0b",
+7250 => x"0b0bfead",
+7251 => x"39fb3d0d",
+7252 => x"77567580",
+7253 => x"2e0b0b0b",
+7254 => x"80dc3882",
+7255 => x"c8160855",
+7256 => x"74802e0b",
+7257 => x"0b0b0bb5",
+7258 => x"38841508",
+7259 => x"ff055480",
+7260 => x"74240b0b",
+7261 => x"0b0b9c38",
+7262 => x"73101015",
+7263 => x"88055372",
+7264 => x"08fc1454",
+7265 => x"52712dff",
+7266 => x"14547380",
+7267 => x"250b0b0b",
+7268 => x"0bed3874",
+7269 => x"0855740b",
+7270 => x"0b0b0bcd",
+7271 => x"38bc1608",
+7272 => x"0b0b0b0b",
+7273 => x"8538873d",
+7274 => x"0d047551",
+7275 => x"bc160852",
+7276 => x"712d873d",
+7277 => x"0d040b0b",
+7278 => x"82f4ec08",
+7279 => x"82c81108",
+7280 => x"56560b0b",
+7281 => x"0bff9939",
+7282 => x"7070700b",
+7283 => x"0b8384fc",
+7284 => x"080b0b0b",
+7285 => x"0b8d380b",
+7286 => x"0b838588",
+7287 => x"0b0b0b83",
+7288 => x"84fc0c0b",
+7289 => x"0b8384fc",
+7290 => x"08751152",
+7291 => x"52ff5370",
+7292 => x"0b87fb80",
+7293 => x"80260b0b",
+7294 => x"0b0b8a38",
+7295 => x"700b0b83",
+7296 => x"84fc0c71",
+7297 => x"5372800c",
+7298 => x"50505004",
+7299 => x"fd3d0d80",
+7300 => x"0b0b0b82",
+7301 => x"f4e00854",
+7302 => x"5472812e",
+7303 => x"0b0b0b0b",
+7304 => x"ab38730b",
+7305 => x"0b838580",
+7306 => x"0c0b0bfe",
+7307 => x"a5853f0b",
+7308 => x"0bfea3cc",
+7309 => x"3f0b0b83",
+7310 => x"84d05281",
+7311 => x"510b0bfe",
+7312 => x"a7dd3f80",
+7313 => x"08510b0b",
+7314 => x"0b89973f",
+7315 => x"720b0b83",
+7316 => x"85800c0b",
+7317 => x"0bfea4db",
+7318 => x"3f0b0bfe",
+7319 => x"a3a23f0b",
+7320 => x"0b8384d0",
+7321 => x"5281510b",
+7322 => x"0bfea7b3",
+7323 => x"3f800851",
+7324 => x"0b0b0b88",
+7325 => x"ed3f000b",
+7326 => x"0b0b0bfb",
+7327 => x"39000b0b",
+7328 => x"0b0bfb39",
+7329 => x"f53d0d7e",
+7330 => x"600b0b83",
+7331 => x"85800870",
+7332 => x"5b585b5b",
+7333 => x"750b0b0b",
+7334 => x"80db3877",
+7335 => x"7a250b0b",
+7336 => x"0b0bac38",
+7337 => x"771b7033",
+7338 => x"7081ff06",
+7339 => x"58585975",
+7340 => x"8a2e0b0b",
+7341 => x"0b0b9f38",
+7342 => x"7681ff06",
+7343 => x"510b0bfe",
+7344 => x"a3cc3f81",
+7345 => x"18587978",
+7346 => x"240b0b0b",
+7347 => x"0bd63879",
+7348 => x"800c8d3d",
+7349 => x"0d048d51",
+7350 => x"0b0bfea3",
+7351 => x"b13f7833",
+7352 => x"7081ff06",
+7353 => x"52570b0b",
+7354 => x"fea3a33f",
+7355 => x"8118580b",
+7356 => x"0b0b0bd2",
+7357 => x"3979557a",
+7358 => x"547d5385",
+7359 => x"528d3dfc",
+7360 => x"05510b0b",
+7361 => x"fea2c03f",
+7362 => x"8008560b",
+7363 => x"0b0b87c9",
+7364 => x"3f7b8008",
+7365 => x"0c75800c",
+7366 => x"8d3d0d04",
+7367 => x"f63d0d7d",
+7368 => x"7f0b0b83",
+7369 => x"85800870",
+7370 => x"5b585a5a",
+7371 => x"750b0b0b",
+7372 => x"80d63877",
+7373 => x"79250b0b",
+7374 => x"0b80c438",
+7375 => x"0b0bfea2",
+7376 => x"a43f8008",
+7377 => x"81ff0670",
+7378 => x"8d327030",
+7379 => x"709f2a51",
+7380 => x"51575776",
+7381 => x"8a2e0b0b",
+7382 => x"0b80d438",
+7383 => x"75802e0b",
+7384 => x"0b0b80cb",
+7385 => x"38771a56",
+7386 => x"76763476",
+7387 => x"510b0bfe",
+7388 => x"a29c3f81",
+7389 => x"18587878",
+7390 => x"240b0b0b",
+7391 => x"ffbe3877",
+7392 => x"5675800c",
+7393 => x"8c3d0d04",
+7394 => x"78557954",
+7395 => x"7c538452",
+7396 => x"8c3dfc05",
+7397 => x"510b0bfe",
+7398 => x"a1ad3f80",
+7399 => x"08560b0b",
+7400 => x"0b86b63f",
+7401 => x"7a80080c",
+7402 => x"75800c8c",
+7403 => x"3d0d0477",
+7404 => x"1a568a76",
+7405 => x"34811858",
+7406 => x"8d510b0b",
+7407 => x"fea1cf3f",
+7408 => x"8a510b0b",
+7409 => x"fea1c73f",
+7410 => x"77560b0b",
+7411 => x"0bffb239",
+7412 => x"f93d0d79",
+7413 => x"570b0b83",
+7414 => x"85800880",
+7415 => x"2e0b0b0b",
+7416 => x"0bb53876",
+7417 => x"510b0b0b",
+7418 => x"f3b13f7b",
+7419 => x"567a5580",
+7420 => x"08810554",
+7421 => x"76538252",
+7422 => x"893dfc05",
+7423 => x"510b0bfe",
+7424 => x"a0c53f80",
+7425 => x"08570b0b",
+7426 => x"0b85ce3f",
+7427 => x"7780080c",
+7428 => x"76800c89",
+7429 => x"3d0d040b",
+7430 => x"0b0b85bd",
+7431 => x"3f850b80",
+7432 => x"080cff0b",
+7433 => x"800c893d",
+7434 => x"0d04fb3d",
+7435 => x"0d0b0b83",
+7436 => x"85800870",
+7437 => x"5654730b",
+7438 => x"0b0b0b88",
+7439 => x"3874800c",
+7440 => x"873d0d04",
+7441 => x"77538352",
+7442 => x"873dfc05",
+7443 => x"510b0bfe",
+7444 => x"9ff53f80",
+7445 => x"08540b0b",
+7446 => x"0b84fe3f",
+7447 => x"7580080c",
+7448 => x"73800c87",
+7449 => x"3d0d04ff",
+7450 => x"0b800c04",
+7451 => x"fb3d0d77",
+7452 => x"550b0b83",
+7453 => x"85800880",
+7454 => x"2e0b0b0b",
+7455 => x"0bb13874",
+7456 => x"510b0b0b",
+7457 => x"f2953f80",
+7458 => x"08810554",
+7459 => x"74538752",
+7460 => x"873dfc05",
+7461 => x"510b0bfe",
+7462 => x"9fad3f80",
+7463 => x"08550b0b",
+7464 => x"0b84b63f",
+7465 => x"7580080c",
+7466 => x"74800c87",
+7467 => x"3d0d040b",
+7468 => x"0b0b84a5",
+7469 => x"3f850b80",
+7470 => x"080cff0b",
+7471 => x"800c873d",
+7472 => x"0d04fa3d",
+7473 => x"0d0b0b83",
+7474 => x"85800880",
+7475 => x"2e0b0b0b",
+7476 => x"0ba8387a",
+7477 => x"55795478",
+7478 => x"53865288",
+7479 => x"3dfc0551",
+7480 => x"0b0bfe9e",
+7481 => x"e23f8008",
+7482 => x"560b0b0b",
+7483 => x"83eb3f76",
+7484 => x"80080c75",
+7485 => x"800c883d",
+7486 => x"0d040b0b",
+7487 => x"0b83da3f",
+7488 => x"9d0b8008",
+7489 => x"0cff0b80",
+7490 => x"0c883d0d",
+7491 => x"04fb3d0d",
+7492 => x"77795656",
+7493 => x"80705454",
+7494 => x"7375250b",
+7495 => x"0b0b0ba3",
+7496 => x"38741010",
+7497 => x"10f80552",
+7498 => x"72167033",
+7499 => x"70742b76",
+7500 => x"078116f8",
+7501 => x"16565656",
+7502 => x"51517473",
+7503 => x"240b0b0b",
+7504 => x"0be63873",
+7505 => x"800c873d",
+7506 => x"0d04fc3d",
+7507 => x"0d767855",
+7508 => x"55bc5380",
+7509 => x"5273510b",
+7510 => x"0b0bc7b9",
+7511 => x"3f845274",
+7512 => x"510b0b0b",
+7513 => x"ffa73f80",
+7514 => x"08742384",
+7515 => x"52841551",
+7516 => x"0b0b0bff",
+7517 => x"983f8008",
+7518 => x"82152384",
+7519 => x"52881551",
+7520 => x"0b0b0bff",
+7521 => x"883f8008",
+7522 => x"84150c84",
+7523 => x"528c1551",
+7524 => x"0b0b0bfe",
+7525 => x"f83f8008",
+7526 => x"88152384",
+7527 => x"52901551",
+7528 => x"0b0b0bfe",
+7529 => x"e83f8008",
+7530 => x"8a152384",
+7531 => x"52941551",
+7532 => x"0b0b0bfe",
+7533 => x"d83f8008",
+7534 => x"8c152384",
+7535 => x"52981551",
+7536 => x"0b0b0bfe",
+7537 => x"c83f8008",
+7538 => x"8e152388",
+7539 => x"529c1551",
+7540 => x"0b0b0bfe",
+7541 => x"b83f8008",
+7542 => x"90150c86",
+7543 => x"3d0d04e9",
+7544 => x"3d0d6a0b",
+7545 => x"0b838580",
+7546 => x"08575775",
+7547 => x"0b0b0b0b",
+7548 => x"933880c0",
+7549 => x"800b8418",
+7550 => x"0c75ac18",
+7551 => x"0c75800c",
+7552 => x"993d0d04",
+7553 => x"893d7055",
+7554 => x"6a54558a",
+7555 => x"52993dff",
+7556 => x"bc05510b",
+7557 => x"0bfe9caf",
+7558 => x"3f800877",
+7559 => x"53755256",
+7560 => x"0b0b0bfe",
+7561 => x"a53f0b0b",
+7562 => x"0b81ae3f",
+7563 => x"7780080c",
+7564 => x"75800c99",
+7565 => x"3d0d04e9",
+7566 => x"3d0d6957",
+7567 => x"0b0b8385",
+7568 => x"8008802e",
+7569 => x"0b0b0b80",
+7570 => x"c1387651",
+7571 => x"0b0b0bee",
+7572 => x"ca3f893d",
+7573 => x"70568008",
+7574 => x"81055577",
+7575 => x"54568f52",
+7576 => x"993dffbc",
+7577 => x"05510b0b",
+7578 => x"fe9bdc3f",
+7579 => x"80086b53",
+7580 => x"7652570b",
+7581 => x"0b0bfdd2",
+7582 => x"3f0b0b0b",
+7583 => x"80db3f77",
+7584 => x"80080c76",
+7585 => x"800c993d",
+7586 => x"0d040b0b",
+7587 => x"0b80ca3f",
+7588 => x"850b8008",
+7589 => x"0cff0b80",
+7590 => x"0c993d0d",
+7591 => x"04fc3d0d",
+7592 => x"81540b0b",
+7593 => x"83858008",
+7594 => x"0b0b0b0b",
+7595 => x"88387380",
+7596 => x"0c863d0d",
+7597 => x"04765397",
+7598 => x"b952863d",
+7599 => x"fc05510b",
+7600 => x"0bfe9b83",
+7601 => x"3f800854",
+7602 => x"0b0b0b0b",
+7603 => x"8c3f7480",
+7604 => x"080c7380",
+7605 => x"0c863d0d",
+7606 => x"040b0b82",
+7607 => x"f4ec0880",
+7608 => x"0c04f73d",
+7609 => x"0d7b0b0b",
+7610 => x"82f4ec08",
+7611 => x"82c81108",
+7612 => x"5a545a77",
+7613 => x"802e0b0b",
+7614 => x"0b80ee38",
+7615 => x"81881884",
+7616 => x"1908ff05",
+7617 => x"81712b59",
+7618 => x"55598074",
+7619 => x"240b0b0b",
+7620 => x"81893880",
+7621 => x"74240b0b",
+7622 => x"0b0bbd38",
+7623 => x"73822b78",
+7624 => x"11880556",
+7625 => x"56818019",
+7626 => x"08770653",
+7627 => x"72802e0b",
+7628 => x"0b0b80c6",
+7629 => x"38781670",
+7630 => x"08535379",
+7631 => x"51740853",
+7632 => x"722dff14",
+7633 => x"fc17fc17",
+7634 => x"79812c5a",
+7635 => x"57575473",
+7636 => x"80250b0b",
+7637 => x"0b0bce38",
+7638 => x"77085877",
+7639 => x"0b0b0bff",
+7640 => x"9b380b0b",
+7641 => x"82f4ec08",
+7642 => x"53bc1308",
+7643 => x"0b0b0b0b",
+7644 => x"b2387951",
+7645 => x"0b0b0bf5",
+7646 => x"fd3f7408",
+7647 => x"53722dff",
+7648 => x"14fc17fc",
+7649 => x"1779812c",
+7650 => x"5a575754",
+7651 => x"7380250b",
+7652 => x"0b0bff91",
+7653 => x"380b0b0b",
+7654 => x"ffbe3980",
+7655 => x"570b0b0b",
+7656 => x"fef13972",
+7657 => x"51bc1308",
+7658 => x"53722d79",
+7659 => x"510b0b0b",
+7660 => x"f5c43f8c",
+7661 => x"08028c0c",
+7662 => x"d43d0d8c",
+7663 => x"08880508",
+7664 => x"510b0b0b",
+7665 => x"8fb43f80",
+7666 => x"08547380",
+7667 => x"2e0b0b0b",
+7668 => x"0b93388c",
+7669 => x"08880508",
+7670 => x"708c08d0",
+7671 => x"050c540b",
+7672 => x"0b0b8e8a",
+7673 => x"398c088c",
+7674 => x"0508510b",
+7675 => x"0b0b8f8a",
+7676 => x"3f800854",
+7677 => x"73802e0b",
+7678 => x"0b0b0b93",
+7679 => x"388c088c",
+7680 => x"0508708c",
+7681 => x"08d0050c",
+7682 => x"540b0b0b",
+7683 => x"8de0398c",
+7684 => x"08880508",
+7685 => x"510b0b0b",
+7686 => x"8eaa3f80",
+7687 => x"08547380",
+7688 => x"2e0b0b0b",
+7689 => x"80d9388c",
+7690 => x"088c0508",
+7691 => x"510b0b0b",
+7692 => x"8e923f80",
+7693 => x"08547380",
+7694 => x"2e0b0b0b",
+7695 => x"0baf388c",
+7696 => x"08880508",
+7697 => x"8c088c05",
+7698 => x"08555584",
+7699 => x"15088415",
+7700 => x"082e0b0b",
+7701 => x"0b0b9638",
+7702 => x"0b0b0b8d",
+7703 => x"d43f8008",
+7704 => x"708c08d0",
+7705 => x"050c540b",
+7706 => x"0b0b8d82",
+7707 => x"398c0888",
+7708 => x"0508708c",
+7709 => x"08d0050c",
+7710 => x"540b0b0b",
+7711 => x"8cf0398c",
+7712 => x"088c0508",
+7713 => x"510b0b0b",
+7714 => x"8dba3f80",
+7715 => x"08547380",
+7716 => x"2e0b0b0b",
+7717 => x"0b93388c",
+7718 => x"088c0508",
+7719 => x"708c08d0",
+7720 => x"050c540b",
+7721 => x"0b0b8cc6",
+7722 => x"398c088c",
+7723 => x"0508510b",
+7724 => x"0b0b8cc7",
+7725 => x"3f800854",
+7726 => x"73802e0b",
+7727 => x"0b0b80f5",
+7728 => x"388c0888",
+7729 => x"0508510b",
+7730 => x"0b0b8caf",
+7731 => x"3f800854",
+7732 => x"73802e0b",
+7733 => x"0b0b80cb",
+7734 => x"388c0890",
+7735 => x"05088c08",
+7736 => x"88050871",
+7737 => x"58565494",
+7738 => x"70547553",
+7739 => x"7652540b",
+7740 => x"0bfea197",
+7741 => x"3f8c0890",
+7742 => x"05088c08",
+7743 => x"8805088c",
+7744 => x"088c0508",
+7745 => x"84120884",
+7746 => x"12080684",
+7747 => x"140c8c08",
+7748 => x"90050870",
+7749 => x"8c08d005",
+7750 => x"0c515656",
+7751 => x"560b0b0b",
+7752 => x"8bcc398c",
+7753 => x"08880508",
+7754 => x"708c08d0",
+7755 => x"050c540b",
+7756 => x"0b0b8bba",
+7757 => x"398c0888",
+7758 => x"0508510b",
+7759 => x"0b0b8bbb",
+7760 => x"3f800854",
+7761 => x"73802e0b",
+7762 => x"0b0b0b93",
+7763 => x"388c088c",
+7764 => x"0508708c",
+7765 => x"08d0050c",
+7766 => x"540b0b0b",
+7767 => x"8b90398c",
+7768 => x"08880508",
+7769 => x"8811088c",
+7770 => x"08f4050c",
+7771 => x"8c088c05",
+7772 => x"08881108",
+7773 => x"8c08f005",
+7774 => x"0c8c0888",
+7775 => x"05085151",
+7776 => x"54901408",
+7777 => x"8c150855",
+7778 => x"55738c08",
+7779 => x"e8050c74",
+7780 => x"8c08ec05",
+7781 => x"0c8c088c",
+7782 => x"05085490",
+7783 => x"14088c15",
+7784 => x"08555573",
+7785 => x"8c08e005",
+7786 => x"0c748c08",
+7787 => x"e4050c8c",
+7788 => x"08f40508",
+7789 => x"8c08f005",
+7790 => x"08318c08",
+7791 => x"dc050c8c",
+7792 => x"08dc0508",
+7793 => x"80250b0b",
+7794 => x"0b0b8c38",
+7795 => x"8c08dc05",
+7796 => x"08308c08",
+7797 => x"dc050c8c",
+7798 => x"08dc0508",
+7799 => x"bf240b0b",
+7800 => x"0b81bf38",
+7801 => x"8c08f005",
+7802 => x"088c08f4",
+7803 => x"0508250b",
+7804 => x"0b0b80cf",
+7805 => x"388c08f0",
+7806 => x"05088105",
+7807 => x"8c08f005",
+7808 => x"0c8c08e0",
+7809 => x"05088006",
+7810 => x"8c08e405",
+7811 => x"0881068c",
+7812 => x"08e00508",
+7813 => x"9f2b8c08",
+7814 => x"e4050881",
+7815 => x"2a707207",
+7816 => x"8c08e005",
+7817 => x"08812a70",
+7818 => x"76078c08",
+7819 => x"e0050c74",
+7820 => x"72078c08",
+7821 => x"e4050c59",
+7822 => x"595b5b58",
+7823 => x"560b0b0b",
+7824 => x"ffa2398c",
+7825 => x"08f40508",
+7826 => x"8c08f005",
+7827 => x"08250b0b",
+7828 => x"0b819a38",
+7829 => x"8c08f405",
+7830 => x"0881058c",
+7831 => x"08f4050c",
+7832 => x"8c08e805",
+7833 => x"0880068c",
+7834 => x"08ec0508",
+7835 => x"81068c08",
+7836 => x"e805089f",
+7837 => x"2b8c08ec",
+7838 => x"0508812a",
+7839 => x"7072078c",
+7840 => x"08e80508",
+7841 => x"812a7076",
+7842 => x"078c08e8",
+7843 => x"050c7472",
+7844 => x"078c08ec",
+7845 => x"050c5959",
+7846 => x"5b5b5856",
+7847 => x"0b0b0bff",
+7848 => x"a2398c08",
+7849 => x"f005088c",
+7850 => x"08f40508",
+7851 => x"250b0b0b",
+7852 => x"0ba1388c",
+7853 => x"08f40508",
+7854 => x"8c08f005",
+7855 => x"0c805480",
+7856 => x"55738c08",
+7857 => x"e0050c74",
+7858 => x"8c08e405",
+7859 => x"0c0b0b0b",
+7860 => x"0b9b398c",
+7861 => x"08f00508",
+7862 => x"8c08f405",
+7863 => x"0c805480",
+7864 => x"55738c08",
+7865 => x"e8050c74",
+7866 => x"8c08ec05",
+7867 => x"0c8c0888",
+7868 => x"05088c08",
+7869 => x"8c050855",
+7870 => x"55841508",
+7871 => x"8415082e",
+7872 => x"0b0b0b85",
+7873 => x"85388c08",
+7874 => x"88050854",
+7875 => x"84140880",
+7876 => x"2e0b0b0b",
+7877 => x"81bc388c",
+7878 => x"08e00508",
+7879 => x"8c08e405",
+7880 => x"08565473",
+7881 => x"8c08c805",
+7882 => x"0c748c08",
+7883 => x"cc050c8c",
+7884 => x"08e80508",
+7885 => x"8c08ec05",
+7886 => x"08575574",
+7887 => x"8c08c005",
+7888 => x"0c758c08",
+7889 => x"c4050c8c",
+7890 => x"08cc0508",
+7891 => x"8c08c405",
+7892 => x"08717131",
+7893 => x"708c08ff",
+7894 => x"bc050c52",
+7895 => x"5556810b",
+7896 => x"8c08ffb4",
+7897 => x"050c8c08",
+7898 => x"ffbc0508",
+7899 => x"8c08cc05",
+7900 => x"08575574",
+7901 => x"76260b0b",
+7902 => x"0b0b8938",
+7903 => x"800b8c08",
+7904 => x"ffb4050c",
+7905 => x"8c08c805",
+7906 => x"088c08c0",
+7907 => x"05087171",
+7908 => x"31708c08",
+7909 => x"ffb8050c",
+7910 => x"8c08ffb8",
+7911 => x"0508708c",
+7912 => x"08ffb405",
+7913 => x"0831708c",
+7914 => x"08ffb805",
+7915 => x"0c525952",
+7916 => x"56548c08",
+7917 => x"ffb80508",
+7918 => x"8c08ffbc",
+7919 => x"05085654",
+7920 => x"738c08f8",
+7921 => x"050c748c",
+7922 => x"08fc050c",
+7923 => x"0b0b0b81",
+7924 => x"bf398c08",
+7925 => x"e805088c",
+7926 => x"08ec0508",
+7927 => x"5755748c",
+7928 => x"08ffac05",
+7929 => x"0c758c08",
+7930 => x"ffb0050c",
+7931 => x"8c08e005",
+7932 => x"088c08e4",
+7933 => x"05085654",
+7934 => x"738c08ff",
+7935 => x"a4050c74",
+7936 => x"8c08ffa8",
+7937 => x"050c8c08",
+7938 => x"ffb00508",
+7939 => x"8c08ffa8",
+7940 => x"05087171",
+7941 => x"31708c08",
+7942 => x"ffa0050c",
+7943 => x"52575581",
+7944 => x"0b8c08ff",
+7945 => x"98050c8c",
+7946 => x"08ffa005",
+7947 => x"088c08ff",
+7948 => x"b0050856",
+7949 => x"54737526",
+7950 => x"0b0b0b0b",
+7951 => x"8938800b",
+7952 => x"8c08ff98",
+7953 => x"050c8c08",
+7954 => x"ffac0508",
+7955 => x"8c08ffa4",
+7956 => x"05087171",
+7957 => x"31708c08",
+7958 => x"ff9c050c",
+7959 => x"8c08ff9c",
+7960 => x"0508708c",
+7961 => x"08ff9805",
+7962 => x"0831708c",
+7963 => x"08ff9c05",
+7964 => x"0c535852",
+7965 => x"55568c08",
+7966 => x"ff9c0508",
+7967 => x"8c08ffa0",
+7968 => x"05085654",
+7969 => x"738c08f8",
+7970 => x"050c748c",
+7971 => x"08fc050c",
+7972 => x"800b8c08",
+7973 => x"f8050824",
+7974 => x"0b0b0b0b",
+7975 => x"ba388c08",
+7976 => x"90050854",
+7977 => x"800b8415",
+7978 => x"0c8c0890",
+7979 => x"05088c08",
+7980 => x"f4050888",
+7981 => x"120c8c08",
+7982 => x"90050857",
+7983 => x"548c08f8",
+7984 => x"05088c08",
+7985 => x"fc050856",
+7986 => x"54738c17",
+7987 => x"0c749017",
+7988 => x"0c0b0b0b",
+7989 => x"80d1398c",
+7990 => x"08900508",
+7991 => x"54810b84",
+7992 => x"150c8c08",
+7993 => x"9005088c",
+7994 => x"08f40508",
+7995 => x"88120c8c",
+7996 => x"08900508",
+7997 => x"8c08d405",
+7998 => x"5858548c",
+7999 => x"08f80508",
+8000 => x"8c08fc05",
+8001 => x"08565473",
+8002 => x"52745375",
+8003 => x"510b0b80",
+8004 => x"cfcb3f8c",
+8005 => x"08d40508",
+8006 => x"8c08d805",
+8007 => x"08565473",
+8008 => x"8c180c74",
+8009 => x"90180c8c",
+8010 => x"08900508",
+8011 => x"548c1408",
+8012 => x"f00a260b",
+8013 => x"0b0b82bb",
+8014 => x"388c0890",
+8015 => x"05088c11",
+8016 => x"08709013",
+8017 => x"08075155",
+8018 => x"5573802e",
+8019 => x"0b0b0b82",
+8020 => x"a2388c08",
+8021 => x"9005088c",
+8022 => x"08900508",
+8023 => x"9011089f",
+8024 => x"2a8c1208",
+8025 => x"10707207",
+8026 => x"8c150c90",
+8027 => x"13081090",
+8028 => x"150c8c08",
+8029 => x"90050888",
+8030 => x"1108ff05",
+8031 => x"88120c53",
+8032 => x"58585557",
+8033 => x"0b0b0bff",
+8034 => x"9e398c08",
+8035 => x"9005088c",
+8036 => x"08880508",
+8037 => x"84110884",
+8038 => x"130c8c08",
+8039 => x"9005088c",
+8040 => x"08f40508",
+8041 => x"88120c8c",
+8042 => x"08900508",
+8043 => x"8c08ff94",
+8044 => x"050c5256",
+8045 => x"548c08e8",
+8046 => x"05088c08",
+8047 => x"ec050857",
+8048 => x"55748c08",
+8049 => x"ff8c050c",
+8050 => x"758c08ff",
+8051 => x"90050c8c",
+8052 => x"08e00508",
+8053 => x"8c08e405",
+8054 => x"08565473",
+8055 => x"8c08ff84",
+8056 => x"050c748c",
+8057 => x"08ff8805",
+8058 => x"0c8c08ff",
+8059 => x"9005088c",
+8060 => x"08ff8805",
+8061 => x"08701270",
+8062 => x"8c08ff80",
+8063 => x"050c5257",
+8064 => x"55810b8c",
+8065 => x"08fef805",
+8066 => x"0c8c08ff",
+8067 => x"8005088c",
+8068 => x"08ff9005",
+8069 => x"08565474",
+8070 => x"74260b0b",
+8071 => x"0b0b8938",
+8072 => x"800b8c08",
+8073 => x"fef8050c",
+8074 => x"8c08ff8c",
+8075 => x"05088c08",
+8076 => x"ff840508",
+8077 => x"7012708c",
+8078 => x"08fefc05",
+8079 => x"0c8c08fe",
+8080 => x"fc05088c",
+8081 => x"08fef805",
+8082 => x"0811708c",
+8083 => x"08fefc05",
+8084 => x"0c535852",
+8085 => x"55568c08",
+8086 => x"fefc0508",
+8087 => x"8c08ff80",
+8088 => x"05088c08",
+8089 => x"ff940508",
+8090 => x"58565473",
+8091 => x"8c170c74",
+8092 => x"90170c8c",
+8093 => x"08900508",
+8094 => x"5483740c",
+8095 => x"8c089005",
+8096 => x"08548c14",
+8097 => x"08f80a26",
+8098 => x"0b0b0b0b",
+8099 => x"87380b0b",
+8100 => x"0b80cf39",
+8101 => x"8c089005",
+8102 => x"088c0890",
+8103 => x"05088c11",
+8104 => x"08800690",
+8105 => x"12088106",
+8106 => x"8c089005",
+8107 => x"088c1108",
+8108 => x"9f2b9012",
+8109 => x"08812a70",
+8110 => x"72078c14",
+8111 => x"08812a70",
+8112 => x"77078c1a",
+8113 => x"0c757207",
+8114 => x"901a0c8c",
+8115 => x"08900508",
+8116 => x"88110881",
+8117 => x"0588120c",
+8118 => x"51575c5f",
+8119 => x"5f5c5a58",
+8120 => x"555b8c08",
+8121 => x"90050870",
+8122 => x"8c08d005",
+8123 => x"0c548c08",
+8124 => x"d0050880",
+8125 => x"0cae3d0d",
+8126 => x"8c0c048c",
+8127 => x"08028c0c",
+8128 => x"7070800b",
+8129 => x"8c08fc05",
+8130 => x"0c8c0888",
+8131 => x"05085170",
+8132 => x"08822e09",
+8133 => x"81060b0b",
+8134 => x"0b0b8838",
+8135 => x"810b8c08",
+8136 => x"fc050c8c",
+8137 => x"08fc0508",
+8138 => x"70800c51",
+8139 => x"50508c0c",
+8140 => x"048c0802",
+8141 => x"8c0c700b",
+8142 => x"0b82f4b8",
+8143 => x"70800c51",
+8144 => x"508c0c04",
+8145 => x"8c08028c",
+8146 => x"0c707080",
+8147 => x"0b8c08fc",
+8148 => x"050c8c08",
+8149 => x"88050851",
+8150 => x"7008842e",
+8151 => x"0981060b",
+8152 => x"0b0b0b88",
+8153 => x"38810b8c",
+8154 => x"08fc050c",
+8155 => x"8c08fc05",
+8156 => x"0870800c",
+8157 => x"5150508c",
+8158 => x"0c048c08",
+8159 => x"028c0c70",
+8160 => x"70800b8c",
+8161 => x"08fc050c",
+8162 => x"8c088805",
+8163 => x"08517008",
+8164 => x"802e0b0b",
+8165 => x"0b0b9738",
+8166 => x"8c088805",
+8167 => x"08517008",
+8168 => x"812e0b0b",
+8169 => x"0b0b8738",
+8170 => x"0b0b0b0b",
+8171 => x"8839810b",
+8172 => x"8c08fc05",
+8173 => x"0c8c08fc",
+8174 => x"05087080",
+8175 => x"0c515050",
+8176 => x"8c0c048c",
+8177 => x"08028c0c",
+8178 => x"e73d0d8c",
+8179 => x"08880508",
+8180 => x"568c088c",
+8181 => x"05088c08",
+8182 => x"90050856",
+8183 => x"54738c08",
+8184 => x"ffb8050c",
+8185 => x"748c08ff",
+8186 => x"bc050c8c",
+8187 => x"08940508",
+8188 => x"8c089805",
+8189 => x"08565473",
+8190 => x"8c08ffb0",
+8191 => x"050c748c",
+8192 => x"08ffb405",
+8193 => x"0c8c08ec",
+8194 => x"0570538c",
+8195 => x"08ffb805",
+8196 => x"70535154",
+8197 => x"0b0b80de",
+8198 => x"c13f8c08",
+8199 => x"d8057053",
+8200 => x"8c08ffb0",
+8201 => x"05705351",
+8202 => x"540b0b80",
+8203 => x"deac3f8c",
+8204 => x"08c40570",
+8205 => x"548c08d8",
+8206 => x"0570548c",
+8207 => x"08ec0570",
+8208 => x"54515154",
+8209 => x"0b0b0bee",
+8210 => x"ea3f8008",
+8211 => x"708c08c0",
+8212 => x"050c8c08",
+8213 => x"c0050853",
+8214 => x"7652540b",
+8215 => x"0b80ccb8",
+8216 => x"3f75800c",
+8217 => x"9b3d0d8c",
+8218 => x"0c048c08",
+8219 => x"028c0ce7",
+8220 => x"3d0d8c08",
+8221 => x"88050856",
+8222 => x"8c088c05",
+8223 => x"088c0890",
+8224 => x"05085654",
+8225 => x"738c08ff",
+8226 => x"b8050c74",
+8227 => x"8c08ffbc",
+8228 => x"050c8c08",
+8229 => x"9405088c",
+8230 => x"08980508",
+8231 => x"5654738c",
+8232 => x"08ffb005",
+8233 => x"0c748c08",
+8234 => x"ffb4050c",
+8235 => x"8c08ec05",
+8236 => x"70538c08",
+8237 => x"ffb80570",
+8238 => x"5351540b",
+8239 => x"0b80dd9a",
+8240 => x"3f8c08d8",
+8241 => x"0570538c",
+8242 => x"08ffb005",
+8243 => x"70535154",
+8244 => x"0b0b80dd",
+8245 => x"853f8c08",
+8246 => x"dc050881",
+8247 => x"328c08dc",
+8248 => x"050c8c08",
+8249 => x"c4057054",
+8250 => x"8c08d805",
+8251 => x"70548c08",
+8252 => x"ec057054",
+8253 => x"5151540b",
+8254 => x"0b0bedb7",
+8255 => x"3f800870",
+8256 => x"8c08c005",
+8257 => x"0c8c08c0",
+8258 => x"05085376",
+8259 => x"52540b0b",
+8260 => x"80cb853f",
+8261 => x"75800c9b",
+8262 => x"3d0d8c0c",
+8263 => x"048c0802",
+8264 => x"8c0cff83",
+8265 => x"3d0d8c08",
+8266 => x"8c05088c",
+8267 => x"08900508",
+8268 => x"5856758c",
+8269 => x"08ffb805",
+8270 => x"0c768c08",
+8271 => x"ffbc050c",
+8272 => x"8c089405",
+8273 => x"088c0898",
+8274 => x"05085856",
+8275 => x"758c08ff",
+8276 => x"b0050c76",
+8277 => x"8c08ffb4",
+8278 => x"050c8c08",
+8279 => x"ec057053",
+8280 => x"8c08ffb8",
+8281 => x"05705351",
+8282 => x"560b0b80",
+8283 => x"dbec3f8c",
+8284 => x"08d80570",
+8285 => x"538c08ff",
+8286 => x"b0057053",
+8287 => x"51560b0b",
+8288 => x"80dbd73f",
+8289 => x"8c08ec05",
+8290 => x"8c08ffac",
+8291 => x"050c8c08",
+8292 => x"d8058c08",
+8293 => x"ffa8050c",
+8294 => x"8c08c405",
+8295 => x"8c08ffa4",
+8296 => x"050c8056",
+8297 => x"8057758c",
+8298 => x"08ff9805",
+8299 => x"0c768c08",
+8300 => x"ff9c050c",
+8301 => x"80568057",
+8302 => x"758c08ff",
+8303 => x"90050c76",
+8304 => x"8c08ff94",
+8305 => x"050c8c08",
+8306 => x"ffac0508",
+8307 => x"510b0b0b",
+8308 => x"9d823f80",
+8309 => x"08567580",
+8310 => x"2e0b0b0b",
+8311 => x"80da388c",
+8312 => x"08ffac05",
+8313 => x"088c08fe",
+8314 => x"c4050c80",
+8315 => x"0b8c08fe",
+8316 => x"c0050c8c",
+8317 => x"08ffac05",
+8318 => x"088c08ff",
+8319 => x"a8050857",
+8320 => x"57841708",
+8321 => x"8417082e",
+8322 => x"0b0b0b0b",
+8323 => x"8938810b",
+8324 => x"8c08fec0",
+8325 => x"050c8c08",
+8326 => x"fec40508",
+8327 => x"8c08fec0",
+8328 => x"05088412",
+8329 => x"0c8c08ff",
+8330 => x"ac05088c",
+8331 => x"08ffa005",
+8332 => x"0c560b0b",
+8333 => x"0b9af139",
+8334 => x"8c08ffa8",
+8335 => x"0508510b",
+8336 => x"0b0b9c90",
+8337 => x"3f800856",
+8338 => x"75802e0b",
+8339 => x"0b0b80da",
+8340 => x"388c08ff",
+8341 => x"a805088c",
+8342 => x"08febc05",
+8343 => x"0c800b8c",
+8344 => x"08feb805",
+8345 => x"0c8c08ff",
+8346 => x"ac05088c",
+8347 => x"08ffa805",
+8348 => x"08575784",
+8349 => x"17088417",
+8350 => x"082e0b0b",
+8351 => x"0b0b8938",
+8352 => x"810b8c08",
+8353 => x"feb8050c",
+8354 => x"8c08febc",
+8355 => x"05088c08",
+8356 => x"feb80508",
+8357 => x"84120c8c",
+8358 => x"08ffa805",
+8359 => x"088c08ff",
+8360 => x"a0050c57",
+8361 => x"0b0b0b99",
+8362 => x"ff398c08",
+8363 => x"ffac0508",
+8364 => x"510b0b0b",
+8365 => x"9ae83f80",
+8366 => x"08567580",
+8367 => x"2e0b0b0b",
+8368 => x"8189388c",
+8369 => x"08ffa805",
+8370 => x"08510b0b",
+8371 => x"0b9a993f",
+8372 => x"80085675",
+8373 => x"802e0b0b",
+8374 => x"0b0b9738",
+8375 => x"0b0b0b99",
+8376 => x"f43f8008",
+8377 => x"708c08ff",
+8378 => x"a0050c56",
+8379 => x"0b0b0b99",
+8380 => x"b7398c08",
+8381 => x"ffac0508",
+8382 => x"8c08feb4",
+8383 => x"050c800b",
+8384 => x"8c08feb0",
+8385 => x"050c8c08",
+8386 => x"ffac0508",
+8387 => x"8c08ffa8",
+8388 => x"05085757",
+8389 => x"84170884",
+8390 => x"17082e0b",
+8391 => x"0b0b0b89",
+8392 => x"38810b8c",
+8393 => x"08feb005",
+8394 => x"0c8c08fe",
+8395 => x"b405088c",
+8396 => x"08feb005",
+8397 => x"0884120c",
+8398 => x"8c08ffac",
+8399 => x"05088c08",
+8400 => x"ffa0050c",
+8401 => x"560b0b0b",
+8402 => x"98de398c",
+8403 => x"08ffa805",
+8404 => x"08510b0b",
+8405 => x"0b99c73f",
+8406 => x"80085675",
+8407 => x"802e0b0b",
+8408 => x"0b818938",
+8409 => x"8c08ffac",
+8410 => x"0508510b",
+8411 => x"0b0b98f8",
+8412 => x"3f800856",
+8413 => x"75802e0b",
+8414 => x"0b0b0b97",
+8415 => x"380b0b0b",
+8416 => x"98d33f80",
+8417 => x"08708c08",
+8418 => x"ffa0050c",
+8419 => x"560b0b0b",
+8420 => x"9896398c",
+8421 => x"08ffa805",
+8422 => x"088c08fe",
+8423 => x"ac050c80",
+8424 => x"0b8c08fe",
+8425 => x"a8050c8c",
+8426 => x"08ffac05",
+8427 => x"088c08ff",
+8428 => x"a8050857",
+8429 => x"57841708",
+8430 => x"8417082e",
+8431 => x"0b0b0b0b",
+8432 => x"8938810b",
+8433 => x"8c08fea8",
+8434 => x"050c8c08",
+8435 => x"feac0508",
+8436 => x"8c08fea8",
+8437 => x"05088412",
+8438 => x"0c8c08ff",
+8439 => x"a805088c",
+8440 => x"08ffa005",
+8441 => x"0c570b0b",
+8442 => x"0b97bd39",
+8443 => x"8c08ffac",
+8444 => x"0508510b",
+8445 => x"0b0b97f0",
+8446 => x"3f800856",
+8447 => x"75802e0b",
+8448 => x"0b0b80da",
+8449 => x"388c08ff",
+8450 => x"ac05088c",
+8451 => x"08fea405",
+8452 => x"0c800b8c",
+8453 => x"08fea005",
+8454 => x"0c8c08ff",
+8455 => x"ac05088c",
+8456 => x"08ffa805",
+8457 => x"08575784",
+8458 => x"17088417",
+8459 => x"082e0b0b",
+8460 => x"0b0b8938",
+8461 => x"810b8c08",
+8462 => x"fea0050c",
+8463 => x"8c08fea4",
+8464 => x"05088c08",
+8465 => x"fea00508",
+8466 => x"84120c8c",
+8467 => x"08ffac05",
+8468 => x"088c08ff",
+8469 => x"a0050c56",
+8470 => x"0b0b0b96",
+8471 => x"cb398c08",
+8472 => x"ffa80508",
+8473 => x"510b0b0b",
+8474 => x"96fe3f80",
+8475 => x"08567580",
+8476 => x"2e0b0b0b",
+8477 => x"80da388c",
+8478 => x"08ffa805",
+8479 => x"088c08fe",
+8480 => x"9c050c80",
+8481 => x"0b8c08fe",
+8482 => x"98050c8c",
+8483 => x"08ffac05",
+8484 => x"088c08ff",
+8485 => x"a8050857",
+8486 => x"57841708",
+8487 => x"8417082e",
+8488 => x"0b0b0b0b",
+8489 => x"8938810b",
+8490 => x"8c08fe98",
+8491 => x"050c8c08",
+8492 => x"fe9c0508",
+8493 => x"8c08fe98",
+8494 => x"05088412",
+8495 => x"0c8c08ff",
+8496 => x"a805088c",
+8497 => x"08ffa005",
+8498 => x"0c570b0b",
+8499 => x"0b95d939",
+8500 => x"8c08ffac",
+8501 => x"05089011",
+8502 => x"088c08ff",
+8503 => x"8c050c8c",
+8504 => x"08ffac05",
+8505 => x"088c1108",
+8506 => x"802a5959",
+8507 => x"5680778c",
+8508 => x"08ff8805",
+8509 => x"0c8c08ff",
+8510 => x"a8050890",
+8511 => x"11088c08",
+8512 => x"ff84050c",
+8513 => x"8c08ffa8",
+8514 => x"05088c11",
+8515 => x"08802a5a",
+8516 => x"5a515680",
+8517 => x"778c08ff",
+8518 => x"80050c8c",
+8519 => x"08ff8405",
+8520 => x"085a5680",
+8521 => x"0b8c08ff",
+8522 => x"8c050858",
+8523 => x"58800b8c",
+8524 => x"08fef005",
+8525 => x"5b567554",
+8526 => x"76557752",
+8527 => x"78537951",
+8528 => x"0b0b0bbb",
+8529 => x"b23f8c08",
+8530 => x"fef00508",
+8531 => x"8c08fef4",
+8532 => x"05085856",
+8533 => x"758c08fe",
+8534 => x"f8050c76",
+8535 => x"8c08fefc",
+8536 => x"050c8c08",
+8537 => x"ff800508",
+8538 => x"59800b8c",
+8539 => x"08ff8c05",
+8540 => x"08585880",
+8541 => x"0b8c08fe",
+8542 => x"e8055b56",
+8543 => x"75547655",
+8544 => x"77527853",
+8545 => x"79510b0b",
+8546 => x"0bbaec3f",
+8547 => x"8c08fee8",
+8548 => x"05088c08",
+8549 => x"feec0508",
+8550 => x"5856758c",
+8551 => x"08fef005",
+8552 => x"0c768c08",
+8553 => x"fef4050c",
+8554 => x"8c08ff84",
+8555 => x"05085980",
+8556 => x"0b8c08ff",
+8557 => x"88050858",
+8558 => x"58800b8c",
+8559 => x"08fee005",
+8560 => x"5b567554",
+8561 => x"76557752",
+8562 => x"78537951",
+8563 => x"0b0b0bba",
+8564 => x"a63f8c08",
+8565 => x"fee00508",
+8566 => x"8c08fee4",
+8567 => x"05085856",
+8568 => x"758c08fe",
+8569 => x"e8050c76",
+8570 => x"8c08feec",
+8571 => x"050c8c08",
+8572 => x"ff800508",
+8573 => x"59800b8c",
+8574 => x"08ff8805",
+8575 => x"08585880",
+8576 => x"0b8c08fe",
+8577 => x"d8055b56",
+8578 => x"75547655",
+8579 => x"77527853",
+8580 => x"79510b0b",
+8581 => x"0bb9e03f",
+8582 => x"8c08fed8",
+8583 => x"05088c08",
+8584 => x"fedc0508",
+8585 => x"5856758c",
+8586 => x"08fee005",
+8587 => x"0c768c08",
+8588 => x"fee4050c",
+8589 => x"80568057",
+8590 => x"758c08fe",
+8591 => x"d8050c76",
+8592 => x"8c08fedc",
+8593 => x"050c8056",
+8594 => x"8057758c",
+8595 => x"08fed005",
+8596 => x"0c768c08",
+8597 => x"fed4050c",
+8598 => x"8c08fef0",
+8599 => x"05088c08",
+8600 => x"fef40508",
+8601 => x"5856758c",
+8602 => x"08fe9005",
+8603 => x"0c768c08",
+8604 => x"fe94050c",
+8605 => x"8c08fee8",
+8606 => x"05088c08",
+8607 => x"feec0508",
+8608 => x"5856758c",
+8609 => x"08fe8805",
+8610 => x"0c768c08",
+8611 => x"fe8c050c",
+8612 => x"8c08fe94",
+8613 => x"05088c08",
+8614 => x"fe8c0508",
+8615 => x"7012708c",
+8616 => x"08fe8405",
+8617 => x"0c525757",
+8618 => x"810b8c08",
+8619 => x"fdfc050c",
+8620 => x"8c08fe84",
+8621 => x"05088c08",
+8622 => x"fe940508",
+8623 => x"57577577",
+8624 => x"260b0b0b",
+8625 => x"0b893880",
+8626 => x"0b8c08fd",
+8627 => x"fc050c8c",
+8628 => x"08fe9005",
+8629 => x"088c08fe",
+8630 => x"88050870",
+8631 => x"12708c08",
+8632 => x"fe80050c",
+8633 => x"8c08fe80",
+8634 => x"05088c08",
+8635 => x"fdfc0508",
+8636 => x"11708c08",
+8637 => x"fe80050c",
+8638 => x"53515257",
+8639 => x"578c08fe",
+8640 => x"8005088c",
+8641 => x"08fe8405",
+8642 => x"08585675",
+8643 => x"8c08fec8",
+8644 => x"050c768c",
+8645 => x"08fecc05",
+8646 => x"0c8c08fe",
+8647 => x"f005088c",
+8648 => x"08fec805",
+8649 => x"08260b0b",
+8650 => x"0b0bb038",
+8651 => x"8c08fef0",
+8652 => x"05088c08",
+8653 => x"fec80508",
+8654 => x"2e098106",
+8655 => x"0b0b0b81",
+8656 => x"d1388c08",
+8657 => x"fef40508",
+8658 => x"8c08fecc",
+8659 => x"0508260b",
+8660 => x"0b0b0b87",
+8661 => x"380b0b0b",
+8662 => x"81b8398c",
+8663 => x"08fed805",
+8664 => x"088c08fe",
+8665 => x"dc050858",
+8666 => x"56758c08",
+8667 => x"fdf4050c",
+8668 => x"768c08fd",
+8669 => x"f8050c81",
+8670 => x"56805775",
+8671 => x"8c08fdec",
+8672 => x"050c768c",
+8673 => x"08fdf005",
+8674 => x"0c8c08fd",
+8675 => x"f805088c",
+8676 => x"08fdf005",
+8677 => x"08701270",
+8678 => x"8c08fde8",
+8679 => x"050c5257",
+8680 => x"57810b8c",
+8681 => x"08fde005",
+8682 => x"0c8c08fd",
+8683 => x"e805088c",
+8684 => x"08fdf805",
+8685 => x"08575775",
+8686 => x"77260b0b",
+8687 => x"0b0b8938",
+8688 => x"800b8c08",
+8689 => x"fde0050c",
+8690 => x"8c08fdf4",
+8691 => x"05088c08",
+8692 => x"fdec0508",
+8693 => x"7012708c",
+8694 => x"08fde405",
+8695 => x"0c8c08fd",
+8696 => x"e405088c",
+8697 => x"08fde005",
+8698 => x"0811708c",
+8699 => x"08fde405",
+8700 => x"0c535152",
+8701 => x"57578c08",
+8702 => x"fde40508",
+8703 => x"8c08fde8",
+8704 => x"05085856",
+8705 => x"758c08fe",
+8706 => x"d8050c76",
+8707 => x"8c08fedc",
+8708 => x"050c8c08",
+8709 => x"fecc0508",
+8710 => x"57807780",
+8711 => x"2b8c08fe",
+8712 => x"f0050c56",
+8713 => x"800b8c08",
+8714 => x"fef4050c",
+8715 => x"8c08fef8",
+8716 => x"05088c08",
+8717 => x"fefc0508",
+8718 => x"5856758c",
+8719 => x"08fdd805",
+8720 => x"0c768c08",
+8721 => x"fddc050c",
+8722 => x"8c08fef0",
+8723 => x"05088c08",
+8724 => x"fef40508",
+8725 => x"5856758c",
+8726 => x"08fdd005",
+8727 => x"0c768c08",
+8728 => x"fdd4050c",
+8729 => x"8c08fddc",
+8730 => x"05088c08",
+8731 => x"fdd40508",
+8732 => x"7012708c",
+8733 => x"08fdcc05",
+8734 => x"0c525757",
+8735 => x"810b8c08",
+8736 => x"fdc4050c",
+8737 => x"8c08fdcc",
+8738 => x"05088c08",
+8739 => x"fddc0508",
+8740 => x"57577577",
+8741 => x"260b0b0b",
+8742 => x"0b893880",
+8743 => x"0b8c08fd",
+8744 => x"c4050c8c",
+8745 => x"08fdd805",
+8746 => x"088c08fd",
+8747 => x"d0050870",
+8748 => x"12708c08",
+8749 => x"fdc8050c",
+8750 => x"8c08fdc8",
+8751 => x"05088c08",
+8752 => x"fdc40508",
+8753 => x"11708c08",
+8754 => x"fdc8050c",
+8755 => x"53515257",
+8756 => x"578c08fd",
+8757 => x"c805088c",
+8758 => x"08fdcc05",
+8759 => x"08585675",
+8760 => x"8c08fed0",
+8761 => x"050c768c",
+8762 => x"08fed405",
+8763 => x"0c8c08fe",
+8764 => x"f805088c",
+8765 => x"08fed005",
+8766 => x"08260b0b",
+8767 => x"0b0bb038",
+8768 => x"8c08fef8",
+8769 => x"05088c08",
+8770 => x"fed00508",
+8771 => x"2e098106",
+8772 => x"0b0b0b81",
+8773 => x"d1388c08",
+8774 => x"fefc0508",
+8775 => x"8c08fed4",
+8776 => x"0508260b",
+8777 => x"0b0b0b87",
+8778 => x"380b0b0b",
+8779 => x"81b8398c",
+8780 => x"08fed805",
+8781 => x"088c08fe",
+8782 => x"dc050858",
+8783 => x"56758c08",
+8784 => x"fdbc050c",
+8785 => x"768c08fd",
+8786 => x"c0050c80",
+8787 => x"56815775",
+8788 => x"8c08fdb4",
+8789 => x"050c768c",
+8790 => x"08fdb805",
+8791 => x"0c8c08fd",
+8792 => x"c005088c",
+8793 => x"08fdb805",
+8794 => x"08701270",
+8795 => x"8c08fdb0",
+8796 => x"050c5257",
+8797 => x"57810b8c",
+8798 => x"08fda805",
+8799 => x"0c8c08fd",
+8800 => x"b005088c",
+8801 => x"08fdc005",
+8802 => x"08575775",
+8803 => x"77260b0b",
+8804 => x"0b0b8938",
+8805 => x"800b8c08",
+8806 => x"fda8050c",
+8807 => x"8c08fdbc",
+8808 => x"05088c08",
+8809 => x"fdb40508",
+8810 => x"7012708c",
+8811 => x"08fdac05",
+8812 => x"0c8c08fd",
+8813 => x"ac05088c",
+8814 => x"08fda805",
+8815 => x"0811708c",
+8816 => x"08fdac05",
+8817 => x"0c535152",
+8818 => x"57578c08",
+8819 => x"fdac0508",
+8820 => x"8c08fdb0",
+8821 => x"05085856",
+8822 => x"758c08fe",
+8823 => x"d8050c76",
+8824 => x"8c08fedc",
+8825 => x"050c8c08",
+8826 => x"fec80508",
+8827 => x"802a708c",
+8828 => x"08fda405",
+8829 => x"0c578070",
+8830 => x"8c08fda0",
+8831 => x"050c568c",
+8832 => x"08fda005",
+8833 => x"088c08fd",
+8834 => x"a4050858",
+8835 => x"56758c08",
+8836 => x"fda0050c",
+8837 => x"768c08fd",
+8838 => x"a4050c8c",
+8839 => x"08fee005",
+8840 => x"088c08fe",
+8841 => x"e4050858",
+8842 => x"56758c08",
+8843 => x"fd98050c",
+8844 => x"768c08fd",
+8845 => x"9c050c8c",
+8846 => x"08fda405",
+8847 => x"088c08fd",
+8848 => x"9c050870",
+8849 => x"12708c08",
+8850 => x"fd94050c",
+8851 => x"52575781",
+8852 => x"0b8c08fd",
+8853 => x"8c050c8c",
+8854 => x"08fd9405",
+8855 => x"088c08fd",
+8856 => x"a4050857",
+8857 => x"57757726",
+8858 => x"0b0b0b0b",
+8859 => x"8938800b",
+8860 => x"8c08fd8c",
+8861 => x"050c8c08",
+8862 => x"fda00508",
+8863 => x"8c08fd98",
+8864 => x"05087012",
+8865 => x"708c08fd",
+8866 => x"90050c8c",
+8867 => x"08fd9005",
+8868 => x"088c08fd",
+8869 => x"8c050811",
+8870 => x"708c08fd",
+8871 => x"90050c53",
+8872 => x"51525757",
+8873 => x"8c08fed8",
+8874 => x"05088c08",
+8875 => x"fedc0508",
+8876 => x"5856758c",
+8877 => x"08fd8405",
+8878 => x"0c768c08",
+8879 => x"fd88050c",
+8880 => x"8c08fd88",
+8881 => x"05088c08",
+8882 => x"fd940508",
+8883 => x"7012708c",
+8884 => x"08fd8005",
+8885 => x"0c525757",
+8886 => x"810b8c08",
+8887 => x"fcf8050c",
+8888 => x"8c08fd80",
+8889 => x"05088c08",
+8890 => x"fd880508",
+8891 => x"57577577",
+8892 => x"260b0b0b",
+8893 => x"0b893880",
+8894 => x"0b8c08fc",
+8895 => x"f8050c8c",
+8896 => x"08fd8405",
+8897 => x"088c08fd",
+8898 => x"90050870",
+8899 => x"12708c08",
+8900 => x"fcfc050c",
+8901 => x"8c08fcfc",
+8902 => x"05088c08",
+8903 => x"fcf80508",
+8904 => x"11708c08",
+8905 => x"fcfc050c",
+8906 => x"53515257",
+8907 => x"578c08fc",
+8908 => x"fc05088c",
+8909 => x"08fd8005",
+8910 => x"08585675",
+8911 => x"8c08fed8",
+8912 => x"050c768c",
+8913 => x"08fedc05",
+8914 => x"0c8c08fe",
+8915 => x"d805088c",
+8916 => x"08fedc05",
+8917 => x"08585675",
+8918 => x"8c08ff90",
+8919 => x"050c768c",
+8920 => x"08ff9405",
+8921 => x"0c8c08fe",
+8922 => x"d005088c",
+8923 => x"08fed405",
+8924 => x"08585675",
+8925 => x"8c08ff98",
+8926 => x"050c768c",
+8927 => x"08ff9c05",
+8928 => x"0c8c08ff",
+8929 => x"a405088c",
+8930 => x"08ffac05",
+8931 => x"088c08ff",
+8932 => x"a8050888",
+8933 => x"12088812",
+8934 => x"08058411",
+8935 => x"88150c8c",
+8936 => x"08ffa405",
+8937 => x"088c08fc",
+8938 => x"f4050c51",
+8939 => x"58585880",
+8940 => x"0b8c08fc",
+8941 => x"f0050c8c",
+8942 => x"08ffac05",
+8943 => x"088c08ff",
+8944 => x"a8050857",
+8945 => x"57841708",
+8946 => x"8417082e",
+8947 => x"0b0b0b0b",
+8948 => x"8938810b",
+8949 => x"8c08fcf0",
+8950 => x"050c8c08",
+8951 => x"fcf40508",
+8952 => x"8c08fcf0",
+8953 => x"05088412",
+8954 => x"0c578c08",
+8955 => x"ff900508",
+8956 => x"f80a260b",
+8957 => x"0b0b0b87",
+8958 => x"380b0b0b",
+8959 => x"81ae398c",
+8960 => x"08ffa405",
+8961 => x"08881108",
+8962 => x"81058812",
+8963 => x"0c8c08ff",
+8964 => x"90050880",
+8965 => x"068c08ff",
+8966 => x"94050881",
+8967 => x"06705259",
+8968 => x"51567580",
+8969 => x"2e0b0b0b",
+8970 => x"80cf388c",
+8971 => x"08ff9805",
+8972 => x"089f2b8c",
+8973 => x"08ff9c05",
+8974 => x"08812a70",
+8975 => x"72078c08",
+8976 => x"ff980508",
+8977 => x"812a5959",
+8978 => x"5959758c",
+8979 => x"08ff9805",
+8980 => x"0c768c08",
+8981 => x"ff9c050c",
+8982 => x"8c08ff98",
+8983 => x"0508810a",
+8984 => x"078c08ff",
+8985 => x"9c050880",
+8986 => x"07585675",
+8987 => x"8c08ff98",
+8988 => x"050c768c",
+8989 => x"08ff9c05",
+8990 => x"0c8c08ff",
+8991 => x"9005089f",
+8992 => x"2b8c08ff",
+8993 => x"94050881",
+8994 => x"2a707207",
+8995 => x"8c08ff90",
+8996 => x"0508812a",
+8997 => x"59595959",
+8998 => x"758c08ff",
+8999 => x"90050c76",
+9000 => x"8c08ff94",
+9001 => x"050c0b0b",
+9002 => x"0bfebf39",
+9003 => x"8c08ff90",
+9004 => x"0508f00a",
+9005 => x"260b0b0b",
+9006 => x"81a1388c",
+9007 => x"08ffa405",
+9008 => x"08881108",
+9009 => x"ff058812",
+9010 => x"0c8c08ff",
+9011 => x"9405089f",
+9012 => x"2a8c08ff",
+9013 => x"90050810",
+9014 => x"7072078c",
+9015 => x"08ff9405",
+9016 => x"08105b53",
+9017 => x"5a5a5675",
+9018 => x"8c08ff90",
+9019 => x"050c768c",
+9020 => x"08ff9405",
+9021 => x"0c800b8c",
+9022 => x"08ff9805",
+9023 => x"08240b0b",
+9024 => x"0b0b8738",
+9025 => x"0b0b0b0b",
+9026 => x"a1398c08",
+9027 => x"ff900508",
+9028 => x"80078c08",
+9029 => x"ff940508",
+9030 => x"81075856",
+9031 => x"758c08ff",
+9032 => x"90050c76",
+9033 => x"8c08ff94",
+9034 => x"050c8c08",
+9035 => x"ff9c0508",
+9036 => x"9f2a8c08",
+9037 => x"ff980508",
+9038 => x"10707207",
+9039 => x"8c08ff9c",
+9040 => x"0508105a",
+9041 => x"58595975",
+9042 => x"8c08ff98",
+9043 => x"050c768c",
+9044 => x"08ff9c05",
+9045 => x"0c0b0b0b",
+9046 => x"fed2398c",
+9047 => x"08ff9005",
+9048 => x"08800670",
+9049 => x"8c08fce8",
+9050 => x"050c8c08",
+9051 => x"ff940508",
+9052 => x"81ff0670",
+9053 => x"8c08fcec",
+9054 => x"050c5856",
+9055 => x"8c08fce8",
+9056 => x"05088c08",
+9057 => x"fcec0508",
+9058 => x"5856758c",
+9059 => x"08fce805",
+9060 => x"0c768c08",
+9061 => x"fcec050c",
+9062 => x"8c08fce8",
+9063 => x"05085776",
+9064 => x"0b0b0b83",
+9065 => x"d0388c08",
+9066 => x"fcec0508",
+9067 => x"56758180",
+9068 => x"2e098106",
+9069 => x"0b0b0b83",
+9070 => x"bc388c08",
+9071 => x"ff900508",
+9072 => x"982b8c08",
+9073 => x"ff940508",
+9074 => x"882a7072",
+9075 => x"078c08ff",
+9076 => x"90050888",
+9077 => x"2a718106",
+9078 => x"51595959",
+9079 => x"5975802e",
+9080 => x"0b0b0b81",
+9081 => x"bf388c08",
+9082 => x"ff900508",
+9083 => x"8c08ff94",
+9084 => x"05085856",
+9085 => x"758c08fc",
+9086 => x"e0050c76",
+9087 => x"8c08fce4",
+9088 => x"050c8056",
+9089 => x"81805775",
+9090 => x"8c08fcd8",
+9091 => x"050c768c",
+9092 => x"08fcdc05",
+9093 => x"0c8c08fc",
+9094 => x"e405088c",
+9095 => x"08fcdc05",
+9096 => x"08701270",
+9097 => x"8c08fcd4",
+9098 => x"050c5257",
+9099 => x"57810b8c",
+9100 => x"08fccc05",
+9101 => x"0c8c08fc",
+9102 => x"d405088c",
+9103 => x"08fce405",
+9104 => x"08575775",
+9105 => x"77260b0b",
+9106 => x"0b0b8938",
+9107 => x"800b8c08",
+9108 => x"fccc050c",
+9109 => x"8c08fce0",
+9110 => x"05088c08",
+9111 => x"fcd80508",
+9112 => x"7012708c",
+9113 => x"08fcd005",
+9114 => x"0c8c08fc",
+9115 => x"d005088c",
+9116 => x"08fccc05",
+9117 => x"0811708c",
+9118 => x"08fcd005",
+9119 => x"0c535152",
+9120 => x"57578c08",
+9121 => x"fcd00508",
+9122 => x"8c08fcd4",
+9123 => x"05085856",
+9124 => x"758c08ff",
+9125 => x"90050c76",
+9126 => x"8c08ff94",
+9127 => x"050c0b0b",
+9128 => x"0b81d239",
+9129 => x"8c08ff98",
+9130 => x"0508708c",
+9131 => x"08ff9c05",
+9132 => x"08075156",
+9133 => x"75802e0b",
+9134 => x"0b0b81b9",
+9135 => x"388c08ff",
+9136 => x"9005088c",
+9137 => x"08ff9405",
+9138 => x"08585675",
+9139 => x"8c08fcc4",
+9140 => x"050c768c",
+9141 => x"08fcc805",
+9142 => x"0c805681",
+9143 => x"8057758c",
+9144 => x"08fcbc05",
+9145 => x"0c768c08",
+9146 => x"fcc0050c",
+9147 => x"8c08fcc8",
+9148 => x"05088c08",
+9149 => x"fcc00508",
+9150 => x"7012708c",
+9151 => x"08fcb805",
+9152 => x"0c525757",
+9153 => x"810b8c08",
+9154 => x"fcb0050c",
+9155 => x"8c08fcb8",
+9156 => x"05088c08",
+9157 => x"fcc80508",
+9158 => x"57577577",
+9159 => x"260b0b0b",
+9160 => x"0b893880",
+9161 => x"0b8c08fc",
+9162 => x"b0050c8c",
+9163 => x"08fcc405",
+9164 => x"088c08fc",
+9165 => x"bc050870",
+9166 => x"12708c08",
+9167 => x"fcb4050c",
+9168 => x"8c08fcb4",
+9169 => x"05088c08",
+9170 => x"fcb00508",
+9171 => x"11708c08",
+9172 => x"fcb4050c",
+9173 => x"53515257",
+9174 => x"578c08fc",
+9175 => x"b405088c",
+9176 => x"08fcb805",
+9177 => x"08585675",
+9178 => x"8c08ff90",
+9179 => x"050c768c",
+9180 => x"08ff9405",
+9181 => x"0c8c08ff",
+9182 => x"a4050856",
+9183 => x"8c08ff90",
+9184 => x"05088c08",
+9185 => x"ff940508",
+9186 => x"5957768c",
+9187 => x"170c7790",
+9188 => x"170c8c08",
+9189 => x"ffa40508",
+9190 => x"5683760c",
+9191 => x"8c08ffa4",
+9192 => x"05088c08",
+9193 => x"ffa0050c",
+9194 => x"8c08ffa0",
+9195 => x"0508708c",
+9196 => x"08c0050c",
+9197 => x"8c08c005",
+9198 => x"08538c08",
+9199 => x"88050852",
+9200 => x"560b0b0b",
+9201 => x"add23f8c",
+9202 => x"08880508",
+9203 => x"800c80ff",
+9204 => x"3d0d8c0c",
+9205 => x"048c0802",
+9206 => x"8c0c700b",
+9207 => x"0b82f4b8",
+9208 => x"70800c51",
+9209 => x"508c0c04",
+9210 => x"8c08028c",
+9211 => x"0c707080",
+9212 => x"0b8c08fc",
+9213 => x"050c8c08",
+9214 => x"88050851",
+9215 => x"7008822e",
+9216 => x"0981060b",
+9217 => x"0b0b0b88",
+9218 => x"38810b8c",
+9219 => x"08fc050c",
+9220 => x"8c08fc05",
+9221 => x"0870800c",
+9222 => x"5150508c",
+9223 => x"0c048c08",
+9224 => x"028c0c70",
+9225 => x"70800b8c",
+9226 => x"08fc050c",
+9227 => x"8c088805",
+9228 => x"08517008",
+9229 => x"842e0981",
+9230 => x"060b0b0b",
+9231 => x"0b883881",
+9232 => x"0b8c08fc",
+9233 => x"050c8c08",
+9234 => x"fc050870",
+9235 => x"800c5150",
+9236 => x"508c0c04",
+9237 => x"8c08028c",
+9238 => x"0c707080",
+9239 => x"0b8c08fc",
+9240 => x"050c8c08",
+9241 => x"88050851",
+9242 => x"7008802e",
+9243 => x"0b0b0b0b",
+9244 => x"97388c08",
+9245 => x"88050851",
+9246 => x"7008812e",
+9247 => x"0b0b0b0b",
+9248 => x"87380b0b",
+9249 => x"0b0b8839",
+9250 => x"810b8c08",
+9251 => x"fc050c8c",
+9252 => x"08fc0508",
+9253 => x"70800c51",
+9254 => x"50508c0c",
+9255 => x"048c0802",
+9256 => x"8c0cffbc",
+9257 => x"3d0d8c08",
+9258 => x"8c05088c",
+9259 => x"08900508",
+9260 => x"5553728c",
+9261 => x"08cc050c",
+9262 => x"738c08d0",
+9263 => x"050c8c08",
+9264 => x"9405088c",
+9265 => x"08980508",
+9266 => x"5553728c",
+9267 => x"08c4050c",
+9268 => x"738c08c8",
+9269 => x"050c8c08",
+9270 => x"ec057053",
+9271 => x"8c08cc05",
+9272 => x"70535153",
+9273 => x"0b0b0bbc",
+9274 => x"f13f8c08",
+9275 => x"d8057053",
+9276 => x"8c08c405",
+9277 => x"70535153",
+9278 => x"0b0b0bbc",
+9279 => x"dd3f8c08",
+9280 => x"ec058c08",
+9281 => x"c0050c8c",
+9282 => x"08d8058c",
+9283 => x"08ffbc05",
+9284 => x"0c8c08c0",
+9285 => x"0508510b",
+9286 => x"0b0b9084",
+9287 => x"3f800853",
+9288 => x"72802e0b",
+9289 => x"0b0b0b92",
+9290 => x"388c08c0",
+9291 => x"05088c08",
+9292 => x"ffb8050c",
+9293 => x"0b0b0b8e",
+9294 => x"bb398c08",
+9295 => x"ffbc0508",
+9296 => x"510b0b0b",
+9297 => x"8fda3f80",
+9298 => x"08537280",
+9299 => x"2e0b0b0b",
+9300 => x"0b93388c",
+9301 => x"08ffbc05",
+9302 => x"088c08ff",
+9303 => x"b8050c0b",
+9304 => x"0b0b8e90",
+9305 => x"398c08c0",
+9306 => x"05088c08",
+9307 => x"c005088c",
+9308 => x"08ffbc05",
+9309 => x"08841208",
+9310 => x"84120832",
+9311 => x"84140c8c",
+9312 => x"08c00508",
+9313 => x"54555555",
+9314 => x"0b0b0b8e",
+9315 => x"dd3f8008",
+9316 => x"53720b0b",
+9317 => x"0b0b9d38",
+9318 => x"8c08c005",
+9319 => x"08510b0b",
+9320 => x"0b8e913f",
+9321 => x"80085372",
+9322 => x"0b0b0b0b",
+9323 => x"87380b0b",
+9324 => x"0b80c339",
+9325 => x"8c08c005",
+9326 => x"088c08ff",
+9327 => x"bc050854",
+9328 => x"54730873",
+9329 => x"082e0981",
+9330 => x"060b0b0b",
+9331 => x"0b97380b",
+9332 => x"0b0b8dcd",
+9333 => x"3f800870",
+9334 => x"8c08ffb8",
+9335 => x"050c530b",
+9336 => x"0b0b8d90",
+9337 => x"398c08c0",
+9338 => x"05088c08",
+9339 => x"ffb8050c",
+9340 => x"0b0b0b8c",
+9341 => x"ff398c08",
+9342 => x"ffbc0508",
+9343 => x"510b0b0b",
+9344 => x"8de83f80",
+9345 => x"08537280",
+9346 => x"2e0b0b0b",
+9347 => x"0baf388c",
+9348 => x"08c00508",
+9349 => x"53805480",
+9350 => x"55738c14",
+9351 => x"0c749014",
+9352 => x"0c8c08c0",
+9353 => x"05085380",
+9354 => x"0b88140c",
+9355 => x"8c08c005",
+9356 => x"088c08ff",
+9357 => x"b8050c0b",
+9358 => x"0b0b8cb8",
+9359 => x"398c08ff",
+9360 => x"bc050851",
+9361 => x"0b0b0b8c",
+9362 => x"eb3f8008",
+9363 => x"5372802e",
+9364 => x"0b0b0b0b",
+9365 => x"9b388c08",
+9366 => x"c0050853",
+9367 => x"84730c8c",
+9368 => x"08c00508",
+9369 => x"8c08ffb8",
+9370 => x"050c0b0b",
+9371 => x"0b8c8539",
+9372 => x"8c08c005",
+9373 => x"088c08c0",
+9374 => x"05088c08",
+9375 => x"ffbc0508",
+9376 => x"88120888",
+9377 => x"12083188",
+9378 => x"140c8c08",
+9379 => x"c0050851",
+9380 => x"55555590",
+9381 => x"13088c14",
+9382 => x"08545472",
+9383 => x"8c08ffa8",
+9384 => x"050c738c",
+9385 => x"08ffac05",
+9386 => x"0c8c08ff",
+9387 => x"bc050853",
+9388 => x"9013088c",
+9389 => x"14085454",
+9390 => x"728c08ff",
+9391 => x"a0050c73",
+9392 => x"8c08ffa4",
+9393 => x"050c8c08",
+9394 => x"ffa00508",
+9395 => x"8c08ffa8",
+9396 => x"0508260b",
+9397 => x"0b0b0bb0",
+9398 => x"388c08ff",
+9399 => x"a005088c",
+9400 => x"08ffa805",
+9401 => x"082e0981",
+9402 => x"060b0b0b",
+9403 => x"81e9388c",
+9404 => x"08ffa405",
+9405 => x"088c08ff",
+9406 => x"ac050826",
+9407 => x"0b0b0b0b",
+9408 => x"87380b0b",
+9409 => x"0b81d039",
+9410 => x"8c08ffa8",
+9411 => x"05088c08",
+9412 => x"ffac0508",
+9413 => x"5553728c",
+9414 => x"08ff9005",
+9415 => x"0c738c08",
+9416 => x"ff94050c",
+9417 => x"8c08ff90",
+9418 => x"05088c08",
+9419 => x"ff940508",
+9420 => x"5553728c",
+9421 => x"08ff8805",
+9422 => x"0c738c08",
+9423 => x"ff8c050c",
+9424 => x"8c08ff8c",
+9425 => x"05088c08",
+9426 => x"ff940508",
+9427 => x"7012708c",
+9428 => x"08ff8405",
+9429 => x"0c525454",
+9430 => x"810b8c08",
+9431 => x"fefc050c",
+9432 => x"8c08ff84",
+9433 => x"05088c08",
+9434 => x"ff8c0508",
+9435 => x"54547274",
+9436 => x"260b0b0b",
+9437 => x"0b893880",
+9438 => x"0b8c08fe",
+9439 => x"fc050c8c",
+9440 => x"08ff8805",
+9441 => x"088c08ff",
+9442 => x"90050870",
+9443 => x"12708c08",
+9444 => x"ff80050c",
+9445 => x"8c08ff80",
+9446 => x"05088c08",
+9447 => x"fefc0508",
+9448 => x"11708c08",
+9449 => x"ff80050c",
+9450 => x"53515254",
+9451 => x"548c08ff",
+9452 => x"8005088c",
+9453 => x"08ff8405",
+9454 => x"08555372",
+9455 => x"8c08ffa8",
+9456 => x"050c738c",
+9457 => x"08ffac05",
+9458 => x"0c8c08c0",
+9459 => x"05088811",
+9460 => x"08ff0588",
+9461 => x"120c5388",
+9462 => x"0a538054",
+9463 => x"728c08ff",
+9464 => x"b0050c73",
+9465 => x"8c08ffb4",
+9466 => x"050c8053",
+9467 => x"8054728c",
+9468 => x"08ff9805",
+9469 => x"0c738c08",
+9470 => x"ff9c050c",
+9471 => x"8c08ffb0",
+9472 => x"0508708c",
+9473 => x"08ffb405",
+9474 => x"08075153",
+9475 => x"72802e0b",
+9476 => x"0b0b849f",
+9477 => x"388c08ff",
+9478 => x"a005088c",
+9479 => x"08ffa805",
+9480 => x"08260b0b",
+9481 => x"0b829838",
+9482 => x"8c08ffa0",
+9483 => x"05088c08",
+9484 => x"ffa80508",
+9485 => x"2e098106",
+9486 => x"0b0b0b0b",
+9487 => x"94388c08",
+9488 => x"ffa40508",
+9489 => x"8c08ffac",
+9490 => x"0508260b",
+9491 => x"0b0b81ef",
+9492 => x"388c08ff",
+9493 => x"9805088c",
+9494 => x"08ffb005",
+9495 => x"08078c08",
+9496 => x"ff9c0508",
+9497 => x"8c08ffb4",
+9498 => x"05080755",
+9499 => x"53728c08",
+9500 => x"ff98050c",
+9501 => x"738c08ff",
+9502 => x"9c050c8c",
+9503 => x"08ffa805",
+9504 => x"088c08ff",
+9505 => x"ac050855",
+9506 => x"53728c08",
+9507 => x"fef4050c",
+9508 => x"738c08fe",
+9509 => x"f8050c8c",
+9510 => x"08ffa005",
+9511 => x"088c08ff",
+9512 => x"a4050855",
+9513 => x"53728c08",
+9514 => x"feec050c",
+9515 => x"738c08fe",
+9516 => x"f0050c8c",
+9517 => x"08fef805",
+9518 => x"088c08fe",
+9519 => x"f0050871",
+9520 => x"7131708c",
+9521 => x"08fee805",
+9522 => x"0c525454",
+9523 => x"810b8c08",
+9524 => x"fee0050c",
+9525 => x"8c08fee8",
+9526 => x"05088c08",
+9527 => x"fef80508",
+9528 => x"54547373",
+9529 => x"260b0b0b",
+9530 => x"0b893880",
+9531 => x"0b8c08fe",
+9532 => x"e0050c8c",
+9533 => x"08fef405",
+9534 => x"088c08fe",
+9535 => x"ec050871",
+9536 => x"7131708c",
+9537 => x"08fee405",
+9538 => x"0c8c08fe",
+9539 => x"e4050870",
+9540 => x"8c08fee0",
+9541 => x"05083170",
+9542 => x"8c08fee4",
+9543 => x"050c5351",
+9544 => x"5254548c",
+9545 => x"08fee405",
+9546 => x"088c08fe",
+9547 => x"e8050855",
+9548 => x"53728c08",
+9549 => x"ffa8050c",
+9550 => x"738c08ff",
+9551 => x"ac050c8c",
+9552 => x"08ffb005",
+9553 => x"089f2b8c",
+9554 => x"08ffb405",
+9555 => x"08812a70",
+9556 => x"72078c08",
+9557 => x"ffb00508",
+9558 => x"812a5656",
+9559 => x"5656728c",
+9560 => x"08ffb005",
+9561 => x"0c738c08",
+9562 => x"ffb4050c",
+9563 => x"8c08ffa8",
+9564 => x"05088c08",
+9565 => x"ffac0508",
+9566 => x"5553728c",
+9567 => x"08fed805",
+9568 => x"0c738c08",
+9569 => x"fedc050c",
+9570 => x"8c08fed8",
+9571 => x"05088c08",
+9572 => x"fedc0508",
+9573 => x"5553728c",
+9574 => x"08fed005",
+9575 => x"0c738c08",
+9576 => x"fed4050c",
+9577 => x"8c08fed4",
+9578 => x"05088c08",
+9579 => x"fedc0508",
+9580 => x"7012708c",
+9581 => x"08fecc05",
+9582 => x"0c525454",
+9583 => x"810b8c08",
+9584 => x"fec4050c",
+9585 => x"8c08fecc",
+9586 => x"05088c08",
+9587 => x"fed40508",
+9588 => x"54547274",
+9589 => x"260b0b0b",
+9590 => x"0b893880",
+9591 => x"0b8c08fe",
+9592 => x"c4050c8c",
+9593 => x"08fed005",
+9594 => x"088c08fe",
+9595 => x"d8050870",
+9596 => x"12708c08",
+9597 => x"fec8050c",
+9598 => x"8c08fec8",
+9599 => x"05088c08",
+9600 => x"fec40508",
+9601 => x"11708c08",
+9602 => x"fec8050c",
+9603 => x"53515254",
+9604 => x"548c08fe",
+9605 => x"c805088c",
+9606 => x"08fecc05",
+9607 => x"08555372",
+9608 => x"8c08ffa8",
+9609 => x"050c738c",
+9610 => x"08ffac05",
+9611 => x"0c0b0b0b",
+9612 => x"fbca398c",
+9613 => x"08ff9805",
+9614 => x"08800670",
+9615 => x"8c08febc",
+9616 => x"050c8c08",
+9617 => x"ff9c0508",
+9618 => x"81ff0670",
+9619 => x"8c08fec0",
+9620 => x"050c5454",
+9621 => x"8c08febc",
+9622 => x"05088c08",
+9623 => x"fec00508",
+9624 => x"5553728c",
+9625 => x"08febc05",
+9626 => x"0c738c08",
+9627 => x"fec0050c",
+9628 => x"8c08febc",
+9629 => x"05085473",
+9630 => x"0b0b0b83",
+9631 => x"d0388c08",
+9632 => x"fec00508",
+9633 => x"53728180",
+9634 => x"2e098106",
+9635 => x"0b0b0b83",
+9636 => x"bc388c08",
+9637 => x"ff980508",
+9638 => x"982b8c08",
+9639 => x"ff9c0508",
+9640 => x"882a7072",
+9641 => x"078c08ff",
+9642 => x"98050888",
+9643 => x"2a718106",
+9644 => x"51565656",
+9645 => x"5672802e",
+9646 => x"0b0b0b81",
+9647 => x"bf388c08",
+9648 => x"ff980508",
+9649 => x"8c08ff9c",
+9650 => x"05085553",
+9651 => x"728c08fe",
+9652 => x"b4050c73",
+9653 => x"8c08feb8",
+9654 => x"050c8053",
+9655 => x"81805472",
+9656 => x"8c08feac",
+9657 => x"050c738c",
+9658 => x"08feb005",
+9659 => x"0c8c08fe",
+9660 => x"b805088c",
+9661 => x"08feb005",
+9662 => x"08701270",
+9663 => x"8c08fea8",
+9664 => x"050c5254",
+9665 => x"54810b8c",
+9666 => x"08fea005",
+9667 => x"0c8c08fe",
+9668 => x"a805088c",
+9669 => x"08feb805",
+9670 => x"08545472",
+9671 => x"74260b0b",
+9672 => x"0b0b8938",
+9673 => x"800b8c08",
+9674 => x"fea0050c",
+9675 => x"8c08feb4",
+9676 => x"05088c08",
+9677 => x"feac0508",
+9678 => x"7012708c",
+9679 => x"08fea405",
+9680 => x"0c8c08fe",
+9681 => x"a405088c",
+9682 => x"08fea005",
+9683 => x"0811708c",
+9684 => x"08fea405",
+9685 => x"0c535152",
+9686 => x"54548c08",
+9687 => x"fea40508",
+9688 => x"8c08fea8",
+9689 => x"05085553",
+9690 => x"728c08ff",
+9691 => x"98050c73",
+9692 => x"8c08ff9c",
+9693 => x"050c0b0b",
+9694 => x"0b81d239",
+9695 => x"8c08ffa8",
+9696 => x"0508708c",
+9697 => x"08ffac05",
+9698 => x"08075153",
+9699 => x"72802e0b",
+9700 => x"0b0b81b9",
+9701 => x"388c08ff",
+9702 => x"9805088c",
+9703 => x"08ff9c05",
+9704 => x"08555372",
+9705 => x"8c08fe98",
+9706 => x"050c738c",
+9707 => x"08fe9c05",
+9708 => x"0c805381",
+9709 => x"8054728c",
+9710 => x"08fe9005",
+9711 => x"0c738c08",
+9712 => x"fe94050c",
+9713 => x"8c08fe9c",
+9714 => x"05088c08",
+9715 => x"fe940508",
+9716 => x"7012708c",
+9717 => x"08fe8c05",
+9718 => x"0c525454",
+9719 => x"810b8c08",
+9720 => x"fe84050c",
+9721 => x"8c08fe8c",
+9722 => x"05088c08",
+9723 => x"fe9c0508",
+9724 => x"54547274",
+9725 => x"260b0b0b",
+9726 => x"0b893880",
+9727 => x"0b8c08fe",
+9728 => x"84050c8c",
+9729 => x"08fe9805",
+9730 => x"088c08fe",
+9731 => x"90050870",
+9732 => x"12708c08",
+9733 => x"fe88050c",
+9734 => x"8c08fe88",
+9735 => x"05088c08",
+9736 => x"fe840508",
+9737 => x"11708c08",
+9738 => x"fe88050c",
+9739 => x"53515254",
+9740 => x"548c08fe",
+9741 => x"8805088c",
+9742 => x"08fe8c05",
+9743 => x"08555372",
+9744 => x"8c08ff98",
+9745 => x"050c738c",
+9746 => x"08ff9c05",
+9747 => x"0c8c08c0",
+9748 => x"0508558c",
+9749 => x"08ff9805",
+9750 => x"088c08ff",
+9751 => x"9c050855",
+9752 => x"53728c16",
+9753 => x"0c739016",
+9754 => x"0c8c08c0",
+9755 => x"05088c08",
+9756 => x"ffb8050c",
+9757 => x"8c08ffb8",
+9758 => x"0508708c",
+9759 => x"08d4050c",
+9760 => x"8c08d405",
+9761 => x"08538c08",
+9762 => x"88050852",
+9763 => x"530b0b0b",
+9764 => x"9c863f8c",
+9765 => x"08880508",
+9766 => x"800c80c6",
+9767 => x"3d0d8c0c",
+9768 => x"048c0802",
+9769 => x"8c0c700b",
+9770 => x"0b82f4b8",
+9771 => x"70800c51",
+9772 => x"508c0c04",
+9773 => x"8c08028c",
+9774 => x"0c707080",
+9775 => x"0b8c08fc",
+9776 => x"050c8c08",
+9777 => x"88050851",
+9778 => x"7008822e",
+9779 => x"0981060b",
+9780 => x"0b0b0b88",
+9781 => x"38810b8c",
+9782 => x"08fc050c",
+9783 => x"8c08fc05",
+9784 => x"0870800c",
+9785 => x"5150508c",
+9786 => x"0c048c08",
+9787 => x"028c0c70",
+9788 => x"70800b8c",
+9789 => x"08fc050c",
+9790 => x"8c088805",
+9791 => x"08517008",
+9792 => x"842e0981",
+9793 => x"060b0b0b",
+9794 => x"0b883881",
+9795 => x"0b8c08fc",
+9796 => x"050c8c08",
+9797 => x"fc050870",
+9798 => x"800c5150",
+9799 => x"508c0c04",
+9800 => x"8c08028c",
+9801 => x"0c707080",
+9802 => x"0b8c08fc",
+9803 => x"050c8c08",
+9804 => x"88050851",
+9805 => x"7008802e",
+9806 => x"0b0b0b0b",
+9807 => x"97388c08",
+9808 => x"88050851",
+9809 => x"7008812e",
+9810 => x"0b0b0b0b",
+9811 => x"87380b0b",
+9812 => x"0b0b8839",
+9813 => x"810b8c08",
+9814 => x"fc050c8c",
+9815 => x"08fc0508",
+9816 => x"70800c51",
+9817 => x"50508c0c",
+9818 => x"048c0802",
+9819 => x"8c0cee3d",
+9820 => x"0d8c0888",
+9821 => x"05088c08",
+9822 => x"8c050855",
+9823 => x"53728c08",
+9824 => x"d0050c73",
+9825 => x"8c08d405",
+9826 => x"0c8c0890",
+9827 => x"05088c08",
+9828 => x"94050855",
+9829 => x"53728c08",
+9830 => x"c8050c73",
+9831 => x"8c08cc05",
+9832 => x"0c8c08ec",
+9833 => x"0570538c",
+9834 => x"08d00570",
+9835 => x"5351530b",
+9836 => x"0b0baba6",
+9837 => x"3f8c08d8",
+9838 => x"0570538c",
+9839 => x"08c80570",
+9840 => x"5351530b",
+9841 => x"0b0bab92",
+9842 => x"3f8c08ec",
+9843 => x"05705253",
+9844 => x"0b0b0b80",
+9845 => x"df3f8008",
+9846 => x"53720b0b",
+9847 => x"0b0b9e38",
+9848 => x"8c08d805",
+9849 => x"7052530b",
+9850 => x"0b0b80c8",
+9851 => x"3f800853",
+9852 => x"720b0b0b",
+9853 => x"0b87380b",
+9854 => x"0b0b0b8e",
+9855 => x"39810b8c",
+9856 => x"08c4050c",
+9857 => x"0b0b0b0b",
+9858 => x"9e398c08",
+9859 => x"d8057053",
+9860 => x"8c08ec05",
+9861 => x"70535153",
+9862 => x"0b0b0bae",
+9863 => x"c53f8008",
+9864 => x"708c08c4",
+9865 => x"050c538c",
+9866 => x"08c40508",
+9867 => x"800c943d",
+9868 => x"0d8c0c04",
+9869 => x"8c08028c",
+9870 => x"0c707080",
+9871 => x"0b8c08fc",
+9872 => x"050c8c08",
+9873 => x"88050851",
+9874 => x"7008802e",
+9875 => x"0b0b0b0b",
+9876 => x"97388c08",
+9877 => x"88050851",
+9878 => x"7008812e",
+9879 => x"0b0b0b0b",
+9880 => x"87380b0b",
+9881 => x"0b0b8839",
+9882 => x"810b8c08",
+9883 => x"fc050c8c",
+9884 => x"08fc0508",
+9885 => x"70800c51",
+9886 => x"50508c0c",
+9887 => x"048c0802",
+9888 => x"8c0cee3d",
+9889 => x"0d8c0888",
+9890 => x"05088c08",
+9891 => x"8c050855",
+9892 => x"53728c08",
+9893 => x"d0050c73",
+9894 => x"8c08d405",
+9895 => x"0c8c0890",
+9896 => x"05088c08",
+9897 => x"94050855",
+9898 => x"53728c08",
+9899 => x"c8050c73",
+9900 => x"8c08cc05",
+9901 => x"0c8c08ec",
+9902 => x"0570538c",
+9903 => x"08d00570",
+9904 => x"5351530b",
+9905 => x"0b0ba992",
+9906 => x"3f8c08d8",
+9907 => x"0570538c",
+9908 => x"08c80570",
+9909 => x"5351530b",
+9910 => x"0b0ba8fe",
+9911 => x"3f8c08ec",
+9912 => x"05705253",
+9913 => x"0b0b0b80",
+9914 => x"df3f8008",
+9915 => x"53720b0b",
+9916 => x"0b0b9e38",
+9917 => x"8c08d805",
+9918 => x"7052530b",
+9919 => x"0b0b80c8",
+9920 => x"3f800853",
+9921 => x"720b0b0b",
+9922 => x"0b87380b",
+9923 => x"0b0b0b8e",
+9924 => x"39810b8c",
+9925 => x"08c4050c",
+9926 => x"0b0b0b0b",
+9927 => x"9e398c08",
+9928 => x"d8057053",
+9929 => x"8c08ec05",
+9930 => x"70535153",
+9931 => x"0b0b0bac",
+9932 => x"b13f8008",
+9933 => x"708c08c4",
+9934 => x"050c538c",
+9935 => x"08c40508",
+9936 => x"800c943d",
+9937 => x"0d8c0c04",
+9938 => x"8c08028c",
+9939 => x"0c707080",
+9940 => x"0b8c08fc",
+9941 => x"050c8c08",
+9942 => x"88050851",
+9943 => x"7008802e",
+9944 => x"0b0b0b0b",
+9945 => x"97388c08",
+9946 => x"88050851",
+9947 => x"7008812e",
+9948 => x"0b0b0b0b",
+9949 => x"87380b0b",
+9950 => x"0b0b8839",
+9951 => x"810b8c08",
+9952 => x"fc050c8c",
+9953 => x"08fc0508",
+9954 => x"70800c51",
+9955 => x"50508c0c",
+9956 => x"048c0802",
+9957 => x"8c0cee3d",
+9958 => x"0d8c0888",
+9959 => x"05088c08",
+9960 => x"8c050855",
+9961 => x"53728c08",
+9962 => x"d0050c73",
+9963 => x"8c08d405",
+9964 => x"0c8c0890",
+9965 => x"05088c08",
+9966 => x"94050855",
+9967 => x"53728c08",
+9968 => x"c8050c73",
+9969 => x"8c08cc05",
+9970 => x"0c8c08ec",
+9971 => x"0570538c",
+9972 => x"08d00570",
+9973 => x"5351530b",
+9974 => x"0b0ba6fe",
+9975 => x"3f8c08d8",
+9976 => x"0570538c",
+9977 => x"08c80570",
+9978 => x"5351530b",
+9979 => x"0b0ba6ea",
+9980 => x"3f8c08ec",
+9981 => x"05705253",
+9982 => x"0b0b0b80",
+9983 => x"df3f8008",
+9984 => x"53720b0b",
+9985 => x"0b0b9e38",
+9986 => x"8c08d805",
+9987 => x"7052530b",
+9988 => x"0b0b80c8",
+9989 => x"3f800853",
+9990 => x"720b0b0b",
+9991 => x"0b87380b",
+9992 => x"0b0b0b8e",
+9993 => x"39ff0b8c",
+9994 => x"08c4050c",
+9995 => x"0b0b0b0b",
+9996 => x"9e398c08",
+9997 => x"d8057053",
+9998 => x"8c08ec05",
+9999 => x"70535153",
+10000 => x"0b0b0baa",
+10001 => x"9d3f8008",
+10002 => x"708c08c4",
+10003 => x"050c538c",
+10004 => x"08c40508",
+10005 => x"800c943d",
+10006 => x"0d8c0c04",
+10007 => x"8c08028c",
+10008 => x"0c707080",
+10009 => x"0b8c08fc",
+10010 => x"050c8c08",
+10011 => x"88050851",
+10012 => x"7008802e",
+10013 => x"0b0b0b0b",
+10014 => x"97388c08",
+10015 => x"88050851",
+10016 => x"7008812e",
+10017 => x"0b0b0b0b",
+10018 => x"87380b0b",
+10019 => x"0b0b8839",
+10020 => x"810b8c08",
+10021 => x"fc050c8c",
+10022 => x"08fc0508",
+10023 => x"70800c51",
+10024 => x"50508c0c",
+10025 => x"048c0802",
+10026 => x"8c0cee3d",
+10027 => x"0d8c0888",
+10028 => x"05088c08",
+10029 => x"8c050855",
+10030 => x"53728c08",
+10031 => x"d0050c73",
+10032 => x"8c08d405",
+10033 => x"0c8c0890",
+10034 => x"05088c08",
+10035 => x"94050855",
+10036 => x"53728c08",
+10037 => x"c8050c73",
+10038 => x"8c08cc05",
+10039 => x"0c8c08ec",
+10040 => x"0570538c",
+10041 => x"08d00570",
+10042 => x"5351530b",
+10043 => x"0b0ba4ea",
+10044 => x"3f8c08d8",
+10045 => x"0570538c",
+10046 => x"08c80570",
+10047 => x"5351530b",
+10048 => x"0b0ba4d6",
+10049 => x"3f8c08ec",
+10050 => x"05705253",
+10051 => x"0b0b0b80",
+10052 => x"df3f8008",
+10053 => x"53720b0b",
+10054 => x"0b0b9e38",
+10055 => x"8c08d805",
+10056 => x"7052530b",
+10057 => x"0b0b80c8",
+10058 => x"3f800853",
+10059 => x"720b0b0b",
+10060 => x"0b87380b",
+10061 => x"0b0b0b8e",
+10062 => x"39810b8c",
+10063 => x"08c4050c",
+10064 => x"0b0b0b0b",
+10065 => x"9e398c08",
+10066 => x"d8057053",
+10067 => x"8c08ec05",
+10068 => x"70535153",
+10069 => x"0b0b0ba8",
+10070 => x"893f8008",
+10071 => x"708c08c4",
+10072 => x"050c538c",
+10073 => x"08c40508",
+10074 => x"800c943d",
+10075 => x"0d8c0c04",
+10076 => x"8c08028c",
+10077 => x"0c707080",
+10078 => x"0b8c08fc",
+10079 => x"050c8c08",
+10080 => x"88050851",
+10081 => x"7008802e",
+10082 => x"0b0b0b0b",
+10083 => x"97388c08",
+10084 => x"88050851",
+10085 => x"7008812e",
+10086 => x"0b0b0b0b",
+10087 => x"87380b0b",
+10088 => x"0b0b8839",
+10089 => x"810b8c08",
+10090 => x"fc050c8c",
+10091 => x"08fc0508",
+10092 => x"70800c51",
+10093 => x"50508c0c",
+10094 => x"048c0802",
+10095 => x"8c0cee3d",
+10096 => x"0d8c0888",
+10097 => x"05088c08",
+10098 => x"8c050855",
+10099 => x"53728c08",
+10100 => x"d0050c73",
+10101 => x"8c08d405",
+10102 => x"0c8c0890",
+10103 => x"05088c08",
+10104 => x"94050855",
+10105 => x"53728c08",
+10106 => x"c8050c73",
+10107 => x"8c08cc05",
+10108 => x"0c8c08ec",
+10109 => x"0570538c",
+10110 => x"08d00570",
+10111 => x"5351530b",
+10112 => x"0b0ba2d6",
+10113 => x"3f8c08d8",
+10114 => x"0570538c",
+10115 => x"08c80570",
+10116 => x"5351530b",
+10117 => x"0b0ba2c2",
+10118 => x"3f8c08ec",
+10119 => x"05705253",
+10120 => x"0b0b0b80",
+10121 => x"df3f8008",
+10122 => x"53720b0b",
+10123 => x"0b0b9e38",
+10124 => x"8c08d805",
+10125 => x"7052530b",
+10126 => x"0b0b80c8",
+10127 => x"3f800853",
+10128 => x"720b0b0b",
+10129 => x"0b87380b",
+10130 => x"0b0b0b8e",
+10131 => x"39810b8c",
+10132 => x"08c4050c",
+10133 => x"0b0b0b0b",
+10134 => x"9e398c08",
+10135 => x"d8057053",
+10136 => x"8c08ec05",
+10137 => x"70535153",
+10138 => x"0b0b0ba5",
+10139 => x"f53f8008",
+10140 => x"708c08c4",
+10141 => x"050c538c",
+10142 => x"08c40508",
+10143 => x"800c943d",
+10144 => x"0d8c0c04",
+10145 => x"8c08028c",
+10146 => x"0c707080",
+10147 => x"0b8c08fc",
+10148 => x"050c8c08",
+10149 => x"88050851",
+10150 => x"7008802e",
+10151 => x"0b0b0b0b",
+10152 => x"97388c08",
+10153 => x"88050851",
+10154 => x"7008812e",
+10155 => x"0b0b0b0b",
+10156 => x"87380b0b",
+10157 => x"0b0b8839",
+10158 => x"810b8c08",
+10159 => x"fc050c8c",
+10160 => x"08fc0508",
+10161 => x"70800c51",
+10162 => x"50508c0c",
+10163 => x"048c0802",
+10164 => x"8c0cf63d",
+10165 => x"0d830b8c",
+10166 => x"08ec050c",
+10167 => x"800b8c08",
+10168 => x"e8050c8c",
+10169 => x"088c0508",
+10170 => x"80250b0b",
+10171 => x"0b0b8838",
+10172 => x"810b8c08",
+10173 => x"e8050c8c",
+10174 => x"08e80508",
+10175 => x"8c08f005",
+10176 => x"0c8c088c",
+10177 => x"05080b0b",
+10178 => x"0b0b8e38",
+10179 => x"820b8c08",
+10180 => x"ec050c0b",
+10181 => x"0b0b81b5",
+10182 => x"39bc0b8c",
+10183 => x"08f4050c",
+10184 => x"8c08f005",
+10185 => x"08802e0b",
+10186 => x"0b0b80c9",
+10187 => x"388c088c",
+10188 => x"0508810a",
+10189 => x"2e098106",
+10190 => x"0b0b0b0b",
+10191 => x"9b388f83",
+10192 => x"0a53800b",
+10193 => x"8c088805",
+10194 => x"08565472",
+10195 => x"750c7384",
+10196 => x"160c0b0b",
+10197 => x"0b818939",
+10198 => x"8c088c05",
+10199 => x"0830708c",
+10200 => x"08fc050c",
+10201 => x"709f2c70",
+10202 => x"8c08f805",
+10203 => x"0c51530b",
+10204 => x"0b0b0b97",
+10205 => x"398c088c",
+10206 => x"0508708c",
+10207 => x"08fc050c",
+10208 => x"709f2c70",
+10209 => x"8c08f805",
+10210 => x"0c51538c",
+10211 => x"08f80508",
+10212 => x"f00a260b",
+10213 => x"0b0b0bb5",
+10214 => x"388c08fc",
+10215 => x"05089f2a",
+10216 => x"8c08f805",
+10217 => x"08107072",
+10218 => x"078c08f8",
+10219 => x"050c8c08",
+10220 => x"fc050810",
+10221 => x"8c08fc05",
+10222 => x"0c8c08f4",
+10223 => x"0508ff05",
+10224 => x"8c08f405",
+10225 => x"0c54540b",
+10226 => x"0b0bffbf",
+10227 => x"398c08ec",
+10228 => x"0570538c",
+10229 => x"08880508",
+10230 => x"52530b0b",
+10231 => x"0b8db93f",
+10232 => x"8c088805",
+10233 => x"08800c8c",
+10234 => x"3d0d8c0c",
+10235 => x"048c0802",
+10236 => x"8c0cec3d",
+10237 => x"0d8c0888",
+10238 => x"05088c08",
+10239 => x"8c050857",
+10240 => x"55748c08",
+10241 => x"e0050c75",
+10242 => x"8c08e405",
+10243 => x"0c8c08ec",
+10244 => x"0570538c",
+10245 => x"08e00570",
+10246 => x"5351550b",
+10247 => x"0b0b9eba",
+10248 => x"3f8c08ec",
+10249 => x"05705255",
+10250 => x"0b0b0b83",
+10251 => x"d93f8008",
+10252 => x"5574802e",
+10253 => x"0b0b0b0b",
+10254 => x"8e38800b",
+10255 => x"8c08d405",
+10256 => x"0c0b0b0b",
+10257 => x"82b4398c",
+10258 => x"08ec0570",
+10259 => x"52550b0b",
+10260 => x"0b82ea3f",
+10261 => x"80085574",
+10262 => x"802e0b0b",
+10263 => x"0b0b8e38",
+10264 => x"800b8c08",
+10265 => x"d4050c0b",
+10266 => x"0b0b828e",
+10267 => x"398c08ec",
+10268 => x"05705255",
+10269 => x"0b0b0b82",
+10270 => x"8e3f8008",
+10271 => x"5574802e",
+10272 => x"0b0b0b0b",
+10273 => x"b4388c08",
+10274 => x"f0050880",
+10275 => x"2e0b0b0b",
+10276 => x"0b8f3881",
+10277 => x"0a0b8c08",
+10278 => x"d0050c0b",
+10279 => x"0b0b0b89",
+10280 => x"39fe0a0b",
+10281 => x"8c08d005",
+10282 => x"0c8c08d0",
+10283 => x"05088c08",
+10284 => x"d4050c0b",
+10285 => x"0b0b81c2",
+10286 => x"398c08f4",
+10287 => x"05088025",
+10288 => x"0b0b0b0b",
+10289 => x"8e38800b",
+10290 => x"8c08d405",
+10291 => x"0c0b0b0b",
+10292 => x"81a8399e",
+10293 => x"0b8c08f4",
+10294 => x"0508250b",
+10295 => x"0b0b0bb4",
+10296 => x"388c08f0",
+10297 => x"0508802e",
+10298 => x"0b0b0b0b",
+10299 => x"8f38810a",
+10300 => x"0b8c08cc",
+10301 => x"050c0b0b",
+10302 => x"0b0b8939",
+10303 => x"fe0a0b8c",
+10304 => x"08cc050c",
+10305 => x"8c08cc05",
+10306 => x"088c08d4",
+10307 => x"050c0b0b",
+10308 => x"0b80e739",
+10309 => x"bc0b8c08",
+10310 => x"f4050831",
+10311 => x"8c08d805",
+10312 => x"71565855",
+10313 => x"8c08f805",
+10314 => x"088c08fc",
+10315 => x"05085755",
+10316 => x"74527553",
+10317 => x"76510b0b",
+10318 => x"0b88d53f",
+10319 => x"8c08d805",
+10320 => x"088c08dc",
+10321 => x"0508708c",
+10322 => x"08e8050c",
+10323 => x"8c08e805",
+10324 => x"088c08c8",
+10325 => x"050c5755",
+10326 => x"8c08f005",
+10327 => x"08802e0b",
+10328 => x"0b0b0b8c",
+10329 => x"388c08c8",
+10330 => x"0508308c",
+10331 => x"08c8050c",
+10332 => x"8c08c805",
+10333 => x"088c08d4",
+10334 => x"050c8c08",
+10335 => x"d4050880",
+10336 => x"0c963d0d",
+10337 => x"8c0c048c",
+10338 => x"08028c0c",
+10339 => x"7070800b",
+10340 => x"8c08fc05",
+10341 => x"0c8c0888",
+10342 => x"05085170",
+10343 => x"08842e09",
+10344 => x"81060b0b",
+10345 => x"0b0b8838",
+10346 => x"810b8c08",
+10347 => x"fc050c8c",
+10348 => x"08fc0508",
+10349 => x"70800c51",
+10350 => x"50508c0c",
+10351 => x"048c0802",
+10352 => x"8c0c7070",
+10353 => x"800b8c08",
+10354 => x"fc050c8c",
+10355 => x"08880508",
+10356 => x"51700880",
+10357 => x"2e0b0b0b",
+10358 => x"0b97388c",
+10359 => x"08880508",
+10360 => x"51700881",
+10361 => x"2e0b0b0b",
+10362 => x"0b87380b",
+10363 => x"0b0b0b88",
+10364 => x"39810b8c",
+10365 => x"08fc050c",
+10366 => x"8c08fc05",
+10367 => x"0870800c",
+10368 => x"5150508c",
+10369 => x"0c048c08",
+10370 => x"028c0c70",
+10371 => x"70800b8c",
+10372 => x"08fc050c",
+10373 => x"8c088805",
+10374 => x"08517008",
+10375 => x"822e0981",
+10376 => x"060b0b0b",
+10377 => x"0b883881",
+10378 => x"0b8c08fc",
+10379 => x"050c8c08",
+10380 => x"fc050870",
+10381 => x"800c5150",
+10382 => x"508c0c04",
+10383 => x"8c08028c",
+10384 => x"0c707070",
+10385 => x"7080538c",
+10386 => x"088c0508",
+10387 => x"528c0888",
+10388 => x"0508510b",
+10389 => x"0bfdccbf",
+10390 => x"3f800870",
+10391 => x"800c5450",
+10392 => x"5050508c",
+10393 => x"0c048c08",
+10394 => x"028c0c70",
+10395 => x"70707081",
+10396 => x"538c088c",
+10397 => x"0508528c",
+10398 => x"08880508",
+10399 => x"510b0bfd",
+10400 => x"cc953f80",
+10401 => x"0870800c",
+10402 => x"54505050",
+10403 => x"508c0c04",
+10404 => x"8c08028c",
+10405 => x"0c707080",
+10406 => x"0b8c08fc",
+10407 => x"050c8c08",
+10408 => x"88050881",
+10409 => x"06ff1170",
+10410 => x"09708c08",
+10411 => x"8c050806",
+10412 => x"8c08fc05",
+10413 => x"08118c08",
+10414 => x"fc050c8c",
+10415 => x"08880508",
+10416 => x"812a8c08",
+10417 => x"88050c8c",
+10418 => x"088c0508",
+10419 => x"108c088c",
+10420 => x"050c5151",
+10421 => x"51518c08",
+10422 => x"88050880",
+10423 => x"2e0b0b0b",
+10424 => x"0b87380b",
+10425 => x"0b0bffb6",
+10426 => x"398c08fc",
+10427 => x"05087080",
+10428 => x"0c515050",
+10429 => x"8c0c048c",
+10430 => x"08028c0c",
+10431 => x"eb3d0d80",
+10432 => x"0b8c08f0",
+10433 => x"050c800b",
+10434 => x"8c08f405",
+10435 => x"0c8c088c",
+10436 => x"05088c08",
+10437 => x"90050856",
+10438 => x"54738c08",
+10439 => x"f0050c74",
+10440 => x"8c08f405",
+10441 => x"0c8c08f8",
+10442 => x"058c08f0",
+10443 => x"05565688",
+10444 => x"70547553",
+10445 => x"7652540b",
+10446 => x"0bfdcccf",
+10447 => x"3f800b8c",
+10448 => x"08e8050c",
+10449 => x"800b8c08",
+10450 => x"ec050c8c",
+10451 => x"08940508",
+10452 => x"8c089805",
+10453 => x"08565473",
+10454 => x"8c08e805",
+10455 => x"0c748c08",
+10456 => x"ec050c8c",
+10457 => x"08f0058c",
+10458 => x"08e80556",
+10459 => x"56887054",
+10460 => x"75537652",
+10461 => x"540b0bfd",
+10462 => x"cc913f80",
+10463 => x"0b8c08e8",
+10464 => x"050c800b",
+10465 => x"8c08ec05",
+10466 => x"0c8c08fc",
+10467 => x"050883ff",
+10468 => x"ff068c08",
+10469 => x"cc050c8c",
+10470 => x"08fc0508",
+10471 => x"902a8c08",
+10472 => x"c4050c8c",
+10473 => x"08f40508",
+10474 => x"83ffff06",
+10475 => x"8c08c805",
+10476 => x"0c8c08f4",
+10477 => x"0508902a",
+10478 => x"8c08c005",
+10479 => x"0c8c08cc",
+10480 => x"05088c08",
+10481 => x"c8050829",
+10482 => x"708c08dc",
+10483 => x"050c8c08",
+10484 => x"cc05088c",
+10485 => x"08c00508",
+10486 => x"29708c08",
+10487 => x"d8050c8c",
+10488 => x"08c40508",
+10489 => x"8c08c805",
+10490 => x"0829708c",
+10491 => x"08d4050c",
+10492 => x"8c08c405",
+10493 => x"088c08c0",
+10494 => x"05082970",
+10495 => x"8c08d005",
+10496 => x"0c8c08dc",
+10497 => x"0508902a",
+10498 => x"8c08d805",
+10499 => x"08118c08",
+10500 => x"d8050c8c",
+10501 => x"08d80508",
+10502 => x"8c08d405",
+10503 => x"08058c08",
+10504 => x"d8050c51",
+10505 => x"51515154",
+10506 => x"8c08d805",
+10507 => x"088c08d4",
+10508 => x"0508270b",
+10509 => x"0b0b0b8f",
+10510 => x"388c08d0",
+10511 => x"05088480",
+10512 => x"80058c08",
+10513 => x"d0050c8c",
+10514 => x"08d80508",
+10515 => x"902a8c08",
+10516 => x"d0050811",
+10517 => x"8c08e005",
+10518 => x"0c8c08d8",
+10519 => x"050883ff",
+10520 => x"ff067090",
+10521 => x"2b8c08dc",
+10522 => x"050883ff",
+10523 => x"ff067012",
+10524 => x"8c08e405",
+10525 => x"0c525751",
+10526 => x"548c08e0",
+10527 => x"05088c08",
+10528 => x"e4050856",
+10529 => x"54738c08",
+10530 => x"e8050c74",
+10531 => x"8c08ec05",
+10532 => x"0c8c08fc",
+10533 => x"05088c08",
+10534 => x"f0050829",
+10535 => x"8c08f805",
+10536 => x"088c08f4",
+10537 => x"05082970",
+10538 => x"128c08e8",
+10539 => x"0508118c",
+10540 => x"08e8050c",
+10541 => x"5155558c",
+10542 => x"08e80508",
+10543 => x"8c08ec05",
+10544 => x"088c0888",
+10545 => x"05085856",
+10546 => x"5473760c",
+10547 => x"7484170c",
+10548 => x"8c088805",
+10549 => x"08800c97",
+10550 => x"3d0d8c0c",
+10551 => x"048c0802",
+10552 => x"8c0cf63d",
+10553 => x"0d800b8c",
+10554 => x"08f0050c",
+10555 => x"800b8c08",
+10556 => x"f4050c8c",
+10557 => x"088c0508",
+10558 => x"8c089005",
+10559 => x"08565473",
+10560 => x"8c08f005",
+10561 => x"0c748c08",
+10562 => x"f4050c8c",
+10563 => x"08f8058c",
+10564 => x"08f00556",
+10565 => x"56887054",
+10566 => x"75537652",
+10567 => x"540b0bfd",
+10568 => x"c8e93f80",
+10569 => x"0b8c08f0",
+10570 => x"050c800b",
+10571 => x"8c08f405",
+10572 => x"0c8c08f8",
+10573 => x"0508308c",
+10574 => x"08ec050c",
+10575 => x"8c08fc05",
+10576 => x"08802e0b",
+10577 => x"0b0b0b8d",
+10578 => x"388c08ec",
+10579 => x"0508ff05",
+10580 => x"8c08ec05",
+10581 => x"0c8c08ec",
+10582 => x"05088c08",
+10583 => x"f0050c8c",
+10584 => x"08fc0508",
+10585 => x"308c08f4",
+10586 => x"050c8c08",
+10587 => x"f005088c",
+10588 => x"08f40508",
+10589 => x"8c088805",
+10590 => x"08585654",
+10591 => x"73760c74",
+10592 => x"84170c8c",
+10593 => x"08880508",
+10594 => x"800c8c3d",
+10595 => x"0d8c0c04",
+10596 => x"8c08028c",
+10597 => x"0cf53d0d",
+10598 => x"8c089405",
+10599 => x"080b0b0b",
+10600 => x"0ba0388c",
+10601 => x"088c0508",
+10602 => x"8c089005",
+10603 => x"088c0888",
+10604 => x"05085856",
+10605 => x"5473760c",
+10606 => x"7484170c",
+10607 => x"0b0b0b81",
+10608 => x"ca39800b",
+10609 => x"8c08f005",
+10610 => x"0c800b8c",
+10611 => x"08f4050c",
+10612 => x"8c088c05",
+10613 => x"088c0890",
+10614 => x"05085654",
+10615 => x"738c08f0",
+10616 => x"050c748c",
+10617 => x"08f4050c",
+10618 => x"8c08f805",
+10619 => x"8c08f005",
+10620 => x"56568870",
+10621 => x"54755376",
+10622 => x"52540b0b",
+10623 => x"fdc78c3f",
+10624 => x"a00b8c08",
+10625 => x"94050831",
+10626 => x"8c08ec05",
+10627 => x"0c8c08ec",
+10628 => x"05088024",
+10629 => x"0b0b0b0b",
+10630 => x"a138800b",
+10631 => x"8c08f005",
+10632 => x"0c8c08ec",
+10633 => x"0508308c",
+10634 => x"08f80508",
+10635 => x"712a8c08",
+10636 => x"f4050c54",
+10637 => x"0b0b0b0b",
+10638 => x"b9398c08",
+10639 => x"f805088c",
+10640 => x"08ec0508",
+10641 => x"2b8c08e8",
+10642 => x"050c8c08",
+10643 => x"f805088c",
+10644 => x"08940508",
+10645 => x"2a8c08f0",
+10646 => x"050c8c08",
+10647 => x"fc05088c",
+10648 => x"08940508",
+10649 => x"2a708c08",
+10650 => x"e8050807",
+10651 => x"8c08f405",
+10652 => x"0c548c08",
+10653 => x"f005088c",
+10654 => x"08f40508",
+10655 => x"8c088805",
+10656 => x"08585654",
+10657 => x"73760c74",
+10658 => x"84170c8c",
+10659 => x"08880508",
+10660 => x"800c8d3d",
+10661 => x"0d8c0c04",
+10662 => x"8c08028c",
+10663 => x"0cc73d0d",
+10664 => x"8c088c05",
+10665 => x"08559015",
+10666 => x"088c1608",
+10667 => x"5656748c",
+10668 => x"08f0050c",
+10669 => x"758c08f4",
+10670 => x"050c8c08",
+10671 => x"8c050884",
+10672 => x"11088c08",
+10673 => x"ec050c55",
+10674 => x"800b8c08",
+10675 => x"e8050c8c",
+10676 => x"088c0508",
+10677 => x"510b0b0b",
+10678 => x"90b73f80",
+10679 => x"08557480",
+10680 => x"2e0b0b0b",
+10681 => x"0bad388f",
+10682 => x"ff0b8c08",
+10683 => x"e8050c8c",
+10684 => x"08f00508",
+10685 => x"a0808007",
+10686 => x"8c08f405",
+10687 => x"08800757",
+10688 => x"55748c08",
+10689 => x"f0050c75",
+10690 => x"8c08f405",
+10691 => x"0c0b0b0b",
+10692 => x"8df4398c",
+10693 => x"088c0508",
+10694 => x"510b0b0b",
+10695 => x"8fbd3f80",
+10696 => x"08557480",
+10697 => x"2e0b0b0b",
+10698 => x"0b9f388f",
+10699 => x"ff0b8c08",
+10700 => x"e8050c80",
+10701 => x"55805674",
+10702 => x"8c08f005",
+10703 => x"0c758c08",
+10704 => x"f4050c0b",
+10705 => x"0b0b8dbe",
+10706 => x"398c088c",
+10707 => x"0508510b",
+10708 => x"0b0b8ed1",
+10709 => x"3f800855",
+10710 => x"74802e0b",
+10711 => x"0b0b0b9e",
+10712 => x"38800b8c",
+10713 => x"08e8050c",
+10714 => x"80558056",
+10715 => x"748c08f0",
+10716 => x"050c758c",
+10717 => x"08f4050c",
+10718 => x"0b0b0b8d",
+10719 => x"89398c08",
+10720 => x"f0050870",
+10721 => x"8c08f405",
+10722 => x"08075155",
+10723 => x"740b0b0b",
+10724 => x"0b8e3880",
+10725 => x"0b8c08e8",
+10726 => x"050c0b0b",
+10727 => x"0b8ce739",
+10728 => x"8c088c05",
+10729 => x"08558815",
+10730 => x"08f88225",
+10731 => x"0b0b0b87",
+10732 => x"af388c08",
+10733 => x"8c0508f8",
+10734 => x"820b8812",
+10735 => x"08318c08",
+10736 => x"e4050c55",
+10737 => x"800b8c08",
+10738 => x"e8050cb8",
+10739 => x"0b8c08e4",
+10740 => x"0508250b",
+10741 => x"0b0b0b97",
+10742 => x"38805580",
+10743 => x"56748c08",
+10744 => x"f0050c75",
+10745 => x"8c08f405",
+10746 => x"0c0b0b0b",
+10747 => x"82b03980",
+10748 => x"0b8c08e0",
+10749 => x"050c8c08",
+10750 => x"d8055780",
+10751 => x"55810b8c",
+10752 => x"08e40508",
+10753 => x"55567452",
+10754 => x"75537651",
+10755 => x"0b0bfdbc",
+10756 => x"ab3f8c08",
+10757 => x"d805088c",
+10758 => x"08dc0508",
+10759 => x"5755748c",
+10760 => x"08d0050c",
+10761 => x"758c08d4",
+10762 => x"050cff56",
+10763 => x"ff57758c",
+10764 => x"08c8050c",
+10765 => x"768c08cc",
+10766 => x"050c8c08",
+10767 => x"d405088c",
+10768 => x"08cc0508",
+10769 => x"7012708c",
+10770 => x"08c4050c",
+10771 => x"52565781",
+10772 => x"0b8c08ff",
+10773 => x"bc050c8c",
+10774 => x"08c40508",
+10775 => x"8c08d405",
+10776 => x"08585676",
+10777 => x"76260b0b",
+10778 => x"0b0b8938",
+10779 => x"800b8c08",
+10780 => x"ffbc050c",
+10781 => x"8c08d005",
+10782 => x"088c08c8",
+10783 => x"05087012",
+10784 => x"708c08c0",
+10785 => x"050c8c08",
+10786 => x"c005088c",
+10787 => x"08ffbc05",
+10788 => x"0811708c",
+10789 => x"08c0050c",
+10790 => x"8c08c005",
+10791 => x"08708c08",
+10792 => x"f0050806",
+10793 => x"8c08c405",
+10794 => x"08708c08",
+10795 => x"f4050806",
+10796 => x"72707207",
+10797 => x"51525752",
+10798 => x"5252525a",
+10799 => x"52575576",
+10800 => x"802e0b0b",
+10801 => x"0b0b8838",
+10802 => x"810b8c08",
+10803 => x"e0050c8c",
+10804 => x"08d8058c",
+10805 => x"08e40508",
+10806 => x"55578c08",
+10807 => x"f005088c",
+10808 => x"08f40508",
+10809 => x"57557452",
+10810 => x"75537651",
+10811 => x"0b0b0bf9",
+10812 => x"9f3f8c08",
+10813 => x"d805088c",
+10814 => x"08dc0508",
+10815 => x"8c08e005",
+10816 => x"089f2c8c",
+10817 => x"08e00508",
+10818 => x"71707507",
+10819 => x"8c08f005",
+10820 => x"0c737207",
+10821 => x"8c08f405",
+10822 => x"0c59595b",
+10823 => x"59578c08",
+10824 => x"f0050880",
+10825 => x"06708c08",
+10826 => x"ffb4050c",
+10827 => x"8c08f405",
+10828 => x"0881ff06",
+10829 => x"708c08ff",
+10830 => x"b8050c57",
+10831 => x"558c08ff",
+10832 => x"b405088c",
+10833 => x"08ffb805",
+10834 => x"08575574",
+10835 => x"8c08ffb4",
+10836 => x"050c758c",
+10837 => x"08ffb805",
+10838 => x"0c8c08ff",
+10839 => x"b4050856",
+10840 => x"750b0b0b",
+10841 => x"81f8388c",
+10842 => x"08ffb805",
+10843 => x"08577681",
+10844 => x"802e0981",
+10845 => x"060b0b0b",
+10846 => x"81e4388c",
+10847 => x"08f00508",
+10848 => x"982b8c08",
+10849 => x"f4050888",
+10850 => x"2a707207",
+10851 => x"8c08f005",
+10852 => x"08882a71",
+10853 => x"81065158",
+10854 => x"58585874",
+10855 => x"802e0b0b",
+10856 => x"0b82ef38",
+10857 => x"8c08f005",
+10858 => x"088c08f4",
+10859 => x"05085755",
+10860 => x"748c08ff",
+10861 => x"ac050c75",
+10862 => x"8c08ffb0",
+10863 => x"050c8056",
+10864 => x"81805775",
+10865 => x"8c08ffa4",
+10866 => x"050c768c",
+10867 => x"08ffa805",
+10868 => x"0c8c08ff",
+10869 => x"b005088c",
+10870 => x"08ffa805",
+10871 => x"08701270",
+10872 => x"8c08ffa0",
+10873 => x"050c5256",
+10874 => x"57810b8c",
+10875 => x"08ff9805",
+10876 => x"0c8c08ff",
+10877 => x"a005088c",
+10878 => x"08ffb005",
+10879 => x"08585676",
+10880 => x"76260b0b",
+10881 => x"0b0b8938",
+10882 => x"800b8c08",
+10883 => x"ff98050c",
+10884 => x"8c08ffac",
+10885 => x"05088c08",
+10886 => x"ffa40508",
+10887 => x"7012708c",
+10888 => x"08ff9c05",
+10889 => x"0c8c08ff",
+10890 => x"9c05088c",
+10891 => x"08ff9805",
+10892 => x"0811708c",
+10893 => x"08ff9c05",
+10894 => x"0c525a52",
+10895 => x"57558c08",
+10896 => x"ff9c0508",
+10897 => x"8c08ffa0",
+10898 => x"05085755",
+10899 => x"748c08f0",
+10900 => x"050c758c",
+10901 => x"08f4050c",
+10902 => x"0b0b0b81",
+10903 => x"b5398c08",
+10904 => x"f005088c",
+10905 => x"08f40508",
+10906 => x"5856758c",
+10907 => x"08ff9005",
+10908 => x"0c768c08",
+10909 => x"ff94050c",
+10910 => x"805580ff",
+10911 => x"56748c08",
+10912 => x"ff88050c",
+10913 => x"758c08ff",
+10914 => x"8c050c8c",
+10915 => x"08ff9405",
+10916 => x"088c08ff",
+10917 => x"8c050870",
+10918 => x"12708c08",
+10919 => x"ff84050c",
+10920 => x"52585681",
+10921 => x"0b8c08fe",
+10922 => x"fc050c8c",
+10923 => x"08ff8405",
+10924 => x"088c08ff",
+10925 => x"94050857",
+10926 => x"55757526",
+10927 => x"0b0b0b0b",
+10928 => x"8938800b",
+10929 => x"8c08fefc",
+10930 => x"050c8c08",
+10931 => x"ff900508",
+10932 => x"8c08ff88",
+10933 => x"05087012",
+10934 => x"708c08ff",
+10935 => x"80050c8c",
+10936 => x"08ff8005",
+10937 => x"088c08fe",
+10938 => x"fc050811",
+10939 => x"708c08ff",
+10940 => x"80050c53",
+10941 => x"59525657",
+10942 => x"8c08ff80",
+10943 => x"05088c08",
+10944 => x"ff840508",
+10945 => x"5755748c",
+10946 => x"08f0050c",
+10947 => x"758c08f4",
+10948 => x"050c8c08",
+10949 => x"f00508f0",
+10950 => x"0a260b0b",
+10951 => x"0b0b8738",
+10952 => x"0b0b0b0b",
+10953 => x"8d398c08",
+10954 => x"e8050881",
+10955 => x"058c08e8",
+10956 => x"050c8c08",
+10957 => x"f0050898",
+10958 => x"2b8c08f4",
+10959 => x"0508882a",
+10960 => x"7072078c",
+10961 => x"08f00508",
+10962 => x"882a5858",
+10963 => x"5858748c",
+10964 => x"08f0050c",
+10965 => x"758c08f4",
+10966 => x"050c0b0b",
+10967 => x"0b85a739",
+10968 => x"8c088c05",
+10969 => x"085587ff",
+10970 => x"0b881608",
+10971 => x"250b0b0b",
+10972 => x"0b9f388f",
+10973 => x"ff0b8c08",
+10974 => x"e8050c80",
+10975 => x"55805674",
+10976 => x"8c08f005",
+10977 => x"0c758c08",
+10978 => x"f4050c0b",
+10979 => x"0b0b84f6",
+10980 => x"398c088c",
+10981 => x"05088811",
+10982 => x"0887ff05",
+10983 => x"8c08e805",
+10984 => x"0c8c08f0",
+10985 => x"05088006",
+10986 => x"708c08fe",
+10987 => x"f4050c8c",
+10988 => x"08f40508",
+10989 => x"81ff0670",
+10990 => x"8c08fef8",
+10991 => x"050c5957",
+10992 => x"558c08fe",
+10993 => x"f405088c",
+10994 => x"08fef805",
+10995 => x"08575574",
+10996 => x"8c08fef4",
+10997 => x"050c758c",
+10998 => x"08fef805",
+10999 => x"0c8c08fe",
+11000 => x"f4050856",
+11001 => x"750b0b0b",
+11002 => x"81f8388c",
+11003 => x"08fef805",
+11004 => x"08577681",
+11005 => x"802e0981",
+11006 => x"060b0b0b",
+11007 => x"81e4388c",
+11008 => x"08f00508",
+11009 => x"982b8c08",
+11010 => x"f4050888",
+11011 => x"2a707207",
+11012 => x"8c08f005",
+11013 => x"08882a71",
+11014 => x"81065158",
+11015 => x"58585874",
+11016 => x"802e0b0b",
+11017 => x"0b82ef38",
+11018 => x"8c08f005",
+11019 => x"088c08f4",
+11020 => x"05085755",
+11021 => x"748c08fe",
+11022 => x"ec050c75",
+11023 => x"8c08fef0",
+11024 => x"050c8056",
+11025 => x"81805775",
+11026 => x"8c08fee4",
+11027 => x"050c768c",
+11028 => x"08fee805",
+11029 => x"0c8c08fe",
+11030 => x"f005088c",
+11031 => x"08fee805",
+11032 => x"08701270",
+11033 => x"8c08fee0",
+11034 => x"050c5256",
+11035 => x"57810b8c",
+11036 => x"08fed805",
+11037 => x"0c8c08fe",
+11038 => x"e005088c",
+11039 => x"08fef005",
+11040 => x"08585676",
+11041 => x"76260b0b",
+11042 => x"0b0b8938",
+11043 => x"800b8c08",
+11044 => x"fed8050c",
+11045 => x"8c08feec",
+11046 => x"05088c08",
+11047 => x"fee40508",
+11048 => x"7012708c",
+11049 => x"08fedc05",
+11050 => x"0c8c08fe",
+11051 => x"dc05088c",
+11052 => x"08fed805",
+11053 => x"0811708c",
+11054 => x"08fedc05",
+11055 => x"0c525a52",
+11056 => x"57558c08",
+11057 => x"fedc0508",
+11058 => x"8c08fee0",
+11059 => x"05085755",
+11060 => x"748c08f0",
+11061 => x"050c758c",
+11062 => x"08f4050c",
+11063 => x"0b0b0b81",
+11064 => x"b5398c08",
+11065 => x"f005088c",
+11066 => x"08f40508",
+11067 => x"5856758c",
+11068 => x"08fed005",
+11069 => x"0c768c08",
+11070 => x"fed4050c",
+11071 => x"805580ff",
+11072 => x"56748c08",
+11073 => x"fec8050c",
+11074 => x"758c08fe",
+11075 => x"cc050c8c",
+11076 => x"08fed405",
+11077 => x"088c08fe",
+11078 => x"cc050870",
+11079 => x"12708c08",
+11080 => x"fec4050c",
+11081 => x"52585681",
+11082 => x"0b8c08fe",
+11083 => x"bc050c8c",
+11084 => x"08fec405",
+11085 => x"088c08fe",
+11086 => x"d4050857",
+11087 => x"55757526",
+11088 => x"0b0b0b0b",
+11089 => x"8938800b",
+11090 => x"8c08febc",
+11091 => x"050c8c08",
+11092 => x"fed00508",
+11093 => x"8c08fec8",
+11094 => x"05087012",
+11095 => x"708c08fe",
+11096 => x"c0050c8c",
+11097 => x"08fec005",
+11098 => x"088c08fe",
+11099 => x"bc050811",
+11100 => x"708c08fe",
+11101 => x"c0050c53",
+11102 => x"59525657",
+11103 => x"8c08fec0",
+11104 => x"05088c08",
+11105 => x"fec40508",
+11106 => x"5755748c",
+11107 => x"08f0050c",
+11108 => x"758c08f4",
+11109 => x"050c8c08",
+11110 => x"f00508f8",
+11111 => x"0a260b0b",
+11112 => x"0b0b8738",
+11113 => x"0b0b0b0b",
+11114 => x"b5398c08",
+11115 => x"f005089f",
+11116 => x"2b8c08f4",
+11117 => x"0508812a",
+11118 => x"7072078c",
+11119 => x"08f00508",
+11120 => x"812a5858",
+11121 => x"5858748c",
+11122 => x"08f0050c",
+11123 => x"758c08f4",
+11124 => x"050c8c08",
+11125 => x"e8050881",
+11126 => x"058c08e8",
+11127 => x"050c8c08",
+11128 => x"f0050898",
+11129 => x"2b8c08f4",
+11130 => x"0508882a",
+11131 => x"7072078c",
+11132 => x"08f00508",
+11133 => x"882a5858",
+11134 => x"5858748c",
+11135 => x"08f0050c",
+11136 => x"758c08f4",
+11137 => x"050c8c08",
+11138 => x"f00508bf",
+11139 => x"ffff068c",
+11140 => x"08f8050c",
+11141 => x"8c08f405",
+11142 => x"08ff068c",
+11143 => x"08fc050c",
+11144 => x"8c08e805",
+11145 => x"08568070",
+11146 => x"8006778f",
+11147 => x"ff067094",
+11148 => x"2b535a58",
+11149 => x"55800b8c",
+11150 => x"08f80508",
+11151 => x"76078c08",
+11152 => x"f8050c70",
+11153 => x"8c08fc05",
+11154 => x"08078c08",
+11155 => x"fc050c8c",
+11156 => x"08ec0508",
+11157 => x"51568070",
+11158 => x"80067781",
+11159 => x"06709f2b",
+11160 => x"535a5855",
+11161 => x"800b8c08",
+11162 => x"f8050876",
+11163 => x"078c08f8",
+11164 => x"050c708c",
+11165 => x"08fc0508",
+11166 => x"078c08fc",
+11167 => x"050c568c",
+11168 => x"08f80508",
+11169 => x"8c08fc05",
+11170 => x"088c0888",
+11171 => x"05085957",
+11172 => x"5574770c",
+11173 => x"7584180c",
+11174 => x"8c088805",
+11175 => x"08800cbb",
+11176 => x"3d0d8c0c",
+11177 => x"048c0802",
+11178 => x"8c0c7070",
+11179 => x"800b8c08",
+11180 => x"fc050c8c",
+11181 => x"08880508",
+11182 => x"51700882",
+11183 => x"2e098106",
+11184 => x"0b0b0b0b",
+11185 => x"8838810b",
+11186 => x"8c08fc05",
+11187 => x"0c8c08fc",
+11188 => x"05087080",
+11189 => x"0c515050",
+11190 => x"8c0c048c",
+11191 => x"08028c0c",
+11192 => x"7070800b",
+11193 => x"8c08fc05",
+11194 => x"0c8c0888",
+11195 => x"05085170",
+11196 => x"08842e09",
+11197 => x"81060b0b",
+11198 => x"0b0b8838",
+11199 => x"810b8c08",
+11200 => x"fc050c8c",
+11201 => x"08fc0508",
+11202 => x"70800c51",
+11203 => x"50508c0c",
+11204 => x"048c0802",
+11205 => x"8c0c7070",
+11206 => x"800b8c08",
+11207 => x"fc050c8c",
+11208 => x"08880508",
+11209 => x"51700880",
+11210 => x"2e0b0b0b",
+11211 => x"0b97388c",
+11212 => x"08880508",
+11213 => x"51700881",
+11214 => x"2e0b0b0b",
+11215 => x"0b87380b",
+11216 => x"0b0b0b88",
+11217 => x"39810b8c",
+11218 => x"08fc050c",
+11219 => x"8c08fc05",
+11220 => x"0870800c",
+11221 => x"5150508c",
+11222 => x"0c048c08",
+11223 => x"028c0cf8",
+11224 => x"3d0d8c08",
+11225 => x"88050870",
+11226 => x"08bfffff",
+11227 => x"068c08f8",
+11228 => x"050c8411",
+11229 => x"08ff068c",
+11230 => x"08fc050c",
+11231 => x"8c088805",
+11232 => x"08700894",
+11233 => x"2a545451",
+11234 => x"80728fff",
+11235 => x"068c08f4",
+11236 => x"050c8c08",
+11237 => x"88050870",
+11238 => x"089f2a54",
+11239 => x"54518072",
+11240 => x"81068c08",
+11241 => x"f0050c8c",
+11242 => x"088c0508",
+11243 => x"8c08f005",
+11244 => x"0884120c",
+11245 => x"51518c08",
+11246 => x"f405080b",
+11247 => x"0b0b81cf",
+11248 => x"388c08f8",
+11249 => x"0508708c",
+11250 => x"08fc0508",
+11251 => x"07515170",
+11252 => x"0b0b0b0b",
+11253 => x"90388c08",
+11254 => x"8c050851",
+11255 => x"82710c0b",
+11256 => x"0b0b82f8",
+11257 => x"398c088c",
+11258 => x"05088c08",
+11259 => x"f40508f8",
+11260 => x"82058812",
+11261 => x"0c8c08fc",
+11262 => x"0508982a",
+11263 => x"8c08f805",
+11264 => x"08882b70",
+11265 => x"72078c08",
+11266 => x"fc050888",
+11267 => x"2b565355",
+11268 => x"5551708c",
+11269 => x"08f8050c",
+11270 => x"718c08fc",
+11271 => x"050c8c08",
+11272 => x"8c050851",
+11273 => x"83710c8c",
+11274 => x"08f80508",
+11275 => x"f00a260b",
+11276 => x"0b0b0bbb",
+11277 => x"388c08fc",
+11278 => x"05089f2a",
+11279 => x"8c08f805",
+11280 => x"08107072",
+11281 => x"078c08fc",
+11282 => x"05081055",
+11283 => x"53545470",
+11284 => x"8c08f805",
+11285 => x"0c718c08",
+11286 => x"fc050c8c",
+11287 => x"088c0508",
+11288 => x"881108ff",
+11289 => x"0588120c",
+11290 => x"510b0b0b",
+11291 => x"ffb9398c",
+11292 => x"088c0508",
+11293 => x"538c08f8",
+11294 => x"05088c08",
+11295 => x"fc050853",
+11296 => x"51708c14",
+11297 => x"0c719014",
+11298 => x"0c0b0b0b",
+11299 => x"81ce398c",
+11300 => x"08f40508",
+11301 => x"8fff2e09",
+11302 => x"81060b0b",
+11303 => x"0b80f438",
+11304 => x"8c08f805",
+11305 => x"08708c08",
+11306 => x"fc050807",
+11307 => x"5151700b",
+11308 => x"0b0b0b90",
+11309 => x"388c088c",
+11310 => x"05085184",
+11311 => x"710c0b0b",
+11312 => x"0b819939",
+11313 => x"8c08f805",
+11314 => x"08932a52",
+11315 => x"80728106",
+11316 => x"51517080",
+11317 => x"2e0b0b0b",
+11318 => x"0b90388c",
+11319 => x"088c0508",
+11320 => x"5181710c",
+11321 => x"0b0b0b0b",
+11322 => x"8a398c08",
+11323 => x"8c050851",
+11324 => x"80710c8c",
+11325 => x"088c0508",
+11326 => x"538c08f8",
+11327 => x"05088c08",
+11328 => x"fc050853",
+11329 => x"51708c14",
+11330 => x"0c719014",
+11331 => x"0c0b0b0b",
+11332 => x"80ca398c",
+11333 => x"088c0508",
+11334 => x"8c08f405",
+11335 => x"08f88105",
+11336 => x"88120c8c",
+11337 => x"088c0508",
+11338 => x"51518371",
+11339 => x"0c8c088c",
+11340 => x"05088c08",
+11341 => x"fc050898",
+11342 => x"2a8c08f8",
+11343 => x"0508882b",
+11344 => x"7072078c",
+11345 => x"08fc0508",
+11346 => x"882b7188",
+11347 => x"0a078c16",
+11348 => x"0c708007",
+11349 => x"90160c56",
+11350 => x"54555555",
+11351 => x"8a3d0d8c",
+11352 => x"0c048c08",
+11353 => x"028c0cf0",
+11354 => x"3d0d8c08",
+11355 => x"88050851",
+11356 => x"0b0b0b89",
+11357 => x"993f8008",
+11358 => x"52710b0b",
+11359 => x"0b0b9d38",
+11360 => x"8c088c05",
+11361 => x"08510b0b",
+11362 => x"0b89833f",
+11363 => x"80085271",
+11364 => x"0b0b0b0b",
+11365 => x"87380b0b",
+11366 => x"0b0b8e39",
+11367 => x"810b8c08",
+11368 => x"fc050c0b",
+11369 => x"0b0b87ed",
+11370 => x"398c0888",
+11371 => x"0508510b",
+11372 => x"0b0b88a4",
+11373 => x"3f800852",
+11374 => x"71802e0b",
+11375 => x"0b0b0bb9",
+11376 => x"388c088c",
+11377 => x"0508510b",
+11378 => x"0b0b888c",
+11379 => x"3f800852",
+11380 => x"71802e0b",
+11381 => x"0b0b0ba1",
+11382 => x"388c088c",
+11383 => x"05088c08",
+11384 => x"88050884",
+11385 => x"12088412",
+11386 => x"0831708c",
+11387 => x"08fc050c",
+11388 => x"5254520b",
+11389 => x"0b0b879d",
+11390 => x"398c0888",
+11391 => x"0508510b",
+11392 => x"0b0b87d4",
+11393 => x"3f800852",
+11394 => x"71802e0b",
+11395 => x"0b0b0bb6",
+11396 => x"388c0888",
+11397 => x"05085284",
+11398 => x"1208802e",
+11399 => x"0b0b0b0b",
+11400 => x"8e38ff0b",
+11401 => x"8c08f805",
+11402 => x"0c0b0b0b",
+11403 => x"0b883981",
+11404 => x"0b8c08f8",
+11405 => x"050c8c08",
+11406 => x"f805088c",
+11407 => x"08fc050c",
+11408 => x"0b0b0b86",
+11409 => x"d0398c08",
+11410 => x"8c050851",
+11411 => x"0b0b0b87",
+11412 => x"873f8008",
+11413 => x"5271802e",
+11414 => x"0b0b0b0b",
+11415 => x"b6388c08",
+11416 => x"8c050852",
+11417 => x"84120880",
+11418 => x"2e0b0b0b",
+11419 => x"0b8e3881",
+11420 => x"0b8c08f4",
+11421 => x"050c0b0b",
+11422 => x"0b0b8839",
+11423 => x"ff0b8c08",
+11424 => x"f4050c8c",
+11425 => x"08f40508",
+11426 => x"8c08fc05",
+11427 => x"0c0b0b0b",
+11428 => x"8683398c",
+11429 => x"08880508",
+11430 => x"510b0b0b",
+11431 => x"86843f80",
+11432 => x"08527180",
+11433 => x"2e0b0b0b",
+11434 => x"0ba6388c",
+11435 => x"088c0508",
+11436 => x"510b0b0b",
+11437 => x"85ec3f80",
+11438 => x"08527180",
+11439 => x"2e0b0b0b",
+11440 => x"0b8e3880",
+11441 => x"0b8c08fc",
+11442 => x"050c0b0b",
+11443 => x"0b85c639",
+11444 => x"8c088805",
+11445 => x"08510b0b",
+11446 => x"0b85c73f",
+11447 => x"80085271",
+11448 => x"802e0b0b",
+11449 => x"0b0bb638",
+11450 => x"8c088c05",
+11451 => x"08528412",
+11452 => x"08802e0b",
+11453 => x"0b0b0b8e",
+11454 => x"38810b8c",
+11455 => x"08f0050c",
+11456 => x"0b0b0b0b",
+11457 => x"8839ff0b",
+11458 => x"8c08f005",
+11459 => x"0c8c08f0",
+11460 => x"05088c08",
+11461 => x"fc050c0b",
+11462 => x"0b0b84f9",
+11463 => x"398c088c",
+11464 => x"0508510b",
+11465 => x"0b0b84fa",
+11466 => x"3f800852",
+11467 => x"71802e0b",
+11468 => x"0b0b0bb6",
+11469 => x"388c0888",
+11470 => x"05085284",
+11471 => x"1208802e",
+11472 => x"0b0b0b0b",
+11473 => x"8e38ff0b",
+11474 => x"8c08ec05",
+11475 => x"0c0b0b0b",
+11476 => x"0b883981",
+11477 => x"0b8c08ec",
+11478 => x"050c8c08",
+11479 => x"ec05088c",
+11480 => x"08fc050c",
+11481 => x"0b0b0b84",
+11482 => x"ac398c08",
+11483 => x"8805088c",
+11484 => x"088c0508",
+11485 => x"53538413",
+11486 => x"08841308",
+11487 => x"2e0b0b0b",
+11488 => x"0bb6388c",
+11489 => x"08880508",
+11490 => x"52841208",
+11491 => x"802e0b0b",
+11492 => x"0b0b8e38",
+11493 => x"ff0b8c08",
+11494 => x"e8050c0b",
+11495 => x"0b0b0b88",
+11496 => x"39810b8c",
+11497 => x"08e8050c",
+11498 => x"8c08e805",
+11499 => x"088c08fc",
+11500 => x"050c0b0b",
+11501 => x"0b83de39",
+11502 => x"8c088805",
+11503 => x"088c088c",
+11504 => x"05085353",
+11505 => x"88120888",
+11506 => x"1408250b",
+11507 => x"0b0b0bb6",
+11508 => x"388c0888",
+11509 => x"05085284",
+11510 => x"1208802e",
+11511 => x"0b0b0b0b",
+11512 => x"8e38ff0b",
+11513 => x"8c08e405",
+11514 => x"0c0b0b0b",
+11515 => x"0b883981",
+11516 => x"0b8c08e4",
+11517 => x"050c8c08",
+11518 => x"e405088c",
+11519 => x"08fc050c",
+11520 => x"0b0b0b83",
+11521 => x"90398c08",
+11522 => x"8805088c",
+11523 => x"088c0508",
+11524 => x"53538813",
+11525 => x"08881308",
+11526 => x"250b0b0b",
+11527 => x"0bb6388c",
+11528 => x"08880508",
+11529 => x"52841208",
+11530 => x"802e0b0b",
+11531 => x"0b0b8e38",
+11532 => x"810b8c08",
+11533 => x"e0050c0b",
+11534 => x"0b0b0b88",
+11535 => x"39ff0b8c",
+11536 => x"08e0050c",
+11537 => x"8c08e005",
+11538 => x"088c08fc",
+11539 => x"050c0b0b",
+11540 => x"0b82c239",
+11541 => x"8c088805",
+11542 => x"088c08dc",
+11543 => x"050c8c08",
+11544 => x"8c05088c",
+11545 => x"08d8050c",
+11546 => x"8c08dc05",
+11547 => x"088c08d8",
+11548 => x"05085452",
+11549 => x"8c12088c",
+11550 => x"1408260b",
+11551 => x"0b0b0bbc",
+11552 => x"388c08dc",
+11553 => x"05088c08",
+11554 => x"d8050854",
+11555 => x"528c1208",
+11556 => x"8c14082e",
+11557 => x"0981060b",
+11558 => x"0b0b80d5",
+11559 => x"388c08dc",
+11560 => x"05088c08",
+11561 => x"d8050854",
+11562 => x"52901208",
+11563 => x"90140826",
+11564 => x"0b0b0b0b",
+11565 => x"87380b0b",
+11566 => x"0b0bb639",
+11567 => x"8c088805",
+11568 => x"08528412",
+11569 => x"08802e0b",
+11570 => x"0b0b0b8e",
+11571 => x"38ff0b8c",
+11572 => x"08d4050c",
+11573 => x"0b0b0b0b",
+11574 => x"8839810b",
+11575 => x"8c08d405",
+11576 => x"0c8c08d4",
+11577 => x"05088c08",
+11578 => x"fc050c0b",
+11579 => x"0b0b81a5",
+11580 => x"398c088c",
+11581 => x"05088c08",
+11582 => x"d0050c8c",
+11583 => x"08880508",
+11584 => x"8c08cc05",
+11585 => x"0c8c08d0",
+11586 => x"05088c08",
+11587 => x"cc050854",
+11588 => x"528c1208",
+11589 => x"8c140826",
+11590 => x"0b0b0b0b",
+11591 => x"bc388c08",
+11592 => x"d005088c",
+11593 => x"08cc0508",
+11594 => x"54528c12",
+11595 => x"088c1408",
+11596 => x"2e098106",
+11597 => x"0b0b0b80",
+11598 => x"d5388c08",
+11599 => x"d005088c",
+11600 => x"08cc0508",
+11601 => x"54529012",
+11602 => x"08901408",
+11603 => x"260b0b0b",
+11604 => x"0b87380b",
+11605 => x"0b0b0bb6",
+11606 => x"398c0888",
+11607 => x"05085284",
+11608 => x"1208802e",
+11609 => x"0b0b0b0b",
+11610 => x"8e38810b",
+11611 => x"8c08c805",
+11612 => x"0c0b0b0b",
+11613 => x"0b8839ff",
+11614 => x"0b8c08c8",
+11615 => x"050c8c08",
+11616 => x"c805088c",
+11617 => x"08fc050c",
+11618 => x"0b0b0b0b",
+11619 => x"8839800b",
+11620 => x"8c08fc05",
+11621 => x"0c8c08fc",
+11622 => x"0508800c",
+11623 => x"923d0d8c",
+11624 => x"0c048c08",
+11625 => x"028c0c70",
+11626 => x"70800b8c",
+11627 => x"08fc050c",
+11628 => x"8c088805",
+11629 => x"08517008",
+11630 => x"822e0981",
+11631 => x"060b0b0b",
+11632 => x"0b883881",
+11633 => x"0b8c08fc",
+11634 => x"050c8c08",
+11635 => x"fc050870",
+11636 => x"800c5150",
+11637 => x"508c0c04",
+11638 => x"8c08028c",
+11639 => x"0c707080",
+11640 => x"0b8c08fc",
+11641 => x"050c8c08",
+11642 => x"88050851",
+11643 => x"7008842e",
+11644 => x"0981060b",
+11645 => x"0b0b0b88",
+11646 => x"38810b8c",
+11647 => x"08fc050c",
+11648 => x"8c08fc05",
+11649 => x"0870800c",
+11650 => x"5150508c",
+11651 => x"0c048c08",
+11652 => x"028c0c70",
+11653 => x"70800b8c",
+11654 => x"08fc050c",
+11655 => x"8c088805",
+11656 => x"08517008",
+11657 => x"802e0b0b",
+11658 => x"0b0b9738",
+11659 => x"8c088805",
+11660 => x"08517008",
+11661 => x"812e0b0b",
+11662 => x"0b0b8738",
+11663 => x"0b0b0b0b",
+11664 => x"8839810b",
+11665 => x"8c08fc05",
+11666 => x"0c8c08fc",
+11667 => x"05087080",
+11668 => x"0c515050",
+11669 => x"8c0c0470",
+11670 => x"700b0b83",
+11671 => x"84d80bfc",
+11672 => x"05700852",
+11673 => x"5270ff2e",
+11674 => x"0b0b0b0b",
+11675 => x"9538702d",
+11676 => x"fc127008",
+11677 => x"525270ff",
+11678 => x"2e098106",
+11679 => x"0b0b0b0b",
+11680 => x"ed385050",
+11681 => x"04040b0b",
+11682 => x"fd9e993f",
+11683 => x"04000000",
+11684 => x"00000040",
+11685 => x"48656c6c",
+11686 => x"6f20776f",
+11687 => x"726c6421",
+11688 => x"0a000000",
+11689 => x"20202020",
+11690 => x"20202020",
+11691 => x"20202020",
+11692 => x"20202020",
+11693 => x"30303030",
+11694 => x"30303030",
+11695 => x"30303030",
+11696 => x"30303030",
+11697 => x"0000164c",
+11698 => x"000010d6",
+11699 => x"000010d6",
+11700 => x"0000163f",
+11701 => x"000010d6",
+11702 => x"000010d6",
+11703 => x"000010d6",
+11704 => x"000010d6",
+11705 => x"000010d6",
+11706 => x"000010d6",
+11707 => x"000010a4",
+11708 => x"000015c6",
+11709 => x"000010d6",
+11710 => x"000010b9",
+11711 => x"000012d9",
+11712 => x"000010d6",
+11713 => x"000015fe",
+11714 => x"000015d5",
+11715 => x"000015d5",
+11716 => x"000015d5",
+11717 => x"000015d5",
+11718 => x"000015d5",
+11719 => x"000015d5",
+11720 => x"000015d5",
+11721 => x"000015d5",
+11722 => x"000015d5",
+11723 => x"000010d6",
+11724 => x"000010d6",
+11725 => x"000010d6",
+11726 => x"000010d6",
+11727 => x"000010d6",
+11728 => x"000010d6",
+11729 => x"000010d6",
+11730 => x"000010d6",
+11731 => x"000010d6",
+11732 => x"00001476",
+11733 => x"00001060",
+11734 => x"000013e5",
+11735 => x"000010d6",
+11736 => x"000013e5",
+11737 => x"000010d6",
+11738 => x"000010d6",
+11739 => x"000010d6",
+11740 => x"000010d6",
+11741 => x"0000160c",
+11742 => x"000010d6",
+11743 => x"000010d6",
+11744 => x"00001024",
+11745 => x"000010d6",
+11746 => x"000010d6",
+11747 => x"000010d6",
+11748 => x"0000152a",
+11749 => x"000010d6",
+11750 => x"00000ce0",
+11751 => x"000010d6",
+11752 => x"000010d6",
+11753 => x"000014d2",
+11754 => x"000010d6",
+11755 => x"000010d6",
+11756 => x"000010d6",
+11757 => x"000010d6",
+11758 => x"000010d6",
+11759 => x"000010d6",
+11760 => x"000010d6",
+11761 => x"000010d6",
+11762 => x"000010d6",
+11763 => x"000010d6",
+11764 => x"00001476",
+11765 => x"00001064",
+11766 => x"000013e5",
+11767 => x"000013e5",
+11768 => x"000013e5",
+11769 => x"000013d7",
+11770 => x"00001064",
+11771 => x"000010d6",
+11772 => x"000010d6",
+11773 => x"000012b5",
+11774 => x"000010d6",
+11775 => x"00001592",
+11776 => x"00001028",
+11777 => x"0000132c",
+11778 => x"000010c9",
+11779 => x"000010d6",
+11780 => x"0000152a",
+11781 => x"000010d6",
+11782 => x"00000ce4",
+11783 => x"000010d6",
+11784 => x"000010d6",
+11785 => x"00001619",
+11786 => x"62756720",
+11787 => x"696e2076",
+11788 => x"66707269",
+11789 => x"6e74663a",
+11790 => x"20626164",
+11791 => x"20626173",
+11792 => x"65000000",
+11793 => x"30313233",
+11794 => x"34353637",
+11795 => x"38396162",
+11796 => x"63646566",
+11797 => x"00000000",
+11798 => x"496e6600",
+11799 => x"30313233",
+11800 => x"34353637",
+11801 => x"38394142",
+11802 => x"43444546",
+11803 => x"00000000",
+11804 => x"30000000",
+11805 => x"2e000000",
+11806 => x"4e614e00",
+11807 => x"286e756c",
+11808 => x"6c290000",
+11809 => x"432d5554",
+11810 => x"462d3800",
+11811 => x"432d534a",
+11812 => x"49530000",
+11813 => x"432d4555",
+11814 => x"434a5000",
+11815 => x"432d4a49",
+11816 => x"53000000",
+11817 => x"496e6669",
+11818 => x"6e697479",
+11819 => x"00000000",
+11820 => x"000037a9",
+11821 => x"000037a9",
+11822 => x"0000378d",
+11823 => x"000031e6",
+11824 => x"00003792",
+11825 => x"000031eb",
+11826 => x"43000000",
+11827 => x"49534f2d",
+11828 => x"38383539",
+11829 => x"2d310000",
+11830 => x"0000b874",
+11831 => x"0000b86c",
+11832 => x"0000b86c",
+11833 => x"0000b86c",
+11834 => x"0000b86c",
+11835 => x"0000b86c",
+11836 => x"0000b86c",
+11837 => x"0000b86c",
+11838 => x"0000b86c",
+11839 => x"0000b86c",
+11840 => x"ffffffff",
+11841 => x"ffffffff",
+11842 => x"3c9cd2b2",
+11843 => x"97d889bc",
+11844 => x"3949f623",
+11845 => x"d5a8a733",
+11846 => x"32a50ffd",
+11847 => x"44f4a73d",
+11848 => x"255bba08",
+11849 => x"cf8c979d",
+11850 => x"0ac80628",
+11851 => x"64ac6f43",
+11852 => x"4341c379",
+11853 => x"37e08000",
+11854 => x"4693b8b5",
+11855 => x"b5056e17",
+11856 => x"4d384f03",
+11857 => x"e93ff9f5",
+11858 => x"5a827748",
+11859 => x"f9301d32",
+11860 => x"75154fdd",
+11861 => x"7f73bf3c",
+11862 => x"3ff00000",
+11863 => x"00000000",
+11864 => x"40240000",
+11865 => x"00000000",
+11866 => x"40590000",
+11867 => x"00000000",
+11868 => x"408f4000",
+11869 => x"00000000",
+11870 => x"40c38800",
+11871 => x"00000000",
+11872 => x"40f86a00",
+11873 => x"00000000",
+11874 => x"412e8480",
+11875 => x"00000000",
+11876 => x"416312d0",
+11877 => x"00000000",
+11878 => x"4197d784",
+11879 => x"00000000",
+11880 => x"41cdcd65",
+11881 => x"00000000",
+11882 => x"4202a05f",
+11883 => x"20000000",
+11884 => x"42374876",
+11885 => x"e8000000",
+11886 => x"426d1a94",
+11887 => x"a2000000",
+11888 => x"42a2309c",
+11889 => x"e5400000",
+11890 => x"42d6bcc4",
+11891 => x"1e900000",
+11892 => x"430c6bf5",
+11893 => x"26340000",
+11894 => x"4341c379",
+11895 => x"37e08000",
+11896 => x"43763457",
+11897 => x"85d8a000",
+11898 => x"43abc16d",
+11899 => x"674ec800",
+11900 => x"43e158e4",
+11901 => x"60913d00",
+11902 => x"4415af1d",
+11903 => x"78b58c40",
+11904 => x"444b1ae4",
+11905 => x"d6e2ef50",
+11906 => x"4480f0cf",
+11907 => x"064dd592",
+11908 => x"44b52d02",
+11909 => x"c7e14af6",
+11910 => x"44ea7843",
+11911 => x"79d99db4",
+11912 => x"00000005",
+11913 => x"00000019",
+11914 => x"0000007d",
+11915 => x"64756d6d",
+11916 => x"792e6578",
+11917 => x"65000000",
+11918 => x"00000000",
+11919 => x"00000000",
+11920 => x"00000000",
+11921 => x"00000000",
+11922 => x"00000000",
+11923 => x"00ffffff",
+11924 => x"ff00ffff",
+11925 => x"ffff00ff",
+11926 => x"ffffff00",
+11927 => x"00000000",
+11928 => x"00000000",
+11929 => x"00000000",
+11930 => x"0000c260",
+11931 => x"0000ba70",
+11932 => x"00000000",
+11933 => x"0000bcd8",
+11934 => x"0000bd34",
+11935 => x"0000bd90",
+11936 => x"00000000",
+11937 => x"00000000",
+11938 => x"00000000",
+11939 => x"00000000",
+11940 => x"00000000",
+11941 => x"00000000",
+11942 => x"00000000",
+11943 => x"00000000",
+11944 => x"00000000",
+11945 => x"0000b8c8",
+11946 => x"00000000",
+11947 => x"00000000",
+11948 => x"00000000",
+11949 => x"00000000",
+11950 => x"00000000",
+11951 => x"00000000",
+11952 => x"00000000",
+11953 => x"00000000",
+11954 => x"00000000",
+11955 => x"00000000",
+11956 => x"00000000",
+11957 => x"00000000",
+11958 => x"00000000",
+11959 => x"00000000",
+11960 => x"00000000",
+11961 => x"00000000",
+11962 => x"00000000",
+11963 => x"00000000",
+11964 => x"00000000",
+11965 => x"00000000",
+11966 => x"00000000",
+11967 => x"00000000",
+11968 => x"00000000",
+11969 => x"00000000",
+11970 => x"00000000",
+11971 => x"00000000",
+11972 => x"00000000",
+11973 => x"00000000",
+11974 => x"00000001",
+11975 => x"330eabcd",
+11976 => x"1234e66d",
+11977 => x"deec0005",
+11978 => x"000b0000",
+11979 => x"00000000",
+11980 => x"00000000",
+11981 => x"00000000",
+11982 => x"00000000",
+11983 => x"00000000",
+11984 => x"00000000",
+11985 => x"00000000",
+11986 => x"00000000",
+11987 => x"00000000",
+11988 => x"00000000",
+11989 => x"00000000",
+11990 => x"00000000",
+11991 => x"00000000",
+11992 => x"00000000",
+11993 => x"00000000",
+11994 => x"00000000",
+11995 => x"00000000",
+11996 => x"00000000",
+11997 => x"00000000",
+11998 => x"00000000",
+11999 => x"00000000",
+12000 => x"00000000",
+12001 => x"00000000",
+12002 => x"00000000",
+12003 => x"00000000",
+12004 => x"00000000",
+12005 => x"00000000",
+12006 => x"00000000",
+12007 => x"00000000",
+12008 => x"00000000",
+12009 => x"00000000",
+12010 => x"00000000",
+12011 => x"00000000",
+12012 => x"00000000",
+12013 => x"00000000",
+12014 => x"00000000",
+12015 => x"00000000",
+12016 => x"00000000",
+12017 => x"00000000",
+12018 => x"00000000",
+12019 => x"00000000",
+12020 => x"00000000",
+12021 => x"00000000",
+12022 => x"00000000",
+12023 => x"00000000",
+12024 => x"00000000",
+12025 => x"00000000",
+12026 => x"00000000",
+12027 => x"00000000",
+12028 => x"00000000",
+12029 => x"00000000",
+12030 => x"00000000",
+12031 => x"00000000",
+12032 => x"00000000",
+12033 => x"00000000",
+12034 => x"00000000",
+12035 => x"00000000",
+12036 => x"00000000",
+12037 => x"00000000",
+12038 => x"00000000",
+12039 => x"00000000",
+12040 => x"00000000",
+12041 => x"00000000",
+12042 => x"00000000",
+12043 => x"00000000",
+12044 => x"00000000",
+12045 => x"00000000",
+12046 => x"00000000",
+12047 => x"00000000",
+12048 => x"00000000",
+12049 => x"00000000",
+12050 => x"00000000",
+12051 => x"00000000",
+12052 => x"00000000",
+12053 => x"00000000",
+12054 => x"00000000",
+12055 => x"00000000",
+12056 => x"00000000",
+12057 => x"00000000",
+12058 => x"00000000",
+12059 => x"00000000",
+12060 => x"00000000",
+12061 => x"00000000",
+12062 => x"00000000",
+12063 => x"00000000",
+12064 => x"00000000",
+12065 => x"00000000",
+12066 => x"00000000",
+12067 => x"00000000",
+12068 => x"00000000",
+12069 => x"00000000",
+12070 => x"00000000",
+12071 => x"00000000",
+12072 => x"00000000",
+12073 => x"00000000",
+12074 => x"00000000",
+12075 => x"00000000",
+12076 => x"00000000",
+12077 => x"00000000",
+12078 => x"00000000",
+12079 => x"00000000",
+12080 => x"00000000",
+12081 => x"00000000",
+12082 => x"00000000",
+12083 => x"00000000",
+12084 => x"00000000",
+12085 => x"00000000",
+12086 => x"00000000",
+12087 => x"00000000",
+12088 => x"00000000",
+12089 => x"00000000",
+12090 => x"00000000",
+12091 => x"00000000",
+12092 => x"00000000",
+12093 => x"00000000",
+12094 => x"00000000",
+12095 => x"00000000",
+12096 => x"00000000",
+12097 => x"00000000",
+12098 => x"00000000",
+12099 => x"00000000",
+12100 => x"00000000",
+12101 => x"00000000",
+12102 => x"00000000",
+12103 => x"00000000",
+12104 => x"00000000",
+12105 => x"00000000",
+12106 => x"00000000",
+12107 => x"00000000",
+12108 => x"00000000",
+12109 => x"00000000",
+12110 => x"00000000",
+12111 => x"00000000",
+12112 => x"00000000",
+12113 => x"00000000",
+12114 => x"00000000",
+12115 => x"00000000",
+12116 => x"00000000",
+12117 => x"00000000",
+12118 => x"00000000",
+12119 => x"00000000",
+12120 => x"00000000",
+12121 => x"00000000",
+12122 => x"00000000",
+12123 => x"00000000",
+12124 => x"00000000",
+12125 => x"00000000",
+12126 => x"00000000",
+12127 => x"00000000",
+12128 => x"00000000",
+12129 => x"00000000",
+12130 => x"00000000",
+12131 => x"00000000",
+12132 => x"00000000",
+12133 => x"00000000",
+12134 => x"00000000",
+12135 => x"00000000",
+12136 => x"00000000",
+12137 => x"00000000",
+12138 => x"00000000",
+12139 => x"00000000",
+12140 => x"00000000",
+12141 => x"00000000",
+12142 => x"00000000",
+12143 => x"00000000",
+12144 => x"00000000",
+12145 => x"00000000",
+12146 => x"00000000",
+12147 => x"00000000",
+12148 => x"00000000",
+12149 => x"00000000",
+12150 => x"00000000",
+12151 => x"00000000",
+12152 => x"00000000",
+12153 => x"00000000",
+12154 => x"00000000",
+12155 => x"43000000",
+12156 => x"00000000",
+12157 => x"00000000",
+12158 => x"00000000",
+12159 => x"00000000",
+12160 => x"00000000",
+12161 => x"00000001",
+12162 => x"0000b8cc",
+12163 => x"00000000",
+12164 => x"00000000",
+12165 => x"00000000",
+12166 => x"00000000",
+12167 => x"00000000",
+12168 => x"00000000",
+12169 => x"00000000",
+12170 => x"00000000",
+12171 => x"00000000",
+12172 => x"00000000",
+12173 => x"00000000",
+12174 => x"00000000",
+12175 => x"ffffffff",
+12176 => x"00000000",
+12177 => x"00020000",
+12178 => x"00000000",
+12179 => x"00000000",
+12180 => x"0000be48",
+12181 => x"0000be48",
+12182 => x"0000be50",
+12183 => x"0000be50",
+12184 => x"0000be58",
+12185 => x"0000be58",
+12186 => x"0000be60",
+12187 => x"0000be60",
+12188 => x"0000be68",
+12189 => x"0000be68",
+12190 => x"0000be70",
+12191 => x"0000be70",
+12192 => x"0000be78",
+12193 => x"0000be78",
+12194 => x"0000be80",
+12195 => x"0000be80",
+12196 => x"0000be88",
+12197 => x"0000be88",
+12198 => x"0000be90",
+12199 => x"0000be90",
+12200 => x"0000be98",
+12201 => x"0000be98",
+12202 => x"0000bea0",
+12203 => x"0000bea0",
+12204 => x"0000bea8",
+12205 => x"0000bea8",
+12206 => x"0000beb0",
+12207 => x"0000beb0",
+12208 => x"0000beb8",
+12209 => x"0000beb8",
+12210 => x"0000bec0",
+12211 => x"0000bec0",
+12212 => x"0000bec8",
+12213 => x"0000bec8",
+12214 => x"0000bed0",
+12215 => x"0000bed0",
+12216 => x"0000bed8",
+12217 => x"0000bed8",
+12218 => x"0000bee0",
+12219 => x"0000bee0",
+12220 => x"0000bee8",
+12221 => x"0000bee8",
+12222 => x"0000bef0",
+12223 => x"0000bef0",
+12224 => x"0000bef8",
+12225 => x"0000bef8",
+12226 => x"0000bf00",
+12227 => x"0000bf00",
+12228 => x"0000bf08",
+12229 => x"0000bf08",
+12230 => x"0000bf10",
+12231 => x"0000bf10",
+12232 => x"0000bf18",
+12233 => x"0000bf18",
+12234 => x"0000bf20",
+12235 => x"0000bf20",
+12236 => x"0000bf28",
+12237 => x"0000bf28",
+12238 => x"0000bf30",
+12239 => x"0000bf30",
+12240 => x"0000bf38",
+12241 => x"0000bf38",
+12242 => x"0000bf40",
+12243 => x"0000bf40",
+12244 => x"0000bf48",
+12245 => x"0000bf48",
+12246 => x"0000bf50",
+12247 => x"0000bf50",
+12248 => x"0000bf58",
+12249 => x"0000bf58",
+12250 => x"0000bf60",
+12251 => x"0000bf60",
+12252 => x"0000bf68",
+12253 => x"0000bf68",
+12254 => x"0000bf70",
+12255 => x"0000bf70",
+12256 => x"0000bf78",
+12257 => x"0000bf78",
+12258 => x"0000bf80",
+12259 => x"0000bf80",
+12260 => x"0000bf88",
+12261 => x"0000bf88",
+12262 => x"0000bf90",
+12263 => x"0000bf90",
+12264 => x"0000bf98",
+12265 => x"0000bf98",
+12266 => x"0000bfa0",
+12267 => x"0000bfa0",
+12268 => x"0000bfa8",
+12269 => x"0000bfa8",
+12270 => x"0000bfb0",
+12271 => x"0000bfb0",
+12272 => x"0000bfb8",
+12273 => x"0000bfb8",
+12274 => x"0000bfc0",
+12275 => x"0000bfc0",
+12276 => x"0000bfc8",
+12277 => x"0000bfc8",
+12278 => x"0000bfd0",
+12279 => x"0000bfd0",
+12280 => x"0000bfd8",
+12281 => x"0000bfd8",
+12282 => x"0000bfe0",
+12283 => x"0000bfe0",
+12284 => x"0000bfe8",
+12285 => x"0000bfe8",
+12286 => x"0000bff0",
+12287 => x"0000bff0",
+12288 => x"0000bff8",
+12289 => x"0000bff8",
+12290 => x"0000c000",
+12291 => x"0000c000",
+12292 => x"0000c008",
+12293 => x"0000c008",
+12294 => x"0000c010",
+12295 => x"0000c010",
+12296 => x"0000c018",
+12297 => x"0000c018",
+12298 => x"0000c020",
+12299 => x"0000c020",
+12300 => x"0000c028",
+12301 => x"0000c028",
+12302 => x"0000c030",
+12303 => x"0000c030",
+12304 => x"0000c038",
+12305 => x"0000c038",
+12306 => x"0000c040",
+12307 => x"0000c040",
+12308 => x"0000c048",
+12309 => x"0000c048",
+12310 => x"0000c050",
+12311 => x"0000c050",
+12312 => x"0000c058",
+12313 => x"0000c058",
+12314 => x"0000c060",
+12315 => x"0000c060",
+12316 => x"0000c068",
+12317 => x"0000c068",
+12318 => x"0000c070",
+12319 => x"0000c070",
+12320 => x"0000c078",
+12321 => x"0000c078",
+12322 => x"0000c080",
+12323 => x"0000c080",
+12324 => x"0000c088",
+12325 => x"0000c088",
+12326 => x"0000c090",
+12327 => x"0000c090",
+12328 => x"0000c098",
+12329 => x"0000c098",
+12330 => x"0000c0a0",
+12331 => x"0000c0a0",
+12332 => x"0000c0a8",
+12333 => x"0000c0a8",
+12334 => x"0000c0b0",
+12335 => x"0000c0b0",
+12336 => x"0000c0b8",
+12337 => x"0000c0b8",
+12338 => x"0000c0c0",
+12339 => x"0000c0c0",
+12340 => x"0000c0c8",
+12341 => x"0000c0c8",
+12342 => x"0000c0d0",
+12343 => x"0000c0d0",
+12344 => x"0000c0d8",
+12345 => x"0000c0d8",
+12346 => x"0000c0e0",
+12347 => x"0000c0e0",
+12348 => x"0000c0e8",
+12349 => x"0000c0e8",
+12350 => x"0000c0f0",
+12351 => x"0000c0f0",
+12352 => x"0000c0f8",
+12353 => x"0000c0f8",
+12354 => x"0000c100",
+12355 => x"0000c100",
+12356 => x"0000c108",
+12357 => x"0000c108",
+12358 => x"0000c110",
+12359 => x"0000c110",
+12360 => x"0000c118",
+12361 => x"0000c118",
+12362 => x"0000c120",
+12363 => x"0000c120",
+12364 => x"0000c128",
+12365 => x"0000c128",
+12366 => x"0000c130",
+12367 => x"0000c130",
+12368 => x"0000c138",
+12369 => x"0000c138",
+12370 => x"0000c140",
+12371 => x"0000c140",
+12372 => x"0000c148",
+12373 => x"0000c148",
+12374 => x"0000c150",
+12375 => x"0000c150",
+12376 => x"0000c158",
+12377 => x"0000c158",
+12378 => x"0000c160",
+12379 => x"0000c160",
+12380 => x"0000c168",
+12381 => x"0000c168",
+12382 => x"0000c170",
+12383 => x"0000c170",
+12384 => x"0000c178",
+12385 => x"0000c178",
+12386 => x"0000c180",
+12387 => x"0000c180",
+12388 => x"0000c188",
+12389 => x"0000c188",
+12390 => x"0000c190",
+12391 => x"0000c190",
+12392 => x"0000c198",
+12393 => x"0000c198",
+12394 => x"0000c1a0",
+12395 => x"0000c1a0",
+12396 => x"0000c1a8",
+12397 => x"0000c1a8",
+12398 => x"0000c1b0",
+12399 => x"0000c1b0",
+12400 => x"0000c1b8",
+12401 => x"0000c1b8",
+12402 => x"0000c1c0",
+12403 => x"0000c1c0",
+12404 => x"0000c1c8",
+12405 => x"0000c1c8",
+12406 => x"0000c1d0",
+12407 => x"0000c1d0",
+12408 => x"0000c1d8",
+12409 => x"0000c1d8",
+12410 => x"0000c1e0",
+12411 => x"0000c1e0",
+12412 => x"0000c1e8",
+12413 => x"0000c1e8",
+12414 => x"0000c1f0",
+12415 => x"0000c1f0",
+12416 => x"0000c1f8",
+12417 => x"0000c1f8",
+12418 => x"0000c200",
+12419 => x"0000c200",
+12420 => x"0000c208",
+12421 => x"0000c208",
+12422 => x"0000c210",
+12423 => x"0000c210",
+12424 => x"0000c218",
+12425 => x"0000c218",
+12426 => x"0000c220",
+12427 => x"0000c220",
+12428 => x"0000c228",
+12429 => x"0000c228",
+12430 => x"0000c230",
+12431 => x"0000c230",
+12432 => x"0000c238",
+12433 => x"0000c238",
+12434 => x"0000c240",
+12435 => x"0000c240",
+12436 => x"0000ba2c",
+12437 => x"ffffffff",
+12438 => x"00000000",
+12439 => x"ffffffff",
+12440 => x"00000000",
diff --git a/zpu/sw/helloworld/hello.c b/zpu/sw/helloworld/hello.c
new file mode 100644
index 0000000..e9cc61e
--- /dev/null
+++ b/zpu/sw/helloworld/hello.c
@@ -0,0 +1,6 @@
+// To compile: zpu-elf-gcc test.c -o test.elf -phi
+// To run:
+int main(int argc, char **argv)
+{
+ printf("Hello world!\n");
+}
diff --git a/zpu/sw/helloworld/hello.elf b/zpu/sw/helloworld/hello.elf
new file mode 100644
index 0000000..be3c093
--- /dev/null
+++ b/zpu/sw/helloworld/hello.elf
Binary files differ
diff --git a/zpu/sw/setup.sh b/zpu/sw/setup.sh
new file mode 100644
index 0000000..57747f8
--- /dev/null
+++ b/zpu/sw/setup.sh
@@ -0,0 +1,6 @@
+. env.sh
+rm -rf /tmp/zpu
+mkdir -p /tmp/zpu/install/bin
+cd /tmp/zpu
+unzip $ZPUSW/tools/zputoolchain.zip
+
diff --git a/zpu/sw/simulator/.classpath b/zpu/sw/simulator/.classpath
new file mode 100644
index 0000000..5e4fa9f
--- /dev/null
+++ b/zpu/sw/simulator/.classpath
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<classpath>
+ <classpathentry excluding="bin/" kind="src" output="bin" path=""/>
+ <classpathentry kind="con" path="org.eclipse.jdt.launching.JRE_CONTAINER"/>
+ <classpathentry kind="con" path="org.eclipse.pde.core.requiredPlugins"/>
+ <classpathentry kind="output" path=""/>
+</classpath>
diff --git a/zpu/sw/simulator/.project b/zpu/sw/simulator/.project
new file mode 100644
index 0000000..29c7a4f
--- /dev/null
+++ b/zpu/sw/simulator/.project
@@ -0,0 +1,28 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>simulator</name>
+ <comment></comment>
+ <projects>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.jdt.core.javabuilder</name>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>org.eclipse.pde.ManifestBuilder</name>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>org.eclipse.pde.SchemaBuilder</name>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.jdt.core.javanature</nature>
+ <nature>org.eclipse.pde.PluginNature</nature>
+ </natures>
+</projectDescription>
diff --git a/zpu/sw/simulator/.settings/org.eclipse.jdt.core.prefs b/zpu/sw/simulator/.settings/org.eclipse.jdt.core.prefs
new file mode 100644
index 0000000..6a131a7
--- /dev/null
+++ b/zpu/sw/simulator/.settings/org.eclipse.jdt.core.prefs
@@ -0,0 +1,66 @@
+#Sat Aug 04 19:47:23 CEST 2007
+eclipse.preferences.version=1
+org.eclipse.jdt.core.compiler.codegen.inlineJsrBytecode=enabled
+org.eclipse.jdt.core.compiler.codegen.targetPlatform=1.5
+org.eclipse.jdt.core.compiler.codegen.unusedLocal=preserve
+org.eclipse.jdt.core.compiler.compliance=1.5
+org.eclipse.jdt.core.compiler.debug.lineNumber=generate
+org.eclipse.jdt.core.compiler.debug.localVariable=generate
+org.eclipse.jdt.core.compiler.debug.sourceFile=generate
+org.eclipse.jdt.core.compiler.problem.annotationSuperInterface=warning
+org.eclipse.jdt.core.compiler.problem.assertIdentifier=error
+org.eclipse.jdt.core.compiler.problem.autoboxing=ignore
+org.eclipse.jdt.core.compiler.problem.deprecation=warning
+org.eclipse.jdt.core.compiler.problem.deprecationInDeprecatedCode=disabled
+org.eclipse.jdt.core.compiler.problem.deprecationWhenOverridingDeprecatedMethod=disabled
+org.eclipse.jdt.core.compiler.problem.discouragedReference=warning
+org.eclipse.jdt.core.compiler.problem.emptyStatement=ignore
+org.eclipse.jdt.core.compiler.problem.enumIdentifier=error
+org.eclipse.jdt.core.compiler.problem.fallthroughCase=ignore
+org.eclipse.jdt.core.compiler.problem.fatalOptionalError=enabled
+org.eclipse.jdt.core.compiler.problem.fieldHiding=ignore
+org.eclipse.jdt.core.compiler.problem.finalParameterBound=ignore
+org.eclipse.jdt.core.compiler.problem.finallyBlockNotCompletingNormally=warning
+org.eclipse.jdt.core.compiler.problem.forbiddenReference=error
+org.eclipse.jdt.core.compiler.problem.hiddenCatchBlock=warning
+org.eclipse.jdt.core.compiler.problem.incompatibleNonInheritedInterfaceMethod=warning
+org.eclipse.jdt.core.compiler.problem.incompleteEnumSwitch=ignore
+org.eclipse.jdt.core.compiler.problem.indirectStaticAccess=ignore
+org.eclipse.jdt.core.compiler.problem.localVariableHiding=ignore
+org.eclipse.jdt.core.compiler.problem.methodWithConstructorName=warning
+org.eclipse.jdt.core.compiler.problem.missingDeprecatedAnnotation=ignore
+org.eclipse.jdt.core.compiler.problem.missingOverrideAnnotation=ignore
+org.eclipse.jdt.core.compiler.problem.missingSerialVersion=ignore
+org.eclipse.jdt.core.compiler.problem.noEffectAssignment=warning
+org.eclipse.jdt.core.compiler.problem.noImplicitStringConversion=warning
+org.eclipse.jdt.core.compiler.problem.nonExternalizedStringLiteral=ignore
+org.eclipse.jdt.core.compiler.problem.nullReference=ignore
+org.eclipse.jdt.core.compiler.problem.overridingPackageDefaultMethod=warning
+org.eclipse.jdt.core.compiler.problem.parameterAssignment=ignore
+org.eclipse.jdt.core.compiler.problem.possibleAccidentalBooleanAssignment=ignore
+org.eclipse.jdt.core.compiler.problem.potentialNullReference=ignore
+org.eclipse.jdt.core.compiler.problem.rawTypeReference=ignore
+org.eclipse.jdt.core.compiler.problem.redundantNullCheck=ignore
+org.eclipse.jdt.core.compiler.problem.specialParameterHidingField=disabled
+org.eclipse.jdt.core.compiler.problem.staticAccessReceiver=warning
+org.eclipse.jdt.core.compiler.problem.suppressWarnings=enabled
+org.eclipse.jdt.core.compiler.problem.syntheticAccessEmulation=ignore
+org.eclipse.jdt.core.compiler.problem.typeParameterHiding=warning
+org.eclipse.jdt.core.compiler.problem.uncheckedTypeOperation=ignore
+org.eclipse.jdt.core.compiler.problem.undocumentedEmptyBlock=ignore
+org.eclipse.jdt.core.compiler.problem.unhandledWarningToken=warning
+org.eclipse.jdt.core.compiler.problem.unnecessaryElse=ignore
+org.eclipse.jdt.core.compiler.problem.unnecessaryTypeCheck=ignore
+org.eclipse.jdt.core.compiler.problem.unqualifiedFieldAccess=ignore
+org.eclipse.jdt.core.compiler.problem.unusedDeclaredThrownException=ignore
+org.eclipse.jdt.core.compiler.problem.unusedDeclaredThrownExceptionWhenOverriding=disabled
+org.eclipse.jdt.core.compiler.problem.unusedImport=warning
+org.eclipse.jdt.core.compiler.problem.unusedLabel=warning
+org.eclipse.jdt.core.compiler.problem.unusedLocal=warning
+org.eclipse.jdt.core.compiler.problem.unusedParameter=ignore
+org.eclipse.jdt.core.compiler.problem.unusedParameterIncludeDocCommentReference=enabled
+org.eclipse.jdt.core.compiler.problem.unusedParameterWhenImplementingAbstract=disabled
+org.eclipse.jdt.core.compiler.problem.unusedParameterWhenOverridingConcrete=disabled
+org.eclipse.jdt.core.compiler.problem.unusedPrivateMember=warning
+org.eclipse.jdt.core.compiler.problem.varargsArgumentNeedCast=warning
+org.eclipse.jdt.core.compiler.source=1.5
diff --git a/zpu/sw/simulator/ChangeLog b/zpu/sw/simulator/ChangeLog
new file mode 100644
index 0000000..2f54967
--- /dev/null
+++ b/zpu/sw/simulator/ChangeLog
@@ -0,0 +1,6 @@
+2008-02-22 Øyvind Harboe
+ * reduced memory for Phi to 2mByte to avoid Java heap out of memory.
+ Why does Java have trouble allocating a meagre 32mByte long array? :-)
+ * Hooked up support for the simulator to the Zylin Embedded CDT
+2007-08-04 Øyvind Harboe
+ * First version after open sourcing ZPU
diff --git a/zpu/sw/simulator/META-INF/MANIFEST.MF b/zpu/sw/simulator/META-INF/MANIFEST.MF
new file mode 100644
index 0000000..b0ad5b9
--- /dev/null
+++ b/zpu/sw/simulator/META-INF/MANIFEST.MF
@@ -0,0 +1,11 @@
+Manifest-Version: 1.0
+Bundle-ManifestVersion: 2
+Bundle-Name: ZPU simulator
+Bundle-SymbolicName: com.zylin.zpu.simulator
+Bundle-Version: 1.0.0
+Export-Package: com.zylin.zpu.simulator,
+ com.zylin.zpu.simulator.applet,
+ com.zylin.zpu.simulator.exceptions,
+ com.zylin.zpu.simulator.gdb,
+ com.zylin.zpu.simulator.tools,
+ com.zylin.zpu.stats
diff --git a/zpu/sw/simulator/build.properties b/zpu/sw/simulator/build.properties
new file mode 100644
index 0000000..19c7019
--- /dev/null
+++ b/zpu/sw/simulator/build.properties
@@ -0,0 +1,3 @@
+source.. = .
+bin.includes = META-INF/,\
+ .
diff --git a/zpu/sw/simulator/build.xml b/zpu/sw/simulator/build.xml
new file mode 100644
index 0000000..a5cc8a3
--- /dev/null
+++ b/zpu/sw/simulator/build.xml
@@ -0,0 +1,7 @@
+<?xml version="1.0"?>
+<project name="project" default="build">
+
+ <target name="build" >
+ <jar destfile="zpusim.jar" basedir="bin"/>
+ </target>
+</project>
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/Abel.java b/zpu/sw/simulator/com/zylin/zpu/simulator/Abel.java
new file mode 100644
index 0000000..8d8667c
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/Abel.java
@@ -0,0 +1,109 @@
+
+package com.zylin.zpu.simulator;
+
+import com.zylin.zpu.simulator.exceptions.CPUException;
+import com.zylin.zpu.simulator.exceptions.MemoryAccessException;
+
+public class Abel extends Simulator
+{
+
+ protected int getIO()
+ {
+ return 0x8000;
+ }
+
+
+
+ protected int ioRead(int addr) throws CPUException
+ {
+ switch (addr)
+ {
+ case 0xc000:
+ return syscall.readUART();
+
+ /* FIFO empty? bit 0, FIFO full bit 1(never the case) */
+ case 0xc004:
+ return syscall.readFIFO();
+
+ case 0x9000:
+ case 0x9004:
+ case 0x9008:
+ case 0x900c:
+
+ case 0x9010:
+ case 0x9014:
+ case 0x9018:
+ case 0x901c:
+ return readSampledTimer(addr, 0x9000);
+
+ case 0x8800:
+ return readMHz();
+
+ default:
+ throw new MemoryAccessException();
+ }
+ }
+
+ /*
+ ; Read/write are on different addresses
+ ; The registers are 8 bits and mapped to bit[7:0]
+ ;
+ ; 0xC000 Write: Writes to UART TX FIFO (4 byte FIFO)
+ ; Read : Reads from UART RX FIFO (4 byte FIFO)
+ ; 0xC004 Read : UART status register
+ ; Bit 0 = RX FIFO empty
+ ; Bit 1 = TX FIFO full
+ ; 0xA000 Write: 8 LED's
+ */
+
+ /*
+ 0x9000 Write: bit 0: 1= reset counter
+ 0= counter running
+ bit 1: 1= sample counter (when set to 1)
+ 0=not used
+ Read : counter bit[7:0]
+ 0x9004 Read: counter bit [15:8]
+ 0x9008 Read: counter bit [23:16]
+ 0x900C Read: counter bit [31:24]
+ 0x9010 Read: counter bit [39:32]
+ 0x9014 Read: counter bit [47:40]
+ 0x9018 Read: counter bit [55:48]
+ 0x901C Read: counter bit [63:56]
+
+ 0x8800 Read: unsigned 8-bit integer with FPGA frequency (in MHz)
+ */
+
+ protected void ioWrite(int addr, int val) throws MemoryAccessException
+ {
+ switch (addr)
+ {
+ case 0x9000:
+ writeTimerSampleReg(val);
+ case 0xc000:
+ syscall.writeUART(val);
+ break;
+ default:
+ throw new MemoryAccessException();
+ }
+ }
+
+ Abel() throws CPUException
+ {
+ }
+
+ protected boolean emulateConfig()
+ {
+ return true;
+ }
+
+ protected int getStartStack()
+ {
+ return getRAMSIZE()-8;
+ }
+
+ protected int getRAMSIZE()
+ {
+ return 32768;
+ }
+
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/FileTracer.java b/zpu/sw/simulator/com/zylin/zpu/simulator/FileTracer.java
new file mode 100644
index 0000000..6ccca24
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/FileTracer.java
@@ -0,0 +1,285 @@
+
+package com.zylin.zpu.simulator;
+
+import java.io.FileNotFoundException;
+import java.io.IOException;
+import java.io.LineNumberReader;
+
+import com.zylin.zpu.simulator.exceptions.CPUException;
+import com.zylin.zpu.simulator.exceptions.GDBServerException;
+import com.zylin.zpu.simulator.exceptions.TraceException;
+
+public class FileTracer implements Tracer
+{
+ private LineNumberReader file;
+ private boolean trigger;
+ private boolean resync;
+ private Simulator simulator;
+ private String line;
+ private boolean ignore;
+
+ static class Trace
+ {
+ int pc;
+ int opcode;
+ int sp;
+ int stackA;
+ int stackB;
+ int intSp;
+ long cycle;
+ public boolean undefinedStackA;
+ public boolean undefinedStackB;
+ public boolean undefinedIntSp;
+ public void print()
+ {
+ System.err.println(Integer.toHexString(pc)+ " " +
+ Integer.toHexString(opcode) + " " +
+ Integer.toHexString(sp) + " " +
+ Integer.toHexString(stackA) + " " +
+ Integer.toHexString(stackB) + " " +
+ intSp + " " +
+ cycle);
+
+ }
+ };
+ private Trace[] trace= new Trace[100];
+ private int current;
+ private String fileName;
+ private boolean metEnd;
+
+
+ public FileTracer(Simulator sim, String string)
+ {
+ simulator=sim;
+ fileName=string;
+
+ resync=true;
+
+
+ for (int i=0; i<trace.length; i++)
+ {
+ trace[i]=new Trace();
+ }
+ findNextTrigger();
+ }
+
+ LineNumberReader getFile()
+ {
+ if (file==null)
+ {
+ try
+ {
+ file=new LineNumberReader(new java.io.FileReader(fileName));
+ } catch (FileNotFoundException e)
+ {
+ throw new RuntimeException(e);
+ }
+ }
+ return file;
+ }
+
+
+ private void findNextTrigger() throws TraceException
+ {
+ trigger=false;
+ try
+ {
+ for (;;)
+ {
+ line=getFile().readLine();
+ if (line==null)
+ {
+ metEnd=true;
+ System.err.println("================== End of trace file ======================");
+ break;
+ }
+ if (line.matches("^\\s*\\#.*$"))
+ {
+ /* this was a comment*/
+ continue;
+ }
+ if (line.matches("^\\s*$"))
+ {
+ /* all whitespace */
+ continue;
+ }
+ String[] val=line.split(" ");
+
+ try
+ {
+ Trace t=trace[current];
+ t.pc=(int) parseInt(val[0]);
+ t.opcode=(int) parseInt(val[1]);
+ t.sp=(int) parseInt(val[2]);
+ try
+ {
+ t.undefinedStackA=false;
+ t.stackA=(int) parseInt(val[3]);
+ } catch (NumberFormatException e)
+ {
+ t.undefinedStackA=true;
+ t.stackB=0;
+ }
+
+ try
+ {
+ t.undefinedStackB=false;
+ t.stackB=(int) parseInt(val[4]);
+ } catch (NumberFormatException e)
+ {
+ t.undefinedStackB=true;
+ t.stackB=0;
+ }
+ try
+ {
+ t.undefinedIntSp=false;
+ t.intSp=(int) parseInt(val[5]);
+ } catch (NumberFormatException e)
+ {
+ t.undefinedIntSp=true;
+ t.intSp=0;
+ }
+ t.cycle=parseInt(val[6]);
+ trigger=true;
+ break;
+ } catch (NumberFormatException e)
+ {
+ /* skip this line. */
+ e.printStackTrace();
+ }
+ }
+ } catch (IOException e)
+ {
+ throw new TraceException(e);
+ }
+
+ }
+
+ private long parseInt(String string2) throws TraceException
+ {
+ String string = string2;
+ if (!string.startsWith("0x"))
+ {
+ throw new TraceException(new Exception("Trace file pasing error line " + getFile().getLineNumber()));
+ }
+ return Long.parseLong(string.substring(2), 16);
+ }
+
+ public void instructionEvent() throws GDBServerException
+ {
+ if (metEnd)
+ {
+ metEnd=false;
+ throw new TraceException();
+ }
+ if (resync&&trigger)
+ {
+ if (match())
+ {
+ /* we have to wait for the first instruction in the trace to be matched */
+ System.out.println("First matching instruction found!");
+ resync=false;
+ }
+ }
+
+ if (!resync&&trigger)
+ {
+
+ boolean m=match();
+ recordCurrent();
+ current=(current+1)%trace.length;
+
+ if (!m)
+ {
+ System.err.println("Trace file mismatch");
+ dumpTraceBack();
+ System.err.print("Expected by Java simulator: \n");
+ simulator.printState(this);
+ System.err.print("Actual from ModelSim: ");
+ System.err.println(line);
+ // we now have to ignore this match.
+ ignore=true;
+ throw new TraceException();
+ }
+ } else
+ {
+ recordCurrent();
+ current=(current+1)%trace.length;
+ }
+ }
+
+ public void dumpTraceBack()
+ {
+ System.err.println("Expected");
+ System.err.println("PC SP topOfStack");
+ for (int i=0; i<trace.length; i++)
+ {
+ trace[(i+current)%trace.length].print();
+ }
+ }
+
+ private void recordCurrent()
+ {
+ recordState(trace[current]);
+ }
+
+ private void recordState(Trace trace3)
+ {
+ trace3.pc=simulator.getPc();
+ trace3.sp=simulator.getSp();
+ trace3.opcode=simulator.getOpcode();
+ try
+ {
+ trace3.stackA=simulator.cpuReadLong(simulator.getSp());
+ trace3.stackB=simulator.cpuReadLong(simulator.getSp()+4);
+ trace3.intSp=simulator.getIntSp();
+ // trace[current].cycle=expectetdCycle();
+ } catch (CPUException e1)
+ {
+ e1.printStackTrace();
+ }
+ }
+
+
+
+ boolean match() throws GDBServerException
+ {
+ if (ignore)
+ return true;
+
+ return simulator.checkMatch(trace[current]);
+ }
+
+ public void commit()
+ {
+ try
+ {
+ if (!resync&&trigger)
+ {
+ ignore=false;
+ findNextTrigger();
+ }
+ }
+ catch (Throwable e)
+ {
+ e.printStackTrace();
+ }
+ }
+
+ public void setSp(int sp)
+ {
+ }
+
+ public boolean onInterrupt()
+ {
+ if (trace[current].pc==0x20)
+ return true;
+ else
+ return false;
+ }
+
+ public boolean simInterrupt()
+ {
+ return true;
+ }
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/Host.java b/zpu/sw/simulator/com/zylin/zpu/simulator/Host.java
new file mode 100644
index 0000000..c1daa9f
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/Host.java
@@ -0,0 +1,46 @@
+
+package com.zylin.zpu.simulator;
+
+import com.zylin.zpu.simulator.exceptions.CPUException;
+
+public interface Host
+{
+ /** generic file io error */
+ public final static int EIO = 5;
+
+ public final static int SYS_read= 4;
+ public final static int SYS_write= 5;
+ public final static int SYS_argv = 13;
+ public final static int SYS_exit=1;
+ public final static int SYS_open= 2;
+ public final static int SYS_close= 3;
+ public final static int SYS_lseek = 6;
+ public final static int SYS_unlink = 7;
+ public final static int SYS_getpid = 8;
+ public final static int SYS_kill = 9;
+ public final static int SYS_fstat = 10;
+ /*final static int SYS_sbrk 11 - not currently a system call, but reserved. */
+ /* ARGV support. */
+ public final static int SYS_argvlen= 12;
+ /* These are extras added for one reason or another. */
+ public final static int SYS_chdir = 14;
+ public final static int SYS_stat = 15;
+ public final static int SYS_chmod = 16;
+ public final static int SYS_utime = 17;
+ public final static int SYS_time = 18;
+ public final static int SYS_gettimeofday =19;
+ public final static int SYS_times = 20;
+ public final static int SYS_link = 21;
+ public final static int SYS_ftruncate=3000;
+ public final static int SYS_isatty=3001;
+ public void syscall(Sim s) throws CPUException;
+ boolean doneContinue();
+ public void writeUART(int val);
+ public int readUART() throws CPUException;
+ public int readFIFO();
+ /** notification that the CPU is halted */
+ public void halted();
+ /** notification that the CPU is running */
+ public void running();
+
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/Machine.java b/zpu/sw/simulator/com/zylin/zpu/simulator/Machine.java
new file mode 100644
index 0000000..3827378
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/Machine.java
@@ -0,0 +1,17 @@
+
+package com.zylin.zpu.simulator;
+
+/**
+ * @author oyvind
+ *
+ * TODO To change the template for this generated type comment go to
+ * Window - Preferences - Java - Code Style - Code Templates
+ */
+public interface Machine
+{
+
+ long getPrevCycles();
+
+ long getCycles();
+
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java b/zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java
new file mode 100644
index 0000000..663e68f
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java
@@ -0,0 +1,126 @@
+
+package com.zylin.zpu.simulator;
+
+import com.zylin.zpu.simulator.exceptions.CPUException;
+import com.zylin.zpu.simulator.exceptions.MemoryAccessException;
+
+public class Phi extends Simulator
+{
+ @Override
+ protected long getSampleOffset()
+ {
+
+ return super.getSampleOffset()-(0x5e7b2-0x0005E7C0);
+ }
+
+
+ public static void main(String[] args)
+ {
+ new SimApp(new SimFactory()
+ {
+ public Simulator create()
+ {
+ return new Phi();
+ }
+ }).run(args);
+ }
+
+
+ protected int getIO()
+ {
+ return 0x08000000;
+ }
+
+
+
+ protected int ioRead(int addr) throws CPUException
+ {
+ switch (addr)
+ {
+
+ case 0x080a0020:
+ return interrupt?0:1; // interrupt mask
+
+
+
+ /* FIFO empty? bit 0, FIFO full bit 1(never the case) */
+ case 0x080a000c:
+ return 0x100; // buffer ready.
+
+ case 0x080a0014:
+ case 0x080a0018:
+ return readSampledTimer(addr, 0x080a0014);
+
+ case 0x080a0030:
+ return timerPending?1:0;
+ case 0x080a0038:
+ return (int)(timerInterval-1-((cycles-lastTimer)%timerInterval));
+
+
+ default:
+ throw new MemoryAccessException();
+ }
+ }
+
+
+
+ protected void ioWrite(int addr, int val) throws MemoryAccessException
+ {
+ switch (addr)
+ {
+ case 0x080a0020:
+ interrupt=(val&1)==0;
+ return;
+ case 0x080a002c:
+ timer=(val&0x1)!=0;
+ break;
+ case 0x080a0030:
+ if ((val&0x1)!=0)
+ {
+ timerPending=false;
+ }
+ if ((val&0x2)!=0)
+ {
+ lastTimer=cycles;
+ }
+ break;
+ case 0x080a0034:
+ timerInterval=val;
+ return;
+
+ case 0x080a0014:
+ writeTimerSampleReg(val);
+ case 0x080a000c:
+ syscall.writeUART(val);
+ break;
+ default:
+ throw new MemoryAccessException();
+ }
+ }
+
+ public Phi() throws CPUException
+ {
+ }
+
+ protected boolean emulateConfig()
+ {
+ return true;
+ }
+
+ protected int getStartStack()
+ {
+ return getRAMSIZE()-8;
+ }
+
+ protected int getRAMSIZE()
+ {
+ return 2*1024*1024;
+ }
+
+
+ protected int getIOSIZE()
+ {
+ return 0x100000;
+ }
+
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/PhiFeeble.java b/zpu/sw/simulator/com/zylin/zpu/simulator/PhiFeeble.java
new file mode 100644
index 0000000..79d3a38
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/PhiFeeble.java
@@ -0,0 +1,34 @@
+package com.zylin.zpu.simulator;
+
+public class PhiFeeble extends Phi
+{
+ public static void main(String[] args)
+ {
+ new SimApp(new SimFactory()
+ {
+ public Simulator create()
+ {
+ return new PhiFeeble();
+ }
+ }).run(args);
+ }
+ protected void setFeeble()
+ {
+// feeble[NEQBRANCH] = false;
+// feeble[EQ] = false;
+// feeble[LOADB] = false;
+// feeble[LESSTHAN] = false;
+// feeble[ULESSTHAN] = false;
+// feeble[STOREB] = false;
+// feeble[MULT] = false;
+// feeble[CALL] = true;
+// feeble[POPPCREL] = true;
+// feeble[LESSTHANOREQUAL] = true;
+// feeble[ULESSTHANOREQUAL] = true;
+//
+// feeble[PUSHSPADD] = false;
+// feeble[CALLPCREL] = false;
+// feeble[SUB] = false;
+ }
+
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/Sim.java b/zpu/sw/simulator/com/zylin/zpu/simulator/Sim.java
new file mode 100644
index 0000000..21450f7
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/Sim.java
@@ -0,0 +1,62 @@
+
+package com.zylin.zpu.simulator;
+
+import com.zylin.zpu.simulator.exceptions.CPUException;
+import com.zylin.zpu.simulator.exceptions.MemoryAccessException;
+
+public interface Sim
+{
+/**
+ * halts the CPU.
+ */
+ void suspend();
+ void writeByte(int i, int val) throws CPUException;
+ /**
+ * synchronous method that returns when simulator enters the halt state.
+ **/
+ void cont();
+ /**
+ * synchronous method that returns when simulator finishes step or otherwise enters
+ * the halt state.
+ **/
+ void step();
+
+ int getReg(int i) throws CPUException;
+
+ int getREGNUM();
+ int readByte(int addr) throws CPUException;
+
+ /**
+ * @param sp The sp to set.
+ * @throws CPUException
+ */
+ void setSp(int sp) throws CPUException;
+
+ /**
+ * @return Returns the sp.
+ */
+ int getSp();
+
+ /**
+ * @param pc The pc to set.
+ * @throws MemoryAccessException
+ */
+ void setPc(int pc) throws MemoryAccessException;
+
+ /**
+ * @return Returns the pc.
+ */
+ int getPc();
+
+ void enableAccessWatchPoint(int address, int length) throws CPUException;
+
+ void disableAccessWatchPoint(int address, int length) throws CPUException;
+
+ int cpuReadLong(int i) throws CPUException;
+
+ void cpuWriteLong(int i, int retval) throws MemoryAccessException;
+
+ int getArg(int num) throws CPUException;
+ void sessionStarted();
+
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/SimApp.java b/zpu/sw/simulator/com/zylin/zpu/simulator/SimApp.java
new file mode 100644
index 0000000..3f6e1a9
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/SimApp.java
@@ -0,0 +1,177 @@
+package com.zylin.zpu.simulator;
+
+import java.io.IOException;
+import java.net.InetSocketAddress;
+import java.net.ServerSocket;
+import java.net.Socket;
+import java.nio.channels.ServerSocketChannel;
+
+import com.zylin.zpu.simulator.exceptions.CPUException;
+import com.zylin.zpu.simulator.gdb.GDBServer;
+
+public class SimApp
+{
+ private static Simulator simulator;
+ private String[] args;
+ private int portNumber;
+ private SimFactory simFactory;
+
+ public SimApp(SimFactory factory)
+ {
+ simFactory=factory;
+ }
+
+ public void parseArgs()
+ {
+ portNumber = 4444;
+ if (args.length>=1)
+ {
+ portNumber=Integer.parseInt(args[0]);
+ }
+ }
+
+ private void moreParse()
+ {
+ if (args.length>=2)
+ {
+ simulator.setTraceFile(args[1]);
+ }
+ }
+
+ void run(String[] args)
+ {
+ this.args=args;
+ createSimulator();
+ parseArgs();
+ moreParse();
+ runSimAndGDB();
+ }
+ Object launched=new Object();
+ private boolean doneLaunching;
+ private boolean manyGDBSessions;
+ public ServerSocket serverSocket;
+ public void runSimAndGDB()
+ {
+ try
+ {
+ serverSocket = new ServerSocket(portNumber);
+ try
+ {
+ serverSocket.setReuseAddress(true);
+ System.out.println("Listening on port " + portNumber);
+ setLaunchedFlag();
+ do
+ {
+ try
+ {
+ runGDBServer();
+ } catch (CPUException e)
+ {
+ e.printStackTrace();
+ }
+ } while (manyGDBSessions);
+ } finally
+ {
+ serverSocket.close();
+ }
+ } catch (IOException e1)
+ {
+ e1.printStackTrace();
+ } finally
+ {
+ setLaunchedFlag();
+ }
+
+ }
+
+ private void setLaunchedFlag()
+ {
+ synchronized(launched)
+ {
+ doneLaunching=true;
+ launched.notify();
+ }
+ }
+
+ public void createSimulator()
+ {
+ simulator=simFactory.create();
+ simulator.suspend();
+ }
+
+ private void runGDBServer() throws CPUException
+ {
+ final GDBServer gdbServer=new GDBServer(simulator, this);
+ simulator.setSyscall(gdbServer);
+ Thread thread = new Thread(new Runnable()
+ {
+ public void run()
+ {
+ try
+ {
+ gdbServer.gdbServer();
+ }
+ catch (Throwable e)
+ {
+ e.printStackTrace();
+ }
+ simulator.shutdown();
+ }
+ });
+ thread.start();
+ try
+ {
+ simulator.run();
+ }
+ finally
+ {
+ try
+ {
+ thread.join();
+ } catch (InterruptedException e)
+ {
+ e.printStackTrace();
+ }
+ }
+
+ }
+
+ public Simulator getSimulator()
+ {
+ return simulator;
+ }
+
+ public void setPort(int i)
+ {
+ portNumber=i;
+ }
+
+ /** synchronous launch of GDB server */
+ public void launchGDBServer()
+ {
+ Thread t=new Thread(new Runnable()
+ {
+
+ public void run()
+ {
+ runSimAndGDB();
+ }
+ });
+ t.start();
+ synchronized (launched)
+ {
+ while (!doneLaunching)
+ {
+ try
+ {
+ launched.wait(2000);
+ } catch (InterruptedException e)
+ {
+ e.printStackTrace();
+ }
+ }
+ }
+
+
+ }
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/SimFactory.java b/zpu/sw/simulator/com/zylin/zpu/simulator/SimFactory.java
new file mode 100644
index 0000000..4db85d7
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/SimFactory.java
@@ -0,0 +1,8 @@
+package com.zylin.zpu.simulator;
+
+public interface SimFactory
+{
+
+ Simulator create();
+
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/Simulator.java b/zpu/sw/simulator/com/zylin/zpu/simulator/Simulator.java
new file mode 100644
index 0000000..cf6cf41
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/Simulator.java
@@ -0,0 +1,2065 @@
+package com.zylin.zpu.simulator;
+
+import java.io.ByteArrayOutputStream;
+import java.io.FileOutputStream;
+import java.io.IOException;
+import java.io.InputStream;
+import java.io.OutputStream;
+import java.util.Collections;
+import java.util.Comparator;
+import java.util.LinkedList;
+import java.util.List;
+
+import com.zylin.zpu.simulator.FileTracer.Trace;
+import com.zylin.zpu.simulator.exceptions.CPUException;
+import com.zylin.zpu.simulator.exceptions.DebuggerBreakpointException;
+import com.zylin.zpu.simulator.exceptions.EndSessionException;
+import com.zylin.zpu.simulator.exceptions.GDBServerException;
+import com.zylin.zpu.simulator.exceptions.HardwareWatchPointException;
+import com.zylin.zpu.simulator.exceptions.IllegalInstructionException;
+import com.zylin.zpu.simulator.exceptions.InterruptException;
+import com.zylin.zpu.simulator.exceptions.MemoryAccessException;
+
+public class Simulator implements ZPU, Machine, Sim
+{
+
+ int minStack;
+
+ /**
+ * the feeble version of the CPU, e.g. only implements
+ * 11 instructions.
+ *
+ * For debugging purposes it is useful to enable/disable
+ * each instruction
+ */
+ boolean feeble[]=new boolean[256];
+
+ private long opcodeHistogram[]=new long[256];
+ private long opcodeHistogramCycles[]=new long[256];
+ private long opcodePairHistogram[]=new long[256*256];
+ private long opcodePairHistogramCycles[]=new long[256*256];
+
+ /** weee! constants are 32 bit by default, so we need to assign a 64 bit
+ * integer in this matter.
+ */
+ private static final long INTMASK = Long.parseLong("ffffffff", 16);
+
+ final static int PUSHPC=59;
+ final static int OR=7;
+ final static int NOT=9;
+ final static int LOAD=8;
+ final static int STORE=12;
+ final static int POPPC=4;
+ final static int FLIP=10;
+
+ final static int ADD=5;
+ final static int PUSHSP=2;
+ final static int POPSP=13;
+ final static int NOP=11;
+ final static int AND=6;
+ final static int ADDSP=16;
+
+ final static int EMULATE=32;
+ final static int LOADH=34;
+ final static int STOREH=35;
+ final static int LESSTHAN=36;
+ final static int LESSTHANOREQUAL=37;
+ final static int ULESSTHAN=38;
+ final static int ULESSTHANOREQUAL=39;
+ final static int SWAP=40;
+ final static int MULT=41;
+ final static int LSHIFTRIGHT=42;
+ final static int ASHIFTLEFT=43;
+ final static int ASHIFTRIGHT=44;
+ final static int CALL=45;
+ final static int EQ=46;
+ final static int NEQ=47;
+ final static int NEG=48;
+ final static int SUB=49;
+ final static int XOR=50;
+ final static int LOADB=51;
+ final static int STOREB=52;
+ final static int DIV=53;
+ final static int MOD=54;
+ final static int EQBRANCH=55;
+ final static int NEQBRANCH=56;
+ final static int POPPCREL=57;
+ final static int CONFIG=58;
+ final static int SYSCALL=60;
+ final static int PUSHSPADD=61;
+ final static int MULT16X16=62;
+ final static int CALLPCREL=63;
+ final static int STORESP=64;
+ final static int LOADSP=64+32;
+
+ int[] memory;
+ boolean[] validMemory;
+ protected long cycles;
+ protected int instructionCount;
+ private int sp;
+ private int pc;
+ protected boolean breakNext;
+
+ /* halting synchronization object */
+ protected Object halt = new Object();
+
+ private int IOSIZE=getIOSIZE();
+ protected int getIOSIZE()
+ {
+ return 32768;
+ }
+ long prevCycles;
+ private static final int VECTORSIZE = 0x20;
+ private static final int VECTOR_RESET = 0;
+ private static final int VECTOR_INTERRUPT = 1;
+ private boolean hitVector;
+ private static final int VECTORBASE = 0x0;
+ private int nextVector;
+ protected long lastTimer;
+ protected boolean timer;
+ private boolean powerdown;
+ private boolean decodeMask;
+
+ private static final int ZETA = 1;
+
+ private static final int ABEL = 0;
+
+ private int startStack;
+
+ protected Host syscall;
+
+ private long[] emulateOpcodeHistogram= new long[256];
+
+ private long[] emulateOpcodeHistogramCycles=new long[256];
+
+ private long emulateCycles;;
+
+ public Simulator() throws CPUException
+ {
+ }
+
+
+ public void run() throws CPUException
+ {
+ syscall.running();
+
+ try
+ {
+
+ instructionLoop();
+
+
+ } catch (EndSessionException e)
+ {
+ /* done */
+ } finally
+ {
+ }
+ dumpInfo();
+
+ System.err.println("Stack usage: " + (startStack-minStack));
+ }
+
+ private void dumpInfo()
+ {
+ dumpOpcodeHistogram();
+
+ //printMemoryHistorgram();
+ }
+
+
+ private void dumpOpcodeHistogram()
+ {
+ System.out.println("Opcode histogram");
+ dumpHistogram(opcodeHistogram, opcodeHistogramCycles);
+ System.out.println("Emulate histogram");
+ dumpHistogram(emulateOpcodeHistogram, emulateOpcodeHistogramCycles);
+ System.out.println("Pair histogram");
+ dumpHistogram(opcodePairHistogram, opcodePairHistogramCycles);
+
+
+ dumpGmon();
+
+ System.out.println("Grouping of LOADSP/STORESP/IM");
+ printRange(64, 96);
+ printRange(96, 128);
+ printRange(128, 256);
+// printRange(64, 65);
+// printRange(65, 66);
+// printRange(66, 64+32);
+// printRange(96, 97);
+// printRange(97, 98);
+// printRange(98, 96+32);
+// printRange(128, 129);
+// printRange(129, 130);
+// printRange(130, 131);
+// printRange(131, 132);
+// printRange(132, 133);
+// printRange(252, 253);
+// printRange(253, 254);
+// printRange(254, 255);
+// printRange(255, 256);
+ }
+
+
+
+// #define GMON_MAGIC "gmon" /* magic cookie */
+// #define GMON_VERSION 1 /* version number */
+//
+// /*
+// * Raw header as it appears on file (without padding):
+// */
+// struct gmon_hdr
+// {
+// char cookie[4];
+// char version[4]; // a cyg_uint32, target-side endianness
+// char spare[3 * 4];
+// };
+//
+// /* types of records in this file: */
+// typedef enum
+// {
+// GMON_TAG_TIME_HIST = 0, GMON_TAG_CG_ARC = 1, GMON_TAG_BB_COUNT = 2
+// }
+// GMON_Record_Tag;
+//
+// /* The histogram tag is followed by this header, and then an array of */
+// /* cyg_uint16's for the actual counts. */
+//
+// struct gmon_hist_hdr
+// {
+// /* host-side gprof adapts to sizeof(void*) and endianness. */
+// /* It is assumed that the compiler does not insert padding around the */
+// /* cyg_uint32's or the char arrays. */
+// void* low_pc; /* base pc address of sample buffer */
+// void* high_pc; /* max pc address of sampled buffer */
+// cyg_uint32 hist_size; /* size of sample buffer */
+// cyg_uint32 prof_rate; /* profiling clock rate */
+// char dimen[15]; /* phys. dim., usually "seconds" */
+// char dimen_abbrev; /* usually 's' for "seconds" */
+// };
+//
+// /* An arc tag is followed by a single arc record. self_pc corresponds to */
+// /* the location of an mcount() call, at the start of a function. from_pc */
+// /* corresponds to the return address, i.e. where the function was called */
+// /* from. count is the number of calls. */
+//
+// struct gmon_cg_arc_record
+// {
+// void* from_pc; /* address within caller's body */
+// void* self_pc; /* address within callee's body */
+// cyg_uint32 count; /* number of arc traversals */
+// };
+//
+// /* In theory gprof can also process basic block counts, as per the */
+// /* compiler's -fprofile-arcs flag. The compiler-generated basic block */
+// /* structure should contain a table of addresses and a table of counts, */
+// /* and the compiled code updates those counts. Current versions of the */
+// /* compiler (~3.2.1) do not output the table of addresses, and without */
+// /* that table gprof cannot process the counts. Possibly gprof should read */
+// /* in the .bb and .bbg files generated for gcov processing, but that does */
+// /* not happen at the moment. */
+// /* */
+// /* So for now gmon.out does not contain basic block counts and gprof */
+// /* operations that depend on it, e.g. --annotated-source, won't work. */
+
+ /**
+ * Write gmon.out file.
+ **/
+ private void dumpGmon()
+ {
+ if (memory==null)
+ return;
+ try
+ {
+ ByteArrayOutputStream b=new ByteArrayOutputStream();
+
+
+// /*
+// * Raw header as it appears on file (without padding):
+// */
+// struct gmon_hdr
+// {
+// char cookie[4];
+// char version[4]; // a cyg_uint32, target-side endianness
+// char spare[3 * 4];
+// };
+// #define GMON_MAGIC "gmon" /* magic cookie */
+// #define GMON_VERSION 1 /* version number */
+
+// dump binary memory gmon.out &profile_gmon_hdr ((char*)&profile_gmon_hdr + sizeof(struct gmon_hdr))
+ b.write("gmon".getBytes());
+ writeLong(b, 1); // version
+ b.write(new byte[3*4]); // spare
+
+// GMON_TAG_TIME_HIST = 0, GMON_TAG_CG_ARC = 1, GMON_TAG_BB_COUNT = 2
+
+// append binary memory gmon.out &profile_tags[0] &profile_tags[1]
+ b.write(new byte[]{0}); // GMON_TAG_TIME_HIST
+
+
+//
+// // The gprof documentation claims that this should be the size in
+// // bytes. The implementation treats it as a count.
+// profile_hist_hdr.hist_size = (cyg_uint32) ((text_size + bucket_size - 1) / bucket_size);
+// profile_hist_hdr.low_pc = _start;
+// profile_hist_hdr.high_pc = (void*)((cyg_uint8*)_end - 1);
+// // The prof_rate is the frequency in hz. The resolution argument is
+// // an interval in microseconds.
+// profile_hist_hdr.prof_rate = 1000000 / resolution;
+//
+// // Now allocate a buffer for the histogram data.
+// profile_hist_data = (cyg_uint16*) malloc(profile_hist_hdr.hist_size * sizeof(cyg_uint16));
+// if ((cyg_uint16*)0 == profile_hist_data) {
+// diag_printf("profile_on(): cannot allocate histogram buffer - ignored\n");
+// return;
+// }
+// memset(profile_hist_data, 0, profile_hist_hdr.hist_size * sizeof(cyg_uint16));
+
+
+
+// struct gmon_hist_hdr
+// {
+// /* host-side gprof adapts to sizeof(void*) and endianness. */
+// /* It is assumed that the compiler does not insert padding around the */
+// /* cyg_uint32's or the char arrays. */
+// void* low_pc; /* base pc address of sample buffer */
+// void* high_pc; /* max pc address of sampled buffer */
+// cyg_uint32 hist_size; /* size of sample buffer */
+// cyg_uint32 prof_rate; /* profiling clock rate */
+// char dimen[15]; /* phys. dim., usually "seconds" */
+// char dimen_abbrev; /* usually 's' for "seconds" */
+// };
+
+
+ // maximum 65536 buckets.
+ int length=memory.length*4;
+ if (length > 60000)
+ {
+ length=60000;
+ }
+ int buckets[]=new int[length];
+ for (long i=0; i<profile.length;i++)
+ {
+ buckets[(int)((i*(((long)buckets.length)-1))/(((long)profile.length)-1))]+=profile[(int)i];
+ }
+
+
+
+ // append binary memory gmon.out &profile_hist_hdr ((char*)&profile_hist_hdr + sizeof(struct gmon_hist_hdr))
+ writeLong(b, 0); // low_pc
+ writeLong(b, memory.length*4); // high_pc
+ writeLong(b, buckets.length); // # of samples
+ writeLong(b, 64000000); // 64MHz
+ b.write("seconds".getBytes());
+ b.write(new byte[15-"seconds".length()]);
+ b.write("s".getBytes());
+
+
+
+// append binary memory gmon.out profile_hist_data (profile_hist_data + profile_hist_hdr.hist_size)
+ for (int i=0; i<buckets.length;i++)
+ {
+ int val;
+ val=buckets[i];
+ if (val>65535)
+ {
+ val=65535;
+ }
+ writeShort(b, val);
+ }
+
+ OutputStream o=new FileOutputStream("gmon.out");
+ b.writeTo(o);
+ o.flush();
+ o.close();
+
+ } catch (IOException e)
+ {
+ // TODO Auto-generated catch block
+ e.printStackTrace();
+ }
+
+
+
+ }
+
+
+ private void writeLong(ByteArrayOutputStream b, int i) throws IOException
+ {
+ int val=i;
+ b.write(new byte[]{(byte)((val>>24)&0xff),
+ (byte)((val>>16)&0xff),
+ (byte)((val>>8)&0xff),
+ (byte)((val>>0)&0xff)});
+ }
+
+
+ private void writeShort(ByteArrayOutputStream b, int i) throws IOException
+ {
+ int val=i;
+ b.write(new byte[]{ (byte)((val>>8)&0xff),
+ (byte)((val>>0)&0xff)});
+ }
+
+
+ private void dumpHistogram(long[] ms, long[] ms2)
+ {
+ List<OpcodeSample> l=new LinkedList();
+
+ totalCycles = 0;
+ for (int i=0; i<256; i++)
+ {
+ totalCycles+=opcodeHistogramCycles[i];
+ }
+ for (int i=0; i<ms.length; i++)
+ {
+ final int j=i;
+ l.add(new OpcodeSample(j, ms2[j]));
+ }
+ Collections.sort(l, new Comparator()
+ {
+
+ public int compare(Object arg0, Object arg1)
+ {
+ OpcodeSample a=(OpcodeSample) arg0, b=(OpcodeSample) arg1;
+ if (a.count<b.count)
+ {
+ return 1;
+ } else if (a.count==b.count)
+ {
+ return 0;
+ } else
+ {
+ return -1;
+ }
+ }
+ });
+
+ for (int i=0; i<ms.length; i++)
+ {
+ if (totalCycles==0)
+ break;
+ double d = ((double)l.get(i).count/((double)totalCycles));
+ if (d<0.005)
+ break;
+ double cycPerIns = ((double)ms2[l.get(i).j]/((double)ms[l.get(i).j]));
+ System.out.println("0x"+ Integer.toHexString(l.get(i).j) + " " + d + " " + l.get(i).count + " " + cycPerIns );
+ }
+ }
+
+
+ private void printRange(int from, int to)
+ {
+ int totalLoadSP=0;
+ for (int i=from; i<to; i++)
+ {
+ totalLoadSP+=opcodeHistogram[i];
+ }
+
+ double d = ((double)totalLoadSP/((double)totalCycles));
+
+ System.out.println(""+ from + " " + d + " " + totalLoadSP);
+ }
+
+
+// private void printMemoryHistorgram()
+// {
+// Arrays.sort(profile, new Comparator()
+// {
+// public int compare(Object o1, Object o2)
+// {
+// return (int)(((Profile)o2).counter-
+// ((Profile)o1).counter);
+// }
+// });
+// System.err.println("Profiling information");
+// for (int i=0; i<1000; i++)
+// {
+// if (profile[i].counter==0)
+// {
+// break;
+// }
+// System.err.println("0x"+Integer.toHexString(profile[i].address)+ " " + profile[i].counter);
+// }
+// }
+
+
+ /**
+ * notify everybody that we are powering down
+ */
+ public void shutdown()
+ {
+ powerdown=true;
+ /* wake up */
+ synchronized(halt)
+ {
+ halt.notify();
+ }
+ }
+
+
+ /**
+ * This method can be invoked in two cases:
+ *
+ * a) while the CPU is running on the simulator thread
+ * b) while the CPU is halted from other threads
+ */
+ protected void resetHardwareInternal() throws CPUException
+ {
+ interrupt=false;
+ timer=false;
+ lastTimer=0;
+ hitVector=false;
+ instructionCount=0;
+ for (int i=0; i<memory.length; i++)
+ {
+ memory[i]=0;
+ }
+
+ setPcToVector(VECTOR_RESET); // starting address
+ startStack=getStartStack();
+ minStack=startStack;
+ changeSp(startStack);
+
+ intSp=0;
+
+ }
+
+
+ private void instructionLoop() throws EndSessionException, CPUException
+ {
+ /* wait for connection.... */
+ for (;;)
+ {
+ try
+ {
+
+ /*
+ * execute an instruction.
+ *
+ * If an exception happens while executing the instruction,
+ * invoke the approperiate exception vector.
+ *
+ * If a second exception occurs while invoking the
+ * exception(i.e. before the first instruction of the vector
+ * is executed), invoke the reboot exception.
+ */
+ executeInstruction();
+ } catch (DebuggerBreakpointException e1)
+ {
+ suspend();
+ } catch (InterruptException e1)
+ {
+ armVector(VECTOR_INTERRUPT);
+ } catch (IllegalInstructionException e1)
+ {
+ suspend();
+ } catch (MemoryAccessException e1)
+ {
+ suspend();
+ } catch (CPUException e)
+ {
+ suspend();
+ } catch (GDBServerException e)
+ {
+ suspend();
+ } catch (IOException e)
+ {
+ e.printStackTrace();
+ suspend();
+ } catch (RuntimeException e)
+ {
+ e.printStackTrace();
+ suspend();
+ } finally
+ {
+ checkCommit();
+ }
+ }
+ }
+
+
+ private void armVector(int vector)
+ {
+ // for now we always break as soon as we hit a vector
+ if (vector!=VECTOR_INTERRUPT)
+ {
+ // print(MINIMAL, "Vector " + vector + " armed at PC: " + formatHex(pc, "00000000"));
+ suspend();
+ }
+ hitVector=true;
+ nextVector=vector;
+ }
+
+ private void checkVector() throws CPUException
+ {
+ if (hitVector)
+ {
+ hitVector=false;
+ invokeVector(nextVector);
+ }
+ }
+
+
+ private void invokeVector(int vector) throws CPUException
+ {
+ push(pc);
+ setPcToVector(vector);
+ }
+
+ private void setPcToVector(int vector) throws MemoryAccessException
+ {
+ setPc(VECTORSIZE*vector+VECTORBASE);
+ }
+
+ private void executeInstruction() throws CPUException, EndSessionException, GDBServerException, IOException
+ {
+ for (;;)
+ {
+ checkHalt();
+
+ /* jump to any armed vector */
+ checkVector();
+
+ checkInterrupts();
+
+ tracer.instructionEvent();
+
+
+
+
+
+ commit = false;
+ savedSp=getSp();
+ savedPc=pc;
+ savedDecodeMask=decodeMask;
+ touchedPc=false;
+
+ instruction=cpuReadByte(pc);
+ // electrons perish each time we attempt an instruction
+ tick();
+
+ if (((instruction&0x80)!=0))
+ {
+ int t=((instruction<<(32-7)))>>(32-7);
+
+ if (decodeMask)
+ {
+ int a;
+ a=(popIntStack()<<7)|(t&0x7f);
+ pushIntStack(a);
+ } else
+ {
+ pushIntStack(t);
+ }
+ decodeMask=true;
+ } else
+ {
+ decodeMask = false;
+ if (isAddSP(instruction))
+ {
+ int offset=instruction - ADDSP;
+ int valAddr=sp+offset*4;
+ int a = popIntStack();
+ pushIntStack(cpuReadLong(valAddr) + a);
+ } else if ((instruction >= LOADSP) && (instruction < LOADSP + 32))
+ {
+ int addr;
+ addr = getSp();
+ int offset=(instruction - LOADSP)^0x10;
+ addr += 4 * offset;
+ pushIntStack(cpuReadLong(addr));
+ } else if (isStoreSP(instruction))
+ {
+ int addr;
+ addr = getSp();
+ int offset=(instruction - STORESP)^0x10;
+ addr += 4 * offset;
+
+ cpuWriteLong(addr, popIntStack());
+ } else
+ {
+ int addr;
+ int val;
+ switch (instruction)
+ {
+ case 0:
+ throw new DebuggerBreakpointException();
+
+ case PUSHPC:
+ pushIntStack(pc);
+ break;
+ case OR:
+ pushIntStack(popIntStack() | popIntStack());
+ break;
+ case NOT:
+ pushIntStack(popIntStack() ^ 0xffffffff);
+ break;
+ case LOAD:
+ pushIntStack(cpuReadLong(popIntStack()));
+ break;
+ case PUSHSPADD:
+ if (feeble[PUSHSPADD])
+ {
+ emulate();
+ } else
+ {
+ int a;
+ int b;
+ a=sp;
+ b=popIntStack()*4;
+ pushIntStack(a+b);
+ }
+ break;
+ case STORE:
+ addr = popIntOrExt();
+ val = popIntOrExt();
+ cpuWriteLong(addr, val);
+ break;
+ case POPPC:
+ {
+ // NB!!!! does NOT flush internal stack
+ int a;
+ if (intSp>0)
+ {
+ a=popIntStack();
+ } else
+ {
+ a=pop();
+ }
+
+ if ((sp>=emulateSp)&&(emulateInProgress))
+ {
+ emulateInProgress=false;
+ /* we returned from an emulate instruction */
+ emulateOpcodeHistogram[emulateOpcode]++;
+ emulateOpcodeHistogramCycles[emulateOpcode]+=cycles-emulateCycles;
+ }
+
+ setPc(a);
+ break;
+ }
+ case POPPCREL:
+ if (feeble[POPPCREL])
+ {
+ emulate();
+ } else
+ {
+ setPc(popIntStack()+getPc());
+ }
+ break;
+ case FLIP:
+ pushIntStack(flip(popIntStack()));
+ break;
+ case ADD:
+ pushIntStack(popIntStack() + popIntStack());
+ break;
+ case SUB:
+ if (feeble[SUB])
+ {
+ emulate();
+ } else
+ {
+ int a=popIntStack();
+ int b=popIntStack();
+ pushIntStack(b-a);
+ }
+ break;
+ case PUSHSP:
+ pushIntStack(getSp());
+ break;
+ case POPSP:
+ changeSp(popIntStack());
+ intSp=0; // flush internal stack
+ break;
+ case NOP:
+ break;
+ case AND:
+ pushIntStack(popIntStack() & popIntStack());
+ break;
+ case XOR:
+ if (feeble[XOR])
+ {
+ emulate();
+ } else
+ {
+ pushIntStack(popIntStack() ^ popIntStack());
+ }
+ break;
+ case LOADB:
+ if (feeble[LOADB])
+ {
+ emulate();
+ } else
+ {
+ pushIntStack(cpuReadByte(popIntStack()));
+ }
+ break;
+ case STOREB:
+ if (feeble[STOREB])
+ {
+ emulate();
+ } else
+ {
+ addr = popIntStack();
+ val = popIntStack();
+ cpuWriteByte(addr, val);
+ }
+ break;
+ case LOADH:
+ if (feeble[LOADH])
+ {
+ emulate();
+ } else
+ {
+ pushIntStack(cpuReadWord(popIntStack()));
+ }
+ break;
+ case STOREH:
+ if (feeble[STOREH])
+ {
+ emulate();
+ } else
+ {
+ addr = popIntStack();
+ val = popIntStack();
+ cpuWriteWord(addr, val);
+ }
+ break;
+ case LESSTHAN:
+ if (feeble[LESSTHAN])
+ {
+ emulate();
+ } else
+ {
+ int a;
+ int b;
+ a = popIntStack();
+ b = popIntStack();
+ pushIntStack((a < b) ? 1 : 0);
+ }
+ break;
+ case LESSTHANOREQUAL:
+ if (feeble[LESSTHANOREQUAL])
+ {
+ emulate();
+ } else
+ {
+ int a;
+ int b;
+ a = popIntStack();
+ b = popIntStack();
+ pushIntStack((a <= b) ? 1 : 0);
+ }
+ break;
+ case ULESSTHAN:
+ if (feeble[ULESSTHAN])
+ {
+ emulate();
+ } else
+ {
+ long a;
+ long b;
+ a = ((long) popIntStack()) & INTMASK;
+ b = ((long) popIntStack()) & INTMASK;
+ pushIntStack((a < b) ? 1 : 0);
+ }
+ break;
+ case ULESSTHANOREQUAL:
+ if (feeble[ULESSTHANOREQUAL])
+ {
+ emulate();
+ } else
+ {
+ long a;
+ long b;
+ a = ((long) popIntStack()) & INTMASK;
+ b = ((long) popIntStack()) & INTMASK;
+ pushIntStack((a <= b) ? 1 : 0);
+ }
+ break;
+
+ case SWAP:
+// if (feeble[SWAP])
+// {
+// emulate();
+// } else
+ {
+ int swapVal=popIntStack();;
+ pushIntStack(((swapVal >>16)&0xffff)|(swapVal<<16));
+ }
+ break;
+ case MULT16X16:
+// if (feeble[SWAP])
+// {
+// emulate();
+// } else
+ {
+ int a=popIntStack();
+ int b=popIntStack();
+ pushIntStack((a&0xffff)*(b&0xffff));
+ }
+ break;
+ case EQBRANCH:
+ if (feeble[EQBRANCH])
+ {
+ emulate();
+ } else
+ {
+ int compare;
+ int target;
+ target = popIntStack() + pc;
+ compare = popIntStack();
+ if (compare == 0)
+ {
+ setPc(target);
+ } else
+ {
+ setPc(pc + 1);
+ }
+ }
+ break;
+
+ case NEQBRANCH:
+ if (feeble[NEQBRANCH])
+ {
+ emulate();
+ } else
+ {
+ int compare;
+ int target;
+ target = popIntStack() + pc;
+ compare = popIntStack();
+ if (compare != 0)
+ {
+ setPc(target);
+ } else
+ {
+ setPc(pc + 1);
+ }
+ }
+ break;
+
+ case MULT:
+ if (feeble[MULT])
+ {
+ emulate();
+ } else
+ {
+ pushIntStack(popIntStack() * popIntStack());
+ }
+ break;
+ case DIV:
+ if (feeble[DIV])
+ {
+ emulate();
+ } else
+ {
+ int a;
+ int b;
+ a = popIntStack();
+ b = popIntStack();
+ if (b == 0)
+ {
+ throw new CPUException();
+ }
+ pushIntStack(a / b);
+ }
+ break;
+ case MOD:
+ if (feeble[MOD])
+ {
+ emulate();
+ } else
+ {
+ int a;
+ int b;
+ a = popIntStack();
+ b = popIntStack();
+ if (b == 0)
+ {
+ throw new CPUException();
+ }
+ pushIntStack(a % b);
+ }
+ break;
+
+ case LSHIFTRIGHT:
+ if (feeble[LSHIFTRIGHT])
+ {
+ emulate();
+ } else
+ {
+ long shift;
+ long valX;
+ int t;
+ shift = ((long) popIntStack()) & INTMASK;
+ valX = ((long) popIntStack()) & INTMASK;
+ t = (int) (valX >> (shift & 0x3f));
+ pushIntStack(t);
+ }
+ break;
+
+ case ASHIFTLEFT:
+ if (feeble[ASHIFTLEFT])
+ {
+ emulate();
+ } else
+ {
+ long shift;
+ long valX;
+ shift = ((long) popIntStack()) & INTMASK;
+ valX = ((long) popIntStack()) & INTMASK;
+ int t = (int) (valX << (shift & 0x3f));
+ pushIntStack(t);
+ }
+ break;
+
+ case ASHIFTRIGHT:
+ if (feeble[ASHIFTRIGHT])
+ {
+ emulate();
+ } else
+ {
+ long shift;
+ int valX;
+ shift = ((long) popIntStack()) & INTMASK;
+ valX = popIntStack();
+ int t = valX >> (shift & 0x3f);
+ pushIntStack(t);
+ }
+ break;
+
+ case CALL:
+ if (feeble[CALL])
+ {
+ emulate();
+ } else
+ {
+ intSp=0; // flush internal stack
+ int address = pop();
+ push(pc + 1);
+ setPc(address);
+ }
+ break;
+ case CALLPCREL:
+ if (feeble[CALLPCREL])
+ {
+ emulate();
+ } else
+ {
+ intSp=0; // flush internal stack
+ int address = pop();
+ push(pc + 1);
+ setPc(address+pc);
+ }
+ break;
+
+ case EQ:
+ if (feeble[EQ])
+ {
+ emulate();
+ } else
+ {
+ pushIntStack((popIntStack() == popIntStack()) ? 1 : 0);
+ }
+ break;
+
+ case NEQ:
+ if (feeble[NEQ])
+ {
+ emulate();
+ } else
+ {
+ pushIntStack((popIntStack() != popIntStack()) ? 1 : 0);
+ }
+ break;
+
+ case NEG:
+ if (feeble[NEG])
+ {
+ emulate();
+ } else
+ {
+ pushIntStack(-popIntStack());
+ }
+ break;
+
+
+ case CONFIG:
+ if (emulateConfig())
+ {
+ emulate();
+ cpu=ABEL;
+ } else
+ {
+ cpu = popIntStack();
+ }
+ switch (cpu)
+ {
+ case ABEL:
+ System.err.println("ZPU feeble instruction set");
+ for (int i = 0; i < feeble.length; i++)
+ {
+ feeble[i] = true;
+ }
+
+ setFeeble();
+
+ break;
+ case ZETA:
+ System.err.println("ZPU full instruction set");
+ for (int i = 0; i < feeble.length; i++)
+ {
+ feeble[i] = false;
+ }
+ break;
+ default:
+ break;
+ }
+ break;
+
+ case SYSCALL:
+ if (feeble[SYSCALL])
+ {
+ throw new IllegalInstructionException();
+ } else
+ {
+ intSp=0; // flush internal stack
+ syscall.syscall(this);
+ }
+ break;
+
+ default:
+ throw new IllegalInstructionException();
+ }
+ }
+ }
+ if (!touchedPc)
+ {
+ setPc(pc + 1);
+ }
+ committed();
+
+ // one more instruction retired
+ instructionCount++;
+ }
+ }
+
+
+ protected void setFeeble()
+ {
+ feeble[NEQBRANCH] = false;
+ feeble[EQ] = false;
+ feeble[LOADB] = false;
+ feeble[LESSTHAN] = false;
+ feeble[ULESSTHAN] = false;
+ feeble[STOREB] = false;
+ feeble[MULT] = false;
+ feeble[CALL] = true;
+ feeble[POPPCREL] = true;
+ feeble[LESSTHANOREQUAL] = true;
+ feeble[ULESSTHANOREQUAL] = true;
+
+ feeble[PUSHSPADD] = false;
+ feeble[CALLPCREL] = false;
+ feeble[SUB] = false;
+ }
+
+
+ private int popIntOrExt()
+ {
+ int a;
+ if (intSp==0)
+ {
+ a=pop();
+ } else
+ {
+ a=popIntStack();
+ }
+ return a;
+ }
+
+ int intSp;
+
+ private int emulateSp;
+
+ private int emulateOpcode;
+
+ private boolean emulateInProgress;
+
+ protected boolean timerPending;
+
+ private boolean inInterrupt;
+ private int popIntStack()
+ {
+// if (intSp<=0)
+// throw new IllegalInstructionException();
+ intSp--;
+ return pop();
+ }
+
+ private void pushIntStack(int x)
+ {
+// if (intSp>=32)
+// throw new IllegalInstructionException();
+ push(x);
+ intSp++;
+ }
+
+
+
+ private static boolean isAddSP(int instruction)
+ {
+ return (instruction >= ADDSP) && (instruction < ADDSP + 16);
+ }
+
+
+ private static boolean isStoreSP(int instruction)
+ {
+ return (instruction >= STORESP) && (instruction < STORESP + 32);
+ }
+
+
+ protected boolean emulateConfig()
+ {
+ return false;
+ }
+
+
+ private void checkCommit() throws CPUException
+ {
+ if (!commit)
+ {
+ decodeMask=savedDecodeMask;
+ pc=savedPc;
+ setSp(savedSp);
+ committed();
+ }
+ }
+
+
+ private void committed()
+ {
+ commit=true;
+ tracer.commit();
+ }
+
+
+ private void emulate() throws CPUException
+ {
+ // NB! Do NOT flush internal stack
+// intSp=0; // flush internal stack
+ /* three total overhead to emulate instruction */
+ if (!emulateInProgress)
+ {
+ emulateInProgress=true;
+ emulateSp = sp;
+ emulateOpcode = getOpcode();
+ emulateCycles = cycles;
+ }
+ pushIntStack(pc+1);
+ setPc((cpuReadByte(pc)-32)*VECTORSIZE+VECTORBASE);
+ }
+
+
+
+ private void checkInterrupts() throws InterruptException
+ {
+ if (!tracer.simInterrupt())
+ {
+ /* These flags are set *regardless* of interrupt state. */
+ while (lastTimer+timerInterval<cycles)
+ {
+ if (timerInterval>0)
+ {
+ lastTimer+=timerInterval;
+ } else
+ {
+ lastTimer=cycles;
+ }
+ timerPending=true;
+ }
+ }
+
+ if (!interrupt)
+ return;
+
+ /* if we are in the middle of decoding an instruction, no interrupt */
+ if (decodeMask)
+ {
+ return;
+ }
+ if (tracer.simInterrupt())
+ {
+ if (!tracer.onInterrupt())
+ {
+ inInterrupt=false;
+ }
+ if (inInterrupt)
+ {
+ return;
+ }
+ /* Use trace information instead of trying to figure out when an interrupt happens. We don't try
+ * to simulate anything more complicated than timer interrupts so we don't need to worry about source.
+ */
+
+ if (tracer.onInterrupt()&&!inInterrupt)
+ {
+ if (!timer)
+ {
+ throw new IllegalInstructionException();
+ }
+
+ inInterrupt=true;
+ timerPending=true;
+ throw new InterruptException();
+ }
+
+ } else
+ {
+ if (!timerPending)
+ inInterrupt=false;
+
+ if (inInterrupt)
+ {
+ return;
+ }
+
+ if (timer&&timerPending)
+ {
+ inInterrupt=true;
+ throw new InterruptException();
+ }
+ }
+ }
+
+
+
+
+ private void cpuWriteWord(int addr, int val) throws MemoryAccessException
+ {
+ if ((addr&0x1)!=0)
+ {
+ throw new MemoryAccessException();
+ }
+ for (int i=0; i<2; i++)
+ {
+ writeByte(addr+i, val>>(8*(1-i)));
+ }
+ }
+
+ /**
+ * @param i
+ * @return
+ * @throws MemoryAccessException
+ */
+ private int cpuReadWord(int addr) throws MemoryAccessException
+ {
+ if ((addr&0x1)!=0)
+ {
+ throw new MemoryAccessException();
+ }
+ return ((readByteInternal(addr+0)&0xff)<<8) | (readByteInternal(addr+1)&0xff);
+ }
+
+ private void cpuWriteByte(int addr, int val) throws MemoryAccessException
+ {
+ writeByte(addr, val);
+ }
+
+
+ protected boolean interrupt;
+ protected long timerInterval;
+ private boolean touchedPc;
+
+ private boolean accessWatchPoint;
+
+ private int accessWatchPointAddress;
+
+ private int accessWatchPointLength;
+
+ private boolean commit;
+
+ private boolean savedDecodeMask;
+
+ private int savedSp;
+
+ private int savedPc;
+
+ private long[] profile;
+
+ private int cpu;
+
+ private long sampledCycle;
+
+ private Tracer tracer=new Tracer()
+ {
+
+ public void instructionEvent()
+ {
+
+ }
+
+ public void commit()
+ {
+ }
+
+ public void setSp(int sp)
+ {
+ }
+
+ public void dumpTraceBack()
+ {
+
+ }
+
+ public boolean onInterrupt()
+ {
+ return false;
+ }
+
+ public boolean simInterrupt()
+ {
+ return false;
+ }
+
+ };
+
+ private int instruction;
+
+ private long totalCycles;
+
+
+ private String traceFileName;
+
+ private int prevOpcode;
+
+ private long prevCycles2;
+
+ private int prevOpcode2;
+
+
+
+
+ /**
+ * checks if the CPU should halt, and halts. Fn. returns when the
+ * CPU has resumed execution.
+ * @throws EndSessionException
+ */
+ private void checkHalt() throws EndSessionException
+ {
+ synchronized(halt)
+ {
+ if (powerdown)
+ {
+ throw new EndSessionException();
+ }
+
+ if (breakNext)
+ {
+ breakNext=false;
+
+ halt.notify();
+ try
+ {
+ syscall.halted();
+ halt.wait();
+ syscall.running();
+ } catch (InterruptedException e)
+ {
+ e.printStackTrace();
+ }
+ }
+
+ if (powerdown)
+ {
+ throw new EndSessionException();
+ }
+ }
+ }
+
+ private int flip(int i)
+ {
+ int t=0;
+ for (int j=0; j<32; j++)
+ {
+ t|=((i>>j)&1)<<(31-j);
+ }
+ return t;
+ }
+
+ /** the CPU is writing a long during execution */
+ public void cpuWriteLong(int addr, int val) throws MemoryAccessException
+ {
+ if (accessWatchPoint&&(addr==accessWatchPointAddress))
+ {
+ suspend();
+ }
+ if ((addr&0x3)!=0)
+ {
+ throw new MemoryAccessException();
+ }
+ if ((addr>=getIO())&&(addr<getIO()+IOSIZE))
+ {
+ ioWrite(addr, val);
+ } else if ((addr>=0)&&(addr<=memory.length*4))
+ {
+ memory[addr/4]=val;
+ validMemory[addr/4]=true;
+ } else
+ {
+ throw new MemoryAccessException();
+ }
+ }
+
+ public void writeByte(int addr, int val) throws MemoryAccessException
+ {
+ if ((addr>=0)&&(addr<memory.length*4))
+ {
+ memory[addr/4]=(memory[addr/4]&(~(0xff<<((3-addr&3)*8))))|((val&0xff)<<((3-addr&3)*8));
+ } else
+ {
+ throw new MemoryAccessException();
+ }
+ }
+
+ protected void ioWrite(int addr, int val) throws MemoryAccessException
+ {
+ addr-=getIO();
+ /* note, big endian! */
+ switch (addr)
+ {
+ case 12:
+ syscall.writeUART(val);
+ break;
+ case 20:
+ interrupt=val!=0;
+ break;
+ case 28:
+ timerInterval=val;
+ break;
+ case 32:
+ timer=val!=0;
+ break;
+ case 0x24:
+ syscall.writeUART(val);
+ break;
+ case 0x100:
+ writeTimerSampleReg(val);
+ break;
+ default:
+ break;
+ }
+
+ }
+
+
+
+
+ protected void writeTimerSampleReg(int val)
+ {
+ if ((val&0x2)!=0)
+ {
+ sampledCycle=getSampleOffset(); // we need a fudge factor to make up for differences in when relative to the instruction the data is sampled.
+ }
+ }
+
+
+ protected long getSampleOffset()
+ {
+ return cycles+2+0xd-(0x8e-0x74);
+ }
+
+
+
+ protected int ioRead(int addr) throws CPUException
+ {
+ addr-=getIO();
+ /* note, big endian! */
+ switch (addr)
+ {
+ case 20:
+ return interrupt?1:0;
+
+ case 32:
+ return timer?1:0;
+
+ case 0x24:
+ return syscall.readUART();
+
+ /* FIFO empty? bit 0, FIFO full bit 1(never the case) */
+ case 0x28:
+ return syscall.readFIFO();
+
+ case 0x100:
+ case 0x104:
+ case 0x108:
+ case 0x10c:
+
+ case 0x110:
+ case 0x114:
+ case 0x118:
+ case 0x11c:
+ return readSampledTimer(addr, 0x100);
+
+ case 0x200:
+ return readMHz();
+
+ default:
+ throw new MemoryAccessException();
+ }
+ }
+
+
+
+
+ protected int readMHz()
+ {
+ /* 90 MHz */
+ return 100;
+ }
+
+
+ protected int readSampledTimer(int addr, int base)
+ {
+ int t=0;
+ t=(int)((sampledCycle>>(((addr-base)/4)*32))&0xffffffff);
+ return t;
+ }
+
+
+
+ private int cpuReadByte(int addr) throws MemoryAccessException
+ {
+ return readByteInternal(addr);
+ }
+
+
+ /** this is the CPU reading a long word during execution */
+ public int cpuReadLong(int addr) throws CPUException
+ {
+ if (accessWatchPoint&&(addr==accessWatchPointAddress))
+ {
+ suspend();
+ }
+ if ((addr&0x3)!=0)
+ {
+ throw new MemoryAccessException();
+ }
+ if ((addr>=getIO())&&(addr<getIO()+IOSIZE))
+ {
+ return ioRead(addr);
+ } else if ((addr>=0)&&(addr<=memory.length*4))
+ {
+ return memory[addr/4];
+ } else
+ {
+ throw new MemoryAccessException();
+ }
+ }
+
+ /**
+ * Causes a cycle to pass.
+ * @throws MemoryAccessException
+ */
+ /** increase time and record how long we spent on this instruction */
+ private void tick() throws MemoryAccessException
+ {
+ profile[pc]++;
+ int opcode;
+ opcode=readByte(pc);
+ opcodeHistogram[prevOpcode]++;
+ opcodeHistogramCycles[prevOpcode]+=cycles-prevCycles;
+ int opcodePair=groupOpcode(prevOpcode2)*256+groupOpcode(prevOpcode);
+
+ opcodePairHistogram[opcodePair]++;
+ opcodePairHistogramCycles[opcodePair]+=cycles-prevCycles2;
+
+ prevOpcode2=prevOpcode;
+ prevOpcode=opcode;
+
+
+
+ prevCycles2=prevCycles;
+ prevCycles=cycles;
+ cycles++;
+ }
+
+ private int groupOpcode(int instruction)
+ {
+ if (isAddSP(instruction))
+ {
+ return ADDSP;
+ } else if ((instruction >= LOADSP) && (instruction < LOADSP + 32))
+ {
+ return LOADSP;
+ } else if (isStoreSP(instruction))
+ {
+ return STORESP;
+ }
+
+ if ((instruction&0x80)!=0)
+ return 0x80;
+ return instruction;
+ }
+
+
+ public int readByte(int addr) throws MemoryAccessException
+ {
+ if ((addr>=0)&&(addr<memory.length*4))
+ {
+ return readByteInternal(addr);
+ } else
+ {
+ throw new MemoryAccessException();
+ }
+ }
+
+
+ protected int readByteInternal(int addr) throws MemoryAccessException
+ {
+ return (memory[addr/4]>>((3-addr&0x3)*8))&0xff;
+ }
+
+ private int pop() throws CPUException
+ {
+ int val;
+ validMemory[getSp()/4]=false;
+ val=cpuReadLong(getSp());
+ setSp(getSp() + 4);
+ return val;
+ }
+
+ private void push(int imm) throws CPUException
+ {
+ setSp(getSp() - 4);
+ cpuWriteLong(getSp(), imm);
+ }
+
+ private final class OpcodeSample
+ {
+ private final int j;
+
+ int opcode;
+
+ long count;
+
+ private OpcodeSample(int j, long l)
+ {
+ this.j = j;
+ opcode = j;
+ count = l;
+ }
+ }
+
+
+
+
+ private void initRam()
+ {
+ memory = (new int[getRAMSIZE()/4]);
+ validMemory = new boolean[getRAMSIZE()/4];
+ for (int i=0; i<validMemory.length; i++)
+ {
+ validMemory[i]=true;
+ }
+
+ profile = new long[getRAMSIZE()];
+ }
+
+
+
+ public void setPc(int pc) throws MemoryAccessException
+ {
+ if ((pc<VECTORBASE)||(pc>memory.length*4))
+ {
+ throw new MemoryAccessException();
+ }
+ this.pc = pc;
+ touchedPc=true;
+ }
+
+ public int getPc()
+ {
+ return pc;
+ }
+
+ /** resume execution. This function returns when the CPU halts again. */
+ public void cont()
+ {
+ for (;;)
+ {
+ synchronized(halt)
+ {
+ halt.notify();
+ try
+ {
+ halt.wait();
+ } catch (InterruptedException e)
+ {
+ e.printStackTrace();
+ }
+ }
+ if (syscall.doneContinue())
+ {
+ break;
+ }
+ }
+ }
+
+ /** resume execution. This function returns when the CPU halts again. */
+ public void step()
+ {
+ synchronized(halt)
+ {
+ suspend();
+ cont();
+ }
+ }
+
+
+
+ public int getReg(int regNum) throws CPUException
+ {
+ if ((regNum>=0)&&(regNum<32))
+ {
+ return memory[regNum];
+ } else if (regNum==32)
+ {
+ return getSp();
+ } else if (regNum==33)
+ {
+ return pc;
+ } else
+ {
+ throw new RuntimeException("Illegal getReg()");
+ }
+ }
+
+ public int getREGNUM()
+ {
+ return 34;
+ }
+
+ public long getCycleCounter()
+ {
+ return cycles;
+ }
+
+ public void addWaitStates(int num)
+ {
+ }
+
+ /** tells simulator to enter the suspended state */
+ public void suspend()
+ {
+ synchronized(halt)
+ {
+ breakNext=true;
+ }
+// tracer.dumpTraceBack();
+ }
+
+
+ public long getPrevCycles()
+ {
+ return prevCycles;
+ }
+
+ public long getCycles()
+ {
+ return cycles;
+ }
+
+
+ public void enableAccessWatchPoint(int address, int length) throws CPUException
+ {
+ if (accessWatchPoint)
+ {
+ throw new HardwareWatchPointException();
+ }
+ accessWatchPointAddress=address;
+ accessWatchPointLength=length;
+ accessWatchPoint=true;
+ }
+ public void disableAccessWatchPoint(int address, int length) throws CPUException
+ {
+ if (!accessWatchPoint)
+ {
+ throw new HardwareWatchPointException();
+ }
+ if ((address!=accessWatchPointAddress)||(length!=accessWatchPointLength))
+ {
+ throw new HardwareWatchPointException();
+ }
+
+ accessWatchPoint=false;
+ }
+
+ /** POPSP changes the stack pointer */
+ public void changeSp(int sp) throws CPUException
+ {
+ setSp(sp);
+ tracer.setSp(sp);
+ }
+
+ public void setSp(int sp) throws CPUException
+ {
+ if ((sp%4)!=0)
+ {
+ throw new IllegalInstructionException();
+ }
+
+ if (sp<minStack)
+ {
+ minStack=sp;
+ }
+
+
+ this.sp = sp;
+ }
+
+
+ public int getSp()
+ {
+ return sp;
+ }
+ public int getIntSp()
+ {
+ return (intSp+(INTSTACKSIZE-1))%INTSTACKSIZE;
+ }
+
+
+
+
+ protected int getIO()
+ {
+ return 0x80000000;
+ }
+
+
+ protected int getRAMSIZE()
+ {
+ return (2*1024*1024);
+ }
+
+ protected int getStartStack()
+ {
+ return memory.length*4-0x10000;
+ }
+
+
+ public void setTraceFile(String string)
+ {
+ traceFileName=string;
+ }
+
+
+ public void setSyscall(Host syscall)
+ {
+ this.syscall=syscall;
+ }
+
+
+ public void loadImage(InputStream inputStream, int length) throws IOException, CPUException
+ {
+ if (length==-1)
+ throw new IOException("File image length not known");
+ for (int i=0; i<length; i++)
+ {
+ int t=inputStream.read();
+ writeByte(0+i, t);
+ }
+
+ }
+
+ public int getArg(int num) throws CPUException
+ {
+ return cpuReadLong(getSp()+4+num*4);
+ }
+
+
+ public int getOpcode() throws MemoryAccessException
+ {
+ return readByte(pc);
+ }
+
+ static final int INTSTACKSIZE=32;
+
+ public boolean checkMatch(Trace trace)
+ {
+ cycles=trace.cycle;
+ if (!trace.undefinedIntSp)
+ {
+ if (trace.intSp!=((intSp+(INTSTACKSIZE-1))%INTSTACKSIZE))
+ return false;
+ }
+
+ if ((getPc() != trace.pc) || (getSp() != trace.sp)
+ || (getOpcode() != trace.opcode))
+ {
+ return false;
+ }
+
+ if (cpuReadLong(getSp()) == trace.stackA)
+ {
+ if (cpuReadLong(getSp() + 4) == trace.stackB)
+ {
+ return true;
+ }
+ }
+ if ((!validMemory[getSp()/4])||cpuReadLong(getSp()) == trace.stackA)
+ {
+ if ((!validMemory[(getSp()+4)/4])||cpuReadLong(getSp() + 4) == trace.stackB)
+ {
+// System.out.println("Undefined memory location mismatch");
+ return true;
+ }
+ }
+ if (!trace.undefinedIntSp)
+ {
+ if ((intSp<1)||cpuReadLong(getSp()) == trace.stackA)
+ {
+ if ((intSp<2)||cpuReadLong(getSp() + 4) == trace.stackB)
+ {
+ return true;
+ }
+ }
+ }
+ return false;
+ }
+
+
+ public void sessionStarted()
+ {
+ if (traceFileName!=null)
+ {
+ tracer = new FileTracer(this, traceFileName);
+ }
+
+ /* Set the feeble flag to enable/disable instructions here */
+ initRam();
+ resetHardwareInternal();
+
+
+
+ }
+
+
+ void printState(FileTracer fileTracer)
+ {
+ System.err.println("intSp: " + getIntSp());
+ System.err.println(Integer.toHexString(getPc())+ " " +
+ Integer.toHexString(getOpcode()) + " " +
+ Integer.toHexString(getSp()) + " " +
+ Integer.toHexString(cpuReadLong(getSp())) + " " +
+ Integer.toHexString(cpuReadLong(getSp()+4)));
+ }
+
+
+
+
+
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/State.java b/zpu/sw/simulator/com/zylin/zpu/simulator/State.java
new file mode 100644
index 0000000..c2cb9f4
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/State.java
@@ -0,0 +1,9 @@
+package com.zylin.zpu.simulator;
+
+
+public class State
+{
+
+ public long cycle;
+ public int insn;
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/Tracer.java b/zpu/sw/simulator/com/zylin/zpu/simulator/Tracer.java
new file mode 100644
index 0000000..31f1766
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/Tracer.java
@@ -0,0 +1,21 @@
+
+package com.zylin.zpu.simulator;
+
+import com.zylin.zpu.simulator.exceptions.GDBServerException;
+
+public interface Tracer
+{
+
+ void instructionEvent() throws GDBServerException;
+
+ void commit();
+
+ void setSp(int sp);
+
+ void dumpTraceBack();
+
+
+ boolean onInterrupt();
+
+ boolean simInterrupt();
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/ZPU.java b/zpu/sw/simulator/com/zylin/zpu/simulator/ZPU.java
new file mode 100644
index 0000000..84a1ca5
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/ZPU.java
@@ -0,0 +1,14 @@
+package com.zylin.zpu.simulator;
+
+public interface ZPU
+{
+ /**
+ * number of cycles passed since reboot
+ */
+ long getCycleCounter();
+
+ /**
+ * Wait this many cycles
+ */
+ void addWaitStates(int i);
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/applet/ZPUApplet.java b/zpu/sw/simulator/com/zylin/zpu/simulator/applet/ZPUApplet.java
new file mode 100644
index 0000000..731c8fc
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/applet/ZPUApplet.java
@@ -0,0 +1,281 @@
+
+package com.zylin.zpu.simulator.applet;
+
+import java.applet.Applet;
+import java.awt.TextArea;
+import java.awt.event.KeyEvent;
+import java.awt.event.KeyListener;
+import java.io.IOException;
+import java.io.PipedInputStream;
+import java.io.PipedOutputStream;
+import java.lang.reflect.InvocationTargetException;
+import java.net.MalformedURLException;
+import java.net.URL;
+import java.net.URLConnection;
+
+import javax.swing.SwingUtilities;
+
+import com.zylin.zpu.simulator.Host;
+import com.zylin.zpu.simulator.Sim;
+import com.zylin.zpu.simulator.Simulator;
+import com.zylin.zpu.simulator.exceptions.CPUException;
+import com.zylin.zpu.simulator.exceptions.UnsupportedSyscallException;
+
+public class ZPUApplet extends Applet implements Host
+{
+
+ private static final long serialVersionUID = 1L;
+ private TextArea console;
+ private Simulator simulator;
+ private PipedOutputStream outputPipe;
+ private PipedInputStream inputPipe;
+
+ public void init()
+ {
+ super.init();
+
+ console=new TextArea();
+ //console.setEditable(false);
+
+
+ console.addKeyListener(new KeyListener()
+ {
+
+ public void keyPressed(KeyEvent e)
+ {
+ try
+ {
+ outputPipe.write((int)e.getKeyChar());
+ } catch (Throwable e1)
+ {
+ e1.printStackTrace();
+ }
+
+ }
+
+ public void keyReleased(KeyEvent e)
+ {
+
+ }
+
+ public void keyTyped(KeyEvent e)
+ {
+
+ }
+ });
+
+ //Add the text field to the applet.
+ add(console);
+
+ //Set the layout manager so that the text field will be
+ //as wide as possible.
+ setLayout(new java.awt.GridLayout(1,0));
+
+ validate();
+ initSimulator();
+
+ }
+
+
+
+
+
+ public void start()
+ {
+ super.start();
+ }
+
+
+
+
+
+ public void stop()
+ {
+ simulator.shutdown();
+ super.stop();
+ }
+
+ private void initSimulator()
+ {
+ final ZPUApplet me = this;
+
+ try
+ {
+ outputPipe = new PipedOutputStream();
+ inputPipe = new PipedInputStream(outputPipe);
+
+ showStatus("Loading ZPU binary image...");
+
+ Thread thread = new Thread(new Runnable() {
+ public void run() {
+ try {
+ // lineReader=new LineNumberReader(new
+ // InputStreamReader(inputPipe));
+
+ simulator = new Simulator();
+ simulator.setSyscall(me);
+
+ String file = getParameter("executable");
+
+ URL url;
+ url = new URL(getCodeBase(), file);
+ showStatus("Loading: " + url.toString() +"...");
+
+ URLConnection connection = url.openConnection();
+
+ simulator.loadImage(connection.getInputStream(), connection.getContentLength());
+
+ simulator.run();
+ } catch (Throwable e) {
+ e.printStackTrace();
+ }
+ }
+ });
+ thread.start();
+ } catch (MalformedURLException e) {
+ throw new RuntimeException(e);
+ } catch (IOException e)
+ {
+ throw new RuntimeException(e);
+ }
+ }
+
+ public void syscall(Sim s) throws CPUException
+ {
+ int retval=-1;
+ int syscallErrno=0;
+ int id;
+ id=simulator.getArg(1);
+ try
+ {
+ switch (id)
+ {
+ case SYS_write:
+ writeToConsole();
+ retval=simulator.getArg(4);
+ break;
+ case SYS_read:
+ int i;
+ for (i=0; i<simulator.getArg(4); i++)
+ {
+ int t=inputPipe.read();
+ simulator.writeByte(simulator.getArg(3)+i, t);
+ if ((t=='\n')||(t=='\r'))
+ {
+ /* done reading line */
+ i++;
+ break;
+ }
+ }
+ retval=i;
+ break;
+
+ case SYS_fstat:
+ syscallErrno=EIO;
+ retval=-1;
+ break;
+
+ default:
+ simulator.suspend();
+ throw new UnsupportedSyscallException();
+ }
+ }
+ catch (IOException e)
+ {
+ retval=-1;
+ syscallErrno=EIO;
+ }
+ simulator.cpuWriteLong(simulator.getArg(0), syscallErrno);
+ simulator.cpuWriteLong(0, retval);
+ }
+
+ private void writeToConsole() throws CPUException
+ {
+ String t="";
+ for (int i=0; i<simulator.getArg(4); i++)
+ {
+ t+=(char)simulator.readByte(simulator.getArg(3)+i);
+ }
+ final String t2=t;
+ System.out.println(t2);
+ try {
+ SwingUtilities.invokeAndWait(new Runnable()
+ {
+ public void run()
+ {
+ console.append(t2);
+ }
+ });
+ } catch (InterruptedException e) {
+ // TODO Auto-generated catch block
+ e.printStackTrace();
+ } catch (InvocationTargetException e) {
+ // TODO Auto-generated catch block
+ e.printStackTrace();
+ }
+ }
+
+
+
+
+ public boolean doneContinue()
+ {
+ return false;
+ }
+
+
+ public void writeUART(final int val)
+ {
+ try {
+ SwingUtilities.invokeAndWait(new Runnable()
+ {
+
+ public void run()
+ {
+ console.append(""+(char)(val));
+ repaint();
+
+ }
+ });
+ } catch (InterruptedException e) {
+ e.printStackTrace();
+ } catch (InvocationTargetException e) {
+ e.printStackTrace();
+ }
+ }
+
+
+
+
+
+ public int readUART() throws CPUException
+ {
+ try
+ {
+ return inputPipe.read();
+ } catch (IOException e)
+ {
+ e.printStackTrace();
+ throw new CPUException();
+ }
+ }
+
+
+
+
+
+ public int readFIFO()
+ {
+ return 0;
+ }
+
+ public void halted()
+ {
+ showStatus("ZPU application halted");
+ }
+
+ public void running()
+ {
+ showStatus("ZPU application running...");
+ }
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/BadPacketException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/BadPacketException.java
new file mode 100644
index 0000000..2e66ab4
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/BadPacketException.java
@@ -0,0 +1,22 @@
+/*
+ * Created on Nov 6, 2004
+ *
+ * To change the template for this generated file go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+package com.zylin.zpu.simulator.exceptions;
+
+/**
+ * @author oyvind
+ *
+ * To change the template for this generated type comment go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+public class BadPacketException extends GDBServerException
+{
+
+ /**
+ *
+ */
+ private static final long serialVersionUID = 3258131340821214260L;
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/CPUException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/CPUException.java
new file mode 100644
index 0000000..6a3f4fe
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/CPUException.java
@@ -0,0 +1,23 @@
+/*
+ * Created on Oct 23, 2004
+ *
+ * To change the template for this generated file go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+package com.zylin.zpu.simulator.exceptions;
+
+/**
+ * @author oyvind
+ *
+ * To change the template for this generated type comment go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+public class CPUException extends GDBServerException
+{
+
+ /**
+ *
+ */
+ private static final long serialVersionUID = 1L;
+
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/DebuggerBreakpointException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/DebuggerBreakpointException.java
new file mode 100644
index 0000000..2360fa8
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/DebuggerBreakpointException.java
@@ -0,0 +1,10 @@
+package com.zylin.zpu.simulator.exceptions;
+
+public class DebuggerBreakpointException extends CPUException
+{
+
+ /**
+ *
+ */
+ private static final long serialVersionUID = 1L;
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/EndSessionException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/EndSessionException.java
new file mode 100644
index 0000000..13fc875
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/EndSessionException.java
@@ -0,0 +1,46 @@
+/*
+ * Created on Nov 16, 2004
+ *
+ * To change the template for this generated file go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+package com.zylin.zpu.simulator.exceptions;
+
+/**
+ * @author oyvind
+ *
+ * To change the template for this generated type comment go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+public class EndSessionException extends Exception
+{
+
+ public EndSessionException()
+ {
+ super();
+ // TODO Auto-generated constructor stub
+ }
+
+ public EndSessionException(String arg0, Throwable arg1)
+ {
+ super(arg0, arg1);
+ // TODO Auto-generated constructor stub
+ }
+
+ public EndSessionException(String arg0)
+ {
+ super(arg0);
+ // TODO Auto-generated constructor stub
+ }
+
+ public EndSessionException(Throwable arg0)
+ {
+ super(arg0);
+ // TODO Auto-generated constructor stub
+ }
+
+ /**
+ *
+ */
+ private static final long serialVersionUID = 1L;
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/GDBServerException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/GDBServerException.java
new file mode 100644
index 0000000..8232790
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/GDBServerException.java
@@ -0,0 +1,25 @@
+package com.zylin.zpu.simulator.exceptions;
+
+
+public class GDBServerException extends RuntimeException
+{
+ /**
+ *
+ */
+ private static final long serialVersionUID = 1L;
+
+ public GDBServerException(NumberFormatException e)
+ {
+ super(e);
+ }
+
+ public GDBServerException()
+ {
+
+ }
+
+ public GDBServerException(Exception e)
+ {
+ super(e);
+ }
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/HardwareWatchPointException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/HardwareWatchPointException.java
new file mode 100644
index 0000000..a4ad3b2
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/HardwareWatchPointException.java
@@ -0,0 +1,12 @@
+
+package com.zylin.zpu.simulator.exceptions;
+
+public class HardwareWatchPointException extends CPUException
+{
+
+ /**
+ *
+ */
+ private static final long serialVersionUID = 1L;
+
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/IllegalInstructionException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/IllegalInstructionException.java
new file mode 100644
index 0000000..a8d0802
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/IllegalInstructionException.java
@@ -0,0 +1,23 @@
+/*
+ * Created on Oct 23, 2004
+ *
+ * To change the template for this generated file go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+package com.zylin.zpu.simulator.exceptions;
+
+
+/**
+ * @author oyvind
+ *
+ * To change the template for this generated type comment go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+public class IllegalInstructionException extends CPUException
+{
+
+ /**
+ *
+ */
+ private static final long serialVersionUID = 1L;
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/InterruptException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/InterruptException.java
new file mode 100644
index 0000000..bd74f04
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/InterruptException.java
@@ -0,0 +1,23 @@
+/*
+ * Created on 02.jan.2005
+ *
+ * To change the template for this generated file go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+package com.zylin.zpu.simulator.exceptions;
+
+
+/**
+ * @author oyvind
+ *
+ * To change the template for this generated type comment go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+public class InterruptException extends CPUException
+{
+
+ /**
+ *
+ */
+ private static final long serialVersionUID = 1L;
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/MemoryAccessException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/MemoryAccessException.java
new file mode 100644
index 0000000..4c9ebae
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/MemoryAccessException.java
@@ -0,0 +1,23 @@
+/*
+ * Created on Oct 23, 2004
+ *
+ * To change the template for this generated file go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+package com.zylin.zpu.simulator.exceptions;
+
+
+/**
+ * @author oyvind
+ *
+ * To change the template for this generated type comment go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+public class MemoryAccessException extends CPUException
+{
+
+ /**
+ *
+ */
+ private static final long serialVersionUID = 1L;
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/NoAckException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/NoAckException.java
new file mode 100644
index 0000000..377f9de
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/NoAckException.java
@@ -0,0 +1,22 @@
+/*
+ * Created on Nov 6, 2004
+ *
+ * To change the template for this generated file go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+package com.zylin.zpu.simulator.exceptions;
+
+/**
+ * @author oyvind
+ *
+ * To change the template for this generated type comment go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+public class NoAckException extends GDBServerException
+{
+
+ /**
+ *
+ */
+ private static final long serialVersionUID = 1L;
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/TraceException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/TraceException.java
new file mode 100644
index 0000000..45fda54
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/TraceException.java
@@ -0,0 +1,22 @@
+
+package com.zylin.zpu.simulator.exceptions;
+
+
+public class TraceException extends GDBServerException
+{
+
+ /**
+ *
+ */
+ private static final long serialVersionUID = 1L;
+
+ public TraceException(Exception e)
+ {
+ super(e);
+ }
+
+ public TraceException()
+ {
+ }
+
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/UnknownPacketException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/UnknownPacketException.java
new file mode 100644
index 0000000..af8a667
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/UnknownPacketException.java
@@ -0,0 +1,10 @@
+package com.zylin.zpu.simulator.exceptions;
+
+public class UnknownPacketException extends GDBServerException
+{
+
+ /**
+ *
+ */
+ private static final long serialVersionUID = 1L;
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/UnsupportedSyscallException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/UnsupportedSyscallException.java
new file mode 100644
index 0000000..6b214f1
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/UnsupportedSyscallException.java
@@ -0,0 +1,12 @@
+
+package com.zylin.zpu.simulator.exceptions;
+
+public class UnsupportedSyscallException extends CPUException
+{
+
+ /**
+ *
+ */
+ private static final long serialVersionUID = 1L;
+
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/gdb/GDBServer.java b/zpu/sw/simulator/com/zylin/zpu/simulator/gdb/GDBServer.java
new file mode 100644
index 0000000..182e426
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/gdb/GDBServer.java
@@ -0,0 +1,364 @@
+/**
+ * Handles TCP/IP communication between simulator and GDB
+ */
+
+package com.zylin.zpu.simulator.gdb;
+
+import java.io.IOException;
+import java.net.Socket;
+import java.nio.ByteBuffer;
+import java.nio.channels.SelectionKey;
+import java.nio.channels.Selector;
+import java.nio.channels.SocketChannel;
+import java.util.Iterator;
+
+import com.zylin.zpu.simulator.Host;
+import com.zylin.zpu.simulator.Sim;
+import com.zylin.zpu.simulator.SimApp;
+import com.zylin.zpu.simulator.exceptions.BadPacketException;
+import com.zylin.zpu.simulator.exceptions.CPUException;
+import com.zylin.zpu.simulator.exceptions.EndSessionException;
+import com.zylin.zpu.simulator.exceptions.GDBServerException;
+import com.zylin.zpu.simulator.exceptions.MemoryAccessException;
+import com.zylin.zpu.simulator.exceptions.UnsupportedSyscallException;
+
+public class GDBServer implements Host
+{
+ /* logging filter */
+ static final boolean UNKNOWN=false;
+ static final boolean ALL=false;
+ static final boolean CPUEXCEPTION = false;
+ static protected boolean MINIMAL=true;
+ static boolean PACKET=true;
+ static boolean REPLY=true;
+ static protected boolean IGNOREDEXCEPTIONS=false;
+
+
+
+ protected Throwable packetException;
+ protected Object packetReady=new Object();
+ private Packet packet;
+ boolean done;
+ private Socket sc;
+ public boolean alive;
+ static private int sessionNr;
+ private SimApp app;
+ Sim simulator;
+
+ public GDBServer(Sim simulator, SimApp app)
+ {
+ this.simulator=simulator;
+ this.app=app;
+ }
+
+ void print(boolean filter, String str)
+ {
+ if (filter)
+ {
+ System.out.println(str);
+ }
+ }
+
+ /** infinite loop that waits for debug sessions to be initiated via TCP/IP */
+ public void gdbServer() throws MemoryAccessException, IOException, GDBServerException, EndSessionException
+ {
+ sc=app.serverSocket.accept();
+ try
+ {
+ debugSession();
+ } catch (IOException e)
+ {
+ // the session failed...
+ if (IGNOREDEXCEPTIONS)
+ {
+ e.printStackTrace();
+ }
+ } catch (GDBServerException e)
+ {
+ // connect failed...
+ if (IGNOREDEXCEPTIONS)
+ {
+ e.printStackTrace();
+ }
+ } catch (EndSessionException e)
+ {
+ } catch (Throwable e)
+ {
+ // some terrible unforseen failure.
+ e.printStackTrace();
+ } finally
+ {
+ sc.close();
+ }
+ }
+
+
+
+ protected void sleepABit()
+ {
+ try
+ {
+ // just to avoid locking up the machine in a busy loop when
+ // debugging the Simulator
+ Thread.sleep(2000);
+ } catch (InterruptedException e1)
+ {
+ e1.printStackTrace();
+ }
+ }
+
+ private void debugSession() throws IOException, GDBServerException, EndSessionException, MemoryAccessException
+ {
+ print(MINIMAL, "GDB server waiting for connection " + sessionNr++ + "...");
+
+ try
+ {
+ sessionStarted();
+
+ expect('+'); // connection ack.
+
+ sessionLoop();
+ } finally
+ {
+ print(MINIMAL, "Session ended");
+ }
+
+ }
+
+ private void sessionStarted()
+ {
+ simulator.sessionStarted();
+ print(MINIMAL, "Session started");
+ }
+
+
+ private void sessionLoop() throws IOException, EndSessionException
+ {
+ alive=true;
+ while (alive)
+ {
+ try
+ {
+ /* wait for new packet to arrive and notify the packet execution thread... */
+ packet=new Packet(this);
+ packet.receive();
+
+ // During execution we can receive an abort/suspend command...
+ packet.parseAndExecute();
+
+ if (!alive)
+ throw new EndSessionException();
+ } catch (BadPacketException e)
+ {
+ // do nothing.
+ if (IGNOREDEXCEPTIONS)
+ {
+ e.printStackTrace();
+ }
+ sleepABit();
+ } catch (GDBServerException e)
+ {
+ if (IGNOREDEXCEPTIONS)
+ {
+ e.printStackTrace();
+ }
+ // continue processing packets
+ sleepABit();
+ }
+ }
+ }
+
+
+
+
+ void expect(char nextChar) throws IOException, GDBServerException
+ {
+ int t = read();
+ if (t!=nextChar)
+ {
+ throw new BadPacketException();
+ }
+ }
+
+ int read() throws IOException
+ {
+ flush();
+ int t=sc.getInputStream().read();
+ if (t==-1)
+ throw new IOException();
+ return t;
+ }
+
+ /**
+ * @param value
+ * @return
+ */
+ protected String printHex(int value)
+ {
+ return formatHex(value, "00000000");
+ }
+
+ /**
+ * @param value
+ * @param pad TODO
+ * @return
+ */
+ protected String formatHex(int value, String pad)
+ {
+ String t=Integer.toHexString(value);
+ if (t.length()>pad.length())
+ {
+ t=t.substring(0, pad.length());
+ }
+ return pad.substring(0, pad.length()-t.length())+t;
+ }
+
+ public void write(byte[] bytes) throws IOException
+ {
+ sc.getOutputStream().write(bytes);
+ }
+
+ void flush() throws IOException
+ {
+ sc.getOutputStream().flush();
+ }
+
+
+ private boolean enterSyscall;
+
+
+
+ /* handle all sorts of IO calls, etc. by sending them to the
+ */
+ public void syscall(Sim s) throws CPUException
+ {
+ simulator.suspend();
+ enterSyscall=true;
+ }
+
+
+ protected void performSyscall()
+ {
+ enterSyscall=false;
+ try
+ {
+ int id;
+ id=simulator.getArg(1);
+ Packet syscall;
+ syscall=new Packet(this);
+ switch (id)
+ {
+ case Host.SYS_write:
+ syscall.invokeSyscall("write", 3, "iii");
+ break;
+ case Host.SYS_read:
+ syscall.invokeSyscall("read", 3, "iii");
+ break;
+ case Host.SYS_lseek:
+ syscall.invokeSyscall("lseek", 3, "iii");
+ break;
+ case Host.SYS_open:
+ syscall.invokeSyscall("open", 3, "sii");
+ break;
+ case Host.SYS_close:
+ syscall.invokeSyscall("close", 1, "i");
+ break;
+ case Host.SYS_fstat:
+ syscall.invokeSyscall("fstat", 2, "ii");
+ break;
+ case Host.SYS_stat:
+ syscall.invokeSyscall("stat", 2, "si");
+ break;
+ case Host.SYS_isatty:
+ syscall.invokeSyscall("isatty", 1, "i");
+ break;
+ case Host.SYS_unlink:
+ syscall.invokeSyscall("unlink", 1, "s");
+ break;
+ default:
+ simulator.suspend();
+ throw new UnsupportedSyscallException();
+ }
+ simulator.cpuWriteLong(simulator.getArg(0), syscall.syscallErrno);
+ simulator.cpuWriteLong(0, syscall.syscallRetval);
+ } catch (CPUException e)
+ {
+ e.printStackTrace();
+ } catch (IOException e)
+ {
+ e.printStackTrace();
+ } catch (GDBServerException e)
+ {
+ e.printStackTrace();
+ } catch (EndSessionException e)
+ {
+ e.printStackTrace();
+ }
+ }
+
+ public boolean doneContinue()
+ {
+ if (!enterSyscall)
+ return true;
+ performSyscall();
+ return false;
+ }
+
+ public int getSyscallArg(int i) throws CPUException
+ {
+ return simulator.getArg(i+2);
+ }
+
+ public void writeUART(int val)
+ {
+ System.out.print((char)val);
+ System.out.flush();
+
+
+ Packet p=new Packet(this);
+ p.reply("O" + formatHex(val, "00"));
+ p.sendReply();
+
+
+ }
+ public int readUART() throws CPUException
+ {
+ try
+ {
+ if (System.in.available()<=0)
+ {
+ throw new MemoryAccessException();
+ }
+
+ return System.in.read();
+ } catch (IOException e)
+ {
+ e.printStackTrace();
+ }
+ return 0;
+ }
+
+ public int readFIFO()
+ {
+ try
+ {
+ return System.in.available()>0?0:1;
+ } catch (IOException e)
+ {
+ e.printStackTrace();
+ }
+ return 1;
+ }
+
+ public void halted()
+ {
+ // TODO Auto-generated method stub
+
+ }
+
+ public void running()
+ {
+ // TODO Auto-generated method stub
+
+ }
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/gdb/Packet.java b/zpu/sw/simulator/com/zylin/zpu/simulator/gdb/Packet.java
new file mode 100644
index 0000000..ad68947
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/gdb/Packet.java
@@ -0,0 +1,472 @@
+/*
+ * Created on Nov 16, 2004
+ *
+ * To change the template for this generated file go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+package com.zylin.zpu.simulator.gdb;
+
+import java.io.IOException;
+import java.util.regex.Matcher;
+import java.util.regex.Pattern;
+
+import com.zylin.zpu.simulator.exceptions.BadPacketException;
+import com.zylin.zpu.simulator.exceptions.CPUException;
+import com.zylin.zpu.simulator.exceptions.EndSessionException;
+import com.zylin.zpu.simulator.exceptions.GDBServerException;
+import com.zylin.zpu.simulator.exceptions.MemoryAccessException;
+import com.zylin.zpu.simulator.exceptions.NoAckException;
+import com.zylin.zpu.simulator.exceptions.UnknownPacketException;
+
+
+/** all packet related operations */
+class Packet
+{
+ private final GDBServer server;
+
+ Packet(GDBServer server)
+ {
+ this.server = server;
+ reply=new StringBuffer();
+ }
+
+ void receive() throws IOException, GDBServerException, EndSessionException
+ {
+ int t;
+ /* we spool until we see a $ */
+ this.server.expect('$');
+
+ StringBuffer packet=new StringBuffer();
+
+ int cc=0;
+ for (;;)
+ {
+ int t1;
+ t1=this.server.read();
+ t = t1;
+ if (t==0x7d)
+ {
+ int t2;
+ t2=this.server.read();
+ /* the next char is escaped after a GDB specific scheme. See
+ * gdb/gdb/remote.c */
+ t = t2;
+ t^=0x20;
+ } else
+ {
+ if (t=='#')
+ {
+ break;
+ }
+ }
+
+ cc+=t;
+
+ packet.append((char)t);
+ }
+ cc&=0xff;
+
+ String checkSum;
+ checkSum=""+(char)this.server.read()+(char)this.server.read();
+ int readCheckSum;
+ readCheckSum=Integer.parseInt(checkSum, 16);
+ if (readCheckSum!=cc)
+ {
+ // error
+ dumpHex(packet.toString());
+
+ this.server.write("-".getBytes());
+ throw new BadPacketException();
+ } else
+ {
+ // ack
+ this.server.write("+".getBytes());
+ }
+
+ cmd=packet.toString();
+ this.server.print(GDBServer.PACKET, "Got " + number + ": #$" + cmd + "#" + checkSum);
+ origCmd=cmd;
+ }
+
+ void parseAndExecute() throws IOException, EndSessionException
+ {
+ boolean silent=false;
+ try
+ {
+ if (checkPrefix("g"))
+ {
+ readRegisters();
+ } else if (checkPrefix("?"))
+ {
+ querySignal();
+ } else if (checkPrefix("s"))
+ {
+ doStep();
+ } else if (checkPrefix("m"))
+ {
+ try
+ {
+ readMemory();
+ } catch (CPUException e)
+ {
+ silent=true; // happens all the time while hovering over variables in the GUI
+ throw e;
+ }
+ } else if (checkPrefix("c"))
+ {
+ continueExecution();
+ } else if (checkPrefix("M"))
+ {
+ writeMemory();
+ } else if (checkPrefix("z4"))
+ {
+ disableAccessWatchPoint();
+ } else if (checkPrefix("Z4"))
+ {
+ enableAccessWatchPoint();
+ } else if (checkPrefix("k"))
+ {
+ /* we must send a reply, but not wait for ack before we shut down
+ the connection.
+ */
+ server.alive=false;
+ reply("OK");
+ } else
+ {
+ throw new UnknownPacketException();
+ }
+ } catch (UnknownPacketException e)
+ {
+ this.server.print(GDBServer.UNKNOWN, "Unknown packet: " + origCmd);
+ // empty reply to unknown packets
+ } catch (CPUException e)
+ {
+ if (!silent)
+ {
+ this.server.print(GDBServer.CPUEXCEPTION, "Exception handling GDB request");
+ if (GDBServer.CPUEXCEPTION)
+ {
+ e.printStackTrace();
+ }
+ }
+ reply("E01");
+ } catch (GDBServerException e)
+ {
+ e.printStackTrace();
+ reply("E01");
+ } catch (RuntimeException e)
+ {
+ e.printStackTrace();
+ reply("E01");
+ }
+
+ sendReply();
+ }
+
+ private void checkEmpty() throws GDBServerException
+ {
+ if (cmd.length()>0)
+ {
+ throw new GDBServerException();
+ }
+ }
+ private void dumpHex(String arrayList2)
+ {
+ for (int i=0; i<arrayList2.length(); i++)
+ {
+ System.out.println(this.server.formatHex(arrayList2.charAt(i), "00"));
+ }
+ }
+ /**
+ * @param packetString
+ * @param string
+ * @return
+ */
+ private boolean checkPrefix(String string)
+ {
+ if (cmd.length() < string.length())
+ {
+ return false;
+ } else
+ {
+ return cmd.substring(0, string.length()).equals(string);
+ }
+ }
+ /**
+ * @throws GDBServerException
+ * @throws IOException
+ * @throws MemoryAccessException
+ *
+ */
+ private void continueExecution() throws GDBServerException
+ {
+ extractString("c");
+ try
+ {
+ if (!isEmpty())
+ {
+ int pc=extractInteger();
+ this.server.simulator.setPc(pc);
+ }
+ checkEmpty();
+ this.server.simulator.cont();
+ } catch (MemoryAccessException e)
+ {
+ if (GDBServer.IGNOREDEXCEPTIONS)
+ {
+ e.printStackTrace();
+ }
+ }
+ reply("S05");
+ }
+ private void doStep()
+ {
+ this.server.simulator.step();
+ reply("S05");
+ }
+ protected int extractInteger() throws GDBServerException
+ {
+ String number;
+ Pattern p=Pattern.compile("(\\-?[0-9a-fA-F]+)");
+ Matcher m = p.matcher(cmd);
+ if (!m.find())
+ {
+ throw new GDBServerException();
+ }
+ number=m.group();
+ extractString(number);
+
+ try
+ {
+ return (int)Long.parseLong(number, 16);
+ } catch (NumberFormatException e)
+ {
+ throw new GDBServerException(e);
+ }
+ }
+ /**
+ * @param string
+ * @throws GDBServerException
+ */
+ private void extractString(String string) throws GDBServerException
+ {
+ if (!checkPrefix(string))
+ {
+ throw new GDBServerException();
+ }
+ stripStart(string.length());
+ }
+ /**
+ * @throws GDBServerException
+ *
+ */
+ private void readMemory() throws CPUException, GDBServerException
+ {
+ extractString("m");
+ int address=extractInteger();
+ extractString(",");
+ int length=extractInteger();
+ checkEmpty();
+
+ for (int i=0; i<length; i++)
+ {
+ reply(this.server.formatHex(this.server.simulator.readByte(address+i), "00"));
+ }
+ }
+ /**
+ *
+ */
+ private void readRegisters() throws CPUException
+ {
+ for (int i=0; i<this.server.simulator.getREGNUM(); i++)
+ {
+ reply(this.server.printHex(this.server.simulator.getReg(i)));
+ }
+ }
+ private void writeMemory() throws GDBServerException, MemoryAccessException
+ {
+ extractString("M");
+ int address=extractInteger();
+ extractString(",");
+ int length=extractInteger();
+ extractString(":");
+
+ for (int i=0; i<length; i++)
+ {
+ String t;
+ t=cmd.substring(i*2, i*2+2);
+ int val;
+ val=Integer.parseInt(t, 16);
+ this.server.simulator.writeByte(address+i, val);
+ }
+ reply("OK");
+
+ }
+
+ private void enableAccessWatchPoint() throws GDBServerException, CPUException
+ {
+ extractString("Z4");
+ extractString(",");
+ int address=extractInteger();
+ extractString(",");
+ int length=extractInteger();
+ checkEmpty();
+ server.simulator.enableAccessWatchPoint(address, length);
+
+ reply("OK");
+ }
+
+ private void disableAccessWatchPoint() throws GDBServerException, CPUException
+ {
+ extractString("z4");
+ extractString(",");
+ int address=extractInteger();
+ extractString(",");
+ int length=extractInteger();
+ checkEmpty();
+ server.simulator.disableAccessWatchPoint(address, length);
+
+ reply("OK");
+ }
+
+
+ private void stripStart(int length)
+ {
+ cmd=cmd.substring(length);
+ }
+ private boolean isEmpty()
+ {
+ return cmd.length()==0;
+ }
+ /**
+ * @param string
+ */
+ protected void reply(String string)
+ {
+ reply.append(string);
+ }
+ void sendReply()
+ {
+ // a bit easier to debug if we can see the entire string.
+ StringBuffer buffer = new StringBuffer();
+ buffer.append("$");
+ number++;
+ String replyString = reply.toString();
+ buffer.append(replyString);
+ byte[] data = replyString.toString().getBytes();
+ int csum = 0;
+ for (int i = 0; i < data.length; i++)
+ {
+ csum += data[i];
+ }
+ csum &= 0xff;
+ buffer.append("#");
+ String t = Integer.toHexString(csum);
+ if (t.length() == 1)
+ {
+ t = "0" + t;
+ }
+ buffer.append(t);
+ this.server.print(GDBServer.REPLY, "Reply " + number + " : " + buffer.toString());
+ try
+ {
+ this.server.write(buffer.toString().getBytes());
+ } catch (IOException e)
+ {
+ throw new RuntimeException(e);
+ }
+
+ if (server.alive)
+ {
+ /* check for ack. */
+ int ack;
+ try
+ {
+ ack = (char)this.server.read();
+ } catch (IOException e)
+ {
+ throw new RuntimeException(e);
+ }
+ if (ack == '+')
+ {
+ return;
+ }
+ this.server.print(GDBServer.MINIMAL, "Retry");
+
+ throw new NoAckException();
+ }
+ reply=new StringBuffer();
+ }
+
+ private void querySignal()
+ {
+ // SIGINT
+ // reply("S02");
+ reply("S05");
+ }
+ protected String cmd;
+ private int number;
+ private StringBuffer reply;
+ private String origCmd;
+ int syscallErrno;
+ int syscallRetval;
+
+
+
+ void invokeSyscall(String string, int argNum, String types) throws IOException, NoAckException, GDBServerException, EndSessionException, CPUException
+ {
+ string="F"+string;
+
+ int j=0;
+ for (int i=0; i<argNum; i++)
+ {
+ string+=",";
+ string+=Integer.toHexString(server.getSyscallArg(j));
+ j++;
+ if (types.charAt(i)=='s')
+ {
+ string+="/" + Integer.toHexString(server.getSyscallArg(j));
+ j++;
+ }
+ }
+
+ reply(string);
+ sendReply();
+ for (;;)
+ {
+ Packet packet=new Packet(server);
+ packet.receive();
+ if (packet.checkPrefix("F"))
+ {
+ /* this is the reply we are waiting for */
+ packet.extractString("F");
+ syscallRetval=packet.extractInteger();
+ syscallErrno=0;
+ if (packet.checkPrefix(","))
+ {
+ /* errno is optional */
+ packet.extractString(",");
+ syscallErrno = packet.extractInteger();
+ }
+ break;
+ } else
+ {
+ /* something else... */
+ try
+ {
+ packet.parseAndExecute();
+ packet.sendReply();
+ } catch (IOException e)
+ {
+ e.printStackTrace();
+ } catch (EndSessionException e)
+ {
+ e.printStackTrace();
+ } catch (RuntimeException e)
+ {
+ e.printStackTrace();
+ }
+ }
+ }
+ }
+} \ No newline at end of file
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/tools/MakeDRAM.java b/zpu/sw/simulator/com/zylin/zpu/simulator/tools/MakeDRAM.java
new file mode 100644
index 0000000..f641595
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/tools/MakeDRAM.java
@@ -0,0 +1,39 @@
+
+package com.zylin.zpu.simulator.tools;
+
+import java.io.FileInputStream;
+import java.io.IOException;
+
+public class MakeDRAM
+{
+ public static void main(String[] args) throws IOException
+ {
+ new MakeDRAM().run(args[0]);
+ }
+
+ private void run(String string) throws IOException
+ {
+ FileInputStream file=new FileInputStream(string);
+
+ int i=0;
+ while (file.available()>4)
+ {
+ byte[] tmp=new byte[4];
+ file.read(tmp);
+ int word=0;
+ for (int j=0; j<4; j++)
+ {
+ word|=((int)(tmp[j])&0xff)<<((3-j)*8);
+ }
+ String str=Integer.toHexString(word);
+ while (str.length()<8)
+ {
+ str="0"+str;
+ }
+
+ System.out.println(str);
+ i++;
+ }
+ }
+
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/tools/MakeRam.java b/zpu/sw/simulator/com/zylin/zpu/simulator/tools/MakeRam.java
new file mode 100644
index 0000000..4a7b233
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/tools/MakeRam.java
@@ -0,0 +1,39 @@
+
+package com.zylin.zpu.simulator.tools;
+
+import java.io.FileInputStream;
+import java.io.IOException;
+
+public class MakeRam
+{
+ public static void main(String[] args) throws IOException
+ {
+ new MakeRam().run(args[0]);
+ }
+
+ private void run(String string) throws IOException
+ {
+ FileInputStream file=new FileInputStream(string);
+
+ int i=0;
+ while (file.available()>4)
+ {
+ byte[] tmp=new byte[4];
+ file.read(tmp);
+ int word=0;
+ for (int j=0; j<4; j++)
+ {
+ word|=((int)(tmp[j])&0xff)<<((3-j)*8);
+ }
+ String str=Integer.toHexString(word);
+ while (str.length()<8)
+ {
+ str="0"+str;
+ }
+
+ System.out.println("" + i + " => x\"" + str + "\",");
+ i++;
+ }
+ }
+
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/stats/CountSequences.java b/zpu/sw/simulator/com/zylin/zpu/stats/CountSequences.java
new file mode 100644
index 0000000..0f06aec
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/stats/CountSequences.java
@@ -0,0 +1,94 @@
+/*
+ * Created on Jan 18, 2005
+ *
+ * TODO To change the template for this generated file go to
+ * Window - Preferences - Java - Code Style - Code Templates
+ */
+package com.zylin.zpu.stats;
+
+import java.io.File;
+import java.io.FileInputStream;
+import java.io.FileNotFoundException;
+import java.io.IOException;
+
+import com.zylin.zpu.simulator.Machine;
+
+public class CountSequences implements Machine
+{
+
+ private byte[] array;
+ private StatKeeper statKeeper;
+
+ public static void main(String[] args)
+ {
+ new CountSequences().run(args[0]);
+ }
+
+ private void run(String string)
+ {
+ try
+ {
+ File file=new File(string);
+ if (file.exists())
+ System.out.println("It exists!");
+ FileInputStream in=new FileInputStream(file);
+
+ try
+ {
+ array=new byte[(int) file.length()];
+
+ if (in.read(array)!=array.length)
+ throw new IOException();
+
+ countStats();
+
+ statKeeper.printStats();
+ } finally
+ {
+ in.close();
+ }
+
+ } catch (FileNotFoundException e)
+ {
+ e.printStackTrace();
+ } catch (IOException e)
+ {
+ e.printStackTrace();
+ }
+
+
+ }
+
+
+ private void countStats()
+ {
+ statKeeper=new StatKeeper(this);
+ for (int i=0; i<array.length; i++)
+ {
+ int j = array[i]&0xff;
+//
+// if ((j>=64)&&(j<96))
+// {
+// j=64;
+// } else if ((j>=96)&&(j<128))
+// {
+// j=96;
+// } else if ((j>=128)&&(j<256))
+// {
+// j=128;
+// }
+ statKeeper.countInstruction(j);
+ }
+
+ }
+
+ public long getPrevCycles()
+ {
+ return 0;
+ }
+
+ public long getCycles()
+ {
+ return 0;
+ }
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/stats/DumpIt.java b/zpu/sw/simulator/com/zylin/zpu/stats/DumpIt.java
new file mode 100644
index 0000000..80be11d
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/stats/DumpIt.java
@@ -0,0 +1,17 @@
+/*
+ * Created on 26.nov.2004
+ *
+ * To change the template for this generated file go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+package com.zylin.zpu.stats;
+/**
+ * @author oyvind
+ *
+ * To change the template for this generated type comment go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+public interface DumpIt
+{
+ int dumpIt(int i);
+} \ No newline at end of file
diff --git a/zpu/sw/simulator/com/zylin/zpu/stats/Instruction.java b/zpu/sw/simulator/com/zylin/zpu/stats/Instruction.java
new file mode 100644
index 0000000..252dd7f
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/stats/Instruction.java
@@ -0,0 +1,62 @@
+package com.zylin.zpu.stats;
+
+public class Instruction
+{
+ public class DumpCycles implements DumpIt
+ {
+ public int dumpIt(int i)
+ {
+ return insn[i].cycles;
+ }
+ }
+
+
+
+ public Instruction[] insn=new Instruction[256];
+ public int count;
+ public int cycles;
+
+ public Instruction addInstruction(int i)
+ {
+ if (insn[i]==null)
+ {
+ insn[i]=new Instruction();
+ }
+ return insn[i];
+ }
+
+ /**
+ * Recursive print of statistics
+ */
+ public void printStats()
+ {
+ System.out.println("Count dump");
+ DumpIt cDump = new DumpCount();
+ printCount("", cDump);
+ }
+
+ /**
+ * Recursive print of counts
+ * @param string
+ * @param dumpIt TODO
+ */
+ private void printCount(String string, DumpIt dumpIt)
+ {
+ for (int i=0; i<insn.length; i++)
+ {
+ if (insn[i]!=null)
+ {
+ insn[i].printCount(string + ", " + i, dumpIt);
+ System.out.println("Count: " + insn[i].count + string + ", " + i);
+ }
+ }
+ }
+
+ class DumpCount implements DumpIt
+ {
+ public int dumpIt(int i)
+ {
+ return insn[i].count;
+ }
+ }
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/stats/StatKeeper.java b/zpu/sw/simulator/com/zylin/zpu/stats/StatKeeper.java
new file mode 100644
index 0000000..9e16e32
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/stats/StatKeeper.java
@@ -0,0 +1,52 @@
+package com.zylin.zpu.stats;
+
+import com.zylin.zpu.simulator.Machine;
+import com.zylin.zpu.simulator.State;
+
+public class StatKeeper
+{
+ private Instruction top=new Instruction();
+ private int trackPos;
+
+ private State[] state = new State[3];
+ private Machine simulator;
+ /**
+ * @param simulator
+ */
+ public StatKeeper(Machine simulator)
+ {
+ this.simulator=simulator;
+ for (int i=0; i<state.length; i++)
+ {
+ state[i]=new State();
+ }
+ }
+ /**
+ * this instruction has been retired. Count it.
+ */
+ public void countInstruction(int instruction)
+ {
+ State currentState=state[trackPos%state.length];
+ currentState.cycle=simulator.getPrevCycles(); // start of instruction
+ currentState.insn=instruction;
+ trackPos++;
+ int backtrackNum;
+ backtrackNum=Math.min(trackPos, state.length);
+ for (int i=0; i<backtrackNum; i++)
+ {
+ Instruction t=top;
+ for (int j=0; j<=i; j++)
+ {
+ currentState=state[(trackPos-backtrackNum+j)%state.length];
+ t=t.addInstruction(currentState.insn);
+ }
+ t.count++;
+ }
+
+ }
+ public void printStats()
+ {
+ top.printStats();
+
+ }
+}
diff --git a/zpu/sw/simulator/zpusim.jar b/zpu/sw/simulator/zpusim.jar
new file mode 100644
index 0000000..e6e763a
--- /dev/null
+++ b/zpu/sw/simulator/zpusim.jar
Binary files differ
diff --git a/zpu/sw/startup/crt0.S b/zpu/sw/startup/crt0.S
new file mode 100644
index 0000000..00870c4
--- /dev/null
+++ b/zpu/sw/startup/crt0.S
@@ -0,0 +1,957 @@
+/* Startup code for ZPU
+ Copyright (C) 2005 Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file with other programs, and to distribute
+those programs without any restriction coming from the use of this
+file. (The General Public License restrictions do apply in other
+respects; for example, they cover modification of the file, and
+distribution when not linked into another program.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING. If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA. */
+ .file "crt0.S"
+
+
+
+
+; .section ".fixed_vectors","ax"
+; KLUDGE!!! we remove the executable bit to avoid relaxation
+ .section ".fixed_vectors","a"
+
+; DANGER!!!!
+; we need to align these code sections to 32 bytes, which
+; means we must not use any assembler instructions that are relaxed
+; at linker time
+; DANGER!!!!
+
+ .macro fixedim value
+ im \value
+ .endm
+
+ .macro jsr address
+
+ im 0 ; save R0
+ load
+ im 4 ; save R1
+ load
+ im 8 ; save R2
+ load
+
+ fixedim \address
+ call
+
+ im 8
+ store ; restore R2
+ im 4
+ store ; restore R1
+ im 0
+ store ; restore R0
+ .endm
+
+
+ .macro jmp address
+ fixedim \address
+ poppc
+ .endm
+
+
+ .macro fast_neg
+ not
+ im 1
+ add
+ .endm
+
+ .macro cimpl funcname
+ ; save R0
+ im 0
+ load
+
+ ; save R1
+ im 4
+ load
+
+ ; save R2
+ im 8
+ load
+
+ loadsp 20
+ loadsp 20
+
+ fixedim \funcname
+ call
+
+ ; destroy arguments on stack
+ storesp 0
+ storesp 0
+
+ im 0
+ load
+
+ ; poke the result into the right slot
+ storesp 24
+
+ ; restore R2
+ im 8
+ store
+
+ ; restore R1
+ im 4
+ store
+
+ ; restore r0
+ im 0
+ store
+
+
+ storesp 4
+ poppc
+ .endm
+
+ .macro mult1bit
+ ; create mask of lowest bit in A
+ loadsp 8 ; A
+ im 1
+ and
+ im -1
+ add
+ not
+ loadsp 8 ; B
+ and
+ add ; accumulate in C
+
+ ; shift B left 1 bit
+ loadsp 4 ; B
+ addsp 0
+ storesp 8 ; B
+
+ ; shift A right 1 bit
+ loadsp 8 ; A
+ flip
+ addsp 0
+ flip
+ storesp 12 ; A
+ .endm
+
+
+
+/* vectors */
+ .balign 32,0
+# offset 0x0000 0000
+ .globl _start
+_start:
+ ; intSp must be 0 when we jump to _premain
+
+ im ZPU_ID
+ loadsp 0
+ im _cpu_config
+ store
+ config
+ jmp _premain
+
+
+
+ .balign 32,0
+# offset 0x0000 0020
+ .globl _zpu_interrupt_vector
+_zpu_interrupt_vector:
+ jsr _zpu_interrupt
+ poppc
+
+
+/* instruction emulation code */
+
+# opcode 34
+# offset 0x0000 0040
+ .balign 32,0
+_loadh:
+ loadsp 4
+ ; by not masking out bit 0, we cause a memory access error
+ ; on unaligned access
+ im ~0x2
+ and
+ load
+
+ ; mult 8
+ loadsp 8
+ im 3
+ and
+ fast_neg
+ im 2
+ add
+ im 3
+ ashiftleft
+ ; shift right addr&3 * 8
+ lshiftright
+ im 0xffff
+ and
+ storesp 8
+
+ poppc
+
+# opcode 35
+# offset 0x0000 0060
+ .balign 32,0
+_storeh:
+ loadsp 4
+ ; by not masking out bit 0, we cause a memory access error
+ ; on unaligned access
+ im ~0x2
+ and
+ load
+
+ ; mask
+ im 0xffff
+ loadsp 12
+ im 3
+ and
+ fast_neg
+ im 2
+ add
+ im 3
+ ashiftleft
+ ashiftleft
+ not
+
+ and
+
+ loadsp 12
+ im 0xffff
+
+ nop
+
+ fixedim _storehtail
+ poppc
+
+
+# opcode 36
+# offset 0x0000 0080
+ .balign 32,0
+_lessthan:
+ loadsp 8
+ fast_neg
+ loadsp 8
+ add
+
+ ; DANGER!!!!
+ ; 0x80000000 will overflow when negated, so we need to mask
+ ; the result above with the compare positive to negative
+ ; number case
+ loadsp 12
+ loadsp 12
+ not
+ and
+ not
+ and
+
+
+ ; handle case where we are comparing a negative number
+ ; and positve number. This can underflow. E.g. consider 0x8000000 < 0x1000
+ loadsp 12
+ not
+ loadsp 12
+ and
+
+ or
+
+
+
+ flip
+ im 1
+ and
+
+
+ storesp 12
+ storesp 4
+ poppc
+
+
+# opcode 37
+# offset 0x0000 00a0
+ .balign 32,0
+_lessthanorequal:
+ loadsp 8
+ loadsp 8
+ lessthan
+ loadsp 12
+ loadsp 12
+ eq
+ or
+
+ storesp 12
+ storesp 4
+ poppc
+
+
+# opcode 38
+# offset 0x0000 00c0
+ .balign 32,0
+_ulessthan:
+ ; fish up arguments
+ loadsp 4
+ loadsp 12
+
+ /* low: -1 if low bit dif is negative 0 otherwise: neg (not x&1 and (y&1))
+ x&1 y&1 neg (not x&1 and (y&1))
+ 1 1 0
+ 1 0 0
+ 0 1 -1
+ 0 0 0
+
+ */
+ loadsp 4
+ not
+ loadsp 4
+ and
+ im 1
+ and
+ neg
+
+
+ /* high: upper 31-bit diff is only wrong when diff is 0 and low=-1
+ high=x>>1 - y>>1 + low
+
+ extremes
+
+ 0000 - 1111:
+ low= neg(not 0 and 1) = 1111 (-1)
+ high=000+ neg(111) +low = 000 + 1001 + low = 1000
+ OK
+
+ 1111 - 0000
+ low=neg(not 1 and 0) = 0
+ high=111+neg(000) + low = 0111
+ OK
+
+
+ */
+ loadsp 8
+
+ flip
+ addsp 0
+ flip
+
+ loadsp 8
+
+ flip
+ addsp 0
+ flip
+
+ sub
+
+ ; if they are equal, then the last bit decides...
+ add
+
+ /* test if negative: result = flip(diff) & 1 */
+ flip
+ im 1
+ and
+
+ ; destroy a&b which are on stack
+ storesp 4
+ storesp 4
+
+ storesp 12
+ storesp 4
+ poppc
+
+# opcode 39
+# offset 0x0000 00e0
+ .balign 32,0
+_ulessthanorequal:
+ loadsp 8
+ loadsp 8
+ ulessthan
+ loadsp 12
+ loadsp 12
+ eq
+ or
+
+ storesp 12
+ storesp 4
+ poppc
+
+
+# opcode 40
+# offset 0x0000 0100
+ .balign 32,0
+ .globl _swap
+_swap:
+ breakpoint ; tbd
+
+# opcode 41
+# offset 0x0000 0120
+ .balign 32,0
+_slowmult:
+ im _slowmultImpl
+ poppc
+
+# opcode 42
+# offset 0x0000 0140
+ .balign 32,0
+_lshiftright:
+ loadsp 8
+ flip
+
+ loadsp 8
+ ashiftleft
+ flip
+
+ storesp 12
+ storesp 4
+
+ poppc
+
+
+# opcode 43
+# offset 0x0000 0160
+ .balign 32,0
+_ashiftleft:
+ loadsp 8
+
+ loadsp 8
+ im 0x1f
+ and
+ fast_neg
+ im _ashiftleftEnd
+ add
+ poppc
+
+
+
+# opcode 44
+# offset 0x0000 0180
+ .balign 32,0
+_ashiftright:
+ loadsp 8
+ loadsp 8
+ lshiftright
+
+ ; handle signed value
+ im -1
+ loadsp 12
+ im 0x1f
+ and
+ lshiftright
+ not ; now we have an integer on the stack with the signed
+ ; bits in the right position
+
+ ; mask these bits with the signed bit.
+ loadsp 16
+ not
+ flip
+ im 1
+ and
+ im -1
+ add
+
+ and
+
+ ; stuff in the signed bits...
+ or
+
+ ; store result into correct stack slot
+ storesp 12
+
+ ; move up return value
+ storesp 4
+ poppc
+
+# opcode 45
+# offset 0x0000 01a0
+ .balign 32,0
+_call:
+ ; fn
+ loadsp 4
+
+ ; return address
+ loadsp 4
+
+ ; store return address
+ storesp 12
+
+ ; fn to call
+ storesp 4
+
+ pushsp ; flush internal stack
+ popsp
+
+ poppc
+
+_storehtail:
+
+ and
+ loadsp 12
+ im 3
+ and
+ fast_neg
+ im 2
+ add
+ im 3
+ ashiftleft
+ nop
+ ashiftleft
+
+ or
+
+ loadsp 8
+ im ~0x3
+ and
+
+ store
+
+ storesp 4
+ storesp 4
+ poppc
+
+
+# opcode 46
+# offset 0x0000 01c0
+ .balign 32,0
+_eq:
+ loadsp 8
+ fast_neg
+ loadsp 8
+ add
+
+ not
+ loadsp 0
+ im 1
+ add
+ not
+ and
+ flip
+ im 1
+ and
+
+ storesp 12
+ storesp 4
+ poppc
+
+# opcode 47
+# offset 0x0000 01e0
+ .balign 32,0
+_neq:
+ loadsp 8
+ fast_neg
+ loadsp 8
+ add
+
+ not
+ loadsp 0
+ im 1
+ add
+ not
+ and
+ flip
+
+ not
+
+ im 1
+ and
+
+ storesp 12
+ storesp 4
+ poppc
+
+
+# opcode 48
+# offset 0x0000 0200
+ .balign 32,0
+_neg:
+ loadsp 4
+ not
+ im 1
+ add
+ storesp 8
+
+ poppc
+
+
+# opcode 49
+# offset 0x0000 0220
+ .balign 32,0
+_sub:
+ loadsp 8
+ loadsp 8
+ fast_neg
+ add
+ storesp 12
+
+ storesp 4
+
+ poppc
+
+
+# opcode 50
+# offset 0x0000 0240
+ .balign 32,0
+_xor:
+ loadsp 8
+ not
+ loadsp 8
+ and
+
+ loadsp 12
+ loadsp 12
+ not
+ and
+
+ or
+
+ storesp 12
+ storesp 4
+ poppc
+
+# opcode 51
+# offset 0x0000 0260
+ .balign 32,0
+_loadb:
+ loadsp 4
+ im ~0x3
+ and
+ load
+
+ loadsp 8
+ im 3
+ and
+ fast_neg
+ im 3
+ add
+ ; x8
+ addsp 0
+ addsp 0
+ addsp 0
+
+ lshiftright
+
+ im 0xff
+ and
+ storesp 8
+
+ poppc
+
+
+# opcode 52
+# offset 0x0000 0280
+ .balign 32,0
+_storeb:
+ loadsp 4
+ im ~0x3
+ and
+ load
+
+ ; mask away destination
+ im _mask
+ loadsp 12
+ im 3
+ and
+ addsp 0
+ addsp 0
+ add
+ load
+
+ and
+
+
+ im _storebtail
+ poppc
+
+# opcode 53
+# offset 0x0000 02a0
+ .balign 32,0
+_div:
+ cimpl __divsi3
+
+# opcode 54
+# offset 0x0000 02c0
+ .balign 32,0
+_mod:
+ cimpl __modsi3
+
+# opcode 55
+# offset 0x0000 02e0
+ .balign 32,0
+ .globl _eqbranch
+_eqbranch:
+ loadsp 8
+
+ ; eq
+
+ not
+ loadsp 0
+ im 1
+ add
+ not
+ and
+ flip
+ im 1
+ and
+
+ ; mask
+ im -1
+ add
+ loadsp 0
+ storesp 16
+
+ ; no branch address
+ loadsp 4
+
+ and
+
+ ; fetch boolean & neg mask
+ loadsp 12
+ not
+
+ ; calc address & mask for branch
+ loadsp 8
+ loadsp 16
+ add
+ ; subtract 1 to find PC of branch instruction
+ im -1
+ add
+
+ and
+
+ or
+
+ storesp 4
+ storesp 4
+ storesp 4
+ poppc
+
+
+# opcode 56
+# offset 0x0000 0300
+ .balign 32,0
+ .globl _neqbranch
+_neqbranch:
+ loadsp 8
+
+ ; neq
+
+ not
+ loadsp 0
+ im 1
+ add
+ not
+ and
+ flip
+
+ not
+
+ im 1
+ and
+
+ ; mask
+ im -1
+ add
+ loadsp 0
+ storesp 16
+
+ ; no branch address
+ loadsp 4
+
+ and
+
+ ; fetch boolean & neg mask
+ loadsp 12
+ not
+
+ ; calc address & mask for branch
+ loadsp 8
+ loadsp 16
+ add
+ ; find address of branch instruction
+ im -1
+ add
+
+ and
+
+ or
+
+ storesp 4
+ storesp 4
+ storesp 4
+ poppc
+
+# opcode 57
+# offset 0x0000 0320
+ .balign 32,0
+ .globl _poppcrel
+_poppcrel:
+ add
+ ; address of poppcrel
+ im -1
+ add
+ poppc
+
+# opcode 58
+# offset 0x0000 0340
+ .balign 32,0
+ .globl _config
+_config:
+ im 1
+ nop
+ im _hardware
+ store
+ storesp 4
+ poppc
+
+# opcode 59
+# offset 0x0000 0360
+ .balign 32,0
+_pushpc:
+ loadsp 4
+ im 1
+ add
+ storesp 8
+ poppc
+
+# opcode 60
+# offset 0x0000 0380
+ .balign 32,0
+_syscall_emulate:
+ .byte 0
+
+# opcode 61
+# offset 0x0000 03a0
+ .balign 32,0
+_pushspadd:
+ pushsp
+ im 4
+ add
+ loadsp 8
+ addsp 0
+ addsp 0
+ add
+ storesp 8
+
+ poppc
+
+# opcode 62
+# offset 0x0000 03c0
+ .balign 32,0
+_halfmult:
+ breakpoint
+
+# opcode 63
+# offset 0x0000 03e0
+ .balign 32,0
+_callpcrel:
+ loadsp 4
+ loadsp 4
+ add
+ im -1
+ add
+ loadsp 4
+
+ storesp 12 ; return address
+ storesp 4
+ pushsp ; this will flush the internal stack.
+ popsp
+ poppc
+
+ .text
+
+
+
+
+_ashiftleftBegin:
+ .rept 0x1f
+ addsp 0
+ .endr
+_ashiftleftEnd:
+ storesp 12
+ storesp 4
+ poppc
+
+_storebtail:
+ loadsp 12
+ im 0xff
+ and
+ loadsp 12
+ im 3
+ and
+
+ fast_neg
+ im 3
+ add
+ ; x8
+ addsp 0
+ addsp 0
+ addsp 0
+
+ ashiftleft
+
+ or
+
+ loadsp 8
+ im ~0x3
+ and
+
+ store
+
+ storesp 4
+ storesp 4
+ poppc
+
+
+
+
+; NB! this is not an EMULATE instruction. It is a varargs fn.
+ .globl _syscall
+_syscall:
+ syscall
+ poppc
+
+_slowmultImpl:
+
+ loadsp 8 ; A
+ loadsp 8 ; B
+ im 0 ; C
+
+.LmoreMult:
+ mult1bit
+
+ ; cutoff
+ loadsp 8
+ .byte (.LmoreMult-.Lbranch)&0x7f+0x80
+.Lbranch:
+ neqbranch
+
+ storesp 4
+ storesp 4
+ storesp 12
+ storesp 4
+ poppc
+
+ .data
+ .balign 4,0
+_mask:
+ .long 0x00ffffff
+ .long 0xff00ffff
+ .long 0xffff00ff
+ .long 0xffffff00
+
+
+ .globl _hardware
+_hardware:
+ .long 0
+ .globl _cpu_config
+_cpu_config:
+ .long 0
+
diff --git a/zpu/sw/startup/crt_io.c b/zpu/sw/startup/crt_io.c
new file mode 100644
index 0000000..966ae33
--- /dev/null
+++ b/zpu/sw/startup/crt_io.c
@@ -0,0 +1,91 @@
+#include <syscall.h>
+#include <stdio.h>
+#include <errno.h>
+#include <sys/stat.h>
+
+extern int _hardware;
+/* _cpu_config==0 => Abel
+ * _cpu_config==1 => Zeta
+ * _cpu_config==2 => Phi
+ */
+extern int _cpu_config;
+static volatile int *UART;
+static volatile int *TIMER;
+volatile int *MHZ;
+
+
+
+/*
+ * Wait indefinitely for input byte
+ */
+
+
+int __attribute__ ((weak)) inbyte()
+{
+ int val;
+ for (;;)
+ {
+ val=UART[1];
+ if ((val&0x100)!=0)
+ {
+ return val&0xff;
+ }
+ }
+}
+
+
+
+/*
+ * Output one character to the serial port
+ *
+ *
+ */
+void __attribute__ ((weak)) outbyte(int c)
+{
+ /* Wait for space in FIFO */
+ while ((UART[0]&0x100)==0);
+ UART[0]=c;
+}
+
+static const int mhz=64;
+
+void __attribute__ ((weak)) _initIO(void)
+{
+ if (_hardware)
+ {
+ if (_cpu_config==2)
+ {
+ /* Phi board addresses */
+ UART=(volatile int *)0x080a000c;
+ TIMER=(volatile int *)0x080a0014;
+ MHZ=(volatile int *)&mhz;
+ } else
+ {
+ /* Abel board */
+ UART=(volatile int *)0xc000;
+ TIMER=(volatile int *)0x9000;
+ MHZ=(volatile int *)0x8800;
+ }
+ } else
+ {
+ UART=(volatile int *)0x80000024;
+ TIMER=(volatile int *)0x80000100;
+ MHZ=(volatile int *)0x80000200;
+ }
+}
+
+
+
+long long __attribute__ ((weak)) _readCycles()
+{
+ long long clock;
+ unsigned int i;
+
+ TIMER[0]=0x2; /* sample timer */
+ clock=0;
+ for (i=0; i<2; i++)
+ {
+ clock|=((long long )(TIMER[i]))<<(i*32);
+ }
+ return clock;
+}
diff --git a/zpu/sw/startup/nextgen_crt0.S b/zpu/sw/startup/nextgen_crt0.S
new file mode 100644
index 0000000..3cf9112
--- /dev/null
+++ b/zpu/sw/startup/nextgen_crt0.S
@@ -0,0 +1,894 @@
+/* Startup code for ZPU
+ Copyright (C) 2005 Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file with other programs, and to distribute
+those programs without any restriction coming from the use of this
+file. (The General Public License restrictions do apply in other
+respects; for example, they cover modification of the file, and
+distribution when not linked into another program.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING. If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA. */
+ .file "crt0.S"
+
+ .section ".fixed_vectors","ax"
+
+
+
+
+ .macro fast_neg
+ not
+ im 1
+ add
+ .endm
+
+ .macro cimpl funcname
+ ; save R0
+ im 0
+ load
+
+ ; save R1
+ im 4
+ load
+
+ ; save R2
+ im 8
+ load
+
+ loadsp 20
+ loadsp 20
+
+ fixedim \funcname
+ call
+
+ ; destroy arguments on stack
+ storesp 0
+ storesp 0
+
+ im 0
+ load
+
+ ; poke the result into the right slot
+ storesp 24
+
+ ; restore R2
+ im 8
+ store
+
+ ; restore R1
+ im 4
+ store
+
+ ; restore r0
+ im 0
+ store
+
+ storesp 4
+ poppc
+ .endm
+
+
+
+
+/* vectors */
+ .balign 32,0
+# offset 0x0000 0000
+ .globl _start
+_start:
+ im _premain
+ poppc
+
+ .balign 16,0
+# offset 0x0000 0010
+ .globl _zpu_unknown_instruction_vector
+_zpu_unknown_instruction:
+ /* We have unsupported instruction * 4 on stack */
+ im _emulate_table
+ add
+ load
+ poppc
+
+ .rodata
+ .balign 4,0
+_emulate_table:
+ .long _storeh
+ .long ...
+
+/* instruction emulation code */
+
+# opcode 34
+# offset 0x0000 0040
+ .balign 32,0
+_loadh:
+ loadsp 4
+ ; by not masking out bit 0, we cause a memory access error
+ ; on unaligned access
+ im ~0x2
+ and
+ load
+
+ ; mult 8
+ loadsp 8
+ im 3
+ and
+ fast_neg
+ im 2
+ add
+ im 3
+ ashiftleft
+ ; shift right addr&3 * 8
+ lshiftright
+ im 0xffff
+ and
+ storesp 8
+
+ poppc
+
+# opcode 35
+# offset 0x0000 0060
+ .balign 32,0
+_storeh:
+ loadsp 4
+ ; by not masking out bit 0, we cause a memory access error
+ ; on unaligned access
+ im ~0x2
+ and
+ load
+
+ ; mask
+ im 0xffff
+ loadsp 12
+ im 3
+ and
+ fast_neg
+ im 2
+ add
+ im 3
+ ashiftleft
+ ashiftleft
+ not
+
+ and
+
+ loadsp 12
+ im 0xffff
+
+ nop
+
+ fixedim _storehtail
+ poppc
+
+
+# opcode 36
+# offset 0x0000 0080
+ .balign 32,0
+_lessthan:
+ loadsp 8
+ fast_neg
+ loadsp 8
+ add
+
+ ; DANGER!!!!
+ ; 0x80000000 will overflow when negated, so we need to mask
+ ; the result above with the compare positive to negative
+ ; number case
+ loadsp 12
+ loadsp 12
+ not
+ and
+ not
+ and
+
+
+ ; handle case where we are comparing a negative number
+ ; and positve number. This can underflow. E.g. consider 0x8000000 < 0x1000
+ loadsp 12
+ not
+ loadsp 12
+ and
+
+ or
+
+
+
+ flip
+ im 1
+ and
+
+
+ storesp 12
+ storesp 4
+ poppc
+
+
+# opcode 37
+# offset 0x0000 00a0
+ .balign 32,0
+_lessthanorequal:
+ loadsp 8
+ loadsp 8
+ lessthan
+ loadsp 12
+ loadsp 12
+ eq
+ or
+
+ storesp 12
+ storesp 4
+ poppc
+
+
+# opcode 38
+# offset 0x0000 00c0
+ .balign 32,0
+_ulessthan:
+ ; fish up arguments
+ loadsp 4
+ loadsp 12
+
+ /* low: -1 if low bit dif is negative 0 otherwise: neg (not x&1 and (y&1))
+ x&1 y&1 neg (not x&1 and (y&1))
+ 1 1 0
+ 1 0 0
+ 0 1 -1
+ 0 0 0
+
+ */
+ loadsp 4
+ not
+ loadsp 4
+ and
+ im 1
+ and
+ neg
+
+
+ /* high: upper 31-bit diff is only wrong when diff is 0 and low=-1
+ high=x>>1 - y>>1 + low
+
+ extremes
+
+ 0000 - 1111:
+ low= neg(not 0 and 1) = 1111 (-1)
+ high=000+ neg(111) +low = 000 + 1001 + low = 1000
+ OK
+
+ 1111 - 0000
+ low=neg(not 1 and 0) = 0
+ high=111+neg(000) + low = 0111
+ OK
+
+
+ */
+ loadsp 8
+
+ flip
+ addsp 0
+ flip
+
+ loadsp 8
+
+ flip
+ addsp 0
+ flip
+
+ sub
+
+ ; if they are equal, then the last bit decides...
+ add
+
+ /* test if negative: result = flip(diff) & 1 */
+ flip
+ im 1
+ and
+
+ ; destroy a&b which are on stack
+ storesp 4
+ storesp 4
+
+ storesp 12
+ storesp 4
+ poppc
+
+# opcode 39
+# offset 0x0000 00e0
+ .balign 32,0
+_ulessthanorequal:
+ loadsp 8
+ loadsp 8
+ ulessthan
+ loadsp 12
+ loadsp 12
+ eq
+ or
+
+ storesp 12
+ storesp 4
+ poppc
+
+
+# opcode 40
+# offset 0x0000 0100
+ .balign 32,0
+ .globl _swap
+_swap:
+ breakpoint ; tbd
+
+# opcode 41
+# offset 0x0000 0120
+ .balign 32,0
+_slowmult:
+ im _slowmultImpl
+ poppc
+
+# opcode 42
+# offset 0x0000 0140
+ .balign 32,0
+_lshiftright:
+ loadsp 8
+ flip
+
+ loadsp 8
+ ashiftleft
+ flip
+
+ storesp 12
+ storesp 4
+
+ poppc
+
+
+# opcode 43
+# offset 0x0000 0160
+ .balign 32,0
+_ashiftleft:
+ loadsp 8
+
+ loadsp 8
+ im 0x1f
+ and
+ fast_neg
+ im _ashiftleftEnd
+ add
+ poppc
+
+
+
+# opcode 44
+# offset 0x0000 0180
+ .balign 32,0
+_ashiftright:
+ loadsp 8
+ loadsp 8
+ lshiftright
+
+ ; handle signed value
+ im -1
+ loadsp 12
+ im 0x1f
+ and
+ lshiftright
+ not ; now we have an integer on the stack with the signed
+ ; bits in the right position
+
+ ; mask these bits with the signed bit.
+ loadsp 16
+ not
+ flip
+ im 1
+ and
+ im -1
+ add
+
+ and
+
+ ; stuff in the signed bits...
+ or
+
+ ; store result into correct stack slot
+ storesp 12
+
+ ; move up return value
+ storesp 4
+ poppc
+
+# opcode 45
+# offset 0x0000 01a0
+ .balign 32,0
+_call:
+ ; fn
+ loadsp 4
+
+ ; return address
+ loadsp 4
+
+ ; store return address
+ storesp 12
+
+ ; fn to call
+ storesp 4
+
+ pushsp ; flush internal stack
+ popsp
+
+ poppc
+
+_storehtail:
+
+ and
+ loadsp 12
+ im 3
+ and
+ fast_neg
+ im 2
+ add
+ im 3
+ ashiftleft
+ nop
+ ashiftleft
+
+ or
+
+ loadsp 8
+ im ~0x3
+ and
+
+ store
+
+ storesp 4
+ storesp 4
+ poppc
+
+
+# opcode 46
+# offset 0x0000 01c0
+ .balign 32,0
+_eq:
+ loadsp 8
+ fast_neg
+ loadsp 8
+ add
+
+ not
+ loadsp 0
+ im 1
+ add
+ not
+ and
+ flip
+ im 1
+ and
+
+ storesp 12
+ storesp 4
+ poppc
+
+# opcode 47
+# offset 0x0000 01e0
+ .balign 32,0
+_neq:
+ loadsp 8
+ fast_neg
+ loadsp 8
+ add
+
+ not
+ loadsp 0
+ im 1
+ add
+ not
+ and
+ flip
+
+ not
+
+ im 1
+ and
+
+ storesp 12
+ storesp 4
+ poppc
+
+
+# opcode 48
+# offset 0x0000 0200
+ .balign 32,0
+_neg:
+ loadsp 4
+ not
+ im 1
+ add
+ storesp 8
+
+ poppc
+
+
+# opcode 49
+# offset 0x0000 0220
+ .balign 32,0
+_sub:
+ loadsp 8
+ loadsp 8
+ fast_neg
+ add
+ storesp 12
+
+ storesp 4
+
+ poppc
+
+
+# opcode 50
+# offset 0x0000 0240
+ .balign 32,0
+_xor:
+ loadsp 8
+ not
+ loadsp 8
+ and
+
+ loadsp 12
+ loadsp 12
+ not
+ and
+
+ or
+
+ storesp 12
+ storesp 4
+ poppc
+
+# opcode 51
+# offset 0x0000 0260
+ .balign 32,0
+_loadb:
+ loadsp 4
+ im ~0x3
+ and
+ load
+
+ loadsp 8
+ im 3
+ and
+ fast_neg
+ im 3
+ add
+ ; x8
+ addsp 0
+ addsp 0
+ addsp 0
+
+ lshiftright
+
+ im 0xff
+ and
+ storesp 8
+
+ poppc
+
+
+# opcode 52
+# offset 0x0000 0280
+ .balign 32,0
+_storeb:
+ loadsp 4
+ im ~0x3
+ and
+ load
+
+ ; mask away destination
+ im _mask
+ loadsp 12
+ im 3
+ and
+ addsp 0
+ addsp 0
+ add
+ load
+
+ and
+
+
+ im _storebtail
+ poppc
+
+# opcode 53
+# offset 0x0000 02a0
+ .balign 32,0
+_div:
+ cimpl __divsi3
+
+# opcode 54
+# offset 0x0000 02c0
+ .balign 32,0
+_mod:
+ cimpl __modsi3
+
+# opcode 55
+# offset 0x0000 02e0
+ .balign 32,0
+ .globl _eqbranch
+_eqbranch:
+ loadsp 8
+
+ ; eq
+
+ not
+ loadsp 0
+ im 1
+ add
+ not
+ and
+ flip
+ im 1
+ and
+
+ ; mask
+ im -1
+ add
+ loadsp 0
+ storesp 16
+
+ ; no branch address
+ loadsp 4
+
+ and
+
+ ; fetch boolean & neg mask
+ loadsp 12
+ not
+
+ ; calc address & mask for branch
+ loadsp 8
+ loadsp 16
+ add
+ ; subtract 1 to find PC of branch instruction
+ im -1
+ add
+
+ and
+
+ or
+
+ storesp 4
+ storesp 4
+ storesp 4
+ poppc
+
+
+# opcode 56
+# offset 0x0000 0300
+ .balign 32,0
+ .globl _neqbranch
+_neqbranch:
+ loadsp 8
+
+ ; neq
+
+ not
+ loadsp 0
+ im 1
+ add
+ not
+ and
+ flip
+
+ not
+
+ im 1
+ and
+
+ ; mask
+ im -1
+ add
+ loadsp 0
+ storesp 16
+
+ ; no branch address
+ loadsp 4
+
+ and
+
+ ; fetch boolean & neg mask
+ loadsp 12
+ not
+
+ ; calc address & mask for branch
+ loadsp 8
+ loadsp 16
+ add
+ ; find address of branch instruction
+ im -1
+ add
+
+ and
+
+ or
+
+ storesp 4
+ storesp 4
+ storesp 4
+ poppc
+
+# opcode 57
+# offset 0x0000 0320
+ .balign 32,0
+ .globl _poppcrel
+_poppcrel:
+ add
+ ; address of poppcrel
+ im -1
+ add
+ poppc
+
+# opcode 58
+# offset 0x0000 0340
+ .balign 32,0
+ .globl _config
+_config:
+ im 1
+ nop
+ im _hardware
+ store
+ storesp 4
+ poppc
+
+# opcode 59
+# offset 0x0000 0360
+ .balign 32,0
+_pushpc:
+ loadsp 4
+ im 1
+ add
+ storesp 8
+ poppc
+
+# opcode 60
+# offset 0x0000 0380
+ .balign 32,0
+_syscall_emulate:
+ .byte 0
+
+# opcode 61
+# offset 0x0000 03a0
+ .balign 32,0
+_pushspadd:
+ pushsp
+ im 4
+ add
+ loadsp 8
+ addsp 0
+ addsp 0
+ add
+ storesp 8
+
+ poppc
+
+# opcode 62
+# offset 0x0000 03c0
+ .balign 32,0
+_halfmult:
+ breakpoint
+
+# opcode 63
+# offset 0x0000 03e0
+ .balign 32,0
+_callpcrel:
+ loadsp 4
+ loadsp 4
+ add
+ im -1
+ add
+ loadsp 4
+
+ storesp 12 ; return address
+ storesp 4
+ pushsp ; this will flush the internal stack.
+ popsp
+ poppc
+
+ .text
+
+
+
+
+_ashiftleftBegin:
+ .rept 0x1f
+ addsp 0
+ .endr
+_ashiftleftEnd:
+ storesp 12
+ storesp 4
+ poppc
+
+_storebtail:
+ loadsp 12
+ im 0xff
+ and
+ loadsp 12
+ im 3
+ and
+
+ fast_neg
+ im 3
+ add
+ ; x8
+ addsp 0
+ addsp 0
+ addsp 0
+
+ ashiftleft
+
+ or
+
+ loadsp 8
+ im ~0x3
+ and
+
+ store
+
+ storesp 4
+ storesp 4
+ poppc
+
+
+
+
+; NB! this is not an EMULATE instruction. It is a varargs fn.
+ .globl _syscall
+_syscall:
+ syscall
+ poppc
+
+_slowmultImpl:
+
+ loadsp 8 ; A
+ loadsp 8 ; B
+ im 0 ; C
+
+.LmoreMult:
+ mult1bit
+
+ ; cutoff
+ loadsp 8
+ .byte (.LmoreMult-.Lbranch)&0x7f+0x80
+.Lbranch:
+ neqbranch
+
+ storesp 4
+ storesp 4
+ storesp 12
+ storesp 4
+ poppc
+
+ .data
+ .balign 4,0
+_mask:
+ .long 0x00ffffff
+ .long 0xff00ffff
+ .long 0xffff00ff
+ .long 0xffffff00
+
+
+ .globl _hardware
+_hardware:
+ .long 0
+ .globl _cpu_config
+_cpu_config:
+ .long 0
+
+; Pointers to emulated instructions
diff --git a/zpu/sw/startup/time.c b/zpu/sw/startup/time.c
new file mode 100644
index 0000000..767b62f
--- /dev/null
+++ b/zpu/sw/startup/time.c
@@ -0,0 +1,32 @@
+#include <_ansi.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+
+extern long long _readCycles();
+
+
+extern volatile int *MHZ;
+
+long long _readMicroseconds()
+{
+ int Hz;
+ long long clock;
+ Hz=(*MHZ&0xff);
+ clock=_readCycles();
+ return clock/(long long)Hz;
+}
+
+
+
+
+time_t
+time (time_t *tloc)
+{
+ time_t t;
+ t=(time_t)(_readMicroseconds()/(long long )1000000);
+ if (tloc!=NULL)
+ {
+ *tloc=t;
+ }
+ return t;
+}
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