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-rw-r--r--zpu/sw/ecos/repository/hal/zylin/arch/current/include/arch.inc79
-rw-r--r--zpu/sw/ecos/repository/hal/zylin/arch/current/include/basetype.h83
-rw-r--r--zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_arch.h255
-rw-r--r--zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_intr.h261
-rw-r--r--zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_io.h305
5 files changed, 983 insertions, 0 deletions
diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/include/arch.inc b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/arch.inc
new file mode 100644
index 0000000..a30819e
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/arch.inc
@@ -0,0 +1,79 @@
+##=============================================================================
+##
+## arch.inc
+##
+## ZYLIN architecture assembler header file
+##
+##=============================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+##=============================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s): jskov
+## Contributors:jskov
+## Date: 2000-11-15
+## Purpose: ZYLIN definitions.
+## Description: This file contains various definitions and macros that are
+## useful for writing assembly code for the ZYLIN
+## It also includes the variant/platform assembly header file.
+## Usage:
+## #include <cyg/hal/arch.inc>
+## ...
+##
+##
+######DESCRIPTIONEND####
+##
+##=============================================================================
+
+#include <cyg/hal/basetype.h>
+
+##-----------------------------------------------------------------------------
+## ZYLIN entry definitions. This allows _ prefixing to change by modifying
+## the CYG_LABEL_DEFN macro.
+
+#define FUNC_START(name) \
+ .type CYG_LABEL_DEFN(name),@function; \
+ .globl CYG_LABEL_DEFN(name); \
+CYG_LABEL_DEFN(name):
+
+#define FUNC_END(name) \
+ .globl CYG_LABEL_DEFN(name); \
+CYG_LABEL_DEFN(name):
+
+#define SYM_DEF(name) \
+ .globl CYG_LABEL_DEFN(name); \
+CYG_LABEL_DEFN(name):
+
+#------------------------------------------------------------------------------
+# end of arch.inc
diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/include/basetype.h b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/basetype.h
new file mode 100644
index 0000000..6f2c2c7
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/basetype.h
@@ -0,0 +1,83 @@
+#ifndef CYGONCE_HAL_BASETYPE_H
+#define CYGONCE_HAL_BASETYPE_H
+
+//=============================================================================
+//
+// basetype.h
+//
+// Standard types for this architecture.
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): nickg, gthomas
+// Contributors: nickg, gthomas
+// Date: 1998-09-11
+// Purpose: Define architecture base types.
+// Usage: Included by "cyg_type.h", do not use directly
+
+//
+//####DESCRIPTIONEND####
+//
+
+//-----------------------------------------------------------------------------
+// Characterize the architecture
+
+#define CYG_BYTEORDER CYG_MSBFIRST // Big endian
+#define CYG_DOUBLE_BYTEORDER CYG_MSBFIRST // Big? endian
+
+//-----------------------------------------------------------------------------
+// ZYLIN does not usually use labels with underscores.
+
+#define CYG_LABEL_NAME(_name_) _name_
+#define CYG_LABEL_DEFN(_name_) _name_
+
+//-----------------------------------------------------------------------------
+// Override the alignment definitions from cyg_type.h. ZYLIN only allows 4
+// byte alignment whereas the default is 8 byte.
+
+#define CYGARC_ALIGNMENT 4
+#define CYGARC_P2ALIGNMENT 2
+
+//-----------------------------------------------------------------------------
+// Define the standard variable sizes
+
+// The ZYLIN architecture uses the default definitions of the base types,
+// so we do not need to define any here.
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_BASETYPE_H
+// End of basetype.h
diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_arch.h b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_arch.h
new file mode 100644
index 0000000..cd61277
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_arch.h
@@ -0,0 +1,255 @@
+#ifndef CYGONCE_HAL_ARCH_H
+#define CYGONCE_HAL_ARCH_H
+
+//==========================================================================
+//
+// hal_arch.h
+//
+// Architecture specific abstractions
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): nickg, gthomas
+// Contributors: nickg, gthomas
+// Date: 1999-02-20
+// Purpose: Define architecture abstractions
+// Usage: #include <cyg/hal/hal_arch.h>
+
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h> // To decide on stack usage
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/plf_io.h>
+#ifdef CYGBLD_HAL_ZYLIN_PLF_ARCH_H
+#include <cyg/hal/plf_arch.h>
+#endif
+
+#ifdef CYGBLD_HAL_ZYLIN_VAR_ARCH_H
+#include <cyg/hal/var_arch.h>
+#endif
+
+
+// It seems that r0-r3,r12 are considered scratch by function calls
+
+typedef struct
+{
+ cyg_uint32 reg[8];
+ cyg_uint32 interrupt;
+ cyg_uint32 pc; // must be last...
+} HAL_SavedRegisters;
+
+//-------------------------------------------------------------------------
+// Exception handling function.
+// This function is defined by the kernel according to this prototype. It is
+// invoked from the HAL to deal with any CPU exceptions that the HAL does
+// not want to deal with itself. It usually invokes the kernel's exception
+// delivery mechanism.
+
+externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data );
+
+//-------------------------------------------------------------------------
+// Bit manipulation macros
+
+externC int hal_lsbindex(int);
+externC int hal_msbindex(int);
+
+#define HAL_LSBIT_INDEX(index, mask) index = hal_lsbindex(mask)
+#define HAL_MSBIT_INDEX(index, mask) index = hal_msbindex(mask)
+
+//-------------------------------------------------------------------------
+// Context Initialization
+// Initialize the context of a thread.
+// Arguments:
+// _sparg_ name of variable containing current sp, will be changed to new sp
+// _thread_ thread object address, passed as argument to entry point
+// _entry_ entry point address.
+// _id_ bit pattern used in initializing registers, for debugging.
+
+#define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ ) \
+ CYG_MACRO_START \
+ cyg_uint32 *_sp_=(cyg_uint32 *)(((CYG_WORD)_sparg_) &~3); \
+ *--_sp_=(CYG_ADDRWORD)_thread_; \
+ *--_sp_=(CYG_ADDRWORD)0xffffffff; /* dummy return address */ \
+ *--_sp_=(cyg_uint32)(_entry_); /* PC = [initial] entry point */ \
+ *--_sp_= 0; /* interrupt mask */ \
+ *--_sp_= (_id_)|7; \
+ *--_sp_= (_id_)|6; \
+ *--_sp_= (_id_)|5; \
+ *--_sp_= (_id_)|4; \
+ *--_sp_= (_id_)|3; \
+ *--_sp_= (_id_)|2; \
+ *--_sp_= (_id_)|1; \
+ *--_sp_=(_id_)|0; \
+ _sparg_ = (CYG_ADDRWORD)_sp_; \
+ CYG_MACRO_END
+
+//--------------------------------------------------------------------------
+// Context switch macros.
+// The arguments are pointers to locations where the stack pointer
+// of the current thread is to be stored, and from where the sp of the
+// next thread is to be fetched.
+
+externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from );
+externC void hal_thread_load_context( CYG_ADDRESS to )
+ __attribute__ ((noreturn));
+
+#define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_) \
+ hal_thread_switch_context((CYG_ADDRESS)_tspptr_, \
+ (CYG_ADDRESS)_fspptr_);
+
+#define HAL_THREAD_LOAD_CONTEXT(_tspptr_) \
+ hal_thread_load_context( (CYG_ADDRESS)_tspptr_ );
+
+//--------------------------------------------------------------------------
+// Execution reorder barrier.
+// When optimizing the compiler can reorder code. In multithreaded systems
+// where the order of actions is vital, this can sometimes cause problems.
+// This macro may be inserted into places where reordering should not happen.
+
+#define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" )
+
+//--------------------------------------------------------------------------
+// Breakpoint support
+// HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to happen
+// if executed.
+// HAL_BREAKINST is the value of the breakpoint instruction and
+// HAL_BREAKINST_SIZE is its size in bytes.
+
+#define _stringify1(__arg) #__arg
+#define _stringify(__arg) _stringify1(__arg)
+
+#define HAL_BREAKINST_ZYLIN 0
+#define HAL_BREAKINST_ZYLIN_SIZE 1
+
+
+#define HAL_BREAKPOINT(_label_) \
+asm volatile (" .globl " #_label_ ";" \
+ #_label_":" \
+ " .byte " _stringify(HAL_BREAKINST_ZYLIN) \
+ );
+
+//#define HAL_BREAKINST {0xFE, 0xDE, 0xFF, 0xE7}
+#define HAL_BREAKINST HAL_BREAKINST_ZYLIN
+#define HAL_BREAKINST_SIZE HAL_BREAKINST_ZYLIN_SIZE
+#define HAL_BREAKINST_TYPE cyg_uint8
+
+extern cyg_uint32 __zylin_breakinst;
+#define HAL_BREAKINST_ADDR(x) (void*)&__zylin_breakinst)
+
+
+// Translate a stack pointer as saved by the thread context macros above into
+// a pointer to a HAL_SavedRegisters structure.
+#define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \
+ (_regs_) = (HAL_SavedRegisters *)(_sp_)
+
+
+
+//--------------------------------------------------------------------------
+// HAL setjmp
+
+#define CYGARC_JMP_BUF_SIZE 16 // Actually 11, but some room left over
+
+typedef cyg_uint32 hal_jmp_buf[CYGARC_JMP_BUF_SIZE];
+
+externC int hal_setjmp(hal_jmp_buf env);
+externC void hal_longjmp(hal_jmp_buf env, int val);
+
+
+//--------------------------------------------------------------------------
+// Idle thread code.
+// This macro is called in the idle thread loop, and gives the HAL the
+// chance to insert code. Typical idle thread behaviour might be to halt the
+// processor. Here we only supply a default fallback if the variant/platform
+// doesn't define anything.
+
+#ifndef HAL_IDLE_THREAD_ACTION
+#define HAL_IDLE_THREAD_ACTION(_count_) CYG_EMPTY_STATEMENT
+#endif
+
+//---------------------------------------------------------------------------
+
+// Minimal and sensible stack sizes: the intention is that applications
+// will use these to provide a stack size in the first instance prior to
+// proper analysis. Idle thread stack should be this big.
+
+// THESE ARE NOT INTENDED TO BE MICROMETRICALLY ACCURATE FIGURES.
+// THEY ARE HOWEVER ENOUGH TO START PROGRAMMING.
+// YOU MUST MAKE YOUR STACKS LARGER IF YOU HAVE LARGE "AUTO" VARIABLES!
+
+// This is not a config option because it should not be adjusted except
+// under "enough rope" sort of disclaimers.
+
+// A minimal, optimized stack frame, rounded up - no autos
+#define CYGNUM_HAL_STACK_FRAME_SIZE (4 * 80)
+
+// Stack needed for a context switch: this is implicit in the estimate for
+// interrupts so not explicitly used below:
+#define CYGNUM_HAL_STACK_CONTEXT_SIZE (4 * 80)
+
+// Interrupt + call to ISR, interrupt_end() and the DSR
+#define CYGNUM_HAL_STACK_INTERRUPT_SIZE \
+ ((4 * 80) + 2 * CYGNUM_HAL_STACK_FRAME_SIZE)
+
+// Space for the maximum number of nested interrupts, plus room to call functions
+#define CYGNUM_HAL_MAX_INTERRUPT_NESTING 16
+
+#if 0
+#define CYGNUM_HAL_STACK_SIZE_MINIMUM
+ (CYGNUM_HAL_MAX_INTERRUPT_NESTING * CYGNUM_HAL_STACK_INTERRUPT_SIZE + \
+ 2 * CYGNUM_HAL_STACK_FRAME_SIZE)
+
+#define CYGNUM_HAL_STACK_SIZE_TYPICAL \
+ (CYGNUM_HAL_STACK_SIZE_MINIMUM + \
+ 16 * CYGNUM_HAL_STACK_FRAME_SIZE)
+#else
+#define CYGNUM_HAL_STACK_SIZE_MINIMUM 16384 // KLUDGE!!! until interrupt stacks can be added
+
+#define CYGNUM_HAL_STACK_SIZE_TYPICAL 32768 // KLUDGE!!! until interrupt stacks can be added
+
+#endif
+
+//--------------------------------------------------------------------------
+// Macros for switching context between two eCos instances (jump from
+// code in ROM to code in RAM or vice versa).
+#define CYGARC_HAL_SAVE_GP()
+#define CYGARC_HAL_RESTORE_GP()
+
+#endif // CYGONCE_HAL_ARCH_H
+// End of hal_arch.h
diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_intr.h b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_intr.h
new file mode 100644
index 0000000..6ec6070
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_intr.h
@@ -0,0 +1,261 @@
+#ifndef CYGONCE_HAL_INTR_H
+#define CYGONCE_HAL_INTR_H
+
+//==========================================================================
+//
+// hal_intr.h
+//
+// HAL Interrupt and clock support
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): nickg, gthomas
+// Contributors: nickg, gthomas,
+// jlzylinour
+// Date: 1999-02-20
+// Purpose: Define Interrupt support
+// Description: The macros defined here provide the HAL APIs for handling
+// interrupts and the clock.
+//
+// Usage: #include <cyg/hal/hal_intr.h>
+// ...
+//
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>
+
+// This is to allow a variant to decide that there is no platform-specific
+// interrupts file; and that in turn can be overridden by a platform that
+// refines the variant's ideas.
+#ifdef CYGBLD_HAL_PLF_INTS_H
+# include CYGBLD_HAL_PLF_INTS_H // should include variant data as required
+#else
+# ifdef CYGBLD_HAL_VAR_INTS_H
+# include CYGBLD_HAL_VAR_INTS_H
+# else
+# include <cyg/hal/hal_platform_ints.h> // default less-complex platforms
+# endif
+#endif
+
+// Spurious interrupt (no interrupt source could be found)
+#define CYGNUM_HAL_INTERRUPT_NONE -1
+
+//--------------------------------------------------------------------------
+// ZYLIN exception vectors.
+
+// These vectors correspond to VSRs. These values are the ones to use for
+// HAL_VSR_GET/SET
+
+#define CYGNUM_HAL_VECTOR_RESET 0
+#define CYGNUM_HAL_VECTOR_UNDEF_INSTRUCTION 1
+#define CYGNUM_HAL_VECTOR_MISC 2
+#define CYGNUM_HAL_VECTOR_IRQ 3
+#define CYGNUM_HAL_VECTOR_MEMORY 4
+
+#define CYGNUM_HAL_VSR_MIN 0
+#define CYGNUM_HAL_VSR_MAX 4
+#define CYGNUM_HAL_VSR_COUNT 5
+
+// Exception vectors. These are the values used when passed out to an
+// external exception handler using cyg_hal_deliver_exception()
+
+#define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION \
+ CYGNUM_HAL_VECTOR_UNDEF_INSTRUCTION
+#define CYGNUM_HAL_EXCEPTION_INTERRUPT \
+ CYGNUM_HAL_VECTOR_SOFTWARE_INTERRUPT
+#define CYGNUM_HAL_EXCEPTION_CODE_ACCESS CYGNUM_HAL_VECTOR_MEMORY
+#define CYGNUM_HAL_EXCEPTION_DATA_ACCESS CYGNUM_HAL_VECTOR_MEMORY
+
+#define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_VSR_MIN
+#define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_VSR_MAX
+#define CYGNUM_HAL_EXCEPTION_COUNT (CYGNUM_HAL_EXCEPTION_MAX - \
+ CYGNUM_HAL_EXCEPTION_MIN + 1)
+
+//--------------------------------------------------------------------------
+// Static data used by HAL
+
+// ISR tables
+
+externC CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
+externC CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];
+externC CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];
+
+// VSR table
+externC CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_COUNT];
+
+//--------------------------------------------------------------------------
+// Default ISR
+// The #define is used to test whether this routine exists, and to allow
+// code outside the HAL to call it.
+
+externC cyg_uint32 hal_default_isr(cyg_uint32 vector, CYG_ADDRWORD data);
+
+#define HAL_DEFAULT_ISR hal_default_isr
+
+//--------------------------------------------------------------------------
+// Interrupt state storage
+
+typedef cyg_uint32 CYG_INTERRUPT_STATE;
+
+//--------------------------------------------------------------------------
+// Interrupt control macros
+
+externC cyg_uint32 zpu_disable_interrupts();
+externC void zpu_enable_interrupts();
+externC void zpu_restore_interrupts(cyg_uint32);
+externC cyg_uint32 zpu_query_interrupts();
+
+#define HAL_DISABLE_INTERRUPTS(_old_) {_old_=zpu_disable_interrupts();}
+#define HAL_ENABLE_INTERRUPTS() zpu_enable_interrupts()
+#define HAL_RESTORE_INTERRUPTS(_old_) { zpu_restore_interrupts(_old_); }
+#define HAL_QUERY_INTERRUPTS(_old_) { _old_=zpu_query_interrupts(); }
+
+
+//--------------------------------------------------------------------------
+// Vector translation.
+
+#ifndef HAL_TRANSLATE_VECTOR
+#define HAL_TRANSLATE_VECTOR(_vector_,_index_) \
+ (_index_) = (_vector_)
+#endif
+
+//--------------------------------------------------------------------------
+// Interrupt and VSR attachment macros
+
+#define HAL_INTERRUPT_IN_USE( _vector_, _state_) \
+ CYG_MACRO_START \
+ cyg_uint32 _index_; \
+ HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
+ \
+ if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr ) \
+ (_state_) = 0; \
+ else \
+ (_state_) = 1; \
+ CYG_MACRO_END
+
+#define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \
+ CYG_MACRO_START \
+ if( hal_interrupt_handlers[_vector_] == (CYG_ADDRESS)hal_default_isr ) \
+ { \
+ hal_interrupt_handlers[_vector_] = (CYG_ADDRESS)_isr_; \
+ hal_interrupt_data[_vector_] = (CYG_ADDRWORD) _data_; \
+ hal_interrupt_objects[_vector_] = (CYG_ADDRESS)_object_; \
+ } \
+ CYG_MACRO_END
+
+#define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \
+ CYG_MACRO_START \
+ if( hal_interrupt_handlers[_vector_] == (CYG_ADDRESS)_isr_ ) \
+ { \
+ hal_interrupt_handlers[_vector_] = (CYG_ADDRESS)hal_default_isr; \
+ hal_interrupt_data[_vector_] = 0; \
+ hal_interrupt_objects[_vector_] = 0; \
+ } \
+ CYG_MACRO_END
+
+#define HAL_VSR_GET( _vector_, _pvsr_ ) \
+ *(CYG_ADDRESS *)(_pvsr_) = hal_vsr_table[_vector_];
+
+
+#define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) \
+ CYG_MACRO_START \
+ if( _poldvsr_ != NULL ) \
+ *(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_]; \
+ hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_; \
+ CYG_MACRO_END
+
+//--------------------------------------------------------------------------
+// Interrupt controller access
+
+externC void hal_interrupt_mask(int);
+externC void hal_interrupt_unmask(int);
+externC void hal_interrupt_acknowledge(int);
+externC void hal_interrupt_configure(int, int, int);
+externC void hal_interrupt_set_level(int, int);
+
+#define HAL_INTERRUPT_MASK( _vector_ ) \
+ hal_interrupt_mask( _vector_ )
+#define HAL_INTERRUPT_UNMASK( _vector_ ) \
+ hal_interrupt_unmask( _vector_ )
+#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
+ hal_interrupt_acknowledge( _vector_ )
+#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \
+ hal_interrupt_configure( _vector_, _level_, _up_ )
+#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \
+ hal_interrupt_set_level( _vector_, _level_ )
+
+//--------------------------------------------------------------------------
+// Clock control
+
+externC void hal_clock_initialize(cyg_uint32);
+externC void hal_clock_read(cyg_uint32 *);
+externC void hal_clock_reset(cyg_uint32, cyg_uint32);
+
+#define HAL_CLOCK_INITIALIZE( _period_ ) hal_clock_initialize( _period_ )
+#define HAL_CLOCK_RESET( _vec_, _period_ ) hal_clock_reset( _vec_, _period_ )
+#define HAL_CLOCK_READ( _pvalue_ ) hal_clock_read( _pvalue_ )
+#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
+# ifndef HAL_CLOCK_LATENCY
+# define HAL_CLOCK_LATENCY( _pvalue_ ) HAL_CLOCK_READ( (cyg_uint32 *)_pvalue_ )
+# endif
+#endif
+
+
+#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
+externC void hal_interrupt_stack_call_pending_DSRs(void);
+#define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \
+ hal_interrupt_stack_call_pending_DSRs()
+
+// these are offered solely for stack usage testing
+// if they are not defined, then there is no interrupt stack.
+#define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base
+#define HAL_INTERRUPT_STACK_TOP cyg_interrupt_stack
+// use them to declare these extern however you want:
+// extern char HAL_INTERRUPT_STACK_BASE[];
+// extern char HAL_INTERRUPT_STACK_TOP[];
+// is recommended
+#endif
+
+
+//--------------------------------------------------------------------------
+#endif // ifndef CYGONCE_HAL_INTR_H
+// End of hal_intr.h
diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_io.h b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_io.h
new file mode 100644
index 0000000..64ad695
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_io.h
@@ -0,0 +1,305 @@
+#ifndef CYGONCE_HAL_IO_H
+#define CYGONCE_HAL_IO_H
+
+//=============================================================================
+//
+// hal_io.h
+//
+// HAL device IO register support.
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): nickg, gthomas
+// Contributors: Fabrice Gautier
+// Date: 1998-09-11
+// Purpose: Define IO register support
+// Description: The macros defined here provide the HAL APIs for handling
+// device IO control registers.
+//
+// Usage:
+// #include <cyg/hal/hal_io.h>
+// ...
+//
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/system.h>
+#include <cyg/infra/cyg_type.h>
+
+#include <cyg/hal/basetype.h>
+
+//-----------------------------------------------------------------------------
+// Include plf_io.h for platforms. Either via var_io.h or directly.
+#ifdef CYGBLD_HAL_ZYLIN_VAR_IO_H
+#include <cyg/hal/var_io.h>
+#else
+#include <cyg/hal/plf_io.h>
+#endif
+
+
+//-----------------------------------------------------------------------------
+// IO Register address.
+// This type is for recording the address of an IO register.
+
+typedef volatile CYG_ADDRWORD HAL_IO_REGISTER;
+
+//-----------------------------------------------------------------------------
+// HAL IO macros.
+#ifndef HAL_IO_MACROS_DEFINED
+
+//-----------------------------------------------------------------------------
+// BYTE Register access.
+// Individual and vectorized access to 8 bit registers.
+
+// Little-endian version or big-endian version that doesn't need address munging
+#if (CYG_BYTEORDER == CYG_LSBFIRST) || defined(HAL_IO_MACROS_NO_ADDRESS_MUNGING)
+
+#define HAL_READ_UINT8( _register_, _value_ ) \
+ ((_value_) = *((volatile CYG_BYTE *)(_register_)))
+
+#define HAL_WRITE_UINT8( _register_, _value_ ) \
+ (*((volatile CYG_BYTE *)(_register_)) = (_value_))
+
+#define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
+ CYG_MACRO_START \
+ cyg_count32 _i_,_j_; \
+ for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
+ (_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_j_]; \
+ CYG_MACRO_END
+
+#define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
+ CYG_MACRO_START \
+ cyg_count32 _i_,_j_; \
+ for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
+ ((volatile CYG_BYTE *)(_register_))[_j_] = (_buf_)[_i_]; \
+ CYG_MACRO_END
+
+#define HAL_READ_UINT8_STRING( _register_, _buf_, _count_ ) \
+ CYG_MACRO_START \
+ cyg_count32 _i_; \
+ for( _i_ = 0; _i_ < (_count_); _i_++) \
+ (_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_i_]; \
+ CYG_MACRO_END
+
+#define HAL_WRITE_UINT8_STRING( _register_, _buf_, _count_ ) \
+ CYG_MACRO_START \
+ cyg_count32 _i_; \
+ for( _i_ = 0; _i_ < (_count_); _i_++) \
+ ((volatile CYG_BYTE *)(_register_)) = (_buf_)[_i_]; \
+ CYG_MACRO_END
+
+#else // Big-endian version
+
+#define HAL_READ_UINT8( _register_, _value_ ) \
+ ((_value_) = *((volatile CYG_BYTE *)((CYG_ADDRWORD)(_register_)^3)))
+
+#define HAL_WRITE_UINT8( _register_, _value_ ) \
+ (*((volatile CYG_BYTE *)((CYG_ADDRWORD)(_register_)^3)) = (_value_))
+
+#define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
+ CYG_MACRO_START \
+ cyg_count32 _i_,_j_; \
+ volatile CYG_BYTE* _r_ = ((CYG_ADDRWORD)(_register_)^3); \
+ for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
+ (_buf_)[_i_] = _r_[_j_]; \
+ CYG_MACRO_END
+
+#define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
+ CYG_MACRO_START \
+ cyg_count32 _i_,_j_; \
+ volatile CYG_BYTE* _r_ = ((CYG_ADDRWORD)(_register_)^3); \
+ for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
+ _r_[_j_] = (_buf_)[_i_]; \
+ CYG_MACRO_END
+
+#define HAL_READ_UINT8_STRING( _register_, _buf_, _count_ ) \
+ CYG_MACRO_START \
+ cyg_count32 _i_; \
+ volatile CYG_BYTE* _r_ = ((CYG_ADDRWORD)(_register_)^3); \
+ for( _i_ = 0; _i_ < (_count_); _i_++; \
+ (_buf_)[_i_] = _r_[_i_]; \
+ CYG_MACRO_END
+
+#define HAL_WRITE_UINT8_STRING( _register_, _buf_, _count_ ) \
+ CYG_MACRO_START \
+ cyg_count32 _i_; \
+ volatile CYG_BYTE* _r_ = ((CYG_ADDRWORD)(_register_)^3); \
+ for( _i_ = 0; _i_ < (_count_); _i_++) \
+ _r_[_i_] = (_buf_)[_i_]; \
+ CYG_MACRO_END
+
+#endif // Big-endian
+
+//-----------------------------------------------------------------------------
+// 16 bit access.
+// Individual and vectorized access to 16 bit registers.
+
+// Little-endian version or big-endian version that doesn't need address munging
+#if (CYG_BYTEORDER == CYG_LSBFIRST) || defined(HAL_IO_MACROS_NO_ADDRESS_MUNGING)
+
+#define HAL_READ_UINT16( _register_, _value_ ) \
+ ((_value_) = *((volatile CYG_WORD16 *)(_register_)))
+
+#define HAL_WRITE_UINT16( _register_, _value_ ) \
+ (*((volatile CYG_WORD16 *)(_register_)) = (_value_))
+
+#define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
+ CYG_MACRO_START \
+ cyg_count32 _i_,_j_; \
+ for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
+ (_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_j_]; \
+ CYG_MACRO_END
+
+#define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
+ CYG_MACRO_START \
+ cyg_count32 _i_,_j_; \
+ for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
+ ((volatile CYG_WORD16 *)(_register_))[_j_] = (_buf_)[_i_]; \
+ CYG_MACRO_END
+
+#define HAL_READ_UINT16_STRING( _register_, _buf_, _count_) \
+ CYG_MACRO_START \
+ cyg_count32 _i_; \
+ for( _i_ = 0; _i_ < (_count_); _i_++) \
+ (_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_i_]; \
+ CYG_MACRO_END
+
+#define HAL_WRITE_UINT16_STRING( _register_, _buf_, _count_) \
+ CYG_MACRO_START \
+ cyg_count32 _i_; \
+ for( _i_ = 0; _i_ < (_count_); _i_++) \
+ ((volatile CYG_WORD16 *)(_register_))[_i_] = (_buf_)[_i_]; \
+ CYG_MACRO_END
+
+
+#else // Big-endian version
+
+#define HAL_READ_UINT16( _register_, _value_ ) \
+ ((_value_) = *((volatile CYG_WORD16 *)((CYG_ADDRWORD)(_register_)^3)))
+
+#define HAL_WRITE_UINT16( _register_, _value_ ) \
+ (*((volatile CYG_WORD16 *)((CYG_ADDRWORD)(_register_)^3)) = (_value_))
+
+#define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
+ CYG_MACRO_START \
+ cyg_count32 _i_,_j_; \
+ volatile CYG_WORD16* _r_ = ((CYG_ADDRWORD)(_register_)^3); \
+ for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
+ (_buf_)[_i_] = _r_[_j_]; \
+ CYG_MACRO_END
+
+#define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
+ CYG_MACRO_START \
+ cyg_count32 _i_,_j_; \
+ volatile CYG_WORD16* _r_ = ((CYG_ADDRWORD)(_register_)^3); \
+ for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
+ _r_[_j_] = (_buf_)[_i_]; \
+ CYG_MACRO_END
+
+#define HAL_READ_UINT16_STRING( _register_, _buf_, _count_) \
+ CYG_MACRO_START \
+ cyg_count32 _i_; \
+ volatile CYG_WORD16* _r_ = ((CYG_ADDRWORD)(_register_)^3); \
+ for( _i_ = 0 = 0; _i_ < (_count_); _i_++) \
+ (_buf_)[_i_] = _r_[_i_]; \
+ CYG_MACRO_END
+
+#define HAL_WRITE_UINT16_STRING( _register_, _buf_, _count_) \
+ CYG_MACRO_START \
+ cyg_count32 _i_; \
+ volatile CYG_WORD16* _r_ = ((CYG_ADDRWORD)(_register_)^3); \
+ for( _i_ = 0 = 0; _i_ < (_count_); _i_++) \
+ _r_[_i_] = (_buf_)[_i_]; \
+ CYG_MACRO_END
+
+
+#endif // Big-endian
+
+//-----------------------------------------------------------------------------
+// 32 bit access.
+// Individual and vectorized access to 32 bit registers.
+
+// Note: same macros for little- and big-endian systems.
+
+#define HAL_READ_UINT32( _register_, _value_ ) \
+ ((_value_) = *((volatile CYG_WORD32 *)(_register_)))
+
+#define HAL_WRITE_UINT32( _register_, _value_ ) \
+ (*((volatile CYG_WORD32 *)(_register_)) = (_value_))
+
+#define HAL_READ_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \
+ CYG_MACRO_START \
+ cyg_count32 _i_,_j_; \
+ for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
+ (_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_j_]; \
+ CYG_MACRO_END
+
+#define HAL_WRITE_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \
+ CYG_MACRO_START \
+ cyg_count32 _i_,_j_; \
+ for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
+ ((volatile CYG_WORD32 *)(_register_))[_j_] = (_buf_)[_i_]; \
+ CYG_MACRO_END
+
+#define HAL_READ_UINT32_STRING( _register_, _buf_, _count_) \
+ CYG_MACRO_START \
+ cyg_count32 _i_; \
+ for( _i_ = 0; _i_ < (_count_); _i_++) \
+ (_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_i_]; \
+ CYG_MACRO_END
+
+#define HAL_WRITE_UINT32_STRING( _register_, _buf_, _count_) \
+ CYG_MACRO_START \
+ cyg_count32 _i_; \
+ for( _i_ = 0; _i_ < (_count_); _i_++) \
+ ((volatile CYG_WORD32 *)(_register_))[_i_] = (_buf_)[_i_]; \
+ CYG_MACRO_END
+
+
+#define HAL_IO_MACROS_DEFINED
+
+#endif // !HAL_IO_MACROS_DEFINED
+
+// Enforce a flow "barrier" to prevent optimizing compiler from reordering
+// operations.
+#define HAL_IO_BARRIER()
+
+//-----------------------------------------------------------------------------
+#endif // ifndef CYGONCE_HAL_IO_H
+// End of hal_io.h
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