diff options
Diffstat (limited to 'zpu/hdl/zy2000/zpu_config_fast.vhd')
-rw-r--r-- | zpu/hdl/zy2000/zpu_config_fast.vhd | 40 |
1 files changed, 20 insertions, 20 deletions
diff --git a/zpu/hdl/zy2000/zpu_config_fast.vhd b/zpu/hdl/zy2000/zpu_config_fast.vhd index 61949c5..c0df294 100644 --- a/zpu/hdl/zy2000/zpu_config_fast.vhd +++ b/zpu/hdl/zy2000/zpu_config_fast.vhd @@ -1,20 +1,20 @@ -library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-
-package zpu_config is
- -- generate trace output or not.
- constant Generate_Trace : boolean := false;
- constant wordPower : integer := 5;
- -- during simulation, set this to '0' to get matching trace.txt
- constant DontCareValue : std_logic := '0';
- -- Clock frequency in MHz.
- constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"40";
- -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
- constant maxAddrBitIncIO : integer := 27;
-
- -- start byte address of stack.
- -- point to top of RAM - 2*words
- constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"1fffff8";
-
-end zpu_config;
+library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +package zpu_config is + -- generate trace output or not. + constant Generate_Trace : boolean := false; + constant wordPower : integer := 5; + -- during simulation, set this to '0' to get matching trace.txt + constant DontCareValue : std_logic := '0'; + -- Clock frequency in MHz. + constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"40"; + -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) + constant maxAddrBitIncIO : integer := 27; + + -- start byte address of stack. + -- point to top of RAM - 2*words + constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"1fffff8"; + +end zpu_config; |