diff options
Diffstat (limited to 'zpu/hdl/zpu4/src')
| -rw-r--r-- | zpu/hdl/zpu4/src/build.xml | 114 | ||||
| -rw-r--r-- | zpu/hdl/zpu4/src/ic300.bitgen | 27 | ||||
| -rw-r--r-- | zpu/hdl/zpu4/src/ic300.lso | 1 | ||||
| -rw-r--r-- | zpu/hdl/zpu4/src/ic300.ucf | 146 | ||||
| -rw-r--r-- | zpu/hdl/zpu4/src/ic300.vhd | 144 | ||||
| -rw-r--r-- | zpu/hdl/zpu4/src/ic300_config.vhd | 26 | ||||
| -rw-r--r-- | zpu/hdl/zpu4/src/ic300pkg.vhd | 88 | ||||
| -rw-r--r-- | zpu/hdl/zpu4/src/xmake.filelist | 12 | ||||
| -rw-r--r-- | zpu/hdl/zpu4/src/xmake.filelist.bramsmall | 5 | ||||
| -rw-r--r-- | zpu/hdl/zpu4/src/xmake.xst | 53 | ||||
| -rw-r--r-- | zpu/hdl/zpu4/src/zpuio_bram.vhd | 229 |
11 files changed, 0 insertions, 845 deletions
diff --git a/zpu/hdl/zpu4/src/build.xml b/zpu/hdl/zpu4/src/build.xml deleted file mode 100644 index e1b268a..0000000 --- a/zpu/hdl/zpu4/src/build.xml +++ /dev/null @@ -1,114 +0,0 @@ -<!-- - -FIX!!! start /b /wait /belownormal does not propagate return code.. ---> -<project name="ZPU3" default="all" basedir="."> - <property name="chipname" value="ic300"/> - <property name="packagetype" value="xc3s400-ft256-4"/> - - - <description>eCosBoard firmware build file</description> - - <target name="setuplibs"> - <!-- N/A yet - <copy todir="../src"> - <fileset dir="..\fpgalib\" includes="foo_top.ngc" /> - </copy> - --> - </target> - - <target name="setup"> - <mkdir dir="..\reports"/> - <mkdir dir="..\syn"/> - <mkdir dir="..\ngo"/> - <mkdir dir="..\output"/> - <mkdir dir="..\tmp"/> - <mkdir dir="..\xst"/> - </target> - - <target name="clean"> - <delete dir="..\reports"/> - <delete dir="..\syn"/> - <delete dir="..\ngo"/> - <delete dir="..\output"/> - <delete dir="..\tmp"/> - <delete dir="..\xst"/> - </target> - - <target name="synthesis" depends="setup"> - <exec executable="cmd" failonerror="true"> - <arg line="/c xst -intstyle ise -ifn xmake.xst -ofn ..\reports\1_synthesis.txt"/> - </exec> - </target> - - - <target name="translate" depends="setup"> - <exec executable="cmd" failonerror="true"> - <arg line="/c ngdbuild -intstyle ise -dd ..\ngo -uc ${chipname}.ucf -a -p ${packagetype} ..\syn\${chipname}.ngc ..\ngo\${chipname}.ngd"/> - </exec> - <move tofile="..\reports\2_translate.txt"> - <fileset dir="..\ngo" includes="${chipname}.bld"/> - </move> - </target> - - <target name="mapping" depends="setup"> - <exec executable="cmd" failonerror="true"> - <arg line="/c map -intstyle ise -p ${packagetype} -ol high -timing -detail -cm area -ignore_keep_hierarchy -pr b -k 6 -r -c 100 -tx off -o ..\ngo\${chipname}_map.ncd ..\ngo\${chipname}.ngd ..\ngo\${chipname}.pcf"/> - </exec> - <move tofile="..\reports\3_mapping.txt"> - <fileset dir="..\ngo" includes="${chipname}_map.mrp"/> - </move> - </target> - - - <target name="placeandroute" depends="setup"> - <exec executable="cmd" failonerror="true"> - <arg line="/c par -w -intstyle ise -ol high -t 1 ..\ngo\${chipname}_map.ncd ..\ngo\${chipname}.ncd ..\ngo\${chipname}.pcf"/> - </exec> - <move tofile="..\reports\4_placeandroute.txt"> - <fileset dir="..\ngo" includes="${chipname}.par"/> - </move> - <move tofile="..\reports\5_pads.txt"> - <fileset dir="..\ngo" includes="${chipname}_pad.txt"/> - </move> - </target> - - - <target name="gentime" depends="setup"> - <exec executable="cmd" failonerror="true"> - <arg line="/c trce -intstyle ise -v 3 -l 3 -a -u 100 ..\ngo\${chipname}.ncd -o ..\reports\timing.twr ..\ngo\${chipname}.pcf"/> - </exec> - <delete file="..\reports\6_timing.txt"/> - <move tofile="..\reports\6_timing.txt"> - <fileset dir="..\reports" includes="timing.twr"/> - </move> - </target> - - - <target name="genbit" depends="setup"> - <exec executable="cmd" failonerror="true"> - <arg line="/c bitgen -intstyle ise -w -f ${chipname}.bitgen ..\ngo\${chipname}.ncd"/> - </exec> - <move tofile="..\reports\7_bitgen.txt"> - <fileset dir="..\ngo" includes="${chipname}.bgn"/> - </move> - </target> - - <target name="copyfiles" depends="setup"> - <copy todir="../output"> - <fileset dir="..\ngo" includes="${chipname}.bin"/> - </copy> - <!-- - <copy tofile="${workspace_loc}\firmware\board\xeddvifpgadata.rawdata"> - <fileset dir="..\ngo" includes="${chipname}.bin"/> - </copy> - --> - </target> - - - <target name="all" depends="setuplibs,synthesis,translate,mapping,placeandroute,gentime,genbit,copyfiles"> - - </target> - - -</project>
\ No newline at end of file diff --git a/zpu/hdl/zpu4/src/ic300.bitgen b/zpu/hdl/zpu4/src/ic300.bitgen deleted file mode 100644 index 1095099..0000000 --- a/zpu/hdl/zpu4/src/ic300.bitgen +++ /dev/null @@ -1,27 +0,0 @@ --g DebugBitstream:No
--g Binary:yes
--g CRC:Enable
--g ConfigRate:50
--g CclkPin:Pullnone
--g M0Pin:Pullnone
--g M1Pin:Pullnone
--g M2Pin:Pullnone
--g ProgPin:PullUp
--g DonePin:Pullnone
--g TckPin:Pullnone
--g TdiPin:Pullnone
--g TdoPin:Pullnone
--g TmsPin:Pullnone
--g UnusedPin:Pullnone
--g UserID:0xFFFFFFFF
--g DCMShutDown:Disable
--g DCIUpdateMode:AsRequired
--g StartUpClk:CClk
--g DONE_cycle:4
--g GTS_cycle:5
--g GWE_cycle:6
--g LCK_cycle:NoWait
--g Security:Level1
--g DonePipe:No
--g DriveDone:Yes
-
diff --git a/zpu/hdl/zpu4/src/ic300.lso b/zpu/hdl/zpu4/src/ic300.lso deleted file mode 100644 index 22de730..0000000 --- a/zpu/hdl/zpu4/src/ic300.lso +++ /dev/null @@ -1 +0,0 @@ -work
diff --git a/zpu/hdl/zpu4/src/ic300.ucf b/zpu/hdl/zpu4/src/ic300.ucf deleted file mode 100644 index 4a141b9..0000000 --- a/zpu/hdl/zpu4/src/ic300.ucf +++ /dev/null @@ -1,146 +0,0 @@ -# clock inputs
-net "cpu_clk_p" loc = "R9" | iostandard=LVTTL;
-
-# input pins
-net "cpu_a_p(0)" loc = "N15" | iostandard=LVTTL;
-net "cpu_a_p(1)" loc = "P16" | iostandard=LVTTL;
-net "cpu_a_p(2)" loc = "P13" | iostandard=LVTTL;
-net "cpu_a_p(3)" loc = "N16" | iostandard=LVTTL;
-net "cpu_a_p(4)" loc = "P15" | iostandard=LVTTL;
-net "cpu_a_p(5)" loc = "R11" | iostandard=LVTTL;
-net "cpu_a_p(6)" loc = "T14" | iostandard=LVTTL;
-net "cpu_a_p(7)" loc = "R16" | iostandard=LVTTL;
-net "cpu_a_p(8)" loc = "P14" | iostandard=LVTTL;
-net "cpu_a_p(9)" loc = "T13" | iostandard=LVTTL;
-net "cpu_a_p(10)" loc = "R13" | iostandard=LVTTL;
-net "cpu_a_p(11)" loc = "P7" | iostandard=LVTTL;
-net "cpu_a_p(12)" loc = "N12" | iostandard=LVTTL;
-net "cpu_a_p(13)" loc = "R12" | iostandard=LVTTL;
-net "cpu_a_p(14)" loc = "L13" | iostandard=LVTTL;
-net "cpu_a_p(15)" loc = "K12" | iostandard=LVTTL;
-net "cpu_a_p(16)" loc = "K15" | iostandard=LVTTL;
-net "cpu_a_p(17)" loc = "T10" | iostandard=LVTTL;
-net "cpu_a_p(18)" loc = "T9" | iostandard=LVTTL;
-net "cpu_a_p(19)" loc = "N10" | iostandard=LVTTL;
-net "cpu_a_p(20)" loc = "T8" | iostandard=LVTTL;
-net "cpu_wr_n_p(0)" loc = "L15" | iostandard=LVTTL;
-net "cpu_wr_n_p(1)" loc = "N14" | iostandard=LVTTL;
-net "cpu_oe_n_p" loc = "T12" | iostandard=LVTTL;
-net "cpu_cs_n_p(1)" loc = "R3" | iostandard=LVTTL;
-net "cpu_cs_n_p(2)" loc = "M16" | iostandard=LVTTL;
-net "cpu_cs_n_p(3)" loc = "P11" | iostandard=LVTTL;
-
-#net "sdr_clk_fb_p" loc = "B8" | iostandard=SSTL2_I;
-
-# output pins
-net "cpu_fiq_p" loc = "K16" | iostandard=LVTTL;
-net "cpu_irq_p(0)" loc = "M14" | iostandard=LVTTL;
-net "cpu_irq_p(1)" loc = "J16" | iostandard=LVTTL;
-net "cpu_wait_n_p" loc = "M15" | iostandard=LVTTL;
-
-#net "sdr_clk_p" loc = "D8" | iostandard=SSTL2_I | FAST;
-#net "sdr_clk_n_p" loc = "F5" | iostandard=SSTL2_I | FAST;
-#net "cke_q_p" loc = "F4" | iostandard=SSTL2_I | FAST;
-#net "cs_qn_p" loc = "M2" | iostandard=SSTL2_I | FAST | PULLUP;
-#net "ras_qn_p" loc = "J2" | iostandard=SSTL2_I | FAST | PULLUP | NODELAY;
-#net "cas_qn_p" loc = "M3" | iostandard=SSTL2_I | FAST | PULLUP | NODELAY;
-#net "we_qn_p" loc = "K4" | iostandard=SSTL2_I | FAST | PULLUP | NODELAY;
-#net "dm_q_p(0)" loc = "L4" | iostandard=SSTL2_I | FAST;
-#net "dm_q_p(1)" loc = "E4" | iostandard=SSTL2_I | FAST;
-#net "dqs_q_p(0)" loc = "L3" | iostandard=SSTL2_I | FAST;
-#net "dqs_q_p(1)" loc = "D3" | iostandard=SSTL2_I | FAST;
-#net "ba_q_p(0)" loc = "M1" | iostandard=SSTL2_I | FAST;
-#net "ba_q_p(1)" loc = "J3" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(0)" loc = "J4" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(1)" loc = "N2" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(2)" loc = "H4" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(3)" loc = "P2" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(4)" loc = "E7" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(5)" loc = "G4" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(6)" loc = "D7" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(7)" loc = "G5" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(8)" loc = "C7" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(9)" loc = "F3" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(10)" loc = "N3" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(11)" loc = "E6" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(12)" loc = "D6" | iostandard=SSTL2_I | FAST;
-
-# bidirectional pins
-net "cpu_d_p(0)" loc = "M11" | iostandard=LVTTL;
-net "cpu_d_p(1)" loc = "N11" | iostandard=LVTTL;
-net "cpu_d_p(2)" loc = "P10" | iostandard=LVTTL;
-net "cpu_d_p(3)" loc = "R10" | iostandard=LVTTL;
-net "cpu_d_p(4)" loc = "T7" | iostandard=LVTTL;
-net "cpu_d_p(5)" loc = "R7" | iostandard=LVTTL;
-net "cpu_d_p(6)" loc = "N6" | iostandard=LVTTL;
-net "cpu_d_p(7)" loc = "M6" | iostandard=LVTTL;
-net "cpu_d_p(8)" loc = "K13" | iostandard=LVTTL;
-net "cpu_d_p(9)" loc = "M10" | iostandard=LVTTL;
-net "cpu_d_p(10)" loc = "L12" | iostandard=LVTTL;
-net "cpu_d_p(11)" loc = "M13" | iostandard=LVTTL;
-net "cpu_d_p(12)" loc = "K14" | iostandard=LVTTL;
-net "cpu_d_p(13)" loc = "L14" | iostandard=LVTTL;
-net "cpu_d_p(14)" loc = "J13" | iostandard=LVTTL;
-net "cpu_d_p(15)" loc = "J14" | iostandard=LVTTL;
-
-#net "sdr_d_p(0)" loc = "G1" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(1)" loc = "H3" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(2)" loc = "G3" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(3)" loc = "K2" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(4)" loc = "F2" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(5)" loc = "L2" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(6)" loc = "E1" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(7)" loc = "M4" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(8)" loc = "C6" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(9)" loc = "E2" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(10)" loc = "C2" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(11)" loc = "D1" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(12)" loc = "B7" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(13)" loc = "D2" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(14)" loc = "B6" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(15)" loc = "B5" | iostandard=SSTL2_I | NODELAY | FAST;
-
-# TIMING
-# Create timing names
-NET "cpu_clk_p" TNM_NET = "cpu_clk_p";
-NET "sdr_clk_fb_p" TNM_NET = "sdr_clk_fb_p";
-#NET "cpu_clk" TNM_NET = "cpu_clk";
-#NET "cpu_clk_2x" TNM_NET = "cpu_clk_2x";
-#NET "cpu_clk_4x" TNM_NET = "cpu_clk_4x";
-#NET "ddr_in_clk" TNM_NET = "ddr_in_clk";
-#NET "ddr_in_clk_2x" TNM_NET = "ddr_in_clk_2x";
-
-## Create timing
-
-# Periode timing
-TIMESPEC "TS_cpu_clk" = PERIOD "cpu_clk_p" 10 ns HIGH 50 %;
-#TIMESPEC "TS_sdr_clk_fb_p" = PERIOD "sdr_clk_fb_p" 7.8 ns HIGH 50 %;
-
-# Clock domain crossing timing
-#TIMESPEC "TS_cpu1_to_cpu2" = FROM "cpu_clk" TO "cpu_clk_2x" 7.8 ns;
-#TIMESPEC "TS_cpu1_to_cpu4" = FROM "cpu_clk" TO "cpu_clk_4x" 3.9 ns;
-#TIMESPEC "TS_cpu1_to_ddr2" = FROM "cpu_clk" TO "ddr_in_clk" 7.8 ns;
-#TIMESPEC "TS_cpu1_to_ddr2_2x" = FROM "cpu_clk" TO "ddr_in_clk_2x" 3.9 ns;
-
-#TIMESPEC "TS_cpu2_to_cpu1" = FROM "cpu_clk_2x" TO "cpu_clk" 7.8 ns;
-#TIMESPEC "TS_cpu2_to_cpu4" = FROM "cpu_clk_2x" TO "cpu_clk_4x" 3.9 ns;
-#TIMESPEC "TS_cpu2_to_ddr2" = FROM "cpu_clk_2x" TO "ddr_in_clk" 7.8 ns;
-#TIMESPEC "TS_cpu2_to_ddr_2x" = FROM "cpu_clk_2x" TO "ddr_in_clk_2x" 3.9 ns;
-
-#TIMESPEC "TS_cpu4_to_cpu1" = FROM "cpu_clk_4x" TO "cpu_clk" 3.9 ns;
-#TIMESPEC "TS_cpu4_to_cpu2" = FROM "cpu_clk_4x" TO "cpu_clk_2x" 3.9 ns;
-#TIMESPEC "TS_cpu4_to_ddr2" = FROM "cpu_clk_4x" TO "ddr_in_clk" 3.9 ns;
-#TIMESPEC "TS_cpu4_to_ddr2_2x" = FROM "cpu_clk_4x" TO "ddr_in_clk_2x" 3.9 ns;
-
-#TIMESPEC "TS_ddr2_to_cpu1" = FROM "ddr_in_clk" TO "cpu_clk" 7.8 ns;
-#TIMESPEC "TS_ddr2_to_cpu2" = FROM "ddr_in_clk" TO "cpu_clk_2x" 7.8 ns;
-#TIMESPEC "TS_ddr2_to_cpu4" = FROM "ddr_in_clk" TO "cpu_clk_4x" 3.9 ns;
-#TIMESPEC "TS_ddr2_to_ddr2_2x" = FROM "ddr_in_clk" TO "ddr_in_clk_2x" 3.9 ns;
-
-#TIMESPEC "TS_ddr2_2x_to_cpu1" = FROM "ddr_in_clk_2x" TO "cpu_clk" 3.9 ns;
-#TIMESPEC "TS_ddr2_2x_to_cpu2" = FROM "ddr_in_clk_2x" TO "cpu_clk_2x" 3.9 ns;
-#TIMESPEC "TS_ddr2_2x_to_cpu4" = FROM "ddr_in_clk_2x" TO "cpu_clk_4x" 3.9 ns;
-#TIMESPEC "TS_ddr2_2x_to_ddr2" = FROM "ddr_in_clk_2x" TO "ddr_in_clk" 3.9 ns;
-
-
-
diff --git a/zpu/hdl/zpu4/src/ic300.vhd b/zpu/hdl/zpu4/src/ic300.vhd deleted file mode 100644 index a1b4f41..0000000 --- a/zpu/hdl/zpu4/src/ic300.vhd +++ /dev/null @@ -1,144 +0,0 @@ ---------------------------------------------------------------------------------
--- Company: Zylin AS
--- Engineer: Tore Ramsland
---
--- Create Date: 21:47:41 07/03/05
--- Design Name: ic300
--- Module Name: ic300 - behave
--- Project Name: eCosBoard
--- Target Device: XC3S400400-FG256
--- Tool versions: 7.1i
--- Description: Top level
---
--- Dependencies:
---
--- Revision:
--- 2005-07-11 Updated to test FPGA
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library UNISIM;
-use UNISIM.VComponents.all;
-
-library zylin;
-use zylin.arm7.all;
-
-library zylin;
-use zylin.zpu_config.all;
-use zylin.zpupkg.all;
-
-library work;
-use work.phi_config.all;
-use work.ic300pkg.all;
-
-entity ic300 is
- generic(
- simulate_io_time : boolean := false);
- port ( -- Clock inputs
- cpu_clk_p : in std_logic;
-
- -- CPU interface signals
- cpu_a_p : in std_logic_vector(20 downto 0);
- cpu_wr_n_p : in std_logic_vector(1 downto 0);
- cpu_cs_n_p : in std_logic_vector(3 downto 1);
- cpu_oe_n_p : in std_logic;
- cpu_d_p : inout std_logic_vector(15 downto 0);
- cpu_irq_p : out std_logic_vector(1 downto 0);
- cpu_fiq_p : out std_logic;
- cpu_wait_n_p : out std_logic;
-
- -- DDR SDRAM Signals
- sdr_clk_p : out std_logic; -- ddr_sdram_clock
- sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock
- cke_q_p : out std_logic; -- clock enable
- cs_qn_p : out std_logic; -- /chip select
- ras_qn_p : inout std_logic; -- /ras
- cas_qn_p : inout std_logic; -- /cas
- we_qn_p : inout std_logic; -- /write enable
- dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00"
- dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write
- ba_q_p : out std_logic_vector(1 downto 0); -- bank select
- sdr_a_p : out std_logic_vector(12 downto 0); -- address bus
- sdr_d_p : inout std_logic_vector(15 downto 0); -- bidir data bus
- sdr_clk_fb_p : in std_logic -- DDR clock feedback
- );
-end ic300;
-
-architecture behave of ic300 is
-
-signal cpu_we : std_logic_vector(1 downto 0); -- Write signal for lower(0) and upper(1) 8 data bits
-signal cpu_re : std_logic; -- Read enable signal for all 16 bits
-signal areset : std_logic; -- Asyncronous active high reset (for initialization)
-signal areset_dummy : std_logic;
-
--- Clock module signals
-signal clk_status : std_logic_vector(2 downto 0); -- DLL lock status (from 3 DLL's)
-signal cpu_clk : std_logic; -- 64 MHz CPU clk
-signal cpu_clk_2x : std_logic; -- 128 MHz CPU clk (in phase with 64 MHz)
-signal cpu_clk_4x : std_logic; -- 256 MHz CPU clk (in phase with 64 MHz)
-signal ddr_in_clk : std_logic; -- 128 MHz clock from DDR SDRAM
-signal ddr_in_clk_2x : std_logic; -- 256 MHz clock from DDR SDRAM
- -- NOTE! Phase relation to 64 MHz clock unknown
-
--- Internal CPU interface signals
-signal cpu_din : std_logic_vector(15 downto 0); -- 16-bit data from CPU
-signal cpu_dout : std_logic_vector(15 downto 0); -- 16-bit data to CPU
-signal cpu_a : std_logic_vector(20 downto 0); -- 21-bit address from CPU
-
-begin
-
--- areset <= '0';
- areset_dummy <= '0';
-
- global_init_reset:
- rocbuf port map(I=>areset_dummy,O=>areset);
-
- allclocks:
- clocks port map(
- areset => areset,
- cpu_clk_p => cpu_clk_p,
- cpu_clk => cpu_clk,
- cpu_clk_2x => cpu_clk_2x,
- cpu_clk_4x => cpu_clk_4x,
- sdr_clk_fb_p => sdr_clk_fb_p,
- ddr_in_clk => ddr_in_clk,
- ddr_in_clk_2x => ddr_in_clk_2x,
- locked => clk_status);
-
- arm7cpu:
- arm7wb generic map (simulate_io_time => simulate_io_time)
- port map(
- areset => areset,
- cpu_clk => cpu_clk,
- cpu_clk_2x => cpu_clk_2x,
- cpu_a_p => cpu_a_p,
- cpu_wr_n_p => cpu_wr_n_p,
- cpu_cs_n_p => cpu_cs_n_p,
- cpu_oe_n_p => cpu_oe_n_p,
- cpu_d_p => cpu_d_p,
- cpu_irq_p => cpu_irq_p,
- cpu_fiq_p => cpu_fiq_p,
- cpu_wait_n_p => cpu_wait_n_p,
- cpu_din => cpu_din,
- cpu_a => cpu_a,
- cpu_we => cpu_we,
- cpu_re => cpu_re,
- cpu_dout => cpu_dout);
-
-
- cpu_fpga_regs:
- zpuio port map(
- areset => areset,
- cpu_clk => cpu_clk,
- clk_status => clk_status,
- cpu_din => cpu_din,
- cpu_a => cpu_a,
- cpu_we => cpu_we,
- cpu_re => cpu_re,
- cpu_dout => cpu_dout);
-
-
-end behave;
diff --git a/zpu/hdl/zpu4/src/ic300_config.vhd b/zpu/hdl/zpu4/src/ic300_config.vhd deleted file mode 100644 index b14ec79..0000000 --- a/zpu/hdl/zpu4/src/ic300_config.vhd +++ /dev/null @@ -1,26 +0,0 @@ -library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-package phi_config is
-
- constant Fpga_Global_Base : std_logic_vector(19 downto 17) := "000"; -- 0x0800....
- constant Clock_Stat_Reg_Addr : std_logic_vector(5 downto 2) := "0000"; -- 0x....0000
- constant Ctrl_Reg_Addr : std_logic_vector(5 downto 2) := "0001"; -- 0x....0004
- constant output_enable : std_logic_vector(5 downto 2) := "0010"; -- 0x....0008
- constant output_disable : std_logic_vector(5 downto 2) := "0011"; -- 0x....000C
- constant data_status : std_logic_vector(5 downto 2) := "0100"; -- 0x....0010
- constant set_output_data : std_logic_vector(5 downto 2) := "0101"; -- 0x....0014
- constant clear_output_data : std_logic_vector(5 downto 2) := "0110"; -- 0x....0018
- constant data_in_read : std_logic_vector(5 downto 2) := "0111"; -- 0x....001C
- constant output_status : std_logic_vector(5 downto 2) := "1000"; -- 0x....0020
- constant cpu_access_address : std_logic_vector(5 downto 2) := "1001"; -- 0x....0024
-
- constant Fpga_Ethernet_Reg_Base : std_logic_vector(19 downto 17) := "110"; -- 0x080C0000
-
- constant Fpga_DDR_Ctrl_Base : std_logic_vector(19 downto 17) := "111"; -- 0x080E....
- constant DDR_Ctrl_Reg_Addr : std_logic_vector(3 downto 2) := "00"; -- 0x....0000
- constant DDR_Mode_Reg_Addr : std_logic_vector(3 downto 2) := "01"; -- 0x....0004
- constant DDR_Page_Select_Addr : std_logic_vector(3 downto 2) := "10"; -- 0x....0008
-
-
-end phi_config;
diff --git a/zpu/hdl/zpu4/src/ic300pkg.vhd b/zpu/hdl/zpu4/src/ic300pkg.vhd deleted file mode 100644 index 13da306..0000000 --- a/zpu/hdl/zpu4/src/ic300pkg.vhd +++ /dev/null @@ -1,88 +0,0 @@ -library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-package ic300pkg is
-
- component ic300 is
- port ( -- Clock inputs
- cpu_clk_p : in std_logic;
-
- -- CPU interface signals
- cpu_a_p : in std_logic_vector(20 downto 0);
- cpu_wr_n_p : in std_logic_vector(1 downto 0);
- cpu_cs_n_p : in std_logic_vector(3 downto 1);
- cpu_oe_n_p : in std_logic;
- cpu_d_p : inout std_logic_vector(15 downto 0);
- cpu_irq_p : out std_logic_vector(1 downto 0);
- cpu_fiq_p : out std_logic;
- cpu_wait_n_p : out std_logic;
-
- -- DDR SDRAM Signals
- sdr_clk_p : out std_logic; -- ddr_sdram_clock
- sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock
- cke_q_p : out std_logic; -- clock enable
- cs_qn_p : out std_logic; -- /chip select
- ras_qn_p : inout std_logic; -- /ras
- cas_qn_p : inout std_logic; -- /cas
- we_qn_p : inout std_logic; -- /write enable
- dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00"
- dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write
- ba_q_p : out std_logic_vector(1 downto 0); -- bank select
- sdr_a_p : out std_logic_vector(12 downto 0); -- address bus
- sdr_d_p : inout std_logic_vector(15 downto 0); -- bidir data bus
- sdr_clk_fb_p : in std_logic -- DDR clock feedback
- );
- end component;
-
- component clocks is
- port ( areset : in std_logic;
- cpu_clk_p : in std_logic;
- sdr_clk_fb_p : in std_logic;
- cpu_clk : out std_logic;
- cpu_clk_2x : out std_logic;
- cpu_clk_4x : out std_logic;
- ddr_in_clk : out std_logic;
- ddr_in_clk_2x : out std_logic;
- locked : out std_logic_vector(2 downto 0));
- end component;
-
- component cpu_regs is
- port ( areset : in std_logic;
- cpu_clk : in std_logic;
- clk_status : in std_logic_vector(2 downto 0);
- cpu_din : in std_logic_vector(15 downto 0);
- cpu_a : in std_logic_vector(20 downto 0);
- cpu_we : in std_logic_vector(1 downto 0);
- cpu_re : in std_logic;
- cpu_dout : inout std_logic_vector(15 downto 0));
- end component;
-
- component ddr_bridge is
- port ( areset : in std_logic;
- cpu_clk : in std_logic;
- cpu_clk_2x : in std_logic;
- cpu_clk_4x : in std_logic;
- ddr_in_clk : in std_logic;
- ddr_in_clk_2x : in std_logic;
-
- cpu_we : in std_logic_vector(1 downto 0);
- cpu_re : in std_logic;
- cpu_din : in std_logic_vector(15 downto 0);
- cpu_a : in std_logic_vector(20 downto 0);
- cpu_dout : inout std_logic_vector(15 downto 0);
-
- sdr_clk_p : out std_logic; -- ddr_sdram_clock
- sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock
- cke_q_p : out std_logic; -- clock enable
- cs_qn_p : out std_logic; -- /chip select
- ras_qn_p : inout std_logic; -- /ras
- cas_qn_p : inout std_logic; -- /cas
- we_qn_p : inout std_logic; -- /write enable
- dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00"
- dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write
- ba_q_p : out std_logic_vector(1 downto 0); -- bank select
- sdr_a_p : out std_logic_vector(12 downto 0); -- address bus
- sdr_d_p : inout std_logic_vector(15 downto 0)); -- bidir data bus
- end component;
-
-end ic300pkg;
diff --git a/zpu/hdl/zpu4/src/xmake.filelist b/zpu/hdl/zpu4/src/xmake.filelist deleted file mode 100644 index 91e623f..0000000 --- a/zpu/hdl/zpu4/src/xmake.filelist +++ /dev/null @@ -1,12 +0,0 @@ -vhdl work "ic300_config.vhd"
-vhdl work "ic300pkg.vhd"
-vhdl zylin "zpu_config.vhd"
-vhdl zylin "zpupkg.vhd"
-vhdl zylin "zpu_core.vhd"
-vhdl work "bram.vhd"
-vhdl zylin "zpuio.vhd"
-vhdl zylin "..\dummyfpgalib\arm7\src\arm7pkg.vhd"
-vhdl zylin "..\dummyfpgalib\arm7\src\arm7wb.vhd"
-vhdl work "clocks.vhd"
-vhdl work "timer.vhd"
-vhdl work "ic300.vhd"
\ No newline at end of file diff --git a/zpu/hdl/zpu4/src/xmake.filelist.bramsmall b/zpu/hdl/zpu4/src/xmake.filelist.bramsmall deleted file mode 100644 index 141633e..0000000 --- a/zpu/hdl/zpu4/src/xmake.filelist.bramsmall +++ /dev/null @@ -1,5 +0,0 @@ -vhdl work "zpu_config.vhd"
-vhdl work "zpupkg.vhd"
-vhdl work "zpu_core_small.vhd"
-vhdl work "bram_dmips.vhd"
-vhdl work "testlut.vhd"
diff --git a/zpu/hdl/zpu4/src/xmake.xst b/zpu/hdl/zpu4/src/xmake.xst deleted file mode 100644 index bfdb23f..0000000 --- a/zpu/hdl/zpu4/src/xmake.xst +++ /dev/null @@ -1,53 +0,0 @@ -set -tmpdir ../tmp
-set -xsthdpdir ../xst
-run
--ifn xmake.filelist
--ifmt mixed
--ofn ../syn/ic300
--ofmt NGC
--p xc3s400-4-ft256
--top ic300
--opt_mode Area
--opt_level 2
--iuc NO
--lso ic300.lso
--keep_hierarchy NO
--glob_opt AllClockNets
--rtlview Yes
--read_cores YES
--write_timing_constraints NO
--cross_clock_analysis NO
--hierarchy_separator /
--bus_delimiter <>
--case maintain
--slice_utilization_ratio 100
--verilog2001 YES
--fsm_extract YES -fsm_encoding Auto
--safe_implementation No
--fsm_style lut
--ram_extract Yes
--ram_style Auto
--rom_extract Yes
--rom_style Auto
--mux_extract YES
--mux_style Auto
--decoder_extract YES
--priority_extract YES
--shreg_extract YES
--shift_extract YES
--xor_collapse YES
--resource_sharing YES
--mult_style auto
--iobuf YES
--max_fanout 500
--bufg 8
--register_duplication YES
--equivalent_register_removal NO
--register_balancing No
--slice_packing YES
--optimize_primitives NO
--use_clock_enable Yes
--use_sync_set No
--use_sync_reset No
--iob true
--slice_utilization_ratio_maxmargin 5
diff --git a/zpu/hdl/zpu4/src/zpuio_bram.vhd b/zpu/hdl/zpu4/src/zpuio_bram.vhd deleted file mode 100644 index 5d3f409..0000000 --- a/zpu/hdl/zpu4/src/zpuio_bram.vhd +++ /dev/null @@ -1,229 +0,0 @@ -library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library work;
-use work.zpu_config.all;
-use work.zpupkg.all;
-
-entity zpuio is
- port ( areset : in std_logic;
- cpu_clk : in std_logic;
- clk_status : in std_logic_vector(2 downto 0);
- cpu_din : in std_logic_vector(15 downto 0);
- cpu_a : in std_logic_vector(20 downto 0);
- cpu_we : in std_logic_vector(1 downto 0);
- cpu_re : in std_logic;
- cpu_dout : inout std_logic_vector(15 downto 0));
-end zpuio;
-
-architecture behave of zpuio is
-
-signal timer_read : std_logic_vector(7 downto 0);
---signal timer_write : std_logic_vector(7 downto 0);
-signal timer_we : std_logic;
-
-
-signal io_busy : std_logic;
-signal io_read : std_logic_vector(7 downto 0);
---signal io_write : std_logic_vector(7 downto 0);
-signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit);
-signal io_writeEnable : std_logic;
-signal Enable : std_logic;
-
-signal din : std_logic_vector(7 downto 0);
-signal dout : std_logic_vector(7 downto 0);
-signal adr : std_logic_vector(15 downto 0);
-signal break : std_logic;
-signal we : std_logic;
-signal re : std_logic;
-
-
--- uart forwarding...
-
-signal uartTXPending : std_logic;
-signal uartTXCleared : std_logic;
-signal uartData : std_logic_vector(7 downto 0);
-
-signal readingTimer : std_logic;
-
-
-
-
-signal mem_busy : std_logic;
-signal mem_read : std_logic_vector(wordSize-1 downto 0);
-signal mem_write : std_logic_vector(wordSize-1 downto 0);
-signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);
-signal mem_writeEnable : std_logic;
-signal mem_readEnable : std_logic;
-signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
-
-
-
-
---signal io_mem_read : std_logic_vector(7 downto 0);
---signal io_mem_writeEnable : std_logic;
---signal io_mem_readEnable : std_logic;
-signal io_readEnable : std_logic;
-
-
-
-
-
-begin
-
- io_addr <= mem_addr(maxAddrBit downto minAddrBit);
-
- timerinst: timer port map (
- clk => cpu_clk,
- areset => areset,
- we => timer_we,
- din => mem_write(7 downto 0),
- adr => io_addr(4 downto 2),
- dout => timer_read);
-
- zpu: zpu_core port map (
- clk => cpu_clk ,
- areset => areset,
- in_mem_busy => mem_busy,
- mem_read => mem_read,
- mem_write => mem_write,
- out_mem_addr => mem_addr,
- out_mem_writeEnable => mem_writeEnable,
- out_mem_readEnable => mem_readEnable,
- mem_writeMask => mem_writeMask,
- interrupt => '0',
- break => break);
-
-
-
-
- -- Read/write are on different addresses
- -- The registers are 8 bits and mapped to bit[7:0]
- --
- -- 0xC000 Write: Writes to UART TX FIFO (4 byte FIFO)
- -- Read : Reads from UART RX FIFO (4 byte FIFO)
- -- 0xC004 Read : UART status register
- -- Bit 0 = RX FIFO empty
- -- Bit 1 = TX FIFO full
- -- 0xA000 Skrive: LED's (8 stk.)
-
- -- 0x9000 Write: bit 0: 1= reset counter
- -- 0= counter running
- -- bit 1: 1= sample counter (when set to 1)
- -- 0=not used
- -- Read : counter bit[7:0]
- -- 0x9004 Read: counter bit [15:8]
- -- 0x9008 Read: counter bit [23:16]
- -- 0x900C Read: counter bit [31:24]
- -- 0x9010 Read: counter bit [39:32]
- -- 0x9014 Read: counter bit [47:40]
- -- 0x9018 Read: counter bit [55:48]
- -- 0x901C Read: counter bit [63:56]
- --
- -- 0x8800 Read: unsigned 8-bit integer with FPGA frequency (in MHz)
-
- fauxUart:
- process(cpu_clk, areset)
- begin
- if areset = '1' then
- io_busy <= '0';
- uartTXPending <= '0';
- timer_we <= '0';
- io_busy <= '0';
- uartData <= x"58"; -- 'X'
- readingTimer <= '0';
- elsif (cpu_clk'event and cpu_clk = '1') then
- timer_we <= '0';
- io_busy <= '0';
- if uartTXCleared = '1' then
- uartTXPending <= '0';
- end if;
-
- if io_writeEnable = '1' then
- if io_addr=x"1000" then
- -- Write to UART
- uartData <= mem_write(7 downto 0);
- uartTXPending <= '1';
- io_busy <= '1';
- elsif io_addr(12)='1' then
- timer_we <= '1';
- io_busy <= '1';
- else
- report "Illegal IO write" severity failure;
- end if;
- end if;
- if (io_readEnable = '1') then
- if io_addr=x"1001" then
- io_read <= (0=>'1', -- recieve empty
- 1 => uartTXPending, -- tx full
- others => '0');
- io_busy <= '1';
- elsif io_addr(12)='1' then
- readingTimer <= '1';
- io_busy <= '1';
- elsif io_addr(11)='1' then
- io_read <= ZPU_Frequency;
- io_busy <= '1';
- else
- report "Illegal IO read" severity failure;
- end if;
-
- else
- if (readingTimer = '1') then
- readingTimer <= '0';
- io_read <= timer_read;
- io_busy <= '0';
- else
- io_read <= (others => '1');
- end if;
- end if;
- end if;
- end process;
-
-
- forwardUARTOutputToARM:
- process(cpu_clk, areset)
- begin
- if areset = '1' then
- uartTXCleared <= '0';
- elsif (cpu_clk = '1' and cpu_clk'event) then
- if cpu_we(0) = '1' and cpu_a(3 downto 1) = "000" then
- uartTXCleared <= cpu_din(0);
- else
- uartTXCleared <= uartTXCleared;
- end if;
- end if;
- end process;
-
- cpu_dout(7 downto 0) <= uartData when (cpu_re = '1' and cpu_a(3 downto 1) = "001") else (others => 'Z');
- cpu_dout <= (0 => uartTXPending, others => '0') when (cpu_re = '1' and cpu_a(3 downto 1) = "000") else (others => 'Z');
-
- io_writeEnable <= mem_writeEnable and mem_addr(ioBit);
--- io_readEnable <= mem_readEnable and mem_addr(ioBit);
- mem_busy <= io_busy or io_readEnable;
-
- -- Memory reads either come from IO or DRAM. We need to pick the right one.
- memorycontrol:
- process(cpu_clk, areset)
- begin
- if areset = '1' then
- io_readEnable <= '0';
-
-
- elsif (cpu_clk'event and cpu_clk = '1') then
- mem_read <= (others => '0');
-
- if mem_addr(ioBit)='1' and mem_readEnable='1' then
- io_readEnable <= '1';
- end if;
- if io_readEnable='1' and io_busy='0' then
- io_readEnable <= '0';
- mem_read(7 downto 0) <= io_read;
- end if;
-
- end if;
- end process;
-
-
-end behave;
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