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-rw-r--r--zpu/hdl/zpu4/src/zpu_config_fastsim.vhd15
1 files changed, 15 insertions, 0 deletions
diff --git a/zpu/hdl/zpu4/src/zpu_config_fastsim.vhd b/zpu/hdl/zpu4/src/zpu_config_fastsim.vhd
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+++ b/zpu/hdl/zpu4/src/zpu_config_fastsim.vhd
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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+package zpu_config is
+
+ constant Generate_Trace : boolean := false;
+ constant wordPower : integer := 5;
+ -- during simulation, set this to '0' to get matching trace.txt
+ constant DontCareValue : std_logic := '0';
+ -- Clock frequency in MHz.
+ constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"50"; -- 80MHz
+ constant maxAddrBitIncIO : integer := 15;
+
+end zpu_config;
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