diff options
Diffstat (limited to 'zpu/hdl/zealot/fpga/digilent-starter-xc3s500e')
10 files changed, 1253 insertions, 0 deletions
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/clean_up.sh b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/clean_up.sh new file mode 100755 index 0000000..3855f16 --- /dev/null +++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/clean_up.sh @@ -0,0 +1,16 @@ +#!/bin/sh + +# ise build stuff +rm -rf build +rm -f top.bit + +# modelsim compile stuff +rm -rf work +rm -rf zpu + +# modelsim simulation stuff +rm -f vsim.wlf +rm -f transcript +rm -f zpu_trace.log +rm -f zpu_med1_io.log +rm -f zpu_small1_io.log diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation.sh b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation.sh new file mode 100755 index 0000000..febf588 --- /dev/null +++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation.sh @@ -0,0 +1,48 @@ +#!/bin/sh + +# need project files: +# run.do +# wave.do + +# need ModelSim tools: +# vlib +# vcom +# vsim + + +echo "###############" +echo "compile zpu lib" +echo "###############" +vlib zpu +vcom -work zpu ../../roms/hello_dbram.vhdl +vcom -work zpu ../../roms/hello_bram.vhdl +#vcom -work zpu ../../roms/dmips_dbram.vhdl +#vcom -work zpu ../../roms/dmips_bram.vhdl + +vcom -work zpu ../../roms/rom_pkg.vhdl +vcom -work zpu ../../zpu_pkg.vhdl +vcom -work zpu ../../zpu_small.vhdl +vcom -work zpu ../../zpu_medium.vhdl +vcom -work zpu ../../helpers/zpu_small1.vhdl +vcom -work zpu ../../helpers/zpu_med1.vhdl +vcom -work zpu ../../devices/txt_util.vhdl +vcom -work zpu ../../devices/phi_io.vhdl +vcom -work zpu ../../devices/timer.vhdl +vcom -work zpu ../../devices/rx_unit.vhdl +vcom -work zpu ../../devices/tx_unit.vhdl +vcom -work zpu ../../devices/br_gen.vhdl +vcom -work zpu ../../devices/trace.vhdl + + +echo "################" +echo "compile work lib" +echo "################" +vlib work +vcom top.vhd +vcom top_tb.vhd + + +echo "###################" +echo "start simulator gui" +echo "###################" +vsim -gui top_tb -do simulation_config/run.do diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/run.do b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/run.do new file mode 100644 index 0000000..7c5e18f --- /dev/null +++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/run.do @@ -0,0 +1,4 @@ +add wave tb_rot_center +add wave tb_clk_50mhz +add wave tb_rs232_dce* +run -all diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis.sh b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis.sh new file mode 100755 index 0000000..66622ea --- /dev/null +++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis.sh @@ -0,0 +1,36 @@ +#!/bin/sh + +# need project files: +# top.xst +# top.prj +# top.ut + +# need Xilinx tools: +# xst +# ngdbuild +# map +# par +# trce +# bitgen + +echo "########################" +echo "generate build directory" +echo "########################" +mkdir build +cd build +mkdir tmp + +echo "###############" +echo "start processes" +echo "###############" +xst -ifn "../synthesis_config/top.xst" -ofn "top.syr" +ngdbuild -dd _ngo -nt timestamp -uc ../synthesis_config/digilent-starter-xc3s500e.ucf -p xc3s500e-fg320-4 top.ngc top.ngd +map -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o top_map.ncd top.ngd top.pcf +par -w -ol high -t 1 top_map.ncd top.ncd top.pcf +trce -v 3 -s 4 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf +bitgen -f ../synthesis_config/top.ut top.ncd + +echo "###########" +echo "get bitfile" +echo "###########" +cp top.bit .. diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/digilent-starter-xc3s500e.ucf b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/digilent-starter-xc3s500e.ucf new file mode 100644 index 0000000..1007d00 --- /dev/null +++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/digilent-starter-xc3s500e.ucf @@ -0,0 +1,356 @@ +#####################################################
+# SPARTAN-3E Starter Kit Board Constraints File
+#
+# Family: Spartan3E
+# Device: XC3S500E
+# Package: FG320
+# Speed: -4
+
+
+############################################################
+## clock/timing constraints
+############################################################
+
+# Define clock period for 50 MHz oscillator (40%/60% duty-cycle)
+TIMESPEC "TS_CLK_50MHZ" = PERIOD "CLK_50MHZ" 50.0 MHz HIGH 40%;
+
+# ethernet clock
+TIMESPEC "TS_E_CLK" = PERIOD "E_CLK" 25.0 MHz HIGH 50% ;
+# need because misplaced ethernet clock lines
+NET "E_RX_CLK" CLOCK_DEDICATED_ROUTE = FALSE ;
+NET "E_TX_CLK" CLOCK_DEDICATED_ROUTE = FALSE ;
+
+############################################################
+## pin placement constraints
+############################################################
+
+# Analog-to-Digital Converter (ADC)
+# some connections shared with SPI Flash, DAC, ADC, and AMP
+NET "AD_CONV" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+
+# Programmable Gain Amplifier (AMP)
+# some connections shared with SPI Flash, DAC, ADC, and AMP
+NET "AMP_CS" LOC = "N7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+NET "AMP_DOUT" LOC = "E18" | IOSTANDARD = LVCMOS33 ;
+NET "AMP_SHDN" LOC = "P7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+
+# Pushbuttons (BTN)
+NET "BTN_EAST" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN | TIG;
+NET "BTN_NORTH" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN | TIG;
+NET "BTN_SOUTH" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN | TIG;
+NET "BTN_WEST" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN | TIG;
+
+# Clock inputs (CLK)
+NET "CLK_50MHZ" LOC = "C9" | IOSTANDARD = LVCMOS33 | TNM_NET = "CLK_50MHZ";
+NET "CLK_AUX" LOC = "B8" | IOSTANDARD = LVCMOS33 ;
+NET "CLK_SMA" LOC = "A10" | IOSTANDARD = LVCMOS33 ;
+
+# Digital-to-Analog Converter (DAC)
+# some connections shared with SPI Flash, DAC, ADC, and AMP
+NET "DAC_CLR" LOC = "P8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "DAC_CS" LOC = "N8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+
+# 1-Wire Secure EEPROM (DS)
+NET "DS_WIRE" LOC = "U4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+
+# Ethernet PHY (E)
+NET "E_COL" LOC = "U6" | IOSTANDARD = LVCMOS33 ;
+NET "E_CRS" LOC = "U13" | IOSTANDARD = LVCMOS33 ;
+NET "E_MDC" LOC = "P9" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "E_MDIO" LOC = "U5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "E_RX_CLK" LOC = "V3" | IOSTANDARD = LVCMOS33 | TNM_NET = "E_CLK";
+NET "E_RX_DV" LOC = "V2" | IOSTANDARD = LVCMOS33 ;
+NET "E_RXD<0>" LOC = "V8" | IOSTANDARD = LVCMOS33 ;
+NET "E_RXD<1>" LOC = "T11" | IOSTANDARD = LVCMOS33 ;
+NET "E_RXD<2>" LOC = "U11" | IOSTANDARD = LVCMOS33 ;
+NET "E_RXD<3>" LOC = "V14" | IOSTANDARD = LVCMOS33 ;
+NET "E_RX_ER" LOC = "U14" | IOSTANDARD = LVCMOS33 ;
+NET "E_TX_CLK" LOC = "T7" | IOSTANDARD = LVCMOS33 | TNM_NET = "E_CLK";
+NET "E_TX_EN" LOC = "P15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "E_TXD<0>" LOC = "R11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "E_TXD<1>" LOC = "T15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "E_TXD<2>" LOC = "R5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "E_TXD<3>" LOC = "T5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "E_TX_ER" LOC = "R6" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+
+# FPGA Configuration Mode, INIT_B Pins (FPGA)
+NET "FPGA_M0" LOC = "M10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "FPGA_M1" LOC = "V11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "FPGA_M2" LOC = "T10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "FPGA_INIT_B" LOC = "T3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
+NET "FPGA_RDWR_B" LOC = "U10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
+NET "FPGA_HSWAP" LOC = "B3" | IOSTANDARD = LVCMOS33 ;
+
+# FX2 Connector (FX2)
+NET "FX2_CLKIN" LOC = "E10" | IOSTANDARD = LVCMOS33 ;
+NET "FX2_CLKIO" LOC = "D9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_CLKOUT" LOC = "D10" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+
+# These four connections are shared with the J1 6-pin accessory header
+NET "FX2_IO<1>" LOC = "B4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<2>" LOC = "A4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<3>" LOC = "D5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<4>" LOC = "C5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+
+# These four connections are shared with the J2 6-pin accessory header
+NET "FX2_IO<5>" LOC = "A6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<6>" LOC = "B6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<7>" LOC = "E7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<8>" LOC = "F7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+
+# These four connections are shared with the J4 6-pin accessory header
+NET "FX2_IO<9>" LOC = "D7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<10>" LOC = "C7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<11>" LOC = "F8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<12>" LOC = "E8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+
+# The discrete LEDs are shared with the following 8 FX2 connections
+NET "FX2_IO<13>" LOC = "F9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<14>" LOC = "E9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<15>" LOC = "D11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<16>" LOC = "C11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<17>" LOC = "F11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<18>" LOC = "E11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<19>" LOC = "E12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<20>" LOC = "F12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+
+NET "FX2_IO<21>" LOC = "A13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<22>" LOC = "B13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<23>" LOC = "A14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<24>" LOC = "B14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<25>" LOC = "C14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<26>" LOC = "D14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<27>" LOC = "A16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<28>" LOC = "B16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<29>" LOC = "E13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<30>" LOC = "C4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<31>" LOC = "B11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<32>" LOC = "A11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<33>" LOC = "A8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<34>" LOC = "G9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#
+NET "FX2_IO<35>" LOC = "D12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<36>" LOC = "C12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<37>" LOC = "A15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<38>" LOC = "B15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#
+NET "FX2_IO<39>" LOC = "C3" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<40>" LOC = "C15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+
+# 6-pin header J1
+# These are shared connections with the FX2 connector
+#NET "J1<0>" LOC = "B4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J1<1>" LOC = "A4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J1<2>" LOC = "D5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J1<3>" LOC = "C5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+
+# 6-pin header J2
+# These are shared connections with the FX2 connector
+#NET "J2<0>" LOC = "A6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J2<1>" LOC = "B6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J2<2>" LOC = "E7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J2<3>" LOC = "F7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+
+# 6-pin header J4
+# These are shared connections with the FX2 connector
+#NET "J4<0>" LOC = "D7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J4<1>" LOC = "C7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J4<2>" LOC = "F8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J4<3>" LOC = "E8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+
+# Character LCD (LCD)
+NET "LCD_E" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "LCD_RS" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "LCD_RW" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+
+# LCD data connections are shared with StrataFlash connections SF_D<11:8>
+#NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+
+# Discrete LEDs (LED)
+# These are shared connections with the FX2 connector
+#NET "LED<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<6>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<7>" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+
+# PS/2 Mouse/Keyboard Port (PS2)
+NET "PS2_CLK" LOC = "G14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW | TIG;
+NET "PS2_DATA" LOC = "G13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW | TIG;
+
+# Rotary Pushbutton Switch (ROT)
+NET "ROT_A" LOC = "K18" | IOSTANDARD = LVTTL | PULLUP | TIG;
+NET "ROT_B" LOC = "G18" | IOSTANDARD = LVTTL | PULLUP | TIG;
+NET "ROT_CENTER" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN | TIG;
+
+# RS-232 Serial Ports (RS232)
+NET "RS232_DCE_RXD" LOC = "R7" | IOSTANDARD = LVTTL | TIG;
+NET "RS232_DCE_TXD" LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW | TIG;
+NET "RS232_DTE_RXD" LOC = "U8" | IOSTANDARD = LVTTL | TIG;
+NET "RS232_DTE_TXD" LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW | TIG;
+
+# DDR SDRAM (SD) (I/O Bank 3, VCCO=2.5V)
+NET "SD_A<0>" LOC = "T1" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<1>" LOC = "R3" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<2>" LOC = "R2" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<3>" LOC = "P1" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<4>" LOC = "F4" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<5>" LOC = "H4" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<6>" LOC = "H3" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<7>" LOC = "H1" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<8>" LOC = "H2" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<9>" LOC = "N4" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<10>" LOC = "T2" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<11>" LOC = "N5" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<12>" LOC = "P2" | IOSTANDARD = SSTL2_I ;
+NET "SD_BA<0>" LOC = "K5" | IOSTANDARD = SSTL2_I ;
+NET "SD_BA<1>" LOC = "K6" | IOSTANDARD = SSTL2_I ;
+NET "SD_CAS" LOC = "C2" | IOSTANDARD = SSTL2_I ;
+NET "SD_CK_N" LOC = "J4" | IOSTANDARD = SSTL2_I ; #DIFF_SSTL2_I ;
+NET "SD_CK_P" LOC = "J5" | IOSTANDARD = SSTL2_I ; #DIFF_SSTL2_I ;
+NET "SD_CKE" LOC = "K3" | IOSTANDARD = SSTL2_I ;
+NET "SD_CS" LOC = "K4" | IOSTANDARD = SSTL2_I ;
+NET "SD_DQ<0>" LOC = "L2" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<1>" LOC = "L1" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<2>" LOC = "L3" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<3>" LOC = "L4" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<4>" LOC = "M3" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<5>" LOC = "M4" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<6>" LOC = "M5" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<7>" LOC = "M6" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<8>" LOC = "E2" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<9>" LOC = "E1" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<10>" LOC = "F1" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<11>" LOC = "F2" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<12>" LOC = "G6" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<13>" LOC = "G5" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<14>" LOC = "H6" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<15>" LOC = "H5" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_LDM" LOC = "J2" | IOSTANDARD = SSTL2_I ;
+NET "SD_UDM" LOC = "J1" | IOSTANDARD = SSTL2_I ;
+NET "SD_RAS" LOC = "C1" | IOSTANDARD = SSTL2_I ;
+NET "SD_LDQS" LOC = "L6" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_UDQS" LOC = "G3" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_WE" LOC = "D1" | IOSTANDARD = SSTL2_I ;
+# Path to allow connection to top DCM connection
+NET "SD_CK_FB" LOC = "B9" | IOSTANDARD = LVCMOS33 ;
+
+# Prohibit VREF pins
+CONFIG PROHIBIT = D2;
+CONFIG PROHIBIT = G4;
+CONFIG PROHIBIT = J6;
+CONFIG PROHIBIT = L5;
+CONFIG PROHIBIT = R4;
+
+# Intel StrataFlash Parallel NOR Flash (SF)
+NET "SF_A<0>" LOC = "H17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<1>" LOC = "J13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<2>" LOC = "J12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<3>" LOC = "J14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<4>" LOC = "J15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<5>" LOC = "J16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<6>" LOC = "J17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<7>" LOC = "K14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<8>" LOC = "K15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<9>" LOC = "K12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<10>" LOC = "K13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<11>" LOC = "L15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<12>" LOC = "L16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<13>" LOC = "T18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<14>" LOC = "R18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<15>" LOC = "T17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<16>" LOC = "U18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<17>" LOC = "T16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<18>" LOC = "U15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<19>" LOC = "V15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<20>" LOC = "T12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<21>" LOC = "V13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<22>" LOC = "V12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<23>" LOC = "N11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<24>" LOC = "A11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_BYTE" LOC = "C17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<1>" LOC = "P10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<2>" LOC = "R10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<3>" LOC = "V9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<4>" LOC = "U9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<5>" LOC = "R9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<6>" LOC = "M9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<7>" LOC = "N9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<12>" LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<13>" LOC = "P6" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<14>" LOC = "R8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<15>" LOC = "T8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_OE" LOC = "C18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_STS" LOC = "B18" | IOSTANDARD = LVCMOS33 ;
+NET "SF_WE" LOC = "D17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+
+# STMicro SPI serial Flash (SPI)
+# some connections shared with SPI Flash, DAC, ADC, and AMP
+NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ;
+NET "SPI_MOSI" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+NET "SPI_SS_B" LOC = "U3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 | PULLUP ;
+NET "SPI_ALT_CS_JP11" LOC = "R12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+
+# Slide Switches (SW)
+NET "SW<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP | TIG;
+NET "SW<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP | TIG;
+NET "SW<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP | TIG;
+NET "SW<3>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP | TIG;
+
+# VGA Port (VGA)
+NET "VGA_BLUE" LOC = "G15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "VGA_GREEN" LOC = "H15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "VGA_HSYNC" LOC = "F15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "VGA_RED" LOC = "H14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "VGA_VSYNC" LOC = "F14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+
+# Xilinx CPLD (XC)
+NET "XC_CMD<0>" LOC = "P18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
+NET "XC_CMD<1>" LOC = "N18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
+NET "XC_CPLD_EN" LOC = "B10" | IOSTANDARD = LVTTL ;
+NET "XC_D<0>" LOC = "G16" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
+NET "XC_D<1>" LOC = "F18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
+NET "XC_D<2>" LOC = "F17" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
+NET "XC_TRIG" LOC = "R17" | IOSTANDARD = LVCMOS33 ;
+NET "XC_GCK0" LOC = "H16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "GCLK10" LOC = "C9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+
+# prohibit unused pins
+CONFIG PROHIBIT = A3;
+CONFIG PROHIBIT = A7;
+CONFIG PROHIBIT = D13;
+CONFIG PROHIBIT = F10;
+CONFIG PROHIBIT = G10;
+CONFIG PROHIBIT = C8;
+CONFIG PROHIBIT = D8;
+CONFIG PROHIBIT = A5;
+CONFIG PROHIBIT = B5;
+#
+CONFIG PROHIBIT = P13;
+CONFIG PROHIBIT = R13;
+CONFIG PROHIBIT = T14;
+CONFIG PROHIBIT = R14;
+#
+CONFIG PROHIBIT = D3;
+CONFIG PROHIBIT = F5;
+CONFIG PROHIBIT = G1;
+CONFIG PROHIBIT = J7;
+CONFIG PROHIBIT = K2;
+CONFIG PROHIBIT = K7;
+CONFIG PROHIBIT = M1;
+CONFIG PROHIBIT = N1;
+CONFIG PROHIBIT = N2;
+CONFIG PROHIBIT = R1;
+CONFIG PROHIBIT = U1;
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj new file mode 100644 index 0000000..81d56ef --- /dev/null +++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj @@ -0,0 +1,18 @@ +vhdl work ../top.vhd +vhdl zpu ../../../zpu_pkg.vhdl +vhdl zpu ../../../zpu_small.vhdl +vhdl zpu ../../../zpu_medium.vhdl +vhdl zpu ../../../roms/rom_pkg.vhdl +#vhdl zpu ../../../roms/hello_dbram.vhdl +#vhdl zpu ../../../roms/hello_bram.vhdl +vhdl zpu ../../../roms/dmips_dbram.vhdl +vhdl zpu ../../../roms/dmips_bram.vhdl +vhdl zpu ../../../helpers/zpu_small1.vhdl +vhdl zpu ../../../helpers/zpu_med1.vhdl +vhdl zpu ../../../devices/txt_util.vhdl +vhdl zpu ../../../devices/phi_io.vhdl +vhdl zpu ../../../devices/timer.vhdl +vhdl zpu ../../../devices/rx_unit.vhdl +vhdl zpu ../../../devices/tx_unit.vhdl +vhdl zpu ../../../devices/br_gen.vhdl +vhdl zpu ../../../devices/trace.vhdl diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut new file mode 100644 index 0000000..06de8d5 --- /dev/null +++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut @@ -0,0 +1,22 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g CRC:Enable +-g ConfigRate:1 +-g ProgPin:PullUp +-g DonePin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g DCMShutdown:Disable +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.xst b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.xst new file mode 100644 index 0000000..fc7cc1d --- /dev/null +++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.xst @@ -0,0 +1,56 @@ +set -tmpdir "tmp" +set -xsthdpdir "xst" +run +-ifn ../synthesis_config/top.prj +-ifmt mixed +-ofn top +-ofmt NGC +-p xc3s500e-4-fg320 +-top top +-opt_mode Speed +-opt_level 1 +-iuc NO +-keep_hierarchy No +-netlist_hierarchy As_Optimized +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case Maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style LUT +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract Yes +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract Yes +-resource_sharing YES +-async_to_sync NO +-mult_style Auto +-iobuf YES +-max_fanout 500 +-bufg 24 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob Auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top.vhd b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top.vhd new file mode 100644 index 0000000..127f6a8 --- /dev/null +++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top.vhd @@ -0,0 +1,419 @@ +-- top module of +-- Spartan-3E Starter Kit Board +-- +-- using following external connections: +-- rotary pushbutton as reset +-- LEDs for output +-- RS232 (DCE, the left one) +-- + + +library ieee; +use ieee.std_logic_1164.all; + +library zpu; +use zpu.zpupkg.all; -- zpu_dbgo_t + +library unisim; +use unisim.vcomponents.dcm_sp; + + +entity top is + port ( + -- pragma translate_off + stop_simulation : out std_logic; + -- pragma translate_on + -- + -- Analog-to-Digital Converter (ADC) + ad_conv : out std_logic; + -- Programmable Gain Amplifier (AMP) + amp_cs : out std_logic; -- active low chip select + amp_dout : in std_logic; + amp_shdn : out std_logic; -- active high shutdown, reset + -- Pushbuttons (BTN) + btn_east : in std_logic; + btn_north : in std_logic; + btn_south : in std_logic; + btn_west : in std_logic; + -- Clock inputs (CLK) + clk_50mhz : in std_logic; + clk_aux : in std_logic; + clk_sma : in std_logic; + -- Digital-to-Analog Converter (DAC) + dac_clr : out std_logic; -- async, active low reset input + dac_cs : out std_logic; -- active low chip select, conv start with rising edge + -- 1-Wire Secure EEPROM (DS) + ds_wire : inout std_logic; + -- Ethernet PHY (E) + e_col : in std_logic; -- MII collision detect + e_crs : in std_logic; -- carrier sense + e_mdc : out std_logic; -- management clock + e_mdio : inout std_logic; -- management data io + e_rx_clk : in std_logic; -- receive clock 25MHz@100BaseTx or 2.5MHz@10Base-T + e_rx_dv : in std_logic; -- receive data valid + e_rxd : in std_logic_vector(3 downto 0); + e_rx_er : in std_logic; + e_tx_clk : in std_logic; -- transmit clock 25MHz@100BaseTx or 2.5MHz@10Base-T + e_tx_en : out std_logic; -- transmit enable + e_txd : out std_logic_vector(3 downto 0); + e_tx_er : out std_logic; + -- FPGA Configuration Mode, INIT_B Pins (FPGA) + fpga_m0 : inout std_logic; + fpga_m1 : inout std_logic; + fpga_m2 : inout std_logic; + fpga_init_b : inout std_logic; + fpga_rdwr_b : in std_logic; + fpga_hswap : in std_logic; + -- FX2 Connector (FX2) + fx2_clkin : inout std_logic; + fx2_clkio : inout std_logic; + fx2_clkout : inout std_logic; + fx2_io : inout std_logic_vector(40 downto 1); + -- These are shared connections with the FX2 connector + --j1 : inout std_logic_vector(3 downto 0); + --j2 : inout std_logic_vector(3 downto 0); + --j4 : inout std_logic_vector(3 downto 0); + --led : out std_logic_vector(7 downto 0); + -- Character LCD (LCD) + lcd_e : out std_logic; + lcd_rs : out std_logic; + lcd_rw : out std_logic; + -- LCD data connections are shared with StrataFlash connections SF_D<11:8> + --sf_d : inout std_ulogic_vector(11 downto 8); + -- PS/2 Mouse/Keyboard Port (PS2) + ps2_clk : inout std_logic; + ps2_data : inout std_logic; + -- Rotary Pushbutton Switch (ROT) + rot_a : in std_logic; + rot_b : in std_logic; + rot_center : in std_logic; + -- RS-232 Serial Ports (RS232) + rs232_dce_rxd : in std_logic; + rs232_dce_txd : out std_logic; + rs232_dte_rxd : in std_logic; + rs232_dte_txd : out std_logic; + -- DDR SDRAM (SD) (I/O Bank 3, VCCO=2.5V) + sd_a : out std_logic_vector(12 downto 0); -- address inputs + sd_dq : inout std_logic_vector(15 downto 0); -- data io + sd_ba : out std_logic_vector(1 downto 0); -- bank address inputs + sd_ras : out std_logic; -- command output + sd_cas : out std_logic; -- command output + sd_we : out std_logic; -- command output + sd_udm : out std_logic; -- data mask + sd_ldm : out std_logic; -- data mask + sd_udqs : inout std_logic; -- data strobe + sd_ldqs : inout std_logic; -- data strobe + sd_cs : out std_logic; -- active low chip select + sd_cke : out std_logic; -- active high clock enable + sd_ck_n : out std_logic; -- differential clock + sd_ck_p : out std_logic; -- differential clock + -- Path to allow connection to top DCM connection + sd_ck_fb : in std_logic; + -- Intel StrataFlash Parallel NOR Flash (SF) + sf_a : out std_logic_vector(23 downto 0); -- sf_a<24> = fx_io32 + sf_byte : out std_logic; + sf_ce0 : out std_logic; + sf_d : inout std_logic_vector(15 downto 1); + sf_oe : out std_logic; + sf_sts : in std_logic; + sf_we : out std_logic; + -- STMicro SPI serial Flash (SPI) + spi_mosi : out std_logic; -- master out slave in + spi_miso : in std_logic; -- master in slave out + spi_sck : out std_logic; -- clock + spi_ss_b : out std_logic; -- active low slave select + spi_alt_cs_jp11 : out std_logic; + -- Slide Switches (SW) + sw : in std_logic_vector(3 downto 0); + -- VGA Port (VGA) + vga_blue : out std_logic; + vga_green : out std_logic; + vga_hsync : out std_logic; + vga_red : out std_logic; + vga_vsync : out std_logic; + -- Xilinx CPLD (XC) + xc_cmd : out std_logic_vector(1 downto 0); + xc_cpld_en : out std_logic; + xc_d : inout std_logic_vector(2 downto 0); + xc_trig : in std_logic; + xc_gck0 : inout std_logic; + gclk10 : inout std_logic + ); +end entity top; + + +architecture rtl of top is + + --------------------------- + -- type declarations + type zpu_type is (zpu_small, zpu_medium); + + --------------------------- + -- constant declarations + constant zpu_flavour : zpu_type := zpu_medium; -- choose your flavour HERE + -- modify frequency here + constant clk_multiply : positive := 3; -- 2 for small, 3 for medium + constant clk_divide : positive := 2; -- 1 for small, 2 for medium + -- + constant word_size_c : natural := 32; -- 32 bits data path + constant addr_w_c : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O + + + constant spi_ss_b_disable : std_ulogic := '1'; -- 1 = disable SPI serial flash + constant dac_cs_disable : std_ulogic := '1'; -- 1 = disable DAC + constant amp_cs_disable : std_ulogic := '1'; -- 1 = disable programmable pre-amplifier + constant ad_conv_disable : std_ulogic := '0'; -- 0 = disable ADC + constant sf_ce0_disable : std_ulogic := '1'; + constant fpga_init_b_disable : std_ulogic := '1'; -- 1 = disable pflatform flash PROM + -- + -- connect ldc to fpga + constant sf_ce0_lcd_to_fpga : std_ulogic := '1'; + -- + constant clk_frequency : positive := 50; -- input frequency for correct calculation + + + --------------------------- + -- component declarations + component zpu_small1 is + generic ( + word_size : natural := 32; -- 32 bits data path + d_care_val : std_logic := '0'; -- Fill value + clk_freq : positive := 50; -- 50 MHz clock + brate : positive := 115200; -- RS232 baudrate + addr_w : natural := 16; -- 16 bits address space=64 kB, 32 kB I/O + bram_w : natural := 15 -- 15 bits RAM space=32 kB + ); + port ( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + break_o : out std_logic; -- Break executed + dbg_o : out zpu_dbgo_t; -- Debug info + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic -- UART Rx + ); + end component zpu_small1; + + component zpu_med1 is + generic( + word_size : natural := 32; -- 32 bits data path + d_care_val : std_logic := '0'; -- Fill value + clk_freq : positive := 50; -- 50 MHz clock + brate : positive := 115200; -- RS232 baudrate + addr_w : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O + bram_w : natural := 15 -- 15 bits RAM space=32 kB + ); + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + break_o : out std_logic; -- Break executed + dbg_o : out zpu_dbgo_t; -- Debug info + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic -- UART Rx + ); + end component zpu_med1; + + + --------------------------- + -- signal declarations + signal dcm_sp_i0_clk0 : std_ulogic; + signal dcm_sp_i0_clkfx : std_ulogic; + signal clk_fb : std_ulogic; + signal clk : std_ulogic; + -- + signal reset_shift_reg : std_ulogic_vector(3 downto 0); + signal reset_sync : std_ulogic; + -- + signal zpu_i0_dbg : zpu_dbgo_t; -- Debug info + signal zpu_i0_break : std_logic; + + --------------------------- + -- alias declarations + alias led : std_logic_vector(7 downto 0) is fx2_io(20 downto 13); + + +begin + + -- default output drivers + -- to pass bitgen DRC + -- outputs used by design are commented + -- + ad_conv <= ad_conv_disable; + amp_cs <= amp_cs_disable; + amp_shdn <= '1'; + -- + dac_clr <= '0'; + dac_cs <= dac_cs_disable; + -- + ds_wire <= 'Z'; + -- + e_txd(3 downto 0) <= (others => '1'); + e_tx_en <= '0'; + e_tx_er <= '0'; + e_mdc <= '1'; + e_mdio <= 'Z'; + -- + fpga_m0 <= 'Z'; + fpga_m1 <= 'Z'; + fpga_m2 <= 'Z'; + fpga_init_b <= fpga_init_b_disable; + -- + fx2_clkin <= 'Z'; + fx2_clkio <= 'Z'; + fx2_clkout <= 'Z'; + fx2_io <= (others => 'Z'); + -- + lcd_e <= '0'; + lcd_rs <= '0'; + lcd_rw <= '0'; + -- + ps2_clk <= 'Z'; + ps2_data <= 'Z'; + -- + --rs232_dce_txd <= '1'; + rs232_dte_txd <= '1'; + -- + sd_a <= (others => '1'); + sd_dq <= (others => 'Z'); + sd_ba <= (others => '1'); + sd_ras <= '0'; + sd_cas <= '0'; + sd_we <= '0'; + sd_udm <= '1'; + sd_ldm <= '1'; + sd_udqs <= '1'; + sd_ldqs <= '1'; + sd_cs <= '1'; + sd_cke <= '1'; + sd_ck_n <= '0'; + sd_ck_p <= '1'; + -- + sf_a <= (others => '0'); + sf_byte <= '0'; + sf_ce0 <= sf_ce0_lcd_to_fpga; + sf_d <= (others => 'Z'); + sf_oe <= '1'; + sf_we <= '0'; + -- + spi_mosi <= '0'; + spi_sck <= '0'; + spi_ss_b <= spi_ss_b_disable; + spi_alt_cs_jp11 <= spi_ss_b_disable; + -- + vga_red <= '0'; + vga_green <= '0'; + vga_blue <= '0'; + vga_hsync <= '0'; + vga_vsync <= '0'; + -- + xc_cmd <= "00"; + xc_d <= (others => 'Z'); + xc_cpld_en <= '0'; + xc_gck0 <= 'Z'; + gclk10 <= 'Z'; + -- led out + --fx2_io(20 downto 13) <= (others => '0'); + + + -- digital clock manager (DCM) + -- to generate higher/other system clock frequencys + dcm_sp_i0 : dcm_sp + generic map ( + startup_wait => true, -- wait with DONE till locked + clkfx_multiply => clk_multiply, + clkfx_divide => clk_divide, + clk_feedback => "1X" + ) + port map ( + clkin => clk_50mhz, + clk0 => dcm_sp_i0_clk0, + clkfx => dcm_sp_i0_clkfx, + clkfb => clk_fb + ); + + clk_fb <= dcm_sp_i0_clk0; + clk <= dcm_sp_i0_clkfx; + + + -- reset synchronizer + -- generate synchronous reset + reset_synchronizer : process(clk, rot_center) + begin + if rot_center = '1' then + reset_shift_reg <= (others => '1'); + elsif rising_edge(clk) then + reset_shift_reg <= reset_shift_reg(reset_shift_reg'high-1 downto 0) & '0'; + end if; + end process; + reset_sync <= reset_shift_reg(reset_shift_reg'high); + + + -- select instance of zpu + zpu_i0_small : if zpu_flavour = zpu_small generate + zpu_i0 : zpu_small1 + generic map ( + addr_w => addr_w_c, + word_size => word_size_c, + clk_freq => clk_frequency * clk_multiply / clk_divide + ) + port map ( + clk_i => clk, -- : in std_logic; -- CPU clock + rst_i => reset_sync, -- : in std_logic; -- Reset + break_o => zpu_i0_break, -- : out std_logic; -- Break executed + dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; -- Debug info + rs232_tx_o => rs232_dce_txd, -- : out std_logic; -- UART Tx + rs232_rx_i => rs232_dce_rxd -- : in std_logic -- UART Rx + ); + end generate zpu_i0_small; + + zpu_i0_medium : if zpu_flavour = zpu_medium generate + zpu_i0 : zpu_med1 + generic map ( + addr_w => addr_w_c, + word_size => word_size_c, + clk_freq => clk_frequency * clk_multiply / clk_divide + ) + port map ( + clk_i => clk, -- : in std_logic; -- CPU clock + rst_i => reset_sync, -- : in std_logic; -- Reset + break_o => zpu_i0_break, -- : out std_logic; -- Break executed + dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; -- Debug info + rs232_tx_o => rs232_dce_txd, -- : out std_logic; -- UART Tx + rs232_rx_i => rs232_dce_rxd -- : in std_logic -- UART Rx + ); + end generate zpu_i0_medium; + + + -- pragma translate_off + stop_simulation <= zpu_i0_break; + + + trace_mod : trace + generic map ( + addr_w => addr_w_c, + word_size => word_size_c, + log_file => "zpu_trace.log" + ) + port map ( + clk_i => clk, + dbg_i => zpu_i0_dbg, + stop_i => zpu_i0_break, + busy_i => '0' + ); + -- pragma translate_on + + + -- switch on all LEDs in case of break + process + begin + wait until rising_edge(clk); + if zpu_i0_break = '1' then + led <= (others => '1'); + end if; + if reset_sync = '1' then + led <= (others => '0'); + end if; + end process; + + + +end architecture rtl; diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top_tb.vhd b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top_tb.vhd new file mode 100644 index 0000000..c774e89 --- /dev/null +++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top_tb.vhd @@ -0,0 +1,278 @@ +-- testbench for Digilent Spartan 3E Starter Board +-- +-- includes "model" for clock generation +-- simulate press on Rotary Pushbutton Switch as reset +-- +-- place models for external components (PHY, SDRAM) in this file +-- + + +library ieee; +use ieee.std_logic_1164.all; + + +entity top_tb is +end entity top_tb; + +architecture testbench of top_tb is + + --------------------------- + -- constant declarations + constant clk_50mhz_period : time := 1 sec / 50_000_000; -- 50 MHz + + + --------------------------- + -- signal declarations + signal simulation_run : boolean := true; + signal tb_stop_simulation : std_logic; + -- + -- Analog-to-Digital Converter (ADC) + signal tb_ad_conv : std_logic; + -- Programmable Gain Amplifier (AMP) + signal tb_amp_cs : std_logic; -- active low chip select + signal tb_amp_dout : std_logic := '1'; + signal tb_amp_shdn : std_logic; -- active high shutdown, reset + -- Pushbuttons (BTN) + signal tb_btn_east : std_logic := '0'; + signal tb_btn_north : std_logic := '0'; + signal tb_btn_south : std_logic := '0'; + signal tb_btn_west : std_logic := '0'; + -- Clock inputs (CLK) + signal tb_clk_50mhz : std_logic := '0'; + signal tb_clk_aux : std_logic := '0'; + signal tb_clk_sma : std_logic := '0'; + -- Digital-to-Analog Converter (DAC) + signal tb_dac_clr : std_logic; -- async, active low reset input + signal tb_dac_cs : std_logic; -- active low chip select, conv start with rising edge + -- 1-Wire Secure EEPROM (DS) + signal tb_ds_wire : std_logic; + -- Ethernet PHY (E) + signal tb_e_col : std_logic := '0'; -- MII collision detect + signal tb_e_crs : std_logic := '0'; -- carrier sense + signal tb_e_mdc : std_logic; -- management clock + signal tb_e_mdio : std_logic; -- management data io + signal tb_e_rx_clk : std_logic := '0'; -- receive clock 25MHz@100BaseTx or 2.5MHz@10Base-T + signal tb_e_rx_dv : std_logic := '0'; -- receive data valid + signal tb_e_rxd : std_logic_vector(3 downto 0) := (others => '0'); + signal tb_e_rx_er : std_logic := '0'; + signal tb_e_tx_clk : std_logic := '0'; -- transmit clock 25MHz@100BaseTx or 2.5MHz@10Base-T + signal tb_e_tx_en : std_logic; -- transmit enable + signal tb_e_txd : std_logic_vector(3 downto 0); + signal tb_e_tx_er : std_logic; + -- FPGA Configuration Mode, INIT_B Pins (FPGA) + signal tb_fpga_m0 : std_logic; + signal tb_fpga_m1 : std_logic; + signal tb_fpga_m2 : std_logic; + signal tb_fpga_init_b : std_logic; + signal tb_fpga_rdwr_b : std_logic := '0'; + signal tb_fpga_hswap : std_logic := '0'; + -- FX2 Connector (FX2) + signal tb_fx2_clkin : std_logic; + signal tb_fx2_clkio : std_logic; + signal tb_fx2_clkout : std_logic; + signal tb_fx2_io : std_logic_vector(40 downto 1); + -- Character LCD (LCD) + signal tb_lcd_e : std_logic; + signal tb_lcd_rs : std_logic; + signal tb_lcd_rw : std_logic; + -- LCD data connections are shared with StrataFlash connections SF_D<11:8> + -- PS/2 Mouse/Keyboard Port (PS2) + signal tb_ps2_clk : std_logic; + signal tb_ps2_data : std_logic; + -- Rotary Pushbutton Switch (ROT) + signal tb_rot_a : std_logic := '0'; + signal tb_rot_b : std_logic := '0'; + signal tb_rot_center : std_logic; -- use as reset + -- RS-232 Serial Ports (RS232) + signal tb_rs232_dce_rxd : std_logic := '1'; + signal tb_rs232_dce_txd : std_logic; + signal tb_rs232_dte_rxd : std_logic := '1'; + signal tb_rs232_dte_txd : std_logic; + -- DDR SDRAM (SD) (I/O Bank 3, VCCO=2.5V) + signal tb_sd_a : std_logic_vector(12 downto 0); -- address inputs + signal tb_sd_dq : std_logic_vector(15 downto 0); -- data io + signal tb_sd_ba : std_logic_vector(1 downto 0); -- bank address inputs + signal tb_sd_ras : std_logic; -- command output + signal tb_sd_cas : std_logic; -- command output + signal tb_sd_we : std_logic; -- command output + signal tb_sd_udm : std_logic; -- data mask + signal tb_sd_ldm : std_logic; -- data mask + signal tb_sd_udqs : std_logic; -- data strobe + signal tb_sd_ldqs : std_logic; -- data strobe + signal tb_sd_cs : std_logic; -- active low chip select + signal tb_sd_cke : std_logic; -- active high clock enable + signal tb_sd_ck_n : std_logic; -- differential clock + signal tb_sd_ck_p : std_logic; -- differential clock + -- Path to allow connection to top DCM connection + signal tb_sd_ck_fb : std_logic; + -- Intel StrataFlash Parallel NOR Flash (SF) + signal tb_sf_a : std_logic_vector(23 downto 0); -- sf_a<24> = fx_io32 :-( + signal tb_sf_byte : std_logic; + signal tb_sf_ce0 : std_logic; + signal tb_sf_d : std_logic_vector(15 downto 1); + signal tb_sf_oe : std_logic; + signal tb_sf_sts : std_logic := '0'; + signal tb_sf_we : std_logic; + -- STMicro SPI serial Flash (SPI) + signal tb_spi_mosi : std_logic; -- master out slave in + signal tb_spi_miso : std_logic := '0'; -- master in slave out + signal tb_spi_sck : std_logic; -- clock + signal tb_spi_ss_b : std_logic; -- active low slave select + signal tb_spi_alt_cs_jp11 : std_logic; + -- Slide Switches (SW) + signal tb_sw : std_logic_vector(3 downto 0) := (others => '0'); + -- VGA Port (VGA) + signal tb_vga_blue : std_logic; + signal tb_vga_green : std_logic; + signal tb_vga_hsync : std_logic; + signal tb_vga_red : std_logic; + signal tb_vga_vsync : std_logic; + -- Xilinx CPLD (XC) + signal tb_xc_cmd : std_logic_vector(1 downto 0); + signal tb_xc_cpld_en : std_logic; + signal tb_xc_d : std_logic_vector(2 downto 0); + signal tb_xc_trig : std_logic := '0'; + signal tb_xc_gck0 : std_logic; + signal tb_gclk10 : std_logic; + + +begin + + + -- generate clock + tb_clk_50mhz <= not tb_clk_50mhz after clk_50mhz_period / 2 when simulation_run; + + -- generate reset + tb_rot_center <= '1', '0' after 6.66 * clk_50mhz_period; + + + -- clock feedback for SD-RAM (on board) + tb_sd_ck_fb <= tb_sd_ck_p; + + + -- dut + top_i0 : entity work.top + port map ( + stop_simulation => tb_stop_simulation, -- : out std_logic; + -- Analog-to-Digital Converter (ADC) + ad_conv => tb_ad_conv, -- : out std_logic; + -- Programmable Gain Amplifier (AMP) + amp_cs => tb_amp_cs, -- : out std_logic; + amp_dout => tb_amp_dout, -- : in std_logic; + amp_shdn => tb_amp_shdn, -- : out std_logic; + -- Pushbuttons (BTN) + btn_east => tb_btn_east, -- : in std_logic; + btn_north => tb_btn_north, -- : in std_logic; + btn_south => tb_btn_south, -- : in std_logic; + btn_west => tb_btn_west, -- : in std_logic; + -- Clock inputs (CLK) + clk_50mhz => tb_clk_50mhz, -- : in std_logic; + clk_aux => tb_clk_aux, -- : in std_logic; + clk_sma => tb_clk_sma, -- : in std_logic; + -- Digital-to-Analog Converter (DAC) + dac_clr => tb_dac_clr, -- : out std_logic; + dac_cs => tb_dac_cs, -- : out std_logic; + -- 1-Wire Secure EEPROM (DS) + ds_wire => tb_ds_wire, -- : inout std_logic; + -- Ethernet PHY (E) + e_col => tb_e_col, -- : in std_logic; + e_crs => tb_e_crs, -- : in std_logic; + e_mdc => tb_e_mdc, -- : out std_logic; + e_mdio => tb_e_mdio, -- : inout std_logic; + e_rx_clk => tb_e_rx_clk, -- : in std_logic; + e_rx_dv => tb_e_rx_dv, -- : in std_logic; + e_rxd => tb_e_rxd, -- : in std_logic_vector(3 downto 0); + e_rx_er => tb_e_rx_er, -- : in std_logic; + e_tx_clk => tb_e_tx_clk, -- : in std_logic; + e_tx_en => tb_e_tx_en, -- : out std_logic; + e_txd => tb_e_txd, -- : out std_logic_vector(3 downto 0); + e_tx_er => tb_e_tx_er, -- : out std_logic; + -- FPGA Configuration Mode, INIT_B Pins (FPGA) + fpga_m0 => tb_fpga_m0, -- : inout std_logic; + fpga_m1 => tb_fpga_m1, -- : inout std_logic; + fpga_m2 => tb_fpga_m2, -- : inout std_logic; + fpga_init_b => tb_fpga_init_b, -- : inout std_logic; + fpga_rdwr_b => tb_fpga_rdwr_b, -- : in std_logic; + fpga_hswap => tb_fpga_hswap, -- : in std_logic; + -- FX2 Connector (FX2) + fx2_clkin => tb_fx2_clkin, -- : inout std_logic; + fx2_clkio => tb_fx2_clkio, -- : inout std_logic; + fx2_clkout => tb_fx2_clkout, -- : inout std_logic; + fx2_io => tb_fx2_io, -- : inout std_logic_vector(40 downto 1); + -- Character LCD (LCD) + lcd_e => tb_lcd_e, -- : out std_logic; + lcd_rs => tb_lcd_rs, -- : out std_logic; + lcd_rw => tb_lcd_rw, -- : out std_logic; + -- LCD data connections are shared with StrataFlash connections SF_D<11:8> + -- PS/2 Mouse/Keyboard Port (PS2) + ps2_clk => tb_ps2_clk, -- : inout std_logic; + ps2_data => tb_ps2_data, -- : inout std_logic; + -- Rotary Pushbutton Switch (ROT) + rot_a => tb_rot_a, -- : in std_logic; + rot_b => tb_rot_b, -- : in std_logic; + rot_center => tb_rot_center, -- : in std_logic; + -- RS-232 Serial Ports (RS232) + rs232_dce_rxd => tb_rs232_dce_rxd, -- : in std_logic; + rs232_dce_txd => tb_rs232_dce_txd, -- : out std_logic; + rs232_dte_rxd => tb_rs232_dte_rxd, -- : in std_logic; + rs232_dte_txd => tb_rs232_dte_txd, -- : out std_logic; + -- DDR SDRAM (SD) (I/O Bank 3, VCCO=2.5V) + sd_a => tb_sd_a, -- : out std_logic_vector(12 downto 0); + sd_dq => tb_sd_dq, -- : inout std_logic_vector(15 downto 0); + sd_ba => tb_sd_ba, -- : out std_logic_vector(1 downto 0); + sd_ras => tb_sd_ras, -- : out std_logic; + sd_cas => tb_sd_cas, -- : out std_logic; + sd_we => tb_sd_we, -- : out std_logic; + sd_udm => tb_sd_udm, -- : out std_logic; + sd_ldm => tb_sd_ldm, -- : out std_logic; + sd_udqs => tb_sd_udqs, -- : inout std_logic; + sd_ldqs => tb_sd_ldqs, -- : inout std_logic; + sd_cs => tb_sd_cs, -- : out std_logic; + sd_cke => tb_sd_cke, -- : out std_logic; + sd_ck_n => tb_sd_ck_n, -- : out std_logic; + sd_ck_p => tb_sd_ck_p, -- : out std_logic; + -- Path to allow connection to top DCM connection + sd_ck_fb => tb_sd_ck_fb, -- : in std_logic; + -- Intel StrataFlash Parallel NOR Flash (SF) + sf_a => tb_sf_a, -- : out std_logic_vector(23 downto 0); + sf_byte => tb_sf_byte, -- : out std_logic; + sf_ce0 => tb_sf_ce0, -- : out std_logic; + sf_d => tb_sf_d, -- : inout std_logic_vector(15 downto 1); + sf_oe => tb_sf_oe, -- : out std_logic; + sf_sts => tb_sf_sts, -- : in std_logic; + sf_we => tb_sf_we, -- : out std_logic; + -- STMicro SPI serial Flash (SPI) + spi_mosi => tb_spi_mosi, -- : out std_logic; + spi_miso => tb_spi_miso, -- : in std_logic; + spi_sck => tb_spi_sck, -- : out std_logic; + spi_ss_b => tb_spi_ss_b, -- : out std_logic; + spi_alt_cs_jp11 => tb_spi_alt_cs_jp11, -- : out std_logic; + -- Slide Switches (SW) + sw => tb_sw, -- : in std_logic_vector(3 downto 0); + -- VGA Port (VGA) + vga_blue => tb_vga_blue, -- : out std_logic; + vga_green => tb_vga_green, -- : out std_logic; + vga_hsync => tb_vga_hsync, -- : out std_logic; + vga_red => tb_vga_red, -- : out std_logic; + vga_vsync => tb_vga_vsync, -- : out std_logic; + -- Xilinx CPLD (XC) + xc_cmd => tb_xc_cmd, -- : out std_logic_vector(1 downto 0); + xc_cpld_en => tb_xc_cpld_en, -- : out std_logic; + xc_d => tb_xc_d, -- : inout std_logic_vector(2 downto 0); + xc_trig => tb_xc_trig, -- : in std_logic; + xc_gck0 => tb_xc_gck0, -- : inout std_logic; + gclk10 => tb_gclk10 -- : inout std_logic + ); + + + -- check for simulation stopping + process (tb_stop_simulation) + begin + if tb_stop_simulation = '1' then + report "Simulation end." severity note; + simulation_run <= false; + end if; + end process; + + +end architecture testbench; |