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Diffstat (limited to 'zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config')
-rw-r--r--zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/altium-livedesign-xc3s1000.ucf397
-rw-r--r--zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.prj19
-rw-r--r--zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.ut29
-rw-r--r--zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.xst56
4 files changed, 501 insertions, 0 deletions
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/altium-livedesign-xc3s1000.ucf b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/altium-livedesign-xc3s1000.ucf
new file mode 100644
index 0000000..ba22ee9
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/altium-livedesign-xc3s1000.ucf
@@ -0,0 +1,397 @@
+############################################################
+# Altium Livedesign Evaluation Board constraints file
+#
+# Familiy: Spartan-3
+# Device: XC3S1000
+# Package: FG456C
+# Speed: -4
+#
+# all banks are powered with 3.3V
+#
+# config pins (M2, M1, M0): 101
+
+############################################################
+## clock/timing constraints
+############################################################
+
+NET "clk_50" period = 50 MHz ;
+
+
+############################################################
+## pin placement constraints
+############################################################
+
+NET "clk_50" LOC = AA12 | IOSTANDARD = LVCMOS33;
+NET "reset_n" LOC = Y17 | IOSTANDARD = LVCMOS33; # low active
+
+# Soft JTAG
+NET "soft_tdo" LOC = D22 | IOSTANDARD = LVCMOS33;
+NET "soft_tms" LOC = E21 | IOSTANDARD = LVCMOS33;
+NET "soft_tdi" LOC = E22 | IOSTANDARD = LVCMOS33;
+NET "soft_tck" LOC = F21 | IOSTANDARD = LVCMOS33;
+
+# SRAM 0
+NET "sram0_a<0>" LOC = L6 | IOSTANDARD = LVCMOS33;
+NET "sram0_a<1>" LOC = K4 | IOSTANDARD = LVCMOS33;
+NET "sram0_a<2>" LOC = H5 | IOSTANDARD = LVCMOS33;
+NET "sram0_a<3>" LOC = G6 | IOSTANDARD = LVCMOS33;
+NET "sram0_a<4>" LOC = F3 | IOSTANDARD = LVCMOS33;
+NET "sram0_a<5>" LOC = G1 | IOSTANDARD = LVCMOS33;
+NET "sram0_a<6>" LOC = G2 | IOSTANDARD = LVCMOS33;
+NET "sram0_a<7>" LOC = K3 | IOSTANDARD = LVCMOS33;
+NET "sram0_a<8>" LOC = T2 | IOSTANDARD = LVCMOS33;
+NET "sram0_a<9>" LOC = T1 | IOSTANDARD = LVCMOS33;
+NET "sram0_a<10>" LOC = U2 | IOSTANDARD = LVCMOS33;
+NET "sram0_a<11>" LOC = V3 | IOSTANDARD = LVCMOS33;
+NET "sram0_a<12>" LOC = V1 | IOSTANDARD = LVCMOS33;
+NET "sram0_a<13>" LOC = W1 | IOSTANDARD = LVCMOS33;
+NET "sram0_a<14>" LOC = V2 | IOSTANDARD = LVCMOS33;
+NET "sram0_a<15>" LOC = V5 | IOSTANDARD = LVCMOS33;
+NET "sram0_a<16>" LOC = V4 | IOSTANDARD = LVCMOS33;
+NET "sram0_a<17>" LOC = U5 | IOSTANDARD = LVCMOS33;
+NET "sram0_a<18>" LOC = U6 | IOSTANDARD = LVCMOS33; # n.c.
+NET "sram0_d<0>" LOC = L4 | IOSTANDARD = LVCMOS33;
+NET "sram0_d<1>" LOC = L3 | IOSTANDARD = LVCMOS33;
+NET "sram0_d<2>" LOC = M5 | IOSTANDARD = LVCMOS33;
+NET "sram0_d<3>" LOC = M4 | IOSTANDARD = LVCMOS33;
+NET "sram0_d<4>" LOC = M3 | IOSTANDARD = LVCMOS33;
+NET "sram0_d<5>" LOC = N4 | IOSTANDARD = LVCMOS33;
+NET "sram0_d<6>" LOC = N3 | IOSTANDARD = LVCMOS33;
+NET "sram0_d<7>" LOC = T5 | IOSTANDARD = LVCMOS33;
+NET "sram0_d<8>" LOC = T4 | IOSTANDARD = LVCMOS33;
+NET "sram0_d<9>" LOC = T6 | IOSTANDARD = LVCMOS33;
+NET "sram0_d<10>" LOC = M6 | IOSTANDARD = LVCMOS33;
+NET "sram0_d<11>" LOC = N2 | IOSTANDARD = LVCMOS33;
+NET "sram0_d<12>" LOC = N1 | IOSTANDARD = LVCMOS33;
+NET "sram0_d<13>" LOC = M2 | IOSTANDARD = LVCMOS33;
+NET "sram0_d<14>" LOC = M1 | IOSTANDARD = LVCMOS33;
+NET "sram0_d<15>" LOC = L2 | IOSTANDARD = LVCMOS33;
+NET "sram0_cs_n" LOC = L5 | IOSTANDARD = LVCMOS33;
+NET "sram0_lb_n" LOC = L1 | IOSTANDARD = LVCMOS33;
+NET "sram0_ub_n" LOC = K2 | IOSTANDARD = LVCMOS33;
+NET "sram0_we_n" LOC = U4 | IOSTANDARD = LVCMOS33;
+NET "sram0_oe_n" LOC = K1 | IOSTANDARD = LVCMOS33;
+
+# SRAM 1
+NET "sram1_a<0>" LOC = K21 | IOSTANDARD = LVCMOS33;
+NET "sram1_a<1>" LOC = K22 | IOSTANDARD = LVCMOS33;
+NET "sram1_a<2>" LOC = K20 | IOSTANDARD = LVCMOS33;
+NET "sram1_a<3>" LOC = G21 | IOSTANDARD = LVCMOS33;
+NET "sram1_a<4>" LOC = G22 | IOSTANDARD = LVCMOS33;
+NET "sram1_a<5>" LOC = M17 | IOSTANDARD = LVCMOS33;
+NET "sram1_a<6>" LOC = L18 | IOSTANDARD = LVCMOS33;
+NET "sram1_a<7>" LOC = K19 | IOSTANDARD = LVCMOS33;
+NET "sram1_a<8>" LOC = V19 | IOSTANDARD = LVCMOS33;
+NET "sram1_a<9>" LOC = W20 | IOSTANDARD = LVCMOS33;
+NET "sram1_a<10>" LOC = W19 | IOSTANDARD = LVCMOS33;
+NET "sram1_a<11>" LOC = Y20 | IOSTANDARD = LVCMOS33;
+NET "sram1_a<12>" LOC = Y21 | IOSTANDARD = LVCMOS33;
+NET "sram1_a<13>" LOC = Y22 | IOSTANDARD = LVCMOS33;
+NET "sram1_a<14>" LOC = W21 | IOSTANDARD = LVCMOS33;
+NET "sram1_a<15>" LOC = W22 | IOSTANDARD = LVCMOS33;
+NET "sram1_a<16>" LOC = V21 | IOSTANDARD = LVCMOS33;
+NET "sram1_a<17>" LOC = V22 | IOSTANDARD = LVCMOS33;
+NET "sram1_a<18>" LOC = V20 | IOSTANDARD = LVCMOS33; # n.c.
+NET "sram1_d<0>" LOC = L21 | IOSTANDARD = LVCMOS33;
+NET "sram1_d<1>" LOC = M22 | IOSTANDARD = LVCMOS33;
+NET "sram1_d<2>" LOC = M21 | IOSTANDARD = LVCMOS33;
+NET "sram1_d<3>" LOC = N22 | IOSTANDARD = LVCMOS33;
+NET "sram1_d<4>" LOC = N21 | IOSTANDARD = LVCMOS33;
+NET "sram1_d<5>" LOC = U20 | IOSTANDARD = LVCMOS33;
+NET "sram1_d<6>" LOC = T22 | IOSTANDARD = LVCMOS33;
+NET "sram1_d<7>" LOC = T21 | IOSTANDARD = LVCMOS33;
+NET "sram1_d<8>" LOC = V18 | IOSTANDARD = LVCMOS33;
+NET "sram1_d<9>" LOC = U19 | IOSTANDARD = LVCMOS33;
+NET "sram1_d<10>" LOC = U18 | IOSTANDARD = LVCMOS33;
+NET "sram1_d<11>" LOC = T18 | IOSTANDARD = LVCMOS33;
+NET "sram1_d<12>" LOC = R18 | IOSTANDARD = LVCMOS33;
+NET "sram1_d<13>" LOC = T17 | IOSTANDARD = LVCMOS33;
+NET "sram1_d<14>" LOC = M18 | IOSTANDARD = LVCMOS33;
+NET "sram1_d<15>" LOC = M20 | IOSTANDARD = LVCMOS33;
+NET "sram1_cs_n" LOC = L22 | IOSTANDARD = LVCMOS33;
+NET "sram1_lb_n" LOC = M19 | IOSTANDARD = LVCMOS33;
+NET "sram1_ub_n" LOC = L20 | IOSTANDARD = LVCMOS33;
+NET "sram1_we_n" LOC = U21 | IOSTANDARD = LVCMOS33;
+NET "sram1_oe_n" LOC = L19 | IOSTANDARD = LVCMOS33;
+
+# RS232
+NET "rs232_rx" LOC = A5 | IOSTANDARD = LVCMOS33;
+NET "rs232_tx" LOC = F7 | IOSTANDARD = LVCMOS33;
+NET "rs232_cts" LOC = F2 | IOSTANDARD = LVCMOS33;
+NET "rs232_rts" LOC = E1 | IOSTANDARD = LVCMOS33;
+
+# 2x PS2 connectors
+NET "mouse_clk" LOC = L17 | IOSTANDARD = LVCMOS33;
+NET "mouse_data" LOC = G18 | IOSTANDARD = LVCMOS33;
+NET "kbd_clk" LOC = F20 | IOSTANDARD = LVCMOS33;
+NET "kbd_data" LOC = G19 | IOSTANDARD = LVCMOS33;
+
+
+# VGA output (2**9 = 512 colors)
+NET "vga_blue<7>" LOC = E14 | IOSTANDARD = LVCMOS33;
+NET "vga_blue<6>" LOC = A13 | IOSTANDARD = LVCMOS33;
+NET "vga_blue<5>" LOC = C13 | IOSTANDARD = LVCMOS33;
+NET "vga_green<7>" LOC = E11 | IOSTANDARD = LVCMOS33;
+NET "vga_green<6>" LOC = C11 | IOSTANDARD = LVCMOS33;
+NET "vga_green<5>" LOC = D10 | IOSTANDARD = LVCMOS33;
+NET "vga_red<7>" LOC = D6 | IOSTANDARD = LVCMOS33;
+NET "vga_red<6>" LOC = D7 | IOSTANDARD = LVCMOS33;
+NET "vga_red<5>" LOC = D9 | IOSTANDARD = LVCMOS33;
+NET "vga_hsync" LOC = A8 | IOSTANDARD = LVCMOS33;
+NET "vga_vsync" LOC = B14 | IOSTANDARD = LVCMOS33;
+
+
+# Stereo Audio out
+NET "audio_r" LOC = U3 | IOSTANDARD = LVCMOS33;
+NET "audio_l" LOC = W3 | IOSTANDARD = LVCMOS33;
+
+
+# GPIO DIP switches 7..0 left..right, low active
+NET "switch_n<0>" LOC = Y6 | IOSTANDARD = LVCMOS33;
+NET "switch_n<1>" LOC = V6 | IOSTANDARD = LVCMOS33;
+NET "switch_n<2>" LOC = U7 | IOSTANDARD = LVCMOS33;
+NET "switch_n<3>" LOC = AA4 | IOSTANDARD = LVCMOS33;
+NET "switch_n<4>" LOC = AB4 | IOSTANDARD = LVCMOS33;
+NET "switch_n<5>" LOC = AA5 | IOSTANDARD = LVCMOS33;
+NET "switch_n<6>" LOC = AB5 | IOSTANDARD = LVCMOS33;
+NET "switch_n<7>" LOC = AA6 | IOSTANDARD = LVCMOS33;
+
+# GPIO push buttons, low active
+NET "button_n<5>" LOC = C21 | IOSTANDARD = LVCMOS33;
+NET "button_n<4>" LOC = B20 | IOSTANDARD = LVCMOS33;
+NET "button_n<3>" LOC = A15 | IOSTANDARD = LVCMOS33;
+NET "button_n<2>" LOC = B6 | IOSTANDARD = LVCMOS33;
+NET "button_n<1>" LOC = C1 | IOSTANDARD = LVCMOS33;
+NET "button_n<0>" LOC = D1 | IOSTANDARD = LVCMOS33;
+
+# GPIO LEDs
+NET "led<7>" LOC = W6 | IOSTANDARD = LVCMOS33;
+NET "led<6>" LOC = Y5 | IOSTANDARD = LVCMOS33;
+NET "led<5>" LOC = W5 | IOSTANDARD = LVCMOS33;
+NET "led<4>" LOC = W4 | IOSTANDARD = LVCMOS33;
+NET "led<3>" LOC = Y3 | IOSTANDARD = LVCMOS33;
+NET "led<2>" LOC = Y2 | IOSTANDARD = LVCMOS33;
+NET "led<1>" LOC = Y1 | IOSTANDARD = LVCMOS33;
+NET "led<0>" LOC = W2 | IOSTANDARD = LVCMOS33;
+
+# seven segment display (5=left 0=right)
+#
+# segment assignment:
+# .ABCDEFG
+# 76543210
+NET "dig0_seg<7>" LOC = E20 | IOSTANDARD = LVCMOS33;
+NET "dig0_seg<6>" LOC = C22 | IOSTANDARD = LVCMOS33;
+NET "dig0_seg<5>" LOC = E18 | IOSTANDARD = LVCMOS33;
+NET "dig0_seg<4>" LOC = D20 | IOSTANDARD = LVCMOS33;
+NET "dig0_seg<3>" LOC = D21 | IOSTANDARD = LVCMOS33;
+NET "dig0_seg<2>" LOC = E19 | IOSTANDARD = LVCMOS33;
+NET "dig0_seg<1>" LOC = G17 | IOSTANDARD = LVCMOS33;
+NET "dig0_seg<0>" LOC = F19 | IOSTANDARD = LVCMOS33;
+
+NET "dig1_seg<7>" LOC = F17 | IOSTANDARD = LVCMOS33;
+NET "dig1_seg<6>" LOC = D18 | IOSTANDARD = LVCMOS33;
+NET "dig1_seg<5>" LOC = B19 | IOSTANDARD = LVCMOS33;
+NET "dig1_seg<4>" LOC = C18 | IOSTANDARD = LVCMOS33;
+NET "dig1_seg<3>" LOC = C19 | IOSTANDARD = LVCMOS33;
+NET "dig1_seg<2>" LOC = C20 | IOSTANDARD = LVCMOS33;
+NET "dig1_seg<1>" LOC = F18 | IOSTANDARD = LVCMOS33;
+NET "dig1_seg<0>" LOC = D19 | IOSTANDARD = LVCMOS33;
+
+NET "dig2_seg<7>" LOC = A19 | IOSTANDARD = LVCMOS33;
+NET "dig2_seg<6>" LOC = E17 | IOSTANDARD = LVCMOS33;
+NET "dig2_seg<5>" LOC = C17 | IOSTANDARD = LVCMOS33;
+NET "dig2_seg<4>" LOC = D17 | IOSTANDARD = LVCMOS33;
+NET "dig2_seg<3>" LOC = B15 | IOSTANDARD = LVCMOS33;
+NET "dig2_seg<2>" LOC = A18 | IOSTANDARD = LVCMOS33;
+NET "dig2_seg<1>" LOC = B18 | IOSTANDARD = LVCMOS33;
+NET "dig2_seg<0>" LOC = B17 | IOSTANDARD = LVCMOS33;
+
+NET "dig3_seg<7>" LOC = D15 | IOSTANDARD = LVCMOS33;
+NET "dig3_seg<6>" LOC = E13 | IOSTANDARD = LVCMOS33;
+NET "dig3_seg<5>" LOC = B13 | IOSTANDARD = LVCMOS33;
+NET "dig3_seg<4>" LOC = D13 | IOSTANDARD = LVCMOS33;
+NET "dig3_seg<3>" LOC = D14 | IOSTANDARD = LVCMOS33;
+NET "dig3_seg<2>" LOC = A14 | IOSTANDARD = LVCMOS33;
+NET "dig3_seg<1>" LOC = E16 | IOSTANDARD = LVCMOS33;
+NET "dig3_seg<0>" LOC = E15 | IOSTANDARD = LVCMOS33;
+
+NET "dig4_seg<7>" LOC = D11 | IOSTANDARD = LVCMOS33;
+NET "dig4_seg<6>" LOC = E9 | IOSTANDARD = LVCMOS33;
+NET "dig4_seg<5>" LOC = A10 | IOSTANDARD = LVCMOS33;
+NET "dig4_seg<4>" LOC = B9 | IOSTANDARD = LVCMOS33;
+NET "dig4_seg<3>" LOC = A9 | IOSTANDARD = LVCMOS33;
+NET "dig4_seg<2>" LOC = C10 | IOSTANDARD = LVCMOS33;
+NET "dig4_seg<1>" LOC = A12 | IOSTANDARD = LVCMOS33;
+NET "dig4_seg<0>" LOC = B10 | IOSTANDARD = LVCMOS33;
+
+NET "dig5_seg<7>" LOC = C7 | IOSTANDARD = LVCMOS33;
+NET "dig5_seg<6>" LOC = A4 | IOSTANDARD = LVCMOS33;
+NET "dig5_seg<5>" LOC = B5 | IOSTANDARD = LVCMOS33;
+NET "dig5_seg<4>" LOC = E6 | IOSTANDARD = LVCMOS33;
+NET "dig5_seg<3>" LOC = C5 | IOSTANDARD = LVCMOS33;
+NET "dig5_seg<2>" LOC = E7 | IOSTANDARD = LVCMOS33;
+NET "dig5_seg<1>" LOC = B8 | IOSTANDARD = LVCMOS33;
+NET "dig5_seg<0>" LOC = C6 | IOSTANDARD = LVCMOS33;
+
+
+# Header A (left)
+NET "header_a<2>" LOC = V7 | IOSTANDARD = LVCMOS33;
+NET "header_a<3>" LOC = AA8 | IOSTANDARD = LVCMOS33;
+NET "header_a<4>" LOC = AB8 | IOSTANDARD = LVCMOS33;
+NET "header_a<5>" LOC = V8 | IOSTANDARD = LVCMOS33;
+NET "header_a<6>" LOC = Y10 | IOSTANDARD = LVCMOS33;
+NET "header_a<7>" LOC = V9 | IOSTANDARD = LVCMOS33;
+NET "header_a<8>" LOC = W9 | IOSTANDARD = LVCMOS33;
+NET "header_a<9>" LOC = AA10 | IOSTANDARD = LVCMOS33;
+NET "header_a<10>" LOC = AB10 | IOSTANDARD = LVCMOS33;
+NET "header_a<11>" LOC = W10 | IOSTANDARD = LVCMOS33;
+NET "header_a<12>" LOC = AB11 | IOSTANDARD = LVCMOS33;
+NET "header_a<13>" LOC = U11 | IOSTANDARD = LVCMOS33;
+NET "header_a<14>" LOC = AB13 | IOSTANDARD = LVCMOS33;
+NET "header_a<15>" LOC = AA13 | IOSTANDARD = LVCMOS33;
+NET "header_a<16>" LOC = V10 | IOSTANDARD = LVCMOS33;
+NET "header_a<17>" LOC = U10 | IOSTANDARD = LVCMOS33;
+NET "header_a<18>" LOC = W13 | IOSTANDARD = LVCMOS33;
+NET "header_a<19>" LOC = Y13 | IOSTANDARD = LVCMOS33;
+
+# Header B (right)
+NET "header_b<2>" LOC = V14 | IOSTANDARD = LVCMOS33;
+NET "header_b<3>" LOC = V13 | IOSTANDARD = LVCMOS33;
+NET "header_b<4>" LOC = AA15 | IOSTANDARD = LVCMOS33;
+NET "header_b<5>" LOC = W14 | IOSTANDARD = LVCMOS33;
+NET "header_b<6>" LOC = AB15 | IOSTANDARD = LVCMOS33;
+NET "header_b<7>" LOC = Y16 | IOSTANDARD = LVCMOS33;
+NET "header_b<8>" LOC = AA17 | IOSTANDARD = LVCMOS33;
+NET "header_b<9>" LOC = AA18 | IOSTANDARD = LVCMOS33;
+NET "header_b<10>" LOC = AB18 | IOSTANDARD = LVCMOS33;
+NET "header_b<11>" LOC = Y18 | IOSTANDARD = LVCMOS33;
+NET "header_b<12>" LOC = Y19 | IOSTANDARD = LVCMOS33;
+NET "header_b<13>" LOC = AB20 | IOSTANDARD = LVCMOS33;
+NET "header_b<14>" LOC = AA20 | IOSTANDARD = LVCMOS33;
+NET "header_b<15>" LOC = U16 | IOSTANDARD = LVCMOS33;
+NET "header_b<16>" LOC = V16 | IOSTANDARD = LVCMOS33;
+NET "header_b<17>" LOC = V17 | IOSTANDARD = LVCMOS33;
+NET "header_b<18>" LOC = W16 | IOSTANDARD = LVCMOS33;
+NET "header_b<19>" LOC = W17 | IOSTANDARD = LVCMOS33;
+
+# usused pins
+CONFIG PROHIBIT = A3;
+CONFIG PROHIBIT = A7;
+CONFIG PROHIBIT = A11;
+CONFIG PROHIBIT = A16;
+CONFIG PROHIBIT = AA3;
+CONFIG PROHIBIT = AA7;
+CONFIG PROHIBIT = AA9;
+CONFIG PROHIBIT = AA11;
+CONFIG PROHIBIT = AA14;
+CONFIG PROHIBIT = AA16;
+CONFIG PROHIBIT = AA19;
+CONFIG PROHIBIT = AB7;
+CONFIG PROHIBIT = AB9;
+CONFIG PROHIBIT = AB12;
+CONFIG PROHIBIT = AB14;
+CONFIG PROHIBIT = AB16;
+CONFIG PROHIBIT = AB19;
+CONFIG PROHIBIT = B4;
+CONFIG PROHIBIT = B7;
+CONFIG PROHIBIT = B12;
+CONFIG PROHIBIT = B11;
+CONFIG PROHIBIT = B16;
+CONFIG PROHIBIT = C2;
+CONFIG PROHIBIT = C3;
+CONFIG PROHIBIT = C4;
+CONFIG PROHIBIT = C12;
+CONFIG PROHIBIT = C16;
+CONFIG PROHIBIT = D2;
+CONFIG PROHIBIT = D3;
+CONFIG PROHIBIT = D4;
+CONFIG PROHIBIT = D5;
+CONFIG PROHIBIT = D8;
+CONFIG PROHIBIT = D12;
+CONFIG PROHIBIT = D16;
+CONFIG PROHIBIT = E2;
+CONFIG PROHIBIT = E3;
+CONFIG PROHIBIT = E8;
+CONFIG PROHIBIT = E4;
+CONFIG PROHIBIT = E5;
+CONFIG PROHIBIT = F4;
+CONFIG PROHIBIT = E10;
+CONFIG PROHIBIT = E12;
+CONFIG PROHIBIT = F12;
+CONFIG PROHIBIT = F5;
+CONFIG PROHIBIT = F13;
+CONFIG PROHIBIT = F6;
+CONFIG PROHIBIT = F9;
+CONFIG PROHIBIT = F10;
+CONFIG PROHIBIT = F16;
+CONFIG PROHIBIT = F11;
+CONFIG PROHIBIT = F14;
+CONFIG PROHIBIT = G3;
+CONFIG PROHIBIT = G4;
+CONFIG PROHIBIT = G5;
+CONFIG PROHIBIT = G20;
+CONFIG PROHIBIT = H1;
+CONFIG PROHIBIT = H2;
+CONFIG PROHIBIT = H4;
+CONFIG PROHIBIT = H18;
+CONFIG PROHIBIT = H19;
+CONFIG PROHIBIT = H21;
+CONFIG PROHIBIT = H22;
+CONFIG PROHIBIT = J1;
+CONFIG PROHIBIT = J2;
+CONFIG PROHIBIT = J4;
+CONFIG PROHIBIT = J5;
+CONFIG PROHIBIT = J6;
+CONFIG PROHIBIT = J17;
+CONFIG PROHIBIT = J18;
+CONFIG PROHIBIT = J19;
+CONFIG PROHIBIT = J21;
+CONFIG PROHIBIT = J22;
+CONFIG PROHIBIT = K5;
+CONFIG PROHIBIT = K6;
+CONFIG PROHIBIT = K17;
+CONFIG PROHIBIT = K18;
+CONFIG PROHIBIT = N5;
+CONFIG PROHIBIT = N6;
+CONFIG PROHIBIT = N17;
+CONFIG PROHIBIT = N18;
+CONFIG PROHIBIT = N19;
+CONFIG PROHIBIT = N20;
+CONFIG PROHIBIT = P1;
+CONFIG PROHIBIT = P2;
+CONFIG PROHIBIT = P4;
+CONFIG PROHIBIT = P5;
+CONFIG PROHIBIT = P6;
+CONFIG PROHIBIT = P17;
+CONFIG PROHIBIT = P18;
+CONFIG PROHIBIT = P19;
+CONFIG PROHIBIT = P21;
+CONFIG PROHIBIT = P22;
+CONFIG PROHIBIT = R1;
+CONFIG PROHIBIT = R2;
+CONFIG PROHIBIT = R4;
+CONFIG PROHIBIT = R5;
+CONFIG PROHIBIT = R19;
+CONFIG PROHIBIT = R21;
+CONFIG PROHIBIT = R22;
+CONFIG PROHIBIT = T3;
+CONFIG PROHIBIT = T19;
+CONFIG PROHIBIT = T20;
+CONFIG PROHIBIT = U9;
+CONFIG PROHIBIT = U12;
+CONFIG PROHIBIT = U13;
+CONFIG PROHIBIT = U14;
+CONFIG PROHIBIT = U17;
+CONFIG PROHIBIT = V11;
+CONFIG PROHIBIT = V12;
+CONFIG PROHIBIT = V15;
+CONFIG PROHIBIT = W7;
+CONFIG PROHIBIT = W8;
+CONFIG PROHIBIT = W11;
+CONFIG PROHIBIT = W12;
+CONFIG PROHIBIT = W15;
+CONFIG PROHIBIT = W18;
+CONFIG PROHIBIT = Y4;
+CONFIG PROHIBIT = Y7;
+CONFIG PROHIBIT = Y11;
+CONFIG PROHIBIT = Y12;
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.prj b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.prj
new file mode 100644
index 0000000..24120d5
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.prj
@@ -0,0 +1,19 @@
+vhdl work ../top.vhd
+vhdl zpu ../../../zpu_pkg.vhdl
+vhdl zpu ../../../zpu_small.vhdl
+vhdl zpu ../../../zpu_medium.vhdl
+vhdl zpu ../../../roms/rom_pkg.vhdl
+#vhdl zpu ../../../roms/hello_dbram.vhdl
+#vhdl zpu ../../../roms/hello_bram.vhdl
+vhdl zpu ../../../roms/dmips_dbram.vhdl
+vhdl zpu ../../../roms/dmips_bram.vhdl
+vhdl zpu ../../../helpers/zpu_small1.vhdl
+vhdl zpu ../../../helpers/zpu_med1.vhdl
+vhdl zpu ../../../devices/txt_util.vhdl
+vhdl zpu ../../../devices/phi_io.vhdl
+vhdl zpu ../../../devices/timer.vhdl
+vhdl zpu ../../../devices/gpio.vhdl
+vhdl zpu ../../../devices/rx_unit.vhdl
+vhdl zpu ../../../devices/tx_unit.vhdl
+vhdl zpu ../../../devices/br_gen.vhdl
+vhdl zpu ../../../devices/trace.vhdl
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.ut b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.ut
new file mode 100644
index 0000000..765a6f3
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.ut
@@ -0,0 +1,29 @@
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g ConfigRate:6
+-g CclkPin:PullUp
+-g M0Pin:PullUp
+-g M1Pin:PullUp
+-g M2Pin:PullUp
+-g ProgPin:PullUp
+-g DonePin:PullUp
+-g HswapenPin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g DCMShutdown:Disable
+-g DCIUpdateMode:AsRequired
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Match_cycle:Auto
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.xst b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.xst
new file mode 100644
index 0000000..14873ea
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.xst
@@ -0,0 +1,56 @@
+set -tmpdir "tmp"
+set -xsthdpdir "xst"
+run
+-ifn ../synthesis_config/top.prj
+-ifmt mixed
+-ofn top
+-ofmt NGC
+-p xc3s1000-4-fg456
+-top top
+-opt_mode Speed
+-opt_level 1
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract Yes
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-auto_bram_packing NO
+-mux_extract Yes
+-resource_sharing YES
+-async_to_sync NO
+-mult_style Auto
+-iobuf YES
+-max_fanout 500
+-bufg 8
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Yes
+-use_sync_set Yes
+-use_sync_reset Yes
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
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