diff options
Diffstat (limited to 'zpu/hdl/example_ghdl')
| -rw-r--r-- | zpu/hdl/example_ghdl/README | 44 | ||||
| -rw-r--r-- | zpu/hdl/example_ghdl/dmipssmalltrace_ghdl.sh | 24 | ||||
| -rw-r--r-- | zpu/hdl/example_ghdl/dmipstrace_ghdl.sh | 24 | ||||
| -rw-r--r-- | zpu/hdl/example_ghdl/ghdl_import.sh | 16 | ||||
| -rw-r--r-- | zpu/hdl/example_ghdl/ghdl_make.sh | 4 | ||||
| -rw-r--r-- | zpu/hdl/example_ghdl/ghdl_options.sh | 2 | ||||
| -rw-r--r-- | zpu/hdl/example_ghdl/simzpu_medium_ghdl.sh | 24 |
7 files changed, 138 insertions, 0 deletions
diff --git a/zpu/hdl/example_ghdl/README b/zpu/hdl/example_ghdl/README new file mode 100644 index 0000000..a098c0c --- /dev/null +++ b/zpu/hdl/example_ghdl/README @@ -0,0 +1,44 @@ +This directory contains a quick setup of the helloworld example for
+the GHDL simulator.
+
+ http://ghdl.free.fr/
+
+Compiled by Arnim Laeuger, 17-Apr-2008.
+Removed ROC/unisim dependency 16-Jun-2008.
+
+Compiling the example
+---------------------
+
+Make all shell scripts executable:
+ $ chmod +x *.sh
+
+On Linux, convert files from DOS format:
+ $ dos2unix *.sh
+
+You need to import the project sources once by running
+ $ ./ghdl_import.sh
+
+Compilation (using GHDL's make feature) is invoked by
+ $ ./ghdl_make.sh
+
+Whenever the VHDL sources change, it's enough to execute ghdl_make.sh. GHDL
+will trace the dependencies and will rebuild only the modified sources.
+
+
+Simulation
+----------
+
+Simulation finally happens by running the fpga_top executable generated by the
+compilation step. Don't forget to set a stop time or the testbench might run
+forever:
+
+ $ ./fpga_top --stop-time=2100us
+
+The log.txt and trace.txt files are generated as simulation progresses. They
+should be compared to the files given in the example directory.
+
+Waveforms can be obtained by specifying the ghw file name:
+
+ $ ./fpga_top --stop-time=1ms --wave=zpu.ghw
+
+They can be inspected with gtkwave from http://home.nc.rr.com/gtkwave/.
diff --git a/zpu/hdl/example_ghdl/dmipssmalltrace_ghdl.sh b/zpu/hdl/example_ghdl/dmipssmalltrace_ghdl.sh new file mode 100644 index 0000000..b3be1a6 --- /dev/null +++ b/zpu/hdl/example_ghdl/dmipssmalltrace_ghdl.sh @@ -0,0 +1,24 @@ +#!/bin/sh
+
+IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work"
+MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding"
+
+if test ! -e work; then
+ echo "Building work library..."
+ mkdir work
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/zpu_config.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpupkg.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/txt_util.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/sim_small_fpga_top.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpu_core_small.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/bram_dmips.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/timer.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/io.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/trace.vhd
+fi
+
+echo "Compiling design..."
+if ghdl -m ${MAKE_OPTIONS} fpga_top; then
+ echo "Compilation finished, start simulation with"
+ echo " ./fpga_top --stop-time=1ms"
+fi
diff --git a/zpu/hdl/example_ghdl/dmipstrace_ghdl.sh b/zpu/hdl/example_ghdl/dmipstrace_ghdl.sh new file mode 100644 index 0000000..53474d4 --- /dev/null +++ b/zpu/hdl/example_ghdl/dmipstrace_ghdl.sh @@ -0,0 +1,24 @@ +#!/bin/sh
+
+IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work"
+MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding"
+
+if test ! -e work; then
+ echo "Building work library..."
+ mkdir work
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/example_medium/zpu_config_trace.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpupkg.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/txt_util.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/example_medium/sim_fpga_top.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpu_core.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/example_medium/dram_dmips.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/timer.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/io.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/trace.vhd
+fi
+
+echo "Compiling design..."
+if ghdl -m ${MAKE_OPTIONS} fpga_top; then
+ echo "Compilation finished, start simulation with"
+ echo " ./fpga_top --stop-time=2500us"
+fi
diff --git a/zpu/hdl/example_ghdl/ghdl_import.sh b/zpu/hdl/example_ghdl/ghdl_import.sh new file mode 100644 index 0000000..b1c2713 --- /dev/null +++ b/zpu/hdl/example_ghdl/ghdl_import.sh @@ -0,0 +1,16 @@ +#!/bin/sh
+. ghdl_options.sh
+
+mkdir -p work
+ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/zpu_config.vhd
+ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpupkg.vhd
+ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/interrupt.vhd
+# to execute helloworld comment interrupt.vhd above
+# and edit sim_small_fpga_top.vhd to never assert interrupts
+#ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/helloworld.vhd
+ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/txt_util.vhd
+ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/trace.vhd
+ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpu_core_small.vhd
+ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/io.vhd
+ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/timer.vhd
+ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/sim_small_fpga_top.vhd
diff --git a/zpu/hdl/example_ghdl/ghdl_make.sh b/zpu/hdl/example_ghdl/ghdl_make.sh new file mode 100644 index 0000000..948b100 --- /dev/null +++ b/zpu/hdl/example_ghdl/ghdl_make.sh @@ -0,0 +1,4 @@ +#!/bin/sh
+. ghdl_options.sh
+
+ghdl -m ${MAKE_OPTIONS} fpga_top
diff --git a/zpu/hdl/example_ghdl/ghdl_options.sh b/zpu/hdl/example_ghdl/ghdl_options.sh new file mode 100644 index 0000000..aba231c --- /dev/null +++ b/zpu/hdl/example_ghdl/ghdl_options.sh @@ -0,0 +1,2 @@ +IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work"
+MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding"
diff --git a/zpu/hdl/example_ghdl/simzpu_medium_ghdl.sh b/zpu/hdl/example_ghdl/simzpu_medium_ghdl.sh new file mode 100644 index 0000000..8ba5078 --- /dev/null +++ b/zpu/hdl/example_ghdl/simzpu_medium_ghdl.sh @@ -0,0 +1,24 @@ +#!/bin/sh
+
+IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work"
+MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding"
+
+if test ! -e work; then
+ echo "Building work library..."
+ mkdir work
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/example_medium/zpu_config_trace.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpupkg.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/txt_util.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/example_medium/sim_fpga_top.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpu_core.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/example_medium/dram_hello.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/timer.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/io.vhd
+ ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/trace.vhd
+fi
+
+echo "Compiling design..."
+if ghdl -m ${MAKE_OPTIONS} fpga_top; then
+ echo "Compilation finished, start simulation with"
+ echo " ./fpga_top --stop-time=1ms"
+fi
|
