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Diffstat (limited to 'tool_makefile/Makefile.synthesis.digilent_s3e')
| -rw-r--r-- | tool_makefile/Makefile.synthesis.digilent_s3e | 203 |
1 files changed, 203 insertions, 0 deletions
diff --git a/tool_makefile/Makefile.synthesis.digilent_s3e b/tool_makefile/Makefile.synthesis.digilent_s3e new file mode 100644 index 0000000..ace90ab --- /dev/null +++ b/tool_makefile/Makefile.synthesis.digilent_s3e @@ -0,0 +1,203 @@ +# +# $HeadURL: https://svn.fzd.de/repo/concast/FWF_Projects/FWKE/beam_position_monitor/hardware/board_sp601_amba/synthese/Makefile $ +# $Date: 2011-11-18 08:42:44 +0100 (Fr, 18. Nov 2011) $ +# $Author: lange $ +# $Revision: 1257 $ +# + +MODULE = top +SPEEDGRADE = 4 +DEVICE = xc3s500e-fg320-$(SPEEDGRADE) +UCF_FILE = s3estarter.ucf +CORES = ../cores/ +SOFTWARE = ../software +BMM_FILE = zpu_i0_memory.bmm + +BUILDDIR = isebuild +DATE = $(shell date +"%Y-%m-%d__%H_%M") +LOGFILE = synthesis_log_$(DATE).txt +export XST_LOGFILE := $(LOGFILE) + + +all: + @echo "check - look for timing and other synthesis issues" + @echo "xst - generate ngc file (netlist, replaces edif and netlist constrains)" + @echo "translate - generate ngd file (native generic database [reduced to primitives])" + @echo "map - generate ncd file (native ciruit description)" + @echo "par - place&route ncd file (design implementation)" + @echo "trace - generate timing report" + @echo "bitgen - generate bit file (ncd -> bit)" + @echo "update - update bitstream with elf file" + @echo "program - program fpga with bit file" + @echo "genmcs - genrate mcs file" + @echo "progspi - program spi flash with mcs file" + @echo "clean" + @echo "..." + @echo "testflow - update bitgen update program check" + @echo "finalflow - update bitgen update progspi check" + +testflow: + time $(MAKE) software bitgen update program check 2>&1 | tee $(XST_LOGFILE) + +finalflow: + time $(MAKE) software bitgen update progspi check 2>&1 | tee $(XST_LOGFILE) + + +check: + @echo -e "Timing score: " + @grep --with-filename "Timing Score" $(BUILDDIR)/*.par + @echo -e "\nUnwanted Latches (737): " + @grep --with-filename "WARNING:Xst:737" $(BUILDDIR)/*.syr || echo -n + @echo -e "\nUnassigned signals (653): " + @grep --with-filename "WARNING:Xst:653" $(BUILDDIR)/*.syr || echo -n + @echo -e "\nCombinatoric loops (2170): " + @grep --with-filename "WARNING:Xst:2170" $(BUILDDIR)/*.syr || echo -n + @echo -e "\nGated clocks (372): " + @grep --with-filename "WARNING:PhysDesignRules:372" $(BUILDDIR)/*.bgn || echo -n + + +software: + ### + ############################################################################# + ### (re)compile software + ### + test ! -d $(SOFTWARE) || make all --directory $(SOFTWARE) + + +update: $(BUILDDIR)/$(MODULE).bit + ### + ############################################################################# + ### update the bitfile + ### + test ! -d $(SOFTWARE) || data2mem -bm $(BMM_FILE) -bd $(SOFTWARE)/*.elf -bt $(BUILDDIR)/$(MODULE).bit -o b $(MODULE)_update.bit + test -d $(SOFTWARE) || cp $(BUILDDIR)/$(MODULE).bit $(MODULE)_update.bit + + +program: + ### + ############################################################################# + ### configure FPGA + ### + impact -batch program_fpga.cmd + + +genmcs: $(MODULE)_update.mcs + +$(MODULE)_update.mcs: $(MODULE)_update.bit + ### + ############################################################################# + ### generate flash file + ### + promgen -spi -p mcs -w -o $(MODULE)_update.mcs -s 8192 -u 0 $(MODULE)_update.bit + + +progspi: genmcs + ### + ############################################################################# + ### program flash + ### + impact -batch program_spi.cmd + + +clean: + rm -f $(MODULE).prj + rm -f *.log + rm -f _impact.cmd + rm -f *.cfi + rm -f *.prm + rm -rf $(BUILDDIR) + + +dir: $(MODULE).prj + ### + ############################################################################# + ### generate build directory + ### + mkdir -p $(BUILDDIR) + mkdir -p $(BUILDDIR)/projnav.tmp + + + +$(MODULE).prj: ../simulation/vhdl_files.txt + ### + ############################################################################# + ### generate project file + ### + grep --invert rtl_tb ../simulation/vhdl_files.txt | grep --invert "^$$" | awk '{printf "vhdl %s %s\n",$$1,$$2}' > $(MODULE).prj + + +xst: $(MODULE).ngc +translate: $(MODULE).ngd +map: $(MODULE)_map.ncd +par: $(MODULE).ncd + + +hw_timestamp: + ### + ############################################################################# + #### update hw timestamp + ### + test ! -f ../rtl/Makefile || make --directory ../rtl + +$(MODULE).ngc: dir hw_timestamp + ### + ############################################################################# + ### synthesis + ### + cd $(BUILDDIR) ; xst -ifn ../$(MODULE).xst -ofn $(MODULE).syr + + +$(MODULE).ngd: $(MODULE).ngc $(UCF_FILE) + ### + ############################################################################# + ### translate + ### + cd $(BUILDDIR) ; ngdbuild -dd _ngo -nt timestamp -uc ../$(UCF_FILE) -p $(DEVICE) -sd ../$(CORES) $(MODULE).ngc $(MODULE).ngd + +$(MODULE)_map.ncd: $(MODULE).ngd + ### + ############################################################################# + ### map + ### + @# explanation of map parameters: + @# -p part number + @# -mt multi-threading + @# -w overwrite existing files + @# -logic_opt logic optimization + @# -ol overall effor level (std|high) + @# -t placer cost table + @# -xt extra placer cost table + @# -register_duplication duplicate registers + @# -global_opt Global Optimization (off|speed|area|power) + @# -ir ignore RLOCs + @# -pr pack registers in IO (off|i|o|b) + @# -lc lut combining (auto|area|off) + @# -power Virtex 6 Power Optimization (on|off|high|xe) + @# -detail Generate Detailed MAP Report + @# -o Output File Name + @# -bp enables block RAM mapping + cd $(BUILDDIR) ; export XIL_PAR_DESIGN_CHECK_VERBOSE=1; map -p $(DEVICE) -cm speed -detail -ir off -pr off -c 100 -o $(MODULE)_map.ncd $(MODULE).ngd $(MODULE).pcf + + +$(MODULE).ncd: $(MODULE)_map.ncd + ### + ############################################################################# + ### place & route + ### + cd $(BUILDDIR) ; par -w -ol high -t 1 $(MODULE)_map.ncd $(MODULE).ncd $(MODULE).pcf + +trace: + cd $(BUILDDIR) ; trce -e -a -u -s $(SPEEDGRADE) -xml $(MODULE).twx $(MODULE).ncd -o $(MODULE).twr $(MODULE).pcf + +tracefast: + cd $(BUILDDIR) ; trce -v 12 -s $(SPEEDGRADE) -fastpaths -xml $(MODULE).twx -o $(MODULE).twr $(MODULE).ncd $(MODULE).pcf + + +bitgen: $(MODULE).ncd + ### + ############################################################################# + ### generate bitfile + ### + cd $(BUILDDIR) ; bitgen -f ../$(MODULE).ut $(MODULE).ncd + + |
