diff options
Diffstat (limited to 'mig_test/vhdl_files.txt')
-rw-r--r-- | mig_test/vhdl_files.txt | 93 |
1 files changed, 93 insertions, 0 deletions
diff --git a/mig_test/vhdl_files.txt b/mig_test/vhdl_files.txt new file mode 100644 index 0000000..a94534a --- /dev/null +++ b/mig_test/vhdl_files.txt @@ -0,0 +1,93 @@ +work rtl/top.vhd +work rtl/box.vhd +work rtl/timestamp.vhd +work rtl_tb/top_tb.vhd + +grlib ../grlib/rtl/ahbctrl.vhd +grlib ../grlib/rtl/amba.vhd +grlib ../grlib/rtl/apbctrl.vhd +grlib ../grlib/rtl/config.vhd +grlib ../grlib/rtl/devices.vhd +grlib ../grlib/rtl/stdlib.vhd +grlib ../grlib/rtl/testlib.vhd +grlib ../grlib/rtl/util.vhd +grlib ../grlib/rtl/version.vhd +grlib ../grlib/rtl_tb/stdio.vhd + +hzdr ../hzdr/rtl/devices_hzdr.vhd +hzdr ../hzdr/rtl/component_package.vhd +hzdr ../hzdr/rtl/debug_con_apb.vhd + +gaisler ../gaisler/rtl/ahbdpram.vhd +gaisler ../gaisler/rtl/ahbram.vhd +gaisler ../gaisler/rtl/apbuart.vhd +gaisler ../gaisler/rtl/grgpio.vhd +gaisler ../gaisler/rtl/uart.vhd +gaisler ../gaisler/rtl/gptimer.vhd +gaisler ../gaisler/rtl/misc.vhd +gaisler ../gaisler/rtl/net.vhd +gaisler ../gaisler/rtl/memctrl.vhd +gaisler ../gaisler/rtl/memoryctrl.vhd +gaisler ../gaisler/rtl_tb/sim.vhd +gaisler ../gaisler/rtl/greth.vhd +gaisler ../gaisler/rtl/ethernet_mac.vhd + +eth ../gaisler/rtl/greth_pkg.vhd +eth ../gaisler/rtl/greth_rx.vhd +eth ../gaisler/rtl/greth_tx.vhd +eth ../gaisler/rtl/grethc.vhd +eth ../gaisler/rtl/eth_ahb_mst.vhd +eth ../gaisler/rtl/eth_rstgen.vhd +eth ../gaisler/rtl/ethcomp.vhd + +techmap ../techmap/rtl/allmem.vhd +techmap ../techmap/rtl/gencomp.vhd +techmap ../techmap/rtl/memory_inferred.vhd +techmap ../techmap/rtl/memory_unisim.vhd +techmap ../techmap/rtl/syncram_2p.vhd +techmap ../techmap/rtl/syncram_dp.vhd +techmap ../techmap/rtl/syncrambw.vhd +techmap ../techmap/rtl/syncram.vhd +techmap ../techmap/rtl/netcomp.vhd + +zpu rtl/zpu_config.vhd +zpu rtl/dualport_ram.vhd +zpu ../zpu/rtl/dualport_ram_ahb_wrapper.vhd +zpu ../zpu/rtl/zpu_ahb.vhd +zpu ../zpu/rtl/zpu_bus_trace.vhd +zpu ../zpu/rtl/zpu_core_medium.vhd +zpu ../zpu/rtl/zpu_core_small.vhd +zpu ../zpu/rtl/zpu_wrapper_package.vhd +zpu ../zpu/rtl/zpupkg.vhd +zpu ../zpu/rtl_tb/sim_small_fpga_top_noint.vhd +zpu ../zpu/rtl_tb/txt_util.vhd + + +# MIG example design +work cores/mig_v3_61/example_design/rtl/example_top.vhd +work cores/mig_v3_61/example_design/rtl/iodrp_controller.vhd +work cores/mig_v3_61/example_design/rtl/iodrp_mcb_controller.vhd +work cores/mig_v3_61/example_design/rtl/mcb_raw_wrapper.vhd +work cores/mig_v3_61/example_design/rtl/mcb_soft_calibration.vhd +work cores/mig_v3_61/example_design/rtl/mcb_soft_calibration_top.vhd +work cores/mig_v3_61/example_design/rtl/memc1_infrastructure.vhd +work cores/mig_v3_61/example_design/rtl/memc1_tb_top.vhd +work cores/mig_v3_61/example_design/rtl/memc1_wrapper.vhd +work cores/mig_v3_61/example_design/rtl/memc3_infrastructure.vhd +work cores/mig_v3_61/example_design/rtl/memc3_tb_top.vhd +work cores/mig_v3_61/example_design/rtl/memc3_wrapper.vhd +work cores/mig_v3_61/example_design/rtl/traffic_gen/afifo.vhd +work cores/mig_v3_61/example_design/rtl/traffic_gen/cmd_gen.vhd +work cores/mig_v3_61/example_design/rtl/traffic_gen/cmd_prbs_gen.vhd +work cores/mig_v3_61/example_design/rtl/traffic_gen/data_prbs_gen.vhd +work cores/mig_v3_61/example_design/rtl/traffic_gen/init_mem_pattern_ctr.vhd +work cores/mig_v3_61/example_design/rtl/traffic_gen/mcb_flow_control.vhd +work cores/mig_v3_61/example_design/rtl/traffic_gen/mcb_traffic_gen.vhd +work cores/mig_v3_61/example_design/rtl/traffic_gen/rd_data_gen.vhd +work cores/mig_v3_61/example_design/rtl/traffic_gen/read_data_path.vhd +work cores/mig_v3_61/example_design/rtl/traffic_gen/read_posted_fifo.vhd +work cores/mig_v3_61/example_design/rtl/traffic_gen/sp6_data_gen.vhd +work cores/mig_v3_61/example_design/rtl/traffic_gen/tg_status.vhd +work cores/mig_v3_61/example_design/rtl/traffic_gen/v6_data_gen.vhd +work cores/mig_v3_61/example_design/rtl/traffic_gen/wr_data_gen.vhd +work cores/mig_v3_61/example_design/rtl/traffic_gen/write_data_path.vhd |