diff options
Diffstat (limited to 'mig_test/synthesis/top.ucf')
| -rw-r--r-- | mig_test/synthesis/top.ucf | 312 |
1 files changed, 312 insertions, 0 deletions
diff --git a/mig_test/synthesis/top.ucf b/mig_test/synthesis/top.ucf new file mode 100644 index 0000000..6223064 --- /dev/null +++ b/mig_test/synthesis/top.ucf @@ -0,0 +1,312 @@ +# voltage +CONFIG VCCAUX = "2.5"; + + +## system stuff +#125MHz clock +NET CLK LOC = AA12 | IOSTANDARD = LVCMOS33; +#NET RESET_N LOC = A4 | IOSTANDARD = LVCMOS33 | PULLDOWN; +NET POWER_FAIL_N LOC = A2; # IO_L83P_3 +NET WATCHDOG LOC = V9 | IOSTANDARD = LVCMOS33; # WATCHDOG INPUT, IO_L50N_2 + +## user clock +NET user_clk LOC = Y13; # U12 + +## DDR3 SDRAM +NET MCB1_DRAM_A<0> LOC = F21 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_A<1> LOC = F22 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_A<2> LOC = E22 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_A<3> LOC = G20 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_A<4> LOC = F20 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_A<5> LOC = K20 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_A<6> LOC = K19 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_A<7> LOC = E20 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_A<8> LOC = C20 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_A<9> LOC = C22 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_A<10> LOC = G19 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_A<11> LOC = F19 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_A<12> LOC = D22 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_A<13> LOC = D19 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_A<14> LOC = D20 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_BA<0> LOC = J17 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_BA<1> LOC = K17 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_BA<2> LOC = H18 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_CAS_B LOC = H22 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_CKE LOC = D21 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_CK_N LOC = J19 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_CK_P LOC = H20 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQ<0> LOC = N20 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQ<1> LOC = N22 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQ<2> LOC = M21 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQ<3> LOC = M22 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQ<4> LOC = J20 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQ<5> LOC = J22 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQ<6> LOC = K21 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQ<7> LOC = K22 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQ<8> LOC = P21 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQ<9> LOC = P22 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQ<10> LOC = R20 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQ<11> LOC = R22 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQ<12> LOC = U20 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQ<13> LOC = U22 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQ<14> LOC = V21 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQ<15> LOC = V22 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_LDM LOC = L19 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQS_N<0> LOC = L22 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQS_P<0> LOC = L20 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_ODT LOC = G22 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_RAS_B LOC = H21 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_RESET_B LOC = F18 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_UDM LOC = M20 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQS_N<1> LOC = T22 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQS_P<1> LOC = T21 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_WE_B LOC = H19 | IOSTANDARD = SSTL15_II; +# +NET MCB3_DRAM_A<0> LOC = H2 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_A<1> LOC = H1 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_A<2> LOC = H5 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_A<3> LOC = K6 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_A<4> LOC = F3 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_A<5> LOC = K3 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_A<6> LOC = J4 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_A<7> LOC = H6 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_A<8> LOC = E3 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_A<9> LOC = E1 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_A<10> LOC = G4 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_A<11> LOC = C1 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_A<12> LOC = D1 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_A<13> LOC = G6 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_A<14> LOC = F5 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_BA<0> LOC = G3 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_BA<1> LOC = G1 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_BA<2> LOC = F1 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_CAS_B LOC = K4 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_CKE LOC = D2 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_CK_N LOC = H3 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_CK_P LOC = H4 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQ<0> LOC = N3 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQ<1> LOC = N1 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQ<2> LOC = M2 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQ<3> LOC = M1 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQ<4> LOC = J3 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQ<5> LOC = J1 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQ<6> LOC = K2 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQ<7> LOC = K1 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQ<8> LOC = P2 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQ<9> LOC = P1 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQ<10> LOC = R3 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQ<11> LOC = R1 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQ<12> LOC = U3 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQ<13> LOC = U1 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQ<14> LOC = V2 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQ<15> LOC = V1 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_LDM LOC = L4 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQS_N<0> LOC = L1 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQS_P<0> LOC = L3 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_ODT LOC = J6 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_RAS_B LOC = K5 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_RESET_B LOC = C3 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_UDM LOC = M3 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQS_N<1> LOC = T1 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQS_P<1> LOC = T2 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_WE_B LOC = F2 | IOSTANDARD = SSTL15_II; + +## Ethernet PHY +#NET PHY_125 LOC = AA12; # used as clk +NET PHY_MDIO LOC = AB3; +NET PHY_MDC LOC = AA2 | IOSTANDARD = LVCMOS33; +NET PHY_INT LOC = AB2; +NET PHY_RESET_B LOC = T15 | IOSTANDARD = LVCMOS33; +NET PHY_CRS LOC = T14; +NET PHY_COL LOC = R13; +NET PHY_TXEN LOC = AB16 | IOSTANDARD = LVCMOS33; +NET PHY_TXCLK LOC = W12; +NET PHY_TXER LOC = AB18 | IOSTANDARD = LVCMOS33; +NET PHY_TXD<0> LOC = AA18 | IOSTANDARD = LVCMOS33; +NET PHY_TXD<1> LOC = AB14 | IOSTANDARD = LVCMOS33; +NET PHY_TXD<2> LOC = AA16 | IOSTANDARD = LVCMOS33; +NET PHY_TXD<3> LOC = W14 | IOSTANDARD = LVCMOS33; +NET PHY_TXD<4> LOC = T16 | IOSTANDARD = LVCMOS33; +NET PHY_TXD<5> LOC = Y14 | IOSTANDARD = LVCMOS33; +NET PHY_TXD<6> LOC = V15 | IOSTANDARD = LVCMOS33; +NET PHY_TXD<7> LOC = AA14 | IOSTANDARD = LVCMOS33; +NET PHY_GTXCLK LOC = R11 | IOSTANDARD = LVCMOS33; +NET PHY_RXCLK LOC = Y11; +NET PHY_RXER LOC = Y8; +NET PHY_RXDV LOC = Y4; +NET PHY_RXD<0> LOC = Y3; +NET PHY_RXD<1> LOC = W8; +NET PHY_RXD<2> LOC = W4; +NET PHY_RXD<3> LOC = U9; +NET PHY_RXD<4> LOC = V7; +NET PHY_RXD<5> LOC = V5; +NET PHY_RXD<6> LOC = W9; +NET PHY_RXD<7> LOC = U6; + +## quad SPI Flash (W25Q64BV) +NET SPI_FLASH_CSO_B LOC = T5 | IOSTANDARD = LVCMOS33; +NET SPI_FLASH_CCLK LOC = Y21 | IOSTANDARD = LVCMOS33; +NET SPI_FLASH_IO<0> LOC = AB20; # MOSI/di +NET SPI_FLASH_IO<1> LOC = AA20; # MISO/do +NET SPI_FLASH_IO<2> LOC = U14; # MISO2/wp_n +NET SPI_FLASH_IO<3> LOC = U13; # MISO3/hold_n + +## EEPROM (48bit MAC address, DS2502-E48) +NET MAC_DATA LOC = T11 | IOSTANDARD = LVCMOS33; + +## B2B J1 user IO +NET B2B_B2_L57_N LOC = AB4; +NET B2B_B2_L57_P LOC = AA4; +NET B2B_B2_L49_N LOC = AB6; +NET B2B_B2_L49_P LOC = AA6; +# +NET B2B_B2_L48_N LOC = AB7; +NET B2B_B2_L48_P LOC = Y7; +NET B2B_B2_L45_N LOC = AB8; +NET B2B_B2_L45_P LOC = AA8; +# +NET B2B_B2_L43_N LOC = AB9; +NET B2B_B2_L43_P LOC = Y9; +NET B2B_B2_L41_N LOC = AB10; +NET B2B_B2_L41_P LOC = AA10; +# +NET B2B_B2_L21_P LOC = Y15; +NET B2B_B2_L21_N LOC = AB15; +NET B2B_B2_L15_P LOC = Y17; +NET B2B_B2_L15_N LOC = AB17; +# +NET B2B_B2_L31_N LOC = AB12; # single ended +# +NET B2B_B2_L32_N LOC = AB11; # single ended +# +NET B2B_B2_L60_P LOC = T7; +NET B2B_B2_L60_N LOC = R7; +NET B2B_B2_L59_N LOC = R8; +NET B2B_B2_L59_P LOC = R9; +# +NET B2B_B2_L44_N LOC = Y10; +NET B2B_B2_L44_P LOC = W10; +NET B2B_B2_L42_N LOC = W11; +NET B2B_B2_L42_P LOC = V11; +# +NET B2B_B2_L18_P LOC = V13; +NET B2B_B2_L18_N LOC = W13; +NET B2B_B2_L8_N LOC = U16; +NET B2B_B2_L8_P LOC = U17; +# +NET B2B_B2_L11_P LOC = V17; +NET B2B_B2_L11_N LOC = W17; +NET B2B_B2_L6_P LOC = W18 | IOSTANDARD = LVCMOS33; +NET B2B_B2_L6_N LOC = Y18; +# +NET B2B_B2_L5_P LOC = Y19; +NET B2B_B2_L5_N LOC = AB19; +NET B2B_B2_L9_N LOC = V18; +NET B2B_B2_L9_P LOC = V19; +# +NET B2B_B2_L4_N LOC = T17; +NET B2B_B2_L4_P LOC = T18; +# +NET B2B_B2_L29_N LOC = Y12; # single ended +# +NET B2B_B2_L10_N LOC = R15; +NET B2B_B2_L10_P LOC = R16; +NET B2B_B2_L2_N LOC = AB21; +NET B2B_B2_L2_P LOC = AA21; + + +## B2B J2 user IO +NET B2B_B3_L60_N LOC = B1; +NET B2B_B3_L60_P LOC = B2; +# +NET B2B_B3_L9_N LOC = T3 | IOSTANDARD = LVCMOS15; +NET B2B_B3_L9_P LOC = T4 | IOSTANDARD = LVCMOS15; +NET B2B_B0_L3_P LOC = D6; +NET B2B_B0_L3_N LOC = C6; +# +NET B2B_B3_L59_P LOC = J7 | IOSTANDARD = LVCMOS15; +NET B2B_B3_L59_N LOC = H8 | IOSTANDARD = LVCMOS15; +NET B2B_B0_L32_P LOC = D7; +NET B2B_B0_L32_N LOC = D8; +# +NET B2B_B0_L7_N LOC = C8; +NET B2B_B0_L7_P LOC = D9; +NET B2B_B0_L33_N LOC = C10; +NET B2B_B0_L33_P LOC = D10; +# +NET B2B_B0_L36_P LOC = D11; +NET B2B_B0_L36_N LOC = C12; +NET B2B_B0_L49_P LOC = D14; +NET B2B_B0_L49_N LOC = C14; +# +NET B2B_B0_L62_P LOC = D15; +NET B2B_B0_L62_N LOC = C16; +NET B2B_B0_L66_P LOC = E16; +NET B2B_B0_L66_N LOC = D17; +# +NET B2B_B1_L10_P LOC = F16; +NET B2B_B1_L10_N LOC = F17; +NET B2B_B1_L9_P LOC = G16; +NET B2B_B1_L9_N LOC = G17; +# +NET B2B_B1_L21_N LOC = J16; +NET B2B_B1_L21_P LOC = K16; +NET B2B_B1_L61_P LOC = L17; +NET B2B_B1_L61_N LOC = K18; +# +NET B2B_B0_L1 LOC = A4; # used as reset_n +# +NET B2B_B0_L2_P LOC = C5; +NET B2B_B0_L2_N LOC = A5; +NET B2B_B0_L4_N LOC = A6; +NET B2B_B0_L4_P LOC = B6; +# +NET B2B_B0_L5_N LOC = A7; +NET B2B_B0_L5_P LOC = C7; +NET B2B_B0_L6_N LOC = A8; +NET B2B_B0_L6_P LOC = B8; +# +NET B2B_B0_L8_N LOC = A9; +NET B2B_B0_L8_P LOC = C9; +NET B2B_B0_L34_N LOC = A10; +NET B2B_B0_L34_P LOC = B10; +# +NET B2B_B0_L35_N LOC = A11; +NET B2B_B0_L35_P LOC = C11; +NET B2B_B0_L37_N LOC = A12; +NET B2B_B0_L37_P LOC = B12; +# +NET B2B_B0_L38_N LOC = A13; +NET B2B_B0_L38_P LOC = C13; +NET B2B_B0_L50_N LOC = A14; +NET B2B_B0_L50_P LOC = B14; +# +NET B2B_B0_L51_N LOC = A15; +NET B2B_B0_L51_P LOC = C15; +NET B2B_B0_L63_N LOC = A16; +NET B2B_B0_L63_P LOC = B16; +# +NET B2B_B0_L64_N LOC = A17; +NET B2B_B0_L64_P LOC = C17; +NET B2B_B0_L65_N LOC = A18; +NET B2B_B0_L65_P LOC = B18; +# +NET B2B_B1_L20_P LOC = A20; +NET B2B_B1_L20_N LOC = A21; +NET B2B_B1_L19_P LOC = B21; +NET B2B_B1_L19_N LOC = B22; +NET B2B_B1_L59 LOC = P19; + + +## misc +NET USER_LED_N LOC = T20 | IOSTANDARD = LVCMOS15; # on board LED +NET AV<0> LOC = U19 | PULLUP | TIG; +NET AV<1> LOC = V20 | PULLUP | TIG; +NET AV<2> LOC = M17 | PULLUP | TIG; +NET AV<3> LOC = M18 | PULLUP | TIG; +NET BR<0> LOC = P17 | PULLUP | TIG; +NET BR<1> LOC = N16 | PULLUP | TIG; +NET BR<2> LOC = P18 | PULLUP | TIG; +NET BR<3> LOC = R19 | PULLUP | TIG; + +NET reprog_n LOC = H16 | IOSTANDARD = "LVCMOS15"; #REPROGRAMMING |
