diff options
Diffstat (limited to 'hw_godil')
-rw-r--r-- | hw_godil/bsp/build.sh | 28 | ||||
-rw-r--r-- | hw_godil/bsp/godil_xc3s500e.ucf | 95 | ||||
-rw-r--r-- | hw_godil/bsp/top.prj | 1 | ||||
-rw-r--r-- | hw_godil/bsp/top.ut | 22 | ||||
-rw-r--r-- | hw_godil/bsp/top.vhd | 42 | ||||
-rw-r--r-- | hw_godil/bsp/top.xst | 56 | ||||
-rw-r--r-- | hw_godil/doc/godil500_Ueberblick_leiterplatte.odg | bin | 0 -> 116255 bytes | |||
-rw-r--r-- | hw_godil/godil_xc3s500e_zpu_zealot_implementation.tar.gz | bin | 0 -> 5048 bytes |
8 files changed, 244 insertions, 0 deletions
diff --git a/hw_godil/bsp/build.sh b/hw_godil/bsp/build.sh new file mode 100644 index 0000000..3ec68a0 --- /dev/null +++ b/hw_godil/bsp/build.sh @@ -0,0 +1,28 @@ +# need project files: +# top.xst +# top.prj +# top.ut + +# need Xilinx tools: +# xst +# ngdbuild +# map +# par +# trce +# bitgen + +# generate build directory +mkdir build +cd build +mkdir tmp + +# start processes +xst -ifn "../top.xst" -ofn "top.syr" +ngdbuild -dd _ngo -nt timestamp -uc ../godil_xc3s500e.ucf -p xc3s500e-vq100-4 top.ngc top.ngd +map -p xc3s500e-vq100-4 -cm area -ir off -pr off -c 100 -o top_map.ncd top.ngd top.pcf +par -w -ol high -t 1 top_map.ncd top.ncd top.pcf +trce -v 3 -s 4 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf +bitgen -f ../top.ut top.ncd + +# get bitfile +cp top.bit .. diff --git a/hw_godil/bsp/godil_xc3s500e.ucf b/hw_godil/bsp/godil_xc3s500e.ucf new file mode 100644 index 0000000..3b36614 --- /dev/null +++ b/hw_godil/bsp/godil_xc3s500e.ucf @@ -0,0 +1,95 @@ +############################################################ +# GODIL Board Constraints File +# +# Family: Spartan3E +# Device: XC3S500E +# Package: VQ100 +# Speed: -4 +# +# all "pin"-IOs are equipped with level shifters + + +############################################################ +## clock/timing constraints +############################################################ + +NET "m49" PERIOD = 50 MHz ; + + +############################################################ +## pin placement constraints +############################################################ + +# inputs only +NET "m49" LOC=P89 | IOSTANDARD = LVCMOS33 ; +NET "sw1" LOC=P39 | IOSTANDARD = LVCMOS33 ; +NET "sw2" LOC=P69 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "c13" LOC=P38 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "d13" LOC=P88 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "sout" LOC=P13 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "rts" LOC=P30 | IOSTANDARD = LVCMOS33 | PULLUP ; + +# I/O's for uart & spi flash +NET "sin" LOC=P43 | IOSTANDARD = LVCMOS33 ; +NET "cts" LOC=P25 | IOSTANDARD = LVCMOS33 ; +NET "cso" LOC=P24 | IOSTANDARD = LVCMOS33 ; +NET "vs2" LOC=P47 | IOSTANDARD = LVCMOS33 ; + +# I/O's for test connector +NET "tvs1" LOC=P48 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; +NET "tvs0" LOC=P49 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; +NET "tmosi" LOC=P27 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; +NET "tdin" LOC=P44 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; +NET "tcclk" LOC=P50 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; +NET "tm1" LOC=P42 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; +NET "thsw" LOC=P99 | IOSTANDARD = LVCMOS33 | DRIVE=16 ; + +# I/O's for DIL / main connector +NET "pin<1>" LOC=P26 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<2>" LOC=P15 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<3>" LOC=P16 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<4>" LOC=P95 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<5>" LOC=P18 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<6>" LOC=P17 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<7>" LOC=P94 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<8>" LOC=P22 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<9>" LOC=P23 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<10>" LOC=P33 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<11>" LOC=P32 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<12>" LOC=P34 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<13>" LOC=P40 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<14>" LOC=P41 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<15>" LOC=P36 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<16>" LOC=P35 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<17>" LOC=P53 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<18>" LOC=P54 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<19>" LOC=P57 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<20>" LOC=P58 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<21>" LOC=P60 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<22>" LOC=P61 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<23>" LOC=P62 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<24>" LOC=P63 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<25>" LOC=P65 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<26>" LOC=P66 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<27>" LOC=P67 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<28>" LOC=P68 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<29>" LOC=P70 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<30>" LOC=P71 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<31>" LOC=P86 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<32>" LOC=P84 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<33>" LOC=P83 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<34>" LOC=P78 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<35>" LOC=P79 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<36>" LOC=P85 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<37>" LOC=P92 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<38>" LOC=P98 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<39>" LOC=P3 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<40>" LOC=P2 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<41>" LOC=P4 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<42>" LOC=P5 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<43>" LOC=P90 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<44>" LOC=P9 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<45>" LOC=P10 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<46>" LOC=P11 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<47>" LOC=P12 | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "pin<48>" LOC=P91 | IOSTANDARD = LVCMOS33 | PULLUP ; diff --git a/hw_godil/bsp/top.prj b/hw_godil/bsp/top.prj new file mode 100644 index 0000000..3975c05 --- /dev/null +++ b/hw_godil/bsp/top.prj @@ -0,0 +1 @@ +vhdl work "../top.vhd" diff --git a/hw_godil/bsp/top.ut b/hw_godil/bsp/top.ut new file mode 100644 index 0000000..06de8d5 --- /dev/null +++ b/hw_godil/bsp/top.ut @@ -0,0 +1,22 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g CRC:Enable +-g ConfigRate:1 +-g ProgPin:PullUp +-g DonePin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g DCMShutdown:Disable +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No diff --git a/hw_godil/bsp/top.vhd b/hw_godil/bsp/top.vhd new file mode 100644 index 0000000..bd11e08 --- /dev/null +++ b/hw_godil/bsp/top.vhd @@ -0,0 +1,42 @@ +-- top module of +-- GODIL + + +library ieee; +use ieee.std_logic_1164.all; + + +entity top is + port ( + m49 : in std_logic; -- oscillator input + -- GPIO + sw1 : in std_logic; -- switch 1, high active + sw2 : in std_logic; -- switch 2, low active + -- TUSB3410 + sin : inout std_logic; -- M0 configuration pin, TUSB3410 serial data input, LED3 + sout : in std_logic; -- TUSB3410 serial data out + rts : in std_logic; -- TUSB3410 ready to send (LED5) + cts : inout std_logic; -- TUSB3410 clear to send (and LED6) + vs2 : inout std_logic; -- TUSB3410 I2C connection, LED8 + tvs1 : inout std_logic; -- TUSB3410 I2C connector (and E2) + -- SPI flash + cso : inout std_logic; -- SPI memory chip select + tmosi : inout std_logic; -- SPI memory mosi (and E4) + tdin : inout std_logic; -- SPI memory data out (and E5) + tcclk : inout std_logic; -- SPI memory clock (and E6) + -- remaining IO pins + c13 : in std_logic; -- external input (pin 49) + d13 : in std_logic; -- external input (pin 50) + tvs0 : inout std_logic; -- E3 + tm1 : inout std_logic; -- M1 configuration pin (and E7) + thsw : inout std_logic; -- HSWAP configuration pin (and E8) + -- I/O's for DIL / main connector + pin : inout std_logic_vector(48 downto 1) + ); +end entity top; + + +architecture rtl of top is + +begin +end architecture rtl; diff --git a/hw_godil/bsp/top.xst b/hw_godil/bsp/top.xst new file mode 100644 index 0000000..6f6b603 --- /dev/null +++ b/hw_godil/bsp/top.xst @@ -0,0 +1,56 @@ +set -tmpdir "tmp" +set -xsthdpdir "xst" +run +-ifn ../top.prj +-ifmt mixed +-ofn top +-ofmt NGC +-p xc3s500e-4-vq100 +-top top +-opt_mode Speed +-opt_level 1 +-iuc NO +-keep_hierarchy No +-netlist_hierarchy As_Optimized +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case Maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style LUT +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract Yes +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract Yes +-resource_sharing YES +-async_to_sync NO +-mult_style Auto +-iobuf YES +-max_fanout 500 +-bufg 24 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob Auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/hw_godil/doc/godil500_Ueberblick_leiterplatte.odg b/hw_godil/doc/godil500_Ueberblick_leiterplatte.odg Binary files differnew file mode 100644 index 0000000..66b0eb3 --- /dev/null +++ b/hw_godil/doc/godil500_Ueberblick_leiterplatte.odg diff --git a/hw_godil/godil_xc3s500e_zpu_zealot_implementation.tar.gz b/hw_godil/godil_xc3s500e_zpu_zealot_implementation.tar.gz Binary files differnew file mode 100644 index 0000000..5715aa8 --- /dev/null +++ b/hw_godil/godil_xc3s500e_zpu_zealot_implementation.tar.gz |