diff options
| -rw-r--r-- | mig_test/readme.txt | 14 | ||||
| -rw-r--r-- | mig_test/rtl/top.vhd | 468 | ||||
| -rw-r--r-- | mig_test/rtl_tb/top_tb.vhd | 416 | ||||
| -rw-r--r-- | mig_test/simulation/Makefile | 66 | ||||
| -rw-r--r-- | mig_test/simulation/run.do | 65 | ||||
| -rw-r--r-- | mig_test/simulation/wave.do | 27 | ||||
| -rw-r--r-- | mig_test/synthesis/Makefile | 436 | ||||
| -rw-r--r-- | mig_test/synthesis/top.ucf | 312 | ||||
| -rw-r--r-- | mig_test/vhdl_files.txt | 2 |
9 files changed, 1806 insertions, 0 deletions
diff --git a/mig_test/readme.txt b/mig_test/readme.txt new file mode 100644 index 0000000..eba2fe9 --- /dev/null +++ b/mig_test/readme.txt @@ -0,0 +1,14 @@ +Frage: Warum geht der Speicher auf den Trenz-Boards nicht richtig? + +Hardware: +Trenz Giagabee +FTDI-Kabel +Stromversorgung + +Firmware: +MIG-Design +ZPU mit AHB2MIG und UART +Chipscope + +Software: +MEM-Test diff --git a/mig_test/rtl/top.vhd b/mig_test/rtl/top.vhd new file mode 100644 index 0000000..5775bd7 --- /dev/null +++ b/mig_test/rtl/top.vhd @@ -0,0 +1,468 @@ +-- top-level beam position monitor +-- für Trenz TE0600 +-- +-- FPGA: LX45, LX100 or LX150 +-- 10/100/1000 Gigabit Ethernet +-- 2*64 MByte DDR3 SDRAM +-- 8 MByte SPI Flash +-- +-- enthält alle Buffer/Treiber für die FPGA-Pins +-- +-- + +-------------------------------------------------------------------------------- +-- $Date: Thu Dec 22 10:52:48 2011 +0100 $ +-- $Author: Bert Lange <b.lange@hzdr.de> $ +-- $Revision: c241a5e741dd3f0c14967956eb305177252c6f25 $ +-------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library unisim; +--use unisim.vcomponents.; + +entity top is + port ( + -- pragma translate_off + simulation_break : out std_logic; + -- pragma translate_on + -- system stuff + CLK : in std_logic; -- 125 MHz + RESET_N : in std_logic; + POWER_FAIL_N : in std_logic; + WATCHDOG : out std_logic; + REPROG_N : out std_logic; + -- user clock + USER_CLK : in std_logic; + -- + -- DDR3 SDRAM + MCB1_DRAM_A : out std_logic_vector(14 downto 0); + MCB1_DRAM_BA : out std_logic_vector(2 downto 0); + MCB1_DRAM_CAS_B : out std_logic; + MCB1_DRAM_RAS_B : out std_logic; + MCB1_DRAM_WE_B : out std_logic; + MCB1_DRAM_CKE : out std_logic; + MCB1_DRAM_CK_N : out std_logic; + MCB1_DRAM_CK_P : out std_logic; + MCB1_DRAM_DQ : inout std_logic_vector(15 downto 0); + MCB1_DRAM_LDM : out std_logic; + MCB1_DRAM_UDM : out std_logic; + MCB1_DRAM_LDQS_N : inout std_logic; + MCB1_DRAM_LDQS_P : inout std_logic; + MCB1_DRAM_UDQS_N : inout std_logic; + MCB1_DRAM_UDQS_P : inout std_logic; + MCB1_DRAM_ODT : out std_logic; + MCB1_DRAM_RESET_B : out std_logic; + -- + MCB3_DRAM_A : out std_logic_vector(14 downto 0); + MCB3_DRAM_BA : out std_logic_vector(2 downto 0); + MCB3_DRAM_CAS_B : out std_logic; + MCB3_DRAM_RAS_B : out std_logic; + MCB3_DRAM_WE_B : out std_logic; + MCB3_DRAM_CKE : out std_logic; + MCB3_DRAM_CK_N : out std_logic; + MCB3_DRAM_CK_P : out std_logic; + MCB3_DRAM_DQ : inout std_logic_vector(15 downto 0); + MCB3_DRAM_LDM : out std_logic; + MCB3_DRAM_UDM : out std_logic; + MCB3_DRAM_LDQS_N : inout std_logic; + MCB3_DRAM_LDQS_P : inout std_logic; + MCB3_DRAM_UDQS_N : inout std_logic; + MCB3_DRAM_UDQS_P : inout std_logic; + MCB3_DRAM_ODT : out std_logic; + MCB3_DRAM_RESET_B : out std_logic; + -- + -- Ethernet PHY + -- phy address = 0b00111 + -- config(0) = '1' + -- config(1) = '0' + -- config(2) = '1' + -- config(3) = PHY_L10 + -- config(4) = '1' + -- config(5) = '1' + -- config(6) = PHY_LED_RX + --PHY_125 : in std_logic; -- 125 MHz from phy, used as clk + PHY_MDIO : inout std_logic; + PHY_MDC : out std_logic; + PHY_INT : in std_logic; + PHY_RESET_B : out std_logic; + PHY_CRS : in std_logic; + PHY_COL : inout std_logic; + PHY_TXEN : out std_logic; + PHY_TXCLK : in std_logic; + PHY_TXER : out std_logic; + PHY_TXD : out std_logic_vector(7 downto 0); + PHY_GTXCLK : out std_logic; + PHY_RXCLK : in std_logic; + PHY_RXER : in std_logic; + PHY_RXDV : in std_logic; + PHY_RXD : in std_logic_vector(7 downto 0); + -- + -- quad SPI Flash (W25Q64BV) + SPI_FLASH_CSO_B : out std_logic; + SPI_FLASH_CCLK : out std_logic; + SPI_FLASH_IO : inout std_logic_vector(3 downto 0); -- ( 0=di, 1=do, 2=wp_n, 3=hold_n) + -- + -- EEPROM (48bit MAC address, DS2502-E48) + MAC_DATA : inout std_logic; + -- + -- B2B J1 user IO + B2B_B2_L57_N : inout std_logic; + B2B_B2_L57_P : inout std_logic; + B2B_B2_L49_N : inout std_logic; + B2B_B2_L49_P : inout std_logic; + B2B_B2_L48_N : inout std_logic; + B2B_B2_L48_P : inout std_logic; + B2B_B2_L45_N : inout std_logic; + B2B_B2_L45_P : inout std_logic; + B2B_B2_L43_N : inout std_logic; + B2B_B2_L43_P : inout std_logic; + B2B_B2_L41_N : inout std_logic; + B2B_B2_L41_P : inout std_logic; + B2B_B2_L21_P : inout std_logic; + B2B_B2_L21_N : inout std_logic; + B2B_B2_L15_P : inout std_logic; + B2B_B2_L15_N : inout std_logic; + B2B_B2_L31_N : inout std_logic; -- single ended + B2B_B2_L32_N : inout std_logic; -- single ended + B2B_B2_L60_P : inout std_logic; + B2B_B2_L60_N : inout std_logic; + B2B_B2_L59_N : inout std_logic; + B2B_B2_L59_P : inout std_logic; + B2B_B2_L44_N : inout std_logic; + B2B_B2_L44_P : inout std_logic; + B2B_B2_L42_N : inout std_logic; + B2B_B2_L42_P : inout std_logic; + B2B_B2_L18_P : inout std_logic; + B2B_B2_L18_N : inout std_logic; + B2B_B2_L8_N : inout std_logic; + B2B_B2_L8_P : inout std_logic; + B2B_B2_L11_P : inout std_logic; + B2B_B2_L11_N : inout std_logic; + B2B_B2_L6_P : inout std_logic; + B2B_B2_L6_N : inout std_logic; + B2B_B2_L5_P : inout std_logic; + B2B_B2_L5_N : inout std_logic; + B2B_B2_L9_N : inout std_logic; + B2B_B2_L9_P : inout std_logic; + B2B_B2_L4_N : inout std_logic; + B2B_B2_L4_P : inout std_logic; + B2B_B2_L29_N : inout std_logic; -- single ended + B2B_B2_L10_N : inout std_logic; + B2B_B2_L10_P : inout std_logic; + B2B_B2_L2_N : inout std_logic; + B2B_B2_L2_P : inout std_logic; + -- + -- B2B J2 user IO + B2B_B3_L60_N : inout std_logic; + B2B_B3_L60_P : inout std_logic; + B2B_B3_L9_N : inout std_logic; + B2B_B3_L9_P : inout std_logic; + B2B_B0_L3_P : inout std_logic; + B2B_B0_L3_N : inout std_logic; + B2B_B3_L59_P : inout std_logic; + B2B_B3_L59_N : inout std_logic; + B2B_B0_L32_P : inout std_logic; + B2B_B0_L32_N : inout std_logic; + B2B_B0_L7_N : inout std_logic; + B2B_B0_L7_P : inout std_logic; + B2B_B0_L33_N : inout std_logic; + B2B_B0_L33_P : inout std_logic; + B2B_B0_L36_P : inout std_logic; + B2B_B0_L36_N : inout std_logic; + B2B_B0_L49_P : inout std_logic; + B2B_B0_L49_N : inout std_logic; + B2B_B0_L62_P : inout std_logic; + B2B_B0_L62_N : inout std_logic; + B2B_B0_L66_P : inout std_logic; + B2B_B0_L66_N : inout std_logic; + B2B_B1_L10_P : inout std_logic; + B2B_B1_L10_N : inout std_logic; + B2B_B1_L9_P : inout std_logic; + B2B_B1_L9_N : inout std_logic; + B2B_B1_L21_N : inout std_logic; + B2B_B1_L21_P : inout std_logic; + B2B_B1_L61_P : inout std_logic; + B2B_B1_L61_N : inout std_logic; + --B2B_B0_L1 : inout std_logic; -- used as reset_n + B2B_B0_L2_P : inout std_logic; + B2B_B0_L2_N : inout std_logic; + B2B_B0_L4_N : inout std_logic; + B2B_B0_L4_P : inout std_logic; + B2B_B0_L5_N : inout std_logic; + B2B_B0_L5_P : inout std_logic; + B2B_B0_L6_N : inout std_logic; + B2B_B0_L6_P : inout std_logic; + B2B_B0_L8_N : inout std_logic; + B2B_B0_L8_P : inout std_logic; + B2B_B0_L34_N : inout std_logic; + B2B_B0_L34_P : inout std_logic; + B2B_B0_L35_N : inout std_logic; + B2B_B0_L35_P : inout std_logic; + B2B_B0_L37_N : inout std_logic; + B2B_B0_L37_P : inout std_logic; + B2B_B0_L38_N : inout std_logic; + B2B_B0_L38_P : inout std_logic; + B2B_B0_L50_N : inout std_logic; + B2B_B0_L50_P : inout std_logic; + B2B_B0_L51_N : inout std_logic; + B2B_B0_L51_P : inout std_logic; + B2B_B0_L63_N : inout std_logic; + B2B_B0_L63_P : inout std_logic; + B2B_B0_L64_N : inout std_logic; + B2B_B0_L64_P : inout std_logic; + B2B_B0_L65_N : inout std_logic; + B2B_B0_L65_P : inout std_logic; + B2B_B1_L20_P : inout std_logic; + B2B_B1_L20_N : inout std_logic; + B2B_B1_L19_P : inout std_logic; + B2B_B1_L19_N : inout std_logic; + B2B_B1_L59 : inout std_logic; + -- + -- misc + USER_LED_N : out std_logic; + AV : in std_logic_vector(3 downto 0); + BR : in std_logic_vector(3 downto 0) + ); +end entity top; + +architecture Behavioral of top is + + function simulation_active return std_ulogic is + variable result : std_ulogic; + begin + result := '0'; + -- pragma translate_off + result := '1'; + -- pragma translate_on + return result; + end function simulation_active; + + function divider_init return integer is + variable result : integer; + begin + -- synthessis value: + result := 62500000; + + -- pragma translate_off + -- simulation value + result := 5; + -- pragma translate_on + + return result; + end function divider_init; + + alias CARRIER_LED0 : std_logic is B2B_B3_L59_N; + alias CARRIER_LED1 : std_logic is B2B_B3_L59_P; + alias CARRIER_LED2 : std_logic is B2B_B3_L9_P; + alias CARRIER_LED3 : std_logic is B2B_B3_L9_N; + + constant divider : integer := divider_init; + -- + signal counter : integer := 0; + signal led_i : std_logic_vector( 4 downto 0) := ( 0 => '0', others => '1'); + + +begin + + -- default output drivers + -- for unused blocks + PHY_MDC <= '1'; + PHY_TXEN <= '0'; + PHY_TXER <= '0'; + PHY_TXD <= (others => '1'); + PHY_GTXCLK <= '0'; + PHY_RESET_B <= '0'; + PHY_COL <= 'Z'; + PHY_MDIO <= 'Z'; + + MCB1_DRAM_RESET_B <= '0'; + MCB1_DRAM_A <= (others => '1'); + MCB1_DRAM_BA <= (others => '1'); + MCB1_DRAM_CAS_B <= '1'; + MCB1_DRAM_RAS_B <= '1'; + MCB1_DRAM_WE_B <= '1'; + MCB1_DRAM_CKE <= '0'; + MCB1_DRAM_CK_N <= '0'; + MCB1_DRAM_CK_P <= '1'; + MCB1_DRAM_LDM <= '0'; + MCB1_DRAM_UDM <= '0'; + MCB1_DRAM_ODT <= '1'; + MCB1_DRAM_UDQS_N <= 'Z'; + MCB1_DRAM_UDQS_P <= 'Z'; + MCB1_DRAM_LDQS_N <= 'Z'; + MCB1_DRAM_LDQS_P <= 'Z'; + MCB1_DRAM_DQ <= (others => 'Z'); + + MCB3_DRAM_RESET_B <= '0'; + MCB3_DRAM_A <= (others => '1'); + MCB3_DRAM_BA <= (others => '1'); + MCB3_DRAM_CAS_B <= '1'; + MCB3_DRAM_RAS_B <= '1'; + MCB3_DRAM_WE_B <= '1'; + MCB3_DRAM_CKE <= '0'; + MCB3_DRAM_CK_N <= '0'; + MCB3_DRAM_CK_P <= '1'; + MCB3_DRAM_LDM <= '0'; + MCB3_DRAM_UDM <= '0'; + MCB3_DRAM_ODT <= '1'; + MCB3_DRAM_UDQS_N <= 'Z'; + MCB3_DRAM_UDQS_P <= 'Z'; + MCB3_DRAM_LDQS_N <= 'Z'; + MCB3_DRAM_LDQS_P <= 'Z'; + MCB3_DRAM_DQ <= (others => 'Z'); + + SPI_FLASH_CSO_B <= '1'; + SPI_FLASH_CCLK <= '1'; + SPI_FLASH_IO <= (others => 'Z'); + + WATCHDOG <= 'Z'; -- disable watchdog + REPROG_N <= '1'; + + MAC_DATA <= 'Z'; + + -- B2B J1 user IO + B2B_B2_L57_N <= 'Z'; + B2B_B2_L57_P <= 'Z'; + B2B_B2_L49_N <= 'Z'; + B2B_B2_L49_P <= 'Z'; + B2B_B2_L48_N <= 'Z'; + B2B_B2_L48_P <= 'Z'; + B2B_B2_L45_N <= 'Z'; + B2B_B2_L45_P <= 'Z'; + B2B_B2_L43_N <= 'Z'; + B2B_B2_L43_P <= 'Z'; + B2B_B2_L41_N <= 'Z'; + B2B_B2_L41_P <= 'Z'; + B2B_B2_L21_P <= 'Z'; + B2B_B2_L21_N <= 'Z'; + B2B_B2_L15_P <= 'Z'; + B2B_B2_L15_N <= 'Z'; + B2B_B2_L31_N <= 'Z'; + B2B_B2_L32_N <= 'Z'; + B2B_B2_L60_P <= 'Z'; + B2B_B2_L60_N <= 'Z'; + B2B_B2_L59_N <= 'Z'; + B2B_B2_L59_P <= 'Z'; + B2B_B2_L44_N <= 'Z'; + B2B_B2_L44_P <= 'Z'; + B2B_B2_L42_N <= 'Z'; + B2B_B2_L42_P <= 'Z'; + B2B_B2_L18_P <= 'Z'; + B2B_B2_L18_N <= 'Z'; + B2B_B2_L8_N <= 'Z'; + B2B_B2_L8_P <= 'Z'; + B2B_B2_L11_P <= 'Z'; + B2B_B2_L11_N <= 'Z'; + B2B_B2_L6_P <= 'Z'; + B2B_B2_L6_N <= 'Z'; + B2B_B2_L5_P <= 'Z'; + B2B_B2_L5_N <= 'Z'; + B2B_B2_L9_N <= 'Z'; + B2B_B2_L9_P <= 'Z'; + B2B_B2_L4_N <= 'Z'; + B2B_B2_L4_P <= 'Z'; + B2B_B2_L29_N <= 'Z'; + B2B_B2_L10_N <= 'Z'; + B2B_B2_L10_P <= 'Z'; + B2B_B2_L2_N <= 'Z'; + B2B_B2_L2_P <= 'Z'; + B2B_B3_L60_N <= 'Z'; + B2B_B3_L60_P <= 'Z'; + --B2B_B3_L9_N <= 'Z'; + --B2B_B3_L9_P <= 'Z'; + B2B_B0_L3_P <= 'Z'; + B2B_B0_L3_N <= 'Z'; + + -- B2B J2 user IO + --B2B_B3_L59_P <= 'Z'; + --B2B_B3_L59_N <= 'Z'; + B2B_B0_L32_P <= 'Z'; + B2B_B0_L32_N <= 'Z'; + B2B_B0_L7_N <= 'Z'; + B2B_B0_L7_P <= 'Z'; + B2B_B0_L33_N <= 'Z'; + B2B_B0_L33_P <= 'Z'; + B2B_B0_L36_P <= 'Z'; + B2B_B0_L36_N <= 'Z'; + B2B_B0_L49_P <= 'Z'; + B2B_B0_L49_N <= 'Z'; + B2B_B0_L62_P <= 'Z'; + B2B_B0_L62_N <= 'Z'; + B2B_B0_L66_P <= 'Z'; + B2B_B0_L66_N <= 'Z'; + B2B_B1_L10_P <= 'Z'; + B2B_B1_L10_N <= 'Z'; + B2B_B1_L9_P <= 'Z'; + B2B_B1_L9_N <= 'Z'; + B2B_B1_L21_N <= 'Z'; + B2B_B1_L21_P <= 'Z'; + B2B_B1_L61_P <= 'Z'; + B2B_B1_L61_N <= 'Z'; + B2B_B0_L2_P <= 'Z'; + B2B_B0_L2_N <= 'Z'; + B2B_B0_L4_N <= 'Z'; + B2B_B0_L4_P <= 'Z'; + B2B_B0_L5_N <= 'Z'; + B2B_B0_L5_P <= 'Z'; + B2B_B0_L6_N <= 'Z'; + B2B_B0_L6_P <= 'Z'; + B2B_B0_L8_N <= 'Z'; + B2B_B0_L8_P <= 'Z'; + B2B_B0_L34_N <= 'Z'; + B2B_B0_L34_P <= 'Z'; + B2B_B0_L35_N <= 'Z'; + B2B_B0_L35_P <= 'Z'; + B2B_B0_L37_N <= 'Z'; + B2B_B0_L37_P <= 'Z'; + B2B_B0_L38_N <= 'Z'; + B2B_B0_L38_P <= 'Z'; + B2B_B0_L50_N <= 'Z'; + B2B_B0_L50_P <= 'Z'; + B2B_B0_L51_N <= 'Z'; + B2B_B0_L51_P <= 'Z'; + B2B_B0_L63_N <= 'Z'; + B2B_B0_L63_P <= 'Z'; + B2B_B0_L64_N <= 'Z'; + B2B_B0_L64_P <= 'Z'; + B2B_B0_L65_N <= 'Z'; + B2B_B0_L65_P <= 'Z'; + B2B_B1_L20_P <= 'Z'; + B2B_B1_L20_N <= 'Z'; + B2B_B1_L19_P <= 'Z'; + B2B_B1_L19_N <= 'Z'; + B2B_B1_L59 <= 'Z'; + + + -- used IOs + user_led_n <= led_i( 0); + CARRIER_LED0 <= led_i( 1); + CARRIER_LED1 <= led_i( 2); + CARRIER_LED2 <= led_i( 3); + CARRIER_LED3 <= led_i( 4); + + process + begin + wait until rising_edge( clk); + if counter = divider-1 then + counter <= 0; + led_i <= led_i( led_i'high - 1 downto 0) & led_i( led_i'high); + else + counter <= counter + 1; + end if; + end process; + + + -- pragma translate_off + process + begin + simulation_break <= '0'; + wait for 1 us; + simulation_break <= '1'; + wait; + end process; + -- pragma translate_on + +end architecture Behavioral; + diff --git a/mig_test/rtl_tb/top_tb.vhd b/mig_test/rtl_tb/top_tb.vhd new file mode 100644 index 0000000..2108ff3 --- /dev/null +++ b/mig_test/rtl_tb/top_tb.vhd @@ -0,0 +1,416 @@ +library ieee; +use ieee.std_logic_1164.all; + + +entity top_tb is +end top_tb; + + +architecture testbench of top_tb is + + constant system_frequency : integer := 125_000_000; -- MHz + constant tb_clk_period : time := (1 sec) / system_frequency; + + signal simulation_run : boolean := true; + signal tb_simulation_break : std_logic; + -- + signal tb_clk : std_logic := '0'; + signal tb_reset_n : std_logic; + signal tb_power_fail_n : std_logic; + signal tb_watchdog : std_logic; + signal tb_reprog_n : std_logic; + -- + signal tb_user_clk : std_logic; + -- + signal tb_mcb1_dram_a : std_logic_vector(14 downto 0); + signal tb_mcb1_dram_ba : std_logic_vector(2 downto 0); + signal tb_mcb1_dram_cas_b : std_logic; + signal tb_mcb1_dram_ras_b : std_logic; + signal tb_mcb1_dram_we_b : std_logic; + signal tb_mcb1_dram_cke : std_logic; + signal tb_mcb1_dram_ck_n : std_logic; + signal tb_mcb1_dram_ck_p : std_logic; + signal tb_mcb1_dram_dq : std_logic_vector(15 downto 0); + signal tb_mcb1_dram_ldm : std_logic; + signal tb_mcb1_dram_udm : std_logic; + signal tb_mcb1_dram_ldqs_n : std_logic; + signal tb_mcb1_dram_ldqs_p : std_logic; + signal tb_mcb1_dram_udqs_n : std_logic; + signal tb_mcb1_dram_udqs_p : std_logic; + signal tb_mcb1_dram_odt : std_logic; + signal tb_mcb1_dram_reset_b : std_logic; + -- + signal tb_mcb3_dram_a : std_logic_vector(14 downto 0); + signal tb_mcb3_dram_ba : std_logic_vector(2 downto 0); + signal tb_mcb3_dram_cas_b : std_logic; + signal tb_mcb3_dram_ras_b : std_logic; + signal tb_mcb3_dram_we_b : std_logic; + signal tb_mcb3_dram_cke : std_logic; + signal tb_mcb3_dram_ck_n : std_logic; + signal tb_mcb3_dram_ck_p : std_logic; + signal tb_mcb3_dram_dq : std_logic_vector(15 downto 0); + signal tb_mcb3_dram_ldm : std_logic; + signal tb_mcb3_dram_udm : std_logic; + signal tb_mcb3_dram_ldqs_n : std_logic; + signal tb_mcb3_dram_ldqs_p : std_logic; + signal tb_mcb3_dram_udqs_n : std_logic; + signal tb_mcb3_dram_udqs_p : std_logic; + signal tb_mcb3_dram_odt : std_logic; + signal tb_mcb3_dram_reset_b : std_logic; + -- + signal tb_phy_mdio : std_logic; + signal tb_phy_mdc : std_logic; + signal tb_phy_int : std_logic; + signal tb_phy_reset_b : std_logic; + signal tb_phy_crs : std_logic; + signal tb_phy_col : std_logic; + signal tb_phy_txen : std_logic; + signal tb_phy_txclk : std_logic; + signal tb_phy_txer : std_logic; + signal tb_phy_txd : std_logic_vector(7 downto 0); + signal tb_phy_gtxclk : std_logic; + signal tb_phy_rxclk : std_logic; + signal tb_phy_rxer : std_logic; + signal tb_phy_rxdv : std_logic; + signal tb_phy_rxd : std_logic_vector(7 downto 0); + -- + signal tb_spi_flash_cso_b : std_logic; + signal tb_spi_flash_cclk : std_logic; + signal tb_spi_flash_io : std_logic_vector(3 downto 0); -- ( 0=di, 1=do, 2=wp_n, 3=hold_n) + -- + signal tb_mac_data : std_logic; + -- + signal tb_b2b_b2_l57_n : std_logic; + signal tb_b2b_b2_l57_p : std_logic; + signal tb_b2b_b2_l49_n : std_logic; + signal tb_b2b_b2_l49_p : std_logic; + signal tb_b2b_b2_l48_n : std_logic; + signal tb_b2b_b2_l48_p : std_logic; + signal tb_b2b_b2_l45_n : std_logic; + signal tb_b2b_b2_l45_p : std_logic; + signal tb_b2b_b2_l43_n : std_logic; + signal tb_b2b_b2_l43_p : std_logic; + signal tb_b2b_b2_l41_n : std_logic; + signal tb_b2b_b2_l41_p : std_logic; + signal tb_b2b_b2_l21_p : std_logic; + signal tb_b2b_b2_l21_n : std_logic; + signal tb_b2b_b2_l15_p : std_logic; + signal tb_b2b_b2_l15_n : std_logic; + signal tb_b2b_b2_l31_n : std_logic; -- single ended + signal tb_b2b_b2_l32_n : std_logic; -- single ended + signal tb_b2b_b2_l60_p : std_logic; + signal tb_b2b_b2_l60_n : std_logic; + signal tb_b2b_b2_l59_n : std_logic; + signal tb_b2b_b2_l59_p : std_logic; + signal tb_b2b_b2_l44_n : std_logic; + signal tb_b2b_b2_l44_p : std_logic; + signal tb_b2b_b2_l42_n : std_logic; + signal tb_b2b_b2_l42_p : std_logic; + signal tb_b2b_b2_l18_p : std_logic; + signal tb_b2b_b2_l18_n : std_logic; + signal tb_b2b_b2_l8_n : std_logic; + signal tb_b2b_b2_l8_p : std_logic; + signal tb_b2b_b2_l11_p : std_logic; + signal tb_b2b_b2_l11_n : std_logic; + signal tb_b2b_b2_l6_p : std_logic; + signal tb_b2b_b2_l6_n : std_logic; + signal tb_b2b_b2_l5_p : std_logic; + signal tb_b2b_b2_l5_n : std_logic; + signal tb_b2b_b2_l9_n : std_logic; + signal tb_b2b_b2_l9_p : std_logic; + signal tb_b2b_b2_l4_n : std_logic; + signal tb_b2b_b2_l4_p : std_logic; + signal tb_b2b_b2_l29_n : std_logic; -- single ended + signal tb_b2b_b2_l10_n : std_logic; + signal tb_b2b_b2_l10_p : std_logic; + signal tb_b2b_b2_l2_n : std_logic; + signal tb_b2b_b2_l2_p : std_logic; + -- + signal tb_b2b_b3_l60_n : std_logic; + signal tb_b2b_b3_l60_p : std_logic; + signal tb_b2b_b3_l9_n : std_logic; + signal tb_b2b_b3_l9_p : std_logic; + signal tb_b2b_b0_l3_p : std_logic; + signal tb_b2b_b0_l3_n : std_logic; + signal tb_b2b_b3_l59_p : std_logic; + signal tb_b2b_b3_l59_n : std_logic; + signal tb_b2b_b0_l32_p : std_logic; + signal tb_b2b_b0_l32_n : std_logic; + signal tb_b2b_b0_l7_n : std_logic; + signal tb_b2b_b0_l7_p : std_logic; + signal tb_b2b_b0_l33_n : std_logic; + signal tb_b2b_b0_l33_p : std_logic; + signal tb_b2b_b0_l36_p : std_logic; + signal tb_b2b_b0_l36_n : std_logic; + signal tb_b2b_b0_l49_p : std_logic; + signal tb_b2b_b0_l49_n : std_logic; + signal tb_b2b_b0_l62_p : std_logic; + signal tb_b2b_b0_l62_n : std_logic; + signal tb_b2b_b0_l66_p : std_logic; + signal tb_b2b_b0_l66_n : std_logic; + signal tb_b2b_b1_l10_p : std_logic; + signal tb_b2b_b1_l10_n : std_logic; + signal tb_b2b_b1_l9_p : std_logic; + signal tb_b2b_b1_l9_n : std_logic; + signal tb_b2b_b1_l21_n : std_logic; + signal tb_b2b_b1_l21_p : std_logic; + signal tb_b2b_b1_l61_p : std_logic; + signal tb_b2b_b1_l61_n : std_logic; + -- + signal tb_b2b_b0_l2_p : std_logic; + signal tb_b2b_b0_l2_n : std_logic; + signal tb_b2b_b0_l4_n : std_logic; + signal tb_b2b_b0_l4_p : std_logic; + signal tb_b2b_b0_l5_n : std_logic; + signal tb_b2b_b0_l5_p : std_logic; + signal tb_b2b_b0_l6_n : std_logic; + signal tb_b2b_b0_l6_p : std_logic; + signal tb_b2b_b0_l8_n : std_logic; + signal tb_b2b_b0_l8_p : std_logic; + signal tb_b2b_b0_l34_n : std_logic; + signal tb_b2b_b0_l34_p : std_logic; + signal tb_b2b_b0_l35_n : std_logic; + signal tb_b2b_b0_l35_p : std_logic; + signal tb_b2b_b0_l37_n : std_logic; + signal tb_b2b_b0_l37_p : std_logic; + signal tb_b2b_b0_l38_n : std_logic; + signal tb_b2b_b0_l38_p : std_logic; + signal tb_b2b_b0_l50_n : std_logic; + signal tb_b2b_b0_l50_p : std_logic; + signal tb_b2b_b0_l51_n : std_logic; + signal tb_b2b_b0_l51_p : std_logic; + signal tb_b2b_b0_l63_n : std_logic; + signal tb_b2b_b0_l63_p : std_logic; + signal tb_b2b_b0_l64_n : std_logic; + signal tb_b2b_b0_l64_p : std_logic; + signal tb_b2b_b0_l65_n : std_logic; + signal tb_b2b_b0_l65_p : std_logic; + signal tb_b2b_b1_l20_p : std_logic; + signal tb_b2b_b1_l20_n : std_logic; + signal tb_b2b_b1_l19_p : std_logic; + signal tb_b2b_b1_l19_n : std_logic; + signal tb_b2b_b1_l59 : std_logic; + -- + signal tb_user_led_n : std_logic; + signal tb_av : std_logic_vector(3 downto 0); + signal tb_br : std_logic_vector(3 downto 0); + + +begin + + tb_clk <= not tb_clk after tb_clk_period / 2 when simulation_run; + tb_reset_n <= '0', '1' after tb_clk_period * 6.66; + + top_i0: entity work.top + port map ( + -- pragma translate_off + simulation_break => tb_simulation_break, -- : out std_logic; + -- pragma translate_on + -- system stuff + CLK => tb_clk, -- : in std_logic; -- 125 MHz + RESET_N => tb_reset_n, -- : in std_logic; + POWER_FAIL_N => tb_power_fail_n, -- : in std_logic; + WATCHDOG => tb_watchdog, -- : out std_logic; + REPROG_N => tb_reprog_n, -- : out std_logic; + -- user clock -- + USER_CLK => tb_user_clk, -- : in std_logic; + -- -- + -- DDR3 SDRAM -- + MCB1_DRAM_A => tb_mcb1_dram_a, -- : out std_logic_vector(14 downto 0); + MCB1_DRAM_BA => tb_mcb1_dram_ba, -- : out std_logic_vector(2 downto 0); + MCB1_DRAM_CAS_B => tb_mcb1_dram_cas_b, -- : out std_logic; + MCB1_DRAM_RAS_B => tb_mcb1_dram_ras_b, -- : out std_logic; + MCB1_DRAM_WE_B => tb_mcb1_dram_we_b, -- : out std_logic; + MCB1_DRAM_CKE => tb_mcb1_dram_cke, -- : out std_logic; + MCB1_DRAM_CK_N => tb_mcb1_dram_ck_n, -- : out std_logic; + MCB1_DRAM_CK_P => tb_mcb1_dram_ck_p, -- : out std_logic; + MCB1_DRAM_DQ => tb_mcb1_dram_dq, -- : inout std_logic_vector(15 downto 0); + MCB1_DRAM_LDM => tb_mcb1_dram_ldm, -- : out std_logic; + MCB1_DRAM_UDM => tb_mcb1_dram_udm, -- : out std_logic; + MCB1_DRAM_LDQS_N => tb_mcb1_dram_ldqs_n, -- : inout std_logic; + MCB1_DRAM_LDQS_P => tb_mcb1_dram_ldqs_p, -- : inout std_logic; + MCB1_DRAM_UDQS_N => tb_mcb1_dram_udqs_n, -- : inout std_logic; + MCB1_DRAM_UDQS_P => tb_mcb1_dram_udqs_p, -- : inout std_logic; + MCB1_DRAM_ODT => tb_mcb1_dram_odt, -- : out std_logic; + MCB1_DRAM_RESET_B => tb_mcb1_dram_reset_b, -- : out std_logic; + -- -- + MCB3_DRAM_A => tb_mcb3_dram_a, -- : out std_logic_vector(14 downto 0); + MCB3_DRAM_BA => tb_mcb3_dram_ba, -- : out std_logic_vector(2 downto 0); + MCB3_DRAM_CAS_B => tb_mcb3_dram_cas_b, -- : out std_logic; + MCB3_DRAM_RAS_B => tb_mcb3_dram_ras_b, -- : out std_logic; + MCB3_DRAM_WE_B => tb_mcb3_dram_we_b, -- : out std_logic; + MCB3_DRAM_CKE => tb_mcb3_dram_cke, -- : out std_logic; + MCB3_DRAM_CK_N => tb_mcb3_dram_ck_n, -- : out std_logic; + MCB3_DRAM_CK_P => tb_mcb3_dram_ck_p, -- : out std_logic; + MCB3_DRAM_DQ => tb_mcb3_dram_dq, -- : inout std_logic_vector(15 downto 0); + MCB3_DRAM_LDM => tb_mcb3_dram_ldm, -- : out std_logic; + MCB3_DRAM_UDM => tb_mcb3_dram_udm, -- : out std_logic; + MCB3_DRAM_LDQS_N => tb_mcb3_dram_ldqs_n, -- : inout std_logic; + MCB3_DRAM_LDQS_P => tb_mcb3_dram_ldqs_p, -- : inout std_logic; + MCB3_DRAM_UDQS_N => tb_mcb3_dram_udqs_n, -- : inout std_logic; + MCB3_DRAM_UDQS_P => tb_mcb3_dram_udqs_p, -- : inout std_logic; + MCB3_DRAM_ODT => tb_mcb3_dram_odt, -- : out std_logic; + MCB3_DRAM_RESET_B => tb_mcb3_dram_reset_b, -- : out std_logic; + -- + -- Ethernet PHY + -- phy address = 0b00111 + -- config(0) = '1' + -- config(1) = '0' + -- config(2) = '1' + -- config(3) = PHY_L10 + -- config(4) = '1' + -- config(5) = '1' + -- config(6) = PHY_LED_RX + --PHY_125 -- : in std_logic; -- 125 MHz from phy, used as clk + PHY_MDIO => tb_phy_mdio, -- : inout std_logic; + PHY_MDC => tb_phy_mdc, -- : out std_logic; + PHY_INT => tb_phy_int, -- : in std_logic; + PHY_RESET_B => tb_phy_reset_b, -- : out std_logic; + PHY_CRS => tb_phy_crs, -- : in std_logic; + PHY_COL => tb_phy_col, -- : inout std_logic; + PHY_TXEN => tb_phy_txen, -- : out std_logic; + PHY_TXCLK => tb_phy_txclk, -- : in std_logic; + PHY_TXER => tb_phy_txer, -- : out std_logic; + PHY_TXD => tb_phy_txd, -- : out std_logic_vector(7 downto 0); + PHY_GTXCLK => tb_phy_gtxclk, -- : out std_logic; + PHY_RXCLK => tb_phy_rxclk, -- : in std_logic; + PHY_RXER => tb_phy_rxer, -- : in std_logic; + PHY_RXDV => tb_phy_rxdv, -- : in std_logic; + PHY_RXD => tb_phy_rxd, -- : in std_logic_vector(7 downto 0); + -- + -- quad SPI Flash (W25Q64BV) + SPI_FLASH_CSO_B => tb_spi_flash_cso_b, -- : out std_logic; + SPI_FLASH_CCLK => tb_spi_flash_cclk, -- : out std_logic; + SPI_FLASH_IO => tb_spi_flash_io, -- : inout std_logic_vector(3 downto 0); -- ( 0=di, 1=do, 2=wp_n, 3=hold_n) + -- + -- EEPROM (48bit MAC address, DS2502-E48) + MAC_DATA => tb_mac_data, -- : inout std_logic; + -- + -- B2B J1 user IO + B2B_B2_L57_N => tb_b2b_b2_l57_n, -- : inout std_logic; + B2B_B2_L57_P => tb_b2b_b2_l57_p, -- : inout std_logic; + B2B_B2_L49_N => tb_b2b_b2_l49_n, -- : inout std_logic; + B2B_B2_L49_P => tb_b2b_b2_l49_p, -- : inout std_logic; + B2B_B2_L48_N => tb_b2b_b2_l48_n, -- : inout std_logic; + B2B_B2_L48_P => tb_b2b_b2_l48_p, -- : inout std_logic; + B2B_B2_L45_N => tb_b2b_b2_l45_n, -- : inout std_logic; + B2B_B2_L45_P => tb_b2b_b2_l45_p, -- : inout std_logic; + B2B_B2_L43_N => tb_b2b_b2_l43_n, -- : inout std_logic; + B2B_B2_L43_P => tb_b2b_b2_l43_p, -- : inout std_logic; + B2B_B2_L41_N => tb_b2b_b2_l41_n, -- : inout std_logic; + B2B_B2_L41_P => tb_b2b_b2_l41_p, -- : inout std_logic; + B2B_B2_L21_P => tb_b2b_b2_l21_p, -- : inout std_logic; + B2B_B2_L21_N => tb_b2b_b2_l21_n, -- : inout std_logic; + B2B_B2_L15_P => tb_b2b_b2_l15_p, -- : inout std_logic; + B2B_B2_L15_N => tb_b2b_b2_l15_n, -- : inout std_logic; + B2B_B2_L31_N => tb_b2b_b2_l31_n, -- : inout std_logic; -- single ended + B2B_B2_L32_N => tb_b2b_b2_l32_n, -- : inout std_logic; -- single ended + B2B_B2_L60_P => tb_b2b_b2_l60_p, -- : inout std_logic; + B2B_B2_L60_N => tb_b2b_b2_l60_n, -- : inout std_logic; + B2B_B2_L59_N => tb_b2b_b2_l59_n, -- : inout std_logic; + B2B_B2_L59_P => tb_b2b_b2_l59_p, -- : inout std_logic; + B2B_B2_L44_N => tb_b2b_b2_l44_n, -- : inout std_logic; + B2B_B2_L44_P => tb_b2b_b2_l44_p, -- : inout std_logic; + B2B_B2_L42_N => tb_b2b_b2_l42_n, -- : inout std_logic; + B2B_B2_L42_P => tb_b2b_b2_l42_p, -- : inout std_logic; + B2B_B2_L18_P => tb_b2b_b2_l18_p, -- : inout std_logic; + B2B_B2_L18_N => tb_b2b_b2_l18_n, -- : inout std_logic; + B2B_B2_L8_N => tb_b2b_b2_l8_n, -- : inout std_logic; + B2B_B2_L8_P => tb_b2b_b2_l8_p, -- : inout std_logic; + B2B_B2_L11_P => tb_b2b_b2_l11_p, -- : inout std_logic; + B2B_B2_L11_N => tb_b2b_b2_l11_n, -- : inout std_logic; + B2B_B2_L6_P => tb_b2b_b2_l6_p, -- : inout std_logic; + B2B_B2_L6_N => tb_b2b_b2_l6_n, -- : inout std_logic; + B2B_B2_L5_P => tb_b2b_b2_l5_p, -- : inout std_logic; + B2B_B2_L5_N => tb_b2b_b2_l5_n, -- : inout std_logic; + B2B_B2_L9_N => tb_b2b_b2_l9_n, -- : inout std_logic; + B2B_B2_L9_P => tb_b2b_b2_l9_p, -- : inout std_logic; + B2B_B2_L4_N => tb_b2b_b2_l4_n, -- : inout std_logic; + B2B_B2_L4_P => tb_b2b_b2_l4_p, -- : inout std_logic; + B2B_B2_L29_N => tb_b2b_b2_l29_n, -- : inout std_logic; -- single ended + B2B_B2_L10_N => tb_b2b_b2_l10_n, -- : inout std_logic; + B2B_B2_L10_P => tb_b2b_b2_l10_p, -- : inout std_logic; + B2B_B2_L2_N => tb_b2b_b2_l2_n, -- : inout std_logic; + B2B_B2_L2_P => tb_b2b_b2_l2_p, -- : inout std_logic; + -- + -- B2B J2 user IO + B2B_B3_L60_N => tb_b2b_b3_l60_n, -- : inout std_logic; + B2B_B3_L60_P => tb_b2b_b3_l60_p, -- : inout std_logic; + B2B_B3_L9_N => tb_b2b_b3_l9_n, -- : inout std_logic; + B2B_B3_L9_P => tb_b2b_b3_l9_p, -- : inout std_logic; + B2B_B0_L3_P => tb_b2b_b0_l3_p, -- : inout std_logic; + B2B_B0_L3_N => tb_b2b_b0_l3_n, -- : inout std_logic; + B2B_B3_L59_P => tb_b2b_b3_l59_p, -- : inout std_logic; + B2B_B3_L59_N => tb_b2b_b3_l59_n, -- : inout std_logic; + B2B_B0_L32_P => tb_b2b_b0_l32_p, -- : inout std_logic; + B2B_B0_L32_N => tb_b2b_b0_l32_n, -- : inout std_logic; + B2B_B0_L7_N => tb_b2b_b0_l7_n, -- : inout std_logic; + B2B_B0_L7_P => tb_b2b_b0_l7_p, -- : inout std_logic; + B2B_B0_L33_N => tb_b2b_b0_l33_n, -- : inout std_logic; + B2B_B0_L33_P => tb_b2b_b0_l33_p, -- : inout std_logic; + B2B_B0_L36_P => tb_b2b_b0_l36_p, -- : inout std_logic; + B2B_B0_L36_N => tb_b2b_b0_l36_n, -- : inout std_logic; + B2B_B0_L49_P => tb_b2b_b0_l49_p, -- : inout std_logic; + B2B_B0_L49_N => tb_b2b_b0_l49_n, -- : inout std_logic; + B2B_B0_L62_P => tb_b2b_b0_l62_p, -- : inout std_logic; + B2B_B0_L62_N => tb_b2b_b0_l62_n, -- : inout std_logic; + B2B_B0_L66_P => tb_b2b_b0_l66_p, -- : inout std_logic; + B2B_B0_L66_N => tb_b2b_b0_l66_n, -- : inout std_logic; + B2B_B1_L10_P => tb_b2b_b1_l10_p, -- : inout std_logic; + B2B_B1_L10_N => tb_b2b_b1_l10_n, -- : inout std_logic; + B2B_B1_L9_P => tb_b2b_b1_l9_p, -- : inout std_logic; + B2B_B1_L9_N => tb_b2b_b1_l9_n, -- : inout std_logic; + B2B_B1_L21_N => tb_b2b_b1_l21_n, -- : inout std_logic; + B2B_B1_L21_P => tb_b2b_b1_l21_p, -- : inout std_logic; + B2B_B1_L61_P => tb_b2b_b1_l61_p, -- : inout std_logic; + B2B_B1_L61_N => tb_b2b_b1_l61_n, -- : inout std_logic; + --B2B_B0_L1 => -- : inout std_logic; -- used as reset_n + B2B_B0_L2_P => tb_b2b_b0_l2_p, -- : inout std_logic; + B2B_B0_L2_N => tb_b2b_b0_l2_n, -- : inout std_logic; + B2B_B0_L4_N => tb_b2b_b0_l4_n, -- : inout std_logic; + B2B_B0_L4_P => tb_b2b_b0_l4_p, -- : inout std_logic; + B2B_B0_L5_N => tb_b2b_b0_l5_n, -- : inout std_logic; + B2B_B0_L5_P => tb_b2b_b0_l5_p, -- : inout std_logic; + B2B_B0_L6_N => tb_b2b_b0_l6_n, -- : inout std_logic; + B2B_B0_L6_P => tb_b2b_b0_l6_p, -- : inout std_logic; + B2B_B0_L8_N => tb_b2b_b0_l8_n, -- : inout std_logic; + B2B_B0_L8_P => tb_b2b_b0_l8_p, -- : inout std_logic; + B2B_B0_L34_N => tb_b2b_b0_l34_n, -- : inout std_logic; + B2B_B0_L34_P => tb_b2b_b0_l34_p, -- : inout std_logic; + B2B_B0_L35_N => tb_b2b_b0_l35_n, -- : inout std_logic; + B2B_B0_L35_P => tb_b2b_b0_l35_p, -- : inout std_logic; + B2B_B0_L37_N => tb_b2b_b0_l37_n, -- : inout std_logic; + B2B_B0_L37_P => tb_b2b_b0_l37_p, -- : inout std_logic; + B2B_B0_L38_N => tb_b2b_b0_l38_n, -- : inout std_logic; + B2B_B0_L38_P => tb_b2b_b0_l38_p, -- : inout std_logic; + B2B_B0_L50_N => tb_b2b_b0_l50_n, -- : inout std_logic; + B2B_B0_L50_P => tb_b2b_b0_l50_p, -- : inout std_logic; + B2B_B0_L51_N => tb_b2b_b0_l51_n, -- : inout std_logic; + B2B_B0_L51_P => tb_b2b_b0_l51_p, -- : inout std_logic; + B2B_B0_L63_N => tb_b2b_b0_l63_n, -- : inout std_logic; + B2B_B0_L63_P => tb_b2b_b0_l63_p, -- : inout std_logic; + B2B_B0_L64_N => tb_b2b_b0_l64_n, -- : inout std_logic; + B2B_B0_L64_P => tb_b2b_b0_l64_p, -- : inout std_logic; + B2B_B0_L65_N => tb_b2b_b0_l65_n, -- : inout std_logic; + B2B_B0_L65_P => tb_b2b_b0_l65_p, -- : inout std_logic; + B2B_B1_L20_P => tb_b2b_b1_l20_p, -- : inout std_logic; + B2B_B1_L20_N => tb_b2b_b1_l20_n, -- : inout std_logic; + B2B_B1_L19_P => tb_b2b_b1_l19_p, -- : inout std_logic; + B2B_B1_L19_N => tb_b2b_b1_l19_n, -- : inout std_logic; + B2B_B1_L59 => tb_b2b_b1_l59, -- : inout std_logic; + -- + -- misc + USER_LED_N => tb_user_led_n, -- : out std_logic; + AV => tb_av, -- : in std_logic_vector(3 downto 0); + BR => tb_br -- : in std_logic_vector(3 downto 0) + ); + + main: process + begin + wait until rising_edge( tb_simulation_break); + simulation_run <= false; + wait; -- forever + end process; + +end architecture testbench; + diff --git a/mig_test/simulation/Makefile b/mig_test/simulation/Makefile new file mode 100644 index 0000000..a5df795 --- /dev/null +++ b/mig_test/simulation/Makefile @@ -0,0 +1,66 @@ +# +# $HeadURL: https://svn.fzd.de/repo/concast/FWF_Projects/FWKE/beam_position_monitor/trunk/hardware/board_prototyp1/simulation/Makefile $ +# $Date: 2013-08-26 14:18:45 +0200 (Mo, 26. Aug 2013) $ +# $Author: lange $ +# $Revision: 2646 $ +# + +library = work +top = top_tb + +software_dir = ../software + + +# http://sourceforge.net/projects/vmk/ +VMK = vmk + +# generate list of used libs +library_list = $(shell cut --field 1 --delimiter=" " --only-delimited ../vhdl_files.txt | grep --invert "\#" | sort --unique) +#library_list += $(shell cut --field 1 --delimiter=" " --only-delimited ../verilog_files.txt | grep --invert "\#" | sort --unique) + +# list of verilog files +#vlog_list = $(shell cut --field 3 --delimiter=" " --only-delimited ../verilog_files.txt | grep --invert "\#" | sort --unique) + + +all: compile + +software: + test ! -d $(software_dir) || make --directory $(software_dir) | ccze -A + +hw_timestamp: + test ! -f ../rtl/Makefile || make --directory ../rtl + +compile: hw_timestamp Makefile.msim + @# compile DDR3 memory model stuff + #vlog -work nanya +define+x16 +define+sg15f +incdir++../rtl_tb $(vlog_list) + @# normal vhdl compile + export ANAFLAGS="-quiet -2008"; \ + make -f Makefile.msim | ccze -A + @echo "Start the simulation with \"make simulate\" now." + + +simulate: + #mkdir -p data + export top=$(top); \ + vsim -quiet -novopt -gui $(library).$(top) -do run.do -l transcript.log + + +clean: + @# modelsim stuff + rm -f transcript.log + rm -f *.wlf + rm -f wlf* + @# compile stuff + -make -f Makefile.msim clean + rm -rf $(library_list) + rm -f Makefile.msim + rm -f .stamp + + +# generate Makefile.msim with vmk +Makefile.msim: software ../vhdl_files.txt $(library_list) + $(VMK) -t modelsim -O -w $(library) -F ../vhdl_files.txt + +$(library_list): + vlib $@ + diff --git a/mig_test/simulation/run.do b/mig_test/simulation/run.do new file mode 100644 index 0000000..bba55ac --- /dev/null +++ b/mig_test/simulation/run.do @@ -0,0 +1,65 @@ + +# +# helper functions +# + +# restart + run +proc r {} { + restart -f + set sim_start [clock seconds] + + run -all + + puts "# simulation run time: [clock format [expr [clock seconds] - $sim_start] -gmt 1 -format %H:%M:%S] " +} + + +# restart with clear +proc rc {} { + .main clear + r +} + +# print varables +proc my_debug {} { + global env + foreach key [array names env] { + puts "$key=$env($key)" + } +} + + +# fast exit +proc e {} { + exit -force +} + +# fast exit +proc x {} { + exit -force +} + + +# get env variables +global env +quietly set top $env(top) + + +if {[file exists wave.do]} { + do wave.do +} else { + if {[file exists wave_$top.do]} { + do wave_$top.do + } else { + puts "INFO: wave file (wave_$top.do) not found" + } + puts "INFO: no wave file (wave.do) found" +} + + + +set sim_start [clock seconds] + +run -all + +puts "# simulation run time: [clock format [expr [clock seconds] - $sim_start] -gmt 1 -format %H:%M:%S] " diff --git a/mig_test/simulation/wave.do b/mig_test/simulation/wave.do new file mode 100644 index 0000000..cc26df8 --- /dev/null +++ b/mig_test/simulation/wave.do @@ -0,0 +1,27 @@ +onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /top_tb/simulation_run
+add wave -noupdate /top_tb/tb_clk
+add wave -noupdate /top_tb/tb_user_led_n
+add wave -noupdate -expand -group {carrier board LEDs} /top_tb/tb_b2b_b3_l59_n
+add wave -noupdate -expand -group {carrier board LEDs} /top_tb/tb_b2b_b3_l59_p
+add wave -noupdate -expand -group {carrier board LEDs} /top_tb/tb_b2b_b3_l9_p
+add wave -noupdate -expand -group {carrier board LEDs} /top_tb/tb_b2b_b3_l9_n
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {83164314 ps} 0}
+quietly wave cursor active 1
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1923
+configure wave -griddelta 32
+configure wave -timeline 1
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ps} {1054200 ps}
diff --git a/mig_test/synthesis/Makefile b/mig_test/synthesis/Makefile new file mode 100644 index 0000000..14df7bc --- /dev/null +++ b/mig_test/synthesis/Makefile @@ -0,0 +1,436 @@ +# +# $HeadURL: https://svn.fzd.de/repo/concast/FWF_Projects/FWKE/beam_position_monitor/trunk/hardware/board_prototyp1/synthesis/Makefile $ +# $Date: 2014-05-23 15:16:41 +0200 (Fr, 23. Mai 2014) $ +# $Author: lange $ +# $Revision: 3192 $ +# + +MODULE = top +DEVICE = xc6slx100 +SPEEDGRADE = 2 +PACKAGE = fgg484 +UCF_FILE = top.ucf +CORES = ../cores/ +SOFTWARE = ../../../software +BMM_FILE = zpu.bmm +BMM_BD_FILE = zpu_bd.bmm + +BUILDDIR = isebuild +DEVICE_DPS = $(DEVICE)-$(PACKAGE)-$(SPEEDGRADE) +DATE = $(shell date +"%Y-%m-%d__%H_%M") +LOGFILE = synthesis_log_$(DATE).txt +export XST_LOGFILE := $(LOGFILE) + + +define XST_FILE +set -tmpdir "projnav.tmp" +set -xsthdpdir "xst" +run +-ifn ../$(MODULE).prj +-ifmt mixed +-ofn $(MODULE) +-ofmt NGC +-p $(DEVICE)-$(SPEEDGRADE)-$(PACKAGE) +-top $(MODULE) +-opt_mode Speed +-opt_level 1 +-power NO +-iuc NO +-keep_hierarchy No +-netlist_hierarchy As_Optimized +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case Maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-dsp_utilization_ratio 100 +-lc Auto +-reduce_control_sets Auto +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style LUT +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-shreg_extract YES +-rom_style Auto +-auto_bram_packing NO +-resource_sharing YES +-async_to_sync NO +-shreg_min_size 2 +-use_dsp48 Auto +-iobuf YES +-max_fanout 100000 +-bufg 16 +-register_duplication YES +-register_balancing No +-optimize_primitives NO +-use_clock_enable Auto +-use_sync_set Auto +-use_sync_reset Auto +-iob Auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 +-infer_ramb8 No +endef + + +define BMM +endef + + +define UT_FILE +-w +-g INIT_9K:Yes +-g DebugBitstream:No +-g Binary:no +-g CRC:Enable +-g Reset_on_err:Yes +-g ConfigRate:26 +-g ProgPin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g ExtMasterCclk_en:No +-g SPI_buswidth:4 +-g TIMER_CFG:0xFFFF +-g multipin_wakeup:No +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No +-g en_sw_gsr:No +-g drive_awake:No +-g sw_clk:Startupclk +-g sw_gwe_cycle:5 +-g sw_gts_cycle:4 +endef + + +define PROGRAM_FPGA_FILE +setMode -bscan +setCable -port auto +Identify +assignFile -p 1 -file "$(MODULE)_update.bit" +Program -p 1 +closeCable +quit +endef + + +define PROGRAM_SPI_FILE +setMode -bs +setCable -port auto +Identify -inferir +identifyMPM +attachflash -position 1 -spi "W25Q64BV" +assignfiletoattachedflash -position 1 -file "$(MODULE)_update.mcs" +Program -p 1 -dataWidth 4 -spionly -e -v -loadfpga +closeCable +quit +endef + + +export XST_FILE := $(XST_FILE) +export BMM := $(BMM) +export UT_FILE := $(UT_FILE) +export PROGRAM_FPGA_FILE := $(PROGRAM_FPGA_FILE) +export PROGRAM_SPI_FILE := $(PROGRAM_SPI_FILE) + + +all: + @echo "check - look for timing and other synthesis issues" + @echo "xst - generate ngc file (netlist, replaces edif and netlist constrains)" + @echo "translate - generate ngd file (native generic database [reduced to primitives])" + @echo "map - generate ncd file (native ciruit description)" + @echo "par - place&route ncd file (design implementation)" + @echo "trace - generate timing report" + @echo "bitgen - generate bit file (ncd -> bit)" + @echo "update - update bitstream with elf file" + @echo "program - program fpga with bit file" + @echo "genmcs - genrate mcs file" + @echo "genbin - genrate bin(ary) file" + @echo "progspi - program spi flash with mcs file" + @echo "clean" + @echo "..." + @echo "softflow - just update fpga with software (software update program)" + @echo "testflow - time software bitgen trace update program check" + @echo "finalflow - time software bitgen trace update progspi check" + + +softflow: + make software update program + +testflow: + time $(MAKE) software bitgen trace update program check 2>&1 | tee $(XST_LOGFILE) + +finalflow: + time $(MAKE) software bitgen trace update progspi check 2>&1 | tee $(XST_LOGFILE) + + +check: + @echo -e "Timing score: " + @grep --with-filename "Timing Score" $(BUILDDIR)/*.par + @echo -e "\nUnwanted Latches (737): " + @grep --with-filename "WARNING:Xst:737" $(BUILDDIR)/*.syr || echo -n + @echo -e "\nUnassigned signals (653): " + @grep --with-filename "WARNING:Xst:653" $(BUILDDIR)/*.syr || echo -n + @echo -e "\nInternal tristates (2042): " + @grep --with-filename "WARNING:Xst:2042" $(BUILDDIR)/*.syr || echo -n + @echo -e "\nCombinatoric loops (2170): " + @grep --with-filename "WARNING:Xst:2170" $(BUILDDIR)/*.syr || echo -n + @echo -e "\nGated clocks (372): " + @grep --with-filename "WARNING:PhysDesignRules:372" $(BUILDDIR)/*.bgn || echo -n + + +software: sw_timestamp + ### + ############################################################################# + ### (re)compile software + ### + test ! -d $(SOFTWARE) || make all --directory $(SOFTWARE) + + +sw_timestamp: + ### + ############################################################################# + #### update sw timestamp + ### + test ! -d $(SOFTWARE) || make --always-make timestamp --directory $(SOFTWARE) + + +update: $(BUILDDIR)/$(MODULE).bit + ### + ############################################################################# + ### update the bitfile + ### + test ! -d $(SOFTWARE) || data2mem -bm $(BMM_BD_FILE) -bd $(SOFTWARE)/*.elf -bt $(BUILDDIR)/$(MODULE).bit -o b $(MODULE)_update.bit + test -d $(SOFTWARE) || cp $(BUILDDIR)/$(MODULE).bit $(MODULE)_update.bit + + +program: + ### + ############################################################################# + ### configure FPGA + ### + echo "$$PROGRAM_FPGA_FILE" > program_fpga.cmd + impact -batch program_fpga.cmd + + +genbin: $(MODULE)_update.bin + +$(MODULE)_update.bin: $(MODULE)_update.bit + ### + ############################################################################# + ### generate flash file, bin format for manual flashing + ### + promgen -b -p bin -w -o $(MODULE)_update.bin -u 0 $(MODULE)_update.bit + + +genmcs: $(MODULE)_update.mcs + +$(MODULE)_update.mcs: $(MODULE)_update.bit + ### + ############################################################################# + ### generate flash file + ### + promgen -spi -p mcs -w -o $(MODULE)_update.mcs -s 8192 -u 0 $(MODULE)_update.bit + + +progspi: genmcs + ### + ############################################################################# + ### program flash + ### + echo "$$PROGRAM_SPI_FILE" > program_spi.cmd + impact -batch program_spi.cmd + + +clean: + rm -f $(MODULE).prj + rm -f *.log + rm -f _impact.cmd + rm -f *.cfi + rm -f *.prm + rm -rf $(BUILDDIR) + rm -rf _ngo + rm -rf _xmsgs + rm -f $(BMM_FILE) + rm -f $(BMM_BD_FILE) + rm -f $(MODULE).xst + rm -f $(MODULE).ut + rm -f program_fpga.cmd + rm -f program_spi.cmd + + +dir: $(MODULE).prj + ### + ############################################################################# + ### generate build directory + ### + mkdir -p $(BUILDDIR) + mkdir -p $(BUILDDIR)/projnav.tmp + + + +$(MODULE).prj: ../vhdl_files.txt + ### + ############################################################################# + ### generate project file + ### + grep --invert rtl_tb ../vhdl_files.txt | grep --invert "\#" | grep --invert "^$$" | awk '{printf "vhdl %s ../%s\n",$$1,$$2}' > $(MODULE).prj + + +xst: $(MODULE).ngc +translate: $(MODULE).ngd +map: $(MODULE)_map.ncd +par: $(MODULE).ncd + + +hw_timestamp: + ### + ############################################################################# + #### update hw timestamp + ### + test ! -f ../rtl/Makefile || make --directory ../rtl + +$(MODULE).ngc: dir hw_timestamp + ### + ############################################################################# + ### synthesis + ### + echo "$$XST_FILE" > $(MODULE).xst + cd $(BUILDDIR) ; xst -ifn ../$(MODULE).xst -ofn $(MODULE).syr + + +$(MODULE).ngd: $(MODULE).ngc $(UCF_FILE) + ### + ############################################################################# + ### translate + ### + echo "$$BMM" > $(BMM_FILE) + cd $(BUILDDIR) ; ngdbuild -dd _ngo -nt timestamp -uc ../$(UCF_FILE) -bm ../$(BMM_FILE) -p $(DEVICE_DPS) -sd ../$(CORES) $(MODULE).ngc $(MODULE).ngd + +$(MODULE)_map.ncd: $(MODULE).ngd + ### + ############################################################################# + ### map + ### + @# explanation of map parameters: + @# -p part number + @# -mt multi-threading + @# -w overwrite existing files + @# -logic_opt logic optimization + @# -ol overall effor level (std|high) + @# -t placer cost table + @# -xt extra placer cost table (0..5) + @# -register_duplication duplicate registers + @# -global_opt Global Optimization (off|speed|area|power) + @# -ir ignore RLOCs + @# -pr pack registers in IO (off|i|o|b) + @# -lc lut combining (auto|area|off) + @# -power Virtex 6 Power Optimization (on|off|high|xe) + @# -detail Generate Detailed MAP Report + @# -o Output File Name + @# -bp enables block RAM mapping + cd $(BUILDDIR) ; export XIL_MAP_NODRC; export XIL_PAR_DESIGN_CHECK_VERBOSE=1; export XIL_PAR_ALLOW_LVDS_LOC_OVERRIDE=1; map -p $(DEVICE_DPS) -mt 1 -w -logic_opt off -ol high -t 22 -xt 5 -register_duplication on -global_opt off -ir off -pr b -lc off -power off -detail -o $(MODULE)_map.ncd $(MODULE).ngd $(MODULE).pcf + + +$(MODULE).ncd: $(MODULE)_map.ncd + ### + ############################################################################# + ### place & route + ### + @# -ol = Overall effort level. high is maximum effort. + @# Default: high except Virtex-4 and Spartan-3 architectures + @# std (standard) for older architectures + @# -pl = Placer effort level. high is maximum effort. Overrides + @# any placer effort level implied by "-ol" option. + @# Default: high for Virtex-4 and Spartan-3 architectures + @# Not supported for newer architectures. + @# -rl = Router effort level. high is maximum effort. Overrides + @# any router effort level implied by "-ol" option. + @# Default: high for Virtex-4 and Spartan-3 architectures + @# Not supported for newer architectures + @# -xe = Extra effort level. c (Continue on Impossible) is maximum effort. + @# Default: none + @# -mt = Multi-threading enabled. 4 is the maximum number of threads. + @# Default: off except Virtex-4 and Spartan-3 architectures + @# Supported only for newer architectures. + @# -t = Placer cost table entry. Start at this entry. + @# Default: 1 for Virtex-4 and Spartan-3 architectures + @# Not supported for newer architectures + @# -p = Don't run the placer. (Keep current placement) + @# -k = Re-entrant route. Keep the current placement. Continue the routing + @# using the existing routing as a starting point. + @# -r = Don't run the router. + @# -w = Overwrite. Allows overwrite of an existing file (including input + @# file). If specified output is a directory, allows files in + @# directory to be overwritten. + @# -f = Read par command line arguments and switches from file. + @# -filter = Message Filter file name (for example "filter.filter"). If + @# specified, the contents of this file will be used to filter messages + @# from this application. The filter file can be created using Xreport. + @# -smartguide = Enables SmartGuide using guidefile.ncd as the guide file. + @# -x = Ignore user timing constraints in physical constraints file and + @# generate timing constraints automatically for all internal clocks to + @# increase performance. Note: the level of performance achieved will + @# be dictated by the effort level (-ol std|high) chosen. + @# -nopad = Turns off generation of the pad report. + @# Default: Pad Report Generated + @# -power = Power Aware Par. Optimizes the capacitance of non-timing-driven + @# design signals. + @# Default: off + @# -activityfile <activityfile.vcd|saif> = Switching activity data file to + @# guide power optimization. This option is only valid if the + @# "-power on" option has been used. + @# -intstyle = Indicate contextual information when invoking Xilinx applications + @# within a flow or project environment. + @# The mode "xflow" indicates that the program is being run as part of a + @# batch flow. The mode "silent" indicates that no output will be + @# displayed to the screen. The mode "ise" indicates that the program is being + @# run as part of an integrated design environment. + @# Default: Program is run as a standalone application. + @# -ise = Use supplied ISE project repository file. + @# -ntd = Ignore Timing constraints in physical constraints file and do NOT + @# generate timing constraints automatically. + @# <infile> = Name of input NCD file. + @# <outfile> = Name of output NCD file or output directory. + @# Use format "<outfile>.ncd" or "<outfile>.dir". + @# <pcffile> = Name of physical constraints file. + cd $(BUILDDIR) ; par -w -ol high $(MODULE)_map.ncd $(MODULE).ncd $(MODULE).pcf + + +trace: + cd $(BUILDDIR) ; trce -v 5 -u 10 -fastpaths -xml $(MODULE).twx -o $(MODULE).twr $(MODULE).ncd $(MODULE).pcf + + +bitgen: $(MODULE).ncd + ### + ############################################################################# + ### generate bitfile + ### + echo "$$UT_FILE" > $(MODULE).ut + cd $(BUILDDIR) ; bitgen -f ../$(MODULE).ut $(MODULE).ncd + + +firmware: $(MODULE)_update.mcs $(MODULE)_update.bin + mkdir -p firmware_$(DATE) + cp Makefile firmware_$(DATE) + cp $(MODULE)_update.bit firmware_$(DATE) + cp $(MODULE)_update.bin firmware_$(DATE) + cp $(MODULE)_update.mcs firmware_$(DATE) + zip -r firmware_$(DATE) firmware_$(DATE)/* + diff --git a/mig_test/synthesis/top.ucf b/mig_test/synthesis/top.ucf new file mode 100644 index 0000000..e8e0f8f --- /dev/null +++ b/mig_test/synthesis/top.ucf @@ -0,0 +1,312 @@ +# voltage +CONFIG VCCAUX = "2.5"; + + +## system stuff +#125MHz clock +NET CLK LOC = AA12 | IOSTANDARD = LVCMOS33; +NET RESET_N LOC = A4 | IOSTANDARD = LVCMOS33 | PULLDOWN; +NET POWER_FAIL_N LOC = A2; # IO_L83P_3 +NET WATCHDOG LOC = V9 | IOSTANDARD = LVCMOS33; # WATCHDOG INPUT, IO_L50N_2 + +## user clock +NET user_clk LOC = Y13; # U12 + +## DDR3 SDRAM +NET MCB1_DRAM_A<0> LOC = F21 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_A<1> LOC = F22 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_A<2> LOC = E22 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_A<3> LOC = G20 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_A<4> LOC = F20 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_A<5> LOC = K20 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_A<6> LOC = K19 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_A<7> LOC = E20 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_A<8> LOC = C20 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_A<9> LOC = C22 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_A<10> LOC = G19 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_A<11> LOC = F19 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_A<12> LOC = D22 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_A<13> LOC = D19 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_A<14> LOC = D20 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_BA<0> LOC = J17 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_BA<1> LOC = K17 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_BA<2> LOC = H18 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_CAS_B LOC = H22 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_CKE LOC = D21 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_CK_N LOC = J19 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_CK_P LOC = H20 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQ<0> LOC = N20 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQ<1> LOC = N22 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQ<2> LOC = M21 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQ<3> LOC = M22 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQ<4> LOC = J20 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQ<5> LOC = J22 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQ<6> LOC = K21 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQ<7> LOC = K22 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQ<8> LOC = P21 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQ<9> LOC = P22 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQ<10> LOC = R20 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQ<11> LOC = R22 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQ<12> LOC = U20 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQ<13> LOC = U22 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQ<14> LOC = V21 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_DQ<15> LOC = V22 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_LDM LOC = L19 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_LDQS_N LOC = L22 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_LDQS_P LOC = L20 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_ODT LOC = G22 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_RAS_B LOC = H21 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_RESET_B LOC = F18 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_UDM LOC = M20 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_UDQS_N LOC = T22 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_UDQS_P LOC = T21 | IOSTANDARD = SSTL15_II; +NET MCB1_DRAM_WE_B LOC = H19 | IOSTANDARD = SSTL15_II; +# +NET MCB3_DRAM_A<0> LOC = H2 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_A<1> LOC = H1 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_A<2> LOC = H5 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_A<3> LOC = K6 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_A<4> LOC = F3 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_A<5> LOC = K3 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_A<6> LOC = J4 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_A<7> LOC = H6 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_A<8> LOC = E3 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_A<9> LOC = E1 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_A<10> LOC = G4 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_A<11> LOC = C1 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_A<12> LOC = D1 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_A<13> LOC = G6 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_A<14> LOC = F5 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_BA<0> LOC = G3 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_BA<1> LOC = G1 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_BA<2> LOC = F1 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_CAS_B LOC = K4 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_CKE LOC = D2 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_CK_N LOC = H3 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_CK_P LOC = H4 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQ<0> LOC = N3 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQ<1> LOC = N1 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQ<2> LOC = M2 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQ<3> LOC = M1 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQ<4> LOC = J3 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQ<5> LOC = J1 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQ<6> LOC = K2 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQ<7> LOC = K1 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQ<8> LOC = P2 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQ<9> LOC = P1 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQ<10> LOC = R3 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQ<11> LOC = R1 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQ<12> LOC = U3 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQ<13> LOC = U1 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQ<14> LOC = V2 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_DQ<15> LOC = V1 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_LDM LOC = L4 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_LDQS_N LOC = L1 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_LDQS_P LOC = L3 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_ODT LOC = J6 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_RAS_B LOC = K5 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_RESET_B LOC = C3 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_UDM LOC = M3 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_UDQS_N LOC = T1 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_UDQS_P LOC = T2 | IOSTANDARD = SSTL15_II; +NET MCB3_DRAM_WE_B LOC = F2 | IOSTANDARD = SSTL15_II; + +## Ethernet PHY +#NET PHY_125 LOC = AA12; # used as clk +NET PHY_MDIO LOC = AB3; +NET PHY_MDC LOC = AA2 | IOSTANDARD = LVCMOS33; +NET PHY_INT LOC = AB2; +NET PHY_RESET_B LOC = T15 | IOSTANDARD = LVCMOS33; +NET PHY_CRS LOC = T14; +NET PHY_COL LOC = R13; +NET PHY_TXEN LOC = AB16 | IOSTANDARD = LVCMOS33; +NET PHY_TXCLK LOC = W12; +NET PHY_TXER LOC = AB18 | IOSTANDARD = LVCMOS33; +NET PHY_TXD<0> LOC = AA18 | IOSTANDARD = LVCMOS33; +NET PHY_TXD<1> LOC = AB14 | IOSTANDARD = LVCMOS33; +NET PHY_TXD<2> LOC = AA16 | IOSTANDARD = LVCMOS33; +NET PHY_TXD<3> LOC = W14 | IOSTANDARD = LVCMOS33; +NET PHY_TXD<4> LOC = T16 | IOSTANDARD = LVCMOS33; +NET PHY_TXD<5> LOC = Y14 | IOSTANDARD = LVCMOS33; +NET PHY_TXD<6> LOC = V15 | IOSTANDARD = LVCMOS33; +NET PHY_TXD<7> LOC = AA14 | IOSTANDARD = LVCMOS33; +NET PHY_GTXCLK LOC = R11 | IOSTANDARD = LVCMOS33; +NET PHY_RXCLK LOC = Y11; +NET PHY_RXER LOC = Y8; +NET PHY_RXDV LOC = Y4; +NET PHY_RXD<0> LOC = Y3; +NET PHY_RXD<1> LOC = W8; +NET PHY_RXD<2> LOC = W4; +NET PHY_RXD<3> LOC = U9; +NET PHY_RXD<4> LOC = V7; +NET PHY_RXD<5> LOC = V5; +NET PHY_RXD<6> LOC = W9; +NET PHY_RXD<7> LOC = U6; + +## quad SPI Flash (W25Q64BV) +NET SPI_FLASH_CSO_B LOC = T5 | IOSTANDARD = LVCMOS33; +NET SPI_FLASH_CCLK LOC = Y21 | IOSTANDARD = LVCMOS33; +NET SPI_FLASH_IO<0> LOC = AB20; # MOSI/di +NET SPI_FLASH_IO<1> LOC = AA20; # MISO/do +NET SPI_FLASH_IO<2> LOC = U14; # MISO2/wp_n +NET SPI_FLASH_IO<3> LOC = U13; # MISO3/hold_n + +## EEPROM (48bit MAC address, DS2502-E48) +NET MAC_DATA LOC = T11; + +## B2B J1 user IO +NET B2B_B2_L57_N LOC = AB4; +NET B2B_B2_L57_P LOC = AA4; +NET B2B_B2_L49_N LOC = AB6; +NET B2B_B2_L49_P LOC = AA6; +# +NET B2B_B2_L48_N LOC = AB7; +NET B2B_B2_L48_P LOC = Y7; +NET B2B_B2_L45_N LOC = AB8; +NET B2B_B2_L45_P LOC = AA8; +# +NET B2B_B2_L43_N LOC = AB9; +NET B2B_B2_L43_P LOC = Y9; +NET B2B_B2_L41_N LOC = AB10; +NET B2B_B2_L41_P LOC = AA10; +# +NET B2B_B2_L21_P LOC = Y15; +NET B2B_B2_L21_N LOC = AB15; +NET B2B_B2_L15_P LOC = Y17; +NET B2B_B2_L15_N LOC = AB17; +# +NET B2B_B2_L31_N LOC = AB12; # single ended +# +NET B2B_B2_L32_N LOC = AB11; # single ended +# +NET B2B_B2_L60_P LOC = T7; +NET B2B_B2_L60_N LOC = R7; +NET B2B_B2_L59_N LOC = R8; +NET B2B_B2_L59_P LOC = R9; +# +NET B2B_B2_L44_N LOC = Y10; +NET B2B_B2_L44_P LOC = W10; +NET B2B_B2_L42_N LOC = W11; +NET B2B_B2_L42_P LOC = V11; +# +NET B2B_B2_L18_P LOC = V13; +NET B2B_B2_L18_N LOC = W13; +NET B2B_B2_L8_N LOC = U16; +NET B2B_B2_L8_P LOC = U17; +# +NET B2B_B2_L11_P LOC = V17; +NET B2B_B2_L11_N LOC = W17; +NET B2B_B2_L6_P LOC = W18; +NET B2B_B2_L6_N LOC = Y18; +# +NET B2B_B2_L5_P LOC = Y19; +NET B2B_B2_L5_N LOC = AB19; +NET B2B_B2_L9_N LOC = V18; +NET B2B_B2_L9_P LOC = V19; +# +NET B2B_B2_L4_N LOC = T17; +NET B2B_B2_L4_P LOC = T18; +# +NET B2B_B2_L29_N LOC = Y12; # single ended +# +NET B2B_B2_L10_N LOC = R15; +NET B2B_B2_L10_P LOC = R16; +NET B2B_B2_L2_N LOC = AB21; +NET B2B_B2_L2_P LOC = AA21; + + +## B2B J2 user IO +NET B2B_B3_L60_N LOC = B1; +NET B2B_B3_L60_P LOC = B2; +# +NET B2B_B3_L9_N LOC = T3 | IOSTANDARD = LVCMOS15; +NET B2B_B3_L9_P LOC = T4 | IOSTANDARD = LVCMOS15; +NET B2B_B0_L3_P LOC = D6; +NET B2B_B0_L3_N LOC = C6; +# +NET B2B_B3_L59_P LOC = J7 | IOSTANDARD = LVCMOS15; +NET B2B_B3_L59_N LOC = H8 | IOSTANDARD = LVCMOS15; +NET B2B_B0_L32_P LOC = D7; +NET B2B_B0_L32_N LOC = D8; +# +NET B2B_B0_L7_N LOC = C8; +NET B2B_B0_L7_P LOC = D9; +NET B2B_B0_L33_N LOC = C10; +NET B2B_B0_L33_P LOC = D10; +# +NET B2B_B0_L36_P LOC = D11; +NET B2B_B0_L36_N LOC = C12; +NET B2B_B0_L49_P LOC = D14; +NET B2B_B0_L49_N LOC = C14; +# +NET B2B_B0_L62_P LOC = D15; +NET B2B_B0_L62_N LOC = C16; +NET B2B_B0_L66_P LOC = E16; +NET B2B_B0_L66_N LOC = D17; +# +NET B2B_B1_L10_P LOC = F16; +NET B2B_B1_L10_N LOC = F17; +NET B2B_B1_L9_P LOC = G16; +NET B2B_B1_L9_N LOC = G17; +# +NET B2B_B1_L21_N LOC = J16; +NET B2B_B1_L21_P LOC = K16; +NET B2B_B1_L61_P LOC = L17; +NET B2B_B1_L61_N LOC = K18; +# +#NET B2B_B0_L1 LOC = A4; # used as reset_n +# +NET B2B_B0_L2_P LOC = C5; +NET B2B_B0_L2_N LOC = A5; +NET B2B_B0_L4_N LOC = A6; +NET B2B_B0_L4_P LOC = B6; +# +NET B2B_B0_L5_N LOC = A7; +NET B2B_B0_L5_P LOC = C7; +NET B2B_B0_L6_N LOC = A8; +NET B2B_B0_L6_P LOC = B8; +# +NET B2B_B0_L8_N LOC = A9; +NET B2B_B0_L8_P LOC = C9; +NET B2B_B0_L34_N LOC = A10; +NET B2B_B0_L34_P LOC = B10; +# +NET B2B_B0_L35_N LOC = A11; +NET B2B_B0_L35_P LOC = C11; +NET B2B_B0_L37_N LOC = A12; +NET B2B_B0_L37_P LOC = B12; +# +NET B2B_B0_L38_N LOC = A13; +NET B2B_B0_L38_P LOC = C13; +NET B2B_B0_L50_N LOC = A14; +NET B2B_B0_L50_P LOC = B14; +# +NET B2B_B0_L51_N LOC = A15; +NET B2B_B0_L51_P LOC = C15; +NET B2B_B0_L63_N LOC = A16; +NET B2B_B0_L63_P LOC = B16; +# +NET B2B_B0_L64_N LOC = A17; +NET B2B_B0_L64_P LOC = C17; +NET B2B_B0_L65_N LOC = A18; +NET B2B_B0_L65_P LOC = B18; +# +NET B2B_B1_L20_P LOC = A20; +NET B2B_B1_L20_N LOC = A21; +NET B2B_B1_L19_P LOC = B21; +NET B2B_B1_L19_N LOC = B22; +NET B2B_B1_L59 LOC = P19; + + +## misc +NET USER_LED_N LOC = T20 | IOSTANDARD = LVCMOS15; # on board LED +NET AV<0> LOC = U19 | PULLUP | TIG; +NET AV<1> LOC = V20 | PULLUP | TIG; +NET AV<2> LOC = M17 | PULLUP | TIG; +NET AV<3> LOC = M18 | PULLUP | TIG; +NET BR<0> LOC = P17 | PULLUP | TIG; +NET BR<1> LOC = N16 | PULLUP | TIG; +NET BR<2> LOC = P18 | PULLUP | TIG; +NET BR<3> LOC = R19 | PULLUP | TIG; + +NET reprog_n LOC = H16 | IOSTANDARD = "LVCMOS15"; #REPROGRAMMING diff --git a/mig_test/vhdl_files.txt b/mig_test/vhdl_files.txt new file mode 100644 index 0000000..c19a027 --- /dev/null +++ b/mig_test/vhdl_files.txt @@ -0,0 +1,2 @@ +work rtl/top.vhd +work rtl_tb/top_tb.vhd |
