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-rw-r--r--zpu/hdl/example/sim_small_fpga_top.vhd2
-rw-r--r--zpu/hdl/example/sim_small_fpga_top_noint.vhd2
-rw-r--r--zpu/hdl/example_medium/sim_fpga_top.vhd2
-rw-r--r--zpu/hdl/zpu4/core/zpu_core.vhd6
-rw-r--r--zpu/hdl/zpu4/core/zpu_core_small.vhd6
-rw-r--r--zpu/hdl/zpu4/core/zpupkg.vhd2
6 files changed, 10 insertions, 10 deletions
diff --git a/zpu/hdl/example/sim_small_fpga_top.vhd b/zpu/hdl/example/sim_small_fpga_top.vhd
index e671460..8054489 100644
--- a/zpu/hdl/example/sim_small_fpga_top.vhd
+++ b/zpu/hdl/example/sim_small_fpga_top.vhd
@@ -115,7 +115,7 @@ begin
zpu: zpu_core port map (
clk => clk ,
- areset => areset,
+ reset => areset,
enable => enable,
in_mem_busy => mem_busy,
mem_read => mem_read,
diff --git a/zpu/hdl/example/sim_small_fpga_top_noint.vhd b/zpu/hdl/example/sim_small_fpga_top_noint.vhd
index 0edb8c7..1a83131 100644
--- a/zpu/hdl/example/sim_small_fpga_top_noint.vhd
+++ b/zpu/hdl/example/sim_small_fpga_top_noint.vhd
@@ -113,7 +113,7 @@ begin
zpu: zpu_core port map (
clk => clk ,
- areset => areset,
+ reset => areset,
enable => enable,
in_mem_busy => mem_busy,
mem_read => mem_read,
diff --git a/zpu/hdl/example_medium/sim_fpga_top.vhd b/zpu/hdl/example_medium/sim_fpga_top.vhd
index a10da37..a0819de 100644
--- a/zpu/hdl/example_medium/sim_fpga_top.vhd
+++ b/zpu/hdl/example_medium/sim_fpga_top.vhd
@@ -96,7 +96,7 @@ signal break : std_logic;
begin
zpu: zpu_core port map (
clk => clk ,
- areset => areset,
+ reset => areset,
enable => enable,
in_mem_busy => mem_busy,
mem_read => mem_read,
diff --git a/zpu/hdl/zpu4/core/zpu_core.vhd b/zpu/hdl/zpu4/core/zpu_core.vhd
index e2e4781..1b95444 100644
--- a/zpu/hdl/zpu4/core/zpu_core.vhd
+++ b/zpu/hdl/zpu4/core/zpu_core.vhd
@@ -65,7 +65,7 @@ use work.zpupkg.all;
entity zpu_core is
port (
clk : in std_logic;
- areset : in std_logic;
+ reset : in std_logic;
enable : in std_logic;
in_mem_busy : in std_logic;
mem_read : in std_logic_vector(wordSize-1 downto 0);
@@ -230,7 +230,7 @@ begin
decSp <= sp - 1;
- opcodeControl : process(clk, areset)
+ opcodeControl : process(clk, reset)
variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0);
variable spOffset : unsigned(4 downto 0);
variable tSpOffset : unsigned(4 downto 0);
@@ -239,7 +239,7 @@ begin
variable tDecodedOpcode : InsnArray;
variable tMultResult : unsigned(wordSize*2-1 downto 0);
begin
- if areset = '1' then
+ if reset = '1' then
state <= State_Idle;
break <= '0';
sp <= unsigned(spStart(maxAddrBitIncIO downto minAddrBit));
diff --git a/zpu/hdl/zpu4/core/zpu_core_small.vhd b/zpu/hdl/zpu4/core/zpu_core_small.vhd
index b975977..9ac35a8 100644
--- a/zpu/hdl/zpu4/core/zpu_core_small.vhd
+++ b/zpu/hdl/zpu4/core/zpu_core_small.vhd
@@ -45,7 +45,7 @@ entity zpu_core is
port (
clk : in std_logic;
-- asynchronous reset signal
- areset : in std_logic;
+ reset : in std_logic;
-- this particular implementation of the ZPU does not
-- have a clocked enable signal
enable : in std_logic;
@@ -312,11 +312,11 @@ begin
end process;
- opcodeControl: process(clk, areset)
+ opcodeControl: process(clk, reset)
variable spOffset : unsigned(4 downto 0);
begin
- if areset = '1' then
+ if reset = '1' then
state <= State_Resync;
break <= '0';
sp <= unsigned(spStart(maxAddrBit downto minAddrBit));
diff --git a/zpu/hdl/zpu4/core/zpupkg.vhd b/zpu/hdl/zpu4/core/zpupkg.vhd
index a6e749d..0363aca 100644
--- a/zpu/hdl/zpu4/core/zpupkg.vhd
+++ b/zpu/hdl/zpu4/core/zpupkg.vhd
@@ -110,7 +110,7 @@ package zpupkg is
component zpu_core is
port (
clk : in std_logic;
- areset : in std_logic;
+ reset : in std_logic;
enable : in std_logic;
in_mem_busy : in std_logic;
mem_read : in std_logic_vector(wordSize-1 downto 0);
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