* moved ZPU core files to seperate folder

	* deleted some obsolete files

15 files changed, 0 insertions, 868 deletions

diff --git a/zpu/hdl/zpu4/src/zpu_config.vhd b/zpu/hdl/zpu4/core/zpu_config.vhd
index a13c0bf..a13c0bf 100644
--- a/zpu/hdl/zpu4/src/zpu_config.vhd
+++ b/zpu/hdl/zpu4/core/zpu_config.vhd
diff --git a/zpu/hdl/zpu4/src/zpu_core.vhd b/zpu/hdl/zpu4/core/zpu_core.vhd
index 37fa2d1..37fa2d1 100644
--- a/zpu/hdl/zpu4/src/zpu_core.vhd
+++ b/zpu/hdl/zpu4/core/zpu_core.vhd
diff --git a/zpu/hdl/zpu4/src/zpu_core_small.vhd b/zpu/hdl/zpu4/core/zpu_core_small.vhd
index 9cda01c..9cda01c 100644
--- a/zpu/hdl/zpu4/src/zpu_core_small.vhd
+++ b/zpu/hdl/zpu4/core/zpu_core_small.vhd
diff --git a/zpu/hdl/zpu4/src/zpu_core_small_wip.vhd b/zpu/hdl/zpu4/core/zpu_core_small_wip.vhd
index 8d87804..8d87804 100644
--- a/zpu/hdl/zpu4/src/zpu_core_small_wip.vhd
+++ b/zpu/hdl/zpu4/core/zpu_core_small_wip.vhd
diff --git a/zpu/hdl/zpu4/src/zpupkg.vhd b/zpu/hdl/zpu4/core/zpupkg.vhd
index f3800b0..f3800b0 100644
--- a/zpu/hdl/zpu4/src/zpupkg.vhd
+++ b/zpu/hdl/zpu4/core/zpupkg.vhd
diff --git a/zpu/hdl/zpu4/src/dmipssmalltrace.do b/zpu/hdl/zpu4/src/dmipssmalltrace.do
deleted file mode 100644
index eb4c6fe..0000000
--- a/zpu/hdl/zpu4/src/dmipssmalltrace.do
+++ /dev/null
@@ -1,26 +0,0 @@
-set BreakOnAssertion 1

-vlib work

-

-vcom -93 -explicit  zpu_config_trace.vhd

-vcom -93 -explicit  zpupkg.vhd

-vcom -93 -explicit  txt_util.vhd

-vcom -93 -explicit  sim_fpga_top.vhd

-vcom -93 -explicit  zpu_core_small.vhd

-vcom -93 -explicit  bram_dmips.vhd

-vcom -93 -explicit  dram_dmips.vhd

-vcom -93 -explicit  timer.vhd

-vcom -93 -explicit  io.vhd

-vcom -93 -explicit  trace.vhd

-

-

-vsim fpga_top

-view wave

-

-add wave -recursive fpga_top/zpu/*

-#--add wave -recursive fpga_top/ioMap/*

-#add wave -recursive fpga_top/*

-view structure

-

-

-# run ZPU

-run 5 ms

diff --git a/zpu/hdl/zpu4/src/dmipssmalltrace_ghdl.sh b/zpu/hdl/zpu4/src/dmipssmalltrace_ghdl.sh
deleted file mode 100644
index 5e43b64..0000000
--- a/zpu/hdl/zpu4/src/dmipssmalltrace_ghdl.sh
+++ /dev/null
@@ -1,26 +0,0 @@
-#!/bin/sh

-

-UNISIM_DIR="'location of GHDL objects for unisim library'/unisim_v93"

-IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work -P${UNISIM_DIR}"

-MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding"

-

-if test ! -e work; then

-    echo "Building work library..."

-    mkdir work

-    ghdl -i ${IMPORT_OPTIONS} zpu_config_trace.vhd

-    ghdl -i ${IMPORT_OPTIONS} zpupkg.vhd

-    ghdl -i ${IMPORT_OPTIONS} txt_util.vhd

-    ghdl -i ${IMPORT_OPTIONS} sim_fpga_top.vhd

-    ghdl -i ${IMPORT_OPTIONS} zpu_core_small.vhd

-    ghdl -i ${IMPORT_OPTIONS} bram_dmips.vhd

-    ghdl -i ${IMPORT_OPTIONS} dram_dmips.vhd

-    ghdl -i ${IMPORT_OPTIONS} timer.vhd

-    ghdl -i ${IMPORT_OPTIONS} io.vhd

-    ghdl -i ${IMPORT_OPTIONS} trace.vhd

-fi

-

-echo "Compiling design..."

-if ghdl -m ${MAKE_OPTIONS} fpga_top; then

-    echo "Compilation finished, start simulation with"

-    echo "  ./fpga_top --stop-time=1ms"

-fi

diff --git a/zpu/hdl/zpu4/src/dmipstrace.do b/zpu/hdl/zpu4/src/dmipstrace.do
deleted file mode 100644
index 64cf8fd..0000000
--- a/zpu/hdl/zpu4/src/dmipstrace.do
+++ /dev/null
@@ -1,30 +0,0 @@
-# Xilinx WebPack modelsim script

-#

-# cd C:/workspace/zpu/zpu/hdl/zpu4/src

-# do dmipstrace.do

-

-set BreakOnAssertion 1

-vlib work

-

-vcom -93 -explicit  zpu_config_trace.vhd

-vcom -93 -explicit  zpupkg.vhd

-vcom -93 -explicit  txt_util.vhd

-vcom -93 -explicit  sim_fpga_top.vhd

-vcom -93 -explicit  zpu_core.vhd

-vcom -93 -explicit  dram_dmips.vhd

-vcom -93 -explicit  timer.vhd

-vcom -93 -explicit  io.vhd

-vcom -93 -explicit  trace.vhd

-

-

-vsim fpga_top

-view wave

-

-add wave -recursive fpga_top/zpu/*

-#--add wave -recursive fpga_top/ioMap/*

-#add wave -recursive fpga_top/*

-view structure

-

-

-# run ZPU

-run 5 ms

diff --git a/zpu/hdl/zpu4/src/dmipstrace_ghdl.sh b/zpu/hdl/zpu4/src/dmipstrace_ghdl.sh
deleted file mode 100644
index 3be392f..0000000
--- a/zpu/hdl/zpu4/src/dmipstrace_ghdl.sh
+++ /dev/null
@@ -1,25 +0,0 @@
-#!/bin/sh

-

-UNISIM_DIR="'location of GHDL objects for unisim library'/unisim_v93"

-IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work -P${UNISIM_DIR}"

-MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding"

-

-if test ! -e work; then

-    echo "Building work library..."

-    mkdir work

-    ghdl -i ${IMPORT_OPTIONS} zpu_config_trace.vhd

-    ghdl -i ${IMPORT_OPTIONS} zpupkg.vhd

-    ghdl -i ${IMPORT_OPTIONS} txt_util.vhd

-    ghdl -i ${IMPORT_OPTIONS} sim_fpga_top.vhd

-    ghdl -i ${IMPORT_OPTIONS} zpu_core.vhd

-    ghdl -i ${IMPORT_OPTIONS} dram_dmips.vhd

-    ghdl -i ${IMPORT_OPTIONS} timer.vhd

-    ghdl -i ${IMPORT_OPTIONS} io.vhd

-    ghdl -i ${IMPORT_OPTIONS} trace.vhd

-fi

-

-echo "Compiling design..."

-if ghdl -m ${MAKE_OPTIONS} fpga_top; then

-    echo "Compilation finished, start simulation with"

-    echo "  ./fpga_top --stop-time=2500us"

-fi

diff --git a/zpu/hdl/zpu4/src/log.txt b/zpu/hdl/zpu4/src/log.txt
deleted file mode 100644
index 7a82879..0000000
--- a/zpu/hdl/zpu4/src/log.txt
+++ /dev/null
@@ -1,380 +0,0 @@
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diff --git a/zpu/hdl/zpu4/src/niltrace.vhd b/zpu/hdl/zpu4/src/niltrace.vhd
deleted file mode 100644
index 40fc1ca..0000000
--- a/zpu/hdl/zpu4/src/niltrace.vhd
+++ /dev/null
@@ -1,26 +0,0 @@
-library ieee;

-use ieee.std_logic_1164.all;

-use IEEE.STD_LOGIC_UNSIGNED.ALL;

-

-use std.textio.all;

-use work.zpu_config.all;

- 

- 

-entity trace is

-  port(

-       	clk         : in std_logic;

-       	begin_inst  : in std_logic;

-       	pc          : in std_logic_vector(maxAddrBit downto 0);

-		opcode		: in std_logic_vector(7 downto 0);

-		sp			: in std_logic_vector(maxAddrBit downto 2);

-		memA		: in std_logic_vector(wordSize-1 downto 0);

-		busy  : in std_logic);

-end trace;

-   

-   

-architecture behave of trace is

-  

-begin

-

-end behave;

- 

diff --git a/zpu/hdl/zpu4/src/sim_fpga_top.vhd b/zpu/hdl/zpu4/src/sim_fpga_top.vhd
deleted file mode 100644
index 29151af..0000000
--- a/zpu/hdl/zpu4/src/sim_fpga_top.vhd
+++ /dev/null
@@ -1,188 +0,0 @@
---------------------------------------------------------------------------------

--- Company: 

--- Engineer:

---

--- Create Date:    20:15:31 04/14/05

--- Design Name:    

--- Module Name:    fpga_top - behave

--- Project Name:   

--- Target Device:  

--- Tool versions:  

--- Description:

---

--- Dependencies:

--- 

--- Revision:

--- Revision 0.01 - File Created

--- Additional Comments:

--- 

---------------------------------------------------------------------------------

-library IEEE;

-use IEEE.STD_LOGIC_1164.ALL;

-

----- Uncomment the following library declaration if instantiating

----- any Xilinx primitives in this code.

-library UNISIM;

-use UNISIM.VComponents.all;

-

-library work;

-use work.zpu_config.all;

-

-entity fpga_top is

-end fpga_top;

-

-use work.zpupkg.all;

-

-architecture behave of fpga_top is

-

-

-signal clk : std_logic;

-

-signal	areset			: std_logic;

-

-

-component  zpu_io is

-  generic (

-           log_file:       string  := "log.txt"

-          );

-  port(

-       	clk         : in std_logic;

-       	areset        : in std_logic;

-		busy : out std_logic;

-		writeEnable : in std_logic;

-		readEnable : in std_logic;

-		write	: in std_logic_vector(wordSize-1 downto 0);

-		read	: out std_logic_vector(wordSize-1 downto 0);

-		addr : in std_logic_vector(maxAddrBit downto minAddrBit)

-		);

-end component;

-

-

-

-

-

-signal			  mem_busy : std_logic;

-signal			  mem_read : std_logic_vector(wordSize-1 downto 0);

-signal			  mem_write : std_logic_vector(wordSize-1 downto 0);

-signal			  mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);

-signal			  mem_writeEnable : std_logic; 

-signal			  mem_readEnable : std_logic;

-signal			  mem_writeMask: std_logic_vector(wordBytes-1 downto 0);

-

-signal			  enable : std_logic;

-

-signal			  dram_mem_busy : std_logic;

-signal			  dram_mem_read : std_logic_vector(wordSize-1 downto 0);

-signal			  dram_mem_write : std_logic_vector(wordSize-1 downto 0);

-signal			  dram_mem_writeEnable : std_logic; 

-signal			  dram_mem_readEnable : std_logic;

-signal			  dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0);

-

-

-signal	 		  io_busy : std_logic;

-

-signal			  io_mem_read : std_logic_vector(wordSize-1 downto 0);

-signal			  io_mem_writeEnable : std_logic; 

-signal			  io_mem_readEnable : std_logic;

-

-

-signal			  dram_ready : std_logic;

-signal			  io_ready : std_logic;

-signal			  io_reading : std_logic;

-

-

-signal break : std_logic;

-

-begin

-	poweronreset: roc port map (O => areset);

-

-

-

-	zpu: zpu_core port map (

-		clk => clk ,

-	 	areset => areset,

-	 	enable => enable,

- 		in_mem_busy => mem_busy, 

- 		mem_read => mem_read,

- 		mem_write => mem_write, 

-		out_mem_addr => mem_addr, 

-		out_mem_writeEnable => mem_writeEnable,  

-		out_mem_readEnable => mem_readEnable,

- 		mem_writeMask => mem_writeMask, 

- 		interrupt => '0',

- 		break  => break);

-

-	dram_imp: dram port map (

-		clk => clk ,

-		areset => areset,

- 		mem_busy => dram_mem_busy, 

- 		mem_read => dram_mem_read,

- 		mem_write => mem_write, 

-		mem_addr => mem_addr(maxAddrBit downto 0), 

-		mem_writeEnable => dram_mem_writeEnable,  

-		mem_readEnable => dram_mem_readEnable,

- 		mem_writeMask => mem_writeMask);

-

-

-	ioMap: zpu_io port map (

-       	clk => clk,

-	 	areset => areset,

-		busy => io_busy,

-		writeEnable => io_mem_writeEnable,

-		readEnable => io_mem_readEnable,

-		write	=> mem_write(wordSize-1 downto 0),

-		read	=> io_mem_read,

-		addr => mem_addr(maxAddrBit downto minAddrBit)

-	);

-

-	dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit);

-	dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit);

-	io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit);

-	io_mem_readEnable <= mem_readEnable and mem_addr(ioBit);

-	mem_busy <= io_busy or dram_mem_busy or io_busy;

-	

-	

-

-	-- Memory reads either come from IO or DRAM. We need to pick the right one.

-	memorycontrol:

-	process(dram_mem_read, dram_ready, io_ready, io_mem_read)

-	begin

-		mem_read <= (others => 'U');

-		if dram_ready='1' then

-			mem_read <= dram_mem_read;

-		end if;

-			 

-		if io_ready='1' then

-			mem_read <= io_mem_read;

-		end if;

-	end process;

-

-	

-	io_ready <= (io_reading or io_mem_readEnable) and not io_busy;

-

-	memoryControlSync:

-	process(clk, areset)

-	begin

-		if areset = '1' then

-			enable <= '0';

-			io_reading <= '0';

-			dram_ready <= '0';

-		elsif (clk'event and clk = '1') then

-			enable <= '1';

-			io_reading <= io_busy or io_mem_readEnable; 

-			dram_ready<=dram_mem_readEnable;

-			

-		end if;

-	end process;

-

-	-- wiggle the clock @ 100MHz

-	clock : PROCESS

-	   begin

-   			clk <= '0';

-		   wait for 5 ns; 

-   			clk <= '1';

-		   wait for 5 ns; 

-	end PROCESS clock;

-

-

-end behave;

diff --git a/zpu/hdl/zpu4/src/simzpu_medium.do b/zpu/hdl/zpu4/src/simzpu_medium.do
deleted file mode 100644
index a6c1fe2..0000000
--- a/zpu/hdl/zpu4/src/simzpu_medium.do
+++ /dev/null
@@ -1,28 +0,0 @@
-# Xilinx WebPack modelsim script

-#

-# cd C:/workspace/zpu/zpu/hdl/zpu4/src

-# do simzpu_medium.do

-

-set BreakOnAssertion 1

-vlib work

-

-vcom -93 -explicit  zpu_config_trace.vhd

-vcom -93 -explicit  zpupkg.vhd

-vcom -93 -explicit  txt_util.vhd

-vcom -93 -explicit  sim_fpga_top.vhd

-vcom -93 -explicit  zpu_core.vhd

-vcom -93 -explicit  dram_hello.vhd

-vcom -93 -explicit  timer.vhd

-vcom -93 -explicit  io.vhd

-vcom -93 -explicit  trace.vhd

-

-# run ZPU

-vsim fpga_top

-view wave

-add wave -recursive fpga_top/zpu/*

-#add wave -recursive fpga_top/*

-view structure

-#view signals

-

-# Enough to run tiny programs

-run 1000 ms

diff --git a/zpu/hdl/zpu4/src/simzpu_medium_ghdl.sh b/zpu/hdl/zpu4/src/simzpu_medium_ghdl.sh
deleted file mode 100644
index 7a7f3df..0000000
--- a/zpu/hdl/zpu4/src/simzpu_medium_ghdl.sh
+++ /dev/null
@@ -1,25 +0,0 @@
-#!/bin/sh

-

-UNISIM_DIR="'location of GHDL objects for unisim library'/unisim_v93"

-IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work -P${UNISIM_DIR}"

-MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding"

-

-if test ! -e work; then

-    echo "Building work library..."

-    mkdir work

-    ghdl -i ${IMPORT_OPTIONS} zpu_config_trace.vhd

-    ghdl -i ${IMPORT_OPTIONS} zpupkg.vhd

-    ghdl -i ${IMPORT_OPTIONS} txt_util.vhd

-    ghdl -i ${IMPORT_OPTIONS} sim_fpga_top.vhd

-    ghdl -i ${IMPORT_OPTIONS} zpu_core.vhd

-    ghdl -i ${IMPORT_OPTIONS} dram_hello.vhd

-    ghdl -i ${IMPORT_OPTIONS} timer.vhd

-    ghdl -i ${IMPORT_OPTIONS} io.vhd

-    ghdl -i ${IMPORT_OPTIONS} trace.vhd

-fi

-

-echo "Compiling design..."

-if ghdl -m ${MAKE_OPTIONS} fpga_top; then

-    echo "Compilation finished, start simulation with"

-    echo "  ./fpga_top --stop-time=1ms"

-fi

diff --git a/zpu/hdl/zpu4/src/testlut.vhd b/zpu/hdl/zpu4/src/testlut.vhd
deleted file mode 100644
index 668efcc..0000000
--- a/zpu/hdl/zpu4/src/testlut.vhd
+++ /dev/null
@@ -1,114 +0,0 @@
--- Company: Zylin AS

---

--- Hooks up the ZPU to physical pads to ensure that it is not optimized to

--- oblivion. This is purely to have something to measure LUT usage against.

---

-library IEEE;

-use IEEE.STD_LOGIC_1164.ALL;

-use IEEE.STD_LOGIC_UNSIGNED.ALL;

-

-library work;

-use work.zpu_config.all;

-use work.zpupkg.all;

-

-entity ic300 is

-	port (	-- Clock inputs

-			cpu_clk_p		: in std_logic;

-			

-			-- CPU interface signals

-			cpu_a_p			: in std_logic_vector(20 downto 0);

-			cpu_wr_n_p		: in std_logic_vector(1 downto 0);

-			cpu_cs_n_p		: in std_logic_vector(3 downto 1);

-			cpu_oe_n_p		: in std_logic;

-			cpu_d_p			: out std_logic_vector(15 downto 0);

-			cpu_irq_p		: out std_logic_vector(1 downto 0);

-			cpu_fiq_p		: out std_logic;

-			cpu_wait_n_p	: out std_logic;

-			

-		    sdr_clk_fb_p	: in std_logic		-- DDR clock feedback

-		);

-end ic300;

-

-architecture behave of ic300 is

-

-

-signal io_busy : std_logic;

-signal io_read : std_logic_vector(7 downto 0);

-signal io_write : std_logic_vector(7 downto 0);

-signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit);

-signal io_writeEnable : std_logic;

-signal io_readEnable : std_logic;

-

-

-signal	cpu_we				: std_logic_vector(1 downto 0);

-signal	cpu_re				: std_logic;

-signal	areset				: std_logic;

-

--- Clock module signals

-signal	clk_status			: std_logic_vector(2 downto 0);

-signal	cpu_clk				: std_logic;

-signal	cpu_clk_2x			: std_logic;

-signal	cpu_clk_4x			: std_logic;

-signal	ddr_in_clk			: std_logic;

-

-

--- Internal CPU interface signals

-signal	cpu_din				: std_logic_vector(15 downto 0);

-signal	cpu_dout			: std_logic_vector(15 downto 0);

-signal	cpu_a				: std_logic_vector(20 downto 0);

-

-signal dummy : std_logic_vector(maxAddrBit downto minAddrBit+5);

-

-signal dummy2 : std_logic_vector(wordSize-1 downto 0);

-signal dummy3 : std_logic_vector(wordSize-1 downto 0);

-signal dummy4 : std_logic_vector(wordSize-1 downto 0);

-begin

-

-	areset <= '0';	-- MUST BE CHANGED TO SOMETHING CORRECT

-	

---	cpu_d_p <= (others => '0');

-	cpu_irq_p <= (others => '0');

-	cpu_fiq_p <= '0';

-	cpu_wait_n_p <= '0';

-

-	cpu_d_p(15 downto 15) <= (others => '0');

-

-	-- delay signals going out/in w/1 clk so the 

-	-- ZPU does not have to drive those pins. 

-	-- 

-	-- these registers can be placed close to the ZPU and these

-	-- registers then have a full clock to drive the pins.

-	process(cpu_clk_p, areset)

-	begin

-		if (cpu_clk_p'event and cpu_clk_p = '1') then

-			cpu_d_p(0) <= io_writeEnable;

-			cpu_d_p(1) <= io_readEnable;

-			cpu_d_p(9 downto 2) <= io_write;

-			io_read <= cpu_a_p(7 downto 0);

-			-- 32 read/write registers is plenty realisitic for a minimal size

-			-- soft-CPU

-			cpu_d_p(14 downto 10) <= io_addr(minAddrBit+4 downto minAddrBit);

-		end if;

-	end process;

-	

-

-	zpu: zpu_core port map (

-    	clk => cpu_clk_p ,

-	 	areset => areset,

-	 	enable => '1', 

-	 	

-		in_mem_busy => '0',

-		out_mem_writeEnable => io_writeEnable,

-		out_mem_readEnable => io_readEnable,

-		mem_write(7 downto 0)	=> io_write,

-		mem_write(wordSize-1 downto 8)	=> dummy3(wordSize-1 downto 8),

-		mem_read(7 downto 0)	=> io_read,

-		mem_read(wordSize-1 downto 8) => dummy2(wordSize-1 downto 8),

-		out_mem_addr(maxAddrBitIncIO) => dummy4(maxAddrBitIncIO),

-		out_mem_addr(minAddrBit-1 downto 0) => dummy4(minAddrBit-1 downto 0) ,

-		out_mem_addr(maxAddrBit downto minAddrBit) => io_addr,

-		interrupt => '0'

-	);

-

-

-end behave;