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authoroharboe <oharboe>2008-05-04 19:29:07 +0000
committeroharboe <oharboe>2008-05-04 19:29:07 +0000
commit1362bd4ace3ce962ed744a153e5f969154bb6682 (patch)
tree0b01b48171f661f1eea5741c4b2086f5e49692f7 /zpu/hdl/zpu4/src
parented14271c9743490ebc4947ba7904adaa0d16e279 (diff)
downloadzpu-1362bd4ace3ce962ed744a153e5f969154bb6682.zip
zpu-1362bd4ace3ce962ed744a153e5f969154bb6682.tar.gz
* Make code synthesize on Synopsis
zpu/hdl/zpu4/src/zpu_core_small.vhd zpu/hdl/zpu4/src/io.vhd
Diffstat (limited to 'zpu/hdl/zpu4/src')
-rw-r--r--zpu/hdl/zpu4/src/io.vhd15
-rw-r--r--zpu/hdl/zpu4/src/sim_small_fpga_top.vhd177
-rw-r--r--zpu/hdl/zpu4/src/zpu_core_small.vhd25
3 files changed, 30 insertions, 187 deletions
diff --git a/zpu/hdl/zpu4/src/io.vhd b/zpu/hdl/zpu4/src/io.vhd
index 7a2601f..9e65929 100644
--- a/zpu/hdl/zpu4/src/io.vhd
+++ b/zpu/hdl/zpu4/src/io.vhd
@@ -59,8 +59,9 @@ begin
elsif (clk'event and clk = '1') then
-- timer_we <= '0';
if writeEnable = '1' then
- -- external interface
- if addr=x"2028003" then
+ -- external interface (fixed address)
+ --<JK> extend compare to avoid waring messages
+ if ("000" & addr)=x"2028003" then
-- Write to UART
-- report "" & character'image(conv_integer(memBint)) severity note;
print(l_file, character'val(to_integer(unsigned(write))));
@@ -69,24 +70,26 @@ begin
-- timer_we <= '1';
else
print(l_file, character'val(to_integer(unsigned(write))));
- report "Illegal IO write" severity warning;
+ -- report "Illegal IO write" severity warning;
end if;
end if;
read <= (others => '0');
if (readEnable = '1') then
- if addr=x"1001" then
+ --<JK> extend compare to avoid waring messages
+ if ("000" & addr)=x"0001001" then
read <= (0=>'1', others => '0'); -- recieve empty
elsif addr(12)='1' then
read(7 downto 0) <= timer_read;
elsif addr(11)='1' then
read(7 downto 0) <= ZPU_Frequency;
- elsif addr=x"2028003" then
+ --<JK> extend compare to avoid waring messages
+ elsif ("000" & addr)=x"2028003" then
read <= (others => '0');
else
read <= (others => '0');
read(8) <= '1';
- report "Illegal IO read" severity warning;
+ -- report "Illegal IO read" severity warning;
end if;
end if;
end if;
diff --git a/zpu/hdl/zpu4/src/sim_small_fpga_top.vhd b/zpu/hdl/zpu4/src/sim_small_fpga_top.vhd
deleted file mode 100644
index 5c05881..0000000
--- a/zpu/hdl/zpu4/src/sim_small_fpga_top.vhd
+++ /dev/null
@@ -1,177 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 20:15:31 04/14/05
--- Design Name:
--- Module Name: fpga_top - behave
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
-library UNISIM;
-use UNISIM.VComponents.all;
-
-library work;
-use work.zpu_config.all;
-use work.zpupkg.all;
-
-entity fpga_top is
-end fpga_top;
-
-architecture behave of fpga_top is
-
-
-signal clk : std_logic;
-
-signal areset : std_logic;
-
-
-component zpu_io is
- generic (
- log_file: string := "log.txt"
- );
- port(
- clk : in std_logic;
- areset : in std_logic;
- busy : out std_logic;
- writeEnable : in std_logic;
- readEnable : in std_logic;
- write : in std_logic_vector(wordSize-1 downto 0);
- read : out std_logic_vector(wordSize-1 downto 0);
- addr : in std_logic_vector(maxAddrBit downto minAddrBit)
- );
-end component;
-
-
-
-
-
-signal mem_busy : std_logic;
-signal mem_read : std_logic_vector(wordSize-1 downto 0);
-signal mem_write : std_logic_vector(wordSize-1 downto 0);
-signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);
-signal mem_writeEnable : std_logic;
-signal mem_readEnable : std_logic;
-signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
-
-signal enable : std_logic;
-
-signal dram_mem_busy : std_logic;
-signal dram_mem_read : std_logic_vector(wordSize-1 downto 0);
-signal dram_mem_write : std_logic_vector(wordSize-1 downto 0);
-signal dram_mem_writeEnable : std_logic;
-signal dram_mem_readEnable : std_logic;
-signal dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
-
-
-signal io_busy : std_logic;
-
-signal io_mem_read : std_logic_vector(wordSize-1 downto 0);
-signal io_mem_writeEnable : std_logic;
-signal io_mem_readEnable : std_logic;
-
-
-signal dram_ready : std_logic;
-signal io_ready : std_logic;
-signal io_reading : std_logic;
-
-
-signal break : std_logic;
-
-begin
- poweronreset: roc port map (O => areset);
-
-
-
- zpu: zpu_core port map (
- clk => clk ,
- areset => areset,
- enable => enable,
- in_mem_busy => mem_busy,
- mem_read => mem_read,
- mem_write => mem_write,
- out_mem_addr => mem_addr,
- out_mem_writeEnable => mem_writeEnable,
- out_mem_readEnable => mem_readEnable,
- mem_writeMask => mem_writeMask,
- interrupt => '0',
- break => break);
-
-
- ioMap: zpu_io port map (
- clk => clk,
- areset => areset,
- busy => io_busy,
- writeEnable => io_mem_writeEnable,
- readEnable => io_mem_readEnable,
- write => mem_write,
- read => io_mem_read,
- addr => mem_addr(maxAddrBit downto minAddrBit)
- );
-
- dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit);
- dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit);
- io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit);
- io_mem_readEnable <= mem_readEnable and mem_addr(ioBit);
- mem_busy <= io_busy;
-
-
-
- -- Memory reads either come from IO or DRAM. We need to pick the right one.
- memorycontrol:
- process(dram_mem_read, dram_ready, io_ready, io_mem_read)
- begin
- mem_read <= (others => 'U');
- if dram_ready='1' then
- mem_read <= dram_mem_read;
- end if;
-
- if io_ready='1' then
- mem_read <= (others => '0');
- mem_read <= io_mem_read;
- end if;
- end process;
-
-
- io_ready <= (io_reading or io_mem_readEnable) and not io_busy;
-
- memoryControlSync:
- process(clk, areset)
- begin
- if areset = '1' then
- enable <= '0';
- io_reading <= '0';
- dram_ready <= '0';
- elsif (clk'event and clk = '1') then
- enable <= '1';
- io_reading <= io_busy or io_mem_readEnable;
- dram_ready<=dram_mem_readEnable;
-
- end if;
- end process;
-
- -- wiggle the clock @ 100MHz
- clock : PROCESS
- begin
- clk <= '0';
- wait for 5 ns;
- clk <= '1';
- wait for 5 ns;
- end PROCESS clock;
-
-
-end behave;
diff --git a/zpu/hdl/zpu4/src/zpu_core_small.vhd b/zpu/hdl/zpu4/src/zpu_core_small.vhd
index 0d734d2..9cda01c 100644
--- a/zpu/hdl/zpu4/src/zpu_core_small.vhd
+++ b/zpu/hdl/zpu4/src/zpu_core_small.vhd
@@ -125,6 +125,11 @@ signal memBAddr_stdlogic : std_logic_vector(AddrBitBRAM_range);
signal memBWrite_stdlogic : std_logic_vector(memBWrite'range);
signal memBRead_stdlogic : std_logic_vector(memBRead'range);
+-- debug
+subtype index is integer range 0 to 3;
+signal tOpcode_sel : index;
+
+
begin
traceFileGenerate:
if Generate_Trace generate
@@ -141,6 +146,8 @@ begin
);
end generate;
+ --<JK> not used in this design
+ mem_writeMask <= (others => '1');
memAAddr_stdlogic <= std_logic_vector(memAAddr(AddrBitBRAM_range));
memAWrite_stdlogic <= std_logic_vector(memAWrite);
@@ -160,14 +167,23 @@ begin
memARead <= unsigned(memARead_stdlogic);
memBRead <= unsigned(memBRead_stdlogic);
+tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0));
decodeControl:
- process(memBRead, pc)
+ process(memBRead, pc,tOpcode_sel)
variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0);
begin
- tOpcode := std_logic_vector(memBRead((wordBytes-1-to_integer(pc(minAddrBit-1 downto 0))+1)*8-1 downto (wordBytes-1-to_integer(pc(minAddrBit-1 downto 0)))*8));
-
+ --<JK> not worked with synopsys
+ --<JK> tOpcode := std_logic_vector(memBRead((wordBytes-1-to_integer(pc(minAddrBit-1 downto 0))+1)*8-1 downto (wordBytes-1-to_integer(pc(minAddrBit-1 downto 0)))*8));
+ --<JK> use full case
+ case (tOpcode_sel) is
+ when 0 => tOpcode := std_logic_vector(memBRead(31 downto 24));
+ when 1 => tOpcode := std_logic_vector(memBRead(23 downto 16));
+ when 2 => tOpcode := std_logic_vector(memBRead(15 downto 8));
+ when 3 => tOpcode := std_logic_vector(memBRead(7 downto 0));
+ when others => tOpcode := std_logic_vector(memBRead(7 downto 0));
+ end case;
sampledOpcode <= tOpcode;
if (tOpcode(7 downto 7)=OpCode_Im) then
@@ -230,7 +246,8 @@ begin
out_mem_readEnable <= '0';
memAWrite <= (others => '0');
memBWrite <= (others => '0');
- mem_writeMask <= (others => '1');
+ -- avoid Latch in synopsys
+ -- mem_writeMask <= (others => '1');
elsif (clk'event and clk = '1') then
memAWriteEnable <= '0';
memBWriteEnable <= '0';
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