Merge branch 'master' of https://github.com/zylin/zpu

71 files changed, 25660 insertions, 0 deletions

diff --git a/zpu/hdl/zealot/0README.txt b/zpu/hdl/zealot/0README.txt
new file mode 100644
index 0000000..4bb4546
--- /dev/null
+++ b/zpu/hdl/zealot/0README.txt
@@ -0,0 +1,195 @@
+This is a test release of the ZPU.
+ZPU is a 32 bits stack CPU. This package contains a VHDL implementation
+suitable for FPGAs. It was tested using a Xilinx Spartan 3 1500 FPGA.
+
+The author of the ZPU is Øyvind Harboe (oyvind.harboe zylin.com) and the
+license is the BSD one. Portions of this package were developed by Salvador E.
+Tropea (salvador inti.gob.ar) and others. Some portions are under the GPL
+license.
+
+Øyvind also added a ZPU target to the gcc/gdb.
+
+For more information about the ZPU core please visit:
+http://www.zylin.com/zpu.htm
+http://www.opencores.org/projects.cgi/web/zpu/overview
+
+What are the files?
+-------------------
+
+zpu_medium.vhdl
+ZPU CPU, medium version.
+
+zpu_small.vhdl
+ZPU CPU, small version (Dual Port RAM only!).
+
+zpu_pkg.vhdl
+Package containing the declarations for the ZPU library.
+
+devices/phi_io.vhdl
+The very basic I/O peripherals needed for the standard C library. It includes a
+timer (64 bits clock counter) and an UART (8N1 without FIFO).
+This is known as the PHI I/O layout, this implementation isn't complete. Only
+the above mentioned peripherals are available.
+
+devices/timer.vhdl
+64 bits clock counter maped by the PHI I/O.
+
+devices/trace.vhdl
+This is used for debug purposes. The ZPU have a debug port to connect this
+module. It can generate an execution trace log during the simulation.
+
+devices/txt_util.vhdl
+Useful text handling routines for the simulation.
+
+devices/br_gen.vhdl
+Fixed baud rate generator for the UART.
+
+devices/rx_unit.vhdl
+UART Rx module.
+
+devices/tx_unit.vhdl
+UART Tx module.
+
+roms/rom_pkg.vhdl
+Package containing the declarations for the memories used by the small and
+medium ZPU.
+
+roms/dmips_bram.vhdl
+A memory that maps to Xilinx BRAMs and contains the Dhrystone Benchmark,
+Version 2.1 (Language: C). This memory can be connected to the ZPU for
+simulation or hardware implementations. The code assumes a 50 MHz clock to
+compute the benchmark. The minimum size for this block should be 32 kB.
+
+roms/dmips_dbram.vhdl
+Same as roms/dmips_bram.vhdl, but dual ported. Suitable for the small ZPU.
+
+roms/hello_bram.vhdl
+A memory that maps to Xilinx BRAMs and contains a simple "Hello World!"
+program (C compiled). This memory can be connected to the ZPU for
+simulation or hardware implementations. The minimum size for this block
+should be 16 kB.
+
+roms/hello_dbram.vhdl
+Same as roms/hello_bram.vhdl, but dual ported. Suitable for the small ZPU.
+helpers/zpu_med1.vhdl
+This is a helper that connects a ZPU to its memory and the PHI I/O space.
+
+testbenches/dmips_med1_tb.vhdl
+A simple testbench to simulate the medium ZPU (behavior).
+
+testbenches/small1_tb.vhdl
+A simple testbench to simulate the small ZPU (behavior).
+
+fpga/dmips_med1.vhdl
+A wrapper to implement the medium ZPU in an FPGA. This example was designed
+for a GR-XC3S board from Pender, but should be easily adapted to other
+boards.
+
+fpga/hello_med1.vhdl
+Same as fpga/dmips_med1.vhdl, but uses less memory, enough for the "Hello
+Wold!" test.
+
+fpga/dmips_small1.vhdl
+Same as fpga/dmips_med1.vhdl, but for the small ZPU.
+
+fpga/hello_small1.vhdl
+Same as fpga/hello_med1.vhdl, but for the small ZPU.
+
+
+ZPU library?
+------------
+
+The following files are part of a library I called ZPU:
+
+zpu_pkg.vhdl, zpu_medium.vhdl, zpu_small.vhdl, txt_util.vhdl, timer.vhdl,
+rx_unit.vhdl, tx_unit.vhdl, br_gen.vhdl, phi_io.vhdl and trace.vhdl.
+
+You should group them inside a library called zpu. This procedure is
+tool-chain dependent. In the ISE tool you must add a library and them move
+these files to the library.
+
+If you don't know how to do it with your tools you can just replace all the:
+
+library zpu;
+use zpu.xxxxxx.all;
+
+code by:
+
+library work;
+use work.xxxxxx.all;
+
+
+Which files are needed for simulation?
+--------------------------------------
+
+You need all the files that compose the zpu library plus:
+1) A memory containing a program, i.e.:
+roms/rom_pkg.vhdl and roms/dmips_bram.vhdl
+2) A testbench (including the memory and I/O interconnections):
+aux/zpu_med1.vhdl and testbenches/dmips_med1_tb.vhdl
+3) Be careful to include only the medium or the small ZPU. Also note that
+the small uses dual port BRAMs, i.e. roms/dmips_dbram.vhdl The testbench
+for the small ZPU is small1_tb.vhdl
+
+
+Which files are needed for synthesis?
+-------------------------------------
+
+This is similar to simulation, but:
+1) You should avoid trace.vhdl.
+2) The top level should connect to the FPGA pins, replace dmips_med1_tb.vhdl
+by fpga/dmips_med1.vhdl or fpga/hello_med1.vhdl
+
+
+What resources are needed in the FPGA?
+--------------------------------------
+
+The DMIPS benchmarks needs aprox (Xilinx Spartan 3):
+
+Medium ZPU:
+
+Flip Flops:   498
+LUTs:        1877
+Slices:      1032
+BRAMs:         16
+Multipliers:    3
+
+The hello world example needs less memory:
+
+Flip Flops:   496
+LUTs:        1871
+Slices:      1027
+BRAMs:          8
+Multipliers:    3
+
+
+Small ZPU:
+
+Flip Flops:   373
+LUTs:         706
+Slices:       434
+BRAMs:         16
+
+The hello world example needs less memory:
+
+Flip Flops:   371
+LUTs:         701
+Slices:       431
+BRAMs:          8
+
+
+The board should contain an RS-232 transceiver. A push button (active when
+pressed) is also used, for reset.
+
+
+Ok, I synthetized it and put in the FPGA, what now?
+---------------------------------------------------
+
+Connect the RS-232 board output to a terminal (a PC). Setup the terminal for
+115200 8N1 reception and press the reset push button. You should get the
+program output. You can change the baudrate in the toplevel VHDL.
+
+
+Please tell me if you succeed or failed!
+Enjoy, Salvador E. Tropea
+
diff --git a/zpu/hdl/zealot/BSD b/zpu/hdl/zealot/BSD
new file mode 100644
index 0000000..cca2a5c
--- /dev/null
+++ b/zpu/hdl/zealot/BSD
@@ -0,0 +1,20 @@
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions
+are met:
+
+1. Redistributions of source code must retain the above copyright
+   notice, this list of conditions and the following disclaimer.
+2. Redistributions in binary form must reproduce the above copyright
+   notice, this list of conditions and the following disclaimer in the
+   documentation and/or other materials provided with the distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
diff --git a/zpu/hdl/zealot/GPL_V2 b/zpu/hdl/zealot/GPL_V2
new file mode 100644
index 0000000..21b9363
--- /dev/null
+++ b/zpu/hdl/zealot/GPL_V2
@@ -0,0 +1,341 @@
+		    GNU GENERAL PUBLIC LICENSE
+		       Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.
+               51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+			    Preamble
+
+  The licenses for most software are designed to take away your
+freedom to share and change it.  By contrast, the GNU General Public
+License is intended to guarantee your freedom to share and change free
+software--to make sure the software is free for all its users.  This
+General Public License applies to most of the Free Software
+Foundation's software and to any other program whose authors commit to
+using it.  (Some other Free Software Foundation software is covered by
+the GNU Library General Public License instead.)  You can apply it to
+your programs, too.
+
+  When we speak of free software, we are referring to freedom, not
+price.  Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
+this service if you wish), that you receive source code or can get it
+if you want it, that you can change the software or use pieces of it
+in new free programs; and that you know you can do these things.
+
+  To protect your rights, we need to make restrictions that forbid
+anyone to deny you these rights or to ask you to surrender the rights.
+These restrictions translate to certain responsibilities for you if you
+distribute copies of the software, or if you modify it.
+
+  For example, if you distribute copies of such a program, whether
+gratis or for a fee, you must give the recipients all the rights that
+you have.  You must make sure that they, too, receive or can get the
+source code.  And you must show them these terms so they know their
+rights.
+
+  We protect your rights with two steps: (1) copyright the software, and
+(2) offer you this license which gives you legal permission to copy,
+distribute and/or modify the software.
+
+  Also, for each author's protection and ours, we want to make certain
+that everyone understands that there is no warranty for this free
+software.  If the software is modified by someone else and passed on, we
+want its recipients to know that what they have is not the original, so
+that any problems introduced by others will not reflect on the original
+authors' reputations.
+
+  Finally, any free program is threatened constantly by software
+patents.  We wish to avoid the danger that redistributors of a free
+program will individually obtain patent licenses, in effect making the
+program proprietary.  To prevent this, we have made it clear that any
+patent must be licensed for everyone's free use or not licensed at all.
+
+  The precise terms and conditions for copying, distribution and
+modification follow.
+
+		    GNU GENERAL PUBLIC LICENSE
+   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
+
+  0. This License applies to any program or other work which contains
+a notice placed by the copyright holder saying it may be distributed
+under the terms of this General Public License.  The "Program", below,
+refers to any such program or work, and a "work based on the Program"
+means either the Program or any derivative work under copyright law:
+that is to say, a work containing the Program or a portion of it,
+either verbatim or with modifications and/or translated into another
+language.  (Hereinafter, translation is included without limitation in
+the term "modification".)  Each licensee is addressed as "you".
+
+Activities other than copying, distribution and modification are not
+covered by this License; they are outside its scope.  The act of
+running the Program is not restricted, and the output from the Program
+is covered only if its contents constitute a work based on the
+Program (independent of having been made by running the Program).
+Whether that is true depends on what the Program does.
+
+  1. You may copy and distribute verbatim copies of the Program's
+source code as you receive it, in any medium, provided that you
+conspicuously and appropriately publish on each copy an appropriate
+copyright notice and disclaimer of warranty; keep intact all the
+notices that refer to this License and to the absence of any warranty;
+and give any other recipients of the Program a copy of this License
+along with the Program.
+
+You may charge a fee for the physical act of transferring a copy, and
+you may at your option offer warranty protection in exchange for a fee.
+
+  2. You may modify your copy or copies of the Program or any portion
+of it, thus forming a work based on the Program, and copy and
+distribute such modifications or work under the terms of Section 1
+above, provided that you also meet all of these conditions:
+
+    a) You must cause the modified files to carry prominent notices
+    stating that you changed the files and the date of any change.
+
+    b) You must cause any work that you distribute or publish, that in
+    whole or in part contains or is derived from the Program or any
+    part thereof, to be licensed as a whole at no charge to all third
+    parties under the terms of this License.
+
+    c) If the modified program normally reads commands interactively
+    when run, you must cause it, when started running for such
+    interactive use in the most ordinary way, to print or display an
+    announcement including an appropriate copyright notice and a
+    notice that there is no warranty (or else, saying that you provide
+    a warranty) and that users may redistribute the program under
+    these conditions, and telling the user how to view a copy of this
+    License.  (Exception: if the Program itself is interactive but
+    does not normally print such an announcement, your work based on
+    the Program is not required to print an announcement.)
+
+These requirements apply to the modified work as a whole.  If
+identifiable sections of that work are not derived from the Program,
+and can be reasonably considered independent and separate works in
+themselves, then this License, and its terms, do not apply to those
+sections when you distribute them as separate works.  But when you
+distribute the same sections as part of a whole which is a work based
+on the Program, the distribution of the whole must be on the terms of
+this License, whose permissions for other licensees extend to the
+entire whole, and thus to each and every part regardless of who wrote it.
+
+Thus, it is not the intent of this section to claim rights or contest
+your rights to work written entirely by you; rather, the intent is to
+exercise the right to control the distribution of derivative or
+collective works based on the Program.
+
+In addition, mere aggregation of another work not based on the Program
+with the Program (or with a work based on the Program) on a volume of
+a storage or distribution medium does not bring the other work under
+the scope of this License.
+
+  3. You may copy and distribute the Program (or a work based on it,
+under Section 2) in object code or executable form under the terms of
+Sections 1 and 2 above provided that you also do one of the following:
+
+    a) Accompany it with the complete corresponding machine-readable
+    source code, which must be distributed under the terms of Sections
+    1 and 2 above on a medium customarily used for software interchange; or,
+
+    b) Accompany it with a written offer, valid for at least three
+    years, to give any third party, for a charge no more than your
+    cost of physically performing source distribution, a complete
+    machine-readable copy of the corresponding source code, to be
+    distributed under the terms of Sections 1 and 2 above on a medium
+    customarily used for software interchange; or,
+
+    c) Accompany it with the information you received as to the offer
+    to distribute corresponding source code.  (This alternative is
+    allowed only for noncommercial distribution and only if you
+    received the program in object code or executable form with such
+    an offer, in accord with Subsection b above.)
+
+The source code for a work means the preferred form of the work for
+making modifications to it.  For an executable work, complete source
+code means all the source code for all modules it contains, plus any
+associated interface definition files, plus the scripts used to
+control compilation and installation of the executable.  However, as a
+special exception, the source code distributed need not include
+anything that is normally distributed (in either source or binary
+form) with the major components (compiler, kernel, and so on) of the
+operating system on which the executable runs, unless that component
+itself accompanies the executable.
+
+If distribution of executable or object code is made by offering
+access to copy from a designated place, then offering equivalent
+access to copy the source code from the same place counts as
+distribution of the source code, even though third parties are not
+compelled to copy the source along with the object code.
+
+  4. You may not copy, modify, sublicense, or distribute the Program
+except as expressly provided under this License.  Any attempt
+otherwise to copy, modify, sublicense or distribute the Program is
+void, and will automatically terminate your rights under this License.
+However, parties who have received copies, or rights, from you under
+this License will not have their licenses terminated so long as such
+parties remain in full compliance.
+
+  5. You are not required to accept this License, since you have not
+signed it.  However, nothing else grants you permission to modify or
+distribute the Program or its derivative works.  These actions are
+prohibited by law if you do not accept this License.  Therefore, by
+modifying or distributing the Program (or any work based on the
+Program), you indicate your acceptance of this License to do so, and
+all its terms and conditions for copying, distributing or modifying
+the Program or works based on it.
+
+  6. Each time you redistribute the Program (or any work based on the
+Program), the recipient automatically receives a license from the
+original licensor to copy, distribute or modify the Program subject to
+these terms and conditions.  You may not impose any further
+restrictions on the recipients' exercise of the rights granted herein.
+You are not responsible for enforcing compliance by third parties to
+this License.
+
+  7. If, as a consequence of a court judgment or allegation of patent
+infringement or for any other reason (not limited to patent issues),
+conditions are imposed on you (whether by court order, agreement or
+otherwise) that contradict the conditions of this License, they do not
+excuse you from the conditions of this License.  If you cannot
+distribute so as to satisfy simultaneously your obligations under this
+License and any other pertinent obligations, then as a consequence you
+may not distribute the Program at all.  For example, if a patent
+license would not permit royalty-free redistribution of the Program by
+all those who receive copies directly or indirectly through you, then
+the only way you could satisfy both it and this License would be to
+refrain entirely from distribution of the Program.
+
+If any portion of this section is held invalid or unenforceable under
+any particular circumstance, the balance of the section is intended to
+apply and the section as a whole is intended to apply in other
+circumstances.
+
+It is not the purpose of this section to induce you to infringe any
+patents or other property right claims or to contest validity of any
+such claims; this section has the sole purpose of protecting the
+integrity of the free software distribution system, which is
+implemented by public license practices.  Many people have made
+generous contributions to the wide range of software distributed
+through that system in reliance on consistent application of that
+system; it is up to the author/donor to decide if he or she is willing
+to distribute software through any other system and a licensee cannot
+impose that choice.
+
+This section is intended to make thoroughly clear what is believed to
+be a consequence of the rest of this License.
+
+  8. If the distribution and/or use of the Program is restricted in
+certain countries either by patents or by copyrighted interfaces, the
+original copyright holder who places the Program under this License
+may add an explicit geographical distribution limitation excluding
+those countries, so that distribution is permitted only in or among
+countries not thus excluded.  In such case, this License incorporates
+the limitation as if written in the body of this License.
+
+  9. The Free Software Foundation may publish revised and/or new versions
+of the General Public License from time to time.  Such new versions will
+be similar in spirit to the present version, but may differ in detail to
+address new problems or concerns.
+
+Each version is given a distinguishing version number.  If the Program
+specifies a version number of this License which applies to it and "any
+later version", you have the option of following the terms and conditions
+either of that version or of any later version published by the Free
+Software Foundation.  If the Program does not specify a version number of
+this License, you may choose any version ever published by the Free Software
+Foundation.
+
+  10. If you wish to incorporate parts of the Program into other free
+programs whose distribution conditions are different, write to the author
+to ask for permission.  For software which is copyrighted by the Free
+Software Foundation, write to the Free Software Foundation; we sometimes
+make exceptions for this.  Our decision will be guided by the two goals
+of preserving the free status of all derivatives of our free software and
+of promoting the sharing and reuse of software generally.
+
+			    NO WARRANTY
+
+  11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
+FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW.  EXCEPT WHEN
+OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
+PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
+OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.  THE ENTIRE RISK AS
+TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU.  SHOULD THE
+PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
+REPAIR OR CORRECTION.
+
+  12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
+WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
+REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
+INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
+OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
+TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
+YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
+PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGES.
+
+		     END OF TERMS AND CONDITIONS
+
+
+	    How to Apply These Terms to Your New Programs
+
+  If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
+  To do so, attach the following notices to the program.  It is safest
+to attach them to the start of each source file to most effectively
+convey the exclusion of warranty; and each file should have at least
+the "copyright" line and a pointer to where the full notice is found.
+
+    <one line to give the program's name and a brief idea of what it does.>
+    Copyright (C) 19yy  <name of author>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+
+Also add information on how to contact you by electronic and paper mail.
+
+If the program is interactive, make it output a short notice like this
+when it starts in an interactive mode:
+
+    Gnomovision version 69, Copyright (C) 19yy name of author
+    Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+    This is free software, and you are welcome to redistribute it
+    under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License.  Of course, the commands you use may
+be called something other than `show w' and `show c'; they could even be
+mouse-clicks or menu items--whatever suits your program.
+
+You should also get your employer (if you work as a programmer) or your
+school, if any, to sign a "copyright disclaimer" for the program, if
+necessary.  Here is a sample; alter the names:
+
+  Yoyodyne, Inc., hereby disclaims all copyright interest in the program
+  `Gnomovision' (which makes passes at compilers) written by James Hacker.
+
+  <signature of Ty Coon>, 1 April 1989
+  Ty Coon, President of Vice
+
+This General Public License does not permit incorporating your program into
+proprietary programs.  If your program is a subroutine library, you may
+consider it more useful to permit linking proprietary applications with the
+library.  If this is what you want to do, use the GNU Library General
+Public License instead of this License.
diff --git a/zpu/hdl/zealot/devices/br_gen.vhdl b/zpu/hdl/zealot/devices/br_gen.vhdl
new file mode 100644
index 0000000..d14440e
--- /dev/null
+++ b/zpu/hdl/zealot/devices/br_gen.vhdl
@@ -0,0 +1,91 @@
+------------------------------------------------------------------------------
+----                                                                      ----
+----  RS-232 baudrate generator                                           ----
+----                                                                      ----
+----  http://www.opencores.org/                                           ----
+----                                                                      ----
+----  Description:                                                        ----
+----  This counter is a parametrizable clock divider. The count value is  ----
+----  the generic parameter COUNT. It has a chip enable ce_i input.       ----
+----  (will count only if CE is high).                                    ----
+----  When it overflows, will emit a pulse on o_o.                        ----
+----                                                                      ----
+----  To Do:                                                              ----
+----  -                                                                   ----
+----                                                                      ----
+----  Author:                                                             ----
+----    - Philippe Carton, philippe.carton2 libertysurf.fr                ----
+----    - Juan Pablo Daniel Borgna, jpdborgna gmail.com                   ----
+----    - Salvador E. Tropea, salvador inti.gob.ar                        ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Copyright (c) 2001-2003 Philippe Carton                              ----
+---- Copyright (c) 2005 Juan Pablo Daniel Borgna                          ----
+---- Copyright (c) 2005-2008 Salvador E. Tropea                           ----
+---- Copyright (c) 2005-2008 Instituto Nacional de Tecnología Industrial  ----
+----                                                                      ----
+---- Distributed under the GPL license                                    ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Design unit:      BRGen(Behaviour) (Entity and architecture)         ----
+---- File name:        br_gen.vhdl                                        ----
+---- Note:             None                                               ----
+---- Limitations:      None known                                         ----
+---- Errors:           None known                                         ----
+---- Library:          zpu                                                ----
+---- Dependencies:     IEEE.std_logic_1164                                ----
+---- Target FPGA:      Spartan                                            ----
+---- Language:         VHDL                                               ----
+---- Wishbone:         No                                                 ----
+---- Synthesis tools:  Xilinx Release 9.2.03i - xst J.39                  ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x)                       ----
+---- Text editor:      SETEdit 0.5.x                                      ----
+----                                                                      ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity BRGen is
+  generic(
+     COUNT : integer range 0 to 65535);-- Count revolution
+  port (
+     clk_i   : in  std_logic;  -- Clock
+     reset_i : in  std_logic;  -- Reset input
+     ce_i    : in  std_logic;  -- Chip Enable
+     o_o     : out std_logic); -- Output
+end entity BRGen;
+
+architecture Behaviour of BRGen is
+
+begin
+  CountGen:
+  if COUNT/=1 generate
+     Counter:
+     process (clk_i)
+        variable cnt : integer range 0 to COUNT-1;
+     begin
+        if rising_edge(clk_i) then
+           o_o <= '0';
+           if reset_i='1' then
+              cnt:=COUNT-1;
+           elsif ce_i='1' then
+              if cnt=0 then
+                 o_o <= '1';
+                 cnt:=COUNT-1;
+              else
+                 cnt:=cnt-1;
+              end if; -- cnt/=0
+           end if; -- ce_i='1'
+        end if; -- rising_edge(clk_i)
+     end process Counter;
+  end generate CountGen;
+
+  CountWire:
+  if COUNT=1 generate
+     o_o <= '0' when reset_i='1' else ce_i;
+  end generate CountWire;
+end architecture Behaviour; -- Entity: BRGen
+
diff --git a/zpu/hdl/zealot/devices/gpio.vhdl b/zpu/hdl/zealot/devices/gpio.vhdl
new file mode 100644
index 0000000..fc66bde
--- /dev/null
+++ b/zpu/hdl/zealot/devices/gpio.vhdl
@@ -0,0 +1,107 @@
+--
+-- this module desribes a simple GPIO interface
+--
+-- data on port_in is synhronized to clk_i and can be read at
+-- address 0
+--
+-- any write to address 0 is mapped to port_out
+--
+-- at address 1 is a direction register (port_dir)
+-- initialized with '1's, what mean direction = in
+-- this register is useful for bidirectional pins, e.g. headers
+--
+--
+-- some examples:
+--
+-- to connect 4 buttons:
+-- port_in( 3 downto  0) <= gpio_button;
+--
+--
+-- to connect 8 LEDs:
+-- gpio_led <= port_out(7 downto 0); 
+--
+--
+-- to connect 2 bidirectional header pins:
+-- port_in(8)  <= gpio_pin(0);
+-- gpio_pin(0) <= port_out(8) when port_dir(8) = '0' else 'Z';
+--
+-- port_in(9)  <= gpio_pin(1);
+-- gpio_pin(1) <= port_out(9) when port_dir(9) = '0' else 'Z';
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+entity gpio is
+    port(
+        clk_i    : in  std_logic;
+        reset_i  : in  std_logic;
+        --
+        we_i     : in  std_logic;
+        data_i   : in  unsigned(31 downto 0);
+        addr_i   : in  unsigned( 0 downto 0);
+        data_o   : out unsigned(31 downto 0);
+        --
+        port_in  : in  std_logic_vector(31 downto 0);
+        port_out : out std_logic_vector(31 downto 0);
+        port_dir : out std_logic_vector(31 downto 0)
+    );
+end entity gpio;
+
+
+architecture rtl of gpio is
+
+    signal port_in_reg  : std_logic_vector(31 downto 0);
+    signal port_in_sync : std_logic_vector(31 downto 0);
+    --
+    signal direction    : std_logic_vector(31 downto 0) := (others => '1');
+
+begin
+
+    process
+    begin
+        wait until rising_edge( clk_i);
+        
+        -- synchronize all inputs with two registers
+        -- to avoid metastability
+        port_in_reg  <= port_in;
+        port_in_sync <= port_in_reg;
+
+        -- write access to gpio
+        if we_i = '1' then
+            -- data
+            if addr_i = "0" then
+                port_out  <= std_logic_vector( data_i);
+            end if;
+            -- direction
+            if addr_i = "1" then
+                direction <= std_logic_vector( data_i);
+            end if;
+        end if;
+
+        -- read access to gpio
+        -- data
+        if addr_i = "0" then
+            data_o <= unsigned( port_in_sync);
+        end if;
+        -- direction
+        if addr_i = "1" then
+            data_o <= unsigned( direction);
+        end if;
+
+        -- outputs
+        port_dir <= direction;
+
+        -- sync reset
+        if reset_i = '1' then
+            direction    <= (others => '1');
+            port_in_reg  <= (others => '0');
+            port_in_sync <= (others => '0');
+        end if;
+
+    end process;
+
+
+end architecture rtl;
diff --git a/zpu/hdl/zealot/devices/phi_io.vhdl b/zpu/hdl/zealot/devices/phi_io.vhdl
new file mode 100644
index 0000000..6e40d1d
--- /dev/null
+++ b/zpu/hdl/zealot/devices/phi_io.vhdl
@@ -0,0 +1,257 @@
+------------------------------------------------------------------------------
+----                                                                      ----
+----  ZPU Phi I/O                                                         ----
+----                                                                      ----
+----  http://www.opencores.org/                                           ----
+----                                                                      ----
+----  Description:                                                        ----
+----  ZPU is a 32 bits small stack cpu. This is the minimum I/O devices   ----
+----  assumed by the libc. They are a timer and an UART.@p                ----
+----  Important! this is currently a simulation only model, no UART       ----
+----  provided and it unconditionally generates a log.                    ----
+----  Important! not all peripherals implemented!                         ----
+----  Important! The enable signals assumes this is mapped @ 0x80A00xx.   ----
+----                                                                      ----
+----  To Do:                                                              ----
+----  -                                                                   ----
+----                                                                      ----
+----  Author:                                                             ----
+----    - Øyvind Harboe, oyvind.harboe zylin.com                          ----
+----    - Salvador E. Tropea, salvador inti.gob.ar                        ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com>           ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar>         ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial       ----
+----                                                                      ----
+---- Distributed under the BSD license                                    ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Design unit:      ZPUPhiIO(Behave) (Entity and architecture)         ----
+---- File name:        phi_io.vhdl                                        ----
+---- Note:             None                                               ----
+---- Limitations:      Only for simulation.                               ----
+---- Errors:           None known                                         ----
+---- Library:          zpu                                                ----
+---- Dependencies:     IEEE.std_logic_1164                                ----
+----                   IEEE.numeric_std                                   ----
+----                   std.textio                                         ----
+----                   zpu.zpupkg                                         ----
+----                   zpu.txt_util                                       ----
+---- Target FPGA:      Spartan 3 (XC3S1500-4-FG456)                       ----
+---- Language:         VHDL                                               ----
+---- Wishbone:         No                                                 ----
+---- Synthesis tools:  N/A                                                ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x)                       ----
+---- Text editor:      SETEdit 0.5.x                                      ----
+----                                                                      ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use std.textio.all;
+
+library zpu;
+use zpu.zpupkg.timer;
+use zpu.zpupkg.gpio;
+use zpu.UART.all;
+use zpu.txt_util.all;
+ 
+entity ZPUPhiIO is
+   generic(
+      BRDIVISOR : positive:=1;   -- Baud rate divisor i.e. br_clk/9600/4
+      ENA_LOG   : boolean:=true; -- Enable log
+      LOG_FILE  : string:="log.txt"); -- Name for the log file
+   port(
+      clk_i      : in  std_logic; -- System Clock
+      reset_i    : in  std_logic; -- Synchronous Reset
+      busy_o     : out std_logic; -- I/O is busy
+      we_i       : in  std_logic; -- Write Enable
+      re_i       : in  std_logic; -- Read Enable
+      data_i     : in  unsigned(31 downto 0);
+      data_o     : out unsigned(31 downto 0);
+      addr_i     : in  unsigned(2  downto 0); -- Address bits 4-2
+      --
+      rs232_rx_i : in  std_logic;  -- UART Rx input
+      rs232_tx_o : out std_logic;  -- UART Tx output
+      br_clk_i   : in  std_logic;  -- UART base clock (enable)
+      --
+      gpio_in    : in  std_logic_vector(31 downto 0);
+      gpio_out   : out std_logic_vector(31 downto 0);
+      gpio_dir   : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
+      );
+end entity ZPUPhiIO;
+   
+   
+architecture Behave of ZPUPhiIO is
+   constant LOW_BITS  : unsigned(1 downto 0):=(others=>'0');
+   constant TX_FULL   : std_logic:='0';
+   constant RX_EMPTY  : std_logic:='1';
+
+   -- "000" 0x00 is CPU enable ... useful?
+   constant IO_DATA   : unsigned(2 downto 0):="001"; -- 0x04
+   constant IO_DIR    : unsigned(2 downto 0):="010"; -- 0x08
+   constant UART_TX   : unsigned(2 downto 0):="011"; -- 0x0C
+   constant UART_RX   : unsigned(2 downto 0):="100"; -- 0x10
+   constant CNT_1     : unsigned(2 downto 0):="101"; -- 0x14
+   constant CNT_2     : unsigned(2 downto 0):="110"; -- 0x18
+   -- "111" 0x1C Unused
+   -- Unimplemented: Interrupt control and timer (not counter ...?)
+
+   signal timer_read : unsigned(31 downto 0);
+   signal timer_we   : std_logic;
+   signal is_timer   : std_logic;
+
+   -- UART
+   -- Rx
+   signal rx_br      : std_logic; -- Rx timing
+   signal uart_read  : std_logic; -- ZPU read the value
+   signal rx_avail   : std_logic; -- Rx data available
+   signal rx_data    : std_logic_vector(7 downto 0); -- Rx data
+   -- Tx
+   signal tx_br      : std_logic; -- Tx timing
+   signal uart_write : std_logic; -- ZPU is writing
+   signal tx_busy    : std_logic; -- Tx can't get a new value
+
+   -- GPIO
+   signal gpio_we    : std_logic;
+   signal is_gpio    : std_logic;
+   signal gpio_read  : unsigned(31 downto 0);
+
+   file l_file       : text open write_mode is LOG_FILE;
+
+begin
+   -----------
+   -- Timer --
+   -----------
+   timerinst: Timer
+      port map(
+         clk_i => clk_i, reset_i => reset_i, we_i => timer_we,
+         data_i => data_i, addr_i => addr_i(1 downto 1),
+         data_o => timer_read);
+   
+   busy_o   <= we_i or re_i;
+   is_timer <= '1' when to_01(addr_i)=CNT_1 or to_01(addr_i)=CNT_2 else '0'; -- 0x80A0014/8
+   timer_we <= we_i and is_timer;
+
+   ----------
+   -- UART --
+   ----------
+   -- Rx section
+   rx_core : RxUnit
+      port map(
+         clk_i => clk_i, reset_i => reset_i, enable_i => rx_br,
+         read_i => uart_read, rxd_i => rs232_rx_i, rxav_o => rx_avail,
+         datao_o => rx_data);
+   uart_read <= '1' when re_i='1' and addr_i=UART_RX else '0';
+
+   -- Tx section
+   tx_core : TxUnit
+      port map(
+         clk_i => clk_i, reset_i => reset_i, enable_i => tx_br,
+         load_i => uart_write, txd_o => rs232_tx_o, busy_o => tx_busy,
+         datai_i => std_logic_vector(data_i(7 downto 0)));
+   uart_write <= '1' when we_i='1' and addr_i=UART_TX else '0';
+
+   -- Rx timing
+   rx_timer : BRGen
+      generic map(COUNT => BRDIVISOR)
+      port map(
+         clk_i => clk_i, reset_i => reset_i, ce_i => br_clk_i, o_o => rx_br);
+
+   -- Tx timing
+   tx_timer : BRGen -- 4 Divider for Tx
+      generic map(COUNT => 4)  
+      port map(
+         clk_i => clk_i, reset_i => reset_i, ce_i => rx_br, o_o => tx_br);
+   
+   ----------
+   -- GPIO --
+   ----------
+   gpio_i0: gpio
+      port map(
+          clk_i    => clk_i,              -- : in  std_logic;
+          reset_i  => reset_i,            -- : in  std_logic;
+          --                              
+          we_i     => gpio_we,            -- : in  std_logic;
+          data_i   => data_i,             -- : in  unsigned(31 downto 0);
+          addr_i   => addr_i(1 downto 1), -- : in  unsigned( 0 downto 0);
+          data_o   => gpio_read,          -- : out unsigned(31 downto 0);
+          --                              
+          port_in  => gpio_in,            -- : std_logic_vector(31 downto 0);
+          port_out => gpio_out,           -- : std_logic_vector(31 downto 0);
+          port_dir => gpio_dir            -- : std_logic_vector(31 downto 0);
+          );
+   is_gpio <= '1' when to_01(addr_i) = IO_DATA or to_01(addr_i) = IO_DIR else '0'; -- 0x80A0004/8
+   gpio_we <= we_i and is_gpio;
+
+
+   do_io:
+   process(clk_i)
+        --synopsys translate off
+        variable line_out : line := new string'("");
+        variable char     : character;
+        --synopsys translate on
+   begin
+      if rising_edge(clk_i) then
+         if reset_i/='1' then
+            --synopsys translate off
+            if we_i='1' then
+               if addr_i=UART_TX and ENA_LOG then -- 0x80a000c
+                  -- Write to UART
+                  print("- Write to UART Tx: 0x" &hstr(data_i)&" ("&
+                        character'val(to_integer(data_i) mod 256)&")");
+                    char := character'val(to_integer(data_i));
+                    if char = lf then
+                        std.textio.writeline(l_file, line_out);
+                    else
+                        std.textio.write(line_out, char);
+                    end if;
+               elsif is_gpio = '1' and ENA_LOG then
+                  print("- Write GPIO: 0x" & hstr(data_i));
+               elsif is_timer='1' and ENA_LOG then
+                  print("- Write to TIMER: 0x" & hstr(data_i));
+               else
+                  --print(l_file,character'val(to_integer(data_i)));
+                  report "Illegal IO data_i=0x"&hstr(data_i)&" @0x"&
+                     hstr(x"80a00"&"000"&addr_i&"00") severity warning;
+               end if;
+            end if;
+            --synopsys translate on
+            data_o <= (others => '0');
+            if re_i='1' then
+               if is_gpio = '1' then
+                  if ENA_LOG then
+                     print("- Read  GPIO: 0x" & hstr(gpio_read));
+                  end if;
+                  data_o <= gpio_read;
+               elsif addr_i=UART_TX then
+                  if ENA_LOG then
+                     print("- Read UART Tx");
+                  end if;
+                  data_o(8) <= not(tx_busy); -- output fifo not full
+               elsif addr_i=UART_RX then
+                  if ENA_LOG then
+                     print("- Read UART Rx");
+                  end if;
+                  data_o(8) <= rx_avail; -- receiver not empty
+                  data_o(7 downto 0) <= unsigned(rx_data);
+               elsif is_timer='1' then
+                  if ENA_LOG then
+                     print("- Read TIMER: 0x" & hstr(timer_read));
+                  end if;
+                  data_o <= timer_read;
+               else
+                  report "Illegal IO data_o @0x"&
+                     hstr(x"80a00"&"000"&addr_i&"00") severity warning;
+               end if;
+            end if; -- re_i='1'
+         end if; -- reset_i/='1'
+      end if; -- rising_edge(clk_i)
+   end process do_io;
+end Behave;
+ 
diff --git a/zpu/hdl/zealot/devices/rx_unit.vhdl b/zpu/hdl/zealot/devices/rx_unit.vhdl
new file mode 100644
index 0000000..e9b3251
--- /dev/null
+++ b/zpu/hdl/zealot/devices/rx_unit.vhdl
@@ -0,0 +1,108 @@
+------------------------------------------------------------------------------
+----                                                                      ----
+----  RS-232 simple Rx module                                             ----
+----                                                                      ----
+----  http://www.opencores.org/                                           ----
+----                                                                      ----
+----  Description:                                                        ----
+----  Implements a simple 8N1 rx module for RS-232.                       ----
+----                                                                      ----
+----  To Do:                                                              ----
+----  -                                                                   ----
+----                                                                      ----
+----  Author:                                                             ----
+----    - Philippe Carton, philippe.carton2 libertysurf.fr                ----
+----    - Juan Pablo Daniel Borgna, jpdborgna gmail.com                   ----
+----    - Salvador E. Tropea, salvador inti.gob.ar                        ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Copyright (c) 2001-2003 Philippe Carton                              ----
+---- Copyright (c) 2005 Juan Pablo Daniel Borgna                          ----
+---- Copyright (c) 2005-2008 Salvador E. Tropea                           ----
+---- Copyright (c) 2005-2008 Instituto Nacional de Tecnología Industrial  ----
+----                                                                      ----
+---- Distributed under the GPL license                                    ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Design unit:      RxUnit(Behaviour) (Entity and architecture)        ----
+---- File name:        rx_unit.vhdl                                       ----
+---- Note:             None                                               ----
+---- Limitations:      None known                                         ----
+---- Errors:           None known                                         ----
+---- Library:          zpu                                                ----
+---- Dependencies:     IEEE.std_logic_1164                                ----
+---- Target FPGA:      Spartan                                            ----
+---- Language:         VHDL                                               ----
+---- Wishbone:         No                                                 ----
+---- Synthesis tools:  Xilinx Release 9.2.03i - xst J.39                  ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x)                       ----
+---- Text editor:      SETEdit 0.5.x                                      ----
+----                                                                      ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+   
+entity RxUnit is
+   port(
+      clk_i    : in  std_logic;  -- System clock signal
+      reset_i  : in  std_logic;  -- Reset input (sync)
+      enable_i : in  std_logic;  -- Enable input (rate*4)
+      read_i   : in  std_logic;  -- Received Byte Read
+      rxd_i    : in  std_logic;  -- RS-232 data input
+      rxav_o   : out std_logic;  -- Byte available
+      datao_o  : out std_logic_vector(7 downto 0)); -- Byte received
+end entity RxUnit;
+
+architecture Behaviour of RxUnit is
+   signal r_r      : std_logic_vector(7 downto 0); -- Receive register
+   signal bavail_r : std_logic:='0';               -- Byte received
+begin
+   rxav_o <= bavail_r;
+   -- Rx Process
+   RxProc:
+   process (clk_i)
+      variable bitpos    : integer range 0 to 10; -- Position of the bit in the frame
+      variable samplecnt : integer range 0 to 3;  -- Count from 0 to 3 in each bit
+   begin
+      if rising_edge(clk_i) then
+         if reset_i='1' then
+            bavail_r <= '0';
+            bitpos:=0;
+         else -- reset_i='0'
+            if read_i='1' then
+               bavail_r <= '0';
+            end if;
+            if enable_i='1' then
+               case bitpos is
+                    when 0 => -- idle
+                         bavail_r <= '0';
+                         if rxd_i='0' then -- Start Bit
+                            samplecnt:=0;
+                            bitpos:=1;
+                         end if;
+                    when 10 => -- Stop Bit
+                         bitpos:=0;    -- next is idle
+                         bavail_r <= '1';    -- Indicate byte received
+                         datao_o  <= r_r; -- Store received byte
+                    when others =>
+                         if samplecnt=1 and bitpos>=2 then -- Sample RxD on 1
+                            r_r(bitpos-2) <= rxd_i; -- Deserialisation
+                         end if;
+                         if samplecnt=3 then -- Increment BitPos on 3
+                            bitpos:=bitpos+1;
+                         end if;
+               end case;
+               if samplecnt=3 then
+                  samplecnt:=0;
+               else
+                  samplecnt:=samplecnt+1;
+               end if;
+            end if; -- enable_i='1'
+         end if; -- reset_i='0'
+      end if; -- rising_edge(clk_i)
+   end process RxProc;
+end architecture Behaviour;
+
diff --git a/zpu/hdl/zealot/devices/timer.vhdl b/zpu/hdl/zealot/devices/timer.vhdl
new file mode 100644
index 0000000..389868c
--- /dev/null
+++ b/zpu/hdl/zealot/devices/timer.vhdl
@@ -0,0 +1,91 @@
+------------------------------------------------------------------------------
+----                                                                      ----
+----  64 bits clock counter                                               ----
+----                                                                      ----
+----  http://www.opencores.org/                                           ----
+----                                                                      ----
+----  Description:                                                        ----
+----  This is a peripheral used by the PHI I/O layout. It just counts the ----
+----  elapsed number of clocks.                                           ----
+----                                                                      ----
+----  To Do:                                                              ----
+----  -                                                                   ----
+----                                                                      ----
+----  Author:                                                             ----
+----    - Øyvind Harboe, oyvind.harboe zylin.com                          ----
+----    - Salvador E. Tropea, salvador inti.gob.ar                        ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com>           ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar>         ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial       ----
+----                                                                      ----
+---- Distributed under the BSD license                                    ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Design unit:      Timer(Behave) (Entity and architecture)            ----
+---- File name:        timer.vhdl                                         ----
+---- Note:             None                                               ----
+---- Limitations:      None known                                         ----
+---- Errors:           None known                                         ----
+---- Library:          zpu                                                ----
+---- Dependencies:     IEEE.std_logic_1164                                ----
+----                   IEEE.numeric_std                                   ----
+----                   zpu.zpupkg                                         ----
+---- Target FPGA:      Spartan 3 (XC3S1500-4-FG456)                       ----
+---- Language:         VHDL                                               ----
+---- Wishbone:         No                                                 ----
+---- Synthesis tools:  Xilinx Release 9.2.03i - xst J.39                  ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x)                       ----
+---- Text editor:      SETEdit 0.5.x                                      ----
+----                                                                      ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+ 
+entity Timer is
+   port(
+      clk_i    : in  std_logic;
+      reset_i  : in  std_logic;
+      we_i     : in  std_logic;
+      data_i   : in  unsigned(31 downto 0);
+      addr_i   : in  unsigned(0 downto 0);
+      data_o   : out unsigned(31 downto 0));
+end entity Timer;
+
+architecture Behave of Timer is
+   signal sample   : std_logic;
+   signal reset    : std_logic;
+   
+   signal cnt      : unsigned(63 downto 0);
+   signal cnt_smp  : unsigned(63 downto 0);
+begin
+   reset  <= '1' when (we_i='1' and data_i(0)='1') else '0';
+   sample <= '1' when (we_i='1' and data_i(1)='1') else '0';
+
+   -- Carry generation
+   do_timer:
+   process (clk_i)
+   begin
+      if rising_edge(clk_i) then
+         if reset_i='1' or reset='1' then
+            cnt <= (others => '0');
+            cnt_smp <= (others => '0');
+         else
+            cnt <= cnt+1;
+            if sample='1' then
+               -- report "sampling" severity failure;
+               cnt_smp <= cnt;
+            end if;
+         end if; -- else reset_i='1'
+      end if; -- rising_edge(clk_i)
+   end process do_timer;
+
+   data_o <= cnt_smp(31 downto  0) when to_01(addr_i)="0" else
+             cnt_smp(63 downto 32);
+end architecture Behave; -- Entity: Timer
+ 
diff --git a/zpu/hdl/zealot/devices/trace.vhdl b/zpu/hdl/zealot/devices/trace.vhdl
new file mode 100644
index 0000000..83d3782
--- /dev/null
+++ b/zpu/hdl/zealot/devices/trace.vhdl
@@ -0,0 +1,258 @@
+------------------------------------------------------------------------------
+----                                                                      ----
+----  ZPU Trace Module                                                    ----
+----                                                                      ----
+----  http://www.opencores.org/                                           ----
+----                                                                      ----
+----  Description:                                                        ----
+----  ZPU is a 32 bits small stack cpu. This is a module to log an        ----
+----  execution trace.                                                    ----
+----                                                                      ----
+----  To Do:                                                              ----
+----  -                                                                   ----
+----                                                                      ----
+----  Author:                                                             ----
+----    - Øyvind Harboe, oyvind.harboe zylin.com                          ----
+----    - Salvador E. Tropea, salvador inti.gob.ar                        ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com>           ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar>         ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial       ----
+----                                                                      ----
+---- Distributed under the BSD license                                    ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Design unit:      Trace(Behave) (Entity and architecture)            ----
+---- File name:        trace.vhdl                                         ----
+---- Note:             None                                               ----
+---- Limitations:      None known                                         ----
+---- Errors:           None known                                         ----
+---- Library:          zpu                                                ----
+---- Dependencies:     IEEE.std_logic_1164                                ----
+----                   IEEE.numeric_std                                   ----
+----                   std.textio                                         ----
+----                   zpu.zpupkg                                         ----
+----                   zpu.txt_util                                       ----
+---- Target FPGA:      N/A                                                ----
+---- Language:         VHDL                                               ----
+---- Wishbone:         No                                                 ----
+---- Synthesis tools:  N/A                                                ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x)                       ----
+---- Text editor:      SETEdit 0.5.x                                      ----
+----                                                                      ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use std.textio.all;
+
+library zpu;
+use zpu.zpupkg.all;
+use zpu.txt_util.all;
+
+entity Trace is
+   generic(
+      LOG_FILE   : string:="trace.txt"; -- Name of the trace file
+      ADDR_W     : integer:=16;  -- Address width
+      WORD_SIZE  : integer:=32); -- 16/32
+   port(
+      clk_i      : in std_logic;
+      dbg_i      : in zpu_dbgo_t;
+      stop_i     : in std_logic;
+      busy_i     : in std_logic
+      );
+end entity Trace;
+   
+architecture Behave of Trace is
+   file l_file : text open write_mode is LOG_FILE;
+   signal counter : unsigned(63 downto 0);
+begin
+   -- write data and control information to a file
+   receive_data:
+   process
+      variable l       : line;
+      variable stk_min : unsigned(31 downto 0):=(others => '1');
+      variable stk_ini : unsigned(31 downto 0);
+      variable first   : boolean:=true;
+      variable sp_off  : unsigned(4 downto 0);
+      variable idim    : boolean:=false;
+      variable im_val  : unsigned(31 downto 0):=(others => '0');
+   begin
+      counter <= to_unsigned(1,64);
+      -- print header for the logfile
+      print(l_file,"#PC      Opcode    SP       A=[SP]    B=[SP+1]  Clk Counter        Assembler");
+      print(l_file,"#---------------------------------------------------------------------------");
+      print(l_file," ");
+   
+      wait until clk_i='1';
+      wait until clk_i='0';
+   
+      while true loop
+         counter <= counter+1;
+         if dbg_i.b_inst='1' then
+            write(l, "0x"&hstr(dbg_i.pc(ADDR_W-1 downto 0))&
+                    " 0x"&hstr(dbg_i.opcode)&
+                    " 0x"&hstr(dbg_i.sp)&
+                    " 0x"&hstr(dbg_i.stk_a)&
+                    " 0x"&hstr(dbg_i.stk_b)&
+                    " 0x"&hstr(counter)&" ");
+            --------------------------
+            -- Instruction Decoder  --
+            --------------------------
+            sp_off(4):=not dbg_i.opcode(4);
+            sp_off(3 downto 0):=dbg_i.opcode(3 downto 0);
+            if dbg_i.opcode(7 downto 7)=OPCODE_IM then
+               if idim then
+                  im_val(31 downto 7):=im_val(24 downto 0);
+                  im_val(6 downto 0):=dbg_i.opcode(6 downto 0);
+               else
+                  im_val:=unsigned(resize(signed(dbg_i.opcode(6 downto 0)),32));
+               end if;
+               idim:=true;
+               write(l,"im 0x"&hstr(dbg_i.opcode(6 downto 0))&" ; 0x"&hstr(im_val));
+            elsif dbg_i.opcode(7 downto 5)=OPCODE_STORESP then
+               if sp_off=0 then
+                  write(l,string'("storesp 0 ; pop"));
+               elsif sp_off=1 then
+                  write(l,string'("storesp 4 ; 1*4 = popdown"));
+               else
+                  write(l,"storesp "&integer'image(to_integer(sp_off)*4)&" ; "&
+                        integer'image(to_integer(sp_off))&"*4");
+               end if;
+            elsif dbg_i.opcode(7 downto 5)=OPCODE_LOADSP then
+               if sp_off=0 then
+                  write(l,string'("loadsp 0 ; dup"));
+               elsif sp_off=1 then
+                  write(l,string'("loadsp 4 ; 1*4 = dupstkb"));
+               else
+                  write(l,"loadsp "&integer'image(to_integer(sp_off)*4)&" ; "&
+                        integer'image(to_integer(sp_off))&"*4");
+               end if;
+            elsif dbg_i.opcode(7 downto 5)=OPCODE_EMULATE then
+               if dbg_i.opcode(5 downto 0)=OPCODE_EQ then
+                  write(l,string'("eq"));
+               elsif dbg_i.opcode(5 downto 0)=OPCODE_LOADB then
+                  write(l,string'("loadb"));
+               elsif dbg_i.opcode(5 downto 0)=OPCODE_NEQBRANCH then
+                  write(l,string'("neqbranch"));
+               elsif dbg_i.opcode(5 downto 0)=OPCODE_PUSHSPADD then
+                  write(l,string'("pushspadd"));
+               elsif dbg_i.opcode(5 downto 0)=OPCODE_LESSTHAN then
+                  write(l,string'("lessthan"));
+               elsif dbg_i.opcode(5 downto 0)=OPCODE_ULESSTHAN then
+                  write(l,string'("ulessthan"));
+               elsif dbg_i.opcode(5 downto 0)=OPCODE_MULT then
+                  write(l,string'("mult"));
+               elsif dbg_i.opcode(5 downto 0)=OPCODE_STOREB then
+                  write(l,string'("storeb"));
+               elsif dbg_i.opcode(5 downto 0)=OPCODE_CALLPCREL then
+                  write(l,string'("callpcrel"));
+               elsif dbg_i.opcode(5 downto 0)=OPCODE_SUB then
+                  write(l,string'("sub"));
+               elsif dbg_i.opcode(5 downto 0)=OPCODE_LESSTHANOREQUAL then
+                  write(l,string'("lessthanorequal"));
+               elsif dbg_i.opcode(5 downto 0)=OPCODE_ULESSTHANOREQUAL then
+                  write(l,string'("ulessthanorequal"));
+               elsif dbg_i.opcode(5 downto 0)=OPCODE_CALL then
+                  write(l,string'("call"));
+               elsif dbg_i.opcode(5 downto 0)=OPCODE_POPPCREL then
+                  write(l,string'("poppcrel"));
+               elsif dbg_i.opcode(5 downto 0)=OPCODE_LSHIFTRIGHT then
+                  write(l,string'("lshiftright"));
+               elsif dbg_i.opcode(5 downto 0)=OPCODE_LOADH then
+                  write(l,string'("loadh"));
+               elsif dbg_i.opcode(5 downto 0)=OPCODE_STOREH then
+                  write(l,string'("storeh"));
+               elsif dbg_i.opcode(5 downto 0)=OPCODE_ASHIFTLEFT then
+                  write(l,string'("ashiftleft"));
+               elsif dbg_i.opcode(5 downto 0)=OPCODE_ASHIFTRIGHT then
+                  write(l,string'("ashiftright"));
+               elsif dbg_i.opcode(5 downto 0)=OPCODE_NEQ then
+                  write(l,string'("neq"));
+               elsif dbg_i.opcode(5 downto 0)=OPCODE_NEG then
+                  write(l,string'("neg"));
+               elsif dbg_i.opcode(5 downto 0)=OPCODE_XOR then
+                  write(l,string'("xor"));
+               elsif dbg_i.opcode(5 downto 0)=OPCODE_DIV then
+                  write(l,string'("div"));
+               elsif dbg_i.opcode(5 downto 0)=OPCODE_MOD then
+                  write(l,string'("mod"));
+               elsif dbg_i.opcode(5 downto 0)=OPCODE_EQBRANCH then
+                  write(l,string'("eqbranch"));
+               elsif dbg_i.opcode(5 downto 0)=OPCODE_CONFIG then
+                  write(l,string'("config"));
+               elsif dbg_i.opcode(5 downto 0)=OPCODE_PUSHPC then
+                  write(l,string'("pushpc"));
+               else
+                  write(l,integer'image(to_integer(dbg_i.opcode(5 downto 0)))&
+                        " ; invalid emulated instruction");
+               end if;
+            elsif dbg_i.opcode(7 downto 4)=OPCODE_ADDSP then
+               if sp_off=0 then
+                  write(l,string'("addsp 0 ; shift"));
+               elsif sp_off=1 then
+                  write(l,string'("addsp 4 ; 1*4 = addtop"));
+               else
+                  write(l,"addsp "&integer'image(to_integer(sp_off)*4)&" ; "&
+                        integer'image(to_integer(sp_off))&"*4");
+               end if;
+            else -- OPCODE_SHORT
+               case dbg_i.opcode(3 downto 0) is
+                    when OPCODE_BREAK =>
+                         write(l,string'("break"));
+                    when OPCODE_PUSHSP =>
+                         write(l,string'("pushsp"));
+                    when OPCODE_POPPC =>
+                         write(l,string'("poppc"));
+                    when OPCODE_ADD =>
+                         write(l,string'("add"));
+                    when OPCODE_OR =>
+                         write(l,string'("or"));
+                    when OPCODE_AND =>
+                         write(l,string'("and"));
+                    when OPCODE_LOAD =>
+                         write(l,string'("load"));
+                    when OPCODE_NOT =>
+                         write(l,string'("not"));
+                    when OPCODE_FLIP =>
+                         write(l,string'("flip"));
+                    when OPCODE_STORE =>
+                         write(l,string'("store"));
+                    when OPCODE_POPSP =>
+                         write(l,string'("popsp"));
+                    when OPCODE_NOP =>
+                         write(l,string'("nop"));
+                    when others =>
+                         write(l,integer'image(to_integer(dbg_i.opcode))&
+                               " ; invalid instruction");
+               end case;
+            end if;
+            if dbg_i.opcode(7 downto 7)/=OPCODE_IM then
+               idim:=false;
+            end if;
+            -----------------------------
+            -- End Instruction Decoder --
+            -----------------------------
+            writeline(l_file,l);
+            if dbg_i.sp<stk_min then
+               stk_min:=dbg_i.sp;
+            end if;
+            if first then
+               stk_ini:=dbg_i.sp+8;
+               first:=false;
+            end if;
+         end if;
+         wait until clk_i='0' or stop_i='1';
+         if stop_i='1' then
+            print(output,"Minimum SP: 0x"&hstr(stk_min)&" Size: 0x"&hstr(stk_ini-stk_min));
+            wait;
+         end if;
+      end loop;
+   end process receive_data;
+end Behave;
+ 
diff --git a/zpu/hdl/zealot/devices/tx_unit.vhdl b/zpu/hdl/zealot/devices/tx_unit.vhdl
new file mode 100644
index 0000000..73293f6
--- /dev/null
+++ b/zpu/hdl/zealot/devices/tx_unit.vhdl
@@ -0,0 +1,109 @@
+------------------------------------------------------------------------------
+----                                                                      ----
+----  RS-232 simple Tx module                                             ----
+----                                                                      ----
+----  http://www.opencores.org/                                           ----
+----                                                                      ----
+----  Description:                                                        ----
+----  Implements a simple 8N1 tx module for RS-232.                       ----
+----                                                                      ----
+----  To Do:                                                              ----
+----  -                                                                   ----
+----                                                                      ----
+----  Author:                                                             ----
+----    - Philippe Carton, philippe.carton2 libertysurf.fr                ----
+----    - Juan Pablo Daniel Borgna, jpdborgna gmail.com                   ----
+----    - Salvador E. Tropea, salvador inti.gob.ar                        ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Copyright (c) 2001-2003 Philippe Carton                              ----
+---- Copyright (c) 2005 Juan Pablo Daniel Borgna                          ----
+---- Copyright (c) 2005-2008 Salvador E. Tropea                           ----
+---- Copyright (c) 2005-2008 Instituto Nacional de Tecnología Industrial  ----
+----                                                                      ----
+---- Distributed under the GPL license                                    ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Design unit:      TxUnit(Behaviour) (Entity and architecture)        ----
+---- File name:        Txunit.vhdl                                        ----
+---- Note:             None                                               ----
+---- Limitations:      None known                                         ----
+---- Errors:           None known                                         ----
+---- Library:          zpu                                                ----
+---- Dependencies:     IEEE.std_logic_1164                                ----
+----                   zpu.UART                                           ----
+---- Target FPGA:      Spartan                                            ----
+---- Language:         VHDL                                               ----
+---- Wishbone:         No                                                 ----
+---- Synthesis tools:  Xilinx Release 9.2.03i - xst J.39                  ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x)                       ----
+---- Text editor:      SETEdit 0.5.x                                      ----
+----                                                                      ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library zpu;
+use zpu.UART.all;
+
+entity TxUnit is
+  port (
+     clk_i    : in  std_logic;  -- Clock signal
+     reset_i  : in  std_logic;  -- Reset input
+     enable_i : in  std_logic;  -- Enable input
+     load_i   : in  std_logic;  -- Load input
+     txd_o    : out std_logic;  -- RS-232 data output
+     busy_o   : out std_logic;  -- Tx Busy
+     datai_i  : in  std_logic_vector(7 downto 0)); -- Byte to transmit
+end entity TxUnit;
+
+architecture Behaviour of TxUnit is
+   signal tbuff_r  : std_logic_vector(7 downto 0); -- transmit buffer
+   signal t_r      : std_logic_vector(7 downto 0); -- transmit register
+   signal loaded_r : std_logic:='0';  -- Buffer loaded
+   signal txd_r    : std_logic:='1';  -- Tx buffer ready
+begin
+  busy_o <= load_i or loaded_r;
+  txd_o  <= txd_r;
+
+  -- Tx process
+  TxProc:
+  process (clk_i)
+     variable bitpos : integer range 0 to 10; -- Bit position in the frame
+  begin
+     if rising_edge(clk_i) then
+        if reset_i='1' then
+           loaded_r <= '0';
+           bitpos:=0;
+           txd_r <= '1';
+        else -- reset_i='0'
+           if load_i='1' then
+              tbuff_r  <= datai_i;
+              loaded_r <= '1';
+           end if;
+           if enable_i='1' then
+              case bitpos is
+                   when 0 => -- idle or stop bit
+                        txd_r <= '1';
+                        if loaded_r='1' then -- start transmit. next is start bit
+                           t_r <= tbuff_r;
+                           loaded_r <= '0';
+                           bitpos:=1;
+                        end if;
+                   when 1 => -- Start bit
+                        txd_r <= '0';
+                        bitpos:=2;
+                   when others =>
+                        txd_r <= t_r(bitpos-2); -- Serialisation of t_r
+                        bitpos:=bitpos+1;
+              end case;
+              if bitpos=10 then -- bit8. next is stop bit
+                 bitpos:=0;
+              end if;
+           end if; -- enable_i='1'
+        end if; -- reset_i='0'
+     end if; -- rising_edge(clk_i)
+  end process TxProc;
+end architecture Behaviour;
diff --git a/zpu/hdl/zealot/devices/txt_util.vhdl b/zpu/hdl/zealot/devices/txt_util.vhdl
new file mode 100644
index 0000000..862611c
--- /dev/null
+++ b/zpu/hdl/zealot/devices/txt_util.vhdl
@@ -0,0 +1,541 @@
+------------------------------------------------------------------------------
+----                                                                      ----
+----  Text Utils                                                          ----
+----                                                                      ----
+----  http://www.opencores.org/                                           ----
+----                                                                      ----
+----  Description:                                                        ----
+----  Utils to handle text. Used for the testbenches.                     ----
+----                                                                      ----
+----  To Do:                                                              ----
+----  -                                                                   ----
+----                                                                      ----
+----  Author:                                                             ----
+----    - Øyvind Harboe, oyvind.harboe zylin.com                          ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com>           ----
+----                                                                      ----
+---- Distributed under the BSD license                                    ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Design unit:      txt_util (Package)                                 ----
+---- File name:        txt_util.vhdl                                      ----
+---- Note:             None                                               ----
+---- Limitations:      None known                                         ----
+---- Errors:           None known                                         ----
+---- Library:          zpu                                                ----
+---- Dependencies:     IEEE.std_logic_1164                                ----
+----                   IEEE.numeric_std                                   ----
+----                   std.textio                                         ----
+---- Target FPGA:      N/A                                                ----
+---- Language:         VHDL                                               ----
+---- Wishbone:         No                                                 ----
+---- Synthesis tools:  Xilinx Release 9.2.03i - xst J.39                  ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x)                       ----
+---- Text editor:      SETEdit 0.5.x                                      ----
+----                                                                      ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use std.textio.all;
+
+library zpu;
+
+package txt_util is
+   -- prints a message to the screen
+   procedure print(text: string);
+
+   -- prints the message when active
+   -- useful for debug switches
+   procedure print(active: boolean; text: string);
+
+   -- converts std_logic into a character
+   function chr(sl: std_logic) return character;
+
+   -- converts std_logic into a string (1 to 1)
+   function str(sl: std_logic) return string;
+
+   -- converts std_logic_vector into a string (binary base)
+   function str(slv: std_logic_vector) return string;
+
+   -- converts boolean into a string
+   function str(b: boolean) return string;
+
+   -- converts an integer into a single character
+   -- (can also be used for hex conversion and other bases)
+   function chr(int: integer) return character;
+
+   -- converts integer into string using specified base
+   function str(int: integer; base: integer) return string;
+
+   -- converts integer to string, using base 10
+   function str(int: integer) return string;
+
+   -- convert std_logic_vector into a string in hex format
+   function hstr(slv: std_logic_vector) return string;
+   function hstr(slv: unsigned) return string;
+
+
+   -- functions to manipulate strings
+   -----------------------------------
+
+   -- convert a character to upper case
+   function to_upper(c: character) return character;
+
+   -- convert a character to lower case
+   function to_lower(c: character) return character;
+
+   -- convert a string to upper case
+   function to_upper(s: string) return string;
+
+   -- convert a string to lower case
+   function to_lower(s: string) return string;
+
+  
+   
+   -- functions to convert strings into other formats
+   --------------------------------------------------
+   
+   -- converts a character into std_logic
+   function to_std_logic(c: character) return std_logic; 
+   
+   -- converts a string into std_logic_vector
+   function to_std_logic_vector(s: string) return std_logic_vector; 
+
+
+ 
+   -- file I/O
+   -----------
+      
+   -- read variable length string from input file
+   procedure str_read(file in_file: TEXT; 
+                      res_string: out string);
+
+   procedure str_write(file out_file: TEXT; 
+                       new_string: in  string);
+       
+   -- print string to a file and start new line
+   procedure print(file out_file: TEXT;
+                   new_string: in  string);
+   
+   -- print character to a file and start new line
+   procedure print(file out_file: TEXT;
+                   char:       in  character);                   
+end package txt_util;
+
+
+
+
+package body txt_util is
+   -- prints text to the screen
+   procedure print(text: string) is
+      variable msg_line: line;
+   begin
+      --synopsys translate off
+      write(msg_line, text);
+      writeline(output, msg_line);
+      --synopsys translate on
+   end procedure print;
+
+   -- prints text to the screen when active
+   procedure print(active: boolean; text: string)  is
+   begin
+      if active then
+         print(text);
+      end if;
+   end procedure print;
+
+   -- converts std_logic into a character
+   function chr(sl: std_logic) return character is
+      variable c: character;
+   begin
+      case sl is
+           when 'U' => c:= 'U';
+           when 'X' => c:= 'X';
+           when '0' => c:= '0';
+           when '1' => c:= '1';
+           when 'Z' => c:= 'Z';
+           when 'W' => c:= 'W';
+           when 'L' => c:= 'L';
+           when 'H' => c:= 'H';
+           when '-' => c:= '-';
+      end case;
+      return c;
+   end function chr;
+
+   -- converts std_logic into a string (1 to 1)
+   function str(sl: std_logic) return string is
+      variable s: string(1 to 1);
+   begin
+      s(1):=chr(sl);
+      return s;
+   end function str;
+
+   -- converts std_logic_vector into a string (binary base)
+   -- (this also takes care of the fact that the range of
+   --  a string is natural while a std_logic_vector may
+   --  have an integer range)
+   function str(slv: std_logic_vector) return string is
+      variable result : string (1 to slv'length);
+      variable r      : integer;
+   begin
+      r:=1;
+      for i in slv'range loop
+          result(r) := chr(slv(i));
+          r:=r+1;
+      end loop;
+      return result;
+   end function str;
+
+
+   function str(b: boolean) return string is
+   begin
+      if b then
+         return "true";
+      else
+         return "false";
+      end if;
+   end function str;
+
+   -- converts an integer into a character
+   -- for 0 to 9 the obvious mapping is used, higher
+   -- values are mapped to the characters A-Z
+   -- (this is usefull for systems with base > 10)
+   -- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
+   function chr(int: integer) return character is
+      variable c: character;
+   begin
+      case int is
+           when  0 => c := '0';
+           when  1 => c := '1';
+           when  2 => c := '2';
+           when  3 => c := '3';
+           when  4 => c := '4';
+           when  5 => c := '5';
+           when  6 => c := '6';
+           when  7 => c := '7';
+           when  8 => c := '8';
+           when  9 => c := '9';
+           when 10 => c := 'A';
+           when 11 => c := 'B';
+           when 12 => c := 'C';
+           when 13 => c := 'D';
+           when 14 => c := 'E';
+           when 15 => c := 'F';
+           when 16 => c := 'G';
+           when 17 => c := 'H';
+           when 18 => c := 'I';
+           when 19 => c := 'J';
+           when 20 => c := 'K';
+           when 21 => c := 'L';
+           when 22 => c := 'M';
+           when 23 => c := 'N';
+           when 24 => c := 'O';
+           when 25 => c := 'P';
+           when 26 => c := 'Q';
+           when 27 => c := 'R';
+           when 28 => c := 'S';
+           when 29 => c := 'T';
+           when 30 => c := 'U';
+           when 31 => c := 'V';
+           when 32 => c := 'W';
+           when 33 => c := 'X';
+           when 34 => c := 'Y';
+           when 35 => c := 'Z';
+           when others => c := '?';
+      end case;
+      return c;
+   end function chr;
+
+   -- convert integer to string using specified base
+   -- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
+   function str(int: integer; base: integer) return string is
+      variable temp    : string(1 to 10);
+      variable num     : integer;
+      variable abs_int : integer;
+      variable len     : integer:=1;
+      variable power   : integer:=1;
+   begin
+      -- bug fix for negative numbers
+      abs_int:=abs(int);
+  
+      num    :=abs_int;
+  
+      while num>=base loop                       -- Determine how many
+         len:=len+1;                             -- characters required
+         num:=num/base;                          -- to represent the
+      end loop;                                  -- number.
+  
+      for i in len downto 1 loop                 -- Convert the number to
+          temp(i):=chr(abs_int/power mod base);  -- a string starting
+          power:=power*base;                     -- with the right hand
+      end loop ;                                 -- side.
+  
+      -- return result and add sign if required
+      if int<0 then
+         return '-'& temp(1 to len);
+      else
+         return temp(1 to len);
+      end if;
+   end function str;
+
+   -- convert integer to string, using base 10
+   function str(int: integer) return string is
+   begin
+      return str(int, 10) ;
+   end function str;
+
+   -- converts a std_logic_vector into a hex string.
+   function hstr(slv: std_logic_vector) return string is
+      variable hexlen: integer;
+      variable longslv : std_logic_vector(67 downto 0):=(others => '0');
+      variable hex : string(1 to 16);
+      variable fourbit : std_logic_vector(3 downto 0);
+   begin
+      hexlen:=(slv'left+1)/4;
+      if (slv'left+1) mod 4/=0 then
+         hexlen := hexlen + 1;
+      end if;
+      longslv(slv'left downto 0) := slv;
+      for i in (hexlen-1) downto 0 loop
+          fourbit:=longslv(((i*4)+3) downto (i*4));
+          case fourbit is
+               when "0000" => hex(hexlen-I):='0';
+               when "0001" => hex(hexlen-I):='1';
+               when "0010" => hex(hexlen-I):='2';
+               when "0011" => hex(hexlen-I):='3';
+               when "0100" => hex(hexlen-I):='4';
+               when "0101" => hex(hexlen-I):='5';
+               when "0110" => hex(hexlen-I):='6';
+               when "0111" => hex(hexlen-I):='7';
+               when "1000" => hex(hexlen-I):='8';
+               when "1001" => hex(hexlen-I):='9';
+               when "1010" => hex(hexlen-I):='A';
+               when "1011" => hex(hexlen-I):='B';
+               when "1100" => hex(hexlen-I):='C';
+               when "1101" => hex(hexlen-I):='D';
+               when "1110" => hex(hexlen-I):='E';
+               when "1111" => hex(hexlen-I):='F';
+               when "ZZZZ" => hex(hexlen-I):='z';
+               when "UUUU" => hex(hexlen-I):='u';
+               when "XXXX" => hex(hexlen-I):='x';
+               when others => hex(hexlen-I):='?';
+          end case;
+      end loop;
+      return hex(1 to hexlen);
+   end function hstr;
+
+   function hstr(slv: unsigned) return string is
+   begin
+      return hstr(std_logic_vector(slv));
+   end function hstr;
+
+   -- functions to manipulate strings
+   -----------------------------------
+
+
+   -- convert a character to upper case
+   function to_upper(c: character) return character is
+      variable u: character;
+   begin
+      case c is
+           when 'a' => u:='A';
+           when 'b' => u:='B';
+           when 'c' => u:='C';
+           when 'd' => u:='D';
+           when 'e' => u:='E';
+           when 'f' => u:='F';
+           when 'g' => u:='G';
+           when 'h' => u:='H';
+           when 'i' => u:='I';
+           when 'j' => u:='J';
+           when 'k' => u:='K';
+           when 'l' => u:='L';
+           when 'm' => u:='M';
+           when 'n' => u:='N';
+           when 'o' => u:='O';
+           when 'p' => u:='P';
+           when 'q' => u:='Q';
+           when 'r' => u:='R';
+           when 's' => u:='S';
+           when 't' => u:='T';
+           when 'u' => u:='U';
+           when 'v' => u:='V';
+           when 'w' => u:='W';
+           when 'x' => u:='X';
+           when 'y' => u:='Y';
+           when 'z' => u:='Z';
+           when others => u:=c;
+      end case;
+      return u;
+   end function to_upper;
+
+
+   -- convert a character to lower case
+   function to_lower(c: character) return character is
+      variable l: character;
+   begin
+      case c is
+           when 'A' => l:='a';
+           when 'B' => l:='b';
+           when 'C' => l:='c';
+           when 'D' => l:='d';
+           when 'E' => l:='e';
+           when 'F' => l:='f';
+           when 'G' => l:='g';
+           when 'H' => l:='h';
+           when 'I' => l:='i';
+           when 'J' => l:='j';
+           when 'K' => l:='k';
+           when 'L' => l:='l';
+           when 'M' => l:='m';
+           when 'N' => l:='n';
+           when 'O' => l:='o';
+           when 'P' => l:='p';
+           when 'Q' => l:='q';
+           when 'R' => l:='r';
+           when 'S' => l:='s';
+           when 'T' => l:='t';
+           when 'U' => l:='u';
+           when 'V' => l:='v';
+           when 'W' => l:='w';
+           when 'X' => l:='x';
+           when 'Y' => l:='y';
+           when 'Z' => l:='z';
+           when others => l:=c;
+      end case;
+      return l;
+   end function to_lower;
+
+   -- convert a string to upper case
+   function to_upper(s: string) return string is
+      variable uppercase: string (s'range);
+   begin
+      for i in s'range loop
+          uppercase(i):=to_upper(s(i));
+      end loop;
+      return uppercase;
+   end to_upper;
+
+   -- convert a string to lower case
+   function to_lower(s: string) return string is
+      variable lowercase: string (s'range);
+   begin
+      for i in s'range loop
+          lowercase(i):=to_lower(s(i));
+      end loop;
+      return lowercase;
+   end to_lower;
+
+   -- functions to convert strings into other types
+   
+   -- converts a character into a std_logic
+   
+   function to_std_logic(c: character) return std_logic is
+      variable sl : std_logic;
+   begin
+      case c is
+           when 'U' =>
+                sl:='U';
+           when 'X' =>
+                sl:='X';
+           when '0' => 
+                sl:='0';
+           when '1' => 
+                sl:='1';
+           when 'Z' => 
+                sl:='Z';
+           when 'W' => 
+                sl:='W';
+           when 'L' => 
+                sl:='L';
+           when 'H' => 
+                sl:='H';
+           when '-' => 
+                sl:='-';
+           when others =>
+                sl:='X';
+      end case;
+      return sl;
+   end function to_std_logic;
+   
+   
+   -- converts a string into std_logic_vector
+   function to_std_logic_vector(s: string) return std_logic_vector is 
+      variable slv : std_logic_vector(s'high-s'low downto 0);
+      variable k   : integer;
+   begin
+      k:=s'high-s'low;
+      for i in s'range loop
+          slv(k):=to_std_logic(s(i));
+          k     :=k-1;
+      end loop;
+      return slv;
+   end function to_std_logic_vector;
+                                       
+                                       
+   ----------------
+   --  file I/O  --
+   ----------------
+   
+   -- read variable length string from input file
+   procedure str_read(file in_file: TEXT; 
+                      res_string: out string) is
+      variable l         : line;
+      variable c         : character;
+      variable is_string : boolean;
+   begin
+      readline(in_file, l);
+      -- clear the contents of the result string
+      for i in res_string'range loop
+          res_string(i):=' ';
+      end loop;   
+      -- read all characters of the line, up to the length  
+      -- of the results string
+      for i in res_string'range loop
+          read(l,c,is_string);
+          res_string(i):=c;
+          if not is_string then -- found end of line
+             exit;
+          end if;
+      end loop; 
+   end procedure str_read;
+   
+   -- print string to a file
+   procedure print(file out_file: TEXT;
+                   new_string: in  string) is
+      variable l: line;
+   begin
+      write(l,new_string);
+      writeline(out_file,l);
+   end procedure print;
+   
+   -- print character to a file and start new line
+   procedure print(file out_file: TEXT;
+                   char: in  character) is
+      variable l: line;
+   begin
+      write(l,char);
+      writeline(out_file,l);
+   end procedure print;
+   
+   -- appends contents of a string to a file until line feed occurs
+   -- (LF is considered to be the end of the string)
+   procedure str_write(file out_file: TEXT; 
+                       new_string: in  string) is
+   begin
+      for i in new_string'range loop
+          print(out_file,new_string(i));
+          if new_string(i)=LF then -- end of string
+             exit;
+          end if;
+      end loop;               
+   end str_write;
+end package body txt_util;
+
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/clean_up.sh b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/clean_up.sh
new file mode 100755
index 0000000..3855f16
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/clean_up.sh
@@ -0,0 +1,16 @@
+#!/bin/sh
+
+# ise build stuff
+rm -rf build
+rm -f top.bit
+
+# modelsim compile stuff
+rm -rf work
+rm -rf zpu
+
+# modelsim simulation stuff
+rm -f vsim.wlf
+rm -f transcript
+rm -f zpu_trace.log
+rm -f zpu_med1_io.log
+rm -f zpu_small1_io.log
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation.sh b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation.sh
new file mode 100755
index 0000000..d525737
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation.sh
@@ -0,0 +1,49 @@
+#!/bin/sh
+
+# need project files:
+#    run.do
+#    wave.do
+
+# need ModelSim tools:
+#    vlib
+#    vcom
+#    vsim
+
+
+echo "###############"
+echo "compile zpu lib"
+echo "###############"
+vlib zpu
+vcom -work zpu ../../roms/hello_dbram.vhdl
+vcom -work zpu ../../roms/hello_bram.vhdl
+#vcom -work zpu ../../roms/dmips_dbram.vhdl
+#vcom -work zpu ../../roms/dmips_bram.vhdl
+
+vcom -work zpu ../../roms/rom_pkg.vhdl
+vcom -work zpu ../../zpu_pkg.vhdl
+vcom -work zpu ../../zpu_small.vhdl
+vcom -work zpu ../../zpu_medium.vhdl
+vcom -work zpu ../../helpers/zpu_small1.vhdl
+vcom -work zpu ../../helpers/zpu_med1.vhdl
+vcom -work zpu ../../devices/txt_util.vhdl
+vcom -work zpu ../../devices/phi_io.vhdl
+vcom -work zpu ../../devices/timer.vhdl
+vcom -work zpu ../../devices/gpio.vhdl
+vcom -work zpu ../../devices/rx_unit.vhdl
+vcom -work zpu ../../devices/tx_unit.vhdl
+vcom -work zpu ../../devices/br_gen.vhdl
+vcom -work zpu ../../devices/trace.vhdl
+
+
+echo "################"
+echo "compile work lib"
+echo "################"
+vlib work
+vcom top.vhd
+vcom top_tb.vhd
+
+
+echo "###################"
+echo "start simulator gui"
+echo "###################"
+vsim -gui top_tb -do simulation_config/run.do
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/run.do b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/run.do
new file mode 100644
index 0000000..acc1710
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/run.do
@@ -0,0 +1,2 @@
+do wave.do
+run -all
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/wave.do b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/wave.do
new file mode 100644
index 0000000..3f5d4fe
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/wave.do
@@ -0,0 +1,30 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /top_tb/tb_reset_n
+add wave -noupdate /top_tb/tb_clk
+add wave -noupdate -divider <NULL>
+add wave -noupdate /top_tb/tb_rs232_rx
+add wave -noupdate /top_tb/tb_rs232_tx
+add wave -noupdate /top_tb/tb_rs232_rts
+add wave -noupdate /top_tb/tb_rs232_cts
+add wave -noupdate -divider Buttons
+add wave -noupdate /top_tb/tb_button_n
+add wave -noupdate -divider LEDs
+add wave -noupdate /top_tb/tb_led
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {0 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 2
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {1294218073 ps} {1421130628 ps}
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis.sh b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis.sh
new file mode 100755
index 0000000..a7180fc
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis.sh
@@ -0,0 +1,36 @@
+#!/bin/sh
+
+# need project files:
+#    top.xst
+#    top.prj
+#    top.ut
+
+# need Xilinx tools:
+#    xst
+#    ngdbuild
+#    map
+#    par
+#    trce
+#    bitgen
+
+echo "########################"
+echo "generate build directory"
+echo "########################"
+mkdir build
+cd build 
+mkdir tmp
+
+echo "###############"
+echo "start processes"
+echo "###############"
+xst      -ifn "../synthesis_config/top.xst" -ofn "top.syr" 
+ngdbuild -dd _ngo -nt timestamp -uc ../synthesis_config/altium-livedesign-xc3s1000.ucf -p xc3s1000-fg456-4 top.ngc top.ngd  
+map      -p xc3s1000-fg456-4 -cm area -ir off -pr off -c 100 -o top_map.ncd top.ngd top.pcf 
+par      -w -ol high -t 1 top_map.ncd top.ncd top.pcf 
+trce     -v 3 -s 4 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf 
+bitgen   -f ../synthesis_config/top.ut top.ncd 
+
+echo "###########"
+echo "get bitfile"
+echo "###########"
+cp top.bit ..
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/altium-livedesign-xc3s1000.ucf b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/altium-livedesign-xc3s1000.ucf
new file mode 100644
index 0000000..ba22ee9
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/altium-livedesign-xc3s1000.ucf
@@ -0,0 +1,397 @@
+############################################################
+# Altium Livedesign Evaluation Board constraints file
+#
+# Familiy: Spartan-3 
+# Device:  XC3S1000
+# Package: FG456C
+# Speed:   -4
+#
+# all banks are powered with 3.3V
+#
+# config pins (M2, M1, M0): 101
+
+############################################################
+## clock/timing constraints
+############################################################
+
+NET "clk_50" period = 50 MHz ;
+
+
+############################################################
+## pin placement constraints
+############################################################
+
+NET "clk_50"         LOC = AA12 | IOSTANDARD = LVCMOS33;
+NET "reset_n"        LOC = Y17  | IOSTANDARD = LVCMOS33; # low active
+
+# Soft JTAG
+NET "soft_tdo"       LOC = D22  | IOSTANDARD = LVCMOS33;
+NET "soft_tms"       LOC = E21  | IOSTANDARD = LVCMOS33;
+NET "soft_tdi"       LOC = E22  | IOSTANDARD = LVCMOS33;
+NET "soft_tck"       LOC = F21  | IOSTANDARD = LVCMOS33;
+
+# SRAM 0
+NET "sram0_a<0>"     LOC = L6   | IOSTANDARD = LVCMOS33;
+NET "sram0_a<1>"     LOC = K4   | IOSTANDARD = LVCMOS33;
+NET "sram0_a<2>"     LOC = H5   | IOSTANDARD = LVCMOS33;
+NET "sram0_a<3>"     LOC = G6   | IOSTANDARD = LVCMOS33;
+NET "sram0_a<4>"     LOC = F3   | IOSTANDARD = LVCMOS33; 
+NET "sram0_a<5>"     LOC = G1   | IOSTANDARD = LVCMOS33; 
+NET "sram0_a<6>"     LOC = G2   | IOSTANDARD = LVCMOS33; 
+NET "sram0_a<7>"     LOC = K3   | IOSTANDARD = LVCMOS33; 
+NET "sram0_a<8>"     LOC = T2   | IOSTANDARD = LVCMOS33;
+NET "sram0_a<9>"     LOC = T1   | IOSTANDARD = LVCMOS33;
+NET "sram0_a<10>"    LOC = U2   | IOSTANDARD = LVCMOS33; 
+NET "sram0_a<11>"    LOC = V3   | IOSTANDARD = LVCMOS33; 
+NET "sram0_a<12>"    LOC = V1   | IOSTANDARD = LVCMOS33;
+NET "sram0_a<13>"    LOC = W1   | IOSTANDARD = LVCMOS33;
+NET "sram0_a<14>"    LOC = V2   | IOSTANDARD = LVCMOS33;
+NET "sram0_a<15>"    LOC = V5   | IOSTANDARD = LVCMOS33; 
+NET "sram0_a<16>"    LOC = V4   | IOSTANDARD = LVCMOS33;
+NET "sram0_a<17>"    LOC = U5   | IOSTANDARD = LVCMOS33;
+NET "sram0_a<18>"    LOC = U6   | IOSTANDARD = LVCMOS33; # n.c. 
+NET "sram0_d<0>"     LOC = L4   | IOSTANDARD = LVCMOS33;
+NET "sram0_d<1>"     LOC = L3   | IOSTANDARD = LVCMOS33;
+NET "sram0_d<2>"     LOC = M5   | IOSTANDARD = LVCMOS33;
+NET "sram0_d<3>"     LOC = M4   | IOSTANDARD = LVCMOS33;
+NET "sram0_d<4>"     LOC = M3   | IOSTANDARD = LVCMOS33;
+NET "sram0_d<5>"     LOC = N4   | IOSTANDARD = LVCMOS33;
+NET "sram0_d<6>"     LOC = N3   | IOSTANDARD = LVCMOS33;
+NET "sram0_d<7>"     LOC = T5   | IOSTANDARD = LVCMOS33;
+NET "sram0_d<8>"     LOC = T4   | IOSTANDARD = LVCMOS33;
+NET "sram0_d<9>"     LOC = T6   | IOSTANDARD = LVCMOS33;
+NET "sram0_d<10>"    LOC = M6   | IOSTANDARD = LVCMOS33; 
+NET "sram0_d<11>"    LOC = N2   | IOSTANDARD = LVCMOS33;
+NET "sram0_d<12>"    LOC = N1   | IOSTANDARD = LVCMOS33;
+NET "sram0_d<13>"    LOC = M2   | IOSTANDARD = LVCMOS33;
+NET "sram0_d<14>"    LOC = M1   | IOSTANDARD = LVCMOS33;
+NET "sram0_d<15>"    LOC = L2   | IOSTANDARD = LVCMOS33;
+NET "sram0_cs_n"     LOC = L5   | IOSTANDARD = LVCMOS33;
+NET "sram0_lb_n"     LOC = L1   | IOSTANDARD = LVCMOS33;
+NET "sram0_ub_n"     LOC = K2   | IOSTANDARD = LVCMOS33;
+NET "sram0_we_n"     LOC = U4   | IOSTANDARD = LVCMOS33;
+NET "sram0_oe_n"     LOC = K1   | IOSTANDARD = LVCMOS33;
+
+# SRAM 1
+NET "sram1_a<0>"     LOC = K21  | IOSTANDARD = LVCMOS33;
+NET "sram1_a<1>"     LOC = K22  | IOSTANDARD = LVCMOS33;
+NET "sram1_a<2>"     LOC = K20  | IOSTANDARD = LVCMOS33;
+NET "sram1_a<3>"     LOC = G21  | IOSTANDARD = LVCMOS33;
+NET "sram1_a<4>"     LOC = G22  | IOSTANDARD = LVCMOS33; 
+NET "sram1_a<5>"     LOC = M17  | IOSTANDARD = LVCMOS33; 
+NET "sram1_a<6>"     LOC = L18  | IOSTANDARD = LVCMOS33; 
+NET "sram1_a<7>"     LOC = K19  | IOSTANDARD = LVCMOS33; 
+NET "sram1_a<8>"     LOC = V19  | IOSTANDARD = LVCMOS33;
+NET "sram1_a<9>"     LOC = W20  | IOSTANDARD = LVCMOS33;
+NET "sram1_a<10>"    LOC = W19  | IOSTANDARD = LVCMOS33; 
+NET "sram1_a<11>"    LOC = Y20  | IOSTANDARD = LVCMOS33; 
+NET "sram1_a<12>"    LOC = Y21  | IOSTANDARD = LVCMOS33;
+NET "sram1_a<13>"    LOC = Y22  | IOSTANDARD = LVCMOS33;
+NET "sram1_a<14>"    LOC = W21  | IOSTANDARD = LVCMOS33;
+NET "sram1_a<15>"    LOC = W22  | IOSTANDARD = LVCMOS33; 
+NET "sram1_a<16>"    LOC = V21  | IOSTANDARD = LVCMOS33;
+NET "sram1_a<17>"    LOC = V22  | IOSTANDARD = LVCMOS33;
+NET "sram1_a<18>"    LOC = V20  | IOSTANDARD = LVCMOS33; # n.c. 
+NET "sram1_d<0>"     LOC = L21  | IOSTANDARD = LVCMOS33;
+NET "sram1_d<1>"     LOC = M22  | IOSTANDARD = LVCMOS33;
+NET "sram1_d<2>"     LOC = M21  | IOSTANDARD = LVCMOS33;
+NET "sram1_d<3>"     LOC = N22  | IOSTANDARD = LVCMOS33;
+NET "sram1_d<4>"     LOC = N21  | IOSTANDARD = LVCMOS33;
+NET "sram1_d<5>"     LOC = U20  | IOSTANDARD = LVCMOS33;
+NET "sram1_d<6>"     LOC = T22  | IOSTANDARD = LVCMOS33;
+NET "sram1_d<7>"     LOC = T21  | IOSTANDARD = LVCMOS33;
+NET "sram1_d<8>"     LOC = V18  | IOSTANDARD = LVCMOS33;
+NET "sram1_d<9>"     LOC = U19  | IOSTANDARD = LVCMOS33;
+NET "sram1_d<10>"    LOC = U18  | IOSTANDARD = LVCMOS33; 
+NET "sram1_d<11>"    LOC = T18  | IOSTANDARD = LVCMOS33;
+NET "sram1_d<12>"    LOC = R18  | IOSTANDARD = LVCMOS33;
+NET "sram1_d<13>"    LOC = T17  | IOSTANDARD = LVCMOS33;
+NET "sram1_d<14>"    LOC = M18  | IOSTANDARD = LVCMOS33;
+NET "sram1_d<15>"    LOC = M20  | IOSTANDARD = LVCMOS33;
+NET "sram1_cs_n"     LOC = L22  | IOSTANDARD = LVCMOS33;
+NET "sram1_lb_n"     LOC = M19  | IOSTANDARD = LVCMOS33;
+NET "sram1_ub_n"     LOC = L20  | IOSTANDARD = LVCMOS33;
+NET "sram1_we_n"     LOC = U21  | IOSTANDARD = LVCMOS33;
+NET "sram1_oe_n"     LOC = L19  | IOSTANDARD = LVCMOS33;
+
+# RS232
+NET "rs232_rx"       LOC = A5   | IOSTANDARD = LVCMOS33;
+NET "rs232_tx"       LOC = F7   | IOSTANDARD = LVCMOS33;
+NET "rs232_cts"      LOC = F2   | IOSTANDARD = LVCMOS33;
+NET "rs232_rts"      LOC = E1   | IOSTANDARD = LVCMOS33;
+                     
+# 2x PS2 connectors
+NET "mouse_clk"      LOC = L17  | IOSTANDARD = LVCMOS33;
+NET "mouse_data"     LOC = G18  | IOSTANDARD = LVCMOS33;
+NET "kbd_clk"        LOC = F20  | IOSTANDARD = LVCMOS33;
+NET "kbd_data"       LOC = G19  | IOSTANDARD = LVCMOS33;
+
+
+# VGA output (2**9 = 512 colors)
+NET "vga_blue<7>"    LOC = E14  | IOSTANDARD = LVCMOS33;
+NET "vga_blue<6>"    LOC = A13  | IOSTANDARD = LVCMOS33;
+NET "vga_blue<5>"    LOC = C13  | IOSTANDARD = LVCMOS33;
+NET "vga_green<7>"   LOC = E11  | IOSTANDARD = LVCMOS33;
+NET "vga_green<6>"   LOC = C11  | IOSTANDARD = LVCMOS33;
+NET "vga_green<5>"   LOC = D10  | IOSTANDARD = LVCMOS33;
+NET "vga_red<7>"     LOC = D6   | IOSTANDARD = LVCMOS33;
+NET "vga_red<6>"     LOC = D7   | IOSTANDARD = LVCMOS33;
+NET "vga_red<5>"     LOC = D9   | IOSTANDARD = LVCMOS33;
+NET "vga_hsync"      LOC = A8   | IOSTANDARD = LVCMOS33;
+NET "vga_vsync"      LOC = B14  | IOSTANDARD = LVCMOS33;
+
+
+# Stereo Audio out
+NET "audio_r"        LOC = U3   | IOSTANDARD = LVCMOS33;
+NET "audio_l"        LOC = W3   | IOSTANDARD = LVCMOS33;
+
+
+# GPIO DIP switches 7..0 left..right, low active
+NET "switch_n<0>"    LOC = Y6   | IOSTANDARD = LVCMOS33;
+NET "switch_n<1>"    LOC = V6   | IOSTANDARD = LVCMOS33;
+NET "switch_n<2>"    LOC = U7   | IOSTANDARD = LVCMOS33;
+NET "switch_n<3>"    LOC = AA4  | IOSTANDARD = LVCMOS33;
+NET "switch_n<4>"    LOC = AB4  | IOSTANDARD = LVCMOS33;
+NET "switch_n<5>"    LOC = AA5  | IOSTANDARD = LVCMOS33;
+NET "switch_n<6>"    LOC = AB5  | IOSTANDARD = LVCMOS33;
+NET "switch_n<7>"    LOC = AA6  | IOSTANDARD = LVCMOS33;
+
+# GPIO push buttons, low active
+NET "button_n<5>"    LOC = C21  | IOSTANDARD = LVCMOS33;
+NET "button_n<4>"    LOC = B20  | IOSTANDARD = LVCMOS33;
+NET "button_n<3>"    LOC = A15  | IOSTANDARD = LVCMOS33;
+NET "button_n<2>"    LOC = B6   | IOSTANDARD = LVCMOS33;
+NET "button_n<1>"    LOC = C1   | IOSTANDARD = LVCMOS33;
+NET "button_n<0>"    LOC = D1   | IOSTANDARD = LVCMOS33;
+
+# GPIO LEDs
+NET "led<7>"         LOC = W6   | IOSTANDARD = LVCMOS33; 
+NET "led<6>"         LOC = Y5   | IOSTANDARD = LVCMOS33;
+NET "led<5>"         LOC = W5   | IOSTANDARD = LVCMOS33;
+NET "led<4>"         LOC = W4   | IOSTANDARD = LVCMOS33;
+NET "led<3>"         LOC = Y3   | IOSTANDARD = LVCMOS33;
+NET "led<2>"         LOC = Y2   | IOSTANDARD = LVCMOS33;
+NET "led<1>"         LOC = Y1   | IOSTANDARD = LVCMOS33;
+NET "led<0>"         LOC = W2   | IOSTANDARD = LVCMOS33;
+
+# seven segment display (5=left 0=right)
+#
+# segment assignment:
+# .ABCDEFG
+# 76543210
+NET "dig0_seg<7>"    LOC = E20  | IOSTANDARD = LVCMOS33;
+NET "dig0_seg<6>"    LOC = C22  | IOSTANDARD = LVCMOS33;
+NET "dig0_seg<5>"    LOC = E18  | IOSTANDARD = LVCMOS33;
+NET "dig0_seg<4>"    LOC = D20  | IOSTANDARD = LVCMOS33;
+NET "dig0_seg<3>"    LOC = D21  | IOSTANDARD = LVCMOS33;
+NET "dig0_seg<2>"    LOC = E19  | IOSTANDARD = LVCMOS33;
+NET "dig0_seg<1>"    LOC = G17  | IOSTANDARD = LVCMOS33;
+NET "dig0_seg<0>"    LOC = F19  | IOSTANDARD = LVCMOS33;
+  
+NET "dig1_seg<7>"    LOC = F17  | IOSTANDARD = LVCMOS33;
+NET "dig1_seg<6>"    LOC = D18  | IOSTANDARD = LVCMOS33;
+NET "dig1_seg<5>"    LOC = B19  | IOSTANDARD = LVCMOS33;
+NET "dig1_seg<4>"    LOC = C18  | IOSTANDARD = LVCMOS33;
+NET "dig1_seg<3>"    LOC = C19  | IOSTANDARD = LVCMOS33;
+NET "dig1_seg<2>"    LOC = C20  | IOSTANDARD = LVCMOS33;
+NET "dig1_seg<1>"    LOC = F18  | IOSTANDARD = LVCMOS33;
+NET "dig1_seg<0>"    LOC = D19  | IOSTANDARD = LVCMOS33;
+
+NET "dig2_seg<7>"    LOC = A19  | IOSTANDARD = LVCMOS33;
+NET "dig2_seg<6>"    LOC = E17  | IOSTANDARD = LVCMOS33;
+NET "dig2_seg<5>"    LOC = C17  | IOSTANDARD = LVCMOS33;
+NET "dig2_seg<4>"    LOC = D17  | IOSTANDARD = LVCMOS33;
+NET "dig2_seg<3>"    LOC = B15  | IOSTANDARD = LVCMOS33;
+NET "dig2_seg<2>"    LOC = A18  | IOSTANDARD = LVCMOS33;
+NET "dig2_seg<1>"    LOC = B18  | IOSTANDARD = LVCMOS33;
+NET "dig2_seg<0>"    LOC = B17  | IOSTANDARD = LVCMOS33;
+
+NET "dig3_seg<7>"    LOC = D15  | IOSTANDARD = LVCMOS33;
+NET "dig3_seg<6>"    LOC = E13  | IOSTANDARD = LVCMOS33;
+NET "dig3_seg<5>"    LOC = B13  | IOSTANDARD = LVCMOS33;
+NET "dig3_seg<4>"    LOC = D13  | IOSTANDARD = LVCMOS33;
+NET "dig3_seg<3>"    LOC = D14  | IOSTANDARD = LVCMOS33;
+NET "dig3_seg<2>"    LOC = A14  | IOSTANDARD = LVCMOS33;
+NET "dig3_seg<1>"    LOC = E16  | IOSTANDARD = LVCMOS33;
+NET "dig3_seg<0>"    LOC = E15  | IOSTANDARD = LVCMOS33;
+
+NET "dig4_seg<7>"    LOC = D11  | IOSTANDARD = LVCMOS33;
+NET "dig4_seg<6>"    LOC = E9   | IOSTANDARD = LVCMOS33;
+NET "dig4_seg<5>"    LOC = A10  | IOSTANDARD = LVCMOS33;
+NET "dig4_seg<4>"    LOC = B9   | IOSTANDARD = LVCMOS33;
+NET "dig4_seg<3>"    LOC = A9   | IOSTANDARD = LVCMOS33;
+NET "dig4_seg<2>"    LOC = C10  | IOSTANDARD = LVCMOS33;
+NET "dig4_seg<1>"    LOC = A12  | IOSTANDARD = LVCMOS33;
+NET "dig4_seg<0>"    LOC = B10  | IOSTANDARD = LVCMOS33;
+
+NET "dig5_seg<7>"    LOC = C7   | IOSTANDARD = LVCMOS33;
+NET "dig5_seg<6>"    LOC = A4   | IOSTANDARD = LVCMOS33;
+NET "dig5_seg<5>"    LOC = B5   | IOSTANDARD = LVCMOS33;
+NET "dig5_seg<4>"    LOC = E6   | IOSTANDARD = LVCMOS33;
+NET "dig5_seg<3>"    LOC = C5   | IOSTANDARD = LVCMOS33;
+NET "dig5_seg<2>"    LOC = E7   | IOSTANDARD = LVCMOS33;
+NET "dig5_seg<1>"    LOC = B8   | IOSTANDARD = LVCMOS33;
+NET "dig5_seg<0>"    LOC = C6   | IOSTANDARD = LVCMOS33;
+
+
+# Header A (left)
+NET "header_a<2>"    LOC = V7   | IOSTANDARD = LVCMOS33;  
+NET "header_a<3>"    LOC = AA8  | IOSTANDARD = LVCMOS33; 
+NET "header_a<4>"    LOC = AB8  | IOSTANDARD = LVCMOS33; 
+NET "header_a<5>"    LOC = V8   | IOSTANDARD = LVCMOS33;  
+NET "header_a<6>"    LOC = Y10  | IOSTANDARD = LVCMOS33; 
+NET "header_a<7>"    LOC = V9   | IOSTANDARD = LVCMOS33;  
+NET "header_a<8>"    LOC = W9   | IOSTANDARD = LVCMOS33;  
+NET "header_a<9>"    LOC = AA10 | IOSTANDARD = LVCMOS33;
+NET "header_a<10>"   LOC = AB10 | IOSTANDARD = LVCMOS33; 
+NET "header_a<11>"   LOC = W10  | IOSTANDARD = LVCMOS33;  
+NET "header_a<12>"   LOC = AB11 | IOSTANDARD = LVCMOS33;
+NET "header_a<13>"   LOC = U11  | IOSTANDARD = LVCMOS33;
+NET "header_a<14>"   LOC = AB13 | IOSTANDARD = LVCMOS33;
+NET "header_a<15>"   LOC = AA13 | IOSTANDARD = LVCMOS33;
+NET "header_a<16>"   LOC = V10  | IOSTANDARD = LVCMOS33;
+NET "header_a<17>"   LOC = U10  | IOSTANDARD = LVCMOS33;
+NET "header_a<18>"   LOC = W13  | IOSTANDARD = LVCMOS33;
+NET "header_a<19>"   LOC = Y13  | IOSTANDARD = LVCMOS33;
+
+# Header B (right)
+NET "header_b<2>"    LOC = V14  | IOSTANDARD = LVCMOS33;  
+NET "header_b<3>"    LOC = V13  | IOSTANDARD = LVCMOS33;
+NET "header_b<4>"    LOC = AA15 | IOSTANDARD = LVCMOS33;
+NET "header_b<5>"    LOC = W14  | IOSTANDARD = LVCMOS33;
+NET "header_b<6>"    LOC = AB15 | IOSTANDARD = LVCMOS33;
+NET "header_b<7>"    LOC = Y16  | IOSTANDARD = LVCMOS33;
+NET "header_b<8>"    LOC = AA17 | IOSTANDARD = LVCMOS33;
+NET "header_b<9>"    LOC = AA18 | IOSTANDARD = LVCMOS33;
+NET "header_b<10>"   LOC = AB18 | IOSTANDARD = LVCMOS33;
+NET "header_b<11>"   LOC = Y18  | IOSTANDARD = LVCMOS33;
+NET "header_b<12>"   LOC = Y19  | IOSTANDARD = LVCMOS33;
+NET "header_b<13>"   LOC = AB20 | IOSTANDARD = LVCMOS33;
+NET "header_b<14>"   LOC = AA20 | IOSTANDARD = LVCMOS33;
+NET "header_b<15>"   LOC = U16  | IOSTANDARD = LVCMOS33;
+NET "header_b<16>"   LOC = V16  | IOSTANDARD = LVCMOS33;
+NET "header_b<17>"   LOC = V17  | IOSTANDARD = LVCMOS33;
+NET "header_b<18>"   LOC = W16  | IOSTANDARD = LVCMOS33;
+NET "header_b<19>"   LOC = W17  | IOSTANDARD = LVCMOS33;
+
+# usused pins
+CONFIG PROHIBIT = A3;
+CONFIG PROHIBIT = A7;
+CONFIG PROHIBIT = A11;
+CONFIG PROHIBIT = A16;
+CONFIG PROHIBIT = AA3;
+CONFIG PROHIBIT = AA7;
+CONFIG PROHIBIT = AA9;
+CONFIG PROHIBIT = AA11;
+CONFIG PROHIBIT = AA14;
+CONFIG PROHIBIT = AA16;
+CONFIG PROHIBIT = AA19;
+CONFIG PROHIBIT = AB7;
+CONFIG PROHIBIT = AB9;
+CONFIG PROHIBIT = AB12;
+CONFIG PROHIBIT = AB14;
+CONFIG PROHIBIT = AB16;
+CONFIG PROHIBIT = AB19;
+CONFIG PROHIBIT = B4;
+CONFIG PROHIBIT = B7;
+CONFIG PROHIBIT = B12;
+CONFIG PROHIBIT = B11;
+CONFIG PROHIBIT = B16;
+CONFIG PROHIBIT = C2;
+CONFIG PROHIBIT = C3;
+CONFIG PROHIBIT = C4;
+CONFIG PROHIBIT = C12;
+CONFIG PROHIBIT = C16;
+CONFIG PROHIBIT = D2;
+CONFIG PROHIBIT = D3;
+CONFIG PROHIBIT = D4;
+CONFIG PROHIBIT = D5;
+CONFIG PROHIBIT = D8;
+CONFIG PROHIBIT = D12;
+CONFIG PROHIBIT = D16;
+CONFIG PROHIBIT = E2;
+CONFIG PROHIBIT = E3;
+CONFIG PROHIBIT = E8;
+CONFIG PROHIBIT = E4;
+CONFIG PROHIBIT = E5;
+CONFIG PROHIBIT = F4;
+CONFIG PROHIBIT = E10;
+CONFIG PROHIBIT = E12;
+CONFIG PROHIBIT = F12;
+CONFIG PROHIBIT = F5;
+CONFIG PROHIBIT = F13;
+CONFIG PROHIBIT = F6;
+CONFIG PROHIBIT = F9;
+CONFIG PROHIBIT = F10;
+CONFIG PROHIBIT = F16;
+CONFIG PROHIBIT = F11;
+CONFIG PROHIBIT = F14;
+CONFIG PROHIBIT = G3;
+CONFIG PROHIBIT = G4;
+CONFIG PROHIBIT = G5;
+CONFIG PROHIBIT = G20;
+CONFIG PROHIBIT = H1;
+CONFIG PROHIBIT = H2;
+CONFIG PROHIBIT = H4;
+CONFIG PROHIBIT = H18;
+CONFIG PROHIBIT = H19;
+CONFIG PROHIBIT = H21;
+CONFIG PROHIBIT = H22;
+CONFIG PROHIBIT = J1;
+CONFIG PROHIBIT = J2;
+CONFIG PROHIBIT = J4;
+CONFIG PROHIBIT = J5;
+CONFIG PROHIBIT = J6;
+CONFIG PROHIBIT = J17;
+CONFIG PROHIBIT = J18;
+CONFIG PROHIBIT = J19;
+CONFIG PROHIBIT = J21;
+CONFIG PROHIBIT = J22;
+CONFIG PROHIBIT = K5;
+CONFIG PROHIBIT = K6;
+CONFIG PROHIBIT = K17;
+CONFIG PROHIBIT = K18;
+CONFIG PROHIBIT = N5;
+CONFIG PROHIBIT = N6;
+CONFIG PROHIBIT = N17;
+CONFIG PROHIBIT = N18;
+CONFIG PROHIBIT = N19;
+CONFIG PROHIBIT = N20;
+CONFIG PROHIBIT = P1;
+CONFIG PROHIBIT = P2;
+CONFIG PROHIBIT = P4;
+CONFIG PROHIBIT = P5;
+CONFIG PROHIBIT = P6;
+CONFIG PROHIBIT = P17;
+CONFIG PROHIBIT = P18;
+CONFIG PROHIBIT = P19;
+CONFIG PROHIBIT = P21;
+CONFIG PROHIBIT = P22;
+CONFIG PROHIBIT = R1;
+CONFIG PROHIBIT = R2;
+CONFIG PROHIBIT = R4;
+CONFIG PROHIBIT = R5;
+CONFIG PROHIBIT = R19;
+CONFIG PROHIBIT = R21;
+CONFIG PROHIBIT = R22;
+CONFIG PROHIBIT = T3;
+CONFIG PROHIBIT = T19;
+CONFIG PROHIBIT = T20;
+CONFIG PROHIBIT = U9;
+CONFIG PROHIBIT = U12;
+CONFIG PROHIBIT = U13;
+CONFIG PROHIBIT = U14;
+CONFIG PROHIBIT = U17;
+CONFIG PROHIBIT = V11;
+CONFIG PROHIBIT = V12;
+CONFIG PROHIBIT = V15;
+CONFIG PROHIBIT = W7;
+CONFIG PROHIBIT = W8;
+CONFIG PROHIBIT = W11;
+CONFIG PROHIBIT = W12;
+CONFIG PROHIBIT = W15;
+CONFIG PROHIBIT = W18;
+CONFIG PROHIBIT = Y4;
+CONFIG PROHIBIT = Y7;
+CONFIG PROHIBIT = Y11;
+CONFIG PROHIBIT = Y12;
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.prj b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.prj
new file mode 100644
index 0000000..24120d5
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.prj
@@ -0,0 +1,19 @@
+vhdl work ../top.vhd
+vhdl zpu ../../../zpu_pkg.vhdl
+vhdl zpu ../../../zpu_small.vhdl
+vhdl zpu ../../../zpu_medium.vhdl
+vhdl zpu ../../../roms/rom_pkg.vhdl
+#vhdl zpu ../../../roms/hello_dbram.vhdl
+#vhdl zpu ../../../roms/hello_bram.vhdl
+vhdl zpu ../../../roms/dmips_dbram.vhdl
+vhdl zpu ../../../roms/dmips_bram.vhdl
+vhdl zpu ../../../helpers/zpu_small1.vhdl
+vhdl zpu ../../../helpers/zpu_med1.vhdl
+vhdl zpu ../../../devices/txt_util.vhdl
+vhdl zpu ../../../devices/phi_io.vhdl
+vhdl zpu ../../../devices/timer.vhdl
+vhdl zpu ../../../devices/gpio.vhdl
+vhdl zpu ../../../devices/rx_unit.vhdl
+vhdl zpu ../../../devices/tx_unit.vhdl
+vhdl zpu ../../../devices/br_gen.vhdl
+vhdl zpu ../../../devices/trace.vhdl
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.ut b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.ut
new file mode 100644
index 0000000..765a6f3
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.ut
@@ -0,0 +1,29 @@
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g ConfigRate:6
+-g CclkPin:PullUp
+-g M0Pin:PullUp
+-g M1Pin:PullUp
+-g M2Pin:PullUp
+-g ProgPin:PullUp
+-g DonePin:PullUp
+-g HswapenPin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g DCMShutdown:Disable
+-g DCIUpdateMode:AsRequired
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Match_cycle:Auto
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.xst b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.xst
new file mode 100644
index 0000000..14873ea
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.xst
@@ -0,0 +1,56 @@
+set -tmpdir "tmp"
+set -xsthdpdir "xst"
+run
+-ifn ../synthesis_config/top.prj
+-ifmt mixed
+-ofn top
+-ofmt NGC
+-p xc3s1000-4-fg456
+-top top
+-opt_mode Speed
+-opt_level 1
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract Yes
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-auto_bram_packing NO
+-mux_extract Yes
+-resource_sharing YES
+-async_to_sync NO
+-mult_style Auto
+-iobuf YES
+-max_fanout 500
+-bufg 8
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Yes
+-use_sync_set Yes
+-use_sync_reset Yes
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top.vhd b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top.vhd
new file mode 100644
index 0000000..4a93c4f
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top.vhd
@@ -0,0 +1,372 @@
+-- top module of
+-- Altium LiveDesign Board
+--
+-- using following external connections:
+-- test button as reset
+-- LEDs and 7 segment for output
+-- RS232
+--
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library zpu;
+use zpu.zpupkg.all;   -- zpu_dbgo_t
+
+library unisim;
+use unisim.vcomponents.dcm;
+
+
+entity top is
+    port (
+        -- pragma translate_off 
+        stop_simulation : out   std_logic;
+        -- pragma translate_on 
+        clk_50     : in    std_logic;
+        reset_n    : in    std_logic;
+        --
+        -- soft JTAG
+        soft_tdo   : out   std_logic;
+        soft_tms   : in    std_logic;
+        soft_tdi   : in    std_logic;
+        soft_tck   : in    std_logic;
+        --
+        -- SRAM 0 (256k x 16) pin connections
+        sram0_a    : out   std_logic_vector(18 downto 0);
+        sram0_d    : inout std_logic_vector(15 downto 0);
+        sram0_lb_n : out   std_logic;
+        sram0_ub_n : out   std_logic;
+        sram0_cs_n : out   std_logic;       -- chip select
+        sram0_we_n : out   std_logic;       -- write-enable
+        sram0_oe_n : out   std_logic;       -- output enable
+        --
+        -- SRAM 1 (256k x 16) pin connections
+        sram1_a    : out   std_logic_vector(18 downto 0);
+        sram1_d    : inout std_logic_vector(15 downto 0);
+        sram1_lb_n : out   std_logic;
+        sram1_ub_n : out   std_logic;
+        sram1_cs_n : out   std_logic;       -- chip select
+        sram1_we_n : out   std_logic;       -- write-enable
+        sram1_oe_n : out   std_logic;       -- output enable
+        --
+        -- RS232
+        rs232_rx   : in    std_logic;
+        rs232_tx   : out   std_logic;
+        rs232_cts  : in    std_logic;
+        rs232_rts  : out   std_logic;
+        --
+        -- PS2 connectors
+        mouse_clk  : inout std_logic;
+        mouse_data : inout std_logic;
+        kbd_clk    : inout std_logic;
+        kbd_data   : inout std_logic;
+        --
+        -- vga output
+        vga_red    : out   std_logic_vector(7 downto 5);
+        vga_green  : out   std_logic_vector(7 downto 5);
+        vga_blue   : out   std_logic_vector(7 downto 5);
+        vga_hsync  : out   std_logic;
+        vga_vsync  : out   std_logic;
+        --
+        -- Audio out
+        audio_r    : out   std_logic;
+        audio_l    : out   std_logic;
+        --
+        -- GPIOs
+        switch_n   : in    std_logic_vector(7 downto 0);
+        button_n   : in    std_logic_vector(5 downto 0);
+        led        : out   std_logic_vector(7 downto 0);
+        --
+        -- seven segment display
+        dig0_seg   : out   std_logic_vector(7 downto 0);
+        dig1_seg   : out   std_logic_vector(7 downto 0);
+        dig2_seg   : out   std_logic_vector(7 downto 0);
+        dig3_seg   : out   std_logic_vector(7 downto 0);
+        dig4_seg   : out   std_logic_vector(7 downto 0);
+        dig5_seg   : out   std_logic_vector(7 downto 0);
+        --
+        -- User Header
+        header_a   : inout std_logic_vector(19 downto 2);
+        header_b   : inout std_logic_vector(19 downto 2)
+    );
+end entity top;
+
+
+architecture rtl of top is
+
+
+    ---------------------------
+    -- type declarations
+    type zpu_type is (zpu_small, zpu_medium);
+
+    ---------------------------
+    -- constant declarations
+    constant zpu_flavour   : zpu_type := zpu_medium;  -- choose your flavour HERE
+    --  modify frequency here
+    constant clk_multiply  : positive := 3; -- 9 for small, 3 for medium
+    constant clk_divide    : positive := 2; -- 5 for small, 2 for medium
+    --
+    constant word_size_c   : natural  := 32; -- 32 bits data path
+    constant addr_w_c      : natural  := 18; -- 18 bits address space=256 kB, 128 kB I/O
+
+    constant clk_frequency : positive := 50; -- input frequency for correct calculation
+
+
+    ---------------------------
+    -- component declarations
+    component zpu_small1 is
+        generic (
+            word_size  : natural   := 32;      -- 32 bits data path
+            d_care_val : std_logic := '0';     -- Fill value
+            clk_freq   : positive  := 50;      -- 50 MHz clock
+            brate      : positive  := 115200;  -- RS232 baudrate
+            addr_w     : natural   := 16;      -- 16 bits address space=64 kB, 32 kB I/O
+            bram_w     : natural   := 15       -- 15 bits RAM space=32 kB
+            );
+        port (
+            clk_i      : in  std_logic;        -- CPU clock
+            rst_i      : in  std_logic;        -- Reset
+            break_o    : out std_logic;        -- Break executed
+            dbg_o      : out zpu_dbgo_t;       -- Debug info
+            rs232_tx_o : out std_logic;        -- UART Tx
+            rs232_rx_i : in  std_logic;        -- UART Rx
+            gpio_in    : in  std_logic_vector(31 downto 0);
+            gpio_out   : out std_logic_vector(31 downto 0);
+            gpio_dir   : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
+            );
+    end component zpu_small1;
+
+    component zpu_med1 is
+        generic(
+            word_size  : natural   := 32;      -- 32 bits data path
+            d_care_val : std_logic := '0';     -- Fill value
+            clk_freq   : positive  := 50;      -- 50 MHz clock
+            brate      : positive  := 115200;  -- RS232 baudrate
+            addr_w     : natural   := 18;      -- 18 bits address space=256 kB, 128 kB I/O
+            bram_w     : natural   := 15       -- 15 bits RAM space=32 kB
+            );
+        port(
+            clk_i      : in  std_logic;        -- CPU clock
+            rst_i      : in  std_logic;        -- Reset
+            break_o    : out std_logic;        -- Break executed
+            dbg_o      : out zpu_dbgo_t;       -- Debug info
+            rs232_tx_o : out std_logic;        -- UART Tx
+            rs232_rx_i : in  std_logic;        -- UART Rx
+            gpio_in    : in  std_logic_vector(31 downto 0);
+            gpio_out   : out std_logic_vector(31 downto 0);
+            gpio_dir   : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
+            );
+    end component zpu_med1;
+
+
+    ---------------------------
+    -- signal declarations
+    signal dcm_i0_clk0     : std_ulogic;
+    signal dcm_i0_clkfx    : std_ulogic;
+    signal clk_fb          : std_ulogic;
+    signal clk             : std_ulogic;
+    --
+    signal reset_shift_reg : std_ulogic_vector(3 downto 0);
+    signal reset_sync      : std_ulogic;
+    --
+    signal zpu_i0_dbg      : zpu_dbgo_t;  -- Debug info
+    signal zpu_i0_break    : std_logic;
+    --
+    signal gpio_in         : std_logic_vector(31 downto 0) := (others => '0');
+    signal zpu_i0_gpio_out : std_logic_vector(31 downto 0);
+    signal zpu_i0_gpio_dir : std_logic_vector(31 downto 0);
+
+
+begin
+
+    -- default output drivers
+    -- to pass bitgen DRC 
+    -- outputs used by design are commented
+    soft_tdo   <= '1';
+    --
+    sram0_a    <= (others => '1');
+    sram0_d    <= (others => 'Z');
+    sram0_lb_n <= '1';
+    sram0_ub_n <= '1';
+    sram0_cs_n <= '1';
+    sram0_we_n <= '1';
+    sram0_oe_n <= '1';
+    --
+    sram1_a    <= (others => '1');
+    sram1_d    <= (others => 'Z');
+    sram1_lb_n <= '1';
+    sram1_ub_n <= '1';
+    sram1_cs_n <= '1';
+    sram1_we_n <= '1';
+    sram1_oe_n <= '1';
+    --
+    --rs232_tx   <= '1';
+    rs232_rts  <= '1';
+    --
+    mouse_clk  <= 'Z'; 
+    mouse_data <= 'Z'; 
+    kbd_clk    <= 'Z'; 
+    kbd_data   <= 'Z'; 
+    --
+    vga_red    <= (others => '1');
+    vga_green  <= (others => '1');
+    vga_blue   <= (others => '1');
+    vga_hsync  <= '1';
+    vga_vsync  <= '1';
+    --
+    audio_r    <= '0';
+    audio_l    <= '0';
+    --
+    --led        <= (others => '0');
+    --
+    --dig0_seg   <= (others => '0');
+    --dig1_seg   <= (others => '0');
+    dig2_seg   <= (others => '0');
+    dig3_seg   <= (others => '0');
+    dig4_seg   <= (others => '0');
+    dig5_seg   <= (others => '0');
+    --
+    header_a   <= (others => 'Z');
+    header_b   <= (others => 'Z');
+
+
+    -- digital clock manager (DCM)
+    -- to generate higher/other system clock frequencys
+    dcm_i0 : dcm
+        generic map (
+            startup_wait   => true,     -- wait with DONE till locked
+            clkfx_multiply => clk_multiply,
+            clkfx_divide   => clk_divide, 
+            clk_feedback   => "1X"
+            )
+        port map (
+            clkin => clk_50,
+            clk0  => dcm_i0_clk0,
+            clkfx => dcm_i0_clkfx,
+            clkfb => clk_fb
+            );
+
+    clk_fb <= dcm_i0_clk0;
+    clk    <= dcm_i0_clkfx;
+
+
+    -- reset synchronizer
+    -- generate synchronous reset
+    reset_synchronizer : process(clk, reset_n)
+    begin
+        if reset_n = '0' then
+            reset_shift_reg <= (others => '1');
+        elsif rising_edge(clk) then
+            reset_shift_reg <= reset_shift_reg(reset_shift_reg'high-1 downto 0) & '0';
+        end if;
+    end process;
+    reset_sync <= reset_shift_reg(reset_shift_reg'high);
+
+
+    -- select instance of zpu
+    zpu_i0_small : if zpu_flavour = zpu_small generate
+        zpu_i0 : zpu_small1
+            generic map (
+                addr_w    => addr_w_c,
+                word_size => word_size_c,
+                clk_freq  => clk_frequency * clk_multiply / clk_divide
+                )
+            port map (
+                clk_i      => clk,             -- : in  std_logic;   -- CPU clock
+                rst_i      => reset_sync,      -- : in  std_logic;   -- Reset
+                break_o    => zpu_i0_break,    -- : out std_logic;   -- Break executed
+                dbg_o      => zpu_i0_dbg,      -- : out zpu_dbgo_t;  -- Debug info
+                rs232_tx_o => rs232_tx,        -- : out std_logic;   -- UART Tx
+                rs232_rx_i => rs232_rx,        -- : in  std_logic    -- UART Rx
+                gpio_in    => gpio_in,         -- : in  std_logic_vector(31 downto 0);
+                gpio_out   => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
+                gpio_dir   => zpu_i0_gpio_dir  -- : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
+                );
+    end generate zpu_i0_small;
+
+    zpu_i0_medium : if zpu_flavour = zpu_medium generate
+        zpu_i0 : zpu_med1
+            generic map (
+                addr_w    => addr_w_c,
+                word_size => word_size_c,
+                clk_freq  => clk_frequency * clk_multiply / clk_divide
+                )
+            port map (
+                clk_i      => clk,             -- : in  std_logic;   -- CPU clock
+                rst_i      => reset_sync,      -- : in  std_logic;   -- Reset
+                break_o    => zpu_i0_break,    -- : out std_logic;   -- Break executed
+                dbg_o      => zpu_i0_dbg,      -- : out zpu_dbgo_t;  -- Debug info
+                rs232_tx_o => rs232_tx,        -- : out std_logic;   -- UART Tx
+                rs232_rx_i => rs232_rx,        -- : in  std_logic    -- UART Rx
+                gpio_in    => gpio_in,         -- : in  std_logic_vector(31 downto 0);
+                gpio_out   => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
+                gpio_dir   => zpu_i0_gpio_dir  -- : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
+                );
+    end generate zpu_i0_medium;
+
+
+    -- pragma translate_off 
+    stop_simulation <= zpu_i0_break;
+
+
+    trace_mod : trace
+        generic map (
+            addr_w    => addr_w_c,
+            word_size => word_size_c,
+            log_file  => "zpu_trace.log"
+            )
+        port map (
+            clk_i  => clk,
+            dbg_i  => zpu_i0_dbg,
+            stop_i => zpu_i0_break,
+            busy_i => '0'
+            );
+    -- pragma translate_on
+
+
+    -- assign GPIOs
+    --
+    -- bit   31 30 29 28 27 26 25 24  23 22 21 20 19 18 17 16  
+    --
+    --  in   header_a(19.........12)  -- -- -- -- -- -- -- --  
+    -- out   header_a(19.........12)  dig1_seg(7...........0)  
+    --
+    --
+    -- bit   15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
+    --                                                       
+    --  in   switch_n(7...........0)  -- --  button_n(5....0)
+    -- out   dig0_seg(7...........0)  led(7................0)
+    --
+
+    gpio_in(31 downto 24) <= header_a(19 downto 12);
+    gpio_in(15 downto 8)  <= switch_n;
+    gpio_in( 5 downto 0)  <= button_n;
+
+    -- 3-state buffers for some headers
+    header_a(19) <= zpu_i0_gpio_out(31) when zpu_i0_gpio_dir(31) = '0' else 'Z';
+    header_a(18) <= zpu_i0_gpio_out(30) when zpu_i0_gpio_dir(30) = '0' else 'Z';
+    header_a(17) <= zpu_i0_gpio_out(29) when zpu_i0_gpio_dir(29) = '0' else 'Z';
+    header_a(16) <= zpu_i0_gpio_out(28) when zpu_i0_gpio_dir(28) = '0' else 'Z';
+    header_a(15) <= zpu_i0_gpio_out(27) when zpu_i0_gpio_dir(27) = '0' else 'Z';
+    header_a(14) <= zpu_i0_gpio_out(26) when zpu_i0_gpio_dir(26) = '0' else 'Z';
+    header_a(13) <= zpu_i0_gpio_out(25) when zpu_i0_gpio_dir(25) = '0' else 'Z';
+    header_a(12) <= zpu_i0_gpio_out(24) when zpu_i0_gpio_dir(24) = '0' else 'Z';
+
+    -- outputs    
+    dig1_seg <= zpu_i0_gpio_out(23 downto 16);
+    dig0_seg <= zpu_i0_gpio_out(15 downto  8);
+
+    -- switch on all LEDs in case of break
+    process
+    begin
+        wait until rising_edge(clk);
+        led <= zpu_i0_gpio_out(7 downto 0);
+        if zpu_i0_break = '1' then
+            led <= (others => '1');
+        end if;
+    end process;
+
+
+end architecture rtl;
+
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top_tb.vhd b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top_tb.vhd
new file mode 100644
index 0000000..e42fc20
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top_tb.vhd
@@ -0,0 +1,194 @@
+-- testbench for
+-- Altium LiveDesign Board
+--
+-- includes "model" for clock generation
+-- simulate press on test/reset as reset
+--
+-- place models for external components (SRAM, PS2) in this file
+--
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity top_tb is
+end entity top_tb;
+
+architecture testbench of top_tb is
+
+    ---------------------------
+    -- constant declarations
+    constant clk_period : time := 1 sec / 50_000_000;  -- 50 MHz
+
+
+    ---------------------------
+    -- signal declarations
+    signal simulation_run     : boolean := true;
+    signal tb_stop_simulation : std_logic;
+    --
+    signal tb_clk             : std_logic                     := '0';
+    signal tb_reset_n         : std_logic;
+    --
+    -- soft JTAG
+    signal tb_soft_tdo        : std_logic;
+    signal tb_soft_tms        : std_logic                     := '1';
+    signal tb_soft_tdi        : std_logic                     := '1';
+    signal tb_soft_tck        : std_logic                     := '1';
+    --
+    -- SRAM 0 (256k x 16) pin connections
+    signal tb_sram0_a         : std_logic_vector(18 downto 0);
+    signal tb_sram0_d         : std_logic_vector(15 downto 0) := (others => 'Z');
+    signal tb_sram0_lb_n      : std_logic;
+    signal tb_sram0_ub_n      : std_logic;
+    signal tb_sram0_cs_n      : std_logic;     -- chip select
+    signal tb_sram0_we_n      : std_logic;     -- write-enable
+    signal tb_sram0_oe_n      : std_logic;     -- output enable
+    --
+    -- SRAM 1 (256k x 16) pin connections
+    signal tb_sram1_a         : std_logic_vector(18 downto 0);
+    signal tb_sram1_d         : std_logic_vector(15 downto 0) := (others => 'Z');
+    signal tb_sram1_lb_n      : std_logic;
+    signal tb_sram1_ub_n      : std_logic;
+    signal tb_sram1_cs_n      : std_logic;     -- chip select
+    signal tb_sram1_we_n      : std_logic;     -- write-enable
+    signal tb_sram1_oe_n      : std_logic;     -- output enable
+    --
+    -- RS232
+    signal tb_rs232_rx        : std_logic                     := '1';
+    signal tb_rs232_tx        : std_logic;
+    signal tb_rs232_cts       : std_logic                     := '1';
+    signal tb_rs232_rts       : std_logic;
+    --
+    -- PS2 connectors
+    signal tb_mouse_clk       : std_logic                     := 'Z';
+    signal tb_mouse_data      : std_logic                     := 'Z';
+    signal tb_kbd_clk         : std_logic                     := 'Z';
+    signal tb_kbd_data        : std_logic                     := 'Z';
+    --
+    -- vga output
+    signal tb_vga_red         : std_logic_vector(7 downto 5);
+    signal tb_vga_green       : std_logic_vector(7 downto 5);
+    signal tb_vga_blue        : std_logic_vector(7 downto 5);
+    signal tb_vga_hsync       : std_logic;
+    signal tb_vga_vsync       : std_logic;
+    --
+    -- Audio out
+    signal tb_audio_r         : std_logic;
+    signal tb_audio_l         : std_logic;
+    --
+    -- GPIOs
+    signal tb_switch_n        : std_logic_vector(7 downto 0)  := (others => '1');
+    signal tb_button_n        : std_logic_vector(5 downto 0)  := (others => '1');
+    signal tb_led             : std_logic_vector(7 downto 0);
+    --
+    -- seven segment display
+    signal tb_dig0_seg        : std_logic_vector(7 downto 0);
+    signal tb_dig1_seg        : std_logic_vector(7 downto 0);
+    signal tb_dig2_seg        : std_logic_vector(7 downto 0);
+    signal tb_dig3_seg        : std_logic_vector(7 downto 0);
+    signal tb_dig4_seg        : std_logic_vector(7 downto 0);
+    signal tb_dig5_seg        : std_logic_vector(7 downto 0);
+    --
+    -- User Header A
+    signal tb_header_a        : std_logic_vector(19 downto 2) := (others => 'Z');
+    signal tb_header_b        : std_logic_vector(19 downto 2) := (others => 'Z');
+
+begin
+
+    -- generate clock
+    tb_clk <= not tb_clk after clk_period / 2 when simulation_run;
+
+    -- generate reset
+    tb_reset_n <= '0', '1' after 6.66 * clk_period;
+
+
+    -- simulate keypress
+    tb_button_n(2) <= '1', '0' after 50 us, '1' after 52 us;
+
+    -- dut
+    top_i0 : entity work.top
+        port map (
+            stop_simulation => tb_stop_simulation, -- : out   std_logic;
+            --
+            clk_50     => tb_clk,        -- : in    std_logic;
+            reset_n    => tb_reset_n,    -- : in    std_logic;
+            --
+            -- soft JTAG
+            soft_tdo   => tb_soft_tdo,   -- : out   std_logic;
+            soft_tms   => tb_soft_tms,   -- : in    std_logic;
+            soft_tdi   => tb_soft_tdi,   -- : in    std_logic;
+            soft_tck   => tb_soft_tck,   -- : in    std_logic;
+            --
+            -- SRAM 0 (256k x 16) pin connections
+            sram0_a    => tb_sram0_a,    -- : out   std_logic_vector(18 downto 0);
+            sram0_d    => tb_sram0_d,    -- : inout std_logic_vector(15 downto 0);
+            sram0_lb_n => tb_sram0_lb_n, -- : out   std_logic;
+            sram0_ub_n => tb_sram0_ub_n, -- : out   std_logic;
+            sram0_cs_n => tb_sram0_cs_n, -- : out   std_logic;       -- chip select
+            sram0_we_n => tb_sram0_we_n, -- : out   std_logic;       -- write-enable
+            sram0_oe_n => tb_sram0_oe_n, -- : out   std_logic;       -- output enable
+            --
+            -- SRAM 1 (256k x 16) pin connections
+            sram1_a    => tb_sram1_a,    -- : out   std_logic_vector(18 downto 0);
+            sram1_d    => tb_sram1_d,    -- : inout std_logic_vector(15 downto 0);
+            sram1_lb_n => tb_sram1_lb_n, -- : out   std_logic;
+            sram1_ub_n => tb_sram1_ub_n, -- : out   std_logic;
+            sram1_cs_n => tb_sram1_cs_n, -- : out   std_logic;       -- chip select
+            sram1_we_n => tb_sram1_we_n, -- : out   std_logic;       -- write-enable
+            sram1_oe_n => tb_sram1_oe_n, -- : out   std_logic;       -- output enable
+            --
+            -- RS232
+            rs232_rx   => tb_rs232_rx,   -- : in    std_logic;
+            rs232_tx   => tb_rs232_tx,   -- : out   std_logic;
+            rs232_cts  => tb_rs232_cts,  -- : in    std_logic;
+            rs232_rts  => tb_rs232_rts,  -- : out   std_logic;
+            --
+            -- PS2 connectors
+            mouse_clk  => tb_mouse_clk,  -- : inout std_logic;
+            mouse_data => tb_mouse_data, -- : inout std_logic;
+            kbd_clk    => tb_kbd_clk,    -- : inout std_logic;
+            kbd_data   => tb_kbd_data,   -- : inout std_logic;
+            --
+            -- vga output
+            vga_red    => tb_vga_red,    -- : out   std_logic_vector(7 downto 5);
+            vga_green  => tb_vga_green,  -- : out   std_logic_vector(7 downto 5);
+            vga_blue   => tb_vga_blue,   -- : out   std_logic_vector(7 downto 5);
+            vga_hsync  => tb_vga_hsync,  -- : out   std_logic;
+            vga_vsync  => tb_vga_vsync,  -- : out   std_logic;
+            --
+            -- Audio out
+            audio_r    => tb_audio_r,    -- : out   std_logic;
+            audio_l    => tb_audio_l,    -- : out   std_logic;
+            --
+            -- GPIOs
+            switch_n   => tb_switch_n,   -- : in    std_logic_vector(7 downto 0);
+            button_n   => tb_button_n,   -- : in    std_logic_vector(5 downto 0);
+            led        => tb_led,        -- : out   std_logic_vector(7 downto 0);
+            --
+            -- seven segment display
+            dig0_seg   => tb_dig0_seg,   -- : out   std_logic_vector(7 downto 0);
+            dig1_seg   => tb_dig1_seg,   -- : out   std_logic_vector(7 downto 0);
+            dig2_seg   => tb_dig2_seg,   -- : out   std_logic_vector(7 downto 0);
+            dig3_seg   => tb_dig3_seg,   -- : out   std_logic_vector(7 downto 0);
+            dig4_seg   => tb_dig4_seg,   -- : out   std_logic_vector(7 downto 0);
+            dig5_seg   => tb_dig5_seg,   -- : out   std_logic_vector(7 downto 0);
+            --
+            -- User Header
+            header_a   => tb_header_a,   -- : inout std_logic_vector(19 downto 2);
+            header_b   => tb_header_b    -- : inout std_logic_vector(19 downto 2)
+        );
+
+
+    -- check for simulation stopping
+    process (tb_stop_simulation)
+    begin
+        if tb_stop_simulation = '1' then
+            report "Simulation end." severity note;
+            simulation_run <= false;
+        end if;
+    end process;
+
+
+end architecture testbench;
+
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/clean_up.sh b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/clean_up.sh
new file mode 100755
index 0000000..3855f16
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/clean_up.sh
@@ -0,0 +1,16 @@
+#!/bin/sh
+
+# ise build stuff
+rm -rf build
+rm -f top.bit
+
+# modelsim compile stuff
+rm -rf work
+rm -rf zpu
+
+# modelsim simulation stuff
+rm -f vsim.wlf
+rm -f transcript
+rm -f zpu_trace.log
+rm -f zpu_med1_io.log
+rm -f zpu_small1_io.log
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation.sh b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation.sh
new file mode 100755
index 0000000..d525737
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation.sh
@@ -0,0 +1,49 @@
+#!/bin/sh
+
+# need project files:
+#    run.do
+#    wave.do
+
+# need ModelSim tools:
+#    vlib
+#    vcom
+#    vsim
+
+
+echo "###############"
+echo "compile zpu lib"
+echo "###############"
+vlib zpu
+vcom -work zpu ../../roms/hello_dbram.vhdl
+vcom -work zpu ../../roms/hello_bram.vhdl
+#vcom -work zpu ../../roms/dmips_dbram.vhdl
+#vcom -work zpu ../../roms/dmips_bram.vhdl
+
+vcom -work zpu ../../roms/rom_pkg.vhdl
+vcom -work zpu ../../zpu_pkg.vhdl
+vcom -work zpu ../../zpu_small.vhdl
+vcom -work zpu ../../zpu_medium.vhdl
+vcom -work zpu ../../helpers/zpu_small1.vhdl
+vcom -work zpu ../../helpers/zpu_med1.vhdl
+vcom -work zpu ../../devices/txt_util.vhdl
+vcom -work zpu ../../devices/phi_io.vhdl
+vcom -work zpu ../../devices/timer.vhdl
+vcom -work zpu ../../devices/gpio.vhdl
+vcom -work zpu ../../devices/rx_unit.vhdl
+vcom -work zpu ../../devices/tx_unit.vhdl
+vcom -work zpu ../../devices/br_gen.vhdl
+vcom -work zpu ../../devices/trace.vhdl
+
+
+echo "################"
+echo "compile work lib"
+echo "################"
+vlib work
+vcom top.vhd
+vcom top_tb.vhd
+
+
+echo "###################"
+echo "start simulator gui"
+echo "###################"
+vsim -gui top_tb -do simulation_config/run.do
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/run.do b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/run.do
new file mode 100644
index 0000000..acc1710
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/run.do
@@ -0,0 +1,2 @@
+do wave.do
+run -all
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/wave.do b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/wave.do
new file mode 100644
index 0000000..d572a06
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/wave.do
@@ -0,0 +1,30 @@
+onerror {resume}

+quietly WaveActivateNextPane {} 0

+add wave -noupdate /top_tb/tb_gpio_button(0)

+add wave -noupdate /top_tb/tb_clk_100MHz

+add wave -noupdate -divider <NULL>

+add wave -noupdate /top_tb/tb_rs232_rx

+add wave -noupdate /top_tb/tb_rs232_tx

+add wave -noupdate /top_tb/tb_rs232_rts

+add wave -noupdate /top_tb/tb_rs232_cts

+add wave -noupdate -divider Buttons

+add wave -noupdate /top_tb/tb_gpio_button

+add wave -noupdate -divider LEDs

+add wave -noupdate /top_tb/tb_gpio_led_n

+TreeUpdate [SetDefaultTree]

+WaveRestoreCursors {{Cursor 1} {0 ps} 0}

+configure wave -namecolwidth 150

+configure wave -valuecolwidth 100

+configure wave -justifyvalue left

+configure wave -signalnamewidth 2

+configure wave -snapdistance 10

+configure wave -datasetprefix 0

+configure wave -rowmargin 4

+configure wave -childrowmargin 2

+configure wave -gridoffset 0

+configure wave -gridperiod 1

+configure wave -griddelta 40

+configure wave -timeline 0

+configure wave -timelineunits ns

+update

+WaveRestoreZoom {0 ps} {126912555 ps}

diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis.sh b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis.sh
new file mode 100755
index 0000000..d8d7603
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis.sh
@@ -0,0 +1,36 @@
+#!/bin/sh
+
+# need project files:
+#    top.xst
+#    top.prj
+#    top.ut
+
+# need Xilinx tools:
+#    xst
+#    ngdbuild
+#    map
+#    par
+#    trce
+#    bitgen
+
+echo "########################"
+echo "generate build directory"
+echo "########################"
+mkdir build
+cd build 
+mkdir tmp
+
+echo "###############"
+echo "start processes"
+echo "###############"
+xst      -ifn "../synthesis_config/top.xst" -ofn "top.syr" 
+ngdbuild -dd _ngo -nt timestamp -uc ../synthesis_config/avnet-eval-xc5vfx30t.ucf -p xc5vfx30t-ff665-1 top.ngc top.ngd  
+map      -p xc5vfx30t-ff665-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -ir off -pr off -lc off -power off -o top_map.ncd top.ngd top.pcf 
+par      -w -ol high -mt off top_map.ncd top.ncd top.pcf 
+trce     -v 3 -s 1 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf 
+bitgen   -f ../synthesis_config/top.ut top.ncd 
+
+echo "###########"
+echo "get bitfile"
+echo "###########"
+cp top.bit ..
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/avnet-eval-xc5vfx30t.ucf b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/avnet-eval-xc5vfx30t.ucf
new file mode 100644
index 0000000..8494af3
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/avnet-eval-xc5vfx30t.ucf
@@ -0,0 +1,482 @@
+############################################################
+# Avnet Virtex 5 FX Evaluation Board constraints file
+#
+# Familiy: Virtex5 
+# Device:  XC5VFX30T
+# Package: FF665
+# Speed:   -1
+#
+#
+# Bank 0  3.3V
+# Bank 1  3.3V
+# Bank 2  3.3V
+# Bank 3  3.3V
+# Bank 4  2.5V or 3.3V (JP2, VIO_EXP1_DP), here 2.5V
+# Bank 11 1.8V
+# Bank 12 3.3V
+# Bank 13 1.8V
+# Bank 15 3.3V
+# Bank 16 2.5V or 3.3V (JP3, VIO_EXP1_SE), here 2.5V
+# Bank 17 1.8V
+# Bank 18 2.5V or 3.3V (JP2, VIO_EXP1_DP), here 2.5V
+
+
+############################################################
+## clock/timing constraints
+############################################################
+
+TIMESPEC "TS_clk_100" = PERIOD "clk_100" 100 MHz;
+
+
+############################################################
+## design placement constraints
+############################################################
+#
+# the following constraint are need if you want to synthesize
+# zpu_medium with 125 MHz
+#
+INST "zpu_i0_medium.zpu_i0/zpu/*" AREA_GROUP = "zpu_block";
+AREA_GROUP "zpu_block" RANGE=SLICE_X18Y0:SLICE_X55Y41;
+AREA_GROUP "zpu_block" RANGE=DSP48_X0Y0:DSP48_X0Y15;
+AREA_GROUP "zpu_block" RANGE=RAMB36_X1Y0:RAMB36_X3Y7;
+
+
+############################################################
+## pin placement constraints
+############################################################
+
+NET "clk_100MHz"                         LOC= E18  | IOSTANDARD = LVCMOS33 | TNM_NET = "clk_100";
+NET "clk_socket"                         LOC= E13  | IOSTANDARD = LVCMOS33;
+NET "user_clk_p"                         LOC= AB15 ;
+NET "user_clk_n"                         LOC= AC16 ;
+
+# RS232
+NET "RS232_RX"                           LOC= K8   | IOSTANDARD = LVCMOS33;
+NET "RS232_TX"                           LOC= L8   | IOSTANDARD = LVCMOS33;
+NET "RS232_RTS"                          LOC= N8   | IOSTANDARD = LVCMOS33; # Jumper J3
+NET "RS232_CTS"                          LOC= R8   | IOSTANDARD = LVCMOS33; # Jumper J4
+
+# RS232_USB
+NET "RS232_USB_RX"                       LOC= AA10 | IOSTANDARD = LVCMOS33;
+NET "RS232_USB_TX"                       LOC= AA19 | IOSTANDARD = LVCMOS33;
+NET "RS232_USB_reset_n"                  LOC= Y20  | IOSTANDARD = LVCMOS33;
+
+# GPIO LEDs, active low
+NET "GPIO_LED_n<0>"                      LOC= AF22 | IOSTANDARD = LVCMOS18 | PULLUP;
+NET "GPIO_LED_n<1>"                      LOC= AF23 | IOSTANDARD = LVCMOS18 | PULLUP;
+NET "GPIO_LED_n<2>"                      LOC= AF25 | IOSTANDARD = LVCMOS18 | PULLUP;
+NET "GPIO_LED_n<3>"                      LOC= AE25 | IOSTANDARD = LVCMOS18 | PULLUP;
+NET "GPIO_LED_n<4>"                      LOC= AD25 | IOSTANDARD = LVCMOS18 | PULLUP;
+NET "GPIO_LED_n<5>"                      LOC= AE26 | IOSTANDARD = LVCMOS18 | PULLUP;
+NET "GPIO_LED_n<6>"                      LOC= AD26 | IOSTANDARD = LVCMOS18 | PULLUP;
+NET "GPIO_LED_n<7>"                      LOC= AC26 | IOSTANDARD = LVCMOS18 | PULLUP;
+
+# GPIO DIP_Switches
+NET "GPIO_DIPswitch<0>"                  LOC= AD13 | IOSTANDARD = LVCMOS18;
+NET "GPIO_DIPswitch<1>"                  LOC= AE13 | IOSTANDARD = LVCMOS18;
+NET "GPIO_DIPswitch<2>"                  LOC= AF13 | IOSTANDARD = LVCMOS18;
+NET "GPIO_DIPswitch<3>"                  LOC= AD15 | IOSTANDARD = LVCMOS18;
+NET "GPIO_DIPswitch<4>"                  LOC= AD14 | IOSTANDARD = LVCMOS18;
+NET "GPIO_DIPswitch<5>"                  LOC= AF14 | IOSTANDARD = LVCMOS18;
+NET "GPIO_DIPswitch<6>"                  LOC= AE15 | IOSTANDARD = LVCMOS18;
+NET "GPIO_DIPswitch<7>"                  LOC= AF15 | IOSTANDARD = LVCMOS18;
+
+# Push Buttons
+NET "GPIO_button<0>"                     LOC= AF20 | IOSTANDARD = LVCMOS18 | PULLUP; #PB1
+NET "GPIO_button<1>"                     LOC= AE20 | IOSTANDARD = LVCMOS18 | PULLUP; #PB2
+NET "GPIO_button<2>"                     LOC= AD19 | IOSTANDARD = LVCMOS18 | PULLUP; #PB3
+NET "GPIO_button<3>"                     LOC= AD20 | IOSTANDARD = LVCMOS18 | PULLUP; #PB4
+
+# FLASH_8Mx16
+NET "FLASH_A<31>"                        LOC= Y11  | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<30>"                        LOC= H9   | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<29>"                        LOC= G10  | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<28>"                        LOC= H21  | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<27>"                        LOC= G20  | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<26>"                        LOC= H11  | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<25>"                        LOC= G11  | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<24>"                        LOC= H19  | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<23>"                        LOC= H18  | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<22>"                        LOC= G12  | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<21>"                        LOC= F13  | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<20>"                        LOC= G19  | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<19>"                        LOC= F18  | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<18>"                        LOC= F14  | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<17>"                        LOC= F15  | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<16>"                        LOC= F17  | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<15>"                        LOC= G17  | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<14>"                        LOC= G14  | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<13>"                        LOC= H13  | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<12>"                        LOC= G16  | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<11>"                        LOC= G15  | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<10>"                        LOC= Y18  | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<9>"                         LOC= AA18 | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<8>"                         LOC= Y10  | IOSTANDARD = LVCMOS33;
+NET "FLASH_A<7>"                         LOC= W11  | IOSTANDARD = LVCMOS33;
+NET "FLASH_DQ<0>"                        LOC= AA15 | IOSTANDARD = LVCMOS33;
+NET "FLASH_DQ<1>"                        LOC= Y15  | IOSTANDARD = LVCMOS33;
+NET "FLASH_DQ<2>"                        LOC= W14  | IOSTANDARD = LVCMOS33;
+NET "FLASH_DQ<3>"                        LOC= Y13  | IOSTANDARD = LVCMOS33;
+NET "FLASH_DQ<4>"                        LOC= W16  | IOSTANDARD = LVCMOS33;
+NET "FLASH_DQ<5>"                        LOC= Y16  | IOSTANDARD = LVCMOS33;
+NET "FLASH_DQ<6>"                        LOC= AA14 | IOSTANDARD = LVCMOS33;
+NET "FLASH_DQ<7>"                        LOC= AA13 | IOSTANDARD = LVCMOS33;
+NET "FLASH_DQ<8>"                        LOC= AB12 | IOSTANDARD = LVCMOS25; # with level shifter
+NET "FLASH_DQ<9>"                        LOC= AC11 | IOSTANDARD = LVCMOS25; # with level shifter
+NET "FLASH_DQ<10>"                       LOC= AB20 | IOSTANDARD = LVCMOS25; # with level shifter
+NET "FLASH_DQ<11>"                       LOC= AB21 | IOSTANDARD = LVCMOS25; # with level shifter
+NET "FLASH_DQ<12>"                       LOC= AB11 | IOSTANDARD = LVCMOS25; # with level shifter
+NET "FLASH_DQ<13>"                       LOC= AB10 | IOSTANDARD = LVCMOS25; # with level shifter
+NET "FLASH_DQ<14>"                       LOC= AA20 | IOSTANDARD = LVCMOS25; # with level shifter
+NET "FLASH_DQ<15>"                       LOC= Y21  | IOSTANDARD = LVCMOS25; # with level shifter
+NET "FLASH_WEN"                          LOC= AA17 | IOSTANDARD = LVCMOS33;
+NET "FLASH_OEN<0>"                       LOC= AA12 | IOSTANDARD = LVCMOS33;
+NET "FLASH_CEN<0>"                       LOC= Y12  | IOSTANDARD = LVCMOS33;
+NET "FLASH_rp_n"                         LOC= D13  | IOSTANDARD = LVCMOS33;
+NET "FLASH_byte_n"                       LOC= Y17  | IOSTANDARD = LVCMOS33;
+NET "FLASH_adv_n"                        LOC= F19  | IOSTANDARD = LVCMOS33;
+NET "FLASH_clk"                          LOC= E12  | IOSTANDARD = LVCMOS33;
+NET "FLASH_wait"                         LOC= D16  | IOSTANDARD = LVCMOS33;
+
+# DDR2_SDRAM_16Mx32
+NET "DDR2_ODT<0>"                        LOC= AF24 | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<0>"                          LOC= U25  | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<1>"                          LOC= T25  | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<2>"                          LOC= T24  | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<3>"                          LOC= T23  | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<4>"                          LOC= U24  | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<5>"                          LOC= V24  | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<6>"                          LOC= Y23  | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<7>"                          LOC= W23  | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<8>"                          LOC= AA25 | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<9>"                          LOC= AB26 | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<10>"                         LOC= AB25 | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<11>"                         LOC= AB24 | IOSTANDARD = SSTL18_II;
+NET "DDR2_A<12>"                         LOC= AA23 | IOSTANDARD = SSTL18_II;
+NET "DDR2_BA<0>"                         LOC= U21  | IOSTANDARD = SSTL18_II;
+NET "DDR2_BA<1>"                         LOC= V22  | IOSTANDARD = SSTL18_II;
+NET "DDR2_CAS_N"                         LOC= W24  | IOSTANDARD = SSTL18_II;
+NET "DDR2_CKE"                           LOC= T22  | IOSTANDARD = SSTL18_II;
+NET "DDR2_CS_N"                          LOC= AD24 | IOSTANDARD = SSTL18_II;
+NET "DDR2_RAS_N"                         LOC= Y22  | IOSTANDARD = SSTL18_II;
+NET "DDR2_WE_N"                          LOC= AA22 | IOSTANDARD = SSTL18_II;
+NET "DDR2_DM<0>"                         LOC= U26  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DM<1>"                         LOC= N24  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DM<2>"                         LOC= M24  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DM<3>"                         LOC= M25  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQS_P<0>"                      LOC= W26  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQS_P<1>"                      LOC= L23  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQS_P<2>"                      LOC= K22  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQS_P<3>"                      LOC= J21  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQS_N<0>"                      LOC= W25  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQS_N<1>"                      LOC= L22  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQS_N<2>"                      LOC= K23  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQS_N<3>"                      LOC= K21  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<0>"                         LOC= R22  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<1>"                         LOC= R23  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<2>"                         LOC= P23  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<3>"                         LOC= P24  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<4>"                         LOC= R25  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<5>"                         LOC= P25  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<6>"                         LOC= R26  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<7>"                         LOC= P26  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<8>"                         LOC= M26  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<9>"                         LOC= N26  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<10>"                        LOC= K25  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<11>"                        LOC= L24  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<12>"                        LOC= K26  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<13>"                        LOC= J26  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<14>"                        LOC= J25  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<15>"                        LOC= N21  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<16>"                        LOC= M21  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<17>"                        LOC= J23  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<18>"                        LOC= H23  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<19>"                        LOC= H22  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<20>"                        LOC= G22  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<21>"                        LOC= F22  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<22>"                        LOC= F23  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<23>"                        LOC= E23  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<24>"                        LOC= G24  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<25>"                        LOC= F24  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<26>"                        LOC= G25  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<27>"                        LOC= H26  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<28>"                        LOC= G26  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<29>"                        LOC= F25  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<30>"                        LOC= E25  | IOSTANDARD = SSTL18_II;
+NET "DDR2_DQ<31>"                        LOC= E26  | IOSTANDARD = SSTL18_II;
+NET "DDR2_CK_p<0>"                       LOC= V21  | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_CK_p<1>"                       LOC= N22  | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_CK_n<0>"                       LOC= W21  | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_CK_n<1>"                       LOC= M22  | IOSTANDARD = DIFF_SSTL18_II;
+
+# Ethernet MAC
+NET "GMII_txer"                          LOC= A22  | IOSTANDARD = LVCMOS33;
+NET "GMII_tx_clk"                        LOC= E17  | IOSTANDARD = LVCMOS33 | PERIOD=40000 ps;
+NET "GMII_rx_clk"                        LOC= E20  | IOSTANDARD = LVCMOS33 | PERIOD=40000 ps;
+NET "GMII_gtc_clk"                       LOC= A19  | IOSTANDARD = LVCMOS33;
+NET "GMII_crs"                           LOC= A25  | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET "GMII_dv"                            LOC= C21  | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET "GMII_rx_data<0>"                    LOC= D24  | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET "GMII_rx_data<1>"                    LOC= D23  | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET "GMII_rx_data<2>"                    LOC= D21  | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET "GMII_rx_data<3>"                    LOC= C26  | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET "GMII_rx_data<4>"                    LOC= D20  | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET "GMII_rx_data<5>"                    LOC= C23  | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET "GMII_rx_data<6>"                    LOC= B25  | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET "GMII_rx_data<7>"                    LOC= C22  | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET "GMII_col"                           LOC= A24  | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET "GMII_rx_er"                         LOC= B24  | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
+NET "GMII_tx_en"                         LOC= A23  | IOSTANDARD = LVCMOS33;
+NET "GMII_tx_data<0>"                    LOC= D19  | IOSTANDARD = LVCMOS33;
+NET "GMII_tx_data<1>"                    LOC= C19  | IOSTANDARD = LVCMOS33;
+NET "GMII_tx_data<2>"                    LOC= A20  | IOSTANDARD = LVCMOS33;
+NET "GMII_tx_data<3>"                    LOC= B20  | IOSTANDARD = LVCMOS33;
+NET "GMII_tx_data<4>"                    LOC= B19  | IOSTANDARD = LVCMOS33;
+NET "GMII_tx_data<5>"                    LOC= A15  | IOSTANDARD = LVCMOS33;
+NET "GMII_tx_data<6>"                    LOC= B22  | IOSTANDARD = LVCMOS33;
+NET "GMII_tx_data<7>"                    LOC= B21  | IOSTANDARD = LVCMOS33;
+NET "GBE_rst_n"                          LOC= B26  | IOSTANDARD = LVCMOS33;
+NET "GBE_mdc"                            LOC= D26  | IOSTANDARD = LVCMOS33;
+NET "GBE_mdio"                           LOC= D25  | IOSTANDARD = LVCMOS33;
+NET "GBE_int_n"                          LOC= C24  | IOSTANDARD = LVCMOS33;
+NET "GBE_mclk"                           LOC= F20  | IOSTANDARD = LVCMOS33;
+
+# SysACE CompactFlash
+NET "SAM_CLK"                            LOC= F12  | IOSTANDARD = LVCMOS33;
+NET "SAM_A<0>"                           LOC= Y5   | IOSTANDARD = LVCMOS33;
+NET "SAM_A<1>"                           LOC= V7   | IOSTANDARD = LVCMOS33;
+NET "SAM_A<2>"                           LOC= W6   | IOSTANDARD = LVCMOS33;
+NET "SAM_A<3>"                           LOC= W5   | IOSTANDARD = LVCMOS33;
+NET "SAM_A<4>"                           LOC= K6   | IOSTANDARD = LVCMOS33;
+NET "SAM_A<5>"                           LOC= J5   | IOSTANDARD = LVCMOS33;
+NET "SAM_A<6>"                           LOC= J6   | IOSTANDARD = LVCMOS33;
+NET "SAM_D<0>"                           LOC= F5   | IOSTANDARD = LVCMOS33;
+NET "SAM_D<1>"                           LOC= U7   | IOSTANDARD = LVCMOS33;
+NET "SAM_D<2>"                           LOC= V6   | IOSTANDARD = LVCMOS33;
+NET "SAM_D<3>"                           LOC= U5   | IOSTANDARD = LVCMOS33;
+NET "SAM_D<4>"                           LOC= U6   | IOSTANDARD = LVCMOS33;
+NET "SAM_D<5>"                           LOC= T5   | IOSTANDARD = LVCMOS33;
+NET "SAM_D<6>"                           LOC= T7   | IOSTANDARD = LVCMOS33;
+NET "SAM_D<7>"                           LOC= R6   | IOSTANDARD = LVCMOS33;
+NET "SAM_D<8>"                           LOC= R7   | IOSTANDARD = LVCMOS33;
+NET "SAM_D<9>"                           LOC= R5   | IOSTANDARD = LVCMOS33;
+NET "SAM_D<10>"                          LOC= P6   | IOSTANDARD = LVCMOS33;
+NET "SAM_D<11>"                          LOC= P8   | IOSTANDARD = LVCMOS33;
+NET "SAM_D<12>"                          LOC= N6   | IOSTANDARD = LVCMOS33;
+NET "SAM_D<13>"                          LOC= M7   | IOSTANDARD = LVCMOS33;
+NET "SAM_D<14>"                          LOC= K5   | IOSTANDARD = LVCMOS33;
+NET "SAM_D<15>"                          LOC= L7   | IOSTANDARD = LVCMOS33;
+NET "SAM_CEN"                            LOC= G4   | IOSTANDARD = LVCMOS33;
+NET "SAM_OEN"                            LOC= Y6   | IOSTANDARD = LVCMOS33;
+NET "SAM_WEN"                            LOC= Y4   | IOSTANDARD = LVCMOS33;
+NET "SAM_MPIRQ"                          LOC= H4   | IOSTANDARD = LVCMOS33;
+NET "SAM_BRDY"                           LOC= G5   | IOSTANDARD = LVCMOS33;
+NET "SAM_RESET_n"                        LOC= H6   | IOSTANDARD = LVCMOS33;
+
+# Expansion Header
+NET "EXP1_SE_IO<0>"                      LOC= A8   | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<1>"                      LOC= A12  | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<2>"                      LOC= B10  | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<3>"                      LOC= A10  | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<4>"                      LOC= B9   | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<5>"                      LOC= A9   | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<6>"                      LOC= A5   | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<7>"                      LOC= B11  | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<8>"                      LOC= B6   | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<9>"                      LOC= A7   | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<10>"                     LOC= D8   | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<11>"                     LOC= C9   | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<12>"                     LOC= B7   | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<13>"                     LOC= A4   | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<14>"                     LOC= B5   | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<15>"                     LOC= C8   | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<16>"                     LOC= C7   | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<17>"                     LOC= A3   | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<18>"                     LOC= C6   | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<19>"                     LOC= B4   | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<20>"                     LOC= D6   | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<21>"                     LOC= D9   | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<22>"                     LOC= E8   | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<23>"                     LOC= D5   | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<24>"                     LOC= F7   | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<25>"                     LOC= E7   | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<26>"                     LOC= E5   | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<27>"                     LOC= E6   | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<28>"                     LOC= F8   | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<29>"                     LOC= H7   | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<30>"                     LOC= G7   | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<31>"                     LOC= H8   | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<32>"                     LOC= G9   | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_IO<33>"                     LOC= J8   | IOSTANDARD = LVCMOS25;
+NET "EXP1_DIFF_P<0>"                     LOC= AF9  ;
+NET "EXP1_DIFF_N<0>"                     LOC= AF10 ;
+NET "EXP1_DIFF_P<1>"                     LOC= AF12 ;
+NET "EXP1_DIFF_N<1>"                     LOC= AE12 ;
+NET "EXP1_DIFF_P<2>"                     LOC= AF7  ;
+NET "EXP1_DIFF_N<2>"                     LOC= AF8  ;
+NET "EXP1_DIFF_P<3>"                     LOC= AE11 ;
+NET "EXP1_DIFF_N<3>"                     LOC= AD11 ;
+NET "EXP1_DIFF_P<4>"                     LOC= AF4  ;
+NET "EXP1_DIFF_N<4>"                     LOC= AF3  ;
+NET "EXP1_DIFF_P<5>"                     LOC= AD10 ;
+NET "EXP1_DIFF_N<5>"                     LOC= AE10 ;
+NET "EXP1_DIFF_P<6>"                     LOC= AE8  ;
+NET "EXP1_DIFF_N<6>"                     LOC= AE7  ;
+NET "EXP1_DIFF_P<7>"                     LOC= AC8  ;
+NET "EXP1_DIFF_N<7>"                     LOC= AD8  ;
+NET "EXP1_DIFF_P<8>"                     LOC= AD9  ;
+NET "EXP1_DIFF_N<8>"                     LOC= AC9  ;
+NET "EXP1_DIFF_P<9>"                     LOC= AE6  ;
+NET "EXP1_DIFF_N<9>"                     LOC= AF5  ;
+NET "EXP1_DIFF_P<10>"                    LOC= AB6  ;
+NET "EXP1_DIFF_N<10>"                    LOC= AB7  ;
+NET "EXP1_DIFF_P<11>"                    LOC= AC6  ;
+NET "EXP1_DIFF_N<11>"                    LOC= AD5  ;
+NET "EXP1_DIFF_P<12>"                    LOC= AD6  ;
+NET "EXP1_DIFF_N<12>"                    LOC= AC7  ;
+NET "EXP1_DIFF_P<13>"                    LOC= AE5  ;
+NET "EXP1_DIFF_N<13>"                    LOC= AD4  ;
+NET "EXP1_DIFF_P<14>"                    LOC= AB9  ;
+NET "EXP1_DIFF_N<14>"                    LOC= AA9  ;
+NET "EXP1_DIFF_P<15>"                    LOC= AC12 ;
+NET "EXP1_DIFF_N<15>"                    LOC= AC13 ;
+NET "EXP1_DIFF_P<16>"                    LOC= AA7  ;
+NET "EXP1_DIFF_N<16>"                    LOC= AA8  ;
+NET "EXP1_DIFF_P<17>"                    LOC= AA5  ;
+NET "EXP1_DIFF_N<17>"                    LOC= AB5  ;
+NET "EXP1_DIFF_P<18>"                    LOC= AB19 ;
+NET "EXP1_DIFF_N<18>"                    LOC= AC19 ;
+NET "EXP1_DIFF_P<19>"                    LOC= Y7   ;
+NET "EXP1_DIFF_N<19>"                    LOC= Y8   ;
+NET "EXP1_DIFF_P<20>"                    LOC= W9   ;
+NET "EXP1_DIFF_N<20>"                    LOC= W8   ;
+NET "EXP1_DIFF_P<21>"                    LOC= V8   ;
+NET "EXP1_DIFF_N<21>"                    LOC= V9   ;
+NET "EXP1_SE_CLK_OUT"                    LOC= B12  | IOSTANDARD = LVCMOS25;
+NET "EXP1_SE_CLK_IN"                     LOC= E10  | IOSTANDARD = LVCMOS33;
+NET "EXP1_DIFF_CLK_OUT_P"                LOC= AC18 ;
+NET "EXP1_DIFF_CLK_OUT_N"                LOC= AB17 ;
+NET "EXP1_DIFF_CLK_IN_P"                 LOC= AB14 ;
+NET "EXP1_DIFF_CLK_IN_N"                 LOC= AC14 ;
+#NET "EXP1_RCLK_DIFF_P"                   LOC= AB6  ;
+#NET "EXP1_RCLK_DIFF_N"                   LOC= AB7  ;
+
+# CPU Debug Trace
+NET "ATDD<8>"                            LOC= C16  | IOSTANDARD = LVCMOS33;
+NET "ATDD<9>"                            LOC= A17  | IOSTANDARD = LVCMOS33;
+NET "ATDD<10>"                           LOC= B15  | IOSTANDARD = LVCMOS33;
+NET "ATDD<11>"                           LOC= E15  | IOSTANDARD = LVCMOS33;
+NET "ATDD<12>"                           LOC= A14  | IOSTANDARD = LVCMOS33;
+NET "ATDD<13>"                           LOC= D18  | IOSTANDARD = LVCMOS33;
+NET "ATDD<14>"                           LOC= A13  | IOSTANDARD = LVCMOS33;
+NET "ATDD<15>"                           LOC= C13  | IOSTANDARD = LVCMOS33;
+NET "ATDD<16>"                           LOC= D14  | IOSTANDARD = LVCMOS33;
+NET "ATDD<17>"                           LOC= C17  | IOSTANDARD = LVCMOS33;
+NET "ATDD<18>"                           LOC= E16  | IOSTANDARD = LVCMOS33;
+NET "ATDD<19>"                           LOC= C14  | IOSTANDARD = LVCMOS33;
+NET "TRACE_TS10"                         LOC= B16  | IOSTANDARD = LVCMOS33;
+NET "TRACE_TS20"                         LOC= E21  | IOSTANDARD = LVCMOS33;
+NET "TRACE_TS1E"                         LOC= B14  | IOSTANDARD = LVCMOS33;
+NET "TRACE_TS2E"                         LOC= B17  | IOSTANDARD = LVCMOS33;
+NET "TRACE_TS3"                          LOC= C18  | IOSTANDARD = LVCMOS33;
+NET "TRACE_TS4"                          LOC= G21  | IOSTANDARD = LVCMOS33;
+NET "TRACE_TS5"                          LOC= A18  | IOSTANDARD = LVCMOS33;
+NET "TRACE_TS6"                          LOC= F10  | IOSTANDARD = LVCMOS33;
+NET "TRACE_CLK"                          LOC= D15  | IOSTANDARD = LVCMOS33;
+NET "CPU_HRESET"                         LOC= E11  | IOSTANDARD = LVCMOS33;
+NET "CPU_TDO"                            LOC= K7   | IOSTANDARD = LVCMOS33;
+NET "CPU_TMS"                            LOC= L5   | IOSTANDARD = LVCMOS33;
+NET "CPU_TDI"                            LOC= M6   | IOSTANDARD = LVCMOS33;
+NET "CPU_TRST"                           LOC= N7   | IOSTANDARD = LVCMOS33;
+NET "CPU_TCK"                            LOC= T8   | IOSTANDARD = LVCMOS33;
+NET "CPU_HALT_n"                         LOC= W4   | IOSTANDARD = LVCMOS33;
+
+
+# voltage termination
+CONFIG PROHIBIT = AA24;
+CONFIG PROHIBIT = AE23;
+CONFIG PROHIBIT = AF17;
+CONFIG PROHIBIT = V26;
+CONFIG PROHIBIT = E22;
+CONFIG PROHIBIT = L25;
+
+# unused pins
+CONFIG PROHIBIT = F9;
+CONFIG PROHIBIT = D10;
+CONFIG PROHIBIT = C12;
+CONFIG PROHIBIT = C11;
+CONFIG PROHIBIT = D11;
+CONFIG PROHIBIT = AB16;
+CONFIG PROHIBIT = AB22;
+CONFIG PROHIBIT = AC17;
+CONFIG PROHIBIT = AC21;
+CONFIG PROHIBIT = AE22;
+CONFIG PROHIBIT = AD23;
+CONFIG PROHIBIT = AC24;
+CONFIG PROHIBIT = AC23;
+CONFIG PROHIBIT = AC22;
+CONFIG PROHIBIT = AB22;
+CONFIG PROHIBIT = AE21;
+CONFIG PROHIBIT = AD21;
+CONFIG PROHIBIT = AF19;
+CONFIG PROHIBIT = AF18;
+CONFIG PROHIBIT = AE18;
+CONFIG PROHIBIT = AD18;
+CONFIG PROHIBIT = AE17;
+CONFIG PROHIBIT = AE16;
+CONFIG PROHIBIT = AD16;
+CONFIG PROHIBIT = G6;
+CONFIG PROHIBIT = H24;
+CONFIG PROHIBIT = J24;
+CONFIG PROHIBIT = N23;
+CONFIG PROHIBIT = N15;
+CONFIG PROHIBIT = P14;
+CONFIG PROHIBIT = V23;
+CONFIG PROHIBIT = Y26;
+CONFIG PROHIBIT = Y25;
+CONFIG PROHIBIT = P21;
+CONFIG PROHIBIT = R21;
+CONFIG PROHIBIT = U22;
+
+# grounded pins from gigabit transcievers
+CONFIG PROHIBIT = K4;
+CONFIG PROHIBIT = K3;
+CONFIG PROHIBIT = J1;
+CONFIG PROHIBIT = K1;
+CONFIG PROHIBIT = M1;
+CONFIG PROHIBIT = L1;
+CONFIG PROHIBIT = T3;
+CONFIG PROHIBIT = T4;
+CONFIG PROHIBIT = R1;
+CONFIG PROHIBIT = T1;
+CONFIG PROHIBIT = V1;
+CONFIG PROHIBIT = U1;
+CONFIG PROHIBIT = D3;
+CONFIG PROHIBIT = D4;
+CONFIG PROHIBIT = C1;
+CONFIG PROHIBIT = D1;
+CONFIG PROHIBIT = E1;
+CONFIG PROHIBIT = F1;
+CONFIG PROHIBIT = AB3;
+CONFIG PROHIBIT = AB4;
+CONFIG PROHIBIT = AA1;
+CONFIG PROHIBIT = AB1;
+CONFIG PROHIBIT = AC1;
+CONFIG PROHIBIT = AD1;
+CONFIG PROHIBIT = H2;
+CONFIG PROHIBIT = J2;
+CONFIG PROHIBIT = N2;
+CONFIG PROHIBIT = M2;
+CONFIG PROHIBIT = P2;
+CONFIG PROHIBIT = R2;
+CONFIG PROHIBIT = V2;
+CONFIG PROHIBIT = W2;
+CONFIG PROHIBIT = B2;
+CONFIG PROHIBIT = C2;
+CONFIG PROHIBIT = G2;
+CONFIG PROHIBIT = F2;
+CONFIG PROHIBIT = Y2;
+CONFIG PROHIBIT = AA2;
+CONFIG PROHIBIT = AD2;
+CONFIG PROHIBIT = AE2;
+
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj
new file mode 100644
index 0000000..24120d5
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj
@@ -0,0 +1,19 @@
+vhdl work ../top.vhd
+vhdl zpu ../../../zpu_pkg.vhdl
+vhdl zpu ../../../zpu_small.vhdl
+vhdl zpu ../../../zpu_medium.vhdl
+vhdl zpu ../../../roms/rom_pkg.vhdl
+#vhdl zpu ../../../roms/hello_dbram.vhdl
+#vhdl zpu ../../../roms/hello_bram.vhdl
+vhdl zpu ../../../roms/dmips_dbram.vhdl
+vhdl zpu ../../../roms/dmips_bram.vhdl
+vhdl zpu ../../../helpers/zpu_small1.vhdl
+vhdl zpu ../../../helpers/zpu_med1.vhdl
+vhdl zpu ../../../devices/txt_util.vhdl
+vhdl zpu ../../../devices/phi_io.vhdl
+vhdl zpu ../../../devices/timer.vhdl
+vhdl zpu ../../../devices/gpio.vhdl
+vhdl zpu ../../../devices/rx_unit.vhdl
+vhdl zpu ../../../devices/tx_unit.vhdl
+vhdl zpu ../../../devices/br_gen.vhdl
+vhdl zpu ../../../devices/trace.vhdl
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.ut b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.ut
new file mode 100644
index 0000000..e0159fb
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.ut
@@ -0,0 +1,39 @@
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g ConfigRate:2
+-g CclkPin:PullUp
+-g M0Pin:PullUp
+-g M1Pin:PullUp
+-g M2Pin:PullUp
+-g ProgPin:PullUp
+-g DonePin:PullUp
+-g InitPin:Pullup
+-g CsPin:Pullup
+-g DinPin:Pullup
+-g BusyPin:Pullup
+-g RdWrPin:Pullup
+-g HswapenPin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g ConfigFallback:Enable
+-g SelectMAPAbort:Enable
+-g BPI_page_size:1
+-g OverTempPowerDown:Disable
+-g JTAG_SysMon:Enable
+-g DCIUpdateMode:AsRequired
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Match_cycle:Auto
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
+-g Encrypt:No
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.xst b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.xst
new file mode 100644
index 0000000..7ca54bc
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.xst
@@ -0,0 +1,60 @@
+set -tmpdir "tmp"
+set -xsthdpdir "xst"
+run
+-ifn ../synthesis_config/top.prj
+-ifmt mixed
+-ofn top
+-ofmt NGC
+-p xc5vfx30t-1-ff665
+-top top
+-opt_mode Speed
+-opt_level 1
+-power NO
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-dsp_utilization_ratio 100
+-lc Off
+-reduce_control_sets Off
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract Yes
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-auto_bram_packing NO
+-mux_extract Yes
+-resource_sharing YES
+-async_to_sync NO
+-use_dsp48 Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 32
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd
new file mode 100644
index 0000000..560e685
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd
@@ -0,0 +1,444 @@
+-- top module of
+-- Avnet Virtex 5 FX Evaluation Board
+--
+-- using following external connections:
+-- pushbutton PB1 as reset
+-- LEDs   for output
+-- RS232 (non USB)
+--
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library zpu;
+use zpu.zpupkg.all;                     -- zpu_dbgo_t
+
+library unisim;
+use unisim.vcomponents.ibufds;
+use unisim.vcomponents.dcm_base;
+
+
+entity top is
+    port (
+        -- pragma translate_off 
+        stop_simulation     : out   std_logic;
+        -- pragma translate_on 
+        clk_100MHz          : in    std_logic;  -- 100 MHz clock
+        clk_socket          : in    std_logic;  -- user clock
+        user_clk_p          : in    std_logic;  -- differential user clock
+        user_clk_n          : in    std_logic;  -- differential user clock
+        --                                         
+        --  RS232                                  
+        rs232_rx            : in    std_logic;
+        rs232_tx            : out   std_logic;
+        rs232_rts           : in    std_logic;
+        rs232_cts           : out   std_logic;
+        --  RS232 USB                              
+        rs232_usb_rx        : in    std_logic;
+        rs232_usb_tx        : out   std_logic;
+        rs232_usb_reset_n   : out   std_logic;
+        --
+        gpio_led_n          : out   std_logic_vector(7 downto 0);
+        gpio_dipswitch      : in    std_logic_vector(7 downto 0);
+        gpio_button         : in    std_logic_vector(3 downto 0);
+        --
+        --  FLASH 8Mx16 
+        flash_a             : out   std_logic_vector(31 downto 7);
+        flash_dq            : inout std_logic_vector(15 downto 0);
+        flash_wen           : out   std_logic;
+        flash_oen           : out   std_logic_vector(0 downto 0);
+        flash_cen           : out   std_logic_vector(0 downto 0);
+        flash_rp_n          : out   std_logic;
+        flash_byte_n        : out   std_logic;
+        flash_adv_n         : out   std_logic;
+        flash_clk           : out   std_logic;
+        flash_wait          : in    std_logic;
+        --
+        --  DDR2 SDRAM 16Mx32 
+        ddr2_odt            : in    std_logic_vector(0 downto 0);
+        ddr2_a              : out   std_logic_vector(12 downto 0);
+        ddr2_ba             : out   std_logic_vector(1 downto 0);
+        ddr2_cas_n          : out   std_logic;
+        ddr2_cke            : out   std_logic;
+        ddr2_cs_n           : out   std_logic;
+        ddr2_ras_n          : out   std_logic;
+        ddr2_we_n           : out   std_logic;
+        ddr2_dm             : out   std_logic_vector(3 downto 0);
+        ddr2_dqs_p          : inout std_logic_vector(3 downto 0);
+        ddr2_dqs_n          : inout std_logic_vector(3 downto 0);
+        ddr2_dq             : inout std_logic_vector(31 downto 0);
+        ddr2_ck_p           : in    std_logic_vector(1 downto 0);
+        ddr2_ck_n           : in    std_logic_vector(1 downto 0);
+        --
+        --  Ethernet MAC 
+        gmii_txer           : out   std_logic;
+        gmii_tx_clk         : in    std_logic;  -- 25 MHz
+        gmii_rx_clk         : in    std_logic;  -- 25 MHz
+        gmii_gtc_clk        : out   std_logic;
+        gmii_crs            : in    std_logic;
+        gmii_dv             : in    std_logic;
+        gmii_rx_data        : in    std_logic_vector(7 downto 0);
+        gmii_col            : in    std_logic;
+        gmii_rx_er          : in    std_logic;
+        gmii_tx_en          : out   std_logic;
+        gmii_tx_data        : out   std_logic_vector(7 downto 0);
+        gbe_rst_n           : out   std_logic;
+        gbe_mdc             : out   std_logic;
+        gbe_mdio            : inout std_logic;
+        gbe_int_n           : inout std_logic;
+        gbe_mclk            : in    std_logic;
+        --
+        --  SysACE CompactFlash 
+        sam_clk             : in    std_logic;
+        sam_a               : out   std_logic_vector(6 downto 0);
+        sam_d               : inout std_logic_vector(15 downto 0);
+        sam_cen             : out   std_logic;
+        sam_oen             : out   std_logic;
+        sam_wen             : out   std_logic;
+        sam_mpirq           : in    std_logic;
+        sam_brdy            : in    std_logic;
+        sam_reset_n         : out   std_logic;
+        --
+        --  Expansion Header
+        exp1_se_io          : inout std_logic_vector(33 downto 0);
+        exp1_diff_p         : inout std_logic_vector(21 downto 0);
+        exp1_diff_n         : inout std_logic_vector(21 downto 0);
+        exp1_se_clk_out     : out   std_logic;
+        exp1_se_clk_in      : in    std_logic;
+        exp1_diff_clk_out_p : out   std_logic;
+        exp1_diff_clk_out_n : out   std_logic;
+        exp1_diff_clk_in_p  : in    std_logic;
+        exp1_diff_clk_in_n  : in    std_logic;
+        --
+        -- Debug/Trace
+        atdd                : inout std_logic_vector(19 downto 8);
+        trace_ts10          : inout std_logic;
+        trace_ts20          : inout std_logic;
+        trace_ts1e          : inout std_logic;
+        trace_ts2e          : inout std_logic;
+        trace_ts3           : inout std_logic;
+        trace_ts4           : inout std_logic;
+        trace_ts5           : inout std_logic;
+        trace_ts6           : inout std_logic;
+        trace_clk           : in    std_logic;
+        cpu_hreset          : in    std_logic;
+        cpu_tdo             : out   std_logic;
+        cpu_tms             : in    std_logic;
+        cpu_tdi             : in    std_logic;
+        cpu_trst            : in    std_logic;
+        cpu_tck             : in    std_logic;
+        cpu_halt_n          : in    std_logic
+    );
+end entity top;
+
+
+architecture rtl of top is
+
+    ---------------------------
+    -- type declarations
+    type zpu_type is (zpu_small, zpu_medium);
+
+    ---------------------------
+    -- constant declarations
+    constant zpu_flavour   : zpu_type := zpu_medium;  -- choose your flavour HERE
+    --  modify frequency here
+    constant clk_multiply  : positive := 5;   -- 7 for small, 5 for medium
+    constant clk_divide    : positive := 4;   -- 4 for small, 4 for medium
+    --
+    --
+    constant word_size_c   : natural  := 32;  -- 32 bits data path
+    constant addr_w_c      : natural  := 18;  -- 18 bits address space=256 kB, 128 kB I/O
+    --
+    constant clk_frequency : positive := 100; -- input frequency for correct calculation
+
+    ---------------------------
+    -- component declarations
+    component zpu_small1 is
+        generic (
+            word_size  : natural   := 32;      -- 32 bits data path
+            d_care_val : std_logic := '0';     -- Fill value
+            clk_freq   : positive  := 50;      -- 50 MHz clock
+            brate      : positive  := 115200;  -- RS232 baudrate
+            addr_w     : natural   := 16;      -- 16 bits address space=64 kB, 32 kB I/O
+            bram_w     : natural   := 15       -- 15 bits RAM space=32 kB
+            );
+        port (
+            clk_i      : in  std_logic;        -- CPU clock
+            rst_i      : in  std_logic;        -- Reset
+            break_o    : out std_logic;        -- Break executed
+            dbg_o      : out zpu_dbgo_t;       -- Debug info
+            rs232_tx_o : out std_logic;        -- UART Tx
+            rs232_rx_i : in  std_logic;        -- UART Rx
+            gpio_in    : in  std_logic_vector(31 downto 0);
+            gpio_out   : out std_logic_vector(31 downto 0);
+            gpio_dir   : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
+            );
+    end component zpu_small1;
+
+    component zpu_med1 is
+        generic(
+            word_size  : natural   := 32;      -- 32 bits data path
+            d_care_val : std_logic := '0';     -- Fill value
+            clk_freq   : positive  := 50;      -- 50 MHz clock
+            brate      : positive  := 115200;  -- RS232 baudrate
+            addr_w     : natural   := 18;      -- 18 bits address space=256 kB, 128 kB I/O
+            bram_w     : natural   := 15       -- 15 bits RAM space=32 kB
+            );
+        port(
+            clk_i      : in  std_logic;        -- CPU clock
+            rst_i      : in  std_logic;        -- Reset
+            break_o    : out std_logic;        -- Break executed
+            dbg_o      : out zpu_dbgo_t;       -- Debug info
+            rs232_tx_o : out std_logic;        -- UART Tx
+            rs232_rx_i : in  std_logic;        -- UART Rx
+            gpio_in    : in  std_logic_vector(31 downto 0);
+            gpio_out   : out std_logic_vector(31 downto 0);
+            gpio_dir   : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
+            );
+    end component zpu_med1;
+
+
+
+    ---------------------------
+    -- signal declarations
+    signal sys_clk           : std_ulogic;
+    signal dcm_base_i0_clk0  : std_ulogic;
+    signal dcm_base_i0_clkfx : std_ulogic;
+    signal clk_fb            : std_ulogic;
+    signal clk               : std_ulogic;
+    --
+    signal reset_shift_reg   : std_ulogic_vector(3 downto 0);
+    signal reset_sync        : std_ulogic;
+    --
+    signal zpu_i0_dbg        : zpu_dbgo_t;  -- Debug info
+    signal zpu_i0_break      : std_logic;
+    --
+    signal ibufds_i0_o       : std_ulogic;
+    signal ibufds_i1_o       : std_ulogic;
+    --
+    signal gpio_in           : std_logic_vector(31 downto 0) := (others => '0');
+    signal zpu_i0_gpio_out   : std_logic_vector(31 downto 0);
+    signal zpu_i0_gpio_dir   : std_logic_vector(31 downto 0);
+    
+begin
+  
+    -- default output drivers
+    -- to pass bitgen DRC 
+      -- other used outputs are only commented
+    --rs232_tx            <= '1';
+    rs232_cts           <= '1';
+    rs232_usb_tx        <= '1';
+    rs232_usb_reset_n   <= '1';
+    --
+    --gpio_led_n        <= (others => '1');
+    --
+    flash_cen           <= "1";
+    flash_oen           <= "1";
+    flash_wen           <= '1';
+    flash_rp_n          <= '1';
+    flash_byte_n        <= '1';
+    flash_adv_n         <= '1';
+    flash_clk           <= '0';
+    flash_a             <= (others => '0');
+    flash_dq            <= (others => 'Z');
+    --
+    ddr2_a              <= (others => '0');
+    ddr2_ba             <= (others => '0');
+    ddr2_dm             <= (others => '0');
+    ddr2_cs_n           <= '1';
+    ddr2_we_n           <= '1';
+    ddr2_cke            <= '1';
+    ddr2_cas_n          <= '1';
+    ddr2_ras_n          <= '1';
+    ddr2_dqs_p          <= (others => 'Z');
+    ddr2_dqs_n          <= (others => 'Z');
+    ddr2_dq             <= (others => 'Z');
+    --
+    gmii_gtc_clk        <= '0';
+    gmii_tx_data        <= (others => '0');
+    gmii_tx_en          <= '0';
+    gmii_txer           <= '0';
+    gbe_rst_n           <= '1';
+    gbe_mdc             <= '1';
+    gbe_mdio            <= 'Z';
+    gbe_int_n           <= 'Z';
+    --
+    sam_cen             <= '1';
+    sam_oen             <= '1';
+    sam_wen             <= '1';
+    sam_a               <= (others => '0');
+    sam_d               <= (others => 'Z');
+    sam_reset_n         <= '1';
+    --
+    exp1_se_io          <= (others => 'Z');
+    exp1_diff_p         <= (others => 'Z');
+    exp1_diff_n         <= (others => 'Z');
+    exp1_se_clk_out     <= '0';
+    exp1_diff_clk_out_p <= '0';
+    exp1_diff_clk_out_n <= '1';
+    --
+    atdd                <= (others => 'Z');
+    trace_ts10          <= 'Z';
+    trace_ts20          <= 'Z';
+    trace_ts1e          <= 'Z';
+    trace_ts2e          <= 'Z';
+    trace_ts3           <= 'Z';
+    trace_ts4           <= 'Z';
+    trace_ts5           <= 'Z';
+    trace_ts6           <= 'Z';
+    cpu_tdo             <= '1';
+
+
+    -- global differential input buffer 
+  ibufds_i0 : ibufds
+    generic map (
+      diff_term => true
+      )
+    port map (
+      o  => ibufds_i0_o,
+      i  => ddr2_ck_p(0),
+      ib => ddr2_ck_n(0)
+      );
+
+    -- global differential input buffer 
+  ibufds_i1 : ibufds
+    generic map (
+      diff_term => true
+      )
+    port map (
+      o  => ibufds_i1_o,
+      i  => ddr2_ck_p(1),
+      ib => ddr2_ck_n(1)
+      );
+  
+    -- digital clock manager (DCM)
+    -- to generate higher/other system clock frequencys
+    dcm_base_i0: dcm_base
+    generic map (
+        startup_wait       => true, -- wait with DONE till locked
+        --dfs_frequency_mode => "HIGH", -- use this with zpu_small for 175 MHz
+        clkfx_multiply     => clk_multiply,
+        clkfx_divide       => clk_divide,
+        clk_feedback       => "1X"
+    )
+    port map (
+        rst   => '0',
+        clkin => clk_100MHz,
+        clk0  => dcm_base_i0_clk0,
+        clkfx => dcm_base_i0_clkfx,
+        clkfb => clk_fb
+    );
+          
+    -- speaking names for dcm output
+    clk_fb    <= dcm_base_i0_clk0;
+    clk       <= dcm_base_i0_clkfx;
+
+
+    -- reset synchronizer
+    -- generate synchronous reset
+    reset_synchronizer : process(clk, gpio_button)
+    begin
+        if (gpio_button(0) = '1') then
+            reset_shift_reg <= (others => '1');
+        elsif rising_edge(clk) then
+            reset_shift_reg <= reset_shift_reg(reset_shift_reg'high-1 downto 0) & '0';
+        end if;
+    end process;
+    reset_sync <= reset_shift_reg(reset_shift_reg'high);
+
+
+
+    -- select instance of zpu
+    zpu_i0_small: if zpu_flavour = zpu_small generate
+        zpu_i0 : zpu_small1
+            generic map (
+                addr_w    => addr_w_c,
+                word_size => word_size_c,
+                clk_freq  => clk_frequency * clk_multiply / clk_divide
+                )
+            port map (
+                clk_i      => clk,             -- : in  std_logic;   - CPU clock
+                rst_i      => reset_sync,      -- : in  std_logic;   - Reset
+                break_o    => zpu_i0_break,    -- : out std_logic;   - Break executed
+                dbg_o      => zpu_i0_dbg,      -- : out zpu_dbgo_t;  - Debug info
+                rs232_tx_o => rs232_tx,        -- : out std_logic;   - UART Tx
+                rs232_rx_i => rs232_rx,        -- : in  std_logic    - UART Rx
+                gpio_in    => gpio_in,         -- : in  std_logic_vector(31 downto 0);
+                gpio_out   => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
+                gpio_dir   => zpu_i0_gpio_dir  -- : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
+                );
+    end generate zpu_i0_small;
+
+    zpu_i0_medium: if zpu_flavour = zpu_medium generate
+        zpu_i0 : zpu_med1
+            generic map (
+                addr_w    => addr_w_c,
+                word_size => word_size_c,
+                clk_freq  => clk_frequency * clk_multiply / clk_divide
+                )
+            port map (
+                clk_i      => clk,             -- : in  std_logic;   - CPU clock
+                rst_i      => reset_sync,      -- : in  std_logic;   - Reset
+                break_o    => zpu_i0_break,    -- : out std_logic;   - Break executed
+                dbg_o      => zpu_i0_dbg,      -- : out zpu_dbgo_t;  - Debug info
+                rs232_tx_o => rs232_tx,        -- : out std_logic;   - UART Tx
+                rs232_rx_i => rs232_rx,        -- : in  std_logic    - UART Rx
+                gpio_in    => gpio_in,         -- : in  std_logic_vector(31 downto 0);
+                gpio_out   => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
+                gpio_dir   => zpu_i0_gpio_dir  -- : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
+                );
+    end generate zpu_i0_medium;
+
+    -- pragma translate_off 
+    stop_simulation <= zpu_i0_break; -- abort() causes to stop the simulation
+
+
+    trace_mod : trace
+        generic map (
+            addr_w    => addr_w_c,
+            word_size => word_size_c,
+            log_file  => "zpu_trace.log"
+            )
+        port map (
+            clk_i  => clk,
+            dbg_i  => zpu_i0_dbg,
+            stop_i => zpu_i0_break,
+            busy_i => '0'
+            );
+    -- pragma translate_on
+
+    -- assign GPIOs
+    -- no bidirectional pins (e.g. headers), so
+    -- gpio_dir is unused
+    --
+    -- bit   31 30 29 28 27 26 25 24  23 22 21 20 19 18 17 16
+    --
+    --  in   -- -- -- -- -- -- -- --  -- -- -- -- -- -- -- --
+    -- out   -- -- -- -- -- -- -- --  -- -- -- -- -- -- -- --
+    --
+    --
+    -- bit   15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
+    --                                                       
+    --  in   gpio_dipswitch(7.....0)  -- -- -- --  buttons3.0
+    -- out   -- -- -- -- -- -- -- --  led(7................0)
+    --
+
+    gpio_in(15 downto 8) <= gpio_dipswitch;
+    gpio_in( 3 downto 0) <= gpio_button;
+
+
+    -- switch on all LEDs in case of break
+    process
+    begin
+        wait until rising_edge(clk);
+        gpio_led_n <= not zpu_i0_gpio_out(7 downto 0);
+        if zpu_i0_break = '1' then
+            gpio_led_n <= (others => '0');
+        end if;
+    end process;
+
+
+
+end architecture rtl;
+
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top_tb.vhd b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top_tb.vhd
new file mode 100644
index 0000000..751ce22
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top_tb.vhd
@@ -0,0 +1,271 @@
+-- testbench for
+-- Avnet Virtex 5 FX Evaluation Board
+--
+-- includes "model" for clock generation
+-- simulate press on gpio_button(0) (=PB1) as reset
+--
+-- place models for external components (PHY, DDR2-RAM) in this file
+--
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity top_tb is
+end entity top_tb;
+
+architecture testbench of top_tb is
+
+    ---------------------------
+    -- constant declarations
+    constant clk_100MHz_period  : time := 1 sec / 100_000_000;  -- 100 MHz
+
+
+    ---------------------------
+    -- signal declarations
+    signal simulation_run         : boolean   := true;
+    signal tb_stop_simulation     : std_logic;
+    --
+    signal tb_clk_100MHz          : std_logic := '0';  -- 100 MHz clock
+    signal tb_clk_socket          : std_logic := '0';  -- user clock
+    signal tb_user_clk_p          : std_logic := '0';  -- diff user clock
+    signal tb_user_clk_n          : std_logic := '0';  -- diff user clock
+    --                                         
+    --  RS232                                  
+    signal tb_rs232_rx            : std_logic := '0';
+    signal tb_rs232_tx            : std_logic;
+    signal tb_rs232_rts           : std_logic := '0';
+    signal tb_rs232_cts           : std_logic;
+    --  RS232 USB                              
+    signal tb_rs232_usb_rx        : std_logic := '0';
+    signal tb_rs232_usb_tx        : std_logic;
+    signal tb_rs232_usb_reset_n   : std_logic;
+    --
+    signal tb_gpio_led_n          : std_logic_vector(7 downto 0);
+    signal tb_gpio_dipswitch      : std_logic_vector(7 downto 0) := (others => '0');
+    signal tb_gpio_button         : std_logic_vector(3 downto 0) := (others => '0');
+    --
+    --  FLASH 8Mx16 
+    signal tb_flash_a             : std_logic_vector(31 downto 7);
+    signal tb_flash_dq            : std_logic_vector(15 downto 0);
+    signal tb_flash_wen           : std_logic;
+    signal tb_flash_oen           : std_logic_vector(0 downto 0);
+    signal tb_flash_cen           : std_logic_vector(0 downto 0);
+    signal tb_flash_rp_n          : std_logic;
+    signal tb_flash_byte_n        : std_logic;
+    signal tb_flash_adv_n         : std_logic;
+    signal tb_flash_clk           : std_logic;
+    signal tb_flash_wait          : std_logic := '0';
+    --
+    --  DDR2 SDRAM 16Mx32 
+    signal tb_ddr2_odt            : std_logic_vector(0 downto 0) := (others => '0');
+    signal tb_ddr2_a              : std_logic_vector(12 downto 0);
+    signal tb_ddr2_ba             : std_logic_vector(1 downto 0);
+    signal tb_ddr2_cas_n          : std_logic;
+    signal tb_ddr2_cke            : std_logic;
+    signal tb_ddr2_cs_n           : std_logic;
+    signal tb_ddr2_ras_n          : std_logic;
+    signal tb_ddr2_we_n           : std_logic;
+    signal tb_ddr2_dm             : std_logic_vector(3 downto 0);
+    signal tb_ddr2_dqs_p          : std_logic_vector(3 downto 0);
+    signal tb_ddr2_dqs_n          : std_logic_vector(3 downto 0);
+    signal tb_ddr2_dq             : std_logic_vector(31 downto 0);
+    signal tb_ddr2_ck_p           : std_logic_vector(1 downto 0) := (others => '0');
+    signal tb_ddr2_ck_n           : std_logic_vector(1 downto 0) := (others => '0');
+    --
+    --  Ethernet MAC 
+    signal tb_gmii_txer           : std_logic;
+    signal tb_gmii_tx_clk         : std_logic := '0';  -- 25 MHz
+    signal tb_gmii_rx_clk         : std_logic := '0';  -- 25 MHz
+    signal tb_gmii_gtc_clk        : std_logic;
+    signal tb_gmii_crs            : std_logic := '0';
+    signal tb_gmii_dv             : std_logic := '0';
+    signal tb_gmii_rx_data        : std_logic_vector(7 downto 0);
+    signal tb_gmii_col            : std_logic := '0';
+    signal tb_gmii_rx_er          : std_logic := '0';
+    signal tb_gmii_tx_en          : std_logic;
+    signal tb_gmii_tx_data        : std_logic_vector(7 downto 0);
+    signal tb_gbe_rst_n           : std_logic;
+    signal tb_gbe_mdc             : std_logic;
+    signal tb_gbe_mdio            : std_logic;
+    signal tb_gbe_int_n           : std_logic;
+    signal tb_gbe_mclk            : std_logic := '0';
+    --
+    --  SysACE CompactFlash 
+    signal tb_sam_clk             : std_logic := '0';
+    signal tb_sam_a               : std_logic_vector(6 downto 0);
+    signal tb_sam_d               : std_logic_vector(15 downto 0);
+    signal tb_sam_cen             : std_logic;
+    signal tb_sam_oen             : std_logic;
+    signal tb_sam_wen             : std_logic;
+    signal tb_sam_mpirq           : std_logic := '0';
+    signal tb_sam_brdy            : std_logic := '0';
+    signal tb_sam_reset_n         : std_logic;
+    --
+    --  Expansion Header
+    signal tb_exp1_se_io          : std_logic_vector(33 downto 0);
+    signal tb_exp1_diff_p         : std_logic_vector(21 downto 0);
+    signal tb_exp1_diff_n         : std_logic_vector(21 downto 0);
+    signal tb_exp1_se_clk_out     : std_logic;
+    signal tb_exp1_se_clk_in      : std_logic := '0';
+    signal tb_exp1_diff_clk_out_p : std_logic;
+    signal tb_exp1_diff_clk_out_n : std_logic;
+    signal tb_exp1_diff_clk_in_p  : std_logic := '0';
+    signal tb_exp1_diff_clk_in_n  : std_logic := '0';
+    --
+    -- Debug/Trace
+    signal tb_atdd                : std_logic_vector(19 downto 8);
+    signal tb_trace_ts10          : std_logic;
+    signal tb_trace_ts20          : std_logic;
+    signal tb_trace_ts1e          : std_logic;
+    signal tb_trace_ts2e          : std_logic;
+    signal tb_trace_ts3           : std_logic;
+    signal tb_trace_ts4           : std_logic;
+    signal tb_trace_ts5           : std_logic;
+    signal tb_trace_ts6           : std_logic;
+    signal tb_trace_clk           : std_logic := '0';
+    signal tb_cpu_hreset          : std_logic := '0';
+    signal tb_cpu_tdo             : std_logic;
+    signal tb_cpu_tms             : std_logic := '0';
+    signal tb_cpu_tdi             : std_logic := '0';
+    signal tb_cpu_trst            : std_logic := '0';
+    signal tb_cpu_tck             : std_logic := '0';
+    signal tb_cpu_halt_n          : std_logic := '0';
+
+
+begin
+
+
+    -- generate clocks
+    tb_clk_100MHz <= not tb_clk_100MHz after clk_100MHz_period / 2 when simulation_run;
+
+    -- generate reset
+    tb_gpio_button(0) <= '1', '0' after 6.66 * clk_100MHz_period;
+
+
+    -- simulate keypress
+    tb_gpio_button(2) <= '0', '1' after 55 us, '0' after 56 us;
+
+    -- dut
+    top_i0 : entity work.top
+        port map (
+            stop_simulation => tb_stop_simulation,  -- : out   std_logic;
+            clk_100MHz          => tb_clk_100MHz,           -- : in    std_logic;
+            clk_socket          => tb_clk_socket,           -- : in    std_logic;
+            user_clk_p          => tb_user_clk_p,           -- : in    std_logic;
+            user_clk_n          => tb_user_clk_n,           -- : in    std_logic;
+            --                                         
+            --  RS232                                  
+            rs232_rx            => tb_rs232_rx,             -- : in    std_logic;
+            rs232_tx            => tb_rs232_tx,             -- : out   std_logic;
+            rs232_rts           => tb_rs232_rts,            -- : in    std_logic;
+            rs232_cts           => tb_rs232_cts,            -- : out   std_logic;
+            --  RS232 USB                              
+            rs232_usb_rx        => tb_rs232_usb_rx,         -- : in    std_logic;
+            rs232_usb_tx        => tb_rs232_usb_tx,         -- : out   std_logic;
+            rs232_usb_reset_n   => tb_rs232_usb_reset_n,    -- : out   std_logic;
+            --                                              
+            gpio_led_n          => tb_gpio_led_n,           -- : out   std_logic_vector(7 downto 0);
+            gpio_dipswitch      => tb_gpio_dipswitch,       -- : in    std_logic_vector(7 downto 0);
+            gpio_button         => tb_gpio_button,          -- : in    std_logic_vector(3 downto 0);
+            --
+            --  FLASH 8Mx16 
+            flash_a             => tb_flash_a,              -- : out   std_logic_vector(31 downto 7);
+            flash_dq            => tb_flash_dq,             -- : inout std_logic_vector(15 downto 0);
+            flash_wen           => tb_flash_wen,            -- : out   std_logic;
+            flash_oen           => tb_flash_oen,            -- : out   std_logic_vector(0 downto 0);
+            flash_cen           => tb_flash_cen,            -- : out   std_logic_vector(0 downto 0);
+            flash_rp_n          => tb_flash_rp_n,           -- : out   std_logic;
+            flash_byte_n        => tb_flash_byte_n,         -- : out   std_logic;
+            flash_adv_n         => tb_flash_adv_n,          -- : out   std_logic;
+            flash_clk           => tb_flash_clk,            -- : out   std_logic;
+            flash_wait          => tb_flash_wait,           -- : in    std_logic;
+            --
+            --  DDR2 SDRAM 16Mx32 
+            ddr2_odt            => tb_ddr2_odt,             -- : in    std_logic_vector(0 downto 0);
+            ddr2_a              => tb_ddr2_a,               -- : out   std_logic_vector(12 downto 0);
+            ddr2_ba             => tb_ddr2_ba,              -- : out   std_logic_vector(1 downto 0);
+            ddr2_cas_n          => tb_ddr2_cas_n,           -- : out   std_logic;
+            ddr2_cke            => tb_ddr2_cke,             -- : out   std_logic;
+            ddr2_cs_n           => tb_ddr2_cs_n,            -- : out   std_logic;
+            ddr2_ras_n          => tb_ddr2_ras_n,           -- : out   std_logic;
+            ddr2_we_n           => tb_ddr2_we_n,            -- : out   std_logic;
+            ddr2_dm             => tb_ddr2_dm,              -- : out   std_logic_vector(3 downto 0);
+            ddr2_dqs_p          => tb_ddr2_dqs_p,           -- : inout std_logic_vector(3 downto 0);
+            ddr2_dqs_n          => tb_ddr2_dqs_n,           -- : inout std_logic_vector(3 downto 0);
+            ddr2_dq             => tb_ddr2_dq,              -- : inout std_logic_vector(31 downto 0);
+            ddr2_ck_p           => tb_ddr2_ck_p,            -- : in    std_logic_vector(1 downto 0);
+            ddr2_ck_n           => tb_ddr2_ck_n,            -- : in    std_logic_vector(1 downto 0);
+            --
+            --  Ethernet MAC 
+            gmii_txer           => tb_gmii_txer,            -- : out   std_logic;
+            gmii_tx_clk         => tb_gmii_tx_clk,          -- : in    std_logic;
+            gmii_rx_clk         => tb_gmii_rx_clk,          -- : in    std_logic;
+            gmii_gtc_clk        => tb_gmii_gtc_clk,         -- : out   std_logic;
+            gmii_crs            => tb_gmii_crs,             -- : in    std_logic;
+            gmii_dv             => tb_gmii_dv,              -- : in    std_logic;
+            gmii_rx_data        => tb_gmii_rx_data,         -- : in    std_logic_vector(7 downto 0);
+            gmii_col            => tb_gmii_col,             -- : in    std_logic;
+            gmii_rx_er          => tb_gmii_rx_er,           -- : in    std_logic;
+            gmii_tx_en          => tb_gmii_tx_en,           -- : out   std_logic;
+            gmii_tx_data        => tb_gmii_tx_data,         -- : out   std_logic_vector(7 downto 0);
+            gbe_rst_n           => tb_gbe_rst_n,            -- : out   std_logic;
+            gbe_mdc             => tb_gbe_mdc,              -- : out   std_logic;
+            gbe_mdio            => tb_gbe_mdio,             -- : inout std_logic;
+            gbe_int_n           => tb_gbe_int_n,            -- : inout std_logic;
+            gbe_mclk            => tb_gbe_mclk,             -- : in    std_logic;
+            --
+            --  SysACE CompactFlash 
+            sam_clk             => tb_sam_clk,              -- : in    std_logic;
+            sam_a               => tb_sam_a,                -- : out   std_logic_vector(6 downto 0);
+            sam_d               => tb_sam_d,                -- : inout std_logic_vector(15 downto 0);
+            sam_cen             => tb_sam_cen,              -- : out   std_logic;
+            sam_oen             => tb_sam_oen,              -- : out   std_logic;
+            sam_wen             => tb_sam_wen,              -- : out   std_logic;
+            sam_mpirq           => tb_sam_mpirq,            -- : in    std_logic;
+            sam_brdy            => tb_sam_brdy,             -- : in    std_logic;
+            sam_reset_n         => tb_sam_reset_n,          -- : out   std_logic;
+            --
+            --  Expansion Header
+            exp1_se_io          => tb_exp1_se_io,           -- : inout std_logic_vector(33 downto 0);
+            exp1_diff_p         => tb_exp1_diff_p,          -- : inout std_logic_vector(21 downto 0);
+            exp1_diff_n         => tb_exp1_diff_n,          -- : inout std_logic_vector(21 downto 0);
+            exp1_se_clk_out     => tb_exp1_se_clk_out,      -- : out   std_logic;
+            exp1_se_clk_in      => tb_exp1_se_clk_in,       -- : in    std_logic;
+            exp1_diff_clk_out_p => tb_exp1_diff_clk_out_p,  -- : out   std_logic;
+            exp1_diff_clk_out_n => tb_exp1_diff_clk_out_n,  -- : out   std_logic;
+            exp1_diff_clk_in_p  => tb_exp1_diff_clk_in_p,   -- : in    std_logic;
+            exp1_diff_clk_in_n  => tb_exp1_diff_clk_in_n,   -- : in    std_logic;
+            --
+            -- Debug/Trace
+            atdd                => tb_atdd,                 -- : inout std_logic_vector(19 downto 8);
+            trace_ts10          => tb_trace_ts10,           -- : inout std_logic;
+            trace_ts20          => tb_trace_ts20,           -- : inout std_logic;
+            trace_ts1e          => tb_trace_ts1e,           -- : inout std_logic;
+            trace_ts2e          => tb_trace_ts2e,           -- : inout std_logic;
+            trace_ts3           => tb_trace_ts3,            -- : inout std_logic;
+            trace_ts4           => tb_trace_ts4,            -- : inout std_logic;
+            trace_ts5           => tb_trace_ts5,            -- : inout std_logic;
+            trace_ts6           => tb_trace_ts6,            -- : inout std_logic;
+            trace_clk           => tb_trace_clk,            -- : in    std_logic;
+            cpu_hreset          => tb_cpu_hreset,           -- : in    std_logic;
+            cpu_tdo             => tb_cpu_tdo,              -- : out   std_logic;
+            cpu_tms             => tb_cpu_tms,              -- : in    std_logic;
+            cpu_tdi             => tb_cpu_tdi,              -- : in    std_logic;
+            cpu_trst            => tb_cpu_trst,             -- : in    std_logic;
+            cpu_tck             => tb_cpu_tck,              -- : in    std_logic;
+            cpu_halt_n          => tb_cpu_halt_n            -- : in    std_logic
+    );
+
+
+    -- check for simulation stopping
+    process (tb_stop_simulation)
+    begin
+        if tb_stop_simulation = '1' then
+            report "Simulation end." severity note;
+            simulation_run <= false;
+        end if;
+    end process;
+
+end architecture testbench;
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/clean_up.sh b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/clean_up.sh
new file mode 100755
index 0000000..3855f16
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/clean_up.sh
@@ -0,0 +1,16 @@
+#!/bin/sh
+
+# ise build stuff
+rm -rf build
+rm -f top.bit
+
+# modelsim compile stuff
+rm -rf work
+rm -rf zpu
+
+# modelsim simulation stuff
+rm -f vsim.wlf
+rm -f transcript
+rm -f zpu_trace.log
+rm -f zpu_med1_io.log
+rm -f zpu_small1_io.log
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation.sh b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation.sh
new file mode 100755
index 0000000..d525737
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation.sh
@@ -0,0 +1,49 @@
+#!/bin/sh
+
+# need project files:
+#    run.do
+#    wave.do
+
+# need ModelSim tools:
+#    vlib
+#    vcom
+#    vsim
+
+
+echo "###############"
+echo "compile zpu lib"
+echo "###############"
+vlib zpu
+vcom -work zpu ../../roms/hello_dbram.vhdl
+vcom -work zpu ../../roms/hello_bram.vhdl
+#vcom -work zpu ../../roms/dmips_dbram.vhdl
+#vcom -work zpu ../../roms/dmips_bram.vhdl
+
+vcom -work zpu ../../roms/rom_pkg.vhdl
+vcom -work zpu ../../zpu_pkg.vhdl
+vcom -work zpu ../../zpu_small.vhdl
+vcom -work zpu ../../zpu_medium.vhdl
+vcom -work zpu ../../helpers/zpu_small1.vhdl
+vcom -work zpu ../../helpers/zpu_med1.vhdl
+vcom -work zpu ../../devices/txt_util.vhdl
+vcom -work zpu ../../devices/phi_io.vhdl
+vcom -work zpu ../../devices/timer.vhdl
+vcom -work zpu ../../devices/gpio.vhdl
+vcom -work zpu ../../devices/rx_unit.vhdl
+vcom -work zpu ../../devices/tx_unit.vhdl
+vcom -work zpu ../../devices/br_gen.vhdl
+vcom -work zpu ../../devices/trace.vhdl
+
+
+echo "################"
+echo "compile work lib"
+echo "################"
+vlib work
+vcom top.vhd
+vcom top_tb.vhd
+
+
+echo "###################"
+echo "start simulator gui"
+echo "###################"
+vsim -gui top_tb -do simulation_config/run.do
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/run.do b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/run.do
new file mode 100644
index 0000000..0d29e0a
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/run.do
@@ -0,0 +1,2 @@
+do wave.do

+run -all

diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/wave.do b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/wave.do
new file mode 100644
index 0000000..12582ce
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/wave.do
@@ -0,0 +1,30 @@
+onerror {resume}

+quietly WaveActivateNextPane {} 0

+add wave -noupdate /top_tb/tb_rot_center

+add wave -noupdate /top_tb/tb_clk_50mhz

+add wave -noupdate /top_tb/tb_rs232_dce_rxd

+add wave -noupdate /top_tb/tb_rs232_dce_txd

+add wave -noupdate -divider Buttons

+add wave -noupdate /top_tb/tb_btn_east

+add wave -noupdate /top_tb/tb_btn_north

+add wave -noupdate /top_tb/tb_btn_south

+add wave -noupdate /top_tb/tb_btn_west

+add wave -noupdate -divider LEDs

+add wave -noupdate /top_tb/top_i0/led

+TreeUpdate [SetDefaultTree]

+WaveRestoreCursors {{Cursor 1} {56714893 ps} 0}

+configure wave -namecolwidth 150

+configure wave -valuecolwidth 100

+configure wave -justifyvalue left

+configure wave -signalnamewidth 2

+configure wave -snapdistance 10

+configure wave -datasetprefix 0

+configure wave -rowmargin 4

+configure wave -childrowmargin 2

+configure wave -gridoffset 0

+configure wave -gridperiod 1

+configure wave -griddelta 40

+configure wave -timeline 0

+configure wave -timelineunits ns

+update

+WaveRestoreZoom {0 ps} {151772250 ps}

diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis.sh b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis.sh
new file mode 100755
index 0000000..66622ea
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis.sh
@@ -0,0 +1,36 @@
+#!/bin/sh
+
+# need project files:
+#    top.xst
+#    top.prj
+#    top.ut
+
+# need Xilinx tools:
+#    xst
+#    ngdbuild
+#    map
+#    par
+#    trce
+#    bitgen
+
+echo "########################"
+echo "generate build directory"
+echo "########################"
+mkdir build
+cd build 
+mkdir tmp
+
+echo "###############"
+echo "start processes"
+echo "###############"
+xst      -ifn "../synthesis_config/top.xst" -ofn "top.syr" 
+ngdbuild -dd _ngo -nt timestamp -uc ../synthesis_config/digilent-starter-xc3s500e.ucf -p xc3s500e-fg320-4 top.ngc top.ngd  
+map      -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o top_map.ncd top.ngd top.pcf 
+par      -w -ol high -t 1 top_map.ncd top.ncd top.pcf 
+trce     -v 3 -s 4 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf 
+bitgen   -f ../synthesis_config/top.ut top.ncd 
+
+echo "###########"
+echo "get bitfile"
+echo "###########"
+cp top.bit ..
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/digilent-starter-xc3s500e.ucf b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/digilent-starter-xc3s500e.ucf
new file mode 100644
index 0000000..1007d00
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/digilent-starter-xc3s500e.ucf
@@ -0,0 +1,356 @@
+#####################################################

+# SPARTAN-3E Starter Kit Board Constraints File

+#

+# Family:  Spartan3E

+# Device:  XC3S500E

+# Package: FG320

+# Speed:   -4

+

+

+############################################################

+## clock/timing constraints

+############################################################

+

+# Define clock period for 50 MHz oscillator (40%/60% duty-cycle)

+TIMESPEC "TS_CLK_50MHZ" = PERIOD "CLK_50MHZ" 50.0 MHz HIGH 40%;

+

+# ethernet clock

+TIMESPEC "TS_E_CLK" = PERIOD "E_CLK" 25.0 MHz HIGH 50% ;

+# need because misplaced ethernet clock lines

+NET "E_RX_CLK" CLOCK_DEDICATED_ROUTE = FALSE ;

+NET "E_TX_CLK" CLOCK_DEDICATED_ROUTE = FALSE ;

+

+############################################################

+## pin placement constraints

+############################################################

+

+# Analog-to-Digital Converter (ADC) 

+# some connections shared with SPI Flash, DAC, ADC, and AMP

+NET "AD_CONV"     LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;

+

+# Programmable Gain Amplifier (AMP) 

+# some connections shared with SPI Flash, DAC, ADC, and AMP

+NET "AMP_CS"      LOC = "N7"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;

+NET "AMP_DOUT"    LOC = "E18" | IOSTANDARD = LVCMOS33 ;

+NET "AMP_SHDN"    LOC = "P7"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;

+

+# Pushbuttons (BTN) 

+NET "BTN_EAST"    LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN | TIG;

+NET "BTN_NORTH"   LOC = "V4"  | IOSTANDARD = LVTTL | PULLDOWN | TIG;

+NET "BTN_SOUTH"   LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN | TIG;

+NET "BTN_WEST"    LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN | TIG;

+

+#  Clock inputs (CLK) 

+NET "CLK_50MHZ"   LOC = "C9"  | IOSTANDARD = LVCMOS33 | TNM_NET = "CLK_50MHZ";

+NET "CLK_AUX"     LOC = "B8"  | IOSTANDARD = LVCMOS33 ;

+NET "CLK_SMA"     LOC = "A10" | IOSTANDARD = LVCMOS33 ;

+

+# Digital-to-Analog Converter (DAC) 

+# some connections shared with SPI Flash, DAC, ADC, and AMP

+NET "DAC_CLR"     LOC = "P8"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

+NET "DAC_CS"      LOC = "N8"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

+

+# 1-Wire Secure EEPROM (DS)

+NET "DS_WIRE"     LOC = "U4"  | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

+

+# Ethernet PHY (E) 

+NET "E_COL"       LOC = "U6"  | IOSTANDARD = LVCMOS33 ;

+NET "E_CRS"       LOC = "U13" | IOSTANDARD = LVCMOS33 ;

+NET "E_MDC"       LOC = "P9"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

+NET "E_MDIO"      LOC = "U5"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

+NET "E_RX_CLK"    LOC = "V3"  | IOSTANDARD = LVCMOS33 | TNM_NET = "E_CLK";

+NET "E_RX_DV"     LOC = "V2"  | IOSTANDARD = LVCMOS33 ;

+NET "E_RXD<0>"    LOC = "V8"  | IOSTANDARD = LVCMOS33 ;

+NET "E_RXD<1>"    LOC = "T11" | IOSTANDARD = LVCMOS33 ;

+NET "E_RXD<2>"    LOC = "U11" | IOSTANDARD = LVCMOS33 ;

+NET "E_RXD<3>"    LOC = "V14" | IOSTANDARD = LVCMOS33 ;

+NET "E_RX_ER"     LOC = "U14" | IOSTANDARD = LVCMOS33 ;

+NET "E_TX_CLK"    LOC = "T7"  | IOSTANDARD = LVCMOS33 | TNM_NET = "E_CLK";

+NET "E_TX_EN"     LOC = "P15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

+NET "E_TXD<0>"    LOC = "R11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

+NET "E_TXD<1>"    LOC = "T15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

+NET "E_TXD<2>"    LOC = "R5"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

+NET "E_TXD<3>"    LOC = "T5"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

+NET "E_TX_ER"     LOC = "R6"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

+

+# FPGA Configuration Mode, INIT_B Pins (FPGA) 

+NET "FPGA_M0"     LOC = "M10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

+NET "FPGA_M1"     LOC = "V11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

+NET "FPGA_M2"     LOC = "T10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

+NET "FPGA_INIT_B" LOC = "T3"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;

+NET "FPGA_RDWR_B" LOC = "U10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;

+NET "FPGA_HSWAP"  LOC = "B3"  | IOSTANDARD = LVCMOS33 ;

+

+# FX2 Connector (FX2) 

+NET "FX2_CLKIN"  LOC = "E10" | IOSTANDARD = LVCMOS33 ;

+NET "FX2_CLKIO"  LOC = "D9"  | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+NET "FX2_CLKOUT" LOC = "D10" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+

+# These four connections are shared with the J1 6-pin accessory header

+NET "FX2_IO<1>"  LOC = "B4"  | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+NET "FX2_IO<2>"  LOC = "A4"  | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+NET "FX2_IO<3>"  LOC = "D5"  | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+NET "FX2_IO<4>"  LOC = "C5"  | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+

+# These four connections are shared with the J2 6-pin accessory header

+NET "FX2_IO<5>"  LOC = "A6"  | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+NET "FX2_IO<6>"  LOC = "B6"  | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+NET "FX2_IO<7>"  LOC = "E7"  | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+NET "FX2_IO<8>"  LOC = "F7"  | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+

+# These four connections are shared with the J4 6-pin accessory header

+NET "FX2_IO<9>"  LOC = "D7"  | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+NET "FX2_IO<10>" LOC = "C7"  | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+NET "FX2_IO<11>" LOC = "F8"  | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+NET "FX2_IO<12>" LOC = "E8"  | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+

+# The discrete LEDs are shared with the following 8 FX2 connections

+NET "FX2_IO<13>" LOC = "F9"  | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+NET "FX2_IO<14>" LOC = "E9"  | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+NET "FX2_IO<15>" LOC = "D11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+NET "FX2_IO<16>" LOC = "C11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+NET "FX2_IO<17>" LOC = "F11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+NET "FX2_IO<18>" LOC = "E11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+NET "FX2_IO<19>" LOC = "E12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+NET "FX2_IO<20>" LOC = "F12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+

+NET "FX2_IO<21>" LOC = "A13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+NET "FX2_IO<22>" LOC = "B13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+NET "FX2_IO<23>" LOC = "A14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+NET "FX2_IO<24>" LOC = "B14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+NET "FX2_IO<25>" LOC = "C14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+NET "FX2_IO<26>" LOC = "D14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+NET "FX2_IO<27>" LOC = "A16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+NET "FX2_IO<28>" LOC = "B16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+NET "FX2_IO<29>" LOC = "E13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+NET "FX2_IO<30>" LOC = "C4"  | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+NET "FX2_IO<31>" LOC = "B11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+NET "FX2_IO<32>" LOC = "A11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+NET "FX2_IO<33>" LOC = "A8"  | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+NET "FX2_IO<34>" LOC = "G9"  | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+#

+NET "FX2_IO<35>" LOC = "D12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+NET "FX2_IO<36>" LOC = "C12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+NET "FX2_IO<37>" LOC = "A15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+NET "FX2_IO<38>" LOC = "B15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+#

+NET "FX2_IO<39>" LOC = "C3"  | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+NET "FX2_IO<40>" LOC = "C15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;

+

+#  6-pin header J1 

+# These are shared connections with the FX2 connector

+#NET "J1<0>" LOC = "B4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;

+#NET "J1<1>" LOC = "A4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;

+#NET "J1<2>" LOC = "D5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;

+#NET "J1<3>" LOC = "C5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;

+

+#  6-pin header J2 

+# These are shared connections with the FX2 connector

+#NET "J2<0>" LOC = "A6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;

+#NET "J2<1>" LOC = "B6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;

+#NET "J2<2>" LOC = "E7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;

+#NET "J2<3>" LOC = "F7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;

+

+#  6-pin header J4 

+# These are shared connections with the FX2 connector

+#NET "J4<0>" LOC = "D7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;

+#NET "J4<1>" LOC = "C7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;

+#NET "J4<2>" LOC = "F8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;

+#NET "J4<3>" LOC = "E8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;

+

+#  Character LCD (LCD) 

+NET "LCD_E"     LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "LCD_RS"    LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "LCD_RW"    LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+

+# LCD data connections are shared with StrataFlash connections SF_D<11:8>

+#NET "SF_D<8>"  LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+#NET "SF_D<9>"  LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+#NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+#NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+

+# Discrete LEDs (LED) 

+# These are shared connections with the FX2 connector

+#NET "LED<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

+#NET "LED<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

+#NET "LED<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

+#NET "LED<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

+#NET "LED<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

+#NET "LED<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

+#NET "LED<6>" LOC = "E9"  | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

+#NET "LED<7>" LOC = "F9"  | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

+

+# PS/2 Mouse/Keyboard Port (PS2) 

+NET "PS2_CLK"           LOC = "G14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW | TIG;

+NET "PS2_DATA"          LOC = "G13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW | TIG;

+

+# Rotary Pushbutton Switch (ROT) 

+NET "ROT_A"             LOC = "K18" | IOSTANDARD = LVTTL | PULLUP | TIG;

+NET "ROT_B"             LOC = "G18" | IOSTANDARD = LVTTL | PULLUP | TIG;

+NET "ROT_CENTER"        LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN | TIG;

+

+# RS-232 Serial Ports (RS232) 

+NET "RS232_DCE_RXD"     LOC = "R7"  | IOSTANDARD = LVTTL | TIG;

+NET "RS232_DCE_TXD"     LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW | TIG;

+NET "RS232_DTE_RXD"     LOC = "U8"  | IOSTANDARD = LVTTL | TIG;

+NET "RS232_DTE_TXD"     LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW | TIG;

+

+# DDR SDRAM (SD)  (I/O Bank 3, VCCO=2.5V)

+NET "SD_A<0>"           LOC = "T1"  | IOSTANDARD = SSTL2_I ;

+NET "SD_A<1>"           LOC = "R3"  | IOSTANDARD = SSTL2_I ;

+NET "SD_A<2>"           LOC = "R2"  | IOSTANDARD = SSTL2_I ;

+NET "SD_A<3>"           LOC = "P1"  | IOSTANDARD = SSTL2_I ;

+NET "SD_A<4>"           LOC = "F4"  | IOSTANDARD = SSTL2_I ;

+NET "SD_A<5>"           LOC = "H4"  | IOSTANDARD = SSTL2_I ;

+NET "SD_A<6>"           LOC = "H3"  | IOSTANDARD = SSTL2_I ;

+NET "SD_A<7>"           LOC = "H1"  | IOSTANDARD = SSTL2_I ;

+NET "SD_A<8>"           LOC = "H2"  | IOSTANDARD = SSTL2_I ;

+NET "SD_A<9>"           LOC = "N4"  | IOSTANDARD = SSTL2_I ;

+NET "SD_A<10>"          LOC = "T2"  | IOSTANDARD = SSTL2_I ;

+NET "SD_A<11>"          LOC = "N5"  | IOSTANDARD = SSTL2_I ;

+NET "SD_A<12>"          LOC = "P2"  | IOSTANDARD = SSTL2_I ;

+NET "SD_BA<0>"          LOC = "K5"  | IOSTANDARD = SSTL2_I ;

+NET "SD_BA<1>"          LOC = "K6"  | IOSTANDARD = SSTL2_I ;

+NET "SD_CAS"            LOC = "C2"  | IOSTANDARD = SSTL2_I ;

+NET "SD_CK_N"           LOC = "J4"  | IOSTANDARD = SSTL2_I ; #DIFF_SSTL2_I ;

+NET "SD_CK_P"           LOC = "J5"  | IOSTANDARD = SSTL2_I ; #DIFF_SSTL2_I ;

+NET "SD_CKE"            LOC = "K3"  | IOSTANDARD = SSTL2_I ;

+NET "SD_CS"             LOC = "K4"  | IOSTANDARD = SSTL2_I ;

+NET "SD_DQ<0>"          LOC = "L2"  | IOSTANDARD = SSTL2_I | PULLUP ;

+NET "SD_DQ<1>"          LOC = "L1"  | IOSTANDARD = SSTL2_I | PULLUP ;

+NET "SD_DQ<2>"          LOC = "L3"  | IOSTANDARD = SSTL2_I | PULLUP ;

+NET "SD_DQ<3>"          LOC = "L4"  | IOSTANDARD = SSTL2_I | PULLUP ;

+NET "SD_DQ<4>"          LOC = "M3"  | IOSTANDARD = SSTL2_I | PULLUP ;

+NET "SD_DQ<5>"          LOC = "M4"  | IOSTANDARD = SSTL2_I | PULLUP ;

+NET "SD_DQ<6>"          LOC = "M5"  | IOSTANDARD = SSTL2_I | PULLUP ;

+NET "SD_DQ<7>"          LOC = "M6"  | IOSTANDARD = SSTL2_I | PULLUP ;

+NET "SD_DQ<8>"          LOC = "E2"  | IOSTANDARD = SSTL2_I | PULLUP ;

+NET "SD_DQ<9>"          LOC = "E1"  | IOSTANDARD = SSTL2_I | PULLUP ;

+NET "SD_DQ<10>"         LOC = "F1"  | IOSTANDARD = SSTL2_I | PULLUP ;

+NET "SD_DQ<11>"         LOC = "F2"  | IOSTANDARD = SSTL2_I | PULLUP ;

+NET "SD_DQ<12>"         LOC = "G6"  | IOSTANDARD = SSTL2_I | PULLUP ;

+NET "SD_DQ<13>"         LOC = "G5"  | IOSTANDARD = SSTL2_I | PULLUP ;

+NET "SD_DQ<14>"         LOC = "H6"  | IOSTANDARD = SSTL2_I | PULLUP ;

+NET "SD_DQ<15>"         LOC = "H5"  | IOSTANDARD = SSTL2_I | PULLUP ;

+NET "SD_LDM"            LOC = "J2"  | IOSTANDARD = SSTL2_I ;

+NET "SD_UDM"            LOC = "J1"  | IOSTANDARD = SSTL2_I ;

+NET "SD_RAS"            LOC = "C1"  | IOSTANDARD = SSTL2_I ;

+NET "SD_LDQS"           LOC = "L6"  | IOSTANDARD = SSTL2_I | PULLUP ;

+NET "SD_UDQS"           LOC = "G3"  | IOSTANDARD = SSTL2_I | PULLUP ;

+NET "SD_WE"             LOC = "D1"  | IOSTANDARD = SSTL2_I ;

+# Path to allow connection to top DCM connection

+NET "SD_CK_FB"          LOC = "B9"  | IOSTANDARD = LVCMOS33 ;

+

+# Prohibit VREF pins

+CONFIG                  PROHIBIT = D2;

+CONFIG                  PROHIBIT = G4;

+CONFIG                  PROHIBIT = J6;

+CONFIG                  PROHIBIT = L5;

+CONFIG                  PROHIBIT = R4;

+

+# Intel StrataFlash Parallel NOR Flash (SF) 

+NET "SF_A<0>"           LOC = "H17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_A<1>"           LOC = "J13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_A<2>"           LOC = "J12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_A<3>"           LOC = "J14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_A<4>"           LOC = "J15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_A<5>"           LOC = "J16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_A<6>"           LOC = "J17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_A<7>"           LOC = "K14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_A<8>"           LOC = "K15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_A<9>"           LOC = "K12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_A<10>"          LOC = "K13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_A<11>"          LOC = "L15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_A<12>"          LOC = "L16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_A<13>"          LOC = "T18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_A<14>"          LOC = "R18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_A<15>"          LOC = "T17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_A<16>"          LOC = "U18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_A<17>"          LOC = "T16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_A<18>"          LOC = "U15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_A<19>"          LOC = "V15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_A<20>"          LOC = "T12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_A<21>"          LOC = "V13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_A<22>"          LOC = "V12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_A<23>"          LOC = "N11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+#NET "SF_A<24>"         LOC = "A11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_BYTE"           LOC = "C17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_CE0"            LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_D<1>"           LOC = "P10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_D<2>"           LOC = "R10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_D<3>"           LOC = "V9"  | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_D<4>"           LOC = "U9"  | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_D<5>"           LOC = "R9"  | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_D<6>"           LOC = "M9"  | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_D<7>"           LOC = "N9"  | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_D<8>"           LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_D<9>"           LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_D<10>"          LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_D<11>"          LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_D<12>"          LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_D<13>"          LOC = "P6"  | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_D<14>"          LOC = "R8"  | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_D<15>"          LOC = "T8"  | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_OE"             LOC = "C18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+NET "SF_STS"            LOC = "B18" | IOSTANDARD = LVCMOS33 ;

+NET "SF_WE"             LOC = "D17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+

+# STMicro SPI serial Flash (SPI) 

+# some connections shared with SPI Flash, DAC, ADC, and AMP

+NET "SPI_MISO" 	        LOC = "N10" | IOSTANDARD = LVCMOS33 ;

+NET "SPI_MOSI" 	        LOC = "T4"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;

+NET "SPI_SCK" 	        LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;

+NET "SPI_SS_B"          LOC = "U3"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 | PULLUP ;

+NET "SPI_ALT_CS_JP11"   LOC = "R12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;

+

+# Slide Switches (SW) 

+NET "SW<0>"             LOC = "L13" | IOSTANDARD = LVTTL | PULLUP | TIG;

+NET "SW<1>"             LOC = "L14" | IOSTANDARD = LVTTL | PULLUP | TIG;

+NET "SW<2>"             LOC = "H18" | IOSTANDARD = LVTTL | PULLUP | TIG;

+NET "SW<3>"             LOC = "N17" | IOSTANDARD = LVTTL | PULLUP | TIG;

+

+# VGA Port (VGA) 

+NET "VGA_BLUE"          LOC = "G15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;

+NET "VGA_GREEN"         LOC = "H15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;

+NET "VGA_HSYNC"         LOC = "F15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;

+NET "VGA_RED"           LOC = "H14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;

+NET "VGA_VSYNC"         LOC = "F14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;

+

+# Xilinx CPLD (XC) 

+NET "XC_CMD<0>"         LOC = "P18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;

+NET "XC_CMD<1>"         LOC = "N18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;

+NET "XC_CPLD_EN"        LOC = "B10" | IOSTANDARD = LVTTL ;

+NET "XC_D<0>"           LOC = "G16" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;

+NET "XC_D<1>"           LOC = "F18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;

+NET "XC_D<2>"           LOC = "F17" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;

+NET "XC_TRIG"           LOC = "R17" | IOSTANDARD = LVCMOS33 ;

+NET "XC_GCK0"           LOC = "H16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+#NET "GCLK10"           LOC = "C9"  | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

+

+# prohibit unused pins

+CONFIG                  PROHIBIT = A3;

+CONFIG                  PROHIBIT = A7;

+CONFIG                  PROHIBIT = D13;

+CONFIG                  PROHIBIT = F10;

+CONFIG                  PROHIBIT = G10;

+CONFIG                  PROHIBIT = C8;

+CONFIG                  PROHIBIT = D8;

+CONFIG                  PROHIBIT = A5;

+CONFIG                  PROHIBIT = B5;

+#

+CONFIG                  PROHIBIT = P13;

+CONFIG                  PROHIBIT = R13;

+CONFIG                  PROHIBIT = T14;

+CONFIG                  PROHIBIT = R14;

+#

+CONFIG                  PROHIBIT = D3;

+CONFIG                  PROHIBIT = F5;

+CONFIG                  PROHIBIT = G1;

+CONFIG                  PROHIBIT = J7;

+CONFIG                  PROHIBIT = K2;

+CONFIG                  PROHIBIT = K7;

+CONFIG                  PROHIBIT = M1;

+CONFIG                  PROHIBIT = N1;

+CONFIG                  PROHIBIT = N2;

+CONFIG                  PROHIBIT = R1;

+CONFIG                  PROHIBIT = U1;

diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj
new file mode 100644
index 0000000..965ae4c
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj
@@ -0,0 +1,19 @@
+vhdl work ../top.vhd

+vhdl zpu ../../../zpu_pkg.vhdl

+vhdl zpu ../../../zpu_small.vhdl

+vhdl zpu ../../../zpu_medium.vhdl

+vhdl zpu ../../../roms/rom_pkg.vhdl

+#vhdl zpu ../../../roms/hello_dbram.vhdl

+#vhdl zpu ../../../roms/hello_bram.vhdl

+vhdl zpu ../../../roms/dmips_dbram.vhdl

+vhdl zpu ../../../roms/dmips_bram.vhdl

+vhdl zpu ../../../helpers/zpu_small1.vhdl

+vhdl zpu ../../../helpers/zpu_med1.vhdl

+vhdl zpu ../../../devices/txt_util.vhdl

+vhdl zpu ../../../devices/phi_io.vhdl

+vhdl zpu ../../../devices/timer.vhdl

+vhdl zpu ../../../devices/gpio.vhdl

+vhdl zpu ../../../devices/rx_unit.vhdl

+vhdl zpu ../../../devices/tx_unit.vhdl

+vhdl zpu ../../../devices/br_gen.vhdl

+vhdl zpu ../../../devices/trace.vhdl

diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut
new file mode 100644
index 0000000..4bf13c6
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut
@@ -0,0 +1,22 @@
+-w

+-g DebugBitstream:No

+-g Binary:no

+-g CRC:Enable

+-g ConfigRate:1

+-g ProgPin:PullUp

+-g DonePin:PullUp

+-g TckPin:PullUp

+-g TdiPin:PullUp

+-g TdoPin:PullUp

+-g TmsPin:PullUp

+-g UnusedPin:PullDown

+-g UserID:0xFFFFFFFF

+-g DCMShutdown:Disable

+-g StartUpClk:CClk

+-g DONE_cycle:4

+-g GTS_cycle:5

+-g GWE_cycle:6

+-g LCK_cycle:NoWait

+-g Security:None

+-g DonePipe:No

+-g DriveDone:No

diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.xst b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.xst
new file mode 100644
index 0000000..d357860
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.xst
@@ -0,0 +1,56 @@
+set -tmpdir "tmp"

+set -xsthdpdir "xst"

+run

+-ifn ../synthesis_config/top.prj

+-ifmt mixed

+-ofn top

+-ofmt NGC

+-p xc3s500e-4-fg320

+-top top

+-opt_mode Speed

+-opt_level 1

+-iuc NO

+-keep_hierarchy No

+-netlist_hierarchy As_Optimized

+-rtlview Yes

+-glob_opt AllClockNets

+-read_cores YES

+-write_timing_constraints NO

+-cross_clock_analysis NO

+-hierarchy_separator /

+-bus_delimiter <>

+-case Maintain

+-slice_utilization_ratio 100

+-bram_utilization_ratio 100

+-verilog2001 YES

+-fsm_extract YES -fsm_encoding Auto

+-safe_implementation No

+-fsm_style LUT

+-ram_extract Yes

+-ram_style Auto

+-rom_extract Yes

+-mux_style Auto

+-decoder_extract YES

+-priority_extract Yes

+-shreg_extract YES

+-shift_extract YES

+-xor_collapse YES

+-rom_style Auto

+-auto_bram_packing NO

+-mux_extract Yes

+-resource_sharing YES

+-async_to_sync NO

+-mult_style Auto

+-iobuf YES

+-max_fanout 500

+-bufg 24

+-register_duplication YES

+-register_balancing No

+-slice_packing YES

+-optimize_primitives NO

+-use_clock_enable Yes

+-use_sync_set Yes

+-use_sync_reset Yes

+-iob Auto

+-equivalent_register_removal YES

+-slice_utilization_ratio_maxmargin 5

diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top.vhd b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top.vhd
new file mode 100644
index 0000000..4adc18b
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top.vhd
@@ -0,0 +1,464 @@
+-- top module of

+-- Spartan-3E Starter Kit Board

+--

+-- using following external connections:

+-- rotary pushbutton as reset

+-- LEDs   for output

+-- RS232 (DCE, the left one)

+--

+

+

+library ieee;

+use ieee.std_logic_1164.all;

+

+library zpu;

+use zpu.zpupkg.all;                     -- zpu_dbgo_t

+

+library unisim;

+use unisim.vcomponents.dcm_sp;

+

+

+entity top is

+    port (

+        -- pragma translate_off 

+        stop_simulation : out   std_logic;

+        -- pragma translate_on 

+        --

+        -- Analog-to-Digital Converter (ADC)

+        ad_conv         : out   std_logic;

+        -- Programmable Gain Amplifier (AMP)

+        amp_cs          : out   std_logic;  -- active low chip select

+        amp_dout        : in    std_logic;

+        amp_shdn        : out   std_logic;  -- active high shutdown, reset

+        -- Pushbuttons (BTN)

+        btn_east        : in    std_logic;

+        btn_north       : in    std_logic;

+        btn_south       : in    std_logic;

+        btn_west        : in    std_logic;

+        -- Clock inputs (CLK)

+        clk_50mhz       : in    std_logic;

+        clk_aux         : in    std_logic;

+        clk_sma         : in    std_logic;

+        -- Digital-to-Analog Converter (DAC)

+        dac_clr         : out   std_logic;  -- async, active low reset input

+        dac_cs          : out   std_logic;  -- active low chip select, conv start with rising edge

+        -- 1-Wire Secure EEPROM (DS)

+        ds_wire         : inout std_logic;

+        -- Ethernet PHY (E)

+        e_col           : in    std_logic;  -- MII collision detect

+        e_crs           : in    std_logic;  -- carrier sense

+        e_mdc           : out   std_logic;  -- management clock

+        e_mdio          : inout std_logic;  -- management data io

+        e_rx_clk        : in    std_logic;  -- receive clock 25MHz@100BaseTx or 2.5MHz@10Base-T

+        e_rx_dv         : in    std_logic;  -- receive data valid

+        e_rxd           : in    std_logic_vector(3 downto 0);

+        e_rx_er         : in    std_logic;

+        e_tx_clk        : in    std_logic;  -- transmit clock 25MHz@100BaseTx or 2.5MHz@10Base-T

+        e_tx_en         : out   std_logic;  -- transmit enable

+        e_txd           : out   std_logic_vector(3 downto 0);

+        e_tx_er         : out   std_logic;

+        -- FPGA Configuration Mode, INIT_B Pins (FPGA)

+        fpga_m0         : inout std_logic;

+        fpga_m1         : inout std_logic;

+        fpga_m2         : inout std_logic;

+        fpga_init_b     : inout std_logic;

+        fpga_rdwr_b     : in    std_logic;

+        fpga_hswap      : in    std_logic;

+        -- FX2 Connector (FX2)

+        fx2_clkin       : inout std_logic;

+        fx2_clkio       : inout std_logic;

+        fx2_clkout      : inout std_logic;

+        fx2_io          : inout std_logic_vector(40 downto 1);

+        -- These are shared connections with the FX2 connector

+        --j1              : inout std_logic_vector(3 downto 0);

+        --j2              : inout std_logic_vector(3 downto 0);

+        --j4              : inout std_logic_vector(3 downto 0);

+        --led             : out   std_logic_vector(7 downto 0);

+        -- Character LCD (LCD)

+        lcd_e           : out   std_logic;

+        lcd_rs          : out   std_logic;

+        lcd_rw          : out   std_logic;

+        -- LCD data connections are shared with StrataFlash connections SF_D<11:8>

+        --sf_d          : inout std_ulogic_vector(11 downto 8);

+        -- PS/2 Mouse/Keyboard Port (PS2)

+        ps2_clk         : inout std_logic;

+        ps2_data        : inout std_logic;

+        -- Rotary Pushbutton Switch (ROT)

+        rot_a           : in    std_logic;

+        rot_b           : in    std_logic;

+        rot_center      : in    std_logic;

+        -- RS-232 Serial Ports (RS232)

+        rs232_dce_rxd   : in    std_logic;

+        rs232_dce_txd   : out   std_logic;

+        rs232_dte_rxd   : in    std_logic;

+        rs232_dte_txd   : out   std_logic;

+        -- DDR SDRAM (SD) (I/O Bank 3, VCCO=2.5V)

+        sd_a            : out   std_logic_vector(12 downto 0);  -- address inputs

+        sd_dq           : inout std_logic_vector(15 downto 0);  -- data io

+        sd_ba           : out   std_logic_vector(1 downto 0);   -- bank address inputs

+        sd_ras          : out   std_logic;                      -- command output

+        sd_cas          : out   std_logic;                      -- command output

+        sd_we           : out   std_logic;                      -- command output 

+        sd_udm          : out   std_logic;                      -- data mask

+        sd_ldm          : out   std_logic;                      -- data mask

+        sd_udqs         : inout std_logic;                      -- data strobe

+        sd_ldqs         : inout std_logic;                      -- data strobe

+        sd_cs           : out   std_logic;                      -- active low chip select

+        sd_cke          : out   std_logic;                      -- active high clock enable

+        sd_ck_n         : out   std_logic;                      -- differential clock

+        sd_ck_p         : out   std_logic;                      -- differential clock

+        -- Path to allow connection to top DCM connection

+        sd_ck_fb        : in    std_logic;

+        -- Intel StrataFlash Parallel NOR Flash (SF)

+        sf_a            : out   std_logic_vector(23 downto 0);  -- sf_a<24> = fx_io32

+        sf_byte         : out   std_logic;

+        sf_ce0          : out   std_logic;

+        sf_d            : inout std_logic_vector(15 downto 1);

+        sf_oe           : out   std_logic;

+        sf_sts          : in    std_logic;

+        sf_we           : out   std_logic;

+        -- STMicro SPI serial Flash (SPI)

+        spi_mosi        : out   std_logic;  -- master out slave in

+        spi_miso        : in    std_logic;  -- master in  slave out

+        spi_sck         : out   std_logic;  -- clock

+        spi_ss_b        : out   std_logic;  -- active low slave select

+        spi_alt_cs_jp11 : out   std_logic;

+        -- Slide Switches (SW)

+        sw              : in    std_logic_vector(3 downto 0);

+        -- VGA Port (VGA)

+        vga_blue        : out   std_logic;

+        vga_green       : out   std_logic;

+        vga_hsync       : out   std_logic;

+        vga_red         : out   std_logic;

+        vga_vsync       : out   std_logic;

+        -- Xilinx CPLD (XC)

+        xc_cmd          : out   std_logic_vector(1 downto 0);

+        xc_cpld_en      : out   std_logic;

+        xc_d            : inout std_logic_vector(2 downto 0);

+        xc_trig         : in    std_logic;

+        xc_gck0         : inout std_logic;

+        gclk10          : inout std_logic

+        );

+end entity top;

+

+

+architecture rtl of top is

+

+    ---------------------------

+    -- type declarations

+    type zpu_type is (zpu_small, zpu_medium);

+

+    ---------------------------

+    -- constant declarations

+    constant zpu_flavour : zpu_type := zpu_medium;  -- choose your flavour HERE

+    --  modify frequency here

+    constant clk_multiply : positive := 3;  -- 2 for small, 3 for medium

+    constant clk_divide   : positive := 2;  -- 1 for small, 2 for medium

+    --

+    constant word_size_c  : natural  := 32; -- 32 bits data path

+    constant addr_w_c     : natural  := 18; -- 18 bits address space=256 kB, 128 kB I/O

+

+

+    constant spi_ss_b_disable    : std_ulogic := '1';  -- 1 = disable SPI serial flash

+    constant dac_cs_disable      : std_ulogic := '1';  -- 1 = disable DAC 

+    constant amp_cs_disable      : std_ulogic := '1';  -- 1 = disable programmable pre-amplifier

+    constant ad_conv_disable     : std_ulogic := '0';  -- 0 = disable ADC

+    constant sf_ce0_disable      : std_ulogic := '1';

+    constant fpga_init_b_disable : std_ulogic := '1';  -- 1 = disable pflatform flash PROM

+    --

+    -- connect ldc to fpga

+    constant sf_ce0_lcd_to_fpga  : std_ulogic := '1';

+    --

+    constant clk_frequency       : positive   := 50;   -- input frequency for correct calculation

+

+

+    ---------------------------

+    -- component declarations

+    component zpu_small1 is

+        generic (

+            word_size  : natural   := 32;      -- 32 bits data path

+            d_care_val : std_logic := '0';     -- Fill value

+            clk_freq   : positive  := 50;      -- 50 MHz clock

+            brate      : positive  := 115200;  -- RS232 baudrate

+            addr_w     : natural   := 16;      -- 16 bits address space=64 kB, 32 kB I/O

+            bram_w     : natural   := 15       -- 15 bits RAM space=32 kB

+            );

+        port (

+            clk_i      : in  std_logic;        -- CPU clock

+            rst_i      : in  std_logic;        -- Reset

+            break_o    : out std_logic;        -- Break executed

+            dbg_o      : out zpu_dbgo_t;       -- Debug info

+            rs232_tx_o : out std_logic;        -- UART Tx

+            rs232_rx_i : in  std_logic;        -- UART Rx

+            gpio_in    : in  std_logic_vector(31 downto 0);

+            gpio_out   : out std_logic_vector(31 downto 0);

+            gpio_dir   : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out

+            );

+    end component zpu_small1;

+

+    component zpu_med1 is

+        generic(

+            word_size  : natural   := 32;      -- 32 bits data path

+            d_care_val : std_logic := '0';     -- Fill value

+            clk_freq   : positive  := 50;      -- 50 MHz clock

+            brate      : positive  := 115200;  -- RS232 baudrate

+            addr_w     : natural   := 18;      -- 18 bits address space=256 kB, 128 kB I/O

+            bram_w     : natural   := 15       -- 15 bits RAM space=32 kB

+            );

+        port(

+            clk_i      : in  std_logic;        -- CPU clock

+            rst_i      : in  std_logic;        -- Reset

+            break_o    : out std_logic;        -- Break executed

+            dbg_o      : out zpu_dbgo_t;       -- Debug info

+            rs232_tx_o : out std_logic;        -- UART Tx

+            rs232_rx_i : in  std_logic;        -- UART Rx

+            gpio_in    : in  std_logic_vector(31 downto 0);

+            gpio_out   : out std_logic_vector(31 downto 0);

+            gpio_dir   : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out

+            );

+    end component zpu_med1;

+

+

+    ---------------------------

+    -- signal declarations

+    signal dcm_sp_i0_clk0  : std_ulogic;

+    signal dcm_sp_i0_clkfx : std_ulogic;

+    signal clk_fb          : std_ulogic;

+    signal clk             : std_ulogic;

+    --

+    signal reset_shift_reg : std_ulogic_vector(3 downto 0);

+    signal reset_sync      : std_ulogic;

+    --

+    signal zpu_i0_dbg      : zpu_dbgo_t;  -- Debug info

+    signal zpu_i0_break    : std_logic;

+    --

+    signal gpio_in         : std_logic_vector(31 downto 0);

+    signal zpu_i0_gpio_out : std_logic_vector(31 downto 0);

+    signal zpu_i0_gpio_dir : std_logic_vector(31 downto 0);

+    

+    ---------------------------

+    -- alias declarations

+    alias led : std_logic_vector(7 downto 0) is fx2_io(20 downto 13);

+

+

+begin

+

+    -- default output drivers

+    -- to pass bitgen DRC 

+    -- outputs used by design are commented

+    --

+    ad_conv           <= ad_conv_disable;

+    amp_cs            <= amp_cs_disable;

+    amp_shdn          <= '1';

+    --

+    dac_clr           <= '0';

+    dac_cs            <= dac_cs_disable;

+    --

+    ds_wire           <= 'Z';

+    --

+    e_txd(3 downto 0) <= (others => '1');

+    e_tx_en           <= '0';

+    e_tx_er           <= '0';

+    e_mdc             <= '1';

+    e_mdio            <= 'Z';

+    --

+    fpga_m0           <= 'Z';

+    fpga_m1           <= 'Z';

+    fpga_m2           <= 'Z';

+    fpga_init_b       <= fpga_init_b_disable;

+    --

+    fx2_clkin         <= 'Z';

+    fx2_clkio         <= 'Z';

+    fx2_clkout        <= 'Z';

+    fx2_io            <= (others => 'Z');

+    --

+    lcd_e             <= '0';

+    lcd_rs            <= '0';

+    lcd_rw            <= '0';

+    --

+    ps2_clk           <= 'Z';

+    ps2_data          <= 'Z';

+    --

+    --rs232_dce_txd     <= '1';

+    rs232_dte_txd     <= '1';

+    --

+    sd_a              <= (others => '1');

+    sd_dq             <= (others => 'Z');

+    sd_ba             <= (others => '1');

+    sd_ras            <= '0';

+    sd_cas            <= '0';

+    sd_we             <= '0';

+    sd_udm            <= '1';

+    sd_ldm            <= '1';

+    sd_udqs           <= '1';

+    sd_ldqs           <= '1';

+    sd_cs             <= '1';

+    sd_cke            <= '1';

+    sd_ck_n           <= '0';

+    sd_ck_p           <= '1';

+    --

+    sf_a              <= (others => '0');

+    sf_byte           <= '0';

+    sf_ce0            <= sf_ce0_lcd_to_fpga;

+    sf_d              <= (others => 'Z');

+    sf_oe             <= '1';

+    sf_we             <= '0';

+    --

+    spi_mosi          <= '0';

+    spi_sck           <= '0';

+    spi_ss_b          <= spi_ss_b_disable;

+    spi_alt_cs_jp11   <= spi_ss_b_disable;

+    --

+    vga_red           <= '0';

+    vga_green         <= '0';

+    vga_blue          <= '0';

+    vga_hsync         <= '0';

+    vga_vsync         <= '0';

+    --

+    xc_cmd            <= "00";

+    xc_d              <= (others => 'Z');

+    xc_cpld_en        <= '0';

+    xc_gck0           <= 'Z';

+    gclk10            <= 'Z';

+    -- led out

+    --fx2_io(20 downto 13) <= (others => '0');

+

+

+    -- digital clock manager (DCM)

+    -- to generate higher/other system clock frequencys

+    dcm_sp_i0 : dcm_sp

+        generic map (

+            startup_wait   => true,     -- wait with DONE till locked

+            clkfx_multiply => clk_multiply,

+            clkfx_divide   => clk_divide, 

+            clk_feedback   => "1X"

+            )

+        port map (

+            clkin => clk_50mhz,

+            clk0  => dcm_sp_i0_clk0,

+            clkfx => dcm_sp_i0_clkfx,

+            clkfb => clk_fb

+            );

+

+    clk_fb <= dcm_sp_i0_clk0;

+    clk    <= dcm_sp_i0_clkfx;

+

+

+    -- reset synchronizer

+    -- generate synchronous reset

+    reset_synchronizer : process(clk, rot_center)

+    begin

+        if rot_center = '1' then

+            reset_shift_reg <= (others => '1');

+        elsif rising_edge(clk) then

+            reset_shift_reg <= reset_shift_reg(reset_shift_reg'high-1 downto 0) & '0';

+        end if;

+    end process;

+    reset_sync <= reset_shift_reg(reset_shift_reg'high);

+

+

+    -- select instance of zpu

+    zpu_i0_small : if zpu_flavour = zpu_small generate

+        zpu_i0 : zpu_small1

+            generic map (

+                addr_w    => addr_w_c,

+                word_size => word_size_c,

+                clk_freq  => clk_frequency * clk_multiply / clk_divide

+                )

+            port map (

+                clk_i      => clk,             -- : in  std_logic;   -- CPU clock

+                rst_i      => reset_sync,      -- : in  std_logic;   -- Reset

+                break_o    => zpu_i0_break,    -- : out std_logic;   -- Break executed

+                dbg_o      => zpu_i0_dbg,      -- : out zpu_dbgo_t;  -- Debug info

+                rs232_tx_o => rs232_dce_txd,   -- : out std_logic;   -- UART Tx

+                rs232_rx_i => rs232_dce_rxd,   -- : in  std_logic    -- UART Rx

+                gpio_in    => gpio_in,         -- : in  std_logic_vector(31 downto 0);

+                gpio_out   => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);

+                gpio_dir   => zpu_i0_gpio_dir  -- : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out

+                );

+    end generate zpu_i0_small;

+

+    zpu_i0_medium : if zpu_flavour = zpu_medium generate

+        zpu_i0 : zpu_med1

+            generic map (

+                addr_w    => addr_w_c,

+                word_size => word_size_c,

+                clk_freq  => clk_frequency * clk_multiply / clk_divide

+                )

+            port map (

+                clk_i      => clk,             -- : in  std_logic;   -- CPU clock

+                rst_i      => reset_sync,      -- : in  std_logic;   -- Reset

+                break_o    => zpu_i0_break,    -- : out std_logic;   -- Break executed

+                dbg_o      => zpu_i0_dbg,      -- : out zpu_dbgo_t;  -- Debug info

+                rs232_tx_o => rs232_dce_txd,   -- : out std_logic;   -- UART Tx

+                rs232_rx_i => rs232_dce_rxd,   -- : in  std_logic    -- UART Rx

+                gpio_in    => gpio_in,         -- : in  std_logic_vector(31 downto 0);

+                gpio_out   => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);

+                gpio_dir   => zpu_i0_gpio_dir  -- : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out

+                );

+    end generate zpu_i0_medium;

+

+

+    -- pragma translate_off 

+    stop_simulation <= zpu_i0_break;

+

+

+    trace_mod : trace

+        generic map (

+            addr_w    => addr_w_c,

+            word_size => word_size_c,

+            log_file  => "zpu_trace.log"

+            )

+        port map (

+            clk_i  => clk,

+            dbg_i  => zpu_i0_dbg,

+            stop_i => zpu_i0_break,

+            busy_i => '0'

+            );

+    -- pragma translate_on

+

+

+    -- assign GPIOs

+    -- no bidirectional pins (e.g. headers), so

+    -- gpio_dir is unused

+    --

+    -- bit   31 30 29 28 27 26 25 24  23 22 21 20 19 18 17 16

+    --

+    --  in   -- -- -- -- -- -- -- --  -- -- -- -- -- -- -- --

+    -- out   -- -- -- -- -- -- -- --  -- -- -- -- -- -- -- --

+    --

+    --

+    -- bit   15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0

+    --                                                       

+    --  in   -- -- -- -- sw(3.....0)  -- ra rb rc be bn bs bw

+    -- out   -- -- -- -- -- -- -- --  led(7................0)

+

+    gpio_in <= ((11) => sw(3),

+                (10) => sw(2),

+                ( 9) => sw(1),

+                ( 8) => sw(0),

+                --

+                ( 6) => rot_a,

+                ( 5) => rot_b,

+                ( 4) => rot_center,

+                --

+                ( 3) => btn_east,

+                ( 2) => btn_north,

+                ( 1) => btn_south,

+                ( 0) => btn_west,

+                others => '0');

+

+

+    -- switch on all LEDs in case of break

+    process

+    begin

+        wait until rising_edge(clk);

+        led <= zpu_i0_gpio_out(7 downto 0);

+        if zpu_i0_break = '1' then

+            led <= (others => '1');

+        end if;

+    end process;

+

+    

+

+end architecture rtl;

diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top_tb.vhd b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top_tb.vhd
new file mode 100644
index 0000000..d62bed9
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top_tb.vhd
@@ -0,0 +1,281 @@
+-- testbench for

+-- Digilent Spartan 3E Starter Board

+--

+-- includes "model" for clock generation

+-- simulate press on Rotary Pushbutton Switch as reset

+--

+-- place models for external components (PHY, SDRAM) in this file

+--

+

+

+library ieee;

+use ieee.std_logic_1164.all;

+

+

+entity top_tb is

+end entity top_tb;

+

+architecture testbench of top_tb is

+

+    ---------------------------

+    -- constant declarations

+    constant clk_50mhz_period : time := 1 sec / 50_000_000;  -- 50 MHz

+

+

+    ---------------------------

+    -- signal declarations

+    signal simulation_run     : boolean                      := true;

+    signal tb_stop_simulation : std_logic;

+    --

+    -- Analog-to-Digital Converter (ADC)

+    signal tb_ad_conv         : std_logic;

+    -- Programmable Gain Amplifier (AMP)

+    signal tb_amp_cs          : std_logic;  -- active low chip select

+    signal tb_amp_dout        : std_logic                    := '1';

+    signal tb_amp_shdn        : std_logic;  -- active high shutdown, reset

+    -- Pushbuttons (BTN)

+    signal tb_btn_east        : std_logic                    := '0';

+    signal tb_btn_north       : std_logic                    := '0';

+    signal tb_btn_south       : std_logic                    := '0';

+    signal tb_btn_west        : std_logic                    := '0';

+    -- Clock inputs (CLK)

+    signal tb_clk_50mhz       : std_logic                    := '0';

+    signal tb_clk_aux         : std_logic                    := '0';

+    signal tb_clk_sma         : std_logic                    := '0';

+    -- Digital-to-Analog Converter (DAC)

+    signal tb_dac_clr         : std_logic;  -- async, active low reset input

+    signal tb_dac_cs          : std_logic;  -- active low chip select, conv start with rising edge

+    -- 1-Wire Secure EEPROM (DS)

+    signal tb_ds_wire         : std_logic;

+    -- Ethernet PHY (E)

+    signal tb_e_col           : std_logic                    := '0';  -- MII collision detect

+    signal tb_e_crs           : std_logic                    := '0';  -- carrier sense

+    signal tb_e_mdc           : std_logic;  -- management clock

+    signal tb_e_mdio          : std_logic;  -- management data io

+    signal tb_e_rx_clk        : std_logic                    := '0';  -- receive clock 25MHz@100BaseTx or 2.5MHz@10Base-T

+    signal tb_e_rx_dv         : std_logic                    := '0';  -- receive data valid

+    signal tb_e_rxd           : std_logic_vector(3 downto 0) := (others => '0');

+    signal tb_e_rx_er         : std_logic                    := '0';

+    signal tb_e_tx_clk        : std_logic                    := '0';  -- transmit clock 25MHz@100BaseTx or 2.5MHz@10Base-T

+    signal tb_e_tx_en         : std_logic;  -- transmit enable

+    signal tb_e_txd           : std_logic_vector(3 downto 0);

+    signal tb_e_tx_er         : std_logic;

+    -- FPGA Configuration Mode, INIT_B Pins (FPGA)

+    signal tb_fpga_m0         : std_logic;

+    signal tb_fpga_m1         : std_logic;

+    signal tb_fpga_m2         : std_logic;

+    signal tb_fpga_init_b     : std_logic;

+    signal tb_fpga_rdwr_b     : std_logic                    := '0';

+    signal tb_fpga_hswap      : std_logic                    := '0';

+    -- FX2 Connector (FX2)

+    signal tb_fx2_clkin       : std_logic;

+    signal tb_fx2_clkio       : std_logic;

+    signal tb_fx2_clkout      : std_logic;

+    signal tb_fx2_io          : std_logic_vector(40 downto 1);

+    -- Character LCD (LCD)

+    signal tb_lcd_e           : std_logic;

+    signal tb_lcd_rs          : std_logic;

+    signal tb_lcd_rw          : std_logic;

+    -- LCD data connections are shared with StrataFlash connections SF_D<11:8>

+    -- PS/2 Mouse/Keyboard Port (PS2)

+    signal tb_ps2_clk         : std_logic;

+    signal tb_ps2_data        : std_logic;

+    -- Rotary Pushbutton Switch (ROT)

+    signal tb_rot_a           : std_logic                    := '0';

+    signal tb_rot_b           : std_logic                    := '0';

+    signal tb_rot_center      : std_logic;  -- use as reset

+    -- RS-232 Serial Ports (RS232)

+    signal tb_rs232_dce_rxd   : std_logic                    := '1';

+    signal tb_rs232_dce_txd   : std_logic;

+    signal tb_rs232_dte_rxd   : std_logic                    := '1';

+    signal tb_rs232_dte_txd   : std_logic;

+    -- DDR SDRAM (SD) (I/O Bank 3, VCCO=2.5V)

+    signal tb_sd_a            : std_logic_vector(12 downto 0);  -- address inputs

+    signal tb_sd_dq           : std_logic_vector(15 downto 0);  -- data io

+    signal tb_sd_ba           : std_logic_vector(1 downto 0);  -- bank address inputs

+    signal tb_sd_ras          : std_logic;  -- command output

+    signal tb_sd_cas          : std_logic;  -- command output

+    signal tb_sd_we           : std_logic;  -- command output 

+    signal tb_sd_udm          : std_logic;  -- data mask

+    signal tb_sd_ldm          : std_logic;  -- data mask

+    signal tb_sd_udqs         : std_logic;  -- data strobe

+    signal tb_sd_ldqs         : std_logic;  -- data strobe

+    signal tb_sd_cs           : std_logic;  -- active low chip select

+    signal tb_sd_cke          : std_logic;  -- active high clock enable

+    signal tb_sd_ck_n         : std_logic;  -- differential clock

+    signal tb_sd_ck_p         : std_logic;  -- differential clock

+    -- Path to allow connection to top DCM connection

+    signal tb_sd_ck_fb        : std_logic;

+    -- Intel StrataFlash Parallel NOR Flash (SF)

+    signal tb_sf_a            : std_logic_vector(23 downto 0);  -- sf_a<24> = fx_io32 :-(

+    signal tb_sf_byte         : std_logic;

+    signal tb_sf_ce0          : std_logic;

+    signal tb_sf_d            : std_logic_vector(15 downto 1);

+    signal tb_sf_oe           : std_logic;

+    signal tb_sf_sts          : std_logic                    := '0';

+    signal tb_sf_we           : std_logic;

+    -- STMicro SPI serial Flash (SPI)

+    signal tb_spi_mosi        : std_logic;  -- master out slave in

+    signal tb_spi_miso        : std_logic                    := '0';  -- master in  slave out

+    signal tb_spi_sck         : std_logic;  -- clock

+    signal tb_spi_ss_b        : std_logic;  -- active low slave select

+    signal tb_spi_alt_cs_jp11 : std_logic;

+    -- Slide Switches (SW)

+    signal tb_sw              : std_logic_vector(3 downto 0) := (others => '0');

+    -- VGA Port (VGA)

+    signal tb_vga_blue        : std_logic;

+    signal tb_vga_green       : std_logic;

+    signal tb_vga_hsync       : std_logic;

+    signal tb_vga_red         : std_logic;

+    signal tb_vga_vsync       : std_logic;

+    -- Xilinx CPLD (XC)

+    signal tb_xc_cmd          : std_logic_vector(1 downto 0);

+    signal tb_xc_cpld_en      : std_logic;

+    signal tb_xc_d            : std_logic_vector(2 downto 0);

+    signal tb_xc_trig         : std_logic                    := '0';

+    signal tb_xc_gck0         : std_logic;

+    signal tb_gclk10          : std_logic;

+

+

+begin

+

+

+    -- generate clock

+    tb_clk_50mhz <= not tb_clk_50mhz after clk_50mhz_period / 2 when simulation_run;

+

+    -- generate reset

+    tb_rot_center <= '1', '0' after 6.66 * clk_50mhz_period;

+

+

+    -- clock feedback for SD-RAM (on board)

+    tb_sd_ck_fb <= tb_sd_ck_p;

+

+    -- simulate keypress

+    tb_btn_north <= '0', '1' after 55 us, '0' after 56 us;

+

+    -- dut

+    top_i0 : entity work.top

+        port map (

+            stop_simulation => tb_stop_simulation,  -- : out   std_logic;

+            -- Analog-to-Digital Converter (ADC)

+            ad_conv         => tb_ad_conv,          -- : out   std_logic;

+            -- Programmable Gain Amplifier (AMP)

+            amp_cs          => tb_amp_cs,           -- : out   std_logic;

+            amp_dout        => tb_amp_dout,         -- : in    std_logic;

+            amp_shdn        => tb_amp_shdn,         -- : out   std_logic;

+            -- Pushbuttons (BTN)

+            btn_east        => tb_btn_east,         -- : in    std_logic;

+            btn_north       => tb_btn_north,        -- : in    std_logic;

+            btn_south       => tb_btn_south,        -- : in    std_logic;

+            btn_west        => tb_btn_west,         -- : in    std_logic;

+            -- Clock inputs (CLK)

+            clk_50mhz       => tb_clk_50mhz,        -- : in    std_logic;

+            clk_aux         => tb_clk_aux,          -- : in    std_logic;

+            clk_sma         => tb_clk_sma,          -- : in    std_logic;

+            -- Digital-to-Analog Converter (DAC)

+            dac_clr         => tb_dac_clr,          -- : out   std_logic;

+            dac_cs          => tb_dac_cs,           -- : out   std_logic;

+            -- 1-Wire Secure EEPROM (DS)

+            ds_wire         => tb_ds_wire,          -- : inout std_logic;

+            -- Ethernet PHY (E)

+            e_col           => tb_e_col,            -- : in    std_logic;

+            e_crs           => tb_e_crs,            -- : in    std_logic;

+            e_mdc           => tb_e_mdc,            -- : out   std_logic;

+            e_mdio          => tb_e_mdio,           -- : inout std_logic;

+            e_rx_clk        => tb_e_rx_clk,         -- : in    std_logic;

+            e_rx_dv         => tb_e_rx_dv,          -- : in    std_logic;

+            e_rxd           => tb_e_rxd,            -- : in    std_logic_vector(3 downto 0);

+            e_rx_er         => tb_e_rx_er,          -- : in    std_logic;

+            e_tx_clk        => tb_e_tx_clk,         -- : in    std_logic;

+            e_tx_en         => tb_e_tx_en,          -- : out   std_logic;

+            e_txd           => tb_e_txd,            -- : out   std_logic_vector(3 downto 0);

+            e_tx_er         => tb_e_tx_er,          -- : out   std_logic;

+            -- FPGA Configuration Mode, INIT_B Pins (FPGA)

+            fpga_m0         => tb_fpga_m0,          -- : inout std_logic;

+            fpga_m1         => tb_fpga_m1,          -- : inout std_logic;

+            fpga_m2         => tb_fpga_m2,          -- : inout std_logic;

+            fpga_init_b     => tb_fpga_init_b,      -- : inout std_logic;

+            fpga_rdwr_b     => tb_fpga_rdwr_b,      -- : in    std_logic;

+            fpga_hswap      => tb_fpga_hswap,       -- : in    std_logic;

+            -- FX2 Connector (FX2)

+            fx2_clkin       => tb_fx2_clkin,        -- : inout std_logic;

+            fx2_clkio       => tb_fx2_clkio,        -- : inout std_logic;

+            fx2_clkout      => tb_fx2_clkout,       -- : inout std_logic;

+            fx2_io          => tb_fx2_io,           -- : inout std_logic_vector(40 downto 1);

+            -- Character LCD (LCD)

+            lcd_e           => tb_lcd_e,            -- : out   std_logic;

+            lcd_rs          => tb_lcd_rs,           -- : out   std_logic;

+            lcd_rw          => tb_lcd_rw,           -- : out   std_logic;

+            -- LCD data connections are shared with StrataFlash connections SF_D<11:8>

+            -- PS/2 Mouse/Keyboard Port (PS2)

+            ps2_clk         => tb_ps2_clk,          -- : inout std_logic;

+            ps2_data        => tb_ps2_data,         -- : inout std_logic;

+            -- Rotary Pushbutton Switch (ROT)

+            rot_a           => tb_rot_a,            -- : in    std_logic;

+            rot_b           => tb_rot_b,            -- : in    std_logic;

+            rot_center      => tb_rot_center,       -- : in    std_logic;

+            -- RS-232 Serial Ports (RS232)

+            rs232_dce_rxd   => tb_rs232_dce_rxd,    -- : in    std_logic;

+            rs232_dce_txd   => tb_rs232_dce_txd,    -- : out   std_logic;

+            rs232_dte_rxd   => tb_rs232_dte_rxd,    -- : in    std_logic;

+            rs232_dte_txd   => tb_rs232_dte_txd,    -- : out   std_logic;

+            -- DDR SDRAM (SD) (I/O Bank 3, VCCO=2.5V)

+            sd_a            => tb_sd_a,             -- : out   std_logic_vector(12 downto 0);

+            sd_dq           => tb_sd_dq,            -- : inout std_logic_vector(15 downto 0);

+            sd_ba           => tb_sd_ba,            -- : out   std_logic_vector(1 downto 0);

+            sd_ras          => tb_sd_ras,           -- : out   std_logic;

+            sd_cas          => tb_sd_cas,           -- : out   std_logic;

+            sd_we           => tb_sd_we,            -- : out   std_logic;

+            sd_udm          => tb_sd_udm,           -- : out   std_logic;

+            sd_ldm          => tb_sd_ldm,           -- : out   std_logic;

+            sd_udqs         => tb_sd_udqs,          -- : inout std_logic;

+            sd_ldqs         => tb_sd_ldqs,          -- : inout std_logic;

+            sd_cs           => tb_sd_cs,            -- : out   std_logic;

+            sd_cke          => tb_sd_cke,           -- : out   std_logic;

+            sd_ck_n         => tb_sd_ck_n,          -- : out   std_logic;

+            sd_ck_p         => tb_sd_ck_p,          -- : out   std_logic;

+            -- Path to allow connection to top DCM connection

+            sd_ck_fb        => tb_sd_ck_fb,         -- : in    std_logic;

+            -- Intel StrataFlash Parallel NOR Flash (SF)

+            sf_a            => tb_sf_a,             -- : out   std_logic_vector(23 downto 0);

+            sf_byte         => tb_sf_byte,          -- : out   std_logic;

+            sf_ce0          => tb_sf_ce0,           -- : out   std_logic;

+            sf_d            => tb_sf_d,             -- : inout std_logic_vector(15 downto 1);

+            sf_oe           => tb_sf_oe,            -- : out   std_logic;

+            sf_sts          => tb_sf_sts,           -- : in    std_logic;

+            sf_we           => tb_sf_we,            -- : out   std_logic;

+            -- STMicro SPI serial Flash (SPI)

+            spi_mosi        => tb_spi_mosi,         -- : out   std_logic;

+            spi_miso        => tb_spi_miso,         -- : in    std_logic;

+            spi_sck         => tb_spi_sck,          -- : out   std_logic;

+            spi_ss_b        => tb_spi_ss_b,         -- : out   std_logic;

+            spi_alt_cs_jp11 => tb_spi_alt_cs_jp11,  -- : out   std_logic;

+            -- Slide Switches (SW)

+            sw              => tb_sw,               -- : in    std_logic_vector(3 downto 0);

+            -- VGA Port (VGA)

+            vga_blue        => tb_vga_blue,         -- : out   std_logic;

+            vga_green       => tb_vga_green,        -- : out   std_logic;

+            vga_hsync       => tb_vga_hsync,        -- : out   std_logic;

+            vga_red         => tb_vga_red,          -- : out   std_logic;

+            vga_vsync       => tb_vga_vsync,        -- : out   std_logic;

+            -- Xilinx CPLD (XC)

+            xc_cmd          => tb_xc_cmd,           -- : out   std_logic_vector(1 downto 0);

+            xc_cpld_en      => tb_xc_cpld_en,       -- : out   std_logic;

+            xc_d            => tb_xc_d,             -- : inout std_logic_vector(2 downto 0);

+            xc_trig         => tb_xc_trig,          -- : in    std_logic;

+            xc_gck0         => tb_xc_gck0,          -- : inout std_logic;

+            gclk10          => tb_gclk10            -- : inout std_logic

+            );

+

+

+    -- check for simulation stopping

+    process (tb_stop_simulation)

+    begin

+        if tb_stop_simulation = '1' then

+            report "Simulation end." severity note;

+            simulation_run <= false;

+        end if;

+    end process;

+

+

+end architecture testbench;

diff --git a/zpu/hdl/zealot/fpga/dmips_med1.vhdl b/zpu/hdl/zealot/fpga/dmips_med1.vhdl
new file mode 100644
index 0000000..b95016c
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/dmips_med1.vhdl
@@ -0,0 +1,119 @@
+------------------------------------------------------------------------------
+----                                                                      ----
+----  ZPU Medium connection to the FPGA pins                              ----
+----                                                                      ----
+----  http://www.opencores.org/                                           ----
+----                                                                      ----
+----  Description:                                                        ----
+----  This module connects the ZPU_Med1 (zpu_med1.vhdl) core to a Spartan ----
+----  3 1500 Xilinx FPGA available in the GR-XC3S board from Pender.      ----
+----                                                                      ----
+----  To Do:                                                              ----
+----  -                                                                   ----
+----                                                                      ----
+----  Author:                                                             ----
+----    - Salvador E. Tropea, salvador inti.gob.ar                        ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar>         ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial       ----
+----                                                                      ----
+---- Distributed under the GPL license                                    ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Design unit:      DMIPS_Med1(FPGA) (Entity and architecture)         ----
+---- File name:        dmips_med1.vhdl                                    ----
+---- Note:             None                                               ----
+---- Limitations:      None known                                         ----
+---- Errors:           None known                                         ----
+---- Library:          work                                               ----
+---- Dependencies:     IEEE.std_logic_1164                                ----
+----                   IEEE.numeric_std                                   ----
+----                   zpu.zpu_pkg                                        ----
+---- Target FPGA:      Spartan 3 (XC3S1500-4-FG456)                       ----
+---- Language:         VHDL                                               ----
+---- Wishbone:         No                                                 ----
+---- Synthesis tools:  Xilinx Release 9.2.03i - xst J.39                  ----
+---- Simulation tools: N/A                                                ----
+---- Text editor:      SETEdit 0.5.x                                      ----
+----                                                                      ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library zpu;
+use zpu.zpupkg.all;
+
+entity DMIPS_Med1 is
+   generic(
+      WORD_SIZE  : natural:=32;  -- 32 bits data path
+      D_CARE_VAL : std_logic:='0'; -- Fill value, I got better results with it
+      CLK_FREQ   : positive:=50; -- 50 MHz clock
+      BRATE      : positive:=115200; -- RS-232 baudrate
+      ADDR_W     : natural:=18;  -- 18 bits address space=256 kB, 128 kB I/O
+      BRAM_W     : natural:=15); -- 15 bits RAM space=32 kB
+   port(
+      clk_i      : in  std_logic;  -- CPU clock
+      rst_i      : in  std_logic;  -- Reset
+      rs232_tx_o : out std_logic;  -- UART Tx
+      rs232_rx_i : in  std_logic); -- UART Rx
+
+   constant BRD_PB1_I      : string:="D19";  -- SWITCH8==S2
+   constant BRD_CLK1_I     : string:="AA12"; -- 50 MHz clock
+   --constant BRD_CLK1_I     : string:="AB12"; -- 40 MHz clock
+   -- UART: direct 1:1 cable
+   constant BRD_TX_O       : string:="L4"; -- UART 1 (J1) TXD1 DB9 pin 2
+   constant BRD_RX_I       : string:="L3"; -- UART 1 (J1) RXD1 DB9 pin 3
+
+   ------------
+   -- Pinout --
+   ------------
+   attribute LOC        : string;
+   attribute IOSTANDARD : string;
+   constant  IOSTD      : string:="LVTTL";
+
+   attribute LOC        of rst_i       : signal is BRD_PB1_I;
+   attribute IOSTANDARD of rst_i       : signal is IOSTD;
+   attribute LOC        of clk_i       : signal is BRD_CLK1_I;
+   attribute LOC        of rs232_tx_o  : signal is BRD_TX_O;
+   attribute IOSTANDARD of rs232_tx_o  : signal is IOSTD;
+   attribute LOC        of rs232_rx_i  : signal is BRD_RX_I;
+   attribute IOSTANDARD of rs232_rx_i  : signal is IOSTD;
+end entity DMIPS_Med1;
+
+architecture FPGA of DMIPS_Med1 is
+   component ZPU_Med1 is
+      generic(
+         WORD_SIZE  : natural:=32;  -- 32 bits data path
+         D_CARE_VAL : std_logic:='X'; -- Fill value
+         CLK_FREQ   : positive:=50; -- 50 MHz clock
+         BRATE      : positive:=9600; -- RS232 baudrate
+         ADDR_W     : natural:=18;  -- 18 bits address space=256 kB, 128 kB I/O
+         BRAM_W     : natural:=15); -- 15 bits RAM space=32 kB
+      port(
+         clk_i      : in  std_logic;  -- CPU clock
+         rst_i      : in  std_logic;  -- Reset
+         break_o    : out std_logic;  -- Break executed
+         dbg_o      : out zpu_dbgo_t; -- Debug info
+         rs232_tx_o : out std_logic;  -- UART Tx
+         rs232_rx_i : in  std_logic;  -- UART Rx
+         gpio_in    : in  std_logic_vector(31 downto 0);
+         gpio_out   : out std_logic_vector(31 downto 0);
+         gpio_dir   : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
+         );
+   end component ZPU_Med1;
+begin
+   zpu : ZPU_Med1
+      generic map(
+         WORD_SIZE => WORD_SIZE, D_CARE_VAL => D_CARE_VAL,
+         CLK_FREQ => CLK_FREQ, BRATE => BRATE, ADDR_W => ADDR_W,
+         BRAM_W => BRAM_W)
+      port map(
+         clk_i => clk_i, rst_i => rst_i, rs232_tx_o => rs232_tx_o,
+         rs232_rx_i => rs232_rx_i, dbg_o => open, gpio_in => (others => '0'));
+end architecture FPGA; -- Entity: DMIPS_Med1
+
diff --git a/zpu/hdl/zealot/fpga/dmips_small1.vhdl b/zpu/hdl/zealot/fpga/dmips_small1.vhdl
new file mode 100644
index 0000000..6edec00
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/dmips_small1.vhdl
@@ -0,0 +1,120 @@
+------------------------------------------------------------------------------
+----                                                                      ----
+----  ZPU Small connection to the FPGA pins                               ----
+----                                                                      ----
+----  http://www.opencores.org/                                           ----
+----                                                                      ----
+----  Description:                                                        ----
+----  This module connects the ZPU_Small1 (zpu_small1.vhdl) core to a     ----
+----  Spartan 3 1500 Xilinx FPGA available in the GR-XC3S board from      ----
+----  Pender.                                                             ----
+----                                                                      ----
+----  To Do:                                                              ----
+----  -                                                                   ----
+----                                                                      ----
+----  Author:                                                             ----
+----    - Salvador E. Tropea, salvador inti.gob.ar                        ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar>         ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial       ----
+----                                                                      ----
+---- Distributed under the GPL license                                    ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Design unit:      DMIPS_Small1(FPGA) (Entity and architecture)       ----
+---- File name:        dmips_small1.vhdl                                  ----
+---- Note:             None                                               ----
+---- Limitations:      None known                                         ----
+---- Errors:           None known                                         ----
+---- Library:          work                                               ----
+---- Dependencies:     IEEE.std_logic_1164                                ----
+----                   IEEE.numeric_std                                   ----
+----                   zpu.zpu_pkg                                        ----
+---- Target FPGA:      Spartan 3 (XC3S1500-4-FG456)                       ----
+---- Language:         VHDL                                               ----
+---- Wishbone:         No                                                 ----
+---- Synthesis tools:  Xilinx Release 9.2.03i - xst J.39                  ----
+---- Simulation tools: N/A                                                ----
+---- Text editor:      SETEdit 0.5.x                                      ----
+----                                                                      ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library zpu;
+use zpu.zpupkg.all;
+
+entity DMIPS_Small1 is
+   generic(
+      WORD_SIZE  : natural:=32;  -- 32 bits data path
+      D_CARE_VAL : std_logic:='0'; -- Fill value, I got better results with it
+      CLK_FREQ   : positive:=50; -- 50 MHz clock
+      BRATE      : positive:=115200; -- RS-232 baudrate
+      ADDR_W     : natural:=18;  -- 18 bits address space=256 kB, 128 kB I/O
+      BRAM_W     : natural:=15); -- 15 bits RAM space=32 kB
+   port(
+      clk_i      : in  std_logic;  -- CPU clock
+      rst_i      : in  std_logic;  -- Reset
+      rs232_tx_o : out std_logic;  -- UART Tx
+      rs232_rx_i : in  std_logic); -- UART Rx
+
+   constant BRD_PB1_I      : string:="D19";  -- SWITCH8==S2
+   constant BRD_CLK1_I     : string:="AA12"; -- 50 MHz clock
+   --constant BRD_CLK1_I     : string:="AB12"; -- 40 MHz clock
+   -- UART: direct 1:1 cable
+   constant BRD_TX_O       : string:="L4"; -- UART 1 (J1) TXD1 DB9 pin 2
+   constant BRD_RX_I       : string:="L3"; -- UART 1 (J1) RXD1 DB9 pin 3
+
+   ------------
+   -- Pinout --
+   ------------
+   attribute LOC        : string;
+   attribute IOSTANDARD : string;
+   constant  IOSTD      : string:="LVTTL";
+
+   attribute LOC        of rst_i       : signal is BRD_PB1_I;
+   attribute IOSTANDARD of rst_i       : signal is IOSTD;
+   attribute LOC        of clk_i       : signal is BRD_CLK1_I;
+   attribute LOC        of rs232_tx_o  : signal is BRD_TX_O;
+   attribute IOSTANDARD of rs232_tx_o  : signal is IOSTD;
+   attribute LOC        of rs232_rx_i  : signal is BRD_RX_I;
+   attribute IOSTANDARD of rs232_rx_i  : signal is IOSTD;
+end entity DMIPS_Small1;
+
+architecture FPGA of DMIPS_Small1 is
+   component ZPU_Small1 is
+      generic(
+         WORD_SIZE  : natural:=32;  -- 32 bits data path
+         D_CARE_VAL : std_logic:='0'; -- Fill value
+         CLK_FREQ   : positive:=50; -- 50 MHz clock
+         BRATE      : positive:=115200; -- RS232 baudrate
+         ADDR_W     : natural:=16;  -- 16 bits address space=64 kB, 32 kB I/O
+         BRAM_W     : natural:=15); -- 15 bits RAM space=32 kB
+      port(
+         clk_i      : in  std_logic;  -- CPU clock
+         rst_i      : in  std_logic;  -- Reset
+         break_o    : out std_logic;  -- Break executed
+         dbg_o      : out zpu_dbgo_t; -- Debug info
+         rs232_tx_o : out std_logic;  -- UART Tx
+         rs232_rx_i : in  std_logic;  -- UART Rx
+         gpio_in    : in  std_logic_vector(31 downto 0);
+         gpio_out   : out std_logic_vector(31 downto 0);
+         gpio_dir   : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
+         );
+   end component ZPU_Small1;
+begin
+   zpu : ZPU_Small1
+      generic map(
+         WORD_SIZE => WORD_SIZE, D_CARE_VAL => D_CARE_VAL,
+         CLK_FREQ => CLK_FREQ, BRATE => BRATE, ADDR_W => ADDR_W,
+         BRAM_W => BRAM_W)
+      port map(
+         clk_i => clk_i, rst_i => rst_i, rs232_tx_o => rs232_tx_o,
+         rs232_rx_i => rs232_rx_i, dbg_o => open, gpio_in => (others => '0'));
+end architecture FPGA; -- Entity: DMIPS_Small1
+
diff --git a/zpu/hdl/zealot/fpga/hello_med1.vhdl b/zpu/hdl/zealot/fpga/hello_med1.vhdl
new file mode 100644
index 0000000..5ffea1f
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/hello_med1.vhdl
@@ -0,0 +1,119 @@
+------------------------------------------------------------------------------
+----                                                                      ----
+----  ZPU Medium connection to the FPGA pins                              ----
+----                                                                      ----
+----  http://www.opencores.org/                                           ----
+----                                                                      ----
+----  Description:                                                        ----
+----  This module connects the ZPU_Med1 (zpu_med1.vhdl) core to a Spartan ----
+----  3 1500 Xilinx FPGA available in the GR-XC3S board from Pender.      ----
+----                                                                      ----
+----  To Do:                                                              ----
+----  -                                                                   ----
+----                                                                      ----
+----  Author:                                                             ----
+----    - Salvador E. Tropea, salvador inti.gob.ar                        ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar>         ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial       ----
+----                                                                      ----
+---- Distributed under the GPL license                                    ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Design unit:      Hello_Med1(FPGA) (Entity and architecture)         ----
+---- File name:        hello_med1.vhdl                                    ----
+---- Note:             None                                               ----
+---- Limitations:      None known                                         ----
+---- Errors:           None known                                         ----
+---- Library:          work                                               ----
+---- Dependencies:     IEEE.std_logic_1164                                ----
+----                   IEEE.numeric_std                                   ----
+----                   zpu.zpu_pkg                                        ----
+---- Target FPGA:      Spartan 3 (XC3S1500-4-FG456)                       ----
+---- Language:         VHDL                                               ----
+---- Wishbone:         No                                                 ----
+---- Synthesis tools:  Xilinx Release 9.2.03i - xst J.39                  ----
+---- Simulation tools: N/A                                                ----
+---- Text editor:      SETEdit 0.5.x                                      ----
+----                                                                      ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library zpu;
+use zpu.zpupkg.all;
+
+entity Hello_Med1 is
+   generic(
+      WORD_SIZE  : natural:=32;  -- 32 bits data path
+      D_CARE_VAL : std_logic:='0'; -- Fill value, I got better results with it
+      CLK_FREQ   : positive:=50; -- 50 MHz clock
+      BRATE      : positive:=115200; -- RS-232 baudrate
+      ADDR_W     : natural:=18;  -- 18 bits address space=256 kB, 128 kB I/O
+      BRAM_W     : natural:=14); -- 14 bits RAM space=16 kB
+   port(
+      clk_i      : in  std_logic;  -- CPU clock
+      rst_i      : in  std_logic;  -- Reset
+      rs232_tx_o : out std_logic;  -- UART Tx
+      rs232_rx_i : in  std_logic); -- UART Rx
+
+   constant BRD_PB1_I      : string:="D19";  -- SWITCH8==S2
+   constant BRD_CLK1_I     : string:="AA12"; -- 50 MHz clock
+   --constant BRD_CLK1_I     : string:="AB12"; -- 40 MHz clock
+   -- UART: direct 1:1 cable
+   constant BRD_TX_O       : string:="L4"; -- UART 1 (J1) TXD1 DB9 pin 2
+   constant BRD_RX_I       : string:="L3"; -- UART 1 (J1) RXD1 DB9 pin 3
+
+   ------------
+   -- Pinout --
+   ------------
+   attribute LOC        : string;
+   attribute IOSTANDARD : string;
+   constant  IOSTD      : string:="LVTTL";
+
+   attribute LOC        of rst_i       : signal is BRD_PB1_I;
+   attribute IOSTANDARD of rst_i       : signal is IOSTD;
+   attribute LOC        of clk_i       : signal is BRD_CLK1_I;
+   attribute LOC        of rs232_tx_o  : signal is BRD_TX_O;
+   attribute IOSTANDARD of rs232_tx_o  : signal is IOSTD;
+   attribute LOC        of rs232_rx_i  : signal is BRD_RX_I;
+   attribute IOSTANDARD of rs232_rx_i  : signal is IOSTD;
+end entity Hello_Med1;
+
+architecture FPGA of Hello_Med1 is
+   component ZPU_Med1 is
+      generic(
+         WORD_SIZE  : natural:=32;  -- 32 bits data path
+         D_CARE_VAL : std_logic:='X'; -- Fill value
+         CLK_FREQ   : positive:=50; -- 50 MHz clock
+         BRATE      : positive:=9600; -- RS232 baudrate
+         ADDR_W     : natural:=18;  -- 18 bits address space=256 kB, 128 kB I/O
+         BRAM_W     : natural:=15); -- 15 bits RAM space=32 kB
+      port(
+         clk_i      : in  std_logic;  -- CPU clock
+         rst_i      : in  std_logic;  -- Reset
+         break_o    : out std_logic;  -- Break executed
+         dbg_o      : out zpu_dbgo_t; -- Debug info
+         rs232_tx_o : out std_logic;  -- UART Tx
+         rs232_rx_i : in  std_logic;  -- UART Rx
+         gpio_in    : in  std_logic_vector(31 downto 0);
+         gpio_out   : out std_logic_vector(31 downto 0);
+         gpio_dir   : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
+         );
+   end component ZPU_Med1;
+begin
+   zpu : ZPU_Med1
+      generic map(
+         WORD_SIZE => WORD_SIZE, D_CARE_VAL => D_CARE_VAL,
+         CLK_FREQ => CLK_FREQ, BRATE => BRATE, ADDR_W => ADDR_W,
+         BRAM_W => BRAM_W)
+      port map(
+         clk_i => clk_i, rst_i => rst_i, rs232_tx_o => rs232_tx_o,
+         rs232_rx_i => rs232_rx_i, dbg_o => open, gpio_in => (others => '0'));
+end architecture FPGA; -- Entity: Hello_Med1
+
diff --git a/zpu/hdl/zealot/fpga/hello_small1.vhdl b/zpu/hdl/zealot/fpga/hello_small1.vhdl
new file mode 100644
index 0000000..a7e2c21
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/hello_small1.vhdl
@@ -0,0 +1,120 @@
+------------------------------------------------------------------------------
+----                                                                      ----
+----  ZPU Small connection to the FPGA pins                               ----
+----                                                                      ----
+----  http://www.opencores.org/                                           ----
+----                                                                      ----
+----  Description:                                                        ----
+----  This module connects the ZPU_Small1 (zpu_small1.vhdl) core to a     ----
+----  Spartan 3 1500 Xilinx FPGA available in the GR-XC3S board from      ----
+----  Pender.                                                             ----
+----                                                                      ----
+----  To Do:                                                              ----
+----  -                                                                   ----
+----                                                                      ----
+----  Author:                                                             ----
+----    - Salvador E. Tropea, salvador inti.gob.ar                        ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar>         ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial       ----
+----                                                                      ----
+---- Distributed under the GPL license                                    ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Design unit:      Hello_Small1(FPGA) (Entity and architecture)       ----
+---- File name:        hello_small1.vhdl                                  ----
+---- Note:             None                                               ----
+---- Limitations:      None known                                         ----
+---- Errors:           None known                                         ----
+---- Library:          work                                               ----
+---- Dependencies:     IEEE.std_logic_1164                                ----
+----                   IEEE.numeric_std                                   ----
+----                   zpu.zpu_pkg                                        ----
+---- Target FPGA:      Spartan 3 (XC3S1500-4-FG456)                       ----
+---- Language:         VHDL                                               ----
+---- Wishbone:         No                                                 ----
+---- Synthesis tools:  Xilinx Release 9.2.03i - xst J.39                  ----
+---- Simulation tools: N/A                                                ----
+---- Text editor:      SETEdit 0.5.x                                      ----
+----                                                                      ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library zpu;
+use zpu.zpupkg.all;
+
+entity Hello_Small1 is
+   generic(
+      WORD_SIZE  : natural:=32;  -- 32 bits data path
+      D_CARE_VAL : std_logic:='0'; -- Fill value, I got better results with it
+      CLK_FREQ   : positive:=50; -- 50 MHz clock
+      BRATE      : positive:=115200; -- RS-232 baudrate
+      ADDR_W     : natural:=18;  -- 18 bits address space=256 kB, 128 kB I/O
+      BRAM_W     : natural:=14); -- 14 bits RAM space=16 kB
+   port(
+      clk_i      : in  std_logic;  -- CPU clock
+      rst_i      : in  std_logic;  -- Reset
+      rs232_tx_o : out std_logic;  -- UART Tx
+      rs232_rx_i : in  std_logic); -- UART Rx
+
+   constant BRD_PB1_I      : string:="D19";  -- SWITCH8==S2
+   constant BRD_CLK1_I     : string:="AA12"; -- 50 MHz clock
+   --constant BRD_CLK1_I     : string:="AB12"; -- 40 MHz clock
+   -- UART: direct 1:1 cable
+   constant BRD_TX_O       : string:="L4"; -- UART 1 (J1) TXD1 DB9 pin 2
+   constant BRD_RX_I       : string:="L3"; -- UART 1 (J1) RXD1 DB9 pin 3
+
+   ------------
+   -- Pinout --
+   ------------
+   attribute LOC        : string;
+   attribute IOSTANDARD : string;
+   constant  IOSTD      : string:="LVTTL";
+
+   attribute LOC        of rst_i       : signal is BRD_PB1_I;
+   attribute IOSTANDARD of rst_i       : signal is IOSTD;
+   attribute LOC        of clk_i       : signal is BRD_CLK1_I;
+   attribute LOC        of rs232_tx_o  : signal is BRD_TX_O;
+   attribute IOSTANDARD of rs232_tx_o  : signal is IOSTD;
+   attribute LOC        of rs232_rx_i  : signal is BRD_RX_I;
+   attribute IOSTANDARD of rs232_rx_i  : signal is IOSTD;
+end entity Hello_Small1;
+
+architecture FPGA of Hello_Small1 is
+   component ZPU_Small1 is
+      generic(
+         WORD_SIZE  : natural:=32;  -- 32 bits data path
+         D_CARE_VAL : std_logic:='0'; -- Fill value
+         CLK_FREQ   : positive:=50; -- 50 MHz clock
+         BRATE      : positive:=115200; -- RS232 baudrate
+         ADDR_W     : natural:=16;  -- 16 bits address space=64 kB, 32 kB I/O
+         BRAM_W     : natural:=15); -- 15 bits RAM space=32 kB
+      port(
+         clk_i      : in  std_logic;  -- CPU clock
+         rst_i      : in  std_logic;  -- Reset
+         break_o    : out std_logic;  -- Break executed
+         dbg_o      : out zpu_dbgo_t; -- Debug info
+         rs232_tx_o : out std_logic;  -- UART Tx
+         rs232_rx_i : in  std_logic;  -- UART Rx
+         gpio_in    : in  std_logic_vector(31 downto 0);
+         gpio_out   : out std_logic_vector(31 downto 0);
+         gpio_dir   : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
+         );
+   end component ZPU_Small1;
+begin
+   zpu : ZPU_Small1
+      generic map(
+         WORD_SIZE => WORD_SIZE, D_CARE_VAL => D_CARE_VAL,
+         CLK_FREQ => CLK_FREQ, BRATE => BRATE, ADDR_W => ADDR_W,
+         BRAM_W => BRAM_W)
+      port map(
+         clk_i => clk_i, rst_i => rst_i, rs232_tx_o => rs232_tx_o,
+         rs232_rx_i => rs232_rx_i, dbg_o => open, gpio_in => (others => '0'));
+end architecture FPGA; -- Entity: Hello_Small1
+
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/clean_up.sh b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/clean_up.sh
new file mode 100755
index 0000000..3855f16
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/clean_up.sh
@@ -0,0 +1,16 @@
+#!/bin/sh
+
+# ise build stuff
+rm -rf build
+rm -f top.bit
+
+# modelsim compile stuff
+rm -rf work
+rm -rf zpu
+
+# modelsim simulation stuff
+rm -f vsim.wlf
+rm -f transcript
+rm -f zpu_trace.log
+rm -f zpu_med1_io.log
+rm -f zpu_small1_io.log
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation.sh b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation.sh
new file mode 100755
index 0000000..d525737
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation.sh
@@ -0,0 +1,49 @@
+#!/bin/sh
+
+# need project files:
+#    run.do
+#    wave.do
+
+# need ModelSim tools:
+#    vlib
+#    vcom
+#    vsim
+
+
+echo "###############"
+echo "compile zpu lib"
+echo "###############"
+vlib zpu
+vcom -work zpu ../../roms/hello_dbram.vhdl
+vcom -work zpu ../../roms/hello_bram.vhdl
+#vcom -work zpu ../../roms/dmips_dbram.vhdl
+#vcom -work zpu ../../roms/dmips_bram.vhdl
+
+vcom -work zpu ../../roms/rom_pkg.vhdl
+vcom -work zpu ../../zpu_pkg.vhdl
+vcom -work zpu ../../zpu_small.vhdl
+vcom -work zpu ../../zpu_medium.vhdl
+vcom -work zpu ../../helpers/zpu_small1.vhdl
+vcom -work zpu ../../helpers/zpu_med1.vhdl
+vcom -work zpu ../../devices/txt_util.vhdl
+vcom -work zpu ../../devices/phi_io.vhdl
+vcom -work zpu ../../devices/timer.vhdl
+vcom -work zpu ../../devices/gpio.vhdl
+vcom -work zpu ../../devices/rx_unit.vhdl
+vcom -work zpu ../../devices/tx_unit.vhdl
+vcom -work zpu ../../devices/br_gen.vhdl
+vcom -work zpu ../../devices/trace.vhdl
+
+
+echo "################"
+echo "compile work lib"
+echo "################"
+vlib work
+vcom top.vhd
+vcom top_tb.vhd
+
+
+echo "###################"
+echo "start simulator gui"
+echo "###################"
+vsim -gui top_tb -do simulation_config/run.do
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/run.do b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/run.do
new file mode 100644
index 0000000..0d29e0a
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/run.do
@@ -0,0 +1,2 @@
+do wave.do

+run -all

diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/wave.do b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/wave.do
new file mode 100644
index 0000000..6a3731d
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/wave.do
@@ -0,0 +1,163 @@
+onerror {resume}

+quietly WaveActivateNextPane {} 0

+add wave -noupdate /top_tb/simulation_run

+add wave -noupdate /top_tb/tb_cpu_reset

+add wave -noupdate /top_tb/tb_sysclk_n

+add wave -noupdate /top_tb/tb_sysclk_p

+add wave -noupdate /top_tb/tb_user_clock

+add wave -noupdate -divider <NULL>

+add wave -noupdate /top_tb/top_i0/clk

+add wave -noupdate -divider <NULL>

+add wave -noupdate /top_tb/tb_gpio_button

+add wave -noupdate /top_tb/tb_gpio_header_ls

+add wave -noupdate /top_tb/tb_gpio_led

+add wave -noupdate /top_tb/tb_gpio_switch

+add wave -noupdate -expand -group USB/RS232 /top_tb/tb_usb_1_cts

+add wave -noupdate -expand -group USB/RS232 /top_tb/tb_usb_1_rts

+add wave -noupdate -expand -group USB/RS232 /top_tb/tb_usb_1_rx

+add wave -noupdate -expand -group USB/RS232 /top_tb/tb_usb_1_tx

+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_a

+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_ba

+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_cas_b

+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_ras_b

+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_we_b

+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_cke

+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_clk_n

+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_clk_p

+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_dq

+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_ldm

+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_udm

+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_ldqs_n

+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_ldqs_p

+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_udqs_n

+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_udqs_p

+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_odt

+add wave -noupdate -group {Flash memory} /top_tb/tb_flash_a

+add wave -noupdate -group {Flash memory} /top_tb/tb_flash_d

+add wave -noupdate -group {Flash memory} /top_tb/tb_fpga_d0_din_miso_miso1

+add wave -noupdate -group {Flash memory} /top_tb/tb_fpga_d1_miso2

+add wave -noupdate -group {Flash memory} /top_tb/tb_fpga_d2_miso3

+add wave -noupdate -group {Flash memory} /top_tb/tb_flash_we_b

+add wave -noupdate -group {Flash memory} /top_tb/tb_flash_oe_b

+add wave -noupdate -group {Flash memory} /top_tb/tb_flash_ce_b

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_clk0_m2c_n

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_clk0_m2c_p

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_clk1_m2c_n

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_clk1_m2c_p

+add wave -noupdate -group {FMC connector} /top_tb/tb_iic_scl_main

+add wave -noupdate -group {FMC connector} /top_tb/tb_iic_sda_main

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la00_cc_n

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la00_cc_p

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la01_cc_n

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la01_cc_p

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la02_n

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la02_p

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la03_n

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la03_p

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la04_n

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la04_p

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la05_n

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la05_p

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la06_n

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la06_p

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la07_n

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la07_p

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la08_n

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la08_p

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la09_n

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la09_p

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la10_n

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la10_p

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la11_n

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la11_p

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la12_n

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la12_p

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la13_n

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la13_p

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la14_n

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la14_p

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la15_n

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la15_p

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la16_n

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la16_p

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la17_cc_n

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la17_cc_p

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la18_cc_n

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la18_cc_p

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la19_n

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la19_p

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la20_n

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la20_p

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la21_n

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la21_p

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la22_n

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la22_p

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la23_n

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la23_p

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la24_n

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la24_p

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la25_n

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la25_p

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la26_n

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la26_p

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la27_n

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la27_p

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la28_n

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la28_p

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la29_n

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la29_p

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la30_n

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la30_p

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la31_n

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la31_p

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la32_n

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la32_p

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la33_n

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la33_p

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_prsnt_m2c_l

+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_pwr_good_flash_rst_b

+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_awake

+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_cclk

+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_cmp_clk

+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_cmp_mosi

+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_hswapen

+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_init_b

+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_m0_cmp_miso

+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_m1

+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_mosi_csi_b_miso0

+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_onchip_term1

+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_onchip_term2

+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_vtemp

+add wave -noupdate -group {special FPGA pins} /top_tb/tb_spi_cs_b

+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_col

+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_crs

+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_int

+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_mdc

+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_mdio

+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_reset

+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_rxclk

+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_rxctl_rxdv

+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_rxd

+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_rxer

+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_txclk

+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_txctl_txen

+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_txc_gtxclk

+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_txd

+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_txer

+TreeUpdate [SetDefaultTree]

+WaveRestoreCursors {{Cursor 1} {1393701250 ps} 0} {{Cursor 2} {138750 ps} 0}

+configure wave -namecolwidth 150

+configure wave -valuecolwidth 100

+configure wave -justifyvalue left

+configure wave -signalnamewidth 1

+configure wave -snapdistance 10

+configure wave -datasetprefix 0

+configure wave -rowmargin 4

+configure wave -childrowmargin 2

+configure wave -gridoffset 0

+configure wave -gridperiod 1

+configure wave -griddelta 40

+configure wave -timeline 0

+configure wave -timelineunits ns

+update

+WaveRestoreZoom {0 ps} {327615 ps}

diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis.sh b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis.sh
new file mode 100755
index 0000000..2f89415
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis.sh
@@ -0,0 +1,36 @@
+#!/bin/sh
+
+# need project files:
+#    top.xst
+#    top.prj
+#    top.ut
+
+# need Xilinx tools:
+#    xst
+#    ngdbuild
+#    map
+#    par
+#    trce
+#    bitgen
+
+echo "########################"
+echo "generate build directory"
+echo "########################"
+mkdir build
+cd build 
+mkdir tmp
+
+echo "###############"
+echo "start processes"
+echo "###############"
+xst      -ifn "../synthesis_config/top.xst" -ofn "top.syr" 
+ngdbuild -dd _ngo -nt timestamp -uc ../synthesis_config/xilinx-sp601-xc6slx16.ucf -p xc6slx16-csg324-2 top.ngc top.ngd  
+map      -p xc6slx16-csg324-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o top_map.ncd top.ngd top.pcf 
+par      -ol high -mt off top_map.ncd -w top.ncd top.pcf 
+trce     -v 3 -s 2 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf 
+bitgen   -f ../synthesis_config/top.ut top.ncd 
+
+echo "###########"
+echo "get bitfile"
+echo "###########"
+cp top.bit ..
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.prj b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.prj
new file mode 100644
index 0000000..965ae4c
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.prj
@@ -0,0 +1,19 @@
+vhdl work ../top.vhd

+vhdl zpu ../../../zpu_pkg.vhdl

+vhdl zpu ../../../zpu_small.vhdl

+vhdl zpu ../../../zpu_medium.vhdl

+vhdl zpu ../../../roms/rom_pkg.vhdl

+#vhdl zpu ../../../roms/hello_dbram.vhdl

+#vhdl zpu ../../../roms/hello_bram.vhdl

+vhdl zpu ../../../roms/dmips_dbram.vhdl

+vhdl zpu ../../../roms/dmips_bram.vhdl

+vhdl zpu ../../../helpers/zpu_small1.vhdl

+vhdl zpu ../../../helpers/zpu_med1.vhdl

+vhdl zpu ../../../devices/txt_util.vhdl

+vhdl zpu ../../../devices/phi_io.vhdl

+vhdl zpu ../../../devices/timer.vhdl

+vhdl zpu ../../../devices/gpio.vhdl

+vhdl zpu ../../../devices/rx_unit.vhdl

+vhdl zpu ../../../devices/tx_unit.vhdl

+vhdl zpu ../../../devices/br_gen.vhdl

+vhdl zpu ../../../devices/trace.vhdl

diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.ut b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.ut
new file mode 100644
index 0000000..be56902
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.ut
@@ -0,0 +1,30 @@
+-w

+-g DebugBitstream:No

+-g Binary:no

+-g CRC:Enable

+-g Reset_on_err:No

+-g ConfigRate:2

+-g ProgPin:PullUp

+-g TckPin:PullUp

+-g TdiPin:PullUp

+-g TdoPin:PullUp

+-g TmsPin:PullUp

+-g UnusedPin:PullDown

+-g UserID:0xFFFFFFFF

+-g ExtMasterCclk_en:No

+-g SPI_buswidth:1

+-g TIMER_CFG:0xFFFF

+-g multipin_wakeup:No

+-g StartUpClk:CClk

+-g DONE_cycle:4

+-g GTS_cycle:5

+-g GWE_cycle:6

+-g LCK_cycle:NoWait

+-g Security:None

+-g DonePipe:No

+-g DriveDone:No

+-g en_sw_gsr:No

+-g drive_awake:No

+-g sw_clk:Startupclk

+-g sw_gwe_cycle:5

+-g sw_gts_cycle:4

diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.xst b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.xst
new file mode 100644
index 0000000..ddddddd
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.xst
@@ -0,0 +1,53 @@
+set -tmpdir "tmp"

+set -xsthdpdir "xst"

+run

+-ifn ../synthesis_config/top.prj

+-ifmt mixed

+-ofn top

+-ofmt NGC

+-p xc6slx16-2-csg324

+-top top

+-opt_mode Speed

+-opt_level 1

+-power NO

+-iuc NO

+-keep_hierarchy No

+-netlist_hierarchy As_Optimized

+-rtlview Yes

+-glob_opt AllClockNets

+-read_cores YES

+-write_timing_constraints NO

+-cross_clock_analysis NO

+-hierarchy_separator /

+-bus_delimiter <>

+-case Maintain

+-slice_utilization_ratio 100

+-bram_utilization_ratio 100

+-dsp_utilization_ratio 100

+-lc Auto

+-reduce_control_sets Auto

+-fsm_extract YES -fsm_encoding Auto

+-safe_implementation No

+-fsm_style LUT

+-ram_extract Yes

+-ram_style Auto

+-rom_extract Yes

+-shreg_extract YES

+-rom_style Auto

+-auto_bram_packing NO

+-resource_sharing YES

+-async_to_sync NO

+-shreg_min_size 2

+-use_dsp48 Auto

+-iobuf YES

+-max_fanout 100000

+-bufg 16

+-register_duplication YES

+-register_balancing No

+-optimize_primitives NO

+-use_clock_enable Auto

+-use_sync_set Auto

+-use_sync_reset Auto

+-iob Auto

+-equivalent_register_removal YES

+-slice_utilization_ratio_maxmargin 5

diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/xilinx-sp601-xc6slx16.ucf b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/xilinx-sp601-xc6slx16.ucf
new file mode 100644
index 0000000..a0c60e7
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/xilinx-sp601-xc6slx16.ucf
@@ -0,0 +1,303 @@
+############################################################

+# SPARTAN-6 SP601 Board Constraints File

+#

+# Family:  Spartan6

+# Device:  XC6SLX16

+# Package: CSG324

+# Speed:   -2

+#

+#

+# Bank Voltage

+# Bank 0: 2.5 V

+# Bank 1: 2.5 V

+# Bank 2: 2.5 V

+# Bank 3: 1.8 V

+# VCCAUX: 2.5 V

+

+# following pins are connected to VCC1V8/2:

+# N3, M5, C1

+

+

+############################################################

+## clock/timing constraints

+############################################################

+

+TIMESPEC "TS_SYSCLK"         = PERIOD "SYSCLK" 200 MHz HIGH 50 %;

+TIMESPEC "TS_USER_SMA_CLOCK" = PERIOD "USER_SMA_CLOCK" 50 MHz HIGH 50 %;

+NET "USER_CLOCK"               PERIOD = 27 MHz HIGH 40%;

+

+

+############################################################

+## pin placement constraints

+############################################################

+

+NET "CPU_RESET"        LOC = "N4";

+

+## 128 MB DDR2 Component Memory

+NET "DDR2_A<12>"       LOC ="G6"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_A<11>"       LOC ="D3"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_A<10>"       LOC ="F4"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_A<9>"        LOC ="D1"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_A<8>"        LOC ="D2"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_A<7>"        LOC ="H6"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_A<6>"        LOC ="H3"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_A<5>"        LOC ="H4"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_A<4>"        LOC ="F3"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_A<3>"        LOC ="L7"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_A<2>"        LOC ="H5"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_A<1>"        LOC ="J6"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_A<0>"        LOC ="J7"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_DQ<15>"      LOC ="U1"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_DQ<14>"      LOC ="U2"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_DQ<13>"      LOC ="T1"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_DQ<12>"      LOC ="T2"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_DQ<11>"      LOC ="N1"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_DQ<10>"      LOC ="N2"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_DQ<9>"       LOC ="M1"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_DQ<8>"       LOC ="M3"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_DQ<7>"       LOC ="J1"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_DQ<6>"       LOC ="J3"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_DQ<5>"       LOC ="H1"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_DQ<4>"       LOC ="H2"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_DQ<3>"       LOC ="K1"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_DQ<2>"       LOC ="K2"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_DQ<1>"       LOC ="L1"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_DQ<0>"       LOC ="L2"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_WE_B"        LOC ="E3"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_UDQS_P"      LOC ="P2"; # | IOSTANDARD = DIFF_SSTL18_II;

+NET "DDR2_UDQS_N"      LOC ="P1"; # | IOSTANDARD = DIFF_SSTL18_II;

+NET "DDR2_UDM"         LOC ="K4"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_RAS_B"       LOC ="L5"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_ODT"         LOC ="K6"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_LDQS_P"      LOC ="L4"; # | IOSTANDARD = DIFF_SSTL18_II;

+NET "DDR2_LDQS_N"      LOC ="L3"; # | IOSTANDARD = DIFF_SSTL18_II;

+NET "DDR2_LDM"         LOC ="K3"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_CLK_P"       LOC ="G3"; # | IOSTANDARD = DIFF_SSTL18_II;

+NET "DDR2_CLK_N"       LOC ="G1"; # | IOSTANDARD = DIFF_SSTL18_II;

+NET "DDR2_CKE"         LOC ="H7"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_CAS_B"       LOC ="K5"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_BA<2>"       LOC ="E1"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_BA<1>"       LOC ="F1"; # | IOSTANDARD = SSTL18_II ;

+NET "DDR2_BA<0>"       LOC ="F2"; # | IOSTANDARD = SSTL18_II ;

+

+## Flash Memory

+NET "FLASH_A<0>"       LOC = "K18";

+NET "FLASH_A<1>"       LOC = "K17";

+NET "FLASH_A<2>"       LOC = "J18";

+NET "FLASH_A<3>"       LOC = "J16";

+NET "FLASH_A<4>"       LOC = "G18";

+NET "FLASH_A<5>"       LOC = "G16";

+NET "FLASH_A<6>"       LOC = "H16";

+NET "FLASH_A<7>"       LOC = "H15";

+NET "FLASH_A<8>"       LOC = "H14";

+NET "FLASH_A<9>"       LOC = "H13";

+NET "FLASH_A<10>"      LOC = "F18";

+NET "FLASH_A<11>"      LOC = "F17";

+NET "FLASH_A<12>"      LOC = "K13";

+NET "FLASH_A<13>"      LOC = "K12";

+NET "FLASH_A<14>"      LOC = "E18";

+NET "FLASH_A<15>"      LOC = "E16";

+NET "FLASH_A<16>"      LOC = "G13";

+NET "FLASH_A<17>"      LOC = "H12";

+NET "FLASH_A<18>"      LOC = "D18";

+NET "FLASH_A<19>"      LOC = "D17";

+NET "FLASH_A<20>"      LOC = "G14";

+NET "FLASH_A<21>"      LOC = "F14";

+NET "FLASH_A<22>"      LOC = "C18";

+NET "FLASH_A<23>"      LOC = "C17";

+NET "FLASH_A<24>"      LOC = "F16";

+#NET "FLASH_D<0>"       LOC = "R13" | SLEW = "SLOW" | DRIVE = 2;

+#NET "FLASH_D<1>"       LOC = "T14" | SLEW = "SLOW" | DRIVE = 2;

+#NET "FLASH_D<2>"       LOC = "V14" | SLEW = "SLOW" | DRIVE = 2;

+NET "FLASH_D<3>"       LOC = "U5"  | SLEW = "SLOW" | DRIVE = 2;

+NET "FLASH_D<4>"       LOC = "V5"  | SLEW = "SLOW" | DRIVE = 2;

+NET "FLASH_D<5>"       LOC = "R3"  | SLEW = "SLOW" | DRIVE = 2;

+NET "FLASH_D<6>"       LOC = "T3"  | SLEW = "SLOW" | DRIVE = 2;

+NET "FLASH_D<7>"       LOC = "R5"  | SLEW = "SLOW" | DRIVE = 2;

+NET "FLASH_OE_B"       LOC = "L18";

+NET "FLASH_WE_B"       LOC = "M16";

+NET "FLASH_CE_B"       LOC = "L17";

+

+# FMC-Connector, Bank 0,2 (M2C = Mezzanine to Carrier, C2M = Carrier to Mezzanine)

+NET "FMC_CLK0_M2C_N"            LOC = "A10";

+NET "FMC_CLK0_M2C_P"            LOC = "C10";

+NET "FMC_CLK1_M2C_N"            LOC = "V9" ;

+NET "FMC_CLK1_M2C_P"            LOC = "T9" ;

+NET "FMC_LA00_CC_N"             LOC = "C9" ;

+NET "FMC_LA00_CC_P"             LOC = "D9" ;

+NET "FMC_LA01_CC_N"             LOC = "C11";

+NET "FMC_LA01_CC_P"             LOC = "D11";

+NET "FMC_LA02_N"                LOC = "A15";

+NET "FMC_LA02_P"                LOC = "C15";

+NET "FMC_LA03_N"                LOC = "A13";

+NET "FMC_LA03_P"                LOC = "C13";

+NET "FMC_LA04_N"                LOC = "A16";

+NET "FMC_LA04_P"                LOC = "B16";

+NET "FMC_LA05_N"                LOC = "A14";

+NET "FMC_LA05_P"                LOC = "B14";

+NET "FMC_LA06_N"                LOC = "C12";

+NET "FMC_LA06_P"                LOC = "D12";

+NET "FMC_LA07_N"                LOC = "E8" ;

+NET "FMC_LA07_P"                LOC = "E7" ;

+NET "FMC_LA08_N"                LOC = "E11";

+NET "FMC_LA08_P"                LOC = "F11";

+NET "FMC_LA09_N"                LOC = "F10";

+NET "FMC_LA09_P"                LOC = "G11";

+NET "FMC_LA10_N"                LOC = "C8" ;

+NET "FMC_LA10_P"                LOC = "D8" ;

+NET "FMC_LA11_N"                LOC = "A12";

+NET "FMC_LA11_P"                LOC = "B12";

+NET "FMC_LA12_N"                LOC = "C6" ;

+NET "FMC_LA12_P"                LOC = "D6" ;

+NET "FMC_LA13_N"                LOC = "A11";

+NET "FMC_LA13_P"                LOC = "B11";

+NET "FMC_LA14_N"                LOC = "A2" ;

+NET "FMC_LA14_P"                LOC = "B2" ;

+NET "FMC_LA15_N"                LOC = "F9" ;

+NET "FMC_LA15_P"                LOC = "G9" ;

+NET "FMC_LA16_N"                LOC = "A7" ;

+NET "FMC_LA16_P"                LOC = "C7" ;

+NET "FMC_LA17_CC_N"             LOC = "T8" ;

+NET "FMC_LA17_CC_P"             LOC = "R8" ;

+NET "FMC_LA18_CC_N"             LOC = "T10";

+NET "FMC_LA18_CC_P"             LOC = "R10";

+NET "FMC_LA19_N"                LOC = "P7" ;

+NET "FMC_LA19_P"                LOC = "N6" ;

+NET "FMC_LA20_N"                LOC = "P8" ;

+NET "FMC_LA20_P"                LOC = "N7" ;

+NET "FMC_LA21_N"                LOC = "V4" ;

+NET "FMC_LA21_P"                LOC = "T4" ;

+NET "FMC_LA22_N"                LOC = "T7" ;

+NET "FMC_LA22_P"                LOC = "R7" ;

+NET "FMC_LA23_N"                LOC = "P6" ;

+NET "FMC_LA23_P"                LOC = "N5" ;

+NET "FMC_LA24_N"                LOC = "V8" ;

+NET "FMC_LA24_P"                LOC = "U8" ;

+NET "FMC_LA25_N"                LOC = "N11";

+NET "FMC_LA25_P"                LOC = "M11";

+NET "FMC_LA26_N"                LOC = "V7" ;

+NET "FMC_LA26_P"                LOC = "U7" ;

+NET "FMC_LA27_N"                LOC = "T11";

+NET "FMC_LA27_P"                LOC = "R11";

+NET "FMC_LA28_N"                LOC = "V11";

+NET "FMC_LA28_P"                LOC = "U11";

+NET "FMC_LA29_N"                LOC = "N8" ;

+NET "FMC_LA29_P"                LOC = "M8" ;

+NET "FMC_LA30_N"                LOC = "V12";

+NET "FMC_LA30_P"                LOC = "T12";

+NET "FMC_LA31_N"                LOC = "V6" ;

+NET "FMC_LA31_P"                LOC = "T6" ;

+NET "FMC_LA32_N"                LOC = "V15";

+NET "FMC_LA32_P"                LOC = "U15";

+NET "FMC_LA33_N"                LOC = "N9" ;

+NET "FMC_LA33_P"                LOC = "M10";

+NET "FMC_PRSNT_M2C_L"           LOC = "U13";

+NET "FMC_PWR_GOOD_FLASH_RST_B"  LOC = "B3";

+

+# special FPGA pins

+NET "FPGA_AWAKE"                LOC = "P15"| SLEW = SLOW | DRIVE = 2;

+NET "FPGA_CCLK"                 LOC = "R15";

+NET "FPGA_CMP_CLK"              LOC = "U16";

+NET "FPGA_CMP_MOSI"             LOC = "V16";

+NET "FPGA_D0_DIN_MISO_MISO1"    LOC = "R13" | DRIVE = 4; ## 8 on U17 (thru series R187 100 ohm), 33 on U10, 6 on J12

+NET "FPGA_D1_MISO2"             LOC = "T14" | DRIVE = 4; ## 9 on U17 (thru series R186 100 ohm), 35 on U10, 3 on J12

+NET "FPGA_D2_MISO3"             LOC = "V14" | DRIVE = 4; ## 1 on U17, 38 on U10, 2 on J12

+NET "FPGA_HSWAPEN"              LOC = "D4";

+NET "FPGA_INIT_B"               LOC = "U3" | SLEW = SLOW | DRIVE = 4;

+NET "FPGA_M0_CMP_MISO"          LOC = "T15";

+NET "FPGA_M1"                   LOC = "N12";

+NET "FPGA_MOSI_CSI_B_MISO0"     LOC = "T13" | DRIVE = 4;

+NET "FPGA_ONCHIP_TERM1"         LOC = "L6";

+NET "FPGA_ONCHIP_TERM2"         LOC = "C2";

+NET "FPGA_VTEMP"                LOC = "P3";

+

+## Pushbuttons, Bank 3, external Pulldown

+NET "GPIO_BUTTON<0>"            LOC = "P4" ;

+NET "GPIO_BUTTON<1>"            LOC = "F6" ;

+NET "GPIO_BUTTON<2>"            LOC = "E4" ;

+NET "GPIO_BUTTON<3>"            LOC = "F5" ;

+NET "GPIO_BUTTON*"              TIG;

+

+## 8 Pin GPIO Header J13, Bank 0,1,2

+NET "GPIO_HEADER_LS<0>"         LOC = "N17"| SLEW = SLOW | DRIVE = 4 ;

+NET "GPIO_HEADER_LS<1>"         LOC = "M18"| SLEW = SLOW | DRIVE = 4 ; 

+NET "GPIO_HEADER_LS<2>"         LOC = "A3" | SLEW = SLOW | DRIVE = 4 ;

+NET "GPIO_HEADER_LS<3>"         LOC = "L15"| SLEW = SLOW | DRIVE = 4 ;

+NET "GPIO_HEADER_LS<4>"         LOC = "F15"| SLEW = SLOW | DRIVE = 4 ;

+NET "GPIO_HEADER_LS<5>"         LOC = "B4" | SLEW = SLOW | DRIVE = 4 ;

+NET "GPIO_HEADER_LS<6>"         LOC = "F13"| SLEW = SLOW | DRIVE = 4 ;

+NET "GPIO_HEADER_LS<7>"         LOC = "P12"| SLEW = SLOW | DRIVE = 4 ;

+

+## 4 GPIO LEDs, Bank 0

+NET "GPIO_LED<0>"               LOC = "E13"| SLEW = SLOW | DRIVE = 4 ;

+NET "GPIO_LED<1>"               LOC = "C14"| SLEW = SLOW | DRIVE = 4 ;

+NET "GPIO_LED<2>"               LOC = "C4" | SLEW = SLOW | DRIVE = 4 ;

+NET "GPIO_LED<3>"               LOC = "A4" | SLEW = SLOW | DRIVE = 4 ;

+NET "GPIO_LED*"                 TIG;

+

+## GPIO Dip Switches, Bank 0,2, external Pulldown

+NET "GPIO_SWITCH<0>"            LOC = "D14";

+NET "GPIO_SWITCH<1>"            LOC = "E12";

+NET "GPIO_SWITCH<2>"            LOC = "F12";

+NET "GPIO_SWITCH<3>"            LOC = "V13";

+NET "GPIO_SWITCH*"              TIG;

+

+## IIC Bus

+NET "IIC_SCL_MAIN"              LOC = "P11";

+NET "IIC_SDA_MAIN"              LOC = "N10";

+

+## 10/100/1000 Tri-Speed Ethernet PHY

+NET "PHY_COL"                   LOC = "L14";

+NET "PHY_CRS"                   LOC = "M13";

+NET "PHY_INT"                   LOC = "J13";

+NET "PHY_MDC"                   LOC = "N14" | SLEW = SLOW | DRIVE = 4;

+NET "PHY_MDIO"                  LOC = "P16" | SLEW = SLOW | DRIVE = 4;

+NET "PHY_RESET"                 LOC = "L13";

+NET "PHY_RXCLK"                 LOC = "L16";

+NET "PHY_RXCTL_RXDV"            LOC = "N18";

+NET "PHY_RXD<0>"                LOC = "M14";

+NET "PHY_RXD<1>"                LOC = "U18";

+NET "PHY_RXD<2>"                LOC = "U17";

+NET "PHY_RXD<3>"                LOC = "T18";

+NET "PHY_RXD<4>"                LOC = "T17";

+NET "PHY_RXD<5>"                LOC = "N16";

+NET "PHY_RXD<6>"                LOC = "N15";

+NET "PHY_RXD<7>"                LOC = "P18";

+NET "PHY_RXER"                  LOC = "P17";

+NET "PHY_TXCLK"                 LOC = "B9" ;

+NET "PHY_TXCTL_TXEN"            LOC = "B8"  | SLEW = SLOW | DRIVE = 4;

+NET "PHY_TXC_GTXCLK"            LOC = "A9" ;

+NET "PHY_TXD<0>"                LOC = "F8"  | SLEW = SLOW | DRIVE = 4;

+NET "PHY_TXD<1>"                LOC = "G8"  | SLEW = SLOW | DRIVE = 4;

+NET "PHY_TXD<2>"                LOC = "A6"  | SLEW = SLOW | DRIVE = 4;

+NET "PHY_TXD<3>"                LOC = "B6"  | SLEW = SLOW | DRIVE = 4;

+NET "PHY_TXD<4>"                LOC = "E6"  | SLEW = SLOW | DRIVE = 4;

+NET "PHY_TXD<5>"                LOC = "F7"  | SLEW = SLOW | DRIVE = 4;

+NET "PHY_TXD<6>"                LOC = "A5"  | SLEW = SLOW | DRIVE = 4;

+NET "PHY_TXD<7>"                LOC = "C5"  | SLEW = SLOW | DRIVE = 4;

+NET "PHY_TXER"                  LOC = "A8"  | SLEW = SLOW | DRIVE = 4;

+

+## SPI x4 Flash

+NET "SPI_CS_B"                  LOC = "V3";

+

+## 200 MHz oscillator (differential)

+NET "SYSCLK_N"                  LOC = "K16"| IOSTANDARD = LVDS_33 | TNM_NET = "SYSCLK";

+NET "SYSCLK_P"                  LOC = "K15"| IOSTANDARD = LVDS_33 | TNM_NET = "SYSCLK";

+

+## USB-UART

+## this names are real net names

+NET "USB_1_CTS"                 LOC = "U10"| DRIVE = 4 | SLEW = SLOW;   # RTS output

+NET "USB_1_RTS"                 LOC = "T5" ;                            # CTS input

+NET "USB_1_RX"                  LOC = "L12"| DRIVE = 4 | SLEW = SLOW;   # TX data out

+NET "USB_1_TX"                  LOC = "K14";                            # RX data in

+

+## 27 MHz

+NET "USER_CLOCK"                LOC = "V10"| IOSTANDARD = LVCMOS33 ;

+##

+NET "USER_SMA_CLOCK_N"          LOC = "H18"| TNM_NET = "USER_SMA_CLOCK";

+NET "USER_SMA_CLOCK_P"          LOC = "H17"| TNM_NET = "USER_SMA_CLOCK";

+

+# pins used for voltage termination

+CONFIG PROHIBIT = C1;

+CONFIG PROHIBIT = M5;

+CONFIG PROHIBIT = N3;

diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top.vhd b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top.vhd
new file mode 100644
index 0000000..27d158f
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top.vhd
@@ -0,0 +1,574 @@
+-- top module of

+-- SP601 evaluation board

+--

+-- using following external connections:

+--

+-- cpu_reset (SW9)      reset

+-- LEDs                 output

+-- USB_UART             communication 

+--

+

+

+library ieee;

+use ieee.std_logic_1164.all;

+

+library zpu;

+use zpu.zpupkg.all;                     -- zpu_dbgo_t

+

+library unisim;

+use unisim.vcomponents.ibufgds;

+use unisim.vcomponents.dcm_sp;

+

+

+entity top is

+    port (

+        -- pragma translate_off 

+        stop_simulation          : out   std_logic;

+        -- pragma translate_on 

+        --

+        cpu_reset                : in    std_logic;  -- SW9 pushbutton (active-high)

+        --

+        -- DDR2 memory 128 MB

+        ddr2_a                   : out   std_logic_vector(12 downto 0);

+        ddr2_ba                  : out   std_logic_vector(2 downto 0);

+        ddr2_cas_b               : out   std_logic;

+        ddr2_ras_b               : out   std_logic;

+        ddr2_we_b                : out   std_logic;

+        ddr2_cke                 : out   std_logic;

+        ddr2_clk_n               : out   std_logic;

+        ddr2_clk_p               : out   std_logic;

+        ddr2_dq                  : inout std_logic_vector(15 downto 0);

+        ddr2_ldm                 : out   std_logic;

+        ddr2_udm                 : out   std_logic;

+        ddr2_ldqs_n              : inout std_logic;

+        ddr2_ldqs_p              : inout std_logic;

+        ddr2_udqs_n              : inout std_logic;

+        ddr2_udqs_p              : inout std_logic;

+        ddr2_odt                 : out   std_logic;

+        --                                

+        -- flash memory                        

+        flash_a                  : out   std_logic_vector(24 downto 0);

+        flash_d                  : inout std_logic_vector(7 downto 3);

+        --

+        fpga_d0_din_miso_miso1   : inout std_logic;  -- dual use

+        fpga_d1_miso2            : inout std_logic;  -- dual use

+        fpga_d2_miso3            : inout std_logic;  -- dual use

+        flash_we_b               : out   std_logic;

+        flash_oe_b               : out   std_logic;

+        flash_ce_b               : out   std_logic;

+        --

+        -- FMC connector

+        -- M2C   Mezzanine to Carrier

+        -- C2M   Carrier to Mezzanine

+        fmc_clk0_m2c_n           : in    std_logic;

+        fmc_clk0_m2c_p           : in    std_logic;

+        fmc_clk1_m2c_n           : in    std_logic;

+        fmc_clk1_m2c_p           : in    std_logic;

+        -- IIC addresses:

+        -- M24C08:                 1010100..1010111

+        -- 2kb EEPROM on FMC card: 1010010

+        iic_scl_main             : inout std_logic;

+        iic_sda_main             : inout std_logic;

+        fmc_la00_cc_n            : inout std_logic;

+        fmc_la00_cc_p            : inout std_logic;

+        fmc_la01_cc_n            : inout std_logic;

+        fmc_la01_cc_p            : inout std_logic;

+        fmc_la02_n               : inout std_logic;

+        fmc_la02_p               : inout std_logic;

+        fmc_la03_n               : inout std_logic;

+        fmc_la03_p               : inout std_logic;

+        fmc_la04_n               : inout std_logic;

+        fmc_la04_p               : inout std_logic;

+        fmc_la05_n               : inout std_logic;

+        fmc_la05_p               : inout std_logic;

+        fmc_la06_n               : inout std_logic;

+        fmc_la06_p               : inout std_logic;

+        fmc_la07_n               : inout std_logic;

+        fmc_la07_p               : inout std_logic;

+        fmc_la08_n               : inout std_logic;

+        fmc_la08_p               : inout std_logic;

+        fmc_la09_n               : inout std_logic;

+        fmc_la09_p               : inout std_logic;

+        fmc_la10_n               : inout std_logic;

+        fmc_la10_p               : inout std_logic;

+        fmc_la11_n               : inout std_logic;

+        fmc_la11_p               : inout std_logic;

+        fmc_la12_n               : inout std_logic;

+        fmc_la12_p               : inout std_logic;

+        fmc_la13_n               : inout std_logic;

+        fmc_la13_p               : inout std_logic;

+        fmc_la14_n               : inout std_logic;

+        fmc_la14_p               : inout std_logic;

+        fmc_la15_n               : inout std_logic;

+        fmc_la15_p               : inout std_logic;

+        fmc_la16_n               : inout std_logic;

+        fmc_la16_p               : inout std_logic;

+        fmc_la17_cc_n            : inout std_logic;

+        fmc_la17_cc_p            : inout std_logic;

+        fmc_la18_cc_n            : inout std_logic;

+        fmc_la18_cc_p            : inout std_logic;

+        fmc_la19_n               : inout std_logic;

+        fmc_la19_p               : inout std_logic;

+        fmc_la20_n               : inout std_logic;

+        fmc_la20_p               : inout std_logic;

+        fmc_la21_n               : inout std_logic;

+        fmc_la21_p               : inout std_logic;

+        fmc_la22_n               : inout std_logic;

+        fmc_la22_p               : inout std_logic;

+        fmc_la23_n               : inout std_logic;

+        fmc_la23_p               : inout std_logic;

+        fmc_la24_n               : inout std_logic;

+        fmc_la24_p               : inout std_logic;

+        fmc_la25_n               : inout std_logic;

+        fmc_la25_p               : inout std_logic;

+        fmc_la26_n               : inout std_logic;

+        fmc_la26_p               : inout std_logic;

+        fmc_la27_n               : inout std_logic;

+        fmc_la27_p               : inout std_logic;

+        fmc_la28_n               : inout std_logic;

+        fmc_la28_p               : inout std_logic;

+        fmc_la29_n               : inout std_logic;

+        fmc_la29_p               : inout std_logic;

+        fmc_la30_n               : inout std_logic;

+        fmc_la30_p               : inout std_logic;

+        fmc_la31_n               : inout std_logic;

+        fmc_la31_p               : inout std_logic;

+        fmc_la32_n               : inout std_logic;

+        fmc_la32_p               : inout std_logic;

+        fmc_la33_n               : inout std_logic;

+        fmc_la33_p               : inout std_logic;

+        fmc_prsnt_m2c_l          : in    std_logic;

+        fmc_pwr_good_flash_rst_b : out   std_logic;  -- multiple destinations: 1 of Q2 (LED DS1 driver), U1 AB2 FPGA_PROG (through series R260 DNP), 44 of U25

+        --

+        fpga_awake               : out   std_logic;

+        fpga_cclk                : out   std_logic;

+        fpga_cmp_clk             : in    std_logic;

+        fpga_cmp_mosi            : in    std_logic;

+        --

+        fpga_hswapen             : in    std_logic;

+        fpga_init_b              : out   std_logic;  -- low active

+        fpga_m0_cmp_miso         : in    std_logic;  -- mode DIP switch SW1 active high

+        fpga_m1                  : in    std_logic;  -- mode DIP switch SW1 active high

+        fpga_mosi_csi_b_miso0    : inout std_logic;

+        fpga_onchip_term1        : inout std_logic;

+        fpga_onchip_term2        : inout std_logic;

+        fpga_vtemp               : in    std_logic;

+        --

+        -- GPIOs

+        gpio_button              : in    std_logic_vector(3 downto 0);  -- active high

+        gpio_header_ls           : inout std_logic_vector(7 downto 0);

+        gpio_led                 : out   std_logic_vector(3 downto 0);

+        gpio_switch              : in    std_logic_vector(3 downto 0);  -- active high

+        --

+        -- Ethernet Gigabit PHY, 

+        -- default settings:

+        -- phy address    = 0b00111

+        -- ANEG[3..0]     = "1111"

+        -- ENA_XC         = 1

+        -- DIS_125        = 1

+        -- HWCFG_MD[3..0] = "1111"

+        -- DIS_FC         = 1

+        -- DIS_SLEEP      = 1

+        -- SEL_BDT        = 0

+        -- INT_POL        = 1

+        -- 75/50Ohm       = 0

+        phy_col                  : in    std_logic;

+        phy_crs                  : in    std_logic;

+        phy_int                  : in    std_logic;

+        phy_mdc                  : out   std_logic;

+        phy_mdio                 : inout std_logic;

+        phy_reset                : out   std_logic;

+        phy_rxclk                : in    std_logic;

+        phy_rxctl_rxdv           : in    std_logic;

+        phy_rxd                  : in    std_logic_vector(7 downto 0);

+        phy_rxer                 : in    std_logic;

+        phy_txclk                : in    std_logic;

+        phy_txctl_txen           : out   std_logic;

+        phy_txc_gtxclk           : out   std_logic;

+        phy_txd                  : out   std_logic_vector(7 downto 0);

+        phy_txer                 : out   std_logic;

+        --

+        --

+        spi_cs_b                 : out   std_logic;

+        --

+        -- 200 MHz oscillator, jitter 50 ppm

+        sysclk_n                 : in    std_logic;

+        sysclk_p                 : in    std_logic;

+        --

+        -- RS232 via USB

+        usb_1_cts                : out   std_logic;  -- function: RTS output

+        usb_1_rts                : in    std_logic;  -- function: CTS input

+        usb_1_rx                 : out   std_logic;  -- function: TX data out

+        usb_1_tx                 : in    std_logic;  -- function: RX data in

+        --

+        --  27 MHz, oscillator socket

+        user_clock               : in    std_logic;

+        --

+        -- user clock provided per SMA

+        user_sma_clock_p         : in    std_logic;

+        user_sma_clock_n         : in    std_logic

+        );

+end entity top;

+

+

+architecture rtl of top is

+

+    ---------------------------

+    -- type declarations

+    type zpu_type is (zpu_small, zpu_medium);

+

+    ---------------------------

+    -- constant declarations

+    constant zpu_flavour   : zpu_type := zpu_medium;  -- choose your flavour HERE

+    --  modify frequency here

+    constant clk_multiply  : positive := 2;  -- 2 for small, 2 for medium

+    constant clk_divide    : positive := 5;  -- 4 for small, 5 for medium

+    --

+    --

+    constant word_size_c   : natural  := 32;  -- 32 bits data path

+    constant addr_w_c      : natural  := 18;  -- 18 bits address space=256 kB, 128 kB I/O

+    --

+    constant clk_frequency : positive := 200; -- input frequency for correct calculation

+

+

+    ---------------------------

+    -- component declarations

+    component zpu_small1 is

+        generic (

+            word_size  : natural   := 32;      -- 32 bits data path

+            d_care_val : std_logic := '0';     -- Fill value

+            clk_freq   : positive  := 50;      -- 50 MHz clock

+            brate      : positive  := 115200;  -- RS232 baudrate

+            addr_w     : natural   := 16;      -- 16 bits address space=64 kB, 32 kB I/O

+            bram_w     : natural   := 15       -- 15 bits RAM space=32 kB

+            );

+        port (

+            clk_i      : in  std_logic;        -- CPU clock

+            rst_i      : in  std_logic;        -- Reset

+            break_o    : out std_logic;        -- Break executed

+            dbg_o      : out zpu_dbgo_t;       -- Debug info

+            rs232_tx_o : out std_logic;        -- UART Tx

+            rs232_rx_i : in  std_logic;        -- UART Rx

+            gpio_in    : in  std_logic_vector(31 downto 0);

+            gpio_out   : out std_logic_vector(31 downto 0);

+            gpio_dir   : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out

+            );

+    end component zpu_small1;

+

+    component zpu_med1 is

+        generic(

+            word_size  : natural   := 32;      -- 32 bits data path

+            d_care_val : std_logic := '0';     -- Fill value

+            clk_freq   : positive  := 50;      -- 50 MHz clock

+            brate      : positive  := 115200;  -- RS232 baudrate

+            addr_w     : natural   := 18;      -- 18 bits address space=256 kB, 128 kB I/O

+            bram_w     : natural   := 15       -- 15 bits RAM space=32 kB

+            );

+        port(

+            clk_i      : in  std_logic;        -- CPU clock

+            rst_i      : in  std_logic;        -- Reset

+            break_o    : out std_logic;        -- Break executed

+            dbg_o      : out zpu_dbgo_t;       -- Debug info

+            rs232_tx_o : out std_logic;        -- UART Tx

+            rs232_rx_i : in  std_logic;        -- UART Rx

+            gpio_in    : in  std_logic_vector(31 downto 0);

+            gpio_out   : out std_logic_vector(31 downto 0);

+            gpio_dir   : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out

+            );

+    end component zpu_med1;

+

+

+

+    ---------------------------

+    -- signal declarations

+    signal sys_clk           : std_ulogic;

+    signal dcm_sp_i0_clk0    : std_ulogic;

+    signal dcm_sp_i0_clkfx   : std_ulogic;

+    signal clk_fb            : std_ulogic;

+    signal clk               : std_ulogic;

+    --

+    signal reset_shift_reg   : std_ulogic_vector(3 downto 0);

+    signal reset_sync        : std_ulogic;

+    --

+    signal zpu_i0_dbg        : zpu_dbgo_t;  -- Debug info

+    signal zpu_i0_break      : std_logic;

+    --

+    signal gpio_in           : std_logic_vector(31 downto 0) := (others => '0');

+    signal zpu_i0_gpio_out   : std_logic_vector(31 downto 0);

+    signal zpu_i0_gpio_dir   : std_logic_vector(31 downto 0);

+

+

+begin

+

+    -- default output drivers

+    -- to pass bitgen DRC 

+    -- outputs used by design are commented

+    --

+    ddr2_a                   <= (others => '1');

+    ddr2_ba                  <= (others => '1');

+    ddr2_cas_b               <= '1';

+    ddr2_ras_b               <= '1';

+    ddr2_we_b                <= '1';

+    ddr2_cke                 <= '0';

+    ddr2_clk_n               <= '0';

+    ddr2_clk_p               <= '1';

+    ddr2_dq                  <= (others => 'Z');

+    ddr2_ldm                 <= '0';

+    ddr2_udm                 <= '0';

+    ddr2_ldqs_n              <= 'Z';

+    ddr2_ldqs_p              <= 'Z';

+    ddr2_udqs_n              <= 'Z';

+    ddr2_udqs_p              <= 'Z';

+    ddr2_odt                 <= '1';

+    --

+    flash_a                  <= (others => '1');

+    flash_d                  <= (others => 'Z');

+    flash_we_b               <= '1';

+    flash_oe_b               <= '1';

+    flash_ce_b               <= '1';

+    --

+    fpga_d0_din_miso_miso1   <= 'Z';

+    fpga_d1_miso2            <= 'Z';

+    fpga_d2_miso3            <= 'Z';

+    --

+    iic_scl_main             <= 'Z';

+    iic_sda_main             <= 'Z';

+    fmc_la00_cc_n            <= 'Z';

+    fmc_la00_cc_p            <= 'Z';

+    fmc_la01_cc_n            <= 'Z';

+    fmc_la01_cc_p            <= 'Z';

+    fmc_la02_n               <= 'Z';

+    fmc_la02_p               <= 'Z';

+    fmc_la03_n               <= 'Z';

+    fmc_la03_p               <= 'Z';

+    fmc_la04_n               <= 'Z';

+    fmc_la04_p               <= 'Z';

+    fmc_la05_n               <= 'Z';

+    fmc_la05_p               <= 'Z';

+    fmc_la06_n               <= 'Z';

+    fmc_la06_p               <= 'Z';

+    fmc_la07_n               <= 'Z';

+    fmc_la07_p               <= 'Z';

+    fmc_la08_n               <= 'Z';

+    fmc_la08_p               <= 'Z';

+    fmc_la09_n               <= 'Z';

+    fmc_la09_p               <= 'Z';

+    fmc_la10_n               <= 'Z';

+    fmc_la10_p               <= 'Z';

+    fmc_la11_n               <= 'Z';

+    fmc_la11_p               <= 'Z';

+    fmc_la12_n               <= 'Z';

+    fmc_la12_p               <= 'Z';

+    fmc_la13_n               <= 'Z';

+    fmc_la13_p               <= 'Z';

+    fmc_la14_n               <= 'Z';

+    fmc_la14_p               <= 'Z';

+    fmc_la15_n               <= 'Z';

+    fmc_la15_p               <= 'Z';

+    fmc_la16_n               <= 'Z';

+    fmc_la16_p               <= 'Z';

+    fmc_la17_cc_n            <= 'Z';

+    fmc_la17_cc_p            <= 'Z';

+    fmc_la18_cc_n            <= 'Z';

+    fmc_la18_cc_p            <= 'Z';

+    fmc_la19_n               <= 'Z';

+    fmc_la19_p               <= 'Z';

+    fmc_la20_n               <= 'Z';

+    fmc_la20_p               <= 'Z';

+    fmc_la21_n               <= 'Z';

+    fmc_la21_p               <= 'Z';

+    fmc_la22_n               <= 'Z';

+    fmc_la22_p               <= 'Z';

+    fmc_la23_n               <= 'Z';

+    fmc_la23_p               <= 'Z';

+    fmc_la24_n               <= 'Z';

+    fmc_la24_p               <= 'Z';

+    fmc_la25_n               <= 'Z';

+    fmc_la25_p               <= 'Z';

+    fmc_la26_n               <= 'Z';

+    fmc_la26_p               <= 'Z';

+    fmc_la27_n               <= 'Z';

+    fmc_la27_p               <= 'Z';

+    fmc_la28_n               <= 'Z';

+    fmc_la28_p               <= 'Z';

+    fmc_la29_n               <= 'Z';

+    fmc_la29_p               <= 'Z';

+    fmc_la30_n               <= 'Z';

+    fmc_la30_p               <= 'Z';

+    fmc_la31_n               <= 'Z';

+    fmc_la31_p               <= 'Z';

+    fmc_la32_n               <= 'Z';

+    fmc_la32_p               <= 'Z';

+    fmc_la33_n               <= 'Z';

+    fmc_la33_p               <= 'Z';

+    fmc_pwr_good_flash_rst_b <= '1';

+    --

+    fpga_awake               <= '1';

+    fpga_cclk                <= '1';    -- SPI clk

+    fpga_init_b              <= '1';

+    fpga_mosi_csi_b_miso0    <= 'Z';

+    fpga_onchip_term1        <= 'Z';

+    fpga_onchip_term2        <= 'Z';

+    --

+    --gpio_led               <= (others => '0'); 

+    --gpio_header_ls         <= (others => 'Z');

+    --

+    phy_mdc                  <= '0';

+    phy_mdio                 <= 'Z';

+    phy_reset                <= '0';

+    phy_txc_gtxclk           <= '0';

+    phy_txctl_txen           <= '0';

+    phy_txd                  <= (others => '1');

+    phy_txer                 <= '0';

+    --

+    spi_cs_b                 <= '1';

+    --

+    --usb_1_rx               <= '1';    -- function: TX data out

+    usb_1_cts                <= '1';    -- function: RTS

+

+

+    -- global differential input buffer 

+    ibufgds_i0 : ibufgds

+        generic map (

+            diff_term => true

+            )

+        port map (

+            i  => sysclk_p,

+            ib => sysclk_n,

+            o  => sys_clk

+            );

+

+    -- digital clock manager (DCM)

+    -- to generate higher/other system clock frequencys

+    dcm_sp_i0 : dcm_sp

+        generic map (

+            startup_wait   => true,     -- wait with DONE till locked

+            clkfx_multiply => clk_multiply,        

+            clkfx_divide   => clk_divide,        

+            clk_feedback   => "1X"

+            )

+        port map (

+            clkin => sys_clk,

+            clk0  => dcm_sp_i0_clk0,

+            clkfx => dcm_sp_i0_clkfx,

+            clkfb => clk_fb

+            );

+

+    clk_fb <= dcm_sp_i0_clk0;

+    clk    <= dcm_sp_i0_clkfx;

+

+

+    -- reset synchronizer

+    -- generate synchronous reset

+    reset_synchronizer : process(clk, cpu_reset)

+    begin

+        if cpu_reset = '1' then

+            reset_shift_reg <= (others => '1');

+        elsif rising_edge(clk) then

+            reset_shift_reg <= reset_shift_reg(reset_shift_reg'high-1 downto 0) & '0';

+        end if;

+    end process;

+    reset_sync <= reset_shift_reg(reset_shift_reg'high);

+

+

+

+    -- select instance of zpu

+    zpu_i0_small: if zpu_flavour = zpu_small generate

+        zpu_i0 : zpu_small1

+            generic map (

+                addr_w    => addr_w_c,

+                word_size => word_size_c,

+                clk_freq  => clk_frequency * clk_multiply / clk_divide

+                )

+            port map (

+                clk_i      => clk,             -- : in  std_logic;   -- CPU clock

+                rst_i      => reset_sync,      -- : in  std_logic;   -- Reset

+                break_o    => zpu_i0_break,    -- : out std_logic;   -- Break executed

+                dbg_o      => zpu_i0_dbg,      -- : out zpu_dbgo_t;  -- Debug info

+                rs232_tx_o => usb_1_rx,        -- : out std_logic;   -- UART Tx

+                rs232_rx_i => usb_1_tx,        -- : in  std_logic    -- UART Rx

+                gpio_in    => gpio_in,         -- : in  std_logic_vector(31 downto 0);

+                gpio_out   => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);

+                gpio_dir   => zpu_i0_gpio_dir  -- : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out

+                );

+    end generate zpu_i0_small;

+

+    zpu_i0_medium: if zpu_flavour = zpu_medium generate

+        zpu_i0 : zpu_med1

+            generic map (

+                addr_w    => addr_w_c,

+                word_size => word_size_c,

+                clk_freq  => clk_frequency * clk_multiply / clk_divide

+                )

+            port map (

+                clk_i      => clk,             -- : in  std_logic;   -- CPU clock

+                rst_i      => reset_sync,      -- : in  std_logic;   -- Reset

+                break_o    => zpu_i0_break,    -- : out std_logic;   -- Break executed

+                dbg_o      => zpu_i0_dbg,      -- : out zpu_dbgo_t;  -- Debug info

+                rs232_tx_o => usb_1_rx,        -- : out std_logic;   -- UART Tx

+                rs232_rx_i => usb_1_tx,        -- : in  std_logic    -- UART Rx

+                gpio_in    => gpio_in,         -- : in  std_logic_vector(31 downto 0);

+                gpio_out   => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);

+                gpio_dir   => zpu_i0_gpio_dir  -- : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out

+                );

+    end generate zpu_i0_medium;

+

+

+    -- pragma translate_off 

+    stop_simulation <= zpu_i0_break; -- abort() causes to stop the simulation

+

+ 

+

+    trace_mod : trace

+        generic map (

+            addr_w    => addr_w_c,

+            word_size => word_size_c,

+            log_file  => "zpu_trace.log"

+            )

+        port map (

+            clk_i  => clk,

+            dbg_i  => zpu_i0_dbg,

+            stop_i => zpu_i0_break,

+            busy_i => '0'

+            );

+    -- pragma translate_on

+

+    -- assign GPIOs

+    --

+    -- bit   31 30 29 28 27 26 25 24  23 22 21 20 19 18 17 16  

+    --

+    --  in   -- -- -- -- -- -- -- --  gpio_header_ls(7.....0)  

+    -- out   -- -- -- -- -- -- -- --  gpio_header_ls(7.....0)  

+    --

+    -- bit   15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0

+    --                                                       

+    --  in   -- -- -- -- switch(3.0)  -- -- -- -- button(3.0)

+    -- out   -- -- -- -- -- -- -- --  gpio_led(7...........0)

+    --

+    gpio_in(23 downto 16) <= gpio_header_ls;

+    gpio_in(11 downto  8) <= gpio_switch;

+    gpio_in( 3 downto  0) <= gpio_button;

+

+    -- 3-state buffers for header_ls

+    gpio_header_ls(7) <= zpu_i0_gpio_out(23) when zpu_i0_gpio_dir(23) = '0' else 'Z';

+    gpio_header_ls(6) <= zpu_i0_gpio_out(22) when zpu_i0_gpio_dir(22) = '0' else 'Z';

+    gpio_header_ls(5) <= zpu_i0_gpio_out(21) when zpu_i0_gpio_dir(21) = '0' else 'Z';

+    gpio_header_ls(4) <= zpu_i0_gpio_out(20) when zpu_i0_gpio_dir(20) = '0' else 'Z';

+    gpio_header_ls(3) <= zpu_i0_gpio_out(19) when zpu_i0_gpio_dir(19) = '0' else 'Z';

+    gpio_header_ls(2) <= zpu_i0_gpio_out(18) when zpu_i0_gpio_dir(18) = '0' else 'Z';

+    gpio_header_ls(1) <= zpu_i0_gpio_out(17) when zpu_i0_gpio_dir(17) = '0' else 'Z';

+    gpio_header_ls(0) <= zpu_i0_gpio_out(16) when zpu_i0_gpio_dir(16) = '0' else 'Z';

+

+    -- switch on all LEDs in case of break

+    process

+    begin

+        wait until rising_edge(clk);

+        gpio_led <= zpu_i0_gpio_out(3 downto 0); 

+        if zpu_i0_break = '1' then

+            gpio_led <= (others => '1');

+        end if;

+    end process;

+

+

+

+end architecture rtl;

diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top_tb.vhd b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top_tb.vhd
new file mode 100644
index 0000000..f089f29
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top_tb.vhd
@@ -0,0 +1,402 @@
+-- testbench for

+-- SP601 evaluation board

+--

+-- includes "model" for clock generation

+-- simulate press on cpu_reset as reset

+--

+-- place models for external components (PHY, DDR2) in this file

+--

+

+

+library ieee;

+use ieee.std_logic_1164.all;

+

+

+entity top_tb is

+end entity top_tb;

+

+architecture testbench of top_tb is

+

+    ---------------------------

+    -- constant declarations

+    constant sys_clk_period  : time := 1 sec / 200_000_000;  -- 200 MHz

+    constant user_clk_period : time := 1 sec / 27_000_000;   -- 27 MHz

+

+

+    ---------------------------

+    -- signal declarations

+    signal simulation_run              : boolean                      := true;

+    signal tb_stop_simulation          : std_logic;

+    --

+    signal tb_cpu_reset                : std_logic;  -- SW9 pushbutton (active-high)

+    --

+    -- DDR2 memory 128 MB

+    signal tb_ddr2_a                   : std_logic_vector(12 downto 0);

+    signal tb_ddr2_ba                  : std_logic_vector(2 downto 0);

+    signal tb_ddr2_cas_b               : std_logic;

+    signal tb_ddr2_ras_b               : std_logic;

+    signal tb_ddr2_we_b                : std_logic;

+    signal tb_ddr2_cke                 : std_logic;

+    signal tb_ddr2_clk_n               : std_logic;

+    signal tb_ddr2_clk_p               : std_logic;

+    signal tb_ddr2_dq                  : std_logic_vector(15 downto 0);

+    signal tb_ddr2_ldm                 : std_logic;

+    signal tb_ddr2_udm                 : std_logic;

+    signal tb_ddr2_ldqs_n              : std_logic;

+    signal tb_ddr2_ldqs_p              : std_logic;

+    signal tb_ddr2_udqs_n              : std_logic;

+    signal tb_ddr2_udqs_p              : std_logic;

+    signal tb_ddr2_odt                 : std_logic;

+    --                                

+    -- flash memory                        

+    signal tb_flash_a                  : std_logic_vector(24 downto 0);

+    signal tb_flash_d                  : std_logic_vector(7 downto 3);

+    signal tb_fpga_d0_din_miso_miso1   : std_logic;  -- dual use

+    signal tb_fpga_d1_miso2            : std_logic;  -- dual use

+    signal tb_fpga_d2_miso3            : std_logic;  -- dual use

+    signal tb_flash_we_b               : std_logic;

+    signal tb_flash_oe_b               : std_logic;

+    signal tb_flash_ce_b               : std_logic;

+    --

+    -- FMC connector

+    -- M2C   Mezzanine to Carrier

+    -- C2M   Carrier to Mezzanine

+    signal tb_fmc_clk0_m2c_n           : std_logic                    := '1';

+    signal tb_fmc_clk0_m2c_p           : std_logic                    := '0';

+    signal tb_fmc_clk1_m2c_n           : std_logic                    := '1';

+    signal tb_fmc_clk1_m2c_p           : std_logic                    := '0';

+    -- IIC addresses:

+    -- M24C08:                 1010100..1010111

+    -- 2kb EEPROM on FMC card: 1010010

+    signal tb_iic_scl_main             : std_logic;

+    signal tb_iic_sda_main             : std_logic;

+    signal tb_fmc_la00_cc_n            : std_logic;

+    signal tb_fmc_la00_cc_p            : std_logic;

+    signal tb_fmc_la01_cc_n            : std_logic;

+    signal tb_fmc_la01_cc_p            : std_logic;

+    signal tb_fmc_la02_n               : std_logic;

+    signal tb_fmc_la02_p               : std_logic;

+    signal tb_fmc_la03_n               : std_logic;

+    signal tb_fmc_la03_p               : std_logic;

+    signal tb_fmc_la04_n               : std_logic;

+    signal tb_fmc_la04_p               : std_logic;

+    signal tb_fmc_la05_n               : std_logic;

+    signal tb_fmc_la05_p               : std_logic;

+    signal tb_fmc_la06_n               : std_logic;

+    signal tb_fmc_la06_p               : std_logic;

+    signal tb_fmc_la07_n               : std_logic;

+    signal tb_fmc_la07_p               : std_logic;

+    signal tb_fmc_la08_n               : std_logic;

+    signal tb_fmc_la08_p               : std_logic;

+    signal tb_fmc_la09_n               : std_logic;

+    signal tb_fmc_la09_p               : std_logic;

+    signal tb_fmc_la10_n               : std_logic;

+    signal tb_fmc_la10_p               : std_logic;

+    signal tb_fmc_la11_n               : std_logic;

+    signal tb_fmc_la11_p               : std_logic;

+    signal tb_fmc_la12_n               : std_logic;

+    signal tb_fmc_la12_p               : std_logic;

+    signal tb_fmc_la13_n               : std_logic;

+    signal tb_fmc_la13_p               : std_logic;

+    signal tb_fmc_la14_n               : std_logic;

+    signal tb_fmc_la14_p               : std_logic;

+    signal tb_fmc_la15_n               : std_logic;

+    signal tb_fmc_la15_p               : std_logic;

+    signal tb_fmc_la16_n               : std_logic;

+    signal tb_fmc_la16_p               : std_logic;

+    signal tb_fmc_la17_cc_n            : std_logic;

+    signal tb_fmc_la17_cc_p            : std_logic;

+    signal tb_fmc_la18_cc_n            : std_logic;

+    signal tb_fmc_la18_cc_p            : std_logic;

+    signal tb_fmc_la19_n               : std_logic;

+    signal tb_fmc_la19_p               : std_logic;

+    signal tb_fmc_la20_n               : std_logic;

+    signal tb_fmc_la20_p               : std_logic;

+    signal tb_fmc_la21_n               : std_logic;

+    signal tb_fmc_la21_p               : std_logic;

+    signal tb_fmc_la22_n               : std_logic;

+    signal tb_fmc_la22_p               : std_logic;

+    signal tb_fmc_la23_n               : std_logic;

+    signal tb_fmc_la23_p               : std_logic;

+    signal tb_fmc_la24_n               : std_logic;

+    signal tb_fmc_la24_p               : std_logic;

+    signal tb_fmc_la25_n               : std_logic;

+    signal tb_fmc_la25_p               : std_logic;

+    signal tb_fmc_la26_n               : std_logic;

+    signal tb_fmc_la26_p               : std_logic;

+    signal tb_fmc_la27_n               : std_logic;

+    signal tb_fmc_la27_p               : std_logic;

+    signal tb_fmc_la28_n               : std_logic;

+    signal tb_fmc_la28_p               : std_logic;

+    signal tb_fmc_la29_n               : std_logic;

+    signal tb_fmc_la29_p               : std_logic;

+    signal tb_fmc_la30_n               : std_logic;

+    signal tb_fmc_la30_p               : std_logic;

+    signal tb_fmc_la31_n               : std_logic;

+    signal tb_fmc_la31_p               : std_logic;

+    signal tb_fmc_la32_n               : std_logic;

+    signal tb_fmc_la32_p               : std_logic;

+    signal tb_fmc_la33_n               : std_logic;

+    signal tb_fmc_la33_p               : std_logic;

+    signal tb_fmc_prsnt_m2c_l          : std_logic                    := '0';

+    signal tb_fmc_pwr_good_flash_rst_b : std_logic;  -- multiple destinations: 1 of Q2 (LED DS1 driver), U1 AB2 FPGA_PROG (through series R260 DNP), 44 of U25

+    --

+    signal tb_fpga_awake               : std_logic;

+    signal tb_fpga_cclk                : std_logic;

+    signal tb_fpga_cmp_clk             : std_logic                    := '0';

+    signal tb_fpga_cmp_mosi            : std_logic                    := '0';

+    signal tb_fpga_hswapen             : std_logic                    := '0';

+    signal tb_fpga_init_b              : std_logic;  -- low active

+    signal tb_fpga_m0_cmp_miso         : std_logic                    := '0';  -- mode DIP switch SW1 active high

+    signal tb_fpga_m1                  : std_logic                    := '0';  -- mode DIP switch SW1 active high

+    signal tb_fpga_mosi_csi_b_miso0    : std_logic;

+    signal tb_fpga_onchip_term1        : std_logic;

+    signal tb_fpga_onchip_term2        : std_logic;

+    signal tb_fpga_vtemp               : std_logic                    := '0';

+    --

+    -- GPIOs

+    signal tb_gpio_button              : std_logic_vector(3 downto 0) := (others => '0');  -- active high

+    signal tb_gpio_header_ls           : std_logic_vector(7 downto 0);  -- 

+    signal tb_gpio_led                 : std_logic_vector(3 downto 0);

+    signal tb_gpio_switch              : std_logic_vector(3 downto 0) := (others => '0');  -- active high

+    --

+    -- Ethernet Gigabit PHY 

+    signal tb_phy_col                  : std_logic                    := '0';

+    signal tb_phy_crs                  : std_logic                    := '0';

+    signal tb_phy_int                  : std_logic                    := '0';

+    signal tb_phy_mdc                  : std_logic;

+    signal tb_phy_mdio                 : std_logic;

+    signal tb_phy_reset                : std_logic;

+    signal tb_phy_rxclk                : std_logic                    := '0';

+    signal tb_phy_rxctl_rxdv           : std_logic                    := '0';

+    signal tb_phy_rxd                  : std_logic_vector(7 downto 0);

+    signal tb_phy_rxer                 : std_logic                    := '0';

+    signal tb_phy_txclk                : std_logic                    := '0';

+    signal tb_phy_txctl_txen           : std_logic;

+    signal tb_phy_txc_gtxclk           : std_logic;

+    signal tb_phy_txd                  : std_logic_vector(7 downto 0);

+    signal tb_phy_txer                 : std_logic;

+    --

+    --

+    signal tb_spi_cs_b                 : std_logic;

+    --

+    -- 200 MHz oscillator, jitter 50 ppm

+    signal tb_sysclk_n                 : std_logic                    := '1';

+    signal tb_sysclk_p                 : std_logic                    := '0';

+    --

+    -- RS232 via USB

+    signal tb_usb_1_cts                : std_logic;  -- function: RTS output

+    signal tb_usb_1_rts                : std_logic                    := '0';  -- function: CTS input

+    signal tb_usb_1_rx                 : std_logic;  -- function: TX data out

+    signal tb_usb_1_tx                 : std_logic                    := '0';  -- function: RX data in

+    --

+    --  27 MHz, oscillator socket

+    signal tb_user_clock               : std_logic                    := '0';

+    --

+    -- user clock provided per SMA

+    signal tb_user_sma_clock_p         : std_logic                    := '0';

+    signal tb_user_sma_clock_n         : std_logic                    := '0';

+

+

+

+begin

+

+    -- generate clocks

+    tb_sysclk_p   <= not tb_sysclk_p   after sys_clk_period / 2  when simulation_run;

+    tb_sysclk_n   <= not tb_sysclk_n   after sys_clk_period / 2  when simulation_run;

+    tb_user_clock <= not tb_user_clock after user_clk_period / 2 when simulation_run;

+

+    -- generate reset

+    tb_cpu_reset <= '1', '0' after 6.66 * sys_clk_period;

+

+

+    -- simulate keypress

+    tb_gpio_button(2) <= '0', '1' after 50 us, '0' after 52 us;

+

+    -- dut

+    top_i0 : entity work.top

+        port map (

+            stop_simulation          => tb_stop_simulation,        -- : out   std_logic;

+            --

+            cpu_reset                => tb_cpu_reset,              -- : in    std_logic;

+            --                                                     

+            -- DDR2 memory 128 MB                                  

+            ddr2_a                   => tb_ddr2_a,                 -- : out   std_logic_vector(12 downto 0);

+            ddr2_ba                  => tb_ddr2_ba,                -- : out   std_logic_vector(2 downto 0);

+            ddr2_cas_b               => tb_ddr2_cas_b,             -- : out   std_logic;

+            ddr2_ras_b               => tb_ddr2_ras_b,             -- : out   std_logic;

+            ddr2_we_b                => tb_ddr2_we_b,              -- : out   std_logic;

+            ddr2_cke                 => tb_ddr2_cke,               -- : out   std_logic;

+            ddr2_clk_n               => tb_ddr2_clk_n,             -- : out   std_logic; 

+            ddr2_clk_p               => tb_ddr2_clk_p,             -- : out   std_logic; 

+            ddr2_dq                  => tb_ddr2_dq,                -- : inout std_logic_vector(15 downto 0);

+            ddr2_ldm                 => tb_ddr2_ldm,               -- : out   std_logic;

+            ddr2_udm                 => tb_ddr2_udm,               -- : out   std_logic;

+            ddr2_ldqs_n              => tb_ddr2_ldqs_n,            -- : inout std_logic;

+            ddr2_ldqs_p              => tb_ddr2_ldqs_p,            -- : inout std_logic;

+            ddr2_udqs_n              => tb_ddr2_udqs_n,            -- : inout std_logic;

+            ddr2_udqs_p              => tb_ddr2_udqs_p,            -- : inout std_logic;

+            ddr2_odt                 => tb_ddr2_odt,               -- : out   std_logic;

+            --                                                     

+            -- flash memory                                        

+            flash_a                  => tb_flash_a,                -- : out   std_logic_vector(24 downto 0);

+            flash_d                  => tb_flash_d,                -- : inout std_logic_vector(7  downto 3);

+            --                              --

+            fpga_d0_din_miso_miso1   => tb_fpga_d0_din_miso_miso1, -- : inout std_logic;

+            fpga_d1_miso2            => tb_fpga_d1_miso2,          -- : inout std_logic;

+            fpga_d2_miso3            => tb_fpga_d2_miso3,          -- : inout std_logic;

+            flash_we_b               => tb_flash_we_b,             -- : out   std_logic;

+            flash_oe_b               => tb_flash_oe_b,             -- : out   std_logic;

+            flash_ce_b               => tb_flash_ce_b,             -- : out   std_logic;

+            --

+            -- FMC connector

+            -- M2C   Mezzanine to Carrier

+            -- C2M   Carrier to Mezzanine

+            fmc_clk0_m2c_n           => tb_fmc_clk0_m2c_n,         -- : in    std_logic;

+            fmc_clk0_m2c_p           => tb_fmc_clk0_m2c_p,         -- : in    std_logic;

+            fmc_clk1_m2c_n           => tb_fmc_clk1_m2c_n,         -- : in    std_logic;

+            fmc_clk1_m2c_p           => tb_fmc_clk1_m2c_p,         -- : in    std_logic;

+            iic_scl_main             => tb_iic_scl_main,           -- : inout std_logic;

+            iic_sda_main             => tb_iic_sda_main,           -- : inout std_logic;

+            fmc_la00_cc_n            => tb_fmc_la00_cc_n,          -- : inout std_logic;

+            fmc_la00_cc_p            => tb_fmc_la00_cc_p,          -- : inout std_logic;

+            fmc_la01_cc_n            => tb_fmc_la01_cc_n,          -- : inout std_logic;

+            fmc_la01_cc_p            => tb_fmc_la01_cc_p,          -- : inout std_logic;

+            fmc_la02_n               => tb_fmc_la02_n,             -- : inout std_logic;

+            fmc_la02_p               => tb_fmc_la02_p,             -- : inout std_logic;

+            fmc_la03_n               => tb_fmc_la03_n,             -- : inout std_logic;

+            fmc_la03_p               => tb_fmc_la03_p,             -- : inout std_logic;

+            fmc_la04_n               => tb_fmc_la04_n,             -- : inout std_logic;

+            fmc_la04_p               => tb_fmc_la04_p,             -- : inout std_logic;

+            fmc_la05_n               => tb_fmc_la05_n,             -- : inout std_logic;

+            fmc_la05_p               => tb_fmc_la05_p,             -- : inout std_logic;

+            fmc_la06_n               => tb_fmc_la06_n,             -- : inout std_logic;

+            fmc_la06_p               => tb_fmc_la06_p,             -- : inout std_logic;

+            fmc_la07_n               => tb_fmc_la07_n,             -- : inout std_logic;

+            fmc_la07_p               => tb_fmc_la07_p,             -- : inout std_logic;

+            fmc_la08_n               => tb_fmc_la08_n,             -- : inout std_logic;

+            fmc_la08_p               => tb_fmc_la08_p,             -- : inout std_logic;

+            fmc_la09_n               => tb_fmc_la09_n,             -- : inout std_logic;

+            fmc_la09_p               => tb_fmc_la09_p,             -- : inout std_logic;

+            fmc_la10_n               => tb_fmc_la10_n,             -- : inout std_logic;

+            fmc_la10_p               => tb_fmc_la10_p,             -- : inout std_logic;

+            fmc_la11_n               => tb_fmc_la11_n,             -- : inout std_logic;

+            fmc_la11_p               => tb_fmc_la11_p,             -- : inout std_logic;

+            fmc_la12_n               => tb_fmc_la12_n,             -- : inout std_logic;

+            fmc_la12_p               => tb_fmc_la12_p,             -- : inout std_logic;

+            fmc_la13_n               => tb_fmc_la13_n,             -- : inout std_logic;

+            fmc_la13_p               => tb_fmc_la13_p,             -- : inout std_logic;

+            fmc_la14_n               => tb_fmc_la14_n,             -- : inout std_logic;

+            fmc_la14_p               => tb_fmc_la14_p,             -- : inout std_logic;

+            fmc_la15_n               => tb_fmc_la15_n,             -- : inout std_logic;

+            fmc_la15_p               => tb_fmc_la15_p,             -- : inout std_logic;

+            fmc_la16_n               => tb_fmc_la16_n,             -- : inout std_logic;

+            fmc_la16_p               => tb_fmc_la16_p,             -- : inout std_logic;

+            fmc_la17_cc_n            => tb_fmc_la17_cc_n,          -- : inout std_logic;

+            fmc_la17_cc_p            => tb_fmc_la17_cc_p,          -- : inout std_logic;

+            fmc_la18_cc_n            => tb_fmc_la18_cc_n,          -- : inout std_logic;

+            fmc_la18_cc_p            => tb_fmc_la18_cc_p,          -- : inout std_logic;

+            fmc_la19_n               => tb_fmc_la19_n,             -- : inout std_logic;

+            fmc_la19_p               => tb_fmc_la19_p,             -- : inout std_logic;

+            fmc_la20_n               => tb_fmc_la20_n,             -- : inout std_logic;

+            fmc_la20_p               => tb_fmc_la20_p,             -- : inout std_logic;

+            fmc_la21_n               => tb_fmc_la21_n,             -- : inout std_logic;

+            fmc_la21_p               => tb_fmc_la21_p,             -- : inout std_logic;

+            fmc_la22_n               => tb_fmc_la22_n,             -- : inout std_logic;

+            fmc_la22_p               => tb_fmc_la22_p,             -- : inout std_logic;

+            fmc_la23_n               => tb_fmc_la23_n,             -- : inout std_logic;

+            fmc_la23_p               => tb_fmc_la23_p,             -- : inout std_logic;

+            fmc_la24_n               => tb_fmc_la24_n,             -- : inout std_logic;

+            fmc_la24_p               => tb_fmc_la24_p,             -- : inout std_logic;

+            fmc_la25_n               => tb_fmc_la25_n,             -- : inout std_logic;

+            fmc_la25_p               => tb_fmc_la25_p,             -- : inout std_logic;

+            fmc_la26_n               => tb_fmc_la26_n,             -- : inout std_logic;

+            fmc_la26_p               => tb_fmc_la26_p,             -- : inout std_logic;

+            fmc_la27_n               => tb_fmc_la27_n,             -- : inout std_logic;

+            fmc_la27_p               => tb_fmc_la27_p,             -- : inout std_logic;

+            fmc_la28_n               => tb_fmc_la28_n,             -- : inout std_logic;

+            fmc_la28_p               => tb_fmc_la28_p,             -- : inout std_logic;

+            fmc_la29_n               => tb_fmc_la29_n,             -- : inout std_logic;

+            fmc_la29_p               => tb_fmc_la29_p,             -- : inout std_logic;

+            fmc_la30_n               => tb_fmc_la30_n,             -- : inout std_logic;

+            fmc_la30_p               => tb_fmc_la30_p,             -- : inout std_logic;

+            fmc_la31_n               => tb_fmc_la31_n,             -- : inout std_logic;

+            fmc_la31_p               => tb_fmc_la31_p,             -- : inout std_logic;

+            fmc_la32_n               => tb_fmc_la32_n,             -- : inout std_logic;

+            fmc_la32_p               => tb_fmc_la32_p,             -- : inout std_logic;

+            fmc_la33_n               => tb_fmc_la33_n,             -- : inout std_logic;

+            fmc_la33_p               => tb_fmc_la33_p,             -- : inout std_logic;

+            fmc_prsnt_m2c_l          => tb_fmc_prsnt_m2c_l,        -- : in    std_logic;

+            fmc_pwr_good_flash_rst_b => tb_fmc_pwr_good_flash_rst_b,  -- : out   std_logic;

+            --

+            fpga_awake               => tb_fpga_awake,             -- : out   std_logic;

+            fpga_cclk                => tb_fpga_cclk,              -- : out   std_logic;

+            fpga_cmp_clk             => tb_fpga_cmp_clk,           -- : in    std_logic;

+            fpga_cmp_mosi            => tb_fpga_cmp_mosi,          -- : in    std_logic;

+            --                              --

+            fpga_hswapen             => tb_fpga_hswapen,           -- : in    std_logic;

+            fpga_init_b              => tb_fpga_init_b,            -- : out   std_logic;

+            fpga_m0_cmp_miso         => tb_fpga_m0_cmp_miso,       -- : in    std_logic;

+            fpga_m1                  => tb_fpga_m1,                -- : in    std_logic;

+            fpga_mosi_csi_b_miso0    => tb_fpga_mosi_csi_b_miso0,  -- : inout std_logic;

+            fpga_onchip_term1        => tb_fpga_onchip_term1,      -- : inout std_logic;

+            fpga_onchip_term2        => tb_fpga_onchip_term2,      -- : inout std_logic;

+            fpga_vtemp               => tb_fpga_vtemp,             -- : in    std_logic;

+            --

+            -- GPIOs

+            gpio_button              => tb_gpio_button,            -- : in    std_logic_vector(3 downto 0);

+            gpio_header_ls           => tb_gpio_header_ls,         -- : inout std_logic_vector(7 downto 0);

+            gpio_led                 => tb_gpio_led,               -- : out   std_logic_vector(3 downto 0);

+            gpio_switch              => tb_gpio_switch,            -- : in    std_logic_vector(3 downto 0);

+            --

+            -- Ethernet Gigabit PHY 

+            phy_col                  => tb_phy_col,                -- : in    std_logic;

+            phy_crs                  => tb_phy_crs,                -- : in    std_logic;

+            phy_int                  => tb_phy_int,                -- : in    std_logic;

+            phy_mdc                  => tb_phy_mdc,                -- : out   std_logic;

+            phy_mdio                 => tb_phy_mdio,               -- : inout std_logic;

+            phy_reset                => tb_phy_reset,              -- : out   std_logic;

+            phy_rxclk                => tb_phy_rxclk,              -- : in    std_logic;

+            phy_rxctl_rxdv           => tb_phy_rxctl_rxdv,         -- : in    std_logic;

+            phy_rxd                  => tb_phy_rxd,                -- : in    std_logic_vector(7 downto 0);

+            phy_rxer                 => tb_phy_rxer,               -- : in    std_logic;

+            phy_txclk                => tb_phy_txclk,              -- : in    std_logic;

+            phy_txctl_txen           => tb_phy_txctl_txen,         -- : out   std_logic;

+            phy_txc_gtxclk           => tb_phy_txc_gtxclk,         -- : out   std_logic;

+            phy_txd                  => tb_phy_txd,                -- : out   std_logic_vector(7 downto 0);

+            phy_txer                 => tb_phy_txer,               -- : out   std_logic;

+            --

+            --

+            spi_cs_b                 => tb_spi_cs_b,               -- : out   std_logic;

+            --                                                     

+            -- 200 MHz oscillator, jitter 50 ppm                   

+            sysclk_n                 => tb_sysclk_n,               -- : in    std_logic;

+            sysclk_p                 => tb_sysclk_p,               -- : in    std_logic;

+            --

+            -- RS232 via USB

+            usb_1_cts                => tb_usb_1_cts,              -- : out   std_logic;

+            usb_1_rts                => tb_usb_1_rts,              -- : in    std_logic;

+            usb_1_rx                 => tb_usb_1_rx,               -- : out   std_logic;

+            usb_1_tx                 => tb_usb_1_tx,               -- : in    std_logic;

+            --

+            --  27 MHz, oscillator socket

+            user_clock               => tb_user_clock,             -- : in    std_logic;

+            --

+            -- user clock provided per SMA

+            user_sma_clock_p         => tb_user_sma_clock_p,       -- : in    std_logic;

+            user_sma_clock_n         => tb_user_sma_clock_n        -- : in    std_logic

+            );

+

+

+    -- check for simulation stopping

+    process (tb_stop_simulation)

+    begin

+        if tb_stop_simulation = '1' then

+            report "Simulation end." severity note;

+            simulation_run <= false;

+        end if;

+    end process;

+

+

+end architecture testbench;

+

diff --git a/zpu/hdl/zealot/helpers/zpu_med1.vhdl b/zpu/hdl/zealot/helpers/zpu_med1.vhdl
new file mode 100644
index 0000000..a0cbcb2
--- /dev/null
+++ b/zpu/hdl/zealot/helpers/zpu_med1.vhdl
@@ -0,0 +1,187 @@
+------------------------------------------------------------------------------
+----                                                                      ----
+----  ZPU Medium + PHI I/O + BRAM                                         ----
+----                                                                      ----
+----  http://www.opencores.org/                                           ----
+----                                                                      ----
+----  Description:                                                        ----
+----  ZPU is a 32 bits small stack cpu. This is a helper that joins the   ----
+----  medium version, the PHI I/O basic layout and a program BRAM.        ----
+----                                                                      ----
+----  To Do:                                                              ----
+----  -                                                                   ----
+----                                                                      ----
+----  Author:                                                             ----
+----    - Salvador E. Tropea, salvador inti.gob.ar                        ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar>         ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial       ----
+----                                                                      ----
+---- Distributed under the BSD license                                    ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Design unit:      ZPU_Med1(Structural) (Entity and architecture)     ----
+---- File name:        zpu_med1.vhdl                                      ----
+---- Note:             None                                               ----
+---- Limitations:      None known                                         ----
+---- Errors:           None known                                         ----
+---- Library:          work                                               ----
+---- Dependencies:     IEEE.std_logic_1164                                ----
+----                   IEEE.numeric_std                                   ----
+----                   zpu.zpupkg                                         ----
+----                   work.zpu_memory                                    ----
+---- Target FPGA:      Spartan 3 (XC3S1500-4-FG456)                       ----
+---- Language:         VHDL                                               ----
+---- Wishbone:         No                                                 ----
+---- Synthesis tools:  Xilinx Release 9.2.03i - xst J.39                  ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x)                       ----
+---- Text editor:      SETEdit 0.5.x                                      ----
+----                                                                      ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library zpu;
+use zpu.zpupkg.all;
+
+-- RAM declaration
+library work;
+use work.zpu_memory.all;
+
+entity ZPU_Med1 is
+   generic(
+      WORD_SIZE  : natural:=32;  -- 32 bits data path
+      D_CARE_VAL : std_logic:='X'; -- Fill value
+      CLK_FREQ   : positive:=50; -- 50 MHz clock
+      BRATE      : positive:=9600; -- RS232 baudrate
+      ADDR_W     : natural:=18;  -- 18 bits address space=256 kB, 128 kB I/O
+      BRAM_W     : natural:=15); -- 15 bits RAM space=32 kB
+   port(
+      clk_i      : in  std_logic;  -- CPU clock
+      rst_i      : in  std_logic;  -- Reset
+      break_o    : out std_logic;  -- Break executed
+      dbg_o      : out zpu_dbgo_t; -- Debug info
+      rs232_tx_o : out std_logic;  -- UART Tx
+      rs232_rx_i : in  std_logic;  -- UART Rx
+      gpio_in    : in  std_logic_vector(31 downto 0);
+      gpio_out   : out std_logic_vector(31 downto 0);
+      gpio_dir   : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
+      );
+end entity ZPU_Med1;
+
+architecture Structural of ZPU_Med1 is
+   constant BYTE_BITS  : integer:=WORD_SIZE/16; -- # of bits in a word that addresses bytes
+   constant IO_BIT     : integer:=ADDR_W-1; -- Address bit to determine this is an I/O
+   constant BRDIVISOR  : positive:=CLK_FREQ*1e6/BRATE/4;
+
+   -- I/O & memory (ZPU)
+   signal mem_busy     : std_logic;
+   signal mem_read     : unsigned(WORD_SIZE-1 downto 0);
+   signal mem_write    : unsigned(WORD_SIZE-1 downto 0);
+   signal mem_addr     : unsigned(ADDR_W-1 downto 0);
+   signal mem_we       : std_logic;
+   signal mem_re       : std_logic;
+
+   -- Memory (SinglePort_RAM)
+   signal ram_busy     : std_logic;
+   signal ram_read     : unsigned(WORD_SIZE-1 downto 0);
+   signal ram_addr     : unsigned(BRAM_W-1 downto BYTE_BITS);
+   signal ram_we       : std_logic;
+   signal ram_re       : std_logic;
+   signal ram_ready_r  : std_logic:='0';
+
+   -- I/O (ZPU_IO)
+   signal io_busy      : std_logic;
+   signal io_re        : std_logic;
+   signal io_we        : std_logic;
+   signal io_read      : unsigned(WORD_SIZE-1 downto 0);
+   signal io_ready     : std_logic;
+   signal io_reading_r : std_logic:='0';
+   signal io_addr      : unsigned(2 downto 0);
+begin
+   memory: SinglePortRAM
+      generic map(
+         WORD_SIZE => WORD_SIZE, BYTE_BITS => BYTE_BITS, BRAM_W => BRAM_W)
+      port map(
+         clk_i => clk_i,
+         we_i => ram_we, re_i => ram_re, addr_i => ram_addr,
+         write_i => mem_write, read_o => ram_read, busy_o => ram_busy);
+   ram_addr <= mem_addr(BRAM_W-1 downto BYTE_BITS);
+   ram_we   <= mem_we and not(mem_addr(IO_BIT));
+   ram_re   <= mem_re and not(mem_addr(IO_BIT));
+
+   -- I/O: Phi layout
+   io_map: ZPUPhiIO
+      generic map(
+         BRDIVISOR => BRDIVISOR, 
+         LOG_FILE  => "zpu_med1_io.log"
+         )
+      port map(
+         clk_i      => clk_i, 
+         reset_i    => rst_i, 
+         busy_o     => io_busy, 
+         we_i       => io_we,
+         re_i       => io_re, 
+         data_i     => mem_write, 
+         data_o     => io_read,
+         addr_i     => io_addr, 
+         rs232_rx_i => rs232_rx_i, 
+         rs232_tx_o => rs232_tx_o,
+         br_clk_i   => '1',
+         gpio_in    => gpio_in,
+         gpio_out   => gpio_out,
+         gpio_dir   => gpio_dir
+         );
+   io_addr  <= mem_addr(4 downto 2);
+   -- Here we decode 0x8xxxx as I/O and not just 0x80A00xx
+   -- Note: We define the address space as 256 kB, so writing to 0x80A00xx
+   -- will be as wrting to 0x200xx and hence we decode it as I/O space.
+   io_we    <= mem_we and mem_addr(IO_BIT);
+   io_re    <= mem_re and mem_addr(IO_BIT);
+   io_ready <= (io_reading_r or io_re) and not io_busy;
+
+   zpu : ZPUMediumCore
+      generic map(
+         WORD_SIZE => WORD_SIZE, ADDR_W => ADDR_W, MEM_W => BRAM_W,
+         D_CARE_VAL => D_CARE_VAL)
+      port map(
+         clk_i => clk_i, reset_i => rst_i, enable_i => '1',
+         break_o => break_o, dbg_o => dbg_o,
+         -- Memory
+         mem_busy_i => mem_busy, data_i => mem_read, data_o => mem_write,
+         addr_o => mem_addr, write_en_o => mem_we, read_en_o => mem_re);
+   mem_busy <= io_busy or ram_busy;
+
+   -- Memory reads either come from IO or DRAM. We need to pick the right one.
+   memory_control:
+   process (ram_read, ram_ready_r, io_ready, io_read)
+   begin
+      mem_read <= (others => '0');
+      if ram_ready_r='1' then
+         mem_read <= ram_read;
+      end if;
+      if io_ready='1' then
+         mem_read <= io_read;
+      end if;
+   end process memory_control;
+
+   memory_control_sync:
+   process (clk_i)
+   begin
+      if rising_edge(clk_i) then
+         if rst_i='1' then
+            io_reading_r <= '0';
+            ram_ready_r  <= '0';
+         else
+            io_reading_r <= io_busy or io_re;
+            ram_ready_r  <= ram_re;
+         end if;
+      end if;
+   end process memory_control_sync;
+end architecture Structural; -- Entity: ZPU_Med1
+
diff --git a/zpu/hdl/zealot/helpers/zpu_small1.vhdl b/zpu/hdl/zealot/helpers/zpu_small1.vhdl
new file mode 100644
index 0000000..52006e4
--- /dev/null
+++ b/zpu/hdl/zealot/helpers/zpu_small1.vhdl
@@ -0,0 +1,153 @@
+------------------------------------------------------------------------------
+----                                                                      ----
+----  ZPU Small + PHI I/O + BRAM                                          ----
+----                                                                      ----
+----  http://www.opencores.org/                                           ----
+----                                                                      ----
+----  Description:                                                        ----
+----  ZPU is a 32 bits small stack cpu. This is a helper that joins the   ----
+----  small version, the PHI I/O basic layout and a program BRAM.         ----
+----                                                                      ----
+----  To Do:                                                              ----
+----  -                                                                   ----
+----                                                                      ----
+----  Author:                                                             ----
+----    - Salvador E. Tropea, salvador inti.gob.ar                        ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar>         ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial       ----
+----                                                                      ----
+---- Distributed under the BSD license                                    ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Design unit:      ZPU_Small1(Structural) (Entity and architecture)   ----
+---- File name:        zpu_small1.vhdl                                    ----
+---- Note:             None                                               ----
+---- Limitations:      None known                                         ----
+---- Errors:           None known                                         ----
+---- Library:          work                                               ----
+---- Dependencies:     IEEE.std_logic_1164                                ----
+----                   IEEE.numeric_std                                   ----
+----                   zpu.zpupkg                                         ----
+----                   work.zpu_memory                                    ----
+---- Target FPGA:      Spartan 3 (XC3S1500-4-FG456)                       ----
+---- Language:         VHDL                                               ----
+---- Wishbone:         No                                                 ----
+---- Synthesis tools:  Xilinx Release 9.2.03i - xst J.39                  ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x)                       ----
+---- Text editor:      SETEdit 0.5.x                                      ----
+----                                                                      ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library zpu;
+use zpu.zpupkg.all;
+
+-- RAM declaration
+library work;
+use work.zpu_memory.all;
+
+entity ZPU_Small1 is
+   generic(
+      WORD_SIZE  : natural:=32;  -- 32 bits data path
+      D_CARE_VAL : std_logic:='0'; -- Fill value
+      CLK_FREQ   : positive:=50; -- 50 MHz clock
+      BRATE      : positive:=115200; -- RS232 baudrate
+      ADDR_W     : natural:=16;  -- 16 bits address space=64 kB, 32 kB I/O
+      BRAM_W     : natural:=15); -- 15 bits RAM space=32 kB
+   port(
+      clk_i      : in  std_logic;  -- CPU clock
+      rst_i      : in  std_logic;  -- Reset
+      break_o    : out std_logic;  -- Break executed
+      dbg_o      : out zpu_dbgo_t; -- Debug info
+      rs232_tx_o : out std_logic;  -- UART Tx
+      rs232_rx_i : in  std_logic;  -- UART Rx
+      gpio_in    : in  std_logic_vector(31 downto 0);
+      gpio_out   : out std_logic_vector(31 downto 0);
+      gpio_dir   : out std_logic_vector(31 downto 0)  -- 1 = in, 0 = out
+      );
+end entity ZPU_Small1;
+
+architecture Structural of ZPU_Small1 is
+   constant BYTE_BITS  : integer:=WORD_SIZE/16; -- # of bits in a word that addresses bytes
+   constant IO_BIT     : integer:=ADDR_W-1; -- Address bit to determine this is an I/O
+   constant BRDIVISOR  : positive:=CLK_FREQ*1e6/BRATE/4;
+
+   -- Program+data+stack BRAM
+   -- Port A
+   signal a_we     : std_logic;
+   signal a_addr   : unsigned(BRAM_W-1 downto BYTE_BITS);
+   signal a_write  : unsigned(WORD_SIZE-1 downto 0);
+   signal a_read   : unsigned(WORD_SIZE-1 downto 0);
+   -- Port B
+   signal b_we     : std_logic;
+   signal b_addr   : unsigned(BRAM_W-1 downto BYTE_BITS);
+   signal b_write  : unsigned(WORD_SIZE-1 downto 0);
+   signal b_read   : unsigned(WORD_SIZE-1 downto 0);
+
+   -- I/O space
+   signal io_busy  : std_logic;
+   signal io_write : unsigned(WORD_SIZE-1 downto 0);
+   signal io_read  : unsigned(WORD_SIZE-1 downto 0);
+   signal io_addr  : unsigned(ADDR_W-1 downto 0);
+   signal phi_addr : unsigned(2 downto 0);
+   signal io_we    : std_logic;
+   signal io_re    : std_logic;
+begin
+   memory: DualPortRAM
+      generic map(
+         WORD_SIZE => WORD_SIZE, BYTE_BITS => BYTE_BITS, BRAM_W => BRAM_W)
+      port map(
+         clk_i => clk_i,
+         -- Port A
+         a_we_i => a_we, a_addr_i => a_addr, a_write_i => a_write,
+         a_read_o => a_read,
+         -- Port B
+         b_we_i => b_we, b_addr_i => b_addr, b_write_i => b_write,
+         b_read_o => b_read);
+
+   -- I/O: Phi layout
+   io_map: ZPUPhiIO
+      generic map(
+         BRDIVISOR => BRDIVISOR, 
+         LOG_FILE  => "zpu_small1_io.log"
+         )
+      port map(
+         clk_i      => clk_i, 
+         reset_i    => rst_i, 
+         busy_o     => io_busy, 
+         we_i       => io_we,
+         re_i       => io_re, 
+         data_i     => io_write, 
+         data_o     => io_read,
+         addr_i     => phi_addr, 
+         rs232_rx_i => rs232_rx_i, 
+         rs232_tx_o => rs232_tx_o,
+         br_clk_i   => '1',
+         gpio_in    => gpio_in,
+         gpio_out   => gpio_out,
+         gpio_dir   => gpio_dir
+         );
+   phi_addr <= io_addr(4 downto 2);
+
+   zpu : ZPUSmallCore
+      generic map(
+         WORD_SIZE => WORD_SIZE, ADDR_W => ADDR_W, MEM_W => BRAM_W,
+         D_CARE_VAL => D_CARE_VAL)
+      port map(
+         clk_i => clk_i, reset_i => rst_i, interrupt_i => '0',
+         break_o => break_o, dbg_o => dbg_o,
+         -- BRAM (text, data, bss and stack)
+         a_we_o => a_we, a_addr_o => a_addr, a_o => a_write, a_i => a_read,
+         b_we_o => b_we, b_addr_o => b_addr, b_o => b_write, b_i => b_read,
+         -- Memory mapped I/O
+         mem_busy_i => io_busy, data_i => io_read, data_o => io_write,
+         addr_o => io_addr, write_en_o => io_we, read_en_o => io_re);
+end architecture Structural; -- Entity: ZPU_Small1
+
diff --git a/zpu/hdl/zealot/roms/dmips_bram.vhdl b/zpu/hdl/zealot/roms/dmips_bram.vhdl
new file mode 100644
index 0000000..977626c
--- /dev/null
+++ b/zpu/hdl/zealot/roms/dmips_bram.vhdl
@@ -0,0 +1,4462 @@
+------------------------------------------------------------------------------
+----                                                                      ----
+----  Single Port RAM that maps to a Xilinx BRAM                          ----
+----                                                                      ----
+----  http://www.opencores.org/                                           ----
+----                                                                      ----
+----  Description:                                                        ----
+----  This is a program+data memory for the ZPU. It maps to a Xilinx BRAM ----
+----                                                                      ----
+----  To Do:                                                              ----
+----  -                                                                   ----
+----                                                                      ----
+----  Author:                                                             ----
+----    - Salvador E. Tropea, salvador inti.gob.ar                        ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar>         ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial       ----
+----                                                                      ----
+---- Distributed under the BSD license                                    ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Design unit:      SinglePortRAM(Xilinx) (Entity and architecture)    ----
+---- File name:        rom_s.in.vhdl (template used)                      ----
+---- Note:             None                                               ----
+---- Limitations:      None known                                         ----
+---- Errors:           None known                                         ----
+---- Library:          work                                               ----
+---- Dependencies:     IEEE.std_logic_1164                                ----
+----                   IEEE.numeric_std                                   ----
+---- Target FPGA:      Spartan 3 (XC3S1500-4-FG456)                       ----
+---- Language:         VHDL                                               ----
+---- Wishbone:         No                                                 ----
+---- Synthesis tools:  Xilinx Release 9.2.03i - xst J.39                  ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x)                       ----
+---- Text editor:      SETEdit 0.5.x                                      ----
+----                                                                      ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity SinglePortRAM is
+   generic(
+      WORD_SIZE    : integer:=32;  -- Word Size 16/32
+      BYTE_BITS    : integer:=2;   -- Bits used to address bytes
+      BRAM_W       : integer:=15); -- Address Width
+   port(
+      clk_i   : in  std_logic;
+      we_i    : in  std_logic;
+      re_i    : in  std_logic;
+      addr_i  : in  unsigned(BRAM_W-1 downto BYTE_BITS);
+      write_i : in  unsigned(WORD_SIZE-1 downto 0);
+      read_o  : out unsigned(WORD_SIZE-1 downto 0);
+      busy_o  : out std_logic);
+end entity SinglePortRAM;
+
+architecture Xilinx of SinglePortRAM is
+   type ram_type is array(natural range 0 to ((2**BRAM_W)/4)-1) of unsigned(WORD_SIZE-1 downto 0);
+   signal addr_r  : unsigned(BRAM_W-1 downto BYTE_BITS);
+
+   signal ram : ram_type :=
+(
+     0 => x"0b0b0b0b",
+     1 => x"82700b0b",
+     2 => x"80f8ec0c",
+     3 => x"3a0b0b80",
+     4 => x"e7ea0400",
+     5 => x"00000000",
+     6 => x"00000000",
+     7 => x"00000000",
+     8 => x"80088408",
+     9 => x"88080b0b",
+    10 => x"80e8b72d",
+    11 => x"880c840c",
+    12 => x"800c0400",
+    13 => x"00000000",
+    14 => x"00000000",
+    15 => x"00000000",
+    16 => x"71fd0608",
+    17 => x"72830609",
+    18 => x"81058205",
+    19 => x"832b2a83",
+    20 => x"ffff0652",
+    21 => x"04000000",
+    22 => x"00000000",
+    23 => x"00000000",
+    24 => x"71fd0608",
+    25 => x"83ffff73",
+    26 => x"83060981",
+    27 => x"05820583",
+    28 => x"2b2b0906",
+    29 => x"7383ffff",
+    30 => x"0b0b0b0b",
+    31 => x"83a70400",
+    32 => x"72098105",
+    33 => x"72057373",
+    34 => x"09060906",
+    35 => x"73097306",
+    36 => x"070a8106",
+    37 => x"53510400",
+    38 => x"00000000",
+    39 => x"00000000",
+    40 => x"72722473",
+    41 => x"732e0753",
+    42 => x"51040000",
+    43 => x"00000000",
+    44 => x"00000000",
+    45 => x"00000000",
+    46 => x"00000000",
+    47 => x"00000000",
+    48 => x"71737109",
+    49 => x"71068106",
+    50 => x"30720a10",
+    51 => x"0a720a10",
+    52 => x"0a31050a",
+    53 => x"81065151",
+    54 => x"53510400",
+    55 => x"00000000",
+    56 => x"72722673",
+    57 => x"732e0753",
+    58 => x"51040000",
+    59 => x"00000000",
+    60 => x"00000000",
+    61 => x"00000000",
+    62 => x"00000000",
+    63 => x"00000000",
+    64 => x"00000000",
+    65 => x"00000000",
+    66 => x"00000000",
+    67 => x"00000000",
+    68 => x"00000000",
+    69 => x"00000000",
+    70 => x"00000000",
+    71 => x"00000000",
+    72 => x"0b0b0b88",
+    73 => x"c4040000",
+    74 => x"00000000",
+    75 => x"00000000",
+    76 => x"00000000",
+    77 => x"00000000",
+    78 => x"00000000",
+    79 => x"00000000",
+    80 => x"720a722b",
+    81 => x"0a535104",
+    82 => x"00000000",
+    83 => x"00000000",
+    84 => x"00000000",
+    85 => x"00000000",
+    86 => x"00000000",
+    87 => x"00000000",
+    88 => x"72729f06",
+    89 => x"0981050b",
+    90 => x"0b0b88a7",
+    91 => x"05040000",
+    92 => x"00000000",
+    93 => x"00000000",
+    94 => x"00000000",
+    95 => x"00000000",
+    96 => x"72722aff",
+    97 => x"739f062a",
+    98 => x"0974090a",
+    99 => x"8106ff05",
+   100 => x"06075351",
+   101 => x"04000000",
+   102 => x"00000000",
+   103 => x"00000000",
+   104 => x"71715351",
+   105 => x"020d0406",
+   106 => x"73830609",
+   107 => x"81058205",
+   108 => x"832b0b2b",
+   109 => x"0772fc06",
+   110 => x"0c515104",
+   111 => x"00000000",
+   112 => x"72098105",
+   113 => x"72050970",
+   114 => x"81050906",
+   115 => x"0a810653",
+   116 => x"51040000",
+   117 => x"00000000",
+   118 => x"00000000",
+   119 => x"00000000",
+   120 => x"72098105",
+   121 => x"72050970",
+   122 => x"81050906",
+   123 => x"0a098106",
+   124 => x"53510400",
+   125 => x"00000000",
+   126 => x"00000000",
+   127 => x"00000000",
+   128 => x"71098105",
+   129 => x"52040000",
+   130 => x"00000000",
+   131 => x"00000000",
+   132 => x"00000000",
+   133 => x"00000000",
+   134 => x"00000000",
+   135 => x"00000000",
+   136 => x"72720981",
+   137 => x"05055351",
+   138 => x"04000000",
+   139 => x"00000000",
+   140 => x"00000000",
+   141 => x"00000000",
+   142 => x"00000000",
+   143 => x"00000000",
+   144 => x"72097206",
+   145 => x"73730906",
+   146 => x"07535104",
+   147 => x"00000000",
+   148 => x"00000000",
+   149 => x"00000000",
+   150 => x"00000000",
+   151 => x"00000000",
+   152 => x"71fc0608",
+   153 => x"72830609",
+   154 => x"81058305",
+   155 => x"1010102a",
+   156 => x"81ff0652",
+   157 => x"04000000",
+   158 => x"00000000",
+   159 => x"00000000",
+   160 => x"71fc0608",
+   161 => x"0b0b80f8",
+   162 => x"d8738306",
+   163 => x"10100508",
+   164 => x"060b0b0b",
+   165 => x"88aa0400",
+   166 => x"00000000",
+   167 => x"00000000",
+   168 => x"80088408",
+   169 => x"88087575",
+   170 => x"0b0b80ce",
+   171 => x"b62d5050",
+   172 => x"80085688",
+   173 => x"0c840c80",
+   174 => x"0c510400",
+   175 => x"00000000",
+   176 => x"80088408",
+   177 => x"88087575",
+   178 => x"0b0b80cf",
+   179 => x"e82d5050",
+   180 => x"80085688",
+   181 => x"0c840c80",
+   182 => x"0c510400",
+   183 => x"00000000",
+   184 => x"72097081",
+   185 => x"0509060a",
+   186 => x"8106ff05",
+   187 => x"70547106",
+   188 => x"73097274",
+   189 => x"05ff0506",
+   190 => x"07515151",
+   191 => x"04000000",
+   192 => x"72097081",
+   193 => x"0509060a",
+   194 => x"098106ff",
+   195 => x"05705471",
+   196 => x"06730972",
+   197 => x"7405ff05",
+   198 => x"06075151",
+   199 => x"51040000",
+   200 => x"05ff0504",
+   201 => x"00000000",
+   202 => x"00000000",
+   203 => x"00000000",
+   204 => x"00000000",
+   205 => x"00000000",
+   206 => x"00000000",
+   207 => x"00000000",
+   208 => x"810b0b0b",
+   209 => x"80f8e80c",
+   210 => x"51040000",
+   211 => x"00000000",
+   212 => x"00000000",
+   213 => x"00000000",
+   214 => x"00000000",
+   215 => x"00000000",
+   216 => x"71810552",
+   217 => x"04000000",
+   218 => x"00000000",
+   219 => x"00000000",
+   220 => x"00000000",
+   221 => x"00000000",
+   222 => x"00000000",
+   223 => x"00000000",
+   224 => x"00000000",
+   225 => x"00000000",
+   226 => x"00000000",
+   227 => x"00000000",
+   228 => x"00000000",
+   229 => x"00000000",
+   230 => x"00000000",
+   231 => x"00000000",
+   232 => x"02840572",
+   233 => x"10100552",
+   234 => x"04000000",
+   235 => x"00000000",
+   236 => x"00000000",
+   237 => x"00000000",
+   238 => x"00000000",
+   239 => x"00000000",
+   240 => x"00000000",
+   241 => x"00000000",
+   242 => x"00000000",
+   243 => x"00000000",
+   244 => x"00000000",
+   245 => x"00000000",
+   246 => x"00000000",
+   247 => x"00000000",
+   248 => x"717105ff",
+   249 => x"05715351",
+   250 => x"020d0400",
+   251 => x"00000000",
+   252 => x"00000000",
+   253 => x"00000000",
+   254 => x"00000000",
+   255 => x"00000000",
+   256 => x"83803f80",
+   257 => x"e2953f04",
+   258 => x"10101010",
+   259 => x"10101010",
+   260 => x"10101010",
+   261 => x"10101010",
+   262 => x"10101010",
+   263 => x"10101010",
+   264 => x"10101010",
+   265 => x"10101053",
+   266 => x"51047381",
+   267 => x"ff067383",
+   268 => x"06098105",
+   269 => x"83051010",
+   270 => x"102b0772",
+   271 => x"fc060c51",
+   272 => x"51043c04",
+   273 => x"72728072",
+   274 => x"8106ff05",
+   275 => x"09720605",
+   276 => x"71105272",
+   277 => x"0a100a53",
+   278 => x"72ed3851",
+   279 => x"51535104",
+   280 => x"ff3d0d0b",
+   281 => x"0b8188e0",
+   282 => x"08527108",
+   283 => x"70882a81",
+   284 => x"32708106",
+   285 => x"51515170",
+   286 => x"f1387372",
+   287 => x"0c833d0d",
+   288 => x"0480f8e8",
+   289 => x"08802ea4",
+   290 => x"3880f8ec",
+   291 => x"08822ebd",
+   292 => x"38838080",
+   293 => x"0b0b0b81",
+   294 => x"88e00c82",
+   295 => x"a0800b81",
+   296 => x"88e40c82",
+   297 => x"90800b81",
+   298 => x"88e80c04",
+   299 => x"f8808080",
+   300 => x"a40b0b0b",
+   301 => x"8188e00c",
+   302 => x"f8808082",
+   303 => x"800b8188",
+   304 => x"e40cf880",
+   305 => x"8084800b",
+   306 => x"8188e80c",
+   307 => x"0480c0a8",
+   308 => x"808c0b0b",
+   309 => x"0b8188e0",
+   310 => x"0c80c0a8",
+   311 => x"80940b81",
+   312 => x"88e40c0b",
+   313 => x"0b80eac8",
+   314 => x"0b8188e8",
+   315 => x"0c04f23d",
+   316 => x"0d608188",
+   317 => x"e408565d",
+   318 => x"82750c80",
+   319 => x"59805a80",
+   320 => x"0b8f3d5d",
+   321 => x"5b7a1010",
+   322 => x"15700871",
+   323 => x"08719f2c",
+   324 => x"7e852b58",
+   325 => x"55557d53",
+   326 => x"59579d94",
+   327 => x"3f7d7f7a",
+   328 => x"72077c72",
+   329 => x"07717160",
+   330 => x"8105415f",
+   331 => x"5d5b5957",
+   332 => x"55817b27",
+   333 => x"8f38767d",
+   334 => x"0c77841e",
+   335 => x"0c7c800c",
+   336 => x"903d0d04",
+   337 => x"8188e408",
+   338 => x"55ffba39",
+   339 => x"ff3d0d81",
+   340 => x"88ec3351",
+   341 => x"70a73880",
+   342 => x"f8f40870",
+   343 => x"08525270",
+   344 => x"802e9438",
+   345 => x"841280f8",
+   346 => x"f40c702d",
+   347 => x"80f8f408",
+   348 => x"70085252",
+   349 => x"70ee3881",
+   350 => x"0b8188ec",
+   351 => x"34833d0d",
+   352 => x"0404803d",
+   353 => x"0d0b0b81",
+   354 => x"88dc0880",
+   355 => x"2e8e380b",
+   356 => x"0b0b0b80",
+   357 => x"0b802e09",
+   358 => x"81068538",
+   359 => x"823d0d04",
+   360 => x"0b0b8188",
+   361 => x"dc510b0b",
+   362 => x"0bf4d53f",
+   363 => x"823d0d04",
+   364 => x"04ff3d0d",
+   365 => x"028f0533",
+   366 => x"52718a2e",
+   367 => x"8a387151",
+   368 => x"fd9e3f83",
+   369 => x"3d0d048d",
+   370 => x"51fd953f",
+   371 => x"7151fd90",
+   372 => x"3f833d0d",
+   373 => x"04ce3d0d",
+   374 => x"b53d7070",
+   375 => x"84055208",
+   376 => x"8bb15c56",
+   377 => x"a53d5e5c",
+   378 => x"80757081",
+   379 => x"05573376",
+   380 => x"5b555873",
+   381 => x"782e80c1",
+   382 => x"388e3d5b",
+   383 => x"73a52e09",
+   384 => x"810680c5",
+   385 => x"38787081",
+   386 => x"055a3354",
+   387 => x"7380e42e",
+   388 => x"81b63873",
+   389 => x"80e42480",
+   390 => x"c6387380",
+   391 => x"e32ea138",
+   392 => x"8052a551",
+   393 => x"792d8052",
+   394 => x"7351792d",
+   395 => x"82185878",
+   396 => x"7081055a",
+   397 => x"335473c4",
+   398 => x"3877800c",
+   399 => x"b43d0d04",
+   400 => x"7b841d83",
+   401 => x"1233565d",
+   402 => x"57805273",
+   403 => x"51792d81",
+   404 => x"18797081",
+   405 => x"055b3355",
+   406 => x"5873ffa0",
+   407 => x"38db3973",
+   408 => x"80f32e09",
+   409 => x"8106ffb8",
+   410 => x"387b841d",
+   411 => x"7108595d",
+   412 => x"56807733",
+   413 => x"55567376",
+   414 => x"2e8d3881",
+   415 => x"16701870",
+   416 => x"33575556",
+   417 => x"74f538ff",
+   418 => x"16558076",
+   419 => x"25ffa038",
+   420 => x"76708105",
+   421 => x"58335480",
+   422 => x"52735179",
+   423 => x"2d811875",
+   424 => x"ff175757",
+   425 => x"58807625",
+   426 => x"ff853876",
+   427 => x"70810558",
+   428 => x"33548052",
+   429 => x"7351792d",
+   430 => x"811875ff",
+   431 => x"17575758",
+   432 => x"758024cc",
+   433 => x"38fee839",
+   434 => x"7b841d71",
+   435 => x"0870719f",
+   436 => x"2c595359",
+   437 => x"5d568075",
+   438 => x"24819338",
+   439 => x"757d7c58",
+   440 => x"56548057",
+   441 => x"73772e09",
+   442 => x"8106b638",
+   443 => x"b07b3402",
+   444 => x"b505567a",
+   445 => x"762e9738",
+   446 => x"ff165675",
+   447 => x"33757081",
+   448 => x"05573481",
+   449 => x"17577a76",
+   450 => x"2e098106",
+   451 => x"eb388075",
+   452 => x"34767dff",
+   453 => x"12575856",
+   454 => x"758024fe",
+   455 => x"f338fe8f",
+   456 => x"398a5273",
+   457 => x"5180c1c0",
+   458 => x"3f800880",
+   459 => x"eacc0533",
+   460 => x"76708105",
+   461 => x"58348a52",
+   462 => x"7351bffa",
+   463 => x"3f800854",
+   464 => x"8008802e",
+   465 => x"ffad388a",
+   466 => x"52735180",
+   467 => x"c19a3f80",
+   468 => x"0880eacc",
+   469 => x"05337670",
+   470 => x"81055834",
+   471 => x"8a527351",
+   472 => x"bfd43f80",
+   473 => x"08548008",
+   474 => x"ffb738ff",
+   475 => x"86397452",
+   476 => x"7653b43d",
+   477 => x"ffb80551",
+   478 => x"978a3fa3",
+   479 => x"3d0856fe",
+   480 => x"db39803d",
+   481 => x"0d80c10b",
+   482 => x"81d7b834",
+   483 => x"800b81d9",
+   484 => x"940c7080",
+   485 => x"0c823d0d",
+   486 => x"04ff3d0d",
+   487 => x"800b81d7",
+   488 => x"b8335252",
+   489 => x"7080c12e",
+   490 => x"99387181",
+   491 => x"d9940807",
+   492 => x"81d9940c",
+   493 => x"80c20b81",
+   494 => x"d7bc3470",
+   495 => x"800c833d",
+   496 => x"0d04810b",
+   497 => x"81d99408",
+   498 => x"0781d994",
+   499 => x"0c80c20b",
+   500 => x"81d7bc34",
+   501 => x"70800c83",
+   502 => x"3d0d04fd",
+   503 => x"3d0d7570",
+   504 => x"088a0553",
+   505 => x"5381d7b8",
+   506 => x"33517080",
+   507 => x"c12e8b38",
+   508 => x"73f33870",
+   509 => x"800c853d",
+   510 => x"0d04ff12",
+   511 => x"7081d7b4",
+   512 => x"0831740c",
+   513 => x"800c853d",
+   514 => x"0d04fc3d",
+   515 => x"0d81d7c0",
+   516 => x"08557480",
+   517 => x"2e8c3876",
+   518 => x"7508710c",
+   519 => x"81d7c008",
+   520 => x"56548c15",
+   521 => x"5381d7b4",
+   522 => x"08528a51",
+   523 => x"8fe73f73",
+   524 => x"800c863d",
+   525 => x"0d04fb3d",
+   526 => x"0d777008",
+   527 => x"5656b053",
+   528 => x"81d7c008",
+   529 => x"52745180",
+   530 => x"cdff3f85",
+   531 => x"0b8c170c",
+   532 => x"850b8c16",
+   533 => x"0c750875",
+   534 => x"0c81d7c0",
+   535 => x"08547380",
+   536 => x"2e8a3873",
+   537 => x"08750c81",
+   538 => x"d7c00854",
+   539 => x"8c145381",
+   540 => x"d7b40852",
+   541 => x"8a518f9d",
+   542 => x"3f841508",
+   543 => x"ad38860b",
+   544 => x"8c160c88",
+   545 => x"15528816",
+   546 => x"08518ea9",
+   547 => x"3f81d7c0",
+   548 => x"08700876",
+   549 => x"0c548c15",
+   550 => x"7054548a",
+   551 => x"52730851",
+   552 => x"8ef33f73",
+   553 => x"800c873d",
+   554 => x"0d047508",
+   555 => x"54b05373",
+   556 => x"52755180",
+   557 => x"cd933f73",
+   558 => x"800c873d",
+   559 => x"0d04d93d",
+   560 => x"0d80f980",
+   561 => x"0b8188e8",
+   562 => x"0cb05180",
+   563 => x"c0e43f80",
+   564 => x"0881d7b0",
+   565 => x"0cb05180",
+   566 => x"c0d83f80",
+   567 => x"0881d7c0",
+   568 => x"0c81d7b0",
+   569 => x"0880080c",
+   570 => x"800b8008",
+   571 => x"84050c82",
+   572 => x"0b800888",
+   573 => x"050ca80b",
+   574 => x"80088c05",
+   575 => x"0c9f5380",
+   576 => x"ead85280",
+   577 => x"08900551",
+   578 => x"80ccbe3f",
+   579 => x"a13d5e9f",
+   580 => x"5380eaf8",
+   581 => x"527d5180",
+   582 => x"ccaf3f8a",
+   583 => x"0b8195f4",
+   584 => x"0c80f59c",
+   585 => x"51f9ae3f",
+   586 => x"80eb9851",
+   587 => x"f9a73f80",
+   588 => x"f59c51f9",
+   589 => x"a03f80f8",
+   590 => x"fc08802e",
+   591 => x"89d73880",
+   592 => x"ebc851f9",
+   593 => x"903f80f5",
+   594 => x"9c51f989",
+   595 => x"3f80f8f8",
+   596 => x"085280eb",
+   597 => x"f451f8fd",
+   598 => x"3f818990",
+   599 => x"5180d5da",
+   600 => x"3f810b9a",
+   601 => x"3d5e5b80",
+   602 => x"0b80f8f8",
+   603 => x"082582d6",
+   604 => x"38903d5f",
+   605 => x"80c10b81",
+   606 => x"d7b83481",
+   607 => x"0b81d994",
+   608 => x"0c80c20b",
+   609 => x"81d7bc34",
+   610 => x"8240835a",
+   611 => x"9f5380ec",
+   612 => x"a4527c51",
+   613 => x"80cbb23f",
+   614 => x"8141807d",
+   615 => x"537e5256",
+   616 => x"8e973f80",
+   617 => x"08762e09",
+   618 => x"81068338",
+   619 => x"81567581",
+   620 => x"d9940c7f",
+   621 => x"70585675",
+   622 => x"8325a238",
+   623 => x"75101016",
+   624 => x"fd0542a9",
+   625 => x"3dffa405",
+   626 => x"53835276",
+   627 => x"518cc63f",
+   628 => x"7f810570",
+   629 => x"41705856",
+   630 => x"837624e0",
+   631 => x"38615475",
+   632 => x"53818998",
+   633 => x"5281d7cc",
+   634 => x"518cba3f",
+   635 => x"81d7c008",
+   636 => x"70085858",
+   637 => x"b0537752",
+   638 => x"765180ca",
+   639 => x"cc3f850b",
+   640 => x"8c190c85",
+   641 => x"0b8c180c",
+   642 => x"7708770c",
+   643 => x"81d7c008",
+   644 => x"5675802e",
+   645 => x"8a387508",
+   646 => x"770c81d7",
+   647 => x"c008568c",
+   648 => x"165381d7",
+   649 => x"b408528a",
+   650 => x"518bea3f",
+   651 => x"84170887",
+   652 => x"eb38860b",
+   653 => x"8c180c88",
+   654 => x"17528818",
+   655 => x"08518af5",
+   656 => x"3f81d7c0",
+   657 => x"08700878",
+   658 => x"0c568c17",
+   659 => x"7054598a",
+   660 => x"52780851",
+   661 => x"8bbf3f80",
+   662 => x"c10b81d7",
+   663 => x"bc335757",
+   664 => x"767626a2",
+   665 => x"3880c352",
+   666 => x"76518ca3",
+   667 => x"3f800861",
+   668 => x"2e89e638",
+   669 => x"81177081",
+   670 => x"ff0681d7",
+   671 => x"bc335858",
+   672 => x"58757727",
+   673 => x"e0387960",
+   674 => x"29627054",
+   675 => x"71535b59",
+   676 => x"b9a43f80",
+   677 => x"0840787a",
+   678 => x"31708729",
+   679 => x"80083180",
+   680 => x"088a0581",
+   681 => x"d7b83381",
+   682 => x"d7b4085e",
+   683 => x"5b525a56",
+   684 => x"7780c12e",
+   685 => x"89d0387b",
+   686 => x"f738811b",
+   687 => x"5b80f8f8",
+   688 => x"087b25fd",
+   689 => x"af3881d7",
+   690 => x"a85180d2",
+   691 => x"ed3f80ec",
+   692 => x"c451f681",
+   693 => x"3f80f59c",
+   694 => x"51f5fa3f",
+   695 => x"80ecd451",
+   696 => x"f5f33f80",
+   697 => x"f59c51f5",
+   698 => x"ec3f81d7",
+   699 => x"b4085280",
+   700 => x"ed8c51f5",
+   701 => x"e03f8552",
+   702 => x"80eda851",
+   703 => x"f5d73f81",
+   704 => x"d9940852",
+   705 => x"80edc451",
+   706 => x"f5cb3f81",
+   707 => x"5280eda8",
+   708 => x"51f5c23f",
+   709 => x"81d7b833",
+   710 => x"5280ede0",
+   711 => x"51f5b63f",
+   712 => x"80c15280",
+   713 => x"edfc51f5",
+   714 => x"ac3f81d7",
+   715 => x"bc335280",
+   716 => x"ee9851f5",
+   717 => x"a03f80c2",
+   718 => x"5280edfc",
+   719 => x"51f5963f",
+   720 => x"81d7ec08",
+   721 => x"5280eeb4",
+   722 => x"51f58a3f",
+   723 => x"875280ed",
+   724 => x"a851f581",
+   725 => x"3f8195f4",
+   726 => x"085280ee",
+   727 => x"d051f4f5",
+   728 => x"3f80eeec",
+   729 => x"51f4ee3f",
+   730 => x"80ef9851",
+   731 => x"f4e73f81",
+   732 => x"d7c00870",
+   733 => x"08535a80",
+   734 => x"efa451f4",
+   735 => x"d83f80ef",
+   736 => x"c051f4d1",
+   737 => x"3f81d7c0",
+   738 => x"08841108",
+   739 => x"535680ef",
+   740 => x"f451f4c1",
+   741 => x"3f805280",
+   742 => x"eda851f4",
+   743 => x"b83f81d7",
+   744 => x"c0088811",
+   745 => x"08535880",
+   746 => x"f09051f4",
+   747 => x"a83f8252",
+   748 => x"80eda851",
+   749 => x"f49f3f81",
+   750 => x"d7c0088c",
+   751 => x"11085357",
+   752 => x"80f0ac51",
+   753 => x"f48f3f91",
+   754 => x"5280eda8",
+   755 => x"51f4863f",
+   756 => x"81d7c008",
+   757 => x"90055280",
+   758 => x"f0c851f3",
+   759 => x"f83f80f0",
+   760 => x"e451f3f1",
+   761 => x"3f80f19c",
+   762 => x"51f3ea3f",
+   763 => x"81d7b008",
+   764 => x"7008535f",
+   765 => x"80efa451",
+   766 => x"f3db3f80",
+   767 => x"f1b051f3",
+   768 => x"d43f81d7",
+   769 => x"b0088411",
+   770 => x"08535b80",
+   771 => x"eff451f3",
+   772 => x"c43f8052",
+   773 => x"80eda851",
+   774 => x"f3bb3f81",
+   775 => x"d7b00888",
+   776 => x"1108535c",
+   777 => x"80f09051",
+   778 => x"f3ab3f81",
+   779 => x"5280eda8",
+   780 => x"51f3a23f",
+   781 => x"81d7b008",
+   782 => x"8c110853",
+   783 => x"5a80f0ac",
+   784 => x"51f3923f",
+   785 => x"925280ed",
+   786 => x"a851f389",
+   787 => x"3f81d7b0",
+   788 => x"08900552",
+   789 => x"80f0c851",
+   790 => x"f2fb3f80",
+   791 => x"f0e451f2",
+   792 => x"f43f7f52",
+   793 => x"80f1f051",
+   794 => x"f2eb3f85",
+   795 => x"5280eda8",
+   796 => x"51f2e23f",
+   797 => x"785280f2",
+   798 => x"8c51f2d9",
+   799 => x"3f8d5280",
+   800 => x"eda851f2",
+   801 => x"d03f6152",
+   802 => x"80f2a851",
+   803 => x"f2c73f87",
+   804 => x"5280eda8",
+   805 => x"51f2be3f",
+   806 => x"605280f2",
+   807 => x"c451f2b5",
+   808 => x"3f815280",
+   809 => x"eda851f2",
+   810 => x"ac3f7d52",
+   811 => x"80f2e051",
+   812 => x"f2a33f80",
+   813 => x"f2fc51f2",
+   814 => x"9c3f7c52",
+   815 => x"80f3b451",
+   816 => x"f2933f80",
+   817 => x"f3d051f2",
+   818 => x"8c3f80f5",
+   819 => x"9c51f285",
+   820 => x"3f81d7a8",
+   821 => x"0881d7ac",
+   822 => x"08818990",
+   823 => x"08818994",
+   824 => x"08727131",
+   825 => x"70742675",
+   826 => x"74317072",
+   827 => x"31818988",
+   828 => x"0c444481",
+   829 => x"898c0c81",
+   830 => x"898c0856",
+   831 => x"80f48855",
+   832 => x"5c595758",
+   833 => x"f1cf3f81",
+   834 => x"89880856",
+   835 => x"80762582",
+   836 => x"a43880f8",
+   837 => x"f8087071",
+   838 => x"9f2c9a3d",
+   839 => x"53565681",
+   840 => x"89880881",
+   841 => x"898c0841",
+   842 => x"537f5470",
+   843 => x"525a8ef6",
+   844 => x"3f66685f",
+   845 => x"8188f80c",
+   846 => x"7d8188fc",
+   847 => x"0c80f8f8",
+   848 => x"08709f2c",
+   849 => x"58568058",
+   850 => x"bd84c078",
+   851 => x"55557652",
+   852 => x"75537951",
+   853 => x"87d23f95",
+   854 => x"3d818988",
+   855 => x"0881898c",
+   856 => x"0841557f",
+   857 => x"56676940",
+   858 => x"537e5470",
+   859 => x"525c8eb6",
+   860 => x"3f64665e",
+   861 => x"8189800c",
+   862 => x"7c818984",
+   863 => x"0c80f8f8",
+   864 => x"08709f2c",
+   865 => x"40588057",
+   866 => x"83dceb94",
+   867 => x"80775555",
+   868 => x"7e527753",
+   869 => x"7b518790",
+   870 => x"3f64665d",
+   871 => x"5b805e8d",
+   872 => x"dd7e5555",
+   873 => x"81898808",
+   874 => x"81898c08",
+   875 => x"59527753",
+   876 => x"795186f4",
+   877 => x"3f666840",
+   878 => x"547e557a",
+   879 => x"527b53a9",
+   880 => x"3dffa805",
+   881 => x"518ddf3f",
+   882 => x"62645e81",
+   883 => x"d7c40c7c",
+   884 => x"81d7c80c",
+   885 => x"80f49851",
+   886 => x"effb3f81",
+   887 => x"88fc0852",
+   888 => x"80f4c851",
+   889 => x"efef3f80",
+   890 => x"f4d051ef",
+   891 => x"e83f8189",
+   892 => x"84085280",
+   893 => x"f4c851ef",
+   894 => x"dc3f81d7",
+   895 => x"c8085280",
+   896 => x"f58051ef",
+   897 => x"d03f80f5",
+   898 => x"9c51efc9",
+   899 => x"3f800b80",
+   900 => x"0ca93d0d",
+   901 => x"0480f5a0",
+   902 => x"51f6a839",
+   903 => x"770857b0",
+   904 => x"53765277",
+   905 => x"5180c2a1",
+   906 => x"3f80c10b",
+   907 => x"81d7bc33",
+   908 => x"5757f8ac",
+   909 => x"39758a38",
+   910 => x"81898c08",
+   911 => x"8126fdd2",
+   912 => x"3880f5d0",
+   913 => x"51ef8e3f",
+   914 => x"80f68851",
+   915 => x"ef873f80",
+   916 => x"f59c51ef",
+   917 => x"803f80f8",
+   918 => x"f8087071",
+   919 => x"9f2c9a3d",
+   920 => x"53565681",
+   921 => x"89880881",
+   922 => x"898c0841",
+   923 => x"537f5470",
+   924 => x"525a8cb2",
+   925 => x"3f66685f",
+   926 => x"8188f80c",
+   927 => x"7d8188fc",
+   928 => x"0c80f8f8",
+   929 => x"08709f2c",
+   930 => x"58568058",
+   931 => x"bd84c078",
+   932 => x"55557652",
+   933 => x"75537951",
+   934 => x"858e3f95",
+   935 => x"3d818988",
+   936 => x"0881898c",
+   937 => x"0841557f",
+   938 => x"56676940",
+   939 => x"537e5470",
+   940 => x"525c8bf2",
+   941 => x"3f64665e",
+   942 => x"8189800c",
+   943 => x"7c818984",
+   944 => x"0c80f8f8",
+   945 => x"08709f2c",
+   946 => x"40588057",
+   947 => x"83dceb94",
+   948 => x"80775555",
+   949 => x"7e527753",
+   950 => x"7b5184cc",
+   951 => x"3f64665d",
+   952 => x"5b805e8d",
+   953 => x"dd7e5555",
+   954 => x"81898808",
+   955 => x"81898c08",
+   956 => x"59527753",
+   957 => x"795184b0",
+   958 => x"3f666840",
+   959 => x"547e557a",
+   960 => x"527b53a9",
+   961 => x"3dffa805",
+   962 => x"518b9b3f",
+   963 => x"62645e81",
+   964 => x"d7c40c7c",
+   965 => x"81d7c80c",
+   966 => x"80f49851",
+   967 => x"edb73f81",
+   968 => x"88fc0852",
+   969 => x"80f4c851",
+   970 => x"edab3f80",
+   971 => x"f4d051ed",
+   972 => x"a43f8189",
+   973 => x"84085280",
+   974 => x"f4c851ed",
+   975 => x"983f81d7",
+   976 => x"c8085280",
+   977 => x"f58051ed",
+   978 => x"8c3f80f5",
+   979 => x"9c51ed85",
+   980 => x"3f800b80",
+   981 => x"0ca93d0d",
+   982 => x"04a93dff",
+   983 => x"a0055280",
+   984 => x"5180d23f",
+   985 => x"9f5380f6",
+   986 => x"a8527c51",
+   987 => x"bfdb3f7a",
+   988 => x"7b81d7b4",
+   989 => x"0c811870",
+   990 => x"81ff0681",
+   991 => x"d7bc3359",
+   992 => x"59595af5",
+   993 => x"fc39ff16",
+   994 => x"707b3160",
+   995 => x"0c5c800b",
+   996 => x"811c5c5c",
+   997 => x"80f8f808",
+   998 => x"7b25f3d8",
+   999 => x"38f6a739",
+  1000 => x"ff3d0d73",
+  1001 => x"82327030",
+  1002 => x"70720780",
+  1003 => x"25800c52",
+  1004 => x"52833d0d",
+  1005 => x"04fe3d0d",
+  1006 => x"74767153",
+  1007 => x"54527182",
+  1008 => x"2e833883",
+  1009 => x"5171812e",
+  1010 => x"9a388172",
+  1011 => x"269f3871",
+  1012 => x"822eb838",
+  1013 => x"71842ea9",
+  1014 => x"3870730c",
+  1015 => x"70800c84",
+  1016 => x"3d0d0480",
+  1017 => x"e40b81d7",
+  1018 => x"b408258b",
+  1019 => x"3880730c",
+  1020 => x"70800c84",
+  1021 => x"3d0d0483",
+  1022 => x"730c7080",
+  1023 => x"0c843d0d",
+  1024 => x"0482730c",
+  1025 => x"70800c84",
+  1026 => x"3d0d0481",
+  1027 => x"730c7080",
+  1028 => x"0c843d0d",
+  1029 => x"04803d0d",
+  1030 => x"74741482",
+  1031 => x"05710c80",
+  1032 => x"0c823d0d",
+  1033 => x"04f73d0d",
+  1034 => x"7b7d7f61",
+  1035 => x"85127082",
+  1036 => x"2b751170",
+  1037 => x"74717084",
+  1038 => x"05530c5a",
+  1039 => x"5a5d5b76",
+  1040 => x"0c7980f8",
+  1041 => x"180c7986",
+  1042 => x"12525758",
+  1043 => x"5a5a7676",
+  1044 => x"24993876",
+  1045 => x"b329822b",
+  1046 => x"79115153",
+  1047 => x"76737084",
+  1048 => x"05550c81",
+  1049 => x"14547574",
+  1050 => x"25f23876",
+  1051 => x"81cc2919",
+  1052 => x"fc110881",
+  1053 => x"05fc120c",
+  1054 => x"7a197008",
+  1055 => x"9fa0130c",
+  1056 => x"5856850b",
+  1057 => x"81d7b40c",
+  1058 => x"75800c8b",
+  1059 => x"3d0d04fe",
+  1060 => x"3d0d0293",
+  1061 => x"05335180",
+  1062 => x"02840597",
+  1063 => x"05335452",
+  1064 => x"70732e88",
+  1065 => x"3871800c",
+  1066 => x"843d0d04",
+  1067 => x"7081d7b8",
+  1068 => x"34810b80",
+  1069 => x"0c843d0d",
+  1070 => x"04f83d0d",
+  1071 => x"7a7c5956",
+  1072 => x"820b8319",
+  1073 => x"55557416",
+  1074 => x"70337533",
+  1075 => x"5b515372",
+  1076 => x"792e80c6",
+  1077 => x"3880c10b",
+  1078 => x"81168116",
+  1079 => x"56565782",
+  1080 => x"7525e338",
+  1081 => x"ffa91770",
+  1082 => x"81ff0655",
+  1083 => x"59738226",
+  1084 => x"83388755",
+  1085 => x"81537680",
+  1086 => x"d22e9838",
+  1087 => x"77527551",
+  1088 => x"be963f80",
+  1089 => x"53728008",
+  1090 => x"25893887",
+  1091 => x"1581d7b4",
+  1092 => x"0c815372",
+  1093 => x"800c8a3d",
+  1094 => x"0d047281",
+  1095 => x"d7b83482",
+  1096 => x"7525ffa2",
+  1097 => x"38ffbd39",
+  1098 => x"8c08028c",
+  1099 => x"0ceb3d0d",
+  1100 => x"800b8c08",
+  1101 => x"f0050c80",
+  1102 => x"0b8c08f4",
+  1103 => x"050c8c08",
+  1104 => x"8c05088c",
+  1105 => x"08900508",
+  1106 => x"5654738c",
+  1107 => x"08f0050c",
+  1108 => x"748c08f4",
+  1109 => x"050c8c08",
+  1110 => x"f8058c08",
+  1111 => x"f0055656",
+  1112 => x"88705475",
+  1113 => x"53765254",
+  1114 => x"bbdf3f80",
+  1115 => x"0b8c08e8",
+  1116 => x"050c800b",
+  1117 => x"8c08ec05",
+  1118 => x"0c8c0894",
+  1119 => x"05088c08",
+  1120 => x"98050856",
+  1121 => x"54738c08",
+  1122 => x"e8050c74",
+  1123 => x"8c08ec05",
+  1124 => x"0c8c08f0",
+  1125 => x"058c08e8",
+  1126 => x"05565688",
+  1127 => x"70547553",
+  1128 => x"765254bb",
+  1129 => x"a43f800b",
+  1130 => x"8c08e805",
+  1131 => x"0c800b8c",
+  1132 => x"08ec050c",
+  1133 => x"8c08fc05",
+  1134 => x"0883ffff",
+  1135 => x"068c08cc",
+  1136 => x"050c8c08",
+  1137 => x"fc050890",
+  1138 => x"2a8c08c4",
+  1139 => x"050c8c08",
+  1140 => x"f4050883",
+  1141 => x"ffff068c",
+  1142 => x"08c8050c",
+  1143 => x"8c08f405",
+  1144 => x"08902a8c",
+  1145 => x"08c0050c",
+  1146 => x"8c08cc05",
+  1147 => x"088c08c8",
+  1148 => x"05082970",
+  1149 => x"8c08dc05",
+  1150 => x"0c8c08cc",
+  1151 => x"05088c08",
+  1152 => x"c0050829",
+  1153 => x"708c08d8",
+  1154 => x"050c8c08",
+  1155 => x"c405088c",
+  1156 => x"08c80508",
+  1157 => x"29708c08",
+  1158 => x"d4050c8c",
+  1159 => x"08c40508",
+  1160 => x"8c08c005",
+  1161 => x"0829708c",
+  1162 => x"08d0050c",
+  1163 => x"8c08dc05",
+  1164 => x"08902a8c",
+  1165 => x"08d80508",
+  1166 => x"118c08d8",
+  1167 => x"050c8c08",
+  1168 => x"d805088c",
+  1169 => x"08d40508",
+  1170 => x"058c08d8",
+  1171 => x"050c5151",
+  1172 => x"5151548c",
+  1173 => x"08d80508",
+  1174 => x"8c08d405",
+  1175 => x"08278f38",
+  1176 => x"8c08d005",
+  1177 => x"08848080",
+  1178 => x"058c08d0",
+  1179 => x"050c8c08",
+  1180 => x"d8050890",
+  1181 => x"2a8c08d0",
+  1182 => x"0508118c",
+  1183 => x"08e0050c",
+  1184 => x"8c08d805",
+  1185 => x"0883ffff",
+  1186 => x"0670902b",
+  1187 => x"8c08dc05",
+  1188 => x"0883ffff",
+  1189 => x"0670128c",
+  1190 => x"08e4050c",
+  1191 => x"52575154",
+  1192 => x"8c08e005",
+  1193 => x"088c08e4",
+  1194 => x"05085654",
+  1195 => x"738c08e8",
+  1196 => x"050c748c",
+  1197 => x"08ec050c",
+  1198 => x"8c08fc05",
+  1199 => x"088c08f0",
+  1200 => x"0508298c",
+  1201 => x"08f80508",
+  1202 => x"8c08f405",
+  1203 => x"08297012",
+  1204 => x"8c08e805",
+  1205 => x"08118c08",
+  1206 => x"e8050c51",
+  1207 => x"55558c08",
+  1208 => x"e805088c",
+  1209 => x"08ec0508",
+  1210 => x"8c088805",
+  1211 => x"08585654",
+  1212 => x"73760c74",
+  1213 => x"84170c8c",
+  1214 => x"08880508",
+  1215 => x"800c973d",
+  1216 => x"0d8c0c04",
+  1217 => x"8c08028c",
+  1218 => x"0cf63d0d",
+  1219 => x"800b8c08",
+  1220 => x"f0050c80",
+  1221 => x"0b8c08f4",
+  1222 => x"050c8c08",
+  1223 => x"8c05088c",
+  1224 => x"08900508",
+  1225 => x"5654738c",
+  1226 => x"08f0050c",
+  1227 => x"748c08f4",
+  1228 => x"050c8c08",
+  1229 => x"f8058c08",
+  1230 => x"f0055656",
+  1231 => x"88705475",
+  1232 => x"53765254",
+  1233 => x"b8833f80",
+  1234 => x"0b8c08f0",
+  1235 => x"050c800b",
+  1236 => x"8c08f405",
+  1237 => x"0c8c08f8",
+  1238 => x"0508308c",
+  1239 => x"08ec050c",
+  1240 => x"8c08fc05",
+  1241 => x"08802e8d",
+  1242 => x"388c08ec",
+  1243 => x"0508ff05",
+  1244 => x"8c08ec05",
+  1245 => x"0c8c08ec",
+  1246 => x"05088c08",
+  1247 => x"f0050c8c",
+  1248 => x"08fc0508",
+  1249 => x"308c08f4",
+  1250 => x"050c8c08",
+  1251 => x"f005088c",
+  1252 => x"08f40508",
+  1253 => x"8c088805",
+  1254 => x"08585654",
+  1255 => x"73760c74",
+  1256 => x"84170c8c",
+  1257 => x"08880508",
+  1258 => x"800c8c3d",
+  1259 => x"0d8c0c04",
+  1260 => x"8c08028c",
+  1261 => x"0cf53d0d",
+  1262 => x"8c089405",
+  1263 => x"089d388c",
+  1264 => x"088c0508",
+  1265 => x"8c089005",
+  1266 => x"088c0888",
+  1267 => x"05085856",
+  1268 => x"5473760c",
+  1269 => x"7484170c",
+  1270 => x"81bf3980",
+  1271 => x"0b8c08f0",
+  1272 => x"050c800b",
+  1273 => x"8c08f405",
+  1274 => x"0c8c088c",
+  1275 => x"05088c08",
+  1276 => x"90050856",
+  1277 => x"54738c08",
+  1278 => x"f0050c74",
+  1279 => x"8c08f405",
+  1280 => x"0c8c08f8",
+  1281 => x"058c08f0",
+  1282 => x"05565688",
+  1283 => x"70547553",
+  1284 => x"765254b6",
+  1285 => x"b43fa00b",
+  1286 => x"8c089405",
+  1287 => x"08318c08",
+  1288 => x"ec050c8c",
+  1289 => x"08ec0508",
+  1290 => x"80249d38",
+  1291 => x"800b8c08",
+  1292 => x"f4050c8c",
+  1293 => x"08ec0508",
+  1294 => x"308c08fc",
+  1295 => x"0508712b",
+  1296 => x"8c08f005",
+  1297 => x"0c54b939",
+  1298 => x"8c08fc05",
+  1299 => x"088c08ec",
+  1300 => x"05082a8c",
+  1301 => x"08e8050c",
+  1302 => x"8c08fc05",
+  1303 => x"088c0894",
+  1304 => x"05082b8c",
+  1305 => x"08f4050c",
+  1306 => x"8c08f805",
+  1307 => x"088c0894",
+  1308 => x"05082b70",
+  1309 => x"8c08e805",
+  1310 => x"08078c08",
+  1311 => x"f0050c54",
+  1312 => x"8c08f005",
+  1313 => x"088c08f4",
+  1314 => x"05088c08",
+  1315 => x"88050858",
+  1316 => x"56547376",
+  1317 => x"0c748417",
+  1318 => x"0c8c0888",
+  1319 => x"0508800c",
+  1320 => x"8d3d0d8c",
+  1321 => x"0c048c08",
+  1322 => x"028c0ccc",
+  1323 => x"3d0d800b",
+  1324 => x"8c08fc05",
+  1325 => x"0c800b8c",
+  1326 => x"08ec050c",
+  1327 => x"800b8c08",
+  1328 => x"f0050c8c",
+  1329 => x"088c0508",
+  1330 => x"8c089005",
+  1331 => x"08565473",
+  1332 => x"8c08ec05",
+  1333 => x"0c748c08",
+  1334 => x"f0050c8c",
+  1335 => x"08f4058c",
+  1336 => x"08ec0556",
+  1337 => x"56887054",
+  1338 => x"75537652",
+  1339 => x"54b4da3f",
+  1340 => x"800b8c08",
+  1341 => x"e4050c80",
+  1342 => x"0b8c08e8",
+  1343 => x"050c8c08",
+  1344 => x"9405088c",
+  1345 => x"08980508",
+  1346 => x"5654738c",
+  1347 => x"08e4050c",
+  1348 => x"748c08e8",
+  1349 => x"050c8c08",
+  1350 => x"ec058c08",
+  1351 => x"e4055656",
+  1352 => x"88705475",
+  1353 => x"53765254",
+  1354 => x"b49f3f8c",
+  1355 => x"08f40508",
+  1356 => x"8025be38",
+  1357 => x"8c08fc05",
+  1358 => x"08098c08",
+  1359 => x"fc050c8c",
+  1360 => x"08d40554",
+  1361 => x"8c08f405",
+  1362 => x"088c08f8",
+  1363 => x"05085755",
+  1364 => x"74527553",
+  1365 => x"7351fbac",
+  1366 => x"3f8c08d4",
+  1367 => x"05088c08",
+  1368 => x"d8050856",
+  1369 => x"54738c08",
+  1370 => x"f4050c74",
+  1371 => x"8c08f805",
+  1372 => x"0c8c08ec",
+  1373 => x"05088025",
+  1374 => x"be388c08",
+  1375 => x"fc050809",
+  1376 => x"8c08fc05",
+  1377 => x"0c8c08d4",
+  1378 => x"05548c08",
+  1379 => x"ec05088c",
+  1380 => x"08f00508",
+  1381 => x"57557452",
+  1382 => x"75537351",
+  1383 => x"fae63f8c",
+  1384 => x"08d40508",
+  1385 => x"8c08d805",
+  1386 => x"08565473",
+  1387 => x"8c08ec05",
+  1388 => x"0c748c08",
+  1389 => x"f0050c8c",
+  1390 => x"08f40508",
+  1391 => x"8c08f805",
+  1392 => x"08565473",
+  1393 => x"8c08d405",
+  1394 => x"0c748c08",
+  1395 => x"d8050c8c",
+  1396 => x"08ec0508",
+  1397 => x"8c08f005",
+  1398 => x"08565473",
+  1399 => x"8c08cc05",
+  1400 => x"0c748c08",
+  1401 => x"d0050c80",
+  1402 => x"0b8c08c8",
+  1403 => x"050c800b",
+  1404 => x"8c08e405",
+  1405 => x"0c800b8c",
+  1406 => x"08e8050c",
+  1407 => x"8c08d405",
+  1408 => x"088c08d8",
+  1409 => x"05085654",
+  1410 => x"738c08e4",
+  1411 => x"050c748c",
+  1412 => x"08e8050c",
+  1413 => x"800b8c08",
+  1414 => x"ffb8050c",
+  1415 => x"800b8c08",
+  1416 => x"ffbc050c",
+  1417 => x"8c08cc05",
+  1418 => x"088c08d0",
+  1419 => x"05085654",
+  1420 => x"738c08ff",
+  1421 => x"b8050c74",
+  1422 => x"8c08ffbc",
+  1423 => x"050c8c08",
+  1424 => x"ffbc0508",
+  1425 => x"8c08ffac",
+  1426 => x"050c8c08",
+  1427 => x"ffb80508",
+  1428 => x"8c08ffa8",
+  1429 => x"050c8c08",
+  1430 => x"e805088c",
+  1431 => x"08ffa405",
+  1432 => x"0c8c08e4",
+  1433 => x"05088c08",
+  1434 => x"ffa0050c",
+  1435 => x"8c08ffa8",
+  1436 => x"050891d4",
+  1437 => x"388c08ff",
+  1438 => x"a005088c",
+  1439 => x"08ffac05",
+  1440 => x"0827868c",
+  1441 => x"388c08ff",
+  1442 => x"ac05088c",
+  1443 => x"08ff8805",
+  1444 => x"0c8c08ff",
+  1445 => x"88050883",
+  1446 => x"ffff26a0",
+  1447 => x"388c08ff",
+  1448 => x"88050881",
+  1449 => x"ff268b38",
+  1450 => x"800b8c08",
+  1451 => x"fed8050c",
+  1452 => x"a939880b",
+  1453 => x"8c08fed8",
+  1454 => x"050c9f39",
+  1455 => x"8c08ff88",
+  1456 => x"0508fe80",
+  1457 => x"0a268b38",
+  1458 => x"900b8c08",
+  1459 => x"fed8050c",
+  1460 => x"8939980b",
+  1461 => x"8c08fed8",
+  1462 => x"050c8c08",
+  1463 => x"fed80508",
+  1464 => x"8c08ff84",
+  1465 => x"050c8c08",
+  1466 => x"ff880508",
+  1467 => x"8c08ff84",
+  1468 => x"05082a80",
+  1469 => x"f6c81133",
+  1470 => x"8c08ff84",
+  1471 => x"050811a0",
+  1472 => x"71318c08",
+  1473 => x"ff8c050c",
+  1474 => x"5151548c",
+  1475 => x"08ff8c05",
+  1476 => x"08802e80",
+  1477 => x"d1388c08",
+  1478 => x"ffac0508",
+  1479 => x"8c08ff8c",
+  1480 => x"05082b8c",
+  1481 => x"08ffac05",
+  1482 => x"0c8c08ff",
+  1483 => x"a005088c",
+  1484 => x"08ff8c05",
+  1485 => x"082ba00b",
+  1486 => x"8c08ff8c",
+  1487 => x"0508318c",
+  1488 => x"08ffa405",
+  1489 => x"08712a70",
+  1490 => x"73078c08",
+  1491 => x"ffa0050c",
+  1492 => x"8c08ffa4",
+  1493 => x"05088c08",
+  1494 => x"ff8c0508",
+  1495 => x"2b8c08ff",
+  1496 => x"a4050c51",
+  1497 => x"56548c08",
+  1498 => x"ffac0508",
+  1499 => x"902a8c08",
+  1500 => x"ff84050c",
+  1501 => x"8c08ffac",
+  1502 => x"050883ff",
+  1503 => x"ff068c08",
+  1504 => x"ff88050c",
+  1505 => x"8c08ffa0",
+  1506 => x"05088c08",
+  1507 => x"ff840508",
+  1508 => x"53705254",
+  1509 => x"9efb3f80",
+  1510 => x"08708c08",
+  1511 => x"fef8050c",
+  1512 => x"8c08ff84",
+  1513 => x"0508538c",
+  1514 => x"08ffa005",
+  1515 => x"0852549e",
+  1516 => x"bb3f8008",
+  1517 => x"708c08ff",
+  1518 => x"80050c8c",
+  1519 => x"08ff8005",
+  1520 => x"088c08ff",
+  1521 => x"88050829",
+  1522 => x"708c08fe",
+  1523 => x"f0050c8c",
+  1524 => x"08fef805",
+  1525 => x"0870902b",
+  1526 => x"8c08ffa4",
+  1527 => x"0508902a",
+  1528 => x"7072078c",
+  1529 => x"08fef805",
+  1530 => x"0c525851",
+  1531 => x"51548c08",
+  1532 => x"fef80508",
+  1533 => x"8c08fef0",
+  1534 => x"05082780",
+  1535 => x"e1388c08",
+  1536 => x"ff800508",
+  1537 => x"ff058c08",
+  1538 => x"ff80050c",
+  1539 => x"8c08fef8",
+  1540 => x"05088c08",
+  1541 => x"ffac0508",
+  1542 => x"058c08fe",
+  1543 => x"f8050c8c",
+  1544 => x"08ffac05",
+  1545 => x"088c08fe",
+  1546 => x"f8050826",
+  1547 => x"b1388c08",
+  1548 => x"fef80508",
+  1549 => x"8c08fef0",
+  1550 => x"050827a2",
+  1551 => x"388c08ff",
+  1552 => x"800508ff",
+  1553 => x"058c08ff",
+  1554 => x"80050c8c",
+  1555 => x"08fef805",
+  1556 => x"088c08ff",
+  1557 => x"ac050805",
+  1558 => x"8c08fef8",
+  1559 => x"050c8c08",
+  1560 => x"fef80508",
+  1561 => x"8c08fef0",
+  1562 => x"0508318c",
+  1563 => x"08fef805",
+  1564 => x"0c8c08fe",
+  1565 => x"f805088c",
+  1566 => x"08ff8405",
+  1567 => x"08537052",
+  1568 => x"549d8e3f",
+  1569 => x"8008708c",
+  1570 => x"08fef405",
+  1571 => x"0c8c08ff",
+  1572 => x"84050853",
+  1573 => x"8c08fef8",
+  1574 => x"05085254",
+  1575 => x"9cce3f80",
+  1576 => x"08708c08",
+  1577 => x"fefc050c",
+  1578 => x"8c08fefc",
+  1579 => x"05088c08",
+  1580 => x"ff880508",
+  1581 => x"29708c08",
+  1582 => x"fef0050c",
+  1583 => x"8c08fef4",
+  1584 => x"05087090",
+  1585 => x"2b8c08ff",
+  1586 => x"a4050883",
+  1587 => x"ffff0670",
+  1588 => x"72078c08",
+  1589 => x"fef4050c",
+  1590 => x"52585151",
+  1591 => x"548c08fe",
+  1592 => x"f405088c",
+  1593 => x"08fef005",
+  1594 => x"082780e1",
+  1595 => x"388c08fe",
+  1596 => x"fc0508ff",
+  1597 => x"058c08fe",
+  1598 => x"fc050c8c",
+  1599 => x"08fef405",
+  1600 => x"088c08ff",
+  1601 => x"ac050805",
+  1602 => x"8c08fef4",
+  1603 => x"050c8c08",
+  1604 => x"ffac0508",
+  1605 => x"8c08fef4",
+  1606 => x"050826b1",
+  1607 => x"388c08fe",
+  1608 => x"f405088c",
+  1609 => x"08fef005",
+  1610 => x"0827a238",
+  1611 => x"8c08fefc",
+  1612 => x"0508ff05",
+  1613 => x"8c08fefc",
+  1614 => x"050c8c08",
+  1615 => x"fef40508",
+  1616 => x"8c08ffac",
+  1617 => x"0508058c",
+  1618 => x"08fef405",
+  1619 => x"0c8c08fe",
+  1620 => x"f405088c",
+  1621 => x"08fef005",
+  1622 => x"08318c08",
+  1623 => x"fef4050c",
+  1624 => x"8c08ff80",
+  1625 => x"05087090",
+  1626 => x"2b708c08",
+  1627 => x"fefc0508",
+  1628 => x"078c08ff",
+  1629 => x"98050c8c",
+  1630 => x"08fef405",
+  1631 => x"088c08ff",
+  1632 => x"a4050c51",
+  1633 => x"54800b8c",
+  1634 => x"08ff9405",
+  1635 => x"0c8af639",
+  1636 => x"8c08ffac",
+  1637 => x"05089738",
+  1638 => x"8c08ffac",
+  1639 => x"05085281",
+  1640 => x"519ac93f",
+  1641 => x"8008708c",
+  1642 => x"08ffac05",
+  1643 => x"0c548c08",
+  1644 => x"ffac0508",
+  1645 => x"8c08fef0",
+  1646 => x"050c8c08",
+  1647 => x"fef00508",
+  1648 => x"83ffff26",
+  1649 => x"a0388c08",
+  1650 => x"fef00508",
+  1651 => x"81ff268b",
+  1652 => x"38800b8c",
+  1653 => x"08fed405",
+  1654 => x"0ca93988",
+  1655 => x"0b8c08fe",
+  1656 => x"d4050c9f",
+  1657 => x"398c08fe",
+  1658 => x"f00508fe",
+  1659 => x"800a268b",
+  1660 => x"38900b8c",
+  1661 => x"08fed405",
+  1662 => x"0c893998",
+  1663 => x"0b8c08fe",
+  1664 => x"d4050c8c",
+  1665 => x"08fed405",
+  1666 => x"088c08fe",
+  1667 => x"f4050c8c",
+  1668 => x"08fef005",
+  1669 => x"088c08fe",
+  1670 => x"f405082a",
+  1671 => x"80f6c811",
+  1672 => x"338c08fe",
+  1673 => x"f4050811",
+  1674 => x"a071318c",
+  1675 => x"08ff8c05",
+  1676 => x"0c515154",
+  1677 => x"8c08ff8c",
+  1678 => x"05089f38",
+  1679 => x"8c08ffa0",
+  1680 => x"05088c08",
+  1681 => x"ffac0508",
+  1682 => x"318c08ff",
+  1683 => x"a0050c81",
+  1684 => x"0b8c08ff",
+  1685 => x"94050c85",
+  1686 => x"8d39a00b",
+  1687 => x"8c08ff8c",
+  1688 => x"0508318c",
+  1689 => x"08ff9005",
+  1690 => x"0c8c08ff",
+  1691 => x"ac05088c",
+  1692 => x"08ff8c05",
+  1693 => x"082b8c08",
+  1694 => x"ffac050c",
+  1695 => x"8c08ffa0",
+  1696 => x"05088c08",
+  1697 => x"ff900508",
+  1698 => x"2a8c08ff",
+  1699 => x"9c050c8c",
+  1700 => x"08ffa005",
+  1701 => x"088c08ff",
+  1702 => x"8c05082b",
+  1703 => x"8c08ffa4",
+  1704 => x"05088c08",
+  1705 => x"ff900508",
+  1706 => x"2a707207",
+  1707 => x"8c08ffa0",
+  1708 => x"050c8c08",
+  1709 => x"ffa40508",
+  1710 => x"8c08ff8c",
+  1711 => x"05082b8c",
+  1712 => x"08ffa405",
+  1713 => x"0c8c08ff",
+  1714 => x"ac050890",
+  1715 => x"2a8c08fe",
+  1716 => x"f0050c8c",
+  1717 => x"08ffac05",
+  1718 => x"0883ffff",
+  1719 => x"068c08fe",
+  1720 => x"f4050c8c",
+  1721 => x"08ff9c05",
+  1722 => x"088c08fe",
+  1723 => x"f0050855",
+  1724 => x"70545155",
+  1725 => x"55989a3f",
+  1726 => x"8008708c",
+  1727 => x"08ff8005",
+  1728 => x"0c8c08fe",
+  1729 => x"f0050853",
+  1730 => x"8c08ff9c",
+  1731 => x"05085254",
+  1732 => x"97da3f80",
+  1733 => x"08708c08",
+  1734 => x"fef8050c",
+  1735 => x"8c08fef8",
+  1736 => x"05088c08",
+  1737 => x"fef40508",
+  1738 => x"29708c08",
+  1739 => x"ff88050c",
+  1740 => x"8c08ff80",
+  1741 => x"05087090",
+  1742 => x"2b8c08ff",
+  1743 => x"a0050890",
+  1744 => x"2a707207",
+  1745 => x"8c08ff80",
+  1746 => x"050c5258",
+  1747 => x"5151548c",
+  1748 => x"08ff8005",
+  1749 => x"088c08ff",
+  1750 => x"88050827",
+  1751 => x"80e1388c",
+  1752 => x"08fef805",
+  1753 => x"08ff058c",
+  1754 => x"08fef805",
+  1755 => x"0c8c08ff",
+  1756 => x"8005088c",
+  1757 => x"08ffac05",
+  1758 => x"08058c08",
+  1759 => x"ff80050c",
+  1760 => x"8c08ffac",
+  1761 => x"05088c08",
+  1762 => x"ff800508",
+  1763 => x"26b1388c",
+  1764 => x"08ff8005",
+  1765 => x"088c08ff",
+  1766 => x"88050827",
+  1767 => x"a2388c08",
+  1768 => x"fef80508",
+  1769 => x"ff058c08",
+  1770 => x"fef8050c",
+  1771 => x"8c08ff80",
+  1772 => x"05088c08",
+  1773 => x"ffac0508",
+  1774 => x"058c08ff",
+  1775 => x"80050c8c",
+  1776 => x"08ff8005",
+  1777 => x"088c08ff",
+  1778 => x"88050831",
+  1779 => x"8c08ff80",
+  1780 => x"050c8c08",
+  1781 => x"ff800508",
+  1782 => x"8c08fef0",
+  1783 => x"05085370",
+  1784 => x"525496ad",
+  1785 => x"3f800870",
+  1786 => x"8c08ff84",
+  1787 => x"050c8c08",
+  1788 => x"fef00508",
+  1789 => x"538c08ff",
+  1790 => x"80050852",
+  1791 => x"5495ed3f",
+  1792 => x"8008708c",
+  1793 => x"08fefc05",
+  1794 => x"0c8c08fe",
+  1795 => x"fc05088c",
+  1796 => x"08fef405",
+  1797 => x"0829708c",
+  1798 => x"08ff8805",
+  1799 => x"0c8c08ff",
+  1800 => x"84050870",
+  1801 => x"902b8c08",
+  1802 => x"ffa00508",
+  1803 => x"83ffff06",
+  1804 => x"7072078c",
+  1805 => x"08ff8405",
+  1806 => x"0c525851",
+  1807 => x"51548c08",
+  1808 => x"ff840508",
+  1809 => x"8c08ff88",
+  1810 => x"05082780",
+  1811 => x"e1388c08",
+  1812 => x"fefc0508",
+  1813 => x"ff058c08",
+  1814 => x"fefc050c",
+  1815 => x"8c08ff84",
+  1816 => x"05088c08",
+  1817 => x"ffac0508",
+  1818 => x"058c08ff",
+  1819 => x"84050c8c",
+  1820 => x"08ffac05",
+  1821 => x"088c08ff",
+  1822 => x"84050826",
+  1823 => x"b1388c08",
+  1824 => x"ff840508",
+  1825 => x"8c08ff88",
+  1826 => x"050827a2",
+  1827 => x"388c08fe",
+  1828 => x"fc0508ff",
+  1829 => x"058c08fe",
+  1830 => x"fc050c8c",
+  1831 => x"08ff8405",
+  1832 => x"088c08ff",
+  1833 => x"ac050805",
+  1834 => x"8c08ff84",
+  1835 => x"050c8c08",
+  1836 => x"ff840508",
+  1837 => x"8c08ff88",
+  1838 => x"0508318c",
+  1839 => x"08ff8405",
+  1840 => x"0c8c08fe",
+  1841 => x"f8050870",
+  1842 => x"902b708c",
+  1843 => x"08fefc05",
+  1844 => x"08078c08",
+  1845 => x"ff94050c",
+  1846 => x"8c08ff84",
+  1847 => x"05088c08",
+  1848 => x"ffa0050c",
+  1849 => x"51548c08",
+  1850 => x"ffac0508",
+  1851 => x"902a8c08",
+  1852 => x"fef0050c",
+  1853 => x"8c08ffac",
+  1854 => x"050883ff",
+  1855 => x"ff068c08",
+  1856 => x"fef4050c",
+  1857 => x"8c08ffa0",
+  1858 => x"05088c08",
+  1859 => x"fef00508",
+  1860 => x"53705254",
+  1861 => x"93fb3f80",
+  1862 => x"08708c08",
+  1863 => x"ff80050c",
+  1864 => x"8c08fef0",
+  1865 => x"0508538c",
+  1866 => x"08ffa005",
+  1867 => x"08525493",
+  1868 => x"bb3f8008",
+  1869 => x"708c08fe",
+  1870 => x"f8050c8c",
+  1871 => x"08fef805",
+  1872 => x"088c08fe",
+  1873 => x"f4050829",
+  1874 => x"708c08ff",
+  1875 => x"88050c8c",
+  1876 => x"08ff8005",
+  1877 => x"0870902b",
+  1878 => x"8c08ffa4",
+  1879 => x"0508902a",
+  1880 => x"7072078c",
+  1881 => x"08ff8005",
+  1882 => x"0c525851",
+  1883 => x"51548c08",
+  1884 => x"ff800508",
+  1885 => x"8c08ff88",
+  1886 => x"05082780",
+  1887 => x"e1388c08",
+  1888 => x"fef80508",
+  1889 => x"ff058c08",
+  1890 => x"fef8050c",
+  1891 => x"8c08ff80",
+  1892 => x"05088c08",
+  1893 => x"ffac0508",
+  1894 => x"058c08ff",
+  1895 => x"80050c8c",
+  1896 => x"08ffac05",
+  1897 => x"088c08ff",
+  1898 => x"80050826",
+  1899 => x"b1388c08",
+  1900 => x"ff800508",
+  1901 => x"8c08ff88",
+  1902 => x"050827a2",
+  1903 => x"388c08fe",
+  1904 => x"f80508ff",
+  1905 => x"058c08fe",
+  1906 => x"f8050c8c",
+  1907 => x"08ff8005",
+  1908 => x"088c08ff",
+  1909 => x"ac050805",
+  1910 => x"8c08ff80",
+  1911 => x"050c8c08",
+  1912 => x"ff800508",
+  1913 => x"8c08ff88",
+  1914 => x"0508318c",
+  1915 => x"08ff8005",
+  1916 => x"0c8c08ff",
+  1917 => x"8005088c",
+  1918 => x"08fef005",
+  1919 => x"08537052",
+  1920 => x"54928e3f",
+  1921 => x"8008708c",
+  1922 => x"08ff8405",
+  1923 => x"0c8c08fe",
+  1924 => x"f0050853",
+  1925 => x"8c08ff80",
+  1926 => x"05085254",
+  1927 => x"91ce3f80",
+  1928 => x"08708c08",
+  1929 => x"fefc050c",
+  1930 => x"8c08fefc",
+  1931 => x"05088c08",
+  1932 => x"fef40508",
+  1933 => x"29708c08",
+  1934 => x"ff88050c",
+  1935 => x"8c08ff84",
+  1936 => x"05087090",
+  1937 => x"2b8c08ff",
+  1938 => x"a4050883",
+  1939 => x"ffff0670",
+  1940 => x"72078c08",
+  1941 => x"ff84050c",
+  1942 => x"52585151",
+  1943 => x"548c08ff",
+  1944 => x"8405088c",
+  1945 => x"08ff8805",
+  1946 => x"082780e1",
+  1947 => x"388c08fe",
+  1948 => x"fc0508ff",
+  1949 => x"058c08fe",
+  1950 => x"fc050c8c",
+  1951 => x"08ff8405",
+  1952 => x"088c08ff",
+  1953 => x"ac050805",
+  1954 => x"8c08ff84",
+  1955 => x"050c8c08",
+  1956 => x"ffac0508",
+  1957 => x"8c08ff84",
+  1958 => x"050826b1",
+  1959 => x"388c08ff",
+  1960 => x"8405088c",
+  1961 => x"08ff8805",
+  1962 => x"0827a238",
+  1963 => x"8c08fefc",
+  1964 => x"0508ff05",
+  1965 => x"8c08fefc",
+  1966 => x"050c8c08",
+  1967 => x"ff840508",
+  1968 => x"8c08ffac",
+  1969 => x"0508058c",
+  1970 => x"08ff8405",
+  1971 => x"0c8c08ff",
+  1972 => x"8405088c",
+  1973 => x"08ff8805",
+  1974 => x"08318c08",
+  1975 => x"ff84050c",
+  1976 => x"8c08fef8",
+  1977 => x"05087090",
+  1978 => x"2b708c08",
+  1979 => x"fefc0508",
+  1980 => x"078c08ff",
+  1981 => x"98050c8c",
+  1982 => x"08ff8405",
+  1983 => x"088c08ff",
+  1984 => x"a4050c51",
+  1985 => x"548c08c8",
+  1986 => x"0508802e",
+  1987 => x"8ea3388c",
+  1988 => x"08ffa405",
+  1989 => x"088c08ff",
+  1990 => x"8c05082a",
+  1991 => x"8c08ffb4",
+  1992 => x"050c800b",
+  1993 => x"8c08ffb0",
+  1994 => x"050c8c08",
+  1995 => x"c8050856",
+  1996 => x"8c08ffb0",
+  1997 => x"05088c08",
+  1998 => x"ffb40508",
+  1999 => x"56547376",
+  2000 => x"0c748417",
+  2001 => x"0c8dea39",
+  2002 => x"8c08ffa0",
+  2003 => x"05088c08",
+  2004 => x"ffa80508",
+  2005 => x"2780d138",
+  2006 => x"800b8c08",
+  2007 => x"ff98050c",
+  2008 => x"800b8c08",
+  2009 => x"ff94050c",
+  2010 => x"8c08c805",
+  2011 => x"08802e8d",
+  2012 => x"c0388c08",
+  2013 => x"ffa40508",
+  2014 => x"8c08ffb4",
+  2015 => x"050c8c08",
+  2016 => x"ffa00508",
+  2017 => x"8c08ffb0",
+  2018 => x"050c8c08",
+  2019 => x"c8050856",
+  2020 => x"8c08ffb0",
+  2021 => x"05088c08",
+  2022 => x"ffb40508",
+  2023 => x"56547376",
+  2024 => x"0c748417",
+  2025 => x"0c8d8a39",
+  2026 => x"8c08ffa8",
+  2027 => x"05088c08",
+  2028 => x"fef0050c",
+  2029 => x"8c08fef0",
+  2030 => x"050883ff",
+  2031 => x"ff26a038",
+  2032 => x"8c08fef0",
+  2033 => x"050881ff",
+  2034 => x"268b3880",
+  2035 => x"0b8c08fe",
+  2036 => x"d0050ca9",
+  2037 => x"39880b8c",
+  2038 => x"08fed005",
+  2039 => x"0c9f398c",
+  2040 => x"08fef005",
+  2041 => x"08fe800a",
+  2042 => x"268b3890",
+  2043 => x"0b8c08fe",
+  2044 => x"d0050c89",
+  2045 => x"39980b8c",
+  2046 => x"08fed005",
+  2047 => x"0c8c08fe",
+  2048 => x"d005088c",
+  2049 => x"08fef405",
+  2050 => x"0c8c08fe",
+  2051 => x"f005088c",
+  2052 => x"08fef405",
+  2053 => x"082a80f6",
+  2054 => x"c811338c",
+  2055 => x"08fef405",
+  2056 => x"0811a071",
+  2057 => x"318c08ff",
+  2058 => x"8c050c51",
+  2059 => x"51548c08",
+  2060 => x"ff8c0508",
+  2061 => x"81d9388c",
+  2062 => x"08ffa005",
+  2063 => x"088c08ff",
+  2064 => x"a8050826",
+  2065 => x"93388c08",
+  2066 => x"ffa40508",
+  2067 => x"8c08ffac",
+  2068 => x"05082784",
+  2069 => x"3880e839",
+  2070 => x"810b8c08",
+  2071 => x"ff98050c",
+  2072 => x"8c08ffa4",
+  2073 => x"05088c08",
+  2074 => x"ffac0508",
+  2075 => x"318c08fe",
+  2076 => x"f0050c8c",
+  2077 => x"08ffa005",
+  2078 => x"088c08ff",
+  2079 => x"a8050831",
+  2080 => x"708c08fe",
+  2081 => x"cc050c54",
+  2082 => x"8c08ffa4",
+  2083 => x"05088c08",
+  2084 => x"fef00508",
+  2085 => x"278f388c",
+  2086 => x"08fecc05",
+  2087 => x"08ff058c",
+  2088 => x"08fecc05",
+  2089 => x"0c8c08fe",
+  2090 => x"cc05088c",
+  2091 => x"08ffa005",
+  2092 => x"0c8c08fe",
+  2093 => x"f005088c",
+  2094 => x"08ffa405",
+  2095 => x"0c893980",
+  2096 => x"0b8c08ff",
+  2097 => x"98050c80",
+  2098 => x"0b8c08ff",
+  2099 => x"94050c8c",
+  2100 => x"08c80508",
+  2101 => x"802e8ad9",
+  2102 => x"388c08ff",
+  2103 => x"a405088c",
+  2104 => x"08ffb405",
+  2105 => x"0c8c08ff",
+  2106 => x"a005088c",
+  2107 => x"08ffb005",
+  2108 => x"0c8c08c8",
+  2109 => x"0508568c",
+  2110 => x"08ffb005",
+  2111 => x"088c08ff",
+  2112 => x"b4050856",
+  2113 => x"5473760c",
+  2114 => x"7484170c",
+  2115 => x"8aa339a0",
+  2116 => x"0b8c08ff",
+  2117 => x"8c050831",
+  2118 => x"8c08ff90",
+  2119 => x"050c8c08",
+  2120 => x"ffa80508",
+  2121 => x"8c08ff8c",
+  2122 => x"05082b8c",
+  2123 => x"08ffac05",
+  2124 => x"088c08ff",
+  2125 => x"9005082a",
+  2126 => x"7072078c",
+  2127 => x"08ffa805",
+  2128 => x"0c8c08ff",
+  2129 => x"ac05088c",
+  2130 => x"08ff8c05",
+  2131 => x"082b8c08",
+  2132 => x"ffac050c",
+  2133 => x"8c08ffa0",
+  2134 => x"05088c08",
+  2135 => x"ff900508",
+  2136 => x"2a8c08ff",
+  2137 => x"9c050c8c",
+  2138 => x"08ffa005",
+  2139 => x"088c08ff",
+  2140 => x"8c05082b",
+  2141 => x"8c08ffa4",
+  2142 => x"05088c08",
+  2143 => x"ff900508",
+  2144 => x"2a707207",
+  2145 => x"8c08ffa0",
+  2146 => x"050c8c08",
+  2147 => x"ffa40508",
+  2148 => x"8c08ff8c",
+  2149 => x"05082b8c",
+  2150 => x"08ffa405",
+  2151 => x"0c8c08ff",
+  2152 => x"a8050890",
+  2153 => x"2a8c08fe",
+  2154 => x"f8050c8c",
+  2155 => x"08ffa805",
+  2156 => x"0883ffff",
+  2157 => x"068c08fe",
+  2158 => x"fc050c8c",
+  2159 => x"08ff9c05",
+  2160 => x"088c08fe",
+  2161 => x"f8050857",
+  2162 => x"70565152",
+  2163 => x"5255558a",
+  2164 => x"c03f8008",
+  2165 => x"708c08ff",
+  2166 => x"88050c8c",
+  2167 => x"08fef805",
+  2168 => x"08538c08",
+  2169 => x"ff9c0508",
+  2170 => x"52548a80",
+  2171 => x"3f800870",
+  2172 => x"8c08ff80",
+  2173 => x"050c8c08",
+  2174 => x"ff800508",
+  2175 => x"8c08fefc",
+  2176 => x"05082970",
+  2177 => x"8c08fee8",
+  2178 => x"050c8c08",
+  2179 => x"ff880508",
+  2180 => x"70902b8c",
+  2181 => x"08ffa005",
+  2182 => x"08902a70",
+  2183 => x"72078c08",
+  2184 => x"ff88050c",
+  2185 => x"52585151",
+  2186 => x"548c08ff",
+  2187 => x"8805088c",
+  2188 => x"08fee805",
+  2189 => x"082780e1",
+  2190 => x"388c08ff",
+  2191 => x"800508ff",
+  2192 => x"058c08ff",
+  2193 => x"80050c8c",
+  2194 => x"08ff8805",
+  2195 => x"088c08ff",
+  2196 => x"a8050805",
+  2197 => x"8c08ff88",
+  2198 => x"050c8c08",
+  2199 => x"ffa80508",
+  2200 => x"8c08ff88",
+  2201 => x"050826b1",
+  2202 => x"388c08ff",
+  2203 => x"8805088c",
+  2204 => x"08fee805",
+  2205 => x"0827a238",
+  2206 => x"8c08ff80",
+  2207 => x"0508ff05",
+  2208 => x"8c08ff80",
+  2209 => x"050c8c08",
+  2210 => x"ff880508",
+  2211 => x"8c08ffa8",
+  2212 => x"0508058c",
+  2213 => x"08ff8805",
+  2214 => x"0c8c08ff",
+  2215 => x"8805088c",
+  2216 => x"08fee805",
+  2217 => x"08318c08",
+  2218 => x"ff88050c",
+  2219 => x"8c08ff88",
+  2220 => x"05088c08",
+  2221 => x"fef80508",
+  2222 => x"53705254",
+  2223 => x"88d33f80",
+  2224 => x"08708c08",
+  2225 => x"feec050c",
+  2226 => x"8c08fef8",
+  2227 => x"0508538c",
+  2228 => x"08ff8805",
+  2229 => x"08525488",
+  2230 => x"933f8008",
+  2231 => x"708c08ff",
+  2232 => x"84050c8c",
+  2233 => x"08ff8405",
+  2234 => x"088c08fe",
+  2235 => x"fc050829",
+  2236 => x"708c08fe",
+  2237 => x"e8050c8c",
+  2238 => x"08feec05",
+  2239 => x"0870902b",
+  2240 => x"8c08ffa0",
+  2241 => x"050883ff",
+  2242 => x"ff067072",
+  2243 => x"078c08fe",
+  2244 => x"ec050c52",
+  2245 => x"58515154",
+  2246 => x"8c08feec",
+  2247 => x"05088c08",
+  2248 => x"fee80508",
+  2249 => x"2780e138",
+  2250 => x"8c08ff84",
+  2251 => x"0508ff05",
+  2252 => x"8c08ff84",
+  2253 => x"050c8c08",
+  2254 => x"feec0508",
+  2255 => x"8c08ffa8",
+  2256 => x"0508058c",
+  2257 => x"08feec05",
+  2258 => x"0c8c08ff",
+  2259 => x"a805088c",
+  2260 => x"08feec05",
+  2261 => x"0826b138",
+  2262 => x"8c08feec",
+  2263 => x"05088c08",
+  2264 => x"fee80508",
+  2265 => x"27a2388c",
+  2266 => x"08ff8405",
+  2267 => x"08ff058c",
+  2268 => x"08ff8405",
+  2269 => x"0c8c08fe",
+  2270 => x"ec05088c",
+  2271 => x"08ffa805",
+  2272 => x"08058c08",
+  2273 => x"feec050c",
+  2274 => x"8c08feec",
+  2275 => x"05088c08",
+  2276 => x"fee80508",
+  2277 => x"318c08fe",
+  2278 => x"ec050c8c",
+  2279 => x"08ff8005",
+  2280 => x"0870902b",
+  2281 => x"708c08ff",
+  2282 => x"84050807",
+  2283 => x"8c08ff98",
+  2284 => x"050c8c08",
+  2285 => x"feec0508",
+  2286 => x"8c08ffa0",
+  2287 => x"050c8c08",
+  2288 => x"ff980508",
+  2289 => x"83ffff06",
+  2290 => x"8c08ff80",
+  2291 => x"050c8c08",
+  2292 => x"ff980508",
+  2293 => x"902a8c08",
+  2294 => x"ff88050c",
+  2295 => x"8c08ffac",
+  2296 => x"050883ff",
+  2297 => x"ff068c08",
+  2298 => x"ff84050c",
+  2299 => x"8c08ffac",
+  2300 => x"0508902a",
+  2301 => x"8c08fee4",
+  2302 => x"050c8c08",
+  2303 => x"ff800508",
+  2304 => x"8c08ff84",
+  2305 => x"05082970",
+  2306 => x"8c08fee8",
+  2307 => x"050c8c08",
+  2308 => x"ff800508",
+  2309 => x"8c08fee4",
+  2310 => x"05082970",
+  2311 => x"8c08feec",
+  2312 => x"050c8c08",
+  2313 => x"ff880508",
+  2314 => x"8c08ff84",
+  2315 => x"05082970",
+  2316 => x"8c08fef8",
+  2317 => x"050c8c08",
+  2318 => x"ff880508",
+  2319 => x"8c08fee4",
+  2320 => x"05082970",
+  2321 => x"8c08fefc",
+  2322 => x"050c8c08",
+  2323 => x"fee80508",
+  2324 => x"902a8c08",
+  2325 => x"feec0508",
+  2326 => x"118c08fe",
+  2327 => x"ec050c8c",
+  2328 => x"08feec05",
+  2329 => x"088c08fe",
+  2330 => x"f8050805",
+  2331 => x"8c08feec",
+  2332 => x"050c5151",
+  2333 => x"51515151",
+  2334 => x"548c08fe",
+  2335 => x"ec05088c",
+  2336 => x"08fef805",
+  2337 => x"08279138",
+  2338 => x"8c08fefc",
+  2339 => x"05088480",
+  2340 => x"80058c08",
+  2341 => x"fefc050c",
+  2342 => x"8c08feec",
+  2343 => x"0508902a",
+  2344 => x"8c08fefc",
+  2345 => x"0508118c",
+  2346 => x"08fef005",
+  2347 => x"0c8c08fe",
+  2348 => x"ec050883",
+  2349 => x"ffff0670",
+  2350 => x"902b8c08",
+  2351 => x"fee80508",
+  2352 => x"83ffff06",
+  2353 => x"70128c08",
+  2354 => x"fef4050c",
+  2355 => x"52575154",
+  2356 => x"8c08fef0",
+  2357 => x"05088c08",
+  2358 => x"ffa00508",
+  2359 => x"26a6388c",
+  2360 => x"08fef005",
+  2361 => x"088c08ff",
+  2362 => x"a005082e",
+  2363 => x"09810680",
+  2364 => x"fe388c08",
+  2365 => x"fef40508",
+  2366 => x"8c08ffa4",
+  2367 => x"05082684",
+  2368 => x"3880ec39",
+  2369 => x"8c08ff98",
+  2370 => x"0508ff05",
+  2371 => x"8c08ff98",
+  2372 => x"050c8c08",
+  2373 => x"fef40508",
+  2374 => x"8c08ffac",
+  2375 => x"0508318c",
+  2376 => x"08fee405",
+  2377 => x"0c8c08fe",
+  2378 => x"f005088c",
+  2379 => x"08ffa805",
+  2380 => x"0831708c",
+  2381 => x"08fec805",
+  2382 => x"0c548c08",
+  2383 => x"fef40508",
+  2384 => x"8c08fee4",
+  2385 => x"0508278f",
+  2386 => x"388c08fe",
+  2387 => x"c80508ff",
+  2388 => x"058c08fe",
+  2389 => x"c8050c8c",
+  2390 => x"08fec805",
+  2391 => x"088c08fe",
+  2392 => x"f0050c8c",
+  2393 => x"08fee405",
+  2394 => x"088c08fe",
+  2395 => x"f4050c80",
+  2396 => x"0b8c08ff",
+  2397 => x"94050c8c",
+  2398 => x"08c80508",
+  2399 => x"802e81b1",
+  2400 => x"388c08ff",
+  2401 => x"a405088c",
+  2402 => x"08fef405",
+  2403 => x"08318c08",
+  2404 => x"fee4050c",
+  2405 => x"8c08ffa0",
+  2406 => x"05088c08",
+  2407 => x"fef00508",
+  2408 => x"31708c08",
+  2409 => x"fec4050c",
+  2410 => x"548c08ff",
+  2411 => x"a405088c",
+  2412 => x"08fee405",
+  2413 => x"08278f38",
+  2414 => x"8c08fec4",
+  2415 => x"0508ff05",
+  2416 => x"8c08fec4",
+  2417 => x"050c8c08",
+  2418 => x"fec40508",
+  2419 => x"8c08ffa0",
+  2420 => x"050c8c08",
+  2421 => x"fee40508",
+  2422 => x"8c08ffa4",
+  2423 => x"050c8c08",
+  2424 => x"ffa00508",
+  2425 => x"8c08ff90",
+  2426 => x"05082b8c",
+  2427 => x"08ffa405",
+  2428 => x"088c08ff",
+  2429 => x"8c05082a",
+  2430 => x"7072078c",
+  2431 => x"08ffb405",
+  2432 => x"0c8c08ff",
+  2433 => x"a005088c",
+  2434 => x"08ff8c05",
+  2435 => x"082a8c08",
+  2436 => x"ffb0050c",
+  2437 => x"8c08c805",
+  2438 => x"08585555",
+  2439 => x"8c08ffb0",
+  2440 => x"05088c08",
+  2441 => x"ffb40508",
+  2442 => x"56547376",
+  2443 => x"0c748417",
+  2444 => x"0c800b8c",
+  2445 => x"08fedc05",
+  2446 => x"0c800b8c",
+  2447 => x"08fee005",
+  2448 => x"0c8c08ff",
+  2449 => x"9405088c",
+  2450 => x"08fedc05",
+  2451 => x"0c8c08ff",
+  2452 => x"9805088c",
+  2453 => x"08fee005",
+  2454 => x"0c8c08fe",
+  2455 => x"dc05088c",
+  2456 => x"08fee005",
+  2457 => x"08565473",
+  2458 => x"8c08c005",
+  2459 => x"0c748c08",
+  2460 => x"c4050c8c",
+  2461 => x"08c00508",
+  2462 => x"8c08c405",
+  2463 => x"08565473",
+  2464 => x"8c08dc05",
+  2465 => x"0c748c08",
+  2466 => x"e0050c8c",
+  2467 => x"08fc0508",
+  2468 => x"802eb338",
+  2469 => x"8c08c005",
+  2470 => x"548c08dc",
+  2471 => x"05088c08",
+  2472 => x"e0050857",
+  2473 => x"55745275",
+  2474 => x"537351d8",
+  2475 => x"d73f8c08",
+  2476 => x"c005088c",
+  2477 => x"08c40508",
+  2478 => x"5654738c",
+  2479 => x"08dc050c",
+  2480 => x"748c08e0",
+  2481 => x"050c8c08",
+  2482 => x"dc05088c",
+  2483 => x"08e00508",
+  2484 => x"8c088805",
+  2485 => x"08585654",
+  2486 => x"73760c74",
+  2487 => x"84170c8c",
+  2488 => x"08880508",
+  2489 => x"800cb63d",
+  2490 => x"0d8c0c04",
+  2491 => x"8c08028c",
+  2492 => x"0cfd3d0d",
+  2493 => x"80538c08",
+  2494 => x"8c050852",
+  2495 => x"8c088805",
+  2496 => x"085182de",
+  2497 => x"3f800870",
+  2498 => x"800c5485",
+  2499 => x"3d0d8c0c",
+  2500 => x"048c0802",
+  2501 => x"8c0cfd3d",
+  2502 => x"0d81538c",
+  2503 => x"088c0508",
+  2504 => x"528c0888",
+  2505 => x"05085182",
+  2506 => x"b93f8008",
+  2507 => x"70800c54",
+  2508 => x"853d0d8c",
+  2509 => x"0c048c08",
+  2510 => x"028c0cf9",
+  2511 => x"3d0d800b",
+  2512 => x"8c08fc05",
+  2513 => x"0c8c0888",
+  2514 => x"05088025",
+  2515 => x"ab388c08",
+  2516 => x"88050830",
+  2517 => x"8c088805",
+  2518 => x"0c800b8c",
+  2519 => x"08f4050c",
+  2520 => x"8c08fc05",
+  2521 => x"08883881",
+  2522 => x"0b8c08f4",
+  2523 => x"050c8c08",
+  2524 => x"f405088c",
+  2525 => x"08fc050c",
+  2526 => x"8c088c05",
+  2527 => x"088025ab",
+  2528 => x"388c088c",
+  2529 => x"0508308c",
+  2530 => x"088c050c",
+  2531 => x"800b8c08",
+  2532 => x"f0050c8c",
+  2533 => x"08fc0508",
+  2534 => x"8838810b",
+  2535 => x"8c08f005",
+  2536 => x"0c8c08f0",
+  2537 => x"05088c08",
+  2538 => x"fc050c80",
+  2539 => x"538c088c",
+  2540 => x"0508528c",
+  2541 => x"08880508",
+  2542 => x"5181a73f",
+  2543 => x"8008708c",
+  2544 => x"08f8050c",
+  2545 => x"548c08fc",
+  2546 => x"0508802e",
+  2547 => x"8c388c08",
+  2548 => x"f8050830",
+  2549 => x"8c08f805",
+  2550 => x"0c8c08f8",
+  2551 => x"05087080",
+  2552 => x"0c54893d",
+  2553 => x"0d8c0c04",
+  2554 => x"8c08028c",
+  2555 => x"0cfb3d0d",
+  2556 => x"800b8c08",
+  2557 => x"fc050c8c",
+  2558 => x"08880508",
+  2559 => x"80259338",
+  2560 => x"8c088805",
+  2561 => x"08308c08",
+  2562 => x"88050c81",
+  2563 => x"0b8c08fc",
+  2564 => x"050c8c08",
+  2565 => x"8c050880",
+  2566 => x"258c388c",
+  2567 => x"088c0508",
+  2568 => x"308c088c",
+  2569 => x"050c8153",
+  2570 => x"8c088c05",
+  2571 => x"08528c08",
+  2572 => x"88050851",
+  2573 => x"ad3f8008",
+  2574 => x"708c08f8",
+  2575 => x"050c548c",
+  2576 => x"08fc0508",
+  2577 => x"802e8c38",
+  2578 => x"8c08f805",
+  2579 => x"08308c08",
+  2580 => x"f8050c8c",
+  2581 => x"08f80508",
+  2582 => x"70800c54",
+  2583 => x"873d0d8c",
+  2584 => x"0c048c08",
+  2585 => x"028c0cfd",
+  2586 => x"3d0d810b",
+  2587 => x"8c08fc05",
+  2588 => x"0c800b8c",
+  2589 => x"08f8050c",
+  2590 => x"8c088c05",
+  2591 => x"088c0888",
+  2592 => x"050827ac",
+  2593 => x"388c08fc",
+  2594 => x"0508802e",
+  2595 => x"a338800b",
+  2596 => x"8c088c05",
+  2597 => x"08249938",
+  2598 => x"8c088c05",
+  2599 => x"08108c08",
+  2600 => x"8c050c8c",
+  2601 => x"08fc0508",
+  2602 => x"108c08fc",
+  2603 => x"050cc939",
+  2604 => x"8c08fc05",
+  2605 => x"08802e80",
+  2606 => x"c9388c08",
+  2607 => x"8c05088c",
+  2608 => x"08880508",
+  2609 => x"26a1388c",
+  2610 => x"08880508",
+  2611 => x"8c088c05",
+  2612 => x"08318c08",
+  2613 => x"88050c8c",
+  2614 => x"08f80508",
+  2615 => x"8c08fc05",
+  2616 => x"08078c08",
+  2617 => x"f8050c8c",
+  2618 => x"08fc0508",
+  2619 => x"812a8c08",
+  2620 => x"fc050c8c",
+  2621 => x"088c0508",
+  2622 => x"812a8c08",
+  2623 => x"8c050cff",
+  2624 => x"af398c08",
+  2625 => x"90050880",
+  2626 => x"2e8f388c",
+  2627 => x"08880508",
+  2628 => x"708c08f4",
+  2629 => x"050c518d",
+  2630 => x"398c08f8",
+  2631 => x"0508708c",
+  2632 => x"08f4050c",
+  2633 => x"518c08f4",
+  2634 => x"0508800c",
+  2635 => x"853d0d8c",
+  2636 => x"0c04ff3d",
+  2637 => x"0d735281",
+  2638 => x"81c80851",
+  2639 => x"963f833d",
+  2640 => x"0d04ff3d",
+  2641 => x"0d735281",
+  2642 => x"81c80851",
+  2643 => x"90953f83",
+  2644 => x"3d0d04f3",
+  2645 => x"3d0d7f61",
+  2646 => x"8b1170f8",
+  2647 => x"065c5555",
+  2648 => x"5e729626",
+  2649 => x"83389059",
+  2650 => x"80792474",
+  2651 => x"7a260753",
+  2652 => x"80547274",
+  2653 => x"2e098106",
+  2654 => x"80cb387d",
+  2655 => x"518ce33f",
+  2656 => x"7883f726",
+  2657 => x"80c63878",
+  2658 => x"832a7010",
+  2659 => x"101080f9",
+  2660 => x"c0058c11",
+  2661 => x"0859595a",
+  2662 => x"76782e83",
+  2663 => x"b0388417",
+  2664 => x"08fc0656",
+  2665 => x"8c170888",
+  2666 => x"1808718c",
+  2667 => x"120c8812",
+  2668 => x"0c587517",
+  2669 => x"84110881",
+  2670 => x"0784120c",
+  2671 => x"537d518c",
+  2672 => x"a23f8817",
+  2673 => x"5473800c",
+  2674 => x"8f3d0d04",
+  2675 => x"78892a79",
+  2676 => x"832a5b53",
+  2677 => x"72802ebf",
+  2678 => x"3878862a",
+  2679 => x"b8055a84",
+  2680 => x"7327b438",
+  2681 => x"80db135a",
+  2682 => x"947327ab",
+  2683 => x"38788c2a",
+  2684 => x"80ee055a",
+  2685 => x"80d47327",
+  2686 => x"9e38788f",
+  2687 => x"2a80f705",
+  2688 => x"5a82d473",
+  2689 => x"27913878",
+  2690 => x"922a80fc",
+  2691 => x"055a8ad4",
+  2692 => x"73278438",
+  2693 => x"80fe5a79",
+  2694 => x"10101080",
+  2695 => x"f9c0058c",
+  2696 => x"11085855",
+  2697 => x"76752ea3",
+  2698 => x"38841708",
+  2699 => x"fc06707a",
+  2700 => x"31555673",
+  2701 => x"8f2488d5",
+  2702 => x"38738025",
+  2703 => x"fee6388c",
+  2704 => x"17085776",
+  2705 => x"752e0981",
+  2706 => x"06df3881",
+  2707 => x"1a5a80f9",
+  2708 => x"d0085776",
+  2709 => x"80f9c82e",
+  2710 => x"82c03884",
+  2711 => x"1708fc06",
+  2712 => x"707a3155",
+  2713 => x"56738f24",
+  2714 => x"81f93880",
+  2715 => x"f9c80b80",
+  2716 => x"f9d40c80",
+  2717 => x"f9c80b80",
+  2718 => x"f9d00c73",
+  2719 => x"8025feb2",
+  2720 => x"3883ff76",
+  2721 => x"2783df38",
+  2722 => x"75892a76",
+  2723 => x"832a5553",
+  2724 => x"72802ebf",
+  2725 => x"3875862a",
+  2726 => x"b8055484",
+  2727 => x"7327b438",
+  2728 => x"80db1354",
+  2729 => x"947327ab",
+  2730 => x"38758c2a",
+  2731 => x"80ee0554",
+  2732 => x"80d47327",
+  2733 => x"9e38758f",
+  2734 => x"2a80f705",
+  2735 => x"5482d473",
+  2736 => x"27913875",
+  2737 => x"922a80fc",
+  2738 => x"05548ad4",
+  2739 => x"73278438",
+  2740 => x"80fe5473",
+  2741 => x"10101080",
+  2742 => x"f9c00588",
+  2743 => x"11085658",
+  2744 => x"74782e86",
+  2745 => x"cf388415",
+  2746 => x"08fc0653",
+  2747 => x"7573278d",
+  2748 => x"38881508",
+  2749 => x"5574782e",
+  2750 => x"098106ea",
+  2751 => x"388c1508",
+  2752 => x"80f9c00b",
+  2753 => x"84050871",
+  2754 => x"8c1a0c76",
+  2755 => x"881a0c78",
+  2756 => x"88130c78",
+  2757 => x"8c180c5d",
+  2758 => x"58795380",
+  2759 => x"7a2483e6",
+  2760 => x"3872822c",
+  2761 => x"81712b5c",
+  2762 => x"537a7c26",
+  2763 => x"8198387b",
+  2764 => x"7b065372",
+  2765 => x"82f13879",
+  2766 => x"fc068405",
+  2767 => x"5a7a1070",
+  2768 => x"7d06545b",
+  2769 => x"7282e038",
+  2770 => x"841a5af1",
+  2771 => x"3988178c",
+  2772 => x"11085858",
+  2773 => x"76782e09",
+  2774 => x"8106fcc2",
+  2775 => x"38821a5a",
+  2776 => x"fdec3978",
+  2777 => x"17798107",
+  2778 => x"84190c70",
+  2779 => x"80f9d40c",
+  2780 => x"7080f9d0",
+  2781 => x"0c80f9c8",
+  2782 => x"0b8c120c",
+  2783 => x"8c110888",
+  2784 => x"120c7481",
+  2785 => x"0784120c",
+  2786 => x"74117571",
+  2787 => x"0c51537d",
+  2788 => x"5188d03f",
+  2789 => x"881754fc",
+  2790 => x"ac3980f9",
+  2791 => x"c00b8405",
+  2792 => x"087a545c",
+  2793 => x"798025fe",
+  2794 => x"f83882da",
+  2795 => x"397a097c",
+  2796 => x"067080f9",
+  2797 => x"c00b8405",
+  2798 => x"0c5c7a10",
+  2799 => x"5b7a7c26",
+  2800 => x"85387a85",
+  2801 => x"b83880f9",
+  2802 => x"c00b8805",
+  2803 => x"08708412",
+  2804 => x"08fc0670",
+  2805 => x"7c317c72",
+  2806 => x"268f7225",
+  2807 => x"0757575c",
+  2808 => x"5d557280",
+  2809 => x"2e80db38",
+  2810 => x"797a1680",
+  2811 => x"f9b8081b",
+  2812 => x"90115a55",
+  2813 => x"575b80f9",
+  2814 => x"b408ff2e",
+  2815 => x"8838a08f",
+  2816 => x"13e08006",
+  2817 => x"5776527d",
+  2818 => x"5187d93f",
+  2819 => x"80085480",
+  2820 => x"08ff2e90",
+  2821 => x"38800876",
+  2822 => x"27829938",
+  2823 => x"7480f9c0",
+  2824 => x"2e829138",
+  2825 => x"80f9c00b",
+  2826 => x"88050855",
+  2827 => x"841508fc",
+  2828 => x"06707a31",
+  2829 => x"7a72268f",
+  2830 => x"72250752",
+  2831 => x"55537283",
+  2832 => x"e6387479",
+  2833 => x"81078417",
+  2834 => x"0c791670",
+  2835 => x"80f9c00b",
+  2836 => x"88050c75",
+  2837 => x"81078412",
+  2838 => x"0c547e52",
+  2839 => x"5787843f",
+  2840 => x"881754fa",
+  2841 => x"e0397583",
+  2842 => x"2a705454",
+  2843 => x"80742481",
+  2844 => x"9b387282",
+  2845 => x"2c81712b",
+  2846 => x"80f9c408",
+  2847 => x"077080f9",
+  2848 => x"c00b8405",
+  2849 => x"0c751010",
+  2850 => x"1080f9c0",
+  2851 => x"05881108",
+  2852 => x"585a5d53",
+  2853 => x"778c180c",
+  2854 => x"7488180c",
+  2855 => x"7688190c",
+  2856 => x"768c160c",
+  2857 => x"fcf33979",
+  2858 => x"7a101010",
+  2859 => x"80f9c005",
+  2860 => x"7057595d",
+  2861 => x"8c150857",
+  2862 => x"76752ea3",
+  2863 => x"38841708",
+  2864 => x"fc06707a",
+  2865 => x"31555673",
+  2866 => x"8f2483ca",
+  2867 => x"38738025",
+  2868 => x"8481388c",
+  2869 => x"17085776",
+  2870 => x"752e0981",
+  2871 => x"06df3888",
+  2872 => x"15811b70",
+  2873 => x"8306555b",
+  2874 => x"5572c938",
+  2875 => x"7c830653",
+  2876 => x"72802efd",
+  2877 => x"b838ff1d",
+  2878 => x"f819595d",
+  2879 => x"88180878",
+  2880 => x"2eea38fd",
+  2881 => x"b539831a",
+  2882 => x"53fc9639",
+  2883 => x"83147082",
+  2884 => x"2c81712b",
+  2885 => x"80f9c408",
+  2886 => x"077080f9",
+  2887 => x"c00b8405",
+  2888 => x"0c761010",
+  2889 => x"1080f9c0",
+  2890 => x"05881108",
+  2891 => x"595b5e51",
+  2892 => x"53fee139",
+  2893 => x"80f98408",
+  2894 => x"17588008",
+  2895 => x"762e818d",
+  2896 => x"3880f9b4",
+  2897 => x"08ff2e83",
+  2898 => x"ec387376",
+  2899 => x"311880f9",
+  2900 => x"840c7387",
+  2901 => x"06705753",
+  2902 => x"72802e88",
+  2903 => x"38887331",
+  2904 => x"70155556",
+  2905 => x"76149fff",
+  2906 => x"06a08071",
+  2907 => x"31177054",
+  2908 => x"7f535753",
+  2909 => x"84ee3f80",
+  2910 => x"08538008",
+  2911 => x"ff2e81a0",
+  2912 => x"3880f984",
+  2913 => x"08167080",
+  2914 => x"f9840c74",
+  2915 => x"7580f9c0",
+  2916 => x"0b88050c",
+  2917 => x"74763118",
+  2918 => x"70810751",
+  2919 => x"5556587b",
+  2920 => x"80f9c02e",
+  2921 => x"839c3879",
+  2922 => x"8f2682cb",
+  2923 => x"38810b84",
+  2924 => x"150c8415",
+  2925 => x"08fc0670",
+  2926 => x"7a317a72",
+  2927 => x"268f7225",
+  2928 => x"07525553",
+  2929 => x"72802efc",
+  2930 => x"f93880db",
+  2931 => x"3980089f",
+  2932 => x"ff065372",
+  2933 => x"feeb3877",
+  2934 => x"80f9840c",
+  2935 => x"80f9c00b",
+  2936 => x"8805087b",
+  2937 => x"18810784",
+  2938 => x"120c5580",
+  2939 => x"f9b00878",
+  2940 => x"27863877",
+  2941 => x"80f9b00c",
+  2942 => x"80f9ac08",
+  2943 => x"7827fcac",
+  2944 => x"387780f9",
+  2945 => x"ac0c8415",
+  2946 => x"08fc0670",
+  2947 => x"7a317a72",
+  2948 => x"268f7225",
+  2949 => x"07525553",
+  2950 => x"72802efc",
+  2951 => x"a5388839",
+  2952 => x"80745456",
+  2953 => x"fedb397d",
+  2954 => x"5183b83f",
+  2955 => x"800b800c",
+  2956 => x"8f3d0d04",
+  2957 => x"73538074",
+  2958 => x"24a93872",
+  2959 => x"822c8171",
+  2960 => x"2b80f9c4",
+  2961 => x"08077080",
+  2962 => x"f9c00b84",
+  2963 => x"050c5d53",
+  2964 => x"778c180c",
+  2965 => x"7488180c",
+  2966 => x"7688190c",
+  2967 => x"768c160c",
+  2968 => x"f9b73983",
+  2969 => x"1470822c",
+  2970 => x"81712b80",
+  2971 => x"f9c40807",
+  2972 => x"7080f9c0",
+  2973 => x"0b84050c",
+  2974 => x"5e5153d4",
+  2975 => x"397b7b06",
+  2976 => x"5372fca3",
+  2977 => x"38841a7b",
+  2978 => x"105c5af1",
+  2979 => x"39ff1a81",
+  2980 => x"11515af7",
+  2981 => x"b9397817",
+  2982 => x"79810784",
+  2983 => x"190c8c18",
+  2984 => x"08881908",
+  2985 => x"718c120c",
+  2986 => x"88120c59",
+  2987 => x"7080f9d4",
+  2988 => x"0c7080f9",
+  2989 => x"d00c80f9",
+  2990 => x"c80b8c12",
+  2991 => x"0c8c1108",
+  2992 => x"88120c74",
+  2993 => x"81078412",
+  2994 => x"0c741175",
+  2995 => x"710c5153",
+  2996 => x"f9bd3975",
+  2997 => x"17841108",
+  2998 => x"81078412",
+  2999 => x"0c538c17",
+  3000 => x"08881808",
+  3001 => x"718c120c",
+  3002 => x"88120c58",
+  3003 => x"7d5181f3",
+  3004 => x"3f881754",
+  3005 => x"f5cf3972",
+  3006 => x"84150cf4",
+  3007 => x"1af80670",
+  3008 => x"841e0881",
+  3009 => x"0607841e",
+  3010 => x"0c701d54",
+  3011 => x"5b850b84",
+  3012 => x"140c850b",
+  3013 => x"88140c8f",
+  3014 => x"7b27fdcf",
+  3015 => x"38881c52",
+  3016 => x"7d5184bf",
+  3017 => x"3f80f9c0",
+  3018 => x"0b880508",
+  3019 => x"80f98408",
+  3020 => x"5955fdb7",
+  3021 => x"397780f9",
+  3022 => x"840c7380",
+  3023 => x"f9b40cfc",
+  3024 => x"91397284",
+  3025 => x"150cfda3",
+  3026 => x"39fc3d0d",
+  3027 => x"7670797b",
+  3028 => x"55555555",
+  3029 => x"8f72278c",
+  3030 => x"38727507",
+  3031 => x"83065170",
+  3032 => x"802ea738",
+  3033 => x"ff125271",
+  3034 => x"ff2e9838",
+  3035 => x"72708105",
+  3036 => x"54337470",
+  3037 => x"81055634",
+  3038 => x"ff125271",
+  3039 => x"ff2e0981",
+  3040 => x"06ea3874",
+  3041 => x"800c863d",
+  3042 => x"0d047451",
+  3043 => x"72708405",
+  3044 => x"54087170",
+  3045 => x"8405530c",
+  3046 => x"72708405",
+  3047 => x"54087170",
+  3048 => x"8405530c",
+  3049 => x"72708405",
+  3050 => x"54087170",
+  3051 => x"8405530c",
+  3052 => x"72708405",
+  3053 => x"54087170",
+  3054 => x"8405530c",
+  3055 => x"f0125271",
+  3056 => x"8f26c938",
+  3057 => x"83722795",
+  3058 => x"38727084",
+  3059 => x"05540871",
+  3060 => x"70840553",
+  3061 => x"0cfc1252",
+  3062 => x"718326ed",
+  3063 => x"387054ff",
+  3064 => x"83390404",
+  3065 => x"fd3d0d80",
+  3066 => x"0b81d998",
+  3067 => x"0c765187",
+  3068 => x"c83f8008",
+  3069 => x"538008ff",
+  3070 => x"2e883872",
+  3071 => x"800c853d",
+  3072 => x"0d0481d9",
+  3073 => x"98085473",
+  3074 => x"802ef038",
+  3075 => x"7574710c",
+  3076 => x"5272800c",
+  3077 => x"853d0d04",
+  3078 => x"fb3d0d77",
+  3079 => x"79707207",
+  3080 => x"83065354",
+  3081 => x"52709338",
+  3082 => x"71737308",
+  3083 => x"54565471",
+  3084 => x"73082e80",
+  3085 => x"c4387375",
+  3086 => x"54527133",
+  3087 => x"7081ff06",
+  3088 => x"52547080",
+  3089 => x"2e9d3872",
+  3090 => x"33557075",
+  3091 => x"2e098106",
+  3092 => x"95388112",
+  3093 => x"81147133",
+  3094 => x"7081ff06",
+  3095 => x"54565452",
+  3096 => x"70e53872",
+  3097 => x"33557381",
+  3098 => x"ff067581",
+  3099 => x"ff067171",
+  3100 => x"31800c52",
+  3101 => x"52873d0d",
+  3102 => x"04710970",
+  3103 => x"f7fbfdff",
+  3104 => x"140670f8",
+  3105 => x"84828180",
+  3106 => x"06515151",
+  3107 => x"70973884",
+  3108 => x"14841671",
+  3109 => x"08545654",
+  3110 => x"7175082e",
+  3111 => x"dc387375",
+  3112 => x"5452ff96",
+  3113 => x"39800b80",
+  3114 => x"0c873d0d",
+  3115 => x"04fb3d0d",
+  3116 => x"77705256",
+  3117 => x"feac3f80",
+  3118 => x"f9c00b88",
+  3119 => x"05088411",
+  3120 => x"08fc0670",
+  3121 => x"7b319fef",
+  3122 => x"05e08006",
+  3123 => x"e0800556",
+  3124 => x"5653a080",
+  3125 => x"74249438",
+  3126 => x"80527551",
+  3127 => x"fe863f80",
+  3128 => x"f9c80815",
+  3129 => x"53728008",
+  3130 => x"2e8f3875",
+  3131 => x"51fdf43f",
+  3132 => x"80537280",
+  3133 => x"0c873d0d",
+  3134 => x"04733052",
+  3135 => x"7551fde4",
+  3136 => x"3f8008ff",
+  3137 => x"2ea83880",
+  3138 => x"f9c00b88",
+  3139 => x"05087575",
+  3140 => x"31810784",
+  3141 => x"120c5380",
+  3142 => x"f9840874",
+  3143 => x"3180f984",
+  3144 => x"0c7551fd",
+  3145 => x"be3f810b",
+  3146 => x"800c873d",
+  3147 => x"0d048052",
+  3148 => x"7551fdb0",
+  3149 => x"3f80f9c0",
+  3150 => x"0b880508",
+  3151 => x"80087131",
+  3152 => x"56538f75",
+  3153 => x"25ffa438",
+  3154 => x"800880f9",
+  3155 => x"b4083180",
+  3156 => x"f9840c74",
+  3157 => x"81078414",
+  3158 => x"0c7551fd",
+  3159 => x"863f8053",
+  3160 => x"ff9039f6",
+  3161 => x"3d0d7c7e",
+  3162 => x"545b7280",
+  3163 => x"2e828338",
+  3164 => x"7a51fcee",
+  3165 => x"3ff81384",
+  3166 => x"110870fe",
+  3167 => x"06701384",
+  3168 => x"1108fc06",
+  3169 => x"5d585954",
+  3170 => x"5880f9c8",
+  3171 => x"08752e82",
+  3172 => x"de387884",
+  3173 => x"160c8073",
+  3174 => x"8106545a",
+  3175 => x"727a2e81",
+  3176 => x"d5387815",
+  3177 => x"84110881",
+  3178 => x"06515372",
+  3179 => x"a0387817",
+  3180 => x"577981e6",
+  3181 => x"38881508",
+  3182 => x"537280f9",
+  3183 => x"c82e82f9",
+  3184 => x"388c1508",
+  3185 => x"708c150c",
+  3186 => x"7388120c",
+  3187 => x"56768107",
+  3188 => x"84190c76",
+  3189 => x"1877710c",
+  3190 => x"53798191",
+  3191 => x"3883ff77",
+  3192 => x"2781c838",
+  3193 => x"76892a77",
+  3194 => x"832a5653",
+  3195 => x"72802ebf",
+  3196 => x"3876862a",
+  3197 => x"b8055584",
+  3198 => x"7327b438",
+  3199 => x"80db1355",
+  3200 => x"947327ab",
+  3201 => x"38768c2a",
+  3202 => x"80ee0555",
+  3203 => x"80d47327",
+  3204 => x"9e38768f",
+  3205 => x"2a80f705",
+  3206 => x"5582d473",
+  3207 => x"27913876",
+  3208 => x"922a80fc",
+  3209 => x"05558ad4",
+  3210 => x"73278438",
+  3211 => x"80fe5574",
+  3212 => x"10101080",
+  3213 => x"f9c00588",
+  3214 => x"11085556",
+  3215 => x"73762e82",
+  3216 => x"b3388414",
+  3217 => x"08fc0653",
+  3218 => x"7673278d",
+  3219 => x"38881408",
+  3220 => x"5473762e",
+  3221 => x"098106ea",
+  3222 => x"388c1408",
+  3223 => x"708c1a0c",
+  3224 => x"74881a0c",
+  3225 => x"7888120c",
+  3226 => x"56778c15",
+  3227 => x"0c7a51fa",
+  3228 => x"f23f8c3d",
+  3229 => x"0d047708",
+  3230 => x"78713159",
+  3231 => x"77058819",
+  3232 => x"08545772",
+  3233 => x"80f9c82e",
+  3234 => x"80e0388c",
+  3235 => x"1808708c",
+  3236 => x"150c7388",
+  3237 => x"120c56fe",
+  3238 => x"89398815",
+  3239 => x"088c1608",
+  3240 => x"708c130c",
+  3241 => x"5788170c",
+  3242 => x"fea33976",
+  3243 => x"832a7054",
+  3244 => x"55807524",
+  3245 => x"81983872",
+  3246 => x"822c8171",
+  3247 => x"2b80f9c4",
+  3248 => x"080780f9",
+  3249 => x"c00b8405",
+  3250 => x"0c537410",
+  3251 => x"101080f9",
+  3252 => x"c0058811",
+  3253 => x"08555675",
+  3254 => x"8c190c73",
+  3255 => x"88190c77",
+  3256 => x"88170c77",
+  3257 => x"8c150cff",
+  3258 => x"8439815a",
+  3259 => x"fdb43978",
+  3260 => x"17738106",
+  3261 => x"54577298",
+  3262 => x"38770878",
+  3263 => x"71315977",
+  3264 => x"058c1908",
+  3265 => x"881a0871",
+  3266 => x"8c120c88",
+  3267 => x"120c5757",
+  3268 => x"76810784",
+  3269 => x"190c7780",
+  3270 => x"f9c00b88",
+  3271 => x"050c80f9",
+  3272 => x"bc087726",
+  3273 => x"fec73880",
+  3274 => x"f9b80852",
+  3275 => x"7a51fafd",
+  3276 => x"3f7a51f9",
+  3277 => x"ae3ffeba",
+  3278 => x"3981788c",
+  3279 => x"150c7888",
+  3280 => x"150c738c",
+  3281 => x"1a0c7388",
+  3282 => x"1a0c5afd",
+  3283 => x"80398315",
+  3284 => x"70822c81",
+  3285 => x"712b80f9",
+  3286 => x"c4080780",
+  3287 => x"f9c00b84",
+  3288 => x"050c5153",
+  3289 => x"74101010",
+  3290 => x"80f9c005",
+  3291 => x"88110855",
+  3292 => x"56fee439",
+  3293 => x"74538075",
+  3294 => x"24a73872",
+  3295 => x"822c8171",
+  3296 => x"2b80f9c4",
+  3297 => x"080780f9",
+  3298 => x"c00b8405",
+  3299 => x"0c53758c",
+  3300 => x"190c7388",
+  3301 => x"190c7788",
+  3302 => x"170c778c",
+  3303 => x"150cfdcd",
+  3304 => x"39831570",
+  3305 => x"822c8171",
+  3306 => x"2b80f9c4",
+  3307 => x"080780f9",
+  3308 => x"c00b8405",
+  3309 => x"0c5153d6",
+  3310 => x"39fe3d0d",
+  3311 => x"8188f008",
+  3312 => x"51708a38",
+  3313 => x"81d99c70",
+  3314 => x"8188f00c",
+  3315 => x"51707512",
+  3316 => x"5252ff53",
+  3317 => x"7087fb80",
+  3318 => x"80268838",
+  3319 => x"708188f0",
+  3320 => x"0c715372",
+  3321 => x"800c843d",
+  3322 => x"0d04fd3d",
+  3323 => x"0d800b80",
+  3324 => x"f8ec0854",
+  3325 => x"5472812e",
+  3326 => x"9e387381",
+  3327 => x"88f40cff",
+  3328 => x"a0ff3fff",
+  3329 => x"9ffa3f81",
+  3330 => x"88c85281",
+  3331 => x"51ffa9ae",
+  3332 => x"3f800851",
+  3333 => x"80e13f72",
+  3334 => x"8188f40c",
+  3335 => x"ffa0e23f",
+  3336 => x"ff9fdd3f",
+  3337 => x"8188c852",
+  3338 => x"8151ffa9",
+  3339 => x"913f8008",
+  3340 => x"5180c43f",
+  3341 => x"00ff3900",
+  3342 => x"ff39f43d",
+  3343 => x"0d7e8188",
+  3344 => x"e8087008",
+  3345 => x"7081ff06",
+  3346 => x"923df805",
+  3347 => x"55515a57",
+  3348 => x"59ffa19a",
+  3349 => x"3f805477",
+  3350 => x"557b7d58",
+  3351 => x"5276538e",
+  3352 => x"3df00551",
+  3353 => x"c0c03f79",
+  3354 => x"7b58790c",
+  3355 => x"76841a0c",
+  3356 => x"78800c8e",
+  3357 => x"3d0d04f7",
+  3358 => x"3d0d7b81",
+  3359 => x"81c80882",
+  3360 => x"c811085a",
+  3361 => x"545a7780",
+  3362 => x"2e80da38",
+  3363 => x"81881884",
+  3364 => x"1908ff05",
+  3365 => x"81712b59",
+  3366 => x"55598074",
+  3367 => x"2480ea38",
+  3368 => x"807424b5",
+  3369 => x"3873822b",
+  3370 => x"78118805",
+  3371 => x"56568180",
+  3372 => x"19087706",
+  3373 => x"5372802e",
+  3374 => x"b6387816",
+  3375 => x"70085353",
+  3376 => x"79517408",
+  3377 => x"53722dff",
+  3378 => x"14fc17fc",
+  3379 => x"1779812c",
+  3380 => x"5a575754",
+  3381 => x"738025d6",
+  3382 => x"38770858",
+  3383 => x"77ffad38",
+  3384 => x"8181c808",
+  3385 => x"53bc1308",
+  3386 => x"a5387951",
+  3387 => x"fec63f74",
+  3388 => x"0853722d",
+  3389 => x"ff14fc17",
+  3390 => x"fc177981",
+  3391 => x"2c5a5757",
+  3392 => x"54738025",
+  3393 => x"ffa838d1",
+  3394 => x"398057ff",
+  3395 => x"93397251",
+  3396 => x"bc130853",
+  3397 => x"722d7951",
+  3398 => x"fe9a3fff",
+  3399 => x"3d0d8188",
+  3400 => x"d00bfc05",
+  3401 => x"70085252",
+  3402 => x"70ff2e91",
+  3403 => x"38702dfc",
+  3404 => x"12700852",
+  3405 => x"5270ff2e",
+  3406 => x"098106f1",
+  3407 => x"38833d0d",
+  3408 => x"0404ffa0",
+  3409 => x"873f0400",
+  3410 => x"00000040",
+  3411 => x"30313233",
+  3412 => x"34353637",
+  3413 => x"38390000",
+  3414 => x"44485259",
+  3415 => x"53544f4e",
+  3416 => x"45205052",
+  3417 => x"4f475241",
+  3418 => x"4d2c2053",
+  3419 => x"4f4d4520",
+  3420 => x"53545249",
+  3421 => x"4e470000",
+  3422 => x"44485259",
+  3423 => x"53544f4e",
+  3424 => x"45205052",
+  3425 => x"4f475241",
+  3426 => x"4d2c2031",
+  3427 => x"27535420",
+  3428 => x"53545249",
+  3429 => x"4e470000",
+  3430 => x"44687279",
+  3431 => x"73746f6e",
+  3432 => x"65204265",
+  3433 => x"6e63686d",
+  3434 => x"61726b2c",
+  3435 => x"20566572",
+  3436 => x"73696f6e",
+  3437 => x"20322e31",
+  3438 => x"20284c61",
+  3439 => x"6e677561",
+  3440 => x"67653a20",
+  3441 => x"43290a00",
+  3442 => x"50726f67",
+  3443 => x"72616d20",
+  3444 => x"636f6d70",
+  3445 => x"696c6564",
+  3446 => x"20776974",
+  3447 => x"68202772",
+  3448 => x"65676973",
+  3449 => x"74657227",
+  3450 => x"20617474",
+  3451 => x"72696275",
+  3452 => x"74650a00",
+  3453 => x"45786563",
+  3454 => x"7574696f",
+  3455 => x"6e207374",
+  3456 => x"61727473",
+  3457 => x"2c202564",
+  3458 => x"2072756e",
+  3459 => x"73207468",
+  3460 => x"726f7567",
+  3461 => x"68204468",
+  3462 => x"72797374",
+  3463 => x"6f6e650a",
+  3464 => x"00000000",
+  3465 => x"44485259",
+  3466 => x"53544f4e",
+  3467 => x"45205052",
+  3468 => x"4f475241",
+  3469 => x"4d2c2032",
+  3470 => x"274e4420",
+  3471 => x"53545249",
+  3472 => x"4e470000",
+  3473 => x"45786563",
+  3474 => x"7574696f",
+  3475 => x"6e20656e",
+  3476 => x"64730a00",
+  3477 => x"46696e61",
+  3478 => x"6c207661",
+  3479 => x"6c756573",
+  3480 => x"206f6620",
+  3481 => x"74686520",
+  3482 => x"76617269",
+  3483 => x"61626c65",
+  3484 => x"73207573",
+  3485 => x"65642069",
+  3486 => x"6e207468",
+  3487 => x"65206265",
+  3488 => x"6e63686d",
+  3489 => x"61726b3a",
+  3490 => x"0a000000",
+  3491 => x"496e745f",
+  3492 => x"476c6f62",
+  3493 => x"3a202020",
+  3494 => x"20202020",
+  3495 => x"20202020",
+  3496 => x"2025640a",
+  3497 => x"00000000",
+  3498 => x"20202020",
+  3499 => x"20202020",
+  3500 => x"73686f75",
+  3501 => x"6c642062",
+  3502 => x"653a2020",
+  3503 => x"2025640a",
+  3504 => x"00000000",
+  3505 => x"426f6f6c",
+  3506 => x"5f476c6f",
+  3507 => x"623a2020",
+  3508 => x"20202020",
+  3509 => x"20202020",
+  3510 => x"2025640a",
+  3511 => x"00000000",
+  3512 => x"43685f31",
+  3513 => x"5f476c6f",
+  3514 => x"623a2020",
+  3515 => x"20202020",
+  3516 => x"20202020",
+  3517 => x"2025630a",
+  3518 => x"00000000",
+  3519 => x"20202020",
+  3520 => x"20202020",
+  3521 => x"73686f75",
+  3522 => x"6c642062",
+  3523 => x"653a2020",
+  3524 => x"2025630a",
+  3525 => x"00000000",
+  3526 => x"43685f32",
+  3527 => x"5f476c6f",
+  3528 => x"623a2020",
+  3529 => x"20202020",
+  3530 => x"20202020",
+  3531 => x"2025630a",
+  3532 => x"00000000",
+  3533 => x"4172725f",
+  3534 => x"315f476c",
+  3535 => x"6f625b38",
+  3536 => x"5d3a2020",
+  3537 => x"20202020",
+  3538 => x"2025640a",
+  3539 => x"00000000",
+  3540 => x"4172725f",
+  3541 => x"325f476c",
+  3542 => x"6f625b38",
+  3543 => x"5d5b375d",
+  3544 => x"3a202020",
+  3545 => x"2025640a",
+  3546 => x"00000000",
+  3547 => x"20202020",
+  3548 => x"20202020",
+  3549 => x"73686f75",
+  3550 => x"6c642062",
+  3551 => x"653a2020",
+  3552 => x"204e756d",
+  3553 => x"6265725f",
+  3554 => x"4f665f52",
+  3555 => x"756e7320",
+  3556 => x"2b203130",
+  3557 => x"0a000000",
+  3558 => x"5074725f",
+  3559 => x"476c6f62",
+  3560 => x"2d3e0a00",
+  3561 => x"20205074",
+  3562 => x"725f436f",
+  3563 => x"6d703a20",
+  3564 => x"20202020",
+  3565 => x"20202020",
+  3566 => x"2025640a",
+  3567 => x"00000000",
+  3568 => x"20202020",
+  3569 => x"20202020",
+  3570 => x"73686f75",
+  3571 => x"6c642062",
+  3572 => x"653a2020",
+  3573 => x"2028696d",
+  3574 => x"706c656d",
+  3575 => x"656e7461",
+  3576 => x"74696f6e",
+  3577 => x"2d646570",
+  3578 => x"656e6465",
+  3579 => x"6e74290a",
+  3580 => x"00000000",
+  3581 => x"20204469",
+  3582 => x"7363723a",
+  3583 => x"20202020",
+  3584 => x"20202020",
+  3585 => x"20202020",
+  3586 => x"2025640a",
+  3587 => x"00000000",
+  3588 => x"2020456e",
+  3589 => x"756d5f43",
+  3590 => x"6f6d703a",
+  3591 => x"20202020",
+  3592 => x"20202020",
+  3593 => x"2025640a",
+  3594 => x"00000000",
+  3595 => x"2020496e",
+  3596 => x"745f436f",
+  3597 => x"6d703a20",
+  3598 => x"20202020",
+  3599 => x"20202020",
+  3600 => x"2025640a",
+  3601 => x"00000000",
+  3602 => x"20205374",
+  3603 => x"725f436f",
+  3604 => x"6d703a20",
+  3605 => x"20202020",
+  3606 => x"20202020",
+  3607 => x"2025730a",
+  3608 => x"00000000",
+  3609 => x"20202020",
+  3610 => x"20202020",
+  3611 => x"73686f75",
+  3612 => x"6c642062",
+  3613 => x"653a2020",
+  3614 => x"20444852",
+  3615 => x"5953544f",
+  3616 => x"4e452050",
+  3617 => x"524f4752",
+  3618 => x"414d2c20",
+  3619 => x"534f4d45",
+  3620 => x"20535452",
+  3621 => x"494e470a",
+  3622 => x"00000000",
+  3623 => x"4e657874",
+  3624 => x"5f507472",
+  3625 => x"5f476c6f",
+  3626 => x"622d3e0a",
+  3627 => x"00000000",
+  3628 => x"20202020",
+  3629 => x"20202020",
+  3630 => x"73686f75",
+  3631 => x"6c642062",
+  3632 => x"653a2020",
+  3633 => x"2028696d",
+  3634 => x"706c656d",
+  3635 => x"656e7461",
+  3636 => x"74696f6e",
+  3637 => x"2d646570",
+  3638 => x"656e6465",
+  3639 => x"6e74292c",
+  3640 => x"2073616d",
+  3641 => x"65206173",
+  3642 => x"2061626f",
+  3643 => x"76650a00",
+  3644 => x"496e745f",
+  3645 => x"315f4c6f",
+  3646 => x"633a2020",
+  3647 => x"20202020",
+  3648 => x"20202020",
+  3649 => x"2025640a",
+  3650 => x"00000000",
+  3651 => x"496e745f",
+  3652 => x"325f4c6f",
+  3653 => x"633a2020",
+  3654 => x"20202020",
+  3655 => x"20202020",
+  3656 => x"2025640a",
+  3657 => x"00000000",
+  3658 => x"496e745f",
+  3659 => x"335f4c6f",
+  3660 => x"633a2020",
+  3661 => x"20202020",
+  3662 => x"20202020",
+  3663 => x"2025640a",
+  3664 => x"00000000",
+  3665 => x"456e756d",
+  3666 => x"5f4c6f63",
+  3667 => x"3a202020",
+  3668 => x"20202020",
+  3669 => x"20202020",
+  3670 => x"2025640a",
+  3671 => x"00000000",
+  3672 => x"5374725f",
+  3673 => x"315f4c6f",
+  3674 => x"633a2020",
+  3675 => x"20202020",
+  3676 => x"20202020",
+  3677 => x"2025730a",
+  3678 => x"00000000",
+  3679 => x"20202020",
+  3680 => x"20202020",
+  3681 => x"73686f75",
+  3682 => x"6c642062",
+  3683 => x"653a2020",
+  3684 => x"20444852",
+  3685 => x"5953544f",
+  3686 => x"4e452050",
+  3687 => x"524f4752",
+  3688 => x"414d2c20",
+  3689 => x"31275354",
+  3690 => x"20535452",
+  3691 => x"494e470a",
+  3692 => x"00000000",
+  3693 => x"5374725f",
+  3694 => x"325f4c6f",
+  3695 => x"633a2020",
+  3696 => x"20202020",
+  3697 => x"20202020",
+  3698 => x"2025730a",
+  3699 => x"00000000",
+  3700 => x"20202020",
+  3701 => x"20202020",
+  3702 => x"73686f75",
+  3703 => x"6c642062",
+  3704 => x"653a2020",
+  3705 => x"20444852",
+  3706 => x"5953544f",
+  3707 => x"4e452050",
+  3708 => x"524f4752",
+  3709 => x"414d2c20",
+  3710 => x"32274e44",
+  3711 => x"20535452",
+  3712 => x"494e470a",
+  3713 => x"00000000",
+  3714 => x"55736572",
+  3715 => x"2074696d",
+  3716 => x"653a2025",
+  3717 => x"640a0000",
+  3718 => x"4d696372",
+  3719 => x"6f736563",
+  3720 => x"6f6e6473",
+  3721 => x"20666f72",
+  3722 => x"206f6e65",
+  3723 => x"2072756e",
+  3724 => x"20746872",
+  3725 => x"6f756768",
+  3726 => x"20446872",
+  3727 => x"7973746f",
+  3728 => x"6e653a20",
+  3729 => x"00000000",
+  3730 => x"2564200a",
+  3731 => x"00000000",
+  3732 => x"44687279",
+  3733 => x"73746f6e",
+  3734 => x"65732070",
+  3735 => x"65722053",
+  3736 => x"65636f6e",
+  3737 => x"643a2020",
+  3738 => x"20202020",
+  3739 => x"20202020",
+  3740 => x"20202020",
+  3741 => x"20202020",
+  3742 => x"20202020",
+  3743 => x"00000000",
+  3744 => x"56415820",
+  3745 => x"4d495053",
+  3746 => x"20726174",
+  3747 => x"696e6720",
+  3748 => x"2a203130",
+  3749 => x"3030203d",
+  3750 => x"20256420",
+  3751 => x"0a000000",
+  3752 => x"50726f67",
+  3753 => x"72616d20",
+  3754 => x"636f6d70",
+  3755 => x"696c6564",
+  3756 => x"20776974",
+  3757 => x"686f7574",
+  3758 => x"20277265",
+  3759 => x"67697374",
+  3760 => x"65722720",
+  3761 => x"61747472",
+  3762 => x"69627574",
+  3763 => x"650a0000",
+  3764 => x"4d656173",
+  3765 => x"75726564",
+  3766 => x"2074696d",
+  3767 => x"6520746f",
+  3768 => x"6f20736d",
+  3769 => x"616c6c20",
+  3770 => x"746f206f",
+  3771 => x"62746169",
+  3772 => x"6e206d65",
+  3773 => x"616e696e",
+  3774 => x"6766756c",
+  3775 => x"20726573",
+  3776 => x"756c7473",
+  3777 => x"0a000000",
+  3778 => x"506c6561",
+  3779 => x"73652069",
+  3780 => x"6e637265",
+  3781 => x"61736520",
+  3782 => x"6e756d62",
+  3783 => x"6572206f",
+  3784 => x"66207275",
+  3785 => x"6e730a00",
+  3786 => x"44485259",
+  3787 => x"53544f4e",
+  3788 => x"45205052",
+  3789 => x"4f475241",
+  3790 => x"4d2c2033",
+  3791 => x"27524420",
+  3792 => x"53545249",
+  3793 => x"4e470000",
+  3794 => x"00010202",
+  3795 => x"03030303",
+  3796 => x"04040404",
+  3797 => x"04040404",
+  3798 => x"05050505",
+  3799 => x"05050505",
+  3800 => x"05050505",
+  3801 => x"05050505",
+  3802 => x"06060606",
+  3803 => x"06060606",
+  3804 => x"06060606",
+  3805 => x"06060606",
+  3806 => x"06060606",
+  3807 => x"06060606",
+  3808 => x"06060606",
+  3809 => x"06060606",
+  3810 => x"07070707",
+  3811 => x"07070707",
+  3812 => x"07070707",
+  3813 => x"07070707",
+  3814 => x"07070707",
+  3815 => x"07070707",
+  3816 => x"07070707",
+  3817 => x"07070707",
+  3818 => x"07070707",
+  3819 => x"07070707",
+  3820 => x"07070707",
+  3821 => x"07070707",
+  3822 => x"07070707",
+  3823 => x"07070707",
+  3824 => x"07070707",
+  3825 => x"07070707",
+  3826 => x"08080808",
+  3827 => x"08080808",
+  3828 => x"08080808",
+  3829 => x"08080808",
+  3830 => x"08080808",
+  3831 => x"08080808",
+  3832 => x"08080808",
+  3833 => x"08080808",
+  3834 => x"08080808",
+  3835 => x"08080808",
+  3836 => x"08080808",
+  3837 => x"08080808",
+  3838 => x"08080808",
+  3839 => x"08080808",
+  3840 => x"08080808",
+  3841 => x"08080808",
+  3842 => x"08080808",
+  3843 => x"08080808",
+  3844 => x"08080808",
+  3845 => x"08080808",
+  3846 => x"08080808",
+  3847 => x"08080808",
+  3848 => x"08080808",
+  3849 => x"08080808",
+  3850 => x"08080808",
+  3851 => x"08080808",
+  3852 => x"08080808",
+  3853 => x"08080808",
+  3854 => x"08080808",
+  3855 => x"08080808",
+  3856 => x"08080808",
+  3857 => x"08080808",
+  3858 => x"43000000",
+  3859 => x"64756d6d",
+  3860 => x"792e6578",
+  3861 => x"65000000",
+  3862 => x"00ffffff",
+  3863 => x"ff00ffff",
+  3864 => x"ffff00ff",
+  3865 => x"ffffff00",
+  3866 => x"00000000",
+  3867 => x"00000000",
+  3868 => x"00000000",
+  3869 => x"00004458",
+  3870 => x"0000000a",
+  3871 => x"00000000",
+  3872 => x"00000032",
+  3873 => x"00000000",
+  3874 => x"00000000",
+  3875 => x"00000000",
+  3876 => x"00000000",
+  3877 => x"00000000",
+  3878 => x"00000000",
+  3879 => x"00000000",
+  3880 => x"00000000",
+  3881 => x"00000000",
+  3882 => x"00000000",
+  3883 => x"00000000",
+  3884 => x"00000000",
+  3885 => x"ffffffff",
+  3886 => x"00000000",
+  3887 => x"00020000",
+  3888 => x"00000000",
+  3889 => x"00000000",
+  3890 => x"00003cc0",
+  3891 => x"00003cc0",
+  3892 => x"00003cc8",
+  3893 => x"00003cc8",
+  3894 => x"00003cd0",
+  3895 => x"00003cd0",
+  3896 => x"00003cd8",
+  3897 => x"00003cd8",
+  3898 => x"00003ce0",
+  3899 => x"00003ce0",
+  3900 => x"00003ce8",
+  3901 => x"00003ce8",
+  3902 => x"00003cf0",
+  3903 => x"00003cf0",
+  3904 => x"00003cf8",
+  3905 => x"00003cf8",
+  3906 => x"00003d00",
+  3907 => x"00003d00",
+  3908 => x"00003d08",
+  3909 => x"00003d08",
+  3910 => x"00003d10",
+  3911 => x"00003d10",
+  3912 => x"00003d18",
+  3913 => x"00003d18",
+  3914 => x"00003d20",
+  3915 => x"00003d20",
+  3916 => x"00003d28",
+  3917 => x"00003d28",
+  3918 => x"00003d30",
+  3919 => x"00003d30",
+  3920 => x"00003d38",
+  3921 => x"00003d38",
+  3922 => x"00003d40",
+  3923 => x"00003d40",
+  3924 => x"00003d48",
+  3925 => x"00003d48",
+  3926 => x"00003d50",
+  3927 => x"00003d50",
+  3928 => x"00003d58",
+  3929 => x"00003d58",
+  3930 => x"00003d60",
+  3931 => x"00003d60",
+  3932 => x"00003d68",
+  3933 => x"00003d68",
+  3934 => x"00003d70",
+  3935 => x"00003d70",
+  3936 => x"00003d78",
+  3937 => x"00003d78",
+  3938 => x"00003d80",
+  3939 => x"00003d80",
+  3940 => x"00003d88",
+  3941 => x"00003d88",
+  3942 => x"00003d90",
+  3943 => x"00003d90",
+  3944 => x"00003d98",
+  3945 => x"00003d98",
+  3946 => x"00003da0",
+  3947 => x"00003da0",
+  3948 => x"00003da8",
+  3949 => x"00003da8",
+  3950 => x"00003db0",
+  3951 => x"00003db0",
+  3952 => x"00003db8",
+  3953 => x"00003db8",
+  3954 => x"00003dc0",
+  3955 => x"00003dc0",
+  3956 => x"00003dc8",
+  3957 => x"00003dc8",
+  3958 => x"00003dd0",
+  3959 => x"00003dd0",
+  3960 => x"00003dd8",
+  3961 => x"00003dd8",
+  3962 => x"00003de0",
+  3963 => x"00003de0",
+  3964 => x"00003de8",
+  3965 => x"00003de8",
+  3966 => x"00003df0",
+  3967 => x"00003df0",
+  3968 => x"00003df8",
+  3969 => x"00003df8",
+  3970 => x"00003e00",
+  3971 => x"00003e00",
+  3972 => x"00003e08",
+  3973 => x"00003e08",
+  3974 => x"00003e10",
+  3975 => x"00003e10",
+  3976 => x"00003e18",
+  3977 => x"00003e18",
+  3978 => x"00003e20",
+  3979 => x"00003e20",
+  3980 => x"00003e28",
+  3981 => x"00003e28",
+  3982 => x"00003e30",
+  3983 => x"00003e30",
+  3984 => x"00003e38",
+  3985 => x"00003e38",
+  3986 => x"00003e40",
+  3987 => x"00003e40",
+  3988 => x"00003e48",
+  3989 => x"00003e48",
+  3990 => x"00003e50",
+  3991 => x"00003e50",
+  3992 => x"00003e58",
+  3993 => x"00003e58",
+  3994 => x"00003e60",
+  3995 => x"00003e60",
+  3996 => x"00003e68",
+  3997 => x"00003e68",
+  3998 => x"00003e70",
+  3999 => x"00003e70",
+  4000 => x"00003e78",
+  4001 => x"00003e78",
+  4002 => x"00003e80",
+  4003 => x"00003e80",
+  4004 => x"00003e88",
+  4005 => x"00003e88",
+  4006 => x"00003e90",
+  4007 => x"00003e90",
+  4008 => x"00003e98",
+  4009 => x"00003e98",
+  4010 => x"00003ea0",
+  4011 => x"00003ea0",
+  4012 => x"00003ea8",
+  4013 => x"00003ea8",
+  4014 => x"00003eb0",
+  4015 => x"00003eb0",
+  4016 => x"00003eb8",
+  4017 => x"00003eb8",
+  4018 => x"00003ec0",
+  4019 => x"00003ec0",
+  4020 => x"00003ec8",
+  4021 => x"00003ec8",
+  4022 => x"00003ed0",
+  4023 => x"00003ed0",
+  4024 => x"00003ed8",
+  4025 => x"00003ed8",
+  4026 => x"00003ee0",
+  4027 => x"00003ee0",
+  4028 => x"00003ee8",
+  4029 => x"00003ee8",
+  4030 => x"00003ef0",
+  4031 => x"00003ef0",
+  4032 => x"00003ef8",
+  4033 => x"00003ef8",
+  4034 => x"00003f00",
+  4035 => x"00003f00",
+  4036 => x"00003f08",
+  4037 => x"00003f08",
+  4038 => x"00003f10",
+  4039 => x"00003f10",
+  4040 => x"00003f18",
+  4041 => x"00003f18",
+  4042 => x"00003f20",
+  4043 => x"00003f20",
+  4044 => x"00003f28",
+  4045 => x"00003f28",
+  4046 => x"00003f30",
+  4047 => x"00003f30",
+  4048 => x"00003f38",
+  4049 => x"00003f38",
+  4050 => x"00003f40",
+  4051 => x"00003f40",
+  4052 => x"00003f48",
+  4053 => x"00003f48",
+  4054 => x"00003f50",
+  4055 => x"00003f50",
+  4056 => x"00003f58",
+  4057 => x"00003f58",
+  4058 => x"00003f60",
+  4059 => x"00003f60",
+  4060 => x"00003f68",
+  4061 => x"00003f68",
+  4062 => x"00003f70",
+  4063 => x"00003f70",
+  4064 => x"00003f78",
+  4065 => x"00003f78",
+  4066 => x"00003f80",
+  4067 => x"00003f80",
+  4068 => x"00003f88",
+  4069 => x"00003f88",
+  4070 => x"00003f90",
+  4071 => x"00003f90",
+  4072 => x"00003f98",
+  4073 => x"00003f98",
+  4074 => x"00003fa0",
+  4075 => x"00003fa0",
+  4076 => x"00003fa8",
+  4077 => x"00003fa8",
+  4078 => x"00003fb0",
+  4079 => x"00003fb0",
+  4080 => x"00003fb8",
+  4081 => x"00003fb8",
+  4082 => x"00003fc0",
+  4083 => x"00003fc0",
+  4084 => x"00003fc8",
+  4085 => x"00003fc8",
+  4086 => x"00003fd0",
+  4087 => x"00003fd0",
+  4088 => x"00003fd8",
+  4089 => x"00003fd8",
+  4090 => x"00003fe0",
+  4091 => x"00003fe0",
+  4092 => x"00003fe8",
+  4093 => x"00003fe8",
+  4094 => x"00003ff0",
+  4095 => x"00003ff0",
+  4096 => x"00003ff8",
+  4097 => x"00003ff8",
+  4098 => x"00004000",
+  4099 => x"00004000",
+  4100 => x"00004008",
+  4101 => x"00004008",
+  4102 => x"00004010",
+  4103 => x"00004010",
+  4104 => x"00004018",
+  4105 => x"00004018",
+  4106 => x"00004020",
+  4107 => x"00004020",
+  4108 => x"00004028",
+  4109 => x"00004028",
+  4110 => x"00004030",
+  4111 => x"00004030",
+  4112 => x"00004038",
+  4113 => x"00004038",
+  4114 => x"00004040",
+  4115 => x"00004040",
+  4116 => x"00004048",
+  4117 => x"00004048",
+  4118 => x"00004050",
+  4119 => x"00004050",
+  4120 => x"00004058",
+  4121 => x"00004058",
+  4122 => x"00004060",
+  4123 => x"00004060",
+  4124 => x"00004068",
+  4125 => x"00004068",
+  4126 => x"00004070",
+  4127 => x"00004070",
+  4128 => x"00004078",
+  4129 => x"00004078",
+  4130 => x"00004080",
+  4131 => x"00004080",
+  4132 => x"00004088",
+  4133 => x"00004088",
+  4134 => x"00004090",
+  4135 => x"00004090",
+  4136 => x"00004098",
+  4137 => x"00004098",
+  4138 => x"000040a0",
+  4139 => x"000040a0",
+  4140 => x"000040a8",
+  4141 => x"000040a8",
+  4142 => x"000040b0",
+  4143 => x"000040b0",
+  4144 => x"000040b8",
+  4145 => x"000040b8",
+  4146 => x"000040cc",
+  4147 => x"00000000",
+  4148 => x"00004334",
+  4149 => x"00004390",
+  4150 => x"000043ec",
+  4151 => x"00000000",
+  4152 => x"00000000",
+  4153 => x"00000000",
+  4154 => x"00000000",
+  4155 => x"00000000",
+  4156 => x"00000000",
+  4157 => x"00000000",
+  4158 => x"00000000",
+  4159 => x"00000000",
+  4160 => x"00003c48",
+  4161 => x"00000000",
+  4162 => x"00000000",
+  4163 => x"00000000",
+  4164 => x"00000000",
+  4165 => x"00000000",
+  4166 => x"00000000",
+  4167 => x"00000000",
+  4168 => x"00000000",
+  4169 => x"00000000",
+  4170 => x"00000000",
+  4171 => x"00000000",
+  4172 => x"00000000",
+  4173 => x"00000000",
+  4174 => x"00000000",
+  4175 => x"00000000",
+  4176 => x"00000000",
+  4177 => x"00000000",
+  4178 => x"00000000",
+  4179 => x"00000000",
+  4180 => x"00000000",
+  4181 => x"00000000",
+  4182 => x"00000000",
+  4183 => x"00000000",
+  4184 => x"00000000",
+  4185 => x"00000000",
+  4186 => x"00000000",
+  4187 => x"00000000",
+  4188 => x"00000000",
+  4189 => x"00000001",
+  4190 => x"330eabcd",
+  4191 => x"1234e66d",
+  4192 => x"deec0005",
+  4193 => x"000b0000",
+  4194 => x"00000000",
+  4195 => x"00000000",
+  4196 => x"00000000",
+  4197 => x"00000000",
+  4198 => x"00000000",
+  4199 => x"00000000",
+  4200 => x"00000000",
+  4201 => x"00000000",
+  4202 => x"00000000",
+  4203 => x"00000000",
+  4204 => x"00000000",
+  4205 => x"00000000",
+  4206 => x"00000000",
+  4207 => x"00000000",
+  4208 => x"00000000",
+  4209 => x"00000000",
+  4210 => x"00000000",
+  4211 => x"00000000",
+  4212 => x"00000000",
+  4213 => x"00000000",
+  4214 => x"00000000",
+  4215 => x"00000000",
+  4216 => x"00000000",
+  4217 => x"00000000",
+  4218 => x"00000000",
+  4219 => x"00000000",
+  4220 => x"00000000",
+  4221 => x"00000000",
+  4222 => x"00000000",
+  4223 => x"00000000",
+  4224 => x"00000000",
+  4225 => x"00000000",
+  4226 => x"00000000",
+  4227 => x"00000000",
+  4228 => x"00000000",
+  4229 => x"00000000",
+  4230 => x"00000000",
+  4231 => x"00000000",
+  4232 => x"00000000",
+  4233 => x"00000000",
+  4234 => x"00000000",
+  4235 => x"00000000",
+  4236 => x"00000000",
+  4237 => x"00000000",
+  4238 => x"00000000",
+  4239 => x"00000000",
+  4240 => x"00000000",
+  4241 => x"00000000",
+  4242 => x"00000000",
+  4243 => x"00000000",
+  4244 => x"00000000",
+  4245 => x"00000000",
+  4246 => x"00000000",
+  4247 => x"00000000",
+  4248 => x"00000000",
+  4249 => x"00000000",
+  4250 => x"00000000",
+  4251 => x"00000000",
+  4252 => x"00000000",
+  4253 => x"00000000",
+  4254 => x"00000000",
+  4255 => x"00000000",
+  4256 => x"00000000",
+  4257 => x"00000000",
+  4258 => x"00000000",
+  4259 => x"00000000",
+  4260 => x"00000000",
+  4261 => x"00000000",
+  4262 => x"00000000",
+  4263 => x"00000000",
+  4264 => x"00000000",
+  4265 => x"00000000",
+  4266 => x"00000000",
+  4267 => x"00000000",
+  4268 => x"00000000",
+  4269 => x"00000000",
+  4270 => x"00000000",
+  4271 => x"00000000",
+  4272 => x"00000000",
+  4273 => x"00000000",
+  4274 => x"00000000",
+  4275 => x"00000000",
+  4276 => x"00000000",
+  4277 => x"00000000",
+  4278 => x"00000000",
+  4279 => x"00000000",
+  4280 => x"00000000",
+  4281 => x"00000000",
+  4282 => x"00000000",
+  4283 => x"00000000",
+  4284 => x"00000000",
+  4285 => x"00000000",
+  4286 => x"00000000",
+  4287 => x"00000000",
+  4288 => x"00000000",
+  4289 => x"00000000",
+  4290 => x"00000000",
+  4291 => x"00000000",
+  4292 => x"00000000",
+  4293 => x"00000000",
+  4294 => x"00000000",
+  4295 => x"00000000",
+  4296 => x"00000000",
+  4297 => x"00000000",
+  4298 => x"00000000",
+  4299 => x"00000000",
+  4300 => x"00000000",
+  4301 => x"00000000",
+  4302 => x"00000000",
+  4303 => x"00000000",
+  4304 => x"00000000",
+  4305 => x"00000000",
+  4306 => x"00000000",
+  4307 => x"00000000",
+  4308 => x"00000000",
+  4309 => x"00000000",
+  4310 => x"00000000",
+  4311 => x"00000000",
+  4312 => x"00000000",
+  4313 => x"00000000",
+  4314 => x"00000000",
+  4315 => x"00000000",
+  4316 => x"00000000",
+  4317 => x"00000000",
+  4318 => x"00000000",
+  4319 => x"00000000",
+  4320 => x"00000000",
+  4321 => x"00000000",
+  4322 => x"00000000",
+  4323 => x"00000000",
+  4324 => x"00000000",
+  4325 => x"00000000",
+  4326 => x"00000000",
+  4327 => x"00000000",
+  4328 => x"00000000",
+  4329 => x"00000000",
+  4330 => x"00000000",
+  4331 => x"00000000",
+  4332 => x"00000000",
+  4333 => x"00000000",
+  4334 => x"00000000",
+  4335 => x"00000000",
+  4336 => x"00000000",
+  4337 => x"00000000",
+  4338 => x"00000000",
+  4339 => x"00000000",
+  4340 => x"00000000",
+  4341 => x"00000000",
+  4342 => x"00000000",
+  4343 => x"00000000",
+  4344 => x"00000000",
+  4345 => x"00000000",
+  4346 => x"00000000",
+  4347 => x"00000000",
+  4348 => x"00000000",
+  4349 => x"00000000",
+  4350 => x"00000000",
+  4351 => x"00000000",
+  4352 => x"00000000",
+  4353 => x"00000000",
+  4354 => x"00000000",
+  4355 => x"00000000",
+  4356 => x"00000000",
+  4357 => x"00000000",
+  4358 => x"00000000",
+  4359 => x"00000000",
+  4360 => x"00000000",
+  4361 => x"00000000",
+  4362 => x"00000000",
+  4363 => x"00000000",
+  4364 => x"00000000",
+  4365 => x"00000000",
+  4366 => x"00000000",
+  4367 => x"00000000",
+  4368 => x"00000000",
+  4369 => x"00000000",
+  4370 => x"00003c4c",
+  4371 => x"ffffffff",
+  4372 => x"00000000",
+  4373 => x"ffffffff",
+  4374 => x"00000000",
+  4375 => x"00000000",
+
+others => x"00000000"
+);
+begin
+   busy_o <= re_i; -- we're done on the cycle after we serve the read request
+
+   do_ram:
+   process (clk_i)
+      variable iaddr : integer;
+   begin
+      if rising_edge(clk_i) then
+         if we_i='1' then
+            ram(to_integer(addr_i)) <= write_i;
+         end if;
+         addr_r <= addr_i;
+      end if;
+   end process do_ram;
+   read_o <= ram(to_integer(addr_r));
+end architecture Xilinx; -- Entity: SinglePortRAM
+
diff --git a/zpu/hdl/zealot/roms/dmips_dbram.vhdl b/zpu/hdl/zealot/roms/dmips_dbram.vhdl
new file mode 100644
index 0000000..32b6947
--- /dev/null
+++ b/zpu/hdl/zealot/roms/dmips_dbram.vhdl
@@ -0,0 +1,4485 @@
+------------------------------------------------------------------------------
+----                                                                      ----
+----  Dual Port RAM that maps to a Xilinx BRAM                            ----
+----                                                                      ----
+----  http://www.opencores.org/                                           ----
+----                                                                      ----
+----  Description:                                                        ----
+----  This is a program+data memory for the ZPU. It maps to a Xilinx BRAM ----
+----                                                                      ----
+----  To Do:                                                              ----
+----  -                                                                   ----
+----                                                                      ----
+----  Author:                                                             ----
+----    - Øyvind Harboe, oyvind.harboe zylin.com                          ----
+----    - Salvador E. Tropea, salvador inti.gob.ar                        ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com>           ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar>         ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial       ----
+----                                                                      ----
+---- Distributed under the BSD license                                    ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Design unit:      DualPortRAM(Xilinx) (Entity and architecture)      ----
+---- File name:        rom.in.vhdl (template used)                        ----
+---- Note:             None                                               ----
+---- Limitations:      None known                                         ----
+---- Errors:           None known                                         ----
+---- Library:          work                                               ----
+---- Dependencies:     IEEE.std_logic_1164                                ----
+----                   IEEE.numeric_std                                   ----
+---- Target FPGA:      Spartan 3 (XC3S1500-4-FG456)                       ----
+---- Language:         VHDL                                               ----
+---- Wishbone:         No                                                 ----
+---- Synthesis tools:  Xilinx Release 9.2.03i - xst J.39                  ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x)                       ----
+---- Text editor:      SETEdit 0.5.x                                      ----
+----                                                                      ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity DualPortRAM is
+   generic(
+      WORD_SIZE    : integer:=32;  -- Word Size 16/32
+      BYTE_BITS    : integer:=2;   -- Bits used to address bytes
+      BRAM_W       : integer:=15); -- Address Width
+   port(
+      clk_i     : in  std_logic;
+      -- Port A
+      a_we_i    : in  std_logic;
+      a_addr_i  : in  unsigned(BRAM_W-1 downto BYTE_BITS);
+      a_write_i : in  unsigned(WORD_SIZE-1 downto 0);
+      a_read_o  : out unsigned(WORD_SIZE-1 downto 0);
+      -- Port B
+      b_we_i    : in  std_logic;
+      b_addr_i  : in  unsigned(BRAM_W-1 downto BYTE_BITS);
+      b_write_i : in  unsigned(WORD_SIZE-1 downto 0);
+      b_read_o  : out unsigned(WORD_SIZE-1 downto 0));
+end entity DualPortRAM;
+
+architecture Xilinx of DualPortRAM is
+   type ram_type is array(natural range 0 to ((2**BRAM_W)/4)-1) of unsigned(WORD_SIZE-1 downto 0);
+
+   shared variable ram : ram_type:=
+(
+     0 => x"0b0b0b0b",
+     1 => x"82700b0b",
+     2 => x"80f8ec0c",
+     3 => x"3a0b0b80",
+     4 => x"e7ea0400",
+     5 => x"00000000",
+     6 => x"00000000",
+     7 => x"00000000",
+     8 => x"80088408",
+     9 => x"88080b0b",
+    10 => x"80e8b72d",
+    11 => x"880c840c",
+    12 => x"800c0400",
+    13 => x"00000000",
+    14 => x"00000000",
+    15 => x"00000000",
+    16 => x"71fd0608",
+    17 => x"72830609",
+    18 => x"81058205",
+    19 => x"832b2a83",
+    20 => x"ffff0652",
+    21 => x"04000000",
+    22 => x"00000000",
+    23 => x"00000000",
+    24 => x"71fd0608",
+    25 => x"83ffff73",
+    26 => x"83060981",
+    27 => x"05820583",
+    28 => x"2b2b0906",
+    29 => x"7383ffff",
+    30 => x"0b0b0b0b",
+    31 => x"83a70400",
+    32 => x"72098105",
+    33 => x"72057373",
+    34 => x"09060906",
+    35 => x"73097306",
+    36 => x"070a8106",
+    37 => x"53510400",
+    38 => x"00000000",
+    39 => x"00000000",
+    40 => x"72722473",
+    41 => x"732e0753",
+    42 => x"51040000",
+    43 => x"00000000",
+    44 => x"00000000",
+    45 => x"00000000",
+    46 => x"00000000",
+    47 => x"00000000",
+    48 => x"71737109",
+    49 => x"71068106",
+    50 => x"30720a10",
+    51 => x"0a720a10",
+    52 => x"0a31050a",
+    53 => x"81065151",
+    54 => x"53510400",
+    55 => x"00000000",
+    56 => x"72722673",
+    57 => x"732e0753",
+    58 => x"51040000",
+    59 => x"00000000",
+    60 => x"00000000",
+    61 => x"00000000",
+    62 => x"00000000",
+    63 => x"00000000",
+    64 => x"00000000",
+    65 => x"00000000",
+    66 => x"00000000",
+    67 => x"00000000",
+    68 => x"00000000",
+    69 => x"00000000",
+    70 => x"00000000",
+    71 => x"00000000",
+    72 => x"0b0b0b88",
+    73 => x"c4040000",
+    74 => x"00000000",
+    75 => x"00000000",
+    76 => x"00000000",
+    77 => x"00000000",
+    78 => x"00000000",
+    79 => x"00000000",
+    80 => x"720a722b",
+    81 => x"0a535104",
+    82 => x"00000000",
+    83 => x"00000000",
+    84 => x"00000000",
+    85 => x"00000000",
+    86 => x"00000000",
+    87 => x"00000000",
+    88 => x"72729f06",
+    89 => x"0981050b",
+    90 => x"0b0b88a7",
+    91 => x"05040000",
+    92 => x"00000000",
+    93 => x"00000000",
+    94 => x"00000000",
+    95 => x"00000000",
+    96 => x"72722aff",
+    97 => x"739f062a",
+    98 => x"0974090a",
+    99 => x"8106ff05",
+   100 => x"06075351",
+   101 => x"04000000",
+   102 => x"00000000",
+   103 => x"00000000",
+   104 => x"71715351",
+   105 => x"020d0406",
+   106 => x"73830609",
+   107 => x"81058205",
+   108 => x"832b0b2b",
+   109 => x"0772fc06",
+   110 => x"0c515104",
+   111 => x"00000000",
+   112 => x"72098105",
+   113 => x"72050970",
+   114 => x"81050906",
+   115 => x"0a810653",
+   116 => x"51040000",
+   117 => x"00000000",
+   118 => x"00000000",
+   119 => x"00000000",
+   120 => x"72098105",
+   121 => x"72050970",
+   122 => x"81050906",
+   123 => x"0a098106",
+   124 => x"53510400",
+   125 => x"00000000",
+   126 => x"00000000",
+   127 => x"00000000",
+   128 => x"71098105",
+   129 => x"52040000",
+   130 => x"00000000",
+   131 => x"00000000",
+   132 => x"00000000",
+   133 => x"00000000",
+   134 => x"00000000",
+   135 => x"00000000",
+   136 => x"72720981",
+   137 => x"05055351",
+   138 => x"04000000",
+   139 => x"00000000",
+   140 => x"00000000",
+   141 => x"00000000",
+   142 => x"00000000",
+   143 => x"00000000",
+   144 => x"72097206",
+   145 => x"73730906",
+   146 => x"07535104",
+   147 => x"00000000",
+   148 => x"00000000",
+   149 => x"00000000",
+   150 => x"00000000",
+   151 => x"00000000",
+   152 => x"71fc0608",
+   153 => x"72830609",
+   154 => x"81058305",
+   155 => x"1010102a",
+   156 => x"81ff0652",
+   157 => x"04000000",
+   158 => x"00000000",
+   159 => x"00000000",
+   160 => x"71fc0608",
+   161 => x"0b0b80f8",
+   162 => x"d8738306",
+   163 => x"10100508",
+   164 => x"060b0b0b",
+   165 => x"88aa0400",
+   166 => x"00000000",
+   167 => x"00000000",
+   168 => x"80088408",
+   169 => x"88087575",
+   170 => x"0b0b80ce",
+   171 => x"b62d5050",
+   172 => x"80085688",
+   173 => x"0c840c80",
+   174 => x"0c510400",
+   175 => x"00000000",
+   176 => x"80088408",
+   177 => x"88087575",
+   178 => x"0b0b80cf",
+   179 => x"e82d5050",
+   180 => x"80085688",
+   181 => x"0c840c80",
+   182 => x"0c510400",
+   183 => x"00000000",
+   184 => x"72097081",
+   185 => x"0509060a",
+   186 => x"8106ff05",
+   187 => x"70547106",
+   188 => x"73097274",
+   189 => x"05ff0506",
+   190 => x"07515151",
+   191 => x"04000000",
+   192 => x"72097081",
+   193 => x"0509060a",
+   194 => x"098106ff",
+   195 => x"05705471",
+   196 => x"06730972",
+   197 => x"7405ff05",
+   198 => x"06075151",
+   199 => x"51040000",
+   200 => x"05ff0504",
+   201 => x"00000000",
+   202 => x"00000000",
+   203 => x"00000000",
+   204 => x"00000000",
+   205 => x"00000000",
+   206 => x"00000000",
+   207 => x"00000000",
+   208 => x"810b0b0b",
+   209 => x"80f8e80c",
+   210 => x"51040000",
+   211 => x"00000000",
+   212 => x"00000000",
+   213 => x"00000000",
+   214 => x"00000000",
+   215 => x"00000000",
+   216 => x"71810552",
+   217 => x"04000000",
+   218 => x"00000000",
+   219 => x"00000000",
+   220 => x"00000000",
+   221 => x"00000000",
+   222 => x"00000000",
+   223 => x"00000000",
+   224 => x"00000000",
+   225 => x"00000000",
+   226 => x"00000000",
+   227 => x"00000000",
+   228 => x"00000000",
+   229 => x"00000000",
+   230 => x"00000000",
+   231 => x"00000000",
+   232 => x"02840572",
+   233 => x"10100552",
+   234 => x"04000000",
+   235 => x"00000000",
+   236 => x"00000000",
+   237 => x"00000000",
+   238 => x"00000000",
+   239 => x"00000000",
+   240 => x"00000000",
+   241 => x"00000000",
+   242 => x"00000000",
+   243 => x"00000000",
+   244 => x"00000000",
+   245 => x"00000000",
+   246 => x"00000000",
+   247 => x"00000000",
+   248 => x"717105ff",
+   249 => x"05715351",
+   250 => x"020d0400",
+   251 => x"00000000",
+   252 => x"00000000",
+   253 => x"00000000",
+   254 => x"00000000",
+   255 => x"00000000",
+   256 => x"83803f80",
+   257 => x"e2953f04",
+   258 => x"10101010",
+   259 => x"10101010",
+   260 => x"10101010",
+   261 => x"10101010",
+   262 => x"10101010",
+   263 => x"10101010",
+   264 => x"10101010",
+   265 => x"10101053",
+   266 => x"51047381",
+   267 => x"ff067383",
+   268 => x"06098105",
+   269 => x"83051010",
+   270 => x"102b0772",
+   271 => x"fc060c51",
+   272 => x"51043c04",
+   273 => x"72728072",
+   274 => x"8106ff05",
+   275 => x"09720605",
+   276 => x"71105272",
+   277 => x"0a100a53",
+   278 => x"72ed3851",
+   279 => x"51535104",
+   280 => x"ff3d0d0b",
+   281 => x"0b8188e0",
+   282 => x"08527108",
+   283 => x"70882a81",
+   284 => x"32708106",
+   285 => x"51515170",
+   286 => x"f1387372",
+   287 => x"0c833d0d",
+   288 => x"0480f8e8",
+   289 => x"08802ea4",
+   290 => x"3880f8ec",
+   291 => x"08822ebd",
+   292 => x"38838080",
+   293 => x"0b0b0b81",
+   294 => x"88e00c82",
+   295 => x"a0800b81",
+   296 => x"88e40c82",
+   297 => x"90800b81",
+   298 => x"88e80c04",
+   299 => x"f8808080",
+   300 => x"a40b0b0b",
+   301 => x"8188e00c",
+   302 => x"f8808082",
+   303 => x"800b8188",
+   304 => x"e40cf880",
+   305 => x"8084800b",
+   306 => x"8188e80c",
+   307 => x"0480c0a8",
+   308 => x"808c0b0b",
+   309 => x"0b8188e0",
+   310 => x"0c80c0a8",
+   311 => x"80940b81",
+   312 => x"88e40c0b",
+   313 => x"0b80eac8",
+   314 => x"0b8188e8",
+   315 => x"0c04f23d",
+   316 => x"0d608188",
+   317 => x"e408565d",
+   318 => x"82750c80",
+   319 => x"59805a80",
+   320 => x"0b8f3d5d",
+   321 => x"5b7a1010",
+   322 => x"15700871",
+   323 => x"08719f2c",
+   324 => x"7e852b58",
+   325 => x"55557d53",
+   326 => x"59579d94",
+   327 => x"3f7d7f7a",
+   328 => x"72077c72",
+   329 => x"07717160",
+   330 => x"8105415f",
+   331 => x"5d5b5957",
+   332 => x"55817b27",
+   333 => x"8f38767d",
+   334 => x"0c77841e",
+   335 => x"0c7c800c",
+   336 => x"903d0d04",
+   337 => x"8188e408",
+   338 => x"55ffba39",
+   339 => x"ff3d0d81",
+   340 => x"88ec3351",
+   341 => x"70a73880",
+   342 => x"f8f40870",
+   343 => x"08525270",
+   344 => x"802e9438",
+   345 => x"841280f8",
+   346 => x"f40c702d",
+   347 => x"80f8f408",
+   348 => x"70085252",
+   349 => x"70ee3881",
+   350 => x"0b8188ec",
+   351 => x"34833d0d",
+   352 => x"0404803d",
+   353 => x"0d0b0b81",
+   354 => x"88dc0880",
+   355 => x"2e8e380b",
+   356 => x"0b0b0b80",
+   357 => x"0b802e09",
+   358 => x"81068538",
+   359 => x"823d0d04",
+   360 => x"0b0b8188",
+   361 => x"dc510b0b",
+   362 => x"0bf4d53f",
+   363 => x"823d0d04",
+   364 => x"04ff3d0d",
+   365 => x"028f0533",
+   366 => x"52718a2e",
+   367 => x"8a387151",
+   368 => x"fd9e3f83",
+   369 => x"3d0d048d",
+   370 => x"51fd953f",
+   371 => x"7151fd90",
+   372 => x"3f833d0d",
+   373 => x"04ce3d0d",
+   374 => x"b53d7070",
+   375 => x"84055208",
+   376 => x"8bb15c56",
+   377 => x"a53d5e5c",
+   378 => x"80757081",
+   379 => x"05573376",
+   380 => x"5b555873",
+   381 => x"782e80c1",
+   382 => x"388e3d5b",
+   383 => x"73a52e09",
+   384 => x"810680c5",
+   385 => x"38787081",
+   386 => x"055a3354",
+   387 => x"7380e42e",
+   388 => x"81b63873",
+   389 => x"80e42480",
+   390 => x"c6387380",
+   391 => x"e32ea138",
+   392 => x"8052a551",
+   393 => x"792d8052",
+   394 => x"7351792d",
+   395 => x"82185878",
+   396 => x"7081055a",
+   397 => x"335473c4",
+   398 => x"3877800c",
+   399 => x"b43d0d04",
+   400 => x"7b841d83",
+   401 => x"1233565d",
+   402 => x"57805273",
+   403 => x"51792d81",
+   404 => x"18797081",
+   405 => x"055b3355",
+   406 => x"5873ffa0",
+   407 => x"38db3973",
+   408 => x"80f32e09",
+   409 => x"8106ffb8",
+   410 => x"387b841d",
+   411 => x"7108595d",
+   412 => x"56807733",
+   413 => x"55567376",
+   414 => x"2e8d3881",
+   415 => x"16701870",
+   416 => x"33575556",
+   417 => x"74f538ff",
+   418 => x"16558076",
+   419 => x"25ffa038",
+   420 => x"76708105",
+   421 => x"58335480",
+   422 => x"52735179",
+   423 => x"2d811875",
+   424 => x"ff175757",
+   425 => x"58807625",
+   426 => x"ff853876",
+   427 => x"70810558",
+   428 => x"33548052",
+   429 => x"7351792d",
+   430 => x"811875ff",
+   431 => x"17575758",
+   432 => x"758024cc",
+   433 => x"38fee839",
+   434 => x"7b841d71",
+   435 => x"0870719f",
+   436 => x"2c595359",
+   437 => x"5d568075",
+   438 => x"24819338",
+   439 => x"757d7c58",
+   440 => x"56548057",
+   441 => x"73772e09",
+   442 => x"8106b638",
+   443 => x"b07b3402",
+   444 => x"b505567a",
+   445 => x"762e9738",
+   446 => x"ff165675",
+   447 => x"33757081",
+   448 => x"05573481",
+   449 => x"17577a76",
+   450 => x"2e098106",
+   451 => x"eb388075",
+   452 => x"34767dff",
+   453 => x"12575856",
+   454 => x"758024fe",
+   455 => x"f338fe8f",
+   456 => x"398a5273",
+   457 => x"5180c1c0",
+   458 => x"3f800880",
+   459 => x"eacc0533",
+   460 => x"76708105",
+   461 => x"58348a52",
+   462 => x"7351bffa",
+   463 => x"3f800854",
+   464 => x"8008802e",
+   465 => x"ffad388a",
+   466 => x"52735180",
+   467 => x"c19a3f80",
+   468 => x"0880eacc",
+   469 => x"05337670",
+   470 => x"81055834",
+   471 => x"8a527351",
+   472 => x"bfd43f80",
+   473 => x"08548008",
+   474 => x"ffb738ff",
+   475 => x"86397452",
+   476 => x"7653b43d",
+   477 => x"ffb80551",
+   478 => x"978a3fa3",
+   479 => x"3d0856fe",
+   480 => x"db39803d",
+   481 => x"0d80c10b",
+   482 => x"81d7b834",
+   483 => x"800b81d9",
+   484 => x"940c7080",
+   485 => x"0c823d0d",
+   486 => x"04ff3d0d",
+   487 => x"800b81d7",
+   488 => x"b8335252",
+   489 => x"7080c12e",
+   490 => x"99387181",
+   491 => x"d9940807",
+   492 => x"81d9940c",
+   493 => x"80c20b81",
+   494 => x"d7bc3470",
+   495 => x"800c833d",
+   496 => x"0d04810b",
+   497 => x"81d99408",
+   498 => x"0781d994",
+   499 => x"0c80c20b",
+   500 => x"81d7bc34",
+   501 => x"70800c83",
+   502 => x"3d0d04fd",
+   503 => x"3d0d7570",
+   504 => x"088a0553",
+   505 => x"5381d7b8",
+   506 => x"33517080",
+   507 => x"c12e8b38",
+   508 => x"73f33870",
+   509 => x"800c853d",
+   510 => x"0d04ff12",
+   511 => x"7081d7b4",
+   512 => x"0831740c",
+   513 => x"800c853d",
+   514 => x"0d04fc3d",
+   515 => x"0d81d7c0",
+   516 => x"08557480",
+   517 => x"2e8c3876",
+   518 => x"7508710c",
+   519 => x"81d7c008",
+   520 => x"56548c15",
+   521 => x"5381d7b4",
+   522 => x"08528a51",
+   523 => x"8fe73f73",
+   524 => x"800c863d",
+   525 => x"0d04fb3d",
+   526 => x"0d777008",
+   527 => x"5656b053",
+   528 => x"81d7c008",
+   529 => x"52745180",
+   530 => x"cdff3f85",
+   531 => x"0b8c170c",
+   532 => x"850b8c16",
+   533 => x"0c750875",
+   534 => x"0c81d7c0",
+   535 => x"08547380",
+   536 => x"2e8a3873",
+   537 => x"08750c81",
+   538 => x"d7c00854",
+   539 => x"8c145381",
+   540 => x"d7b40852",
+   541 => x"8a518f9d",
+   542 => x"3f841508",
+   543 => x"ad38860b",
+   544 => x"8c160c88",
+   545 => x"15528816",
+   546 => x"08518ea9",
+   547 => x"3f81d7c0",
+   548 => x"08700876",
+   549 => x"0c548c15",
+   550 => x"7054548a",
+   551 => x"52730851",
+   552 => x"8ef33f73",
+   553 => x"800c873d",
+   554 => x"0d047508",
+   555 => x"54b05373",
+   556 => x"52755180",
+   557 => x"cd933f73",
+   558 => x"800c873d",
+   559 => x"0d04d93d",
+   560 => x"0d80f980",
+   561 => x"0b8188e8",
+   562 => x"0cb05180",
+   563 => x"c0e43f80",
+   564 => x"0881d7b0",
+   565 => x"0cb05180",
+   566 => x"c0d83f80",
+   567 => x"0881d7c0",
+   568 => x"0c81d7b0",
+   569 => x"0880080c",
+   570 => x"800b8008",
+   571 => x"84050c82",
+   572 => x"0b800888",
+   573 => x"050ca80b",
+   574 => x"80088c05",
+   575 => x"0c9f5380",
+   576 => x"ead85280",
+   577 => x"08900551",
+   578 => x"80ccbe3f",
+   579 => x"a13d5e9f",
+   580 => x"5380eaf8",
+   581 => x"527d5180",
+   582 => x"ccaf3f8a",
+   583 => x"0b8195f4",
+   584 => x"0c80f59c",
+   585 => x"51f9ae3f",
+   586 => x"80eb9851",
+   587 => x"f9a73f80",
+   588 => x"f59c51f9",
+   589 => x"a03f80f8",
+   590 => x"fc08802e",
+   591 => x"89d73880",
+   592 => x"ebc851f9",
+   593 => x"903f80f5",
+   594 => x"9c51f989",
+   595 => x"3f80f8f8",
+   596 => x"085280eb",
+   597 => x"f451f8fd",
+   598 => x"3f818990",
+   599 => x"5180d5da",
+   600 => x"3f810b9a",
+   601 => x"3d5e5b80",
+   602 => x"0b80f8f8",
+   603 => x"082582d6",
+   604 => x"38903d5f",
+   605 => x"80c10b81",
+   606 => x"d7b83481",
+   607 => x"0b81d994",
+   608 => x"0c80c20b",
+   609 => x"81d7bc34",
+   610 => x"8240835a",
+   611 => x"9f5380ec",
+   612 => x"a4527c51",
+   613 => x"80cbb23f",
+   614 => x"8141807d",
+   615 => x"537e5256",
+   616 => x"8e973f80",
+   617 => x"08762e09",
+   618 => x"81068338",
+   619 => x"81567581",
+   620 => x"d9940c7f",
+   621 => x"70585675",
+   622 => x"8325a238",
+   623 => x"75101016",
+   624 => x"fd0542a9",
+   625 => x"3dffa405",
+   626 => x"53835276",
+   627 => x"518cc63f",
+   628 => x"7f810570",
+   629 => x"41705856",
+   630 => x"837624e0",
+   631 => x"38615475",
+   632 => x"53818998",
+   633 => x"5281d7cc",
+   634 => x"518cba3f",
+   635 => x"81d7c008",
+   636 => x"70085858",
+   637 => x"b0537752",
+   638 => x"765180ca",
+   639 => x"cc3f850b",
+   640 => x"8c190c85",
+   641 => x"0b8c180c",
+   642 => x"7708770c",
+   643 => x"81d7c008",
+   644 => x"5675802e",
+   645 => x"8a387508",
+   646 => x"770c81d7",
+   647 => x"c008568c",
+   648 => x"165381d7",
+   649 => x"b408528a",
+   650 => x"518bea3f",
+   651 => x"84170887",
+   652 => x"eb38860b",
+   653 => x"8c180c88",
+   654 => x"17528818",
+   655 => x"08518af5",
+   656 => x"3f81d7c0",
+   657 => x"08700878",
+   658 => x"0c568c17",
+   659 => x"7054598a",
+   660 => x"52780851",
+   661 => x"8bbf3f80",
+   662 => x"c10b81d7",
+   663 => x"bc335757",
+   664 => x"767626a2",
+   665 => x"3880c352",
+   666 => x"76518ca3",
+   667 => x"3f800861",
+   668 => x"2e89e638",
+   669 => x"81177081",
+   670 => x"ff0681d7",
+   671 => x"bc335858",
+   672 => x"58757727",
+   673 => x"e0387960",
+   674 => x"29627054",
+   675 => x"71535b59",
+   676 => x"b9a43f80",
+   677 => x"0840787a",
+   678 => x"31708729",
+   679 => x"80083180",
+   680 => x"088a0581",
+   681 => x"d7b83381",
+   682 => x"d7b4085e",
+   683 => x"5b525a56",
+   684 => x"7780c12e",
+   685 => x"89d0387b",
+   686 => x"f738811b",
+   687 => x"5b80f8f8",
+   688 => x"087b25fd",
+   689 => x"af3881d7",
+   690 => x"a85180d2",
+   691 => x"ed3f80ec",
+   692 => x"c451f681",
+   693 => x"3f80f59c",
+   694 => x"51f5fa3f",
+   695 => x"80ecd451",
+   696 => x"f5f33f80",
+   697 => x"f59c51f5",
+   698 => x"ec3f81d7",
+   699 => x"b4085280",
+   700 => x"ed8c51f5",
+   701 => x"e03f8552",
+   702 => x"80eda851",
+   703 => x"f5d73f81",
+   704 => x"d9940852",
+   705 => x"80edc451",
+   706 => x"f5cb3f81",
+   707 => x"5280eda8",
+   708 => x"51f5c23f",
+   709 => x"81d7b833",
+   710 => x"5280ede0",
+   711 => x"51f5b63f",
+   712 => x"80c15280",
+   713 => x"edfc51f5",
+   714 => x"ac3f81d7",
+   715 => x"bc335280",
+   716 => x"ee9851f5",
+   717 => x"a03f80c2",
+   718 => x"5280edfc",
+   719 => x"51f5963f",
+   720 => x"81d7ec08",
+   721 => x"5280eeb4",
+   722 => x"51f58a3f",
+   723 => x"875280ed",
+   724 => x"a851f581",
+   725 => x"3f8195f4",
+   726 => x"085280ee",
+   727 => x"d051f4f5",
+   728 => x"3f80eeec",
+   729 => x"51f4ee3f",
+   730 => x"80ef9851",
+   731 => x"f4e73f81",
+   732 => x"d7c00870",
+   733 => x"08535a80",
+   734 => x"efa451f4",
+   735 => x"d83f80ef",
+   736 => x"c051f4d1",
+   737 => x"3f81d7c0",
+   738 => x"08841108",
+   739 => x"535680ef",
+   740 => x"f451f4c1",
+   741 => x"3f805280",
+   742 => x"eda851f4",
+   743 => x"b83f81d7",
+   744 => x"c0088811",
+   745 => x"08535880",
+   746 => x"f09051f4",
+   747 => x"a83f8252",
+   748 => x"80eda851",
+   749 => x"f49f3f81",
+   750 => x"d7c0088c",
+   751 => x"11085357",
+   752 => x"80f0ac51",
+   753 => x"f48f3f91",
+   754 => x"5280eda8",
+   755 => x"51f4863f",
+   756 => x"81d7c008",
+   757 => x"90055280",
+   758 => x"f0c851f3",
+   759 => x"f83f80f0",
+   760 => x"e451f3f1",
+   761 => x"3f80f19c",
+   762 => x"51f3ea3f",
+   763 => x"81d7b008",
+   764 => x"7008535f",
+   765 => x"80efa451",
+   766 => x"f3db3f80",
+   767 => x"f1b051f3",
+   768 => x"d43f81d7",
+   769 => x"b0088411",
+   770 => x"08535b80",
+   771 => x"eff451f3",
+   772 => x"c43f8052",
+   773 => x"80eda851",
+   774 => x"f3bb3f81",
+   775 => x"d7b00888",
+   776 => x"1108535c",
+   777 => x"80f09051",
+   778 => x"f3ab3f81",
+   779 => x"5280eda8",
+   780 => x"51f3a23f",
+   781 => x"81d7b008",
+   782 => x"8c110853",
+   783 => x"5a80f0ac",
+   784 => x"51f3923f",
+   785 => x"925280ed",
+   786 => x"a851f389",
+   787 => x"3f81d7b0",
+   788 => x"08900552",
+   789 => x"80f0c851",
+   790 => x"f2fb3f80",
+   791 => x"f0e451f2",
+   792 => x"f43f7f52",
+   793 => x"80f1f051",
+   794 => x"f2eb3f85",
+   795 => x"5280eda8",
+   796 => x"51f2e23f",
+   797 => x"785280f2",
+   798 => x"8c51f2d9",
+   799 => x"3f8d5280",
+   800 => x"eda851f2",
+   801 => x"d03f6152",
+   802 => x"80f2a851",
+   803 => x"f2c73f87",
+   804 => x"5280eda8",
+   805 => x"51f2be3f",
+   806 => x"605280f2",
+   807 => x"c451f2b5",
+   808 => x"3f815280",
+   809 => x"eda851f2",
+   810 => x"ac3f7d52",
+   811 => x"80f2e051",
+   812 => x"f2a33f80",
+   813 => x"f2fc51f2",
+   814 => x"9c3f7c52",
+   815 => x"80f3b451",
+   816 => x"f2933f80",
+   817 => x"f3d051f2",
+   818 => x"8c3f80f5",
+   819 => x"9c51f285",
+   820 => x"3f81d7a8",
+   821 => x"0881d7ac",
+   822 => x"08818990",
+   823 => x"08818994",
+   824 => x"08727131",
+   825 => x"70742675",
+   826 => x"74317072",
+   827 => x"31818988",
+   828 => x"0c444481",
+   829 => x"898c0c81",
+   830 => x"898c0856",
+   831 => x"80f48855",
+   832 => x"5c595758",
+   833 => x"f1cf3f81",
+   834 => x"89880856",
+   835 => x"80762582",
+   836 => x"a43880f8",
+   837 => x"f8087071",
+   838 => x"9f2c9a3d",
+   839 => x"53565681",
+   840 => x"89880881",
+   841 => x"898c0841",
+   842 => x"537f5470",
+   843 => x"525a8ef6",
+   844 => x"3f66685f",
+   845 => x"8188f80c",
+   846 => x"7d8188fc",
+   847 => x"0c80f8f8",
+   848 => x"08709f2c",
+   849 => x"58568058",
+   850 => x"bd84c078",
+   851 => x"55557652",
+   852 => x"75537951",
+   853 => x"87d23f95",
+   854 => x"3d818988",
+   855 => x"0881898c",
+   856 => x"0841557f",
+   857 => x"56676940",
+   858 => x"537e5470",
+   859 => x"525c8eb6",
+   860 => x"3f64665e",
+   861 => x"8189800c",
+   862 => x"7c818984",
+   863 => x"0c80f8f8",
+   864 => x"08709f2c",
+   865 => x"40588057",
+   866 => x"83dceb94",
+   867 => x"80775555",
+   868 => x"7e527753",
+   869 => x"7b518790",
+   870 => x"3f64665d",
+   871 => x"5b805e8d",
+   872 => x"dd7e5555",
+   873 => x"81898808",
+   874 => x"81898c08",
+   875 => x"59527753",
+   876 => x"795186f4",
+   877 => x"3f666840",
+   878 => x"547e557a",
+   879 => x"527b53a9",
+   880 => x"3dffa805",
+   881 => x"518ddf3f",
+   882 => x"62645e81",
+   883 => x"d7c40c7c",
+   884 => x"81d7c80c",
+   885 => x"80f49851",
+   886 => x"effb3f81",
+   887 => x"88fc0852",
+   888 => x"80f4c851",
+   889 => x"efef3f80",
+   890 => x"f4d051ef",
+   891 => x"e83f8189",
+   892 => x"84085280",
+   893 => x"f4c851ef",
+   894 => x"dc3f81d7",
+   895 => x"c8085280",
+   896 => x"f58051ef",
+   897 => x"d03f80f5",
+   898 => x"9c51efc9",
+   899 => x"3f800b80",
+   900 => x"0ca93d0d",
+   901 => x"0480f5a0",
+   902 => x"51f6a839",
+   903 => x"770857b0",
+   904 => x"53765277",
+   905 => x"5180c2a1",
+   906 => x"3f80c10b",
+   907 => x"81d7bc33",
+   908 => x"5757f8ac",
+   909 => x"39758a38",
+   910 => x"81898c08",
+   911 => x"8126fdd2",
+   912 => x"3880f5d0",
+   913 => x"51ef8e3f",
+   914 => x"80f68851",
+   915 => x"ef873f80",
+   916 => x"f59c51ef",
+   917 => x"803f80f8",
+   918 => x"f8087071",
+   919 => x"9f2c9a3d",
+   920 => x"53565681",
+   921 => x"89880881",
+   922 => x"898c0841",
+   923 => x"537f5470",
+   924 => x"525a8cb2",
+   925 => x"3f66685f",
+   926 => x"8188f80c",
+   927 => x"7d8188fc",
+   928 => x"0c80f8f8",
+   929 => x"08709f2c",
+   930 => x"58568058",
+   931 => x"bd84c078",
+   932 => x"55557652",
+   933 => x"75537951",
+   934 => x"858e3f95",
+   935 => x"3d818988",
+   936 => x"0881898c",
+   937 => x"0841557f",
+   938 => x"56676940",
+   939 => x"537e5470",
+   940 => x"525c8bf2",
+   941 => x"3f64665e",
+   942 => x"8189800c",
+   943 => x"7c818984",
+   944 => x"0c80f8f8",
+   945 => x"08709f2c",
+   946 => x"40588057",
+   947 => x"83dceb94",
+   948 => x"80775555",
+   949 => x"7e527753",
+   950 => x"7b5184cc",
+   951 => x"3f64665d",
+   952 => x"5b805e8d",
+   953 => x"dd7e5555",
+   954 => x"81898808",
+   955 => x"81898c08",
+   956 => x"59527753",
+   957 => x"795184b0",
+   958 => x"3f666840",
+   959 => x"547e557a",
+   960 => x"527b53a9",
+   961 => x"3dffa805",
+   962 => x"518b9b3f",
+   963 => x"62645e81",
+   964 => x"d7c40c7c",
+   965 => x"81d7c80c",
+   966 => x"80f49851",
+   967 => x"edb73f81",
+   968 => x"88fc0852",
+   969 => x"80f4c851",
+   970 => x"edab3f80",
+   971 => x"f4d051ed",
+   972 => x"a43f8189",
+   973 => x"84085280",
+   974 => x"f4c851ed",
+   975 => x"983f81d7",
+   976 => x"c8085280",
+   977 => x"f58051ed",
+   978 => x"8c3f80f5",
+   979 => x"9c51ed85",
+   980 => x"3f800b80",
+   981 => x"0ca93d0d",
+   982 => x"04a93dff",
+   983 => x"a0055280",
+   984 => x"5180d23f",
+   985 => x"9f5380f6",
+   986 => x"a8527c51",
+   987 => x"bfdb3f7a",
+   988 => x"7b81d7b4",
+   989 => x"0c811870",
+   990 => x"81ff0681",
+   991 => x"d7bc3359",
+   992 => x"59595af5",
+   993 => x"fc39ff16",
+   994 => x"707b3160",
+   995 => x"0c5c800b",
+   996 => x"811c5c5c",
+   997 => x"80f8f808",
+   998 => x"7b25f3d8",
+   999 => x"38f6a739",
+  1000 => x"ff3d0d73",
+  1001 => x"82327030",
+  1002 => x"70720780",
+  1003 => x"25800c52",
+  1004 => x"52833d0d",
+  1005 => x"04fe3d0d",
+  1006 => x"74767153",
+  1007 => x"54527182",
+  1008 => x"2e833883",
+  1009 => x"5171812e",
+  1010 => x"9a388172",
+  1011 => x"269f3871",
+  1012 => x"822eb838",
+  1013 => x"71842ea9",
+  1014 => x"3870730c",
+  1015 => x"70800c84",
+  1016 => x"3d0d0480",
+  1017 => x"e40b81d7",
+  1018 => x"b408258b",
+  1019 => x"3880730c",
+  1020 => x"70800c84",
+  1021 => x"3d0d0483",
+  1022 => x"730c7080",
+  1023 => x"0c843d0d",
+  1024 => x"0482730c",
+  1025 => x"70800c84",
+  1026 => x"3d0d0481",
+  1027 => x"730c7080",
+  1028 => x"0c843d0d",
+  1029 => x"04803d0d",
+  1030 => x"74741482",
+  1031 => x"05710c80",
+  1032 => x"0c823d0d",
+  1033 => x"04f73d0d",
+  1034 => x"7b7d7f61",
+  1035 => x"85127082",
+  1036 => x"2b751170",
+  1037 => x"74717084",
+  1038 => x"05530c5a",
+  1039 => x"5a5d5b76",
+  1040 => x"0c7980f8",
+  1041 => x"180c7986",
+  1042 => x"12525758",
+  1043 => x"5a5a7676",
+  1044 => x"24993876",
+  1045 => x"b329822b",
+  1046 => x"79115153",
+  1047 => x"76737084",
+  1048 => x"05550c81",
+  1049 => x"14547574",
+  1050 => x"25f23876",
+  1051 => x"81cc2919",
+  1052 => x"fc110881",
+  1053 => x"05fc120c",
+  1054 => x"7a197008",
+  1055 => x"9fa0130c",
+  1056 => x"5856850b",
+  1057 => x"81d7b40c",
+  1058 => x"75800c8b",
+  1059 => x"3d0d04fe",
+  1060 => x"3d0d0293",
+  1061 => x"05335180",
+  1062 => x"02840597",
+  1063 => x"05335452",
+  1064 => x"70732e88",
+  1065 => x"3871800c",
+  1066 => x"843d0d04",
+  1067 => x"7081d7b8",
+  1068 => x"34810b80",
+  1069 => x"0c843d0d",
+  1070 => x"04f83d0d",
+  1071 => x"7a7c5956",
+  1072 => x"820b8319",
+  1073 => x"55557416",
+  1074 => x"70337533",
+  1075 => x"5b515372",
+  1076 => x"792e80c6",
+  1077 => x"3880c10b",
+  1078 => x"81168116",
+  1079 => x"56565782",
+  1080 => x"7525e338",
+  1081 => x"ffa91770",
+  1082 => x"81ff0655",
+  1083 => x"59738226",
+  1084 => x"83388755",
+  1085 => x"81537680",
+  1086 => x"d22e9838",
+  1087 => x"77527551",
+  1088 => x"be963f80",
+  1089 => x"53728008",
+  1090 => x"25893887",
+  1091 => x"1581d7b4",
+  1092 => x"0c815372",
+  1093 => x"800c8a3d",
+  1094 => x"0d047281",
+  1095 => x"d7b83482",
+  1096 => x"7525ffa2",
+  1097 => x"38ffbd39",
+  1098 => x"8c08028c",
+  1099 => x"0ceb3d0d",
+  1100 => x"800b8c08",
+  1101 => x"f0050c80",
+  1102 => x"0b8c08f4",
+  1103 => x"050c8c08",
+  1104 => x"8c05088c",
+  1105 => x"08900508",
+  1106 => x"5654738c",
+  1107 => x"08f0050c",
+  1108 => x"748c08f4",
+  1109 => x"050c8c08",
+  1110 => x"f8058c08",
+  1111 => x"f0055656",
+  1112 => x"88705475",
+  1113 => x"53765254",
+  1114 => x"bbdf3f80",
+  1115 => x"0b8c08e8",
+  1116 => x"050c800b",
+  1117 => x"8c08ec05",
+  1118 => x"0c8c0894",
+  1119 => x"05088c08",
+  1120 => x"98050856",
+  1121 => x"54738c08",
+  1122 => x"e8050c74",
+  1123 => x"8c08ec05",
+  1124 => x"0c8c08f0",
+  1125 => x"058c08e8",
+  1126 => x"05565688",
+  1127 => x"70547553",
+  1128 => x"765254bb",
+  1129 => x"a43f800b",
+  1130 => x"8c08e805",
+  1131 => x"0c800b8c",
+  1132 => x"08ec050c",
+  1133 => x"8c08fc05",
+  1134 => x"0883ffff",
+  1135 => x"068c08cc",
+  1136 => x"050c8c08",
+  1137 => x"fc050890",
+  1138 => x"2a8c08c4",
+  1139 => x"050c8c08",
+  1140 => x"f4050883",
+  1141 => x"ffff068c",
+  1142 => x"08c8050c",
+  1143 => x"8c08f405",
+  1144 => x"08902a8c",
+  1145 => x"08c0050c",
+  1146 => x"8c08cc05",
+  1147 => x"088c08c8",
+  1148 => x"05082970",
+  1149 => x"8c08dc05",
+  1150 => x"0c8c08cc",
+  1151 => x"05088c08",
+  1152 => x"c0050829",
+  1153 => x"708c08d8",
+  1154 => x"050c8c08",
+  1155 => x"c405088c",
+  1156 => x"08c80508",
+  1157 => x"29708c08",
+  1158 => x"d4050c8c",
+  1159 => x"08c40508",
+  1160 => x"8c08c005",
+  1161 => x"0829708c",
+  1162 => x"08d0050c",
+  1163 => x"8c08dc05",
+  1164 => x"08902a8c",
+  1165 => x"08d80508",
+  1166 => x"118c08d8",
+  1167 => x"050c8c08",
+  1168 => x"d805088c",
+  1169 => x"08d40508",
+  1170 => x"058c08d8",
+  1171 => x"050c5151",
+  1172 => x"5151548c",
+  1173 => x"08d80508",
+  1174 => x"8c08d405",
+  1175 => x"08278f38",
+  1176 => x"8c08d005",
+  1177 => x"08848080",
+  1178 => x"058c08d0",
+  1179 => x"050c8c08",
+  1180 => x"d8050890",
+  1181 => x"2a8c08d0",
+  1182 => x"0508118c",
+  1183 => x"08e0050c",
+  1184 => x"8c08d805",
+  1185 => x"0883ffff",
+  1186 => x"0670902b",
+  1187 => x"8c08dc05",
+  1188 => x"0883ffff",
+  1189 => x"0670128c",
+  1190 => x"08e4050c",
+  1191 => x"52575154",
+  1192 => x"8c08e005",
+  1193 => x"088c08e4",
+  1194 => x"05085654",
+  1195 => x"738c08e8",
+  1196 => x"050c748c",
+  1197 => x"08ec050c",
+  1198 => x"8c08fc05",
+  1199 => x"088c08f0",
+  1200 => x"0508298c",
+  1201 => x"08f80508",
+  1202 => x"8c08f405",
+  1203 => x"08297012",
+  1204 => x"8c08e805",
+  1205 => x"08118c08",
+  1206 => x"e8050c51",
+  1207 => x"55558c08",
+  1208 => x"e805088c",
+  1209 => x"08ec0508",
+  1210 => x"8c088805",
+  1211 => x"08585654",
+  1212 => x"73760c74",
+  1213 => x"84170c8c",
+  1214 => x"08880508",
+  1215 => x"800c973d",
+  1216 => x"0d8c0c04",
+  1217 => x"8c08028c",
+  1218 => x"0cf63d0d",
+  1219 => x"800b8c08",
+  1220 => x"f0050c80",
+  1221 => x"0b8c08f4",
+  1222 => x"050c8c08",
+  1223 => x"8c05088c",
+  1224 => x"08900508",
+  1225 => x"5654738c",
+  1226 => x"08f0050c",
+  1227 => x"748c08f4",
+  1228 => x"050c8c08",
+  1229 => x"f8058c08",
+  1230 => x"f0055656",
+  1231 => x"88705475",
+  1232 => x"53765254",
+  1233 => x"b8833f80",
+  1234 => x"0b8c08f0",
+  1235 => x"050c800b",
+  1236 => x"8c08f405",
+  1237 => x"0c8c08f8",
+  1238 => x"0508308c",
+  1239 => x"08ec050c",
+  1240 => x"8c08fc05",
+  1241 => x"08802e8d",
+  1242 => x"388c08ec",
+  1243 => x"0508ff05",
+  1244 => x"8c08ec05",
+  1245 => x"0c8c08ec",
+  1246 => x"05088c08",
+  1247 => x"f0050c8c",
+  1248 => x"08fc0508",
+  1249 => x"308c08f4",
+  1250 => x"050c8c08",
+  1251 => x"f005088c",
+  1252 => x"08f40508",
+  1253 => x"8c088805",
+  1254 => x"08585654",
+  1255 => x"73760c74",
+  1256 => x"84170c8c",
+  1257 => x"08880508",
+  1258 => x"800c8c3d",
+  1259 => x"0d8c0c04",
+  1260 => x"8c08028c",
+  1261 => x"0cf53d0d",
+  1262 => x"8c089405",
+  1263 => x"089d388c",
+  1264 => x"088c0508",
+  1265 => x"8c089005",
+  1266 => x"088c0888",
+  1267 => x"05085856",
+  1268 => x"5473760c",
+  1269 => x"7484170c",
+  1270 => x"81bf3980",
+  1271 => x"0b8c08f0",
+  1272 => x"050c800b",
+  1273 => x"8c08f405",
+  1274 => x"0c8c088c",
+  1275 => x"05088c08",
+  1276 => x"90050856",
+  1277 => x"54738c08",
+  1278 => x"f0050c74",
+  1279 => x"8c08f405",
+  1280 => x"0c8c08f8",
+  1281 => x"058c08f0",
+  1282 => x"05565688",
+  1283 => x"70547553",
+  1284 => x"765254b6",
+  1285 => x"b43fa00b",
+  1286 => x"8c089405",
+  1287 => x"08318c08",
+  1288 => x"ec050c8c",
+  1289 => x"08ec0508",
+  1290 => x"80249d38",
+  1291 => x"800b8c08",
+  1292 => x"f4050c8c",
+  1293 => x"08ec0508",
+  1294 => x"308c08fc",
+  1295 => x"0508712b",
+  1296 => x"8c08f005",
+  1297 => x"0c54b939",
+  1298 => x"8c08fc05",
+  1299 => x"088c08ec",
+  1300 => x"05082a8c",
+  1301 => x"08e8050c",
+  1302 => x"8c08fc05",
+  1303 => x"088c0894",
+  1304 => x"05082b8c",
+  1305 => x"08f4050c",
+  1306 => x"8c08f805",
+  1307 => x"088c0894",
+  1308 => x"05082b70",
+  1309 => x"8c08e805",
+  1310 => x"08078c08",
+  1311 => x"f0050c54",
+  1312 => x"8c08f005",
+  1313 => x"088c08f4",
+  1314 => x"05088c08",
+  1315 => x"88050858",
+  1316 => x"56547376",
+  1317 => x"0c748417",
+  1318 => x"0c8c0888",
+  1319 => x"0508800c",
+  1320 => x"8d3d0d8c",
+  1321 => x"0c048c08",
+  1322 => x"028c0ccc",
+  1323 => x"3d0d800b",
+  1324 => x"8c08fc05",
+  1325 => x"0c800b8c",
+  1326 => x"08ec050c",
+  1327 => x"800b8c08",
+  1328 => x"f0050c8c",
+  1329 => x"088c0508",
+  1330 => x"8c089005",
+  1331 => x"08565473",
+  1332 => x"8c08ec05",
+  1333 => x"0c748c08",
+  1334 => x"f0050c8c",
+  1335 => x"08f4058c",
+  1336 => x"08ec0556",
+  1337 => x"56887054",
+  1338 => x"75537652",
+  1339 => x"54b4da3f",
+  1340 => x"800b8c08",
+  1341 => x"e4050c80",
+  1342 => x"0b8c08e8",
+  1343 => x"050c8c08",
+  1344 => x"9405088c",
+  1345 => x"08980508",
+  1346 => x"5654738c",
+  1347 => x"08e4050c",
+  1348 => x"748c08e8",
+  1349 => x"050c8c08",
+  1350 => x"ec058c08",
+  1351 => x"e4055656",
+  1352 => x"88705475",
+  1353 => x"53765254",
+  1354 => x"b49f3f8c",
+  1355 => x"08f40508",
+  1356 => x"8025be38",
+  1357 => x"8c08fc05",
+  1358 => x"08098c08",
+  1359 => x"fc050c8c",
+  1360 => x"08d40554",
+  1361 => x"8c08f405",
+  1362 => x"088c08f8",
+  1363 => x"05085755",
+  1364 => x"74527553",
+  1365 => x"7351fbac",
+  1366 => x"3f8c08d4",
+  1367 => x"05088c08",
+  1368 => x"d8050856",
+  1369 => x"54738c08",
+  1370 => x"f4050c74",
+  1371 => x"8c08f805",
+  1372 => x"0c8c08ec",
+  1373 => x"05088025",
+  1374 => x"be388c08",
+  1375 => x"fc050809",
+  1376 => x"8c08fc05",
+  1377 => x"0c8c08d4",
+  1378 => x"05548c08",
+  1379 => x"ec05088c",
+  1380 => x"08f00508",
+  1381 => x"57557452",
+  1382 => x"75537351",
+  1383 => x"fae63f8c",
+  1384 => x"08d40508",
+  1385 => x"8c08d805",
+  1386 => x"08565473",
+  1387 => x"8c08ec05",
+  1388 => x"0c748c08",
+  1389 => x"f0050c8c",
+  1390 => x"08f40508",
+  1391 => x"8c08f805",
+  1392 => x"08565473",
+  1393 => x"8c08d405",
+  1394 => x"0c748c08",
+  1395 => x"d8050c8c",
+  1396 => x"08ec0508",
+  1397 => x"8c08f005",
+  1398 => x"08565473",
+  1399 => x"8c08cc05",
+  1400 => x"0c748c08",
+  1401 => x"d0050c80",
+  1402 => x"0b8c08c8",
+  1403 => x"050c800b",
+  1404 => x"8c08e405",
+  1405 => x"0c800b8c",
+  1406 => x"08e8050c",
+  1407 => x"8c08d405",
+  1408 => x"088c08d8",
+  1409 => x"05085654",
+  1410 => x"738c08e4",
+  1411 => x"050c748c",
+  1412 => x"08e8050c",
+  1413 => x"800b8c08",
+  1414 => x"ffb8050c",
+  1415 => x"800b8c08",
+  1416 => x"ffbc050c",
+  1417 => x"8c08cc05",
+  1418 => x"088c08d0",
+  1419 => x"05085654",
+  1420 => x"738c08ff",
+  1421 => x"b8050c74",
+  1422 => x"8c08ffbc",
+  1423 => x"050c8c08",
+  1424 => x"ffbc0508",
+  1425 => x"8c08ffac",
+  1426 => x"050c8c08",
+  1427 => x"ffb80508",
+  1428 => x"8c08ffa8",
+  1429 => x"050c8c08",
+  1430 => x"e805088c",
+  1431 => x"08ffa405",
+  1432 => x"0c8c08e4",
+  1433 => x"05088c08",
+  1434 => x"ffa0050c",
+  1435 => x"8c08ffa8",
+  1436 => x"050891d4",
+  1437 => x"388c08ff",
+  1438 => x"a005088c",
+  1439 => x"08ffac05",
+  1440 => x"0827868c",
+  1441 => x"388c08ff",
+  1442 => x"ac05088c",
+  1443 => x"08ff8805",
+  1444 => x"0c8c08ff",
+  1445 => x"88050883",
+  1446 => x"ffff26a0",
+  1447 => x"388c08ff",
+  1448 => x"88050881",
+  1449 => x"ff268b38",
+  1450 => x"800b8c08",
+  1451 => x"fed8050c",
+  1452 => x"a939880b",
+  1453 => x"8c08fed8",
+  1454 => x"050c9f39",
+  1455 => x"8c08ff88",
+  1456 => x"0508fe80",
+  1457 => x"0a268b38",
+  1458 => x"900b8c08",
+  1459 => x"fed8050c",
+  1460 => x"8939980b",
+  1461 => x"8c08fed8",
+  1462 => x"050c8c08",
+  1463 => x"fed80508",
+  1464 => x"8c08ff84",
+  1465 => x"050c8c08",
+  1466 => x"ff880508",
+  1467 => x"8c08ff84",
+  1468 => x"05082a80",
+  1469 => x"f6c81133",
+  1470 => x"8c08ff84",
+  1471 => x"050811a0",
+  1472 => x"71318c08",
+  1473 => x"ff8c050c",
+  1474 => x"5151548c",
+  1475 => x"08ff8c05",
+  1476 => x"08802e80",
+  1477 => x"d1388c08",
+  1478 => x"ffac0508",
+  1479 => x"8c08ff8c",
+  1480 => x"05082b8c",
+  1481 => x"08ffac05",
+  1482 => x"0c8c08ff",
+  1483 => x"a005088c",
+  1484 => x"08ff8c05",
+  1485 => x"082ba00b",
+  1486 => x"8c08ff8c",
+  1487 => x"0508318c",
+  1488 => x"08ffa405",
+  1489 => x"08712a70",
+  1490 => x"73078c08",
+  1491 => x"ffa0050c",
+  1492 => x"8c08ffa4",
+  1493 => x"05088c08",
+  1494 => x"ff8c0508",
+  1495 => x"2b8c08ff",
+  1496 => x"a4050c51",
+  1497 => x"56548c08",
+  1498 => x"ffac0508",
+  1499 => x"902a8c08",
+  1500 => x"ff84050c",
+  1501 => x"8c08ffac",
+  1502 => x"050883ff",
+  1503 => x"ff068c08",
+  1504 => x"ff88050c",
+  1505 => x"8c08ffa0",
+  1506 => x"05088c08",
+  1507 => x"ff840508",
+  1508 => x"53705254",
+  1509 => x"9efb3f80",
+  1510 => x"08708c08",
+  1511 => x"fef8050c",
+  1512 => x"8c08ff84",
+  1513 => x"0508538c",
+  1514 => x"08ffa005",
+  1515 => x"0852549e",
+  1516 => x"bb3f8008",
+  1517 => x"708c08ff",
+  1518 => x"80050c8c",
+  1519 => x"08ff8005",
+  1520 => x"088c08ff",
+  1521 => x"88050829",
+  1522 => x"708c08fe",
+  1523 => x"f0050c8c",
+  1524 => x"08fef805",
+  1525 => x"0870902b",
+  1526 => x"8c08ffa4",
+  1527 => x"0508902a",
+  1528 => x"7072078c",
+  1529 => x"08fef805",
+  1530 => x"0c525851",
+  1531 => x"51548c08",
+  1532 => x"fef80508",
+  1533 => x"8c08fef0",
+  1534 => x"05082780",
+  1535 => x"e1388c08",
+  1536 => x"ff800508",
+  1537 => x"ff058c08",
+  1538 => x"ff80050c",
+  1539 => x"8c08fef8",
+  1540 => x"05088c08",
+  1541 => x"ffac0508",
+  1542 => x"058c08fe",
+  1543 => x"f8050c8c",
+  1544 => x"08ffac05",
+  1545 => x"088c08fe",
+  1546 => x"f8050826",
+  1547 => x"b1388c08",
+  1548 => x"fef80508",
+  1549 => x"8c08fef0",
+  1550 => x"050827a2",
+  1551 => x"388c08ff",
+  1552 => x"800508ff",
+  1553 => x"058c08ff",
+  1554 => x"80050c8c",
+  1555 => x"08fef805",
+  1556 => x"088c08ff",
+  1557 => x"ac050805",
+  1558 => x"8c08fef8",
+  1559 => x"050c8c08",
+  1560 => x"fef80508",
+  1561 => x"8c08fef0",
+  1562 => x"0508318c",
+  1563 => x"08fef805",
+  1564 => x"0c8c08fe",
+  1565 => x"f805088c",
+  1566 => x"08ff8405",
+  1567 => x"08537052",
+  1568 => x"549d8e3f",
+  1569 => x"8008708c",
+  1570 => x"08fef405",
+  1571 => x"0c8c08ff",
+  1572 => x"84050853",
+  1573 => x"8c08fef8",
+  1574 => x"05085254",
+  1575 => x"9cce3f80",
+  1576 => x"08708c08",
+  1577 => x"fefc050c",
+  1578 => x"8c08fefc",
+  1579 => x"05088c08",
+  1580 => x"ff880508",
+  1581 => x"29708c08",
+  1582 => x"fef0050c",
+  1583 => x"8c08fef4",
+  1584 => x"05087090",
+  1585 => x"2b8c08ff",
+  1586 => x"a4050883",
+  1587 => x"ffff0670",
+  1588 => x"72078c08",
+  1589 => x"fef4050c",
+  1590 => x"52585151",
+  1591 => x"548c08fe",
+  1592 => x"f405088c",
+  1593 => x"08fef005",
+  1594 => x"082780e1",
+  1595 => x"388c08fe",
+  1596 => x"fc0508ff",
+  1597 => x"058c08fe",
+  1598 => x"fc050c8c",
+  1599 => x"08fef405",
+  1600 => x"088c08ff",
+  1601 => x"ac050805",
+  1602 => x"8c08fef4",
+  1603 => x"050c8c08",
+  1604 => x"ffac0508",
+  1605 => x"8c08fef4",
+  1606 => x"050826b1",
+  1607 => x"388c08fe",
+  1608 => x"f405088c",
+  1609 => x"08fef005",
+  1610 => x"0827a238",
+  1611 => x"8c08fefc",
+  1612 => x"0508ff05",
+  1613 => x"8c08fefc",
+  1614 => x"050c8c08",
+  1615 => x"fef40508",
+  1616 => x"8c08ffac",
+  1617 => x"0508058c",
+  1618 => x"08fef405",
+  1619 => x"0c8c08fe",
+  1620 => x"f405088c",
+  1621 => x"08fef005",
+  1622 => x"08318c08",
+  1623 => x"fef4050c",
+  1624 => x"8c08ff80",
+  1625 => x"05087090",
+  1626 => x"2b708c08",
+  1627 => x"fefc0508",
+  1628 => x"078c08ff",
+  1629 => x"98050c8c",
+  1630 => x"08fef405",
+  1631 => x"088c08ff",
+  1632 => x"a4050c51",
+  1633 => x"54800b8c",
+  1634 => x"08ff9405",
+  1635 => x"0c8af639",
+  1636 => x"8c08ffac",
+  1637 => x"05089738",
+  1638 => x"8c08ffac",
+  1639 => x"05085281",
+  1640 => x"519ac93f",
+  1641 => x"8008708c",
+  1642 => x"08ffac05",
+  1643 => x"0c548c08",
+  1644 => x"ffac0508",
+  1645 => x"8c08fef0",
+  1646 => x"050c8c08",
+  1647 => x"fef00508",
+  1648 => x"83ffff26",
+  1649 => x"a0388c08",
+  1650 => x"fef00508",
+  1651 => x"81ff268b",
+  1652 => x"38800b8c",
+  1653 => x"08fed405",
+  1654 => x"0ca93988",
+  1655 => x"0b8c08fe",
+  1656 => x"d4050c9f",
+  1657 => x"398c08fe",
+  1658 => x"f00508fe",
+  1659 => x"800a268b",
+  1660 => x"38900b8c",
+  1661 => x"08fed405",
+  1662 => x"0c893998",
+  1663 => x"0b8c08fe",
+  1664 => x"d4050c8c",
+  1665 => x"08fed405",
+  1666 => x"088c08fe",
+  1667 => x"f4050c8c",
+  1668 => x"08fef005",
+  1669 => x"088c08fe",
+  1670 => x"f405082a",
+  1671 => x"80f6c811",
+  1672 => x"338c08fe",
+  1673 => x"f4050811",
+  1674 => x"a071318c",
+  1675 => x"08ff8c05",
+  1676 => x"0c515154",
+  1677 => x"8c08ff8c",
+  1678 => x"05089f38",
+  1679 => x"8c08ffa0",
+  1680 => x"05088c08",
+  1681 => x"ffac0508",
+  1682 => x"318c08ff",
+  1683 => x"a0050c81",
+  1684 => x"0b8c08ff",
+  1685 => x"94050c85",
+  1686 => x"8d39a00b",
+  1687 => x"8c08ff8c",
+  1688 => x"0508318c",
+  1689 => x"08ff9005",
+  1690 => x"0c8c08ff",
+  1691 => x"ac05088c",
+  1692 => x"08ff8c05",
+  1693 => x"082b8c08",
+  1694 => x"ffac050c",
+  1695 => x"8c08ffa0",
+  1696 => x"05088c08",
+  1697 => x"ff900508",
+  1698 => x"2a8c08ff",
+  1699 => x"9c050c8c",
+  1700 => x"08ffa005",
+  1701 => x"088c08ff",
+  1702 => x"8c05082b",
+  1703 => x"8c08ffa4",
+  1704 => x"05088c08",
+  1705 => x"ff900508",
+  1706 => x"2a707207",
+  1707 => x"8c08ffa0",
+  1708 => x"050c8c08",
+  1709 => x"ffa40508",
+  1710 => x"8c08ff8c",
+  1711 => x"05082b8c",
+  1712 => x"08ffa405",
+  1713 => x"0c8c08ff",
+  1714 => x"ac050890",
+  1715 => x"2a8c08fe",
+  1716 => x"f0050c8c",
+  1717 => x"08ffac05",
+  1718 => x"0883ffff",
+  1719 => x"068c08fe",
+  1720 => x"f4050c8c",
+  1721 => x"08ff9c05",
+  1722 => x"088c08fe",
+  1723 => x"f0050855",
+  1724 => x"70545155",
+  1725 => x"55989a3f",
+  1726 => x"8008708c",
+  1727 => x"08ff8005",
+  1728 => x"0c8c08fe",
+  1729 => x"f0050853",
+  1730 => x"8c08ff9c",
+  1731 => x"05085254",
+  1732 => x"97da3f80",
+  1733 => x"08708c08",
+  1734 => x"fef8050c",
+  1735 => x"8c08fef8",
+  1736 => x"05088c08",
+  1737 => x"fef40508",
+  1738 => x"29708c08",
+  1739 => x"ff88050c",
+  1740 => x"8c08ff80",
+  1741 => x"05087090",
+  1742 => x"2b8c08ff",
+  1743 => x"a0050890",
+  1744 => x"2a707207",
+  1745 => x"8c08ff80",
+  1746 => x"050c5258",
+  1747 => x"5151548c",
+  1748 => x"08ff8005",
+  1749 => x"088c08ff",
+  1750 => x"88050827",
+  1751 => x"80e1388c",
+  1752 => x"08fef805",
+  1753 => x"08ff058c",
+  1754 => x"08fef805",
+  1755 => x"0c8c08ff",
+  1756 => x"8005088c",
+  1757 => x"08ffac05",
+  1758 => x"08058c08",
+  1759 => x"ff80050c",
+  1760 => x"8c08ffac",
+  1761 => x"05088c08",
+  1762 => x"ff800508",
+  1763 => x"26b1388c",
+  1764 => x"08ff8005",
+  1765 => x"088c08ff",
+  1766 => x"88050827",
+  1767 => x"a2388c08",
+  1768 => x"fef80508",
+  1769 => x"ff058c08",
+  1770 => x"fef8050c",
+  1771 => x"8c08ff80",
+  1772 => x"05088c08",
+  1773 => x"ffac0508",
+  1774 => x"058c08ff",
+  1775 => x"80050c8c",
+  1776 => x"08ff8005",
+  1777 => x"088c08ff",
+  1778 => x"88050831",
+  1779 => x"8c08ff80",
+  1780 => x"050c8c08",
+  1781 => x"ff800508",
+  1782 => x"8c08fef0",
+  1783 => x"05085370",
+  1784 => x"525496ad",
+  1785 => x"3f800870",
+  1786 => x"8c08ff84",
+  1787 => x"050c8c08",
+  1788 => x"fef00508",
+  1789 => x"538c08ff",
+  1790 => x"80050852",
+  1791 => x"5495ed3f",
+  1792 => x"8008708c",
+  1793 => x"08fefc05",
+  1794 => x"0c8c08fe",
+  1795 => x"fc05088c",
+  1796 => x"08fef405",
+  1797 => x"0829708c",
+  1798 => x"08ff8805",
+  1799 => x"0c8c08ff",
+  1800 => x"84050870",
+  1801 => x"902b8c08",
+  1802 => x"ffa00508",
+  1803 => x"83ffff06",
+  1804 => x"7072078c",
+  1805 => x"08ff8405",
+  1806 => x"0c525851",
+  1807 => x"51548c08",
+  1808 => x"ff840508",
+  1809 => x"8c08ff88",
+  1810 => x"05082780",
+  1811 => x"e1388c08",
+  1812 => x"fefc0508",
+  1813 => x"ff058c08",
+  1814 => x"fefc050c",
+  1815 => x"8c08ff84",
+  1816 => x"05088c08",
+  1817 => x"ffac0508",
+  1818 => x"058c08ff",
+  1819 => x"84050c8c",
+  1820 => x"08ffac05",
+  1821 => x"088c08ff",
+  1822 => x"84050826",
+  1823 => x"b1388c08",
+  1824 => x"ff840508",
+  1825 => x"8c08ff88",
+  1826 => x"050827a2",
+  1827 => x"388c08fe",
+  1828 => x"fc0508ff",
+  1829 => x"058c08fe",
+  1830 => x"fc050c8c",
+  1831 => x"08ff8405",
+  1832 => x"088c08ff",
+  1833 => x"ac050805",
+  1834 => x"8c08ff84",
+  1835 => x"050c8c08",
+  1836 => x"ff840508",
+  1837 => x"8c08ff88",
+  1838 => x"0508318c",
+  1839 => x"08ff8405",
+  1840 => x"0c8c08fe",
+  1841 => x"f8050870",
+  1842 => x"902b708c",
+  1843 => x"08fefc05",
+  1844 => x"08078c08",
+  1845 => x"ff94050c",
+  1846 => x"8c08ff84",
+  1847 => x"05088c08",
+  1848 => x"ffa0050c",
+  1849 => x"51548c08",
+  1850 => x"ffac0508",
+  1851 => x"902a8c08",
+  1852 => x"fef0050c",
+  1853 => x"8c08ffac",
+  1854 => x"050883ff",
+  1855 => x"ff068c08",
+  1856 => x"fef4050c",
+  1857 => x"8c08ffa0",
+  1858 => x"05088c08",
+  1859 => x"fef00508",
+  1860 => x"53705254",
+  1861 => x"93fb3f80",
+  1862 => x"08708c08",
+  1863 => x"ff80050c",
+  1864 => x"8c08fef0",
+  1865 => x"0508538c",
+  1866 => x"08ffa005",
+  1867 => x"08525493",
+  1868 => x"bb3f8008",
+  1869 => x"708c08fe",
+  1870 => x"f8050c8c",
+  1871 => x"08fef805",
+  1872 => x"088c08fe",
+  1873 => x"f4050829",
+  1874 => x"708c08ff",
+  1875 => x"88050c8c",
+  1876 => x"08ff8005",
+  1877 => x"0870902b",
+  1878 => x"8c08ffa4",
+  1879 => x"0508902a",
+  1880 => x"7072078c",
+  1881 => x"08ff8005",
+  1882 => x"0c525851",
+  1883 => x"51548c08",
+  1884 => x"ff800508",
+  1885 => x"8c08ff88",
+  1886 => x"05082780",
+  1887 => x"e1388c08",
+  1888 => x"fef80508",
+  1889 => x"ff058c08",
+  1890 => x"fef8050c",
+  1891 => x"8c08ff80",
+  1892 => x"05088c08",
+  1893 => x"ffac0508",
+  1894 => x"058c08ff",
+  1895 => x"80050c8c",
+  1896 => x"08ffac05",
+  1897 => x"088c08ff",
+  1898 => x"80050826",
+  1899 => x"b1388c08",
+  1900 => x"ff800508",
+  1901 => x"8c08ff88",
+  1902 => x"050827a2",
+  1903 => x"388c08fe",
+  1904 => x"f80508ff",
+  1905 => x"058c08fe",
+  1906 => x"f8050c8c",
+  1907 => x"08ff8005",
+  1908 => x"088c08ff",
+  1909 => x"ac050805",
+  1910 => x"8c08ff80",
+  1911 => x"050c8c08",
+  1912 => x"ff800508",
+  1913 => x"8c08ff88",
+  1914 => x"0508318c",
+  1915 => x"08ff8005",
+  1916 => x"0c8c08ff",
+  1917 => x"8005088c",
+  1918 => x"08fef005",
+  1919 => x"08537052",
+  1920 => x"54928e3f",
+  1921 => x"8008708c",
+  1922 => x"08ff8405",
+  1923 => x"0c8c08fe",
+  1924 => x"f0050853",
+  1925 => x"8c08ff80",
+  1926 => x"05085254",
+  1927 => x"91ce3f80",
+  1928 => x"08708c08",
+  1929 => x"fefc050c",
+  1930 => x"8c08fefc",
+  1931 => x"05088c08",
+  1932 => x"fef40508",
+  1933 => x"29708c08",
+  1934 => x"ff88050c",
+  1935 => x"8c08ff84",
+  1936 => x"05087090",
+  1937 => x"2b8c08ff",
+  1938 => x"a4050883",
+  1939 => x"ffff0670",
+  1940 => x"72078c08",
+  1941 => x"ff84050c",
+  1942 => x"52585151",
+  1943 => x"548c08ff",
+  1944 => x"8405088c",
+  1945 => x"08ff8805",
+  1946 => x"082780e1",
+  1947 => x"388c08fe",
+  1948 => x"fc0508ff",
+  1949 => x"058c08fe",
+  1950 => x"fc050c8c",
+  1951 => x"08ff8405",
+  1952 => x"088c08ff",
+  1953 => x"ac050805",
+  1954 => x"8c08ff84",
+  1955 => x"050c8c08",
+  1956 => x"ffac0508",
+  1957 => x"8c08ff84",
+  1958 => x"050826b1",
+  1959 => x"388c08ff",
+  1960 => x"8405088c",
+  1961 => x"08ff8805",
+  1962 => x"0827a238",
+  1963 => x"8c08fefc",
+  1964 => x"0508ff05",
+  1965 => x"8c08fefc",
+  1966 => x"050c8c08",
+  1967 => x"ff840508",
+  1968 => x"8c08ffac",
+  1969 => x"0508058c",
+  1970 => x"08ff8405",
+  1971 => x"0c8c08ff",
+  1972 => x"8405088c",
+  1973 => x"08ff8805",
+  1974 => x"08318c08",
+  1975 => x"ff84050c",
+  1976 => x"8c08fef8",
+  1977 => x"05087090",
+  1978 => x"2b708c08",
+  1979 => x"fefc0508",
+  1980 => x"078c08ff",
+  1981 => x"98050c8c",
+  1982 => x"08ff8405",
+  1983 => x"088c08ff",
+  1984 => x"a4050c51",
+  1985 => x"548c08c8",
+  1986 => x"0508802e",
+  1987 => x"8ea3388c",
+  1988 => x"08ffa405",
+  1989 => x"088c08ff",
+  1990 => x"8c05082a",
+  1991 => x"8c08ffb4",
+  1992 => x"050c800b",
+  1993 => x"8c08ffb0",
+  1994 => x"050c8c08",
+  1995 => x"c8050856",
+  1996 => x"8c08ffb0",
+  1997 => x"05088c08",
+  1998 => x"ffb40508",
+  1999 => x"56547376",
+  2000 => x"0c748417",
+  2001 => x"0c8dea39",
+  2002 => x"8c08ffa0",
+  2003 => x"05088c08",
+  2004 => x"ffa80508",
+  2005 => x"2780d138",
+  2006 => x"800b8c08",
+  2007 => x"ff98050c",
+  2008 => x"800b8c08",
+  2009 => x"ff94050c",
+  2010 => x"8c08c805",
+  2011 => x"08802e8d",
+  2012 => x"c0388c08",
+  2013 => x"ffa40508",
+  2014 => x"8c08ffb4",
+  2015 => x"050c8c08",
+  2016 => x"ffa00508",
+  2017 => x"8c08ffb0",
+  2018 => x"050c8c08",
+  2019 => x"c8050856",
+  2020 => x"8c08ffb0",
+  2021 => x"05088c08",
+  2022 => x"ffb40508",
+  2023 => x"56547376",
+  2024 => x"0c748417",
+  2025 => x"0c8d8a39",
+  2026 => x"8c08ffa8",
+  2027 => x"05088c08",
+  2028 => x"fef0050c",
+  2029 => x"8c08fef0",
+  2030 => x"050883ff",
+  2031 => x"ff26a038",
+  2032 => x"8c08fef0",
+  2033 => x"050881ff",
+  2034 => x"268b3880",
+  2035 => x"0b8c08fe",
+  2036 => x"d0050ca9",
+  2037 => x"39880b8c",
+  2038 => x"08fed005",
+  2039 => x"0c9f398c",
+  2040 => x"08fef005",
+  2041 => x"08fe800a",
+  2042 => x"268b3890",
+  2043 => x"0b8c08fe",
+  2044 => x"d0050c89",
+  2045 => x"39980b8c",
+  2046 => x"08fed005",
+  2047 => x"0c8c08fe",
+  2048 => x"d005088c",
+  2049 => x"08fef405",
+  2050 => x"0c8c08fe",
+  2051 => x"f005088c",
+  2052 => x"08fef405",
+  2053 => x"082a80f6",
+  2054 => x"c811338c",
+  2055 => x"08fef405",
+  2056 => x"0811a071",
+  2057 => x"318c08ff",
+  2058 => x"8c050c51",
+  2059 => x"51548c08",
+  2060 => x"ff8c0508",
+  2061 => x"81d9388c",
+  2062 => x"08ffa005",
+  2063 => x"088c08ff",
+  2064 => x"a8050826",
+  2065 => x"93388c08",
+  2066 => x"ffa40508",
+  2067 => x"8c08ffac",
+  2068 => x"05082784",
+  2069 => x"3880e839",
+  2070 => x"810b8c08",
+  2071 => x"ff98050c",
+  2072 => x"8c08ffa4",
+  2073 => x"05088c08",
+  2074 => x"ffac0508",
+  2075 => x"318c08fe",
+  2076 => x"f0050c8c",
+  2077 => x"08ffa005",
+  2078 => x"088c08ff",
+  2079 => x"a8050831",
+  2080 => x"708c08fe",
+  2081 => x"cc050c54",
+  2082 => x"8c08ffa4",
+  2083 => x"05088c08",
+  2084 => x"fef00508",
+  2085 => x"278f388c",
+  2086 => x"08fecc05",
+  2087 => x"08ff058c",
+  2088 => x"08fecc05",
+  2089 => x"0c8c08fe",
+  2090 => x"cc05088c",
+  2091 => x"08ffa005",
+  2092 => x"0c8c08fe",
+  2093 => x"f005088c",
+  2094 => x"08ffa405",
+  2095 => x"0c893980",
+  2096 => x"0b8c08ff",
+  2097 => x"98050c80",
+  2098 => x"0b8c08ff",
+  2099 => x"94050c8c",
+  2100 => x"08c80508",
+  2101 => x"802e8ad9",
+  2102 => x"388c08ff",
+  2103 => x"a405088c",
+  2104 => x"08ffb405",
+  2105 => x"0c8c08ff",
+  2106 => x"a005088c",
+  2107 => x"08ffb005",
+  2108 => x"0c8c08c8",
+  2109 => x"0508568c",
+  2110 => x"08ffb005",
+  2111 => x"088c08ff",
+  2112 => x"b4050856",
+  2113 => x"5473760c",
+  2114 => x"7484170c",
+  2115 => x"8aa339a0",
+  2116 => x"0b8c08ff",
+  2117 => x"8c050831",
+  2118 => x"8c08ff90",
+  2119 => x"050c8c08",
+  2120 => x"ffa80508",
+  2121 => x"8c08ff8c",
+  2122 => x"05082b8c",
+  2123 => x"08ffac05",
+  2124 => x"088c08ff",
+  2125 => x"9005082a",
+  2126 => x"7072078c",
+  2127 => x"08ffa805",
+  2128 => x"0c8c08ff",
+  2129 => x"ac05088c",
+  2130 => x"08ff8c05",
+  2131 => x"082b8c08",
+  2132 => x"ffac050c",
+  2133 => x"8c08ffa0",
+  2134 => x"05088c08",
+  2135 => x"ff900508",
+  2136 => x"2a8c08ff",
+  2137 => x"9c050c8c",
+  2138 => x"08ffa005",
+  2139 => x"088c08ff",
+  2140 => x"8c05082b",
+  2141 => x"8c08ffa4",
+  2142 => x"05088c08",
+  2143 => x"ff900508",
+  2144 => x"2a707207",
+  2145 => x"8c08ffa0",
+  2146 => x"050c8c08",
+  2147 => x"ffa40508",
+  2148 => x"8c08ff8c",
+  2149 => x"05082b8c",
+  2150 => x"08ffa405",
+  2151 => x"0c8c08ff",
+  2152 => x"a8050890",
+  2153 => x"2a8c08fe",
+  2154 => x"f8050c8c",
+  2155 => x"08ffa805",
+  2156 => x"0883ffff",
+  2157 => x"068c08fe",
+  2158 => x"fc050c8c",
+  2159 => x"08ff9c05",
+  2160 => x"088c08fe",
+  2161 => x"f8050857",
+  2162 => x"70565152",
+  2163 => x"5255558a",
+  2164 => x"c03f8008",
+  2165 => x"708c08ff",
+  2166 => x"88050c8c",
+  2167 => x"08fef805",
+  2168 => x"08538c08",
+  2169 => x"ff9c0508",
+  2170 => x"52548a80",
+  2171 => x"3f800870",
+  2172 => x"8c08ff80",
+  2173 => x"050c8c08",
+  2174 => x"ff800508",
+  2175 => x"8c08fefc",
+  2176 => x"05082970",
+  2177 => x"8c08fee8",
+  2178 => x"050c8c08",
+  2179 => x"ff880508",
+  2180 => x"70902b8c",
+  2181 => x"08ffa005",
+  2182 => x"08902a70",
+  2183 => x"72078c08",
+  2184 => x"ff88050c",
+  2185 => x"52585151",
+  2186 => x"548c08ff",
+  2187 => x"8805088c",
+  2188 => x"08fee805",
+  2189 => x"082780e1",
+  2190 => x"388c08ff",
+  2191 => x"800508ff",
+  2192 => x"058c08ff",
+  2193 => x"80050c8c",
+  2194 => x"08ff8805",
+  2195 => x"088c08ff",
+  2196 => x"a8050805",
+  2197 => x"8c08ff88",
+  2198 => x"050c8c08",
+  2199 => x"ffa80508",
+  2200 => x"8c08ff88",
+  2201 => x"050826b1",
+  2202 => x"388c08ff",
+  2203 => x"8805088c",
+  2204 => x"08fee805",
+  2205 => x"0827a238",
+  2206 => x"8c08ff80",
+  2207 => x"0508ff05",
+  2208 => x"8c08ff80",
+  2209 => x"050c8c08",
+  2210 => x"ff880508",
+  2211 => x"8c08ffa8",
+  2212 => x"0508058c",
+  2213 => x"08ff8805",
+  2214 => x"0c8c08ff",
+  2215 => x"8805088c",
+  2216 => x"08fee805",
+  2217 => x"08318c08",
+  2218 => x"ff88050c",
+  2219 => x"8c08ff88",
+  2220 => x"05088c08",
+  2221 => x"fef80508",
+  2222 => x"53705254",
+  2223 => x"88d33f80",
+  2224 => x"08708c08",
+  2225 => x"feec050c",
+  2226 => x"8c08fef8",
+  2227 => x"0508538c",
+  2228 => x"08ff8805",
+  2229 => x"08525488",
+  2230 => x"933f8008",
+  2231 => x"708c08ff",
+  2232 => x"84050c8c",
+  2233 => x"08ff8405",
+  2234 => x"088c08fe",
+  2235 => x"fc050829",
+  2236 => x"708c08fe",
+  2237 => x"e8050c8c",
+  2238 => x"08feec05",
+  2239 => x"0870902b",
+  2240 => x"8c08ffa0",
+  2241 => x"050883ff",
+  2242 => x"ff067072",
+  2243 => x"078c08fe",
+  2244 => x"ec050c52",
+  2245 => x"58515154",
+  2246 => x"8c08feec",
+  2247 => x"05088c08",
+  2248 => x"fee80508",
+  2249 => x"2780e138",
+  2250 => x"8c08ff84",
+  2251 => x"0508ff05",
+  2252 => x"8c08ff84",
+  2253 => x"050c8c08",
+  2254 => x"feec0508",
+  2255 => x"8c08ffa8",
+  2256 => x"0508058c",
+  2257 => x"08feec05",
+  2258 => x"0c8c08ff",
+  2259 => x"a805088c",
+  2260 => x"08feec05",
+  2261 => x"0826b138",
+  2262 => x"8c08feec",
+  2263 => x"05088c08",
+  2264 => x"fee80508",
+  2265 => x"27a2388c",
+  2266 => x"08ff8405",
+  2267 => x"08ff058c",
+  2268 => x"08ff8405",
+  2269 => x"0c8c08fe",
+  2270 => x"ec05088c",
+  2271 => x"08ffa805",
+  2272 => x"08058c08",
+  2273 => x"feec050c",
+  2274 => x"8c08feec",
+  2275 => x"05088c08",
+  2276 => x"fee80508",
+  2277 => x"318c08fe",
+  2278 => x"ec050c8c",
+  2279 => x"08ff8005",
+  2280 => x"0870902b",
+  2281 => x"708c08ff",
+  2282 => x"84050807",
+  2283 => x"8c08ff98",
+  2284 => x"050c8c08",
+  2285 => x"feec0508",
+  2286 => x"8c08ffa0",
+  2287 => x"050c8c08",
+  2288 => x"ff980508",
+  2289 => x"83ffff06",
+  2290 => x"8c08ff80",
+  2291 => x"050c8c08",
+  2292 => x"ff980508",
+  2293 => x"902a8c08",
+  2294 => x"ff88050c",
+  2295 => x"8c08ffac",
+  2296 => x"050883ff",
+  2297 => x"ff068c08",
+  2298 => x"ff84050c",
+  2299 => x"8c08ffac",
+  2300 => x"0508902a",
+  2301 => x"8c08fee4",
+  2302 => x"050c8c08",
+  2303 => x"ff800508",
+  2304 => x"8c08ff84",
+  2305 => x"05082970",
+  2306 => x"8c08fee8",
+  2307 => x"050c8c08",
+  2308 => x"ff800508",
+  2309 => x"8c08fee4",
+  2310 => x"05082970",
+  2311 => x"8c08feec",
+  2312 => x"050c8c08",
+  2313 => x"ff880508",
+  2314 => x"8c08ff84",
+  2315 => x"05082970",
+  2316 => x"8c08fef8",
+  2317 => x"050c8c08",
+  2318 => x"ff880508",
+  2319 => x"8c08fee4",
+  2320 => x"05082970",
+  2321 => x"8c08fefc",
+  2322 => x"050c8c08",
+  2323 => x"fee80508",
+  2324 => x"902a8c08",
+  2325 => x"feec0508",
+  2326 => x"118c08fe",
+  2327 => x"ec050c8c",
+  2328 => x"08feec05",
+  2329 => x"088c08fe",
+  2330 => x"f8050805",
+  2331 => x"8c08feec",
+  2332 => x"050c5151",
+  2333 => x"51515151",
+  2334 => x"548c08fe",
+  2335 => x"ec05088c",
+  2336 => x"08fef805",
+  2337 => x"08279138",
+  2338 => x"8c08fefc",
+  2339 => x"05088480",
+  2340 => x"80058c08",
+  2341 => x"fefc050c",
+  2342 => x"8c08feec",
+  2343 => x"0508902a",
+  2344 => x"8c08fefc",
+  2345 => x"0508118c",
+  2346 => x"08fef005",
+  2347 => x"0c8c08fe",
+  2348 => x"ec050883",
+  2349 => x"ffff0670",
+  2350 => x"902b8c08",
+  2351 => x"fee80508",
+  2352 => x"83ffff06",
+  2353 => x"70128c08",
+  2354 => x"fef4050c",
+  2355 => x"52575154",
+  2356 => x"8c08fef0",
+  2357 => x"05088c08",
+  2358 => x"ffa00508",
+  2359 => x"26a6388c",
+  2360 => x"08fef005",
+  2361 => x"088c08ff",
+  2362 => x"a005082e",
+  2363 => x"09810680",
+  2364 => x"fe388c08",
+  2365 => x"fef40508",
+  2366 => x"8c08ffa4",
+  2367 => x"05082684",
+  2368 => x"3880ec39",
+  2369 => x"8c08ff98",
+  2370 => x"0508ff05",
+  2371 => x"8c08ff98",
+  2372 => x"050c8c08",
+  2373 => x"fef40508",
+  2374 => x"8c08ffac",
+  2375 => x"0508318c",
+  2376 => x"08fee405",
+  2377 => x"0c8c08fe",
+  2378 => x"f005088c",
+  2379 => x"08ffa805",
+  2380 => x"0831708c",
+  2381 => x"08fec805",
+  2382 => x"0c548c08",
+  2383 => x"fef40508",
+  2384 => x"8c08fee4",
+  2385 => x"0508278f",
+  2386 => x"388c08fe",
+  2387 => x"c80508ff",
+  2388 => x"058c08fe",
+  2389 => x"c8050c8c",
+  2390 => x"08fec805",
+  2391 => x"088c08fe",
+  2392 => x"f0050c8c",
+  2393 => x"08fee405",
+  2394 => x"088c08fe",
+  2395 => x"f4050c80",
+  2396 => x"0b8c08ff",
+  2397 => x"94050c8c",
+  2398 => x"08c80508",
+  2399 => x"802e81b1",
+  2400 => x"388c08ff",
+  2401 => x"a405088c",
+  2402 => x"08fef405",
+  2403 => x"08318c08",
+  2404 => x"fee4050c",
+  2405 => x"8c08ffa0",
+  2406 => x"05088c08",
+  2407 => x"fef00508",
+  2408 => x"31708c08",
+  2409 => x"fec4050c",
+  2410 => x"548c08ff",
+  2411 => x"a405088c",
+  2412 => x"08fee405",
+  2413 => x"08278f38",
+  2414 => x"8c08fec4",
+  2415 => x"0508ff05",
+  2416 => x"8c08fec4",
+  2417 => x"050c8c08",
+  2418 => x"fec40508",
+  2419 => x"8c08ffa0",
+  2420 => x"050c8c08",
+  2421 => x"fee40508",
+  2422 => x"8c08ffa4",
+  2423 => x"050c8c08",
+  2424 => x"ffa00508",
+  2425 => x"8c08ff90",
+  2426 => x"05082b8c",
+  2427 => x"08ffa405",
+  2428 => x"088c08ff",
+  2429 => x"8c05082a",
+  2430 => x"7072078c",
+  2431 => x"08ffb405",
+  2432 => x"0c8c08ff",
+  2433 => x"a005088c",
+  2434 => x"08ff8c05",
+  2435 => x"082a8c08",
+  2436 => x"ffb0050c",
+  2437 => x"8c08c805",
+  2438 => x"08585555",
+  2439 => x"8c08ffb0",
+  2440 => x"05088c08",
+  2441 => x"ffb40508",
+  2442 => x"56547376",
+  2443 => x"0c748417",
+  2444 => x"0c800b8c",
+  2445 => x"08fedc05",
+  2446 => x"0c800b8c",
+  2447 => x"08fee005",
+  2448 => x"0c8c08ff",
+  2449 => x"9405088c",
+  2450 => x"08fedc05",
+  2451 => x"0c8c08ff",
+  2452 => x"9805088c",
+  2453 => x"08fee005",
+  2454 => x"0c8c08fe",
+  2455 => x"dc05088c",
+  2456 => x"08fee005",
+  2457 => x"08565473",
+  2458 => x"8c08c005",
+  2459 => x"0c748c08",
+  2460 => x"c4050c8c",
+  2461 => x"08c00508",
+  2462 => x"8c08c405",
+  2463 => x"08565473",
+  2464 => x"8c08dc05",
+  2465 => x"0c748c08",
+  2466 => x"e0050c8c",
+  2467 => x"08fc0508",
+  2468 => x"802eb338",
+  2469 => x"8c08c005",
+  2470 => x"548c08dc",
+  2471 => x"05088c08",
+  2472 => x"e0050857",
+  2473 => x"55745275",
+  2474 => x"537351d8",
+  2475 => x"d73f8c08",
+  2476 => x"c005088c",
+  2477 => x"08c40508",
+  2478 => x"5654738c",
+  2479 => x"08dc050c",
+  2480 => x"748c08e0",
+  2481 => x"050c8c08",
+  2482 => x"dc05088c",
+  2483 => x"08e00508",
+  2484 => x"8c088805",
+  2485 => x"08585654",
+  2486 => x"73760c74",
+  2487 => x"84170c8c",
+  2488 => x"08880508",
+  2489 => x"800cb63d",
+  2490 => x"0d8c0c04",
+  2491 => x"8c08028c",
+  2492 => x"0cfd3d0d",
+  2493 => x"80538c08",
+  2494 => x"8c050852",
+  2495 => x"8c088805",
+  2496 => x"085182de",
+  2497 => x"3f800870",
+  2498 => x"800c5485",
+  2499 => x"3d0d8c0c",
+  2500 => x"048c0802",
+  2501 => x"8c0cfd3d",
+  2502 => x"0d81538c",
+  2503 => x"088c0508",
+  2504 => x"528c0888",
+  2505 => x"05085182",
+  2506 => x"b93f8008",
+  2507 => x"70800c54",
+  2508 => x"853d0d8c",
+  2509 => x"0c048c08",
+  2510 => x"028c0cf9",
+  2511 => x"3d0d800b",
+  2512 => x"8c08fc05",
+  2513 => x"0c8c0888",
+  2514 => x"05088025",
+  2515 => x"ab388c08",
+  2516 => x"88050830",
+  2517 => x"8c088805",
+  2518 => x"0c800b8c",
+  2519 => x"08f4050c",
+  2520 => x"8c08fc05",
+  2521 => x"08883881",
+  2522 => x"0b8c08f4",
+  2523 => x"050c8c08",
+  2524 => x"f405088c",
+  2525 => x"08fc050c",
+  2526 => x"8c088c05",
+  2527 => x"088025ab",
+  2528 => x"388c088c",
+  2529 => x"0508308c",
+  2530 => x"088c050c",
+  2531 => x"800b8c08",
+  2532 => x"f0050c8c",
+  2533 => x"08fc0508",
+  2534 => x"8838810b",
+  2535 => x"8c08f005",
+  2536 => x"0c8c08f0",
+  2537 => x"05088c08",
+  2538 => x"fc050c80",
+  2539 => x"538c088c",
+  2540 => x"0508528c",
+  2541 => x"08880508",
+  2542 => x"5181a73f",
+  2543 => x"8008708c",
+  2544 => x"08f8050c",
+  2545 => x"548c08fc",
+  2546 => x"0508802e",
+  2547 => x"8c388c08",
+  2548 => x"f8050830",
+  2549 => x"8c08f805",
+  2550 => x"0c8c08f8",
+  2551 => x"05087080",
+  2552 => x"0c54893d",
+  2553 => x"0d8c0c04",
+  2554 => x"8c08028c",
+  2555 => x"0cfb3d0d",
+  2556 => x"800b8c08",
+  2557 => x"fc050c8c",
+  2558 => x"08880508",
+  2559 => x"80259338",
+  2560 => x"8c088805",
+  2561 => x"08308c08",
+  2562 => x"88050c81",
+  2563 => x"0b8c08fc",
+  2564 => x"050c8c08",
+  2565 => x"8c050880",
+  2566 => x"258c388c",
+  2567 => x"088c0508",
+  2568 => x"308c088c",
+  2569 => x"050c8153",
+  2570 => x"8c088c05",
+  2571 => x"08528c08",
+  2572 => x"88050851",
+  2573 => x"ad3f8008",
+  2574 => x"708c08f8",
+  2575 => x"050c548c",
+  2576 => x"08fc0508",
+  2577 => x"802e8c38",
+  2578 => x"8c08f805",
+  2579 => x"08308c08",
+  2580 => x"f8050c8c",
+  2581 => x"08f80508",
+  2582 => x"70800c54",
+  2583 => x"873d0d8c",
+  2584 => x"0c048c08",
+  2585 => x"028c0cfd",
+  2586 => x"3d0d810b",
+  2587 => x"8c08fc05",
+  2588 => x"0c800b8c",
+  2589 => x"08f8050c",
+  2590 => x"8c088c05",
+  2591 => x"088c0888",
+  2592 => x"050827ac",
+  2593 => x"388c08fc",
+  2594 => x"0508802e",
+  2595 => x"a338800b",
+  2596 => x"8c088c05",
+  2597 => x"08249938",
+  2598 => x"8c088c05",
+  2599 => x"08108c08",
+  2600 => x"8c050c8c",
+  2601 => x"08fc0508",
+  2602 => x"108c08fc",
+  2603 => x"050cc939",
+  2604 => x"8c08fc05",
+  2605 => x"08802e80",
+  2606 => x"c9388c08",
+  2607 => x"8c05088c",
+  2608 => x"08880508",
+  2609 => x"26a1388c",
+  2610 => x"08880508",
+  2611 => x"8c088c05",
+  2612 => x"08318c08",
+  2613 => x"88050c8c",
+  2614 => x"08f80508",
+  2615 => x"8c08fc05",
+  2616 => x"08078c08",
+  2617 => x"f8050c8c",
+  2618 => x"08fc0508",
+  2619 => x"812a8c08",
+  2620 => x"fc050c8c",
+  2621 => x"088c0508",
+  2622 => x"812a8c08",
+  2623 => x"8c050cff",
+  2624 => x"af398c08",
+  2625 => x"90050880",
+  2626 => x"2e8f388c",
+  2627 => x"08880508",
+  2628 => x"708c08f4",
+  2629 => x"050c518d",
+  2630 => x"398c08f8",
+  2631 => x"0508708c",
+  2632 => x"08f4050c",
+  2633 => x"518c08f4",
+  2634 => x"0508800c",
+  2635 => x"853d0d8c",
+  2636 => x"0c04ff3d",
+  2637 => x"0d735281",
+  2638 => x"81c80851",
+  2639 => x"963f833d",
+  2640 => x"0d04ff3d",
+  2641 => x"0d735281",
+  2642 => x"81c80851",
+  2643 => x"90953f83",
+  2644 => x"3d0d04f3",
+  2645 => x"3d0d7f61",
+  2646 => x"8b1170f8",
+  2647 => x"065c5555",
+  2648 => x"5e729626",
+  2649 => x"83389059",
+  2650 => x"80792474",
+  2651 => x"7a260753",
+  2652 => x"80547274",
+  2653 => x"2e098106",
+  2654 => x"80cb387d",
+  2655 => x"518ce33f",
+  2656 => x"7883f726",
+  2657 => x"80c63878",
+  2658 => x"832a7010",
+  2659 => x"101080f9",
+  2660 => x"c0058c11",
+  2661 => x"0859595a",
+  2662 => x"76782e83",
+  2663 => x"b0388417",
+  2664 => x"08fc0656",
+  2665 => x"8c170888",
+  2666 => x"1808718c",
+  2667 => x"120c8812",
+  2668 => x"0c587517",
+  2669 => x"84110881",
+  2670 => x"0784120c",
+  2671 => x"537d518c",
+  2672 => x"a23f8817",
+  2673 => x"5473800c",
+  2674 => x"8f3d0d04",
+  2675 => x"78892a79",
+  2676 => x"832a5b53",
+  2677 => x"72802ebf",
+  2678 => x"3878862a",
+  2679 => x"b8055a84",
+  2680 => x"7327b438",
+  2681 => x"80db135a",
+  2682 => x"947327ab",
+  2683 => x"38788c2a",
+  2684 => x"80ee055a",
+  2685 => x"80d47327",
+  2686 => x"9e38788f",
+  2687 => x"2a80f705",
+  2688 => x"5a82d473",
+  2689 => x"27913878",
+  2690 => x"922a80fc",
+  2691 => x"055a8ad4",
+  2692 => x"73278438",
+  2693 => x"80fe5a79",
+  2694 => x"10101080",
+  2695 => x"f9c0058c",
+  2696 => x"11085855",
+  2697 => x"76752ea3",
+  2698 => x"38841708",
+  2699 => x"fc06707a",
+  2700 => x"31555673",
+  2701 => x"8f2488d5",
+  2702 => x"38738025",
+  2703 => x"fee6388c",
+  2704 => x"17085776",
+  2705 => x"752e0981",
+  2706 => x"06df3881",
+  2707 => x"1a5a80f9",
+  2708 => x"d0085776",
+  2709 => x"80f9c82e",
+  2710 => x"82c03884",
+  2711 => x"1708fc06",
+  2712 => x"707a3155",
+  2713 => x"56738f24",
+  2714 => x"81f93880",
+  2715 => x"f9c80b80",
+  2716 => x"f9d40c80",
+  2717 => x"f9c80b80",
+  2718 => x"f9d00c73",
+  2719 => x"8025feb2",
+  2720 => x"3883ff76",
+  2721 => x"2783df38",
+  2722 => x"75892a76",
+  2723 => x"832a5553",
+  2724 => x"72802ebf",
+  2725 => x"3875862a",
+  2726 => x"b8055484",
+  2727 => x"7327b438",
+  2728 => x"80db1354",
+  2729 => x"947327ab",
+  2730 => x"38758c2a",
+  2731 => x"80ee0554",
+  2732 => x"80d47327",
+  2733 => x"9e38758f",
+  2734 => x"2a80f705",
+  2735 => x"5482d473",
+  2736 => x"27913875",
+  2737 => x"922a80fc",
+  2738 => x"05548ad4",
+  2739 => x"73278438",
+  2740 => x"80fe5473",
+  2741 => x"10101080",
+  2742 => x"f9c00588",
+  2743 => x"11085658",
+  2744 => x"74782e86",
+  2745 => x"cf388415",
+  2746 => x"08fc0653",
+  2747 => x"7573278d",
+  2748 => x"38881508",
+  2749 => x"5574782e",
+  2750 => x"098106ea",
+  2751 => x"388c1508",
+  2752 => x"80f9c00b",
+  2753 => x"84050871",
+  2754 => x"8c1a0c76",
+  2755 => x"881a0c78",
+  2756 => x"88130c78",
+  2757 => x"8c180c5d",
+  2758 => x"58795380",
+  2759 => x"7a2483e6",
+  2760 => x"3872822c",
+  2761 => x"81712b5c",
+  2762 => x"537a7c26",
+  2763 => x"8198387b",
+  2764 => x"7b065372",
+  2765 => x"82f13879",
+  2766 => x"fc068405",
+  2767 => x"5a7a1070",
+  2768 => x"7d06545b",
+  2769 => x"7282e038",
+  2770 => x"841a5af1",
+  2771 => x"3988178c",
+  2772 => x"11085858",
+  2773 => x"76782e09",
+  2774 => x"8106fcc2",
+  2775 => x"38821a5a",
+  2776 => x"fdec3978",
+  2777 => x"17798107",
+  2778 => x"84190c70",
+  2779 => x"80f9d40c",
+  2780 => x"7080f9d0",
+  2781 => x"0c80f9c8",
+  2782 => x"0b8c120c",
+  2783 => x"8c110888",
+  2784 => x"120c7481",
+  2785 => x"0784120c",
+  2786 => x"74117571",
+  2787 => x"0c51537d",
+  2788 => x"5188d03f",
+  2789 => x"881754fc",
+  2790 => x"ac3980f9",
+  2791 => x"c00b8405",
+  2792 => x"087a545c",
+  2793 => x"798025fe",
+  2794 => x"f83882da",
+  2795 => x"397a097c",
+  2796 => x"067080f9",
+  2797 => x"c00b8405",
+  2798 => x"0c5c7a10",
+  2799 => x"5b7a7c26",
+  2800 => x"85387a85",
+  2801 => x"b83880f9",
+  2802 => x"c00b8805",
+  2803 => x"08708412",
+  2804 => x"08fc0670",
+  2805 => x"7c317c72",
+  2806 => x"268f7225",
+  2807 => x"0757575c",
+  2808 => x"5d557280",
+  2809 => x"2e80db38",
+  2810 => x"797a1680",
+  2811 => x"f9b8081b",
+  2812 => x"90115a55",
+  2813 => x"575b80f9",
+  2814 => x"b408ff2e",
+  2815 => x"8838a08f",
+  2816 => x"13e08006",
+  2817 => x"5776527d",
+  2818 => x"5187d93f",
+  2819 => x"80085480",
+  2820 => x"08ff2e90",
+  2821 => x"38800876",
+  2822 => x"27829938",
+  2823 => x"7480f9c0",
+  2824 => x"2e829138",
+  2825 => x"80f9c00b",
+  2826 => x"88050855",
+  2827 => x"841508fc",
+  2828 => x"06707a31",
+  2829 => x"7a72268f",
+  2830 => x"72250752",
+  2831 => x"55537283",
+  2832 => x"e6387479",
+  2833 => x"81078417",
+  2834 => x"0c791670",
+  2835 => x"80f9c00b",
+  2836 => x"88050c75",
+  2837 => x"81078412",
+  2838 => x"0c547e52",
+  2839 => x"5787843f",
+  2840 => x"881754fa",
+  2841 => x"e0397583",
+  2842 => x"2a705454",
+  2843 => x"80742481",
+  2844 => x"9b387282",
+  2845 => x"2c81712b",
+  2846 => x"80f9c408",
+  2847 => x"077080f9",
+  2848 => x"c00b8405",
+  2849 => x"0c751010",
+  2850 => x"1080f9c0",
+  2851 => x"05881108",
+  2852 => x"585a5d53",
+  2853 => x"778c180c",
+  2854 => x"7488180c",
+  2855 => x"7688190c",
+  2856 => x"768c160c",
+  2857 => x"fcf33979",
+  2858 => x"7a101010",
+  2859 => x"80f9c005",
+  2860 => x"7057595d",
+  2861 => x"8c150857",
+  2862 => x"76752ea3",
+  2863 => x"38841708",
+  2864 => x"fc06707a",
+  2865 => x"31555673",
+  2866 => x"8f2483ca",
+  2867 => x"38738025",
+  2868 => x"8481388c",
+  2869 => x"17085776",
+  2870 => x"752e0981",
+  2871 => x"06df3888",
+  2872 => x"15811b70",
+  2873 => x"8306555b",
+  2874 => x"5572c938",
+  2875 => x"7c830653",
+  2876 => x"72802efd",
+  2877 => x"b838ff1d",
+  2878 => x"f819595d",
+  2879 => x"88180878",
+  2880 => x"2eea38fd",
+  2881 => x"b539831a",
+  2882 => x"53fc9639",
+  2883 => x"83147082",
+  2884 => x"2c81712b",
+  2885 => x"80f9c408",
+  2886 => x"077080f9",
+  2887 => x"c00b8405",
+  2888 => x"0c761010",
+  2889 => x"1080f9c0",
+  2890 => x"05881108",
+  2891 => x"595b5e51",
+  2892 => x"53fee139",
+  2893 => x"80f98408",
+  2894 => x"17588008",
+  2895 => x"762e818d",
+  2896 => x"3880f9b4",
+  2897 => x"08ff2e83",
+  2898 => x"ec387376",
+  2899 => x"311880f9",
+  2900 => x"840c7387",
+  2901 => x"06705753",
+  2902 => x"72802e88",
+  2903 => x"38887331",
+  2904 => x"70155556",
+  2905 => x"76149fff",
+  2906 => x"06a08071",
+  2907 => x"31177054",
+  2908 => x"7f535753",
+  2909 => x"84ee3f80",
+  2910 => x"08538008",
+  2911 => x"ff2e81a0",
+  2912 => x"3880f984",
+  2913 => x"08167080",
+  2914 => x"f9840c74",
+  2915 => x"7580f9c0",
+  2916 => x"0b88050c",
+  2917 => x"74763118",
+  2918 => x"70810751",
+  2919 => x"5556587b",
+  2920 => x"80f9c02e",
+  2921 => x"839c3879",
+  2922 => x"8f2682cb",
+  2923 => x"38810b84",
+  2924 => x"150c8415",
+  2925 => x"08fc0670",
+  2926 => x"7a317a72",
+  2927 => x"268f7225",
+  2928 => x"07525553",
+  2929 => x"72802efc",
+  2930 => x"f93880db",
+  2931 => x"3980089f",
+  2932 => x"ff065372",
+  2933 => x"feeb3877",
+  2934 => x"80f9840c",
+  2935 => x"80f9c00b",
+  2936 => x"8805087b",
+  2937 => x"18810784",
+  2938 => x"120c5580",
+  2939 => x"f9b00878",
+  2940 => x"27863877",
+  2941 => x"80f9b00c",
+  2942 => x"80f9ac08",
+  2943 => x"7827fcac",
+  2944 => x"387780f9",
+  2945 => x"ac0c8415",
+  2946 => x"08fc0670",
+  2947 => x"7a317a72",
+  2948 => x"268f7225",
+  2949 => x"07525553",
+  2950 => x"72802efc",
+  2951 => x"a5388839",
+  2952 => x"80745456",
+  2953 => x"fedb397d",
+  2954 => x"5183b83f",
+  2955 => x"800b800c",
+  2956 => x"8f3d0d04",
+  2957 => x"73538074",
+  2958 => x"24a93872",
+  2959 => x"822c8171",
+  2960 => x"2b80f9c4",
+  2961 => x"08077080",
+  2962 => x"f9c00b84",
+  2963 => x"050c5d53",
+  2964 => x"778c180c",
+  2965 => x"7488180c",
+  2966 => x"7688190c",
+  2967 => x"768c160c",
+  2968 => x"f9b73983",
+  2969 => x"1470822c",
+  2970 => x"81712b80",
+  2971 => x"f9c40807",
+  2972 => x"7080f9c0",
+  2973 => x"0b84050c",
+  2974 => x"5e5153d4",
+  2975 => x"397b7b06",
+  2976 => x"5372fca3",
+  2977 => x"38841a7b",
+  2978 => x"105c5af1",
+  2979 => x"39ff1a81",
+  2980 => x"11515af7",
+  2981 => x"b9397817",
+  2982 => x"79810784",
+  2983 => x"190c8c18",
+  2984 => x"08881908",
+  2985 => x"718c120c",
+  2986 => x"88120c59",
+  2987 => x"7080f9d4",
+  2988 => x"0c7080f9",
+  2989 => x"d00c80f9",
+  2990 => x"c80b8c12",
+  2991 => x"0c8c1108",
+  2992 => x"88120c74",
+  2993 => x"81078412",
+  2994 => x"0c741175",
+  2995 => x"710c5153",
+  2996 => x"f9bd3975",
+  2997 => x"17841108",
+  2998 => x"81078412",
+  2999 => x"0c538c17",
+  3000 => x"08881808",
+  3001 => x"718c120c",
+  3002 => x"88120c58",
+  3003 => x"7d5181f3",
+  3004 => x"3f881754",
+  3005 => x"f5cf3972",
+  3006 => x"84150cf4",
+  3007 => x"1af80670",
+  3008 => x"841e0881",
+  3009 => x"0607841e",
+  3010 => x"0c701d54",
+  3011 => x"5b850b84",
+  3012 => x"140c850b",
+  3013 => x"88140c8f",
+  3014 => x"7b27fdcf",
+  3015 => x"38881c52",
+  3016 => x"7d5184bf",
+  3017 => x"3f80f9c0",
+  3018 => x"0b880508",
+  3019 => x"80f98408",
+  3020 => x"5955fdb7",
+  3021 => x"397780f9",
+  3022 => x"840c7380",
+  3023 => x"f9b40cfc",
+  3024 => x"91397284",
+  3025 => x"150cfda3",
+  3026 => x"39fc3d0d",
+  3027 => x"7670797b",
+  3028 => x"55555555",
+  3029 => x"8f72278c",
+  3030 => x"38727507",
+  3031 => x"83065170",
+  3032 => x"802ea738",
+  3033 => x"ff125271",
+  3034 => x"ff2e9838",
+  3035 => x"72708105",
+  3036 => x"54337470",
+  3037 => x"81055634",
+  3038 => x"ff125271",
+  3039 => x"ff2e0981",
+  3040 => x"06ea3874",
+  3041 => x"800c863d",
+  3042 => x"0d047451",
+  3043 => x"72708405",
+  3044 => x"54087170",
+  3045 => x"8405530c",
+  3046 => x"72708405",
+  3047 => x"54087170",
+  3048 => x"8405530c",
+  3049 => x"72708405",
+  3050 => x"54087170",
+  3051 => x"8405530c",
+  3052 => x"72708405",
+  3053 => x"54087170",
+  3054 => x"8405530c",
+  3055 => x"f0125271",
+  3056 => x"8f26c938",
+  3057 => x"83722795",
+  3058 => x"38727084",
+  3059 => x"05540871",
+  3060 => x"70840553",
+  3061 => x"0cfc1252",
+  3062 => x"718326ed",
+  3063 => x"387054ff",
+  3064 => x"83390404",
+  3065 => x"fd3d0d80",
+  3066 => x"0b81d998",
+  3067 => x"0c765187",
+  3068 => x"c83f8008",
+  3069 => x"538008ff",
+  3070 => x"2e883872",
+  3071 => x"800c853d",
+  3072 => x"0d0481d9",
+  3073 => x"98085473",
+  3074 => x"802ef038",
+  3075 => x"7574710c",
+  3076 => x"5272800c",
+  3077 => x"853d0d04",
+  3078 => x"fb3d0d77",
+  3079 => x"79707207",
+  3080 => x"83065354",
+  3081 => x"52709338",
+  3082 => x"71737308",
+  3083 => x"54565471",
+  3084 => x"73082e80",
+  3085 => x"c4387375",
+  3086 => x"54527133",
+  3087 => x"7081ff06",
+  3088 => x"52547080",
+  3089 => x"2e9d3872",
+  3090 => x"33557075",
+  3091 => x"2e098106",
+  3092 => x"95388112",
+  3093 => x"81147133",
+  3094 => x"7081ff06",
+  3095 => x"54565452",
+  3096 => x"70e53872",
+  3097 => x"33557381",
+  3098 => x"ff067581",
+  3099 => x"ff067171",
+  3100 => x"31800c52",
+  3101 => x"52873d0d",
+  3102 => x"04710970",
+  3103 => x"f7fbfdff",
+  3104 => x"140670f8",
+  3105 => x"84828180",
+  3106 => x"06515151",
+  3107 => x"70973884",
+  3108 => x"14841671",
+  3109 => x"08545654",
+  3110 => x"7175082e",
+  3111 => x"dc387375",
+  3112 => x"5452ff96",
+  3113 => x"39800b80",
+  3114 => x"0c873d0d",
+  3115 => x"04fb3d0d",
+  3116 => x"77705256",
+  3117 => x"feac3f80",
+  3118 => x"f9c00b88",
+  3119 => x"05088411",
+  3120 => x"08fc0670",
+  3121 => x"7b319fef",
+  3122 => x"05e08006",
+  3123 => x"e0800556",
+  3124 => x"5653a080",
+  3125 => x"74249438",
+  3126 => x"80527551",
+  3127 => x"fe863f80",
+  3128 => x"f9c80815",
+  3129 => x"53728008",
+  3130 => x"2e8f3875",
+  3131 => x"51fdf43f",
+  3132 => x"80537280",
+  3133 => x"0c873d0d",
+  3134 => x"04733052",
+  3135 => x"7551fde4",
+  3136 => x"3f8008ff",
+  3137 => x"2ea83880",
+  3138 => x"f9c00b88",
+  3139 => x"05087575",
+  3140 => x"31810784",
+  3141 => x"120c5380",
+  3142 => x"f9840874",
+  3143 => x"3180f984",
+  3144 => x"0c7551fd",
+  3145 => x"be3f810b",
+  3146 => x"800c873d",
+  3147 => x"0d048052",
+  3148 => x"7551fdb0",
+  3149 => x"3f80f9c0",
+  3150 => x"0b880508",
+  3151 => x"80087131",
+  3152 => x"56538f75",
+  3153 => x"25ffa438",
+  3154 => x"800880f9",
+  3155 => x"b4083180",
+  3156 => x"f9840c74",
+  3157 => x"81078414",
+  3158 => x"0c7551fd",
+  3159 => x"863f8053",
+  3160 => x"ff9039f6",
+  3161 => x"3d0d7c7e",
+  3162 => x"545b7280",
+  3163 => x"2e828338",
+  3164 => x"7a51fcee",
+  3165 => x"3ff81384",
+  3166 => x"110870fe",
+  3167 => x"06701384",
+  3168 => x"1108fc06",
+  3169 => x"5d585954",
+  3170 => x"5880f9c8",
+  3171 => x"08752e82",
+  3172 => x"de387884",
+  3173 => x"160c8073",
+  3174 => x"8106545a",
+  3175 => x"727a2e81",
+  3176 => x"d5387815",
+  3177 => x"84110881",
+  3178 => x"06515372",
+  3179 => x"a0387817",
+  3180 => x"577981e6",
+  3181 => x"38881508",
+  3182 => x"537280f9",
+  3183 => x"c82e82f9",
+  3184 => x"388c1508",
+  3185 => x"708c150c",
+  3186 => x"7388120c",
+  3187 => x"56768107",
+  3188 => x"84190c76",
+  3189 => x"1877710c",
+  3190 => x"53798191",
+  3191 => x"3883ff77",
+  3192 => x"2781c838",
+  3193 => x"76892a77",
+  3194 => x"832a5653",
+  3195 => x"72802ebf",
+  3196 => x"3876862a",
+  3197 => x"b8055584",
+  3198 => x"7327b438",
+  3199 => x"80db1355",
+  3200 => x"947327ab",
+  3201 => x"38768c2a",
+  3202 => x"80ee0555",
+  3203 => x"80d47327",
+  3204 => x"9e38768f",
+  3205 => x"2a80f705",
+  3206 => x"5582d473",
+  3207 => x"27913876",
+  3208 => x"922a80fc",
+  3209 => x"05558ad4",
+  3210 => x"73278438",
+  3211 => x"80fe5574",
+  3212 => x"10101080",
+  3213 => x"f9c00588",
+  3214 => x"11085556",
+  3215 => x"73762e82",
+  3216 => x"b3388414",
+  3217 => x"08fc0653",
+  3218 => x"7673278d",
+  3219 => x"38881408",
+  3220 => x"5473762e",
+  3221 => x"098106ea",
+  3222 => x"388c1408",
+  3223 => x"708c1a0c",
+  3224 => x"74881a0c",
+  3225 => x"7888120c",
+  3226 => x"56778c15",
+  3227 => x"0c7a51fa",
+  3228 => x"f23f8c3d",
+  3229 => x"0d047708",
+  3230 => x"78713159",
+  3231 => x"77058819",
+  3232 => x"08545772",
+  3233 => x"80f9c82e",
+  3234 => x"80e0388c",
+  3235 => x"1808708c",
+  3236 => x"150c7388",
+  3237 => x"120c56fe",
+  3238 => x"89398815",
+  3239 => x"088c1608",
+  3240 => x"708c130c",
+  3241 => x"5788170c",
+  3242 => x"fea33976",
+  3243 => x"832a7054",
+  3244 => x"55807524",
+  3245 => x"81983872",
+  3246 => x"822c8171",
+  3247 => x"2b80f9c4",
+  3248 => x"080780f9",
+  3249 => x"c00b8405",
+  3250 => x"0c537410",
+  3251 => x"101080f9",
+  3252 => x"c0058811",
+  3253 => x"08555675",
+  3254 => x"8c190c73",
+  3255 => x"88190c77",
+  3256 => x"88170c77",
+  3257 => x"8c150cff",
+  3258 => x"8439815a",
+  3259 => x"fdb43978",
+  3260 => x"17738106",
+  3261 => x"54577298",
+  3262 => x"38770878",
+  3263 => x"71315977",
+  3264 => x"058c1908",
+  3265 => x"881a0871",
+  3266 => x"8c120c88",
+  3267 => x"120c5757",
+  3268 => x"76810784",
+  3269 => x"190c7780",
+  3270 => x"f9c00b88",
+  3271 => x"050c80f9",
+  3272 => x"bc087726",
+  3273 => x"fec73880",
+  3274 => x"f9b80852",
+  3275 => x"7a51fafd",
+  3276 => x"3f7a51f9",
+  3277 => x"ae3ffeba",
+  3278 => x"3981788c",
+  3279 => x"150c7888",
+  3280 => x"150c738c",
+  3281 => x"1a0c7388",
+  3282 => x"1a0c5afd",
+  3283 => x"80398315",
+  3284 => x"70822c81",
+  3285 => x"712b80f9",
+  3286 => x"c4080780",
+  3287 => x"f9c00b84",
+  3288 => x"050c5153",
+  3289 => x"74101010",
+  3290 => x"80f9c005",
+  3291 => x"88110855",
+  3292 => x"56fee439",
+  3293 => x"74538075",
+  3294 => x"24a73872",
+  3295 => x"822c8171",
+  3296 => x"2b80f9c4",
+  3297 => x"080780f9",
+  3298 => x"c00b8405",
+  3299 => x"0c53758c",
+  3300 => x"190c7388",
+  3301 => x"190c7788",
+  3302 => x"170c778c",
+  3303 => x"150cfdcd",
+  3304 => x"39831570",
+  3305 => x"822c8171",
+  3306 => x"2b80f9c4",
+  3307 => x"080780f9",
+  3308 => x"c00b8405",
+  3309 => x"0c5153d6",
+  3310 => x"39fe3d0d",
+  3311 => x"8188f008",
+  3312 => x"51708a38",
+  3313 => x"81d99c70",
+  3314 => x"8188f00c",
+  3315 => x"51707512",
+  3316 => x"5252ff53",
+  3317 => x"7087fb80",
+  3318 => x"80268838",
+  3319 => x"708188f0",
+  3320 => x"0c715372",
+  3321 => x"800c843d",
+  3322 => x"0d04fd3d",
+  3323 => x"0d800b80",
+  3324 => x"f8ec0854",
+  3325 => x"5472812e",
+  3326 => x"9e387381",
+  3327 => x"88f40cff",
+  3328 => x"a0ff3fff",
+  3329 => x"9ffa3f81",
+  3330 => x"88c85281",
+  3331 => x"51ffa9ae",
+  3332 => x"3f800851",
+  3333 => x"80e13f72",
+  3334 => x"8188f40c",
+  3335 => x"ffa0e23f",
+  3336 => x"ff9fdd3f",
+  3337 => x"8188c852",
+  3338 => x"8151ffa9",
+  3339 => x"913f8008",
+  3340 => x"5180c43f",
+  3341 => x"00ff3900",
+  3342 => x"ff39f43d",
+  3343 => x"0d7e8188",
+  3344 => x"e8087008",
+  3345 => x"7081ff06",
+  3346 => x"923df805",
+  3347 => x"55515a57",
+  3348 => x"59ffa19a",
+  3349 => x"3f805477",
+  3350 => x"557b7d58",
+  3351 => x"5276538e",
+  3352 => x"3df00551",
+  3353 => x"c0c03f79",
+  3354 => x"7b58790c",
+  3355 => x"76841a0c",
+  3356 => x"78800c8e",
+  3357 => x"3d0d04f7",
+  3358 => x"3d0d7b81",
+  3359 => x"81c80882",
+  3360 => x"c811085a",
+  3361 => x"545a7780",
+  3362 => x"2e80da38",
+  3363 => x"81881884",
+  3364 => x"1908ff05",
+  3365 => x"81712b59",
+  3366 => x"55598074",
+  3367 => x"2480ea38",
+  3368 => x"807424b5",
+  3369 => x"3873822b",
+  3370 => x"78118805",
+  3371 => x"56568180",
+  3372 => x"19087706",
+  3373 => x"5372802e",
+  3374 => x"b6387816",
+  3375 => x"70085353",
+  3376 => x"79517408",
+  3377 => x"53722dff",
+  3378 => x"14fc17fc",
+  3379 => x"1779812c",
+  3380 => x"5a575754",
+  3381 => x"738025d6",
+  3382 => x"38770858",
+  3383 => x"77ffad38",
+  3384 => x"8181c808",
+  3385 => x"53bc1308",
+  3386 => x"a5387951",
+  3387 => x"fec63f74",
+  3388 => x"0853722d",
+  3389 => x"ff14fc17",
+  3390 => x"fc177981",
+  3391 => x"2c5a5757",
+  3392 => x"54738025",
+  3393 => x"ffa838d1",
+  3394 => x"398057ff",
+  3395 => x"93397251",
+  3396 => x"bc130853",
+  3397 => x"722d7951",
+  3398 => x"fe9a3fff",
+  3399 => x"3d0d8188",
+  3400 => x"d00bfc05",
+  3401 => x"70085252",
+  3402 => x"70ff2e91",
+  3403 => x"38702dfc",
+  3404 => x"12700852",
+  3405 => x"5270ff2e",
+  3406 => x"098106f1",
+  3407 => x"38833d0d",
+  3408 => x"0404ffa0",
+  3409 => x"873f0400",
+  3410 => x"00000040",
+  3411 => x"30313233",
+  3412 => x"34353637",
+  3413 => x"38390000",
+  3414 => x"44485259",
+  3415 => x"53544f4e",
+  3416 => x"45205052",
+  3417 => x"4f475241",
+  3418 => x"4d2c2053",
+  3419 => x"4f4d4520",
+  3420 => x"53545249",
+  3421 => x"4e470000",
+  3422 => x"44485259",
+  3423 => x"53544f4e",
+  3424 => x"45205052",
+  3425 => x"4f475241",
+  3426 => x"4d2c2031",
+  3427 => x"27535420",
+  3428 => x"53545249",
+  3429 => x"4e470000",
+  3430 => x"44687279",
+  3431 => x"73746f6e",
+  3432 => x"65204265",
+  3433 => x"6e63686d",
+  3434 => x"61726b2c",
+  3435 => x"20566572",
+  3436 => x"73696f6e",
+  3437 => x"20322e31",
+  3438 => x"20284c61",
+  3439 => x"6e677561",
+  3440 => x"67653a20",
+  3441 => x"43290a00",
+  3442 => x"50726f67",
+  3443 => x"72616d20",
+  3444 => x"636f6d70",
+  3445 => x"696c6564",
+  3446 => x"20776974",
+  3447 => x"68202772",
+  3448 => x"65676973",
+  3449 => x"74657227",
+  3450 => x"20617474",
+  3451