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| author | Bert Lange <b.lange@hzdr.de> | 2011-10-15 08:50:18 +0200 |
|---|---|---|
| committer | Bert Lange <b.lange@hzdr.de> | 2011-10-15 08:50:18 +0200 |
| commit | 66a60bf34fd1960bb3c8f87a784dd2e6d27e2213 (patch) | |
| tree | 2fb33ba6896bcb022c687dab00bdf1f87e111247 /zpu/hdl/zealot | |
| parent | 0bf783475d6610a14f71884737aeae33246bb9be (diff) | |
| download | zpu-66a60bf34fd1960bb3c8f87a784dd2e6d27e2213.zip zpu-66a60bf34fd1960bb3c8f87a784dd2e6d27e2213.tar.gz | |
minor fix: to satisfy some synthesis tools
Diffstat (limited to 'zpu/hdl/zealot')
| -rw-r--r-- | zpu/hdl/zealot/devices/phi_io.vhdl | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/zpu/hdl/zealot/devices/phi_io.vhdl b/zpu/hdl/zealot/devices/phi_io.vhdl index b70ccd7..99e0f8f 100644 --- a/zpu/hdl/zealot/devices/phi_io.vhdl +++ b/zpu/hdl/zealot/devices/phi_io.vhdl @@ -158,8 +158,10 @@ begin do_io: process(clk_i) + --synopsys translate off variable line_out : line := new string'(""); variable char : character; + --synopsys translate on begin if rising_edge(clk_i) then if reset_i/='1' then |
