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| author | Bert Lange <b.lange@hzdr.de> | 2015-04-15 13:36:55 +0200 |
|---|---|---|
| committer | Bert Lange <b.lange@hzdr.de> | 2015-04-15 13:36:55 +0200 |
| commit | a1c964908b51599bf624bd2d253419c7e629f195 (patch) | |
| tree | 06125d59e83b7dde82d1bb57bc0e09ca83451b98 /zpu/hdl/zealot/fpga | |
| parent | bbfe29a15f11548eb7c9fa71dcb4d2d18c164a53 (diff) | |
| parent | 8679e4f91dcae05aef40f96629f33f0f4161f14a (diff) | |
| download | zpu-a1c964908b51599bf624bd2d253419c7e629f195.zip zpu-a1c964908b51599bf624bd2d253419c7e629f195.tar.gz | |
Merge branch 'master' of https://github.com/zylin/zpu
Diffstat (limited to 'zpu/hdl/zealot/fpga')
48 files changed, 6104 insertions, 0 deletions
diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/clean_up.sh b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/clean_up.sh new file mode 100755 index 0000000..3855f16 --- /dev/null +++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/clean_up.sh @@ -0,0 +1,16 @@ +#!/bin/sh + +# ise build stuff +rm -rf build +rm -f top.bit + +# modelsim compile stuff +rm -rf work +rm -rf zpu + +# modelsim simulation stuff +rm -f vsim.wlf +rm -f transcript +rm -f zpu_trace.log +rm -f zpu_med1_io.log +rm -f zpu_small1_io.log diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation.sh b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation.sh new file mode 100755 index 0000000..d525737 --- /dev/null +++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation.sh @@ -0,0 +1,49 @@ +#!/bin/sh + +# need project files: +# run.do +# wave.do + +# need ModelSim tools: +# vlib +# vcom +# vsim + + +echo "###############" +echo "compile zpu lib" +echo "###############" +vlib zpu +vcom -work zpu ../../roms/hello_dbram.vhdl +vcom -work zpu ../../roms/hello_bram.vhdl +#vcom -work zpu ../../roms/dmips_dbram.vhdl +#vcom -work zpu ../../roms/dmips_bram.vhdl + +vcom -work zpu ../../roms/rom_pkg.vhdl +vcom -work zpu ../../zpu_pkg.vhdl +vcom -work zpu ../../zpu_small.vhdl +vcom -work zpu ../../zpu_medium.vhdl +vcom -work zpu ../../helpers/zpu_small1.vhdl +vcom -work zpu ../../helpers/zpu_med1.vhdl +vcom -work zpu ../../devices/txt_util.vhdl +vcom -work zpu ../../devices/phi_io.vhdl +vcom -work zpu ../../devices/timer.vhdl +vcom -work zpu ../../devices/gpio.vhdl +vcom -work zpu ../../devices/rx_unit.vhdl +vcom -work zpu ../../devices/tx_unit.vhdl +vcom -work zpu ../../devices/br_gen.vhdl +vcom -work zpu ../../devices/trace.vhdl + + +echo "################" +echo "compile work lib" +echo "################" +vlib work +vcom top.vhd +vcom top_tb.vhd + + +echo "###################" +echo "start simulator gui" +echo "###################" +vsim -gui top_tb -do simulation_config/run.do diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/run.do b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/run.do new file mode 100644 index 0000000..acc1710 --- /dev/null +++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/run.do @@ -0,0 +1,2 @@ +do wave.do +run -all diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/wave.do b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/wave.do new file mode 100644 index 0000000..3f5d4fe --- /dev/null +++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/simulation_config/wave.do @@ -0,0 +1,30 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /top_tb/tb_reset_n +add wave -noupdate /top_tb/tb_clk +add wave -noupdate -divider <NULL> +add wave -noupdate /top_tb/tb_rs232_rx +add wave -noupdate /top_tb/tb_rs232_tx +add wave -noupdate /top_tb/tb_rs232_rts +add wave -noupdate /top_tb/tb_rs232_cts +add wave -noupdate -divider Buttons +add wave -noupdate /top_tb/tb_button_n +add wave -noupdate -divider LEDs +add wave -noupdate /top_tb/tb_led +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 ps} 0} +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 2 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {1294218073 ps} {1421130628 ps} diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis.sh b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis.sh new file mode 100755 index 0000000..a7180fc --- /dev/null +++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis.sh @@ -0,0 +1,36 @@ +#!/bin/sh + +# need project files: +# top.xst +# top.prj +# top.ut + +# need Xilinx tools: +# xst +# ngdbuild +# map +# par +# trce +# bitgen + +echo "########################" +echo "generate build directory" +echo "########################" +mkdir build +cd build +mkdir tmp + +echo "###############" +echo "start processes" +echo "###############" +xst -ifn "../synthesis_config/top.xst" -ofn "top.syr" +ngdbuild -dd _ngo -nt timestamp -uc ../synthesis_config/altium-livedesign-xc3s1000.ucf -p xc3s1000-fg456-4 top.ngc top.ngd +map -p xc3s1000-fg456-4 -cm area -ir off -pr off -c 100 -o top_map.ncd top.ngd top.pcf +par -w -ol high -t 1 top_map.ncd top.ncd top.pcf +trce -v 3 -s 4 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf +bitgen -f ../synthesis_config/top.ut top.ncd + +echo "###########" +echo "get bitfile" +echo "###########" +cp top.bit .. diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/altium-livedesign-xc3s1000.ucf b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/altium-livedesign-xc3s1000.ucf new file mode 100644 index 0000000..ba22ee9 --- /dev/null +++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/altium-livedesign-xc3s1000.ucf @@ -0,0 +1,397 @@ +############################################################ +# Altium Livedesign Evaluation Board constraints file +# +# Familiy: Spartan-3 +# Device: XC3S1000 +# Package: FG456C +# Speed: -4 +# +# all banks are powered with 3.3V +# +# config pins (M2, M1, M0): 101 + +############################################################ +## clock/timing constraints +############################################################ + +NET "clk_50" period = 50 MHz ; + + +############################################################ +## pin placement constraints +############################################################ + +NET "clk_50" LOC = AA12 | IOSTANDARD = LVCMOS33; +NET "reset_n" LOC = Y17 | IOSTANDARD = LVCMOS33; # low active + +# Soft JTAG +NET "soft_tdo" LOC = D22 | IOSTANDARD = LVCMOS33; +NET "soft_tms" LOC = E21 | IOSTANDARD = LVCMOS33; +NET "soft_tdi" LOC = E22 | IOSTANDARD = LVCMOS33; +NET "soft_tck" LOC = F21 | IOSTANDARD = LVCMOS33; + +# SRAM 0 +NET "sram0_a<0>" LOC = L6 | IOSTANDARD = LVCMOS33; +NET "sram0_a<1>" LOC = K4 | IOSTANDARD = LVCMOS33; +NET "sram0_a<2>" LOC = H5 | IOSTANDARD = LVCMOS33; +NET "sram0_a<3>" LOC = G6 | IOSTANDARD = LVCMOS33; +NET "sram0_a<4>" LOC = F3 | IOSTANDARD = LVCMOS33; +NET "sram0_a<5>" LOC = G1 | IOSTANDARD = LVCMOS33; +NET "sram0_a<6>" LOC = G2 | IOSTANDARD = LVCMOS33; +NET "sram0_a<7>" LOC = K3 | IOSTANDARD = LVCMOS33; +NET "sram0_a<8>" LOC = T2 | IOSTANDARD = LVCMOS33; +NET "sram0_a<9>" LOC = T1 | IOSTANDARD = LVCMOS33; +NET "sram0_a<10>" LOC = U2 | IOSTANDARD = LVCMOS33; +NET "sram0_a<11>" LOC = V3 | IOSTANDARD = LVCMOS33; +NET "sram0_a<12>" LOC = V1 | IOSTANDARD = LVCMOS33; +NET "sram0_a<13>" LOC = W1 | IOSTANDARD = LVCMOS33; +NET "sram0_a<14>" LOC = V2 | IOSTANDARD = LVCMOS33; +NET "sram0_a<15>" LOC = V5 | IOSTANDARD = LVCMOS33; +NET "sram0_a<16>" LOC = V4 | IOSTANDARD = LVCMOS33; +NET "sram0_a<17>" LOC = U5 | IOSTANDARD = LVCMOS33; +NET "sram0_a<18>" LOC = U6 | IOSTANDARD = LVCMOS33; # n.c. +NET "sram0_d<0>" LOC = L4 | IOSTANDARD = LVCMOS33; +NET "sram0_d<1>" LOC = L3 | IOSTANDARD = LVCMOS33; +NET "sram0_d<2>" LOC = M5 | IOSTANDARD = LVCMOS33; +NET "sram0_d<3>" LOC = M4 | IOSTANDARD = LVCMOS33; +NET "sram0_d<4>" LOC = M3 | IOSTANDARD = LVCMOS33; +NET "sram0_d<5>" LOC = N4 | IOSTANDARD = LVCMOS33; +NET "sram0_d<6>" LOC = N3 | IOSTANDARD = LVCMOS33; +NET "sram0_d<7>" LOC = T5 | IOSTANDARD = LVCMOS33; +NET "sram0_d<8>" LOC = T4 | IOSTANDARD = LVCMOS33; +NET "sram0_d<9>" LOC = T6 | IOSTANDARD = LVCMOS33; +NET "sram0_d<10>" LOC = M6 | IOSTANDARD = LVCMOS33; +NET "sram0_d<11>" LOC = N2 | IOSTANDARD = LVCMOS33; +NET "sram0_d<12>" LOC = N1 | IOSTANDARD = LVCMOS33; +NET "sram0_d<13>" LOC = M2 | IOSTANDARD = LVCMOS33; +NET "sram0_d<14>" LOC = M1 | IOSTANDARD = LVCMOS33; +NET "sram0_d<15>" LOC = L2 | IOSTANDARD = LVCMOS33; +NET "sram0_cs_n" LOC = L5 | IOSTANDARD = LVCMOS33; +NET "sram0_lb_n" LOC = L1 | IOSTANDARD = LVCMOS33; +NET "sram0_ub_n" LOC = K2 | IOSTANDARD = LVCMOS33; +NET "sram0_we_n" LOC = U4 | IOSTANDARD = LVCMOS33; +NET "sram0_oe_n" LOC = K1 | IOSTANDARD = LVCMOS33; + +# SRAM 1 +NET "sram1_a<0>" LOC = K21 | IOSTANDARD = LVCMOS33; +NET "sram1_a<1>" LOC = K22 | IOSTANDARD = LVCMOS33; +NET "sram1_a<2>" LOC = K20 | IOSTANDARD = LVCMOS33; +NET "sram1_a<3>" LOC = G21 | IOSTANDARD = LVCMOS33; +NET "sram1_a<4>" LOC = G22 | IOSTANDARD = LVCMOS33; +NET "sram1_a<5>" LOC = M17 | IOSTANDARD = LVCMOS33; +NET "sram1_a<6>" LOC = L18 | IOSTANDARD = LVCMOS33; +NET "sram1_a<7>" LOC = K19 | IOSTANDARD = LVCMOS33; +NET "sram1_a<8>" LOC = V19 | IOSTANDARD = LVCMOS33; +NET "sram1_a<9>" LOC = W20 | IOSTANDARD = LVCMOS33; +NET "sram1_a<10>" LOC = W19 | IOSTANDARD = LVCMOS33; +NET "sram1_a<11>" LOC = Y20 | IOSTANDARD = LVCMOS33; +NET "sram1_a<12>" LOC = Y21 | IOSTANDARD = LVCMOS33; +NET "sram1_a<13>" LOC = Y22 | IOSTANDARD = LVCMOS33; +NET "sram1_a<14>" LOC = W21 | IOSTANDARD = LVCMOS33; +NET "sram1_a<15>" LOC = W22 | IOSTANDARD = LVCMOS33; +NET "sram1_a<16>" LOC = V21 | IOSTANDARD = LVCMOS33; +NET "sram1_a<17>" LOC = V22 | IOSTANDARD = LVCMOS33; +NET "sram1_a<18>" LOC = V20 | IOSTANDARD = LVCMOS33; # n.c. +NET "sram1_d<0>" LOC = L21 | IOSTANDARD = LVCMOS33; +NET "sram1_d<1>" LOC = M22 | IOSTANDARD = LVCMOS33; +NET "sram1_d<2>" LOC = M21 | IOSTANDARD = LVCMOS33; +NET "sram1_d<3>" LOC = N22 | IOSTANDARD = LVCMOS33; +NET "sram1_d<4>" LOC = N21 | IOSTANDARD = LVCMOS33; +NET "sram1_d<5>" LOC = U20 | IOSTANDARD = LVCMOS33; +NET "sram1_d<6>" LOC = T22 | IOSTANDARD = LVCMOS33; +NET "sram1_d<7>" LOC = T21 | IOSTANDARD = LVCMOS33; +NET "sram1_d<8>" LOC = V18 | IOSTANDARD = LVCMOS33; +NET "sram1_d<9>" LOC = U19 | IOSTANDARD = LVCMOS33; +NET "sram1_d<10>" LOC = U18 | IOSTANDARD = LVCMOS33; +NET "sram1_d<11>" LOC = T18 | IOSTANDARD = LVCMOS33; +NET "sram1_d<12>" LOC = R18 | IOSTANDARD = LVCMOS33; +NET "sram1_d<13>" LOC = T17 | IOSTANDARD = LVCMOS33; +NET "sram1_d<14>" LOC = M18 | IOSTANDARD = LVCMOS33; +NET "sram1_d<15>" LOC = M20 | IOSTANDARD = LVCMOS33; +NET "sram1_cs_n" LOC = L22 | IOSTANDARD = LVCMOS33; +NET "sram1_lb_n" LOC = M19 | IOSTANDARD = LVCMOS33; +NET "sram1_ub_n" LOC = L20 | IOSTANDARD = LVCMOS33; +NET "sram1_we_n" LOC = U21 | IOSTANDARD = LVCMOS33; +NET "sram1_oe_n" LOC = L19 | IOSTANDARD = LVCMOS33; + +# RS232 +NET "rs232_rx" LOC = A5 | IOSTANDARD = LVCMOS33; +NET "rs232_tx" LOC = F7 | IOSTANDARD = LVCMOS33; +NET "rs232_cts" LOC = F2 | IOSTANDARD = LVCMOS33; +NET "rs232_rts" LOC = E1 | IOSTANDARD = LVCMOS33; + +# 2x PS2 connectors +NET "mouse_clk" LOC = L17 | IOSTANDARD = LVCMOS33; +NET "mouse_data" LOC = G18 | IOSTANDARD = LVCMOS33; +NET "kbd_clk" LOC = F20 | IOSTANDARD = LVCMOS33; +NET "kbd_data" LOC = G19 | IOSTANDARD = LVCMOS33; + + +# VGA output (2**9 = 512 colors) +NET "vga_blue<7>" LOC = E14 | IOSTANDARD = LVCMOS33; +NET "vga_blue<6>" LOC = A13 | IOSTANDARD = LVCMOS33; +NET "vga_blue<5>" LOC = C13 | IOSTANDARD = LVCMOS33; +NET "vga_green<7>" LOC = E11 | IOSTANDARD = LVCMOS33; +NET "vga_green<6>" LOC = C11 | IOSTANDARD = LVCMOS33; +NET "vga_green<5>" LOC = D10 | IOSTANDARD = LVCMOS33; +NET "vga_red<7>" LOC = D6 | IOSTANDARD = LVCMOS33; +NET "vga_red<6>" LOC = D7 | IOSTANDARD = LVCMOS33; +NET "vga_red<5>" LOC = D9 | IOSTANDARD = LVCMOS33; +NET "vga_hsync" LOC = A8 | IOSTANDARD = LVCMOS33; +NET "vga_vsync" LOC = B14 | IOSTANDARD = LVCMOS33; + + +# Stereo Audio out +NET "audio_r" LOC = U3 | IOSTANDARD = LVCMOS33; +NET "audio_l" LOC = W3 | IOSTANDARD = LVCMOS33; + + +# GPIO DIP switches 7..0 left..right, low active +NET "switch_n<0>" LOC = Y6 | IOSTANDARD = LVCMOS33; +NET "switch_n<1>" LOC = V6 | IOSTANDARD = LVCMOS33; +NET "switch_n<2>" LOC = U7 | IOSTANDARD = LVCMOS33; +NET "switch_n<3>" LOC = AA4 | IOSTANDARD = LVCMOS33; +NET "switch_n<4>" LOC = AB4 | IOSTANDARD = LVCMOS33; +NET "switch_n<5>" LOC = AA5 | IOSTANDARD = LVCMOS33; +NET "switch_n<6>" LOC = AB5 | IOSTANDARD = LVCMOS33; +NET "switch_n<7>" LOC = AA6 | IOSTANDARD = LVCMOS33; + +# GPIO push buttons, low active +NET "button_n<5>" LOC = C21 | IOSTANDARD = LVCMOS33; +NET "button_n<4>" LOC = B20 | IOSTANDARD = LVCMOS33; +NET "button_n<3>" LOC = A15 | IOSTANDARD = LVCMOS33; +NET "button_n<2>" LOC = B6 | IOSTANDARD = LVCMOS33; +NET "button_n<1>" LOC = C1 | IOSTANDARD = LVCMOS33; +NET "button_n<0>" LOC = D1 | IOSTANDARD = LVCMOS33; + +# GPIO LEDs +NET "led<7>" LOC = W6 | IOSTANDARD = LVCMOS33; +NET "led<6>" LOC = Y5 | IOSTANDARD = LVCMOS33; +NET "led<5>" LOC = W5 | IOSTANDARD = LVCMOS33; +NET "led<4>" LOC = W4 | IOSTANDARD = LVCMOS33; +NET "led<3>" LOC = Y3 | IOSTANDARD = LVCMOS33; +NET "led<2>" LOC = Y2 | IOSTANDARD = LVCMOS33; +NET "led<1>" LOC = Y1 | IOSTANDARD = LVCMOS33; +NET "led<0>" LOC = W2 | IOSTANDARD = LVCMOS33; + +# seven segment display (5=left 0=right) +# +# segment assignment: +# .ABCDEFG +# 76543210 +NET "dig0_seg<7>" LOC = E20 | IOSTANDARD = LVCMOS33; +NET "dig0_seg<6>" LOC = C22 | IOSTANDARD = LVCMOS33; +NET "dig0_seg<5>" LOC = E18 | IOSTANDARD = LVCMOS33; +NET "dig0_seg<4>" LOC = D20 | IOSTANDARD = LVCMOS33; +NET "dig0_seg<3>" LOC = D21 | IOSTANDARD = LVCMOS33; +NET "dig0_seg<2>" LOC = E19 | IOSTANDARD = LVCMOS33; +NET "dig0_seg<1>" LOC = G17 | IOSTANDARD = LVCMOS33; +NET "dig0_seg<0>" LOC = F19 | IOSTANDARD = LVCMOS33; + +NET "dig1_seg<7>" LOC = F17 | IOSTANDARD = LVCMOS33; +NET "dig1_seg<6>" LOC = D18 | IOSTANDARD = LVCMOS33; +NET "dig1_seg<5>" LOC = B19 | IOSTANDARD = LVCMOS33; +NET "dig1_seg<4>" LOC = C18 | IOSTANDARD = LVCMOS33; +NET "dig1_seg<3>" LOC = C19 | IOSTANDARD = LVCMOS33; +NET "dig1_seg<2>" LOC = C20 | IOSTANDARD = LVCMOS33; +NET "dig1_seg<1>" LOC = F18 | IOSTANDARD = LVCMOS33; +NET "dig1_seg<0>" LOC = D19 | IOSTANDARD = LVCMOS33; + +NET "dig2_seg<7>" LOC = A19 | IOSTANDARD = LVCMOS33; +NET "dig2_seg<6>" LOC = E17 | IOSTANDARD = LVCMOS33; +NET "dig2_seg<5>" LOC = C17 | IOSTANDARD = LVCMOS33; +NET "dig2_seg<4>" LOC = D17 | IOSTANDARD = LVCMOS33; +NET "dig2_seg<3>" LOC = B15 | IOSTANDARD = LVCMOS33; +NET "dig2_seg<2>" LOC = A18 | IOSTANDARD = LVCMOS33; +NET "dig2_seg<1>" LOC = B18 | IOSTANDARD = LVCMOS33; +NET "dig2_seg<0>" LOC = B17 | IOSTANDARD = LVCMOS33; + +NET "dig3_seg<7>" LOC = D15 | IOSTANDARD = LVCMOS33; +NET "dig3_seg<6>" LOC = E13 | IOSTANDARD = LVCMOS33; +NET "dig3_seg<5>" LOC = B13 | IOSTANDARD = LVCMOS33; +NET "dig3_seg<4>" LOC = D13 | IOSTANDARD = LVCMOS33; +NET "dig3_seg<3>" LOC = D14 | IOSTANDARD = LVCMOS33; +NET "dig3_seg<2>" LOC = A14 | IOSTANDARD = LVCMOS33; +NET "dig3_seg<1>" LOC = E16 | IOSTANDARD = LVCMOS33; +NET "dig3_seg<0>" LOC = E15 | IOSTANDARD = LVCMOS33; + +NET "dig4_seg<7>" LOC = D11 | IOSTANDARD = LVCMOS33; +NET "dig4_seg<6>" LOC = E9 | IOSTANDARD = LVCMOS33; +NET "dig4_seg<5>" LOC = A10 | IOSTANDARD = LVCMOS33; +NET "dig4_seg<4>" LOC = B9 | IOSTANDARD = LVCMOS33; +NET "dig4_seg<3>" LOC = A9 | IOSTANDARD = LVCMOS33; +NET "dig4_seg<2>" LOC = C10 | IOSTANDARD = LVCMOS33; +NET "dig4_seg<1>" LOC = A12 | IOSTANDARD = LVCMOS33; +NET "dig4_seg<0>" LOC = B10 | IOSTANDARD = LVCMOS33; + +NET "dig5_seg<7>" LOC = C7 | IOSTANDARD = LVCMOS33; +NET "dig5_seg<6>" LOC = A4 | IOSTANDARD = LVCMOS33; +NET "dig5_seg<5>" LOC = B5 | IOSTANDARD = LVCMOS33; +NET "dig5_seg<4>" LOC = E6 | IOSTANDARD = LVCMOS33; +NET "dig5_seg<3>" LOC = C5 | IOSTANDARD = LVCMOS33; +NET "dig5_seg<2>" LOC = E7 | IOSTANDARD = LVCMOS33; +NET "dig5_seg<1>" LOC = B8 | IOSTANDARD = LVCMOS33; +NET "dig5_seg<0>" LOC = C6 | IOSTANDARD = LVCMOS33; + + +# Header A (left) +NET "header_a<2>" LOC = V7 | IOSTANDARD = LVCMOS33; +NET "header_a<3>" LOC = AA8 | IOSTANDARD = LVCMOS33; +NET "header_a<4>" LOC = AB8 | IOSTANDARD = LVCMOS33; +NET "header_a<5>" LOC = V8 | IOSTANDARD = LVCMOS33; +NET "header_a<6>" LOC = Y10 | IOSTANDARD = LVCMOS33; +NET "header_a<7>" LOC = V9 | IOSTANDARD = LVCMOS33; +NET "header_a<8>" LOC = W9 | IOSTANDARD = LVCMOS33; +NET "header_a<9>" LOC = AA10 | IOSTANDARD = LVCMOS33; +NET "header_a<10>" LOC = AB10 | IOSTANDARD = LVCMOS33; +NET "header_a<11>" LOC = W10 | IOSTANDARD = LVCMOS33; +NET "header_a<12>" LOC = AB11 | IOSTANDARD = LVCMOS33; +NET "header_a<13>" LOC = U11 | IOSTANDARD = LVCMOS33; +NET "header_a<14>" LOC = AB13 | IOSTANDARD = LVCMOS33; +NET "header_a<15>" LOC = AA13 | IOSTANDARD = LVCMOS33; +NET "header_a<16>" LOC = V10 | IOSTANDARD = LVCMOS33; +NET "header_a<17>" LOC = U10 | IOSTANDARD = LVCMOS33; +NET "header_a<18>" LOC = W13 | IOSTANDARD = LVCMOS33; +NET "header_a<19>" LOC = Y13 | IOSTANDARD = LVCMOS33; + +# Header B (right) +NET "header_b<2>" LOC = V14 | IOSTANDARD = LVCMOS33; +NET "header_b<3>" LOC = V13 | IOSTANDARD = LVCMOS33; +NET "header_b<4>" LOC = AA15 | IOSTANDARD = LVCMOS33; +NET "header_b<5>" LOC = W14 | IOSTANDARD = LVCMOS33; +NET "header_b<6>" LOC = AB15 | IOSTANDARD = LVCMOS33; +NET "header_b<7>" LOC = Y16 | IOSTANDARD = LVCMOS33; +NET "header_b<8>" LOC = AA17 | IOSTANDARD = LVCMOS33; +NET "header_b<9>" LOC = AA18 | IOSTANDARD = LVCMOS33; +NET "header_b<10>" LOC = AB18 | IOSTANDARD = LVCMOS33; +NET "header_b<11>" LOC = Y18 | IOSTANDARD = LVCMOS33; +NET "header_b<12>" LOC = Y19 | IOSTANDARD = LVCMOS33; +NET "header_b<13>" LOC = AB20 | IOSTANDARD = LVCMOS33; +NET "header_b<14>" LOC = AA20 | IOSTANDARD = LVCMOS33; +NET "header_b<15>" LOC = U16 | IOSTANDARD = LVCMOS33; +NET "header_b<16>" LOC = V16 | IOSTANDARD = LVCMOS33; +NET "header_b<17>" LOC = V17 | IOSTANDARD = LVCMOS33; +NET "header_b<18>" LOC = W16 | IOSTANDARD = LVCMOS33; +NET "header_b<19>" LOC = W17 | IOSTANDARD = LVCMOS33; + +# usused pins +CONFIG PROHIBIT = A3; +CONFIG PROHIBIT = A7; +CONFIG PROHIBIT = A11; +CONFIG PROHIBIT = A16; +CONFIG PROHIBIT = AA3; +CONFIG PROHIBIT = AA7; +CONFIG PROHIBIT = AA9; +CONFIG PROHIBIT = AA11; +CONFIG PROHIBIT = AA14; +CONFIG PROHIBIT = AA16; +CONFIG PROHIBIT = AA19; +CONFIG PROHIBIT = AB7; +CONFIG PROHIBIT = AB9; +CONFIG PROHIBIT = AB12; +CONFIG PROHIBIT = AB14; +CONFIG PROHIBIT = AB16; +CONFIG PROHIBIT = AB19; +CONFIG PROHIBIT = B4; +CONFIG PROHIBIT = B7; +CONFIG PROHIBIT = B12; +CONFIG PROHIBIT = B11; +CONFIG PROHIBIT = B16; +CONFIG PROHIBIT = C2; +CONFIG PROHIBIT = C3; +CONFIG PROHIBIT = C4; +CONFIG PROHIBIT = C12; +CONFIG PROHIBIT = C16; +CONFIG PROHIBIT = D2; +CONFIG PROHIBIT = D3; +CONFIG PROHIBIT = D4; +CONFIG PROHIBIT = D5; +CONFIG PROHIBIT = D8; +CONFIG PROHIBIT = D12; +CONFIG PROHIBIT = D16; +CONFIG PROHIBIT = E2; +CONFIG PROHIBIT = E3; +CONFIG PROHIBIT = E8; +CONFIG PROHIBIT = E4; +CONFIG PROHIBIT = E5; +CONFIG PROHIBIT = F4; +CONFIG PROHIBIT = E10; +CONFIG PROHIBIT = E12; +CONFIG PROHIBIT = F12; +CONFIG PROHIBIT = F5; +CONFIG PROHIBIT = F13; +CONFIG PROHIBIT = F6; +CONFIG PROHIBIT = F9; +CONFIG PROHIBIT = F10; +CONFIG PROHIBIT = F16; +CONFIG PROHIBIT = F11; +CONFIG PROHIBIT = F14; +CONFIG PROHIBIT = G3; +CONFIG PROHIBIT = G4; +CONFIG PROHIBIT = G5; +CONFIG PROHIBIT = G20; +CONFIG PROHIBIT = H1; +CONFIG PROHIBIT = H2; +CONFIG PROHIBIT = H4; +CONFIG PROHIBIT = H18; +CONFIG PROHIBIT = H19; +CONFIG PROHIBIT = H21; +CONFIG PROHIBIT = H22; +CONFIG PROHIBIT = J1; +CONFIG PROHIBIT = J2; +CONFIG PROHIBIT = J4; +CONFIG PROHIBIT = J5; +CONFIG PROHIBIT = J6; +CONFIG PROHIBIT = J17; +CONFIG PROHIBIT = J18; +CONFIG PROHIBIT = J19; +CONFIG PROHIBIT = J21; +CONFIG PROHIBIT = J22; +CONFIG PROHIBIT = K5; +CONFIG PROHIBIT = K6; +CONFIG PROHIBIT = K17; +CONFIG PROHIBIT = K18; +CONFIG PROHIBIT = N5; +CONFIG PROHIBIT = N6; +CONFIG PROHIBIT = N17; +CONFIG PROHIBIT = N18; +CONFIG PROHIBIT = N19; +CONFIG PROHIBIT = N20; +CONFIG PROHIBIT = P1; +CONFIG PROHIBIT = P2; +CONFIG PROHIBIT = P4; +CONFIG PROHIBIT = P5; +CONFIG PROHIBIT = P6; +CONFIG PROHIBIT = P17; +CONFIG PROHIBIT = P18; +CONFIG PROHIBIT = P19; +CONFIG PROHIBIT = P21; +CONFIG PROHIBIT = P22; +CONFIG PROHIBIT = R1; +CONFIG PROHIBIT = R2; +CONFIG PROHIBIT = R4; +CONFIG PROHIBIT = R5; +CONFIG PROHIBIT = R19; +CONFIG PROHIBIT = R21; +CONFIG PROHIBIT = R22; +CONFIG PROHIBIT = T3; +CONFIG PROHIBIT = T19; +CONFIG PROHIBIT = T20; +CONFIG PROHIBIT = U9; +CONFIG PROHIBIT = U12; +CONFIG PROHIBIT = U13; +CONFIG PROHIBIT = U14; +CONFIG PROHIBIT = U17; +CONFIG PROHIBIT = V11; +CONFIG PROHIBIT = V12; +CONFIG PROHIBIT = V15; +CONFIG PROHIBIT = W7; +CONFIG PROHIBIT = W8; +CONFIG PROHIBIT = W11; +CONFIG PROHIBIT = W12; +CONFIG PROHIBIT = W15; +CONFIG PROHIBIT = W18; +CONFIG PROHIBIT = Y4; +CONFIG PROHIBIT = Y7; +CONFIG PROHIBIT = Y11; +CONFIG PROHIBIT = Y12; diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.prj b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.prj new file mode 100644 index 0000000..24120d5 --- /dev/null +++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.prj @@ -0,0 +1,19 @@ +vhdl work ../top.vhd +vhdl zpu ../../../zpu_pkg.vhdl +vhdl zpu ../../../zpu_small.vhdl +vhdl zpu ../../../zpu_medium.vhdl +vhdl zpu ../../../roms/rom_pkg.vhdl +#vhdl zpu ../../../roms/hello_dbram.vhdl +#vhdl zpu ../../../roms/hello_bram.vhdl +vhdl zpu ../../../roms/dmips_dbram.vhdl +vhdl zpu ../../../roms/dmips_bram.vhdl +vhdl zpu ../../../helpers/zpu_small1.vhdl +vhdl zpu ../../../helpers/zpu_med1.vhdl +vhdl zpu ../../../devices/txt_util.vhdl +vhdl zpu ../../../devices/phi_io.vhdl +vhdl zpu ../../../devices/timer.vhdl +vhdl zpu ../../../devices/gpio.vhdl +vhdl zpu ../../../devices/rx_unit.vhdl +vhdl zpu ../../../devices/tx_unit.vhdl +vhdl zpu ../../../devices/br_gen.vhdl +vhdl zpu ../../../devices/trace.vhdl diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.ut b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.ut new file mode 100644 index 0000000..765a6f3 --- /dev/null +++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.ut @@ -0,0 +1,29 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g CRC:Enable +-g ConfigRate:6 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g HswapenPin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g DCMShutdown:Disable +-g DCIUpdateMode:AsRequired +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Match_cycle:Auto +-g Security:None +-g DonePipe:No +-g DriveDone:No diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.xst b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.xst new file mode 100644 index 0000000..14873ea --- /dev/null +++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.xst @@ -0,0 +1,56 @@ +set -tmpdir "tmp" +set -xsthdpdir "xst" +run +-ifn ../synthesis_config/top.prj +-ifmt mixed +-ofn top +-ofmt NGC +-p xc3s1000-4-fg456 +-top top +-opt_mode Speed +-opt_level 1 +-iuc NO +-keep_hierarchy No +-netlist_hierarchy As_Optimized +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case Maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style LUT +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract Yes +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract Yes +-resource_sharing YES +-async_to_sync NO +-mult_style Auto +-iobuf YES +-max_fanout 500 +-bufg 8 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob Auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top.vhd b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top.vhd new file mode 100644 index 0000000..4a93c4f --- /dev/null +++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top.vhd @@ -0,0 +1,372 @@ +-- top module of +-- Altium LiveDesign Board +-- +-- using following external connections: +-- test button as reset +-- LEDs and 7 segment for output +-- RS232 +-- + + +library ieee; +use ieee.std_logic_1164.all; + +library zpu; +use zpu.zpupkg.all; -- zpu_dbgo_t + +library unisim; +use unisim.vcomponents.dcm; + + +entity top is + port ( + -- pragma translate_off + stop_simulation : out std_logic; + -- pragma translate_on + clk_50 : in std_logic; + reset_n : in std_logic; + -- + -- soft JTAG + soft_tdo : out std_logic; + soft_tms : in std_logic; + soft_tdi : in std_logic; + soft_tck : in std_logic; + -- + -- SRAM 0 (256k x 16) pin connections + sram0_a : out std_logic_vector(18 downto 0); + sram0_d : inout std_logic_vector(15 downto 0); + sram0_lb_n : out std_logic; + sram0_ub_n : out std_logic; + sram0_cs_n : out std_logic; -- chip select + sram0_we_n : out std_logic; -- write-enable + sram0_oe_n : out std_logic; -- output enable + -- + -- SRAM 1 (256k x 16) pin connections + sram1_a : out std_logic_vector(18 downto 0); + sram1_d : inout std_logic_vector(15 downto 0); + sram1_lb_n : out std_logic; + sram1_ub_n : out std_logic; + sram1_cs_n : out std_logic; -- chip select + sram1_we_n : out std_logic; -- write-enable + sram1_oe_n : out std_logic; -- output enable + -- + -- RS232 + rs232_rx : in std_logic; + rs232_tx : out std_logic; + rs232_cts : in std_logic; + rs232_rts : out std_logic; + -- + -- PS2 connectors + mouse_clk : inout std_logic; + mouse_data : inout std_logic; + kbd_clk : inout std_logic; + kbd_data : inout std_logic; + -- + -- vga output + vga_red : out std_logic_vector(7 downto 5); + vga_green : out std_logic_vector(7 downto 5); + vga_blue : out std_logic_vector(7 downto 5); + vga_hsync : out std_logic; + vga_vsync : out std_logic; + -- + -- Audio out + audio_r : out std_logic; + audio_l : out std_logic; + -- + -- GPIOs + switch_n : in std_logic_vector(7 downto 0); + button_n : in std_logic_vector(5 downto 0); + led : out std_logic_vector(7 downto 0); + -- + -- seven segment display + dig0_seg : out std_logic_vector(7 downto 0); + dig1_seg : out std_logic_vector(7 downto 0); + dig2_seg : out std_logic_vector(7 downto 0); + dig3_seg : out std_logic_vector(7 downto 0); + dig4_seg : out std_logic_vector(7 downto 0); + dig5_seg : out std_logic_vector(7 downto 0); + -- + -- User Header + header_a : inout std_logic_vector(19 downto 2); + header_b : inout std_logic_vector(19 downto 2) + ); +end entity top; + + +architecture rtl of top is + + + --------------------------- + -- type declarations + type zpu_type is (zpu_small, zpu_medium); + + --------------------------- + -- constant declarations + constant zpu_flavour : zpu_type := zpu_medium; -- choose your flavour HERE + -- modify frequency here + constant clk_multiply : positive := 3; -- 9 for small, 3 for medium + constant clk_divide : positive := 2; -- 5 for small, 2 for medium + -- + constant word_size_c : natural := 32; -- 32 bits data path + constant addr_w_c : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O + + constant clk_frequency : positive := 50; -- input frequency for correct calculation + + + --------------------------- + -- component declarations + component zpu_small1 is + generic ( + word_size : natural := 32; -- 32 bits data path + d_care_val : std_logic := '0'; -- Fill value + clk_freq : positive := 50; -- 50 MHz clock + brate : positive := 115200; -- RS232 baudrate + addr_w : natural := 16; -- 16 bits address space=64 kB, 32 kB I/O + bram_w : natural := 15 -- 15 bits RAM space=32 kB + ); + port ( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + break_o : out std_logic; -- Break executed + dbg_o : out zpu_dbgo_t; -- Debug info + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic; -- UART Rx + gpio_in : in std_logic_vector(31 downto 0); + gpio_out : out std_logic_vector(31 downto 0); + gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out + ); + end component zpu_small1; + + component zpu_med1 is + generic( + word_size : natural := 32; -- 32 bits data path + d_care_val : std_logic := '0'; -- Fill value + clk_freq : positive := 50; -- 50 MHz clock + brate : positive := 115200; -- RS232 baudrate + addr_w : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O + bram_w : natural := 15 -- 15 bits RAM space=32 kB + ); + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + break_o : out std_logic; -- Break executed + dbg_o : out zpu_dbgo_t; -- Debug info + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic; -- UART Rx + gpio_in : in std_logic_vector(31 downto 0); + gpio_out : out std_logic_vector(31 downto 0); + gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out + ); + end component zpu_med1; + + + --------------------------- + -- signal declarations + signal dcm_i0_clk0 : std_ulogic; + signal dcm_i0_clkfx : std_ulogic; + signal clk_fb : std_ulogic; + signal clk : std_ulogic; + -- + signal reset_shift_reg : std_ulogic_vector(3 downto 0); + signal reset_sync : std_ulogic; + -- + signal zpu_i0_dbg : zpu_dbgo_t; -- Debug info + signal zpu_i0_break : std_logic; + -- + signal gpio_in : std_logic_vector(31 downto 0) := (others => '0'); + signal zpu_i0_gpio_out : std_logic_vector(31 downto 0); + signal zpu_i0_gpio_dir : std_logic_vector(31 downto 0); + + +begin + + -- default output drivers + -- to pass bitgen DRC + -- outputs used by design are commented + soft_tdo <= '1'; + -- + sram0_a <= (others => '1'); + sram0_d <= (others => 'Z'); + sram0_lb_n <= '1'; + sram0_ub_n <= '1'; + sram0_cs_n <= '1'; + sram0_we_n <= '1'; + sram0_oe_n <= '1'; + -- + sram1_a <= (others => '1'); + sram1_d <= (others => 'Z'); + sram1_lb_n <= '1'; + sram1_ub_n <= '1'; + sram1_cs_n <= '1'; + sram1_we_n <= '1'; + sram1_oe_n <= '1'; + -- + --rs232_tx <= '1'; + rs232_rts <= '1'; + -- + mouse_clk <= 'Z'; + mouse_data <= 'Z'; + kbd_clk <= 'Z'; + kbd_data <= 'Z'; + -- + vga_red <= (others => '1'); + vga_green <= (others => '1'); + vga_blue <= (others => '1'); + vga_hsync <= '1'; + vga_vsync <= '1'; + -- + audio_r <= '0'; + audio_l <= '0'; + -- + --led <= (others => '0'); + -- + --dig0_seg <= (others => '0'); + --dig1_seg <= (others => '0'); + dig2_seg <= (others => '0'); + dig3_seg <= (others => '0'); + dig4_seg <= (others => '0'); + dig5_seg <= (others => '0'); + -- + header_a <= (others => 'Z'); + header_b <= (others => 'Z'); + + + -- digital clock manager (DCM) + -- to generate higher/other system clock frequencys + dcm_i0 : dcm + generic map ( + startup_wait => true, -- wait with DONE till locked + clkfx_multiply => clk_multiply, + clkfx_divide => clk_divide, + clk_feedback => "1X" + ) + port map ( + clkin => clk_50, + clk0 => dcm_i0_clk0, + clkfx => dcm_i0_clkfx, + clkfb => clk_fb + ); + + clk_fb <= dcm_i0_clk0; + clk <= dcm_i0_clkfx; + + + -- reset synchronizer + -- generate synchronous reset + reset_synchronizer : process(clk, reset_n) + begin + if reset_n = '0' then + reset_shift_reg <= (others => '1'); + elsif rising_edge(clk) then + reset_shift_reg <= reset_shift_reg(reset_shift_reg'high-1 downto 0) & '0'; + end if; + end process; + reset_sync <= reset_shift_reg(reset_shift_reg'high); + + + -- select instance of zpu + zpu_i0_small : if zpu_flavour = zpu_small generate + zpu_i0 : zpu_small1 + generic map ( + addr_w => addr_w_c, + word_size => word_size_c, + clk_freq => clk_frequency * clk_multiply / clk_divide + ) + port map ( + clk_i => clk, -- : in std_logic; -- CPU clock + rst_i => reset_sync, -- : in std_logic; -- Reset + break_o => zpu_i0_break, -- : out std_logic; -- Break executed + dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; -- Debug info + rs232_tx_o => rs232_tx, -- : out std_logic; -- UART Tx + rs232_rx_i => rs232_rx, -- : in std_logic -- UART Rx + gpio_in => gpio_in, -- : in std_logic_vector(31 downto 0); + gpio_out => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0); + gpio_dir => zpu_i0_gpio_dir -- : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out + ); + end generate zpu_i0_small; + + zpu_i0_medium : if zpu_flavour = zpu_medium generate + zpu_i0 : zpu_med1 + generic map ( + addr_w => addr_w_c, + word_size => word_size_c, + clk_freq => clk_frequency * clk_multiply / clk_divide + ) + port map ( + clk_i => clk, -- : in std_logic; -- CPU clock + rst_i => reset_sync, -- : in std_logic; -- Reset + break_o => zpu_i0_break, -- : out std_logic; -- Break executed + dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; -- Debug info + rs232_tx_o => rs232_tx, -- : out std_logic; -- UART Tx + rs232_rx_i => rs232_rx, -- : in std_logic -- UART Rx + gpio_in => gpio_in, -- : in std_logic_vector(31 downto 0); + gpio_out => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0); + gpio_dir => zpu_i0_gpio_dir -- : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out + ); + end generate zpu_i0_medium; + + + -- pragma translate_off + stop_simulation <= zpu_i0_break; + + + trace_mod : trace + generic map ( + addr_w => addr_w_c, + word_size => word_size_c, + log_file => "zpu_trace.log" + ) + port map ( + clk_i => clk, + dbg_i => zpu_i0_dbg, + stop_i => zpu_i0_break, + busy_i => '0' + ); + -- pragma translate_on + + + -- assign GPIOs + -- + -- bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 + -- + -- in header_a(19.........12) -- -- -- -- -- -- -- -- + -- out header_a(19.........12) dig1_seg(7...........0) + -- + -- + -- bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + -- + -- in switch_n(7...........0) -- -- button_n(5....0) + -- out dig0_seg(7...........0) led(7................0) + -- + + gpio_in(31 downto 24) <= header_a(19 downto 12); + gpio_in(15 downto 8) <= switch_n; + gpio_in( 5 downto 0) <= button_n; + + -- 3-state buffers for some headers + header_a(19) <= zpu_i0_gpio_out(31) when zpu_i0_gpio_dir(31) = '0' else 'Z'; + header_a(18) <= zpu_i0_gpio_out(30) when zpu_i0_gpio_dir(30) = '0' else 'Z'; + header_a(17) <= zpu_i0_gpio_out(29) when zpu_i0_gpio_dir(29) = '0' else 'Z'; + header_a(16) <= zpu_i0_gpio_out(28) when zpu_i0_gpio_dir(28) = '0' else 'Z'; + header_a(15) <= zpu_i0_gpio_out(27) when zpu_i0_gpio_dir(27) = '0' else 'Z'; + header_a(14) <= zpu_i0_gpio_out(26) when zpu_i0_gpio_dir(26) = '0' else 'Z'; + header_a(13) <= zpu_i0_gpio_out(25) when zpu_i0_gpio_dir(25) = '0' else 'Z'; + header_a(12) <= zpu_i0_gpio_out(24) when zpu_i0_gpio_dir(24) = '0' else 'Z'; + + -- outputs + dig1_seg <= zpu_i0_gpio_out(23 downto 16); + dig0_seg <= zpu_i0_gpio_out(15 downto 8); + + -- switch on all LEDs in case of break + process + begin + wait until rising_edge(clk); + led <= zpu_i0_gpio_out(7 downto 0); + if zpu_i0_break = '1' then + led <= (others => '1'); + end if; + end process; + + +end architecture rtl; + diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top_tb.vhd b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top_tb.vhd new file mode 100644 index 0000000..e42fc20 --- /dev/null +++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/top_tb.vhd @@ -0,0 +1,194 @@ +-- testbench for +-- Altium LiveDesign Board +-- +-- includes "model" for clock generation +-- simulate press on test/reset as reset +-- +-- place models for external components (SRAM, PS2) in this file +-- + + +library ieee; +use ieee.std_logic_1164.all; + + +entity top_tb is +end entity top_tb; + +architecture testbench of top_tb is + + --------------------------- + -- constant declarations + constant clk_period : time := 1 sec / 50_000_000; -- 50 MHz + + + --------------------------- + -- signal declarations + signal simulation_run : boolean := true; + signal tb_stop_simulation : std_logic; + -- + signal tb_clk : std_logic := '0'; + signal tb_reset_n : std_logic; + -- + -- soft JTAG + signal tb_soft_tdo : std_logic; + signal tb_soft_tms : std_logic := '1'; + signal tb_soft_tdi : std_logic := '1'; + signal tb_soft_tck : std_logic := '1'; + -- + -- SRAM 0 (256k x 16) pin connections + signal tb_sram0_a : std_logic_vector(18 downto 0); + signal tb_sram0_d : std_logic_vector(15 downto 0) := (others => 'Z'); + signal tb_sram0_lb_n : std_logic; + signal tb_sram0_ub_n : std_logic; + signal tb_sram0_cs_n : std_logic; -- chip select + signal tb_sram0_we_n : std_logic; -- write-enable + signal tb_sram0_oe_n : std_logic; -- output enable + -- + -- SRAM 1 (256k x 16) pin connections + signal tb_sram1_a : std_logic_vector(18 downto 0); + signal tb_sram1_d : std_logic_vector(15 downto 0) := (others => 'Z'); + signal tb_sram1_lb_n : std_logic; + signal tb_sram1_ub_n : std_logic; + signal tb_sram1_cs_n : std_logic; -- chip select + signal tb_sram1_we_n : std_logic; -- write-enable + signal tb_sram1_oe_n : std_logic; -- output enable + -- + -- RS232 + signal tb_rs232_rx : std_logic := '1'; + signal tb_rs232_tx : std_logic; + signal tb_rs232_cts : std_logic := '1'; + signal tb_rs232_rts : std_logic; + -- + -- PS2 connectors + signal tb_mouse_clk : std_logic := 'Z'; + signal tb_mouse_data : std_logic := 'Z'; + signal tb_kbd_clk : std_logic := 'Z'; + signal tb_kbd_data : std_logic := 'Z'; + -- + -- vga output + signal tb_vga_red : std_logic_vector(7 downto 5); + signal tb_vga_green : std_logic_vector(7 downto 5); + signal tb_vga_blue : std_logic_vector(7 downto 5); + signal tb_vga_hsync : std_logic; + signal tb_vga_vsync : std_logic; + -- + -- Audio out + signal tb_audio_r : std_logic; + signal tb_audio_l : std_logic; + -- + -- GPIOs + signal tb_switch_n : std_logic_vector(7 downto 0) := (others => '1'); + signal tb_button_n : std_logic_vector(5 downto 0) := (others => '1'); + signal tb_led : std_logic_vector(7 downto 0); + -- + -- seven segment display + signal tb_dig0_seg : std_logic_vector(7 downto 0); + signal tb_dig1_seg : std_logic_vector(7 downto 0); + signal tb_dig2_seg : std_logic_vector(7 downto 0); + signal tb_dig3_seg : std_logic_vector(7 downto 0); + signal tb_dig4_seg : std_logic_vector(7 downto 0); + signal tb_dig5_seg : std_logic_vector(7 downto 0); + -- + -- User Header A + signal tb_header_a : std_logic_vector(19 downto 2) := (others => 'Z'); + signal tb_header_b : std_logic_vector(19 downto 2) := (others => 'Z'); + +begin + + -- generate clock + tb_clk <= not tb_clk after clk_period / 2 when simulation_run; + + -- generate reset + tb_reset_n <= '0', '1' after 6.66 * clk_period; + + + -- simulate keypress + tb_button_n(2) <= '1', '0' after 50 us, '1' after 52 us; + + -- dut + top_i0 : entity work.top + port map ( + stop_simulation => tb_stop_simulation, -- : out std_logic; + -- + clk_50 => tb_clk, -- : in std_logic; + reset_n => tb_reset_n, -- : in std_logic; + -- + -- soft JTAG + soft_tdo => tb_soft_tdo, -- : out std_logic; + soft_tms => tb_soft_tms, -- : in std_logic; + soft_tdi => tb_soft_tdi, -- : in std_logic; + soft_tck => tb_soft_tck, -- : in std_logic; + -- + -- SRAM 0 (256k x 16) pin connections + sram0_a => tb_sram0_a, -- : out std_logic_vector(18 downto 0); + sram0_d => tb_sram0_d, -- : inout std_logic_vector(15 downto 0); + sram0_lb_n => tb_sram0_lb_n, -- : out std_logic; + sram0_ub_n => tb_sram0_ub_n, -- : out std_logic; + sram0_cs_n => tb_sram0_cs_n, -- : out std_logic; -- chip select + sram0_we_n => tb_sram0_we_n, -- : out std_logic; -- write-enable + sram0_oe_n => tb_sram0_oe_n, -- : out std_logic; -- output enable + -- + -- SRAM 1 (256k x 16) pin connections + sram1_a => tb_sram1_a, -- : out std_logic_vector(18 downto 0); + sram1_d => tb_sram1_d, -- : inout std_logic_vector(15 downto 0); + sram1_lb_n => tb_sram1_lb_n, -- : out std_logic; + sram1_ub_n => tb_sram1_ub_n, -- : out std_logic; + sram1_cs_n => tb_sram1_cs_n, -- : out std_logic; -- chip select + sram1_we_n => tb_sram1_we_n, -- : out std_logic; -- write-enable + sram1_oe_n => tb_sram1_oe_n, -- : out std_logic; -- output enable + -- + -- RS232 + rs232_rx => tb_rs232_rx, -- : in std_logic; + rs232_tx => tb_rs232_tx, -- : out std_logic; + rs232_cts => tb_rs232_cts, -- : in std_logic; + rs232_rts => tb_rs232_rts, -- : out std_logic; + -- + -- PS2 connectors + mouse_clk => tb_mouse_clk, -- : inout std_logic; + mouse_data => tb_mouse_data, -- : inout std_logic; + kbd_clk => tb_kbd_clk, -- : inout std_logic; + kbd_data => tb_kbd_data, -- : inout std_logic; + -- + -- vga output + vga_red => tb_vga_red, -- : out std_logic_vector(7 downto 5); + vga_green => tb_vga_green, -- : out std_logic_vector(7 downto 5); + vga_blue => tb_vga_blue, -- : out std_logic_vector(7 downto 5); + vga_hsync => tb_vga_hsync, -- : out std_logic; + vga_vsync => tb_vga_vsync, -- : out std_logic; + -- + -- Audio out + audio_r => tb_audio_r, -- : out std_logic; + audio_l => tb_audio_l, -- : out std_logic; + -- + -- GPIOs + switch_n => tb_switch_n, -- : in std_logic_vector(7 downto 0); + button_n => tb_button_n, -- : in std_logic_vector(5 downto 0); + led => tb_led, -- : out std_logic_vector(7 downto 0); + -- + -- seven segment display + dig0_seg => tb_dig0_seg, -- : out std_logic_vector(7 downto 0); + dig1_seg => tb_dig1_seg, -- : out std_logic_vector(7 downto 0); + dig2_seg => tb_dig2_seg, -- : out std_logic_vector(7 downto 0); + dig3_seg => tb_dig3_seg, -- : out std_logic_vector(7 downto 0); + dig4_seg => tb_dig4_seg, -- : out std_logic_vector(7 downto 0); + dig5_seg => tb_dig5_seg, -- : out std_logic_vector(7 downto 0); + -- + -- User Header + header_a => tb_header_a, -- : inout std_logic_vector(19 downto 2); + header_b => tb_header_b -- : inout std_logic_vector(19 downto 2) + ); + + + -- check for simulation stopping + process (tb_stop_simulation) + begin + if tb_stop_simulation = '1' then + report "Simulation end." severity note; + simulation_run <= false; + end if; + end process; + + +end architecture testbench; + diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/clean_up.sh b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/clean_up.sh new file mode 100755 index 0000000..3855f16 --- /dev/null +++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/clean_up.sh @@ -0,0 +1,16 @@ +#!/bin/sh + +# ise build stuff +rm -rf build +rm -f top.bit + +# modelsim compile stuff +rm -rf work +rm -rf zpu + +# modelsim simulation stuff +rm -f vsim.wlf +rm -f transcript +rm -f zpu_trace.log +rm -f zpu_med1_io.log +rm -f zpu_small1_io.log diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation.sh b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation.sh new file mode 100755 index 0000000..d525737 --- /dev/null +++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation.sh @@ -0,0 +1,49 @@ +#!/bin/sh + +# need project files: +# run.do +# wave.do + +# need ModelSim tools: +# vlib +# vcom +# vsim + + +echo "###############" +echo "compile zpu lib" +echo "###############" +vlib zpu +vcom -work zpu ../../roms/hello_dbram.vhdl +vcom -work zpu ../../roms/hello_bram.vhdl +#vcom -work zpu ../../roms/dmips_dbram.vhdl +#vcom -work zpu ../../roms/dmips_bram.vhdl + +vcom -work zpu ../../roms/rom_pkg.vhdl +vcom -work zpu ../../zpu_pkg.vhdl +vcom -work zpu ../../zpu_small.vhdl +vcom -work zpu ../../zpu_medium.vhdl +vcom -work zpu ../../helpers/zpu_small1.vhdl +vcom -work zpu ../../helpers/zpu_med1.vhdl +vcom -work zpu ../../devices/txt_util.vhdl +vcom -work zpu ../../devices/phi_io.vhdl +vcom -work zpu ../../devices/timer.vhdl +vcom -work zpu ../../devices/gpio.vhdl +vcom -work zpu ../../devices/rx_unit.vhdl +vcom -work zpu ../../devices/tx_unit.vhdl +vcom -work zpu ../../devices/br_gen.vhdl +vcom -work zpu ../../devices/trace.vhdl + + +echo "################" +echo "compile work lib" +echo "################" +vlib work +vcom top.vhd +vcom top_tb.vhd + + +echo "###################" +echo "start simulator gui" +echo "###################" +vsim -gui top_tb -do simulation_config/run.do diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/run.do b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/run.do new file mode 100644 index 0000000..acc1710 --- /dev/null +++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/run.do @@ -0,0 +1,2 @@ +do wave.do +run -all diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/wave.do b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/wave.do new file mode 100644 index 0000000..d572a06 --- /dev/null +++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/wave.do @@ -0,0 +1,30 @@ +onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /top_tb/tb_gpio_button(0)
+add wave -noupdate /top_tb/tb_clk_100MHz
+add wave -noupdate -divider <NULL>
+add wave -noupdate /top_tb/tb_rs232_rx
+add wave -noupdate /top_tb/tb_rs232_tx
+add wave -noupdate /top_tb/tb_rs232_rts
+add wave -noupdate /top_tb/tb_rs232_cts
+add wave -noupdate -divider Buttons
+add wave -noupdate /top_tb/tb_gpio_button
+add wave -noupdate -divider LEDs
+add wave -noupdate /top_tb/tb_gpio_led_n
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {0 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 2
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ps} {126912555 ps}
diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis.sh b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis.sh new file mode 100755 index 0000000..d8d7603 --- /dev/null +++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis.sh @@ -0,0 +1,36 @@ +#!/bin/sh + +# need project files: +# top.xst +# top.prj +# top.ut + +# need Xilinx tools: +# xst +# ngdbuild +# map +# par +# trce +# bitgen + +echo "########################" +echo "generate build directory" +echo "########################" +mkdir build +cd build +mkdir tmp + +echo "###############" +echo "start processes" +echo "###############" +xst -ifn "../synthesis_config/top.xst" -ofn "top.syr" +ngdbuild -dd _ngo -nt timestamp -uc ../synthesis_config/avnet-eval-xc5vfx30t.ucf -p xc5vfx30t-ff665-1 top.ngc top.ngd +map -p xc5vfx30t-ff665-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -ir off -pr off -lc off -power off -o top_map.ncd top.ngd top.pcf +par -w -ol high -mt off top_map.ncd top.ncd top.pcf +trce -v 3 -s 1 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf +bitgen -f ../synthesis_config/top.ut top.ncd + +echo "###########" +echo "get bitfile" +echo "###########" +cp top.bit .. diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/avnet-eval-xc5vfx30t.ucf b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/avnet-eval-xc5vfx30t.ucf new file mode 100644 index 0000000..8494af3 --- /dev/null +++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/avnet-eval-xc5vfx30t.ucf @@ -0,0 +1,482 @@ +############################################################ +# Avnet Virtex 5 FX Evaluation Board constraints file +# +# Familiy: Virtex5 +# Device: XC5VFX30T +# Package: FF665 +# Speed: -1 +# +# +# Bank 0 3.3V +# Bank 1 3.3V +# Bank 2 3.3V +# Bank 3 3.3V +# Bank 4 2.5V or 3.3V (JP2, VIO_EXP1_DP), here 2.5V +# Bank 11 1.8V +# Bank 12 3.3V +# Bank 13 1.8V +# Bank 15 3.3V +# Bank 16 2.5V or 3.3V (JP3, VIO_EXP1_SE), here 2.5V +# Bank 17 1.8V +# Bank 18 2.5V or 3.3V (JP2, VIO_EXP1_DP), here 2.5V + + +############################################################ +## clock/timing constraints +############################################################ + +TIMESPEC "TS_clk_100" = PERIOD "clk_100" 100 MHz; + + +############################################################ +## design placement constraints +############################################################ +# +# the following constraint are need if you want to synthesize +# zpu_medium with 125 MHz +# +INST "zpu_i0_medium.zpu_i0/zpu/*" AREA_GROUP = "zpu_block"; +AREA_GROUP "zpu_block" RANGE=SLICE_X18Y0:SLICE_X55Y41; +AREA_GROUP "zpu_block" RANGE=DSP48_X0Y0:DSP48_X0Y15; +AREA_GROUP "zpu_block" RANGE=RAMB36_X1Y0:RAMB36_X3Y7; + + +############################################################ +## pin placement constraints +############################################################ + +NET "clk_100MHz" LOC= E18 | IOSTANDARD = LVCMOS33 | TNM_NET = "clk_100"; +NET "clk_socket" LOC= E13 | IOSTANDARD = LVCMOS33; +NET "user_clk_p" LOC= AB15 ; +NET "user_clk_n" LOC= AC16 ; + +# RS232 +NET "RS232_RX" LOC= K8 | IOSTANDARD = LVCMOS33; +NET "RS232_TX" LOC= L8 | IOSTANDARD = LVCMOS33; +NET "RS232_RTS" LOC= N8 | IOSTANDARD = LVCMOS33; # Jumper J3 +NET "RS232_CTS" LOC= R8 | IOSTANDARD = LVCMOS33; # Jumper J4 + +# RS232_USB +NET "RS232_USB_RX" LOC= AA10 | IOSTANDARD = LVCMOS33; +NET "RS232_USB_TX" LOC= AA19 | IOSTANDARD = LVCMOS33; +NET "RS232_USB_reset_n" LOC= Y20 | IOSTANDARD = LVCMOS33; + +# GPIO LEDs, active low +NET "GPIO_LED_n<0>" LOC= AF22 | IOSTANDARD = LVCMOS18 | PULLUP; +NET "GPIO_LED_n<1>" LOC= AF23 | IOSTANDARD = LVCMOS18 | PULLUP; +NET "GPIO_LED_n<2>" LOC= AF25 | IOSTANDARD = LVCMOS18 | PULLUP; +NET "GPIO_LED_n<3>" LOC= AE25 | IOSTANDARD = LVCMOS18 | PULLUP; +NET "GPIO_LED_n<4>" LOC= AD25 | IOSTANDARD = LVCMOS18 | PULLUP; +NET "GPIO_LED_n<5>" LOC= AE26 | IOSTANDARD = LVCMOS18 | PULLUP; +NET "GPIO_LED_n<6>" LOC= AD26 | IOSTANDARD = LVCMOS18 | PULLUP; +NET "GPIO_LED_n<7>" LOC= AC26 | IOSTANDARD = LVCMOS18 | PULLUP; + +# GPIO DIP_Switches +NET "GPIO_DIPswitch<0>" LOC= AD13 | IOSTANDARD = LVCMOS18; +NET "GPIO_DIPswitch<1>" LOC= AE13 | IOSTANDARD = LVCMOS18; +NET "GPIO_DIPswitch<2>" LOC= AF13 | IOSTANDARD = LVCMOS18; +NET "GPIO_DIPswitch<3>" LOC= AD15 | IOSTANDARD = LVCMOS18; +NET "GPIO_DIPswitch<4>" LOC= AD14 | IOSTANDARD = LVCMOS18; +NET "GPIO_DIPswitch<5>" LOC= AF14 | IOSTANDARD = LVCMOS18; +NET "GPIO_DIPswitch<6>" LOC= AE15 | IOSTANDARD = LVCMOS18; +NET "GPIO_DIPswitch<7>" LOC= AF15 | IOSTANDARD = LVCMOS18; + +# Push Buttons +NET "GPIO_button<0>" LOC= AF20 | IOSTANDARD = LVCMOS18 | PULLUP; #PB1 +NET "GPIO_button<1>" LOC= AE20 | IOSTANDARD = LVCMOS18 | PULLUP; #PB2 +NET "GPIO_button<2>" LOC= AD19 | IOSTANDARD = LVCMOS18 | PULLUP; #PB3 +NET "GPIO_button<3>" LOC= AD20 | IOSTANDARD = LVCMOS18 | PULLUP; #PB4 + +# FLASH_8Mx16 +NET "FLASH_A<31>" LOC= Y11 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<30>" LOC= H9 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<29>" LOC= G10 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<28>" LOC= H21 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<27>" LOC= G20 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<26>" LOC= H11 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<25>" LOC= G11 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<24>" LOC= H19 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<23>" LOC= H18 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<22>" LOC= G12 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<21>" LOC= F13 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<20>" LOC= G19 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<19>" LOC= F18 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<18>" LOC= F14 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<17>" LOC= F15 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<16>" LOC= F17 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<15>" LOC= G17 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<14>" LOC= G14 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<13>" LOC= H13 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<12>" LOC= G16 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<11>" LOC= G15 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<10>" LOC= Y18 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<9>" LOC= AA18 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<8>" LOC= Y10 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<7>" LOC= W11 | IOSTANDARD = LVCMOS33; +NET "FLASH_DQ<0>" LOC= AA15 | IOSTANDARD = LVCMOS33; +NET "FLASH_DQ<1>" LOC= Y15 | IOSTANDARD = LVCMOS33; +NET "FLASH_DQ<2>" LOC= W14 | IOSTANDARD = LVCMOS33; +NET "FLASH_DQ<3>" LOC= Y13 | IOSTANDARD = LVCMOS33; +NET "FLASH_DQ<4>" LOC= W16 | IOSTANDARD = LVCMOS33; +NET "FLASH_DQ<5>" LOC= Y16 | IOSTANDARD = LVCMOS33; +NET "FLASH_DQ<6>" LOC= AA14 | IOSTANDARD = LVCMOS33; +NET "FLASH_DQ<7>" LOC= AA13 | IOSTANDARD = LVCMOS33; +NET "FLASH_DQ<8>" LOC= AB12 | IOSTANDARD = LVCMOS25; # with level shifter +NET "FLASH_DQ<9>" LOC= AC11 | IOSTANDARD = LVCMOS25; # with level shifter +NET "FLASH_DQ<10>" LOC= AB20 | IOSTANDARD = LVCMOS25; # with level shifter +NET "FLASH_DQ<11>" LOC= AB21 | IOSTANDARD = LVCMOS25; # with level shifter +NET "FLASH_DQ<12>" LOC= AB11 | IOSTANDARD = LVCMOS25; # with level shifter +NET "FLASH_DQ<13>" LOC= AB10 | IOSTANDARD = LVCMOS25; # with level shifter +NET "FLASH_DQ<14>" LOC= AA20 | IOSTANDARD = LVCMOS25; # with level shifter +NET "FLASH_DQ<15>" LOC= Y21 | IOSTANDARD = LVCMOS25; # with level shifter +NET "FLASH_WEN" LOC= AA17 | IOSTANDARD = LVCMOS33; +NET "FLASH_OEN<0>" LOC= AA12 | IOSTANDARD = LVCMOS33; +NET "FLASH_CEN<0>" LOC= Y12 | IOSTANDARD = LVCMOS33; +NET "FLASH_rp_n" LOC= D13 | IOSTANDARD = LVCMOS33; +NET "FLASH_byte_n" LOC= Y17 | IOSTANDARD = LVCMOS33; +NET "FLASH_adv_n" LOC= F19 | IOSTANDARD = LVCMOS33; +NET "FLASH_clk" LOC= E12 | IOSTANDARD = LVCMOS33; +NET "FLASH_wait" LOC= D16 | IOSTANDARD = LVCMOS33; + +# DDR2_SDRAM_16Mx32 +NET "DDR2_ODT<0>" LOC= AF24 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<0>" LOC= U25 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<1>" LOC= T25 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<2>" LOC= T24 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<3>" LOC= T23 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<4>" LOC= U24 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<5>" LOC= V24 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<6>" LOC= Y23 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<7>" LOC= W23 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<8>" LOC= AA25 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<9>" LOC= AB26 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<10>" LOC= AB25 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<11>" LOC= AB24 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<12>" LOC= AA23 | IOSTANDARD = SSTL18_II; +NET "DDR2_BA<0>" LOC= U21 | IOSTANDARD = SSTL18_II; +NET "DDR2_BA<1>" LOC= V22 | IOSTANDARD = SSTL18_II; +NET "DDR2_CAS_N" LOC= W24 | IOSTANDARD = SSTL18_II; +NET "DDR2_CKE" LOC= T22 | IOSTANDARD = SSTL18_II; +NET "DDR2_CS_N" LOC= AD24 | IOSTANDARD = SSTL18_II; +NET "DDR2_RAS_N" LOC= Y22 | IOSTANDARD = SSTL18_II; +NET "DDR2_WE_N" LOC= AA22 | IOSTANDARD = SSTL18_II; +NET "DDR2_DM<0>" LOC= U26 | IOSTANDARD = SSTL18_II; +NET "DDR2_DM<1>" LOC= N24 | IOSTANDARD = SSTL18_II; +NET "DDR2_DM<2>" LOC= M24 | IOSTANDARD = SSTL18_II; +NET "DDR2_DM<3>" LOC= M25 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQS_P<0>" LOC= W26 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQS_P<1>" LOC= L23 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQS_P<2>" LOC= K22 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQS_P<3>" LOC= J21 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQS_N<0>" LOC= W25 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQS_N<1>" LOC= L22 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQS_N<2>" LOC= K23 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQS_N<3>" LOC= K21 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<0>" LOC= R22 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<1>" LOC= R23 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<2>" LOC= P23 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<3>" LOC= P24 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<4>" LOC= R25 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<5>" LOC= P25 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<6>" LOC= R26 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<7>" LOC= P26 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<8>" LOC= M26 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<9>" LOC= N26 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<10>" LOC= K25 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<11>" LOC= L24 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<12>" LOC= K26 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<13>" LOC= J26 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<14>" LOC= J25 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<15>" LOC= N21 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<16>" LOC= M21 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<17>" LOC= J23 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<18>" LOC= H23 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<19>" LOC= H22 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<20>" LOC= G22 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<21>" LOC= F22 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<22>" LOC= F23 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<23>" LOC= E23 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<24>" LOC= G24 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<25>" LOC= F24 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<26>" LOC= G25 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<27>" LOC= H26 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<28>" LOC= G26 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<29>" LOC= F25 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<30>" LOC= E25 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<31>" LOC= E26 | IOSTANDARD = SSTL18_II; +NET "DDR2_CK_p<0>" LOC= V21 | IOSTANDARD = DIFF_SSTL18_II; +NET "DDR2_CK_p<1>" LOC= N22 | IOSTANDARD = DIFF_SSTL18_II; +NET "DDR2_CK_n<0>" LOC= W21 | IOSTANDARD = DIFF_SSTL18_II; +NET "DDR2_CK_n<1>" LOC= M22 | IOSTANDARD = DIFF_SSTL18_II; + +# Ethernet MAC +NET "GMII_txer" LOC= A22 | IOSTANDARD = LVCMOS33; +NET "GMII_tx_clk" LOC= E17 | IOSTANDARD = LVCMOS33 | PERIOD=40000 ps; +NET "GMII_rx_clk" LOC= E20 | IOSTANDARD = LVCMOS33 | PERIOD=40000 ps; +NET "GMII_gtc_clk" LOC= A19 | IOSTANDARD = LVCMOS33; +NET "GMII_crs" LOC= A25 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; +NET "GMII_dv" LOC= C21 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; +NET "GMII_rx_data<0>" LOC= D24 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; +NET "GMII_rx_data<1>" LOC= D23 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; +NET "GMII_rx_data<2>" LOC= D21 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; +NET "GMII_rx_data<3>" LOC= C26 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; +NET "GMII_rx_data<4>" LOC= D20 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; +NET "GMII_rx_data<5>" LOC= C23 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; +NET "GMII_rx_data<6>" LOC= B25 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; +NET "GMII_rx_data<7>" LOC= C22 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; +NET "GMII_col" LOC= A24 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; +NET "GMII_rx_er" LOC= B24 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; +NET "GMII_tx_en" LOC= A23 | IOSTANDARD = LVCMOS33; +NET "GMII_tx_data<0>" LOC= D19 | IOSTANDARD = LVCMOS33; +NET "GMII_tx_data<1>" LOC= C19 | IOSTANDARD = LVCMOS33; +NET "GMII_tx_data<2>" LOC= A20 | IOSTANDARD = LVCMOS33; +NET "GMII_tx_data<3>" LOC= B20 | IOSTANDARD = LVCMOS33; +NET "GMII_tx_data<4>" LOC= B19 | IOSTANDARD = LVCMOS33; +NET "GMII_tx_data<5>" LOC= A15 | IOSTANDARD = LVCMOS33; +NET "GMII_tx_data<6>" LOC= B22 | IOSTANDARD = LVCMOS33; +NET "GMII_tx_data<7>" LOC= B21 | IOSTANDARD = LVCMOS33; +NET "GBE_rst_n" LOC= B26 | IOSTANDARD = LVCMOS33; +NET "GBE_mdc" LOC= D26 | IOSTANDARD = LVCMOS33; +NET "GBE_mdio" LOC= D25 | IOSTANDARD = LVCMOS33; +NET "GBE_int_n" LOC= C24 | IOSTANDARD = LVCMOS33; +NET "GBE_mclk" LOC= F20 | IOSTANDARD = LVCMOS33; + +# SysACE CompactFlash +NET "SAM_CLK" LOC= F12 | IOSTANDARD = LVCMOS33; +NET "SAM_A<0>" LOC= Y5 | IOSTANDARD = LVCMOS33; +NET "SAM_A<1>" LOC= V7 | IOSTANDARD = LVCMOS33; +NET "SAM_A<2>" LOC= W6 | IOSTANDARD = LVCMOS33; +NET "SAM_A<3>" LOC= W5 | IOSTANDARD = LVCMOS33; +NET "SAM_A<4>" LOC= K6 | IOSTANDARD = LVCMOS33; +NET "SAM_A<5>" LOC= J5 | IOSTANDARD = LVCMOS33; +NET "SAM_A<6>" LOC= J6 | IOSTANDARD = LVCMOS33; +NET "SAM_D<0>" LOC= F5 | IOSTANDARD = LVCMOS33; +NET "SAM_D<1>" LOC= U7 | IOSTANDARD = LVCMOS33; +NET "SAM_D<2>" LOC= V6 | IOSTANDARD = LVCMOS33; +NET "SAM_D<3>" LOC= U5 | IOSTANDARD = LVCMOS33; +NET "SAM_D<4>" LOC= U6 | IOSTANDARD = LVCMOS33; +NET "SAM_D<5>" LOC= T5 | IOSTANDARD = LVCMOS33; +NET "SAM_D<6>" LOC= T7 | IOSTANDARD = LVCMOS33; +NET "SAM_D<7>" LOC= R6 | IOSTANDARD = LVCMOS33; +NET "SAM_D<8>" LOC= R7 | IOSTANDARD = LVCMOS33; +NET "SAM_D<9>" LOC= R5 | IOSTANDARD = LVCMOS33; +NET "SAM_D<10>" LOC= P6 | IOSTANDARD = LVCMOS33; +NET "SAM_D<11>" LOC= P8 | IOSTANDARD = LVCMOS33; +NET "SAM_D<12>" LOC= N6 | IOSTANDARD = LVCMOS33; +NET "SAM_D<13>" LOC= M7 | IOSTANDARD = LVCMOS33; +NET "SAM_D<14>" LOC= K5 | IOSTANDARD = LVCMOS33; +NET "SAM_D<15>" LOC= L7 | IOSTANDARD = LVCMOS33; +NET "SAM_CEN" LOC= G4 | IOSTANDARD = LVCMOS33; +NET "SAM_OEN" LOC= Y6 | IOSTANDARD = LVCMOS33; +NET "SAM_WEN" LOC= Y4 | IOSTANDARD = LVCMOS33; +NET "SAM_MPIRQ" LOC= H4 | IOSTANDARD = LVCMOS33; +NET "SAM_BRDY" LOC= G5 | IOSTANDARD = LVCMOS33; +NET "SAM_RESET_n" LOC= H6 | IOSTANDARD = LVCMOS33; + +# Expansion Header +NET "EXP1_SE_IO<0>" LOC= A8 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<1>" LOC= A12 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<2>" LOC= B10 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<3>" LOC= A10 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<4>" LOC= B9 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<5>" LOC= A9 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<6>" LOC= A5 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<7>" LOC= B11 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<8>" LOC= B6 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<9>" LOC= A7 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<10>" LOC= D8 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<11>" LOC= C9 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<12>" LOC= B7 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<13>" LOC= A4 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<14>" LOC= B5 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<15>" LOC= C8 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<16>" LOC= C7 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<17>" LOC= A3 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<18>" LOC= C6 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<19>" LOC= B4 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<20>" LOC= D6 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<21>" LOC= D9 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<22>" LOC= E8 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<23>" LOC= D5 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<24>" LOC= F7 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<25>" LOC= E7 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<26>" LOC= E5 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<27>" LOC= E6 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<28>" LOC= F8 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<29>" LOC= H7 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<30>" LOC= G7 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<31>" LOC= H8 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<32>" LOC= G9 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<33>" LOC= J8 | IOSTANDARD = LVCMOS25; +NET "EXP1_DIFF_P<0>" LOC= AF9 ; +NET "EXP1_DIFF_N<0>" LOC= AF10 ; +NET "EXP1_DIFF_P<1>" LOC= AF12 ; +NET "EXP1_DIFF_N<1>" LOC= AE12 ; +NET "EXP1_DIFF_P<2>" LOC= AF7 ; +NET "EXP1_DIFF_N<2>" LOC= AF8 ; +NET "EXP1_DIFF_P<3>" LOC= AE11 ; +NET "EXP1_DIFF_N<3>" LOC= AD11 ; +NET "EXP1_DIFF_P<4>" LOC= AF4 ; +NET "EXP1_DIFF_N<4>" LOC= AF3 ; +NET "EXP1_DIFF_P<5>" LOC= AD10 ; +NET "EXP1_DIFF_N<5>" LOC= AE10 ; +NET "EXP1_DIFF_P<6>" LOC= AE8 ; +NET "EXP1_DIFF_N<6>" LOC= AE7 ; +NET "EXP1_DIFF_P<7>" LOC= AC8 ; +NET "EXP1_DIFF_N<7>" LOC= AD8 ; +NET "EXP1_DIFF_P<8>" LOC= AD9 ; +NET "EXP1_DIFF_N<8>" LOC= AC9 ; +NET "EXP1_DIFF_P<9>" LOC= AE6 ; +NET "EXP1_DIFF_N<9>" LOC= AF5 ; +NET "EXP1_DIFF_P<10>" LOC= AB6 ; +NET "EXP1_DIFF_N<10>" LOC= AB7 ; +NET "EXP1_DIFF_P<11>" LOC= AC6 ; +NET "EXP1_DIFF_N<11>" LOC= AD5 ; +NET "EXP1_DIFF_P<12>" LOC= AD6 ; +NET "EXP1_DIFF_N<12>" LOC= AC7 ; +NET "EXP1_DIFF_P<13>" LOC= AE5 ; +NET "EXP1_DIFF_N<13>" LOC= AD4 ; +NET "EXP1_DIFF_P<14>" LOC= AB9 ; +NET "EXP1_DIFF_N<14>" LOC= AA9 ; +NET "EXP1_DIFF_P<15>" LOC= AC12 ; +NET "EXP1_DIFF_N<15>" LOC= AC13 ; +NET "EXP1_DIFF_P<16>" LOC= AA7 ; +NET "EXP1_DIFF_N<16>" LOC= AA8 ; +NET "EXP1_DIFF_P<17>" LOC= AA5 ; +NET "EXP1_DIFF_N<17>" LOC= AB5 ; +NET "EXP1_DIFF_P<18>" LOC= AB19 ; +NET "EXP1_DIFF_N<18>" LOC= AC19 ; +NET "EXP1_DIFF_P<19>" LOC= Y7 ; +NET "EXP1_DIFF_N<19>" LOC= Y8 ; +NET "EXP1_DIFF_P<20>" LOC= W9 ; +NET "EXP1_DIFF_N<20>" LOC= W8 ; +NET "EXP1_DIFF_P<21>" LOC= V8 ; +NET "EXP1_DIFF_N<21>" LOC= V9 ; +NET "EXP1_SE_CLK_OUT" LOC= B12 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_CLK_IN" LOC= E10 | IOSTANDARD = LVCMOS33; +NET "EXP1_DIFF_CLK_OUT_P" LOC= AC18 ; +NET "EXP1_DIFF_CLK_OUT_N" LOC= AB17 ; +NET "EXP1_DIFF_CLK_IN_P" LOC= AB14 ; +NET "EXP1_DIFF_CLK_IN_N" LOC= AC14 ; +#NET "EXP1_RCLK_DIFF_P" LOC= AB6 ; +#NET "EXP1_RCLK_DIFF_N" LOC= AB7 ; + +# CPU Debug Trace +NET "ATDD<8>" LOC= C16 | IOSTANDARD = LVCMOS33; +NET "ATDD<9>" LOC= A17 | IOSTANDARD = LVCMOS33; +NET "ATDD<10>" LOC= B15 | IOSTANDARD = LVCMOS33; +NET "ATDD<11>" LOC= E15 | IOSTANDARD = LVCMOS33; +NET "ATDD<12>" LOC= A14 | IOSTANDARD = LVCMOS33; +NET "ATDD<13>" LOC= D18 | IOSTANDARD = LVCMOS33; +NET "ATDD<14>" LOC= A13 | IOSTANDARD = LVCMOS33; +NET "ATDD<15>" LOC= C13 | IOSTANDARD = LVCMOS33; +NET "ATDD<16>" LOC= D14 | IOSTANDARD = LVCMOS33; +NET "ATDD<17>" LOC= C17 | IOSTANDARD = LVCMOS33; +NET "ATDD<18>" LOC= E16 | IOSTANDARD = LVCMOS33; +NET "ATDD<19>" LOC= C14 | IOSTANDARD = LVCMOS33; +NET "TRACE_TS10" LOC= B16 | IOSTANDARD = LVCMOS33; +NET "TRACE_TS20" LOC= E21 | IOSTANDARD = LVCMOS33; +NET "TRACE_TS1E" LOC= B14 | IOSTANDARD = LVCMOS33; +NET "TRACE_TS2E" LOC= B17 | IOSTANDARD = LVCMOS33; +NET "TRACE_TS3" LOC= C18 | IOSTANDARD = LVCMOS33; +NET "TRACE_TS4" LOC= G21 | IOSTANDARD = LVCMOS33; +NET "TRACE_TS5" LOC= A18 | IOSTANDARD = LVCMOS33; +NET "TRACE_TS6" LOC= F10 | IOSTANDARD = LVCMOS33; +NET "TRACE_CLK" LOC= D15 | IOSTANDARD = LVCMOS33; +NET "CPU_HRESET" LOC= E11 | IOSTANDARD = LVCMOS33; +NET "CPU_TDO" LOC= K7 | IOSTANDARD = LVCMOS33; +NET "CPU_TMS" LOC= L5 | IOSTANDARD = LVCMOS33; +NET "CPU_TDI" LOC= M6 | IOSTANDARD = LVCMOS33; +NET "CPU_TRST" LOC= N7 | IOSTANDARD = LVCMOS33; +NET "CPU_TCK" LOC= T8 | IOSTANDARD = LVCMOS33; +NET "CPU_HALT_n" LOC= W4 | IOSTANDARD = LVCMOS33; + + +# voltage termination +CONFIG PROHIBIT = AA24; +CONFIG PROHIBIT = AE23; +CONFIG PROHIBIT = AF17; +CONFIG PROHIBIT = V26; +CONFIG PROHIBIT = E22; +CONFIG PROHIBIT = L25; + +# unused pins +CONFIG PROHIBIT = F9; +CONFIG PROHIBIT = D10; +CONFIG PROHIBIT = C12; +CONFIG PROHIBIT = C11; +CONFIG PROHIBIT = D11; +CONFIG PROHIBIT = AB16; +CONFIG PROHIBIT = AB22; +CONFIG PROHIBIT = AC17; +CONFIG PROHIBIT = AC21; +CONFIG PROHIBIT = AE22; +CONFIG PROHIBIT = AD23; +CONFIG PROHIBIT = AC24; +CONFIG PROHIBIT = AC23; +CONFIG PROHIBIT = AC22; +CONFIG PROHIBIT = AB22; +CONFIG PROHIBIT = AE21; +CONFIG PROHIBIT = AD21; +CONFIG PROHIBIT = AF19; +CONFIG PROHIBIT = AF18; +CONFIG PROHIBIT = AE18; +CONFIG PROHIBIT = AD18; +CONFIG PROHIBIT = AE17; +CONFIG PROHIBIT = AE16; +CONFIG PROHIBIT = AD16; +CONFIG PROHIBIT = G6; +CONFIG PROHIBIT = H24; +CONFIG PROHIBIT = J24; +CONFIG PROHIBIT = N23; +CONFIG PROHIBIT = N15; +CONFIG PROHIBIT = P14; +CONFIG PROHIBIT = V23; +CONFIG PROHIBIT = Y26; +CONFIG PROHIBIT = Y25; +CONFIG PROHIBIT = P21; +CONFIG PROHIBIT = R21; +CONFIG PROHIBIT = U22; + +# grounded pins from gigabit transcievers +CONFIG PROHIBIT = K4; +CONFIG PROHIBIT = K3; +CONFIG PROHIBIT = J1; +CONFIG PROHIBIT = K1; +CONFIG PROHIBIT = M1; +CONFIG PROHIBIT = L1; +CONFIG PROHIBIT = T3; +CONFIG PROHIBIT = T4; +CONFIG PROHIBIT = R1; +CONFIG PROHIBIT = T1; +CONFIG PROHIBIT = V1; +CONFIG PROHIBIT = U1; +CONFIG PROHIBIT = D3; +CONFIG PROHIBIT = D4; +CONFIG PROHIBIT = C1; +CONFIG PROHIBIT = D1; +CONFIG PROHIBIT = E1; +CONFIG PROHIBIT = F1; +CONFIG PROHIBIT = AB3; +CONFIG PROHIBIT = AB4; +CONFIG PROHIBIT = AA1; +CONFIG PROHIBIT = AB1; +CONFIG PROHIBIT = AC1; +CONFIG PROHIBIT = AD1; +CONFIG PROHIBIT = H2; +CONFIG PROHIBIT = J2; +CONFIG PROHIBIT = N2; +CONFIG PROHIBIT = M2; +CONFIG PROHIBIT = P2; +CONFIG PROHIBIT = R2; +CONFIG PROHIBIT = V2; +CONFIG PROHIBIT = W2; +CONFIG PROHIBIT = B2; +CONFIG PROHIBIT = C2; +CONFIG PROHIBIT = G2; +CONFIG PROHIBIT = F2; +CONFIG PROHIBIT = Y2; +CONFIG PROHIBIT = AA2; +CONFIG PROHIBIT = AD2; +CONFIG PROHIBIT = AE2; + diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj new file mode 100644 index 0000000..24120d5 --- /dev/null +++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj @@ -0,0 +1,19 @@ +vhdl work ../top.vhd +vhdl zpu ../../../zpu_pkg.vhdl +vhdl zpu ../../../zpu_small.vhdl +vhdl zpu ../../../zpu_medium.vhdl +vhdl zpu ../../../roms/rom_pkg.vhdl +#vhdl zpu ../../../roms/hello_dbram.vhdl +#vhdl zpu ../../../roms/hello_bram.vhdl +vhdl zpu ../../../roms/dmips_dbram.vhdl +vhdl zpu ../../../roms/dmips_bram.vhdl +vhdl zpu ../../../helpers/zpu_small1.vhdl +vhdl zpu ../../../helpers/zpu_med1.vhdl +vhdl zpu ../../../devices/txt_util.vhdl +vhdl zpu ../../../devices/phi_io.vhdl +vhdl zpu ../../../devices/timer.vhdl +vhdl zpu ../../../devices/gpio.vhdl +vhdl zpu ../../../devices/rx_unit.vhdl +vhdl zpu ../../../devices/tx_unit.vhdl +vhdl zpu ../../../devices/br_gen.vhdl +vhdl zpu ../../../devices/trace.vhdl diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.ut b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.ut new file mode 100644 index 0000000..e0159fb --- /dev/null +++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.ut @@ -0,0 +1,39 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g CRC:Enable +-g ConfigRate:2 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g InitPin:Pullup +-g CsPin:Pullup +-g DinPin:Pullup +-g BusyPin:Pullup +-g RdWrPin:Pullup +-g HswapenPin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g ConfigFallback:Enable +-g SelectMAPAbort:Enable +-g BPI_page_size:1 +-g OverTempPowerDown:Disable +-g JTAG_SysMon:Enable +-g DCIUpdateMode:AsRequired +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Match_cycle:Auto +-g Security:None +-g DonePipe:No +-g DriveDone:No +-g Encrypt:No diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.xst b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.xst new file mode 100644 index 0000000..7ca54bc --- /dev/null +++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.xst @@ -0,0 +1,60 @@ +set -tmpdir "tmp" +set -xsthdpdir "xst" +run +-ifn ../synthesis_config/top.prj +-ifmt mixed +-ofn top +-ofmt NGC +-p xc5vfx30t-1-ff665 +-top top +-opt_mode Speed +-opt_level 1 +-power NO +-iuc NO +-keep_hierarchy No +-netlist_hierarchy As_Optimized +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case Maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-dsp_utilization_ratio 100 +-lc Off +-reduce_control_sets Off +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style LUT +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract Yes +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract Yes +-resource_sharing YES +-async_to_sync NO +-use_dsp48 Auto +-iobuf YES +-max_fanout 100000 +-bufg 32 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-use_clock_enable Auto +-use_sync_set Auto +-use_sync_reset Auto +-iob Auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd new file mode 100644 index 0000000..560e685 --- /dev/null +++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd @@ -0,0 +1,444 @@ +-- top module of +-- Avnet Virtex 5 FX Evaluation Board +-- +-- using following external connections: +-- pushbutton PB1 as reset +-- LEDs for output +-- RS232 (non USB) +-- + + +library ieee; +use ieee.std_logic_1164.all; + +library zpu; +use zpu.zpupkg.all; -- zpu_dbgo_t + +library unisim; +use unisim.vcomponents.ibufds; +use unisim.vcomponents.dcm_base; + + +entity top is + port ( + -- pragma translate_off + stop_simulation : out std_logic; + -- pragma translate_on + clk_100MHz : in std_logic; -- 100 MHz clock + clk_socket : in std_logic; -- user clock + user_clk_p : in std_logic; -- differential user clock + user_clk_n : in std_logic; -- differential user clock + -- + -- RS232 + rs232_rx : in std_logic; + rs232_tx : out std_logic; + rs232_rts : in std_logic; + rs232_cts : out std_logic; + -- RS232 USB + rs232_usb_rx : in std_logic; + rs232_usb_tx : out std_logic; + rs232_usb_reset_n : out std_logic; + -- + gpio_led_n : out std_logic_vector(7 downto 0); + gpio_dipswitch : in std_logic_vector(7 downto 0); + gpio_button : in std_logic_vector(3 downto 0); + -- + -- FLASH 8Mx16 + flash_a : out std_logic_vector(31 downto 7); + flash_dq : inout std_logic_vector(15 downto 0); + flash_wen : out std_logic; + flash_oen : out std_logic_vector(0 downto 0); + flash_cen : out std_logic_vector(0 downto 0); + flash_rp_n : out std_logic; + flash_byte_n : out std_logic; + flash_adv_n : out std_logic; + flash_clk : out std_logic; + flash_wait : in std_logic; + -- + -- DDR2 SDRAM 16Mx32 + ddr2_odt : in std_logic_vector(0 downto 0); + ddr2_a : out std_logic_vector(12 downto 0); + ddr2_ba : out std_logic_vector(1 downto 0); + ddr2_cas_n : out std_logic; + ddr2_cke : out std_logic; + ddr2_cs_n : out std_logic; + ddr2_ras_n : out std_logic; + ddr2_we_n : out std_logic; + ddr2_dm : out std_logic_vector(3 downto 0); + ddr2_dqs_p : inout std_logic_vector(3 downto 0); + ddr2_dqs_n : inout std_logic_vector(3 downto 0); + ddr2_dq : inout std_logic_vector(31 downto 0); + ddr2_ck_p : in std_logic_vector(1 downto 0); + ddr2_ck_n : in std_logic_vector(1 downto 0); + -- + -- Ethernet MAC + gmii_txer : out std_logic; + gmii_tx_clk : in std_logic; -- 25 MHz + gmii_rx_clk : in std_logic; -- 25 MHz + gmii_gtc_clk : out std_logic; + gmii_crs : in std_logic; + gmii_dv : in std_logic; + gmii_rx_data : in std_logic_vector(7 downto 0); + gmii_col : in std_logic; + gmii_rx_er : in std_logic; + gmii_tx_en : out std_logic; + gmii_tx_data : out std_logic_vector(7 downto 0); + gbe_rst_n : out std_logic; + gbe_mdc : out std_logic; + gbe_mdio : inout std_logic; + gbe_int_n : inout std_logic; + gbe_mclk : in std_logic; + -- + -- SysACE CompactFlash + sam_clk : in std_logic; + sam_a : out std_logic_vector(6 downto 0); + sam_d : inout std_logic_vector(15 downto 0); + sam_cen : out std_logic; + sam_oen : out std_logic; + sam_wen : out std_logic; + sam_mpirq : in std_logic; + sam_brdy : in std_logic; + sam_reset_n : out std_logic; + -- + -- Expansion Header + exp1_se_io : inout std_logic_vector(33 downto 0); + exp1_diff_p : inout std_logic_vector(21 downto 0); + exp1_diff_n : inout std_logic_vector(21 downto 0); + exp1_se_clk_out : out std_logic; + exp1_se_clk_in : in std_logic; + exp1_diff_clk_out_p : out std_logic; + exp1_diff_clk_out_n : out std_logic; + exp1_diff_clk_in_p : in std_logic; + exp1_diff_clk_in_n : in std_logic; + -- + -- Debug/Trace + atdd : inout std_logic_vector(19 downto 8); + trace_ts10 : inout std_logic; + trace_ts20 : inout std_logic; + trace_ts1e : inout std_logic; + trace_ts2e : inout std_logic; + trace_ts3 : inout std_logic; + trace_ts4 : inout std_logic; + trace_ts5 : inout std_logic; + trace_ts6 : inout std_logic; + trace_clk : in std_logic; + cpu_hreset : in std_logic; + cpu_tdo : out std_logic; + cpu_tms : in std_logic; + cpu_tdi : in std_logic; + cpu_trst : in std_logic; + cpu_tck : in std_logic; + cpu_halt_n : in std_logic + ); +end entity top; + + +architecture rtl of top is + + --------------------------- + -- type declarations + type zpu_type is (zpu_small, zpu_medium); + + --------------------------- + -- constant declarations + constant zpu_flavour : zpu_type := zpu_medium; -- choose your flavour HERE + -- modify frequency here + constant clk_multiply : positive := 5; -- 7 for small, 5 for medium + constant clk_divide : positive := 4; -- 4 for small, 4 for medium + -- + -- + constant word_size_c : natural := 32; -- 32 bits data path + constant addr_w_c : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O + -- + constant clk_frequency : positive := 100; -- input frequency for correct calculation + + --------------------------- + -- component declarations + component zpu_small1 is + generic ( + word_size : natural := 32; -- 32 bits data path + d_care_val : std_logic := '0'; -- Fill value + clk_freq : positive := 50; -- 50 MHz clock + brate : positive := 115200; -- RS232 baudrate + addr_w : natural := 16; -- 16 bits address space=64 kB, 32 kB I/O + bram_w : natural := 15 -- 15 bits RAM space=32 kB + ); + port ( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + break_o : out std_logic; -- Break executed + dbg_o : out zpu_dbgo_t; -- Debug info + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic; -- UART Rx + gpio_in : in std_logic_vector(31 downto 0); + gpio_out : out std_logic_vector(31 downto 0); + gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out + ); + end component zpu_small1; + + component zpu_med1 is + generic( + word_size : natural := 32; -- 32 bits data path + d_care_val : std_logic := '0'; -- Fill value + clk_freq : positive := 50; -- 50 MHz clock + brate : positive := 115200; -- RS232 baudrate + addr_w : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O + bram_w : natural := 15 -- 15 bits RAM space=32 kB + ); + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + break_o : out std_logic; -- Break executed + dbg_o : out zpu_dbgo_t; -- Debug info + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic; -- UART Rx + gpio_in : in std_logic_vector(31 downto 0); + gpio_out : out std_logic_vector(31 downto 0); + gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out + ); + end component zpu_med1; + + + + --------------------------- + -- signal declarations + signal sys_clk : std_ulogic; + signal dcm_base_i0_clk0 : std_ulogic; + signal dcm_base_i0_clkfx : std_ulogic; + signal clk_fb : std_ulogic; + signal clk : std_ulogic; + -- + signal reset_shift_reg : std_ulogic_vector(3 downto 0); + signal reset_sync : std_ulogic; + -- + signal zpu_i0_dbg : zpu_dbgo_t; -- Debug info + signal zpu_i0_break : std_logic; + -- + signal ibufds_i0_o : std_ulogic; + signal ibufds_i1_o : std_ulogic; + -- + signal gpio_in : std_logic_vector(31 downto 0) := (others => '0'); + signal zpu_i0_gpio_out : std_logic_vector(31 downto 0); + signal zpu_i0_gpio_dir : std_logic_vector(31 downto 0); + +begin + + -- default output drivers + -- to pass bitgen DRC + -- other used outputs are only commented + --rs232_tx <= '1'; + rs232_cts <= '1'; + rs232_usb_tx <= '1'; + rs232_usb_reset_n <= '1'; + -- + --gpio_led_n <= (others => '1'); + -- + flash_cen <= "1"; + flash_oen <= "1"; + flash_wen <= '1'; + flash_rp_n <= '1'; + flash_byte_n <= '1'; + flash_adv_n <= '1'; + flash_clk <= '0'; + flash_a <= (others => '0'); + flash_dq <= (others => 'Z'); + -- + ddr2_a <= (others => '0'); + ddr2_ba <= (others => '0'); + ddr2_dm <= (others => '0'); + ddr2_cs_n <= '1'; + ddr2_we_n <= '1'; + ddr2_cke <= '1'; + ddr2_cas_n <= '1'; + ddr2_ras_n <= '1'; + ddr2_dqs_p <= (others => 'Z'); + ddr2_dqs_n <= (others => 'Z'); + ddr2_dq <= (others => 'Z'); + -- + gmii_gtc_clk <= '0'; + gmii_tx_data <= (others => '0'); + gmii_tx_en <= '0'; + gmii_txer <= '0'; + gbe_rst_n <= '1'; + gbe_mdc <= '1'; + gbe_mdio <= 'Z'; + gbe_int_n <= 'Z'; + -- + sam_cen <= '1'; + sam_oen <= '1'; + sam_wen <= '1'; + sam_a <= (others => '0'); + sam_d <= (others => 'Z'); + sam_reset_n <= '1'; + -- + exp1_se_io <= (others => 'Z'); + exp1_diff_p <= (others => 'Z'); + exp1_diff_n <= (others => 'Z'); + exp1_se_clk_out <= '0'; + exp1_diff_clk_out_p <= '0'; + exp1_diff_clk_out_n <= '1'; + -- + atdd <= (others => 'Z'); + trace_ts10 <= 'Z'; + trace_ts20 <= 'Z'; + trace_ts1e <= 'Z'; + trace_ts2e <= 'Z'; + trace_ts3 <= 'Z'; + trace_ts4 <= 'Z'; + trace_ts5 <= 'Z'; + trace_ts6 <= 'Z'; + cpu_tdo <= '1'; + + + -- global differential input buffer + ibufds_i0 : ibufds + generic map ( + diff_term => true + ) + port map ( + o => ibufds_i0_o, + i => ddr2_ck_p(0), + ib => ddr2_ck_n(0) + ); + + -- global differential input buffer + ibufds_i1 : ibufds + generic map ( + diff_term => true + ) + port map ( + o => ibufds_i1_o, + i => ddr2_ck_p(1), + ib => ddr2_ck_n(1) + ); + + -- digital clock manager (DCM) + -- to generate higher/other system clock frequencys + dcm_base_i0: dcm_base + generic map ( + startup_wait => true, -- wait with DONE till locked + --dfs_frequency_mode => "HIGH", -- use this with zpu_small for 175 MHz + clkfx_multiply => clk_multiply, + clkfx_divide => clk_divide, + clk_feedback => "1X" + ) + port map ( + rst => '0', + clkin => clk_100MHz, + clk0 => dcm_base_i0_clk0, + clkfx => dcm_base_i0_clkfx, + clkfb => clk_fb + ); + + -- speaking names for dcm output + clk_fb <= dcm_base_i0_clk0; + clk <= dcm_base_i0_clkfx; + + + -- reset synchronizer + -- generate synchronous reset + reset_synchronizer : process(clk, gpio_button) + begin + if (gpio_button(0) = '1') then + reset_shift_reg <= (others => '1'); + elsif rising_edge(clk) then + reset_shift_reg <= reset_shift_reg(reset_shift_reg'high-1 downto 0) & '0'; + end if; + end process; + reset_sync <= reset_shift_reg(reset_shift_reg'high); + + + + -- select instance of zpu + zpu_i0_small: if zpu_flavour = zpu_small generate + zpu_i0 : zpu_small1 + generic map ( + addr_w => addr_w_c, + word_size => word_size_c, + clk_freq => clk_frequency * clk_multiply / clk_divide + ) + port map ( + clk_i => clk, -- : in std_logic; - CPU clock + rst_i => reset_sync, -- : in std_logic; - Reset + break_o => zpu_i0_break, -- : out std_logic; - Break executed + dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; - Debug info + rs232_tx_o => rs232_tx, -- : out std_logic; - UART Tx + rs232_rx_i => rs232_rx, -- : in std_logic - UART Rx + gpio_in => gpio_in, -- : in std_logic_vector(31 downto 0); + gpio_out => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0); + gpio_dir => zpu_i0_gpio_dir -- : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out + ); + end generate zpu_i0_small; + + zpu_i0_medium: if zpu_flavour = zpu_medium generate + zpu_i0 : zpu_med1 + generic map ( + addr_w => addr_w_c, + word_size => word_size_c, + clk_freq => clk_frequency * clk_multiply / clk_divide + ) + port map ( + clk_i => clk, -- : in std_logic; - CPU clock + rst_i => reset_sync, -- : in std_logic; - Reset + break_o => zpu_i0_break, -- : out std_logic; - Break executed + dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; - Debug info + rs232_tx_o => rs232_tx, -- : out std_logic; - UART Tx + rs232_rx_i => rs232_rx, -- : in std_logic - UART Rx + gpio_in => gpio_in, -- : in std_logic_vector(31 downto 0); + gpio_out => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0); + gpio_dir => zpu_i0_gpio_dir -- : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out + ); + end generate zpu_i0_medium; + + -- pragma translate_off + stop_simulation <= zpu_i0_break; -- abort() causes to stop the simulation + + + trace_mod : trace + generic map ( + addr_w => addr_w_c, + word_size => word_size_c, + log_file => "zpu_trace.log" + ) + port map ( + clk_i => clk, + dbg_i => zpu_i0_dbg, + stop_i => zpu_i0_break, + busy_i => '0' + ); + -- pragma translate_on + + -- assign GPIOs + -- no bidirectional pins (e.g. headers), so + -- gpio_dir is unused + -- + -- bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 + -- + -- in -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- + -- out -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- + -- + -- + -- bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + -- + -- in gpio_dipswitch(7.....0) -- -- -- -- buttons3.0 + -- out -- -- -- -- -- -- -- -- led(7................0) + -- + + gpio_in(15 downto 8) <= gpio_dipswitch; + gpio_in( 3 downto 0) <= gpio_button; + + + -- switch on all LEDs in case of break + process + begin + wait until rising_edge(clk); + gpio_led_n <= not zpu_i0_gpio_out(7 downto 0); + if zpu_i0_break = '1' then + gpio_led_n <= (others => '0'); + end if; + end process; + + + +end architecture rtl; + diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top_tb.vhd b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top_tb.vhd new file mode 100644 index 0000000..751ce22 --- /dev/null +++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top_tb.vhd @@ -0,0 +1,271 @@ +-- testbench for +-- Avnet Virtex 5 FX Evaluation Board +-- +-- includes "model" for clock generation +-- simulate press on gpio_button(0) (=PB1) as reset +-- +-- place models for external components (PHY, DDR2-RAM) in this file +-- + + +library ieee; +use ieee.std_logic_1164.all; + + +entity top_tb is +end entity top_tb; + +architecture testbench of top_tb is + + --------------------------- + -- constant declarations + constant clk_100MHz_period : time := 1 sec / 100_000_000; -- 100 MHz + + + --------------------------- + -- signal declarations + signal simulation_run : boolean := true; + signal tb_stop_simulation : std_logic; + -- + signal tb_clk_100MHz : std_logic := '0'; -- 100 MHz clock + signal tb_clk_socket : std_logic := '0'; -- user clock + signal tb_user_clk_p : std_logic := '0'; -- diff user clock + signal tb_user_clk_n : std_logic := '0'; -- diff user clock + -- + -- RS232 + signal tb_rs232_rx : std_logic := '0'; + signal tb_rs232_tx : std_logic; + signal tb_rs232_rts : std_logic := '0'; + signal tb_rs232_cts : std_logic; + -- RS232 USB + signal tb_rs232_usb_rx : std_logic := '0'; + signal tb_rs232_usb_tx : std_logic; + signal tb_rs232_usb_reset_n : std_logic; + -- + signal tb_gpio_led_n : std_logic_vector(7 downto 0); + signal tb_gpio_dipswitch : std_logic_vector(7 downto 0) := (others => '0'); + signal tb_gpio_button : std_logic_vector(3 downto 0) := (others => '0'); + -- + -- FLASH 8Mx16 + signal tb_flash_a : std_logic_vector(31 downto 7); + signal tb_flash_dq : std_logic_vector(15 downto 0); + signal tb_flash_wen : std_logic; + signal tb_flash_oen : std_logic_vector(0 downto 0); + signal tb_flash_cen : std_logic_vector(0 downto 0); + signal tb_flash_rp_n : std_logic; + signal tb_flash_byte_n : std_logic; + signal tb_flash_adv_n : std_logic; + signal tb_flash_clk : std_logic; + signal tb_flash_wait : std_logic := '0'; + -- + -- DDR2 SDRAM 16Mx32 + signal tb_ddr2_odt : std_logic_vector(0 downto 0) := (others => '0'); + signal tb_ddr2_a : std_logic_vector(12 downto 0); + signal tb_ddr2_ba : std_logic_vector(1 downto 0); + signal tb_ddr2_cas_n : std_logic; + signal tb_ddr2_cke : std_logic; + signal tb_ddr2_cs_n : std_logic; + signal tb_ddr2_ras_n : std_logic; + signal tb_ddr2_we_n : std_logic; + signal tb_ddr2_dm : std_logic_vector(3 downto 0); + signal tb_ddr2_dqs_p : std_logic_vector(3 downto 0); + signal tb_ddr2_dqs_n : std_logic_vector(3 downto 0); + signal tb_ddr2_dq : std_logic_vector(31 downto 0); + signal tb_ddr2_ck_p : std_logic_vector(1 downto 0) := (others => '0'); + signal tb_ddr2_ck_n : std_logic_vector(1 downto 0) := (others => '0'); + -- + -- Ethernet MAC + signal tb_gmii_txer : std_logic; + signal tb_gmii_tx_clk : std_logic := '0'; -- 25 MHz + signal tb_gmii_rx_clk : std_logic := '0'; -- 25 MHz + signal tb_gmii_gtc_clk : std_logic; + signal tb_gmii_crs : std_logic := '0'; + signal tb_gmii_dv : std_logic := '0'; + signal tb_gmii_rx_data : std_logic_vector(7 downto 0); + signal tb_gmii_col : std_logic := '0'; + signal tb_gmii_rx_er : std_logic := '0'; + signal tb_gmii_tx_en : std_logic; + signal tb_gmii_tx_data : std_logic_vector(7 downto 0); + signal tb_gbe_rst_n : std_logic; + signal tb_gbe_mdc : std_logic; + signal tb_gbe_mdio : std_logic; + signal tb_gbe_int_n : std_logic; + signal tb_gbe_mclk : std_logic := '0'; + -- + -- SysACE CompactFlash + signal tb_sam_clk : std_logic := '0'; + signal tb_sam_a : std_logic_vector(6 downto 0); + signal tb_sam_d : std_logic_vector(15 downto 0); + signal tb_sam_cen : std_logic; + signal tb_sam_oen : std_logic; + signal tb_sam_wen : std_logic; + signal tb_sam_mpirq : std_logic := '0'; + signal tb_sam_brdy : std_logic := '0'; + signal tb_sam_reset_n : std_logic; + -- + -- Expansion Header + signal tb_exp1_se_io : std_logic_vector(33 downto 0); + signal tb_exp1_diff_p : std_logic_vector(21 downto 0); + signal tb_exp1_diff_n : std_logic_vector(21 downto 0); + signal tb_exp1_se_clk_out : std_logic; + signal tb_exp1_se_clk_in : std_logic := '0'; + signal tb_exp1_diff_clk_out_p : std_logic; + signal tb_exp1_diff_clk_out_n : std_logic; + signal tb_exp1_diff_clk_in_p : std_logic := '0'; + signal tb_exp1_diff_clk_in_n : std_logic := '0'; + -- + -- Debug/Trace + signal tb_atdd : std_logic_vector(19 downto 8); + signal tb_trace_ts10 : std_logic; + signal tb_trace_ts20 : std_logic; + signal tb_trace_ts1e : std_logic; + signal tb_trace_ts2e : std_logic; + signal tb_trace_ts3 : std_logic; + signal tb_trace_ts4 : std_logic; + signal tb_trace_ts5 : std_logic; + signal tb_trace_ts6 : std_logic; + signal tb_trace_clk : std_logic := '0'; + signal tb_cpu_hreset : std_logic := '0'; + signal tb_cpu_tdo : std_logic; + signal tb_cpu_tms : std_logic := '0'; + signal tb_cpu_tdi : std_logic := '0'; + signal tb_cpu_trst : std_logic := '0'; + signal tb_cpu_tck : std_logic := '0'; + signal tb_cpu_halt_n : std_logic := '0'; + + +begin + + + -- generate clocks + tb_clk_100MHz <= not tb_clk_100MHz after clk_100MHz_period / 2 when simulation_run; + + -- generate reset + tb_gpio_button(0) <= '1', '0' after 6.66 * clk_100MHz_period; + + + -- simulate keypress + tb_gpio_button(2) <= '0', '1' after 55 us, '0' after 56 us; + + -- dut + top_i0 : entity work.top + port map ( + stop_simulation => tb_stop_simulation, -- : out std_logic; + clk_100MHz => tb_clk_100MHz, -- : in std_logic; + clk_socket => tb_clk_socket, -- : in std_logic; + user_clk_p => tb_user_clk_p, -- : in std_logic; + user_clk_n => tb_user_clk_n, -- : in std_logic; + -- + -- RS232 + rs232_rx => tb_rs232_rx, -- : in std_logic; + rs232_tx => tb_rs232_tx, -- : out std_logic; + rs232_rts => tb_rs232_rts, -- : in std_logic; + rs232_cts => tb_rs232_cts, -- : out std_logic; + -- RS232 USB + rs232_usb_rx => tb_rs232_usb_rx, -- : in std_logic; + rs232_usb_tx => tb_rs232_usb_tx, -- : out std_logic; + rs232_usb_reset_n => tb_rs232_usb_reset_n, -- : out std_logic; + -- + gpio_led_n => tb_gpio_led_n, -- : out std_logic_vector(7 downto 0); + gpio_dipswitch => tb_gpio_dipswitch, -- : in std_logic_vector(7 downto 0); + gpio_button => tb_gpio_button, -- : in std_logic_vector(3 downto 0); + -- + -- FLASH 8Mx16 + flash_a => tb_flash_a, -- : out std_logic_vector(31 downto 7); + flash_dq => tb_flash_dq, -- : inout std_logic_vector(15 downto 0); + flash_wen => tb_flash_wen, -- : out std_logic; + flash_oen => tb_flash_oen, -- : out std_logic_vector(0 downto 0); + flash_cen => tb_flash_cen, -- : out std_logic_vector(0 downto 0); + flash_rp_n => tb_flash_rp_n, -- : out std_logic; + flash_byte_n => tb_flash_byte_n, -- : out std_logic; + flash_adv_n => tb_flash_adv_n, -- : out std_logic; + flash_clk => tb_flash_clk, -- : out std_logic; + flash_wait => tb_flash_wait, -- : in std_logic; + -- + -- DDR2 SDRAM 16Mx32 + ddr2_odt => tb_ddr2_odt, -- : in std_logic_vector(0 downto 0); + ddr2_a => tb_ddr2_a, -- : out std_logic_vector(12 downto 0); + ddr2_ba => tb_ddr2_ba, -- : out std_logic_vector(1 downto 0); + ddr2_cas_n => tb_ddr2_cas_n, -- : out std_logic; + ddr2_cke => tb_ddr2_cke, -- : out std_logic; + ddr2_cs_n => tb_ddr2_cs_n, -- : out std_logic; + ddr2_ras_n => tb_ddr2_ras_n, -- : out std_logic; + ddr2_we_n => tb_ddr2_we_n, -- : out std_logic; + ddr2_dm => tb_ddr2_dm, -- : out std_logic_vector(3 downto 0); + ddr2_dqs_p => tb_ddr2_dqs_p, -- : inout std_logic_vector(3 downto 0); + ddr2_dqs_n => tb_ddr2_dqs_n, -- : inout std_logic_vector(3 downto 0); + ddr2_dq => tb_ddr2_dq, -- : inout std_logic_vector(31 downto 0); + ddr2_ck_p => tb_ddr2_ck_p, -- : in std_logic_vector(1 downto 0); + ddr2_ck_n => tb_ddr2_ck_n, -- : in std_logic_vector(1 downto 0); + -- + -- Ethernet MAC + gmii_txer => tb_gmii_txer, -- : out std_logic; + gmii_tx_clk => tb_gmii_tx_clk, -- : in std_logic; + gmii_rx_clk => tb_gmii_rx_clk, -- : in std_logic; + gmii_gtc_clk => tb_gmii_gtc_clk, -- : out std_logic; + gmii_crs => tb_gmii_crs, -- : in std_logic; + gmii_dv => tb_gmii_dv, -- : in std_logic; + gmii_rx_data => tb_gmii_rx_data, -- : in std_logic_vector(7 downto 0); + gmii_col => tb_gmii_col, -- : in std_logic; + gmii_rx_er => tb_gmii_rx_er, -- : in std_logic; + gmii_tx_en => tb_gmii_tx_en, -- : out std_logic; + gmii_tx_data => tb_gmii_tx_data, -- : out std_logic_vector(7 downto 0); + gbe_rst_n => tb_gbe_rst_n, -- : out std_logic; + gbe_mdc => tb_gbe_mdc, -- : out std_logic; + gbe_mdio => tb_gbe_mdio, -- : inout std_logic; + gbe_int_n => tb_gbe_int_n, -- : inout std_logic; + gbe_mclk => tb_gbe_mclk, -- : in std_logic; + -- + -- SysACE CompactFlash + sam_clk => tb_sam_clk, -- : in std_logic; + sam_a => tb_sam_a, -- : out std_logic_vector(6 downto 0); + sam_d => tb_sam_d, -- : inout std_logic_vector(15 downto 0); + sam_cen => tb_sam_cen, -- : out std_logic; + sam_oen => tb_sam_oen, -- : out std_logic; + sam_wen => tb_sam_wen, -- : out std_logic; + sam_mpirq => tb_sam_mpirq, -- : in std_logic; + sam_brdy => tb_sam_brdy, -- : in std_logic; + sam_reset_n => tb_sam_reset_n, -- : out std_logic; + -- + -- Expansion Header + exp1_se_io => tb_exp1_se_io, -- : inout std_logic_vector(33 downto 0); + exp1_diff_p => tb_exp1_diff_p, -- : inout std_logic_vector(21 downto 0); + exp1_diff_n => tb_exp1_diff_n, -- : inout std_logic_vector(21 downto 0); + exp1_se_clk_out => tb_exp1_se_clk_out, -- : out std_logic; + exp1_se_clk_in => tb_exp1_se_clk_in, -- : in std_logic; + exp1_diff_clk_out_p => tb_exp1_diff_clk_out_p, -- : out std_logic; + exp1_diff_clk_out_n => tb_exp1_diff_clk_out_n, -- : out std_logic; + exp1_diff_clk_in_p => tb_exp1_diff_clk_in_p, -- : in std_logic; + exp1_diff_clk_in_n => tb_exp1_diff_clk_in_n, -- : in std_logic; + -- + -- Debug/Trace + atdd => tb_atdd, -- : inout std_logic_vector(19 downto 8); + trace_ts10 => tb_trace_ts10, -- : inout std_logic; + trace_ts20 => tb_trace_ts20, -- : inout std_logic; + trace_ts1e => tb_trace_ts1e, -- : inout std_logic; + trace_ts2e => tb_trace_ts2e, -- : inout std_logic; + trace_ts3 => tb_trace_ts3, -- : inout std_logic; + trace_ts4 => tb_trace_ts4, -- : inout std_logic; + trace_ts5 => tb_trace_ts5, -- : inout std_logic; + trace_ts6 => tb_trace_ts6, -- : inout std_logic; + trace_clk => tb_trace_clk, -- : in std_logic; + cpu_hreset => tb_cpu_hreset, -- : in std_logic; + cpu_tdo => tb_cpu_tdo, -- : out std_logic; + cpu_tms => tb_cpu_tms, -- : in std_logic; + cpu_tdi => tb_cpu_tdi, -- : in std_logic; + cpu_trst => tb_cpu_trst, -- : in std_logic; + cpu_tck => tb_cpu_tck, -- : in std_logic; + cpu_halt_n => tb_cpu_halt_n -- : in std_logic + ); + + + -- check for simulation stopping + process (tb_stop_simulation) + begin + if tb_stop_simulation = '1' then + report "Simulation end." severity note; + simulation_run <= false; + end if; + end process; + +end architecture testbench; diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/clean_up.sh b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/clean_up.sh new file mode 100755 index 0000000..3855f16 --- /dev/null +++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/clean_up.sh @@ -0,0 +1,16 @@ +#!/bin/sh + +# ise build stuff +rm -rf build +rm -f top.bit + +# modelsim compile stuff +rm -rf work +rm -rf zpu + +# modelsim simulation stuff +rm -f vsim.wlf +rm -f transcript +rm -f zpu_trace.log +rm -f zpu_med1_io.log +rm -f zpu_small1_io.log diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation.sh b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation.sh new file mode 100755 index 0000000..d525737 --- /dev/null +++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation.sh @@ -0,0 +1,49 @@ +#!/bin/sh + +# need project files: +# run.do +# wave.do + +# need ModelSim tools: +# vlib +# vcom +# vsim + + +echo "###############" +echo "compile zpu lib" +echo "###############" +vlib zpu +vcom -work zpu ../../roms/hello_dbram.vhdl +vcom -work zpu ../../roms/hello_bram.vhdl +#vcom -work zpu ../../roms/dmips_dbram.vhdl +#vcom -work zpu ../../roms/dmips_bram.vhdl + +vcom -work zpu ../../roms/rom_pkg.vhdl +vcom -work zpu ../../zpu_pkg.vhdl +vcom -work zpu ../../zpu_small.vhdl +vcom -work zpu ../../zpu_medium.vhdl +vcom -work zpu ../../helpers/zpu_small1.vhdl +vcom -work zpu ../../helpers/zpu_med1.vhdl +vcom -work zpu ../../devices/txt_util.vhdl +vcom -work zpu ../../devices/phi_io.vhdl +vcom -work zpu ../../devices/timer.vhdl +vcom -work zpu ../../devices/gpio.vhdl +vcom -work zpu ../../devices/rx_unit.vhdl +vcom -work zpu ../../devices/tx_unit.vhdl +vcom -work zpu ../../devices/br_gen.vhdl +vcom -work zpu ../../devices/trace.vhdl + + +echo "################" +echo "compile work lib" +echo "################" +vlib work +vcom top.vhd +vcom top_tb.vhd + + +echo "###################" +echo "start simulator gui" +echo "###################" +vsim -gui top_tb -do simulation_config/run.do diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/run.do b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/run.do new file mode 100644 index 0000000..0d29e0a --- /dev/null +++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/run.do @@ -0,0 +1,2 @@ +do wave.do
+run -all
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/wave.do b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/wave.do new file mode 100644 index 0000000..12582ce --- /dev/null +++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/simulation_config/wave.do @@ -0,0 +1,30 @@ +onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /top_tb/tb_rot_center
+add wave -noupdate /top_tb/tb_clk_50mhz
+add wave -noupdate /top_tb/tb_rs232_dce_rxd
+add wave -noupdate /top_tb/tb_rs232_dce_txd
+add wave -noupdate -divider Buttons
+add wave -noupdate /top_tb/tb_btn_east
+add wave -noupdate /top_tb/tb_btn_north
+add wave -noupdate /top_tb/tb_btn_south
+add wave -noupdate /top_tb/tb_btn_west
+add wave -noupdate -divider LEDs
+add wave -noupdate /top_tb/top_i0/led
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {56714893 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 2
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ps} {151772250 ps}
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis.sh b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis.sh new file mode 100755 index 0000000..66622ea --- /dev/null +++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis.sh @@ -0,0 +1,36 @@ +#!/bin/sh + +# need project files: +# top.xst +# top.prj +# top.ut + +# need Xilinx tools: +# xst +# ngdbuild +# map +# par +# trce +# bitgen + +echo "########################" +echo "generate build directory" +echo "########################" +mkdir build +cd build +mkdir tmp + +echo "###############" +echo "start processes" +echo "###############" +xst -ifn "../synthesis_config/top.xst" -ofn "top.syr" +ngdbuild -dd _ngo -nt timestamp -uc ../synthesis_config/digilent-starter-xc3s500e.ucf -p xc3s500e-fg320-4 top.ngc top.ngd +map -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o top_map.ncd top.ngd top.pcf +par -w -ol high -t 1 top_map.ncd top.ncd top.pcf +trce -v 3 -s 4 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf +bitgen -f ../synthesis_config/top.ut top.ncd + +echo "###########" +echo "get bitfile" +echo "###########" +cp top.bit .. diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/digilent-starter-xc3s500e.ucf b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/digilent-starter-xc3s500e.ucf new file mode 100644 index 0000000..1007d00 --- /dev/null +++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/digilent-starter-xc3s500e.ucf @@ -0,0 +1,356 @@ +#####################################################
+# SPARTAN-3E Starter Kit Board Constraints File
+#
+# Family: Spartan3E
+# Device: XC3S500E
+# Package: FG320
+# Speed: -4
+
+
+############################################################
+## clock/timing constraints
+############################################################
+
+# Define clock period for 50 MHz oscillator (40%/60% duty-cycle)
+TIMESPEC "TS_CLK_50MHZ" = PERIOD "CLK_50MHZ" 50.0 MHz HIGH 40%;
+
+# ethernet clock
+TIMESPEC "TS_E_CLK" = PERIOD "E_CLK" 25.0 MHz HIGH 50% ;
+# need because misplaced ethernet clock lines
+NET "E_RX_CLK" CLOCK_DEDICATED_ROUTE = FALSE ;
+NET "E_TX_CLK" CLOCK_DEDICATED_ROUTE = FALSE ;
+
+############################################################
+## pin placement constraints
+############################################################
+
+# Analog-to-Digital Converter (ADC)
+# some connections shared with SPI Flash, DAC, ADC, and AMP
+NET "AD_CONV" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+
+# Programmable Gain Amplifier (AMP)
+# some connections shared with SPI Flash, DAC, ADC, and AMP
+NET "AMP_CS" LOC = "N7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+NET "AMP_DOUT" LOC = "E18" | IOSTANDARD = LVCMOS33 ;
+NET "AMP_SHDN" LOC = "P7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+
+# Pushbuttons (BTN)
+NET "BTN_EAST" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN | TIG;
+NET "BTN_NORTH" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN | TIG;
+NET "BTN_SOUTH" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN | TIG;
+NET "BTN_WEST" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN | TIG;
+
+# Clock inputs (CLK)
+NET "CLK_50MHZ" LOC = "C9" | IOSTANDARD = LVCMOS33 | TNM_NET = "CLK_50MHZ";
+NET "CLK_AUX" LOC = "B8" | IOSTANDARD = LVCMOS33 ;
+NET "CLK_SMA" LOC = "A10" | IOSTANDARD = LVCMOS33 ;
+
+# Digital-to-Analog Converter (DAC)
+# some connections shared with SPI Flash, DAC, ADC, and AMP
+NET "DAC_CLR" LOC = "P8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "DAC_CS" LOC = "N8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+
+# 1-Wire Secure EEPROM (DS)
+NET "DS_WIRE" LOC = "U4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+
+# Ethernet PHY (E)
+NET "E_COL" LOC = "U6" | IOSTANDARD = LVCMOS33 ;
+NET "E_CRS" LOC = "U13" | IOSTANDARD = LVCMOS33 ;
+NET "E_MDC" LOC = "P9" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "E_MDIO" LOC = "U5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "E_RX_CLK" LOC = "V3" | IOSTANDARD = LVCMOS33 | TNM_NET = "E_CLK";
+NET "E_RX_DV" LOC = "V2" | IOSTANDARD = LVCMOS33 ;
+NET "E_RXD<0>" LOC = "V8" | IOSTANDARD = LVCMOS33 ;
+NET "E_RXD<1>" LOC = "T11" | IOSTANDARD = LVCMOS33 ;
+NET "E_RXD<2>" LOC = "U11" | IOSTANDARD = LVCMOS33 ;
+NET "E_RXD<3>" LOC = "V14" | IOSTANDARD = LVCMOS33 ;
+NET "E_RX_ER" LOC = "U14" | IOSTANDARD = LVCMOS33 ;
+NET "E_TX_CLK" LOC = "T7" | IOSTANDARD = LVCMOS33 | TNM_NET = "E_CLK";
+NET "E_TX_EN" LOC = "P15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "E_TXD<0>" LOC = "R11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "E_TXD<1>" LOC = "T15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "E_TXD<2>" LOC = "R5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "E_TXD<3>" LOC = "T5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "E_TX_ER" LOC = "R6" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+
+# FPGA Configuration Mode, INIT_B Pins (FPGA)
+NET "FPGA_M0" LOC = "M10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "FPGA_M1" LOC = "V11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "FPGA_M2" LOC = "T10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "FPGA_INIT_B" LOC = "T3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
+NET "FPGA_RDWR_B" LOC = "U10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
+NET "FPGA_HSWAP" LOC = "B3" | IOSTANDARD = LVCMOS33 ;
+
+# FX2 Connector (FX2)
+NET "FX2_CLKIN" LOC = "E10" | IOSTANDARD = LVCMOS33 ;
+NET "FX2_CLKIO" LOC = "D9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_CLKOUT" LOC = "D10" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+
+# These four connections are shared with the J1 6-pin accessory header
+NET "FX2_IO<1>" LOC = "B4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<2>" LOC = "A4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<3>" LOC = "D5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<4>" LOC = "C5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+
+# These four connections are shared with the J2 6-pin accessory header
+NET "FX2_IO<5>" LOC = "A6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<6>" LOC = "B6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<7>" LOC = "E7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<8>" LOC = "F7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+
+# These four connections are shared with the J4 6-pin accessory header
+NET "FX2_IO<9>" LOC = "D7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<10>" LOC = "C7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<11>" LOC = "F8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<12>" LOC = "E8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+
+# The discrete LEDs are shared with the following 8 FX2 connections
+NET "FX2_IO<13>" LOC = "F9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<14>" LOC = "E9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<15>" LOC = "D11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<16>" LOC = "C11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<17>" LOC = "F11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<18>" LOC = "E11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<19>" LOC = "E12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<20>" LOC = "F12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+
+NET "FX2_IO<21>" LOC = "A13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<22>" LOC = "B13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<23>" LOC = "A14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<24>" LOC = "B14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<25>" LOC = "C14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<26>" LOC = "D14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<27>" LOC = "A16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<28>" LOC = "B16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<29>" LOC = "E13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<30>" LOC = "C4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<31>" LOC = "B11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<32>" LOC = "A11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<33>" LOC = "A8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<34>" LOC = "G9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#
+NET "FX2_IO<35>" LOC = "D12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<36>" LOC = "C12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<37>" LOC = "A15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<38>" LOC = "B15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#
+NET "FX2_IO<39>" LOC = "C3" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+NET "FX2_IO<40>" LOC = "C15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+
+# 6-pin header J1
+# These are shared connections with the FX2 connector
+#NET "J1<0>" LOC = "B4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J1<1>" LOC = "A4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J1<2>" LOC = "D5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J1<3>" LOC = "C5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+
+# 6-pin header J2
+# These are shared connections with the FX2 connector
+#NET "J2<0>" LOC = "A6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J2<1>" LOC = "B6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J2<2>" LOC = "E7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J2<3>" LOC = "F7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+
+# 6-pin header J4
+# These are shared connections with the FX2 connector
+#NET "J4<0>" LOC = "D7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J4<1>" LOC = "C7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J4<2>" LOC = "F8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J4<3>" LOC = "E8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+
+# Character LCD (LCD)
+NET "LCD_E" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "LCD_RS" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "LCD_RW" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+
+# LCD data connections are shared with StrataFlash connections SF_D<11:8>
+#NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+
+# Discrete LEDs (LED)
+# These are shared connections with the FX2 connector
+#NET "LED<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<6>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<7>" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+
+# PS/2 Mouse/Keyboard Port (PS2)
+NET "PS2_CLK" LOC = "G14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW | TIG;
+NET "PS2_DATA" LOC = "G13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW | TIG;
+
+# Rotary Pushbutton Switch (ROT)
+NET "ROT_A" LOC = "K18" | IOSTANDARD = LVTTL | PULLUP | TIG;
+NET "ROT_B" LOC = "G18" | IOSTANDARD = LVTTL | PULLUP | TIG;
+NET "ROT_CENTER" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN | TIG;
+
+# RS-232 Serial Ports (RS232)
+NET "RS232_DCE_RXD" LOC = "R7" | IOSTANDARD = LVTTL | TIG;
+NET "RS232_DCE_TXD" LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW | TIG;
+NET "RS232_DTE_RXD" LOC = "U8" | IOSTANDARD = LVTTL | TIG;
+NET "RS232_DTE_TXD" LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW | TIG;
+
+# DDR SDRAM (SD) (I/O Bank 3, VCCO=2.5V)
+NET "SD_A<0>" LOC = "T1" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<1>" LOC = "R3" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<2>" LOC = "R2" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<3>" LOC = "P1" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<4>" LOC = "F4" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<5>" LOC = "H4" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<6>" LOC = "H3" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<7>" LOC = "H1" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<8>" LOC = "H2" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<9>" LOC = "N4" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<10>" LOC = "T2" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<11>" LOC = "N5" | IOSTANDARD = SSTL2_I ;
+NET "SD_A<12>" LOC = "P2" | IOSTANDARD = SSTL2_I ;
+NET "SD_BA<0>" LOC = "K5" | IOSTANDARD = SSTL2_I ;
+NET "SD_BA<1>" LOC = "K6" | IOSTANDARD = SSTL2_I ;
+NET "SD_CAS" LOC = "C2" | IOSTANDARD = SSTL2_I ;
+NET "SD_CK_N" LOC = "J4" | IOSTANDARD = SSTL2_I ; #DIFF_SSTL2_I ;
+NET "SD_CK_P" LOC = "J5" | IOSTANDARD = SSTL2_I ; #DIFF_SSTL2_I ;
+NET "SD_CKE" LOC = "K3" | IOSTANDARD = SSTL2_I ;
+NET "SD_CS" LOC = "K4" | IOSTANDARD = SSTL2_I ;
+NET "SD_DQ<0>" LOC = "L2" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<1>" LOC = "L1" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<2>" LOC = "L3" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<3>" LOC = "L4" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<4>" LOC = "M3" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<5>" LOC = "M4" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<6>" LOC = "M5" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<7>" LOC = "M6" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<8>" LOC = "E2" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<9>" LOC = "E1" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<10>" LOC = "F1" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<11>" LOC = "F2" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<12>" LOC = "G6" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<13>" LOC = "G5" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<14>" LOC = "H6" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_DQ<15>" LOC = "H5" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_LDM" LOC = "J2" | IOSTANDARD = SSTL2_I ;
+NET "SD_UDM" LOC = "J1" | IOSTANDARD = SSTL2_I ;
+NET "SD_RAS" LOC = "C1" | IOSTANDARD = SSTL2_I ;
+NET "SD_LDQS" LOC = "L6" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_UDQS" LOC = "G3" | IOSTANDARD = SSTL2_I | PULLUP ;
+NET "SD_WE" LOC = "D1" | IOSTANDARD = SSTL2_I ;
+# Path to allow connection to top DCM connection
+NET "SD_CK_FB" LOC = "B9" | IOSTANDARD = LVCMOS33 ;
+
+# Prohibit VREF pins
+CONFIG PROHIBIT = D2;
+CONFIG PROHIBIT = G4;
+CONFIG PROHIBIT = J6;
+CONFIG PROHIBIT = L5;
+CONFIG PROHIBIT = R4;
+
+# Intel StrataFlash Parallel NOR Flash (SF)
+NET "SF_A<0>" LOC = "H17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<1>" LOC = "J13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<2>" LOC = "J12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<3>" LOC = "J14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<4>" LOC = "J15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<5>" LOC = "J16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<6>" LOC = "J17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<7>" LOC = "K14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<8>" LOC = "K15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<9>" LOC = "K12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<10>" LOC = "K13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<11>" LOC = "L15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<12>" LOC = "L16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<13>" LOC = "T18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<14>" LOC = "R18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<15>" LOC = "T17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<16>" LOC = "U18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<17>" LOC = "T16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<18>" LOC = "U15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<19>" LOC = "V15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<20>" LOC = "T12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<21>" LOC = "V13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<22>" LOC = "V12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_A<23>" LOC = "N11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<24>" LOC = "A11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_BYTE" LOC = "C17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<1>" LOC = "P10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<2>" LOC = "R10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<3>" LOC = "V9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<4>" LOC = "U9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<5>" LOC = "R9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<6>" LOC = "M9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<7>" LOC = "N9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<12>" LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<13>" LOC = "P6" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<14>" LOC = "R8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_D<15>" LOC = "T8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_OE" LOC = "C18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "SF_STS" LOC = "B18" | IOSTANDARD = LVCMOS33 ;
+NET "SF_WE" LOC = "D17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+
+# STMicro SPI serial Flash (SPI)
+# some connections shared with SPI Flash, DAC, ADC, and AMP
+NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ;
+NET "SPI_MOSI" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+NET "SPI_SS_B" LOC = "U3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 | PULLUP ;
+NET "SPI_ALT_CS_JP11" LOC = "R12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+
+# Slide Switches (SW)
+NET "SW<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP | TIG;
+NET "SW<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP | TIG;
+NET "SW<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP | TIG;
+NET "SW<3>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP | TIG;
+
+# VGA Port (VGA)
+NET "VGA_BLUE" LOC = "G15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "VGA_GREEN" LOC = "H15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "VGA_HSYNC" LOC = "F15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "VGA_RED" LOC = "H14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "VGA_VSYNC" LOC = "F14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+
+# Xilinx CPLD (XC)
+NET "XC_CMD<0>" LOC = "P18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
+NET "XC_CMD<1>" LOC = "N18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
+NET "XC_CPLD_EN" LOC = "B10" | IOSTANDARD = LVTTL ;
+NET "XC_D<0>" LOC = "G16" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
+NET "XC_D<1>" LOC = "F18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
+NET "XC_D<2>" LOC = "F17" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
+NET "XC_TRIG" LOC = "R17" | IOSTANDARD = LVCMOS33 ;
+NET "XC_GCK0" LOC = "H16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "GCLK10" LOC = "C9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+
+# prohibit unused pins
+CONFIG PROHIBIT = A3;
+CONFIG PROHIBIT = A7;
+CONFIG PROHIBIT = D13;
+CONFIG PROHIBIT = F10;
+CONFIG PROHIBIT = G10;
+CONFIG PROHIBIT = C8;
+CONFIG PROHIBIT = D8;
+CONFIG PROHIBIT = A5;
+CONFIG PROHIBIT = B5;
+#
+CONFIG PROHIBIT = P13;
+CONFIG PROHIBIT = R13;
+CONFIG PROHIBIT = T14;
+CONFIG PROHIBIT = R14;
+#
+CONFIG PROHIBIT = D3;
+CONFIG PROHIBIT = F5;
+CONFIG PROHIBIT = G1;
+CONFIG PROHIBIT = J7;
+CONFIG PROHIBIT = K2;
+CONFIG PROHIBIT = K7;
+CONFIG PROHIBIT = M1;
+CONFIG PROHIBIT = N1;
+CONFIG PROHIBIT = N2;
+CONFIG PROHIBIT = R1;
+CONFIG PROHIBIT = U1;
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj new file mode 100644 index 0000000..965ae4c --- /dev/null +++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj @@ -0,0 +1,19 @@ +vhdl work ../top.vhd
+vhdl zpu ../../../zpu_pkg.vhdl
+vhdl zpu ../../../zpu_small.vhdl
+vhdl zpu ../../../zpu_medium.vhdl
+vhdl zpu ../../../roms/rom_pkg.vhdl
+#vhdl zpu ../../../roms/hello_dbram.vhdl
+#vhdl zpu ../../../roms/hello_bram.vhdl
+vhdl zpu ../../../roms/dmips_dbram.vhdl
+vhdl zpu ../../../roms/dmips_bram.vhdl
+vhdl zpu ../../../helpers/zpu_small1.vhdl
+vhdl zpu ../../../helpers/zpu_med1.vhdl
+vhdl zpu ../../../devices/txt_util.vhdl
+vhdl zpu ../../../devices/phi_io.vhdl
+vhdl zpu ../../../devices/timer.vhdl
+vhdl zpu ../../../devices/gpio.vhdl
+vhdl zpu ../../../devices/rx_unit.vhdl
+vhdl zpu ../../../devices/tx_unit.vhdl
+vhdl zpu ../../../devices/br_gen.vhdl
+vhdl zpu ../../../devices/trace.vhdl
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut new file mode 100644 index 0000000..4bf13c6 --- /dev/null +++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut @@ -0,0 +1,22 @@ +-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g ConfigRate:1
+-g ProgPin:PullUp
+-g DonePin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g DCMShutdown:Disable
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.xst b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.xst new file mode 100644 index 0000000..d357860 --- /dev/null +++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.xst @@ -0,0 +1,56 @@ +set -tmpdir "tmp"
+set -xsthdpdir "xst"
+run
+-ifn ../synthesis_config/top.prj
+-ifmt mixed
+-ofn top
+-ofmt NGC
+-p xc3s500e-4-fg320
+-top top
+-opt_mode Speed
+-opt_level 1
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract Yes
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-auto_bram_packing NO
+-mux_extract Yes
+-resource_sharing YES
+-async_to_sync NO
+-mult_style Auto
+-iobuf YES
+-max_fanout 500
+-bufg 24
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Yes
+-use_sync_set Yes
+-use_sync_reset Yes
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top.vhd b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top.vhd new file mode 100644 index 0000000..4adc18b --- /dev/null +++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top.vhd @@ -0,0 +1,464 @@ +-- top module of
+-- Spartan-3E Starter Kit Board
+--
+-- using following external connections:
+-- rotary pushbutton as reset
+-- LEDs for output
+-- RS232 (DCE, the left one)
+--
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library zpu;
+use zpu.zpupkg.all; -- zpu_dbgo_t
+
+library unisim;
+use unisim.vcomponents.dcm_sp;
+
+
+entity top is
+ port (
+ -- pragma translate_off
+ stop_simulation : out std_logic;
+ -- pragma translate_on
+ --
+ -- Analog-to-Digital Converter (ADC)
+ ad_conv : out std_logic;
+ -- Programmable Gain Amplifier (AMP)
+ amp_cs : out std_logic; -- active low chip select
+ amp_dout : in std_logic;
+ amp_shdn : out std_logic; -- active high shutdown, reset
+ -- Pushbuttons (BTN)
+ btn_east : in std_logic;
+ btn_north : in std_logic;
+ btn_south : in std_logic;
+ btn_west : in std_logic;
+ -- Clock inputs (CLK)
+ clk_50mhz : in std_logic;
+ clk_aux : in std_logic;
+ clk_sma : in std_logic;
+ -- Digital-to-Analog Converter (DAC)
+ dac_clr : out std_logic; -- async, active low reset input
+ dac_cs : out std_logic; -- active low chip select, conv start with rising edge
+ -- 1-Wire Secure EEPROM (DS)
+ ds_wire : inout std_logic;
+ -- Ethernet PHY (E)
+ e_col : in std_logic; -- MII collision detect
+ e_crs : in std_logic; -- carrier sense
+ e_mdc : out std_logic; -- management clock
+ e_mdio : inout std_logic; -- management data io
+ e_rx_clk : in std_logic; -- receive clock 25MHz@100BaseTx or 2.5MHz@10Base-T
+ e_rx_dv : in std_logic; -- receive data valid
+ e_rxd : in std_logic_vector(3 downto 0);
+ e_rx_er : in std_logic;
+ e_tx_clk : in std_logic; -- transmit clock 25MHz@100BaseTx or 2.5MHz@10Base-T
+ e_tx_en : out std_logic; -- transmit enable
+ e_txd : out std_logic_vector(3 downto 0);
+ e_tx_er : out std_logic;
+ -- FPGA Configuration Mode, INIT_B Pins (FPGA)
+ fpga_m0 : inout std_logic;
+ fpga_m1 : inout std_logic;
+ fpga_m2 : inout std_logic;
+ fpga_init_b : inout std_logic;
+ fpga_rdwr_b : in std_logic;
+ fpga_hswap : in std_logic;
+ -- FX2 Connector (FX2)
+ fx2_clkin : inout std_logic;
+ fx2_clkio : inout std_logic;
+ fx2_clkout : inout std_logic;
+ fx2_io : inout std_logic_vector(40 downto 1);
+ -- These are shared connections with the FX2 connector
+ --j1 : inout std_logic_vector(3 downto 0);
+ --j2 : inout std_logic_vector(3 downto 0);
+ --j4 : inout std_logic_vector(3 downto 0);
+ --led : out std_logic_vector(7 downto 0);
+ -- Character LCD (LCD)
+ lcd_e : out std_logic;
+ lcd_rs : out std_logic;
+ lcd_rw : out std_logic;
+ -- LCD data connections are shared with StrataFlash connections SF_D<11:8>
+ --sf_d : inout std_ulogic_vector(11 downto 8);
+ -- PS/2 Mouse/Keyboard Port (PS2)
+ ps2_clk : inout std_logic;
+ ps2_data : inout std_logic;
+ -- Rotary Pushbutton Switch (ROT)
+ rot_a : in std_logic;
+ rot_b : in std_logic;
+ rot_center : in std_logic;
+ -- RS-232 Serial Ports (RS232)
+ rs232_dce_rxd : in std_logic;
+ rs232_dce_txd : out std_logic;
+ rs232_dte_rxd : in std_logic;
+ rs232_dte_txd : out std_logic;
+ -- DDR SDRAM (SD) (I/O Bank 3, VCCO=2.5V)
+ sd_a : out std_logic_vector(12 downto 0); -- address inputs
+ sd_dq : inout std_logic_vector(15 downto 0); -- data io
+ sd_ba : out std_logic_vector(1 downto 0); -- bank address inputs
+ sd_ras : out std_logic; -- command output
+ sd_cas : out std_logic; -- command output
+ sd_we : out std_logic; -- command output
+ sd_udm : out std_logic; -- data mask
+ sd_ldm : out std_logic; -- data mask
+ sd_udqs : inout std_logic; -- data strobe
+ sd_ldqs : inout std_logic; -- data strobe
+ sd_cs : out std_logic; -- active low chip select
+ sd_cke : out std_logic; -- active high clock enable
+ sd_ck_n : out std_logic; -- differential clock
+ sd_ck_p : out std_logic; -- differential clock
+ -- Path to allow connection to top DCM connection
+ sd_ck_fb : in std_logic;
+ -- Intel StrataFlash Parallel NOR Flash (SF)
+ sf_a : out std_logic_vector(23 downto 0); -- sf_a<24> = fx_io32
+ sf_byte : out std_logic;
+ sf_ce0 : out std_logic;
+ sf_d : inout std_logic_vector(15 downto 1);
+ sf_oe : out std_logic;
+ sf_sts : in std_logic;
+ sf_we : out std_logic;
+ -- STMicro SPI serial Flash (SPI)
+ spi_mosi : out std_logic; -- master out slave in
+ spi_miso : in std_logic; -- master in slave out
+ spi_sck : out std_logic; -- clock
+ spi_ss_b : out std_logic; -- active low slave select
+ spi_alt_cs_jp11 : out std_logic;
+ -- Slide Switches (SW)
+ sw : in std_logic_vector(3 downto 0);
+ -- VGA Port (VGA)
+ vga_blue : out std_logic;
+ vga_green : out std_logic;
+ vga_hsync : out std_logic;
+ vga_red : out std_logic;
+ vga_vsync : out std_logic;
+ -- Xilinx CPLD (XC)
+ xc_cmd : out std_logic_vector(1 downto 0);
+ xc_cpld_en : out std_logic;
+ xc_d : inout std_logic_vector(2 downto 0);
+ xc_trig : in std_logic;
+ xc_gck0 : inout std_logic;
+ gclk10 : inout std_logic
+ );
+end entity top;
+
+
+architecture rtl of top is
+
+ ---------------------------
+ -- type declarations
+ type zpu_type is (zpu_small, zpu_medium);
+
+ ---------------------------
+ -- constant declarations
+ constant zpu_flavour : zpu_type := zpu_medium; -- choose your flavour HERE
+ -- modify frequency here
+ constant clk_multiply : positive := 3; -- 2 for small, 3 for medium
+ constant clk_divide : positive := 2; -- 1 for small, 2 for medium
+ --
+ constant word_size_c : natural := 32; -- 32 bits data path
+ constant addr_w_c : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O
+
+
+ constant spi_ss_b_disable : std_ulogic := '1'; -- 1 = disable SPI serial flash
+ constant dac_cs_disable : std_ulogic := '1'; -- 1 = disable DAC
+ constant amp_cs_disable : std_ulogic := '1'; -- 1 = disable programmable pre-amplifier
+ constant ad_conv_disable : std_ulogic := '0'; -- 0 = disable ADC
+ constant sf_ce0_disable : std_ulogic := '1';
+ constant fpga_init_b_disable : std_ulogic := '1'; -- 1 = disable pflatform flash PROM
+ --
+ -- connect ldc to fpga
+ constant sf_ce0_lcd_to_fpga : std_ulogic := '1';
+ --
+ constant clk_frequency : positive := 50; -- input frequency for correct calculation
+
+
+ ---------------------------
+ -- component declarations
+ component zpu_small1 is
+ generic (
+ word_size : natural := 32; -- 32 bits data path
+ d_care_val : std_logic := '0'; -- Fill value
+ clk_freq : positive := 50; -- 50 MHz clock
+ brate : positive := 115200; -- RS232 baudrate
+ addr_w : natural := 16; -- 16 bits address space=64 kB, 32 kB I/O
+ bram_w : natural := 15 -- 15 bits RAM space=32 kB
+ );
+ port (
+ clk_i : in std_logic; -- CPU clock
+ rst_i : in std_logic; -- Reset
+ break_o : out std_logic; -- Break executed
+ dbg_o : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o : out std_logic; -- UART Tx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end component zpu_small1;
+
+ component zpu_med1 is
+ generic(
+ word_size : natural := 32; -- 32 bits data path
+ d_care_val : std_logic := '0'; -- Fill value
+ clk_freq : positive := 50; -- 50 MHz clock
+ brate : positive := 115200; -- RS232 baudrate
+ addr_w : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O
+ bram_w : natural := 15 -- 15 bits RAM space=32 kB
+ );
+ port(
+ clk_i : in std_logic; -- CPU clock
+ rst_i : in std_logic; -- Reset
+ break_o : out std_logic; -- Break executed
+ dbg_o : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o : out std_logic; -- UART Tx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end component zpu_med1;
+
+
+ ---------------------------
+ -- signal declarations
+ signal dcm_sp_i0_clk0 : std_ulogic;
+ signal dcm_sp_i0_clkfx : std_ulogic;
+ signal clk_fb : std_ulogic;
+ signal clk : std_ulogic;
+ --
+ signal reset_shift_reg : std_ulogic_vector(3 downto 0);
+ signal reset_sync : std_ulogic;
+ --
+ signal zpu_i0_dbg : zpu_dbgo_t; -- Debug info
+ signal zpu_i0_break : std_logic;
+ --
+ signal gpio_in : std_logic_vector(31 downto 0);
+ signal zpu_i0_gpio_out : std_logic_vector(31 downto 0);
+ signal zpu_i0_gpio_dir : std_logic_vector(31 downto 0);
+
+ ---------------------------
+ -- alias declarations
+ alias led : std_logic_vector(7 downto 0) is fx2_io(20 downto 13);
+
+
+begin
+
+ -- default output drivers
+ -- to pass bitgen DRC
+ -- outputs used by design are commented
+ --
+ ad_conv <= ad_conv_disable;
+ amp_cs <= amp_cs_disable;
+ amp_shdn <= '1';
+ --
+ dac_clr <= '0';
+ dac_cs <= dac_cs_disable;
+ --
+ ds_wire <= 'Z';
+ --
+ e_txd(3 downto 0) <= (others => '1');
+ e_tx_en <= '0';
+ e_tx_er <= '0';
+ e_mdc <= '1';
+ e_mdio <= 'Z';
+ --
+ fpga_m0 <= 'Z';
+ fpga_m1 <= 'Z';
+ fpga_m2 <= 'Z';
+ fpga_init_b <= fpga_init_b_disable;
+ --
+ fx2_clkin <= 'Z';
+ fx2_clkio <= 'Z';
+ fx2_clkout <= 'Z';
+ fx2_io <= (others => 'Z');
+ --
+ lcd_e <= '0';
+ lcd_rs <= '0';
+ lcd_rw <= '0';
+ --
+ ps2_clk <= 'Z';
+ ps2_data <= 'Z';
+ --
+ --rs232_dce_txd <= '1';
+ rs232_dte_txd <= '1';
+ --
+ sd_a <= (others => '1');
+ sd_dq <= (others => 'Z');
+ sd_ba <= (others => '1');
+ sd_ras <= '0';
+ sd_cas <= '0';
+ sd_we <= '0';
+ sd_udm <= '1';
+ sd_ldm <= '1';
+ sd_udqs <= '1';
+ sd_ldqs <= '1';
+ sd_cs <= '1';
+ sd_cke <= '1';
+ sd_ck_n <= '0';
+ sd_ck_p <= '1';
+ --
+ sf_a <= (others => '0');
+ sf_byte <= '0';
+ sf_ce0 <= sf_ce0_lcd_to_fpga;
+ sf_d <= (others => 'Z');
+ sf_oe <= '1';
+ sf_we <= '0';
+ --
+ spi_mosi <= '0';
+ spi_sck <= '0';
+ spi_ss_b <= spi_ss_b_disable;
+ spi_alt_cs_jp11 <= spi_ss_b_disable;
+ --
+ vga_red <= '0';
+ vga_green <= '0';
+ vga_blue <= '0';
+ vga_hsync <= '0';
+ vga_vsync <= '0';
+ --
+ xc_cmd <= "00";
+ xc_d <= (others => 'Z');
+ xc_cpld_en <= '0';
+ xc_gck0 <= 'Z';
+ gclk10 <= 'Z';
+ -- led out
+ --fx2_io(20 downto 13) <= (others => '0');
+
+
+ -- digital clock manager (DCM)
+ -- to generate higher/other system clock frequencys
+ dcm_sp_i0 : dcm_sp
+ generic map (
+ startup_wait => true, -- wait with DONE till locked
+ clkfx_multiply => clk_multiply,
+ clkfx_divide => clk_divide,
+ clk_feedback => "1X"
+ )
+ port map (
+ clkin => clk_50mhz,
+ clk0 => dcm_sp_i0_clk0,
+ clkfx => dcm_sp_i0_clkfx,
+ clkfb => clk_fb
+ );
+
+ clk_fb <= dcm_sp_i0_clk0;
+ clk <= dcm_sp_i0_clkfx;
+
+
+ -- reset synchronizer
+ -- generate synchronous reset
+ reset_synchronizer : process(clk, rot_center)
+ begin
+ if rot_center = '1' then
+ reset_shift_reg <= (others => '1');
+ elsif rising_edge(clk) then
+ reset_shift_reg <= reset_shift_reg(reset_shift_reg'high-1 downto 0) & '0';
+ end if;
+ end process;
+ reset_sync <= reset_shift_reg(reset_shift_reg'high);
+
+
+ -- select instance of zpu
+ zpu_i0_small : if zpu_flavour = zpu_small generate
+ zpu_i0 : zpu_small1
+ generic map (
+ addr_w => addr_w_c,
+ word_size => word_size_c,
+ clk_freq => clk_frequency * clk_multiply / clk_divide
+ )
+ port map (
+ clk_i => clk, -- : in std_logic; -- CPU clock
+ rst_i => reset_sync, -- : in std_logic; -- Reset
+ break_o => zpu_i0_break, -- : out std_logic; -- Break executed
+ dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o => rs232_dce_txd, -- : out std_logic; -- UART Tx
+ rs232_rx_i => rs232_dce_rxd, -- : in std_logic -- UART Rx
+ gpio_in => gpio_in, -- : in std_logic_vector(31 downto 0);
+ gpio_out => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
+ gpio_dir => zpu_i0_gpio_dir -- : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end generate zpu_i0_small;
+
+ zpu_i0_medium : if zpu_flavour = zpu_medium generate
+ zpu_i0 : zpu_med1
+ generic map (
+ addr_w => addr_w_c,
+ word_size => word_size_c,
+ clk_freq => clk_frequency * clk_multiply / clk_divide
+ )
+ port map (
+ clk_i => clk, -- : in std_logic; -- CPU clock
+ rst_i => reset_sync, -- : in std_logic; -- Reset
+ break_o => zpu_i0_break, -- : out std_logic; -- Break executed
+ dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o => rs232_dce_txd, -- : out std_logic; -- UART Tx
+ rs232_rx_i => rs232_dce_rxd, -- : in std_logic -- UART Rx
+ gpio_in => gpio_in, -- : in std_logic_vector(31 downto 0);
+ gpio_out => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
+ gpio_dir => zpu_i0_gpio_dir -- : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end generate zpu_i0_medium;
+
+
+ -- pragma translate_off
+ stop_simulation <= zpu_i0_break;
+
+
+ trace_mod : trace
+ generic map (
+ addr_w => addr_w_c,
+ word_size => word_size_c,
+ log_file => "zpu_trace.log"
+ )
+ port map (
+ clk_i => clk,
+ dbg_i => zpu_i0_dbg,
+ stop_i => zpu_i0_break,
+ busy_i => '0'
+ );
+ -- pragma translate_on
+
+
+ -- assign GPIOs
+ -- no bidirectional pins (e.g. headers), so
+ -- gpio_dir is unused
+ --
+ -- bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
+ --
+ -- in -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ -- out -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ --
+ --
+ -- bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+ --
+ -- in -- -- -- -- sw(3.....0) -- ra rb rc be bn bs bw
+ -- out -- -- -- -- -- -- -- -- led(7................0)
+
+ gpio_in <= ((11) => sw(3),
+ (10) => sw(2),
+ ( 9) => sw(1),
+ ( 8) => sw(0),
+ --
+ ( 6) => rot_a,
+ ( 5) => rot_b,
+ ( 4) => rot_center,
+ --
+ ( 3) => btn_east,
+ ( 2) => btn_north,
+ ( 1) => btn_south,
+ ( 0) => btn_west,
+ others => '0');
+
+
+ -- switch on all LEDs in case of break
+ process
+ begin
+ wait until rising_edge(clk);
+ led <= zpu_i0_gpio_out(7 downto 0);
+ if zpu_i0_break = '1' then
+ led <= (others => '1');
+ end if;
+ end process;
+
+
+
+end architecture rtl;
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top_tb.vhd b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top_tb.vhd new file mode 100644 index 0000000..d62bed9 --- /dev/null +++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/top_tb.vhd @@ -0,0 +1,281 @@ +-- testbench for
+-- Digilent Spartan 3E Starter Board
+--
+-- includes "model" for clock generation
+-- simulate press on Rotary Pushbutton Switch as reset
+--
+-- place models for external components (PHY, SDRAM) in this file
+--
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity top_tb is
+end entity top_tb;
+
+architecture testbench of top_tb is
+
+ ---------------------------
+ -- constant declarations
+ constant clk_50mhz_period : time := 1 sec / 50_000_000; -- 50 MHz
+
+
+ ---------------------------
+ -- signal declarations
+ signal simulation_run : boolean := true;
+ signal tb_stop_simulation : std_logic;
+ --
+ -- Analog-to-Digital Converter (ADC)
+ signal tb_ad_conv : std_logic;
+ -- Programmable Gain Amplifier (AMP)
+ signal tb_amp_cs : std_logic; -- active low chip select
+ signal tb_amp_dout : std_logic := '1';
+ signal tb_amp_shdn : std_logic; -- active high shutdown, reset
+ -- Pushbuttons (BTN)
+ signal tb_btn_east : std_logic := '0';
+ signal tb_btn_north : std_logic := '0';
+ signal tb_btn_south : std_logic := '0';
+ signal tb_btn_west : std_logic := '0';
+ -- Clock inputs (CLK)
+ signal tb_clk_50mhz : std_logic := '0';
+ signal tb_clk_aux : std_logic := '0';
+ signal tb_clk_sma : std_logic := '0';
+ -- Digital-to-Analog Converter (DAC)
+ signal tb_dac_clr : std_logic; -- async, active low reset input
+ signal tb_dac_cs : std_logic; -- active low chip select, conv start with rising edge
+ -- 1-Wire Secure EEPROM (DS)
+ signal tb_ds_wire : std_logic;
+ -- Ethernet PHY (E)
+ signal tb_e_col : std_logic := '0'; -- MII collision detect
+ signal tb_e_crs : std_logic := '0'; -- carrier sense
+ signal tb_e_mdc : std_logic; -- management clock
+ signal tb_e_mdio : std_logic; -- management data io
+ signal tb_e_rx_clk : std_logic := '0'; -- receive clock 25MHz@100BaseTx or 2.5MHz@10Base-T
+ signal tb_e_rx_dv : std_logic := '0'; -- receive data valid
+ signal tb_e_rxd : std_logic_vector(3 downto 0) := (others => '0');
+ signal tb_e_rx_er : std_logic := '0';
+ signal tb_e_tx_clk : std_logic := '0'; -- transmit clock 25MHz@100BaseTx or 2.5MHz@10Base-T
+ signal tb_e_tx_en : std_logic; -- transmit enable
+ signal tb_e_txd : std_logic_vector(3 downto 0);
+ signal tb_e_tx_er : std_logic;
+ -- FPGA Configuration Mode, INIT_B Pins (FPGA)
+ signal tb_fpga_m0 : std_logic;
+ signal tb_fpga_m1 : std_logic;
+ signal tb_fpga_m2 : std_logic;
+ signal tb_fpga_init_b : std_logic;
+ signal tb_fpga_rdwr_b : std_logic := '0';
+ signal tb_fpga_hswap : std_logic := '0';
+ -- FX2 Connector (FX2)
+ signal tb_fx2_clkin : std_logic;
+ signal tb_fx2_clkio : std_logic;
+ signal tb_fx2_clkout : std_logic;
+ signal tb_fx2_io : std_logic_vector(40 downto 1);
+ -- Character LCD (LCD)
+ signal tb_lcd_e : std_logic;
+ signal tb_lcd_rs : std_logic;
+ signal tb_lcd_rw : std_logic;
+ -- LCD data connections are shared with StrataFlash connections SF_D<11:8>
+ -- PS/2 Mouse/Keyboard Port (PS2)
+ signal tb_ps2_clk : std_logic;
+ signal tb_ps2_data : std_logic;
+ -- Rotary Pushbutton Switch (ROT)
+ signal tb_rot_a : std_logic := '0';
+ signal tb_rot_b : std_logic := '0';
+ signal tb_rot_center : std_logic; -- use as reset
+ -- RS-232 Serial Ports (RS232)
+ signal tb_rs232_dce_rxd : std_logic := '1';
+ signal tb_rs232_dce_txd : std_logic;
+ signal tb_rs232_dte_rxd : std_logic := '1';
+ signal tb_rs232_dte_txd : std_logic;
+ -- DDR SDRAM (SD) (I/O Bank 3, VCCO=2.5V)
+ signal tb_sd_a : std_logic_vector(12 downto 0); -- address inputs
+ signal tb_sd_dq : std_logic_vector(15 downto 0); -- data io
+ signal tb_sd_ba : std_logic_vector(1 downto 0); -- bank address inputs
+ signal tb_sd_ras : std_logic; -- command output
+ signal tb_sd_cas : std_logic; -- command output
+ signal tb_sd_we : std_logic; -- command output
+ signal tb_sd_udm : std_logic; -- data mask
+ signal tb_sd_ldm : std_logic; -- data mask
+ signal tb_sd_udqs : std_logic; -- data strobe
+ signal tb_sd_ldqs : std_logic; -- data strobe
+ signal tb_sd_cs : std_logic; -- active low chip select
+ signal tb_sd_cke : std_logic; -- active high clock enable
+ signal tb_sd_ck_n : std_logic; -- differential clock
+ signal tb_sd_ck_p : std_logic; -- differential clock
+ -- Path to allow connection to top DCM connection
+ signal tb_sd_ck_fb : std_logic;
+ -- Intel StrataFlash Parallel NOR Flash (SF)
+ signal tb_sf_a : std_logic_vector(23 downto 0); -- sf_a<24> = fx_io32 :-(
+ signal tb_sf_byte : std_logic;
+ signal tb_sf_ce0 : std_logic;
+ signal tb_sf_d : std_logic_vector(15 downto 1);
+ signal tb_sf_oe : std_logic;
+ signal tb_sf_sts : std_logic := '0';
+ signal tb_sf_we : std_logic;
+ -- STMicro SPI serial Flash (SPI)
+ signal tb_spi_mosi : std_logic; -- master out slave in
+ signal tb_spi_miso : std_logic := '0'; -- master in slave out
+ signal tb_spi_sck : std_logic; -- clock
+ signal tb_spi_ss_b : std_logic; -- active low slave select
+ signal tb_spi_alt_cs_jp11 : std_logic;
+ -- Slide Switches (SW)
+ signal tb_sw : std_logic_vector(3 downto 0) := (others => '0');
+ -- VGA Port (VGA)
+ signal tb_vga_blue : std_logic;
+ signal tb_vga_green : std_logic;
+ signal tb_vga_hsync : std_logic;
+ signal tb_vga_red : std_logic;
+ signal tb_vga_vsync : std_logic;
+ -- Xilinx CPLD (XC)
+ signal tb_xc_cmd : std_logic_vector(1 downto 0);
+ signal tb_xc_cpld_en : std_logic;
+ signal tb_xc_d : std_logic_vector(2 downto 0);
+ signal tb_xc_trig : std_logic := '0';
+ signal tb_xc_gck0 : std_logic;
+ signal tb_gclk10 : std_logic;
+
+
+begin
+
+
+ -- generate clock
+ tb_clk_50mhz <= not tb_clk_50mhz after clk_50mhz_period / 2 when simulation_run;
+
+ -- generate reset
+ tb_rot_center <= '1', '0' after 6.66 * clk_50mhz_period;
+
+
+ -- clock feedback for SD-RAM (on board)
+ tb_sd_ck_fb <= tb_sd_ck_p;
+
+ -- simulate keypress
+ tb_btn_north <= '0', '1' after 55 us, '0' after 56 us;
+
+ -- dut
+ top_i0 : entity work.top
+ port map (
+ stop_simulation => tb_stop_simulation, -- : out std_logic;
+ -- Analog-to-Digital Converter (ADC)
+ ad_conv => tb_ad_conv, -- : out std_logic;
+ -- Programmable Gain Amplifier (AMP)
+ amp_cs => tb_amp_cs, -- : out std_logic;
+ amp_dout => tb_amp_dout, -- : in std_logic;
+ amp_shdn => tb_amp_shdn, -- : out std_logic;
+ -- Pushbuttons (BTN)
+ btn_east => tb_btn_east, -- : in std_logic;
+ btn_north => tb_btn_north, -- : in std_logic;
+ btn_south => tb_btn_south, -- : in std_logic;
+ btn_west => tb_btn_west, -- : in std_logic;
+ -- Clock inputs (CLK)
+ clk_50mhz => tb_clk_50mhz, -- : in std_logic;
+ clk_aux => tb_clk_aux, -- : in std_logic;
+ clk_sma => tb_clk_sma, -- : in std_logic;
+ -- Digital-to-Analog Converter (DAC)
+ dac_clr => tb_dac_clr, -- : out std_logic;
+ dac_cs => tb_dac_cs, -- : out std_logic;
+ -- 1-Wire Secure EEPROM (DS)
+ ds_wire => tb_ds_wire, -- : inout std_logic;
+ -- Ethernet PHY (E)
+ e_col => tb_e_col, -- : in std_logic;
+ e_crs => tb_e_crs, -- : in std_logic;
+ e_mdc => tb_e_mdc, -- : out std_logic;
+ e_mdio => tb_e_mdio, -- : inout std_logic;
+ e_rx_clk => tb_e_rx_clk, -- : in std_logic;
+ e_rx_dv => tb_e_rx_dv, -- : in std_logic;
+ e_rxd => tb_e_rxd, -- : in std_logic_vector(3 downto 0);
+ e_rx_er => tb_e_rx_er, -- : in std_logic;
+ e_tx_clk => tb_e_tx_clk, -- : in std_logic;
+ e_tx_en => tb_e_tx_en, -- : out std_logic;
+ e_txd => tb_e_txd, -- : out std_logic_vector(3 downto 0);
+ e_tx_er => tb_e_tx_er, -- : out std_logic;
+ -- FPGA Configuration Mode, INIT_B Pins (FPGA)
+ fpga_m0 => tb_fpga_m0, -- : inout std_logic;
+ fpga_m1 => tb_fpga_m1, -- : inout std_logic;
+ fpga_m2 => tb_fpga_m2, -- : inout std_logic;
+ fpga_init_b => tb_fpga_init_b, -- : inout std_logic;
+ fpga_rdwr_b => tb_fpga_rdwr_b, -- : in std_logic;
+ fpga_hswap => tb_fpga_hswap, -- : in std_logic;
+ -- FX2 Connector (FX2)
+ fx2_clkin => tb_fx2_clkin, -- : inout std_logic;
+ fx2_clkio => tb_fx2_clkio, -- : inout std_logic;
+ fx2_clkout => tb_fx2_clkout, -- : inout std_logic;
+ fx2_io => tb_fx2_io, -- : inout std_logic_vector(40 downto 1);
+ -- Character LCD (LCD)
+ lcd_e => tb_lcd_e, -- : out std_logic;
+ lcd_rs => tb_lcd_rs, -- : out std_logic;
+ lcd_rw => tb_lcd_rw, -- : out std_logic;
+ -- LCD data connections are shared with StrataFlash connections SF_D<11:8>
+ -- PS/2 Mouse/Keyboard Port (PS2)
+ ps2_clk => tb_ps2_clk, -- : inout std_logic;
+ ps2_data => tb_ps2_data, -- : inout std_logic;
+ -- Rotary Pushbutton Switch (ROT)
+ rot_a => tb_rot_a, -- : in std_logic;
+ rot_b => tb_rot_b, -- : in std_logic;
+ rot_center => tb_rot_center, -- : in std_logic;
+ -- RS-232 Serial Ports (RS232)
+ rs232_dce_rxd => tb_rs232_dce_rxd, -- : in std_logic;
+ rs232_dce_txd => tb_rs232_dce_txd, -- : out std_logic;
+ rs232_dte_rxd => tb_rs232_dte_rxd, -- : in std_logic;
+ rs232_dte_txd => tb_rs232_dte_txd, -- : out std_logic;
+ -- DDR SDRAM (SD) (I/O Bank 3, VCCO=2.5V)
+ sd_a => tb_sd_a, -- : out std_logic_vector(12 downto 0);
+ sd_dq => tb_sd_dq, -- : inout std_logic_vector(15 downto 0);
+ sd_ba => tb_sd_ba, -- : out std_logic_vector(1 downto 0);
+ sd_ras => tb_sd_ras, -- : out std_logic;
+ sd_cas => tb_sd_cas, -- : out std_logic;
+ sd_we => tb_sd_we, -- : out std_logic;
+ sd_udm => tb_sd_udm, -- : out std_logic;
+ sd_ldm => tb_sd_ldm, -- : out std_logic;
+ sd_udqs => tb_sd_udqs, -- : inout std_logic;
+ sd_ldqs => tb_sd_ldqs, -- : inout std_logic;
+ sd_cs => tb_sd_cs, -- : out std_logic;
+ sd_cke => tb_sd_cke, -- : out std_logic;
+ sd_ck_n => tb_sd_ck_n, -- : out std_logic;
+ sd_ck_p => tb_sd_ck_p, -- : out std_logic;
+ -- Path to allow connection to top DCM connection
+ sd_ck_fb => tb_sd_ck_fb, -- : in std_logic;
+ -- Intel StrataFlash Parallel NOR Flash (SF)
+ sf_a => tb_sf_a, -- : out std_logic_vector(23 downto 0);
+ sf_byte => tb_sf_byte, -- : out std_logic;
+ sf_ce0 => tb_sf_ce0, -- : out std_logic;
+ sf_d => tb_sf_d, -- : inout std_logic_vector(15 downto 1);
+ sf_oe => tb_sf_oe, -- : out std_logic;
+ sf_sts => tb_sf_sts, -- : in std_logic;
+ sf_we => tb_sf_we, -- : out std_logic;
+ -- STMicro SPI serial Flash (SPI)
+ spi_mosi => tb_spi_mosi, -- : out std_logic;
+ spi_miso => tb_spi_miso, -- : in std_logic;
+ spi_sck => tb_spi_sck, -- : out std_logic;
+ spi_ss_b => tb_spi_ss_b, -- : out std_logic;
+ spi_alt_cs_jp11 => tb_spi_alt_cs_jp11, -- : out std_logic;
+ -- Slide Switches (SW)
+ sw => tb_sw, -- : in std_logic_vector(3 downto 0);
+ -- VGA Port (VGA)
+ vga_blue => tb_vga_blue, -- : out std_logic;
+ vga_green => tb_vga_green, -- : out std_logic;
+ vga_hsync => tb_vga_hsync, -- : out std_logic;
+ vga_red => tb_vga_red, -- : out std_logic;
+ vga_vsync => tb_vga_vsync, -- : out std_logic;
+ -- Xilinx CPLD (XC)
+ xc_cmd => tb_xc_cmd, -- : out std_logic_vector(1 downto 0);
+ xc_cpld_en => tb_xc_cpld_en, -- : out std_logic;
+ xc_d => tb_xc_d, -- : inout std_logic_vector(2 downto 0);
+ xc_trig => tb_xc_trig, -- : in std_logic;
+ xc_gck0 => tb_xc_gck0, -- : inout std_logic;
+ gclk10 => tb_gclk10 -- : inout std_logic
+ );
+
+
+ -- check for simulation stopping
+ process (tb_stop_simulation)
+ begin
+ if tb_stop_simulation = '1' then
+ report "Simulation end." severity note;
+ simulation_run <= false;
+ end if;
+ end process;
+
+
+end architecture testbench;
diff --git a/zpu/hdl/zealot/fpga/dmips_med1.vhdl b/zpu/hdl/zealot/fpga/dmips_med1.vhdl new file mode 100644 index 0000000..b95016c --- /dev/null +++ b/zpu/hdl/zealot/fpga/dmips_med1.vhdl @@ -0,0 +1,119 @@ +------------------------------------------------------------------------------ +---- ---- +---- ZPU Medium connection to the FPGA pins ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- This module connects the ZPU_Med1 (zpu_med1.vhdl) core to a Spartan ---- +---- 3 1500 Xilinx FPGA available in the GR-XC3S board from Pender. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the GPL license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: DMIPS_Med1(FPGA) (Entity and architecture) ---- +---- File name: dmips_med1.vhdl ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: work ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- zpu.zpu_pkg ---- +---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: N/A ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library zpu; +use zpu.zpupkg.all; + +entity DMIPS_Med1 is + generic( + WORD_SIZE : natural:=32; -- 32 bits data path + D_CARE_VAL : std_logic:='0'; -- Fill value, I got better results with it + CLK_FREQ : positive:=50; -- 50 MHz clock + BRATE : positive:=115200; -- RS-232 baudrate + ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O + BRAM_W : natural:=15); -- 15 bits RAM space=32 kB + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic); -- UART Rx + + constant BRD_PB1_I : string:="D19"; -- SWITCH8==S2 + constant BRD_CLK1_I : string:="AA12"; -- 50 MHz clock + --constant BRD_CLK1_I : string:="AB12"; -- 40 MHz clock + -- UART: direct 1:1 cable + constant BRD_TX_O : string:="L4"; -- UART 1 (J1) TXD1 DB9 pin 2 + constant BRD_RX_I : string:="L3"; -- UART 1 (J1) RXD1 DB9 pin 3 + + ------------ + -- Pinout -- + ------------ + attribute LOC : string; + attribute IOSTANDARD : string; + constant IOSTD : string:="LVTTL"; + + attribute LOC of rst_i : signal is BRD_PB1_I; + attribute IOSTANDARD of rst_i : signal is IOSTD; + attribute LOC of clk_i : signal is BRD_CLK1_I; + attribute LOC of rs232_tx_o : signal is BRD_TX_O; + attribute IOSTANDARD of rs232_tx_o : signal is IOSTD; + attribute LOC of rs232_rx_i : signal is BRD_RX_I; + attribute IOSTANDARD of rs232_rx_i : signal is IOSTD; +end entity DMIPS_Med1; + +architecture FPGA of DMIPS_Med1 is + component ZPU_Med1 is + generic( + WORD_SIZE : natural:=32; -- 32 bits data path + D_CARE_VAL : std_logic:='X'; -- Fill value + CLK_FREQ : positive:=50; -- 50 MHz clock + BRATE : positive:=9600; -- RS232 baudrate + ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O + BRAM_W : natural:=15); -- 15 bits RAM space=32 kB + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + break_o : out std_logic; -- Break executed + dbg_o : out zpu_dbgo_t; -- Debug info + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic; -- UART Rx + gpio_in : in std_logic_vector(31 downto 0); + gpio_out : out std_logic_vector(31 downto 0); + gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out + ); + end component ZPU_Med1; +begin + zpu : ZPU_Med1 + generic map( + WORD_SIZE => WORD_SIZE, D_CARE_VAL => D_CARE_VAL, + CLK_FREQ => CLK_FREQ, BRATE => BRATE, ADDR_W => ADDR_W, + BRAM_W => BRAM_W) + port map( + clk_i => clk_i, rst_i => rst_i, rs232_tx_o => rs232_tx_o, + rs232_rx_i => rs232_rx_i, dbg_o => open, gpio_in => (others => '0')); +end architecture FPGA; -- Entity: DMIPS_Med1 + diff --git a/zpu/hdl/zealot/fpga/dmips_small1.vhdl b/zpu/hdl/zealot/fpga/dmips_small1.vhdl new file mode 100644 index 0000000..6edec00 --- /dev/null +++ b/zpu/hdl/zealot/fpga/dmips_small1.vhdl @@ -0,0 +1,120 @@ +------------------------------------------------------------------------------ +---- ---- +---- ZPU Small connection to the FPGA pins ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- This module connects the ZPU_Small1 (zpu_small1.vhdl) core to a ---- +---- Spartan 3 1500 Xilinx FPGA available in the GR-XC3S board from ---- +---- Pender. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the GPL license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: DMIPS_Small1(FPGA) (Entity and architecture) ---- +---- File name: dmips_small1.vhdl ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: work ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- zpu.zpu_pkg ---- +---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: N/A ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library zpu; +use zpu.zpupkg.all; + +entity DMIPS_Small1 is + generic( + WORD_SIZE : natural:=32; -- 32 bits data path + D_CARE_VAL : std_logic:='0'; -- Fill value, I got better results with it + CLK_FREQ : positive:=50; -- 50 MHz clock + BRATE : positive:=115200; -- RS-232 baudrate + ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O + BRAM_W : natural:=15); -- 15 bits RAM space=32 kB + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic); -- UART Rx + + constant BRD_PB1_I : string:="D19"; -- SWITCH8==S2 + constant BRD_CLK1_I : string:="AA12"; -- 50 MHz clock + --constant BRD_CLK1_I : string:="AB12"; -- 40 MHz clock + -- UART: direct 1:1 cable + constant BRD_TX_O : string:="L4"; -- UART 1 (J1) TXD1 DB9 pin 2 + constant BRD_RX_I : string:="L3"; -- UART 1 (J1) RXD1 DB9 pin 3 + + ------------ + -- Pinout -- + ------------ + attribute LOC : string; + attribute IOSTANDARD : string; + constant IOSTD : string:="LVTTL"; + + attribute LOC of rst_i : signal is BRD_PB1_I; + attribute IOSTANDARD of rst_i : signal is IOSTD; + attribute LOC of clk_i : signal is BRD_CLK1_I; + attribute LOC of rs232_tx_o : signal is BRD_TX_O; + attribute IOSTANDARD of rs232_tx_o : signal is IOSTD; + attribute LOC of rs232_rx_i : signal is BRD_RX_I; + attribute IOSTANDARD of rs232_rx_i : signal is IOSTD; +end entity DMIPS_Small1; + +architecture FPGA of DMIPS_Small1 is + component ZPU_Small1 is + generic( + WORD_SIZE : natural:=32; -- 32 bits data path + D_CARE_VAL : std_logic:='0'; -- Fill value + CLK_FREQ : positive:=50; -- 50 MHz clock + BRATE : positive:=115200; -- RS232 baudrate + ADDR_W : natural:=16; -- 16 bits address space=64 kB, 32 kB I/O + BRAM_W : natural:=15); -- 15 bits RAM space=32 kB + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + break_o : out std_logic; -- Break executed + dbg_o : out zpu_dbgo_t; -- Debug info + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic; -- UART Rx + gpio_in : in std_logic_vector(31 downto 0); + gpio_out : out std_logic_vector(31 downto 0); + gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out + ); + end component ZPU_Small1; +begin + zpu : ZPU_Small1 + generic map( + WORD_SIZE => WORD_SIZE, D_CARE_VAL => D_CARE_VAL, + CLK_FREQ => CLK_FREQ, BRATE => BRATE, ADDR_W => ADDR_W, + BRAM_W => BRAM_W) + port map( + clk_i => clk_i, rst_i => rst_i, rs232_tx_o => rs232_tx_o, + rs232_rx_i => rs232_rx_i, dbg_o => open, gpio_in => (others => '0')); +end architecture FPGA; -- Entity: DMIPS_Small1 + diff --git a/zpu/hdl/zealot/fpga/hello_med1.vhdl b/zpu/hdl/zealot/fpga/hello_med1.vhdl new file mode 100644 index 0000000..5ffea1f --- /dev/null +++ b/zpu/hdl/zealot/fpga/hello_med1.vhdl @@ -0,0 +1,119 @@ +------------------------------------------------------------------------------ +---- ---- +---- ZPU Medium connection to the FPGA pins ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- This module connects the ZPU_Med1 (zpu_med1.vhdl) core to a Spartan ---- +---- 3 1500 Xilinx FPGA available in the GR-XC3S board from Pender. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the GPL license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: Hello_Med1(FPGA) (Entity and architecture) ---- +---- File name: hello_med1.vhdl ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: work ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- zpu.zpu_pkg ---- +---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: N/A ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library zpu; +use zpu.zpupkg.all; + +entity Hello_Med1 is + generic( + WORD_SIZE : natural:=32; -- 32 bits data path + D_CARE_VAL : std_logic:='0'; -- Fill value, I got better results with it + CLK_FREQ : positive:=50; -- 50 MHz clock + BRATE : positive:=115200; -- RS-232 baudrate + ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O + BRAM_W : natural:=14); -- 14 bits RAM space=16 kB + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic); -- UART Rx + + constant BRD_PB1_I : string:="D19"; -- SWITCH8==S2 + constant BRD_CLK1_I : string:="AA12"; -- 50 MHz clock + --constant BRD_CLK1_I : string:="AB12"; -- 40 MHz clock + -- UART: direct 1:1 cable + constant BRD_TX_O : string:="L4"; -- UART 1 (J1) TXD1 DB9 pin 2 + constant BRD_RX_I : string:="L3"; -- UART 1 (J1) RXD1 DB9 pin 3 + + ------------ + -- Pinout -- + ------------ + attribute LOC : string; + attribute IOSTANDARD : string; + constant IOSTD : string:="LVTTL"; + + attribute LOC of rst_i : signal is BRD_PB1_I; + attribute IOSTANDARD of rst_i : signal is IOSTD; + attribute LOC of clk_i : signal is BRD_CLK1_I; + attribute LOC of rs232_tx_o : signal is BRD_TX_O; + attribute IOSTANDARD of rs232_tx_o : signal is IOSTD; + attribute LOC of rs232_rx_i : signal is BRD_RX_I; + attribute IOSTANDARD of rs232_rx_i : signal is IOSTD; +end entity Hello_Med1; + +architecture FPGA of Hello_Med1 is + component ZPU_Med1 is + generic( + WORD_SIZE : natural:=32; -- 32 bits data path + D_CARE_VAL : std_logic:='X'; -- Fill value + CLK_FREQ : positive:=50; -- 50 MHz clock + BRATE : positive:=9600; -- RS232 baudrate + ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O + BRAM_W : natural:=15); -- 15 bits RAM space=32 kB + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + break_o : out std_logic; -- Break executed + dbg_o : out zpu_dbgo_t; -- Debug info + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic; -- UART Rx + gpio_in : in std_logic_vector(31 downto 0); + gpio_out : out std_logic_vector(31 downto 0); + gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out + ); + end component ZPU_Med1; +begin + zpu : ZPU_Med1 + generic map( + WORD_SIZE => WORD_SIZE, D_CARE_VAL => D_CARE_VAL, + CLK_FREQ => CLK_FREQ, BRATE => BRATE, ADDR_W => ADDR_W, + BRAM_W => BRAM_W) + port map( + clk_i => clk_i, rst_i => rst_i, rs232_tx_o => rs232_tx_o, + rs232_rx_i => rs232_rx_i, dbg_o => open, gpio_in => (others => '0')); +end architecture FPGA; -- Entity: Hello_Med1 + diff --git a/zpu/hdl/zealot/fpga/hello_small1.vhdl b/zpu/hdl/zealot/fpga/hello_small1.vhdl new file mode 100644 index 0000000..a7e2c21 --- /dev/null +++ b/zpu/hdl/zealot/fpga/hello_small1.vhdl @@ -0,0 +1,120 @@ +------------------------------------------------------------------------------ +---- ---- +---- ZPU Small connection to the FPGA pins ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- This module connects the ZPU_Small1 (zpu_small1.vhdl) core to a ---- +---- Spartan 3 1500 Xilinx FPGA available in the GR-XC3S board from ---- +---- Pender. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the GPL license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: Hello_Small1(FPGA) (Entity and architecture) ---- +---- File name: hello_small1.vhdl ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: work ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- zpu.zpu_pkg ---- +---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: N/A ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library zpu; +use zpu.zpupkg.all; + +entity Hello_Small1 is + generic( + WORD_SIZE : natural:=32; -- 32 bits data path + D_CARE_VAL : std_logic:='0'; -- Fill value, I got better results with it + CLK_FREQ : positive:=50; -- 50 MHz clock + BRATE : positive:=115200; -- RS-232 baudrate + ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O + BRAM_W : natural:=14); -- 14 bits RAM space=16 kB + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic); -- UART Rx + + constant BRD_PB1_I : string:="D19"; -- SWITCH8==S2 + constant BRD_CLK1_I : string:="AA12"; -- 50 MHz clock + --constant BRD_CLK1_I : string:="AB12"; -- 40 MHz clock + -- UART: direct 1:1 cable + constant BRD_TX_O : string:="L4"; -- UART 1 (J1) TXD1 DB9 pin 2 + constant BRD_RX_I : string:="L3"; -- UART 1 (J1) RXD1 DB9 pin 3 + + ------------ + -- Pinout -- + ------------ + attribute LOC : string; + attribute IOSTANDARD : string; + constant IOSTD : string:="LVTTL"; + + attribute LOC of rst_i : signal is BRD_PB1_I; + attribute IOSTANDARD of rst_i : signal is IOSTD; + attribute LOC of clk_i : signal is BRD_CLK1_I; + attribute LOC of rs232_tx_o : signal is BRD_TX_O; + attribute IOSTANDARD of rs232_tx_o : signal is IOSTD; + attribute LOC of rs232_rx_i : signal is BRD_RX_I; + attribute IOSTANDARD of rs232_rx_i : signal is IOSTD; +end entity Hello_Small1; + +architecture FPGA of Hello_Small1 is + component ZPU_Small1 is + generic( + WORD_SIZE : natural:=32; -- 32 bits data path + D_CARE_VAL : std_logic:='0'; -- Fill value + CLK_FREQ : positive:=50; -- 50 MHz clock + BRATE : positive:=115200; -- RS232 baudrate + ADDR_W : natural:=16; -- 16 bits address space=64 kB, 32 kB I/O + BRAM_W : natural:=15); -- 15 bits RAM space=32 kB + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + break_o : out std_logic; -- Break executed + dbg_o : out zpu_dbgo_t; -- Debug info + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic; -- UART Rx + gpio_in : in std_logic_vector(31 downto 0); + gpio_out : out std_logic_vector(31 downto 0); + gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out + ); + end component ZPU_Small1; +begin + zpu : ZPU_Small1 + generic map( + WORD_SIZE => WORD_SIZE, D_CARE_VAL => D_CARE_VAL, + CLK_FREQ => CLK_FREQ, BRATE => BRATE, ADDR_W => ADDR_W, + BRAM_W => BRAM_W) + port map( + clk_i => clk_i, rst_i => rst_i, rs232_tx_o => rs232_tx_o, + rs232_rx_i => rs232_rx_i, dbg_o => open, gpio_in => (others => '0')); +end architecture FPGA; -- Entity: Hello_Small1 + diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/clean_up.sh b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/clean_up.sh new file mode 100755 index 0000000..3855f16 --- /dev/null +++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/clean_up.sh @@ -0,0 +1,16 @@ +#!/bin/sh + +# ise build stuff +rm -rf build +rm -f top.bit + +# modelsim compile stuff +rm -rf work +rm -rf zpu + +# modelsim simulation stuff +rm -f vsim.wlf +rm -f transcript +rm -f zpu_trace.log +rm -f zpu_med1_io.log +rm -f zpu_small1_io.log diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation.sh b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation.sh new file mode 100755 index 0000000..d525737 --- /dev/null +++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation.sh @@ -0,0 +1,49 @@ +#!/bin/sh + +# need project files: +# run.do +# wave.do + +# need ModelSim tools: +# vlib +# vcom +# vsim + + +echo "###############" +echo "compile zpu lib" +echo "###############" +vlib zpu +vcom -work zpu ../../roms/hello_dbram.vhdl +vcom -work zpu ../../roms/hello_bram.vhdl +#vcom -work zpu ../../roms/dmips_dbram.vhdl +#vcom -work zpu ../../roms/dmips_bram.vhdl + +vcom -work zpu ../../roms/rom_pkg.vhdl +vcom -work zpu ../../zpu_pkg.vhdl +vcom -work zpu ../../zpu_small.vhdl +vcom -work zpu ../../zpu_medium.vhdl +vcom -work zpu ../../helpers/zpu_small1.vhdl +vcom -work zpu ../../helpers/zpu_med1.vhdl +vcom -work zpu ../../devices/txt_util.vhdl +vcom -work zpu ../../devices/phi_io.vhdl +vcom -work zpu ../../devices/timer.vhdl +vcom -work zpu ../../devices/gpio.vhdl +vcom -work zpu ../../devices/rx_unit.vhdl +vcom -work zpu ../../devices/tx_unit.vhdl +vcom -work zpu ../../devices/br_gen.vhdl +vcom -work zpu ../../devices/trace.vhdl + + +echo "################" +echo "compile work lib" +echo "################" +vlib work +vcom top.vhd +vcom top_tb.vhd + + +echo "###################" +echo "start simulator gui" +echo "###################" +vsim -gui top_tb -do simulation_config/run.do diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/run.do b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/run.do new file mode 100644 index 0000000..0d29e0a --- /dev/null +++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/run.do @@ -0,0 +1,2 @@ +do wave.do
+run -all
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/wave.do b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/wave.do new file mode 100644 index 0000000..6a3731d --- /dev/null +++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/wave.do @@ -0,0 +1,163 @@ +onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /top_tb/simulation_run
+add wave -noupdate /top_tb/tb_cpu_reset
+add wave -noupdate /top_tb/tb_sysclk_n
+add wave -noupdate /top_tb/tb_sysclk_p
+add wave -noupdate /top_tb/tb_user_clock
+add wave -noupdate -divider <NULL>
+add wave -noupdate /top_tb/top_i0/clk
+add wave -noupdate -divider <NULL>
+add wave -noupdate /top_tb/tb_gpio_button
+add wave -noupdate /top_tb/tb_gpio_header_ls
+add wave -noupdate /top_tb/tb_gpio_led
+add wave -noupdate /top_tb/tb_gpio_switch
+add wave -noupdate -expand -group USB/RS232 /top_tb/tb_usb_1_cts
+add wave -noupdate -expand -group USB/RS232 /top_tb/tb_usb_1_rts
+add wave -noupdate -expand -group USB/RS232 /top_tb/tb_usb_1_rx
+add wave -noupdate -expand -group USB/RS232 /top_tb/tb_usb_1_tx
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_a
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_ba
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_cas_b
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_ras_b
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_we_b
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_cke
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_clk_n
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_clk_p
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_dq
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_ldm
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_udm
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_ldqs_n
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_ldqs_p
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_udqs_n
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_udqs_p
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_odt
+add wave -noupdate -group {Flash memory} /top_tb/tb_flash_a
+add wave -noupdate -group {Flash memory} /top_tb/tb_flash_d
+add wave -noupdate -group {Flash memory} /top_tb/tb_fpga_d0_din_miso_miso1
+add wave -noupdate -group {Flash memory} /top_tb/tb_fpga_d1_miso2
+add wave -noupdate -group {Flash memory} /top_tb/tb_fpga_d2_miso3
+add wave -noupdate -group {Flash memory} /top_tb/tb_flash_we_b
+add wave -noupdate -group {Flash memory} /top_tb/tb_flash_oe_b
+add wave -noupdate -group {Flash memory} /top_tb/tb_flash_ce_b
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_clk0_m2c_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_clk0_m2c_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_clk1_m2c_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_clk1_m2c_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_iic_scl_main
+add wave -noupdate -group {FMC connector} /top_tb/tb_iic_sda_main
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la00_cc_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la00_cc_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la01_cc_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la01_cc_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la02_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la02_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la03_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la03_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la04_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la04_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la05_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la05_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la06_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la06_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la07_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la07_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la08_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la08_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la09_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la09_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la10_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la10_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la11_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la11_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la12_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la12_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la13_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la13_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la14_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la14_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la15_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la15_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la16_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la16_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la17_cc_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la17_cc_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la18_cc_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la18_cc_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la19_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la19_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la20_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la20_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la21_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la21_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la22_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la22_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la23_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la23_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la24_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la24_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la25_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la25_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la26_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la26_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la27_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la27_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la28_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la28_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la29_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la29_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la30_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la30_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la31_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la31_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la32_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la32_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la33_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la33_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_prsnt_m2c_l
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_pwr_good_flash_rst_b
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_awake
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_cclk
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_cmp_clk
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_cmp_mosi
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_hswapen
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_init_b
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_m0_cmp_miso
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_m1
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_mosi_csi_b_miso0
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_onchip_term1
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_onchip_term2
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_vtemp
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_spi_cs_b
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_col
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_crs
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_int
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_mdc
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_mdio
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_reset
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_rxclk
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_rxctl_rxdv
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_rxd
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_rxer
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_txclk
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_txctl_txen
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_txc_gtxclk
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_txd
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_txer
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {1393701250 ps} 0} {{Cursor 2} {138750 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ps} {327615 ps}
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis.sh b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis.sh new file mode 100755 index 0000000..2f89415 --- /dev/null +++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis.sh @@ -0,0 +1,36 @@ +#!/bin/sh + +# need project files: +# top.xst +# top.prj +# top.ut + +# need Xilinx tools: +# xst +# ngdbuild +# map +# par +# trce +# bitgen + +echo "########################" +echo "generate build directory" +echo "########################" +mkdir build +cd build +mkdir tmp + +echo "###############" +echo "start processes" +echo "###############" +xst -ifn "../synthesis_config/top.xst" -ofn "top.syr" +ngdbuild -dd _ngo -nt timestamp -uc ../synthesis_config/xilinx-sp601-xc6slx16.ucf -p xc6slx16-csg324-2 top.ngc top.ngd +map -p xc6slx16-csg324-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o top_map.ncd top.ngd top.pcf +par -ol high -mt off top_map.ncd -w top.ncd top.pcf +trce -v 3 -s 2 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf +bitgen -f ../synthesis_config/top.ut top.ncd + +echo "###########" +echo "get bitfile" +echo "###########" +cp top.bit .. diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.prj b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.prj new file mode 100644 index 0000000..965ae4c --- /dev/null +++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.prj @@ -0,0 +1,19 @@ +vhdl work ../top.vhd
+vhdl zpu ../../../zpu_pkg.vhdl
+vhdl zpu ../../../zpu_small.vhdl
+vhdl zpu ../../../zpu_medium.vhdl
+vhdl zpu ../../../roms/rom_pkg.vhdl
+#vhdl zpu ../../../roms/hello_dbram.vhdl
+#vhdl zpu ../../../roms/hello_bram.vhdl
+vhdl zpu ../../../roms/dmips_dbram.vhdl
+vhdl zpu ../../../roms/dmips_bram.vhdl
+vhdl zpu ../../../helpers/zpu_small1.vhdl
+vhdl zpu ../../../helpers/zpu_med1.vhdl
+vhdl zpu ../../../devices/txt_util.vhdl
+vhdl zpu ../../../devices/phi_io.vhdl
+vhdl zpu ../../../devices/timer.vhdl
+vhdl zpu ../../../devices/gpio.vhdl
+vhdl zpu ../../../devices/rx_unit.vhdl
+vhdl zpu ../../../devices/tx_unit.vhdl
+vhdl zpu ../../../devices/br_gen.vhdl
+vhdl zpu ../../../devices/trace.vhdl
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.ut b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.ut new file mode 100644 index 0000000..be56902 --- /dev/null +++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.ut @@ -0,0 +1,30 @@ +-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g Reset_on_err:No
+-g ConfigRate:2
+-g ProgPin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g ExtMasterCclk_en:No
+-g SPI_buswidth:1
+-g TIMER_CFG:0xFFFF
+-g multipin_wakeup:No
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
+-g en_sw_gsr:No
+-g drive_awake:No
+-g sw_clk:Startupclk
+-g sw_gwe_cycle:5
+-g sw_gts_cycle:4
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.xst b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.xst new file mode 100644 index 0000000..ddddddd --- /dev/null +++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.xst @@ -0,0 +1,53 @@ +set -tmpdir "tmp"
+set -xsthdpdir "xst"
+run
+-ifn ../synthesis_config/top.prj
+-ifmt mixed
+-ofn top
+-ofmt NGC
+-p xc6slx16-2-csg324
+-top top
+-opt_mode Speed
+-opt_level 1
+-power NO
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-dsp_utilization_ratio 100
+-lc Auto
+-reduce_control_sets Auto
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-shreg_extract YES
+-rom_style Auto
+-auto_bram_packing NO
+-resource_sharing YES
+-async_to_sync NO
+-shreg_min_size 2
+-use_dsp48 Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 16
+-register_duplication YES
+-register_balancing No
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/xilinx-sp601-xc6slx16.ucf b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/xilinx-sp601-xc6slx16.ucf new file mode 100644 index 0000000..a0c60e7 --- /dev/null +++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/xilinx-sp601-xc6slx16.ucf @@ -0,0 +1,303 @@ +############################################################
+# SPARTAN-6 SP601 Board Constraints File
+#
+# Family: Spartan6
+# Device: XC6SLX16
+# Package: CSG324
+# Speed: -2
+#
+#
+# Bank Voltage
+# Bank 0: 2.5 V
+# Bank 1: 2.5 V
+# Bank 2: 2.5 V
+# Bank 3: 1.8 V
+# VCCAUX: 2.5 V
+
+# following pins are connected to VCC1V8/2:
+# N3, M5, C1
+
+
+############################################################
+## clock/timing constraints
+############################################################
+
+TIMESPEC "TS_SYSCLK" = PERIOD "SYSCLK" 200 MHz HIGH 50 %;
+TIMESPEC "TS_USER_SMA_CLOCK" = PERIOD "USER_SMA_CLOCK" 50 MHz HIGH 50 %;
+NET "USER_CLOCK" PERIOD = 27 MHz HIGH 40%;
+
+
+############################################################
+## pin placement constraints
+############################################################
+
+NET "CPU_RESET" LOC = "N4";
+
+## 128 MB DDR2 Component Memory
+NET "DDR2_A<12>" LOC ="G6"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<11>" LOC ="D3"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<10>" LOC ="F4"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<9>" LOC ="D1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<8>" LOC ="D2"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<7>" LOC ="H6"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<6>" LOC ="H3"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<5>" LOC ="H4"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<4>" LOC ="F3"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<3>" LOC ="L7"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<2>" LOC ="H5"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<1>" LOC ="J6"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_A<0>" LOC ="J7"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<15>" LOC ="U1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<14>" LOC ="U2"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<13>" LOC ="T1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<12>" LOC ="T2"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<11>" LOC ="N1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<10>" LOC ="N2"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<9>" LOC ="M1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<8>" LOC ="M3"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<7>" LOC ="J1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<6>" LOC ="J3"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<5>" LOC ="H1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<4>" LOC ="H2"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<3>" LOC ="K1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<2>" LOC ="K2"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<1>" LOC ="L1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_DQ<0>" LOC ="L2"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_WE_B" LOC ="E3"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_UDQS_P" LOC ="P2"; # | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_UDQS_N" LOC ="P1"; # | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_UDM" LOC ="K4"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_RAS_B" LOC ="L5"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_ODT" LOC ="K6"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_LDQS_P" LOC ="L4"; # | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_LDQS_N" LOC ="L3"; # | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_LDM" LOC ="K3"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_CLK_P" LOC ="G3"; # | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_CLK_N" LOC ="G1"; # | IOSTANDARD = DIFF_SSTL18_II;
+NET "DDR2_CKE" LOC ="H7"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_CAS_B" LOC ="K5"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_BA<2>" LOC ="E1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_BA<1>" LOC ="F1"; # | IOSTANDARD = SSTL18_II ;
+NET "DDR2_BA<0>" LOC ="F2"; # | IOSTANDARD = SSTL18_II ;
+
+## Flash Memory
+NET "FLASH_A<0>" LOC = "K18";
+NET "FLASH_A<1>" LOC = "K17";
+NET "FLASH_A<2>" LOC = "J18";
+NET "FLASH_A<3>" LOC = "J16";
+NET "FLASH_A<4>" LOC = "G18";
+NET "FLASH_A<5>" LOC = "G16";
+NET "FLASH_A<6>" LOC = "H16";
+NET "FLASH_A<7>" LOC = "H15";
+NET "FLASH_A<8>" LOC = "H14";
+NET "FLASH_A<9>" LOC = "H13";
+NET "FLASH_A<10>" LOC = "F18";
+NET "FLASH_A<11>" LOC = "F17";
+NET "FLASH_A<12>" LOC = "K13";
+NET "FLASH_A<13>" LOC = "K12";
+NET "FLASH_A<14>" LOC = "E18";
+NET "FLASH_A<15>" LOC = "E16";
+NET "FLASH_A<16>" LOC = "G13";
+NET "FLASH_A<17>" LOC = "H12";
+NET "FLASH_A<18>" LOC = "D18";
+NET "FLASH_A<19>" LOC = "D17";
+NET "FLASH_A<20>" LOC = "G14";
+NET "FLASH_A<21>" LOC = "F14";
+NET "FLASH_A<22>" LOC = "C18";
+NET "FLASH_A<23>" LOC = "C17";
+NET "FLASH_A<24>" LOC = "F16";
+#NET "FLASH_D<0>" LOC = "R13" | SLEW = "SLOW" | DRIVE = 2;
+#NET "FLASH_D<1>" LOC = "T14" | SLEW = "SLOW" | DRIVE = 2;
+#NET "FLASH_D<2>" LOC = "V14" | SLEW = "SLOW" | DRIVE = 2;
+NET "FLASH_D<3>" LOC = "U5" | SLEW = "SLOW" | DRIVE = 2;
+NET "FLASH_D<4>" LOC = "V5" | SLEW = "SLOW" | DRIVE = 2;
+NET "FLASH_D<5>" LOC = "R3" | SLEW = "SLOW" | DRIVE = 2;
+NET "FLASH_D<6>" LOC = "T3" | SLEW = "SLOW" | DRIVE = 2;
+NET "FLASH_D<7>" LOC = "R5" | SLEW = "SLOW" | DRIVE = 2;
+NET "FLASH_OE_B" LOC = "L18";
+NET "FLASH_WE_B" LOC = "M16";
+NET "FLASH_CE_B" LOC = "L17";
+
+# FMC-Connector, Bank 0,2 (M2C = Mezzanine to Carrier, C2M = Carrier to Mezzanine)
+NET "FMC_CLK0_M2C_N" LOC = "A10";
+NET "FMC_CLK0_M2C_P" LOC = "C10";
+NET "FMC_CLK1_M2C_N" LOC = "V9" ;
+NET "FMC_CLK1_M2C_P" LOC = "T9" ;
+NET "FMC_LA00_CC_N" LOC = "C9" ;
+NET "FMC_LA00_CC_P" LOC = "D9" ;
+NET "FMC_LA01_CC_N" LOC = "C11";
+NET "FMC_LA01_CC_P" LOC = "D11";
+NET "FMC_LA02_N" LOC = "A15";
+NET "FMC_LA02_P" LOC = "C15";
+NET "FMC_LA03_N" LOC = "A13";
+NET "FMC_LA03_P" LOC = "C13";
+NET "FMC_LA04_N" LOC = "A16";
+NET "FMC_LA04_P" LOC = "B16";
+NET "FMC_LA05_N" LOC = "A14";
+NET "FMC_LA05_P" LOC = "B14";
+NET "FMC_LA06_N" LOC = "C12";
+NET "FMC_LA06_P" LOC = "D12";
+NET "FMC_LA07_N" LOC = "E8" ;
+NET "FMC_LA07_P" LOC = "E7" ;
+NET "FMC_LA08_N" LOC = "E11";
+NET "FMC_LA08_P" LOC = "F11";
+NET "FMC_LA09_N" LOC = "F10";
+NET "FMC_LA09_P" LOC = "G11";
+NET "FMC_LA10_N" LOC = "C8" ;
+NET "FMC_LA10_P" LOC = "D8" ;
+NET "FMC_LA11_N" LOC = "A12";
+NET "FMC_LA11_P" LOC = "B12";
+NET "FMC_LA12_N" LOC = "C6" ;
+NET "FMC_LA12_P" LOC = "D6" ;
+NET "FMC_LA13_N" LOC = "A11";
+NET "FMC_LA13_P" LOC = "B11";
+NET "FMC_LA14_N" LOC = "A2" ;
+NET "FMC_LA14_P" LOC = "B2" ;
+NET "FMC_LA15_N" LOC = "F9" ;
+NET "FMC_LA15_P" LOC = "G9" ;
+NET "FMC_LA16_N" LOC = "A7" ;
+NET "FMC_LA16_P" LOC = "C7" ;
+NET "FMC_LA17_CC_N" LOC = "T8" ;
+NET "FMC_LA17_CC_P" LOC = "R8" ;
+NET "FMC_LA18_CC_N" LOC = "T10";
+NET "FMC_LA18_CC_P" LOC = "R10";
+NET "FMC_LA19_N" LOC = "P7" ;
+NET "FMC_LA19_P" LOC = "N6" ;
+NET "FMC_LA20_N" LOC = "P8" ;
+NET "FMC_LA20_P" LOC = "N7" ;
+NET "FMC_LA21_N" LOC = "V4" ;
+NET "FMC_LA21_P" LOC = "T4" ;
+NET "FMC_LA22_N" LOC = "T7" ;
+NET "FMC_LA22_P" LOC = "R7" ;
+NET "FMC_LA23_N" LOC = "P6" ;
+NET "FMC_LA23_P" LOC = "N5" ;
+NET "FMC_LA24_N" LOC = "V8" ;
+NET "FMC_LA24_P" LOC = "U8" ;
+NET "FMC_LA25_N" LOC = "N11";
+NET "FMC_LA25_P" LOC = "M11";
+NET "FMC_LA26_N" LOC = "V7" ;
+NET "FMC_LA26_P" LOC = "U7" ;
+NET "FMC_LA27_N" LOC = "T11";
+NET "FMC_LA27_P" LOC = "R11";
+NET "FMC_LA28_N" LOC = "V11";
+NET "FMC_LA28_P" LOC = "U11";
+NET "FMC_LA29_N" LOC = "N8" ;
+NET "FMC_LA29_P" LOC = "M8" ;
+NET "FMC_LA30_N" LOC = "V12";
+NET "FMC_LA30_P" LOC = "T12";
+NET "FMC_LA31_N" LOC = "V6" ;
+NET "FMC_LA31_P" LOC = "T6" ;
+NET "FMC_LA32_N" LOC = "V15";
+NET "FMC_LA32_P" LOC = "U15";
+NET "FMC_LA33_N" LOC = "N9" ;
+NET "FMC_LA33_P" LOC = "M10";
+NET "FMC_PRSNT_M2C_L" LOC = "U13";
+NET "FMC_PWR_GOOD_FLASH_RST_B" LOC = "B3";
+
+# special FPGA pins
+NET "FPGA_AWAKE" LOC = "P15"| SLEW = SLOW | DRIVE = 2;
+NET "FPGA_CCLK" LOC = "R15";
+NET "FPGA_CMP_CLK" LOC = "U16";
+NET "FPGA_CMP_MOSI" LOC = "V16";
+NET "FPGA_D0_DIN_MISO_MISO1" LOC = "R13" | DRIVE = 4; ## 8 on U17 (thru series R187 100 ohm), 33 on U10, 6 on J12
+NET "FPGA_D1_MISO2" LOC = "T14" | DRIVE = 4; ## 9 on U17 (thru series R186 100 ohm), 35 on U10, 3 on J12
+NET "FPGA_D2_MISO3" LOC = "V14" | DRIVE = 4; ## 1 on U17, 38 on U10, 2 on J12
+NET "FPGA_HSWAPEN" LOC = "D4";
+NET "FPGA_INIT_B" LOC = "U3" | SLEW = SLOW | DRIVE = 4;
+NET "FPGA_M0_CMP_MISO" LOC = "T15";
+NET "FPGA_M1" LOC = "N12";
+NET "FPGA_MOSI_CSI_B_MISO0" LOC = "T13" | DRIVE = 4;
+NET "FPGA_ONCHIP_TERM1" LOC = "L6";
+NET "FPGA_ONCHIP_TERM2" LOC = "C2";
+NET "FPGA_VTEMP" LOC = "P3";
+
+## Pushbuttons, Bank 3, external Pulldown
+NET "GPIO_BUTTON<0>" LOC = "P4" ;
+NET "GPIO_BUTTON<1>" LOC = "F6" ;
+NET "GPIO_BUTTON<2>" LOC = "E4" ;
+NET "GPIO_BUTTON<3>" LOC = "F5" ;
+NET "GPIO_BUTTON*" TIG;
+
+## 8 Pin GPIO Header J13, Bank 0,1,2
+NET "GPIO_HEADER_LS<0>" LOC = "N17"| SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_HEADER_LS<1>" LOC = "M18"| SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_HEADER_LS<2>" LOC = "A3" | SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_HEADER_LS<3>" LOC = "L15"| SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_HEADER_LS<4>" LOC = "F15"| SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_HEADER_LS<5>" LOC = "B4" | SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_HEADER_LS<6>" LOC = "F13"| SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_HEADER_LS<7>" LOC = "P12"| SLEW = SLOW | DRIVE = 4 ;
+
+## 4 GPIO LEDs, Bank 0
+NET "GPIO_LED<0>" LOC = "E13"| SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_LED<1>" LOC = "C14"| SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_LED<2>" LOC = "C4" | SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_LED<3>" LOC = "A4" | SLEW = SLOW | DRIVE = 4 ;
+NET "GPIO_LED*" TIG;
+
+## GPIO Dip Switches, Bank 0,2, external Pulldown
+NET "GPIO_SWITCH<0>" LOC = "D14";
+NET "GPIO_SWITCH<1>" LOC = "E12";
+NET "GPIO_SWITCH<2>" LOC = "F12";
+NET "GPIO_SWITCH<3>" LOC = "V13";
+NET "GPIO_SWITCH*" TIG;
+
+## IIC Bus
+NET "IIC_SCL_MAIN" LOC = "P11";
+NET "IIC_SDA_MAIN" LOC = "N10";
+
+## 10/100/1000 Tri-Speed Ethernet PHY
+NET "PHY_COL" LOC = "L14";
+NET "PHY_CRS" LOC = "M13";
+NET "PHY_INT" LOC = "J13";
+NET "PHY_MDC" LOC = "N14" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_MDIO" LOC = "P16" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_RESET" LOC = "L13";
+NET "PHY_RXCLK" LOC = "L16";
+NET "PHY_RXCTL_RXDV" LOC = "N18";
+NET "PHY_RXD<0>" LOC = "M14";
+NET "PHY_RXD<1>" LOC = "U18";
+NET "PHY_RXD<2>" LOC = "U17";
+NET "PHY_RXD<3>" LOC = "T18";
+NET "PHY_RXD<4>" LOC = "T17";
+NET "PHY_RXD<5>" LOC = "N16";
+NET "PHY_RXD<6>" LOC = "N15";
+NET "PHY_RXD<7>" LOC = "P18";
+NET "PHY_RXER" LOC = "P17";
+NET "PHY_TXCLK" LOC = "B9" ;
+NET "PHY_TXCTL_TXEN" LOC = "B8" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXC_GTXCLK" LOC = "A9" ;
+NET "PHY_TXD<0>" LOC = "F8" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXD<1>" LOC = "G8" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXD<2>" LOC = "A6" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXD<3>" LOC = "B6" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXD<4>" LOC = "E6" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXD<5>" LOC = "F7" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXD<6>" LOC = "A5" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXD<7>" LOC = "C5" | SLEW = SLOW | DRIVE = 4;
+NET "PHY_TXER" LOC = "A8" | SLEW = SLOW | DRIVE = 4;
+
+## SPI x4 Flash
+NET "SPI_CS_B" LOC = "V3";
+
+## 200 MHz oscillator (differential)
+NET "SYSCLK_N" LOC = "K16"| IOSTANDARD = LVDS_33 | TNM_NET = "SYSCLK";
+NET "SYSCLK_P" LOC = "K15"| IOSTANDARD = LVDS_33 | TNM_NET = "SYSCLK";
+
+## USB-UART
+## this names are real net names
+NET "USB_1_CTS" LOC = "U10"| DRIVE = 4 | SLEW = SLOW; # RTS output
+NET "USB_1_RTS" LOC = "T5" ; # CTS input
+NET "USB_1_RX" LOC = "L12"| DRIVE = 4 | SLEW = SLOW; # TX data out
+NET "USB_1_TX" LOC = "K14"; # RX data in
+
+## 27 MHz
+NET "USER_CLOCK" LOC = "V10"| IOSTANDARD = LVCMOS33 ;
+##
+NET "USER_SMA_CLOCK_N" LOC = "H18"| TNM_NET = "USER_SMA_CLOCK";
+NET "USER_SMA_CLOCK_P" LOC = "H17"| TNM_NET = "USER_SMA_CLOCK";
+
+# pins used for voltage termination
+CONFIG PROHIBIT = C1;
+CONFIG PROHIBIT = M5;
+CONFIG PROHIBIT = N3;
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top.vhd b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top.vhd new file mode 100644 index 0000000..27d158f --- /dev/null +++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top.vhd @@ -0,0 +1,574 @@ +-- top module of
+-- SP601 evaluation board
+--
+-- using following external connections:
+--
+-- cpu_reset (SW9) reset
+-- LEDs output
+-- USB_UART communication
+--
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library zpu;
+use zpu.zpupkg.all; -- zpu_dbgo_t
+
+library unisim;
+use unisim.vcomponents.ibufgds;
+use unisim.vcomponents.dcm_sp;
+
+
+entity top is
+ port (
+ -- pragma translate_off
+ stop_simulation : out std_logic;
+ -- pragma translate_on
+ --
+ cpu_reset : in std_logic; -- SW9 pushbutton (active-high)
+ --
+ -- DDR2 memory 128 MB
+ ddr2_a : out std_logic_vector(12 downto 0);
+ ddr2_ba : out std_logic_vector(2 downto 0);
+ ddr2_cas_b : out std_logic;
+ ddr2_ras_b : out std_logic;
+ ddr2_we_b : out std_logic;
+ ddr2_cke : out std_logic;
+ ddr2_clk_n : out std_logic;
+ ddr2_clk_p : out std_logic;
+ ddr2_dq : inout std_logic_vector(15 downto 0);
+ ddr2_ldm : out std_logic;
+ ddr2_udm : out std_logic;
+ ddr2_ldqs_n : inout std_logic;
+ ddr2_ldqs_p : inout std_logic;
+ ddr2_udqs_n : inout std_logic;
+ ddr2_udqs_p : inout std_logic;
+ ddr2_odt : out std_logic;
+ --
+ -- flash memory
+ flash_a : out std_logic_vector(24 downto 0);
+ flash_d : inout std_logic_vector(7 downto 3);
+ --
+ fpga_d0_din_miso_miso1 : inout std_logic; -- dual use
+ fpga_d1_miso2 : inout std_logic; -- dual use
+ fpga_d2_miso3 : inout std_logic; -- dual use
+ flash_we_b : out std_logic;
+ flash_oe_b : out std_logic;
+ flash_ce_b : out std_logic;
+ --
+ -- FMC connector
+ -- M2C Mezzanine to Carrier
+ -- C2M Carrier to Mezzanine
+ fmc_clk0_m2c_n : in std_logic;
+ fmc_clk0_m2c_p : in std_logic;
+ fmc_clk1_m2c_n : in std_logic;
+ fmc_clk1_m2c_p : in std_logic;
+ -- IIC addresses:
+ -- M24C08: 1010100..1010111
+ -- 2kb EEPROM on FMC card: 1010010
+ iic_scl_main : inout std_logic;
+ iic_sda_main : inout std_logic;
+ fmc_la00_cc_n : inout std_logic;
+ fmc_la00_cc_p : inout std_logic;
+ fmc_la01_cc_n : inout std_logic;
+ fmc_la01_cc_p : inout std_logic;
+ fmc_la02_n : inout std_logic;
+ fmc_la02_p : inout std_logic;
+ fmc_la03_n : inout std_logic;
+ fmc_la03_p : inout std_logic;
+ fmc_la04_n : inout std_logic;
+ fmc_la04_p : inout std_logic;
+ fmc_la05_n : inout std_logic;
+ fmc_la05_p : inout std_logic;
+ fmc_la06_n : inout std_logic;
+ fmc_la06_p : inout std_logic;
+ fmc_la07_n : inout std_logic;
+ fmc_la07_p : inout std_logic;
+ fmc_la08_n : inout std_logic;
+ fmc_la08_p : inout std_logic;
+ fmc_la09_n : inout std_logic;
+ fmc_la09_p : inout std_logic;
+ fmc_la10_n : inout std_logic;
+ fmc_la10_p : inout std_logic;
+ fmc_la11_n : inout std_logic;
+ fmc_la11_p : inout std_logic;
+ fmc_la12_n : inout std_logic;
+ fmc_la12_p : inout std_logic;
+ fmc_la13_n : inout std_logic;
+ fmc_la13_p : inout std_logic;
+ fmc_la14_n : inout std_logic;
+ fmc_la14_p : inout std_logic;
+ fmc_la15_n : inout std_logic;
+ fmc_la15_p : inout std_logic;
+ fmc_la16_n : inout std_logic;
+ fmc_la16_p : inout std_logic;
+ fmc_la17_cc_n : inout std_logic;
+ fmc_la17_cc_p : inout std_logic;
+ fmc_la18_cc_n : inout std_logic;
+ fmc_la18_cc_p : inout std_logic;
+ fmc_la19_n : inout std_logic;
+ fmc_la19_p : inout std_logic;
+ fmc_la20_n : inout std_logic;
+ fmc_la20_p : inout std_logic;
+ fmc_la21_n : inout std_logic;
+ fmc_la21_p : inout std_logic;
+ fmc_la22_n : inout std_logic;
+ fmc_la22_p : inout std_logic;
+ fmc_la23_n : inout std_logic;
+ fmc_la23_p : inout std_logic;
+ fmc_la24_n : inout std_logic;
+ fmc_la24_p : inout std_logic;
+ fmc_la25_n : inout std_logic;
+ fmc_la25_p : inout std_logic;
+ fmc_la26_n : inout std_logic;
+ fmc_la26_p : inout std_logic;
+ fmc_la27_n : inout std_logic;
+ fmc_la27_p : inout std_logic;
+ fmc_la28_n : inout std_logic;
+ fmc_la28_p : inout std_logic;
+ fmc_la29_n : inout std_logic;
+ fmc_la29_p : inout std_logic;
+ fmc_la30_n : inout std_logic;
+ fmc_la30_p : inout std_logic;
+ fmc_la31_n : inout std_logic;
+ fmc_la31_p : inout std_logic;
+ fmc_la32_n : inout std_logic;
+ fmc_la32_p : inout std_logic;
+ fmc_la33_n : inout std_logic;
+ fmc_la33_p : inout std_logic;
+ fmc_prsnt_m2c_l : in std_logic;
+ fmc_pwr_good_flash_rst_b : out std_logic; -- multiple destinations: 1 of Q2 (LED DS1 driver), U1 AB2 FPGA_PROG (through series R260 DNP), 44 of U25
+ --
+ fpga_awake : out std_logic;
+ fpga_cclk : out std_logic;
+ fpga_cmp_clk : in std_logic;
+ fpga_cmp_mosi : in std_logic;
+ --
+ fpga_hswapen : in std_logic;
+ fpga_init_b : out std_logic; -- low active
+ fpga_m0_cmp_miso : in std_logic; -- mode DIP switch SW1 active high
+ fpga_m1 : in std_logic; -- mode DIP switch SW1 active high
+ fpga_mosi_csi_b_miso0 : inout std_logic;
+ fpga_onchip_term1 : inout std_logic;
+ fpga_onchip_term2 : inout std_logic;
+ fpga_vtemp : in std_logic;
+ --
+ -- GPIOs
+ gpio_button : in std_logic_vector(3 downto 0); -- active high
+ gpio_header_ls : inout std_logic_vector(7 downto 0);
+ gpio_led : out std_logic_vector(3 downto 0);
+ gpio_switch : in std_logic_vector(3 downto 0); -- active high
+ --
+ -- Ethernet Gigabit PHY,
+ -- default settings:
+ -- phy address = 0b00111
+ -- ANEG[3..0] = "1111"
+ -- ENA_XC = 1
+ -- DIS_125 = 1
+ -- HWCFG_MD[3..0] = "1111"
+ -- DIS_FC = 1
+ -- DIS_SLEEP = 1
+ -- SEL_BDT = 0
+ -- INT_POL = 1
+ -- 75/50Ohm = 0
+ phy_col : in std_logic;
+ phy_crs : in std_logic;
+ phy_int : in std_logic;
+ phy_mdc : out std_logic;
+ phy_mdio : inout std_logic;
+ phy_reset : out std_logic;
+ phy_rxclk : in std_logic;
+ phy_rxctl_rxdv : in std_logic;
+ phy_rxd : in std_logic_vector(7 downto 0);
+ phy_rxer : in std_logic;
+ phy_txclk : in std_logic;
+ phy_txctl_txen : out std_logic;
+ phy_txc_gtxclk : out std_logic;
+ phy_txd : out std_logic_vector(7 downto 0);
+ phy_txer : out std_logic;
+ --
+ --
+ spi_cs_b : out std_logic;
+ --
+ -- 200 MHz oscillator, jitter 50 ppm
+ sysclk_n : in std_logic;
+ sysclk_p : in std_logic;
+ --
+ -- RS232 via USB
+ usb_1_cts : out std_logic; -- function: RTS output
+ usb_1_rts : in std_logic; -- function: CTS input
+ usb_1_rx : out std_logic; -- function: TX data out
+ usb_1_tx : in std_logic; -- function: RX data in
+ --
+ -- 27 MHz, oscillator socket
+ user_clock : in std_logic;
+ --
+ -- user clock provided per SMA
+ user_sma_clock_p : in std_logic;
+ user_sma_clock_n : in std_logic
+ );
+end entity top;
+
+
+architecture rtl of top is
+
+ ---------------------------
+ -- type declarations
+ type zpu_type is (zpu_small, zpu_medium);
+
+ ---------------------------
+ -- constant declarations
+ constant zpu_flavour : zpu_type := zpu_medium; -- choose your flavour HERE
+ -- modify frequency here
+ constant clk_multiply : positive := 2; -- 2 for small, 2 for medium
+ constant clk_divide : positive := 5; -- 4 for small, 5 for medium
+ --
+ --
+ constant word_size_c : natural := 32; -- 32 bits data path
+ constant addr_w_c : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O
+ --
+ constant clk_frequency : positive := 200; -- input frequency for correct calculation
+
+
+ ---------------------------
+ -- component declarations
+ component zpu_small1 is
+ generic (
+ word_size : natural := 32; -- 32 bits data path
+ d_care_val : std_logic := '0'; -- Fill value
+ clk_freq : positive := 50; -- 50 MHz clock
+ brate : positive := 115200; -- RS232 baudrate
+ addr_w : natural := 16; -- 16 bits address space=64 kB, 32 kB I/O
+ bram_w : natural := 15 -- 15 bits RAM space=32 kB
+ );
+ port (
+ clk_i : in std_logic; -- CPU clock
+ rst_i : in std_logic; -- Reset
+ break_o : out std_logic; -- Break executed
+ dbg_o : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o : out std_logic; -- UART Tx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end component zpu_small1;
+
+ component zpu_med1 is
+ generic(
+ word_size : natural := 32; -- 32 bits data path
+ d_care_val : std_logic := '0'; -- Fill value
+ clk_freq : positive := 50; -- 50 MHz clock
+ brate : positive := 115200; -- RS232 baudrate
+ addr_w : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O
+ bram_w : natural := 15 -- 15 bits RAM space=32 kB
+ );
+ port(
+ clk_i : in std_logic; -- CPU clock
+ rst_i : in std_logic; -- Reset
+ break_o : out std_logic; -- Break executed
+ dbg_o : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o : out std_logic; -- UART Tx
+ rs232_rx_i : in std_logic; -- UART Rx
+ gpio_in : in std_logic_vector(31 downto 0);
+ gpio_out : out std_logic_vector(31 downto 0);
+ gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end component zpu_med1;
+
+
+
+ ---------------------------
+ -- signal declarations
+ signal sys_clk : std_ulogic;
+ signal dcm_sp_i0_clk0 : std_ulogic;
+ signal dcm_sp_i0_clkfx : std_ulogic;
+ signal clk_fb : std_ulogic;
+ signal clk : std_ulogic;
+ --
+ signal reset_shift_reg : std_ulogic_vector(3 downto 0);
+ signal reset_sync : std_ulogic;
+ --
+ signal zpu_i0_dbg : zpu_dbgo_t; -- Debug info
+ signal zpu_i0_break : std_logic;
+ --
+ signal gpio_in : std_logic_vector(31 downto 0) := (others => '0');
+ signal zpu_i0_gpio_out : std_logic_vector(31 downto 0);
+ signal zpu_i0_gpio_dir : std_logic_vector(31 downto 0);
+
+
+begin
+
+ -- default output drivers
+ -- to pass bitgen DRC
+ -- outputs used by design are commented
+ --
+ ddr2_a <= (others => '1');
+ ddr2_ba <= (others => '1');
+ ddr2_cas_b <= '1';
+ ddr2_ras_b <= '1';
+ ddr2_we_b <= '1';
+ ddr2_cke <= '0';
+ ddr2_clk_n <= '0';
+ ddr2_clk_p <= '1';
+ ddr2_dq <= (others => 'Z');
+ ddr2_ldm <= '0';
+ ddr2_udm <= '0';
+ ddr2_ldqs_n <= 'Z';
+ ddr2_ldqs_p <= 'Z';
+ ddr2_udqs_n <= 'Z';
+ ddr2_udqs_p <= 'Z';
+ ddr2_odt <= '1';
+ --
+ flash_a <= (others => '1');
+ flash_d <= (others => 'Z');
+ flash_we_b <= '1';
+ flash_oe_b <= '1';
+ flash_ce_b <= '1';
+ --
+ fpga_d0_din_miso_miso1 <= 'Z';
+ fpga_d1_miso2 <= 'Z';
+ fpga_d2_miso3 <= 'Z';
+ --
+ iic_scl_main <= 'Z';
+ iic_sda_main <= 'Z';
+ fmc_la00_cc_n <= 'Z';
+ fmc_la00_cc_p <= 'Z';
+ fmc_la01_cc_n <= 'Z';
+ fmc_la01_cc_p <= 'Z';
+ fmc_la02_n <= 'Z';
+ fmc_la02_p <= 'Z';
+ fmc_la03_n <= 'Z';
+ fmc_la03_p <= 'Z';
+ fmc_la04_n <= 'Z';
+ fmc_la04_p <= 'Z';
+ fmc_la05_n <= 'Z';
+ fmc_la05_p <= 'Z';
+ fmc_la06_n <= 'Z';
+ fmc_la06_p <= 'Z';
+ fmc_la07_n <= 'Z';
+ fmc_la07_p <= 'Z';
+ fmc_la08_n <= 'Z';
+ fmc_la08_p <= 'Z';
+ fmc_la09_n <= 'Z';
+ fmc_la09_p <= 'Z';
+ fmc_la10_n <= 'Z';
+ fmc_la10_p <= 'Z';
+ fmc_la11_n <= 'Z';
+ fmc_la11_p <= 'Z';
+ fmc_la12_n <= 'Z';
+ fmc_la12_p <= 'Z';
+ fmc_la13_n <= 'Z';
+ fmc_la13_p <= 'Z';
+ fmc_la14_n <= 'Z';
+ fmc_la14_p <= 'Z';
+ fmc_la15_n <= 'Z';
+ fmc_la15_p <= 'Z';
+ fmc_la16_n <= 'Z';
+ fmc_la16_p <= 'Z';
+ fmc_la17_cc_n <= 'Z';
+ fmc_la17_cc_p <= 'Z';
+ fmc_la18_cc_n <= 'Z';
+ fmc_la18_cc_p <= 'Z';
+ fmc_la19_n <= 'Z';
+ fmc_la19_p <= 'Z';
+ fmc_la20_n <= 'Z';
+ fmc_la20_p <= 'Z';
+ fmc_la21_n <= 'Z';
+ fmc_la21_p <= 'Z';
+ fmc_la22_n <= 'Z';
+ fmc_la22_p <= 'Z';
+ fmc_la23_n <= 'Z';
+ fmc_la23_p <= 'Z';
+ fmc_la24_n <= 'Z';
+ fmc_la24_p <= 'Z';
+ fmc_la25_n <= 'Z';
+ fmc_la25_p <= 'Z';
+ fmc_la26_n <= 'Z';
+ fmc_la26_p <= 'Z';
+ fmc_la27_n <= 'Z';
+ fmc_la27_p <= 'Z';
+ fmc_la28_n <= 'Z';
+ fmc_la28_p <= 'Z';
+ fmc_la29_n <= 'Z';
+ fmc_la29_p <= 'Z';
+ fmc_la30_n <= 'Z';
+ fmc_la30_p <= 'Z';
+ fmc_la31_n <= 'Z';
+ fmc_la31_p <= 'Z';
+ fmc_la32_n <= 'Z';
+ fmc_la32_p <= 'Z';
+ fmc_la33_n <= 'Z';
+ fmc_la33_p <= 'Z';
+ fmc_pwr_good_flash_rst_b <= '1';
+ --
+ fpga_awake <= '1';
+ fpga_cclk <= '1'; -- SPI clk
+ fpga_init_b <= '1';
+ fpga_mosi_csi_b_miso0 <= 'Z';
+ fpga_onchip_term1 <= 'Z';
+ fpga_onchip_term2 <= 'Z';
+ --
+ --gpio_led <= (others => '0');
+ --gpio_header_ls <= (others => 'Z');
+ --
+ phy_mdc <= '0';
+ phy_mdio <= 'Z';
+ phy_reset <= '0';
+ phy_txc_gtxclk <= '0';
+ phy_txctl_txen <= '0';
+ phy_txd <= (others => '1');
+ phy_txer <= '0';
+ --
+ spi_cs_b <= '1';
+ --
+ --usb_1_rx <= '1'; -- function: TX data out
+ usb_1_cts <= '1'; -- function: RTS
+
+
+ -- global differential input buffer
+ ibufgds_i0 : ibufgds
+ generic map (
+ diff_term => true
+ )
+ port map (
+ i => sysclk_p,
+ ib => sysclk_n,
+ o => sys_clk
+ );
+
+ -- digital clock manager (DCM)
+ -- to generate higher/other system clock frequencys
+ dcm_sp_i0 : dcm_sp
+ generic map (
+ startup_wait => true, -- wait with DONE till locked
+ clkfx_multiply => clk_multiply,
+ clkfx_divide => clk_divide,
+ clk_feedback => "1X"
+ )
+ port map (
+ clkin => sys_clk,
+ clk0 => dcm_sp_i0_clk0,
+ clkfx => dcm_sp_i0_clkfx,
+ clkfb => clk_fb
+ );
+
+ clk_fb <= dcm_sp_i0_clk0;
+ clk <= dcm_sp_i0_clkfx;
+
+
+ -- reset synchronizer
+ -- generate synchronous reset
+ reset_synchronizer : process(clk, cpu_reset)
+ begin
+ if cpu_reset = '1' then
+ reset_shift_reg <= (others => '1');
+ elsif rising_edge(clk) then
+ reset_shift_reg <= reset_shift_reg(reset_shift_reg'high-1 downto 0) & '0';
+ end if;
+ end process;
+ reset_sync <= reset_shift_reg(reset_shift_reg'high);
+
+
+
+ -- select instance of zpu
+ zpu_i0_small: if zpu_flavour = zpu_small generate
+ zpu_i0 : zpu_small1
+ generic map (
+ addr_w => addr_w_c,
+ word_size => word_size_c,
+ clk_freq => clk_frequency * clk_multiply / clk_divide
+ )
+ port map (
+ clk_i => clk, -- : in std_logic; -- CPU clock
+ rst_i => reset_sync, -- : in std_logic; -- Reset
+ break_o => zpu_i0_break, -- : out std_logic; -- Break executed
+ dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o => usb_1_rx, -- : out std_logic; -- UART Tx
+ rs232_rx_i => usb_1_tx, -- : in std_logic -- UART Rx
+ gpio_in => gpio_in, -- : in std_logic_vector(31 downto 0);
+ gpio_out => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
+ gpio_dir => zpu_i0_gpio_dir -- : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end generate zpu_i0_small;
+
+ zpu_i0_medium: if zpu_flavour = zpu_medium generate
+ zpu_i0 : zpu_med1
+ generic map (
+ addr_w => addr_w_c,
+ word_size => word_size_c,
+ clk_freq => clk_frequency * clk_multiply / clk_divide
+ )
+ port map (
+ clk_i => clk, -- : in std_logic; -- CPU clock
+ rst_i => reset_sync, -- : in std_logic; -- Reset
+ break_o => zpu_i0_break, -- : out std_logic; -- Break executed
+ dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; -- Debug info
+ rs232_tx_o => usb_1_rx, -- : out std_logic; -- UART Tx
+ rs232_rx_i => usb_1_tx, -- : in std_logic -- UART Rx
+ gpio_in => gpio_in, -- : in std_logic_vector(31 downto 0);
+ gpio_out => zpu_i0_gpio_out, -- : out std_logic_vector(31 downto 0);
+ gpio_dir => zpu_i0_gpio_dir -- : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
+ );
+ end generate zpu_i0_medium;
+
+
+ -- pragma translate_off
+ stop_simulation <= zpu_i0_break; -- abort() causes to stop the simulation
+
+
+
+ trace_mod : trace
+ generic map (
+ addr_w => addr_w_c,
+ word_size => word_size_c,
+ log_file => "zpu_trace.log"
+ )
+ port map (
+ clk_i => clk,
+ dbg_i => zpu_i0_dbg,
+ stop_i => zpu_i0_break,
+ busy_i => '0'
+ );
+ -- pragma translate_on
+
+ -- assign GPIOs
+ --
+ -- bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
+ --
+ -- in -- -- -- -- -- -- -- -- gpio_header_ls(7.....0)
+ -- out -- -- -- -- -- -- -- -- gpio_header_ls(7.....0)
+ --
+ -- bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+ --
+ -- in -- -- -- -- switch(3.0) -- -- -- -- button(3.0)
+ -- out -- -- -- -- -- -- -- -- gpio_led(7...........0)
+ --
+ gpio_in(23 downto 16) <= gpio_header_ls;
+ gpio_in(11 downto 8) <= gpio_switch;
+ gpio_in( 3 downto 0) <= gpio_button;
+
+ -- 3-state buffers for header_ls
+ gpio_header_ls(7) <= zpu_i0_gpio_out(23) when zpu_i0_gpio_dir(23) = '0' else 'Z';
+ gpio_header_ls(6) <= zpu_i0_gpio_out(22) when zpu_i0_gpio_dir(22) = '0' else 'Z';
+ gpio_header_ls(5) <= zpu_i0_gpio_out(21) when zpu_i0_gpio_dir(21) = '0' else 'Z';
+ gpio_header_ls(4) <= zpu_i0_gpio_out(20) when zpu_i0_gpio_dir(20) = '0' else 'Z';
+ gpio_header_ls(3) <= zpu_i0_gpio_out(19) when zpu_i0_gpio_dir(19) = '0' else 'Z';
+ gpio_header_ls(2) <= zpu_i0_gpio_out(18) when zpu_i0_gpio_dir(18) = '0' else 'Z';
+ gpio_header_ls(1) <= zpu_i0_gpio_out(17) when zpu_i0_gpio_dir(17) = '0' else 'Z';
+ gpio_header_ls(0) <= zpu_i0_gpio_out(16) when zpu_i0_gpio_dir(16) = '0' else 'Z';
+
+ -- switch on all LEDs in case of break
+ process
+ begin
+ wait until rising_edge(clk);
+ gpio_led <= zpu_i0_gpio_out(3 downto 0);
+ if zpu_i0_break = '1' then
+ gpio_led <= (others => '1');
+ end if;
+ end process;
+
+
+
+end architecture rtl;
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top_tb.vhd b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top_tb.vhd new file mode 100644 index 0000000..f089f29 --- /dev/null +++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top_tb.vhd @@ -0,0 +1,402 @@ +-- testbench for
+-- SP601 evaluation board
+--
+-- includes "model" for clock generation
+-- simulate press on cpu_reset as reset
+--
+-- place models for external components (PHY, DDR2) in this file
+--
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity top_tb is
+end entity top_tb;
+
+architecture testbench of top_tb is
+
+ ---------------------------
+ -- constant declarations
+ constant sys_clk_period : time := 1 sec / 200_000_000; -- 200 MHz
+ constant user_clk_period : time := 1 sec / 27_000_000; -- 27 MHz
+
+
+ ---------------------------
+ -- signal declarations
+ signal simulation_run : boolean := true;
+ signal tb_stop_simulation : std_logic;
+ --
+ signal tb_cpu_reset : std_logic; -- SW9 pushbutton (active-high)
+ --
+ -- DDR2 memory 128 MB
+ signal tb_ddr2_a : std_logic_vector(12 downto 0);
+ signal tb_ddr2_ba : std_logic_vector(2 downto 0);
+ signal tb_ddr2_cas_b : std_logic;
+ signal tb_ddr2_ras_b : std_logic;
+ signal tb_ddr2_we_b : std_logic;
+ signal tb_ddr2_cke : std_logic;
+ signal tb_ddr2_clk_n : std_logic;
+ signal tb_ddr2_clk_p : std_logic;
+ signal tb_ddr2_dq : std_logic_vector(15 downto 0);
+ signal tb_ddr2_ldm : std_logic;
+ signal tb_ddr2_udm : std_logic;
+ signal tb_ddr2_ldqs_n : std_logic;
+ signal tb_ddr2_ldqs_p : std_logic;
+ signal tb_ddr2_udqs_n : std_logic;
+ signal tb_ddr2_udqs_p : std_logic;
+ signal tb_ddr2_odt : std_logic;
+ --
+ -- flash memory
+ signal tb_flash_a : std_logic_vector(24 downto 0);
+ signal tb_flash_d : std_logic_vector(7 downto 3);
+ signal tb_fpga_d0_din_miso_miso1 : std_logic; -- dual use
+ signal tb_fpga_d1_miso2 : std_logic; -- dual use
+ signal tb_fpga_d2_miso3 : std_logic; -- dual use
+ signal tb_flash_we_b : std_logic;
+ signal tb_flash_oe_b : std_logic;
+ signal tb_flash_ce_b : std_logic;
+ --
+ -- FMC connector
+ -- M2C Mezzanine to Carrier
+ -- C2M Carrier to Mezzanine
+ signal tb_fmc_clk0_m2c_n : std_logic := '1';
+ signal tb_fmc_clk0_m2c_p : std_logic := '0';
+ signal tb_fmc_clk1_m2c_n : std_logic := '1';
+ signal tb_fmc_clk1_m2c_p : std_logic := '0';
+ -- IIC addresses:
+ -- M24C08: 1010100..1010111
+ -- 2kb EEPROM on FMC card: 1010010
+ signal tb_iic_scl_main : std_logic;
+ signal tb_iic_sda_main : std_logic;
+ signal tb_fmc_la00_cc_n : std_logic;
+ signal tb_fmc_la00_cc_p : std_logic;
+ signal tb_fmc_la01_cc_n : std_logic;
+ signal tb_fmc_la01_cc_p : std_logic;
+ signal tb_fmc_la02_n : std_logic;
+ signal tb_fmc_la02_p : std_logic;
+ signal tb_fmc_la03_n : std_logic;
+ signal tb_fmc_la03_p : std_logic;
+ signal tb_fmc_la04_n : std_logic;
+ signal tb_fmc_la04_p : std_logic;
+ signal tb_fmc_la05_n : std_logic;
+ signal tb_fmc_la05_p : std_logic;
+ signal tb_fmc_la06_n : std_logic;
+ signal tb_fmc_la06_p : std_logic;
+ signal tb_fmc_la07_n : std_logic;
+ signal tb_fmc_la07_p : std_logic;
+ signal tb_fmc_la08_n : std_logic;
+ signal tb_fmc_la08_p : std_logic;
+ signal tb_fmc_la09_n : std_logic;
+ signal tb_fmc_la09_p : std_logic;
+ signal tb_fmc_la10_n : std_logic;
+ signal tb_fmc_la10_p : std_logic;
+ signal tb_fmc_la11_n : std_logic;
+ signal tb_fmc_la11_p : std_logic;
+ signal tb_fmc_la12_n : std_logic;
+ signal tb_fmc_la12_p : std_logic;
+ signal tb_fmc_la13_n : std_logic;
+ signal tb_fmc_la13_p : std_logic;
+ signal tb_fmc_la14_n : std_logic;
+ signal tb_fmc_la14_p : std_logic;
+ signal tb_fmc_la15_n : std_logic;
+ signal tb_fmc_la15_p : std_logic;
+ signal tb_fmc_la16_n : std_logic;
+ signal tb_fmc_la16_p : std_logic;
+ signal tb_fmc_la17_cc_n : std_logic;
+ signal tb_fmc_la17_cc_p : std_logic;
+ signal tb_fmc_la18_cc_n : std_logic;
+ signal tb_fmc_la18_cc_p : std_logic;
+ signal tb_fmc_la19_n : std_logic;
+ signal tb_fmc_la19_p : std_logic;
+ signal tb_fmc_la20_n : std_logic;
+ signal tb_fmc_la20_p : std_logic;
+ signal tb_fmc_la21_n : std_logic;
+ signal tb_fmc_la21_p : std_logic;
+ signal tb_fmc_la22_n : std_logic;
+ signal tb_fmc_la22_p : std_logic;
+ signal tb_fmc_la23_n : std_logic;
+ signal tb_fmc_la23_p : std_logic;
+ signal tb_fmc_la24_n : std_logic;
+ signal tb_fmc_la24_p : std_logic;
+ signal tb_fmc_la25_n : std_logic;
+ signal tb_fmc_la25_p : std_logic;
+ signal tb_fmc_la26_n : std_logic;
+ signal tb_fmc_la26_p : std_logic;
+ signal tb_fmc_la27_n : std_logic;
+ signal tb_fmc_la27_p : std_logic;
+ signal tb_fmc_la28_n : std_logic;
+ signal tb_fmc_la28_p : std_logic;
+ signal tb_fmc_la29_n : std_logic;
+ signal tb_fmc_la29_p : std_logic;
+ signal tb_fmc_la30_n : std_logic;
+ signal tb_fmc_la30_p : std_logic;
+ signal tb_fmc_la31_n : std_logic;
+ signal tb_fmc_la31_p : std_logic;
+ signal tb_fmc_la32_n : std_logic;
+ signal tb_fmc_la32_p : std_logic;
+ signal tb_fmc_la33_n : std_logic;
+ signal tb_fmc_la33_p : std_logic;
+ signal tb_fmc_prsnt_m2c_l : std_logic := '0';
+ signal tb_fmc_pwr_good_flash_rst_b : std_logic; -- multiple destinations: 1 of Q2 (LED DS1 driver), U1 AB2 FPGA_PROG (through series R260 DNP), 44 of U25
+ --
+ signal tb_fpga_awake : std_logic;
+ signal tb_fpga_cclk : std_logic;
+ signal tb_fpga_cmp_clk : std_logic := '0';
+ signal tb_fpga_cmp_mosi : std_logic := '0';
+ signal tb_fpga_hswapen : std_logic := '0';
+ signal tb_fpga_init_b : std_logic; -- low active
+ signal tb_fpga_m0_cmp_miso : std_logic := '0'; -- mode DIP switch SW1 active high
+ signal tb_fpga_m1 : std_logic := '0'; -- mode DIP switch SW1 active high
+ signal tb_fpga_mosi_csi_b_miso0 : std_logic;
+ signal tb_fpga_onchip_term1 : std_logic;
+ signal tb_fpga_onchip_term2 : std_logic;
+ signal tb_fpga_vtemp : std_logic := '0';
+ --
+ -- GPIOs
+ signal tb_gpio_button : std_logic_vector(3 downto 0) := (others => '0'); -- active high
+ signal tb_gpio_header_ls : std_logic_vector(7 downto 0); --
+ signal tb_gpio_led : std_logic_vector(3 downto 0);
+ signal tb_gpio_switch : std_logic_vector(3 downto 0) := (others => '0'); -- active high
+ --
+ -- Ethernet Gigabit PHY
+ signal tb_phy_col : std_logic := '0';
+ signal tb_phy_crs : std_logic := '0';
+ signal tb_phy_int : std_logic := '0';
+ signal tb_phy_mdc : std_logic;
+ signal tb_phy_mdio : std_logic;
+ signal tb_phy_reset : std_logic;
+ signal tb_phy_rxclk : std_logic := '0';
+ signal tb_phy_rxctl_rxdv : std_logic := '0';
+ signal tb_phy_rxd : std_logic_vector(7 downto 0);
+ signal tb_phy_rxer : std_logic := '0';
+ signal tb_phy_txclk : std_logic := '0';
+ signal tb_phy_txctl_txen : std_logic;
+ signal tb_phy_txc_gtxclk : std_logic;
+ signal tb_phy_txd : std_logic_vector(7 downto 0);
+ signal tb_phy_txer : std_logic;
+ --
+ --
+ signal tb_spi_cs_b : std_logic;
+ --
+ -- 200 MHz oscillator, jitter 50 ppm
+ signal tb_sysclk_n : std_logic := '1';
+ signal tb_sysclk_p : std_logic := '0';
+ --
+ -- RS232 via USB
+ signal tb_usb_1_cts : std_logic; -- function: RTS output
+ signal tb_usb_1_rts : std_logic := '0'; -- function: CTS input
+ signal tb_usb_1_rx : std_logic; -- function: TX data out
+ signal tb_usb_1_tx : std_logic := '0'; -- function: RX data in
+ --
+ -- 27 MHz, oscillator socket
+ signal tb_user_clock : std_logic := '0';
+ --
+ -- user clock provided per SMA
+ signal tb_user_sma_clock_p : std_logic := '0';
+ signal tb_user_sma_clock_n : std_logic := '0';
+
+
+
+begin
+
+ -- generate clocks
+ tb_sysclk_p <= not tb_sysclk_p after sys_clk_period / 2 when simulation_run;
+ tb_sysclk_n <= not tb_sysclk_n after sys_clk_period / 2 when simulation_run;
+ tb_user_clock <= not tb_user_clock after user_clk_period / 2 when simulation_run;
+
+ -- generate reset
+ tb_cpu_reset <= '1', '0' after 6.66 * sys_clk_period;
+
+
+ -- simulate keypress
+ tb_gpio_button(2) <= '0', '1' after 50 us, '0' after 52 us;
+
+ -- dut
+ top_i0 : entity work.top
+ port map (
+ stop_simulation => tb_stop_simulation, -- : out std_logic;
+ --
+ cpu_reset => tb_cpu_reset, -- : in std_logic;
+ --
+ -- DDR2 memory 128 MB
+ ddr2_a => tb_ddr2_a, -- : out std_logic_vector(12 downto 0);
+ ddr2_ba => tb_ddr2_ba, -- : out std_logic_vector(2 downto 0);
+ ddr2_cas_b => tb_ddr2_cas_b, -- : out std_logic;
+ ddr2_ras_b => tb_ddr2_ras_b, -- : out std_logic;
+ ddr2_we_b => tb_ddr2_we_b, -- : out std_logic;
+ ddr2_cke => tb_ddr2_cke, -- : out std_logic;
+ ddr2_clk_n => tb_ddr2_clk_n, -- : out std_logic;
+ ddr2_clk_p => tb_ddr2_clk_p, -- : out std_logic;
+ ddr2_dq => tb_ddr2_dq, -- : inout std_logic_vector(15 downto 0);
+ ddr2_ldm => tb_ddr2_ldm, -- : out std_logic;
+ ddr2_udm => tb_ddr2_udm, -- : out std_logic;
+ ddr2_ldqs_n => tb_ddr2_ldqs_n, -- : inout std_logic;
+ ddr2_ldqs_p => tb_ddr2_ldqs_p, -- : inout std_logic;
+ ddr2_udqs_n => tb_ddr2_udqs_n, -- : inout std_logic;
+ ddr2_udqs_p => tb_ddr2_udqs_p, -- : inout std_logic;
+ ddr2_odt => tb_ddr2_odt, -- : out std_logic;
+ --
+ -- flash memory
+ flash_a => tb_flash_a, -- : out std_logic_vector(24 downto 0);
+ flash_d => tb_flash_d, -- : inout std_logic_vector(7 downto 3);
+ -- --
+ fpga_d0_din_miso_miso1 => tb_fpga_d0_din_miso_miso1, -- : inout std_logic;
+ fpga_d1_miso2 => tb_fpga_d1_miso2, -- : inout std_logic;
+ fpga_d2_miso3 => tb_fpga_d2_miso3, -- : inout std_logic;
+ flash_we_b => tb_flash_we_b, -- : out std_logic;
+ flash_oe_b => tb_flash_oe_b, -- : out std_logic;
+ flash_ce_b => tb_flash_ce_b, -- : out std_logic;
+ --
+ -- FMC connector
+ -- M2C Mezzanine to Carrier
+ -- C2M Carrier to Mezzanine
+ fmc_clk0_m2c_n => tb_fmc_clk0_m2c_n, -- : in std_logic;
+ fmc_clk0_m2c_p => tb_fmc_clk0_m2c_p, -- : in std_logic;
+ fmc_clk1_m2c_n => tb_fmc_clk1_m2c_n, -- : in std_logic;
+ fmc_clk1_m2c_p => tb_fmc_clk1_m2c_p, -- : in std_logic;
+ iic_scl_main => tb_iic_scl_main, -- : inout std_logic;
+ iic_sda_main => tb_iic_sda_main, -- : inout std_logic;
+ fmc_la00_cc_n => tb_fmc_la00_cc_n, -- : inout std_logic;
+ fmc_la00_cc_p => tb_fmc_la00_cc_p, -- : inout std_logic;
+ fmc_la01_cc_n => tb_fmc_la01_cc_n, -- : inout std_logic;
+ fmc_la01_cc_p => tb_fmc_la01_cc_p, -- : inout std_logic;
+ fmc_la02_n => tb_fmc_la02_n, -- : inout std_logic;
+ fmc_la02_p => tb_fmc_la02_p, -- : inout std_logic;
+ fmc_la03_n => tb_fmc_la03_n, -- : inout std_logic;
+ fmc_la03_p => tb_fmc_la03_p, -- : inout std_logic;
+ fmc_la04_n => tb_fmc_la04_n, -- : inout std_logic;
+ fmc_la04_p => tb_fmc_la04_p, -- : inout std_logic;
+ fmc_la05_n => tb_fmc_la05_n, -- : inout std_logic;
+ fmc_la05_p => tb_fmc_la05_p, -- : inout std_logic;
+ fmc_la06_n => tb_fmc_la06_n, -- : inout std_logic;
+ fmc_la06_p => tb_fmc_la06_p, -- : inout std_logic;
+ fmc_la07_n => tb_fmc_la07_n, -- : inout std_logic;
+ fmc_la07_p => tb_fmc_la07_p, -- : inout std_logic;
+ fmc_la08_n => tb_fmc_la08_n, -- : inout std_logic;
+ fmc_la08_p => tb_fmc_la08_p, -- : inout std_logic;
+ fmc_la09_n => tb_fmc_la09_n, -- : inout std_logic;
+ fmc_la09_p => tb_fmc_la09_p, -- : inout std_logic;
+ fmc_la10_n => tb_fmc_la10_n, -- : inout std_logic;
+ fmc_la10_p => tb_fmc_la10_p, -- : inout std_logic;
+ fmc_la11_n => tb_fmc_la11_n, -- : inout std_logic;
+ fmc_la11_p => tb_fmc_la11_p, -- : inout std_logic;
+ fmc_la12_n => tb_fmc_la12_n, -- : inout std_logic;
+ fmc_la12_p => tb_fmc_la12_p, -- : inout std_logic;
+ fmc_la13_n => tb_fmc_la13_n, -- : inout std_logic;
+ fmc_la13_p => tb_fmc_la13_p, -- : inout std_logic;
+ fmc_la14_n => tb_fmc_la14_n, -- : inout std_logic;
+ fmc_la14_p => tb_fmc_la14_p, -- : inout std_logic;
+ fmc_la15_n => tb_fmc_la15_n, -- : inout std_logic;
+ fmc_la15_p => tb_fmc_la15_p, -- : inout std_logic;
+ fmc_la16_n => tb_fmc_la16_n, -- : inout std_logic;
+ fmc_la16_p => tb_fmc_la16_p, -- : inout std_logic;
+ fmc_la17_cc_n => tb_fmc_la17_cc_n, -- : inout std_logic;
+ fmc_la17_cc_p => tb_fmc_la17_cc_p, -- : inout std_logic;
+ fmc_la18_cc_n => tb_fmc_la18_cc_n, -- : inout std_logic;
+ fmc_la18_cc_p => tb_fmc_la18_cc_p, -- : inout std_logic;
+ fmc_la19_n => tb_fmc_la19_n, -- : inout std_logic;
+ fmc_la19_p => tb_fmc_la19_p, -- : inout std_logic;
+ fmc_la20_n => tb_fmc_la20_n, -- : inout std_logic;
+ fmc_la20_p => tb_fmc_la20_p, -- : inout std_logic;
+ fmc_la21_n => tb_fmc_la21_n, -- : inout std_logic;
+ fmc_la21_p => tb_fmc_la21_p, -- : inout std_logic;
+ fmc_la22_n => tb_fmc_la22_n, -- : inout std_logic;
+ fmc_la22_p => tb_fmc_la22_p, -- : inout std_logic;
+ fmc_la23_n => tb_fmc_la23_n, -- : inout std_logic;
+ fmc_la23_p => tb_fmc_la23_p, -- : inout std_logic;
+ fmc_la24_n => tb_fmc_la24_n, -- : inout std_logic;
+ fmc_la24_p => tb_fmc_la24_p, -- : inout std_logic;
+ fmc_la25_n => tb_fmc_la25_n, -- : inout std_logic;
+ fmc_la25_p => tb_fmc_la25_p, -- : inout std_logic;
+ fmc_la26_n => tb_fmc_la26_n, -- : inout std_logic;
+ fmc_la26_p => tb_fmc_la26_p, -- : inout std_logic;
+ fmc_la27_n => tb_fmc_la27_n, -- : inout std_logic;
+ fmc_la27_p => tb_fmc_la27_p, -- : inout std_logic;
+ fmc_la28_n => tb_fmc_la28_n, -- : inout std_logic;
+ fmc_la28_p => tb_fmc_la28_p, -- : inout std_logic;
+ fmc_la29_n => tb_fmc_la29_n, -- : inout std_logic;
+ fmc_la29_p => tb_fmc_la29_p, -- : inout std_logic;
+ fmc_la30_n => tb_fmc_la30_n, -- : inout std_logic;
+ fmc_la30_p => tb_fmc_la30_p, -- : inout std_logic;
+ fmc_la31_n => tb_fmc_la31_n, -- : inout std_logic;
+ fmc_la31_p => tb_fmc_la31_p, -- : inout std_logic;
+ fmc_la32_n => tb_fmc_la32_n, -- : inout std_logic;
+ fmc_la32_p => tb_fmc_la32_p, -- : inout std_logic;
+ fmc_la33_n => tb_fmc_la33_n, -- : inout std_logic;
+ fmc_la33_p => tb_fmc_la33_p, -- : inout std_logic;
+ fmc_prsnt_m2c_l => tb_fmc_prsnt_m2c_l, -- : in std_logic;
+ fmc_pwr_good_flash_rst_b => tb_fmc_pwr_good_flash_rst_b, -- : out std_logic;
+ --
+ fpga_awake => tb_fpga_awake, -- : out std_logic;
+ fpga_cclk => tb_fpga_cclk, -- : out std_logic;
+ fpga_cmp_clk => tb_fpga_cmp_clk, -- : in std_logic;
+ fpga_cmp_mosi => tb_fpga_cmp_mosi, -- : in std_logic;
+ -- --
+ fpga_hswapen => tb_fpga_hswapen, -- : in std_logic;
+ fpga_init_b => tb_fpga_init_b, -- : out std_logic;
+ fpga_m0_cmp_miso => tb_fpga_m0_cmp_miso, -- : in std_logic;
+ fpga_m1 => tb_fpga_m1, -- : in std_logic;
+ fpga_mosi_csi_b_miso0 => tb_fpga_mosi_csi_b_miso0, -- : inout std_logic;
+ fpga_onchip_term1 => tb_fpga_onchip_term1, -- : inout std_logic;
+ fpga_onchip_term2 => tb_fpga_onchip_term2, -- : inout std_logic;
+ fpga_vtemp => tb_fpga_vtemp, -- : in std_logic;
+ --
+ -- GPIOs
+ gpio_button => tb_gpio_button, -- : in std_logic_vector(3 downto 0);
+ gpio_header_ls => tb_gpio_header_ls, -- : inout std_logic_vector(7 downto 0);
+ gpio_led => tb_gpio_led, -- : out std_logic_vector(3 downto 0);
+ gpio_switch => tb_gpio_switch, -- : in std_logic_vector(3 downto 0);
+ --
+ -- Ethernet Gigabit PHY
+ phy_col => tb_phy_col, -- : in std_logic;
+ phy_crs => tb_phy_crs, -- : in std_logic;
+ phy_int => tb_phy_int, -- : in std_logic;
+ phy_mdc => tb_phy_mdc, -- : out std_logic;
+ phy_mdio => tb_phy_mdio, -- : inout std_logic;
+ phy_reset => tb_phy_reset, -- : out std_logic;
+ phy_rxclk => tb_phy_rxclk, -- : in std_logic;
+ phy_rxctl_rxdv => tb_phy_rxctl_rxdv, -- : in std_logic;
+ phy_rxd => tb_phy_rxd, -- : in std_logic_vector(7 downto 0);
+ phy_rxer => tb_phy_rxer, -- : in std_logic;
+ phy_txclk => tb_phy_txclk, -- : in std_logic;
+ phy_txctl_txen => tb_phy_txctl_txen, -- : out std_logic;
+ phy_txc_gtxclk => tb_phy_txc_gtxclk, -- : out std_logic;
+ phy_txd => tb_phy_txd, -- : out std_logic_vector(7 downto 0);
+ phy_txer => tb_phy_txer, -- : out std_logic;
+ --
+ --
+ spi_cs_b => tb_spi_cs_b, -- : out std_logic;
+ --
+ -- 200 MHz oscillator, jitter 50 ppm
+ sysclk_n => tb_sysclk_n, -- : in std_logic;
+ sysclk_p => tb_sysclk_p, -- : in std_logic;
+ --
+ -- RS232 via USB
+ usb_1_cts => tb_usb_1_cts, -- : out std_logic;
+ usb_1_rts => tb_usb_1_rts, -- : in std_logic;
+ usb_1_rx => tb_usb_1_rx, -- : out std_logic;
+ usb_1_tx => tb_usb_1_tx, -- : in std_logic;
+ --
+ -- 27 MHz, oscillator socket
+ user_clock => tb_user_clock, -- : in std_logic;
+ --
+ -- user clock provided per SMA
+ user_sma_clock_p => tb_user_sma_clock_p, -- : in std_logic;
+ user_sma_clock_n => tb_user_sma_clock_n -- : in std_logic
+ );
+
+
+ -- check for simulation stopping
+ process (tb_stop_simulation)
+ begin
+ if tb_stop_simulation = '1' then
+ report "Simulation end." severity note;
+ simulation_run <= false;
+ end if;
+ end process;
+
+
+end architecture testbench;
+
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