diff options
| author | Bert Lange <b.lange@hzdr.de> | 2011-10-13 12:37:49 +0200 |
|---|---|---|
| committer | Bert Lange <b.lange@hzdr.de> | 2011-10-13 12:37:49 +0200 |
| commit | 0bf783475d6610a14f71884737aeae33246bb9be (patch) | |
| tree | 8545a4d2e76761131f4945db6eeca7b563f7161e /zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16 | |
| parent | bf4405c61a9c010a8e888da678436a282b9551a3 (diff) | |
| download | zpu-0bf783475d6610a14f71884737aeae33246bb9be.zip zpu-0bf783475d6610a14f71884737aeae33246bb9be.tar.gz | |
add: ZPU reference designs for zealot
Diffstat (limited to 'zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16')
11 files changed, 1600 insertions, 0 deletions
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/clean_up.sh b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/clean_up.sh new file mode 100755 index 0000000..3855f16 --- /dev/null +++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/clean_up.sh @@ -0,0 +1,16 @@ +#!/bin/sh + +# ise build stuff +rm -rf build +rm -f top.bit + +# modelsim compile stuff +rm -rf work +rm -rf zpu + +# modelsim simulation stuff +rm -f vsim.wlf +rm -f transcript +rm -f zpu_trace.log +rm -f zpu_med1_io.log +rm -f zpu_small1_io.log diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation.sh b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation.sh new file mode 100755 index 0000000..febf588 --- /dev/null +++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation.sh @@ -0,0 +1,48 @@ +#!/bin/sh + +# need project files: +# run.do +# wave.do + +# need ModelSim tools: +# vlib +# vcom +# vsim + + +echo "###############" +echo "compile zpu lib" +echo "###############" +vlib zpu +vcom -work zpu ../../roms/hello_dbram.vhdl +vcom -work zpu ../../roms/hello_bram.vhdl +#vcom -work zpu ../../roms/dmips_dbram.vhdl +#vcom -work zpu ../../roms/dmips_bram.vhdl + +vcom -work zpu ../../roms/rom_pkg.vhdl +vcom -work zpu ../../zpu_pkg.vhdl +vcom -work zpu ../../zpu_small.vhdl +vcom -work zpu ../../zpu_medium.vhdl +vcom -work zpu ../../helpers/zpu_small1.vhdl +vcom -work zpu ../../helpers/zpu_med1.vhdl +vcom -work zpu ../../devices/txt_util.vhdl +vcom -work zpu ../../devices/phi_io.vhdl +vcom -work zpu ../../devices/timer.vhdl +vcom -work zpu ../../devices/rx_unit.vhdl +vcom -work zpu ../../devices/tx_unit.vhdl +vcom -work zpu ../../devices/br_gen.vhdl +vcom -work zpu ../../devices/trace.vhdl + + +echo "################" +echo "compile work lib" +echo "################" +vlib work +vcom top.vhd +vcom top_tb.vhd + + +echo "###################" +echo "start simulator gui" +echo "###################" +vsim -gui top_tb -do simulation_config/run.do diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/run.do b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/run.do new file mode 100644 index 0000000..acc1710 --- /dev/null +++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/run.do @@ -0,0 +1,2 @@ +do wave.do +run -all diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/wave.do b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/wave.do new file mode 100644 index 0000000..6a3731d --- /dev/null +++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/simulation_config/wave.do @@ -0,0 +1,163 @@ +onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /top_tb/simulation_run
+add wave -noupdate /top_tb/tb_cpu_reset
+add wave -noupdate /top_tb/tb_sysclk_n
+add wave -noupdate /top_tb/tb_sysclk_p
+add wave -noupdate /top_tb/tb_user_clock
+add wave -noupdate -divider <NULL>
+add wave -noupdate /top_tb/top_i0/clk
+add wave -noupdate -divider <NULL>
+add wave -noupdate /top_tb/tb_gpio_button
+add wave -noupdate /top_tb/tb_gpio_header_ls
+add wave -noupdate /top_tb/tb_gpio_led
+add wave -noupdate /top_tb/tb_gpio_switch
+add wave -noupdate -expand -group USB/RS232 /top_tb/tb_usb_1_cts
+add wave -noupdate -expand -group USB/RS232 /top_tb/tb_usb_1_rts
+add wave -noupdate -expand -group USB/RS232 /top_tb/tb_usb_1_rx
+add wave -noupdate -expand -group USB/RS232 /top_tb/tb_usb_1_tx
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_a
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_ba
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_cas_b
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_ras_b
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_we_b
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_cke
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_clk_n
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_clk_p
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_dq
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_ldm
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_udm
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_ldqs_n
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_ldqs_p
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_udqs_n
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_udqs_p
+add wave -noupdate -group DDR2 /top_tb/tb_ddr2_odt
+add wave -noupdate -group {Flash memory} /top_tb/tb_flash_a
+add wave -noupdate -group {Flash memory} /top_tb/tb_flash_d
+add wave -noupdate -group {Flash memory} /top_tb/tb_fpga_d0_din_miso_miso1
+add wave -noupdate -group {Flash memory} /top_tb/tb_fpga_d1_miso2
+add wave -noupdate -group {Flash memory} /top_tb/tb_fpga_d2_miso3
+add wave -noupdate -group {Flash memory} /top_tb/tb_flash_we_b
+add wave -noupdate -group {Flash memory} /top_tb/tb_flash_oe_b
+add wave -noupdate -group {Flash memory} /top_tb/tb_flash_ce_b
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_clk0_m2c_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_clk0_m2c_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_clk1_m2c_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_clk1_m2c_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_iic_scl_main
+add wave -noupdate -group {FMC connector} /top_tb/tb_iic_sda_main
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la00_cc_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la00_cc_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la01_cc_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la01_cc_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la02_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la02_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la03_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la03_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la04_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la04_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la05_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la05_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la06_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la06_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la07_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la07_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la08_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la08_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la09_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la09_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la10_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la10_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la11_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la11_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la12_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la12_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la13_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la13_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la14_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la14_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la15_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la15_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la16_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la16_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la17_cc_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la17_cc_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la18_cc_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la18_cc_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la19_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la19_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la20_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la20_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la21_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la21_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la22_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la22_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la23_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la23_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la24_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la24_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la25_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la25_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la26_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la26_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la27_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la27_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la28_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la28_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la29_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la29_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la30_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la30_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la31_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la31_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la32_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la32_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la33_n
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_la33_p
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_prsnt_m2c_l
+add wave -noupdate -group {FMC connector} /top_tb/tb_fmc_pwr_good_flash_rst_b
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_awake
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_cclk
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_cmp_clk
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_cmp_mosi
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_hswapen
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_init_b
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_m0_cmp_miso
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_m1
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_mosi_csi_b_miso0
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_onchip_term1
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_onchip_term2
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_fpga_vtemp
+add wave -noupdate -group {special FPGA pins} /top_tb/tb_spi_cs_b
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_col
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_crs
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_int
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_mdc
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_mdio
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_reset
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_rxclk
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_rxctl_rxdv
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_rxd
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_rxer
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_txclk
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_txctl_txen
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_txc_gtxclk
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_txd
+add wave -noupdate -group {Ethernet phy} /top_tb/tb_phy_txer
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {1393701250 ps} 0} {{Cursor 2} {138750 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ps} {327615 ps}
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis.sh b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis.sh new file mode 100755 index 0000000..2f89415 --- /dev/null +++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis.sh @@ -0,0 +1,36 @@ +#!/bin/sh + +# need project files: +# top.xst +# top.prj +# top.ut + +# need Xilinx tools: +# xst +# ngdbuild +# map +# par +# trce +# bitgen + +echo "########################" +echo "generate build directory" +echo "########################" +mkdir build +cd build +mkdir tmp + +echo "###############" +echo "start processes" +echo "###############" +xst -ifn "../synthesis_config/top.xst" -ofn "top.syr" +ngdbuild -dd _ngo -nt timestamp -uc ../synthesis_config/xilinx-sp601-xc6slx16.ucf -p xc6slx16-csg324-2 top.ngc top.ngd +map -p xc6slx16-csg324-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o top_map.ncd top.ngd top.pcf +par -ol high -mt off top_map.ncd -w top.ncd top.pcf +trce -v 3 -s 2 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf +bitgen -f ../synthesis_config/top.ut top.ncd + +echo "###########" +echo "get bitfile" +echo "###########" +cp top.bit .. diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.prj b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.prj new file mode 100644 index 0000000..81d56ef --- /dev/null +++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.prj @@ -0,0 +1,18 @@ +vhdl work ../top.vhd +vhdl zpu ../../../zpu_pkg.vhdl +vhdl zpu ../../../zpu_small.vhdl +vhdl zpu ../../../zpu_medium.vhdl +vhdl zpu ../../../roms/rom_pkg.vhdl +#vhdl zpu ../../../roms/hello_dbram.vhdl +#vhdl zpu ../../../roms/hello_bram.vhdl +vhdl zpu ../../../roms/dmips_dbram.vhdl +vhdl zpu ../../../roms/dmips_bram.vhdl +vhdl zpu ../../../helpers/zpu_small1.vhdl +vhdl zpu ../../../helpers/zpu_med1.vhdl +vhdl zpu ../../../devices/txt_util.vhdl +vhdl zpu ../../../devices/phi_io.vhdl +vhdl zpu ../../../devices/timer.vhdl +vhdl zpu ../../../devices/rx_unit.vhdl +vhdl zpu ../../../devices/tx_unit.vhdl +vhdl zpu ../../../devices/br_gen.vhdl +vhdl zpu ../../../devices/trace.vhdl diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.ut b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.ut new file mode 100644 index 0000000..ea9319f --- /dev/null +++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.ut @@ -0,0 +1,30 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g CRC:Enable +-g Reset_on_err:No +-g ConfigRate:2 +-g ProgPin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g ExtMasterCclk_en:No +-g SPI_buswidth:1 +-g TIMER_CFG:0xFFFF +-g multipin_wakeup:No +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No +-g en_sw_gsr:No +-g drive_awake:No +-g sw_clk:Startupclk +-g sw_gwe_cycle:5 +-g sw_gts_cycle:4 diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.xst b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.xst new file mode 100644 index 0000000..8952afe --- /dev/null +++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/top.xst @@ -0,0 +1,53 @@ +set -tmpdir "tmp" +set -xsthdpdir "xst" +run +-ifn ../synthesis_config/top.prj +-ifmt mixed +-ofn top +-ofmt NGC +-p xc6slx16-2-csg324 +-top top +-opt_mode Speed +-opt_level 1 +-power NO +-iuc NO +-keep_hierarchy No +-netlist_hierarchy As_Optimized +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case Maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-dsp_utilization_ratio 100 +-lc Auto +-reduce_control_sets Auto +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style LUT +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-shreg_extract YES +-rom_style Auto +-auto_bram_packing NO +-resource_sharing YES +-async_to_sync NO +-shreg_min_size 2 +-use_dsp48 Auto +-iobuf YES +-max_fanout 100000 +-bufg 16 +-register_duplication YES +-register_balancing No +-optimize_primitives NO +-use_clock_enable Auto +-use_sync_set Auto +-use_sync_reset Auto +-iob Auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/xilinx-sp601-xc6slx16.ucf b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/xilinx-sp601-xc6slx16.ucf new file mode 100644 index 0000000..c54705a --- /dev/null +++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis_config/xilinx-sp601-xc6slx16.ucf @@ -0,0 +1,303 @@ +############################################################ +# SPARTAN-6 SP601 Board Constraints File +# +# Family: Spartan6 +# Device: XC6SLX16 +# Package: CSG324 +# Speed: -2 +# +# +# Bank Voltage +# Bank 0: 2.5 V +# Bank 1: 2.5 V +# Bank 2: 2.5 V +# Bank 3: 1.8 V +# VCCAUX: 2.5 V + +# following pins are connected to VCC1V8/2: +# N3, M5, C1 + + +############################################################ +## clock/timing constraints +############################################################ + +TIMESPEC "TS_SYSCLK" = PERIOD "SYSCLK" 200 MHz HIGH 50 %; +TIMESPEC "TS_USER_SMA_CLOCK" = PERIOD "USER_SMA_CLOCK" 50 MHz HIGH 50 %; +NET "USER_CLOCK" PERIOD = 27 MHz HIGH 40%; + + +############################################################ +## pin placement constraints +############################################################ + +NET "CPU_RESET" LOC = "N4"; + +## 128 MB DDR2 Component Memory +NET "DDR2_A<12>" LOC ="G6"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_A<11>" LOC ="D3"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_A<10>" LOC ="F4"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_A<9>" LOC ="D1"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_A<8>" LOC ="D2"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_A<7>" LOC ="H6"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_A<6>" LOC ="H3"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_A<5>" LOC ="H4"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_A<4>" LOC ="F3"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_A<3>" LOC ="L7"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_A<2>" LOC ="H5"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_A<1>" LOC ="J6"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_A<0>" LOC ="J7"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_DQ<15>" LOC ="U1"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_DQ<14>" LOC ="U2"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_DQ<13>" LOC ="T1"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_DQ<12>" LOC ="T2"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_DQ<11>" LOC ="N1"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_DQ<10>" LOC ="N2"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_DQ<9>" LOC ="M1"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_DQ<8>" LOC ="M3"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_DQ<7>" LOC ="J1"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_DQ<6>" LOC ="J3"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_DQ<5>" LOC ="H1"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_DQ<4>" LOC ="H2"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_DQ<3>" LOC ="K1"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_DQ<2>" LOC ="K2"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_DQ<1>" LOC ="L1"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_DQ<0>" LOC ="L2"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_WE_B" LOC ="E3"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_UDQS_P" LOC ="P2"; # | IOSTANDARD = DIFF_SSTL18_II; +NET "DDR2_UDQS_N" LOC ="P1"; # | IOSTANDARD = DIFF_SSTL18_II; +NET "DDR2_UDM" LOC ="K4"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_RAS_B" LOC ="L5"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_ODT" LOC ="K6"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_LDQS_P" LOC ="L4"; # | IOSTANDARD = DIFF_SSTL18_II; +NET "DDR2_LDQS_N" LOC ="L3"; # | IOSTANDARD = DIFF_SSTL18_II; +NET "DDR2_LDM" LOC ="K3"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_CLK_P" LOC ="G3"; # | IOSTANDARD = DIFF_SSTL18_II; +NET "DDR2_CLK_N" LOC ="G1"; # | IOSTANDARD = DIFF_SSTL18_II; +NET "DDR2_CKE" LOC ="H7"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_CAS_B" LOC ="K5"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_BA<2>" LOC ="E1"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_BA<1>" LOC ="F1"; # | IOSTANDARD = SSTL18_II ; +NET "DDR2_BA<0>" LOC ="F2"; # | IOSTANDARD = SSTL18_II ; + +## Flash Memory +NET "FLASH_A<0>" LOC = "K18"; +NET "FLASH_A<1>" LOC = "K17"; +NET "FLASH_A<2>" LOC = "J18"; +NET "FLASH_A<3>" LOC = "J16"; +NET "FLASH_A<4>" LOC = "G18"; +NET "FLASH_A<5>" LOC = "G16"; +NET "FLASH_A<6>" LOC = "H16"; +NET "FLASH_A<7>" LOC = "H15"; +NET "FLASH_A<8>" LOC = "H14"; +NET "FLASH_A<9>" LOC = "H13"; +NET "FLASH_A<10>" LOC = "F18"; +NET "FLASH_A<11>" LOC = "F17"; +NET "FLASH_A<12>" LOC = "K13"; +NET "FLASH_A<13>" LOC = "K12"; +NET "FLASH_A<14>" LOC = "E18"; +NET "FLASH_A<15>" LOC = "E16"; +NET "FLASH_A<16>" LOC = "G13"; +NET "FLASH_A<17>" LOC = "H12"; +NET "FLASH_A<18>" LOC = "D18"; +NET "FLASH_A<19>" LOC = "D17"; +NET "FLASH_A<20>" LOC = "G14"; +NET "FLASH_A<21>" LOC = "F14"; +NET "FLASH_A<22>" LOC = "C18"; +NET "FLASH_A<23>" LOC = "C17"; +NET "FLASH_A<24>" LOC = "F16"; +#NET "FLASH_D<0>" LOC = "R13" | SLEW = "SLOW" | DRIVE = 2; +#NET "FLASH_D<1>" LOC = "T14" | SLEW = "SLOW" | DRIVE = 2; +#NET "FLASH_D<2>" LOC = "V14" | SLEW = "SLOW" | DRIVE = 2; +NET "FLASH_D<3>" LOC = "U5" | SLEW = "SLOW" | DRIVE = 2; +NET "FLASH_D<4>" LOC = "V5" | SLEW = "SLOW" | DRIVE = 2; +NET "FLASH_D<5>" LOC = "R3" | SLEW = "SLOW" | DRIVE = 2; +NET "FLASH_D<6>" LOC = "T3" | SLEW = "SLOW" | DRIVE = 2; +NET "FLASH_D<7>" LOC = "R5" | SLEW = "SLOW" | DRIVE = 2; +NET "FLASH_OE_B" LOC = "L18"; +NET "FLASH_WE_B" LOC = "M16"; +NET "FLASH_CE_B" LOC = "L17"; + +# FMC-Connector, Bank 0,2 (M2C = Mezzanine to Carrier, C2M = Carrier to Mezzanine) +NET "FMC_CLK0_M2C_N" LOC = "A10"; +NET "FMC_CLK0_M2C_P" LOC = "C10"; +NET "FMC_CLK1_M2C_N" LOC = "V9" ; +NET "FMC_CLK1_M2C_P" LOC = "T9" ; +NET "FMC_LA00_CC_N" LOC = "C9" ; +NET "FMC_LA00_CC_P" LOC = "D9" ; +NET "FMC_LA01_CC_N" LOC = "C11"; +NET "FMC_LA01_CC_P" LOC = "D11"; +NET "FMC_LA02_N" LOC = "A15"; +NET "FMC_LA02_P" LOC = "C15"; +NET "FMC_LA03_N" LOC = "A13"; +NET "FMC_LA03_P" LOC = "C13"; +NET "FMC_LA04_N" LOC = "A16"; +NET "FMC_LA04_P" LOC = "B16"; +NET "FMC_LA05_N" LOC = "A14"; +NET "FMC_LA05_P" LOC = "B14"; +NET "FMC_LA06_N" LOC = "C12"; +NET "FMC_LA06_P" LOC = "D12"; +NET "FMC_LA07_N" LOC = "E8" ; +NET "FMC_LA07_P" LOC = "E7" ; +NET "FMC_LA08_N" LOC = "E11"; +NET "FMC_LA08_P" LOC = "F11"; +NET "FMC_LA09_N" LOC = "F10"; +NET "FMC_LA09_P" LOC = "G11"; +NET "FMC_LA10_N" LOC = "C8" ; +NET "FMC_LA10_P" LOC = "D8" ; +NET "FMC_LA11_N" LOC = "A12"; +NET "FMC_LA11_P" LOC = "B12"; +NET "FMC_LA12_N" LOC = "C6" ; +NET "FMC_LA12_P" LOC = "D6" ; +NET "FMC_LA13_N" LOC = "A11"; +NET "FMC_LA13_P" LOC = "B11"; +NET "FMC_LA14_N" LOC = "A2" ; +NET "FMC_LA14_P" LOC = "B2" ; +NET "FMC_LA15_N" LOC = "F9" ; +NET "FMC_LA15_P" LOC = "G9" ; +NET "FMC_LA16_N" LOC = "A7" ; +NET "FMC_LA16_P" LOC = "C7" ; +NET "FMC_LA17_CC_N" LOC = "T8" ; +NET "FMC_LA17_CC_P" LOC = "R8" ; +NET "FMC_LA18_CC_N" LOC = "T10"; +NET "FMC_LA18_CC_P" LOC = "R10"; +NET "FMC_LA19_N" LOC = "P7" ; +NET "FMC_LA19_P" LOC = "N6" ; +NET "FMC_LA20_N" LOC = "P8" ; +NET "FMC_LA20_P" LOC = "N7" ; +NET "FMC_LA21_N" LOC = "V4" ; +NET "FMC_LA21_P" LOC = "T4" ; +NET "FMC_LA22_N" LOC = "T7" ; +NET "FMC_LA22_P" LOC = "R7" ; +NET "FMC_LA23_N" LOC = "P6" ; +NET "FMC_LA23_P" LOC = "N5" ; +NET "FMC_LA24_N" LOC = "V8" ; +NET "FMC_LA24_P" LOC = "U8" ; +NET "FMC_LA25_N" LOC = "N11"; +NET "FMC_LA25_P" LOC = "M11"; +NET "FMC_LA26_N" LOC = "V7" ; +NET "FMC_LA26_P" LOC = "U7" ; +NET "FMC_LA27_N" LOC = "T11"; +NET "FMC_LA27_P" LOC = "R11"; +NET "FMC_LA28_N" LOC = "V11"; +NET "FMC_LA28_P" LOC = "U11"; +NET "FMC_LA29_N" LOC = "N8" ; +NET "FMC_LA29_P" LOC = "M8" ; +NET "FMC_LA30_N" LOC = "V12"; +NET "FMC_LA30_P" LOC = "T12"; +NET "FMC_LA31_N" LOC = "V6" ; +NET "FMC_LA31_P" LOC = "T6" ; +NET "FMC_LA32_N" LOC = "V15"; +NET "FMC_LA32_P" LOC = "U15"; +NET "FMC_LA33_N" LOC = "N9" ; +NET "FMC_LA33_P" LOC = "M10"; +NET "FMC_PRSNT_M2C_L" LOC = "U13"; +NET "FMC_PWR_GOOD_FLASH_RST_B" LOC = "B3"; + +# special FPGA pins +NET "FPGA_AWAKE" LOC = "P15"| SLEW = SLOW | DRIVE = 2; +NET "FPGA_CCLK" LOC = "R15"; +NET "FPGA_CMP_CLK" LOC = "U16"; +NET "FPGA_CMP_MOSI" LOC = "V16"; +NET "FPGA_D0_DIN_MISO_MISO1" LOC = "R13" | DRIVE = 4; ## 8 on U17 (thru series R187 100 ohm), 33 on U10, 6 on J12 +NET "FPGA_D1_MISO2" LOC = "T14" | DRIVE = 4; ## 9 on U17 (thru series R186 100 ohm), 35 on U10, 3 on J12 +NET "FPGA_D2_MISO3" LOC = "V14" | DRIVE = 4; ## 1 on U17, 38 on U10, 2 on J12 +NET "FPGA_HSWAPEN" LOC = "D4"; +NET "FPGA_INIT_B" LOC = "U3" | SLEW = SLOW | DRIVE = 4; +NET "FPGA_M0_CMP_MISO" LOC = "T15"; +NET "FPGA_M1" LOC = "N12"; +NET "FPGA_MOSI_CSI_B_MISO0" LOC = "T13" | DRIVE = 4; +NET "FPGA_ONCHIP_TERM1" LOC = "L6"; +NET "FPGA_ONCHIP_TERM2" LOC = "C2"; +NET "FPGA_VTEMP" LOC = "P3"; + +## Pushbuttons, Bank 3, external Pulldown +NET "GPIO_BUTTON<0>" LOC = "P4" ; +NET "GPIO_BUTTON<1>" LOC = "F6" ; +NET "GPIO_BUTTON<2>" LOC = "E4" ; +NET "GPIO_BUTTON<3>" LOC = "F5" ; +NET "GPIO_BUTTON*" TIG; + +## 8 Pin GPIO Header J13, Bank 0,1,2 +NET "GPIO_HEADER_LS<0>" LOC = "N17"| SLEW = SLOW | DRIVE = 4 ; +NET "GPIO_HEADER_LS<1>" LOC = "M18"| SLEW = SLOW | DRIVE = 4 ; +NET "GPIO_HEADER_LS<2>" LOC = "A3" | SLEW = SLOW | DRIVE = 4 ; +NET "GPIO_HEADER_LS<3>" LOC = "L15"| SLEW = SLOW | DRIVE = 4 ; +NET "GPIO_HEADER_LS<4>" LOC = "F15"| SLEW = SLOW | DRIVE = 4 ; +NET "GPIO_HEADER_LS<5>" LOC = "B4" | SLEW = SLOW | DRIVE = 4 ; +NET "GPIO_HEADER_LS<6>" LOC = "F13"| SLEW = SLOW | DRIVE = 4 ; +NET "GPIO_HEADER_LS<7>" LOC = "P12"| SLEW = SLOW | DRIVE = 4 ; + +## 4 GPIO LEDs, Bank 0 +NET "GPIO_LED<0>" LOC = "E13"| SLEW = SLOW | DRIVE = 4 ; +NET "GPIO_LED<1>" LOC = "C14"| SLEW = SLOW | DRIVE = 4 ; +NET "GPIO_LED<2>" LOC = "C4" | SLEW = SLOW | DRIVE = 4 ; +NET "GPIO_LED<3>" LOC = "A4" | SLEW = SLOW | DRIVE = 4 ; +NET "GPIO_LED*" TIG; + +## GPIO Dip Switches, Bank 0,2, external Pulldown +NET "GPIO_SWITCH<0>" LOC = "D14"; +NET "GPIO_SWITCH<1>" LOC = "E12"; +NET "GPIO_SWITCH<2>" LOC = "F12"; +NET "GPIO_SWITCH<3>" LOC = "V13"; +NET "GPIO_SWITCH*" TIG; + +## IIC Bus +NET "IIC_SCL_MAIN" LOC = "P11"; +NET "IIC_SDA_MAIN" LOC = "N10"; + +## 10/100/1000 Tri-Speed Ethernet PHY +NET "PHY_COL" LOC = "L14"; +NET "PHY_CRS" LOC = "M13"; +NET "PHY_INT" LOC = "J13"; +NET "PHY_MDC" LOC = "N14" | SLEW = SLOW | DRIVE = 4; +NET "PHY_MDIO" LOC = "P16" | SLEW = SLOW | DRIVE = 4; +NET "PHY_RESET" LOC = "L13"; +NET "PHY_RXCLK" LOC = "L16"; +NET "PHY_RXCTL_RXDV" LOC = "N18"; +NET "PHY_RXD<0>" LOC = "M14"; +NET "PHY_RXD<1>" LOC = "U18"; +NET "PHY_RXD<2>" LOC = "U17"; +NET "PHY_RXD<3>" LOC = "T18"; +NET "PHY_RXD<4>" LOC = "T17"; +NET "PHY_RXD<5>" LOC = "N16"; +NET "PHY_RXD<6>" LOC = "N15"; +NET "PHY_RXD<7>" LOC = "P18"; +NET "PHY_RXER" LOC = "P17"; +NET "PHY_TXCLK" LOC = "B9" ; +NET "PHY_TXCTL_TXEN" LOC = "B8" | SLEW = SLOW | DRIVE = 4; +NET "PHY_TXC_GTXCLK" LOC = "A9" ; +NET "PHY_TXD<0>" LOC = "F8" | SLEW = SLOW | DRIVE = 4; +NET "PHY_TXD<1>" LOC = "G8" | SLEW = SLOW | DRIVE = 4; +NET "PHY_TXD<2>" LOC = "A6" | SLEW = SLOW | DRIVE = 4; +NET "PHY_TXD<3>" LOC = "B6" | SLEW = SLOW | DRIVE = 4; +NET "PHY_TXD<4>" LOC = "E6" | SLEW = SLOW | DRIVE = 4; +NET "PHY_TXD<5>" LOC = "F7" | SLEW = SLOW | DRIVE = 4; +NET "PHY_TXD<6>" LOC = "A5" | SLEW = SLOW | DRIVE = 4; +NET "PHY_TXD<7>" LOC = "C5" | SLEW = SLOW | DRIVE = 4; +NET "PHY_TXER" LOC = "A8" | SLEW = SLOW | DRIVE = 4; + +## SPI x4 Flash +NET "SPI_CS_B" LOC = "V3"; + +## 200 MHz oscillator (differential) +NET "SYSCLK_N" LOC = "K16"| IOSTANDARD = LVDS_33 | TNM_NET = "SYSCLK"; +NET "SYSCLK_P" LOC = "K15"| IOSTANDARD = LVDS_33 | TNM_NET = "SYSCLK"; + +## USB-UART +## this names are real net names +NET "USB_1_CTS" LOC = "U10"| DRIVE = 4 | SLEW = SLOW; # RTS output +NET "USB_1_RTS" LOC = "T5" ; # CTS input +NET "USB_1_RX" LOC = "L12"| DRIVE = 4 | SLEW = SLOW; # TX data out +NET "USB_1_TX" LOC = "K14"; # RX data in + +## 27 MHz +NET "USER_CLOCK" LOC = "V10"| IOSTANDARD = LVCMOS33 ; +## +NET "USER_SMA_CLOCK_N" LOC = "H18"| TNM_NET = "USER_SMA_CLOCK"; +NET "USER_SMA_CLOCK_P" LOC = "H17"| TNM_NET = "USER_SMA_CLOCK"; + +# pins used for voltage termination +CONFIG PROHIBIT = C1; +CONFIG PROHIBIT = M5; +CONFIG PROHIBIT = N3; diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top.vhd b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top.vhd new file mode 100644 index 0000000..120b1cf --- /dev/null +++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top.vhd @@ -0,0 +1,533 @@ +-- top module of +-- SP601 evaluation board +-- +-- using following external connections: +-- +-- cpu_reset (SW9) reset +-- LEDs output +-- USB_UART communication +-- + + +library ieee; +use ieee.std_logic_1164.all; + +library zpu; +use zpu.zpupkg.all; -- zpu_dbgo_t + +library unisim; +use unisim.vcomponents.ibufgds; +use unisim.vcomponents.dcm_sp; + + +entity top is + port ( + -- pragma translate_off + stop_simulation : out std_logic; + -- pragma translate_on + -- + cpu_reset : in std_logic; -- SW9 pushbutton (active-high) + -- + -- DDR2 memory 128 MB + ddr2_a : out std_logic_vector(12 downto 0); + ddr2_ba : out std_logic_vector(2 downto 0); + ddr2_cas_b : out std_logic; + ddr2_ras_b : out std_logic; + ddr2_we_b : out std_logic; + ddr2_cke : out std_logic; + ddr2_clk_n : out std_logic; + ddr2_clk_p : out std_logic; + ddr2_dq : inout std_logic_vector(15 downto 0); + ddr2_ldm : out std_logic; + ddr2_udm : out std_logic; + ddr2_ldqs_n : inout std_logic; + ddr2_ldqs_p : inout std_logic; + ddr2_udqs_n : inout std_logic; + ddr2_udqs_p : inout std_logic; + ddr2_odt : out std_logic; + -- + -- flash memory + flash_a : out std_logic_vector(24 downto 0); + flash_d : inout std_logic_vector(7 downto 3); + -- + fpga_d0_din_miso_miso1 : inout std_logic; -- dual use + fpga_d1_miso2 : inout std_logic; -- dual use + fpga_d2_miso3 : inout std_logic; -- dual use + flash_we_b : out std_logic; + flash_oe_b : out std_logic; + flash_ce_b : out std_logic; + -- + -- FMC connector + -- M2C Mezzanine to Carrier + -- C2M Carrier to Mezzanine + fmc_clk0_m2c_n : in std_logic; + fmc_clk0_m2c_p : in std_logic; + fmc_clk1_m2c_n : in std_logic; + fmc_clk1_m2c_p : in std_logic; + -- IIC addresses: + -- M24C08: 1010100..1010111 + -- 2kb EEPROM on FMC card: 1010010 + iic_scl_main : inout std_logic; + iic_sda_main : inout std_logic; + fmc_la00_cc_n : inout std_logic; + fmc_la00_cc_p : inout std_logic; + fmc_la01_cc_n : inout std_logic; + fmc_la01_cc_p : inout std_logic; + fmc_la02_n : inout std_logic; + fmc_la02_p : inout std_logic; + fmc_la03_n : inout std_logic; + fmc_la03_p : inout std_logic; + fmc_la04_n : inout std_logic; + fmc_la04_p : inout std_logic; + fmc_la05_n : inout std_logic; + fmc_la05_p : inout std_logic; + fmc_la06_n : inout std_logic; + fmc_la06_p : inout std_logic; + fmc_la07_n : inout std_logic; + fmc_la07_p : inout std_logic; + fmc_la08_n : inout std_logic; + fmc_la08_p : inout std_logic; + fmc_la09_n : inout std_logic; + fmc_la09_p : inout std_logic; + fmc_la10_n : inout std_logic; + fmc_la10_p : inout std_logic; + fmc_la11_n : inout std_logic; + fmc_la11_p : inout std_logic; + fmc_la12_n : inout std_logic; + fmc_la12_p : inout std_logic; + fmc_la13_n : inout std_logic; + fmc_la13_p : inout std_logic; + fmc_la14_n : inout std_logic; + fmc_la14_p : inout std_logic; + fmc_la15_n : inout std_logic; + fmc_la15_p : inout std_logic; + fmc_la16_n : inout std_logic; + fmc_la16_p : inout std_logic; + fmc_la17_cc_n : inout std_logic; + fmc_la17_cc_p : inout std_logic; + fmc_la18_cc_n : inout std_logic; + fmc_la18_cc_p : inout std_logic; + fmc_la19_n : inout std_logic; + fmc_la19_p : inout std_logic; + fmc_la20_n : inout std_logic; + fmc_la20_p : inout std_logic; + fmc_la21_n : inout std_logic; + fmc_la21_p : inout std_logic; + fmc_la22_n : inout std_logic; + fmc_la22_p : inout std_logic; + fmc_la23_n : inout std_logic; + fmc_la23_p : inout std_logic; + fmc_la24_n : inout std_logic; + fmc_la24_p : inout std_logic; + fmc_la25_n : inout std_logic; + fmc_la25_p : inout std_logic; + fmc_la26_n : inout std_logic; + fmc_la26_p : inout std_logic; + fmc_la27_n : inout std_logic; + fmc_la27_p : inout std_logic; + fmc_la28_n : inout std_logic; + fmc_la28_p : inout std_logic; + fmc_la29_n : inout std_logic; + fmc_la29_p : inout std_logic; + fmc_la30_n : inout std_logic; + fmc_la30_p : inout std_logic; + fmc_la31_n : inout std_logic; + fmc_la31_p : inout std_logic; + fmc_la32_n : inout std_logic; + fmc_la32_p : inout std_logic; + fmc_la33_n : inout std_logic; + fmc_la33_p : inout std_logic; + fmc_prsnt_m2c_l : in std_logic; + fmc_pwr_good_flash_rst_b : out std_logic; -- multiple destinations: 1 of Q2 (LED DS1 driver), U1 AB2 FPGA_PROG (through series R260 DNP), 44 of U25 + -- + fpga_awake : out std_logic; + fpga_cclk : out std_logic; + fpga_cmp_clk : in std_logic; + fpga_cmp_mosi : in std_logic; + -- + fpga_hswapen : in std_logic; + fpga_init_b : out std_logic; -- low active + fpga_m0_cmp_miso : in std_logic; -- mode DIP switch SW1 active high + fpga_m1 : in std_logic; -- mode DIP switch SW1 active high + fpga_mosi_csi_b_miso0 : inout std_logic; + fpga_onchip_term1 : inout std_logic; + fpga_onchip_term2 : inout std_logic; + fpga_vtemp : in std_logic; + -- + -- GPIOs + gpio_button : in std_logic_vector(3 downto 0); -- active high + gpio_header_ls : inout std_logic_vector(7 downto 0); + gpio_led : out std_logic_vector(3 downto 0); + gpio_switch : in std_logic_vector(3 downto 0); -- active high + -- + -- Ethernet Gigabit PHY, + -- default settings: + -- phy address = 0b00111 + -- ANEG[3..0] = "1111" + -- ENA_XC = 1 + -- DIS_125 = 1 + -- HWCFG_MD[3..0] = "1111" + -- DIS_FC = 1 + -- DIS_SLEEP = 1 + -- SEL_BDT = 0 + -- INT_POL = 1 + -- 75/50Ohm = 0 + phy_col : in std_logic; + phy_crs : in std_logic; + phy_int : in std_logic; + phy_mdc : out std_logic; + phy_mdio : inout std_logic; + phy_reset : out std_logic; + phy_rxclk : in std_logic; + phy_rxctl_rxdv : in std_logic; + phy_rxd : in std_logic_vector(7 downto 0); + phy_rxer : in std_logic; + phy_txclk : in std_logic; + phy_txctl_txen : out std_logic; + phy_txc_gtxclk : out std_logic; + phy_txd : out std_logic_vector(7 downto 0); + phy_txer : out std_logic; + -- + -- + spi_cs_b : out std_logic; + -- + -- 200 MHz oscillator, jitter 50 ppm + sysclk_n : in std_logic; + sysclk_p : in std_logic; + -- + -- RS232 via USB + usb_1_cts : out std_logic; -- function: RTS output + usb_1_rts : in std_logic; -- function: CTS input + usb_1_rx : out std_logic; -- function: TX data out + usb_1_tx : in std_logic; -- function: RX data in + -- + -- 27 MHz, oscillator socket + user_clock : in std_logic; + -- + -- user clock provided per SMA + user_sma_clock_p : in std_logic; + user_sma_clock_n : in std_logic + ); +end entity top; + + +architecture rtl of top is + + --------------------------- + -- type declarations + type zpu_type is (zpu_small, zpu_medium); + + --------------------------- + -- constant declarations + constant zpu_flavour : zpu_type := zpu_medium; -- choose your flavour HERE + -- modify frequency here + constant clk_multiply : positive := 2; -- 2 for small, 2 for medium + constant clk_divide : positive := 5; -- 4 for small, 5 for medium + -- + -- + constant word_size_c : natural := 32; -- 32 bits data path + constant addr_w_c : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O + -- + constant clk_frequency : positive := 200; -- input frequency for correct calculation + + + --------------------------- + -- component declarations + component zpu_small1 is + generic ( + word_size : natural := 32; -- 32 bits data path + d_care_val : std_logic := '0'; -- Fill value + clk_freq : positive := 50; -- 50 MHz clock + brate : positive := 115200; -- RS232 baudrate + addr_w : natural := 16; -- 16 bits address space=64 kB, 32 kB I/O + bram_w : natural := 15 -- 15 bits RAM space=32 kB + ); + port ( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + break_o : out std_logic; -- Break executed + dbg_o : out zpu_dbgo_t; -- Debug info + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic -- UART Rx + ); + end component zpu_small1; + + component zpu_med1 is + generic( + word_size : natural := 32; -- 32 bits data path + d_care_val : std_logic := '0'; -- Fill value + clk_freq : positive := 50; -- 50 MHz clock + brate : positive := 115200; -- RS232 baudrate + addr_w : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O + bram_w : natural := 15 -- 15 bits RAM space=32 kB + ); + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + break_o : out std_logic; -- Break executed + dbg_o : out zpu_dbgo_t; -- Debug info + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic -- UART Rx + ); + end component zpu_med1; + + + --------------------------- + -- signal declarations + signal sys_clk : std_ulogic; + signal dcm_sp_i0_clk0 : std_ulogic; + signal dcm_sp_i0_clkfx : std_ulogic; + signal clk_fb : std_ulogic; + signal clk : std_ulogic; + -- + signal reset_shift_reg : std_ulogic_vector(3 downto 0); + signal reset_sync : std_ulogic; + -- + signal zpu_i0_dbg : zpu_dbgo_t; -- Debug info + signal zpu_i0_break : std_logic; + + +begin + + -- default output drivers + -- to pass bitgen DRC + -- outputs used by design are commented + -- + ddr2_a <= (others => '1'); + ddr2_ba <= (others => '1'); + ddr2_cas_b <= '1'; + ddr2_ras_b <= '1'; + ddr2_we_b <= '1'; + ddr2_cke <= '0'; + ddr2_clk_n <= '0'; + ddr2_clk_p <= '1'; + ddr2_dq <= (others => 'Z'); + ddr2_ldm <= '0'; + ddr2_udm <= '0'; + ddr2_ldqs_n <= 'Z'; + ddr2_ldqs_p <= 'Z'; + ddr2_udqs_n <= 'Z'; + ddr2_udqs_p <= 'Z'; + ddr2_odt <= '1'; + -- + flash_a <= (others => '1'); + flash_d <= (others => 'Z'); + flash_we_b <= '1'; + flash_oe_b <= '1'; + flash_ce_b <= '1'; + -- + fpga_d0_din_miso_miso1 <= 'Z'; + fpga_d1_miso2 <= 'Z'; + fpga_d2_miso3 <= 'Z'; + -- + iic_scl_main <= 'Z'; + iic_sda_main <= 'Z'; + fmc_la00_cc_n <= 'Z'; + fmc_la00_cc_p <= 'Z'; + fmc_la01_cc_n <= 'Z'; + fmc_la01_cc_p <= 'Z'; + fmc_la02_n <= 'Z'; + fmc_la02_p <= 'Z'; + fmc_la03_n <= 'Z'; + fmc_la03_p <= 'Z'; + fmc_la04_n <= 'Z'; + fmc_la04_p <= 'Z'; + fmc_la05_n <= 'Z'; + fmc_la05_p <= 'Z'; + fmc_la06_n <= 'Z'; + fmc_la06_p <= 'Z'; + fmc_la07_n <= 'Z'; + fmc_la07_p <= 'Z'; + fmc_la08_n <= 'Z'; + fmc_la08_p <= 'Z'; + fmc_la09_n <= 'Z'; + fmc_la09_p <= 'Z'; + fmc_la10_n <= 'Z'; + fmc_la10_p <= 'Z'; + fmc_la11_n <= 'Z'; + fmc_la11_p <= 'Z'; + fmc_la12_n <= 'Z'; + fmc_la12_p <= 'Z'; + fmc_la13_n <= 'Z'; + fmc_la13_p <= 'Z'; + fmc_la14_n <= 'Z'; + fmc_la14_p <= 'Z'; + fmc_la15_n <= 'Z'; + fmc_la15_p <= 'Z'; + fmc_la16_n <= 'Z'; + fmc_la16_p <= 'Z'; + fmc_la17_cc_n <= 'Z'; + fmc_la17_cc_p <= 'Z'; + fmc_la18_cc_n <= 'Z'; + fmc_la18_cc_p <= 'Z'; + fmc_la19_n <= 'Z'; + fmc_la19_p <= 'Z'; + fmc_la20_n <= 'Z'; + fmc_la20_p <= 'Z'; + fmc_la21_n <= 'Z'; + fmc_la21_p <= 'Z'; + fmc_la22_n <= 'Z'; + fmc_la22_p <= 'Z'; + fmc_la23_n <= 'Z'; + fmc_la23_p <= 'Z'; + fmc_la24_n <= 'Z'; + fmc_la24_p <= 'Z'; + fmc_la25_n <= 'Z'; + fmc_la25_p <= 'Z'; + fmc_la26_n <= 'Z'; + fmc_la26_p <= 'Z'; + fmc_la27_n <= 'Z'; + fmc_la27_p <= 'Z'; + fmc_la28_n <= 'Z'; + fmc_la28_p <= 'Z'; + fmc_la29_n <= 'Z'; + fmc_la29_p <= 'Z'; + fmc_la30_n <= 'Z'; + fmc_la30_p <= 'Z'; + fmc_la31_n <= 'Z'; + fmc_la31_p <= 'Z'; + fmc_la32_n <= 'Z'; + fmc_la32_p <= 'Z'; + fmc_la33_n <= 'Z'; + fmc_la33_p <= 'Z'; + fmc_pwr_good_flash_rst_b <= '1'; + -- + fpga_awake <= '1'; + fpga_cclk <= '1'; -- SPI clk + fpga_init_b <= '1'; + fpga_mosi_csi_b_miso0 <= 'Z'; + fpga_onchip_term1 <= 'Z'; + fpga_onchip_term2 <= 'Z'; + -- + --gpio_led <= (others => '0'); + gpio_header_ls <= (others => 'Z'); + -- + phy_mdc <= '0'; + phy_mdio <= 'Z'; + phy_reset <= '0'; + phy_txc_gtxclk <= '0'; + phy_txctl_txen <= '0'; + phy_txd <= (others => '1'); + phy_txer <= '0'; + -- + spi_cs_b <= '1'; + -- + --usb_1_rx <= '1'; -- function: TX data out + usb_1_cts <= '1'; -- function: RTS + + + -- global differential input buffer + ibufgds_i0 : ibufgds + generic map ( + diff_term => true + ) + port map ( + i => sysclk_p, + ib => sysclk_n, + o => sys_clk + ); + + -- digital clock manager (DCM) + -- to generate higher/other system clock frequencys + dcm_sp_i0 : dcm_sp + generic map ( + startup_wait => true, -- wait with DONE till locked + clkfx_multiply => clk_multiply, + clkfx_divide => clk_divide, + clk_feedback => "1X" + ) + port map ( + clkin => sys_clk, + clk0 => dcm_sp_i0_clk0, + clkfx => dcm_sp_i0_clkfx, + clkfb => clk_fb + ); + + clk_fb <= dcm_sp_i0_clk0; + clk <= dcm_sp_i0_clkfx; + + + -- reset synchronizer + -- generate synchronous reset + reset_synchronizer : process(clk, cpu_reset) + begin + if cpu_reset = '1' then + reset_shift_reg <= (others => '1'); + elsif rising_edge(clk) then + reset_shift_reg <= reset_shift_reg(reset_shift_reg'high-1 downto 0) & '0'; + end if; + end process; + reset_sync <= reset_shift_reg(reset_shift_reg'high); + + + + -- select instance of zpu + zpu_i0_small : if zpu_flavour = zpu_small generate + zpu_i0 : zpu_small1 + generic map ( + addr_w => addr_w_c, + word_size => word_size_c, + clk_freq => clk_frequency * clk_multiply / clk_divide + ) + port map ( + clk_i => clk, -- : in std_logic; -- CPU clock + rst_i => reset_sync, -- : in std_logic; -- Reset + break_o => zpu_i0_break, -- : out std_logic; -- Break executed + dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; -- Debug info + rs232_tx_o => usb_1_rx, -- : out std_logic; -- UART Tx + rs232_rx_i => usb_1_tx -- : in std_logic -- UART Rx + ); + end generate zpu_i0_small; + + zpu_i0_medium : if zpu_flavour = zpu_medium generate + zpu_i0 : zpu_med1 + generic map ( + addr_w => addr_w_c, + word_size => word_size_c, + clk_freq => clk_frequency * clk_multiply / clk_divide + ) + port map ( + clk_i => clk, -- : in std_logic; -- CPU clock + rst_i => reset_sync, -- : in std_logic; -- Reset + break_o => zpu_i0_break, -- : out std_logic; -- Break executed + dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; -- Debug info + rs232_tx_o => usb_1_rx, -- : out std_logic; -- UART Tx + rs232_rx_i => usb_1_tx -- : in std_logic -- UART Rx + ); + end generate zpu_i0_medium; + + + -- pragma translate_off + stop_simulation <= zpu_i0_break; + + + trace_mod : trace + generic map ( + addr_w => addr_w_c, + word_size => word_size_c, + log_file => "zpu_trace.log" + ) + port map ( + clk_i => clk, + dbg_i => zpu_i0_dbg, + stop_i => zpu_i0_break, + busy_i => '0' + ); + -- pragma translate_on + + + -- switch on all LEDs in case of break + process + begin + wait until rising_edge(clk); + if zpu_i0_break = '1' then + gpio_led <= (others => '1'); + end if; + if reset_sync = '1' then + gpio_led <= (others => '0'); + end if; + end process; + + + +end architecture rtl; diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top_tb.vhd b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top_tb.vhd new file mode 100644 index 0000000..b09b144 --- /dev/null +++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/top_tb.vhd @@ -0,0 +1,398 @@ +-- testbench for +-- SP601 evaluation board +-- +-- includes "model" for clock generation +-- simulate press on cpu_reset as reset +-- +-- place models for external components (PHY, DDR2) in this file +-- + + +library ieee; +use ieee.std_logic_1164.all; + + +entity top_tb is +end entity top_tb; + +architecture testbench of top_tb is + + --------------------------- + -- constant declarations + constant sys_clk_period : time := 1 sec / 200_000_000; -- 200 MHz + constant user_clk_period : time := 1 sec / 27_000_000; -- 27 MHz + + + --------------------------- + -- signal declarations + signal simulation_run : boolean := true; + signal tb_stop_simulation : std_logic; + -- + signal tb_cpu_reset : std_logic; -- SW9 pushbutton (active-high) + -- + -- DDR2 memory 128 MB + signal tb_ddr2_a : std_logic_vector(12 downto 0); + signal tb_ddr2_ba : std_logic_vector(2 downto 0); + signal tb_ddr2_cas_b : std_logic; + signal tb_ddr2_ras_b : std_logic; + signal tb_ddr2_we_b : std_logic; + signal tb_ddr2_cke : std_logic; + signal tb_ddr2_clk_n : std_logic; + signal tb_ddr2_clk_p : std_logic; + signal tb_ddr2_dq : std_logic_vector(15 downto 0); + signal tb_ddr2_ldm : std_logic; + signal tb_ddr2_udm : std_logic; + signal tb_ddr2_ldqs_n : std_logic; + signal tb_ddr2_ldqs_p : std_logic; + signal tb_ddr2_udqs_n : std_logic; + signal tb_ddr2_udqs_p : std_logic; + signal tb_ddr2_odt : std_logic; + -- + -- flash memory + signal tb_flash_a : std_logic_vector(24 downto 0); + signal tb_flash_d : std_logic_vector(7 downto 3); + signal tb_fpga_d0_din_miso_miso1 : std_logic; -- dual use + signal tb_fpga_d1_miso2 : std_logic; -- dual use + signal tb_fpga_d2_miso3 : std_logic; -- dual use + signal tb_flash_we_b : std_logic; + signal tb_flash_oe_b : std_logic; + signal tb_flash_ce_b : std_logic; + -- + -- FMC connector + -- M2C Mezzanine to Carrier + -- C2M Carrier to Mezzanine + signal tb_fmc_clk0_m2c_n : std_logic := '1'; + signal tb_fmc_clk0_m2c_p : std_logic := '0'; + signal tb_fmc_clk1_m2c_n : std_logic := '1'; + signal tb_fmc_clk1_m2c_p : std_logic := '0'; + -- IIC addresses: + -- M24C08: 1010100..1010111 + -- 2kb EEPROM on FMC card: 1010010 + signal tb_iic_scl_main : std_logic; + signal tb_iic_sda_main : std_logic; + signal tb_fmc_la00_cc_n : std_logic; + signal tb_fmc_la00_cc_p : std_logic; + signal tb_fmc_la01_cc_n : std_logic; + signal tb_fmc_la01_cc_p : std_logic; + signal tb_fmc_la02_n : std_logic; + signal tb_fmc_la02_p : std_logic; + signal tb_fmc_la03_n : std_logic; + signal tb_fmc_la03_p : std_logic; + signal tb_fmc_la04_n : std_logic; + signal tb_fmc_la04_p : std_logic; + signal tb_fmc_la05_n : std_logic; + signal tb_fmc_la05_p : std_logic; + signal tb_fmc_la06_n : std_logic; + signal tb_fmc_la06_p : std_logic; + signal tb_fmc_la07_n : std_logic; + signal tb_fmc_la07_p : std_logic; + signal tb_fmc_la08_n : std_logic; + signal tb_fmc_la08_p : std_logic; + signal tb_fmc_la09_n : std_logic; + signal tb_fmc_la09_p : std_logic; + signal tb_fmc_la10_n : std_logic; + signal tb_fmc_la10_p : std_logic; + signal tb_fmc_la11_n : std_logic; + signal tb_fmc_la11_p : std_logic; + signal tb_fmc_la12_n : std_logic; + signal tb_fmc_la12_p : std_logic; + signal tb_fmc_la13_n : std_logic; + signal tb_fmc_la13_p : std_logic; + signal tb_fmc_la14_n : std_logic; + signal tb_fmc_la14_p : std_logic; + signal tb_fmc_la15_n : std_logic; + signal tb_fmc_la15_p : std_logic; + signal tb_fmc_la16_n : std_logic; + signal tb_fmc_la16_p : std_logic; + signal tb_fmc_la17_cc_n : std_logic; + signal tb_fmc_la17_cc_p : std_logic; + signal tb_fmc_la18_cc_n : std_logic; + signal tb_fmc_la18_cc_p : std_logic; + signal tb_fmc_la19_n : std_logic; + signal tb_fmc_la19_p : std_logic; + signal tb_fmc_la20_n : std_logic; + signal tb_fmc_la20_p : std_logic; + signal tb_fmc_la21_n : std_logic; + signal tb_fmc_la21_p : std_logic; + signal tb_fmc_la22_n : std_logic; + signal tb_fmc_la22_p : std_logic; + signal tb_fmc_la23_n : std_logic; + signal tb_fmc_la23_p : std_logic; + signal tb_fmc_la24_n : std_logic; + signal tb_fmc_la24_p : std_logic; + signal tb_fmc_la25_n : std_logic; + signal tb_fmc_la25_p : std_logic; + signal tb_fmc_la26_n : std_logic; + signal tb_fmc_la26_p : std_logic; + signal tb_fmc_la27_n : std_logic; + signal tb_fmc_la27_p : std_logic; + signal tb_fmc_la28_n : std_logic; + signal tb_fmc_la28_p : std_logic; + signal tb_fmc_la29_n : std_logic; + signal tb_fmc_la29_p : std_logic; + signal tb_fmc_la30_n : std_logic; + signal tb_fmc_la30_p : std_logic; + signal tb_fmc_la31_n : std_logic; + signal tb_fmc_la31_p : std_logic; + signal tb_fmc_la32_n : std_logic; + signal tb_fmc_la32_p : std_logic; + signal tb_fmc_la33_n : std_logic; + signal tb_fmc_la33_p : std_logic; + signal tb_fmc_prsnt_m2c_l : std_logic := '0'; + signal tb_fmc_pwr_good_flash_rst_b : std_logic; -- multiple destinations: 1 of Q2 (LED DS1 driver), U1 AB2 FPGA_PROG (through series R260 DNP), 44 of U25 + -- + signal tb_fpga_awake : std_logic; + signal tb_fpga_cclk : std_logic; + signal tb_fpga_cmp_clk : std_logic := '0'; + signal tb_fpga_cmp_mosi : std_logic := '0'; + signal tb_fpga_hswapen : std_logic := '0'; + signal tb_fpga_init_b : std_logic; -- low active + signal tb_fpga_m0_cmp_miso : std_logic := '0'; -- mode DIP switch SW1 active high + signal tb_fpga_m1 : std_logic := '0'; -- mode DIP switch SW1 active high + signal tb_fpga_mosi_csi_b_miso0 : std_logic; + signal tb_fpga_onchip_term1 : std_logic; + signal tb_fpga_onchip_term2 : std_logic; + signal tb_fpga_vtemp : std_logic := '0'; + -- + -- GPIOs + signal tb_gpio_button : std_logic_vector(3 downto 0) := (others => '0'); -- active high + signal tb_gpio_header_ls : std_logic_vector(7 downto 0); -- + signal tb_gpio_led : std_logic_vector(3 downto 0); + signal tb_gpio_switch : std_logic_vector(3 downto 0) := (others => '0'); -- active high + -- + -- Ethernet Gigabit PHY + signal tb_phy_col : std_logic := '0'; + signal tb_phy_crs : std_logic := '0'; + signal tb_phy_int : std_logic := '0'; + signal tb_phy_mdc : std_logic; + signal tb_phy_mdio : std_logic; + signal tb_phy_reset : std_logic; + signal tb_phy_rxclk : std_logic := '0'; + signal tb_phy_rxctl_rxdv : std_logic := '0'; + signal tb_phy_rxd : std_logic_vector(7 downto 0); + signal tb_phy_rxer : std_logic := '0'; + signal tb_phy_txclk : std_logic := '0'; + signal tb_phy_txctl_txen : std_logic; + signal tb_phy_txc_gtxclk : std_logic; + signal tb_phy_txd : std_logic_vector(7 downto 0); + signal tb_phy_txer : std_logic; + -- + -- + signal tb_spi_cs_b : std_logic; + -- + -- 200 MHz oscillator, jitter 50 ppm + signal tb_sysclk_n : std_logic := '1'; + signal tb_sysclk_p : std_logic := '0'; + -- + -- RS232 via USB + signal tb_usb_1_cts : std_logic; -- function: RTS output + signal tb_usb_1_rts : std_logic := '0'; -- function: CTS input + signal tb_usb_1_rx : std_logic; -- function: TX data out + signal tb_usb_1_tx : std_logic := '0'; -- function: RX data in + -- + -- 27 MHz, oscillator socket + signal tb_user_clock : std_logic := '0'; + -- + -- user clock provided per SMA + signal tb_user_sma_clock_p : std_logic := '0'; + signal tb_user_sma_clock_n : std_logic := '0'; + + + +begin + + -- generate clocks + tb_sysclk_p <= not tb_sysclk_p after sys_clk_period / 2 when simulation_run; + tb_sysclk_n <= not tb_sysclk_n after sys_clk_period / 2 when simulation_run; + tb_user_clock <= not tb_user_clock after user_clk_period / 2 when simulation_run; + + -- generate reset + tb_cpu_reset <= '1', '0' after 6.66 * sys_clk_period; + + -- dut + top_i0 : entity work.top + port map ( + stop_simulation => tb_stop_simulation, -- : out std_logic; + -- + cpu_reset => tb_cpu_reset, -- : in std_logic; + -- + -- DDR2 memory 128 MB + ddr2_a => tb_ddr2_a, -- : out std_logic_vector(12 downto 0); + ddr2_ba => tb_ddr2_ba, -- : out std_logic_vector(2 downto 0); + ddr2_cas_b => tb_ddr2_cas_b, -- : out std_logic; + ddr2_ras_b => tb_ddr2_ras_b, -- : out std_logic; + ddr2_we_b => tb_ddr2_we_b, -- : out std_logic; + ddr2_cke => tb_ddr2_cke, -- : out std_logic; + ddr2_clk_n => tb_ddr2_clk_n, -- : out std_logic; + ddr2_clk_p => tb_ddr2_clk_p, -- : out std_logic; + ddr2_dq => tb_ddr2_dq, -- : inout std_logic_vector(15 downto 0); + ddr2_ldm => tb_ddr2_ldm, -- : out std_logic; + ddr2_udm => tb_ddr2_udm, -- : out std_logic; + ddr2_ldqs_n => tb_ddr2_ldqs_n, -- : inout std_logic; + ddr2_ldqs_p => tb_ddr2_ldqs_p, -- : inout std_logic; + ddr2_udqs_n => tb_ddr2_udqs_n, -- : inout std_logic; + ddr2_udqs_p => tb_ddr2_udqs_p, -- : inout std_logic; + ddr2_odt => tb_ddr2_odt, -- : out std_logic; + -- + -- flash memory + flash_a => tb_flash_a, -- : out std_logic_vector(24 downto 0); + flash_d => tb_flash_d, -- : inout std_logic_vector(7 downto 3); + -- -- + fpga_d0_din_miso_miso1 => tb_fpga_d0_din_miso_miso1, -- : inout std_logic; + fpga_d1_miso2 => tb_fpga_d1_miso2, -- : inout std_logic; + fpga_d2_miso3 => tb_fpga_d2_miso3, -- : inout std_logic; + flash_we_b => tb_flash_we_b, -- : out std_logic; + flash_oe_b => tb_flash_oe_b, -- : out std_logic; + flash_ce_b => tb_flash_ce_b, -- : out std_logic; + -- + -- FMC connector + -- M2C Mezzanine to Carrier + -- C2M Carrier to Mezzanine + fmc_clk0_m2c_n => tb_fmc_clk0_m2c_n, -- : in std_logic; + fmc_clk0_m2c_p => tb_fmc_clk0_m2c_p, -- : in std_logic; + fmc_clk1_m2c_n => tb_fmc_clk1_m2c_n, -- : in std_logic; + fmc_clk1_m2c_p => tb_fmc_clk1_m2c_p, -- : in std_logic; + iic_scl_main => tb_iic_scl_main, -- : inout std_logic; + iic_sda_main => tb_iic_sda_main, -- : inout std_logic; + fmc_la00_cc_n => tb_fmc_la00_cc_n, -- : inout std_logic; + fmc_la00_cc_p => tb_fmc_la00_cc_p, -- : inout std_logic; + fmc_la01_cc_n => tb_fmc_la01_cc_n, -- : inout std_logic; + fmc_la01_cc_p => tb_fmc_la01_cc_p, -- : inout std_logic; + fmc_la02_n => tb_fmc_la02_n, -- : inout std_logic; + fmc_la02_p => tb_fmc_la02_p, -- : inout std_logic; + fmc_la03_n => tb_fmc_la03_n, -- : inout std_logic; + fmc_la03_p => tb_fmc_la03_p, -- : inout std_logic; + fmc_la04_n => tb_fmc_la04_n, -- : inout std_logic; + fmc_la04_p => tb_fmc_la04_p, -- : inout std_logic; + fmc_la05_n => tb_fmc_la05_n, -- : inout std_logic; + fmc_la05_p => tb_fmc_la05_p, -- : inout std_logic; + fmc_la06_n => tb_fmc_la06_n, -- : inout std_logic; + fmc_la06_p => tb_fmc_la06_p, -- : inout std_logic; + fmc_la07_n => tb_fmc_la07_n, -- : inout std_logic; + fmc_la07_p => tb_fmc_la07_p, -- : inout std_logic; + fmc_la08_n => tb_fmc_la08_n, -- : inout std_logic; + fmc_la08_p => tb_fmc_la08_p, -- : inout std_logic; + fmc_la09_n => tb_fmc_la09_n, -- : inout std_logic; + fmc_la09_p => tb_fmc_la09_p, -- : inout std_logic; + fmc_la10_n => tb_fmc_la10_n, -- : inout std_logic; + fmc_la10_p => tb_fmc_la10_p, -- : inout std_logic; + fmc_la11_n => tb_fmc_la11_n, -- : inout std_logic; + fmc_la11_p => tb_fmc_la11_p, -- : inout std_logic; + fmc_la12_n => tb_fmc_la12_n, -- : inout std_logic; + fmc_la12_p => tb_fmc_la12_p, -- : inout std_logic; + fmc_la13_n => tb_fmc_la13_n, -- : inout std_logic; + fmc_la13_p => tb_fmc_la13_p, -- : inout std_logic; + fmc_la14_n => tb_fmc_la14_n, -- : inout std_logic; + fmc_la14_p => tb_fmc_la14_p, -- : inout std_logic; + fmc_la15_n => tb_fmc_la15_n, -- : inout std_logic; + fmc_la15_p => tb_fmc_la15_p, -- : inout std_logic; + fmc_la16_n => tb_fmc_la16_n, -- : inout std_logic; + fmc_la16_p => tb_fmc_la16_p, -- : inout std_logic; + fmc_la17_cc_n => tb_fmc_la17_cc_n, -- : inout std_logic; + fmc_la17_cc_p => tb_fmc_la17_cc_p, -- : inout std_logic; + fmc_la18_cc_n => tb_fmc_la18_cc_n, -- : inout std_logic; + fmc_la18_cc_p => tb_fmc_la18_cc_p, -- : inout std_logic; + fmc_la19_n => tb_fmc_la19_n, -- : inout std_logic; + fmc_la19_p => tb_fmc_la19_p, -- : inout std_logic; + fmc_la20_n => tb_fmc_la20_n, -- : inout std_logic; + fmc_la20_p => tb_fmc_la20_p, -- : inout std_logic; + fmc_la21_n => tb_fmc_la21_n, -- : inout std_logic; + fmc_la21_p => tb_fmc_la21_p, -- : inout std_logic; + fmc_la22_n => tb_fmc_la22_n, -- : inout std_logic; + fmc_la22_p => tb_fmc_la22_p, -- : inout std_logic; + fmc_la23_n => tb_fmc_la23_n, -- : inout std_logic; + fmc_la23_p => tb_fmc_la23_p, -- : inout std_logic; + fmc_la24_n => tb_fmc_la24_n, -- : inout std_logic; + fmc_la24_p => tb_fmc_la24_p, -- : inout std_logic; + fmc_la25_n => tb_fmc_la25_n, -- : inout std_logic; + fmc_la25_p => tb_fmc_la25_p, -- : inout std_logic; + fmc_la26_n => tb_fmc_la26_n, -- : inout std_logic; + fmc_la26_p => tb_fmc_la26_p, -- : inout std_logic; + fmc_la27_n => tb_fmc_la27_n, -- : inout std_logic; + fmc_la27_p => tb_fmc_la27_p, -- : inout std_logic; + fmc_la28_n => tb_fmc_la28_n, -- : inout std_logic; + fmc_la28_p => tb_fmc_la28_p, -- : inout std_logic; + fmc_la29_n => tb_fmc_la29_n, -- : inout std_logic; + fmc_la29_p => tb_fmc_la29_p, -- : inout std_logic; + fmc_la30_n => tb_fmc_la30_n, -- : inout std_logic; + fmc_la30_p => tb_fmc_la30_p, -- : inout std_logic; + fmc_la31_n => tb_fmc_la31_n, -- : inout std_logic; + fmc_la31_p => tb_fmc_la31_p, -- : inout std_logic; + fmc_la32_n => tb_fmc_la32_n, -- : inout std_logic; + fmc_la32_p => tb_fmc_la32_p, -- : inout std_logic; + fmc_la33_n => tb_fmc_la33_n, -- : inout std_logic; + fmc_la33_p => tb_fmc_la33_p, -- : inout std_logic; + fmc_prsnt_m2c_l => tb_fmc_prsnt_m2c_l, -- : in std_logic; + fmc_pwr_good_flash_rst_b => tb_fmc_pwr_good_flash_rst_b, -- : out std_logic; + -- + fpga_awake => tb_fpga_awake, -- : out std_logic; + fpga_cclk => tb_fpga_cclk, -- : out std_logic; + fpga_cmp_clk => tb_fpga_cmp_clk, -- : in std_logic; + fpga_cmp_mosi => tb_fpga_cmp_mosi, -- : in std_logic; + -- -- + fpga_hswapen => tb_fpga_hswapen, -- : in std_logic; + fpga_init_b => tb_fpga_init_b, -- : out std_logic; + fpga_m0_cmp_miso => tb_fpga_m0_cmp_miso, -- : in std_logic; + fpga_m1 => tb_fpga_m1, -- : in std_logic; + fpga_mosi_csi_b_miso0 => tb_fpga_mosi_csi_b_miso0, -- : inout std_logic; + fpga_onchip_term1 => tb_fpga_onchip_term1, -- : inout std_logic; + fpga_onchip_term2 => tb_fpga_onchip_term2, -- : inout std_logic; + fpga_vtemp => tb_fpga_vtemp, -- : in std_logic; + -- + -- GPIOs + gpio_button => tb_gpio_button, -- : in std_logic_vector(3 downto 0); + gpio_header_ls => tb_gpio_header_ls, -- : inout std_logic_vector(7 downto 0); + gpio_led => tb_gpio_led, -- : out std_logic_vector(3 downto 0); + gpio_switch => tb_gpio_switch, -- : in std_logic_vector(3 downto 0); + -- + -- Ethernet Gigabit PHY + phy_col => tb_phy_col, -- : in std_logic; + phy_crs => tb_phy_crs, -- : in std_logic; + phy_int => tb_phy_int, -- : in std_logic; + phy_mdc => tb_phy_mdc, -- : out std_logic; + phy_mdio => tb_phy_mdio, -- : inout std_logic; + phy_reset => tb_phy_reset, -- : out std_logic; + phy_rxclk => tb_phy_rxclk, -- : in std_logic; + phy_rxctl_rxdv => tb_phy_rxctl_rxdv, -- : in std_logic; + phy_rxd => tb_phy_rxd, -- : in std_logic_vector(7 downto 0); + phy_rxer => tb_phy_rxer, -- : in std_logic; + phy_txclk => tb_phy_txclk, -- : in std_logic; + phy_txctl_txen => tb_phy_txctl_txen, -- : out std_logic; + phy_txc_gtxclk => tb_phy_txc_gtxclk, -- : out std_logic; + phy_txd => tb_phy_txd, -- : out std_logic_vector(7 downto 0); + phy_txer => tb_phy_txer, -- : out std_logic; + -- + -- + spi_cs_b => tb_spi_cs_b, -- : out std_logic; + -- + -- 200 MHz oscillator, jitter 50 ppm + sysclk_n => tb_sysclk_n, -- : in std_logic; + sysclk_p => tb_sysclk_p, -- : in std_logic; + -- + -- RS232 via USB + usb_1_cts => tb_usb_1_cts, -- : out std_logic; + usb_1_rts => tb_usb_1_rts, -- : in std_logic; + usb_1_rx => tb_usb_1_rx, -- : out std_logic; + usb_1_tx => tb_usb_1_tx, -- : in std_logic; + -- + -- 27 MHz, oscillator socket + user_clock => tb_user_clock, -- : in std_logic; + -- + -- user clock provided per SMA + user_sma_clock_p => tb_user_sma_clock_p, -- : in std_logic; + user_sma_clock_n => tb_user_sma_clock_n -- : in std_logic + ); + + + -- check for simulation stopping + process (tb_stop_simulation) + begin + if tb_stop_simulation = '1' then + report "Simulation end." severity note; + simulation_run <= false; + end if; + end process; + + +end architecture testbench; + |
