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author | Bert Lange <b.lange@hzdr.de> | 2015-04-15 13:36:55 +0200 |
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committer | Bert Lange <b.lange@hzdr.de> | 2015-04-15 13:36:55 +0200 |
commit | a1c964908b51599bf624bd2d253419c7e629f195 (patch) | |
tree | 06125d59e83b7dde82d1bb57bc0e09ca83451b98 /zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis.sh | |
parent | bbfe29a15f11548eb7c9fa71dcb4d2d18c164a53 (diff) | |
parent | 8679e4f91dcae05aef40f96629f33f0f4161f14a (diff) | |
download | zpu-a1c964908b51599bf624bd2d253419c7e629f195.zip zpu-a1c964908b51599bf624bd2d253419c7e629f195.tar.gz |
Merge branch 'master' of https://github.com/zylin/zpu
Diffstat (limited to 'zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis.sh')
-rwxr-xr-x | zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis.sh | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis.sh b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis.sh new file mode 100755 index 0000000..2f89415 --- /dev/null +++ b/zpu/hdl/zealot/fpga/xilinx-sp601-xc6slx16/synthesis.sh @@ -0,0 +1,36 @@ +#!/bin/sh + +# need project files: +# top.xst +# top.prj +# top.ut + +# need Xilinx tools: +# xst +# ngdbuild +# map +# par +# trce +# bitgen + +echo "########################" +echo "generate build directory" +echo "########################" +mkdir build +cd build +mkdir tmp + +echo "###############" +echo "start processes" +echo "###############" +xst -ifn "../synthesis_config/top.xst" -ofn "top.syr" +ngdbuild -dd _ngo -nt timestamp -uc ../synthesis_config/xilinx-sp601-xc6slx16.ucf -p xc6slx16-csg324-2 top.ngc top.ngd +map -p xc6slx16-csg324-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o top_map.ncd top.ngd top.pcf +par -ol high -mt off top_map.ncd -w top.ncd top.pcf +trce -v 3 -s 2 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf +bitgen -f ../synthesis_config/top.ut top.ncd + +echo "###########" +echo "get bitfile" +echo "###########" +cp top.bit .. |