add: GPIO module to zealot SoC

3 files changed, 97 insertions, 96 deletions

diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj
index 81d56ef..965ae4c 100644
--- a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.prj
@@ -1,18 +1,19 @@
-vhdl work ../top.vhd
-vhdl zpu ../../../zpu_pkg.vhdl
-vhdl zpu ../../../zpu_small.vhdl
-vhdl zpu ../../../zpu_medium.vhdl
-vhdl zpu ../../../roms/rom_pkg.vhdl
-#vhdl zpu ../../../roms/hello_dbram.vhdl
-#vhdl zpu ../../../roms/hello_bram.vhdl
-vhdl zpu ../../../roms/dmips_dbram.vhdl
-vhdl zpu ../../../roms/dmips_bram.vhdl
-vhdl zpu ../../../helpers/zpu_small1.vhdl
-vhdl zpu ../../../helpers/zpu_med1.vhdl
-vhdl zpu ../../../devices/txt_util.vhdl
-vhdl zpu ../../../devices/phi_io.vhdl
-vhdl zpu ../../../devices/timer.vhdl
-vhdl zpu ../../../devices/rx_unit.vhdl
-vhdl zpu ../../../devices/tx_unit.vhdl
-vhdl zpu ../../../devices/br_gen.vhdl
-vhdl zpu ../../../devices/trace.vhdl
+vhdl work ../top.vhd

+vhdl zpu ../../../zpu_pkg.vhdl

+vhdl zpu ../../../zpu_small.vhdl

+vhdl zpu ../../../zpu_medium.vhdl

+vhdl zpu ../../../roms/rom_pkg.vhdl

+#vhdl zpu ../../../roms/hello_dbram.vhdl

+#vhdl zpu ../../../roms/hello_bram.vhdl

+vhdl zpu ../../../roms/dmips_dbram.vhdl

+vhdl zpu ../../../roms/dmips_bram.vhdl

+vhdl zpu ../../../helpers/zpu_small1.vhdl

+vhdl zpu ../../../helpers/zpu_med1.vhdl

+vhdl zpu ../../../devices/txt_util.vhdl

+vhdl zpu ../../../devices/phi_io.vhdl

+vhdl zpu ../../../devices/timer.vhdl

+vhdl zpu ../../../devices/gpio.vhdl

+vhdl zpu ../../../devices/rx_unit.vhdl

+vhdl zpu ../../../devices/tx_unit.vhdl

+vhdl zpu ../../../devices/br_gen.vhdl

+vhdl zpu ../../../devices/trace.vhdl

diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut
index 06de8d5..4bf13c6 100644
--- a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut
@@ -1,22 +1,22 @@
--w
--g DebugBitstream:No
--g Binary:no
--g CRC:Enable
--g ConfigRate:1
--g ProgPin:PullUp
--g DonePin:PullUp
--g TckPin:PullUp
--g TdiPin:PullUp
--g TdoPin:PullUp
--g TmsPin:PullUp
--g UnusedPin:PullDown
--g UserID:0xFFFFFFFF
--g DCMShutdown:Disable
--g StartUpClk:CClk
--g DONE_cycle:4
--g GTS_cycle:5
--g GWE_cycle:6
--g LCK_cycle:NoWait
--g Security:None
--g DonePipe:No
--g DriveDone:No
+-w

+-g DebugBitstream:No

+-g Binary:no

+-g CRC:Enable

+-g ConfigRate:1

+-g ProgPin:PullUp

+-g DonePin:PullUp

+-g TckPin:PullUp

+-g TdiPin:PullUp

+-g TdoPin:PullUp

+-g TmsPin:PullUp

+-g UnusedPin:PullDown

+-g UserID:0xFFFFFFFF

+-g DCMShutdown:Disable

+-g StartUpClk:CClk

+-g DONE_cycle:4

+-g GTS_cycle:5

+-g GWE_cycle:6

+-g LCK_cycle:NoWait

+-g Security:None

+-g DonePipe:No

+-g DriveDone:No

diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.xst b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.xst
index fc7cc1d..d357860 100644
--- a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.xst
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.xst
@@ -1,56 +1,56 @@
-set -tmpdir "tmp"
-set -xsthdpdir "xst"
-run
--ifn ../synthesis_config/top.prj
--ifmt mixed
--ofn top
--ofmt NGC
--p xc3s500e-4-fg320
--top top
--opt_mode Speed
--opt_level 1
--iuc NO
--keep_hierarchy No
--netlist_hierarchy As_Optimized
--rtlview Yes
--glob_opt AllClockNets
--read_cores YES
--write_timing_constraints NO
--cross_clock_analysis NO
--hierarchy_separator /
--bus_delimiter <>
--case Maintain
--slice_utilization_ratio 100
--bram_utilization_ratio 100
--verilog2001 YES
--fsm_extract YES -fsm_encoding Auto
--safe_implementation No
--fsm_style LUT
--ram_extract Yes
--ram_style Auto
--rom_extract Yes
--mux_style Auto
--decoder_extract YES
--priority_extract Yes
--shreg_extract YES
--shift_extract YES
--xor_collapse YES
--rom_style Auto
--auto_bram_packing NO
--mux_extract Yes
--resource_sharing YES
--async_to_sync NO
--mult_style Auto
--iobuf YES
--max_fanout 500
--bufg 24
--register_duplication YES
--register_balancing No
--slice_packing YES
--optimize_primitives NO
--use_clock_enable Yes
--use_sync_set Yes
--use_sync_reset Yes
--iob Auto
--equivalent_register_removal YES
--slice_utilization_ratio_maxmargin 5
+set -tmpdir "tmp"

+set -xsthdpdir "xst"

+run

+-ifn ../synthesis_config/top.prj

+-ifmt mixed

+-ofn top

+-ofmt NGC

+-p xc3s500e-4-fg320

+-top top

+-opt_mode Speed

+-opt_level 1

+-iuc NO

+-keep_hierarchy No

+-netlist_hierarchy As_Optimized

+-rtlview Yes

+-glob_opt AllClockNets

+-read_cores YES

+-write_timing_constraints NO

+-cross_clock_analysis NO

+-hierarchy_separator /

+-bus_delimiter <>

+-case Maintain

+-slice_utilization_ratio 100

+-bram_utilization_ratio 100

+-verilog2001 YES

+-fsm_extract YES -fsm_encoding Auto

+-safe_implementation No

+-fsm_style LUT

+-ram_extract Yes

+-ram_style Auto

+-rom_extract Yes

+-mux_style Auto

+-decoder_extract YES

+-priority_extract Yes

+-shreg_extract YES

+-shift_extract YES

+-xor_collapse YES

+-rom_style Auto

+-auto_bram_packing NO

+-mux_extract Yes

+-resource_sharing YES

+-async_to_sync NO

+-mult_style Auto

+-iobuf YES

+-max_fanout 500

+-bufg 24

+-register_duplication YES

+-register_balancing No

+-slice_packing YES

+-optimize_primitives NO

+-use_clock_enable Yes

+-use_sync_set Yes

+-use_sync_reset Yes

+-iob Auto

+-equivalent_register_removal YES

+-slice_utilization_ratio_maxmargin 5