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authorBert Lange <b.lange@hzdr.de>2011-10-25 23:26:36 +0200
committerBert Lange <b.lange@hzdr.de>2011-10-25 23:26:36 +0200
commitc883cd4a4e4fa1974e5d7d72a79240de88bd26da (patch)
treeff3c0f3f7aa62f809001ea9ac9130683ab98a49e /zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut
parent105f8b40509ea2657e36e13af76b7580029fd2e5 (diff)
downloadzpu-c883cd4a4e4fa1974e5d7d72a79240de88bd26da.zip
zpu-c883cd4a4e4fa1974e5d7d72a79240de88bd26da.tar.gz
add: GPIO module to zealot SoC
Diffstat (limited to 'zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut')
-rw-r--r--zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut44
1 files changed, 22 insertions, 22 deletions
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut
index 06de8d5..4bf13c6 100644
--- a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut
@@ -1,22 +1,22 @@
--w
--g DebugBitstream:No
--g Binary:no
--g CRC:Enable
--g ConfigRate:1
--g ProgPin:PullUp
--g DonePin:PullUp
--g TckPin:PullUp
--g TdiPin:PullUp
--g TdoPin:PullUp
--g TmsPin:PullUp
--g UnusedPin:PullDown
--g UserID:0xFFFFFFFF
--g DCMShutdown:Disable
--g StartUpClk:CClk
--g DONE_cycle:4
--g GTS_cycle:5
--g GWE_cycle:6
--g LCK_cycle:NoWait
--g Security:None
--g DonePipe:No
--g DriveDone:No
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g ConfigRate:1
+-g ProgPin:PullUp
+-g DonePin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g DCMShutdown:Disable
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
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