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| author | Bert Lange <b.lange@hzdr.de> | 2011-10-13 12:37:49 +0200 |
|---|---|---|
| committer | Bert Lange <b.lange@hzdr.de> | 2011-10-13 12:37:49 +0200 |
| commit | 0bf783475d6610a14f71884737aeae33246bb9be (patch) | |
| tree | 8545a4d2e76761131f4945db6eeca7b563f7161e /zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut | |
| parent | bf4405c61a9c010a8e888da678436a282b9551a3 (diff) | |
| download | zpu-0bf783475d6610a14f71884737aeae33246bb9be.zip zpu-0bf783475d6610a14f71884737aeae33246bb9be.tar.gz | |
add: ZPU reference designs for zealot
Diffstat (limited to 'zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut')
| -rw-r--r-- | zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut new file mode 100644 index 0000000..06de8d5 --- /dev/null +++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut @@ -0,0 +1,22 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g CRC:Enable +-g ConfigRate:1 +-g ProgPin:PullUp +-g DonePin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g DCMShutdown:Disable +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No |
