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authorBert Lange <b.lange@hzdr.de>2015-04-15 13:36:55 +0200
committerBert Lange <b.lange@hzdr.de>2015-04-15 13:36:55 +0200
commita1c964908b51599bf624bd2d253419c7e629f195 (patch)
tree06125d59e83b7dde82d1bb57bc0e09ca83451b98 /zpu/hdl/example_medium/zpu_config_trace.vhd
parentbbfe29a15f11548eb7c9fa71dcb4d2d18c164a53 (diff)
parent8679e4f91dcae05aef40f96629f33f0f4161f14a (diff)
downloadzpu-a1c964908b51599bf624bd2d253419c7e629f195.zip
zpu-a1c964908b51599bf624bd2d253419c7e629f195.tar.gz
Merge branch 'master' of https://github.com/zylin/zpu
Diffstat (limited to 'zpu/hdl/example_medium/zpu_config_trace.vhd')
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diff --git a/zpu/hdl/example_medium/zpu_config_trace.vhd b/zpu/hdl/example_medium/zpu_config_trace.vhd
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+library ieee;
+use ieee.std_logic_1164.all;
+
+package zpu_config is
+
+ constant Generate_Trace : boolean := true;
+ constant wordPower : integer := 5;
+ -- during simulation, set this to '0' to get matching trace.txt
+ constant DontCareValue : std_logic := '0';
+ -- Clock frequency in MHz.
+ constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64";
+ constant maxAddrBitIncIO : integer := 27;
+ constant maxAddrBitDRAM : integer := 16;
+ constant maxAddrBitBRAM : integer := 16;
+ constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"001fff8";
+
+end zpu_config;
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