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author | oharboe <oharboe> | 2008-04-22 05:52:16 +0000 |
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committer | oharboe <oharboe> | 2008-04-22 05:52:16 +0000 |
commit | d09fa3de9df02a66c5084623076ac3e167b58274 (patch) | |
tree | b734b58ae8ca60717464d503e9a9bcd4a98727a7 /zpu/hdl/example_ghdl/README | |
parent | 167263dcae188a8812627ab52cfd96b8fdc5df8a (diff) | |
download | zpu-d09fa3de9df02a66c5084623076ac3e167b58274.zip zpu-d09fa3de9df02a66c5084623076ac3e167b58274.tar.gz |
* zpu/hdl/example_ghdl/ghdl_import.sh, zpu/hdl/example_ghdl/ghdl_make.sh,
zpu/hdl/example_ghdl/ghdl_options.sh, zpu/hdl/example_ghdl/README: GHDL example
* zpu/hdl/zpu4/src/dmipssmalltrace_ghdl.sh: testcase for GHDL
* zpu/hdl/zpu4/src/dmipstrace_ghdl.sh: testcase for GHDL
* zpu/hdl/zpu4/src/simzpu_medium_ghdl.sh: testcase for GHDL
* zpu/hdl/example/helloworld.vhd, zpu/hdl/zpu4/src/bram_dmips.vhd,
zpu/hdl/zpu4/src/dmipssmalltrace_ghdl.sh, zpu/hdl/zpu4/src/dram_dmips.vhd,
zpu/hdl/zpu4/src/dram_hello.vhd, zpu/hdl/zpu4/src/io.vhd,
zpu/hdl/zpu4/src/sim_fpga_top.vhd, zpu/hdl/zpu4/src/sim_small_fpga_top.vhd,
zpu/hdl/zpu4/src/timer.vhd, zpu/hdl/zpu4/src/trace.vhd,
zpu/hdl/zpu4/src/zpu_config_trace.vhd, zpu/hdl/zpu4/src/zpu_core_small.vhd,
zpu/hdl/zpu4/src/zpu_core.vhd, zpu/hdl/zpu4/src/zpupkg.vhd: conversion to numeric_std
Diffstat (limited to 'zpu/hdl/example_ghdl/README')
-rw-r--r-- | zpu/hdl/example_ghdl/README | 74 |
1 files changed, 74 insertions, 0 deletions
diff --git a/zpu/hdl/example_ghdl/README b/zpu/hdl/example_ghdl/README new file mode 100644 index 0000000..c537284 --- /dev/null +++ b/zpu/hdl/example_ghdl/README @@ -0,0 +1,74 @@ +This directory contains a quick setup of the helloworld example for
+the GHDL simulator.
+
+ http://ghdl.free.fr/
+
+Compiled by Arnim Laeuger, 17-Apr-2008.
+
+
+Prerequisites
+-------------
+
+The RTL source code references the ROC component from Xilinx' unisim
+library. If not already done, you'll have to prepare this library containing
+at least the roc entity and architecture objects.
+
+Decide where to store this library. This could be locally in this directory or
+at some central place where it can be referenced from other projects. I'd
+prefer the latter option.
+
+ $ cd <where unisim lib should be stored>
+
+Prepare the sources for GHDL:
+ $ mkdir src
+ $ cd src
+ $ ghdl --chop <WebPack installation dir>/vhdl/src/unisims/*
+ $ cd ..
+
+Import the sources into the library:
+ $ mkdir unisim_v93
+ $ ghdl -i --work=unisim --workdir=unisim_v93 --std=93 -fexplicit --no-vital-checks --ieee=synopsys src/*
+
+Compile the required component:
+ $ ghdl -m --syn-binding --work=unisim --workdir=unisim_v93 --std=93 -fexplicit --no-vital-checks --ieee=synopsys roc
+ $ rm roc
+ -> not required for library
+
+If you require more components from the unisim library for other projects, you
+can repeat the compile step later on without running through the preparation
+and import steps.
+
+
+Compiling the example
+---------------------
+
+Edit ghdl_options.sh and point the variable UNISIM_DIR to the location of your
+newly created unisim library.
+
+You need to import the project sources once by running
+ $ ./ghdl_import.sh
+
+Compilation (using GHDL's make feature) is invoked by
+ $ ./ghdl_make.sh
+
+Whenever the VHDL sources change, it's enough to execute ghdl_make.sh. GHDL
+will trace the dependencies and will rebuild only the modified sources.
+
+
+Simulation
+----------
+
+Simulation finally happens by running the fpga_top executable generated by the
+compilation step. Don't forget to set a stop time or the testbench might run
+forever:
+
+ $ ./fpga_top --stop-time=2100us
+
+The log.txt and trace.txt files are generated as simulation progresses. They
+should be compared to the files given in the example directory.
+
+Waveforms can be obtained by specifying the ghw file name:
+
+ $ ./fpga_top --stop-time=1ms --wave=zpu.ghw
+
+They can be inspected with gtkwave from http://home.nc.rr.com/gtkwave/.
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