Merge branch 'master' of https://github.com/zylin/zpu

author: Bert Lange <b.lange@hzdr.de> 2015-04-15 13:36:55 +0200
committer: Bert Lange <b.lange@hzdr.de> 2015-04-15 13:36:55 +0200
commit: a1c964908b51599bf624bd2d253419c7e629f195 (patch)
tree: 06125d59e83b7dde82d1bb57bc0e09ca83451b98 /zpu/hdl/example
parent: bbfe29a15f11548eb7c9fa71dcb4d2d18c164a53 (diff)
parent: 8679e4f91dcae05aef40f96629f33f0f4161f14a (diff)
download: zpu-a1c964908b51599bf624bd2d253419c7e629f195.zip
zpu-a1c964908b51599bf624bd2d253419c7e629f195.tar.gz
13 files changed, 10271 insertions, 0 deletions
diff --git a/zpu/hdl/example/.cvsignore b/zpu/hdl/example/.cvsignore
new file mode 100644
index 0000000..8238018
--- /dev/null
+++ b/zpu/hdl/example/.cvsignore
@@ -0,0 +1,3 @@
+work
+vsim.wlf
+install
diff --git a/zpu/hdl/example/bram_dmips.vhd b/zpu/hdl/example/bram_dmips.vhd
new file mode 100644
index 0000000..07b19f4
--- /dev/null
+++ b/zpu/hdl/example/bram_dmips.vhd
@@ -0,0 +1,3356 @@
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity dualport_ram is
+port (clk : in std_logic;
+	memAWriteEnable : in std_logic;
+	memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+	memAWrite : in std_logic_vector(wordSize-1 downto 0);
+	memARead : out std_logic_vector(wordSize-1 downto 0);
+	memBWriteEnable : in std_logic;
+	memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+	memBWrite : in std_logic_vector(wordSize-1 downto 0);
+	memBRead : out std_logic_vector(wordSize-1 downto 0));
+end dualport_ram;
+
+architecture dualport_ram_arch of dualport_ram is
+
+
+type ram_type is array(natural range 0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
+
+shared variable ram : ram_type :=
+(
+     0 => x"0b0b0b0b",
+     1 => x"82700b0b",
+     2 => x"80d5f40c",
+     3 => x"3a0b0b80",
+     4 => x"c4fb0400",
+     5 => x"00000000",
+     6 => x"00000000",
+     7 => x"00000000",
+     8 => x"80088408",
+     9 => x"88080b0b",
+    10 => x"80c5c22d",
+    11 => x"880c840c",
+    12 => x"800c0400",
+    13 => x"00000000",
+    14 => x"00000000",
+    15 => x"00000000",
+    16 => x"71fd0608",
+    17 => x"72830609",
+    18 => x"81058205",
+    19 => x"832b2a83",
+    20 => x"ffff0652",
+    21 => x"04000000",
+    22 => x"00000000",
+    23 => x"00000000",
+    24 => x"71fd0608",
+    25 => x"83ffff73",
+    26 => x"83060981",
+    27 => x"05820583",
+    28 => x"2b2b0906",
+    29 => x"7383ffff",
+    30 => x"0b0b0b0b",
+    31 => x"83a70400",
+    32 => x"72098105",
+    33 => x"72057373",
+    34 => x"09060906",
+    35 => x"73097306",
+    36 => x"070a8106",
+    37 => x"53510400",
+    38 => x"00000000",
+    39 => x"00000000",
+    40 => x"72722473",
+    41 => x"732e0753",
+    42 => x"51040000",
+    43 => x"00000000",
+    44 => x"00000000",
+    45 => x"00000000",
+    46 => x"00000000",
+    47 => x"00000000",
+    48 => x"71737109",
+    49 => x"71068106",
+    50 => x"30720a10",
+    51 => x"0a720a10",
+    52 => x"0a31050a",
+    53 => x"81065151",
+    54 => x"53510400",
+    55 => x"00000000",
+    56 => x"72722673",
+    57 => x"732e0753",
+    58 => x"51040000",
+    59 => x"00000000",
+    60 => x"00000000",
+    61 => x"00000000",
+    62 => x"00000000",
+    63 => x"00000000",
+    64 => x"00000000",
+    65 => x"00000000",
+    66 => x"00000000",
+    67 => x"00000000",
+    68 => x"00000000",
+    69 => x"00000000",
+    70 => x"00000000",
+    71 => x"00000000",
+    72 => x"0b0b0b88",
+    73 => x"c3040000",
+    74 => x"00000000",
+    75 => x"00000000",
+    76 => x"00000000",
+    77 => x"00000000",
+    78 => x"00000000",
+    79 => x"00000000",
+    80 => x"720a722b",
+    81 => x"0a535104",
+    82 => x"00000000",
+    83 => x"00000000",
+    84 => x"00000000",
+    85 => x"00000000",
+    86 => x"00000000",
+    87 => x"00000000",
+    88 => x"72729f06",
+    89 => x"0981050b",
+    90 => x"0b0b88a6",
+    91 => x"05040000",
+    92 => x"00000000",
+    93 => x"00000000",
+    94 => x"00000000",
+    95 => x"00000000",
+    96 => x"72722aff",
+    97 => x"739f062a",
+    98 => x"0974090a",
+    99 => x"8106ff05",
+   100 => x"06075351",
+   101 => x"04000000",
+   102 => x"00000000",
+   103 => x"00000000",
+   104 => x"71715351",
+   105 => x"020d0406",
+   106 => x"73830609",
+   107 => x"81058205",
+   108 => x"832b0b2b",
+   109 => x"0772fc06",
+   110 => x"0c515104",
+   111 => x"00000000",
+   112 => x"72098105",
+   113 => x"72050970",
+   114 => x"81050906",
+   115 => x"0a810653",
+   116 => x"51040000",
+   117 => x"00000000",
+   118 => x"00000000",
+   119 => x"00000000",
+   120 => x"72098105",
+   121 => x"72050970",
+   122 => x"81050906",
+   123 => x"0a098106",
+   124 => x"53510400",
+   125 => x"00000000",
+   126 => x"00000000",
+   127 => x"00000000",
+   128 => x"71098105",
+   129 => x"52040000",
+   130 => x"00000000",
+   131 => x"00000000",
+   132 => x"00000000",
+   133 => x"00000000",
+   134 => x"00000000",
+   135 => x"00000000",
+   136 => x"72720981",
+   137 => x"05055351",
+   138 => x"04000000",
+   139 => x"00000000",
+   140 => x"00000000",
+   141 => x"00000000",
+   142 => x"00000000",
+   143 => x"00000000",
+   144 => x"72097206",
+   145 => x"73730906",
+   146 => x"07535104",
+   147 => x"00000000",
+   148 => x"00000000",
+   149 => x"00000000",
+   150 => x"00000000",
+   151 => x"00000000",
+   152 => x"71fc0608",
+   153 => x"72830609",
+   154 => x"81058305",
+   155 => x"1010102a",
+   156 => x"81ff0652",
+   157 => x"04000000",
+   158 => x"00000000",
+   159 => x"00000000",
+   160 => x"71fc0608",
+   161 => x"0b0b80d5",
+   162 => x"e0738306",
+   163 => x"10100508",
+   164 => x"060b0b0b",
+   165 => x"88a90400",
+   166 => x"00000000",
+   167 => x"00000000",
+   168 => x"80088408",
+   169 => x"88087575",
+   170 => x"0b0b0bad",
+   171 => x"aa2d5050",
+   172 => x"80085688",
+   173 => x"0c840c80",
+   174 => x"0c510400",
+   175 => x"00000000",
+   176 => x"80088408",
+   177 => x"88087575",
+   178 => x"0b0b0bad",
+   179 => x"ee2d5050",
+   180 => x"80085688",
+   181 => x"0c840c80",
+   182 => x"0c510400",
+   183 => x"00000000",
+   184 => x"72097081",
+   185 => x"0509060a",
+   186 => x"8106ff05",
+   187 => x"70547106",
+   188 => x"73097274",
+   189 => x"05ff0506",
+   190 => x"07515151",
+   191 => x"04000000",
+   192 => x"72097081",
+   193 => x"0509060a",
+   194 => x"098106ff",
+   195 => x"05705471",
+   196 => x"06730972",
+   197 => x"7405ff05",
+   198 => x"06075151",
+   199 => x"51040000",
+   200 => x"05ff0504",
+   201 => x"00000000",
+   202 => x"00000000",
+   203 => x"00000000",
+   204 => x"00000000",
+   205 => x"00000000",
+   206 => x"00000000",
+   207 => x"00000000",
+   208 => x"810b0b0b",
+   209 => x"80d5f00c",
+   210 => x"51040000",
+   211 => x"00000000",
+   212 => x"00000000",
+   213 => x"00000000",
+   214 => x"00000000",
+   215 => x"00000000",
+   216 => x"71810552",
+   217 => x"04000000",
+   218 => x"00000000",
+   219 => x"00000000",
+   220 => x"00000000",
+   221 => x"00000000",
+   222 => x"00000000",
+   223 => x"00000000",
+   224 => x"00000000",
+   225 => x"00000000",
+   226 => x"00000000",
+   227 => x"00000000",
+   228 => x"00000000",
+   229 => x"00000000",
+   230 => x"00000000",
+   231 => x"00000000",
+   232 => x"02840572",
+   233 => x"10100552",
+   234 => x"04000000",
+   235 => x"00000000",
+   236 => x"00000000",
+   237 => x"00000000",
+   238 => x"00000000",
+   239 => x"00000000",
+   240 => x"00000000",
+   241 => x"00000000",
+   242 => x"00000000",
+   243 => x"00000000",
+   244 => x"00000000",
+   245 => x"00000000",
+   246 => x"00000000",
+   247 => x"00000000",
+   248 => x"717105ff",
+   249 => x"05715351",
+   250 => x"020d0400",
+   251 => x"00000000",
+   252 => x"00000000",
+   253 => x"00000000",
+   254 => x"00000000",
+   255 => x"00000000",
+   256 => x"82fd3fbf",
+   257 => x"a03f0410",
+   258 => x"10101010",
+   259 => x"10101010",
+   260 => x"10101010",
+   261 => x"10101010",
+   262 => x"10101010",
+   263 => x"10101010",
+   264 => x"10101010",
+   265 => x"10105351",
+   266 => x"047381ff",
+   267 => x"06738306",
+   268 => x"09810583",
+   269 => x"05101010",
+   270 => x"2b0772fc",
+   271 => x"060c5151",
+   272 => x"043c0472",
+   273 => x"72807281",
+   274 => x"06ff0509",
+   275 => x"72060571",
+   276 => x"1052720a",
+   277 => x"100a5372",
+   278 => x"ed385151",
+   279 => x"535104ff",
+   280 => x"3d0d0b0b",
+   281 => x"80e5e408",
+   282 => x"52710870",
+   283 => x"882a8132",
+   284 => x"70810651",
+   285 => x"515170f1",
+   286 => x"3873720c",
+   287 => x"833d0d04",
+   288 => x"80d5f008",
+   289 => x"802ea438",
+   290 => x"80d5f408",
+   291 => x"822ebd38",
+   292 => x"8380800b",
+   293 => x"0b0b80e5",
+   294 => x"e40c82a0",
+   295 => x"800b80e5",
+   296 => x"e80c8290",
+   297 => x"800b80e5",
+   298 => x"ec0c04f8",
+   299 => x"808080a4",
+   300 => x"0b0b0b80",
+   301 => x"e5e40cf8",
+   302 => x"80808280",
+   303 => x"0b80e5e8",
+   304 => x"0cf88080",
+   305 => x"84800b80",
+   306 => x"e5ec0c04",
+   307 => x"80c0a880",
+   308 => x"8c0b0b0b",
+   309 => x"80e5e40c",
+   310 => x"80c0a880",
+   311 => x"940b80e5",
+   312 => x"e80c0b0b",
+   313 => x"80c7d00b",
+   314 => x"80e5ec0c",
+   315 => x"04f23d0d",
+   316 => x"6080e5e8",
+   317 => x"08565d82",
+   318 => x"750c8059",
+   319 => x"805a800b",
+   320 => x"8f3d5d5b",
+   321 => x"7a101015",
+   322 => x"70087108",
+   323 => x"719f2c7e",
+   324 => x"852b5855",
+   325 => x"557d5359",
+   326 => x"5799993f",
+   327 => x"7d7f7a72",
+   328 => x"077c7207",
+   329 => x"71716081",
+   330 => x"05415f5d",
+   331 => x"5b595755",
+   332 => x"817b278f",
+   333 => x"38767d0c",
+   334 => x"77841e0c",
+   335 => x"7c800c90",
+   336 => x"3d0d0480",
+   337 => x"e5e80855",
+   338 => x"ffba3970",
+   339 => x"7080e5f0",
+   340 => x"335170a7",
+   341 => x"3880d5fc",
+   342 => x"08700852",
+   343 => x"5270802e",
+   344 => x"94388412",
+   345 => x"80d5fc0c",
+   346 => x"702d80d5",
+   347 => x"fc087008",
+   348 => x"525270ee",
+   349 => x"38810b80",
+   350 => x"e5f03450",
+   351 => x"50040470",
+   352 => x"0b0b80e5",
+   353 => x"e008802e",
+   354 => x"8e380b0b",
+   355 => x"0b0b800b",
+   356 => x"802e0981",
+   357 => x"06833850",
+   358 => x"040b0b80",
+   359 => x"e5e0510b",
+   360 => x"0b0bf4dc",
+   361 => x"3f500404",
+   362 => x"ff3d0d02",
+   363 => x"8f053352",
+   364 => x"718a2e8a",
+   365 => x"387151fd",
+   366 => x"a63f833d",
+   367 => x"0d048d51",
+   368 => x"fd9d3f71",
+   369 => x"51fd983f",
+   370 => x"833d0d04",
+   371 => x"ce3d0db5",
+   372 => x"3d707084",
+   373 => x"0552088b",
+   374 => x"a85c56a5",
+   375 => x"3d5e5c80",
+   376 => x"75708105",
+   377 => x"5733765b",
+   378 => x"55587378",
+   379 => x"2e80c138",
+   380 => x"8e3d5b73",
+   381 => x"a52e0981",
+   382 => x"0680c538",
+   383 => x"78708105",
+   384 => x"5a335473",
+   385 => x"80e42e81",
+   386 => x"b6387380",
+   387 => x"e42480c6",
+   388 => x"387380e3",
+   389 => x"2ea13880",
+   390 => x"52a55179",
+   391 => x"2d805273",
+   392 => x"51792d82",
+   393 => x"18587870",
+   394 => x"81055a33",
+   395 => x"5473c438",
+   396 => x"77800cb4",
+   397 => x"3d0d047b",
+   398 => x"841d8312",
+   399 => x"33565d57",
+   400 => x"80527351",
+   401 => x"792d8118",
+   402 => x"79708105",
+   403 => x"5b335558",
+   404 => x"73ffa038",
+   405 => x"db397380",
+   406 => x"f32e0981",
+   407 => x"06ffb838",
+   408 => x"7b841d71",
+   409 => x"08595d56",
+   410 => x"80773355",
+   411 => x"5673762e",
+   412 => x"8d388116",
+   413 => x"70187033",
+   414 => x"57555674",
+   415 => x"f538ff16",
+   416 => x"55807625",
+   417 => x"ffa03876",
+   418 => x"70810558",
+   419 => x"33548052",
+   420 => x"7351792d",
+   421 => x"811875ff",
+   422 => x"17575758",
+   423 => x"807625ff",
+   424 => x"85387670",
+   425 => x"81055833",
+   426 => x"54805273",
+   427 => x"51792d81",
+   428 => x"1875ff17",
+   429 => x"57575875",
+   430 => x"8024cc38",
+   431 => x"fee8397b",
+   432 => x"841d7108",
+   433 => x"70719f2c",
+   434 => x"5953595d",
+   435 => x"56807524",
+   436 => x"81913875",
+   437 => x"7d7c5856",
+   438 => x"54805773",
+   439 => x"772e0981",
+   440 => x"06b638b0",
+   441 => x"7b3402b5",
+   442 => x"05567a76",
+   443 => x"2e9738ff",
+   444 => x"16567533",
+   445 => x"75708105",
+   446 => x"57348117",
+   447 => x"577a762e",
+   448 => x"098106eb",
+   449 => x"38807534",
+   450 => x"767dff12",
+   451 => x"57585675",
+   452 => x"8024fef3",
+   453 => x"38fe8f39",
+   454 => x"8a527351",
+   455 => x"9fd03f80",
+   456 => x"0880c7d4",
+   457 => x"05337670",
+   458 => x"81055834",
+   459 => x"8a527351",
+   460 => x"9ef83f80",
+   461 => x"08548008",
+   462 => x"802effae",
+   463 => x"388a5273",
+   464 => x"519fab3f",
+   465 => x"800880c7",
+   466 => x"d4053376",
+   467 => x"70810558",
+   468 => x"348a5273",
+   469 => x"519ed33f",
+   470 => x"80085480",
+   471 => x"08ffb938",
+   472 => x"ff883974",
+   473 => x"527653b4",
+   474 => x"3dffb805",
+   475 => x"51949a3f",
+   476 => x"a33d0856",
+   477 => x"fedd3980",
+   478 => x"3d0d80c1",
+   479 => x"0b81b4bc",
+   480 => x"34800b81",
+   481 => x"b6980c70",
+   482 => x"800c823d",
+   483 => x"0d04ff3d",
+   484 => x"0d800b81",
+   485 => x"b4bc3352",
+   486 => x"527080c1",
+   487 => x"2e993871",
+   488 => x"81b69808",
+   489 => x"0781b698",
+   490 => x"0c80c20b",
+   491 => x"81b4c034",
+   492 => x"70800c83",
+   493 => x"3d0d0481",
+   494 => x"0b81b698",
+   495 => x"080781b6",
+   496 => x"980c80c2",
+   497 => x"0b81b4c0",
+   498 => x"3470800c",
+   499 => x"833d0d04",
+   500 => x"fd3d0d75",
+   501 => x"70088a05",
+   502 => x"535381b4",
+   503 => x"bc335170",
+   504 => x"80c12e8b",
+   505 => x"3873f338",
+   506 => x"70800c85",
+   507 => x"3d0d04ff",
+   508 => x"127081b4",
+   509 => x"b8083174",
+   510 => x"0c800c85",
+   511 => x"3d0d04fc",
+   512 => x"3d0d81b4",
+   513 => x"c4085574",
+   514 => x"802e8c38",
+   515 => x"76750871",
+   516 => x"0c81b4c4",
+   517 => x"0856548c",
+   518 => x"155381b4",
+   519 => x"b808528a",
+   520 => x"518fd43f",
+   521 => x"73800c86",
+   522 => x"3d0d04fb",
+   523 => x"3d0d7770",
+   524 => x"085656b0",
+   525 => x"5381b4c4",
+   526 => x"08527451",
+   527 => x"ab943f85",
+   528 => x"0b8c170c",
+   529 => x"850b8c16",
+   530 => x"0c750875",
+   531 => x"0c81b4c4",
+   532 => x"08547380",
+   533 => x"2e8a3873",
+   534 => x"08750c81",
+   535 => x"b4c40854",
+   536 => x"8c145381",
+   537 => x"b4b80852",
+   538 => x"8a518f8b",
+   539 => x"3f841508",
+   540 => x"ad38860b",
+   541 => x"8c160c88",
+   542 => x"15528816",
+   543 => x"08518e97",
+   544 => x"3f81b4c4",
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+  2873 => x"00002cdc",
+  2874 => x"00002cdc",
+  2875 => x"00002ce4",
+  2876 => x"00002ce4",
+  2877 => x"00002cec",
+  2878 => x"00002cec",
+  2879 => x"00002cf4",
+  2880 => x"00002cf4",
+  2881 => x"00002cfc",
+  2882 => x"00002cfc",
+  2883 => x"00002d04",
+  2884 => x"00002d04",
+  2885 => x"00002d0c",
+  2886 => x"00002d0c",
+  2887 => x"00002d14",
+  2888 => x"00002d14",
+  2889 => x"00002d1c",
+  2890 => x"00002d1c",
+  2891 => x"00002d24",
+  2892 => x"00002d24",
+  2893 => x"00002d2c",
+  2894 => x"00002d2c",
+  2895 => x"00002d34",
+  2896 => x"00002d34",
+  2897 => x"00002d3c",
+  2898 => x"00002d3c",
+  2899 => x"00002d44",
+  2900 => x"00002d44",
+  2901 => x"00002d4c",
+  2902 => x"00002d4c",
+  2903 => x"00002d54",
+  2904 => x"00002d54",
+  2905 => x"00002d5c",
+  2906 => x"00002d5c",
+  2907 => x"00002d64",
+  2908 => x"00002d64",
+  2909 => x"00002d6c",
+  2910 => x"00002d6c",
+  2911 => x"00002d74",
+  2912 => x"00002d74",
+  2913 => x"00002d7c",
+  2914 => x"00002d7c",
+  2915 => x"00002d84",
+  2916 => x"00002d84",
+  2917 => x"00002d8c",
+  2918 => x"00002d8c",
+  2919 => x"00002d94",
+  2920 => x"00002d94",
+  2921 => x"00002d9c",
+  2922 => x"00002d9c",
+  2923 => x"00002da4",
+  2924 => x"00002da4",
+  2925 => x"00002dac",
+  2926 => x"00002dac",
+  2927 => x"00002db4",
+  2928 => x"00002db4",
+  2929 => x"00002dbc",
+  2930 => x"00002dbc",
+  2931 => x"00002dc4",
+  2932 => x"00002dc4",
+  2933 => x"00002dcc",
+  2934 => x"00002dcc",
+  2935 => x"00002dd4",
+  2936 => x"00002dd4",
+  2937 => x"00002ddc",
+  2938 => x"00002ddc",
+  2939 => x"00002de4",
+  2940 => x"00002de4",
+  2941 => x"00002dec",
+  2942 => x"00002dec",
+  2943 => x"00002df4",
+  2944 => x"00002df4",
+  2945 => x"00002dfc",
+  2946 => x"00002dfc",
+  2947 => x"00002e04",
+  2948 => x"00002e04",
+  2949 => x"00002e0c",
+  2950 => x"00002e0c",
+  2951 => x"00002e14",
+  2952 => x"00002e14",
+  2953 => x"00002e1c",
+  2954 => x"00002e1c",
+  2955 => x"00002e24",
+  2956 => x"00002e24",
+  2957 => x"00002e2c",
+  2958 => x"00002e2c",
+  2959 => x"00002e34",
+  2960 => x"00002e34",
+  2961 => x"00002e3c",
+  2962 => x"00002e3c",
+  2963 => x"00002e44",
+  2964 => x"00002e44",
+  2965 => x"00002e4c",
+  2966 => x"00002e4c",
+  2967 => x"00002e54",
+  2968 => x"00002e54",
+  2969 => x"00002e5c",
+  2970 => x"00002e5c",
+  2971 => x"00002e64",
+  2972 => x"00002e64",
+  2973 => x"00002e6c",
+  2974 => x"00002e6c",
+  2975 => x"00002e74",
+  2976 => x"00002e74",
+  2977 => x"00002e7c",
+  2978 => x"00002e7c",
+  2979 => x"00002e84",
+  2980 => x"00002e84",
+  2981 => x"00002e8c",
+  2982 => x"00002e8c",
+  2983 => x"00002e94",
+  2984 => x"00002e94",
+  2985 => x"00002e9c",
+  2986 => x"00002e9c",
+  2987 => x"00002ea4",
+  2988 => x"00002ea4",
+  2989 => x"00002eac",
+  2990 => x"00002eac",
+  2991 => x"00002eb4",
+  2992 => x"00002eb4",
+  2993 => x"00002ebc",
+  2994 => x"00002ebc",
+  2995 => x"00002ec4",
+  2996 => x"00002ec4",
+  2997 => x"00002ecc",
+  2998 => x"00002ecc",
+  2999 => x"00002ed4",
+  3000 => x"00002ed4",
+  3001 => x"00002edc",
+  3002 => x"00002edc",
+  3003 => x"00002ee4",
+  3004 => x"00002ee4",
+  3005 => x"00002eec",
+  3006 => x"00002eec",
+  3007 => x"00002ef4",
+  3008 => x"00002ef4",
+  3009 => x"00002efc",
+  3010 => x"00002efc",
+  3011 => x"00002f04",
+  3012 => x"00002f04",
+  3013 => x"00002f0c",
+  3014 => x"00002f0c",
+  3015 => x"00002f14",
+  3016 => x"00002f14",
+  3017 => x"00002f1c",
+  3018 => x"00002f1c",
+  3019 => x"00002f24",
+  3020 => x"00002f24",
+  3021 => x"00002f2c",
+  3022 => x"00002f2c",
+  3023 => x"00002f34",
+  3024 => x"00002f34",
+  3025 => x"00002f3c",
+  3026 => x"00002f3c",
+  3027 => x"00002f50",
+  3028 => x"00000000",
+  3029 => x"000031b8",
+  3030 => x"00003214",
+  3031 => x"00003270",
+  3032 => x"00000000",
+  3033 => x"00000000",
+  3034 => x"00000000",
+  3035 => x"00000000",
+  3036 => x"00000000",
+  3037 => x"00000000",
+  3038 => x"00000000",
+  3039 => x"00000000",
+  3040 => x"00000000",
+  3041 => x"00002ad0",
+  3042 => x"00000000",
+  3043 => x"00000000",
+  3044 => x"00000000",
+  3045 => x"00000000",
+  3046 => x"00000000",
+  3047 => x"00000000",
+  3048 => x"00000000",
+  3049 => x"00000000",
+  3050 => x"00000000",
+  3051 => x"00000000",
+  3052 => x"00000000",
+  3053 => x"00000000",
+  3054 => x"00000000",
+  3055 => x"00000000",
+  3056 => x"00000000",
+  3057 => x"00000000",
+  3058 => x"00000000",
+  3059 => x"00000000",
+  3060 => x"00000000",
+  3061 => x"00000000",
+  3062 => x"00000000",
+  3063 => x"00000000",
+  3064 => x"00000000",
+  3065 => x"00000000",
+  3066 => x"00000000",
+  3067 => x"00000000",
+  3068 => x"00000000",
+  3069 => x"00000000",
+  3070 => x"00000001",
+  3071 => x"330eabcd",
+  3072 => x"1234e66d",
+  3073 => x"deec0005",
+  3074 => x"000b0000",
+  3075 => x"00000000",
+  3076 => x"00000000",
+  3077 => x"00000000",
+  3078 => x"00000000",
+  3079 => x"00000000",
+  3080 => x"00000000",
+  3081 => x"00000000",
+  3082 => x"00000000",
+  3083 => x"00000000",
+  3084 => x"00000000",
+  3085 => x"00000000",
+  3086 => x"00000000",
+  3087 => x"00000000",
+  3088 => x"00000000",
+  3089 => x"00000000",
+  3090 => x"00000000",
+  3091 => x"00000000",
+  3092 => x"00000000",
+  3093 => x"00000000",
+  3094 => x"00000000",
+  3095 => x"00000000",
+  3096 => x"00000000",
+  3097 => x"00000000",
+  3098 => x"00000000",
+  3099 => x"00000000",
+  3100 => x"00000000",
+  3101 => x"00000000",
+  3102 => x"00000000",
+  3103 => x"00000000",
+  3104 => x"00000000",
+  3105 => x"00000000",
+  3106 => x"00000000",
+  3107 => x"00000000",
+  3108 => x"00000000",
+  3109 => x"00000000",
+  3110 => x"00000000",
+  3111 => x"00000000",
+  3112 => x"00000000",
+  3113 => x"00000000",
+  3114 => x"00000000",
+  3115 => x"00000000",
+  3116 => x"00000000",
+  3117 => x"00000000",
+  3118 => x"00000000",
+  3119 => x"00000000",
+  3120 => x"00000000",
+  3121 => x"00000000",
+  3122 => x"00000000",
+  3123 => x"00000000",
+  3124 => x"00000000",
+  3125 => x"00000000",
+  3126 => x"00000000",
+  3127 => x"00000000",
+  3128 => x"00000000",
+  3129 => x"00000000",
+  3130 => x"00000000",
+  3131 => x"00000000",
+  3132 => x"00000000",
+  3133 => x"00000000",
+  3134 => x"00000000",
+  3135 => x"00000000",
+  3136 => x"00000000",
+  3137 => x"00000000",
+  3138 => x"00000000",
+  3139 => x"00000000",
+  3140 => x"00000000",
+  3141 => x"00000000",
+  3142 => x"00000000",
+  3143 => x"00000000",
+  3144 => x"00000000",
+  3145 => x"00000000",
+  3146 => x"00000000",
+  3147 => x"00000000",
+  3148 => x"00000000",
+  3149 => x"00000000",
+  3150 => x"00000000",
+  3151 => x"00000000",
+  3152 => x"00000000",
+  3153 => x"00000000",
+  3154 => x"00000000",
+  3155 => x"00000000",
+  3156 => x"00000000",
+  3157 => x"00000000",
+  3158 => x"00000000",
+  3159 => x"00000000",
+  3160 => x"00000000",
+  3161 => x"00000000",
+  3162 => x"00000000",
+  3163 => x"00000000",
+  3164 => x"00000000",
+  3165 => x"00000000",
+  3166 => x"00000000",
+  3167 => x"00000000",
+  3168 => x"00000000",
+  3169 => x"00000000",
+  3170 => x"00000000",
+  3171 => x"00000000",
+  3172 => x"00000000",
+  3173 => x"00000000",
+  3174 => x"00000000",
+  3175 => x"00000000",
+  3176 => x"00000000",
+  3177 => x"00000000",
+  3178 => x"00000000",
+  3179 => x"00000000",
+  3180 => x"00000000",
+  3181 => x"00000000",
+  3182 => x"00000000",
+  3183 => x"00000000",
+  3184 => x"00000000",
+  3185 => x"00000000",
+  3186 => x"00000000",
+  3187 => x"00000000",
+  3188 => x"00000000",
+  3189 => x"00000000",
+  3190 => x"00000000",
+  3191 => x"00000000",
+  3192 => x"00000000",
+  3193 => x"00000000",
+  3194 => x"00000000",
+  3195 => x"00000000",
+  3196 => x"00000000",
+  3197 => x"00000000",
+  3198 => x"00000000",
+  3199 => x"00000000",
+  3200 => x"00000000",
+  3201 => x"00000000",
+  3202 => x"00000000",
+  3203 => x"00000000",
+  3204 => x"00000000",
+  3205 => x"00000000",
+  3206 => x"00000000",
+  3207 => x"00000000",
+  3208 => x"00000000",
+  3209 => x"00000000",
+  3210 => x"00000000",
+  3211 => x"00000000",
+  3212 => x"00000000",
+  3213 => x"00000000",
+  3214 => x"00000000",
+  3215 => x"00000000",
+  3216 => x"00000000",
+  3217 => x"00000000",
+  3218 => x"00000000",
+  3219 => x"00000000",
+  3220 => x"00000000",
+  3221 => x"00000000",
+  3222 => x"00000000",
+  3223 => x"00000000",
+  3224 => x"00000000",
+  3225 => x"00000000",
+  3226 => x"00000000",
+  3227 => x"00000000",
+  3228 => x"00000000",
+  3229 => x"00000000",
+  3230 => x"00000000",
+  3231 => x"00000000",
+  3232 => x"00000000",
+  3233 => x"00000000",
+  3234 => x"00000000",
+  3235 => x"00000000",
+  3236 => x"00000000",
+  3237 => x"00000000",
+  3238 => x"00000000",
+  3239 => x"00000000",
+  3240 => x"00000000",
+  3241 => x"00000000",
+  3242 => x"00000000",
+  3243 => x"00000000",
+  3244 => x"00000000",
+  3245 => x"00000000",
+  3246 => x"00000000",
+  3247 => x"00000000",
+  3248 => x"00000000",
+  3249 => x"00000000",
+  3250 => x"00000000",
+  3251 => x"00002ad4",
+  3252 => x"ffffffff",
+  3253 => x"00000000",
+  3254 => x"ffffffff",
+  3255 => x"00000000",
+  3256 => x"00000000",
+	others => x"00000000"
+);
+
+begin
+
+process (clk)
+begin
+	if (clk'event and clk = '1') then
+		if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then
+			report "write collision" severity failure;
+		end if;
+	
+		if (memAWriteEnable = '1') then
+			ram(to_integer(unsigned(memAAddr))) := memAWrite;
+			memARead <= memAWrite;
+		else
+			memARead <= ram(to_integer(unsigned(memAAddr)));
+		end if;
+	end if;
+end process;
+
+process (clk)
+begin
+	if (clk'event and clk = '1') then
+		if (memBWriteEnable = '1') then
+			ram(to_integer(unsigned(memBAddr))) := memBWrite;
+			memBRead <= memBWrite;
+		else
+			memBRead <= ram(to_integer(unsigned(memBAddr)));
+		end if;
+	end if;
+end process;
+
+
+
+
+end dualport_ram_arch;
diff --git a/zpu/hdl/example/helloworld.vhd b/zpu/hdl/example/helloworld.vhd
new file mode 100644
index 0000000..cc8d8c6
--- /dev/null
+++ b/zpu/hdl/example/helloworld.vhd
@@ -0,0 +1,3154 @@
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity dualport_ram is
+port (clk : in std_logic;
+	memAWriteEnable : in std_logic;
+	memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+	memAWrite : in std_logic_vector(wordSize-1 downto 0);
+	memARead : out std_logic_vector(wordSize-1 downto 0);
+	memBWriteEnable : in std_logic;
+	memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+	memBWrite : in std_logic_vector(wordSize-1 downto 0);
+	memBRead : out std_logic_vector(wordSize-1 downto 0));
+end dualport_ram;
+
+architecture dualport_ram_arch of dualport_ram is
+
+
+type ram_type is array(natural range 0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
+
+shared variable ram : ram_type :=
+(
+0 => x"0b0b0b0b",
+1 => x"82700b0b",
+2 => x"80cfd80c",
+3 => x"3a0b0b80",
+4 => x"c6d00400",
+5 => x"00000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"80c7972d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
+17 => x"72830609",
+18 => x"81058205",
+19 => x"832b2a83",
+20 => x"ffff0652",
+21 => x"04000000",
+22 => x"00000000",
+23 => x"00000000",
+24 => x"71fd0608",
+25 => x"83ffff73",
+26 => x"83060981",
+27 => x"05820583",
+28 => x"2b2b0906",
+29 => x"7383ffff",
+30 => x"0b0b0b0b",
+31 => x"83a70400",
+32 => x"72098105",
+33 => x"72057373",
+34 => x"09060906",
+35 => x"73097306",
+36 => x"070a8106",
+37 => x"53510400",
+38 => x"00000000",
+39 => x"00000000",
+40 => x"72722473",
+41 => x"732e0753",
+42 => x"51040000",
+43 => x"00000000",
+44 => x"00000000",
+45 => x"00000000",
+46 => x"00000000",
+47 => x"00000000",
+48 => x"71737109",
+49 => x"71068106",
+50 => x"30720a10",
+51 => x"0a720a10",
+52 => x"0a31050a",
+53 => x"81065151",
+54 => x"53510400",
+55 => x"00000000",
+56 => x"72722673",
+57 => x"732e0753",
+58 => x"51040000",
+59 => x"00000000",
+60 => x"00000000",
+61 => x"00000000",
+62 => x"00000000",
+63 => x"00000000",
+64 => x"00000000",
+65 => x"00000000",
+66 => x"00000000",
+67 => x"00000000",
+68 => x"00000000",
+69 => x"00000000",
+70 => x"00000000",
+71 => x"00000000",
+72 => x"0b0b0b88",
+73 => x"c4040000",
+74 => x"00000000",
+75 => x"00000000",
+76 => x"00000000",
+77 => x"00000000",
+78 => x"00000000",
+79 => x"00000000",
+80 => x"720a722b",
+81 => x"0a535104",
+82 => x"00000000",
+83 => x"00000000",
+84 => x"00000000",
+85 => x"00000000",
+86 => x"00000000",
+87 => x"00000000",
+88 => x"72729f06",
+89 => x"0981050b",
+90 => x"0b0b88a7",
+91 => x"05040000",
+92 => x"00000000",
+93 => x"00000000",
+94 => x"00000000",
+95 => x"00000000",
+96 => x"72722aff",
+97 => x"739f062a",
+98 => x"0974090a",
+99 => x"8106ff05",
+100 => x"06075351",
+101 => x"04000000",
+102 => x"00000000",
+103 => x"00000000",
+104 => x"71715351",
+105 => x"020d0406",
+106 => x"73830609",
+107 => x"81058205",
+108 => x"832b0b2b",
+109 => x"0772fc06",
+110 => x"0c515104",
+111 => x"00000000",
+112 => x"72098105",
+113 => x"72050970",
+114 => x"81050906",
+115 => x"0a810653",
+116 => x"51040000",
+117 => x"00000000",
+118 => x"00000000",
+119 => x"00000000",
+120 => x"72098105",
+121 => x"72050970",
+122 => x"81050906",
+123 => x"0a098106",
+124 => x"53510400",
+125 => x"00000000",
+126 => x"00000000",
+127 => x"00000000",
+128 => x"71098105",
+129 => x"52040000",
+130 => x"00000000",
+131 => x"00000000",
+132 => x"00000000",
+133 => x"00000000",
+134 => x"00000000",
+135 => x"00000000",
+136 => x"72720981",
+137 => x"05055351",
+138 => x"04000000",
+139 => x"00000000",
+140 => x"00000000",
+141 => x"00000000",
+142 => x"00000000",
+143 => x"00000000",
+144 => x"72097206",
+145 => x"73730906",
+146 => x"07535104",
+147 => x"00000000",
+148 => x"00000000",
+149 => x"00000000",
+150 => x"00000000",
+151 => x"00000000",
+152 => x"71fc0608",
+153 => x"72830609",
+154 => x"81058305",
+155 => x"1010102a",
+156 => x"81ff0652",
+157 => x"04000000",
+158 => x"00000000",
+159 => x"00000000",
+160 => x"71fc0608",
+161 => x"0b0b80cf",
+162 => x"c4738306",
+163 => x"10100508",
+164 => x"060b0b0b",
+165 => x"88aa0400",
+166 => x"00000000",
+167 => x"00000000",
+168 => x"80088408",
+169 => x"88087575",
+170 => x"0b0b0b8b",
+171 => x"9f2d5050",
+172 => x"80085688",
+173 => x"0c840c80",
+174 => x"0c510400",
+175 => x"00000000",
+176 => x"80088408",
+177 => x"88087575",
+178 => x"0b0b0b8b",
+179 => x"e32d5050",
+180 => x"80085688",
+181 => x"0c840c80",
+182 => x"0c510400",
+183 => x"00000000",
+184 => x"72097081",
+185 => x"0509060a",
+186 => x"8106ff05",
+187 => x"70547106",
+188 => x"73097274",
+189 => x"05ff0506",
+190 => x"07515151",
+191 => x"04000000",
+192 => x"72097081",
+193 => x"0509060a",
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+2781 => x"00000000",
+2782 => x"00000000",
+2783 => x"00000000",
+2784 => x"00000000",
+2785 => x"00000000",
+2786 => x"00000000",
+2787 => x"00000000",
+2788 => x"00000000",
+2789 => x"ffffffff",
+2790 => x"00000000",
+2791 => x"00020000",
+2792 => x"00000000",
+2793 => x"00000000",
+2794 => x"00002ba0",
+2795 => x"00002ba0",
+2796 => x"00002ba8",
+2797 => x"00002ba8",
+2798 => x"00002bb0",
+2799 => x"00002bb0",
+2800 => x"00002bb8",
+2801 => x"00002bb8",
+2802 => x"00002bc0",
+2803 => x"00002bc0",
+2804 => x"00002bc8",
+2805 => x"00002bc8",
+2806 => x"00002bd0",
+2807 => x"00002bd0",
+2808 => x"00002bd8",
+2809 => x"00002bd8",
+2810 => x"00002be0",
+2811 => x"00002be0",
+2812 => x"00002be8",
+2813 => x"00002be8",
+2814 => x"00002bf0",
+2815 => x"00002bf0",
+2816 => x"00002bf8",
+2817 => x"00002bf8",
+2818 => x"00002c00",
+2819 => x"00002c00",
+2820 => x"00002c08",
+2821 => x"00002c08",
+2822 => x"00002c10",
+2823 => x"00002c10",
+2824 => x"00002c18",
+2825 => x"00002c18",
+2826 => x"00002c20",
+2827 => x"00002c20",
+2828 => x"00002c28",
+2829 => x"00002c28",
+2830 => x"00002c30",
+2831 => x"00002c30",
+2832 => x"00002c38",
+2833 => x"00002c38",
+2834 => x"00002c40",
+2835 => x"00002c40",
+2836 => x"00002c48",
+2837 => x"00002c48",
+2838 => x"00002c50",
+2839 => x"00002c50",
+2840 => x"00002c58",
+2841 => x"00002c58",
+2842 => x"00002c60",
+2843 => x"00002c60",
+2844 => x"00002c68",
+2845 => x"00002c68",
+2846 => x"00002c70",
+2847 => x"00002c70",
+2848 => x"00002c78",
+2849 => x"00002c78",
+2850 => x"00002c80",
+2851 => x"00002c80",
+2852 => x"00002c88",
+2853 => x"00002c88",
+2854 => x"00002c90",
+2855 => x"00002c90",
+2856 => x"00002c98",
+2857 => x"00002c98",
+2858 => x"00002ca0",
+2859 => x"00002ca0",
+2860 => x"00002ca8",
+2861 => x"00002ca8",
+2862 => x"00002cb0",
+2863 => x"00002cb0",
+2864 => x"00002cb8",
+2865 => x"00002cb8",
+2866 => x"00002cc0",
+2867 => x"00002cc0",
+2868 => x"00002cc8",
+2869 => x"00002cc8",
+2870 => x"00002cd0",
+2871 => x"00002cd0",
+2872 => x"00002cd8",
+2873 => x"00002cd8",
+2874 => x"00002ce0",
+2875 => x"00002ce0",
+2876 => x"00002ce8",
+2877 => x"00002ce8",
+2878 => x"00002cf0",
+2879 => x"00002cf0",
+2880 => x"00002cf8",
+2881 => x"00002cf8",
+2882 => x"00002d00",
+2883 => x"00002d00",
+2884 => x"00002d08",
+2885 => x"00002d08",
+2886 => x"00002d10",
+2887 => x"00002d10",
+2888 => x"00002d18",
+2889 => x"00002d18",
+2890 => x"00002d20",
+2891 => x"00002d20",
+2892 => x"00002d28",
+2893 => x"00002d28",
+2894 => x"00002d30",
+2895 => x"00002d30",
+2896 => x"00002d38",
+2897 => x"00002d38",
+2898 => x"00002d40",
+2899 => x"00002d40",
+2900 => x"00002d48",
+2901 => x"00002d48",
+2902 => x"00002d50",
+2903 => x"00002d50",
+2904 => x"00002d58",
+2905 => x"00002d58",
+2906 => x"00002d60",
+2907 => x"00002d60",
+2908 => x"00002d68",
+2909 => x"00002d68",
+2910 => x"00002d70",
+2911 => x"00002d70",
+2912 => x"00002d78",
+2913 => x"00002d78",
+2914 => x"00002d80",
+2915 => x"00002d80",
+2916 => x"00002d88",
+2917 => x"00002d88",
+2918 => x"00002d90",
+2919 => x"00002d90",
+2920 => x"00002d98",
+2921 => x"00002d98",
+2922 => x"00002da0",
+2923 => x"00002da0",
+2924 => x"00002da8",
+2925 => x"00002da8",
+2926 => x"00002db0",
+2927 => x"00002db0",
+2928 => x"00002db8",
+2929 => x"00002db8",
+2930 => x"00002dc0",
+2931 => x"00002dc0",
+2932 => x"00002dc8",
+2933 => x"00002dc8",
+2934 => x"00002dd0",
+2935 => x"00002dd0",
+2936 => x"00002dd8",
+2937 => x"00002dd8",
+2938 => x"00002de0",
+2939 => x"00002de0",
+2940 => x"00002de8",
+2941 => x"00002de8",
+2942 => x"00002df0",
+2943 => x"00002df0",
+2944 => x"00002df8",
+2945 => x"00002df8",
+2946 => x"00002e00",
+2947 => x"00002e00",
+2948 => x"00002e08",
+2949 => x"00002e08",
+2950 => x"00002e10",
+2951 => x"00002e10",
+2952 => x"00002e18",
+2953 => x"00002e18",
+2954 => x"00002e20",
+2955 => x"00002e20",
+2956 => x"00002e28",
+2957 => x"00002e28",
+2958 => x"00002e30",
+2959 => x"00002e30",
+2960 => x"00002e38",
+2961 => x"00002e38",
+2962 => x"00002e40",
+2963 => x"00002e40",
+2964 => x"00002e48",
+2965 => x"00002e48",
+2966 => x"00002e50",
+2967 => x"00002e50",
+2968 => x"00002e58",
+2969 => x"00002e58",
+2970 => x"00002e60",
+2971 => x"00002e60",
+2972 => x"00002e68",
+2973 => x"00002e68",
+2974 => x"00002e70",
+2975 => x"00002e70",
+2976 => x"00002e78",
+2977 => x"00002e78",
+2978 => x"00002e80",
+2979 => x"00002e80",
+2980 => x"00002e88",
+2981 => x"00002e88",
+2982 => x"00002e90",
+2983 => x"00002e90",
+2984 => x"00002e98",
+2985 => x"00002e98",
+2986 => x"00002ea0",
+2987 => x"00002ea0",
+2988 => x"00002ea8",
+2989 => x"00002ea8",
+2990 => x"00002eb0",
+2991 => x"00002eb0",
+2992 => x"00002eb8",
+2993 => x"00002eb8",
+2994 => x"00002ec0",
+2995 => x"00002ec0",
+2996 => x"00002ec8",
+2997 => x"00002ec8",
+2998 => x"00002ed0",
+2999 => x"00002ed0",
+3000 => x"00002ed8",
+3001 => x"00002ed8",
+3002 => x"00002ee0",
+3003 => x"00002ee0",
+3004 => x"00002ee8",
+3005 => x"00002ee8",
+3006 => x"00002ef0",
+3007 => x"00002ef0",
+3008 => x"00002ef8",
+3009 => x"00002ef8",
+3010 => x"00002f00",
+3011 => x"00002f00",
+3012 => x"00002f08",
+3013 => x"00002f08",
+3014 => x"00002f10",
+3015 => x"00002f10",
+3016 => x"00002f18",
+3017 => x"00002f18",
+3018 => x"00002f20",
+3019 => x"00002f20",
+3020 => x"00002f28",
+3021 => x"00002f28",
+3022 => x"00002f30",
+3023 => x"00002f30",
+3024 => x"00002f38",
+3025 => x"00002f38",
+3026 => x"00002f40",
+3027 => x"00002f40",
+3028 => x"00002f48",
+3029 => x"00002f48",
+3030 => x"00002f50",
+3031 => x"00002f50",
+3032 => x"00002f58",
+3033 => x"00002f58",
+3034 => x"00002f60",
+3035 => x"00002f60",
+3036 => x"00002f68",
+3037 => x"00002f68",
+3038 => x"00002f70",
+3039 => x"00002f70",
+3040 => x"00002f78",
+3041 => x"00002f78",
+3042 => x"00002f80",
+3043 => x"00002f80",
+3044 => x"00002f88",
+3045 => x"00002f88",
+3046 => x"00002f90",
+3047 => x"00002f90",
+3048 => x"00002f98",
+3049 => x"00002f98",
+3050 => x"000027b8",
+3051 => x"ffffffff",
+3052 => x"00000000",
+3053 => x"ffffffff",
+3054 => x"00000000",
+	others => x"00000000"
+);
+
+begin
+
+process (clk)
+begin
+	if (clk'event and clk = '1') then
+		if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then
+			report "write collision" severity failure;
+		end if;
+	
+		if (memAWriteEnable = '1') then
+			ram(to_integer(unsigned(memAAddr))) := memAWrite;
+			memARead <= memAWrite;
+		else
+			memARead <= ram(to_integer(unsigned(memAAddr)));
+		end if;
+	end if;
+end process;
+
+process (clk)
+begin
+	if (clk'event and clk = '1') then
+		if (memBWriteEnable = '1') then
+			ram(to_integer(unsigned(memBAddr))) := memBWrite;
+			memBRead <= memBWrite;
+		else
+			memBRead <= ram(to_integer(unsigned(memBAddr)));
+		end if;
+	end if;
+end process;
+
+
+
+
+end dualport_ram_arch;
diff --git a/zpu/hdl/example/interrupt.vhd b/zpu/hdl/example/interrupt.vhd
new file mode 100644
index 0000000..d2bc709
--- /dev/null
+++ b/zpu/hdl/example/interrupt.vhd
@@ -0,0 +1,3156 @@
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity dualport_ram is
+port (clk : in std_logic;
+	memAWriteEnable : in std_logic;
+	memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+	memAWrite : in std_logic_vector(wordSize-1 downto 0);
+	memARead : out std_logic_vector(wordSize-1 downto 0);
+	memBWriteEnable : in std_logic;
+	memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+	memBWrite : in std_logic_vector(wordSize-1 downto 0);
+	memBRead : out std_logic_vector(wordSize-1 downto 0));
+end dualport_ram;
+
+architecture dualport_ram_arch of dualport_ram is
+
+
+type ram_type is array(natural range 0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
+
+shared variable ram : ram_type :=
+(
+0 => x"0b0b0b0b",
+1 => x"82700b0b",
+2 => x"80cfe00c",
+3 => x"3a0b0b80",
+4 => x"c6e00400",
+5 => x"00000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"0b8af02d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
+17 => x"72830609",
+18 => x"81058205",
+19 => x"832b2a83",
+20 => x"ffff0652",
+21 => x"04000000",
+22 => x"00000000",
+23 => x"00000000",
+24 => x"71fd0608",
+25 => x"83ffff73",
+26 => x"83060981",
+27 => x"05820583",
+28 => x"2b2b0906",
+29 => x"7383ffff",
+30 => x"0b0b0b0b",
+31 => x"83a70400",
+32 => x"72098105",
+33 => x"72057373",
+34 => x"09060906",
+35 => x"73097306",
+36 => x"070a8106",
+37 => x"53510400",
+38 => x"00000000",
+39 => x"00000000",
+40 => x"72722473",
+41 => x"732e0753",
+42 => x"51040000",
+43 => x"00000000",
+44 => x"00000000",
+45 => x"00000000",
+46 => x"00000000",
+47 => x"00000000",
+48 => x"71737109",
+49 => x"71068106",
+50 => x"30720a10",
+51 => x"0a720a10",
+52 => x"0a31050a",
+53 => x"81065151",
+54 => x"53510400",
+55 => x"00000000",
+56 => x"72722673",
+57 => x"732e0753",
+58 => x"51040000",
+59 => x"00000000",
+60 => x"00000000",
+61 => x"00000000",
+62 => x"00000000",
+63 => x"00000000",
+64 => x"00000000",
+65 => x"00000000",
+66 => x"00000000",
+67 => x"00000000",
+68 => x"00000000",
+69 => x"00000000",
+70 => x"00000000",
+71 => x"00000000",
+72 => x"0b0b0b88",
+73 => x"c4040000",
+74 => x"00000000",
+75 => x"00000000",
+76 => x"00000000",
+77 => x"00000000",
+78 => x"00000000",
+79 => x"00000000",
+80 => x"720a722b",
+81 => x"0a535104",
+82 => x"00000000",
+83 => x"00000000",
+84 => x"00000000",
+85 => x"00000000",
+86 => x"00000000",
+87 => x"00000000",
+88 => x"72729f06",
+89 => x"0981050b",
+90 => x"0b0b88a7",
+91 => x"05040000",
+92 => x"00000000",
+93 => x"00000000",
+94 => x"00000000",
+95 => x"00000000",
+96 => x"72722aff",
+97 => x"739f062a",
+98 => x"0974090a",
+99 => x"8106ff05",
+100 => x"06075351",
+101 => x"04000000",
+102 => x"00000000",
+103 => x"00000000",
+104 => x"71715351",
+105 => x"020d0406",
+106 => x"73830609",
+107 => x"81058205",
+108 => x"832b0b2b",
+109 => x"0772fc06",
+110 => x"0c515104",
+111 => x"00000000",
+112 => x"72098105",
+113 => x"72050970",
+114 => x"81050906",
+115 => x"0a810653",
+116 => x"51040000",
+117 => x"00000000",
+118 => x"00000000",
+119 => x"00000000",
+120 => x"72098105",
+121 => x"72050970",
+122 => x"81050906",
+123 => x"0a098106",
+124 => x"53510400",
+125 => x"00000000",
+126 => x"00000000",
+127 => x"00000000",
+128 => x"71098105",
+129 => x"52040000",
+130 => x"00000000",
+131 => x"00000000",
+132 => x"00000000",
+133 => x"00000000",
+134 => x"00000000",
+135 => x"00000000",
+136 => x"72720981",
+137 => x"05055351",
+138 => x"04000000",
+139 => x"00000000",
+140 => x"00000000",
+141 => x"00000000",
+142 => x"00000000",
+143 => x"00000000",
+144 => x"72097206",
+145 => x"73730906",
+146 => x"07535104",
+147 => x"00000000",
+148 => x"00000000",
+149 => x"00000000",
+150 => x"00000000",
+151 => x"00000000",
+152 => x"71fc0608",
+153 => x"72830609",
+154 => x"81058305",
+155 => x"1010102a",
+156 => x"81ff0652",
+157 => x"04000000",
+158 => x"00000000",
+159 => x"00000000",
+160 => x"71fc0608",
+161 => x"0b0b80cf",
+162 => x"cc738306",
+163 => x"10100508",
+164 => x"060b0b0b",
+165 => x"88aa0400",
+166 => x"00000000",
+167 => x"00000000",
+168 => x"80088408",
+169 => x"88087575",
+170 => x"0b0b0b8b",
+171 => x"ab2d5050",
+172 => x"80085688",
+173 => x"0c840c80",
+174 => x"0c510400",
+175 => x"00000000",
+176 => x"80088408",
+177 => x"88087575",
+178 => x"0b0b0b8b",
+179 => x"ef2d5050",
+180 => x"80085688",
+181 => x"0c840c80",
+182 => x"0c510400",
+183 => x"00000000",
+184 => x"72097081",
+185 => x"0509060a",
+186 => x"8106ff05",
+187 => x"70547106",
+188 => x"73097274",
+189 => x"05ff0506",
+190 => x"07515151",
+191 => x"04000000",
+192 => x"72097081",
+193 => x"0509060a",
+194 => x"098106ff",
+195 => x"05705471",
+196 => x"06730972",
+197 => x"7405ff05",
+198 => x"06075151",
+199 => x"51040000",
+200 => x"05ff0504",
+201 => x"00000000",
+202 => x"00000000",
+203 => x"00000000",
+204 => x"00000000",
+205 => x"00000000",
+206 => x"00000000",
+207 => x"00000000",
+208 => x"810b0b0b",
+209 => x"80cfdc0c",
+210 => x"51040000",
+211 => x"00000000",
+212 => x"00000000",
+213 => x"00000000",
+214 => x"00000000",
+215 => x"00000000",
+216 => x"71810552",
+217 => x"04000000",
+218 => x"00000000",
+219 => x"00000000",
+220 => x"00000000",
+221 => x"00000000",
+222 => x"00000000",
+223 => x"00000000",
+224 => x"00000000",
+225 => x"00000000",
+226 => x"00000000",
+227 => x"00000000",
+228 => x"00000000",
+229 => x"00000000",
+230 => x"00000000",
+231 => x"00000000",
+232 => x"02840572",
+233 => x"10100552",
+234 => x"04000000",
+235 => x"00000000",
+236 => x"00000000",
+237 => x"00000000",
+238 => x"00000000",
+239 => x"00000000",
+240 => x"00000000",
+241 => x"00000000",
+242 => x"00000000",
+243 => x"00000000",
+244 => x"00000000",
+245 => x"00000000",
+246 => x"00000000",
+247 => x"00000000",
+248 => x"717105ff",
+249 => x"05715351",
+250 => x"020d0400",
+251 => x"00000000",
+252 => x"00000000",
+253 => x"00000000",
+254 => x"00000000",
+255 => x"00000000",
+256 => x"82c53f80",
+257 => x"c6e63f04",
+258 => x"10101010",
+259 => x"10101010",
+260 => x"10101010",
+261 => x"10101010",
+262 => x"10101010",
+263 => x"10101010",
+264 => x"10101010",
+265 => x"10101053",
+266 => x"51047381",
+267 => x"ff067383",
+268 => x"06098105",
+269 => x"83051010",
+270 => x"102b0772",
+271 => x"fc060c51",
+272 => x"51043c04",
+273 => x"72728072",
+274 => x"8106ff05",
+275 => x"09720605",
+276 => x"71105272",
+277 => x"0a100a53",
+278 => x"72ed3851",
+279 => x"51535104",
+280 => x"fe3d0d0b",
+281 => x"0b80dfc8",
+282 => x"08538413",
+283 => x"0870882a",
+284 => x"70810651",
+285 => x"52527080",
+286 => x"2ef03871",
+287 => x"81ff0680",
+288 => x"0c843d0d",
+289 => x"04ff3d0d",
+290 => x"0b0b80df",
+291 => x"c8085271",
+292 => x"0870882a",
+293 => x"81327081",
+294 => x"06515151",
+295 => x"70f13873",
+296 => x"720c833d",
+297 => x"0d0480cf",
+298 => x"dc08802e",
+299 => x"a43880cf",
+300 => x"e008822e",
+301 => x"bd388380",
+302 => x"800b0b0b",
+303 => x"80dfc80c",
+304 => x"82a0800b",
+305 => x"80dfcc0c",
+306 => x"8290800b",
+307 => x"80dfd00c",
+308 => x"04f88080",
+309 => x"80a40b0b",
+310 => x"0b80dfc8",
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+2881 => x"00002cf8",
+2882 => x"00002d00",
+2883 => x"00002d00",
+2884 => x"00002d08",
+2885 => x"00002d08",
+2886 => x"00002d10",
+2887 => x"00002d10",
+2888 => x"00002d18",
+2889 => x"00002d18",
+2890 => x"00002d20",
+2891 => x"00002d20",
+2892 => x"00002d28",
+2893 => x"00002d28",
+2894 => x"00002d30",
+2895 => x"00002d30",
+2896 => x"00002d38",
+2897 => x"00002d38",
+2898 => x"00002d40",
+2899 => x"00002d40",
+2900 => x"00002d48",
+2901 => x"00002d48",
+2902 => x"00002d50",
+2903 => x"00002d50",
+2904 => x"00002d58",
+2905 => x"00002d58",
+2906 => x"00002d60",
+2907 => x"00002d60",
+2908 => x"00002d68",
+2909 => x"00002d68",
+2910 => x"00002d70",
+2911 => x"00002d70",
+2912 => x"00002d78",
+2913 => x"00002d78",
+2914 => x"00002d80",
+2915 => x"00002d80",
+2916 => x"00002d88",
+2917 => x"00002d88",
+2918 => x"00002d90",
+2919 => x"00002d90",
+2920 => x"00002d98",
+2921 => x"00002d98",
+2922 => x"00002da0",
+2923 => x"00002da0",
+2924 => x"00002da8",
+2925 => x"00002da8",
+2926 => x"00002db0",
+2927 => x"00002db0",
+2928 => x"00002db8",
+2929 => x"00002db8",
+2930 => x"00002dc0",
+2931 => x"00002dc0",
+2932 => x"00002dc8",
+2933 => x"00002dc8",
+2934 => x"00002dd0",
+2935 => x"00002dd0",
+2936 => x"00002dd8",
+2937 => x"00002dd8",
+2938 => x"00002de0",
+2939 => x"00002de0",
+2940 => x"00002de8",
+2941 => x"00002de8",
+2942 => x"00002df0",
+2943 => x"00002df0",
+2944 => x"00002df8",
+2945 => x"00002df8",
+2946 => x"00002e00",
+2947 => x"00002e00",
+2948 => x"00002e08",
+2949 => x"00002e08",
+2950 => x"00002e10",
+2951 => x"00002e10",
+2952 => x"00002e18",
+2953 => x"00002e18",
+2954 => x"00002e20",
+2955 => x"00002e20",
+2956 => x"00002e28",
+2957 => x"00002e28",
+2958 => x"00002e30",
+2959 => x"00002e30",
+2960 => x"00002e38",
+2961 => x"00002e38",
+2962 => x"00002e40",
+2963 => x"00002e40",
+2964 => x"00002e48",
+2965 => x"00002e48",
+2966 => x"00002e50",
+2967 => x"00002e50",
+2968 => x"00002e58",
+2969 => x"00002e58",
+2970 => x"00002e60",
+2971 => x"00002e60",
+2972 => x"00002e68",
+2973 => x"00002e68",
+2974 => x"00002e70",
+2975 => x"00002e70",
+2976 => x"00002e78",
+2977 => x"00002e78",
+2978 => x"00002e80",
+2979 => x"00002e80",
+2980 => x"00002e88",
+2981 => x"00002e88",
+2982 => x"00002e90",
+2983 => x"00002e90",
+2984 => x"00002e98",
+2985 => x"00002e98",
+2986 => x"00002ea0",
+2987 => x"00002ea0",
+2988 => x"00002ea8",
+2989 => x"00002ea8",
+2990 => x"00002eb0",
+2991 => x"00002eb0",
+2992 => x"00002eb8",
+2993 => x"00002eb8",
+2994 => x"00002ec0",
+2995 => x"00002ec0",
+2996 => x"00002ec8",
+2997 => x"00002ec8",
+2998 => x"00002ed0",
+2999 => x"00002ed0",
+3000 => x"00002ed8",
+3001 => x"00002ed8",
+3002 => x"00002ee0",
+3003 => x"00002ee0",
+3004 => x"00002ee8",
+3005 => x"00002ee8",
+3006 => x"00002ef0",
+3007 => x"00002ef0",
+3008 => x"00002ef8",
+3009 => x"00002ef8",
+3010 => x"00002f00",
+3011 => x"00002f00",
+3012 => x"00002f08",
+3013 => x"00002f08",
+3014 => x"00002f10",
+3015 => x"00002f10",
+3016 => x"00002f18",
+3017 => x"00002f18",
+3018 => x"00002f20",
+3019 => x"00002f20",
+3020 => x"00002f28",
+3021 => x"00002f28",
+3022 => x"00002f30",
+3023 => x"00002f30",
+3024 => x"00002f38",
+3025 => x"00002f38",
+3026 => x"00002f40",
+3027 => x"00002f40",
+3028 => x"00002f48",
+3029 => x"00002f48",
+3030 => x"00002f50",
+3031 => x"00002f50",
+3032 => x"00002f58",
+3033 => x"00002f58",
+3034 => x"00002f60",
+3035 => x"00002f60",
+3036 => x"00002f68",
+3037 => x"00002f68",
+3038 => x"00002f70",
+3039 => x"00002f70",
+3040 => x"00002f78",
+3041 => x"00002f78",
+3042 => x"00002f80",
+3043 => x"00002f80",
+3044 => x"00002f88",
+3045 => x"00002f88",
+3046 => x"00002f90",
+3047 => x"00002f90",
+3048 => x"00002f98",
+3049 => x"00002f98",
+3050 => x"00002fa0",
+3051 => x"00002fa0",
+3052 => x"000027c0",
+3053 => x"ffffffff",
+3054 => x"00000000",
+3055 => x"ffffffff",
+3056 => x"00000000",
+	others => x"00000000"
+);
+
+begin
+
+process (clk)
+begin
+	if (clk'event and clk = '1') then
+		if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then
+			report "write collision" severity failure;
+		end if;
+	
+		if (memAWriteEnable = '1') then
+			ram(to_integer(unsigned(memAAddr))) := memAWrite;
+			memARead <= memAWrite;
+		else
+			memARead <= ram(to_integer(unsigned(memAAddr)));
+		end if;
+	end if;
+end process;
+
+process (clk)
+begin
+	if (clk'event and clk = '1') then
+		if (memBWriteEnable = '1') then
+			ram(to_integer(unsigned(memBAddr))) := memBWrite;
+			memBRead <= memBWrite;
+		else
+			memBRead <= ram(to_integer(unsigned(memBAddr)));
+		end if;
+	end if;
+end process;
+
+
+
+
+end dualport_ram_arch;
diff --git a/zpu/hdl/example/log.txt b/zpu/hdl/example/log.txt
new file mode 100644
index 0000000..6ee1d94
--- /dev/null
+++ b/zpu/hdl/example/log.txt
@@ -0,0 +1,20 @@
+Hello world 1
+
+Hello world 2
+
+Hello world 1
+
+Hello world 2
+
+Hello world 1
+
+Hello world 2
+
+Hello world 1
+
+Hello world 2
+
+Hello world 1
+
+Hello world 2
+
diff --git a/zpu/hdl/example/sim_small_fpga_top.vhd b/zpu/hdl/example/sim_small_fpga_top.vhd
new file mode 100644
index 0000000..909ea21
--- /dev/null
+++ b/zpu/hdl/example/sim_small_fpga_top.vhd
@@ -0,0 +1,197 @@
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+
+entity fpga_top is
+end fpga_top;
+
+
+architecture behave of fpga_top is
+
+
+    signal clk    : std_logic;
+    
+    signal areset : std_logic := '1';
+ 
+ 
+    component  zpu_io is
+        generic (
+            log_file:       string  := "log.txt"
+        );
+        port (
+            clk         : in  std_logic;
+            areset      : in  std_logic;
+            busy        : out std_logic;
+            writeEnable : in  std_logic;
+            readEnable  : in  std_logic;
+            write       : in  std_logic_vector(wordSize-1 downto 0);
+            read        : out std_logic_vector(wordSize-1 downto 0);
+            addr        : in  std_logic_vector(maxAddrBit downto minAddrBit)
+        );
+    end component;
+ 
+ 
+    signal mem_busy             : std_logic;
+    signal mem_read             : std_logic_vector(wordSize-1 downto 0);
+    signal mem_write            : std_logic_vector(wordSize-1 downto 0);
+    signal mem_addr             : std_logic_vector(maxAddrBitIncIO downto 0);
+    signal mem_writeEnable      : std_logic; 
+    signal mem_readEnable       : std_logic;
+    signal mem_writeMask        : std_logic_vector(wordBytes-1 downto 0);
+ 
+    signal enable               : std_logic;
+ 
+    signal dram_mem_busy        : std_logic;
+    signal dram_mem_read        : std_logic_vector(wordSize-1 downto 0);
+    signal dram_mem_write       : std_logic_vector(wordSize-1 downto 0);
+    signal dram_mem_writeEnable : std_logic; 
+    signal dram_mem_readEnable  : std_logic;
+    signal dram_mem_writeMask   : std_logic_vector(wordBytes-1 downto 0);
+ 
+    signal io_busy              : std_logic;
+ 
+    signal io_mem_read          : std_logic_vector(wordSize-1 downto 0);
+    signal io_mem_writeEnable   : std_logic; 
+    signal io_mem_readEnable    : std_logic;
+ 
+    signal dram_ready           : std_logic;
+    signal io_ready             : std_logic;
+    signal io_reading           : std_logic;
+    signal interruptcounter     : unsigned(15 downto 0);
+    signal interrupt            : std_logic;
+ 
+    signal break                : std_logic;
+
+begin
+
+    zpu: zpu_core 
+    port map (
+        clk                 => clk,
+        reset               => areset,
+        enable              => enable,
+        in_mem_busy         => mem_busy, 
+        mem_read            => mem_read,
+        mem_write           => mem_write, 
+        out_mem_addr        => mem_addr, 
+        out_mem_writeEnable => mem_writeEnable,  
+        out_mem_readEnable  => mem_readEnable,
+        mem_writeMask       => mem_writeMask, 
+        interrupt           => interrupt,
+        break               => break
+    );
+
+
+    ioMap: zpu_io 
+    port map (
+        clk         => clk,
+        areset      => areset,
+        busy        => io_busy,
+        writeEnable => io_mem_writeEnable,
+        readEnable  => io_mem_readEnable,
+        write       => mem_write,
+        read        => io_mem_read,
+        addr        => mem_addr(maxAddrBit downto minAddrBit)
+    );
+
+    dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit);
+    dram_mem_readEnable  <= mem_readEnable  and not mem_addr(ioBit);
+    io_mem_writeEnable   <= mem_writeEnable and mem_addr(ioBit);
+    io_mem_readEnable    <= mem_readEnable  and mem_addr(ioBit);
+    mem_busy             <= io_busy;
+    
+
+    -- Memory reads either come from IO or DRAM. We need to pick the right one.
+    memorycontrol: process(dram_mem_read, dram_ready, io_ready, io_mem_read)
+    begin
+        mem_read <= (others => 'U');
+        if dram_ready='1' then
+            mem_read <= dram_mem_read;
+        end if;
+             
+        if io_ready='1' then
+            mem_read <= (others => '0');
+            mem_read <= io_mem_read;
+        end if;
+    end process;
+
+    
+    io_ready <= (io_reading or io_mem_readEnable) and not io_busy;
+
+    memoryControlSync: process(clk, areset)
+    begin
+        if areset = '1' then
+            enable           <= '0';
+            io_reading       <= '0';
+            dram_ready       <= '0';
+            
+            interruptcounter <= to_unsigned(0, 16);
+            interrupt        <= '0'; 
+            
+        elsif rising_edge(clk) then
+            enable     <= '1';
+            io_reading <= io_busy or io_mem_readEnable; 
+            dram_ready <= dram_mem_readEnable;
+            
+            -- keep interrupt signal high for 16 cycles
+            interruptcounter <= interruptcounter + 1;
+            if (interruptcounter < 16) then
+                report "Interrupt asserted!" severity note;
+                interrupt <='1';
+            else
+                interrupt <='0';
+            end if;
+        end if;
+    end process;
+
+    -- wiggle the clock @ 100MHz
+    clock: process
+       begin
+            clk <= '0';
+           wait for 5 ns; 
+            clk <= '1';
+           wait for 5 ns; 
+           areset <= '0';
+    end process clock;
+
+
+end architecture behave;
diff --git a/zpu/hdl/example/sim_small_fpga_top_noint.vhd b/zpu/hdl/example/sim_small_fpga_top_noint.vhd
new file mode 100644
index 0000000..23b92cc
--- /dev/null
+++ b/zpu/hdl/example/sim_small_fpga_top_noint.vhd
@@ -0,0 +1,184 @@
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+
+entity fpga_top is
+end fpga_top;
+
+
+architecture behave of fpga_top is
+
+
+    signal clk    : std_logic;
+
+    signal areset : std_logic := '1';
+ 
+ 
+    component  zpu_io is
+        generic (
+            log_file:       string  := "log.txt"
+        );
+        port (
+            clk         : in  std_logic;
+            areset      : in  std_logic;
+            busy        : out std_logic;
+            writeEnable : in  std_logic;
+            readEnable  : in  std_logic;
+            write       : in  std_logic_vector(wordSize-1 downto 0);
+            read        : out std_logic_vector(wordSize-1 downto 0);
+            addr        : in  std_logic_vector(maxAddrBit downto minAddrBit)
+        );
+    end component;
+ 
+ 
+    signal mem_busy             : std_logic;
+    signal mem_read             : std_logic_vector(wordSize-1 downto 0);
+    signal mem_write            : std_logic_vector(wordSize-1 downto 0);
+    signal mem_addr             : std_logic_vector(maxAddrBitIncIO downto 0);
+    signal mem_writeEnable      : std_logic; 
+    signal mem_readEnable       : std_logic;
+    signal mem_writeMask        : std_logic_vector(wordBytes-1 downto 0);
+ 
+    signal enable               : std_logic;
+ 
+    signal dram_mem_busy        : std_logic;
+    signal dram_mem_read        : std_logic_vector(wordSize-1 downto 0);
+    signal dram_mem_write       : std_logic_vector(wordSize-1 downto 0);
+    signal dram_mem_writeEnable : std_logic; 
+    signal dram_mem_readEnable  : std_logic;
+    signal dram_mem_writeMask   : std_logic_vector(wordBytes-1 downto 0);
+ 
+    signal io_busy              : std_logic;
+ 
+    signal io_mem_read          : std_logic_vector(wordSize-1 downto 0);
+    signal io_mem_writeEnable   : std_logic; 
+    signal io_mem_readEnable    : std_logic;
+ 
+    signal dram_ready           : std_logic;
+    signal io_ready             : std_logic;
+    signal io_reading           : std_logic;
+
+    signal break                : std_logic;
+
+
+begin
+
+    zpu: zpu_core 
+    port map (
+        clk                 => clk,
+        reset               => areset,
+        enable              => enable,
+        in_mem_busy         => mem_busy, 
+        mem_read            => mem_read,
+        mem_write           => mem_write, 
+        out_mem_addr        => mem_addr, 
+        out_mem_writeEnable => mem_writeEnable,  
+        out_mem_readEnable  => mem_readEnable,
+        mem_writeMask       => mem_writeMask, 
+        interrupt           => '0',
+        break               => break
+    );
+
+
+    ioMap: zpu_io 
+    port map (
+        clk         => clk,
+        areset      => areset,
+        busy        => io_busy,
+        writeEnable => io_mem_writeEnable,
+        readEnable  => io_mem_readEnable,
+        write       => mem_write,
+        read        => io_mem_read,
+        addr        => mem_addr(maxAddrBit downto minAddrBit)
+    );
+
+    dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit);
+    dram_mem_readEnable  <= mem_readEnable  and not mem_addr(ioBit);
+    io_mem_writeEnable   <= mem_writeEnable and mem_addr(ioBit);
+    io_mem_readEnable    <= mem_readEnable  and mem_addr(ioBit);
+    mem_busy             <= io_busy;
+    
+
+    -- Memory reads either come from IO or DRAM. We need to pick the right one.
+    memorycontrol: process(dram_mem_read, dram_ready, io_ready, io_mem_read)
+    begin
+        mem_read <= (others => 'U');
+        if dram_ready='1' then
+            mem_read <= dram_mem_read;
+        end if;
+             
+        if io_ready='1' then
+            mem_read <= (others => '0');
+            mem_read <= io_mem_read;
+        end if;
+    end process;
+
+
+    
+    io_ready <= (io_reading or io_mem_readEnable) and not io_busy;
+
+    memoryControlSync: process(clk, areset)
+    begin
+        if areset = '1' then
+            enable     <= '0';
+            io_reading <= '0';
+            dram_ready <= '0';
+            
+        elsif rising_edge(clk) then
+            enable     <= '1';
+            io_reading <= io_busy or io_mem_readEnable; 
+            dram_ready <= dram_mem_readEnable;
+        end if;
+    end process;
+
+    -- wiggle the clock @ 100MHz
+    clock: process
+       begin
+            clk <= '0';
+           wait for 5 ns; 
+            clk <= '1';
+           wait for 5 ns; 
+           areset <= '0';
+    end process clock;
+
+
+end architecture behave;
diff --git a/zpu/hdl/example/simzpu_dmips.do b/zpu/hdl/example/simzpu_dmips.do
new file mode 100644
index 0000000..883259e
--- /dev/null
+++ b/zpu/hdl/example/simzpu_dmips.do
@@ -0,0 +1,29 @@
+# Xilinx WebPack modelsim script
+#
+# 
+# cd C:/workspace/zpu/zpu/hdl/example
+# do simzpu_dmips.do
+
+set BreakOnAssertion 1
+vlib work
+
+vcom -93 -explicit  zpu_config.vhd
+vcom -93 -explicit  ../zpu4/core/zpupkg.vhd
+vcom -93 -explicit  ../zpu4/src/txt_util.vhd
+vcom -93 -explicit  sim_small_fpga_top_noint.vhd
+vcom -93 -explicit  ../zpu4/core/zpu_core_small.vhd
+vcom -93 -explicit  bram_dmips.vhd
+vcom -93 -explicit  ../zpu4/src/timer.vhd
+vcom -93 -explicit  ../zpu4/src/io.vhd
+vcom -93 -explicit  ../zpu4/src/trace.vhd
+
+# run ZPU
+vsim fpga_top
+view wave
+add wave -recursive fpga_top/zpu/*
+#add wave -recursive fpga_top/*
+view structure
+#view signals
+
+# Enough to run tiny programs
+run 10 ms
diff --git a/zpu/hdl/example/simzpu_interrupt.do b/zpu/hdl/example/simzpu_interrupt.do
new file mode 100644
index 0000000..864bf76
--- /dev/null
+++ b/zpu/hdl/example/simzpu_interrupt.do
@@ -0,0 +1,29 @@
+# Xilinx WebPack modelsim script
+#
+# 
+# cd C:/workspace/zpu/zpu/hdl/example
+# do simzpu_interrupt.do
+
+set BreakOnAssertion 1
+vlib work
+
+vcom -93 -explicit  zpu_config.vhd
+vcom -93 -explicit  ../zpu4/core/zpupkg.vhd
+vcom -93 -explicit  ../zpu4/src/txt_util.vhd
+vcom -93 -explicit  sim_small_fpga_top.vhd
+vcom -93 -explicit  ../zpu4/core/zpu_core_small.vhd
+vcom -93 -explicit  interrupt.vhd
+vcom -93 -explicit  ../zpu4/src/timer.vhd
+vcom -93 -explicit  ../zpu4/src/io.vhd
+vcom -93 -explicit  ../zpu4/src/trace.vhd
+
+# run ZPU
+vsim fpga_top
+view wave
+add wave -recursive fpga_top/zpu/*
+#add wave -recursive fpga_top/*
+view structure
+#view signals
+
+# Enough to run tiny programs
+run 10 ms
diff --git a/zpu/hdl/example/simzpu_small.do b/zpu/hdl/example/simzpu_small.do
new file mode 100644
index 0000000..2b64926
--- /dev/null
+++ b/zpu/hdl/example/simzpu_small.do
@@ -0,0 +1,29 @@
+# Xilinx WebPack modelsim script
+#
+# 
+# cd C:/workspace/zpu/zpu/hdl/example
+# do simzpu_small.do
+
+set BreakOnAssertion 1
+vlib work
+
+vcom -93 -explicit  zpu_config.vhd
+vcom -93 -explicit  ../zpu4/core/zpupkg.vhd
+vcom -93 -explicit  ../zpu4/src/txt_util.vhd
+vcom -93 -explicit  sim_small_fpga_top_noint.vhd
+vcom -93 -explicit  ../zpu4/core/zpu_core_small.vhd
+vcom -93 -explicit  helloworld.vhd
+vcom -93 -explicit  ../zpu4/src/timer.vhd
+vcom -93 -explicit  ../zpu4/src/io.vhd
+vcom -93 -explicit  ../zpu4/src/trace.vhd
+
+# run ZPU
+vsim fpga_top
+view wave
+add wave -recursive fpga_top/zpu/*
+#add wave -recursive fpga_top/*
+view structure
+#view signals
+
+# Enough to run tiny programs
+run 10 ms
diff --git a/zpu/hdl/example/zpu_config.vhd b/zpu/hdl/example/zpu_config.vhd
new file mode 100644
index 0000000..cd4163d
--- /dev/null
+++ b/zpu/hdl/example/zpu_config.vhd
@@ -0,0 +1,55 @@
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
+-- 
+-- The FreeBSD license
+-- 
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+-- 
+-- 1. Redistributions of source code must retain the above copyright
+--    notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+--    copyright notice, this list of conditions and the following
+--    disclaimer in the documentation and/or other materials
+--    provided with the distribution.
+-- 
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-- 
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package zpu_config is
+	-- generate trace output
+	constant	Generate_Trace		: boolean := true;
+	constant 	wordPower			: integer := 5;
+	-- during simulation, set this to '0' to get matching trace.txt 
+	constant	DontCareValue		: std_logic := '0';
+	-- Clock frequency in MHz.
+	constant	ZPU_Frequency		: std_logic_vector(7 downto 0) := x"64";
+	-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
+	constant 	maxAddrBitIncIO		: integer := 27;
+	constant 	maxAddrBitBRAM		: integer := 16;
+		
+	-- start byte address of stack. 
+	-- point to top of RAM - 2*words
+	constant 	spStart				: std_logic_vector(maxAddrBitIncIO downto 0) :=
+					std_logic_vector(to_unsigned((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1));
+end zpu_config;
diff --git a/zpu/hdl/example/zpuromgen.c b/zpu/hdl/example/zpuromgen.c
new file mode 100644
index 0000000..fb8c4ba
--- /dev/null
+++ b/zpu/hdl/example/zpuromgen.c
@@ -0,0 +1,59 @@
+// zpuromgen.c
+//
+// Program to turn a binary file into a VHDL lookup table.
+//   by Adam Pierce
+//   29-Feb-2008
+//
+// This software is free to use by anyone for any purpose.
+//
+
+#include <unistd.h>
+#include <stdio.h>
+
+typedef uint8_t BYTE;
+
+main(int argc, char **argv)
+{
+       BYTE    opcode[4];
+       int     fd;
+       int     addr = 0;
+       ssize_t s;
+
+// Check the user has given us an input file.
+       if(argc < 2)
+       {
+               printf("Usage: %s <binary_file>\n\n", argv[0]);
+               return 1;
+       }
+
+// Open the input file.
+       fd = open(argv[1], 0);
+       if(fd == -1)
+       {
+               perror("File Open");
+               return 2;
+       }
+
+       while(1)
+       {
+       // Read 32 bits.
+               s = read(fd, opcode, 4);
+               if(s == -1)
+               {
+                       perror("File read");
+                       return 3;
+               }
+
+               if(s == 0)
+                       break; // End of file.
+
+       // Output to STDOUT.
+               printf("%6d => x\"%02x%02x%02x%02x\",\n",
+                      addr++, opcode[0], opcode[1],
+                      opcode[2], opcode[3]);
+       }
+
+       close(fd);
+       return 0;
+}
+
diff --git a/zpu/hdl/example/zpuromgen.exe b/zpu/hdl/example/zpuromgen.exe
new file mode 100644
index 0000000..6655412
--- /dev/null
+++ b/zpu/hdl/example/zpuromgen.exe
author	Bert Lange <b.lange@hzdr.de>	2015-04-15 13:36:55 +0200
committer	Bert Lange <b.lange@hzdr.de>	2015-04-15 13:36:55 +0200
commit	a1c964908b51599bf624bd2d253419c7e629f195 (patch)
tree	06125d59e83b7dde82d1bb57bc0e09ca83451b98 /zpu/hdl/example
parent	bbfe29a15f11548eb7c9fa71dcb4d2d18c164a53 (diff)
parent	8679e4f91dcae05aef40f96629f33f0f4161f14a (diff)
download	zpu-a1c964908b51599bf624bd2d253419c7e629f195.zip zpu-a1c964908b51599bf624bd2d253419c7e629f195.tar.gz