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authoroharboe <oharboe>2008-04-17 08:31:56 +0000
committeroharboe <oharboe>2008-04-17 08:31:56 +0000
commit167263dcae188a8812627ab52cfd96b8fdc5df8a (patch)
tree3d1f2b4c2eddfa5f9d3093a47d5ee3e0ae9ffff6 /zpu/hdl/example
parent748de9774226a19c32ee1ed6a4e6474e9e0acb27 (diff)
downloadzpu-167263dcae188a8812627ab52cfd96b8fdc5df8a.zip
zpu-167263dcae188a8812627ab52cfd96b8fdc5df8a.tar.gz
* deleted duplicate files from example folder.
Diffstat (limited to 'zpu/hdl/example')
-rw-r--r--zpu/hdl/example/io.vhd97
-rw-r--r--zpu/hdl/example/sim_fpga_top.vhd179
-rw-r--r--zpu/hdl/example/simzpu_small.do4
3 files changed, 2 insertions, 278 deletions
diff --git a/zpu/hdl/example/io.vhd b/zpu/hdl/example/io.vhd
deleted file mode 100644
index 7dbe36f..0000000
--- a/zpu/hdl/example/io.vhd
+++ /dev/null
@@ -1,97 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-use std.textio.all;
-
-library work;
-use work.zpu_config.all;
-use work.zpupkg.all;
-use work.txt_util.all;
-
-entity zpu_io is
- generic (
- log_file: string := "log.txt"
- );
- port(
- clk : in std_logic;
- areset : in std_logic;
- busy : out std_logic;
- writeEnable : in std_logic;
- readEnable : in std_logic;
- write : in std_logic_vector(wordSize-1 downto 0);
- read : out std_logic_vector(wordSize-1 downto 0);
- addr : in std_logic_vector(maxAddrBit downto minAddrBit)
- );
-end zpu_io;
-
-
-architecture behave of zpu_io is
-
-
-
-signal timer_read : std_logic_vector(7 downto 0);
---signal timer_write : std_logic_vector(7 downto 0);
-signal timer_we : std_logic;
-
-signal serving : std_logic;
-
-file l_file : TEXT open write_mode is log_file;
-
-begin
-
-
- timerinst: timer port map (
- clk => clk,
- areset => areset,
- we => timer_we,
- din => write(7 downto 0),
- adr => addr(4 downto 2),
- dout => timer_read);
-
- busy <= writeEnable or readEnable;
- timer_we <= writeEnable and addr(12);
-
- process(areset, clk)
- begin
- if (areset = '1') then
--- timer_we <= '0';
- elsif (clk'event and clk = '1') then
--- timer_we <= '0';
- if writeEnable = '1' then
- -- external interface
- if addr=x"2028003" then
- -- Write to UART
- -- report "" & character'image(conv_integer(memBint)) severity note;
- print(l_file, character'val(conv_integer(write)));
- elsif addr(12)='1' then
--- report "xxx" severity failure;
--- timer_we <= '1';
- else
- print(l_file, character'val(conv_integer(write)));
- report "Illegal IO write" severity warning;
- end if;
-
- end if;
- read <= (others => '0');
- if (readEnable = '1') then
- if addr=x"1001" then
- read <= (0=>'1', others => '0'); -- recieve empty
- elsif addr(12)='1' then
- read(7 downto 0) <= timer_read;
- elsif addr(11)='1' then
- read(7 downto 0) <= ZPU_Frequency;
- elsif addr=x"2028003" then
- read <= (others => '0');
- else
- read <= (others => '0');
- read(8) <= '1';
- report "Illegal IO read" severity warning;
- end if;
- end if;
- end if;
- end process;
-
-
-end behave;
-
diff --git a/zpu/hdl/example/sim_fpga_top.vhd b/zpu/hdl/example/sim_fpga_top.vhd
deleted file mode 100644
index b51fea0..0000000
--- a/zpu/hdl/example/sim_fpga_top.vhd
+++ /dev/null
@@ -1,179 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 20:15:31 04/14/05
--- Design Name:
--- Module Name: fpga_top - behave
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
-library UNISIM;
-use UNISIM.VComponents.all;
-
-library work;
-use work.zpu_config.all;
-use work.zpupkg.all;
-
-entity fpga_top is
-end fpga_top;
-
-architecture behave of fpga_top is
-
-
-signal clk : std_logic;
-
-signal areset : std_logic;
-
-
-component zpu_io is
- generic (
- log_file: string := "log.txt"
- );
- port(
- clk : in std_logic;
- areset : in std_logic;
- busy : out std_logic;
- writeEnable : in std_logic;
- readEnable : in std_logic;
- write : in std_logic_vector(wordSize-1 downto 0);
- read : out std_logic_vector(wordSize-1 downto 0);
- addr : in std_logic_vector(maxAddrBit downto minAddrBit)
- );
-end component;
-
-
-
-
-
-signal mem_busy : std_logic;
-signal mem_read : std_logic_vector(wordSize-1 downto 0);
-signal mem_write : std_logic_vector(wordSize-1 downto 0);
-signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);
-signal mem_writeEnable : std_logic;
-signal mem_readEnable : std_logic;
-signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
-
-signal enable : std_logic;
-
-signal dram_mem_busy : std_logic;
-signal dram_mem_read : std_logic_vector(wordSize-1 downto 0);
-signal dram_mem_write : std_logic_vector(wordSize-1 downto 0);
-signal dram_mem_writeEnable : std_logic;
-signal dram_mem_readEnable : std_logic;
-signal dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
-
-
-signal io_busy : std_logic;
-
-signal io_mem_read : std_logic_vector(wordSize-1 downto 0);
-signal io_mem_writeEnable : std_logic;
-signal io_mem_readEnable : std_logic;
-
-
-signal dram_ready : std_logic;
-signal io_ready : std_logic;
-signal io_reading : std_logic;
-
-
-signal break : std_logic;
-
-begin
- poweronreset: roc port map (O => areset);
-
-
-
- zpu: zpu_core port map (
- clk => clk ,
- areset => areset,
- enable => enable,
- in_mem_busy => mem_busy,
- mem_read => mem_read,
- mem_write => mem_write,
- out_mem_addr => mem_addr,
- out_mem_writeEnable => mem_writeEnable,
- out_mem_readEnable => mem_readEnable,
- mem_writeMask => mem_writeMask,
- interrupt => '0',
- break => break);
-
-
- ioMap: zpu_io port map (
- clk => clk,
- areset => areset,
- busy => io_busy,
- writeEnable => io_mem_writeEnable,
- readEnable => io_mem_readEnable,
- write => mem_write,
- read => io_mem_read,
- addr => mem_addr(maxAddrBit downto minAddrBit)
- );
-
- dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit);
- dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit);
- io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit);
- io_mem_readEnable <= mem_readEnable and mem_addr(ioBit);
- mem_busy <= io_busy;
-
-
-
- -- Memory reads either come from IO or DRAM. We need to pick the right one.
- memorycontrol:
- process(dram_mem_read, dram_ready, io_ready, io_mem_read)
- begin
- mem_read <= (others => 'U');
- if dram_ready='1' then
- mem_read <= dram_mem_read;
- end if;
-
- if io_ready='1' then
- mem_read <= (others => '0');
- mem_read <= io_mem_read;
- end if;
- end process;
-
-
- io_ready <= (io_reading or io_mem_readEnable) and not io_busy;
-
- memoryControlSync:
- process(clk, areset)
- begin
- if areset = '1' then
- enable <= '0';
- io_reading <= '0';
- dram_ready <= '0';
- elsif (clk'event and clk = '1') then
- enable <= '1';
- io_reading <= io_busy or io_mem_readEnable;
- dram_ready<=dram_mem_readEnable;
-
- end if;
- end process;
-
- -- wiggle the clock @ 100MHz
- clock : PROCESS
- begin
- clk <= '0';
- wait for 5 ns;
- clk <= '1';
- wait for 5 ns;
- end PROCESS clock;
-
-
-end behave;
diff --git a/zpu/hdl/example/simzpu_small.do b/zpu/hdl/example/simzpu_small.do
index 5fb906d..1f8f358 100644
--- a/zpu/hdl/example/simzpu_small.do
+++ b/zpu/hdl/example/simzpu_small.do
@@ -10,11 +10,11 @@ vlib work
vcom -93 -explicit zpu_config.vhd
vcom -93 -explicit ../zpu4/src/zpupkg.vhd
vcom -93 -explicit ../zpu4/src/txt_util.vhd
-vcom -93 -explicit sim_fpga_top.vhd
+vcom -93 -explicit ../zpu4/src/sim_small_fpga_top.vhd
vcom -93 -explicit ../zpu4/src/zpu_core_small.vhd
vcom -93 -explicit helloworld.vhd
vcom -93 -explicit ../zpu4/src/timer.vhd
-vcom -93 -explicit io.vhd
+vcom -93 -explicit ../zpu4/src/io.vhd
vcom -93 -explicit ../zpu4/src/trace.vhd
# run ZPU
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