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| author | oharboe <oharboe> | 2008-08-18 12:28:59 +0000 |
|---|---|---|
| committer | oharboe <oharboe> | 2008-08-18 12:28:59 +0000 |
| commit | 7792f314b6b259b9d5088337dad4c9e8519ce095 (patch) | |
| tree | 59402b77f82bb2598a500cca28bf808924d4f5f6 /zpu/docs | |
| parent | 431a1bf775d468bcd788c3dd716b97cc0fca1f34 (diff) | |
| download | zpu-7792f314b6b259b9d5088337dad4c9e8519ce095.zip zpu-7792f314b6b259b9d5088337dad4c9e8519ce095.tar.gz | |
very early work.
Diffstat (limited to 'zpu/docs')
| -rw-r--r-- | zpu/docs/zpu_arch.html | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index d8d982d..21b7df5 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -1335,6 +1335,12 @@ pushed onto stack before jumping to unkonwn instruction vector. This makes it po to write denser microcode for missing instructions. For emulated opcodes that are not in use, the microcode can more easily be disabled. Determining that e.g. MULT is not used, can be a bit tricky, but disabling it is easy. +<p> +The address of this entry will be 0x10. The reason 0x00 is not used is that +GCC needs 0x00-0x0b inclusive to store R0-R2(memory mapped GCC registers). +The reset vector remains 0x0 so the 0x00-0x0f addresses contains the +first few instructions executed by the ZPU. Some very early work has been +done in <a href="../sw/startup/nextgen_crt0.S"> nextgen_crt0.S</a>. <li>Single entry for *all* unknown instructions does not limit emulation to the EMULATE instructions today, but instructions such as OR, LOADSP, STORESP, ADDSP, etc. can also be emulated. This opens up for further reduction in logic usage. |
