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author | oharboe <oharboe> | 2008-06-18 09:22:21 +0000 |
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committer | oharboe <oharboe> | 2008-06-18 09:22:21 +0000 |
commit | 0711a2b4fc2dec8bf65e5821095bed895976b83a (patch) | |
tree | 7638a9d98dc7b15b4a6589de15772fe44125bea6 /misc/readme.txt | |
parent | 6647b91cf267e7e155c95c6adbcfbc43f083356b (diff) | |
download | zpu-0711a2b4fc2dec8bf65e5821095bed895976b83a.zip zpu-0711a2b4fc2dec8bf65e5821095bed895976b83a.tar.gz |
* Various ZY2000 vhdl files of more general interest made
available as part of the ZPU project under the same
license(FreeBSD). Files should have headers updated.
Diffstat (limited to 'misc/readme.txt')
-rw-r--r-- | misc/readme.txt | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/misc/readme.txt b/misc/readme.txt new file mode 100644 index 0000000..0ae1786 --- /dev/null +++ b/misc/readme.txt @@ -0,0 +1,20 @@ +These files are provided as is under a FreeBSD license. + +Patches most gratefully accepted to document this better. + +These are parts of the VHDL code that went into ZY2000 that +can be used on other FPGA brands and with other parts than +went into ZY2000. + +http://www.zylin.com/protoboard.htm + +The long term plan is to split out these from the ZPU project +into a DDR controller and ARM7 wishbone bridge +project on OpenCores.org and document them. + +Directories +=========== +arm7 - ARM7 wishbone interface +ddsdram - a generic ddr ram controller. Implemented for Xilinx + mt46v16m16 but +can be adapted to other FPGA brands and DRAM chips +wishbone - atomic 32 bit wishbone access inside FPGA and in ARM7 SW, over a 16 bit CPU databus
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