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| author | Bert Lange <b.lange@hzdr.de> | 2015-04-15 13:36:55 +0200 |
|---|---|---|
| committer | Bert Lange <b.lange@hzdr.de> | 2015-04-15 13:36:55 +0200 |
| commit | a1c964908b51599bf624bd2d253419c7e629f195 (patch) | |
| tree | 06125d59e83b7dde82d1bb57bc0e09ca83451b98 /misc/ddrsdram/simscripts/ddr_tb.do | |
| parent | bbfe29a15f11548eb7c9fa71dcb4d2d18c164a53 (diff) | |
| parent | 8679e4f91dcae05aef40f96629f33f0f4161f14a (diff) | |
| download | zpu-a1c964908b51599bf624bd2d253419c7e629f195.zip zpu-a1c964908b51599bf624bd2d253419c7e629f195.tar.gz | |
Merge branch 'master' of https://github.com/zylin/zpu
Diffstat (limited to 'misc/ddrsdram/simscripts/ddr_tb.do')
| -rw-r--r-- | misc/ddrsdram/simscripts/ddr_tb.do | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/misc/ddrsdram/simscripts/ddr_tb.do b/misc/ddrsdram/simscripts/ddr_tb.do new file mode 100644 index 0000000..1f643f1 --- /dev/null +++ b/misc/ddrsdram/simscripts/ddr_tb.do @@ -0,0 +1,16 @@ +vlib work
+vcom -93 -explicit ../src/ddr_pkg.vhd
+vcom -93 -explicit ../src/ddr_top.vhd
+vcom -93 -explicit ../src/mt46v16m16.vhd
+vcom -93 -explicit ../simsrc/ddr_tb.vhd
+vsim -t 1ps ddr_tb
+view wave
+view signals
+radix hex
+add wave *
+add wave sim:/ddr_tb/ddr_ctrl/*
+force -freeze sim:/ddr_tb/areset 1 0
+run 10 ns
+force -freeze sim:/ddr_tb/areset 0 0
+when sim:/ddr_tb/break_out stop
+run 10 ms
\ No newline at end of file |
