rename directorys

5 files changed, 0 insertions, 488 deletions

diff --git a/hw_v5_fx30t_extension/synthese/Makefile b/hw_v5_fx30t_extension/synthese/Makefile
deleted file mode 100644
index da1819b..0000000
--- a/hw_v5_fx30t_extension/synthese/Makefile
+++ /dev/null
@@ -1,140 +0,0 @@
-#
-# $HeadURL: https://svn.fzd.de/repo/concast/FWF_Projects/FWKE/beam_position_monitor/hardware/board_sp605/synthese/Makefile $
-# $Date: 2011-08-29 13:52:33 +0200 (Mo, 29. Aug 2011) $
-# $Author: lange $
-# $Revision: 1226 $
-#
-
-MODULE = top
-DEVICE = xc5vfx30t-ff665-1
-UCF_FILE = virtex5_fx30t_eval.ucf
-CORES = ../cores/
-SOFTWARE = ../../../software/test
-DATE = $(shell date +"%Y-%m-%d__%H_%M")
-LOGFILE = synthesis_log_$(DATE).txt
-export XST_LOGFILE := $(LOGFILE)
-
-
-all:	
-	@echo "check     - look for timing and other synthesis issues"
-	@echo "xst       - generate ngc file (netlist, replaces edif and netlist constrains)"
-	@echo "translate - generate ngd file (native generic database [reduced to primitives])"
-	@echo "map       - generate ncd file (native ciruit description)"
-	@echo "par       - place&route ncd file (design implementation)"
-	@echo "trace     - generate timing report"
-	@echo "bitgen    - generate bit file (ncd -> bit)"
-	@echo "update    - update bitstream with elf file"
-	@echo "program   - program fpga with bit file"
-	@echo "genmcs    - genrate mcs file"
-	@echo "progspi   - program spi flash with mcs file"
-	@echo "clean"
-	@echo "..."
-	@echo "testflow  - update bitgen update program check"
-	@echo "finalflow - update bitgen update progspi check"
-
-testflow: 
-	$(MAKE) bitgen update program check     2>&1 | tee $(XST_LOGFILE)
-
-finalflow:
-	$(MAKE) bitgen update progspi check     2>&1 | tee $(XST_LOGFILE)
-
-
-check:
-	@echo -e "Timing score: "
-	@grep --with-filename "Timing Score"                xst/*.par
-	@echo -e "\nUnwanted Latches (737): "           
-	@grep --with-filename "WARNING:Xst:737"             xst/*.syr || echo -n
-	@echo -e "\nUnassigned signals (653): "         
-	@grep --with-filename "WARNING:Xst:653"             xst/*.syr || echo -n
-	@echo -e "\nCombinatoric loops (2170): "        
-	@grep --with-filename "WARNING:Xst:2170"            xst/*.syr || echo -n
-	@echo -e "\n Gated clocks (372): "
-	@grep --with-filename "WARNING:PhysDesignRules:372" xst/*.bgn || echo -n
-
-
-update:
-	make all --directory $(SOFTWARE)
-	data2mem -bm zpu_i0_memory_64k.bmm -bd $(SOFTWARE)/*.elf -bt xst/$(MODULE).bit -o b xst/$(MODULE)_update.bit
-
-
-program:
-	impact -batch program_fpga.cmd
-
-
-genmcs:
-	promgen -spi -p mcs -w -o $(MODULE)_update.mcs -s 8192 -u 0 xst/$(MODULE)_update.bit
-
-
-progspi: genmcs
-	impact -batch program_spi.cmd
-
-
-clean:
-	rm -f *.log
-	rm -f _impact.cmd
-	rm -f *.cfi
-	rm -f *.prm
-	rm -rf xst
-
-
-dir:	
-	mkdir -p xst
-	mkdir -p xst/projnav.tmp
-	cp *.xst xst
-	cp *.prj xst
-	cp *.ut  xst
-
-xst:    $(MODULE).ngc
-translate: $(MODULE).ngd
-map:    $(MODULE)_map.ncd
-par:    $(MODULE).ncd
-
-#.PHONY: xst
-
-hw_timestamp:
-	make --directory ../rtl
-
-$(MODULE).ngc: dir 
-	cd xst ; xst -ifn $(MODULE).xst -ofn $(MODULE).syr
-
-
-$(MODULE).ngd: $(MODULE).ngc $(UCF_FILE)
-	cd xst ; ngdbuild -dd _ngo -nt timestamp -uc ../$(UCF_FILE) -p $(DEVICE) -sd ../$(CORES) $(MODULE).ngc $(MODULE).ngd
-
-	# -p                    part number
-	# -mt                   multi-threading
-	# -w                    overwrite existing files
-	# -logic_opt            logic optimization
-	# -ol                   overall effor level (std|high)
-	# -t	                placer cost table
-	# -register_duplication duplicate registers
-	# -global_opt	        Global Optimization (off|speed|area|power)
-	# -ir                   ignore RLOCs
-	# -pr			pack registers in IO (off|i|o|b)
-	# -lc                   lut combining (auto|area|off)
-	# -power		Virtex 6 Power Optimization (on|off|high|xe)
-	# -detail		Generate Detailed MAP Report
-	# -o			Output File Name
-	# -bp                   enables block RAM mapping
-$(MODULE)_map.ncd: $(MODULE).ngd
-	cd xst ; export XIL_PAR_DESIGN_CHECK_VERBOSE=1; map -p $(DEVICE) -mt 2 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -ir off -pr off -lc off -power off -detail -o $(MODULE)_map.ncd $(MODULE).ngd $(MODULE).pcf
-
-
-$(MODULE).ncd: $(MODULE)_map.ncd
-	cd xst ; par -w -mt 4 -ol high $(MODULE)_map.ncd $(MODULE).ncd $(MODULE).pcf
-
-
-trace:
-	cd xst ; trce -e -a -u -s 2 -xml $(MODULE).twx $(MODULE).ncd -o $(MODULE).twr $(MODULE).pcf
-
-tracefast:
-	cd xst ; trce -v 12 -fastpaths -xml $(MODULE).twx -o $(MODULE).twr $(MODULE).ncd $(MODULE).pcf
-
-
-bitgen: $(MODULE).ncd
-	cd xst ; bitgen -d -f $(MODULE).ut $(MODULE).ncd
-
-upload: xst/$(MODULE).bit
-	scp xst/$(MODULE).bit bl5599@uts:
-
-
diff --git a/hw_v5_fx30t_extension/synthese/top.prj b/hw_v5_fx30t_extension/synthese/top.prj
deleted file mode 100644
index 83c45d1..0000000
--- a/hw_v5_fx30t_extension/synthese/top.prj
+++ /dev/null
@@ -1 +0,0 @@
-vhdl work "../../rtl/top.vhd"

diff --git a/hw_v5_fx30t_extension/synthese/top.ut b/hw_v5_fx30t_extension/synthese/top.ut
deleted file mode 100644
index 613bf04..0000000
--- a/hw_v5_fx30t_extension/synthese/top.ut
+++ /dev/null
@@ -1,39 +0,0 @@
--w

--g DebugBitstream:No

--g Binary:no

--g CRC:Enable

--g ConfigRate:2

--g CclkPin:PullUp

--g M0Pin:PullUp

--g M1Pin:PullUp

--g M2Pin:PullUp

--g ProgPin:PullUp

--g DonePin:PullUp

--g InitPin:Pullup

--g CsPin:Pullup

--g DinPin:Pullup

--g BusyPin:Pullup

--g RdWrPin:Pullup

--g HswapenPin:PullUp

--g TckPin:PullUp

--g TdiPin:PullUp

--g TdoPin:PullUp

--g TmsPin:PullUp

--g UnusedPin:PullDown

--g UserID:0xFFFFFFFF

--g ConfigFallback:Enable

--g SelectMAPAbort:Enable

--g BPI_page_size:1

--g OverTempPowerDown:Disable

--g JTAG_SysMon:Enable

--g DCIUpdateMode:AsRequired

--g StartUpClk:CClk

--g DONE_cycle:4

--g GTS_cycle:5

--g GWE_cycle:6

--g LCK_cycle:NoWait

--g Match_cycle:Auto

--g Security:None

--g DonePipe:No

--g DriveDone:Yes

--g Encrypt:No

diff --git a/hw_v5_fx30t_extension/synthese/top.xst b/hw_v5_fx30t_extension/synthese/top.xst
deleted file mode 100644
index 10878e1..0000000
--- a/hw_v5_fx30t_extension/synthese/top.xst
+++ /dev/null
@@ -1,61 +0,0 @@
-set -tmpdir "projnav.tmp"

-set -xsthdpdir "xst"

-run

--ifn top.prj

--ifmt mixed

--ofn top

--ofmt NGC

--p xc5vfx30t-1-ff665

--top top

--opt_mode Speed

--opt_level 1

--power NO

--iuc NO

--keep_hierarchy No

--netlist_hierarchy As_Optimized

--rtlview Yes

--glob_opt AllClockNets

--read_cores YES

--write_timing_constraints NO

--cross_clock_analysis NO

--hierarchy_separator /

--bus_delimiter <>

--case Maintain

--slice_utilization_ratio 100

--bram_utilization_ratio 100

--dsp_utilization_ratio 100

-# lut combinig

--lc Off

--reduce_control_sets Off

--verilog2001 YES

--fsm_extract YES -fsm_encoding Auto

--safe_implementation No

--fsm_style LUT

--ram_extract Yes

--ram_style Auto

--rom_extract Yes

--mux_style Auto

--decoder_extract YES

--priority_extract Yes

--shreg_extract YES

--shift_extract YES

--xor_collapse YES

--rom_style Auto

--auto_bram_packing NO

--mux_extract Yes

--resource_sharing YES

--async_to_sync NO

--use_dsp48 Auto

--iobuf YES

--max_fanout 100000

--bufg 32

--register_duplication YES

--register_balancing No

--slice_packing YES

--optimize_primitives NO

--use_clock_enable Auto

--use_sync_set Auto

--use_sync_reset Auto

--iob Auto

--equivalent_register_removal YES

--slice_utilization_ratio_maxmargin 5

diff --git a/hw_v5_fx30t_extension/synthese/virtex5_fx30t_eval.ucf b/hw_v5_fx30t_extension/synthese/virtex5_fx30t_eval.ucf
deleted file mode 100644
index 81e18ec..0000000
--- a/hw_v5_fx30t_extension/synthese/virtex5_fx30t_eval.ucf
+++ /dev/null
@@ -1,247 +0,0 @@
-############################################################################
-## This system.ucf file is generated by Base System Builder based on the
-## settings in the selected Xilinx Board Definition file. Please add other
-## user constraints to this file based on customer design specifications.
-##
-##
-## modified Bert Lange
-## 2011-09-08
-############################################################################
-
-NET sys_clk                            LOC= E18  | IOSTANDARD = LVCMOS33;
-NET clk_socket                         LOC= E13  | IOSTANDARD = LVCMOS33;
-#NET sys_rst                           LOC= AF20 | IOSTANDARD = LVCMOS18; button sw1
-#NET sys_rst TIG;
-

-
-## System level constraints
-NET sys_clk TNM_NET = sys_clk;
-TIMESPEC TS_sys_clk = PERIOD sys_clk 10000 ps;
-
-
-## IO Devices constraints
-
-#### Module RS232 constraints
-
-NET RS232_RX                           LOC= K8   | IOSTANDARD = LVCMOS33;
-NET RS232_TX                           LOC= L8   | IOSTANDARD = LVCMOS33;
-#NET RS232_RTS                         LOC= N8   | IOSTANDARD = LVCMOS33; # Jumper J3
-#NET RS232_CTS                         LOC= R8   | IOSTANDARD = LVCMOS33; # Jumper J4
-
-#### Module RS232_USB constraints
-
-NET RS232_USB_RX                       LOC= AA10 | IOSTANDARD = LVCMOS33;
-NET RS232_USB_TX                       LOC= AA19 | IOSTANDARD = LVCMOS33;
-NET RS232_USB_reset_dummy              LOC= Y20  | IOSTANDARD = LVCMOS33;
-
-#### Module LEDs_8Bit constraints
-
-NET GPIO_LED_out<0>                    LOC= AF22 | IOSTANDARD = LVCMOS18 | PULLUP;
-NET GPIO_LED_out<1>                    LOC= AF23 | IOSTANDARD = LVCMOS18 | PULLUP;
-NET GPIO_LED_out<2>                    LOC= AF25 | IOSTANDARD = LVCMOS18 | PULLUP;
-NET GPIO_LED_out<3>                    LOC= AE25 | IOSTANDARD = LVCMOS18 | PULLUP;
-NET GPIO_LED_out<4>                    LOC= AD25 | IOSTANDARD = LVCMOS18 | PULLUP;
-NET GPIO_LED_out<5>                    LOC= AE26 | IOSTANDARD = LVCMOS18 | PULLUP;
-NET GPIO_LED_out<6>                    LOC= AD26 | IOSTANDARD = LVCMOS18 | PULLUP;
-NET GPIO_LED_out<7>                    LOC= AC26 | IOSTANDARD = LVCMOS18 | PULLUP;
-
-#### Module DIP_Switches_8Bit constraints
-
-NET GPIO_DIPswitch_in<0>               LOC= AD13 | IOSTANDARD = LVCMOS18;
-NET GPIO_DIPswitch_in<1>               LOC= AE13 | IOSTANDARD = LVCMOS18;
-NET GPIO_DIPswitch_in<2>               LOC= AF13 | IOSTANDARD = LVCMOS18;
-NET GPIO_DIPswitch_in<3>               LOC= AD15 | IOSTANDARD = LVCMOS18;
-NET GPIO_DIPswitch_in<4>               LOC= AD14 | IOSTANDARD = LVCMOS18;
-NET GPIO_DIPswitch_in<5>               LOC= AF14 | IOSTANDARD = LVCMOS18;
-NET GPIO_DIPswitch_in<6>               LOC= AE15 | IOSTANDARD = LVCMOS18;
-NET GPIO_DIPswitch_in<7>               LOC= AF15 | IOSTANDARD = LVCMOS18;
-
-#### Module Push_Buttons_3Bit constraints
-
-NET GPIO_button_in<0>                  LOC= AF20 | IOSTANDARD = LVCMOS18 | PULLUP; #PB1
-NET GPIO_button_in<1>                  LOC= AE20 | IOSTANDARD = LVCMOS18 | PULLUP; #PB2
-NET GPIO_button_in<2>                  LOC= AD19 | IOSTANDARD = LVCMOS18 | PULLUP; #PB3
-NET GPIO_button_in<3>                  LOC= AD20 | IOSTANDARD = LVCMOS18 | PULLUP; #PB4
-
-#### Module FLASH_8Mx16 constraints
-
-
-NET FLASH_8Mx16_Mem_A<31>              LOC= Y11  | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_A<30>              LOC= H9   | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_A<29>              LOC= G10  | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_A<28>              LOC= H21  | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_A<27>              LOC= G20  | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_A<26>              LOC= H11  | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_A<25>              LOC= G11  | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_A<24>              LOC= H19  | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_A<23>              LOC= H18  | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_A<22>              LOC= G12  | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_A<21>              LOC= F13  | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_A<20>              LOC= G19  | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_A<19>              LOC= F18  | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_A<18>              LOC= F14  | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_A<17>              LOC= F15  | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_A<16>              LOC= F17  | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_A<15>              LOC= G17  | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_A<14>              LOC= G14  | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_A<13>              LOC= H13  | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_A<12>              LOC= G16  | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_A<11>              LOC= G15  | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_A<10>              LOC= Y18  | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_A<9>               LOC= AA18 | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_A<8>               LOC= Y10  | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_A<7>               LOC= W11  | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_DQ<15>             LOC= AA15 | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_DQ<14>             LOC= Y15  | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_DQ<13>             LOC= W14  | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_DQ<12>             LOC= Y13  | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_DQ<11>             LOC= W16  | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_DQ<10>             LOC= Y16  | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_DQ<9>              LOC= AA14 | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_DQ<8>              LOC= AA13 | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_DQ<7>              LOC= AB12 | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_DQ<6>              LOC= AC11 | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_DQ<5>              LOC= AB20 | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_DQ<4>              LOC= AB21 | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_DQ<3>              LOC= AB11 | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_DQ<2>              LOC= AB10 | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_DQ<1>              LOC= AA20 | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_DQ<0>              LOC= Y21  | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_WEN                LOC= AA17 | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_OEN<0>             LOC= AA12 | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_Mem_CEN<0>             LOC= Y12  | IOSTANDARD = LVCMOS33;
-NET FLASH_8Mx16_rpn_dummy              LOC= D13  | IOSTANDARD = LVCMOS33;
-#NET FLASH_8Mx16_byte_dummy            LOC= Y17  | IOSTANDARD = LVCMOS33;
-#NET FLASH_8Mx16_adv_dummy             LOC= F19  | IOSTANDARD = LVCMOS33;
-#NET FLASH_8Mx16_clk_dummy             LOC= E12  | IOSTANDARD = LVCMOS33;
-#NET FLASH_8Mx16_wait_dummy            LOC= D16  | IOSTANDARD = LVCMOS33;
-
-
-
-
-#### Module DDR2_SDRAM_16Mx32 constraints
-
-NET DDR2_SDRAM_16Mx32_DDR2_ODT<0>      LOC= AF24 | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_A<0>        LOC= U25  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_A<1>        LOC= T25  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_A<2>        LOC= T24  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_A<3>        LOC= T23  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_A<4>        LOC= U24  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_A<5>        LOC= V24  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_A<6>        LOC= Y23  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_A<7>        LOC= W23  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_A<8>        LOC= AA25 | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_A<9>        LOC= AB26 | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_A<10>       LOC= AB25 | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_A<11>       LOC= AB24 | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_A<12>       LOC= AA23 | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_BA<0>       LOC= U21  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_BA<1>       LOC= V22  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_CAS_N       LOC= W24  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_CKE         LOC= T22  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_CS_N        LOC= AD24 | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_RAS_N       LOC= Y22  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_WE_N        LOC= AA22 | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DM<0>       LOC= U26  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DM<1>       LOC= N24  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DM<2>       LOC= M24  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DM<3>       LOC= M25  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQS<0>      LOC= W26  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQS<1>      LOC= L23  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQS<2>      LOC= K22  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQS<3>      LOC= J21  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQS_N<0>    LOC= W25  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQS_N<1>    LOC= L22  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQS_N<2>    LOC= K23  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQS_N<3>    LOC= K21  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQ<0>       LOC= R22  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQ<1>       LOC= R23  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQ<2>       LOC= P23  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQ<3>       LOC= P24  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQ<4>       LOC= R25  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQ<5>       LOC= P25  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQ<6>       LOC= R26  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQ<7>       LOC= P26  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQ<8>       LOC= M26  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQ<9>       LOC= N26  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQ<10>      LOC= K25  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQ<11>      LOC= L24  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQ<12>      LOC= K26  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQ<13>      LOC= J26  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQ<14>      LOC= J25  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQ<15>      LOC= N21  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQ<16>      LOC= M21  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQ<17>      LOC= J23  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQ<18>      LOC= H23  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQ<19>      LOC= H22  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQ<20>      LOC= G22  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQ<21>      LOC= F22  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQ<22>      LOC= F23  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQ<23>      LOC= E23  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQ<24>      LOC= G24  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQ<25>      LOC= F24  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQ<26>      LOC= G25  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQ<27>      LOC= H26  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQ<28>      LOC= G26  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQ<29>      LOC= F25  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQ<30>      LOC= E25  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_DQ<31>      LOC= E26  | IOSTANDARD = SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_CK<0>       LOC= V21  | IOSTANDARD = DIFF_SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_CK<1>       LOC= N22  | IOSTANDARD = DIFF_SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_CK_N<0>     LOC= W21  | IOSTANDARD = DIFF_SSTL18_II;
-NET DDR2_SDRAM_16Mx32_DDR2_CK_N<1>     LOC= M22  | IOSTANDARD = DIFF_SSTL18_II;
-
-#### Module Ethernet_MAC constraints
-
-NET Ethernet_MAC_DUMMY_ETH_TXER        LOC= A22  | IOSTANDARD = LVCMOS33;
-NET Ethernet_MAC_PHY_tx_clk            LOC= E17  | IOSTANDARD = LVCMOS33 | PERIOD=40000 ps;
-NET Ethernet_MAC_PHY_rx_clk            LOC= E20  | IOSTANDARD = LVCMOS33 | PERIOD=40000 ps;
-NET Ethernet_MAC_PHY_crs               LOC= A25  | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
-NET Ethernet_MAC_PHY_dv                LOC= C21  | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
-NET Ethernet_MAC_PHY_rx_data<0>        LOC= D24  | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
-NET Ethernet_MAC_PHY_rx_data<1>        LOC= D23  | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
-NET Ethernet_MAC_PHY_rx_data<2>        LOC= D21  | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
-NET Ethernet_MAC_PHY_rx_data<3>        LOC= C26  | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
-NET Ethernet_MAC_PHY_col               LOC= A24  | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
-NET Ethernet_MAC_PHY_rx_er             LOC= B24  | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE;
-NET Ethernet_MAC_PHY_tx_en             LOC= A23  | IOSTANDARD = LVCMOS33;
-NET Ethernet_MAC_PHY_tx_data<0>        LOC= D19  | IOSTANDARD = LVCMOS33;
-NET Ethernet_MAC_PHY_tx_data<1>        LOC= C19  | IOSTANDARD = LVCMOS33;
-NET Ethernet_MAC_PHY_tx_data<2>        LOC= A20  | IOSTANDARD = LVCMOS33;
-NET Ethernet_MAC_PHY_tx_data<3>        LOC= B20  | IOSTANDARD = LVCMOS33;
-NET Ethernet_MAC_PHY_rst_n             LOC= B26  | IOSTANDARD = LVCMOS33;
-NET Ethernet_MAC_PHY_Mii_clk           LOC= D26  | IOSTANDARD = LVCMOS33;
-NET Ethernet_MAC_PHY_Mii_data          LOC= D25  | IOSTANDARD = LVCMOS33;
-
-#### Module SysACE_CompactFlash constraints
-
-NET SysACE_CompactFlash_SysACE_CLK     LOC= F12  | IOSTANDARD = LVCMOS33;
-NET SysACE_CompactFlash_SysACE_MPA<0>  LOC= Y5   | IOSTANDARD = LVCMOS33;
-NET SysACE_CompactFlash_SysACE_MPA<1>  LOC= V7   | IOSTANDARD = LVCMOS33;
-NET SysACE_CompactFlash_SysACE_MPA<2>  LOC= W6   | IOSTANDARD = LVCMOS33;
-NET SysACE_CompactFlash_SysACE_MPA<3>  LOC= W5   | IOSTANDARD = LVCMOS33;
-NET SysACE_CompactFlash_SysACE_MPA<4>  LOC= K6   | IOSTANDARD = LVCMOS33;
-NET SysACE_CompactFlash_SysACE_MPA<5>  LOC= J5   | IOSTANDARD = LVCMOS33;
-NET SysACE_CompactFlash_SysACE_MPA<6>  LOC= J6   | IOSTANDARD = LVCMOS33;
-NET SysACE_CompactFlash_SysACE_MPD<0>  LOC= F5   | IOSTANDARD = LVCMOS33;
-NET SysACE_CompactFlash_SysACE_MPD<1>  LOC= U7   | IOSTANDARD = LVCMOS33;
-NET SysACE_CompactFlash_SysACE_MPD<2>  LOC= V6   | IOSTANDARD = LVCMOS33;
-NET SysACE_CompactFlash_SysACE_MPD<3>  LOC= U5   | IOSTANDARD = LVCMOS33;
-NET SysACE_CompactFlash_SysACE_MPD<4>  LOC= U6   | IOSTANDARD = LVCMOS33;
-NET SysACE_CompactFlash_SysACE_MPD<5>  LOC= T5   | IOSTANDARD = LVCMOS33;
-NET SysACE_CompactFlash_SysACE_MPD<6>  LOC= T7   | IOSTANDARD = LVCMOS33;
-NET SysACE_CompactFlash_SysACE_MPD<7>  LOC= R6   | IOSTANDARD = LVCMOS33;
-NET SysACE_CompactFlash_SysACE_MPD<8>  LOC= R7   | IOSTANDARD = LVCMOS33;
-NET SysACE_CompactFlash_SysACE_MPD<9>  LOC= R5   | IOSTANDARD = LVCMOS33;
-NET SysACE_CompactFlash_SysACE_MPD<10> LOC= P6   | IOSTANDARD = LVCMOS33;
-NET SysACE_CompactFlash_SysACE_MPD<11> LOC= P8   | IOSTANDARD = LVCMOS33;
-NET SysACE_CompactFlash_SysACE_MPD<12> LOC= N6   | IOSTANDARD = LVCMOS33;
-NET SysACE_CompactFlash_SysACE_MPD<13> LOC= M7   | IOSTANDARD = LVCMOS33;
-NET SysACE_CompactFlash_SysACE_MPD<14> LOC= K5   | IOSTANDARD = LVCMOS33;
-NET SysACE_CompactFlash_SysACE_MPD<15> LOC= L7   | IOSTANDARD = LVCMOS33;
-NET SysACE_CompactFlash_SysACE_CEN     LOC= G4   | IOSTANDARD = LVCMOS33;
-NET SysACE_CompactFlash_SysACE_OEN     LOC= Y6   | IOSTANDARD = LVCMOS33;
-NET SysACE_CompactFlash_SysACE_WEN     LOC= Y4   | IOSTANDARD = LVCMOS33;
-NET SysACE_CompactFlash_SysACE_MPIRQ   LOC= H4   | IOSTANDARD = LVCMOS33;
-
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