summaryrefslogtreecommitdiffstats
path: root/hw_godil/bsp/top.vhd
diff options
context:
space:
mode:
authorBert Lange <b.lange@fzd.de>2011-11-07 14:19:00 +0100
committerBert Lange <b.lange@fzd.de>2011-11-07 14:19:00 +0100
commit084229d151fc6e420ebde8069e059285cee14f07 (patch)
tree2dce60f4e358d281585d9e24ab541f43372149ff /hw_godil/bsp/top.vhd
parent9c59f6b33ff524906a62e7cb7d08878b53d35509 (diff)
downloadzpu-084229d151fc6e420ebde8069e059285cee14f07.zip
zpu-084229d151fc6e420ebde8069e059285cee14f07.tar.gz
initial commit
Diffstat (limited to 'hw_godil/bsp/top.vhd')
-rw-r--r--hw_godil/bsp/top.vhd42
1 files changed, 42 insertions, 0 deletions
diff --git a/hw_godil/bsp/top.vhd b/hw_godil/bsp/top.vhd
new file mode 100644
index 0000000..bd11e08
--- /dev/null
+++ b/hw_godil/bsp/top.vhd
@@ -0,0 +1,42 @@
+-- top module of
+-- GODIL
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity top is
+ port (
+ m49 : in std_logic; -- oscillator input
+ -- GPIO
+ sw1 : in std_logic; -- switch 1, high active
+ sw2 : in std_logic; -- switch 2, low active
+ -- TUSB3410
+ sin : inout std_logic; -- M0 configuration pin, TUSB3410 serial data input, LED3
+ sout : in std_logic; -- TUSB3410 serial data out
+ rts : in std_logic; -- TUSB3410 ready to send (LED5)
+ cts : inout std_logic; -- TUSB3410 clear to send (and LED6)
+ vs2 : inout std_logic; -- TUSB3410 I2C connection, LED8
+ tvs1 : inout std_logic; -- TUSB3410 I2C connector (and E2)
+ -- SPI flash
+ cso : inout std_logic; -- SPI memory chip select
+ tmosi : inout std_logic; -- SPI memory mosi (and E4)
+ tdin : inout std_logic; -- SPI memory data out (and E5)
+ tcclk : inout std_logic; -- SPI memory clock (and E6)
+ -- remaining IO pins
+ c13 : in std_logic; -- external input (pin 49)
+ d13 : in std_logic; -- external input (pin 50)
+ tvs0 : inout std_logic; -- E3
+ tm1 : inout std_logic; -- M1 configuration pin (and E7)
+ thsw : inout std_logic; -- HSWAP configuration pin (and E8)
+ -- I/O's for DIL / main connector
+ pin : inout std_logic_vector(48 downto 1)
+ );
+end entity top;
+
+
+architecture rtl of top is
+
+begin
+end architecture rtl;
OpenPOWER on IntegriCloud