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authorBert Lange <b.lange@hzdr.de>2011-10-13 12:33:03 +0200
committerBert Lange <b.lange@hzdr.de>2011-10-13 12:33:03 +0200
commitf5af2532d9d7de635e154ad416af42695f6d96ea (patch)
tree4b278661b8c349f43680190c124c4327fd0a6b13
parent3941564bb9cb1fa9faa9a3461074d06f2ef0dbe0 (diff)
downloadzpu-f5af2532d9d7de635e154ad416af42695f6d96ea.zip
zpu-f5af2532d9d7de635e154ad416af42695f6d96ea.tar.gz
add: performance measurement for Xilinx FPGAs
-rw-r--r--zpu/docs/zpu_arch.html97
1 files changed, 77 insertions, 20 deletions
diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html
index ac6b182..9506811 100644
--- a/zpu/docs/zpu_arch.html
+++ b/zpu/docs/zpu_arch.html
@@ -1068,55 +1068,112 @@ For now if you are starting a design, zpu4 or zealot are probably the safest. z
<a name="performance"/>
<h2>Performance Summary</h2>
-TODO fill in performance table.
+TODO fill in performance table for Altera and Lattice.
+<p>
+Tests are done with the <a href="#zealot">Zealot</a>
+ SoC-System and Xilinx ISE 12.2 with standard settings.
<p>
<TABLE WIDTH=604 BORDER=1 BORDERCOLOR="#000000" CELLPADDING=7 CELLSPACING=0 STYLE="page-break-after: avoid">
<TR VALIGN=TOP>
<TD WIDTH=85> <P><B>CORE/Config</B></P> </TD>
- <TD WIDTH=85> <P><B>Spartan3e</B></P> </TD>
- <TD WIDTH=85> <P><B>Cyclone3</B></P> </TD>
- <TD WIDTH=85> <P><B>DMIPS @ 50MHz</B></P> </TD>
+ <TD WIDTH=85> <P><B>Spartan-3</B></P> </TD>
+ <TD WIDTH=85> <P><B>Spartan-3E</B></P> </TD>
+ <TD WIDTH=85> <P><B>Spartan-6</B></P> </TD>
+ <TD WIDTH=85> <P><B>Virtex-5</B></P> </TD>
+ <TD WIDTH=85> <P><B>Cyclone-3</B></P> </TD>
+ <TD WIDTH=85> <P><B>DMIPS</B></P> </TD>
</TR>
<TR VALIGN=TOP>
-<TD WIDTH=85> <PRE>
+<TD WIDTH=85> <P>
zpu4 small
-maxAddrBit=?
-...
+maxAddrBit=16
+</P> </TD>
+<TD WIDTH=85> <PRE>
+<!-- Spartan-3 -->
+591 LUT
+389 REG
+ 0 MULT18x18
+ 16 BRAM
+ 90 fmax
</PRE> </TD>
<TD WIDTH=85> <PRE>
-? LUT
-? REG
-? MULT18x18
-? BRAM
-? fmax
+<!-- Spartan-3E -->
+626 LUT
+389 REG
+ 0 MULT18x18
+ 16 BRAM
+100 fmax
+</PRE> </TD>
+<TD WIDTH=85> <PRE>
+<!-- Spartan-6 -->
+639 LUT
+372 REG
+ 0 MULT18x18
+ 16 BRAM
+100 fmax
+</PRE> </TD>
+<TD WIDTH=85> <PRE>
+<!-- Virtex-5 -->
+560 LUT
+388 REG
+ 0 MULT18x18
+ 8 BRAM (RAMB36)
+140 fmax
</PRE> </TD>
<TD WIDTH=85> <PRE>
+<!-- Cyclone -->
? LUT
? REG
? MULT18x18
? M4K
? fmax
</PRE> </TD>
-<TD WIDTH=85> <P>???</P> </TD>
+<TD WIDTH=85> <!-- DMIPS --> <P>0.5</P> </TD>
</TR>
<TR VALIGN=TOP> <TD WIDTH=85> <P>zpu4 medium</P> </TD>
<TD WIDTH=85> <PRE>
-? LUT
-? REG
-? MULT18x18
-? BRAM
-? fmax
+<!-- Spartan-3 -->
+1760 LUT
+ 514 REG
+ 3 MULT18x18
+ 16 BRAM (RAMB16)
+ 75 fmax
+</PRE> </TD>
+<TD WIDTH=85> <PRE>
+<!-- Spartan-3E -->
+1754 LUT
+ 509 REG
+ 3 MULT18x18
+ 16 BRAM (RAMB16)
+ 75 fmax
+</PRE> </TD>
+<TD WIDTH=85> <PRE>
+<!-- Spartan-6 -->
+1162 LUT
+ 481 REG
+ 3 MULT (DSP48A1)
+ 16 BRAM (RAMB16)
+ 80 fmax
+</PRE> </TD>
+<TD WIDTH=85> <PRE>
+<!-- Virtex-5 -->
+1292 LUT
+ 490 REG
+ 3 MULT (DSP48E)
+ 8 BRAM (RAMB36)
+ 125 fmax
</PRE> </TD>
<TD WIDTH=85> <PRE>
+<!-- Cyclone -->
? LUT
? REG
? MULT18x18
? M4K
? fmax
</PRE> </TD>
-<TD WIDTH=85> <P>???</P> </TD>
+<TD WIDTH=85><!-- DMIPS --><P>2.6</P> </TD>
</TR>
</TABLE>
@@ -1128,7 +1185,7 @@ Found in <a href="../hdl/zpu4/core/zpu_core_small.vhd">zpu/zpu/hdl/zpu4/core/zpu
The small ZPU4 implements the minimum instruction set. It is optimized for size and simplicity
serving as a reference in both regards.
<p>
-It uses a BRAM (dual port RAM w/read/write to both ports) as data & code storage and
+It uses a RAM (dual port RAM w/read/write to both ports) as data & code storage and
is implemented as a simple state machine.
<p>
Essentially it has three states:
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