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authorBert Lange <b.lange@hzdr.de>2014-07-18 14:45:17 +0200
committerBert Lange <b.lange@hzdr.de>2014-07-18 14:45:17 +0200
commit02431f006669785afdf8e12ef1e91e06cb6318b4 (patch)
tree03203e489811676c59fff5a97d626538ce170981
parentf598b91ba530b07ee8230b20c7d9be8e5316b05d (diff)
downloadzpu-02431f006669785afdf8e12ef1e91e06cb6318b4.zip
zpu-02431f006669785afdf8e12ef1e91e06cb6318b4.tar.gz
change: to minimal zpu system
-rw-r--r--mig_test/rtl/Makefile30
-rw-r--r--mig_test/rtl/box.vhd432
-rw-r--r--mig_test/rtl/top.vhd183
-rw-r--r--mig_test/rtl/zpu_config.vhd61
-rw-r--r--mig_test/rtl_tb/top_tb.vhd26
-rw-r--r--mig_test/simulation/Makefile7
-rw-r--r--mig_test/simulation/wave.do2
-rw-r--r--mig_test/software/Makefile89
-rw-r--r--mig_test/software/ambainfo.c216
-rw-r--r--mig_test/software/ambainfo.h16
-rw-r--r--mig_test/software/include/common.h23
-rw-r--r--mig_test/software/include/lcd-routines.h167
-rw-r--r--mig_test/software/include/peripherie.h323
-rw-r--r--mig_test/software/include/timer.h49
-rw-r--r--mig_test/software/include/types.h43
-rw-r--r--mig_test/software/include/uart.h25
-rw-r--r--mig_test/software/include/vga.h18
-rw-r--r--mig_test/software/lib/crt0.S973
-rw-r--r--mig_test/software/lib/divmod.c50
-rw-r--r--mig_test/software/lib/premain.c26
-rw-r--r--mig_test/software/lib/udivmodsi4.c24
-rw-r--r--mig_test/software/libhal/Makefile31
-rw-r--r--mig_test/software/libhal/common.c203
-rw-r--r--mig_test/software/libhal/hw.c28
-rw-r--r--mig_test/software/libhal/include.mak16
-rw-r--r--mig_test/software/libhal/timer.c132
-rw-r--r--mig_test/software/libhal/uart.c56
-rw-r--r--mig_test/software/libhal/vga.c67
-rw-r--r--mig_test/software/main.c285
-rw-r--r--mig_test/software/monitor.c225
-rw-r--r--mig_test/software/monitor.h67
-rw-r--r--mig_test/software/monitor_functions.c134
-rw-r--r--mig_test/software/monitor_functions.h24
-rw-r--r--mig_test/software/schedule.c144
-rw-r--r--mig_test/software/schedule.h25
-rw-r--r--mig_test/synthesis/Makefile46
-rw-r--r--mig_test/synthesis/top.ucf24
-rw-r--r--mig_test/vhdl_files.txt61
38 files changed, 4249 insertions, 102 deletions
diff --git a/mig_test/rtl/Makefile b/mig_test/rtl/Makefile
new file mode 100644
index 0000000..17336cd
--- /dev/null
+++ b/mig_test/rtl/Makefile
@@ -0,0 +1,30 @@
+#
+# $HeadURL: https://svn.fzd.de/repo/concast/FWF_Projects/FWF_Internals/FPGA/hw_sp601/bsp_zpuahb/rtl/Makefile $
+# $Date$
+# $Author$
+# $Revision$
+#
+
+
+DATE = $(shell date +"%b %e %Y %X")
+DATELENGTH = $(shell expr length "$(DATE)")
+
+SVNREV = $(shell svnversion | awk '{printf "%-21s", $$0}')
+SVNLENGTH = $(shell expr length "$(SVNREV)")
+
+
+all: timestamp.vhd
+
+timestamp.vhd:
+ @echo "updating $@ ($(DATE); $(SVNREV))"
+ @rm -f $@
+ @echo "package timestamp is" >> $@
+ @echo "" >> $@
+ @echo " constant version_time_c : string( 1 to $(DATELENGTH)) := \"$(DATE)\";" >> $@
+ @echo " constant svnrevision_c : string( 1 to $(SVNLENGTH)) := \"$(SVNREV)\";" >> $@
+ @echo "" >> $@
+ @echo "end package timestamp;" >> $@
+
+
+clean:
+ rm timestamp.vhd
diff --git a/mig_test/rtl/box.vhd b/mig_test/rtl/box.vhd
new file mode 100644
index 0000000..229954a
--- /dev/null
+++ b/mig_test/rtl/box.vhd
@@ -0,0 +1,432 @@
+--------------------------------------------------------------------------------
+-- $Date$
+-- $Author$
+-- $Revision$
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_misc.or_reduce; -- by synopsis
+use ieee.numeric_std.all;
+
+library grlib;
+use grlib.amba.all;
+
+library gaisler;
+use gaisler.misc.all; -- types
+use gaisler.uart.all; -- types
+use gaisler.net.all; -- types
+use gaisler.memctrl.all; -- spimctrl types + spmictrl component
+
+-- components
+library gaisler;
+use gaisler.uart.apbuart;
+use gaisler.misc.ahbdpram;
+use gaisler.misc.gptimer;
+use gaisler.misc.grgpio;
+use gaisler.misc.apbvga;
+use gaisler.misc.ahbram;
+use gaisler.memoryctrl.mctrl; -- original in esa lib
+use gaisler.net.greth;
+
+library techmap;
+use techmap.gencomp.all; -- constants
+
+library zpu;
+use zpu.zpu_wrapper_package.all; -- types
+use zpu.zpu_config.all;
+use zpu.zpupkg.all;
+use zpu.zpu_wrapper_package.zpu_ahb;
+use zpu.zpu_wrapper_package.dualport_ram_ahb_wrapper; -- for medium zpu
+
+library hzdr;
+use hzdr.component_package.debug_con_apb;
+
+library work;
+use work.timestamp.all;
+
+
+
+entity box is
+ generic (
+ system_frequency : integer;
+ simulation_active : std_ulogic
+ );
+ port (
+ clk : in std_ulogic; -- clock
+ reset_n : in std_ulogic; -- synchronous reset (low active)
+ break : out std_ulogic; -- to stop simulation
+ --
+ uarti : in uart_in_type; -- UART
+ uarto : out uart_out_type;
+ --
+ gpioi : in gpio_in_type; -- GPIO (button, switches, LED, header pins)
+ gpioo : out gpio_out_type
+ );
+end entity box;
+
+
+
+
+architecture rtl of box is
+
+ signal box_reset : std_ulogic;
+ signal box_reset_n : std_ulogic;
+ --
+ signal debug_con_apb_i0_softreset : std_ulogic;
+ --
+ signal ahbctrl_i0_msti : ahb_mst_in_type;
+ signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
+ signal ahbctrl_i0_slvi : ahb_slv_in_type;
+ signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
+ signal apbctrl_i0_apbi : apb_slv_in_type;
+ signal apbo : apb_slv_out_vector := (others => apb_none);
+ --
+ signal gpti : gptimer_in_type;
+ signal gptimer_i0_gpto : gptimer_out_type;
+ --
+ signal grgpio_i0_gpioo : gpio_out_type;
+ --
+ signal box_mctrl_wpo : wprot_out_type := (wprothit => '0');
+ --
+ -- put these signals in entity (later)
+ signal ethi : eth_in_type; -- ethernet PHY
+ signal etho : eth_out_type;
+
+begin
+
+ ---------------------------------------------------------------------
+ -- reset
+
+ box_reset <= (not reset_n) or debug_con_apb_i0_softreset;
+ box_reset_n <= not box_reset;
+
+ ---------------------------------------------------------------------
+ -- AHB bus masters
+ ---------------------------------------------------------------------
+
+ ---------------------------------------------------------------------
+ -- zpu
+
+ zpu_ahb_i0: zpu_ahb
+ generic map (
+ hindex => 0, -- : integer := 0
+ zpu_small => false -- : boolean := true
+ )
+ port map (
+ clk => clk, -- : in std_ulogic;
+ reset => box_reset, -- : in std_ulogic;
+ ahbi => ahbctrl_i0_msti, -- : in ahb_mst_in_type;
+ ahbo => ahbmo(0), -- : out ahb_mst_out_type;
+ irq => or_reduce(ahbctrl_i0_msti.hirq), -- : in std_ulogic;
+ break => break -- : out std_ulogic
+ );
+ ---------------------------------------------------------------------
+
+
+ ---------------------------------------------------------------------
+ -- ethernet (ahb master + apb slave)
+
+ greth_i0: greth
+ generic map (
+ hindex => 1,
+ pindex => 5,
+ paddr => 5,
+ pirq => 5,
+ memtech => inferred,
+ mdcscaler => 20,
+ enable_mdio => 1,
+ fifosize => 32,
+ nsync => 1,
+ phyrstadr => 7 -- depends on used hardware
+ )
+ port map (
+ rst => reset_n,
+ clk => clk,
+ ahbmi => ahbctrl_i0_msti,
+ ahbmo => ahbmo(1),
+ apbi => apbctrl_i0_apbi,
+ apbo => apbo(5),
+ ethi => ethi,
+ etho => etho
+ );
+ ---------------------------------------------------------------------
+
+
+ ---------------------------------------------------------------------
+ -- AHB CONTROLLER
+
+ --ahbmo(0) <= (ahbm_none); -- zpu_ahb_i0
+ --ahbmo(1) <= (ahbm_none); -- greth_i0
+ ahbmo( 2) <= ahbm_none;
+ ahbmo( 3) <= ahbm_none;
+ ahbmo( 4) <= ahbm_none;
+ ahbmo( 5) <= ahbm_none;
+ ahbmo( 6) <= ahbm_none;
+ ahbmo( 7) <= ahbm_none;
+ ahbmo( 8) <= ahbm_none;
+ ahbmo( 9) <= ahbm_none;
+ ahbmo(10) <= ahbm_none;
+ ahbmo(11) <= ahbm_none;
+ ahbmo(12) <= ahbm_none;
+ ahbmo(13) <= ahbm_none;
+ ahbmo(14) <= ahbm_none;
+ ahbmo(15) <= ahbm_none;
+ --
+ --ahbso(0) <= (ahbs_none); -- apbctrl_i0
+ --ahbso(1) <= (ahbs_none); -- ahbram_i0
+ ahbso( 2) <= (ahbs_none);
+ --ahbso(3) <= (ahbs_none); -- dualport_ram_ahb_wrapper_i0
+ ahbso( 4) <= (ahbs_none); -- spimctrl
+ ahbso( 5) <= (ahbs_none);
+ ahbso( 6) <= (ahbs_none);
+ ahbso( 7) <= (ahbs_none);
+ ahbso( 8) <= (ahbs_none);
+ ahbso( 9) <= (ahbs_none);
+ ahbso(10) <= (ahbs_none);
+ ahbso(11) <= (ahbs_none);
+ ahbso(12) <= (ahbs_none);
+ ahbso(13) <= (ahbs_none);
+ ahbso(14) <= (ahbs_none);
+ ahbso(15) <= (ahbs_none);
+
+ ahbctrl_i0 : ahbctrl -- AHB arbiter/multiplexer
+ generic map (
+ defmast => 0, -- default master
+ timeout => 11,
+ disirq => 0, -- enable interrupt routing
+ enbusmon => 0, -- enable bus monitor
+ rrobin => 0,
+ assertwarn => 1, -- enable assertions for warnings
+ asserterr => 1 -- enable assertions for errors
+ )
+ port map (
+ rst => box_reset_n, -- : in std_ulogic;
+ clk => clk, -- : in std_ulogic;
+ msti => ahbctrl_i0_msti, -- : out ahb_mst_in_type;
+ msto => ahbmo, -- : in ahb_mst_out_vector;
+ slvi => ahbctrl_i0_slvi, -- : out ahb_slv_in_type;
+ slvo => ahbso, -- : in ahb_slv_out_vector;
+ testen => '0',
+ testrst => '1',
+ scanen => '0',
+ testoen => '1'
+ );
+ ----------------------------------------------------------------------
+
+
+ ---------------------------------------------------------------------
+ -- AHB bus slaves
+ ---------------------------------------------------------------------
+
+
+ ---------------------------------------------------------------------
+ -- AHB RAM (internal 4k BRAM)
+
+ ahbram_i0 : ahbram
+ generic map (
+ hindex => 1,
+ haddr => 16#a00#,
+ hmask => 16#FFF#,
+ tech => inferred,
+ kbytes => 4
+ )
+ port map (
+ rst => box_reset_n,
+ clk => clk,
+ ahbsi => ahbctrl_i0_slvi,
+ ahbso => ahbso(1)
+ );
+ ----------------------------------------------------------------------
+
+
+ ---------------------------------------------------------------------
+ -- AHB ZPU memory (instruction + data memory)
+
+ dualport_ram_ahb_wrapper_i0 : dualport_ram_ahb_wrapper
+ generic map (
+ hindex => 3,
+ haddr => 16#000#
+ )
+ port map (
+ clk => clk,
+ reset => box_reset,
+ ahbsi => ahbctrl_i0_slvi,
+ ahbso => ahbso(3)
+ );
+ ----------------------------------------------------------------------
+
+
+-- ---------------------------------------------------------------------
+-- -- AHB SPI memory controller
+-- -- for SPI X4 (Winbond W25Q64VSFIG) 64-Mbit flash memory
+-- spimctrl_i0 : spimctrl
+-- generic map (
+-- hindex => 4, -- : integer := 0; -- AHB slave index
+-- faddr => 16#E00#, -- : integer := 16#000#; -- Flash map base address
+-- fmask => 16#FF8#, -- : integer := 16#fff#; -- Flash area mask
+-- ioaddr => 16#002#, -- : integer := 16#000#; -- I/O base address
+-- iomask => 16#fff#, -- : integer := 16#fff#; -- I/O mask
+-- readcmd => 16#3b#, -- : integer range 0 to 255 := 16#0B#; -- Mem. dev. READ command
+-- dummybyte => 1, -- : integer range 0 to 1 := 1; -- Dummy byte after cmd
+-- dualoutput => 1 -- : integer range 0 to 1 := 0; -- Enable dual output
+-- )
+-- port map (
+-- rstn => box_reset_n, -- : in std_ulogic;
+-- clk => clk, -- : in std_ulogic;
+-- ahbsi => ahbctrl_i0_slvi, -- : in ahb_slv_in_type;
+-- ahbso => ahbso(4), -- : out ahb_slv_out_type;
+-- spii => spmi, -- : in spimctrl_in_type;
+-- spio => spmo -- : out spimctrl_out_type
+-- );
+-- ---------------------------------------------------------------------
+
+
+
+
+ ---------------------------------------------------------------------
+ -- AHB/APB bridge
+
+ --apbo( 0) <= (apb_none); -- debug_con_apb_i0
+ --apbo( 1) <= (apb_none); -- apbuart_i0
+ --apbo( 2) <= (apb_none); -- gptimer_i0
+ apbo( 3) <= (apb_none);
+ --apbo( 4) <= (apb_none); -- grgpio_i0
+ --apbo( 5) <= (apb_none); -- greth_i0
+ apbo( 6) <= (apb_none); -- no apbvga_i0
+ apbo( 7) <= (apb_none); -- no i2cmst_i0
+ apbo( 8) <= (apb_none);
+ apbo( 9) <= (apb_none);
+ apbo(10) <= (apb_none);
+ apbo(11) <= (apb_none);
+ apbo(12) <= (apb_none);
+ apbo(13) <= (apb_none);
+ apbo(14) <= (apb_none);
+ apbo(15) <= (apb_none);
+
+ apbctrl_i0: apbctrl
+ generic map (
+ hindex => 0, -- : integer := 0;
+ haddr => 16#800#, -- : integer := 0;
+ nslaves => 16, -- : integer range 1 to NAPBSLV := NAPBSLV;
+ asserterr => 1,
+ assertwarn => 1
+ )
+ port map (
+ rst => box_reset_n, -- : in std_ulogic;
+ clk => clk, -- : in std_ulogic;
+ ahbi => ahbctrl_i0_slvi, -- : in ahb_slv_in_type;
+ ahbo => ahbso(0), -- : out ahb_slv_out_type;
+ apbi => apbctrl_i0_apbi, -- : out apb_slv_in_type;
+ apbo => apbo -- : in apb_slv_out_vector
+ );
+ ----------------------------------------------------------------------
+
+
+ ---------------------------------------------------------------------
+ -- APB bus slaves
+ ---------------------------------------------------------------------
+
+
+ ---------------------------------------------------------------------
+ -- debug console (for fast simulation output)
+ debug_con_apb_i0: debug_con_apb
+ generic map (
+ pindex => 0, -- : integer := 0;
+ paddr => 0, -- : integer := 0;
+ -- values taken from timestamp.vhd:
+ svnrevision => svnrevision_c, -- : string( 1 to 21) := "unknown SVN revision ";
+ version_time => version_time_c, -- : string( 1 to 21) := "undefined version "
+ system_frequency => system_frequency -- : integer
+ )
+ port map (
+ rst => box_reset_n, -- : in std_ulogic;
+ clk => clk, -- : in std_ulogic;
+ apbi => apbctrl_i0_apbi, -- : in apb_slv_in_type;
+ apbo => apbo(0), -- : out apb_slv_out_type;
+ softreset => debug_con_apb_i0_softreset -- : out std_ulogic
+ );
+ ---------------------------------------------------------------------
+
+
+ ---------------------------------------------------------------------
+ -- uart
+ apbuart_i0: apbuart
+ generic map (
+ pindex => 1,
+ paddr => 1,
+ console => 1, -- fast simulation output
+ parity => 0, -- no parity
+ flow => 1, -- hardware handshake
+ fifosize => 16
+ )
+ port map (
+ rst => box_reset_n, -- : in std_ulogic;
+ clk => clk, -- : in std_ulogic;
+ apbi => apbctrl_i0_apbi, -- : in apb_slv_in_type;
+ apbo => apbo(1), -- : out apb_slv_out_type;
+ uarti => uarti, -- : in uart_in_type;
+ uarto => uarto -- : out uart_out_type);
+ );
+ ---------------------------------------------------------------------
+
+
+ ---------------------------------------------------------------------
+ -- GP timer (grip.pdf p. 279)
+
+ gpti.extclk <= '0'; -- alternativ timer clock
+ gpti.dhalt <= '0'; -- debug halt
+ gpti.wdogen <= '0'; -- watchdog enable
+
+ gptimer_i0: gptimer
+ generic map (
+ pindex => 2,
+ paddr => 2,
+ pirq => 3,
+ sepirq => 0, -- use separate interupts for each timer
+ sbits => 8, -- prescaler bits
+ ntimers => 2, -- number of timers
+ nbits => 24 -- timer bits
+ )
+ port map (
+ rst => box_reset_n,
+ clk => clk,
+ apbi => apbctrl_i0_apbi,
+ apbo => apbo(2),
+ gpti => gpti,
+ gpto => gptimer_i0_gpto
+ );
+ ---------------------------------------------------------------------
+
+
+ ---------------------------------------------------------------------
+ -- GPIO
+ grgpio_i0: grgpio
+ generic map (
+ pindex => 4,
+ paddr => 4,
+-- imask => 16#00000FF0#, -- interrupt mask (+ enable per software)
+ syncrst => 1, -- only synchronous reset
+ nbits => 32 -- number of port bits
+ )
+ port map (
+ rst => box_reset_n,
+ clk => clk,
+ apbi => apbctrl_i0_apbi,
+ apbo => apbo(4),
+ gpioi => gpioi,
+ gpioo => grgpio_i0_gpioo
+ );
+ gpioo <= grgpio_i0_gpioo;
+ -- gpio.dout gpio.din
+ ---------------------------------------------------------------------
+ -- 3 - 0 LED unused
+ -- 4 MAC_DATA MAC_DATA
+ -- 5 user_led unused
+ -- 15 - 8 unused unused
+ -- 30 - 16 unused unused
+ -- 31 unused simulation_active
+ ---------------------------------------------------------------------
+
+
+end architecture rtl;
diff --git a/mig_test/rtl/top.vhd b/mig_test/rtl/top.vhd
index 5775bd7..2d02186 100644
--- a/mig_test/rtl/top.vhd
+++ b/mig_test/rtl/top.vhd
@@ -11,17 +11,14 @@
--
--------------------------------------------------------------------------------
--- $Date: Thu Dec 22 10:52:48 2011 +0100 $
--- $Author: Bert Lange <b.lange@hzdr.de> $
--- $Revision: c241a5e741dd3f0c14967956eb305177252c6f25 $
+-- $Date$
+-- $Author$
+-- $Revision$
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-library unisim;
---use unisim.vcomponents.;
-
entity top is
port (
-- pragma translate_off
@@ -29,7 +26,7 @@ entity top is
-- pragma translate_on
-- system stuff
CLK : in std_logic; -- 125 MHz
- RESET_N : in std_logic;
+ --RESET_N : in std_logic;
POWER_FAIL_N : in std_logic;
WATCHDOG : out std_logic;
REPROG_N : out std_logic;
@@ -48,12 +45,12 @@ entity top is
MCB1_DRAM_DQ : inout std_logic_vector(15 downto 0);
MCB1_DRAM_LDM : out std_logic;
MCB1_DRAM_UDM : out std_logic;
- MCB1_DRAM_LDQS_N : inout std_logic;
- MCB1_DRAM_LDQS_P : inout std_logic;
- MCB1_DRAM_UDQS_N : inout std_logic;
- MCB1_DRAM_UDQS_P : inout std_logic;
+ MCB1_DRAM_DQS_N : inout std_logic_vector( 1 downto 0);
+ MCB1_DRAM_DQS_P : inout std_logic_vector( 1 downto 0);
MCB1_DRAM_ODT : out std_logic;
MCB1_DRAM_RESET_B : out std_logic;
+ MCB1_RZQ : inout std_logic;
+ MCB1_ZIO : inout std_logic;
--
MCB3_DRAM_A : out std_logic_vector(14 downto 0);
MCB3_DRAM_BA : out std_logic_vector(2 downto 0);
@@ -66,12 +63,12 @@ entity top is
MCB3_DRAM_DQ : inout std_logic_vector(15 downto 0);
MCB3_DRAM_LDM : out std_logic;
MCB3_DRAM_UDM : out std_logic;
- MCB3_DRAM_LDQS_N : inout std_logic;
- MCB3_DRAM_LDQS_P : inout std_logic;
- MCB3_DRAM_UDQS_N : inout std_logic;
- MCB3_DRAM_UDQS_P : inout std_logic;
+ MCB3_DRAM_DQS_N : inout std_logic_vector( 1 downto 0);
+ MCB3_DRAM_DQS_P : inout std_logic_vector( 1 downto 0);
MCB3_DRAM_ODT : out std_logic;
MCB3_DRAM_RESET_B : out std_logic;
+ MCB3_RZQ : inout std_logic;
+ MCB3_ZIO : inout std_logic;
--
-- Ethernet PHY
-- phy address = 0b00111
@@ -185,7 +182,7 @@ entity top is
B2B_B1_L21_P : inout std_logic;
B2B_B1_L61_P : inout std_logic;
B2B_B1_L61_N : inout std_logic;
- --B2B_B0_L1 : inout std_logic; -- used as reset_n
+ B2B_B0_L1 : inout std_logic; -- used as reset_n
B2B_B0_L2_P : inout std_logic;
B2B_B0_L2_N : inout std_logic;
B2B_B0_L4_N : inout std_logic;
@@ -227,6 +224,19 @@ entity top is
);
end entity top;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library gaisler;
+use gaisler.misc.all; -- types
+use gaisler.uart.all; -- types
+use gaisler.net.all; -- types
+use gaisler.memctrl.all; -- spimctrl types
+
+
architecture Behavioral of top is
function simulation_active return std_ulogic is
@@ -239,30 +249,35 @@ architecture Behavioral of top is
return result;
end function simulation_active;
- function divider_init return integer is
- variable result : integer;
- begin
- -- synthessis value:
- result := 62500000;
-
- -- pragma translate_off
- -- simulation value
- result := 5;
- -- pragma translate_on
- return result;
- end function divider_init;
alias CARRIER_LED0 : std_logic is B2B_B3_L59_N;
alias CARRIER_LED1 : std_logic is B2B_B3_L59_P;
alias CARRIER_LED2 : std_logic is B2B_B3_L9_P;
alias CARRIER_LED3 : std_logic is B2B_B3_L9_N;
+ --
+ alias UART_RX : std_logic is B2B_B2_L9_N;
+ alias UART_TX : std_logic is B2B_B2_L6_P;
+
+
+ constant system_frequency_c : natural := 125_000_000;
+
+ -- system signals
+ signal clk_box : std_ulogic;
+ signal clk_ready : std_ulogic := '1';
+ --
+ signal reset_shreg : std_ulogic_vector(3 downto 0) := (others => '1');
+ signal reset : std_ulogic := '1';
+ signal reset_n : std_ulogic := '0';
+ --
+ -- io signals
+ signal box_i0_break : std_ulogic;
+ signal gpioi : gpio_in_type;
+ signal uarti : uart_in_type;
+ --
+ signal box_i0_gpioo : gpio_out_type;
+ signal box_i0_uarto : uart_out_type;
- constant divider : integer := divider_init;
- --
- signal counter : integer := 0;
- signal led_i : std_logic_vector( 4 downto 0) := ( 0 => '0', others => '1');
-
begin
@@ -289,10 +304,8 @@ begin
MCB1_DRAM_LDM <= '0';
MCB1_DRAM_UDM <= '0';
MCB1_DRAM_ODT <= '1';
- MCB1_DRAM_UDQS_N <= 'Z';
- MCB1_DRAM_UDQS_P <= 'Z';
- MCB1_DRAM_LDQS_N <= 'Z';
- MCB1_DRAM_LDQS_P <= 'Z';
+ MCB1_DRAM_DQS_N <= (others => 'Z');
+ MCB1_DRAM_DQS_P <= (others => 'Z');
MCB1_DRAM_DQ <= (others => 'Z');
MCB3_DRAM_RESET_B <= '0';
@@ -307,10 +320,8 @@ begin
MCB3_DRAM_LDM <= '0';
MCB3_DRAM_UDM <= '0';
MCB3_DRAM_ODT <= '1';
- MCB3_DRAM_UDQS_N <= 'Z';
- MCB3_DRAM_UDQS_P <= 'Z';
- MCB3_DRAM_LDQS_N <= 'Z';
- MCB3_DRAM_LDQS_P <= 'Z';
+ MCB3_DRAM_DQS_N <= (others => 'Z');
+ MCB3_DRAM_DQS_P <= (others => 'Z');
MCB3_DRAM_DQ <= (others => 'Z');
SPI_FLASH_CSO_B <= '1';
@@ -318,7 +329,7 @@ begin
SPI_FLASH_IO <= (others => 'Z');
WATCHDOG <= 'Z'; -- disable watchdog
- REPROG_N <= '1';
+ --REPROG_N <= '1';
MAC_DATA <= 'Z';
@@ -435,34 +446,76 @@ begin
B2B_B1_L59 <= 'Z';
+ ------------------------------------------------------------
+ -- (internal) reset generation
+ -- with wait for locked DCM
+ reset_generator_p : process( clk_box, clk_ready)
+ begin
+ if clk_ready = '0' then
+ reset_shreg <= (others => '1');
+ elsif rising_edge( clk_box) then
+ reset_shreg <= reset_shreg(reset_shreg'left-1 downto 0) & '0';
+ end if;
+ end process;
+ reset <= reset_shreg(reset_shreg'left);
+ reset_n <= not reset;
+
+
+ ------------------------------------------------------------
+ -- clock selection
+ clk_box <= CLK; -- 125 MHz
+
-- used IOs
- user_led_n <= led_i( 0);
- CARRIER_LED0 <= led_i( 1);
- CARRIER_LED1 <= led_i( 2);
- CARRIER_LED2 <= led_i( 3);
- CARRIER_LED3 <= led_i( 4);
-
- process
- begin
- wait until rising_edge( clk);
- if counter = divider-1 then
- counter <= 0;
- led_i <= led_i( led_i'high - 1 downto 0) & led_i( led_i'high);
- else
- counter <= counter + 1;
- end if;
- end process;
+ -- LEDs
+ gpioi.sig_in <= ( others => '0');
+ gpioi.sig_en <= ( others => '0');
+ gpioi.din <= ( 4 => MAC_DATA,
+ 31 => simulation_active,
+ others => '0');
+ CARRIER_LED0 <= not box_i0_gpioo.dout( 0);
+ CARRIER_LED1 <= not box_i0_gpioo.dout( 1);
+ CARRIER_LED2 <= not box_i0_gpioo.dout( 2);
+ CARRIER_LED3 <= not box_i0_gpioo.dout( 3);
+ user_led_n <= not box_i0_gpioo.dout( 5);
+ MAC_DATA <= box_i0_gpioo.dout(4) when box_i0_gpioo.oen(4) = '0' else 'Z';
+
+ -- uart i/o
+ uarti.rxd <= UART_RX;
+ uarti.ctsn <= '0';
+ uarti.extclk <= '0';
+ --
+ UART_TX <= box_i0_uarto.txd;
+
+
+ ------------------------------------------------------------
+ -- box system
+ box_i0: entity work.box
+ generic map (
+ simulation_active => simulation_active, --: std_ulogic;
+ system_frequency => system_frequency_c --: integer
+ )
+ port map (
+ clk => clk_box, --: in std_ulogic;
+ reset_n => reset_n, --: in std_ulogic;
+ break => box_i0_break, --: out std_ulogic;
+ --
+ uarti => uarti, --: in uart_in_type;
+ uarto => box_i0_uarto, --: out uart_out_type;
+ --
+ gpioi => gpioi, --: in gpio_in_type;
+ gpioo => box_i0_gpioo --: out gpio_out_type;
+ );
+ ------------------------------------------------------------
+ -- break handling
+ --
-- pragma translate_off
- process
- begin
- simulation_break <= '0';
- wait for 1 us;
- simulation_break <= '1';
- wait;
- end process;
+ simulation_break <= box_i0_break;
-- pragma translate_on
+ -- reboot FPGA for real
+ REPROG_N <= not box_i0_break;
+
end architecture Behavioral;
diff --git a/mig_test/rtl/zpu_config.vhd b/mig_test/rtl/zpu_config.vhd
new file mode 100644
index 0000000..ae410e2
--- /dev/null
+++ b/mig_test/rtl/zpu_config.vhd
@@ -0,0 +1,61 @@
+-- ZPU
+--
+-- Copyright 2004-2008 oharboe - Űyvind Harboe - oyvind.harboe@zylin.com
+--
+-- The FreeBSD license
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+--
+-- 1. Redistributions of source code must retain the above copyright
+-- notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+-- copyright notice, this list of conditions and the following
+-- disclaimer in the documentation and/or other materials
+-- provided with the distribution.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+-- The views and conclusions contained in the software and documentation
+-- are those of the authors and should not be interpreted as representing
+-- official policies, either expressed or implied, of the ZPU Project.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package zpu_config is
+ -- generate trace output
+ constant Generate_Trace : boolean := false;
+ constant wordPower : integer := 5;
+ -- during simulation, set this to '0' to get matching trace.txt
+ constant DontCareValue : std_logic := '0';
+ -- Clock frequency in MHz.
+ constant ZPU_Frequency : std_ulogic_vector(7 downto 0) := std_ulogic_vector(to_unsigned(50, 8));
+ -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
+ constant maxAddrBitIncIO : integer := 31; -- BLa: 31 -- was: 27
+ --constant maxAddrBitBRAM : integer := 13; -- 16k
+ constant maxAddrBitBRAM : integer := 14; -- 32k
+ --constant maxAddrBitBRAM : integer := 16;
+
+ --
+ -- derived constants
+ constant bram_words : integer := 2 ** (maxAddrBitBRAM - 1);
+
+ -- start byte address of stack.
+ -- point to top of RAM - 2*words
+ constant spStart : unsigned(maxAddrBitIncIO downto 0) :=
+ to_unsigned((4*bram_words)-8, maxAddrBitIncIO+1);
+end zpu_config;
diff --git a/mig_test/rtl_tb/top_tb.vhd b/mig_test/rtl_tb/top_tb.vhd
index 2108ff3..a8c3ead 100644
--- a/mig_test/rtl_tb/top_tb.vhd
+++ b/mig_test/rtl_tb/top_tb.vhd
@@ -33,10 +33,8 @@ architecture testbench of top_tb is
signal tb_mcb1_dram_dq : std_logic_vector(15 downto 0);
signal tb_mcb1_dram_ldm : std_logic;
signal tb_mcb1_dram_udm : std_logic;
- signal tb_mcb1_dram_ldqs_n : std_logic;
- signal tb_mcb1_dram_ldqs_p : std_logic;
- signal tb_mcb1_dram_udqs_n : std_logic;
- signal tb_mcb1_dram_udqs_p : std_logic;
+ signal tb_mcb1_dram_dqs_n : std_logic_vector( 1 downto 0);
+ signal tb_mcb1_dram_dqs_p : std_logic_vector( 1 downto 0);
signal tb_mcb1_dram_odt : std_logic;
signal tb_mcb1_dram_reset_b : std_logic;
--
@@ -51,10 +49,8 @@ architecture testbench of top_tb is
signal tb_mcb3_dram_dq : std_logic_vector(15 downto 0);
signal tb_mcb3_dram_ldm : std_logic;
signal tb_mcb3_dram_udm : std_logic;
- signal tb_mcb3_dram_ldqs_n : std_logic;
- signal tb_mcb3_dram_ldqs_p : std_logic;
- signal tb_mcb3_dram_udqs_n : std_logic;
- signal tb_mcb3_dram_udqs_p : std_logic;
+ signal tb_mcb3_dram_dqs_n : std_logic_vector( 1 downto 0);
+ signal tb_mcb3_dram_dqs_p : std_logic_vector( 1 downto 0);
signal tb_mcb3_dram_odt : std_logic;
signal tb_mcb3_dram_reset_b : std_logic;
--
@@ -208,7 +204,7 @@ begin
-- pragma translate_on
-- system stuff
CLK => tb_clk, -- : in std_logic; -- 125 MHz
- RESET_N => tb_reset_n, -- : in std_logic;
+ --RESET_N => tb_reset_n, -- : in std_logic;
POWER_FAIL_N => tb_power_fail_n, -- : in std_logic;
WATCHDOG => tb_watchdog, -- : out std_logic;
REPROG_N => tb_reprog_n, -- : out std_logic;
@@ -227,10 +223,8 @@ begin
MCB1_DRAM_DQ => tb_mcb1_dram_dq, -- : inout std_logic_vector(15 downto 0);
MCB1_DRAM_LDM => tb_mcb1_dram_ldm, -- : out std_logic;
MCB1_DRAM_UDM => tb_mcb1_dram_udm, -- : out std_logic;
- MCB1_DRAM_LDQS_N => tb_mcb1_dram_ldqs_n, -- : inout std_logic;
- MCB1_DRAM_LDQS_P => tb_mcb1_dram_ldqs_p, -- : inout std_logic;
- MCB1_DRAM_UDQS_N => tb_mcb1_dram_udqs_n, -- : inout std_logic;
- MCB1_DRAM_UDQS_P => tb_mcb1_dram_udqs_p, -- : inout std_logic;
+ MCB1_DRAM_DQS_N => tb_mcb1_dram_dqs_n, -- : inout std_logic_vector;
+ MCB1_DRAM_DQS_P => tb_mcb1_dram_dqs_p, -- : inout std_logic_vector;
MCB1_DRAM_ODT => tb_mcb1_dram_odt, -- : out std_logic;
MCB1_DRAM_RESET_B => tb_mcb1_dram_reset_b, -- : out std_logic;
-- --
@@ -245,10 +239,8 @@ begin
MCB3_DRAM_DQ => tb_mcb3_dram_dq, -- : inout std_logic_vector(15 downto 0);
MCB3_DRAM_LDM => tb_mcb3_dram_ldm, -- : out std_logic;
MCB3_DRAM_UDM => tb_mcb3_dram_udm, -- : out std_logic;
- MCB3_DRAM_LDQS_N => tb_mcb3_dram_ldqs_n, -- : inout std_logic;
- MCB3_DRAM_LDQS_P => tb_mcb3_dram_ldqs_p, -- : inout std_logic;
- MCB3_DRAM_UDQS_N => tb_mcb3_dram_udqs_n, -- : inout std_logic;
- MCB3_DRAM_UDQS_P => tb_mcb3_dram_udqs_p, -- : inout std_logic;
+ MCB3_DRAM_DQS_N => tb_mcb3_dram_dqs_n, -- : inout std_logic_vector;
+ MCB3_DRAM_DQS_P => tb_mcb3_dram_dqs_p, -- : inout std_logic_vector;
MCB3_DRAM_ODT => tb_mcb3_dram_odt, -- : out std_logic;
MCB3_DRAM_RESET_B => tb_mcb3_dram_reset_b, -- : out std_logic;
--
diff --git a/mig_test/simulation/Makefile b/mig_test/simulation/Makefile
index a5df795..b1a0b89 100644
--- a/mig_test/simulation/Makefile
+++ b/mig_test/simulation/Makefile
@@ -1,8 +1,8 @@
#
# $HeadURL: https://svn.fzd.de/repo/concast/FWF_Projects/FWKE/beam_position_monitor/trunk/hardware/board_prototyp1/simulation/Makefile $
-# $Date: 2013-08-26 14:18:45 +0200 (Mo, 26. Aug 2013) $
-# $Author: lange $
-# $Revision: 2646 $
+# $Date$
+# $Author$
+# $Revision$
#
library = work
@@ -48,6 +48,7 @@ simulate:
clean:
@# modelsim stuff
rm -f transcript.log
+ rm -f bus_trace.txt
rm -f *.wlf
rm -f wlf*
@# compile stuff
diff --git a/mig_test/simulation/wave.do b/mig_test/simulation/wave.do
index cc26df8..607e5f3 100644
--- a/mig_test/simulation/wave.do
+++ b/mig_test/simulation/wave.do
@@ -24,4 +24,4 @@ configure wave -griddelta 32
configure wave -timeline 1
configure wave -timelineunits ns
update
-WaveRestoreZoom {0 ps} {1054200 ps}
+WaveRestoreZoom {0 ps} {901530 ns}
diff --git a/mig_test/software/Makefile b/mig_test/software/Makefile
new file mode 100644
index 0000000..1246803
--- /dev/null
+++ b/mig_test/software/Makefile
@@ -0,0 +1,89 @@
+#
+# $HeadURL: https://svn.fzd.de/repo/concast/FWF_Projects/FWKE/hw_sp605/bsp_zpuahb/software/Makefile $
+# $Date$
+# $Author$
+# $Revision$
+#
+
+COMPILER_OPTIONS=-ffunction-sections -fdata-sections -Iinclude
+OBJCOPY_OPTIONS=--strip-debug --discard-locals
+
+ZPU_SUPPORT_DIR=../../zpu/support
+ZPU_ROM_GEN=$(ZPU_SUPPORT_DIR)/zpuromgen
+AHB_ROM_GEN=../../gaisler/support/ahbrom
+
+
+SVNPATH = ..
+SVNREV = $(shell svnversion -n $(SVNPATH))
+
+all: software
+
+help:
+ @echo "software - build main software"
+ @echo
+ @echo "clean - clean up"
+
+
+startup = lib/crt0.S
+objs = lib/crt0.o
+lib_src = lib/premain.c lib/divmod.c lib/udivmodsi4.c
+#ldflags = -nostartfiles -nostdlib -nodefaultlibs $(objs) -Wl,--relax -Wl,--gc-sections -Wl,-lhal -Wl,-Llibhal
+ldflags = -nostartfiles $(objs) -Wl,--relax,--gc-sections,-lhal,-Llibhal
+
+
+zpu_rom_vhdl = ../rtl/dualport_ram.vhd
+ahb_rom_vhdl = ../rtl/ahbrom.vhd
+c_files += main.c
+c_files += timestamp.c
+c_files += monitor.c
+c_files += schedule.c
+c_files += ambainfo.c
+c_files += monitor_functions.c
+c_files += $(lib_src)
+h_files = *.h include/peripherie.h
+
+
+software: $(zpu_rom_vhdl) $(ahb_rom_vhdl)
+
+
+main.bin: $(c_files) $(h_files) $(objs)
+ make --directory libhal
+ @# normal compile command (emulate instructions)
+ zpu-elf-gcc $(COMPILER_OPTIONS) -O3 -phi $(c_files) $(ldflags) -o main.elf
+
+ zpu-elf-size main.elf
+ print_mem_zpu.sh main.elf
+ zpu-elf-objdump -D -S main.elf > main.lst
+ zpu-elf-objcopy $(OBJCOPY_OPTIONS) -O binary main.elf main.bin
+
+$(zpu_rom_vhdl): main.bin $(ZPU_ROM_GEN)
+ # concat parts
+ cat > $(zpu_rom_vhdl) $(ZPU_SUPPORT_DIR)/dualport_ram.vhd_header
+ $(ZPU_ROM_GEN) main.bin >> $(zpu_rom_vhdl)
+ cat >> $(zpu_rom_vhdl) $(ZPU_SUPPORT_DIR)/dualport_ram.vhd_footer
+
+$(ahb_rom_vhdl): main.bin $(AHB_ROM_GEN)
+ $(AHB_ROM_GEN) main.bin $(ahb_rom_vhdl)
+
+
+$(startup:.S=.o): $(startup)
+ zpu-elf-gcc -c $< -o $@
+
+clean:
+ rm -f *.bin
+ rm -f *.elf
+ rm -f *.lst
+ rm -f *.o
+ rm -f lib/*.o
+
+
+timestamp: timestamp.c
+timestamp.c:
+ @echo "updating $@ ($(SVNREV))"
+ @rm -f $@
+ @echo "const char* sw_svn_revision = \"$(SVNREV)\"; " >> $@
+
+
+# disable implicit rule for c files
+.SUFFIXES:
+%.c: %.w %.ch
diff --git a/mig_test/software/ambainfo.c b/mig_test/software/ambainfo.c
new file mode 100644
index 0000000..83813b0
--- /dev/null
+++ b/mig_test/software/ambainfo.c
@@ -0,0 +1,216 @@
+/*
+ * $HeadURL: https://svn.fzd.de/repo/concast/FWF_Projects/FWKE/hw_sp605/bsp_zpuahb/software/ambainfo.c $
+ * $Date$
+ * $Author$
+ * $Revision$
+ */
+
+#include <types.h>
+
+
+/*
+ print some spaces to make output alignment columnwise
+*/
+void fill(uint8_t length, uint8_t fillupto)
+{
+ while (length < fillupto)
+ {
+ putchar(' ');
+ length++;
+ }
+}
+
+
+
+////////////////////////////////////////////////////////////
+// print vendor
+void print_vendor_device( uint8_t vendor, uint8_t device)
+{
+ switch( vendor)
+ {
+ case 0x01: putstr("gaisler ");
+ switch( device)
+ {
+ case 0x06: putstr("AHB/APB Bridge"); break;
+ case 0x0c: putstr("Generic UART"); break;
+ case 0x0f: putstr("Dual-port AHB SRAM module"); break;
+ case 0x11: putstr("Modular Timer Unit"); break;
+ case 0x1a: putstr("General Purpose I/O port"); break;
+ case 0x1d: putstr("GR 10/100 Mbit Ethernet MAC"); break;
+ case 0x28: putstr("AMBA Wrapper for OC I2C-master");break;
+ case 0x45: putstr("SPI Memory Controller"); break;
+ case 0x61: putstr("VGA controller"); break;
+ case 0x87: putstr("General Purpose Register"); break;
+ default : putstr("unknown device"); break;
+ }
+ break;
+ case 0x04: putstr("ESA ");
+ switch( device)
+ {
+ case 0x0f: putstr("Leon2 Memory Controller"); break;
+ default : putstr("unknown device"); break;
+ }
+ break;
+ case 0x55: putstr("HZDR ");
+ switch( device)
+ {
+ case 0x01: putstr("ZPU AHB Wrapper"); break;
+ case 0x02: putstr("ZPU Memory wrapper"); break;
+ case 0x03: putstr("DCM phase shift control"); break;
+ case 0x04: putstr("debug console"); break;
+ case 0x05: putstr("trigger generator"); break;
+ case 0x06: putstr("beam position monitor"); break;
+ case 0x07: putstr("debug buffer control"); break;
+ case 0x08: putstr("EA-DOGS display driver"); break;
+ case 0x09: putstr("debug tracer memory"); break;
+ case 0x0a: putstr("differential current monitor"); break;
+ default : putstr("unknown device"); break;
+ }
+ break;
+ default : putstr("vendor? "); break;
+ }
+}
+
+////////////////////////////////////////////////////////////
+// apb info
+void apb_info( uint32_t* addr, uint8_t verbose)
+{
+ // identification register
+ uint16_t vendor;
+ uint16_t device;
+ uint16_t version;
+ uint16_t irq;
+ uint32_t dev_addr;
+
+ uint32_t* config;
+ uint32_t* idreg_addr;
+ uint32_t idreg_word;
+ uint32_t* bar_addr;
+ uint32_t bar_word;
+
+ uint32_t apb_addr;
+ uint32_t apb_unit;
+
+ config = addr;
+ apb_addr = (*config & 0xfff00000); // get apb address
+
+ // we can have up to 512 slaves, but we scan only 16
+ // to avoid double scans at the moment
+ for (apb_unit = 0; apb_unit < 16; apb_unit++)
+ {
+ idreg_addr = (uint32_t*) (apb_addr | 0x000ff000 | (apb_unit << 3));
+ idreg_word = *idreg_addr;
+ bar_addr = idreg_addr + 1;
+ bar_word = *bar_addr;
+
+ dev_addr = apb_addr | ((bar_word & 0xfff00000) >> 12);
+ vendor = (idreg_word >> 24) & 0xff;
+ device = (idreg_word >> 12) & 0xfff;
+ version = (idreg_word >> 5) & 0xf;
+ irq = (idreg_word >> 0) & 0x1f;
+
+ if (vendor > 0)
+ {
+ putstr(" apbslv");
+ fill( putint( apb_unit), 4);
+
+ // print idreg word
+ putstr("vend 0x"); fill( puthex( 8, vendor), 4);
+ putstr("dev 0x"); fill( puthex(16, device), 6);
+ putstr("ver "); fill( putint( version), 4);
+ putstr("irq "); fill( putint( irq), 4);
+ putstr("addr 0x"); fill( puthex(32, dev_addr), 10);
+ if (verbose)
+ print_vendor_device( vendor, device);
+ putchar('\n');
+ }
+ }
+}
+
+void ahb_info( uint8_t verbose)
+{
+ uint16_t vendor;
+ uint16_t device;
+ uint16_t version;
+ uint16_t irq;
+
+ uint32_t address;
+ uint16_t cp;
+ uint16_t mask;
+ uint16_t type;
+
+ uint32_t config_word;
+ uint32_t bar;
+ uint32_t ahb_unit;
+
+ uint8_t i;
+
+ uint32_t* config_addr = (uint32_t*) 0xfffff000;
+ uint32_t* bar_addr = (uint32_t*) 0xfffff010;
+
+
+ // check for 64 master and 64 slaves
+ for (ahb_unit = 0; ahb_unit < 128; ahb_unit++)
+ {
+ config_addr = (uint32_t*) (0xfffff000 + (ahb_unit << 5));
+ bar_addr = (uint32_t*) config_addr + 4;
+
+ config_word = *config_addr;
+
+ vendor = (config_word >> 24) & 0xff;
+ device = (config_word >> 12) & 0xfff;
+ version = (config_word >> 5) & 0xf;
+ irq = (config_word >> 0) & 0x1f;
+
+ if (vendor > 0)
+ {
+ if (ahb_unit < 64)
+ {
+ putstr("ahbmst");
+ fill( putint( ahb_unit), 6);
+ }
+ else
+ {
+ putstr("ahbslv");
+ fill( putint( ahb_unit - 64), 6);
+ }
+
+ // print config word
+ putstr("vend 0x"); fill( puthex( 8, vendor), 4);
+ putstr("dev 0x"); fill( puthex(16, device), 6);
+ putstr("ver "); fill( putint( version), 4);
+ putstr("irq "); fill( putint( irq), 4);
+ putstr("addr 0x"); fill( puthex(32, *bar_addr & 0xfff00000), 10);
+ if (verbose)
+ print_vendor_device( vendor, device);
+ putchar('\n');
+
+ if ((vendor == 1) && (device == 6))
+ apb_info( bar_addr, verbose);
+
+ /*
+ // check all 4 bank address registers
+ for (i = 0; i < 4; i++)
+ {
+ bar = *bar_addr;
+
+ address = bar & 0xfff0000;
+ cp = (bar >> 16) & 0xf;
+ mask = (bar >> 4) & 0xfff;
+ type = (bar >> 0) & 0xf;
+
+ // print bank address register
+ putstr("address 0x"); fill( puthex( 32, address), 6);
+ putstr("c/p 0x"); fill( puthex( 8, cp), 6);
+ putstr("mask 0x"); fill( puthex( 16, mask), 6);
+ putstr("type 0x"); fill( puthex( 8, type), 6);
+ putchar('\n');
+
+ bar_addr++;
+ } // for i
+ */
+
+ } // vendor > 0
+ } // for ahb_unit
+}
+
diff --git a/mig_test/software/ambainfo.h b/mig_test/software/ambainfo.h
new file mode 100644
index 0000000..e9828f1
--- /dev/null
+++ b/mig_test/software/ambainfo.h
@@ -0,0 +1,16 @@
+/*
+ * $HeadURL: https://svn.fzd.de/repo/concast/FWF_Projects/FWKE/hw_sp605/bsp_zpuahb/software/ambainfo.h $
+ * $Date$
+ * $Author$
+ * $Revision$
+ */
+
+
+#ifndef AMBAINFO_H
+#define AMBAINFO_H
+
+void print_vendor_device( uint8_t vendor, uint8_t device);
+void apb_info( uint32_t* addr, uint8_t verbose);
+void ahb_info( uint8_t verbose);
+
+#endif // AMBAINFO_H
diff --git a/mig_test/software/include/common.h b/mig_test/software/include/common.h
new file mode 100644
index 0000000..9028a90
--- /dev/null
+++ b/mig_test/software/include/common.h
@@ -0,0 +1,23 @@
+/*
+ * $HeadURL: https://svn.fzd.de/repo/concast/FWF_Projects/FWKE/hw_sp605/bsp_zpuahb/software/include/common.h $
+ * $Date$
+ * $Author$
+ * $Revision$
+ */
+
+#ifndef COMMON_H
+#define COMMON_H
+
+////////////////////////////////////////
+// specific stuff
+
+char putchar ( char c);
+void putstr ( const char *s);
+void putbin ( unsigned char dataType, unsigned long data);
+unsigned char puthex ( unsigned char dataType, unsigned long data);
+unsigned char itoa ( int z, char* Buffer );
+unsigned char putint ( unsigned long data);
+unsigned char putuint ( long data);
+void putpfloat( unsigned long data);
+
+#endif // COMMON_H
diff --git a/mig_test/software/include/lcd-routines.h b/mig_test/software/include/lcd-routines.h
new file mode 100644
index 0000000..e3516cf
--- /dev/null
+++ b/mig_test/software/include/lcd-routines.h
@@ -0,0 +1,167 @@
+/*
+ * $HeadURL: https://svn.fzd.de/repo/concast/FWF_Projects/FWKE/hw_sp605/bsp_zpuahb/software/include/lcd-routines.h $
+ * $Date$
+ * $Author$
+ * $Revision$
+ */
+
+
+// Ansteuerung eines HD44780 kompatiblen LCD im 4-Bit-Interfacemodus
+// http://www.mikrocontroller.net/articles/AVR-GCC-Tutorial/LCD-Ansteuerung
+//
+
+#ifndef LCD_ROUTINES_H
+#define LCD_ROUTINES_H
+
+#include "peripherie.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Hier die verwendete Taktfrequenz in Hz eintragen, wichtig!
+
+#ifndef F_CPU
+#define F_CPU 50000000
+#endif
+
+////////////////////////////////////////////////////////////////////////////////
+// Pinbelegung fĂŒr das LCD, an verwendete Pins anpassen
+// Alle LCD Pins mĂŒssen an einem Port angeschlossen sein und die 4
+// Datenleitungen mĂŒssen auf aufeinanderfolgenden Pins liegen
+
+// LCD DB4-DB7 <--> PORTD Bit PD0-PD3
+#define LCD_PORT (gpio0->ioout)
+#define LCD_DDR (gpio0->iodir)
+#define LCD_DB (8)
+
+// LCD RS <--> PORTD Bit PD4 (RS: 0=Data, 1=Command)
+#define LCD_RS (14)
+
+// LCD EN <--> PORTD Bit PD5 (EN: 1-Impuls fĂŒr Daten)
+#define LCD_EN (13)
+
+#define LCD_RW (15)
+
+////////////////////////////////////////////////////////////////////////////////
+// LCD AusfĂŒhrungszeiten (MS=Millisekunden, US=Mikrosekunden)
+
+#define LCD_BOOTUP_MS 15
+#define LCD_ENABLE_US 1
+#define LCD_WRITEDATA_US 46
+#define LCD_COMMAND_US 42
+
+#define LCD_SOFT_RESET_MS1 5
+#define LCD_SOFT_RESET_MS2 1
+#define LCD_SOFT_RESET_MS3 1
+#define LCD_SET_4BITMODE_MS 5
+
+#define LCD_CLEAR_DISPLAY_MS 2
+#define LCD_CURSOR_HOME_MS 2
+
+////////////////////////////////////////////////////////////////////////////////
+// Zeilendefinitionen des verwendeten LCD
+// Die EintrĂ€ge hier sollten fĂŒr ein LCD mit einer ZeilenlĂ€nge von 16 Zeichen passen
+// Bei anderen ZeilenlĂ€ngen mĂŒssen diese EintrĂ€ge angepasst werden
+
+#define LCD_DDADR_LINE1 0x00
+#define LCD_DDADR_LINE2 0x40
+#define LCD_DDADR_LINE3 0x10
+#define LCD_DDADR_LINE4 0x50
+
+////////////////////////////////////////////////////////////////////////////////
+// Initialisierung: muss ganz am Anfang des Programms aufgerufen werden.
+void lcd_init( void );
+
+////////////////////////////////////////////////////////////////////////////////
+// LCD löschen
+void lcd_clear( void );
+
+////////////////////////////////////////////////////////////////////////////////
+// Cursor in die 1. Zeile, 0-te Spalte
+void lcd_home( void );
+
+////////////////////////////////////////////////////////////////////////////////
+// Cursor an eine beliebige Position
+void lcd_setcursor( uint8_t spalte, uint8_t zeile );
+
+////////////////////////////////////////////////////////////////////////////////
+// Ausgabe eines einzelnen Zeichens an der aktuellen Cursorposition
+void lcd_data( uint8_t data );
+
+////////////////////////////////////////////////////////////////////////////////
+// Ausgabe eines Strings an der aktuellen Cursorposition
+void lcd_string( const char *data );
+
+////////////////////////////////////////////////////////////////////////////////
+// Definition eines benutzerdefinierten Sonderzeichens.
+// data muss auf ein Array[5] mit den Spaltencodes des zu definierenden Zeichens
+// zeigen
+void lcd_generatechar( uint8_t code, const uint8_t *data );
+
+////////////////////////////////////////////////////////////////////////////////
+// Ausgabe eines Kommandos an das LCD.
+void lcd_command( uint8_t data );
+
+
+////////////////////////////////////////////////////////////////////////////////
+// LCD Befehle und Argumente.
+// Zur Verwendung in lcd_command
+
+// Clear Display -------------- 0b00000001
+#define LCD_CLEAR_DISPLAY 0x01
+
+// Cursor Home ---------------- 0b0000001x
+#define LCD_CURSOR_HOME 0x02
+
+// Set Entry Mode ------------- 0b000001xx
+#define LCD_SET_ENTRY 0x04
+
+#define LCD_ENTRY_DECREASE 0x00
+#define LCD_ENTRY_INCREASE 0x02
+#define LCD_ENTRY_NOSHIFT 0x00
+#define LCD_ENTRY_SHIFT 0x01
+
+// Set Display ---------------- 0b00001xxx
+#define LCD_SET_DISPLAY 0x08
+
+#define LCD_DISPLAY_OFF 0x00
+#define LCD_DISPLAY_ON 0x04
+#define LCD_CURSOR_OFF 0x00
+#define LCD_CURSOR_ON 0x02
+#define LCD_BLINKING_OFF 0x00
+#define LCD_BLINKING_ON 0x01
+
+// Set Shift ------------------ 0b0001xxxx
+#define LCD_SET_SHIFT 0x10
+
+#define LCD_CURSOR_MOVE 0x00
+#define LCD_DISPLAY_SHIFT 0x08
+#define LCD_SHIFT_LEFT 0x00
+#define LCD_SHIFT_RIGHT 0x04
+
+// Set Function --------------- 0b001xxxxx
+#define LCD_SET_FUNCTION 0x20
+
+#define LCD_FUNCTION_4BIT 0x00
+#define LCD_FUNCTION_8BIT 0x10
+#define LCD_FUNCTION_1LINE 0x00
+#define LCD_FUNCTION_2LINE 0x08
+#define LCD_FUNCTION_5X7 0x00
+#define LCD_FUNCTION_5X10 0x04
+
+#define LCD_SOFT_RESET 0x30
+
+// Set CG RAM Address --------- 0b01xxxxxx (Character Generator RAM)
+#define LCD_SET_CGADR 0x40
+
+#define LCD_GC_CHAR0 0
+#define LCD_GC_CHAR1 1
+#define LCD_GC_CHAR2 2
+#define LCD_GC_CHAR3 3
+#define LCD_GC_CHAR4 4
+#define LCD_GC_CHAR5 5
+#define LCD_GC_CHAR6 6
+#define LCD_GC_CHAR7 7
+
+// Set DD RAM Address --------- 0b1xxxxxxx (Display Data RAM)
+#define LCD_SET_DDADR 0x80
+
+#endif
diff --git a/mig_test/software/include/peripherie.h b/mig_test/software/include/peripherie.h
new file mode 100644
index 0000000..9734d4c
--- /dev/null
+++ b/mig_test/software/include/peripherie.h
@@ -0,0 +1,323 @@
+/*
+ * $HeadURL: https://svn.fzd.de/repo/concast/FWF_Projects/FWKE/hw_sp605/bsp_zpuahb/software/include/peripherie.h $
+ * $Date$
+ * $Author$
+ * $Revision$
+ */
+
+
+#ifndef PERIPHERIE_H
+#define PERIPHERIE_H
+
+#include <types.h>
+
+////////////////////
+// hardware types
+
+// gpio
+typedef struct {
+ volatile uint32_t iodata; // 000
+ volatile uint32_t ioout; // 001
+ volatile uint32_t iodir; // 010, for bidir port bits
+ volatile uint32_t irqmask; // 011
+ volatile uint32_t irqpol; // 100
+ volatile uint32_t irqedge; // 101
+ volatile uint32_t bypass; // 110
+} grgpio_t;
+
+
+// uart
+#define UART_STATUS_DATA_READY (1<< 0)
+#define UART_STATUS_TX_SHREG_EMPTY (1<< 1)
+#define UART_STATUS_TX_REG_EMPTY (1<< 2)
+#define UART_STATUS_BREAK_RECEIVED (1<< 3)
+#define UART_STATUS_OVERRUN (1<< 4)
+#define UART_STATUS_PARITY_ERROR (1<< 5)
+#define UART_STATUS_FRAMING_ERROR (1<< 6)
+#define UART_STATUS_TX_FIFO_HALF_FULL (1<< 7)
+#define UART_STATUS_RX_FIFO_HALF_FULL (1<< 8)
+#define UART_STATUS_TX_FIFO_FULL (1<< 9)
+#define UART_STATUS_RX_FIFO_FULL (1<<10)
+
+#define UART_CONTROL_RX_ENABLE (1<< 0)
+#define UART_CONTROL_TX_ENABLE (1<< 1)
+#define UART_CONTROL_RX_INT_ENABLE (1<< 2)
+#define UART_CONTROL_TX_INT_ENABLE (1<< 3)
+#define UART_CONTROL_PARITY_SELECT (1<< 4)
+#define UART_CONTROL_PARITY_ENABLE (1<< 5)
+#define UART_CONTROL_FLOW_CONTROL (1<< 6)
+#define UART_CONTROL_LOOP_BACK (1<< 7)
+#define UART_CONTROL_EXTERNAL_CLOCK (1<< 8)
+#define UART_CONTROL_TX_FIFO_INT_ENABLE (1<< 9)
+#define UART_CONTROL_RX_FIFO_INT_ENABLE (1<<10)
+#define UART_CONTROL_FIFO_DEBUG_MODE (1<<11)
+#define UART_CONTROL_BREAK_INT_ENABLE (1<<12)
+#define UART_CONTROL_DELAYED_INT_ENABLE (1<<13)
+#define UART_CONTROL_TX_REG_EMPTY_INT_ENABLE (1<<14)
+#define UART_CONTROL_FIFO_AVAILIBLE (1<<31)
+
+typedef struct {
+ volatile uint32_t data; // 000000
+ volatile uint32_t status; // 000001
+ volatile uint32_t ctrl; // 000010
+ volatile uint32_t scaler; // 000011
+ volatile uint32_t fifo_debug; // 000100
+} apbuart_t;
+
+
+// timer (grip.pdf p. 279)
+#define TIMER_ENABLE (1<<0)
+#define TIMER_RESTART (1<<1)
+#define TIMER_LOAD (1<<2)
+#define TIMER_INT_ENABLE (1<<3)
+#define TIMER_INT_PENDING (1<<4)
+#define TIMER_CHAIN (1<<5)
+#define TIMER_DEBUG_HALT (1<<6)
+typedef struct {
+ volatile uint32_t value;
+ volatile uint32_t reload;
+ volatile uint32_t ctrl;
+ volatile uint32_t unused;
+} gptimer_element_t;
+
+#define TIMER_CONFIG_DISABLE_FREEZE (1<<8)
+typedef struct {
+ volatile uint32_t scaler; // 00000
+ volatile uint32_t scaler_reload; // 00001
+ volatile uint32_t config; // 00010 ntimers, pirq
+ volatile uint32_t unused; // 00011
+ gptimer_element_t e[8];
+} gptimer_t;
+
+#define CLOCKS_PER_SECOND (1000)
+void usleep( uint32_t nsec);
+void msleep( uint32_t msec);
+void sleep( uint32_t sec);
+void timer_init( void);
+
+
+// i2c
+// control register
+#define I2C_CORE_ENABLE (1<<7)
+#define I2C_INT_ENABLE (1<<6)
+// command register
+#define I2C_START (1<<7)
+#define I2C_STOP (1<<6)
+#define I2C_READ (1<<5)
+#define I2C_WRITE (1<<4)
+#define I2C_ACK (1<<3)
+#define I2C_INT_ACK (1<<0)
+// status register
+#define I2C_RX_ACK (1<<7)
+#define I2C_BUSY (1<<6)
+#define I2C_ARB_LOST (1<<5)
+#define I2C_TIP (1<<1)
+#define I2C_INT (1<<0)
+
+typedef struct {
+ volatile uint32_t clock_prescaler; // prer 0x00
+ volatile uint32_t control; // ctr 0x04
+ volatile uint32_t data; // xr 0x08 write -> transmit, read -> receive
+ volatile uint32_t command; // csr 0x0c write -> command, read -> status
+} i2cmst_t; // i2cmstregs
+
+
+// vga
+typedef struct {
+ volatile uint32_t data;
+ volatile uint32_t background_color;
+ volatile uint32_t foreground_color;
+} apbvga_t;
+
+
+// ethernet
+#define ETHER_DESCRIPTOR_ENABLE (1<<11)
+#define ETHER_DESCRIPTOR_WRAP (1<<12)
+#define ETHER_DESCRIPTOR_INT_ENABLE (1<<13)
+#define ETHER_DESCRIPTOR_UNDERRUN_ERR (1<<14)
+#define ETHER_DESCRIPTOR_ATTEMEPT_LIMIT_ERR (1<<15)
+typedef struct {
+ volatile uint32_t control;
+ volatile uint32_t address;
+} greth_tx_descriptor_t;
+
+#define ETHER_CONTROL_TX_ENABLE (1<< 0)
+#define ETHER_CONTROL_RX_ENABLE (1<< 1)
+#define ETHER_CONTROL_TX_INT (1<< 2)
+#define ETHER_CONTROL_RX_INT (1<< 3)
+#define ETHER_CONTROL_FULL_DUPLEX (1<< 4)
+#define ETHER_CONTROL_PROMISCUOUS_MODE (1<< 5)
+#define ETHER_CONTROL_RESET (1<< 6)
+#define ETHER_CONTROL_SPEED (1<< 7)
+#define ETHER_CONTROL_EDCL_AVAILABLE (1<<31)
+
+#define ETHER_STATUS_RX_ERROR (1<< 0)
+#define ETHER_STATUS_TX_ERROR (1<< 1)
+#define ETHER_STATUS_RX_INT (1<< 2)
+#define ETHER_STATUS_TX_INT (1<< 3)
+#define ETHER_STATUS_RX_AHB_ERROR (1<< 4)
+#define ETHER_STATUS_TX_AHB_ERROR (1<< 5)
+#define ETHER_STATUS_RX_TOO_SMALL (1<< 6)
+#define ETHER_STATUS_INVALID_ADDRESS (1<< 7)
+
+#define ETHER_MDIO_WR (1<< 0)
+#define ETHER_MDIO_RD (1<< 1)
+#define ETHER_MDIO_LINKFAIL (1<< 2)
+#define ETHER_MDIO_BUSY (1<< 3)
+#define ETHER_MDIO_NOT_VALID (1<< 4)
+
+typedef struct {
+ volatile uint32_t control; // 0x00
+ volatile uint32_t status; // 0x04
+ volatile uint32_t mac_msb; // 0x08
+ volatile uint32_t mac_lsb; // 0x0C
+ volatile uint32_t mdio_control; // 0x10
+ volatile uint32_t tx_pointer; // 0x14
+ volatile uint32_t rx_pointer; // 0x18
+ volatile uint32_t edcl_ip; // 0x1C
+ volatile uint32_t hash_msb; // 0x20
+ volatile uint32_t hash_lsb; // 0x24
+} greth_t;
+
+
+struct udp_header_st {
+ uint16_t source_port;
+ uint16_t dest_port;
+ uint16_t length;
+ uint16_t checksum;
+ uint8_t data[1500];//[data_length];
+} __attribute((packed));
+
+typedef struct udp_header_st udp_header_t;
+
+
+//uint32_t data_length = 64; // minimum size is 46 (w/o vlan tag) or 42 (with vlan tag)
+
+#define PROTOCOL_UDP (17)
+#define FLAG_DF (1<<14)
+#define FLAG_MF (1<<15)
+struct ip_header_st {
+ uint8_t version; // +ihl (ip header length)
+ uint8_t tos;
+ uint16_t length;
+ uint16_t identification;
+ uint16_t fragment_offset; // +flags
+ uint8_t ttl;
+ uint8_t protocol_id; // udp = 17, tcp = 6
+ uint16_t checksum;
+ uint32_t source_ip;
+ uint32_t dest_ip;
+ udp_header_t udp_header;
+} __attribute((packed));
+
+typedef struct ip_header_st ip_header_t;
+
+#define ETHERTYPE_IPv4 (0x0800)
+#define ETHERTYPE_ARP (0x0806)
+struct mac_header_st {
+ uint8_t dest_mac[6];
+ uint8_t source_mac[6];
+ uint16_t ethertype; // length or eg. 0x800 IPv4, 0x0806 ARP, 0x8892 Profinet, 0x88a4 etherCat
+ ip_header_t ip_header;
+} __attribute((packed));
+typedef struct mac_header_st mac_header_t;
+
+
+// ddr control register set
+typedef struct {
+ volatile uint32_t sdram_control;
+ volatile uint32_t sdram_config;
+ volatile uint32_t sdram_power_saving;
+ volatile uint32_t reserved;
+ volatile uint32_t status_read;
+ volatile uint32_t phy_config_0;
+ volatile uint32_t phy_config_1;
+} ddrspa_t;
+
+
+// dcm control
+typedef struct {
+ volatile uint32_t psstatus;
+ volatile int32_t psdec;
+ volatile int32_t psinc;
+ volatile int32_t psvalue;
+} dcm_ctrl_t;
+
+
+// debug console (for simulation)
+char debug_putchar( char c);
+
+// function pointer for putchar
+extern char (* stdout) ( char);
+
+
+// iqr
+typedef struct {
+ volatile uint32_t irq_level; // 0x00
+ volatile uint32_t irq_pending; // 0x04
+ volatile uint32_t irq_force; // 0x08
+ volatile uint32_t irq_clear; // 0x0c
+ volatile uint32_t mp_status; // 0x10
+ volatile uint32_t broadcast; // 0x14 (NCPU > 1)
+ volatile uint32_t dummy[10]; // 0x18 - 0x3c
+ volatile uint32_t irq_mask; // 0x40
+ // open: interrupt force, extended interrupt acknowledge
+} irqmp_t;
+
+
+// mctrl
+typedef struct {
+ volatile uint32_t mcfg1; // 0x00
+ volatile uint32_t mcfg2; // 0x04
+ volatile uint32_t mcfg3; // 0x08
+ volatile uint32_t mcfg4; // 0x0c
+} mctrl_t;
+
+
+////////////////////
+// hardware units
+
+// ZPU frequency
+#define F_CPU (125000000)
+
+// set min prescaler to ntimers+1
+#define TIMER_PRESCALER (8)
+
+// scaler for uart
+#define UART_BAUD_RATE (115200)
+//#define UART_BAUD_RATE (9600)
+#define UART_SCALER (F_CPU/(8 * UART_BAUD_RATE))
+#define UART_FIFOSIZE (16)
+
+// scaler for i2c
+#define I2C_PRESCALER_100K (F_CPU/(5 * 100000)-1)
+#define I2C_PRESCALER_400K (F_CPU/(5 * 400000)-1)
+
+
+extern apbuart_t *uart0;
+extern gptimer_t *timer0;
+extern irqmp_t *irqmp0;
+extern apbvga_t *vga0;
+extern grgpio_t *gpio0;
+extern greth_t *ether0;
+extern mctrl_t *mctrl0;
+volatile extern uint32_t *debug_con0;
+volatile extern uint32_t *reset_reg;
+extern ddrspa_t *ddr0;
+
+extern i2cmst_t *i2c_dvi;
+extern i2cmst_t *i2c_fmc;
+
+//char *debug_con0 = (char *) 0x80000000;
+//uint32_t *reset_reg = (uint32_t *) 0x80000004;
+//apbuart_t *uart0 = (apbuart_t *) 0x80000100;
+//gptimer_t *timer0 = (gptimer_t *) 0x80000200;
+//grgpio_t *gpio0 = (grgpio_t *) 0x80000400;
+//apbvga_t *vga0 = (apbvga_t *) 0x80000600;
+//i2cmst_t *i2cmst0 = (i2cmst_t *) 0x80000700;
+
+//greth_t *ether0 = (greth_t *) 0x80000c00;
+//dcm_ctrl_t *dcm_ctrl0 = (dcm_ctrl_t *) 0x80000e00;
+//ddrspa_t *ddr0 = (ddrspa_t *) 0xfff00000;
+
+#endif // PERIPHERIE_H
diff --git a/mig_test/software/include/timer.h b/mig_test/software/include/timer.h
new file mode 100644
index 0000000..fa4875f
--- /dev/null
+++ b/mig_test/software/include/timer.h
@@ -0,0 +1,49 @@
+/*
+ * $HeadURL: https://svn.fzd.de/repo/concast/FWF_Projects/FWKE/hw_sp605/bsp_zpuahb/software/include/timer.h $
+ * $Date$
+ * $Author$
+ * $Revision$
+ */
+
+
+#include "peripherie.h"
+
+#ifndef TIMER_H
+#define TIMER_H
+
+
+////////////////////////////////////////
+// timer functions
+
+
+// wait for a given time in micro seconds
+void usleep(uint32_t usec);
+
+// wait for given time in milli seconds
+void msleep(uint32_t msec);
+
+
+// wait for given time in seconds
+void sleep(uint32_t sec);
+
+
+// deliver the milli seconds from timer 0.1
+uint32_t msecs( void);
+
+// deliver the seconds from timer 0.2
+uint32_t seconds( void);
+
+// deliver the time (in seconds and fraction) from timer
+uint32_t get_time( void);
+
+// just a loop
+void wait( uint32_t value);
+
+
+// initialisation for the timer
+void timer_init( void);
+
+#define TIMER_STOP timer0->e[1].ctrl &= ~TIMER_ENABLE;
+#define TIMER_RUN timer0->e[1].ctrl |= TIMER_ENABLE;
+
+#endif // TIMER_H
diff --git a/mig_test/software/include/types.h b/mig_test/software/include/types.h
new file mode 100644
index 0000000..d8e6862
--- /dev/null
+++ b/mig_test/software/include/types.h
@@ -0,0 +1,43 @@
+/*
+ * $HeadURL: https://svn.fzd.de/repo/concast/FWF_Projects/FWKE/hw_sp605/bsp_zpuahb/software/include/types.h $
+ * $Date$
+ * $Author$
+ * $Revision$
+ */
+
+
+#ifndef TYPES_H
+#define TYPES_H
+
+////////////////////
+// common types
+
+typedef signed char int8_t;
+typedef unsigned char uint8_t;
+
+typedef short int16_t;
+typedef unsigned short uint16_t;
+
+typedef long int32_t;
+typedef unsigned long uint32_t;
+
+typedef long long int64_t;
+typedef unsigned long long uint64_t;
+
+#define TRUE (1==1)
+#define FALSE (1==0)
+
+
+////////////////////////////////////////
+// common defines
+
+#define set_bit(mem, bv) ((mem) |= bv)
+#define clear_bit(mem, bv) ((mem) &= ~bv)
+#define toggle_bit(mem, bv) ((mem) ^= bv)
+#define bit_is_set(mem, bv) (mem & bv)
+#define bit_is_clear(mem, bv) (!(mem & bv))
+#define loop_until_bit_is_set(mem, bv) do {} while( bit_is_clear(mem, bv))
+#define loop_until_bit_is_clear(mem, bv) do {} while( bit_is_set(mem, bv))
+
+
+#endif // TYPES_H
diff --git a/mig_test/software/include/uart.h b/mig_test/software/include/uart.h
new file mode 100644
index 0000000..ca040e4
--- /dev/null
+++ b/mig_test/software/include/uart.h
@@ -0,0 +1,25 @@
+/*
+ * $HeadURL: https://svn.fzd.de/repo/concast/FWF_Projects/FWKE/hw_sp605/bsp_zpuahb/software/include/uart.h $
+ * $Date$
+ * $Author$
+ * $Revision$
+ */
+
+
+#ifndef UART_H
+#define UART_H
+
+
+////////////////////////////////////////
+// uart functions
+
+#define UART_HW_HANDSHAKE_ON (uart0-> ctrl |= UART_CONTROL_FLOW_CONTROL)
+#define UART_HW_HANDSHAKE_OFF (uart0-> ctrl &= ~UART_CONTROL_FLOW_CONTROL)
+
+void uart_init( void);
+unsigned int uart_check_receiver();
+char uart_getchar();
+void uart_putchar_raw( char c);
+char uart_putchar( char c);
+
+#endif // UART_H
diff --git a/mig_test/software/include/vga.h b/mig_test/software/include/vga.h
new file mode 100644
index 0000000..f4d3914
--- /dev/null
+++ b/mig_test/software/include/vga.h
@@ -0,0 +1,18 @@
+/*
+ * $HeadURL: https://svn.fzd.de/repo/concast/FWF_Projects/FWKE/hw_sp605/bsp_zpuahb/software/include/vga.h $
+ * $Date$
+ * $Author$
+ * $Revision$
+ */
+
+
+#include "peripherie.h"
+
+
+extern uint8_t vga_line;
+extern uint8_t vga_column;
+
+void vga_init( void);
+void vga_clear( void);
+void vga_putchar( char c);
+
diff --git a/mig_test/software/lib/crt0.S b/mig_test/software/lib/crt0.S
new file mode 100644
index 0000000..9c9e199
--- /dev/null
+++ b/mig_test/software/lib/crt0.S
@@ -0,0 +1,973 @@
+/* Startup code for ZPU
+ Copyright (C) 2005 Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file with other programs, and to distribute
+those programs without any restriction coming from the use of this
+file. (The General Public License restrictions do apply in other
+respects; for example, they cover modification of the file, and
+distribution when not linked into another program.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING. If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA. */
+ .file "crt0.S"
+
+
+; cleaned BLa
+
+
+; .section ".fixed_vectors","ax"
+; KLUDGE!!! we remove the executable bit to avoid relaxation
+ .section ".fixed_vectors","a"
+
+; DANGER!!!!
+; we need to align these code sections to 32 bytes, which
+; means we must not use any assembler instructions that are relaxed
+; at linker time
+; DANGER!!!!
+
+ .macro fixedim value
+ im \value
+ .endm
+
+ .macro jsr address
+ im _memreg ; save R0
+ load
+ im _memreg+4 ; save R1
+ load
+ im _memreg+8 ; save R2
+ load
+ fixedim \address
+ call
+ im _memreg+8
+ store ; restore R2
+ im _memreg+4
+ store ; restore R1
+ im _memreg
+ store ; restore R0
+ .endm
+
+
+ .macro jmp address
+ fixedim \address
+ poppc
+ .endm
+
+
+ .macro fast_neg
+ not
+ im 1
+ add
+ .endm
+
+ .macro cimpl funcname
+ ; save R0
+ im _memreg
+ load
+
+ ; save R1
+ im _memreg+4
+ load
+
+ ; save R2
+ im _memreg+8
+ load
+
+ loadsp 20
+ loadsp 20
+
+ fixedim \funcname
+ call
+
+ ; destroy arguments on stack
+ storesp 0
+ storesp 0
+
+ im _memreg
+ load
+
+ ; poke the result into the right slot
+ storesp 24
+
+ ; restore R2
+ im _memreg+8
+ store
+
+ ; restore R1
+ im _memreg+4
+ store
+
+ ; restore r0
+ im _memreg
+ store
+
+
+ storesp 4
+ poppc
+ .endm
+
+ .macro mult1bit
+ ; create mask of lowest bit in A
+ loadsp 8 ; A
+ im 1
+ and
+ im -1
+ add
+ not
+ loadsp 8 ; B
+ and
+ add ; accumulate in C
+
+ ; shift B left 1 bit
+ loadsp 4 ; B
+ addsp 0
+ storesp 8 ; B
+
+ ; shift A right 1 bit
+ loadsp 8 ; A
+ flip
+ addsp 0
+ flip
+ storesp 12 ; A
+ .endm
+
+
+
+/* vectors */
+ .balign 32,0
+# offset 0x0000 0000
+ .globl _start
+_start:
+ ; intSp must be 0 when we jump to _premain; aha BLa
+
+ ;im ZPU_ID
+ ;loadsp 0
+ ;im _cpu_config
+ ;store
+ ;config
+ jmp _premain
+
+
+ .balign 32,0
+# offset 0x0000 0020
+ .globl _zpu_interrupt_vector
+_zpu_interrupt_vector:
+ jmp ___zpu_interrupt_vector
+
+# memreg moved Bla
+# offset 0x0000 0030
+ .balign 16,0
+ .globl _memreg
+ .weak _memreg
+_memreg:
+
+
+
+/* instruction emulation code */
+
+# opcode 34
+# offset 0x0000 0040
+ .balign 32,0
+_loadh:
+ loadsp 4
+ ; by not masking out bit 0, we cause a memory access error
+ ; on unaligned access
+ im ~0x2
+ and
+ load
+
+ ; mult 8
+ loadsp 8
+ im 3
+ and
+ fast_neg
+ im 2
+ add
+ im 3
+ ashiftleft
+ ; shift right addr&3 * 8
+ lshiftright
+ im 0xffff
+ and
+ storesp 8
+
+ poppc
+
+# opcode 35
+# offset 0x0000 0060
+ .balign 32,0
+_storeh:
+ loadsp 4
+ ; by not masking out bit 0, we cause a memory access error
+ ; on unaligned access
+ im ~0x2
+ and
+ load
+
+ ; mask
+ im 0xffff
+ loadsp 12
+ im 3
+ and
+ fast_neg
+ im 2
+ add
+ im 3
+ ashiftleft
+ ashiftleft
+ not
+
+ and
+
+ loadsp 12
+ im 0xffff
+
+ nop
+
+ fixedim _storehtail
+ poppc
+
+
+# opcode 36
+# offset 0x0000 0080
+ .balign 32,0
+_lessthan:
+ loadsp 8
+ fast_neg
+ loadsp 8
+ add
+
+ ; DANGER!!!!
+ ; 0x80000000 will overflow when negated, so we need to mask
+ ; the result above with the compare positive to negative
+ ; number case
+ loadsp 12
+ loadsp 12
+ not
+ and
+ not
+ and
+
+
+ ; handle case where we are comparing a negative number
+ ; and positve number. This can underflow. E.g. consider 0x8000000 < 0x1000
+ loadsp 12
+ not
+ loadsp 12
+ and
+
+ or
+
+
+
+ flip
+ im 1
+ and
+
+
+ storesp 12
+ storesp 4
+ poppc
+
+
+# opcode 37
+# offset 0x0000 00a0
+ .balign 32,0
+_lessthanorequal:
+ loadsp 8
+ loadsp 8
+ lessthan
+ loadsp 12
+ loadsp 12
+ eq
+ or
+
+ storesp 12
+ storesp 4
+ poppc
+
+
+# opcode 38
+# offset 0x0000 00c0
+ .balign 32,0
+_ulessthan:
+ ; fish up arguments
+ loadsp 4
+ loadsp 12
+
+ /* low: -1 if low bit dif is negative 0 otherwise: neg (not x&1 and (y&1))
+ x&1 y&1 neg (not x&1 and (y&1))
+ 1 1 0
+ 1 0 0
+ 0 1 -1
+ 0 0 0
+
+ */
+ loadsp 4
+ not
+ loadsp 4
+ and
+ im 1
+ and
+ neg
+
+
+ /* high: upper 31-bit diff is only wrong when diff is 0 and low=-1
+ high=x>>1 - y>>1 + low
+
+ extremes
+
+ 0000 - 1111:
+ low= neg(not 0 and 1) = 1111 (-1)
+ high=000+ neg(111) +low = 000 + 1001 + low = 1000
+ OK
+
+ 1111 - 0000
+ low=neg(not 1 and 0) = 0
+ high=111+neg(000) + low = 0111
+ OK
+
+
+ */
+ loadsp 8
+
+ flip
+ addsp 0
+ flip
+
+ loadsp 8
+
+ flip
+ addsp 0
+ flip
+
+ sub
+
+ ; if they are equal, then the last bit decides...
+ add
+
+ /* test if negative: result = flip(diff) & 1 */
+ flip
+ im 1
+ and
+
+ ; destroy a&b which are on stack
+ storesp 4
+ storesp 4
+
+ storesp 12
+ storesp 4
+ poppc
+
+# opcode 39
+# offset 0x0000 00e0
+ .balign 32,0
+_ulessthanorequal:
+ loadsp 8
+ loadsp 8
+ ulessthan
+ loadsp 12
+ loadsp 12
+ eq
+ or
+
+ storesp 12
+ storesp 4
+ poppc
+
+
+# opcode 40
+# offset 0x0000 0100
+ .balign 32,0
+ .globl _swap
+_swap:
+ breakpoint ; tbd
+
+# opcode 41
+# offset 0x0000 0120
+ .balign 32,0
+_slowmult:
+ im _slowmultImpl
+ poppc
+
+# opcode 42
+# offset 0x0000 0140
+ .balign 32,0
+_lshiftright:
+ loadsp 8
+ flip
+
+ loadsp 8
+ ashiftleft
+ flip
+
+ storesp 12
+ storesp 4
+
+ poppc
+
+
+# opcode 43
+# offset 0x0000 0160
+ .balign 32,0
+_ashiftleft:
+ loadsp 8
+
+ loadsp 8
+ im 0x1f
+ and
+ fast_neg
+ im _ashiftleftEnd
+ add
+ poppc
+
+
+
+# opcode 44
+# offset 0x0000 0180
+ .balign 32,0
+_ashiftright:
+ loadsp 8
+ loadsp 8
+ lshiftright
+
+ ; handle signed value
+ im -1
+ loadsp 12
+ im 0x1f
+ and
+ lshiftright
+ not ; now we have an integer on the stack with the signed
+ ; bits in the right position
+
+ ; mask these bits with the signed bit.
+ loadsp 16
+ not
+ flip
+ im 1
+ and
+ im -1
+ add
+
+ and
+
+ ; stuff in the signed bits...
+ or
+
+ ; store result into correct stack slot
+ storesp 12
+
+ ; move up return value
+ storesp 4
+ poppc
+
+# opcode 45
+# offset 0x0000 01a0
+ .balign 32,0
+_call:
+ ; fn
+ loadsp 4
+
+ ; return address
+ loadsp 4
+
+ ; store return address
+ storesp 12
+
+ ; fn to call
+ storesp 4
+
+ pushsp ; flush internal stack
+ popsp
+
+ poppc
+
+_storehtail:
+
+ and
+ loadsp 12
+ im 3
+ and
+ fast_neg
+ im 2
+ add
+ im 3
+ ashiftleft
+ nop
+ ashiftleft
+
+ or
+
+ loadsp 8
+ im ~0x3
+ and
+
+ store
+
+ storesp 4
+ storesp 4
+ poppc
+
+
+# opcode 46
+# offset 0x0000 01c0
+ .balign 32,0
+_eq:
+ loadsp 8
+ fast_neg
+ loadsp 8
+ add
+
+ not
+ loadsp 0
+ im 1
+ add
+ not
+ and
+ flip
+ im 1
+ and
+
+ storesp 12
+ storesp 4
+ poppc
+
+# opcode 47
+# offset 0x0000 01e0
+ .balign 32,0
+_neq:
+ loadsp 8
+ fast_neg
+ loadsp 8
+ add
+
+ not
+ loadsp 0
+ im 1
+ add
+ not
+ and
+ flip
+
+ not
+
+ im 1
+ and
+
+ storesp 12
+ storesp 4
+ poppc
+
+
+# opcode 48
+# offset 0x0000 0200
+ .balign 32,0
+_neg:
+ loadsp 4
+ not
+ im 1
+ add
+ storesp 8
+
+ poppc
+
+
+# opcode 49
+# offset 0x0000 0220
+ .balign 32,0
+_sub:
+ loadsp 8
+ loadsp 8
+ fast_neg
+ add
+ storesp 12
+
+ storesp 4
+
+ poppc
+
+
+# opcode 50
+# offset 0x0000 0240
+ .balign 32,0
+_xor:
+ loadsp 8
+ not
+ loadsp 8
+ and
+
+ loadsp 12
+ loadsp 12
+ not
+ and
+
+ or
+
+ storesp 12
+ storesp 4
+ poppc
+
+# opcode 51
+# offset 0x0000 0260
+ .balign 32,0
+_loadb:
+ loadsp 4
+ im ~0x3
+ and
+ load
+
+ loadsp 8
+ im 3
+ and
+ fast_neg
+ im 3
+ add
+ ; x8
+ addsp 0
+ addsp 0
+ addsp 0
+
+ lshiftright
+
+ im 0xff
+ and
+ storesp 8
+
+ poppc
+
+
+# opcode 52
+# offset 0x0000 0280
+ .balign 32,0
+_storeb:
+ loadsp 4
+ im ~0x3
+ and
+ load
+
+ ; mask away destination
+ im _mask
+ loadsp 12
+ im 3
+ and
+ addsp 0
+ addsp 0
+ add
+ load
+
+ and
+
+
+ im _storebtail
+ poppc
+
+# opcode 53
+# offset 0x0000 02a0
+ .balign 32,0
+_div:
+ jmp ___div
+
+# opcode 54
+# offset 0x0000 02c0
+ .balign 32,0
+_mod:
+ jmp ___mod
+
+# opcode 55
+# offset 0x0000 02e0
+ .balign 32,0
+ .globl _eqbranch
+_eqbranch:
+ loadsp 8
+
+ ; eq
+
+ not
+ loadsp 0
+ im 1
+ add
+ not
+ and
+ flip
+ im 1
+ and
+
+ ; mask
+ im -1
+ add
+ loadsp 0
+ storesp 16
+
+ ; no branch address
+ loadsp 4
+
+ and
+
+ ; fetch boolean & neg mask
+ loadsp 12
+ not
+
+ ; calc address & mask for branch
+ loadsp 8
+ loadsp 16
+ add
+ ; subtract 1 to find PC of branch instruction
+ im -1
+ add
+
+ and
+
+ or
+
+ storesp 4
+ storesp 4
+ storesp 4
+ poppc
+
+
+# opcode 56
+# offset 0x0000 0300
+ .balign 32,0
+ .globl _neqbranch
+_neqbranch:
+ loadsp 8
+
+ ; neq
+
+ not
+ loadsp 0
+ im 1
+ add
+ not
+ and
+ flip
+
+ not
+
+ im 1
+ and
+
+ ; mask
+ im -1
+ add
+ loadsp 0
+ storesp 16
+
+ ; no branch address
+ loadsp 4
+
+ and
+
+ ; fetch boolean & neg mask
+ loadsp 12
+ not
+
+ ; calc address & mask for branch
+ loadsp 8
+ loadsp 16
+ add
+ ; find address of branch instruction
+ im -1
+ add
+
+ and
+
+ or
+
+ storesp 4
+ storesp 4
+ storesp 4
+ poppc
+
+# opcode 57
+# offset 0x0000 0320
+ .balign 32,0
+ .globl _poppcrel
+_poppcrel:
+ add
+ ; address of poppcrel
+ im -1
+ add
+ poppc
+
+# opcode 58
+# offset 0x0000 0340
+ .balign 32,0
+ .globl _config
+_config:
+ im 1
+ nop
+ im _hardware
+ store
+ storesp 4
+ poppc
+
+# opcode 59
+# offset 0x0000 0360
+ .balign 32,0
+_pushpc:
+ loadsp 4
+ im 1
+ add
+ storesp 8
+ poppc
+
+# opcode 60
+# offset 0x0000 0380
+ .balign 32,0
+_syscall_emulate:
+ .byte 0
+
+# opcode 61
+# offset 0x0000 03a0
+ .balign 32,0
+_pushspadd:
+ pushsp
+ im 4
+ add
+ loadsp 8
+ addsp 0
+ addsp 0
+ add
+ storesp 8
+
+ poppc
+
+# opcode 62
+# offset 0x0000 03c0
+ .balign 32,0
+_halfmult:
+ breakpoint
+
+# opcode 63
+# offset 0x0000 03e0
+ .balign 32,0
+_callpcrel:
+ loadsp 4
+ loadsp 4
+ add
+ im -1
+ add
+ loadsp 4
+
+ storesp 12 ; return address
+ storesp 4
+ pushsp ; this will flush the internal stack.
+ popsp
+ poppc
+
+ .text
+
+
+
+
+_ashiftleftBegin:
+ .rept 0x1f
+ addsp 0
+ .endr
+_ashiftleftEnd:
+ storesp 12
+ storesp 4
+ poppc
+
+_storebtail:
+ loadsp 12
+ im 0xff
+ and
+ loadsp 12
+ im 3
+ and
+
+ fast_neg
+ im 3
+ add
+ ; x8
+ addsp 0
+ addsp 0
+ addsp 0
+
+ ashiftleft
+
+ or
+
+ loadsp 8
+ im ~0x3
+ and
+
+ store
+
+ storesp 4
+ storesp 4
+ poppc
+
+
+
+
+; NB! this is not an EMULATE instruction. It is a varargs fn.
+ .globl _syscall
+_syscall:
+ syscall
+ poppc
+
+_slowmultImpl:
+
+ loadsp 8 ; A
+ loadsp 8 ; B
+ im 0 ; C
+
+.LmoreMult:
+ mult1bit
+
+ ; cutoff
+ loadsp 8
+ .byte (.LmoreMult-.Lbranch)&0x7f+0x80
+.Lbranch:
+ neqbranch
+
+ storesp 4
+ storesp 4
+ storesp 12
+ storesp 4
+ poppc
+
+___mod:
+ cimpl __modsi3
+___div:
+ cimpl __divsi3
+
+ .globl ___zpu_interrupt_vector
+ .weak ___zpu_interrupt_vector
+
+___zpu_interrupt_vector:
+ jsr _zpu_interrupt
+ poppc
+
+ .data
+ .balign 4,0
+_mask:
+ .long 0x00ffffff
+ .long 0xff00ffff
+ .long 0xffff00ff
+ .long 0xffffff00
+
+
+ .globl _hardware
+_hardware:
+ .long 0
+ .globl _cpu_config
+_cpu_config:
+ .long 0
+
diff --git a/mig_test/software/lib/divmod.c b/mig_test/software/lib/divmod.c
new file mode 100644
index 0000000..e810ea7
--- /dev/null
+++ b/mig_test/software/lib/divmod.c
@@ -0,0 +1,50 @@
+long udivmodsi4 ();
+
+long
+__divsi3 (long a, long b)
+{
+ int neg = 0;
+ long res;
+
+ if (a < 0)
+ {
+ a = -a;
+ neg = !neg;
+ }
+
+ if (b < 0)
+ {
+ b = -b;
+ neg = !neg;
+ }
+
+ res = udivmodsi4 (a, b, 0);
+
+ if (neg)
+ res = -res;
+
+ return res;
+}
+
+long
+__modsi3 (long a, long b)
+{
+ int neg = 0;
+ long res;
+
+ if (a < 0)
+ {
+ a = -a;
+ neg = 1;
+ }
+
+ if (b < 0)
+ b = -b;
+
+ res = udivmodsi4 (a, b, 1);
+
+ if (neg)
+ res = -res;
+
+ return res;
+}
diff --git a/mig_test/software/lib/premain.c b/mig_test/software/lib/premain.c
new file mode 100644
index 0000000..6206c06
--- /dev/null
+++ b/mig_test/software/lib/premain.c
@@ -0,0 +1,26 @@
+/*
+extern char _data_start;
+extern char _data_end;
+extern char _data_start_rom;
+*/
+
+
+void _premain( void)
+{
+/*
+ int count;
+ char *dst = (char *) &_data_start;
+ char *src = (char *) &_data_start_rom;
+
+ if ( (&_data_start) != (&_data_start_rom) )
+ {
+ count = &_data_end - &_data_start;
+ while (count--)
+ {
+ *dst++ = *src++;
+ }
+ }
+*/
+
+ main();
+}
diff --git a/mig_test/software/lib/udivmodsi4.c b/mig_test/software/lib/udivmodsi4.c
new file mode 100644
index 0000000..7d1cb67
--- /dev/null
+++ b/mig_test/software/lib/udivmodsi4.c
@@ -0,0 +1,24 @@
+unsigned long
+udivmodsi4(unsigned long num, unsigned long den, int modwanted)
+{
+ unsigned long bit = 1;
+ unsigned long res = 0;
+
+ while (den < num && bit && !(den & (1L<<31)))
+ {
+ den <<=1;
+ bit <<=1;
+ }
+ while (bit)
+ {
+ if (num >= den)
+ {
+ num -= den;
+ res |= bit;
+ }
+ bit >>=1;
+ den >>=1;
+ }
+ if (modwanted) return num;
+ return res;
+}
diff --git a/mig_test/software/libhal/Makefile b/mig_test/software/libhal/Makefile
new file mode 100644
index 0000000..fe149c1
--- /dev/null
+++ b/mig_test/software/libhal/Makefile
@@ -0,0 +1,31 @@
+#
+# $HeadURL: https://svn.fzd.de/repo/concast/FWF_Projects/FWKE/hw_sp605/bsp_zpuahb/software/libhal/Makefile $
+# $Date$
+# $Author$
+# $Revision$
+#
+
+DIR=..
+include include.mak
+
+
+C_FILES=hw.c common.c timer.c uart.c vga.c
+OBJECTS=hw.o common.o timer.o uart.o vga.o
+INCLUDES=../include/peripherie.h
+
+
+all: libhal.a
+
+
+libhal.a: $(OBJECTS) $(INCLUDES)
+ $(AR) clr libhal.a $(OBJECTS)
+ $(RANLIB) libhal.a
+
+
+%.o: %.c $(INCLUDES)
+ $(CC) -c -o $@ $< $(CFLAGS)
+
+
+clean:
+ rm -f *.o
+ rm -f libhal.a
diff --git a/mig_test/software/libhal/common.c b/mig_test/software/libhal/common.c
new file mode 100644
index 0000000..941c7e4
--- /dev/null
+++ b/mig_test/software/libhal/common.c
@@ -0,0 +1,203 @@
+/*
+ * $HeadURL: https://svn.fzd.de/repo/concast/FWF_Projects/FWF_Internals/FPGA/hw_sp605/bsp_zpuahb/software/libhal/common.c $
+ * $Date$
+ * $Author$
+ * $Revision$
+ */
+
+
+#include <peripherie.h>
+#include <stdlib.h> // utoa, dtostrf (actually not implemented)
+
+////////////////////////////////////////
+// common stuff
+
+
+// libgloss/zpu/syscalls.c work with inbyte and outbyte
+char putchar( char c)
+{
+ return stdout( c);
+}
+
+
+
+void putstr(const char *s)
+{
+ while (*s)
+ putchar( *s++);
+}
+
+
+/*
+ print data in binary format
+ prepend 0b
+ parameter: dataType - number of bits
+*/
+void putbin( unsigned char dataType, unsigned long data)
+{
+ unsigned char i, temp;
+ char dataString[] = "0b ";
+
+ for(i=dataType; i>0; i--)
+ {
+ temp = data % 2;
+ dataString [i+1] = temp + 0x30;
+ data = data/2;
+ }
+ putstr( dataString);
+}
+
+
+// http://asalt-vehicle.googlecode.com/svnâ€ș trunkâ€ș srcâ€ș uart.c
+unsigned char puthex( unsigned char dataType, unsigned long data)
+{
+ unsigned char count = 8; // number of chars
+ unsigned char i;
+ unsigned char temp;
+ char dataString[] = " ";
+
+ // dataType = bit width
+ if (dataType == 4) count = 1;
+ if (dataType == 8) count = 2;
+ if (dataType == 16) count = 4;
+
+ for(i=count; i>0; i--)
+ {
+ temp = data % 16;
+ if (temp<10) dataString [i-1] = temp + 0x30;
+ else dataString [i-1] = (temp - 10) + 0x41;
+
+ data = data/16;
+ }
+ dataString[count] = '\0';
+ putstr( dataString);
+
+ return count; // return length
+}
+
+
+
+// http://www.mikrocontroller.net/articles/FAQ#itoa.28.29
+unsigned char itoa( long z, char* Buffer )
+{
+ int i = 0;
+ int j;
+ char tmp;
+ unsigned u; // In u bearbeiten wir den Absolutbetrag von z.
+
+ // ist die Zahl negativ?
+ // gleich mal ein - hinterlassen und die Zahl positiv machen
+ if( z < 0 ) {
+ Buffer[0] = '-';
+ Buffer++;
+ // -INT_MIN ist idR. grĂ¶ĂŸer als INT_MAX und nicht mehr
+ // als int darstellbar! Man muss daher bei der Bildung
+ // des Absolutbetrages aufpassen.
+ u = ( (unsigned)-(z+1) ) + 1;
+ }
+ else {
+ u = (unsigned)z;
+ }
+ // die einzelnen Stellen der Zahl berechnen
+ do {
+ Buffer[i++] = '0' + u % 10;
+ u /= 10;
+ } while( u > 0 );
+
+ // den String in sich spiegeln
+ for( j = 0; j < i / 2; ++j ) {
+ tmp = Buffer[j];
+ Buffer[j] = Buffer[i-j-1];
+ Buffer[i-j-1] = tmp;
+ }
+ Buffer[i] = '\0';
+ // Laengenkorrektur wg. Vorzeichen
+ if (z < 0)
+ i++;
+ return i; // BLa: Laenge des Buffers zurueckgeben
+}
+
+unsigned char utoa( unsigned long i, char *p)
+{
+ unsigned char length;
+
+ length = 0;
+ do {
+ *--p = '0' + i % 10;
+ i /= 10;
+ length++;
+ } while (i > 0);
+ return length;
+}
+
+
+unsigned char putuint( unsigned long data)
+{
+ char str[20];
+ unsigned char length;
+
+ length = utoa( data, str);
+ putstr( str);
+ return length;
+}
+
+
+unsigned char putint( long data)
+{
+ char str[20];
+ unsigned char length;
+
+ length = itoa( data, str);
+ putstr( str);
+ return length;
+}
+/*
+ putint( 1000); putchar('\n'); // ok
+ putint( 10000); putchar('\n'); // ok
+ putint( 100000); putchar('\n'); // ok
+ putint( 1000000); putchar('\n'); // ok
+ putint( 10000000); putchar('\n'); // ok
+ putint( 100000000); putchar('\n'); // ok
+ putint( 200000000); putchar('\n'); // ok
+ putint( 400000000); putchar('\n'); // ok
+ putint( 800000000); putchar('\n'); // ok
+ putint( 1000000000); putchar('\n'); // ok
+ putint( 2000000000); putchar('\n'); // ok
+ putint( 4000000000); putchar('\n'); // -294967296 warning: this decimal constant is unsigned only in ISO C90
+ putint( 8000000000); putchar('\n'); // -589934592 warning: integer constant is too large for "long" type
+*/
+
+unsigned char putfloat( float data)
+{
+ char str[20];
+ unsigned char length;
+
+ length = dtostrf( data, 2, 1, str);
+ putstr( str);
+ return length;
+}
+
+
+// p means pseudo float
+// (an integer with 3 significant digits after the point)
+void putpfloat( unsigned long data)
+{
+ putint( data/1000);
+ putchar( '.');
+ putint( data%1000 );
+}
+
+
+unsigned char putbool( int data)
+{
+ if (data)
+ {
+ putstr( "yes");
+ }
+ else
+ {
+ putstr( "no");
+ }
+ return 0;
+}
+
diff --git a/mig_test/software/libhal/hw.c b/mig_test/software/libhal/hw.c
new file mode 100644
index 0000000..8401010
--- /dev/null
+++ b/mig_test/software/libhal/hw.c
@@ -0,0 +1,28 @@
+#include "peripherie.h"
+
+volatile uint32_t *debug_con0 = (uint32_t *) 0x80000000;
+volatile uint32_t *reset_reg = (uint32_t *) 0x80000004;
+apbuart_t *uart0 = (apbuart_t *) 0x80000100;
+gptimer_t *timer0 = (gptimer_t *) 0x80000200;
+irqmp_t *irqmp0 = (irqmp_t *) 0x80000300;
+grgpio_t *gpio0 = (grgpio_t *) 0x80000400;
+apbvga_t *vga0 = (apbvga_t *) 0x80000600;
+i2cmst_t *i2c_dvi = (i2cmst_t *) 0x80000700;
+i2cmst_t *i2c_fmc = (i2cmst_t *) 0x80000a00;
+
+mctrl_t *mctrl0 = (mctrl_t *) 0x80000f00;
+/*
+greth_t *ether0 = (greth_t *) 0x80000c00;
+dcm_ctrl_t *dcm_ctrl0 = (dcm_ctrl_t *) 0x80000e00;
+ddrspa_t *ddr0 = (ddrspa_t *) 0xfff00000;
+*/
+
+char debug_putchar( char c)
+{
+ *debug_con0 = (uint32_t) c;
+ return 0;
+}
+
+char (* stdout) (char) = debug_putchar;
+
+
diff --git a/mig_test/software/libhal/include.mak b/mig_test/software/libhal/include.mak
new file mode 100644
index 0000000..226ca66
--- /dev/null
+++ b/mig_test/software/libhal/include.mak
@@ -0,0 +1,16 @@
+AS=zpu-elf-as
+CC=zpu-elf-gcc
+LD=zpu-elf-ld
+OBJCOPY=zpu-elf-objcopy
+OBJDUMP=zpu-elf-objdump
+AR=zpu-elf-ar
+RANLIB=zpu-elf-ranlib
+SIZE=zpu-elf-size
+
+ROMGEN=$(DIR)/support/zpuromgen
+
+INLCUDES=-I$(DIR)/include
+ASFLAGS=-adhls -g $(INLCUDES)
+CFLAGS=-O3 -phi -Wall -ffunction-sections -fdata-sections $(INLCUDES)
+LDFLAGS=--relax --gc-sections
+OBJCOPYFLAGS=--strip-debug --discard-locals
diff --git a/mig_test/software/libhal/timer.c b/mig_test/software/libhal/timer.c
new file mode 100644
index 0000000..789c565
--- /dev/null
+++ b/mig_test/software/libhal/timer.c
@@ -0,0 +1,132 @@
+#include "peripherie.h"
+
+#include "timer.h"
+
+////////////////////////////////////////
+// timer functions
+// timer 0.0 is used for usleep
+// timer 0.0 is used for msleep
+// timer 0.0 is used for sleep (via msleep)
+//
+// timer 0.0 ticks with milliseconds
+// timer 0.1 ticks with seconds
+
+
+// wait for a given time in micro seconds
+void usleep(uint32_t usec)
+{
+ uint32_t tcr;
+
+ // 1 usec = 6
+ timer0->e[0].reload = (F_CPU/TIMER_PRESCALER/1000000)*usec;
+ timer0->e[0].ctrl = TIMER_ENABLE | TIMER_LOAD;
+
+ do
+ {
+ tcr = timer0->e[0].ctrl;
+ } while ( (tcr & TIMER_ENABLE));
+}
+
+
+// wait for given time in milli seconds
+void msleep(uint32_t msec)
+{
+ uint32_t tcr;
+
+ // some values for 50MHz @ Spartan 3e
+ // 1 msec = 6250
+ // 167 msec = 2**20 (20 bit counter) 391 slices
+ // 2684 msec = 2**24 (24 bit counter) 450 slices
+ // = 2**32 (32 bit counter) 572 slices
+ // some values for 52MHz @ Spartan 6
+ // 1 msec = 6500
+ // 161 msec = 2**20 (20 bit counter)
+ // 2581 msec = 2**24 (24 bit counter) 450 slices
+ // 660 sec = 2**32 (32 bit counter) 572 slices
+ timer0->e[0].reload = (F_CPU/TIMER_PRESCALER/1000)*msec;
+ timer0->e[0].ctrl = TIMER_ENABLE | TIMER_LOAD;
+
+ do
+ {
+ tcr = timer0->e[0].ctrl;
+ } while ( (tcr & TIMER_ENABLE));
+}
+
+
+// wait for given time in seconds
+void sleep(uint32_t sec)
+{
+ uint32_t timer;
+
+ for (timer=0; timer<sec; timer++)
+ {
+ msleep( 100);
+ msleep( 100);
+ msleep( 100);
+ msleep( 100);
+ msleep( 100);
+ msleep( 100);
+ msleep( 100);
+ msleep( 100);
+ msleep( 100);
+ msleep( 100);
+ }
+}
+
+
+
+// deliver the milliseconds from timer 0.0
+uint32_t msecs( void)
+{
+ return( timer0->e[0].value);
+}
+
+
+// deliver the seconds from timer 0.1
+uint32_t seconds( void)
+{
+ return( timer0->e[1].value);
+}
+
+
+// deliver the time (in seconds and fraction) from timer
+uint32_t get_time( void)
+{
+ uint32_t value;
+
+ TIMER_STOP;
+
+ // combine values (seconds.milliseconds)
+ value = timer0->e[1].value * 1000 + timer0->e[0].value;
+
+ TIMER_RUN;
+
+ return( value);
+}
+
+
+// just a loop
+void wait( uint32_t value)
+{
+ uint32_t i;
+
+ for (i=0; i<value; i++) {}
+}
+
+
+// initialisation for the timer
+void timer_init( void)
+{
+ timer0->scaler_reload = TIMER_PRESCALER-1; // set prescaler
+
+ // set timer 0.1 in chain mode to timer 0.0
+ // so it counts in seconds
+ timer0->e[1].reload = 0xffffffff;
+ timer0->e[1].ctrl = TIMER_ENABLE | TIMER_RESTART | TIMER_LOAD | TIMER_CHAIN;
+
+ // set timer 0.0 to free running in msec
+ timer0->e[0].reload = (F_CPU/TIMER_PRESCALER/CLOCKS_PER_SECOND);
+ timer0->e[0].ctrl = TIMER_ENABLE | TIMER_RESTART | TIMER_LOAD;
+}
+
+
diff --git a/mig_test/software/libhal/uart.c b/mig_test/software/libhal/uart.c
new file mode 100644
index 0000000..d1290b5
--- /dev/null
+++ b/mig_test/software/libhal/uart.c
@@ -0,0 +1,56 @@
+//#include <stdio.h>
+
+#include "peripherie.h"
+
+////////////////////////////////////////
+// common defines
+
+#define bit_is_set(mem, bv) (mem & bv)
+#define bit_is_clear(mem, bv) (!(mem & bv))
+#define loop_until_bit_is_set(mem, bv) do {} while( bit_is_clear(mem, bv))
+#define loop_until_bit_is_clear(mem, bv) do {} while( bit_is_set(mem, bv))
+
+
+////////////////////////////////////////
+// uart functions
+
+
+void uart_init( void)
+{
+ uart0->scaler = UART_SCALER;
+ uart0->ctrl = UART_CONTROL_TX_ENABLE | UART_CONTROL_RX_ENABLE;
+}
+
+
+unsigned int uart_check_receiver()
+{
+ return ( bit_is_set( uart0->status, UART_STATUS_DATA_READY) != 0);
+}
+
+
+char uart_getchar()
+{
+ loop_until_bit_is_set(uart0->status, UART_STATUS_DATA_READY);
+ return uart0->data;
+}
+
+
+void uart_putchar_raw( char c)
+{
+ #if UART_FIFOSIZE==1 || !defined(UART_FIFOSIZE)
+ loop_until_bit_is_set( uart0->status, UART_STATUS_TX_REG_EMPTY);
+ #else
+ loop_until_bit_is_clear( uart0->status, UART_STATUS_TX_FIFO_FULL);
+ #endif
+ uart0->data = c;
+}
+
+
+char uart_putchar( char c)
+{
+ if (c == '\n')
+ uart_putchar_raw( '\r');
+ uart_putchar_raw( c);
+ return 0;
+}
+
diff --git a/mig_test/software/libhal/vga.c b/mig_test/software/libhal/vga.c
new file mode 100644
index 0000000..8cc55b9
--- /dev/null
+++ b/mig_test/software/libhal/vga.c
@@ -0,0 +1,67 @@
+//#include <stdio.h>
+
+#include "peripherie.h"
+
+
+////////////////////////////////////////
+// common defines
+
+#define bit_is_set(mem, bv) (mem & bv)
+#define bit_is_clear(mem, bv) (!(mem & bv))
+#define loop_until_bit_is_set(mem, bv) do {} while( bit_is_clear(mem, bv))
+#define loop_until_bit_is_clear(mem, bv) do {} while( bit_is_set(mem, bv))
+
+
+
+
+uint8_t vga_line;
+uint8_t vga_column;
+
+void vga_init( void)
+{
+ vga0->background_color = 0x00000000;
+ vga0->foreground_color = 0x0000ff00;
+ vga_line = 0;
+ vga_column = 0;
+}
+
+
+
+void vga_clear( void)
+{
+ uint32_t count;
+ uint32_t count_max = 37*80;
+
+ for(count = 0; count< count_max; count++)
+ vga0->data = count<<8;
+
+ vga_line = 0;
+ vga_column = 0;
+}
+
+
+void vga_putchar( char c)
+{
+
+ vga0->data = (( vga_line * 80 + vga_column)<<8) | c;
+ if ( (c == '\n') || (vga_column == 79) ) // line feed (+ carrige return)
+ {
+ if (vga_line<36)
+ vga_line++;
+ else
+ vga_line = 0;
+
+ vga_column = 0;
+ }
+ else if (c == '\f') // form feed
+ {
+ vga_clear();
+ }
+ else
+ {
+ vga_column++;
+ }
+
+}
+
+
diff --git a/mig_test/software/main.c b/mig_test/software/main.c
new file mode 100644
index 0000000..883090a
--- /dev/null
+++ b/mig_test/software/main.c
@@ -0,0 +1,285 @@
+/*
+ * $Date$
+ * $Author$
+ * $Revision$
+ */
+
+//#include <stdio.h>
+
+#define BOARD_GIGABEE
+
+#include "../include/peripherie.h"
+#include <common.h>
+#include <timer.h> // sleep
+#include <uart.h>
+#include "schedule.h" // scheduler_init, scheduler_task_*
+#include "monitor.h" // monitor_init, monitor_add_command, monitor_mainloop
+#include "monitor_functions.h" // x_function, wmem_function, clear_function, quit_function
+
+
+////////////////////////////////////////
+// named IOs
+// input
+#define MAC_DATA (1<< 4)
+#define SIMULATION_ACTIVE (1<< 31)
+// output
+#define LED0 (1<< 0)
+#define LED1 (1<< 1)
+#define LED2 (1<< 2)
+#define LED3 (1<< 3)
+#define LED_USER (1<< 5)
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////
+
+uint32_t simulation_active;
+volatile uint8_t timer_tick;
+uint8_t end_simulation = FALSE;
+
+
+////////////////////////////////////////
+// prototypes
+
+void running_light( uint32_t simulation_active);
+
+uint32_t run_light_function( void);
+
+
+
+
+////////////////////////////////////////
+// combined print functions
+
+/*
+char uart_lcd_putchar( char c, FILE *stream)
+{
+ uart_putchar( c, stream);
+ lcd_putc( c, stream);
+}
+*/
+
+
+
+
+// helper functions ////////////////////////////////////////
+////////////////////////////////////////////////////////////
+
+// monitor functions ///////////////////////////////////////
+////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////
+
+void running_light( uint32_t simulation_active)
+{
+ unsigned int pattern = 0x80300700;
+
+ while (1)
+ {
+
+ gpio0->ioout = 0x0000000f & pattern;
+ pattern = (pattern << 1) | (pattern >> 31);
+
+
+ if ( simulation_active)
+ {
+ // do only limited runs
+ if ( timer_tick)
+ {
+ timer_tick = FALSE;
+ scheduler_task_check();
+
+ if ( end_simulation) break;
+ }
+ }
+ else
+ {
+ msleep( 125);
+ }
+ }
+
+}
+
+
+
+////////////////////////////////////////////////////////////
+
+
+////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////
+// functions for scheduler
+
+void end_simulation_task( void)
+{
+ end_simulation = TRUE;
+}
+
+
+
+////////////////////////////////////////////////////////////
+// start running light
+uint32_t run_light_function( void)
+{
+ running_light( simulation_active);
+ return 0;
+}
+
+
+
+//
+// process serial commands
+//
+void uart_monitor( void)
+{
+ uint8_t c;
+ uint8_t key_time_out = 250;
+ uint32_t key_state;
+
+ putchar( '\n');
+
+ monitor_init();
+
+
+// monitor_add_command("reset", "system reset", reset_function);
+ monitor_add_command("sysinfo", "show system info <verbose>", system_info_function);
+
+ monitor_add_command("run", "running light", run_light_function);
+
+ monitor_add_command("wmem", "write word <addr> <length> <value(s)>", wmem_function);
+ monitor_add_command("x", "eXamine memory <addr> <length>", x_function);
+ monitor_add_command("task", "print tasklist", scheduler_tasklist);
+
+ monitor_add_command("help", "", help_function);
+
+
+ // initial help
+ help_function();
+
+ monitor_prompt();
+
+ monitor_run = TRUE;
+
+ while( monitor_run)
+ {
+ // process scheduler
+ if (timer_tick)
+ {
+ timer_tick = FALSE;
+ scheduler_task_check();
+ }
+
+ // process uart
+ if ( uart_check_receiver() )
+ {
+ monitor_input( uart_getchar() );
+ }
+
+ // process commands
+ monitor_mainloop();
+ }
+}
+
+
+
+////////////////////////////////////////////////////////////
+
+void banner( void)
+{
+ putstr("\n\n");
+ putstr("BSP Trenz Gigabee");
+
+ char *hw_revision = (char *)0x80000000;
+ char *svn_revision = (char *)0x80000020;
+ int32_t *hw_frequency = (int32_t *)0x80000040;
+
+ if (simulation_active)
+ {
+ putstr(" (on sim)\n");
+ }
+ else
+ {
+ putstr("\nSVN revision : "); putstr( svn_revision);
+ putstr("\nHW synthesized: "); putstr( hw_revision);
+ putstr("\nHW frequency : "); putint( *hw_frequency/1000000); putstr(" MHz");
+ putstr("\nSW compiled : " __DATE__ " " __TIME__ );
+ putstr("\nSW frequency : "); putint( F_CPU/1000000); putstr(" MHz");
+ putchar('\n');
+ }
+}
+
+
+////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////
+void _zpu_interrupt( void)
+{
+ uint32_t reg_val;
+
+ // check for timer 0.0 interrupt
+ reg_val = timer0->e[0].ctrl;
+ if bit_is_set( reg_val, TIMER_INT_PENDING)
+ {
+ // clear interrupt pending bit
+ clear_bit( reg_val, TIMER_INT_PENDING);
+ timer0->e[0].ctrl = reg_val;
+
+ timer_tick = TRUE;
+ }
+ return;
+}
+
+////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////
+
+int main(void)
+{
+
+ // check if on simulator or on hardware
+ simulation_active = bit_is_set( gpio0->iodata, (1<<31));
+
+ ////////////////////////////////////////////////////////////
+ // init stuff
+ timer_init();
+ uart_init();
+ scheduler_init();
+
+
+ // enable timer interrupt, for scheduler
+ set_bit( timer0->e[0].ctrl, TIMER_INT_ENABLE);
+
+
+ if (!simulation_active)
+ {
+ stdout = uart_putchar;
+ }
+ else
+ {
+ // debug_putchar is for simulator
+ stdout = debug_putchar;
+ }
+
+ ////////////////////////////////////////////////////////////
+ banner();
+
+ ////////////////////////////////////////////////////////////
+ // decide which main function to use
+
+ if ( !simulation_active)
+ {
+ uart_monitor();
+ }
+
+ // test of scheduler
+ scheduler_task_add( end_simulation_task, 1);
+ running_light( simulation_active);
+
+ ////////////////////////////////////////////////////////////
+ // end simulation
+ abort();
+
+}
diff --git a/mig_test/software/monitor.c b/mig_test/software/monitor.c
new file mode 100644
index 0000000..c5131e6
--- /dev/null
+++ b/mig_test/software/monitor.c
@@ -0,0 +1,225 @@
+/*
+ * $HeadURL: https://svn.fzd.de/repo/concast/FWF_Projects/FWKE/hw_sp605/bsp_zpuahb/software/monitor.c $
+ * $Date$
+ * $Author$
+ * $Revision$
+ */
+
+#include "monitor.h"
+
+////////////////////////////////////////////////////////////
+// monitor functions
+
+static char command_list[MAX_COMMANDS][MAX_COMMAND_LENGTH];
+static char help_list [MAX_COMMANDS][MAX_HELP_LENGTH];
+static command_ptr_t command_ptr_list[MAX_COMMANDS];
+
+uint8_t buffer[BUFFER_LENGTH];
+uint8_t command_number;
+uint8_t buffer_position;
+command_ptr_t exec_function;
+
+
+
+/*
+ reset some values for monitor
+*/
+void monitor_init( void)
+{
+ buffer_position = 0;
+ command_number = 0;
+ exec_function = 0;
+}
+
+
+/*
+ add an command to the monitor list
+*/
+void monitor_add_command(char* new_command, char* new_help, command_ptr_t new_command_ptr)
+{
+ if (command_number < MAX_COMMANDS)
+ {
+ strcpy( command_list[ command_number], new_command);
+ strcpy( help_list[ command_number], new_help);
+ command_ptr_list[ command_number] = new_command_ptr;
+ command_number++;
+ }
+ else
+ {
+ putstr("ERROR: too much commands.\n");
+ }
+}
+
+
+/*
+ print out a nice promt
+*/
+void monitor_prompt( void) {
+ putstr("> ");
+}
+
+
+/*
+ check the line buffer content and search command
+*/
+void process_buffer( void) {
+ uint8_t command_index;
+ uint8_t i;
+
+ i = 0;
+
+ while ( !((buffer[i] == ' ') || (buffer[i] == 0)) ) i++;
+
+ if (!i) {
+ monitor_prompt();
+ return;
+ }
+
+ for ( command_index = 0; command_index < command_number; command_index++) {
+ if ( !strncmp( command_list[ command_index], buffer, i) ) {
+ exec_function = command_ptr_list[ command_index];
+ return;
+ }
+ }
+ putstr("command not found.\n");
+ monitor_prompt();
+}
+
+
+uint8_t monitor_run;
+
+
+/*
+ execute the command
+*/
+void monitor_mainloop( void)
+{
+ uint32_t return_value;
+
+ // execute selected function
+ if (exec_function) {
+ return_value = exec_function();
+ exec_function = 0;
+
+ // print return value (as hex)
+ if (return_value > 0)
+ {
+ putstr("0x");
+ if (return_value > 0xffff)
+ puthex(32, return_value);
+ else
+ if (return_value > 0xff)
+ puthex(16, return_value);
+ else
+ puthex(8, return_value);
+ putchar('\n');
+ }
+
+ monitor_prompt();
+ }
+}
+
+
+/*
+ add an character to the monitor line buffer
+*/
+void monitor_input(uint8_t c) {
+
+ // carrige return
+ if (c == CR) {
+ putchar( LF);
+ buffer[ buffer_position++] = 0;
+ process_buffer();
+ buffer_position = 0;
+
+ // backspace or delete
+ } else if ( (c == BS) || (c == DEL)) {
+ if (buffer_position > 0) {
+ putchar( BS);
+ putchar( ' ');
+ putchar( BS);
+ buffer_position--;
+ }
+ } else {
+ // add to buffer
+ if ((c >= 0x20) && (buffer_position < (BUFFER_LENGTH-1))) {
+ putchar( c);
+ buffer[ buffer_position++] = c;
+ }
+ }
+}
+
+
+/*
+ parse the argument as string
+*/
+char* monitor_get_argument_string(uint8_t num)
+{
+ uint8_t index;
+ uint8_t arg;
+
+ // example line:
+ // " command arg1 arg2 arg3 "
+
+ index = 0;
+
+ // search for first char (non space)
+ while (( buffer[ index] != 0) && (buffer[ index] == ' ')) index++;
+
+ for ( arg = 0; arg < num; arg++)
+ {
+ // next space
+ while (( buffer[ index] != 0) && (buffer[ index] != ' ')) index++;
+ // next non space
+ while (( buffer[ index] != 0) && (buffer[ index] == ' ')) index++;
+ }
+ return &buffer[ index];
+}
+
+
+/*
+ parse the argument as integer
+*/
+int monitor_get_argument_int(uint8_t num)
+{
+ char *endptr;
+ return strtol( monitor_get_argument_string(num), &endptr, 0);
+}
+
+
+/*
+ parse the argument as hex number
+*/
+uint32_t monitor_get_argument_hex(uint8_t num)
+{
+ char *endptr;
+ return strtoul( monitor_get_argument_string(num), &endptr, 16);
+}
+
+
+
+/*
+ print all avalible functions as help screen
+*/
+uint32_t help_function( void)
+{
+ uint8_t command_index;
+ uint8_t i;
+
+ putchar( LF);
+ putstr("supported commands:\n\n");
+ for ( command_index = 0; command_index < command_number; command_index++) {
+ putstr( command_list[ command_index]);
+ if (strlen( help_list[ command_index]) > 0 )
+ {
+ for (i = strlen( command_list[ command_index]); i < MAX_COMMAND_LENGTH; i++) putchar(' ');
+ putstr( " - ");
+ putstr( help_list[ command_index]);
+ }
+ putchar('\n');
+ }
+ putchar( LF);
+ return command_number;
+}
+
+
diff --git a/mig_test/software/monitor.h b/mig_test/software/monitor.h
new file mode 100644
index 0000000..74d6472
--- /dev/null
+++ b/mig_test/software/monitor.h
@@ -0,0 +1,67 @@
+/*
+ * $HeadURL: https://svn.fzd.de/repo/concast/FWF_Projects/FWKE/hw_sp605/bsp_zpuahb/software/monitor.h $
+ * $Date$
+ * $Author$
+ * $Revision$
+ */
+
+
+#ifndef MONITOR_H
+#define MONITOR_H
+
+#include <types.h>
+
+////////////////////////////////////////////////////////////
+// monitor definitions
+
+#define MAX_COMMANDS (64)
+#define MAX_COMMAND_LENGTH (12)
+#define MAX_HELP_LENGTH (40)
+#define BUFFER_LENGTH (80)
+
+#define CR '\r'
+#define LF '\n'
+#define BS '\b'
+#define DEL (0x7f)
+
+#define SOH (0x01)
+#define EOT (0x04)
+#define ACK (0x06)
+#define NAK (0x15)
+#define CAN (0x18)
+#define EOF (0x1a)
+
+
+////////////////////////////////////////////////////////////
+// monitor variables
+
+typedef uint32_t (*command_ptr_t) (void);
+
+extern char command_list[MAX_COMMANDS][MAX_COMMAND_LENGTH];
+extern char help_list [MAX_COMMANDS][MAX_HELP_LENGTH];
+extern command_ptr_t command_ptr_list[MAX_COMMANDS];
+
+extern uint8_t buffer[BUFFER_LENGTH];
+extern uint8_t command_number;
+extern uint8_t buffer_position;
+extern command_ptr_t exec_function;
+
+
+////////////////////////////////////////////////////////////
+// monitor functions
+
+void monitor_init( void);
+void monitor_add_command(char* new_command, char* new_help, command_ptr_t new_command_ptr);
+void monitor_prompt( void);
+void process_buffer( void);
+extern uint8_t monitor_run;
+
+void monitor_mainloop( void);
+void monitor_input(uint8_t c);
+char* monitor_get_argument_string(uint8_t num);
+int monitor_get_argument_int(uint8_t num);
+uint32_t monitor_get_argument_hex(uint8_t num);
+
+uint32_t help_function( void);
+
+#endif // MONITOR_H
diff --git a/mig_test/software/monitor_functions.c b/mig_test/software/monitor_functions.c
new file mode 100644
index 0000000..5eda564
--- /dev/null
+++ b/mig_test/software/monitor_functions.c
@@ -0,0 +1,134 @@
+/*
+ * $HeadURL: https://svn.fzd.de/repo/concast/FWF_Projects/FWKE/hw_sp605/bsp_zpuahb/software/monitor_functions.c $
+ * $Date$
+ * $Author$
+ * $Revision$
+ */
+
+#include <types.h>
+#include "monitor.h"
+#include "ambainfo.h" // apb_info, ahb_info
+#include "peripherie.h"
+
+
+volatile uint8_t running_direction = 0;
+
+
+/*
+ exit the monitor program
+*/
+uint32_t quit_function( void)
+{
+ monitor_run = FALSE;
+ return 0;
+}
+
+
+/*
+ do a memory dump
+ arguments:
+ start address
+ length
+*/
+uint32_t x_function( void)
+{
+ uint32_t addr;
+ uint32_t count;
+ uint32_t index;
+ uint32_t* ptr;
+
+ addr = monitor_get_argument_hex(1);
+ count = monitor_get_argument_hex(2);
+
+ // set minimum count, if count is not set
+ if (count == 0) count = 16;
+
+ // we can only read at 32 bit aligned addresses
+ ptr = (uint32_t*)(addr & 0xfffffffc);
+
+ if (count != 1)
+ {
+ for (index = 0; index < count; index++)
+ {
+ if ( (index % 4) == 0)
+ {
+ putstr("\n0x"); puthex(32, (uint32_t)ptr); putstr(" : ");
+ }
+ putstr("0x"); puthex( 32, *ptr); putchar(' ');
+ *ptr++;
+ }
+ }
+ else
+ // fast version without address
+ {
+ putstr("0x"); puthex( 32, *ptr);
+ }
+ putchar( '\n');
+ return 0;
+}
+
+
+/*
+ write specific value on memory
+ arguments:
+ address
+ count
+ value(0) .. value(n)
+*/
+uint32_t wmem_function( void)
+{
+ uint32_t addr;
+ uint8_t count;
+ uint8_t index;
+ uint32_t value;
+ uint32_t* ptr;
+
+ addr = monitor_get_argument_hex(1);
+ count = monitor_get_argument_int(2);
+
+ ptr = (uint32_t*)addr; // automatic word aligned
+
+ index = 3;
+ while (count > 0)
+ {
+ value = monitor_get_argument_hex(index);
+ index++;
+ count--;
+ *ptr = value;
+ ptr++;
+ }
+ return count;
+}
+
+
+/*
+ clear screen
+*/
+uint32_t clear_function( void)
+{
+ putchar('\f');
+ return 0;
+}
+
+
+////////////////////////////////////////////////////////////
+// reset function
+uint32_t reset_function( void)
+{
+ *reset_reg = 0x87654321;
+ return 1;
+}
+
+
+////////////////////////////////////////////////////////////
+// system info
+uint32_t system_info_function( void)
+{
+ uint8_t verbose;
+
+ verbose = monitor_get_argument_int(1);
+ ahb_info( verbose);
+ return 0;
+}
+
+
diff --git a/mig_test/software/monitor_functions.h b/mig_test/software/monitor_functions.h
new file mode 100644
index 0000000..3061290
--- /dev/null
+++ b/mig_test/software/monitor_functions.h
@@ -0,0 +1,24 @@
+/*
+ * $HeadURL: https://svn.fzd.de/repo/concast/FWF_Projects/FWKE/hw_sp605/bsp_zpuahb/software/monitor_functions.h $
+ * $Date$
+ * $Author$
+ * $Revision$
+ */
+
+
+#ifndef MONITOR_FUNCTIONS_H
+#define MONITOR_FUNCTIONS_H
+
+extern volatile uint8_t running_direction;
+
+
+uint32_t quit_function( void);
+uint32_t x_function( void);
+uint32_t wmem_function( void);
+uint32_t clear_function( void);
+
+uint32_t reset_function( void);
+
+uint32_t system_info_function( void);
+
+#endif // MONITOR_FUNCTIONS_H
diff --git a/mig_test/software/schedule.c b/mig_test/software/schedule.c
new file mode 100644
index 0000000..41357eb
--- /dev/null
+++ b/mig_test/software/schedule.c
@@ -0,0 +1,144 @@
+/*
+ * $HeadURL: https://svn.fzd.de/repo/concast/FWF_Projects/FWKE/hw_sp605/bsp_zpuahb/software/schedule.c $
+ * $Date$
+ * $Author$
+ * $Revision$
+ */
+
+#include <types.h>
+#include "schedule.h"
+
+#define MAXTIMERS 10
+#define T_FREE 254 // > MAXTIMERS
+#define T_LAST 255
+
+typedef struct{
+ uint8_t next; // next in list or end mark
+ t_res delta; // delta to previous entry
+ funcp func;
+} t_ctrl_struct;
+
+
+t_ctrl_struct t_ctrl_lst[MAXTIMERS];
+t_res t_delay; // count down until next service
+uint8_t t_first; // point to first entry
+
+
+void scheduler_task_check(void)
+{
+ t_ctrl_struct *p; // for faster access
+
+ --t_delay;
+ while( t_delay == 0 ){ // serve if delay = 0
+ if( t_first == T_LAST ) // no function to serve
+ break;
+ p = &t_ctrl_lst[t_first];
+ t_first = p->next; // point to next
+ p->next = T_FREE; // mark free
+ t_delay = t_ctrl_lst[t_first].delta; // next delay delta
+ p->func(); // execute function
+ }
+}
+
+
+uint8_t scheduler_task_add( funcp func, t_res delay )
+{
+ uint8_t n;
+ uint8_t i; // index
+ uint8_t ipre; // previous index
+ t_res d1; // last delta delay
+ t_ctrl_struct *p; // for faster access
+
+ for( n = 0;; ){
+ p = &t_ctrl_lst[n];
+ if( p->next == T_FREE )
+ break;
+ n++;
+ if( n == MAXTIMERS )
+ return 1; // error, list full
+ }
+
+ i = t_first;
+ d1 = t_delay;
+ while( i != T_LAST ){ // check until end
+ if( d1 >= delay ){ // last >= new
+ t_ctrl_lst[i].delta = d1 - delay; // correct following entry
+ break;
+ }else{
+ delay -= d1; // remaining delay
+ ipre = i; // previous entry
+ i = t_ctrl_lst[i].next; // index of next entry
+ d1 = t_ctrl_lst[i].delta; // next delay delta
+ }
+ } // insert new entry
+
+ p->next = i; // following entry
+ p->delta = delay; // store remaining delay
+ p->func = func;
+
+ if( i == t_first ){ // insert at first
+ t_first = n;
+ t_delay = delay;
+ }else{
+ t_ctrl_lst[ipre].next = n; // previous entry
+ }
+ return 0; // successful
+}
+
+
+uint8_t scheduler_task_remove( funcp func )
+{
+ uint8_t ipre; // previous index
+ uint8_t irem; // index to be removed
+ uint8_t ifol = t_first; // following index
+ t_ctrl_struct *p; // for faster access
+
+ do{
+ if( ifol == T_LAST )
+ return 1; // not found
+ ipre = irem;
+ irem = ifol;
+ p = &t_ctrl_lst[irem];
+ ifol = p->next; // get next
+ }while( p->func != func ); // found it
+
+ p->next = T_FREE; // mark it as free
+ if( irem == t_first ){
+ t_first = ifol; // serve next entry
+ t_delay += t_ctrl_lst[ifol].delta; // correct current delta
+ }else{
+ t_ctrl_lst[ipre].next = ifol; // skip index
+ if( ifol != T_LAST ) // correct following delta
+ t_ctrl_lst[ifol].delta += p->delta;
+ }
+ return 0; // successful
+}
+
+
+void scheduler_init(void)
+{
+ uint8_t i;
+
+ for( i = MAXTIMERS; i; i-- )
+ t_ctrl_lst[i-1].next = T_FREE; // mark all free
+ t_first = T_LAST; // set no timer served
+}
+
+
+uint32_t scheduler_tasklist( void)
+{
+ uint8_t i;
+
+ for( i = MAXTIMERS; i; i-- )
+ {
+ if ( t_ctrl_lst[i-1].next != T_FREE)
+ {
+ putint( i);
+ putstr(": func: ");
+ puthex( 32, t_ctrl_lst[i-1].func);
+ putchar('\n');
+ }
+ }
+
+ return 0;
+}
diff --git a/mig_test/software/schedule.h b/mig_test/software/schedule.h
new file mode 100644
index 0000000..cd9729d
--- /dev/null
+++ b/mig_test/software/schedule.h
@@ -0,0 +1,25 @@
+/*
+ * $HeadURL: https://svn.fzd.de/repo/concast/FWF_Projects/FWKE/hw_sp605/bsp_zpuahb/software/schedule.h $
+ * $Date$
+ * $Author$
+ * $Revision$
+ */
+
+
+#ifndef SCHEDULE_H
+#define SCHEDULE_H
+
+#define t_res uint32_t // resolution for time
+
+#define SECONDS(x) ((t_res)(CLOCKS_PER_SECOND * x + 0.5))
+
+
+typedef void (*funcp)(void);
+
+void scheduler_task_check(void);
+uint8_t scheduler_task_add( funcp func, t_res delay );
+uint8_t scheduler_task_remove( funcp func );
+void scheduler_init(void);
+uint32_t scheduler_tasklist( void);
+
+#endif // SCHEDULE_H
diff --git a/mig_test/synthesis/Makefile b/mig_test/synthesis/Makefile
index 14df7bc..89e3aed 100644
--- a/mig_test/synthesis/Makefile
+++ b/mig_test/synthesis/Makefile
@@ -1,8 +1,8 @@
#
# $HeadURL: https://svn.fzd.de/repo/concast/FWF_Projects/FWKE/beam_position_monitor/trunk/hardware/board_prototyp1/synthesis/Makefile $
-# $Date: 2014-05-23 15:16:41 +0200 (Fr, 23. Mai 2014) $
-# $Author: lange $
-# $Revision: 3192 $
+# $Date$
+# $Author$
+# $Revision$
#
MODULE = top
@@ -11,7 +11,7 @@ SPEEDGRADE = 2
PACKAGE = fgg484
UCF_FILE = top.ucf
CORES = ../cores/
-SOFTWARE = ../../../software
+SOFTWARE = ../software
BMM_FILE = zpu.bmm
BMM_BD_FILE = zpu_bd.bmm
@@ -79,8 +79,46 @@ run
-infer_ramb8 No
endef
+# 16k
+define BMM16
+ADDRESS_SPACE zpu_i0_memory
+ RAMB16 [0x00000000:0x00003fff]
+ BUS_BLOCK
+ box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram8 [31:28];
+ box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram7 [27:24];
+ box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram6 [23:20];
+ box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram5 [19:16];
+ box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram4 [15:12];
+ box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram3 [11: 8];
+ box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram2 [ 7: 4];
+ box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram1 [ 3: 0];
+ END_BUS_BLOCK;
+END_ADDRESS_SPACE;
+endef
+# 32k
define BMM
+ADDRESS_SPACE zpu_core_medium_i0_memory
+ RAMB16 [0x00000000:0x00007fff]
+ BUS_BLOCK
+ box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram16 [31:30];
+ box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram15 [29:28];
+ box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram14 [27:26];
+ box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram13 [25:24];
+ box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram12 [23:22];
+ box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram11 [21:20];
+ box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram10 [19:18];
+ box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram9 [17:16];
+ box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram8 [15:14];
+ box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram7 [13:12];
+ box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram6 [11:10];
+ box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram5 [ 9: 8];
+ box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram4 [ 7: 6];
+ box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram3 [ 5: 4];
+ box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram2 [ 3: 2];
+ box_i0/dualport_ram_ahb_wrapper_i0/dualport_ram_i0/Mram_ram1 [ 1: 0];
+ END_BUS_BLOCK;
+END_ADDRESS_SPACE;
endef
diff --git a/mig_test/synthesis/top.ucf b/mig_test/synthesis/top.ucf
index e8e0f8f..6223064 100644
--- a/mig_test/synthesis/top.ucf
+++ b/mig_test/synthesis/top.ucf
@@ -5,7 +5,7 @@ CONFIG VCCAUX = "2.5";
## system stuff
#125MHz clock
NET CLK LOC = AA12 | IOSTANDARD = LVCMOS33;
-NET RESET_N LOC = A4 | IOSTANDARD = LVCMOS33 | PULLDOWN;
+#NET RESET_N LOC = A4 | IOSTANDARD = LVCMOS33 | PULLDOWN;
NET POWER_FAIL_N LOC = A2; # IO_L83P_3
NET WATCHDOG LOC = V9 | IOSTANDARD = LVCMOS33; # WATCHDOG INPUT, IO_L50N_2
@@ -52,14 +52,14 @@ NET MCB1_DRAM_DQ<13> LOC = U22 | IOSTANDARD = SSTL15_II;
NET MCB1_DRAM_DQ<14> LOC = V21 | IOSTANDARD = SSTL15_II;
NET MCB1_DRAM_DQ<15> LOC = V22 | IOSTANDARD = SSTL15_II;
NET MCB1_DRAM_LDM LOC = L19 | IOSTANDARD = SSTL15_II;
-NET MCB1_DRAM_LDQS_N LOC = L22 | IOSTANDARD = SSTL15_II;
-NET MCB1_DRAM_LDQS_P LOC = L20 | IOSTANDARD = SSTL15_II;
+NET MCB1_DRAM_DQS_N<0> LOC = L22 | IOSTANDARD = SSTL15_II;
+NET MCB1_DRAM_DQS_P<0> LOC = L20 | IOSTANDARD = SSTL15_II;
NET MCB1_DRAM_ODT LOC = G22 | IOSTANDARD = SSTL15_II;
NET MCB1_DRAM_RAS_B LOC = H21 | IOSTANDARD = SSTL15_II;
NET MCB1_DRAM_RESET_B LOC = F18 | IOSTANDARD = SSTL15_II;
NET MCB1_DRAM_UDM LOC = M20 | IOSTANDARD = SSTL15_II;
-NET MCB1_DRAM_UDQS_N LOC = T22 | IOSTANDARD = SSTL15_II;
-NET MCB1_DRAM_UDQS_P LOC = T21 | IOSTANDARD = SSTL15_II;
+NET MCB1_DRAM_DQS_N<1> LOC = T22 | IOSTANDARD = SSTL15_II;
+NET MCB1_DRAM_DQS_P<1> LOC = T21 | IOSTANDARD = SSTL15_II;
NET MCB1_DRAM_WE_B LOC = H19 | IOSTANDARD = SSTL15_II;
#
NET MCB3_DRAM_A<0> LOC = H2 | IOSTANDARD = SSTL15_II;
@@ -101,14 +101,14 @@ NET MCB3_DRAM_DQ<13> LOC = U1 | IOSTANDARD = SSTL15_II;
NET MCB3_DRAM_DQ<14> LOC = V2 | IOSTANDARD = SSTL15_II;
NET MCB3_DRAM_DQ<15> LOC = V1 | IOSTANDARD = SSTL15_II;
NET MCB3_DRAM_LDM LOC = L4 | IOSTANDARD = SSTL15_II;
-NET MCB3_DRAM_LDQS_N LOC = L1 | IOSTANDARD = SSTL15_II;
-NET MCB3_DRAM_LDQS_P LOC = L3 | IOSTANDARD = SSTL15_II;
+NET MCB3_DRAM_DQS_N<0> LOC = L1 | IOSTANDARD = SSTL15_II;
+NET MCB3_DRAM_DQS_P<0> LOC = L3 | IOSTANDARD = SSTL15_II;
NET MCB3_DRAM_ODT LOC = J6 | IOSTANDARD = SSTL15_II;
NET MCB3_DRAM_RAS_B LOC = K5 | IOSTANDARD = SSTL15_II;
NET MCB3_DRAM_RESET_B LOC = C3 | IOSTANDARD = SSTL15_II;
NET MCB3_DRAM_UDM LOC = M3 | IOSTANDARD = SSTL15_II;
-NET MCB3_DRAM_UDQS_N LOC = T1 | IOSTANDARD = SSTL15_II;
-NET MCB3_DRAM_UDQS_P LOC = T2 | IOSTANDARD = SSTL15_II;
+NET MCB3_DRAM_DQS_N<1> LOC = T1 | IOSTANDARD = SSTL15_II;
+NET MCB3_DRAM_DQS_P<1> LOC = T2 | IOSTANDARD = SSTL15_II;
NET MCB3_DRAM_WE_B LOC = F2 | IOSTANDARD = SSTL15_II;
## Ethernet PHY
@@ -152,7 +152,7 @@ NET SPI_FLASH_IO<2> LOC = U14; # MISO2/wp_n
NET SPI_FLASH_IO<3> LOC = U13; # MISO3/hold_n
## EEPROM (48bit MAC address, DS2502-E48)
-NET MAC_DATA LOC = T11;
+NET MAC_DATA LOC = T11 | IOSTANDARD = LVCMOS33;
## B2B J1 user IO
NET B2B_B2_L57_N LOC = AB4;
@@ -196,7 +196,7 @@ NET B2B_B2_L8_P LOC = U17;
#
NET B2B_B2_L11_P LOC = V17;
NET B2B_B2_L11_N LOC = W17;
-NET B2B_B2_L6_P LOC = W18;
+NET B2B_B2_L6_P LOC = W18 | IOSTANDARD = LVCMOS33;
NET B2B_B2_L6_N LOC = Y18;
#
NET B2B_B2_L5_P LOC = Y19;
@@ -254,7 +254,7 @@ NET B2B_B1_L21_P LOC = K16;
NET B2B_B1_L61_P LOC = L17;
NET B2B_B1_L61_N LOC = K18;
#
-#NET B2B_B0_L1 LOC = A4; # used as reset_n
+NET B2B_B0_L1 LOC = A4; # used as reset_n
#
NET B2B_B0_L2_P LOC = C5;
NET B2B_B0_L2_N LOC = A5;
diff --git a/mig_test/vhdl_files.txt b/mig_test/vhdl_files.txt
index c19a027..693137b 100644
--- a/mig_test/vhdl_files.txt
+++ b/mig_test/vhdl_files.txt
@@ -1,2 +1,63 @@
work rtl/top.vhd
+work rtl/box.vhd
+work rtl/timestamp.vhd
work rtl_tb/top_tb.vhd
+
+grlib ../grlib/rtl/ahbctrl.vhd
+grlib ../grlib/rtl/amba.vhd
+grlib ../grlib/rtl/apbctrl.vhd
+grlib ../grlib/rtl/config.vhd
+grlib ../grlib/rtl/devices.vhd
+grlib ../grlib/rtl/stdlib.vhd
+grlib ../grlib/rtl/testlib.vhd
+grlib ../grlib/rtl/util.vhd
+grlib ../grlib/rtl/version.vhd
+grlib ../grlib/rtl_tb/stdio.vhd
+
+hzdr ../hzdr/rtl/devices_hzdr.vhd
+hzdr ../hzdr/rtl/component_package.vhd
+hzdr ../hzdr/rtl/debug_con_apb.vhd
+
+gaisler ../gaisler/rtl/ahbdpram.vhd
+gaisler ../gaisler/rtl/ahbram.vhd
+gaisler ../gaisler/rtl/apbuart.vhd
+gaisler ../gaisler/rtl/grgpio.vhd
+gaisler ../gaisler/rtl/uart.vhd
+gaisler ../gaisler/rtl/gptimer.vhd
+gaisler ../gaisler/rtl/misc.vhd
+gaisler ../gaisler/rtl/net.vhd
+gaisler ../gaisler/rtl/memctrl.vhd
+gaisler ../gaisler/rtl/memoryctrl.vhd
+gaisler ../gaisler/rtl_tb/sim.vhd
+gaisler ../gaisler/rtl/greth.vhd
+gaisler ../gaisler/rtl/ethernet_mac.vhd
+
+eth ../gaisler/rtl/greth_pkg.vhd
+eth ../gaisler/rtl/greth_rx.vhd
+eth ../gaisler/rtl/greth_tx.vhd
+eth ../gaisler/rtl/grethc.vhd
+eth ../gaisler/rtl/eth_ahb_mst.vhd
+eth ../gaisler/rtl/eth_rstgen.vhd
+eth ../gaisler/rtl/ethcomp.vhd
+
+techmap ../techmap/rtl/allmem.vhd
+techmap ../techmap/rtl/gencomp.vhd
+techmap ../techmap/rtl/memory_inferred.vhd
+techmap ../techmap/rtl/memory_unisim.vhd
+techmap ../techmap/rtl/syncram_2p.vhd
+techmap ../techmap/rtl/syncram_dp.vhd
+techmap ../techmap/rtl/syncrambw.vhd
+techmap ../techmap/rtl/syncram.vhd
+techmap ../techmap/rtl/netcomp.vhd
+
+zpu rtl/zpu_config.vhd
+zpu rtl/dualport_ram.vhd
+zpu ../zpu/rtl/dualport_ram_ahb_wrapper.vhd
+zpu ../zpu/rtl/zpu_ahb.vhd
+zpu ../zpu/rtl/zpu_bus_trace.vhd
+zpu ../zpu/rtl/zpu_core_medium.vhd
+zpu ../zpu/rtl/zpu_core_small.vhd
+zpu ../zpu/rtl/zpu_wrapper_package.vhd
+zpu ../zpu/rtl/zpupkg.vhd
+zpu ../zpu/rtl_tb/sim_small_fpga_top_noint.vhd
+zpu ../zpu/rtl_tb/txt_util.vhd
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