I'm also attaching another patch which removes unisim/roc dependency

(it was used just to pulse the areset) and fixes paths for building
the ghdl examples out of the box. I guess this is the easiest way to
get zpu running on linux with minimum effort.

You should check if the areset change doesn't break modelsim. It feels
much simpler this way and seems to work the same, i might be missing
something.

10 files changed, 63 insertions, 89 deletions

diff --git a/zpu/ChangeLog b/zpu/ChangeLog
index c5ab833..72c76c0 100644
--- a/zpu/ChangeLog
+++ b/zpu/ChangeLog
@@ -1,4 +1,17 @@
-2008-05-06 Miguel Freitas <mfreitas@gmail.com>

+2008-05-18 Miguel Freitas <mfreitas@gmail.com>

+

+	*

+I'm also attaching another patch which removes unisim/roc dependency

+(it was used just to pulse the areset) and fixes paths for building

+the ghdl examples out of the box. I guess this is the easiest way to

+get zpu running on linux with minimum effort.

+

+You should check if the areset change doesn't break modelsim. It feels

+much simpler this way and seems to work the same, i might be missing

+something.

+	

+	

+2008-05-16 Miguel Freitas <mfreitas@gmail.com>

 

 	* io.vhd: fix address comparsion and added numerous outputs

 	during simulation to make things a bit easier 

diff --git a/zpu/hdl/example/sim_small_fpga_top.vhd b/zpu/hdl/example/sim_small_fpga_top.vhd
index 2a7a9f5..0727bea 100644
--- a/zpu/hdl/example/sim_small_fpga_top.vhd
+++ b/zpu/hdl/example/sim_small_fpga_top.vhd
@@ -23,8 +23,8 @@ use ieee.numeric_std.all;
 

 ---- Uncomment the following library declaration if instantiating

 ---- any Xilinx primitives in this code.

-library UNISIM;

-use UNISIM.VComponents.all;

+--library UNISIM;

+--use UNISIM.VComponents.all;

 

 library work;

 use work.zpu_config.all;

@@ -38,7 +38,7 @@ architecture behave of fpga_top is
 

 signal clk : std_logic;

 

-signal	areset			: std_logic;

+signal	areset			: std_logic := '1';

 

 

 component  zpu_io is

@@ -97,9 +97,6 @@ signal			  interrupt : std_logic;
 signal break : std_logic;

 

 begin

-	poweronreset: roc port map (O => areset);

-

-

 

 	zpu: zpu_core port map (

 		clk => clk ,

@@ -188,6 +185,7 @@ begin
 		   wait for 5 ns; 

    			clk <= '1';

 		   wait for 5 ns; 

+		   areset <= '0';

 	end PROCESS clock;

 

 

diff --git a/zpu/hdl/example_ghdl/README b/zpu/hdl/example_ghdl/README
index c537284..a098c0c 100644
--- a/zpu/hdl/example_ghdl/README
+++ b/zpu/hdl/example_ghdl/README
@@ -4,46 +4,16 @@ the GHDL simulator.
   http://ghdl.free.fr/

 

 Compiled by Arnim Laeuger, 17-Apr-2008.

-

-

-Prerequisites

--------------

-

-The RTL source code references the ROC component from Xilinx' unisim

-library. If not already done, you'll have to prepare this library containing

-at least the roc entity and architecture objects.

-

-Decide where to store this library. This could be locally in this directory or

-at some central place where it can be referenced from other projects. I'd

-prefer the latter option.

-

-  $ cd <where unisim lib should be stored>

-

-Prepare the sources for GHDL:

-  $ mkdir src

-  $ cd src

-  $ ghdl --chop <WebPack installation dir>/vhdl/src/unisims/*

-  $ cd ..

-

-Import the sources into the library:

-  $ mkdir unisim_v93

-  $ ghdl -i --work=unisim --workdir=unisim_v93 --std=93 -fexplicit --no-vital-checks --ieee=synopsys src/*

-

-Compile the required component:

-  $ ghdl -m --syn-binding --work=unisim --workdir=unisim_v93 --std=93 -fexplicit --no-vital-checks --ieee=synopsys roc

-  $ rm roc

-    -> not required for library

-

-If you require more components from the unisim library for other projects, you

-can repeat the compile step later on without running through the preparation

-and import steps.

-

+Removed ROC/unisim dependency 16-Jun-2008.

 

 Compiling the example

 ---------------------

 

-Edit ghdl_options.sh and point the variable UNISIM_DIR to the location of your

-newly created unisim library.

+Make all shell scripts executable:

+  $ chmod +x *.sh

+

+On Linux, convert files from DOS format:

+  $ dos2unix *.sh

 

 You need to import the project sources once by running

   $ ./ghdl_import.sh

diff --git a/zpu/hdl/example_ghdl/dmipssmalltrace_ghdl.sh b/zpu/hdl/example_ghdl/dmipssmalltrace_ghdl.sh
index 5e43b64..b3be1a6 100644
--- a/zpu/hdl/example_ghdl/dmipssmalltrace_ghdl.sh
+++ b/zpu/hdl/example_ghdl/dmipssmalltrace_ghdl.sh
@@ -1,22 +1,20 @@
 #!/bin/sh

 

-UNISIM_DIR="'location of GHDL objects for unisim library'/unisim_v93"

-IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work -P${UNISIM_DIR}"

+IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work"

 MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding"

 

 if test ! -e work; then

     echo "Building work library..."

     mkdir work

-    ghdl -i ${IMPORT_OPTIONS} zpu_config_trace.vhd

-    ghdl -i ${IMPORT_OPTIONS} zpupkg.vhd

-    ghdl -i ${IMPORT_OPTIONS} txt_util.vhd

-    ghdl -i ${IMPORT_OPTIONS} sim_fpga_top.vhd

-    ghdl -i ${IMPORT_OPTIONS} zpu_core_small.vhd

-    ghdl -i ${IMPORT_OPTIONS} bram_dmips.vhd

-    ghdl -i ${IMPORT_OPTIONS} dram_dmips.vhd

-    ghdl -i ${IMPORT_OPTIONS} timer.vhd

-    ghdl -i ${IMPORT_OPTIONS} io.vhd

-    ghdl -i ${IMPORT_OPTIONS} trace.vhd

+    ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/zpu_config.vhd

+    ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpupkg.vhd

+    ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/txt_util.vhd

+    ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/sim_small_fpga_top.vhd

+    ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpu_core_small.vhd

+    ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/bram_dmips.vhd

+    ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/timer.vhd

+    ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/io.vhd

+    ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/trace.vhd

 fi

 

 echo "Compiling design..."

diff --git a/zpu/hdl/example_ghdl/dmipstrace_ghdl.sh b/zpu/hdl/example_ghdl/dmipstrace_ghdl.sh
index 3be392f..53474d4 100644
--- a/zpu/hdl/example_ghdl/dmipstrace_ghdl.sh
+++ b/zpu/hdl/example_ghdl/dmipstrace_ghdl.sh
@@ -1,21 +1,20 @@
 #!/bin/sh

 

-UNISIM_DIR="'location of GHDL objects for unisim library'/unisim_v93"

-IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work -P${UNISIM_DIR}"

+IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work"

 MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding"

 

 if test ! -e work; then

     echo "Building work library..."

     mkdir work

-    ghdl -i ${IMPORT_OPTIONS} zpu_config_trace.vhd

-    ghdl -i ${IMPORT_OPTIONS} zpupkg.vhd

-    ghdl -i ${IMPORT_OPTIONS} txt_util.vhd

-    ghdl -i ${IMPORT_OPTIONS} sim_fpga_top.vhd

-    ghdl -i ${IMPORT_OPTIONS} zpu_core.vhd

-    ghdl -i ${IMPORT_OPTIONS} dram_dmips.vhd

-    ghdl -i ${IMPORT_OPTIONS} timer.vhd

-    ghdl -i ${IMPORT_OPTIONS} io.vhd

-    ghdl -i ${IMPORT_OPTIONS} trace.vhd

+    ghdl -i ${IMPORT_OPTIONS} ../../hdl/example_medium/zpu_config_trace.vhd

+    ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpupkg.vhd

+    ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/txt_util.vhd

+    ghdl -i ${IMPORT_OPTIONS} ../../hdl/example_medium/sim_fpga_top.vhd

+    ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpu_core.vhd

+    ghdl -i ${IMPORT_OPTIONS} ../../hdl/example_medium/dram_dmips.vhd

+    ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/timer.vhd

+    ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/io.vhd

+    ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/trace.vhd

 fi

 

 echo "Compiling design..."

diff --git a/zpu/hdl/example_ghdl/ghdl_import.sh b/zpu/hdl/example_ghdl/ghdl_import.sh
index 299134b..a0ae61c 100644
--- a/zpu/hdl/example_ghdl/ghdl_import.sh
+++ b/zpu/hdl/example_ghdl/ghdl_import.sh
@@ -3,11 +3,11 @@
 

 mkdir -p work

 ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/zpu_config.vhd

-ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/zpupkg.vhd

+ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpupkg.vhd

 ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/helloworld.vhd

 ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/txt_util.vhd

 ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/trace.vhd

-ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/zpu_core_small.vhd

+ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpu_core_small.vhd

 ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/io.vhd

 ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/timer.vhd

-ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/sim_small_fpga_top.vhd

+ghdl -i ${IMPORT_OPTIONS} ../../hdl/example/sim_small_fpga_top.vhd

diff --git a/zpu/hdl/example_ghdl/ghdl_options.sh b/zpu/hdl/example_ghdl/ghdl_options.sh
index 3883ee7..aba231c 100644
--- a/zpu/hdl/example_ghdl/ghdl_options.sh
+++ b/zpu/hdl/example_ghdl/ghdl_options.sh
@@ -1,3 +1,2 @@
-UNISIM_DIR="'location of GHDL objects for unisim library'/unisim_v93"

-IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work -P${UNISIM_DIR}"

+IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work"

 MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding"

diff --git a/zpu/hdl/example_ghdl/simzpu_medium_ghdl.sh b/zpu/hdl/example_ghdl/simzpu_medium_ghdl.sh
index 7a7f3df..8ba5078 100644
--- a/zpu/hdl/example_ghdl/simzpu_medium_ghdl.sh
+++ b/zpu/hdl/example_ghdl/simzpu_medium_ghdl.sh
@@ -1,21 +1,20 @@
 #!/bin/sh

 

-UNISIM_DIR="'location of GHDL objects for unisim library'/unisim_v93"

-IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work -P${UNISIM_DIR}"

+IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work"

 MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding"

 

 if test ! -e work; then

     echo "Building work library..."

     mkdir work

-    ghdl -i ${IMPORT_OPTIONS} zpu_config_trace.vhd

-    ghdl -i ${IMPORT_OPTIONS} zpupkg.vhd

-    ghdl -i ${IMPORT_OPTIONS} txt_util.vhd

-    ghdl -i ${IMPORT_OPTIONS} sim_fpga_top.vhd

-    ghdl -i ${IMPORT_OPTIONS} zpu_core.vhd

-    ghdl -i ${IMPORT_OPTIONS} dram_hello.vhd

-    ghdl -i ${IMPORT_OPTIONS} timer.vhd

-    ghdl -i ${IMPORT_OPTIONS} io.vhd

-    ghdl -i ${IMPORT_OPTIONS} trace.vhd

+    ghdl -i ${IMPORT_OPTIONS} ../../hdl/example_medium/zpu_config_trace.vhd

+    ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpupkg.vhd

+    ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/txt_util.vhd

+    ghdl -i ${IMPORT_OPTIONS} ../../hdl/example_medium/sim_fpga_top.vhd

+    ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/core/zpu_core.vhd

+    ghdl -i ${IMPORT_OPTIONS} ../../hdl/example_medium/dram_hello.vhd

+    ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/timer.vhd

+    ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/io.vhd

+    ghdl -i ${IMPORT_OPTIONS} ../../hdl/zpu4/src/trace.vhd

 fi

 

 echo "Compiling design..."

diff --git a/zpu/hdl/example_medium/sim_fpga_top.vhd b/zpu/hdl/example_medium/sim_fpga_top.vhd
index 29151af..2191889 100644
--- a/zpu/hdl/example_medium/sim_fpga_top.vhd
+++ b/zpu/hdl/example_medium/sim_fpga_top.vhd
@@ -22,8 +22,8 @@ use IEEE.STD_LOGIC_1164.ALL;
 

 ---- Uncomment the following library declaration if instantiating

 ---- any Xilinx primitives in this code.

-library UNISIM;

-use UNISIM.VComponents.all;

+--library UNISIM;

+--use UNISIM.VComponents.all;

 

 library work;

 use work.zpu_config.all;

@@ -38,7 +38,7 @@ architecture behave of fpga_top is
 

 signal clk : std_logic;

 

-signal	areset			: std_logic;

+signal	areset			: std_logic := '1';

 

 

 component  zpu_io is

@@ -94,10 +94,6 @@ signal			  io_reading : std_logic;
 signal break : std_logic;

 

 begin

-	poweronreset: roc port map (O => areset);

-

-

-

 	zpu: zpu_core port map (

 		clk => clk ,

 	 	areset => areset,

@@ -182,6 +178,7 @@ begin
 		   wait for 5 ns; 

    			clk <= '1';

 		   wait for 5 ns; 

+		   areset <= '0';

 	end PROCESS clock;

 

 

diff --git a/zpu/hdl/zpu4/src/io.vhd b/zpu/hdl/zpu4/src/io.vhd
index f71f51d..e2576e2 100644
--- a/zpu/hdl/zpu4/src/io.vhd
+++ b/zpu/hdl/zpu4/src/io.vhd
@@ -54,6 +54,7 @@ begin
 	timer_we <= writeEnable and addr(12);

 	

 	process(areset, clk)

+	variable taddr  : std_logic_vector(maxAddrBit downto 0);

 	begin

 		taddr := (others => '0');

 		taddr(maxAddrBit downto minAddrBit) := addr;