diff options
| author | oharboe <oharboe> | 2008-04-17 06:42:27 +0000 |
|---|---|---|
| committer | oharboe <oharboe> | 2008-04-17 06:42:27 +0000 |
| commit | 748de9774226a19c32ee1ed6a4e6474e9e0acb27 (patch) | |
| tree | 1efbda55f9c7f6d89358024f2eabab3ff166f9d8 | |
| parent | af5b54efbbcbe6e80478ddb24ac2e95a33e63a2d (diff) | |
| download | zpu-748de9774226a19c32ee1ed6a4e6474e9e0acb27.zip zpu-748de9774226a19c32ee1ed6a4e6474e9e0acb27.tar.gz | |
* retired Xilinx synthesizing example. It messes up the zpu4 directory.
20 files changed, 2 insertions, 3588 deletions
diff --git a/zpu/ChangeLog b/zpu/ChangeLog index 3c432e8..9b722e8 100644 --- a/zpu/ChangeLog +++ b/zpu/ChangeLog @@ -1,3 +1,5 @@ +2008-04-17 Øyvind Harboe
+ * retired Xilinx synthesizing example. It messes up the zpu4 directory.
2008-04-16 Øyvind Harboe
* zpu/doc/zpupresentation_old.odt: interesting bits moved into zpu_arch.html
* zpu/doc/zpupresentation.*: interesting bits moved into zpu_arch.html
diff --git a/zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7pkg.vhd b/zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7pkg.vhd deleted file mode 100644 index 95fbc18..0000000 --- a/zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7pkg.vhd +++ /dev/null @@ -1,31 +0,0 @@ -library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-package arm7 is
-
- component arm7wb
- generic(
- simulate_io_time : boolean := false);
- port ( areset : in std_logic;
- cpu_clk : in std_logic;
- cpu_clk_2x : in std_logic;
- cpu_a_p : in std_logic_vector(20 downto 0);
- cpu_wr_n_p : in std_logic_vector(1 downto 0);
- cpu_cs_n_p : in std_logic_vector(3 downto 1);
- cpu_oe_n_p : in std_logic;
- cpu_d_p : inout std_logic_vector(15 downto 0);
- cpu_irq_p : out std_logic_vector(1 downto 0);
- cpu_fiq_p : out std_logic;
- cpu_wait_n_p : out std_logic;
-
- cpu_din : out std_logic_vector(15 downto 0);
- cpu_a : out std_logic_vector(20 downto 0);
- cpu_we : out std_logic_vector(1 downto 0);
- cpu_re : out std_logic;
- cpu_dout : in std_logic_vector(15 downto 0));
- end component;
-
-end arm7;
-
-
\ No newline at end of file diff --git a/zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7wb.vhd b/zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7wb.vhd deleted file mode 100644 index 55b8125..0000000 --- a/zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7wb.vhd +++ /dev/null @@ -1,213 +0,0 @@ -library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-entity arm7wb is
- generic(
- simulate_io_time : boolean := false);
- port ( areset : in std_logic;
- cpu_clk : in std_logic;
- cpu_clk_2x : in std_logic;
- cpu_a_p : in std_logic_vector(20 downto 0);
- cpu_wr_n_p : in std_logic_vector(1 downto 0);
- cpu_cs_n_p : in std_logic_vector(3 downto 1);
- cpu_oe_n_p : in std_logic;
- cpu_d_p : inout std_logic_vector(15 downto 0);
- cpu_irq_p : out std_logic_vector(1 downto 0);
- cpu_fiq_p : out std_logic;
- cpu_wait_n_p : out std_logic;
-
- cpu_din : out std_logic_vector(15 downto 0);
- cpu_a : out std_logic_vector(20 downto 0);
- cpu_we : out std_logic_vector(1 downto 0);
- cpu_re : out std_logic;
- cpu_dout : in std_logic_vector(15 downto 0));
-end arm7wb;
-
-architecture behave of arm7wb is
-
-attribute keep : string;
-
-signal cpu_oe_n : std_logic;
-signal cpu_fiq : std_logic;
-signal cpu_wait_n : std_logic;
-signal cpu_clk_toggle : std_logic;
-signal cpu_clk_smp1 : std_logic;
-signal cpu_clk_smp2 : std_logic;
-signal cpu_clk_phase : std_logic;
-signal cpu_oe_n_del : std_logic;
-signal cpu_a_smp : std_logic_vector(20 downto 0);
-signal cpu_d_smp : std_logic_vector(15 downto 0);
-
-signal int_oe_n : std_logic_vector(15 downto 0);
-attribute keep of int_oe_n:signal is "true";
-
-signal cpu_irq : std_logic_vector(1 downto 0);
-signal cpu_wr_n : std_logic_vector(1 downto 0);
-signal cpu_cs_n : std_logic_vector(3 downto 1);
-
-signal dout : std_logic_vector(15 downto 0);
-signal cpu_d_p_out : std_logic_vector(15 downto 0);
-signal read_cnt : std_logic_vector(1 downto 0);
-
-signal cpu_wr_n_p_del : std_logic_vector(1 downto 0);
-signal cpu_a_p_del : std_logic_vector(20 downto 0);
-signal cpu_d_p_del : std_logic_vector(15 downto 0);
-signal cpu_cs_n_p_del : std_logic_vector(3 downto 1);
-signal cpu_oe_n_p_del : std_logic;
-
-constant Sim_Delay : time := 0.5 ns;
-constant Clock_2_Out : time := 5.5 ns;
-constant Input_Setup : time := 2.5 ns;
-
-begin
-
- cpu_wait_n <= '1';
- cpu_fiq <= '1';
- cpu_irq <= "11";
-
- iotimingon:
- if simulate_io_time generate
- begin
- cpu_wr_n_p_del <= "XX" after 0 ns, cpu_wr_n_p after Input_Setup;
- cpu_a_p_del <= "XXXXXXXXXXXXXXXXXXXXX" after 0 ns, cpu_a_p after Input_Setup;
- cpu_d_p_del <= "XXXXXXXXXXXXXXXX" after 0 ns, cpu_d_p after Input_Setup;
- cpu_cs_n_p_del <= "XXX" after 0 ns, cpu_cs_n_p after Input_Setup;
- cpu_oe_n_p_del <= 'X' after 0 ns, cpu_oe_n_p after Input_Setup;
- end generate;
-
- iotimingoff:
- if not simulate_io_time generate
- begin
- cpu_wr_n_p_del <= cpu_wr_n_p;
- cpu_a_p_del <= cpu_a_p;
- cpu_d_p_del <= cpu_d_p;
- cpu_cs_n_p_del <= cpu_cs_n_p;
- cpu_oe_n_p_del <= cpu_oe_n_p;
- end generate;
-
- process(cpu_clk, areset) -- Toggle FF with 1x clock to find phase
- begin
- if areset = '1' then
- cpu_clk_toggle <= '0';
- elsif (cpu_clk'event and cpu_clk = '1') then
- cpu_clk_toggle <= not(cpu_clk_toggle);
- end if;
- end process;
-
- process(cpu_clk_2x, areset) -- Find phase relationsship between 1x and 2x clock
- begin
- if areset = '1' then
- cpu_clk_smp1 <= '0';
- cpu_clk_smp2 <= '1';
- cpu_clk_phase <= '0';
- elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
- cpu_clk_smp1 <= cpu_clk_toggle;
- cpu_clk_smp2 <= cpu_clk_smp1;
- if cpu_clk_smp1 = '1' and cpu_clk_smp2 = '0' then
- cpu_clk_phase <= '0' after Sim_Delay;
- else
- cpu_clk_phase <= not(cpu_clk_phase) after Sim_Delay;
- end if;
- end if;
- end process;
-
- process(cpu_clk_2x, areset) -- Sample input signals
- begin
- if areset = '1' then
- cpu_oe_n <= '1';
- cpu_a_smp <= "000000000000000000000";
- cpu_d_smp <= "0000000000000000";
- cpu_wr_n <= "11";
- cpu_cs_n <= "111";
- elsif (cpu_clk_2x = '1' and cpu_clk_2x'event) then
- cpu_oe_n <= cpu_oe_n_p_del after Sim_Delay;
- cpu_a_smp <= cpu_a_p_del after Sim_Delay;
- cpu_d_smp <= cpu_d_p_del after Sim_Delay;
- cpu_wr_n <= cpu_wr_n_p_del after Sim_Delay;
- cpu_cs_n <= cpu_cs_n_p_del after Sim_Delay;
- end if;
- end process;
-
- cpu_d_out:
- for i in 0 to 15 generate
- begin
- process(cpu_clk_2x, areset)
- begin
- if areset = '1' then
- cpu_d_p(i) <= 'Z';
- elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
- if int_oe_n(i) = '0' then
- cpu_d_p(i) <= cpu_d_p_out(i) after Clock_2_Out;
- else
- cpu_d_p(i) <= 'Z' after Clock_2_Out;
- end if;
- end if;
- end process;
- end generate;
-
- process(cpu_clk, areset) -- Clocked output pins
- begin
- if areset = '1' then
- cpu_d_p_out <= "1111111111111111";
- cpu_wait_n_p <= '1';
- cpu_irq_p <= "11";
- cpu_fiq_p <= '1';
- elsif (cpu_clk = '1' and cpu_clk'event) then
- cpu_d_p_out <= cpu_dout;
- cpu_wait_n_p <= '1';
- cpu_irq_p <= "11";
- cpu_fiq_p <= '1';
- end if;
- end process;
-
- process(cpu_clk, areset) -- Generate control signals
- begin
- if areset = '1' then
- int_oe_n <= "1111111111111111";
- read_cnt <= "00";
- cpu_we <= "00";
- cpu_re <= '0';
- cpu_a <= "000000000000000000000";
- cpu_din <= "0000000000000000";
- elsif (cpu_clk = '1' and cpu_clk'event) then
-
- cpu_a <= cpu_a_smp;
- cpu_din <= cpu_d_smp;
-
- cpu_oe_n_del <= cpu_oe_n;
-
- if cpu_cs_n(1) = '1' then
- read_cnt <= "00";
- else
- read_cnt <= read_cnt + '1';
- end if;
-
- if read_cnt = "01" and cpu_cs_n(1) = '0' and cpu_wr_n(0) = '0' then
- cpu_we(0) <= '1';
- else
- cpu_we(0) <= '0';
- end if;
-
- if read_cnt = "01" and cpu_cs_n(1) = '0' and cpu_wr_n(1) = '0' then
- cpu_we(1) <= '1';
- else
- cpu_we(1) <= '0';
- end if;
-
- if read_cnt = "00" and cpu_cs_n(1) = '0' and cpu_oe_n = '0' then
- cpu_re <= '1';
- else
- cpu_re <= '0';
- end if;
-
- if read_cnt = "01" and cpu_cs_n(1) = '0' and cpu_oe_n = '0' then
- int_oe_n <= "0000000000000000";
- else
- int_oe_n <= "1111111111111111";
- end if;
-
- end if;
- end process;
-
-end behave;
diff --git a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_tb.do b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_tb.do deleted file mode 100644 index d2c22cf..0000000 --- a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_tb.do +++ /dev/null @@ -1,17 +0,0 @@ -vlib zylin
-vcom -93 -explicit -work zylin ../ddrsdram/src/ddr_pkg.vhd
-vcom -93 -explicit -work zylin ../ddrsdram/src/ddr_top.vhd
-vcom -93 -explicit -work zylin ../ddrsdram/src/mt46v16m16.vhd
-vcom -93 -explicit -work zylin ../ddrsdram/src/ddr_tb.vhd
-vlib work
-vsim -t 1ps zylin.ddr_tb
-view wave
-view signals
-radix hex
-add wave *
-add wave sim:/ddr_tb/ddr_ctrl/*
-force -freeze sim:/ddr_tb/areset 1 0
-run 10 ns
-force -freeze sim:/ddr_tb/areset 0 0
-when sim:/ddr_tb/break_out stop
-run 10 ms
\ No newline at end of file diff --git a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_top.do b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_top.do deleted file mode 100644 index 31dd294..0000000 --- a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_top.do +++ /dev/null @@ -1,111 +0,0 @@ -vlib zylin
-vcom -93 -explicit -work zylin ../ddrsdram/src/ddr_pkg.vhd
-vcom -93 -explicit -work zylin ../ddrsdram/src/ddr_top.vhd
-vlib work
-vsim -t 1ps zylin.ddr_top
-view wave
-view signals
-radix hex
-# Add wave signals
-
-add wave -divider "System"
-add wave sim:/ddr_top/areset
-add wave sim:/ddr_top/cpu_clk
-add wave sim:/ddr_top/cpu_clk_2x
-add wave sim:/ddr_top/cpu_clk_4x
-add wave sim:/ddr_top/ddr_in_clk
-add wave sim:/ddr_top/ddr_in_clk_2x
-
-add wave -divider "Ctrl interface"
-add wave sim:/ddr_top/cpu_clk
-add wave sim:/ddr_top/ddr_data_read
-add wave sim:/ddr_top/ddr_data_write
-add wave sim:/ddr_top/ddr_req
-add wave sim:/ddr_top/ddr_rd_wr_n
-add wave sim:/ddr_top/ddr_req_len
-add wave sim:/ddr_top/ddr_wr_mask
-add wave sim:/ddr_top/ddr_read_en
-add wave sim:/ddr_top/ddr_write_en
-add wave sim:/ddr_top/ddr_command
-add wave sim:/ddr_top/ddr_command_we
-
-add wave -divider "DDR interface"
-add wave sim:/ddr_top/sdr_clk_p
-add wave sim:/ddr_top/sdr_clk_n_p
-add wave sim:/ddr_top/cke_q_p
-add wave sim:/ddr_top/cs_qn_p
-add wave sim:/ddr_top/ras_qn_p
-add wave sim:/ddr_top/cas_qn_p
-add wave sim:/ddr_top/we_qn_p
-add wave sim:/ddr_top/dm_q_p
-add wave sim:/ddr_top/dqs_q_p
-add wave sim:/ddr_top/ba_q_p
-add wave sim:/ddr_top/sdr_a_p
-add wave sim:/ddr_top/sdr_d_p
-
-add wave -divider "Internal signals"
-add wave sim:/ddr_top/clk2_phase
-add wave sim:/ddr_top/clk4_phase
-add wave sim:/ddr_top/ddr_state
-add wave sim:/ddr_top/sdr_oe_n
-add wave sim:/ddr_top/sdr_smp
-add wave sim:/ddr_top/sdr_d
-
-
-# Add input signals
-force -freeze sim:/ddr_top/cpu_clk_4x 1 0, 0 {1.875 ns} -r 3.75
-run 100 ps
-force -freeze sim:/ddr_top/cpu_clk_2x 1 0, 0 {3.75 ns} -r 7.5
-run 100 ps
-force -freeze sim:/ddr_top/cpu_clk 1 0, 0 {7.5 ns} -r 15
-force -freeze sim:/ddr_top/ddr_in_clk 1 2ns, 0 {5.75 ns} -r 7.5
-force -freeze sim:/ddr_top/ddr_in_clk_2x 0 0.125ns, 1 {2 ns} -r 3.75
-
-force -freeze sim:/ddr_top/areset 1 0
-force -freeze sim:/ddr_top/ddr_command 0000 0
-force -freeze sim:/ddr_top/ddr_command_we 0 0
-force -freeze sim:/ddr_top/ddr_data_write 1234abcd 0
-force -freeze sim:/ddr_top/ddr_req 0 0
-force -freeze sim:/ddr_top/ddr_req_adr 000000 0
-force -freeze sim:/ddr_top/ddr_rd_wr_n 0 0
-force -freeze sim:/ddr_top/ddr_req_len 000 0
-force -freeze sim:/ddr_top/ddr_wr_mask 0 0
-
-# Start simulation
-run 45
-force -freeze sim:/ddr_top/areset 0 0
-run 92
-# DDR Command
-force -freeze sim:/ddr_top/ddr_command 000A 0
-force -freeze sim:/ddr_top/ddr_command_we 1 0
-run 15
-force -freeze sim:/ddr_top/ddr_command 0000 0
-force -freeze sim:/ddr_top/ddr_command_we 0 0
-run 90
-# DDR Read
-force -freeze sim:/ddr_top/ddr_req 1 0
-force -freeze sim:/ddr_top/ddr_req_adr 00ABCD 0
-force -freeze sim:/ddr_top/ddr_rd_wr_n 1 0
-force -freeze sim:/ddr_top/ddr_req_len 000 0
-force -freeze sim:/ddr_top/ddr_wr_mask 0 0
-run 15
-force -freeze sim:/ddr_top/ddr_req 0 0
-force -freeze sim:/ddr_top/ddr_req_adr 000000 0
-force -freeze sim:/ddr_top/ddr_rd_wr_n 0 0
-force -freeze sim:/ddr_top/ddr_req_len 000 0
-force -freeze sim:/ddr_top/ddr_wr_mask 0 0
-run 150
-# DDR Write
-force -freeze sim:/ddr_top/ddr_req 1 0
-force -freeze sim:/ddr_top/ddr_req_adr 00ABCD 0
-force -freeze sim:/ddr_top/ddr_rd_wr_n 0 0
-force -freeze sim:/ddr_top/ddr_req_len 000 0
-force -freeze sim:/ddr_top/ddr_wr_mask 0 0
-run 15
-force -freeze sim:/ddr_top/ddr_req 0 0
-force -freeze sim:/ddr_top/ddr_req_adr 000000 0
-force -freeze sim:/ddr_top/ddr_rd_wr_n 0 0
-force -freeze sim:/ddr_top/ddr_req_len 000 0
-force -freeze sim:/ddr_top/ddr_wr_mask 0 0
-run 180
-
diff --git a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_pkg.vhd b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_pkg.vhd deleted file mode 100644 index 95f4b8a..0000000 --- a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_pkg.vhd +++ /dev/null @@ -1,90 +0,0 @@ -library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-package ddr is
-
- component ddr_top
- generic(
- simulate_io_time : boolean := false);
- port ( -- Asyncronous reset and clocks
- areset : in std_logic;
- cpu_clk : in std_logic;
- cpu_clk_2x : in std_logic;
- cpu_clk_4x : in std_logic;
- ddr_in_clk : in std_logic;
- ddr_in_clk_2x : in std_logic;
-
- -- Command interface
- ddr_command : in std_logic_vector(15 downto 0);
- ddr_command_we : in std_logic;
- refresh_en : in std_logic;
-
-
- -- Data interface signals
- ddr_data_read : out std_logic_vector(31 downto 0); -- Data read from DDR SDRAM
- ddr_data_write : in std_logic_vector(35 downto 0); -- Data to be written to DDR SDRAM
- ddr_req_adr : in std_logic_vector(23 downto 1); -- Request address
- ddr_req : in std_logic; -- Request DDR SDRAM access
- ddr_req_ack : out std_logic; -- Request acknowledge
- ddr_busy : out std_logic; -- Request acknowledge
- ddr_rd_wr_n : in std_logic; -- Access type 1=READ, 0=WRITE
- ddr_req_len : in std_logic; -- Number of 16-bits words to transfer (0=2, 1=8)
- ddr_read_en : out std_logic; -- Enable signal for read data
- ddr_write_en : out std_logic; -- Enable (read) signal for data write
-
- -- DDR SDRAM Signals
- sdr_clk_p : out std_logic; -- ddr_sdram_clock
- sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock
- cke_q_p : out std_logic; -- clock enable
- cs_qn_p : out std_logic; -- /chip select
- ras_qn_p : inout std_logic; -- /ras
- cas_qn_p : inout std_logic; -- /cas
- we_qn_p : inout std_logic; -- /write enable
- dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00"
- dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write
- ba_q_p : out std_logic_vector(1 downto 0); -- bank select
- sdr_a_p : out std_logic_vector(12 downto 0); -- address bus
- sdr_d_p : inout std_logic_vector(15 downto 0)); -- bidir data bus
- end component;
-
- component MT46V16M16
- GENERIC ( -- Timing for -75Z CL2
- tCK : TIME := 7.500 ns;
- tCH : TIME := 3.375 ns; -- 0.45*tCK
- tCL : TIME := 3.375 ns; -- 0.45*tCK
- tDH : TIME := 0.500 ns;
- tDS : TIME := 0.500 ns;
- tIH : TIME := 0.900 ns;
- tIS : TIME := 0.900 ns;
- tMRD : TIME := 15.000 ns;
- tRAS : TIME := 40.000 ns;
- tRAP : TIME := 20.000 ns;
- tRC : TIME := 65.000 ns;
- tRFC : TIME := 75.000 ns;
- tRCD : TIME := 20.000 ns;
- tRP : TIME := 20.000 ns;
- tRRD : TIME := 15.000 ns;
- tWR : TIME := 15.000 ns;
- addr_bits : INTEGER := 13;
- data_bits : INTEGER := 16;
- cols_bits : INTEGER := 9
- );
- PORT (
- Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
- Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
- Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
- Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
- Clk : IN STD_LOGIC;
- Clk_n : IN STD_LOGIC;
- Cke : IN STD_LOGIC;
- Cs_n : IN STD_LOGIC;
- Ras_n : IN STD_LOGIC;
- Cas_n : IN STD_LOGIC;
- We_n : IN STD_LOGIC;
- Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
- );
- end component;
-
-end ddr;
-
\ No newline at end of file diff --git a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_tb.vhd b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_tb.vhd deleted file mode 100644 index 5666532..0000000 --- a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_tb.vhd +++ /dev/null @@ -1,301 +0,0 @@ -library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-library zylin;
-use zylin.ddr.all;
-
-entity ddr_tb is
- port ( areset : in std_logic;
- break_out : out std_logic);
-end ddr_tb;
-
-architecture behave of ddr_tb is
-
-signal cpu_clk : std_logic;
-signal cpu_clk_2x : std_logic;
-signal cpu_clk_4x : std_logic;
-signal ddr_in_clk : std_logic;
-signal ddr_in_clk_2x : std_logic;
-
-signal ddr_command : std_logic_vector(15 downto 0);
-signal ddr_command_we : std_logic;
-
-signal ddr_data_read : std_logic_vector(31 downto 0); -- Data read from DDR SDRAM
-signal ddr_data_write : std_logic_vector(35 downto 0); -- Data to be written to DDR SDRAM
-signal ddr_req_adr : std_logic_vector(23 downto 1); -- Request address
-signal ddr_req : std_logic; -- Request DDR SDRAM access
-signal ddr_req_ack : std_logic; -- Request acknowledge
-signal ddr_busy : std_logic; -- Request acknowledge
-signal ddr_rd_wr_n : std_logic; -- Access type 1=READ, 0=WRITE
-signal ddr_req_len : std_logic; -- Number of 16-bits words to transfer
-signal ddr_read_en : std_logic; -- Enable signal for read data
-signal ddr_write_en : std_logic; -- Enable (read) signal for data write
-signal refresh_en : std_logic;
-
-signal sdr_clk_p : std_logic; -- ddr_sdram_clock
-signal sdr_clk_n_p : std_logic; -- /ddr_sdram_clock
-signal cke_q_p : std_logic; -- clock enable
-signal cs_qn_p : std_logic; -- /chip select
-signal ras_qn_p : std_logic; -- /ras
-signal cas_qn_p : std_logic; -- /cas
-signal we_qn_p : std_logic; -- /write enable
-signal dm_q_p : std_logic_vector(1 downto 0); -- data mask bits, set to "00"
-signal dqs_q_p : std_logic_vector(1 downto 0); -- data strobe, only for write
-signal ba_q_p : std_logic_vector(1 downto 0); -- bank select
-signal sdr_a_p : std_logic_vector(12 downto 0); -- address bus
-signal sdr_d_p : std_logic_vector(15 downto 0); -- bidir data bus
-
-constant min_time : time := 1.875 ns;
-
-begin
-
- clock1:
- process
- begin
- loop
- cpu_clk_4x <= '1';
- wait for min_time;
- cpu_clk_4x <= '0';
- wait for min_time;
- end loop;
- end process;
-
- clock2:
- process
- begin
- loop
- cpu_clk_2x <= '1' after 100 ps;
- wait until rising_edge(cpu_clk_4x);
- cpu_clk_2x <= '0' after 100 ps;
- wait until rising_edge(cpu_clk_4x);
- end loop;
- end process;
-
- clock3:
- process
- begin
- loop
- cpu_clk <= '1' after 100 ps;
- wait until rising_edge(cpu_clk_2x);
- cpu_clk <= '0' after 100 ps;
- wait until rising_edge(cpu_clk_2x);
- end loop;
- end process;
-
- ddr_in_clk_2x <= cpu_clk_4x after 1 ns;
-
- clock4:
- process
- begin
- loop
- ddr_in_clk <= '0' after 100 ps;
- wait until rising_edge(ddr_in_clk_2x);
- ddr_in_clk <= '1' after 100 ps;
- wait until rising_edge(ddr_in_clk_2x);
- end loop;
- end process;
-
- inputdata:
- process
- begin
- -- Wait until global reset released
- loop
- ddr_command <= x"0000";
- ddr_command_we <= '0';
- ddr_data_write <= x"000000000";
- ddr_req <= '0';
- ddr_req_adr <= "00000000000000000000000";
- ddr_rd_wr_n <= '0';
- ddr_req_len <= '0';
- break_out <= '0';
- refresh_en <= '0';
-
- wait until falling_edge(areset);
-
- -- DDR initialization sequence
- -- Wait more than 200 us
- wait for 201000 ns;
-
- -- Send precharge command
- wait until rising_edge(cpu_clk);
- ddr_command <= x"8000";
- ddr_command_we <= '1';
- wait until rising_edge(cpu_clk);
- ddr_command <= x"0000";
- ddr_command_we <= '0';
-
- -- Wait for 1 us
- wait for 1000 ns;
-
- -- Load extended mode register
- -- Enable DLL
- -- Normal drive strength
- wait until rising_edge(cpu_clk);
- ddr_command <= x"2000";
- ddr_command_we <= '1';
- wait until rising_edge(cpu_clk);
- ddr_command <= x"0000";
- ddr_command_we <= '0';
-
- -- Wait for 1 us
- wait for 1000 ns;
-
- -- Load mode register
- -- Burst length: 2
- -- Burst type: Sequential
- -- Cas latency: 2
- -- Reset DLL
- wait until rising_edge(cpu_clk);
- ddr_command <= x"0121";
- ddr_command_we <= '1';
- wait until rising_edge(cpu_clk);
- ddr_command <= x"0000";
- ddr_command_we <= '0';
-
- -- Wait for 1 us
- wait for 1000 ns;
-
- -- Send precharge command
- wait until rising_edge(cpu_clk);
- ddr_command <= x"8000";
- ddr_command_we <= '1';
- wait until rising_edge(cpu_clk);
- ddr_command <= x"0000";
- ddr_command_we <= '0';
-
- -- Enable refresh
- refresh_en <= '1';
-
- -- Wait 30 us (minimum 2 autorefresh cycles)
- wait for 30000 ns;
-
- -- Load mode register
- -- Burst length: 2
- -- Burst type: Sequential
- -- Cas latency: 2
- -- Deactivate Reset DLL
- wait until rising_edge(cpu_clk);
- ddr_command <= x"0021";
- ddr_command_we <= '1';
- wait until rising_edge(cpu_clk);
- ddr_command <= x"0000";
- ddr_command_we <= '0';
-
- -- Wait for 2 us (DLL stable)
- wait for 2000 ns;
-
- -- Write data to DDR
- wait until rising_edge(cpu_clk_2x);
- ddr_data_write <= x"312345678";
- ddr_req <= '1';
- ddr_req_adr <= "00000000000000000000000";
- ddr_rd_wr_n <= '0';
- ddr_req_len <= '0';
- wait until rising_edge(ddr_write_en);
- wait until rising_edge(cpu_clk_2x);
- ddr_req <= '0';
- ddr_req_adr <= "00000000000000000000000";
- ddr_rd_wr_n <= '0';
- ddr_req_len <= '0';
- ddr_data_write <= x"000000000";
- wait for 100 ns;
-
- -- Read data from DDR
- wait until rising_edge(cpu_clk_2x);
- ddr_req <= '1';
- ddr_req_adr <= "00000000000000000000000";
- ddr_rd_wr_n <= '1';
- ddr_req_len <= '0';
- wait until rising_edge(ddr_req_ack);
- wait until rising_edge(cpu_clk_2x);
- ddr_req <= '0';
- ddr_req_adr <= "00000000000000000000000";
- ddr_rd_wr_n <= '0';
- ddr_req_len <= '0';
- ddr_data_write <= x"000000000";
-
-
-
- wait for 100 ns;
- break_out <= '1';
- wait for 100 ns;
-
- end loop;
-
- end process;
-
- ddr_ctrl:
- ddr_top port map(
- areset => areset,
- cpu_clk => cpu_clk,
- cpu_clk_2x => cpu_clk_2x,
- cpu_clk_4x => cpu_clk_4x,
- ddr_in_clk => ddr_in_clk,
- ddr_in_clk_2x => ddr_in_clk_2x,
-
- -- Command interface
- ddr_command => ddr_command,
- ddr_command_we => ddr_command_we,
- refresh_en => refresh_en,
-
- -- Data interface signals
- ddr_data_read => ddr_data_read,
- ddr_data_write => ddr_data_write,
- ddr_req_adr => ddr_req_adr,
- ddr_req => ddr_req,
- ddr_req_ack => ddr_req_ack,
- ddr_busy => ddr_busy,
- ddr_rd_wr_n => ddr_rd_wr_n,
- ddr_req_len => ddr_req_len,
- ddr_read_en => ddr_read_en,
- ddr_write_en => ddr_write_en,
- -- DDR SDRAM Signals
- sdr_clk_p => sdr_clk_p,
- sdr_clk_n_p => sdr_clk_n_p,
- cke_q_p => cke_q_p,
- cs_qn_p => cs_qn_p,
- ras_qn_p => ras_qn_p,
- cas_qn_p => cas_qn_p,
- we_qn_p => we_qn_p,
- dm_q_p => dm_q_p,
- dqs_q_p => dqs_q_p,
- ba_q_p => ba_q_p,
- sdr_a_p => sdr_a_p,
- sdr_d_p => sdr_d_p);
-
- myram:
- MT46V16M16 generic map(
- tCK => 7.500 ns,
- tCH => 3.375 ns, -- 0.45*tCK
- tCL => 3.375 ns, -- 0.45*tCK
- tDH => 0.500 ns,
- tDS => 0.500 ns,
- tIH => 0.900 ns,
- tIS => 0.900 ns,
- tMRD => 15.000 ns,
- tRAS => 40.000 ns,
- tRAP => 20.000 ns,
- tRC => 65.000 ns,
- tRFC => 75.000 ns,
- tRCD => 20.000 ns,
- tRP => 20.000 ns,
- tRRD => 15.000 ns,
- tWR => 15.000 ns,
- addr_bits => 13,
- data_bits => 16,
- cols_bits => 9)
- port map(
- Dq => sdr_d_p,
- Dqs => dqs_q_p,
- Addr => sdr_a_p,
- Ba => ba_q_p,
- Clk => sdr_clk_p,
- Clk_n => sdr_clk_n_p,
- Cke => cke_q_p,
- Cs_n => cs_qn_p,
- Ras_n => ras_qn_p,
- Cas_n => cas_qn_p,
- We_n => we_qn_p,
- Dm => dm_q_p);
-
-end behave;
diff --git a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_top.vhd b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_top.vhd deleted file mode 100644 index d5e98e1..0000000 --- a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_top.vhd +++ /dev/null @@ -1,660 +0,0 @@ -library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-entity ddr_top is
- generic(
- simulate_io_time : boolean := false);
- port ( -- Asyncronous reset and clocks
- areset : in std_logic;
- cpu_clk : in std_logic;
- cpu_clk_2x : in std_logic;
- cpu_clk_4x : in std_logic;
- ddr_in_clk : in std_logic;
- ddr_in_clk_2x : in std_logic;
-
- -- Command interface
- ddr_command : in std_logic_vector(15 downto 0);
- ddr_command_we : in std_logic;
- refresh_en : in std_logic;
-
- -- Data interface signals
- ddr_data_read : out std_logic_vector(31 downto 0); -- Data read from DDR SDRAM
- ddr_data_write : in std_logic_vector(35 downto 0); -- Data to be written to DDR SDRAM
- ddr_req_adr : in std_logic_vector(23 downto 1); -- Request address
- ddr_req : in std_logic; -- Request DDR SDRAM access
- ddr_req_ack : out std_logic; -- Request acknowledge
- ddr_busy : out std_logic; -- Request acknowledge
- ddr_rd_wr_n : in std_logic; -- Access type 1=READ, 0=WRITE
- ddr_req_len : in std_logic; -- Number of 16-bits words to transfer (0=2, 1=8)
- ddr_read_en : out std_logic; -- Enable signal for read data
- ddr_write_en : out std_logic; -- Enable (read) signal for data write
-
- -- DDR SDRAM Signals
- sdr_clk_p : out std_logic; -- ddr_sdram_clock
- sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock
- cke_q_p : out std_logic; -- clock enable
- cs_qn_p : out std_logic; -- /chip select
- ras_qn_p : inout std_logic; -- /ras
- cas_qn_p : inout std_logic; -- /cas
- we_qn_p : inout std_logic; -- /write enable
- dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00"
- dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write
- ba_q_p : out std_logic_vector(1 downto 0); -- bank select
- sdr_a_p : out std_logic_vector(12 downto 0); -- address bus
- sdr_d_p : inout std_logic_vector(15 downto 0)); -- bidir data bus
-end ddr_top;
-
-architecture behave of ddr_top is
-
-attribute keep : string;
-
-signal cpu_clk_tog : std_logic;
-signal ddr_cmd : std_logic_vector(15 downto 0);
-signal ddr_cmd_we_smp : std_logic;
-signal new_command : std_logic;
-
-signal cpu_clk_2x_smp1 : std_logic;
-signal cpu_clk_2x_smp2 : std_logic;
-signal cpu_clk_4x_smp1 : std_logic;
-signal cpu_clk_4x_smp2 : std_logic;
-
-signal clk2_phase : std_logic;
-signal clk4_phase : std_logic_vector(3 downto 0);
-signal clk4_phase_short : std_logic_vector(1 downto 0);
-
-signal ddr_clk_tog : std_logic;
-signal ddr_clk_smp1 : std_logic;
-signal ddr_clk_smp2 : std_logic;
-signal ddr_clk_phase : std_logic;
-
-signal smp_req_adr : std_logic_vector(23 downto 1);
-signal smp_req_type : std_logic;
-signal smp_req_len : std_logic;
-signal ddr_write_en_int : std_logic;
-signal ddr_read_en_int : std_logic;
-
-signal dqs_q : std_logic_vector(1 downto 0);
-signal dqs_oe_n : std_logic_vector(1 downto 0);
-attribute keep of dqs_oe_n:signal is "true";
-signal cas_qn : std_logic;
-signal ras_qn : std_logic;
-signal we_qn : std_logic;
-signal ba_q : std_logic_vector(1 downto 0);
-signal sdr_clk : std_logic;
-signal sdr_clk_n : std_logic;
-signal sdr_a : std_logic_vector(12 downto 0);
-signal sdr_d : std_logic_vector(15 downto 0);
-signal sdr_smp : std_logic_vector(35 downto 0);
-signal sdr_oe_n : std_logic_vector(15 downto 0);
-attribute keep of sdr_oe_n:signal is "true";
-signal sdr_oe_ctrl : std_logic;
-signal sdr_wr_msw : std_logic_vector(17 downto 0);
-attribute keep of sdr_wr_msw:signal is "true";
-signal dm_q : std_logic_vector(1 downto 0);
-
-signal cas_n_smp : std_logic;
-signal ras_n_smp : std_logic;
-signal we_n_smp : std_logic;
-signal read_start_sig : std_logic;
-signal sdr_d_in : std_logic_vector(15 downto 0);
-signal read_time_cnt : std_logic_vector(1 downto 0);
-signal read_input_en : std_logic;
-signal ddr_data_read_int : std_logic_vector(31 downto 0);
-
-signal refresh_pend : std_logic;
-signal refresh_end : std_logic;
-signal refresh_cnt : std_logic_vector(9 downto 0);
-signal refresh_wait_cnt : std_logic_vector(2 downto 0);
-signal refresh_wait_end : std_logic;
-
-signal cas_qn_p_del : std_logic;
-signal ras_qn_p_del : std_logic;
-signal we_qn_p_del : std_logic;
-signal sdr_d_p_del : std_logic_vector(15 downto 0);
-
-type state_type is (idle, act, act_nop1, act_nop2, rd_wr, rd_nop1,
- rd_nop2, pre, pre_nop1, pre_nop2, wr_nop1, wr_nop2,
- wr_nop3, cmd, cpu_pre, refresh, refresh_wait);
-signal ddr_state : state_type;
-
-constant Clk_to_Output : time := 2.2 ns;
-constant Sim_Delay : time := 0.5 ns;
-constant Input_Setup : time := 2.5 ns;
-
-constant Refresh_Interval : std_logic_vector(9 downto 0) := "1111100110";
-
-begin
-
- iotimingon:
- if simulate_io_time generate
- begin
- cas_qn_p_del <= 'X' after 0 ns, cas_qn_p after Input_Setup;
- ras_qn_p_del <= 'X' after 0 ns, ras_qn_p after Input_Setup;
- we_qn_p_del <= 'X' after 0 ns, we_qn_p after Input_Setup;
- sdr_d_p_del <= "XXXXXXXXXXXXXXXX" after 0 ns, sdr_d_p after Input_Setup;
- end generate;
-
- iotimingoff:
- if not simulate_io_time generate
- begin
- cas_qn_p_del <= cas_qn_p;
- ras_qn_p_del <= ras_qn_p;
- we_qn_p_del <= we_qn_p;
- sdr_d_p_del <= sdr_d_p;
- end generate;
-
- ddr_write_en <= ddr_write_en_int;
- ddr_read_en <= ddr_read_en_int;
- ddr_data_read <= ddr_data_read_int;
-
- process(cpu_clk, areset) -- Toggle a flip-flop with cpu_clk, in order
- begin -- to find phase relation with 2x and 4x clocks
- if areset = '1' then
- cpu_clk_tog <= '0';
- elsif (cpu_clk'event and cpu_clk = '1') then
- cpu_clk_tog <= not(cpu_clk_tog) after Sim_Delay;
- end if;
- end process;
-
- process(cpu_clk_2x, areset) -- Find phase relation between cpu_clk and cpu_clk_2x
- begin
- if areset = '1' then
- cpu_clk_2x_smp1 <= '0';
- cpu_clk_2x_smp2 <= '0';
- clk2_phase <= '0';
- elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
- cpu_clk_2x_smp1 <= cpu_clk_tog after Sim_Delay;
- cpu_clk_2x_smp2 <= cpu_clk_2x_smp1 after Sim_Delay;
- if (cpu_clk_2x_smp1 = '1' and cpu_clk_2x_smp2 = '0') then
- clk2_phase <= '0' after Sim_Delay;
- else
- clk2_phase <= not(clk2_phase) after Sim_Delay;
- end if;
- end if;
- end process;
-
- process(cpu_clk_4x, areset) -- Find phase relation between cpu_clk and cpu_clk_4x
- begin
- if areset = '1' then
- cpu_clk_4x_smp1 <= '0';
- cpu_clk_4x_smp2 <= '0';
- clk4_phase <= "0000";
- clk4_phase_short <= "00";
- elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then
- cpu_clk_4x_smp1 <= cpu_clk_tog after Sim_Delay;
- cpu_clk_4x_smp2 <= cpu_clk_4x_smp1 after Sim_Delay;
- if (cpu_clk_4x_smp1 = '1' and cpu_clk_4x_smp2 = '0') then
- clk4_phase <= "0100" after Sim_Delay;
- clk4_phase_short <= "01" after Sim_Delay;
- else
- clk4_phase <= (clk4_phase(2 downto 0) & clk4_phase(3)) after Sim_Delay;
- clk4_phase_short <= clk4_phase_short(0) & clk4_phase_short(1);
- end if;
- end if;
- end process;
-
- process(cpu_clk_4x, areset) --
- begin
- if areset = '1' then
- sdr_clk <= '0';
- sdr_clk_n <= '0';
- elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then
- if clk4_phase_short(0) = '1' then
- sdr_clk <= '1' after Sim_Delay;
- else
- sdr_clk <= '0' after Sim_Delay;
- end if;
- if clk4_phase_short(1) = '1' then
- sdr_clk_n <= '1' after Sim_Delay;
- else
- sdr_clk_n <= '0' after Sim_Delay;
- end if;
- end if;
- end process;
-
- cke_q_p <= '1' after Clk_to_Output;
- cs_qn_p <= '0' after Clk_to_Output;
-
- process(cpu_clk_4x, areset) --
- begin
- if areset = '1' then
- ras_qn_p <= '1';
- cas_qn_p <= '1';
- we_qn_p <= '1';
- dqs_q_p <= "ZZ";
- sdr_a_p <= "0000000000000";
- ba_q_p <= "00";
- sdr_clk_p <= '0';
- sdr_clk_n_p <= '1';
- elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then
- ras_qn_p <= transport ras_qn after Clk_to_Output;
- cas_qn_p <= transport cas_qn after Clk_to_Output;
- we_qn_p <= transport we_qn after Clk_to_Output;
- if dqs_oe_n(0) = '0' then
- dqs_q_p(0) <= transport dqs_q(0) after Clk_to_Output;
- else
- dqs_q_p(0) <= transport 'Z' after Clk_to_Output;
- end if;
- if dqs_oe_n(1) = '0' then
- dqs_q_p(1) <= transport dqs_q(1) after Clk_to_Output;
- else
- dqs_q_p(1) <= transport 'Z' after Clk_to_Output;
- end if;
- sdr_a_p <= transport sdr_a after Clk_to_Output;
- ba_q_p <= transport ba_q after Clk_to_Output;
- sdr_clk_p <= transport sdr_clk after Clk_to_Output;
- sdr_clk_n_p <= transport sdr_clk_n after Clk_to_Output;
- end if;
- end process;
-
- process(cpu_clk_2x, areset) --
- begin
- if areset = '1' then
- ddr_state <= idle;
- ras_qn <= '1';
- cas_qn <= '1';
- we_qn <= '1';
- smp_req_adr <= (others => '0');
- smp_req_type <= '0';
- smp_req_len <= '0';
- sdr_a <= "XXXXXXXXXXXXX";
- ba_q <= "00";
- ddr_req_ack <= '0';
- ddr_busy <= '1';
- ddr_write_en_int <= '0';
- ddr_read_en_int <= '0';
- elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
-
- -- Default values
- ras_qn <= '1' after Sim_Delay;
- cas_qn <= '1' after Sim_Delay;
- we_qn <= '1' after Sim_Delay;
- sdr_a <= "XXXXXXXXXXXXX" after Sim_Delay;
- ba_q <= "00" after Sim_Delay;
- ddr_req_ack <= '0' after Sim_Delay;
- ddr_busy <= '1' after Sim_Delay;
- ddr_write_en_int <= '0' after Sim_Delay;
- ddr_read_en_int <= '0' after Sim_Delay;
-
- case ddr_state is
- when idle =>
- smp_req_adr <= ddr_req_adr after Sim_Delay;
- smp_req_type <= ddr_rd_wr_n after Sim_Delay;
- smp_req_len <= ddr_req_len after Sim_Delay;
- ddr_busy <= '0' after Sim_Delay;
- if refresh_pend = '1' then
- ddr_state <= refresh after Sim_Delay;
- elsif new_command = '1' then
- if ddr_cmd(15) = '1' then
- ddr_state <= cpu_pre after Sim_Delay;
- else
- ddr_state <= cmd after Sim_Delay;
- end if;
- elsif ddr_req = '1' then
- ddr_state <= act after Sim_Delay;
- else
- ddr_state <= idle after Sim_Delay;
- end if;
- when act =>
- sdr_a <= smp_req_adr(23 downto 11) after Sim_Delay;
- ras_qn <= '0' after Sim_Delay;
- ddr_state <= act_nop1 after Sim_Delay;
- ddr_req_ack <= '1' after Sim_Delay;
- ddr_write_en_int <= not(smp_req_type) after Sim_Delay;
- when act_nop1 =>
- ddr_state <= act_nop2 after Sim_Delay;
- when act_nop2 =>
- ddr_state <= rd_wr after Sim_Delay;
- when rd_wr =>
- sdr_a(10) <= '0' after Sim_Delay; -- Disable auto precharge
- sdr_a(9 downto 0) <= smp_req_adr(10 downto 1) after Sim_Delay;
- cas_qn <= '0' after Sim_Delay;
- we_qn <= smp_req_type after Sim_Delay;
- if smp_req_type = '1' then
- ddr_state <= rd_nop1 after Sim_Delay;
- else
- ddr_state <= wr_nop1 after Sim_Delay;
- end if;
- when wr_nop1 =>
- ddr_state <= wr_nop2 after Sim_Delay;
- when wr_nop2 =>
- ddr_state <= wr_nop3 after Sim_Delay;
- when wr_nop3 =>
- ddr_state <= pre after Sim_Delay;
- when rd_nop1 =>
- ddr_state <= rd_nop2 after Sim_Delay;
- when rd_nop2 =>
- ddr_state <= pre after Sim_Delay;
- when pre =>
- ras_qn <= '0' after Sim_Delay;
- we_qn <= '0' after Sim_Delay;
- sdr_a(10) <= '1' after Sim_Delay; -- Precharge all banks
- ddr_state <= pre_nop1 after Sim_Delay;
- ddr_read_en_int <= smp_req_type after Sim_Delay;
- when pre_nop1 =>
- ddr_state <= pre_nop2 after Sim_Delay;
- when cmd =>
- cas_qn <= '0' after Sim_Delay;
- ras_qn <= '0' after Sim_Delay;
- we_qn <= '0' after Sim_Delay;
- ba_q <= ddr_cmd(14 downto 13) after Sim_Delay;
- sdr_a <= ddr_cmd(12 downto 0) after Sim_Delay;
- ddr_state <= idle after Sim_Delay;
- when cpu_pre =>
- ddr_state <= pre after Sim_Delay;
- when refresh =>
- cas_qn <= '0' after Sim_Delay;
- ras_qn <= '0' after Sim_Delay;
- ddr_state <= refresh_wait after Sim_Delay;
- when refresh_wait =>
- if refresh_wait_end = '1' then
- ddr_state <= pre after Sim_Delay;
- end if;
- when pre_nop2 =>
- ddr_state <= idle after Sim_Delay;
- when others =>
- ddr_state <= idle after Sim_Delay;
- end case;
- end if;
- end process;
-
- process(cpu_clk, areset) --
- begin
- if areset = '1' then
- ddr_cmd <= "0000000000000000";
- elsif (cpu_clk'event and cpu_clk = '1') then
- if ddr_command_we = '1' then
- ddr_cmd <= ddr_command after Sim_Delay;
- else
- ddr_cmd <= ddr_cmd after Sim_Delay;
- end if;
- end if;
- end process;
-
- process(cpu_clk_2x, areset) --
- begin
- if areset = '1' then
- ddr_cmd_we_smp <= '0';
- new_command <= '0';
- sdr_smp <= "000000000000000000000000000000000000";
- elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
- ddr_cmd_we_smp <= ddr_command_we after Sim_Delay;
- if ddr_command_we = '0' and ddr_cmd_we_smp = '1' then
- new_command <= '1' after Sim_Delay;
- elsif ddr_state = cmd or ddr_state = cpu_pre then
- new_command <= '0' after Sim_Delay;
- else
- new_command <= new_command after Sim_Delay;
- end if;
-
- if ddr_write_en_int = '1' then
- sdr_smp <= ddr_data_write after Sim_Delay;
- else
- sdr_smp <= sdr_smp after Sim_Delay;
- end if;
-
- end if;
- end process;
-
- process(cpu_clk_4x, areset) --
- begin
- if areset = '1' then
- dqs_q <= "00";
- dqs_oe_n <= "11";
- sdr_oe_ctrl <= '1';
- sdr_wr_msw <= "000000000000000000";
- elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then
-
- if ddr_state = wr_nop1 and clk4_phase_short(0) = '1' then
- sdr_oe_ctrl <= '0' after Sim_Delay;
- elsif ddr_state = wr_nop3 and clk4_phase_short(0) = '1' then
- sdr_oe_ctrl <= '1' after Sim_Delay;
- else
- sdr_oe_ctrl <= sdr_oe_ctrl after Sim_Delay;
- end if;
-
- if ddr_state = idle or ddr_state = wr_nop3 then
- dqs_oe_n <= "11" after Sim_Delay;
- elsif ddr_state = wr_nop1 then
- dqs_oe_n <= "00" after Sim_Delay;
- else
- dqs_oe_n <= dqs_oe_n after Sim_Delay;
- end if;
-
- if (ddr_state = wr_nop2 and clk4_phase_short(0) = '1') then
- dqs_q <= "11" after Sim_Delay;
- else
- dqs_q <= "00" after Sim_Delay;
- end if;
-
- if ddr_state = wr_nop1 and clk4_phase_short(1) = '1' then
- sdr_wr_msw <= "111111111111111111" after Sim_Delay;
- else
- sdr_wr_msw <= "000000000000000000" after Sim_Delay;
- end if;
-
- end if;
- end process;
-
- -- NOTE! DATA OUTPUT PATH. CLOCKED ON FALLING 4X CLOCK
- process(cpu_clk_4x, areset) --
- begin
- if areset = '1' then
- sdr_d_p <= "ZZZZZZZZZZZZZZZZ";
- dm_q_p <= "11";
- sdr_oe_n <= "1111111111111111";
- sdr_d <= "0000000000000000";
- dm_q <= "11";
- elsif (cpu_clk_4x'event and cpu_clk_4x = '0') then
-
- for i in 0 to 15 loop
- if sdr_oe_n(i) = '0' then
- sdr_d_p(i) <= transport sdr_d(i) after Clk_to_Output;
- else
- sdr_d_p(i) <= transport 'Z' after Clk_to_Output;
- end if;
- end loop;
-
- dm_q_p <= transport dm_q after Clk_to_Output;
-
- if sdr_oe_ctrl = '0' then
- sdr_oe_n <= "0000000000000000" after Sim_Delay;
- else
- sdr_oe_n <= "1111111111111111" after Sim_Delay;
- end if;
-
- for i in 0 to 15 loop
- if sdr_wr_msw(i) = '0' then
- sdr_d(i) <= sdr_smp(i) after Sim_Delay;
- else
- sdr_d(i) <= sdr_smp(i+16) after Sim_Delay;
- end if;
- end loop;
-
- for i in 0 to 1 loop
- if sdr_wr_msw(i+16) = '0' then
- dm_q(i) <= sdr_smp(i+32) after Sim_Delay;
- else
- dm_q(i) <= sdr_smp(i+34) after Sim_Delay;
- end if;
- end loop;
-
- end if;
- end process;
-
- process(cpu_clk_2x, areset) --
- begin
- if areset = '1' then
- refresh_cnt <= "0000000000";
- refresh_pend <= '0';
- refresh_end <= '0';
- refresh_wait_cnt <= "000";
- refresh_wait_end <= '0';
- elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
-
- if refresh_cnt = Refresh_Interval then
- refresh_end <= '1';
- else
- refresh_end <= '0';
- end if;
-
- if refresh_end = '1' then
- refresh_cnt <= "0000000000";
- else
- refresh_cnt <= refresh_cnt + '1';
- end if;
-
- if refresh_end = '1' and refresh_en = '1' then
- refresh_pend <= '1' after Sim_Delay;
- elsif ddr_state = refresh then
- refresh_pend <= '0' after Sim_Delay;
- else
- refresh_pend <= refresh_pend after Sim_Delay;
- end if;
-
- if ddr_state = refresh_wait then
- refresh_wait_cnt <= refresh_wait_cnt + '1';
- else
- refresh_wait_cnt <= "000";
- end if;
-
- if refresh_wait_cnt = "111" then
- refresh_wait_end <= '1' after Sim_Delay;
- else
- refresh_wait_end <= '0' after Sim_Delay;
- end if;
-
- end if;
- end process;
-
- -- 911. THIS IS A DUMMY FOR FGPA IMPEMENTATION TESTING
-
- process(ddr_in_clk, areset)
- begin
- if areset = '1' then
- ddr_clk_tog <= '0';
- elsif (ddr_in_clk'event and ddr_in_clk = '1') then
- ddr_clk_tog <= not(ddr_clk_tog) after Sim_Delay;
- end if;
- end process;
-
- process(ddr_in_clk_2x, areset)
- begin
- if areset = '1' then
- ddr_clk_smp1 <= '0';
- ddr_clk_smp2 <= '0';
- ddr_clk_phase <= '0';
- elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then
- ddr_clk_smp1 <= ddr_clk_tog after Sim_Delay;
- ddr_clk_smp2 <= ddr_clk_smp1 after Sim_Delay;
- if ddr_clk_smp1 = '1' and ddr_clk_smp2 = '0' then
- ddr_clk_phase <= '0';
- else
- ddr_clk_phase <= not(ddr_clk_phase);
- end if;
- end if;
- end process;
-
- process(ddr_in_clk_2x, areset)
- begin
- if areset = '1' then
- cas_n_smp <= '0';
- ras_n_smp <= '0';
- we_n_smp <= '0';
- read_start_sig <= '0';
- elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then
- cas_n_smp <= cas_qn_p_del after Sim_Delay;
- ras_n_smp <= ras_qn_p_del after Sim_Delay;
- we_n_smp <= we_qn_p_del after Sim_Delay;
- if ras_n_smp = '1' and cas_n_smp = '0' and we_n_smp = '1' and ddr_clk_phase = '1' then
- read_start_sig <= '1' after Sim_Delay;
- else
- read_start_sig <= '0' after Sim_Delay;
- end if;
- end if;
- end process;
-
- process(ddr_in_clk_2x, areset)
- begin
- if areset = '1' then
- sdr_d_in <= "0000000000000000";
- elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then
- sdr_d_in <= sdr_d_p_del after Sim_Delay;
- end if;
- end process;
-
- process(ddr_in_clk_2x, areset)
- begin
- if areset = '1' then
- read_time_cnt <= "00";
- read_input_en <= '0';
- elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then
-
- if read_start_sig = '1' then
- read_time_cnt <= "01" after Sim_Delay;
- elsif read_time_cnt = "00" then
- read_time_cnt <= read_time_cnt after Sim_Delay;
- else
- read_time_cnt <= read_time_cnt + '1' after Sim_Delay;
- end if;
-
- if read_time_cnt = "11" then
- read_input_en <= '1' after Sim_Delay;
- else
- read_input_en <= '0' after Sim_Delay;
- end if;
-
- end if;
- end process;
-
- process(ddr_in_clk_2x, areset)
- begin
- if areset = '1' then
- ddr_data_read_int <= "00000000000000000000000000000000";
- elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then
- ddr_data_read_int(31 downto 16) <= "0000000000000000" after Sim_Delay;
- if read_input_en = '1' then
- ddr_data_read_int(15 downto 0) <= sdr_d_in after Sim_Delay;
- else
- ddr_data_read_int(15 downto 0) <= ddr_data_read_int(15 downto 0) after Sim_Delay;
- end if;
- end if;
- end process;
-
-
-
-
-
-
-
-
- -- ###############
-
- process(cpu_clk, areset) --
- begin
- if areset = '1' then
- elsif (cpu_clk'event and cpu_clk = '1') then
- end if;
- end process;
-
-
- process(cpu_clk_2x, areset) --
- begin
- if areset = '1' then
- elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
- end if;
- end process;
-
-
- process(cpu_clk_4x, areset) --
- begin
- if areset = '1' then
- elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then
- end if;
- end process;
-
-
-end behave;
-
-
diff --git a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/mt46v16m16.vhd b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/mt46v16m16.vhd deleted file mode 100644 index 6b89345..0000000 --- a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/mt46v16m16.vhd +++ /dev/null @@ -1,1320 +0,0 @@ ------------------------------------------------------------------------------------------
---
--- File Name: MT46V16M16.VHD
--- Version: 2.1
--- Date: January 14th, 2002
--- Model: Behavioral
--- Simulator: NCDesktop - http://www.cadence.com
--- ModelSim PE - http://www.model.com
---
--- Dependencies: None
---
--- Author: Son P. Huynh
--- Email: sphuynh@micron.com
--- Phone: (208) 368-3825
--- Company: Micron Technology, Inc.
--- Part Number: MT46V16M16 (4 Mb x 16 x 4 Banks)
---
--- Description: Micron 256 Mb SDRAM DDR (Double Data Rate)
---
--- Limitation: Doesn't model internal refresh counter
---
--- Note:
---
--- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
--- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
--- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
--- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
---
--- Copyright (c) 1998 Micron Semiconductor Products, Inc.
--- All rights researved
---
--- Rev Author Date Changes
--- --- ---------------------------- ---------- -------------------------------------
--- 2.1 Son P. Huynh 01/14/2002 - Fix Burst_counter
--- Micron Technology, Inc.
---
--- 2.0 Son P. Huynh 11/08/2001 - Second release
--- Micron Technology, Inc. - Rewrote and remove SHARED VARIABLE
---
------------------------------------------------------------------------------------------
-
-LIBRARY IEEE;
- USE IEEE.STD_LOGIC_1164.ALL;
- USE IEEE.STD_LOGIC_UNSIGNED.ALL;
- USE IEEE.STD_LOGIC_ARITH.ALL;
-
-ENTITY MT46V16M16 IS
- GENERIC ( -- Timing for -75Z CL2
- tCK : TIME := 7.500 ns;
- tCH : TIME := 3.375 ns; -- 0.45*tCK
- tCL : TIME := 3.375 ns; -- 0.45*tCK
- tDH : TIME := 0.500 ns;
- tDS : TIME := 0.500 ns;
- tIH : TIME := 0.900 ns;
- tIS : TIME := 0.900 ns;
- tMRD : TIME := 15.000 ns;
- tRAS : TIME := 40.000 ns;
- tRAP : TIME := 20.000 ns;
- tRC : TIME := 65.000 ns;
- tRFC : TIME := 75.000 ns;
- tRCD : TIME := 20.000 ns;
- tRP : TIME := 20.000 ns;
- tRRD : TIME := 15.000 ns;
- tWR : TIME := 15.000 ns;
- addr_bits : INTEGER := 13;
- data_bits : INTEGER := 16;
- cols_bits : INTEGER := 9
- );
- PORT (
- Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
- Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
- Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
- Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
- Clk : IN STD_LOGIC;
- Clk_n : IN STD_LOGIC;
- Cke : IN STD_LOGIC;
- Cs_n : IN STD_LOGIC;
- Ras_n : IN STD_LOGIC;
- Cas_n : IN STD_LOGIC;
- We_n : IN STD_LOGIC;
- Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
- );
-END MT46V16M16;
-
-ARCHITECTURE behave OF MT46V16M16 IS
- -- Array for Read pipeline
- TYPE Array_Read_cmnd IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
- TYPE Array_Read_bank IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
- TYPE Array_Read_cols IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
-
- -- Array for Write pipeline
- TYPE Array_Write_cmnd IS ARRAY (2 DOWNTO 0) OF STD_LOGIC;
- TYPE Array_Write_bank IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
- TYPE Array_Write_cols IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
-
- -- Array for Auto Precharge
- TYPE Array_Read_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC;
- TYPE Array_Write_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC;
- TYPE Array_Count_precharge IS ARRAY (3 DOWNTO 0) OF INTEGER;
-
- -- Array for Manual Precharge
- TYPE Array_A10_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
- TYPE Array_Bank_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
- TYPE Array_Cmnd_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
-
- -- Array for Burst Terminate
- TYPE Array_Cmnd_bst IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
-
- -- Array for Memory Access
- TYPE Array_ram_type IS ARRAY (2**cols_bits - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
- TYPE Array_ram_pntr IS ACCESS Array_ram_type;
- TYPE Array_ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF Array_ram_pntr;
-
- -- Data pair
- SIGNAL Dq_pair : STD_LOGIC_VECTOR (2 * data_bits - 1 DOWNTO 0);
- SIGNAL Dm_pair : STD_LOGIC_VECTOR (3 DOWNTO 0);
-
- -- Mode Register
- SIGNAL Mode_reg : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
-
- -- Command Decode Variables
- SIGNAL Active_enable, Aref_enable, Burst_term, Ext_mode_enable : STD_LOGIC := '0';
- SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : STD_LOGIC := '0';
-
- -- Burst Length Decode Variables
- SIGNAL Burst_length_2, Burst_length_4, Burst_length_8, Burst_length_f : STD_LOGIC := '0';
-
- -- Cas Latency Decode Variables
- SIGNAL Cas_latency_15, Cas_latency_2, Cas_latency_25, Cas_latency_3, Cas_latency_4 : STD_LOGIC := '0';
-
- -- Internal Control Signals
- SIGNAL Cs_in, Ras_in, Cas_in, We_in : STD_LOGIC := '0';
-
- -- System Clock
- SIGNAL Sys_clk : STD_LOGIC := '0';
-
- -- Dqs buffer
- SIGNAL Dqs_out : STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
-
-BEGIN
- -- Strip the strength
- Cs_in <= To_X01 (Cs_n);
- Ras_in <= To_X01 (Ras_n);
- Cas_in <= To_X01 (Cas_n);
- We_in <= To_X01 (We_n);
-
- -- Commands Decode
- Active_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND We_in;
- Aref_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND We_in;
- Burst_term <= NOT(Cs_in) AND Ras_in AND Cas_in AND NOT(We_in);
- Ext_mode_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND Ba(0) AND NOT(Ba(1));
- Mode_reg_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND NOT(Ba(0)) AND NOT(Ba(1));
- Prech_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND NOT(We_in);
- Read_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND We_in;
- Write_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND NOT(We_in);
-
- -- Burst Length Decode
- Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0);
- Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0));
- Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0);
- Burst_length_f <= (Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0);
-
- -- CAS Latency Decode
- Cas_latency_15 <= Mode_reg(6) AND NOT(Mode_reg(5)) AND (Mode_reg(4));
- Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4));
- Cas_latency_25 <= Mode_reg(6) AND Mode_reg(5) AND NOT(Mode_reg(4));
- Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4);
- Cas_latency_4 <= (Mode_reg(6)) AND NOT(Mode_reg(5)) AND NOT(Mode_reg(4));
-
- -- Dqs buffer
- Dqs <= Dqs_out;
-
- --
- -- System Clock
- --
- int_clk : PROCESS (Clk, Clk_n)
- VARIABLE ClkZ, CkeZ : STD_LOGIC := '0';
- begin
- IF Clk = '1' AND Clk_n = '0' THEN
- ClkZ := '1';
- CkeZ := Cke;
- ELSIF Clk = '0' AND Clk_n = '1' THEN
- ClkZ := '0';
- END IF;
- Sys_clk <= CkeZ AND ClkZ;
- END PROCESS;
-
- --
- -- Main Process
- --
- state_register : PROCESS
- -- Precharge Variables
- VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : STD_LOGIC := '0';
-
- -- Activate Variables
- VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : STD_LOGIC := '1';
-
- -- Data IO variables
- VARIABLE Data_in_enable, Data_out_enable : STD_LOGIC := '0';
-
- -- Internal address mux variables
- VARIABLE Cols_brst : STD_LOGIC_VECTOR (2 DOWNTO 0);
- VARIABLE Prev_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
- VARIABLE Bank_addr : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
- VARIABLE Cols_addr : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
- VARIABLE Rows_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
- VARIABLE B0_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
- VARIABLE B1_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
- VARIABLE B2_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
- VARIABLE B3_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
-
- -- DLL Reset variables
- VARIABLE DLL_enable : STD_LOGIC := '0';
- VARIABLE DLL_reset : STD_LOGIC := '0';
- VARIABLE DLL_done : STD_LOGIC := '0';
- VARIABLE DLL_count : INTEGER := 0;
-
- -- Timing Check
- VARIABLE MRD_chk : TIME := 0 ns;
- VARIABLE RFC_chk : TIME := 0 ns;
- VARIABLE RRD_chk : TIME := 0 ns;
- VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns;
- VARIABLE RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3 : TIME := 0 ns;
- VARIABLE RC_chk0, RC_chk1, RC_chk2, RC_chk3 : TIME := 0 ns;
- VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns;
- VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns;
- VARIABLE WR_chk0, WR_chk1, WR_chk2, WR_chk3 : TIME := 0 ns;
-
- -- Read pipeline variables
- VARIABLE Read_cmnd : Array_Read_cmnd;
- VARIABLE Read_bank : Array_Read_bank;
- VARIABLE Read_cols : Array_Read_cols;
-
- -- Write pipeline variables
- VARIABLE Write_cmnd : Array_Write_cmnd;
- VARIABLE Write_bank : Array_Write_bank;
- VARIABLE Write_cols : Array_Write_cols;
-
- -- Auto Precharge variables
- VARIABLE Read_precharge : Array_Read_precharge := ('0' & '0' & '0' & '0');
- VARIABLE Write_precharge : Array_Write_precharge := ('0' & '0' & '0' & '0');
- VARIABLE Count_precharge : Array_Count_precharge := ( 0 & 0 & 0 & 0 );
-
- -- Manual Precharge variables
- VARIABLE A10_precharge : Array_A10_precharge;
- VARIABLE Bank_precharge : Array_Bank_precharge;
- VARIABLE Cmnd_precharge : Array_Cmnd_precharge;
-
- -- Burst Terminate variable
- VARIABLE Cmnd_bst : Array_Cmnd_bst;
-
- -- Memory Banks
- VARIABLE Bank0 : Array_ram_stor;
- VARIABLE Bank1 : Array_ram_stor;
- VARIABLE Bank2 : Array_ram_stor;
- VARIABLE Bank3 : Array_ram_stor;
-
- -- Burst Counter
- VARIABLE Burst_counter : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
-
- -- Internal Dqs initialize
- VARIABLE Dqs_int : STD_LOGIC := '0';
-
- -- Data buffer for DM Mask
- VARIABLE Data_buf : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
-
- --
- -- Initialize empty rows
- --
- PROCEDURE Init_mem (Bank : STD_LOGIC_VECTOR; Row_index : INTEGER) IS
- VARIABLE i, j : INTEGER := 0;
- BEGIN
- IF Bank = "00" THEN
- IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty
- Bank0 (Row_index) := NEW Array_ram_type; -- Open new row for access
- FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros
- FOR j IN (data_bits - 1) DOWNTO 0 LOOP
- Bank0 (Row_index) (i) (j) := '0';
- END LOOP;
- END LOOP;
- END IF;
- ELSIF Bank = "01" THEN
- IF Bank1 (Row_index) = NULL THEN
- Bank1 (Row_index) := NEW Array_ram_type;
- FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
- FOR j IN (data_bits - 1) DOWNTO 0 LOOP
- Bank1 (Row_index) (i) (j) := '0';
- END LOOP;
- END LOOP;
- END IF;
- ELSIF Bank = "10" THEN
- IF Bank2 (Row_index) = NULL THEN
- Bank2 (Row_index) := NEW Array_ram_type;
- FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
- FOR j IN (data_bits - 1) DOWNTO 0 LOOP
- Bank2 (Row_index) (i) (j) := '0';
- END LOOP;
- END LOOP;
- END IF;
- ELSIF Bank = "11" THEN
- IF Bank3 (Row_index) = NULL THEN
- Bank3 (Row_index) := NEW Array_ram_type;
- FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
- FOR j IN (data_bits - 1) DOWNTO 0 LOOP
- Bank3 (Row_index) (i) (j) := '0';
- END LOOP;
- END LOOP;
- END IF;
- END IF;
- END;
-
- --
- -- Burst Counter
- --
- PROCEDURE Burst_decode IS
- VARIABLE Cols_temp : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0) := (OTHERS => '0');
- BEGIN
- -- Advance burst counter
- Burst_counter := Burst_counter + 1;
-
- -- Burst Type
- IF Mode_reg (3) = '0' THEN
- Cols_temp := Cols_addr + 1;
- ELSIF Mode_reg (3) = '1' THEN
- Cols_temp (2) := Burst_counter (2) XOR Cols_brst (2);
- Cols_temp (1) := Burst_counter (1) XOR Cols_brst (1);
- Cols_temp (0) := Burst_counter (0) XOR Cols_brst (0);
- END IF;
-
- -- Burst Length
- IF Burst_length_2 = '1' THEN
- Cols_addr (0) := Cols_temp (0);
- ELSIF Burst_length_4 = '1' THEN
- Cols_addr (1 DOWNTO 0) := Cols_temp (1 DOWNTO 0);
- ELSIF Burst_length_8 = '1' THEN
- Cols_addr (2 DOWNTO 0) := Cols_temp (2 DOWNTO 0);
- ELSE
- Cols_addr := Cols_temp;
- END IF;
-
- -- Data counter
- IF Burst_length_2 = '1' THEN
- IF Burst_counter >= 2 THEN
- IF Data_in_enable = '1' THEN
- Data_in_enable := '0';
- ELSIF Data_out_enable = '1' THEN
- Data_out_enable := '0';
- END IF;
- END IF;
- ELSIF Burst_length_4 = '1' THEN
- IF Burst_counter >= 4 THEN
- IF Data_in_enable = '1' THEN
- Data_in_enable := '0';
- ELSIF Data_out_enable = '1' THEN
- Data_out_enable := '0';
- END IF;
- END IF;
- ELSIF Burst_length_8 = '1' THEN
- IF Burst_counter >= 8 THEN
- IF Data_in_enable = '1' THEN
- Data_in_enable := '0';
- ELSIF Data_out_enable = '1' THEN
- Data_out_enable := '0';
- END IF;
- END IF;
- END IF;
- END;
-
- BEGIN
- WAIT ON Sys_clk;
-
- --
- -- Manual Precharge Pipeline
- --
- IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
- -- A10 Precharge Pipeline
- A10_precharge(0) := A10_precharge(1);
- A10_precharge(1) := A10_precharge(2);
- A10_precharge(2) := A10_precharge(3);
- A10_precharge(3) := A10_precharge(4);
- A10_precharge(4) := A10_precharge(5);
- A10_precharge(5) := A10_precharge(6);
- A10_precharge(6) := A10_precharge(7);
- A10_precharge(7) := A10_precharge(8);
- A10_precharge(8) := '0';
-
- -- Bank Precharge Pipeline
- Bank_precharge(0) := Bank_precharge(1);
- Bank_precharge(1) := Bank_precharge(2);
- Bank_precharge(2) := Bank_precharge(3);
- Bank_precharge(3) := Bank_precharge(4);
- Bank_precharge(4) := Bank_precharge(5);
- Bank_precharge(5) := Bank_precharge(6);
- Bank_precharge(6) := Bank_precharge(7);
- Bank_precharge(7) := Bank_precharge(8);
- Bank_precharge(8) := "00";
-
- -- Command Precharge Pipeline
- Cmnd_precharge(0) := Cmnd_precharge(1);
- Cmnd_precharge(1) := Cmnd_precharge(2);
- Cmnd_precharge(2) := Cmnd_precharge(3);
- Cmnd_precharge(3) := Cmnd_precharge(4);
- Cmnd_precharge(4) := Cmnd_precharge(5);
- Cmnd_precharge(5) := Cmnd_precharge(6);
- Cmnd_precharge(6) := Cmnd_precharge(7);
- Cmnd_precharge(7) := Cmnd_precharge(8);
- Cmnd_precharge(8) := '0';
-
- -- Terminate Read if same bank or all banks
- IF ((Cmnd_precharge (0) = '1') AND
- (Bank_precharge (0) = Bank_addr OR A10_precharge (0) = '1') AND
- (Data_out_enable = '1')) THEN
- Data_out_enable := '0';
- END IF;
- END IF;
-
- --
- -- Burst Terminate Pipeline
- --
- IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
- -- Burst Terminate pipeline
- Cmnd_bst (0) := Cmnd_bst (1);
- Cmnd_bst (1) := Cmnd_bst (2);
- Cmnd_bst (2) := Cmnd_bst (3);
- Cmnd_bst (3) := Cmnd_bst (4);
- Cmnd_bst (4) := Cmnd_bst (5);
- Cmnd_bst (5) := Cmnd_bst (6);
- Cmnd_bst (6) := Cmnd_bst (7);
- Cmnd_bst (7) := Cmnd_bst (8);
- Cmnd_bst (8) := '0';
-
- -- Terminate current Read
- IF ((Cmnd_bst (0) = '1') AND (Data_out_enable = '1')) THEN
- Data_out_enable := '0';
- END IF;
- END IF;
-
- --
- -- Dq and Dqs Drivers
- --
- IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
- -- Read Command Pipeline
- Read_cmnd (0) := Read_cmnd (1);
- Read_cmnd (1) := Read_cmnd (2);
- Read_cmnd (2) := Read_cmnd (3);
- Read_cmnd (3) := Read_cmnd (4);
- Read_cmnd (4) := Read_cmnd (5);
- Read_cmnd (5) := Read_cmnd (6);
- Read_cmnd (6) := Read_cmnd (7);
- Read_cmnd (7) := Read_cmnd (8);
- Read_cmnd (8) := '0';
-
- -- Read Bank Pipeline
- Read_bank (0) := Read_bank (1);
- Read_bank (1) := Read_bank (2);
- Read_bank (2) := Read_bank (3);
- Read_bank (3) := Read_bank (4);
- Read_bank (4) := Read_bank (5);
- Read_bank (5) := Read_bank (6);
- Read_bank (6) := Read_bank (7);
- Read_bank (7) := Read_bank (8);
- Read_bank (8) := "00";
-
- -- Read Column Pipeline
- Read_cols (0) := Read_cols (1);
- Read_cols (1) := Read_cols (2);
- Read_cols (2) := Read_cols (3);
- Read_cols (3) := Read_cols (4);
- Read_cols (4) := Read_cols (5);
- Read_cols (5) := Read_cols (6);
- Read_cols (6) := Read_cols (7);
- Read_cols (7) := Read_cols (8);
- Read_cols (8) := (OTHERS => '0');
-
- -- Initialize Read command
- IF Read_cmnd (0) = '1' THEN
- Data_out_enable := '1';
- Bank_addr := Read_bank (0);
- Cols_addr := Read_cols (0);
- Cols_brst := Cols_addr (2 DOWNTO 0);
- Burst_counter := (OTHERS => '0');
-
- -- Row address mux
- CASE Bank_addr IS
- WHEN "00" => Rows_addr := B0_row_addr;
- WHEN "01" => Rows_addr := B1_row_addr;
- WHEN "10" => Rows_addr := B2_row_addr;
- WHEN OTHERS => Rows_addr := B3_row_addr;
- END CASE;
- END IF;
-
- -- Toggle Dqs during Read command
- IF Data_out_enable = '1' THEN
- Dqs_int := '0';
- IF Dqs_out = "00" THEN
- Dqs_out <= "11";
- ELSIF Dqs_out = "11" THEN
- Dqs_out <= "00";
- ELSE
- Dqs_out <= "00";
- END IF;
- ELSIF Data_out_enable = '0' AND Dqs_int = '0' THEN
- Dqs_out <= "ZZ";
- END IF;
-
- -- Initialize Dqs for Read command
- IF Read_cmnd (2) = '1' THEN
- IF Data_out_enable = '0' THEN
- Dqs_int := '1';
- Dqs_out <= "00";
- END IF;
- END IF;
-
- -- Read Latch
- IF Data_out_enable = '1' THEN
- -- Initialize Memory
- Init_mem (Bank_addr, CONV_INTEGER(Rows_addr));
-
- -- Output Data
- CASE Bank_addr IS
- WHEN "00" => Dq <= Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
- WHEN "01" => Dq <= Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
- WHEN "10" => Dq <= Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
- WHEN OTHERS => Dq <= Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
- END CASE;
-
- -- Increase Burst Counter
- Burst_decode;
- ELSE
- Dq <= (OTHERS => 'Z');
- END IF;
- END IF;
-
- --
- -- Write FIFO and DM Mask Logic
- --
- IF Sys_clk'EVENT AND Sys_clk = '1' THEN
- -- Write command pipeline
- Write_cmnd (0) := Write_cmnd (1);
- Write_cmnd (1) := Write_cmnd (2);
- Write_cmnd (2) := '0';
-
- -- Write command pipeline
- Write_bank (0) := Write_bank (1);
- Write_bank (1) := Write_bank (2);
- Write_bank (2) := "00";
-
- -- Write column pipeline
- Write_cols (0) := Write_cols (1);
- Write_cols (1) := Write_cols (2);
- Write_cols (2) := (OTHERS => '0');
-
- -- Initialize Write command
- IF Write_cmnd (0) = '1' THEN
- Data_in_enable := '1';
- Bank_addr := Write_bank (0);
- Cols_addr := Write_cols (0);
- Cols_brst := Cols_addr (2 DOWNTO 0);
- Burst_counter := (OTHERS => '0');
-
- -- Row address mux
- CASE Bank_addr IS
- WHEN "00" => Rows_addr := B0_row_addr;
- WHEN "01" => Rows_addr := B1_row_addr;
- WHEN "10" => Rows_addr := B2_row_addr;
- WHEN OTHERS => Rows_addr := B3_row_addr;
- END CASE;
- END IF;
-
- -- Write data
- IF Data_in_enable = '1' THEN
- -- Initialize memory
- Init_mem (Bank_addr, CONV_INTEGER(Rows_addr));
-
- -- Write first data
- IF Dm_pair (1) = '0' OR Dm_pair (0) = '0' THEN
- -- Data Buffer
- CASE Bank_addr IS
- WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
- WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
- WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
- WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
- END CASE;
-
- -- Perform DM Mask
- IF Dm_pair (0) = '0' THEN
- Data_buf ( 7 DOWNTO 0) := Dq_pair ( 7 DOWNTO 0);
- END IF;
- IF Dm_pair (1) = '0' THEN
- Data_buf (15 DOWNTO 8) := Dq_pair (15 DOWNTO 8);
- END IF;
-
- -- Write Data
- CASE Bank_addr IS
- WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
- WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
- WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
- WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
- END CASE;
- END IF;
-
- -- Increase Burst Counter
- Burst_decode;
-
- -- Write second data
- IF Dm_pair (3) = '0' OR Dm_pair (2) = '0' THEN
- -- Data Buffer
- CASE Bank_addr IS
- WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
- WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
- WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
- WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
- END CASE;
-
- -- Perform DM Mask
- IF Dm_pair (2) = '0' THEN
- Data_buf ( 7 DOWNTO 0) := Dq_pair (23 DOWNTO 16);
- END IF;
- IF Dm_pair (3) = '0' THEN
- Data_buf (15 DOWNTO 8) := Dq_pair (31 DOWNTO 24);
- END IF;
-
- -- Write Data
- CASE Bank_addr IS
- WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
- WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
- WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
- WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
- END CASE;
- END IF;
-
- -- Increase Burst Counter
- Burst_decode;
-
- -- tWR start and tWTR check
- IF Dm_pair (3 DOWNTO 2) = "00" OR Dm_pair (1 DOWNTO 0) = "00" THEN
- CASE Bank_addr IS
- WHEN "00" => WR_chk0 := NOW;
- WHEN "01" => WR_chk1 := NOW;
- WHEN "10" => WR_chk2 := NOW;
- WHEN OTHERS => WR_chk3 := NOW;
- END CASE;
-
- -- tWTR check
- ASSERT (Read_enable = '0')
- REPORT "tWTR violation during Read"
- SEVERITY WARNING;
- END IF;
- END IF;
- END IF;
-
- --
- -- Auto Precharge Calculation
- --
- IF Sys_clk'EVENT AND Sys_clk = '1' THEN
- -- Precharge counter
- IF Read_precharge (0) = '1' OR Write_precharge (0) = '1' THEN
- Count_precharge (0) := Count_precharge (0) + 1;
- END IF;
- IF Read_precharge (1) = '1' OR Write_precharge (1) = '1' THEN
- Count_precharge (1) := Count_precharge (1) + 1;
- END IF;
- IF Read_precharge (2) = '1' OR Write_precharge (2) = '1' THEN
- Count_precharge (2) := Count_precharge (2) + 1;
- END IF;
- IF Read_precharge (3) = '1' OR Write_precharge (3) = '1' THEN
- Count_precharge (3) := Count_precharge (3) + 1;
- END IF;
-
- -- Read with AutoPrecharge Calculation
- -- The device start internal precharge when:
- -- 1. Meet tRAS requirement
- -- 2. BL/2 cycles after command
- IF ((Read_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN
- IF ((Burst_length_2 = '1' AND Count_precharge(0) >= 1) OR
- (Burst_length_4 = '1' AND Count_precharge(0) >= 2) OR
- (Burst_length_8 = '1' AND Count_precharge(0) >= 4)) THEN
- Pc_b0 := '1';
- Act_b0 := '0';
- RP_chk0 := NOW;
- Read_precharge(0) := '0';
- END IF;
- END IF;
- IF ((Read_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN
- IF ((Burst_length_2 = '1' AND Count_precharge(1) >= 1) OR
- (Burst_length_4 = '1' AND Count_precharge(1) >= 2) OR
- (Burst_length_8 = '1' AND Count_precharge(1) >= 4)) THEN
- Pc_b1 := '1';
- Act_b1 := '0';
- RP_chk1 := NOW;
- Read_precharge(1) := '0';
- END IF;
- END IF;
- IF ((Read_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN
- IF ((Burst_length_2 = '1' AND Count_precharge(2) >= 1) OR
- (Burst_length_4 = '1' AND Count_precharge(2) >= 2) OR
- (Burst_length_8 = '1' AND Count_precharge(2) >= 4)) THEN
- Pc_b2 := '1';
- Act_b2 := '0';
- RP_chk2 := NOW;
- Read_precharge(2) := '0';
- END IF;
- END IF;
- IF ((Read_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN
- IF ((Burst_length_2 = '1' AND Count_precharge(3) >= 1) OR
- (Burst_length_4 = '1' AND Count_precharge(3) >= 2) OR
- (Burst_length_8 = '1' AND Count_precharge(3) >= 4)) THEN
- Pc_b3 := '1';
- Act_b3 := '0';
- RP_chk3 := NOW;
- Read_precharge(3) := '0';
- END IF;
- END IF;
-
- -- Write with AutoPrecharge Calculation
- -- The device start internal precharge when:
- -- 1. Meet tRAS requirement
- -- 2. Two clock after last burst
- -- Since tWR is time base, the model will compensate tRP
- IF ((Write_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN
- IF ((Burst_length_2 = '1' AND Count_precharge (0) >= 4) OR
- (Burst_length_4 = '1' AND Count_precharge (0) >= 5) OR
- (Burst_length_8 = '1' AND Count_precharge (0) >= 7)) THEN
- Pc_b0 := '1';
- Act_b0 := '0';
- RP_chk0 := NOW - ((2 * tCK) - tWR);
- Write_precharge(0) := '0';
- END IF;
- END IF;
- IF ((Write_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN
- IF ((Burst_length_2 = '1' AND Count_precharge (1) >= 4) OR
- (Burst_length_4 = '1' AND Count_precharge (1) >= 5) OR
- (Burst_length_8 = '1' AND Count_precharge (1) >= 7)) THEN
- Pc_b1 := '1';
- Act_b1 := '0';
- RP_chk1 := NOW - ((2 * tCK) - tWR);
- Write_precharge(1) := '0';
- END IF;
- END IF;
- IF ((Write_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN
- IF ((Burst_length_2 = '1' AND Count_precharge (2) >= 4) OR
- (Burst_length_4 = '1' AND Count_precharge (2) >= 5) OR
- (Burst_length_8 = '1' AND Count_precharge (2) >= 7)) THEN
- Pc_b2 := '1';
- Act_b2 := '0';
- RP_chk2 := NOW - ((2 * tCK) - tWR);
- Write_precharge(2) := '0';
- END IF;
- END IF;
- IF ((Write_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN
- IF ((Burst_length_2 = '1' AND Count_precharge (3) >= 4) OR
- (Burst_length_4 = '1' AND Count_precharge (3) >= 5) OR
- (Burst_length_8 = '1' AND Count_precharge (3) >= 7)) THEN
- Pc_b3 := '1';
- Act_b3 := '0';
- RP_chk3 := NOW - ((2 * tCK) - tWR);
- Write_precharge(3) := '0';
- END IF;
- END IF;
- END IF;
-
- --
- -- DLL Counter
- --
- IF Sys_clk'EVENT AND Sys_clk = '1' THEN
- IF (DLL_Reset = '1' AND DLL_done = '0') THEN
- DLL_count := DLL_count + 1;
- IF (DLL_count >= 200) THEN
- DLL_done := '1';
- END IF;
- END IF;
- END IF;
-
- --
- -- Control Logic
- --
- IF Sys_clk'EVENT AND Sys_clk = '1' THEN
- -- Auto Refresh
- IF Aref_enable = '1' THEN
- -- Auto Refresh to Auto Refresh
- ASSERT (NOW - RFC_chk >= tRFC)
- REPORT "tRFC violation during Auto Refresh"
- SEVERITY WARNING;
-
- -- Precharge to Auto Refresh
- ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
- (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
- REPORT "tRP violation during Auto Refresh"
- SEVERITY WARNING;
-
- -- Precharge to Auto Refresh
- ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
- REPORT "All banks must be Precharge before Auto Refresh"
- SEVERITY WARNING;
-
- -- Record current tRFC time
- RFC_chk := NOW;
- END IF;
-
- -- Extended Load Mode Register
- IF Ext_mode_enable = '1' THEN
- IF (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') THEN
- IF (Addr (0) = '0') THEN
- DLL_enable := '1';
- ELSE
- DLL_enable := '0';
- END IF;
- END IF;
-
- -- Precharge to EMR
- ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
- REPORT "All bank must be Precharged before Extended Mode Register"
- SEVERITY WARNING;
-
- -- Precharge to EMR
- ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
- (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
- REPORT "tRP violation during Extended Load Register"
- SEVERITY WARNING;
-
- -- LMR/EMR to EMR
- ASSERT (NOW - MRD_chk >= tMRD)
- REPORT "tMRD violation during Extended Mode Register"
- SEVERITY WARNING;
-
- -- Record current tMRD time
- MRD_chk := NOW;
- END IF;
-
- -- Load Mode Register
- IF Mode_reg_enable = '1' THEN
- -- Register mode
- Mode_reg <= Addr;
-
- -- DLL Reset
- IF (DLL_enable = '1' AND Addr (8) = '1') THEN
- DLL_reset := '1';
- DLL_done := '0';
- DLL_count := 0;
- ELSIF (DLL_enable = '1' AND DLL_reset = '0' AND Addr (8) = '0') THEN
- ASSERT (FALSE)
- REPORT "DLL is ENABLE: DLL RESET is require"
- SEVERITY WARNING;
- ELSIF (DLL_enable = '0' AND Addr (8) = '1') THEN
- ASSERT (FALSE)
- REPORT "DLL is DISABLE: DLL RESET will be ignored"
- SEVERITY WARNING;
- END IF;
-
- -- Precharge to LMR
- ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
- REPORT "All bank must be Precharged before Load Mode Register"
- SEVERITY WARNING;
-
- -- Precharge to EMR
- ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
- (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
- REPORT "tRP violation during Load Mode Register"
- SEVERITY WARNING;
-
- -- LMR/ELMR to LMR
- ASSERT (NOW - MRD_chk >= tMRD)
- REPORT "tMRD violation during Load Mode Register"
- SEVERITY WARNING;
-
- -- Check for invalid Burst Length
- ASSERT ((Addr (2 DOWNTO 0) = "001") OR -- BL = 2
- (Addr (2 DOWNTO 0) = "010") OR -- BL = 4
- (Addr (2 DOWNTO 0) = "011")) -- BL = 8
- REPORT "Invalid Burst Length during Load Mode Register"
- SEVERITY WARNING;
-
- -- Check for invalid CAS Latency
- ASSERT ((Addr (6 DOWNTO 4) = "010") OR -- CL = 2.0
- (Addr (6 DOWNTO 4) = "110")) -- CL = 2.5
- REPORT "Invalid CAS Latency during Load Mode Register"
- SEVERITY WARNING;
-
- -- Record current tMRD time
- MRD_chk := NOW;
- END IF;
-
- -- Active Block (latch Bank and Row Address)
- IF Active_enable = '1' THEN
- -- Activate an OPEN bank can corrupt data
- ASSERT ((Ba = "00" AND Act_b0 = '0') OR
- (Ba = "01" AND Act_b1 = '0') OR
- (Ba = "10" AND Act_b2 = '0') OR
- (Ba = "11" AND Act_b3 = '0'))
- REPORT "Bank is already activated - data can be corrupted"
- SEVERITY WARNING;
-
- -- Activate Bank 0
- IF Ba = "00" AND Pc_b0 = '1' THEN
- -- Activate to Activate (same bank)
- ASSERT (NOW - RC_chk0 >= tRC)
- REPORT "tRC violation during Activate Bank 0"
- SEVERITY WARNING;
-
- -- Precharge to Active
- ASSERT (NOW - RP_chk0 >= tRP)
- REPORT "tRP violation during Activate Bank 0"
- SEVERITY WARNING;
-
- -- Record Variables for checking violation
- Act_b0 := '1';
- Pc_b0 := '0';
- B0_row_addr := Addr;
- RC_chk0 := NOW;
- RCD_chk0 := NOW;
- RAS_chk0 := NOW;
- RAP_chk0 := NOW;
- END IF;
-
- -- Activate Bank 1
- IF Ba = "01" AND Pc_b1 = '1' THEN
- -- Activate to Activate (same bank)
- ASSERT (NOW - RC_chk1 >= tRC)
- REPORT "tRC violation during Activate Bank 1"
- SEVERITY WARNING;
-
- -- Precharge to Active
- ASSERT (NOW - RP_chk1 >= tRP)
- REPORT "tRP violation during Activate Bank 1"
- SEVERITY WARNING;
-
- -- Record Variables for checking violation
- Act_b1 := '1';
- Pc_b1 := '0';
- B1_row_addr := Addr;
- RC_chk1 := NOW;
- RCD_chk1 := NOW;
- RAS_chk1 := NOW;
- RAP_chk1 := NOW;
- END IF;
-
- -- Activate Bank 2
- IF Ba = "10" AND Pc_b2 = '1' THEN
- -- Activate to Activate (same bank)
- ASSERT (NOW - RC_chk2 >= tRC)
- REPORT "tRC violation during Activate Bank 2"
- SEVERITY WARNING;
-
- -- Precharge to Active
- ASSERT (NOW - RP_chk2 >= tRP)
- REPORT "tRP violation during Activate Bank 2"
- SEVERITY WARNING;
-
- -- Record Variables for checking violation
- Act_b2 := '1';
- Pc_b2 := '0';
- B2_row_addr := Addr;
- RC_chk2 := NOW;
- RCD_chk2 := NOW;
- RAS_chk2 := NOW;
- RAP_chk2 := NOW;
- END IF;
-
- -- Activate Bank 3
- IF Ba = "11" AND Pc_b3 = '1' THEN
- -- Activate to Activate (same bank)
- ASSERT (NOW - RC_chk3 >= tRC)
- REPORT "tRC violation during Activate Bank 3"
- SEVERITY WARNING;
-
- -- Precharge to Active
- ASSERT (NOW - RP_chk3 >= tRP)
- REPORT "tRP violation during Activate Bank 3"
- SEVERITY WARNING;
-
- -- Record Variables for checking violation
- Act_b3 := '1';
- Pc_b3 := '0';
- B3_row_addr := Addr;
- RC_chk3 := NOW;
- RCD_chk3 := NOW;
- RAS_chk3 := NOW;
- RAP_chk3 := NOW;
- END IF;
-
- -- Activate Bank A to Activate Bank B
- IF (Prev_bank /= Ba) THEN
- ASSERT (NOW - RRD_chk >= tRRD)
- REPORT "tRRD violation during Activate"
- SEVERITY WARNING;
- END IF;
-
- -- AutoRefresh to Activate
- ASSERT (NOW - RFC_chk >= tRFC)
- REPORT "tRFC violation during Activate"
- SEVERITY WARNING;
-
- -- Record Variables for Checking Violation
- RRD_chk := NOW;
- Prev_bank := Ba;
- END IF;
-
- -- Precharge Block - Consider NOP if bank already precharged or in process of precharging
- IF Prech_enable = '1' THEN
- -- EMR or LMR to Precharge
- ASSERT (NOW - MRD_chk >= tMRD)
- REPORT "tMRD violation during Precharge"
- SEVERITY WARNING;
-
- -- Precharge Bank 0
- IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "00")) AND Act_b0 = '1') THEN
- Act_b0 := '0';
- Pc_b0 := '1';
- RP_chk0 := NOW;
-
- -- Activate to Precharge bank 0
- ASSERT (NOW - RAS_chk0 >= tRAS)
- REPORT "tRAS violation during Precharge"
- SEVERITY WARNING;
-
- -- tWR violation check for Write
- ASSERT (NOW - WR_chk0 >= tWR)
- REPORT "tWR violation during Precharge"
- SEVERITY WARNING;
- END IF;
-
- -- Precharge Bank 1
- IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "01")) AND Act_b1 = '1') THEN
- Act_b1 := '0';
- Pc_b1 := '1';
- RP_chk1 := NOW;
-
- -- Activate to Precharge
- ASSERT (NOW - RAS_chk1 >= tRAS)
- REPORT "tRAS violation during Precharge"
- SEVERITY WARNING;
-
- -- tWR violation check for Write
- ASSERT (NOW - WR_chk1 >= tWR)
- REPORT "tWR violation during Precharge"
- SEVERITY WARNING;
- END IF;
-
- -- Precharge Bank 2
- IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "10")) AND Act_b2 = '1') THEN
- Act_b2 := '0';
- Pc_b2 := '1';
- RP_chk2 := NOW;
-
- -- Activate to Precharge
- ASSERT (NOW - RAS_chk2 >= tRAS)
- REPORT "tRAS violation during Precharge"
- SEVERITY WARNING;
-
- -- tWR violation check for Write
- ASSERT (NOW - WR_chk2 >= tWR)
- REPORT "tWR violation during Precharge"
- SEVERITY WARNING;
- END IF;
-
- -- Precharge Bank 3
- IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "11")) AND Act_b3 = '1') THEN
- Act_b3 := '0';
- Pc_b3 := '1';
- RP_chk3 := NOW;
-
- -- Activate to Precharge
- ASSERT (NOW - RAS_chk3 >= tRAS)
- REPORT "tRAS violation during Precharge"
- SEVERITY WARNING;
-
- -- tWR violation check for Write
- ASSERT (NOW - WR_chk3 >= tWR)
- REPORT "tWR violation during Precharge"
- SEVERITY WARNING;
- END IF;
-
- -- Pipeline for READ
- IF CAS_latency_15 = '1' THEN
- A10_precharge (3) := Addr(10);
- Bank_precharge (3) := Ba;
- Cmnd_precharge (3) := '1';
- ELSIF CAS_latency_2 = '1' THEN
- A10_precharge (4) := Addr(10);
- Bank_precharge (4) := Ba;
- Cmnd_precharge (4) := '1';
- ELSIF CAS_latency_25 = '1' THEN
- A10_precharge (5) := Addr(10);
- Bank_precharge (5) := Ba;
- Cmnd_precharge (5) := '1';
- ELSIF CAS_latency_3 = '1' THEN
- A10_precharge (6) := Addr(10);
- Bank_precharge (6) := Ba;
- Cmnd_precharge (6) := '1';
- ELSIF CAS_latency_4 = '1' THEN
- A10_precharge (8) := Addr(10);
- Bank_precharge (8) := Ba;
- Cmnd_precharge (8) := '1';
- END IF;
- END IF;
-
- -- Burst Terminate
- IF Burst_term = '1' THEN
- -- Pipeline for Read
- IF CAS_latency_15 = '1' THEN
- Cmnd_bst (3) := '1';
- ELSIF CAS_latency_2 = '1' THEN
- Cmnd_bst (4) := '1';
- ELSIF CAS_latency_25 = '1' THEN
- Cmnd_bst (5) := '1';
- ELSIF CAS_latency_3 = '1' THEN
- Cmnd_bst (6) := '1';
- ELSIF CAS_latency_4 = '1' THEN
- Cmnd_bst (8) := '1';
- END IF;
-
- -- Terminate Write
- ASSERT (Data_in_enable = '0')
- REPORT "It's illegal to Burst Terminate a Write"
- SEVERITY WARNING;
-
- -- Terminate Read with Auto Precharge
- ASSERT (Read_precharge (0) = '0' AND Read_precharge (1) = '0' AND
- Read_precharge (2) = '0' AND Read_precharge (3) = '0')
- REPORT "It's illegal to Burst Terminate a Read with Auto Precharge"
- SEVERITY WARNING;
- END IF;
-
- -- Read Command
- IF Read_enable = '1' THEN
- -- CAS Latency Pipeline
- IF Cas_latency_15 = '1' THEN
- Read_cmnd (3) := '1';
- Read_bank (3) := Ba;
- Read_cols (3) := Addr (8 DOWNTO 0);
- ELSIF Cas_latency_2 = '1' THEN
- Read_cmnd (4) := '1';
- Read_bank (4) := Ba;
- Read_cols (4) := Addr (8 DOWNTO 0);
- ELSIF Cas_latency_25 = '1' THEN
- Read_cmnd (5) := '1';
- Read_bank (5) := Ba;
- Read_cols (5) := Addr (8 DOWNTO 0);
- ELSIF Cas_latency_3 = '1' THEN
- Read_cmnd (6) := '1';
- Read_bank (6) := Ba;
- Read_cols (6) := Addr (8 DOWNTO 0);
- ELSIF Cas_latency_4 = '1' THEN
- Read_cmnd (8) := '1';
- Read_bank (8) := Ba;
- Read_cols (8) := Addr (8 DOWNTO 0);
- END IF;
-
- -- Write to Read: Terminate Write Immediately
- IF Data_in_enable = '1' THEN
- Data_in_enable := '0';
- END IF;
-
- -- Interrupting a Read with Auto Precharge (same bank only)
- ASSERT (Read_precharge(CONV_INTEGER(Ba)) = '0')
- REPORT "It's illegal to interrupt a Read with Auto Precharge"
- SEVERITY WARNING;
-
- -- Activate to Read
- ASSERT ((Ba = "00" AND Act_b0 = '1') OR
- (Ba = "01" AND Act_b1 = '1') OR
- (Ba = "10" AND Act_b2 = '1') OR
- (Ba = "11" AND Act_b3 = '1'))
- REPORT "Bank is not Activated for Read"
- SEVERITY WARNING;
-
- -- Activate to Read without Auto Precharge
- IF Addr (10) = '0' THEN
- ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR
- (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR
- (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR
- (Ba = "11" AND NOW - RCD_chk3 >= tRCD))
- REPORT "tRCD violation during Read"
- SEVERITY WARNING;
- END IF;
-
- -- Activate to Read with Auto Precharge
- IF Addr (10) = '1' THEN
- ASSERT ((Ba = "00" AND NOW - RAP_chk0 >= tRAP) OR
- (Ba = "01" AND NOW - RAP_chk1 >= tRAP) OR
- (Ba = "10" AND NOW - RAP_chk2 >= tRAP) OR
- (Ba = "11" AND NOW - RAP_chk3 >= tRAP))
- REPORT "tRAP violation during Read"
- SEVERITY WARNING;
- END IF;
-
- -- Auto precharge
- IF Addr (10) = '1' THEN
- Read_precharge (Conv_INTEGER(Ba)) := '1';
- Count_precharge (Conv_INTEGER(Ba)) := 0;
- END IF;
-
- -- DLL Check
- IF (DLL_reset = '1') THEN
- ASSERT (DLL_done = '1')
- REPORT "DLL RESET not complete"
- SEVERITY WARNING;
- END IF;
- END IF;
-
- -- Write Command
- IF Write_enable = '1' THEN
- -- Pipeline for Write
- Write_cmnd (2) := '1';
- Write_bank (2) := Ba;
- Write_cols (2) := Addr (8 DOWNTO 0);
-
- -- Interrupting a Write with Auto Precharge (same bank only)
- ASSERT (Write_precharge(CONV_INTEGER(Ba)) = '0')
- REPORT "It's illegal to interrupt a Write with Auto Precharge"
- SEVERITY WARNING;
-
- -- Activate to Write
- ASSERT ((Ba = "00" AND Act_b0 = '1') OR
- (Ba = "01" AND Act_b1 = '1') OR
- (Ba = "10" AND Act_b2 = '1') OR
- (Ba = "11" AND Act_b3 = '1'))
- REPORT "Bank is not Activated for Write"
- SEVERITY WARNING;
-
- -- Activate to Write
- ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR
- (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR
- (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR
- (Ba = "11" AND NOW - RCD_chk3 >= tRCD))
- REPORT "tRCD violation during Write"
- SEVERITY WARNING;
-
- -- Auto precharge
- IF Addr (10) = '1' THEN
- Write_precharge (Conv_INTEGER(Ba)) := '1';
- Count_precharge (Conv_INTEGER(Ba)) := 0;
- END IF;
- END IF;
- END IF;
- END PROCESS;
-
- --
- -- Dqs Receiver
- --
- dqs_rcvrs : PROCESS
- VARIABLE Dm_temp : STD_LOGIC_VECTOR (1 DOWNTO 0);
- VARIABLE Dq_temp : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
- BEGIN
- WAIT ON Dqs;
- -- Latch data at posedge Dqs
- IF Dqs'EVENT AND Dqs (1) = '1' AND Dqs (0) = '1' THEN
- Dq_temp := Dq;
- Dm_temp := Dm;
- END IF;
- -- Latch data at negedge Dqs
- IF Dqs'EVENT AND Dqs (1) = '0' AND Dqs (0) = '0' THEN
- Dq_pair <= (Dq & Dq_temp);
- Dm_pair <= (Dm & Dm_temp);
- END IF;
- END PROCESS;
-
- --
- -- Setup timing checks
- --
- Setup_check : PROCESS
- BEGIN
- WAIT ON Sys_clk;
- IF Sys_clk'EVENT AND Sys_clk = '1' THEN
- ASSERT(Cke'LAST_EVENT >= tIS)
- REPORT "CKE Setup time violation -- tIS"
- SEVERITY WARNING;
- ASSERT(Cs_n'LAST_EVENT >= tIS)
- REPORT "CS# Setup time violation -- tIS"
- SEVERITY WARNING;
- ASSERT(Cas_n'LAST_EVENT >= tIS)
- REPORT "CAS# Setup time violation -- tIS"
- SEVERITY WARNING;
- ASSERT(Ras_n'LAST_EVENT >= tIS)
- REPORT "RAS# Setup time violation -- tIS"
- SEVERITY WARNING;
- ASSERT(We_n'LAST_EVENT >= tIS)
- REPORT "WE# Setup time violation -- tIS"
- SEVERITY WARNING;
- ASSERT(Addr'LAST_EVENT >= tIS)
- REPORT "ADDR Setup time violation -- tIS"
- SEVERITY WARNING;
- ASSERT(Ba'LAST_EVENT >= tIS)
- REPORT "BA Setup time violation -- tIS"
- SEVERITY WARNING;
- END IF;
- END PROCESS;
-
- --
- -- Hold timing checks
- --
- Hold_check : PROCESS
- BEGIN
- WAIT ON Sys_clk'DELAYED (tIH);
- IF Sys_clk'DELAYED (tIH) = '1' THEN
- ASSERT(Cke'LAST_EVENT >= tIH)
- REPORT "CKE Hold time violation -- tIH"
- SEVERITY WARNING;
- ASSERT(Cs_n'LAST_EVENT >= tIH)
- REPORT "CS# Hold time violation -- tIH"
- SEVERITY WARNING;
- ASSERT(Cas_n'LAST_EVENT >= tIH)
- REPORT "CAS# Hold time violation -- tIH"
- SEVERITY WARNING;
- ASSERT(Ras_n'LAST_EVENT >= tIH)
- REPORT "RAS# Hold time violation -- tIH"
- SEVERITY WARNING;
- ASSERT(We_n'LAST_EVENT >= tIH)
- REPORT "WE# Hold time violation -- tIH"
- SEVERITY WARNING;
- ASSERT(Addr'LAST_EVENT >= tIH)
- REPORT "ADDR Hold time violation -- tIH"
- SEVERITY WARNING;
- ASSERT(Ba'LAST_EVENT >= tIH)
- REPORT "BA Hold time violation -- tIH"
- SEVERITY WARNING;
- END IF;
- END PROCESS;
-
-END behave;
diff --git a/zpu/hdl/zpu4/src/build.xml b/zpu/hdl/zpu4/src/build.xml deleted file mode 100644 index e1b268a..0000000 --- a/zpu/hdl/zpu4/src/build.xml +++ /dev/null @@ -1,114 +0,0 @@ -<!-- - -FIX!!! start /b /wait /belownormal does not propagate return code.. ---> -<project name="ZPU3" default="all" basedir="."> - <property name="chipname" value="ic300"/> - <property name="packagetype" value="xc3s400-ft256-4"/> - - - <description>eCosBoard firmware build file</description> - - <target name="setuplibs"> - <!-- N/A yet - <copy todir="../src"> - <fileset dir="..\fpgalib\" includes="foo_top.ngc" /> - </copy> - --> - </target> - - <target name="setup"> - <mkdir dir="..\reports"/> - <mkdir dir="..\syn"/> - <mkdir dir="..\ngo"/> - <mkdir dir="..\output"/> - <mkdir dir="..\tmp"/> - <mkdir dir="..\xst"/> - </target> - - <target name="clean"> - <delete dir="..\reports"/> - <delete dir="..\syn"/> - <delete dir="..\ngo"/> - <delete dir="..\output"/> - <delete dir="..\tmp"/> - <delete dir="..\xst"/> - </target> - - <target name="synthesis" depends="setup"> - <exec executable="cmd" failonerror="true"> - <arg line="/c xst -intstyle ise -ifn xmake.xst -ofn ..\reports\1_synthesis.txt"/> - </exec> - </target> - - - <target name="translate" depends="setup"> - <exec executable="cmd" failonerror="true"> - <arg line="/c ngdbuild -intstyle ise -dd ..\ngo -uc ${chipname}.ucf -a -p ${packagetype} ..\syn\${chipname}.ngc ..\ngo\${chipname}.ngd"/> - </exec> - <move tofile="..\reports\2_translate.txt"> - <fileset dir="..\ngo" includes="${chipname}.bld"/> - </move> - </target> - - <target name="mapping" depends="setup"> - <exec executable="cmd" failonerror="true"> - <arg line="/c map -intstyle ise -p ${packagetype} -ol high -timing -detail -cm area -ignore_keep_hierarchy -pr b -k 6 -r -c 100 -tx off -o ..\ngo\${chipname}_map.ncd ..\ngo\${chipname}.ngd ..\ngo\${chipname}.pcf"/> - </exec> - <move tofile="..\reports\3_mapping.txt"> - <fileset dir="..\ngo" includes="${chipname}_map.mrp"/> - </move> - </target> - - - <target name="placeandroute" depends="setup"> - <exec executable="cmd" failonerror="true"> - <arg line="/c par -w -intstyle ise -ol high -t 1 ..\ngo\${chipname}_map.ncd ..\ngo\${chipname}.ncd ..\ngo\${chipname}.pcf"/> - </exec> - <move tofile="..\reports\4_placeandroute.txt"> - <fileset dir="..\ngo" includes="${chipname}.par"/> - </move> - <move tofile="..\reports\5_pads.txt"> - <fileset dir="..\ngo" includes="${chipname}_pad.txt"/> - </move> - </target> - - - <target name="gentime" depends="setup"> - <exec executable="cmd" failonerror="true"> - <arg line="/c trce -intstyle ise -v 3 -l 3 -a -u 100 ..\ngo\${chipname}.ncd -o ..\reports\timing.twr ..\ngo\${chipname}.pcf"/> - </exec> - <delete file="..\reports\6_timing.txt"/> - <move tofile="..\reports\6_timing.txt"> - <fileset dir="..\reports" includes="timing.twr"/> - </move> - </target> - - - <target name="genbit" depends="setup"> - <exec executable="cmd" failonerror="true"> - <arg line="/c bitgen -intstyle ise -w -f ${chipname}.bitgen ..\ngo\${chipname}.ncd"/> - </exec> - <move tofile="..\reports\7_bitgen.txt"> - <fileset dir="..\ngo" includes="${chipname}.bgn"/> - </move> - </target> - - <target name="copyfiles" depends="setup"> - <copy todir="../output"> - <fileset dir="..\ngo" includes="${chipname}.bin"/> - </copy> - <!-- - <copy tofile="${workspace_loc}\firmware\board\xeddvifpgadata.rawdata"> - <fileset dir="..\ngo" includes="${chipname}.bin"/> - </copy> - --> - </target> - - - <target name="all" depends="setuplibs,synthesis,translate,mapping,placeandroute,gentime,genbit,copyfiles"> - - </target> - - -</project>
\ No newline at end of file diff --git a/zpu/hdl/zpu4/src/ic300.bitgen b/zpu/hdl/zpu4/src/ic300.bitgen deleted file mode 100644 index 1095099..0000000 --- a/zpu/hdl/zpu4/src/ic300.bitgen +++ /dev/null @@ -1,27 +0,0 @@ --g DebugBitstream:No
--g Binary:yes
--g CRC:Enable
--g ConfigRate:50
--g CclkPin:Pullnone
--g M0Pin:Pullnone
--g M1Pin:Pullnone
--g M2Pin:Pullnone
--g ProgPin:PullUp
--g DonePin:Pullnone
--g TckPin:Pullnone
--g TdiPin:Pullnone
--g TdoPin:Pullnone
--g TmsPin:Pullnone
--g UnusedPin:Pullnone
--g UserID:0xFFFFFFFF
--g DCMShutDown:Disable
--g DCIUpdateMode:AsRequired
--g StartUpClk:CClk
--g DONE_cycle:4
--g GTS_cycle:5
--g GWE_cycle:6
--g LCK_cycle:NoWait
--g Security:Level1
--g DonePipe:No
--g DriveDone:Yes
-
diff --git a/zpu/hdl/zpu4/src/ic300.lso b/zpu/hdl/zpu4/src/ic300.lso deleted file mode 100644 index 22de730..0000000 --- a/zpu/hdl/zpu4/src/ic300.lso +++ /dev/null @@ -1 +0,0 @@ -work
diff --git a/zpu/hdl/zpu4/src/ic300.ucf b/zpu/hdl/zpu4/src/ic300.ucf deleted file mode 100644 index 4a141b9..0000000 --- a/zpu/hdl/zpu4/src/ic300.ucf +++ /dev/null @@ -1,146 +0,0 @@ -# clock inputs
-net "cpu_clk_p" loc = "R9" | iostandard=LVTTL;
-
-# input pins
-net "cpu_a_p(0)" loc = "N15" | iostandard=LVTTL;
-net "cpu_a_p(1)" loc = "P16" | iostandard=LVTTL;
-net "cpu_a_p(2)" loc = "P13" | iostandard=LVTTL;
-net "cpu_a_p(3)" loc = "N16" | iostandard=LVTTL;
-net "cpu_a_p(4)" loc = "P15" | iostandard=LVTTL;
-net "cpu_a_p(5)" loc = "R11" | iostandard=LVTTL;
-net "cpu_a_p(6)" loc = "T14" | iostandard=LVTTL;
-net "cpu_a_p(7)" loc = "R16" | iostandard=LVTTL;
-net "cpu_a_p(8)" loc = "P14" | iostandard=LVTTL;
-net "cpu_a_p(9)" loc = "T13" | iostandard=LVTTL;
-net "cpu_a_p(10)" loc = "R13" | iostandard=LVTTL;
-net "cpu_a_p(11)" loc = "P7" | iostandard=LVTTL;
-net "cpu_a_p(12)" loc = "N12" | iostandard=LVTTL;
-net "cpu_a_p(13)" loc = "R12" | iostandard=LVTTL;
-net "cpu_a_p(14)" loc = "L13" | iostandard=LVTTL;
-net "cpu_a_p(15)" loc = "K12" | iostandard=LVTTL;
-net "cpu_a_p(16)" loc = "K15" | iostandard=LVTTL;
-net "cpu_a_p(17)" loc = "T10" | iostandard=LVTTL;
-net "cpu_a_p(18)" loc = "T9" | iostandard=LVTTL;
-net "cpu_a_p(19)" loc = "N10" | iostandard=LVTTL;
-net "cpu_a_p(20)" loc = "T8" | iostandard=LVTTL;
-net "cpu_wr_n_p(0)" loc = "L15" | iostandard=LVTTL;
-net "cpu_wr_n_p(1)" loc = "N14" | iostandard=LVTTL;
-net "cpu_oe_n_p" loc = "T12" | iostandard=LVTTL;
-net "cpu_cs_n_p(1)" loc = "R3" | iostandard=LVTTL;
-net "cpu_cs_n_p(2)" loc = "M16" | iostandard=LVTTL;
-net "cpu_cs_n_p(3)" loc = "P11" | iostandard=LVTTL;
-
-#net "sdr_clk_fb_p" loc = "B8" | iostandard=SSTL2_I;
-
-# output pins
-net "cpu_fiq_p" loc = "K16" | iostandard=LVTTL;
-net "cpu_irq_p(0)" loc = "M14" | iostandard=LVTTL;
-net "cpu_irq_p(1)" loc = "J16" | iostandard=LVTTL;
-net "cpu_wait_n_p" loc = "M15" | iostandard=LVTTL;
-
-#net "sdr_clk_p" loc = "D8" | iostandard=SSTL2_I | FAST;
-#net "sdr_clk_n_p" loc = "F5" | iostandard=SSTL2_I | FAST;
-#net "cke_q_p" loc = "F4" | iostandard=SSTL2_I | FAST;
-#net "cs_qn_p" loc = "M2" | iostandard=SSTL2_I | FAST | PULLUP;
-#net "ras_qn_p" loc = "J2" | iostandard=SSTL2_I | FAST | PULLUP | NODELAY;
-#net "cas_qn_p" loc = "M3" | iostandard=SSTL2_I | FAST | PULLUP | NODELAY;
-#net "we_qn_p" loc = "K4" | iostandard=SSTL2_I | FAST | PULLUP | NODELAY;
-#net "dm_q_p(0)" loc = "L4" | iostandard=SSTL2_I | FAST;
-#net "dm_q_p(1)" loc = "E4" | iostandard=SSTL2_I | FAST;
-#net "dqs_q_p(0)" loc = "L3" | iostandard=SSTL2_I | FAST;
-#net "dqs_q_p(1)" loc = "D3" | iostandard=SSTL2_I | FAST;
-#net "ba_q_p(0)" loc = "M1" | iostandard=SSTL2_I | FAST;
-#net "ba_q_p(1)" loc = "J3" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(0)" loc = "J4" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(1)" loc = "N2" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(2)" loc = "H4" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(3)" loc = "P2" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(4)" loc = "E7" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(5)" loc = "G4" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(6)" loc = "D7" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(7)" loc = "G5" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(8)" loc = "C7" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(9)" loc = "F3" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(10)" loc = "N3" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(11)" loc = "E6" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(12)" loc = "D6" | iostandard=SSTL2_I | FAST;
-
-# bidirectional pins
-net "cpu_d_p(0)" loc = "M11" | iostandard=LVTTL;
-net "cpu_d_p(1)" loc = "N11" | iostandard=LVTTL;
-net "cpu_d_p(2)" loc = "P10" | iostandard=LVTTL;
-net "cpu_d_p(3)" loc = "R10" | iostandard=LVTTL;
-net "cpu_d_p(4)" loc = "T7" | iostandard=LVTTL;
-net "cpu_d_p(5)" loc = "R7" | iostandard=LVTTL;
-net "cpu_d_p(6)" loc = "N6" | iostandard=LVTTL;
-net "cpu_d_p(7)" loc = "M6" | iostandard=LVTTL;
-net "cpu_d_p(8)" loc = "K13" | iostandard=LVTTL;
-net "cpu_d_p(9)" loc = "M10" | iostandard=LVTTL;
-net "cpu_d_p(10)" loc = "L12" | iostandard=LVTTL;
-net "cpu_d_p(11)" loc = "M13" | iostandard=LVTTL;
-net "cpu_d_p(12)" loc = "K14" | iostandard=LVTTL;
-net "cpu_d_p(13)" loc = "L14" | iostandard=LVTTL;
-net "cpu_d_p(14)" loc = "J13" | iostandard=LVTTL;
-net "cpu_d_p(15)" loc = "J14" | iostandard=LVTTL;
-
-#net "sdr_d_p(0)" loc = "G1" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(1)" loc = "H3" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(2)" loc = "G3" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(3)" loc = "K2" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(4)" loc = "F2" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(5)" loc = "L2" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(6)" loc = "E1" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(7)" loc = "M4" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(8)" loc = "C6" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(9)" loc = "E2" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(10)" loc = "C2" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(11)" loc = "D1" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(12)" loc = "B7" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(13)" loc = "D2" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(14)" loc = "B6" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(15)" loc = "B5" | iostandard=SSTL2_I | NODELAY | FAST;
-
-# TIMING
-# Create timing names
-NET "cpu_clk_p" TNM_NET = "cpu_clk_p";
-NET "sdr_clk_fb_p" TNM_NET = "sdr_clk_fb_p";
-#NET "cpu_clk" TNM_NET = "cpu_clk";
-#NET "cpu_clk_2x" TNM_NET = "cpu_clk_2x";
-#NET "cpu_clk_4x" TNM_NET = "cpu_clk_4x";
-#NET "ddr_in_clk" TNM_NET = "ddr_in_clk";
-#NET "ddr_in_clk_2x" TNM_NET = "ddr_in_clk_2x";
-
-## Create timing
-
-# Periode timing
-TIMESPEC "TS_cpu_clk" = PERIOD "cpu_clk_p" 10 ns HIGH 50 %;
-#TIMESPEC "TS_sdr_clk_fb_p" = PERIOD "sdr_clk_fb_p" 7.8 ns HIGH 50 %;
-
-# Clock domain crossing timing
-#TIMESPEC "TS_cpu1_to_cpu2" = FROM "cpu_clk" TO "cpu_clk_2x" 7.8 ns;
-#TIMESPEC "TS_cpu1_to_cpu4" = FROM "cpu_clk" TO "cpu_clk_4x" 3.9 ns;
-#TIMESPEC "TS_cpu1_to_ddr2" = FROM "cpu_clk" TO "ddr_in_clk" 7.8 ns;
-#TIMESPEC "TS_cpu1_to_ddr2_2x" = FROM "cpu_clk" TO "ddr_in_clk_2x" 3.9 ns;
-
-#TIMESPEC "TS_cpu2_to_cpu1" = FROM "cpu_clk_2x" TO "cpu_clk" 7.8 ns;
-#TIMESPEC "TS_cpu2_to_cpu4" = FROM "cpu_clk_2x" TO "cpu_clk_4x" 3.9 ns;
-#TIMESPEC "TS_cpu2_to_ddr2" = FROM "cpu_clk_2x" TO "ddr_in_clk" 7.8 ns;
-#TIMESPEC "TS_cpu2_to_ddr_2x" = FROM "cpu_clk_2x" TO "ddr_in_clk_2x" 3.9 ns;
-
-#TIMESPEC "TS_cpu4_to_cpu1" = FROM "cpu_clk_4x" TO "cpu_clk" 3.9 ns;
-#TIMESPEC "TS_cpu4_to_cpu2" = FROM "cpu_clk_4x" TO "cpu_clk_2x" 3.9 ns;
-#TIMESPEC "TS_cpu4_to_ddr2" = FROM "cpu_clk_4x" TO "ddr_in_clk" 3.9 ns;
-#TIMESPEC "TS_cpu4_to_ddr2_2x" = FROM "cpu_clk_4x" TO "ddr_in_clk_2x" 3.9 ns;
-
-#TIMESPEC "TS_ddr2_to_cpu1" = FROM "ddr_in_clk" TO "cpu_clk" 7.8 ns;
-#TIMESPEC "TS_ddr2_to_cpu2" = FROM "ddr_in_clk" TO "cpu_clk_2x" 7.8 ns;
-#TIMESPEC "TS_ddr2_to_cpu4" = FROM "ddr_in_clk" TO "cpu_clk_4x" 3.9 ns;
-#TIMESPEC "TS_ddr2_to_ddr2_2x" = FROM "ddr_in_clk" TO "ddr_in_clk_2x" 3.9 ns;
-
-#TIMESPEC "TS_ddr2_2x_to_cpu1" = FROM "ddr_in_clk_2x" TO "cpu_clk" 3.9 ns;
-#TIMESPEC "TS_ddr2_2x_to_cpu2" = FROM "ddr_in_clk_2x" TO "cpu_clk_2x" 3.9 ns;
-#TIMESPEC "TS_ddr2_2x_to_cpu4" = FROM "ddr_in_clk_2x" TO "cpu_clk_4x" 3.9 ns;
-#TIMESPEC "TS_ddr2_2x_to_ddr2" = FROM "ddr_in_clk_2x" TO "ddr_in_clk" 3.9 ns;
-
-
-
diff --git a/zpu/hdl/zpu4/src/ic300.vhd b/zpu/hdl/zpu4/src/ic300.vhd deleted file mode 100644 index a1b4f41..0000000 --- a/zpu/hdl/zpu4/src/ic300.vhd +++ /dev/null @@ -1,144 +0,0 @@ ---------------------------------------------------------------------------------
--- Company: Zylin AS
--- Engineer: Tore Ramsland
---
--- Create Date: 21:47:41 07/03/05
--- Design Name: ic300
--- Module Name: ic300 - behave
--- Project Name: eCosBoard
--- Target Device: XC3S400400-FG256
--- Tool versions: 7.1i
--- Description: Top level
---
--- Dependencies:
---
--- Revision:
--- 2005-07-11 Updated to test FPGA
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library UNISIM;
-use UNISIM.VComponents.all;
-
-library zylin;
-use zylin.arm7.all;
-
-library zylin;
-use zylin.zpu_config.all;
-use zylin.zpupkg.all;
-
-library work;
-use work.phi_config.all;
-use work.ic300pkg.all;
-
-entity ic300 is
- generic(
- simulate_io_time : boolean := false);
- port ( -- Clock inputs
- cpu_clk_p : in std_logic;
-
- -- CPU interface signals
- cpu_a_p : in std_logic_vector(20 downto 0);
- cpu_wr_n_p : in std_logic_vector(1 downto 0);
- cpu_cs_n_p : in std_logic_vector(3 downto 1);
- cpu_oe_n_p : in std_logic;
- cpu_d_p : inout std_logic_vector(15 downto 0);
- cpu_irq_p : out std_logic_vector(1 downto 0);
- cpu_fiq_p : out std_logic;
- cpu_wait_n_p : out std_logic;
-
- -- DDR SDRAM Signals
- sdr_clk_p : out std_logic; -- ddr_sdram_clock
- sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock
- cke_q_p : out std_logic; -- clock enable
- cs_qn_p : out std_logic; -- /chip select
- ras_qn_p : inout std_logic; -- /ras
- cas_qn_p : inout std_logic; -- /cas
- we_qn_p : inout std_logic; -- /write enable
- dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00"
- dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write
- ba_q_p : out std_logic_vector(1 downto 0); -- bank select
- sdr_a_p : out std_logic_vector(12 downto 0); -- address bus
- sdr_d_p : inout std_logic_vector(15 downto 0); -- bidir data bus
- sdr_clk_fb_p : in std_logic -- DDR clock feedback
- );
-end ic300;
-
-architecture behave of ic300 is
-
-signal cpu_we : std_logic_vector(1 downto 0); -- Write signal for lower(0) and upper(1) 8 data bits
-signal cpu_re : std_logic; -- Read enable signal for all 16 bits
-signal areset : std_logic; -- Asyncronous active high reset (for initialization)
-signal areset_dummy : std_logic;
-
--- Clock module signals
-signal clk_status : std_logic_vector(2 downto 0); -- DLL lock status (from 3 DLL's)
-signal cpu_clk : std_logic; -- 64 MHz CPU clk
-signal cpu_clk_2x : std_logic; -- 128 MHz CPU clk (in phase with 64 MHz)
-signal cpu_clk_4x : std_logic; -- 256 MHz CPU clk (in phase with 64 MHz)
-signal ddr_in_clk : std_logic; -- 128 MHz clock from DDR SDRAM
-signal ddr_in_clk_2x : std_logic; -- 256 MHz clock from DDR SDRAM
- -- NOTE! Phase relation to 64 MHz clock unknown
-
--- Internal CPU interface signals
-signal cpu_din : std_logic_vector(15 downto 0); -- 16-bit data from CPU
-signal cpu_dout : std_logic_vector(15 downto 0); -- 16-bit data to CPU
-signal cpu_a : std_logic_vector(20 downto 0); -- 21-bit address from CPU
-
-begin
-
--- areset <= '0';
- areset_dummy <= '0';
-
- global_init_reset:
- rocbuf port map(I=>areset_dummy,O=>areset);
-
- allclocks:
- clocks port map(
- areset => areset,
- cpu_clk_p => cpu_clk_p,
- cpu_clk => cpu_clk,
- cpu_clk_2x => cpu_clk_2x,
- cpu_clk_4x => cpu_clk_4x,
- sdr_clk_fb_p => sdr_clk_fb_p,
- ddr_in_clk => ddr_in_clk,
- ddr_in_clk_2x => ddr_in_clk_2x,
- locked => clk_status);
-
- arm7cpu:
- arm7wb generic map (simulate_io_time => simulate_io_time)
- port map(
- areset => areset,
- cpu_clk => cpu_clk,
- cpu_clk_2x => cpu_clk_2x,
- cpu_a_p => cpu_a_p,
- cpu_wr_n_p => cpu_wr_n_p,
- cpu_cs_n_p => cpu_cs_n_p,
- cpu_oe_n_p => cpu_oe_n_p,
- cpu_d_p => cpu_d_p,
- cpu_irq_p => cpu_irq_p,
- cpu_fiq_p => cpu_fiq_p,
- cpu_wait_n_p => cpu_wait_n_p,
- cpu_din => cpu_din,
- cpu_a => cpu_a,
- cpu_we => cpu_we,
- cpu_re => cpu_re,
- cpu_dout => cpu_dout);
-
-
- cpu_fpga_regs:
- zpuio port map(
- areset => areset,
- cpu_clk => cpu_clk,
- clk_status => clk_status,
- cpu_din => cpu_din,
- cpu_a => cpu_a,
- cpu_we => cpu_we,
- cpu_re => cpu_re,
- cpu_dout => cpu_dout);
-
-
-end behave;
diff --git a/zpu/hdl/zpu4/src/ic300_config.vhd b/zpu/hdl/zpu4/src/ic300_config.vhd deleted file mode 100644 index b14ec79..0000000 --- a/zpu/hdl/zpu4/src/ic300_config.vhd +++ /dev/null @@ -1,26 +0,0 @@ -library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-package phi_config is
-
- constant Fpga_Global_Base : std_logic_vector(19 downto 17) := "000"; -- 0x0800....
- constant Clock_Stat_Reg_Addr : std_logic_vector(5 downto 2) := "0000"; -- 0x....0000
- constant Ctrl_Reg_Addr : std_logic_vector(5 downto 2) := "0001"; -- 0x....0004
- constant output_enable : std_logic_vector(5 downto 2) := "0010"; -- 0x....0008
- constant output_disable : std_logic_vector(5 downto 2) := "0011"; -- 0x....000C
- constant data_status : std_logic_vector(5 downto 2) := "0100"; -- 0x....0010
- constant set_output_data : std_logic_vector(5 downto 2) := "0101"; -- 0x....0014
- constant clear_output_data : std_logic_vector(5 downto 2) := "0110"; -- 0x....0018
- constant data_in_read : std_logic_vector(5 downto 2) := "0111"; -- 0x....001C
- constant output_status : std_logic_vector(5 downto 2) := "1000"; -- 0x....0020
- constant cpu_access_address : std_logic_vector(5 downto 2) := "1001"; -- 0x....0024
-
- constant Fpga_Ethernet_Reg_Base : std_logic_vector(19 downto 17) := "110"; -- 0x080C0000
-
- constant Fpga_DDR_Ctrl_Base : std_logic_vector(19 downto 17) := "111"; -- 0x080E....
- constant DDR_Ctrl_Reg_Addr : std_logic_vector(3 downto 2) := "00"; -- 0x....0000
- constant DDR_Mode_Reg_Addr : std_logic_vector(3 downto 2) := "01"; -- 0x....0004
- constant DDR_Page_Select_Addr : std_logic_vector(3 downto 2) := "10"; -- 0x....0008
-
-
-end phi_config;
diff --git a/zpu/hdl/zpu4/src/ic300pkg.vhd b/zpu/hdl/zpu4/src/ic300pkg.vhd deleted file mode 100644 index 13da306..0000000 --- a/zpu/hdl/zpu4/src/ic300pkg.vhd +++ /dev/null @@ -1,88 +0,0 @@ -library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-package ic300pkg is
-
- component ic300 is
- port ( -- Clock inputs
- cpu_clk_p : in std_logic;
-
- -- CPU interface signals
- cpu_a_p : in std_logic_vector(20 downto 0);
- cpu_wr_n_p : in std_logic_vector(1 downto 0);
- cpu_cs_n_p : in std_logic_vector(3 downto 1);
- cpu_oe_n_p : in std_logic;
- cpu_d_p : inout std_logic_vector(15 downto 0);
- cpu_irq_p : out std_logic_vector(1 downto 0);
- cpu_fiq_p : out std_logic;
- cpu_wait_n_p : out std_logic;
-
- -- DDR SDRAM Signals
- sdr_clk_p : out std_logic; -- ddr_sdram_clock
- sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock
- cke_q_p : out std_logic; -- clock enable
- cs_qn_p : out std_logic; -- /chip select
- ras_qn_p : inout std_logic; -- /ras
- cas_qn_p : inout std_logic; -- /cas
- we_qn_p : inout std_logic; -- /write enable
- dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00"
- dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write
- ba_q_p : out std_logic_vector(1 downto 0); -- bank select
- sdr_a_p : out std_logic_vector(12 downto 0); -- address bus
- sdr_d_p : inout std_logic_vector(15 downto 0); -- bidir data bus
- sdr_clk_fb_p : in std_logic -- DDR clock feedback
- );
- end component;
-
- component clocks is
- port ( areset : in std_logic;
- cpu_clk_p : in std_logic;
- sdr_clk_fb_p : in std_logic;
- cpu_clk : out std_logic;
- cpu_clk_2x : out std_logic;
- cpu_clk_4x : out std_logic;
- ddr_in_clk : out std_logic;
- ddr_in_clk_2x : out std_logic;
- locked : out std_logic_vector(2 downto 0));
- end component;
-
- component cpu_regs is
- port ( areset : in std_logic;
- cpu_clk : in std_logic;
- clk_status : in std_logic_vector(2 downto 0);
- cpu_din : in std_logic_vector(15 downto 0);
- cpu_a : in std_logic_vector(20 downto 0);
- cpu_we : in std_logic_vector(1 downto 0);
- cpu_re : in std_logic;
- cpu_dout : inout std_logic_vector(15 downto 0));
- end component;
-
- component ddr_bridge is
- port ( areset : in std_logic;
- cpu_clk : in std_logic;
- cpu_clk_2x : in std_logic;
- cpu_clk_4x : in std_logic;
- ddr_in_clk : in std_logic;
- ddr_in_clk_2x : in std_logic;
-
- cpu_we : in std_logic_vector(1 downto 0);
- cpu_re : in std_logic;
- cpu_din : in std_logic_vector(15 downto 0);
- cpu_a : in std_logic_vector(20 downto 0);
- cpu_dout : inout std_logic_vector(15 downto 0);
-
- sdr_clk_p : out std_logic; -- ddr_sdram_clock
- sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock
- cke_q_p : out std_logic; -- clock enable
- cs_qn_p : out std_logic; -- /chip select
- ras_qn_p : inout std_logic; -- /ras
- cas_qn_p : inout std_logic; -- /cas
- we_qn_p : inout std_logic; -- /write enable
- dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00"
- dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write
- ba_q_p : out std_logic_vector(1 downto 0); -- bank select
- sdr_a_p : out std_logic_vector(12 downto 0); -- address bus
- sdr_d_p : inout std_logic_vector(15 downto 0)); -- bidir data bus
- end component;
-
-end ic300pkg;
diff --git a/zpu/hdl/zpu4/src/xmake.filelist b/zpu/hdl/zpu4/src/xmake.filelist deleted file mode 100644 index 91e623f..0000000 --- a/zpu/hdl/zpu4/src/xmake.filelist +++ /dev/null @@ -1,12 +0,0 @@ -vhdl work "ic300_config.vhd"
-vhdl work "ic300pkg.vhd"
-vhdl zylin "zpu_config.vhd"
-vhdl zylin "zpupkg.vhd"
-vhdl zylin "zpu_core.vhd"
-vhdl work "bram.vhd"
-vhdl zylin "zpuio.vhd"
-vhdl zylin "..\dummyfpgalib\arm7\src\arm7pkg.vhd"
-vhdl zylin "..\dummyfpgalib\arm7\src\arm7wb.vhd"
-vhdl work "clocks.vhd"
-vhdl work "timer.vhd"
-vhdl work "ic300.vhd"
\ No newline at end of file diff --git a/zpu/hdl/zpu4/src/xmake.filelist.bramsmall b/zpu/hdl/zpu4/src/xmake.filelist.bramsmall deleted file mode 100644 index 141633e..0000000 --- a/zpu/hdl/zpu4/src/xmake.filelist.bramsmall +++ /dev/null @@ -1,5 +0,0 @@ -vhdl work "zpu_config.vhd"
-vhdl work "zpupkg.vhd"
-vhdl work "zpu_core_small.vhd"
-vhdl work "bram_dmips.vhd"
-vhdl work "testlut.vhd"
diff --git a/zpu/hdl/zpu4/src/xmake.xst b/zpu/hdl/zpu4/src/xmake.xst deleted file mode 100644 index bfdb23f..0000000 --- a/zpu/hdl/zpu4/src/xmake.xst +++ /dev/null @@ -1,53 +0,0 @@ -set -tmpdir ../tmp
-set -xsthdpdir ../xst
-run
--ifn xmake.filelist
--ifmt mixed
--ofn ../syn/ic300
--ofmt NGC
--p xc3s400-4-ft256
--top ic300
--opt_mode Area
--opt_level 2
--iuc NO
--lso ic300.lso
--keep_hierarchy NO
--glob_opt AllClockNets
--rtlview Yes
--read_cores YES
--write_timing_constraints NO
--cross_clock_analysis NO
--hierarchy_separator /
--bus_delimiter <>
--case maintain
--slice_utilization_ratio 100
--verilog2001 YES
--fsm_extract YES -fsm_encoding Auto
--safe_implementation No
--fsm_style lut
--ram_extract Yes
--ram_style Auto
--rom_extract Yes
--rom_style Auto
--mux_extract YES
--mux_style Auto
--decoder_extract YES
--priority_extract YES
--shreg_extract YES
--shift_extract YES
--xor_collapse YES
--resource_sharing YES
--mult_style auto
--iobuf YES
--max_fanout 500
--bufg 8
--register_duplication YES
--equivalent_register_removal NO
--register_balancing No
--slice_packing YES
--optimize_primitives NO
--use_clock_enable Yes
--use_sync_set No
--use_sync_reset No
--iob true
--slice_utilization_ratio_maxmargin 5
diff --git a/zpu/hdl/zpu4/src/zpuio_bram.vhd b/zpu/hdl/zpu4/src/zpuio_bram.vhd deleted file mode 100644 index 5d3f409..0000000 --- a/zpu/hdl/zpu4/src/zpuio_bram.vhd +++ /dev/null @@ -1,229 +0,0 @@ -library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library work;
-use work.zpu_config.all;
-use work.zpupkg.all;
-
-entity zpuio is
- port ( areset : in std_logic;
- cpu_clk : in std_logic;
- clk_status : in std_logic_vector(2 downto 0);
- cpu_din : in std_logic_vector(15 downto 0);
- cpu_a : in std_logic_vector(20 downto 0);
- cpu_we : in std_logic_vector(1 downto 0);
- cpu_re : in std_logic;
- cpu_dout : inout std_logic_vector(15 downto 0));
-end zpuio;
-
-architecture behave of zpuio is
-
-signal timer_read : std_logic_vector(7 downto 0);
---signal timer_write : std_logic_vector(7 downto 0);
-signal timer_we : std_logic;
-
-
-signal io_busy : std_logic;
-signal io_read : std_logic_vector(7 downto 0);
---signal io_write : std_logic_vector(7 downto 0);
-signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit);
-signal io_writeEnable : std_logic;
-signal Enable : std_logic;
-
-signal din : std_logic_vector(7 downto 0);
-signal dout : std_logic_vector(7 downto 0);
-signal adr : std_logic_vector(15 downto 0);
-signal break : std_logic;
-signal we : std_logic;
-signal re : std_logic;
-
-
--- uart forwarding...
-
-signal uartTXPending : std_logic;
-signal uartTXCleared : std_logic;
-signal uartData : std_logic_vector(7 downto 0);
-
-signal readingTimer : std_logic;
-
-
-
-
-signal mem_busy : std_logic;
-signal mem_read : std_logic_vector(wordSize-1 downto 0);
-signal mem_write : std_logic_vector(wordSize-1 downto 0);
-signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);
-signal mem_writeEnable : std_logic;
-signal mem_readEnable : std_logic;
-signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
-
-
-
-
---signal io_mem_read : std_logic_vector(7 downto 0);
---signal io_mem_writeEnable : std_logic;
---signal io_mem_readEnable : std_logic;
-signal io_readEnable : std_logic;
-
-
-
-
-
-begin
-
- io_addr <= mem_addr(maxAddrBit downto minAddrBit);
-
- timerinst: timer port map (
- clk => cpu_clk,
- areset => areset,
- we => timer_we,
- din => mem_write(7 downto 0),
- adr => io_addr(4 downto 2),
- dout => timer_read);
-
- zpu: zpu_core port map (
- clk => cpu_clk ,
- areset => areset,
- in_mem_busy => mem_busy,
- mem_read => mem_read,
- mem_write => mem_write,
- out_mem_addr => mem_addr,
- out_mem_writeEnable => mem_writeEnable,
- out_mem_readEnable => mem_readEnable,
- mem_writeMask => mem_writeMask,
- interrupt => '0',
- break => break);
-
-
-
-
- -- Read/write are on different addresses
- -- The registers are 8 bits and mapped to bit[7:0]
- --
- -- 0xC000 Write: Writes to UART TX FIFO (4 byte FIFO)
- -- Read : Reads from UART RX FIFO (4 byte FIFO)
- -- 0xC004 Read : UART status register
- -- Bit 0 = RX FIFO empty
- -- Bit 1 = TX FIFO full
- -- 0xA000 Skrive: LED's (8 stk.)
-
- -- 0x9000 Write: bit 0: 1= reset counter
- -- 0= counter running
- -- bit 1: 1= sample counter (when set to 1)
- -- 0=not used
- -- Read : counter bit[7:0]
- -- 0x9004 Read: counter bit [15:8]
- -- 0x9008 Read: counter bit [23:16]
- -- 0x900C Read: counter bit [31:24]
- -- 0x9010 Read: counter bit [39:32]
- -- 0x9014 Read: counter bit [47:40]
- -- 0x9018 Read: counter bit [55:48]
- -- 0x901C Read: counter bit [63:56]
- --
- -- 0x8800 Read: unsigned 8-bit integer with FPGA frequency (in MHz)
-
- fauxUart:
- process(cpu_clk, areset)
- begin
- if areset = '1' then
- io_busy <= '0';
- uartTXPending <= '0';
- timer_we <= '0';
- io_busy <= '0';
- uartData <= x"58"; -- 'X'
- readingTimer <= '0';
- elsif (cpu_clk'event and cpu_clk = '1') then
- timer_we <= '0';
- io_busy <= '0';
- if uartTXCleared = '1' then
- uartTXPending <= '0';
- end if;
-
- if io_writeEnable = '1' then
- if io_addr=x"1000" then
- -- Write to UART
- uartData <= mem_write(7 downto 0);
- uartTXPending <= '1';
- io_busy <= '1';
- elsif io_addr(12)='1' then
- timer_we <= '1';
- io_busy <= '1';
- else
- report "Illegal IO write" severity failure;
- end if;
- end if;
- if (io_readEnable = '1') then
- if io_addr=x"1001" then
- io_read <= (0=>'1', -- recieve empty
- 1 => uartTXPending, -- tx full
- others => '0');
- io_busy <= '1';
- elsif io_addr(12)='1' then
- readingTimer <= '1';
- io_busy <= '1';
- elsif io_addr(11)='1' then
- io_read <= ZPU_Frequency;
- io_busy <= '1';
- else
- report "Illegal IO read" severity failure;
- end if;
-
- else
- if (readingTimer = '1') then
- readingTimer <= '0';
- io_read <= timer_read;
- io_busy <= '0';
- else
- io_read <= (others => '1');
- end if;
- end if;
- end if;
- end process;
-
-
- forwardUARTOutputToARM:
- process(cpu_clk, areset)
- begin
- if areset = '1' then
- uartTXCleared <= '0';
- elsif (cpu_clk = '1' and cpu_clk'event) then
- if cpu_we(0) = '1' and cpu_a(3 downto 1) = "000" then
- uartTXCleared <= cpu_din(0);
- else
- uartTXCleared <= uartTXCleared;
- end if;
- end if;
- end process;
-
- cpu_dout(7 downto 0) <= uartData when (cpu_re = '1' and cpu_a(3 downto 1) = "001") else (others => 'Z');
- cpu_dout <= (0 => uartTXPending, others => '0') when (cpu_re = '1' and cpu_a(3 downto 1) = "000") else (others => 'Z');
-
- io_writeEnable <= mem_writeEnable and mem_addr(ioBit);
--- io_readEnable <= mem_readEnable and mem_addr(ioBit);
- mem_busy <= io_busy or io_readEnable;
-
- -- Memory reads either come from IO or DRAM. We need to pick the right one.
- memorycontrol:
- process(cpu_clk, areset)
- begin
- if areset = '1' then
- io_readEnable <= '0';
-
-
- elsif (cpu_clk'event and cpu_clk = '1') then
- mem_read <= (others => '0');
-
- if mem_addr(ioBit)='1' and mem_readEnable='1' then
- io_readEnable <= '1';
- end if;
- if io_readEnable='1' and io_busy='0' then
- io_readEnable <= '0';
- mem_read(7 downto 0) <= io_read;
- end if;
-
- end if;
- end process;
-
-
-end behave;
|
