diff options
| author | oharboe <oharboe> | 2008-04-15 05:58:32 +0000 |
|---|---|---|
| committer | oharboe <oharboe> | 2008-04-15 05:58:32 +0000 |
| commit | 4f29574821f2931771b30ee8e2be33030e7695a8 (patch) | |
| tree | 95833ac6dfd60cc12739957ea4a6a2ff10c6572f | |
| parent | 830f2d5f90f9a864ad76a9d43a8fcf362ac2b18e (diff) | |
| download | zpu-4f29574821f2931771b30ee8e2be33030e7695a8.zip zpu-4f29574821f2931771b30ee8e2be33030e7695a8.tar.gz | |
* zpu/simzpu_bram.do - retired.
* zpu/zpu_core_bram.vhd - retired
* zpu/hdl/zpu3 - retired
36 files changed, 5 insertions, 24291 deletions
diff --git a/zpu/ChangeLog b/zpu/ChangeLog index 8cc3b5b..e883d0d 100644 --- a/zpu/ChangeLog +++ b/zpu/ChangeLog @@ -1,3 +1,7 @@ +2008-04-15 Øyvind Harboe
+ * zpu/simzpu_bram.do - retired.
+ * zpu/zpu_core_bram.vhd - retired
+ * zpu/hdl/zpu3 - retired
2008-04-05 Øyvind Harboe
* zpu/docs/zpuphiregs.odt - ZPU Phi register overview
2008-03-06 Adam Pierce
diff --git a/zpu/hdl/zpu3/src/.cvsignore b/zpu/hdl/zpu3/src/.cvsignore deleted file mode 100644 index 760be11..0000000 --- a/zpu/hdl/zpu3/src/.cvsignore +++ /dev/null @@ -1 +0,0 @@ -xilinx_device_details.xml diff --git a/zpu/hdl/zpu3/src/build.xml b/zpu/hdl/zpu3/src/build.xml deleted file mode 100644 index e1b268a..0000000 --- a/zpu/hdl/zpu3/src/build.xml +++ /dev/null @@ -1,114 +0,0 @@ -<!-- - -FIX!!! start /b /wait /belownormal does not propagate return code.. ---> -<project name="ZPU3" default="all" basedir="."> - <property name="chipname" value="ic300"/> - <property name="packagetype" value="xc3s400-ft256-4"/> - - - <description>eCosBoard firmware build file</description> - - <target name="setuplibs"> - <!-- N/A yet - <copy todir="../src"> - <fileset dir="..\fpgalib\" includes="foo_top.ngc" /> - </copy> - --> - </target> - - <target name="setup"> - <mkdir dir="..\reports"/> - <mkdir dir="..\syn"/> - <mkdir dir="..\ngo"/> - <mkdir dir="..\output"/> - <mkdir dir="..\tmp"/> - <mkdir dir="..\xst"/> - </target> - - <target name="clean"> - <delete dir="..\reports"/> - <delete dir="..\syn"/> - <delete dir="..\ngo"/> - <delete dir="..\output"/> - <delete dir="..\tmp"/> - <delete dir="..\xst"/> - </target> - - <target name="synthesis" depends="setup"> - <exec executable="cmd" failonerror="true"> - <arg line="/c xst -intstyle ise -ifn xmake.xst -ofn ..\reports\1_synthesis.txt"/> - </exec> - </target> - - - <target name="translate" depends="setup"> - <exec executable="cmd" failonerror="true"> - <arg line="/c ngdbuild -intstyle ise -dd ..\ngo -uc ${chipname}.ucf -a -p ${packagetype} ..\syn\${chipname}.ngc ..\ngo\${chipname}.ngd"/> - </exec> - <move tofile="..\reports\2_translate.txt"> - <fileset dir="..\ngo" includes="${chipname}.bld"/> - </move> - </target> - - <target name="mapping" depends="setup"> - <exec executable="cmd" failonerror="true"> - <arg line="/c map -intstyle ise -p ${packagetype} -ol high -timing -detail -cm area -ignore_keep_hierarchy -pr b -k 6 -r -c 100 -tx off -o ..\ngo\${chipname}_map.ncd ..\ngo\${chipname}.ngd ..\ngo\${chipname}.pcf"/> - </exec> - <move tofile="..\reports\3_mapping.txt"> - <fileset dir="..\ngo" includes="${chipname}_map.mrp"/> - </move> - </target> - - - <target name="placeandroute" depends="setup"> - <exec executable="cmd" failonerror="true"> - <arg line="/c par -w -intstyle ise -ol high -t 1 ..\ngo\${chipname}_map.ncd ..\ngo\${chipname}.ncd ..\ngo\${chipname}.pcf"/> - </exec> - <move tofile="..\reports\4_placeandroute.txt"> - <fileset dir="..\ngo" includes="${chipname}.par"/> - </move> - <move tofile="..\reports\5_pads.txt"> - <fileset dir="..\ngo" includes="${chipname}_pad.txt"/> - </move> - </target> - - - <target name="gentime" depends="setup"> - <exec executable="cmd" failonerror="true"> - <arg line="/c trce -intstyle ise -v 3 -l 3 -a -u 100 ..\ngo\${chipname}.ncd -o ..\reports\timing.twr ..\ngo\${chipname}.pcf"/> - </exec> - <delete file="..\reports\6_timing.txt"/> - <move tofile="..\reports\6_timing.txt"> - <fileset dir="..\reports" includes="timing.twr"/> - </move> - </target> - - - <target name="genbit" depends="setup"> - <exec executable="cmd" failonerror="true"> - <arg line="/c bitgen -intstyle ise -w -f ${chipname}.bitgen ..\ngo\${chipname}.ncd"/> - </exec> - <move tofile="..\reports\7_bitgen.txt"> - <fileset dir="..\ngo" includes="${chipname}.bgn"/> - </move> - </target> - - <target name="copyfiles" depends="setup"> - <copy todir="../output"> - <fileset dir="..\ngo" includes="${chipname}.bin"/> - </copy> - <!-- - <copy tofile="${workspace_loc}\firmware\board\xeddvifpgadata.rawdata"> - <fileset dir="..\ngo" includes="${chipname}.bin"/> - </copy> - --> - </target> - - - <target name="all" depends="setuplibs,synthesis,translate,mapping,placeandroute,gentime,genbit,copyfiles"> - - </target> - - -</project>
\ No newline at end of file diff --git a/zpu/hdl/zpu3/src/clocks.vhd b/zpu/hdl/zpu3/src/clocks.vhd deleted file mode 100644 index a352b3c..0000000 --- a/zpu/hdl/zpu3/src/clocks.vhd +++ /dev/null @@ -1,246 +0,0 @@ -library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library UNISIM;
-use UNISIM.vcomponents.all;
-
-entity clocks is
- port ( areset : in std_logic;
- cpu_clk_p : in std_logic;
- sdr_clk_fb_p : in std_logic;
- cpu_clk : out std_logic;
- cpu_clk_2x : out std_logic;
- cpu_clk_4x : out std_logic;
- ddr_in_clk : out std_logic;
- ddr_in_clk_2x : out std_logic;
- locked : out std_logic_vector(2 downto 0));
-end clocks;
-
-architecture behave of clocks is
-
-signal low : std_logic;
-
-signal cpu_clk_in : std_logic;
-signal sdr_clk_fb_in : std_logic;
-
-signal dcm_cpu1 : std_logic;
-signal dcm_cpu2 : std_logic;
-signal dcm_cpu2_dum : std_logic;
-signal dcm_cpu4 : std_logic;
-signal dcm_ddr2 : std_logic;
-signal dcm_ddr2_2x : std_logic;
-
-signal cpu_clk_int : std_logic;
-signal cpu_clk_2x_int : std_logic;
-signal cpu_clk_2x_dum_int : std_logic;
-signal cpu_clk_4x_int : std_logic;
-signal ddr_in_clk_int : std_logic;
-signal ddr_in_clk_2x_int : std_logic;
-
-signal dcm1_locked_del : std_logic;
-signal dcm2_locked_del : std_logic;
-signal dcm2_reset : std_logic;
-signal dcm3_reset : std_logic;
-
-signal locked_int : std_logic_vector(2 downto 0);
-signal del_addr : std_logic_vector(3 downto 0);
-
-begin
-
- low <= '0';
- del_addr <= "1111";
-
- cpu_clk <= cpu_clk_int;
- cpu_clk_2x <= cpu_clk_2x_int;
- cpu_clk_4x <= cpu_clk_4x_int;
- ddr_in_clk <= ddr_in_clk_int;
- ddr_in_clk_2x <= ddr_in_clk_2x_int;
- locked <= locked_int;
-
-
- CPU_IBUFG:
- IBUFG port map (
- O => cpu_clk_in,
- I => cpu_clk_p);
-
- SDR_FB_IBUFG:
- IBUFG port map (
- O => sdr_clk_fb_in,
- I => sdr_clk_fb_p);
-
- dcm2_rst:
- SRL16 generic map (
- INIT => X"0000")
- port map (
- Q => dcm1_locked_del,
- A0 => del_addr(0),
- A1 => del_addr(1),
- A2 => del_addr(2),
- A3 => del_addr(3),
- CLK => cpu_clk_int,
- D => locked_int(0));
-
- dcm2_reset <= not(dcm1_locked_del);
-
- dcm3_rst:
- SRL16 generic map (
- INIT => X"0000")
- port map (
- Q => dcm2_locked_del,
- A0 => del_addr(0),
- A1 => del_addr(1),
- A2 => del_addr(2),
- A3 => del_addr(3),
- CLK => cpu_clk_int,
- D => locked_int(1));
-
- dcm3_reset <= not(dcm2_locked_del);
-
- cpu1_dcm:
- DCM generic map (
- CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
- -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
- CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
- CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32
- CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
- CLKIN_PERIOD => 15.625, -- Specify period of input clock
- CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
- CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
- DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
- -- an integer from 0 to 15
- DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
- DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
- DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
- FACTORY_JF => X"8080", -- FACTORY JF Values
- PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
- STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
- port map (
- CLK0 => dcm_cpu1, -- 0 degree DCM CLK ouptput
- CLK180 => open, -- 180 degree DCM CLK output
- CLK270 => open, -- 270 degree DCM CLK output
- CLK2X => dcm_cpu2, -- 2X DCM CLK output
- CLK2X180 => open, -- 2X, 180 degree DCM CLK out
- CLK90 => open, -- 90 degree DCM CLK output
- CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
- CLKFX => open, -- DCM CLK synthesis out (M/D)
- CLKFX180 => open, -- 180 degree CLK synthesis out
- LOCKED => locked_int(0), -- DCM LOCK status output
- PSDONE => open, -- Dynamic phase adjust done output
- STATUS => open, -- 8-bit DCM status bits output
- CLKFB => cpu_clk_int, -- DCM clock feedback
- CLKIN => cpu_clk_in, -- Clock input (from IBUFG, BUFG or DCM)
- PSCLK => low, -- Dynamic phase adjust clock input
- PSEN => low, -- Dynamic phase adjust enable input
- PSINCDEC => low, -- Dynamic phase adjust increment/decrement
- RST => areset); -- DCM asynchronous reset input
-
- cpu2_dcm:
- DCM generic map (
- CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
- -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
- CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
- CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32
- CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
- CLKIN_PERIOD => 7.8125, -- Specify period of input clock
- CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
- CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
- DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
- -- an integer from 0 to 15
- DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
- DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
- DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
- FACTORY_JF => X"8080", -- FACTORY JF Values
- PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
- STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
- port map (
- CLK0 => dcm_cpu2_dum, -- 0 degree DCM CLK ouptput
- CLK180 => open, -- 180 degree DCM CLK output
- CLK270 => open, -- 270 degree DCM CLK output
- CLK2X => dcm_cpu4, -- 2X DCM CLK output
- CLK2X180 => open, -- 2X, 180 degree DCM CLK out
- CLK90 => open, -- 90 degree DCM CLK output
- CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
- CLKFX => open, -- DCM CLK synthesis out (M/D)
- CLKFX180 => open, -- 180 degree CLK synthesis out
- LOCKED => locked_int(1), -- DCM LOCK status output
- PSDONE => open, -- Dynamic phase adjust done output
- STATUS => open, -- 8-bit DCM status bits output
- CLKFB => cpu_clk_2x_dum_int, -- DCM clock feedback
- CLKIN => cpu_clk_2x_int, -- Clock input (from IBUFG, BUFG or DCM)
- PSCLK => low, -- Dynamic phase adjust clock input
- PSEN => low, -- Dynamic phase adjust enable input
- PSINCDEC => low, -- Dynamic phase adjust increment/decrement
- RST => dcm2_reset); -- DCM asynchronous reset input
-
- ddr_read_dcm:
- DCM generic map (
- CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
- -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
- CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
- CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32
- CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
- CLKIN_PERIOD => 7.8125, -- Specify period of input clock
- CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift of NONE, FIXED or VARIABLE
--- CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
- CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
- DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
- -- an integer from 0 to 15
- DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
- DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
- DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
- FACTORY_JF => X"8080", -- FACTORY JF Values
- PHASE_SHIFT => 103, -- Amount of fixed phase shift from -255 to 255
--- PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
- STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
- port map (
- CLK0 => dcm_ddr2, -- 0 degree DCM CLK ouptput
- CLK180 => open, -- 180 degree DCM CLK output
- CLK270 => open, -- 270 degree DCM CLK output
- CLK2X => dcm_ddr2_2x, -- 2X DCM CLK output
- CLK2X180 => open, -- 2X, 180 degree DCM CLK out
- CLK90 => open, -- 90 degree DCM CLK output
- CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
- CLKFX => open, -- DCM CLK synthesis out (M/D)
- CLKFX180 => open, -- 180 degree CLK synthesis out
- LOCKED => locked_int(2), -- DCM LOCK status output
- PSDONE => open, -- Dynamic phase adjust done output
- STATUS => open, -- 8-bit DCM status bits output
- CLKFB => ddr_in_clk_int, -- DCM clock feedback
- CLKIN => sdr_clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM)
- PSCLK => low, -- Dynamic phase adjust clock input
- PSEN => low, -- Dynamic phase adjust enable input
- PSINCDEC => low, -- Dynamic phase adjust increment/decrement
- RST => dcm3_reset); -- DCM asynchronous reset input
-
- cpu1:
- BUFG port map (
- I => dcm_cpu1,
- O => cpu_clk_int);
-
- cpu2:
- BUFG port map (
- I => dcm_cpu2,
- O => cpu_clk_2x_int);
-
- cpu2_dum:
- BUFG port map (
- I => dcm_cpu2_dum,
- O => cpu_clk_2x_dum_int);
-
- cpu4:
- BUFG port map (
- I => dcm_cpu4,
- O => cpu_clk_4x_int);
-
- ddr_clk:
- BUFG port map (
- I => dcm_ddr2,
- O => ddr_in_clk_int);
-
- ddr_clk_2x:
- BUFG port map (
- I => dcm_ddr2_2x,
- O => ddr_in_clk_2x_int);
-
-end behave;
\ No newline at end of file diff --git a/zpu/hdl/zpu3/src/ddr_bridge.vhd b/zpu/hdl/zpu3/src/ddr_bridge.vhd deleted file mode 100644 index 7dece76..0000000 --- a/zpu/hdl/zpu3/src/ddr_bridge.vhd +++ /dev/null @@ -1,203 +0,0 @@ -library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library UNISIM;
-use UNISIM.vcomponents.all;
-
-library zylin;
-use zylin.ddr.all;
-
-library work;
-use work.phi_config.all;
-
-entity ddr_bridge is
- port ( areset : in std_logic;
- cpu_clk : in std_logic;
- cpu_clk_2x : in std_logic;
- cpu_clk_4x : in std_logic;
- ddr_in_clk : in std_logic;
- ddr_in_clk_2x : in std_logic;
-
- cpu_we : in std_logic_vector(1 downto 0);
- cpu_re : in std_logic;
- cpu_din : in std_logic_vector(15 downto 0);
- cpu_a : in std_logic_vector(20 downto 0);
- cpu_dout : inout std_logic_vector(15 downto 0);
-
- sdr_clk_p : out std_logic; -- ddr_sdram_clock
- sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock
- cke_q_p : out std_logic; -- clock enable
- cs_qn_p : out std_logic; -- /chip select
- ras_qn_p : inout std_logic; -- /ras
- cas_qn_p : inout std_logic; -- /cas
- we_qn_p : inout std_logic; -- /write enable
- dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00"
- dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write
- ba_q_p : out std_logic_vector(1 downto 0); -- bank select
- sdr_a_p : out std_logic_vector(12 downto 0); -- address bus
- sdr_d_p : inout std_logic_vector(15 downto 0)); -- bidir data bus
-end ddr_bridge;
-
-architecture behave of ddr_bridge is
-
-signal refresh_en : std_logic;
-signal ddr_command_we : std_logic;
-signal ddr_command : std_logic_vector(15 downto 0);
-
-signal ddr_req : std_logic;
-signal ddr_req_adr : std_logic_vector(23 downto 1);
-signal ddr_rd_wr_n : std_logic;
-signal ddr_req_len : std_logic;
-
-signal ddr_read_en : std_logic;
-signal ddr_write_en : std_logic;
-signal ddr_data_read : std_logic_vector(31 downto 0);
-signal ddr_data_write : std_logic_vector(35 downto 0);
-
-signal ddr_read_smp : std_logic_vector(31 downto 0);
-signal ddr_read_delay : std_logic_vector(15 downto 0);
-
-signal ddr_write_smp : std_logic_vector(15 downto 0);
-signal ddr_addr_smp : std_logic_vector(15 downto 0);
-
-signal ddr_req_type_smp : std_logic;
-signal ddr_req_on : std_logic;
-signal ddr_req_off : std_logic;
-signal ddr_req_int : std_logic;
-
-constant Sim_Delay : time := 1.0 ns;
-
-begin
-
- ddr_req_len <= '0';
- ddr_data_write <= "0000" & ddr_write_smp & ddr_write_smp;
- ddr_req_adr <= "0000000" & ddr_addr_smp;
- ddr_rd_wr_n <= ddr_req_type_smp;
- ddr_req <= ddr_req_int;
-
- process(cpu_clk, areset) -- CPU writeable registers
- begin
- if areset = '1' then
- refresh_en <= '0';
- ddr_command_we <= '0';
- ddr_command <= "0000000000000000";
- ddr_write_smp <= "0000000000000000";
- ddr_req_type_smp <= '0';
- ddr_req_on <= '0';
- elsif (cpu_clk'event and cpu_clk = '1') then
-
- if cpu_we(0) = '1' and cpu_a(19 downto 17) = Fpga_DDR_Ctrl_Base and cpu_a(3 downto 1) = DDR_Ctrl_Reg_Addr then
- refresh_en <= cpu_din(0);
- else
- refresh_en <= refresh_en;
- end if;
-
- if cpu_we(0) = '1' and cpu_a(19 downto 17) = Fpga_DDR_Ctrl_Base and cpu_a(3 downto 1) = DDR_Mode_Reg_Addr then
- ddr_command <= cpu_din;
- ddr_command_we <= '1';
- else
- ddr_command <= ddr_command;
- ddr_command_we <= '0';
- end if;
-
- if cpu_we(0) = '1' and cpu_a(19 downto 17) = Fpga_DDR_Ctrl_Base and cpu_a(3 downto 1) = DDR_Data_Reg_Addr then
- ddr_write_smp <= cpu_din;
- else
- ddr_write_smp <= ddr_write_smp;
- end if;
-
- if cpu_we(0) = '1' and cpu_a(19 downto 17) = Fpga_DDR_Ctrl_Base and cpu_a(3 downto 1) = DDR_Addr_Reg_Addr then
- ddr_addr_smp <= cpu_din;
- else
- ddr_addr_smp <= ddr_addr_smp;
- end if;
-
- if cpu_we(0) = '1' and cpu_a(19 downto 17) = Fpga_DDR_Ctrl_Base and cpu_a(3 downto 1) = DDR_Req_Reg_Addr then
- ddr_req_type_smp <= cpu_din(0);
- ddr_req_on <= '1';
- else
- ddr_req_type_smp <= ddr_req_type_smp;
- ddr_req_on <= '0';
- end if;
-
- end if;
- end process;
-
- -- CPU readable registers
- cpu_dout <= ddr_read_delay when (cpu_re = '1' and cpu_a(19 downto 17) = Fpga_DDR_Ctrl_Base and cpu_a(3 downto 1) = DDR_Data_Reg_Addr) else "ZZZZZZZZZZZZZZZZ";
-
- -- Capture data read from DDR
- process(cpu_clk_2x, areset)
- begin
- if areset = '1' then
- ddr_read_smp <= (others => '0');
- elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
- if ddr_read_en = '1' then
- ddr_read_smp <= ddr_data_read after Sim_Delay;
- else
- ddr_read_smp <= ddr_read_smp after Sim_Delay;
- end if;
- end if;
- end process;
-
- -- Move captured data from DDR to cpu_clk domain (for better routing timing)
- process(cpu_clk, areset)
- begin
- if areset = '1' then
- ddr_read_delay <= "0000000000000000";
- elsif (cpu_clk'event and cpu_clk = '1') then
- ddr_read_delay <= ddr_read_smp(15 downto 0);
- end if;
- end process;
-
- process(cpu_clk_2x, areset)
- begin
- if areset = '1' then
- ddr_req_int <= '0';
- elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
- if ddr_req_on = '1' then
- ddr_req_int <= '1' after Sim_Delay;
- elsif ddr_read_en = '1' or ddr_write_en = '1' then
- ddr_req_int <= '0' after Sim_Delay;
- else
- ddr_req_int <= ddr_req_int after Sim_Delay;
- end if;
- end if;
- end process;
-
-
- ddr_interface:
- ddr_top port map(
- areset => areset,
- cpu_clk => cpu_clk,
- cpu_clk_2x => cpu_clk_2x,
- cpu_clk_4x => cpu_clk_4x,
- ddr_in_clk => ddr_in_clk,
- ddr_in_clk_2x => ddr_in_clk_2x,
- ddr_command => ddr_command,
- ddr_command_we => ddr_command_we,
- refresh_en => refresh_en,
- ddr_data_read => ddr_data_read,
- ddr_data_write => ddr_data_write,
- ddr_req => ddr_req,
- ddr_req_adr => ddr_req_adr,
- ddr_rd_wr_n => ddr_rd_wr_n,
- ddr_req_len => ddr_req_len,
- ddr_read_en => ddr_read_en,
- ddr_write_en => ddr_write_en,
- sdr_clk_p => sdr_clk_p,
- sdr_clk_n_p => sdr_clk_n_p,
- cke_q_p => cke_q_p,
- cs_qn_p => cs_qn_p,
- ras_qn_p => ras_qn_p,
- cas_qn_p => cas_qn_p,
- we_qn_p => we_qn_p,
- dm_q_p => dm_q_p,
- dqs_q_p => dqs_q_p,
- ba_q_p => ba_q_p,
- sdr_a_p => sdr_a_p,
- sdr_d_p => sdr_d_p);
-
-
-end behave;
diff --git a/zpu/hdl/zpu3/src/dmips_ram.vhd b/zpu/hdl/zpu3/src/dmips_ram.vhd deleted file mode 100644 index f472653..0000000 --- a/zpu/hdl/zpu3/src/dmips_ram.vhd +++ /dev/null @@ -1,3824 +0,0 @@ -library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-
-
-library zylin;
-use zylin.zpu_config.all;
-use zylin.zpupkg.all;
-
-entity dualport_ram is
-port (clk : in std_logic;
- memAWriteEnable : in std_logic;
- memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
- memAWrite : in std_logic_vector(wordSize-1 downto 0);
- memARead : out std_logic_vector(wordSize-1 downto 0);
- memBWriteEnable : in std_logic;
- memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
- memBWrite : in std_logic_vector(wordSize-1 downto 0);
- memBRead : out std_logic_vector(wordSize-1 downto 0));
-end dualport_ram;
-
-architecture dualport_ram_arch of dualport_ram is
-
-
-type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
-
-shared variable ram : ram_type :=
-(
-0 => x"800b0b0b",
-1 => x"0b0b8070",
-2 => x"0b0b80e5",
-3 => x"d00c3a0b",
-4 => x"0b0bbed7",
-5 => x"04000000",
-6 => x"00000000",
-7 => x"00000000",
-8 => x"80088408",
-9 => x"88080b0b",
-10 => x"0bbfa72d",
-11 => x"880c840c",
-12 => x"800c0400",
-13 => x"00000000",
-14 => x"00000000",
-15 => x"00000000",
-16 => x"71fd0608",
-17 => x"72830609",
-18 => x"81058205",
-19 => x"832b2a83",
-20 => x"ffff0652",
-21 => x"0b0b0400",
-22 => x"00000000",
-23 => x"00000000",
-24 => x"71fd0608",
-25 => x"83ffff73",
-26 => x"83060981",
-27 => x"05820583",
-28 => x"2b2b0906",
-29 => x"7383ffff",
-30 => x"0b0b0b0b",
-31 => x"83a70400",
-32 => x"72098105",
-33 => x"72057373",
-34 => x"09060906",
-35 => x"73097306",
-36 => x"070a8106",
-37 => x"530b0b51",
-38 => x"04000000",
-39 => x"00000000",
-40 => x"72722473",
-41 => x"732e0753",
-42 => x"0b0b5104",
-43 => x"00000000",
-44 => x"00000000",
-45 => x"00000000",
-46 => x"00000000",
-47 => x"00000000",
-48 => x"71737109",
-49 => x"71068106",
-50 => x"30720a10",
-51 => x"0a720a10",
-52 => x"0a31050a",
-53 => x"81065151",
-54 => x"530b0b51",
-55 => x"04000000",
-56 => x"72722673",
-57 => x"732e0753",
-58 => x"0b0b5104",
-59 => x"00000000",
-60 => x"00000000",
-61 => x"00000000",
-62 => x"00000000",
-63 => x"00000000",
-64 => x"00000000",
-65 => x"00000000",
-66 => x"00000000",
-67 => x"00000000",
-68 => x"00000000",
-69 => x"00000000",
-70 => x"00000000",
-71 => x"00000000",
-72 => x"0b0b0b88",
-73 => x"c6040000",
-74 => x"00000000",
-75 => x"00000000",
-76 => x"00000000",
-77 => x"00000000",
-78 => x"00000000",
-79 => x"00000000",
-80 => x"720a722b",
-81 => x"0a530b0b",
-82 => x"51040000",
-83 => x"00000000",
-84 => x"00000000",
-85 => x"00000000",
-86 => x"00000000",
-87 => x"00000000",
-88 => x"72729f06",
-89 => x"0981050b",
-90 => x"0b0b88a7",
-91 => x"05040000",
-92 => x"00000000",
-93 => x"00000000",
-94 => x"00000000",
-95 => x"00000000",
-96 => x"72722aff",
-97 => x"739f062a",
-98 => x"0974090a",
-99 => x"8106ff05",
-100 => x"0607530b",
-101 => x"0b510400",
-102 => x"00000000",
-103 => x"00000000",
-104 => x"7171530b",
-105 => x"0b510406",
-106 => x"73830609",
-107 => x"81058205",
-108 => x"832b0b2b",
-109 => x"0772fc06",
-110 => x"0c515104",
-111 => x"00000000",
-112 => x"72098105",
-113 => x"72050970",
-114 => x"81050906",
-115 => x"0a810653",
-116 => x"0b0b5104",
-117 => x"00000000",
-118 => x"00000000",
-119 => x"00000000",
-120 => x"72098105",
-121 => x"72050970",
-122 => x"81050906",
-123 => x"0a098106",
-124 => x"530b0b51",
-125 => x"04000000",
-126 => x"00000000",
-127 => x"00000000",
-128 => x"71098105",
-129 => x"520b0b04",
-130 => x"00000000",
-131 => x"00000000",
-132 => x"00000000",
-133 => x"00000000",
-134 => x"00000000",
-135 => x"00000000",
-136 => x"72720981",
-137 => x"0505530b",
-138 => x"0b510400",
-139 => x"00000000",
-140 => x"00000000",
-141 => x"00000000",
-142 => x"00000000",
-143 => x"00000000",
-144 => x"72097206",
-145 => x"73730906",
-146 => x"07530b0b",
-147 => x"51040000",
-148 => x"00000000",
-149 => x"00000000",
-150 => x"00000000",
-151 => x"00000000",
-152 => x"71fc0608",
-153 => x"72830609",
-154 => x"81058305",
-155 => x"1010102a",
-156 => x"81ff0652",
-157 => x"0b0b0400",
-158 => x"00000000",
-159 => x"00000000",
-160 => x"71fc0608",
-161 => x"0b0b80e5",
-162 => x"bc738306",
-163 => x"10100508",
-164 => x"060b0b0b",
-165 => x"88ac0400",
-166 => x"00000000",
-167 => x"00000000",
-168 => x"80088408",
-169 => x"88087575",
-170 => x"0b0b0ba3",
-171 => x"fa2d5050",
-172 => x"80085688",
-173 => x"0c840c80",
-174 => x"0c510400",
-175 => x"00000000",
-176 => x"80088408",
-177 => x"88087575",
-178 => x"0b0b0ba4",
-179 => x"ca2d5050",
-180 => x"80085688",
-181 => x"0c840c80",
-182 => x"0c510400",
-183 => x"00000000",
-184 => x"72097081",
-185 => x"0509060a",
-186 => x"8106ff05",
-187 => x"70540b0b",
-188 => x"71067309",
-189 => x"727405ff",
-190 => x"05060751",
-191 => x"51510400",
-192 => x"72097081",
-193 => x"0509060a",
-194 => x"098106ff",
-195 => x"0570540b",
-196 => x"0b710673",
-197 => x"09727405",
-198 => x"ff050607",
-199 => x"51515104",
-200 => x"05ff0504",
-201 => x"00000000",
-202 => x"00000000",
-203 => x"00000000",
-204 => x"00000000",
-205 => x"00000000",
-206 => x"00000000",
-207 => x"00000000",
-208 => x"810b0b0b",
-209 => x"80e5cc0c",
-210 => x"51040000",
-211 => x"00000000",
-212 => x"00000000",
-213 => x"00000000",
-214 => x"00000000",
-215 => x"00000000",
-216 => x"71810552",
-217 => x"0b0b0400",
-218 => x"00000000",
-219 => x"00000000",
-220 => x"00000000",
-221 => x"00000000",
-222 => x"00000000",
-223 => x"00000000",
-224 => x"00000000",
-225 => x"00000000",
-226 => x"00000000",
-227 => x"00000000",
-228 => x"00000000",
-229 => x"00000000",
-230 => x"00000000",
-231 => x"00000000",
-232 => x"02840572",
-233 => x"10100552",
-234 => x"0b0b0400",
-235 => x"00000000",
-236 => x"00000000",
-237 => x"00000000",
-238 => x"00000000",
-239 => x"00000000",
-240 => x"00000000",
-241 => x"00000000",
-242 => x"00000000",
-243 => x"00000000",
-244 => x"00000000",
-245 => x"00000000",
-246 => x"00000000",
-247 => x"00000000",
-248 => x"717105ff",
-249 => x"0571530b",
-250 => x"0b510400",
-251 => x"00000000",
-252 => x"00000000",
-253 => x"00000000",
-254 => x"00000000",
-255 => x"00000000",
-256 => x"84803f80",
-257 => x"cef23f04",
-258 => x"10101010",
-259 => x"10101010",
-260 => x"10101010",
-261 => x"10101010",
-262 => x"10101010",
-263 => x"10101010",
-264 => x"10101010",
-265 => x"10101053",
-266 => x"0b0b5104",
-267 => x"7381ff06",
-268 => x"73830609",
-269 => x"81058305",
-270 => x"1010102b",
-271 => x"0772fc06",
-272 => x"0c515104",
-273 => x"3c047272",
-274 => x"80728106",
-275 => x"ff050972",
-276 => x"06057110",
-277 => x"520b0b72",
-278 => x"0a100a53",
-279 => x"0b0b72e9",
-280 => x"38515153",
-281 => x"0b0b5104",
-282 => x"70700b0b",
-283 => x"80f5c008",
-284 => x"520b0b84",
-285 => x"0b720508",
-286 => x"70810651",
-287 => x"510b0b70",
-288 => x"f2387108",
-289 => x"81ff0680",
-290 => x"0c505004",
-291 => x"70700b0b",
-292 => x"80f5c008",
-293 => x"520b0b84",
-294 => x"0b720508",
-295 => x"700a100a",
-296 => x"70810651",
-297 => x"51510b0b",
-298 => x"70ed3873",
-299 => x"720c5050",
-300 => x"0480e5cc",
-301 => x"08802ea8",
-302 => x"38838080",
-303 => x"0b0b0b80",
-304 => x"f5c00c82",
-305 => x"a0800b0b",
-306 => x"0b80f5c4",
-307 => x"0c829080",
-308 => x"0b80f5d4",
-309 => x"0c0b0b80",
-310 => x"f5c80b80",
-311 => x"f5d80c04",
-312 => x"f8808080",
-313 => x"a40b0b0b",
-314 => x"80f5c00c",
-315 => x"f8808082",
-316 => x"800b0b0b",
-317 => x"80f5c40c",
-318 => x"f8808084",
-319 => x"800b80f5",
-320 => x"d40cf880",
-321 => x"8080940b",
-322 => x"80f5d80c",
-323 => x"f8808080",
-324 => x"9c0b80f5",
-325 => x"d00cf880",
-326 => x"8080a00b",
-327 => x"80f5dc0c",
-328 => x"04f23d0d",
-329 => x"600b0b80",
-330 => x"f5c40856",
-331 => x"5d82750c",
-332 => x"8059805a",
-333 => x"800b8f3d",
-334 => x"71101017",
-335 => x"70085957",
-336 => x"5d5b8076",
-337 => x"81ff067c",
-338 => x"832b5658",
-339 => x"520b0b0b",
-340 => x"76530b0b",
-341 => x"7b5198c6",
-342 => x"3f7d7f7a",
-343 => x"72077c72",
-344 => x"07717160",
-345 => x"8105415f",
-346 => x"5d5b5957",
-347 => x"557a8724",
-348 => x"80c1380b",
-349 => x"0b80f5c4",
-350 => x"087b1010",
-351 => x"71057008",
-352 => x"58515580",
-353 => x"7681ff06",
-354 => x"7c832b56",
-355 => x"58520b0b",
-356 => x"0b76530b",
-357 => x"0b7b5198",
-358 => x"853f7d7f",
-359 => x"7a72077c",
-360 => x"72077171",
-361 => x"60810541",
-362 => x"5f5d5b59",
-363 => x"5755877b",
-364 => x"25c13876",
-365 => x"7d0c7784",
-366 => x"1e0c7c80",
-367 => x"0c903d0d",
-368 => x"04707080",
-369 => x"f5cc3351",
-370 => x"0b0b70b2",
-371 => x"3880e5d8",
-372 => x"08700852",
-373 => x"0b0b520b",
-374 => x"0b0b7080",
-375 => x"2e9a3884",
-376 => x"720580e5",
-377 => x"d80c702d",
-378 => x"80e5d808",
-379 => x"7008520b",
-380 => x"0b520b0b",
-381 => x"0b70e838",
-382 => x"810b80f5",
-383 => x"cc345050",
-384 => x"0404700b",
-385 => x"0b80f5bc",
-386 => x"08802e8e",
-387 => x"380b0b0b",
-388 => x"0b800b80",
-389 => x"2e098106",
-390 => x"83385004",
-391 => x"0b0b80f5",
-392 => x"bc510b0b",
-393 => x"0bf3d93f",
-394 => x"50040470",
-395 => x"70028f05",
-396 => x"33520b0b",
-397 => x"0b0b718a",
-398 => x"2e893871",
-399 => x"51fccd3f",
-400 => x"5050048d",
-401 => x"51fcc53f",
-402 => x"7151fcc0",
-403 => x"3f505004",
-404 => x"cd3d0db6",
-405 => x"3d707084",
-406 => x"05520b0b",
-407 => x"088cab5d",
-408 => x"56a63d5f",
-409 => x"5d807570",
-410 => x"81055733",
-411 => x"765c5559",
-412 => x"0b730b79",
-413 => x"2e80ca38",
-414 => x"8f3d5c73",
-415 => x"a52e0981",
-416 => x"0680cf38",
-417 => x"79708105",
-418 => x"5b33540b",
-419 => x"0b7380e4",
-420 => x"2e81c838",
-421 => x"7380e424",
-422 => x"80d13873",
-423 => x"80e32ea8",
-424 => x"3880520b",
-425 => x"0ba5517a",
-426 => x"2d80520b",
-427 => x"0b73517a",
-428 => x"2d821959",
-429 => x"79708105",
-430 => x"5b33540b",
-431 => x"0b73ffbb",
-432 => x"3878800c",
-433 => x"b53d0d04",
-434 => x"7c841e83",
-435 => x"72053356",
-436 => x"5e578052",
-437 => x"0b0b7351",
-438 => x"7a2d8119",
-439 => x"7a708105",
-440 => x"5c335559",
-441 => x"0b73ff93",
-442 => x"38d73973",
-443 => x"80f32e09",
-444 => x"8106ffad",
-445 => x"387c841e",
-446 => x"7108595e",
-447 => x"56807733",
-448 => x"56560b74",
-449 => x"0b762e8d",
-450 => x"38811670",
-451 => x"1870335a",
-452 => x"555677f5",
-453 => x"38ff1655",
-454 => x"807625ff",
-455 => x"97387670",
-456 => x"81055833",
-457 => x"5880520b",
-458 => x"0b77517a",
-459 => x"2d811975",
-460 => x"ff175757",
-461 => x"59807625",
-462 => x"fefa3876",
-463 => x"70810558",
-464 => x"33588052",
-465 => x"0b0b7751",
-466 => x"7a2d8119",
-467 => x"75ff1757",
-468 => x"57590b75",
-469 => x"8024c738",
-470 => x"feda397c",
-471 => x"841e7108",
-472 => x"70719f2c",
-473 => x"59530b0b",
-474 => x"595e5680",
-475 => x"7524818d",
-476 => x"38757e7d",
-477 => x"58595580",
-478 => x"57740b77",
-479 => x"2e098106",
-480 => x"bc38b07c",
-481 => x"3402b905",
-482 => x"567b0b76",
-483 => x"2e9938ff",
-484 => x"16560b0b",
-485 => x"75337870",
-486 => x"81055a34",
-487 => x"8117577b",
-488 => x"762e0981",
-489 => x"06e93880",
-490 => x"7834767e",
-491 => x"ff720557",
-492 => x"58560b0b",
-493 => x"758024fe",
-494 => x"e538fdf8",
-495 => x"398a7536",
-496 => x"0b0b80d7",
-497 => x"b005540b",
-498 => x"0b733376",
-499 => x"70810558",
-500 => x"348a7535",
-501 => x"550b0b74",
-502 => x"802effad",
-503 => x"388a7536",
-504 => x"0b0b80d7",
-505 => x"b005540b",
-506 => x"0b733376",
-507 => x"70810558",
-508 => x"348a7535",
-509 => x"550b0b74",
-510 => x"c438ff8d",
-511 => x"3974520b",
-512 => x"0b76530b",
-513 => x"0bb53dff",
-514 => x"b8055192",
-515 => x"dc3fa43d",
-516 => x"0856fedd",
-517 => x"397080c1",
-518 => x"0b81c48c",
-519 => x"34800b81",
-520 => x"c5e40c70",
-521 => x"800c5004",
-522 => x"7070800b",
-523 => x"81c48c33",
-524 => x"520b0b52",
-525 => x"0b0b0b70",
-526 => x"80c12e98",
-527 => x"387181c5",
-528 => x"e4080781",
-529 => x"c5e40c80",
-530 => x"c20b81c4",
-531 => x"90347080",
-532 => x"0c505004",
-533 => x"810b81c5",
-534 => x"e4080781",
-535 => x"c5e40c80",
-536 => x"c20b81c4",
-537 => x"90347080",
-538 => x"0c505004",
-539 => x"70707070",
-540 => x"7570088a",
-541 => x"05530b0b",
-542 => x"530b0b81",
-543 => x"c48c3351",
-544 => x"0b0b7080",
-545 => x"c12e8c38",
-546 => x"73f13870",
-547 => x"800c5050",
-548 => x"505004ff",
-549 => x"72057081",
-550 => x"c4880831",
-551 => x"740c800c",
-552 => x"50505050",
-553 => x"04fc3d0d",
-554 => x"81c49408",
-555 => x"550b0b74",
-556 => x"802e8e38",
-557 => x"76750871",
-558 => x"0c81c494",
-559 => x"0856540b",
-560 => x"0b8c1553",
-561 => x"0b0b81c4",
-562 => x"8808520b",
-563 => x"0b8a518e",
-564 => x"e93f7380",
-565 => x"0c863d0d",
-566 => x"04fb3d0d",
-567 => x"77700856",
-568 => x"56b0530b",
-569 => x"0b81c494",
-570 => x"08520b0b",
-571 => x"7451a1ff",
-572 => x"3f850b8c",
-573 => x"170c850b",
-574 => x"8c160c75",
-575 => x"08750c81",
-576 => x"c4940854",
-577 => x"0b0b7380",
-578 => x"2e8c3873",
-579 => x"08750c81",
-580 => x"c4940854",
-581 => x"0b0b8c14",
-582 => x"530b0b81",
-583 => x"c4880852",
-584 => x"0b0b8a51",
-585 => x"8e943f84",
-586 => x"1508b738",
-587 => x"860b8c16",
-588 => x"0c881552",
-589 => x"0b0b8816",
-590 => x"08518d96",
-591 => x"3f81c494",
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-3022 => x"2d646570",
-3023 => x"656e6465",
-3024 => x"6e74292c",
-3025 => x"2073616d",
-3026 => x"65206173",
-3027 => x"2061626f",
-3028 => x"76650a00",
-3029 => x"496e745f",
-3030 => x"315f4c6f",
-3031 => x"633a2020",
-3032 => x"20202020",
-3033 => x"20202020",
-3034 => x"2025640a",
-3035 => x"00000000",
-3036 => x"496e745f",
-3037 => x"325f4c6f",
-3038 => x"633a2020",
-3039 => x"20202020",
-3040 => x"20202020",
-3041 => x"2025640a",
-3042 => x"00000000",
-3043 => x"496e745f",
-3044 => x"335f4c6f",
-3045 => x"633a2020",
-3046 => x"20202020",
-3047 => x"20202020",
-3048 => x"2025640a",
-3049 => x"00000000",
-3050 => x"456e756d",
-3051 => x"5f4c6f63",
-3052 => x"3a202020",
-3053 => x"20202020",
-3054 => x"20202020",
-3055 => x"2025640a",
-3056 => x"00000000",
-3057 => x"5374725f",
-3058 => x"315f4c6f",
-3059 => x"633a2020",
-3060 => x"20202020",
-3061 => x"20202020",
-3062 => x"2025730a",
-3063 => x"00000000",
-3064 => x"20202020",
-3065 => x"20202020",
-3066 => x"73686f75",
-3067 => x"6c642062",
-3068 => x"653a2020",
-3069 => x"20444852",
-3070 => x"5953544f",
-3071 => x"4e452050",
-3072 => x"524f4752",
-3073 => x"414d2c20",
-3074 => x"31275354",
-3075 => x"20535452",
-3076 => x"494e470a",
-3077 => x"00000000",
-3078 => x"5374725f",
-3079 => x"325f4c6f",
-3080 => x"633a2020",
-3081 => x"20202020",
-3082 => x"20202020",
-3083 => x"2025730a",
-3084 => x"00000000",
-3085 => x"20202020",
-3086 => x"20202020",
-3087 => x"73686f75",
-3088 => x"6c642062",
-3089 => x"653a2020",
-3090 => x"20444852",
-3091 => x"5953544f",
-3092 => x"4e452050",
-3093 => x"524f4752",
-3094 => x"414d2c20",
-3095 => x"32274e44",
-3096 => x"20535452",
-3097 => x"494e470a",
-3098 => x"00000000",
-3099 => x"55736572",
-3100 => x"2074696d",
-3101 => x"653a2025",
-3102 => x"640a0000",
-3103 => x"4d696372",
-3104 => x"6f736563",
-3105 => x"6f6e6473",
-3106 => x"20666f72",
-3107 => x"206f6e65",
-3108 => x"2072756e",
-3109 => x"20746872",
-3110 => x"6f756768",
-3111 => x"20446872",
-3112 => x"7973746f",
-3113 => x"6e653a20",
-3114 => x"00000000",
-3115 => x"2564200a",
-3116 => x"00000000",
-3117 => x"44687279",
-3118 => x"73746f6e",
-3119 => x"65732070",
-3120 => x"65722053",
-3121 => x"65636f6e",
-3122 => x"643a2020",
-3123 => x"20202020",
-3124 => x"20202020",
-3125 => x"20202020",
-3126 => x"20202020",
-3127 => x"20202020",
-3128 => x"00000000",
-3129 => x"56415820",
-3130 => x"4d495053",
-3131 => x"20726174",
-3132 => x"696e6720",
-3133 => x"2a203130",
-3134 => x"3030203d",
-3135 => x"20256420",
-3136 => x"0a000000",
-3137 => x"50726f67",
-3138 => x"72616d20",
-3139 => x"636f6d70",
-3140 => x"696c6564",
-3141 => x"20776974",
-3142 => x"686f7574",
-3143 => x"20277265",
-3144 => x"67697374",
-3145 => x"65722720",
-3146 => x"61747472",
-3147 => x"69627574",
-3148 => x"650a0000",
-3149 => x"4d656173",
-3150 => x"75726564",
-3151 => x"2074696d",
-3152 => x"6520746f",
-3153 => x"6f20736d",
-3154 => x"616c6c20",
-3155 => x"746f206f",
-3156 => x"62746169",
-3157 => x"6e206d65",
-3158 => x"616e696e",
-3159 => x"6766756c",
-3160 => x"20726573",
-3161 => x"756c7473",
-3162 => x"0a000000",
-3163 => x"506c6561",
-3164 => x"73652069",
-3165 => x"6e637265",
-3166 => x"61736520",
-3167 => x"6e756d62",
-3168 => x"6572206f",
-3169 => x"66207275",
-3170 => x"6e730a00",
-3171 => x"44485259",
-3172 => x"53544f4e",
-3173 => x"45205052",
-3174 => x"4f475241",
-3175 => x"4d2c2033",
-3176 => x"27524420",
-3177 => x"53545249",
-3178 => x"4e470000",
-3179 => x"43000000",
-3180 => x"64756d6d",
-3181 => x"792e6578",
-3182 => x"65000000",
-3183 => x"00010202",
-3184 => x"03030303",
-3185 => x"04040404",
-3186 => x"04040404",
-3187 => x"05050505",
-3188 => x"05050505",
-3189 => x"05050505",
-3190 => x"05050505",
-3191 => x"06060606",
-3192 => x"06060606",
-3193 => x"06060606",
-3194 => x"06060606",
-3195 => x"06060606",
-3196 => x"06060606",
-3197 => x"06060606",
-3198 => x"06060606",
-3199 => x"07070707",
-3200 => x"07070707",
-3201 => x"07070707",
-3202 => x"07070707",
-3203 => x"07070707",
-3204 => x"07070707",
-3205 => x"07070707",
-3206 => x"07070707",
-3207 => x"07070707",
-3208 => x"07070707",
-3209 => x"07070707",
-3210 => x"07070707",
-3211 => x"07070707",
-3212 => x"07070707",
-3213 => x"07070707",
-3214 => x"07070707",
-3215 => x"08080808",
-3216 => x"08080808",
-3217 => x"08080808",
-3218 => x"08080808",
-3219 => x"08080808",
-3220 => x"08080808",
-3221 => x"08080808",
-3222 => x"08080808",
-3223 => x"08080808",
-3224 => x"08080808",
-3225 => x"08080808",
-3226 => x"08080808",
-3227 => x"08080808",
-3228 => x"08080808",
-3229 => x"08080808",
-3230 => x"08080808",
-3231 => x"08080808",
-3232 => x"08080808",
-3233 => x"08080808",
-3234 => x"08080808",
-3235 => x"08080808",
-3236 => x"08080808",
-3237 => x"08080808",
-3238 => x"08080808",
-3239 => x"08080808",
-3240 => x"08080808",
-3241 => x"08080808",
-3242 => x"08080808",
-3243 => x"08080808",
-3244 => x"08080808",
-3245 => x"08080808",
-3246 => x"08080808",
-3247 => x"00ffffff",
-3248 => x"ff00ffff",
-3249 => x"ffff00ff",
-3250 => x"ffffff00",
-3251 => x"00000000",
-3252 => x"00000000",
-3253 => x"00000000",
-3254 => x"00003ab8",
-3255 => x"000186a0", -- iterations
-3256 => x"00000000",
-3257 => x"00000000",
-3258 => x"00000000",
-3259 => x"00000000",
-3260 => x"00000000",
-3261 => x"00000000",
-3262 => x"00000000",
-3263 => x"00000000",
-3264 => x"00000000",
-3265 => x"00000000",
-3266 => x"00000000",
-3267 => x"00000000",
-3268 => x"00000000",
-3269 => x"ffffffff",
-3270 => x"00000000",
-3271 => x"00020000",
-3272 => x"00000000",
-3273 => x"00000000",
-3274 => x"00003320",
-3275 => x"00003320",
-3276 => x"00003328",
-3277 => x"00003328",
-3278 => x"00003330",
-3279 => x"00003330",
-3280 => x"00003338",
-3281 => x"00003338",
-3282 => x"00003340",
-3283 => x"00003340",
-3284 => x"00003348",
-3285 => x"00003348",
-3286 => x"00003350",
-3287 => x"00003350",
-3288 => x"00003358",
-3289 => x"00003358",
-3290 => x"00003360",
-3291 => x"00003360",
-3292 => x"00003368",
-3293 => x"00003368",
-3294 => x"00003370",
-3295 => x"00003370",
-3296 => x"00003378",
-3297 => x"00003378",
-3298 => x"00003380",
-3299 => x"00003380",
-3300 => x"00003388",
-3301 => x"00003388",
-3302 => x"00003390",
-3303 => x"00003390",
-3304 => x"00003398",
-3305 => x"00003398",
-3306 => x"000033a0",
-3307 => x"000033a0",
-3308 => x"000033a8",
-3309 => x"000033a8",
-3310 => x"000033b0",
-3311 => x"000033b0",
-3312 => x"000033b8",
-3313 => x"000033b8",
-3314 => x"000033c0",
-3315 => x"000033c0",
-3316 => x"000033c8",
-3317 => x"000033c8",
-3318 => x"000033d0",
-3319 => x"000033d0",
-3320 => x"000033d8",
-3321 => x"000033d8",
-3322 => x"000033e0",
-3323 => x"000033e0",
-3324 => x"000033e8",
-3325 => x"000033e8",
-3326 => x"000033f0",
-3327 => x"000033f0",
-3328 => x"000033f8",
-3329 => x"000033f8",
-3330 => x"00003400",
-3331 => x"00003400",
-3332 => x"00003408",
-3333 => x"00003408",
-3334 => x"00003410",
-3335 => x"00003410",
-3336 => x"00003418",
-3337 => x"00003418",
-3338 => x"00003420",
-3339 => x"00003420",
-3340 => x"00003428",
-3341 => x"00003428",
-3342 => x"00003430",
-3343 => x"00003430",
-3344 => x"00003438",
-3345 => x"00003438",
-3346 => x"00003440",
-3347 => x"00003440",
-3348 => x"00003448",
-3349 => x"00003448",
-3350 => x"00003450",
-3351 => x"00003450",
-3352 => x"00003458",
-3353 => x"00003458",
-3354 => x"00003460",
-3355 => x"00003460",
-3356 => x"00003468",
-3357 => x"00003468",
-3358 => x"00003470",
-3359 => x"00003470",
-3360 => x"00003478",
-3361 => x"00003478",
-3362 => x"00003480",
-3363 => x"00003480",
-3364 => x"00003488",
-3365 => x"00003488",
-3366 => x"00003490",
-3367 => x"00003490",
-3368 => x"00003498",
-3369 => x"00003498",
-3370 => x"000034a0",
-3371 => x"000034a0",
-3372 => x"000034a8",
-3373 => x"000034a8",
-3374 => x"000034b0",
-3375 => x"000034b0",
-3376 => x"000034b8",
-3377 => x"000034b8",
-3378 => x"000034c0",
-3379 => x"000034c0",
-3380 => x"000034c8",
-3381 => x"000034c8",
-3382 => x"000034d0",
-3383 => x"000034d0",
-3384 => x"000034d8",
-3385 => x"000034d8",
-3386 => x"000034e0",
-3387 => x"000034e0",
-3388 => x"000034e8",
-3389 => x"000034e8",
-3390 => x"000034f0",
-3391 => x"000034f0",
-3392 => x"000034f8",
-3393 => x"000034f8",
-3394 => x"00003500",
-3395 => x"00003500",
-3396 => x"00003508",
-3397 => x"00003508",
-3398 => x"00003510",
-3399 => x"00003510",
-3400 => x"00003518",
-3401 => x"00003518",
-3402 => x"00003520",
-3403 => x"00003520",
-3404 => x"00003528",
-3405 => x"00003528",
-3406 => x"00003530",
-3407 => x"00003530",
-3408 => x"00003538",
-3409 => x"00003538",
-3410 => x"00003540",
-3411 => x"00003540",
-3412 => x"00003548",
-3413 => x"00003548",
-3414 => x"00003550",
-3415 => x"00003550",
-3416 => x"00003558",
-3417 => x"00003558",
-3418 => x"00003560",
-3419 => x"00003560",
-3420 => x"00003568",
-3421 => x"00003568",
-3422 => x"00003570",
-3423 => x"00003570",
-3424 => x"00003578",
-3425 => x"00003578",
-3426 => x"00003580",
-3427 => x"00003580",
-3428 => x"00003588",
-3429 => x"00003588",
-3430 => x"00003590",
-3431 => x"00003590",
-3432 => x"00003598",
-3433 => x"00003598",
-3434 => x"000035a0",
-3435 => x"000035a0",
-3436 => x"000035a8",
-3437 => x"000035a8",
-3438 => x"000035b0",
-3439 => x"000035b0",
-3440 => x"000035b8",
-3441 => x"000035b8",
-3442 => x"000035c0",
-3443 => x"000035c0",
-3444 => x"000035c8",
-3445 => x"000035c8",
-3446 => x"000035d0",
-3447 => x"000035d0",
-3448 => x"000035d8",
-3449 => x"000035d8",
-3450 => x"000035e0",
-3451 => x"000035e0",
-3452 => x"000035e8",
-3453 => x"000035e8",
-3454 => x"000035f0",
-3455 => x"000035f0",
-3456 => x"000035f8",
-3457 => x"000035f8",
-3458 => x"00003600",
-3459 => x"00003600",
-3460 => x"00003608",
-3461 => x"00003608",
-3462 => x"00003610",
-3463 => x"00003610",
-3464 => x"00003618",
-3465 => x"00003618",
-3466 => x"00003620",
-3467 => x"00003620",
-3468 => x"00003628",
-3469 => x"00003628",
-3470 => x"00003630",
-3471 => x"00003630",
-3472 => x"00003638",
-3473 => x"00003638",
-3474 => x"00003640",
-3475 => x"00003640",
-3476 => x"00003648",
-3477 => x"00003648",
-3478 => x"00003650",
-3479 => x"00003650",
-3480 => x"00003658",
-3481 => x"00003658",
-3482 => x"00003660",
-3483 => x"00003660",
-3484 => x"00003668",
-3485 => x"00003668",
-3486 => x"00003670",
-3487 => x"00003670",
-3488 => x"00003678",
-3489 => x"00003678",
-3490 => x"00003680",
-3491 => x"00003680",
-3492 => x"00003688",
-3493 => x"00003688",
-3494 => x"00003690",
-3495 => x"00003690",
-3496 => x"00003698",
-3497 => x"00003698",
-3498 => x"000036a0",
-3499 => x"000036a0",
-3500 => x"000036a8",
-3501 => x"000036a8",
-3502 => x"000036b0",
-3503 => x"000036b0",
-3504 => x"000036b8",
-3505 => x"000036b8",
-3506 => x"000036c0",
-3507 => x"000036c0",
-3508 => x"000036c8",
-3509 => x"000036c8",
-3510 => x"000036d0",
-3511 => x"000036d0",
-3512 => x"000036d8",
-3513 => x"000036d8",
-3514 => x"000036e0",
-3515 => x"000036e0",
-3516 => x"000036e8",
-3517 => x"000036e8",
-3518 => x"000036f0",
-3519 => x"000036f0",
-3520 => x"000036f8",
-3521 => x"000036f8",
-3522 => x"00003700",
-3523 => x"00003700",
-3524 => x"00003708",
-3525 => x"00003708",
-3526 => x"00003710",
-3527 => x"00003710",
-3528 => x"00003718",
-3529 => x"00003718",
-3530 => x"0000372c",
-3531 => x"00000000",
-3532 => x"00003994",
-3533 => x"000039f0",
-3534 => x"00003a4c",
-3535 => x"00000000",
-3536 => x"00000000",
-3537 => x"00000000",
-3538 => x"00000000",
-3539 => x"00000000",
-3540 => x"00000000",
-3541 => x"00000000",
-3542 => x"00000000",
-3543 => x"00000000",
-3544 => x"000031ac",
-3545 => x"00000000",
-3546 => x"00000000",
-3547 => x"00000000",
-3548 => x"00000000",
-3549 => x"00000000",
-3550 => x"00000000",
-3551 => x"00000000",
-3552 => x"00000000",
-3553 => x"00000000",
-3554 => x"00000000",
-3555 => x"00000000",
-3556 => x"00000000",
-3557 => x"00000000",
-3558 => x"00000000",
-3559 => x"00000000",
-3560 => x"00000000",
-3561 => x"00000000",
-3562 => x"00000000",
-3563 => x"00000000",
-3564 => x"00000000",
-3565 => x"00000000",
-3566 => x"00000000",
-3567 => x"00000000",
-3568 => x"00000000",
-3569 => x"00000000",
-3570 => x"00000000",
-3571 => x"00000000",
-3572 => x"00000000",
-3573 => x"00000001",
-3574 => x"330eabcd",
-3575 => x"1234e66d",
-3576 => x"deec0005",
-3577 => x"000b0000",
-3578 => x"00000000",
-3579 => x"00000000",
-3580 => x"00000000",
-3581 => x"00000000",
-3582 => x"00000000",
-3583 => x"00000000",
-3584 => x"00000000",
-3585 => x"00000000",
-3586 => x"00000000",
-3587 => x"00000000",
-3588 => x"00000000",
-3589 => x"00000000",
-3590 => x"00000000",
-3591 => x"00000000",
-3592 => x"00000000",
-3593 => x"00000000",
-3594 => x"00000000",
-3595 => x"00000000",
-3596 => x"00000000",
-3597 => x"00000000",
-3598 => x"00000000",
-3599 => x"00000000",
-3600 => x"00000000",
-3601 => x"00000000",
-3602 => x"00000000",
-3603 => x"00000000",
-3604 => x"00000000",
-3605 => x"00000000",
-3606 => x"00000000",
-3607 => x"00000000",
-3608 => x"00000000",
-3609 => x"00000000",
-3610 => x"00000000",
-3611 => x"00000000",
-3612 => x"00000000",
-3613 => x"00000000",
-3614 => x"00000000",
-3615 => x"00000000",
-3616 => x"00000000",
-3617 => x"00000000",
-3618 => x"00000000",
-3619 => x"00000000",
-3620 => x"00000000",
-3621 => x"00000000",
-3622 => x"00000000",
-3623 => x"00000000",
-3624 => x"00000000",
-3625 => x"00000000",
-3626 => x"00000000",
-3627 => x"00000000",
-3628 => x"00000000",
-3629 => x"00000000",
-3630 => x"00000000",
-3631 => x"00000000",
-3632 => x"00000000",
-3633 => x"00000000",
-3634 => x"00000000",
-3635 => x"00000000",
-3636 => x"00000000",
-3637 => x"00000000",
-3638 => x"00000000",
-3639 => x"00000000",
-3640 => x"00000000",
-3641 => x"00000000",
-3642 => x"00000000",
-3643 => x"00000000",
-3644 => x"00000000",
-3645 => x"00000000",
-3646 => x"00000000",
-3647 => x"00000000",
-3648 => x"00000000",
-3649 => x"00000000",
-3650 => x"00000000",
-3651 => x"00000000",
-3652 => x"00000000",
-3653 => x"00000000",
-3654 => x"00000000",
-3655 => x"00000000",
-3656 => x"00000000",
-3657 => x"00000000",
-3658 => x"00000000",
-3659 => x"00000000",
-3660 => x"00000000",
-3661 => x"00000000",
-3662 => x"00000000",
-3663 => x"00000000",
-3664 => x"00000000",
-3665 => x"00000000",
-3666 => x"00000000",
-3667 => x"00000000",
-3668 => x"00000000",
-3669 => x"00000000",
-3670 => x"00000000",
-3671 => x"00000000",
-3672 => x"00000000",
-3673 => x"00000000",
-3674 => x"00000000",
-3675 => x"00000000",
-3676 => x"00000000",
-3677 => x"00000000",
-3678 => x"00000000",
-3679 => x"00000000",
-3680 => x"00000000",
-3681 => x"00000000",
-3682 => x"00000000",
-3683 => x"00000000",
-3684 => x"00000000",
-3685 => x"00000000",
-3686 => x"00000000",
-3687 => x"00000000",
-3688 => x"00000000",
-3689 => x"00000000",
-3690 => x"00000000",
-3691 => x"00000000",
-3692 => x"00000000",
-3693 => x"00000000",
-3694 => x"00000000",
-3695 => x"00000000",
-3696 => x"00000000",
-3697 => x"00000000",
-3698 => x"00000000",
-3699 => x"00000000",
-3700 => x"00000000",
-3701 => x"00000000",
-3702 => x"00000000",
-3703 => x"00000000",
-3704 => x"00000000",
-3705 => x"00000000",
-3706 => x"00000000",
-3707 => x"00000000",
-3708 => x"00000000",
-3709 => x"00000000",
-3710 => x"00000000",
-3711 => x"00000000",
-3712 => x"00000000",
-3713 => x"00000000",
-3714 => x"00000000",
-3715 => x"00000000",
-3716 => x"00000000",
-3717 => x"00000000",
-3718 => x"00000000",
-3719 => x"00000000",
-3720 => x"00000000",
-3721 => x"00000000",
-3722 => x"00000000",
-3723 => x"00000000",
-3724 => x"00000000",
-3725 => x"00000000",
-3726 => x"00000000",
-3727 => x"00000000",
-3728 => x"00000000",
-3729 => x"00000000",
-3730 => x"00000000",
-3731 => x"00000000",
-3732 => x"00000000",
-3733 => x"00000000",
-3734 => x"00000000",
-3735 => x"00000000",
-3736 => x"00000000",
-3737 => x"00000000",
-3738 => x"00000000",
-3739 => x"00000000",
-3740 => x"00000000",
-3741 => x"00000000",
-3742 => x"00000000",
-3743 => x"00000000",
-3744 => x"00000000",
-3745 => x"00000000",
-3746 => x"00000000",
-3747 => x"00000000",
-3748 => x"00000000",
-3749 => x"00000000",
-3750 => x"00000000",
-3751 => x"00000000",
-3752 => x"00000000",
-3753 => x"00000000",
-3754 => x"000031b0",
-3755 => x"ffffffff",
-3756 => x"00000000",
-3757 => x"ffffffff",
-3758 => x"00000000",
- others => x"00000000"
-);
-
-begin
-
-process (clk)
-begin
- if (clk'event and clk = '1') then
- if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then
- report "write collision" severity failure;
- end if;
-
- if (memAWriteEnable = '1') then
- ram(conv_integer(memAAddr)) := memAWrite;
- memARead <= memAWrite;
- else
- memARead <= ram(conv_integer(memAAddr));
- end if;
- end if;
-end process;
-
-process (clk)
-begin
- if (clk'event and clk = '1') then
- if (memBWriteEnable = '1') then
- ram(conv_integer(memBAddr)) := memBWrite;
- memBRead <= memBWrite;
- else
- memBRead <= ram(conv_integer(memBAddr));
- end if;
- end if;
-end process;
-
-
-
-
-end dualport_ram_arch;
diff --git a/zpu/hdl/zpu3/src/dualport_ram.vhd b/zpu/hdl/zpu3/src/dualport_ram.vhd deleted file mode 100644 index 54380ce..0000000 --- a/zpu/hdl/zpu3/src/dualport_ram.vhd +++ /dev/null @@ -1,4996 +0,0 @@ -library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-
-
-library zylin;
-use zylin.zpu_config.all;
-use zylin.zpupkg.all;
-
-entity dualport_ram is
-port (clk : in std_logic;
- memAWriteEnable : in std_logic;
- memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
- memAWrite : in std_logic_vector(wordSize-1 downto 0);
- memARead : out std_logic_vector(wordSize-1 downto 0);
- memBWriteEnable : in std_logic;
- memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
- memBWrite : in std_logic_vector(wordSize-1 downto 0);
- memBRead : out std_logic_vector(wordSize-1 downto 0));
-end dualport_ram;
-
-architecture dualport_ram_arch of dualport_ram is
-
-
-type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
-
-shared variable ram : ram_type :=
-(
-0 => x"800b0b0b",
-1 => x"0b0b8070",
-2 => x"0b0b818a",
-3 => x"880c3a0b",
-4 => x"0b80fae8",
-5 => x"04000000",
-6 => x"00000000",
-7 => x"00000000",
-8 => x"80088408",
-9 => x"88080b0b",
-10 => x"80fbba2d",
-11 => x"880c840c",
-12 => x"800c0400",
-13 => x"00000000",
-14 => x"00000000",
-15 => x"00000000",
-16 => x"71fd0608",
-17 => x"72830609",
-18 => x"81058205",
-19 => x"832b2a83",
-20 => x"ffff0652",
-21 => x"04000000",
-22 => x"00000000",
-23 => x"00000000",
-24 => x"71fd0608",
-25 => x"83ffff73",
-26 => x"83060981",
-27 => x"05820583",
-28 => x"2b2b0906",
-29 => x"7383ffff",
-30 => x"0b0b0b0b",
-31 => x"83a70400",
-32 => x"72098105",
-33 => x"72057373",
-34 => x"09060906",
-35 => x"73097306",
-36 => x"070a8106",
-37 => x"530b0b51",
-38 => x"04000000",
-39 => x"00000000",
-40 => x"72722473",
-41 => x"732e0753",
-42 => x"0b0b5104",
-43 => x"00000000",
-44 => x"00000000",
-45 => x"00000000",
-46 => x"00000000",
-47 => x"00000000",
-48 => x"71737109",
-49 => x"71068106",
-50 => x"30720a10",
-51 => x"0a720a10",
-52 => x"0a31050a",
-53 => x"81065151",
-54 => x"530b0b51",
-55 => x"04000000",
-56 => x"72722673",
-57 => x"732e0753",
-58 => x"0b0b5104",
-59 => x"00000000",
-60 => x"00000000",
-61 => x"00000000",
-62 => x"00000000",
-63 => x"00000000",
-64 => x"00000000",
-65 => x"00000000",
-66 => x"00000000",
-67 => x"00000000",
-68 => x"00000000",
-69 => x"00000000",
-70 => x"00000000",
-71 => x"00000000",
-72 => x"72728072",
-73 => x"8106ff05",
-74 => x"09720605",
-75 => x"71105272",
-76 => x"0a100a53",
-77 => x"0b0b72eb",
-78 => x"38515153",
-79 => x"0b0b5104",
-80 => x"720a722b",
-81 => x"0a530b0b",
-82 => x"51040000",
-83 => x"00000000",
-84 => x"00000000",
-85 => x"00000000",
-86 => x"00000000",
-87 => x"00000000",
-88 => x"72729f06",
-89 => x"0981050b",
-90 => x"0b0b88a7",
-91 => x"05040000",
-92 => x"00000000",
-93 => x"00000000",
-94 => x"00000000",
-95 => x"00000000",
-96 => x"72722aff",
-97 => x"739f062a",
-98 => x"0974090a",
-99 => x"8106ff05",
-100 => x"0607530b",
-101 => x"0b510400",
-102 => x"00000000",
-103 => x"00000000",
-104 => x"7171530b",
-105 => x"0b510406",
-106 => x"73830609",
-107 => x"81058205",
-108 => x"832b0b2b",
-109 => x"0772fc06",
-110 => x"0c515104",
-111 => x"00000000",
-112 => x"72098105",
-113 => x"72050970",
-114 => x"81050906",
-115 => x"0a810653",
-116 => x"0b0b5104",
-117 => x"00000000",
-118 => x"00000000",
-119 => x"00000000",
-120 => x"72098105",
-121 => x"72050970",
-122 => x"81050906",
-123 => x"0a098106",
-124 => x"530b0b51",
-125 => x"04000000",
-126 => x"00000000",
-127 => x"00000000",
-128 => x"71098105",
-129 => x"52040000",
-130 => x"00000000",
-131 => x"00000000",
-132 => x"00000000",
-133 => x"00000000",
-134 => x"00000000",
-135 => x"00000000",
-136 => x"72720981",
-137 => x"0505530b",
-138 => x"0b510400",
-139 => x"00000000",
-140 => x"00000000",
-141 => x"00000000",
-142 => x"00000000",
-143 => x"00000000",
-144 => x"72097206",
-145 => x"73730906",
-146 => x"07530b0b",
-147 => x"51040000",
-148 => x"00000000",
-149 => x"00000000",
-150 => x"00000000",
-151 => x"00000000",
-152 => x"71fc0608",
-153 => x"72830609",
-154 => x"81058305",
-155 => x"1010102a",
-156 => x"81ff0652",
-157 => x"04000000",
-158 => x"00000000",
-159 => x"00000000",
-160 => x"71fc0608",
-161 => x"0b0b8189",
-162 => x"f4738306",
-163 => x"10100508",
-164 => x"060b0b0b",
-165 => x"88ac0400",
-166 => x"00000000",
-167 => x"00000000",
-168 => x"80088408",
-169 => x"88087575",
-170 => x"0b0b0b8f",
-171 => x"e42d5050",
-172 => x"80085688",
-173 => x"0c840c80",
-174 => x"0c510400",
-175 => x"00000000",
-176 => x"80088408",
-177 => x"88087575",
-178 => x"0b0b0b91",
-179 => x"9c2d5050",
-180 => x"80085688",
-181 => x"0c840c80",
-182 => x"0c510400",
-183 => x"00000000",
-184 => x"72097081",
-185 => x"0509060a",
-186 => x"8106ff05",
-187 => x"70540b0b",
-188 => x"71067309",
-189 => x"727405ff",
-190 => x"05060751",
-191 => x"51510400",
-192 => x"72097081",
-193 => x"0509060a",
-194 => x"098106ff",
-195 => x"0570540b",
-196 => x"0b710673",
-197 => x"09727405",
-198 => x"ff050607",
-199 => x"51515104",
-200 => x"05ff0504",
-201 => x"00000000",
-202 => x"00000000",
-203 => x"00000000",
-204 => x"00000000",
-205 => x"00000000",
-206 => x"00000000",
-207 => x"00000000",
-208 => x"810b0b0b",
-209 => x"818a840c",
-210 => x"51040000",
-211 => x"00000000",
-212 => x"00000000",
-213 => x"00000000",
-214 => x"00000000",
-215 => x"00000000",
-216 => x"71810552",
-217 => x"04000000",
-218 => x"00000000",
-219 => x"00000000",
-220 => x"00000000",
-221 => x"00000000",
-222 => x"00000000",
-223 => x"00000000",
-224 => x"00000000",
-225 => x"00000000",
-226 => x"00000000",
-227 => x"00000000",
-228 => x"00000000",
-229 => x"00000000",
-230 => x"00000000",
-231 => x"00000000",
-232 => x"02840572",
-233 => x"10100552",
-234 => x"04000000",
-235 => x"00000000",
-236 => x"00000000",
-237 => x"00000000",
-238 => x"00000000",
-239 => x"00000000",
-240 => x"00000000",
-241 => x"00000000",
-242 => x"00000000",
-243 => x"00000000",
-244 => x"00000000",
-245 => x"00000000",
-246 => x"00000000",
-247 => x"00000000",
-248 => x"717105ff",
-249 => x"0571530b",
-250 => x"0b510400",
-251 => x"00000000",
-252 => x"00000000",
-253 => x"00000000",
-254 => x"00000000",
-255 => x"00000000",
-256 => x"83cd3f80",
-257 => x"fd803f04",
-258 => x"10101010",
-259 => x"10101010",
-260 => x"10101010",
-261 => x"10101010",
-262 => x"10101010",
-263 => x"10101010",
-264 => x"10101010",
-265 => x"10101053",
-266 => x"0b0b5104",
-267 => x"7381ff06",
-268 => x"73830609",
-269 => x"81058305",
-270 => x"1010102b",
-271 => x"0772fc06",
-272 => x"0c515104",
-273 => x"3c047070",
-274 => x"0b0b819a",
-275 => x"90085284",
-276 => x"0b720508",
-277 => x"70810651",
-278 => x"510b0b70",
-279 => x"f2387108",
-280 => x"81ff0680",
-281 => x"0c505004",
-282 => x"70700b0b",
-283 => x"819a9008",
-284 => x"52840b72",
-285 => x"0508700a",
-286 => x"100a7081",
-287 => x"06515151",
-288 => x"0b0b70ed",
-289 => x"3873720c",
-290 => x"50500481",
-291 => x"8a840880",
-292 => x"2ea83883",
-293 => x"80800b0b",
-294 => x"0b819a90",
-295 => x"0c82a080",
-296 => x"0b0b0b81",
-297 => x"9a940c82",
-298 => x"90800b81",
-299 => x"9aa40c0b",
-300 => x"0b819a98",
-301 => x"0b819aa8",
-302 => x"0c04f880",
-303 => x"8080a40b",
-304 => x"0b0b819a",
-305 => x"900cf880",
-306 => x"8082800b",
-307 => x"0b0b819a",
-308 => x"940cf880",
-309 => x"8084800b",
-310 => x"819aa40c",
-311 => x"f8808080",
-312 => x"940b819a",
-313 => x"a80cf880",
-314 => x"80809c0b",
-315 => x"819aa00c",
-316 => x"f8808080",
-317 => x"a00b819a",
-318 => x"ac0c04f2",
-319 => x"3d0d600b",
-320 => x"0b819a94",
-321 => x"08565d82",
-322 => x"750c8059",
-323 => x"805a800b",
-324 => x"8f3d7110",
-325 => x"10177008",
-326 => x"5a575d5b",
-327 => x"807781ff",
-328 => x"067c832b",
-329 => x"5658520b",
-330 => x"76530b0b",
-331 => x"7b5183ae",
-332 => x"3f7d7f7a",
-333 => x"72077c72",
-334 => x"07717160",
-335 => x"8105415f",
-336 => x"5d5b5957",
-337 => x"557a8724",
-338 => x"bf380b0b",
-339 => x"819a9408",
-340 => x"7b101071",
-341 => x"05700859",
-342 => x"51558077",
-343 => x"81ff067c",
-344 => x"832b5658",
-345 => x"520b7653",
-346 => x"0b0b7b51",
-347 => x"82f03f7d",
-348 => x"7f7a7207",
-349 => x"7c720771",
-350 => x"71608105",
-351 => x"415f5d5b",
-352 => x"59575587",
-353 => x"7b25c338",
-354 => x"767d0c77",
-355 => x"841e0c7c",
-356 => x"800c903d",
-357 => x"0d047070",
-358 => x"819a9c33",
-359 => x"510b0b70",
-360 => x"aa38818a",
-361 => x"90087008",
-362 => x"52520b70",
-363 => x"802e9638",
-364 => x"84720581",
-365 => x"8a900c70",
-366 => x"2d818a90",
-367 => x"08700852",
-368 => x"520b70ec",
-369 => x"38810b81",
-370 => x"9a9c3450",
-371 => x"50040470",
-372 => x"0b0b819a",
-373 => x"8c08802e",
-374 => x"8e380b0b",
-375 => x"0b0b800b",
-376 => x"802e0981",
-377 => x"06833850",
-378 => x"040b0b81",
-379 => x"9a8c510b",
-380 => x"0b0bf48c",
-381 => x"3f500404",
-382 => x"8c08028c",
-383 => x"0cfa3d0d",
-384 => x"800b8c08",
-385 => x"fc050c8c",
-386 => x"08fc0508",
-387 => x"892481b9",
-388 => x"388c08f0",
-389 => x"05705253",
-390 => x"0b0bfddf",
-391 => x"3f8c08f4",
-392 => x"05088c08",
-393 => x"f8050c8c",
-394 => x"08f80508",
-395 => x"520b0b81",
-396 => x"85b45187",
-397 => x"c53f0b0b",
-398 => x"8185c051",
-399 => x"8a8b3f0b",
-400 => x"0b8185d0",
-401 => x"518a823f",
-402 => x"fc0b819a",
-403 => x"b00c819a",
-404 => x"b008812c",
-405 => x"530b0b72",
-406 => x"fe2e8438",
-407 => x"87903f8a",
-408 => x"0b819ab4",
-409 => x"0c819ab4",
-410 => x"08819ab0",
-411 => x"0829530b",
-412 => x"0b72d82e",
-413 => x"843886f6",
-414 => x"3f8a0b81",
-415 => x"9ab00c84",
-416 => x"e2ad800b",
-417 => x"819ab40c",
-418 => x"819ab408",
-419 => x"819ab008",
-420 => x"29530b0b",
-421 => x"72afd7c2",
-422 => x"802e8438",
-423 => x"86d03f81",
-424 => x"0a0b819a",
-425 => x"b00cff0b",
-426 => x"819ab40c",
-427 => x"819ab408",
-428 => x"819ab008",
-429 => x"25843886",
-430 => x"b53f8c08",
-431 => x"fc050881",
-432 => x"058c08fc",
-433 => x"050cfebf",
-434 => x"398c08fc",
-435 => x"05088a2e",
-436 => x"8438869a",
-437 => x"3f72800c",
-438 => x"883d0d8c",
-439 => x"0c048c08",
-440 => x"028c0cf5",
-441 => x"3d0d8c08",
-442 => x"9405089f",
-443 => x"388c088c",
-444 => x"05088c08",
-445 => x"9005088c",
-446 => x"08880508",
-447 => x"5856540b",
-448 => x"0b73760c",
-449 => x"7484170c",
-450 => x"81cd3980",
-451 => x"0b8c08f0",
-452 => x"050c800b",
-453 => x"8c08f405",
-454 => x"0c8c088c",
-455 => x"05088c08",
-456 => x"90050856",
-457 => x"540b0b73",
-458 => x"8c08f005",
-459 => x"0c748c08",
-460 => x"f4050c8c",
-461 => x"08f8058c",
-462 => x"08f00556",
-463 => x"56887054",
-464 => x"0b0b7553",
-465 => x"0b0b7652",
-466 => x"540b0b85",
-467 => x"ef3fa00b",
-468 => x"8c089405",
-469 => x"08318c08",
-470 => x"ec050c8c",
-471 => x"08ec0508",
-472 => x"80249f38",
-473 => x"800b8c08",
-474 => x"f4050c8c",
-475 => x"08ec0508",
-476 => x"308c08fc",
-477 => x"0508712b",
-478 => x"8c08f005",
-479 => x"0c540b0b",
-480 => x"bb398c08",
-481 => x"fc05088c",
-482 => x"08ec0508",
-483 => x"2a8c08e8",
-484 => x"050c8c08",
-485 => x"fc05088c",
-486 => x"08940508",
-487 => x"2b8c08f4",
-488 => x"050c8c08",
-489 => x"f805088c",
-490 => x"08940508",
-491 => x"2b708c08",
-492 => x"e8050807",
-493 => x"8c08f005",
-494 => x"0c540b0b",
-495 => x"8c08f005",
-496 => x"088c08f4",
-497 => x"05088c08",
-498 => x"88050858",
-499 => x"56540b0b",
-500 => x"73760c74",
-501 => x"84170c8c",
-502 => x"08880508",
-503 => x"800c8d3d",
-504 => x"0d8c0c04",
-505 => x"8c08028c",
-506 => x"0cf93d0d",
-507 => x"800b8c08",
-508 => x"fc050c8c",
-509 => x"08880508",
-510 => x"8025ab38",
-511 => x"8c088805",
-512 => x"08308c08",
-513 => x"88050c80",
-514 => x"0b8c08f4",
-515 => x"050c8c08",
-516 => x"fc050888",
-517 => x"38810b8c",
-518 => x"08f4050c",
-519 => x"8c08f405",
-520 => x"088c08fc",
-521 => x"050c8c08",
-522 => x"8c050880",
-523 => x"25ab388c",
-524 => x"088c0508",
-525 => x"308c088c",
-526 => x"050c800b",
-527 => x"8c08f005",
-528 => x"0c8c08fc",
-529 => x"05088838",
-530 => x"810b8c08",
-531 => x"f0050c8c",
-532 => x"08f00508",
-533 => x"8c08fc05",
-534 => x"0c80530b",
-535 => x"0b8c088c",
-536 => x"0508528c",
-537 => x"08880508",
-538 => x"5181b13f",
-539 => x"8008708c",
-540 => x"08f8050c",
-541 => x"540b0b8c",
-542 => x"08fc0508",
-543 => x"802e8c38",
-544 => x"8c08f805",
-545 => x"08308c08",
-546 => x"f8050c8c",
-547 => x"08f80508",
-548 => x"70800c54",
-549 => x"0b0b893d",
-550 => x"0d8c0c04",
-551 => x"8c08028c",
-552 => x"0cfb3d0d",
-553 => x"800b8c08",
-554 => x"fc050c8c",
-555 => x"08880508",
-556 => x"80259338",
-557 => x"8c088805",
-558 => x"08308c08",
-559 => x"88050c81",
-560 => x"0b8c08fc",
-561 => x"050c8c08",
-562 => x"8c050880",
-563 => x"258c388c",
-564 => x"088c0508",
-565 => x"308c088c",
-566 => x"050c8153",
-567 => x"0b0b8c08",
-568 => x"8c050852",
-569 => x"8c088805",
-570 => x"0851b13f",
-571 => x"8008708c",
-572 => x"08f8050c",
-573 => x"540b0b8c",
-574 => x"08fc0508",
-575 => x"802e8c38",
-576 => x"8c08f805",
-577 => x"08308c08",
-578 => x"f8050c8c",
-579 => x"08f80508",
-580 => x"70800c54",
-581 => x"0b0b873d",
-582 => x"0d8c0c04",
-583 => x"8c08028c",
-584 => x"0c707070",
-585 => x"70810b8c",
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-4246 => x"0c048c08",
-4247 => x"028c0c70",
-4248 => x"70707081",
-4249 => x"530b0b8c",
-4250 => x"088c0508",
-4251 => x"528c0888",
-4252 => x"050851ff",
-4253 => x"8da63f80",
-4254 => x"0870800c",
-4255 => x"540b0b50",
-4256 => x"5050508c",
-4257 => x"0c047070",
-4258 => x"819a800b",
-4259 => x"fc057008",
-4260 => x"52520b70",
-4261 => x"ff2e9338",
-4262 => x"702dfc72",
-4263 => x"05700852",
-4264 => x"520b70ff",
-4265 => x"2e098106",
-4266 => x"ef385050",
-4267 => x"0404ff85",
-4268 => x"e53f0400",
-4269 => x"4379636c",
-4270 => x"65732025",
-4271 => x"640a0000",
-4272 => x"48656c6c",
-4273 => x"6f20776f",
-4274 => x"726c6420",
-4275 => x"310a0000",
-4276 => x"48656c6c",
-4277 => x"6f20776f",
-4278 => x"726c6420",
-4279 => x"320a0000",
-4280 => x"0a000000",
-4281 => x"20202020",
-4282 => x"20202020",
-4283 => x"20202020",
-4284 => x"20202020",
-4285 => x"30303030",
-4286 => x"30303030",
-4287 => x"30303030",
-4288 => x"30303030",
-4289 => x"000017e3",
-4290 => x"0000138d",
-4291 => x"0000138d",
-4292 => x"000017d9",
-4293 => x"0000138d",
-4294 => x"0000138d",
-4295 => x"0000138d",
-4296 => x"0000138d",
-4297 => x"0000138d",
-4298 => x"0000138d",
-4299 => x"00001364",
-4300 => x"0000177e",
-4301 => x"0000138d",
-4302 => x"00001376",
-4303 => x"000016ec",
-4304 => x"0000138d",
-4305 => x"000017af",
-4306 => x"0000178a",
-4307 => x"0000178a",
-4308 => x"0000178a",
-4309 => x"0000178a",
-4310 => x"0000178a",
-4311 => x"0000178a",
-4312 => x"0000178a",
-4313 => x"0000178a",
-4314 => x"0000178a",
-4315 => x"0000138d",
-4316 => x"0000138d",
-4317 => x"0000138d",
-4318 => x"0000138d",
-4319 => x"0000138d",
-4320 => x"0000138d",
-4321 => x"0000138d",
-4322 => x"0000138d",
-4323 => x"0000138d",
-4324 => x"00001699",
-4325 => x"00001326",
-4326 => x"0000138d",
-4327 => x"0000138d",
-4328 => x"0000138d",
-4329 => x"0000138d",
-4330 => x"0000138d",
-4331 => x"0000138d",
-4332 => x"0000138d",
-4333 => x"0000138d",
-4334 => x"0000138d",
-4335 => x"0000138d",
-4336 => x"000012ec",
-4337 => x"0000138d",
-4338 => x"0000138d",
-4339 => x"0000138d",
-4340 => x"00001553",
-4341 => x"0000138d",
-4342 => x"00001015",
-4343 => x"0000138d",
-4344 => x"0000138d",
-4345 => x"00001733",
-4346 => x"0000138d",
-4347 => x"0000138d",
-4348 => x"0000138d",
-4349 => x"0000138d",
-4350 => x"0000138d",
-4351 => x"0000138d",
-4352 => x"0000138d",
-4353 => x"0000138d",
-4354 => x"0000138d",
-4355 => x"0000138d",
-4356 => x"00001699",
-4357 => x"0000132a",
-4358 => x"0000138d",
-4359 => x"0000138d",
-4360 => x"0000138d",
-4361 => x"0000168e",
-4362 => x"0000132a",
-4363 => x"0000138d",
-4364 => x"0000138d",
-4365 => x"000015d8",
-4366 => x"0000138d",
-4367 => x"000015a8",
-4368 => x"000012f0",
-4369 => x"000015f7",
-4370 => x"00001383",
-4371 => x"0000138d",
-4372 => x"00001553",
-4373 => x"0000138d",
-4374 => x"00001019",
-4375 => x"0000138d",
-4376 => x"0000138d",
-4377 => x"000017ba",
-4378 => x"62756720",
-4379 => x"696e2076",
-4380 => x"66707269",
-4381 => x"6e74663a",
-4382 => x"20626164",
-4383 => x"20626173",
-4384 => x"65000000",
-4385 => x"30313233",
-4386 => x"34353637",
-4387 => x"38396162",
-4388 => x"63646566",
-4389 => x"00000000",
-4390 => x"30313233",
-4391 => x"34353637",
-4392 => x"38394142",
-4393 => x"43444546",
-4394 => x"00000000",
-4395 => x"286e756c",
-4396 => x"6c290000",
-4397 => x"432d5554",
-4398 => x"462d3800",
-4399 => x"432d534a",
-4400 => x"49530000",
-4401 => x"432d4555",
-4402 => x"434a5000",
-4403 => x"432d4a49",
-4404 => x"53000000",
-4405 => x"43000000",
-4406 => x"2e000000",
-4407 => x"49534f2d",
-4408 => x"38383539",
-4409 => x"2d310000",
-4410 => x"64756d6d",
-4411 => x"792e6578",
-4412 => x"65000000",
-4413 => x"00ffffff",
-4414 => x"ff00ffff",
-4415 => x"ffff00ff",
-4416 => x"ffffff00",
-4417 => x"00000000",
-4418 => x"00000000",
-4419 => x"00000000",
-4420 => x"00004d08",
-4421 => x"00004518",
-4422 => x"00000000",
-4423 => x"00004780",
-4424 => x"000047dc",
-4425 => x"00004838",
-4426 => x"00000000",
-4427 => x"00000000",
-4428 => x"00000000",
-4429 => x"00000000",
-4430 => x"00000000",
-4431 => x"00000000",
-4432 => x"00000000",
-4433 => x"00000000",
-4434 => x"00000000",
-4435 => x"000044d4",
-4436 => x"00000000",
-4437 => x"00000000",
-4438 => x"00000000",
-4439 => x"00000000",
-4440 => x"00000000",
-4441 => x"00000000",
-4442 => x"00000000",
-4443 => x"00000000",
-4444 => x"00000000",
-4445 => x"00000000",
-4446 => x"00000000",
-4447 => x"00000000",
-4448 => x"00000000",
-4449 => x"00000000",
-4450 => x"00000000",
-4451 => x"00000000",
-4452 => x"00000000",
-4453 => x"00000000",
-4454 => x"00000000",
-4455 => x"00000000",
-4456 => x"00000000",
-4457 => x"00000000",
-4458 => x"00000000",
-4459 => x"00000000",
-4460 => x"00000000",
-4461 => x"00000000",
-4462 => x"00000000",
-4463 => x"00000000",
-4464 => x"00000001",
-4465 => x"330eabcd",
-4466 => x"1234e66d",
-4467 => x"deec0005",
-4468 => x"000b0000",
-4469 => x"00000000",
-4470 => x"00000000",
-4471 => x"00000000",
-4472 => x"00000000",
-4473 => x"00000000",
-4474 => x"00000000",
-4475 => x"00000000",
-4476 => x"00000000",
-4477 => x"00000000",
-4478 => x"00000000",
-4479 => x"00000000",
-4480 => x"00000000",
-4481 => x"00000000",
-4482 => x"00000000",
-4483 => x"00000000",
-4484 => x"00000000",
-4485 => x"00000000",
-4486 => x"00000000",
-4487 => x"00000000",
-4488 => x"00000000",
-4489 => x"00000000",
-4490 => x"00000000",
-4491 => x"00000000",
-4492 => x"00000000",
-4493 => x"00000000",
-4494 => x"00000000",
-4495 => x"00000000",
-4496 => x"00000000",
-4497 => x"00000000",
-4498 => x"00000000",
-4499 => x"00000000",
-4500 => x"00000000",
-4501 => x"00000000",
-4502 => x"00000000",
-4503 => x"00000000",
-4504 => x"00000000",
-4505 => x"00000000",
-4506 => x"00000000",
-4507 => x"00000000",
-4508 => x"00000000",
-4509 => x"00000000",
-4510 => x"00000000",
-4511 => x"00000000",
-4512 => x"00000000",
-4513 => x"00000000",
-4514 => x"00000000",
-4515 => x"00000000",
-4516 => x"00000000",
-4517 => x"00000000",
-4518 => x"00000000",
-4519 => x"00000000",
-4520 => x"00000000",
-4521 => x"00000000",
-4522 => x"00000000",
-4523 => x"00000000",
-4524 => x"00000000",
-4525 => x"00000000",
-4526 => x"00000000",
-4527 => x"00000000",
-4528 => x"00000000",
-4529 => x"00000000",
-4530 => x"00000000",
-4531 => x"00000000",
-4532 => x"00000000",
-4533 => x"00000000",
-4534 => x"00000000",
-4535 => x"00000000",
-4536 => x"00000000",
-4537 => x"00000000",
-4538 => x"00000000",
-4539 => x"00000000",
-4540 => x"00000000",
-4541 => x"00000000",
-4542 => x"00000000",
-4543 => x"00000000",
-4544 => x"00000000",
-4545 => x"00000000",
-4546 => x"00000000",
-4547 => x"00000000",
-4548 => x"00000000",
-4549 => x"00000000",
-4550 => x"00000000",
-4551 => x"00000000",
-4552 => x"00000000",
-4553 => x"00000000",
-4554 => x"00000000",
-4555 => x"00000000",
-4556 => x"00000000",
-4557 => x"00000000",
-4558 => x"00000000",
-4559 => x"00000000",
-4560 => x"00000000",
-4561 => x"00000000",
-4562 => x"00000000",
-4563 => x"00000000",
-4564 => x"00000000",
-4565 => x"00000000",
-4566 => x"00000000",
-4567 => x"00000000",
-4568 => x"00000000",
-4569 => x"00000000",
-4570 => x"00000000",
-4571 => x"00000000",
-4572 => x"00000000",
-4573 => x"00000000",
-4574 => x"00000000",
-4575 => x"00000000",
-4576 => x"00000000",
-4577 => x"00000000",
-4578 => x"00000000",
-4579 => x"00000000",
-4580 => x"00000000",
-4581 => x"00000000",
-4582 => x"00000000",
-4583 => x"00000000",
-4584 => x"00000000",
-4585 => x"00000000",
-4586 => x"00000000",
-4587 => x"00000000",
-4588 => x"00000000",
-4589 => x"00000000",
-4590 => x"00000000",
-4591 => x"00000000",
-4592 => x"00000000",
-4593 => x"00000000",
-4594 => x"00000000",
-4595 => x"00000000",
-4596 => x"00000000",
-4597 => x"00000000",
-4598 => x"00000000",
-4599 => x"00000000",
-4600 => x"00000000",
-4601 => x"00000000",
-4602 => x"00000000",
-4603 => x"00000000",
-4604 => x"00000000",
-4605 => x"00000000",
-4606 => x"00000000",
-4607 => x"00000000",
-4608 => x"00000000",
-4609 => x"00000000",
-4610 => x"00000000",
-4611 => x"00000000",
-4612 => x"00000000",
-4613 => x"00000000",
-4614 => x"00000000",
-4615 => x"00000000",
-4616 => x"00000000",
-4617 => x"00000000",
-4618 => x"00000000",
-4619 => x"00000000",
-4620 => x"00000000",
-4621 => x"00000000",
-4622 => x"00000000",
-4623 => x"00000000",
-4624 => x"00000000",
-4625 => x"00000000",
-4626 => x"00000000",
-4627 => x"00000000",
-4628 => x"00000000",
-4629 => x"00000000",
-4630 => x"00000000",
-4631 => x"00000000",
-4632 => x"00000000",
-4633 => x"00000000",
-4634 => x"00000000",
-4635 => x"00000000",
-4636 => x"00000000",
-4637 => x"00000000",
-4638 => x"00000000",
-4639 => x"00000000",
-4640 => x"00000000",
-4641 => x"00000000",
-4642 => x"00000000",
-4643 => x"00000000",
-4644 => x"00000000",
-4645 => x"43000000",
-4646 => x"00000000",
-4647 => x"00000000",
-4648 => x"00000000",
-4649 => x"00000000",
-4650 => x"00000000",
-4651 => x"00000001",
-4652 => x"000044dc",
-4653 => x"00000000",
-4654 => x"00000000",
-4655 => x"00000000",
-4656 => x"00000000",
-4657 => x"00000000",
-4658 => x"00000000",
-4659 => x"00000000",
-4660 => x"00000000",
-4661 => x"00000000",
-4662 => x"00000000",
-4663 => x"00000000",
-4664 => x"00000000",
-4665 => x"ffffffff",
-4666 => x"00000000",
-4667 => x"00020000",
-4668 => x"00000000",
-4669 => x"00000000",
-4670 => x"000048f0",
-4671 => x"000048f0",
-4672 => x"000048f8",
-4673 => x"000048f8",
-4674 => x"00004900",
-4675 => x"00004900",
-4676 => x"00004908",
-4677 => x"00004908",
-4678 => x"00004910",
-4679 => x"00004910",
-4680 => x"00004918",
-4681 => x"00004918",
-4682 => x"00004920",
-4683 => x"00004920",
-4684 => x"00004928",
-4685 => x"00004928",
-4686 => x"00004930",
-4687 => x"00004930",
-4688 => x"00004938",
-4689 => x"00004938",
-4690 => x"00004940",
-4691 => x"00004940",
-4692 => x"00004948",
-4693 => x"00004948",
-4694 => x"00004950",
-4695 => x"00004950",
-4696 => x"00004958",
-4697 => x"00004958",
-4698 => x"00004960",
-4699 => x"00004960",
-4700 => x"00004968",
-4701 => x"00004968",
-4702 => x"00004970",
-4703 => x"00004970",
-4704 => x"00004978",
-4705 => x"00004978",
-4706 => x"00004980",
-4707 => x"00004980",
-4708 => x"00004988",
-4709 => x"00004988",
-4710 => x"00004990",
-4711 => x"00004990",
-4712 => x"00004998",
-4713 => x"00004998",
-4714 => x"000049a0",
-4715 => x"000049a0",
-4716 => x"000049a8",
-4717 => x"000049a8",
-4718 => x"000049b0",
-4719 => x"000049b0",
-4720 => x"000049b8",
-4721 => x"000049b8",
-4722 => x"000049c0",
-4723 => x"000049c0",
-4724 => x"000049c8",
-4725 => x"000049c8",
-4726 => x"000049d0",
-4727 => x"000049d0",
-4728 => x"000049d8",
-4729 => x"000049d8",
-4730 => x"000049e0",
-4731 => x"000049e0",
-4732 => x"000049e8",
-4733 => x"000049e8",
-4734 => x"000049f0",
-4735 => x"000049f0",
-4736 => x"000049f8",
-4737 => x"000049f8",
-4738 => x"00004a00",
-4739 => x"00004a00",
-4740 => x"00004a08",
-4741 => x"00004a08",
-4742 => x"00004a10",
-4743 => x"00004a10",
-4744 => x"00004a18",
-4745 => x"00004a18",
-4746 => x"00004a20",
-4747 => x"00004a20",
-4748 => x"00004a28",
-4749 => x"00004a28",
-4750 => x"00004a30",
-4751 => x"00004a30",
-4752 => x"00004a38",
-4753 => x"00004a38",
-4754 => x"00004a40",
-4755 => x"00004a40",
-4756 => x"00004a48",
-4757 => x"00004a48",
-4758 => x"00004a50",
-4759 => x"00004a50",
-4760 => x"00004a58",
-4761 => x"00004a58",
-4762 => x"00004a60",
-4763 => x"00004a60",
-4764 => x"00004a68",
-4765 => x"00004a68",
-4766 => x"00004a70",
-4767 => x"00004a70",
-4768 => x"00004a78",
-4769 => x"00004a78",
-4770 => x"00004a80",
-4771 => x"00004a80",
-4772 => x"00004a88",
-4773 => x"00004a88",
-4774 => x"00004a90",
-4775 => x"00004a90",
-4776 => x"00004a98",
-4777 => x"00004a98",
-4778 => x"00004aa0",
-4779 => x"00004aa0",
-4780 => x"00004aa8",
-4781 => x"00004aa8",
-4782 => x"00004ab0",
-4783 => x"00004ab0",
-4784 => x"00004ab8",
-4785 => x"00004ab8",
-4786 => x"00004ac0",
-4787 => x"00004ac0",
-4788 => x"00004ac8",
-4789 => x"00004ac8",
-4790 => x"00004ad0",
-4791 => x"00004ad0",
-4792 => x"00004ad8",
-4793 => x"00004ad8",
-4794 => x"00004ae0",
-4795 => x"00004ae0",
-4796 => x"00004ae8",
-4797 => x"00004ae8",
-4798 => x"00004af0",
-4799 => x"00004af0",
-4800 => x"00004af8",
-4801 => x"00004af8",
-4802 => x"00004b00",
-4803 => x"00004b00",
-4804 => x"00004b08",
-4805 => x"00004b08",
-4806 => x"00004b10",
-4807 => x"00004b10",
-4808 => x"00004b18",
-4809 => x"00004b18",
-4810 => x"00004b20",
-4811 => x"00004b20",
-4812 => x"00004b28",
-4813 => x"00004b28",
-4814 => x"00004b30",
-4815 => x"00004b30",
-4816 => x"00004b38",
-4817 => x"00004b38",
-4818 => x"00004b40",
-4819 => x"00004b40",
-4820 => x"00004b48",
-4821 => x"00004b48",
-4822 => x"00004b50",
-4823 => x"00004b50",
-4824 => x"00004b58",
-4825 => x"00004b58",
-4826 => x"00004b60",
-4827 => x"00004b60",
-4828 => x"00004b68",
-4829 => x"00004b68",
-4830 => x"00004b70",
-4831 => x"00004b70",
-4832 => x"00004b78",
-4833 => x"00004b78",
-4834 => x"00004b80",
-4835 => x"00004b80",
-4836 => x"00004b88",
-4837 => x"00004b88",
-4838 => x"00004b90",
-4839 => x"00004b90",
-4840 => x"00004b98",
-4841 => x"00004b98",
-4842 => x"00004ba0",
-4843 => x"00004ba0",
-4844 => x"00004ba8",
-4845 => x"00004ba8",
-4846 => x"00004bb0",
-4847 => x"00004bb0",
-4848 => x"00004bb8",
-4849 => x"00004bb8",
-4850 => x"00004bc0",
-4851 => x"00004bc0",
-4852 => x"00004bc8",
-4853 => x"00004bc8",
-4854 => x"00004bd0",
-4855 => x"00004bd0",
-4856 => x"00004bd8",
-4857 => x"00004bd8",
-4858 => x"00004be0",
-4859 => x"00004be0",
-4860 => x"00004be8",
-4861 => x"00004be8",
-4862 => x"00004bf0",
-4863 => x"00004bf0",
-4864 => x"00004bf8",
-4865 => x"00004bf8",
-4866 => x"00004c00",
-4867 => x"00004c00",
-4868 => x"00004c08",
-4869 => x"00004c08",
-4870 => x"00004c10",
-4871 => x"00004c10",
-4872 => x"00004c18",
-4873 => x"00004c18",
-4874 => x"00004c20",
-4875 => x"00004c20",
-4876 => x"00004c28",
-4877 => x"00004c28",
-4878 => x"00004c30",
-4879 => x"00004c30",
-4880 => x"00004c38",
-4881 => x"00004c38",
-4882 => x"00004c40",
-4883 => x"00004c40",
-4884 => x"00004c48",
-4885 => x"00004c48",
-4886 => x"00004c50",
-4887 => x"00004c50",
-4888 => x"00004c58",
-4889 => x"00004c58",
-4890 => x"00004c60",
-4891 => x"00004c60",
-4892 => x"00004c68",
-4893 => x"00004c68",
-4894 => x"00004c70",
-4895 => x"00004c70",
-4896 => x"00004c78",
-4897 => x"00004c78",
-4898 => x"00004c80",
-4899 => x"00004c80",
-4900 => x"00004c88",
-4901 => x"00004c88",
-4902 => x"00004c90",
-4903 => x"00004c90",
-4904 => x"00004c98",
-4905 => x"00004c98",
-4906 => x"00004ca0",
-4907 => x"00004ca0",
-4908 => x"00004ca8",
-4909 => x"00004ca8",
-4910 => x"00004cb0",
-4911 => x"00004cb0",
-4912 => x"00004cb8",
-4913 => x"00004cb8",
-4914 => x"00004cc0",
-4915 => x"00004cc0",
-4916 => x"00004cc8",
-4917 => x"00004cc8",
-4918 => x"00004cd0",
-4919 => x"00004cd0",
-4920 => x"00004cd8",
-4921 => x"00004cd8",
-4922 => x"00004ce0",
-4923 => x"00004ce0",
-4924 => x"00004ce8",
-4925 => x"00004ce8",
-4926 => x"000044e8",
-4927 => x"ffffffff",
-4928 => x"00000000",
-4929 => x"ffffffff",
-4930 => x"00000000",
- others => x"00000000"
-);
-
-begin
-
-process (clk)
-begin
- if (clk'event and clk = '1') then
- if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then
- report "write collision" severity failure;
- end if;
-
- if (memAWriteEnable = '1') then
- ram(conv_integer(memAAddr)) := memAWrite;
- memARead <= memAWrite;
- else
- memARead <= ram(conv_integer(memAAddr));
- end if;
- end if;
-end process;
-
-process (clk)
-begin
- if (clk'event and clk = '1') then
- if (memBWriteEnable = '1') then
- ram(conv_integer(memBAddr)) := memBWrite;
- memBRead <= memBWrite;
- else
- memBRead <= ram(conv_integer(memBAddr));
- end if;
- end if;
-end process;
-
-
-
-
-end dualport_ram_arch;
diff --git a/zpu/hdl/zpu3/src/dualport_ram_synplicity.vhd b/zpu/hdl/zpu3/src/dualport_ram_synplicity.vhd deleted file mode 100644 index 83a7de2..0000000 --- a/zpu/hdl/zpu3/src/dualport_ram_synplicity.vhd +++ /dev/null @@ -1,5012 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - - -library zylin; -use zylin.zpu_config.all; -use zylin.zpupkg.all; - -entity dualport_ram is -port (clk : in std_logic; - memAWriteEnable : in std_logic; - memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit); - memAWrite : in std_logic_vector(wordSize-1 downto 0); - memARead : out std_logic_vector(wordSize-1 downto 0); - memBWriteEnable : in std_logic; - memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit); - memBWrite : in std_logic_vector(wordSize-1 downto 0); - memBRead : out std_logic_vector(wordSize-1 downto 0)); -end dualport_ram; - -architecture dualport_ram_arch of dualport_ram is - - -type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); - - ---shared variable ram : ram_type := -signal ram : ram_type := -( -0 => x"800b0b0b", -1 => x"0b0b8070", -2 => x"0b0b818a", -3 => x"dc0c3a0b", -4 => x"0b80dab4", -5 => x"04000000", -6 => x"00000000", -7 => x"00000000", -8 => x"80088408", -9 => x"88080b0b", -10 => x"80db972d", -11 => x"880c840c", -12 => x"800c0400", -13 => x"00000000", -14 => x"00000000", -15 => x"00000000", -16 => x"71fd0608", -17 => x"72830609", -18 => x"81058205", -19 => x"832b0b2a", -20 => x"83ffff06", -21 => x"52810504", -22 => x"00000000", -23 => x"00000000", -24 => x"71fd0608", -25 => x"83ffff73", -26 => x"83060981", -27 => x"05820583", -28 => x"2b0b2b09", -29 => x"067383ff", -30 => x"ff0b0b0b", -31 => x"0b83a704", -32 => x"72098105", -33 => x"72057373", -34 => x"09060906", -35 => x"73097306", -36 => x"070a8106", -37 => x"53518105", -38 => x"04000000", -39 => x"00000000", -40 => x"72722473", -41 => x"732e0753", -42 => x"51810504", -43 => x"00000000", -44 => x"00000000", -45 => x"00000000", -46 => x"00000000", -47 => x"00000000", -48 => x"71737109", -49 => x"71068106", -50 => x"30720a10", -51 => x"0a720a10", -52 => x"0a31050a", -53 => x"81065151", -54 => x"53518105", -55 => x"04000000", -56 => x"72722673", -57 => x"732e0753", -58 => x"51810504", -59 => x"00000000", -60 => x"00000000", -61 => x"00000000", -62 => x"00000000", -63 => x"00000000", -64 => x"72ff0571", -65 => x"81050673", -66 => x"ff050972", -67 => x"74058005", -68 => x"06075350", -69 => x"50040000", -70 => x"00000000", -71 => x"00000000", -72 => x"0b0b0b8c", -73 => x"f8040000", -74 => x"00000000", -75 => x"00000000", -76 => x"00000000", -77 => x"00000000", -78 => x"00000000", -79 => x"00000000", -80 => x"720a722b", -81 => x"0a535181", -82 => x"05040000", -83 => x"00000000", -84 => x"00000000", -85 => x"00000000", -86 => x"00000000", -87 => x"00000000", -88 => x"72729f06", -89 => x"0981050b", -90 => x"0b0b88a7", -91 => x"05040000", -92 => x"00000000", -93 => x"00000000", -94 => x"00000000", -95 => x"00000000", -96 => x"72722aff", -97 => x"739f062a", -98 => x"0974090a", -99 => x"8106ff05", -100 => x"06075351", -101 => x"81050400", -102 => x"00000000", -103 => x"00000000", -104 => x"71718105", -105 => x"53510406", -106 => x"73830609", -107 => x"81058205", -108 => x"832b0b2b", -109 => x"0772fc06", -110 => x"0c515181", -111 => x"05040000", -112 => x"72098105", -113 => x"72050970", -114 => x"81050906", -115 => x"0a810653", -116 => x"51810504", -117 => x"00000000", -118 => x"00000000", -119 => x"00000000", -120 => x"72098105", -121 => x"72050970", -122 => x"81050906", -123 => x"0a098106", -124 => x"53518105", -125 => x"04000000", -126 => x"00000000", -127 => x"00000000", -128 => x"71098105", -129 => x"52810504", -130 => x"00000000", -131 => x"00000000", -132 => x"00000000", -133 => x"00000000", -134 => x"00000000", -135 => x"00000000", -136 => x"72720981", -137 => x"05055351", -138 => x"81050409", -139 => x"81058305", -140 => x"1010102b", -141 => x"0772fc06", -142 => x"0c515181", -143 => x"05040000", -144 => x"72097206", -145 => x"73730906", -146 => x"07535181", -147 => x"05040000", -148 => x"00000000", -149 => x"00000000", -150 => x"00000000", -151 => x"00000000", -152 => x"71fc0608", -153 => x"72830609", -154 => x"81058305", -155 => x"1010102a", -156 => x"81ff0652", -157 => x"81050400", -158 => x"00000000", -159 => x"00000000", -160 => x"71fc0608", -161 => x"0b0b818a", -162 => x"88738306", -163 => x"10100508", -164 => x"067381ff", -165 => x"06738306", -166 => x"0b0b0b84", -167 => x"ab040000", -168 => x"80088408", -169 => x"88087575", -170 => x"0b0b0bb3", -171 => x"912d5050", -172 => x"80085688", -173 => x"0c840c80", -174 => x"0c810551", -175 => x"04000000", -176 => x"80088408", -177 => x"88087575", -178 => x"0b0b0bb4", -179 => x"8a2d5050", -180 => x"80085688", -181 => x"0c840c80", -182 => x"0c810551", -183 => x"04000000", -184 => x"72097081", -185 => x"0509060a", -186 => x"8106ff05", -187 => x"70547181", -188 => x"05067309", -189 => x"72740580", -190 => x"05060753", -191 => x"50500400", -192 => x"72097081", -193 => x"0509060a", -194 => x"098106ff", -195 => x"05705471", -196 => x"81050673", -197 => x"09727405", -198 => x"80050607", -199 => x"53505004", -200 => x"05800504", -201 => x"00000000", -202 => x"00000000", -203 => x"00000000", -204 => x"00000000", -205 => x"00000000", -206 => x"00000000", -207 => x"00000000", -208 => x"810b0b0b", -209 => x"818ad80c", -210 => x"51810504", -211 => x"00000000", -212 => x"00000000", -213 => x"00000000", -214 => x"00000000", -215 => x"00000000", -216 => x"72830610", -217 => x"10728306", -218 => x"0710100b", -219 => x"0b818a98", -220 => x"05080400", -221 => x"00000000", -222 => x"00000000", -223 => x"00000000", -224 => x"00000000", -225 => x"00000000", -226 => x"00000000", -227 => x"00000000", -228 => x"00000000", -229 => x"00000000", -230 => x"00000000", -231 => x"00000000", -232 => x"02840572", -233 => x"10100552", -234 => x"81050400", -235 => x"00000000", -236 => x"00000000", -237 => x"00000000", -238 => x"00000000", -239 => x"00000000", -240 => x"00000000", -241 => x"00000000", -242 => x"00000000", -243 => x"00000000", -244 => x"00000000", -245 => x"00000000", -246 => x"00000000", -247 => x"00000000", -248 => x"71710571", -249 => x"81055351", -250 => x"04000000", -251 => x"00000000", -252 => x"00000000", -253 => x"00000000", -254 => x"00000000", -255 => x"00000000", -256 => x"8db33f80", -257 => x"f39e3f04", -258 => x"10101010", -259 => x"10101010", -260 => x"10101010", -261 => x"10101010", -262 => x"10101010", -263 => x"10101010", -264 => x"10101010", -265 => x"10101053", -266 => x"51810504", -267 => x"72fc0608", -268 => x"81ff0a06", -269 => x"72fc0670", -270 => x"5408fe80", -271 => x"0a060772", -272 => x"0c515181", -273 => x"050472fc", -274 => x"06080a10", -275 => x"10101010", -276 => x"1010100a", -277 => x"87fc8080", -278 => x"0672fc06", -279 => x"08f883ff", -280 => x"ff060772", -281 => x"fc060c51", -282 => x"51810504", -283 => x"72fc0608", -284 => x"0a101010", -285 => x"10101010", -286 => x"10101010", -287 => x"10101010", -288 => x"100a83fe", -289 => x"800672fc", -290 => x"0608fc81", -291 => x"ff060772", -292 => x"fc060c51", -293 => x"51810504", -294 => x"72fc0608", -295 => x"0a101010", -296 => x"10101010", -297 => x"10101010", -298 => x"10101010", -299 => x"10101010", -300 => x"10101010", -301 => x"100a81ff", -302 => x"0672fc06", -303 => x"08fe8006", -304 => x"0772fc06", -305 => x"0c515181", -306 => x"050472fc", -307 => x"06081010", -308 => x"10101010", -309 => x"101081ff", -310 => x"0a0672fc", -311 => x"0608fe80", -312 => x"0a060772", -313 => x"fc060c51", -314 => x"51810504", -315 => x"72fc0608", -316 => x"87fc8080", -317 => x"0672fc06", -318 => x"705408f8", -319 => x"83ffff06", -320 => x"07720c51", -321 => x"51810504", -322 => x"72fc0608", -323 => x"0a101010", -324 => x"10101010", -325 => x"100a83fe", -326 => x"800672fc", -327 => x"0608fc81", -328 => x"ff060772", -329 => x"fc060c51", -330 => x"51810504", -331 => x"72fc0608", -332 => x"0a101010", -333 => x"10101010", -334 => x"10101010", -335 => x"10101010", -336 => x"100a81ff", -337 => x"0672fc06", -338 => x"08fe8006", -339 => x"0772fc06", -340 => x"0c515181", -341 => x"050472fc", -342 => x"06081010", -343 => x"10101010", -344 => x"10101010", -345 => x"10101010", -346 => x"101081ff", -347 => x"0a0672fc", -348 => x"0608fe80", -349 => x"0a060772", -350 => x"fc060c51", -351 => x"51810504", -352 => x"72fc0608", -353 => x"10101010", -354 => x"10101010", -355 => x"87fc8080", -356 => x"0672fc06", -357 => x"08f883ff", -358 => x"ff060772", -359 => x"fc060c51", -360 => x"51810504", -361 => x"72fc0608", -362 => x"83fe8006", -363 => x"72fc0670", -364 => x"5408fc81", -365 => x"ff060772", -366 => x"0c515181", -367 => x"050472fc", -368 => x"06080a10", -369 => x"10101010", -370 => x"1010100a", -371 => x"81ff0672", -372 => x"fc0608fe", -373 => x"80060772", -374 => x"fc060c51", -375 => x"51810504", -376 => x"72fc0608", -377 => x"10101010", -378 => x"10101010", -379 => x"10101010", -380 => x"10101010", -381 => x"10101010", -382 => x"10101010", -383 => x"81ff0a06", -384 => x"72fc0608", -385 => x"fe800a06", -386 => x"0772fc06", -387 => x"0c515181", -388 => x"050472fc", -389 => x"06081010", -390 => x"10101010", -391 => x"10101010", -392 => x"10101010", -393 => x"101087fc", -394 => x"80800672", -395 => x"fc0608f8", -396 => x"83ffff06", -397 => x"0772fc06", -398 => x"0c515181", -399 => x"050472fc", -400 => x"06081010", -401 => x"10101010", -402 => x"101083fe", -403 => x"800672fc", -404 => x"0608fc81", -405 => x"ff060772", -406 => x"fc060c51", -407 => x"51810504", -408 => x"72fc0608", -409 => x"81ff0672", -410 => x"fc067054", -411 => x"08fe8006", -412 => x"07720c51", -413 => x"51810504", -414 => x"72728072", -415 => x"8106ff05", -416 => x"09720605", -417 => x"71105272", -418 => x"0a100a53", -419 => x"728106ff", -420 => x"05097206", -421 => x"05711052", -422 => x"720a100a", -423 => x"53728106", -424 => x"ff050972", -425 => x"06057110", -426 => x"52720a10", -427 => x"0a537281", -428 => x"06ff0509", -429 => x"72060571", -430 => x"1052720a", -431 => x"100a5372", -432 => x"8106ff05", -433 => x"09720605", -434 => x"71105272", -435 => x"0a100a53", -436 => x"728106ff", -437 => x"05097206", -438 => x"05711052", -439 => x"720a100a", -440 => x"53728106", -441 => x"ff050972", -442 => x"06057110", -443 => x"52720a10", -444 => x"0a537281", -445 => x"06ff0509", -446 => x"72060571", -447 => x"1052720a", -448 => x"100a5372", -449 => x"83a13772", -450 => x"8106ff05", -451 => x"09720605", -452 => x"71105272", -453 => x"0a100a53", -454 => x"728106ff", -455 => x"05097206", -456 => x"05711052", -457 => x"720a100a", -458 => x"53728106", -459 => x"ff050972", -460 => x"06057110", -461 => x"52720a10", -462 => x"0a537281", -463 => x"06ff0509", -464 => x"72060571", -465 => x"1052720a", -466 => x"100a5372", -467 => x"8106ff05", -468 => x"09720605", -469 => x"71105272", -470 => x"0a100a53", -471 => x"728106ff", -472 => x"05097206", -473 => x"05711052", -474 => x"720a100a", -475 => x"53728106", -476 => x"ff050972", -477 => x"06057110", -478 => x"52720a10", -479 => x"0a537281", -480 => x"06ff0509", -481 => x"72060571", -482 => x"1052720a", -483 => x"100a5372", -484 => x"82953772", -485 => x"8106ff05", -486 => x"09720605", -487 => x"71105272", -488 => x"0a100a53", -489 => x"728106ff", -490 => x"05097206", -491 => x"05711052", -492 => x"720a100a", -493 => x"53728106", -494 => x"ff050972", -495 => x"06057110", -496 => x"52720a10", -497 => x"0a537281", -498 => x"06ff0509", -499 => x"72060571", -500 => x"1052720a", -501 => x"100a5372", -502 => x"8106ff05", -503 => x"09720605", -504 => x"71105272", -505 => x"0a100a53", -506 => x"728106ff", -507 => x"05097206", -508 => x"05711052", -509 => x"720a100a", -510 => x"53728106", -511 => x"ff050972", -512 => x"06057110", -513 => x"52720a10", -514 => x"0a537281", -515 => x"06ff0509", -516 => x"72060571", -517 => x"1052720a", -518 => x"100a5372", -519 => x"81893772", -520 => x"8106ff05", -521 => x"09720605", -522 => x"71105272", -523 => x"0a100a53", -524 => x"728106ff", -525 => x"05097206", -526 => x"05711052", -527 => x"720a100a", -528 => x"53728106", -529 => x"ff050972", -530 => x"06057110", -531 => x"52720a10", -532 => x"0a537281", -533 => x"06ff0509", -534 => x"72060571", -535 => x"1052720a", -536 => x"100a5372", -537 => x"8106ff05", -538 => x"09720605", -539 => x"71105272", -540 => x"0a100a53", -541 => x"728106ff", -542 => x"05097206", -543 => x"05711052", -544 => x"720a100a", -545 => x"53728106", -546 => x"ff050972", -547 => x"06057110", -548 => x"52720a10", -549 => x"0a537281", -550 => x"06ff0509", -551 => x"72060571", -552 => x"1052720a", -553 => x"100a5351", -554 => x"51535181", -555 => x"05043c04", -556 => x"70700b0b", -557 => x"819acc08", -558 => x"52841208", -559 => x"70810651", -560 => x"51700970", -561 => x"81050906", -562 => x"0a098106", -563 => x"ff0509e9", -564 => x"0bf70506", -565 => x"84010505", -566 => x"04710881", -567 => x"ff06800c", -568 => x"50500470", -569 => x"700b0b81", -570 => x"9acc0852", -571 => x"84120870", -572 => x"0a100a70", -573 => x"81065151", -574 => x"51700970", -575 => x"81050906", -576 => x"0a098106", -577 => x"ff0509e4", -578 => x"0bf70506", -579 => x"84010505", -580 => x"0473720c", -581 => x"50500481", -582 => x"8ad80809", -583 => x"70810509", -584 => x"060a8106", -585 => x"ff0509b0", -586 => x"0bf70506", -587 => x"84010505", -588 => x"04838080", -589 => x"0b0b0b81", -590 => x"9acc0c82", -591 => x"a0800b0b", -592 => x"0b819ad0", -593 => x"0c829080", -594 => x"0b819ae0", -595 => x"0c0b0b81", -596 => x"9ad40b81", -597 => x"9ae40c04", -598 => x"f8808080", -599 => x"a40b0b0b", -600 => x"819acc0c", -601 => x"f8808082", -602 => x"800b0b0b", -603 => x"819ad00c", -604 => x"f8808084", -605 => x"800b819a", -606 => x"e00cf880", -607 => x"8080940b", -608 => x"819ae40c", -609 => x"f8808080", -610 => x"9c0b819a", -611 => x"dc0cf880", -612 => x"8080a00b", -613 => x"819ae80c", -614 => x"04f23d0d", -615 => x"600b0b81", -616 => x"9ad00856", -617 => x"5d82750c", -618 => x"8059805a", -619 => x"800b8f3d", -620 => x"71101017", -621 => x"70085957", -622 => x"5d5b8076", -623 => x"81ff067c", -624 => x"832b5658", -625 => x"5276537b", -626 => x"519ede3f", -627 => x"7d7f7a72", -628 => x"077c7207", -629 => x"71716081", -630 => x"05415f5d", -631 => x"5b595755", -632 => x"7a8724ff", -633 => x"050980ce", -634 => x"0bf70506", -635 => x"84010505", -636 => x"040b0b81", -637 => x"9ad0087b", -638 => x"10101170", -639 => x"08585155", -640 => x"807681ff", -641 => x"067c832b", -642 => x"56585276", -643 => x"537b519e", -644 => x"983f7d7f", -645 => x"7a72077c", -646 => x"72077171", -647 => x"60810541", -648 => x"5f5d5b59", -649 => x"5755877b", -650 => x"25ff0509", -651 => x"c40bf705", -652 => x"06840105", -653 => x"0504767d", -654 => x"0c77841e", -655 => x"0c7c800c", -656 => x"903d0d04", -657 => x"7070819a", -658 => x"d8335170", -659 => x"09708105", -660 => x"09060a09", -661 => x"8106ff05", -662 => x"0980d60b", -663 => x"f7050684", -664 => x"01050504", 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x"000047cc", -4599 => x"000047d4", -4600 => x"000047d4", -4601 => x"000047dc", -4602 => x"000047dc", -4603 => x"000047e4", -4604 => x"000047e4", -4605 => x"000047ec", -4606 => x"000047ec", -4607 => x"000047f4", -4608 => x"000047f4", -4609 => x"000047fc", -4610 => x"000047fc", -4611 => x"00004804", -4612 => x"00004804", -4613 => x"0000480c", -4614 => x"0000480c", -4615 => x"00004814", -4616 => x"00004814", -4617 => x"0000481c", -4618 => x"0000481c", -4619 => x"00004824", -4620 => x"00004824", -4621 => x"0000482c", -4622 => x"0000482c", -4623 => x"00004834", -4624 => x"00004834", -4625 => x"0000483c", -4626 => x"0000483c", -4627 => x"00004844", -4628 => x"00004844", -4629 => x"0000484c", -4630 => x"0000484c", -4631 => x"00004854", -4632 => x"00004854", -4633 => x"0000485c", -4634 => x"0000485c", -4635 => x"00004864", -4636 => x"00004864", -4637 => x"0000486c", -4638 => x"0000486c", -4639 => x"00004874", -4640 => x"00004874", -4641 => x"0000487c", -4642 => x"0000487c", -4643 => x"00004884", -4644 => x"00004884", -4645 => x"0000488c", -4646 => x"0000488c", -4647 => x"00004894", -4648 => x"00004894", -4649 => x"0000489c", -4650 => x"0000489c", -4651 => x"000048a4", -4652 => x"000048a4", -4653 => x"000048ac", -4654 => x"000048ac", -4655 => x"000048b4", -4656 => x"000048b4", -4657 => x"000048bc", -4658 => x"000048bc", -4659 => x"000048c4", -4660 => x"000048c4", -4661 => x"000048cc", -4662 => x"000048cc", -4663 => x"000048d4", -4664 => x"000048d4", -4665 => x"000048dc", -4666 => x"000048dc", -4667 => x"000048e4", -4668 => x"000048e4", -4669 => x"000048ec", -4670 => x"000048ec", -4671 => x"000048f4", -4672 => x"000048f4", -4673 => x"000048fc", -4674 => x"000048fc", -4675 => x"00004904", -4676 => x"00004904", -4677 => x"0000490c", -4678 => x"0000490c", -4679 => x"00004914", -4680 => x"00004914", -4681 => x"0000491c", -4682 => x"0000491c", -4683 => x"00004924", -4684 => x"00004924", -4685 => x"0000492c", -4686 => x"0000492c", -4687 => x"00004934", -4688 => x"00004934", -4689 => x"0000493c", -4690 => x"0000493c", -4691 => x"00004944", -4692 => x"00004944", -4693 => x"0000494c", -4694 => x"0000494c", -4695 => x"00004954", -4696 => x"00004954", -4697 => x"0000495c", -4698 => x"0000495c", -4699 => x"00004964", -4700 => x"00004964", -4701 => x"0000496c", -4702 => x"0000496c", -4703 => x"00004974", -4704 => x"00004974", -4705 => x"0000497c", -4706 => x"0000497c", -4707 => x"00004984", -4708 => x"00004984", -4709 => x"0000498c", -4710 => x"0000498c", -4711 => x"00004994", -4712 => x"00004994", -4713 => x"0000499c", -4714 => x"0000499c", -4715 => x"000049a4", -4716 => x"000049a4", -4717 => x"000049b8", -4718 => x"00000000", -4719 => x"00004c20", -4720 => x"00004c7c", -4721 => x"00004cd8", -4722 => x"00000000", -4723 => x"00000000", -4724 => x"00000000", -4725 => x"00000000", -4726 => x"00000000", -4727 => x"00000000", -4728 => x"00000000", -4729 => x"00000000", -4730 => x"00000000", -4731 => x"000043f8", -4732 => x"00000000", -4733 => x"00000000", -4734 => x"00000000", -4735 => x"00000000", -4736 => x"00000000", -4737 => x"00000000", -4738 => x"00000000", -4739 => x"00000000", -4740 => x"00000000", -4741 => x"00000000", -4742 => x"00000000", -4743 => x"00000000", -4744 => x"00000000", -4745 => x"00000000", -4746 => x"00000000", -4747 => x"00000000", -4748 => x"00000000", -4749 => x"00000000", -4750 => x"00000000", -4751 => x"00000000", -4752 => x"00000000", -4753 => x"00000000", -4754 => x"00000000", -4755 => x"00000000", -4756 => x"00000000", -4757 => x"00000000", -4758 => x"00000000", -4759 => x"00000000", -4760 => x"00000001", -4761 => x"330eabcd", -4762 => x"1234e66d", -4763 => x"deec0005", -4764 => x"000b0000", -4765 => x"00000000", -4766 => x"00000000", -4767 => x"00000000", -4768 => x"00000000", -4769 => x"00000000", -4770 => x"00000000", -4771 => x"00000000", -4772 => x"00000000", -4773 => x"00000000", -4774 => x"00000000", -4775 => x"00000000", -4776 => x"00000000", -4777 => x"00000000", -4778 => x"00000000", -4779 => x"00000000", -4780 => x"00000000", -4781 => x"00000000", -4782 => x"00000000", -4783 => x"00000000", -4784 => x"00000000", -4785 => x"00000000", -4786 => x"00000000", -4787 => x"00000000", -4788 => x"00000000", -4789 => x"00000000", -4790 => x"00000000", -4791 => x"00000000", -4792 => x"00000000", -4793 => x"00000000", -4794 => x"00000000", -4795 => x"00000000", -4796 => x"00000000", -4797 => x"00000000", -4798 => x"00000000", -4799 => x"00000000", -4800 => x"00000000", -4801 => x"00000000", -4802 => x"00000000", -4803 => x"00000000", -4804 => x"00000000", -4805 => x"00000000", -4806 => x"00000000", -4807 => x"00000000", -4808 => x"00000000", -4809 => x"00000000", -4810 => x"00000000", -4811 => x"00000000", -4812 => x"00000000", -4813 => x"00000000", -4814 => x"00000000", -4815 => x"00000000", -4816 => x"00000000", -4817 => x"00000000", -4818 => x"00000000", -4819 => x"00000000", -4820 => x"00000000", -4821 => x"00000000", -4822 => x"00000000", -4823 => x"00000000", -4824 => x"00000000", -4825 => x"00000000", -4826 => x"00000000", -4827 => x"00000000", -4828 => x"00000000", -4829 => x"00000000", -4830 => x"00000000", -4831 => x"00000000", -4832 => x"00000000", -4833 => x"00000000", -4834 => x"00000000", -4835 => x"00000000", -4836 => x"00000000", -4837 => x"00000000", -4838 => x"00000000", -4839 => x"00000000", -4840 => x"00000000", -4841 => x"00000000", -4842 => x"00000000", -4843 => x"00000000", -4844 => x"00000000", -4845 => x"00000000", -4846 => x"00000000", -4847 => x"00000000", -4848 => x"00000000", -4849 => x"00000000", -4850 => x"00000000", -4851 => x"00000000", -4852 => x"00000000", -4853 => x"00000000", -4854 => x"00000000", -4855 => x"00000000", -4856 => x"00000000", -4857 => x"00000000", -4858 => x"00000000", -4859 => x"00000000", -4860 => x"00000000", -4861 => x"00000000", -4862 => x"00000000", -4863 => x"00000000", -4864 => x"00000000", -4865 => x"00000000", -4866 => x"00000000", -4867 => x"00000000", -4868 => x"00000000", -4869 => x"00000000", -4870 => x"00000000", -4871 => x"00000000", -4872 => x"00000000", -4873 => x"00000000", -4874 => x"00000000", -4875 => x"00000000", -4876 => x"00000000", -4877 => x"00000000", -4878 => x"00000000", -4879 => x"00000000", -4880 => x"00000000", -4881 => x"00000000", -4882 => x"00000000", -4883 => x"00000000", -4884 => x"00000000", -4885 => x"00000000", -4886 => x"00000000", -4887 => x"00000000", -4888 => x"00000000", -4889 => x"00000000", -4890 => x"00000000", -4891 => x"00000000", -4892 => x"00000000", -4893 => x"00000000", -4894 => x"00000000", -4895 => x"00000000", -4896 => x"00000000", -4897 => x"00000000", -4898 => x"00000000", -4899 => x"00000000", -4900 => x"00000000", -4901 => x"00000000", -4902 => x"00000000", -4903 => x"00000000", -4904 => x"00000000", -4905 => x"00000000", -4906 => x"00000000", -4907 => x"00000000", -4908 => x"00000000", -4909 => x"00000000", -4910 => x"00000000", -4911 => x"00000000", -4912 => x"00000000", -4913 => x"00000000", -4914 => x"00000000", -4915 => x"00000000", -4916 => x"00000000", -4917 => x"00000000", -4918 => x"00000000", -4919 => x"00000000", -4920 => x"00000000", -4921 => x"00000000", -4922 => x"00000000", -4923 => x"00000000", -4924 => x"00000000", -4925 => x"00000000", -4926 => x"00000000", -4927 => x"00000000", -4928 => x"00000000", -4929 => x"00000000", -4930 => x"00000000", -4931 => x"00000000", -4932 => x"00000000", -4933 => x"00000000", -4934 => x"00000000", -4935 => x"00000000", -4936 => x"00000000", -4937 => x"00000000", -4938 => x"00000000", -4939 => x"00000000", -4940 => x"00000000", -4941 => x"000043fc", -4942 => x"ffffffff", -4943 => x"00000000", -4944 => x"ffffffff", -4945 => x"00000000", - others => x"00000000" -); - -attribute syn_ramstyle : string; -attribute syn_ramstyle of ram : signal is "no_rw_check" ; - -begin - -process (clk) -begin - if (clk'event and clk = '1') then - if (memAWriteEnable = '1') then - ram(conv_integer(memAAddr)) <= memAWrite; - memARead <= memAWrite; - else - memARead <= ram(conv_integer(memAAddr)); - end if; - end if; -end process; - -process (clk) -begin - if (clk'event and clk = '1') then - if (memBWriteEnable = '1') then - ram(conv_integer(memBAddr)) <= memBWrite; - memBRead <= memBWrite; - else - memBRead <= ram(conv_integer(memBAddr)); - end if; - end if; -end process; - - - - -end dualport_ram_arch; diff --git a/zpu/hdl/zpu3/src/helloworld_ram.vhd b/zpu/hdl/zpu3/src/helloworld_ram.vhd deleted file mode 100644 index 2e1d35d..0000000 --- a/zpu/hdl/zpu3/src/helloworld_ram.vhd +++ /dev/null @@ -1,3345 +0,0 @@ -library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-
-library zylin;
-use zylin.zpu_config.all;
-use zylin.zpupkg.all;
-
-entity dualport_ram is
-port (clk : in std_logic;
- memAWriteEnable : in std_logic;
- memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
- memAWrite : in std_logic_vector(wordSize-1 downto 0);
- memARead : out std_logic_vector(wordSize-1 downto 0);
- memBWriteEnable : in std_logic;
- memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
- memBWrite : in std_logic_vector(wordSize-1 downto 0);
- memBRead : out std_logic_vector(wordSize-1 downto 0));
-end dualport_ram;
-
-architecture dualport_ram_arch of dualport_ram is
-
-
-type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
-
-shared variable ram : ram_type :=
-(
-0 => x"800b0b0b",
-1 => x"0b0b8070",
-2 => x"0b0b80d6",
-3 => x"f00c3a0b",
-4 => x"0b80cd92",
-5 => x"04000000",
-6 => x"00000000",
-7 => x"00000000",
-8 => x"80088408",
-9 => x"88080b0b",
-10 => x"80cde02d",
-11 => x"880c840c",
-12 => x"800c0400",
-13 => x"00000000",
-14 => x"00000000",
-15 => x"00000000",
-16 => x"71fd0608",
-17 => x"72830609",
-18 => x"81058205",
-19 => x"832b0b2a",
-20 => x"83ffff06",
-21 => x"52040000",
-22 => x"00000000",
-23 => x"00000000",
-24 => x"71fd0608",
-25 => x"83ffff73",
-26 => x"83060981",
-27 => x"05820583",
-28 => x"2b0b2b09",
-29 => x"067383ff",
-30 => x"ff0b0b0b",
-31 => x"0b83a504",
-32 => x"72098105",
-33 => x"72057373",
-34 => x"09060906",
-35 => x"73097306",
-36 => x"070a8106",
-37 => x"53510400",
-38 => x"00000000",
-39 => x"00000000",
-40 => x"72722473",
-41 => x"732e0753",
-42 => x"51040000",
-43 => x"00000000",
-44 => x"00000000",
-45 => x"00000000",
-46 => x"00000000",
-47 => x"00000000",
-48 => x"71737109",
-49 => x"71068106",
-50 => x"30720a10",
-51 => x"0a720a10",
-52 => x"0a31050a",
-53 => x"81065151",
-54 => x"53510400",
-55 => x"00000000",
-56 => x"72722673",
-57 => x"732e0753",
-58 => x"51040000",
-59 => x"00000000",
-60 => x"00000000",
-61 => x"00000000",
-62 => x"00000000",
-63 => x"00000000",
-64 => x"00000000",
-65 => x"00000000",
-66 => x"00000000",
-67 => x"00000000",
-68 => x"00000000",
-69 => x"00000000",
-70 => x"00000000",
-71 => x"00000000",
-72 => x"72728072",
-73 => x"8106ff05",
-74 => x"09720605",
-75 => x"71105272",
-76 => x"0a100a53",
-77 => x"72ed3851",
-78 => x"51535104",
-79 => x"00000000",
-80 => x"720a722b",
-81 => x"0a535104",
-82 => x"00000000",
-83 => x"00000000",
-84 => x"00000000",
-85 => x"00000000",
-86 => x"00000000",
-87 => x"00000000",
-88 => x"72729f06",
-89 => x"0981050b",
-90 => x"0b0b88a7",
-91 => x"05040000",
-92 => x"00000000",
-93 => x"00000000",
-94 => x"00000000",
-95 => x"00000000",
-96 => x"72722aff",
-97 => x"739f062a",
-98 => x"0974090a",
-99 => x"8106ff05",
-100 => x"06075351",
-101 => x"04000000",
-102 => x"00000000",
-103 => x"00000000",
-104 => x"71715351",
-105 => x"04067383",
-106 => x"06098105",
-107 => x"8205832b",
-108 => x"0b2b0772",
-109 => x"fc060c51",
-110 => x"51040000",
-111 => x"00000000",
-112 => x"72098105",
-113 => x"72050970",
-114 => x"81050906",
-115 => x"0a810653",
-116 => x"51040000",
-117 => x"00000000",
-118 => x"00000000",
-119 => x"00000000",
-120 => x"72098105",
-121 => x"72050970",
-122 => x"81050906",
-123 => x"0a098106",
-124 => x"53510400",
-125 => x"00000000",
-126 => x"00000000",
-127 => x"00000000",
-128 => x"71098105",
-129 => x"52040000",
-130 => x"00000000",
-131 => x"00000000",
-132 => x"00000000",
-133 => x"00000000",
-134 => x"00000000",
-135 => x"00000000",
-136 => x"72720981",
-137 => x"05055351",
-138 => x"04098105",
-139 => x"83051010",
-140 => x"102b0772",
-141 => x"fc060c51",
-142 => x"51040000",
-143 => x"00000000",
-144 => x"72097206",
-145 => x"73730906",
-146 => x"07535104",
-147 => x"00000000",
-148 => x"00000000",
-149 => x"00000000",
-150 => x"00000000",
-151 => x"00000000",
-152 => x"71fc0608",
-153 => x"72830609",
-154 => x"81058305",
-155 => x"1010102a",
-156 => x"81ff0652",
-157 => x"04000000",
-158 => x"00000000",
-159 => x"00000000",
-160 => x"71fc0608",
-161 => x"0b0b80d6",
-162 => x"dc738306",
-163 => x"10100508",
-164 => x"067381ff",
-165 => x"06738306",
-166 => x"0b0b0b84",
-167 => x"a9040000",
-168 => x"80088408",
-169 => x"88087575",
-170 => x"0b0b0b8e",
-171 => x"fd2d5050",
-172 => x"80085688",
-173 => x"0c840c80",
-174 => x"0c510400",
-175 => x"00000000",
-176 => x"80088408",
-177 => x"88087575",
-178 => x"0b0b0b90",
-179 => x"af2d5050",
-180 => x"80085688",
-181 => x"0c840c80",
-182 => x"0c510400",
-183 => x"00000000",
-184 => x"72097081",
-185 => x"0509060a",
-186 => x"8106ff05",
-187 => x"70547106",
-188 => x"73097274",
-189 => x"05ff0506",
-190 => x"07535050",
-191 => x"04000000",
-192 => x"72097081",
-193 => x"0509060a",
-194 => x"098106ff",
-195 => x"05705471",
-196 => x"06730972",
-197 => x"7405ff05",
-198 => x"06075350",
-199 => x"50040000",
-200 => x"05ff0504",
-201 => x"00000000",
-202 => x"00000000",
-203 => x"00000000",
-204 => x"00000000",
-205 => x"00000000",
-206 => x"00000000",
-207 => x"00000000",
-208 => x"810b0b0b",
-209 => x"80d6ec0c",
-210 => x"51040000",
-211 => x"00000000",
-212 => x"00000000",
-213 => x"00000000",
-214 => x"00000000",
-215 => x"00000000",
-216 => x"71810552",
-217 => x"04000000",
-218 => x"00000000",
-219 => x"00000000",
-220 => x"00000000",
-221 => x"00000000",
-222 => x"00000000",
-223 => x"00000000",
-224 => x"00000000",
-225 => x"00000000",
-226 => x"00000000",
-227 => x"00000000",
-228 => x"00000000",
-229 => x"00000000",
-230 => x"00000000",
-231 => x"00000000",
-232 => x"02840572",
-233 => x"10100552",
-234 => x"04000000",
-235 => x"00000000",
-236 => x"00000000",
-237 => x"00000000",
-238 => x"00000000",
-239 => x"00000000",
-240 => x"00000000",
-241 => x"00000000",
-242 => x"00000000",
-243 => x"00000000",
-244 => x"00000000",
-245 => x"00000000",
-246 => x"00000000",
-247 => x"00000000",
-248 => x"717105ff",
-249 => x"05715351",
-250 => x"04000000",
-251 => x"00000000",
-252 => x"00000000",
-253 => x"00000000",
-254 => x"00000000",
-255 => x"00000000",
-256 => x"839f3f80",
-257 => x"cdf83f04",
-258 => x"10101010",
-259 => x"10101010",
-260 => x"10101010",
-261 => x"10101010",
-262 => x"10101010",
-263 => x"10101010",
-264 => x"10101010",
-265 => x"10101053",
-266 => x"51043c04",
-267 => x"70700b0b",
-268 => x"80e6d808",
-269 => x"52841208",
-270 => x"70810651",
-271 => x"5170f638",
-272 => x"710881ff",
-273 => x"06800c50",
-274 => x"50047070",
-275 => x"0b0b80e6",
-276 => x"d8085284",
-277 => x"1208700a",
-278 => x"100a7081",
-279 => x"06515151",
-280 => x"70f13873",
-281 => x"720c5050",
-282 => x"0480d6ec",
-283 => x"08802ea8",
-284 => x"38838080",
-285 => x"0b0b0b80",
-286 => x"e6d80c82",
-287 => x"a0800b0b",
-288 => x"0b80e6dc",
-289 => x"0c829080",
-290 => x"0b80e6ec",
-291 => x"0c0b0b80",
-292 => x"e6e00b80",
-293 => x"e6f00c04",
-294 => x"f8808080",
-295 => x"a40b0b0b",
-296 => x"80e6d80c",
-297 => x"f8808082",
-298 => x"800b0b0b",
-299 => x"80e6dc0c",
-300 => x"f8808084",
-301 => x"800b80e6",
-302 => x"ec0cf880",
-303 => x"8080940b",
-304 => x"80e6f00c",
-305 => x"f8808080",
-306 => x"9c0b80e6",
-307 => x"e80cf880",
-308 => x"8080a00b",
-309 => x"80e6f40c",
-310 => x"04f23d0d",
-311 => x"600b0b80",
-312 => x"e6dc0856",
-313 => x"5d82750c",
-314 => x"8059805a",
-315 => x"800b8f3d",
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-2844 => x"00000000",
-2845 => x"00000000",
-2846 => x"00000000",
-2847 => x"00000000",
-2848 => x"00000000",
-2849 => x"00000000",
-2850 => x"00000000",
-2851 => x"00000000",
-2852 => x"00000000",
-2853 => x"00000000",
-2854 => x"00000000",
-2855 => x"00000000",
-2856 => x"00000000",
-2857 => x"00000000",
-2858 => x"00000000",
-2859 => x"00000000",
-2860 => x"00000000",
-2861 => x"00000000",
-2862 => x"00000000",
-2863 => x"00000000",
-2864 => x"00000000",
-2865 => x"00000000",
-2866 => x"00000000",
-2867 => x"00000000",
-2868 => x"00000000",
-2869 => x"00000000",
-2870 => x"00000000",
-2871 => x"00000000",
-2872 => x"00000000",
-2873 => x"00000000",
-2874 => x"00000000",
-2875 => x"00000000",
-2876 => x"00000000",
-2877 => x"00000000",
-2878 => x"00000000",
-2879 => x"00000000",
-2880 => x"00000000",
-2881 => x"00000000",
-2882 => x"00000000",
-2883 => x"00000000",
-2884 => x"00000000",
-2885 => x"00000000",
-2886 => x"00000000",
-2887 => x"00000000",
-2888 => x"00000000",
-2889 => x"00000000",
-2890 => x"00000000",
-2891 => x"00000000",
-2892 => x"00000000",
-2893 => x"00000000",
-2894 => x"00000000",
-2895 => x"00000000",
-2896 => x"00000000",
-2897 => x"00000000",
-2898 => x"00000000",
-2899 => x"00000000",
-2900 => x"00000000",
-2901 => x"00000000",
-2902 => x"00000000",
-2903 => x"00000000",
-2904 => x"00000000",
-2905 => x"00000000",
-2906 => x"00000000",
-2907 => x"00000000",
-2908 => x"00000000",
-2909 => x"00000000",
-2910 => x"00000000",
-2911 => x"00000000",
-2912 => x"00000000",
-2913 => x"00000000",
-2914 => x"00000000",
-2915 => x"00000000",
-2916 => x"00000000",
-2917 => x"00000000",
-2918 => x"00000000",
-2919 => x"00000000",
-2920 => x"00000000",
-2921 => x"00000000",
-2922 => x"00000000",
-2923 => x"00000000",
-2924 => x"00000000",
-2925 => x"00000000",
-2926 => x"00000000",
-2927 => x"00000000",
-2928 => x"00000000",
-2929 => x"00000000",
-2930 => x"00000000",
-2931 => x"00000000",
-2932 => x"00000000",
-2933 => x"00000000",
-2934 => x"00000000",
-2935 => x"00000000",
-2936 => x"00000000",
-2937 => x"00000000",
-2938 => x"00000000",
-2939 => x"00000000",
-2940 => x"00000000",
-2941 => x"00000000",
-2942 => x"00000000",
-2943 => x"00000000",
-2944 => x"00000000",
-2945 => x"00000000",
-2946 => x"00000000",
-2947 => x"00000000",
-2948 => x"00000000",
-2949 => x"00000000",
-2950 => x"00000000",
-2951 => x"00000000",
-2952 => x"00000000",
-2953 => x"00000000",
-2954 => x"00000000",
-2955 => x"00000000",
-2956 => x"00000000",
-2957 => x"00000000",
-2958 => x"00000000",
-2959 => x"00000000",
-2960 => x"00000000",
-2961 => x"00000000",
-2962 => x"00000000",
-2963 => x"00000000",
-2964 => x"00000000",
-2965 => x"00000000",
-2966 => x"00000000",
-2967 => x"00000000",
-2968 => x"00000000",
-2969 => x"00000000",
-2970 => x"00000000",
-2971 => x"00000000",
-2972 => x"00000000",
-2973 => x"00000000",
-2974 => x"00000000",
-2975 => x"00000000",
-2976 => x"00000000",
-2977 => x"00000000",
-2978 => x"00000000",
-2979 => x"00000000",
-2980 => x"00000000",
-2981 => x"00000000",
-2982 => x"00000000",
-2983 => x"00000000",
-2984 => x"00000000",
-2985 => x"00000000",
-2986 => x"00000000",
-2987 => x"00000000",
-2988 => x"00000000",
-2989 => x"00000000",
-2990 => x"00000000",
-2991 => x"00000000",
-2992 => x"00000000",
-2993 => x"00000000",
-2994 => x"00000000",
-2995 => x"00000000",
-2996 => x"00000000",
-2997 => x"00000000",
-2998 => x"00000000",
-2999 => x"00000000",
-3000 => x"00000000",
-3001 => x"00000000",
-3002 => x"00000000",
-3003 => x"00000000",
-3004 => x"00000000",
-3005 => x"00000000",
-3006 => x"00000000",
-3007 => x"00000000",
-3008 => x"00000000",
-3009 => x"00000000",
-3010 => x"00000000",
-3011 => x"00000000",
-3012 => x"00000000",
-3013 => x"00000000",
-3014 => x"00000000",
-3015 => x"00000000",
-3016 => x"00000000",
-3017 => x"00000000",
-3018 => x"00000000",
-3019 => x"ffffffff",
-3020 => x"00000000",
-3021 => x"00020000",
-3022 => x"00000000",
-3023 => x"00000000",
-3024 => x"00002f38",
-3025 => x"00002f38",
-3026 => x"00002f40",
-3027 => x"00002f40",
-3028 => x"00002f48",
-3029 => x"00002f48",
-3030 => x"00002f50",
-3031 => x"00002f50",
-3032 => x"00002f58",
-3033 => x"00002f58",
-3034 => x"00002f60",
-3035 => x"00002f60",
-3036 => x"00002f68",
-3037 => x"00002f68",
-3038 => x"00002f70",
-3039 => x"00002f70",
-3040 => x"00002f78",
-3041 => x"00002f78",
-3042 => x"00002f80",
-3043 => x"00002f80",
-3044 => x"00002f88",
-3045 => x"00002f88",
-3046 => x"00002f90",
-3047 => x"00002f90",
-3048 => x"00002f98",
-3049 => x"00002f98",
-3050 => x"00002fa0",
-3051 => x"00002fa0",
-3052 => x"00002fa8",
-3053 => x"00002fa8",
-3054 => x"00002fb0",
-3055 => x"00002fb0",
-3056 => x"00002fb8",
-3057 => x"00002fb8",
-3058 => x"00002fc0",
-3059 => x"00002fc0",
-3060 => x"00002fc8",
-3061 => x"00002fc8",
-3062 => x"00002fd0",
-3063 => x"00002fd0",
-3064 => x"00002fd8",
-3065 => x"00002fd8",
-3066 => x"00002fe0",
-3067 => x"00002fe0",
-3068 => x"00002fe8",
-3069 => x"00002fe8",
-3070 => x"00002ff0",
-3071 => x"00002ff0",
-3072 => x"00002ff8",
-3073 => x"00002ff8",
-3074 => x"00003000",
-3075 => x"00003000",
-3076 => x"00003008",
-3077 => x"00003008",
-3078 => x"00003010",
-3079 => x"00003010",
-3080 => x"00003018",
-3081 => x"00003018",
-3082 => x"00003020",
-3083 => x"00003020",
-3084 => x"00003028",
-3085 => x"00003028",
-3086 => x"00003030",
-3087 => x"00003030",
-3088 => x"00003038",
-3089 => x"00003038",
-3090 => x"00003040",
-3091 => x"00003040",
-3092 => x"00003048",
-3093 => x"00003048",
-3094 => x"00003050",
-3095 => x"00003050",
-3096 => x"00003058",
-3097 => x"00003058",
-3098 => x"00003060",
-3099 => x"00003060",
-3100 => x"00003068",
-3101 => x"00003068",
-3102 => x"00003070",
-3103 => x"00003070",
-3104 => x"00003078",
-3105 => x"00003078",
-3106 => x"00003080",
-3107 => x"00003080",
-3108 => x"00003088",
-3109 => x"00003088",
-3110 => x"00003090",
-3111 => x"00003090",
-3112 => x"00003098",
-3113 => x"00003098",
-3114 => x"000030a0",
-3115 => x"000030a0",
-3116 => x"000030a8",
-3117 => x"000030a8",
-3118 => x"000030b0",
-3119 => x"000030b0",
-3120 => x"000030b8",
-3121 => x"000030b8",
-3122 => x"000030c0",
-3123 => x"000030c0",
-3124 => x"000030c8",
-3125 => x"000030c8",
-3126 => x"000030d0",
-3127 => x"000030d0",
-3128 => x"000030d8",
-3129 => x"000030d8",
-3130 => x"000030e0",
-3131 => x"000030e0",
-3132 => x"000030e8",
-3133 => x"000030e8",
-3134 => x"000030f0",
-3135 => x"000030f0",
-3136 => x"000030f8",
-3137 => x"000030f8",
-3138 => x"00003100",
-3139 => x"00003100",
-3140 => x"00003108",
-3141 => x"00003108",
-3142 => x"00003110",
-3143 => x"00003110",
-3144 => x"00003118",
-3145 => x"00003118",
-3146 => x"00003120",
-3147 => x"00003120",
-3148 => x"00003128",
-3149 => x"00003128",
-3150 => x"00003130",
-3151 => x"00003130",
-3152 => x"00003138",
-3153 => x"00003138",
-3154 => x"00003140",
-3155 => x"00003140",
-3156 => x"00003148",
-3157 => x"00003148",
-3158 => x"00003150",
-3159 => x"00003150",
-3160 => x"00003158",
-3161 => x"00003158",
-3162 => x"00003160",
-3163 => x"00003160",
-3164 => x"00003168",
-3165 => x"00003168",
-3166 => x"00003170",
-3167 => x"00003170",
-3168 => x"00003178",
-3169 => x"00003178",
-3170 => x"00003180",
-3171 => x"00003180",
-3172 => x"00003188",
-3173 => x"00003188",
-3174 => x"00003190",
-3175 => x"00003190",
-3176 => x"00003198",
-3177 => x"00003198",
-3178 => x"000031a0",
-3179 => x"000031a0",
-3180 => x"000031a8",
-3181 => x"000031a8",
-3182 => x"000031b0",
-3183 => x"000031b0",
-3184 => x"000031b8",
-3185 => x"000031b8",
-3186 => x"000031c0",
-3187 => x"000031c0",
-3188 => x"000031c8",
-3189 => x"000031c8",
-3190 => x"000031d0",
-3191 => x"000031d0",
-3192 => x"000031d8",
-3193 => x"000031d8",
-3194 => x"000031e0",
-3195 => x"000031e0",
-3196 => x"000031e8",
-3197 => x"000031e8",
-3198 => x"000031f0",
-3199 => x"000031f0",
-3200 => x"000031f8",
-3201 => x"000031f8",
-3202 => x"00003200",
-3203 => x"00003200",
-3204 => x"00003208",
-3205 => x"00003208",
-3206 => x"00003210",
-3207 => x"00003210",
-3208 => x"00003218",
-3209 => x"00003218",
-3210 => x"00003220",
-3211 => x"00003220",
-3212 => x"00003228",
-3213 => x"00003228",
-3214 => x"00003230",
-3215 => x"00003230",
-3216 => x"00003238",
-3217 => x"00003238",
-3218 => x"00003240",
-3219 => x"00003240",
-3220 => x"00003248",
-3221 => x"00003248",
-3222 => x"00003250",
-3223 => x"00003250",
-3224 => x"00003258",
-3225 => x"00003258",
-3226 => x"00003260",
-3227 => x"00003260",
-3228 => x"00003268",
-3229 => x"00003268",
-3230 => x"00003270",
-3231 => x"00003270",
-3232 => x"00003278",
-3233 => x"00003278",
-3234 => x"00003280",
-3235 => x"00003280",
-3236 => x"00003288",
-3237 => x"00003288",
-3238 => x"00003290",
-3239 => x"00003290",
-3240 => x"00003298",
-3241 => x"00003298",
-3242 => x"000032a0",
-3243 => x"000032a0",
-3244 => x"000032a8",
-3245 => x"000032a8",
-3246 => x"000032b0",
-3247 => x"000032b0",
-3248 => x"000032b8",
-3249 => x"000032b8",
-3250 => x"000032c0",
-3251 => x"000032c0",
-3252 => x"000032c8",
-3253 => x"000032c8",
-3254 => x"000032d0",
-3255 => x"000032d0",
-3256 => x"000032d8",
-3257 => x"000032d8",
-3258 => x"000032e0",
-3259 => x"000032e0",
-3260 => x"000032e8",
-3261 => x"000032e8",
-3262 => x"000032f0",
-3263 => x"000032f0",
-3264 => x"000032f8",
-3265 => x"000032f8",
-3266 => x"00003300",
-3267 => x"00003300",
-3268 => x"00003308",
-3269 => x"00003308",
-3270 => x"00003310",
-3271 => x"00003310",
-3272 => x"00003318",
-3273 => x"00003318",
-3274 => x"00003320",
-3275 => x"00003320",
-3276 => x"00003328",
-3277 => x"00003328",
-3278 => x"00003330",
-3279 => x"00003330",
-3280 => x"00002b50",
-3281 => x"ffffffff",
-3282 => x"00000000",
-3283 => x"ffffffff",
-3284 => x"00000000",
- others => x"00000000"
-);
-
-begin
-
-process (clk)
-begin
- if (clk'event and clk = '1') then
- if (memAWriteEnable = '1') then
- ram(conv_integer(memAAddr)) := memAWrite;
- memARead <= memAWrite;
- else
- memARead <= ram(conv_integer(memAAddr));
- end if;
- end if;
-end process;
-
-process (clk)
-begin
- if (clk'event and clk = '1') then
- if (memBWriteEnable = '1') then
- ram(conv_integer(memBAddr)) := memBWrite;
- memBRead <= memBWrite;
- else
- memBRead <= ram(conv_integer(memBAddr));
- end if;
- end if;
-end process;
-
-
-
-
-end dualport_ram_arch;
diff --git a/zpu/hdl/zpu3/src/ic300.bitgen b/zpu/hdl/zpu3/src/ic300.bitgen deleted file mode 100644 index 1095099..0000000 --- a/zpu/hdl/zpu3/src/ic300.bitgen +++ /dev/null @@ -1,27 +0,0 @@ --g DebugBitstream:No
--g Binary:yes
--g CRC:Enable
--g ConfigRate:50
--g CclkPin:Pullnone
--g M0Pin:Pullnone
--g M1Pin:Pullnone
--g M2Pin:Pullnone
--g ProgPin:PullUp
--g DonePin:Pullnone
--g TckPin:Pullnone
--g TdiPin:Pullnone
--g TdoPin:Pullnone
--g TmsPin:Pullnone
--g UnusedPin:Pullnone
--g UserID:0xFFFFFFFF
--g DCMShutDown:Disable
--g DCIUpdateMode:AsRequired
--g StartUpClk:CClk
--g DONE_cycle:4
--g GTS_cycle:5
--g GWE_cycle:6
--g LCK_cycle:NoWait
--g Security:Level1
--g DonePipe:No
--g DriveDone:Yes
-
diff --git a/zpu/hdl/zpu3/src/ic300.lso b/zpu/hdl/zpu3/src/ic300.lso deleted file mode 100644 index 22de730..0000000 --- a/zpu/hdl/zpu3/src/ic300.lso +++ /dev/null @@ -1 +0,0 @@ -work
diff --git a/zpu/hdl/zpu3/src/ic300.ucf b/zpu/hdl/zpu3/src/ic300.ucf deleted file mode 100644 index e11357f..0000000 --- a/zpu/hdl/zpu3/src/ic300.ucf +++ /dev/null @@ -1,146 +0,0 @@ -# clock inputs
-net "cpu_clk_p" loc = "R9" | iostandard=LVTTL;
-
-# input pins
-net "cpu_a_p(0)" loc = "N15" | iostandard=LVTTL;
-net "cpu_a_p(1)" loc = "P16" | iostandard=LVTTL;
-net "cpu_a_p(2)" loc = "P13" | iostandard=LVTTL;
-net "cpu_a_p(3)" loc = "N16" | iostandard=LVTTL;
-net "cpu_a_p(4)" loc = "P15" | iostandard=LVTTL;
-net "cpu_a_p(5)" loc = "R11" | iostandard=LVTTL;
-net "cpu_a_p(6)" loc = "T14" | iostandard=LVTTL;
-net "cpu_a_p(7)" loc = "R16" | iostandard=LVTTL;
-net "cpu_a_p(8)" loc = "P14" | iostandard=LVTTL;
-net "cpu_a_p(9)" loc = "T13" | iostandard=LVTTL;
-net "cpu_a_p(10)" loc = "R13" | iostandard=LVTTL;
-net "cpu_a_p(11)" loc = "P7" | iostandard=LVTTL;
-net "cpu_a_p(12)" loc = "N12" | iostandard=LVTTL;
-net "cpu_a_p(13)" loc = "R12" | iostandard=LVTTL;
-net "cpu_a_p(14)" loc = "L13" | iostandard=LVTTL;
-net "cpu_a_p(15)" loc = "K12" | iostandard=LVTTL;
-net "cpu_a_p(16)" loc = "K15" | iostandard=LVTTL;
-net "cpu_a_p(17)" loc = "T10" | iostandard=LVTTL;
-net "cpu_a_p(18)" loc = "T9" | iostandard=LVTTL;
-net "cpu_a_p(19)" loc = "N10" | iostandard=LVTTL;
-net "cpu_a_p(20)" loc = "T8" | iostandard=LVTTL;
-net "cpu_wr_n_p(0)" loc = "L15" | iostandard=LVTTL;
-net "cpu_wr_n_p(1)" loc = "N14" | iostandard=LVTTL;
-net "cpu_oe_n_p" loc = "T12" | iostandard=LVTTL;
-net "cpu_cs_n_p(1)" loc = "R3" | iostandard=LVTTL;
-net "cpu_cs_n_p(2)" loc = "M16" | iostandard=LVTTL;
-net "cpu_cs_n_p(3)" loc = "P11" | iostandard=LVTTL;
-
-#net "sdr_clk_fb_p" loc = "B8" | iostandard=SSTL2_I;
-
-# output pins
-net "cpu_fiq_p" loc = "K16" | iostandard=LVTTL;
-net "cpu_irq_p(0)" loc = "M14" | iostandard=LVTTL;
-net "cpu_irq_p(1)" loc = "J16" | iostandard=LVTTL;
-net "cpu_wait_n_p" loc = "M15" | iostandard=LVTTL;
-
-#net "sdr_clk_p" loc = "D8" | iostandard=SSTL2_I | FAST;
-#net "sdr_clk_n_p" loc = "F5" | iostandard=SSTL2_I | FAST;
-#net "cke_q_p" loc = "F4" | iostandard=SSTL2_I | FAST;
-#net "cs_qn_p" loc = "M2" | iostandard=SSTL2_I | FAST | PULLUP;
-#net "ras_qn_p" loc = "J2" | iostandard=SSTL2_I | FAST | PULLUP | NODELAY;
-#net "cas_qn_p" loc = "M3" | iostandard=SSTL2_I | FAST | PULLUP | NODELAY;
-#net "we_qn_p" loc = "K4" | iostandard=SSTL2_I | FAST | PULLUP | NODELAY;
-#net "dm_q_p(0)" loc = "L4" | iostandard=SSTL2_I | FAST;
-#net "dm_q_p(1)" loc = "E4" | iostandard=SSTL2_I | FAST;
-#net "dqs_q_p(0)" loc = "L3" | iostandard=SSTL2_I | FAST;
-#net "dqs_q_p(1)" loc = "D3" | iostandard=SSTL2_I | FAST;
-#net "ba_q_p(0)" loc = "M1" | iostandard=SSTL2_I | FAST;
-#net "ba_q_p(1)" loc = "J3" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(0)" loc = "J4" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(1)" loc = "N2" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(2)" loc = "H4" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(3)" loc = "P2" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(4)" loc = "E7" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(5)" loc = "G4" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(6)" loc = "D7" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(7)" loc = "G5" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(8)" loc = "C7" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(9)" loc = "F3" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(10)" loc = "N3" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(11)" loc = "E6" | iostandard=SSTL2_I | FAST;
-#net "sdr_a_p(12)" loc = "D6" | iostandard=SSTL2_I | FAST;
-
-# bidirectional pins
-net "cpu_d_p(0)" loc = "M11" | iostandard=LVTTL;
-net "cpu_d_p(1)" loc = "N11" | iostandard=LVTTL;
-net "cpu_d_p(2)" loc = "P10" | iostandard=LVTTL;
-net "cpu_d_p(3)" loc = "R10" | iostandard=LVTTL;
-net "cpu_d_p(4)" loc = "T7" | iostandard=LVTTL;
-net "cpu_d_p(5)" loc = "R7" | iostandard=LVTTL;
-net "cpu_d_p(6)" loc = "N6" | iostandard=LVTTL;
-net "cpu_d_p(7)" loc = "M6" | iostandard=LVTTL;
-net "cpu_d_p(8)" loc = "K13" | iostandard=LVTTL;
-net "cpu_d_p(9)" loc = "M10" | iostandard=LVTTL;
-net "cpu_d_p(10)" loc = "L12" | iostandard=LVTTL;
-net "cpu_d_p(11)" loc = "M13" | iostandard=LVTTL;
-net "cpu_d_p(12)" loc = "K14" | iostandard=LVTTL;
-net "cpu_d_p(13)" loc = "L14" | iostandard=LVTTL;
-net "cpu_d_p(14)" loc = "J13" | iostandard=LVTTL;
-net "cpu_d_p(15)" loc = "J14" | iostandard=LVTTL;
-
-#net "sdr_d_p(0)" loc = "G1" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(1)" loc = "H3" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(2)" loc = "G3" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(3)" loc = "K2" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(4)" loc = "F2" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(5)" loc = "L2" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(6)" loc = "E1" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(7)" loc = "M4" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(8)" loc = "C6" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(9)" loc = "E2" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(10)" loc = "C2" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(11)" loc = "D1" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(12)" loc = "B7" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(13)" loc = "D2" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(14)" loc = "B6" | iostandard=SSTL2_I | NODELAY | FAST;
-#net "sdr_d_p(15)" loc = "B5" | iostandard=SSTL2_I | NODELAY | FAST;
-
-# TIMING
-# Create timing names
-NET "cpu_clk_p" TNM_NET = "cpu_clk_p";
-NET "sdr_clk_fb_p" TNM_NET = "sdr_clk_fb_p";
-#NET "cpu_clk" TNM_NET = "cpu_clk";
-#NET "cpu_clk_2x" TNM_NET = "cpu_clk_2x";
-#NET "cpu_clk_4x" TNM_NET = "cpu_clk_4x";
-#NET "ddr_in_clk" TNM_NET = "ddr_in_clk";
-#NET "ddr_in_clk_2x" TNM_NET = "ddr_in_clk_2x";
-
-## Create timing
-
-# Periode timing
-TIMESPEC "TS_cpu_clk" = PERIOD "cpu_clk_p" 15.6 ns HIGH 50 %;
-#TIMESPEC "TS_sdr_clk_fb_p" = PERIOD "sdr_clk_fb_p" 7.8 ns HIGH 50 %;
-
-# Clock domain crossing timing
-#TIMESPEC "TS_cpu1_to_cpu2" = FROM "cpu_clk" TO "cpu_clk_2x" 7.8 ns;
-#TIMESPEC "TS_cpu1_to_cpu4" = FROM "cpu_clk" TO "cpu_clk_4x" 3.9 ns;
-#TIMESPEC "TS_cpu1_to_ddr2" = FROM "cpu_clk" TO "ddr_in_clk" 7.8 ns;
-#TIMESPEC "TS_cpu1_to_ddr2_2x" = FROM "cpu_clk" TO "ddr_in_clk_2x" 3.9 ns;
-
-#TIMESPEC "TS_cpu2_to_cpu1" = FROM "cpu_clk_2x" TO "cpu_clk" 7.8 ns;
-#TIMESPEC "TS_cpu2_to_cpu4" = FROM "cpu_clk_2x" TO "cpu_clk_4x" 3.9 ns;
-#TIMESPEC "TS_cpu2_to_ddr2" = FROM "cpu_clk_2x" TO "ddr_in_clk" 7.8 ns;
-#TIMESPEC "TS_cpu2_to_ddr_2x" = FROM "cpu_clk_2x" TO "ddr_in_clk_2x" 3.9 ns;
-
-#TIMESPEC "TS_cpu4_to_cpu1" = FROM "cpu_clk_4x" TO "cpu_clk" 3.9 ns;
-#TIMESPEC "TS_cpu4_to_cpu2" = FROM "cpu_clk_4x" TO "cpu_clk_2x" 3.9 ns;
-#TIMESPEC "TS_cpu4_to_ddr2" = FROM "cpu_clk_4x" TO "ddr_in_clk" 3.9 ns;
-#TIMESPEC "TS_cpu4_to_ddr2_2x" = FROM "cpu_clk_4x" TO "ddr_in_clk_2x" 3.9 ns;
-
-#TIMESPEC "TS_ddr2_to_cpu1" = FROM "ddr_in_clk" TO "cpu_clk" 7.8 ns;
-#TIMESPEC "TS_ddr2_to_cpu2" = FROM "ddr_in_clk" TO "cpu_clk_2x" 7.8 ns;
-#TIMESPEC "TS_ddr2_to_cpu4" = FROM "ddr_in_clk" TO "cpu_clk_4x" 3.9 ns;
-#TIMESPEC "TS_ddr2_to_ddr2_2x" = FROM "ddr_in_clk" TO "ddr_in_clk_2x" 3.9 ns;
-
-#TIMESPEC "TS_ddr2_2x_to_cpu1" = FROM "ddr_in_clk_2x" TO "cpu_clk" 3.9 ns;
-#TIMESPEC "TS_ddr2_2x_to_cpu2" = FROM "ddr_in_clk_2x" TO "cpu_clk_2x" 3.9 ns;
-#TIMESPEC "TS_ddr2_2x_to_cpu4" = FROM "ddr_in_clk_2x" TO "cpu_clk_4x" 3.9 ns;
-#TIMESPEC "TS_ddr2_2x_to_ddr2" = FROM "ddr_in_clk_2x" TO "ddr_in_clk" 3.9 ns;
-
-
-
diff --git a/zpu/hdl/zpu3/src/ic300.vhd b/zpu/hdl/zpu3/src/ic300.vhd deleted file mode 100644 index a1b4f41..0000000 --- a/zpu/hdl/zpu3/src/ic300.vhd +++ /dev/null @@ -1,144 +0,0 @@ ---------------------------------------------------------------------------------
--- Company: Zylin AS
--- Engineer: Tore Ramsland
---
--- Create Date: 21:47:41 07/03/05
--- Design Name: ic300
--- Module Name: ic300 - behave
--- Project Name: eCosBoard
--- Target Device: XC3S400400-FG256
--- Tool versions: 7.1i
--- Description: Top level
---
--- Dependencies:
---
--- Revision:
--- 2005-07-11 Updated to test FPGA
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library UNISIM;
-use UNISIM.VComponents.all;
-
-library zylin;
-use zylin.arm7.all;
-
-library zylin;
-use zylin.zpu_config.all;
-use zylin.zpupkg.all;
-
-library work;
-use work.phi_config.all;
-use work.ic300pkg.all;
-
-entity ic300 is
- generic(
- simulate_io_time : boolean := false);
- port ( -- Clock inputs
- cpu_clk_p : in std_logic;
-
- -- CPU interface signals
- cpu_a_p : in std_logic_vector(20 downto 0);
- cpu_wr_n_p : in std_logic_vector(1 downto 0);
- cpu_cs_n_p : in std_logic_vector(3 downto 1);
- cpu_oe_n_p : in std_logic;
- cpu_d_p : inout std_logic_vector(15 downto 0);
- cpu_irq_p : out std_logic_vector(1 downto 0);
- cpu_fiq_p : out std_logic;
- cpu_wait_n_p : out std_logic;
-
- -- DDR SDRAM Signals
- sdr_clk_p : out std_logic; -- ddr_sdram_clock
- sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock
- cke_q_p : out std_logic; -- clock enable
- cs_qn_p : out std_logic; -- /chip select
- ras_qn_p : inout std_logic; -- /ras
- cas_qn_p : inout std_logic; -- /cas
- we_qn_p : inout std_logic; -- /write enable
- dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00"
- dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write
- ba_q_p : out std_logic_vector(1 downto 0); -- bank select
- sdr_a_p : out std_logic_vector(12 downto 0); -- address bus
- sdr_d_p : inout std_logic_vector(15 downto 0); -- bidir data bus
- sdr_clk_fb_p : in std_logic -- DDR clock feedback
- );
-end ic300;
-
-architecture behave of ic300 is
-
-signal cpu_we : std_logic_vector(1 downto 0); -- Write signal for lower(0) and upper(1) 8 data bits
-signal cpu_re : std_logic; -- Read enable signal for all 16 bits
-signal areset : std_logic; -- Asyncronous active high reset (for initialization)
-signal areset_dummy : std_logic;
-
--- Clock module signals
-signal clk_status : std_logic_vector(2 downto 0); -- DLL lock status (from 3 DLL's)
-signal cpu_clk : std_logic; -- 64 MHz CPU clk
-signal cpu_clk_2x : std_logic; -- 128 MHz CPU clk (in phase with 64 MHz)
-signal cpu_clk_4x : std_logic; -- 256 MHz CPU clk (in phase with 64 MHz)
-signal ddr_in_clk : std_logic; -- 128 MHz clock from DDR SDRAM
-signal ddr_in_clk_2x : std_logic; -- 256 MHz clock from DDR SDRAM
- -- NOTE! Phase relation to 64 MHz clock unknown
-
--- Internal CPU interface signals
-signal cpu_din : std_logic_vector(15 downto 0); -- 16-bit data from CPU
-signal cpu_dout : std_logic_vector(15 downto 0); -- 16-bit data to CPU
-signal cpu_a : std_logic_vector(20 downto 0); -- 21-bit address from CPU
-
-begin
-
--- areset <= '0';
- areset_dummy <= '0';
-
- global_init_reset:
- rocbuf port map(I=>areset_dummy,O=>areset);
-
- allclocks:
- clocks port map(
- areset => areset,
- cpu_clk_p => cpu_clk_p,
- cpu_clk => cpu_clk,
- cpu_clk_2x => cpu_clk_2x,
- cpu_clk_4x => cpu_clk_4x,
- sdr_clk_fb_p => sdr_clk_fb_p,
- ddr_in_clk => ddr_in_clk,
- ddr_in_clk_2x => ddr_in_clk_2x,
- locked => clk_status);
-
- arm7cpu:
- arm7wb generic map (simulate_io_time => simulate_io_time)
- port map(
- areset => areset,
- cpu_clk => cpu_clk,
- cpu_clk_2x => cpu_clk_2x,
- cpu_a_p => cpu_a_p,
- cpu_wr_n_p => cpu_wr_n_p,
- cpu_cs_n_p => cpu_cs_n_p,
- cpu_oe_n_p => cpu_oe_n_p,
- cpu_d_p => cpu_d_p,
- cpu_irq_p => cpu_irq_p,
- cpu_fiq_p => cpu_fiq_p,
- cpu_wait_n_p => cpu_wait_n_p,
- cpu_din => cpu_din,
- cpu_a => cpu_a,
- cpu_we => cpu_we,
- cpu_re => cpu_re,
- cpu_dout => cpu_dout);
-
-
- cpu_fpga_regs:
- zpuio port map(
- areset => areset,
- cpu_clk => cpu_clk,
- clk_status => clk_status,
- cpu_din => cpu_din,
- cpu_a => cpu_a,
- cpu_we => cpu_we,
- cpu_re => cpu_re,
- cpu_dout => cpu_dout);
-
-
-end behave;
diff --git a/zpu/hdl/zpu3/src/ic300_config.vhd b/zpu/hdl/zpu3/src/ic300_config.vhd deleted file mode 100644 index 9d3f939..0000000 --- a/zpu/hdl/zpu3/src/ic300_config.vhd +++ /dev/null @@ -1,20 +0,0 @@ -library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-package phi_config is
-
- constant Fpga_Global_Base : std_logic_vector(19 downto 17) := "000"; -- 0x0280....
- constant Clock_Stat_Reg_Addr : std_logic_vector(3 downto 1) := "000"; -- 0x....0000
- constant Testreg32_Lower_Addr : std_logic_vector(3 downto 1) := "110"; -- 0x....000C
- constant Testreg32_Upper_Addr : std_logic_vector(3 downto 1) := "111"; -- 0x....000E
-
- constant Fpga_DDR_Ctrl_Base : std_logic_vector(19 downto 17) := "111"; -- 0x028E....
- constant DDR_Ctrl_Reg_Addr : std_logic_vector(3 downto 1) := "000"; -- 0x....0000
- constant DDR_Mode_Reg_Addr : std_logic_vector(3 downto 1) := "001"; -- 0x....0002
-
- -- These are temporary test registers only!
- constant DDR_Data_Reg_Addr : std_logic_vector(3 downto 1) := "100"; -- 0x....0008
- constant DDR_Addr_Reg_Addr : std_logic_vector(3 downto 1) := "101"; -- 0x....000A
- constant DDR_Req_Reg_Addr : std_logic_vector(3 downto 1) := "110"; -- 0x....000C
-
-end phi_config;
diff --git a/zpu/hdl/zpu3/src/ic300pkg.vhd b/zpu/hdl/zpu3/src/ic300pkg.vhd deleted file mode 100644 index 13da306..0000000 --- a/zpu/hdl/zpu3/src/ic300pkg.vhd +++ /dev/null @@ -1,88 +0,0 @@ -library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-package ic300pkg is
-
- component ic300 is
- port ( -- Clock inputs
- cpu_clk_p : in std_logic;
-
- -- CPU interface signals
- cpu_a_p : in std_logic_vector(20 downto 0);
- cpu_wr_n_p : in std_logic_vector(1 downto 0);
- cpu_cs_n_p : in std_logic_vector(3 downto 1);
- cpu_oe_n_p : in std_logic;
- cpu_d_p : inout std_logic_vector(15 downto 0);
- cpu_irq_p : out std_logic_vector(1 downto 0);
- cpu_fiq_p : out std_logic;
- cpu_wait_n_p : out std_logic;
-
- -- DDR SDRAM Signals
- sdr_clk_p : out std_logic; -- ddr_sdram_clock
- sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock
- cke_q_p : out std_logic; -- clock enable
- cs_qn_p : out std_logic; -- /chip select
- ras_qn_p : inout std_logic; -- /ras
- cas_qn_p : inout std_logic; -- /cas
- we_qn_p : inout std_logic; -- /write enable
- dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00"
- dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write
- ba_q_p : out std_logic_vector(1 downto 0); -- bank select
- sdr_a_p : out std_logic_vector(12 downto 0); -- address bus
- sdr_d_p : inout std_logic_vector(15 downto 0); -- bidir data bus
- sdr_clk_fb_p : in std_logic -- DDR clock feedback
- );
- end component;
-
- component clocks is
- port ( areset : in std_logic;
- cpu_clk_p : in std_logic;
- sdr_clk_fb_p : in std_logic;
- cpu_clk : out std_logic;
- cpu_clk_2x : out std_logic;
- cpu_clk_4x : out std_logic;
- ddr_in_clk : out std_logic;
- ddr_in_clk_2x : out std_logic;
- locked : out std_logic_vector(2 downto 0));
- end component;
-
- component cpu_regs is
- port ( areset : in std_logic;
- cpu_clk : in std_logic;
- clk_status : in std_logic_vector(2 downto 0);
- cpu_din : in std_logic_vector(15 downto 0);
- cpu_a : in std_logic_vector(20 downto 0);
- cpu_we : in std_logic_vector(1 downto 0);
- cpu_re : in std_logic;
- cpu_dout : inout std_logic_vector(15 downto 0));
- end component;
-
- component ddr_bridge is
- port ( areset : in std_logic;
- cpu_clk : in std_logic;
- cpu_clk_2x : in std_logic;
- cpu_clk_4x : in std_logic;
- ddr_in_clk : in std_logic;
- ddr_in_clk_2x : in std_logic;
-
- cpu_we : in std_logic_vector(1 downto 0);
- cpu_re : in std_logic;
- cpu_din : in std_logic_vector(15 downto 0);
- cpu_a : in std_logic_vector(20 downto 0);
- cpu_dout : inout std_logic_vector(15 downto 0);
-
- sdr_clk_p : out std_logic; -- ddr_sdram_clock
- sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock
- cke_q_p : out std_logic; -- clock enable
- cs_qn_p : out std_logic; -- /chip select
- ras_qn_p : inout std_logic; -- /ras
- cas_qn_p : inout std_logic; -- /cas
- we_qn_p : inout std_logic; -- /write enable
- dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00"
- dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write
- ba_q_p : out std_logic_vector(1 downto 0); -- bank select
- sdr_a_p : out std_logic_vector(12 downto 0); -- address bus
- sdr_d_p : inout std_logic_vector(15 downto 0)); -- bidir data bus
- end component;
-
-end ic300pkg;
diff --git a/zpu/hdl/zpu3/src/io.vhd b/zpu/hdl/zpu3/src/io.vhd deleted file mode 100644 index 6b50ca1..0000000 --- a/zpu/hdl/zpu3/src/io.vhd +++ /dev/null @@ -1,95 +0,0 @@ -library ieee;
-use ieee.std_logic_1164.all;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-use std.textio.all;
-
-library zylin;
-use zylin.zpu_config.all;
-use zylin.zpupkg.all;
-use zylin.txt_util.all;
-
-entity zpu_io is
- generic (
- log_file: string := "log.txt"
- );
- port(
- clk : in std_logic;
- areset : in std_logic;
- busy : out std_logic;
- writeEnable : in std_logic;
- readEnable : in std_logic;
- write : in std_logic_vector(7 downto 0);
- read : out std_logic_vector(7 downto 0);
- addr : in std_logic_vector(maxAddrBit downto minAddrBit)
- );
-end zpu_io;
-
-
-architecture behave of zpu_io is
-
-
-
-signal timer_read : std_logic_vector(7 downto 0);
---signal timer_write : std_logic_vector(7 downto 0);
-signal timer_we : std_logic;
-
-file l_file : TEXT open write_mode is log_file;
-
-begin
-
-
- timerinst: timer port map (
- clk => clk,
- areset => areset,
- we => timer_we,
- din => write,
- adr => addr(4 downto 2),
- dout => timer_read);
-
-
- process(areset, clk)
- begin
- if (areset = '1') then
- timer_we <= '0';
- busy <= '1';
- elsif (clk'event and clk = '1') then
- busy <= '1';
- timer_we <= '0';
- if writeEnable = '1' then
- -- external interface
- if addr=x"1000" then
- -- Write to UART
- -- report "" & character'image(conv_integer(memBint)) severity note;
- print(l_file, character'val(conv_integer(write)));
- busy <= '0';
- elsif addr(12)='1' then
- timer_we <= '1';
- busy <= '0';
- else
- report "Illegal IO write" severity failure;
- end if;
-
- end if;
- if (readEnable = '1') then
- if addr=x"1001" then
- read <= (0=>'1', others => '0'); -- recieve empty
- busy <= '0';
- elsif addr(12)='1' then
- read <= timer_read;
- busy <= '0';
- elsif addr(11)='1' then
- read <= ZPU_Frequency;
- busy <= '0';
- else
- report "Illegal IO read" severity failure;
- end if;
- else
- read <= (others => '1');
- end if;
- end if;
- end process;
-
-
-end behave;
-
diff --git a/zpu/hdl/zpu3/src/log.txt b/zpu/hdl/zpu3/src/log.txt deleted file mode 100644 index 5557b06..0000000 --- a/zpu/hdl/zpu3/src/log.txt +++ /dev/null @@ -1,156 +0,0 @@ - - - -D -h -r -y -s -t -o -n -e - -B -e -n -c -h -m -a -r -k -, - -V -e -r -s -i -o -n - -2 -. -1 - -( -L -a -n -g -u -a -g -e -: - -C -) - - - - - - -P -r -o -g -r -a -m - -c -o -m -p -i -l -e -d - -w -i -t -h -o -u -t - -' -r -e -g -i -s -t -e -r -' - -a -t -t -r -i -b -u -t -e - - - - - - -E -x -e -c -u -t -i -o -n - -s -t -a -r -t -s -, - -2 -0 -0 -0 -0 -0 - -r -u -n -s - -t -h -r -o -u -g -h - -D -h -r -y -s -t -o -n -e - - - diff --git a/zpu/hdl/zpu3/src/niltrace.vhd b/zpu/hdl/zpu3/src/niltrace.vhd deleted file mode 100644 index 40fc1ca..0000000 --- a/zpu/hdl/zpu3/src/niltrace.vhd +++ /dev/null @@ -1,26 +0,0 @@ -library ieee;
-use ieee.std_logic_1164.all;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-use std.textio.all;
-use work.zpu_config.all;
-
-
-entity trace is
- port(
- clk : in std_logic;
- begin_inst : in std_logic;
- pc : in std_logic_vector(maxAddrBit downto 0);
- opcode : in std_logic_vector(7 downto 0);
- sp : in std_logic_vector(maxAddrBit downto 2);
- memA : in std_logic_vector(wordSize-1 downto 0);
- busy : in std_logic);
-end trace;
-
-
-architecture behave of trace is
-
-begin
-
-end behave;
-
diff --git a/zpu/hdl/zpu3/src/sim_fpga_top.vhd b/zpu/hdl/zpu3/src/sim_fpga_top.vhd deleted file mode 100644 index 3044606..0000000 --- a/zpu/hdl/zpu3/src/sim_fpga_top.vhd +++ /dev/null @@ -1,127 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 20:15:31 04/14/05 --- Design Name: --- Module Name: fpga_top - behave --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. -library UNISIM; -use UNISIM.VComponents.all; - -library zylin; -use zylin.zpu_config.all; -use zylin.zpupkg.all; - -entity fpga_top is -end fpga_top; - -architecture behave of fpga_top is - - -signal clk : std_logic; - -signal areset : std_logic; - - -component zpu_top is - Port ( clk : in std_logic; - areset : in std_logic; - io_busy : in std_logic; - io_read : in std_logic_vector(7 downto 0); - io_write : out std_logic_vector(7 downto 0); - io_addr : out std_logic_vector(maxAddrBit downto minAddrBit); - io_writeEnable : out std_logic; - io_readEnable : out std_logic; - interrupt : in std_logic; - break : out std_logic); -end component; - - -component zpu_io is - generic ( - log_file: string := "log.txt" - ); - port( - clk : in std_logic; - areset : in std_logic; - busy : out std_logic; - writeEnable : in std_logic; - readEnable : in std_logic; - write : in std_logic_vector(7 downto 0); - read : out std_logic_vector(7 downto 0); - addr : in std_logic_vector(maxAddrBit downto minAddrBit) - ); -end component; - - - -signal io_busy : std_logic; -signal io_read : std_logic_vector(7 downto 0); -signal io_write : std_logic_vector(7 downto 0); -signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit); -signal io_writeEnable : std_logic; -signal io_readEnable : std_logic; - -signal break : std_logic; - -begin - poweronreset: roc port map (O => areset); - - - - zpu: zpu_top port map ( - clk => clk , - areset => areset, - io_busy => io_busy, - io_read => io_read, - io_write => io_write, - io_addr => io_addr, - io_writeEnable => io_writeEnable, - io_readEnable => io_readEnable, - interrupt => '0', - break => break); - - - ioMap: zpu_io port map ( - clk => clk, - areset => areset, - busy => io_busy, - writeEnable => io_writeEnable, - readEnable => io_readEnable, - write => io_write, - read => io_read, - addr => io_addr - ); - - - - -- wiggle the clock @ 100MHz - clock : PROCESS - begin - clk <= '0'; - wait for 5 ns; - clk <= '1'; - wait for 5 ns; - end PROCESS clock; - - -end behave; diff --git a/zpu/hdl/zpu3/src/status.txt b/zpu/hdl/zpu3/src/status.txt deleted file mode 100644 index df8773a..0000000 --- a/zpu/hdl/zpu3/src/status.txt +++ /dev/null @@ -1,67 +0,0 @@ -- Make LOADSP/STORESP/ADDSP/PUSHPC & OR emulated => From 444 => 428 LUT. - A pitiful saving in return for destroying performance. -- If I reduce datapath to 8(which is useless) => 197 LUT. - -Bare bones version of ZPU3: - -- remove NOP, PUSHPC, STORESP, LOADSP, ADDSP and OR instructions. This requires - modification to the GCC toolchain and will result in a fairly significant - code increase. We should still do better than ARM though. -- reduce datapath to 16 bits. This will reduce stack usage, which is good. -- 4kBytes of RAM. - - [exec] ========================================================================= - [exec] Device utilization summary: - [exec] --------------------------- - [exec] Selected Device : 3s400ft256-4 - [exec] Number of Slices: 167 out of 3584 4% - [exec] Number of Slice Flip Flops: 126 out of 7168 1% - [exec] Number of 4 input LUTs: 288 out of 7168 4% - [exec] Number of bonded IOBs: 49 out of 173 28% - [exec] Number of BRAMs: 1 out of 16 6% - [exec] Number of GCLKs: 1 out of 8 12% - [exec] ========================================================================= - - - - -Measurements: - -- Removing PUSHPC(which is possible) reduces usage by 2 LUT's. -- I tried to introduce the instructions as seperate states at the top level, - but did not succeed in reducing LUT count. This might be an avenue to - pursue if asynchronous(?) ROM's could replace logic. -- 550 LUT @ 76MHz. 32 bit datapath & 8 bit instructions. Added seperate decode - stage. -- Tried to move memAControl into decoded opcode. Usage went up to 594 from 550. - -- using 16 bit opcodes to encode signals directly. 466 LUT's. -- w/2kBytes 32 RAM & 32 bit opcodes. 415 LUT's. -- 16 bit opcode, 16 bit datapath and 1kbyte RAM. 292 LUT's. - -- 725 LUT's @ 63MHz - Minimum period: 15.909ns{1} (Maximum frequency: 62.858MHz) -- removed addsp, loadsp & storesp. => 670 LUT's. -- removed all pushes & pops to sp. => 638 LUT's. -- removed OR instruction. => 672 LUT's. -- on the second cycle an ADD is done regardless => 713 LUT's. -- using others => 'x' for e.g. pushsp. 713 => 703. -- switching from lots of prioritized if() for decoding instruction to a case - statement. 713 => 631. -- Using ZPU1's memory scheme instead of inferred memory. 713 => 715, i.e. no - difference. -- Removing AddSP. 715 => 704 LUT's. -- Add COMPARE. 715 => 743 LUT's. -- Slight reorganization of binary operand & NOP 715 => 704. -- STORE only pops 1 (which can be fixed in the assembler). 704 => 701. -- Remove NOP. NOP is only used to clear idim_flag. Use NOT instead. -- Removing FLIP. 681 => 646. Using a different way to generate the FLIP, - 681 => 679. -- Add a seperate memory system for code? -- Use IDIM_FLAG to cache value before IM and make add single cycle. - -- by expanding the opcode to 32 bits, encoding everything in the opcode & - using case statements. 713 => 433 LUT. -- 32 bit opcode w/encoded state & 16 bit datapath. => 325 LUT -- by using 512 byte RAM, 16 bit datapath and 32 bit instructions => 285. - diff --git a/zpu/hdl/zpu3/src/testlut.vhd b/zpu/hdl/zpu3/src/testlut.vhd deleted file mode 100644 index fcc8fde..0000000 --- a/zpu/hdl/zpu3/src/testlut.vhd +++ /dev/null @@ -1,106 +0,0 @@ --- Company: Zylin AS
---
--- Hooks up the ZPU to physical pads to ensure that it is not optimized to
--- oblivion. This is purely to have something to measure LUT usage against.
---
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library zylin;
-use zylin.zpu_config.all;
-use zylin.zpupkg.all;
-
-entity ic300 is
- port ( -- Clock inputs
- cpu_clk_p : in std_logic;
-
- -- CPU interface signals
- cpu_a_p : in std_logic_vector(20 downto 0);
- cpu_wr_n_p : in std_logic_vector(1 downto 0);
- cpu_cs_n_p : in std_logic_vector(3 downto 1);
- cpu_oe_n_p : in std_logic;
- cpu_d_p : out std_logic_vector(15 downto 0);
- cpu_irq_p : out std_logic_vector(1 downto 0);
- cpu_fiq_p : out std_logic;
- cpu_wait_n_p : out std_logic;
-
- sdr_clk_fb_p : in std_logic -- DDR clock feedback
- );
-end ic300;
-
-architecture behave of ic300 is
-
-
-signal io_busy : std_logic;
-signal io_read : std_logic_vector(7 downto 0);
-signal io_write : std_logic_vector(7 downto 0);
-signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit);
-signal io_writeEnable : std_logic;
-signal io_readEnable : std_logic;
-
-
-signal cpu_we : std_logic_vector(1 downto 0);
-signal cpu_re : std_logic;
-signal areset : std_logic;
-
--- Clock module signals
-signal clk_status : std_logic_vector(2 downto 0);
-signal cpu_clk : std_logic;
-signal cpu_clk_2x : std_logic;
-signal cpu_clk_4x : std_logic;
-signal ddr_in_clk : std_logic;
-
-
--- Internal CPU interface signals
-signal cpu_din : std_logic_vector(15 downto 0);
-signal cpu_dout : std_logic_vector(15 downto 0);
-signal cpu_a : std_logic_vector(20 downto 0);
-
-signal dummy : std_logic_vector(maxAddrBit downto minAddrBit+5);
-
-begin
-
- areset <= '0'; -- MUST BE CHANGED TO SOMETHING CORRECT
-
--- cpu_d_p <= (others => '0');
- cpu_irq_p <= (others => '0');
- cpu_fiq_p <= '0';
- cpu_wait_n_p <= '0';
-
- cpu_d_p(15 downto 15) <= (others => '0');
-
- -- delay signals going out/in w/1 clk so the
- -- ZPU does not have to drive those pins.
- --
- -- these registers can be placed close to the ZPU and these
- -- registers then have a full clock to drive the pins.
- process(cpu_clk_p, areset)
- begin
- if (cpu_clk_p'event and cpu_clk_p = '1') then
- cpu_d_p(0) <= io_writeEnable;
- cpu_d_p(1) <= io_readEnable;
- cpu_d_p(9 downto 2) <= io_write;
- io_read <= cpu_a_p(7 downto 0);
- -- 32 read/write registers is plenty realisitic for a minimal size
- -- soft-CPU
- cpu_d_p(14 downto 10) <= io_addr(minAddrBit+4 downto minAddrBit);
- end if;
- end process;
-
-
- zpu: zpu_top port map (
- clk => cpu_clk_p ,
- areset => areset,
- io_busy => '0',
- io_writeEnable => io_writeEnable,
- io_readEnable => io_readEnable,
- io_write => io_write,
- io_read => io_read,
- io_addr => io_addr,
- interrupt => '0'
- );
-
-
-
-end behave;
diff --git a/zpu/hdl/zpu3/src/timer.vhd b/zpu/hdl/zpu3/src/timer.vhd deleted file mode 100644 index 65836f0..0000000 --- a/zpu/hdl/zpu3/src/timer.vhd +++ /dev/null @@ -1,157 +0,0 @@ -library ieee;
-use ieee.std_logic_1164.all;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-entity timer is
- port(
- clk : in std_logic;
- areset : in std_logic;
- we : in std_logic;
- din : in std_logic_vector(7 downto 0);
- adr : in std_logic_vector(2 downto 0);
- dout : out std_logic_vector(7 downto 0));
-end timer;
-
-
-architecture behave of timer is
-
-signal sample : std_logic;
-signal reset : std_logic;
-
-signal c : std_logic_vector(1 to 7);
-
-signal cnt : std_logic_vector(63 downto 0);
-signal cnt_smp : std_logic_vector(63 downto 0);
-
-begin
-
- reset <= '1' when (we = '1' and din(0) = '1') else '0';
- sample <= '1' when (we = '1' and din(1) = '1') else '0';
-
- process(clk, areset) -- Carry generation
- begin
- if areset = '1' then
- c <= "0000000";
- elsif (clk'event and clk = '1') then
- if reset = '1' then
- c <= "0000000";
- else
- if cnt(7 downto 0) = "11111110" then
- c(1) <= '1';
- else
- c(1) <= '0';
- end if;
- if cnt(15 downto 8) = "11111111" then
- c(2) <= '1';
- else
- c(2) <= '0';
- end if;
- if cnt(23 downto 16) = "11111111" and c(2) = '1' then
- c(3) <= '1';
- else
- c(3) <= '0';
- end if;
- if cnt(31 downto 24) = "11111111" and c(3) = '1' then
- c(4) <= '1';
- else
- c(4) <= '0';
- end if;
- if cnt(39 downto 32) = "11111111" and c(4) = '1' then
- c(5) <= '1';
- else
- c(5) <= '0';
- end if;
- if cnt(47 downto 40) = "11111111" and c(5) = '1' then
- c(6) <= '1';
- else
- c(6) <= '0';
- end if;
- if cnt(55 downto 48) = "11111111" and c(6) = '1' then
- c(7) <= '1';
- else
- c(7) <= '0';
- end if;
- end if;
- end if;
- end process;
-
- process(clk, areset)
- begin
- if areset = '1' then
- cnt <= (others=>'0');
- elsif (clk'event and clk = '1') then
- if reset = '1' then
- cnt <= (others=>'0');
- else
- cnt(7 downto 0) <= cnt(7 downto 0) + '1';
- if c(1) = '1' then
- cnt(15 downto 8) <= cnt(15 downto 8) + '1';
- else
- cnt(15 downto 8) <= cnt(15 downto 8);
- end if;
- if c(2) = '1' and c(1) = '1' then
- cnt(23 downto 16) <= cnt(23 downto 16) + '1';
- else
- cnt(23 downto 16) <= cnt(23 downto 16);
- end if;
- if c(3) = '1' and c(1) = '1' then
- cnt(31 downto 24) <= cnt(31 downto 24) + '1';
- else
- cnt(31 downto 24) <= cnt(31 downto 24);
- end if;
- if c(4) = '1' and c(1) = '1' then
- cnt(39 downto 32) <= cnt(39 downto 32) + '1';
- else
- cnt(39 downto 32) <= cnt(39 downto 32);
- end if;
- if c(5) = '1' and c(1) = '1' then
- cnt(47 downto 40) <= cnt(47 downto 40) + '1';
- else
- cnt(47 downto 40) <= cnt(47 downto 40);
- end if;
- if c(6) = '1' and c(1) = '1' then
- cnt(55 downto 48) <= cnt(55 downto 48) + '1';
- else
- cnt(55 downto 48) <= cnt(55 downto 48);
- end if;
- if c(7) = '1' and c(1) = '1' then
- cnt(63 downto 56) <= cnt(63 downto 56) + '1';
- else
- cnt(63 downto 56) <= cnt(63 downto 56);
- end if;
- end if;
- end if;
- end process;
-
- process(clk, areset)
- begin
- if areset = '1' then
- cnt_smp <= (others=>'0');
- elsif (clk'event and clk = '1') then
- if reset = '1' then
- cnt_smp <= (others=>'0');
- elsif sample = '1' then
- cnt_smp <= cnt;
- else
- cnt_smp <= cnt_smp;
- end if;
- end if;
- end process;
-
- process(cnt_smp, adr)
- begin
- case adr is
- when "000" => dout <= cnt_smp(7 downto 0);
- when "001" => dout <= cnt_smp(15 downto 8);
- when "010" => dout <= cnt_smp(23 downto 16);
- when "011" => dout <= cnt_smp(31 downto 24);
- when "100" => dout <= cnt_smp(39 downto 32);
- when "101" => dout <= cnt_smp(47 downto 40);
- when "110" => dout <= cnt_smp(55 downto 48);
- when others => dout <= cnt_smp(63 downto 56);
- end case;
- end process;
-
-
-end behave;
-
diff --git a/zpu/hdl/zpu3/src/trace.vhd b/zpu/hdl/zpu3/src/trace.vhd deleted file mode 100644 index 81eb448..0000000 --- a/zpu/hdl/zpu3/src/trace.vhd +++ /dev/null @@ -1,80 +0,0 @@ -library ieee;
-use ieee.std_logic_1164.all;
---use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-use std.textio.all;
-
-library zylin;
-use zylin.zpu_config.all;
-use zylin.zpupkg.all;
-use zylin.txt_util.all;
-
-
-entity trace is
- generic (
- log_file: string := "trace.txt"
- );
- port(
- clk : in std_logic;
- begin_inst : in std_logic;
- pc : in std_logic_vector(maxAddrBit downto 0);
- opcode : in std_logic_vector(7 downto 0);
- sp : in std_logic_vector(maxAddrBit downto 2);
- memA : in std_logic_vector(wordSize-1 downto 0);
- memB : in std_logic_vector(wordSize-1 downto 0);
- busy : in std_logic
- );
-end trace;
-
-
-architecture behave of trace is
-
-
-file l_file : TEXT open write_mode is log_file;
-
-
-begin
-
-
--- write data and control information to a file
-
-receive_data: process
-
-variable l: line;
-variable t : std_logic_vector(wordSize-1 downto 0);
-variable t2 : std_logic_vector(maxAddrBit downto 0);
-
-
-
-begin
-
- t:= (others => '0');
- t2:= (others => '0');
-
- -- print header for the logfile
- print(l_file, "#pc,opcode,sp,top_of_stack ");
- print(l_file, "#----------");
- print(l_file, " ");
-
- wait until clk = '1';
- wait until clk = '0';
-
- while true loop
-
- if begin_inst = '1' then
- t(maxAddrBit downto 2):=sp;
- t2:=pc;
- print(l_file, "0x" & hstr(t2) & " 0x" & hstr(opcode) & " 0x" & hstr(t) & " 0x" & hstr(memA) & " 0x" & hstr(memB));
- end if;
-
- wait until clk = '0';
-
- end loop;
-
- end process receive_data;
-
-
-
-end behave;
-
diff --git a/zpu/hdl/zpu3/src/txt_util.vhd b/zpu/hdl/zpu3/src/txt_util.vhd deleted file mode 100644 index d42303b..0000000 --- a/zpu/hdl/zpu3/src/txt_util.vhd +++ /dev/null @@ -1,586 +0,0 @@ -library ieee;
-use ieee.std_logic_1164.all;
-use std.textio.all;
-
-
-package txt_util is
-
- -- prints a message to the screen
- procedure print(text: string);
-
- -- prints the message when active
- -- useful for debug switches
- procedure print(active: boolean; text: string);
-
- -- converts std_logic into a character
- function chr(sl: std_logic) return character;
-
- -- converts std_logic into a string (1 to 1)
- function str(sl: std_logic) return string;
-
- -- converts std_logic_vector into a string (binary base)
- function str(slv: std_logic_vector) return string;
-
- -- converts boolean into a string
- function str(b: boolean) return string;
-
- -- converts an integer into a single character
- -- (can also be used for hex conversion and other bases)
- function chr(int: integer) return character;
-
- -- converts integer into string using specified base
- function str(int: integer; base: integer) return string;
-
- -- converts integer to string, using base 10
- function str(int: integer) return string;
-
- -- convert std_logic_vector into a string in hex format
- function hstr(slv: std_logic_vector) return string;
-
-
- -- functions to manipulate strings
- -----------------------------------
-
- -- convert a character to upper case
- function to_upper(c: character) return character;
-
- -- convert a character to lower case
- function to_lower(c: character) return character;
-
- -- convert a string to upper case
- function to_upper(s: string) return string;
-
- -- convert a string to lower case
- function to_lower(s: string) return string;
-
-
-
- -- functions to convert strings into other formats
- --------------------------------------------------
-
- -- converts a character into std_logic
- function to_std_logic(c: character) return std_logic;
-
- -- converts a string into std_logic_vector
- function to_std_logic_vector(s: string) return std_logic_vector;
-
-
-
- -- file I/O
- -----------
-
- -- read variable length string from input file
- procedure str_read(file in_file: TEXT;
- res_string: out string);
-
- -- print string to a file and start new line
- procedure print(file out_file: TEXT;
- new_string: in string);
-
- -- print character to a file and start new line
- procedure print(file out_file: TEXT;
- char: in character);
-
-end txt_util;
-
-
-
-
-package body txt_util is
-
-
-
-
- -- prints text to the screen
-
- procedure print(text: string) is
- variable msg_line: line;
- begin
- write(msg_line, text);
- writeline(output, msg_line);
- end print;
-
-
-
-
- -- prints text to the screen when active
-
- procedure print(active: boolean; text: string) is
- begin
- if active then
- print(text);
- end if;
- end print;
-
-
- -- converts std_logic into a character
-
- function chr(sl: std_logic) return character is
- variable c: character;
- begin
- case sl is
- when 'U' => c:= 'U';
- when 'X' => c:= 'X';
- when '0' => c:= '0';
- when '1' => c:= '1';
- when 'Z' => c:= 'Z';
- when 'W' => c:= 'W';
- when 'L' => c:= 'L';
- when 'H' => c:= 'H';
- when '-' => c:= '-';
- end case;
- return c;
- end chr;
-
-
-
- -- converts std_logic into a string (1 to 1)
-
- function str(sl: std_logic) return string is
- variable s: string(1 to 1);
- begin
- s(1) := chr(sl);
- return s;
- end str;
-
-
-
- -- converts std_logic_vector into a string (binary base)
- -- (this also takes care of the fact that the range of
- -- a string is natural while a std_logic_vector may
- -- have an integer range)
-
- function str(slv: std_logic_vector) return string is
- variable result : string (1 to slv'length);
- variable r : integer;
- begin
- r := 1;
- for i in slv'range loop
- result(r) := chr(slv(i));
- r := r + 1;
- end loop;
- return result;
- end str;
-
-
- function str(b: boolean) return string is
-
- begin
- if b then
- return "true";
- else
- return "false";
- end if;
- end str;
-
-
- -- converts an integer into a character
- -- for 0 to 9 the obvious mapping is used, higher
- -- values are mapped to the characters A-Z
- -- (this is usefull for systems with base > 10)
- -- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
-
- function chr(int: integer) return character is
- variable c: character;
- begin
- case int is
- when 0 => c := '0';
- when 1 => c := '1';
- when 2 => c := '2';
- when 3 => c := '3';
- when 4 => c := '4';
- when 5 => c := '5';
- when 6 => c := '6';
- when 7 => c := '7';
- when 8 => c := '8';
- when 9 => c := '9';
- when 10 => c := 'A';
- when 11 => c := 'B';
- when 12 => c := 'C';
- when 13 => c := 'D';
- when 14 => c := 'E';
- when 15 => c := 'F';
- when 16 => c := 'G';
- when 17 => c := 'H';
- when 18 => c := 'I';
- when 19 => c := 'J';
- when 20 => c := 'K';
- when 21 => c := 'L';
- when 22 => c := 'M';
- when 23 => c := 'N';
- when 24 => c := 'O';
- when 25 => c := 'P';
- when 26 => c := 'Q';
- when 27 => c := 'R';
- when 28 => c := 'S';
- when 29 => c := 'T';
- when 30 => c := 'U';
- when 31 => c := 'V';
- when 32 => c := 'W';
- when 33 => c := 'X';
- when 34 => c := 'Y';
- when 35 => c := 'Z';
- when others => c := '?';
- end case;
- return c;
- end chr;
-
-
-
- -- convert integer to string using specified base
- -- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
-
- function str(int: integer; base: integer) return string is
-
- variable temp: string(1 to 10);
- variable num: integer;
- variable abs_int: integer;
- variable len: integer := 1;
- variable power: integer := 1;
-
- begin
-
- -- bug fix for negative numbers
- abs_int := abs(int);
-
- num := abs_int;
-
- while num >= base loop -- Determine how many
- len := len + 1; -- characters required
- num := num / base; -- to represent the
- end loop ; -- number.
-
- for i in len downto 1 loop -- Convert the number to
- temp(i) := chr(abs_int/power mod base); -- a string starting
- power := power * base; -- with the right hand
- end loop ; -- side.
-
- -- return result and add sign if required
- if int < 0 then
- return '-'& temp(1 to len);
- else
- return temp(1 to len);
- end if;
-
- end str;
-
-
- -- convert integer to string, using base 10
- function str(int: integer) return string is
-
- begin
-
- return str(int, 10) ;
-
- end str;
-
-
-
- -- converts a std_logic_vector into a hex string.
- function hstr(slv: std_logic_vector) return string is
- variable hexlen: integer;
- variable longslv : std_logic_vector(67 downto 0) := (others => '0');
- variable hex : string(1 to 16);
- variable fourbit : std_logic_vector(3 downto 0);
- begin
- hexlen := (slv'left+1)/4;
- if (slv'left+1) mod 4 /= 0 then
- hexlen := hexlen + 1;
- end if;
- longslv(slv'left downto 0) := slv;
- for i in (hexlen -1) downto 0 loop
- fourbit := longslv(((i*4)+3) downto (i*4));
- case fourbit is
- when "0000" => hex(hexlen -I) := '0';
- when "0001" => hex(hexlen -I) := '1';
- when "0010" => hex(hexlen -I) := '2';
- when "0011" => hex(hexlen -I) := '3';
- when "0100" => hex(hexlen -I) := '4';
- when "0101" => hex(hexlen -I) := '5';
- when "0110" => hex(hexlen -I) := '6';
- when "0111" => hex(hexlen -I) := '7';
- when "1000" => hex(hexlen -I) := '8';
- when "1001" => hex(hexlen -I) := '9';
- when "1010" => hex(hexlen -I) := 'A';
- when "1011" => hex(hexlen -I) := 'B';
- when "1100" => hex(hexlen -I) := 'C';
- when "1101" => hex(hexlen -I) := 'D';
- when "1110" => hex(hexlen -I) := 'E';
- when "1111" => hex(hexlen -I) := 'F';
- when "ZZZZ" => hex(hexlen -I) := 'z';
- when "UUUU" => hex(hexlen -I) := 'u';
- when "XXXX" => hex(hexlen -I) := 'x';
- when others => hex(hexlen -I) := '?';
- end case;
- end loop;
- return hex(1 to hexlen);
- end hstr;
-
-
-
- -- functions to manipulate strings
- -----------------------------------
-
-
- -- convert a character to upper case
-
- function to_upper(c: character) return character is
-
- variable u: character;
-
- begin
-
- case c is
- when 'a' => u := 'A';
- when 'b' => u := 'B';
- when 'c' => u := 'C';
- when 'd' => u := 'D';
- when 'e' => u := 'E';
- when 'f' => u := 'F';
- when 'g' => u := 'G';
- when 'h' => u := 'H';
- when 'i' => u := 'I';
- when 'j' => u := 'J';
- when 'k' => u := 'K';
- when 'l' => u := 'L';
- when 'm' => u := 'M';
- when 'n' => u := 'N';
- when 'o' => u := 'O';
- when 'p' => u := 'P';
- when 'q' => u := 'Q';
- when 'r' => u := 'R';
- when 's' => u := 'S';
- when 't' => u := 'T';
- when 'u' => u := 'U';
- when 'v' => u := 'V';
- when 'w' => u := 'W';
- when 'x' => u := 'X';
- when 'y' => u := 'Y';
- when 'z' => u := 'Z';
- when others => u := c;
- end case;
-
- return u;
-
- end to_upper;
-
-
- -- convert a character to lower case
-
- function to_lower(c: character) return character is
-
- variable l: character;
-
- begin
-
- case c is
- when 'A' => l := 'a';
- when 'B' => l := 'b';
- when 'C' => l := 'c';
- when 'D' => l := 'd';
- when 'E' => l := 'e';
- when 'F' => l := 'f';
- when 'G' => l := 'g';
- when 'H' => l := 'h';
- when 'I' => l := 'i';
- when 'J' => l := 'j';
- when 'K' => l := 'k';
- when 'L' => l := 'l';
- when 'M' => l := 'm';
- when 'N' => l := 'n';
- when 'O' => l := 'o';
- when 'P' => l := 'p';
- when 'Q' => l := 'q';
- when 'R' => l := 'r';
- when 'S' => l := 's';
- when 'T' => l := 't';
- when 'U' => l := 'u';
- when 'V' => l := 'v';
- when 'W' => l := 'w';
- when 'X' => l := 'x';
- when 'Y' => l := 'y';
- when 'Z' => l := 'z';
- when others => l := c;
- end case;
-
- return l;
-
- end to_lower;
-
-
-
- -- convert a string to upper case
-
- function to_upper(s: string) return string is
-
- variable uppercase: string (s'range);
-
- begin
-
- for i in s'range loop
- uppercase(i):= to_upper(s(i));
- end loop;
- return uppercase;
-
- end to_upper;
-
-
-
- -- convert a string to lower case
-
- function to_lower(s: string) return string is
-
- variable lowercase: string (s'range);
-
- begin
-
- for i in s'range loop
- lowercase(i):= to_lower(s(i));
- end loop;
- return lowercase;
-
- end to_lower;
-
-
-
--- functions to convert strings into other types
-
-
--- converts a character into a std_logic
-
-function to_std_logic(c: character) return std_logic is
- variable sl: std_logic;
- begin
- case c is
- when 'U' =>
- sl := 'U';
- when 'X' =>
- sl := 'X';
- when '0' =>
- sl := '0';
- when '1' =>
- sl := '1';
- when 'Z' =>
- sl := 'Z';
- when 'W' =>
- sl := 'W';
- when 'L' =>
- sl := 'L';
- when 'H' =>
- sl := 'H';
- when '-' =>
- sl := '-';
- when others =>
- sl := 'X';
- end case;
- return sl;
- end to_std_logic;
-
-
--- converts a string into std_logic_vector
-
-function to_std_logic_vector(s: string) return std_logic_vector is
- variable slv: std_logic_vector(s'high-s'low downto 0);
- variable k: integer;
-begin
- k := s'high-s'low;
- for i in s'range loop
- slv(k) := to_std_logic(s(i));
- k := k - 1;
- end loop;
- return slv;
-end to_std_logic_vector;
-
-
-
-
-
-
-----------------
--- file I/O --
-----------------
-
-
-
--- read variable length string from input file
-
-procedure str_read(file in_file: TEXT;
- res_string: out string) is
-
- variable l: line;
- variable c: character;
- variable is_string: boolean;
-
- begin
-
- readline(in_file, l);
- -- clear the contents of the result string
- for i in res_string'range loop
- res_string(i) := ' ';
- end loop;
- -- read all characters of the line, up to the length
- -- of the results string
- for i in res_string'range loop
- read(l, c, is_string);
- res_string(i) := c;
- if not is_string then -- found end of line
- exit;
- end if;
- end loop;
-
-end str_read;
-
-
--- print string to a file
-procedure print(file out_file: TEXT;
- new_string: in string) is
-
- variable l: line;
-
- begin
-
- write(l, new_string);
- writeline(out_file, l);
-
-end print;
-
-
--- print character to a file and start new line
-procedure print(file out_file: TEXT;
- char: in character) is
-
- variable l: line;
-
- begin
-
- write(l, char);
- writeline(out_file, l);
-
-end print;
-
-
-
--- appends contents of a string to a file until line feed occurs
--- (LF is considered to be the end of the string)
-
-procedure str_write(file out_file: TEXT;
- new_string: in string) is
- begin
-
- for i in new_string'range loop
- print(out_file, new_string(i));
- if new_string(i) = LF then -- end of string
- exit;
- end if;
- end loop;
-
-end str_write;
-
-
-
-
-end txt_util;
-
-
-
-
diff --git a/zpu/hdl/zpu3/src/xilinx_dualport.vhd b/zpu/hdl/zpu3/src/xilinx_dualport.vhd deleted file mode 100644 index 0e6edc9..0000000 --- a/zpu/hdl/zpu3/src/xilinx_dualport.vhd +++ /dev/null @@ -1,1482 +0,0 @@ ---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 11:47:36 03/22/05
--- Design Name:
--- Module Name: mem_sys - behave
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
-library UNISIM;
-use UNISIM.VComponents.all;
-library zylin;
-use zylin.zpu_config.all;
-
-entity dualport_ram is
-port (clk : in std_logic;
- memAWriteEnable : in std_logic;
- memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
- memAWrite : in std_logic_vector(wordSize-1 downto 0);
- memARead : out std_logic_vector(wordSize-1 downto 0);
- memBWriteEnable : in std_logic;
- memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
- memBWrite : in std_logic_vector(wordSize-1 downto 0);
- memBRead : out std_logic_vector(wordSize-1 downto 0));
-end dualport_ram;
-
-architecture dualport_ram_arch of dualport_ram is
-
-
-signal low : std_logic;
-signal high : std_logic;
-signal re : std_logic;
-
-begin
-
- high <= '1';
- low <= '0';
- re <= '1';
-
-
- ZPU_RAM0 : RAMB16_S2_S2
- generic map (
- INIT_A => X"0", -- Value of output RAM registers on Port A at startup
- INIT_B => X"0", -- Value of output RAM registers on Port B at startup
- SRVAL_A => X"0", -- Port A ouput value upon SSR assertion
- SRVAL_B => X"0", -- Port B ouput value upon SSR assertion
- WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
- WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
- SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
- INIT_00 => X"01A100E100010001003600770002006D000F0000000F06AD000302940008003C",
- INIT_01 => X"7D4000000741F68100C800030000377935990003000300030003002A00150001",
- INIT_02 => X"0007584101010C3D55555555370000000092800000001490000000066A594EBB",
- INIT_03 => X"0009015555932D564C093A4024055555564CB555593C1569EA90C00000007000",
- INIT_04 => X"BF8AA55961BE2A956586C40A4CB00932C00024A80000024C9569C893C0024E90",
- INIT_05 => X"18A1251E2A956586F8AA55961BF8AA55961BE2A956586FE2A956586F8AA55961",
- INIT_06 => X"51349D53764E258A2043E21BE5645DE5C4FC00E0100430C140E4665595558750",
- INIT_07 => X"47B1656A855555D435575A815D077558E475559E755715A1C364945042425555",
- INIT_08 => X"5555F123348C17657C405070D5E745A518B58DD5555F55551D5506F00D707B15",
- INIT_09 => X"C141C74DD5137120D51C0715094CC4F01006A8131DD91531B913118944815155",
- INIT_0A => X"5E559655003D3549550D458C5994A04D476568D05B0F45451D143E53D0F2CD6B",
- INIT_0B => X"4D1E1C5D3474C5C5A1E1C5D34787171C44DC7844D3451D37974D164DD55DD555",
- INIT_0C => X"2074532E4C3A5074DE129D074D1137134477D546C01D374DD348774DE15D3717",
- INIT_0D => X"875650117671948CB05545A5A2615074889149341D04D4956F843575543E1A19",
- INIT_0E => X"F804036D9753106651D5140E6905C158D8979404C7459123540DD9955A43F563",
- INIT_0F => X"7958D037C3557056405549520F96E88622775767141BA3755D1418E1BE234480",
- INIT_10 => X"294A1C405ACCC3705D5599D55037776149584D8F98F98F98FDD00D904D205421",
- INIT_11 => X"74710D5C26798346751441DD555BE179544D8F98F98F98FDD00D910DC3D357C3",
- INIT_12 => X"605D5570051840119D04C0DC3755B61D7951D9A9522D995D51D5BB106B90F7C0",
- INIT_13 => X"D81BC3646611D695A02D1A9419695D695422C40110C0F85D6F899E4D0D555BC3",
- INIT_14 => X"28531104D5F01EDD204141807555735D38346423303676407555545F6B945696",
- INIT_15 => X"5212D7645155503146685C599546660676E81041C85D570DCE1B07116F116021",
- INIT_16 => X"5F9D03530F840406A5725910604E420D910DD521D6170F9AF0F940D91836445D",
- INIT_17 => X"83E03E03C03414D5D5F5D9BE7550DD55775514A145E5405657024C3664F3059C",
- INIT_18 => X"444C7584143756C431049D594DC444FD19CE181427555124440155503F58E14D",
- INIT_19 => X"D54521B201810644D895159C568F40C6C85503E135203FCF555151102C7343CC",
- INIT_1A => X"5A95904431351D93820C4D1AA2C7FD0CD95555311185802971639A1755607515",
- INIT_1B => X"E7D41815C826057201815C826057201815C806057209815C82741C75D1BF4336",
- INIT_1C => X"41BD443664E14155000C4191440445305B46A8D40443A3E115495503116861C3",
- INIT_1D => X"A1520F9C10F850FC18DB80D4777F1D5757195241D35F9754D755DD35F40D9D99",
- INIT_1E => X"65E6A10F206870F0557411545536F0D5FA1765C8D5443E658956E52727558D14",
- INIT_1F => X"DDD2151D31A956A0400F03FC754175510FD4A34252E0DC4076A5EC66A10FB312",
- INIT_20 => X"77C1676610FBD310C3C3CC76F05C9FF20755DC17ECE5451D3472D9D215D34C40",
- INIT_21 => X"55556189C508B6C3F0F0FF1D9F4561676610F207A5EF52D7957CC0F8800F7726",
- INIT_22 => X"8890203480C224080B251D4352F126920C8CF13E00C15A16445A44DA4F105554",
- INIT_23 => X"0F203CF4495240B82923890203080E20B8809249524080C2C0B490210C803203",
- INIT_24 => X"854F25C74C20400C1030000B24838A6F858A08E24080F2823890203C80D203C8",
- INIT_25 => X"00000C000000001F75D5D74FC0000000000000003FFFFFFFEAAA95438104DA47",
- INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_28 => X"0000000000000000000000000000000000000000000154000000000000000000",
- INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000",
- INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
- port map (
- DOA => memARead(1 downto 0), -- Port A 2-bit Data Output
- DOB => memBRead(1 downto 0), -- Port B 2-bit Data Output
- ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input
- ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input
- CLKA => clk, -- Port A Clock
- CLKB => clk, -- Port B Clock
- DIA => memAWrite(1 downto 0), -- Port A 2-bit Data Input
- DIB => memBWrite(1 downto 0), -- Port B 2-bit Data Input
- ENA => re, -- Port A RAM Enable Input
- ENB => high, -- PortB RAM Enable Input
- SSRA => low, -- Port A Synchronous Set/Reset Input
- SSRB => low, -- Port B Synchronous Set/Reset Input
- WEA => low, -- Port A Write Enable Input
- WEB => memBWriteEnable -- Port B Write Enable Input
- );
- ZPU_RAM1 : RAMB16_S2_S2
- generic map (
- INIT_A => X"0", -- Value of output RAM registers on Port A at startup
- INIT_B => X"0", -- Value of output RAM registers on Port B at startup
- SRVAL_A => X"0", -- Port A ouput value upon SSR assertion
- SRVAL_B => X"0", -- Port B ouput value upon SSR assertion
- WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
- WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
- SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
- INIT_00 => X"01510111000100020061006B0000004000100002001005510001059A00360064",
- INIT_01 => X"40300000064005640380001E0001543802180002000200010002000500110005",
- INIT_02 => X"000653709D19C24E555555552400000000920000000024000000000162843876",
- INIT_03 => X"0000CC55555DC1557EC5DC00033155555577055555D315607655000000007000",
- INIT_04 => X"74818211417206084505C705770000F940000398000001765560745D30017700",
- INIT_05 => X"165081C206084505C8182114174818211417206084505D206084505C81821141",
- INIT_06 => X"51200592163801450816D095E0044564ADB5C58C82606080118051A1162881C8",
- INIT_07 => X"550175554516163566505D44014118AA4818516C185014519662131830201616",
- INIT_08 => X"96140906D01981608AF43685992015DA5245D45628675859062835B511755017",
- INIT_09 => X"6000B8F861B22CE39C0EC602ED202FC596B59458405845C55118595694001162",
- INIT_0A => X"55A58300016D31668D5941040556516111611710005B4D4545716E190280595B",
- INIT_0B => X"C968C00BA5BE80B2C68C00B65A3002C1BC8BA32CBE70C3EA02C9CAC89C59458A",
- INIT_0C => X"0B1A0D6164EC408F8A047008D9CB622E2D19546CB32362C8BE8312FACC4BA202",
- INIT_0D => X"4455CCCC1601143B2E45916976DC147401104104059F14685B456418596D1171",
- INIT_0E => X"B4B55655D7453C5DA01654441070416015693378C475DC495A0458256156D15F",
- INIT_0F => X"468751645665865943F040105B8164446641416011165018A11454D15D007415",
- INIT_10 => X"8175134656FB96434615446289641B554684057595597595D066598611165695",
- INIT_11 => X"18A6599B55F856501AD764059656556684017495497495C066598559C91D555D",
- INIT_12 => X"5346166005EB404406411356518A35554684656685DD4686446112185F85B684",
- INIT_13 => X"D555D6601585546854151468D5568546895EB4044115B4595F454E12599655D6",
- INIT_14 => X"335D511B5557C55D467C504218A4E119C7135101456604AE1A05A1555F861668",
- INIT_15 => X"91101161116169E0F5D448156855955595171C7110462859E41D55815FD556C1",
- INIT_16 => X"153011465B440F059A495550560474598A50591544045B8105B8459841662905",
- INIT_17 => X"16E16C16C16514546104654E051C0615418A9450651A1155A1B165662D1D417D",
- INIT_18 => X"700111F690095D6159A445904D270024D7D3C3B711855915976D62896C56D165",
- INIT_19 => X"62A10F7C5B0C0557D468857E5149D00170C316D15CCD6EC558AD0441D72116D2",
- INIT_1A => X"97681F4400824581000023D4516DE3E2517161920D8D38057557861185921514",
- INIT_1B => X"E152154484F551212D544846551210954484D551212154484515A45C3B78F895",
- INIT_1C => X"457E256626804961925697473A0E2C44D0F51470F47849C431468400D048CD56",
- INIT_1D => X"51105B8C05B445B315555C05417946285153C440619C2166018A4619C8598151",
- INIT_1E => X"4595955BA2EA0761584405655975B59920519556E9056E0566859A4581645C14",
- INIT_1F => X"9055965A909455530D5B16F1185118A55B15520D55159076C55AF455155B50B6",
- INIT_20 => X"8085515155B6E90616D6E0146830806841851156724A0EC620DD04559653A415",
- INIT_21 => X"75858C001F40514145B5B40507C305515155BA2D93E496D5695545B4605B9418",
- INIT_22 => X"0810203080F20408032DA18003C200E266D1C15050400CF788038803844E58A1",
- INIT_23 => X"0F203CCF4CF040B12103010203480F208C80A24CF04080D0C03C1023BC82F203",
- INIT_24 => X"0600F6CFD04155043040000C38832340070840C04080F2103010203C803203C8",
- INIT_25 => X"0A000C00000020061C7185CFEAAAAAAAAAAAAAAA95555555555555540B080387",
- INIT_26 => X"0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A",
- INIT_27 => X"313A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A",
- INIT_28 => X"00000000000000000000000000000000000000000001F0000000000000030000",
- INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000",
- INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
- port map (
- DOA => memARead(3 downto 2), -- Port A 2-bit Data Output
- DOB => memBRead(3 downto 2), -- Port B 2-bit Data Output
- ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input
- ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input
- CLKA => clk, -- Port A Clock
- CLKB => clk, -- Port B Clock
- DIA => memAWrite(3 downto 2), -- Port A 2-bit Data Input
- DIB => memBWrite(3 downto 2), -- Port B 2-bit Data Input
- ENA => re, -- Port A RAM Enable Input
- ENB => high, -- PortB RAM Enable Input
- SSRA => low, -- Port A Synchronous Set/Reset Input
- SSRB => low, -- Port B Synchronous Set/Reset Input
- WEA => memAWriteEnable, -- Port A Write Enable Input
- WEB => memBWriteEnable -- Port B Write Enable Input
- );
- ZPU_RAM2 : RAMB16_S2_S2
- generic map (
- INIT_A => X"0", -- Value of output RAM registers on Port A at startup
- INIT_B => X"0", -- Value of output RAM registers on Port B at startup
- SRVAL_A => X"0", -- Port A ouput value upon SSR assertion
- SRVAL_B => X"0", -- Port B ouput value upon SSR assertion
- WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
- WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
- SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
- INIT_00 => X"0008000800000000000000010001002A000200000002000800000080000800C6",
- INIT_01 => X"023AAAAAA028A040002A0000000002B000000000000000000000000000080000",
- INIT_02 => X"AAA00B000020000C0000000002AAAAAAAA082AAAAAAA828AAAAAAAA008223032",
- INIT_03 => X"AAA8CC000000E0000CC00E2AA33000000003800000030008300C2AAAAAAA3AAA",
- INIT_04 => X"3C2828002830A0A000A0C020038AA8F02AAAA302AAAAA8000008300032A8038A",
- INIT_05 => X"820800C0A0A000A0C282800283C2828002830A0A000A0F0A0A000A0C28280028",
- INIT_06 => X"00000C00303000208600C841C0008C028AB00806C170000010000C0080002A30",
- INIT_07 => X"8AB83808200000C000020C2000023002A830001E300380080002A00230100000",
- INIT_08 => X"0000C00C00322300330800E0008020C088C0E280000B0003CC0020F08038AB83",
- INIT_09 => X"40001DA0C0200401080400000CD880A23C00C23008C00A3B20303010102C8000",
- INIT_0A => X"0000002AEC0C70000A0093220A8008C0230028EE00032A008CA00C230004F00B",
- INIT_0B => X"9030420240C820130704202C1C108041C900C10A2CD04E0C00B34C80380E4000",
- INIT_0C => X"8E32028C080030DA0244070DA342C0BC26AA40880A36C0A020D1008304020040",
- INIT_0D => X"20A0303230280000AC0020A828028A20220000000C2080000B200030000C82C2",
- INIT_0E => X"323200204380C300000080880B80A80B83008D037820E3A00008C0400000C203",
- INIT_0F => X"00004800400008012C2000000300820808A323008D800A30008083C81C801000",
- INIT_10 => X"8030808000C0002F8C0008C0000230000002200882883881C8CB0002FA000000",
- INIT_11 => X"3080000A8030002A3220A08C0002800002200882883881C8CB000200C1200170",
- INIT_12 => X"2F8C000AB0282A0A8CAFA006230000040008C8300080100408C08A820B003028",
- INIT_13 => X"0002C0020208400002C8C1020800040002C282A0A800320003203C02000000C0",
- INIT_14 => X"28002208005C2A840002A08A3009090828820E0900000A823200200507004300",
- INIT_15 => X"0880A3000000020F00420E030000A080A0208208828C00000821810007080322",
- INIT_16 => X"85002D080320300040088382000800000008C080E0AA0300E030A0000000008C",
- INIT_17 => X"80C00C00C0010088C088C83C00028C002300800820000200013834000010B03C",
- INIT_18 => X"0A20108A00290E4080038C088C00A20081C12810A30000E0A0A000000C02C804",
- INIT_19 => X"C000020C0223C020C300000C002300C20882C0C813280FEF0008C0A8280900C0",
- INIT_1A => X"8200000030428C0E008C100108E0CC084020000ABA882800380702E300026028",
- INIT_1B => X"C0CE4280A240A02890280A240A02890280A200A02880280A2230228824330210",
- INIT_1C => X"081C8000008000008C00C204DC280368800042CE0002C1C0A0000383A00E0280",
- INIT_1D => X"0880030E803200308281822223088C00020082C0C08C630003008C08CA000000",
- INIT_1E => X"00206003248C882E00238008023030008EB33021D0D00C002020400323020E80",
- INIT_1F => X"08CA008A00888008AE0300F230223002030008AE02A00808A040812060030823",
- INIT_20 => X"88B0060A0032E00880C0C8322821A22AA3020D83B00D808C182E28CA00878020",
- INIT_21 => X"20000C003280A28E2030320C8B8220060A003248C6EA80C3003820302403026A",
- INIT_22 => X"C2BA0AAC2AA0AE82A93AAEABA2A0B110EAAFA3EFEE8ABBAAC2C442444F300000",
- INIT_23 => X"A90AA4BABAAAE82F04946BA0AAC2AA0AC82AE0BAAAE82AB24E5ABA09E42B90AA",
- INIT_24 => X"AA8FAAAAACFBBEE8BED8AAA9EC0AEEBECAC1251AE82A905946BA0AA42AA0AA42",
- INIT_25 => X"FAA00C000000700562A2FC8FC00000000000000000000000000000000E02C44E",
- INIT_26 => X"FAA5500FFAA5500FFAA5500FFAA5500FFAA5500FFAA5500FFAA5500FFAA5500F",
- INIT_27 => X"0D25500FFAA5500FFAA5500FFAA5500FFAA5500FFAA5500FFAA5500FFAA5500F",
- INIT_28 => X"0000000000000000000000000000000000000000000080000000000000020000",
- INIT_29 => X"00000000000000000CF000000000000000000000000000000000000000000000",
- INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
- port map (
- DOA => memARead(5 downto 4), -- Port A 2-bit Data Output
- DOB => memBRead(5 downto 4), -- Port B 2-bit Data Output
- ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input
- ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input
- CLKA => clk, -- Port A Clock
- CLKB => clk, -- Port B Clock
- DIA => memAWrite(5 downto 4), -- Port A 2-bit Data Input
- DIB => memBWrite(5 downto 4), -- Port B 2-bit Data Input
- ENA => re, -- Port A RAM Enable Input
- ENB => high, -- PortB RAM Enable Input
- SSRA => low, -- Port A Synchronous Set/Reset Input
- SSRB => low, -- Port B Synchronous Set/Reset Input
- WEA => memAWriteEnable, -- Port A Write Enable Input
- WEB => memBWriteEnable -- Port B Write Enable Input
- );
- ZPU_RAM3 : RAMB16_S2_S2
- generic map (
- INIT_A => X"0", -- Value of output RAM registers on Port A at startup
- INIT_B => X"0", -- Value of output RAM registers on Port B at startup
- SRVAL_A => X"0", -- Port A ouput value upon SSR assertion
- SRVAL_B => X"0", -- Port B ouput value upon SSR assertion
- WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
- WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
- SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
- INIT_00 => X"00040044000000020008000200020115000500020005000400020000000C0089",
- INIT_01 => X"2975555550165082031500000000017218820002000200020002002000040000",
- INIT_02 => X"5550070B0150281C000000008155555555849555555561555555555404117230",
- INIT_03 => X"5555EE000000D8000CE00D9557B8000000036000000B80053000555555553555",
- INIT_04 => X"31141484143450521050E090036555F0955557015555540000053200B9540365",
- INIT_05 => X"4305181450521050D1414841431141484143450521050C450521050D14148414",
- INIT_06 => X"088A0C0830B088305988C583C9824C914136660AEABA8A2AAA2A08084081160A",
- INIT_07 => X"1544300C14808010800A0C1694A932055632082D3208420448095991A8684080",
- INIT_08 => X"008210800A02130B030A8092006990C04620C540821702028C8290F568315443",
- INIT_09 => X"9AB92A20C8084AAB01A820AB082640D53AA081A164C265B750A1702032124808",
- INIT_0A => X"08016955148DF82021207E5595420685930996D9952351204C588C926A2FC00B",
- INIT_0B => X"20E9A590C3A2192A9E9A590C3A6964A7A312A6830CEBA08A6433AA21310CA020",
- INIT_0C => X"6E31A15036890AA312FD78AA33A084ACBE61820106E8843108A6A4229A90C4A4",
- INIT_0D => X"11510AC9309402005C20185021614512190A28A28CF042020F108232008C45C4",
- INIT_0E => X"31214814832100080940422454855404420142448520CC9E00A4C2C40808D90B",
- INIT_0F => X"20268482C800150257062188232541244453130942420532044203C43C593612",
- INIT_10 => X"7830466802C008134C8064C8208132082025942102102103D4C6202525980008",
- INIT_11 => X"3241200540B2481531105A4C0002082025942102102103D4C6202520FB5002B0",
- INIT_12 => X"134C801D711635AD4C525809932060882024C4202648202924C855430F223516",
- INIT_13 => X"8282C80B91A8820265040201042028202691635AD44231040B103C99200003C8",
- INIT_14 => X"9600999400AC154C98015A653207468C14C808871080914131A01A0A0F24C301",
- INIT_15 => X"044853098808030C00C111820210C16080C44104654C8220949E86A80B240B19",
- INIT_16 => X"4B46A224231280A0801E421B0AA401202064C048D1552324123252026480814C",
- INIT_17 => X"48E88E88E8828204C864C42C90814C8053204205108099080A743C809070883D",
- INIT_18 => X"0596A8858AA60CAA58004C066C60594203DB16B053201012505808208D03C468",
- INIT_19 => X"C818807D4458A0C2C202603D081702E6862888C460988FDF02089AD4164688C6",
- INIT_1A => X"420200A2B99B4C29286E640205F1CC088844081F49601684300F25132009D084",
- INIT_1B => X"C9C2831215A0C4856831215A0C4856831215A0C485683121593251515C730222",
- INIT_1C => X"203D4080904A20086864E4682C918096010081C30A0292C6442020EBD9160148",
- INIT_1D => X"0548232D623112344203115113204C82084015E8C94D930063204C94D5202448",
- INIT_1E => X"1080842348196501021064050170B2005553108554208C902010C06313012D42",
- INIT_1F => X"04C500542A464205692388F93219320523420569084206041080560084234606",
- INIT_20 => X"660408084234C2A548C8D63106851905632142433C9D654C965D54C5005B0A92",
- INIT_21 => X"00201E21706259615232358C576854080842348195C541C3003112361A235591",
- INIT_22 => X"005000100050140005055541515105505555514554414515441544554002020A",
- INIT_23 => X"0500145455514015051545000140050014001055514000514054500114005001",
- INIT_24 => X"4545554554515544005000055401555541414551400050515450001400500140",
- INIT_25 => X"FFF00C000000501394E93A4FC000000000000000000000000000000005041545",
- INIT_26 => X"FFFFFFFAAAAAAAA5555555500000000FFFFFFFFAAAAAAAA5555555500000000F",
- INIT_27 => X"093FFFFAAAAAAAA5555555500000000FFFFFFFFAAAAAAAA5555555500000000F",
- INIT_28 => X"0000000000000000000000000000000000000000000070000000000000000000",
- INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000",
- INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
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- port map (
- DOA => memARead(7 downto 6), -- Port A 2-bit Data Output
- DOB => memBRead(7 downto 6), -- Port B 2-bit Data Output
- ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input
- ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input
- CLKA => clk, -- Port A Clock
- CLKB => clk, -- Port B Clock
- DIA => memAWrite(7 downto 6), -- Port A 2-bit Data Input
- DIB => memBWrite(7 downto 6), -- Port B 2-bit Data Input
- ENA => re, -- Port A RAM Enable Input
- ENB => high, -- PortB RAM Enable Input
- SSRA => low, -- Port A Synchronous Set/Reset Input
- SSRB => low, -- Port B Synchronous Set/Reset Input
- WEA => memAWriteEnable, -- Port A Write Enable Input
- WEB => memBWriteEnable -- Port B Write Enable Input
- );
- ZPU_RAM4 : RAMB16_S2_S2
- generic map (
- INIT_A => X"0", -- Value of output RAM registers on Port A at startup
- INIT_B => X"0", -- Value of output RAM registers on Port B at startup
- SRVAL_A => X"0", -- Port A ouput value upon SSR assertion
- SRVAL_B => X"0", -- Port B ouput value upon SSR assertion
- WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
- WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
- SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
- INIT_00 => X"02550195000200030077007600030359001E0003001C09DD000307EA00000064",
- INIT_01 => X"706555555755A365027600130001222837780003000300030003001600120005",
- INIT_02 => X"555709831042087800000000D355555554DA5555555536355555554D5AA46DF7",
- INIT_03 => X"5541AA00002A2800AC82A25506A8000000A8A00002A200018329555555559555",
- INIT_04 => X"A6956586F8AA55961BE2AAACA89541B85555060D555554AAC001822A2154A895",
- INIT_05 => X"15564C3A55961BE2A956586F8A6956586F8AA55961BE29A55961BE2A956586F8",
- INIT_06 => X"C4DD0F9C3E254D554C5A94D4A3500F07C1D00B5C330CF3C3F3CC5544DD52494A",
- INIT_07 => X"E1B5D755571D97818E76755CE71835646436755036461D5558E13248A5555D99",
- INIT_08 => X"DD953042010B03E0024CD486B931E7579D27491D5550765A0D55154409D21B5D",
- INIT_09 => X"4424F150D91D3714CDB070020425D4601515551100F8018994D19555114041D5",
- INIT_0A => X"75543554959F55D556679190489D554403E0072C4060DE140F41BA11D6E44451",
- INIT_0B => X"6845704D611544DC545704D5111C1371144C1DC79E5C71E113697174D0747754",
- INIT_0C => X"38344823553107174E413471697193C477905D84C7455344DE19D378574D9313",
- INIT_0D => X"55DD48483E1B310505675CCD58860351454104100F441D5552558C3655B95098",
- INIT_0E => X"65111AF8DD1AD055541D1D54F08F41D115509285CE0754B47450F82DDB5B6556",
- INIT_0F => X"D550499F18E4B076DA4214846A8499649843C3E382555435685D9495496C3106",
- INIT_10 => X"4DD55C3555001BD40D9110D5558C3701D5515951951D5114D0D2678221658145",
- INIT_11 => X"340D6B9445289AC434711C0F9F15CDD5515951951D5114D0D2678267C4950175",
- INIT_12 => X"F40D912D604235CD0D221D444356E005D550D1555381555500D97D875686A420",
- INIT_13 => X"80549BE357DF5D553D7DD55A1DD555D557D4336CD746A5475E5D6A216391175A",
- INIT_14 => X"010501F5405D40C8D5940C1435580D3849CE5740B18E1910340745C556881D5B",
- INIT_15 => X"9B4603E049D9C0084555521555D5710555774D34040D536B8421F9D453441141",
- INIT_16 => X"041175106E554455555F9551036500638510F943D169668356285678818E340F",
- INIT_17 => X"D8F98F98F98FDD00D920DD6A08440D9103545D563755637555C621AE0505C164",
- INIT_18 => X"1157D3918169757BC8590F9710611503950440C103644653210DD555BE179544",
- INIT_19 => X"D54C433594B0854455550145755140154527D89514BD8B95754C1CD64F0D1906",
- INIT_1A => X"5551405045830F8D75D16D155464110C4D99D918486C8049DD528503667CD750",
- INIT_1B => X"A3429553102554C409553102554C409553102554C4095531003C972139044313",
- INIT_1C => X"D151519E005111D94414170D204D0484CA4555500503216C59D5301C3526441B",
- INIT_1D => X"57046685066556A495D5DD4103D10D51773591C0DE4C83E503570DE4CD6B889D",
- INIT_1E => X"1775776F4CCF97A4766261D877D536396DC347407021AA255525558D03E7055D",
- INIT_1F => X"30F31DBD15BBDD56706F9BF83648357C6F5D547377B6FD0855545F35776F3A33",
- INIT_20 => X"8837575776B0C15859D9843C816FE39A4366411D28401C0D41F3E0FB1D9F4566",
- INIT_21 => X"07670D146590C32F1676610FF31267545776B40CCCCFC89D59D5A6E8DC6F2CDF",
- INIT_22 => X"CC30300C00300C000C320499A95208E1C4535A2755E92DCB882389238A427556",
- INIT_23 => X"000002951C50C080313003030BC02D003400811C50C002CB87E43003F803E300",
- INIT_24 => X"5841550C544F955C0740000C380831B1C14C8C00C0C023330030300800D00000",
- INIT_25 => X"FFF00C000000F01400FFEAB3C0000000000000003FFFFFFFEAAA9543850823A8",
- INIT_26 => X"555555555555555555555555555555500000000000000000000000000000000F",
- INIT_27 => X"3A3FFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA5",
- INIT_28 => X"00000000000000000000000000000000000000000000B0000000000000020000",
- INIT_29 => X"00000000000000000CE000000000000000000000000000000000000000000000",
- INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
- port map (
- DOA => memARead(9 downto 8), -- Port A 2-bit Data Output
- DOB => memBRead(9 downto 8), -- Port B 2-bit Data Output
- ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input
- ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input
- CLKA => clk, -- Port A Clock
- CLKB => clk, -- Port B Clock
- DIA => memAWrite(9 downto 8), -- Port A 2-bit Data Input
- DIB => memBWrite(9 downto 8), -- Port B 2-bit Data Input
- ENA => re, -- Port A RAM Enable Input
- ENB => high, -- PortB RAM Enable Input
- SSRA => low, -- Port A Synchronous Set/Reset Input
- SSRB => low, -- Port B Synchronous Set/Reset Input
- WEA => memAWriteEnable, -- Port A Write Enable Input
- WEB => memBWriteEnable -- Port B Write Enable Input
- );
- ZPU_RAM5 : RAMB16_S2_S2
- generic map (
- INIT_A => X"0", -- Value of output RAM registers on Port A at startup
- INIT_B => X"0", -- Value of output RAM registers on Port B at startup
- SRVAL_A => X"0", -- Port A ouput value upon SSR assertion
- SRVAL_B => X"0", -- Port B ouput value upon SSR assertion
- WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
- WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
- SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
- INIT_00 => X"0028016800040002006B00A40002002500150002001500200002078500620060",
- INIT_01 => X"090555555A16501F0555001E00011554543400020002000200020008001C0004",
- INIT_02 => X"555A082282D08E55000000009355555555841555555561455555555058510938",
- INIT_03 => X"5564320000C598030D3C595590C80000031660000C58C0246FC1555555550555",
- INIT_04 => X"12084505C8182114172040DF165564345555903D55555715C0246FC58D571655",
- INIT_05 => X"96296A48211417206084505C81A084505C8182114172058211417206084505C8",
- INIT_06 => X"E18B5B896D1CD962A7546A5450CF5B71580861C4E138618E91B8586205916041",
- INIT_07 => X"17146758A54584656E0B18A04CF16646C1660945661A862854D183703F0F0588",
- INIT_08 => X"0582C0F063C156D030459915F861A18480718705961516185996751FBC617146",
- INIT_09 => X"378E9CA59823E272012C64BB400C144101558A49B5B4BD50710945615F380059",
- INIT_0A => X"1852855419554461645F509EE3462926D6D2F546F1595CCC5B756511B2343155",
- INIT_0B => X"B7702AFAD5CB6C8B1702AFAD9C0AB629CBD9C4BA28082E8CBEA02C8E801A1166",
- INIT_0C => X"0166AC531C4502C8D941902C80263E735D40066BA5723A8DA8CCBEA322DAFEBE",
- INIT_0D => X"A01240416D1107E5A19151016694527B3730C30C5B44061651A15D6601668510",
- INIT_0E => X"DA01D4D9861C12585D05065D2811A8519615D0104661940514C5B41453955451",
- INIT_0F => X"6168095D15E114149C58BE2F5542950D5956D6D080162966440614694692E3C5",
- INIT_10 => X"40628441544996DA5988A599654D643461695D65165D65D45596534A07012D74",
- INIT_11 => X"668D5784B55457D16459CA5B8496B061695D65165D65D4559653465304D4BC14",
- INIT_12 => X"CA5985D59F72958459207121566453606155996169016161A5985D5559451715",
- INIT_13 => X"4D5555D195940616913116116061606165B7295844555A2759A175215B85D555",
- INIT_14 => X"70B417352F056B6A715694656668C4C6756858D0D14D121D66E164A05D440611",
- INIT_15 => X"80ACD6D20058E080458A141616C58D8595B41041C55991577DC058B25D774D57",
- INIT_16 => X"A01F145855A314C58515165132DC89574495B80B0855514715545534054D025B",
- INIT_17 => X"17495497495C066598559D45356659889666462941859D185867416D14046975",
- INIT_18 => X"99524CDD7720192513505B84634995CA1454710996622409D9C0596565546840",
- INIT_19 => X"996DF895A74805A21616894518A86430CC0D5568440545001645484671C4D444",
- INIT_1A => X"561B22C94D195B472D1345162807D10000A4582043DF16F464514116627A61A5",
- INIT_1B => X"5100966998A59A662966998A59A662966998A59A66296699896E9892E1FC400C",
- INIT_1C => X"6545195D1AC85458697806A50148143DF1458A102C00D046646190140D247717",
- INIT_1D => X"280F5144451A15D51616D05456C1599118412815927256E196655927215B4460",
- INIT_1E => X"11858751486456951621685817855578511641A9DF0165016105845C16E02E06",
- INIT_1F => X"35B8051B0CB846294559D7456619664659462A441B75B441C587E5058759A619",
- INIT_20 => X"641759587598E0C15454556E8BAA56A5566140865C12B2596B3255B40507C305",
- INIT_21 => X"C1632BBD073618665515155B50B647595875948676CA8846106405D4D05DA420",
- INIT_22 => X"C030003C40F10C040D284715799040C1155498499FE9FDA30103010304C41658",
- INIT_23 => X"0D1036025D60C0F617D18300080422103440125D60C0420B00C4301190424003",
- INIT_24 => X"D0456C31905419FC4108000C300999F50245F460C000C14D1830003040D10344",
- INIT_25 => X"AAA00C000000002AAA555573EAAAAAAAAAAAAAAA955555555555555407010320",
- INIT_26 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA",
- INIT_27 => X"003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
- INIT_28 => X"0000000000000000000000000000000000000000000060000000000000020000",
- INIT_29 => X"00000000000000000CE000000000000000000000000000000000000000000000",
- INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
- port map (
- DOA => memARead(11 downto 10), -- Port A 2-bit Data Output
- DOB => memBRead(11 downto 10), -- Port B 2-bit Data Output
- ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input
- ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input
- CLKA => clk, -- Port A Clock
- CLKB => clk, -- Port B Clock
- DIA => memAWrite(11 downto 10), -- Port A 2-bit Data Input
- DIB => memBWrite(11 downto 10), -- Port B 2-bit Data Input
- ENA => re, -- Port A RAM Enable Input
- ENB => high, -- PortB RAM Enable Input
- SSRA => low, -- Port A Synchronous Set/Reset Input
- SSRB => low, -- Port B Synchronous Set/Reset Input
- WEA => memAWriteEnable, -- Port A Write Enable Input
- WEB => memBWriteEnable -- Port B Write Enable Input
- );
- ZPU_RAM6 : RAMB16_S2_S2
- generic map (
- INIT_A => X"0", -- Value of output RAM registers on Port A at startup
- INIT_B => X"0", -- Value of output RAM registers on Port B at startup
- SRVAL_A => X"0", -- Port A ouput value upon SSR assertion
- SRVAL_B => X"0", -- Port B ouput value upon SSR assertion
- WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
- WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
- SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
- INIT_00 => X"00000000000000000001000200000000000200000002008800000300000000B0",
- INIT_01 => X"202000000800080A010000000000080202B20000000000000000000200000000",
- INIT_02 => X"0008A20300A00C02AAAAAAAA0B00000000020000000000000000000002002830",
- INIT_03 => X"0000B8AAAAC002AB2CBC000002E2AAAAAB000AAAAC0EEA800FC8000000000000",
- INIT_04 => X"84A000A0C2828002830A22CF000000B00000023C00000300EA800FC0EC030000",
- INIT_05 => X"000003028002830A0A000A0C284A000A0C2828002830A328002830A0A000A0C2",
- INIT_06 => X"3C0003000CA33000040300400B38030004028238020082002600000C8C080000",
- INIT_07 => X"8A08CB00028C0A803C31300EA08000208000200800208C0003C8380232828C02",
- INIT_08 => X"8C000B04881380C8800F0400B03803020093020C000A30280000202224C0A08C",
- INIT_09 => X"003914C000B6C0E02C000003000820C882A00080003200900D800800B802D8C0",
- INIT_0A => X"30003002B808C8C004033000800C020000C802409E0608CE03080080A00C0302",
- INIT_0B => X"C0D00083034C08010D100830340028034CB3403C3000030420C004DA00322302",
- INIT_0C => X"E0002A07384C004DB0C22004D00B6894C2820CAE22D364D8304820C120932820",
- INIT_0D => X"00E002C00C811C0028A3282C08228A2400CB2CB203C08C0000002C0008000200",
- INIT_0E => X"000E80CACC0B80002A0C0C80280088C20008800A22B32C0E30803220CB808800",
- INIT_0F => X"C002283E00C289320830C830042028000200C0C8200000002A8C80000022BC30",
- INIT_10 => X"88C0020880BB82C800080000003C02F8C0000C08408008008002032202088038",
- INIT_11 => X"022C0B02300202C0000020030A00B8C0000C0840800800800203220B08800010",
- INIT_12 => X"C8000A04800A12240020200280022F80C000000001080000200000010020A080",
- INIT_13 => X"BE8081C90A260C0010BA8008A8C000C00100A122401000030C0030880F0A0080",
- INIT_14 => X"0A00822000040020688002080028208008480200401C8A80002302800C200C08",
- INIT_15 => X"00A000C8D8C0C0800000028000E00C20200082082000080B202050200E020802",
- INIT_16 => X"000218020C02208000050088F8834C0F2A20300FB400002380C20072201CA803",
- INIT_17 => X"00882883881C8CB000200C008880000800028C00230002300003203C81004038",
- INIT_18 => X"000008428210320A080A03020820002200880A80000202B92028C00028000022",
- INIT_19 => X"00890210803420210000280A30001020B8C8C200000C1800302F82430A2083B2",
- INIT_1A => X"0000D0B68823032CC0A208000200000C20A8C0E000830008C800228000B06320",
- INIT_1B => X"0820808E8CA023A12808E84A023A12808E84A023A12808E8480C0B8AE0040304",
- INIT_1C => X"C808003C8233A0C00C30080800009008320000000B83A00828C0082808800001",
- INIT_1D => X"00B00820E0C000A08080022200C6000A322860C0083880C000020083800F2028",
- INIT_1E => X"E320230E188022AA300E24C13380203035000332ED0C20800080020E80C03C8C",
- INIT_1F => X"70320C8A08388C003602C18800000022028C00363330F3888002A2E0230A2220",
- INIT_20 => X"2263020230E1E0880182800C92308AAA0000384C8C202300C23220320C8B8220",
- INIT_21 => X"E303800A0100820A0060A003082303020230E18800DAB48C08C8B0E0C80202AA",
- INIT_22 => X"4AAA2AA4AAA2AA8AAB2AEEEAE2A12512CFEFA2FAAA8F2AA2C59444944F803000",
- INIT_23 => X"A32A8CAAABAAA8EF04892AA3AC4AB02AD0AAC2ABAAA8AB12CF7EAA2B4CA932AA",
- INIT_24 => X"AE8EEAAFA8FBFAA8AE94AAAAAC8FABAA8A81224AA8EA305892AA3A8CAAB2A8CA",
- INIT_25 => X"00000C000000100000000033C00000000000000000000000000000000A04944E",
- INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_27 => X"1500000000000000000000000000000000000000000000000000000000000000",
- INIT_28 => X"00000000000000000000000000000000000000000000A0000000000000000000",
- INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000",
- INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
- port map (
- DOA => memARead(13 downto 12), -- Port A 2-bit Data Output
- DOB => memBRead(13 downto 12), -- Port B 2-bit Data Output
- ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input
- ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input
- CLKA => clk, -- Port A Clock
- CLKB => clk, -- Port B Clock
- DIA => memAWrite(13 downto 12), -- Port A 2-bit Data Input
- DIB => memBWrite(13 downto 12), -- Port B 2-bit Data Input
- ENA => re, -- Port A RAM Enable Input
- ENB => high, -- PortB RAM Enable Input
- SSRA => low, -- Port A Synchronous Set/Reset Input
- SSRB => low, -- Port B Synchronous Set/Reset Input
- WEA => memAWriteEnable, -- Port A Write Enable Input
- WEB => memBWriteEnable -- Port B Write Enable Input
- );
- ZPU_RAM7 : RAMB16_S2_S2
- generic map (
- INIT_A => X"0", -- Value of output RAM registers on Port A at startup
- INIT_B => X"0", -- Value of output RAM registers on Port B at startup
- SRVAL_A => X"0", -- Port A ouput value upon SSR assertion
- SRVAL_B => X"0", -- Port B ouput value upon SSR assertion
- WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
- WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
- SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
- INIT_00 => X"028200020002000000020081000001800000000000000A4600000320002A00CA",
- INIT_01 => X"905000000C800680020000080000444101710000000000000000001100000002",
- INIT_02 => X"000C51A6981A9A015555555587000000002140000000081000000006010850B2",
- INIT_03 => X"0001745555E001579D7E000005D15555578005555E0DD5410FE400000000A000",
- INIT_04 => X"4C521050D1414841434519CF80000172000005BC00000380D5410FE0DC038000",
- INIT_05 => X"00800311484143450521050D148521050D1414841434521484143450521050D1",
- INIT_06 => X"B21023208C60000808020082040823582DA15A0A0A828A202A0202024C040620",
- INIT_07 => X"5454C702054C25583CB23201564080111480B02080B14C8202C4451530504C29",
- INIT_08 => X"4C2CD70F843F88C6782C0E40B2442321A663258C008530942000508418C9454C",
- INIT_09 => X"90332AA202A8C4867C420A02E68152956550205C02310276425C64087C4124C0",
- INIT_0A => X"320900014031E4C8090F7980048C817008C409D4390C4DAD23442049465EBE08",
- INIT_0B => X"A6EA40229BAA42128EA40229BA900843AA22A93A69924E9A08A64AA22E319301",
- INIT_0C => X"1080551FB198A8AA21E92A8AA64A88A82A6D8C6B22EA88A329A508A694328808",
- INIT_0D => X"091921E08C46AC38145316580551649C4024924923E24C8008083C80A4202506",
- INIT_0E => X"809103D78C9C4802118C8C50462554C94085486515E31E1D32123198C7831708",
- INIT_0F => X"C805903D82C942314421C0700C1514904108C8C518408080114C42002005E000",
- INIT_10 => X"64C82514423FC3D4202E1200002C8134C8000C048048048202080B1484546834",
- INIT_11 => X"81380F25708102D882181023258074C8000C048048048202080B140BA642AAA2",
- INIT_12 => X"D42025987905A11A208844A948010368C80200080368080812025822081080C0",
- INIT_13 => X"0D4202C615198C803475408494C808C802D05A11A220C0A30C0830540B258202",
- INIT_14 => X"45A24450AAA8001ED44005148016322E0482011A9C2C554C8013056A0C128C84",
- INIT_15 => X"267108C424C2CAA22020854080D02C10102165961120040B501AB6060C09A404",
- INIT_16 => X"2A80668308085210208B405C3410A90B1512326F49010C17408110F1542C5423",
- INIT_17 => X"42102102103D4C6202520C204660202E08014C80932001320243982C52A28031",
- INIT_18 => X"800422C160763185560523251E58003082160568080B914B1814C00020820259",
- INIT_19 => X"00470222620A101A808054213206208A2193C202621C225A301FD1A305320225",
- INIT_1A => X"408028096013231C01580480818028AE6674C292201F5104C60814480A709312",
- INIT_1B => X"05A8405D4A5017529405D4A5017529405D4A5017529405D4A48D445D900A2B99",
- INIT_1C => X"C421882C5F0098C24E6697488A6D6201F520208A80EBD91434C81A9690E40082",
- INIT_1D => X"81700C11108080C14040851988D92005316491C20534C8C808012053440F1254",
- INIT_1E => X"1310130866891415309108C2332080B255482315568030580850212D48C9BC4C",
- INIT_1F => X"B2358C41A1714C810908C22080848011084C81093370B4E690215110130841A2",
- INIT_20 => X"119301013086DA150202108D206544150809068C5E980520407852358C576850",
- INIT_21 => X"D30B40018241451440808423460613010130866895E50E4C84C54086C6085545",
- INIT_22 => X"4410101440510404051545555151455155455154554145554515451540283001",
- INIT_23 => X"0510145455504015151141010144051054405055504040514154101054415101",
- INIT_24 => X"5445551554515554415400041401555541454450404051511410101440510144",
- INIT_25 => X"55500C000000D00000000033C000000000000000000000000000000005051544",
- INIT_26 => X"5555555555555555555555555555555555555555555555555555555555555555",
- INIT_27 => X"1515555555555555555555555555555555555555555555555555555555555555",
- INIT_28 => X"00000000000000000000000000000000000000000000E0000000000000010000",
- INIT_29 => X"00000000000000000CD000000000000000000000000000000000000000000000",
- INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
- port map (
- DOA => memARead(15 downto 14), -- Port A 2-bit Data Output
- DOB => memBRead(15 downto 14), -- Port B 2-bit Data Output
- ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input
- ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input
- CLKA => clk, -- Port A Clock
- CLKB => clk, -- Port B Clock
- DIA => memAWrite(15 downto 14), -- Port A 2-bit Data Input
- DIB => memBWrite(15 downto 14), -- Port B 2-bit Data Input
- ENA => re, -- Port A RAM Enable Input
- ENB => high, -- PortB RAM Enable Input
- SSRA => low, -- Port A Synchronous Set/Reset Input
- SSRB => low, -- Port B Synchronous Set/Reset Input
- WEA => memAWriteEnable, -- Port A Write Enable Input
- WEB => memBWriteEnable -- Port B Write Enable Input
- );
- ZPU_RAM8 : RAMB16_S2_S2
- generic map (
- INIT_A => X"0", -- Value of output RAM registers on Port A at startup
- INIT_B => X"0", -- Value of output RAM registers on Port B at startup
- SRVAL_A => X"0", -- Port A ouput value upon SSR assertion
- SRVAL_B => X"0", -- Port B ouput value upon SSR assertion
- WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
- WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
- SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
- INIT_00 => X"015502550005000300F6005200030357002A0003002A066500030BDD001C000F",
- INIT_01 => X"793000000D4EC7C70123002F0001191522250003000300030003003D00060009",
- INIT_02 => X"000D601010C040A555555554DA00000001DCC000000077600000001645953DFD",
- INIT_03 => X"0024C9555693855A7CB92A00932555555A4E15556932D564899E00000000A000",
- INIT_04 => X"5D961BE2A956586F8AA567064E0024F0000093A4000002405564CB932C024A80",
- INIT_05 => X"5D510E56586F8AA55961BE2A955961BE2A956586F8AA566586F8AA55961BE2A9",
- INIT_06 => X"A2CD6E8D995445D50415505D54486DAC86F2014401004100D90F76420F951317",
- INIT_07 => X"1510D0756C0F85016A08356D69D1AE7545BE09D1BE090D551595211564540F86",
- INIT_08 => X"0F805644C511DB9595044165E874C364C783450F96543E146F9B074370D9510D",
- INIT_09 => X"D0059716B8C5137DC0372001534D13641227546416A51443126409D9590120F9",
- INIT_0A => X"36560854A95A40D9CF52944C950D51909A94912C5C5517E569C5555639E4D274",
- INIT_0B => X"1C5D34787171C74DC5D34787174D1531714974D1874D34571E113716083403E4",
- INIT_0C => X"11BC45059E74587172579D87113C5A54D9100D71F15C56148574D215D3785A1E",
- INIT_0D => X"57101951A951691C0443C079D85206791520820865500D917555498E15555D43",
- INIT_0E => X"5643D4020DC94C76460F0D54FD2FB0F89D9E0713B48365143E566570FDD56475",
- INIT_0F => X"D9515D4955A1203DB50398E455555344471A9996A41D51BE6B0D1D51D5B6B105",
- INIT_10 => X"10D5514C5D3FD4116B8D1639C1459E40D9C401D0DD3DD2DD36BE5659440CD400",
- INIT_11 => X"9F7C5E85475555A1AF08416284DD00D9F401D01D31D21D36BE56595B07104410",
- INIT_12 => X"016B86C4001110346B344830DAE76470D916F1D9C089D9C816783811755571F1",
- INIT_13 => X"905DD595B4040D9C0A341D9FD0D9C0D98D1111034FC55553757DD5545E865D17",
- INIT_14 => X"11907484261415500C0179A5BE6373A31C467445C5596D8D8C03C3F0755C0D9D",
- INIT_15 => X"83E4589420F845D51755749D9C37408777410410826F9657E7434002771C0034",
- INIT_16 => X"354053475556521764441D2BC0A4815E5456A851083F555955557525B559536A",
- INIT_17 => X"951951D5114D0D2678263DD55BD1678D58E60D5903659436431C1549535241DD",
- INIT_18 => X"44003B04E4403403010B6681900440719D0110345BE343C85440F9715CDD5515",
- INIT_19 => X"7986431374C5975D9D99B9D835502D49FC805555310551403E56034C107395E0",
- INIT_1A => X"9D9120C85C8066553413241D5C5014B168B0F8D350CD1D40D275549BE1100366",
- INIT_1B => X"54B49D071CE741C739D071CE741C739D071C2741C739D071CD815C8654051858",
- INIT_1C => X"D1D145596B4080F8C1518D8456E6310CD53754060C2C353430D91D85BC110115",
- INIT_1D => X"5264555525557571DDDD84001BD76B9437189636B0241BA01AE46B024D525D40",
- INIT_1E => X"0377485474C5E3903E3400F03FC755E86D59C3478B415575D96767055BA26C0D",
- INIT_1F => X"E6A10F207A310D5D0455154D8E21AE7F540D550437D5EC0C6767EA6748574D31",
- INIT_20 => X"EF2D7675C576C499D515DDAD233DBA2F18E0360D814C1E67410C66A10FB31265",
- INIT_21 => X"03E10116505841CC7565776BFB332B767485444C49EF430D90DD1554E856A57E",
- INIT_22 => X"060010B042F18004022C024D1C0C8C024C88055CCD9726B03330313015D43E70",
- INIT_23 => X"2E10B94C860800712F77200103040C105040C086080040C8029A0013B84AE10B",
- INIT_24 => X"7D02A0C02689FCD84294002EC00712EB68CBDDC80042C2F7720010B040210B84",
- INIT_25 => X"00008C00000000000000003CC0000000000000003FFFFFFFEAAA954349323032",
- INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_28 => X"0000000000000000000000000000000000000000000C20000000000000000000",
- INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000",
- INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
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- port map (
- DOA => memARead(17 downto 16), -- Port A 2-bit Data Output
- DOB => memBRead(17 downto 16), -- Port B 2-bit Data Output
- ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input
- ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input
- CLKA => clk, -- Port A Clock
- CLKB => clk, -- Port B Clock
- DIA => memAWrite(17 downto 16), -- Port A 2-bit Data Input
- DIB => memBWrite(17 downto 16), -- Port B 2-bit Data Input
- ENA => re, -- Port A RAM Enable Input
- ENB => high, -- PortB RAM Enable Input
- SSRA => low, -- Port A Synchronous Set/Reset Input
- SSRB => low, -- Port B Synchronous Set/Reset Input
- WEA => memAWriteEnable, -- Port A Write Enable Input
- WEB => memBWriteEnable -- Port B Write Enable Input
- );
- ZPU_RAM9 : RAMB16_S2_S2
- generic map (
- INIT_A => X"0", -- Value of output RAM registers on Port A at startup
- INIT_B => X"0", -- Value of output RAM registers on Port B at startup
- SRVAL_A => X"0", -- Port A ouput value upon SSR assertion
- SRVAL_B => X"0", -- Port B ouput value upon SSR assertion
- WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
- WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
- SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
- INIT_00 => X"009600160000000600E4009200060557000C0006000C02960006039300FA003A",
- INIT_01 => X"B5D000000581E4BC081000060000110A155A0006000600060006004200740002",
- INIT_02 => X"000959D19C274612555555558600000001AD000000006B60000000120541D009",
- INIT_03 => X"00176555560F45581050E6005D955555583D155560F955579000000000002000",
- INIT_04 => X"811417206084505C818201B03D00174C00005DC0000000331557D00F94003980",
- INIT_05 => X"05904844505C8182114172060811417206084505C818204505C8182114172060",
- INIT_06 => X"00B95D4956847059025610062B41597E299E04403812086A800816305B801AB3",
- INIT_07 => X"16159116405B452D7501664AC09D5E01854D00657D01599654685565C7F75B44",
- INIT_08 => X"5B405444511054691C433355D45496618696555B86456D155784919B25916159",
- INIT_09 => X"970A02C57472B208C4E68B5073F10827B8D166E7551A574890E7B45841D905B8",
- INIT_0A => X"6608B8000D640598E4514E75D5599B9D54695D15555904C55955628C08C3901A",
- INIT_0B => X"C00B65A3002C1BE880B25A3002E96FA02CB02E9C30CB670268CB22CAE16696E1",
- INIT_0C => X"356F85644232302C85304B02CBE7201284D6591C100B20C8302FA0CCBEB32C68",
- INIT_0D => X"5A1BF03D468501103796DC24564AC421C50C30C3550C59841859454D1161632D",
- INIT_0E => X"85D4D448590820161C5B595667C5A5B00581FCE8121643C16C95DA45B0D65418",
- INIT_0F => X"985951471451596F6CB8120458A153154515546A2F45996E0059061061011525",
- INIT_10 => X"659969F546555451534615B81D455DA5981400574554574665B551AAF5F542E5",
- INIT_11 => X"6E55514D618A545D4CF26151450565984400574554574665B151AA555CD50306",
- INIT_12 => X"615B4500879C03135F4F516357E04A6598053058E04058E495F4D4C818A5A16D",
- INIT_13 => X"2B06D5689712598E0D3485815598E5986439C031312585AA184862965D454615",
- INIT_14 => X"5C56557980C2D511356D69554E245A019110147CD1668D555F16CD6E18AD5981",
- INIT_15 => X"4547156A05B44C709165B5058C4155014151861854578151255C0A1E1890E155",
- INIT_16 => X"2C2148055859485162900507A804095DA5159403033C58A4458A051A45469451",
- INIT_17 => X"D65165D65D4559653465B062850D534657E159901662056619D03156BAC41061",
- INIT_18 => X"B40CA027558966CDB0B5594581EB405406459A4355D1A9405265B84963061695",
- INIT_19 => X"B88C400052E3616445894869665813035A621616A3C160716E0031309D5A160E",
- INIT_1A => X"85810003DF1055A137F7C24592C0B0534655B4753E2568459918A017D1809655",
- INIT_1B => X"2ABF45A916115A458456916115A458456916D15A4584569161554844B32CD4D2",
- INIT_1C => X"90665146A34835B4405B2243F45997E25841667C00140D3415982F3F5F100D16",
- INIT_1D => X"914458A14585B58D0505057316525381649A743537DD175394E25B7DD251A445",
- INIT_1E => X"564156596A42E5216D10D5B16F1195145157D6798BF562805801602E55501859",
- INIT_1F => X"55955BA2D8F159910159565D4D217E105A5995016785D8328160E61156594E90",
- INIT_20 => X"ED891416A5952D91D6561D652197FA6617D2065983117557579455155B50B645",
- INIT_21 => X"96D1C15CCF5965D07595875966192514156597A438065D59859925A5D55A7182",
- INIT_22 => X"86601098427198040F00102D2065F4638C0066147C25890194D197D1A48D6E32",
- INIT_23 => X"2F10BD01DBE980D133F4660103040C10F04001DBE98040CF435E60123048C109",
- INIT_24 => X"41CC71F0461277C043200020184454DCA90C7D198042D31F466010B440F10BC4",
- INIT_25 => X"00000C00000000000000003CEAAAAAAAAAAAAAAA95555555555555540D14D180",
- INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_28 => X"0000000000000000000000000000000000000000000B70000000000000000000",
- INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000",
- INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
- port map (
- DOA => memARead(19 downto 18), -- Port A 2-bit Data Output
- DOB => memBRead(19 downto 18), -- Port B 2-bit Data Output
- ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input
- ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input
- CLKA => clk, -- Port A Clock
- CLKB => clk, -- Port B Clock
- DIA => memAWrite(19 downto 18), -- Port A 2-bit Data Input
- DIB => memBWrite(19 downto 18), -- Port B 2-bit Data Input
- ENA => re, -- Port A RAM Enable Input
- ENB => high, -- PortB RAM Enable Input
- SSRA => low, -- Port A Synchronous Set/Reset Input
- SSRB => low, -- Port B Synchronous Set/Reset Input
- WEA => memAWriteEnable, -- Port A Write Enable Input
- WEB => memBWriteEnable -- Port B Write Enable Input
- );
- ZPU_RAM10 : RAMB16_S2_S2
- generic map (
- INIT_A => X"0", -- Value of output RAM registers on Port A at startup
- INIT_B => X"0", -- Value of output RAM registers on Port B at startup
- SRVAL_A => X"0", -- Port A ouput value upon SSR assertion
- SRVAL_B => X"0", -- Port B ouput value upon SSR assertion
- WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
- WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
- SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
- INIT_00 => X"00000000000200000042000800000003000A0000000A00000000038300200000",
- INIT_01 => X"300AAAAAA020C232008800040000088008000000000000000000000800020000",
- INIT_02 => X"AAA00002000008000000000000AAAAAAA8042AAAAAAA010AAAAAAA8020080088",
- INIT_03 => X"AA800000008F00020208C0AA00000000023C000008F00000088CAAAAAAAA0AAA",
- INIT_04 => X"0002830A0A000A0C282820323C2A800CAAAA00E2AAAAAA330000C88F02AA302A",
- INIT_05 => X"8C0800000A0C2828002830A0A0002830A0A000A0C2828000A0C2828002830A0A",
- INIT_06 => X"00300020200000C0A1000A0C000002088CA200005C130CB400003000030080C3",
- INIT_07 => X"020002302E0320083088002282802C00880C88C83C880000C000083000800320",
- INIT_08 => X"0322C80CE030C20033203A80C2CB0000E00022030A800C830F0A2321A0082000",
- INIT_09 => X"020C00407253203845C00010EF0EF6002003008C60406000008C08C000200030",
- INIT_0A => X"000003AAA80820008C020809000002318101802138028CC00E20000838403030",
- INIT_0B => X"4202C0C108040C8010241C108090720804C0093413A20D00B042004C0C0000C0",
- INIT_0C => X"802D008C8E130004D020800042893401283000252C01344D1008344020C13030",
- INIT_0D => X"008A4000100000328380C228C82C20A028000000063200023000082C800000C0",
- INIT_0E => X"02A8408800BCD830040300828028A0328C009022AA0000000EA0800030C08030",
- INIT_0F => X"00A0000A0008280C031A0E8000000B8020C18000808C083C0A000C08C0A20800",
- INIT_10 => X"000000808C9540880F24C0F0A0183C8000A2A0C78C78C68C90B000080080A800",
- INIT_11 => X"0C100020230080883C080804208C8000A2A0C78C78C68C90B00008020822A882",
- INIT_12 => X"880720A2880288820F00008800C0A800008070C0C0A8C0C140320BE030002868",
- INIT_13 => X"A00C000080A0000C0A120C004000C000880028882000002E3028C0000C208C00",
- INIT_14 => X"02A03008AA200022008010800C001222002A3008243000041C40D082300C0002",
- INIT_15 => X"20808202003208CF6300308C0EA32823032C208220030202210210BA32028B30",
- INIT_16 => X"08D080B10000B62300200C028200260C0080C20B80FF0000000030003800020C",
- INIT_17 => X"C084080080080020322030C02A200B2401C0000880028000200AA000258210C8",
- INIT_18 => X"82A22200A08000200A0A0820C2282A1A8CA0000800C90280080030A00B8C0000",
- INIT_19 => X"7038030C21E023288C0238C80023663238A100000C2002080C000822021200A2",
- INIT_1A => X"8C0C088083000C003020CD8C08382EA2083032C0008420000A3000C0C8000020",
- INIT_1B => X"00F08C08A0A3022828C08A0A3022828C08A023022828C08A08280A2C0D0B6882",
- INIT_1C => X"00C800000108003200820121208428084F63002088280880B000FC0A230B8800",
- INIT_1D => X"088000002000300C8C0CB208838A0300000AA21072EA030B82C00F2EA2000820",
- INIT_1E => X"802328022802E2A80C8AE0300F2320023A02C0294F080038C023003C03080E00",
- INIT_1F => X"206003248E340008E002008C3C903C08020008E00380E000E30008A328021E00",
- INIT_20 => X"ECAA3232802208C0C0808C386200BAA2C3C8E20012002B0B0281206003082300",
- INIT_21 => X"00C82C04338C00893020230E2220EA32328022800A22AC00000AA020E00200AA",
- INIT_22 => X"8BAA2AC8AB22EA8AAA3AAAABAEF12242EAEEFAAAEAEAB9EB858904893FB00C38",
- INIT_23 => X"B62ADAAFAAAEA88604013AA2AD8AB62AA8AAA3AAAEA8AB6ECAA3AA299CAE72AC",
- INIT_24 => X"FA8BABAAF8BEAEACBAC0AABBF88B3FAB8FC1804EA8AB706013AA2ADCAA22AD8A",
- INIT_25 => X"00000C00000000000000003CC00000000000000000000000000000000B05893B",
- INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_28 => X"00000000000000000000000000000000000000000002C0000000000000000000",
- INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000",
- INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
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- port map (
- DOA => memARead(21 downto 20), -- Port A 2-bit Data Output
- DOB => memBRead(21 downto 20), -- Port B 2-bit Data Output
- ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input
- ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input
- CLKA => clk, -- Port A Clock
- CLKB => clk, -- Port B Clock
- DIA => memAWrite(21 downto 20), -- Port A 2-bit Data Input
- DIB => memBWrite(21 downto 20), -- Port B 2-bit Data Input
- ENA => re, -- Port A RAM Enable Input
- ENB => high, -- PortB RAM Enable Input
- SSRA => low, -- Port A Synchronous Set/Reset Input
- SSRB => low, -- Port B Synchronous Set/Reset Input
- WEA => memAWriteEnable, -- Port A Write Enable Input
- WEB => memBWriteEnable -- Port B Write Enable Input
- );
- ZPU_RAM11 : RAMB16_S2_S2
- generic map (
- INIT_A => X"0", -- Value of output RAM registers on Port A at startup
- INIT_B => X"0", -- Value of output RAM registers on Port B at startup
- SRVAL_A => X"0", -- Port A ouput value upon SSR assertion
- SRVAL_B => X"0", -- Port B ouput value upon SSR assertion
- WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
- WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
- SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
- INIT_00 => X"010002800005000000C1008400000003002100000021040000000B0B00000080",
- INIT_01 => X"300555555818C13E024600280002446044400000000000000000001400210008",
- INIT_02 => X"5558001502C05488000000002055555554085555555502055555554490240A60",
- INIT_03 => X"55400000005F20014925C05500000000017C800005F080001652555555554555",
- INIT_04 => X"284143450521050D141494397C95402E555500D95555557B8000D65F09557015",
- INIT_05 => X"4C06A011050D1414841434505284143450521050D1414A1050D1414841434505",
- INIT_06 => X"08300810202228C05A80858C82220C544955A62AAEABAEBA2AA230A8232640C7",
- INIT_07 => X"81820930112311843064801515403C98683C64CC3C642000820254B002222311",
- INIT_08 => X"2319C42EE8BAC200709BF860C11608091088112325648C440F25531652041820",
- INIT_09 => X"0AAA64A0B1AA88B6AE80A0F9CB0D89600123002ED080D0A1082E04C2601C8232",
- INIT_0A => X"80B1F855540592024B086067802000BB42034297B9016AC008640821B6A83830",
- INIT_0B => X"A590C3A6964A7A3129083A696430E8864AA6423AE830CEA4A9A084AA0C8048C8",
- INIT_0C => X"402E609E6DA6824AA1855024A08AA99B160820AA6292A9AA6A4229A908A6A9E9",
- INIT_0D => X"0155C680202440B64308D144C55D125014820820088920293200203C44080420",
- INIT_0E => X"21158224204A263099232052441402364C257115550828288DD0801236C05232",
- INIT_0F => X"025008204204448D20BD0F420204075350030300404C042C95208C84C8591480",
- INIT_10 => X"120000824C6A82140F18C0B258202D42025358CF4CF4CF4C70F6080202425682",
- INIT_11 => X"2D2E0814132042102D960C0C114C42025358CF4CF4CF4C70F608020811195469",
- INIT_12 => X"140F1159658164C80B60264402C9144202E0B8C2CA74C2C6C0F140DA32001498",
- INIT_13 => X"508C820240D8202CA5A58C268202C2024698164C8BB0201D3214C8120C114C82",
- INIT_14 => X"41582246551A8099826834902C91209986B53201DC3018282FC8F041320C2024",
- INIT_15 => X"14404302823121C09300314C2D531653231C1041590B25085301B0E5318547A2",
- INIT_16 => X"812A614202024993081A8C9343921D0C01408167603C02062020808004200508",
- INIT_17 => X"C048048048202080B140B8C815580B1803C9200648096080914544201F19B8C4",
- INIT_18 => X"635309A05A60803045A50814A916352D4C51801602C6196216023258074C8000",
- INIT_19 => X"B2642B997AD453154C2904C48011F864F8BA80800C1809048C988C8B81208071",
- INIT_1A => X"4C2886A01F5A0808B007D24C040A0258047231C180889E2205320603C46A4810",
- INIT_1B => X"80704C945513251544C945513251544C945513251544C9455031215D42809601",
- INIT_1C => X"08C528201A2E02316950461B05582C08889300706A9690E6B2029C005E94E8C0",
- INIT_1D => X"044202085020302C4C8C718442140B248247C1B0F4D18206C3C90B4D15080612",
- INIT_1E => X"4813140150A9C5588C5692388F9310815542C81567040804C25309BC02058D20",
- INIT_1F => X"80842348197820041901405C3C782C95012004188320C6849309555314016C2A",
- INIT_20 => X"CC55313140158184C0404C219A25715003C510202846A50F6A46008423460610",
- INIT_21 => X"08C41C890A4D24963010130841A215313140150A91905D2022045012D6015414",
- INIT_22 => X"4050001400501400051411551455445144445554554505515511551140808CB4",
- INIT_23 => X"0500154555414015155545000500140050004155414001414154500154015001",
- INIT_24 => X"5545515054551554015400055445555541451551400051455450001400500140",
- INIT_25 => X"00000C00000000000000003CC000000000000000000000000000000001151151",
- INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_28 => X"0000000000000000000000000000000000000000000300000000000000000000",
- INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000",
- INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
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- port map (
- DOA => memARead(23 downto 22), -- Port A 2-bit Data Output
- DOB => memBRead(23 downto 22), -- Port B 2-bit Data Output
- ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input
- ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input
- CLKA => clk, -- Port A Clock
- CLKB => clk, -- Port B Clock
- DIA => memAWrite(23 downto 22), -- Port A 2-bit Data Input
- DIB => memBWrite(23 downto 22), -- Port B 2-bit Data Input
- ENA => re, -- Port A RAM Enable Input
- ENB => high, -- PortB RAM Enable Input
- SSRA => low, -- Port A Synchronous Set/Reset Input
- SSRB => low, -- Port B Synchronous Set/Reset Input
- WEA => memAWriteEnable, -- Port A Write Enable Input
- WEB => memBWriteEnable -- Port B Write Enable Input
- );
- ZPU_RAM12 : RAMB16_S2_S2
- generic map (
- INIT_A => X"0", -- Value of output RAM registers on Port A at startup
- INIT_B => X"0", -- Value of output RAM registers on Port B at startup
- SRVAL_A => X"0", -- Port A ouput value upon SSR assertion
- SRVAL_B => X"0", -- Port B ouput value upon SSR assertion
- WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
- WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
- SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
- INIT_00 => X"039A019A000D000B001200DA0007023A001E000F001E0FDA000F0BD9003C00CC",
- INIT_01 => X"B69555554C5750DF077600150001D65619160003000B0003000B007E00620009",
- INIT_02 => X"554C39042084105A00000001DD55555555D955555555769555555565615EB5BE",
- INIT_03 => X"554AAC0000192000620183552AB000000064800001B8800A0819555555549555",
- INIT_04 => X"686F8AA55961BE2A9565862064954A8855552A255555506A800A481B855060D5",
- INIT_05 => X"0F947491BE2A956586F8AA559686F8AA55961BE2A9565A1BE2A956586F8AA559",
- INIT_06 => X"55E4555D553130F9471D940D531356044986430CC330E31F333C3E346A848391",
- INIT_07 => X"35D6B03E5162555DD551BE454D416A32594950D1695D6F969D55D0B050106257",
- INIT_08 => X"6A55650674135555948D2557551899E1D319DC6686C599575286C34146735D6B",
- INIT_09 => X"0B511375E55C5CCB20300054564209022543E5E74557415004E410F8141746E8",
- INIT_0A => X"AE0A5E5545D396F84475FC1100639791155105719777D7445735D550CB8C5434",
- INIT_0B => X"704D5111C1371164C4DA119C13584551371134971C79E5D3C571D371018C5BA1",
- INIT_0C => X"994753E402D391371FF80D1371A5C46D51346795104DC671DD378774DE15C546",
- INIT_0D => X"5B5A9011555CD497541A5760FB60D8541C4D34D354C86B843665D9495DD99522",
- INIT_0E => X"64695D546782203E03646F924107E6D50F86A6360919C905A7E55556E49D9436",
- INIT_0F => X"B8440DDE1D5511B9048D4B53755C343160951559A40F957A056F0D90D94114C7",
- INIT_10 => X"D679D4140D155DD85255D5E851D14116B87360F80F80F00D0537757F43D40796",
- INIT_11 => X"7410755803559DF9600C1C55540FD6387360F80F80F00D0534757C75D144000D",
- INIT_12 => X"D8525415078455CE5804350557A1910638D530F845D0F840E5651B0C35474055",
- INIT_13 => X"450D5D5551C06F8451150F8B46F8467840C8455CEC0766083640D5A775540D9D",
- INIT_14 => X"C435C39600054001D41427915A29110183343D0001D5B8055FDAF500354C6B86",
- INIT_15 => X"5E50155F46A5765083E7050F8583D043C3C4D34D43568A75400001C83704D943",
- INIT_16 => X"092310E176738BC3E0850F1317C143755645556B5856754057556754DDD55B55",
- INIT_17 => X"1D05D35D25D36BE56595F0D52318565417A1679C5AE171AE108065D5B81070DC",
- INIT_18 => X"137710413751AC75D19455584241371D0D284586159535150C16284DD40D9740",
- INIT_19 => X"68B51C594F5503C60F85C0DDBE728B201C6CDD960905D341AA04DCE847119D04",
- INIT_1A => X"0F8C5FD0CDD555441033720F9048321F20C6655390C4D1167C355C5495C159F5",
- INIT_1B => X"54650F25F943C97E50F25F943C97E50F25F943C97E50F25F99553100D20C86C8",
- INIT_1C => X"B0D3CDD5C10D16651A0001CA4C27190C4C83E467FD85FC2686B8D90E8F841C1D",
- INIT_1D => X"9B517557476727680F0FB03495F05689BECE30C59D995556D6A05DD991756036",
- INIT_1E => X"9AC3CC76F058CBDDA96706F9BF837755E8D719DE3645D500F8C3E26C15549C6B",
- INIT_1F => X"75776F40CEB46F9098761DF5694D6A1D776B9C198FF7418483E18F83EC767C15",
- INIT_20 => X"CF6C3C3EC76E0CC7DD9D71515318703B9794416707741951E1AF35776F3A3327",
- INIT_21 => X"1995184149CDC7DFA76748564D310C3C3CC76F45BAFA416F86F01755E5775604",
- INIT_22 => X"C13000BC02E04C002D999D80225BDDC38B0652041E3E0C672F772F7700859A10",
- INIT_23 => X"3900D6125104C0BE1369130006001000D000C25104C001872DE13009E407500B",
- INIT_24 => X"9B24DA1D155701E2091800057049300F44449A44C003B116913000DC02D00F40",
- INIT_25 => X"00000C00000000000000003F00000000000000003FFFFFFFEAAA954314EF7729",
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- INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_28 => X"00000000000000000000000000000000000000000002B0000000000000000000",
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- INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
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- port map (
- DOA => memARead(25 downto 24), -- Port A 2-bit Data Output
- DOB => memBRead(25 downto 24), -- Port B 2-bit Data Output
- ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input
- ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input
- CLKA => clk, -- Port A Clock
- CLKB => clk, -- Port B Clock
- DIA => memAWrite(25 downto 24), -- Port A 2-bit Data Input
- DIB => memBWrite(25 downto 24), -- Port B 2-bit Data Input
- ENA => re, -- Port A RAM Enable Input
- ENB => high, -- PortB RAM Enable Input
- SSRA => low, -- Port A Synchronous Set/Reset Input
- SSRB => low, -- Port B Synchronous Set/Reset Input
- WEA => memAWriteEnable, -- Port A Write Enable Input
- WEB => memBWriteEnable -- Port B Write Enable Input
- );
- ZPU_RAM13 : RAMB16_S2_S2
- generic map (
- INIT_A => X"0", -- Value of output RAM registers on Port A at startup
- INIT_B => X"0", -- Value of output RAM registers on Port B at startup
- SRVAL_A => X"0", -- Port A ouput value upon SSR assertion
- SRVAL_B => X"0", -- Port B ouput value upon SSR assertion
- WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
- WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
- SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
- INIT_00 => X"048000800000000200D00184000A017000000002000011200002000000180188",
- INIT_01 => X"7C5555555854138606440000000108641104000E0006000A0002005000C00000",
- INIT_02 => X"5558042D08A0B41A00000001AD555555549155555555E41555555541A0206648",
- INIT_03 => X"55715C000240F00919240F55C57000000903C000243480300640555555555555",
- INIT_04 => X"405C8182114172060845114903D571635555C5955555590C80300643455903D5",
- INIT_05 => X"5B801D017206084505C818211405C8182114172060845017206084505C818211",
- INIT_06 => X"CF9158A961AC95B82D05825991BD5A818146BA784E178E05EE196D1F5140921C",
- INIT_07 => X"B005756E115DA14862955E25811175003146959146905384061691264ACA55A0",
- INIT_08 => X"59A42C80120D1614043907018A5255D15255DD5D458556865145564855BB005F",
- INIT_09 => X"01CCB2259A0B2392C28EB25C2C44439D7556E1C065846DC42FC145B4B017F5D4",
- INIT_0A => X"5D045055085455F440192D596B5B87059615B7094314F0445810596FD2990D67",
- INIT_0B => X"2AFAD9C0AB629CBFAFADDC0ABEB572DBE2CBEB0208A280BA712A3A2C017F5451",
- INIT_0C => X"11556380E4B31F22CC8459F22A00B2C9AD2F53440AC8B22C8BAA332CA8CCB170",
- INIT_0D => X"20521D116161320750D75445BA63043113F3CF3C5A8353456600614680580100",
- INIT_0E => X"61C0465D5B55056D2C59536A410615565B4484160756D1354445850590451166",
- INIT_0F => X"34540464C6282165840F2FC01644185361165611845B8175155F598598574301",
- INIT_10 => X"95B81610590006D555A145D454614515B44D55B85B05B059451518414910F155",
- INIT_11 => X"754218A4566586A15676D758A25B95745945B85B05B05945151841195403B8C5",
- INIT_12 => X"D551A2D57526556851549CC515512185746555B44C55B454651AD2896651552D",
- INIT_13 => X"8559861581715344E5155B4405F4557449226556808162B96615991018A25946",
- INIT_14 => X"26810900EE302D971042C7156514441D7E116C47006114D165575485665C5744",
- INIT_15 => X"A0C05611F51A011016E3015B4416DC56D6D50410605144194847857167575649",
- INIT_16 => X"8501D75816390056D02C5B13154B001851558A06B000164401658184C0614458",
- INIT_17 => X"0574554574665B151AA515999DD755A194515B8256D1855D195248612057559C",
- INIT_18 => X"294541ADD1C95F545C0658A6DD729444592D35B5D46841BCF6D5145056598440",
- INIT_19 => X"149C18D3853DD6ED5B46C5954E2306988017058001305075452D168064440507",
- INIT_1A => X"5B45DE3E255C5866C889405B844000F7C4859A19500318D5F56654D4686755D5",
- INIT_1B => X"94C55B661556D98555B661556D98555B661556D98555B6615966998090003DF1",
- INIT_1C => X"3592E46160BFE5DAB10482E8425701001416E005E33F6F15057471E127141505",
- INIT_1D => X"80C9165B516301415B5B0701161251457D340D55D4531628D7525D4509184AA5",
- INIT_1E => X"16D6E0146835CA997694559D7456518A815556F59C405905B416D01856291657",
- INIT_1F => X"8587514864C4538C5A1605E146B57504145784994C01A31416D14956D0141E0C",
- INIT_20 => X"CD516D6D0145C6464505A965E90EB3E9566B0C5F1536A2596A25058759A61921",
- INIT_21 => X"5468563D4019C7D5514156594E90616D6E0146C37529415345B4115925148658",
- INIT_22 => X"01C0003000C07000268DD053D75C7D13203354162007003471F473F46485451C",
- INIT_23 => X"020009137507003F200E1C000C003400D00003750700030D29C1C00BC00F0003",
- INIT_24 => X"CC244C4D1D8522020A340015444E300FD448038700000200E1C0000002D00080",
- INIT_25 => X"00000C00000000000000003F2AAAAAAAAAAAAAAA95555555555555541931F475",
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- INIT_28 => X"0000000000000000000000000000000000000000000300000000000000000000",
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- INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
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- INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
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- port map (
- DOA => memARead(27 downto 26), -- Port A 2-bit Data Output
- DOB => memBRead(27 downto 26), -- Port B 2-bit Data Output
- ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input
- ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input
- CLKA => clk, -- Port A Clock
- CLKB => clk, -- Port B Clock
- DIA => memAWrite(27 downto 26), -- Port A 2-bit Data Input
- DIB => memBWrite(27 downto 26), -- Port B 2-bit Data Input
- ENA => re, -- Port A RAM Enable Input
- ENB => high, -- PortB RAM Enable Input
- SSRA => low, -- Port A Synchronous Set/Reset Input
- SSRB => low, -- Port B Synchronous Set/Reset Input
- WEA => memAWriteEnable, -- Port A Write Enable Input
- WEB => memBWriteEnable -- Port B Write Enable Input
- );
- ZPU_RAM14 : RAMB16_S2_S2
- generic map (
- INIT_A => X"0", -- Value of output RAM registers on Port A at startup
- INIT_B => X"0", -- Value of output RAM registers on Port B at startup
- SRVAL_A => X"0", -- Port A ouput value upon SSR assertion
- SRVAL_B => X"0", -- Port B ouput value upon SSR assertion
- WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
- WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
- SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
- INIT_00 => X"000A000A00020008000A0002000400B2000A0008000A008A000C000A00100010",
- INIT_01 => X"3C00000002000B2100020000000000020882000C000800000004000A00060002",
- INIT_02 => X"0002800A00C02800AAAAAAA80400000003080000000042000000000008082020",
- INIT_03 => X"00300EAAA808FAA00C008F00C03AAAAAA023EAAA80B02AB22008000000000000",
- INIT_04 => X"2A0C2828002830A0A000802023C0303B0000C0000000002E2AB2200B000023C0",
- INIT_05 => X"0302A00830A0A000A0C2828002A0C2828002830A0A000A830A0A000A0C282800",
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- INIT_1B => X"0B000302E000C0B800302E000C0B800302E000C0B800302E0808E84000880830",
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- INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
- port map (
- DOA => memARead(29 downto 28), -- Port A 2-bit Data Output
- DOB => memBRead(29 downto 28), -- Port B 2-bit Data Output
- ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input
- ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input
- CLKA => clk, -- Port A Clock
- CLKB => clk, -- Port B Clock
- DIA => memAWrite(29 downto 28), -- Port A 2-bit Data Input
- DIB => memBWrite(29 downto 28), -- Port B 2-bit Data Input
- ENA => re, -- Port A RAM Enable Input
- ENB => high, -- PortB RAM Enable Input
- SSRA => low, -- Port A Synchronous Set/Reset Input
- SSRB => low, -- Port B Synchronous Set/Reset Input
- WEA => memAWriteEnable, -- Port A Write Enable Input
- WEB => memBWriteEnable -- Port B Write Enable Input
- );
- ZPU_RAM15 : RAMB16_S2_S2
- generic map (
- INIT_A => X"0", -- Value of output RAM registers on Port A at startup
- INIT_B => X"0", -- Value of output RAM registers on Port B at startup
- SRVAL_A => X"0", -- Port A ouput value upon SSR assertion
- SRVAL_B => X"0", -- Port B ouput value upon SSR assertion
- WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
- WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
- SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
- INIT_00 => X"012501250005000C00850021000C04790015000800150445000C06A500A20022",
- INIT_01 => X"3E0000000102861A0021001A000062014461000800080008000C000500090005",
- INIT_02 => X"00016181A9A606405555555408000000020400000000C1800000002406860012",
- INIT_03 => X"00380D555416F5504C816F00E0355555505BD555417215799015000000000000",
- INIT_04 => X"150D141484143450521044505BC038370000E0000000005D1579901720005BC0",
- INIT_05 => X"232560943450521050D141484150D1414841434505210543450521050D141484",
- INIT_06 => X"00220200080CA232424C242006C10156652140C2A0A8208A00A08C600C152802",
- INIT_07 => X"7960B48C94080954C8002C90603830464420020820060B290C804A2B0A8A0808",
- INIT_08 => X"0801A099B260808262038663204603C45802DC0C111020210811482500B7960F",
- INIT_09 => X"B21A08408092A834489A08F2B02D6019E008C8D9C021C81E70D9D231028F00C1",
- INIT_0A => X"3C65F50054C400B126310D53AA0B236700872053A93255150278C00D7442A482",
- INIT_0B => X"40229BA900843AA20229BA9008A6EA90C4A08A6493A69908EA4E884AE83E0304",
- INIT_0C => X"083213991D0B0084AC3620084E992813008A0B666021294A508A694329A528EA",
- INIT_0D => X"941900480802026609C30522351855428704104100200F1080A4C42028C29489",
- INIT_0E => X"09924C500B55848C49080F5E48945081231541904403C48021D020A0854C8880",
- INIT_0F => X"F11354CE4C829821D2282A093015515E4540408412232430540F202202542263",
- INIT_10 => X"C0B252C920AA8C820809A0C114C82140F11A123A23A23A20A08132192B490540",
- INIT_11 => X"31A9320188014C4821458A02082340F11A123A23A23A20A08132193189540F14",
- INIT_12 => X"82080840056000820852B53082055430F180823121423135908045108013168C",
- INIT_13 => X"50204C8060860B121484231580B130B12056000826630914809200493208204C",
- INIT_14 => X"60147B5503C56A444956B3C8304DAD4164688CA9A8C840D832822238801B0B15",
- INIT_15 => X"050A408700809D8A08CB58231148D108C8D65965050811315FBC68B48264017B",
- INIT_16 => X"3987081A30B361C8C641238A42DC6932092020630669301593001321D4C82502",
- INIT_17 => X"8CF4CF4CF4C70F60802082005016080982040F2403C4582C4D2424C852942208",
- INIT_18 => X"5A12D4581F1C3F2241500201C105A1AA20896085820254018580C114C4202535",
- INIT_19 => X"81709601658808D02311D2042C992E2EAE684C29A084C9682040482661AD4CA0",
- INIT_1A => X"231F1CC0888102070A2228232621A807D66080894AE65C90B4801182024003D0",
- INIT_1B => X"060023511408D445023511408D445023511408D4450235114405D4AA486A01F5",
- INIT_1C => X"F208D4C846C8108005EA29C4245760AE6A08CA81CC005E9120F1C00A4B12968C",
- INIT_1D => X"26093003130B531623235855404608102D249870C644408183040C6451321180",
- INIT_1E => X"42C8D6310685E5402010908C22081320554202D55024C0523108C58D80818C0F",
- INIT_1F => X"1013086689640B2442308CC820343062310B24402E93142648C56148D6315DA1",
- INIT_20 => X"ED148C8D631068854C4C500542A579414301690F86B5240C527110130841A213",
- INIT_21 => X"82028B29217CE3C1531314016C2A548C8D6310685441680F10F6131181315052",
- INIT_22 => X"4150005401505400051555515555155155055515155504555455555540A03041",
- INIT_23 => X"1100451145454055115515000500140050004145454001414151500144051005",
- INIT_24 => X"5544555515551154011400155405100554441545400111055150004400500440",
- INIT_25 => X"00000C00000000000000003F0000000000000000000000000000000015545555",
- INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_28 => X"0000000000000000000000000000000000000000000300000000000000000000",
- INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000",
- INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
- port map (
- DOA => memARead(31 downto 30), -- Port A 2-bit Data Output
- DOB => memBRead(31 downto 30), -- Port B 2-bit Data Output
- ADDRA => memAAddr(14 downto 2), -- Port A 13-bit Address Input
- ADDRB => memBAddr(14 downto 2), -- Port B 13-bit Address Input
- CLKA => clk, -- Port A Clock
- CLKB => clk, -- Port B Clock
- DIA => memAWrite(31 downto 30), -- Port A 2-bit Data Input
- DIB => memBWrite(31 downto 30), -- Port B 2-bit Data Input
- ENA => re, -- Port A RAM Enable Input
- ENB => high, -- PortB RAM Enable Input
- SSRA => low, -- Port A Synchronous Set/Reset Input
- SSRB => low, -- Port B Synchronous Set/Reset Input
- WEA => memAWriteEnable, -- Port A Write Enable Input
- WEB => memBWriteEnable -- Port B Write Enable Input
- );
-end dualport_ram_arch;
diff --git a/zpu/hdl/zpu3/src/xmake.filelist b/zpu/hdl/zpu3/src/xmake.filelist deleted file mode 100644 index 3d0a779..0000000 --- a/zpu/hdl/zpu3/src/xmake.filelist +++ /dev/null @@ -1,5 +0,0 @@ -vhdl zylin "zpu_config.vhd"
-vhdl zylin "zpupkg.vhd"
-vhdl work "dmips_ram.vhd"
-vhdl zylin "zpu_top_bram_intstack.vhd"
-vhdl work "testlut.vhd"
diff --git a/zpu/hdl/zpu3/src/xmake.xst b/zpu/hdl/zpu3/src/xmake.xst deleted file mode 100644 index bfdb23f..0000000 --- a/zpu/hdl/zpu3/src/xmake.xst +++ /dev/null @@ -1,53 +0,0 @@ -set -tmpdir ../tmp
-set -xsthdpdir ../xst
-run
--ifn xmake.filelist
--ifmt mixed
--ofn ../syn/ic300
--ofmt NGC
--p xc3s400-4-ft256
--top ic300
--opt_mode Area
--opt_level 2
--iuc NO
--lso ic300.lso
--keep_hierarchy NO
--glob_opt AllClockNets
--rtlview Yes
--read_cores YES
--write_timing_constraints NO
--cross_clock_analysis NO
--hierarchy_separator /
--bus_delimiter <>
--case maintain
--slice_utilization_ratio 100
--verilog2001 YES
--fsm_extract YES -fsm_encoding Auto
--safe_implementation No
--fsm_style lut
--ram_extract Yes
--ram_style Auto
--rom_extract Yes
--rom_style Auto
--mux_extract YES
--mux_style Auto
--decoder_extract YES
--priority_extract YES
--shreg_extract YES
--shift_extract YES
--xor_collapse YES
--resource_sharing YES
--mult_style auto
--iobuf YES
--max_fanout 500
--bufg 8
--register_duplication YES
--equivalent_register_removal NO
--register_balancing No
--slice_packing YES
--optimize_primitives NO
--use_clock_enable Yes
--use_sync_set No
--use_sync_reset No
--iob true
--slice_utilization_ratio_maxmargin 5
diff --git a/zpu/hdl/zpu3/src/zpu_config.vhd b/zpu/hdl/zpu3/src/zpu_config.vhd deleted file mode 100644 index 506121c..0000000 --- a/zpu/hdl/zpu3/src/zpu_config.vhd +++ /dev/null @@ -1,25 +0,0 @@ -library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-
-package zpu_config is
-
- constant Generate_Trace : boolean := false;
- -- during simulation, set this to '0' to get matching trace.txt
- constant DontCareValue : std_logic := '0';
- -- Clock frequency in MHz.
- constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64";
- -- maximum address includes upper bit for IO registers
- -- the rest is RAM
- constant maxAddrBit : integer := 14;
- constant minAddrBit : integer := 2;
- -- This bit is set for read/writes to IO
- -- FIX!!! eventually this should be set to wordSize-1 so as to
- -- to make the address of IO independent of amount of memory
- -- reserved for CPU. Requires trivial tweaks in toolchain/runtime
- -- libraries.
- constant ioBit : integer := maxAddrBit+1;
- constant wordPower : integer := 5;
- constant wordSize : integer := 2**wordPower;
-
-end zpu_config;
diff --git a/zpu/hdl/zpu3/src/zpu_pipelined.vhd b/zpu/hdl/zpu3/src/zpu_pipelined.vhd deleted file mode 100644 index 207939d..0000000 --- a/zpu/hdl/zpu3/src/zpu_pipelined.vhd +++ /dev/null @@ -1,852 +0,0 @@ --- Company: ZPU3 --- Engineer: Øyvind Harboe - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -use IEEE.STD_LOGIC_arith.ALL; - -library zylin; -use zylin.zpu_config.all; -use zylin.zpupkg.all; - - -entity zpu_top is - Port ( clk : in std_logic; - areset : in std_logic; - io_busy : in std_logic; - io_read : in std_logic_vector(7 downto 0); - io_write : out std_logic_vector(7 downto 0); - io_addr : out std_logic_vector(maxAddrBit downto minAddrBit); - io_writeEnable : out std_logic; - io_readEnable : out std_logic; - interrupt : in std_logic; - break : out std_logic); -end zpu_top; - -architecture behave of zpu_top is - -signal readIO : std_logic; - - - -signal memAWriteEnable : std_logic; -signal memAAddr : std_logic_vector(maxAddrBit downto minAddrBit); -signal memAWrite : std_logic_vector(wordSize-1 downto 0); -signal memARead : std_logic_vector(wordSize-1 downto 0); -signal memBWriteEnable : std_logic; -signal memBAddr : std_logic_vector(maxAddrBit downto minAddrBit); -signal memBWrite : std_logic_vector(wordSize-1 downto 0); -signal memBRead : std_logic_vector(wordSize-1 downto 0); - - -signal busy : std_logic; - -signal begin_inst : std_logic; - - - -signal trace_opcode : std_logic_vector(7 downto 0); -signal trace_pc : std_logic_vector(maxAddrBit downto 0); -signal trace_sp : std_logic_vector(maxAddrBit downto minAddrBit); -signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); -signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); - -type DecodedOpcodeType is -( -Decoded_Stall , -Decoded_Nop , -Decoded_Im , -Decoded_ImShift , -Decoded_LoadSP , -Decoded_StoreSP , -Decoded_AddSP , -Decoded_Emulate , -Decoded_Break , -Decoded_PushPC , -Decoded_PushSP , -Decoded_PopPC , -Decoded_Add , -Decoded_Or , -Decoded_And , -Decoded_Load , -Decoded_Not , -Decoded_Flip , -Decoded_Store , -Decoded_Storeb , -Decoded_PopSP , -Decoded_Ashiftleft , -Decoded_Ashiftright , -Decoded_Lshiftright , -Decoded_Eqbranch , -Decoded_Neqbranch , -Decoded_Eq , -Decoded_Neq , -Decoded_Loadb , -Decoded_Lessthan , -Decoded_Lessthanorequal , -Decoded_Ulessthan , -Decoded_Ulessthanorequal , -Decoded_Duplicate , -Decoded_Duplicate2 , -Decoded_Duplicate3 , -Decoded_MoveDown, -Decoded_MoveDown2, -Decoded_MoveDown3, -Decoded_Pushspadd, -Decoded_Callpcrel, -Decoded_Sub -); - - -signal decode_pc : std_logic_vector(maxAddrBit downto 0); -signal decode_fetchedPC : std_logic_vector(maxAddrBit downto 0); -signal decode_fetched : std_logic; -signal decode_opcode : std_logic_vector(OpCode_Size-1 downto 0); -signal decode_opcodeWord : std_logic_vector(wordSize-1 downto 0); -signal decode_starved : std_logic; -signal decode_wordStarved : std_logic; -signal decode_willBeStarved : std_logic; -signal decode_idim_flag : std_logic; - -signal execute1_stall : std_logic; -signal execute1_fetched : std_logic; -signal execute1_decodedOpcode : DecodedOpcodeType; -signal execute1_fetchedPC : std_logic_vector(maxAddrBit downto 0); -signal execute1_sp : std_logic_vector(maxAddrBit downto minAddrBit); -signal execute1_opcode : std_logic_vector(opCode_Size-1 downto 0); -signal execute1_spOffset : std_logic_vector(4 downto 0); -signal execute1_fetchPC : std_logic_vector(maxAddrBit downto 0); -signal execute1_push1 : std_logic; -signal execute1_push2 : std_logic; -signal execute1_pop1 : std_logic; -signal execute1_pop2 : std_logic; -signal execute1_antialias : std_logic; -signal execute1_savedTopOfStack : std_logic_vector(wordSize-1 downto 0); - - -signal load_decodedOpcode : DecodedOpcodeType; -signal load_opcode : std_logic_vector(opCode_Size-1 downto 0); -signal load_spOffset : std_logic_vector(4 downto 0); -signal load_stall : std_logic; -signal load_willBeStalled : std_logic; - -signal execute2_opcode : std_logic_vector(opCode_Size-1 downto 0); -signal execute2_topOfStack : std_logic_vector(wordSize-1 downto 0); -signal execute2_addResult : std_logic_vector(wordSize-1 downto 0); -signal execute2_topOfStackB : std_logic_vector(wordSize-1 downto 0); -signal execute2_pc : std_logic_vector(maxAddrBit downto 0); -signal execute2_sp : std_logic_vector(maxAddrBit downto minAddrBit); -signal execute2_loading : std_logic; -signal execute2_loadByte : std_logic; -signal execute2_storeByte : std_logic; -signal execute2_loadingDone : std_logic; -signal execute2_decodedOpcode : DecodedOpcodeType; -signal execute2_spOffset : std_logic_vector(4 downto 0); -signal execute2_persistTopOfStack : std_logic; -signal execute2_persistTopOfStackB : std_logic; -signal execute2_resync : std_logic; -signal execute2_resync2 : std_logic; -signal execute2_resync3 : std_logic; -signal execute2_resync4 : std_logic; -signal execute2_resync5 : std_logic; -signal execute2_resync6 : std_logic; -signal execute2_resync7 : std_logic; -signal execute2_resync8 : std_logic; -signal execute2_resync9 : std_logic; -signal execute2_resync10 : std_logic; - - -begin - traceFileGenerate: - if Generate_Trace generate - trace_file: trace port map ( - clk => clk, - begin_inst => begin_inst, - pc => trace_pc, - opcode => trace_opcode, - sp => trace_sp, - memA => trace_topOfStack, - memB => trace_topOfStackB, - busy => busy - ); - end generate; - - - memory: dualport_ram port map ( - clk => clk, - memAWriteEnable => memAWriteEnable, - memAAddr => memAAddr, - memAWrite => memAWrite, - memARead => memARead, - memBWriteEnable => memBWriteEnable, - memBAddr => memBAddr, - memBWrite => memBWrite, - memBRead => memBRead - ); - - opcodeControl: - process(clk, areset) - variable compareA : signed(wordSize-1 downto 0); - variable compareB : signed(wordSize-1 downto 0); - variable execute1_doFetch : boolean; - begin - if areset = '1' then - break <= '0'; - begin_inst <= '0'; - memAAddr <= (others => '0'); - memBAddr <= (others => '0'); - memAWriteEnable <= '0'; - memBWriteEnable <= '0'; - memAWrite <= (others => '0'); - memBWrite <= (others => '0'); - - memBAddr <= (others => '0'); - memBWrite <= (others => '0'); - - - io_writeEnable <= '0'; - io_readEnable <= '0'; - io_addr <= (others => '0'); - io_write <= (others => '0'); - - -- stage 1. Don't care since this is driven by stage2 - decode_pc <= (others => '0'); - decode_fetched <= '0'; - decode_starved <= '0'; - decode_opcode <= (others => '0'); - decode_opcodeWord <= (others => '0'); - - -- stage 2. - execute1_antialias <= '0'; - execute1_fetchPC <= (others => '0'); - execute1_fetched <= '0'; - execute1_decodedOpcode <= Decoded_Stall; - execute1_sp <= (2 => '0', others => '1'); - execute1_push1 <= '0'; - execute1_push2 <= '0'; - execute1_pop1 <= '0'; - execute1_pop2 <= '0'; - execute1_stall <= '1'; - - -- stage 3 - load_decodedOpcode <= Decoded_Stall; - load_stall <= '1'; - load_willBeStalled <= '1'; - - -- stage 4 - decode_idim_flag <= '0'; - execute2_pc <= (others => '0'); - execute2_sp <= (2 => '0', others => '1'); - execute2_loading <= '0'; - execute2_loadByte <= '0'; - execute2_storeByte <= '0'; - execute2_loadingDone <= '0'; - execute2_decodedOpcode <= Decoded_Stall; - execute2_resync <= '1'; - execute2_resync2 <= '0'; - execute2_resync3 <= '0'; - execute2_resync4 <= '0'; - execute2_resync5 <= '0'; - execute2_resync6 <= '0'; - execute2_resync7 <= '0'; - execute2_resync8 <= '0'; - execute2_resync9 <= '0'; - execute2_resync10 <= '0'; - execute2_persistTopOfStack <= '0'; - execute2_persistTopOfStackB <= '0'; - - -- stage 5 - memBWriteEnable <= '0'; - - - elsif (clk'event and clk = '1') then - memAWriteEnable <= '0'; - memBWriteEnable <= '0'; - io_writeEnable <= '0'; - io_readEnable <= '0'; - begin_inst <= '0'; - - -- stage0: fetch - decode_willBeStarved <= '0'; - if (decode_fetched='1') then - -- resync #4 - decode_opcodeWord <= memARead; - decode_pc <= decode_fetchedPC; - elsif (decode_pc(minAddrBit-1 downto 0)=b"11") then - decode_willBeStarved <= '1'; - else - -- we can continue decoding. - decode_pc <= decode_pc + 1; - end if; - - -- stage 0b: move to byte.. - -- resync #5 - decode_starved <= decode_willBeStarved; - case decode_pc(minAddrBit-1 downto 0) is - when "00" => decode_opcode <= decode_opcodeWord(31 downto 24); - when "01" => decode_opcode <= decode_opcodeWord(23 downto 16); - when "10" => decode_opcode <= decode_opcodeWord(15 downto 8); - when others => decode_opcode <= decode_opcodeWord(7 downto 0); - end case; - - -- stage1: decode 1 - execute1_opcode <= decode_opcode; - - execute1_spOffset(4)<=not decode_opcode(4); - execute1_spOffset(3 downto 0)<=decode_opcode(3 downto 0); - - execute1_decodedOpcode<=Decoded_Break; - - decode_idim_flag <= '0'; - - -- resync #6 - -- resync #1 - if (decode_starved = '1') then - execute1_decodedOpcode<=Decoded_Stall; - decode_idim_flag <= decode_idim_flag; - elsif (decode_opcode(7 downto 7)=OpCode_Im) then - decode_idim_flag <= '1'; - if (decode_idim_flag = '0') then - execute1_decodedOpcode<=Decoded_Im; - else - execute1_decodedOpcode<=Decoded_ImShift; - end if; - elsif (decode_opcode(7 downto 5)=OpCode_StoreSP) then - if (decode_opcode(4 downto 0)=b"10001") then - execute1_decodedOpcode<=Decoded_MoveDown; - elsif (decode_opcode(4 downto 0)=b"10010") then - execute1_decodedOpcode<=Decoded_MoveDown2; --- elsif (decode_opcode(4 downto 0)=b"10011") then --- execute1_decodedOpcode<=Decoded_MoveDown3; - else - execute1_decodedOpcode<=Decoded_StoreSP; - end if; - elsif (decode_opcode(7 downto 5)=OpCode_LoadSP) then - if (decode_opcode(4 downto 0)=b"10000") then - execute1_decodedOpcode<=Decoded_Duplicate; - elsif (decode_opcode(4 downto 0)=b"10001") then - execute1_decodedOpcode<=Decoded_Duplicate2; - elsif (decode_opcode(4 downto 0)=b"10010") then - execute1_decodedOpcode<=Decoded_Duplicate3; - else - execute1_decodedOpcode<=Decoded_LoadSP; - end if; - elsif (decode_opcode(7 downto 5)=OpCode_Emulate) then - execute1_decodedOpcode<=Decoded_Emulate; - if decode_opcode(5 downto 0)=OpCode_Neqbranch then - execute1_decodedOpcode <= Decoded_Neqbranch; - elsif decode_opcode(5 downto 0)=OpCode_Eq then - execute1_decodedOpcode <= Decoded_Eq; - elsif decode_opcode(5 downto 0)=OpCode_Lessthan then - execute1_decodedOpcode <= Decoded_Lessthan; - elsif decode_opcode(5 downto 0)=OpCode_Ulessthan then - execute1_decodedOpcode <= Decoded_Ulessthan; - elsif decode_opcode(5 downto 0)=OpCode_Loadb then - execute1_decodedOpcode <= Decoded_Loadb; - elsif decode_opcode(5 downto 0)=OpCode_Storeb then - execute1_decodedOpcode <= Decoded_Storeb; - elsif decode_opcode(5 downto 0)=OpCode_Pushspadd then - execute1_decodedOpcode <= Decoded_Pushspadd; - elsif decode_opcode(5 downto 0)=OpCode_Callpcrel then - execute1_decodedOpcode <= Decoded_Callpcrel; - elsif decode_opcode(5 downto 0)=OpCode_Sub then - execute1_decodedOpcode <= Decoded_Sub; - end if; - elsif (decode_opcode(7 downto 4)=OpCode_AddSP) then - if (decode_opcode(3 downto 0) = 0) then - execute1_decodedOpcode<=Decoded_Ashiftleft; - elsif (decode_opcode(3 downto 0) = 1) then --- execute1_decodedOpcode<=Decoded_AddSP; - elsif (decode_opcode(3 downto 0) = 2) then --- execute1_decodedOpcode<=Decoded_AddSP; - else - execute1_decodedOpcode<=Decoded_AddSP; - end if; - else - case decode_opcode(3 downto 0) is - when OpCode_Nop => - execute1_decodedOpcode<=Decoded_Nop; - when OpCode_PushSP => - execute1_decodedOpcode<=Decoded_PushSP; - when OpCode_PopPC => - execute1_decodedOpcode<=Decoded_PopPC; - when OpCode_Add => - execute1_decodedOpcode<=Decoded_Add; - when OpCode_Or => - execute1_decodedOpcode<=Decoded_Or; - when OpCode_And => - execute1_decodedOpcode<=Decoded_And; - when OpCode_Load => - execute1_decodedOpcode<=Decoded_Load; - when OpCode_Not => - execute1_decodedOpcode<=Decoded_Not; - when OpCode_Flip => - execute1_decodedOpcode<=Decoded_Flip; - when OpCode_Store => - execute1_decodedOpcode<=Decoded_Store; - when OpCode_PopSP => - execute1_decodedOpcode<=Decoded_PopSP; - when others => - execute1_decodedOpcode<=Decoded_Break; - end case; - end if; - - - -- stage 2: execute 1 - load stage. - -- - -- the address must be known without using the value on top of the stack... - -- resync #3 - execute1_fetched <= '0'; - decode_fetched <= execute1_fetched; -- the value in memAAddr will be valid for 1 cycle only - decode_fetchedPC <= execute1_fetchedPC; - - if (execute1_fetchPC(1 downto 0)/=b"00") then - execute1_fetchPC <= execute1_fetchPC+1; - end if; - - execute1_push1 <= '0'; - execute1_push2 <= execute1_push1; - execute1_pop1 <= '0'; - execute1_pop2 <= execute1_pop1; - - if ((execute1_push1 and execute1_push2)='1') then - memAWrite <= execute2_topOfStack; - else - memAWrite <= execute2_topOfStackB; - end if; - - -- resync #7 - case execute1_decodedOpcode is - when Decoded_Neqbranch | Decoded_MoveDown3 | Decoded_Load | Decoded_Loadb | Decoded_Store | Decoded_Storeb | Decoded_Emulate | Decoded_PopSP | Decoded_PopPC| Decoded_Callpcrel => - execute1_stall <= '1'; - when others => - -- nothing... - end case; - - execute1_antialias <= load_stall; - execute1_doFetch := false; - case execute1_decodedOpcode is - when Decoded_PushSP | Decoded_Emulate => - execute1_sp <= execute1_sp - 1; - execute1_push1 <= '1'; - execute1_doFetch := true; - when Decoded_Duplicate3 => - memAWriteEnable <= ((execute1_push1 and execute1_push2) or - (execute1_push1 and not execute1_pop2) or - (execute1_push2 and not execute1_pop1)) and - (not execute1_antialias and not execute1_stall); - memAAddr <= execute1_sp + 2; - execute1_sp <= execute1_sp - 1; - execute1_push1 <= '1'; - when Decoded_Im | Decoded_Duplicate | Decoded_Duplicate2 => - execute1_sp <= execute1_sp - 1; - execute1_push1 <= '1'; - execute1_doFetch := true; - when Decoded_LoadSP => - memAAddr <= execute1_sp+execute1_spOffset; - execute1_sp <= execute1_sp - 1; - execute1_push1 <= '1'; - when Decoded_AddSP => - memAAddr <= execute1_sp+execute1_spOffset; - when Decoded_MoveDown2 => - execute1_sp <= execute1_sp + 1; - execute1_pop1 <= '1'; - execute1_doFetch := true; - when Decoded_Ulessthan | Decoded_Lessthan | Decoded_Eq | Decoded_Neqbranch | Decoded_MoveDown3 | Decoded_MoveDown | Decoded_Add | Decoded_Sub | Decoded_Or | Decoded_And | Decoded_PopPC | Decoded_StoreSP => - -- be afraid :-) - memAWriteEnable <= ((execute1_push1 and execute1_push2) or - (execute1_push1 and not execute1_pop2) or - (execute1_push2 and not execute1_pop1)) and - (not execute1_antialias and not execute1_stall); - memAAddr <= execute1_sp + 2; - execute1_sp <= execute1_sp + 1; - execute1_pop1 <= '1'; - when others => - execute1_doFetch := true; - end case; - - if execute1_doFetch then - -- resync #2 - -- some instruction that does not change the stack pointer - -- and does not need use a memory operand. - -- We can fetch the next word to be decoded to avoid stalls - execute1_fetchPC <= execute1_fetchPC+1; - memAAddr <= execute1_fetchPC(maxAddrBit downto minAddrBit); - execute1_fetchedPC <= execute1_fetchPC; - execute1_fetched <= '1'; - end if; - - - -- stage 3: fetching memory takes 1 cycle - -- here we also verify that we've fetched & decoded the right - -- opcode. - -- resync #8 - load_decodedOpcode <= execute1_decodedOpcode; - load_opcode <= execute1_opcode; - load_spOffset <= execute1_spOffset; - load_stall <= execute1_stall; - -- resync #9 - if (load_stall = '1') then - execute2_decodedOpcode <= Decoded_Stall; - else - execute2_decodedOpcode <= load_decodedOpcode; - end if; - execute2_opcode <= load_opcode; - execute2_spOffset <= load_spOffset; - - -- stage 4: execute 2 - we now have both operands. This is the - -- main execute stage... - begin_inst <= '1'; - trace_pc <= execute2_pc; - trace_opcode <= execute2_opcode; - trace_sp <= execute2_sp; - trace_topOfStack <= execute2_topOfStack; - trace_topOfStackB <= execute2_topOfStackB; - - execute2_pc <= execute2_pc + 1; - execute2_loading <= '0'; - memBWriteEnable <= '0'; - - case execute2_decodedOpcode is - when Decoded_PopSP => - execute2_sp <= execute2_topOfStack(maxAddrBit downto minAddrBit); - - memBWriteEnable <= '1'; - memBAddr <= execute2_sp + 1; - memBWrite <= execute2_topOfStackB; - execute2_resync <= '1'; - when Decoded_Callpcrel => - execute2_topOfStack <= (others => DontCareValue); - execute2_topOfStack(maxAddrBit downto 0) <= execute2_pc + 1; - execute2_pc <= execute2_pc + execute2_topOfStack(maxAddrBit downto 0); - execute2_persistTopOfStack <= '1'; - when Decoded_PopPC => - execute2_pc <= execute2_topOfStack(maxAddrBit downto 0); - execute2_sp <= execute2_sp + 1; - - memBWriteEnable <= '1'; - memBAddr <= execute2_sp + 1; - memBWrite <= execute2_topOfStackB; - execute2_resync <= '1'; - when Decoded_Emulate => - execute2_sp <= execute2_sp - 1; - - execute2_topOfStack <= (others => DontCareValue); - execute2_topOfStack(maxAddrBit downto 0) <= execute2_pc + 1; - execute2_topOfStackB <= execute2_topOfStack; - - memBWriteEnable <= '1'; - memBAddr <= execute2_sp+1; - memBWrite <= execute2_topOfStackB; - -- The emulate address is: - -- 98 7654 3210 - -- 0000 00aa aaa0 0000 - execute2_pc <= (others => '0'); - execute2_pc(9 downto 5) <= execute2_opcode(4 downto 0); - execute2_persistTopOfStack <= '1'; - when Decoded_Im => - execute2_sp <= execute2_sp - 1; - for i in wordSize-1 downto 7 loop - execute2_topOfStack(i) <= execute2_opcode(6); - end loop; - execute2_topOfStack(6 downto 0) <= execute2_opcode(6 downto 0); - - execute2_topOfStackB <= execute2_topOfStack; - memBWriteEnable <= '1'; - memBAddr <= execute2_sp + 1; - memBWrite <= execute2_topOfStackB; - when Decoded_ImShift => - execute2_topOfStack(wordSize-1 downto 7) <= execute2_topOfStack(wordSize-8 downto 0); - execute2_topOfStack(6 downto 0) <= execute2_opcode(6 downto 0); - when Decoded_LoadSP => - execute2_sp <= execute2_sp - 1; - execute2_topOfStack <= memARead; - execute2_topOfStackB <= execute2_topOfStack; - memBWriteEnable <= '1'; - memBAddr <= execute2_sp + 1; - memBWrite <= execute2_topOfStackB; - when Decoded_Break => - report "Break instruction encountered" severity failure; - break <= '1'; - when Decoded_PushSP => - execute2_topOfStack <= (others => DontCareValue); - execute2_topOfStack(maxAddrBit downto minAddrBit) <= execute2_sp; - - execute2_sp <= execute2_sp - 1; - execute2_topOfStackB <= execute2_topOfStack; - memBWriteEnable <= '1'; - memBAddr <= execute2_sp + 1; - memBWrite <= execute2_topOfStackB; - when Decoded_Add => - execute2_sp <= execute2_sp + 1; - execute2_topOfStack <= execute2_topOfStackB + execute2_topOfStack; - execute2_topOfStackB <= memARead; - when Decoded_Sub => - execute2_sp <= execute2_sp + 1; - execute2_topOfStack <= execute2_topOfStackB - execute2_topOfStack; - execute2_topOfStackB <= memARead; - when Decoded_AddSP => - execute2_topOfStack <= execute2_topOfStack + memARead; - when Decoded_Or => - execute2_sp <= execute2_sp + 1; - execute2_topOfStack <= execute2_topOfStackB or execute2_topOfStack; - execute2_topOfStackB <= memARead; - when Decoded_And => - execute2_sp <= execute2_sp + 1; - execute2_topOfStack <= execute2_topOfStackB and execute2_topOfStack; - execute2_topOfStackB <= memARead; - when Decoded_Load | Decoded_Loadb | Decoded_Storeb => - if (execute2_topOfStack(ioBit)='1') then - io_addr <= execute2_topOfStack(maxAddrBit downto minAddrBit); - io_readEnable <= '1'; - else - memAAddr <= execute2_topOfStack(maxAddrBit downto minAddrBit); - execute1_fetched <= '0'; - end if; - if (execute2_decodedOpcode = Decoded_Loadb) then - execute2_loadByte <= '1'; - else - execute2_loadByte <= '0'; - end if; - if (execute2_decodedOpcode = Decoded_Storeb) then - execute2_storeByte <= '1'; - else - execute2_storebyte <= '0'; - end if; - execute2_loading <= '1'; - when Decoded_Ashiftleft => - execute2_topOfStack(wordSize-1 downto 1) <= execute2_topOfStack(wordSize-2 downto 0); - execute2_topOfStack(0) <= '0'; - when Decoded_MoveDown => - execute2_sp <= execute2_sp + 1; - execute2_topOfStackB <= memARead; - when Decoded_MoveDown2 => - execute2_sp <= execute2_sp + 1; - execute2_topOfStack <= execute2_topOfStackB; - execute2_topOfStackB <= execute2_topOfStack; - when Decoded_MoveDown3 => - execute2_sp <= execute2_sp + 1; - memBWriteEnable <= '1'; - memBAddr <= execute2_sp+execute2_spOffset; - memBWrite <= execute2_topOfStack; - - execute2_topOfStack <= execute2_topOfStackB; - execute2_topOfStackB <= memARead; - execute2_persistTopOfStack <= '1'; - when Decoded_Duplicate => - execute2_topOfStackB <= execute2_topOfStack; - execute2_sp <= execute2_sp - 1; - memBWriteEnable <= '1'; - memBAddr <= execute2_sp + 1; - memBWrite <= execute2_topOfStackB; - when Decoded_Duplicate2 => - execute2_topOfStack <= execute2_topOfStackB; - execute2_topOfStackB <= execute2_topOfStack; - execute2_sp <= execute2_sp - 1; - memBWriteEnable <= '1'; - memBAddr <= execute2_sp + 1; - memBWrite <= execute2_topOfStackB; - when Decoded_Duplicate3 => - execute2_topOfStack <= memARead; - execute2_topOfStackB <= execute2_topOfStack; - execute2_sp <= execute2_sp - 1; - memBWriteEnable <= '1'; - memBAddr <= execute2_sp + 1; - memBWrite <= execute2_topOfStackB; - when Decoded_Pushspadd => - execute2_topOfStack <= (others => DontCareValue); - execute2_topOfStack(maxAddrBit downto minAddrBit) <= execute2_sp + execute2_topOfStack(maxAddrBit-minAddrBit downto 0); - when Decoded_Not => - execute2_topOfStack <= not execute2_topOfStack; - when Decoded_Flip => - for i in 0 to wordSize-1 loop - execute2_topOfStack(i) <= execute2_topOfStack(wordSize-1-i); - end loop; - when Decoded_Store => - execute2_sp <= execute2_sp + 2; - if (execute2_topOfStack(ioBit)='0') then - memBAddr <= execute2_topOfStack(maxAddrBit downto minAddrBit); - memBWrite <= execute2_topOfStackB; - memBWriteEnable <= '1'; - else - io_addr <= execute2_topOfStack(maxAddrBit downto minAddrBit); - io_write <= execute2_topOfStackB(7 downto 0); - io_writeEnable <= '1'; - end if; - execute2_resync <= '1'; - when Decoded_StoreSP => - execute2_sp <= execute2_sp + 1; - memBWriteEnable <= '1'; - memBAddr <= execute2_sp+execute2_spOffset; - memBWrite <= execute2_topOfStack; - - execute2_topOfStack <= execute2_topOfStackB; - execute2_topOfStackB <= memARead; - when Decoded_Neqbranch => - execute2_sp <= execute2_sp + 2; - if (execute2_topOfStackB/=0) then - execute2_pc <= execute2_topOfStack(maxAddrBit downto 0) + execute2_pc; - end if; - execute2_resync <= '1'; - when Decoded_Eq => - execute2_sp <= execute2_sp + 1; - execute2_topOfStack <= (others => '0'); - if (execute2_topOfStack=execute2_topOfStackB) then - execute2_topOfStack(0) <= '1'; - end if; - execute2_topOfStackB <= memARead; - when Decoded_Ulessthan => - execute2_sp <= execute2_sp + 1; - execute2_topOfStack <= (others => '0'); - if (execute2_topOfStack<execute2_topOfStackB) then - execute2_topOfStack(0) <= '1'; - end if; - execute2_topOfStackB <= memARead; - when Decoded_Lessthan => - execute2_sp <= execute2_sp + 1; - execute2_topOfStack <= (others => '0'); - compareA := signed(execute2_topOfStack); - compareB := signed(execute2_topOfStackB); - if (compareA<compareB) then - execute2_topOfStack(0) <= '1'; - end if; - execute2_topOfStackB <= memARead; - when Decoded_Stall => - begin_inst <= '0'; - execute2_pc <= execute2_pc; - when others => - -- nop - end case; - - -- load cycle... - execute2_loadingDone <= execute2_loading; - if (execute2_loadingDone ='1') then - if (execute2_topOfStack(ioBit)='1') then - if (io_busy = '0') then - execute2_topOfStack <= (others => '0'); - execute2_topOfStack(7 downto 0) <= io_read; - execute2_persistTopOfStack <= '1'; - else - execute2_loadingDone <= '1'; - end if; - else - if (execute2_storeByte = '1') then - execute2_sp <= execute2_sp + 2; - memBWriteEnable <= '1'; - memBAddr <= execute2_topOfStack(maxAddrBit downto minAddrBit); - memBWrite <= memARead; - case execute2_topOfStack(minAddrBit-1 downto 0) is - when "00" => memBWrite(31 downto 24) <= execute2_topOfStackB(7 downto 0); - when "01" => memBWrite(23 downto 16) <= execute2_topOfStackB(7 downto 0); - when "10" => memBWrite(15 downto 8) <= execute2_topOfStackB(7 downto 0); - when others => memBWrite(7 downto 0) <= execute2_topOfStackB(7 downto 0); - end case; --- case execute2_topOfStack(0 downto 0) is --- when "1" => memBWrite(15 downto 8) <= execute2_topOfStackB(7 downto 0); --- when others => memBWrite(7 downto 0) <= execute2_topOfStackB(7 downto 0); --- end case; - execute2_resync <= '1'; - elsif (execute2_loadByte = '1') then - execute2_topOfStack <= (others => '0'); - case execute2_topOfStack(minAddrBit-1 downto 0) is - when "00" => execute2_topOfStack(7 downto 0) <= memARead(31 downto 24); - when "01" => execute2_topOfStack(7 downto 0) <= memARead(23 downto 16); - when "10" => execute2_topOfStack(7 downto 0) <= memARead(15 downto 8); - when others => execute2_topOfStack(7 downto 0) <= memARead(7 downto 0); - end case; --- case execute2_topOfStack(0 downto 0) is --- when "1" => execute2_topOfStack(7 downto 0) <= memARead(15 downto 8); --- when others => execute2_topOfStack(7 downto 0) <= memARead(7 downto 0); --- end case; - execute2_persistTopOfStack <= '1'; - else - execute2_topOfStack <= memARead; - execute2_persistTopOfStack <= '1'; - end if; - end if; - end if; - - -- write top of stack... - execute2_persistTopOfStackB <= execute2_persistTopOfStack; - if (execute2_persistTopOfStack = '1') then - execute2_persistTopOfStack <= '0'; - memBWriteEnable <= '1'; - memBAddr <= execute2_sp; - memBWrite <= execute2_topOfStack; - end if; - if (execute2_persistTopOfStackB = '1') then - memBWriteEnable <= '1'; - memBAddr <= execute2_sp+1; - memBWrite <= execute2_topOfStackB; - - execute2_resync <= '1'; - end if; - - -- here we resync the pipeline. - -- a number of things have to happen on certain cycles - execute2_resync2 <= execute2_resync; - execute2_resync3 <= execute2_resync2; - execute2_resync4 <= execute2_resync3; - execute2_resync5 <= execute2_resync4; - execute2_resync6 <= execute2_resync5; - execute2_resync7 <= execute2_resync6; - execute2_resync8 <= execute2_resync7; - execute2_resync9 <= execute2_resync8; - execute2_resync10 <= execute2_resync9; - - if (execute2_resync = '1' ) then - -- resync #1 - execute2_resync <= '0'; - decode_starved <= '1'; - memAAddr <= execute2_sp; - end if; - if (execute2_resync2 = '1') then - -- resync #2 - execute1_fetchPC <= execute2_pc; - memAAddr <= execute2_sp + 1; - end if; - if (execute2_resync3 = '1') then - -- resync #3 - execute2_topOfStack <= memARead; - end if; - if (execute2_resync4 = '1') then - -- resync #4 - -- during this cycle the address is set to the opcode - execute2_topOfStackB <= memARead; - end if; - if (execute2_resync5 = '1') then - -- resync #5 - execute1_pop1 <= '0'; - execute1_push1 <= '0'; - end if; - if (execute2_resync6 = '1') then - -- resync #6 - decode_idim_flag <= '0'; - execute1_pop1 <= '0'; - execute1_push1 <= '0'; - end if; - if (execute2_resync7 = '1') then - -- resync #7 - execute1_sp <= execute2_sp; - execute1_stall <= '0'; - end if; - if (execute2_resync8 = '1') then - -- resync #8 --- load_stall <= '0'; - end if; - if (execute2_resync9 = '1') then - -- resync #9 - end if; - if (execute2_resync10 = '1') then - end if; - - - - - end if; - end process; - - - -end behave; diff --git a/zpu/hdl/zpu3/src/zpu_top.vhd b/zpu/hdl/zpu3/src/zpu_top.vhd deleted file mode 100644 index 0ac6df4..0000000 --- a/zpu/hdl/zpu3/src/zpu_top.vhd +++ /dev/null @@ -1,421 +0,0 @@ --- Company: ZPU3 --- Engineer: Øyvind Harboe - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library zylin; -use zylin.zpu_config.all; -use zylin.zpupkg.all; - - -entity zpu_top is - Port ( clk : in std_logic; - areset : in std_logic; - io_busy : in std_logic; - io_read : in std_logic_vector(7 downto 0); - io_write : out std_logic_vector(7 downto 0); - io_addr : out std_logic_vector(maxAddrBit downto minAddrBit); - io_writeEnable : out std_logic; - io_readEnable : out std_logic; - interrupt : in std_logic; - break : out std_logic); -end zpu_top; - -architecture behave of zpu_top is - -signal readIO : std_logic; - - - -signal memAWriteEnable : std_logic; -signal memAAddr : std_logic_vector(maxAddrBit downto minAddrBit); -signal memAWrite : std_logic_vector(wordSize-1 downto 0); -signal memARead : std_logic_vector(wordSize-1 downto 0); -signal memBWriteEnable : std_logic; -signal memBAddr : std_logic_vector(maxAddrBit downto minAddrBit); -signal memBWrite : std_logic_vector(wordSize-1 downto 0); -signal memBRead : std_logic_vector(wordSize-1 downto 0); - - - -signal pc : std_logic_vector(maxAddrBit downto 0); -signal sp : std_logic_vector(maxAddrBit downto minAddrBit); - -signal idim_flag : std_logic; - ---signal storeToStack : std_logic; ---signal fetchNextInstruction : std_logic; ---signal extraCycle : std_logic; -signal busy : std_logic; ---signal fetching : std_logic; - -signal begin_inst : std_logic; - - - -signal trace_opcode : std_logic_vector(7 downto 0); -signal trace_pc : std_logic_vector(maxAddrBit downto 0); -signal trace_sp : std_logic_vector(maxAddrBit downto minAddrBit); -signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); -signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); - --- state machine. - -subtype State_Type is std_logic_vector(3 downto 0); -constant State_Fetch : State_Type := b"0000"; -constant State_WriteIODone : State_Type := b"0001"; -constant State_Execute : State_Type := b"0010"; -constant State_StoreToStack : State_Type := b"0011"; -constant State_Add : State_Type := b"0100"; -constant State_Or : State_Type := b"0101"; -constant State_And : State_Type := b"0110"; -constant State_Store : State_Type := b"0111"; -constant State_ReadIO : State_Type := b"1000"; -constant State_WriteIO : State_Type := b"1001"; -constant State_Load : State_Type := b"1010"; -constant State_FetchNext : State_Type := b"1011"; -constant State_AddSP : State_Type := b"1100"; -constant State_ReadIODone : State_Type := b"1101"; -constant State_Decode : State_Type := b"1110"; -constant State_Resync : State_Type := b"1111"; - - -subtype DecodedOpcodeType is std_logic_vector(4 downto 0); -constant Decoded_Nop : DecodedOpcodeType := b"00000"; -constant Decoded_Im : DecodedOpcodeType := b"00001"; -constant Decoded_ImShift : DecodedOpcodeType := b"00010"; -constant Decoded_LoadSP : DecodedOpcodeType := b"00011"; -constant Decoded_StoreSP : DecodedOpcodeType := b"00100"; -constant Decoded_AddSP : DecodedOpcodeType := b"00101"; -constant Decoded_Emulate : DecodedOpcodeType := b"00110"; -constant Decoded_Break : DecodedOpcodeType := b"00111"; -constant Decoded_PushPC : DecodedOpcodeType := b"01000"; -constant Decoded_PushSP : DecodedOpcodeType := b"01001"; -constant Decoded_PopPC : DecodedOpcodeType := b"01010"; -constant Decoded_Add : DecodedOpcodeType := b"01011"; -constant Decoded_Or : DecodedOpcodeType := b"01100"; -constant Decoded_And : DecodedOpcodeType := b"01101"; -constant Decoded_Load : DecodedOpcodeType := b"01110"; -constant Decoded_Not : DecodedOpcodeType := b"01111"; -constant Decoded_Flip : DecodedOpcodeType := b"10000"; -constant Decoded_Store : DecodedOpcodeType := b"10001"; -constant Decoded_PopSP : DecodedOpcodeType := b"10010"; - -signal opcode : std_logic_vector(OpCode_Size-1 downto 0); - -signal decodedOpcode : DecodedOpcodeType; - -signal state : State_Type; - -begin - traceFileGenerate: - if Generate_Trace generate - trace_file: trace port map ( - clk => clk, - begin_inst => begin_inst, - pc => trace_pc, - opcode => trace_opcode, - sp => trace_sp, - memA => trace_topOfStack, - memB => trace_topOfStackB, - busy => busy - ); - end generate; - - - memory: dualport_ram port map ( - clk => clk, - memAWriteEnable => memAWriteEnable, - memAAddr => memAAddr, - memAWrite => memAWrite, - memARead => memARead, - memBWriteEnable => memBWriteEnable, - memBAddr => memBAddr, - memBWrite => memBWrite, - memBRead => memBRead - ); - - - - - opcodeControl: - process(clk, areset) - variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); - variable spOffset : std_logic_vector(4 downto 0); - begin - if areset = '1' then - state <= State_Resync; - break <= '0'; - sp <= (2 => '0', others => '1'); - pc <= (others => '0'); - idim_flag <= '0'; - begin_inst <= '0'; - memAAddr <= (others => '0'); - memBAddr <= (others => '0'); - memAWriteEnable <= '0'; - memBWriteEnable <= '0'; - io_writeEnable <= '0'; - io_readEnable <= '0'; - decodedOpcode <= (others => '0'); - memAWrite <= (others => '0'); - memBWrite <= (others => '0'); - opcode <= (others => '0'); - io_addr <= (others => '0'); - io_write <= (others => '0'); - elsif (clk'event and clk = '1') then - memAWriteEnable <= '0'; - memBWriteEnable <= '0'; - -- This saves ca. 100 LUT's, by explicitly declaring that the - -- memAWrite can be left at whatever value if memAWriteEnable is - -- not set. - memAWrite <= (others => DontCareValue); - memBWrite <= (others => DontCareValue); - opcode <= (others => DontCareValue); --- io_addr <= (others => DontCareValue); --- io_write <= (others => DontCareValue); - spOffset := (others => DontCareValue); - memAAddr <= (others => DontCareValue); - memBAddr <= (others => DontCareValue); - - io_writeEnable <= '0'; - io_readEnable <= '0'; - begin_inst <= '0'; - - case state is - when State_Execute => - state <= State_Fetch; - -- at this point: - -- memBRead contains opcode word - -- memARead contains top of stack - pc <= pc + 1; - - -- trace - begin_inst <= '1'; - trace_pc <= pc; - trace_opcode <= opcode; - trace_sp <= sp; - trace_topOfStack <= memARead; - trace_topOfStackB <= memBRead; - - -- during the next cycle we'll be reading the next opcode - spOffset(4):=not opcode(4); - spOffset(3 downto 0):=opcode(3 downto 0); - - case decodedOpcode is - when Decoded_Im => - memAWriteEnable <= '1'; - sp <= sp - 1; - memAAddr <= sp-1; - for i in wordSize-1 downto 7 loop - memAWrite(i) <= opcode(6); - end loop; - memAWrite(6 downto 0) <= opcode(6 downto 0); - when Decoded_ImShift => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0); - memAWrite(6 downto 0) <= opcode(6 downto 0); - when Decoded_StoreSP => - memBWriteEnable <= '1'; - memBAddr <= sp+spOffset; - memBWrite <= memARead; - sp <= sp + 1; - state <= State_Resync; - when Decoded_LoadSP => - sp <= sp - 1; - memAAddr <= sp+spOffset; - when Decoded_Emulate => - sp <= sp - 1; - memAWriteEnable <= '1'; - memAAddr <= sp - 1; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto 0) <= pc + 1; - -- The emulate address is: - -- 98 7654 3210 - -- 0000 00aa aaa0 0000 - pc <= (others => '0'); - pc(9 downto 5) <= opcode(4 downto 0); - when Decoded_AddSP => - memAAddr <= sp; - memBAddr <= sp+spOffset; - state <= State_AddSP; - when Decoded_Break => - report "Break instruction encountered" severity failure; - break <= '1'; - when Decoded_PushSP => - memAWriteEnable <= '1'; - memAAddr <= sp - 1; - sp <= sp - 1; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto minAddrBit) <= sp; - when Decoded_PopPC => - pc <= memARead(maxAddrBit downto 0); - sp <= sp + 1; - state <= State_Resync; - when Decoded_Add => - sp <= sp + 1; - state <= State_Add; - when Decoded_Or => - sp <= sp + 1; - state <= State_Or; - when Decoded_And => - sp <= sp + 1; - state <= State_And; - when Decoded_Load => - if (memARead(ioBit)='1') then - io_addr <= memARead(maxAddrBit downto minAddrBit); - io_readEnable <= '1'; - state <= State_ReadIO; - else - memAAddr <= memARead(maxAddrBit downto minAddrBit); - end if; - when Decoded_Not => - memAAddr <= sp(maxAddrBit downto minAddrBit); - memAWriteEnable <= '1'; - memAWrite <= not memARead; - when Decoded_Flip => - memAAddr <= sp(maxAddrBit downto minAddrBit); - memAWriteEnable <= '1'; - for i in 0 to wordSize-1 loop - memAWrite(i) <= memARead(wordSize-1-i); - end loop; - when Decoded_Store => - memBAddr <= sp + 1; - sp <= sp + 1; - if (memARead(ioBit)='1') then - state <= State_WriteIO; - else - state <= State_Store; - end if; - when Decoded_PopSP => - sp <= memARead(maxAddrBit downto minAddrBit); - state <= State_Resync; - when Decoded_Nop => - memAAddr <= sp; - when others => - null; - end case; - when State_ReadIO => - if (io_busy = '0') then - state <= State_Fetch; - memAWriteEnable <= '1'; - memAWrite <= (others => '0'); - memAWrite(7 downto 0) <= io_read; - end if; - when State_WriteIO => - sp <= sp + 1; - io_writeEnable <= '1'; - io_addr <= memARead(maxAddrBit downto minAddrBit); - io_write <= memBRead(7 downto 0); - state <= State_WriteIODone; - when State_WriteIODone => - if (io_busy = '0') then - state <= State_Resync; - end if; - when State_Fetch => - -- We need to resync. During the *next* cycle - -- we'll fetch the opcode @ pc and thus it will - -- be available for State_Execute the cycle after - -- next - memBAddr <= pc(maxAddrBit downto minAddrBit); - state <= State_FetchNext; - when State_FetchNext => - -- at this point memARead contains the value that is either - -- from the top of stack or should be copied to the top of the stack - memAWriteEnable <= '1'; - memAWrite <= memARead; - memAAddr <= sp; - memBAddr <= sp + 1; - state <= State_Decode; - when State_Decode => - case pc(1 downto 0) is - when "00" => tOpcode := memBRead(31 downto 24); - when "01" => tOpcode := memBRead(23 downto 16); - when "10" => tOpcode := memBRead(15 downto 8); - when others => tOpcode := memBRead(7 downto 0); - end case; - idim_flag <= tOpcode(7); - opcode <= tOpcode; - if (tOpcode(7 downto 7)=OpCode_Im) then - if (idim_flag='1') then - decodedOpcode<=Decoded_ImShift; - else - decodedOpcode<=Decoded_Im; - end if; - elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then - decodedOpcode<=Decoded_StoreSP; - elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then - decodedOpcode<=Decoded_LoadSP; - elsif (tOpcode(7 downto 5)=OpCode_Emulate) then - decodedOpcode<=Decoded_Emulate; - elsif (tOpcode(7 downto 4)=OpCode_AddSP) then - decodedOpcode<=Decoded_AddSP; - else - case tOpcode(3 downto 0) is - when OpCode_Break => - decodedOpcode<=Decoded_Break; - when OpCode_PushSP => - decodedOpcode<=Decoded_PushSP; - when OpCode_PopPC => - decodedOpcode<=Decoded_PopPC; - when OpCode_Add => - decodedOpcode<=Decoded_Add; - when OpCode_Or => - decodedOpcode<=Decoded_Or; - when OpCode_And => - decodedOpcode<=Decoded_And; - when OpCode_Load => - decodedOpcode<=Decoded_Load; - when OpCode_Not => - decodedOpcode<=Decoded_Not; - when OpCode_Flip => - decodedOpcode<=Decoded_Flip; - when OpCode_Store => - decodedOpcode<=Decoded_Store; - when OpCode_PopSP => - decodedOpcode<=Decoded_PopSP; - when others => - decodedOpcode<=Decoded_Nop; - end case; - end if; - -- during the State_Execute cycle we'll be fetching SP+1 - memAAddr <= sp; - memBAddr <= sp + 1; - state <= State_Execute; - when State_Store => - sp <= sp + 1; - memAWriteEnable <= '1'; - memAAddr <= memARead(maxAddrBit downto minAddrBit); - memAWrite <= memBRead; - state <= State_Resync; - when State_AddSP => - state <= State_Add; - when State_Add => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead + memBRead; - state <= State_Fetch; - when State_Or => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead or memBRead; - state <= State_Fetch; - when State_Resync => - memAAddr <= sp; - state <= State_Fetch; - when State_And => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead and memBRead; - state <= State_Fetch; - when others => - null; - end case; - end if; - end process; - - - -end behave; diff --git a/zpu/hdl/zpu3/src/zpu_top_medium.vhd b/zpu/hdl/zpu3/src/zpu_top_medium.vhd deleted file mode 100644 index 4896b30..0000000 --- a/zpu/hdl/zpu3/src/zpu_top_medium.vhd +++ /dev/null @@ -1,768 +0,0 @@ --- Company: ZPU3 --- Engineer: Øyvind Harboe - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -use IEEE.STD_LOGIC_arith.ALL; - -library zylin; -use zylin.zpu_config.all; -use zylin.zpupkg.all; - - -entity zpu_top is - Port ( clk : in std_logic; - areset : in std_logic; - io_busy : in std_logic; - io_read : in std_logic_vector(7 downto 0); - io_write : out std_logic_vector(7 downto 0); - io_addr : out std_logic_vector(maxAddrBit downto minAddrBit); - io_writeEnable : out std_logic; - io_readEnable : out std_logic; - interrupt : in std_logic; - break : out std_logic); -end zpu_top; - -architecture behave of zpu_top is - -signal readIO : std_logic; - - - -signal memAWriteEnable : std_logic; -signal memAAddr : std_logic_vector(maxAddrBit downto minAddrBit); -signal memAWrite : std_logic_vector(wordSize-1 downto 0); -signal memARead : std_logic_vector(wordSize-1 downto 0); -signal memBWriteEnable : std_logic; -signal memBAddr : std_logic_vector(maxAddrBit downto minAddrBit); -signal memBWrite : std_logic_vector(wordSize-1 downto 0); -signal memBRead : std_logic_vector(wordSize-1 downto 0); - - - -signal pc : std_logic_vector(maxAddrBit downto 0); -signal sp : std_logic_vector(maxAddrBit downto minAddrBit); - -signal idim_flag : std_logic; - ---signal storeToStack : std_logic; ---signal fetchNextInstruction : std_logic; ---signal extraCycle : std_logic; -signal busy : std_logic; ---signal fetching : std_logic; - -signal begin_inst : std_logic; - - - -signal trace_opcode : std_logic_vector(7 downto 0); -signal trace_pc : std_logic_vector(maxAddrBit downto 0); -signal trace_sp : std_logic_vector(maxAddrBit downto minAddrBit); -signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); - --- state machine. - -subtype State_Type is std_logic_vector(4 downto 0); -constant State_ResyncDecode : State_Type := b"00000"; -constant State_WriteIODone : State_Type := b"00001"; -constant State_Execute : State_Type := b"00010"; -constant State_StoreToStack : State_Type := b"00011"; -constant State_Add : State_Type := b"00100"; -constant State_Or : State_Type := b"00101"; -constant State_And : State_Type := b"00110"; -constant State_Store : State_Type := b"00111"; -constant State_ReadIO : State_Type := b"01000"; -constant State_WriteIO : State_Type := b"01001"; -constant State_Load : State_Type := b"01010"; -constant State_ResyncStack : State_Type := b"01011"; -constant State_AddSP : State_Type := b"01100"; -constant State_ReadIODone : State_Type := b"01101"; -constant State_Decode : State_Type := b"01110"; -constant State_LoadByte1 : State_Type := b"01111"; -constant State_LoadByte2 : State_Type := b"10000"; -constant State_StoreByte1 : State_Type := b"10001"; -constant State_StoreByte2 : State_Type := b"10010"; -constant State_Mult1 : State_Type := b"10011"; -constant State_Mult2 : State_Type := b"10100"; -constant State_Mult3 : State_Type := b"10101"; - - -subtype DecodedOpcodeType is std_logic_vector(5 downto 0); -constant Decoded_Nop : DecodedOpcodeType := b"000000"; -constant Decoded_Im : DecodedOpcodeType := b"000001"; -constant Decoded_ImShift : DecodedOpcodeType := b"000010"; -constant Decoded_LoadSP : DecodedOpcodeType := b"000011"; -constant Decoded_StoreSP : DecodedOpcodeType := b"000100"; -constant Decoded_AddSP : DecodedOpcodeType := b"000101"; -constant Decoded_Emulate : DecodedOpcodeType := b"000110"; -constant Decoded_Break : DecodedOpcodeType := b"000111"; -constant Decoded_PushPC : DecodedOpcodeType := b"001000"; -constant Decoded_PushSP : DecodedOpcodeType := b"001001"; -constant Decoded_PopPC : DecodedOpcodeType := b"001010"; -constant Decoded_Add : DecodedOpcodeType := b"001011"; -constant Decoded_Or : DecodedOpcodeType := b"001100"; -constant Decoded_And : DecodedOpcodeType := b"001101"; -constant Decoded_Load : DecodedOpcodeType := b"001110"; -constant Decoded_Not : DecodedOpcodeType := b"001111"; -constant Decoded_Flip : DecodedOpcodeType := b"010000"; -constant Decoded_Store : DecodedOpcodeType := b"010001"; -constant Decoded_PopSP : DecodedOpcodeType := b"010010"; -constant Decoded_Ashiftleft : DecodedOpcodeType := b"010011"; -constant Decoded_Ashiftright : DecodedOpcodeType := b"010100"; -constant Decoded_Lshiftright : DecodedOpcodeType := b"010101"; -constant Decoded_Eqbranch : DecodedOpcodeType := b"010110"; -constant Decoded_Neqbranch : DecodedOpcodeType := b"010111"; -constant Decoded_Eq : DecodedOpcodeType := b"011000"; -constant Decoded_Neq : DecodedOpcodeType := b"011001"; -constant Decoded_Loadb : DecodedOpcodeType := b"011010"; -constant Decoded_Lessthan : DecodedOpcodeType := b"011011"; -constant Decoded_Lessthanorequal : DecodedOpcodeType := b"011100"; -constant Decoded_Ulessthan : DecodedOpcodeType := b"011101"; -constant Decoded_Ulessthanorequal : DecodedOpcodeType := b"011110"; -constant Decoded_Storeb : DecodedOpcodeType := b"011111"; -constant Decoded_Lshift2 : DecodedOpcodeType := b"100000"; -constant Decoded_DoubleIm : DecodedOpcodeType := b"100001"; -constant Decoded_AddIm : DecodedOpcodeType := b"100011"; -constant Decoded_Mult16x16 : DecodedOpcodeType := b"100100"; -constant Decoded_Swap : DecodedOpcodeType := b"100101"; -constant Decoded_Callpcrel : DecodedOpcodeType := b"100110"; -constant Decoded_Pushspadd : DecodedOpcodeType := b"100111"; - - -signal mult1 : std_logic_vector(wordSize/2-1 downto 0); -signal mult2 : std_logic_vector(wordSize/2-1 downto 0); -signal multResult : std_logic_vector(wordSize-1 downto 0); - -signal storeByte : std_logic_vector(7 downto 0); -signal byteSelect : std_logic_vector(minAddrBit-1 downto 0); - -signal opcode : std_logic_vector(OpCode_Size-1 downto 0); -signal opcode2 : std_logic_vector(OpCode_Size-1 downto 0); - -signal decodedOpcode : DecodedOpcodeType; - -signal state : State_Type; - -begin - traceFileGenerate: - if Generate_Trace generate - trace_file: trace port map ( - clk => clk, - begin_inst => begin_inst, - pc => trace_pc, - opcode => trace_opcode, - sp => trace_sp, - memA => trace_topOfStack, - busy => busy - ); - end generate; - - - memory: dualport_ram port map ( - clk => clk, - memAWriteEnable => memAWriteEnable, - memAAddr => memAAddr, - memAWrite => memAWrite, - memARead => memARead, - memBWriteEnable => memBWriteEnable, - memBAddr => memBAddr, - memBWrite => memBWrite, - memBRead => memBRead - ); - - - process(clk, areset) - begin - if (clk'event and clk = '1') then - multResult <= mult1 * mult2; - end if; - end process; - - - - opcodeControl: - process(clk, areset) - variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); - variable tOpcode2 : std_logic_vector(OpCode_Size-1 downto 0); - variable spOffset : std_logic_vector(4 downto 0); - variable spOffset2 : std_logic_vector(4 downto 0); - variable nextPC : std_logic_vector(maxAddrBit downto 0); - variable pushspaddTemp : std_logic_vector(maxAddrBit downto minAddrBit); - variable tempVal : std_logic_vector(wordSize-1 downto 0); - variable compareA : signed(wordSize-1 downto 0); - variable compareB : signed(wordSize-1 downto 0); - begin - if areset = '1' then - mult1 <= (others => '0'); - mult2 <= (others => '0'); - state <= State_ResyncDecode; - break <= '0'; - sp <= (2 => '0', others => '1'); - pc <= (others => '0'); - idim_flag <= '0'; - begin_inst <= '0'; - memAAddr <= (others => '0'); - memBAddr <= (others => '0'); - memAWriteEnable <= '0'; - memBWriteEnable <= '0'; - io_writeEnable <= '0'; - io_readEnable <= '0'; - decodedOpcode <= (others => '0'); - memAWrite <= (others => '0'); - memBWrite <= (others => '0'); - opcode <= (others => '0'); - io_addr <= (others => '0'); - io_write <= (others => '0'); - elsif (clk'event and clk = '1') then - memAWriteEnable <= '0'; - memBWriteEnable <= '0'; - - io_writeEnable <= '0'; - io_readEnable <= '0'; - begin_inst <= '0'; - - case state is - when State_Decode => - nextPC:=pc+1; - case pc(1 downto 0) is - when "00" => tOpcode := memARead(31 downto 24); - when "01" => tOpcode := memARead(23 downto 16); - when "10" => tOpcode := memARead(15 downto 8); - when others => tOpcode := memARead(7 downto 0); - end case; - case nextPC(1 downto 0) is - when "00" => tOpcode2 := memBRead(31 downto 24); - when "01" => tOpcode2 := memBRead(23 downto 16); - when "10" => tOpcode2 := memBRead(15 downto 8); - when others => tOpcode2 := memBRead(7 downto 0); - end case; - idim_flag <= tOpcode(7); - opcode <= tOpcode; - opcode2 <= tOpcode2; - if (tOpcode(7 downto 7)=OpCode_Im and tOpcode2(7 downto 4)=0 and tOpcode2(3 downto 0)=Opcode_Add and idim_flag='0') then - idim_flag <= '0'; - decodedOpcode <= Decoded_AddIm; - nextPC := pc + 2; - elsif (tOpcode(7 downto 7)=OpCode_Im and tOpcode2(7 downto 7)=OpCode_Im and idim_flag='0') then - decodedOpcode <= Decoded_DoubleIm; - nextPC := pc + 2; - elsif (tOpcode(7 downto 4)=OpCode_AddSP and tOpcode(3 downto 0)=0 and - tOpcode2(7 downto 4)=OpCode_AddSP and tOpcode2(3 downto 0)=0) then - decodedOpcode <= Decoded_Lshift2; - nextPC := pc + 2; - elsif (tOpcode(7 downto 7)=OpCode_Im) then - if (idim_flag='1') then - decodedOpcode<=Decoded_ImShift; - else - decodedOpcode<=Decoded_Im; - end if; - elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then - decodedOpcode<=Decoded_StoreSP; - elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then - decodedOpcode<=Decoded_LoadSP; - elsif (tOpcode(7 downto 5)=OpCode_Emulate) then - if tOpcode(5 downto 0)=OpCode_Eqbranch then - decodedOpcode <= Decoded_Eqbranch; - elsif tOpcode(5 downto 0)=OpCode_Neqbranch then - decodedOpcode <= Decoded_Neqbranch; - elsif tOpcode(5 downto 0)=OpCode_Eq then - decodedOpcode <= Decoded_Eq; - elsif tOpcode(5 downto 0)=OpCode_Neq then - decodedOpcode <= Decoded_Neq; - elsif tOpcode(5 downto 0)=OpCode_Lessthan then - decodedOpcode <= Decoded_Lessthan; - elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then - decodedOpcode <= Decoded_Lessthanorequal; - elsif tOpcode(5 downto 0)=OpCode_Ulessthan then - decodedOpcode <= Decoded_Ulessthan; - elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then - decodedOpcode <= Decoded_Ulessthanorequal; - elsif tOpcode(5 downto 0)=OpCode_Loadb then - decodedOpcode <= Decoded_Loadb; - elsif tOpcode(5 downto 0)=OpCode_Storeb then - decodedOpcode <= Decoded_Storeb; - elsif tOpcode(5 downto 0)=OpCode_Mult16x16 then - decodedOpcode <= Decoded_Mult16x16; - elsif tOpcode(5 downto 0)=OpCode_Swap then - decodedOpcode <= Decoded_Swap; - elsif tOpcode(5 downto 0)=OpCode_Callpcrel then - decodedOpcode <= Decoded_Callpcrel; - elsif tOpcode(5 downto 0)=OpCode_Pushspadd then - decodedOpcode <= Decoded_Pushspadd; --- elsif tOpcode(5 downto 0)=OpCode_Lshiftright then --- decodedOpcode <= Decoded_Lshiftright; --- elsif tOpcode(5 downto 0)=OpCode_Ashiftleft then --- decodedOpcode <= Decoded_Ashiftleft; --- elsif tOpcode(5 downto 0)=OpCode_Ashiftright then --- decodedOpcode <= Decoded_Ashiftright; - else - decodedOpcode<=Decoded_Emulate; - end if; - elsif (tOpcode(7 downto 4)=OpCode_AddSP) then - decodedOpcode<=Decoded_AddSP; - else - case tOpcode(3 downto 0) is - when OpCode_Break => - decodedOpcode<=Decoded_Break; - when OpCode_PushPC => - decodedOpcode<=Decoded_PushPC; - when OpCode_PushSP => - decodedOpcode<=Decoded_PushSP; - when OpCode_PopPC => - decodedOpcode<=Decoded_PopPC; - when OpCode_Add => - decodedOpcode<=Decoded_Add; - when OpCode_Or => - decodedOpcode<=Decoded_Or; - when OpCode_And => - decodedOpcode<=Decoded_And; - when OpCode_Load => - decodedOpcode<=Decoded_Load; - when OpCode_Not => - decodedOpcode<=Decoded_Not; - when OpCode_Flip => - decodedOpcode<=Decoded_Flip; - when OpCode_Store => - decodedOpcode<=Decoded_Store; - when OpCode_PopSP => - decodedOpcode<=Decoded_PopSP; - when others => - decodedOpcode<=Decoded_Nop; - end case; - end if; - -- Fetch the two next opcodes... :-) - memAAddr <= nextPC(maxAddrBit downto minAddrBit); - nextPC:=nextPC+1; - memBAddr <= nextPC(maxAddrBit downto minAddrBit); - state <= State_Execute; - when State_Execute => - state <= State_Decode; - -- at this point: - -- memBRead contains opcode word - -- memARead contains top of stack - pc <= pc + 1; - - -- trace - begin_inst <= '1'; - trace_pc <= pc; - trace_opcode <= opcode; - trace_sp <= sp; - trace_topOfStack <= memARead; - - -- during the next cycle we'll be reading the next opcode - spOffset(4):=not opcode(4); - spOffset(3 downto 0):=opcode(3 downto 0); - spOffset2(4):=not opcode2(4); - spOffset2(3 downto 0):=opcode2(3 downto 0); - - case decodedOpcode is - - when Decoded_DoubleIm => - memAWriteEnable <= '1'; - sp <= sp - 1; - memAAddr <= sp-1; - for i in wordSize-1 downto 14 loop - memAWrite(i) <= opcode(6); - end loop; - memAWrite(13 downto 7) <= opcode(6 downto 0); - memAWrite(6 downto 0) <= opcode2(6 downto 0); - memBAddr <= sp; - memBWrite <= memARead; - memBWriteEnable <= '1'; - pc <= pc + 2; - when Decoded_Im => - memAWriteEnable <= '1'; - sp <= sp - 1; - memAAddr <= sp-1; - for i in wordSize-1 downto 7 loop - memAWrite(i) <= opcode(6); - end loop; - memAWrite(6 downto 0) <= opcode(6 downto 0); - memBAddr <= sp; - memBWrite <= memARead; - memBWriteEnable <= '1'; - when Decoded_ImShift => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0); - memAWrite(6 downto 0) <= opcode(6 downto 0); - memBAddr <= sp + 1; - when Decoded_StoreSP => - memAWriteEnable <= '1'; - memAAddr <= sp+spOffset; - memAWrite <= memARead; - -- avoid address crashes. - memBAddr <= sp - 1; - sp <= sp + 1; - state <= State_ResyncDecode; - when Decoded_LoadSP => - sp <= sp - 1; - if (spOffset = 0) then - -- This is a duplicate instruction. - memAAddr <= sp-1; - memAWriteEnable <= '1'; - memAWrite <= memARead; - else - memAAddr <= sp+spOffset; - end if; - memBAddr <= sp; - memBWrite <= memARead; - memBWriteEnable <= '1'; - when Decoded_Callpcrel => - memAWriteEnable <= '1'; - memAAddr <= sp; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto 0) <= pc + 1; - memBAddr <= sp+1; - pc <= pc + memARead(maxAddrBit downto 0); - state <= State_ResyncDecode; - when Decoded_Emulate => - sp <= sp - 1; - memAWriteEnable <= '1'; - memAAddr <= sp - 1; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto 0) <= pc; - memBAddr <= sp; - memBWrite <= memARead; - memBWriteEnable <= '1'; - -- The emulate address is: - -- 98 7654 3210 - -- 0000 00aa aaa0 0000 - pc <= (others => '0'); - pc(9 downto 5) <= opcode(4 downto 0); - state <= State_ResyncDecode; - when Decoded_AddSP => - if spOffset=0 then - -- avoid address line crashes... - -- FIX!!! is this an issue? - -- oh-well. While we are at it, we've got a faster - -- shift operation without updating the toolchain. - memAWriteEnable <= '1'; - memAAddr <= sp; - memAWrite <= memARead + memARead; - memBAddr <= sp+1; - else - memAWriteEnable <= '1'; - memAAddr <= sp; - memAWrite <= memARead; - memBAddr <= sp+spOffset; - state <= State_AddSP; - end if; - when Decoded_Break => - report "Break instruction encountered" severity failure; - break <= '1'; - when Decoded_PushPC => - memAWriteEnable <= '1'; - memAAddr <= sp - 1; - sp <= sp - 1; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto 0) <= pc; - memBAddr <= sp; - memBWrite <= memARead; - memBWriteEnable <= '1'; - when Decoded_PushSP => - memAWriteEnable <= '1'; - memAAddr <= sp - 1; - sp <= sp - 1; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto minAddrBit) <= sp; - memBAddr <= sp; - memBWrite <= memARead; - memBWriteEnable <= '1'; - when Decoded_Pushspadd => - memAWriteEnable <= '1'; - memAAddr <= sp; - memAWrite <= (others => DontCareValue); - pushspaddTemp := memARead(maxAddrBit-minAddrBit downto 0); - memAWrite(maxAddrBit downto minAddrBit) <= sp+pushspaddTemp; - memBAddr <= sp+1; - when Decoded_PopPC => - memAAddr <= sp; - pc <= memARead(maxAddrBit downto 0); - sp <= sp + 1; - state <= State_ResyncDecode; - when Decoded_AddIm => - memAWriteEnable <= '1'; - memAAddr <= sp; - tempVal(wordSize-1 downto 7) := (others => tOpcode(6)); - tempVal(6 downto 0) := tOpcode(6 downto 0); - memAWrite <= memARead + tempVal; - memBAddr <= sp + 1; - pc <= pc + 2; - when Decoded_Add => - memAWriteEnable <= '1'; - memAWrite <= memARead + memBRead; - memAAddr <= sp + 1; - memBAddr <= sp + 2; - sp <= sp + 1; - when Decoded_Or => - sp <= sp + 1; - memAWriteEnable <= '1'; - memAWrite <= memARead or memBRead; - memAWriteEnable <= '1'; - memAAddr <= sp + 1; - memBAddr <= sp + 2; - when Decoded_And => - sp <= sp + 1; - memAWriteEnable <= '1'; - memAWrite <= memARead and memBRead; - memAWriteEnable <= '1'; - memAAddr <= sp + 1; - memBAddr <= sp + 2; - when Decoded_Load => - if (memARead(ioBit)='1') then - io_addr <= memARead(maxAddrBit downto minAddrBit); - io_readEnable <= '1'; - state <= State_ReadIO; - else - memAAddr <= memARead(maxAddrBit downto minAddrBit); - memBAddr <= sp + 1; - end if; - when Decoded_Swap => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite(wordSize/2-1 downto 0) <= memARead(wordSize-1 downto wordSize/2); - memAWrite(wordSize-1 downto wordSize/2) <= memARead(wordSize/2-1 downto 0); - memBAddr <= sp + 1; - when Decoded_Not => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= not memARead; - memBAddr <= sp + 1; - when Decoded_Flip => - memAAddr <= sp; - memAWriteEnable <= '1'; - for i in 0 to wordSize-1 loop - memAWrite(i) <= memARead(wordSize-1-i); - end loop; - memBAddr <= sp + 1; - when Decoded_Lshift2 => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite(1 downto 0) <= (others => '0'); - memAWrite(wordSize-1 downto 2) <= memARead(wordSize-1-2 downto 0); - memBAddr <= sp + 1; - pc <= pc + 2; - when Decoded_Store => - sp <= sp + 2; - if (memARead(ioBit)='1') then - io_writeEnable <= '1'; - io_addr <= memARead(maxAddrBit downto minAddrBit); - io_write <= memBRead(7 downto 0); - state <= State_WriteIO; - else - memAWriteEnable <= '1'; - memAAddr <= memARead(maxAddrBit downto minAddrBit); - memAWrite <= memBRead; - state <= State_ResyncDecode; - end if; - when Decoded_PopSP => - sp <= memARead(maxAddrBit downto minAddrBit); - state <= State_ResyncDecode; - when Decoded_Ashiftleft => - memAWrite(wordSize-1 downto conv_integer(memARead(wordPower-1 downto 0))) <= - memBRead(wordSize-conv_integer(memARead(wordPower-1 downto 0))-1 downto 0); - if memARead(wordPower-1 downto 0)/=0 then - memAWrite(conv_integer(memARead(wordPower-1 downto 0))-1 downto 0) <= (others => '0'); - end if; - memAWriteEnable <= '1'; - memAAddr <= sp + 1; - memBAddr <= sp + 2; - sp <= sp + 1; - when Decoded_Ashiftright | Decoded_Lshiftright => - memAWrite(wordSize-1-conv_integer(memARead(wordPower-1 downto 0)) downto 0) <= - memBRead(wordSize-1 downto conv_integer(memARead(wordPower-1 downto 0))); - if memARead(wordPower-1 downto 0)/=0 then - if decodedOpcode=Decoded_Ashiftright and memBRead(wordSize-1)='1' then - memAWrite(wordSize-1 downto wordSize-conv_integer(memARead(wordPower-1 downto 0))-1) <= (others => '1'); - else - memAWrite(wordSize-1 downto wordSize-conv_integer(memARead(wordPower-1 downto 0))-1) <= (others => '0'); - end if; - end if; - memAWriteEnable <= '1'; - memAAddr <= sp + 1; - memBAddr <= sp + 2; - sp <= sp + 1; - when Decoded_Eqbranch => - sp <= sp + 2; - if (memBRead=0) then - pc <= memARead(maxAddrBit downto 0) + pc; - end if; - state <= State_ResyncDecode; - when Decoded_Neqbranch => - sp <= sp + 2; - if (memBRead/=0) then - pc <= memARead(maxAddrBit downto 0) + pc; - end if; - state <= State_ResyncDecode; - when Decoded_Eq => - sp <= sp + 1; - memAWrite <= (others => '0'); - if (memARead=memBRead) then - memAWrite(0) <= '1'; - end if; - memAAddr <= sp + 1; - memAWriteEnable <= '1'; - memBAddr <= sp + 2; - when Decoded_Neq => - sp <= sp + 1; - memAWrite <= (others => '0'); - if (memARead/=memBRead) then - memAWrite(0) <= '1'; - end if; - memAAddr <= sp + 1; - memAWriteEnable <= '1'; - memBAddr <= sp + 2; - when Decoded_Ulessthan => - sp <= sp + 1; - memAWrite <= (others => '0'); - if (memARead<memBRead) then - memAWrite(0) <= '1'; - end if; - memAAddr <= sp + 1; - memAWriteEnable <= '1'; - memBAddr <= sp + 2; - when Decoded_Ulessthanorequal => - sp <= sp + 1; - memAWrite <= (others => '0'); - if (memARead<=memBRead) then - memAWrite(0) <= '1'; - end if; - memAAddr <= sp + 1; - memAWriteEnable <= '1'; - memBAddr <= sp + 2; - when Decoded_Lessthan => - sp <= sp + 1; - memAWrite <= (others => '0'); - compareA := signed(memARead); - compareB := signed(memBRead); - if (compareA<compareB) then - memAWrite(0) <= '1'; - end if; - memAAddr <= sp + 1; - memAWriteEnable <= '1'; - memBAddr <= sp + 2; - when Decoded_Lessthanorequal => - sp <= sp + 1; - memAWrite <= (others => '0'); - compareA := signed(memARead); - compareB := signed(memBRead); - if (compareA<=compareB) then - memAWrite(0) <= '1'; - end if; - memAAddr <= sp + 1; - memAWriteEnable <= '1'; - memBAddr <= sp + 2; - when Decoded_Loadb => - byteSelect <= memARead(minAddrBit-1 downto 0); - memAAddr <= memARead(maxAddrBit downto minAddrBit); - state <= State_LoadByte1; - when Decoded_Storeb => - sp <= sp + 2; - byteSelect <= memARead(minAddrBit-1 downto 0); - storeByte <= memBRead(7 downto 0); - memAAddr <= memARead(maxAddrBit downto minAddrBit); - memBAddr <= sp; - state <= State_StoreByte1; - when Decoded_Mult16x16 => - mult1 <= memARead(wordSize/2-1 downto 0); - mult2 <= memBRead(wordSize/2-1 downto 0); - sp <= sp + 1; - state <= State_Mult1; - when others => - -- nop. Here we persist whatever was loaded into - -- memARead - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead; - memBAddr <= sp + 1; - - end case; - when State_ReadIO => - state <= State_ReadIODone; - when State_ReadIODone => - if (io_busy = '0') then - state <= State_ResyncDecode; - memAWriteEnable <= '1'; - memAWrite <= (others => '0'); - memAWrite(7 downto 0) <= io_read; - memAAddr <= sp; - end if; - when State_WriteIO => - state <= State_WriteIODone; - when State_WriteIODone => - if (io_busy = '0') then - state <= State_ResyncDecode; - end if; - when State_ResyncDecode => - memAAddr <= pc(maxAddrBit downto minAddrBit); - nextPC:=pc+1; - memBAddr <= nextPC(maxAddrBit downto minAddrBit); - state <= State_ResyncStack; - when State_ResyncStack => - memAAddr <= sp; - memBAddr <= sp+1; - state <= State_Decode; - when State_AddSP => - memAAddr <= pc(maxAddrBit downto minAddrBit); - nextPC:=pc+1; - memBAddr <= nextPC(maxAddrBit downto minAddrBit); - state <= State_Add; - when State_Add => - memAWriteEnable <= '1'; - memAWrite <= memARead + memBRead; - memAAddr <= sp; - memBAddr <= sp + 1; - state <= State_Decode; - when State_LoadByte1 => - memAAddr <= pc(maxAddrBit downto minAddrBit); - nextPC:=pc+1; - memBAddr <= nextPC(maxAddrBit downto minAddrBit); - state <= State_LoadByte2; - when State_LoadByte2 => - memAWriteEnable <= '1'; - memAAddr <= sp; - memAWrite <= (others => '0'); - case byteSelect is - when "00" => memAWrite(7 downto 0) <= memARead(31 downto 24); - when "01" => memAWrite(7 downto 0) <= memARead(23 downto 16); - when "10" => memAWrite(7 downto 0) <= memARead(15 downto 8); - when others => memAWrite(7 downto 0) <= memARead(7 downto 0); - end case; - memBAddr <= sp + 1; - state <= State_Decode; - when State_StoreByte1 => - state <= State_StoreByte2; - when State_StoreByte2 => - memAWriteEnable <= '1'; - memAAddr <= memBRead(maxAddrBit downto minAddrBit); - memAWrite <= memARead; - case byteSelect is - when "00" => memAWrite(31 downto 24) <= storeByte; - when "01" => memAWrite(23 downto 16) <= storeByte; - when "10" => memAWrite(15 downto 8) <= storeByte; - when others => memAWrite(7 downto 0) <= storeByte; - end case; - state <= State_ResyncDecode; - when State_Mult1 => - memAAddr <= pc(maxAddrBit downto minAddrBit); - nextPC:=pc+1; - memBAddr <= nextPC(maxAddrBit downto minAddrBit); - state <= State_Mult2; - when State_Mult2 => - memAWriteEnable <= '1'; - memAWrite <= multResult; - memAAddr <= sp; - memBAddr <= sp + 1; - state <= State_Decode; - - when others => - null; - end case; - end if; - end process; - - - -end behave; diff --git a/zpu/hdl/zpu3/src/zpuio.vhd b/zpu/hdl/zpu3/src/zpuio.vhd deleted file mode 100644 index 96e9aea..0000000 --- a/zpu/hdl/zpu3/src/zpuio.vhd +++ /dev/null @@ -1,180 +0,0 @@ -library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library zylin;
-use zylin.arm7.all;
-
-library zylin;
-use zylin.zpu_config.all;
-use zylin.zpupkg.all;
-
-entity zpuio is
- port ( areset : in std_logic;
- cpu_clk : in std_logic;
- clk_status : in std_logic_vector(2 downto 0);
- cpu_din : in std_logic_vector(15 downto 0);
- cpu_a : in std_logic_vector(20 downto 0);
- cpu_we : in std_logic_vector(1 downto 0);
- cpu_re : in std_logic;
- cpu_dout : inout std_logic_vector(15 downto 0));
-end zpuio;
-
-architecture behave of zpuio is
-
-signal timer_read : std_logic_vector(7 downto 0);
---signal timer_write : std_logic_vector(7 downto 0);
-signal timer_we : std_logic;
-
-
-signal io_busy : std_logic;
-signal io_read : std_logic_vector(7 downto 0);
-signal io_write : std_logic_vector(7 downto 0);
-signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit);
-signal io_writeEnable : std_logic;
-signal io_readEnable : std_logic;
-
-signal din : std_logic_vector(7 downto 0);
-signal dout : std_logic_vector(7 downto 0);
-signal adr : std_logic_vector(15 downto 0);
-signal break : std_logic;
-signal we : std_logic;
-signal re : std_logic;
-
-
--- uart forwarding...
-
-signal uartTXPending : std_logic;
-signal uartTXCleared : std_logic;
-signal uartData : std_logic_vector(7 downto 0);
-
-signal readingTimer : std_logic;
-begin
-
- timerinst: timer port map (
- clk => cpu_clk,
- areset => areset,
- we => timer_we,
- din => io_write,
- adr => io_addr(4 downto 2),
- dout => timer_read);
-
- zpu: zpu_top port map (
- clk => cpu_clk ,
- areset => areset,
- io_busy => io_busy,
- io_writeEnable => io_writeEnable,
- io_readEnable => io_readEnable,
- io_write => io_write,
- io_read => io_read,
- io_addr => io_addr,
- interrupt => '0'
- --,
--- break => cpu_fiq_p
-);
-
-
- -- Read/write are on different addresses
- -- The registers are 8 bits and mapped to bit[7:0]
- --
- -- 0xC000 Write: Writes to UART TX FIFO (4 byte FIFO)
- -- Read : Reads from UART RX FIFO (4 byte FIFO)
- -- 0xC004 Read : UART status register
- -- Bit 0 = RX FIFO empty
- -- Bit 1 = TX FIFO full
- -- 0xA000 Skrive: LED's (8 stk.)
-
- -- 0x9000 Write: bit 0: 1= reset counter
- -- 0= counter running
- -- bit 1: 1= sample counter (when set to 1)
- -- 0=not used
- -- Read : counter bit[7:0]
- -- 0x9004 Read: counter bit [15:8]
- -- 0x9008 Read: counter bit [23:16]
- -- 0x900C Read: counter bit [31:24]
- -- 0x9010 Read: counter bit [39:32]
- -- 0x9014 Read: counter bit [47:40]
- -- 0x9018 Read: counter bit [55:48]
- -- 0x901C Read: counter bit [63:56]
- --
- -- 0x8800 Read: unsigned 8-bit integer with FPGA frequency (in MHz)
-
- fauxUart:
- process(cpu_clk, areset)
- begin
- if areset = '1' then
- io_busy <= '0';
- uartTXPending <= '0';
- timer_we <= '0';
- io_busy <= '1';
- uartData <= x"58"; -- 'X'
- readingTimer <= '0';
- elsif (cpu_clk'event and cpu_clk = '1') then
- timer_we <= '0';
- io_busy <= '1';
- if uartTXCleared = '1' then
- uartTXPending <= '0';
- end if;
-
- if io_writeEnable = '1' then
- if io_addr=x"1000" then
- -- Write to UART
- uartData <= io_write;
- uartTXPending <= '1';
- io_busy <= '0';
- elsif io_addr(12)='1' then
- timer_we <= '1';
- io_busy <= '0';
- else
- report "Illegal IO write" severity failure;
- end if;
- end if;
- if (io_readEnable = '1') then
- if io_addr=x"1001" then
- io_read <= (0=>'1', -- recieve empty
- 1 => uartTXPending, -- tx full
- others => '0');
- io_busy <= '0';
- elsif io_addr(12)='1' then
- readingTimer <= '1';
- io_busy <= '1';
- elsif io_addr(11)='1' then
- io_read <= ZPU_Frequency;
- io_busy <= '0';
- else
- report "Illegal IO read" severity failure;
- end if;
-
- else
- if (readingTimer = '1') then
- readingTimer <= '0';
- io_read <= timer_read;
- io_busy <= '0';
- else
- io_read <= (others => '1');
- end if;
- end if;
- end if;
- end process;
-
-
- forwardUARTOutputToARM:
- process(cpu_clk, areset)
- begin
- if areset = '1' then
- uartTXCleared <= '0';
- elsif (cpu_clk = '1' and cpu_clk'event) then
- if cpu_we(0) = '1' and cpu_a(3 downto 1) = "000" then
- uartTXCleared <= cpu_din(0);
- else
- uartTXCleared <= uartTXCleared;
- end if;
- end if;
- end process;
-
- cpu_dout(7 downto 0) <= uartData when (cpu_re = '1' and cpu_a(3 downto 1) = "001") else (others => 'Z');
- cpu_dout <= (0 => uartTXPending, others => '0') when (cpu_re = '1' and cpu_a(3 downto 1) = "000") else (others => 'Z');
-
-
-
-end behave;
diff --git a/zpu/hdl/zpu3/src/zpupkg.vhd b/zpu/hdl/zpu3/src/zpupkg.vhd deleted file mode 100644 index a904b11..0000000 --- a/zpu/hdl/zpu3/src/zpupkg.vhd +++ /dev/null @@ -1,130 +0,0 @@ -library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-
-library zylin;
-use zylin.zpu_config.all;
-
-package zpupkg is
-
- component dualport_ram is
- port (clk : in std_logic;
- memAWriteEnable : in std_logic;
- memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
- memAWrite : in std_logic_vector(wordSize-1 downto 0);
- memARead : out std_logic_vector(wordSize-1 downto 0);
- memBWriteEnable : in std_logic;
- memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
- memBWrite : in std_logic_vector(wordSize-1 downto 0);
- memBRead : out std_logic_vector(wordSize-1 downto 0));
- end component;
-
-
- component trace is
- port(
- clk : in std_logic;
- begin_inst : in std_logic;
- pc : in std_logic_vector(maxAddrBit downto 0);
- opcode : in std_logic_vector(7 downto 0);
- sp : in std_logic_vector(maxAddrBit downto minAddrBit);
- memA : in std_logic_vector(wordSize-1 downto 0);
- memB : in std_logic_vector(wordSize-1 downto 0);
- busy : in std_logic
- );
- end component;
-
- component zpu_top is
- Port ( clk : in std_logic;
- areset : in std_logic;
- io_busy : in std_logic;
- io_read : in std_logic_vector(7 downto 0);
- io_write : out std_logic_vector(7 downto 0);
- io_addr : out std_logic_vector(maxAddrBit downto minAddrBit);
- io_writeEnable : out std_logic;
- io_readEnable : out std_logic;
- interrupt : in std_logic;
- break : out std_logic);
- end component;
-
-
- component timer is
- port(
- clk : in std_logic;
- areset : in std_logic;
- we : in std_logic;
- din : in std_logic_vector(7 downto 0);
- adr : in std_logic_vector(2 downto 0);
- dout : out std_logic_vector(7 downto 0));
- end component;
-
-
- component zpuio is
- port ( areset : in std_logic;
- cpu_clk : in std_logic;
- clk_status : in std_logic_vector(2 downto 0);
- cpu_din : in std_logic_vector(15 downto 0);
- cpu_a : in std_logic_vector(20 downto 0);
- cpu_we : in std_logic_vector(1 downto 0);
- cpu_re : in std_logic;
- cpu_dout : inout std_logic_vector(15 downto 0));
- end component;
-
-
- -- opcode decode constants
- constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
- constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
- constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
- constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
- constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
- constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
-
- constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
- constant OpCode_Shiftleft: std_logic_vector(3 downto 0) := "0001";
- constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
- constant OpCode_PushInt : std_logic_vector(3 downto 0) := "0011";
-
- constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
- constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
- constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
- constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
-
- constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
- constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
- constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
- constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
-
- constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
- constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
- constant OpCode_Compare : std_logic_vector(3 downto 0) := "1110";
- constant OpCode_PopInt : std_logic_vector(3 downto 0) := "1111";
-
- constant OpCode_Lessthan : std_logic_vector(5 downto 0) := conv_std_logic_vector(36, 6);
- constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := conv_std_logic_vector(37, 6);
- constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := conv_std_logic_vector(38, 6);
- constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := conv_std_logic_vector(39, 6);
-
- constant OpCode_Swap : std_logic_vector(5 downto 0) := conv_std_logic_vector(40, 6);
-
- constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := conv_std_logic_vector(42, 6);
- constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := conv_std_logic_vector(43, 6);
- constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := conv_std_logic_vector(44, 6);
-
- constant OpCode_Eq : std_logic_vector(5 downto 0) := conv_std_logic_vector(46, 6);
- constant OpCode_Neq : std_logic_vector(5 downto 0) := conv_std_logic_vector(47, 6);
-
- constant OpCode_Sub : std_logic_vector(5 downto 0) := conv_std_logic_vector(49, 6);
- constant OpCode_Loadb : std_logic_vector(5 downto 0) := conv_std_logic_vector(51, 6);
- constant OpCode_Storeb : std_logic_vector(5 downto 0) := conv_std_logic_vector(52, 6);
-
- constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := conv_std_logic_vector(55, 6);
- constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := conv_std_logic_vector(56, 6);
-
- constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := conv_std_logic_vector(61, 6);
- constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := conv_std_logic_vector(62, 6);
- constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := conv_std_logic_vector(63, 6);
-
-
-
- constant OpCode_Size : integer := 8;
-
-end zpupkg;
diff --git a/zpu/hdl/zpu4/src/simzpu_bram.do b/zpu/hdl/zpu4/src/simzpu_bram.do deleted file mode 100644 index 1c8673d..0000000 --- a/zpu/hdl/zpu4/src/simzpu_bram.do +++ /dev/null @@ -1,28 +0,0 @@ -# Xilinx WebPack modelsim script
-#
-# cd C:/workspace/zpu/zpu/hdl/zpu4/src
-# do simzpu_bram.do
-
-set BreakOnAssertion 1
-vlib work
-
-vcom -93 -explicit zpu_config_trace.vhd
-vcom -93 -explicit zpupkg.vhd
-vcom -93 -explicit txt_util.vhd
-vcom -93 -explicit sim_fpga_top.vhd
-vcom -93 -explicit zpu_core_bram.vhd
-vcom -93 -explicit bram_dmips.vhd
-vcom -93 -explicit timer.vhd
-vcom -93 -explicit io.vhd
-vcom -93 -explicit trace.vhd
-
-# run ZPU
-vsim fpga_top
-view wave
-add wave -recursive fpga_top/zpu/*
-#add wave -recursive fpga_top/*
-view structure
-#view signals
-
-# Enough to run tiny programs
-run 1us
diff --git a/zpu/hdl/zpu4/src/zpu_core_bram.vhd b/zpu/hdl/zpu4/src/zpu_core_bram.vhd deleted file mode 100644 index 0bedba3..0000000 --- a/zpu/hdl/zpu4/src/zpu_core_bram.vhd +++ /dev/null @@ -1,780 +0,0 @@ --- Company: ZPU3 --- Engineer: Øyvind Harboe - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -use IEEE.STD_LOGIC_arith.ALL; - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - - --- io_busy : in std_logic; --- io_read : in std_logic_vector(7 downto 0); --- io_write : out std_logic_vector(7 downto 0); --- io_addr : out std_logic_vector(maxAddrBit downto minAddrBit); --- io_writeEnable : out std_logic; --- io_readEnable : out std_logic; - - -entity zpu_core is - Port ( clk : in std_logic; - areset : in std_logic; - enable : in std_logic; - in_mem_busy : in std_logic; - mem_read : in std_logic_vector(wordSize-1 downto 0); - mem_write : out std_logic_vector(wordSize-1 downto 0); - out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); - out_mem_writeEnable : out std_logic; - out_mem_readEnable : out std_logic; - mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); - interrupt : in std_logic; - break : out std_logic); -end zpu_core; - - -architecture behave of zpu_core is - -signal readIO : std_logic; - - - -signal memAWriteEnable : std_logic; -signal memAAddr : std_logic_vector(maxAddrBit downto minAddrBit); -signal memAWrite : std_logic_vector(wordSize-1 downto 0); -signal memARead : std_logic_vector(wordSize-1 downto 0); -signal memBWriteEnable : std_logic; -signal memBAddr : std_logic_vector(maxAddrBit downto minAddrBit); -signal memBWrite : std_logic_vector(wordSize-1 downto 0); -signal memBRead : std_logic_vector(wordSize-1 downto 0); - - - -signal pc : std_logic_vector(maxAddrBit downto 0); -signal sp : std_logic_vector(maxAddrBit downto minAddrBit); - -signal idim_flag : std_logic; - ---signal storeToStack : std_logic; ---signal fetchNextInstruction : std_logic; ---signal extraCycle : std_logic; -signal busy : std_logic; ---signal fetching : std_logic; - -signal begin_inst : std_logic; - - - -signal trace_opcode : std_logic_vector(7 downto 0); -signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); -signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); -signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); - --- state machine. - -type State_Type is -( -State_ResyncDecode, -State_WriteIODone, -State_Execute, -State_StoreToStack, -State_Add, -State_Or, -State_And, -State_Store, -State_ReadIO, -State_WriteIO, -State_Load, -State_ResyncStack, -State_AddSP, -State_ReadIODone, -State_Decode, -State_LoadByte1, -State_LoadByte2, -State_StoreByte1, -State_StoreByte2, -State_Mult1, -State_Mult2, -State_Mult3 -); - -type DecodedOpcodeType is -( -Decoded_Nop, -Decoded_Im, -Decoded_ImShift, -Decoded_LoadSP, -Decoded_StoreSP, -Decoded_AddSP, -Decoded_Emulate, -Decoded_Break, -Decoded_PushPC, -Decoded_PushSP, -Decoded_PopPC, -Decoded_Add, -Decoded_Or, -Decoded_And, -Decoded_Load, -Decoded_Not, -Decoded_Flip, -Decoded_Store, -Decoded_PopSP, -Decoded_Ashiftleft, -Decoded_Ashiftright, -Decoded_Lshiftright, -Decoded_Eqbranch, -Decoded_Neqbranch, -Decoded_Eq, -Decoded_Neq, -Decoded_Loadb, -Decoded_Lessthan, -Decoded_Lessthanorequal, -Decoded_Ulessthan, -Decoded_Ulessthanorequal, -Decoded_Storeb, -Decoded_Lshift2, -Decoded_DoubleIm, -Decoded_AddIm, -Decoded_Mult16x16, -Decoded_Swap, -Decoded_Callpcrel, -Decoded_Pushspadd -); - - -signal mult1 : std_logic_vector(wordSize/2-1 downto 0); -signal mult2 : std_logic_vector(wordSize/2-1 downto 0); -signal multResult : std_logic_vector(wordSize-1 downto 0); - -signal storeByte : std_logic_vector(7 downto 0); -signal byteSelect : std_logic_vector(minAddrBit-1 downto 0); - -signal opcode : std_logic_vector(OpCode_Size-1 downto 0); -signal opcode2 : std_logic_vector(OpCode_Size-1 downto 0); - -signal decodedOpcode : DecodedOpcodeType; - -signal state : State_Type; - -begin - traceFileGenerate: - if Generate_Trace generate - trace_file: trace port map ( - clk => clk, - begin_inst => begin_inst, - pc => trace_pc, - opcode => trace_opcode, - sp => trace_sp, - memA => trace_topOfStack, - memB => trace_topOfStackB, - busy => busy, - intsp => (others => 'U') - ); - end generate; - - - memory: dualport_ram port map ( - clk => clk, - memAWriteEnable => memAWriteEnable, - memAAddr => memAAddr(maxAddrBitBRAM downto minAddrBit), - memAWrite => memAWrite, - memARead => memARead, - memBWriteEnable => memBWriteEnable, - memBAddr => memBAddr(maxAddrBitBRAM downto minAddrBit), - memBWrite => memBWrite, - memBRead => memBRead - ); - - - - process(clk, areset) - begin - if (clk'event and clk = '1') then - multResult <= mult1 * mult2; - end if; - end process; - - - - opcodeControl: - process(clk, areset) - variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); - variable tOpcode2 : std_logic_vector(OpCode_Size-1 downto 0); - variable spOffset : std_logic_vector(4 downto 0); - variable spOffset2 : std_logic_vector(4 downto 0); - variable nextPC : std_logic_vector(maxAddrBit downto 0); - variable pushspaddTemp : std_logic_vector(maxAddrBit downto minAddrBit); - variable tempVal : std_logic_vector(wordSize-1 downto 0); - variable compareA : signed(wordSize-1 downto 0); - variable compareB : signed(wordSize-1 downto 0); - begin - if areset = '1' then - mult1 <= (others => '0'); - mult2 <= (others => '0'); - state <= State_ResyncDecode; - break <= '0'; - sp <= spStart(maxAddrBit downto minAddrBit); - pc <= (others => '0'); - idim_flag <= '0'; - begin_inst <= '0'; - memAAddr <= (others => '0'); - memBAddr <= (others => '0'); - memAWriteEnable <= '0'; - memBWriteEnable <= '0'; - out_mem_writeEnable <= '0'; - out_mem_readEnable <= '0'; - decodedOpcode <= Decoded_Break; - memAWrite <= (others => '0'); - memBWrite <= (others => '0'); - opcode <= (others => '0'); - out_mem_addr <= (others => '0'); - mem_write <= (others => '0'); - elsif (clk'event and clk = '1') then - memAWriteEnable <= '0'; - memBWriteEnable <= '0'; - - out_mem_writeEnable <= '0'; - out_mem_readEnable <= '0'; - out_mem_addr <= memARead(maxAddrBitIncIO downto 0); - begin_inst <= '0'; - - case state is - when State_Decode => - nextPC:=pc+1; - case pc(1 downto 0) is - when "00" => tOpcode := memARead(31 downto 24); - when "01" => tOpcode := memARead(23 downto 16); - when "10" => tOpcode := memARead(15 downto 8); - when others => tOpcode := memARead(7 downto 0); - end case; - case nextPC(1 downto 0) is - when "00" => tOpcode2 := memBRead(31 downto 24); - when "01" => tOpcode2 := memBRead(23 downto 16); - when "10" => tOpcode2 := memBRead(15 downto 8); - when others => tOpcode2 := memBRead(7 downto 0); - end case; - idim_flag <= tOpcode(7); - opcode <= tOpcode; - opcode2 <= tOpcode2; - if (tOpcode(7 downto 7)=OpCode_Im and tOpcode2(7 downto 4)=0 and tOpcode2(3 downto 0)=Opcode_Add and idim_flag='0') then - idim_flag <= '0'; - decodedOpcode <= Decoded_AddIm; - nextPC := pc + 2; - elsif (tOpcode(7 downto 7)=OpCode_Im and tOpcode2(7 downto 7)=OpCode_Im and idim_flag='0') then - decodedOpcode <= Decoded_DoubleIm; - nextPC := pc + 2; - elsif (tOpcode(7 downto 4)=OpCode_AddSP and tOpcode(3 downto 0)=0 and - tOpcode2(7 downto 4)=OpCode_AddSP and tOpcode2(3 downto 0)=0) then - decodedOpcode <= Decoded_Lshift2; - nextPC := pc + 2; - elsif (tOpcode(7 downto 7)=OpCode_Im) then - if (idim_flag='1') then - decodedOpcode<=Decoded_ImShift; - else - decodedOpcode<=Decoded_Im; - end if; - elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then - decodedOpcode<=Decoded_StoreSP; - elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then - decodedOpcode<=Decoded_LoadSP; - elsif (tOpcode(7 downto 5)=OpCode_Emulate) then - if tOpcode(5 downto 0)=OpCode_Eqbranch then - decodedOpcode <= Decoded_Eqbranch; - elsif tOpcode(5 downto 0)=OpCode_Neqbranch then - decodedOpcode <= Decoded_Neqbranch; - elsif tOpcode(5 downto 0)=OpCode_Eq then - decodedOpcode <= Decoded_Eq; - elsif tOpcode(5 downto 0)=OpCode_Neq then - decodedOpcode <= Decoded_Neq; - elsif tOpcode(5 downto 0)=OpCode_Lessthan then - decodedOpcode <= Decoded_Lessthan; - elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then - decodedOpcode <= Decoded_Lessthanorequal; - elsif tOpcode(5 downto 0)=OpCode_Ulessthan then - decodedOpcode <= Decoded_Ulessthan; - elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then - decodedOpcode <= Decoded_Ulessthanorequal; - elsif tOpcode(5 downto 0)=OpCode_Loadb then - decodedOpcode <= Decoded_Loadb; - elsif tOpcode(5 downto 0)=OpCode_Storeb then - decodedOpcode <= Decoded_Storeb; - elsif tOpcode(5 downto 0)=OpCode_Mult16x16 then - decodedOpcode <= Decoded_Mult16x16; - elsif tOpcode(5 downto 0)=OpCode_Swap then - decodedOpcode <= Decoded_Swap; - elsif tOpcode(5 downto 0)=OpCode_Callpcrel then - decodedOpcode <= Decoded_Callpcrel; - elsif tOpcode(5 downto 0)=OpCode_Pushspadd then - decodedOpcode <= Decoded_Pushspadd; --- elsif tOpcode(5 downto 0)=OpCode_Lshiftright then --- decodedOpcode <= Decoded_Lshiftright; --- elsif tOpcode(5 downto 0)=OpCode_Ashiftleft then --- decodedOpcode <= Decoded_Ashiftleft; --- elsif tOpcode(5 downto 0)=OpCode_Ashiftright then --- decodedOpcode <= Decoded_Ashiftright; - else - decodedOpcode<=Decoded_Emulate; - end if; - elsif (tOpcode(7 downto 4)=OpCode_AddSP) then - decodedOpcode<=Decoded_AddSP; - else - case tOpcode(3 downto 0) is - when OpCode_PushSP => - decodedOpcode<=Decoded_PushSP; - when OpCode_PopPC => - decodedOpcode<=Decoded_PopPC; - when OpCode_Add => - decodedOpcode<=Decoded_Add; - when OpCode_Or => - decodedOpcode<=Decoded_Or; - when OpCode_And => - decodedOpcode<=Decoded_And; - when OpCode_Load => - decodedOpcode<=Decoded_Load; - when OpCode_Not => - decodedOpcode<=Decoded_Not; - when OpCode_Flip => - decodedOpcode<=Decoded_Flip; - when OpCode_Store => - decodedOpcode<=Decoded_Store; - when OpCode_PopSP => - decodedOpcode<=Decoded_PopSP; - when OpCode_Break => - decodedOpcode<=Decoded_Break; - when others => - decodedOpcode<=Decoded_Nop; - end case; - end if; - -- Fetch the two next opcodes... :-) - memAAddr <= nextPC(maxAddrBit downto minAddrBit); - nextPC:=nextPC+1; - memBAddr <= nextPC(maxAddrBit downto minAddrBit); - state <= State_Execute; - when State_Execute => - state <= State_Decode; - -- at this point: - -- memBRead contains opcode word - -- memARead contains top of stack - pc <= pc + 1; - - -- trace - begin_inst <= '1'; - trace_pc <= (others => '0'); - trace_pc(maxAddrBit downto 0) <= pc; - trace_sp <= (others => '0'); - trace_sp(maxAddrBit downto minAddrBit) <= sp; - trace_opcode <= opcode; - trace_topOfStack <= memARead; - trace_topOfStackB <= memBRead; - - - -- during the next cycle we'll be reading the next opcode - spOffset(4):=not opcode(4); - spOffset(3 downto 0):=opcode(3 downto 0); - spOffset2(4):=not opcode2(4); - spOffset2(3 downto 0):=opcode2(3 downto 0); - - case decodedOpcode is - - when Decoded_DoubleIm => - memAWriteEnable <= '1'; - sp <= sp - 1; - memAAddr <= sp-1; - for i in wordSize-1 downto 14 loop - memAWrite(i) <= opcode(6); - end loop; - memAWrite(13 downto 7) <= opcode(6 downto 0); - memAWrite(6 downto 0) <= opcode2(6 downto 0); - memBAddr <= sp; - memBWrite <= memARead; - memBWriteEnable <= '1'; - pc <= pc + 2; - when Decoded_Im => - memAWriteEnable <= '1'; - sp <= sp - 1; - memAAddr <= sp-1; - for i in wordSize-1 downto 7 loop - memAWrite(i) <= opcode(6); - end loop; - memAWrite(6 downto 0) <= opcode(6 downto 0); - memBAddr <= sp; - memBWrite <= memARead; - memBWriteEnable <= '1'; - when Decoded_ImShift => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0); - memAWrite(6 downto 0) <= opcode(6 downto 0); - memBAddr <= sp + 1; - when Decoded_StoreSP => - memAWriteEnable <= '1'; - memAAddr <= sp+spOffset; - memAWrite <= memARead; - -- avoid address crashes. - memBAddr <= sp - 1; - sp <= sp + 1; - state <= State_ResyncDecode; - when Decoded_LoadSP => - sp <= sp - 1; - if (spOffset = 0) then - -- This is a duplicate instruction. - memAAddr <= sp-1; - memAWriteEnable <= '1'; - memAWrite <= memARead; - else - memAAddr <= sp+spOffset; - end if; - memBAddr <= sp; - memBWrite <= memARead; - memBWriteEnable <= '1'; - when Decoded_Callpcrel => - memAWriteEnable <= '1'; - memAAddr <= sp; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto 0) <= pc + 1; - memBAddr <= sp+1; - pc <= pc + memARead(maxAddrBit downto 0); - state <= State_ResyncDecode; - when Decoded_Emulate => - sp <= sp - 1; - memAWriteEnable <= '1'; - memAAddr <= sp - 1; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto 0) <= pc + 1; - memBAddr <= sp; - memBWrite <= memARead; - memBWriteEnable <= '1'; - -- The emulate address is: - -- 98 7654 3210 - -- 0000 00aa aaa0 0000 - pc <= (others => '0'); - pc(9 downto 5) <= opcode(4 downto 0); - state <= State_ResyncDecode; - when Decoded_AddSP => - if spOffset=0 then - -- avoid address line crashes... - -- FIX!!! is this an issue? - -- oh-well. While we are at it, we've got a faster - -- shift operation without updating the toolchain. - memAWriteEnable <= '1'; - memAAddr <= sp; - memAWrite <= memARead + memARead; - memBAddr <= sp+1; - else - memAWriteEnable <= '1'; - memAAddr <= sp; - memAWrite <= memARead; - memBAddr <= sp+spOffset; - state <= State_AddSP; - end if; - when Decoded_Break => - report "Break instruction encountered" severity failure; - break <= '1'; - when Decoded_PushSP => - memAWriteEnable <= '1'; - memAAddr <= sp - 1; - sp <= sp - 1; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto minAddrBit) <= sp; - memBAddr <= sp; - memBWrite <= memARead; - memBWriteEnable <= '1'; - when Decoded_Pushspadd => - memAWriteEnable <= '1'; - memAAddr <= sp; - memAWrite <= (others => DontCareValue); - pushspaddTemp := memARead(maxAddrBit-minAddrBit downto 0); - memAWrite(maxAddrBit downto minAddrBit) <= sp+pushspaddTemp; - memBAddr <= sp+1; - when Decoded_PopPC => - memAAddr <= sp; - pc <= memARead(maxAddrBit downto 0); - sp <= sp + 1; - state <= State_ResyncDecode; - when Decoded_AddIm => - memAWriteEnable <= '1'; - memAAddr <= sp; - tempVal(wordSize-1 downto 7) := (others => tOpcode(6)); - tempVal(6 downto 0) := tOpcode(6 downto 0); - memAWrite <= memARead + tempVal; - memBAddr <= sp + 1; - pc <= pc + 2; - when Decoded_Add => - memAWriteEnable <= '1'; - memAWrite <= memARead + memBRead; - memAAddr <= sp + 1; - memBAddr <= sp + 2; - sp <= sp + 1; - when Decoded_Or => - sp <= sp + 1; - memAWriteEnable <= '1'; - memAWrite <= memARead or memBRead; - memAWriteEnable <= '1'; - memAAddr <= sp + 1; - memBAddr <= sp + 2; - when Decoded_And => - sp <= sp + 1; - memAWriteEnable <= '1'; - memAWrite <= memARead and memBRead; - memAWriteEnable <= '1'; - memAAddr <= sp + 1; - memBAddr <= sp + 2; - when Decoded_Load => - if (memARead(ioBit)='1') then - out_mem_addr <= memARead(maxAddrBitIncIO downto 0); - out_mem_readEnable <= '1'; - state <= State_ReadIO; - else - memAAddr <= memARead(maxAddrBit downto minAddrBit); - memBAddr <= sp + 1; - end if; - when Decoded_Swap => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite(wordSize/2-1 downto 0) <= memARead(wordSize-1 downto wordSize/2); - memAWrite(wordSize-1 downto wordSize/2) <= memARead(wordSize/2-1 downto 0); - memBAddr <= sp + 1; - when Decoded_Not => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= not memARead; - memBAddr <= sp + 1; - when Decoded_Flip => - memAAddr <= sp; - memAWriteEnable <= '1'; - for i in 0 to wordSize-1 loop - memAWrite(i) <= memARead(wordSize-1-i); - end loop; - memBAddr <= sp + 1; - when Decoded_Lshift2 => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite(1 downto 0) <= (others => '0'); - memAWrite(wordSize-1 downto 2) <= memARead(wordSize-1-2 downto 0); - memBAddr <= sp + 1; - pc <= pc + 2; - when Decoded_Store => - sp <= sp + 2; - if (memARead(ioBit)='1') then - out_mem_writeEnable <= '1'; - out_mem_addr <= memARead(maxAddrBitIncIO downto 0); - mem_write <= memBRead; - state <= State_WriteIO; - else - memAWriteEnable <= '1'; - memAAddr <= memARead(maxAddrBit downto minAddrBit); - memAWrite <= memBRead; - state <= State_ResyncDecode; - end if; - when Decoded_PopSP => - sp <= memARead(maxAddrBit downto minAddrBit); - state <= State_ResyncDecode; - when Decoded_Ashiftleft => - memAWrite(wordSize-1 downto conv_integer(memARead(wordPower-1 downto 0))) <= - memBRead(wordSize-conv_integer(memARead(wordPower-1 downto 0))-1 downto 0); - if memARead(wordPower-1 downto 0)/=0 then - memAWrite(conv_integer(memARead(wordPower-1 downto 0))-1 downto 0) <= (others => '0'); - end if; - memAWriteEnable <= '1'; - memAAddr <= sp + 1; - memBAddr <= sp + 2; - sp <= sp + 1; - when Decoded_Ashiftright | Decoded_Lshiftright => - memAWrite(wordSize-1-conv_integer(memARead(wordPower-1 downto 0)) downto 0) <= - memBRead(wordSize-1 downto conv_integer(memARead(wordPower-1 downto 0))); - if memARead(wordPower-1 downto 0)/=0 then - if decodedOpcode=Decoded_Ashiftright and memBRead(wordSize-1)='1' then - memAWrite(wordSize-1 downto wordSize-conv_integer(memARead(wordPower-1 downto 0))-1) <= (others => '1'); - else - memAWrite(wordSize-1 downto wordSize-conv_integer(memARead(wordPower-1 downto 0))-1) <= (others => '0'); - end if; - end if; - memAWriteEnable <= '1'; - memAAddr <= sp + 1; - memBAddr <= sp + 2; - sp <= sp + 1; - when Decoded_Eqbranch => - sp <= sp + 2; - if (memBRead=0) then - pc <= memARead(maxAddrBit downto 0) + pc; - end if; - state <= State_ResyncDecode; - when Decoded_Neqbranch => - sp <= sp + 2; - if (memBRead/=0) then - pc <= memARead(maxAddrBit downto 0) + pc; - end if; - state <= State_ResyncDecode; - when Decoded_Eq => - sp <= sp + 1; - memAWrite <= (others => '0'); - if (memARead=memBRead) then - memAWrite(0) <= '1'; - end if; - memAAddr <= sp + 1; - memAWriteEnable <= '1'; - memBAddr <= sp + 2; - when Decoded_Neq => - sp <= sp + 1; - memAWrite <= (others => '0'); - if (memARead/=memBRead) then - memAWrite(0) <= '1'; - end if; - memAAddr <= sp + 1; - memAWriteEnable <= '1'; - memBAddr <= sp + 2; - when Decoded_Ulessthan => - sp <= sp + 1; - memAWrite <= (others => '0'); - if (memARead<memBRead) then - memAWrite(0) <= '1'; - end if; - memAAddr <= sp + 1; - memAWriteEnable <= '1'; - memBAddr <= sp + 2; - when Decoded_Ulessthanorequal => - sp <= sp + 1; - memAWrite <= (others => '0'); - if (memARead<=memBRead) then - memAWrite(0) <= '1'; - end if; - memAAddr <= sp + 1; - memAWriteEnable <= '1'; - memBAddr <= sp + 2; - when Decoded_Lessthan => - sp <= sp + 1; - memAWrite <= (others => '0'); - compareA := signed(memARead); - compareB := signed(memBRead); - if (compareA<compareB) then - memAWrite(0) <= '1'; - end if; - memAAddr <= sp + 1; - memAWriteEnable <= '1'; - memBAddr <= sp + 2; - when Decoded_Lessthanorequal => - sp <= sp + 1; - memAWrite <= (others => '0'); - compareA := signed(memARead); - compareB := signed(memBRead); - if (compareA<=compareB) then - memAWrite(0) <= '1'; - end if; - memAAddr <= sp + 1; - memAWriteEnable <= '1'; - memBAddr <= sp + 2; - when Decoded_Loadb => - byteSelect <= memARead(minAddrBit-1 downto 0); - memAAddr <= memARead(maxAddrBit downto minAddrBit); - state <= State_LoadByte1; - when Decoded_Storeb => - sp <= sp + 2; - byteSelect <= memARead(minAddrBit-1 downto 0); - storeByte <= memBRead(7 downto 0); - memAAddr <= memARead(maxAddrBit downto minAddrBit); - memBAddr <= sp; - state <= State_StoreByte1; - when Decoded_Mult16x16 => - mult1 <= memARead(wordSize/2-1 downto 0); - mult2 <= memBRead(wordSize/2-1 downto 0); - sp <= sp + 1; - state <= State_Mult1; - when others => - -- nop. Here we persist whatever was loaded into - -- memARead - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead; - memBAddr <= sp + 1; - - end case; - when State_ReadIO => - state <= State_ReadIODone; - when State_ReadIODone => - if (in_mem_busy = '0') then - state <= State_ResyncDecode; - memAWriteEnable <= '1'; - memAWrite <= (others => '0'); - memAWrite <= mem_read; - memAAddr <= sp; - end if; - when State_WriteIO => - state <= State_WriteIODone; - when State_WriteIODone => - if (in_mem_busy = '0') then - state <= State_ResyncDecode; - end if; - when State_ResyncDecode => - memAAddr <= pc(maxAddrBit downto minAddrBit); - nextPC:=pc+1; - memBAddr <= nextPC(maxAddrBit downto minAddrBit); - state <= State_ResyncStack; - when State_ResyncStack => - memAAddr <= sp; - memBAddr <= sp+1; - state <= State_Decode; - when State_AddSP => - memAAddr <= pc(maxAddrBit downto minAddrBit); - nextPC:=pc+1; - memBAddr <= nextPC(maxAddrBit downto minAddrBit); - state <= State_Add; - when State_Add => - memAWriteEnable <= '1'; - memAWrite <= memARead + memBRead; - memAAddr <= sp; - memBAddr <= sp + 1; - state <= State_Decode; - when State_LoadByte1 => - memAAddr <= pc(maxAddrBit downto minAddrBit); - nextPC:=pc+1; - memBAddr <= nextPC(maxAddrBit downto minAddrBit); - state <= State_LoadByte2; - when State_LoadByte2 => - memAWriteEnable <= '1'; - memAAddr <= sp; - memAWrite <= (others => '0'); - case byteSelect is - when "00" => memAWrite(7 downto 0) <= memARead(31 downto 24); - when "01" => memAWrite(7 downto 0) <= memARead(23 downto 16); - when "10" => memAWrite(7 downto 0) <= memARead(15 downto 8); - when others => memAWrite(7 downto 0) <= memARead(7 downto 0); - end case; - memBAddr <= sp + 1; - state <= State_Decode; - when State_StoreByte1 => - state <= State_StoreByte2; - when State_StoreByte2 => - memAWriteEnable <= '1'; - memAAddr <= memBRead(maxAddrBit downto minAddrBit); - memAWrite <= memARead; - case byteSelect is - when "00" => memAWrite(31 downto 24) <= storeByte; - when "01" => memAWrite(23 downto 16) <= storeByte; - when "10" => memAWrite(15 downto 8) <= storeByte; - when others => memAWrite(7 downto 0) <= storeByte; - end case; - state <= State_ResyncDecode; - when State_Mult1 => - memAAddr <= pc(maxAddrBit downto minAddrBit); - nextPC:=pc+1; - memBAddr <= nextPC(maxAddrBit downto minAddrBit); - state <= State_Mult2; - when State_Mult2 => - memAWriteEnable <= '1'; - memAWrite <= multResult; - memAAddr <= sp; - memBAddr <= sp + 1; - state <= State_Decode; - - when others => - null; - end case; - end if; - end process; - - - -end behave; diff --git a/zpu/roadshow/roadshow/helloworld/test.c b/zpu/roadshow/roadshow/helloworld/test.c index 8c33640..5243468 100644 --- a/zpu/roadshow/roadshow/helloworld/test.c +++ b/zpu/roadshow/roadshow/helloworld/test.c @@ -1,3 +1,4 @@ +/* zpu-elf-gcc -g -Wl,--relax test.c -phi -o hello.elf */ int main(int argc, char **argv) { for (;;) |
