* Make code synthesize on Synopsis

	 zpu/hdl/zpu4/src/zpu_core_small.vhd
	 zpu/hdl/zpu4/src/io.vhd

5 files changed, 35 insertions, 12 deletions

diff --git a/zpu/hdl/zpu4/src/sim_small_fpga_top.vhd b/zpu/hdl/example/sim_small_fpga_top.vhd
index 5c05881..5c05881 100644
--- a/zpu/hdl/zpu4/src/sim_small_fpga_top.vhd
+++ b/zpu/hdl/example/sim_small_fpga_top.vhd
diff --git a/zpu/hdl/example/simzpu_small.do b/zpu/hdl/example/simzpu_small.do
index 1f8f358..095069a 100644
--- a/zpu/hdl/example/simzpu_small.do
+++ b/zpu/hdl/example/simzpu_small.do
@@ -10,7 +10,7 @@ vlib work
 vcom -93 -explicit  zpu_config.vhd

 vcom -93 -explicit  ../zpu4/src/zpupkg.vhd

 vcom -93 -explicit  ../zpu4/src/txt_util.vhd

-vcom -93 -explicit  ../zpu4/src/sim_small_fpga_top.vhd

+vcom -93 -explicit  sim_small_fpga_top.vhd

 vcom -93 -explicit  ../zpu4/src/zpu_core_small.vhd

 vcom -93 -explicit  helloworld.vhd

 vcom -93 -explicit  ../zpu4/src/timer.vhd

diff --git a/zpu/hdl/zpu4/src/io.vhd b/zpu/hdl/zpu4/src/io.vhd
index 7a2601f..9e65929 100644
--- a/zpu/hdl/zpu4/src/io.vhd
+++ b/zpu/hdl/zpu4/src/io.vhd
@@ -59,8 +59,9 @@ begin
 		elsif (clk'event and clk = '1') then

 --			timer_we <= '0';

 			if writeEnable = '1' then

-				-- external interface

-				if addr=x"2028003" then

+				-- external interface (fixed address)
+				--<JK> extend compare to avoid waring messages
+				if ("000" & addr)=x"2028003" then
 					-- Write to UART

 					-- report "" & character'image(conv_integer(memBint)) severity note;

 				    print(l_file, character'val(to_integer(unsigned(write))));

@@ -69,24 +70,26 @@ begin
 -- 					timer_we <= '1';

 				else

 					print(l_file, character'val(to_integer(unsigned(write))));

-					report "Illegal IO write" severity warning;

+					-- report "Illegal IO write" severity warning;
 				end if;

 				

 			end if;

 			read <= (others => '0');

 			if (readEnable = '1') then

-				if addr=x"1001" then

+				--<JK> extend compare to avoid waring messages
+				if ("000" & addr)=x"0001001" then
 					read <= (0=>'1', others => '0'); -- recieve empty

  				elsif addr(12)='1' then

  					read(7 downto 0) <= timer_read;

  				elsif addr(11)='1' then

  					read(7 downto 0) <= ZPU_Frequency;

- 				elsif addr=x"2028003" then

+				--<JK> extend compare to avoid waring messages
+				elsif ("000" & addr)=x"2028003" then
 					read <= (others => '0');

 				else

 					read <= (others => '0');

 					read(8) <= '1';

-					report "Illegal IO read" severity warning;

+					-- report "Illegal IO read" severity warning;
 				end if;

 			end if;

 		end if;

diff --git a/zpu/hdl/zpu4/src/zpu_core_small.vhd b/zpu/hdl/zpu4/src/zpu_core_small.vhd
index 0d734d2..9cda01c 100644
--- a/zpu/hdl/zpu4/src/zpu_core_small.vhd
+++ b/zpu/hdl/zpu4/src/zpu_core_small.vhd
@@ -125,6 +125,11 @@ signal memBAddr_stdlogic  : std_logic_vector(AddrBitBRAM_range);
 signal memBWrite_stdlogic : std_logic_vector(memBWrite'range);

 signal memBRead_stdlogic  : std_logic_vector(memBRead'range);

 

+-- debug
+subtype index is integer range 0 to 3;
+signal tOpcode_sel : index;
+
+
 begin

 	traceFileGenerate:

    if Generate_Trace generate

@@ -141,6 +146,8 @@ begin
         );

 	end generate;

 

+	--<JK> not used in this design
+	mem_writeMask <= (others => '1');
 

 	memAAddr_stdlogic  <= std_logic_vector(memAAddr(AddrBitBRAM_range));

 	memAWrite_stdlogic <= std_logic_vector(memAWrite);

@@ -160,14 +167,23 @@ begin
 	memARead <= unsigned(memARead_stdlogic);

 	memBRead <= unsigned(memBRead_stdlogic);

 

+tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0));
 

 

 	decodeControl:

-	process(memBRead, pc)

+	process(memBRead, pc,tOpcode_sel)
 		variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0);

 	begin

-		tOpcode := std_logic_vector(memBRead((wordBytes-1-to_integer(pc(minAddrBit-1 downto 0))+1)*8-1 downto (wordBytes-1-to_integer(pc(minAddrBit-1 downto 0)))*8));

-

+		--<JK> not worked with synopsys
+		--<JK> tOpcode := std_logic_vector(memBRead((wordBytes-1-to_integer(pc(minAddrBit-1 downto 0))+1)*8-1 downto (wordBytes-1-to_integer(pc(minAddrBit-1 downto 0)))*8));
+		--<JK> use full case
+		case (tOpcode_sel) is
+			when 0 => tOpcode := std_logic_vector(memBRead(31 downto 24));
+			when 1 => tOpcode := std_logic_vector(memBRead(23 downto 16));
+			when 2 => tOpcode := std_logic_vector(memBRead(15 downto 8));
+			when 3 => tOpcode := std_logic_vector(memBRead(7 downto 0));
+			when others => tOpcode := std_logic_vector(memBRead(7 downto 0));
+		end case;
 		sampledOpcode <= tOpcode;

 

 		if (tOpcode(7 downto 7)=OpCode_Im) then

@@ -230,7 +246,8 @@ begin
 			out_mem_readEnable <= '0';

 			memAWrite <= (others => '0');

 			memBWrite <= (others => '0');

-			mem_writeMask <= (others => '1');

+			-- avoid Latch in synopsys
+			-- mem_writeMask <= (others => '1');
 		elsif (clk'event and clk = '1') then

 			memAWriteEnable <= '0';

 			memBWriteEnable <= '0';

diff --git a/zpu/hdl/zpu4/test/interrupt/int.c b/zpu/hdl/zpu4/test/interrupt/int.c
index 2be6483..1b6ec01 100644
--- a/zpu/hdl/zpu4/test/interrupt/int.c
+++ b/zpu/hdl/zpu4/test/interrupt/int.c
@@ -6,7 +6,10 @@
 

 int counter;

 

-/* Example of single, fixed interval non-maskable, nested interrupt */

+/* Example of single, fixed interval non-maskable, nested interrupt. The interrupt signal is

+ * held high for enough cycles to guarantee that it will be noticed, i.e. longer than

+ * any io access + 4 cycles roughly.

+ */

 void  _zpu_interrupt(void)

 {

 	/* interrupts are enabled so we need to finish up quickly,