1 2 3 4 5 6 7 8
#ifndef _ASM_M32R_CACHE_H #define _ASM_M32R_CACHE_H /* L1 cache line size */ #define L1_CACHE_SHIFT 4 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) #endif /* _ASM_M32R_CACHE_H */