summaryrefslogtreecommitdiffstats
path: root/drivers/platform/x86/intel_pmic_gpio.c
blob: 930e62762365ab262155baf814ad6f74fa261733 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
/* Moorestown PMIC GPIO (access through IPC) driver
 * Copyright (c) 2008 - 2009, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

/* Supports:
 * Moorestown platform PMIC chip
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/stddef.h>
#include <linux/slab.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <asm/intel_scu_ipc.h>
#include <linux/device.h>
#include <linux/intel_pmic_gpio.h>
#include <linux/platform_device.h>

#define DRIVER_NAME "pmic_gpio"

/* register offset that IPC driver should use
 * 8 GPIO + 8 GPOSW (6 controllable) + 8GPO
 */
enum pmic_gpio_register {
	GPIO0		= 0xE0,
	GPIO7		= 0xE7,
	GPIOINT		= 0xE8,
	GPOSWCTL0	= 0xEC,
	GPOSWCTL5	= 0xF1,
	GPO		= 0xF4,
};

/* bits definition for GPIO & GPOSW */
#define GPIO_DRV 0x01
#define GPIO_DIR 0x02
#define GPIO_DIN 0x04
#define GPIO_DOU 0x08
#define GPIO_INTCTL 0x30
#define GPIO_DBC 0xc0

#define GPOSW_DRV 0x01
#define GPOSW_DOU 0x08
#define GPOSW_RDRV 0x30


#define NUM_GPIO 24

struct pmic_gpio_irq {
	spinlock_t lock;
	u32 trigger[NUM_GPIO];
	u32 dirty;
	struct work_struct work;
};


struct pmic_gpio {
	struct gpio_chip	chip;
	struct pmic_gpio_irq	irqtypes;
	void			*gpiointr;
	int			irq;
	unsigned		irq_base;
};

static void pmic_program_irqtype(int gpio, int type)
{
	if (type & IRQ_TYPE_EDGE_RISING)
		intel_scu_ipc_update_register(GPIO0 + gpio, 0x20, 0x20);
	else
		intel_scu_ipc_update_register(GPIO0 + gpio, 0x00, 0x20);

	if (type & IRQ_TYPE_EDGE_FALLING)
		intel_scu_ipc_update_register(GPIO0 + gpio, 0x10, 0x10);
	else
		intel_scu_ipc_update_register(GPIO0 + gpio, 0x00, 0x10);
};

static void pmic_irqtype_work(struct work_struct *work)
{
	struct pmic_gpio_irq *t =
		container_of(work, struct pmic_gpio_irq, work);
	unsigned long flags;
	int i;
	u16 type;

	spin_lock_irqsave(&t->lock, flags);
	/* As we drop the lock, we may need multiple scans if we race the
	   pmic_irq_type function */
	while (t->dirty) {
		/*
		 *	For each pin that has the dirty bit set send an IPC
		 *	message to configure the hardware via the PMIC
		 */
		for (i = 0; i < NUM_GPIO; i++) {
			if (!(t->dirty & (1 << i)))
				continue;
			t->dirty &= ~(1 << i);
			/* We can't trust the array entry or dirty
			   once the lock is dropped */
			type = t->trigger[i];
			spin_unlock_irqrestore(&t->lock, flags);
			pmic_program_irqtype(i, type);
			spin_lock_irqsave(&t->lock, flags);
		}
	}
	spin_unlock_irqrestore(&t->lock, flags);
}

static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	if (offset > 8) {
		printk(KERN_ERR
			"%s: only pin 0-7 support input\n", __func__);
		return -1;/* we only have 8 GPIO can use as input */
	}
	return intel_scu_ipc_update_register(GPIO0 + offset,
							GPIO_DIR, GPIO_DIR);
}

static int pmic_gpio_direction_output(struct gpio_chip *chip,
			unsigned offset, int value)
{
	int rc = 0;

	if (offset < 8)/* it is GPIO */
		rc = intel_scu_ipc_update_register(GPIO0 + offset,
				GPIO_DRV | (value ? GPIO_DOU : 0),
				GPIO_DRV | GPIO_DOU | GPIO_DIR);
	else if (offset < 16)/* it is GPOSW */
		rc = intel_scu_ipc_update_register(GPOSWCTL0 + offset - 8,
				GPOSW_DRV | (value ? GPOSW_DOU : 0),
				GPOSW_DRV | GPOSW_DOU | GPOSW_RDRV);
	else if (offset > 15 && offset < 24)/* it is GPO */
		rc = intel_scu_ipc_update_register(GPO,
				value ? 1 << (offset - 16) : 0,
				1 << (offset - 16));
	else {
		printk(KERN_ERR
			"%s: invalid PMIC GPIO pin %d!\n", __func__, offset);
		WARN_ON(1);
	}

	return rc;
}

static int pmic_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	u8 r;
	int ret;

	/* we only have 8 GPIO pins we can use as input */
	if (offset > 8)
		return -EOPNOTSUPP;
	ret = intel_scu_ipc_ioread8(GPIO0 + offset, &r);
	if (ret < 0)
		return ret;
	return r & GPIO_DIN;
}

static void pmic_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	if (offset < 8)/* it is GPIO */
		intel_scu_ipc_update_register(GPIO0 + offset,
			GPIO_DRV | (value ? GPIO_DOU : 0),
			GPIO_DRV | GPIO_DOU);
	else if (offset < 16)/* it is GPOSW */
		intel_scu_ipc_update_register(GPOSWCTL0 + offset - 8,
			GPOSW_DRV | (value ? GPOSW_DOU : 0),
			GPOSW_DRV | GPOSW_DOU | GPOSW_RDRV);
	else if (offset > 15 && offset < 24) /* it is GPO */
		intel_scu_ipc_update_register(GPO,
			value ? 1 << (offset - 16) : 0,
			1 << (offset - 16));
}

static int pmic_irq_type(unsigned irq, unsigned type)
{
	struct pmic_gpio *pg = get_irq_chip_data(irq);
	u32 gpio = irq - pg->irq_base;
	unsigned long flags;

	if (gpio >= pg->chip.ngpio)
		return -EINVAL;

	spin_lock_irqsave(&pg->irqtypes.lock, flags);
	pg->irqtypes.trigger[gpio] = type;
	pg->irqtypes.dirty |=  (1 << gpio);
	spin_unlock_irqrestore(&pg->irqtypes.lock, flags);
	schedule_work(&pg->irqtypes.work);
	return 0;
}



static int pmic_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	struct pmic_gpio *pg = container_of(chip, struct pmic_gpio, chip);

	return pg->irq_base + offset;
}

/* the gpiointr register is read-clear, so just do nothing. */
static void pmic_irq_unmask(unsigned irq)
{
};

static void pmic_irq_mask(unsigned irq)
{
};

static struct irq_chip pmic_irqchip = {
	.name		= "PMIC-GPIO",
	.mask		= pmic_irq_mask,
	.unmask		= pmic_irq_unmask,
	.set_type	= pmic_irq_type,
};

static void pmic_irq_handler(unsigned irq, struct irq_desc *desc)
{
	struct pmic_gpio *pg = (struct pmic_gpio *)get_irq_data(irq);
	u8 intsts = *((u8 *)pg->gpiointr + 4);
	int gpio;

	for (gpio = 0; gpio < 8; gpio++) {
		if (intsts & (1 << gpio)) {
			pr_debug("pmic pin %d triggered\n", gpio);
			generic_handle_irq(pg->irq_base + gpio);
		}
	}

	if (desc->chip->irq_eoi)
		desc->chip->irq_eoi(irq_get_irq_data(irq));
	else
		dev_warn(pg->chip.dev, "missing EOI handler for irq %d\n", irq);
}

static int __devinit platform_pmic_gpio_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	int irq = platform_get_irq(pdev, 0);
	struct intel_pmic_gpio_platform_data *pdata = dev->platform_data;

	struct pmic_gpio *pg;
	int retval;
	int i;

	if (irq < 0) {
		dev_dbg(dev, "no IRQ line\n");
		return -EINVAL;
	}

	if (!pdata || !pdata->gpio_base || !pdata->irq_base) {
		dev_dbg(dev, "incorrect or missing platform data\n");
		return -EINVAL;
	}

	pg = kzalloc(sizeof(*pg), GFP_KERNEL);
	if (!pg)
		return -ENOMEM;

	dev_set_drvdata(dev, pg);

	pg->irq = irq;
	/* setting up SRAM mapping for GPIOINT register */
	pg->gpiointr = ioremap_nocache(pdata->gpiointr, 8);
	if (!pg->gpiointr) {
		printk(KERN_ERR "%s: Can not map GPIOINT.\n", __func__);
		retval = -EINVAL;
		goto err2;
	}
	pg->irq_base = pdata->irq_base;
	pg->chip.label = "intel_pmic";
	pg->chip.direction_input = pmic_gpio_direction_input;
	pg->chip.direction_output = pmic_gpio_direction_output;
	pg->chip.get = pmic_gpio_get;
	pg->chip.set = pmic_gpio_set;
	pg->chip.to_irq = pmic_gpio_to_irq;
	pg->chip.base = pdata->gpio_base;
	pg->chip.ngpio = NUM_GPIO;
	pg->chip.can_sleep = 1;
	pg->chip.dev = dev;

	INIT_WORK(&pg->irqtypes.work, pmic_irqtype_work);
	spin_lock_init(&pg->irqtypes.lock);

	pg->chip.dev = dev;
	retval = gpiochip_add(&pg->chip);
	if (retval) {
		printk(KERN_ERR "%s: Can not add pmic gpio chip.\n", __func__);
		goto err;
	}
	set_irq_data(pg->irq, pg);
	set_irq_chained_handler(pg->irq, pmic_irq_handler);
	for (i = 0; i < 8; i++) {
		set_irq_chip_and_handler_name(i + pg->irq_base, &pmic_irqchip,
					handle_simple_irq, "demux");
		set_irq_chip_data(i + pg->irq_base, pg);
	}
	return 0;
err:
	iounmap(pg->gpiointr);
err2:
	kfree(pg);
	return retval;
}

/* at the same time, register a platform driver
 * this supports the sfi 0.81 fw */
static struct platform_driver platform_pmic_gpio_driver = {
	.driver = {
		.name		= DRIVER_NAME,
		.owner		= THIS_MODULE,
	},
	.probe		= platform_pmic_gpio_probe,
};

static int __init platform_pmic_gpio_init(void)
{
	return platform_driver_register(&platform_pmic_gpio_driver);
}

subsys_initcall(platform_pmic_gpio_init);

MODULE_AUTHOR("Alek Du <alek.du@intel.com>");
MODULE_DESCRIPTION("Intel Moorestown PMIC GPIO driver");
MODULE_LICENSE("GPL v2");
OpenPOWER on IntegriCloud