summaryrefslogtreecommitdiffstats
path: root/drivers/net/wireless/rtl8187.h
blob: 6124e467b156467d2f7101806a78d29d5edbf531 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
/*
 * Definitions for RTL8187 hardware
 *
 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
 * Copyright 2007 Andrea Merello <andreamrl@tiscali.it>
 *
 * Based on the r8187 driver, which is:
 * Copyright 2005 Andrea Merello <andreamrl@tiscali.it>, et al.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef RTL8187_H
#define RTL8187_H

#include "rtl818x.h"

#define RTL8187_EEPROM_TXPWR_BASE	0x05
#define RTL8187_EEPROM_MAC_ADDR		0x07
#define RTL8187_EEPROM_TXPWR_CHAN_1	0x16	/* 3 channels */
#define RTL8187_EEPROM_TXPWR_CHAN_6	0x1B	/* 2 channels */
#define RTL8187_EEPROM_TXPWR_CHAN_4	0x3D	/* 2 channels */

#define RTL8187_REQT_READ	0xC0
#define RTL8187_REQT_WRITE	0x40
#define RTL8187_REQ_GET_REG	0x05
#define RTL8187_REQ_SET_REG	0x05

#define RTL8187_MAX_RX		0x9C4

struct rtl8187_rx_info {
	struct urb *urb;
	struct ieee80211_hw *dev;
};

struct rtl8187_rx_hdr {
	__le16 len;
	__le16 rate;
	u8 noise;
	u8 signal;
	u8 agc;
	u8 reserved;
	__le64 mac_time;
} __attribute__((packed));

struct rtl8187_tx_info {
	struct ieee80211_tx_control *control;
	struct urb *urb;
	struct ieee80211_hw *dev;
};

struct rtl8187_tx_hdr {
	__le32 flags;
#define RTL8187_TX_FLAG_NO_ENCRYPT	(1 << 15)
#define RTL8187_TX_FLAG_MORE_FRAG	(1 << 17)
#define RTL8187_TX_FLAG_CTS		(1 << 18)
#define RTL8187_TX_FLAG_RTS		(1 << 23)
	__le16 rts_duration;
	__le16 len;
	__le32 retry;
} __attribute__((packed));

struct rtl8187_priv {
	/* common between rtl818x drivers */
	struct rtl818x_csr *map;
	void (*rf_init)(struct ieee80211_hw *);
	int mode;

	/* rtl8187 specific */
	struct ieee80211_channel channels[14];
	struct ieee80211_rate rates[12];
	struct ieee80211_hw_mode modes[2];
	struct usb_device *udev;
	u8 *hwaddr;
	u16 txpwr_base;
	u8 asic_rev;
	struct sk_buff_head rx_queue;
};

void rtl8187_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data);

static inline u8 rtl818x_ioread8(struct rtl8187_priv *priv, u8 *addr)
{
	u8 val;

	usb_control_msg(priv->udev, usb_rcvctrlpipe(priv->udev, 0),
			RTL8187_REQ_GET_REG, RTL8187_REQT_READ,
			(unsigned long)addr, 0, &val, sizeof(val), HZ / 2);

	return val;
}

static inline u16 rtl818x_ioread16(struct rtl8187_priv *priv, __le16 *addr)
{
	__le16 val;

	usb_control_msg(priv->udev, usb_rcvctrlpipe(priv->udev, 0),
			RTL8187_REQ_GET_REG, RTL8187_REQT_READ,
			(unsigned long)addr, 0, &val, sizeof(val), HZ / 2);

	return le16_to_cpu(val);
}

static inline u32 rtl818x_ioread32(struct rtl8187_priv *priv, __le32 *addr)
{
	__le32 val;

	usb_control_msg(priv->udev, usb_rcvctrlpipe(priv->udev, 0),
			RTL8187_REQ_GET_REG, RTL8187_REQT_READ,
			(unsigned long)addr, 0, &val, sizeof(val), HZ / 2);

	return le32_to_cpu(val);
}

static inline void rtl818x_iowrite8(struct rtl8187_priv *priv,
				    u8 *addr, u8 val)
{
	usb_control_msg(priv->udev, usb_sndctrlpipe(priv->udev, 0),
			RTL8187_REQ_SET_REG, RTL8187_REQT_WRITE,
			(unsigned long)addr, 0, &val, sizeof(val), HZ / 2);
}

static inline void rtl818x_iowrite16(struct rtl8187_priv *priv,
				     __le16 *addr, u16 val)
{
	__le16 buf = cpu_to_le16(val);

	usb_control_msg(priv->udev, usb_sndctrlpipe(priv->udev, 0),
			RTL8187_REQ_SET_REG, RTL8187_REQT_WRITE,
			(unsigned long)addr, 0, &buf, sizeof(buf), HZ / 2);
}

static inline void rtl818x_iowrite32(struct rtl8187_priv *priv,
				     __le32 *addr, u32 val)
{
	__le32 buf = cpu_to_le32(val);

	usb_control_msg(priv->udev, usb_sndctrlpipe(priv->udev, 0),
			RTL8187_REQ_SET_REG, RTL8187_REQT_WRITE,
			(unsigned long)addr, 0, &buf, sizeof(buf), HZ / 2);
}

#endif /* RTL8187_H */
OpenPOWER on IntegriCloud