summaryrefslogtreecommitdiffstats
path: root/drivers/mtd/lpddr/lpddr2_nvm.c
blob: 2342277c9bcb063f3c1c4691ecfe467cac04dfa8 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
/*
 * LPDDR2-NVM MTD driver. This module provides read, write, erase, lock/unlock
 * support for LPDDR2-NVM PCM memories
 *
 * Copyright © 2012 Micron Technology, Inc.
 *
 * Vincenzo Aliberti <vincenzo.aliberti@gmail.com>
 * Domenico Manna <domenico.manna@gmail.com>
 * Many thanks to Andrea Vigilante for initial enabling
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": %s: " fmt, __func__

#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/mtd/map.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/ioport.h>
#include <linux/err.h>

/* Parameters */
#define ERASE_BLOCKSIZE			(0x00020000/2)	/* in Word */
#define WRITE_BUFFSIZE			(0x00000400/2)	/* in Word */
#define OW_BASE_ADDRESS			0x00000000	/* OW offset */
#define BUS_WIDTH			0x00000020	/* x32 devices */

/* PFOW symbols address offset */
#define PFOW_QUERY_STRING_P		(0x0000/2)	/* in Word */
#define PFOW_QUERY_STRING_F		(0x0002/2)	/* in Word */
#define PFOW_QUERY_STRING_O		(0x0004/2)	/* in Word */
#define PFOW_QUERY_STRING_W		(0x0006/2)	/* in Word */

/* OW registers address */
#define CMD_CODE_OFS			(0x0080/2)	/* in Word */
#define CMD_DATA_OFS			(0x0084/2)	/* in Word */
#define CMD_ADD_L_OFS			(0x0088/2)	/* in Word */
#define CMD_ADD_H_OFS			(0x008A/2)	/* in Word */
#define MPR_L_OFS			(0x0090/2)	/* in Word */
#define MPR_H_OFS			(0x0092/2)	/* in Word */
#define CMD_EXEC_OFS			(0x00C0/2)	/* in Word */
#define STATUS_REG_OFS			(0x00CC/2)	/* in Word */
#define PRG_BUFFER_OFS			(0x0010/2)	/* in Word */

/* Datamask */
#define MR_CFGMASK			0x8000
#define SR_OK_DATAMASK			0x0080

/* LPDDR2-NVM Commands */
#define LPDDR2_NVM_LOCK			0x0061
#define LPDDR2_NVM_UNLOCK		0x0062
#define LPDDR2_NVM_SW_PROGRAM		0x0041
#define LPDDR2_NVM_SW_OVERWRITE		0x0042
#define LPDDR2_NVM_BUF_PROGRAM		0x00E9
#define LPDDR2_NVM_BUF_OVERWRITE	0x00EA
#define LPDDR2_NVM_ERASE		0x0020

/* LPDDR2-NVM Registers offset */
#define LPDDR2_MODE_REG_DATA		0x0040
#define LPDDR2_MODE_REG_CFG		0x0050

/*
 * Internal Type Definitions
 * pcm_int_data contains memory controller details:
 * @reg_data : LPDDR2_MODE_REG_DATA register address after remapping
 * @reg_cfg  : LPDDR2_MODE_REG_CFG register address after remapping
 * &bus_width: memory bus-width (eg: x16 2 Bytes, x32 4 Bytes)
 */
struct pcm_int_data {
	void __iomem *ctl_regs;
	int bus_width;
};

static DEFINE_MUTEX(lpdd2_nvm_mutex);

/*
 * Build a map_word starting from an u_long
 */
static inline map_word build_map_word(u_long myword)
{
	map_word val = { {0} };
	val.x[0] = myword;
	return val;
}

/*
 * Build Mode Register Configuration DataMask based on device bus-width
 */
static inline u_int build_mr_cfgmask(u_int bus_width)
{
	u_int val = MR_CFGMASK;

	if (bus_width == 0x0004)		/* x32 device */
		val = val << 16;

	return val;
}

/*
 * Build Status Register OK DataMask based on device bus-width
 */
static inline u_int build_sr_ok_datamask(u_int bus_width)
{
	u_int val = SR_OK_DATAMASK;

	if (bus_width == 0x0004)		/* x32 device */
		val = (val << 16)+val;

	return val;
}

/*
 * Evaluates Overlay Window Control Registers address
 */
static inline u_long ow_reg_add(struct map_info *map, u_long offset)
{
	u_long val = 0;
	struct pcm_int_data *pcm_data = map->fldrv_priv;

	val = map->pfow_base + offset*pcm_data->bus_width;

	return val;
}

/*
 * Enable lpddr2-nvm Overlay Window
 * Overlay Window is a memory mapped area containing all LPDDR2-NVM registers
 * used by device commands as well as uservisible resources like Device Status
 * Register, Device ID, etc
 */
static inline void ow_enable(struct map_info *map)
{
	struct pcm_int_data *pcm_data = map->fldrv_priv;

	writel_relaxed(build_mr_cfgmask(pcm_data->bus_width) | 0x18,
		pcm_data->ctl_regs + LPDDR2_MODE_REG_CFG);
	writel_relaxed(0x01, pcm_data->ctl_regs + LPDDR2_MODE_REG_DATA);
}

/*
 * Disable lpddr2-nvm Overlay Window
 * Overlay Window is a memory mapped area containing all LPDDR2-NVM registers
 * used by device commands as well as uservisible resources like Device Status
 * Register, Device ID, etc
 */
static inline void ow_disable(struct map_info *map)
{
	struct pcm_int_data *pcm_data = map->fldrv_priv;

	writel_relaxed(build_mr_cfgmask(pcm_data->bus_width) | 0x18,
		pcm_data->ctl_regs + LPDDR2_MODE_REG_CFG);
	writel_relaxed(0x02, pcm_data->ctl_regs + LPDDR2_MODE_REG_DATA);
}

/*
 * Execute lpddr2-nvm operations
 */
static int lpddr2_nvm_do_op(struct map_info *map, u_long cmd_code,
	u_long cmd_data, u_long cmd_add, u_long cmd_mpr, u_char *buf)
{
	map_word add_l = { {0} }, add_h = { {0} }, mpr_l = { {0} },
		mpr_h = { {0} }, data_l = { {0} }, cmd = { {0} },
		exec_cmd = { {0} }, sr;
	map_word data_h = { {0} };	/* only for 2x x16 devices stacked */
	u_long i, status_reg, prg_buff_ofs;
	struct pcm_int_data *pcm_data = map->fldrv_priv;
	u_int sr_ok_datamask = build_sr_ok_datamask(pcm_data->bus_width);

	/* Builds low and high words for OW Control Registers */
	add_l.x[0]	= cmd_add & 0x0000FFFF;
	add_h.x[0]	= (cmd_add >> 16) & 0x0000FFFF;
	mpr_l.x[0]	= cmd_mpr & 0x0000FFFF;
	mpr_h.x[0]	= (cmd_mpr >> 16) & 0x0000FFFF;
	cmd.x[0]	= cmd_code & 0x0000FFFF;
	exec_cmd.x[0]	= 0x0001;
	data_l.x[0]	= cmd_data & 0x0000FFFF;
	data_h.x[0]	= (cmd_data >> 16) & 0x0000FFFF; /* only for 2x x16 */

	/* Set Overlay Window Control Registers */
	map_write(map, cmd, ow_reg_add(map, CMD_CODE_OFS));
	map_write(map, data_l, ow_reg_add(map, CMD_DATA_OFS));
	map_write(map, add_l, ow_reg_add(map, CMD_ADD_L_OFS));
	map_write(map, add_h, ow_reg_add(map, CMD_ADD_H_OFS));
	map_write(map, mpr_l, ow_reg_add(map, MPR_L_OFS));
	map_write(map, mpr_h, ow_reg_add(map, MPR_H_OFS));
	if (pcm_data->bus_width == 0x0004) {	/* 2x16 devices stacked */
		map_write(map, cmd, ow_reg_add(map, CMD_CODE_OFS) + 2);
		map_write(map, data_h, ow_reg_add(map, CMD_DATA_OFS) + 2);
		map_write(map, add_l, ow_reg_add(map, CMD_ADD_L_OFS) + 2);
		map_write(map, add_h, ow_reg_add(map, CMD_ADD_H_OFS) + 2);
		map_write(map, mpr_l, ow_reg_add(map, MPR_L_OFS) + 2);
		map_write(map, mpr_h, ow_reg_add(map, MPR_H_OFS) + 2);
	}

	/* Fill Program Buffer */
	if ((cmd_code == LPDDR2_NVM_BUF_PROGRAM) ||
		(cmd_code == LPDDR2_NVM_BUF_OVERWRITE)) {
		prg_buff_ofs = (map_read(map,
			ow_reg_add(map, PRG_BUFFER_OFS))).x[0];
		for (i = 0; i < cmd_mpr; i++) {
			map_write(map, build_map_word(buf[i]), map->pfow_base +
			prg_buff_ofs + i);
		}
	}

	/* Command Execute */
	map_write(map, exec_cmd, ow_reg_add(map, CMD_EXEC_OFS));
	if (pcm_data->bus_width == 0x0004)	/* 2x16 devices stacked */
		map_write(map, exec_cmd, ow_reg_add(map, CMD_EXEC_OFS) + 2);

	/* Status Register Check */
	do {
		sr = map_read(map, ow_reg_add(map, STATUS_REG_OFS));
		status_reg = sr.x[0];
		if (pcm_data->bus_width == 0x0004) {/* 2x16 devices stacked */
			sr = map_read(map, ow_reg_add(map,
				STATUS_REG_OFS) + 2);
			status_reg += sr.x[0] << 16;
		}
	} while ((status_reg & sr_ok_datamask) != sr_ok_datamask);

	return (((status_reg & sr_ok_datamask) == sr_ok_datamask) ? 0 : -EIO);
}

/*
 * Execute lpddr2-nvm operations @ block level
 */
static int lpddr2_nvm_do_block_op(struct mtd_info *mtd, loff_t start_add,
	uint64_t len, u_char block_op)
{
	struct map_info *map = mtd->priv;
	u_long add, end_add;
	int ret = 0;

	mutex_lock(&lpdd2_nvm_mutex);

	ow_enable(map);

	add = start_add;
	end_add = add + len;

	do {
		ret = lpddr2_nvm_do_op(map, block_op, 0x00, add, add, NULL);
		if (ret)
			goto out;
		add += mtd->erasesize;
	} while (add < end_add);

out:
	ow_disable(map);
	mutex_unlock(&lpdd2_nvm_mutex);
	return ret;
}

/*
 * verify presence of PFOW string
 */
static int lpddr2_nvm_pfow_present(struct map_info *map)
{
	map_word pfow_val[4];
	unsigned int found = 1;

	mutex_lock(&lpdd2_nvm_mutex);

	ow_enable(map);

	/* Load string from array */
	pfow_val[0] = map_read(map, ow_reg_add(map, PFOW_QUERY_STRING_P));
	pfow_val[1] = map_read(map, ow_reg_add(map, PFOW_QUERY_STRING_F));
	pfow_val[2] = map_read(map, ow_reg_add(map, PFOW_QUERY_STRING_O));
	pfow_val[3] = map_read(map, ow_reg_add(map, PFOW_QUERY_STRING_W));

	/* Verify the string loaded vs expected */
	if (!map_word_equal(map, build_map_word('P'), pfow_val[0]))
		found = 0;
	if (!map_word_equal(map, build_map_word('F'), pfow_val[1]))
		found = 0;
	if (!map_word_equal(map, build_map_word('O'), pfow_val[2]))
		found = 0;
	if (!map_word_equal(map, build_map_word('W'), pfow_val[3]))
		found = 0;

	ow_disable(map);

	mutex_unlock(&lpdd2_nvm_mutex);

	return found;
}

/*
 * lpddr2_nvm driver read method
 */
static int lpddr2_nvm_read(struct mtd_info *mtd, loff_t start_add,
				size_t len, size_t *retlen, u_char *buf)
{
	struct map_info *map = mtd->priv;

	mutex_lock(&lpdd2_nvm_mutex);

	*retlen = len;

	map_copy_from(map, buf, start_add, *retlen);

	mutex_unlock(&lpdd2_nvm_mutex);
	return 0;
}

/*
 * lpddr2_nvm driver write method
 */
static int lpddr2_nvm_write(struct mtd_info *mtd, loff_t start_add,
				size_t len, size_t *retlen, const u_char *buf)
{
	struct map_info *map = mtd->priv;
	struct pcm_int_data *pcm_data = map->fldrv_priv;
	u_long add, current_len, tot_len, target_len, my_data;
	u_char *write_buf = (u_char *)buf;
	int ret = 0;

	mutex_lock(&lpdd2_nvm_mutex);

	ow_enable(map);

	/* Set start value for the variables */
	add = start_add;
	target_len = len;
	tot_len = 0;

	while (tot_len < target_len) {
		if (!(IS_ALIGNED(add, mtd->writesize))) { /* do sw program */
			my_data = write_buf[tot_len];
			my_data += (write_buf[tot_len+1]) << 8;
			if (pcm_data->bus_width == 0x0004) {/* 2x16 devices */
				my_data += (write_buf[tot_len+2]) << 16;
				my_data += (write_buf[tot_len+3]) << 24;
			}
			ret = lpddr2_nvm_do_op(map, LPDDR2_NVM_SW_OVERWRITE,
				my_data, add, 0x00, NULL);
			if (ret)
				goto out;

			add += pcm_data->bus_width;
			tot_len += pcm_data->bus_width;
		} else {		/* do buffer program */
			current_len = min(target_len - tot_len,
				(u_long) mtd->writesize);
			ret = lpddr2_nvm_do_op(map, LPDDR2_NVM_BUF_OVERWRITE,
				0x00, add, current_len, write_buf + tot_len);
			if (ret)
				goto out;

			add += current_len;
			tot_len += current_len;
		}
	}

out:
	*retlen = tot_len;
	ow_disable(map);
	mutex_unlock(&lpdd2_nvm_mutex);
	return ret;
}

/*
 * lpddr2_nvm driver erase method
 */
static int lpddr2_nvm_erase(struct mtd_info *mtd, struct erase_info *instr)
{
	int ret = lpddr2_nvm_do_block_op(mtd, instr->addr, instr->len,
		LPDDR2_NVM_ERASE);
	if (!ret) {
		instr->state = MTD_ERASE_DONE;
		mtd_erase_callback(instr);
	}

	return ret;
}

/*
 * lpddr2_nvm driver unlock method
 */
static int lpddr2_nvm_unlock(struct mtd_info *mtd, loff_t start_add,
	uint64_t len)
{
	return lpddr2_nvm_do_block_op(mtd, start_add, len, LPDDR2_NVM_UNLOCK);
}

/*
 * lpddr2_nvm driver lock method
 */
static int lpddr2_nvm_lock(struct mtd_info *mtd, loff_t start_add,
	uint64_t len)
{
	return lpddr2_nvm_do_block_op(mtd, start_add, len, LPDDR2_NVM_LOCK);
}

/*
 * lpddr2_nvm driver probe method
 */
static int lpddr2_nvm_probe(struct platform_device *pdev)
{
	struct map_info *map;
	struct mtd_info *mtd;
	struct resource *add_range;
	struct resource *control_regs;
	struct pcm_int_data *pcm_data;

	/* Allocate memory control_regs data structures */
	pcm_data = devm_kzalloc(&pdev->dev, sizeof(*pcm_data), GFP_KERNEL);
	if (!pcm_data)
		return -ENOMEM;

	pcm_data->bus_width = BUS_WIDTH;

	/* Allocate memory for map_info & mtd_info data structures */
	map = devm_kzalloc(&pdev->dev, sizeof(*map), GFP_KERNEL);
	if (!map)
		return -ENOMEM;

	mtd = devm_kzalloc(&pdev->dev, sizeof(*mtd), GFP_KERNEL);
	if (!mtd)
		return -ENOMEM;

	/* lpddr2_nvm address range */
	add_range = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	/* Populate map_info data structure */
	*map = (struct map_info) {
		.virt		= devm_ioremap_resource(&pdev->dev, add_range),
		.name		= pdev->dev.init_name,
		.phys		= add_range->start,
		.size		= resource_size(add_range),
		.bankwidth	= pcm_data->bus_width / 2,
		.pfow_base	= OW_BASE_ADDRESS,
		.fldrv_priv	= pcm_data,
	};
	if (IS_ERR(map->virt))
		return PTR_ERR(map->virt);

	simple_map_init(map);	/* fill with default methods */

	control_regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	pcm_data->ctl_regs = devm_ioremap_resource(&pdev->dev, control_regs);
	if (IS_ERR(pcm_data->ctl_regs))
		return PTR_ERR(pcm_data->ctl_regs);

	/* Populate mtd_info data structure */
	*mtd = (struct mtd_info) {
		.dev		= { .parent = &pdev->dev },
		.name		= pdev->dev.init_name,
		.type		= MTD_RAM,
		.priv		= map,
		.size		= resource_size(add_range),
		.erasesize	= ERASE_BLOCKSIZE * pcm_data->bus_width,
		.writesize	= 1,
		.writebufsize	= WRITE_BUFFSIZE * pcm_data->bus_width,
		.flags		= (MTD_CAP_NVRAM | MTD_POWERUP_LOCK),
		._read		= lpddr2_nvm_read,
		._write		= lpddr2_nvm_write,
		._erase		= lpddr2_nvm_erase,
		._unlock	= lpddr2_nvm_unlock,
		._lock		= lpddr2_nvm_lock,
	};

	/* Verify the presence of the device looking for PFOW string */
	if (!lpddr2_nvm_pfow_present(map)) {
		pr_err("device not recognized\n");
		return -EINVAL;
	}
	/* Parse partitions and register the MTD device */
	return mtd_device_parse_register(mtd, NULL, NULL, NULL, 0);
}

/*
 * lpddr2_nvm driver remove method
 */
static int lpddr2_nvm_remove(struct platform_device *pdev)
{
	return mtd_device_unregister(dev_get_drvdata(&pdev->dev));
}

/* Initialize platform_driver data structure for lpddr2_nvm */
static struct platform_driver lpddr2_nvm_drv = {
	.driver		= {
		.name	= "lpddr2_nvm",
	},
	.probe		= lpddr2_nvm_probe,
	.remove		= lpddr2_nvm_remove,
};

module_platform_driver(lpddr2_nvm_drv);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Vincenzo Aliberti <vincenzo.aliberti@gmail.com>");
MODULE_DESCRIPTION("MTD driver for LPDDR2-NVM PCM memories");
OpenPOWER on IntegriCloud