summaryrefslogtreecommitdiffstats
path: root/drivers/infiniband/hw/ocrdma/ocrdma_sli.h
blob: 9f9570ec3c2ee300f828e8275820ca7c25b9e71d (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
/*******************************************************************
 * This file is part of the Emulex RoCE Device Driver for          *
 * RoCE (RDMA over Converged Ethernet) adapters.                   *
 * Copyright (C) 2008-2012 Emulex. All rights reserved.            *
 * EMULEX and SLI are trademarks of Emulex.                        *
 * www.emulex.com                                                  *
 *                                                                 *
 * This program is free software; you can redistribute it and/or   *
 * modify it under the terms of version 2 of the GNU General       *
 * Public License as published by the Free Software Foundation.    *
 * This program is distributed in the hope that it will be useful. *
 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
 * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
 * more details, a copy of which can be found in the file COPYING  *
 * included with this package.                                     *
 *
 * Contact Information:
 * linux-drivers@emulex.com
 *
 * Emulex
 * 3333 Susan Street
 * Costa Mesa, CA 92626
 *******************************************************************/

#ifndef __OCRDMA_SLI_H__
#define __OCRDMA_SLI_H__

#define Bit(_b) (1 << (_b))

#define OCRDMA_GEN1_FAMILY	0xB
#define OCRDMA_GEN2_FAMILY	0x2

#define OCRDMA_SUBSYS_ROCE 10
enum {
	OCRDMA_CMD_QUERY_CONFIG = 1,
	OCRDMA_CMD_ALLOC_PD,
	OCRDMA_CMD_DEALLOC_PD,

	OCRDMA_CMD_CREATE_AH_TBL,
	OCRDMA_CMD_DELETE_AH_TBL,

	OCRDMA_CMD_CREATE_QP,
	OCRDMA_CMD_QUERY_QP,
	OCRDMA_CMD_MODIFY_QP,
	OCRDMA_CMD_DELETE_QP,

	OCRDMA_CMD_RSVD1,
	OCRDMA_CMD_ALLOC_LKEY,
	OCRDMA_CMD_DEALLOC_LKEY,
	OCRDMA_CMD_REGISTER_NSMR,
	OCRDMA_CMD_REREGISTER_NSMR,
	OCRDMA_CMD_REGISTER_NSMR_CONT,
	OCRDMA_CMD_QUERY_NSMR,
	OCRDMA_CMD_ALLOC_MW,
	OCRDMA_CMD_QUERY_MW,

	OCRDMA_CMD_CREATE_SRQ,
	OCRDMA_CMD_QUERY_SRQ,
	OCRDMA_CMD_MODIFY_SRQ,
	OCRDMA_CMD_DELETE_SRQ,

	OCRDMA_CMD_ATTACH_MCAST,
	OCRDMA_CMD_DETACH_MCAST,

	OCRDMA_CMD_MAX
};

#define OCRDMA_SUBSYS_COMMON 1
enum {
	OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1 = 5,
	OCRDMA_CMD_CREATE_CQ		= 12,
	OCRDMA_CMD_CREATE_EQ		= 13,
	OCRDMA_CMD_CREATE_MQ		= 21,
	OCRDMA_CMD_GET_FW_VER		= 35,
	OCRDMA_CMD_DELETE_MQ		= 53,
	OCRDMA_CMD_DELETE_CQ		= 54,
	OCRDMA_CMD_DELETE_EQ		= 55,
	OCRDMA_CMD_GET_FW_CONFIG	= 58,
	OCRDMA_CMD_CREATE_MQ_EXT	= 90
};

enum {
	QTYPE_EQ	= 1,
	QTYPE_CQ	= 2,
	QTYPE_MCCQ	= 3
};

#define OCRDMA_MAX_SGID (8)

#define OCRDMA_MAX_QP    2048
#define OCRDMA_MAX_CQ    2048
#define OCRDMA_MAX_STAG  8192

enum {
	OCRDMA_DB_RQ_OFFSET		= 0xE0,
	OCRDMA_DB_GEN2_RQ_OFFSET        = 0x100,
	OCRDMA_DB_SQ_OFFSET		= 0x60,
	OCRDMA_DB_GEN2_SQ_OFFSET	= 0x1C0,
	OCRDMA_DB_SRQ_OFFSET		= OCRDMA_DB_RQ_OFFSET,
	OCRDMA_DB_GEN2_SRQ_OFFSET	= OCRDMA_DB_GEN2_RQ_OFFSET,
	OCRDMA_DB_CQ_OFFSET		= 0x120,
	OCRDMA_DB_EQ_OFFSET		= OCRDMA_DB_CQ_OFFSET,
	OCRDMA_DB_MQ_OFFSET		= 0x140
};

#define OCRDMA_DB_CQ_RING_ID_MASK       0x3FF	/* bits 0 - 9 */
#define OCRDMA_DB_CQ_RING_ID_EXT_MASK  0x0C00	/* bits 10-11 of qid at 12-11 */
/* qid #2 msbits at 12-11 */
#define OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT  0x1
#define OCRDMA_DB_CQ_NUM_POPPED_SHIFT       (16)	/* bits 16 - 28 */
/* Rearm bit */
#define OCRDMA_DB_CQ_REARM_SHIFT        (29)	/* bit 29 */
/* solicited bit */
#define OCRDMA_DB_CQ_SOLICIT_SHIFT   (31)	/* bit 31 */

#define OCRDMA_EQ_ID_MASK		0x1FF	/* bits 0 - 8 */
#define OCRDMA_EQ_ID_EXT_MASK		0x3e00	/* bits 9-13 */
#define OCRDMA_EQ_ID_EXT_MASK_SHIFT	(2)	/* qid bits 9-13 at 11-15 */

/* Clear the interrupt for this eq */
#define OCRDMA_EQ_CLR_SHIFT			(9)	/* bit 9 */
/* Must be 1 */
#define OCRDMA_EQ_TYPE_SHIFT		(10)	/* bit 10 */
/* Number of event entries processed */
#define OCRDMA_NUM_EQE_SHIFT		(16)	/* bits 16 - 28 */
/* Rearm bit */
#define OCRDMA_REARM_SHIFT		(29)	/* bit 29 */

#define OCRDMA_MQ_ID_MASK		0x7FF	/* bits 0 - 10 */
/* Number of entries posted */
#define OCRDMA_MQ_NUM_MQE_SHIFT	(16)	/* bits 16 - 29 */

#define OCRDMA_MIN_HPAGE_SIZE (4096)

#define OCRDMA_MIN_Q_PAGE_SIZE (4096)
#define OCRDMA_MAX_Q_PAGES     (8)

/*
# 0: 4K Bytes
# 1: 8K Bytes
# 2: 16K Bytes
# 3: 32K Bytes
# 4: 64K Bytes
# 5: 128K Bytes
# 6: 256K Bytes
# 7: 512K Bytes
*/
#define OCRDMA_MAX_Q_PAGE_SIZE_CNT (8)
#define OCRDMA_Q_PAGE_BASE_SIZE (OCRDMA_MIN_Q_PAGE_SIZE * OCRDMA_MAX_Q_PAGES)

#define MAX_OCRDMA_QP_PAGES      (8)
#define OCRDMA_MAX_WQE_MEM_SIZE (MAX_OCRDMA_QP_PAGES * OCRDMA_MIN_HQ_PAGE_SIZE)

#define OCRDMA_CREATE_CQ_MAX_PAGES (4)
#define OCRDMA_DPP_CQE_SIZE (4)

#define OCRDMA_GEN2_MAX_CQE 1024
#define OCRDMA_GEN2_CQ_PAGE_SIZE 4096
#define OCRDMA_GEN2_WQE_SIZE 256
#define OCRDMA_MAX_CQE  4095
#define OCRDMA_CQ_PAGE_SIZE 16384
#define OCRDMA_WQE_SIZE 128
#define OCRDMA_WQE_STRIDE 8
#define OCRDMA_WQE_ALIGN_BYTES 16

#define MAX_OCRDMA_SRQ_PAGES MAX_OCRDMA_QP_PAGES

enum {
	OCRDMA_MCH_OPCODE_SHIFT	= 0,
	OCRDMA_MCH_OPCODE_MASK	= 0xFF,
	OCRDMA_MCH_SUBSYS_SHIFT	= 8,
	OCRDMA_MCH_SUBSYS_MASK	= 0xFF00
};

/* mailbox cmd header */
struct ocrdma_mbx_hdr {
	u32 subsys_op;
	u32 timeout;		/* in seconds */
	u32 cmd_len;
	u32 rsvd_version;
};

enum {
	OCRDMA_MBX_RSP_OPCODE_SHIFT	= 0,
	OCRDMA_MBX_RSP_OPCODE_MASK	= 0xFF,
	OCRDMA_MBX_RSP_SUBSYS_SHIFT	= 8,
	OCRDMA_MBX_RSP_SUBSYS_MASK	= 0xFF << OCRDMA_MBX_RSP_SUBSYS_SHIFT,

	OCRDMA_MBX_RSP_STATUS_SHIFT	= 0,
	OCRDMA_MBX_RSP_STATUS_MASK	= 0xFF,
	OCRDMA_MBX_RSP_ASTATUS_SHIFT	= 8,
	OCRDMA_MBX_RSP_ASTATUS_MASK	= 0xFF << OCRDMA_MBX_RSP_ASTATUS_SHIFT
};

/* mailbox cmd response */
struct ocrdma_mbx_rsp {
	u32 subsys_op;
	u32 status;
	u32 rsp_len;
	u32 add_rsp_len;
};

enum {
	OCRDMA_MQE_EMBEDDED	= 1,
	OCRDMA_MQE_NONEMBEDDED	= 0
};

struct ocrdma_mqe_sge {
	u32 pa_lo;
	u32 pa_hi;
	u32 len;
};

enum {
	OCRDMA_MQE_HDR_EMB_SHIFT	= 0,
	OCRDMA_MQE_HDR_EMB_MASK		= Bit(0),
	OCRDMA_MQE_HDR_SGE_CNT_SHIFT	= 3,
	OCRDMA_MQE_HDR_SGE_CNT_MASK	= 0x1F << OCRDMA_MQE_HDR_SGE_CNT_SHIFT,
	OCRDMA_MQE_HDR_SPECIAL_SHIFT	= 24,
	OCRDMA_MQE_HDR_SPECIAL_MASK	= 0xFF << OCRDMA_MQE_HDR_SPECIAL_SHIFT
};

struct ocrdma_mqe_hdr {
	u32 spcl_sge_cnt_emb;
	u32 pyld_len;
	u32 tag_lo;
	u32 tag_hi;
	u32 rsvd3;
};

struct ocrdma_mqe_emb_cmd {
	struct ocrdma_mbx_hdr mch;
	u8 pyld[220];
};

struct ocrdma_mqe {
	struct ocrdma_mqe_hdr hdr;
	union {
		struct ocrdma_mqe_emb_cmd emb_req;
		struct {
			struct ocrdma_mqe_sge sge[19];
		} nonemb_req;
		u8 cmd[236];
		struct ocrdma_mbx_rsp rsp;
	} u;
};

#define OCRDMA_EQ_LEN       4096
#define OCRDMA_MQ_CQ_LEN    256
#define OCRDMA_MQ_LEN       128

#define PAGE_SHIFT_4K		12
#define PAGE_SIZE_4K		(1 << PAGE_SHIFT_4K)

/* Returns number of pages spanned by the data starting at the given addr */
#define PAGES_4K_SPANNED(_address, size) \
	((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) +	\
			(size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))

struct ocrdma_delete_q_req {
	struct ocrdma_mbx_hdr req;
	u32 id;
};

struct ocrdma_pa {
	u32 lo;
	u32 hi;
};

#define MAX_OCRDMA_EQ_PAGES (8)
struct ocrdma_create_eq_req {
	struct ocrdma_mbx_hdr req;
	u32 num_pages;
	u32 valid;
	u32 cnt;
	u32 delay;
	u32 rsvd;
	struct ocrdma_pa pa[MAX_OCRDMA_EQ_PAGES];
};

enum {
	OCRDMA_CREATE_EQ_VALID	= Bit(29),
	OCRDMA_CREATE_EQ_CNT_SHIFT	= 26,
	OCRDMA_CREATE_CQ_DELAY_SHIFT	= 13,
};

struct ocrdma_create_eq_rsp {
	struct ocrdma_mbx_rsp rsp;
	u32 vector_eqid;
};

#define OCRDMA_EQ_MINOR_OTHER (0x1)

enum {
	OCRDMA_MCQE_STATUS_SHIFT	= 0,
	OCRDMA_MCQE_STATUS_MASK		= 0xFFFF,
	OCRDMA_MCQE_ESTATUS_SHIFT	= 16,
	OCRDMA_MCQE_ESTATUS_MASK	= 0xFFFF << OCRDMA_MCQE_ESTATUS_SHIFT,
	OCRDMA_MCQE_CONS_SHIFT		= 27,
	OCRDMA_MCQE_CONS_MASK		= Bit(27),
	OCRDMA_MCQE_CMPL_SHIFT		= 28,
	OCRDMA_MCQE_CMPL_MASK		= Bit(28),
	OCRDMA_MCQE_AE_SHIFT		= 30,
	OCRDMA_MCQE_AE_MASK		= Bit(30),
	OCRDMA_MCQE_VALID_SHIFT		= 31,
	OCRDMA_MCQE_VALID_MASK		= Bit(31)
};

struct ocrdma_mcqe {
	u32 status;
	u32 tag_lo;
	u32 tag_hi;
	u32 valid_ae_cmpl_cons;
};

enum {
	OCRDMA_AE_MCQE_QPVALID		= Bit(31),
	OCRDMA_AE_MCQE_QPID_MASK	= 0xFFFF,

	OCRDMA_AE_MCQE_CQVALID		= Bit(31),
	OCRDMA_AE_MCQE_CQID_MASK	= 0xFFFF,
	OCRDMA_AE_MCQE_VALID		= Bit(31),
	OCRDMA_AE_MCQE_AE		= Bit(30),
	OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT	= 16,
	OCRDMA_AE_MCQE_EVENT_TYPE_MASK	=
					0xFF << OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT,
	OCRDMA_AE_MCQE_EVENT_CODE_SHIFT	= 8,
	OCRDMA_AE_MCQE_EVENT_CODE_MASK	=
					0xFF << OCRDMA_AE_MCQE_EVENT_CODE_SHIFT
};
struct ocrdma_ae_mcqe {
	u32 qpvalid_qpid;
	u32 cqvalid_cqid;
	u32 evt_tag;
	u32 valid_ae_event;
};

enum {
	OCRDMA_AE_PVID_MCQE_ENABLED_SHIFT = 0,
	OCRDMA_AE_PVID_MCQE_ENABLED_MASK  = 0xFF,
	OCRDMA_AE_PVID_MCQE_TAG_SHIFT = 16,
	OCRDMA_AE_PVID_MCQE_TAG_MASK = 0xFFFF << OCRDMA_AE_PVID_MCQE_TAG_SHIFT
};

struct ocrdma_ae_pvid_mcqe {
	u32 tag_enabled;
	u32 event_tag;
	u32 rsvd1;
	u32 rsvd2;
};

enum {
	OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT		= 16,
	OCRDMA_AE_MPA_MCQE_REQ_ID_MASK		= 0xFFFF <<
					OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT,

	OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT	= 8,
	OCRDMA_AE_MPA_MCQE_EVENT_CODE_MASK	= 0xFF <<
					OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT,
	OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT	= 16,
	OCRDMA_AE_MPA_MCQE_EVENT_TYPE_MASK	= 0xFF <<
					OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT,
	OCRDMA_AE_MPA_MCQE_EVENT_AE_SHIFT	= 30,
	OCRDMA_AE_MPA_MCQE_EVENT_AE_MASK	= Bit(30),
	OCRDMA_AE_MPA_MCQE_EVENT_VALID_SHIFT	= 31,
	OCRDMA_AE_MPA_MCQE_EVENT_VALID_MASK	= Bit(31)
};

struct ocrdma_ae_mpa_mcqe {
	u32 req_id;
	u32 w1;
	u32 w2;
	u32 valid_ae_event;
};

enum {
	OCRDMA_AE_QP_MCQE_NEW_QP_STATE_SHIFT	= 0,
	OCRDMA_AE_QP_MCQE_NEW_QP_STATE_MASK	= 0xFFFF,
	OCRDMA_AE_QP_MCQE_QP_ID_SHIFT		= 16,
	OCRDMA_AE_QP_MCQE_QP_ID_MASK		= 0xFFFF <<
						OCRDMA_AE_QP_MCQE_QP_ID_SHIFT,

	OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT	= 8,
	OCRDMA_AE_QP_MCQE_EVENT_CODE_MASK	= 0xFF <<
				OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT,
	OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT	= 16,
	OCRDMA_AE_QP_MCQE_EVENT_TYPE_MASK	= 0xFF <<
				OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT,
	OCRDMA_AE_QP_MCQE_EVENT_AE_SHIFT	= 30,
	OCRDMA_AE_QP_MCQE_EVENT_AE_MASK		= Bit(30),
	OCRDMA_AE_QP_MCQE_EVENT_VALID_SHIFT	= 31,
	OCRDMA_AE_QP_MCQE_EVENT_VALID_MASK	= Bit(31)
};

struct ocrdma_ae_qp_mcqe {
	u32 qp_id_state;
	u32 w1;
	u32 w2;
	u32 valid_ae_event;
};

#define OCRDMA_ASYNC_RDMA_EVE_CODE 0x14
#define OCRDMA_ASYNC_GRP5_EVE_CODE 0x5
#define OCRDMA_ASYNC_EVENT_PVID_STATE 0x3

enum OCRDMA_ASYNC_EVENT_TYPE {
	OCRDMA_CQ_ERROR			= 0x00,
	OCRDMA_CQ_OVERRUN_ERROR		= 0x01,
	OCRDMA_CQ_QPCAT_ERROR		= 0x02,
	OCRDMA_QP_ACCESS_ERROR		= 0x03,
	OCRDMA_QP_COMM_EST_EVENT	= 0x04,
	OCRDMA_SQ_DRAINED_EVENT		= 0x05,
	OCRDMA_DEVICE_FATAL_EVENT	= 0x08,
	OCRDMA_SRQCAT_ERROR		= 0x0E,
	OCRDMA_SRQ_LIMIT_EVENT		= 0x0F,
	OCRDMA_QP_LAST_WQE_EVENT	= 0x10
};

/* mailbox command request and responses */
enum {
	OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT		= 2,
	OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK		= Bit(2),
	OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT	= 3,
	OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK		= Bit(3),
	OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT		= 8,
	OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK		= 0xFFFFFF <<
				OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT,

	OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT		= 16,
	OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK		= 0xFFFF <<
					OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT,
	OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT		= 8,
	OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK		= 0xFF <<
				OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT,

	OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT		= 0,
	OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK		= 0xFFFF,
	OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT	= 16,
	OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_MASK		= 0xFFFF <<
				OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT,

	OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT	= 0,
	OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK	= 0xFFFF,
	OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT	= 16,
	OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK	= 0xFFFF <<
				OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT,

	OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET	= 24,
	OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK		= 0xFF <<
				OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET,
	OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET	= 16,
	OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK		= 0xFF <<
				OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET,
	OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET	= 0,
	OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_MASK		= 0xFFFF <<
				OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET,

	OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET		= 16,
	OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK		= 0xFFFF <<
				OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET,
	OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET	= 0,
	OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_MASK		= 0xFFFF <<
				OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET,

	OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET		= 16,
	OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_MASK		= 0xFFFF <<
				OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET,
	OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET	= 0,
	OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_MASK	= 0xFFFF <<
				OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET,

	OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET		= 0,
	OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_MASK		= 0xFFFF <<
				OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET,

	OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET	= 16,
	OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_MASK	= 0xFFFF <<
				OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET,
	OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET	= 0,
	OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK	= 0xFFFF <<
				OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET,

	OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET		= 16,
	OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK		= 0xFFFF <<
				OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET,
	OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET	= 0,
	OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK	= 0xFFFF <<
				OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET,

	OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET		= 16,
	OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_MASK		= 0xFFFF <<
				OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET,
	OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET		= 0,
	OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK		= 0xFFFF <<
				OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET,
};

struct ocrdma_mbx_query_config {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_rsp rsp;
	u32 qp_srq_cq_ird_ord;
	u32 max_pd_ca_ack_delay;
	u32 max_write_send_sge;
	u32 max_ird_ord_per_qp;
	u32 max_shared_ird_ord;
	u32 max_mr;
	u32 max_mr_size_lo;
	u32 max_mr_size_hi;
	u32 max_num_mr_pbl;
	u32 max_mw;
	u32 max_fmr;
	u32 max_pages_per_frmr;
	u32 max_mcast_group;
	u32 max_mcast_qp_attach;
	u32 max_total_mcast_qp_attach;
	u32 wqe_rqe_stride_max_dpp_cqs;
	u32 max_srq_rpir_qps;
	u32 max_dpp_pds_credits;
	u32 max_dpp_credits_pds_per_pd;
	u32 max_wqes_rqes_per_q;
	u32 max_cq_cqes_per_cq;
	u32 max_srq_rqe_sge;
};

struct ocrdma_fw_ver_rsp {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_rsp rsp;

	u8 running_ver[32];
};

struct ocrdma_fw_conf_rsp {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_rsp rsp;

	u32 config_num;
	u32 asic_revision;
	u32 phy_port;
	u32 fn_mode;
	struct {
		u32 mode;
		u32 nic_wqid_base;
		u32 nic_wq_tot;
		u32 prot_wqid_base;
		u32 prot_wq_tot;
		u32 prot_rqid_base;
		u32 prot_rqid_tot;
		u32 rsvd[6];
	} ulp[2];
	u32 fn_capabilities;
	u32 rsvd1;
	u32 rsvd2;
	u32 base_eqid;
	u32 max_eq;

};

enum {
	OCRDMA_FN_MODE_RDMA	= 0x4
};

struct ocrdma_get_link_speed_rsp {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_rsp rsp;

	u8 pt_port_num;
	u8 link_duplex;
	u8 phys_port_speed;
	u8 phys_port_fault;
	u16 rsvd1;
	u16 qos_lnk_speed;
	u8 logical_lnk_status;
	u8 rsvd2[3];
};

enum {
	OCRDMA_PHYS_LINK_SPEED_ZERO = 0x0,
	OCRDMA_PHYS_LINK_SPEED_10MBPS = 0x1,
	OCRDMA_PHYS_LINK_SPEED_100MBPS = 0x2,
	OCRDMA_PHYS_LINK_SPEED_1GBPS = 0x3,
	OCRDMA_PHYS_LINK_SPEED_10GBPS = 0x4,
	OCRDMA_PHYS_LINK_SPEED_20GBPS = 0x5,
	OCRDMA_PHYS_LINK_SPEED_25GBPS = 0x6,
	OCRDMA_PHYS_LINK_SPEED_40GBPS = 0x7,
	OCRDMA_PHYS_LINK_SPEED_100GBPS = 0x8
};

enum {
	OCRDMA_CREATE_CQ_VER2			= 2,
	OCRDMA_CREATE_CQ_VER3                   = 3,

	OCRDMA_CREATE_CQ_PAGE_CNT_MASK		= 0xFFFF,
	OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT	= 16,
	OCRDMA_CREATE_CQ_PAGE_SIZE_MASK		= 0xFF,

	OCRDMA_CREATE_CQ_COALESCWM_SHIFT	= 12,
	OCRDMA_CREATE_CQ_COALESCWM_MASK		= Bit(13) | Bit(12),
	OCRDMA_CREATE_CQ_FLAGS_NODELAY		= Bit(14),
	OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID	= Bit(15),

	OCRDMA_CREATE_CQ_EQ_ID_MASK		= 0xFFFF,
	OCRDMA_CREATE_CQ_CQE_COUNT_MASK		= 0xFFFF
};

enum {
	OCRDMA_CREATE_CQ_VER0			= 0,
	OCRDMA_CREATE_CQ_DPP			= 1,
	OCRDMA_CREATE_CQ_TYPE_SHIFT		= 24,
	OCRDMA_CREATE_CQ_EQID_SHIFT		= 22,

	OCRDMA_CREATE_CQ_CNT_SHIFT		= 27,
	OCRDMA_CREATE_CQ_FLAGS_VALID		= Bit(29),
	OCRDMA_CREATE_CQ_FLAGS_EVENTABLE	= Bit(31),
	OCRDMA_CREATE_CQ_DEF_FLAGS		= OCRDMA_CREATE_CQ_FLAGS_VALID |
					OCRDMA_CREATE_CQ_FLAGS_EVENTABLE |
					OCRDMA_CREATE_CQ_FLAGS_NODELAY
};

struct ocrdma_create_cq_cmd {
	struct ocrdma_mbx_hdr req;
	u32 pgsz_pgcnt;
	u32 ev_cnt_flags;
	u32 eqn;
	u16 cqe_count;
	u16 pd_id;
	u32 rsvd6;
	struct ocrdma_pa pa[OCRDMA_CREATE_CQ_MAX_PAGES];
};

struct ocrdma_create_cq {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_create_cq_cmd cmd;
};

enum {
	OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK	= 0xFFFF
};

struct ocrdma_create_cq_cmd_rsp {
	struct ocrdma_mbx_rsp rsp;
	u32 cq_id;
};

struct ocrdma_create_cq_rsp {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_create_cq_cmd_rsp rsp;
};

enum {
	OCRDMA_CREATE_MQ_V0_CQ_ID_SHIFT		= 22,
	OCRDMA_CREATE_MQ_CQ_ID_SHIFT		= 16,
	OCRDMA_CREATE_MQ_RING_SIZE_SHIFT	= 16,
	OCRDMA_CREATE_MQ_VALID			= Bit(31),
	OCRDMA_CREATE_MQ_ASYNC_CQ_VALID		= Bit(0)
};

struct ocrdma_create_mq_req {
	struct ocrdma_mbx_hdr req;
	u32 cqid_pages;
	u32 async_event_bitmap;
	u32 async_cqid_ringsize;
	u32 valid;
	u32 async_cqid_valid;
	u32 rsvd;
	struct ocrdma_pa pa[8];
};

struct ocrdma_create_mq_rsp {
	struct ocrdma_mbx_rsp rsp;
	u32 id;
};

enum {
	OCRDMA_DESTROY_CQ_QID_SHIFT			= 0,
	OCRDMA_DESTROY_CQ_QID_MASK			= 0xFFFF,
	OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT	= 16,
	OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_MASK		= 0xFFFF <<
				OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT
};

struct ocrdma_destroy_cq {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_hdr req;

	u32 bypass_flush_qid;
};

struct ocrdma_destroy_cq_rsp {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_rsp rsp;
};

enum {
	OCRDMA_QPT_GSI	= 1,
	OCRDMA_QPT_RC	= 2,
	OCRDMA_QPT_UD	= 4,
};

enum {
	OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT	= 0,
	OCRDMA_CREATE_QP_REQ_PD_ID_MASK		= 0xFFFF,
	OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT	= 16,
	OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT	= 19,
	OCRDMA_CREATE_QP_REQ_QPT_SHIFT		= 29,
	OCRDMA_CREATE_QP_REQ_QPT_MASK		= Bit(31) | Bit(30) | Bit(29),

	OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT	= 0,
	OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK	= 0xFFFF,
	OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT	= 16,
	OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK	= 0xFFFF <<
					OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT,

	OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT	= 0,
	OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK		= 0xFFFF,
	OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT		= 16,
	OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK		= 0xFFFF <<
					OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT,

	OCRDMA_CREATE_QP_REQ_FMR_EN_SHIFT		= 0,
	OCRDMA_CREATE_QP_REQ_FMR_EN_MASK		= Bit(0),
	OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_SHIFT		= 1,
	OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK		= Bit(1),
	OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_SHIFT		= 2,
	OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK		= Bit(2),
	OCRDMA_CREATE_QP_REQ_INB_WREN_SHIFT		= 3,
	OCRDMA_CREATE_QP_REQ_INB_WREN_MASK		= Bit(3),
	OCRDMA_CREATE_QP_REQ_INB_RDEN_SHIFT		= 4,
	OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK		= Bit(4),
	OCRDMA_CREATE_QP_REQ_USE_SRQ_SHIFT		= 5,
	OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK		= Bit(5),
	OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_SHIFT		= 6,
	OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_MASK		= Bit(6),
	OCRDMA_CREATE_QP_REQ_ENABLE_DPP_SHIFT		= 7,
	OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK		= Bit(7),
	OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_SHIFT	= 8,
	OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_MASK		= Bit(8),
	OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT		= 16,
	OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK		= 0xFFFF <<
				OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT,

	OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT		= 0,
	OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK		= 0xFFFF,
	OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT		= 16,
	OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK		= 0xFFFF <<
				OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT,

	OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT		= 0,
	OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK		= 0xFFFF,
	OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT		= 16,
	OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK		= 0xFFFF <<
				OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT,

	OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT		= 0,
	OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK		= 0xFFFF,
	OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT		= 16,
	OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK		= 0xFFFF <<
				OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT,

	OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT		= 0,
	OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK		= 0xFFFF,
	OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT		= 16,
	OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK		= 0xFFFF <<
				OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT,

	OCRDMA_CREATE_QP_REQ_DPP_CQPID_SHIFT		= 0,
	OCRDMA_CREATE_QP_REQ_DPP_CQPID_MASK		= 0xFFFF,
	OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT		= 16,
	OCRDMA_CREATE_QP_REQ_DPP_CREDIT_MASK		= 0xFFFF <<
				OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT
};

enum {
	OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT	= 16,
	OCRDMA_CREATE_QP_RSP_DPP_PAGE_SHIFT	= 1
};

#define MAX_OCRDMA_IRD_PAGES 4

enum ocrdma_qp_flags {
	OCRDMA_QP_MW_BIND	= 1,
	OCRDMA_QP_LKEY0		= (1 << 1),
	OCRDMA_QP_FAST_REG	= (1 << 2),
	OCRDMA_QP_INB_RD	= (1 << 6),
	OCRDMA_QP_INB_WR	= (1 << 7),
};

enum ocrdma_qp_state {
	OCRDMA_QPS_RST		= 0,
	OCRDMA_QPS_INIT		= 1,
	OCRDMA_QPS_RTR		= 2,
	OCRDMA_QPS_RTS		= 3,
	OCRDMA_QPS_SQE		= 4,
	OCRDMA_QPS_SQ_DRAINING	= 5,
	OCRDMA_QPS_ERR		= 6,
	OCRDMA_QPS_SQD		= 7
};

struct ocrdma_create_qp_req {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_hdr req;

	u32 type_pgsz_pdn;
	u32 max_wqe_rqe;
	u32 max_sge_send_write;
	u32 max_sge_recv_flags;
	u32 max_ord_ird;
	u32 num_wq_rq_pages;
	u32 wqe_rqe_size;
	u32 wq_rq_cqid;
	struct ocrdma_pa wq_addr[MAX_OCRDMA_QP_PAGES];
	struct ocrdma_pa rq_addr[MAX_OCRDMA_QP_PAGES];
	u32 dpp_credits_cqid;
	u32 rpir_lkey;
	struct ocrdma_pa ird_addr[MAX_OCRDMA_IRD_PAGES];
};

enum {
	OCRDMA_CREATE_QP_RSP_QP_ID_SHIFT		= 0,
	OCRDMA_CREATE_QP_RSP_QP_ID_MASK			= 0xFFFF,

	OCRDMA_CREATE_QP_RSP_MAX_RQE_SHIFT		= 0,
	OCRDMA_CREATE_QP_RSP_MAX_RQE_MASK		= 0xFFFF,
	OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT		= 16,
	OCRDMA_CREATE_QP_RSP_MAX_WQE_MASK		= 0xFFFF <<
				OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT,

	OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_SHIFT	= 0,
	OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_MASK		= 0xFFFF,
	OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT		= 16,
	OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_MASK		= 0xFFFF <<
				OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT,

	OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT		= 16,
	OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_MASK		= 0xFFFF <<
				OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT,

	OCRDMA_CREATE_QP_RSP_MAX_IRD_SHIFT		= 0,
	OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK		= 0xFFFF,
	OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT		= 16,
	OCRDMA_CREATE_QP_RSP_MAX_ORD_MASK		= 0xFFFF <<
				OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT,

	OCRDMA_CREATE_QP_RSP_RQ_ID_SHIFT		= 0,
	OCRDMA_CREATE_QP_RSP_RQ_ID_MASK			= 0xFFFF,
	OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT		= 16,
	OCRDMA_CREATE_QP_RSP_SQ_ID_MASK			= 0xFFFF <<
				OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT,

	OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK		= Bit(0),
	OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT	= 1,
	OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK	= 0x7FFF <<
				OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT,
	OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT		= 16,
	OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK		= 0xFFFF <<
				OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT,
};

struct ocrdma_create_qp_rsp {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_rsp rsp;

	u32 qp_id;
	u32 max_wqe_rqe;
	u32 max_sge_send_write;
	u32 max_sge_recv;
	u32 max_ord_ird;
	u32 sq_rq_id;
	u32 dpp_response;
};

struct ocrdma_destroy_qp {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_hdr req;
	u32 qp_id;
};

struct ocrdma_destroy_qp_rsp {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_rsp rsp;
};

enum {
	OCRDMA_MODIFY_QP_ID_SHIFT	= 0,
	OCRDMA_MODIFY_QP_ID_MASK	= 0xFFFF,

	OCRDMA_QP_PARA_QPS_VALID	= Bit(0),
	OCRDMA_QP_PARA_SQD_ASYNC_VALID	= Bit(1),
	OCRDMA_QP_PARA_PKEY_VALID	= Bit(2),
	OCRDMA_QP_PARA_QKEY_VALID	= Bit(3),
	OCRDMA_QP_PARA_PMTU_VALID	= Bit(4),
	OCRDMA_QP_PARA_ACK_TO_VALID	= Bit(5),
	OCRDMA_QP_PARA_RETRY_CNT_VALID	= Bit(6),
	OCRDMA_QP_PARA_RRC_VALID	= Bit(7),
	OCRDMA_QP_PARA_RQPSN_VALID	= Bit(8),
	OCRDMA_QP_PARA_MAX_IRD_VALID	= Bit(9),
	OCRDMA_QP_PARA_MAX_ORD_VALID	= Bit(10),
	OCRDMA_QP_PARA_RNT_VALID	= Bit(11),
	OCRDMA_QP_PARA_SQPSN_VALID	= Bit(12),
	OCRDMA_QP_PARA_DST_QPN_VALID	= Bit(13),
	OCRDMA_QP_PARA_MAX_WQE_VALID	= Bit(14),
	OCRDMA_QP_PARA_MAX_RQE_VALID	= Bit(15),
	OCRDMA_QP_PARA_SGE_SEND_VALID	= Bit(16),
	OCRDMA_QP_PARA_SGE_RECV_VALID	= Bit(17),
	OCRDMA_QP_PARA_SGE_WR_VALID	= Bit(18),
	OCRDMA_QP_PARA_INB_RDEN_VALID	= Bit(19),
	OCRDMA_QP_PARA_INB_WREN_VALID	= Bit(20),
	OCRDMA_QP_PARA_FLOW_LBL_VALID	= Bit(21),
	OCRDMA_QP_PARA_BIND_EN_VALID	= Bit(22),
	OCRDMA_QP_PARA_ZLKEY_EN_VALID	= Bit(23),
	OCRDMA_QP_PARA_FMR_EN_VALID	= Bit(24),
	OCRDMA_QP_PARA_INBAT_EN_VALID	= Bit(25),
	OCRDMA_QP_PARA_VLAN_EN_VALID	= Bit(26),

	OCRDMA_MODIFY_QP_FLAGS_RD	= Bit(0),
	OCRDMA_MODIFY_QP_FLAGS_WR	= Bit(1),
	OCRDMA_MODIFY_QP_FLAGS_SEND	= Bit(2),
	OCRDMA_MODIFY_QP_FLAGS_ATOMIC	= Bit(3)
};

enum {
	OCRDMA_QP_PARAMS_SRQ_ID_SHIFT		= 0,
	OCRDMA_QP_PARAMS_SRQ_ID_MASK		= 0xFFFF,

	OCRDMA_QP_PARAMS_MAX_RQE_SHIFT		= 0,
	OCRDMA_QP_PARAMS_MAX_RQE_MASK		= 0xFFFF,
	OCRDMA_QP_PARAMS_MAX_WQE_SHIFT		= 16,
	OCRDMA_QP_PARAMS_MAX_WQE_MASK		= 0xFFFF <<
	    OCRDMA_QP_PARAMS_MAX_WQE_SHIFT,

	OCRDMA_QP_PARAMS_MAX_SGE_WRITE_SHIFT	= 0,
	OCRDMA_QP_PARAMS_MAX_SGE_WRITE_MASK	= 0xFFFF,
	OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT	= 16,
	OCRDMA_QP_PARAMS_MAX_SGE_SEND_MASK	= 0xFFFF <<
					OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT,

	OCRDMA_QP_PARAMS_FLAGS_FMR_EN		= Bit(0),
	OCRDMA_QP_PARAMS_FLAGS_LKEY_0_EN	= Bit(1),
	OCRDMA_QP_PARAMS_FLAGS_BIND_MW_EN	= Bit(2),
	OCRDMA_QP_PARAMS_FLAGS_INBWR_EN		= Bit(3),
	OCRDMA_QP_PARAMS_FLAGS_INBRD_EN		= Bit(4),
	OCRDMA_QP_PARAMS_STATE_SHIFT		= 5,
	OCRDMA_QP_PARAMS_STATE_MASK		= Bit(5) | Bit(6) | Bit(7),
	OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC	= Bit(8),
	OCRDMA_QP_PARAMS_FLAGS_INB_ATEN		= Bit(9),
	OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT	= 16,
	OCRDMA_QP_PARAMS_MAX_SGE_RECV_MASK	= 0xFFFF <<
					OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT,

	OCRDMA_QP_PARAMS_MAX_IRD_SHIFT		= 0,
	OCRDMA_QP_PARAMS_MAX_IRD_MASK		= 0xFFFF,
	OCRDMA_QP_PARAMS_MAX_ORD_SHIFT		= 16,
	OCRDMA_QP_PARAMS_MAX_ORD_MASK		= 0xFFFF <<
					OCRDMA_QP_PARAMS_MAX_ORD_SHIFT,

	OCRDMA_QP_PARAMS_RQ_CQID_SHIFT		= 0,
	OCRDMA_QP_PARAMS_RQ_CQID_MASK		= 0xFFFF,
	OCRDMA_QP_PARAMS_WQ_CQID_SHIFT		= 16,
	OCRDMA_QP_PARAMS_WQ_CQID_MASK		= 0xFFFF <<
					OCRDMA_QP_PARAMS_WQ_CQID_SHIFT,

	OCRDMA_QP_PARAMS_RQ_PSN_SHIFT		= 0,
	OCRDMA_QP_PARAMS_RQ_PSN_MASK		= 0xFFFFFF,
	OCRDMA_QP_PARAMS_HOP_LMT_SHIFT		= 24,
	OCRDMA_QP_PARAMS_HOP_LMT_MASK		= 0xFF <<
					OCRDMA_QP_PARAMS_HOP_LMT_SHIFT,

	OCRDMA_QP_PARAMS_SQ_PSN_SHIFT		= 0,
	OCRDMA_QP_PARAMS_SQ_PSN_MASK		= 0xFFFFFF,
	OCRDMA_QP_PARAMS_TCLASS_SHIFT		= 24,
	OCRDMA_QP_PARAMS_TCLASS_MASK		= 0xFF <<
					OCRDMA_QP_PARAMS_TCLASS_SHIFT,

	OCRDMA_QP_PARAMS_DEST_QPN_SHIFT		= 0,
	OCRDMA_QP_PARAMS_DEST_QPN_MASK		= 0xFFFFFF,
	OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT	= 24,
	OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK	= 0x7 <<
					OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT,
	OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT	= 27,
	OCRDMA_QP_PARAMS_ACK_TIMEOUT_MASK	= 0x1F <<
					OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT,

	OCRDMA_QP_PARAMS_PKEY_IDNEX_SHIFT	= 0,
	OCRDMA_QP_PARAMS_PKEY_INDEX_MASK	= 0xFFFF,
	OCRDMA_QP_PARAMS_PATH_MTU_SHIFT		= 18,
	OCRDMA_QP_PARAMS_PATH_MTU_MASK		= 0x3FFF <<
					OCRDMA_QP_PARAMS_PATH_MTU_SHIFT,

	OCRDMA_QP_PARAMS_FLOW_LABEL_SHIFT	= 0,
	OCRDMA_QP_PARAMS_FLOW_LABEL_MASK	= 0xFFFFF,
	OCRDMA_QP_PARAMS_SL_SHIFT		= 20,
	OCRDMA_QP_PARAMS_SL_MASK		= 0xF <<
					OCRDMA_QP_PARAMS_SL_SHIFT,
	OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT	= 24,
	OCRDMA_QP_PARAMS_RETRY_CNT_MASK		= 0x7 <<
					OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT,
	OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT	= 27,
	OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK	= 0x1F <<
					OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT,

	OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_SHIFT	= 0,
	OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_MASK	= 0xFFFF,
	OCRDMA_QP_PARAMS_VLAN_SHIFT		= 16,
	OCRDMA_QP_PARAMS_VLAN_MASK		= 0xFFFF <<
					OCRDMA_QP_PARAMS_VLAN_SHIFT
};

struct ocrdma_qp_params {
	u32 id;
	u32 max_wqe_rqe;
	u32 max_sge_send_write;
	u32 max_sge_recv_flags;
	u32 max_ord_ird;
	u32 wq_rq_cqid;
	u32 hop_lmt_rq_psn;
	u32 tclass_sq_psn;
	u32 ack_to_rnr_rtc_dest_qpn;
	u32 path_mtu_pkey_indx;
	u32 rnt_rc_sl_fl;
	u8 sgid[16];
	u8 dgid[16];
	u32 dmac_b0_to_b3;
	u32 vlan_dmac_b4_to_b5;
	u32 qkey;
};


struct ocrdma_modify_qp {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_hdr req;

	struct ocrdma_qp_params params;
	u32 flags;
	u32 rdma_flags;
	u32 num_outstanding_atomic_rd;
};

enum {
	OCRDMA_MODIFY_QP_RSP_MAX_RQE_SHIFT	= 0,
	OCRDMA_MODIFY_QP_RSP_MAX_RQE_MASK	= 0xFFFF,
	OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT	= 16,
	OCRDMA_MODIFY_QP_RSP_MAX_WQE_MASK	= 0xFFFF <<
					OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT,

	OCRDMA_MODIFY_QP_RSP_MAX_IRD_SHIFT	= 0,
	OCRDMA_MODIFY_QP_RSP_MAX_IRD_MASK	= 0xFFFF,
	OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT	= 16,
	OCRDMA_MODIFY_QP_RSP_MAX_ORD_MASK	= 0xFFFF <<
					OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT
};
struct ocrdma_modify_qp_rsp {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_rsp rsp;

	u32 max_wqe_rqe;
	u32 max_ord_ird;
};

struct ocrdma_query_qp {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_hdr req;

#define OCRDMA_QUERY_UP_QP_ID_SHIFT 0
#define OCRDMA_QUERY_UP_QP_ID_MASK   0xFFFFFF
	u32 qp_id;
};

struct ocrdma_query_qp_rsp {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_rsp rsp;
	struct ocrdma_qp_params params;
};

enum {
	OCRDMA_CREATE_SRQ_PD_ID_SHIFT		= 0,
	OCRDMA_CREATE_SRQ_PD_ID_MASK		= 0xFFFF,
	OCRDMA_CREATE_SRQ_PG_SZ_SHIFT		= 16,
	OCRDMA_CREATE_SRQ_PG_SZ_MASK		= 0x3 <<
					OCRDMA_CREATE_SRQ_PG_SZ_SHIFT,

	OCRDMA_CREATE_SRQ_MAX_RQE_SHIFT		= 0,
	OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT	= 16,
	OCRDMA_CREATE_SRQ_MAX_SGE_RECV_MASK	= 0xFFFF <<
					OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT,

	OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT	= 0,
	OCRDMA_CREATE_SRQ_RQE_SIZE_MASK		= 0xFFFF,
	OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT	= 16,
	OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_MASK	= 0xFFFF <<
					OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT
};

struct ocrdma_create_srq {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_hdr req;

	u32 pgsz_pdid;
	u32 max_sge_rqe;
	u32 pages_rqe_sz;
	struct ocrdma_pa rq_addr[MAX_OCRDMA_SRQ_PAGES];
};

enum {
	OCRDMA_CREATE_SRQ_RSP_SRQ_ID_SHIFT			= 0,
	OCRDMA_CREATE_SRQ_RSP_SRQ_ID_MASK			= 0xFFFFFF,

	OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT		= 0,
	OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK		= 0xFFFF,
	OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT	= 16,
	OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK	= 0xFFFF <<
			OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT
};

struct ocrdma_create_srq_rsp {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_rsp rsp;

	u32 id;
	u32 max_sge_rqe_allocated;
};

enum {
	OCRDMA_MODIFY_SRQ_ID_SHIFT	= 0,
	OCRDMA_MODIFY_SRQ_ID_MASK	= 0xFFFFFF,

	OCRDMA_MODIFY_SRQ_MAX_RQE_SHIFT	= 0,
	OCRDMA_MODIFY_SRQ_MAX_RQE_MASK	= 0xFFFF,
	OCRDMA_MODIFY_SRQ_LIMIT_SHIFT	= 16,
	OCRDMA_MODIFY_SRQ__LIMIT_MASK	= 0xFFFF <<
					OCRDMA_MODIFY_SRQ_LIMIT_SHIFT
};

struct ocrdma_modify_srq {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_rsp rep;

	u32 id;
	u32 limit_max_rqe;
};

enum {
	OCRDMA_QUERY_SRQ_ID_SHIFT	= 0,
	OCRDMA_QUERY_SRQ_ID_MASK	= 0xFFFFFF
};

struct ocrdma_query_srq {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_rsp req;

	u32 id;
};

enum {
	OCRDMA_QUERY_SRQ_RSP_PD_ID_SHIFT	= 0,
	OCRDMA_QUERY_SRQ_RSP_PD_ID_MASK		= 0xFFFF,
	OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT	= 16,
	OCRDMA_QUERY_SRQ_RSP_MAX_RQE_MASK	= 0xFFFF <<
					OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT,

	OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_SHIFT	= 0,
	OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK	= 0xFFFF,
	OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT	= 16,
	OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_MASK	= 0xFFFF <<
					OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT
};

struct ocrdma_query_srq_rsp {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_rsp req;

	u32 max_rqe_pdid;
	u32 srq_lmt_max_sge;
};

enum {
	OCRDMA_DESTROY_SRQ_ID_SHIFT	= 0,
	OCRDMA_DESTROY_SRQ_ID_MASK	= 0xFFFFFF
};

struct ocrdma_destroy_srq {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_rsp req;

	u32 id;
};

enum {
	OCRDMA_ALLOC_PD_ENABLE_DPP	= BIT(16),
	OCRDMA_PD_MAX_DPP_ENABLED_QP	= 8,
	OCRDMA_DPP_PAGE_SIZE		= 4096
};

struct ocrdma_alloc_pd {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_hdr req;
	u32 enable_dpp_rsvd;
};

enum {
	OCRDMA_ALLOC_PD_RSP_DPP			= Bit(16),
	OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT	= 20,
	OCRDMA_ALLOC_PD_RSP_PDID_MASK		= 0xFFFF,
};

struct ocrdma_alloc_pd_rsp {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_rsp rsp;
	u32 dpp_page_pdid;
};

struct ocrdma_dealloc_pd {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_hdr req;
	u32 id;
};

struct ocrdma_dealloc_pd_rsp {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_rsp rsp;
};

enum {
	OCRDMA_ADDR_CHECK_ENABLE	= 1,
	OCRDMA_ADDR_CHECK_DISABLE	= 0
};

enum {
	OCRDMA_ALLOC_LKEY_PD_ID_SHIFT		= 0,
	OCRDMA_ALLOC_LKEY_PD_ID_MASK		= 0xFFFF,

	OCRDMA_ALLOC_LKEY_ADDR_CHECK_SHIFT	= 0,
	OCRDMA_ALLOC_LKEY_ADDR_CHECK_MASK	= Bit(0),
	OCRDMA_ALLOC_LKEY_FMR_SHIFT		= 1,
	OCRDMA_ALLOC_LKEY_FMR_MASK		= Bit(1),
	OCRDMA_ALLOC_LKEY_REMOTE_INV_SHIFT	= 2,
	OCRDMA_ALLOC_LKEY_REMOTE_INV_MASK	= Bit(2),
	OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT	= 3,
	OCRDMA_ALLOC_LKEY_REMOTE_WR_MASK	= Bit(3),
	OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT	= 4,
	OCRDMA_ALLOC_LKEY_REMOTE_RD_MASK	= Bit(4),
	OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT	= 5,
	OCRDMA_ALLOC_LKEY_LOCAL_WR_MASK		= Bit(5),
	OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_MASK	= Bit(6),
	OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT	= 6,
	OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT	= 16,
	OCRDMA_ALLOC_LKEY_PBL_SIZE_MASK		= 0xFFFF <<
						OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT
};

struct ocrdma_alloc_lkey {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_hdr req;

	u32 pdid;
	u32 pbl_sz_flags;
};

struct ocrdma_alloc_lkey_rsp {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_rsp rsp;

	u32 lrkey;
	u32 num_pbl_rsvd;
};

struct ocrdma_dealloc_lkey {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_hdr req;

	u32 lkey;
	u32 rsvd_frmr;
};

struct ocrdma_dealloc_lkey_rsp {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_rsp rsp;
};

#define MAX_OCRDMA_NSMR_PBL    (u32)22
#define MAX_OCRDMA_PBL_SIZE     65536
#define MAX_OCRDMA_PBL_PER_LKEY	32767

enum {
	OCRDMA_REG_NSMR_LRKEY_INDEX_SHIFT	= 0,
	OCRDMA_REG_NSMR_LRKEY_INDEX_MASK	= 0xFFFFFF,
	OCRDMA_REG_NSMR_LRKEY_SHIFT		= 24,
	OCRDMA_REG_NSMR_LRKEY_MASK		= 0xFF <<
					OCRDMA_REG_NSMR_LRKEY_SHIFT,

	OCRDMA_REG_NSMR_PD_ID_SHIFT		= 0,
	OCRDMA_REG_NSMR_PD_ID_MASK		= 0xFFFF,
	OCRDMA_REG_NSMR_NUM_PBL_SHIFT		= 16,
	OCRDMA_REG_NSMR_NUM_PBL_MASK		= 0xFFFF <<
					OCRDMA_REG_NSMR_NUM_PBL_SHIFT,

	OCRDMA_REG_NSMR_PBE_SIZE_SHIFT		= 0,
	OCRDMA_REG_NSMR_PBE_SIZE_MASK		= 0xFFFF,
	OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT	= 16,
	OCRDMA_REG_NSMR_HPAGE_SIZE_MASK		= 0xFF <<
					OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT,
	OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT	= 24,
	OCRDMA_REG_NSMR_BIND_MEMWIN_MASK	= Bit(24),
	OCRDMA_REG_NSMR_ZB_SHIFT		= 25,
	OCRDMA_REG_NSMR_ZB_SHIFT_MASK		= Bit(25),
	OCRDMA_REG_NSMR_REMOTE_INV_SHIFT	= 26,
	OCRDMA_REG_NSMR_REMOTE_INV_MASK		= Bit(26),
	OCRDMA_REG_NSMR_REMOTE_WR_SHIFT		= 27,
	OCRDMA_REG_NSMR_REMOTE_WR_MASK		= Bit(27),
	OCRDMA_REG_NSMR_REMOTE_RD_SHIFT		= 28,
	OCRDMA_REG_NSMR_REMOTE_RD_MASK		= Bit(28),
	OCRDMA_REG_NSMR_LOCAL_WR_SHIFT		= 29,
	OCRDMA_REG_NSMR_LOCAL_WR_MASK		= Bit(29),
	OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT	= 30,
	OCRDMA_REG_NSMR_REMOTE_ATOMIC_MASK	= Bit(30),
	OCRDMA_REG_NSMR_LAST_SHIFT		= 31,
	OCRDMA_REG_NSMR_LAST_MASK		= Bit(31)
};

struct ocrdma_reg_nsmr {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_hdr cmd;

	u32 fr_mr;
	u32 num_pbl_pdid;
	u32 flags_hpage_pbe_sz;
	u32 totlen_low;
	u32 totlen_high;
	u32 fbo_low;
	u32 fbo_high;
	u32 va_loaddr;
	u32 va_hiaddr;
	struct ocrdma_pa pbl[MAX_OCRDMA_NSMR_PBL];
};

enum {
	OCRDMA_REG_NSMR_CONT_PBL_SHIFT		= 0,
	OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK	= 0xFFFF,
	OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT	= 16,
	OCRDMA_REG_NSMR_CONT_NUM_PBL_MASK	= 0xFFFF <<
					OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT,

	OCRDMA_REG_NSMR_CONT_LAST_SHIFT		= 31,
	OCRDMA_REG_NSMR_CONT_LAST_MASK		= Bit(31)
};

struct ocrdma_reg_nsmr_cont {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_hdr cmd;

	u32 lrkey;
	u32 num_pbl_offset;
	u32 last;

	struct ocrdma_pa pbl[MAX_OCRDMA_NSMR_PBL];
};

struct ocrdma_pbe {
	u32 pa_hi;
	u32 pa_lo;
};

enum {
	OCRDMA_REG_NSMR_RSP_NUM_PBL_SHIFT	= 16,
	OCRDMA_REG_NSMR_RSP_NUM_PBL_MASK	= 0xFFFF0000
};
struct ocrdma_reg_nsmr_rsp {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_rsp rsp;

	u32 lrkey;
	u32 num_pbl;
};

enum {
	OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_SHIFT	= 0,
	OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_MASK	= 0xFFFFFF,
	OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT		= 24,
	OCRDMA_REG_NSMR_CONT_RSP_LRKEY_MASK		= 0xFF <<
					OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT,

	OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT		= 16,
	OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_MASK		= 0xFFFF <<
					OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT
};

struct ocrdma_reg_nsmr_cont_rsp {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_rsp rsp;

	u32 lrkey_key_index;
	u32 num_pbl;
};

enum {
	OCRDMA_ALLOC_MW_PD_ID_SHIFT	= 0,
	OCRDMA_ALLOC_MW_PD_ID_MASK	= 0xFFFF
};

struct ocrdma_alloc_mw {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_hdr req;

	u32 pdid;
};

enum {
	OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_SHIFT	= 0,
	OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_MASK	= 0xFFFFFF
};

struct ocrdma_alloc_mw_rsp {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_rsp rsp;

	u32 lrkey_index;
};

struct ocrdma_attach_mcast {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_hdr req;
	u32 qp_id;
	u8 mgid[16];
	u32 mac_b0_to_b3;
	u32 vlan_mac_b4_to_b5;
};

struct ocrdma_attach_mcast_rsp {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_rsp rsp;
};

struct ocrdma_detach_mcast {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_hdr req;
	u32 qp_id;
	u8 mgid[16];
	u32 mac_b0_to_b3;
	u32 vlan_mac_b4_to_b5;
};

struct ocrdma_detach_mcast_rsp {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_rsp rsp;
};

enum {
	OCRDMA_CREATE_AH_NUM_PAGES_SHIFT	= 19,
	OCRDMA_CREATE_AH_NUM_PAGES_MASK		= 0xF <<
					OCRDMA_CREATE_AH_NUM_PAGES_SHIFT,

	OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT	= 16,
	OCRDMA_CREATE_AH_PAGE_SIZE_MASK		= 0x7 <<
					OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT,

	OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT	= 23,
	OCRDMA_CREATE_AH_ENTRY_SIZE_MASK	= 0x1FF <<
					OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT,
};

#define OCRDMA_AH_TBL_PAGES 8

struct ocrdma_create_ah_tbl {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_hdr req;

	u32 ah_conf;
	struct ocrdma_pa tbl_addr[8];
};

struct ocrdma_create_ah_tbl_rsp {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_rsp rsp;
	u32 ahid;
};

struct ocrdma_delete_ah_tbl {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_hdr req;
	u32 ahid;
};

struct ocrdma_delete_ah_tbl_rsp {
	struct ocrdma_mqe_hdr hdr;
	struct ocrdma_mbx_rsp rsp;
};

enum {
	OCRDMA_EQE_VALID_SHIFT		= 0,
	OCRDMA_EQE_VALID_MASK		= Bit(0),
	OCRDMA_EQE_FOR_CQE_MASK		= 0xFFFE,
	OCRDMA_EQE_RESOURCE_ID_SHIFT	= 16,
	OCRDMA_EQE_RESOURCE_ID_MASK	= 0xFFFF <<
				OCRDMA_EQE_RESOURCE_ID_SHIFT,
};

struct ocrdma_eqe {
	u32 id_valid;
};

enum OCRDMA_CQE_STATUS {
	OCRDMA_CQE_SUCCESS = 0,
	OCRDMA_CQE_LOC_LEN_ERR,
	OCRDMA_CQE_LOC_QP_OP_ERR,
	OCRDMA_CQE_LOC_EEC_OP_ERR,
	OCRDMA_CQE_LOC_PROT_ERR,
	OCRDMA_CQE_WR_FLUSH_ERR,
	OCRDMA_CQE_MW_BIND_ERR,
	OCRDMA_CQE_BAD_RESP_ERR,
	OCRDMA_CQE_LOC_ACCESS_ERR,
	OCRDMA_CQE_REM_INV_REQ_ERR,
	OCRDMA_CQE_REM_ACCESS_ERR,
	OCRDMA_CQE_REM_OP_ERR,
	OCRDMA_CQE_RETRY_EXC_ERR,
	OCRDMA_CQE_RNR_RETRY_EXC_ERR,
	OCRDMA_CQE_LOC_RDD_VIOL_ERR,
	OCRDMA_CQE_REM_INV_RD_REQ_ERR,
	OCRDMA_CQE_REM_ABORT_ERR,
	OCRDMA_CQE_INV_EECN_ERR,
	OCRDMA_CQE_INV_EEC_STATE_ERR,
	OCRDMA_CQE_FATAL_ERR,
	OCRDMA_CQE_RESP_TIMEOUT_ERR,
	OCRDMA_CQE_GENERAL_ERR
};

enum {
	/* w0 */
	OCRDMA_CQE_WQEIDX_SHIFT		= 0,
	OCRDMA_CQE_WQEIDX_MASK		= 0xFFFF,

	/* w1 */
	OCRDMA_CQE_UD_XFER_LEN_SHIFT	= 16,
	OCRDMA_CQE_PKEY_SHIFT		= 0,
	OCRDMA_CQE_PKEY_MASK		= 0xFFFF,

	/* w2 */
	OCRDMA_CQE_QPN_SHIFT		= 0,
	OCRDMA_CQE_QPN_MASK		= 0x0000FFFF,

	OCRDMA_CQE_BUFTAG_SHIFT		= 16,
	OCRDMA_CQE_BUFTAG_MASK		= 0xFFFF << OCRDMA_CQE_BUFTAG_SHIFT,

	/* w3 */
	OCRDMA_CQE_UD_STATUS_SHIFT	= 24,
	OCRDMA_CQE_UD_STATUS_MASK	= 0x7 << OCRDMA_CQE_UD_STATUS_SHIFT,
	OCRDMA_CQE_STATUS_SHIFT		= 16,
	OCRDMA_CQE_STATUS_MASK		= 0xFF << OCRDMA_CQE_STATUS_SHIFT,
	OCRDMA_CQE_VALID		= Bit(31),
	OCRDMA_CQE_INVALIDATE		= Bit(30),
	OCRDMA_CQE_QTYPE		= Bit(29),
	OCRDMA_CQE_IMM			= Bit(28),
	OCRDMA_CQE_WRITE_IMM		= Bit(27),
	OCRDMA_CQE_QTYPE_SQ		= 0,
	OCRDMA_CQE_QTYPE_RQ		= 1,
	OCRDMA_CQE_SRCQP_MASK		= 0xFFFFFF
};

struct ocrdma_cqe {
	union {
		/* w0 to w2 */
		struct {
			u32 wqeidx;
			u32 bytes_xfered;
			u32 qpn;
		} wq;
		struct {
			u32 lkey_immdt;
			u32 rxlen;
			u32 buftag_qpn;
		} rq;
		struct {
			u32 lkey_immdt;
			u32 rxlen_pkey;
			u32 buftag_qpn;
		} ud;
		struct {
			u32 word_0;
			u32 word_1;
			u32 qpn;
		} cmn;
	};
	u32 flags_status_srcqpn;	/* w3 */
};

struct ocrdma_sge {
	u32 addr_hi;
	u32 addr_lo;
	u32 lrkey;
	u32 len;
};

enum {
	OCRDMA_FLAG_SIG		= 0x1,
	OCRDMA_FLAG_INV		= 0x2,
	OCRDMA_FLAG_FENCE_L	= 0x4,
	OCRDMA_FLAG_FENCE_R	= 0x8,
	OCRDMA_FLAG_SOLICIT	= 0x10,
	OCRDMA_FLAG_IMM		= 0x20,

	/* Stag flags */
	OCRDMA_LKEY_FLAG_LOCAL_WR	= 0x1,
	OCRDMA_LKEY_FLAG_REMOTE_RD	= 0x2,
	OCRDMA_LKEY_FLAG_REMOTE_WR	= 0x4,
	OCRDMA_LKEY_FLAG_VATO		= 0x8,
};

enum OCRDMA_WQE_OPCODE {
	OCRDMA_WRITE		= 0x06,
	OCRDMA_READ		= 0x0C,
	OCRDMA_RESV0		= 0x02,
	OCRDMA_SEND		= 0x00,
	OCRDMA_CMP_SWP		= 0x14,
	OCRDMA_BIND_MW		= 0x10,
	OCRDMA_FR_MR            = 0x11,
	OCRDMA_RESV1		= 0x0A,
	OCRDMA_LKEY_INV		= 0x15,
	OCRDMA_FETCH_ADD	= 0x13,
	OCRDMA_POST_RQ		= 0x12
};

enum {
	OCRDMA_TYPE_INLINE	= 0x0,
	OCRDMA_TYPE_LKEY	= 0x1,
};

enum {
	OCRDMA_WQE_OPCODE_SHIFT		= 0,
	OCRDMA_WQE_OPCODE_MASK		= 0x0000001F,
	OCRDMA_WQE_FLAGS_SHIFT		= 5,
	OCRDMA_WQE_TYPE_SHIFT		= 16,
	OCRDMA_WQE_TYPE_MASK		= 0x00030000,
	OCRDMA_WQE_SIZE_SHIFT		= 18,
	OCRDMA_WQE_SIZE_MASK		= 0xFF,
	OCRDMA_WQE_NXT_WQE_SIZE_SHIFT	= 25,

	OCRDMA_WQE_LKEY_FLAGS_SHIFT	= 0,
	OCRDMA_WQE_LKEY_FLAGS_MASK	= 0xF
};

/* header WQE for all the SQ and RQ operations */
struct ocrdma_hdr_wqe {
	u32 cw;
	union {
		u32 rsvd_tag;
		u32 rsvd_lkey_flags;
	};
	union {
		u32 immdt;
		u32 lkey;
	};
	u32 total_len;
};

struct ocrdma_ewqe_ud_hdr {
	u32 rsvd_dest_qpn;
	u32 qkey;
	u32 rsvd_ahid;
	u32 rsvd;
};

/* extended wqe followed by hdr_wqe for Fast Memory register */
struct ocrdma_ewqe_fr {
	u32 va_hi;
	u32 va_lo;
	u32 fbo_hi;
	u32 fbo_lo;
	u32 size_sge;
	u32 num_sges;
	u32 rsvd;
	u32 rsvd2;
};

struct ocrdma_eth_basic {
	u8 dmac[6];
	u8 smac[6];
	__be16 eth_type;
} __packed;

struct ocrdma_eth_vlan {
	u8 dmac[6];
	u8 smac[6];
	__be16 eth_type;
	__be16 vlan_tag;
#define OCRDMA_ROCE_ETH_TYPE 0x8915
	__be16 roce_eth_type;
} __packed;

struct ocrdma_grh {
	__be32	tclass_flow;
	__be32	pdid_hoplimit;
	u8	sgid[16];
	u8	dgid[16];
	u16	rsvd;
} __packed;

#define OCRDMA_AV_VALID		Bit(0)
#define OCRDMA_AV_VLAN_VALID	Bit(1)

struct ocrdma_av {
	struct ocrdma_eth_vlan eth_hdr;
	struct ocrdma_grh grh;
	u32 valid;
} __packed;

#endif				/* __OCRDMA_SLI_H__ */
OpenPOWER on IntegriCloud